--- /dev/null
+// ----------------------------------------------------------------------------\r
+// ATMEL Microcontroller Software Support - ROUSSET -\r
+// ----------------------------------------------------------------------------\r
+// The software is delivered "AS IS" without warranty or condition of any\r
+// kind, either express, implied or statutory. This includes without\r
+// limitation any warranty or condition with respect to merchantability or\r
+// fitness for any particular purpose, or against the infringements of\r
+// intellectual property rights of others.\r
+// ----------------------------------------------------------------------------\r
+// File Name : AT91R40008.h\r
+// Object : AT91R40008 definitions\r
+// Generated : AT91 SW Application Group 02/19/2003 (11:13:31)\r
+// \r
+// CVS Reference : /AT91R40008.pl/1.3/Tue Nov 12 16:01:52 2002//\r
+// CVS Reference : /AIC_1246F.pl/1.4/Mon Nov 04 17:51:00 2002//\r
+// CVS Reference : /WD_1241B.pl/1.1/Mon Nov 04 17:51:00 2002//\r
+// CVS Reference : /PS_x40.pl/1.2/Tue Nov 12 16:01:52 2002//\r
+// CVS Reference : /PIO_1321C.pl/1.5/Tue Oct 29 15:50:24 2002//\r
+// CVS Reference : /TC_1243B.pl/1.4/Tue Nov 05 12:43:10 2002//\r
+// CVS Reference : /PDC_1363D.pl/1.3/Wed Oct 23 14:49:48 2002//\r
+// CVS Reference : /US_1242E.pl/1.5/Thu Nov 21 13:37:56 2002//\r
+// CVS Reference : /SF_x40.pl/1.1/Tue Nov 12 13:27:20 2002//\r
+// CVS Reference : /EBI_x40.pl/1.5/Wed Feb 19 09:25:22 2003//\r
+// ----------------------------------------------------------------------------\r
+\r
+#ifndef AT91R40008_H\r
+#define AT91R40008_H\r
+\r
+/* AT91 Register type */\r
+typedef volatile unsigned int AT91_REG; // Hardware register definition\r
+typedef volatile unsigned int at91_reg;\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller\r
+// *****************************************************************************\r
+typedef struct _AT91S_AIC {\r
+ AT91_REG AIC_SMR[32]; // Source Mode egister\r
+ AT91_REG AIC_SVR[32]; // Source Vector egister\r
+ AT91_REG AIC_IVR; // IRQ Vector Register\r
+ AT91_REG AIC_FVR; // FIQ Vector Register\r
+ AT91_REG AIC_ISR; // Interrupt Status Register\r
+ AT91_REG AIC_IPR; // Interrupt Pending Register\r
+ AT91_REG AIC_IMR; // Interrupt Mask Register\r
+ AT91_REG AIC_CISR; // Core Interrupt Status Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG AIC_IECR; // Interrupt Enable Command Register\r
+ AT91_REG AIC_IDCR; // Interrupt Disable Command egister\r
+ AT91_REG AIC_ICCR; // Interrupt Clear Command Register\r
+ AT91_REG AIC_ISCR; // Interrupt Set Command Register\r
+ AT91_REG AIC_EOICR; // End of Interrupt Command Register\r
+ AT91_REG AIC_SPU; // Spurious Vector Register\r
+} AT91S_AIC, *AT91PS_AIC;\r
+\r
+// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- \r
+#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level\r
+#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level\r
+#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level\r
+#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type\r
+#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive\r
+#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered\r
+#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive\r
+#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered\r
+// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- \r
+#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status\r
+#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Watchdog Timer Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_WD {\r
+ AT91_REG WD_OMR; // Overflow Mode Register\r
+ AT91_REG WD_CMR; // Clock Mode Register\r
+ AT91_REG WD_CR; // Control Register\r
+ AT91_REG WD_SR; // Status Register\r
+} AT91S_WD, *AT91PS_WD;\r
+\r
+// -------- WD_OMR : (WD Offset: 0x0) Overflow Mode Register -------- \r
+#define AT91C_WD_WDEN ((unsigned int) 0x1 << 0) // (WD) Watchdog Enable\r
+#define AT91C_WD_RSTEN ((unsigned int) 0x1 << 1) // (WD) Reset Enable\r
+#define AT91C_WD_IRQEN ((unsigned int) 0x1 << 2) // (WD) Interrupt Enable\r
+#define AT91C_WD_EXTEN ((unsigned int) 0x1 << 3) // (WD) External Signal Enable\r
+#define AT91C_WD_OKEY ((unsigned int) 0xFFF << 4) // (WD) Watchdog Enable\r
+// -------- WD_CMR : (WD Offset: 0x4) Clock Mode Register -------- \r
+#define AT91C_WD_WDCLKS ((unsigned int) 0x3 << 0) // (WD) Clock Selection\r
+#define AT91C_WD_WDCLKS_MCK32 ((unsigned int) 0x0) // (WD) Master Clock divided by 32\r
+#define AT91C_WD_WDCLKS_MCK128 ((unsigned int) 0x1) // (WD) Master Clock divided by 128\r
+#define AT91C_WD_WDCLKS_MCK1024 ((unsigned int) 0x2) // (WD) Master Clock divided by 1024\r
+#define AT91C_WD_WDCLKS_MCK4096 ((unsigned int) 0x3) // (WD) Master Clock divided by 4096\r
+#define AT91C_WD_HPCV ((unsigned int) 0xF << 2) // (WD) High Pre-load Counter Value\r
+#define AT91C_WD_CKEY ((unsigned int) 0x1FF << 7) // (WD) Clock Access Key\r
+// -------- WD_CR : (WD Offset: 0x8) Control Register -------- \r
+#define AT91C_WD_RSTKEY ((unsigned int) 0xFFFF << 0) // (WD) Restart Key\r
+// -------- WD_SR : (WD Offset: 0xc) Status Register -------- \r
+#define AT91C_WD_WDOVF ((unsigned int) 0x1 << 0) // (WD) Watchdog Overflow\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Power Saving Controler\r
+// *****************************************************************************\r
+typedef struct _AT91S_PS {\r
+ AT91_REG PS_CR; // Control Register\r
+ AT91_REG PS_PCER; // Peripheral Clock Enable Register\r
+ AT91_REG PS_PCDR; // Peripheral Clock Disable Register\r
+ AT91_REG PS_PCSR; // Peripheral Clock Status Register\r
+} AT91S_PS, *AT91PS_PS;\r
+\r
+// -------- PS_PCER : (PS Offset: 0x4) Peripheral Clock Enable Register -------- \r
+#define AT91C_PS_US0 ((unsigned int) 0x1 << 2) // (PS) Usart 0 Clock\r
+#define AT91C_PS_US1 ((unsigned int) 0x1 << 3) // (PS) Usart 1 Clock\r
+#define AT91C_PS_TC0 ((unsigned int) 0x1 << 4) // (PS) Timer Counter 0 Clock\r
+#define AT91C_PS_TC1 ((unsigned int) 0x1 << 5) // (PS) Timer Counter 1 Clock\r
+#define AT91C_PS_TC2 ((unsigned int) 0x1 << 6) // (PS) Timer Counter 2 Clock\r
+#define AT91C_PS_PIO ((unsigned int) 0x1 << 8) // (PS) PIO Clock\r
+// -------- PS_PCDR : (PS Offset: 0x8) Peripheral Clock Disable Register -------- \r
+// -------- PS_PCSR : (PS Offset: 0xc) Peripheral Clock Satus Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Parallel Input Output Controler\r
+// *****************************************************************************\r
+typedef struct _AT91S_PIO {\r
+ AT91_REG PIO_PER; // PIO Enable Register\r
+ AT91_REG PIO_PDR; // PIO Disable Register\r
+ AT91_REG PIO_PSR; // PIO Status Register\r
+ AT91_REG Reserved0[1]; // \r
+ AT91_REG PIO_OER; // Output Enable Register\r
+ AT91_REG PIO_ODR; // Output Disable Registerr\r
+ AT91_REG PIO_OSR; // Output Status Register\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG PIO_IFER; // Input Filter Enable Register\r
+ AT91_REG PIO_IFDR; // Input Filter Disable Register\r
+ AT91_REG PIO_IFSR; // Input Filter Status Register\r
+ AT91_REG Reserved2[1]; // \r
+ AT91_REG PIO_SODR; // Set Output Data Register\r
+ AT91_REG PIO_CODR; // Clear Output Data Register\r
+ AT91_REG PIO_ODSR; // Output Data Status Register\r
+ AT91_REG PIO_PDSR; // Pin Data Status Register\r
+ AT91_REG PIO_IER; // Interrupt Enable Register\r
+ AT91_REG PIO_IDR; // Interrupt Disable Register\r
+ AT91_REG PIO_IMR; // Interrupt Mask Register\r
+ AT91_REG PIO_ISR; // Interrupt Status Register\r
+ AT91_REG PIO_MDER; // Multi-driver Enable Register\r
+ AT91_REG PIO_MDDR; // Multi-driver Disable Register\r
+ AT91_REG PIO_MDSR; // Multi-driver Status Register\r
+} AT91S_PIO, *AT91PS_PIO;\r
+\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_TC {\r
+ AT91_REG TC_CCR; // Channel Control Register\r
+ AT91_REG TC_CMR; // Channel Mode Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG TC_CV; // Counter Value\r
+ AT91_REG TC_RA; // Register A\r
+ AT91_REG TC_RB; // Register B\r
+ AT91_REG TC_RC; // Register C\r
+ AT91_REG TC_SR; // Status Register\r
+ AT91_REG TC_IER; // Interrupt Enable Register\r
+ AT91_REG TC_IDR; // Interrupt Disable Register\r
+ AT91_REG TC_IMR; // Interrupt Mask Register\r
+} AT91S_TC, *AT91PS_TC;\r
+\r
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- \r
+#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command\r
+#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command\r
+#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command\r
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- \r
+#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare\r
+#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare\r
+#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection\r
+#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None\r
+#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge\r
+#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge\r
+#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge\r
+#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection\r
+#define AT91C_TC_EEVT_NONE ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input\r
+#define AT91C_TC_EEVT_RISING ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output\r
+#define AT91C_TC_EEVT_FALLING ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output\r
+#define AT91C_TC_EEVT_BOTH ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output\r
+#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable\r
+#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection\r
+#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare\r
+#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x1 << 13) // (TC) UP mode with automatic trigger on RC Compare\r
+#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x2 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare\r
+#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare\r
+#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable\r
+#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) \r
+#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA\r
+#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none\r
+#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set\r
+#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear\r
+#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle\r
+#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA\r
+#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none\r
+#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set\r
+#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear\r
+#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle\r
+#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA\r
+#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none\r
+#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set\r
+#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear\r
+#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle\r
+#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA\r
+#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none\r
+#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set\r
+#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear\r
+#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle\r
+#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB\r
+#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none\r
+#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set\r
+#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear\r
+#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle\r
+#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB\r
+#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none\r
+#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set\r
+#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear\r
+#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle\r
+#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB\r
+#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none\r
+#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set\r
+#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear\r
+#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle\r
+#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB\r
+#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none\r
+#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set\r
+#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear\r
+#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle\r
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- \r
+#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow\r
+#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun\r
+#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare\r
+#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare\r
+#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare\r
+#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading\r
+#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading\r
+#define AT91C_TC_ETRCS ((unsigned int) 0x1 << 7) // (TC) External Trigger\r
+#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 16) // (TC) Clock Enabling\r
+#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror\r
+#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror\r
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- \r
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- \r
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Timer Counter Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_TCB {\r
+ AT91S_TC TCB_TC0; // TC Channel 0\r
+ AT91_REG Reserved0[4]; // \r
+ AT91S_TC TCB_TC1; // TC Channel 1\r
+ AT91_REG Reserved1[4]; // \r
+ AT91S_TC TCB_TC2; // TC Channel 2\r
+ AT91_REG Reserved2[4]; // \r
+ AT91_REG TCB_BCR; // TC Block Control Register\r
+ AT91_REG TCB_BMR; // TC Block Mode Register\r
+} AT91S_TCB, *AT91PS_TCB;\r
+\r
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- \r
+#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command\r
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- \r
+#define AT91C_TCB_TC0XC0S ((unsigned int) 0x1 << 0) // (TCB) External Clock Signal 0 Selection\r
+#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0\r
+#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0\r
+#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0\r
+#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0\r
+#define AT91C_TCB_TC1XC1S ((unsigned int) 0x1 << 2) // (TCB) External Clock Signal 1 Selection\r
+#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1\r
+#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1\r
+#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1\r
+#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1\r
+#define AT91C_TCB_TC2XC2S ((unsigned int) 0x1 << 4) // (TCB) External Clock Signal 2 Selection\r
+#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2\r
+#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2\r
+#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2\r
+#define AT91C_TCB_TC2XC2S_TIOA2 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Peripheral Data Controller\r
+// *****************************************************************************\r
+typedef struct _AT91S_PDC {\r
+ AT91_REG PDC_RPR; // Receive Pointer Register\r
+ AT91_REG PDC_RCR; // Receive Counter Register\r
+ AT91_REG PDC_TPR; // Transmit Pointer Register\r
+ AT91_REG PDC_TCR; // Transmit Counter Register\r
+} AT91S_PDC, *AT91PS_PDC;\r
+\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Usart\r
+// *****************************************************************************\r
+typedef struct _AT91S_USART {\r
+ AT91_REG US_CR; // Control Register\r
+ AT91_REG US_MR; // Mode Register\r
+ AT91_REG US_IER; // Interrupt Enable Register\r
+ AT91_REG US_IDR; // Interrupt Disable Register\r
+ AT91_REG US_IMR; // Interrupt Mask Register\r
+ AT91_REG US_CSR; // Channel Status Register\r
+ AT91_REG US_RHR; // Receiver Holding Register\r
+ AT91_REG US_THR; // Transmitter Holding Register\r
+ AT91_REG US_BRGR; // Baud Rate Generator Register\r
+ AT91_REG US_RTOR; // Receiver Time-out Register\r
+ AT91_REG US_TTGR; // Transmitter Time-guard Register\r
+ AT91_REG Reserved0[1]; // \r
+ AT91_REG US_RPR; // Receive Pointer Register\r
+ AT91_REG US_RCR; // Receive Counter Register\r
+ AT91_REG US_TPR; // Transmit Pointer Register\r
+ AT91_REG US_TCR; // Transmit Counter Register\r
+} AT91S_USART, *AT91PS_USART;\r
+\r
+// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- \r
+#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (USART) Reset Receiver\r
+#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (USART) Reset Transmitter\r
+#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (USART) Receiver Enable\r
+#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (USART) Receiver Disable\r
+#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (USART) Transmitter Enable\r
+#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (USART) Transmitter Disable\r
+#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (USART) Reset Status Bits\r
+#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break\r
+#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break\r
+#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out\r
+#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address\r
+// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- \r
+#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock\r
+#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock\r
+#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1\r
+#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM)\r
+#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK)\r
+#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock\r
+#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits\r
+#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits\r
+#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits\r
+#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits\r
+#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select\r
+#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (USART) Parity type\r
+#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (USART) Even Parity\r
+#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (USART) Odd Parity\r
+#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (USART) Parity forced to 0 (Space)\r
+#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (USART) Parity forced to 1 (Mark)\r
+#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (USART) No Parity\r
+#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (USART) Multi-drop mode\r
+#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits\r
+#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit\r
+#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits\r
+#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits\r
+#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (USART) Channel Mode\r
+#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (USART) Normal Mode: The USART channel operates as an RX/TX USART.\r
+#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (USART) Automatic Echo: Receiver Data Input is connected to the TXD pin.\r
+#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (USART) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.\r
+#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (USART) Remote Loopback: RXD pin is internally connected to TXD pin.\r
+#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length\r
+#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select\r
+// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- \r
+#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (USART) RXRDY Interrupt\r
+#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (USART) TXRDY Interrupt\r
+#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break\r
+#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (USART) End of Receive Transfer Interrupt\r
+#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (USART) End of Transmit Interrupt\r
+#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (USART) Overrun Interrupt\r
+#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (USART) Framing Error Interrupt\r
+#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (USART) Parity Error Interrupt\r
+#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out\r
+#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (USART) TXEMPTY Interrupt\r
+// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- \r
+// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- \r
+// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Special Function Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_SF {\r
+ AT91_REG SF_CIDR; // Chip ID Register\r
+ AT91_REG SF_EXID; // Chip ID Extension Register\r
+ AT91_REG SF_RSR; // Reset Status Register\r
+ AT91_REG SF_MMR; // Memory Mode Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG SF_PMR; // Protect Mode Register\r
+} AT91S_SF, *AT91PS_SF;\r
+\r
+// -------- SF_CIDR : (SF Offset: 0x0) Chip ID Register -------- \r
+#define AT91C_SF_VERSION ((unsigned int) 0x1F << 0) // (SF) Version of the chip\r
+#define AT91C_SF_BIT5 ((unsigned int) 0x1 << 5) // (SF) Hardwired at 0\r
+#define AT91C_SF_BIT6 ((unsigned int) 0x1 << 6) // (SF) Hardwired at 1\r
+#define AT91C_SF_BIT7 ((unsigned int) 0x1 << 7) // (SF) Hardwired at 0\r
+#define AT91C_SF_NVPSIZ ((unsigned int) 0xF << 8) // (SF) Nonvolatile Program Memory Size\r
+#define AT91C_SF_NVPSIZ_NONE ((unsigned int) 0x0 << 8) // (SF) None\r
+#define AT91C_SF_NVPSIZ_32K ((unsigned int) 0x3 << 8) // (SF) 32K Bytes\r
+#define AT91C_SF_NVPSIZ_64K ((unsigned int) 0x5 << 8) // (SF) 64K Bytes\r
+#define AT91C_SF_NVPSIZ_128K ((unsigned int) 0x7 << 8) // (SF) 128K Bytes\r
+#define AT91C_SF_NVPSIZ_256K ((unsigned int) 0x11 << 8) // (SF) 256K Bytes\r
+#define AT91C_SF_NVDSIZ ((unsigned int) 0xF << 12) // (SF) Nonvolatile Data Memory Size\r
+#define AT91C_SF_NVDSIZ_NONE ((unsigned int) 0x0 << 12) // (SF) None\r
+#define AT91C_SF_VDSIZ ((unsigned int) 0xF << 16) // (SF) Volatile Data Memory Size\r
+#define AT91C_SF_VDSIZ_NONE ((unsigned int) 0x0 << 16) // (SF) None\r
+#define AT91C_SF_VDSIZ_1K ((unsigned int) 0x3 << 16) // (SF) 1K Bytes\r
+#define AT91C_SF_VDSIZ_2K ((unsigned int) 0x5 << 16) // (SF) 2K Bytes\r
+#define AT91C_SF_VDSIZ_4K ((unsigned int) 0x7 << 16) // (SF) 4K Bytes\r
+#define AT91C_SF_VDSIZ_8K ((unsigned int) 0x11 << 16) // (SF) 8K Bytes\r
+#define AT91C_SF_ARCH ((unsigned int) 0xFF << 20) // (SF) Chip Architecture\r
+#define AT91C_SF_ARCH_AT91x40 ((unsigned int) 0x28 << 20) // (SF) AT91x40yyy\r
+#define AT91C_SF_ARCH_AT91x55 ((unsigned int) 0x37 << 20) // (SF) AT91x55yyy\r
+#define AT91C_SF_ARCH_AT91x63 ((unsigned int) 0x3F << 20) // (SF) AT91x63yyy\r
+#define AT91C_SF_NVPTYP ((unsigned int) 0x7 << 28) // (SF) Nonvolatile Program Memory Type\r
+#define AT91C_SF_NVPTYP_NVPTYP_M ((unsigned int) 0x1 << 28) // (SF) 'M' Series or 'F' Series\r
+#define AT91C_SF_NVPTYP_NVPTYP_R ((unsigned int) 0x4 << 28) // (SF) 'R' Series\r
+#define AT91C_SF_EXT ((unsigned int) 0x1 << 31) // (SF) Extension Flag\r
+// -------- SF_RSR : (SF Offset: 0x8) Reset Status Information -------- \r
+#define AT91C_SF_RESET ((unsigned int) 0xFF << 0) // (SF) Cause of Reset\r
+#define AT91C_SF_RESET_WD ((unsigned int) 0x35) // (SF) Internal Watchdog\r
+#define AT91C_SF_RESET_EXT ((unsigned int) 0x6C) // (SF) External Pin\r
+// -------- SF_MMR : (SF Offset: 0xc) Memory Mode Register -------- \r
+#define AT91C_SF_RAMWU ((unsigned int) 0x1 << 0) // (SF) Internal Extended RAM Write Detection\r
+// -------- SF_PMR : (SF Offset: 0x18) Protection Mode Register -------- \r
+#define AT91C_SF_AIC ((unsigned int) 0x1 << 5) // (SF) AIC Protect Mode Enable\r
+#define AT91C_SF_PMRKEY ((unsigned int) 0xFFFF << 16) // (SF) Protect Mode Register Key\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR External Bus Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_EBI {\r
+ AT91_REG EBI_CSR[8]; // Chip-select Register\r
+ AT91_REG EBI_RCR; // Remap Control Register\r
+ AT91_REG EBI_MCR; // Memory Control Register\r
+} AT91S_EBI, *AT91PS_EBI;\r
+\r
+// -------- EBI_CSR : (EBI Offset: 0x0) Chip Select Register -------- \r
+#define AT91C_EBI_DBW ((unsigned int) 0x3 << 0) // (EBI) Data Bus Width\r
+#define AT91C_EBI_DBW_16 ((unsigned int) 0x1) // (EBI) 16-bit data bus width\r
+#define AT91C_EBI_DBW_8 ((unsigned int) 0x2) // (EBI) 8-bit data bus width\r
+#define AT91C_EBI_NWS ((unsigned int) 0x7 << 2) // (EBI) Number of wait states\r
+#define AT91C_EBI_NWS_1 ((unsigned int) 0x0 << 2) // (EBI) 1 wait state\r
+#define AT91C_EBI_NWS_2 ((unsigned int) 0x1 << 2) // (EBI) 2 wait state\r
+#define AT91C_EBI_NWS_3 ((unsigned int) 0x2 << 2) // (EBI) 3 wait state\r
+#define AT91C_EBI_NWS_4 ((unsigned int) 0x3 << 2) // (EBI) 4 wait state\r
+#define AT91C_EBI_NWS_5 ((unsigned int) 0x4 << 2) // (EBI) 5 wait state\r
+#define AT91C_EBI_NWS_6 ((unsigned int) 0x5 << 2) // (EBI) 6 wait state\r
+#define AT91C_EBI_NWS_7 ((unsigned int) 0x6 << 2) // (EBI) 7 wait state\r
+#define AT91C_EBI_NWS_8 ((unsigned int) 0x7 << 2) // (EBI) 8 wait state\r
+#define AT91C_EBI_WSE ((unsigned int) 0x1 << 5) // (EBI) Wait State Enable\r
+#define AT91C_EBI_PAGES ((unsigned int) 0x3 << 7) // (EBI) Pages Size\r
+#define AT91C_EBI_PAGES_1M ((unsigned int) 0x0 << 7) // (EBI) 1M Byte\r
+#define AT91C_EBI_PAGES_4M ((unsigned int) 0x1 << 7) // (EBI) 4M Byte\r
+#define AT91C_EBI_PAGES_16M ((unsigned int) 0x2 << 7) // (EBI) 16M Byte\r
+#define AT91C_EBI_PAGES_64M ((unsigned int) 0x3 << 7) // (EBI) 64M Byte\r
+#define AT91C_EBI_TDF ((unsigned int) 0x7 << 9) // (EBI) Data Float Output Time\r
+#define AT91C_EBI_TDF_0 ((unsigned int) 0x0 << 9) // (EBI) 1 TDF\r
+#define AT91C_EBI_TDF_1 ((unsigned int) 0x1 << 9) // (EBI) 2 TDF\r
+#define AT91C_EBI_TDF_2 ((unsigned int) 0x2 << 9) // (EBI) 3 TDF\r
+#define AT91C_EBI_TDF_3 ((unsigned int) 0x3 << 9) // (EBI) 4 TDF\r
+#define AT91C_EBI_TDF_4 ((unsigned int) 0x4 << 9) // (EBI) 5 TDF\r
+#define AT91C_EBI_TDF_5 ((unsigned int) 0x5 << 9) // (EBI) 6 TDF\r
+#define AT91C_EBI_TDF_6 ((unsigned int) 0x6 << 9) // (EBI) 7 TDF\r
+#define AT91C_EBI_TDF_7 ((unsigned int) 0x7 << 9) // (EBI) 8 TDF\r
+#define AT91C_EBI_BAT ((unsigned int) 0x1 << 12) // (EBI) Byte Access Type\r
+#define AT91C_EBI_CSEN ((unsigned int) 0x1 << 13) // (EBI) Chip Select Enable\r
+#define AT91C_EBI_BA ((unsigned int) 0xFFF << 20) // (EBI) Base Address\r
+// -------- EBI_RCR : (EBI Offset: 0x20) Remap Control Register -------- \r
+#define AT91C_EBI_RCB ((unsigned int) 0x1 << 0) // (EBI) 0 = No effect. 1 = Cancels the remapping (performed at reset) of the page zero memory devices.\r
+// -------- EBI_MCR : (EBI Offset: 0x24) Memory Control Register -------- \r
+#define AT91C_EBI_ALE ((unsigned int) 0x7 << 0) // (EBI) Address Line Enable\r
+#define AT91C_EBI_ALE_16M ((unsigned int) 0x0) // (EBI) Valid Address Bits = A20, A21, A22, A23 Max Addressable Space = 16M Bytes Valid Chip Select=None \r
+#define AT91C_EBI_ALE_8M ((unsigned int) 0x4) // (EBI) Valid Address Bits = A20, A21, A22 Max Addressable Space = 8M Bytes Valid Chip Select = CS4 \r
+#define AT91C_EBI_ALE_4M ((unsigned int) 0x5) // (EBI) Valid Address Bits = A20, A21 Max Addressable Space = 4M Bytes Valid Chip Select = CS4, CS5 \r
+#define AT91C_EBI_ALE_2M ((unsigned int) 0x6) // (EBI) Valid Address Bits = A20 Max Addressable Space = 2M Bytes Valid Chip Select = CS4, CS5, CS6 \r
+#define AT91C_EBI_ALE_1M ((unsigned int) 0x7) // (EBI) Valid Address Bits = None Max Addressable Space = 1M Byte Valid Chip Select = CS4, CS5, CS6, CS7 \r
+#define AT91C_EBI_DRP ((unsigned int) 0x1 << 4) // (EBI) \r
+\r
+// *****************************************************************************\r
+// REGISTER ADDRESS DEFINITION FOR AT91R40008\r
+// *****************************************************************************\r
+// ========== Register definition for AIC peripheral ========== \r
+#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register\r
+#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register\r
+#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register\r
+#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector egister\r
+#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode egister\r
+#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register\r
+#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register\r
+#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register\r
+#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register\r
+#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register\r
+#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register\r
+#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register\r
+#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register\r
+#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command egister\r
+// ========== Register definition for WD peripheral ========== \r
+#define AT91C_WD_SR ((AT91_REG *) 0xFFFF800C) // (WD) Status Register\r
+#define AT91C_WD_CMR ((AT91_REG *) 0xFFFF8004) // (WD) Clock Mode Register\r
+#define AT91C_WD_CR ((AT91_REG *) 0xFFFF8008) // (WD) Control Register\r
+#define AT91C_WD_OMR ((AT91_REG *) 0xFFFF8000) // (WD) Overflow Mode Register\r
+// ========== Register definition for PS peripheral ========== \r
+#define AT91C_PS_PCDR ((AT91_REG *) 0xFFFF4008) // (PS) Peripheral Clock Disable Register\r
+#define AT91C_PS_CR ((AT91_REG *) 0xFFFF4000) // (PS) Control Register\r
+#define AT91C_PS_PCSR ((AT91_REG *) 0xFFFF400C) // (PS) Peripheral Clock Status Register\r
+#define AT91C_PS_PCER ((AT91_REG *) 0xFFFF4004) // (PS) Peripheral Clock Enable Register\r
+// ========== Register definition for PIO peripheral ========== \r
+#define AT91C_PIO_MDSR ((AT91_REG *) 0xFFFF0058) // (PIO) Multi-driver Status Register\r
+#define AT91C_PIO_IFSR ((AT91_REG *) 0xFFFF0028) // (PIO) Input Filter Status Register\r
+#define AT91C_PIO_IFER ((AT91_REG *) 0xFFFF0020) // (PIO) Input Filter Enable Register\r
+#define AT91C_PIO_OSR ((AT91_REG *) 0xFFFF0018) // (PIO) Output Status Register\r
+#define AT91C_PIO_OER ((AT91_REG *) 0xFFFF0010) // (PIO) Output Enable Register\r
+#define AT91C_PIO_PSR ((AT91_REG *) 0xFFFF0008) // (PIO) PIO Status Register\r
+#define AT91C_PIO_PDSR ((AT91_REG *) 0xFFFF003C) // (PIO) Pin Data Status Register\r
+#define AT91C_PIO_CODR ((AT91_REG *) 0xFFFF0034) // (PIO) Clear Output Data Register\r
+#define AT91C_PIO_IFDR ((AT91_REG *) 0xFFFF0024) // (PIO) Input Filter Disable Register\r
+#define AT91C_PIO_MDER ((AT91_REG *) 0xFFFF0050) // (PIO) Multi-driver Enable Register\r
+#define AT91C_PIO_IMR ((AT91_REG *) 0xFFFF0048) // (PIO) Interrupt Mask Register\r
+#define AT91C_PIO_IER ((AT91_REG *) 0xFFFF0040) // (PIO) Interrupt Enable Register\r
+#define AT91C_PIO_ODSR ((AT91_REG *) 0xFFFF0038) // (PIO) Output Data Status Register\r
+#define AT91C_PIO_SODR ((AT91_REG *) 0xFFFF0030) // (PIO) Set Output Data Register\r
+#define AT91C_PIO_PER ((AT91_REG *) 0xFFFF0000) // (PIO) PIO Enable Register\r
+#define AT91C_PIO_MDDR ((AT91_REG *) 0xFFFF0054) // (PIO) Multi-driver Disable Register\r
+#define AT91C_PIO_ISR ((AT91_REG *) 0xFFFF004C) // (PIO) Interrupt Status Register\r
+#define AT91C_PIO_IDR ((AT91_REG *) 0xFFFF0044) // (PIO) Interrupt Disable Register\r
+#define AT91C_PIO_PDR ((AT91_REG *) 0xFFFF0004) // (PIO) PIO Disable Register\r
+#define AT91C_PIO_ODR ((AT91_REG *) 0xFFFF0014) // (PIO) Output Disable Registerr\r
+// ========== Register definition for TC2 peripheral ========== \r
+#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFE00A8) // (TC2) Interrupt Disable Register\r
+#define AT91C_TC2_SR ((AT91_REG *) 0xFFFE00A0) // (TC2) Status Register\r
+#define AT91C_TC2_RB ((AT91_REG *) 0xFFFE0098) // (TC2) Register B\r
+#define AT91C_TC2_CV ((AT91_REG *) 0xFFFE0090) // (TC2) Counter Value\r
+#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFE0080) // (TC2) Channel Control Register\r
+#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFE00AC) // (TC2) Interrupt Mask Register\r
+#define AT91C_TC2_IER ((AT91_REG *) 0xFFFE00A4) // (TC2) Interrupt Enable Register\r
+#define AT91C_TC2_RC ((AT91_REG *) 0xFFFE009C) // (TC2) Register C\r
+#define AT91C_TC2_RA ((AT91_REG *) 0xFFFE0094) // (TC2) Register A\r
+#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFE0084) // (TC2) Channel Mode Register\r
+// ========== Register definition for TC1 peripheral ========== \r
+#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFE0068) // (TC1) Interrupt Disable Register\r
+#define AT91C_TC1_SR ((AT91_REG *) 0xFFFE0060) // (TC1) Status Register\r
+#define AT91C_TC1_RB ((AT91_REG *) 0xFFFE0058) // (TC1) Register B\r
+#define AT91C_TC1_CV ((AT91_REG *) 0xFFFE0050) // (TC1) Counter Value\r
+#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFE0040) // (TC1) Channel Control Register\r
+#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFE006C) // (TC1) Interrupt Mask Register\r
+#define AT91C_TC1_IER ((AT91_REG *) 0xFFFE0064) // (TC1) Interrupt Enable Register\r
+#define AT91C_TC1_RC ((AT91_REG *) 0xFFFE005C) // (TC1) Register C\r
+#define AT91C_TC1_RA ((AT91_REG *) 0xFFFE0054) // (TC1) Register A\r
+#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFE0044) // (TC1) Channel Mode Register\r
+// ========== Register definition for TC0 peripheral ========== \r
+#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFE0028) // (TC0) Interrupt Disable Register\r
+#define AT91C_TC0_SR ((AT91_REG *) 0xFFFE0020) // (TC0) Status Register\r
+#define AT91C_TC0_RB ((AT91_REG *) 0xFFFE0018) // (TC0) Register B\r
+#define AT91C_TC0_CV ((AT91_REG *) 0xFFFE0010) // (TC0) Counter Value\r
+#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFE0000) // (TC0) Channel Control Register\r
+#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFE002C) // (TC0) Interrupt Mask Register\r
+#define AT91C_TC0_IER ((AT91_REG *) 0xFFFE0024) // (TC0) Interrupt Enable Register\r
+#define AT91C_TC0_RC ((AT91_REG *) 0xFFFE001C) // (TC0) Register C\r
+#define AT91C_TC0_RA ((AT91_REG *) 0xFFFE0014) // (TC0) Register A\r
+#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFE0004) // (TC0) Channel Mode Register\r
+// ========== Register definition for TCB0 peripheral ========== \r
+#define AT91C_TCB0_BCR ((AT91_REG *) 0xFFFE00C0) // (TCB0) TC Block Control Register\r
+#define AT91C_TCB0_BMR ((AT91_REG *) 0xFFFE00C4) // (TCB0) TC Block Mode Register\r
+// ========== Register definition for PDC_US1 peripheral ========== \r
+#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4038) // (PDC_US1) Transmit Pointer Register\r
+#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4030) // (PDC_US1) Receive Pointer Register\r
+#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC403C) // (PDC_US1) Transmit Counter Register\r
+#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4034) // (PDC_US1) Receive Counter Register\r
+// ========== Register definition for US1 peripheral ========== \r
+#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFCC024) // (US1) Receiver Time-out Register\r
+#define AT91C_US1_THR ((AT91_REG *) 0xFFFCC01C) // (US1) Transmitter Holding Register\r
+#define AT91C_US1_CSR ((AT91_REG *) 0xFFFCC014) // (US1) Channel Status Register\r
+#define AT91C_US1_IDR ((AT91_REG *) 0xFFFCC00C) // (US1) Interrupt Disable Register\r
+#define AT91C_US1_MR ((AT91_REG *) 0xFFFCC004) // (US1) Mode Register\r
+#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFCC028) // (US1) Transmitter Time-guard Register\r
+#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFCC020) // (US1) Baud Rate Generator Register\r
+#define AT91C_US1_RHR ((AT91_REG *) 0xFFFCC018) // (US1) Receiver Holding Register\r
+#define AT91C_US1_IMR ((AT91_REG *) 0xFFFCC010) // (US1) Interrupt Mask Register\r
+#define AT91C_US1_IER ((AT91_REG *) 0xFFFCC008) // (US1) Interrupt Enable Register\r
+#define AT91C_US1_CR ((AT91_REG *) 0xFFFCC000) // (US1) Control Register\r
+// ========== Register definition for PDC_US0 peripheral ========== \r
+#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0038) // (PDC_US0) Transmit Pointer Register\r
+#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0030) // (PDC_US0) Receive Pointer Register\r
+#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC003C) // (PDC_US0) Transmit Counter Register\r
+#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0034) // (PDC_US0) Receive Counter Register\r
+// ========== Register definition for US0 peripheral ========== \r
+#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFD0024) // (US0) Receiver Time-out Register\r
+#define AT91C_US0_THR ((AT91_REG *) 0xFFFD001C) // (US0) Transmitter Holding Register\r
+#define AT91C_US0_CSR ((AT91_REG *) 0xFFFD0014) // (US0) Channel Status Register\r
+#define AT91C_US0_IDR ((AT91_REG *) 0xFFFD000C) // (US0) Interrupt Disable Register\r
+#define AT91C_US0_MR ((AT91_REG *) 0xFFFD0004) // (US0) Mode Register\r
+#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFD0028) // (US0) Transmitter Time-guard Register\r
+#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFD0020) // (US0) Baud Rate Generator Register\r
+#define AT91C_US0_RHR ((AT91_REG *) 0xFFFD0018) // (US0) Receiver Holding Register\r
+#define AT91C_US0_IMR ((AT91_REG *) 0xFFFD0010) // (US0) Interrupt Mask Register\r
+#define AT91C_US0_IER ((AT91_REG *) 0xFFFD0008) // (US0) Interrupt Enable Register\r
+#define AT91C_US0_CR ((AT91_REG *) 0xFFFD0000) // (US0) Control Register\r
+// ========== Register definition for SF peripheral ========== \r
+#define AT91C_SF_PMR ((AT91_REG *) 0xFFF00018) // (SF) Protect Mode Register\r
+#define AT91C_SF_RSR ((AT91_REG *) 0xFFF00008) // (SF) Reset Status Register\r
+#define AT91C_SF_CIDR ((AT91_REG *) 0xFFF00000) // (SF) Chip ID Register\r
+#define AT91C_SF_MMR ((AT91_REG *) 0xFFF0000C) // (SF) Memory Mode Register\r
+#define AT91C_SF_EXID ((AT91_REG *) 0xFFF00004) // (SF) Chip ID Extension Register\r
+// ========== Register definition for EBI peripheral ========== \r
+#define AT91C_EBI_RCR ((AT91_REG *) 0xFFE00020) // (EBI) Remap Control Register\r
+#define AT91C_EBI_CSR ((AT91_REG *) 0xFFE00000) // (EBI) Chip-select Register\r
+#define AT91C_EBI_MCR ((AT91_REG *) 0xFFE00024) // (EBI) Memory Control Register\r
+\r
+// *****************************************************************************\r
+// PIO DEFINITIONS FOR AT91R40008\r
+// *****************************************************************************\r
+#define AT91C_PIO_P0 ((unsigned int) 1 << 0) // Pin Controlled by P0\r
+#define AT91C_P0_TCLK0 ((unsigned int) AT91C_PIO_P0) // Timer 0 Clock signal\r
+#define AT91C_PIO_P1 ((unsigned int) 1 << 1) // Pin Controlled by P1\r
+#define AT91C_P1_TIOA0 ((unsigned int) AT91C_PIO_P1) // Timer 0 Signal A\r
+#define AT91C_PIO_P10 ((unsigned int) 1 << 10) // Pin Controlled by P10\r
+#define AT91C_P10_IRQ1 ((unsigned int) AT91C_PIO_P10) // External Interrupt 1\r
+#define AT91C_PIO_P11 ((unsigned int) 1 << 11) // Pin Controlled by P11\r
+#define AT91C_P11_IRQ2 ((unsigned int) AT91C_PIO_P11) // External Interrupt 2\r
+#define AT91C_PIO_P12 ((unsigned int) 1 << 12) // Pin Controlled by P12\r
+#define AT91C_P12_FIQ ((unsigned int) AT91C_PIO_P12) // Fast External Interrupt\r
+#define AT91C_PIO_P13 ((unsigned int) 1 << 13) // Pin Controlled by P13\r
+#define AT91C_P13_SCK0 ((unsigned int) AT91C_PIO_P13) // USART 0 Serial Clock\r
+#define AT91C_PIO_P14 ((unsigned int) 1 << 14) // Pin Controlled by P14\r
+#define AT91C_P14_TXD0 ((unsigned int) AT91C_PIO_P14) // USART 0 Transmit Data\r
+#define AT91C_PIO_P15 ((unsigned int) 1 << 15) // Pin Controlled by P15\r
+#define AT91C_P15_RXD0 ((unsigned int) AT91C_PIO_P15) // USART 0 Receive Data\r
+#define AT91C_PIO_P16 ((unsigned int) 1 << 16) // Pin Controlled by P16\r
+#define AT91C_PIO_P17 ((unsigned int) 1 << 17) // Pin Controlled by P17\r
+#define AT91C_PIO_P18 ((unsigned int) 1 << 18) // Pin Controlled by P18\r
+#define AT91C_PIO_P19 ((unsigned int) 1 << 19) // Pin Controlled by P19\r
+#define AT91C_PIO_P2 ((unsigned int) 1 << 2) // Pin Controlled by P2\r
+#define AT91C_P2_TIOB0 ((unsigned int) AT91C_PIO_P2) // Timer 0 Signal B\r
+#define AT91C_PIO_P20 ((unsigned int) 1 << 20) // Pin Controlled by P20\r
+#define AT91C_P20_SCK1 ((unsigned int) AT91C_PIO_P20) // USART 1 Serial Clock\r
+#define AT91C_PIO_P21 ((unsigned int) 1 << 21) // Pin Controlled by P21\r
+#define AT91C_P21_TXD1 ((unsigned int) AT91C_PIO_P21) // USART 1 Transmit Data\r
+#define AT91C_P21_NTRI ((unsigned int) AT91C_PIO_P21) // Tri-state Mode\r
+#define AT91C_PIO_P22 ((unsigned int) 1 << 22) // Pin Controlled by P22\r
+#define AT91C_P22_RXD1 ((unsigned int) AT91C_PIO_P22) // USART 1 Receive Data\r
+#define AT91C_PIO_P23 ((unsigned int) 1 << 23) // Pin Controlled by P23\r
+#define AT91C_PIO_P24 ((unsigned int) 1 << 24) // Pin Controlled by P24\r
+#define AT91C_P24_BMS ((unsigned int) AT91C_PIO_P24) // Boot Mode Select\r
+#define AT91C_PIO_P25 ((unsigned int) 1 << 25) // Pin Controlled by P25\r
+#define AT91C_P25_MCKO ((unsigned int) AT91C_PIO_P25) // Master Clock Out\r
+#define AT91C_PIO_P26 ((unsigned int) 1 << 26) // Pin Controlled by P26\r
+#define AT91C_P26_NCS2 ((unsigned int) AT91C_PIO_P26) // Chip Select 2\r
+#define AT91C_PIO_P27 ((unsigned int) 1 << 27) // Pin Controlled by P27\r
+#define AT91C_P27_NCS3 ((unsigned int) AT91C_PIO_P27) // Chip Select 3\r
+#define AT91C_PIO_P28 ((unsigned int) 1 << 28) // Pin Controlled by P28\r
+#define AT91C_P28_A20 ((unsigned int) AT91C_PIO_P28) // Address line A20\r
+#define AT91C_P28_NCS7 ((unsigned int) AT91C_PIO_P28) // Chip Select 7\r
+#define AT91C_PIO_P29 ((unsigned int) 1 << 29) // Pin Controlled by P29\r
+#define AT91C_P29_A21 ((unsigned int) AT91C_PIO_P29) // Address line A21\r
+#define AT91C_P29_NCS6 ((unsigned int) AT91C_PIO_P29) // Chip Select 6\r
+#define AT91C_PIO_P3 ((unsigned int) 1 << 3) // Pin Controlled by P3\r
+#define AT91C_P3_TCLK1 ((unsigned int) AT91C_PIO_P3) // Timer 1 Clock signal\r
+#define AT91C_PIO_P30 ((unsigned int) 1 << 30) // Pin Controlled by P30\r
+#define AT91C_P30_A22 ((unsigned int) AT91C_PIO_P30) // Address line A22\r
+#define AT91C_P30_NCS5 ((unsigned int) AT91C_PIO_P30) // Chip Select 5\r
+#define AT91C_PIO_P31 ((unsigned int) 1 << 31) // Pin Controlled by P31\r
+#define AT91C_P31_A23 ((unsigned int) AT91C_PIO_P31) // Address line A23\r
+#define AT91C_P31_NCS4 ((unsigned int) AT91C_PIO_P31) // Chip Select 4\r
+#define AT91C_PIO_P4 ((unsigned int) 1 << 4) // Pin Controlled by P4\r
+#define AT91C_P4_TIOA1 ((unsigned int) AT91C_PIO_P4) // Timer 1 Signal A\r
+#define AT91C_PIO_P5 ((unsigned int) 1 << 5) // Pin Controlled by P5\r
+#define AT91C_P5_TIOB1 ((unsigned int) AT91C_PIO_P5) // Timer 1 Signal B\r
+#define AT91C_PIO_P6 ((unsigned int) 1 << 6) // Pin Controlled by P6\r
+#define AT91C_P6_TCLK2 ((unsigned int) AT91C_PIO_P6) // Timer 2 Clock signal\r
+#define AT91C_PIO_P7 ((unsigned int) 1 << 7) // Pin Controlled by P7\r
+#define AT91C_P7_TIOA2 ((unsigned int) AT91C_PIO_P7) // Timer 2 Signal A\r
+#define AT91C_PIO_P8 ((unsigned int) 1 << 8) // Pin Controlled by P8\r
+#define AT91C_P8_TIOB2 ((unsigned int) AT91C_PIO_P8) // Timer 2 Signal B\r
+#define AT91C_PIO_P9 ((unsigned int) 1 << 9) // Pin Controlled by P9\r
+#define AT91C_P9_IRQ0 ((unsigned int) AT91C_PIO_P9) // External Interrupt 0\r
+\r
+// *****************************************************************************\r
+// PERIPHERAL ID DEFINITIONS FOR AT91R40008\r
+// *****************************************************************************\r
+#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ)\r
+#define AT91C_ID_SYS ((unsigned int) 1) // SWI\r
+#define AT91C_ID_US0 ((unsigned int) 2) // USART 0\r
+#define AT91C_ID_US1 ((unsigned int) 3) // USART 1\r
+#define AT91C_ID_TC0 ((unsigned int) 4) // Timer Counter 0\r
+#define AT91C_ID_TC1 ((unsigned int) 5) // Timer Counter 1\r
+#define AT91C_ID_TC2 ((unsigned int) 6) // Timer Counter 2\r
+#define AT91C_ID_WD ((unsigned int) 7) // Watchdog Timer\r
+#define AT91C_ID_PIO ((unsigned int) 8) // Parallel IO Controller\r
+#define AT91C_ID_IRQ0 ((unsigned int) 16) // Advanced Interrupt Controller (IRQ0)\r
+#define AT91C_ID_IRQ1 ((unsigned int) 17) // Advanced Interrupt Controller (IRQ1)\r
+#define AT91C_ID_IRQ2 ((unsigned int) 18) // Advanced Interrupt Controller (IRQ2)\r
+\r
+// *****************************************************************************\r
+// BASE ADDRESS DEFINITIONS FOR AT91R40008\r
+// *****************************************************************************\r
+#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address\r
+#define AT91C_BASE_WD ((AT91PS_WD) 0xFFFF8000) // (WD) Base Address\r
+#define AT91C_BASE_PS ((AT91PS_PS) 0xFFFF4000) // (PS) Base Address\r
+#define AT91C_BASE_PIO ((AT91PS_PIO) 0xFFFF0000) // (PIO) Base Address\r
+#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFE0080) // (TC2) Base Address\r
+#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFE0040) // (TC1) Base Address\r
+#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFE0000) // (TC0) Base Address\r
+#define AT91C_BASE_TCB0 ((AT91PS_TCB) 0xFFFE0000) // (TCB0) Base Address\r
+#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4030) // (PDC_US1) Base Address\r
+#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFCC000) // (US1) Base Address\r
+#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0030) // (PDC_US0) Base Address\r
+#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFD0000) // (US0) Base Address\r
+#define AT91C_BASE_SF ((AT91PS_SF) 0xFFF00000) // (SF) Base Address\r
+#define AT91C_BASE_EBI ((AT91PS_EBI) 0xFFE00000) // (EBI) Base Address\r
+\r
+// *****************************************************************************\r
+// MEMORY MAPPING DEFINITIONS FOR AT91R40008\r
+// *****************************************************************************\r
+#define AT91C_SRAM_BEFORE_REMAP ((char *) 0x00300000) // Internal SRAM before remap base address\r
+#define AT91C_SRAM_BEFORE_REMAP_SIZE ((unsigned int) 0x00040000) // Internal SRAM before remap size in byte (256 Kbyte)\r
+#define AT91C_SRAM_AFTER_REMAP ((char *) 0x00000000) // Internal SRAM after remap base address\r
+#define AT91C_SRAM_AFTER_REMAP_SIZE ((unsigned int) 0x00040000) // Internal SRAM after remap size in byte (256 Kbyte)\r
+\r
+#endif\r
--- /dev/null
+[SETUP]\r
+CpuVendor=Atmel\r
+CpuChip=AT91R40807\r
+FlashVendor=Atmel\r
+FlashChip=AT49BV/F1614A\r
+RamAddress=$00000000\r
+RamSupport=1\r
+FlashAddress=$01000000\r
+FlashWidth=16\r
+FlashChipsPerSector=1\r
+LittleEndian=0\r
+SectStart=0\r
+SectEnd=38\r
+AutoErase=0\r
+AutoVerify=1\r
+CpuEndian=LITTLE\r
+SimCount=3\r
+MemoryCount=0\r
+ProgramFile=E:\temp\embesttest\Demo\ARM7_AT91R40008_GCC_Embest\rtosdemo.hex\r
+UploadFile=c:\EB40_Lower.bin\r
+Format=Intel Hex\r
+Sim3=EBI_RCR:$00000001\r
+Sim2=EBI_CSR1:$02002122\r
+Sim1=EBI_CSR0:$01002539\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+#include <AT91R40008.h>\r
+\r
+#define configFLASH_SPEED_NSEC 100 /* External flash access speed (for ROM builds) */\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. \r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 66000000 ) /* = 66.000MHz clk gen */\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 128 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 25 * 1024 ) )\r
+#define configMAX_TASK_NAME_LEN ( 16 )\r
+#define configUSE_TRACE_FACILITY 0\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 1\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+# FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+#\r
+# This file is part of the FreeRTOS distribution.\r
+#\r
+# FreeRTOS is free software; you can redistribute it and/or modify\r
+# it under the terms of the GNU General Public License as published by\r
+# the Free Software Foundation; either version 2 of the License, or\r
+# (at your option) any later version.\r
+#\r
+# FreeRTOS is distributed in the hope that it will be useful,\r
+# but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+# GNU General Public License for more details.\r
+#\r
+# You should have received a copy of the GNU General Public License\r
+# along with FreeRTOS; if not, write to the Free Software\r
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+#\r
+# A special exception to the GPL can be applied should you wish to distribute\r
+# a combined work that includes FreeRTOS, without being obliged to provide\r
+# the source code for any proprietary components. See the licensing section \r
+# of http://www.FreeRTOS.org for full details of how and when the exception\r
+# can be applied.\r
+#\r
+# ***************************************************************************\r
+# See http://www.FreeRTOS.org for documentation, latest information, license \r
+# and contact details. Please ensure to read the configuration and relevant \r
+# port sections of the online documentation.\r
+# ***************************************************************************\r
+\r
+CC=arm-elf-gcc\r
+OBJCOPY=arm-elf-objcopy\r
+ARCH=arm-elf-ar\r
+CRT0=boot.s\r
+\r
+#\r
+# CFLAGS common to both the THUMB and ARM mode builds\r
+#\r
+CFLAGS=-Wall -D $(RUN_MODE) -D GCC_AT91FR40008 -I. -I../../Source/include \\r
+ -I../Common/include $(DEBUG) -mcpu=arm7tdmi -T$(LDSCRIPT) \\r
+ -Wcast-align $(OPTIM)\r
+\r
+ifeq ($(USE_THUMB_MODE),YES)\r
+ CFLAGS += -mthumb-interwork -D THUMB_INTERWORK\r
+ THUMB_FLAGS=-mthumb\r
+endif\r
+\r
+\r
+LINKER_FLAGS=-Xlinker -ortosdemo.elf -Xlinker -M -Xlinker -Map=rtosdemo.map\r
+\r
+#\r
+# Source files that can be built to THUMB mode.\r
+#\r
+THUMB_SRC = \\r
+main.c \\r
+serial/serial.c \\r
+ParTest/ParTest.c \\r
+../Common/Minimal/integer.c \\r
+../Common/Minimal/flash.c \\r
+../Common/Minimal/PollQ.c \\r
+../Common/Minimal/comtest.c \\r
+../Common/Minimal/flop.c \\r
+../Common/Minimal/semtest.c \\r
+../Common/Minimal/dynamic.c \\r
+../Common/Minimal/BlockQ.c \\r
+../../Source/tasks.c \\r
+../../Source/queue.c \\r
+../../Source/list.c \\r
+../../Source/portable/MemMang/heap_2.c \\r
+../../Source/portable/GCC/ARM7_AT91FR40008/port.c\r
+\r
+#\r
+# Source files that must be built to ARM mode.\r
+#\r
+ARM_SRC = \\r
+../../Source/portable/GCC/ARM7_AT91FR40008/portISR.c \\r
+serial/serialISR.c\r
+\r
+#\r
+# Define all object files.\r
+#\r
+ARM_OBJ = $(ARM_SRC:.c=.o)\r
+THUMB_OBJ = $(THUMB_SRC:.c=.o)\r
+\r
+rtosdemo.hex : rtosdemo.elf\r
+ $(OBJCOPY) rtosdemo.elf -O ihex rtosdemo.hex\r
+\r
+rtosdemo.elf : $(ARM_OBJ) $(THUMB_OBJ) $(CRT0) Makefile\r
+ $(CC) $(CFLAGS) $(ARM_OBJ) $(THUMB_OBJ) -nostartfiles $(CRT0) $(LINKER_FLAGS)\r
+\r
+$(THUMB_OBJ) : %.o : %.c $(LDSCRIPT) Makefile\r
+ $(CC) -c $(THUMB_FLAGS) $(CFLAGS) $< -o $@\r
+\r
+$(ARM_OBJ) : %.o : %.c $(LDSCRIPT) Makefile\r
+ $(CC) -c $(CFLAGS) $< -o $@\r
+\r
+clean :\r
+ touch Makefile\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "portable.h"\r
+\r
+/* Demo app includes. */\r
+#include "partest.h"\r
+\r
+/* Hardware specific definitions. */\r
+#include "AT91R40008.h"\r
+#include "pio.h"\r
+#include "aic.h"\r
+\r
+#define partstNUM_LEDS ( 8 )\r
+#define partstALL_OUTPUTS_OFF ( ( unsigned portLONG ) ~(0xFFFFFFFF << partstNUM_LEDS) )\r
+\r
+static unsigned portLONG ulLEDReg;\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple parallel port IO routines.\r
+ *-----------------------------------------------------------*/\r
+\r
+static void SetLeds (unsigned int leds)\r
+{\r
+unsigned portLONG ulPIOSetReg, ulPIOClearReg;\r
+\r
+ /* LEDs are grouped in different port bits: P3-P6 and P16-P19.\r
+ A port bit set to '0' turns an LED on, '1' turns it off. */\r
+\r
+ ulPIOSetReg = ( (leds & 0xF) << 16 ) | ( (leds & 0xF0) >> 1 );\r
+ ulPIOClearReg = (~ulPIOSetReg) & 0x000F0078;\r
+\r
+ AT91C_BASE_PIO->PIO_SODR = ulPIOSetReg;\r
+ AT91C_BASE_PIO->PIO_CODR = ulPIOClearReg;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestInitialise( void )\r
+{\r
+ /* This is performed from main() as the io bits are shared with other setup\r
+ functions. Ensure the outputs are off to start. */\r
+ ulLEDReg = partstALL_OUTPUTS_OFF; \r
+\r
+ /* Enable clock to PIO... */\r
+ AT91C_BASE_PS->PS_PCER = AT91C_PS_PIO;\r
+\r
+ /* Enable all 8 LEDs and the four switches to be controlled by PIO... */\r
+ AT91C_BASE_PIO->PIO_PER = P3 | P4 | P5 | P6 | P16 | P17 | P18 | P19 | P1 | P2 | P9 | P12;\r
+\r
+ /* Configure all LED PIO lines for output... */\r
+ AT91C_BASE_PIO->PIO_OER = P3 | P4 | P5 | P6 | P16 | P17 | P18 | P19;\r
+\r
+ /* Configure all switch PIO lines for input... */\r
+ AT91C_BASE_PIO->PIO_ODR = P1 | P2 | P9 | P12;\r
+\r
+ /* Set initial state of LEDs. */\r
+ SetLeds( ulLEDReg );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )\r
+{\r
+ /* Switch an LED on or off as requested. */\r
+ if (uxLED < partstNUM_LEDS)\r
+ {\r
+ if( xValue )\r
+ {\r
+ ulLEDReg &= ~(1 << uxLED);\r
+ }\r
+ else\r
+ {\r
+ ulLEDReg |= (1 << uxLED);\r
+ }\r
+\r
+ SetLeds( ulLEDReg );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+ /* Toggle the state of the requested LED. */\r
+ if (uxLED < partstNUM_LEDS)\r
+ {\r
+ ulLEDReg ^= ( 1 << uxLED );\r
+ SetLeds( ulLEDReg );\r
+ }\r
+}\r
+\r
--- /dev/null
+//*----------------------------------------------------------------------------\r
+//* ATMEL Microcontroller Software Support - ROUSSET -\r
+//*----------------------------------------------------------------------------\r
+//* The software is delivered "AS IS" without warranty or condition of any\r
+//* kind, either express, implied or statutory. This includes without\r
+//* limitation any warranty or condition with respect to merchantability or\r
+//* fitness for any particular purpose, or against the infringements of\r
+//* intellectual property rights of others.\r
+//*----------------------------------------------------------------------------\r
+//* File Name : aic.h\r
+//* Object : Advanced Interrupt Controller Definition File.\r
+//*\r
+//* 1.0 01/04/00 JCZ : Creation\r
+//*----------------------------------------------------------------------------\r
+\r
+#ifndef aic_h\r
+#define aic_h\r
+\r
+//#include "periph/stdc/std_c.h"\r
+\r
+/*-----------------------------------------*/\r
+/* AIC User Interface Structure Definition */\r
+/*-----------------------------------------*/\r
+\r
+typedef struct\r
+{\r
+ at91_reg AIC_SMR[32] ; /* Source Mode Register */\r
+ at91_reg AIC_SVR[32] ; /* Source Vector Register */\r
+ at91_reg AIC_IVR ; /* IRQ Vector Register */\r
+ at91_reg AIC_FVR ; /* FIQ Vector Register */\r
+ at91_reg AIC_ISR ; /* Interrupt Status Register */\r
+ at91_reg AIC_IPR ; /* Interrupt Pending Register */\r
+ at91_reg AIC_IMR ; /* Interrupt Mask Register */\r
+ at91_reg AIC_CISR ; /* Core Interrupt Status Register */\r
+ at91_reg reserved0 ;\r
+ at91_reg reserved1 ;\r
+ at91_reg AIC_IECR ; /* Interrupt Enable Command Register */\r
+ at91_reg AIC_IDCR ; /* Interrupt Disable Command Register */\r
+ at91_reg AIC_ICCR ; /* Interrupt Clear Command Register */\r
+ at91_reg AIC_ISCR ; /* Interrupt Set Command Register */\r
+ at91_reg AIC_EOICR ; /* End of Interrupt Command Register */\r
+ at91_reg AIC_SPU ; /* Spurious Vector Register */\r
+} StructAIC ;\r
+\r
+/*--------------------------------------------*/\r
+/* AIC_SMR[]: Interrupt Source Mode Registers */\r
+/*--------------------------------------------*/\r
+\r
+#define AIC_PRIOR 0x07 /* Priority */\r
+\r
+#define AIC_SRCTYPE 0x60 /* Source Type Definition */\r
+\r
+/* Internal Interrupts */\r
+#define AIC_SRCTYPE_INT_LEVEL_SENSITIVE 0x00 /* Level Sensitive */\r
+#define AIC_SRCTYPE_INT_EDGE_TRIGGERED 0x20 /* Edge Triggered */\r
+\r
+/* External Interrupts */\r
+#define AIC_SRCTYPE_EXT_LOW_LEVEL 0x00 /* Low Level */\r
+#define AIC_SRCTYPE_EXT_NEGATIVE_EDGE 0x20 /* Negative Edge */\r
+#define AIC_SRCTYPE_EXT_HIGH_LEVEL 0x40 /* High Level */\r
+#define AIC_SRCTYPE_EXT_POSITIVE_EDGE 0x60 /* Positive Edge */\r
+\r
+/*------------------------------------*/\r
+/* AIC_ISR: Interrupt Status Register */\r
+/*------------------------------------*/\r
+\r
+#define AIC_IRQID 0x1F /* Current source interrupt */\r
+\r
+/*------------------------------------------*/\r
+/* AIC_CISR: Interrupt Core Status Register */\r
+/*------------------------------------------*/\r
+\r
+#define AIC_NFIQ 0x01 /* Core FIQ Status */\r
+#define AIC_NIRQ 0x02 /* Core IRQ Status */\r
+\r
+/*-------------------------------*/\r
+/* Advanced Interrupt Controller */\r
+/*-------------------------------*/\r
+#define AIC_BASE ((StructAIC *)0xFFFFF000)\r
+\r
+#endif /* aic_h */\r
--- /dev/null
+MEMORY \r
+{\r
+ ram : ORIGIN = 0x00000000, LENGTH = 256K\r
+}\r
+\r
+__stack_end__ = 0x00000000 + 256K - 4;\r
+\r
+SECTIONS \r
+{\r
+ . = 0;\r
+ startup : { *(.startup)} >ram\r
+\r
+ prog : \r
+ {\r
+ *(.text)\r
+ *(.rodata)\r
+ *(.rodata*)\r
+ *(.glue_7)\r
+ *(.glue_7t)\r
+ } >ram\r
+\r
+ __end_of_text__ = .;\r
+\r
+ .data : \r
+ {\r
+ __data_beg__ = .;\r
+ __data_beg_src__ = __end_of_text__;\r
+ *(.data)\r
+ __data_end__ = .;\r
+ } >ram\r
+\r
+ .bss : \r
+ {\r
+ __bss_beg__ = .;\r
+ *(.bss)\r
+ } >ram\r
+\r
+ /* Align here to ensure that the .bss section occupies space up to\r
+ _end. Align after .bss to ensure correct alignment even if the\r
+ .bss section disappears because there are no input sections. */\r
+ . = ALIGN(32 / 8);\r
+}\r
+ . = ALIGN(32 / 8);\r
+ _end = .;\r
+ _bss_end__ = . ; __bss_end__ = . ; __end__ = . ;\r
+ PROVIDE (end = .);\r
+\r
+\r
--- /dev/null
+MEMORY \r
+{\r
+ flash : ORIGIN = 0x00000000, LENGTH = 2048K\r
+ ram : ORIGIN = 0x00300000, LENGTH = 256K\r
+}\r
+\r
+__stack_end__ = 0x00300000 + 256K - 4;\r
+\r
+SECTIONS \r
+{\r
+ . = 0;\r
+ startup : { *(.startup)} >flash\r
+\r
+ prog : \r
+ {\r
+ *(.text)\r
+ *(.rodata)\r
+ *(.rodata*)\r
+ *(.glue_7)\r
+ *(.glue_7t)\r
+ } >flash\r
+\r
+ __end_of_text__ = .;\r
+\r
+ .data : \r
+ {\r
+ __data_beg__ = .;\r
+ __data_beg_src__ = __end_of_text__;\r
+ *(.data)\r
+ __data_end__ = .;\r
+ } >ram AT>flash\r
+\r
+ .bss : \r
+ {\r
+ __bss_beg__ = .;\r
+ *(.bss)\r
+ } >ram\r
+\r
+ /* Align here to ensure that the .bss section occupies space up to\r
+ _end. Align after .bss to ensure correct alignment even if the\r
+ .bss section disappears because there are no input sections. */\r
+ . = ALIGN(32 / 8);\r
+}\r
+ . = ALIGN(32 / 8);\r
+ _end = .;\r
+ _bss_end__ = . ; __bss_end__ = . ; __end__ = . ;\r
+ PROVIDE (end = .);\r
+\r
+\r
--- /dev/null
+ /* Sample initialization file */\r
+\r
+ .extern main\r
+ .extern exit\r
+\r
+ .text\r
+ .code 32\r
+\r
+\r
+ .align 0\r
+\r
+ .extern __bss_beg__\r
+ .extern __bss_end__\r
+ .extern __stack_end__\r
+ .extern __data_beg__\r
+ .extern __data_end__\r
+ .extern __data+beg_src__\r
+\r
+ .global start\r
+ .global endless_loop\r
+\r
+ /* Stack Sizes */\r
+ .set UND_STACK_SIZE, 0x00000004\r
+ .set ABT_STACK_SIZE, 0x00000004\r
+ .set FIQ_STACK_SIZE, 0x00000004\r
+ .set IRQ_STACK_SIZE, 0X00000400\r
+ .set SVC_STACK_SIZE, 0x00000400\r
+\r
+ /* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */\r
+ .set MODE_USR, 0x10 /* User Mode */\r
+ .set MODE_FIQ, 0x11 /* FIQ Mode */\r
+ .set MODE_IRQ, 0x12 /* IRQ Mode */\r
+ .set MODE_SVC, 0x13 /* Supervisor Mode */\r
+ .set MODE_ABT, 0x17 /* Abort Mode */\r
+ .set MODE_UND, 0x1B /* Undefined Mode */\r
+ .set MODE_SYS, 0x1F /* System Mode */\r
+\r
+ .equ I_BIT, 0x80 /* when I bit is set, IRQ is disabled */\r
+ .equ F_BIT, 0x40 /* when F bit is set, FIQ is disabled */\r
+\r
+\r
+start:\r
+_start:\r
+_mainCRTStartup:\r
+\r
+ /* Setup a stack for each mode - note that this only sets up a usable stack\r
+ for system/user, SWI and IRQ modes. Also each mode is setup with\r
+ interrupts initially disabled. */\r
+ ldr r0, .LC6\r
+ msr CPSR_c, #MODE_UND|I_BIT|F_BIT /* Undefined Instruction Mode */\r
+ mov sp, r0\r
+ sub r0, r0, #UND_STACK_SIZE\r
+ msr CPSR_c, #MODE_ABT|I_BIT|F_BIT /* Abort Mode */\r
+ mov sp, r0\r
+ sub r0, r0, #ABT_STACK_SIZE\r
+ msr CPSR_c, #MODE_FIQ|I_BIT|F_BIT /* FIQ Mode */\r
+ mov sp, r0\r
+ sub r0, r0, #FIQ_STACK_SIZE\r
+ msr CPSR_c, #MODE_IRQ|I_BIT|F_BIT /* IRQ Mode */\r
+ mov sp, r0\r
+ sub r0, r0, #IRQ_STACK_SIZE\r
+ msr CPSR_c, #MODE_SVC|I_BIT|F_BIT /* Supervisor Mode */\r
+ mov sp, r0\r
+ sub r0, r0, #SVC_STACK_SIZE\r
+ msr CPSR_c, #MODE_SYS|I_BIT|F_BIT /* System Mode */\r
+ mov sp, r0\r
+\r
+ /* We want to start in supervisor mode. Operation will switch to system\r
+ mode when the first task starts. */\r
+ msr CPSR_c, #MODE_SVC|I_BIT|F_BIT\r
+\r
+ /* Clear BSS. */\r
+\r
+ mov a2, #0 /* Fill value */\r
+ mov fp, a2 /* Null frame pointer */\r
+ mov r7, a2 /* Null frame pointer for Thumb */\r
+\r
+ ldr r1, .LC1 /* Start of memory block */\r
+ ldr r3, .LC2 /* End of memory block */\r
+ subs r3, r3, r1 /* Length of block */\r
+ beq .end_clear_loop\r
+ mov r2, #0\r
+\r
+.clear_loop:\r
+ strb r2, [r1], #1\r
+ subs r3, r3, #1\r
+ bgt .clear_loop\r
+\r
+.end_clear_loop:\r
+\r
+ /* Initialise data. */\r
+\r
+ ldr r1, .LC3 /* Start of memory block */\r
+ ldr r2, .LC4 /* End of memory block */\r
+ ldr r3, .LC5\r
+ subs r3, r3, r1 /* Length of block */\r
+ beq .end_set_loop\r
+\r
+.set_loop:\r
+ ldrb r4, [r2], #1\r
+ strb r4, [r1], #1\r
+ subs r3, r3, #1\r
+ bgt .set_loop\r
+\r
+.end_set_loop:\r
+\r
+ mov r0, #0 /* no arguments */\r
+ mov r1, #0 /* no argv either */\r
+\r
+ bl main\r
+\r
+endless_loop:\r
+ b endless_loop\r
+\r
+\r
+ .align 0\r
+\r
+ .LC1:\r
+ .word __bss_beg__\r
+ .LC2:\r
+ .word __bss_end__\r
+ .LC3:\r
+ .word __data_beg__\r
+ .LC4:\r
+ .word __data_beg_src__\r
+ .LC5:\r
+ .word __data_end__\r
+ .LC6:\r
+ .word __stack_end__\r
+\r
+\r
+ /* Setup vector table. Note that undf, pabt, dabt, fiq just execute\r
+ a null loop. */\r
+\r
+.section .startup,"ax"\r
+ .code 32\r
+ .align 0\r
+\r
+ b _start /* reset - _start */\r
+ ldr pc, _undf /* undefined - _undf */\r
+ ldr pc, _swi /* SWI - _swi */\r
+ ldr pc, _pabt /* program abort - _pabt */\r
+ ldr pc, _dabt /* data abort - _dabt */\r
+ nop /* reserved */\r
+ ldr pc, [pc,#-0xF20] /* IRQ - read the AIC */\r
+ ldr pc, _fiq /* FIQ - _fiq */\r
+\r
+_undf: .word __undf /* undefined */\r
+_swi: .word vPortYieldProcessor /* SWI */\r
+_pabt: .word __pabt /* program abort */\r
+_dabt: .word __dabt /* data abort */\r
+_fiq: .word __fiq /* FIQ */\r
+\r
+__undf: b . /* undefined */\r
+__pabt: b . /* program abort */\r
+__dabt: b . /* data abort */\r
+__fiq: b . /* FIQ */\r
--- /dev/null
+//*-----------------------------------------------------------------------------
+//* ATMEL Microcontroller Software Support - ROUSSET -
+//*-----------------------------------------------------------------------------
+//* The software is delivered "AS IS" without warranty or condition of any
+//* kind, either express, implied or statutory. This includes without
+//* limitation any warranty or condition with respect to merchantability or
+//* fitness for any particular purpose, or against the infringements of
+//* intellectual property rights of others.
+//*-----------------------------------------------------------------------------
+//* File Name : ebi.h
+//* Object : External Bus Interface Definition File
+//* Translator : ARM Software Development Toolkit V2.11a
+//*
+//* 1.0 03/11/97 JCZ : Creation
+//* 2.0 21/10/98 JCZ : Clean up
+//*-----------------------------------------------------------------------------
+
+#ifndef ebi_h
+#define ebi_h
+
+/*----------------------------------------*/
+/* Memory Controller Interface Definition */
+/*----------------------------------------*/
+
+typedef struct
+{
+ at91_reg EBI_CSR[8] ; /* Chip Select Register */
+ at91_reg EBI_RCR ; /* Remap Control Register */
+ at91_reg EBI_MCR ; /* Memory Control Register */
+} StructEBI ;
+
+/*-----------------------*/
+/* Chip Select Registers */
+/*-----------------------*/
+
+/* Data Bus Width */
+#define DataBus16 (1<<0)
+#define DataBus8 (2<<0)
+#define DBW (3<<0)
+
+/* Number of Wait States */
+#define B_NWS 2
+#define WaitState1 (0<<B_NWS)
+#define WaitState2 (1<<B_NWS)
+#define WaitState3 (2<<B_NWS)
+#define WaitState4 (3<<B_NWS)
+#define WaitState5 (4<<B_NWS)
+#define WaitState6 (5<<B_NWS)
+#define WaitState7 (6<<B_NWS)
+#define WaitState8 (7<<B_NWS)
+#define NWS (7<<B_NWS)
+
+/* Wait State Enable */
+#define WaitStateDisable (0<<5)
+#define WaitStateEnable (1<<5)
+#define WSE (1<<5)
+
+/* Page size */
+#define PageSize1M (0<<7)
+#define PageSize4M (1<<7)
+#define PageSize16M (2<<7)
+#define PageSize64M (3<<7)
+#define PAGES (3<<7)
+
+/* Number of Data Float Output Time Clock Cycle */
+#define B_TDF 9
+#define tDF_0cycle (0<<B_TDF)
+#define tDF_1cycle (1<<B_TDF)
+#define tDF_2cycle (2<<B_TDF)
+#define tDF_3cycle (3<<B_TDF)
+#define tDF_4cycle (4<<B_TDF)
+#define tDF_5cycle (5<<B_TDF)
+#define tDF_6cycle (6<<B_TDF)
+#define tDF_7cycle (7<<B_TDF)
+#define TDF (7<<B_TDF)
+
+/* Byte Access Type */
+#define ByteWriteAccessType (0<<12)
+#define ByteSelectAccessType (1<<12)
+#define BAT 1<<12)
+
+/* Chip Select Enable */
+#define CSEnable (1<<13)
+#define CSDisable (0<<13)
+#define CSE (1<<13)
+
+#define BA ((u_int)(0xFFF)<<20)
+
+/*-------------------------*/
+/* Memory Control Register */
+/*-------------------------*/
+
+/* Address Line Enable */
+#define ALE (7<<0)
+#define BankSize16M (0<<0)
+#define BankSize8M (4<<0)
+#define BankSize4M (5<<0)
+#define BankSize2M (6<<0)
+#define BankSize1M (7<<0)
+
+/* Data Read Protocol */
+#define StandardReadProtocol (0<<4)
+#define EarlyReadProtocol (1<<4)
+#define DRP (1<<4)
+
+/*------------------------*/
+/* Remap Control Register */
+/*------------------------*/
+
+#define RCB (1<<0)
+
+/*--------------------------------*/
+/* Device Dependancies Definition */
+/*--------------------------------*/
+
+#ifdef AT91M40400
+/* External Bus Interface User Interface BAse Address */
+#define EBI_BASE ((StructEBI *) 0xFFE00000)
+#endif
+
+#endif /* ebi_h */
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* \r
+ NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.\r
+ The processor MUST be in supervisor mode when vTaskStartScheduler is \r
+ called. The demo applications included in the FreeRTOS.org download switch\r
+ to supervisor mode prior to main being called. If you are not using one of\r
+ these demo application projects then ensure Supervisor mode is used.\r
+*/\r
+\r
+\r
+/*\r
+ * Creates all the demo application tasks, then starts the scheduler. The WEB\r
+ * documentation provides more details of the demo application tasks.\r
+ * \r
+ * Main.c also creates a task called "Check". This only executes every three \r
+ * seconds but has the highest priority so is guaranteed to get processor time. \r
+ * Its main function is to check that all the other tasks are still operational.\r
+ * Each task (other than the "flash" tasks) maintains a unique count that is \r
+ * incremented each time the task successfully completes its function. Should \r
+ * any error occur within such a task the count is permanently halted. The \r
+ * check task inspects the count of each task to ensure it has changed since\r
+ * the last time the check task executed. If all the count variables have \r
+ * changed all the tasks are still executing error free, and the check task\r
+ * toggles the onboard LED. Should any task contain an error at any time \r
+ * the LED toggle rate will change from 3 seconds to 500ms.\r
+ *\r
+ * To check the operation of the memory allocator the check task also \r
+ * dynamically creates a task before delaying, and deletes it again when it \r
+ * wakes. If memory cannot be allocated for the new task the call to xTaskCreate\r
+ * will fail and an error is signalled. The dynamically created task itself\r
+ * allocates and frees memory just to give the allocator a bit more exercise.\r
+ *\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdlib.h>\r
+#include <string.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo application includes. */\r
+#include "partest.h"\r
+#include "flash.h"\r
+#include "integer.h"\r
+#include "PollQ.h"\r
+#include "comtest2.h"\r
+#include "semtest.h"\r
+#include "flop.h"\r
+#include "dynamic.h"\r
+#include "BlockQ.h"\r
+#include "serial.h"\r
+\r
+/* Hardware specific definitions. */\r
+#include "aic.h"\r
+#include "ebi.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Constants for the ComTest tasks. */\r
+#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 115200 )\r
+#define mainCOM_TEST_LED ( 5 )\r
+\r
+/* Priorities for the demo application tasks. */\r
+#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 )\r
+#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+\r
+/* The rate at which the on board LED will toggle when there is/is not an \r
+error. */\r
+#define mainNO_ERROR_FLASH_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS )\r
+#define mainERROR_FLASH_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS )\r
+#define mainON_BOARD_LED_BIT ( ( unsigned portLONG ) 7 )\r
+\r
+/* Constants used by the vMemCheckTask() task. */\r
+#define mainCOUNT_INITIAL_VALUE ( ( unsigned portLONG ) 0 )\r
+#define mainNO_TASK ( 0 )\r
+\r
+/* The size of the memory blocks allocated by the vMemCheckTask() task. */\r
+#define mainMEM_CHECK_SIZE_1 ( ( size_t ) 51 )\r
+#define mainMEM_CHECK_SIZE_2 ( ( size_t ) 52 )\r
+#define mainMEM_CHECK_SIZE_3 ( ( size_t ) 151 )\r
+\r
+#define MAX_WAIT_STATES 8\r
+static const unsigned portLONG ululCSRWaitValues[ MAX_WAIT_STATES + 1 ] =\r
+{\r
+ WaitState1,/* There is no "zero wait state" value, so use one wait state */\r
+ WaitState1,\r
+ WaitState2,\r
+ WaitState3,\r
+ WaitState4,\r
+ WaitState5,\r
+ WaitState6,\r
+ WaitState7,\r
+ WaitState8\r
+};\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Checks that all the demo application tasks are still executing without error\r
+ * - as described at the top of the file.\r
+ */\r
+static portLONG prvCheckOtherTasksAreStillRunning( unsigned portLONG ulMemCheckTaskCount );\r
+\r
+/*\r
+ * The task that executes at the highest priority and calls \r
+ * prvCheckOtherTasksAreStillRunning(). See the description at the top\r
+ * of the file.\r
+ */\r
+static void vErrorChecks( void *pvParameters );\r
+\r
+/*\r
+ * Dynamically created and deleted during each cycle of the vErrorChecks()\r
+ * task. This is done to check the operation of the memory allocator.\r
+ * See the top of vErrorChecks for more details.\r
+ */\r
+static void vMemCheckTask( void *pvParameters );\r
+\r
+/*\r
+ * Configure the processor for use with the Olimex demo board. This includes\r
+ * setup for the I/O, system clock, and access timings.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Starts all the other tasks, then starts the scheduler. \r
+ */\r
+int main( void )\r
+{\r
+ /* Setup the hardware for use with the Olimex demo board. */\r
+ prvSetupHardware();\r
+\r
+ /* Start the demo/test application tasks. */\r
+ vStartIntegerMathTasks( tskIDLE_PRIORITY );\r
+ vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED );\r
+ vStartLEDFlashTasks( mainLED_TASK_PRIORITY );\r
+ vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
+ vStartMathTasks( tskIDLE_PRIORITY );\r
+ vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
+ vStartDynamicPriorityTasks(); \r
+ vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
+\r
+ /* Start the check task - which is defined in this file. */\r
+ xTaskCreate( vErrorChecks, ( signed portCHAR * ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
+\r
+ /* Now all the tasks have been started - start the scheduler.\r
+\r
+ NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.\r
+ The processor MUST be in supervisor mode when vTaskStartScheduler is \r
+ called. The demo applications included in the FreeRTOS.org download switch\r
+ to supervisor mode prior to main being called. If you are not using one of\r
+ these demo application projects then ensure Supervisor mode is used here. */\r
+ vTaskStartScheduler();\r
+\r
+ /* Should never reach here! */\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vErrorChecks( void *pvParameters )\r
+{\r
+portTickType xDelayPeriod = mainNO_ERROR_FLASH_PERIOD;\r
+unsigned portLONG ulMemCheckTaskRunningCount;\r
+xTaskHandle xCreatedTask;\r
+\r
+ /* Cycle for ever, delaying then checking all the other tasks are still\r
+ operating without error. If an error is detected then the delay period\r
+ is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so\r
+ the on board LED flash rate will increase. \r
+ \r
+ In addition to the standard tests the memory allocator is tested through\r
+ the dynamic creation and deletion of a task each cycle. Each time the \r
+ task is created memory must be allocated for its stack. When the task is\r
+ deleted this memory is returned to the heap. If the task cannot be created \r
+ then it is likely that the memory allocation failed. */\r
+\r
+ for( ;; )\r
+ {\r
+ /* Reset xCreatedTask. This is modified by the task about to be \r
+ created so we can tell if it is executing correctly or not. */\r
+ xCreatedTask = mainNO_TASK;\r
+\r
+ /* Dynamically create a task - passing ulMemCheckTaskRunningCount as a \r
+ parameter. */\r
+ ulMemCheckTaskRunningCount = mainCOUNT_INITIAL_VALUE; \r
+ if( xTaskCreate( vMemCheckTask, ( signed portCHAR * ) "MEM_CHECK", configMINIMAL_STACK_SIZE, ( void * ) &ulMemCheckTaskRunningCount, tskIDLE_PRIORITY, &xCreatedTask ) != pdPASS )\r
+ {\r
+ /* Could not create the task - we have probably run out of heap. */\r
+ xDelayPeriod = mainERROR_FLASH_PERIOD;\r
+ }\r
+\r
+ /* Delay until it is time to execute again. */\r
+ vTaskDelay( xDelayPeriod );\r
+\r
+ /* Delete the dynamically created task. */\r
+ if( xCreatedTask != mainNO_TASK )\r
+ {\r
+ vTaskDelete( xCreatedTask );\r
+ }\r
+\r
+ /* Check all the standard demo application tasks are executing without \r
+ error. ulMemCheckTaskRunningCount is checked to ensure it was\r
+ modified by the task just deleted. */\r
+ if( prvCheckOtherTasksAreStillRunning( ulMemCheckTaskRunningCount ) != pdPASS )\r
+ {\r
+ /* An error has been detected in one of the tasks - flash faster. */\r
+ xDelayPeriod = mainERROR_FLASH_PERIOD;\r
+ }\r
+\r
+ /* The toggle rate of the LED depends on how long this task delays for.\r
+ An error reduces the delay period and so increases the toggle rate. */\r
+ vParTestToggleLED( mainON_BOARD_LED_BIT );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+portLONG lCount;\r
+\r
+ #ifdef RUN_FROM_ROM\r
+ {\r
+ portFLOAT nsecsPerClockTick;\r
+ portLONG lNumWaitStates;\r
+ unsigned portLONG ulCSRWaitValue;\r
+\r
+ /* We are compiling to run from ROM (either on-chip or off-chip flash).\r
+ Leave the RAM/flash mapped the way they are on reset\r
+ (flash @ 0x00000000, RAM @ 0x00300000), and set up the\r
+ proper flash wait states (starts out at the maximum number\r
+ of wait states on reset, so we should be able to reduce it).\r
+ Most of this code will probably get removed by the compiler\r
+ if optimization is enabled, since these calculations are\r
+ based on constants. But the compiler should still produce\r
+ a correct wait state register value. */\r
+ nsecsPerClockTick = ( portFLOAT ) 1000000000 / configCPU_CLOCK_HZ;\r
+ lNumWaitStates = ( portLONG )( ( configFLASH_SPEED_NSEC / nsecsPerClockTick ) + 0.5 ) - 1;\r
+\r
+ if( lNumWaitStates < 0 )\r
+ {\r
+ lNumWaitStates = 0;\r
+ }\r
+\r
+ if( lNumWaitStates > MAX_WAIT_STATES )\r
+ {\r
+ lNumWaitStates = MAX_WAIT_STATES;\r
+ }\r
+\r
+ ulCSRWaitValue = ululCSRWaitValues[ lNumWaitStates ];\r
+ ulCSRWaitValue = WaitState5;\r
+\r
+ AT91C_BASE_EBI->EBI_CSR[ 0 ] = ulCSRWaitValue | DataBus16 | WaitStateEnable\r
+ | PageSize1M | tDF_0cycle \r
+ | ByteWriteAccessType | CSEnable\r
+ | 0x00000000 /* Base Address */;\r
+ }\r
+ #else /* else we are compiling to run from on-chip RAM */\r
+ {\r
+ /* If compiling to run from RAM, we expect the on-chip RAM to already\r
+ be mapped at 0x00000000. This is typically done with an initialization\r
+ script for the JTAG emulator you are using to download and run the\r
+ demo application. So there is nothing to do here in this case. */\r
+ }\r
+ #endif\r
+\r
+ /* Disable all interrupts at the AIC level initially... */\r
+ AT91C_BASE_AIC->AIC_IDCR = 0xFFFFFFFF;\r
+\r
+ /* Set all SVR and SMR entries to default values (start with a clean slate)... */\r
+ for( lCount = 0; lCount < 32; lCount++ )\r
+ {\r
+ AT91C_BASE_AIC->AIC_SVR[ lCount ] = (unsigned long) 0;\r
+ AT91C_BASE_AIC->AIC_SMR[ lCount ] = AIC_SRCTYPE_INT_EDGE_TRIGGERED;\r
+ }\r
+\r
+ /* Disable clocks to all peripherals initially... */\r
+ AT91C_BASE_PS->PS_PCDR = 0xFFFFFFFF;\r
+\r
+ /* Clear all interrupts at the AIC level initially... */\r
+ AT91C_BASE_AIC->AIC_ICCR = 0xFFFFFFFF;\r
+\r
+ /* Perform 8 "End Of Interrupt" cmds to make sure AIC will not Lock out \r
+ nIRQ */\r
+ for( lCount = 0; lCount < 8; lCount++ )\r
+ {\r
+ AT91C_BASE_AIC->AIC_EOICR = 0;\r
+ }\r
+\r
+ /* Initialise LED outputs. */\r
+ vParTestInitialise();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portLONG prvCheckOtherTasksAreStillRunning( unsigned portLONG ulMemCheckTaskCount )\r
+{\r
+portLONG lReturn = ( portLONG ) pdPASS;\r
+\r
+ /* Check all the demo tasks (other than the flash tasks) to ensure\r
+ that they are all still running, and that none of them have detected\r
+ an error. */\r
+\r
+ if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ lReturn = ( portLONG ) pdFAIL;\r
+ }\r
+\r
+ if( xAreComTestTasksStillRunning() != pdTRUE )\r
+ {\r
+ lReturn = ( portLONG ) pdFAIL;\r
+ }\r
+\r
+ if( xArePollingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ lReturn = ( portLONG ) pdFAIL;\r
+ }\r
+\r
+ if( xAreMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ lReturn = ( portLONG ) pdFAIL;\r
+ }\r
+\r
+ if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ lReturn = ( portLONG ) pdFAIL;\r
+ }\r
+\r
+ if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )\r
+ {\r
+ lReturn = ( portLONG ) pdFAIL;\r
+ }\r
+\r
+ if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ lReturn = ( portLONG ) pdFAIL;\r
+ }\r
+\r
+ if( ulMemCheckTaskCount == mainCOUNT_INITIAL_VALUE )\r
+ {\r
+ /* The vMemCheckTask did not increment the counter - it must\r
+ have failed. */\r
+ lReturn = ( portLONG ) pdFAIL;\r
+ }\r
+\r
+ return lReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vMemCheckTask( void *pvParameters )\r
+{\r
+unsigned portLONG *pulMemCheckTaskRunningCounter;\r
+void *pvMem1, *pvMem2, *pvMem3;\r
+static portLONG lErrorOccurred = pdFALSE;\r
+\r
+ /* This task is dynamically created then deleted during each cycle of the\r
+ vErrorChecks task to check the operation of the memory allocator. Each time\r
+ the task is created memory is allocated for the stack and TCB. Each time\r
+ the task is deleted this memory is returned to the heap. This task itself\r
+ exercises the allocator by allocating and freeing blocks. \r
+ \r
+ The task executes at the idle priority so does not require a delay. \r
+ \r
+ pulMemCheckTaskRunningCounter is incremented each cycle to indicate to the\r
+ vErrorChecks() task that this task is still executing without error. */\r
+\r
+ pulMemCheckTaskRunningCounter = ( unsigned portLONG * ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ if( lErrorOccurred == pdFALSE )\r
+ {\r
+ /* We have never seen an error so increment the counter. */\r
+ ( *pulMemCheckTaskRunningCounter )++;\r
+ }\r
+ else\r
+ {\r
+ /* There has been an error so reset the counter so the check task \r
+ can tell that an error occurred. */\r
+ *pulMemCheckTaskRunningCounter = mainCOUNT_INITIAL_VALUE;\r
+ }\r
+\r
+ /* Allocate some memory - just to give the allocator some extra \r
+ exercise. This has to be in a critical section to ensure the\r
+ task does not get deleted while it has memory allocated. */\r
+ vTaskSuspendAll();\r
+ {\r
+ pvMem1 = pvPortMalloc( mainMEM_CHECK_SIZE_1 );\r
+ if( pvMem1 == NULL )\r
+ {\r
+ lErrorOccurred = pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ memset( pvMem1, 0xaa, mainMEM_CHECK_SIZE_1 );\r
+ vPortFree( pvMem1 );\r
+ }\r
+ }\r
+ xTaskResumeAll();\r
+\r
+ /* Again - with a different size block. */\r
+ vTaskSuspendAll();\r
+ {\r
+ pvMem2 = pvPortMalloc( mainMEM_CHECK_SIZE_2 );\r
+ if( pvMem2 == NULL )\r
+ {\r
+ lErrorOccurred = pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ memset( pvMem2, 0xaa, mainMEM_CHECK_SIZE_2 );\r
+ vPortFree( pvMem2 );\r
+ }\r
+ }\r
+ xTaskResumeAll();\r
+\r
+ /* Again - with a different size block. */\r
+ vTaskSuspendAll();\r
+ {\r
+ pvMem3 = pvPortMalloc( mainMEM_CHECK_SIZE_3 );\r
+ if( pvMem3 == NULL )\r
+ {\r
+ lErrorOccurred = pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ memset( pvMem3, 0xaa, mainMEM_CHECK_SIZE_3 );\r
+ vPortFree( pvMem3 );\r
+ }\r
+ }\r
+ xTaskResumeAll();\r
+ }\r
+}\r
+\r
--- /dev/null
+//*---------------------------------------------------------------------------
+//* ATMEL Microcontroller Software Support - ROUSSET -
+//*---------------------------------------------------------------------------
+//* The software is delivered "AS IS" without warranty or condition of any
+//* kind, either express, implied or statutory. This includes without
+//* limitation any warranty or condition with respect to merchantability or
+//* fitness for any particular purpose, or against the infringements of
+//* intellectual property rights of others.
+//*-----------------------------------------------------------------------------
+//* File Name : pio.h
+//* Object : Parallel I/O Definition File
+//* Translator : ARM Software Development Toolkit V2.11a
+//*
+//* 1.0 20/10/97 JCZ : Creation
+//* 2.0 21/10/98 JCZ : Clean up
+//*---------------------------------------------------------------------------
+
+#ifndef pio_h
+#define pio_h
+
+/*---------------------------------------------*/
+/* Parallel I/O Interface Structure Definition */
+/*---------------------------------------------*/
+
+typedef struct
+{
+ at91_reg PIO_PER ; /* PIO Enable Register */
+ at91_reg PIO_PDR ; /* PIO Disable Register */
+ at91_reg PIO_PSR ; /* PIO Status Register */
+ at91_reg Reserved0 ;
+ at91_reg PIO_OER ; /* Output Enable Register */
+ at91_reg PIO_ODR ; /* Output Disable Register */
+ at91_reg PIO_OSR ; /* Output Status Register */
+ at91_reg Reserved1 ;
+ at91_reg PIO_IFER ; /* Input Filter Enable Register */
+ at91_reg PIO_IFDR ; /* Input Filter Disable Register */
+ at91_reg PIO_IFSR ; /* Input Filter Status Register */
+ at91_reg Reserved2 ;
+ at91_reg PIO_SODR ; /* Set Output Data Register */
+ at91_reg PIO_CODR ; /* Clear Output Data Register */
+ at91_reg PIO_ODSR ; /* Output Data Status Register */
+ at91_reg PIO_PDSR ; /* Pin Data Status Register */
+ at91_reg PIO_IER ; /* Interrupt Enable Register */
+ at91_reg PIO_IDR ; /* Interrupt Disable Register */
+ at91_reg PIO_IMR ; /* Interrupt Mask Register */
+ at91_reg PIO_ISR ; /* Interrupt Status Register */
+} StructPIO ;
+
+/*-----------------------------*/
+/* PIO Handler type definition */
+/*-----------------------------*/
+
+//typedef void (*TypePIOHandler) ( StructPIO *pio_pt, u_int pio_mask ) ;
+
+/*--------------------------------*/
+/* Device Dependancies Definition */
+/*--------------------------------*/
+
+/* Number of PIO Controller */
+#define NB_PIO_CTRL 1
+/* Base Address */
+#define PIO_BASE ((StructPIO *) 0xFFFF0000 )
+/* Number of PIO Lines */
+#define NB_PIO 32
+
+/* Parallel I/O Bits Definition */
+#define P0 (1<<0)
+#define P1 (1<<1)
+#define P2 (1<<2)
+#define P3 (1<<3)
+#define P4 (1<<4)
+#define P5 (1<<5)
+#define P6 (1<<6)
+#define P7 (1<<7)
+#define P8 (1<<8)
+#define P9 (1<<9)
+#define P10 (1<<10)
+#define P11 (1<<11)
+#define P12 (1<<12)
+#define P13 (1<<13)
+#define P14 (1<<14)
+#define P15 (1<<15)
+#define P16 (1<<16)
+#define P17 (1<<17)
+#define P18 (1<<18)
+#define P19 (1<<19)
+#define P20 (1<<20)
+#define P21 (1<<21)
+#define P22 (1<<22)
+#define P23 (1<<23)
+#define P24 (1<<24)
+#define P25 (1<<25)
+#define P26 (1<<26)
+#define P27 (1<<27)
+#define P28 (1<<28)
+#define P29 (1<<29)
+#define P30 (1<<30)
+#define P31 (1<<31)
+
+/* PIO Multiplexing Definition */
+
+/* There is only one PIO Controller */
+#define PIO_CTRL 0
+
+#define PIO_TC0 PIO_CTRL
+#define TCLK0 P0
+#define TIOA0 P1
+#define TIOB0 P2
+#define PIN_TC0 (TIOA0|TIOB0|TCLK0)
+
+#define PIO_TC1 PIO_CTRL
+#define TCLK1 P3
+#define TIOA1 P4
+#define TIOB1 P5
+#define PIN_TC1 (TIOA1|TIOB1|TCLK1)
+
+#define PIO_TC2 PIO_CTRL
+#define TCLK2 P6
+#define TIOA2 P7
+#define TIOB2 P8
+#define PIN_TC2 (TIOA2|TIOB2|TCLK2)
+
+#define PIO_EXT_IRQ PIO_CTRL
+#define PIN_IRQ0 P9
+#define PIN_IRQ1 P10
+#define PIN_IRQ2 P11
+#define PIN_FIQ P12
+
+#define PIO_USART0 PIO_CTRL
+#define SCK0 P13
+#define TXD0 P14
+#define RXD0 P15
+#define PIN_USART0 (SCK0|TXD0|RXD0)
+
+#define PIO_USART1 PIO_CTRL
+#define SCK1 P20
+#define TXD1 P21
+#define RXD1 P22
+#define PIN_USART1 (SCK1|TXD1|RXD1)
+
+#define MCKO P25
+#define CS2 P26
+#define CS3 P27
+#define CS4 P31
+#define CS5 P30
+#define CS6 P29
+#define CS7 P28
+
+#endif /* pio_h */
--- /dev/null
+set USE_THUMB_MODE=NO\r
+set DEBUG=-g\r
+set OPTIM=-O0\r
+set RUN_MODE=RUN_FROM_RAM\r
+set LDSCRIPT=atmel-ram.ld\r
+make\r
--- /dev/null
+set USE_THUMB_MODE=YES\r
+set DEBUG=-g\r
+set OPTIM=-O0\r
+set RUN_MODE=RUN_FROM_RAM\r
+set LDSCRIPT=atmel-ram.ld\r
+make\r
--- /dev/null
+set USE_THUMB_MODE=NO\r
+set DEBUG=-g\r
+set OPTIM=-O2\r
+set RUN_MODE=RUN_FROM_ROM\r
+set LDSCRIPT=atmel-rom.ld\r
+make\r
--- /dev/null
+set USE_THUMB_MODE=YES\r
+set DEBUG=-g\r
+set OPTIM=-O2\r
+set RUN_MODE=RUN_FROM_ROM\r
+set LDSCRIPT=atmel-rom.ld\r
+make\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* \r
+ BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR USART0. \r
+\r
+ This file contains all the serial port components that can be compiled to\r
+ either ARM or THUMB mode. Components that must be compiled to ARM mode are\r
+ contained in serialISR.c.\r
+*/\r
+\r
+/* Standard includes. */\r
+#include <stdlib.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "queue.h"\r
+#include "task.h"\r
+\r
+/* Demo application includes. */\r
+#include "serial.h"\r
+#include "AT91R40008.h"\r
+#include "usart.h"\r
+#include "pio.h"\r
+#include "aic.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Constants to setup and access the UART. */\r
+#define portUSART0_AIC_CHANNEL ( ( unsigned portLONG ) 2 )\r
+\r
+#define serINVALID_QUEUE ( ( xQueueHandle ) 0 )\r
+#define serHANDLE ( ( xComPortHandle ) 1 )\r
+#define serNO_BLOCK ( ( portTickType ) 0 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Queues used to hold received characters, and characters waiting to be\r
+transmitted. */\r
+static xQueueHandle xRxedChars; \r
+static xQueueHandle xCharsForTx; \r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* \r
+ * The queues are created in serialISR.c as they are used from the ISR.\r
+ * Obtain references to the queues and THRE Empty flag. \r
+ */\r
+extern void vSerialISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxRxedChars, xQueueHandle *pxCharsForTx );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )\r
+{\r
+unsigned portLONG ulSpeed;\r
+unsigned portLONG ulCD;\r
+xComPortHandle xReturn = serHANDLE;\r
+extern void ( vUART_ISR )( void );\r
+\r
+ /* The queues are used in the serial ISR routine, so are created from\r
+ serialISR.c (which is always compiled to ARM mode. */\r
+ vSerialISRCreateQueues( uxQueueLength, &xRxedChars, &xCharsForTx );\r
+\r
+ if( \r
+ ( xRxedChars != serINVALID_QUEUE ) && \r
+ ( xCharsForTx != serINVALID_QUEUE ) && \r
+ ( ulWantedBaud != ( unsigned portLONG ) 0 ) \r
+ )\r
+ {\r
+ portENTER_CRITICAL();\r
+ {\r
+ /* Enable clock to USART0... */\r
+ AT91C_BASE_PS->PS_PCER = AT91C_PS_US0;\r
+\r
+ /* Disable all USART0 interrupt sources to begin... */\r
+ AT91C_BASE_US0->US_IDR = 0xFFFFFFFF;\r
+\r
+ /* Reset various status bits (just in case)... */\r
+ AT91C_BASE_US0->US_CR = US_RSTSTA;\r
+\r
+ AT91C_BASE_PIO->PIO_PDR = TXD0 | RXD0; /* Enable RXD and TXD pins */\r
+ AT91C_BASE_US0->US_CR = US_RSTRX | US_RSTTX | US_RXDIS | US_TXDIS;\r
+\r
+ /* Clear Transmit and Receive Counters */\r
+ AT91C_BASE_US0->US_RCR = 0;\r
+ AT91C_BASE_US0->US_TCR = 0;\r
+\r
+ /* Input clock to baud rate generator is MCK */\r
+ ulSpeed = configCPU_CLOCK_HZ * 10; \r
+ ulSpeed = ulSpeed / 16;\r
+ ulSpeed = ulSpeed / ulWantedBaud;\r
+ \r
+ /* compute the error */\r
+ ulCD = ulSpeed / 10;\r
+ if ((ulSpeed - (ulCD * 10)) >= 5)\r
+ ulCD++;\r
+\r
+ /* Define the baud rate divisor register */\r
+ AT91C_BASE_US0->US_BRGR = ulCD;\r
+\r
+ /* Define the USART mode */\r
+ AT91C_BASE_US0->US_MR = US_CLKS_MCK | US_CHRL_8 | US_PAR_NO | US_NBSTOP_1 | US_CHMODE_NORMAL;\r
+\r
+ /* Write the Timeguard Register */\r
+ AT91C_BASE_US0->US_TTGR = 0;\r
+\r
+ /* Setup the interrupt for USART0.\r
+\r
+ Store interrupt handler function address in USART0 vector register... */\r
+ AT91C_BASE_AIC->AIC_SVR[ portUSART0_AIC_CHANNEL ] = (unsigned long)vUART_ISR;\r
+ \r
+ /* USART0 interrupt level-sensitive, priority 1... */\r
+ AT91C_BASE_AIC->AIC_SMR[ portUSART0_AIC_CHANNEL ] = AIC_SRCTYPE_INT_LEVEL_SENSITIVE | 1;\r
+ \r
+ /* Clear some pending USART0 interrupts (just in case)... */\r
+ AT91C_BASE_US0->US_CR = US_RSTSTA;\r
+\r
+ /* Enable USART0 interrupt sources (but not Tx for now)... */\r
+ AT91C_BASE_US0->US_IER = US_RXRDY;\r
+\r
+ /* Enable USART0 interrupts in the AIC... */\r
+ AT91C_BASE_AIC->AIC_IECR = ( 1 << portUSART0_AIC_CHANNEL );\r
+\r
+ /* Enable receiver and transmitter... */\r
+ AT91C_BASE_US0->US_CR = US_RXEN | US_TXEN;\r
+ }\r
+ portEXIT_CRITICAL();\r
+ }\r
+ else\r
+ {\r
+ xReturn = ( xComPortHandle ) 0;\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )\r
+{\r
+ /* The port handle is not required as this driver only supports UART0. */\r
+ ( void ) pxPort;\r
+\r
+ /* Get the next character from the buffer. Return false if no characters\r
+ are available, or arrive before xBlockTime expires. */\r
+ if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )\r
+ {\r
+ return pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ return pdFALSE;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength )\r
+{\r
+signed portCHAR *pxNext;\r
+\r
+ /* NOTE: This implementation does not handle the queue being full as no\r
+ block time is used! */\r
+\r
+ /* The port handle is not required as this driver only supports UART0. */\r
+ ( void ) pxPort;\r
+\r
+ /* Send each character in the string, one at a time. */\r
+ pxNext = ( signed portCHAR * ) pcString;\r
+ while( *pxNext )\r
+ {\r
+ xSerialPutChar( pxPort, *pxNext, serNO_BLOCK );\r
+ pxNext++;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )\r
+{\r
+ /* Place the character in the queue of characters to be transmitted. */\r
+ if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )\r
+ {\r
+ return pdFAIL;\r
+ }\r
+\r
+ /* Turn on the Tx interrupt so the ISR will remove the character from the\r
+ queue and send it. This does not need to be in a critical section as\r
+ if the interrupt has already removed the character the next interrupt\r
+ will simply turn off the Tx interrupt again. */\r
+ AT91C_BASE_US0->US_IER = US_TXRDY;\r
+\r
+ return pdPASS;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSerialClose( xComPortHandle xPort )\r
+{\r
+ /* Not supported as not required by the demo application. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+\r
+/* \r
+ BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR USART0. \r
+\r
+ This file contains all the serial port components that must be compiled\r
+ to ARM mode. The components that can be compiled to either ARM or THUMB\r
+ mode are contained in serial.c.\r
+\r
+*/\r
+\r
+/* Standard includes. */\r
+#include <stdlib.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "queue.h"\r
+#include "task.h"\r
+\r
+/* Demo application includes. */\r
+#include "serial.h"\r
+#include "AT91R40008.h"\r
+#include "usart.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Constant to access the AIC. */\r
+#define serCLEAR_AIC_INTERRUPT ( ( unsigned portLONG ) 0 )\r
+\r
+/* Constants to determine the ISR source. */\r
+#define serSOURCE_THRE ( ( unsigned portCHAR ) 0x02 )\r
+#define serSOURCE_RX_TIMEOUT ( ( unsigned portCHAR ) 0x0c )\r
+#define serSOURCE_ERROR ( ( unsigned portCHAR ) 0x06 )\r
+#define serSOURCE_RX ( ( unsigned portCHAR ) 0x04 )\r
+#define serINTERRUPT_SOURCE_MASK ( ( unsigned portLONG ) (US_RXRDY | US_TXRDY | US_RXBRK | US_OVRE | US_FRAME | US_PARE) )\r
+\r
+/* Queues used to hold received characters, and characters waiting to be\r
+transmitted. */\r
+static xQueueHandle xRxedChars; \r
+static xQueueHandle xCharsForTx; \r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* UART0 interrupt service routine. This can cause a context switch so MUST\r
+be declared "naked". */\r
+void vUART_ISR( void ) __attribute__ ((naked));\r
+\r
+/*-----------------------------------------------------------*/\r
+void vSerialISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxRxedChars, xQueueHandle *pxCharsForTx )\r
+{\r
+ /* Create the queues used to hold Rx and Tx characters. */\r
+ xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );\r
+ xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );\r
+\r
+ /* Pass back a reference to the queues so the serial API file can \r
+ post/receive characters. */\r
+ *pxRxedChars = xRxedChars;\r
+ *pxCharsForTx = xCharsForTx;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vUART_ISR( void )\r
+{\r
+ /* This ISR can cause a context switch, so the first statement must be a\r
+ call to the portENTER_SWITCHING_ISR() macro. This must be BEFORE any\r
+ variable declarations. */\r
+ portENTER_SWITCHING_ISR();\r
+\r
+ /* Now we can declare the local variables. */\r
+ signed portCHAR cChar;\r
+ portBASE_TYPE xTaskWokenByTx = pdFALSE, xTaskWokenByRx = pdFALSE;\r
+ unsigned portLONG ulStatus;\r
+\r
+ /* What caused the interrupt? */\r
+ ulStatus = AT91C_BASE_US0->US_CSR & AT91C_BASE_US0->US_IMR;\r
+\r
+ if (ulStatus & US_TXRDY)\r
+ {\r
+ /* The interrupt was caused by the THR becoming empty. Are there any\r
+ more characters to transmit? */\r
+ if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWokenByTx ) == pdTRUE )\r
+ {\r
+ /* A character was retrieved from the queue so can be sent to the\r
+ THR now. */\r
+ AT91C_BASE_US0->US_THR = cChar;\r
+ }\r
+ else\r
+ {\r
+ /* Queue empty, nothing to send so turn off the Tx interrupt. */\r
+ AT91C_BASE_US0->US_IDR = US_TXRDY;\r
+ } \r
+ }\r
+\r
+ if (ulStatus & US_RXRDY)\r
+ {\r
+ /* The interrupt was caused by the receiver getting data. */\r
+ cChar = AT91C_BASE_US0->US_RHR;\r
+\r
+ if (xQueueSendFromISR(xRxedChars, &cChar, pdFALSE))\r
+ {\r
+ xTaskWokenByRx = pdTRUE;\r
+ }\r
+ }\r
+\r
+ // Acknowledge the interrupt at AIC level...\r
+ AT91C_BASE_AIC->AIC_EOICR = serCLEAR_AIC_INTERRUPT;\r
+\r
+ /* Exit the ISR. If a task was woken by either a character being received\r
+ or transmitted then a context switch will occur. */\r
+ portEXIT_SWITCHING_ISR( ( xTaskWokenByTx || xTaskWokenByRx ) );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+//*----------------------------------------------------------------------------\r
+//* ATMEL Microcontroller Software Support - ROUSSET -\r
+//*----------------------------------------------------------------------------\r
+//* The software is delivered "AS IS" without warranty or condition of any\r
+//* kind, either express, implied or statutory. This includes without\r
+//* limitation any warranty or condition with respect to merchantability or\r
+//* fitness for any particular purpose, or against the infringements of\r
+//* intellectual property rights of others.\r
+//*-----------------------------------------------------------------------------\r
+//* File Name : tc.h\r
+//* Object : Timer Counter Header File\r
+//*\r
+//* 1.0 01/04/00 JCZ : Creation\r
+//* 1.0 01/09/00 JPP : modification TC_BEEVT, TC_BEEVT_SET_OUTPUT,\r
+//* TC_BEEVT_CLEAR_OUTPUT, TC_BEEVT_TOGGLE_OUTPUT\r
+//*-----------------------------------------------------------------------------\r
+\r
+#ifndef tc_h\r
+#define tc_h\r
+\r
+//#include "periph/stdc/std_c.h"\r
+//#include "periph/pio/lib_pio.h"\r
+\r
+/*-------------------------------------------*/\r
+/* Timer User Interface Structure Definition */\r
+/*-------------------------------------------*/\r
+\r
+typedef struct\r
+{\r
+ at91_reg TC_CCR ; /* Control Register */\r
+ at91_reg TC_CMR ; /* Mode Register */\r
+ at91_reg Reserved0 ;\r
+ at91_reg Reserved1 ;\r
+ at91_reg TC_CV ; /* Counter value */\r
+ at91_reg TC_RA ; /* Register A */\r
+ at91_reg TC_RB ; /* Register B */\r
+ at91_reg TC_RC ; /* Register C */\r
+ at91_reg TC_SR ; /* Status Register */\r
+ at91_reg TC_IER ; /* Interrupt Enable Register */\r
+ at91_reg TC_IDR ; /* Interrupt Disable Register */\r
+ at91_reg TC_IMR ; /* Interrupt Mask Register */\r
+ at91_reg Reserved2 ;\r
+ at91_reg Reserved3 ;\r
+ at91_reg Reserved4 ;\r
+ at91_reg Reserved5 ;\r
+} StructTC ;\r
+\r
+#define NB_TC_CHANNEL 3\r
+\r
+typedef struct\r
+{\r
+ StructTC TC[NB_TC_CHANNEL] ;\r
+ at91_reg TC_BCR ; /* Block Control Register */\r
+ at91_reg TC_BMR ; /* Block Mode Register */\r
+} StructTCBlock ;\r
+\r
+/*--------------------------------------------------------*/\r
+/* TC_CCR: Timer Counter Control Register Bits Definition */\r
+/*--------------------------------------------------------*/\r
+#define TC_CLKEN 0x1\r
+#define TC_CLKDIS 0x2\r
+#define TC_SWTRG 0x4\r
+\r
+/*---------------------------------------------------------------*/\r
+/* TC_CMR: Timer Counter Channel Mode Register Bits Definition */\r
+/*---------------------------------------------------------------*/\r
+\r
+/*-----------------*/\r
+/* Clock Selection */\r
+/*-----------------*/\r
+#define TC_CLKS 0x7\r
+#define TC_CLKS_MCK2 0x0\r
+#define TC_CLKS_MCK8 0x1\r
+#define TC_CLKS_MCK32 0x2\r
+#define TC_CLKS_MCK128 0x3\r
+#define TC_CLKS_MCK1024 0x4\r
+\r
+#define TC_CLKS_SLCK 0x4\r
+\r
+#define TC_CLKS_XC0 0x5\r
+#define TC_CLKS_XC1 0x6\r
+#define TC_CLKS_XC2 0x7\r
+\r
+\r
+/*-----------------*/\r
+/* Clock Inversion */\r
+/*-----------------*/\r
+#define TC_CLKI 0x8\r
+\r
+/*------------------------*/\r
+/* Burst Signal Selection */\r
+/*------------------------*/\r
+#define TC_BURST 0x30\r
+#define TC_BURST_NONE 0x0\r
+#define TC_BUSRT_XC0 0x10\r
+#define TC_BURST_XC1 0x20\r
+#define TC_BURST_XC2 0x30\r
+\r
+/*------------------------------------------------------*/\r
+/* Capture Mode : Counter Clock Stopped with RB Loading */\r
+/*------------------------------------------------------*/\r
+#define TC_LDBSTOP 0x40\r
+\r
+/*-------------------------------------------------------*/\r
+/* Waveform Mode : Counter Clock Stopped with RC Compare */\r
+/*-------------------------------------------------------*/\r
+#define TC_CPCSTOP 0x40\r
+\r
+/*-------------------------------------------------------*/\r
+/* Capture Mode : Counter Clock Disabled with RB Loading */\r
+/*--------------------------------------------------------*/\r
+#define TC_LDBDIS 0x80\r
+\r
+/*--------------------------------------------------------*/\r
+/* Waveform Mode : Counter Clock Disabled with RC Compare */\r
+/*--------------------------------------------------------*/\r
+#define TC_CPCDIS 0x80\r
+\r
+/*------------------------------------------------*/\r
+/* Capture Mode : External Trigger Edge Selection */\r
+/*------------------------------------------------*/\r
+#define TC_ETRGEDG 0x300\r
+#define TC_ETRGEDG_EDGE_NONE 0x0\r
+#define TC_ETRGEDG_RISING_EDGE 0x100\r
+#define TC_ETRGEDG_FALLING_EDGE 0x200\r
+#define TC_ETRGEDG_BOTH_EDGE 0x300\r
+\r
+/*-----------------------------------------------*/\r
+/* Waveform Mode : External Event Edge Selection */\r
+/*-----------------------------------------------*/\r
+#define TC_EEVTEDG 0x300\r
+#define TC_EEVTEDG_EDGE_NONE 0x0\r
+#define TC_EEVTEDG_RISING_EDGE 0x100\r
+#define TC_EEVTEDG_FALLING_EDGE 0x200\r
+#define TC_EEVTEDG_BOTH_EDGE 0x300\r
+\r
+/*--------------------------------------------------------*/\r
+/* Capture Mode : TIOA or TIOB External Trigger Selection */\r
+/*--------------------------------------------------------*/\r
+#define TC_ABETRG 0x400\r
+#define TC_ABETRG_TIOB 0x0\r
+#define TC_ABETRG_TIOA 0x400\r
+\r
+/*------------------------------------------*/\r
+/* Waveform Mode : External Event Selection */\r
+/*------------------------------------------*/\r
+#define TC_EEVT 0xC00\r
+#define TC_EEVT_TIOB 0x0\r
+#define TC_EEVT_XC0 0x400\r
+#define TC_EEVT_XC1 0x800\r
+#define TC_EEVT_XC2 0xC00\r
+\r
+/*--------------------------------------------------*/\r
+/* Waveform Mode : Enable Trigger on External Event */\r
+/*--------------------------------------------------*/\r
+#define TC_ENETRG 0x1000\r
+\r
+/*----------------------------------*/\r
+/* RC Compare Enable Trigger Enable */\r
+/*----------------------------------*/\r
+#define TC_CPCTRG 0x4000\r
+\r
+/*----------------*/\r
+/* Mode Selection */\r
+/*----------------*/\r
+#define TC_WAVE 0x8000\r
+#define TC_CAPT 0x0\r
+\r
+/*-------------------------------------*/\r
+/* Capture Mode : RA Loading Selection */\r
+/*-------------------------------------*/\r
+#define TC_LDRA 0x30000\r
+#define TC_LDRA_EDGE_NONE 0x0\r
+#define TC_LDRA_RISING_EDGE 0x10000\r
+#define TC_LDRA_FALLING_EDGE 0x20000\r
+#define TC_LDRA_BOTH_EDGE 0x30000\r
+\r
+/*-------------------------------------------*/\r
+/* Waveform Mode : RA Compare Effect on TIOA */\r
+/*-------------------------------------------*/\r
+#define TC_ACPA 0x30000\r
+#define TC_ACPA_OUTPUT_NONE 0x0\r
+#define TC_ACPA_SET_OUTPUT 0x10000\r
+#define TC_ACPA_CLEAR_OUTPUT 0x20000\r
+#define TC_ACPA_TOGGLE_OUTPUT 0x30000\r
+\r
+/*-------------------------------------*/\r
+/* Capture Mode : RB Loading Selection */\r
+/*-------------------------------------*/\r
+#define TC_LDRB 0xC0000\r
+#define TC_LDRB_EDGE_NONE 0x0\r
+#define TC_LDRB_RISING_EDGE 0x40000\r
+#define TC_LDRB_FALLING_EDGE 0x80000\r
+#define TC_LDRB_BOTH_EDGE 0xC0000\r
+\r
+/*-------------------------------------------*/\r
+/* Waveform Mode : RC Compare Effect on TIOA */\r
+/*-------------------------------------------*/\r
+#define TC_ACPC 0xC0000\r
+#define TC_ACPC_OUTPUT_NONE 0x0\r
+#define TC_ACPC_SET_OUTPUT 0x40000\r
+#define TC_ACPC_CLEAR_OUTPUT 0x80000\r
+#define TC_ACPC_TOGGLE_OUTPUT 0xC0000\r
+\r
+/*-----------------------------------------------*/\r
+/* Waveform Mode : External Event Effect on TIOA */\r
+/*-----------------------------------------------*/\r
+#define TC_AEEVT 0x300000\r
+#define TC_AEEVT_OUTPUT_NONE 0x0\r
+#define TC_AEEVT_SET_OUTPUT 0x100000\r
+#define TC_AEEVT_CLEAR_OUTPUT 0x200000\r
+#define TC_AEEVT_TOGGLE_OUTPUT 0x300000\r
+\r
+/*-------------------------------------------------*/\r
+/* Waveform Mode : Software Trigger Effect on TIOA */\r
+/*-------------------------------------------------*/\r
+#define TC_ASWTRG 0xC00000\r
+#define TC_ASWTRG_OUTPUT_NONE 0x0\r
+#define TC_ASWTRG_SET_OUTPUT 0x400000\r
+#define TC_ASWTRG_CLEAR_OUTPUT 0x800000\r
+#define TC_ASWTRG_TOGGLE_OUTPUT 0xC00000\r
+\r
+/*-------------------------------------------*/\r
+/* Waveform Mode : RB Compare Effect on TIOB */\r
+/*-------------------------------------------*/\r
+#define TC_BCPB 0x1000000\r
+#define TC_BCPB_OUTPUT_NONE 0x0\r
+#define TC_BCPB_SET_OUTPUT 0x1000000\r
+#define TC_BCPB_CLEAR_OUTPUT 0x2000000\r
+#define TC_BCPB_TOGGLE_OUTPUT 0x3000000\r
+\r
+/*-------------------------------------------*/\r
+/* Waveform Mode : RC Compare Effect on TIOB */\r
+/*-------------------------------------------*/\r
+#define TC_BCPC 0xC000000\r
+#define TC_BCPC_OUTPUT_NONE 0x0\r
+#define TC_BCPC_SET_OUTPUT 0x4000000\r
+#define TC_BCPC_CLEAR_OUTPUT 0x8000000\r
+#define TC_BCPC_TOGGLE_OUTPUT 0xC000000\r
+\r
+/*-----------------------------------------------*/\r
+/* Waveform Mode : External Event Effect on TIOB */\r
+/*-----------------------------------------------*/\r
+#define TC_BEEVT 0x30000000 //* bit 29-28\r
+#define TC_BEEVT_OUTPUT_NONE 0x0\r
+#define TC_BEEVT_SET_OUTPUT 0x10000000 //* bit 29-28 01\r
+#define TC_BEEVT_CLEAR_OUTPUT 0x20000000 //* bit 29-28 10\r
+#define TC_BEEVT_TOGGLE_OUTPUT 0x30000000 //* bit 29-28 11\r
+\r
+/*- -----------------------------------------------*/\r
+/* Waveform Mode : Software Trigger Effect on TIOB */\r
+/*-------------------------------------------------*/\r
+#define TC_BSWTRG 0xC0000000\r
+#define TC_BSWTRG_OUTPUT_NONE 0x0\r
+#define TC_BSWTRG_SET_OUTPUT 0x40000000\r
+#define TC_BSWTRG_CLEAR_OUTPUT 0x80000000\r
+#define TC_BSWTRG_TOGGLE_OUTPUT 0xC0000000\r
+\r
+/*------------------------------------------------------*/\r
+/* TC_SR: Timer Counter Status Register Bits Definition */\r
+/*------------------------------------------------------*/\r
+#define TC_COVFS 0x1 /* Counter Overflow Status */\r
+#define TC_LOVRS 0x2 /* Load Overrun Status */\r
+#define TC_CPAS 0x4 /* RA Compare Status */\r
+#define TC_CPBS 0x8 /* RB Compare Status */\r
+#define TC_CPCS 0x10 /* RC Compare Status */\r
+#define TC_LDRAS 0x20 /* RA Loading Status */\r
+#define TC_LDRBS 0x40 /* RB Loading Status */\r
+#define TC_ETRGS 0x80 /* External Trigger Status */\r
+#define TC_CLKSTA 0x10000 /* Clock Status */\r
+#define TC_MTIOA 0x20000 /* TIOA Mirror */\r
+#define TC_MTIOB 0x40000 /* TIOB Status */\r
+\r
+/*--------------------------------------------------------------*/\r
+/* TC_BCR: Timer Counter Block Control Register Bits Definition */\r
+/*--------------------------------------------------------------*/\r
+#define TC_SYNC 0x1 /* Synchronisation Trigger */\r
+\r
+/*------------------------------------------------------------*/\r
+/* TC_BMR: Timer Counter Block Mode Register Bits Definition */\r
+/*------------------------------------------------------------*/\r
+#define TC_TC0XC0S 0x3 /* External Clock Signal 0 Selection */\r
+#define TC_TCLK0XC0 0x0\r
+#define TC_NONEXC0 0x1\r
+#define TC_TIOA1XC0 0x2\r
+#define TC_TIOA2XC0 0x3\r
+\r
+#define TC_TC1XC1S 0xC /* External Clock Signal 1 Selection */\r
+#define TC_TCLK1XC1 0x0\r
+#define TC_NONEXC1 0x4\r
+#define TC_TIOA0XC1 0x8\r
+#define TC_TIOA2XC1 0xC\r
+\r
+#define TC_TC2XC2S 0x30 /* External Clock Signal 2 Selection */\r
+#define TC_TCLK2XC2 0x0\r
+#define TC_NONEXC2 0x10\r
+#define TC_TIOA0XC2 0x20\r
+#define TC_TIOA1XC2 0x30\r
+\r
+#endif /* tc_h */\r
+\r
--- /dev/null
+//*----------------------------------------------------------------------------\r
+//* ATMEL Microcontroller Software Support - ROUSSET -\r
+//*----------------------------------------------------------------------------\r
+//* The software is delivered "AS IS" without warranty or condition of any\r
+//* kind, either express, implied or statutory. This includes without\r
+//* limitation any warranty or condition with respect to merchantability or\r
+//* fitness for any particular purpose, or against the infringements of\r
+//* intellectual property rights of others.\r
+//*-----------------------------------------------------------------------------\r
+//* File Name : usart.h\r
+//* Object : USART Header File.\r
+//*\r
+//* 1.0 01/04/00 JCZ : Creation\r
+//*----------------------------------------------------------------------------\r
+\r
+#ifndef usart_h\r
+#define usart_h\r
+\r
+//#include "periph/stdc/std_c.h"\r
+//#include "periph/pio/lib_pio.h"\r
+\r
+/*-------------------------------------------*/\r
+/* USART User Interface Structure Definition */\r
+/*-------------------------------------------*/\r
+\r
+typedef struct\r
+{\r
+ at91_reg US_CR ; /* Control Register */\r
+ at91_reg US_MR ; /* Mode Register */\r
+ at91_reg US_IER ; /* Interrupt Enable Register */\r
+ at91_reg US_IDR ; /* Interrupt Disable Register */\r
+ at91_reg US_IMR ; /* Interrupt Mask Register */\r
+ at91_reg US_CSR ; /* Channel Status Register */\r
+ at91_reg US_RHR ; /* Receive Holding Register */\r
+ at91_reg US_THR ; /* Transmit Holding Register */\r
+ at91_reg US_BRGR ; /* Baud Rate Generator Register */\r
+ at91_reg US_RTOR ; /* Receiver Timeout Register */\r
+ at91_reg US_TTGR ; /* Transmitter Time-guard Register */\r
+ at91_reg Reserved ;\r
+ at91_reg US_RPR ; /* Receiver Pointer Register */\r
+ at91_reg US_RCR ; /* Receiver Counter Register */\r
+ at91_reg US_TPR ; /* Transmitter Pointer Register */\r
+ at91_reg US_TCR ; /* Transmitter Counter Register */\r
+} StructUSART ;\r
+\r
+/*--------------------------*/\r
+/* US_CR : Control Register */\r
+/*--------------------------*/\r
+\r
+#define US_RSTRX 0x0004 /* Reset Receiver */\r
+#define US_RSTTX 0x0008 /* Reset Transmitter */\r
+#define US_RXEN 0x0010 /* Receiver Enable */\r
+#define US_RXDIS 0x0020 /* Receiver Disable */\r
+#define US_TXEN 0x0040 /* Transmitter Enable */\r
+#define US_TXDIS 0x0080 /* Transmitter Disable */\r
+#define US_RSTSTA 0x0100 /* Reset Status Bits */\r
+#define US_STTBRK 0x0200 /* Start Break */\r
+#define US_STPBRK 0x0400 /* Stop Break */\r
+#define US_STTTO 0x0800 /* Start Time-out */\r
+#define US_SENDA 0x1000 /* Send Address */\r
+\r
+/*-----------------------*/\r
+/* US_MR : Mode Register */\r
+/*-----------------------*/\r
+\r
+#define US_CLKS 0x0030 /* Clock Selection */\r
+#define US_CLKS_MCK 0x00 /* Master Clock */\r
+#define US_CLKS_MCK8 0x10 /* Master Clock divided by 8 */\r
+#define US_CLKS_SCK 0x20 /* External Clock */\r
+#define US_CLKS_SLCK 0x30 /* Slow Clock */\r
+\r
+#define US_CHRL 0x00C0 /* Byte Length */\r
+#define US_CHRL_5 0x00 /* 5 bits */\r
+#define US_CHRL_6 0x40 /* 6 bits */\r
+#define US_CHRL_7 0x80 /* 7 bits */\r
+#define US_CHRL_8 0xC0 /* 8 bits */\r
+\r
+#define US_SYNC 0x0100 /* Synchronous Mode Enable */\r
+\r
+#define US_PAR 0x0E00 /* Parity Mode */\r
+#define US_PAR_EVEN 0x00 /* Even Parity */\r
+#define US_PAR_ODD 0x200 /* Odd Parity */\r
+#define US_PAR_SPACE 0x400 /* Space Parity to 0 */\r
+#define US_PAR_MARK 0x600 /* Marked Parity to 1 */\r
+#define US_PAR_NO 0x800 /* No Parity */\r
+#define US_PAR_MULTIDROP 0xC00 /* Multi-drop Mode */\r
+\r
+#define US_NBSTOP 0x3000 /* Stop Bit Number */\r
+#define US_NBSTOP_1 0x0000 /* 1 Stop Bit */\r
+#define US_NBSTOP_1_5 0x1000 /* 1.5 Stop Bits */\r
+#define US_NBSTOP_2 0x2000 /* 2 Stop Bits */\r
+\r
+#define US_CHMODE 0xC000 /* Channel Mode */\r
+#define US_CHMODE_NORMAL 0x0000 /* Normal Mode */\r
+#define US_CHMODE_AUTOMATIC_ECHO 0x4000 /* Automatic Echo */\r
+#define US_CHMODE_LOCAL_LOOPBACK 0x8000 /* Local Loopback */\r
+#define US_CHMODE_REMOTE_LOOPBACK 0xC000 /* Remote Loopback */\r
+\r
+#define US_MODE9 0x20000 /* 9 Bit Mode */\r
+\r
+#define US_CLKO 0x40000 /* Baud Rate Output Enable */\r
+\r
+/* Mode Register model */\r
+\r
+/* Standard Asynchronous Mode : 8 bits , 1 stop , no parity */\r
+#define US_ASYNC_MODE ( US_CHMODE_NORMAL + \\r
+ US_NBSTOP_1 + \\r
+ US_PAR_NO + \\r
+ US_CHRL_8 + \\r
+ US_CLKS_MCK )\r
+\r
+/* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity */\r
+#define US_ASYNC_SCK_MODE ( US_CHMODE_NORMAL + \\r
+ US_NBSTOP_1 + \\r
+ US_PAR_NO + \\r
+ US_CHRL_8 + \\r
+ US_CLKS_SCK )\r
+\r
+/* Standard Synchronous Mode : 8 bits , 1 stop , no parity */\r
+#define US_SYNC_MODE ( US_SYNC + \\r
+ US_CHMODE_NORMAL + \\r
+ US_NBSTOP_1 + \\r
+ US_PAR_NO + \\r
+ US_CHRL_8 + \\r
+ US_CLKS_MCK )\r
+\r
+/* SCK used Label */\r
+#define SCK_USED (US_CLKO | US_CLKS_SCK)\r
+\r
+/*---------------------------------------------------------------*/\r
+/* US_IER, US_IDR, US_IMR, US_IMR: Status and Interrupt Register */\r
+/*---------------------------------------------------------------*/\r
+\r
+#define US_RXRDY 0x1 /* Receiver Ready */\r
+#define US_TXRDY 0x2 /* Transmitter Ready */\r
+#define US_RXBRK 0x4 /* Receiver Break */\r
+#define US_ENDRX 0x8 /* End of Receiver PDC Transfer */\r
+#define US_ENDTX 0x10 /* End of Transmitter PDC Transfer */\r
+#define US_OVRE 0x20 /* Overrun Error */\r
+#define US_FRAME 0x40 /* Framing Error */\r
+#define US_PARE 0x80 /* Parity Error */\r
+#define US_TIMEOUT 0x100 /* Receiver Timeout */\r
+#define US_TXEMPTY 0x200 /* Transmitter Empty */\r
+\r
+#define US_MASK_IRQ_TX (US_TXRDY | US_ENDTX | US_TXEMPTY)\r
+#define US_MASK_IRQ_RX (US_RXRDY | US_ENDRX | US_TIMEOUT)\r
+#define US_MASK_IRQ_ERROR (US_PARE | US_FRAME | US_OVRE | US_RXBRK)\r
+\r
+\r
+\r
+#endif /* usart_h */\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+#include <intrinsic.h>\r
+#include "board.h"\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 47923200 )\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 100 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) 14200 )\r
+#define configMAX_TASK_NAME_LEN ( 16 )\r
+#define configUSE_TRACE_FACILITY 0\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 1\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 0\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#include "FreeRTOS.h"\r
+#include "partest.h"\r
+#include "board.h"\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple parallel port IO routines for the LED's.\r
+ *-----------------------------------------------------------*/\r
+\r
+const unsigned portLONG led_mask[ NB_LED ]= { LED1, LED2, LED3, LED4 };\r
+\r
+void vParTestInitialise( void )\r
+{ \r
+ /* Start with all LED's off. */\r
+ AT91F_PIO_SetOutput( AT91C_BASE_PIOA, LED_MASK ); \r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )\r
+{\r
+ if( uxLED < ( portBASE_TYPE ) NB_LED )\r
+ {\r
+ if( xValue )\r
+ {\r
+ AT91F_PIO_SetOutput( AT91C_BASE_PIOA, led_mask[ uxLED ] );\r
+ }\r
+ else\r
+ {\r
+ AT91F_PIO_ClearOutput( AT91C_BASE_PIOA, led_mask[ uxLED ]);\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+ if( uxLED < ( portBASE_TYPE ) NB_LED )\r
+ {\r
+ if( AT91F_PIO_GetInput( AT91C_BASE_PIOA ) & led_mask[ uxLED ] )\r
+ {\r
+ AT91F_PIO_ClearOutput( AT91C_BASE_PIOA, led_mask[ uxLED ]);\r
+ }\r
+ else\r
+ {\r
+ AT91F_PIO_SetOutput( AT91C_BASE_PIOA, led_mask[ uxLED ] ); \r
+ }\r
+ }\r
+}\r
+\r
+\r
--- /dev/null
+/*----------------------------------------------------------------------------\r
+* ATMEL Microcontroller Software Support - ROUSSET -\r
+*----------------------------------------------------------------------------\r
+* The software is delivered "AS IS" without warranty or condition of any\r
+* kind, either express, implied or statutory. This includes without\r
+* limitation any warranty or condition with respect to merchantability or\r
+* fitness for any particular purpose, or against the infringements of\r
+* intellectual property rights of others.\r
+*----------------------------------------------------------------------------\r
+* File Name : Board.h\r
+* Object : AT91SAM7S Evaluation Board Features Definition File.\r
+*\r
+* Creation : JPP 16/Jun/2004\r
+*----------------------------------------------------------------------------\r
+*/\r
+#ifndef Board_h\r
+#define Board_h\r
+\r
+#include "AT91SAM7S64.h"\r
+#define __inline inline\r
+#include "lib_AT91SAM7S64.h"\r
+\r
+#define true -1\r
+#define false 0\r
+\r
+/*-------------------------------*/\r
+/* SAM7Board Memories Definition */\r
+/*-------------------------------*/\r
+// The AT91SAM7S64 embeds a 16-Kbyte SRAM bank, and 64 K-Byte Flash\r
+\r
+#define INT_SARM 0x00200000\r
+#define INT_SARM_REMAP 0x00000000\r
+\r
+#define INT_FLASH 0x00000000\r
+#define INT_FLASH_REMAP 0x01000000\r
+\r
+#define FLASH_PAGE_NB 512\r
+#define FLASH_PAGE_SIZE 128\r
+\r
+/*-----------------*/\r
+/* Leds Definition */\r
+/*-----------------*/\r
+/* PIO Flash PA PB PIN */\r
+#define LED1 (1<<0) /* PA0 / PGMEN0 & PWM0 TIOA0 48 */\r
+#define LED2 (1<<1) /* PA1 / PGMEN1 & PWM1 TIOB0 47 */\r
+#define LED3 (1<<2) /* PA2 & PWM2 SCK0 44 */\r
+#define LED4 (1<<3) /* PA3 & TWD NPCS3 43 */\r
+#define NB_LED 4\r
+\r
+#define LED_MASK (LED1|LED2|LED3|LED4)\r
+\r
+/*-------------------------*/\r
+/* Push Buttons Definition */\r
+/*-------------------------*/\r
+/* PIO Flash PA PB PIN */\r
+#define SW1_MASK (1<<19) /* PA19 / PGMD7 & RK FIQ 13 */\r
+#define SW2_MASK (1<<20) /* PA20 / PGMD8 & RF IRQ0 16 */\r
+#define SW3_MASK (1<<15) /* PA15 / PGM3 & TF TIOA1 20 */\r
+#define SW4_MASK (1<<14) /* PA14 / PGMD2 & SPCK PWM3 21 */\r
+#define SW_MASK (SW1_MASK|SW2_MASK|SW3_MASK|SW4_MASK)\r
+\r
+\r
+#define SW1 (1<<19) // PA19\r
+#define SW2 (1<<20) // PA20\r
+#define SW3 (1<<15) // PA15\r
+#define SW4 (1<<14) // PA14\r
+\r
+/*------------------*/\r
+/* USART Definition */\r
+/*------------------*/\r
+/* SUB-D 9 points J3 DBGU*/\r
+#define DBGU_RXD AT91C_PA9_DRXD /* JP11 must be close */\r
+#define DBGU_TXD AT91C_PA10_DTXD /* JP12 must be close */\r
+#define AT91C_DBGU_BAUD 115200 // Baud rate\r
+\r
+#define US_RXD_PIN AT91C_PA5_RXD0 /* JP9 must be close */\r
+#define US_TXD_PIN AT91C_PA6_TXD0 /* JP7 must be close */\r
+#define US_RTS_PIN AT91C_PA7_RTS0 /* JP8 must be close */\r
+#define US_CTS_PIN AT91C_PA8_CTS0 /* JP6 must be close */\r
+\r
+/*--------------*/\r
+/* Master Clock */\r
+/*--------------*/\r
+\r
+#define EXT_OC 18432000 // Exetrnal ocilator MAINCK\r
+#define MCK 47923200 // MCK (PLLRC div by 2)\r
+#define MCKKHz (MCK/1000) //\r
+\r
+#endif /* Board_h */\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;- ATMEL Microcontroller Software Support - ROUSSET -\r
+;------------------------------------------------------------------------------\r
+; The software is delivered "AS IS" without warranty or condition of any\r
+; kind, either express, implied or statutory. This includes without\r
+; limitation any warranty or condition with respect to merchantability or\r
+; fitness for any particular purpose, or against the infringements of\r
+; intellectual property rights of others.\r
+;-----------------------------------------------------------------------------\r
+;- File source : Cstartup.s79\r
+;- Object : Generic CStartup for IAR No Use REMAP\r
+;- Compilation flag : None\r
+;-\r
+;- 1.0 15/Jun/04 JPP : Creation\r
+;------------------------------------------------------------------------------\r
+\r
+#include "AT91SAM7S64_inc.h"\r
+\r
+;------------------------------------------------------------------------------\r
+;- Area Definition\r
+;------------------------------------------------------------------------------\r
+\r
+;---------------------------------------------------------------\r
+; ?RESET\r
+; Reset Vector.\r
+; Normally, segment INTVEC is linked at address 0.\r
+; For debugging purposes, INTVEC may be placed at other\r
+; addresses.\r
+; A debugger that honors the entry point will start the\r
+; program in a normal way even if INTVEC is not at address 0.\r
+;-------------------------------------------------------------\r
+\r
+ PROGRAM ?RESET\r
+ RSEG INTRAMSTART_REMAP\r
+ RSEG INTRAMEND_REMAP\r
+\r
+ EXTERN vPortYieldProcessor\r
+\r
+ RSEG ICODE:CODE:ROOT(2)\r
+ CODE32 ; Always ARM mode after reset \r
+ org 0 \r
+reset \r
+;------------------------------------------------------------------------------\r
+;- Exception vectors \r
+;--------------------\r
+;- These vectors can be read at address 0 or at RAM address\r
+;- They ABSOLUTELY requires to be in relative addresssing mode in order to\r
+;- guarantee a valid jump. For the moment, all are just looping.\r
+;- If an exception occurs before remap, this would result in an infinite loop.\r
+;- To ensure if a exeption occurs before start application to infinite loop.\r
+;------------------------------------------------------------------------------\r
+\r
+ B InitReset ; 0x00 Reset handler\r
+undefvec:\r
+ B undefvec ; 0x04 Undefined Instruction\r
+swivec:\r
+ B vPortYieldProcessor ; 0x08 Software Interrupt\r
+pabtvec:\r
+ B pabtvec ; 0x0C Prefetch Abort\r
+dabtvec:\r
+ B dabtvec ; 0x10 Data Abort\r
+rsvdvec:\r
+ B rsvdvec ; 0x14 reserved\r
+irqvec:\r
+ LDR PC, [PC, #-0xF20] ; Jump directly to the address given by the AIC\r
+\r
+fiqvec: ; 0x1c FIQ\r
+\r
+;------------------------------------------------------------------------------\r
+;- Function : FIQ_Handler_Entry\r
+;- Treatments : FIQ Controller Interrupt Handler.\r
+;- Called Functions : AIC_FVR[interrupt] \r
+;------------------------------------------------------------------------------\r
+\r
+FIQ_Handler_Entry:\r
+\r
+;- Switch in SVC/User Mode to allow User Stack access for C code \r
+; because the FIQ is not yet acknowledged\r
+\r
+;- Save and r0 in FIQ_Register \r
+ mov r9,r0\r
+ ldr r0 , [r8, #AIC_FVR]\r
+ msr CPSR_c,#I_BIT | F_BIT | ARM_MODE_SVC\r
+\r
+;- Save scratch/used registers and LR in User Stack\r
+ stmfd sp!, { r1-r3, r12, lr}\r
+\r
+;- Branch to the routine pointed by the AIC_FVR\r
+ mov r14, pc\r
+ bx r0\r
+\r
+;- Restore scratch/used registers and LR from User Stack\r
+ ldmia sp!, { r1-r3, r12, lr}\r
+\r
+;- Leave Interrupts disabled and switch back in FIQ mode\r
+ msr CPSR_c, #I_BIT | F_BIT | ARM_MODE_FIQ\r
+\r
+;- Restore the R0 ARM_MODE_SVC register \r
+ mov r0,r9\r
+\r
+;- Restore the Program Counter using the LR_fiq directly in the PC\r
+ subs pc,lr,#4\r
+\r
+InitReset:\r
+;------------------------------------------------------------------------------\r
+;- Low level Init (PMC, AIC, ? ....) by C function AT91F_LowLevelInit\r
+;------------------------------------------------------------------------------\r
+ EXTERN AT91F_LowLevelInit\r
+\r
+#define __iramend SFB(INTRAMEND_REMAP)\r
+\r
+;- minumum C initialization\r
+;- call AT91F_LowLevelInit( void)\r
+\r
+ ldr r13,=__iramend ; temporary stack in internal RAM\r
+;--Call Low level init function in ABSOLUTE through the Interworking\r
+ ldr r0,=AT91F_LowLevelInit\r
+ mov lr, pc\r
+ bx r0\r
+;------------------------------------------------------------------------------\r
+;- Stack Sizes Definition\r
+;------------------------\r
+;- Interrupt Stack requires 2 words x 8 priority level x 4 bytes when using\r
+;- the vectoring. This assume that the IRQ management.\r
+;- The Interrupt Stack must be adjusted depending on the interrupt handlers.\r
+;- Fast Interrupt not requires stack If in your application it required you must\r
+;- be definehere.\r
+;- The System stack size is not defined and is limited by the free internal\r
+;- SRAM.\r
+;------------------------------------------------------------------------------\r
+\r
+;------------------------------------------------------------------------------\r
+;- Top of Stack Definition\r
+;-------------------------\r
+;- Interrupt and Supervisor Stack are located at the top of internal memory in \r
+;- order to speed the exception handling context saving and restoring.\r
+;- ARM_MODE_SVC (Application, C) Stack is located at the top of the external memory.\r
+;------------------------------------------------------------------------------\r
+\r
+IRQ_STACK_SIZE EQU 300\r
+\r
+ARM_MODE_FIQ EQU 0x11\r
+ARM_MODE_IRQ EQU 0x12\r
+ARM_MODE_SVC EQU 0x13\r
+\r
+I_BIT EQU 0x80\r
+F_BIT EQU 0x40\r
+\r
+;------------------------------------------------------------------------------\r
+;- Setup the stack for each mode\r
+;-------------------------------\r
+ ldr r0, =__iramend\r
+\r
+;- Set up Fast Interrupt Mode and set FIQ Mode Stack\r
+ msr CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT\r
+;- Init the FIQ register\r
+ ldr r8, =AT91C_BASE_AIC\r
+\r
+;- Set up Interrupt Mode and set IRQ Mode Stack\r
+ msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT\r
+ mov r13, r0 ; Init stack IRQ\r
+ sub r0, r0, #IRQ_STACK_SIZE\r
+\r
+;- Enable interrupt & Set up Supervisor Mode and set Supervisor Mode Stack\r
+ msr CPSR_c, #ARM_MODE_SVC \r
+ mov r13, r0 \r
+\r
+\r
+;---------------------------------------------------------------\r
+; ?CSTARTUP\r
+;---------------------------------------------------------------\r
+ EXTERN __segment_init\r
+ EXTERN main\r
+; Initialize segments.\r
+; __segment_init is assumed to use\r
+; instruction set and to be reachable by BL from the ICODE segment\r
+; (it is safest to link them in segment ICODE).\r
+ ldr r0,=__segment_init\r
+ mov lr, pc\r
+ bx r0\r
+\r
+ PUBLIC __main\r
+?jump_to_main:\r
+ ldr lr,=?call_exit\r
+ ldr r0,=main\r
+__main:\r
+ bx r0\r
+\r
+;------------------------------------------------------------------------------\r
+;- Loop for ever\r
+;---------------\r
+;- End of application. Normally, never occur.\r
+;- Could jump on Software Reset ( B 0x0 ).\r
+;------------------------------------------------------------------------------\r
+?call_exit:\r
+End\r
+ b End\r
+\r
+\r
+\r
+;---------------------------------------------------------------\r
+; ?EXEPTION_VECTOR\r
+; This module is only linked if needed for closing files.\r
+;---------------------------------------------------------------\r
+ PUBLIC AT91F_Default_FIQ_handler\r
+ PUBLIC AT91F_Default_IRQ_handler\r
+ PUBLIC AT91F_Spurious_handler\r
+\r
+ CODE32 ; Always ARM mode after exeption \r
+\r
+AT91F_Default_FIQ_handler\r
+ b AT91F_Default_FIQ_handler\r
+\r
+AT91F_Default_IRQ_handler\r
+ b AT91F_Default_IRQ_handler\r
+\r
+AT91F_Spurious_handler\r
+ b AT91F_Spurious_handler\r
+\r
+ ENDMOD\r
+\r
+ END\r
+\r
--- /dev/null
+//*----------------------------------------------------------------------------\r
+//* ATMEL Microcontroller Software Support - ROUSSET -\r
+//*----------------------------------------------------------------------------\r
+//* The software is delivered "AS IS" without warranty or condition of any\r
+//* kind, either express, implied or statutory. This includes without\r
+//* limitation any warranty or condition with respect to merchantability or\r
+//* fitness for any particular purpose, or against the infringements of\r
+//* intellectual property rights of others.\r
+//*----------------------------------------------------------------------------\r
+//* File Name : Cstartup_SAM7.c\r
+//* Object : Low level initializations written in C for IAR\r
+//* tools\r
+//* Creation : 12/Jun/04\r
+//*\r
+//*----------------------------------------------------------------------------\r
+\r
+\r
+// Include the board file description\r
+#include "Board.h"\r
+\r
+// The following functions must be write in ARM mode this function called directly\r
+// by exception vector\r
+extern void AT91F_Spurious_handler(void);\r
+extern void AT91F_Default_IRQ_handler(void);\r
+extern void AT91F_Default_FIQ_handler(void);\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_LowLevelInit\r
+//* \brief This function performs very low level HW initialization\r
+//* this function can be use a Stack, depending the compilation\r
+//* optimization mode\r
+//*----------------------------------------------------------------------------\r
+void AT91F_LowLevelInit( void );\r
+void AT91F_LowLevelInit( void) @ "ICODE"\r
+{\r
+ int i;\r
+ AT91PS_PMC pPMC = AT91C_BASE_PMC;\r
+ //* Set Flash Waite sate\r
+ // Single Cycle Access at Up to 30 MHz, or 40\r
+ // if MCK = 47923200 I have 50 Cycle for 1 useconde ( flied MC_FMR->FMCN\r
+ AT91C_BASE_MC->MC_FMR = ((AT91C_MC_FMCN)&(50 <<16)) | AT91C_MC_FWS_1FWS ;\r
+\r
+ //* Watchdog Disable\r
+ AT91C_BASE_WDTC->WDTC_WDMR= AT91C_SYSC_WDDIS;\r
+\r
+ //* Set MCK at 47 923 200\r
+ // 1 Enabling the Main Oscillator:\r
+ // SCK = 1/32768 = 30.51 uSeconde\r
+ // Start up time = 8 * 6 / SCK = 56 * 30.51 = 1,46484375 ms\r
+ pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) | AT91C_CKGR_MOSCEN ));\r
+ // Wait the startup time\r
+ while(!(pPMC->PMC_SR & AT91C_PMC_MOSCS));\r
+ // 2 Checking the Main Oscillator Frequency (Optional)\r
+ // 3 Setting PLL and divider:\r
+ // - div by 5 Fin = 3,6864 =(18,432 / 5)\r
+ // - Mul 25+1: Fout = 95,8464 =(3,6864 *26)\r
+ // for 96 MHz the erroe is 0.16%\r
+ // Field out NOT USED = 0\r
+ // PLLCOUNT pll startup time esrtimate at : 0.844 ms\r
+ // PLLCOUNT 28 = 0.000844 /(1/32768)\r
+ pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 0x05) |\r
+ (AT91C_CKGR_PLLCOUNT & (28<<8)) |\r
+ (AT91C_CKGR_MUL & (25<<16)));\r
+\r
+ // Wait the startup time\r
+ while(!(pPMC->PMC_SR & AT91C_PMC_LOCK));\r
+ // 4. Selection of Master Clock and Processor Clock\r
+ // select the PLL clock divided by 2\r
+ pPMC->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK | AT91C_PMC_PRES_CLK_2 ;\r
+\r
+ // Enable User Reset and set its minimal assertion to 960 us\r
+ AT91C_BASE_RSTC->RSTC_RMR = AT91C_SYSC_URSTEN | (0x4<<8) | (unsigned int) (0xA5<<24);\r
+\r
+\r
+ // Set up the default interrupts handler vectors\r
+ AT91C_BASE_AIC->AIC_SVR[0] = (int) AT91F_Default_FIQ_handler ;\r
+ for (i=1;i < 31; i++)\r
+ {\r
+ AT91C_BASE_AIC->AIC_SVR[i] = (int) AT91F_Default_IRQ_handler ;\r
+ }\r
+ AT91C_BASE_AIC->AIC_SPU = (int) AT91F_Spurious_handler ;\r
+\r
+}\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+ Sample interrupt driven USB device driver. This is a minimal implementation \r
+ for demonstration only. Although functional, it is not a full and compliant\r
+ implementation. \r
+ \r
+ The USB device enumerates as a simple 3 axis joystick, and once configured\r
+ transmits 3 axis of data which can be viewed from the USB host machine.\r
+\r
+ This file implements the USB interrupt service routine, and a demo FreeRTOS \r
+ task. The interrupt service routine handles the USB hardware - taking a \r
+ snapshot of the USB status at the point of the interrupt. The task receives\r
+ the status information from the interrupt for processing at the task level.\r
+ \r
+ See the FreeRTOS.org WEB documentation for more information.\r
+*/\r
+\r
+/*\r
+ Changes from V2.5.5\r
+ \r
+ + Descriptors that have a length that is an exact multiple of usbFIFO_LENGTH\r
+ can now be transmitted. To this end an extra parameter has been \r
+ added to the prvSendControlData() function, and the state\r
+ eSENDING_EVEN_DESCRIPTOR has been introduced. Thanks to Scott Miller for\r
+ assisting with this contribution.\r
+\r
+ Changes from V2.6.0\r
+\r
+ + Replaced the duplicated RX_DATA_BK0 in the interrupt mask with the\r
+ RX_DATA_BK1.\r
+*/\r
+\r
+/* Standard includes. */\r
+#include <string.h>\r
+\r
+/* Demo board includes. */\r
+#include "board.h"\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+\r
+\r
+/* Descriptor type definitions. */\r
+#define usbDESCRIPTOR_TYPE_DEVICE ( 0x01 )\r
+#define usbDESCRIPTOR_TYPE_CONFIGURATION ( 0x02 )\r
+#define usbDESCRIPTOR_TYPE_STRING ( 0x03 )\r
+\r
+/* USB request type definitions. */\r
+#define usbGET_REPORT_REQUEST ( 0x01 )\r
+#define usbGET_IDLE_REQUEST ( 0x02 )\r
+#define usbGET_PROTOCOL_REQUEST ( 0x03 )\r
+#define usbSET_REPORT_REQUEST ( 0x09 )\r
+#define usbSET_IDLE_REQUEST ( 0x0A )\r
+#define usbSET_PROTOCOL_REQUEST ( 0x0B )\r
+#define usbGET_CONFIGURATION_REQUEST ( 0x08 )\r
+#define usbGET_STATUS_REQUEST ( 0x00 )\r
+#define usbCLEAR_FEATURE_REQUEST ( 0x01 )\r
+#define usbSET_FEATURE_REQUEST ( 0x03 )\r
+#define usbSET_ADDRESS_REQUEST ( 0x05 )\r
+#define usbGET_DESCRIPTOR_REQUEST ( 0x06 )\r
+#define usbSET_CONFIGURATION_REQUEST ( 0x09 )\r
+#define usbGET_INTERFACE_REQUEST ( 0x0A )\r
+#define usbSET_INTERFACE_REQUEST ( 0x0B )\r
+\r
+\r
+/* Misc USB definitions. */\r
+#define usbDEVICE_CLASS_VENDOR_SPECIFIC ( 0xFF )\r
+#define usbBUS_POWERED ( 0x80 )\r
+#define usbHID_REPORT_DESCRIPTOR ( 0x22 )\r
+#define AT91C_UDP_TRANSCEIVER_ENABLE ( *( ( unsigned long * ) 0xfffb0074 ) )\r
+\r
+/* Index to the various string. */\r
+#define usbLANGUAGE_STRING ( 0 )\r
+#define usbMANUFACTURER_STRING ( 1 )\r
+#define usbPRODUCT_STRING ( 2 )\r
+#define usbCONFIGURATION_STRING ( 3 )\r
+#define usbINTERFACE_STRING ( 4 )\r
+\r
+/* Data indexes for reading the request from the xISRStatus.ucFifoData[]\r
+into xUSB_REQUEST. The data order is designed for speed - so looks a \r
+little odd. */\r
+#define usbREQUEST_TYPE_INDEX ( 7 )\r
+#define usbREQUEST_INDEX ( 6 )\r
+#define usbVALUE_HIGH_BYTE ( 4 )\r
+#define usbVALUE_LOW_BYTE ( 5 )\r
+#define usbINDEX_HIGH_BYTE ( 2 )\r
+#define usbINDEX_LOW_BYTE ( 3 )\r
+#define usbLENGTH_HIGH_BYTE ( 0 )\r
+#define usbLENGTH_LOW_BYTE ( 1 )\r
+\r
+/* Misc application definitions. */\r
+#define usbINTERRUPT_PRIORITY ( 3 )\r
+#define usbQUEUE_LENGTH ( 0x3 ) /* Must have all bits set! */\r
+#define usbFIFO_LENGTH ( ( unsigned portLONG ) 8 )\r
+#define usbEND_POINT_0 ( 0 )\r
+#define usbEND_POINT_1 ( 1 )\r
+#define usbXUP ( 1 )\r
+#define usbXDOWN ( 2 )\r
+#define usbYUP ( 3 )\r
+#define usbYDOWN ( 4 )\r
+#define usbMAX_COORD ( 120 )\r
+#define usbMAX_TX_MESSAGE_SIZE ( 128 )\r
+#define usbRX_COUNT_MASK ( ( unsigned portLONG ) 0x7ff )\r
+#define AT91C_UDP_STALLSENT AT91C_UDP_ISOERROR\r
+#define usbSHORTEST_DELAY ( ( portTickType ) 1 )\r
+#define usbINIT_DELAY ( ( portTickType ) 500 / portTICK_RATE_MS )\r
+#define usbSHORT_DELAY ( ( portTickType ) 50 / portTICK_RATE_MS )\r
+#define usbEND_POINT_RESET_MASK ( ( unsigned portLONG ) 0x0f )\r
+#define usbDATA_INC ( ( portCHAR ) 5 )\r
+#define usbEXPECTED_NUMBER_OF_BYTES ( ( unsigned portLONG ) 8 )\r
+\r
+/* Control request types. */\r
+#define usbSTANDARD_DEVICE_REQUEST ( 0 )\r
+#define usbSTANDARD_INTERFACE_REQUEST ( 1 )\r
+#define usbSTANDARD_END_POINT_REQUEST ( 2 )\r
+#define usbCLASS_INTERFACE_REQUEST ( 5 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Structure used to take a snapshot of the USB status from within the ISR. */\r
+typedef struct X_ISR_STATUS\r
+{\r
+ unsigned portLONG ulISR;\r
+ unsigned portLONG ulCSR0;\r
+ unsigned portCHAR ucFifoData[ 8 ];\r
+} xISRStatus;\r
+\r
+/* Structure used to hold the received requests. */\r
+typedef struct \r
+{\r
+ unsigned portCHAR ucReqType;\r
+ unsigned portCHAR ucRequest;\r
+ unsigned portSHORT usValue;\r
+ unsigned portSHORT usIndex;\r
+ unsigned portSHORT usLength;\r
+} xUSB_REQUEST;\r
+\r
+typedef enum\r
+{\r
+ eNOTHING,\r
+ eJUST_RESET,\r
+ eJUST_GOT_CONFIG,\r
+ eJUST_GOT_ADDRESS,\r
+ eSENDING_EVEN_DESCRIPTOR,\r
+ eREADY_TO_SEND\r
+} eDRIVER_STATE;\r
+\r
+/* Structure used to control the data being sent to the host. */\r
+typedef struct\r
+{\r
+ unsigned portCHAR ucTxBuffer[ usbMAX_TX_MESSAGE_SIZE ];\r
+ unsigned portLONG ulNextCharIndex;\r
+ unsigned portLONG ulTotalDataLength;\r
+} xTX_MESSAGE;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* \r
+ * The USB interrupt service routine. This takes a snapshot of the USB\r
+ * device at the time of the interrupt, clears the interrupts, and posts\r
+ * the data to the USB processing task.\r
+ */\r
+__arm void vUSB_ISR( void );\r
+\r
+/*\r
+ * Called after the bus reset interrupt - this function readies all the\r
+ * end points for communication.\r
+ */\r
+static void prvResetEndPoints( void );\r
+\r
+/*\r
+ * Setup the USB hardware, install the interrupt service routine and \r
+ * initialise all the state variables.\r
+ */\r
+static void vInitUSBInterface( void );\r
+\r
+/*\r
+ * Decode and act upon an interrupt generated by the control end point.\r
+ */\r
+static void prvProcessEndPoint0Interrupt( xISRStatus *pxMessage );\r
+\r
+/* \r
+ * For simplicity requests are separated into device, interface, class \r
+ * interface and end point requests.\r
+ *\r
+ * Decode and handle standard device requests originating on the control\r
+ * end point. \r
+ */\r
+static void prvHandleStandardDeviceRequest( xUSB_REQUEST *pxRequest );\r
+\r
+/*\r
+ * For simplicity requests are separated into device, interface, class \r
+ * interface and end point requests.\r
+ *\r
+ * Decode and handle standard interface requests originating on the control\r
+ * end point.\r
+ */\r
+static void prvHandleStandardInterfaceRequest( xUSB_REQUEST *pxRequest );\r
+\r
+/*\r
+ * For simplicity requests are separated into device, interface, class \r
+ * interface and end point requests.\r
+ *\r
+ * Decode and handle standard end point requests originating on the control\r
+ * end point.\r
+ */\r
+static void prvHandleStandardEndPointRequest( xUSB_REQUEST *pxRequest );\r
+\r
+/*\r
+ * For simplicity requests are separated into device, interface, class \r
+ * interface and end point requests.\r
+ *\r
+ * Decode and handle the class interface requests.\r
+ */\r
+static void prvHandleClassInterfaceRequest( xUSB_REQUEST *pxRequest );\r
+\r
+/*\r
+ * Setup the Tx buffer to send data in response to a control request.\r
+ *\r
+ * The data to be transmitted is buffered, the state variables are updated,\r
+ * then prvSendNextSegment() is called to start the transmission off. Once\r
+ * the first segment has been sent the remaining segments are transmitted\r
+ * in response to TXCOMP interrupts until the entire buffer has been\r
+ * sent.\r
+ */\r
+static void prvSendControlData( unsigned portCHAR *pucData, unsigned portSHORT usRequestedLength, unsigned portLONG ulLengthLeftToSend, portLONG lSendingDescriptor );\r
+\r
+/*\r
+ * Examine the Tx buffer to see if there is any more data to be transmitted.\r
+ * \r
+ * If there is data to be transmitted then send the next segment. A segment\r
+ * can have a maximum of 8 bytes (this is defined as the maximum for the end\r
+ * point by the descriptor). The final segment may be less than 8 bytes if\r
+ * the total data length was not an exact multiple of 8.\r
+ */\r
+static void prvSendNextSegment( void );\r
+\r
+/*\r
+ * A stall condition is forced each time the host makes a request that is not\r
+ * supported by this minimal implementation.\r
+ * \r
+ * A stall is forced by setting the appropriate bit in the end points control\r
+ * and status register. \r
+ */\r
+static void prvSendStall( void );\r
+\r
+/*\r
+ * A NULL (or zero length packet) is transmitted in acknowledge the reception \r
+ * of certain events from the host.\r
+ */\r
+static void prvUSBTransmitNull( void );\r
+\r
+/* \r
+ * When the host requests a descriptor this function is called to determine \r
+ * which descriptor is being requested and start its transmission.\r
+ */\r
+static void prvGetStandardInterfaceDescriptor( xUSB_REQUEST *pxRequest );\r
+\r
+/*\r
+ * This demo USB device enumerates as a simple 3 axis joystick. Once \r
+ * configured this function is periodically called to generate some sample\r
+ * joystick data.\r
+ *\r
+ * The x and y axis are made to move in a square. The z axis is made to \r
+ * repeatedly increment up to its maximum.\r
+ */\r
+static void prvTransmitSampleValues( void );\r
+\r
+/*\r
+ * The created task to handle the USB demo functionality. \r
+ */\r
+void vUSBDemoTask( void *pvParameters );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ - DESCRIPTOR DEFINITIONS -\r
+*/\r
+\r
+/* String descriptors used during the enumeration process.\r
+These take the form:\r
+\r
+{\r
+ Length of descriptor,\r
+ Descriptor type,\r
+ Data\r
+}\r
+*/\r
+const portCHAR pxLanguageStringDescriptor[] =\r
+{\r
+ 4,\r
+ usbDESCRIPTOR_TYPE_STRING,\r
+ 0x09, 0x04\r
+};\r
+\r
+const portCHAR pxManufacturerStringDescriptor[] = \r
+{\r
+ 18,\r
+ usbDESCRIPTOR_TYPE_STRING,\r
+\r
+ 'F', 0x00,\r
+ 'r', 0x00,\r
+ 'e', 0x00,\r
+ 'e', 0x00,\r
+ 'R', 0x00,\r
+ 'T', 0x00,\r
+ 'O', 0x00,\r
+ 'S', 0x00 \r
+};\r
+\r
+const portCHAR pxProductStringDescriptor[] = \r
+{\r
+ 44,\r
+ usbDESCRIPTOR_TYPE_STRING,\r
+\r
+ 'F', 0x00,\r
+ 'r', 0x00,\r
+ 'e', 0x00,\r
+ 'e', 0x00,\r
+ 'R', 0x00,\r
+ 'T', 0x00,\r
+ 'O', 0x00,\r
+ 'S', 0x00,\r
+ '.', 0x00,\r
+ 'o', 0x00,\r
+ 'r', 0x00,\r
+ 'g', 0x00,\r
+ ' ', 0x00,\r
+ 'J', 0x00,\r
+ 'o', 0x00,\r
+ 'y', 0x00,\r
+ 's', 0x00,\r
+ 't', 0x00,\r
+ 'i', 0x00,\r
+ 'c', 0x00,\r
+ 'k', 0x00\r
+};\r
+\r
+const portCHAR pxConfigurationStringDescriptor[] = \r
+{\r
+ 38,\r
+ usbDESCRIPTOR_TYPE_STRING,\r
+\r
+ 'C', 0x00,\r
+ 'o', 0x00,\r
+ 'n', 0x00,\r
+ 'f', 0x00,\r
+ 'i', 0x00,\r
+ 'g', 0x00,\r
+ 'u', 0x00,\r
+ 'r', 0x00,\r
+ 'a', 0x00,\r
+ 't', 0x00,\r
+ 'i', 0x00,\r
+ 'o', 0x00,\r
+ 'n', 0x00,\r
+ ' ', 0x00,\r
+ 'N', 0x00,\r
+ 'a', 0x00,\r
+ 'm', 0x00,\r
+ 'e', 0x00\r
+};\r
+\r
+const portCHAR pxInterfaceStringDescriptor[] = \r
+{\r
+ 30,\r
+ usbDESCRIPTOR_TYPE_STRING,\r
+\r
+ 'I', 0x00,\r
+ 'n', 0x00,\r
+ 't', 0x00,\r
+ 'e', 0x00,\r
+ 'r', 0x00,\r
+ 'f', 0x00,\r
+ 'a', 0x00,\r
+ 'c', 0x00,\r
+ 'e', 0x00,\r
+ ' ', 0x00,\r
+ 'N', 0x00,\r
+ 'a', 0x00,\r
+ 'm', 0x00,\r
+ 'e', 0x00\r
+};\r
+\r
+/* Enumeration descriptors. */\r
+const portCHAR pxReportDescriptor[] =\r
+{\r
+ 0x05, 0x01, /* USAGE_PAGE (Generic Desktop) */\r
+ 0x09, 0x04, /* USAGE (Joystick) */\r
+ 0xa1, 0x01, /* COLLECTION (Application) */\r
+ 0x05, 0x01, /* USAGE_PAGE (Generic Desktop) */\r
+ 0x09, 0x01, /* USAGE (Pointer) */\r
+ 0xa1, 0x00, /* COLLECTION (Physical) */\r
+ 0x09, 0x30, /* USAGE (X) */\r
+ 0x09, 0x31, /* USAGE (Y) */\r
+ 0x09, 0x32, /* USAGE (Z) */\r
+ 0x15, 0x81, /* LOGICAL_MINIMUM (-127) */\r
+ 0x25, 0x7f, /* LOGICAL_MAXIMUM (127) */\r
+ 0x75, 0x08, /* REPORT_SIZE (8) */\r
+ 0x95, 0x03, /* REPORT_COUNT (3) */\r
+ 0x81, 0x02, /* INPUT (Data,Var,Abs) */\r
+ 0xc0, /* END_COLLECTION */\r
+ 0xc0 /* END_COLLECTION */\r
+};\r
+\r
+const char pxDeviceDescriptor[] = \r
+{\r
+ /* Device descriptor */\r
+ 0x12, /* bLength */\r
+ 0x01, /* bDescriptorType */\r
+ 0x10, 0x01, /* bcdUSBL */\r
+ usbDEVICE_CLASS_VENDOR_SPECIFIC, /* bDeviceClass: */\r
+ 0x00, /* bDeviceSubclass: */\r
+ 0x00, /* bDeviceProtocol: */\r
+ 0x08, /* bMaxPacketSize0 */\r
+ 0xFF, 0xFF, /* idVendorL */\r
+ 0x01, 0x00, /* idProductL */\r
+ 0x00, 0x01, /* bcdDeviceL */\r
+ usbMANUFACTURER_STRING, /* iManufacturer */\r
+ usbPRODUCT_STRING, /* iProduct */\r
+ 0x00, /* SerialNumber */\r
+ 0x01 /* bNumConfigs */\r
+};\r
+\r
+const char pxConfigDescriptor[] = {\r
+ /* Configuration 1 descriptor */\r
+ 0x09, /* CbLength */\r
+ 0x02, /* CbDescriptorType */\r
+ 0x22, 0x00, /* CwTotalLength 2 EP + Control */\r
+ 0x01, /* CbNumInterfaces */\r
+ 0x01, /* CbConfigurationValue */\r
+ usbCONFIGURATION_STRING,/* CiConfiguration */\r
+ usbBUS_POWERED, /* CbmAttributes Bus powered + Remote Wakeup*/\r
+ 0x32, /* CMaxPower: 100mA */\r
+\r
+ /* Joystick Interface Descriptor Requirement */\r
+ 0x09, /* bLength */\r
+ 0x04, /* bDescriptorType */\r
+ 0x00, /* bInterfaceNumber */\r
+ 0x00, /* bAlternateSetting */\r
+ 0x01, /* bNumEndpoints */\r
+ 0x03, /* bInterfaceClass: HID code */\r
+ 0x00, /* bInterfaceSubclass */\r
+ 0x00, /* bInterfaceProtocol */\r
+ usbINTERFACE_STRING,/* iInterface */\r
+\r
+ /* HID Descriptor */\r
+ 0x09, /* bLength */\r
+ 0x21, /* bDescriptor type: HID Descriptor Type */\r
+ 0x00, 0x01, /* bcdHID */\r
+ 0x00, /* bCountryCode */\r
+ 0x01, /* bNumDescriptors */\r
+ usbHID_REPORT_DESCRIPTOR, /* bDescriptorType */\r
+ sizeof( pxReportDescriptor ), 0x00, /* wItemLength */\r
+\r
+ /* Endpoint 1 descriptor */\r
+ 0x07, /* bLength */\r
+ 0x05, /* bDescriptorType */\r
+ 0x81, /* bEndpointAddress, Endpoint 01 - IN */\r
+ 0x03, /* bmAttributes INT */\r
+ 0x03, 0x00, /* wMaxPacketSize: 3 bytes (x, y, z) */\r
+ 0x0A /* bInterval */\r
+};\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* File scope state variables. */\r
+static unsigned portCHAR ucUSBConfig = ( unsigned portCHAR ) 0;\r
+static unsigned portLONG ulReceivedAddress = ( unsigned portLONG ) 0;\r
+static eDRIVER_STATE eDriverState = eNOTHING;\r
+\r
+/* Array in which the USB interrupt status is passed between the ISR and task. */\r
+static xISRStatus xISRMessages[ usbQUEUE_LENGTH + 1 ];\r
+\r
+/* Structure used to control the characters being sent to the host. */\r
+static xTX_MESSAGE pxCharsForTx;\r
+\r
+/* Queue used to pass messages between the ISR and the task. */\r
+static xQueueHandle xUSBInterruptQueue; \r
+\r
+/* ISR entry has to be written in the asm file as we want a context switch\r
+to occur from within the ISR. See the port documentation on the FreeRTOS.org\r
+WEB site for more information. */\r
+extern void vUSBISREntry( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Macros to manipulate the control and status registers. These registers \r
+cannot be accessed using a direct read modify write operation outside of the \r
+ISR as some bits are left unchanged by writing with a 0, and some are left \r
+unchanged by writing with a 1. */\r
+\r
+#define usbINT_CLEAR_MASK (AT91C_UDP_TXCOMP | AT91C_UDP_STALLSENT | AT91C_UDP_RXSETUP | AT91C_UDP_RX_DATA_BK0 | AT91C_UDP_RX_DATA_BK1 )\r
+\r
+#define usbCSR_SET_BIT( pulValueNow, ulBit ) \\r
+{ \\r
+ /* Set TXCOMP, RX_DATA_BK0, RXSETUP, */ \\r
+ /* STALLSENT and RX_DATA_BK1 to 1 so the */ \\r
+ /* write has no effect. */ \\r
+ ( * ( ( unsigned portLONG * ) pulValueNow ) ) |= ( unsigned portLONG ) 0x4f; \\r
+ \\r
+ /* Clear the FORCE_STALL and TXPKTRDY bits */ \\r
+ /* so the write has no effect. */ \\r
+ ( * ( ( unsigned portLONG * ) pulValueNow ) ) &= ( unsigned portLONG ) 0xffffffcf; \\r
+ \\r
+ /* Set whichever bit we want set. */ \\r
+ ( * ( ( unsigned portLONG * ) pulValueNow ) ) |= ( ulBit ); \\r
+}\r
+\r
+#define usbCSR_CLEAR_BIT( pulValueNow, ulBit ) \\r
+{ \\r
+ /* Set TXCOMP, RX_DATA_BK0, RXSETUP, */ \\r
+ /* STALLSENT and RX_DATA_BK1 to 1 so the */ \\r
+ /* write has no effect. */ \\r
+ ( * ( ( unsigned portLONG * ) pulValueNow ) ) |= ( unsigned portLONG ) 0x4f; \\r
+ \\r
+ /* Clear the FORCE_STALL and TXPKTRDY bits */ \\r
+ /* so the write has no effect. */ \\r
+ ( * ( ( unsigned portLONG * ) pulValueNow ) ) &= ( unsigned portLONG ) 0xffffffcf; \\r
+ \\r
+ /* Clear whichever bit we want clear. */ \\r
+ ( * ( ( unsigned portLONG * ) pulValueNow ) ) &= ( ~ulBit ); \\r
+}\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+__arm void vUSB_ISR( void )\r
+{\r
+portBASE_TYPE xTaskWokenByPost = pdFALSE; \r
+static volatile unsigned portLONG ulNextMessage = 0;\r
+xISRStatus *pxMessage;\r
+unsigned portLONG ulTemp, ulRxBytes;\r
+\r
+ /* Take the next message from the queue. Note that usbQUEUE_LENGTH *must*\r
+ be all 1's, as in 0x01, 0x03, 0x07, etc. */\r
+ pxMessage = &( xISRMessages[ ( ulNextMessage & usbQUEUE_LENGTH ) ] );\r
+ ulNextMessage++;\r
+\r
+ /* Take a snapshot of the current USB state for processing at the task\r
+ level. */\r
+ pxMessage->ulISR = AT91C_BASE_UDP->UDP_ISR;\r
+ pxMessage->ulCSR0 = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ];\r
+\r
+ /* Clear the interrupts from the ICR register. The bus end interrupt is\r
+ cleared separately as it does not appear in the mask register. */\r
+ AT91C_BASE_UDP->UDP_ICR = AT91C_BASE_UDP->UDP_IMR | AT91C_UDP_ENDBUSRES;\r
+ \r
+ /* If there are bytes in the FIFO then we have to retrieve them here. \r
+ Ideally this would be done at the task level. However we need to clear the\r
+ RXSETUP interrupt before leaving the ISR, and this may cause the data in\r
+ the FIFO to be overwritten. Also the DIR bit has to be changed before the\r
+ RXSETUP bit is cleared (as per the SAM7 manual). */\r
+ ulTemp = pxMessage->ulCSR0;\r
+ \r
+ /* Are there any bytes in the FIFO? */\r
+ ulRxBytes = ulTemp >> 16;\r
+ ulRxBytes &= usbRX_COUNT_MASK;\r
+ \r
+ /* With this minimal implementation we are only interested in receiving \r
+ setup bytes on the control end point. */\r
+ if( ( ulRxBytes > 0 ) && ( ulTemp & AT91C_UDP_RXSETUP ) )\r
+ {\r
+ /* Take off 1 for a zero based index. */\r
+ while( ulRxBytes > 0 )\r
+ {\r
+ ulRxBytes--;\r
+ pxMessage->ucFifoData[ ulRxBytes ] = AT91C_BASE_UDP->UDP_FDR[ usbEND_POINT_0 ]; \r
+ }\r
+ \r
+ /* The direction must be changed first. */\r
+ usbCSR_SET_BIT( &ulTemp, ( AT91C_UDP_DIR ) );\r
+ AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] = ulTemp;\r
+ }\r
+ \r
+ /* Must write zero's to TXCOMP, STALLSENT, RXSETUP, and the RX DATA\r
+ registers to clear the interrupts in the CSR register. */\r
+ usbCSR_CLEAR_BIT( &ulTemp, usbINT_CLEAR_MASK );\r
+ AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] = ulTemp;\r
+\r
+ /* Also clear the interrupts in the CSR1 register. */\r
+ ulTemp = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ];\r
+ usbCSR_CLEAR_BIT( &ulTemp, usbINT_CLEAR_MASK ); \r
+ AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ] = ulTemp;\r
+\r
+ /* The message now contains the entire state and optional data from\r
+ the USB interrupt. This can now be posted on the Rx queue ready for\r
+ processing at the task level. */\r
+ xTaskWokenByPost = xQueueSendFromISR( xUSBInterruptQueue, &pxMessage, xTaskWokenByPost );\r
+\r
+ /* We may want to switch to the USB task, if this message has made\r
+ it the highest priority task that is ready to execute. */\r
+ portEND_SWITCHING_ISR( xTaskWokenByPost );\r
+\r
+ /* Clear the AIC ready for the next interrupt. */ \r
+ AT91C_BASE_AIC->AIC_EOICR = 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vUSBDemoTask( void *pvParameters )\r
+{\r
+xISRStatus *pxMessage;\r
+\r
+ /* The parameters are not used in this task. */\r
+ ( void ) pvParameters;\r
+\r
+ /* Init USB device */\r
+ portENTER_CRITICAL();\r
+ vInitUSBInterface();\r
+ portEXIT_CRITICAL();\r
+\r
+ /* Process interrupts as they arrive. The ISR takes a snapshot of the \r
+ interrupt status then posts the information on this queue for processing\r
+ at the task level. This simple demo implementation only processes\r
+ a few interrupt sources. */\r
+ for( ;; )\r
+ {\r
+ if( xQueueReceive( xUSBInterruptQueue, &pxMessage, usbSHORT_DELAY ) )\r
+ {\r
+ if( pxMessage->ulISR & AT91C_UDP_EPINT0 )\r
+ {\r
+ /* Process end point 0 interrupt. */\r
+ prvProcessEndPoint0Interrupt( pxMessage );\r
+ }\r
+\r
+ if( pxMessage->ulISR & AT91C_UDP_ENDBUSRES )\r
+ {\r
+ /* Process an end of bus reset interrupt. */\r
+ prvResetEndPoints(); \r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* The ISR did not post any data for us to process on the queue, so\r
+ just generate and send some sample data. */\r
+ if( eDriverState == eREADY_TO_SEND )\r
+ {\r
+ prvTransmitSampleValues();\r
+ }\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvTransmitSampleValues( void )\r
+{\r
+unsigned portLONG ulStatus;\r
+static portLONG lState = usbXUP;\r
+\r
+/* Variables to hold dummy x, y and z joystick axis data. */\r
+static signed portCHAR x = 0, y = 0, z = 0;\r
+\r
+ /* Generate some sample data in the x and y axis - draw a square. */\r
+ switch( lState )\r
+ {\r
+ case usbXUP : x += usbDATA_INC;\r
+ if( x >= usbMAX_COORD )\r
+ {\r
+ lState = usbYUP;\r
+ }\r
+ break;\r
+ \r
+ case usbXDOWN : x -= usbDATA_INC;\r
+ if( x <= -usbMAX_COORD )\r
+ {\r
+ lState = usbYDOWN;\r
+ }\r
+ break;\r
+ \r
+ case usbYUP : y += usbDATA_INC;\r
+ if( y >= usbMAX_COORD )\r
+ {\r
+ lState = usbXDOWN;\r
+ }\r
+ break;\r
+ \r
+ case usbYDOWN : y -= usbDATA_INC;\r
+ if( y <= -usbMAX_COORD )\r
+ {\r
+ lState = usbXUP;\r
+ }\r
+ break;\r
+ }\r
+\r
+ /* Just make the z axis go up and down. */\r
+ z += usbDATA_INC;\r
+\r
+ /* Can we place data in the fifo? */\r
+ if( !( AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ] & AT91C_UDP_TXPKTRDY ) )\r
+ {\r
+ /* Write our sample data to the fifo. */\r
+ AT91C_BASE_UDP->UDP_FDR[ usbEND_POINT_1 ] = x;\r
+ AT91C_BASE_UDP->UDP_FDR[ usbEND_POINT_1 ] = y;\r
+ AT91C_BASE_UDP->UDP_FDR[ usbEND_POINT_1 ] = z;\r
+ \r
+ /* Send the data. */\r
+ portENTER_CRITICAL();\r
+ {\r
+ ulStatus = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ];\r
+ usbCSR_SET_BIT( &ulStatus, ( AT91C_UDP_TXPKTRDY ) );\r
+ AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ] = ulStatus;\r
+ }\r
+ portEXIT_CRITICAL();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvUSBTransmitNull( void )\r
+{\r
+unsigned portLONG ulStatus;\r
+\r
+ /* Wait until the FIFO is free - even though we are not going to use it.\r
+ THERE IS NO TIMEOUT HERE! */\r
+ while( AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] & AT91C_UDP_TXPKTRDY )\r
+ {\r
+ vTaskDelay( usbSHORTEST_DELAY );\r
+ }\r
+\r
+ portENTER_CRITICAL();\r
+ {\r
+ /* Set the length of data to send to equal the index of the next byte\r
+ to send. This will prevent the ACK to this NULL packet causing any\r
+ further data transmissions. */\r
+ pxCharsForTx.ulTotalDataLength = pxCharsForTx.ulNextCharIndex;\r
+\r
+ /* Set the TXPKTRDY bit to cause a transmission with no data. */\r
+ ulStatus = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ];\r
+ usbCSR_SET_BIT( &ulStatus, ( AT91C_UDP_TXPKTRDY ) );\r
+ AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] = ulStatus;\r
+ }\r
+ portEXIT_CRITICAL();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSendStall( void )\r
+{\r
+unsigned portLONG ulStatus;\r
+\r
+ portENTER_CRITICAL();\r
+ {\r
+ /* Force a stall by simply setting the FORCESTALL bit in the CSR. */\r
+ ulStatus = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ];\r
+ usbCSR_SET_BIT( &ulStatus, AT91C_UDP_FORCESTALL );\r
+ AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] = ulStatus;\r
+ }\r
+ portEXIT_CRITICAL();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvResetEndPoints( void )\r
+{\r
+unsigned portLONG ulTemp;\r
+\r
+ eDriverState = eJUST_RESET;\r
+\r
+ /* Reset all the end points. */\r
+ AT91C_BASE_UDP->UDP_RSTEP = usbEND_POINT_RESET_MASK;\r
+ AT91C_BASE_UDP->UDP_RSTEP = ( unsigned portLONG ) 0x00;\r
+\r
+ /* Enable data to be sent and received. */\r
+ AT91C_BASE_UDP->UDP_FADDR = AT91C_UDP_FEN;\r
+\r
+ /* Repair the configuration end point. */\r
+ portENTER_CRITICAL();\r
+ {\r
+ ulTemp = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ];\r
+ usbCSR_SET_BIT( &ulTemp, ( ( unsigned portLONG ) ( AT91C_UDP_EPEDS | AT91C_UDP_EPTYPE_CTRL ) ) );\r
+ AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] = ulTemp;\r
+ AT91F_UDP_EnableIt( AT91C_BASE_UDP, AT91C_UDP_EPINT0 );\r
+ }\r
+ portEXIT_CRITICAL();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvProcessEndPoint0Interrupt( xISRStatus *pxMessage )\r
+{\r
+ if( pxMessage->ulCSR0 & AT91C_UDP_RX_DATA_BK0 )\r
+ { \r
+ /* We only expect to receive zero length data here as ACK's. \r
+ Set the data pointer to the end of the current Tx packet to\r
+ ensure we don't send out any more data. */ \r
+ pxCharsForTx.ulNextCharIndex = pxCharsForTx.ulTotalDataLength;\r
+ }\r
+\r
+ if( pxMessage->ulCSR0 & AT91C_UDP_TXCOMP )\r
+ {\r
+ /* We received a TX complete interrupt. What we do depends on\r
+ what we sent to get this interrupt. */\r
+\r
+ if( eDriverState == eJUST_GOT_CONFIG )\r
+ {\r
+ /* We sent an acknowledgement of a SET_CONFIG request. We\r
+ are now at the end of the enumeration. */\r
+ AT91C_BASE_UDP->UDP_GLBSTATE = AT91C_UDP_CONFG;\r
+\r
+ /* Read the end point for data transfer. */\r
+ portENTER_CRITICAL();\r
+ {\r
+ unsigned portLONG ulTemp;\r
+\r
+ ulTemp = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ]; \r
+ usbCSR_SET_BIT( &ulTemp, AT91C_UDP_EPEDS | AT91C_UDP_EPTYPE_INT_IN );\r
+ AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ] = ulTemp; \r
+ AT91F_UDP_EnableIt( AT91C_BASE_UDP, AT91C_UDP_EPINT1 );\r
+ }\r
+ portEXIT_CRITICAL();\r
+\r
+ eDriverState = eREADY_TO_SEND;\r
+ } \r
+ else if( eDriverState == eJUST_GOT_ADDRESS )\r
+ {\r
+ /* We sent an acknowledgement of a SET_ADDRESS request. Move\r
+ to the addressed state. */\r
+ if( ulReceivedAddress != ( unsigned portLONG ) 0 )\r
+ { \r
+ AT91C_BASE_UDP->UDP_GLBSTATE = AT91C_UDP_FADDEN;\r
+ }\r
+ else\r
+ {\r
+ AT91C_BASE_UDP->UDP_GLBSTATE = 0;\r
+ } \r
+\r
+ AT91C_BASE_UDP->UDP_FADDR = ( AT91C_UDP_FEN | ulReceivedAddress ); \r
+ eDriverState = eNOTHING;\r
+ }\r
+ else\r
+ { \r
+ /* The TXCOMP was not for any special type of transmission. See\r
+ if there is any more data to send. */\r
+ prvSendNextSegment();\r
+ }\r
+ }\r
+\r
+ if( pxMessage->ulCSR0 & AT91C_UDP_RXSETUP )\r
+ {\r
+ xUSB_REQUEST xRequest;\r
+ unsigned portCHAR ucRequest;\r
+ unsigned portLONG ulRxBytes;\r
+\r
+ /* A data packet is available. */ \r
+ ulRxBytes = pxMessage->ulCSR0 >> 16;\r
+ ulRxBytes &= usbRX_COUNT_MASK;\r
+\r
+ if( ulRxBytes >= usbEXPECTED_NUMBER_OF_BYTES )\r
+ {\r
+ /* Create an xUSB_REQUEST variable from the raw bytes array. */\r
+\r
+ xRequest.ucReqType = pxMessage->ucFifoData[ usbREQUEST_TYPE_INDEX ];\r
+ xRequest.ucRequest = pxMessage->ucFifoData[ usbREQUEST_INDEX ];\r
+\r
+ /* NOT PORTABLE CODE! */\r
+ xRequest.usValue = pxMessage->ucFifoData[ usbVALUE_HIGH_BYTE ];\r
+ xRequest.usValue <<= 8;\r
+ xRequest.usValue |= pxMessage->ucFifoData[ usbVALUE_LOW_BYTE ];\r
+ \r
+ xRequest.usIndex = pxMessage->ucFifoData[ usbINDEX_HIGH_BYTE ];\r
+ xRequest.usIndex <<= 8;\r
+ xRequest.usIndex |= pxMessage->ucFifoData[ usbINDEX_LOW_BYTE ];\r
+ \r
+ xRequest.usLength = pxMessage->ucFifoData[ usbLENGTH_HIGH_BYTE ];\r
+ xRequest.usLength <<= 8;\r
+ xRequest.usLength |= pxMessage->ucFifoData[ usbLENGTH_LOW_BYTE ];\r
+ \r
+ /* Manipulate the ucRequestType and the ucRequest parameters to \r
+ generate a zero based request selection. This is just done to \r
+ break up the requests into subsections for clarity. The \r
+ alternative would be to have more huge switch statement that would\r
+ be difficult to optimise. */\r
+ ucRequest = ( ( xRequest.ucReqType & 0x60 ) >> 3 );\r
+ ucRequest |= ( xRequest.ucReqType & 0x03 );\r
+\r
+ switch( ucRequest )\r
+ {\r
+ case usbSTANDARD_DEVICE_REQUEST: \r
+ /* Standard Device request */\r
+ prvHandleStandardDeviceRequest( &xRequest );\r
+ break;\r
+ \r
+ case usbSTANDARD_INTERFACE_REQUEST: \r
+ /* Standard Interface request */\r
+ prvHandleStandardInterfaceRequest( &xRequest );\r
+ break;\r
+ \r
+ case usbSTANDARD_END_POINT_REQUEST: \r
+ /* Standard Endpoint request */\r
+ prvHandleStandardEndPointRequest( &xRequest );\r
+ break;\r
+ \r
+ case usbCLASS_INTERFACE_REQUEST: \r
+ /* Class Interface request */\r
+ prvHandleClassInterfaceRequest( &xRequest );\r
+ break;\r
+ \r
+ default: /* This is not something we want to respond to. */\r
+ prvSendStall(); \r
+ }\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvGetStandardDeviceDescriptor( xUSB_REQUEST *pxRequest )\r
+{\r
+ /* The type is in the high byte. Return whatever has been requested. */\r
+ switch( ( pxRequest->usValue & 0xff00 ) >> 8 )\r
+ {\r
+ case usbDESCRIPTOR_TYPE_DEVICE:\r
+ prvSendControlData( ( unsigned portCHAR * ) &pxDeviceDescriptor, pxRequest->usLength, sizeof( pxDeviceDescriptor ), pdTRUE );\r
+ break;\r
+ \r
+ case usbDESCRIPTOR_TYPE_CONFIGURATION:\r
+ prvSendControlData( ( unsigned portCHAR * ) &( pxConfigDescriptor ), pxRequest->usLength, sizeof( pxConfigDescriptor ), pdTRUE );\r
+ break;\r
+\r
+ case usbDESCRIPTOR_TYPE_STRING:\r
+\r
+ /* The index to the string descriptor is the lower byte. */\r
+ switch( pxRequest->usValue & 0xff )\r
+ { \r
+ case usbLANGUAGE_STRING:\r
+ prvSendControlData( ( unsigned portCHAR * ) &pxLanguageStringDescriptor, pxRequest->usLength, sizeof(pxLanguageStringDescriptor), pdTRUE );\r
+ break;\r
+\r
+ case usbMANUFACTURER_STRING:\r
+ prvSendControlData( ( unsigned portCHAR * ) &pxManufacturerStringDescriptor, pxRequest->usLength, sizeof( pxManufacturerStringDescriptor ), pdTRUE );\r
+ break;\r
+\r
+ case usbPRODUCT_STRING:\r
+ prvSendControlData( ( unsigned portCHAR * ) &pxProductStringDescriptor, pxRequest->usLength, sizeof( pxProductStringDescriptor ), pdTRUE );\r
+ break;\r
+\r
+ case usbCONFIGURATION_STRING:\r
+ prvSendControlData( ( unsigned portCHAR * ) &pxConfigurationStringDescriptor, pxRequest->usLength, sizeof( pxConfigurationStringDescriptor ), pdTRUE );\r
+ break;\r
+\r
+ case usbINTERFACE_STRING:\r
+ prvSendControlData( ( unsigned portCHAR * ) &pxInterfaceStringDescriptor, pxRequest->usLength, sizeof( pxInterfaceStringDescriptor ), pdTRUE );\r
+ break;\r
+\r
+ default:\r
+ /* Don't know what this string is. */\r
+ prvSendStall();\r
+ break;\r
+ }\r
+\r
+ break;\r
+\r
+ default:\r
+ /* We are not responding to anything else. */\r
+ prvSendStall();\r
+ break;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvHandleStandardDeviceRequest( xUSB_REQUEST *pxRequest )\r
+{\r
+unsigned portSHORT usStatus = 0;\r
+\r
+ switch( pxRequest->ucRequest )\r
+ {\r
+ case usbGET_STATUS_REQUEST:\r
+ /* Just send two byte dummy status. */\r
+ prvSendControlData( ( unsigned portCHAR * ) &usStatus, sizeof( usStatus ), sizeof( usStatus ), pdFALSE );\r
+ break;\r
+\r
+ case usbGET_DESCRIPTOR_REQUEST:\r
+ /* Send device descriptor */\r
+ prvGetStandardDeviceDescriptor( pxRequest );\r
+ break;\r
+\r
+ case usbGET_CONFIGURATION_REQUEST:\r
+ /* Send selected device configuration */\r
+ prvSendControlData( ( unsigned portCHAR * ) &ucUSBConfig, sizeof( ucUSBConfig ), sizeof( ucUSBConfig ), pdFALSE );\r
+ break;\r
+\r
+ case usbSET_FEATURE_REQUEST:\r
+ prvUSBTransmitNull();\r
+ break;\r
+\r
+ case usbSET_ADDRESS_REQUEST:\r
+ \r
+ /* Acknowledge the SET_ADDRESS, but (according to the manual) we\r
+ cannot actually move to the addressed state until we get a TXCOMP\r
+ interrupt from this NULL packet. Therefore we just remember the\r
+ address and set our state so we know we have received the address. */\r
+ prvUSBTransmitNull(); \r
+ eDriverState = eJUST_GOT_ADDRESS; \r
+ ulReceivedAddress = ( unsigned portLONG ) pxRequest->usValue;\r
+ break;\r
+\r
+ case usbSET_CONFIGURATION_REQUEST:\r
+\r
+ /* Acknowledge the SET_CONFIGURATION, but (according to the manual) \r
+ we cannot actually move to the configured state until we get a \r
+ TXCOMP interrupt from this NULL packet. Therefore we just remember the\r
+ config and set our state so we know we have received the go ahead. */ \r
+ ucUSBConfig = ( unsigned portCHAR ) ( pxRequest->usValue & 0xff );\r
+ eDriverState = eJUST_GOT_CONFIG;\r
+ prvUSBTransmitNull();\r
+ break;\r
+\r
+ default:\r
+\r
+ /* We don't answer to anything else. */\r
+ prvSendStall();\r
+ break;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvHandleClassInterfaceRequest( xUSB_REQUEST *pxRequest )\r
+{\r
+ switch( pxRequest->ucRequest )\r
+ {\r
+ case usbSET_IDLE_REQUEST:\r
+ prvUSBTransmitNull();\r
+ break;\r
+\r
+ /* This minimal implementation ignores these. */\r
+ case usbGET_REPORT_REQUEST:\r
+ case usbGET_IDLE_REQUEST:\r
+ case usbGET_PROTOCOL_REQUEST:\r
+ case usbSET_REPORT_REQUEST:\r
+ case usbSET_PROTOCOL_REQUEST: \r
+ default:\r
+\r
+ prvSendStall();\r
+ break;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvGetStandardInterfaceDescriptor( xUSB_REQUEST *pxRequest )\r
+{\r
+ switch( ( pxRequest->usValue & ( unsigned portSHORT ) 0xff00 ) >> 8 )\r
+ {\r
+ case usbHID_REPORT_DESCRIPTOR:\r
+ prvSendControlData( ( unsigned portCHAR * ) pxReportDescriptor, pxRequest->usLength, sizeof( pxReportDescriptor ), pdTRUE );\r
+ break;\r
+\r
+ default:\r
+\r
+ /* Don't expect to send any others. */\r
+ prvSendStall();\r
+ break;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvHandleStandardInterfaceRequest( xUSB_REQUEST *pxRequest )\r
+{\r
+unsigned portSHORT usStatus = 0;\r
+\r
+ switch( pxRequest->ucRequest )\r
+ {\r
+ case usbGET_STATUS_REQUEST:\r
+ /* Send dummy 2 bytes. */\r
+ prvSendControlData( ( unsigned portCHAR * ) &usStatus, sizeof( usStatus ), sizeof( usStatus ), pdFALSE );\r
+ break;\r
+\r
+ case usbGET_DESCRIPTOR_REQUEST:\r
+ prvGetStandardInterfaceDescriptor( pxRequest ); \r
+ break;\r
+\r
+ /* This minimal implementation does not respond to these. */\r
+ case usbGET_INTERFACE_REQUEST:\r
+ case usbSET_FEATURE_REQUEST:\r
+ case usbSET_INTERFACE_REQUEST: \r
+\r
+ default:\r
+ prvSendStall();\r
+ break;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvHandleStandardEndPointRequest( xUSB_REQUEST *pxRequest )\r
+{\r
+ switch( pxRequest->ucRequest )\r
+ {\r
+ /* This minimal implementation does not expect to respond to these. */\r
+ case usbGET_STATUS_REQUEST:\r
+ case usbCLEAR_FEATURE_REQUEST: \r
+ case usbSET_FEATURE_REQUEST:\r
+\r
+ default: \r
+ prvSendStall();\r
+ break;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vInitUSBInterface( void )\r
+{\r
+volatile unsigned portLONG ulTemp;\r
+\r
+ /* Create the queue used to communicate between the USB ISR and task. */\r
+ xUSBInterruptQueue = xQueueCreate( usbQUEUE_LENGTH + 1, sizeof( xISRStatus * ) );\r
+\r
+ /* Initialise a few state variables. */\r
+ pxCharsForTx.ulNextCharIndex = ( unsigned portLONG ) 0;\r
+ ucUSBConfig = ( unsigned portCHAR ) 0;\r
+ eDriverState = eNOTHING;\r
+\r
+ /* HARDWARE SETUP */\r
+\r
+ /* Set the PLL USB Divider */\r
+ AT91C_BASE_CKGR->CKGR_PLLR |= AT91C_CKGR_USBDIV_1;\r
+\r
+ /* Enables the 48MHz USB clock UDPCK and System Peripheral USB Clock. */\r
+ AT91C_BASE_PMC->PMC_SCER = AT91C_PMC_UDP;\r
+ AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_UDP);\r
+\r
+ /* Setup the PIO for the USB pull up resistor. */\r
+ AT91F_PIO_CfgOutput(AT91C_BASE_PIOA,AT91C_PIO_PA16);\r
+\r
+ /* Start without the pullup - this will get set at the end of this \r
+ function. */\r
+ AT91F_PIO_SetOutput( AT91C_BASE_PIOA, AT91C_PIO_PA16 );\r
+\r
+ /* When using the USB debugger the peripheral registers do not always get\r
+ set to the correct default values. To make sure set the relevant registers\r
+ manually here. */\r
+ AT91C_BASE_UDP->UDP_IDR = ( unsigned portLONG ) 0xffffffff;\r
+ AT91C_BASE_UDP->UDP_ICR = ( unsigned portLONG ) 0xffffffff;\r
+ AT91C_BASE_UDP->UDP_CSR[ 0 ] = ( unsigned portLONG ) 0x00;\r
+ AT91C_BASE_UDP->UDP_CSR[ 1 ] = ( unsigned portLONG ) 0x00;\r
+ AT91C_BASE_UDP->UDP_GLBSTATE = 0;\r
+ AT91C_BASE_UDP->UDP_FADDR = 0;\r
+\r
+ /* Enable the transceiver. */\r
+ AT91C_UDP_TRANSCEIVER_ENABLE = 0;\r
+\r
+ /* Enable the USB interrupts - other interrupts get enabled as the \r
+ enumeration process progresses. */\r
+ AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_UDP, usbINTERRUPT_PRIORITY, AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE, ( void (*)( void ) ) vUSBISREntry );\r
+ AT91F_AIC_EnableIt( AT91C_BASE_AIC, AT91C_ID_UDP );\r
+\r
+ /* Wait a short while before making our presence known. */\r
+ vTaskDelay( usbINIT_DELAY );\r
+ AT91F_PIO_ClearOutput(AT91C_BASE_PIOA, AT91C_PIO_PA16 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSendControlData( unsigned portCHAR *pucData, unsigned portSHORT usRequestedLength, unsigned portLONG ulLengthToSend, portLONG lSendingDescriptor )\r
+{\r
+ if( ( ( unsigned portLONG ) usRequestedLength < ulLengthToSend ) )\r
+ {\r
+ /* Cap the data length to that requested. */\r
+ ulLengthToSend = ( unsigned portSHORT ) usRequestedLength;\r
+ }\r
+ else if( ( ulLengthToSend < ( unsigned portLONG ) usRequestedLength ) && lSendingDescriptor )\r
+ {\r
+ /* We are sending a descriptor. If the descriptor is an exact \r
+ multiple of the FIFO length then it will have to be terminated\r
+ with a NULL packet. Set the state to indicate this if\r
+ necessary. */\r
+ if( ( ulLengthToSend % usbFIFO_LENGTH ) == 0 )\r
+ {\r
+ eDriverState = eSENDING_EVEN_DESCRIPTOR;\r
+ }\r
+ }\r
+\r
+ /* Here we assume that the previous message has been sent. THERE IS NO\r
+ BUFFER OVERFLOW PROTECTION HERE.\r
+\r
+ Copy the data to send into the buffer as we cannot send it all at once\r
+ (if it is greater than 8 bytes in length). */\r
+ memcpy( pxCharsForTx.ucTxBuffer, pucData, ulLengthToSend );\r
+\r
+ /* Reinitialise the buffer index so we start sending from the start of \r
+ the data. */\r
+ pxCharsForTx.ulTotalDataLength = ulLengthToSend;\r
+ pxCharsForTx.ulNextCharIndex = ( unsigned portLONG ) 0;\r
+\r
+ /* Send the first 8 bytes now. The rest will get sent in response to \r
+ TXCOMP interrupts. */\r
+ prvSendNextSegment();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSendNextSegment( void )\r
+{\r
+volatile unsigned portLONG ulNextLength, ulStatus, ulLengthLeftToSend;\r
+\r
+ /* Is there any data to send? */\r
+ if( pxCharsForTx.ulTotalDataLength > pxCharsForTx.ulNextCharIndex )\r
+ {\r
+ ulLengthLeftToSend = pxCharsForTx.ulTotalDataLength - pxCharsForTx.ulNextCharIndex;\r
+ \r
+ /* We can only send 8 bytes to the fifo at a time. */\r
+ if( ulLengthLeftToSend > usbFIFO_LENGTH )\r
+ {\r
+ ulNextLength = usbFIFO_LENGTH;\r
+ }\r
+ else\r
+ {\r
+ ulNextLength = ulLengthLeftToSend;\r
+ }\r
+\r
+ /* Wait until we can place data in the fifo. THERE IS NO TIMEOUT\r
+ HERE! */\r
+ while( AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] & AT91C_UDP_TXPKTRDY )\r
+ {\r
+ vTaskDelay( usbSHORTEST_DELAY );\r
+ }\r
+\r
+ /* Write the data to the FIFO. */\r
+ while( ulNextLength > ( unsigned portLONG ) 0 )\r
+ {\r
+ AT91C_BASE_UDP->UDP_FDR[ usbEND_POINT_0 ] = pxCharsForTx.ucTxBuffer[ pxCharsForTx.ulNextCharIndex ];\r
+ \r
+ ulNextLength--;\r
+ pxCharsForTx.ulNextCharIndex++;\r
+ }\r
+ \r
+ /* Start the transmission. */\r
+ portENTER_CRITICAL();\r
+ {\r
+ ulStatus = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ];\r
+ usbCSR_SET_BIT( &ulStatus, ( ( unsigned portLONG ) 0x10 ) );\r
+ AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] = ulStatus;\r
+ }\r
+ portEXIT_CRITICAL();\r
+ }\r
+ else\r
+ {\r
+ /* There is no data to send. If we were sending a descriptor and the \r
+ descriptor was an exact multiple of the max packet size then we need\r
+ to send a null to terminate the transmission. */\r
+ if( eDriverState == eSENDING_EVEN_DESCRIPTOR )\r
+ {\r
+ prvUSBTransmitNull();\r
+ eDriverState = eNOTHING;\r
+ }\r
+ }\r
+}\r
+\r
+\r
+\r
--- /dev/null
+#ifndef USB_DEMO_H\r
+#define USB_DEMO_H\r
+\r
+void vUSBDemoTask( void *pvParameters );\r
+\r
+\r
+#endif\r
+\r
--- /dev/null
+ RSEG ICODE:CODE\r
+ CODE32\r
+\r
+ EXTERN vUSB_ISR\r
+ PUBLIC vUSBISREntry\r
+\r
+; Wrapper for the USB interrupt service routine. This can cause a\r
+; context switch so requires an assembly wrapper.\r
+\r
+; Defines the portSAVE_CONTEXT and portRESTORE_CONTEXT macros.\r
+#include "ISR_Support.h"\r
+\r
+vUSBISREntry:\r
+\r
+ portSAVE_CONTEXT ; Save the context of the current task.\r
+\r
+ bl vUSB_ISR ; Call the ISR routine.\r
+\r
+ portRESTORE_CONTEXT ; Restore the context of the current task -\r
+ ; which may be different to the task that\r
+ ; was interrupted.\r
+\r
+ END\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* \r
+ NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.\r
+ The processor MUST be in supervisor mode when vTaskStartScheduler is \r
+ called. The demo applications included in the FreeRTOS.org download switch\r
+ to supervisor mode prior to main being called. If you are not using one of\r
+ these demo application projects then ensure Supervisor mode is used.\r
+*/\r
+\r
+/*\r
+ * Creates all the demo application tasks, then starts the scheduler. The WEB\r
+ * documentation provides more details of the demo application tasks. The SAM7\r
+ * includes a sample USB that emulates a Joystick input to a USB host.\r
+ * \r
+ * Main.c also creates a task called "Check". This only executes every three \r
+ * seconds but has the highest priority so is guaranteed to get processor time. \r
+ * Its main function is to check that all the other tasks are still operational.\r
+ * Each task (other than the "flash" tasks) maintains a unique count that is \r
+ * incremented each time the task successfully completes its function. Should \r
+ * any error occur within such a task the count is permanently halted. The \r
+ * check task inspects the count of each task to ensure it has changed since\r
+ * the last time the check task executed. If all the count variables have \r
+ * changed all the tasks are still executing error free, and the check task\r
+ * toggles the onboard LED. Should any task contain an error at any time \r
+ * the LED toggle rate will change from 3 seconds to 500ms.\r
+ *\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdlib.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo application includes. */\r
+#include "flash.h"\r
+#include "integer.h"\r
+#include "PollQ.h"\r
+#include "BlockQ.h"\r
+#include "semtest.h"\r
+#include "dynamic.h"\r
+#include "partest.h"\r
+#include "comtest2.h"\r
+#include "USB/USBSample.h"\r
+\r
+/* Priorities for the demo application tasks. */\r
+#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 )\r
+#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainUSB_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+\r
+/* Constants required by the 'Check' task. */\r
+#define mainNO_ERROR_FLASH_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS )\r
+#define mainERROR_FLASH_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS )\r
+#define mainCHECK_TASK_LED ( 3 )\r
+\r
+/* Constants for the ComTest tasks. */\r
+#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 115200 )\r
+#define mainCOM_TEST_LED ( 4 ) /* Off the board. */\r
+\r
+/*\r
+ * The task that executes at the highest priority and calls \r
+ * prvCheckOtherTasksAreStillRunning(). See the description at the top\r
+ * of the file.\r
+ */\r
+static void vErrorChecks( void *pvParameters );\r
+\r
+/*\r
+ * Configure the processor for use with the Atmel demo board. Setup is minimal\r
+ * as the low level init function (called from the startup asm file) takes care\r
+ * of most things.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*\r
+ * Checks that all the demo application tasks are still executing without error\r
+ * - as described at the top of the file.\r
+ */\r
+static portLONG prvCheckOtherTasksAreStillRunning( void );\r
+\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Starts all the other tasks, then starts the scheduler. \r
+ */\r
+void main( void )\r
+{\r
+ /* Setup any hardware that has not already been configured by the low\r
+ level init routines. */\r
+ prvSetupHardware();\r
+\r
+ /* Initialise the LED outputs for use by the demo application tasks. */\r
+ vParTestInitialise();\r
+\r
+ /* Start all the standard demo application tasks. */\r
+ vStartIntegerMathTasks( tskIDLE_PRIORITY );\r
+ vStartLEDFlashTasks( mainLED_TASK_PRIORITY );\r
+ vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
+ vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
+ vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
+ vStartDynamicPriorityTasks();\r
+ vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED );\r
+ \r
+ /* Also start the USB demo which is just for the SAM7. */\r
+ xTaskCreate( vUSBDemoTask, "USB", configMINIMAL_STACK_SIZE, NULL, mainUSB_PRIORITY, NULL );\r
+ \r
+ /* Start the check task - which is defined in this file. */\r
+ xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
+\r
+ /* Start the scheduler.\r
+\r
+ NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.\r
+ The processor MUST be in supervisor mode when vTaskStartScheduler is \r
+ called. The demo applications included in the FreeRTOS.org download switch\r
+ to supervisor mode prior to main being called. If you are not using one of\r
+ these demo application projects then ensure Supervisor mode is used here. */\r
+\r
+ vTaskStartScheduler();\r
+\r
+ /* We should never get here as control is now taken by the scheduler. */\r
+ return;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+ /* When using the JTAG debugger the hardware is not always initialised to\r
+ the correct default state. This line just ensures that this does not\r
+ cause all interrupts to be masked at the start. */\r
+ AT91C_BASE_AIC->AIC_EOICR = 0;\r
+ \r
+ /* Most setup is performed by the low level init function called from the \r
+ startup asm file. */\r
+\r
+ /* Configure the PIO Lines corresponding to LED1 to LED4 to be outputs as \r
+ well as the UART Tx line. */\r
+ AT91F_PIO_CfgOutput( AT91C_BASE_PIOA, LED_MASK );\r
+ \r
+ /* Enable the peripheral clock. */\r
+ AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, 1 << AT91C_ID_PIOA );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vErrorChecks( void *pvParameters )\r
+{\r
+portTickType xDelayPeriod = mainNO_ERROR_FLASH_PERIOD;\r
+\r
+ /* The parameters are not used in this task. */\r
+ ( void ) pvParameters;\r
+\r
+ /* Cycle for ever, delaying then checking all the other tasks are still\r
+ operating without error. If an error is detected then the delay period\r
+ is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so\r
+ the on board LED flash rate will increase. */\r
+\r
+ for( ;; )\r
+ {\r
+ /* Delay until it is time to execute again. */\r
+ vTaskDelay( xDelayPeriod );\r
+ \r
+ /* Check all the standard demo application tasks are executing without \r
+ error. */\r
+ if( prvCheckOtherTasksAreStillRunning() != pdPASS )\r
+ {\r
+ /* An error has been detected in one of the tasks - flash faster. */\r
+ xDelayPeriod = mainERROR_FLASH_PERIOD;\r
+ }\r
+ \r
+ vParTestToggleLED( mainCHECK_TASK_LED );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portLONG prvCheckOtherTasksAreStillRunning( void )\r
+{\r
+portLONG lReturn = ( portLONG ) pdPASS;\r
+\r
+ /* Check all the demo tasks (other than the flash tasks) to ensure\r
+ that they are all still running, and that none of them have detected\r
+ an error. */\r
+\r
+ if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ lReturn = ( portLONG ) pdFAIL;\r
+ }\r
+\r
+ if( xArePollingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ lReturn = ( portLONG ) pdFAIL;\r
+ }\r
+\r
+ if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ lReturn = ( portLONG ) pdFAIL;\r
+ }\r
+\r
+ if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ lReturn = ( portLONG ) pdFAIL;\r
+ }\r
+\r
+ if( xAreComTestTasksStillRunning() != pdTRUE )\r
+ {\r
+ lReturn = ( portLONG ) pdFAIL;\r
+ }\r
+\r
+ if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )\r
+ {\r
+ lReturn = ( portLONG ) pdFAIL;\r
+ }\r
+\r
+ return lReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
--- /dev/null
+// ---------------------------------------------------------\r
+// ATMEL Microcontroller Software Support - ROUSSET -\r
+// ---------------------------------------------------------\r
+// The software is delivered "AS IS" without warranty or \r
+// condition of any kind, either express, implied or \r
+// statutory. This includes without limitation any warranty \r
+// or condition with respect to merchantability or fitness \r
+// for any particular purpose, or against the infringements of\r
+// intellectual property rights of others.\r
+// ---------------------------------------------------------\r
+// File: SAM7.mac\r
+//\r
+// User setup file for CSPY debugger to simulate interrupt\r
+// driven Fibonacchi data input. \r
+// 1.1 16/Jun/04 JPP : Creation\r
+//\r
+// $Revision: 1.3 $\r
+//\r
+// ---------------------------------------------------------\r
+\r
+__var i;\r
+__var pt;\r
+\r
+execUserPreload()\r
+{\r
+//* Set the RAM memory at 0x0020 0000 for code AT 0 flash area \r
+ CheckRemap();\r
+//* Get the Chip ID (AT91C_DBGU_C1R & AT91C_DBGU_C2R\r
+ i=__readMemory32(0xFFFFF240,"Memory");\r
+ __message " ---------------------------------------- Chip ID 0x",i:%X; \r
+ i=__readMemory32(0xFFFFF244,"Memory");\r
+ __message " ---------------------------------------- Extention 0x",i:%X; \r
+//* Get the chip status\r
+\r
+//* Init AIC\r
+ AIC();\r
+//* Watchdog Disable\r
+ Watchdog();\r
+\r
+}\r
+\r
+\r
+//-----------------------------------------------------------------------------\r
+// Watchdog\r
+//-------------------------------\r
+// Normally, the Watchdog is enable at the reset for load it's preferable to\r
+// Disable.\r
+//-----------------------------------------------------------------------------\r
+Watchdog()\r
+{\r
+//* Watchdog Disable\r
+// AT91C_BASE_WDTC->WDTC_WDMR= AT91C_SYSC_WDDIS;\r
+ __writeMemory32(0x00008000,0xFFFFFD44,"Memory");\r
+ __message "------------------------------- Watchdog Disable ----------------------------------------"; \r
+}\r
+\r
+\r
+//-----------------------------------------------------------------------------\r
+// Check Remap\r
+//-------------\r
+//-----------------------------------------------------------------------------\r
+CheckRemap()\r
+{\r
+//* Read the value at 0x0\r
+ i=__readMemory32(0x00000000,"Memory");\r
+ i=i+1;\r
+ __writeMemory32(i,0x00,"Memory");\r
+ pt=__readMemory32(0x00000000,"Memory");\r
+ \r
+ if (i == pt) \r
+ {\r
+ __message "------------------------------- The Remap is done ----------------------------------------"; \r
+//* Toggel RESET The remap\r
+ __writeMemory32(0x00000001,0xFFFFFF00,"Memory");\r
+ \r
+ } else { \r
+ __message "------------------------------- The Remap is NOT -----------------------------------------"; \r
+ }\r
+\r
+}\r
+\r
+\r
+execUserSetup()\r
+{\r
+ ini();\r
+ __message "-------------------------------Set PC ----------------------------------------"; \r
+ __writeMemory32(0x00000000,0xB4,"Register");\r
+}\r
+\r
+\r
+\r
+//-----------------------------------------------------------------------------\r
+// Reset the Interrupt Controller\r
+//-------------------------------\r
+// Normally, the code is executed only if a reset has been actually performed.\r
+// So, the AIC initialization resumes at setting up the default vectors.\r
+//-----------------------------------------------------------------------------\r
+AIC()\r
+{\r
+// Mask All interrupt pAic->AIC_IDCR = 0xFFFFFFFF;\r
+ __writeMemory32(0xFFFFFFFF,0xFFFFF124,"Memory");\r
+\r
+ for (i=0;i < 8; i++)\r
+ {\r
+ // AT91C_BASE_AIC->AIC_EOICR\r
+ pt = __readMemory32(0xFFFFF130,"Memory");\r
+ \r
+ }\r
+ __message "------------------------------- AIC INIT ---------------------------------------------"; \r
+}\r
+\r
+ini()\r
+{\r
+__writeMemory32(0x0,0x00,"Register");\r
+__writeMemory32(0x0,0x04,"Register");\r
+__writeMemory32(0x0,0x08,"Register");\r
+__writeMemory32(0x0,0x0C,"Register");\r
+__writeMemory32(0x0,0x10,"Register");\r
+__writeMemory32(0x0,0x14,"Register");\r
+__writeMemory32(0x0,0x18,"Register");\r
+__writeMemory32(0x0,0x1C,"Register");\r
+__writeMemory32(0x0,0x20,"Register");\r
+__writeMemory32(0x0,0x24,"Register");\r
+__writeMemory32(0x0,0x28,"Register");\r
+__writeMemory32(0x0,0x2C,"Register");\r
+__writeMemory32(0x0,0x30,"Register");\r
+__writeMemory32(0x0,0x34,"Register");\r
+__writeMemory32(0x0,0x38,"Register");\r
+\r
+// Set CPSR\r
+__writeMemory32(0x0D3,0x98,"Register");\r
+\r
+\r
+}\r
+\r
+RG()\r
+{\r
+\r
+i=__readMemory32(0x00,"Register"); __message "R00 0x",i:%X; \r
+i=__readMemory32(0x04,"Register"); __message "R01 0x",i:%X; \r
+i=__readMemory32(0x08,"Register"); __message "R02 0x",i:%X; \r
+i=__readMemory32(0x0C,"Register"); __message "R03 0x",i:%X; \r
+i=__readMemory32(0x10,"Register"); __message "R04 0x",i:%X; \r
+i=__readMemory32(0x14,"Register"); __message "R05 0x",i:%X; \r
+i=__readMemory32(0x18,"Register"); __message "R06 0x",i:%X; \r
+i=__readMemory32(0x1C,"Register"); __message "R07 0x",i:%X; \r
+i=__readMemory32(0x20,"Register"); __message "R08 0x",i:%X; \r
+i=__readMemory32(0x24,"Register"); __message "R09 0x",i:%X; \r
+i=__readMemory32(0x28,"Register"); __message "R10 0x",i:%X; \r
+i=__readMemory32(0x2C,"Register"); __message "R11 0x",i:%X; \r
+i=__readMemory32(0x30,"Register"); __message "R12 0x",i:%X; \r
+i=__readMemory32(0x34,"Register"); __message "R13 0x",i:%X; \r
+i=__readMemory32(0x38,"Register"); __message "R14 0x",i:%X; \r
+i=__readMemory32(0x3C,"Register"); __message "R13 SVC 0x",i:%X; \r
+i=__readMemory32(0x40,"Register"); __message "R14 SVC 0x",i:%X; \r
+i=__readMemory32(0x44,"Register"); __message "R13 ABT 0x",i:%X; \r
+i=__readMemory32(0x48,"Register"); __message "R14 ABT 0x",i:%X; \r
+i=__readMemory32(0x4C,"Register"); __message "R13 UND 0x",i:%X; \r
+i=__readMemory32(0x50,"Register"); __message "R14 UND 0x",i:%X; \r
+i=__readMemory32(0x54,"Register"); __message "R13 IRQ 0x",i:%X; \r
+i=__readMemory32(0x58,"Register"); __message "R14 IRQ 0x",i:%X; \r
+i=__readMemory32(0x5C,"Register"); __message "R08 FIQ 0x",i:%X; \r
+i=__readMemory32(0x60,"Register"); __message "R09 FIQ 0x",i:%X; \r
+i=__readMemory32(0x64,"Register"); __message "R10 FIQ 0x",i:%X; \r
+i=__readMemory32(0x68,"Register"); __message "R11 FIQ 0x",i:%X; \r
+i=__readMemory32(0x6C,"Register"); __message "R12 FIQ 0x",i:%X; \r
+i=__readMemory32(0x70,"Register"); __message "R13 FIQ 0x",i:%X; \r
+i=__readMemory32(0x74,"Register"); __message "R14 FIQ0x",i:%X; \r
+i=__readMemory32(0x98,"Register"); __message "CPSR ",i:%X; \r
+i=__readMemory32(0x94,"Register"); __message "SPSR ",i:%X; \r
+i=__readMemory32(0x9C,"Register"); __message "SPSR ABT ",i:%X; \r
+i=__readMemory32(0xA0,"Register"); __message "SPSR ABT ",i:%X; \r
+i=__readMemory32(0xA4,"Register"); __message "SPSR UND ",i:%X; \r
+i=__readMemory32(0xA8,"Register"); __message "SPSR IRQ ",i:%X; \r
+i=__readMemory32(0xAC,"Register"); __message "SPSR FIQ ",i:%X; \r
+\r
+i=__readMemory32(0xB4,"Register"); __message "PC 0x",i:%X; \r
+\r
+}\r
+\r
--- /dev/null
+// ---------------------------------------------------------\r
+// ATMEL Microcontroller Software Support - ROUSSET -\r
+// ---------------------------------------------------------\r
+// The software is delivered "AS IS" without warranty or \r
+// condition of any kind, either express, implied or \r
+// statutory. This includes without limitation any warranty \r
+// or condition with respect to merchantability or fitness \r
+// for any particular purpose, or against the infringements of\r
+// intellectual property rights of others.\r
+// ---------------------------------------------------------\r
+// File: SAM7_RAM.mac\r
+//\r
+// User setup file for CSPY debugger to simulate interrupt\r
+// driven Fibonacchi data input. \r
+// 1.1 16/Jun/04 JPP : Creation\r
+// 1.2 27/Aug/04 JPP : PLL setting\r
+//\r
+// $Revision: 1.3 $\r
+//\r
+// ---------------------------------------------------------\r
+\r
+__var i;\r
+__var pt;\r
+\r
+execUserPreload()\r
+{\r
+//* \r
+ PllSetting();\r
+//* Set the RAM memory at 0x0020 0000 for code AT 0 flash area \r
+ CheckNoRemap();\r
+//* Get the Chip ID (AT91C_DBGU_C1R & AT91C_DBGU_C2R\r
+ i=__readMemory32(0xFFFFF240,"Memory");\r
+ __message " ---------------------------------------- Chip ID 0x",i:%X; \r
+ i=__readMemory32(0xFFFFF244,"Memory");\r
+ __message " ---------------------------------------- Extention 0x",i:%X; \r
+ i=__readMemory32(0xFFFFFF6C,"Memory");\r
+ __message " ---------------------------------------- Flash Version 0x",i:%X; \r
+//* Get the chip status\r
+\r
+//* Init AIC\r
+ AIC();\r
+//* Watchdog Disable\r
+ Watchdog();\r
+}\r
+//-----------------------------------------------------------------------------\r
+// PllSetting\r
+//-------------------------------\r
+// Set PLL\r
+//-----------------------------------------------------------------------------\r
+PllSetting()\r
+{\r
+// -1- Enabling the Main Oscillator:\r
+//*#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register\r
+//*#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register\r
+//*#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register\r
+\r
+//*pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) | //0x0000 0600\r
+// AT91C_CKGR_MOSCEN )); //0x0000 0001 \r
+__writeMemory32(0x00000601,0xFFFFFC20,"Memory");\r
+\r
+// -2- Wait\r
+// -3- Setting PLL and divider:\r
+// - div by 5 Fin = 3,6864 =(18,432 / 5)\r
+// - Mul 25+1: Fout = 95,8464 =(3,6864 *26)\r
+// for 96 MHz the erroe is 0.16%\r
+// Field out NOT USED = 0\r
+// PLLCOUNT pll startup time esrtimate at : 0.844 ms\r
+// PLLCOUNT 28 = 0.000844 /(1/32768)\r
+// pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 0x05) | //0x0000 0005\r
+// (AT91C_CKGR_PLLCOUNT & (28<<8)) //0x0000 1C00\r
+// (AT91C_CKGR_MUL & (25<<16))); //0x0019 0000 \r
+__writeMemory32(0x00191C05,0xFFFFFC2C,"Memory");\r
+// -2- Wait\r
+// -5- Selection of Master Clock and Processor Clock\r
+// select the PLL clock divided by 2\r
+// pPMC->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK | //0x0000 0003\r
+// AT91C_PMC_PRES_CLK_2 ; //0x0000 0004\r
+__writeMemory32(0x00000007,0xFFFFFC30,"Memory"); \r
+\r
+ __message "------------------------------- PLL Enable ----------------------------------------"; \r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+// Watchdog\r
+//-------------------------------\r
+// Normally, the Watchdog is enable at the reset for load it's preferable to\r
+// Disable.\r
+//-----------------------------------------------------------------------------\r
+Watchdog()\r
+{\r
+//* Watchdog Disable\r
+// AT91C_BASE_WDTC->WDTC_WDMR= AT91C_SYSC_WDDIS;\r
+ __writeMemory32(0x00008000,0xFFFFFD44,"Memory");\r
+ __message "------------------------------- Watchdog Disable ----------------------------------------"; \r
+}\r
+\r
+CheckNoRemap()\r
+{\r
+//* Read the value at 0x0\r
+ i=__readMemory32(0x00000000,"Memory");\r
+ i=i+1;\r
+ __writeMemory32(i,0x00,"Memory");\r
+ pt=__readMemory32(0x00000000,"Memory");\r
+ \r
+ if (i == pt) \r
+ {\r
+ __message "------------------------------- The Remap is done ----------------------------------------"; \r
+ \r
+ } else { \r
+ __message "------------------------------- The Remap is NOT -----------------------------------------"; \r
+//* Toggel RESET The remap\r
+ __writeMemory32(0x00000001,0xFFFFFF00,"Memory");\r
+ }\r
+\r
+}\r
+\r
+execUserSetup()\r
+{\r
+ ini();\r
+ __message "-------------------------------Set PC ----------------------------------------"; \r
+ __writeMemory32(0x00000000,0xB4,"Register");\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+// Reset the Interrupt Controller\r
+//-------------------------------\r
+// Normally, the code is executed only if a reset has been actually performed.\r
+// So, the AIC initialization resumes at setting up the default vectors.\r
+//-----------------------------------------------------------------------------\r
+AIC()\r
+{\r
+// Mask All interrupt pAic->AIC_IDCR = 0xFFFFFFFF;\r
+ __writeMemory32(0xFFFFFFFF,0xFFFFF124,"Memory");\r
+\r
+ for (i=0;i < 8; i++)\r
+ {\r
+ // AT91C_BASE_AIC->AIC_EOICR\r
+ pt = __readMemory32(0xFFFFF130,"Memory");\r
+ \r
+ }\r
+ __message "------------------------------- AIC INIT ---------------------------------------------"; \r
+}\r
+\r
+ini()\r
+{\r
+__writeMemory32(0x0,0x00,"Register");\r
+__writeMemory32(0x0,0x04,"Register");\r
+__writeMemory32(0x0,0x08,"Register");\r
+__writeMemory32(0x0,0x0C,"Register");\r
+__writeMemory32(0x0,0x10,"Register");\r
+__writeMemory32(0x0,0x14,"Register");\r
+__writeMemory32(0x0,0x18,"Register");\r
+__writeMemory32(0x0,0x1C,"Register");\r
+__writeMemory32(0x0,0x20,"Register");\r
+__writeMemory32(0x0,0x24,"Register");\r
+__writeMemory32(0x0,0x28,"Register");\r
+__writeMemory32(0x0,0x2C,"Register");\r
+__writeMemory32(0x0,0x30,"Register");\r
+__writeMemory32(0x0,0x34,"Register");\r
+__writeMemory32(0x0,0x38,"Register");\r
+\r
+// Set CPSR\r
+__writeMemory32(0x0D3,0x98,"Register");\r
+\r
+}\r
+\r
+RG()\r
+{\r
+\r
+i=__readMemory32(0x00,"Register"); __message "R00 0x",i:%X; \r
+i=__readMemory32(0x04,"Register"); __message "R01 0x",i:%X; \r
+i=__readMemory32(0x08,"Register"); __message "R02 0x",i:%X; \r
+i=__readMemory32(0x0C,"Register"); __message "R03 0x",i:%X; \r
+i=__readMemory32(0x10,"Register"); __message "R04 0x",i:%X; \r
+i=__readMemory32(0x14,"Register"); __message "R05 0x",i:%X; \r
+i=__readMemory32(0x18,"Register"); __message "R06 0x",i:%X; \r
+i=__readMemory32(0x1C,"Register"); __message "R07 0x",i:%X; \r
+i=__readMemory32(0x20,"Register"); __message "R08 0x",i:%X; \r
+i=__readMemory32(0x24,"Register"); __message "R09 0x",i:%X; \r
+i=__readMemory32(0x28,"Register"); __message "R10 0x",i:%X; \r
+i=__readMemory32(0x2C,"Register"); __message "R11 0x",i:%X; \r
+i=__readMemory32(0x30,"Register"); __message "R12 0x",i:%X; \r
+i=__readMemory32(0x34,"Register"); __message "R13 0x",i:%X; \r
+i=__readMemory32(0x38,"Register"); __message "R14 0x",i:%X; \r
+i=__readMemory32(0x3C,"Register"); __message "R13 SVC 0x",i:%X; \r
+i=__readMemory32(0x40,"Register"); __message "R14 SVC 0x",i:%X; \r
+i=__readMemory32(0x44,"Register"); __message "R13 ABT 0x",i:%X; \r
+i=__readMemory32(0x48,"Register"); __message "R14 ABT 0x",i:%X; \r
+i=__readMemory32(0x4C,"Register"); __message "R13 UND 0x",i:%X; \r
+i=__readMemory32(0x50,"Register"); __message "R14 UND 0x",i:%X; \r
+i=__readMemory32(0x54,"Register"); __message "R13 IRQ 0x",i:%X; \r
+i=__readMemory32(0x58,"Register"); __message "R14 IRQ 0x",i:%X; \r
+i=__readMemory32(0x5C,"Register"); __message "R08 FIQ 0x",i:%X; \r
+i=__readMemory32(0x60,"Register"); __message "R09 FIQ 0x",i:%X; \r
+i=__readMemory32(0x64,"Register"); __message "R10 FIQ 0x",i:%X; \r
+i=__readMemory32(0x68,"Register"); __message "R11 FIQ 0x",i:%X; \r
+i=__readMemory32(0x6C,"Register"); __message "R12 FIQ 0x",i:%X; \r
+i=__readMemory32(0x70,"Register"); __message "R13 FIQ 0x",i:%X; \r
+i=__readMemory32(0x74,"Register"); __message "R14 FIQ0x",i:%X; \r
+i=__readMemory32(0x98,"Register"); __message "CPSR ",i:%X; \r
+i=__readMemory32(0x94,"Register"); __message "SPSR ",i:%X; \r
+i=__readMemory32(0x9C,"Register"); __message "SPSR ABT ",i:%X; \r
+i=__readMemory32(0xA0,"Register"); __message "SPSR ABT ",i:%X; \r
+i=__readMemory32(0xA4,"Register"); __message "SPSR UND ",i:%X; \r
+i=__readMemory32(0xA8,"Register"); __message "SPSR IRQ ",i:%X; \r
+i=__readMemory32(0xAC,"Register"); __message "SPSR FIQ ",i:%X; \r
+\r
+i=__readMemory32(0xB4,"Register"); __message "PC 0x",i:%X; \r
+\r
+}\r
+\r
--- /dev/null
+// ---------------------------------------------------------\r
+// ATMEL Microcontroller Software Support - ROUSSET -\r
+// ---------------------------------------------------------\r
+// The software is delivered "AS IS" without warranty or \r
+// condition of any kind, either express, implied or \r
+// statutory. This includes without limitation any warranty \r
+// or condition with respect to merchantability or fitness \r
+// for any particular purpose, or against the infringements of\r
+// intellectual property rights of others.\r
+// ---------------------------------------------------------\r
+// File: at91SAM7S64_16KRAM.xlc\r
+//\r
+// 1.1 16/Jun/04 JPP : Creation for 4.11A\r
+//\r
+// $Revision: 1.1.1.1 $\r
+//\r
+// ---------------------------------------------------------\r
+\r
+//*************************************************************************\r
+// XLINK command file template for EWARM/ICCARM\r
+//\r
+// Usage: xlink -f lnkarm <your_object_file(s)>\r
+// -s <program start label> <C/C++ runtime library>\r
+//\r
+// $Revision: 1.1.1.1 $\r
+//*************************************************************************\r
+\r
+//************************************************\r
+// Inform the linker about the CPU family used.\r
+// AT91SAM7S64 Memory mapping\r
+// No remap\r
+// ROMSTART\r
+// Start address 0x0000 0000 \r
+// Size 64 Kbo 0x0001 0000 \r
+// RAMSTART\r
+// Start address 0x0020 0000 \r
+// Size 16 Kbo 0x0000 4000 \r
+// Remap done\r
+// RAMSTART\r
+// Start address 0x0000 0000 \r
+// Size 16 Kbo 0x0000 4000 \r
+// ROMSTART\r
+// Start address 0x0010 0000 \r
+// Size 64 Kbo 0x0001 0000 \r
+\r
+//************************************************\r
+-carm\r
+\r
+//*************************************************************************\r
+// Internal Ram segments mapped AFTER REMAP 16 K.\r
+//*************************************************************************\r
+// Use these addresses for the .\r
+-Z(CONST)INTRAMSTART_REMAP=00000000\r
+-Z(CONST)INTRAMEND_REMAP=00003FFF\r
+\r
+//*************************************************************************\r
+// Read-only segments mapped to Flash 64 K.\r
+//*************************************************************************\r
+-DROMSTART=00000000\r
+-DROMEND=0000FFFF\r
+//*************************************************************************\r
+// Read/write segments mapped to RAM.\r
+//*************************************************************************\r
+-DRAMSTART=00000000\r
+-DRAMEND=00003FFF\r
+\r
+//************************************************\r
+// Address range for reset and exception\r
+// vectors (INTVEC).\r
+// The vector area is 32 bytes, \r
+// an additional 32 bytes is allocated for the\r
+// constant table used by ldr PC in cstartup.s79.\r
+//************************************************\r
+-Z(CODE)INTVEC=00-3F\r
+\r
+//************************************************\r
+// Startup code and exception routines (ICODE).\r
+//************************************************\r
+-Z(CODE)ICODE,DIFUNCT=ROMSTART-ROMEND\r
+-Z(CODE)SWITAB=ROMSTART-ROMEND\r
+\r
+//************************************************\r
+// Code segments may be placed anywhere.\r
+//************************************************\r
+-Z(CODE)CODE=ROMSTART-ROMEND\r
+\r
+//************************************************\r
+// Various constants and initializers.\r
+//************************************************\r
+-Z(CONST)INITTAB,DATA_ID,DATA_C=ROMSTART-ROMEND\r
+-Z(CONST)CHECKSUM=ROMSTART-ROMEND\r
+\r
+//************************************************\r
+// Data segments.\r
+//************************************************\r
+-Z(DATA)DATA_I,DATA_Z,DATA_N=RAMSTART-RAMEND\r
+\r
+//************************************************\r
+// __ramfunc code copied to and executed from RAM.\r
+//************************************************\r
+-Z(DATA)CODE_I=RAMSTART-RAMEND\r
+\r
+//************************************************\r
+// ICCARM produces code for __ramfunc functions in\r
+// CODE_I segments. The -Q XLINK command line\r
+// option redirects XLINK to emit the code in the\r
+// debug information associated with the CODE_I\r
+// segment, where the code will execute.\r
+//************************************************\r
+\r
+//*************************************************************************\r
+// Stack and heap segments.\r
+//*************************************************************************\r
+-D_CSTACK_SIZE=(100*4)\r
+-D_IRQ_STACK_SIZE=(2*8*4)\r
+\r
+-Z(DATA)CSTACK+_CSTACK_SIZE=RAMSTART-RAMEND\r
+-Z(DATA)IRQ_STACK+_IRQ_STACK_SIZE=RAMSTART-RAMEND\r
+\r
+//*************************************************************************\r
+// ELF/DWARF support.\r
+//\r
+// Uncomment the line "-Felf" below to generate ELF/DWARF output.\r
+// Available format specifiers are:\r
+//\r
+// "-yn": Suppress DWARF debug output\r
+// "-yp": Multiple ELF program sections\r
+// "-yas": Format suitable for debuggers from ARM Ltd (also sets -p flag)\r
+//\r
+// "-Felf" and the format specifiers can also be supplied directly as\r
+// command line options, or selected from the Xlink Output tab in the\r
+// IAR Embedded Workbench.\r
+//*************************************************************************\r
+\r
+// -Felf\r
--- /dev/null
+// ---------------------------------------------------------\r
+// ATMEL Microcontroller Software Support - ROUSSET -\r
+// ---------------------------------------------------------\r
+// The software is delivered "AS IS" without warranty or \r
+// condition of any kind, either express, implied or \r
+// statutory. This includes without limitation any warranty \r
+// or condition with respect to merchantability or fitness \r
+// for any particular purpose, or against the infringements of\r
+// intellectual property rights of others.\r
+// ---------------------------------------------------------\r
+// File: at91SAM7S64_NoRemap.xlc\r
+//\r
+// 1.1 16/Jun/04 JPP : Creation for 4.11A\r
+//\r
+// $Revision: 1.1.1.1 $\r
+//\r
+// ---------------------------------------------------------\r
+\r
+//*************************************************************************\r
+// XLINK command file template for EWARM/ICCARM\r
+//\r
+// Usage: xlink -f lnkarm <your_object_file(s)>\r
+// -s <program start label> <C/C++ runtime library>\r
+//\r
+// $Revision: 1.1.1.1 $\r
+//*************************************************************************\r
+\r
+//************************************************\r
+// Inform the linker about the CPU family used.\r
+// AT91SAM7S64 Memory mapping\r
+// No remap\r
+// ROMSTART\r
+// Start address 0x0000 0000 \r
+// Size 64 Kbo 0x0001 0000 \r
+// RAMSTART\r
+// Start address 0x0020 0000 \r
+// Size 16 Kbo 0x0000 4000 \r
+// Remap done\r
+// RAMSTART\r
+// Start address 0x0000 0000 \r
+// Size 16 Kbo 0x0000 4000 \r
+// ROMSTART\r
+// Start address 0x0010 0000 \r
+// Size 64 Kbo 0x0001 0000 \r
+\r
+//************************************************\r
+-carm\r
+\r
+//*************************************************************************\r
+// Internal Ram segments mapped AFTER REMAP 16 K.\r
+//*************************************************************************\r
+// Use these addresses for the .\r
+-Z(CONST)INTRAMSTART_REMAP=00200000\r
+-Z(CONST)INTRAMEND_REMAP=00203FFF\r
+\r
+//*************************************************************************\r
+// Read-only segments mapped to Flash 64 K.\r
+//*************************************************************************\r
+-DROMSTART=00000000\r
+-DROMEND=0000FFFF\r
+//*************************************************************************\r
+// Read/write segments mapped to RAM.\r
+//*************************************************************************\r
+-DRAMSTART=00200000\r
+-DRAMEND=002003FFF\r
+\r
+//************************************************\r
+// Address range for reset and exception\r
+// vectors (INTVEC).\r
+// The vector area is 32 bytes, \r
+// an additional 32 bytes is allocated for the\r
+// constant table used by ldr PC in cstartup.s79.\r
+//************************************************\r
+-Z(CODE)INTVEC=00-3F\r
+\r
+//************************************************\r
+// Startup code and exception routines (ICODE).\r
+//************************************************\r
+-Z(CODE)ICODE,DIFUNCT=ROMSTART-ROMEND\r
+-Z(CODE)SWITAB=ROMSTART-ROMEND\r
+\r
+//************************************************\r
+// Code segments may be placed anywhere.\r
+//************************************************\r
+-Z(CODE)CODE=ROMSTART-ROMEND\r
+\r
+//************************************************\r
+// Various constants and initializers.\r
+//************************************************\r
+-Z(CONST)INITTAB,DATA_ID,DATA_C=ROMSTART-ROMEND\r
+-Z(CONST)CHECKSUM=ROMSTART-ROMEND\r
+\r
+\r
+//************************************************\r
+// Data segments.\r
+//************************************************\r
+-Z(DATA)DATA_I,DATA_Z,DATA_N=RAMSTART-RAMEND\r
+\r
+//************************************************\r
+// __ramfunc code copied to and executed from RAM.\r
+//************************************************\r
+-Z(DATA)CODE_I=RAMSTART-RAMEND\r
+\r
+//************************************************\r
+// ICCARM produces code for __ramfunc functions in\r
+// CODE_I segments. The -Q XLINK command line\r
+// option redirects XLINK to emit the code in the\r
+// debug information associated with the CODE_I\r
+// segment, where the code will execute.\r
+//************************************************\r
+\r
+//*************************************************************************\r
+// Stack and heap segments.\r
+//*************************************************************************\r
+//-D_CSTACK_SIZE=(100*4)\r
+//-D_IRQ_STACK_SIZE=(2*8*4)\r
+\r
+//-Z(DATA)CSTACK+_CSTACK_SIZE=RAMSTART-RAMEND\r
+//-Z(DATA)IRQ_STACK+_IRQ_STACK_SIZE=RAMSTART-RAMEND\r
+\r
+//*************************************************************************\r
+// ELF/DWARF support.\r
+//\r
+// Uncomment the line "-Felf" below to generate ELF/DWARF output.\r
+// Available format specifiers are:\r
+//\r
+// "-yn": Suppress DWARF debug output\r
+// "-yp": Multiple ELF program sections\r
+// "-yas": Format suitable for debuggers from ARM Ltd (also sets -p flag)\r
+//\r
+// "-Felf" and the format specifiers can also be supplied directly as\r
+// command line options, or selected from the Xlink Output tab in the\r
+// IAR Embedded Workbench.\r
+//*************************************************************************\r
+\r
+// -Felf\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+ <fileVersion>1</fileVersion>\r
+ <configuration>\r
+ <name>Flash Debug</name>\r
+ <toolchain>\r
+ <name>ARM</name>\r
+ </toolchain>\r
+ <debug>1</debug>\r
+ <settings>\r
+ <name>C-SPY</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>13</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CInput</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CEndian</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCVariant</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacOverride</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>MacFile</name>\r
+ <state>$PROJ_DIR$\resource\SAM7.mac</state>\r
+ </option>\r
+ <option>\r
+ <name>MemOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MemFile</name>\r
+ <state>$TOOLKIT_DIR$\CONFIG\ioat91sam7s64.ddf</state>\r
+ </option>\r
+ <option>\r
+ <name>RunToEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RunToName</name>\r
+ <state>main</state>\r
+ </option>\r
+ <option>\r
+ <name>CExtraOptionsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CFpuProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDDFArgumentProducer</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadSuppressDownload</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadVerifyAll</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCProductVersion</name>\r
+ <state>4.10B</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDynDriverList</name>\r
+ <state>JLINK_ID</state>\r
+ </option>\r
+ <option>\r
+ <name>OCLastSavedByProductVersion</name>\r
+ <state>4.30A</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadAttachToProgram</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>FlashLoaders</name>\r
+ <state>,,,,(default),</state>\r
+ </option>\r
+ <option>\r
+ <name>UseFlashLoader</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ARMSIM_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCSimDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ANGEL_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CCAngelHeartbeat</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommunication</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommBaud</name>\r
+ <version>0</version>\r
+ <state>3</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ANGELTCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>DoAngelLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AngelLogFile</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>IARROM_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CRomLogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomLogFileEditB</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomCommunication</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomCommBaud</name>\r
+ <version>0</version>\r
+ <state>7</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>JLINK_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>2</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>JLinkSpeed</name>\r
+ <state>30</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkHWReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkTRSTReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkLogFile</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkHWResetDelay</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkSpeedRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>JLinkInitialSpeed</name>\r
+ <state>32</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDoJlinkMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCScanChainNonARMDevices</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkIRLength</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkCommRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkTCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>MACRAIGOR_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>jtag</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuSpeed</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>TCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>DoEmuMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuMultiTarget</name>\r
+ <state>0@ARM7TDMI</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuHWReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CEmuCommBaud</name>\r
+ <version>0</version>\r
+ <state>4</state>\r
+ </option>\r
+ <option>\r
+ <name>CEmuCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>jtago</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>UnusedAddr</name>\r
+ <state>0x00800000</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMacraigorHWResetDelay</name>\r
+ <state></state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>RDI_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CRDIDriverDll</name>\r
+ <state>Browse to your RDI driver</state>\r
+ </option>\r
+ <option>\r
+ <name>CRDILogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRDILogFileEdit</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDIHWReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchUndef</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchSWI</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchData</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchPrefetch</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchIRQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchFIQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDIUseETM</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>THIRDPARTY_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CThirdPartyDriverDll</name>\r
+ <state>Browse to your third-party driver</state>\r
+ </option>\r
+ <option>\r
+ <name>CThirdPartyLogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CThirdPartyLogFileEditB</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <debuggerPlugins>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Orti\Orti.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Profiling\Profiling.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ </debuggerPlugins>\r
+ </configuration>\r
+ <configuration>\r
+ <name>Flash Bin</name>\r
+ <toolchain>\r
+ <name>ARM</name>\r
+ </toolchain>\r
+ <debug>1</debug>\r
+ <settings>\r
+ <name>C-SPY</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>13</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CInput</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CEndian</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCVariant</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacOverride</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>MacFile</name>\r
+ <state>$PROJ_DIR$\resource\SAM7.mac</state>\r
+ </option>\r
+ <option>\r
+ <name>MemOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MemFile</name>\r
+ <state>$TOOLKIT_DIR$\CONFIG\ioat91sam7s64.ddf</state>\r
+ </option>\r
+ <option>\r
+ <name>RunToEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RunToName</name>\r
+ <state>main</state>\r
+ </option>\r
+ <option>\r
+ <name>CExtraOptionsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CFpuProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDDFArgumentProducer</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadSuppressDownload</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadVerifyAll</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCProductVersion</name>\r
+ <state>4.10B</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDynDriverList</name>\r
+ <state>JLINK_ID</state>\r
+ </option>\r
+ <option>\r
+ <name>OCLastSavedByProductVersion</name>\r
+ <state>4.30A</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadAttachToProgram</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>FlashLoaders</name>\r
+ <state>,,,,(default),</state>\r
+ </option>\r
+ <option>\r
+ <name>UseFlashLoader</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ARMSIM_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCSimDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ANGEL_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CCAngelHeartbeat</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommunication</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommBaud</name>\r
+ <version>0</version>\r
+ <state>3</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ANGELTCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>DoAngelLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AngelLogFile</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>IARROM_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CRomLogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomLogFileEditB</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomCommunication</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomCommBaud</name>\r
+ <version>0</version>\r
+ <state>7</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>JLINK_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>2</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>JLinkSpeed</name>\r
+ <state>30</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkHWReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkTRSTReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkLogFile</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkHWResetDelay</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkSpeedRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>JLinkInitialSpeed</name>\r
+ <state>32</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDoJlinkMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCScanChainNonARMDevices</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkIRLength</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkCommRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkTCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>MACRAIGOR_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>jtag</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuSpeed</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>TCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>DoEmuMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuMultiTarget</name>\r
+ <state>0@ARM7TDMI</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuHWReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CEmuCommBaud</name>\r
+ <version>0</version>\r
+ <state>4</state>\r
+ </option>\r
+ <option>\r
+ <name>CEmuCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>jtago</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>UnusedAddr</name>\r
+ <state>0x00800000</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMacraigorHWResetDelay</name>\r
+ <state></state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>RDI_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CRDIDriverDll</name>\r
+ <state>Browse to your RDI driver</state>\r
+ </option>\r
+ <option>\r
+ <name>CRDILogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRDILogFileEdit</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDIHWReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchUndef</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchSWI</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchData</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchPrefetch</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchIRQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchFIQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDIUseETM</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>THIRDPARTY_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CThirdPartyDriverDll</name>\r
+ <state>Browse to your third-party driver</state>\r
+ </option>\r
+ <option>\r
+ <name>CThirdPartyLogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CThirdPartyLogFileEditB</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <debuggerPlugins>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Orti\Orti.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Profiling\Profiling.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ </debuggerPlugins>\r
+ </configuration>\r
+</project>\r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+ <fileVersion>1</fileVersion>\r
+ <configuration>\r
+ <name>Flash Debug</name>\r
+ <toolchain>\r
+ <name>ARM</name>\r
+ </toolchain>\r
+ <debug>1</debug>\r
+ <settings>\r
+ <name>General</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>9</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>GProcessorMode</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>ExePath</name>\r
+ <state>Flash_Debug\Exe</state>\r
+ </option>\r
+ <option>\r
+ <name>ObjPath</name>\r
+ <state>Flash_Debug\Obj</state>\r
+ </option>\r
+ <option>\r
+ <name>ListPath</name>\r
+ <state>Flash_Debug\List</state>\r
+ </option>\r
+ <option>\r
+ <name>Variant</name>\r
+ <version>3</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GEndianMode</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GInterwork</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GStackAlign</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>Input variant</name>\r
+ <version>1</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>Input description</name>\r
+ <state>Full formatting.</state>\r
+ </option>\r
+ <option>\r
+ <name>Output variant</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>Output description</name>\r
+ <state>Full formatting.</state>\r
+ </option>\r
+ <option>\r
+ <name>GOutputBinary</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>FPU</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OGCoreOrChip</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GRuntimeLibSelect</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GRuntimeLibSelectSlave</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RTDescription</name>\r
+ <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\r
+ </option>\r
+ <option>\r
+ <name>RTConfigPath</name>\r
+ <state>$TOOLKIT_DIR$\LIB\dl4tptinl8n.h</state>\r
+ </option>\r
+ <option>\r
+ <name>RTLibraryPath</name>\r
+ <state>$TOOLKIT_DIR$\LIB\dl4tptinl8n.r79</state>\r
+ </option>\r
+ <option>\r
+ <name>OGProductVersion</name>\r
+ <state>4.11A</state>\r
+ </option>\r
+ <option>\r
+ <name>OGLastSavedByProductVersion</name>\r
+ <state>4.11B</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraRules</name>\r
+ <version>0</version>\r
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralEnableMisra</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraVerbose</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OGChipSelectEditMenu</name>\r
+ <state>AT91SAM7S64 Atmel AT91SAM7S64</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ICCARM</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>13</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CCDefines</name>\r
+ <state>SAM7_IAR</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocComments</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCMnemonics</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCMessages</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListAssFile</name>\r
+ <state>0</state>\r
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+ <prebuild></prebuild>\r
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+ <settings>\r
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+ <name>BILINK</name>\r
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+ </configuration>\r
+ <group>\r
+ <name>Demo Source</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\BlockQ.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\comtest.c</name>\r
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+ <file>\r
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+ <file>\r
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+ <file>\r
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+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\serial\serialISR.s79</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\USB\USB_ISR.s79</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\USB\USBSample.c</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>Scheduler Source</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\list.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\IAR\AtmelSAM7S64\port.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\IAR\AtmelSAM7S64\portasm.s79</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\queue.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\tasks.c</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>System Files</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\SrcIAR\Cstartup.s79</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\SrcIAR\Cstartup_SAM7.c</name>\r
+ </file>\r
+ </group>\r
+</project>\r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<workspace>\r
+ <project>\r
+ <path>$WS_DIR$\rtosdemo.ewp</path>\r
+ </project>\r
+ <batchBuild/>\r
+</workspace>\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* \r
+ BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0. \r
+*/\r
+\r
+/* Standard includes. */ \r
+#include <stdlib.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "queue.h"\r
+\r
+/* Demo application includes. */\r
+#include "serial.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Location of the COM0 registers. */\r
+#define serCOM0 ( ( AT91PS_USART ) AT91C_BASE_US0 )\r
+\r
+/* Interrupt control macros. */\r
+#define serINTERRUPT_LEVEL ( 5 )\r
+#define vInterruptOn() AT91F_US_EnableIt( serCOM0, AT91C_US_TXRDY | AT91C_US_RXRDY )\r
+#define vInterruptOff() AT91F_US_DisableIt( serCOM0, AT91C_US_TXRDY )\r
+\r
+/* Misc constants. */\r
+#define serINVALID_QUEUE ( ( xQueueHandle ) 0 )\r
+#define serHANDLE ( ( xComPortHandle ) 1 )\r
+#define serNO_BLOCK ( ( portTickType ) 0 )\r
+#define serNO_TIMEGUARD ( ( unsigned portLONG ) 0 )\r
+#define serNO_PERIPHERAL_B_SETUP ( ( unsigned portLONG ) 0 )\r
+\r
+\r
+/* Queues used to hold received characters, and characters waiting to be\r
+transmitted. */\r
+static xQueueHandle xRxedChars; \r
+static xQueueHandle xCharsForTx; \r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Interrupt entry point written in the assembler file serialISR.s79. */\r
+extern void vSerialISREntry( void );\r
+\r
+/* The interrupt service routine - called from the assembly entry point. */\r
+__arm void vSerialISR( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * See the serial2.h header file.\r
+ */\r
+xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )\r
+{\r
+xComPortHandle xReturn = serHANDLE;\r
+extern void ( vUART_ISR )( void );\r
+\r
+ /* Create the queues used to hold Rx and Tx characters. */\r
+ xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );\r
+ xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );\r
+\r
+ /* If the queues were created correctly then setup the serial port \r
+ hardware. */\r
+ if( ( xRxedChars != serINVALID_QUEUE ) && ( xCharsForTx != serINVALID_QUEUE ) )\r
+ {\r
+ portENTER_CRITICAL();\r
+ {\r
+ /* Enable the USART clock. */\r
+ AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, 1 << AT91C_ID_US0 );\r
+\r
+ AT91F_PIO_CfgPeriph( AT91C_BASE_PIOA, ( ( unsigned portLONG ) AT91C_PA5_RXD0 ) | ( ( unsigned portLONG ) AT91C_PA6_TXD0 ), serNO_PERIPHERAL_B_SETUP );\r
+\r
+ /* Set the required protocol. */\r
+ AT91F_US_Configure( serCOM0, configCPU_CLOCK_HZ, AT91C_US_ASYNC_MODE, ulWantedBaud, serNO_TIMEGUARD );\r
+\r
+ /* Enable Rx and Tx. */\r
+ serCOM0->US_CR = AT91C_US_RXEN | AT91C_US_TXEN;\r
+\r
+ /* Enable the Rx interrupts. The Tx interrupts are not enabled\r
+ until there are characters to be transmitted. */\r
+ AT91F_US_EnableIt( serCOM0, AT91C_US_RXRDY );\r
+\r
+ /* Enable the interrupts in the AIC. */\r
+ AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_US0, serINTERRUPT_LEVEL, AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE, ( void (*)( void ) ) vSerialISREntry );\r
+ AT91F_AIC_EnableIt( AT91C_BASE_AIC, AT91C_ID_US0 );\r
+ }\r
+ portEXIT_CRITICAL();\r
+ }\r
+ else\r
+ {\r
+ xReturn = ( xComPortHandle ) 0;\r
+ }\r
+\r
+ /* This demo file only supports a single port but we have to return \r
+ something to comply with the standard demo header file. */\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )\r
+{\r
+ /* The port handle is not required as this driver only supports one port. */\r
+ ( void ) pxPort;\r
+\r
+ /* Get the next character from the buffer. Return false if no characters\r
+ are available, or arrive before xBlockTime expires. */\r
+ if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )\r
+ {\r
+ return pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ return pdFALSE;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength )\r
+{\r
+signed portCHAR *pxNext;\r
+\r
+ /* A couple of parameters that this port does not use. */\r
+ ( void ) usStringLength;\r
+ ( void ) pxPort;\r
+\r
+ /* NOTE: This implementation does not handle the queue being full as no\r
+ block time is used! */\r
+\r
+ /* The port handle is not required as this driver only supports UART0. */\r
+ ( void ) pxPort;\r
+\r
+ /* Send each character in the string, one at a time. */\r
+ pxNext = ( signed portCHAR * ) pcString;\r
+ while( *pxNext )\r
+ {\r
+ xSerialPutChar( pxPort, *pxNext, serNO_BLOCK );\r
+ pxNext++;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )\r
+{\r
+ /* Place the character in the queue of characters to be transmitted. */\r
+ if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )\r
+ {\r
+ return pdFAIL;\r
+ }\r
+\r
+ /* Turn on the Tx interrupt so the ISR will remove the character from the\r
+ queue and send it. This does not need to be in a critical section as\r
+ if the interrupt has already removed the character the next interrupt\r
+ will simply turn off the Tx interrupt again. */\r
+ vInterruptOn();\r
+\r
+ return pdPASS;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSerialClose( xComPortHandle xPort )\r
+{\r
+ /* Not supported as not required by the demo application. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Serial port ISR. This can cause a context switch so is not defined as a\r
+standard ISR using the __irq keyword. Instead a wrapper function is defined\r
+within serialISR.s79 which in turn calls this function. See the port\r
+documentation on the FreeRTOS.org website for more information. */\r
+__arm void vSerialISR( void )\r
+{\r
+unsigned portLONG ulStatus;\r
+signed portCHAR cChar;\r
+portBASE_TYPE xTaskWokenByTx = pdFALSE, xTaskWokenByPost = pdFALSE;\r
+\r
+ /* What caused the interrupt? */\r
+ ulStatus = serCOM0->US_CSR &= serCOM0->US_IMR;\r
+\r
+ if( ulStatus & AT91C_US_TXRDY )\r
+ {\r
+ /* The interrupt was caused by the THR becoming empty. Are there any\r
+ more characters to transmit? */\r
+ if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWokenByTx ) == pdTRUE )\r
+ {\r
+ /* A character was retrieved from the queue so can be sent to the\r
+ THR now. */\r
+ serCOM0->US_THR = cChar;\r
+ }\r
+ else\r
+ {\r
+ /* Queue empty, nothing to send so turn off the Tx interrupt. */\r
+ vInterruptOff();\r
+ } \r
+ }\r
+\r
+ if( ulStatus & AT91C_US_RXRDY )\r
+ {\r
+ /* The interrupt was caused by a character being received. Grab the\r
+ character from the RHR and place it in the queue or received \r
+ characters. */\r
+ cChar = serCOM0->US_RHR;\r
+ xTaskWokenByPost = xQueueSendFromISR( xRxedChars, &cChar, xTaskWokenByPost );\r
+ }\r
+\r
+ /* If a task was woken by either a character being received or a character \r
+ being transmitted then we may need to switch to another task. */\r
+ portEND_SWITCHING_ISR( ( xTaskWokenByPost || xTaskWokenByTx ) );\r
+\r
+ /* End the interrupt in the AIC. */\r
+ AT91C_BASE_AIC->AIC_EOICR = 0;\r
+}\r
+\r
+\r
+\r
+\r
+ \r
--- /dev/null
+ RSEG ICODE:CODE\r
+ CODE32\r
+\r
+ EXTERN vSerialISR\r
+ PUBLIC vSerialISREntry\r
+\r
+; Wrapper for the serial port interrupt service routine. This can cause a\r
+; context switch so requires an assembly wrapper.\r
+\r
+; Defines the portSAVE_CONTEXT and portRESTORE_CONTEXT macros.\r
+#include "ISR_Support.h"\r
+\r
+vSerialISREntry:\r
+\r
+ portSAVE_CONTEXT ; Save the context of the current task.\r
+\r
+ bl vSerialISR ; Call the ISR routine.\r
+\r
+ portRESTORE_CONTEXT ; Restore the context of the current task -\r
+ ; which may be different to the task that\r
+ ; was interrupted.\r
+\r
+ END\r
+\r
--- /dev/null
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+\r
+\r
--- /dev/null
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--- /dev/null
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+ </Desktop>\r
+</Workspace>\r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<Project>\r
+ <Desktop>\r
+ <Static>\r
+ <Workspace>\r
+ <ColumnWidths>\r
+ \r
+ \r
+ \r
+ <Column0>191</Column0><Column1>27</Column1><Column2>27</Column2></ColumnWidths>\r
+ </Workspace>\r
+ <Disassembly>\r
+ \r
+ \r
+ \r
+ <PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><MixedMode>1</MixedMode><CodeCovEnabled>0</CodeCovEnabled><CodeCovShow>0</CodeCovShow></Disassembly>\r
+ <Debug-Log><PreferedWindows><Position>3</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows><Window><Factory>Build</Factory></Window></Windows></PreferedWindows></Debug-Log>\r
+ <Build><PreferedWindows><Position>3</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows><Window><Factory>Debug-Log</Factory></Window></Windows></PreferedWindows></Build>\r
+ <Register>\r
+ <PreferedWindows>\r
+ \r
+ \r
+ \r
+ \r
+ <Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows>\r
+ </Register>\r
+ <QWatch><Column0>161</Column0><Column1>100</Column1><Column2>100</Column2><Column3>100</Column3></QWatch><Memory><PreferedWindows><Position>3</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><ZoneNumber>0</ZoneNumber><FindDirection>1</FindDirection><FindAsHex>0</FindAsHex></Memory></Static>\r
+ <Windows>\r
+ \r
+ \r
+ \r
+ <Wnd2>\r
+ <Tabs>\r
+ <Tab>\r
+ <Identity>TabID-22256-14845</Identity>\r
+ <TabName>Workspace</TabName>\r
+ <Factory>Workspace</Factory>\r
+ <Session>\r
+ \r
+ <NodeDict><ExpandedNode>rtosdemo</ExpandedNode><ExpandedNode>rtosdemo/USBSample.c</ExpandedNode></NodeDict></Session>\r
+ </Tab>\r
+ </Tabs>\r
+ \r
+ <SelectedTab>0</SelectedTab></Wnd2></Windows>\r
+ <Editor>\r
+ \r
+ \r
+ \r
+ \r
+ <Pane><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\source\portable\iar\AtmelSAM7S64\lib_AT91SAM7S64.h</Filename><XPos>0</XPos><YPos>615</YPos><SelStart>24806</SelStart><SelEnd>24806</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Demo\ARM7_AT91SAM7S64_IAR\USB\USBSample.c</Filename><XPos>0</XPos><YPos>289</YPos><SelStart>10498</SelStart><SelEnd>10498</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Demo\ARM7_AT91SAM7S64_IAR\main.c</Filename><XPos>0</XPos><YPos>141</YPos><SelStart>6420</SelStart><SelEnd>6420</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Source\portable\IAR\AtmelSAM7S64\port.c</Filename><XPos>0</XPos><YPos>117</YPos><SelStart>5493</SelStart><SelEnd>5493</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Demo\ARM7_AT91SAM7S64_IAR\serial\serial.c</Filename><XPos>0</XPos><YPos>132</YPos><SelStart>5547</SelStart><SelEnd>5547</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Source\portable\MemMang\heap_1.c</Filename><XPos>0</XPos><YPos>82</YPos><SelStart>3650</SelStart><SelEnd>3650</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Demo\ARM7_AT91SAM7S64_IAR\SrcIAR\Cstartup.s79</Filename><XPos>0</XPos><YPos>27</YPos><SelStart>2226</SelStart><SelEnd>2226</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Demo\Common\Minimal\integer.c</Filename><XPos>0</XPos><YPos>77</YPos><SelStart>4024</SelStart><SelEnd>4024</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Source\tasks.c</Filename><XPos>0</XPos><YPos>823</YPos><SelStart>29289</SelStart><SelEnd>29289</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Source\portable\IAR\AtmelSAM7S64\portasm.s79</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>519</SelStart><SelEnd>519</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Source\portable\IAR\AtmelSAM7S64\portmacro.h</Filename><XPos>0</XPos><YPos>57</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Demo\ARM7_AT91SAM7S64_IAR\FreeRTOSConfig.h</Filename><XPos>0</XPos><YPos>24</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Demo\Common\Minimal\semtest.c</Filename><XPos>0</XPos><YPos>166</YPos><SelStart>7856</SelStart><SelEnd>7856</SelEnd></Tab><ActiveTab>12</ActiveTab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>\r
+ <Positions>\r
+ \r
+ \r
+ \r
+ \r
+ \r
+ <Top><Row0><Sizes><Toolbar-0084f8b0><key>IarIdePM1</key></Toolbar-0084f8b0><Toolbar-0272db18><key>DebuggerGui1</key></Toolbar-0272db18></Sizes></Row0></Top><Left><Row0><Sizes><Wnd2><Rect><Top>-2</Top><Left>-2</Left><Bottom>1072</Bottom><Right>265</Right><x>-2</x><y>-2</y><xscreen>0</xscreen><yscreen>0</yscreen><sizeHorzCX>0</sizeHorzCX><sizeHorzCY>0</sizeHorzCY><sizeVertCX>166875</sizeVertCX><sizeVertCY>959785</sizeVertCY></Rect></Wnd2></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes/></Row0></Bottom><Float><Sizes/></Float></Positions>\r
+ </Desktop>\r
+</Project>\r
+\r
+\r
--- /dev/null
+[DisAssemblyWindow]\r
+NumStates=_ 1\r
+State 1=_ 1\r
+[JLinkDriver]\r
+WatchVectorCatch=_ 0\r
+WatchCond=_ 0\r
+Watch0=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0\r
+Watch1=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0\r
+[Low Level]\r
+Pipeline mode=1\r
+Initialized=0\r
+[Log file]\r
+LoggingEnabled=_ 0\r
+LogFile=_ ""\r
+Category=_ 0\r
+[TermIOLog]\r
+LoggingEnabled=_ 0\r
+LogFile=_ ""\r
+[Disassemble mode]\r
+mode=0\r
+[Breakpoints]\r
+Count=0\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<Workspace>\r
+ <ConfigDictionary>\r
+ \r
+ <CurrentConfigs><Project>rtosdemo/Flash Debug</Project></CurrentConfigs></ConfigDictionary>\r
+ <Desktop>\r
+ <Static>\r
+ <Workspace>\r
+ <ColumnWidths>\r
+ \r
+ \r
+ \r
+ <Column0>221</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>\r
+ </Workspace>\r
+ <Build><ColumnWidth0>18</ColumnWidth0><ColumnWidth1>1155</ColumnWidth1><ColumnWidth2>308</ColumnWidth2><ColumnWidth3>77</ColumnWidth3></Build>\r
+ <Debug-Log/>\r
+ <TerminalIO/>\r
+ <CodeCoveragePlugin/>\r
+ <Profiling/>\r
+ <Watch>\r
+ <Format>\r
+ <struct_types/>\r
+ <watch_formats/>\r
+ </Format>\r
+ </Watch>\r
+ <Disassembly><MixedMode>1</MixedMode><CodeCovEnabled>0</CodeCovEnabled><CodeCovShow>0</CodeCovShow></Disassembly><Memory><ZoneNumber>0</ZoneNumber><FindDirection>1</FindDirection><FindAsHex>0</FindAsHex></Memory></Static>\r
+ <Windows>\r
+ \r
+ \r
+ <Wnd0>\r
+ <Tabs>\r
+ <Tab>\r
+ <Identity>TabID-17425-14382</Identity>\r
+ <TabName>Workspace</TabName>\r
+ <Factory>Workspace</Factory>\r
+ <Session>\r
+ \r
+ <NodeDict><ExpandedNode>rtosdemo</ExpandedNode><ExpandedNode>rtosdemo/Demo Source</ExpandedNode><ExpandedNode>rtosdemo/Scheduler Source</ExpandedNode><ExpandedNode>rtosdemo/System Files</ExpandedNode></NodeDict></Session>\r
+ </Tab>\r
+ </Tabs>\r
+ \r
+ <SelectedTab>0</SelectedTab></Wnd0><Wnd1>\r
+ <Tabs>\r
+ <Tab>\r
+ <Identity>TabID-4084-16269</Identity>\r
+ <TabName>Build</TabName>\r
+ <Factory>Build</Factory>\r
+ <Session/>\r
+ </Tab>\r
+ <Tab>\r
+ <Identity>TabID-25581-16276</Identity>\r
+ <TabName>Debug Log</TabName>\r
+ <Factory>Debug-Log</Factory>\r
+ <Session/>\r
+ </Tab>\r
+ </Tabs>\r
+ \r
+ <SelectedTab>0</SelectedTab></Wnd1></Windows>\r
+ <Editor>\r
+ \r
+ \r
+ \r
+ \r
+ <Pane><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Demo\ARM7_AT91SAM7S64_IAR\FreeRTOSConfig.h</Filename><XPos>0</XPos><YPos>18</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Demo\ARM7_AT91SAM7S64_IAR\SrcIAR\Board.h</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>952</SelStart><SelEnd>969</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Demo\ARM7_AT91SAM7S64_IAR\SrcIAR\Cstartup.s79</Filename><XPos>0</XPos><YPos>142</YPos><SelStart>6503</SelStart><SelEnd>6517</SelEnd></Tab><ActiveTab>2</ActiveTab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>\r
+ <Positions>\r
+ \r
+ \r
+ \r
+ \r
+ \r
+ <Top><Row0><Sizes><Toolbar-0084c368><key>iaridepm1</key></Toolbar-0084c368></Sizes></Row0></Top><Left><Row0><Sizes><Wnd0><Rect><Top>-2</Top><Left>-2</Left><Bottom>659</Bottom><Right>295</Right><x>-2</x><y>-2</y><xscreen>30</xscreen><yscreen>30</yscreen><sizeHorzCX>18750</sizeHorzCX><sizeHorzCY>26809</sizeHorzCY><sizeVertCX>185625</sizeVertCX><sizeVertCY>590705</sizeVertCY></Rect></Wnd0></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd1><Rect><Top>-2</Top><Left>-2</Left><Bottom>413</Bottom><Right>1602</Right><x>-2</x><y>-2</y><xscreen>1604</xscreen><yscreen>415</yscreen><sizeHorzCX>1002500</sizeHorzCX><sizeHorzCY>370866</sizeHorzCY><sizeVertCX>18750</sizeVertCX><sizeVertCY>26809</sizeVertCY></Rect></Wnd1></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>\r
+ </Desktop>\r
+</Workspace>\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+#include <lpc210x.h>\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. \r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 58982400 ) /* =14.7456MHz xtal multiplied by 4 using the PLL. */\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 128 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 23 * 1024 ) )\r
+#define configMAX_TASK_NAME_LEN ( 16 )\r
+#define configUSE_TRACE_FACILITY 0\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 1\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+# FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+#\r
+# This file is part of the FreeRTOS distribution.\r
+#\r
+# FreeRTOS is free software; you can redistribute it and/or modify\r
+# it under the terms of the GNU General Public License as published by\r
+# the Free Software Foundation; either version 2 of the License, or\r
+# (at your option) any later version.\r
+#\r
+# FreeRTOS is distributed in the hope that it will be useful,\r
+# but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+# GNU General Public License for more details.\r
+#\r
+# You should have received a copy of the GNU General Public License\r
+# along with FreeRTOS; if not, write to the Free Software\r
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+#\r
+# A special exception to the GPL can be applied should you wish to distribute\r
+# a combined work that includes FreeRTOS, without being obliged to provide\r
+# the source code for any proprietary components. See the licensing section \r
+# of http://www.FreeRTOS.org for full details of how and when the exception\r
+# can be applied.\r
+#\r
+# ***************************************************************************\r
+# See http://www.FreeRTOS.org for documentation, latest information, license \r
+# and contact details. Please ensure to read the configuration and relevant \r
+# port sections of the online documentation.\r
+# ***************************************************************************\r
+\r
+# Changes from V2.4.2\r
+#\r
+# + Replaced source/portable/gcc/arm7/portheap.c with source/portable/memmang/heap_2.c.\r
+\r
+CC=arm-elf-gcc\r
+OBJCOPY=arm-elf-objcopy\r
+ARCH=arm-elf-ar\r
+CRT0=boot.s\r
+WARNINGS=-Wall -Wextra -Wshadow -Wpointer-arith -Wbad-function-cast -Wcast-align -Wsign-compare \\r
+ -Waggregate-return -Wstrict-prototypes -Wmissing-prototypes -Wmissing-declarations -Wunused\r
+\r
+#\r
+# CFLAGS common to both the THUMB and ARM mode builds\r
+#\r
+CFLAGS=$(WARNINGS) -D $(RUN_MODE) -D GCC_ARM7 -I. -I../../Source/include \\r
+ -I../Common/include $(DEBUG) -mcpu=arm7tdmi -T$(LDSCRIPT) \\r
+ $(OPTIM)\r
+\r
+ifeq ($(USE_THUMB_MODE),YES)\r
+ CFLAGS += -mthumb-interwork -D THUMB_INTERWORK\r
+ THUMB_FLAGS=-mthumb\r
+endif\r
+\r
+\r
+LINKER_FLAGS=-Xlinker -ortosdemo.elf -Xlinker -M -Xlinker -Map=rtosdemo.map\r
+\r
+RTOS_SOURCE_DIR=../../Source\r
+DEMO_SOURCE_DIR=../Common/Minimal\r
+#\r
+# Source files that can be built to THUMB mode.\r
+#\r
+THUMB_SRC = \\r
+main.c \\r
+serial/serial.c \\r
+ParTest/ParTest.c \\r
+$(DEMO_SOURCE_DIR)/integer.c \\r
+$(DEMO_SOURCE_DIR)/flash.c \\r
+$(DEMO_SOURCE_DIR)/PollQ.c \\r
+$(DEMO_SOURCE_DIR)/comtest.c \\r
+$(DEMO_SOURCE_DIR)/flop.c \\r
+$(DEMO_SOURCE_DIR)/semtest.c \\r
+$(DEMO_SOURCE_DIR)/dynamic.c \\r
+$(DEMO_SOURCE_DIR)/BlockQ.c \\r
+$(RTOS_SOURCE_DIR)/tasks.c \\r
+$(RTOS_SOURCE_DIR)/queue.c \\r
+$(RTOS_SOURCE_DIR)/list.c \\r
+$(RTOS_SOURCE_DIR)/portable/MemMang/heap_2.c \\r
+$(RTOS_SOURCE_DIR)/portable/GCC/ARM7_LPC2000/port.c\r
+\r
+#\r
+# Source files that must be built to ARM mode.\r
+#\r
+ARM_SRC = \\r
+$(RTOS_SOURCE_DIR)/portable/GCC/ARM7_LPC2000/portISR.c \\r
+serial/serialISR.c\r
+\r
+#\r
+# Define all object files.\r
+#\r
+ARM_OBJ = $(ARM_SRC:.c=.o)\r
+THUMB_OBJ = $(THUMB_SRC:.c=.o)\r
+\r
+rtosdemo.hex : rtosdemo.elf\r
+ $(OBJCOPY) rtosdemo.elf -O ihex rtosdemo.hex\r
+\r
+rtosdemo.elf : $(ARM_OBJ) $(THUMB_OBJ) $(CRT0) Makefile\r
+ $(CC) $(CFLAGS) $(ARM_OBJ) $(THUMB_OBJ) -nostartfiles $(CRT0) $(LINKER_FLAGS)\r
+\r
+$(THUMB_OBJ) : %.o : %.c $(LDSCRIPT) Makefile\r
+ $(CC) -c $(THUMB_FLAGS) $(CFLAGS) $< -o $@\r
+\r
+$(ARM_OBJ) : %.o : %.c $(LDSCRIPT) Makefile\r
+ $(CC) -c $(CFLAGS) $< -o $@\r
+\r
+clean :\r
+ touch Makefile\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+ \r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+ Changes from V2.5.2\r
+ \r
+ + All LED's are turned off to start.\r
+*/\r
+\r
+\r
+#include "FreeRTOS.h"\r
+#include "partest.h"\r
+\r
+#define partstFIRST_IO ( ( unsigned portLONG ) 0x400 )\r
+#define partstNUM_LEDS ( 4 )\r
+#define partstALL_OUTPUTS_OFF ( ( unsigned portLONG ) 0xffffffff )\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple parallel port IO routines.\r
+ *-----------------------------------------------------------*/\r
+\r
+void vParTestInitialise( void )\r
+{\r
+ /* This is performed from main() as the io bits are shared with other setup\r
+ functions. */\r
+\r
+ /* Turn all outputs off. */\r
+ GPIO_IOSET = partstALL_OUTPUTS_OFF;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )\r
+{\r
+unsigned portLONG ulLED = partstFIRST_IO;\r
+\r
+ if( uxLED < partstNUM_LEDS )\r
+ {\r
+ /* Rotate to the wanted bit of port 0. Only P10 to P13 have an LED\r
+ attached. */\r
+ ulLED <<= ( unsigned portLONG ) uxLED;\r
+\r
+ /* Set of clear the output. */\r
+ if( xValue )\r
+ {\r
+ GPIO_IOCLR = ulLED;\r
+ }\r
+ else\r
+ {\r
+ GPIO_IOSET = ulLED; \r
+ }\r
+ } \r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+unsigned portLONG ulLED = partstFIRST_IO, ulCurrentState;\r
+\r
+ if( uxLED < partstNUM_LEDS )\r
+ {\r
+ /* Rotate to the wanted bit of port 0. Only P10 to P13 have an LED\r
+ attached. */\r
+ ulLED <<= ( unsigned portLONG ) uxLED;\r
+\r
+ /* If this bit is already set, clear it, and visa versa. */\r
+ ulCurrentState = GPIO0_IOPIN;\r
+ if( ulCurrentState & ulLED )\r
+ {\r
+ GPIO_IOCLR = ulLED;\r
+ }\r
+ else\r
+ {\r
+ GPIO_IOSET = ulLED; \r
+ }\r
+ } \r
+}\r
+\r
--- /dev/null
+ /* Sample initialization file */\r
+\r
+ .extern main\r
+ .extern exit\r
+\r
+ .text\r
+ .code 32\r
+\r
+\r
+ .align 0\r
+\r
+ .extern __bss_beg__\r
+ .extern __bss_end__\r
+ .extern __stack_end__\r
+ .extern __data_beg__\r
+ .extern __data_end__\r
+ .extern __data+beg_src__\r
+\r
+ .global start\r
+ .global endless_loop\r
+\r
+ /* Stack Sizes */\r
+ .set UND_STACK_SIZE, 0x00000004\r
+ .set ABT_STACK_SIZE, 0x00000004\r
+ .set FIQ_STACK_SIZE, 0x00000004\r
+ .set IRQ_STACK_SIZE, 0X00000400\r
+ .set SVC_STACK_SIZE, 0x00000400\r
+\r
+ /* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */\r
+ .set MODE_USR, 0x10 /* User Mode */\r
+ .set MODE_FIQ, 0x11 /* FIQ Mode */\r
+ .set MODE_IRQ, 0x12 /* IRQ Mode */\r
+ .set MODE_SVC, 0x13 /* Supervisor Mode */\r
+ .set MODE_ABT, 0x17 /* Abort Mode */\r
+ .set MODE_UND, 0x1B /* Undefined Mode */\r
+ .set MODE_SYS, 0x1F /* System Mode */\r
+\r
+ .equ I_BIT, 0x80 /* when I bit is set, IRQ is disabled */\r
+ .equ F_BIT, 0x40 /* when F bit is set, FIQ is disabled */\r
+\r
+\r
+start:\r
+_start:\r
+_mainCRTStartup:\r
+\r
+ /* Setup a stack for each mode - note that this only sets up a usable stack\r
+ for system/user, SWI and IRQ modes. Also each mode is setup with\r
+ interrupts initially disabled. */\r
+ ldr r0, .LC6\r
+ msr CPSR_c, #MODE_UND|I_BIT|F_BIT /* Undefined Instruction Mode\r
+ mov sp, r0\r
+ sub r0, r0, #UND_STACK_SIZE\r
+ msr CPSR_c, #MODE_ABT|I_BIT|F_BIT /* Abort Mode */\r
+ mov sp, r0\r
+ sub r0, r0, #ABT_STACK_SIZE\r
+ msr CPSR_c, #MODE_FIQ|I_BIT|F_BIT /* FIQ Mode */\r
+ mov sp, r0\r
+ sub r0, r0, #FIQ_STACK_SIZE\r
+ msr CPSR_c, #MODE_IRQ|I_BIT|F_BIT /* IRQ Mode */\r
+ mov sp, r0\r
+ sub r0, r0, #IRQ_STACK_SIZE\r
+ msr CPSR_c, #MODE_SVC|I_BIT|F_BIT /* Supervisor Mode */\r
+ mov sp, r0\r
+ sub r0, r0, #SVC_STACK_SIZE\r
+ msr CPSR_c, #MODE_SYS|I_BIT|F_BIT /* System Mode */\r
+ mov sp, r0\r
+\r
+ /* We want to start in supervisor mode. Operation will switch to system\r
+ mode when the first task starts. */\r
+ msr CPSR_c, #MODE_SVC|I_BIT|F_BIT\r
+\r
+ /* Clear BSS. */\r
+\r
+ mov a2, #0 /* Fill value */\r
+ mov fp, a2 /* Null frame pointer */\r
+ mov r7, a2 /* Null frame pointer for Thumb */\r
+\r
+ ldr r1, .LC1 /* Start of memory block */\r
+ ldr r3, .LC2 /* End of memory block */\r
+ subs r3, r3, r1 /* Length of block */\r
+ beq .end_clear_loop\r
+ mov r2, #0\r
+\r
+.clear_loop:\r
+ strb r2, [r1], #1\r
+ subs r3, r3, #1\r
+ bgt .clear_loop\r
+\r
+.end_clear_loop:\r
+\r
+ /* Initialise data. */\r
+\r
+ ldr r1, .LC3 /* Start of memory block */\r
+ ldr r2, .LC4 /* End of memory block */\r
+ ldr r3, .LC5\r
+ subs r3, r3, r1 /* Length of block */\r
+ beq .end_set_loop\r
+\r
+.set_loop:\r
+ ldrb r4, [r2], #1\r
+ strb r4, [r1], #1\r
+ subs r3, r3, #1\r
+ bgt .set_loop\r
+\r
+.end_set_loop:\r
+\r
+ mov r0, #0 /* no arguments */\r
+ mov r1, #0 /* no argv either */\r
+\r
+ bl main\r
+\r
+endless_loop:\r
+ b endless_loop\r
+\r
+\r
+ .align 0\r
+\r
+ .LC1:\r
+ .word __bss_beg__\r
+ .LC2:\r
+ .word __bss_end__\r
+ .LC3:\r
+ .word __data_beg__\r
+ .LC4:\r
+ .word __data_beg_src__\r
+ .LC5:\r
+ .word __data_end__\r
+ .LC6:\r
+ .word __stack_end__\r
+\r
+\r
+ /* Setup vector table. Note that undf, pabt, dabt, fiq just execute\r
+ a null loop. */\r
+\r
+.section .startup,"ax"\r
+ .code 32\r
+ .align 0\r
+\r
+ b _start /* reset - _start */\r
+ ldr pc, _undf /* undefined - _undf */\r
+ ldr pc, _swi /* SWI - _swi */\r
+ ldr pc, _pabt /* program abort - _pabt */\r
+ ldr pc, _dabt /* data abort - _dabt */\r
+ nop /* reserved */\r
+ ldr pc, [pc,#-0xFF0] /* IRQ - read the VIC */\r
+ ldr pc, _fiq /* FIQ - _fiq */\r
+\r
+_undf: .word __undf /* undefined */\r
+_swi: .word vPortYieldProcessor /* SWI */\r
+_pabt: .word __pabt /* program abort */\r
+_dabt: .word __dabt /* data abort */\r
+_fiq: .word __fiq /* FIQ */\r
+\r
+__undf: b . /* undefined */\r
+__pabt: b . /* program abort */\r
+__dabt: b . /* data abort */\r
+__fiq: b . /* FIQ */\r
--- /dev/null
+MEMORY \r
+{\r
+ flash : ORIGIN = 0, LENGTH = 120K\r
+ ram : ORIGIN = 0x40000000, LENGTH = 64K\r
+}\r
+\r
+__stack_end__ = 0x40000000 + 64K - 4;\r
+\r
+SECTIONS \r
+{\r
+ . = 0;\r
+ startup : { *(.startup)} >ram\r
+\r
+ prog : \r
+ {\r
+ *(.text)\r
+ *(.rodata)\r
+ *(.rodata*)\r
+ *(.glue_7)\r
+ *(.glue_7t)\r
+ } >ram\r
+\r
+ __end_of_text__ = .;\r
+\r
+ .data : \r
+ {\r
+ __data_beg__ = .;\r
+ __data_beg_src__ = __end_of_text__;\r
+ *(.data)\r
+ __data_end__ = .;\r
+ } >ram\r
+\r
+ .bss : \r
+ {\r
+ __bss_beg__ = .;\r
+ *(.bss)\r
+ } >ram\r
+\r
+ /* Align here to ensure that the .bss section occupies space up to\r
+ _end. Align after .bss to ensure correct alignment even if the\r
+ .bss section disappears because there are no input sections. */\r
+ . = ALIGN(32 / 8);\r
+}\r
+ . = ALIGN(32 / 8);\r
+ _end = .;\r
+ _bss_end__ = . ; __bss_end__ = . ; __end__ = . ;\r
+ PROVIDE (end = .);\r
+\r
+\r
--- /dev/null
+MEMORY \r
+{\r
+ flash : ORIGIN = 0, LENGTH = 120K\r
+ ram : ORIGIN = 0x40000000, LENGTH = 64K\r
+}\r
+\r
+__stack_end__ = 0x40000000 + 64K - 4;\r
+\r
+SECTIONS \r
+{\r
+ . = 0;\r
+ startup : { *(.startup)} >flash\r
+\r
+ prog : \r
+ {\r
+ *(.text)\r
+ *(.rodata)\r
+ *(.rodata*)\r
+ *(.glue_7)\r
+ *(.glue_7t)\r
+ } >flash\r
+\r
+ __end_of_text__ = .;\r
+\r
+ .data : \r
+ {\r
+ __data_beg__ = .;\r
+ __data_beg_src__ = __end_of_text__;\r
+ *(.data)\r
+ __data_end__ = .;\r
+ } >ram AT>flash\r
+\r
+ .bss : \r
+ {\r
+ __bss_beg__ = .;\r
+ *(.bss)\r
+ } >ram\r
+\r
+ /* Align here to ensure that the .bss section occupies space up to\r
+ _end. Align after .bss to ensure correct alignment even if the\r
+ .bss section disappears because there are no input sections. */\r
+ . = ALIGN(32 / 8);\r
+}\r
+ . = ALIGN(32 / 8);\r
+ _end = .;\r
+ _bss_end__ = . ; __bss_end__ = . ; __end__ = . ;\r
+ PROVIDE (end = .);\r
+\r
+\r
--- /dev/null
+#ifndef lpc210x_h\r
+#define lpc210x_h\r
+/*******************************************************************************\r
+lpc210x.h - Register defs for Philips LPC210X: LPC2104, LPC2105 and LPC2106\r
+\r
+ \r
+THE SOFTWARE IS DELIVERED "AS IS" WITHOUT WARRANTY OR CONDITION OF ANY KIND, \r
+EITHER EXPRESS, IMPLIED OR STATUTORY. THIS INCLUDES WITHOUT LIMITATION ANY \r
+WARRANTY OR CONDITION WITH RESPECT TO MERCHANTABILITY OR FITNESS FOR ANY \r
+PARTICULAR PURPOSE, OR AGAINST THE INFRINGEMENTS OF INTELLECTUAL PROPERTY RIGHTS \r
+OF OTHERS.\r
+ \r
+This file may be freely used for commercial and non-commercial applications, \r
+including being redistributed with any tools.\r
+\r
+If you find a problem with the file, please report it so that it can be fixed.\r
+\r
+Created by Sten Larsson (sten_larsson at yahoo com)\r
+\r
+Edited by Richard Barry.\r
+*******************************************************************************/\r
+\r
+#define REG8 (volatile unsigned char*)\r
+#define REG16 (volatile unsigned short*)\r
+#define REG32 (volatile unsigned int*)\r
+\r
+\r
+/*##############################################################################\r
+## MISC\r
+##############################################################################*/\r
+\r
+ /* Constants for data to put in IRQ/FIQ Exception Vectors */\r
+#define VECTDATA_IRQ 0xE51FFFF0 /* LDR PC,[PC,#-0xFF0] */\r
+#define VECTDATA_FIQ /* __TODO */\r
+\r
+\r
+/*##############################################################################\r
+## VECTORED INTERRUPT CONTROLLER\r
+##############################################################################*/\r
+\r
+#define VICIRQStatus (*(REG32 (0xFFFFF000)))\r
+#define VICFIQStatus (*(REG32 (0xFFFFF004)))\r
+#define VICRawIntr (*(REG32 (0xFFFFF008)))\r
+#define VICIntSelect (*(REG32 (0xFFFFF00C)))\r
+#define VICIntEnable (*(REG32 (0xFFFFF010)))\r
+#define VICIntEnClear (*(REG32 (0xFFFFF014)))\r
+#define VICSoftInt (*(REG32 (0xFFFFF018)))\r
+#define VICSoftIntClear (*(REG32 (0xFFFFF01C)))\r
+#define VICProtection (*(REG32 (0xFFFFF020)))\r
+#define VICVectAddr (*(REG32 (0xFFFFF030)))\r
+#define VICDefVectAddr (*(REG32 (0xFFFFF034)))\r
+\r
+#define VICVectAddr0 (*(REG32 (0xFFFFF100)))\r
+#define VICVectAddr1 (*(REG32 (0xFFFFF104)))\r
+#define VICVectAddr2 (*(REG32 (0xFFFFF108)))\r
+#define VICVectAddr3 (*(REG32 (0xFFFFF10C)))\r
+#define VICVectAddr4 (*(REG32 (0xFFFFF110)))\r
+#define VICVectAddr5 (*(REG32 (0xFFFFF114)))\r
+#define VICVectAddr6 (*(REG32 (0xFFFFF118)))\r
+#define VICVectAddr7 (*(REG32 (0xFFFFF11C)))\r
+#define VICVectAddr8 (*(REG32 (0xFFFFF120)))\r
+#define VICVectAddr9 (*(REG32 (0xFFFFF124)))\r
+#define VICVectAddr10 (*(REG32 (0xFFFFF128)))\r
+#define VICVectAddr11 (*(REG32 (0xFFFFF12C)))\r
+#define VICVectAddr12 (*(REG32 (0xFFFFF130)))\r
+#define VICVectAddr13 (*(REG32 (0xFFFFF134)))\r
+#define VICVectAddr14 (*(REG32 (0xFFFFF138)))\r
+#define VICVectAddr15 (*(REG32 (0xFFFFF13C)))\r
+\r
+#define VICVectCntl0 (*(REG32 (0xFFFFF200)))\r
+#define VICVectCntl1 (*(REG32 (0xFFFFF204)))\r
+#define VICVectCntl2 (*(REG32 (0xFFFFF208)))\r
+#define VICVectCntl3 (*(REG32 (0xFFFFF20C)))\r
+#define VICVectCntl4 (*(REG32 (0xFFFFF210)))\r
+#define VICVectCntl5 (*(REG32 (0xFFFFF214)))\r
+#define VICVectCntl6 (*(REG32 (0xFFFFF218)))\r
+#define VICVectCntl7 (*(REG32 (0xFFFFF21C)))\r
+#define VICVectCntl8 (*(REG32 (0xFFFFF220)))\r
+#define VICVectCntl9 (*(REG32 (0xFFFFF224)))\r
+#define VICVectCntl10 (*(REG32 (0xFFFFF228)))\r
+#define VICVectCntl11 (*(REG32 (0xFFFFF22C)))\r
+#define VICVectCntl12 (*(REG32 (0xFFFFF230)))\r
+#define VICVectCntl13 (*(REG32 (0xFFFFF234)))\r
+#define VICVectCntl14 (*(REG32 (0xFFFFF238)))\r
+#define VICVectCntl15 (*(REG32 (0xFFFFF23C)))\r
+\r
+#define VICITCR (*(REG32 (0xFFFFF300)))\r
+#define VICITIP1 (*(REG32 (0xFFFFF304)))\r
+#define VICITIP2 (*(REG32 (0xFFFFF308)))\r
+#define VICITOP1 (*(REG32 (0xFFFFF30C)))\r
+#define VICITOP2 (*(REG32 (0xFFFFF310)))\r
+#define VICPeriphID0 (*(REG32 (0xFFFFFFE0)))\r
+#define VICPeriphID1 (*(REG32 (0xFFFFFFE4)))\r
+#define VICPeriphID2 (*(REG32 (0xFFFFFFE8)))\r
+#define VICPeriphID3 (*(REG32 (0xFFFFFFEC)))\r
+\r
+#define VICIntEnClr VICIntEnClear\r
+#define VICSoftIntClr VICSoftIntClear\r
+\r
+\r
+/*##############################################################################\r
+## PCB - Pin Connect Block\r
+##############################################################################*/\r
+\r
+#define PCB_PINSEL0 (*(REG32 (0xE002C000)))\r
+#define PCB_PINSEL1 (*(REG32 (0xE002C004)))\r
+\r
+\r
+/*##############################################################################\r
+## GPIO - General Purpose I/O\r
+##############################################################################*/\r
+\r
+#define GPIO_IOPIN (*(REG32 (0xE0028000))) /* ALTERNATE NAME GPIO = GPIO0 */\r
+#define GPIO_IOSET (*(REG32 (0xE0028004)))\r
+#define GPIO_IODIR (*(REG32 (0xE0028008)))\r
+#define GPIO_IOCLR (*(REG32 (0xE002800C)))\r
+\r
+#define GPIO0_IOPIN (*(REG32 (0xE0028000))) /* ALTERNATE NAME GPIO = GPIO0 */\r
+#define GPIO0_IOSET (*(REG32 (0xE0028004)))\r
+#define GPIO0_IODIR (*(REG32 (0xE0028008)))\r
+#define GPIO0_IOCLR (*(REG32 (0xE002800C)))\r
+\r
+\r
+/*##############################################################################\r
+## UART0 / UART1\r
+##############################################################################*/\r
+\r
+/* ---- UART 0 --------------------------------------------- */\r
+#define UART0_RBR (*(REG32 (0xE000C000)))\r
+#define UART0_THR (*(REG32 (0xE000C000)))\r
+#define UART0_IER (*(REG32 (0xE000C004)))\r
+#define UART0_IIR (*(REG32 (0xE000C008)))\r
+#define UART0_FCR (*(REG32 (0xE000C008)))\r
+#define UART0_LCR (*(REG32 (0xE000C00C)))\r
+#define UART0_LSR (*(REG32 (0xE000C014)))\r
+#define UART0_SCR (*(REG32 (0xE000C01C)))\r
+#define UART0_DLL (*(REG32 (0xE000C000)))\r
+#define UART0_DLM (*(REG32 (0xE000C004)))\r
+\r
+/* ---- UART 1 --------------------------------------------- */\r
+#define UART1_RBR (*(REG32 (0xE0010000)))\r
+#define UART1_THR (*(REG32 (0xE0010000)))\r
+#define UART1_IER (*(REG32 (0xE0010004)))\r
+#define UART1_IIR (*(REG32 (0xE0010008)))\r
+#define UART1_FCR (*(REG32 (0xE0010008)))\r
+#define UART1_LCR (*(REG32 (0xE001000C)))\r
+#define UART1_LSR (*(REG32 (0xE0010014)))\r
+#define UART1_SCR (*(REG32 (0xE001001C)))\r
+#define UART1_DLL (*(REG32 (0xE0010000)))\r
+#define UART1_DLM (*(REG32 (0xE0010004)))\r
+#define UART1_MCR (*(REG32 (0xE0010010)))\r
+#define UART1_MSR (*(REG32 (0xE0010018)))\r
+\r
+\r
+/*##############################################################################\r
+## I2C\r
+##############################################################################*/\r
+\r
+#define I2C_I2CONSET (*(REG32 (0xE001C000)))\r
+#define I2C_I2STAT (*(REG32 (0xE001C004)))\r
+#define I2C_I2DAT (*(REG32 (0xE001C008)))\r
+#define I2C_I2ADR (*(REG32 (0xE001C00C)))\r
+#define I2C_I2SCLH (*(REG32 (0xE001C010)))\r
+#define I2C_I2SCLL (*(REG32 (0xE001C014)))\r
+#define I2C_I2CONCLR (*(REG32 (0xE001C018)))\r
+\r
+\r
+/*##############################################################################\r
+## SPI - Serial Peripheral Interface\r
+##############################################################################*/\r
+\r
+#define SPI_SPCR (*(REG32 (0xE0020000)))\r
+#define SPI_SPSR (*(REG32 (0xE0020004)))\r
+#define SPI_SPDR (*(REG32 (0xE0020008)))\r
+#define SPI_SPCCR (*(REG32 (0xE002000C)))\r
+#define SPI_SPTCR (*(REG32 (0xE0020010)))\r
+#define SPI_SPTSR (*(REG32 (0xE0020014)))\r
+#define SPI_SPTOR (*(REG32 (0xE0020018)))\r
+#define SPI_SPINT (*(REG32 (0xE002001C)))\r
+\r
+\r
+/*##############################################################################\r
+## Timer 0 and Timer 1\r
+##############################################################################*/\r
+\r
+/* ---- Timer 0 -------------------------------------------- */\r
+#define T0_IR (*(REG32 (0xE0004000)))\r
+#define T0_TCR (*(REG32 (0xE0004004)))\r
+#define T0_TC (*(REG32 (0xE0004008)))\r
+#define T0_PR (*(REG32 (0xE000400C)))\r
+#define T0_PC (*(REG32 (0xE0004010)))\r
+#define T0_MCR (*(REG32 (0xE0004014)))\r
+#define T0_MR0 (*(REG32 (0xE0004018)))\r
+#define T0_MR1 (*(REG32 (0xE000401C)))\r
+#define T0_MR2 (*(REG32 (0xE0004020)))\r
+#define T0_MR3 (*(REG32 (0xE0004024)))\r
+#define T0_CCR (*(REG32 (0xE0004028)))\r
+#define T0_CR0 (*(REG32 (0xE000402C)))\r
+#define T0_CR1 (*(REG32 (0xE0004030)))\r
+#define T0_CR2 (*(REG32 (0xE0004034)))\r
+#define T0_CR3 (*(REG32 (0xE0004038)))\r
+#define T0_EMR (*(REG32 (0xE000403C)))\r
+\r
+/* ---- Timer 1 -------------------------------------------- */\r
+#define T1_IR (*(REG32 (0xE0008000)))\r
+#define T1_TCR (*(REG32 (0xE0008004)))\r
+#define T1_TC (*(REG32 (0xE0008008)))\r
+#define T1_PR (*(REG32 (0xE000800C)))\r
+#define T1_PC (*(REG32 (0xE0008010)))\r
+#define T1_MCR (*(REG32 (0xE0008014)))\r
+#define T1_MR0 (*(REG32 (0xE0008018)))\r
+#define T1_MR1 (*(REG32 (0xE000801C)))\r
+#define T1_MR2 (*(REG32 (0xE0008020)))\r
+#define T1_MR3 (*(REG32 (0xE0008024)))\r
+#define T1_CCR (*(REG32 (0xE0008028)))\r
+#define T1_CR0 (*(REG32 (0xE000802C)))\r
+#define T1_CR1 (*(REG32 (0xE0008030)))\r
+#define T1_CR2 (*(REG32 (0xE0008034)))\r
+#define T1_CR3 (*(REG32 (0xE0008038)))\r
+#define T1_EMR (*(REG32 (0xE000803C)))\r
+\r
+\r
+/*##############################################################################\r
+## PWM\r
+##############################################################################*/\r
+\r
+#define PWM_IR (*(REG32 (0xE0014000)))\r
+#define PWM_TCR (*(REG32 (0xE0014004)))\r
+#define PWM_TC (*(REG32 (0xE0014008)))\r
+#define PWM_PR (*(REG32 (0xE001400C)))\r
+#define PWM_PC (*(REG32 (0xE0014010)))\r
+#define PWM_MCR (*(REG32 (0xE0014014)))\r
+#define PWM_MR0 (*(REG32 (0xE0014018)))\r
+#define PWM_MR1 (*(REG32 (0xE001401C)))\r
+#define PWM_MR2 (*(REG32 (0xE0014020)))\r
+#define PWM_MR3 (*(REG32 (0xE0014024)))\r
+#define PWM_MR4 (*(REG32 (0xE0014040)))\r
+#define PWM_MR5 (*(REG32 (0xE0014044)))\r
+#define PWM_MR6 (*(REG32 (0xE0014048)))\r
+#define PWM_EMR (*(REG32 (0xE001403C)))\r
+#define PWM_PCR (*(REG32 (0xE001404C)))\r
+#define PWM_LER (*(REG32 (0xE0014050)))\r
+#define PWM_CCR (*(REG32 (0xE0014028)))\r
+#define PWM_CR0 (*(REG32 (0xE001402C)))\r
+#define PWM_CR1 (*(REG32 (0xE0014030)))\r
+#define PWM_CR2 (*(REG32 (0xE0014034)))\r
+#define PWM_CR3 (*(REG32 (0xE0014038)))\r
+\r
+/*##############################################################################\r
+## RTC\r
+##############################################################################*/\r
+\r
+/* ---- RTC: Miscellaneous Register Group ------------------ */\r
+#define RTC_ILR (*(REG32 (0xE0024000)))\r
+#define RTC_CTC (*(REG32 (0xE0024004)))\r
+#define RTC_CCR (*(REG32 (0xE0024008))) \r
+#define RTC_CIIR (*(REG32 (0xE002400C)))\r
+#define RTC_AMR (*(REG32 (0xE0024010)))\r
+#define RTC_CTIME0 (*(REG32 (0xE0024014)))\r
+#define RTC_CTIME1 (*(REG32 (0xE0024018)))\r
+#define RTC_CTIME2 (*(REG32 (0xE002401C)))\r
+\r
+/* ---- RTC: Timer Control Group --------------------------- */\r
+#define RTC_SEC (*(REG32 (0xE0024020)))\r
+#define RTC_MIN (*(REG32 (0xE0024024)))\r
+#define RTC_HOUR (*(REG32 (0xE0024028)))\r
+#define RTC_DOM (*(REG32 (0xE002402C)))\r
+#define RTC_DOW (*(REG32 (0xE0024030)))\r
+#define RTC_DOY (*(REG32 (0xE0024034)))\r
+#define RTC_MONTH (*(REG32 (0xE0024038)))\r
+#define RTC_YEAR (*(REG32 (0xE002403C)))\r
+\r
+/* ---- RTC: Alarm Control Group --------------------------- */\r
+#define RTC_ALSEC (*(REG32 (0xE0024060)))\r
+#define RTC_ALMIN (*(REG32 (0xE0024064)))\r
+#define RTC_ALHOUR (*(REG32 (0xE0024068)))\r
+#define RTC_ALDOM (*(REG32 (0xE002406C)))\r
+#define RTC_ALDOW (*(REG32 (0xE0024070)))\r
+#define RTC_ALDOY (*(REG32 (0xE0024074)))\r
+#define RTC_ALMON (*(REG32 (0xE0024078)))\r
+#define RTC_ALYEAR (*(REG32 (0xE002407C)))\r
+\r
+/* ---- RTC: Reference Clock Divider Group ----------------- */\r
+#define RTC_PREINT (*(REG32 (0xE0024080)))\r
+#define RTC_PREFRAC (*(REG32 (0xE0024084)))\r
+\r
+\r
+/*##############################################################################\r
+## WD - Watchdog\r
+##############################################################################*/\r
+\r
+#define WD_WDMOD (*(REG32 (0xE0000000)))\r
+#define WD_WDTC (*(REG32 (0xE0000004)))\r
+#define WD_WDFEED (*(REG32 (0xE0000008)))\r
+#define WD_WDTV (*(REG32 (0xE000000C)))\r
+\r
+\r
+/*##############################################################################\r
+## System Control Block\r
+##############################################################################*/\r
+\r
+#define SCB_EXTINT (*(REG32 (0xE01FC140)))\r
+#define SCB_EXTWAKE (*(REG32 (0xE01FC144)))\r
+#define SCB_MEMMAP (*(REG32 (0xE01FC040)))\r
+#define SCB_PLLCON (*(REG32 (0xE01FC080)))\r
+#define SCB_PLLCFG (*(REG32 (0xE01FC084)))\r
+#define SCB_PLLSTAT (*(REG32 (0xE01FC088)))\r
+#define SCB_PLLFEED (*(REG32 (0xE01FC08C)))\r
+#define SCB_PCON (*(REG32 (0xE01FC0C0)))\r
+#define SCB_PCONP (*(REG32 (0xE01FC0C4)))\r
+#define SCB_VPBDIV (*(REG32 (0xE01FC100)))\r
+\r
+/*##############################################################################\r
+## Memory Accelerator Module (MAM)\r
+##############################################################################*/\r
+\r
+#define MAM_TIM (*(REG32 (0xE01FC004)))\r
+#define MAM_CR (*(REG32 (0xE01FC000)))\r
+\r
+#endif /* lpc210x_h */\r
+\r
--- /dev/null
+#include "lpc2114.h"
\ No newline at end of file
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* \r
+ NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.\r
+ The processor MUST be in supervisor mode when vTaskStartScheduler is \r
+ called. The demo applications included in the FreeRTOS.org download switch\r
+ to supervisor mode prior to main being called. If you are not using one of\r
+ these demo application projects then ensure Supervisor mode is used.\r
+*/\r
+\r
+\r
+/*\r
+ * Creates all the demo application tasks, then starts the scheduler. The WEB\r
+ * documentation provides more details of the demo application tasks.\r
+ * \r
+ * Main.c also creates a task called "Check". This only executes every three \r
+ * seconds but has the highest priority so is guaranteed to get processor time. \r
+ * Its main function is to check that all the other tasks are still operational.\r
+ * Each task (other than the "flash" tasks) maintains a unique count that is \r
+ * incremented each time the task successfully completes its function. Should \r
+ * any error occur within such a task the count is permanently halted. The \r
+ * check task inspects the count of each task to ensure it has changed since\r
+ * the last time the check task executed. If all the count variables have \r
+ * changed all the tasks are still executing error free, and the check task\r
+ * toggles the onboard LED. Should any task contain an error at any time \r
+ * the LED toggle rate will change from 3 seconds to 500ms.\r
+ *\r
+ * To check the operation of the memory allocator the check task also \r
+ * dynamically creates a task before delaying, and deletes it again when it \r
+ * wakes. If memory cannot be allocated for the new task the call to xTaskCreate\r
+ * will fail and an error is signalled. The dynamically created task itself\r
+ * allocates and frees memory just to give the allocator a bit more exercise.\r
+ *\r
+ */\r
+\r
+/* \r
+ Changes from V2.4.2\r
+\r
+ + The vErrorChecks() task now dynamically creates then deletes a task each\r
+ cycle. This tests the operation of the memory allocator.\r
+\r
+ Changes from V2.5.2\r
+ \r
+ + vParTestInitialise() is called during initialisation to ensure all the \r
+ LED's start off.\r
+*/\r
+\r
+\r
+/* Standard includes. */\r
+#include <stdlib.h>\r
+#include <string.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo application includes. */\r
+#include "partest.h"\r
+#include "flash.h"\r
+#include "integer.h"\r
+#include "PollQ.h"\r
+#include "comtest2.h"\r
+#include "semtest.h"\r
+#include "flop.h"\r
+#include "dynamic.h"\r
+#include "BlockQ.h"\r
+#include "serial.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Constants to setup I/O. */\r
+#define mainTX_ENABLE ( ( unsigned portLONG ) 0x0001 )\r
+#define mainRX_ENABLE ( ( unsigned portLONG ) 0x0004 )\r
+#define mainP0_14 ( ( unsigned portLONG ) 0x4000 )\r
+#define mainJTAG_PORT ( ( unsigned portLONG ) 0x3E0000UL )\r
+\r
+/* Constants to setup the PLL. */\r
+#define mainPLL_MUL_4 ( ( unsigned portCHAR ) 0x0003 )\r
+#define mainPLL_DIV_1 ( ( unsigned portCHAR ) 0x0000 )\r
+#define mainPLL_ENABLE ( ( unsigned portCHAR ) 0x0001 )\r
+#define mainPLL_CONNECT ( ( unsigned portCHAR ) 0x0003 )\r
+#define mainPLL_FEED_BYTE1 ( ( unsigned portCHAR ) 0xaa )\r
+#define mainPLL_FEED_BYTE2 ( ( unsigned portCHAR ) 0x55 )\r
+#define mainPLL_LOCK ( ( unsigned portLONG ) 0x0400 )\r
+\r
+/* Constants to setup the MAM. */\r
+#define mainMAM_TIM_3 ( ( unsigned portCHAR ) 0x03 )\r
+#define mainMAM_MODE_FULL ( ( unsigned portCHAR ) 0x02 )\r
+\r
+/* Constants to setup the peripheral bus. */\r
+#define mainBUS_CLK_FULL ( ( unsigned portCHAR ) 0x01 )\r
+\r
+/* Constants for the ComTest tasks. */\r
+#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 115200 )\r
+#define mainCOM_TEST_LED ( 3 )\r
+\r
+/* Priorities for the demo application tasks. */\r
+#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 )\r
+#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+\r
+/* The rate at which the on board LED will toggle when there is/is not an \r
+error. */\r
+#define mainNO_ERROR_FLASH_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS )\r
+#define mainERROR_FLASH_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS )\r
+#define mainON_BOARD_LED_BIT ( ( unsigned portLONG ) 0x80 )\r
+\r
+/* Constants used by the vMemCheckTask() task. */\r
+#define mainCOUNT_INITIAL_VALUE ( ( unsigned portLONG ) 0 )\r
+#define mainNO_TASK ( 0 )\r
+\r
+/* The size of the memory blocks allocated by the vMemCheckTask() task. */\r
+#define mainMEM_CHECK_SIZE_1 ( ( size_t ) 51 )\r
+#define mainMEM_CHECK_SIZE_2 ( ( size_t ) 52 )\r
+#define mainMEM_CHECK_SIZE_3 ( ( size_t ) 151 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The Olimex demo board has a single built in LED. This function simply\r
+ * toggles its state. \r
+ */\r
+void prvToggleOnBoardLED( void );\r
+\r
+/*\r
+ * Checks that all the demo application tasks are still executing without error\r
+ * - as described at the top of the file.\r
+ */\r
+static portLONG prvCheckOtherTasksAreStillRunning( unsigned portLONG ulMemCheckTaskCount );\r
+\r
+/*\r
+ * The task that executes at the highest priority and calls \r
+ * prvCheckOtherTasksAreStillRunning(). See the description at the top\r
+ * of the file.\r
+ */\r
+static void vErrorChecks( void *pvParameters );\r
+\r
+/*\r
+ * Dynamically created and deleted during each cycle of the vErrorChecks()\r
+ * task. This is done to check the operation of the memory allocator.\r
+ * See the top of vErrorChecks for more details.\r
+ */\r
+static void vMemCheckTask( void *pvParameters );\r
+\r
+/*\r
+ * Configure the processor for use with the Olimex demo board. This includes\r
+ * setup for the I/O, system clock, and access timings.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Starts all the other tasks, then starts the scheduler. \r
+ */\r
+int main( void )\r
+{\r
+ /* Setup the hardware for use with the Olimex demo board. */\r
+ prvSetupHardware();\r
+\r
+ /* Start the demo/test application tasks. */\r
+ vStartIntegerMathTasks( tskIDLE_PRIORITY );\r
+ vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED );\r
+ vStartLEDFlashTasks( mainLED_TASK_PRIORITY );\r
+ vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
+ vStartMathTasks( tskIDLE_PRIORITY );\r
+ vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
+ vStartDynamicPriorityTasks();\r
+ vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
+\r
+ /* Start the check task - which is defined in this file. */\r
+ xTaskCreate( vErrorChecks, ( signed portCHAR * ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
+\r
+ /* Now all the tasks have been started - start the scheduler.\r
+\r
+ NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.\r
+ The processor MUST be in supervisor mode when vTaskStartScheduler is \r
+ called. The demo applications included in the FreeRTOS.org download switch\r
+ to supervisor mode prior to main being called. If you are not using one of\r
+ these demo application projects then ensure Supervisor mode is used here. */\r
+ vTaskStartScheduler();\r
+\r
+ /* Should never reach here! */\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vErrorChecks( void *pvParameters )\r
+{\r
+portTickType xDelayPeriod = mainNO_ERROR_FLASH_PERIOD;\r
+unsigned portLONG ulMemCheckTaskRunningCount;\r
+xTaskHandle xCreatedTask;\r
+\r
+ /* The parameters are not used in this function. */\r
+ ( void ) pvParameters;\r
+\r
+ /* Cycle for ever, delaying then checking all the other tasks are still\r
+ operating without error. If an error is detected then the delay period\r
+ is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so\r
+ the on board LED flash rate will increase. \r
+ \r
+ In addition to the standard tests the memory allocator is tested through\r
+ the dynamic creation and deletion of a task each cycle. Each time the \r
+ task is created memory must be allocated for its stack. When the task is\r
+ deleted this memory is returned to the heap. If the task cannot be created \r
+ then it is likely that the memory allocation failed. */\r
+\r
+ for( ;; )\r
+ {\r
+ /* Dynamically create a task - passing ulMemCheckTaskRunningCount as a \r
+ parameter. */\r
+ ulMemCheckTaskRunningCount = mainCOUNT_INITIAL_VALUE;\r
+ xCreatedTask = mainNO_TASK;\r
+ if( xTaskCreate( vMemCheckTask, ( signed portCHAR * ) "MEM_CHECK", configMINIMAL_STACK_SIZE, ( void * ) &ulMemCheckTaskRunningCount, tskIDLE_PRIORITY, &xCreatedTask ) != pdPASS )\r
+ {\r
+ /* Could not create the task - we have probably run out of heap. */\r
+ xDelayPeriod = mainERROR_FLASH_PERIOD;\r
+ }\r
+\r
+ /* Delay until it is time to execute again. */\r
+ vTaskDelay( xDelayPeriod );\r
+ \r
+ /* Delete the dynamically created task. */\r
+ if( xCreatedTask != mainNO_TASK )\r
+ {\r
+ vTaskDelete( xCreatedTask );\r
+ }\r
+\r
+ /* Check all the standard demo application tasks are executing without \r
+ error. ulMemCheckTaskRunningCount is checked to ensure it was\r
+ modified by the task just deleted. */\r
+ if( prvCheckOtherTasksAreStillRunning( ulMemCheckTaskRunningCount ) != pdPASS )\r
+ {\r
+ /* An error has been detected in one of the tasks - flash faster. */\r
+ xDelayPeriod = mainERROR_FLASH_PERIOD;\r
+ }\r
+\r
+ prvToggleOnBoardLED();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+ #ifdef RUN_FROM_RAM\r
+ /* Remap the interrupt vectors to RAM if we are are running from RAM. */\r
+ SCB_MEMMAP = 2;\r
+ #endif\r
+\r
+ /* Configure the RS2332 pins. All other pins remain at their default of 0. */\r
+ PCB_PINSEL0 |= mainTX_ENABLE;\r
+ PCB_PINSEL0 |= mainRX_ENABLE;\r
+\r
+ /* Set all GPIO to output other than the P0.14 (BSL), and the JTAG pins. \r
+ The JTAG pins are left as input as I'm not sure what will happen if the \r
+ Wiggler is connected after powerup - not that it would be a good idea to\r
+ do that anyway. */\r
+ GPIO_IODIR = ~( mainP0_14 + mainJTAG_PORT );\r
+\r
+ /* Setup the PLL to multiply the XTAL input by 4. */\r
+ SCB_PLLCFG = ( mainPLL_MUL_4 | mainPLL_DIV_1 );\r
+\r
+ /* Activate the PLL by turning it on then feeding the correct sequence of\r
+ bytes. */\r
+ SCB_PLLCON = mainPLL_ENABLE;\r
+ SCB_PLLFEED = mainPLL_FEED_BYTE1;\r
+ SCB_PLLFEED = mainPLL_FEED_BYTE2;\r
+\r
+ /* Wait for the PLL to lock... */\r
+ while( !( SCB_PLLSTAT & mainPLL_LOCK ) );\r
+\r
+ /* ...before connecting it using the feed sequence again. */\r
+ SCB_PLLCON = mainPLL_CONNECT;\r
+ SCB_PLLFEED = mainPLL_FEED_BYTE1;\r
+ SCB_PLLFEED = mainPLL_FEED_BYTE2;\r
+\r
+ /* Setup and turn on the MAM. Three cycle access is used due to the fast\r
+ PLL used. It is possible faster overall performance could be obtained by\r
+ tuning the MAM and PLL settings. */\r
+ MAM_TIM = mainMAM_TIM_3;\r
+ MAM_CR = mainMAM_MODE_FULL;\r
+\r
+ /* Setup the peripheral bus to be the same as the PLL output. */\r
+ SCB_VPBDIV = mainBUS_CLK_FULL;\r
+ \r
+ /* Initialise LED outputs. */\r
+ vParTestInitialise();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void prvToggleOnBoardLED( void )\r
+{\r
+unsigned portLONG ulState;\r
+\r
+ ulState = GPIO0_IOPIN;\r
+ if( ulState & mainON_BOARD_LED_BIT )\r
+ {\r
+ GPIO_IOCLR = mainON_BOARD_LED_BIT;\r
+ }\r
+ else\r
+ {\r
+ GPIO_IOSET = mainON_BOARD_LED_BIT;\r
+ } \r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portLONG prvCheckOtherTasksAreStillRunning( unsigned portLONG ulMemCheckTaskCount )\r
+{\r
+portLONG lReturn = ( portLONG ) pdPASS;\r
+\r
+ /* Check all the demo tasks (other than the flash tasks) to ensure\r
+ that they are all still running, and that none of them have detected\r
+ an error. */\r
+\r
+ if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ lReturn = ( portLONG ) pdFAIL;\r
+ }\r
+\r
+ if( xAreComTestTasksStillRunning() != pdTRUE )\r
+ {\r
+ lReturn = ( portLONG ) pdFAIL;\r
+ }\r
+\r
+ if( xArePollingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ lReturn = ( portLONG ) pdFAIL;\r
+ }\r
+\r
+ if( xAreMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ lReturn = ( portLONG ) pdFAIL;\r
+ }\r
+\r
+ if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ lReturn = ( portLONG ) pdFAIL;\r
+ }\r
+\r
+ if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )\r
+ {\r
+ lReturn = ( portLONG ) pdFAIL;\r
+ }\r
+\r
+ if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ lReturn = ( portLONG ) pdFAIL;\r
+ }\r
+\r
+ if( ulMemCheckTaskCount == mainCOUNT_INITIAL_VALUE )\r
+ {\r
+ /* The vMemCheckTask did not increment the counter - it must\r
+ have failed. */\r
+ lReturn = ( portLONG ) pdFAIL;\r
+ }\r
+\r
+ return lReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vMemCheckTask( void *pvParameters )\r
+{\r
+unsigned portLONG *pulMemCheckTaskRunningCounter;\r
+void *pvMem1, *pvMem2, *pvMem3;\r
+static portLONG lErrorOccurred = pdFALSE;\r
+\r
+ /* This task is dynamically created then deleted during each cycle of the\r
+ vErrorChecks task to check the operation of the memory allocator. Each time\r
+ the task is created memory is allocated for the stack and TCB. Each time\r
+ the task is deleted this memory is returned to the heap. This task itself\r
+ exercises the allocator by allocating and freeing blocks. \r
+ \r
+ The task executes at the idle priority so does not require a delay. \r
+ \r
+ pulMemCheckTaskRunningCounter is incremented each cycle to indicate to the\r
+ vErrorChecks() task that this task is still executing without error. */\r
+\r
+ pulMemCheckTaskRunningCounter = ( unsigned portLONG * ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ if( lErrorOccurred == pdFALSE )\r
+ {\r
+ /* We have never seen an error so increment the counter. */\r
+ ( *pulMemCheckTaskRunningCounter )++;\r
+ }\r
+\r
+ /* Allocate some memory - just to give the allocator some extra \r
+ exercise. This has to be in a critical section to ensure the\r
+ task does not get deleted while it has memory allocated. */\r
+ vTaskSuspendAll();\r
+ {\r
+ pvMem1 = pvPortMalloc( mainMEM_CHECK_SIZE_1 );\r
+ if( pvMem1 == NULL )\r
+ {\r
+ lErrorOccurred = pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ memset( pvMem1, 0xaa, mainMEM_CHECK_SIZE_1 );\r
+ vPortFree( pvMem1 );\r
+ }\r
+ }\r
+ xTaskResumeAll();\r
+\r
+ /* Again - with a different size block. */\r
+ vTaskSuspendAll();\r
+ {\r
+ pvMem2 = pvPortMalloc( mainMEM_CHECK_SIZE_2 );\r
+ if( pvMem2 == NULL )\r
+ {\r
+ lErrorOccurred = pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ memset( pvMem2, 0xaa, mainMEM_CHECK_SIZE_2 );\r
+ vPortFree( pvMem2 );\r
+ }\r
+ }\r
+ xTaskResumeAll();\r
+\r
+ /* Again - with a different size block. */\r
+ vTaskSuspendAll();\r
+ {\r
+ pvMem3 = pvPortMalloc( mainMEM_CHECK_SIZE_3 );\r
+ if( pvMem3 == NULL )\r
+ {\r
+ lErrorOccurred = pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ memset( pvMem3, 0xaa, mainMEM_CHECK_SIZE_3 );\r
+ vPortFree( pvMem3 );\r
+ }\r
+ }\r
+ xTaskResumeAll();\r
+ }\r
+}\r
+\r
+\r
+\r
--- /dev/null
+set USE_THUMB_MODE=NO\r
+set DEBUG=-g\r
+set OPTIM=-O0\r
+set RUN_MODE=RUN_FROM_RAM\r
+set LDSCRIPT=lpc2106-ram.ld\r
+make\r
--- /dev/null
+set USE_THUMB_MODE=YES\r
+set DEBUG=-g\r
+set OPTIM=-O0\r
+set RUN_MODE=RUN_FROM_RAM\r
+set LDSCRIPT=lpc2106-ram.ld\r
+make\r
--- /dev/null
+Use one of the following four batch files to build the demo application:\r
+\r
++ rom_arm.bat\r
+\r
+Creates an ARM mode release build suitable for programming into flash.\r
+\r
++ ram_arm.bat\r
+\r
+Creates an ARM mode debug build suitable for running from RAM.\r
+\r
++ rom_thumb.bat\r
+\r
+Creates a THUMB mode release build suitable for programming into flash.\r
+\r
++ ram_thumb.bat\r
+\r
+Creates a THUMB mode debug build suitable for running from RAM.\r
+\r
--- /dev/null
+set USE_THUMB_MODE=NO\r
+set DEBUG=\r
+set OPTIM=-O3\r
+set RUN_MODE=RUN_FROM_ROM\r
+set LDSCRIPT=lpc2106-rom.ld\r
+make\r
--- /dev/null
+set USE_THUMB_MODE=YES\r
+set DEBUG=\r
+set OPTIM=-O3\r
+set RUN_MODE=RUN_FROM_ROM\r
+set LDSCRIPT=lpc2106-rom.ld\r
+make\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+ Changes from V2.4.0\r
+\r
+ + Made serial ISR handling more complete and robust.\r
+\r
+ Changes from V2.4.1\r
+\r
+ + Split serial.c into serial.c and serialISR.c. serial.c can be \r
+ compiled using ARM or THUMB modes. serialISR.c must always be\r
+ compiled in ARM mode.\r
+ + Another small change to cSerialPutChar().\r
+\r
+ Changed from V2.5.1\r
+\r
+ + In cSerialPutChar() an extra check is made to ensure the post to\r
+ the queue was successful if then attempting to retrieve the posted\r
+ character.\r
+\r
+*/\r
+\r
+/* \r
+ BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0. \r
+\r
+ This file contains all the serial port components that can be compiled to\r
+ either ARM or THUMB mode. Components that must be compiled to ARM mode are\r
+ contained in serialISR.c.\r
+*/\r
+\r
+/* Standard includes. */\r
+#include <stdlib.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "queue.h"\r
+#include "task.h"\r
+\r
+/* Demo application includes. */\r
+#include "serial.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Constants to setup and access the UART. */\r
+#define serDLAB ( ( unsigned portCHAR ) 0x80 )\r
+#define serENABLE_INTERRUPTS ( ( unsigned portCHAR ) 0x03 )\r
+#define serNO_PARITY ( ( unsigned portCHAR ) 0x00 )\r
+#define ser1_STOP_BIT ( ( unsigned portCHAR ) 0x00 )\r
+#define ser8_BIT_CHARS ( ( unsigned portCHAR ) 0x03 )\r
+#define serFIFO_ON ( ( unsigned portCHAR ) 0x01 )\r
+#define serCLEAR_FIFO ( ( unsigned portCHAR ) 0x06 )\r
+#define serWANTED_CLOCK_SCALING ( ( unsigned portLONG ) 16 )\r
+\r
+/* Constants to setup and access the VIC. */\r
+#define serUART0_VIC_CHANNEL ( ( unsigned portLONG ) 0x0006 )\r
+#define serUART0_VIC_CHANNEL_BIT ( ( unsigned portLONG ) 0x0040 )\r
+#define serUART0_VIC_ENABLE ( ( unsigned portLONG ) 0x0020 )\r
+#define serCLEAR_VIC_INTERRUPT ( ( unsigned portLONG ) 0 )\r
+\r
+#define serINVALID_QUEUE ( ( xQueueHandle ) 0 )\r
+#define serHANDLE ( ( xComPortHandle ) 1 )\r
+#define serNO_BLOCK ( ( portTickType ) 0 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Queues used to hold received characters, and characters waiting to be\r
+transmitted. */\r
+static xQueueHandle xRxedChars; \r
+static xQueueHandle xCharsForTx; \r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Communication flag between the interrupt service routine and serial API. */\r
+static volatile portLONG *plTHREEmpty;\r
+\r
+/* \r
+ * The queues are created in serialISR.c as they are used from the ISR.\r
+ * Obtain references to the queues and THRE Empty flag. \r
+ */\r
+extern void vSerialISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxRxedChars, xQueueHandle *pxCharsForTx, portLONG volatile **pplTHREEmptyFlag );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )\r
+{\r
+unsigned portLONG ulDivisor, ulWantedClock;\r
+xComPortHandle xReturn = serHANDLE;\r
+extern void ( vUART_ISR )( void );\r
+\r
+ /* The queues are used in the serial ISR routine, so are created from\r
+ serialISR.c (which is always compiled to ARM mode. */\r
+ vSerialISRCreateQueues( uxQueueLength, &xRxedChars, &xCharsForTx, &plTHREEmpty );\r
+\r
+ if( \r
+ ( xRxedChars != serINVALID_QUEUE ) && \r
+ ( xCharsForTx != serINVALID_QUEUE ) && \r
+ ( ulWantedBaud != ( unsigned portLONG ) 0 ) \r
+ )\r
+ {\r
+ portENTER_CRITICAL();\r
+ {\r
+ /* Setup the baud rate: Calculate the divisor value. */\r
+ ulWantedClock = ulWantedBaud * serWANTED_CLOCK_SCALING;\r
+ ulDivisor = configCPU_CLOCK_HZ / ulWantedClock;\r
+\r
+ /* Set the DLAB bit so we can access the divisor. */\r
+ UART0_LCR |= serDLAB;\r
+\r
+ /* Setup the divisor. */\r
+ UART0_DLL = ( unsigned portCHAR ) ( ulDivisor & ( unsigned portLONG ) 0xff );\r
+ ulDivisor >>= 8;\r
+ UART0_DLM = ( unsigned portCHAR ) ( ulDivisor & ( unsigned portLONG ) 0xff );\r
+\r
+ /* Turn on the FIFO's and clear the buffers. */\r
+ UART0_FCR = ( serFIFO_ON | serCLEAR_FIFO );\r
+\r
+ /* Setup transmission format. */\r
+ UART0_LCR = serNO_PARITY | ser1_STOP_BIT | ser8_BIT_CHARS;\r
+\r
+ /* Setup the VIC for the UART. */\r
+ VICIntSelect &= ~( serUART0_VIC_CHANNEL_BIT );\r
+ VICIntEnable |= serUART0_VIC_CHANNEL_BIT;\r
+ VICVectAddr1 = ( portLONG ) vUART_ISR;\r
+ VICVectCntl1 = serUART0_VIC_CHANNEL | serUART0_VIC_ENABLE;\r
+\r
+ /* Enable UART0 interrupts. */\r
+ UART0_IER |= serENABLE_INTERRUPTS;\r
+ }\r
+ portEXIT_CRITICAL();\r
+ }\r
+ else\r
+ {\r
+ xReturn = ( xComPortHandle ) 0;\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )\r
+{\r
+ /* The port handle is not required as this driver only supports UART0. */\r
+ ( void ) pxPort;\r
+\r
+ /* Get the next character from the buffer. Return false if no characters\r
+ are available, or arrive before xBlockTime expires. */\r
+ if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )\r
+ {\r
+ return pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ return pdFALSE;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength )\r
+{\r
+signed portCHAR *pxNext;\r
+\r
+ /* NOTE: This implementation does not handle the queue being full as no\r
+ block time is used! */\r
+\r
+ /* The port handle is not required as this driver only supports UART0. */\r
+ ( void ) pxPort;\r
+ ( void ) usStringLength;\r
+\r
+ /* Send each character in the string, one at a time. */\r
+ pxNext = ( signed portCHAR * ) pcString;\r
+ while( *pxNext )\r
+ {\r
+ xSerialPutChar( pxPort, *pxNext, serNO_BLOCK );\r
+ pxNext++;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )\r
+{\r
+signed portBASE_TYPE xReturn;\r
+\r
+ /* This demo driver only supports one port so the parameter is not used. */\r
+ ( void ) pxPort;\r
+\r
+ portENTER_CRITICAL();\r
+ {\r
+ /* Is there space to write directly to the UART? */\r
+ if( *plTHREEmpty == ( portLONG ) pdTRUE )\r
+ {\r
+ /* We wrote the character directly to the UART, so was \r
+ successful. */\r
+ *plTHREEmpty = pdFALSE;\r
+ UART0_THR = cOutChar;\r
+ xReturn = pdPASS;\r
+ }\r
+ else \r
+ {\r
+ /* We cannot write directly to the UART, so queue the character.\r
+ Block for a maximum of xBlockTime if there is no space in the\r
+ queue. */\r
+ xReturn = xQueueSend( xCharsForTx, &cOutChar, xBlockTime );\r
+\r
+ /* Depending on queue sizing and task prioritisation: While we \r
+ were blocked waiting to post interrupts were not disabled. It is \r
+ possible that the serial ISR has emptied the Tx queue, in which\r
+ case we need to start the Tx off again. */\r
+ if( ( *plTHREEmpty == ( portLONG ) pdTRUE ) && ( xReturn == pdPASS ) )\r
+ {\r
+ xQueueReceive( xCharsForTx, &cOutChar, serNO_BLOCK );\r
+ *plTHREEmpty = pdFALSE;\r
+ UART0_THR = cOutChar;\r
+ }\r
+ }\r
+ }\r
+ portEXIT_CRITICAL();\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSerialClose( xComPortHandle xPort )\r
+{\r
+ /* Not supported as not required by the demo application. */\r
+ ( void ) xPort;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+\r
+\r
+\r
+ \r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+\r
+/* \r
+ BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0. \r
+\r
+ This file contains all the serial port components that must be compiled\r
+ to ARM mode. The components that can be compiled to either ARM or THUMB\r
+ mode are contained in serial.c.\r
+\r
+*/\r
+\r
+/* Standard includes. */\r
+#include <stdlib.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "queue.h"\r
+#include "task.h"\r
+\r
+/* Demo application includes. */\r
+#include "serial.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Constant to access the VIC. */\r
+#define serCLEAR_VIC_INTERRUPT ( ( unsigned portLONG ) 0 )\r
+\r
+/* Constants to determine the ISR source. */\r
+#define serSOURCE_THRE ( ( unsigned portCHAR ) 0x02 )\r
+#define serSOURCE_RX_TIMEOUT ( ( unsigned portCHAR ) 0x0c )\r
+#define serSOURCE_ERROR ( ( unsigned portCHAR ) 0x06 )\r
+#define serSOURCE_RX ( ( unsigned portCHAR ) 0x04 )\r
+#define serINTERRUPT_SOURCE_MASK ( ( unsigned portCHAR ) 0x0f )\r
+\r
+/* Queues used to hold received characters, and characters waiting to be\r
+transmitted. */\r
+static xQueueHandle xRxedChars; \r
+static xQueueHandle xCharsForTx; \r
+static volatile portLONG lTHREEmpty;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* \r
+ * The queues are created in serialISR.c as they are used from the ISR.\r
+ * Obtain references to the queues and THRE Empty flag. \r
+ */\r
+void vSerialISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxRxedChars, xQueueHandle *pxCharsForTx, portLONG volatile **pplTHREEmptyFlag );\r
+\r
+/* UART0 interrupt service routine. This can cause a context switch so MUST\r
+be declared "naked". */\r
+void vUART_ISR( void ) __attribute__ ((naked));\r
+\r
+/*-----------------------------------------------------------*/\r
+void vSerialISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxRxedChars, \r
+ xQueueHandle *pxCharsForTx, portLONG volatile **pplTHREEmptyFlag )\r
+{\r
+ /* Create the queues used to hold Rx and Tx characters. */\r
+ xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );\r
+ xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );\r
+\r
+ /* Pass back a reference to the queues so the serial API file can \r
+ post/receive characters. */\r
+ *pxRxedChars = xRxedChars;\r
+ *pxCharsForTx = xCharsForTx;\r
+\r
+ /* Initialise the THRE empty flag - and pass back a reference. */\r
+ lTHREEmpty = ( portLONG ) pdTRUE;\r
+ *pplTHREEmptyFlag = &lTHREEmpty;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vUART_ISR( void )\r
+{\r
+ /* This ISR can cause a context switch, so the first statement must be a\r
+ call to the portENTER_SWITCHING_ISR() macro. This must be BEFORE any\r
+ variable declarations. */\r
+ portENTER_SWITCHING_ISR();\r
+\r
+ /* Now we can declare the local variables. */\r
+ signed portCHAR cChar;\r
+ portBASE_TYPE xTaskWokenByTx = pdFALSE, xTaskWokenByRx = pdFALSE;\r
+\r
+ /* What caused the interrupt? */\r
+ switch( UART0_IIR & serINTERRUPT_SOURCE_MASK )\r
+ {\r
+ case serSOURCE_ERROR : /* Not handling this, but clear the interrupt. */\r
+ cChar = UART0_LSR;\r
+ break;\r
+\r
+ case serSOURCE_THRE : /* The THRE is empty. If there is another\r
+ character in the Tx queue, send it now. */\r
+ if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWokenByTx ) == pdTRUE )\r
+ {\r
+ UART0_THR = cChar;\r
+ }\r
+ else\r
+ {\r
+ /* There are no further characters \r
+ queued to send so we can indicate \r
+ that the THRE is available. */\r
+ lTHREEmpty = pdTRUE;\r
+ }\r
+ break;\r
+\r
+ case serSOURCE_RX_TIMEOUT :\r
+ case serSOURCE_RX : /* A character was received. Place it in \r
+ the queue of received characters. */\r
+ cChar = UART0_RBR;\r
+ if( xQueueSendFromISR( xRxedChars, &cChar, ( portBASE_TYPE ) pdFALSE ) ) \r
+ {\r
+ xTaskWokenByRx = pdTRUE;\r
+ }\r
+ break;\r
+\r
+ default : /* There is nothing to do, leave the ISR. */\r
+ break;\r
+ }\r
+\r
+ /* Clear the ISR in the VIC. */\r
+ VICVectAddr = serCLEAR_VIC_INTERRUPT;\r
+\r
+ /* Exit the ISR. If a task was woken by either a character being received\r
+ or transmitted then a context switch will occur. */\r
+ portEXIT_SWITCHING_ISR( ( xTaskWokenByTx || xTaskWokenByRx ) );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+\r
+\r
+\r
+ \r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/* Hardware specifics. */\r
+#include <iolpc2129.h>\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 60000000 ) /* =12.0MHz xtal multiplied by 5 using the PLL. */\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 100 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) 14200 )\r
+#define configMAX_TASK_NAME_LEN ( 16 )\r
+#define configUSE_TRACE_FACILITY 0\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 1\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 0\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple parallel port IO routines for the LED's.\r
+ *-----------------------------------------------------------*/\r
+\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+\r
+/* Demo application includes. */\r
+#include "partest.h"\r
+\r
+/* Board specific defines. */\r
+#define partstFIRST_IO ( ( unsigned portLONG ) 0x10000 )\r
+#define partstNUM_LEDS ( 8 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestInitialise( void )\r
+{ \r
+ /* The ports are setup within prvInitialiseHardware(), called by main(). */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )\r
+{\r
+unsigned portLONG ulLED = partstFIRST_IO;\r
+\r
+ if( uxLED < partstNUM_LEDS )\r
+ {\r
+ /* Rotate to the wanted bit of port 1. Only P16 to P23 have an LED\r
+ attached. */\r
+ ulLED <<= ( unsigned portLONG ) uxLED;\r
+\r
+ /* Set or clear the output. */\r
+ if( xValue )\r
+ {\r
+ IO1SET = ulLED;\r
+ }\r
+ else\r
+ {\r
+ IO1CLR = ulLED; \r
+ }\r
+ } \r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+unsigned portLONG ulLED = partstFIRST_IO, ulCurrentState;\r
+\r
+ if( uxLED < partstNUM_LEDS )\r
+ {\r
+ /* Rotate to the wanted bit of port 1. Only P10 to P13 have an LED\r
+ attached. */\r
+ ulLED <<= ( unsigned portLONG ) uxLED;\r
+\r
+ /* If this bit is already set, clear it, and visa versa. */\r
+ ulCurrentState = IO1PIN;\r
+ if( ulCurrentState & ulLED )\r
+ {\r
+ IO1CLR = ulLED;\r
+ }\r
+ else\r
+ {\r
+ IO1SET = ulLED; \r
+ }\r
+ } \r
+}\r
+\r
+\r
--- /dev/null
+;-----------------------------------------------------------------------------\r
+; This file contains the startup code used by the ICCARM C compiler.\r
+;\r
+; The modules in this file are included in the libraries, and may be replaced\r
+; by any user-defined modules that define the PUBLIC symbol _program_start or\r
+; a user defined start symbol.\r
+; To override the cstartup defined in the library, simply add your modified\r
+; version to the workbench project.\r
+;\r
+; All code in the modules (except ?RESET) will be placed in the ICODE segment.\r
+;\r
+; $Revision: 1.56 $\r
+;\r
+;-----------------------------------------------------------------------------\r
+ \r
+;\r
+; Naming covention of labels in this file:\r
+;\r
+; ?xxx - External labels only accessed from assembler.\r
+; __xxx - External labels accessed from or defined in C.\r
+; xxx - Labels local to one module (note: this file contains\r
+; several modules).\r
+; main - The starting point of the user program.\r
+;\r
+\r
+;---------------------------------------------------------------\r
+; Macros and definitions for the whole file\r
+;---------------------------------------------------------------\r
+\r
+; Mode, correspords to bits 0-5 in CPSR\r
+MODE_BITS DEFINE 0x1F ; Bit mask for mode bits in CPSR\r
+USR_MODE DEFINE 0x10 ; User mode\r
+FIQ_MODE DEFINE 0x11 ; Fast Interrupt Request mode\r
+IRQ_MODE DEFINE 0x12 ; Interrupt Request mode\r
+SVC_MODE DEFINE 0x13 ; Supervisor mode\r
+ABT_MODE DEFINE 0x17 ; Abort mode\r
+UND_MODE DEFINE 0x1B ; Undefined Instruction mode\r
+SYS_MODE DEFINE 0x1F ; System mode\r
+ \r
+I_Bit DEFINE 0x80 ; IRQ Disable Bit\r
+F_Bit DEFINE 0x40 ; FIQ Disable Bit\r
+\r
+;---------------------------------------------------------------\r
+; ?RESET\r
+; Reset Vector.\r
+; Normally, segment INTVEC is linked at address 0.\r
+; For debugging purposes, INTVEC may be placed at other\r
+; addresses.\r
+; A debugger that honors the entry point will start the\r
+; program in a normal way even if INTVEC is not at address 0.\r
+;---------------------------------------------------------------\r
+\r
+ MODULE ?RESET\r
+ COMMON INTVEC:CODE:NOROOT(2)\r
+ PUBLIC __program_start\r
+ EXTERN ?cstartup\r
+ EXTERN undef_handler, swi_handler, prefetch_handler\r
+ EXTERN data_handler, irq_handler, fiq_handler\r
+ EXTERN vPortYieldProcessor\r
+\r
+ CODE32 ; Always ARM mode after reset \r
+\r
+__program_start\r
+\r
+ org 0x00\r
+\r
+ B InitReset ; 0x00 Reset handler\r
+ undefvec:\r
+ B undefvec ; 0x04 Undefined Instruction\r
+ swivec:\r
+ B vPortYieldProcessor ; 0x08 Software Interrupt\r
+ pabtvec:\r
+ B pabtvec ; 0x0C Prefetch Abort\r
+ dabtvec:\r
+ B dabtvec ; 0x10 Data Abort\r
+ rsvdvec:\r
+ B rsvdvec ; 0x14 reserved\r
+ irqvec:\r
+ LDR PC, [PC, #-0xFF0] ; Jump directly to the address given by the AIC\r
+ \r
+ fiqvec: ; 0x1c FIQ\r
+\r
+\r
+;---------------------------------------------------------------\r
+; ?CSTARTUP\r
+;---------------------------------------------------------------\r
+\r
+ RSEG IRQ_STACK:DATA(2)\r
+ RSEG SVC_STACK:DATA:NOROOT(2)\r
+ RSEG CSTACK:DATA(2)\r
+ RSEG ICODE:CODE:NOROOT(2)\r
+ EXTERN ?main\r
+\r
+; Execution starts here.\r
+; After a reset, the mode is ARM, Supervisor, interrupts disabled.\r
+\r
+\r
+ CODE32\r
+\r
+InitReset\r
+\r
+; Add initialization needed before setup of stackpointers here\r
+\r
+\r
+; Initialize the stack pointers.\r
+; The pattern below can be used for any of the exception stacks:\r
+; FIQ, IRQ, SVC, ABT, UND, SYS.\r
+; The USR mode uses the same stack as SYS.\r
+; The stack segments must be defined in the linker command file,\r
+; and be declared above.\r
+ mrs r0,cpsr ; Original PSR value\r
+ bic r0,r0,#MODE_BITS ; Clear the mode bits\r
+ orr r0,r0,#IRQ_MODE ; Set IRQ mode bits\r
+ msr cpsr_c,r0 ; Change the mode\r
+ ldr sp,=SFE(IRQ_STACK) & 0xFFFFFFF8 ; End of IRQ_STACK\r
+\r
+ bic r0,r0,#MODE_BITS ; Clear the mode bits\r
+ orr r0,r0,#SYS_MODE ; Set System mode bits\r
+ msr cpsr_c,r0 ; Change the mode\r
+ ldr sp,=SFE(CSTACK) & 0xFFFFFFF8 ; End of CSTACK\r
+\r
+ bic r0,r0,#MODE_BITS ; Clear the mode bits\r
+ orr r0,r0,#SVC_MODE ; Set System mode bits\r
+ msr cpsr_c,r0 ; Change the mode\r
+ ldr sp,=SFE(SVC_STACK) & 0xFFFFFFF8 ; End of CSTACK\r
+\r
+; Must start in supervisor mode.\r
+ MSR CPSR_c, #SVC_MODE|I_Bit|F_Bit\r
+\r
+\r
+; Add more initialization here\r
+\r
+\r
+; Continue to ?main for more IAR specific system startup\r
+\r
+ ldr r0,=?main\r
+ bx r0\r
+\r
+\r
+\r
+\r
+;---------------------------------------------------------------\r
+; ?EXEPTION_VECTOR\r
+; This module is only linked if needed for closing files.\r
+;---------------------------------------------------------------\r
+ PUBLIC AT91F_Default_FIQ_handler\r
+ PUBLIC AT91F_Default_IRQ_handler\r
+ PUBLIC AT91F_Spurious_handler\r
+\r
+ CODE32 ; Always ARM mode after exeption \r
+\r
+AT91F_Default_FIQ_handler\r
+ b AT91F_Default_FIQ_handler\r
+\r
+AT91F_Default_IRQ_handler\r
+ b AT91F_Default_IRQ_handler\r
+\r
+AT91F_Spurious_handler\r
+ b AT91F_Spurious_handler\r
+\r
+ ENDMOD\r
+\r
+ END\r
+\r
+\r
+\r
+\r
+ ENDMOD\r
+ END\r
+\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+\r
+/* \r
+ NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.\r
+ The processor MUST be in supervisor mode when vTaskStartScheduler is \r
+ called. The demo applications included in the FreeRTOS.org download switch\r
+ to supervisor mode prior to main being called. If you are not using one of\r
+ these demo application projects then ensure Supervisor mode is used.\r
+*/\r
+\r
+\r
+/*\r
+ * Creates all the demo application tasks, then starts the scheduler. The WEB\r
+ * documentation provides more details of the demo application tasks.\r
+ *\r
+ * Main.c also creates a task called "Check". This only executes every three\r
+ * seconds but has the highest priority so is guaranteed to get processor time.\r
+ * Its main function is to check that all the other tasks are still operational.\r
+ * Each task (other than the "flash" tasks) maintains a unique count that is\r
+ * incremented each time the task successfully completes its function. Should\r
+ * any error occur within such a task the count is permanently halted. The\r
+ * check task inspects the count of each task to ensure it has changed since\r
+ * the last time the check task executed. If all the count variables have\r
+ * changed all the tasks are still executing error free, and the check task\r
+ * toggles the onboard LED. Should any task contain an error at any time\r
+ * the LED toggle rate will change from 3 seconds to 500ms.\r
+ *\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdlib.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo application includes. */\r
+#include "flash.h"\r
+#include "integer.h"\r
+#include "PollQ.h"\r
+#include "BlockQ.h"\r
+#include "semtest.h"\r
+#include "dynamic.h"\r
+#include "partest.h"\r
+#include "comtest2.h"\r
+\r
+/* Priorities for the demo application tasks. */\r
+#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 )\r
+#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+\r
+/* Constants required by the 'Check' task. */\r
+#define mainNO_ERROR_FLASH_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS )\r
+#define mainERROR_FLASH_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS )\r
+#define mainCHECK_TASK_LED ( 7 )\r
+\r
+/* Constants for the ComTest tasks. */\r
+#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 115200 )\r
+#define mainCOM_TEST_LED ( 4 )\r
+#define mainTX_ENABLE ( ( unsigned portLONG ) 0x0001 )\r
+#define mainRX_ENABLE ( ( unsigned portLONG ) 0x0004 )\r
+\r
+/* Constants to setup the PLL. */\r
+#define mainPLL_MUL_4 ( ( unsigned portCHAR ) 0x0003 )\r
+#define mainPLL_DIV_1 ( ( unsigned portCHAR ) 0x0000 )\r
+#define mainPLL_ENABLE ( ( unsigned portCHAR ) 0x0001 )\r
+#define mainPLL_CONNECT ( ( unsigned portCHAR ) 0x0003 )\r
+#define mainPLL_FEED_BYTE1 ( ( unsigned portCHAR ) 0xaa )\r
+#define mainPLL_FEED_BYTE2 ( ( unsigned portCHAR ) 0x55 )\r
+#define mainPLL_LOCK ( ( unsigned portLONG ) 0x0400 )\r
+\r
+/* Constants to setup the MAM. */\r
+#define mainMAM_TIM_3 ( ( unsigned portCHAR ) 0x03 )\r
+#define mainMAM_MODE_FULL ( ( unsigned portCHAR ) 0x02 )\r
+\r
+/* Constants to setup the peripheral bus. */\r
+#define mainBUS_CLK_FULL ( ( unsigned portCHAR ) 0x01 )\r
+\r
+/* And finally, constant to setup the port for the LED's. */\r
+#define mainLED_TO_OUTPUT ( ( unsigned portLONG ) 0xff0000 )\r
+\r
+/*\r
+ * The task that executes at the highest priority and calls\r
+ * prvCheckOtherTasksAreStillRunning(). See the description at the top\r
+ * of the file.\r
+ */\r
+static void vErrorChecks( void *pvParameters );\r
+\r
+/*\r
+ * Configures the processor for use with this demo.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*\r
+ * Checks that all the demo application tasks are still executing without error\r
+ * - as described at the top of the file.\r
+ */\r
+static portLONG prvCheckOtherTasksAreStillRunning( void );\r
+\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Starts all the other tasks, then starts the scheduler.\r
+ */\r
+void main( void )\r
+{\r
+ /* Setup the processor. */\r
+ prvSetupHardware();\r
+\r
+ /* Start all the standard demo application tasks. */\r
+ vStartIntegerMathTasks( tskIDLE_PRIORITY );\r
+ vStartLEDFlashTasks( mainLED_TASK_PRIORITY );\r
+ vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
+ vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
+ vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
+ vStartDynamicPriorityTasks();\r
+ vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED );\r
+ \r
+ /* Start the check task - which is defined in this file. */\r
+ xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
+\r
+ /* Start the scheduler.\r
+ \r
+ NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.\r
+ The processor MUST be in supervisor mode when vTaskStartScheduler is \r
+ called. The demo applications included in the FreeRTOS.org download switch\r
+ to supervisor mode prior to main being called. If you are not using one of\r
+ these demo application projects then ensure Supervisor mode is used here.\r
+ */\r
+ vTaskStartScheduler();\r
+\r
+ /* We should never get here as control is now taken by the scheduler. */\r
+ return;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+ /* Setup the PLL to multiply the XTAL input by 4. */\r
+ PLLCFG = ( mainPLL_MUL_4 | mainPLL_DIV_1 );\r
+\r
+ /* Activate the PLL by turning it on then feeding the correct sequence of\r
+ bytes. */\r
+ PLLCON = mainPLL_ENABLE;\r
+ PLLFEED = mainPLL_FEED_BYTE1;\r
+ PLLFEED = mainPLL_FEED_BYTE2;\r
+\r
+ /* Wait for the PLL to lock... */\r
+ while( !( PLLSTAT & mainPLL_LOCK ) );\r
+\r
+ /* ...before connecting it using the feed sequence again. */\r
+ PLLCON = mainPLL_CONNECT;\r
+ PLLFEED = mainPLL_FEED_BYTE1;\r
+ PLLFEED = mainPLL_FEED_BYTE2;\r
+\r
+ /* Setup and turn on the MAM. Three cycle access is used due to the fast\r
+ PLL used. It is possible faster overall performance could be obtained by\r
+ tuning the MAM and PLL settings. */\r
+ MAMTIM = mainMAM_TIM_3;\r
+ MAMCR = mainMAM_MODE_FULL;\r
+\r
+ /* Setup the peripheral bus to be the same as the PLL output. */\r
+ VPBDIV = mainBUS_CLK_FULL;\r
+ \r
+ /* Configure the RS2332 pins. All other pins remain at their default of 0. */\r
+ PINSEL0 |= mainTX_ENABLE;\r
+ PINSEL0 |= mainRX_ENABLE;\r
+\r
+ /* LED pins need to be output. */\r
+ IO1DIR = mainLED_TO_OUTPUT;\r
+\r
+ /* Setup the peripheral bus to be the same as the PLL output. */\r
+ VPBDIV = mainBUS_CLK_FULL;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vErrorChecks( void *pvParameters )\r
+{\r
+portTickType xDelayPeriod = mainNO_ERROR_FLASH_PERIOD;\r
+\r
+ /* The parameters are not used in this task. */\r
+ ( void ) pvParameters;\r
+\r
+ /* Cycle for ever, delaying then checking all the other tasks are still\r
+ operating without error. If an error is detected then the delay period\r
+ is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so\r
+ the on board LED flash rate will increase. */\r
+\r
+ for( ;; )\r
+ {\r
+ /* Delay until it is time to execute again. */\r
+ vTaskDelay( xDelayPeriod );\r
+ \r
+ /* Check all the standard demo application tasks are executing without\r
+ error. */\r
+ if( prvCheckOtherTasksAreStillRunning() != pdPASS )\r
+ {\r
+ /* An error has been detected in one of the tasks - flash faster. */\r
+ xDelayPeriod = mainERROR_FLASH_PERIOD;\r
+ }\r
+ \r
+ vParTestToggleLED( mainCHECK_TASK_LED );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portLONG prvCheckOtherTasksAreStillRunning( void )\r
+{\r
+portLONG lReturn = ( portLONG ) pdPASS;\r
+\r
+ /* Check all the demo tasks (other than the flash tasks) to ensure\r
+ that they are all still running, and that none of them have detected\r
+ an error. */\r
+\r
+ if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ lReturn = ( portLONG ) pdFAIL;\r
+ }\r
+\r
+ if( xArePollingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ lReturn = ( portLONG ) pdFAIL;\r
+ }\r
+\r
+ if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ lReturn = ( portLONG ) pdFAIL;\r
+ }\r
+\r
+ if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ lReturn = ( portLONG ) pdFAIL;\r
+ }\r
+\r
+ if( xAreComTestTasksStillRunning() != pdTRUE )\r
+ {\r
+ lReturn = ( portLONG ) pdFAIL;\r
+ }\r
+\r
+ if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )\r
+ {\r
+ lReturn = ( portLONG ) pdFAIL;\r
+ }\r
+\r
+ return lReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
--- /dev/null
+//*************************************************************************\r
+// XLINK command file template for EWARM/ICCARM\r
+//\r
+// Usage: xlink -f lnkarm <your_object_file(s)>\r
+// -s <program start label> <C/C++ runtime library>\r
+//\r
+// $Revision: 1.1 $\r
+//*************************************************************************\r
+\r
+//*************************************************************************\r
+//\r
+// -------------\r
+// Code segments - may be placed anywhere in memory.\r
+// -------------\r
+//\r
+// INTVEC -- Exception vector table.\r
+// SWITAB -- Software interrupt vector table.\r
+// ICODE -- Startup (cstartup) and exception code.\r
+// DIFUNCT -- Dynamic initialization vectors used by C++.\r
+// CODE -- Compiler generated code.\r
+// CODE_I -- Compiler generated code declared __ramfunc (executes in RAM)\r
+// CODE_ID -- Initializer for CODE_I (ROM).\r
+//\r
+// -------------\r
+// Data segments - may be placed anywhere in memory.\r
+// -------------\r
+//\r
+// CSTACK -- The stack used by C/C++ programs (system and user mode).\r
+// IRQ_STACK -- The stack used by IRQ service routines.\r
+// SVC_STACK -- The stack used in supervisor mode\r
+// (Define other exception stacks as needed for\r
+// FIQ, ABT, UND).\r
+// HEAP -- The heap used by malloc and free in C and new and\r
+// delete in C++.\r
+// INITTAB -- Table containing addresses and sizes of segments that\r
+// need to be initialized at startup (by cstartup).\r
+// CHECKSUM -- The linker places checksum byte(s) in this segment,\r
+// when the -J linker command line option is used.\r
+// DATA_y -- Data objects.\r
+//\r
+// Where _y can be one of:\r
+//\r
+// _AN -- Holds uninitialized located objects, i.e. objects with\r
+// an absolute location given by the @ operator or the\r
+// #pragma location directive. Since these segments\r
+// contain objects which already have a fixed address,\r
+// they should not be mentioned in this linker command\r
+// file.\r
+// _C -- Constants (ROM).\r
+// _I -- Initialized data (RAM).\r
+// _ID -- The original content of _I (copied to _I by cstartup) (ROM).\r
+// _N -- Uninitialized data (RAM).\r
+// _Z -- Zero initialized data (RAM).\r
+//\r
+// Note: Be sure to use end values for the defined address ranges.\r
+// Otherwise, the linker may allocate space outside the\r
+// intended memory range.\r
+//*************************************************************************\r
+\r
+\r
+//************************************************\r
+// Inform the linker about the CPU family used.\r
+//************************************************\r
+\r
+-carm\r
+\r
+//*************************************************************************\r
+// Segment placement - General information\r
+//\r
+// All numbers in the segment placement command lines below are interpreted\r
+// as hexadecimal unless they are immediately preceded by a '.', which\r
+// denotes decimal notation. \r
+//\r
+// When specifying the segment placement using the -P instead of the -Z\r
+// option, the linker is free to split each segment into its segment parts\r
+// and randomly place these parts within the given ranges in order to\r
+// achieve a more efficient memory usage. One disadvantage, however, is\r
+// that it is not possible to find the start or end address (using\r
+// the assembler operators .sfb./.sfe.) of a segment which has been split\r
+// and reformed. \r
+//\r
+// When generating an output file which is to be used for programming\r
+// external ROM/Flash devices, the -M linker option is very useful \r
+// (see xlink.pdf for details).\r
+//*************************************************************************\r
+\r
+\r
+//*************************************************************************\r
+// Read-only segments mapped to ROM.\r
+//*************************************************************************\r
+\r
+-DROMSTART=00000000\r
+-DROMEND=00001ffff\r
+\r
+//************************************************\r
+// Address range for reset and exception\r
+// vectors (INTVEC).\r
+// The vector area is 32 bytes, \r
+// an additional 32 bytes is allocated for the\r
+// constant table used by ldr PC in cstartup.s79.\r
+//************************************************\r
+\r
+-Z(CODE)INTVEC=00000000-0000003f\r
+\r
+//************************************************\r
+// Startup code and exception routines (ICODE).\r
+//************************************************\r
+\r
+-Z(CODE)ICODE,DIFUNCT=ROMSTART-ROMEND\r
+-Z(CODE)SWITAB=ROMSTART-ROMEND\r
+\r
+//************************************************\r
+// Code segments may be placed anywhere.\r
+//************************************************\r
+\r
+-Z(CODE)CODE=ROMSTART-ROMEND\r
+\r
+//************************************************\r
+// Original ROM location for __ramfunc code copied\r
+// to and executed from RAM.\r
+//************************************************\r
+\r
+-Z(CONST)CODE_ID=ROMSTART-ROMEND\r
+\r
+//************************************************\r
+// Various constants and initializers.\r
+//************************************************\r
+\r
+-Z(CONST)INITTAB,DATA_ID,DATA_C=ROMSTART-ROMEND\r
+-Z(CONST)CHECKSUM=ROMSTART-ROMEND\r
+\r
+//*************************************************************************\r
+// Read/write segments mapped to RAM.\r
+//*************************************************************************\r
+\r
+-DRAMSTART=40000000\r
+-DRAMEND=40003fff\r
+\r
+//************************************************\r
+// Data segments.\r
+//************************************************\r
+\r
+-Z(DATA)DATA_I,DATA_Z,DATA_N=RAMSTART-RAMEND\r
+\r
+//************************************************\r
+// __ramfunc code copied to and executed from RAM.\r
+//************************************************\r
+\r
+-Z(DATA)CODE_I=RAMSTART-RAMEND\r
+\r
+//************************************************\r
+// ICCARM produces code for __ramfunc functions in\r
+// CODE_I segments. The -Q XLINK command line\r
+// option redirects XLINK to emit the code in the\r
+// CODE_ID segment instead, but to keep symbol and\r
+// debug information associated with the CODE_I\r
+// segment, where the code will execute.\r
+//************************************************\r
+\r
+-QCODE_I=CODE_ID\r
+\r
+//*************************************************************************\r
+// Stack and heap segments.\r
+//*************************************************************************\r
+\r
+-D_CSTACK_SIZE=200\r
+-D_SVC_STACK_SIZE=190\r
+-D_IRQ_STACK_SIZE=190\r
+-D_HEAP_SIZE=4\r
+\r
+-Z(DATA)CSTACK+_CSTACK_SIZE=RAMSTART-RAMEND\r
+-Z(DATA)SVC_STACK+_SVC_STACK_SIZE=RAMSTART-RAMEND\r
+-Z(DATA)IRQ_STACK+_IRQ_STACK_SIZE,HEAP+_HEAP_SIZE=RAMSTART-RAMEND\r
+\r
+//*************************************************************************\r
+// ELF/DWARF support.\r
+//\r
+// Uncomment the line "-Felf" below to generate ELF/DWARF output.\r
+// Available format specifiers are:\r
+//\r
+// "-yn": Suppress DWARF debug output\r
+// "-yp": Multiple ELF program sections\r
+// "-yas": Format suitable for debuggers from ARM Ltd (also sets -p flag)\r
+//\r
+// "-Felf" and the format specifiers can also be supplied directly as\r
+// command line options, or selected from the Xlink Output tab in the\r
+// IAR Embedded Workbench.\r
+//*************************************************************************\r
+\r
+// -Felf\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+ <fileVersion>1</fileVersion>\r
+ <configuration>\r
+ <name>Flash Debug</name>\r
+ <toolchain>\r
+ <name>ARM</name>\r
+ </toolchain>\r
+ <debug>1</debug>\r
+ <settings>\r
+ <name>C-SPY</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>13</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CInput</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CEndian</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCVariant</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>MemOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MemFile</name>\r
+ <state>$TOOLKIT_DIR$\CONFIG\iolpc2129.ddf</state>\r
+ </option>\r
+ <option>\r
+ <name>RunToEnable</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RunToName</name>\r
+ <state>main</state>\r
+ </option>\r
+ <option>\r
+ <name>CExtraOptionsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CFpuProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDDFArgumentProducer</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadSuppressDownload</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadVerifyAll</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCProductVersion</name>\r
+ <state>4.10B</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDynDriverList</name>\r
+ <state>JLINK_ID</state>\r
+ </option>\r
+ <option>\r
+ <name>OCLastSavedByProductVersion</name>\r
+ <state>4.30A</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadAttachToProgram</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>FlashLoaders</name>\r
+ <state>,,,,(default),</state>\r
+ </option>\r
+ <option>\r
+ <name>UseFlashLoader</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ARMSIM_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCSimDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ANGEL_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CCAngelHeartbeat</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommunication</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommBaud</name>\r
+ <version>0</version>\r
+ <state>3</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ANGELTCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>DoAngelLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AngelLogFile</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>IARROM_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CRomLogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomLogFileEditB</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomCommunication</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomCommBaud</name>\r
+ <version>0</version>\r
+ <state>7</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>JLINK_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>2</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>JLinkSpeed</name>\r
+ <state>30</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkHWReset</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkTRSTReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkLogFile</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkHWResetDelay</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkSpeedRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>JLinkInitialSpeed</name>\r
+ <state>32</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDoJlinkMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCScanChainNonARMDevices</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkIRLength</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkCommRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkTCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>MACRAIGOR_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>jtag</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuSpeed</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>TCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>DoEmuMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuMultiTarget</name>\r
+ <state>0@ARM7TDMI</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuHWReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CEmuCommBaud</name>\r
+ <version>0</version>\r
+ <state>4</state>\r
+ </option>\r
+ <option>\r
+ <name>CEmuCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>jtago</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>UnusedAddr</name>\r
+ <state>0x00800000</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMacraigorHWResetDelay</name>\r
+ <state></state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>RDI_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CRDIDriverDll</name>\r
+ <state>Browse to your RDI driver</state>\r
+ </option>\r
+ <option>\r
+ <name>CRDILogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRDILogFileEdit</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDIHWReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchUndef</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchSWI</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchData</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchPrefetch</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchIRQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchFIQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDIUseETM</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>THIRDPARTY_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CThirdPartyDriverDll</name>\r
+ <state>Browse to your third-party driver</state>\r
+ </option>\r
+ <option>\r
+ <name>CThirdPartyLogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CThirdPartyLogFileEditB</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <debuggerPlugins>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Profiling\Profiling.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Trace\Trace.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Orti\Orti.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ </debuggerPlugins>\r
+ </configuration>\r
+ <configuration>\r
+ <name>Flash Bin</name>\r
+ <toolchain>\r
+ <name>ARM</name>\r
+ </toolchain>\r
+ <debug>0</debug>\r
+ <settings>\r
+ <name>C-SPY</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>13</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>CInput</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CEndian</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCVariant</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>MemOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MemFile</name>\r
+ <state>$TOOLKIT_DIR$\CONFIG\iolpc2129.ddf</state>\r
+ </option>\r
+ <option>\r
+ <name>RunToEnable</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RunToName</name>\r
+ <state>main</state>\r
+ </option>\r
+ <option>\r
+ <name>CExtraOptionsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CFpuProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDDFArgumentProducer</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadSuppressDownload</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadVerifyAll</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCProductVersion</name>\r
+ <state>4.10B</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDynDriverList</name>\r
+ <state>JLINK_ID</state>\r
+ </option>\r
+ <option>\r
+ <name>OCLastSavedByProductVersion</name>\r
+ <state>4.30A</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadAttachToProgram</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>FlashLoaders</name>\r
+ <state>,,,,(default),</state>\r
+ </option>\r
+ <option>\r
+ <name>UseFlashLoader</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ARMSIM_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>OCSimDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ANGEL_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>CCAngelHeartbeat</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommunication</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommBaud</name>\r
+ <version>0</version>\r
+ <state>3</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ANGELTCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>DoAngelLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AngelLogFile</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>IARROM_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>CRomLogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomLogFileEditB</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomCommunication</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomCommBaud</name>\r
+ <version>0</version>\r
+ <state>7</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>JLINK_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>2</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>JLinkSpeed</name>\r
+ <state>30</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkHWReset</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkTRSTReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkLogFile</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkHWResetDelay</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkSpeedRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>JLinkInitialSpeed</name>\r
+ <state>32</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDoJlinkMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCScanChainNonARMDevices</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkIRLength</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkCommRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkTCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>MACRAIGOR_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>jtag</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuSpeed</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>TCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>DoEmuMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuMultiTarget</name>\r
+ <state>0@ARM7TDMI</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuHWReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CEmuCommBaud</name>\r
+ <version>0</version>\r
+ <state>4</state>\r
+ </option>\r
+ <option>\r
+ <name>CEmuCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>jtago</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>UnusedAddr</name>\r
+ <state>0x00800000</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMacraigorHWResetDelay</name>\r
+ <state></state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>RDI_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>CRDIDriverDll</name>\r
+ <state>Browse to your RDI driver</state>\r
+ </option>\r
+ <option>\r
+ <name>CRDILogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRDILogFileEdit</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDIHWReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchUndef</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchSWI</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchData</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchPrefetch</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchIRQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchFIQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDIUseETM</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>THIRDPARTY_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>CThirdPartyDriverDll</name>\r
+ <state>Browse to your third-party driver</state>\r
+ </option>\r
+ <option>\r
+ <name>CThirdPartyLogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CThirdPartyLogFileEditB</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <debuggerPlugins>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Profiling\Profiling.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Trace\Trace.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Orti\Orti.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ </debuggerPlugins>\r
+ </configuration>\r
+</project>\r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+ <fileVersion>1</fileVersion>\r
+ <configuration>\r
+ <name>Flash Debug</name>\r
+ <toolchain>\r
+ <name>ARM</name>\r
+ </toolchain>\r
+ <debug>1</debug>\r
+ <settings>\r
+ <name>General</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>9</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>GProcessorMode</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>ExePath</name>\r
+ <state>Flash_Debug\Exe</state>\r
+ </option>\r
+ <option>\r
+ <name>ObjPath</name>\r
+ <state>Flash_Debug\Obj</state>\r
+ </option>\r
+ <option>\r
+ <name>ListPath</name>\r
+ <state>Flash_Debug\List</state>\r
+ </option>\r
+ <option>\r
+ <name>Variant</name>\r
+ <version>3</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GEndianMode</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GInterwork</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GStackAlign</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>Input variant</name>\r
+ <version>1</version>\r
+ <state>3</state>\r
+ </option>\r
+ <option>\r
+ <name>Input description</name>\r
+ <state>No specifier n, no float nor long long, no scan set, no assignment suppressing.</state>\r
+ </option>\r
+ <option>\r
+ <name>Output variant</name>\r
+ <version>0</version>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>Output description</name>\r
+ <state>No specifier a, A, no specifier n, no float nor long long.</state>\r
+ </option>\r
+ <option>\r
+ <name>GOutputBinary</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>FPU</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OGCoreOrChip</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GRuntimeLibSelect</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GRuntimeLibSelectSlave</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RTDescription</name>\r
+ <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\r
+ </option>\r
+ <option>\r
+ <name>RTConfigPath</name>\r
+ <state>$TOOLKIT_DIR$\LIB\dl4tptinl8n.h</state>\r
+ </option>\r
+ <option>\r
+ <name>RTLibraryPath</name>\r
+ <state>$TOOLKIT_DIR$\LIB\dl4tptinl8n.r79</state>\r
+ </option>\r
+ <option>\r
+ <name>OGProductVersion</name>\r
+ <state>4.11A</state>\r
+ </option>\r
+ <option>\r
+ <name>OGLastSavedByProductVersion</name>\r
+ <state>4.30A</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraRules</name>\r
+ <version>0</version>\r
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralEnableMisra</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraVerbose</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OGChipSelectEditMenu</name>\r
+ <state>LPC2129 Philips LPC2129</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ICCARM</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>13</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CCDefines</name>\r
+ <state>LPC2000_IAR</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocComments</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCMnemonics</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCMessages</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListAssFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListAssSource</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCEnableRemarks</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagSuppress</name>\r
+ <state>pe815, pe191, pa082, pe167</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagRemark</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagWarning</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagError</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCObjPrefix</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptSizeSpeed</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptimization</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCAllowList</name>\r
+ <version>1</version>\r
+ <state>0000000</state>\r
+ </option>\r
+ <option>\r
+ <name>CCObjUseModuleName</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCObjModuleName</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCDebugInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IProcessorMode</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IEndianMode</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IStackAlign</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IInterwork</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IExtraOptionsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCLangConformance</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSignedPlainChar</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRequirePrototypes</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMultibyteSupport</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagWarnAreErr</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCompilerRuntimeInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IFpuProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OutputFile</name>\r
+ <state>$FILE_BNAME$.r79</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLangSelect</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLibConfigHeader</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptSizeSpeedSlave</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptimizationSlave</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCodeFunctions</name>\r
+ <state>CODE</state>\r
+ </option>\r
+ <option>\r
+ <name>CCData</name>\r
+ <state>DATA</state>\r
+ </option>\r
+ <option>\r
+ <name>PreInclude</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CompilerMisraRules</name>\r
+ <version>0</version>\r
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>CompilerMisraOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCModuleTypeOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCModuleType</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCModuleTypeCmdlineProducer</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCIncludePath2</name>\r
+ <state>$PROJ_DIR$\..\..\source\portable\iar\LPC2000</state>\r
+ <state>$PROJ_DIR$\..\common\include</state>\r
+ <state>$PROJ_DIR$\..\..\source\include</state>\r
+ <state>$PROJ_DIR$\SrcIAR</state>\r
+ <state>$PROJ_DIR$</state>\r
+ </option>\r
+ <option>\r
+ <name>CCStdIncCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCStdIncludePath</name>\r
+ <state>$TOOLKIT_DIR$\INC\</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>AARM</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>6</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>AObjPrefix</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AEndian</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>ACaseSensitivity</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>MacroChars</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnWhat</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnOne</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnRange1</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnRange2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>ADebug</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AltRegisterNames</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ADefines</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>AList</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AListHeader</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AListing</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>Includes</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacDefs</name>\r
+ <state>0</state>\r
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+ <option>\r
+ <name>MacExps</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>MacExec</name>\r
+ <state>0</state>\r
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+ <option>\r
+ <name>OnlyAssed</name>\r
+ <state>0</state>\r
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+ <option>\r
+ <name>MultiLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>PageLengthCheck</name>\r
+ <state>0</state>\r
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+ <option>\r
+ <name>PageLength</name>\r
+ <state>80</state>\r
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+ <option>\r
+ <name>TabSpacing</name>\r
+ <state>8</state>\r
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+ <option>\r
+ <name>AXRef</name>\r
+ <state>0</state>\r
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+ <option>\r
+ <name>AXRefDefines</name>\r
+ <state>0</state>\r
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+ <option>\r
+ <name>AXRefInternal</name>\r
+ <state>0</state>\r
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+ <option>\r
+ <name>AXRefDual</name>\r
+ <state>0</state>\r
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+ <option>\r
+ <name>AProcessor</name>\r
+ <state>1</state>\r
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+ <option>\r
+ <name>AFpuProcessor</name>\r
+ <state>1</state>\r
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+ <option>\r
+ <name>AOutputFile</name>\r
+ <state>$FILE_BNAME$.r79</state>\r
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+ <option>\r
+ <name>AMultibyteSupport</name>\r
+ <state>0</state>\r
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+ <option>\r
+ <name>AModuleTypeOverride</name>\r
+ <state>0</state>\r
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+ <option>\r
+ <name>AModuleType</name>\r
+ <state>0</state>\r
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+ <option>\r
+ <name>AModuleTypeCmdlineProducer</name>\r
+ <state>0</state>\r
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+ <option>\r
+ <name>ALimitErrorsCheck</name>\r
+ <state>0</state>\r
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+ <option>\r
+ <name>ALimitErrorsEdit</name>\r
+ <state>100</state>\r
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+ <option>\r
+ <name>AIgnoreStdInclude</name>\r
+ <state>0</state>\r
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+ <option>\r
+ <name>AStdIncludes</name>\r
+ <state>$TOOLKIT_DIR$\INC\</state>\r
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+ <option>\r
+ <name>AUserIncludes</name>\r
+ <state>$PROJ_DIR$\srciar\</state>\r
+ <state>$PROJ_DIR$\..\..\include\</state>\r
+ <state>$PROJ_DIR$\..\common\include</state>\r
+ <state>$PROJ_DIR$\..\..\Source\include</state>\r
+ <state>$PROJ_DIR$</state>\r
+ <state>$PROJ_DIR$\..\..\Source\portable\IAR\LPC2000</state>\r
+ </option>\r
+ <option>\r
+ <name>AExtraOptionsCheckV2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AExtraOptionsV2</name>\r
+ <state></state>\r
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+ </settings>\r
+ <settings>\r
+ <name>CUSTOM</name>\r
+ <archiveVersion>3</archiveVersion>\r
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+ <extensions></extensions>\r
+ <cmdline></cmdline>\r
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+ </settings>\r
+ <settings>\r
+ <name>BICOMP</name>\r
+ <archiveVersion>0</archiveVersion>\r
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+ </settings>\r
+ <settings>\r
+ <name>BUILDACTION</name>\r
+ <archiveVersion>1</archiveVersion>\r
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+ <prebuild></prebuild>\r
+ <postbuild></postbuild>\r
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+ </settings>\r
+ <settings>\r
+ <name>XLINK</name>\r
+ <archiveVersion>2</archiveVersion>\r
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+ <version>17</version>\r
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+ <option>\r
+ <name>XOutOverride</name>\r
+ <state>0</state>\r
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+ <name>OutputFile</name>\r
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+ <option>\r
+ <name>OutputFormat</name>\r
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+ <name>FormatVariant</name>\r
+ <version>6</version>\r
+ <state>15</state>\r
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+ <option>\r
+ <name>SecondaryOutputFile</name>\r
+ <state>(None for the selected format)</state>\r
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+ <name>XDefines</name>\r
+ <state></state>\r
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+ <option>\r
+ <name>AlwaysOutput</name>\r
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+ <option>\r
+ <name>ModuleStatus</name>\r
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+ <state></state>\r
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+ <version>9</version>\r
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+ <debug>0</debug>\r
+ <option>\r
+ <name>GProcessorMode</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>ExePath</name>\r
+ <state>Flash Bin\Exe</state>\r
+ </option>\r
+ <option>\r
+ <name>ObjPath</name>\r
+ <state>Flash Bin\Obj</state>\r
+ </option>\r
+ <option>\r
+ <name>ListPath</name>\r
+ <state>Flash Bin\List</state>\r
+ </option>\r
+ <option>\r
+ <name>Variant</name>\r
+ <version>3</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GEndianMode</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GInterwork</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GStackAlign</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>Input variant</name>\r
+ <version>1</version>\r
+ <state>3</state>\r
+ </option>\r
+ <option>\r
+ <name>Input description</name>\r
+ <state>No specifier n, no float nor long long, no scan set, no assignment suppressing.</state>\r
+ </option>\r
+ <option>\r
+ <name>Output variant</name>\r
+ <version>0</version>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>Output description</name>\r
+ <state>No specifier a, A, no specifier n, no float nor long long.</state>\r
+ </option>\r
+ <option>\r
+ <name>GOutputBinary</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>FPU</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OGCoreOrChip</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GRuntimeLibSelect</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GRuntimeLibSelectSlave</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RTDescription</name>\r
+ <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\r
+ </option>\r
+ <option>\r
+ <name>RTConfigPath</name>\r
+ <state>$TOOLKIT_DIR$\LIB\dl4tptinl8n.h</state>\r
+ </option>\r
+ <option>\r
+ <name>RTLibraryPath</name>\r
+ <state>$TOOLKIT_DIR$\LIB\dl4tptinl8n.r79</state>\r
+ </option>\r
+ <option>\r
+ <name>OGProductVersion</name>\r
+ <state>4.11A</state>\r
+ </option>\r
+ <option>\r
+ <name>OGLastSavedByProductVersion</name>\r
+ <state>4.30A</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraRules</name>\r
+ <version>0</version>\r
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralEnableMisra</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraVerbose</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OGChipSelectEditMenu</name>\r
+ <state>LPC2129 Philips LPC2129</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ICCARM</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>13</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>CCDefines</name>\r
+ <state>LPC2000_IAR</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocComments</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCMnemonics</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCMessages</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListAssFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListAssSource</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCEnableRemarks</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagSuppress</name>\r
+ <state>pe815, pe191, pa082, pe167</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagRemark</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagWarning</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagError</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCObjPrefix</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptSizeSpeed</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptimization</name>\r
+ <version>0</version>\r
+ <state>3</state>\r
+ </option>\r
+ <option>\r
+ <name>CCAllowList</name>\r
+ <version>1</version>\r
+ <state>1111101</state>\r
+ </option>\r
+ <option>\r
+ <name>CCObjUseModuleName</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCObjModuleName</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCDebugInfo</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IProcessorMode</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IEndianMode</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IStackAlign</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IInterwork</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IExtraOptionsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCLangConformance</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSignedPlainChar</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRequirePrototypes</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMultibyteSupport</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagWarnAreErr</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCompilerRuntimeInfo</name>\r
+ <state>1</state>\r
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+ <option>\r
+ <name>IFpuProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OutputFile</name>\r
+ <state>$FILE_BNAME$.r79</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLangSelect</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLibConfigHeader</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptSizeSpeedSlave</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptimizationSlave</name>\r
+ <version>0</version>\r
+ <state>3</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCodeFunctions</name>\r
+ <state>CODE</state>\r
+ </option>\r
+ <option>\r
+ <name>CCData</name>\r
+ <state>DATA</state>\r
+ </option>\r
+ <option>\r
+ <name>PreInclude</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CompilerMisraRules</name>\r
+ <version>0</version>\r
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>CompilerMisraOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCModuleTypeOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCModuleType</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCModuleTypeCmdlineProducer</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCIncludePath2</name>\r
+ <state>$PROJ_DIR$\..\..\source\portable\iar\LPC2000</state>\r
+ <state>$PROJ_DIR$\..\common\include</state>\r
+ <state>$PROJ_DIR$\..\..\source\include</state>\r
+ <state>$PROJ_DIR$\SrcIAR</state>\r
+ <state>$PROJ_DIR$</state>\r
+ </option>\r
+ <option>\r
+ <name>CCStdIncCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCStdIncludePath</name>\r
+ <state>$TOOLKIT_DIR$\INC\</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>AARM</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>6</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>AObjPrefix</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AEndian</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>ACaseSensitivity</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>MacroChars</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnWhat</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnOne</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnRange1</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnRange2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>ADebug</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AltRegisterNames</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ADefines</name>\r
+ <state></state>\r
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+ <option>\r
+ <name>AList</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AListHeader</name>\r
+ <state>1</state>\r
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+ <option>\r
+ <name>AListing</name>\r
+ <state>1</state>\r
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+ <option>\r
+ <name>Includes</name>\r
+ <state>0</state>\r
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+ <option>\r
+ <name>MacDefs</name>\r
+ <state>0</state>\r
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+ <option>\r
+ <name>MacExps</name>\r
+ <state>1</state>\r
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+ <option>\r
+ <name>MacExec</name>\r
+ <state>0</state>\r
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+ <option>\r
+ <name>OnlyAssed</name>\r
+ <state>0</state>\r
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+ <option>\r
+ <name>MultiLine</name>\r
+ <state>0</state>\r
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+ <option>\r
+ <name>PageLengthCheck</name>\r
+ <state>0</state>\r
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+ <option>\r
+ <name>PageLength</name>\r
+ <state>80</state>\r
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+ <option>\r
+ <name>TabSpacing</name>\r
+ <state>8</state>\r
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+ <option>\r
+ <name>AXRef</name>\r
+ <state>0</state>\r
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+ <option>\r
+ <name>AXRefDefines</name>\r
+ <state>0</state>\r
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+ <option>\r
+ <name>AXRefInternal</name>\r
+ <state>0</state>\r
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+ <option>\r
+ <name>AXRefDual</name>\r
+ <state>0</state>\r
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+ <option>\r
+ <name>AProcessor</name>\r
+ <state>1</state>\r
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+ <option>\r
+ <name>AFpuProcessor</name>\r
+ <state>1</state>\r
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+ <option>\r
+ <name>AOutputFile</name>\r
+ <state>$FILE_BNAME$.r79</state>\r
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+ <option>\r
+ <name>AMultibyteSupport</name>\r
+ <state>0</state>\r
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+ <option>\r
+ <name>AModuleTypeOverride</name>\r
+ <state>0</state>\r
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+ <option>\r
+ <name>AModuleType</name>\r
+ <state>0</state>\r
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+ <option>\r
+ <name>AModuleTypeCmdlineProducer</name>\r
+ <state>0</state>\r
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+ <option>\r
+ <name>ALimitErrorsCheck</name>\r
+ <state>0</state>\r
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+ <option>\r
+ <name>ALimitErrorsEdit</name>\r
+ <state>100</state>\r
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+ <option>\r
+ <name>AIgnoreStdInclude</name>\r
+ <state>0</state>\r
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+ <option>\r
+ <name>AStdIncludes</name>\r
+ <state>$TOOLKIT_DIR$\INC\</state>\r
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+ <option>\r
+ <name>AUserIncludes</name>\r
+ <state>$PROJ_DIR$\srciar\</state>\r
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+ <state>$PROJ_DIR$\..\common\include</state>\r
+ <state>$PROJ_DIR$\..\..\Source\include</state>\r
+ <state>$PROJ_DIR$</state>\r
+ <state>$PROJ_DIR$\..\..\Source\portable\IAR\LPC2000</state>\r
+ </option>\r
+ <option>\r
+ <name>AExtraOptionsCheckV2</name>\r
+ <state>0</state>\r
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+ <option>\r
+ <name>AExtraOptionsV2</name>\r
+ <state></state>\r
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+ </settings>\r
+ <settings>\r
+ <name>CUSTOM</name>\r
+ <archiveVersion>3</archiveVersion>\r
+ <data>\r
+ <extensions></extensions>\r
+ <cmdline></cmdline>\r
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+ </settings>\r
+ <settings>\r
+ <name>BICOMP</name>\r
+ <archiveVersion>0</archiveVersion>\r
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+ <settings>\r
+ <name>BUILDACTION</name>\r
+ <archiveVersion>1</archiveVersion>\r
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+ <prebuild></prebuild>\r
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+ </settings>\r
+ <settings>\r
+ <name>XLINK</name>\r
+ <archiveVersion>2</archiveVersion>\r
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+ <version>17</version>\r
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+ <name>XOutOverride</name>\r
+ <state>0</state>\r
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+ <option>\r
+ <name>OutputFile</name>\r
+ <state>rtosdemo.bin</state>\r
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+ <option>\r
+ <name>OutputFormat</name>\r
+ <version>11</version>\r
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+ <name>FormatVariant</name>\r
+ <version>6</version>\r
+ <state>2</state>\r
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+ <option>\r
+ <name>SecondaryOutputFile</name>\r
+ <state>(None for the selected format)</state>\r
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+ <name>XDefines</name>\r
+ <state></state>\r
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+ <option>\r
+ <name>AlwaysOutput</name>\r
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+ <state>1</state>\r
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+ <option>\r
+ <name>ModuleStatus</name>\r
+ <state>0</state>\r
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+ <state>1</state>\r
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+ <state></state>\r
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+ <name>XAROverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>XAROutput</name>\r
+ <state>###Unitialized###</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>BILINK</name>\r
+ <archiveVersion>0</archiveVersion>\r
+ <data/>\r
+ </settings>\r
+ </configuration>\r
+ <group>\r
+ <name>Demo Source</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\BlockQ.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\comtest.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\dynamic.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\flash.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\MemMang\heap_1.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\integer.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\main.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\ParTest\ParTest.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\PollQ.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\semtest.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\serial\serial.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\serial\serialISR.s79</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>Scheduler Source</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\list.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\IAR\LPC2000\port.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\IAR\LPC2000\portasm.s79</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\queue.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\tasks.c</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>System Files</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\SrcIAR\cstartup.s79</name>\r
+ </file>\r
+ </group>\r
+</project>\r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<workspace>\r
+ <project>\r
+ <path>$WS_DIR$\rtosdemo.ewp</path>\r
+ </project>\r
+ <batchBuild/>\r
+</workspace>\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+\r
+/*\r
+ BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0.\r
+*/\r
+\r
+/* Standard includes. */\r
+#include <stdlib.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "queue.h"\r
+#include "task.h"\r
+\r
+/* Demo application includes. */\r
+#include "serial.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Constants to setup and access the UART. */\r
+#define serDLAB ( ( unsigned portCHAR ) 0x80 )\r
+#define serENABLE_INTERRUPTS ( ( unsigned portCHAR ) 0x03 )\r
+#define serNO_PARITY ( ( unsigned portCHAR ) 0x00 )\r
+#define ser1_STOP_BIT ( ( unsigned portCHAR ) 0x00 )\r
+#define ser8_BIT_CHARS ( ( unsigned portCHAR ) 0x03 )\r
+#define serFIFO_ON ( ( unsigned portCHAR ) 0x01 )\r
+#define serCLEAR_FIFO ( ( unsigned portCHAR ) 0x06 )\r
+#define serWANTED_CLOCK_SCALING ( ( unsigned portLONG ) 16 )\r
+\r
+/* Constants to setup and access the VIC. */\r
+#define serU0VIC_CHANNEL ( ( unsigned portLONG ) 0x0006 )\r
+#define serU0VIC_CHANNEL_BIT ( ( unsigned portLONG ) 0x0040 )\r
+#define serU0VIC_ENABLE ( ( unsigned portLONG ) 0x0020 )\r
+#define serCLEAR_VIC_INTERRUPT ( ( unsigned portLONG ) 0 )\r
+\r
+/* Constants to determine the ISR source. */\r
+#define serSOURCE_THRE ( ( unsigned portCHAR ) 0x02 )\r
+#define serSOURCE_RX_TIMEOUT ( ( unsigned portCHAR ) 0x0c )\r
+#define serSOURCE_ERROR ( ( unsigned portCHAR ) 0x06 )\r
+#define serSOURCE_RX ( ( unsigned portCHAR ) 0x04 )\r
+#define serINTERRUPT_SOURCE_MASK ( ( unsigned portCHAR ) 0x0f )\r
+\r
+/* Misc. */\r
+#define serINVALID_QUEUE ( ( xQueueHandle ) 0 )\r
+#define serHANDLE ( ( xComPortHandle ) 1 )\r
+#define serNO_BLOCK ( ( portTickType ) 0 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Queues used to hold received characters, and characters waiting to be\r
+transmitted. */\r
+static xQueueHandle xRxedChars;\r
+static xQueueHandle xCharsForTx;\r
+static volatile portLONG lTHREEmpty = pdFALSE;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The ISR. Note that this is called by a wrapper written in the file\r
+SerialISR.s79. See the WEB documentation for this port for further\r
+information. */\r
+__arm void vSerialISR( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )\r
+{\r
+unsigned portLONG ulDivisor, ulWantedClock;\r
+xComPortHandle xReturn = serHANDLE;\r
+extern void ( vSerialISREntry) ( void );\r
+\r
+ /* Create the queues used to hold Rx and Tx characters. */\r
+ xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );\r
+ xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );\r
+\r
+ /* Initialise the THRE empty flag. */\r
+ lTHREEmpty = pdTRUE;\r
+\r
+ if(\r
+ ( xRxedChars != serINVALID_QUEUE ) &&\r
+ ( xCharsForTx != serINVALID_QUEUE ) &&\r
+ ( ulWantedBaud != ( unsigned portLONG ) 0 )\r
+ )\r
+ {\r
+ portENTER_CRITICAL();\r
+ {\r
+ /* Setup the baud rate: Calculate the divisor value. */\r
+ ulWantedClock = ulWantedBaud * serWANTED_CLOCK_SCALING;\r
+ ulDivisor = configCPU_CLOCK_HZ / ulWantedClock;\r
+\r
+ /* Set the DLAB bit so we can access the divisor. */\r
+ U0LCR |= serDLAB;\r
+\r
+ /* Setup the divisor. */\r
+ U0DLL = ( unsigned portCHAR ) ( ulDivisor & ( unsigned portLONG ) 0xff );\r
+ ulDivisor >>= 8;\r
+ U0DLM = ( unsigned portCHAR ) ( ulDivisor & ( unsigned portLONG ) 0xff );\r
+\r
+ /* Turn on the FIFO's and clear the buffers. */\r
+ U0FCR = ( serFIFO_ON | serCLEAR_FIFO );\r
+\r
+ /* Setup transmission format. */\r
+ U0LCR = serNO_PARITY | ser1_STOP_BIT | ser8_BIT_CHARS;\r
+\r
+ /* Setup the VIC for the UART. */\r
+ VICIntSelect &= ~( serU0VIC_CHANNEL_BIT );\r
+ VICIntEnable |= serU0VIC_CHANNEL_BIT;\r
+ VICVectAddr1 = ( unsigned portLONG ) vSerialISREntry;\r
+ VICVectCntl1 = serU0VIC_CHANNEL | serU0VIC_ENABLE;\r
+\r
+ /* Enable UART0 interrupts. */\r
+ U0IER |= serENABLE_INTERRUPTS;\r
+ }\r
+ portEXIT_CRITICAL();\r
+\r
+ xReturn = ( xComPortHandle ) 1;\r
+ }\r
+ else\r
+ {\r
+ xReturn = ( xComPortHandle ) 0;\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )\r
+{\r
+ /* The port handle is not required as this driver only supports UART0. */\r
+ ( void ) pxPort;\r
+\r
+ /* Get the next character from the buffer. Return false if no characters\r
+ are available, or arrive before xBlockTime expires. */\r
+ if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )\r
+ {\r
+ return pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ return pdFALSE;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength )\r
+{\r
+signed portCHAR *pxNext;\r
+\r
+ /* NOTE: This implementation does not handle the queue being full as no\r
+ block time is used! */\r
+\r
+ /* The port handle is not required as this driver only supports UART0. */\r
+ ( void ) pxPort;\r
+ ( void ) usStringLength;\r
+\r
+ /* Send each character in the string, one at a time. */\r
+ pxNext = ( signed portCHAR * ) pcString;\r
+ while( *pxNext )\r
+ {\r
+ xSerialPutChar( pxPort, *pxNext, serNO_BLOCK );\r
+ pxNext++;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )\r
+{\r
+signed portBASE_TYPE xReturn;\r
+\r
+ /* The port handle is not required as this driver only supports UART0. */\r
+ ( void ) pxPort;\r
+\r
+ portENTER_CRITICAL();\r
+ {\r
+ /* Is there space to write directly to the UART? */\r
+ if( lTHREEmpty == ( portLONG ) pdTRUE )\r
+ {\r
+ /* We wrote the character directly to the UART, so was\r
+ successful. */\r
+ lTHREEmpty = pdFALSE;\r
+ U0THR = cOutChar;\r
+ xReturn = pdPASS;\r
+ }\r
+ else\r
+ {\r
+ /* We cannot write directly to the UART, so queue the character.\r
+ Block for a maximum of xBlockTime if there is no space in the\r
+ queue. It is ok to block within a critical section as each\r
+ task has it's own critical section management. */\r
+ xReturn = xQueueSend( xCharsForTx, &cOutChar, xBlockTime );\r
+\r
+ /* Depending on queue sizing and task prioritisation: While we\r
+ were blocked waiting to post interrupts were not disabled. It is\r
+ possible that the serial ISR has emptied the Tx queue, in which\r
+ case we need to start the Tx off again. */\r
+ if( lTHREEmpty == ( portLONG ) pdTRUE )\r
+ {\r
+ xQueueReceive( xCharsForTx, &cOutChar, serNO_BLOCK );\r
+ lTHREEmpty = pdFALSE;\r
+ U0THR = cOutChar;\r
+ }\r
+ }\r
+ }\r
+ portEXIT_CRITICAL();\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+__arm void vSerialISR( void )\r
+{\r
+signed portCHAR cChar;\r
+portBASE_TYPE xTaskWokenByRx = pdFALSE, xTaskWokenByTx = pdFALSE;\r
+\r
+ /* What caused the interrupt? */\r
+ switch( U0IIR & serINTERRUPT_SOURCE_MASK )\r
+ {\r
+ case serSOURCE_ERROR : /* Not handling this, but clear the interrupt. */\r
+ cChar = U0LSR;\r
+ break;\r
+\r
+ case serSOURCE_THRE : /* The THRE is empty. If there is another\r
+ character in the Tx queue, send it now. */\r
+ if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWokenByTx ) == pdTRUE )\r
+ {\r
+ U0THR = cChar;\r
+ }\r
+ else\r
+ {\r
+ /* There are no further characters\r
+ queued to send so we can indicate\r
+ that the THRE is available. */\r
+ lTHREEmpty = pdTRUE;\r
+ }\r
+ break;\r
+\r
+ case serSOURCE_RX_TIMEOUT :\r
+ case serSOURCE_RX : /* A character was received. Place it in\r
+ the queue of received characters. */\r
+ cChar = U0RBR;\r
+ if( xQueueSendFromISR( xRxedChars, &cChar, pdFALSE ) )\r
+ {\r
+ xTaskWokenByRx = pdTRUE;\r
+ }\r
+ break;\r
+\r
+ default : /* There is nothing to do, leave the ISR. */\r
+ break;\r
+ }\r
+\r
+ /* Exit the ISR. If a task was woken by either a character being received\r
+ or transmitted then a context switch will occur. */\r
+ portEND_SWITCHING_ISR( ( xTaskWokenByTx || xTaskWokenByRx ) );\r
+\r
+ /* Clear the ISR in the VIC. */\r
+ VICVectAddr = serCLEAR_VIC_INTERRUPT;\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+ RSEG ICODE:CODE\r
+ CODE32\r
+\r
+ EXTERN vSerialISR\r
+ PUBLIC vSerialISREntry\r
+\r
+; Wrapper for the serial port interrupt service routine. This can cause a\r
+; context switch so requires an assembly wrapper.\r
+\r
+; Defines the portSAVE_CONTEXT and portRESTORE_CONTEXT macros.\r
+#include "ISR_Support.h"\r
+\r
+vSerialISREntry:\r
+\r
+ portSAVE_CONTEXT ; Save the context of the current task.\r
+\r
+ bl vSerialISR ; Call the ISR routine.\r
+\r
+ portRESTORE_CONTEXT ; Restore the context of the current task -\r
+ ; which may be different to the task that\r
+ ; was interrupted.\r
+\r
+ END\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<Project>\r
+ <Desktop>\r
+ <Static>\r
+ <Workspace>\r
+ <ColumnWidths>\r
+ \r
+ \r
+ \r
+ <Column0>189</Column0><Column1>27</Column1><Column2>27</Column2></ColumnWidths>\r
+ </Workspace>\r
+ <Disassembly>\r
+ \r
+ \r
+ \r
+ <PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><MixedMode>1</MixedMode><CodeCovEnabled>0</CodeCovEnabled><CodeCovShow>0</CodeCovShow></Disassembly>\r
+ <Debug-Log/>\r
+ <Build/>\r
+ <Register><PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows></Register><QWatch><Column0>188</Column0><Column1>171</Column1><Column2>100</Column2><Column3>100</Column3></QWatch><Memory><ZoneNumber>0</ZoneNumber><FindDirection>1</FindDirection><FindAsHex>0</FindAsHex></Memory><Watch><Format><struct_types/><watch_formats/></Format></Watch></Static>\r
+ <Windows>\r
+ <Wnd0>\r
+ <Tabs>\r
+ <Tab>\r
+ <Identity>TabID-23416-30482</Identity>\r
+ <TabName>Workspace</TabName>\r
+ <Factory>Workspace</Factory>\r
+ <Session>\r
+ \r
+ <NodeDict><ExpandedNode>rtosdemo</ExpandedNode></NodeDict></Session>\r
+ </Tab>\r
+ </Tabs>\r
+ \r
+ <SelectedTab>0</SelectedTab></Wnd0>\r
+ \r
+ <Wnd2>\r
+ <Tabs>\r
+ <Tab>\r
+ <Identity>TabID-12145-30489</Identity>\r
+ <TabName>Debug Log</TabName>\r
+ <Factory>Debug-Log</Factory>\r
+ <Session/>\r
+ </Tab>\r
+ <Tab>\r
+ <Identity>TabID-22894-30492</Identity>\r
+ <TabName>Build</TabName>\r
+ <Factory>Build</Factory>\r
+ <Session/>\r
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+ <Wnd4><Tabs><Tab><Identity>TabID-18780-12821</Identity><TabName>Memory</TabName><Factory>Memory</Factory><Session><SelectionAnchor>2097764</SelectionAnchor><SelectionEnd>2097764</SelectionEnd><UnitsPerGroup>1</UnitsPerGroup><EndianMode>0</EndianMode><DataCovEnabled>0</DataCovEnabled><DataCovShown>0</DataCovShown></Session></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd4><Wnd5><Tabs><Tab><Identity>TabID-23506-14575</Identity><TabName>Watch</TabName><Factory>Watch</Factory><Session><Expressions><Expression><Expression>pxCurrentTCB</Expression></Expression><Expression><Expression>ulCriticalNesting</Expression></Expression></Expressions><TabId>0</TabId><Column0>176</Column0><Column1>100</Column1><Column2>100</Column2><Column3>100</Column3></Session></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd5><Wnd1><Tabs><Tab><Identity>TabID-4859-22480</Identity><TabName>Disassembly</TabName><Factory>Disassembly</Factory><Session/></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd1><Wnd3><Tabs><Tab><Identity>TabID-154-22568</Identity><TabName>Register</TabName><Factory>Register</Factory><Session><REG1>0</REG1><REG2>0</REG2><Group>0</Group><States>1</States><State0>CPSR</State0></Session></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd3></Windows>\r
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+ \r
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+tom><Float><Sizes/></Float></Positions>\r
+ </Desktop>\r
+</Project>\r
+\r
+\r
--- /dev/null
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+NumStates=_ 1\r
+State 1=_ 1\r
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--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
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+ <Workspace>\r
+ <ColumnWidths>\r
+ \r
+ \r
+ \r
+ <Column0>138</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>\r
+ </Workspace>\r
+ <Disassembly>\r
+ \r
+ \r
+ \r
+ <PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><MixedMode>1</MixedMode><CodeCovEnabled>0</CodeCovEnabled><CodeCovShow>0</CodeCovShow></Disassembly>\r
+ <Debug-Log><PreferedWindows><Position>3</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows><Window><Factory>Build</Factory></Window></Windows></PreferedWindows></Debug-Log>\r
+ <Build><PreferedWindows><Position>3</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows><Window><Factory>Debug-Log</Factory></Window></Windows></PreferedWindows></Build>\r
+ <Register>\r
+ <PreferedWindows>\r
+ \r
+ \r
+ \r
+ \r
+ <Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows>\r
+ </Register>\r
+ <QWatch><Column0>161</Column0><Column1>100</Column1><Column2>100</Column2><Column3>100</Column3></QWatch><Memory><PreferedWindows><Position>3</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><ZoneNumber>0</ZoneNumber><FindDirection>1</FindDirection><FindAsHex>0</FindAsHex></Memory><Driver-Trace><PreferedWindows><Position>3</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><Column0>300</Column0></Driver-Trace><Breakpoints/><Watch><Format><struct_types/><watch_formats/></Format><PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><Column0>100</Column0><Column1>100</Column1><Column2>100</Column2><Column3>100</Column3></Watch><QuickWatch><PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><Column0>100</Column0><Column1>100</Column1><Column2>100</Column2><Column3>100</Column3></QuickWatch></Static>\r
+ <Windows>\r
+ \r
+ \r
+ \r
+ <Wnd2>\r
+ <Tabs>\r
+ <Tab>\r
+ <Identity>TabID-22256-14845</Identity>\r
+ <TabName>Workspace</TabName>\r
+ <Factory>Workspace</Factory>\r
+ <Session>\r
+ \r
+ <NodeDict><ExpandedNode>rtosdemo</ExpandedNode><ExpandedNode>rtosdemo/Demo Source</ExpandedNode><ExpandedNode>rtosdemo/Scheduler Source</ExpandedNode><ExpandedNode>rtosdemo/System Files</ExpandedNode><ExpandedNode>rtosdemo/USBSample.c</ExpandedNode></NodeDict></Session>\r
+ </Tab>\r
+ </Tabs>\r
+ \r
+ <SelectedTab>0</SelectedTab></Wnd2><Wnd3><Tabs><Tab><Identity>TabID-32269-5949</Identity><TabName>Debug Log</TabName><Factory>Debug-Log</Factory><Session/></Tab><Tab><Identity>TabID-30271-4373</Identity><TabName>Breakpoints</TabName><Factory>Breakpoints</Factory><Session/></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd3></Windows>\r
+ <Editor>\r
+ \r
+ \r
+ \r
+ \r
+ <Pane><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Source\list.c</Filename><XPos>0</XPos><YPos>159</YPos><SelStart>6486</SelStart><SelEnd>6613</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Source\include\list.h</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Source\tasks.c</Filename><XPos>0</XPos><YPos>172</YPos><SelStart>6942</SelStart><SelEnd>6959</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Source\include\task.h</Filename><XPos>0</XPos><YPos>50</YPos><SelStart>2282</SelStart><SelEnd>2291</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Demo\ARM7_LPC2129_IAR\serial\serialISR.s79</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Source\portable\IAR\LPC2000\ISR_Support.h</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Source\portable\IAR\LPC2000\portmacro.h</Filename><XPos>0</XPos><YPos>52</YPos><SelStart>2522</SelStart><SelEnd>2531</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Source\queue.c</Filename><XPos>0</XPos><YPos>148</YPos><SelStart>7593</SelStart><SelEnd>7593</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Demo\ARM7_LPC2129_IAR\main.c</Filename><XPos>0</XPos><YPos>166</YPos><SelStart>7172</SelStart><SelEnd>7172</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Source\portable\MemMang\heap_1.c</Filename><XPos>0</XPos><YPos>75</YPos><SelStart>2927</SelStart><SelEnd>2938</SelEnd></Tab><ActiveTab>9</ActiveTab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>\r
+ <Positions>\r
+ \r
+ \r
+ \r
+ \r
+ \r
+ <Top><Row0><Sizes><Toolbar-0084fb00><key>iaridepm1</key></Toolbar-0084fb00><Toolbar-021f0ee0><key>debuggergui1</key></Toolbar-021f0ee0></Sizes></Row0></Top><Left><Row0><Sizes><Wnd2><Rect><Top>-2</Top><Left>-2</Left><Bottom>739</Bottom><Right>212</Right><x>-2</x><y>-2</y><xscreen>0</xscreen><yscreen>0</yscreen><sizeHorzCX>0</sizeHorzCX><sizeHorzCY>0</sizeHorzCY><sizeVertCX>133750</sizeVertCX><sizeVertCY>662198</sizeVertCY></Rect></Wnd2></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd3><Rect><Top>-2</Top><Left>-2</Left><Bottom>333</Bottom><Right>1602</Right><x>-2</x><y>-2</y><xscreen>1604</xscreen><yscreen>335</yscreen><sizeHorzCX>1002500</sizeHorzCX><sizeHorzCY>299374</sizeHorzCY><sizeVertCX>92500</sizeVertCX><sizeVertCY>132260</sizeVertCY></Rect></Wnd3></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>\r
+ </Desktop>\r
+</Project>\r
+\r
+\r
--- /dev/null
+[DisAssemblyWindow]\r
+NumStates=_ 1\r
+State 1=_ 1\r
+[JLinkDriver]\r
+WatchVectorCatch=_ 0\r
+WatchCond=_ 0\r
+Watch0=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0\r
+Watch1=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0\r
+[Low Level]\r
+Pipeline mode=1\r
+Initialized=0\r
+[Log file]\r
+LoggingEnabled=_ 0\r
+LogFile=_ ""\r
+Category=_ 0\r
+[TermIOLog]\r
+LoggingEnabled=_ 0\r
+LogFile=_ ""\r
+[Disassemble mode]\r
+mode=0\r
+[Breakpoints]\r
+Bp0=_ "Code" "{E:\Dev\FreeRTOS\Source\queue.c}.179.3@1" 1 0 0 0 "" 0 ""\r
+Count=1\r
+[Interrupts]\r
+Enabled=1\r
+[MemoryMap]\r
+Enabled=0\r
+TypeVolition=1\r
+UnspecRange=1\r
+ActionState=1\r
+[TraceHelper]\r
+Enabled=0\r
+ShowSource=1\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<Workspace>\r
+ <ConfigDictionary>\r
+ \r
+ <CurrentConfigs><Project>rtosdemo/Flash Debug</Project></CurrentConfigs></ConfigDictionary>\r
+ <Desktop>\r
+ <Static>\r
+ <Workspace>\r
+ <ColumnWidths>\r
+ \r
+ \r
+ \r
+ <Column0>229</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>\r
+ </Workspace>\r
+ <Build><ColumnWidth0>18</ColumnWidth0><ColumnWidth1>1155</ColumnWidth1><ColumnWidth2>308</ColumnWidth2><ColumnWidth3>77</ColumnWidth3></Build>\r
+ <Debug-Log/>\r
+ <TerminalIO/>\r
+ <CodeCoveragePlugin/>\r
+ <Profiling/>\r
+ <Watch>\r
+ <Format>\r
+ <struct_types/>\r
+ <watch_formats/>\r
+ </Format>\r
+ </Watch>\r
+ <Disassembly><MixedMode>1</MixedMode><CodeCovEnabled>0</CodeCovEnabled><CodeCovShow>0</CodeCovShow></Disassembly><Memory><ZoneNumber>0</ZoneNumber><FindDirection>1</FindDirection><FindAsHex>0</FindAsHex></Memory><Find-in-Files><ColumnWidth0>552</ColumnWidth0><ColumnWidth1>78</ColumnWidth1><ColumnWidth2>946</ColumnWidth2></Find-in-Files><Breakpoints/></Static>\r
+ <Windows>\r
+ \r
+ \r
+ <Wnd2>\r
+ <Tabs>\r
+ <Tab>\r
+ <Identity>TabID-17425-14382</Identity>\r
+ <TabName>Workspace</TabName>\r
+ <Factory>Workspace</Factory>\r
+ <Session>\r
+ \r
+ <NodeDict><ExpandedNode>rtosdemo</ExpandedNode><ExpandedNode>rtosdemo/Scheduler Source</ExpandedNode><ExpandedNode>rtosdemo/System Files</ExpandedNode></NodeDict></Session>\r
+ </Tab>\r
+ </Tabs>\r
+ \r
+ <SelectedTab>0</SelectedTab></Wnd2><Wnd3><Tabs><Tab><Identity>TabID-22109-27077</Identity><TabName>Build</TabName><Factory>Build</Factory><Session/></Tab><Tab><Identity>TabID-12074-10873</Identity><TabName>Breakpoints</TabName><Factory>Breakpoints</Factory><Session/></Tab><Tab><Identity>TabID-18349-15872</Identity><TabName>Debug Log</TabName><Factory>Debug-Log</Factory><Session/></Tab><Tab><Identity>TabID-30013-18825</Identity><TabName>Find in Files</TabName><Factory>Find-in-Files</Factory><Session/></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd3></Windows>\r
+ <Editor>\r
+ \r
+ \r
+ \r
+ \r
+ <Pane><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Source\list.c</Filename><XPos>0</XPos><YPos>159</YPos><SelStart>6486</SelStart><SelEnd>6613</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Source\include\list.h</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Source\tasks.c</Filename><XPos>0</XPos><YPos>172</YPos><SelStart>6942</SelStart><SelEnd>6959</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Source\include\task.h</Filename><XPos>0</XPos><YPos>50</YPos><SelStart>2282</SelStart><SelEnd>2291</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Demo\ARM7_LPC2129_IAR\serial\serialISR.s79</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Source\portable\IAR\LPC2000\ISR_Support.h</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Source\portable\IAR\LPC2000\portmacro.h</Filename><XPos>0</XPos><YPos>52</YPos><SelStart>2522</SelStart><SelEnd>2531</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Source\queue.c</Filename><XPos>0</XPos><YPos>148</YPos><SelStart>7593</SelStart><SelEnd>7593</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Demo\ARM7_LPC2129_IAR\main.c</Filename><XPos>0</XPos><YPos>166</YPos><SelStart>7172</SelStart><SelEnd>7172</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Source\portable\MemMang\heap_1.c</Filename><XPos>0</XPos><YPos>75</YPos><SelStart>2927</SelStart><SelEnd>2938</SelEnd></Tab><ActiveTab>9</ActiveTab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>\r
+ <Positions>\r
+ \r
+ \r
+ \r
+ \r
+ \r
+ <Top><Row0><Sizes><Toolbar-0084fb00><key>iaridepm1</key></Toolbar-0084fb00></Sizes></Row0><Row1><Sizes/></Row1></Top><Left><Row0><Sizes><Wnd2><Rect><Top>-2</Top><Left>-2</Left><Bottom>944</Bottom><Right>303</Right><x>-2</x><y>-2</y><xscreen>0</xscreen><yscreen>0</yscreen><sizeHorzCX>0</sizeHorzCX><sizeHorzCY>0</sizeHorzCY><sizeVertCX>190625</sizeVertCX><sizeVertCY>845397</sizeVertCY></Rect></Wnd2></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd3><Rect><Top>-2</Top><Left>-2</Left><Bottom>128</Bottom><Right>1602</Right><x>-2</x><y>-2</y><xscreen>1604</xscreen><yscreen>130</yscreen><sizeHorzCX>1002500</sizeHorzCX><sizeHorzCY>116175</sizeHorzCY><sizeVertCX>55000</sizeVertCX><sizeVertCY>78641</sizeVertCY></Rect></Wnd3></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>\r
+ </Desktop>\r
+</Workspace>\r
+\r
+\r
--- /dev/null
+// IAR XLINK Setup\r
+// Autogenerated file - do not edit \r
+%\r
+setrangelist($evec_ADR,[0-3F]);\r
+setrangelist($internal_ROM,[8000-FFFFF]);\r
+setrangelist($external_ROM,[]);\r
+setrangelist($internal_RAM,[100000-7FFFFF]);\r
+setrangelist($external_RAM,[]);\r
+$CSTACK_SIZE=200;\r
+$IRQSTACK_SIZE=400;\r
+$HEAP_SIZE=4;\r
+$COMMANDS="";\r
+$STACK_LOCATION="Internal RAM";\r
+$IRQSTACK_LOCATION="Internal RAM";\r
+$HEAP_LOCATION="Internal RAM";\r
+$iar_saved_xclfilename="E:\Dev\FreeRTOS\Demo\ARM7_LPC2129_IAR\resource\rtosdemo_lnk.xcl";\r
+%
\ No newline at end of file
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+#include <lpc21xx.h>\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. \r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 60000000 ) /* =12.0MHz xtal multiplied by 5 using the PLL. */\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 100 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) 14250 )\r
+#define configMAX_TASK_NAME_LEN ( 16 )\r
+#define configUSE_TRACE_FACILITY 0\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 1\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+\r
+\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+\r
+#include "FreeRTOS.h"\r
+#include "portable.h"\r
+#include "partest.h"\r
+\r
+#define partstFIRST_IO ( ( unsigned portLONG ) 0x10000 )\r
+#define partstNUM_LEDS ( 8 )\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple parallel port IO routines.\r
+ *-----------------------------------------------------------*/\r
+\r
+void vParTestInitialise( void )\r
+{\r
+ /* This is performed from main() as the io bits are shared with other setup\r
+ functions. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )\r
+{\r
+unsigned portLONG ulLED = partstFIRST_IO;\r
+\r
+ if( uxLED < partstNUM_LEDS )\r
+ {\r
+ /* Rotate to the wanted bit of port 0. Only P16 to P23 have an LED\r
+ attached. */\r
+ ulLED <<= ( unsigned portLONG ) uxLED;\r
+\r
+ /* Set or clear the output. */\r
+ if( xValue )\r
+ {\r
+ IOSET1 = ulLED;\r
+ }\r
+ else\r
+ {\r
+ IOCLR1 = ulLED; \r
+ }\r
+ } \r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+unsigned portLONG ulLED = partstFIRST_IO, ulCurrentState;\r
+\r
+ if( uxLED < partstNUM_LEDS )\r
+ {\r
+ /* Rotate to the wanted bit of port 0. Only P10 to P13 have an LED\r
+ attached. */\r
+ ulLED <<= ( unsigned portLONG ) uxLED;\r
+\r
+ /* If this bit is already set, clear it, and visa versa. */\r
+ ulCurrentState = IOPIN1;\r
+ if( ulCurrentState & ulLED )\r
+ {\r
+ IOCLR1 = ulLED;\r
+ }\r
+ else\r
+ {\r
+ IOSET1 = ulLED; \r
+ }\r
+ } \r
+}\r
+\r
--- /dev/null
+[Signal 1]\r
+DispName=Port1\r
+PlotType=1\r
+Color=16711935\r
+MinDec=0\r
+MinVal=0.\r
+MaxDec=0\r
+MaxVal=-1.\r
+Mask=65536\r
+Offset=16\r
+[Signal 2]\r
+DispName=Port1\r
+PlotType=1\r
+Color=255\r
+MinDec=0\r
+MinVal=0.\r
+MaxDec=0\r
+MaxVal=-1.\r
+Mask=131072\r
+Offset=17\r
+[Signal 3]\r
+DispName=Port1\r
+PlotType=1\r
+Color=32768\r
+MinDec=0\r
+MinVal=0.\r
+MaxDec=0\r
+MaxVal=-1.\r
+Mask=262144\r
+Offset=18\r
+[Signal 4]\r
+DispName=Port1\r
+PlotType=1\r
+Color=16711680\r
+MinDec=0\r
+MinVal=0.\r
+MaxDec=0\r
+MaxVal=-1.\r
+Mask=524288\r
+Offset=19\r
--- /dev/null
+/***********************************************************************/\r
+/* This file is part of the uVision/ARM development tools */\r
+/* Copyright KEIL ELEKTRONIK GmbH 2002-2004 */\r
+/***********************************************************************/\r
+/* */\r
+/* STARTUP.S: Startup file for Philips LPC2000 device series */\r
+/* */\r
+/***********************************************************************/\r
+\r
+\r
+/* \r
+//*** <<< Use Configuration Wizard in Context Menu >>> *** \r
+*/\r
+\r
+\r
+// *** Startup Code (executed after Reset) ***\r
+\r
+\r
+// Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs\r
+\r
+ Mode_USR EQU 0x10\r
+ Mode_FIQ EQU 0x11\r
+ Mode_IRQ EQU 0x12\r
+ Mode_SVC EQU 0x13\r
+ Mode_ABT EQU 0x17\r
+ Mode_UND EQU 0x1B\r
+ Mode_SYS EQU 0x1F\r
+\r
+ I_Bit EQU 0x80 /* when I bit is set, IRQ is disabled */\r
+ F_Bit EQU 0x40 /* when F bit is set, FIQ is disabled */\r
+\r
+\r
+/*\r
+// <h> Stack Configuration (Stack Sizes in Bytes)\r
+// <o0> Undefined Mode <0x0-0xFFFFFFFF>\r
+// <o1> Supervisor Mode <0x0-0xFFFFFFFF>\r
+// <o2> Abort Mode <0x0-0xFFFFFFFF>\r
+// <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF>\r
+// <o4> Interrupt Mode <0x0-0xFFFFFFFF>\r
+// <o5> User/System Mode <0x0-0xFFFFFFFF>\r
+// </h>\r
+*/\r
+ UND_Stack_Size EQU 0x00000004\r
+ SVC_Stack_Size EQU 0x00000100\r
+ ABT_Stack_Size EQU 0x00000004\r
+ FIQ_Stack_Size EQU 0x00000004\r
+ IRQ_Stack_Size EQU 0x00000300\r
+ USR_Stack_Size EQU 0x00000200\r
+\r
+AREA STACK, DATA, READWRITE, ALIGN=2\r
+ DS (USR_Stack_Size+3)&~3 ; Stack for User/System Mode \r
+ DS (IRQ_Stack_Size+3)&~3 ; Stack for Interrupt Mode\r
+ DS (FIQ_Stack_Size+3)&~3 ; Stack for Fast Interrupt Mode \r
+ DS (ABT_Stack_Size+3)&~3 ; Stack for Abort Mode\r
+ DS (SVC_Stack_Size+3)&~3 ; Stack for Supervisor Mode\r
+ DS (UND_Stack_Size+3)&~3 ; Stack for Undefined Mode\r
+Top_Stack:\r
+\r
+\r
+// Phase Locked Loop (PLL) definitions\r
+ PLL_BASE EQU 0xE01FC080 /* PLL Base Address */\r
+ PLLCON_OFS EQU 0x00 /* PLL Control Offset*/\r
+ PLLCFG_OFS EQU 0x04 /* PLL Configuration Offset */\r
+ PLLSTAT_OFS EQU 0x08 /* PLL Status Offset */\r
+ PLLFEED_OFS EQU 0x0C /* PLL Feed Offset */\r
+ PLLCON_PLLE EQU (1<<0) /* PLL Enable */\r
+ PLLCON_PLLC EQU (1<<1) /* PLL Connect */\r
+ PLLCFG_MSEL EQU (0x1F<<0) /* PLL Multiplier */\r
+ PLLCFG_PSEL EQU (0x03<<5) /* PLL Divider */\r
+ PLLSTAT_PLOCK EQU (1<<10) /* PLL Lock Status */\r
+\r
+/*\r
+// <e> PLL Setup\r
+// <i> Phase Locked Loop\r
+// <o1.0..4> MSEL: PLL Multiplier Selection\r
+// <1-32><#-1>\r
+// <i> M Value\r
+// <o1.5..6> PSEL: PLL Divider Selection\r
+// <0=> 1 <1=> 2 <2=> 4 <3=> 8\r
+// <i> P Value\r
+// </e>\r
+*/\r
+ PLL_SETUP EQU 1\r
+ PLLCFG_Val EQU 0x00000024\r
+\r
+\r
+// Memory Accelerator Module (MAM) definitions\r
+ MAM_BASE EQU 0xE01FC000 /* MAM Base Address */\r
+ MAMCR_OFS EQU 0x00 /* MAM Control Offset*/\r
+ MAMTIM_OFS EQU 0x04 /* MAM Timing Offset */\r
+\r
+/*\r
+// <e> MAM Setup\r
+// <i> Memory Accelerator Module\r
+// <o1.0..1> MAM Control\r
+// <0=> Disabled\r
+// <1=> Partially Enabled\r
+// <2=> Fully Enabled\r
+// <i> Mode\r
+// <o2.0..2> MAM Timing\r
+// <0=> Reserved <1=> 1 <2=> 2 <3=> 3\r
+// <4=> 4 <5=> 5 <6=> 6 <7=> 7\r
+// <i> Fetch Cycles\r
+// </e>\r
+*/\r
+ MAM_SETUP EQU 1\r
+ MAMCR_Val EQU 0x00000002\r
+ MAMTIM_Val EQU 0x00000003\r
+\r
+\r
+// External Memory Controller (EMC) definitions\r
+ EMC_BASE EQU 0xFFE00000 /* EMC Base Address */\r
+ BCFG0_OFS EQU 0x00 /* BCFG0 Offset */\r
+ BCFG1_OFS EQU 0x04 /* BCFG1 Offset */\r
+ BCFG2_OFS EQU 0x08 /* BCFG2 Offset */\r
+ BCFG3_OFS EQU 0x0C /* BCFG3 Offset */\r
+\r
+/*\r
+// <e> External Memory Controller (EMC)\r
+*/\r
+ EMC_SETUP EQU 0\r
+\r
+/*\r
+// <e> Bank Configuration 0 (BCFG0)\r
+// <o1.0..3> IDCY: Idle Cycles <0-15>\r
+// <o1.5..9> WST1: Wait States 1 <0-31>\r
+// <o1.11..15> WST2: Wait States 2 <0-31>\r
+// <o1.10> RBLE: Read Byte Lane Enable\r
+// <o1.26> WP: Write Protect\r
+// <o1.27> BM: Burst ROM\r
+// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit\r
+// <2=> 32-bit <3=> Reserved\r
+// </e>\r
+*/\r
+ BCFG0_SETUP EQU 0\r
+ BCFG0_Val EQU 0x0000FBEF\r
+\r
+/*\r
+// <e> Bank Configuration 1 (BCFG1)\r
+// <o1.0..3> IDCY: Idle Cycles <0-15>\r
+// <o1.5..9> WST1: Wait States 1 <0-31>\r
+// <o1.11..15> WST2: Wait States 2 <0-31>\r
+// <o1.10> RBLE: Read Byte Lane Enable\r
+// <o1.26> WP: Write Protect\r
+// <o1.27> BM: Burst ROM\r
+// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit\r
+// <2=> 32-bit <3=> Reserved\r
+// </e>\r
+*/\r
+ BCFG1_SETUP EQU 0\r
+ BCFG1_Val EQU 0x0000FBEF\r
+\r
+/*\r
+// <e> Bank Configuration 0 (BCFG2)\r
+// <o1.0..3> IDCY: Idle Cycles <0-15>\r
+// <o1.5..9> WST1: Wait States 1 <0-31>\r
+// <o1.11..15> WST2: Wait States 2 <0-31>\r
+// <o1.10> RBLE: Read Byte Lane Enable\r
+// <o1.26> WP: Write Protect\r
+// <o1.27> BM: Burst ROM\r
+// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit\r
+// <2=> 32-bit <3=> Reserved\r
+// </e>\r
+*/\r
+ BCFG2_SETUP EQU 0\r
+ BCFG2_Val EQU 0x0000FBEF\r
+\r
+/*\r
+// <e> Bank Configuration 3 (BCFG3)\r
+// <o1.0..3> IDCY: Idle Cycles <0-15>\r
+// <o1.5..9> WST1: Wait States 1 <0-31>\r
+// <o1.11..15> WST2: Wait States 2 <0-31>\r
+// <o1.10> RBLE: Read Byte Lane Enable\r
+// <o1.26> WP: Write Protect\r
+// <o1.27> BM: Burst ROM\r
+// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit\r
+// <2=> 32-bit <3=> Reserved\r
+// </e>\r
+*/\r
+ BCFG3_SETUP EQU 0\r
+ BCFG3_Val EQU 0x0000FBEF\r
+\r
+/*\r
+// </e> End of EMC\r
+*/\r
+\r
+\r
+// External Memory Pins definitions\r
+ PINSEL2 EQU 0xE002C014 /* PINSEL2 Address */\r
+ PINSEL2_Val EQU 0x0E6149E4 /* CS0..3, OE, WE, BLS0..3, \r
+ D0..31, A2..23, JTAG Pins */\r
+\r
+\r
+// Starupt Code must be linked first at Address at which it expects to run.\r
+\r
+$IF (EXTERNAL_MODE)\r
+ CODE_BASE EQU 0x80000000\r
+$ELSE\r
+ CODE_BASE EQU 0x00000000\r
+$ENDIF\r
+\r
+AREA STARTUPCODE, CODE, AT CODE_BASE // READONLY, ALIGN=4\r
+ PUBLIC __startup\r
+\r
+ EXTERN CODE32 (?C?INIT)\r
+\r
+__startup PROC CODE32\r
+\r
+// Pre-defined interrupt handlers that may be directly \r
+// overwritten by C interrupt functions\r
+EXTERN CODE32 (Undef_Handler?A)\r
+EXTERN CODE32 (vPortYieldProcessor?A)\r
+EXTERN CODE32 (PAbt_Handler?A)\r
+EXTERN CODE32 (DAbt_Handler?A)\r
+EXTERN CODE32 (IRQ_Handler?A)\r
+EXTERN CODE32 (FIQ_Handler?A)\r
+\r
+// Exception Vectors\r
+// Mapped to Address 0.\r
+// Absolute addressing mode must be used.\r
+\r
+Vectors: LDR PC,Reset_Addr \r
+ LDR PC,Undef_Addr\r
+ LDR PC,SWI_Addr\r
+ LDR PC,PAbt_Addr\r
+ LDR PC,DAbt_Addr\r
+ NOP /* Reserved Vector */\r
+; LDR PC,IRQ_Addr\r
+ LDR PC,[PC, #-0x0FF0] /* Vector from VicVectAddr */\r
+ LDR PC,FIQ_Addr\r
+\r
+Reset_Addr: DD Reset_Handler\r
+Undef_Addr: DD Undef_Handler?A\r
+SWI_Addr: DD vPortYieldProcessor?A\r
+PAbt_Addr: DD PAbt_Handler?A\r
+DAbt_Addr: DD DAbt_Handler?A\r
+ DD 0 /* Reserved Address */\r
+IRQ_Addr: DD IRQ_Handler?A\r
+FIQ_Addr: DD FIQ_Handler?A\r
+\r
+\r
+// Reset Handler\r
+\r
+Reset_Handler: \r
+\r
+\r
+$IF (EXTERNAL_MODE)\r
+ LDR R0, =PINSEL2\r
+ LDR R1, =PINSEL2_Val\r
+ STR R1, [R0]\r
+$ENDIF\r
+\r
+\r
+IF (EMC_SETUP != 0)\r
+ LDR R0, =EMC_BASE\r
+\r
+IF (BCFG0_SETUP != 0)\r
+ LDR R1, =BCFG0_Val\r
+ STR R1, [R0, #BCFG0_OFS]\r
+ENDIF\r
+\r
+IF (BCFG1_SETUP != 0)\r
+ LDR R1, =BCFG1_Val\r
+ STR R1, [R0, #BCFG1_OFS]\r
+ENDIF\r
+\r
+IF (BCFG2_SETUP != 0)\r
+ LDR R1, =BCFG2_Val\r
+ STR R1, [R0, #BCFG2_OFS]\r
+ENDIF\r
+\r
+IF (BCFG3_SETUP != 0)\r
+ LDR R1, =BCFG3_Val\r
+ STR R1, [R0, #BCFG3_OFS]\r
+ENDIF\r
+\r
+ENDIF\r
+\r
+\r
+IF (PLL_SETUP != 0)\r
+ LDR R0, =PLL_BASE\r
+ MOV R1, #0xAA\r
+ MOV R2, #0x55\r
+\r
+// Configure and Enable PLL\r
+ MOV R3, #PLLCFG_Val\r
+ STR R3, [R0, #PLLCFG_OFS] \r
+ MOV R3, #PLLCON_PLLE\r
+ STR R3, [R0, #PLLCON_OFS]\r
+ STR R1, [R0, #PLLFEED_OFS]\r
+ STR R2, [R0, #PLLFEED_OFS]\r
+\r
+// Wait until PLL Locked\r
+PLL_Loop: LDR R3, [R0, #PLLSTAT_OFS]\r
+ ANDS R3, R3, #PLLSTAT_PLOCK\r
+ BEQ PLL_Loop\r
+\r
+// Switch to PLL Clock\r
+ MOV R3, #(PLLCON_PLLE | PLLCON_PLLC)\r
+ STR R3, [R0, #PLLCON_OFS]\r
+ STR R1, [R0, #PLLFEED_OFS]\r
+ STR R2, [R0, #PLLFEED_OFS]\r
+ENDIF\r
+\r
+\r
+IF (MAM_SETUP != 0)\r
+ LDR R0, =MAM_BASE\r
+ MOV R1, #MAMTIM_Val\r
+ STR R1, [R0, #MAMTIM_OFS] \r
+ MOV R1, #MAMCR_Val\r
+ STR R1, [R0, #MAMCR_OFS] \r
+ENDIF\r
+\r
+\r
+// Memory Mapping (when Interrupt Vectors are in RAM)\r
+ MEMMAP EQU 0xE01FC040 /* Memory Mapping Control */\r
+\r
+$IF (RAM_INTVEC)\r
+ LDR R0, =MEMMAP\r
+ MOV R1, #2\r
+ STR R1, [R0]\r
+$ENDIF\r
+\r
+\r
+// Setup Stack for each mode\r
+ LDR R0, =Top_Stack\r
+\r
+// Enter Undefined Instruction Mode and set its Stack Pointer\r
+ MSR CPSR_c, #Mode_UND|I_Bit|F_Bit\r
+ MOV SP, R0\r
+ SUB R0, R0, #UND_Stack_Size\r
+\r
+// Enter Abort Mode and set its Stack Pointer\r
+ MSR CPSR_c, #Mode_ABT|I_Bit|F_Bit\r
+ MOV SP, R0\r
+ SUB R0, R0, #ABT_Stack_Size\r
+\r
+// Enter FIQ Mode and set its Stack Pointer\r
+ MSR CPSR_c, #Mode_FIQ|I_Bit|F_Bit\r
+ MOV SP, R0\r
+ SUB R0, R0, #FIQ_Stack_Size\r
+\r
+// Enter IRQ Mode and set its Stack Pointer\r
+ MSR CPSR_c, #Mode_IRQ|I_Bit|F_Bit\r
+ MOV SP, R0\r
+ SUB R0, R0, #IRQ_Stack_Size\r
+\r
+// Enter Supervisor Mode and set its Stack Pointer\r
+ MSR CPSR_c, #Mode_SVC|I_Bit|F_Bit\r
+ MOV SP, R0\r
+ SUB R0, R0, #SVC_Stack_Size\r
+\r
+// Enter S Mode and set its Stack Pointer\r
+ MSR CPSR_c, #Mode_SYS\r
+ MOV SP, R0\r
+\r
+// Start in supervisor mode\r
+ MSR CPSR_c, #Mode_SVC|I_Bit|F_Bit\r
+\r
+// Enter the C code\r
+ LDR R0,=?C?INIT\r
+ TST R0,#1 ; Bit-0 set: INIT is Thumb\r
+ LDREQ LR,=exit?A ; ARM Mode\r
+ LDRNE LR,=exit?T ; Thumb Mode\r
+ BX R0\r
+ ENDP\r
+\r
+PUBLIC exit?A\r
+exit?A PROC CODE32\r
+ B exit?A\r
+ ENDP\r
+\r
+PUBLIC exit?T\r
+exit?T PROC CODE16\r
+exit: B exit?T\r
+ ENDP\r
+\r
+\r
+ END\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* \r
+ NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.\r
+ The processor MUST be in supervisor mode when vTaskStartScheduler is \r
+ called. The demo applications included in the FreeRTOS.org download switch\r
+ to supervisor mode prior to main being called. If you are not using one of\r
+ these demo application projects then ensure Supervisor mode is used.\r
+*/\r
+\r
+\r
+/*\r
+ * Creates all the demo application tasks, then starts the scheduler. The WEB\r
+ * documentation provides more details of the demo application tasks.\r
+ * \r
+ * Main.c also creates a task called "Check". This only executes every three \r
+ * seconds but has the highest priority so is guaranteed to get processor time. \r
+ * Its main function is to check that all the other tasks are still operational.\r
+ * Each task (other than the "flash" tasks) maintains a unique count that is \r
+ * incremented each time the task successfully completes its function. Should \r
+ * any error occur within such a task the count is permanently halted. The \r
+ * check task inspects the count of each task to ensure it has changed since\r
+ * the last time the check task executed. If all the count variables have \r
+ * changed all the tasks are still executing error free, and the check task\r
+ * toggles the onboard LED. Should any task contain an error at any time \r
+ * the LED toggle rate will change from 3 seconds to 500ms.\r
+ *\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdlib.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo application includes. */\r
+#include "partest.h"\r
+#include "flash.h"\r
+#include "integer.h"\r
+#include "comtest2.h"\r
+#include "serial.h"\r
+\r
+#ifdef KEIL_THUMB_INTERWORK\r
+ /* \r
+ THUMB mode allows more tasks to be created without the executable \r
+ binary exceeding the limits allowed by the evaluation version of \r
+ uVision3.\r
+ */\r
+ #include "PollQ.h"\r
+ #include "BlockQ.h"\r
+ #include "semtest.h"\r
+ #include "dynamic.h"\r
+\r
+#endif\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Constants to setup I/O and processor. */\r
+#define mainTX_ENABLE ( ( unsigned portLONG ) 0x0001 )\r
+#define mainRX_ENABLE ( ( unsigned portLONG ) 0x0004 )\r
+#define mainBUS_CLK_FULL ( ( unsigned portCHAR ) 0x01 )\r
+#define mainLED_TO_OUTPUT ( ( unsigned portLONG ) 0xff0000 )\r
+\r
+/* Constants for the ComTest demo application tasks. */\r
+#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 115200 )\r
+#define mainCOM_TEST_LED ( 3 )\r
+\r
+/* Priorities for the demo application tasks. */\r
+#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 )\r
+\r
+/* Constants used by the "check" task. As described at the head of this file\r
+the check task toggles an LED. The rate at which the LED flashes is used to\r
+indicate whether an error has been detected or not. If the LED toggles every\r
+3 seconds then no errors have been detected. If the rate increases to 500ms\r
+then an error has been detected in at least one of the demo application tasks. */\r
+#define mainCHECK_LED ( 7 )\r
+#define mainNO_ERROR_FLASH_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS )\r
+#define mainERROR_FLASH_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Checks that all the demo application tasks are still executing without error\r
+ * - as described at the top of the file.\r
+ */\r
+static portLONG prvCheckOtherTasksAreStillRunning( void );\r
+\r
+/*\r
+ * The task that executes at the highest priority and calls \r
+ * prvCheckOtherTasksAreStillRunning(). See the description at the top\r
+ * of the file.\r
+ */\r
+static void vErrorChecks( void *pvParameters );\r
+\r
+/*\r
+ * Configure the processor for use with the Keil demo board. This is very\r
+ * minimal as most of the setup is managed by the settings in the project\r
+ * file.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+\r
+/*\r
+ * Application entry point:\r
+ * Starts all the other tasks, then starts the scheduler. \r
+ */\r
+int main( void )\r
+{\r
+ /* Setup the hardware for use with the Keil demo board. */\r
+ prvSetupHardware();\r
+\r
+ /* Start the demo/test application tasks. */\r
+ vStartIntegerMathTasks( tskIDLE_PRIORITY );\r
+ vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED );\r
+ vStartLEDFlashTasks( mainLED_TASK_PRIORITY );\r
+\r
+ #ifdef KEIL_THUMB_INTERWORK\r
+ /* When using THUMB mode we can start more tasks without the executable\r
+ exceeding the size limit imposed by the evaluation version of uVision3. */\r
+ vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
+ vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
+ vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
+ vStartDynamicPriorityTasks();\r
+ #endif\r
+\r
+ /* Start the check task - which is defined in this file. This is the task\r
+ that periodically checks to see that all the other tasks are executing \r
+ without error. */\r
+ xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
+\r
+ /* Now all the tasks have been started - start the scheduler.\r
+\r
+ NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.\r
+ The processor MUST be in supervisor mode when vTaskStartScheduler is \r
+ called. The demo applications included in the FreeRTOS.org download switch\r
+ to supervisor mode prior to main being called. If you are not using one of\r
+ these demo application projects then ensure Supervisor mode is used here. */\r
+ vTaskStartScheduler();\r
+\r
+ /* Should never reach here! */\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vErrorChecks( void *pvParameters )\r
+{\r
+portTickType xDelayPeriod = mainNO_ERROR_FLASH_PERIOD;\r
+\r
+ /* Parameters are not used. */\r
+ ( void ) pvParameters;\r
+\r
+ /* Cycle for ever, delaying then checking all the other tasks are still\r
+ operating without error. If an error is detected then the delay period\r
+ is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so\r
+ the on board LED flash rate will increase.\r
+\r
+ This task runs at the highest priority. */\r
+\r
+ for( ;; )\r
+ {\r
+ /* The period of the delay depends on whether an error has been \r
+ detected or not. If an error has been detected then the period\r
+ is reduced to increase the LED flash rate. */\r
+ vTaskDelay( xDelayPeriod );\r
+\r
+ if( prvCheckOtherTasksAreStillRunning() != pdPASS )\r
+ {\r
+ /* An error has been detected in one of the tasks - flash faster. */\r
+ xDelayPeriod = mainERROR_FLASH_PERIOD;\r
+ }\r
+\r
+ /* Toggle the LED before going back to wait for the next cycle. */\r
+ vParTestToggleLED( mainCHECK_LED );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+ /* Perform the hardware setup required. This is minimal as most of the\r
+ setup is managed by the settings in the project file. */\r
+\r
+ /* Configure the RS2332 pins. All other pins remain at their default of 0. */\r
+ PINSEL0 |= mainTX_ENABLE;\r
+ PINSEL0 |= mainRX_ENABLE;\r
+\r
+ /* LED pins need to be output. */\r
+ IODIR1 = mainLED_TO_OUTPUT;\r
+\r
+ /* Setup the peripheral bus to be the same as the PLL output. */\r
+ VPBDIV = mainBUS_CLK_FULL;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portLONG prvCheckOtherTasksAreStillRunning( void )\r
+{\r
+portLONG lReturn = pdPASS;\r
+\r
+ /* Check all the demo tasks (other than the flash tasks) to ensure\r
+ that they are all still running, and that none of them have detected\r
+ an error. */\r
+ if( xAreIntegerMathsTaskStillRunning() != pdPASS )\r
+ {\r
+ lReturn = pdFAIL;\r
+ }\r
+\r
+ if( xAreComTestTasksStillRunning() != pdPASS )\r
+ {\r
+ lReturn = pdFAIL;\r
+ }\r
+\r
+ #ifdef KEIL_THUMB_INTERWORK\r
+\r
+ /* When using THUMB mode we can start more tasks without the executable\r
+ exceeding the size limit imposed by the evaluation version of uVision3. */\r
+ \r
+ if( xArePollingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ lReturn = pdFAIL;\r
+ }\r
+ \r
+ if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ lReturn = pdFAIL;\r
+ }\r
+ \r
+ if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ lReturn = pdFAIL;\r
+ }\r
+\r
+ if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )\r
+ {\r
+ lReturn = pdFAIL;\r
+ }\r
+\r
+ #endif\r
+\r
+ return lReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
--- /dev/null
+### uVision2 Project, (C) Keil Software\r
+### Do not modify !\r
+\r
+ cExt (*.c)\r
+ aExt (*.s*; *.src; *.a*)\r
+ oExt (*.obj)\r
+ lExt (*.lib)\r
+ tExt (*.txt; *.h; *.inc)\r
+ pExt (*.plm)\r
+ CppX (*.cpp)\r
+ DaveTm { 0,0,0,0,0,0,0,0 }\r
+\r
+Target (FreeRTOS), 0x0005 // Tools: ''\r
+GRPOPT 1,(ARM_DEMO),1,0,0\r
+\r
+OPTFFF 1,1,1,2,0,127,137,0,<.\main.c><main.c> { 44,0,0,0,2,0,0,0,3,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,228,255,255,255,27,0,0,0,27,0,0,0,41,4,0,0,102,2,0,0 }\r
+OPTFFF 1,2,2,0,0,0,0,0,<.\Startup.s><Startup.s> \r
+OPTFFF 1,3,1,0,0,0,0,0,<.\ParTest\ParTest.c><ParTest.c> \r
+OPTFFF 1,4,1,0,0,0,0,0,<.\serial\serial.c><serial.c> \r
+OPTFFF 1,5,1,0,0,0,0,0,<.\serial\serialISR.c><serialISR.c> \r
+OPTFFF 1,6,1,0,0,0,0,0,<..\..\Source\tasks.c><tasks.c> \r
+OPTFFF 1,7,1,0,0,0,0,0,<..\..\Source\queue.c><queue.c> \r
+OPTFFF 1,8,1,0,0,0,0,0,<..\..\Source\list.c><list.c> \r
+OPTFFF 1,9,1,0,0,0,0,0,<..\..\Source\portable\Keil\ARM7\port.c><port.c> \r
+OPTFFF 1,10,1,0,0,0,0,0,<..\..\Source\portable\Keil\ARM7\portISR.c><portISR.c> \r
+OPTFFF 1,11,1,0,0,0,0,0,<..\Common\Minimal\flash.c><flash.c> \r
+OPTFFF 1,12,1,16777216,0,0,0,0,<..\Common\Minimal\comtest.c><comtest.c> \r
+OPTFFF 1,13,1,0,0,0,0,0,<..\Common\Minimal\integer.c><integer.c> \r
+OPTFFF 1,14,1,0,0,0,0,0,<..\..\Source\portable\MemMang\heap_2.c><heap_2.c> \r
+\r
+\r
+TARGOPT 1, (FreeRTOS)\r
+ KACLK=12000000\r
+ OPTTT 1,1,1,0\r
+ OPTHX 0,65535,0,0,0\r
+ OPTLX 120,65,8,<.\>\r
+ OPTOX 16\r
+ OPTLT 1,1,1,0,1,1,0,1,0,0,0,0\r
+ OPTXL 1,1,1,1,1,1,1,0,0\r
+ OPTFL 1,0,1\r
+ OPTBL 0,(Data Sheet)<DATASHTS\PHILIPS\LPC2119_2129.PDF>\r
+ OPTBL 1,(User Manual)<DATASHTS\PHILIPS\UM_LPC21XX_LPC22XX.PDF>\r
+ OPTDL (SARM.DLL)(-cLPC2100)(DARMP.DLL)(-pLPC21x9)(SARM.DLL)()(TARMP.DLL)(-pLPC21x9)\r
+ OPTDBG 44029,-1,()()()()()()()()()() (BIN\UL2ARM.DLL)()()()\r
+ OPTKEY 0,(DLGTARM)((134=-1,-1,-1,-1,0)(135=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)(108=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(80=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(113=-1,-1,-1,-1,0)(112=-1,-1,-1,-1,0)(136=-1,-1,-1,-1,0)(117=-1,-1,-1,-1,0)(118=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(114=-1,-1,-1,-1,0)(119=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(115=-1,-1,-1,-1,0)(116=-1,-1,-1,-1,0))\r
+ OPTKEY 0,(UL2ARM)(-U174073036 -O7 -S0 -C0 -N00("ARM7TDMI-S Core") -D00(4F1F0F0F) -L00(4) -FO7 -FD40000000 -FC800 -FN1 -FF0LPC_IAP_256 -FS00 -FL03E000)\r
+ OPTKEY 0,(DLGDARM)((134=-1,-1,-1,-1,0)(135=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)(108=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(80=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(113=-1,-1,-1,-1,0)(112=-1,-1,-1,-1,0)(136=-1,-1,-1,-1,0)(117=-1,-1,-1,-1,0)(118=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(114=-1,-1,-1,-1,0)(119=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(115=-1,-1,-1,-1,0)(116=-1,-1,-1,-1,0))\r
+ OPTKEY 0,(ARMDBGFLAGS)(-T5F)\r
+ OPTMM 1,0,(0x40001800)\r
+ OPTDF 0x1000080\r
+ OPTLE <>\r
+ OPTLC <>\r
+ OPTLA 0,((Port1 & 0x10000) >> 16)(FF00FF000000000000000000000000000000F0BF010000006400000000E8764817000000506F72743100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000020370000)\r
+ OPTLA 1,((Port1 & 0x20000) >> 17)(FF0000000000000000000000000000000000F0BF010000006400000000E8764817000000506F72743100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000020370000)\r
+ OPTLA 2,((Port1 & 0x40000) >> 18)(008000000000000000000000000000000000F0BF010000006400000000E8764817000000506F72743100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000020370000)\r
+ OPTLA 3,((Port1 & 0x80000) >> 19)(0000FF000000000000000000000000000000F0BF010000006400000000E8764817000000506F72743100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000020370000)\r
+EndOpt\r
+\r
--- /dev/null
+### uVision2 Project, (C) Keil Software\r
+### Do not modify !\r
+\r
+Target (FreeRTOS), 0x0005 // Tools: ''\r
+\r
+Group (ARM_DEMO)\r
+\r
+File 1,1,<.\main.c><main.c> 0x4162D96A \r
+File 1,2,<.\Startup.s><Startup.s> 0x415AF382 \r
+File 1,1,<.\ParTest\ParTest.c><ParTest.c> 0x415AF50E \r
+File 1,1,<.\serial\serial.c><serial.c> 0x4162D488 \r
+File 1,1,<.\serial\serialISR.c><serialISR.c> 0x4162D404 \r
+File 1,1,<..\..\Source\tasks.c><tasks.c> 0x4162D9E6 \r
+File 1,1,<..\..\Source\queue.c><queue.c> 0x411B5F14 \r
+File 1,1,<..\..\Source\list.c><list.c> 0x411B5F24 \r
+File 1,1,<..\..\Source\portable\Keil\ARM7\port.c><port.c> 0x4162D434 \r
+File 1,1,<..\..\Source\portable\Keil\ARM7\portISR.c><portISR.c> 0x415A85E0 \r
+File 1,1,<..\Common\Minimal\flash.c><flash.c> 0x411B5F8E \r
+File 1,1,<..\Common\Minimal\comtest.c><comtest.c> 0x413335E6 \r
+File 1,1,<..\Common\Minimal\integer.c><integer.c> 0x415FB7EE \r
+File 1,1,<..\..\Source\portable\MemMang\heap_2.c><heap_2.c> 0x0 \r
+\r
+\r
+Options 1,0,0 // Target 'FreeRTOS'\r
+ Device (LPC2129)\r
+ Vendor (Philips)\r
+ Cpu (IRAM(0x40000000-0x40003FFF) IROM(0-0x3FFFF) CLOCK(12000000) CPUTYPE(ARM7TDMI))\r
+ FlashUt (LPC210x_ISP.EXE ("#H" ^X $D COM1: 9600 1))\r
+ StupF ("STARTUP\Philips\Startup.s" ("Philips LPC2100 Startup Code"))\r
+ FlashDR (UL2ARM(-U40296420 -O7 -C0 -FO7 -FD40000000 -FC800 -FN1 -FF0LPC_IAP_256 -FS00 -FL03E000))\r
+ Rgf (LPC21xx.H)\r
+ Mem ()\r
+ C ()\r
+ A ()\r
+ RL ()\r
+ OH ()\r
+ DBC_IFX ()\r
+ DBC_CMS ()\r
+ DBC_AMS ()\r
+ DBC_LMS ()\r
+ UseEnv=0\r
+ EnvBin (D:\DevTools\Keil\arm\ARM\BIN\)\r
+ EnvInc ()\r
+ EnvLib ()\r
+ EnvReg (ÿPhilips\)\r
+ OrgReg (ÿPhilips\)\r
+ TgStat=16\r
+ OutDir (.\)\r
+ OutName (rtosdemo_ARM)\r
+ GenApp=1\r
+ GenLib=0\r
+ GenHex=0\r
+ Debug=1\r
+ Browse=0\r
+ LstDir (.\)\r
+ HexSel=0\r
+ MG32K=0\r
+ TGMORE=0\r
+ RunUsr 0 0 <>\r
+ RunUsr 1 0 <>\r
+ BrunUsr 0 0 <>\r
+ BrunUsr 1 0 <>\r
+ SVCSID <>\r
+ KACPU (ARM7TDMI)\r
+ TKAFL { 0,27,183,0,0,15,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ KIROM { 1,0,0,0,0,0,0,4,0 }\r
+ KIRAM { 0,0,0,0,64,0,64,0,0 }\r
+ KXRAM { 0,0,0,0,0,0,0,0,0 }\r
+ KAOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ KCAFLG { 197,132,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ KCAMSC (INTERWORK)\r
+ KCADEF (KEIL_ARM7)\r
+ KCAUDF ()\r
+ KCAINC (..\Common\include\;..\..\Source\include\;..\..\Source\portable\Keil\ARM7\)\r
+ KAAFLG { 20,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ KAAMSC ()\r
+ KAASET ()\r
+ KAARST ()\r
+ KAAINC ()\r
+ PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ IncBld=1\r
+ AlwaysBuild=0\r
+ GenAsm=0\r
+ AsmAsm=0\r
+ PublicsOnly=0\r
+ StopCode=3\r
+ CustArgs ()\r
+ LibMods ()\r
+ KLAFLG { 44,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ KLAMSC ()\r
+ KLADWN (25)\r
+ KLACFI ()\r
+ KLAASN ()\r
+ KLARES ()\r
+ KLACCL ()\r
+ KLAUCL ()\r
+ KLACSC ()\r
+ KLAUCS ()\r
+ OPTDL (SARM.DLL)(-cLPC2100)(DARMP.DLL)(-pLPC21x9)(SARM.DLL)()(TARMP.DLL)(-pLPC21x9)\r
+ OPTDBG 44029,-1,()()()()()()()()()() (BIN\UL2ARM.DLL)()()()\r
+ FLASH1 { 1,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ FLASH2 (BIN\UL2ARM.DLL)\r
+ FLASH3 ("LPC210x_ISP.EXE" ("#H" ^X $D COM1: 9600 1))\r
+ FLASH4 ()\r
+EndOpt\r
+\r
--- /dev/null
+### uVision2 Project, (C) Keil Software\r
+### Do not modify !\r
+\r
+ cExt (*.c)\r
+ aExt (*.s*; *.src; *.a*)\r
+ oExt (*.obj)\r
+ lExt (*.lib)\r
+ tExt (*.txt; *.h; *.inc)\r
+ pExt (*.plm)\r
+ CppX (*.cpp)\r
+ DaveTm { 0,0,0,0,0,0,0,0 }\r
+\r
+Target (FreeRTOS), 0x0005 // Tools: ''\r
+GRPOPT 1,(THUMB_DEMO),1,0,0\r
+\r
+OPTFFF 1,1,1,1,0,121,137,0,<.\main.c><main.c> { 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,228,255,255,255,0,0,0,0,0,0,0,0,14,4,0,0,75,2,0,0 }\r
+OPTFFF 1,2,2,0,0,0,0,0,<.\Startup.s><Startup.s> \r
+OPTFFF 1,3,1,1040187392,0,0,0,0,<.\ParTest\ParTest.c><ParTest.c> \r
+OPTFFF 1,4,1,0,0,0,0,0,<.\serial\serial.c><serial.c> \r
+OPTFFF 1,5,1,0,0,0,0,0,<.\serial\serialISR.c><serialISR.c> \r
+OPTFFF 1,6,1,0,0,0,0,0,<..\..\Source\tasks.c><tasks.c> \r
+OPTFFF 1,7,1,0,0,0,0,0,<..\..\Source\queue.c><queue.c> \r
+OPTFFF 1,8,1,0,0,0,0,0,<..\..\Source\list.c><list.c> \r
+OPTFFF 1,9,1,553648128,0,0,0,0,<..\..\Source\portable\Keil\ARM7\port.c><port.c> \r
+OPTFFF 1,10,1,0,0,0,0,0,<..\..\Source\portable\Keil\ARM7\portISR.c><portISR.c> \r
+OPTFFF 1,11,1,0,0,0,0,0,<..\Common\Minimal\BlockQ.c><BlockQ.c> \r
+OPTFFF 1,12,1,402653184,0,0,0,0,<..\Common\Minimal\semtest.c><semtest.c> \r
+OPTFFF 1,13,1,0,0,0,0,0,<..\Common\Minimal\PollQ.c><PollQ.c> \r
+OPTFFF 1,14,1,0,0,0,0,0,<..\Common\Minimal\flash.c><flash.c> \r
+OPTFFF 1,15,1,0,0,0,0,0,<..\Common\Minimal\comtest.c><comtest.c> \r
+OPTFFF 1,16,1,0,0,0,0,0,<..\Common\Minimal\integer.c><integer.c> \r
+OPTFFF 1,17,1,0,0,0,0,0,<..\..\Source\portable\MemMang\heap_2.c><heap_2.c> \r
+OPTFFF 1,18,1,0,0,0,0,0,<..\Common\Minimal\dynamic.c><dynamic.c> \r
+\r
+ExtF <..\..\SOURCE\PORTABLE\KEIL\ARM7\PORTMACRO.H> 127,127,0,{ 44,0,0,0,2,0,0,0,3,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,228,255,255,255,27,0,0,0,27,0,0,0,72,4,0,0,33,2,0,0 }\r
+\r
+TARGOPT 1, (FreeRTOS)\r
+ KACLK=12000000\r
+ OPTTT 1,1,1,0\r
+ OPTHX 0,65535,0,0,0\r
+ OPTLX 120,65,8,<.\>\r
+ OPTOX 16\r
+ OPTLT 1,1,1,0,1,1,0,1,0,0,0,0\r
+ OPTXL 1,1,1,1,1,1,1,0,0\r
+ OPTFL 1,0,1\r
+ OPTBL 0,(Data Sheet)<DATASHTS\PHILIPS\LPC2119_2129.PDF>\r
+ OPTBL 1,(User Manual)<DATASHTS\PHILIPS\UM_LPC21XX_LPC22XX.PDF>\r
+ OPTDL (SARM.DLL)(-cLPC2100)(DARMP.DLL)(-pLPC21x9)(SARM.DLL)()(TARMP.DLL)(-pLPC21x9)\r
+ OPTDBG 44029,-1,()()()()()()()()()() (BIN\UL2ARM.DLL)()()()\r
+ OPTKEY 0,(DLGTARM)((134=-1,-1,-1,-1,0)(135=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)(108=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(80=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(113=-1,-1,-1,-1,0)(112=-1,-1,-1,-1,0)(136=-1,-1,-1,-1,0)(117=-1,-1,-1,-1,0)(118=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(114=-1,-1,-1,-1,0)(119=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(115=-1,-1,-1,-1,0)(116=-1,-1,-1,-1,0))\r
+ OPTKEY 0,(UL2ARM)(-U170927308 -O7 -S0 -C0 -N00("ARM7TDMI-S Core") -D00(4F1F0F0F) -L00(4) -FO7 -FD40000000 -FC800 -FN1 -FF0LPC_IAP_256 -FS00 -FL03E000)\r
+ OPTKEY 0,(DLGDARM)((134=-1,-1,-1,-1,0)(135=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)(108=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(80=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(113=-1,-1,-1,-1,0)(112=-1,-1,-1,-1,0)(136=-1,-1,-1,-1,0)(117=-1,-1,-1,-1,0)(118=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(114=-1,-1,-1,-1,0)(119=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(115=-1,-1,-1,-1,0)(116=-1,-1,-1,-1,0))\r
+ OPTKEY 0,(ARMDBGFLAGS)(-T5F)\r
+ OPTMM 1,0,(0x40000840)\r
+ OPTDF 0x1000086\r
+ OPTLE <>\r
+ OPTLC <>\r
+ OPTLA 0,((Port1 & 0x10000) >> 16)(0000FF000000000000000000000000000000F0BF010000006400000000743BA40B000000506F7274310000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000001C030000)\r
+ OPTLA 1,((Port1 & 0x20000) >> 17)(0000FF000000000000000000000000000000F0BF010000006400000000743BA40B000000506F7274310000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000001C030000)\r
+ OPTLA 2,((Port1 & 0x40000) >> 18)(0000FF000000000000000000000000000000F0BF010000006400000000743BA40B000000506F7274310000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000001C030000)\r
+ OPTLA 3,((Port1 & 0x80000) >> 19)(0000FF000000000000000000000000000000F0BF010000006400000000743BA40B000000506F7274310000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000001C030000)\r
+EndOpt\r
+\r
--- /dev/null
+### uVision2 Project, (C) Keil Software\r
+### Do not modify !\r
+\r
+Target (FreeRTOS), 0x0005 // Tools: ''\r
+\r
+Group (THUMB_DEMO)\r
+\r
+File 1,1,<.\main.c><main.c> 0x4162D96A \r
+File 1,2,<.\Startup.s><Startup.s> 0x415AF382 \r
+File 1,1,<.\ParTest\ParTest.c><ParTest.c> 0x415AF50E \r
+File 1,1,<.\serial\serial.c><serial.c> 0x4162D488 \r
+File 1,1,<.\serial\serialISR.c><serialISR.c> 0x4162D404 \r
+File 1,1,<..\..\Source\tasks.c><tasks.c> 0x4162D9E6 \r
+File 1,1,<..\..\Source\queue.c><queue.c> 0x411B5F14 \r
+File 1,1,<..\..\Source\list.c><list.c> 0x411B5F24 \r
+File 1,1,<..\..\Source\portable\Keil\ARM7\port.c><port.c> 0x4162D434 \r
+File 1,1,<..\..\Source\portable\Keil\ARM7\portISR.c><portISR.c> 0x415A85E0 \r
+File 1,1,<..\Common\Minimal\BlockQ.c><BlockQ.c> 0x411B5F8C \r
+File 1,1,<..\Common\Minimal\semtest.c><semtest.c> 0x411B5F8C \r
+File 1,1,<..\Common\Minimal\PollQ.c><PollQ.c> 0x411B5F8E \r
+File 1,1,<..\Common\Minimal\flash.c><flash.c> 0x411B5F8E \r
+File 1,1,<..\Common\Minimal\comtest.c><comtest.c> 0x413335E6 \r
+File 1,1,<..\Common\Minimal\integer.c><integer.c> 0x415FB7EE \r
+File 1,1,<..\..\Source\portable\MemMang\heap_2.c><heap_2.c> 0x0 \r
+File 1,1,<..\Common\Minimal\dynamic.c><dynamic.c> 0x0 \r
+\r
+\r
+Options 1,0,0 // Target 'FreeRTOS'\r
+ Device (LPC2129)\r
+ Vendor (Philips)\r
+ Cpu (IRAM(0x40000000-0x40003FFF) IROM(0-0x3FFFF) CLOCK(12000000) CPUTYPE(ARM7TDMI))\r
+ FlashUt (LPC210x_ISP.EXE ("#H" ^X $D COM1: 9600 1))\r
+ StupF ("STARTUP\Philips\Startup.s" ("Philips LPC2100 Startup Code"))\r
+ FlashDR (UL2ARM(-U40296420 -O7 -C0 -FO7 -FD40000000 -FC800 -FN1 -FF0LPC_IAP_256 -FS00 -FL03E000))\r
+ Rgf (LPC21xx.H)\r
+ Mem ()\r
+ C ()\r
+ A ()\r
+ RL ()\r
+ OH ()\r
+ DBC_IFX ()\r
+ DBC_CMS ()\r
+ DBC_AMS ()\r
+ DBC_LMS ()\r
+ UseEnv=0\r
+ EnvBin (D:\DevTools\Keil\arm\ARM\BIN\)\r
+ EnvInc ()\r
+ EnvLib ()\r
+ EnvReg (ÿPhilips\)\r
+ OrgReg (ÿPhilips\)\r
+ TgStat=16\r
+ OutDir (.\)\r
+ OutName (rtosdemo_THUMB)\r
+ GenApp=1\r
+ GenLib=0\r
+ GenHex=0\r
+ Debug=1\r
+ Browse=0\r
+ LstDir (.\)\r
+ HexSel=0\r
+ MG32K=0\r
+ TGMORE=0\r
+ RunUsr 0 0 <>\r
+ RunUsr 1 0 <>\r
+ BrunUsr 0 0 <>\r
+ BrunUsr 1 0 <>\r
+ SVCSID <>\r
+ KACPU (ARM7TDMI)\r
+ TKAFL { 0,27,183,0,0,15,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ KIROM { 1,0,0,0,0,0,0,4,0 }\r
+ KIRAM { 0,0,0,0,64,0,64,0,0 }\r
+ KXRAM { 0,0,0,0,0,0,0,0,0 }\r
+ KAOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ KCAFLG { 197,156,20,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ KCAMSC (INTERWORK)\r
+ KCADEF (KEIL_ARM7 KEIL_THUMB_INTERWORK)\r
+ KCAUDF ()\r
+ KCAINC (..\Common\include\;..\..\Source\include\;..\..\Source\portable\Keil\ARM7\)\r
+ KAAFLG { 20,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ KAAMSC ()\r
+ KAASET ()\r
+ KAARST ()\r
+ KAAINC ()\r
+ PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ IncBld=1\r
+ AlwaysBuild=0\r
+ GenAsm=0\r
+ AsmAsm=0\r
+ PublicsOnly=0\r
+ StopCode=3\r
+ CustArgs ()\r
+ LibMods ()\r
+ KLAFLG { 44,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ KLAMSC ()\r
+ KLADWN (25)\r
+ KLACFI ()\r
+ KLAASN ()\r
+ KLARES ()\r
+ KLACCL ()\r
+ KLAUCL ()\r
+ KLACSC ()\r
+ KLAUCS ()\r
+ OPTDL (SARM.DLL)(-cLPC2100)(DARMP.DLL)(-pLPC21x9)(SARM.DLL)()(TARMP.DLL)(-pLPC21x9)\r
+ OPTDBG 44029,-1,()()()()()()()()()() (BIN\UL2ARM.DLL)()()()\r
+ FLASH1 { 1,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ FLASH2 (BIN\UL2ARM.DLL)\r
+ FLASH3 ("LPC210x_ISP.EXE" ("#H" ^X $D COM1: 9600 1))\r
+ FLASH4 ()\r
+EndOpt\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+\r
+/* \r
+ BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0. \r
+\r
+ This file contains all the serial port components that can be compiled to\r
+ either ARM or THUMB mode. Components that must be compiled to ARM mode are\r
+ contained in serialISR.c.\r
+*/\r
+\r
+/* Standard includes. */\r
+#include <stdlib.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "queue.h"\r
+#include "task.h"\r
+\r
+/* Demo application includes. */\r
+#include "serial.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Constants to setup and access the UART. */\r
+#define serDLAB ( ( unsigned portCHAR ) 0x80 )\r
+#define serENABLE_INTERRUPTS ( ( unsigned portCHAR ) 0x03 )\r
+#define serNO_PARITY ( ( unsigned portCHAR ) 0x00 )\r
+#define ser1_STOP_BIT ( ( unsigned portCHAR ) 0x00 )\r
+#define ser8_BIT_CHARS ( ( unsigned portCHAR ) 0x03 )\r
+#define serFIFO_ON ( ( unsigned portCHAR ) 0x01 )\r
+#define serCLEAR_FIFO ( ( unsigned portCHAR ) 0x06 )\r
+#define serWANTED_CLOCK_SCALING ( ( unsigned portLONG ) 16 )\r
+\r
+/* Constants to setup and access the VIC. */\r
+#define serU0VIC_CHANNEL ( ( unsigned portLONG ) 0x0006 )\r
+#define serU0VIC_CHANNEL_BIT ( ( unsigned portLONG ) 0x0040 )\r
+#define serU0VIC_ENABLE ( ( unsigned portLONG ) 0x0020 )\r
+\r
+/* Misc. */\r
+#define serINVALID_QUEUE ( ( xQueueHandle ) 0 )\r
+#define serHANDLE ( ( xComPortHandle ) 1 )\r
+#define serNO_BLOCK ( ( portTickType ) 0 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Queues used to hold received characters, and characters waiting to be\r
+transmitted. */\r
+static xQueueHandle xRxedChars; \r
+static xQueueHandle xCharsForTx; \r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Communication flag between the interrupt service routine and serial API. */\r
+static volatile portLONG *plTHREEmpty;\r
+\r
+/* \r
+ * The queues are created in serialISR.c as they are used from the ISR.\r
+ * Obtain references to the queues and THRE Empty flag. \r
+ */\r
+extern void vSerialISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxRxedChars, xQueueHandle *pxCharsForTx, portLONG volatile **pplTHREEmptyFlag );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )\r
+{\r
+unsigned portLONG ulDivisor, ulWantedClock;\r
+xComPortHandle xReturn = serHANDLE;\r
+\r
+ /* The queues are used in the serial ISR routine, so are created from\r
+ serialISR.c (which is always compiled to ARM mode). */\r
+ vSerialISRCreateQueues( uxQueueLength, &xRxedChars, &xCharsForTx, &plTHREEmpty );\r
+\r
+ if( \r
+ ( xRxedChars != serINVALID_QUEUE ) && \r
+ ( xCharsForTx != serINVALID_QUEUE ) && \r
+ ( ulWantedBaud != ( unsigned portLONG ) 0 ) \r
+ )\r
+ {\r
+ portENTER_CRITICAL();\r
+ {\r
+ /* The reference to the ISR function is required to load into the \r
+ interrupt controller. The prototype is slightly different \r
+ depending on whether in ARM or THUMB mode. */\r
+ #ifdef KEIL_THUMB_INTERWORK\r
+ extern void ( vUART_ISR )( void ) __arm __task;\r
+ #else\r
+ extern void ( vUART_ISR )( void ) __task;\r
+ #endif\r
+\r
+ /* Setup the baud rate: Calculate the divisor value. */\r
+ ulWantedClock = ulWantedBaud * serWANTED_CLOCK_SCALING;\r
+ ulDivisor = configCPU_CLOCK_HZ / ulWantedClock;\r
+\r
+ /* Set the DLAB bit so we can access the divisor. */\r
+ U0LCR |= serDLAB;\r
+\r
+ /* Setup the divisor. */\r
+ U0DLL = ( unsigned portCHAR ) ( ulDivisor & ( unsigned portLONG ) 0xff );\r
+ ulDivisor >>= 8;\r
+ U0DLM = ( unsigned portCHAR ) ( ulDivisor & ( unsigned portLONG ) 0xff );\r
+\r
+ /* Turn on the FIFO's and clear the buffers. */\r
+ U0FCR = ( serFIFO_ON | serCLEAR_FIFO );\r
+\r
+ /* Setup transmission format. */\r
+ U0LCR = serNO_PARITY | ser1_STOP_BIT | ser8_BIT_CHARS;\r
+\r
+ /* Setup the VIC for the UART. */\r
+ VICIntSelect &= ~( serU0VIC_CHANNEL_BIT );\r
+ VICIntEnable |= serU0VIC_CHANNEL_BIT;\r
+ VICVectAddr1 = ( unsigned portLONG ) vUART_ISR;\r
+ VICVectCntl1 = serU0VIC_CHANNEL | serU0VIC_ENABLE;\r
+\r
+ /* Enable UART0 interrupts. */\r
+ U0IER |= serENABLE_INTERRUPTS;\r
+ }\r
+ portEXIT_CRITICAL();\r
+ }\r
+ else\r
+ {\r
+ xReturn = ( xComPortHandle ) 0;\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )\r
+{\r
+ /* The port handle is not required as this driver only supports UART0. */\r
+ ( void ) pxPort;\r
+\r
+ /* Get the next character from the buffer. Return false if no characters\r
+ are available, or arrive before xBlockTime expires. */\r
+ if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )\r
+ {\r
+ return pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ return pdFALSE;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength )\r
+{\r
+signed portCHAR *pxNext;\r
+\r
+ /* NOTE: This implementation does not handle the queue being full as no\r
+ block time is used! */\r
+\r
+ /* The port handle is not required as this driver only supports UART0. */\r
+ ( void ) pxPort;\r
+ ( void ) usStringLength;\r
+\r
+ /* Send each character in the string, one at a time. */\r
+ pxNext = ( signed portCHAR * ) pcString;\r
+ while( *pxNext )\r
+ {\r
+ xSerialPutChar( pxPort, *pxNext, serNO_BLOCK );\r
+ pxNext++;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )\r
+{\r
+signed portBASE_TYPE xReturn;\r
+\r
+ /* The port handle is not required as this driver only supports UART0. */\r
+ ( void ) pxPort;\r
+\r
+ portENTER_CRITICAL();\r
+ {\r
+ /* Is there space to write directly to the UART? */\r
+ if( *plTHREEmpty == ( portLONG ) pdTRUE )\r
+ {\r
+ /* We wrote the character directly to the UART, so was \r
+ successful. */\r
+ *plTHREEmpty = pdFALSE;\r
+ U0THR = cOutChar;\r
+ xReturn = pdPASS;\r
+ }\r
+ else \r
+ {\r
+ /* We cannot write directly to the UART, so queue the character.\r
+ Block for a maximum of xBlockTime if there is no space in the\r
+ queue. It is ok to block within a critical section as each\r
+ task has it's own critical section management. */\r
+ xReturn = xQueueSend( xCharsForTx, &cOutChar, xBlockTime );\r
+\r
+ /* Depending on queue sizing and task prioritisation: While we \r
+ were blocked waiting to post interrupts were not disabled. It is \r
+ possible that the serial ISR has emptied the Tx queue, in which\r
+ case we need to start the Tx off again. */\r
+ if( *plTHREEmpty == ( portLONG ) pdTRUE )\r
+ {\r
+ xQueueReceive( xCharsForTx, &cOutChar, serNO_BLOCK );\r
+ *plTHREEmpty = pdFALSE;\r
+ U0THR = cOutChar;\r
+ }\r
+ }\r
+ }\r
+ portEXIT_CRITICAL();\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+\r
+\r
+\r
+\r
+ \r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+\r
+/* \r
+ BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0. \r
+\r
+ This file contains all the serial port components that must be compiled\r
+ to ARM mode. The components that can be compiled to either ARM or THUMB\r
+ mode are contained in serial.c.\r
+*/\r
+\r
+/* This file must always be compiled to ARM mode as it contains ISR \r
+definitions. */\r
+#pragma ARM\r
+\r
+/* Standard includes. */\r
+#include <stdlib.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "queue.h"\r
+#include "task.h"\r
+\r
+/* Demo application includes. */\r
+#include "serial.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Constant to access the VIC. */\r
+#define serCLEAR_VIC_INTERRUPT ( ( unsigned portLONG ) 0 )\r
+\r
+/* Constants to determine the ISR source. */\r
+#define serSOURCE_THRE ( ( unsigned portCHAR ) 0x02 )\r
+#define serSOURCE_RX_TIMEOUT ( ( unsigned portCHAR ) 0x0c )\r
+#define serSOURCE_ERROR ( ( unsigned portCHAR ) 0x06 )\r
+#define serSOURCE_RX ( ( unsigned portCHAR ) 0x04 )\r
+#define serINTERRUPT_SOURCE_MASK ( ( unsigned portCHAR ) 0x0f )\r
+\r
+/* Queues used to hold received characters, and characters waiting to be\r
+transmitted. */\r
+static xQueueHandle xRxedChars; \r
+static xQueueHandle xCharsForTx; \r
+static volatile portLONG lTHREEmpty;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* UART0 interrupt service routine. This can cause a context switch so MUST\r
+be declared "naked". */\r
+void vUART_ISR( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+void vSerialISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxRxedChars, \r
+ xQueueHandle *pxCharsForTx, portLONG volatile **pplTHREEmptyFlag )\r
+{\r
+ /* Create the queues used to hold Rx and Tx characters. */\r
+ xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );\r
+ xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );\r
+\r
+ /* Pass back a reference to the queues so the serial API file can \r
+ post/receive characters. */\r
+ *pxRxedChars = xRxedChars;\r
+ *pxCharsForTx = xCharsForTx;\r
+\r
+ /* Initialise the THRE empty flag - and pass back a reference. */\r
+ lTHREEmpty = pdTRUE;\r
+ *pplTHREEmptyFlag = &lTHREEmpty;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vUART_ISR( void ) __task\r
+{\r
+ portENTER_SWITCHING_ISR()\r
+\r
+ /* Now we can declare the local variables. */\r
+ static signed portCHAR cChar;\r
+ static portBASE_TYPE xTaskWokenByRx, xTaskWokenByTx;\r
+\r
+ xTaskWokenByTx = pdFALSE;\r
+ xTaskWokenByRx = pdFALSE;\r
+\r
+ /* What caused the interrupt? */\r
+ switch( U0IIR & serINTERRUPT_SOURCE_MASK )\r
+ {\r
+ case serSOURCE_ERROR : /* Not handling this, but clear the interrupt. */\r
+ cChar = U0LSR;\r
+ break;\r
+\r
+ case serSOURCE_THRE : /* The THRE is empty. If there is another\r
+ character in the Tx queue, send it now. */\r
+ if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWokenByTx ) == pdTRUE )\r
+ {\r
+ U0THR = cChar;\r
+ }\r
+ else\r
+ {\r
+ /* There are no further characters \r
+ queued to send so we can indicate \r
+ that the THRE is available. */\r
+ lTHREEmpty = pdTRUE;\r
+ }\r
+ break;\r
+\r
+ case serSOURCE_RX_TIMEOUT :\r
+ case serSOURCE_RX : /* A character was received. Place it in \r
+ the queue of received characters. */\r
+ cChar = U0RBR;\r
+ if( xQueueSendFromISR( xRxedChars, &cChar, pdFALSE ) )\r
+ {\r
+ xTaskWokenByRx = pdTRUE;\r
+ }\r
+ break;\r
+\r
+ default : /* There is nothing to do, leave the ISR. */\r
+ break;\r
+ }\r
+\r
+ /* Clear the ISR in the VIC. */\r
+ VICVectAddr = serCLEAR_VIC_INTERRUPT;\r
+\r
+ /* Exit the ISR. If a task was woken by either a character being received\r
+ or transmitted then a context switch will occur. */\r
+ portEXIT_SWITCHING_ISR( ( xTaskWokenByTx || xTaskWokenByRx ) );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+\r
+\r
+\r
+ \r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 48000000 )\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 100 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) 20480 )\r
+#define configMAX_TASK_NAME_LEN ( 16 )\r
+#define configUSE_TRACE_FACILITY 0\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 1\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 0\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+/******************** (C) COPYRIGHT 2003 STMicroelectronics ********************\r
+* File Name : 71x_lib.c\r
+* Author : MCD Application Team\r
+* Date First Issued : 05/16/2003\r
+* Description : Peripherals pointers initialization\r
+********************************************************************************\r
+* History:\r
+* 30/11/2004 : V2.0\r
+* 14/07/2004 : V1.3\r
+* 01/01/2004 : V1.2\r
+*******************************************************************************\r
+ THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH\r
+ CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+ AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT\r
+ OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT\r
+ OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION\r
+ CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+#define EXT\r
+\r
+#include "71x_map.h"\r
+\r
+#ifdef DEBUG\r
+\r
+extern u32 T0TIMI_Addr;\r
+\r
+/*******************************************************************************\r
+* Function Name : debug\r
+* Description : Initialize the pointers to peripherals\r
+* Input : none\r
+* Output : none\r
+* Return : none\r
+*******************************************************************************/\r
+void debug(void)\r
+{\r
+ #ifdef _ADC12\r
+ ADC12 = (ADC12_TypeDef *)ADC12_BASE;\r
+ #endif\r
+\r
+ #ifdef _APB\r
+ #ifdef _APB1\r
+ APB1 = (APB_TypeDef *)APB1_BASE;\r
+ #endif\r
+ #ifdef _APB2\r
+ APB2 = (APB_TypeDef *)APB2_BASE;\r
+ #endif\r
+ #endif\r
+\r
+ #ifdef _BSPI\r
+ #ifdef _BSPI0\r
+ BSPI0 = (BSPI_TypeDef *)BSPI0_BASE;\r
+ #endif\r
+ #ifdef _BSPI1\r
+ BSPI1 = (BSPI_TypeDef *)BSPI1_BASE;\r
+ #endif\r
+ #endif\r
+\r
+ #ifdef _CAN\r
+ CAN = (CAN_TypeDef *)CAN_BASE;\r
+ #endif\r
+\r
+ #ifdef _EIC\r
+ EIC = (EIC_TypeDef *)EIC_BASE;\r
+ #endif\r
+\r
+ #ifdef _EMI\r
+ EMI = (EMI_TypeDef *)EMI_BASE;\r
+ #endif\r
+\r
+ #ifdef _FLASH\r
+ FLASHR = (FLASHR_TypeDef *)FLASHR_BASE;\r
+ FLASHPR = (FLASHPR_TypeDef *)FLASHPR_BASE;\r
+ #endif\r
+\r
+ #ifdef _GPIO\r
+ #ifdef _GPIO0\r
+ GPIO0 = (GPIO_TypeDef *)GPIO0_BASE;\r
+ #endif\r
+ #ifdef _GPIO1\r
+ GPIO1 = (GPIO_TypeDef *)GPIO1_BASE;\r
+ #endif\r
+ #ifdef _GPIO2\r
+ GPIO2 = (GPIO_TypeDef *)GPIO2_BASE;\r
+ #endif\r
+ #endif\r
+\r
+ #ifdef _I2C\r
+ #ifdef _I2C0\r
+ I2C0 = (I2C_TypeDef *)I2C0_BASE;\r
+ #endif\r
+ #ifdef _I2C1\r
+ I2C1 = (I2C_TypeDef *)I2C1_BASE;\r
+ #endif\r
+ #endif\r
+\r
+ #ifdef _PCU\r
+ PCU = (PCU_TypeDef *)PCU_BASE;\r
+ #endif\r
+\r
+ #ifdef _RCCU\r
+ RCCU = (RCCU_TypeDef *)RCCU_BASE;\r
+ #endif\r
+\r
+ #ifdef _RTC\r
+ RTC = (RTC_TypeDef *)RTC_BASE;\r
+ #endif\r
+\r
+ #ifdef _TIM\r
+ #ifdef _TIM0\r
+ TIM0 = (TIM_TypeDef *)TIM0_BASE;\r
+ #endif\r
+ #ifdef _TIM1\r
+ TIM1 = (TIM_TypeDef *)TIM1_BASE;\r
+ #endif\r
+ #ifdef _TIM2\r
+ TIM2 = (TIM_TypeDef *)TIM2_BASE;\r
+ #endif\r
+ #ifdef _TIM3\r
+ TIM3 = (TIM_TypeDef *)TIM3_BASE;\r
+ #endif\r
+ #endif\r
+\r
+ #ifdef _UART\r
+ #ifdef _UART0\r
+ UART0 = (UART_TypeDef *)UART0_BASE;\r
+ #endif\r
+ #ifdef _UART1\r
+ UART1 = (UART_TypeDef *)UART1_BASE;\r
+ #endif\r
+ #ifdef _UART2\r
+ UART2 = (UART_TypeDef *)UART2_BASE;\r
+ #endif\r
+ #ifdef _UART3\r
+ UART3 = (UART_TypeDef *)UART3_BASE;\r
+ #endif\r
+ #endif\r
+\r
+ #ifdef _USB\r
+ USB = (USB_TypeDef *)USB_BASE;\r
+ #endif\r
+\r
+ #ifdef _WDG\r
+ WDG = (WDG_TypeDef *)WDG_BASE;\r
+ #endif\r
+\r
+ #ifdef _XTI\r
+ XTI = (XTI_TypeDef *)XTI_BASE;\r
+ #endif\r
+\r
+ #ifdef _IRQVectors\r
+ IRQVectors = (IRQVectors_TypeDef *)&T0TIMI_Addr;\r
+ #endif\r
+}\r
+\r
+#endif /* DEBUG */\r
+\r
+/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2003 STMicroelectronics ********************\r
+* File Name : gpio.c\r
+* Author : MCD Application Team\r
+* Date First Issued : 06/08/2003\r
+* Description : This file provides all the GPIO software functions\r
+********************************************************************************\r
+* History:\r
+* 30/11/2004 : V2.0\r
+* 14/07/2004 : V1.3\r
+* 01/01/2004 : V1.2\r
+*******************************************************************************\r
+ THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH\r
+ CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+ AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT\r
+ OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT\r
+ OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION\r
+ CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+#include "gpio.h"\r
+\r
+/*******************************************************************************\r
+* Function Name : GPIO_Config\r
+* Description : Configure the GPIO port pins\r
+* Input 1 : GPIOx (x can be 0,1 or 2) the desired port\r
+* Input 2 : Port_Pins : pins placements\r
+* Input 3 : Pins Mode\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void GPIO_Config (GPIO_TypeDef *GPIOx, u16 Port_Pins, GpioPinMode_TypeDef GPIO_Mode)\r
+{\r
+ switch (GPIO_Mode)\r
+ {\r
+ case GPIO_HI_AIN_TRI:\r
+ GPIOx->PC0&=~Port_Pins;\r
+ GPIOx->PC1&=~Port_Pins;\r
+ GPIOx->PC2&=~Port_Pins;\r
+ break;\r
+\r
+ case GPIO_IN_TRI_TTL:\r
+ GPIOx->PC0|=Port_Pins;\r
+ GPIOx->PC1&=~Port_Pins;\r
+ GPIOx->PC2&=~Port_Pins;\r
+ break;\r
+\r
+ case GPIO_IN_TRI_CMOS:\r
+ GPIOx->PC0&=~Port_Pins;\r
+ GPIOx->PC1|=Port_Pins;\r
+ GPIOx->PC2&=~Port_Pins;\r
+ break;\r
+\r
+ case GPIO_IPUPD_WP:\r
+ GPIOx->PC0|=Port_Pins;\r
+ GPIOx->PC1|=Port_Pins;\r
+ GPIOx->PC2&=~Port_Pins;\r
+ break;\r
+\r
+ case GPIO_OUT_OD:\r
+ GPIOx->PC0&=~Port_Pins;\r
+ GPIOx->PC1&=~Port_Pins;\r
+ GPIOx->PC2|=Port_Pins;\r
+ break;\r
+\r
+ case GPIO_OUT_PP:\r
+ GPIOx->PC0|=Port_Pins;\r
+ GPIOx->PC1&=~Port_Pins;\r
+ GPIOx->PC2|=Port_Pins;\r
+ break;\r
+\r
+ case GPIO_AF_OD:\r
+ GPIOx->PC0&=~Port_Pins;\r
+ GPIOx->PC1|=Port_Pins;\r
+ GPIOx->PC2|=Port_Pins;\r
+ break;\r
+\r
+ case GPIO_AF_PP:\r
+ GPIOx->PC0|=Port_Pins;\r
+ GPIOx->PC1|=Port_Pins;\r
+ GPIOx->PC2|=Port_Pins;\r
+ break;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : GPIO_BitWrite\r
+* Description : Set or reset the selected port pin\r
+* Input 1 : Selected GPIO port\r
+* Input 2 : Pin number\r
+* Input 3 : bit value\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void GPIO_BitWrite(GPIO_TypeDef *GPIOx, u8 Port_Pin, u8 Port_Val)\r
+{\r
+ if (Port_Val&0x01) GPIOx->PD |= 1<<Port_Pin; else GPIOx->PD &= ~(1<<Port_Pin);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : GPIO_ByteWrite\r
+* Description : Write byte value to the selected PD register\r
+* Input 1 : Selected GPIO port\r
+* Input 2 : GPIO_MSB or GPIO_LSB\r
+* Input 3 : Byte value\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void GPIO_ByteWrite(GPIO_TypeDef *GPIOx, u8 Port_Byte, u8 Port_Val)\r
+{\r
+ GPIOx->PD = Port_Byte ? (GPIOx->PD&0x00FF) | ((u16)Port_Val<<8)\r
+ : (GPIOx->PD&0xFF00) | Port_Val;\r
+}\r
+\r
+/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2003 STMicroelectronics ********************\r
+* File Name : 71x_conf.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 16/05/2003\r
+* Description : Library configuration for the ADC12 example\r
+********************************************************************************\r
+* History:\r
+* 16/05/2003 : Created\r
+* 30/11/2004 : V2.0\r
+*******************************************************************************\r
+ THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH\r
+ CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+ AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT\r
+ OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT\r
+ OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION\r
+ CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+#ifndef __71x_CONF_H\r
+#define __71x_CONF_H\r
+\r
+\r
+/* Comment the line below to put the library in release mode */\r
+//#define DEBUG\r
+\r
+//#define inline inline\r
+\r
+//#define USE_SERIAL_PORT\r
+//#define USE_UART0\r
+\r
+// Main Oscillator Frequency value = 4 Mhz\r
+#define RCCU_Main_Osc 4000000\r
+\r
+/* Comment the lines below corresponding to unwanted peripherals */\r
+//#define _ADC12\r
+\r
+//#define _APB\r
+//#define _APB1\r
+//#define _APB2\r
+\r
+//#define _BSPI\r
+//#define _BSPI0\r
+//#define _BSPI1\r
+\r
+//#define _CAN\r
+\r
+//#define _EIC\r
+\r
+//#define _EMI\r
+\r
+//#define _FLASH\r
+\r
+#define _GPIO\r
+#define _GPIO0\r
+#define _GPIO1\r
+#define _GPIO2\r
+\r
+//#define _I2C\r
+//#define _I2C0\r
+//#define _I2C1\r
+\r
+#define _PCU\r
+\r
+#define _RCCU\r
+\r
+//#define _RTC\r
+\r
+#define _TIM\r
+#define _TIM0\r
+//#define _TIM1\r
+//#define _TIM2\r
+//#define _TIM3\r
+\r
+//#define _UART\r
+//#define _UART0\r
+//#define _UART1\r
+//#define _UART2\r
+//#define _UART3\r
+\r
+//#define _USB\r
+\r
+//#define _WDG\r
+\r
+//#define _XTI\r
+\r
+\r
+//#define _IRQVectors\r
+\r
+\r
+#endif /* __71x_CONF_H */\r
+\r
+/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2003 STMicroelectronics ********************\r
+* File Name : 71x_it.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 05/16/2003\r
+* Description : Interrupt handlers\r
+********************************************************************************\r
+* History:\r
+* 30/11/2004 : V2.0\r
+* 14/07/2004 : V1.3\r
+* 01/01/2004 : V1.2\r
+*******************************************************************************\r
+ THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH\r
+ CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+ AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT\r
+ OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT\r
+ OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION\r
+ CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+#ifndef _71x_IT_H\r
+#define _71x_IT_H\r
+\r
+#include "71x_lib.h"\r
+\r
+\r
+void Undefined_Handler (void);\r
+void FIQ_Handler (void);\r
+void SWI_Handler (void);\r
+void Prefetch_Handler (void);\r
+void Abort_Handler (void);\r
+void T0TIMI_IRQHandler (void);\r
+void FLASH_IRQHandler (void);\r
+void RCCU_IRQHandler (void);\r
+void RTC_IRQHandler (void);\r
+void WDG_IRQHandler (void);\r
+void XTI_IRQHandler (void);\r
+void USBHP_IRQHandler (void);\r
+void I2C0ITERR_IRQHandler(void);\r
+void I2C1ITERR_IRQHandler(void);\r
+void UART0_IRQHandler (void);\r
+void UART1_IRQHandler (void);\r
+void UART2_IRQHandler (void);\r
+void UART3_IRQHandler (void);\r
+void BSPI0_IRQHandler (void);\r
+void BSPI1_IRQHandler (void);\r
+void I2C0_IRQHandler (void);\r
+void I2C1_IRQHandler (void);\r
+void CAN_IRQHandler (void);\r
+void ADC12_IRQHandler (void);\r
+void T1TIMI_IRQHandler (void);\r
+void T2TIMI_IRQHandler (void);\r
+void T3TIMI_IRQHandler (void);\r
+void HDLC_IRQHandler (void);\r
+void USBLP_IRQHandler (void);\r
+void T0TOI_IRQHandler (void);\r
+void T0OC1_IRQHandler (void);\r
+void T0OC2_IRQHandler (void);\r
+\r
+#endif /* _71x_IT_H */\r
+\r
+/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2003 STMicroelectronics ********************\r
+* File Name : 71x_lib.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 05/16/2003\r
+* Description : Global include for all peripherals\r
+********************************************************************************\r
+* 30/11/2004 : V2.0\r
+* 14/07/2004 : V1.3\r
+* 01/01/2004 : V1.2\r
+*******************************************************************************\r
+ THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH\r
+ CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+ AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT\r
+ OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT\r
+ OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION\r
+ CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+#ifndef __71x_LIB_H\r
+#define __71x_LIB_H\r
+\r
+#include "71x_map.h"\r
+#include "71x_conf.h"\r
+\r
+\r
+#ifdef _ADC12\r
+ #include "adc12.h"\r
+#endif\r
+\r
+#ifdef _APB\r
+ #include "apb.h"\r
+#endif\r
+\r
+#ifdef _BSPI\r
+ #include "bspi.h"\r
+#endif\r
+\r
+#ifdef _CAN\r
+ #include "can.h"\r
+#endif\r
+\r
+#ifdef _EIC\r
+ #include "eic.h"\r
+#endif\r
+\r
+#ifdef _EMI\r
+ #include "emi.h"\r
+#endif\r
+\r
+#ifdef _FLASH\r
+ #include "flash.h"\r
+#endif\r
+\r
+#ifdef _GPIO\r
+ #include "gpio.h"\r
+#endif\r
+\r
+#ifdef _I2C\r
+ #include "i2c.h"\r
+#endif\r
+\r
+#ifdef _PCU\r
+ #include "pcu.h"\r
+#endif\r
+\r
+#ifdef _RCCU\r
+ #include "rccu.h"\r
+#endif\r
+\r
+#ifdef _RTC\r
+ #include "rtc.h"\r
+#endif\r
+\r
+#ifdef _TIM\r
+ #include "tim.h"\r
+#endif\r
+\r
+#ifdef _UART\r
+ #include "uart.h"\r
+#endif\r
+\r
+#ifdef _USB\r
+#endif\r
+\r
+#ifdef _WDG\r
+ #include "wdg.h"\r
+#endif\r
+\r
+#ifdef _XTI\r
+ #include "xti.h"\r
+#endif\r
+\r
+\r
+#ifdef DEBUG\r
+ void debug(void);\r
+#endif\r
+\r
+#endif /* __71x_LIB_H */\r
+\r
+/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2003 STMicroelectronics ********************\r
+* File Name : 71x_map.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 05/16/2003\r
+* Description : Peripherals memory mapping and registers structures\r
+********************************************************************************\r
+* History:\r
+* 30/11/2004 : V2.0\r
+* 14/07/2004 : V1.3\r
+* 01/01/2004 : V1.2\r
+*******************************************************************************\r
+ THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH\r
+ CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+ AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT\r
+ OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT\r
+ OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION\r
+ CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+#ifndef __71x_map_H\r
+#define __71x_map_H\r
+\r
+#ifndef EXT\r
+ #define EXT extern\r
+#endif\r
+\r
+#include "71x_conf.h"\r
+#include "71x_type.h"\r
+\r
+\r
+/* IP registers structures */\r
+\r
+typedef volatile struct\r
+{\r
+ vu16 DATA0;\r
+ vu16 EMPTY1[3];\r
+ vu16 DATA1;\r
+ vu16 EMPTY2[3];\r
+ vu16 DATA2;\r
+ vu16 EMPTY3[3];\r
+ vu16 DATA3;\r
+ vu16 EMPTY4[3];\r
+ vu16 CSR;\r
+ vu16 EMPTY5[7];\r
+ vu16 CPR;\r
+} ADC12_TypeDef;\r
+\r
+typedef volatile struct\r
+{\r
+ vu32 CKDIS;\r
+ vu32 SWRES;\r
+} APB_TypeDef;\r
+\r
+typedef volatile struct\r
+{\r
+ vu16 RXR;\r
+ vu16 EMPTY1;\r
+ vu16 TXR;\r
+ vu16 EMPTY2;\r
+ vu16 CSR1;\r
+ vu16 EMPTY3;\r
+ vu16 CSR2;\r
+ vu16 EMPTY4;\r
+ vu16 CLK;\r
+} BSPI_TypeDef;\r
+\r
+typedef volatile struct\r
+{\r
+ vu16 CRR;\r
+ vu16 EMPTY1;\r
+ vu16 CMR;\r
+ vu16 EMPTY2;\r
+ vu16 M1R;\r
+ vu16 EMPTY3;\r
+ vu16 M2R;\r
+ vu16 EMPTY4;\r
+ vu16 A1R;\r
+ vu16 EMPTY5;\r
+ vu16 A2R;\r
+ vu16 EMPTY6;\r
+ vu16 MCR;\r
+ vu16 EMPTY7;\r
+ vu16 DA1R;\r
+ vu16 EMPTY8;\r
+ vu16 DA2R;\r
+ vu16 EMPTY9;\r
+ vu16 DB1R;\r
+ vu16 EMPTY10;\r
+ vu16 DB2R;\r
+ vu16 EMPTY11[27];\r
+} CAN_MsgObj_TypeDef;\r
+\r
+typedef volatile struct\r
+{\r
+ vu16 CR;\r
+ vu16 EMPTY1;\r
+ vu16 SR;\r
+ vu16 EMPTY2;\r
+ vu16 ERR;\r
+ vu16 EMPTY3;\r
+ vu16 BTR;\r
+ vu16 EMPTY4;\r
+ vu16 IDR;\r
+ vu16 EMPTY5;\r
+ vu16 TESTR;\r
+ vu16 EMPTY6;\r
+ vu16 BRPR;\r
+ vu16 EMPTY7[3];\r
+ CAN_MsgObj_TypeDef sMsgObj[2];\r
+ vu16 EMPTY8[16];\r
+ vu16 TR1R;\r
+ vu16 EMPTY9;\r
+ vu16 TR2R;\r
+ vu16 EMPTY10[13];\r
+ vu16 ND1R;\r
+ vu16 EMPTY11;\r
+ vu16 ND2R;\r
+ vu16 EMPTY12[13];\r
+ vu16 IP1R;\r
+ vu16 EMPTY13;\r
+ vu16 IP2R;\r
+ vu16 EMPTY14[13];\r
+ vu16 MV1R;\r
+ vu16 EMPTY15;\r
+ vu16 MV2R;\r
+ vu16 EMPTY16;\r
+} CAN_TypeDef;\r
+\r
+typedef volatile struct\r
+{\r
+ vu32 ICR;\r
+ vu32 CICR;\r
+ vu32 CIPR;\r
+ vu32 EMPTY1[3];\r
+ vu32 IVR;\r
+ vu32 FIR;\r
+ vu32 IER;\r
+ vu32 EMPTY2[7];\r
+ vu32 IPR;\r
+ vu32 EMPTY3[7];\r
+ vu32 SIR[32];\r
+} EIC_TypeDef;\r
+\r
+typedef volatile struct\r
+{\r
+ vu16 BCON0;\r
+ vu16 EMPTY1;\r
+ vu16 BCON1;\r
+ vu16 EMPTY2;\r
+ vu16 BCON2;\r
+ vu16 EMPTY3;\r
+ vu16 BCON3;\r
+ vu16 EMPTY4;\r
+} EMI_TypeDef;\r
+\r
+typedef volatile struct\r
+{\r
+ vu32 CR0;\r
+ vu32 CR1;\r
+ vu32 DR0;\r
+ vu32 DR1;\r
+ vu32 AR;\r
+ vu32 ER;\r
+} FLASHR_TypeDef;\r
+\r
+typedef volatile struct\r
+{\r
+ vu32 NVWPAR;\r
+ vu32 EMPTY;\r
+ vu32 NVAPR0;\r
+ vu32 NVAPR1;\r
+} FLASHPR_TypeDef;\r
+\r
+typedef volatile struct\r
+{\r
+ vu16 PC0;\r
+ vu16 EMPTY1;\r
+ vu16 PC1;\r
+ vu16 EMPTY2;\r
+ vu16 PC2;\r
+ vu16 EMPTY3;\r
+ vu16 PD;\r
+ vu16 EMPTY4;\r
+} GPIO_TypeDef;\r
+\r
+typedef volatile struct\r
+{\r
+ vu8 CR;\r
+ vu8 EMPTY1[3];\r
+ vu8 SR1;\r
+ vu8 EMPTY2[3];\r
+ vu8 SR2;\r
+ vu8 EMPTY3[3];\r
+ vu8 CCR;\r
+ vu8 EMPTY4[3];\r
+ vu8 OAR1;\r
+ vu8 EMPTY5[3];\r
+ vu8 OAR2;\r
+ vu8 EMPTY6[3];\r
+ vu8 DR;\r
+ vu8 EMPTY7[3];\r
+ vu8 ECCR;\r
+} I2C_TypeDef;\r
+\r
+typedef volatile struct\r
+{\r
+ vu32 CCR;\r
+ vu32 EMPTY1;\r
+ vu32 CFR;\r
+ vu32 EMPTY2[3];\r
+ vu32 PLL1CR;\r
+ vu32 PER;\r
+ vu32 SMR;\r
+} RCCU_TypeDef;\r
+\r
+typedef volatile struct\r
+{\r
+ vu16 MDIVR;\r
+ vu16 EMPTY1;\r
+ vu16 PDIVR;\r
+ vu16 EMPTY2;\r
+ vu16 RSTR;\r
+ vu16 EMPTY3;\r
+ vu16 PLL2CR;\r
+ vu16 EMPTY4;\r
+ vu16 BOOTCR;\r
+ vu16 EMPTY5;\r
+ vu16 PWRCR;\r
+} PCU_TypeDef;\r
+\r
+typedef volatile struct\r
+{\r
+ vu16 CRH;\r
+ vu16 EMPTY1;\r
+ vu16 CRL;\r
+ vu16 EMPTY2;\r
+ vu16 PRLH;\r
+ vu16 EMPTY3;\r
+ vu16 PRLL;\r
+ vu16 EMPTY4;\r
+ vu16 DIVH;\r
+ vu16 EMPTY5;\r
+ vu16 DIVL;\r
+ vu16 EMPTY6;\r
+ vu16 CNTH;\r
+ vu16 EMPTY7;\r
+ vu16 CNTL;\r
+ vu16 EMPTY8;\r
+ vu16 ALRH;\r
+ vu16 EMPTY9;\r
+ vu16 ALRL;\r
+} RTC_TypeDef;\r
+\r
+typedef volatile struct\r
+{\r
+ vu16 ICAR;\r
+ vu16 EMPTY1;\r
+ vu16 ICBR;\r
+ vu16 EMPTY2;\r
+ vu16 OCAR;\r
+ vu16 EMPTY3;\r
+ vu16 OCBR;\r
+ vu16 EMPTY4;\r
+ vu16 CNTR;\r
+ vu16 EMPTY5;\r
+ vu16 CR1;\r
+ vu16 EMPTY6;\r
+ vu16 CR2;\r
+ vu16 EMPTY7;\r
+ vu16 SR;\r
+} TIM_TypeDef;\r
+\r
+typedef volatile struct\r
+{\r
+ vu16 BR;\r
+ vu16 EMPTY1;\r
+ vu16 TxBUFR;\r
+ vu16 EMPTY2;\r
+ vu16 RxBUFR;\r
+ vu16 EMPTY3;\r
+ vu16 CR;\r
+ vu16 EMPTY4;\r
+ vu16 IER;\r
+ vu16 EMPTY5;\r
+ vu16 SR;\r
+ vu16 EMPTY6;\r
+ vu16 GTR;\r
+ vu16 EMPTY7;\r
+ vu16 TOR;\r
+ vu16 EMPTY8;\r
+ vu16 TxRSTR;\r
+ vu16 EMPTY9;\r
+ vu16 RxRSTR;\r
+} UART_TypeDef;\r
+\r
+typedef volatile struct\r
+{\r
+ vu32 EP0R;\r
+ vu32 EP1R;\r
+ vu32 EP2R;\r
+ vu32 EP3R;\r
+ vu32 EP4R;\r
+ vu32 EP5R;\r
+ vu32 EP6R;\r
+ vu32 EP7R;\r
+ vu32 EP8R;\r
+ vu32 EP9R;\r
+ vu32 EP10R;\r
+ vu32 EP11R;\r
+ vu32 EP12R;\r
+ vu32 EP13R;\r
+ vu32 EP14R;\r
+ vu32 EP15R;\r
+ vu32 CNTR;\r
+ vu32 ISTR;\r
+ vu32 FNR;\r
+ vu32 DADDR;\r
+ vu32 BTABLE;\r
+} USB_TypeDef;\r
+\r
+typedef volatile struct\r
+{\r
+ vu16 CR;\r
+ vu16 EMPTY1;\r
+ vu16 PR;\r
+ vu16 EMPTY2;\r
+ vu16 VR;\r
+ vu16 EMPTY3;\r
+ vu16 CNT;\r
+ vu16 EMPTY4;\r
+ vu16 SR;\r
+ vu16 EMPTY5;\r
+ vu16 MR;\r
+ vu16 EMPTY6;\r
+ vu16 KR;\r
+} WDG_TypeDef;\r
+\r
+typedef volatile struct\r
+{\r
+ vu8 SR;\r
+ vu8 EMPTY1[7];\r
+ vu8 CTRL;\r
+ vu8 EMPTY2[3];\r
+ vu8 MRH;\r
+ vu8 EMPTY3[3];\r
+ vu8 MRL;\r
+ vu8 EMPTY4[3];\r
+ vu8 TRH;\r
+ vu8 EMPTY5[3];\r
+ vu8 TRL;\r
+ vu8 EMPTY6[3];\r
+ vu8 PRH;\r
+ vu8 EMPTY7[3];\r
+ vu8 PRL;\r
+} XTI_TypeDef;\r
+\r
+\r
+/* IRQ vectors */\r
+typedef volatile struct\r
+{\r
+ vu32 T0TIMI_IRQHandler;\r
+ vu32 FLASH_IRQHandler;\r
+ vu32 RCCU_IRQHandler;\r
+ vu32 RTC_IRQHandler;\r
+ vu32 WDG_IRQHandler;\r
+ vu32 XTI_IRQHandler;\r
+ vu32 USBHP_IRQHandler;\r
+ vu32 I2C0ITERR_IRQHandler;\r
+ vu32 I2C1ITERR_IRQHandler;\r
+ vu32 UART0_IRQHandler;\r
+ vu32 UART1_IRQHandler;\r
+ vu32 UART2_IRQHandler;\r
+ vu32 UART3_IRQHandler;\r
+ vu32 BSPI0_IRQHandler;\r
+ vu32 BSPI1_IRQHandler;\r
+ vu32 I2C0_IRQHandler;\r
+ vu32 I2C1_IRQHandler;\r
+ vu32 CAN_IRQHandler;\r
+ vu32 ADC12_IRQHandler;\r
+ vu32 T1TIMI_IRQHandler;\r
+ vu32 T2TIMI_IRQHandler;\r
+ vu32 T3TIMI_IRQHandler;\r
+ vu32 EMPTY1[3];\r
+ vu32 HDLC_IRQHandler;\r
+ vu32 USBLP_IRQHandler;\r
+ vu32 EMPTY2[2];\r
+ vu32 T0TOI_IRQHandler;\r
+ vu32 T0OC1_IRQHandler;\r
+ vu32 T0OC2_IRQHandler;\r
+} IRQVectors_TypeDef;\r
+\r
+/*===================================================================*/\r
+\r
+/* Memory mapping */\r
+\r
+#define RAM_BASE 0x20000000\r
+\r
+#define FLASHR_BASE 0x40100000\r
+#define FLASHPR_BASE 0x4010DFB0\r
+\r
+#define EXTMEM_BASE 0x60000000\r
+#define RCCU_BASE 0xA0000000\r
+#define PCU_BASE 0xA0000040\r
+#define APB1_BASE 0xC0000000\r
+#define APB2_BASE 0xE0000000\r
+#define EIC_BASE 0xFFFFF800\r
+\r
+#define I2C0_BASE (APB1_BASE + 0x1000)\r
+#define I2C1_BASE (APB1_BASE + 0x2000)\r
+#define UART0_BASE (APB1_BASE + 0x4000)\r
+#define UART1_BASE (APB1_BASE + 0x5000)\r
+#define UART2_BASE (APB1_BASE + 0x6000)\r
+#define UART3_BASE (APB1_BASE + 0x7000)\r
+#define CAN_BASE (APB1_BASE + 0x9000)\r
+#define BSPI0_BASE (APB1_BASE + 0xA000)\r
+#define BSPI1_BASE (APB1_BASE + 0xB000)\r
+#define USB_BASE (APB1_BASE + 0x8800)\r
+\r
+#define XTI_BASE (APB2_BASE + 0x101C)\r
+#define GPIO0_BASE (APB2_BASE + 0x3000)\r
+#define GPIO1_BASE (APB2_BASE + 0x4000)\r
+#define GPIO2_BASE (APB2_BASE + 0x5000)\r
+#define ADC12_BASE (APB2_BASE + 0x7000)\r
+#define TIM0_BASE (APB2_BASE + 0x9000)\r
+#define TIM1_BASE (APB2_BASE + 0xA000)\r
+#define TIM2_BASE (APB2_BASE + 0xB000)\r
+#define TIM3_BASE (APB2_BASE + 0xC000)\r
+#define RTC_BASE (APB2_BASE + 0xD000)\r
+#define WDG_BASE (APB2_BASE + 0xE000)\r
+\r
+#define EMI_BASE (EXTMEM_BASE + 0x0C000000)\r
+\r
+/*===================================================================*/\r
+\r
+/* IP data access */\r
+\r
+#ifndef DEBUG\r
+ #define ADC12 ((ADC12_TypeDef *)ADC12_BASE)\r
+\r
+ #define APB1 ((APB_TypeDef *)APB1_BASE)\r
+ #define APB2 ((APB_TypeDef *)APB2_BASE+0x10)\r
+\r
+ #define BSPI0 ((BSPI_TypeDef *)BSPI0_BASE)\r
+ #define BSPI1 ((BSPI_TypeDef *)BSPI1_BASE)\r
+\r
+ #define CAN ((CAN_TypeDef *)CAN_BASE)\r
+\r
+ #define EIC ((EIC_TypeDef *)EIC_BASE)\r
+\r
+ #define EMI ((EMI_TypeDef *)EMI_BASE)\r
+\r
+ #define FLASHR ((FLASHR_TypeDef *)FLASHR_BASE)\r
+ #define FLASHPR ((FLASHPR_TypeDef *)FLASHPR_BASE)\r
+\r
+ #define GPIO0 ((GPIO_TypeDef *)GPIO0_BASE)\r
+ #define GPIO1 ((GPIO_TypeDef *)GPIO1_BASE)\r
+ #define GPIO2 ((GPIO_TypeDef *)GPIO2_BASE)\r
+\r
+ #define I2C0 ((I2C_TypeDef *)I2C0_BASE)\r
+ #define I2C1 ((I2C_TypeDef *)I2C1_BASE)\r
+\r
+ #define PCU ((PCU_TypeDef *)PCU_BASE)\r
+\r
+ #define RCCU ((RCCU_TypeDef *)RCCU_BASE)\r
+\r
+ #define RTC ((RTC_TypeDef *)RTC_BASE)\r
+\r
+ #define TIM0 ((TIM_TypeDef *)TIM0_BASE)\r
+ #define TIM1 ((TIM_TypeDef *)TIM1_BASE)\r
+ #define TIM2 ((TIM_TypeDef *)TIM2_BASE)\r
+ #define TIM3 ((TIM_TypeDef *)TIM3_BASE)\r
+\r
+ #define UART0 ((UART_TypeDef *)UART0_BASE)\r
+ #define UART1 ((UART_TypeDef *)UART1_BASE)\r
+ #define UART2 ((UART_TypeDef *)UART2_BASE)\r
+ #define UART3 ((UART_TypeDef *)UART3_BASE)\r
+\r
+ #define USB ((USB_TypeDef *)USB_BASE)\r
+\r
+ #define WDG ((WDG_TypeDef *)WDG_BASE)\r
+\r
+ #define XTI ((XTI_TypeDef *)XTI_BASE)\r
+\r
+ #define IRQVectors ((IRQVectors_TypeDef *)&T0TIMI_Addr)\r
+\r
+#else /* DEBUG */\r
+\r
+ #ifdef _ADC12\r
+ EXT ADC12_TypeDef *ADC12;\r
+ #endif\r
+\r
+ #ifdef _APB\r
+ #ifdef _APB1\r
+ EXT APB_TypeDef *APB1;\r
+ #endif\r
+ #ifdef _APB2\r
+ EXT APB_TypeDef *APB2;\r
+ #endif\r
+ #endif\r
+\r
+ #ifdef _BSPI\r
+ #ifdef _BSPI0\r
+ EXT BSPI_TypeDef *BSPI0;\r
+ #endif\r
+ #ifdef _BSPI1\r
+ EXT BSPI_TypeDef *BSPI1;\r
+ #endif\r
+ #endif\r
+\r
+ #ifdef _CAN\r
+ EXT CAN_TypeDef *CAN;\r
+ #endif\r
+\r
+ #ifdef _EIC\r
+ EXT EIC_TypeDef *EIC;\r
+ #endif\r
+\r
+ #ifdef _EMI\r
+ EXT EMI_TypeDef *EMI;\r
+ #endif\r
+\r
+ #ifdef _FLASH\r
+ EXT FLASHR_TypeDef *FLASHR;\r
+ EXT FLASHPR_TypeDef *FLASHPR;\r
+ #endif\r
+\r
+ #ifdef _GPIO\r
+ #ifdef _GPIO0\r
+ EXT GPIO_TypeDef *GPIO0;\r
+ #endif\r
+ #ifdef _GPIO1\r
+ EXT GPIO_TypeDef *GPIO1;\r
+ #endif\r
+ #ifdef _GPIO2\r
+ EXT GPIO_TypeDef *GPIO2;\r
+ #endif\r
+ #endif\r
+\r
+ #ifdef _I2C\r
+ #ifdef _I2C0\r
+ EXT I2C_TypeDef *I2C0;\r
+ #endif\r
+ #ifdef _I2C1\r
+ EXT I2C_TypeDef *I2C1;\r
+ #endif\r
+ #endif\r
+\r
+ #ifdef _PCU\r
+ EXT PCU_TypeDef *PCU;\r
+ #endif\r
+\r
+ #ifdef _RCCU\r
+ EXT RCCU_TypeDef *RCCU;\r
+ #endif\r
+\r
+ #ifdef _RTC\r
+ EXT RTC_TypeDef *RTC;\r
+ #endif\r
+\r
+ #ifdef _TIM\r
+ #ifdef _TIM0\r
+ EXT TIM_TypeDef *TIM0;\r
+ #endif\r
+ #ifdef _TIM1\r
+ EXT TIM_TypeDef *TIM1;\r
+ #endif\r
+ #ifdef _TIM2\r
+ EXT TIM_TypeDef *TIM2;\r
+ #endif\r
+ #ifdef _TIM3\r
+ EXT TIM_TypeDef *TIM3;\r
+ #endif\r
+ #endif\r
+\r
+ #ifdef _UART\r
+ #ifdef _UART0\r
+ EXT UART_TypeDef *UART0;\r
+ #endif\r
+ #ifdef _UART1\r
+ EXT UART_TypeDef *UART1;\r
+ #endif\r
+ #ifdef _UART2\r
+ EXT UART_TypeDef *UART2;\r
+ #endif\r
+ #ifdef _UART3\r
+ EXT UART_TypeDef *UART3;\r
+ #endif\r
+ #endif\r
+\r
+ #ifdef _USB\r
+ EXT USB_TypeDef *USB;\r
+ #endif\r
+\r
+ #ifdef _WDG\r
+ EXT WDG_TypeDef *WDG;\r
+ #endif\r
+\r
+ #ifdef _XTI\r
+ EXT XTI_TypeDef *XTI;\r
+ #endif\r
+\r
+ #ifdef _IRQVectors\r
+ EXT IRQVectors_TypeDef *IRQVectors;\r
+ #endif\r
+\r
+#endif /* DEBUG */\r
+\r
+#endif /* __71x_map_H */\r
+\r
+/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2003 STMicroelectronics ********************\r
+* File Name : 71x_type.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 05/16/2003\r
+* Description : Common data types\r
+********************************************************************************\r
+* History:\r
+* 30/11/2004 : V2.0\r
+* 14/07/2004 : V1.3\r
+* 01/01/2004 : V1.2\r
+*******************************************************************************\r
+ THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH\r
+ CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+ AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT\r
+ OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT\r
+ OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION\r
+ CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+#ifndef _71x_type_H\r
+#define _71x_type_H\r
+\r
+typedef unsigned long u32;\r
+typedef unsigned short u16;\r
+typedef unsigned char u8;\r
+\r
+typedef signed long s32;\r
+typedef signed short s16;\r
+typedef signed char s8;\r
+\r
+typedef volatile unsigned long vu32;\r
+typedef volatile unsigned short vu16;\r
+typedef volatile unsigned char vu8;\r
+\r
+typedef volatile signed long vs32;\r
+typedef volatile signed short vs16;\r
+typedef volatile signed char vs8;\r
+\r
+/*===================================================================*/\r
+typedef enum { FALSE = 0, TRUE = !FALSE } bool;\r
+/*===================================================================*/\r
+typedef enum { RESET = 0, SET = !RESET } FlagStatus;\r
+/*===================================================================*/\r
+typedef enum { DISABLE = 0, ENABLE = !DISABLE} FunctionalState;\r
+/*===================================================================*/\r
+typedef enum { INDIRECT = 0, DIRECT = !INDIRECT} RegisterAccess;\r
+/*===================================================================*/\r
+\r
+#endif /* _71x_type_H */\r
+\r
+/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2003 STMicroelectronics ********************\r
+* File Name : eic.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 25/06/2003\r
+* Description : This file contains all the functions prototypes for the\r
+* EIC software library.\r
+********************************************************************************\r
+* History:\r
+* 30/11/2004 : V2.0\r
+* 14/07/2004 : V1.3\r
+* 01/01/2004 : V1.2\r
+*******************************************************************************\r
+ THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH\r
+ CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+ AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT\r
+ OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT\r
+ OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION\r
+ CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+#ifndef __eic_H\r
+#define __eic_H\r
+\r
+#include "71x_map.h"\r
+\r
+typedef enum\r
+{\r
+ T0TIMI_IRQChannel = 0,\r
+ FLASH_IRQChannel = 1,\r
+ RCCU_IRQChannel = 2,\r
+ RTC_IRQChannel = 3,\r
+ WDG_IRQChannel = 4,\r
+ XTI_IRQChannel = 5,\r
+ USBHP_IRQChannel = 6,\r
+ I2C0ITERR_IRQChannel = 7,\r
+ I2C1ITERR_IRQChannel = 8,\r
+ UART0_IRQChannel = 9,\r
+ UART1_IRQChannel = 10,\r
+ UART2_IRQChannel = 11,\r
+ UART3_IRQChannel = 12,\r
+ SPI0_IRQChannel = 13,\r
+ SPI1_IRQChannel = 14,\r
+ I2C0_IRQChannel = 15,\r
+ I2C1_IRQChannel = 16,\r
+ CAN_IRQChannel = 17,\r
+ ADC_IRQChannel = 18,\r
+ T1TIMI_IRQChannel = 19,\r
+ T2TIMI_IRQChannel = 20,\r
+ T3TIMI_IRQChannel = 21,\r
+ HDLC_IRQChannel = 25,\r
+ USBLP_IRQChannel = 26,\r
+ T0TOI_IRQChannel = 29,\r
+ T0OC1_IRQChannel = 30,\r
+ T0OC2_IRQChannel = 31\r
+} IRQChannel_TypeDef;\r
+\r
+typedef enum\r
+{\r
+ T0TIMI_FIQChannel = 0x00000001,\r
+ WDG_FIQChannel = 0x00000002,\r
+ WDGT0TIMI_FIQChannels = 0x00000003\r
+} FIQChannel_TypeDef;\r
+\r
+/*******************************************************************************\r
+* Function Name : EIC_Init\r
+* Description : Initialise the EIC using the load PC instruction\r
+* (PC = PC +offset)\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void EIC_Init(void);\r
+\r
+/*******************************************************************************\r
+* Function Name : EIC_IRQConfig\r
+* Description : Enable or Disable IRQ interrupts\r
+* Input 1 : New status : can be ENABLE or DISABLE\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+inline void EIC_IRQConfig(FunctionalState NewState)\r
+{\r
+ if (NewState==ENABLE) EIC->ICR |= 0x0001; else EIC->ICR &= ~0x0001;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : EIC_FIQConfig\r
+* Description : Enable or Disable FIQ interrupts\r
+* Input 1 : New status : can be ENABLE or DISABLE\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+inline void EIC_FIQConfig(FunctionalState NewState)\r
+{\r
+ if (NewState==ENABLE) EIC->ICR |= 0x0002; else EIC->ICR &= ~0x0002;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : EIC_IRQChannelConfig\r
+* Description : Configure the IRQ Channel\r
+* Input 1 : IRQ channel name\r
+* Input 2 : Channel New status : can be ENABLE or DISABLE\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+inline void EIC_IRQChannelConfig(IRQChannel_TypeDef IRQChannel, FunctionalState NewState)\r
+{\r
+ if (NewState==ENABLE) EIC->IER |= 0x0001 << IRQChannel;\r
+ else EIC->IER &= ~(0x0001 << IRQChannel);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : EIC_FIQChannelConfig\r
+* Description : Configure the FIQ Channel\r
+* Input 1 : FIQ channel name\r
+* Input 2 : Channel New status : can be ENABLE or DISABLE\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+inline void EIC_FIQChannelConfig(FIQChannel_TypeDef FIQChannel,\r
+ FunctionalState NewState)\r
+{\r
+ if (NewState==ENABLE) EIC->FIR |= FIQChannel;\r
+ else EIC->FIR &= ~FIQChannel;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : EIC_IRQChannelPriorityConfig\r
+* Description : Configure the selected IRQ channel priority\r
+* Input 1 : IRQ channel name\r
+* Input 2 : IRQ channel priority\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+inline void EIC_IRQChannelPriorityConfig(IRQChannel_TypeDef IRQChannel, u8 Priority)\r
+{\r
+ EIC->SIR[IRQChannel] = (EIC->SIR[IRQChannel]&0xFFFF0000) | (u16)Priority & 0x000F;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : EIC_CurrentPriorityLevelConfig\r
+* Description : Change the current priority level of the srved IRQ routine\r
+* Input 1 : New priority\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void EIC_CurrentPriorityLevelConfig(u8 NewPriorityLevel);\r
+\r
+/*******************************************************************************\r
+* Function Name : EIC_CurrentPriorityLevelValue\r
+* Description : Return the current priority level of the current served IRQ\r
+* routine\r
+* Input : None\r
+* Output : None\r
+* Return : The current priority level\r
+*******************************************************************************/\r
+inline u8 EIC_CurrentPriorityLevelValue(void)\r
+{\r
+ return EIC->CIPR & 0xF;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : EIC_CurrentIRQChannelValue\r
+* Description : Return the current served IRQ channel number\r
+* Input 0 : None\r
+* Output : None\r
+* Return : The current served IRQ channel number\r
+*******************************************************************************/\r
+inline IRQChannel_TypeDef EIC_CurrentIRQChannelValue(void)\r
+{\r
+ return (IRQChannel_TypeDef)(EIC->CICR & 0x1F);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : EIC_CurrentFIQChannelValue\r
+* Description : Return the current served FIQ channel number\r
+* Input : None\r
+* Output : None\r
+* Return : The current served FIQ channel number\r
+*******************************************************************************/\r
+inline FIQChannel_TypeDef EIC_CurrentFIQChannelValue(void)\r
+{\r
+ return (FIQChannel_TypeDef)((EIC->FIR >> 2) & 0x0003);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : EIC_FIPendingBitClear\r
+* Description : Clear the FIQ pending bit\r
+* Input 1 : FIQ channel\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+inline void EIC_FIQPendingBitClear(FIQChannel_TypeDef FIQChannel)\r
+{\r
+ EIC->FIR = (EIC->FIR & 0x0003) | (FIQChannel << 2);\r
+}\r
+\r
+#endif /* __eic_H */\r
+\r
+/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2003 STMicroelectronics ********************\r
+* File Name : gpio.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 08/06/2003\r
+* Description : This file contains all the functions prototypes for the\r
+* GPIO software library.\r
+********************************************************************************\r
+* History:\r
+* 30/11/2004 : V2.0\r
+* 14/07/2004 : V1.3\r
+* 01/01/2004 : V1.2\r
+*******************************************************************************\r
+ THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH\r
+ CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+ AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT\r
+ OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT\r
+ OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION\r
+ CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+#ifndef __gpio_H\r
+#define __gpio_H\r
+\r
+#include "71x_map.h"\r
+\r
+typedef enum\r
+{\r
+ GPIO_HI_AIN_TRI,\r
+ GPIO_IN_TRI_TTL,\r
+ GPIO_IN_TRI_CMOS,\r
+ GPIO_IPUPD_WP, \r
+ GPIO_OUT_OD,\r
+ GPIO_OUT_PP,\r
+ GPIO_AF_OD,\r
+ GPIO_AF_PP\r
+} GpioPinMode_TypeDef;\r
+\r
+#define GPIO_LSB 0x00\r
+#define GPIO_MSB 0x08\r
+\r
+/*******************************************************************************\r
+* Function Name : GPIO_Config\r
+* Description : Configure the GPIO port pins\r
+* Input 1 : GPIOx (x can be 0,1 or 2) the desired port\r
+* Input 2 : Port_Pins : pins placements\r
+* Input 3 : Pins Mode\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void GPIO_Config (GPIO_TypeDef *GPIOx, u16 Port_Pins, GpioPinMode_TypeDef GPIO_Mode);\r
+\r
+/*******************************************************************************\r
+* Function Name : GPIO_BitRead\r
+* Description : Read the desired port pin value\r
+* Input 1 : Selected GPIO port\r
+* Input 2 : Pin number\r
+* Output : None\r
+* Return : The selected pin value\r
+*******************************************************************************/\r
+inline u8 GPIO_BitRead(GPIO_TypeDef *GPIOx, u8 Port_Pin)\r
+{\r
+ return (GPIOx->PD >> Port_Pin) & 0x0001;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : GPIO_ByteRead\r
+* Description : Read the desired port Byte value\r
+* Input 1 : Selected GPIO port\r
+* Input 2 : GPIO_MSB or GPIO_LSB\r
+* Output : None\r
+* Return : The GPIO_MSB or GPIO_LSB of the selected PD register\r
+*******************************************************************************/\r
+inline u8 GPIO_ByteRead(GPIO_TypeDef *GPIOx, u8 Port_Byte)\r
+{\r
+ return (u8)(GPIOx->PD >> Port_Byte);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : GPIO_WordRead\r
+* Description : Read the desired port word value\r
+* Input 1 : Selected GPIO port\r
+* Output : None\r
+* Return : The selected PD register value\r
+*******************************************************************************/\r
+inline u16 GPIO_WordRead(GPIO_TypeDef *GPIOx)\r
+{\r
+ return GPIOx->PD;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : GPIO_BitWrite\r
+* Description : Set or reset the selected port pin\r
+* Input 1 : Selected GPIO port\r
+* Input 2 : Pin number\r
+* Input 3 : bit value\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void GPIO_BitWrite(GPIO_TypeDef *GPIOx, u8 Port_Pin, u8 Port_Val);\r
+\r
+/*******************************************************************************\r
+* Function Name : GPIO_ByteWrite\r
+* Description : Write byte value to the selected PD register\r
+* Input 1 : Selected GPIO port\r
+* Input 2 : GPIO_MSB or GPIO_LSB\r
+* Input 3 : Byte value\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void GPIO_ByteWrite(GPIO_TypeDef *GPIOx, u8 Port_Byte, u8 Port_Val);\r
+\r
+/*******************************************************************************\r
+* Function Name : GPIO_WordWrite\r
+* Description : Write word value to the selected PD register\r
+* Input 1 : Selected GPIO port\r
+* Input 2 : Value\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+inline void GPIO_WordWrite(GPIO_TypeDef *GPIOx, u16 Port_Val)\r
+{\r
+ GPIOx->PD = Port_Val;\r
+}\r
+\r
+#endif /* __gpio_H */\r
+\r
+/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2003 STMicroelectronics ********************\r
+* File Name : pcu.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 30/05/2003\r
+* Description : This file contains all the functions prototypes for the\r
+* PCU software library.\r
+********************************************************************************\r
+* History:\r
+* 30/11/2004 : V2.0\r
+* 14/07/2004 : V1.3\r
+* 01/01/2004 : V1.2\r
+*******************************************************************************\r
+ THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH\r
+ CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+ AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT\r
+ OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT\r
+ OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION\r
+ CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+#ifndef __PCU_H\r
+#define __PCU_H\r
+\r
+#include "71x_map.h"\r
+\r
+typedef enum\r
+{\r
+ PCU_WREN = 0x8000,\r
+ PCU_VROK = 0x1000\r
+} PCU_Flags;\r
+\r
+typedef enum\r
+{\r
+ PCU_STABLE,\r
+ PCU_UNSTABLE\r
+} PCU_VR_Status;\r
+\r
+typedef enum\r
+{\r
+ PCU_MVR = 0x0008,\r
+ PCU_LPR = 0x0020\r
+} PCU_VR;\r
+\r
+typedef enum\r
+{\r
+ WFI_CLOCK2_16,\r
+ WFI_EXTERNAL\r
+} WFI_CLOCKS;\r
+\r
+typedef enum\r
+{\r
+ PCU_SLOW,\r
+ PCU_STOP,\r
+ PCU_STANDBY\r
+} LPM_MODES;\r
+\r
+\r
+// VR_OK : Voltage Regulator OK\r
+#define PCU_VROK_Mask 0x1000\r
+\r
+// Main Voltage Regulator\r
+#define PCU_MVR_Mask 0x0008\r
+\r
+// Low Power Voltage Regulator\r
+#define PCU_LPR_Mask 0x0020\r
+\r
+// PCU register Write Enable Bit\r
+#define PCU_WREN_Mask 0x8000\r
+\r
+// Low Voltage Detector\r
+#define PCU_LVD_Mask 0x0100\r
+\r
+// Power Down Flag\r
+#define PCU_PWRDWN_Mask 0x0040\r
+\r
+// WFI Mode Clock Selection Bit\r
+#define PCU_WFI_CKSEL_Mask 0x00000002\r
+\r
+// Halt Mode Enable Bit\r
+#define PCU_EN_HALT_Mask 0x00000800\r
+\r
+// Halt Mode Flag\r
+#define PCU_HALT_Mask 0x0002\r
+\r
+// Stop Mode Enable Bit\r
+#define PCU_STOP_EN_Mask 0x00000400\r
+\r
+// Low Power Regulator in Wait For interrupt Mode\r
+#define PCU_LPRWFI_Mask 0x0020\r
+\r
+// Low Power Mode in Wait For interrupt Mode\r
+#define PCU_LPOWFI_Mask 0x00000001\r
+\r
+// Software Reset Enable\r
+#define PCU_SRESEN_Mask 0x00000001\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name : PCU_MVRStatus\r
+* Description : This routine is used to check the Main Voltage Regulator\r
+* : NewState.\r
+* Input : None\r
+* Return : STABLE, UNSTABLE\r
+*******************************************************************************/\r
+inline PCU_VR_Status PCU_MVRStatus ( void )\r
+{\r
+ return (PCU->PWRCR & PCU_VROK_Mask) == 0x00 ? PCU_UNSTABLE : PCU_STABLE;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : PCU_FlagStatus\r
+* Description : This routine is used to return the PCU register flag\r
+* Input 1 : The flag to get\r
+* Return : RESET, SET\r
+*******************************************************************************/\r
+inline FlagStatus PCU_FlagStatus ( PCU_Flags Xflag )\r
+{\r
+ return ( PCU->PWRCR & Xflag ) == 0x00 ? RESET : SET;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : PCU_VRConfig\r
+* Description : This routine is used to configure PCU voltage regultors\r
+* Input 1 : MVR : Main voltage Regulator\r
+ LPR : Low Power Regulator\r
+* Input 2 : ENABLE : Enable the Voltage Regulator\r
+ DISABLE: Disable ( ByPass ) the VR\r
+* Return : None\r
+*******************************************************************************/\r
+void PCU_VRConfig ( PCU_VR xVR, FunctionalState NewState );\r
+\r
+/*******************************************************************************\r
+* Function Name : PCU_VRStatus\r
+* Description : This routine is used to get the PCU voltage regultors status\r
+* Input : MVR : Main voltage Regulator\r
+ LPR : Low Power Regulator\r
+* Return : ENABLE : Enable the Voltage Regulator\r
+ DISABLE: Disable ( ByPass ) the VR\r
+*******************************************************************************/\r
+inline FunctionalState PCU_VRStatus ( PCU_VR xVR )\r
+{\r
+ return ( PCU->PWRCR & xVR ) == 0 ? ENABLE : DISABLE;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : PCU_LVDDisable\r
+* Description : This routine is used to disable the Low Voltage Detector.\r
+* Input : None\r
+* Return : None\r
+*******************************************************************************/\r
+inline void PCU_LVDDisable ( void )\r
+{\r
+ PCU->PWRCR |= PCU_WREN_Mask; // Unlock Power Control Register\r
+ PCU->PWRCR |= PCU_LVD_Mask; // Set the LVD DIS Flag\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : PCU_LVDStatus\r
+* Description : This routine is used to get the LVD NewState.\r
+* Input : None\r
+* Return : ENABLE, DISABLE\r
+*******************************************************************************/\r
+inline FunctionalState PCU_LVDStatus ( void )\r
+{\r
+ return ( PCU->PWRCR & PCU_LVD_Mask ) == 0 ? ENABLE : DISABLE;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : PCU_WFIEnter\r
+* Description : This routine is used to force the Device to enter in WFI mode\r
+* Input 1 : CLOCK2_16 : Clock2_16 as system clock for WFI mode\r
+* EXTERNAL : external clock as system clock for WFI mode\r
+* Input 2 : ENABLE : Enable Low Power Regulator during Wait For Interrupt Mode\r
+* DISABLE: Disable Low Power Regulator during Wait For Interrupt Mode\r
+* Input 3 : ENABLE : Enable Low Power Mode during Wait For Interrupt Mode\r
+* DISABLE: Disable Low Power Mode during Wait For Interrupt Mode\r
+* Return : None\r
+*******************************************************************************/\r
+void PCU_WFIEnter ( WFI_CLOCKS Xclock, FunctionalState Xlpr, FunctionalState Xlpm );\r
+\r
+/*******************************************************************************\r
+* Function Name : PCU_LPMEnter\r
+* Description : This routine is used to force the Device to enter low\r
+* power mode\r
+* Input : SLOW : Slow Mode\r
+ STOP : Stop Mode\r
+ HALT : Halt Mode\r
+* Return : None\r
+*******************************************************************************/\r
+void PCU_LPMEnter ( LPM_MODES Xmode);\r
+\r
+#endif // __PCU_H\r
+\r
+/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2003 STMicroelectronics ********************\r
+* File Name : rccu.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 28/07/2003\r
+* Description : This file contains all the functions prototypes for the\r
+* RCCU software library.\r
+********************************************************************************\r
+* History:\r
+* 30/11/2004 : V2.0\r
+* 14/07/2004 : V1.3\r
+* 01/01/2004 : V1.2\r
+*******************************************************************************\r
+ THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH\r
+ CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+ AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT\r
+ OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT\r
+ OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION\r
+ CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+#ifndef __RCCU_H\r
+#define __RCCU_H\r
+\r
+#include "71x_map.h"\r
+\r
+typedef enum {\r
+ RCCU_DEFAULT=0x00,\r
+ RCCU_RCLK_2 =0x01,\r
+ RCCU_RCLK_4 =0x02,\r
+ RCCU_RCLK_8 =0x03\r
+ } RCCU_Clock_Div;\r
+\r
+typedef enum {\r
+ RCCU_PLL1_Output,\r
+ RCCU_CLOCK2_16,\r
+ RCCU_CLOCK2,\r
+ RCCU_RTC_CLOCK\r
+ } RCCU_RCLK_Clocks;\r
+\r
+\r
+ typedef enum {\r
+ RCCU_PLL1_Mul_12=0x01,\r
+ RCCU_PLL1_Mul_16=0x03,\r
+ RCCU_PLL1_Mul_20=0x00,\r
+ RCCU_PLL1_Mul_24=0x02\r
+ } RCCU_PLL1_Mul;\r
+\r
+typedef enum {\r
+ RCCU_PLL2_Mul_12=0x01,\r
+ RCCU_PLL2_Mul_16=0x03,\r
+ RCCU_PLL2_Mul_20=0x00,\r
+ RCCU_PLL2_Mul_28=0x02\r
+ } RCCU_PLL2_Mul;\r
+\r
+typedef enum {\r
+ RCCU_Div_1=0x00,\r
+ RCCU_Div_2=0x01,\r
+ RCCU_Div_3=0x02,\r
+ RCCU_Div_4=0x03,\r
+ RCCU_Div_5=0x04,\r
+ RCCU_Div_6=0x05,\r
+ RCCU_Div_7=0x06\r
+ } RCCU_PLL_Div;\r
+\r
+typedef enum {\r
+ RCCU_PLL2_Output = 0x01,\r
+ RCCU_USBCK = 0x00\r
+ } RCCU_USB_Clocks;\r
+\r
+typedef enum {\r
+ RCCU_CLK2,\r
+ RCCU_RCLK,\r
+ RCCU_MCLK,\r
+ RCCU_PCLK,\r
+ RCCU_FCLK\r
+ } RCCU_Clocks;\r
+\r
+typedef enum {\r
+ RCCU_PLL1_LOCK_IT = 0x0080,\r
+ RCCU_CKAF_IT = 0x0100,\r
+ RCCU_CK2_16_IT = 0x0200,\r
+ RCCU_STOP_IT = 0x0400\r
+ } RCCU_Interrupts;\r
+\r
+typedef enum {\r
+ RCCU_PLL1_LOCK = 0x0002,\r
+ RCCU_CKAF_ST = 0x0004,\r
+ RCCU_PLL1_LOCK_I = 0x0800,\r
+ RCCU_CKAF_I = 0x1000,\r
+ RCCU_CK2_16_I = 0x2000,\r
+ RCCU_STOP_I = 0x4000\r
+ } RCCU_Flags;\r
+\r
+typedef enum {\r
+ RCCU_ExternalReset = 0x00000000,\r
+ RCCU_SoftwareReset = 0x00000020,\r
+ RCCU_WDGReset = 0x00000040,\r
+ RCCU_RTCAlarmReset = 0x00000080,\r
+ RCCU_LVDReset = 0x00000200,\r
+ RCCU_WKPReset = 0x00000400\r
+ }RCCU_ResetSources;\r
+\r
+\r
+#define RCCU_Div2_Mask 0x00008000\r
+#define RCCU_Div2_Index 0x0F\r
+#define RCCU_FACT_Mask 0x0003\r
+\r
+#define RCCU_FACT1_Mask 0x0003\r
+\r
+#define RCCU_FACT2_Mask 0x0300\r
+#define RCCU_FACT2_Index 0x08\r
+\r
+#define RCCU_MX_Mask 0x00000030\r
+#define RCCU_MX_Index 0x04\r
+\r
+#define RCCU_DX_Mask 0x00000007\r
+\r
+#define RCCU_FREEN_Mask 0x00000080\r
+\r
+#define RCCU_CSU_CKSEL_Mask 0x00000001\r
+\r
+#define RCCU_CK2_16_Mask 0x00000008\r
+\r
+#define RCCU_CKAF_SEL_Mask 0x00000004\r
+\r
+#define RCCU_LOCK_Mask 0x00000002\r
+\r
+#define RCCU_USBEN_Mask 0x0100\r
+#define RCCU_USBEN_Index 0x08\r
+#define RCCU_ResetSources_Mask 0x000006E0\r
+\r
+// RTC Oscillator Frequency value = 32 768 Hz\r
+#define RCCU_RTC_Osc 32768\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name : RCCU_Div2Config\r
+* Description : Enables/Disables the clock division by two\r
+* Input : NewState : ENABLE or DISABLE\r
+* Return : None\r
+*******************************************************************************/\r
+inline void RCCU_Div2Config ( FunctionalState NewState )\r
+{\r
+ if (NewState == ENABLE) RCCU->CFR |= RCCU_Div2_Mask;\r
+ else RCCU->CFR &= ~RCCU_Div2_Mask;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCCU_Div2Status\r
+* Description : Gets the Div2 Flag status\r
+* Input : None\r
+* Input : FlagStatus\r
+* Return : None\r
+*******************************************************************************/\r
+inline FlagStatus RCCU_Div2Status ( void )\r
+{\r
+ return (RCCU->CFR & RCCU_Div2_Mask) == 0 ? RESET : SET;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCCU_MCLKConfig\r
+* Description : Selects the division factor for RCLK to obtain the\r
+* MCLK clock for the CPU\r
+* Input : New_Clock : RCCU_DEFAULT, RCCU_RCLK_2, RCCU_RCLK_4, RCCU_RCLK_8\r
+* Return : None\r
+*******************************************************************************/\r
+inline void RCCU_MCLKConfig ( RCCU_Clock_Div New_Clock )\r
+{\r
+ PCU->MDIVR = ( PCU->MDIVR & ~RCCU_FACT_Mask ) | New_Clock;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCCU_FCLKConfig\r
+* Description : Selects the division factor for RCLK to obtain the\r
+* FCLK clock for the APB1 fast peripherals (PCLK1).\r
+* Input : New_Clock : RCCU_DEFAULT, RCCU_RCLK_2,\r
+* RCCU_RCLK_4, RCCU_RCLK_8\r
+* Return : None\r
+*******************************************************************************/\r
+inline void RCCU_FCLKConfig ( RCCU_Clock_Div New_Clock )\r
+{\r
+ PCU->PDIVR = ( PCU->PDIVR & ~RCCU_FACT1_Mask ) | New_Clock;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCCU_PCLKConfig\r
+* Description : Selects the division factor for RCLK to obtain the\r
+* PCLK clock for the APB2 peripherals (PCLK2).\r
+* Input : New_Clock : RCCU_DEFAULT, RCCU_RCLK_2,\r
+* RCCU_RCLK_4, RCCU_RCLK_8\r
+* Return : None\r
+*******************************************************************************/\r
+inline void RCCU_PCLKConfig ( RCCU_Clock_Div New_Clock )\r
+{\r
+ PCU->PDIVR =(PCU->PDIVR & ~RCCU_FACT2_Mask)|(New_Clock << RCCU_FACT2_Index);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCCU_PLL1Config\r
+* Description : Configures the PLL1 div & mul factors.\r
+* Input : New_Mul : RCCU_Mul_12, RCCU_Mul_16, RCCU_Mul_20, RCCU_Mul_28\r
+* : New_Div : RCCU_Div_1, RCCU_Div_2, RCCU_Div_3,\r
+* RCCU_Div_4, RCCU_Div_5, RCCU_Div_6, RCCU_Div_7\r
+* Return : None\r
+*******************************************************************************/\r
+void RCCU_PLL1Config ( RCCU_PLL1_Mul New_Mul, RCCU_PLL_Div New_Div );\r
+\r
+/*******************************************************************************\r
+* Function Name : RCCU_PLL2Config\r
+* Description : Configures the PLL2 div & mul factors.\r
+* Input : New_Mul : RCCU_Mul_12, RCCU_Mul_16, RCCU_Mul_20, RCCU_Mul_28\r
+* : New_Div : RCCU_Div_1, RCCU_Div_2, RCCU_Div_3, RCCU_Div_4,\r
+* RCCU_Div_5, RCCU_Div_6, RCCU_Div_7\r
+* Return : None\r
+*******************************************************************************/\r
+void RCCU_PLL2Config ( RCCU_PLL2_Mul New_Mul, RCCU_PLL_Div New_Div );\r
+\r
+/*******************************************************************************\r
+* Function Name : RCCU_RCLKSourceConfig\r
+* Description : Selects the RCLK source clock\r
+* Input : New_Clock : RCCU_PLL1_OutPut, RCCU_CLOCK2_16, RCCU_CLOCK2\r
+* Return : None\r
+*******************************************************************************/\r
+void RCCU_RCLKSourceConfig ( RCCU_RCLK_Clocks New_Clock );\r
+\r
+/*******************************************************************************\r
+* Function Name : RCCU_RCLKClockSource\r
+* Description : Returns the current RCLK source clock\r
+* Input : None\r
+* Return : RCCU_PLL1_Output, RCCU_CLOCK2_16, RCCU_CLOCK2\r
+*******************************************************************************/\r
+RCCU_RCLK_Clocks RCCU_RCLKClockSource ( void );\r
+\r
+/*******************************************************************************\r
+* Function Name : RCCU_USBCLKConfig\r
+* Description : Selects the USB source clock\r
+* Input : New_Clock : RCCU_PLL2_Output, RCCU_USBCK\r
+* Return : None\r
+*******************************************************************************/\r
+inline void RCCU_USBCLKConfig ( RCCU_USB_Clocks New_Clock )\r
+{\r
+ PCU->PLL2CR = (PCU->PLL2CR & ~RCCU_USBEN_Mask)|(New_Clock << RCCU_USBEN_Index);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCCU_USBClockSource\r
+* Description : Gets the USB source clock\r
+* Input : None\r
+* Return : RCCU_USB_Clocks\r
+*******************************************************************************/\r
+RCCU_USB_Clocks RCCU_USBClockSource ( void );\r
+\r
+/*******************************************************************************\r
+* Function Name : RCCU_FrequencyValue\r
+* Description : Calculates & Returns any internal RCCU clock freuqency\r
+* passed in parametres\r
+* Input : RCCU_Clocks : RCCU_CLK2, RCCU_RCLK, RCCU_MCLK,\r
+* RCCU_PCLK, RCCU_FCLK\r
+* Return : u32\r
+*******************************************************************************/\r
+u32 RCCU_FrequencyValue ( RCCU_Clocks Internal_Clk );\r
+\r
+/*******************************************************************************\r
+* Function Name : RCCU_ITConfig\r
+* Description : Configures the RCCU interrupts\r
+* Input : RCCU interrupts : RCCU_CK2_16_IT, RCCU_CKAF_IT,\r
+* RCCU_PLL1_LOCK_IT\r
+* Return : None\r
+*******************************************************************************/\r
+inline void RCCU_ITConfig ( RCCU_Interrupts RCCU_IT, FunctionalState NewState)\r
+{\r
+ if (NewState == ENABLE) RCCU->CCR |= RCCU_IT; else RCCU->CCR &= ~RCCU_IT;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCCU_FlagStatus\r
+* Description : Checks the RCCU clock flag register status\r
+* Input : RCCU Flags : RCCU_CK2_16, RCCU_CKAF, RCCU_PLL1_LOCK\r
+* Return : FlagStatus : SET or RESET\r
+*******************************************************************************/\r
+inline FlagStatus RCCU_FlagStatus ( RCCU_Flags RCCU_flag )\r
+{\r
+ return (RCCU->CFR & RCCU_flag) == 0 ? RESET : SET;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCCU_FlagClear\r
+* Description : Clears a specified flag in the RCCU registers\r
+* Input : RCCU Flags : RCCU_CK2_16, RCCU_CKAF, RCCU_PLL1_LOCK\r
+* Return : None\r
+*******************************************************************************/\r
+inline void RCCU_FlagClear ( RCCU_Interrupts RCCU_IT )\r
+{\r
+ RCCU->CFR |= RCCU_IT;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCCU_ResetSources\r
+* Description : Return the source of the system reset\r
+* Input : None\r
+* Return : The reset source\r
+*******************************************************************************/\r
+inline RCCU_ResetSources RCCU_ResetSource ()\r
+{\r
+\r
+ switch(RCCU->CFR & RCCU_ResetSources_Mask)\r
+ {\r
+ case 0x00000020: return RCCU_SoftwareReset;\r
+ case 0x00000040: return RCCU_WDGReset;\r
+ case 0x00000080: return RCCU_RTCAlarmReset;\r
+ case 0x00000200: return RCCU_LVDReset;\r
+ case 0x00000400: return RCCU_WKPReset;\r
+ default : return RCCU_ExternalReset;\r
+ }\r
+}\r
+\r
+#endif // __RCCU_H\r
+\r
+/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2003 STMicroelectronics ********************\r
+* File Name : tim.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 08/09/2003\r
+* Description : This file contains all the functions prototypes for the\r
+* TIM software library.\r
+********************************************************************************\r
+* History:\r
+* 30/11/2004 : V2.0\r
+* 14/07/2004 : V1.3\r
+* 01/01/2004 : V1.2\r
+*******************************************************************************\r
+ THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH\r
+ CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+ AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT\r
+ OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT\r
+ OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION\r
+ CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+#ifndef __TIM_H\r
+#define __TIM_H\r
+\r
+#include "71x_map.h"\r
+\r
+typedef enum { TIM_EXTERNAL,\r
+ TIM_INTERNAL\r
+ } TIM_Clocks;\r
+\r
+typedef enum { TIM_RISING,\r
+ TIM_FALLING\r
+ } TIM_Clock_Edges;\r
+\r
+typedef enum { TIM_CHANNEL_A,\r
+ TIM_CHANNEL_B\r
+ } TIM_Channels;\r
+\r
+typedef enum { TIM_WITH_IT,\r
+ TIM_WITHOUT_IT\r
+ } TIM_IT_Mode;\r
+\r
+typedef enum { TIM_TIMING,\r
+ TIM_WAVE\r
+ } TIM_OC_Modes;\r
+\r
+typedef enum { TIM_HIGH,\r
+ TIM_LOW\r
+ } TIM_Logic_Levels;\r
+\r
+typedef enum { TIM_START,\r
+ TIM_STOP,\r
+ TIM_CLEAR\r
+ } TIM_CounterOperations;\r
+\r
+typedef enum { TIM_ICFA = 0x8000,\r
+ TIM_OCFA = 0x4000,\r
+ TIM_TOF = 0x2000,\r
+ TIM_ICFB = 0x1000,\r
+ TIM_OCFB = 0x0800\r
+ } TIM_Flags;\r
+\r
+typedef struct { u16 Pulse;\r
+ u16 Period;\r
+ } PWMI_parameters;\r
+\r
+#define TIM_ECKEN_Mask 0x0001\r
+#define TIM_EXEDG_Mask 0x0002\r
+\r
+#define TIM_IEDGA_Mask 0x0004\r
+#define TIM_IEDGB_Mask 0x0008\r
+\r
+#define TIM_PWM_Mask 0x0010\r
+\r
+#define TIM_OMP_Mask 0x0020\r
+\r
+#define TIM_OCAE_Mask 0x0040\r
+#define TIM_OCBE_Mask 0x0080\r
+\r
+#define TIM_OLVLA_Mask 0x0100\r
+#define TIM_OLVLB_Mask 0x0200\r
+\r
+#define TIM_FOLVA_Mask 0x0400\r
+#define TIM_FOLVB_Mask 0x0800\r
+\r
+#define TIM_PWMI_Mask 0x4000\r
+\r
+#define TIM_EN_Mask 0x8000\r
+\r
+#define TIM_OCBIE_mask 0x0800\r
+#define TIM_ICBIE_Mask 0x1000\r
+#define TIM_TOE_Mask 0x2000\r
+#define TIM_ICAIE_Mask 0x8000\r
+#define TIM_OCAIE_mask 0x4000\r
+\r
+#define TIM_ICA_IT 0x8000 // Input Capture Channel A\r
+#define TIM_OCA_IT 0x4000 // Output Compare Channel A\r
+#define TIM_TO_IT 0x2000 // Timer OverFlow\r
+#define TIM_ICB_IT 0x1000 // Input Capture Channel B\r
+#define TIM_OCB_IT 0x0800 // Input Capture Channel A\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_Init\r
+* Description : This routine is used to Initialize the TIM peripheral\r
+* Input : TIM Timer to Initialize\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_Init( TIM_TypeDef *TIMx );\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_ClockSourceConfig\r
+* Description : This routine is used to configure the TIM clock source\r
+* Input : (1) TIM Timer\r
+* : (2) TIM_Clocks : Specifies the TIM source clock\r
+* - TIM_INTERNAL : The TIM is clocked by the APB2 frequency\r
+* divided by the prescaler value.\r
+* - TIM_EXTERNAL : The TIM is clocked by an external Clock\r
+* Return : None\r
+*******************************************************************************/\r
+inline void TIM_ClockSourceConfig ( TIM_TypeDef *TIMx, TIM_Clocks Xclock )\r
+{\r
+ if (Xclock==TIM_EXTERNAL) TIMx->CR1|=TIM_ECKEN_Mask; else TIMx->CR1&=~TIM_ECKEN_Mask;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_ClockSourceValue\r
+* Description : This routine is used to get the TIM clock source\r
+* Input : TIM Timer\r
+* Return : TIM_Clocks : Specifies the TIM source clock\r
+* - TIM_INTERNAL : The TIM is clocked by the APB2 frequency\r
+* divided by the prescaler value.\r
+* - TIM_EXTERNAL : The TIM is clocked by an external Clock\r
+*******************************************************************************/\r
+inline TIM_Clocks TIM_ClockSourceValue ( TIM_TypeDef *TIMx )\r
+{\r
+ return ( TIMx->CR1 & TIM_ECKEN_Mask) == 0 ? TIM_INTERNAL : TIM_EXTERNAL;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_PrescalerConfig\r
+* Description : This routine is used to configure the TIM prescaler value\r
+* ( using an internal clock )\r
+* Input : (1) TIM Timer\r
+* : (2) Prescaler ( u8 )\r
+* Return : None\r
+*******************************************************************************/\r
+inline void TIM_PrescalerConfig ( TIM_TypeDef *TIMx, u8 Xprescaler )\r
+{\r
+ TIMx->CR2 = ( TIMx->CR2 & 0xFF00 ) | Xprescaler;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_PrescalerValue\r
+* Description : This routine is used to get the TIM prescaler value\r
+* ( when using using an internal clock )\r
+* Input : TIM Timer\r
+* Return : Prescaler ( u8 )\r
+*******************************************************************************/\r
+inline u8 TIM_PrescalerValue ( TIM_TypeDef *TIMx )\r
+{\r
+ return TIMx->CR2 & 0x00FF;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_ClockLevelConfig\r
+* Description : This routine is used to configure the TIM clock level\r
+* ( using an external clock )\r
+* Input : TIM Timer\r
+* : TIM_Clock_Edges : Specifies the active adge of the external clock\r
+* - TIM_RISING : The rising edge\r
+* - TIM_FALLING : The falling edge\r
+* Return : None\r
+*******************************************************************************/\r
+inline void TIM_ClockLevelConfig ( TIM_TypeDef *TIMx, TIM_Clock_Edges Xedge )\r
+{\r
+ if (Xedge == TIM_RISING) TIMx->CR1 |= TIM_EXEDG_Mask; else TIMx->CR1 &= ~TIM_EXEDG_Mask;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_ClockLevelValue\r
+* Description : This routine is used to get the TIM clock level\r
+* Input : TIM Timer\r
+* Output : TIM_Clock_Edges : Specifies the active adge of the external clock\r
+* - TIM_RISING : The rising edge\r
+* - TIM_FALLING : The falling edge\r
+*******************************************************************************/\r
+inline TIM_Clock_Edges TIM_ClockLevelValue ( TIM_TypeDef *TIMx )\r
+{\r
+ return ( TIMx->CR1 & TIM_EXEDG_Mask ) == 0 ? TIM_FALLING : TIM_RISING;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_ICAPModeConfig\r
+* Description : This routine is used to configure the input capture feature\r
+* Input : (1) TIM Timer\r
+* : (2) Input Capture Channel ( Channel_A or Channel_B )\r
+* : (3) Active Edge : Rising edge or Falling edge.\r
+* Output : None\r
+*******************************************************************************/\r
+void TIM_ICAPModeConfig ( TIM_TypeDef *TIMx,\r
+ TIM_Channels Xchannel,\r
+ TIM_Clock_Edges Xedge );\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_ICAPValue\r
+* Description : This routine is used to get the Input Capture value\r
+* Input : (1) TIM Timer\r
+* : (2) Input Capture Channel ( Channel_A or Channel_B )\r
+* Output : None\r
+*******************************************************************************/\r
+inline u16 TIM_ICAPValue ( TIM_TypeDef *TIMx, TIM_Channels Xchannel )\r
+{\r
+ return Xchannel == TIM_CHANNEL_A ? TIMx->ICAR : TIMx->ICBR;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_OCMPModeConfig\r
+* Description : This routine is used to configure the output compare feature\r
+* Input : (1) TIM Timer\r
+* : (2) OCMP Channel ( Channel_A or Channel_B )\r
+* : (3) Pulse Length\r
+* : (4) OC_Mode : output wave, or only timing.\r
+* : (5) Level : Rising edge or Falling edge after the ==\r
+* Output : None\r
+*******************************************************************************/\r
+void TIM_OCMPModeConfig ( TIM_TypeDef *TIMx,\r
+ TIM_Channels Xchannel,\r
+ u16 XpulseLength,\r
+ TIM_OC_Modes Xmode,\r
+ TIM_Logic_Levels Xlevel );\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_OPModeConfig\r
+* Description : This routine is used to configure the one pulse mode\r
+* Input : (1) TIM Timer\r
+* : (3) XpulseLength : Length of the pulse\r
+* : (4) Level1 : Level during the pulse\r
+* : (5) Level2 : Level after the pulse\r
+* : (6) Activation Edge : High or Low on ICAP A\r
+* Output : None\r
+*******************************************************************************/\r
+void TIM_OPModeConfig ( TIM_TypeDef *TIMx,\r
+ u16 XpulseLength,\r
+ TIM_Logic_Levels XLevel1,\r
+ TIM_Logic_Levels XLevel2,\r
+ TIM_Clock_Edges Xedge );\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_PWMOModeConfig\r
+* Description : This routine is used to configure the PWM in output mode\r
+* Input : (1) TIM Timer\r
+* : (2) DutyCycle : u16\r
+* : (3) Level 1 : During the Duty Cycle\r
+* : (4) Level 2 : During the after the pulse\r
+* : (5) Full period : u16\r
+* Output : None\r
+*******************************************************************************/\r
+void TIM_PWMOModeConfig ( TIM_TypeDef *TIMx,\r
+ u16 XDutyCycle,\r
+ TIM_Logic_Levels XLevel1,\r
+ u16 XFullperiod,\r
+ TIM_Logic_Levels XLevel2\r
+ );\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_PWMInputConfig\r
+* Description : This routine is used to configure the PWM in input mode\r
+* Input : (1) TIM Timer\r
+* : (2) First Activation Edge\r
+* Output : None\r
+*******************************************************************************/\r
+void TIM_PWMIModeConfig ( TIM_TypeDef *TIMx, TIM_Clock_Edges Xedge );\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_PWMIValue\r
+* Description : This routine is used to get the PWMI values\r
+* Input : (1) TIM Timer\r
+* Output : PWMI_parameters : - u16 Dyty cycle\r
+ - u16 Full period\r
+*******************************************************************************/\r
+PWMI_parameters TIM_PWMIValue (TIM_TypeDef *TIMx );\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_CounterConfig\r
+* Description : This routine is used to start/stop and clear the selected\r
+* timer counter\r
+* Input : (1) TIM Timer\r
+* : (2) TIM_CounterOperations\r
+ TIM_START Enables or resumes the counter\r
+* TIM_STOP Stops the TIM counter\r
+* TIM_CLEAR Set the TIM counter value to FFFCh\r
+* Output : None\r
+*******************************************************************************/\r
+void TIM_CounterConfig ( TIM_TypeDef *TIMx, TIM_CounterOperations Xoperation );\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_ITConfig\r
+* Description : This routine is used to configure the TIM IT\r
+* Input : (1) TIM Timer\r
+* : (2) TIM interrupt\r
+* : (2) ENABLE / DISABLE\r
+* Output : None\r
+*******************************************************************************/\r
+inline void TIM_ITConfig ( TIM_TypeDef *TIMx, u16 New_IT, FunctionalState NewState )\r
+{\r
+ if (NewState == ENABLE) TIMx->CR2 |= New_IT; else TIMx->CR2 &= ~New_IT;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_FlagStatus\r
+* Description : This routine is used to check whether a Flag is Set.\r
+* Input : (1) TIM Timer\r
+* : (2) The TIM FLag\r
+* Output : Flag NewState\r
+*******************************************************************************/\r
+inline FlagStatus TIM_FlagStatus ( TIM_TypeDef *TIMx, TIM_Flags Xflag )\r
+{\r
+ return (TIMx->SR & Xflag) == 0 ? RESET : SET;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_FlagClear\r
+* Description : This routine is used to clear Flags.\r
+* Input : (1) TIM Timer\r
+* : (2) The TIM FLag\r
+* Output : None\r
+*******************************************************************************/\r
+inline void TIM_FlagClear ( TIM_TypeDef *TIMx, TIM_Flags Xflag )\r
+{\r
+ TIMx->SR &= ~Xflag;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_CounterValue\r
+* Description : This routine returns the timer counter value.\r
+* Input : TIM Timer\r
+* Output : The counter value\r
+*******************************************************************************/\r
+inline u16 TIM_CounterValue(TIM_TypeDef *TIMx)\r
+{\r
+ return TIMx->CNTR;\r
+}\r
+#endif // __TIM_H\r
+\r
+/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2003 STMicroelectronics ********************\r
+* File Name : uart.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 16/05/2003\r
+* Description : This file contains all the functions prototypes for the\r
+* UART software library.\r
+********************************************************************************\r
+* History:\r
+* 30/11/2004 : V2.0\r
+* 14/07/2004 : V1.3\r
+* 01/01/2004 : V1.2\r
+*******************************************************************************\r
+ THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH\r
+ CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+ AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT\r
+ OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT\r
+ OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION\r
+ CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+#ifndef _UART_H\r
+#define _UART_H\r
+\r
+#include "71x_map.h"\r
+#include "rccu.h"\r
+\r
+typedef enum\r
+{\r
+ UART_RxFIFO,\r
+ UART_TxFIFO\r
+} UARTFIFO_TypeDef;\r
+\r
+typedef enum\r
+{\r
+ UART_EVEN_PARITY = 0x0000,\r
+ UART_ODD_PARITY = 0x0020,\r
+ UART_NO_PARITY\r
+} UARTParity_TypeDef;\r
+\r
+typedef enum\r
+{\r
+ UART_0_5_StopBits = 0x00,\r
+ UART_1_StopBits = 0x08,\r
+ UART_1_5_StopBits = 0x10,\r
+ UART_2_StopBits = 0x18\r
+} UARTStopBits_TypeDef;\r
+\r
+typedef enum\r
+{\r
+ UARTM_8D = 0x01,\r
+ UARTM_7D_P = 0x03,\r
+ UARTM_9D = 0x04,\r
+ UARTM_8D_W = 0x05,\r
+ UARTM_8D_P = 0x07\r
+} UARTMode_TypeDef;\r
+\r
+\r
+#define DUMMY 0\r
+\r
+// UART flags definition\r
+#define UART_TxFull 0x0200\r
+#define UART_RxHalfFull 0x0100\r
+#define UART_TimeOutIdle 0x0080\r
+#define UART_TimeOutNotEmpty 0x0040\r
+#define UART_OverrunError 0x0020\r
+#define UART_FrameError 0x0010\r
+#define UART_ParityError 0x0008\r
+#define UART_TxHalfEmpty 0x0004\r
+#define UART_TxEmpty 0x0002\r
+#define UART_RxBufFull 0x0001\r
+\r
+// CR regiter bit definition\r
+#define UART_FIFOEnableBit 10\r
+#define UART_RxEnableBit 8\r
+#define UART_RunBit 7\r
+#define UART_LoopBackBit 6\r
+#define UART_ParityOddBit 5\r
+#define UART_StopBits 3\r
+\r
+// Stop bits definition\r
+#define UART_05StopBits 0x00\r
+#define UART_1StopBit (0x01<<3)\r
+#define UART_15StopBits (0x02<<3)\r
+#define UART_2StopBits (0x03<<3)\r
+\r
+// Modes definition\r
+#define UART_8BitsData 0x01\r
+#define UART_7BitsData 0x03\r
+#define UART_9BitsData 0x04\r
+#define UART_8BitsDataWakeUp 0x05\r
+#define UART_8BitsDataParity 0x07\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_Init\r
+* Description : This function initializes the selected UART.\r
+* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void UART_Init(UART_TypeDef *UARTx);\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_ModeConfig\r
+* Description : This function configures the mode of the selected UART.\r
+* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART\r
+* Input 2 : The UART mode\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+inline void UART_ModeConfig(UART_TypeDef *UARTx, UARTMode_TypeDef UART_Mode)\r
+{\r
+ UARTx->CR = (UARTx->CR&0xFFF8)|(u16)UART_Mode;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_BaudRateConfig\r
+* Description : This function configures the baud rate of the selected UART.\r
+* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART\r
+* Input 2 : The baudrate value\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void UART_BaudRateConfig(UART_TypeDef *UARTx, u32 BaudRate);\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_ParityConfig\r
+* Description : This function configures the data parity of the selected UART.\r
+* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART\r
+* Input 2 : The parity type\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+inline void UART_ParityConfig(UART_TypeDef *UARTx, UARTParity_TypeDef Parity)\r
+{\r
+ UARTx->CR = (UARTx->CR&0xFFDF)|(u16)Parity;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_StopBitsConfig\r
+* Description : This function configures the number of stop bits of the\r
+* selected UART.\r
+* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART\r
+* Input 2 : The number of stop bits\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+inline void UART_StopBitsConfig(UART_TypeDef *UARTx, UARTStopBits_TypeDef StopBits)\r
+{\r
+ UARTx->CR = (UARTx->CR&0xFFE7)|(u16)StopBits;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_Config\r
+* Description : This function configures the baudrate, the mode, the data\r
+* parity and the number of stop bits of the selected UART.\r
+* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART\r
+* Input 2 : The baudrate value\r
+* Input 3 : The parity type\r
+* Input 4 : The number of stop bits\r
+* Input 5 : The UART mode\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void UART_Config(UART_TypeDef *UARTx, u32 BaudRate, UARTParity_TypeDef Parity,\r
+ UARTStopBits_TypeDef StopBits, UARTMode_TypeDef Mode);\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_ItConfig\r
+* Description : This function enables or disables the interrupts of the\r
+* selected UART.\r
+* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART\r
+* Input 2 : The new interrupt flag\r
+* Input 3 : ENABLE or DISABLE\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void UART_ItConfig(UART_TypeDef *UARTx, u16 UART_Flag, FunctionalState NewState);\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_FifoConfig\r
+* Description : This function enables or disables the Rx and Tx FIFOs of\r
+* the selected UART.\r
+* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART\r
+* Input 2 : ENABLE or DISABLE\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void UART_FifoConfig(UART_TypeDef *UARTx, FunctionalState NewState);\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_FifoReset\r
+* Description : This function resets the Rx and the Tx FIFOs of the\r
+* selected UART.\r
+* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART\r
+* Input 2 : RxFIFO or TxFIFO\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void UART_FifoReset(UART_TypeDef *UARTx, UARTFIFO_TypeDef FIFO);\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_LoopBackConfig\r
+* Description : This function enables or disables the loop back mode of\r
+* the selected UART.\r
+* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART\r
+* Input 2 : ENABLE or DISABLE\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void UART_LoopBackConfig(UART_TypeDef *UARTx, FunctionalState NewState);\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_TimeOutPeriodConfig\r
+* Description : This function configure the Time Out Period.\r
+* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART\r
+* Input 2 : The time-out period value\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+inline void UART_TimeOutPeriodConfig(UART_TypeDef *UARTx, u16 TimeOutPeriod)\r
+{\r
+ UARTx->TOR = TimeOutPeriod;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_GuardTimeConfig\r
+* Description : This function configure the Guard Time.\r
+* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART\r
+* Input 2 : The guard time value\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+inline void UART_GuardTimeConfig(UART_TypeDef *UARTx, u16 GuardTime)\r
+{\r
+ UARTx->GTR = GuardTime;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_RxConfig\r
+* Description : This function enable and disable the UART data reception.\r
+* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART\r
+* Input 2 : ENABLE or DISABLE\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void UART_RxConfig(UART_TypeDef *UARTx, FunctionalState NewState);\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_OnOffConfig\r
+* Description : This function sets On/Off the selected UART.\r
+* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART\r
+* Input 2 : ENABLE or DISABLE\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void UART_OnOffConfig(UART_TypeDef *UARTx, FunctionalState NewState);\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_ByteSend\r
+* Description : This function sends a data byte to the selected UART.\r
+* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART\r
+* Input 2 : A pointer to the data byte to send\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void UART_ByteSend(UART_TypeDef *UARTx, u8 *Data);\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_9BitByteSend\r
+* Description : This function sends a 9 bits data byte to the selected UART.\r
+* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART\r
+* Input 2 : A pointer to the data to send\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void UART_9BitByteSend(UART_TypeDef *UARTx, u16 *Data);\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_DataSend\r
+* Description : This function sends several data bytes to the selected UART.\r
+* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART\r
+* Input 2 : A pointer to the data to send\r
+* Input 3 : The data length in bytes\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void UART_DataSend(UART_TypeDef *UARTx, u8 *Data, u8 DataLength);\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_9BitDataSend\r
+* Description : This function sends several 9 bits data bytes to the selected UART.\r
+* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART\r
+* Input 2 : A pointer to the data to send\r
+* Input 3 : The data length\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void UART_9BitDataSend(UART_TypeDef *UARTx, u16 *Data, u8 DataLength);\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_StringSend\r
+* Description : This function sends a string to the selected UART.\r
+* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART\r
+* Input 2 : A pointer to the string to send\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void UART_StringSend(UART_TypeDef *UARTx, u8 *String);\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_ByteReceive\r
+* Description : This function gets a data byte from the selected UART.\r
+* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART\r
+* Input 2 : A pointer to the buffer where the data will be stored\r
+* Input 3 : The time-out period\r
+* Output : The received data\r
+* Return : The UARTx.SR register contents\r
+*******************************************************************************/\r
+u16 UART_ByteReceive(UART_TypeDef *UARTx, u8 *Data, u8 TimeOut);\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_9BitByteReceive\r
+* Description : This function gets a 9 bits data byte from the selected UART.\r
+* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART\r
+* Input 2 : A pointer to the buffer where the data will be stored\r
+* Input 3 : The time-out period value\r
+* Output : The received data\r
+* Return : The UARTx.SR register contents\r
+*******************************************************************************/\r
+u16 UART_9BitByteReceive(UART_TypeDef *UARTx, u16 *Data, u8 TimeOut);\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_DataReceive\r
+* Description : This function gets 8 bits data bytes from the selected UART.\r
+* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART\r
+* Input 2 : A pointer to the buffer where the data will be stored\r
+* Input 3 : The data length\r
+* Input 4 : The time-out period value\r
+* Output : The received data\r
+* Return : The UARTx.SR register contents\r
+*******************************************************************************/\r
+u16 UART_DataReceive(UART_TypeDef *UARTx, u8 *Data, u8 DataLength, u8 TimeOut);\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_9BitDataReceive\r
+* Description : This function gets 9 bits data bytes from the selected UART.\r
+* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART\r
+* Input 2 : A pointer to the buffer where the data will be stored\r
+* Input 3 : The data length\r
+* Input 4 : The time-out value\r
+* Output : The received data\r
+* Return : The UARTx.SR register contents\r
+*******************************************************************************/\r
+u16 UART_9BitDataReceive(UART_TypeDef *UARTx, u16 *Data, u8 DataLength, u8 TimeOut);\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_StringReceive\r
+* Description : This function gets 8 bits data bytes from the selected UART.\r
+* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART\r
+* Input 2 : A pointer to the buffer where the string will be stored\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+u16 UART_StringReceive(UART_TypeDef *UARTx, u8 *Data);\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_FlagStatus\r
+* Description : This function gets the flags status of the selected UART.\r
+* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+inline u16 UART_FlagStatus(UART_TypeDef *UARTx)\r
+{\r
+ return UARTx->SR;\r
+}\r
+\r
+#ifdef USE_SERIAL_PORT\r
+/*******************************************************************************\r
+* Function Name : sendchar\r
+* Description : This function sends a character to the selected UART.\r
+* Input 1 : A pointer to the character to send.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void sendchar( char *ch );\r
+#endif /* USE_SERIAL_PORT */\r
+\r
+#endif /* _UART_H */\r
+\r
+/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2003 STMicroelectronics ********************\r
+* File Name : wdg.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 25/08/2003\r
+* Description : This file contains all the functions prototypes for the\r
+* WDG software library.\r
+********************************************************************************\r
+* History:\r
+* 30/11/2004 : V2.0\r
+* 14/07/2004 : V1.3\r
+* 01/01/2004 : V1.2\r
+*******************************************************************************\r
+ THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH\r
+ CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+ AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT\r
+ OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT\r
+ OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION\r
+ CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+#ifndef __WDG_H\r
+#define __WDG_H\r
+\r
+#include "71x_map.h"\r
+#include "rccu.h"\r
+\r
+/*******************************************************************************\r
+* Function Name : WDG_Enable\r
+* Description : Enable the Watchdog Mode\r
+* Input : None\r
+* Return : None\r
+*******************************************************************************/\r
+inline void WDG_Enable ( void )\r
+{\r
+ WDG->CR |= 0x01;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : WDG_CntRefresh\r
+* Description : Refresh and update the WDG counter to avoid a system reset.\r
+* Input : None\r
+* Return : None\r
+*******************************************************************************/\r
+inline void WDG_CntRefresh ( void )\r
+{\r
+ //write the first value in the key register\r
+ WDG->KR = 0xA55A;\r
+ //write the consecutive value\r
+ WDG->KR = 0x5AA5;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : WDG_PrescalerConfig\r
+* Description : Set the counter prescaler value.\r
+* Divide the counter clock by (Prescaler + 1)\r
+* Input : Prescaler data value (8 bit)\r
+* Return : None\r
+*******************************************************************************/\r
+inline void WDG_PrescalerConfig ( u8 Prescaler )\r
+{\r
+ WDG->PR = Prescaler;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : WDG_CntReloadUpdate\r
+* Description : Update the counter pre-load value.\r
+* Input : Pre-load data value (16 bit)\r
+* Return : None\r
+*******************************************************************************/\r
+inline void WDG_CntReloadUpdate ( u16 PreLoadValue )\r
+{\r
+ WDG->VR = PreLoadValue;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : WDG_PeriodValueConfig\r
+* Description : Set the prescaler and counter reload value based on the\r
+* time needed\r
+* Input : Amount of time (us) needed, peripheral clock2 value\r
+* Return : None\r
+*******************************************************************************/\r
+void WDG_PeriodValueConfig ( u32 Time );\r
+\r
+/*******************************************************************************\r
+* Function Name : WDG_CntOnOffConfig\r
+* Description : Start or stop the free auto-reload timer to countdown.\r
+* Input : ENABLE or DISABLE\r
+* Return : None\r
+*******************************************************************************/\r
+inline void WDG_CntOnOffConfig ( FunctionalState NewState )\r
+{\r
+ if (NewState == ENABLE) WDG->CR |= 0x0002; else WDG->CR &= ~0x0002;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : WDG_ECITConfig\r
+* Description : Enable or Disable the end of count interrupt\r
+* Input : ENABLE or DISABLE\r
+* Return : None\r
+*******************************************************************************/\r
+inline void WDG_ECITConfig (FunctionalState NewState)\r
+{\r
+ if (NewState == ENABLE) WDG->MR |= 0x0001; else WDG->MR &= ~0x0001;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : WDG_ECFlagClear\r
+* Description : Clear the end of count flag\r
+* Input : None\r
+* Return : None\r
+*******************************************************************************/\r
+inline void WDG_ECFlagClear ( void )\r
+{\r
+ WDG->SR = 0x0000;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : WDG_ECStatus\r
+* Description : Return the end of count status\r
+* Input : None\r
+* Return : NewState value\r
+*******************************************************************************/\r
+inline u16 WDG_ECStatus ( void )\r
+{\r
+ return WDG->SR;\r
+}\r
+\r
+#endif // __WDG_H\r
+\r
+/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2003 STMicroelectronics ********************\r
+* File Name : rccu.c\r
+* Author : MCD Application Team\r
+* Date First Issued : 07/28/2003\r
+* Description : This file provides all the RCCU software functions\r
+********************************************************************************\r
+* History:\r
+* 30/11/2004 : V2.0\r
+* 14/07/2004 : V1.3\r
+* 01/01/2004 : V1.2\r
+*******************************************************************************\r
+ THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH\r
+ CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+ AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT\r
+ OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT\r
+ OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION\r
+ CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+#include "rccu.h"\r
+\r
+/*******************************************************************************\r
+* Function Name : RCCU_PLL1Config\r
+* Description : Configures the PLL1 div & mul factors.\r
+* Input : New_Mul ( RCCU_PLL1_Mul_12, RCCU_PLL1_Mul_16, RCCU_PLL1_Mul_20,\r
+* RCCU_PLL1_Mul_24 )\r
+* : New_Div ( RCCU_Div_1, RCCU_Div_2, RCCU_Div_3, RCCU_Div_4,\r
+* RCCU_Div_5, RCCU_Div_6, RCCU_Div_7)\r
+* Return : None\r
+*******************************************************************************/\r
+void RCCU_PLL1Config ( RCCU_PLL1_Mul New_Mul, RCCU_PLL_Div New_Div )\r
+{\r
+ u32 Tmp = ( RCCU->PLL1CR & ~RCCU_MX_Mask ) | ( New_Mul << RCCU_MX_Index );\r
+ RCCU->PLL1CR = ( Tmp & ~RCCU_DX_Mask ) | New_Div | 0x40;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCCU_PLL2Config\r
+* Description : Configures the PLL2 div & mul factors.\r
+* Input : New_Mul ( RCCU_PLL2_Mul_12, RCCU_PLL2_Mul_16, RCCU_PLL2_Mul_20, \r
+* RCCU_Mul_PLL2_28 )\r
+* : New_Div ( RCCU_Div_1, RCCU_Div_2, RCCU_Div_3, RCCU_Div_4,\r
+* RCCU_Div_5, RCCU_Div_6, RCCU_Div_7)\r
+* Return : None\r
+*******************************************************************************/\r
+void RCCU_PLL2Config ( RCCU_PLL2_Mul New_Mul, RCCU_PLL_Div New_Div )\r
+{\r
+ u32 Tmp = ( PCU->PLL2CR & ~RCCU_MX_Mask ) | ( New_Mul << RCCU_MX_Index );\r
+ PCU->PLL2CR = ( Tmp & ~RCCU_DX_Mask ) | ( New_Div | RCCU_FREEN_Mask );\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCCU_RCLKSourceConfig\r
+* Description : Selects the RCLK source clock\r
+* Input : New_Clock ( RCCU_PLL1_Output, RCCU_CLOCK2_16, RCCU_CLOCK2 )\r
+* Return : None\r
+*******************************************************************************/\r
+void RCCU_RCLKSourceConfig ( RCCU_RCLK_Clocks New_Clock )\r
+{\r
+ switch ( New_Clock )\r
+ {\r
+ case RCCU_CLOCK2 :{// Resets the CSU_Cksel bit in clk_flag\r
+ RCCU->CFR &= ~RCCU_CSU_CKSEL_Mask;\r
+ // Set the CK2_16 Bit in the CFR\r
+ RCCU->CFR |= RCCU_CK2_16_Mask;\r
+ // Deselect The CKAF\r
+ RCCU->CCR &= ~RCCU_CKAF_SEL_Mask;\r
+ // switch off the PLL1\r
+ RCCU->PLL1CR=((RCCU->PLL1CR & ~RCCU_DX_Mask)\\r
+ |0x00000003) & ~RCCU_FREEN_Mask;\r
+ break;}\r
+ case RCCU_CLOCK2_16 :{// ReSet the CK2_16 Bit in the CFR\r
+ RCCU->CFR &= ~RCCU_CK2_16_Mask;\r
+ // Deselect The CKAF\r
+ RCCU->CCR &= ~RCCU_CKAF_SEL_Mask;\r
+ // switch off the PLL1\r
+ RCCU->PLL1CR=((RCCU->PLL1CR & ~RCCU_DX_Mask)\\r
+ |0x00000003) & ~RCCU_FREEN_Mask;\r
+ break;}\r
+ case RCCU_PLL1_Output:{// Set the CK2_16 Bit in the CFR\r
+ RCCU->CFR = RCCU->CFR | RCCU_CK2_16_Mask;\r
+ // Waits the PLL1 to lock if DX bits are different from '111'\r
+ // If all DX bit are set the PLL lock flag in meaningless\r
+ if (( RCCU->PLL1CR & 0x0007 ) != 7)\r
+ while(!(RCCU->CFR & RCCU_LOCK_Mask));\r
+ // Deselect The CKAF\r
+ RCCU->CCR &= ~RCCU_CKAF_SEL_Mask;\r
+ // Select The CSU_CKSEL\r
+ RCCU->CFR |= RCCU_CSU_CKSEL_Mask;\r
+ break;}\r
+ case RCCU_RTC_CLOCK : {RCCU->CCR |= 0x04;\r
+ break;}\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCCU_RCLKClockSource\r
+* Description : Returns the current RCLK source clock\r
+* Input : None\r
+* Return : RCCU_PLL1_Output, RCCU_CLOCK2_16, RCCU_CLOCK2, RCCU_RTC_CLOCK\r
+*******************************************************************************/\r
+RCCU_RCLK_Clocks RCCU_RCLKClockSource ( void )\r
+{\r
+ if ((RCCU->CCR & 0x04)==0x04)\r
+ return RCCU_RTC_CLOCK;\r
+\r
+ else if ((RCCU->CFR & RCCU_CK2_16_Mask)==0)\r
+ return RCCU_CLOCK2_16;\r
+\r
+ else if (RCCU->CFR & RCCU_CSU_CKSEL_Mask)\r
+ return RCCU_PLL1_Output;\r
+\r
+ else\r
+ return RCCU_CLOCK2;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCCU_USBClockSource\r
+* Description : Gets the RCLK source clock\r
+* Input : None\r
+* Return : RCCU_USB_Clocks ( RCCU_PLL2_Output, RCCU_USBCK )\r
+*******************************************************************************/\r
+RCCU_USB_Clocks RCCU_USBClockSource ( void )\r
+{\r
+ if ((PCU->PLL2CR & RCCU_USBEN_Mask ) >> RCCU_USBEN_Index == 1 )\r
+ return RCCU_PLL2_Output;\r
+ else return RCCU_USBCK;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCCU_FrequencyValue\r
+* Description : Calculates & Returns any internal RCCU clock frequency\r
+* passed in parametres\r
+* Input : RCCU_Clocks ( RCCU_CLK2, RCCU_RCLK, RCCU_MCLK, RCCU_PCLK, RCCU_FCLK )\r
+* Return : u32\r
+*******************************************************************************/\r
+u32 RCCU_FrequencyValue ( RCCU_Clocks Internal_Clk )\r
+{\r
+ u32 Tmp;\r
+ u8 Div, Mul;\r
+ RCCU_RCLK_Clocks CurrentRCLK;\r
+\r
+ Tmp = ( RCCU_Div2Status() == SET )? RCCU_Main_Osc / 2 : RCCU_Main_Osc;\r
+\r
+ if ( Internal_Clk == RCCU_CLK2 )\r
+ {\r
+ Div = 1;\r
+ Mul = 1;\r
+ }\r
+ else\r
+ { CurrentRCLK = RCCU_RCLKClockSource ();\r
+ switch ( CurrentRCLK ){\r
+ case RCCU_CLOCK2_16 : Div = 16;\r
+ Mul = 1;\r
+ break;\r
+ case RCCU_CLOCK2 : Div = 1;\r
+ Mul = 1;\r
+ break;\r
+ case RCCU_PLL1_Output :{Mul=(RCCU->PLL1CR & RCCU_MX_Mask ) >> RCCU_MX_Index;\r
+ switch ( Mul )\r
+ {case 0: Mul = 20; break;\r
+ case 1: Mul = 12; break;\r
+ case 2: Mul = 28; break;\r
+ case 3: Mul = 16; break;\r
+ }\r
+ Div = ( RCCU->PLL1CR & RCCU_DX_Mask ) + 1;\r
+ break;}\r
+ case RCCU_RTC_CLOCK : Mul = 1;\r
+ Div = 1;\r
+ Tmp = RCCU_RTC_Osc;\r
+ break;}}\r
+\r
+ switch ( Internal_Clk ){\r
+ case RCCU_MCLK :{Div <<= PCU->MDIVR & RCCU_FACT_Mask;\r
+ break;}\r
+ case RCCU_PCLK :{Div <<=(PCU->PDIVR & RCCU_FACT2_Mask ) >> RCCU_FACT2_Index;\r
+ break;}\r
+ case RCCU_FCLK :{Div <<= PCU->PDIVR & 0x3;\r
+ break;}}\r
+\r
+ return (Tmp * Mul) / Div;\r
+}\r
+\r
+/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2003 STMicroelectronics ********************\r
+* File Name : uart.c\r
+* Author : MCD Application Team\r
+* Date First Issued : 06/08/2003\r
+* Description : This file provides all the UART software functions\r
+********************************************************************************\r
+* History:\r
+* 30/11/2004 : V2.0\r
+* 14/07/2004 : V1.3\r
+* 01/01/2004 : V1.2\r
+*******************************************************************************\r
+ THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH\r
+ CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+ AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT\r
+ OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT\r
+ OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION\r
+ CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+#include "uart.h"\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_Init\r
+* Description : This function initializes the selected UART.\r
+* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void UART_Init(UART_TypeDef *UARTx)\r
+{\r
+ UARTx->IER = 0x00;\r
+ UARTx->CR = 0x00;\r
+ (void)UARTx->RxBUFR;\r
+ UARTx->RxRSTR = 0xFFFF;\r
+ UARTx->TxRSTR = 0xFFFF;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_BaudRateConfig\r
+* Description : This function configures the baud rate of the selected UART.\r
+* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART\r
+* Input 2 : The baudrate value\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void UART_BaudRateConfig(UART_TypeDef *UARTx, u32 BaudRate)\r
+{\r
+ UARTx->BR = (u16)(RCCU_FrequencyValue(RCCU_FCLK)/(16*BaudRate));\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_Config\r
+* Description : This function configures the baudrate, the mode, the data\r
+* parity and the number of stop bits of the selected UART.\r
+* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART\r
+* Input 2 : The baudrate value\r
+* Input 3 : The parity type\r
+* Input 4 : The number of stop bits\r
+* Input 5 : The UART mode\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void UART_Config(UART_TypeDef *UARTx, u32 BaudRate, UARTParity_TypeDef Parity,\r
+ UARTStopBits_TypeDef StopBits, UARTMode_TypeDef Mode)\r
+{\r
+ UART_ModeConfig(UARTx, Mode);\r
+ UART_BaudRateConfig(UARTx, BaudRate);\r
+ UART_ParityConfig(UARTx, Parity);\r
+ UART_StopBitsConfig(UARTx, StopBits);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_ItConfig\r
+* Description : This function enables or disables the interrupts of the\r
+* selected UART.\r
+* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART\r
+* Input 2 : The new interrupt flag\r
+* Input 3 : ENABLE or DISABLE\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void UART_ItConfig(UART_TypeDef *UARTx, u16 UART_Flag, FunctionalState NewState)\r
+{\r
+ if (NewState==ENABLE) UARTx->IER|=UART_Flag; else UARTx->IER&=~UART_Flag;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_FifoConfig\r
+* Description : This function enables or disables the Rx and Tx FIFOs of\r
+* the selected UART.\r
+* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART\r
+* Input 2 : ENABLE or DISABLE\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void UART_FifoConfig(UART_TypeDef *UARTx, FunctionalState NewState)\r
+{\r
+ if (NewState==ENABLE) UARTx->CR|=0x0400; else UARTx->CR&=~0x0400;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_FifoReset\r
+* Description : This function resets the Rx and the Tx FIFOs of the\r
+* selected UART.\r
+* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART\r
+* Input 2 : UART_RxFIFO or UART_TxFIFO\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void UART_FifoReset(UART_TypeDef *UARTx, UARTFIFO_TypeDef FIFO)\r
+{\r
+ if (FIFO==UART_RxFIFO) UARTx->RxRSTR=0xFFFF; else UARTx->TxRSTR=0xFFFF;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_LoopBackConfig\r
+* Description : This function enables or disables the loop back mode of\r
+* the selected UART.\r
+* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART\r
+* Input 2 : ENABLE or DISABLE\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void UART_LoopBackConfig(UART_TypeDef *UARTx, FunctionalState NewState)\r
+{\r
+ if (NewState==ENABLE) UARTx->CR|=0x0040; else UARTx->CR&=~0x0040;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_RxConfig\r
+* Description : This function enables or disables the UART data reception.\r
+* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART\r
+* Input 2 : ENABLE or DISABLE\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void UART_RxConfig(UART_TypeDef *UARTx, FunctionalState NewState)\r
+{\r
+ if (NewState==ENABLE) UARTx->CR|=0x0100; else UARTx->CR&=~0x0100;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_OnOffConfig\r
+* Description : This function sets On/Off the selected UART.\r
+* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART\r
+* Input 2 : ENABLE or DISABLE\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void UART_OnOffConfig(UART_TypeDef *UARTx, FunctionalState NewState)\r
+{\r
+ if (NewState==ENABLE) UARTx->CR|=0x0080; else UARTx->CR&=~0x0080;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_ByteSend\r
+* Description : This function sends a data byte to the selected UART.\r
+* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART\r
+* Input 2 : A pointer to the data byte to send\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void UART_ByteSend(UART_TypeDef *UARTx, u8 *Data)\r
+{\r
+ if (UARTx->CR & (0x0001<<UART_FIFOEnableBit))// if FIFO ENABLED\r
+ while((UARTx->SR & UART_TxFull)); // while the UART_TxFIFO contain 16 characters.\r
+ else // if FIFO DISABLED\r
+ while (!(UARTx->SR & UART_TxEmpty)); // while the transmit shift register not empty\r
+ UARTx->TxBUFR = *Data;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_9BitByteSend\r
+* Description : This function sends a 9 bits data byte to the selected UART.\r
+* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART\r
+* Input 2 : A pointer to the data to send\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void UART_9BitByteSend(UART_TypeDef *UARTx, u16 *Data)\r
+{\r
+ if(UARTx->CR & (0x0001<<UART_FIFOEnableBit))// if FIFO ENABLED\r
+ while((UARTx->SR & UART_TxFull)); // while the UART_TxFIFO contain 16 characters.\r
+ else // if FIFO DISABLED\r
+ while (!(UARTx->SR & UART_TxEmpty)); // while the transmit shift register not empty\r
+ UARTx->TxBUFR = *Data;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_DataSend\r
+* Description : This function sends several data bytes to the selected UART.\r
+* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART\r
+* Input 2 : A pointer to the data to send\r
+* Input 3 : The data length in bytes\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void UART_DataSend(UART_TypeDef *UARTx, u8 *Data, u8 DataLength)\r
+{\r
+ while(DataLength--)\r
+ {\r
+ UART_ByteSend(UARTx,Data);\r
+ Data++;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_9BitDataSend\r
+* Description : This function sends several 9 bits data bytes to the selected UART.\r
+* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART\r
+* Input 2 : A pointer to the data to send\r
+* Input 3 : The data length\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void UART_9BitDataSend(UART_TypeDef *UARTx, u16 *Data, u8 DataLength)\r
+{\r
+ while(DataLength--)\r
+ {\r
+ UART_9BitByteSend(UARTx,Data);\r
+ Data++;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_StringSend\r
+* Description : This function sends a string to the selected UART.\r
+* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART\r
+* Input 2 : A pointer to the string to send\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void UART_StringSend(UART_TypeDef *UARTx, u8 *String)\r
+{\r
+ u8 *Data=String;\r
+ while(*Data != '\0')\r
+ UART_ByteSend(UARTx, Data++);\r
+ *Data='\0';\r
+ UART_ByteSend(UARTx, Data);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_ByteReceive\r
+* Description : This function gets a data byte from the selected UART.\r
+* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART\r
+* Input 2 : A pointer to the buffer where the data will be stored\r
+* Input 3 : The time-out period\r
+* Output : The received data\r
+* Return : The UARTx.SR register contents\r
+*******************************************************************************/\r
+u16 UART_ByteReceive(UART_TypeDef *UARTx, u8 *Data, u8 TimeOut)\r
+{\r
+ u16 wStatus;\r
+ UARTx->TOR=TimeOut;// reload the Timeout counter\r
+ while (!((wStatus=UARTx->SR) & (UART_TimeOutIdle|UART_RxHalfFull|UART_RxBufFull)));// while the UART_RxFIFO is empty and no Timeoutidle\r
+ *Data = (u8)UARTx->RxBUFR; // then read the Receive Buffer Register\r
+ return wStatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_9BitByteReceive\r
+* Description : This function gets a 9 bits data byte from the selected UART.\r
+* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART\r
+* Input 2 : A pointer to the buffer where the data will be stored\r
+* Input 3 : The time-out period value\r
+* Output : The received data\r
+* Return : The UARTx.SR register contents\r
+*******************************************************************************/\r
+u16 UART_9BitByteReceive(UART_TypeDef *UARTx, u16 *Data, u8 TimeOut)\r
+{\r
+ u16 wStatus;\r
+ UARTx->TOR=TimeOut;// reload the Timeout counter\r
+ while (!((wStatus=UARTx->SR) & (UART_TimeOutIdle|UART_RxHalfFull|UART_RxBufFull)));// while the UART_RxFIFO is empty and no Timeoutidle\r
+ *Data = (u16)UARTx->RxBUFR; // then read the RxBUFR\r
+ return wStatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_DataReceive\r
+* Description : This function gets 8 bits data bytes from the selected UART.\r
+* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART\r
+* Input 2 : A pointer to the buffer where the data will be stored\r
+* Input 3 : The data length\r
+* Input 4 : The time-out period value\r
+* Output : The received data\r
+* Return : The UARTx.SR register contents\r
+*******************************************************************************/\r
+u16 UART_DataReceive(UART_TypeDef *UARTx, u8 *Data, u8 DataLength, u8 TimeOut)\r
+{\r
+ u16 wStatus;\r
+ while(DataLength--)\r
+ wStatus=UART_ByteReceive(UARTx,Data++,TimeOut);\r
+ return wStatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_9BitDataReceive\r
+* Description : This function gets 9 bits data bytes from the selected UART.\r
+* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART\r
+* Input 2 : A pointer to the buffer where the data will be stored\r
+* Input 3 : The data length\r
+* Input 4 : The time-out value\r
+* Output : The received data\r
+* Return : The UARTx.SR register contents\r
+*******************************************************************************/\r
+u16 UART_9BitDataReceive(UART_TypeDef *UARTx, u16 *Data, u8 DataLength, u8 TimeOut)\r
+{\r
+ u16 wStatus;\r
+ while(DataLength--)\r
+ wStatus=UART_9BitByteReceive(UARTx,Data++,TimeOut);\r
+ return wStatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_StringReceive\r
+* Description : This function gets 8 bits data bytes from the selected UART.\r
+* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART\r
+* Input 2 : A pointer to the buffer where the string will be stored\r
+* Output : The received string\r
+* Return : The UARTx.SR register contents\r
+*******************************************************************************/\r
+u16 UART_StringReceive(UART_TypeDef *UARTx, u8 *Data)\r
+{\r
+ u8 *pSTRING=Data;\r
+ u16 wStatus;\r
+ do\r
+ {\r
+ while (!((wStatus=UARTx->SR) & (UART_RxHalfFull|UART_RxBufFull)));// while the UART_RxFIFO is empty and no Timeoutidle\r
+ *(pSTRING++) = (u8)UARTx->RxBUFR; // then read the RxBUFR\r
+ } while((*(pSTRING - 1)!=0x0D)&(*(pSTRING - 1)!='\0'));\r
+ *(pSTRING - 1)='\0';\r
+ return wStatus;\r
+}\r
+\r
+#ifdef USE_SERIAL_PORT\r
+/*******************************************************************************\r
+* Function Name : sendchar\r
+* Description : This function sends a character to the selected UART.\r
+* Input 1 : A pointer to the character to send.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void sendchar( char *ch )\r
+{\r
+ #ifdef USE_UART0\r
+ #define UARTx UART0\r
+ #endif /* Use_UART0 */\r
+\r
+ #ifdef USE_UART1\r
+ #define UARTx UART1\r
+ #endif /* Use_UART1 */\r
+\r
+ #ifdef USE_UART2\r
+ #define UARTx UART2\r
+ #endif /* Use_UART2 */\r
+\r
+ #ifdef USE_UART3\r
+ #define UARTx UART3\r
+ #endif /* Use_UART3 */\r
+\r
+ UART_ByteSend(UARTx,(u8 *)ch);\r
+}\r
+#endif /* USE_SERIAL_PORT */\r
+\r
+/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2003 STMicroelectronics ********************\r
+* File Name : WDG.c\r
+* Author : MCD Application Team\r
+* Date First Issued : 10/24/2003\r
+* Description : This file provides all the WDG software functions\r
+********************************************************************************\r
+* History:\r
+* 30/11/2004 : V2.0\r
+* 14/07/2004 : V1.3\r
+* 01/01/2004 : V1.2\r
+*******************************************************************************\r
+ THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH\r
+ CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+ AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT\r
+ OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT\r
+ OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION\r
+ CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+#include "wdg.h"\r
+\r
+#ifndef abs\r
+ #define abs(x) ((x)>0 ? (x) : -(x))\r
+#endif\r
+\r
+/*******************************************************************************\r
+* Function Name : FindFactors\r
+* Description : Search for the best (a,b) values that fit n = a*b\r
+* with the following constraints: 1<=a<=256, 1<=b<=65536\r
+* Input 1 : n: the number to decompose\r
+* Input/Output 2 : a: a pointer to the first factor\r
+* Input/Output 3 : b: a pointer to the second factor\r
+* Return : None\r
+*******************************************************************************/\r
+static void FindFactors(unsigned long n, unsigned int *a, unsigned long *b)\r
+{\r
+ unsigned long b0;\r
+ unsigned int a0;\r
+ long err, err_min=n;\r
+\r
+ *a = a0 = ((n-1)/65536ul) + 1;\r
+ *b = b0 = n / *a;\r
+\r
+ for (; *a <= 256; (*a)++)\r
+ {\r
+ *b = n / *a;\r
+ err = (long)*a * (long)*b - (long)n;\r
+ if (abs(err) > (*a / 2))\r
+ {\r
+ (*b)++;\r
+ err = (long)*a * (long)*b - (long)n;\r
+ }\r
+ if (abs(err) < abs(err_min))\r
+ {\r
+ err_min = err;\r
+ a0 = *a;\r
+ b0 = *b;\r
+ if (err == 0) break;\r
+ }\r
+ }\r
+\r
+ *a = a0;\r
+ *b = b0;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : WDG_PeriodValueConfig\r
+* Description : Set the prescaler and counter reload value\r
+* Input : Amount of time (us) needed\r
+* Return : None\r
+*******************************************************************************/\r
+void WDG_PeriodValueConfig ( u32 Time )\r
+{\r
+ unsigned int a;\r
+ unsigned long n, b;\r
+\r
+ n = Time * (RCCU_FrequencyValue(RCCU_PCLK) / 1000000);\r
+ FindFactors(n, &a, &b);\r
+ WDG->PR = a - 1;\r
+ WDG->VR = b - 1;\r
+}\r
+\r
+/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* Library includes. */\r
+#include "GPIO.h"\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+\r
+/* Demo application includes. */\r
+#include "partest.h"\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple parallel port IO routines for the LED's - which are\r
+ * connected to the second nibble of GPIO port 1.\r
+ *-----------------------------------------------------------*/\r
+\r
+#define partstLED_3 0x0080\r
+#define partstLED_2 0x0040\r
+#define partstLED_1 0x0020\r
+#define partstLED_0 0x0010\r
+#define partstON_BOARD 0x0100 /* The LED built onto the KickStart board. */\r
+\r
+#define partstALL_LEDs ( partstLED_0 | partstLED_1 | partstLED_2 | partstLED_3 | partstON_BOARD )\r
+\r
+#define partstFIRST_LED_BIT 4\r
+\r
+/* This demo application uses files that are common to all port demo \r
+applications. These files assume 6 LED's are available, whereas I have\r
+only 5 (including the LED built onto the development board). To prevent\r
+two tasks trying to use the same LED a bit of remapping is performed. \r
+The ComTest tasks will try and use LED's 6 and 7. LED 6 is ignored and\r
+has no effect, LED 7 is mapped to LED3. The LED usage is described in\r
+the port documentation available from the FreeRTOS.org WEB site. */\r
+#define partstCOM_TEST_LED 7\r
+#define partstRX_CHAR_LED 3\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestInitialise( void )\r
+{ \r
+ /* Configure the bits used to flash LED's on port 1 as output. */\r
+ GPIO_Config(GPIO1, partstALL_LEDs, GPIO_OUT_OD);\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )\r
+{\r
+ if( uxLED == partstCOM_TEST_LED )\r
+ {\r
+ /* Remap as described above. */\r
+ uxLED = partstRX_CHAR_LED;\r
+ }\r
+\r
+ /* Adjust the LED value to map to the port pins actually being used,\r
+ then write the required value to the port. */\r
+ uxLED += partstFIRST_LED_BIT;\r
+ GPIO_BitWrite( GPIO1, uxLED, !xValue );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+ if( uxLED == partstCOM_TEST_LED )\r
+ {\r
+ /* Remap as described above. */\r
+ uxLED = partstRX_CHAR_LED;\r
+ }\r
+\r
+ /* Adjust the LED value to map to the port pins actually being used,\r
+ then write the opposite value to the current state to the port pin. */\r
+ uxLED += partstFIRST_LED_BIT;\r
+ GPIO_BitWrite(GPIO1, uxLED, ~GPIO_BitRead( GPIO1, uxLED ) );\r
+}\r
+\r
+\r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+ <fileVersion>2</fileVersion>\r
+ <configuration>\r
+ <name>Debug</name>\r
+ <outputs>\r
+ <file>$PROJ_DIR$\..\Common\Minimal\comtest.c</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\tasks.pbi</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\serial.pbi</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\71x_lib.pbi</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\wdg.pbi</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\semtest.r79</file>\r
+ <file>$TOOLKIT_DIR$\inc\string.h</file>\r
+ <file>$TOOLKIT_DIR$\inc\ysizet.h</file>\r
+ <file>$PROJ_DIR$\..\Common\include\comtest.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\BlockQ.pbi</file>\r
+ <file>$PROJ_DIR$\..\Common\include\dynamic.h</file>\r
+ <file>$PROJ_DIR$\Library\include\71x_map.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\list.r79</file>\r
+ <file>$PROJ_DIR$\Library\include\eic.h</file>\r
+ <file>$TOOLKIT_DIR$\inc\xencoding_limits.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\list.pbi</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\ParTest.r79</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\BlockQ.r79</file>\r
+ <file>$TOOLKIT_DIR$\inc\yvals.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\main.r79</file>\r
+ <file>$PROJ_DIR$\..\Common\include\partest.h</file>\r
+ <file>$PROJ_DIR$\Library\include\rccu.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\portasm.r79</file>\r
+ <file>$PROJ_DIR$\..\..\Source\portable\IAR\STR71x\ISR_Support.h</file>\r
+ <file>$PROJ_DIR$\..\Common\include\PollQ.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\cstartup.r79</file>\r
+ <file>$TOOLKIT_DIR$\inc\DLib_Threads.h</file>\r
+ <file>$PROJ_DIR$\FreeRTOSConfig.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\dynamic.pbi</file>\r
+ <file>$PROJ_DIR$\..\..\Source\include\FreeRTOS.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\heap_2.r79</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\queue.r79</file>\r
+ <file>$PROJ_DIR$\..\..\Source\include\queue.h</file>\r
+ <file>$TOOLKIT_DIR$\inc\stdlib.h</file>\r
+ <file>$PROJ_DIR$\Library\include\wdg.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\serialISR.r79</file>\r
+ <file>$TOOLKIT_DIR$\lib\dl4tptinl8n.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\heap_2.pbi</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\integer.pbi</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\rccu.pbi</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\uart.r79</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\port.pbi</file>\r
+ <file>$PROJ_DIR$\..\..\Source\include\croutine.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\queue.pbi</file>\r
+ <file>$TOOLKIT_DIR$\inc\DLib_Defaults.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\port.r79</file>\r
+ <file>$TOOLKIT_DIR$\inc\stddef.h</file>\r
+ <file>$PROJ_DIR$\..\Common\include\comtest2.h</file>\r
+ <file>$PROJ_DIR$\Library\include\71x_conf.h</file>\r
+ <file>$TOOLKIT_DIR$\inc\stdio.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\serial.r79</file>\r
+ <file>$PROJ_DIR$\..\Common\include\BlockQ.h</file>\r
+ <file>$PROJ_DIR$\..\Common\include\integer.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\comtest.r79</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\71x_lib.r79</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\main.pbi</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\dynamic.r79</file>\r
+ <file>$PROJ_DIR$\Library\include\gpio.h</file>\r
+ <file>$TOOLKIT_DIR$\inc\DLib_Product.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\tasks.r79</file>\r
+ <file>$PROJ_DIR$\..\..\Source\include\semphr.h</file>\r
+ <file>$TOOLKIT_DIR$\inc\intrinsic.h</file>\r
+ <file>$PROJ_DIR$\Library\include\uart.h</file>\r
+ <file>$PROJ_DIR$\Debug\Exe\RTOSDemo.sim</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\flash.r79</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\integer.r79</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\PollQ.r79</file>\r
+ <file>$PROJ_DIR$\Debug\Exe\RTOSDemo.d79</file>\r
+ <file>$TOOLKIT_DIR$\lib\dl4tptinl8n.r79</file>\r
+ <file>$PROJ_DIR$\..\..\Source\include\task.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\uart.pbi</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\gpio.pbi</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\flash.pbi</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\vect.r79</file>\r
+ <file>$PROJ_DIR$\..\Common\include\serial.h</file>\r
+ <file>$PROJ_DIR$\..\Common\include\flash.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\rccu.r79</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\ParTest.pbi</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\PollQ.pbi</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\semtest.pbi</file>\r
+ <file>$PROJ_DIR$\..\..\Source\include\projdefs.h</file>\r
+ <file>$PROJ_DIR$\..\..\Source\include\list.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\comtest.pbi</file>\r
+ <file>$PROJ_DIR$\Library\include\71x_type.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\gpio.r79</file>\r
+ <file>$PROJ_DIR$\..\..\Source\include\portable.h</file>\r
+ <file>$PROJ_DIR$\..\..\Source\portable\IAR\STR71x\portmacro.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\wdg.r79</file>\r
+ <file>$PROJ_DIR$\..\Common\include\semtest.h</file>\r
+ <file>$PROJ_DIR$\cstartup.s79</file>\r
+ <file>$PROJ_DIR$\lnkarm.xcl</file>\r
+ <file>$PROJ_DIR$\vect.s79</file>\r
+ <file>$PROJ_DIR$\..\Common\Minimal\BlockQ.c</file>\r
+ <file>$PROJ_DIR$\serial\serialISR.s79</file>\r
+ <file>$PROJ_DIR$\Library\rccu.c</file>\r
+ <file>$PROJ_DIR$\Library\uart.c</file>\r
+ <file>$PROJ_DIR$\Library\wdg.c</file>\r
+ <file>$PROJ_DIR$\..\..\Source\list.c</file>\r
+ <file>$PROJ_DIR$\..\..\Source\portable\IAR\STR71x\port.c</file>\r
+ <file>$PROJ_DIR$\..\..\Source\portable\IAR\STR71x\portasm.s79</file>\r
+ <file>$PROJ_DIR$\..\..\Source\queue.c</file>\r
+ <file>$PROJ_DIR$\..\..\Source\tasks.c</file>\r
+ <file>$PROJ_DIR$\..\Common\Minimal\flash.c</file>\r
+ <file>$PROJ_DIR$\..\..\Source\portable\MemMang\heap_2.c</file>\r
+ <file>$PROJ_DIR$\..\Common\Minimal\dynamic.c</file>\r
+ <file>$PROJ_DIR$\..\Common\Minimal\integer.c</file>\r
+ <file>$PROJ_DIR$\main.c</file>\r
+ <file>$PROJ_DIR$\ParTest\ParTest.c</file>\r
+ <file>$PROJ_DIR$\..\Common\Minimal\PollQ.c</file>\r
+ <file>$PROJ_DIR$\..\Common\Minimal\semtest.c</file>\r
+ <file>$PROJ_DIR$\serial\serial.c</file>\r
+ <file>$PROJ_DIR$\Library\gpio.c</file>\r
+ <file>$PROJ_DIR$\Library\71x_lib.c</file>\r
+ </outputs>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\comtest.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 53</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 82</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 33 18 44 36 58 14 26 7 29 46 80 27 85 86 61 69 81 74 8 20</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>[ROOT_NODE]</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>XLINK</name>\r
+ <file> 67 63</file>\r
+ </tool>\r
+ </outputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\Debug\Exe\RTOSDemo.d79</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>XLINK</name>\r
+ <file> 63</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>XLINK</name>\r
+ <file> 90 54 17 16 66 53 25 56 64 84 30 65 12 19 45 22 31 76 5 50 35 59 40 73 87 68</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\cstartup.s79</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>AARM</name>\r
+ <file> 25</file>\r
+ </tool>\r
+ </outputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\vect.s79</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>AARM</name>\r
+ <file> 73</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>AARM</name>\r
+ <file> 27</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\BlockQ.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 17</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 9</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 33 18 44 36 58 14 26 7 29 46 80 27 85 86 61 69 81 32 51</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\serial\serialISR.s79</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>AARM</name>\r
+ <file> 35</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>AARM</name>\r
+ <file> 23</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\Library\rccu.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 76</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 39</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 21 11 48 83</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\Library\uart.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 40</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 70</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 62 11 48 83 21</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\Library\wdg.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 87</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 4</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 34 11 48 83 21</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\list.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 12</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 15</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 33 18 44 36 58 14 26 7 29 46 80 27 85 86 61 81</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\IAR\STR71x\port.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 45</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 41</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 34 11 48 83 21 13 33 18 44 36 58 14 26 7 29 46 80 27 85 86 61 69 81</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\IAR\STR71x\portasm.s79</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>AARM</name>\r
+ <file> 22</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>AARM</name>\r
+ <file> 23</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\queue.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 31</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 43</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 33 18 44 36 58 14 26 7 6 29 46 80 27 85 86 61 69 81 42</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\tasks.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 59</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 1</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 49 18 44 36 58 14 26 7 33 6 29 46 80 27 85 86 61 69 81</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\flash.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 64</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 72</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 33 18 44 36 58 14 26 7 29 46 80 27 85 86 61 69 81 20 75</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\MemMang\heap_2.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 30</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 37</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 33 18 44 36 58 14 26 7 29 46 80 27 85 86 61 69 81</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
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+\r
--- /dev/null
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+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>DoEmuMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuMultiTarget</name>\r
+ <state>0@ARM7TDMI</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuHWReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CEmuCommBaud</name>\r
+ <version>0</version>\r
+ <state>4</state>\r
+ </option>\r
+ <option>\r
+ <name>CEmuCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>jtago</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>UnusedAddr</name>\r
+ <state>0x00800000</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMacraigorHWResetDelay</name>\r
+ <state></state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>RDI_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CRDIDriverDll</name>\r
+ <state>Browse to your RDI driver</state>\r
+ </option>\r
+ <option>\r
+ <name>CRDILogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRDILogFileEdit</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDIHWReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchUndef</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchSWI</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchData</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchPrefetch</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchIRQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchFIQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDIUseETM</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>THIRDPARTY_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CThirdPartyDriverDll</name>\r
+ <state>Browse to your third-party driver</state>\r
+ </option>\r
+ <option>\r
+ <name>CThirdPartyLogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CThirdPartyLogFileEditB</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <debuggerPlugins>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Profiling\Profiling.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Trace\Trace.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ </debuggerPlugins>\r
+ </configuration>\r
+ <configuration>\r
+ <name>Release</name>\r
+ <toolchain>\r
+ <name>ARM</name>\r
+ </toolchain>\r
+ <debug>0</debug>\r
+ <settings>\r
+ <name>C-SPY</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>12</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>CInput</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CEndian</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCVariant</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>MemOverride</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>MemFile</name>\r
+ <state>$TOOLKIT_DIR$\CONFIG\iostr712.ddf</state>\r
+ </option>\r
+ <option>\r
+ <name>RunToEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RunToName</name>\r
+ <state>main</state>\r
+ </option>\r
+ <option>\r
+ <name>CExtraOptionsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CFpuProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDDFArgumentProducer</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadSuppressDownload</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadVerifyAll</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadFlashDownload</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadFlashOverride</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadFlashLoader</name>\r
+ <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTR71xF.d79</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadFlashLoaderSlave</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCProductVersion</name>\r
+ <state>4.20A</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDynDriverList</name>\r
+ <state>JLINK_ID</state>\r
+ </option>\r
+ <option>\r
+ <name>OCLastSavedByProductVersion</name>\r
+ <state>4.20A</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadFlashLoaderArgs</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadFlashBaseAddrOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadFlashBaseAddr</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadAttachToProgram</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ARMSIM_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>OCSimDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ANGEL_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>CCAngelHeartbeat</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommunication</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommBaud</name>\r
+ <version>0</version>\r
+ <state>3</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ANGELTCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>DoAngelLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AngelLogFile</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>IARROM_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>CRomLogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomLogFileEditB</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomCommunication</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomCommBaud</name>\r
+ <version>0</version>\r
+ <state>7</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>JLINK_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>JLinkSpeed</name>\r
+ <state>32</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkHWReset</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkTRSTReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDoJlinkMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkLogFile</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkHWResetDelay</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkSpeedRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>JLinkInitialSpeed</name>\r
+ <state>4000</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>MACRAIGOR_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>jtag</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuSpeed</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>TCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>DoEmuMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuMultiTarget</name>\r
+ <state>0@ARM7TDMI</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuHWReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CEmuCommBaud</name>\r
+ <version>0</version>\r
+ <state>4</state>\r
+ </option>\r
+ <option>\r
+ <name>CEmuCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>jtago</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>UnusedAddr</name>\r
+ <state>0x00800000</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMacraigorHWResetDelay</name>\r
+ <state></state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>RDI_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>CRDIDriverDll</name>\r
+ <state>Browse to your RDI driver</state>\r
+ </option>\r
+ <option>\r
+ <name>CRDILogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRDILogFileEdit</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDIHWReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchUndef</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchSWI</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchData</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchPrefetch</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchIRQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchFIQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDIUseETM</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>THIRDPARTY_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>CThirdPartyDriverDll</name>\r
+ <state>Browse to your third-party driver</state>\r
+ </option>\r
+ <option>\r
+ <name>CThirdPartyLogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CThirdPartyLogFileEditB</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <debuggerPlugins>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Profiling\Profiling.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Trace\Trace.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ </debuggerPlugins>\r
+ </configuration>\r
+</project>\r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+ <fileVersion>1</fileVersion>\r
+ <configuration>\r
+ <name>Debug</name>\r
+ <toolchain>\r
+ <name>ARM</name>\r
+ </toolchain>\r
+ <debug>1</debug>\r
+ <settings>\r
+ <name>General</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>8</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>GProcessorMode</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>ExePath</name>\r
+ <state>Debug\Exe</state>\r
+ </option>\r
+ <option>\r
+ <name>ObjPath</name>\r
+ <state>Debug\Obj</state>\r
+ </option>\r
+ <option>\r
+ <name>ListPath</name>\r
+ <state>Debug\List</state>\r
+ </option>\r
+ <option>\r
+ <name>Variant</name>\r
+ <version>2</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GEndianMode</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GInterwork</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GStackAlign</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>Input variant</name>\r
+ <version>1</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>Input description</name>\r
+ <state>Full formatting.</state>\r
+ </option>\r
+ <option>\r
+ <name>Output variant</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>Output description</name>\r
+ <state>Full formatting.</state>\r
+ </option>\r
+ <option>\r
+ <name>GOutputBinary</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>FPU</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OGCoreOrChip</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OGChipSelect</name>\r
+ <state>$TOOLKIT_DIR$\config\chip\ST\STR712.i79</state>\r
+ </option>\r
+ <option>\r
+ <name>GRuntimeLibSelect</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GRuntimeLibSelectSlave</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RTDescription</name>\r
+ <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\r
+ </option>\r
+ <option>\r
+ <name>RTConfigPath</name>\r
+ <state>$TOOLKIT_DIR$\LIB\dl4tptinl8n.h</state>\r
+ </option>\r
+ <option>\r
+ <name>RTLibraryPath</name>\r
+ <state>$TOOLKIT_DIR$\LIB\dl4tptinl8n.r79</state>\r
+ </option>\r
+ <option>\r
+ <name>OGProductVersion</name>\r
+ <state>4.20A</state>\r
+ </option>\r
+ <option>\r
+ <name>OGLastSavedByProductVersion</name>\r
+ <state>4.20A</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraRules</name>\r
+ <version>0</version>\r
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralEnableMisra</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraVerbose</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ICCARM</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>11</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CCIncludePaths</name>\r
+ <state>$TOOLKIT_DIR$\INC\</state>\r
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+ </settings>\r
+ <settings>\r
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+ <archiveVersion>3</archiveVersion>\r
+ <data>\r
+ <extensions></extensions>\r
+ <cmdline></cmdline>\r
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+ </settings>\r
+ <settings>\r
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+ <prebuild></prebuild>\r
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+ <settings>\r
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+ <wantNonLocal>1</wantNonLocal>\r
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+ <option>\r
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+ <option>\r
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+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
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+ <option>\r
+ <name>XAROverride</name>\r
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+ </settings>\r
+ <settings>\r
+ <name>BILINK</name>\r
+ <archiveVersion>0</archiveVersion>\r
+ <data/>\r
+ </settings>\r
+ </configuration>\r
+ <group>\r
+ <name>Demo Source</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\BlockQ.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\comtest.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\dynamic.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\flash.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\MemMang\heap_2.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\integer.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\main.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\ParTest\ParTest.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\PollQ.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\semtest.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\serial\serial.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\serial\serialISR.s79</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>Library Source</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\Library\71x_lib.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\Library\gpio.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\Library\rccu.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\Library\uart.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\Library\wdg.c</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>RTOS Source</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\list.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\IAR\STR71x\port.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\IAR\STR71x\portasm.s79</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\queue.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\tasks.c</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>System Files</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\cstartup.s79</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\lnkarm.xcl</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\vect.s79</name>\r
+ </file>\r
+ </group>\r
+</project>\r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<workspace>\r
+ <project>\r
+ <path>$WS_DIR$\RTOSDemo.ewp</path>\r
+ </project>\r
+ <batchBuild/>\r
+</workspace>\r
+\r
+\r
--- /dev/null
+;-----------------------------------------------------------------------------\r
+; This file contains the startup code used by the ICCARM C compiler.\r
+;\r
+; The modules in this file are included in the libraries, and may be replaced\r
+; by any user-defined modules that define the PUBLIC symbol _program_start or\r
+; a user defined start symbol.\r
+; To override the cstartup defined in the library, simply add your modified\r
+; version to the workbench project.\r
+;\r
+; All code in the modules (except ?RESET) will be placed in the ICODE segment.\r
+;\r
+; $Revision: 1.1 $\r
+;\r
+;-----------------------------------------------------------------------------\r
+ \r
+;\r
+; Naming covention of labels in this file:\r
+;\r
+; ?xxx - External labels only accessed from assembler.\r
+; __xxx - External labels accessed from or defined in C.\r
+; xxx - Labels local to one module (note: this file contains\r
+; several modules).\r
+; main - The starting point of the user program.\r
+;\r
+\r
+;---------------------------------------------------------------\r
+; Macros and definitions for the whole file\r
+;---------------------------------------------------------------\r
+\r
+\r
+; --- Standard definitions of mode bits and interrupt (I & F) flags in PSRs\r
+\r
+\r
+\r
+Mode_USR DEFINE 0x10\r
+Mode_FIQ DEFINE 0x11\r
+Mode_IRQ DEFINE 0x12\r
+Mode_SVC DEFINE 0x13\r
+Mode_ABT DEFINE 0x17\r
+Mode_UNDEF DEFINE 0x1B\r
+Mode_SYS DEFINE 0x1F ; available on ARM Arch 4 and later\r
+\r
+I_Bit DEFINE 0x80 ; when I bit is set, IRQ is disabled\r
+F_Bit DEFINE 0x40 ; when F bit is set, FIQ is disabled\r
+\r
+\r
+; --- System memory locations\r
+\r
+RAM_Base DEFINE 0x20000000\r
+RAM_Limit DEFINE 0x20010000\r
+SRAM_Base DEFINE 0x60000000\r
+\r
+SVC_Stack DEFINE RAM_Limit ; 512 byte SVC stack at\r
+ ; top of memory - used by kernel.\r
+IRQ_Stack DEFINE SVC_Stack-512 ; followed by IRQ stack\r
+USR_Stack DEFINE IRQ_Stack-512 ; followed by USR stack. Tasks run in\r
+ ; system mode but task stacks are allocated\r
+ ; when the task is created.\r
+FIQ_Stack DEFINE USR_Stack-8 ; followed by FIQ stack\r
+ABT_Stack DEFINE FIQ_Stack-8 ; followed by ABT stack\r
+UNDEF_Stack DEFINE ABT_Stack-8 ; followed by UNDEF stack\r
+\r
+EIC_Base_addr DEFINE 0xFFFFF800 ; EIC base address\r
+ICR_off_addr DEFINE 0x00 ; Interrupt Control register offset\r
+CIPR_off_addr DEFINE 0x08 ; Current Interrupt Priority Register offset\r
+IVR_off_addr DEFINE 0x18 ; Interrupt Vector Register offset\r
+FIR_off_addr DEFINE 0x1C ; Fast Interrupt Register offset\r
+IER_off_addr DEFINE 0x20 ; Interrupt Enable Register offset\r
+IPR_off_addr DEFINE 0x40 ; Interrupt Pending Bit Register offset\r
+SIR0_off_addr DEFINE 0x60 ; Source Interrupt Register 0\r
+\r
+EMI_Base_addr DEFINE 0x6C000000 ; EMI base address\r
+BCON0_off_addr DEFINE 0x00 ; Bank 0 configuration register offset\r
+BCON1_off_addr DEFINE 0x04 ; Bank 1 configuration register offset\r
+BCON2_off_addr DEFINE 0x08 ; Bank 2 configuration register offset\r
+BCON3_off_addr DEFINE 0x0C ; Bank 3 configuration register offset\r
+\r
+GPIO2_Base_addr DEFINE 0xE0005000 ; GPIO2 base address\r
+PC0_off_addr DEFINE 0x00 ; Port Configuration Register 0 offset\r
+PC1_off_addr DEFINE 0x04 ; Port Configuration Register 1 offset\r
+PC2_off_addr DEFINE 0x08 ; Port Configuration Register 2 offset\r
+PD_off_addr DEFINE 0x0C ; Port Data Register offset\r
+\r
+CPM_Base_addr DEFINE 0xA0000040 ; CPM Base Address\r
+BOOTCONF_off_addr DEFINE 0x10 ; CPM - Boot Configuration Register\r
+FLASH_mask DEFINE 0x0000 ; to remap FLASH at 0x0\r
+RAM_mask DEFINE 0x0002 ; to remap RAM at 0x0\r
+EXTMEM_mask DEFINE 0x0003 ; to remap EXTMEM at 0x0\r
+\r
+;---------------------------------------------------------------\r
+; ?RESET\r
+; Reset Vector.\r
+; Normally, segment INTVEC is linked at address 0.\r
+; For debugging purposes, INTVEC may be placed at other\r
+; addresses.\r
+; A debugger that honors the entry point will start the\r
+; program in a normal way even if INTVEC is not at address 0.\r
+;---------------------------------------------------------------\r
+\r
+ MODULE ?RESET\r
+ COMMON INTVEC:CODE:NOROOT(2)\r
+ PUBLIC __program_start\r
+ EXTERN ?cstartup \r
+ CODE32 ; Always ARM mode after reset \r
+ \r
+__program_start\r
+ ldr pc,=?cstartup ; Absolute jump can reach 4 GByte\r
+ b ?cstartup ; Relative branch allows remap, limited to 32 MByte\r
+ \r
+ LTORG\r
+ ENDMOD\r
+\r
+\r
+;---------------------------------------------------------------\r
+; ?CSTARTUP\r
+;---------------------------------------------------------------\r
+ MODULE ?CSTARTUP\r
+\r
+; RSEG IRQ_STACK:DATA(2)\r
+; RSEG SVC_STACK:DATA:NOROOT(2)\r
+; RSEG CSTACK:DATA(2)\r
+ RSEG ICODE:CODE:NOROOT(2)\r
+ PUBLIC ?cstartup\r
+ EXTERN ?main\r
+\r
+\r
+\r
+\r
+ CODE32\r
+?cstartup\r
+\r
+\r
+ NOP ; Wait for OSC stabilization\r
+ NOP\r
+ NOP\r
+ NOP\r
+ NOP\r
+ NOP\r
+ NOP\r
+ NOP\r
+ NOP\r
+ \r
+\r
+ /* Setup a stack for each mode - note that this only sets up a usable stack\r
+ for system/user, SWI and IRQ modes. Also each mode is setup with\r
+ interrupts initially disabled. */\r
+ msr CPSR_c, #Mode_UNDEF|I_Bit|F_Bit /* Undefined Instruction Mode */\r
+ LDR SP, =UNDEF_Stack\r
+\r
+ msr CPSR_c, #Mode_ABT|I_Bit|F_Bit /* Abort Mode */\r
+ LDR SP, =ABT_Stack\r
+\r
+ msr CPSR_c, #Mode_FIQ|I_Bit|F_Bit /* FIQ Mode */\r
+ LDR SP, =FIQ_Stack\r
+\r
+ msr CPSR_c, #Mode_IRQ|I_Bit|F_Bit /* IRQ Mode */\r
+ LDR SP, =IRQ_Stack\r
+\r
+ msr CPSR_c, #Mode_SVC|I_Bit|F_Bit /* Supervisor Mode */\r
+ LDR SP, =SVC_Stack\r
+\r
+ msr CPSR_c, #Mode_SYS|I_Bit|F_Bit /* System Mode */\r
+ LDR SP, =USR_Stack\r
+\r
+ /* We want to start in supervisor mode. Operation will switch to system\r
+ mode when the first task starts. */\r
+ msr CPSR_c, #Mode_SVC|I_Bit|F_Bit\r
+\r
+\r
+ IMPORT T0TIMI_Addr\r
+\r
+EIC_INIT\r
+ LDR r3, =EIC_Base_addr\r
+ LDR r4, =0x00000000\r
+ STR r4, [r3, #ICR_off_addr] ; Disable FIQ and IRQ\r
+ STR r4, [r3, #IER_off_addr] ; Disable all channels interrupts\r
+ LDR r4, =0xFFFFFFFF\r
+ STR r4, [r3, #IPR_off_addr] ; Clear all IRQ pending bits\r
+ LDR r4, =0x0C\r
+ STR r4, [r3, #FIR_off_addr] ; Disable FIQ channels and clear FIQ pending bits\r
+ LDR r4, =0x00000000\r
+ STR r4, [r3, #CIPR_off_addr] ; Reset the current priority register\r
+ LDR r4, =0xE59F0000\r
+ STR r4, [r3, #IVR_off_addr] ; Write the LDR pc,pc,#offset instruction code in IVR[31:16]\r
+ LDR r2, =32 ; 32 Channel to initialize\r
+ LDR r0, =T0TIMI_Addr ; Read the address of the IRQs address table\r
+ LDR r1, =0x00000FFF\r
+ AND r0,r0,r1\r
+ LDR r5, =SIR0_off_addr ; Read SIR0 address\r
+ SUB r4,r0,#8 ; subtract 8 for prefetch\r
+ LDR r1, =0xF7E8 ; add the offset to the 0x00000000 address(IVR address + 7E8 = 0x00000000)\r
+ ; 0xF7E8 used to complete the LDR pc,pc,#offset opcode\r
+ ADD r1,r4,r1 ; compute the jump offset\r
+EIC_INI MOV r4, r1, LSL #16 ; Left shift the result\r
+ STR r4, [r3, r5] ; Store the result in SIRx register\r
+ ADD r1, r1, #4 ; Next IRQ address\r
+ ADD r5, r5, #4 ; Next SIR\r
+ SUBS r2, r2, #1 ; Decrement the number of SIR registers to initialize\r
+ BNE EIC_INI ; If more then continue\r
+\r
+\r
+ ldr r0,=?main\r
+ bx r0\r
+\r
+ LTORG\r
+\r
+ ENDMOD\r
+\r
+\r
+ END\r
+\r
+\r
--- /dev/null
+//*************************************************************************\r
+// XLINK command file template for EWARM/ICCARM\r
+//\r
+// Usage: xlink -f lnkarm <your_object_file(s)>\r
+// -s <program start label> <C/C++ runtime library>\r
+//\r
+// $Revision: 1.1 $\r
+//*************************************************************************\r
+\r
+// Code memory in flash\r
+-DROMSTART=0x00000000\r
+-DROMEND=0x0003FFFF\r
+-DVECSTART=ROMSTART\r
+\r
+// Data memory\r
+-DRAMSTART=0x20000000\r
+-DRAMEND=0x2000FFFF\r
+\r
+\r
+//*************************************************************************\r
+// In this file it is assumed that the system has the following\r
+// memory layout:\r
+//\r
+// Exception vectors [0x000000--0x00001F] RAM or ROM\r
+// ROMSTART--ROMEND [0x008000--0x0FFFFF] ROM (or other non-volatile memory)\r
+// RAMSTART--RAMEND [0x100000--0x7FFFFF] RAM (or other read/write memory)\r
+//\r
+// -------------\r
+// Code segments - may be placed anywhere in memory.\r
+// -------------\r
+//\r
+// INTVEC -- Exception vector table.\r
+// SWITAB -- Software interrupt vector table.\r
+// ICODE -- Startup (cstartup) and exception code.\r
+// DIFUNCT -- Dynamic initialization vectors used by C++.\r
+// CODE -- Compiler generated code.\r
+// CODE_I -- Compiler generated code declared __ramfunc (executes in RAM)\r
+// CODE_ID -- Initializer for CODE_I (ROM).\r
+//\r
+// -------------\r
+// Data segments - may be placed anywhere in memory.\r
+// -------------\r
+//\r
+// CSTACK -- The stack used by C/C++ programs (system and user mode).\r
+// IRQ_STACK -- The stack used by IRQ service routines.\r
+// SVC_STACK -- The stack used in supervisor mode\r
+// (Define other exception stacks as needed for\r
+// FIQ, ABT, UND).\r
+// HEAP -- The heap used by malloc and free in C and new and\r
+// delete in C++.\r
+// INITTAB -- Table containing addresses and sizes of segments that\r
+// need to be initialized at startup (by cstartup).\r
+// CHECKSUM -- The linker places checksum byte(s) in this segment,\r
+// when the -J linker command line option is used.\r
+// DATA_y -- Data objects.\r
+//\r
+// Where _y can be one of:\r
+//\r
+// _AN -- Holds uninitialized located objects, i.e. objects with\r
+// an absolute location given by the @ operator or the\r
+// #pragma location directive. Since these segments\r
+// contain objects which already have a fixed address,\r
+// they should not be mentioned in this linker command\r
+// file.\r
+// _C -- Constants (ROM).\r
+// _I -- Initialized data (RAM).\r
+// _ID -- The original content of _I (copied to _I by cstartup) (ROM).\r
+// _N -- Uninitialized data (RAM).\r
+// _Z -- Zero initialized data (RAM).\r
+//\r
+// Note: Be sure to use end values for the defined address ranges.\r
+// Otherwise, the linker may allocate space outside the\r
+// intended memory range.\r
+//*************************************************************************\r
+\r
+\r
+//************************************************\r
+// Inform the linker about the CPU family used.\r
+//************************************************\r
+\r
+-carm\r
+\r
+//*************************************************************************\r
+// Segment placement - General information\r
+//\r
+// All numbers in the segment placement command lines below are interpreted\r
+// as hexadecimal unless they are immediately preceded by a '.', which\r
+// denotes decimal notation.\r
+//\r
+// When specifying the segment placement using the -P instead of the -Z\r
+// option, the linker is free to split each segment into its segment parts\r
+// and randomly place these parts within the given ranges in order to\r
+// achieve a more efficient memory usage. One disadvantage, however, is\r
+// that it is not possible to find the start or end address (using\r
+// the assembler operators .sfb./.sfe.) of a segment which has been split\r
+// and reformed.\r
+//\r
+// When generating an output file which is to be used for programming\r
+// external ROM/Flash devices, the -M linker option is very useful\r
+// (see xlink.pdf for details).\r
+//*************************************************************************\r
+\r
+\r
+//*************************************************************************\r
+// Read-only segments mapped to ROM.\r
+//*************************************************************************\r
+\r
+//************************************************\r
+// Address range for reset and exception\r
+// vectors (INTVEC).\r
+// The vector area is 32 bytes,\r
+// an additional 32 bytes is allocated for the\r
+// constant table used by ldr PC in cstartup.s79.\r
+//************************************************\r
+\r
+-Z(CODE)INTVEC=VECSTART:+0x940\r
+\r
+//************************************************\r
+// Startup code and exception routines (ICODE).\r
+//************************************************\r
+\r
+-Z(CODE)ICODE,DIFUNCT=ROMSTART-ROMEND\r
+-Z(CODE)SWITAB=ROMSTART-ROMEND\r
+\r
+//************************************************\r
+// Code segments may be placed anywhere.\r
+//************************************************\r
+\r
+-Z(CODE)CODE=ROMSTART-ROMEND\r
+\r
+//************************************************\r
+// Original ROM location for __ramfunc code copied\r
+// to and executed from RAM.\r
+//************************************************\r
+\r
+-Z(CONST)CODE_ID=ROMSTART-ROMEND\r
+\r
+//************************************************\r
+// Various constants and initializers.\r
+//************************************************\r
+\r
+-Z(CONST)INITTAB,DATA_ID,DATA_C=ROMSTART-ROMEND\r
+-Z(CONST)CHECKSUM=ROMSTART-ROMEND\r
+\r
+\r
+//*************************************************************************\r
+// Read/write segments mapped to RAM.\r
+//*************************************************************************\r
+\r
+//************************************************\r
+// Data segments.\r
+//************************************************\r
+\r
+-Z(DATA)DATA_I,DATA_Z,DATA_N=RAMSTART-RAMEND\r
+\r
+//************************************************\r
+// __ramfunc code copied to and executed from RAM.\r
+//************************************************\r
+\r
+-Z(DATA)CODE_I=RAMSTART-RAMEND\r
+\r
+//************************************************\r
+// ICCARM produces code for __ramfunc functions in\r
+// CODE_I segments. The -Q XLINK command line\r
+// option redirects XLINK to emit the code in the\r
+// CODE_ID segment instead, but to keep symbol and\r
+// debug information associated with the CODE_I\r
+// segment, where the code will execute.\r
+//************************************************\r
+\r
+-QCODE_I=CODE_ID\r
+\r
+//*************************************************************************\r
+// Stack and heap segments.\r
+//*************************************************************************\r
+\r
+//-D_CSTACK_SIZE=400\r
+// -D_SVC_STACK_SIZE=10\r
+//-D_IRQ_STACK_SIZE=500\r
+//-D_HEAP_SIZE=4\r
+\r
+//-Z(DATA)CSTACK+_CSTACK_SIZE=RAMSTART-RAMEND\r
+//-Z(DATA)SVC_STACK+_SVC_STACK_SIZE=RAMSTART-RAMEND\r
+//-Z(DATA)IRQ_STACK+_IRQ_STACK_SIZE,HEAP+_HEAP_SIZE=RAMSTART-RAMEND\r
+\r
+//*************************************************************************\r
+// ELF/DWARF support.\r
+//\r
+// Uncomment the line "-Felf" below to generate ELF/DWARF output.\r
+// Available format specifiers are:\r
+//\r
+// "-yn": Suppress DWARF debug output\r
+// "-yp": Multiple ELF program sections\r
+// "-yas": Format suitable for debuggers from ARM Ltd (also sets -p flag)\r
+//\r
+// "-Felf" and the format specifiers can also be supplied directly as\r
+// command line options, or selected from the Xlink Output tab in the\r
+// IAR Embedded Workbench.\r
+//*************************************************************************\r
+\r
+// -Felf\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+ NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.\r
+ The processor MUST be in supervisor mode when vTaskStartScheduler is\r
+ called. The demo applications included in the FreeRTOS.org download switch\r
+ to supervisor mode prior to main being called. If you are not using one of\r
+ these demo application projects then ensure Supervisor mode is used.\r
+*/\r
+\r
+/*\r
+ * Creates all the demo application tasks, then starts the scheduler. The WEB\r
+ * documentation provides more details of the demo application tasks.\r
+ *\r
+ * Main.c also creates a task called "Check". This only executes every three\r
+ * seconds but has the highest priority so is guaranteed to get processor time.\r
+ * Its main function is to check that all the other tasks are still operational.\r
+ * Each task (other than the "flash" tasks) maintains a unique count that is\r
+ * incremented each time the task successfully completes its function. Should\r
+ * any error occur within such a task the count is permanently halted. The\r
+ * check task inspects the count of each task to ensure it has changed since\r
+ * the last time the check task executed. If all the count variables have\r
+ * changed all the tasks are still executing error free, and the check task\r
+ * toggles the onboard LED. Should any task contain an error at any time\r
+ * the LED toggle rate will change from 3 seconds to 500ms.\r
+ *\r
+ */\r
+\r
+/* Library includes. */\r
+#include "RCCU.h"\r
+#include "wdg.h"\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo application includes. */\r
+#include "flash.h"\r
+#include "integer.h"\r
+#include "PollQ.h"\r
+#include "BlockQ.h"\r
+#include "semtest.h"\r
+#include "dynamic.h"\r
+#include "partest.h"\r
+#include "comtest2.h"\r
+\r
+/* Priorities for the demo application tasks. */\r
+#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 )\r
+#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+\r
+/* Constants required by the 'Check' task. */\r
+#define mainNO_ERROR_FLASH_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS )\r
+#define mainERROR_FLASH_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS )\r
+#define mainCHECK_TASK_LED ( 4 )\r
+\r
+/* Constants for the ComTest tasks. */\r
+#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 115200 )\r
+#define mainCOM_TEST_LED ( 6 ) /* The LED built onto the kickstart board. */\r
+\r
+/*\r
+ * The task that executes at the highest priority and calls\r
+ * prvCheckOtherTasksAreStillRunning(). See the description at the top\r
+ * of the file.\r
+ */\r
+static void vErrorChecks( void *pvParameters );\r
+\r
+/*\r
+ * Configure the processor for use with the IAR STR71x demo board. This\r
+ * just sets the PLL for the required frequency.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*\r
+ * Checks that all the demo application tasks are still executing without error\r
+ * - as described at the top of the file. Called by vErrorChecks().\r
+ */\r
+static portLONG prvCheckOtherTasksAreStillRunning( void );\r
+\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Starts all the other tasks, then starts the scheduler.\r
+ */\r
+void main( void )\r
+{\r
+ /* Setup any hardware that has not already been configured by the low\r
+ level init routines. */\r
+ prvSetupHardware();\r
+\r
+ /* Initialise the LED outputs for use by the demo application tasks. */\r
+ vParTestInitialise();\r
+\r
+ /* Start all the standard demo application tasks. */\r
+ vStartIntegerMathTasks( tskIDLE_PRIORITY );\r
+ vStartLEDFlashTasks( mainLED_TASK_PRIORITY );\r
+ vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
+ vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
+ vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
+ vStartDynamicPriorityTasks();\r
+ vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED );\r
+\r
+ /* Start the check task - which is defined in this file. */\r
+ xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
+\r
+ /* Start the scheduler.\r
+\r
+ NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.\r
+ The processor MUST be in supervisor mode when vTaskStartScheduler is\r
+ called. The demo applications included in the FreeRTOS.org download switch\r
+ to supervisor mode prior to main being called. If you are not using one of\r
+ these demo application projects then ensure Supervisor mode is used here. */\r
+\r
+ vTaskStartScheduler();\r
+\r
+ /* We should never get here as control is now taken by the scheduler. */\r
+ return;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+ /* Setup the PLL to generate a 48MHz clock from the 4MHz CLK. */\r
+\r
+ /* Turn of the div by two. */\r
+ RCCU_Div2Config( DISABLE );\r
+\r
+ /* 48MHz = ( 4MHz * 12 ) / 1 */\r
+ RCCU_PLL1Config( RCCU_PLL1_Mul_12, RCCU_Div_1 );\r
+ RCCU_RCLKSourceConfig( RCCU_PLL1_Output );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vErrorChecks( void *pvParameters )\r
+{\r
+portTickType xDelayPeriod = mainNO_ERROR_FLASH_PERIOD;\r
+portTickType xLastWakeTime;\r
+\r
+ /* The parameters are not used in this task. */\r
+ ( void ) pvParameters;\r
+\r
+ /* Initialise xLastWakeTime to ensure the first call to vTaskDelayUntil()\r
+ functions correctly. */\r
+ xLastWakeTime = xTaskGetTickCount();\r
+\r
+ /* Cycle for ever, delaying then checking all the other tasks are still\r
+ operating without error. If an error is detected then the delay period\r
+ is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so\r
+ the on board LED flash rate will increase. */\r
+\r
+ for( ;; )\r
+ {\r
+ /* Delay until it is time to execute again. The delay period is\r
+ shorter following an error so the LED flashes faster. */\r
+ vTaskDelayUntil( &xLastWakeTime, xDelayPeriod );\r
+ \r
+ /* Check all the standard demo application tasks are executing without\r
+ error. */\r
+ if( prvCheckOtherTasksAreStillRunning() != pdPASS )\r
+ {\r
+ /* An error has been detected in one of the tasks - flash faster. */\r
+ xDelayPeriod = mainERROR_FLASH_PERIOD;\r
+ }\r
+ \r
+ vParTestToggleLED( mainCHECK_TASK_LED );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portLONG prvCheckOtherTasksAreStillRunning( void )\r
+{\r
+portLONG lReturn = ( portLONG ) pdPASS;\r
+\r
+ /* Check all the demo tasks (other than the flash tasks) to ensure\r
+ that they are all still running, and that none of them have detected\r
+ an error. */\r
+\r
+ if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ lReturn = ( portLONG ) pdFAIL;\r
+ }\r
+\r
+ if( xArePollingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ lReturn = ( portLONG ) pdFAIL;\r
+ }\r
+\r
+ if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ lReturn = ( portLONG ) pdFAIL;\r
+ }\r
+\r
+ if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ lReturn = ( portLONG ) pdFAIL;\r
+ }\r
+\r
+ if( xAreComTestTasksStillRunning() != pdTRUE )\r
+ {\r
+ lReturn = ( portLONG ) pdFAIL;\r
+ }\r
+\r
+ if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )\r
+ {\r
+ lReturn = ( portLONG ) pdFAIL;\r
+ }\r
+\r
+ return lReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+ BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0.\r
+*/\r
+\r
+/* Library includes. */\r
+#include "uart.h"\r
+#include "gpio.h"\r
+#include "eic.h"\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "queue.h"\r
+\r
+/* Demo application includes. */\r
+#include "serial.h"\r
+\r
+#define UART0_Rx_Pin ( 0x0001<< 8 )\r
+#define UART0_Tx_Pin ( 0x0001<< 9 )\r
+\r
+#define serINVALID_QUEUE ( ( xQueueHandle ) 0 )\r
+#define serNO_BLOCK ( ( portTickType ) 0 )\r
+\r
+/* Macros to turn on and off the Tx empty interrupt. */\r
+#define serINTERRUPT_ON() UART0->IER |= UART_TxHalfEmpty\r
+#define serINTERRUPT_OFF() UART0->IER &= ~UART_TxHalfEmpty\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Queues used to hold received characters, and characters waiting to be\r
+transmitted. */\r
+static xQueueHandle xRxedChars;\r
+static xQueueHandle xCharsForTx;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Interrupt entry point written in the assembler file serialISR.s79. */\r
+extern void vSerialISREntry( void );\r
+\r
+/* The interrupt service routine - called from the assembly entry point. */\r
+__arm void vSerialISR( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * See the serial2.h header file.\r
+ */\r
+xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )\r
+{\r
+xComPortHandle xReturn;\r
+ \r
+ /* Create the queues used to hold Rx and Tx characters. */\r
+ xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );\r
+ xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );\r
+\r
+ /* If the queues were created correctly then setup the serial port\r
+ hardware. */\r
+ if( ( xRxedChars != serINVALID_QUEUE ) && ( xCharsForTx != serINVALID_QUEUE ) )\r
+ {\r
+ portENTER_CRITICAL();\r
+ {\r
+ /* Setup the UART port pins. */\r
+ GPIO_Config( GPIO0, UART0_Tx_Pin, GPIO_AF_PP );\r
+ GPIO_Config( GPIO0, UART0_Rx_Pin, GPIO_IN_TRI_CMOS );\r
+\r
+ /* Configure the UART. */\r
+ UART_OnOffConfig( UART0, ENABLE );\r
+ UART_FifoConfig( UART0, DISABLE );\r
+ UART_FifoReset( UART0, UART_RxFIFO );\r
+ UART_FifoReset( UART0, UART_TxFIFO );\r
+ UART_LoopBackConfig(UART0, DISABLE );\r
+ UART_Config( UART0, ulWantedBaud, UART_NO_PARITY, UART_1_StopBits, UARTM_8D );\r
+ UART_RxConfig( UART0, ENABLE );\r
+\r
+ /* Configure the IEC for the UART interrupts. */\r
+ EIC_IRQChannelPriorityConfig( UART0_IRQChannel, 1 );\r
+ EIC_IRQChannelConfig( UART0_IRQChannel, ENABLE );\r
+ EIC_IRQConfig( ENABLE );\r
+ UART_ItConfig( UART0, UART_RxBufFull, ENABLE );\r
+ }\r
+ portEXIT_CRITICAL();\r
+ }\r
+ else\r
+ {\r
+ xReturn = ( xComPortHandle ) 0;\r
+ }\r
+\r
+ /* This demo file only supports a single port but we have to return\r
+ something to comply with the standard demo header file. */\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )\r
+{\r
+ /* The port handle is not required as this driver only supports one port. */\r
+ ( void ) pxPort;\r
+\r
+ /* Get the next character from the buffer. Return false if no characters\r
+ are available, or arrive before xBlockTime expires. */\r
+ if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )\r
+ {\r
+ return pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ return pdFALSE;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength )\r
+{\r
+signed portCHAR *pxNext;\r
+\r
+ /* A couple of parameters that this port does not use. */\r
+ ( void ) usStringLength;\r
+ ( void ) pxPort;\r
+\r
+ /* NOTE: This implementation does not handle the queue being full as no\r
+ block time is used! */\r
+\r
+ /* The port handle is not required as this driver only supports UART0. */\r
+ ( void ) pxPort;\r
+\r
+ /* Send each character in the string, one at a time. */\r
+ pxNext = ( signed portCHAR * ) pcString;\r
+ while( *pxNext )\r
+ {\r
+ xSerialPutChar( pxPort, *pxNext, serNO_BLOCK );\r
+ pxNext++;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )\r
+{\r
+ /* Place the character in the queue of characters to be transmitted. */\r
+ if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )\r
+ {\r
+ return pdFAIL;\r
+ }\r
+\r
+ /* Turn on the Tx interrupt so the ISR will remove the character from the\r
+ queue and send it. This does not need to be in a critical section as\r
+ if the interrupt has already removed the character the next interrupt\r
+ will simply turn off the Tx interrupt again. */\r
+ serINTERRUPT_ON();\r
+\r
+ return pdPASS;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSerialClose( xComPortHandle xPort )\r
+{\r
+ /* Not supported as not required by the demo application. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Serial port ISR. This can cause a context switch so is not defined as a\r
+standard ISR using the __irq keyword. Instead a wrapper function is defined\r
+within serialISR.s79 which in turn calls this function. See the port\r
+documentation on the FreeRTOS.org website for more information. */\r
+__arm void vSerialISR( void )\r
+{\r
+unsigned portSHORT usStatus;\r
+signed portCHAR cChar;\r
+portBASE_TYPE xTaskWokenByTx = pdFALSE, xTaskWokenByPost = pdFALSE;\r
+\r
+ /* What caused the interrupt? */\r
+ usStatus = UART_FlagStatus( UART0 );\r
+\r
+ if( usStatus & UART_TxHalfEmpty )\r
+ {\r
+ /* The interrupt was caused by the THR becoming empty. Are there any\r
+ more characters to transmit? */\r
+ if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWokenByTx ) == pdTRUE )\r
+ {\r
+ /* A character was retrieved from the queue so can be sent to the\r
+ THR now. */\r
+ UART0->TxBUFR = cChar;\r
+ }\r
+ else\r
+ {\r
+ /* Queue empty, nothing to send so turn off the Tx interrupt. */\r
+ serINTERRUPT_OFF();\r
+ } \r
+ }\r
+\r
+ if( usStatus & UART_RxBufFull )\r
+ {\r
+ /* The interrupt was caused by a character being received. Grab the\r
+ character from the RHR and place it in the queue of received\r
+ characters. */\r
+ cChar = UART0->RxBUFR;\r
+ xTaskWokenByPost = xQueueSendFromISR( xRxedChars, &cChar, xTaskWokenByPost );\r
+ }\r
+\r
+ /* If a task was woken by either a character being received or a character\r
+ being transmitted then we may need to switch to another task. */\r
+ portEND_SWITCHING_ISR( ( xTaskWokenByPost || xTaskWokenByTx ) );\r
+\r
+ /* End the interrupt in the EIC. */\r
+ portCLEAR_EIC();\r
+}\r
+\r
+\r
+\r
+\r
+\r
+ \r
--- /dev/null
+ RSEG ICODE:CODE\r
+ CODE32\r
+\r
+ EXTERN vSerialISR\r
+ PUBLIC vSerialISREntry\r
+\r
+; Wrapper for the serial port interrupt service routine. This can cause a\r
+; context switch so requires an assembly wrapper.\r
+\r
+; Defines the portSAVE_CONTEXT and portRESTORE_CONTEXT macros.\r
+#include "ISR_Support.h"\r
+\r
+vSerialISREntry:\r
+\r
+ portSAVE_CONTEXT ; Save the context of the current task.\r
+\r
+ bl vSerialISR ; Call the ISR routine.\r
+\r
+ portRESTORE_CONTEXT ; Restore the context of the current task -\r
+ ; which may be different to the task that\r
+ ; was interrupted.\r
+\r
+ END\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<Project>\r
+ <Desktop>\r
+ <Static>\r
+ <Workspace>\r
+ <ColumnWidths>\r
+ \r
+ \r
+ \r
+ \r
+ <Column0>129</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>\r
+ </Workspace>\r
+ <Disassembly>\r
+ <PreferedWindows>\r
+ \r
+ \r
+ \r
+ \r
+ <Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows>\r
+ \r
+ \r
+ \r
+ <MixedMode>1</MixedMode><CodeCovEnabled>0</CodeCovEnabled><CodeCovShow>0</CodeCovShow></Disassembly>\r
+ <Debug-Log/>\r
+ <Build>\r
+ \r
+ \r
+ \r
+ \r
+ <ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1153</ColumnWidth1><ColumnWidth2>307</ColumnWidth2><ColumnWidth3>76</ColumnWidth3></Build>\r
+ <Register><PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows></Register><Breakpoints/></Static>\r
+ <Windows>\r
+ \r
+ \r
+ <Wnd2>\r
+ <Tabs>\r
+ <Tab>\r
+ <Identity>TabID-24393-22702</Identity>\r
+ <TabName>Workspace</TabName>\r
+ <Factory>Workspace</Factory>\r
+ <Session>\r
+ \r
+ <NodeDict><ExpandedNode>RTOSDemo</ExpandedNode><ExpandedNode>RTOSDemo/Demo Source</ExpandedNode><ExpandedNode>RTOSDemo/RTOS Source</ExpandedNode><ExpandedNode>RTOSDemo/System Files</ExpandedNode><ExpandedNode>RTOSDemo/System Files/vect.s79</ExpandedNode></NodeDict></Session>\r
+ </Tab>\r
+ </Tabs>\r
+ \r
+ <SelectedTab>0</SelectedTab></Wnd2><Wnd3>\r
+ <Tabs>\r
+ <Tab>\r
+ <Identity>TabID-13122-22708</Identity>\r
+ <TabName>Debug Log</TabName>\r
+ <Factory>Debug-Log</Factory>\r
+ <Session/>\r
+ </Tab>\r
+ <Tab>\r
+ <Identity>TabID-23870-22711</Identity>\r
+ <TabName>Build</TabName>\r
+ <Factory>Build</Factory>\r
+ <Session/>\r
+ </Tab>\r
+ <Tab><Identity>TabID-19116-28152</Identity><TabName>Breakpoints</TabName><Factory>Breakpoints</Factory><Session/></Tab></Tabs>\r
+ \r
+ <SelectedTab>0</SelectedTab></Wnd3><Wnd0><Tabs><Tab><Identity>TabID-10243-6871</Identity><TabName>Register</TabName><Factory>Register</Factory><Session><REG1>0</REG1><REG2>0</REG2><Group>0</Group><States>1</States><State0>CPSR</State0></Session></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd0></Windows>\r
+ <Editor>\r
+ \r
+ \r
+ \r
+ \r
+ <Pane/><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>\r
+ <Positions>\r
+ \r
+ \r
+ \r
+ \r
+ \r
+ <Top><Row0><Sizes><Toolbar-0084c368><key>iaridepm1</key></Toolbar-0084c368><Toolbar-011f0628><key>debuggergui1</key></Toolbar-011f0628></Sizes></Row0></Top><Left><Row0><Sizes><Wnd2><Rect><Top>-2</Top><Left>-2</Left><Bottom>853</Bottom><Right>203</Right><x>-2</x><y>-2</y><xscreen>125</xscreen><yscreen>125</yscreen><sizeHorzCX>78125</sizeHorzCX><sizeHorzCY>111706</sizeHorzCY><sizeVertCX>128124</sizeVertCX><sizeVertCY>764075</sizeVertCY></Rect></Wnd2></Sizes></Row0></Left><Right><Row0><Sizes><Wnd0><Rect><Top>-2</Top><Left>-2</Left><Bottom>853</Bottom><Right>447</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>125000</sizeHorzCX><sizeHorzCY>178731</sizeHorzCY><sizeVertCX>280625</sizeVertCX><sizeVertCY>764075</sizeVertCY></Rect></Wnd0></Sizes></Row0></Right><Bottom><Row0><Sizes><Wnd3><Rect><Top>-2</Top><Left>-2</Left><Bottom>219</Bottom><Right>1602</Right><x>-2</x><y>-2</y><xscreen>1604</xscreen><yscreen>221</yscreen><sizeHorzCX>1002500</sizeHorzCX><sizeHorzCY>197497</sizeHorzCY><sizeVertCX>78125</sizeVertCX><sizeVertCY>111706</sizeVertCY></Rect></Wnd3></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>\r
+ </Desktop>\r
+</Project>\r
+\r
+\r
--- /dev/null
+[DisAssemblyWindow]\r
+NumStates=_ 1\r
+State 1=_ 1\r
+[JLinkDriver]\r
+WatchVectorCatch=_ 0\r
+WatchCond=_ 0\r
+Watch0=_ 0 "0x00000000" 0 "0x00000000" 0 "0x00000000" 0 "0x00000000" 0 0 0 0\r
+Watch1=_ 0 "0x00000000" 0 "0x00000000" 0 "0x00000000" 0 "0x00000000" 0 0 0 0\r
+[Low Level]\r
+Pipeline mode=0\r
+Initialized=0\r
+[Disassemble mode]\r
+mode=0\r
+[Breakpoints]\r
+Bp0=_ "Code" "{E:\Dev\FreeRTOS\Source\portable\IAR\STR71x\port.c}.240.4@1" 1 0 0 0 "" 0 ""\r
+Count=1\r
+[Log file]\r
+LoggingEnabled=_ 0\r
+LogFile=_ ""\r
+Category=_ 0\r
+[TermIOLog]\r
+LoggingEnabled=_ 0\r
+LogFile=_ ""\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<Workspace>\r
+ <ConfigDictionary>\r
+ \r
+ <CurrentConfigs><Project>RTOSDemo/Debug</Project></CurrentConfigs></ConfigDictionary>\r
+ <Desktop>\r
+ <Static>\r
+ <Workspace>\r
+ <ColumnWidths>\r
+ \r
+ \r
+ \r
+ \r
+ <Column0>227</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>\r
+ </Workspace>\r
+ <Build>\r
+ \r
+ \r
+ \r
+ \r
+ <ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1153</ColumnWidth1><ColumnWidth2>307</ColumnWidth2><ColumnWidth3>76</ColumnWidth3></Build>\r
+ <TerminalIO/>\r
+ <Profiling/>\r
+ <Debug-Log/>\r
+ <CodeCoveragePlugin/><Breakpoints/></Static>\r
+ <Windows>\r
+ \r
+ \r
+ <Wnd2>\r
+ <Tabs>\r
+ <Tab>\r
+ <Identity>TabID-14962-21036</Identity>\r
+ <TabName>Workspace</TabName>\r
+ <Factory>Workspace</Factory>\r
+ <Session>\r
+ \r
+ <NodeDict><ExpandedNode>RTOSDemo</ExpandedNode><ExpandedNode>RTOSDemo/source</ExpandedNode></NodeDict></Session>\r
+ </Tab>\r
+ </Tabs>\r
+ \r
+ <SelectedTab>0</SelectedTab></Wnd2><Wnd3>\r
+ <Tabs>\r
+ <Tab>\r
+ <Identity>TabID-24623-22493</Identity>\r
+ <TabName>Build</TabName>\r
+ <Factory>Build</Factory>\r
+ <Session/>\r
+ </Tab>\r
+ <Tab>\r
+ <Identity>TabID-13645-22698</Identity>\r
+ <TabName>Debug Log</TabName>\r
+ <Factory>Debug-Log</Factory>\r
+ <Session/>\r
+ </Tab>\r
+ <Tab><Identity>TabID-25855-25419</Identity><TabName>Breakpoints</TabName><Factory>Breakpoints</Factory><Session/></Tab></Tabs>\r
+ \r
+ <SelectedTab>0</SelectedTab></Wnd3></Windows>\r
+ <Editor>\r
+ \r
+ \r
+ \r
+ \r
+ <Pane><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Demo\ARM7_STR71x_IAR\main.c</Filename><XPos>0</XPos><YPos>98</YPos><SelStart>4693</SelStart><SelEnd>4693</SelEnd></Tab><ActiveTab>0</ActiveTab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>\r
+ <Positions>\r
+ \r
+ \r
+ \r
+ \r
+ \r
+ <Top><Row0><Sizes><Toolbar-0084c368><key>iaridepm1</key></Toolbar-0084c368></Sizes></Row0><Row1><Sizes><Toolbar-011f0628><key>debuggergui1</key></Toolbar-011f0628></Sizes></Row1></Top><Left><Row0><Sizes><Wnd2><Rect><Top>-2</Top><Left>-2</Left><Bottom>675</Bottom><Right>301</Right><x>-2</x><y>-2</y><xscreen>21</xscreen><yscreen>21</yscreen><sizeHorzCX>13125</sizeHorzCX><sizeHorzCY>18766</sizeHorzCY><sizeVertCX>189375</sizeVertCX><sizeVertCY>605004</sizeVertCY></Rect></Wnd2></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd3><Rect><Top>-2</Top><Left>-2</Left><Bottom>397</Bottom><Right>1602</Right><x>-2</x><y>-2</y><xscreen>1604</xscreen><yscreen>399</yscreen><sizeHorzCX>1002500</sizeHorzCX><sizeHorzCY>356568</sizeHorzCY><sizeVertCX>13125</sizeVertCX><sizeVertCY>18766</sizeVertCY></Rect></Wnd3></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>\r
+ </Desktop>\r
+</Workspace>\r
+\r
+\r
--- /dev/null
+#include "FreeRTOSConfig.h"\r
+\r
+IVR_ADDR DEFINE 0xFFFFF818\r
+\r
+;*******************************************************************************\r
+; Import the Reset_Handler address from 71x_init.s\r
+;*******************************************************************************\r
+\r
+ IMPORT __program_start\r
+\r
+;*******************************************************************************\r
+; Import exception handlers\r
+;*******************************************************************************\r
+\r
+ IMPORT vPortYieldProcessor ; FreeRTOS SWI handler\r
+\r
+;*******************************************************************************\r
+; Import IRQ handlers from 71x_it.c\r
+;*******************************************************************************\r
+\r
+ IMPORT vPortNonPreemptiveTick ; Cooperative FreeRTOS tick handler\r
+ IMPORT vPortPreemptiveTickISR ; Preemptive FreeRTOS tick handler\r
+ IMPORT vSerialISREntry ; Demo serial port handler\r
+\r
+;*******************************************************************************\r
+; Export Peripherals IRQ handlers table address\r
+;*******************************************************************************\r
+\r
+ CODE32\r
+\r
+\r
+ LDR PC, Reset_Addr\r
+ LDR PC, Undefined_Addr\r
+ LDR PC, SWI_Addr\r
+ LDR PC, Prefetch_Addr\r
+ LDR PC, Abort_Addr\r
+ NOP ; Reserved vector\r
+ LDR PC, =IVR_ADDR\r
+ LDR PC, FIQ_Addr\r
+\r
+\r
+\r
+;*******************************************************************************\r
+; Exception handlers address table\r
+;*******************************************************************************\r
+\r
+Reset_Addr DCD __program_start\r
+Undefined_Addr DCD UndefinedHandler\r
+SWI_Addr DCD vPortYieldProcessor\r
+Prefetch_Addr DCD PrefetchAbortHandler\r
+Abort_Addr DCD DataAbortHandler\r
+ DCD 0 ; Reserved vector\r
+IRQ_Addr DCD IRQHandler\r
+FIQ_Addr DCD FIQHandler\r
+\r
+;*******************************************************************************\r
+; Peripherals IRQ handlers address table\r
+;*******************************************************************************\r
+\r
+ EXPORT T0TIMI_Addr\r
+\r
+T0TIMI_Addr DCD DefaultISR\r
+FLASH_Addr DCD DefaultISR\r
+RCCU_Addr DCD DefaultISR\r
+RTC_Addr DCD DefaultISR\r
+#if configUSE_PREEMPTION == 0\r
+WDG_Addr DCD vPortNonPreemptiveTick ; Tick ISR if the cooperative scheduler is used.\r
+#else\r
+WDG_Addr DCD vPortPreemptiveTickISR ; Tick ISR if the preemptive scheduler is used.\r
+#endif\r
+XTI_Addr DCD DefaultISR\r
+USBHP_Addr DCD DefaultISR\r
+I2C0ITERR_Addr DCD DefaultISR\r
+I2C1ITERR_ADDR DCD DefaultISR\r
+UART0_Addr DCD vSerialISREntry\r
+UART1_Addr DCD DefaultISR\r
+UART2_ADDR DCD DefaultISR\r
+UART3_ADDR DCD DefaultISR\r
+BSPI0_ADDR DCD DefaultISR\r
+BSPI1_Addr DCD DefaultISR\r
+I2C0_Addr DCD DefaultISR\r
+I2C1_Addr DCD DefaultISR\r
+CAN_Addr DCD DefaultISR\r
+ADC12_Addr DCD DefaultISR\r
+T1TIMI_Addr DCD DefaultISR\r
+T2TIMI_Addr DCD DefaultISR\r
+T3TIMI_Addr DCD DefaultISR\r
+ DCD 0 ; reserved\r
+ DCD 0 ; reserved\r
+ DCD 0 ; reserved\r
+HDLC_Addr DCD DefaultISR\r
+USBLP_Addr DCD DefaultISR\r
+ DCD 0 ; reserved\r
+ DCD 0 ; reserved\r
+T0TOI_Addr DCD DefaultISR\r
+T0OC1_Addr DCD DefaultISR\r
+T0OC2_Addr DCD DefaultISR\r
+\r
+\r
+;*******************************************************************************\r
+; Exception Handlers\r
+;*******************************************************************************\r
+\r
+\r
+UndefinedHandler\r
+ b UndefinedHandler\r
+\r
+PrefetchAbortHandler\r
+ b PrefetchAbortHandler\r
+\r
+DataAbortHandler\r
+ b DataAbortHandler\r
+\r
+IRQHandler\r
+ b DefaultISR\r
+\r
+FIQHandler\r
+ b FIQHandler\r
+\r
+DefaultISR\r
+ b DefaultISR\r
+\r
+\r
+\r
+ LTORG\r
+\r
+ END\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+#include <iom323.h>\r
+\r
+#define configCALL_STACK_SIZE 20\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. \r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 8000000 )\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 4 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 85 )\r
+#define configTOTAL_HEAP_SIZE ( (size_t ) ( 1500 ) )\r
+#define configMAX_TASK_NAME_LEN ( 8 )\r
+#define configUSE_TRACE_FACILITY 0\r
+#define configUSE_16_BIT_TICKS 1\r
+#define configIDLE_SHOULD_YIELD 1\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet 0\r
+#define INCLUDE_uxTaskPriorityGet 0\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 0\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* \r
+Changes from V2.0.0\r
+\r
+ + Use scheduler suspends in place of critical sections.\r
+\r
+Changes from V2.6.0\r
+\r
+ + Replaced the inb() and outb() functions with direct memory\r
+ access. This allows the port to be built with the 20050414 build of\r
+ WinAVR.\r
+*/\r
+\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "partest.h"\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple parallel port IO routines.\r
+ *-----------------------------------------------------------*/\r
+\r
+#define partstALL_BITS_OUTPUT ( ( unsigned portCHAR ) 0xff )\r
+#define partstALL_OUTPUTS_OFF ( ( unsigned portCHAR ) 0xff )\r
+#define partstMAX_OUTPUT_LED ( ( unsigned portCHAR ) 7 )\r
+\r
+static volatile unsigned portCHAR ucCurrentOutputValue = partstALL_OUTPUTS_OFF; /*lint !e956 File scope parameters okay here. */\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestInitialise( void )\r
+{\r
+ ucCurrentOutputValue = partstALL_OUTPUTS_OFF;\r
+\r
+ /* Set port B direction to outputs. Start with all output off. */\r
+ DDRB = partstALL_BITS_OUTPUT;\r
+ PORTB = ucCurrentOutputValue;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )\r
+{\r
+unsigned portCHAR ucBit = ( unsigned portCHAR ) 1;\r
+\r
+ if( uxLED <= partstMAX_OUTPUT_LED )\r
+ {\r
+ ucBit <<= uxLED;\r
+ } \r
+\r
+ vTaskSuspendAll();\r
+ {\r
+ if( xValue == pdTRUE )\r
+ {\r
+ ucBit ^= ( unsigned portCHAR ) 0xff;\r
+ ucCurrentOutputValue &= ucBit;\r
+ }\r
+ else\r
+ {\r
+ ucCurrentOutputValue |= ucBit;\r
+ }\r
+\r
+ PORTB = ucCurrentOutputValue;\r
+ }\r
+ xTaskResumeAll();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+unsigned portCHAR ucBit;\r
+\r
+ if( uxLED <= partstMAX_OUTPUT_LED )\r
+ {\r
+ ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED;\r
+\r
+ vTaskSuspendAll();\r
+ {\r
+ if( ucCurrentOutputValue & ucBit )\r
+ {\r
+ ucCurrentOutputValue &= ~ucBit;\r
+ }\r
+ else\r
+ {\r
+ ucCurrentOutputValue |= ucBit;\r
+ }\r
+\r
+ PORTB = ucCurrentOutputValue;\r
+ }\r
+ xTaskResumeAll(); \r
+ }\r
+}\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+ * Creates all the demo application tasks, then starts the scheduler. The WEB\r
+ * documentation provides more details of the demo application tasks.\r
+ *\r
+ * Main. c also creates a task called "Check". This only executes every three\r
+ * seconds but has the highest priority so is guaranteed to get processor time.\r
+ * Its main function is to check that all the other tasks are still operational.\r
+ * Each task that does not flash an LED maintains a unique count that is\r
+ * incremented each time the task successfully completes its function. Should\r
+ * any error occur within such a task the count is permanently halted. The\r
+ * check task inspects the count of each task to ensure it has changed since\r
+ * the last time the check task executed. If all the count variables have\r
+ * changed all the tasks are still executing error free, and the check task\r
+ * toggles an LED. Should any task contain an error at any time the LED toggle\r
+ * will stop.\r
+ *\r
+ * The LED flash and communications test tasks do not maintain a count.\r
+ */\r
+\r
+/*\r
+Changes from V1.2.0\r
+ \r
+ + Changed the baud rate for the serial test from 19200 to 57600.\r
+\r
+Changes from V1.2.3\r
+\r
+ + The integer and comtest tasks are now used when the cooperative scheduler\r
+ is being used. Previously they were only used with the preemptive\r
+ scheduler.\r
+\r
+Changes from V1.2.5\r
+\r
+ + Set the baud rate to 38400. This has a smaller error percentage with an\r
+ 8MHz clock (according to the manual).\r
+\r
+Changes from V2.0.0\r
+\r
+ + Delay periods are now specified using variables and constants of\r
+ portTickType rather than unsigned portLONG.\r
+\r
+Changes from V2.2.0\r
+\r
+ + File can now be built using either the IAR or WinAVR compiler.\r
+\r
+Changes from V2.6.1\r
+\r
+ + The IAR and WinAVR AVR ports are now maintained separately.\r
+*/\r
+\r
+#include <stdlib.h>\r
+#include <string.h>\r
+\r
+#ifdef GCC_MEGA_AVR\r
+ /* EEPROM routines used only with the WinAVR compiler. */\r
+ #include <avr/eeprom.h>\r
+#endif\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo file headers. */\r
+#include "PollQ.h"\r
+#include "integer.h"\r
+#include "serial.h"\r
+#include "comtest.h"\r
+#include "flash.h"\r
+#include "print.h"\r
+#include "partest.h"\r
+\r
+/* Priority definitions for most of the tasks in the demo application. Some\r
+tasks just use the idle priority. */\r
+#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+\r
+/* Baud rate used by the serial port tasks. */\r
+#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 38400 )\r
+\r
+/* LED used by the serial port tasks. This is toggled on each character Tx,\r
+and mainCOM_TEST_LED + 1 is toggles on each character Rx. */\r
+#define mainCOM_TEST_LED ( 4 )\r
+\r
+/* LED that is toggled by the check task. The check task periodically checks\r
+that all the other tasks are operating without error. If no errors are found\r
+the LED is toggled. If an error is found at any time the LED is never toggles\r
+again. */\r
+#define mainCHECK_TASK_LED ( 7 )\r
+\r
+/* The period between executions of the check task. */\r
+#define mainCHECK_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS )\r
+\r
+/* An address in the EEPROM used to count resets. This is used to check that\r
+the demo application is not unexpectedly resetting. */\r
+#define mainRESET_COUNT_ADDRESS ( ( void * ) 0x50 )\r
+\r
+/*\r
+ * The task function for the "Check" task.\r
+ */\r
+static void vErrorChecks( void *pvParameters );\r
+\r
+/*\r
+ * Checks the unique counts of other tasks to ensure they are still operational.\r
+ * Flashes an LED if everything is okay.\r
+ */\r
+static void prvCheckOtherTasksAreStillRunning( void );\r
+\r
+/*\r
+ * Called on boot to increment a count stored in the EEPROM. This is used to\r
+ * ensure the CPU does not reset unexpectedly.\r
+ */\r
+static void prvIncrementResetCount( void );\r
+\r
+portSHORT main( void )\r
+{\r
+ prvIncrementResetCount();\r
+\r
+ /* Setup the LED's for output. */\r
+ vParTestInitialise();\r
+\r
+ vStartIntegerMathTasks( tskIDLE_PRIORITY );\r
+ vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED );\r
+ vStartLEDFlashTasks( mainLED_TASK_PRIORITY );\r
+ vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
+\r
+ xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
+\r
+ /* In this port, to use preemptive scheduler define configUSE_PREEMPTION\r
+ as 1 in portmacro.h. To use the cooperative scheduler define\r
+ configUSE_PREEMPTION as 0. */\r
+ vTaskStartScheduler();\r
+\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vErrorChecks( void *pvParameters )\r
+{\r
+static volatile unsigned portLONG ulDummyVariable = 3UL;\r
+\r
+ /* The parameters are not used. */\r
+ ( void ) pvParameters;\r
+\r
+ /* Cycle for ever, delaying then checking all the other tasks are still\r
+ operating without error. */\r
+ for( ;; )\r
+ {\r
+ vTaskDelay( mainCHECK_PERIOD );\r
+\r
+ /* Perform a bit of 32bit maths to ensure the registers used by the\r
+ integer tasks get some exercise. The result here is not important -\r
+ see the demo application documentation for more info. */\r
+ ulDummyVariable *= 3;\r
+ \r
+ prvCheckOtherTasksAreStillRunning();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCheckOtherTasksAreStillRunning( void )\r
+{\r
+static portBASE_TYPE xErrorHasOccurred = pdFALSE;\r
+\r
+ if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ xErrorHasOccurred = pdTRUE;\r
+ }\r
+\r
+ if( xAreComTestTasksStillRunning() != pdTRUE )\r
+ {\r
+ xErrorHasOccurred = pdTRUE;\r
+ }\r
+\r
+ if( xArePollingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ xErrorHasOccurred = pdTRUE;\r
+ }\r
+\r
+ if( xErrorHasOccurred == pdFALSE )\r
+ {\r
+ /* Toggle the LED if everything is okay so we know if an error occurs even if not\r
+ using console IO. */\r
+ vParTestToggleLED( mainCHECK_TASK_LED );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvIncrementResetCount( void )\r
+{\r
+unsigned portCHAR ucCount;\r
+const unsigned portCHAR ucReadBit = ( unsigned portCHAR ) 0x01;\r
+const unsigned portCHAR ucWrite1 = ( unsigned portCHAR ) 0x04;\r
+const unsigned portCHAR ucWrite2 = ( unsigned portCHAR ) 0x02;\r
+\r
+ /* Increment the EEPROM value at 0x00.\r
+ \r
+ Setup the EEPROM address. */\r
+ EEARH = 0x00;\r
+ EEARL = 0x00;\r
+ \r
+ /* Set the read enable bit. */\r
+ EECR |= ucReadBit;\r
+\r
+ /* Wait for the read. */\r
+ while( EECR & ucReadBit );\r
+ \r
+ /* The byte is ready. */\r
+ ucCount = EEDR;\r
+ \r
+ /* Increment the reset count, then write the byte back. */\r
+ ucCount++;\r
+ EEDR = ucCount;\r
+ EECR = ucWrite1;\r
+ EECR = ( ucWrite1 | ucWrite2 );\r
+}\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+ <fileVersion>1</fileVersion>\r
+ <configuration>\r
+ <name>Debug</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\ParTest\ParTest.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCAVR</name>\r
+ <file>$PROJ_DIR$\Output\Obj\ParTest.r90</file>\r
+ </tool>\r
+ </outputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\serial\serial.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCAVR</name>\r
+ <file>$PROJ_DIR$\Output\Obj\serial.r90</file>\r
+ </tool>\r
+ </outputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\IAR\ATMega323\portmacro.s90</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>AAVR</name>\r
+ <file>$PROJ_DIR$\Output\Obj\portmacro.r90</file>\r
+ </tool>\r
+ </outputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\comtest.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCAVR</name>\r
+ <file>$PROJ_DIR$\Output\Obj\comtest.r90</file>\r
+ </tool>\r
+ </outputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\tasks.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCAVR</name>\r
+ <file>$PROJ_DIR$\Output\Obj\tasks.r90</file>\r
+ </tool>\r
+ </outputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\integer.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCAVR</name>\r
+ <file>$PROJ_DIR$\Output\Obj\integer.r90</file>\r
+ </tool>\r
+ </outputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\MemMang\heap_1.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCAVR</name>\r
+ <file>$PROJ_DIR$\Output\Obj\heap_1.r90</file>\r
+ </tool>\r
+ </outputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\IAR\ATMega323\port.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCAVR</name>\r
+ <file>$PROJ_DIR$\Output\Obj\port.r90</file>\r
+ </tool>\r
+ </outputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\PollQ.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCAVR</name>\r
+ <file>$PROJ_DIR$\Output\Obj\PollQ.r90</file>\r
+ </tool>\r
+ </outputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\queue.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCAVR</name>\r
+ <file>$PROJ_DIR$\Output\Obj\queue.r90</file>\r
+ </tool>\r
+ </outputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\flash.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCAVR</name>\r
+ <file>$PROJ_DIR$\Output\Obj\flash.r90</file>\r
+ </tool>\r
+ </outputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\main.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCAVR</name>\r
+ <file>$PROJ_DIR$\Output\Obj\main.r90</file>\r
+ </tool>\r
+ </outputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\list.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCAVR</name>\r
+ <file>$PROJ_DIR$\Output\Obj\list.r90</file>\r
+ </tool>\r
+ </outputs>\r
+ </file>\r
+ <file>\r
+ <name>[ROOT_NODE]</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>XLINK</name>\r
+ <file>$PROJ_DIR$\Output\Exe\rtosdemo.a90</file>\r
+ <file>$PROJ_DIR$\Output\Exe\rtosdemo.d90</file>\r
+ </tool>\r
+ </outputs>\r
+ </file>\r
+ <forcedrebuild>\r
+ <name>[MULTI_TOOL]</name>\r
+ <tool>XLINK</tool>\r
+ </forcedrebuild>\r
+ </configuration>\r
+</project>\r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+ <fileVersion>1</fileVersion>\r
+ <configuration>\r
+ <name>Debug</name>\r
+ <toolchain>\r
+ <name>AVR</name>\r
+ </toolchain>\r
+ <debug>1</debug>\r
+ <settings>\r
+ <name>C-SPY</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>11</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CSVariantProcessor</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacFile</name>\r
+ <state>$TOOLKIT_DIR$\*.mac</state>\r
+ </option>\r
+ <option>\r
+ <name>DDFile</name>\r
+ <state>$TOOLKIT_DIR$\Config\iom323.ddf</state>\r
+ </option>\r
+ <option>\r
+ <name>CInput</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCEnhancedCore</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OC64BitDoubles</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>DdfFileSlave</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>RunToEnable</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RunToName</name>\r
+ <state>main</state>\r
+ </option>\r
+ <option>\r
+ <name>newDDFileOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CSVariantEepromSize</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CSVariant64KFlash</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CdDllSlave</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CDynDriver</name>\r
+ <state>SIMAVR</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>CCRAVR</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCCRAVRDriver</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCCRAVRExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCCRAVRExtraOptionsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCCRAVRPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCCRAVRBaud</name>\r
+ <version>0</version>\r
+ <state>5</state>\r
+ </option>\r
+ <option>\r
+ <name>OCCRAVRParity</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCCRAVRDataBits</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCCRAVRStopBits</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCCRAVRHandshake</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCCRAVRAllComm</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCCRAVRDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCCRAVRLogFile</name>\r
+ <state>cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>OCCRAVRSuppressLoad</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCCRAVRFastDownload</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCCRAVRTargetCCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCCRAVRdownloadToData</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ICE200AVR</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OICE200AVRDriver</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OICE200AVRExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OICE200AVRExtraOptionsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OICE200AVRPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OICE200AVRBaud</name>\r
+ <version>0</version>\r
+ <state>5</state>\r
+ </option>\r
+ <option>\r
+ <name>OICE200AVRParity</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OICE200AVRDataBits</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OICE200AVRStopBits</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OICE200AVRHandshake</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OICE200AVRAllComm</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OICE200AVRDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OICE200AVRLogFile</name>\r
+ <state>cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>OICE200AVRHighSpeed</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OICE200AVRSingleStepTimers</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OICE200AVRRestoreEEPROM</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OICE200AVRComPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OICE200AVRSuppLoad</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OICE200AVRConsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OICE200AVRIce200ResetDelayList</name>\r
+ <version>8</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OICE200AVRIce200downloadToData</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>JTAGICEAVR</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OJTAGICEAVRDriver</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEAVRExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEAVRExtraOptionsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEAVRPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEAVRBaud</name>\r
+ <version>0</version>\r
+ <state>5</state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEAVRParity</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEAVRDataBits</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEAVRStopBits</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEAVRHandshake</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEAVRAllComm</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEAVRDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEAVRLogFile</name>\r
+ <state>cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEAVRJtagIceDefaultCom</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEAVRJtagIceComPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEAVRJtagIceSuppLoad</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEAVRJtagIceConsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEAVRJtagIceJtagFreqRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEAVRJtagIceJtagFreqManually</name>\r
+ <state>100000</state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEAVRJtagIceJtagFreq</name>\r
+ <version>0</version>\r
+ <state>5</state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEAVRJtagIceJtagDeviceBefore</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEAVRJtagIceJtagDeviceAfter</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEAVRJtagIceJtagInstrBitsBefore</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEAVRJtagIceJtagInstrBitsAfter</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEAVRJtagIceDaisyChain</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEAVRJtagDebugTimers</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEAVRJtagDebugEeprom</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEAVRJtagDebugReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEAVRJtagDebugFuses</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEAVRJtagIcedownloadToData</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>JTAGICEMKIIAVR</name>\r
+ <archiveVersion>1</archiveVersion>\r
+ <data>\r
+ <version>3</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OJTAGICEMKIIAVRDriver</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEMKIIAVRExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEMKIIAVRExtraOptionsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEMKIIAVRPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEMKIIAVRBaud</name>\r
+ <version>0</version>\r
+ <state>5</state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEMKIIAVRParity</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEMKIIAVRDataBits</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEMKIIAVRStopBits</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEMKIIAVRHandshake</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEMKIIAVRAllComm</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEMKIIAVRDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEMKIIAVRLogFile</name>\r
+ <state>cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEMKIIAVRJtagIceDefaultCom</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEMKIIAVRJtagIceComPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEMKIIAVRJtagIceSuppLoad</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEMKIIAVRJtagIceConsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEMKIIAVRJtagIceJtagFreqRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEMKIIAVRJtagIceJtagFreqManually</name>\r
+ <state>100000</state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEMKIIAVRJtagIceJtagFreq</name>\r
+ <version>0</version>\r
+ <state>8</state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEMKIIAVRJtagIceJtagDeviceBefore</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEMKIIAVRJtagIceJtagDeviceAfter</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEMKIIAVRJtagIceJtagInstrBitsBefore</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEMKIIAVRJtagIceJtagInstrBitsAfter</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEMKIIAVRJtagIceDaisyChain</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEMKIIAVRJtagDebugTimers</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEMKIIAVRJtagDebugEeprom</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEMKIIAVRJtagDebugReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEMKIIAVRJtagDebugFuses</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEMKIIAVRJtagIcedownloadToData</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEMKIIAVRCommunication</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OJTAGICEMKIIAVRJtagSoftwareBreak</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>SIMAVR</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OSIMAVRDriver</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OSIMAVRExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OSIMAVRExtraOptionsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>THIRDPARTYAVR</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OTHIRDPARTYAVRDriver</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OTHIRDPARTYAVRExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OTHIRDPARTYAVRExtraOptionsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OTHIRDPARTYAVRDriverDll</name>\r
+ <state>Browse to your Third party driver</state>\r
+ </option>\r
+ <option>\r
+ <name>OTHIRDPARTYAVRSuppress</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OTHIRDPARTYAVRVerify</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OTHIRDPARTYAVRLogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OTHIRDPARTYAVRLogFileEditB</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <debuggerPlugins>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Profiling\Profiling.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Trace\Trace.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Orti\Orti.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ </debuggerPlugins>\r
+ </configuration>\r
+</project>\r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+ <fileVersion>1</fileVersion>\r
+ <configuration>\r
+ <name>Debug</name>\r
+ <toolchain>\r
+ <name>AVR</name>\r
+ </toolchain>\r
+ <debug>1</debug>\r
+ <settings>\r
+ <name>General</name>\r
+ <archiveVersion>3</archiveVersion>\r
+ <data>\r
+ <version>6</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>GGEnhancedCore</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>Variant Memory</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>ExePath</name>\r
+ <state>Output\Exe</state>\r
+ </option>\r
+ <option>\r
+ <name>ObjPath</name>\r
+ <state>Output\Obj</state>\r
+ </option>\r
+ <option>\r
+ <name>ListPath</name>\r
+ <state>Output\List</state>\r
+ </option>\r
+ <option>\r
+ <name>GGEnableConfig</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GG64KFlash</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GG64BitDoubles</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GGFPSLICCOnfig</name>\r
+ <version>0</version>\r
+ <state>3</state>\r
+ </option>\r
+ <option>\r
+ <name>LCEnableBitDefs</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LCHeapSize</name>\r
+ <state>0x10</state>\r
+ </option>\r
+ <option>\r
+ <name>SCCStackSize</name>\r
+ <state>0x55</state>\r
+ </option>\r
+ <option>\r
+ <name>SCExtCStack</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>SCRStackSize</name>\r
+ <state>12</state>\r
+ </option>\r
+ <option>\r
+ <name>SCExtRStack</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>SCEnableBus</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>SCAddWaitstate</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>SCRamBase</name>\r
+ <state>0x0</state>\r
+ </option>\r
+ <option>\r
+ <name>SCRamSize</name>\r
+ <state>0x0</state>\r
+ </option>\r
+ <option>\r
+ <name>SCRomBase</name>\r
+ <state>0x0</state>\r
+ </option>\r
+ <option>\r
+ <name>SCRomSize</name>\r
+ <state>0x0</state>\r
+ </option>\r
+ <option>\r
+ <name>SCNVBase</name>\r
+ <state>0x0</state>\r
+ </option>\r
+ <option>\r
+ <name>SCNVSize</name>\r
+ <state>0x0</state>\r
+ </option>\r
+ <option>\r
+ <name>SCInitWithReti</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GOutputBinary</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GGEepromUtil</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GGEepromUtilSize</name>\r
+ <state>1024</state>\r
+ </option>\r
+ <option>\r
+ <name>New Variant Processor</name>\r
+ <version>13</version>\r
+ <state>41</state>\r
+ </option>\r
+ <option>\r
+ <name>GRuntimeLibSelect</name>\r
+ <version>0</version>\r
+ <state>4</state>\r
+ </option>\r
+ <option>\r
+ <name>RTDescription</name>\r
+ <state>Use the legacy C runtime library.</state>\r
+ </option>\r
+ <option>\r
+ <name>RTConfigPath</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>RTLibraryPath</name>\r
+ <state>$TOOLKIT_DIR$\LIB\CLIB\cl3s-ec-sf.r90</state>\r
+ </option>\r
+ <option>\r
+ <name>Input variant</name>\r
+ <version>0</version>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>Input description</name>\r
+ <state>No float.</state>\r
+ </option>\r
+ <option>\r
+ <name>Output variant</name>\r
+ <version>0</version>\r
+ <state>3</state>\r
+ </option>\r
+ <option>\r
+ <name>Output description</name>\r
+ <state>No float, no field width, no precision.</state>\r
+ </option>\r
+ <option>\r
+ <name>GRuntimeLibSelectSlave</name>\r
+ <version>0</version>\r
+ <state>4</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraRules</name>\r
+ <version>0</version>\r
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralEnableMisra</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraVerbose</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LCTinyHeapSize</name>\r
+ <state>0x10</state>\r
+ </option>\r
+ <option>\r
+ <name>LCNearHeapSize</name>\r
+ <state>0x20</state>\r
+ </option>\r
+ <option>\r
+ <name>LCFarHeapSize</name>\r
+ <state>0x1000</state>\r
+ </option>\r
+ <option>\r
+ <name>LCHugeHeapSize</name>\r
+ <state>0x1000</state>\r
+ </option>\r
+ <option>\r
+ <name>LCsHeapConfigText</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ICCAVR</name>\r
+ <archiveVersion>3</archiveVersion>\r
+ <data>\r
+ <version>12</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CCVariantProcessor</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCEnhancedCore</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCVariantMemory</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCObjPrefix</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDefines</name>\r
+ <state>IAR_MEGA_AVR</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocComments</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCFile</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCMnemonics</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCMessages</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListAssFile</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListAssSource</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCEnableRemarks</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagSuppress</name>\r
+ <state>PE815, PE191, TA006, PA082</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagRemark</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagWarning</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagError</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCWarnAsError</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCConstInRAM</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCInitInFlash</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCForceVariables</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOldCallConv</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLockRegs</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptSizeSpeed</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptimization</name>\r
+ <version>1</version>\r
+ <state>4</state>\r
+ </option>\r
+ <option>\r
+ <name>CCAllowList</name>\r
+ <version>3</version>\r
+ <state>111111</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCrossCallPassesList</name>\r
+ <version>8</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCObjUseModuleName</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCObjModuleName</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCDebugInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCNoErrorMsg</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CC64BitDoubles</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CC64KFlash</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCEnableExtBus</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCEnableBitDefs</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptForceCrossCall</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCharIs</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCExt</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IExtraOptions</name>\r
+ <state>--lock_regs 1</state>\r
+ </option>\r
+ <option>\r
+ <name>IExtraOptionsCheck</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMultibyteSupport</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRequirePrototypes</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCompilerRuntimeInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>newCCIncludePaths</name>\r
+ <state>$PROJ_DIR$\..\..\Source\include</state>\r
+ <state>$PROJ_DIR$\..\Common\include</state>\r
+ <state>$PROJ_DIR$</state>\r
+ </option>\r
+ <option>\r
+ <name>CCStdIncCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCStdIncludePaths</name>\r
+ <state>$TOOLKIT_DIR$\INC\</state>\r
+ <state>$TOOLKIT_DIR$\INC\CLIB\</state>\r
+ </option>\r
+ <option>\r
+ <name>CCEepromSize</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLockRegsSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptSizeSpeedSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptimizationSlave</name>\r
+ <version>1</version>\r
+ <state>4</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOutputFile</name>\r
+ <state>$FILE_BNAME$.r90</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLangSelect</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CompilerMisraRules</name>\r
+ <version>0</version>\r
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>CompilerMisraOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLibConfigHeader</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>PreInclude</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCOverrideModuleTypeDefault</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRadioModuleType</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRadioModuleTypeSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>AAVR</name>\r
+ <archiveVersion>3</archiveVersion>\r
+ <data>\r
+ <version>9</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>IProcessor</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AObjPrefix</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>ACaseSensitivity</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnWhat</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnOne</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnRange1</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnRange2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CDebug</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>ADefines</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>MacroChars</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>UndefAsm</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>UndefFile</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>UndefLine</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>UndefTime</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>UndefDate</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>UndefTid</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AList</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AListHeader</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AListing</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>Includes</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacDefs</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacExps</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>MacExec</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OnlyAssed</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MultiLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>PageLengthCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>PageLength</name>\r
+ <state>80</state>\r
+ </option>\r
+ <option>\r
+ <name>TabSpacing</name>\r
+ <state>8</state>\r
+ </option>\r
+ <option>\r
+ <name>AXRef</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AXRefDefines</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AXRefInternal</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AXRefDual</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OAEnhancedCore</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AExtraOptionsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AMaxErrOn</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AMaxErrNum</name>\r
+ <state>100</state>\r
+ </option>\r
+ <option>\r
+ <name>ANewIncludes</name>\r
+ <state>$TOOLKIT_DIR$\INC\</state>\r
+ </option>\r
+ <option>\r
+ <name>AsmMultiByteSupport</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AavrVariantMemory</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AsmHasElpm</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AsmOutputFile</name>\r
+ <state>$FILE_BNAME$.r90</state>\r
+ </option>\r
+ <option>\r
+ <name>AOverrideModuleTypeDefault</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ARadioModuleType</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ARadioModuleTypeSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>CUSTOM</name>\r
+ <archiveVersion>3</archiveVersion>\r
+ <data>\r
+ <extensions></extensions>\r
+ <cmdline></cmdline>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>BICOMP</name>\r
+ <archiveVersion>0</archiveVersion>\r
+ <data/>\r
+ </settings>\r
+ <settings>\r
+ <name>BUILDACTION</name>\r
+ <archiveVersion>1</archiveVersion>\r
+ <data>\r
+ <prebuild></prebuild>\r
+ <postbuild></postbuild>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>XLINK</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>12</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>XOutOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OutputFile</name>\r
+ <state>rtosdemo.d90</state>\r
+ </option>\r
+ <option>\r
+ <name>OutputFormat</name>\r
+ <version>10</version>\r
+ <state>23</state>\r
+ </option>\r
+ <option>\r
+ <name>FormatVariant</name>\r
+ <version>6</version>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>SecondaryOutputFile</name>\r
+ <state>(None for the selected format)</state>\r
+ </option>\r
+ <option>\r
+ <name>XDefines</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>AlwaysOutput</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OverlapWarnings</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>NoGlobalCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>XList</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>SegmentMap</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>ListSymbols</name>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>PageLengthCheck</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>PageLength</name>\r
+ <state>80</state>\r
+ </option>\r
+ <option>\r
+ <name>XIncludes</name>\r
+ <state>$TOOLKIT_DIR$\LIB\</state>\r
+ </option>\r
+ <option>\r
+ <name>ModuleStatus</name>\r
+ <state>0</state>\r
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+ <option>\r
+ <name>XclOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>XclFile</name>\r
+ <state>$TOOLKIT_DIR$\src\template\cfgm323.xcl</state>\r
+ </option>\r
+ <option>\r
+ <name>XclFileSlave</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>DoFill</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>FillerByte</name>\r
+ <state>0xFF</state>\r
+ </option>\r
+ <option>\r
+ <name>DoCrc</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcSize</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcAlgo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcPoly</name>\r
+ <state>0x11021</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcCompl</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RangeCheckAlternatives</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>SuppressAllWarn</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>SuppressDiags</name>\r
+ <state>w6</state>\r
+ </option>\r
+ <option>\r
+ <name>TreatAsWarn</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>TreatAsErr</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>ModuleLocalSym</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
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+ <option>\r
+ <name>CrcBitOrder</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
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+ <option>\r
+ <name>OXSysConfig</name>\r
+ <state>1</state>\r
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+ <option>\r
+ <name>XExtraOptionsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>XExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IncludeSuppressed</name>\r
+ <state>1</state>\r
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+ <option>\r
+ <name>ModuleSummary</name>\r
+ <state>1</state>\r
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+ <option>\r
+ <name>xcProgramEntryLabel</name>\r
+ <state>__program_start</state>\r
+ </option>\r
+ <option>\r
+ <name>DebugInformation</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RuntimeControl</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IoEmulation</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AllowExtraOutput</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GenerateExtraOutput</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>XExtraOutOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ExtraOutputFile</name>\r
+ <state>rtosdemo.a90</state>\r
+ </option>\r
+ <option>\r
+ <name>ExtraOutputFormat</name>\r
+ <version>10</version>\r
+ <state>25</state>\r
+ </option>\r
+ <option>\r
+ <name>ExtraFormatVariant</name>\r
+ <version>6</version>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>xcOverrideProgramEntryLabel</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>xcProgramEntryLabelSelect</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ListOutputFormat</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>BufferedTermOutput</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>XcRTLibraryFile</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OXLibIOConfig</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>XLinkMisraHandler</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OverlaySystemMap</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RawBinaryFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>RawBinarySymbol</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>RawBinarySegment</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>RawBinaryAlign</name>\r
+ <state></state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>XAR</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>XAROutOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>XARInputs</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OutputFile</name>\r
+ <state></state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>BILINK</name>\r
+ <archiveVersion>0</archiveVersion>\r
+ <data/>\r
+ </settings>\r
+ </configuration>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\comtest.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\flash.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\MemMang\heap_1.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\integer.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\list.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\main.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\ParTest\ParTest.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\PollQ.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\IAR\ATMega323\port.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\IAR\ATMega323\portmacro.s90</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\queue.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\serial\serial.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\tasks.c</name>\r
+ </file>\r
+</project>\r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<workspace>\r
+ <project>\r
+ <path>$WS_DIR$\rtosdemo.ewp</path>\r
+ </project>\r
+ <batchBuild/>\r
+</workspace>\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+\r
+/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR IAR AVR PORT. */\r
+\r
+\r
+#include <stdlib.h>\r
+#include "FreeRTOS.h"\r
+#include "queue.h"\r
+#include "task.h"\r
+#include "serial.h"\r
+\r
+#define serBAUD_DIV_CONSTANT ( ( unsigned portLONG ) 16 )\r
+\r
+/* Constants for writing to UCSRB. */\r
+#define serRX_INT_ENABLE ( ( unsigned portCHAR ) 0x80 )\r
+#define serRX_ENABLE ( ( unsigned portCHAR ) 0x10 )\r
+#define serTX_ENABLE ( ( unsigned portCHAR ) 0x08 )\r
+#define serTX_INT_ENABLE ( ( unsigned portCHAR ) 0x20 )\r
+\r
+/* Constants for writing to UCSRC. */\r
+#define serUCSRC_SELECT ( ( unsigned portCHAR ) 0x80 )\r
+#define serEIGHT_DATA_BITS ( ( unsigned portCHAR ) 0x06 )\r
+\r
+static xQueueHandle xRxedChars; \r
+static xQueueHandle xCharsForTx; \r
+\r
+#define vInterruptOn() \\r
+{ \\r
+ unsigned portCHAR ucByte; \\r
+ \\r
+ ucByte = UCSRB; \\r
+ ucByte |= serTX_INT_ENABLE; \\r
+ outb( UCSRB, ucByte ); \\r
+} \r
+/*-----------------------------------------------------------*/\r
+\r
+#define vInterruptOff() \\r
+{ \\r
+ unsigned portCHAR ucByte; \\r
+ \\r
+ ucByte = UCSRB; \\r
+ ucByte &= ~serTX_INT_ENABLE; \\r
+ outb( UCSRB, ucByte ); \\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )\r
+{\r
+unsigned portLONG ulBaudRateCounter;\r
+unsigned portCHAR ucByte;\r
+\r
+ portENTER_CRITICAL();\r
+ {\r
+ /* Create the queues used by the com test task. */\r
+ xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );\r
+ xCharsForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );\r
+\r
+ /* Calculate the baud rate register value from the equation in the\r
+ data sheet. */\r
+ ulBaudRateCounter = ( configCPU_CLOCK_HZ / ( serBAUD_DIV_CONSTANT * ulWantedBaud ) ) - ( unsigned portLONG ) 1;\r
+\r
+ /* Set the baud rate. */ \r
+ ucByte = ( unsigned portCHAR ) ( ulBaudRateCounter & ( unsigned portLONG ) 0xff ); \r
+ outb( UBRRL, ucByte );\r
+\r
+ ulBaudRateCounter >>= ( unsigned portLONG ) 8;\r
+ ucByte = ( unsigned portCHAR ) ( ulBaudRateCounter & ( unsigned portLONG ) 0xff ); \r
+ outb( UBRRH, ucByte );\r
+\r
+ /* Enable the Rx interrupt. The Tx interrupt will get enabled\r
+ later. Also enable the Rx and Tx. */\r
+ outb( UCSRB, serRX_INT_ENABLE | serRX_ENABLE | serTX_ENABLE );\r
+\r
+ /* Set the data bits to 8. */\r
+ outb( UCSRC, serUCSRC_SELECT | serEIGHT_DATA_BITS );\r
+ }\r
+ portEXIT_CRITICAL();\r
+ \r
+ /* Unlike other ports, this serial code does not allow for more than one\r
+ com port. We therefore don't return a pointer to a port structure and can\r
+ instead just return NULL. */\r
+ return NULL;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )\r
+{\r
+ /* Get the next character from the buffer. Return false if no characters\r
+ are available, or arrive before xBlockTime expires. */\r
+ if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )\r
+ {\r
+ return pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ return pdFALSE;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )\r
+{\r
+ /* Return false if after the block time there is no room on the Tx queue. */\r
+ if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )\r
+ {\r
+ return pdFAIL;\r
+ }\r
+\r
+ vInterruptOn();\r
+\r
+ return pdPASS;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSerialClose( xComPortHandle xPort )\r
+{\r
+unsigned portCHAR ucByte;\r
+\r
+ /* Turn off the interrupts. We may also want to delete the queues and/or\r
+ re-install the original ISR. */\r
+\r
+ portENTER_CRITICAL();\r
+ {\r
+ vInterruptOff();\r
+ ucByte = UCSRB;\r
+ ucByte &= ~serRX_INT_ENABLE;\r
+ outb( UCSRB, ucByte );\r
+ }\r
+ portEXIT_CRITICAL();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+__interrupt void SIG_UART_RECV( void )\r
+{\r
+signed portCHAR cChar;\r
+\r
+ /* Get the character and post it on the queue of Rxed characters.\r
+ If the post causes a task to wake force a context switch as the woken task\r
+ may have a higher priority than the task we have interrupted. */\r
+ cChar = UDR;\r
+\r
+ if( xQueueSendFromISR( xRxedChars, &cChar, pdFALSE ) )\r
+ {\r
+ taskYIELD();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+__interrupt void SIG_UART_DATA( void )\r
+{\r
+signed portCHAR cChar, cTaskWoken;\r
+\r
+ if( xQueueReceiveFromISR( xCharsForTx, &cChar, &cTaskWoken ) == pdTRUE )\r
+ {\r
+ /* Send the next character queued for Tx. */\r
+ outb( UDR, cChar );\r
+ }\r
+ else\r
+ {\r
+ /* Queue empty, nothing to send. */\r
+ vInterruptOff();\r
+ }\r
+}\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<Project/>\r
+\r
+\r
--- /dev/null
+[DisAssemblyWindow]\r
+NumStates=_ 1\r
+State 1=_ 1\r
+[Watch]\r
+Watch 1=_ 1 "usCurrentNumberOfTasks"\r
+Watch 2=\r
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+LogFile=_ ""\r
+[Breakpoints]\r
+Count=0\r
--- /dev/null
+[struct types]\r
+Count=_ 0\r
+[watch formats]\r
+Count=_ 0\r
--- /dev/null
+[WorkspaceWindow]\r
+ExpandedNodes=_ 1 "rtosdemo" 1 "rtosdemo/Debug"\r
+SelectedTab=_ 0\r
+[Desktop-Workspace]\r
+Wnd0=_ "TextEditor" "open" 44 0 1 -1 -1 -1 -1 378 14 1227 671 "E:\Dev\FreeRTOS\Source\tasks.c" 1 1 0 1170 37742 37742\r
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+Maximized=_ 0\r
+Count=_ 4\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<Workspace>\r
+ <ConfigDictionary>\r
+ \r
+ <CurrentConfigs><Project>rtosdemo/Debug</Project></CurrentConfigs></ConfigDictionary>\r
+ <Desktop>\r
+ <Static>\r
+ <Workspace>\r
+ <ColumnWidths>\r
+ \r
+ \r
+ \r
+ \r
+ <Column0>109</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>\r
+ </Workspace>\r
+ <Build><ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1153</ColumnWidth1><ColumnWidth2>307</ColumnWidth2><ColumnWidth3>76</ColumnWidth3></Build></Static>\r
+ <Windows>\r
+ \r
+ <Wnd0>\r
+ <Tabs>\r
+ <Tab>\r
+ <Identity>TabID-12388-19520</Identity>\r
+ <TabName>Workspace</TabName>\r
+ <Factory>Workspace</Factory>\r
+ <Session>\r
+ \r
+ <NodeDict><ExpandedNode>rtosdemo</ExpandedNode><ExpandedNode>rtosdemo/portheap.c</ExpandedNode></NodeDict></Session>\r
+ </Tab>\r
+ </Tabs>\r
+ \r
+ <SelectedTab>0</SelectedTab></Wnd0><Wnd1><Tabs><Tab><Identity>TabID-19172-8303</Identity><TabName>Build</TabName><Factory>Build</Factory><Session/></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd1></Windows>\r
+ <Editor>\r
+ \r
+ \r
+ \r
+ \r
+ <Pane/><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>\r
+ <Positions>\r
+ \r
+ \r
+ \r
+ \r
+ \r
+ <Top><Row0><Sizes><Toolbar-0084f828><key>iaridepm1</key></Toolbar-0084f828></Sizes></Row0></Top><Left><Row0><Sizes><Wnd0><Rect><Top>-2</Top><Left>-2</Left><Bottom>718</Bottom><Right>183</Right><x>-2</x><y>-2</y><xscreen>185</xscreen><yscreen>185</yscreen><sizeHorzCX>115625</sizeHorzCX><sizeHorzCY>165326</sizeHorzCY><sizeVertCX>115625</sizeVertCX><sizeVertCY>643431</sizeVertCY></Rect></Wnd0></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd1><Rect><Top>-2</Top><Left>-2</Left><Bottom>354</Bottom><Right>1602</Right><x>-2</x><y>-2</y><xscreen>1604</xscreen><yscreen>356</yscreen><sizeHorzCX>1002500</sizeHorzCX><sizeHorzCY>318141</sizeHorzCY><sizeVertCX>116250</sizeVertCX><sizeVertCY>166219</sizeVertCY></Rect></Wnd1></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>\r
+ </Desktop>\r
+</Workspace>\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+#include <avr/io.h>\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. \r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 8000000 )\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 4 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 85 )\r
+#define configTOTAL_HEAP_SIZE ( (size_t ) ( 1500 ) )\r
+#define configMAX_TASK_NAME_LEN ( 8 )\r
+#define configUSE_TRACE_FACILITY 0\r
+#define configUSE_16_BIT_TICKS 1\r
+#define configIDLE_SHOULD_YIELD 1\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet 0\r
+#define INCLUDE_uxTaskPriorityGet 0\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 0\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* \r
+Changes from V2.0.0\r
+\r
+ + Use scheduler suspends in place of critical sections.\r
+\r
+Changes from V2.6.0\r
+\r
+ + Replaced the inb() and outb() functions with direct memory\r
+ access. This allows the port to be built with the 20050414 build of\r
+ WinAVR.\r
+*/\r
+\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "partest.h"\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple parallel port IO routines.\r
+ *-----------------------------------------------------------*/\r
+\r
+#define partstALL_BITS_OUTPUT ( ( unsigned portCHAR ) 0xff )\r
+#define partstALL_OUTPUTS_OFF ( ( unsigned portCHAR ) 0xff )\r
+#define partstMAX_OUTPUT_LED ( ( unsigned portCHAR ) 7 )\r
+\r
+static volatile unsigned portCHAR ucCurrentOutputValue = partstALL_OUTPUTS_OFF; /*lint !e956 File scope parameters okay here. */\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestInitialise( void )\r
+{\r
+ ucCurrentOutputValue = partstALL_OUTPUTS_OFF;\r
+\r
+ /* Set port B direction to outputs. Start with all output off. */\r
+ DDRB = partstALL_BITS_OUTPUT;\r
+ PORTB = ucCurrentOutputValue;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )\r
+{\r
+unsigned portCHAR ucBit = ( unsigned portCHAR ) 1;\r
+\r
+ if( uxLED <= partstMAX_OUTPUT_LED )\r
+ {\r
+ ucBit <<= uxLED;\r
+ } \r
+\r
+ vTaskSuspendAll();\r
+ {\r
+ if( xValue == pdTRUE )\r
+ {\r
+ ucBit ^= ( unsigned portCHAR ) 0xff;\r
+ ucCurrentOutputValue &= ucBit;\r
+ }\r
+ else\r
+ {\r
+ ucCurrentOutputValue |= ucBit;\r
+ }\r
+\r
+ PORTB = ucCurrentOutputValue;\r
+ }\r
+ xTaskResumeAll();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+unsigned portCHAR ucBit;\r
+\r
+ if( uxLED <= partstMAX_OUTPUT_LED )\r
+ {\r
+ ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED;\r
+\r
+ vTaskSuspendAll();\r
+ {\r
+ if( ucCurrentOutputValue & ucBit )\r
+ {\r
+ ucCurrentOutputValue &= ~ucBit;\r
+ }\r
+ else\r
+ {\r
+ ucCurrentOutputValue |= ucBit;\r
+ }\r
+\r
+ PORTB = ucCurrentOutputValue;\r
+ }\r
+ xTaskResumeAll(); \r
+ }\r
+}\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+ * Creates all the demo application tasks, then starts the scheduler. The WEB\r
+ * documentation provides more details of the demo application tasks.\r
+ * \r
+ * Main. c also creates a task called "Check". This only executes every three \r
+ * seconds but has the highest priority so is guaranteed to get processor time. \r
+ * Its main function is to check that all the other tasks are still operational. \r
+ * Each task that does not flash an LED maintains a unique count that is \r
+ * incremented each time the task successfully completes its function. Should \r
+ * any error occur within such a task the count is permanently halted. The \r
+ * check task inspects the count of each task to ensure it has changed since\r
+ * the last time the check task executed. If all the count variables have \r
+ * changed all the tasks are still executing error free, and the check task\r
+ * toggles an LED. Should any task contain an error at any time the LED toggle\r
+ * will stop.\r
+ *\r
+ * The LED flash and communications test tasks do not maintain a count.\r
+ */\r
+\r
+/*\r
+Changes from V1.2.0\r
+ \r
+ + Changed the baud rate for the serial test from 19200 to 57600.\r
+\r
+Changes from V1.2.3\r
+\r
+ + The integer and comtest tasks are now used when the cooperative scheduler \r
+ is being used. Previously they were only used with the preemptive\r
+ scheduler.\r
+\r
+Changes from V1.2.5\r
+\r
+ + Set the baud rate to 38400. This has a smaller error percentage with an\r
+ 8MHz clock (according to the manual).\r
+\r
+Changes from V2.0.0\r
+\r
+ + Delay periods are now specified using variables and constants of\r
+ portTickType rather than unsigned portLONG.\r
+\r
+Changes from V2.6.1\r
+\r
+ + The IAR and WinAVR AVR ports are now maintained separately.\r
+*/\r
+\r
+#include <stdlib.h>\r
+#include <string.h>\r
+\r
+#ifdef GCC_MEGA_AVR\r
+ /* EEPROM routines used only with the WinAVR compiler. */\r
+ #include <avr/eeprom.h> \r
+#endif\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo file headers. */\r
+#include "PollQ.h"\r
+#include "integer.h"\r
+#include "serial.h"\r
+#include "comtest.h"\r
+#include "flash.h"\r
+#include "print.h"\r
+#include "partest.h"\r
+\r
+/* Priority definitions for most of the tasks in the demo application. Some\r
+tasks just use the idle priority. */\r
+#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+\r
+/* Baud rate used by the serial port tasks. */\r
+#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 38400 )\r
+\r
+/* LED used by the serial port tasks. This is toggled on each character Tx,\r
+and mainCOM_TEST_LED + 1 is toggles on each character Rx. */\r
+#define mainCOM_TEST_LED ( 4 )\r
+\r
+/* LED that is toggled by the check task. The check task periodically checks\r
+that all the other tasks are operating without error. If no errors are found\r
+the LED is toggled. If an error is found at any time the LED is never toggles\r
+again. */\r
+#define mainCHECK_TASK_LED ( 7 )\r
+\r
+/* The period between executions of the check task. */\r
+#define mainCHECK_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS )\r
+\r
+/* An address in the EEPROM used to count resets. This is used to check that\r
+the demo application is not unexpectedly resetting. */\r
+#define mainRESET_COUNT_ADDRESS ( ( void * ) 0x50 )\r
+\r
+/*\r
+ * The task function for the "Check" task.\r
+ */\r
+static void vErrorChecks( void *pvParameters );\r
+\r
+/*\r
+ * Checks the unique counts of other tasks to ensure they are still operational.\r
+ * Flashes an LED if everything is okay. \r
+ */\r
+static void prvCheckOtherTasksAreStillRunning( void );\r
+\r
+/*\r
+ * Called on boot to increment a count stored in the EEPROM. This is used to \r
+ * ensure the CPU does not reset unexpectedly.\r
+ */\r
+static void prvIncrementResetCount( void );\r
+\r
+portSHORT main( void )\r
+{\r
+ prvIncrementResetCount();\r
+\r
+ /* Setup the LED's for output. */\r
+ vParTestInitialise();\r
+\r
+ vStartIntegerMathTasks( tskIDLE_PRIORITY );\r
+ vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED );\r
+ vStartLEDFlashTasks( mainLED_TASK_PRIORITY );\r
+ vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
+\r
+ xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
+\r
+ /* In this port, to use preemptive scheduler define configUSE_PREEMPTION \r
+ as 1 in portmacro.h. To use the cooperative scheduler define \r
+ configUSE_PREEMPTION as 0. */\r
+ vTaskStartScheduler();\r
+\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vErrorChecks( void *pvParameters )\r
+{\r
+static volatile unsigned portLONG ulDummyVariable = 3UL;\r
+\r
+ /* The parameters are not used. */\r
+ ( void ) pvParameters;\r
+\r
+ /* Cycle for ever, delaying then checking all the other tasks are still\r
+ operating without error. */\r
+ for( ;; )\r
+ {\r
+ vTaskDelay( mainCHECK_PERIOD );\r
+\r
+ /* Perform a bit of 32bit maths to ensure the registers used by the \r
+ integer tasks get some exercise. The result here is not important - \r
+ see the demo application documentation for more info. */\r
+ ulDummyVariable *= 3;\r
+ \r
+ prvCheckOtherTasksAreStillRunning();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCheckOtherTasksAreStillRunning( void )\r
+{\r
+static portBASE_TYPE xErrorHasOccurred = pdFALSE;\r
+\r
+ if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ xErrorHasOccurred = pdTRUE;\r
+ }\r
+\r
+ if( xAreComTestTasksStillRunning() != pdTRUE )\r
+ {\r
+ xErrorHasOccurred = pdTRUE;\r
+ }\r
+\r
+ if( xArePollingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ xErrorHasOccurred = pdTRUE;\r
+ }\r
+\r
+ if( xErrorHasOccurred == pdFALSE )\r
+ {\r
+ /* Toggle the LED if everything is okay so we know if an error occurs even if not\r
+ using console IO. */\r
+ vParTestToggleLED( mainCHECK_TASK_LED );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvIncrementResetCount( void )\r
+{\r
+unsigned portCHAR ucCount;\r
+\r
+ eeprom_read_block( &ucCount, mainRESET_COUNT_ADDRESS, sizeof( ucCount ) );\r
+ ucCount++;\r
+ eeprom_write_byte( mainRESET_COUNT_ADDRESS, ucCount );\r
+}\r
+\r
--- /dev/null
+# WinAVR Sample makefile written by Eric B. Weddington, Jörg Wunsch, et al.\r
+# Released to the Public Domain\r
+# Please read the make user manual!\r
+#\r
+# Additional material for this makefile was submitted by:\r
+# Tim Henigan\r
+# Peter Fleury\r
+# Reiner Patommel\r
+# Sander Pool\r
+# Frederik Rouleau\r
+# Markus Pfaff\r
+#\r
+# On command line:\r
+#\r
+# make all = Make software.\r
+#\r
+# make clean = Clean out built project files.\r
+#\r
+# make coff = Convert ELF to AVR COFF (for use with AVR Studio 3.x or VMLAB).\r
+#\r
+# make extcoff = Convert ELF to AVR Extended COFF (for use with AVR Studio\r
+# 4.07 or greater).\r
+#\r
+# make program = Download the hex file to the device, using avrdude. Please\r
+# customize the avrdude settings below first!\r
+#\r
+# make filename.s = Just compile filename.c into the assembler code only\r
+#\r
+# To rebuild project do "make clean" then "make all".\r
+#\r
+\r
+\r
+# MCU name\r
+MCU = atmega323\r
+\r
+# Output format. (can be srec, ihex, binary)\r
+FORMAT = ihex\r
+\r
+# Target file name (without extension).\r
+TARGET = rtosdemo\r
+\r
+# Optimization level, can be [0, 1, 2, 3, s]. 0 turns off optimization.\r
+# (Note: 3 is not always the best optimization level. See avr-libc FAQ.)\r
+OPT = s\r
+\r
+\r
+# List C source files here. (C dependencies are automatically generated.)\r
+DEMO_DIR = ../Common/Minimal\r
+SOURCE_DIR = ../../Source\r
+PORT_DIR = ../../Source/portable/GCC/ATMega323\r
+\r
+SRC = \\r
+main.c \\r
+ParTest/ParTest.c \\r
+serial/serial.c \\r
+$(SOURCE_DIR)/tasks.c \\r
+$(SOURCE_DIR)/queue.c \\r
+$(SOURCE_DIR)/list.c \\r
+$(SOURCE_DIR)/portable/MemMang/heap_1.c \\r
+$(PORT_DIR)/port.c \\r
+$(DEMO_DIR)/flash.c \\r
+$(DEMO_DIR)/integer.c \\r
+$(DEMO_DIR)/PollQ.c \\r
+$(DEMO_DIR)/comtest.c\r
+\r
+\r
+# If there is more than one source file, append them above, or modify and\r
+# uncomment the following:\r
+#SRC += foo.c bar.c\r
+\r
+# You can also wrap lines by appending a backslash to the end of the line:\r
+#SRC += baz.c \\r
+#xyzzy.c\r
+\r
+\r
+\r
+# List Assembler source files here.\r
+# Make them always end in a capital .S. Files ending in a lowercase .s\r
+# will not be considered source files but generated files (assembler\r
+# output from the compiler), and will be deleted upon "make clean"!\r
+# Even though the DOS/Win* filesystem matches both .s and .S the same,\r
+# it will preserve the spelling of the filenames, and gcc itself does\r
+# care about how the name is spelled on its command-line.\r
+ASRC = \r
+\r
+\r
+# List any extra directories to look for include files here.\r
+# Each directory must be seperated by a space.\r
+EXTRAINCDIRS = \r
+\r
+\r
+# Optional compiler flags.\r
+# -g: generate debugging information (for GDB, or for COFF conversion)\r
+# -O*: optimization level\r
+# -f...: tuning, see gcc manual and avr-libc documentation\r
+# -Wall...: warning level\r
+# -Wa,...: tell GCC to pass this to the assembler.\r
+# -ahlms: create assembler listing\r
+\r
+DEBUG_LEVEL=-g\r
+WARNINGS=-Wall -Wextra -Wshadow -Wpointer-arith -Wbad-function-cast -Wcast-align -Wsign-compare \\r
+ -Waggregate-return -Wstrict-prototypes -Wmissing-prototypes -Wmissing-declarations -Wunused\r
+\r
+CFLAGS = -D GCC_MEGA_AVR -I. -I../../Source/include -I../Common/include \\r
+$(DEBUG_LEVEL) -O$(OPT) \\r
+-fsigned-char -funsigned-bitfields -fpack-struct -fshort-enums \\r
+$(WARNINGS) \\r
+-Wa,-adhlns=$(<:.c=.lst) \\r
+$(patsubst %,-I%,$(EXTRAINCDIRS))\r
+\r
+\r
+# Set a "language standard" compiler flag.\r
+# Unremark just one line below to set the language standard to use.\r
+# gnu99 = C99 + GNU extensions. See GCC manual for more information.\r
+#CFLAGS += -std=c89\r
+#CFLAGS += -std=gnu89\r
+#CFLAGS += -std=c99\r
+CFLAGS += -std=gnu99\r
+\r
+\r
+\r
+# Optional assembler flags.\r
+# -Wa,...: tell GCC to pass this to the assembler.\r
+# -ahlms: create listing\r
+# -gstabs: have the assembler create line number information; note that\r
+# for use in COFF files, additional information about filenames\r
+# and function names needs to be present in the assembler source\r
+# files -- see avr-libc docs [FIXME: not yet described there]\r
+ASFLAGS = -Wa,-adhlns=$(<:.S=.lst),-gstabs \r
+\r
+\r
+\r
+# Optional linker flags.\r
+# -Wl,...: tell GCC to pass this to linker.\r
+# -Map: create map file\r
+# --cref: add cross reference to map file\r
+LDFLAGS = -Wl,-Map=$(TARGET).map,--cref\r
+\r
+\r
+\r
+# Additional libraries\r
+\r
+# Minimalistic printf version\r
+#LDFLAGS += -Wl,-u,vfprintf -lprintf_min\r
+\r
+# Floating point printf version (requires -lm below)\r
+#LDFLAGS += -Wl,-u,vfprintf -lprintf_flt\r
+\r
+# -lm = math library\r
+LDFLAGS += -lm\r
+\r
+\r
+\r
+\r
+# Programming support using avrdude. Settings and variables.\r
+\r
+# Programming hardware: alf avr910 avrisp bascom bsd \r
+# dt006 pavr picoweb pony-stk200 sp12 stk200 stk500\r
+#\r
+# Type: avrdude -c ?\r
+# to get a full listing.\r
+#\r
+AVRDUDE_PROGRAMMER = stk500\r
+\r
+\r
+AVRDUDE_PORT = com1 # programmer connected to serial device\r
+#AVRDUDE_PORT = lpt1 # programmer connected to parallel port\r
+\r
+AVRDUDE_WRITE_FLASH = -U flash:w:$(TARGET).hex\r
+#AVRDUDE_WRITE_EEPROM = -U eeprom:w:$(TARGET).eep\r
+\r
+AVRDUDE_FLAGS = -p $(MCU) -P $(AVRDUDE_PORT) -c $(AVRDUDE_PROGRAMMER)\r
+\r
+# Uncomment the following if you want avrdude's erase cycle counter.\r
+# Note that this counter needs to be initialized first using -Yn,\r
+# see avrdude manual.\r
+#AVRDUDE_ERASE += -y\r
+\r
+# Uncomment the following if you do /not/ wish a verification to be\r
+# performed after programming the device.\r
+#AVRDUDE_FLAGS += -V\r
+\r
+# Increase verbosity level. Please use this when submitting bug\r
+# reports about avrdude. See <http://savannah.nongnu.org/projects/avrdude> \r
+# to submit bug reports.\r
+#AVRDUDE_FLAGS += -v -v\r
+\r
+\r
+\r
+\r
+# ---------------------------------------------------------------------------\r
+\r
+# Define directories, if needed.\r
+DIRAVR = c:/winavr\r
+DIRAVRBIN = $(DIRAVR)/bin\r
+DIRAVRUTILS = $(DIRAVR)/utils/bin\r
+DIRINC = .\r
+DIRLIB = $(DIRAVR)/avr/lib\r
+\r
+\r
+# Define programs and commands.\r
+SHELL = sh\r
+\r
+CC = avr-gcc\r
+\r
+OBJCOPY = avr-objcopy\r
+OBJDUMP = avr-objdump\r
+SIZE = avr-size\r
+\r
+\r
+# Programming support using avrdude.\r
+AVRDUDE = avrdude\r
+\r
+\r
+REMOVE = rm -f\r
+COPY = cp\r
+\r
+HEXSIZE = $(SIZE) --target=$(FORMAT) $(TARGET).hex\r
+ELFSIZE = $(SIZE) -A $(TARGET).elf\r
+\r
+\r
+\r
+# Define Messages\r
+# English\r
+MSG_ERRORS_NONE = Errors: none\r
+MSG_BEGIN = -------- begin --------\r
+MSG_END = -------- end --------\r
+MSG_SIZE_BEFORE = Size before: \r
+MSG_SIZE_AFTER = Size after:\r
+MSG_COFF = Converting to AVR COFF:\r
+MSG_EXTENDED_COFF = Converting to AVR Extended COFF:\r
+MSG_FLASH = Creating load file for Flash:\r
+MSG_EEPROM = Creating load file for EEPROM:\r
+MSG_EXTENDED_LISTING = Creating Extended Listing:\r
+MSG_SYMBOL_TABLE = Creating Symbol Table:\r
+MSG_LINKING = Linking:\r
+MSG_COMPILING = Compiling:\r
+MSG_ASSEMBLING = Assembling:\r
+MSG_CLEANING = Cleaning project:\r
+\r
+\r
+\r
+\r
+# Define all object files.\r
+OBJ = $(SRC:.c=.o) $(ASRC:.S=.o) \r
+\r
+# Define all listing files.\r
+LST = $(ASRC:.S=.lst) $(SRC:.c=.lst)\r
+\r
+# Combine all necessary flags and optional flags.\r
+# Add target processor to flags.\r
+ALL_CFLAGS = -mmcu=$(MCU) -I. $(CFLAGS)\r
+ALL_ASFLAGS = -mmcu=$(MCU) -I. -x assembler-with-cpp $(ASFLAGS)\r
+\r
+\r
+\r
+# Default target.\r
+all: begin gccversion sizebefore $(TARGET).elf $(TARGET).hex $(TARGET).eep \\r
+ $(TARGET).lss $(TARGET).sym sizeafter finished end\r
+\r
+\r
+# Eye candy.\r
+# AVR Studio 3.x does not check make's exit code but relies on\r
+# the following magic strings to be generated by the compile job.\r
+begin:\r
+ @echo\r
+ @echo $(MSG_BEGIN)\r
+\r
+finished:\r
+ @echo $(MSG_ERRORS_NONE)\r
+\r
+end:\r
+ @echo $(MSG_END)\r
+ @echo\r
+\r
+\r
+# Display size of file.\r
+sizebefore:\r
+ @if [ -f $(TARGET).elf ]; then echo; echo $(MSG_SIZE_BEFORE); $(ELFSIZE); echo; fi\r
+\r
+sizeafter:\r
+ @if [ -f $(TARGET).elf ]; then echo; echo $(MSG_SIZE_AFTER); $(ELFSIZE); echo; fi\r
+\r
+\r
+\r
+# Display compiler version information.\r
+gccversion : \r
+ @$(CC) --version\r
+\r
+\r
+\r
+\r
+# Convert ELF to COFF for use in debugging / simulating in\r
+# AVR Studio or VMLAB.\r
+COFFCONVERT=$(OBJCOPY) --debugging \\r
+ --change-section-address .data-0x800000 \\r
+ --change-section-address .bss-0x800000 \\r
+ --change-section-address .noinit-0x800000 \\r
+ --change-section-address .eeprom-0x810000 \r
+\r
+\r
+coff: $(TARGET).elf\r
+ @echo\r
+ @echo $(MSG_COFF) $(TARGET).cof\r
+ $(COFFCONVERT) -O coff-avr $< $(TARGET).cof\r
+\r
+\r
+extcoff: $(TARGET).elf\r
+ @echo\r
+ @echo $(MSG_EXTENDED_COFF) $(TARGET).cof\r
+ $(COFFCONVERT) -O coff-ext-avr $< $(TARGET).cof\r
+\r
+\r
+\r
+\r
+# Program the device. \r
+program: $(TARGET).hex $(TARGET).eep\r
+ $(AVRDUDE) $(AVRDUDE_FLAGS) $(AVRDUDE_WRITE_FLASH) $(AVRDUDE_WRITE_EEPROM)\r
+\r
+\r
+\r
+\r
+# Create final output files (.hex, .eep) from ELF output file.\r
+%.hex: %.elf\r
+ @echo
+ @echo $(MSG_FLASH) $@
+ $(OBJCOPY) -O $(FORMAT) -R .eeprom $< $@\r
+\r
+%.eep: %.elf\r
+ @echo
+ @echo $(MSG_EEPROM) $@
+ -$(OBJCOPY) -j .eeprom --set-section-flags=.eeprom="alloc,load" \\r
+ --change-section-lma .eeprom=0 -O $(FORMAT) $< $@\r
+\r
+# Create extended listing file from ELF output file.\r
+%.lss: %.elf\r
+ @echo
+ @echo $(MSG_EXTENDED_LISTING) $@
+ $(OBJDUMP) -h -S $< > $@\r
+\r
+# Create a symbol table from ELF output file.
+%.sym: %.elf
+ @echo
+ @echo $(MSG_SYMBOL_TABLE) $@
+ avr-nm -n $< > $@\r
+\r
+\r
+\r
+# Link: create ELF output file from object files.\r
+.SECONDARY : $(TARGET).elf\r
+.PRECIOUS : $(OBJ)\r
+%.elf: $(OBJ)\r
+ @echo\r
+ @echo $(MSG_LINKING) $@\r
+ $(CC) $(ALL_CFLAGS) $(OBJ) --output $@ $(LDFLAGS)\r
+\r
+\r
+# Compile: create object files from C source files.\r
+%.o : %.c\r
+ @echo\r
+ @echo $(MSG_COMPILING) $<\r
+ $(CC) -c $(ALL_CFLAGS) $< -o $@\r
+\r
+\r
+# Compile: create assembler files from C source files.\r
+%.s : %.c\r
+ $(CC) -S $(ALL_CFLAGS) $< -o $@\r
+\r
+\r
+# Assemble: create object files from assembler source files.\r
+%.o : %.S\r
+ @echo\r
+ @echo $(MSG_ASSEMBLING) $<\r
+ $(CC) -c $(ALL_ASFLAGS) $< -o $@\r
+\r
+\r
+\r
+\r
+\r
+\r
+# Target: clean project.\r
+clean: begin clean_list finished end\r
+\r
+clean_list :\r
+ @echo
+ @echo $(MSG_CLEANING)
+ $(REMOVE) $(TARGET).hex\r
+ $(REMOVE) $(TARGET).eep\r
+ $(REMOVE) $(TARGET).obj\r
+ $(REMOVE) $(TARGET).cof\r
+ $(REMOVE) $(TARGET).elf\r
+ $(REMOVE) $(TARGET).map\r
+ $(REMOVE) $(TARGET).obj\r
+ $(REMOVE) $(TARGET).a90\r
+ $(REMOVE) $(TARGET).sym\r
+ $(REMOVE) $(TARGET).lnk\r
+ $(REMOVE) $(TARGET).lss\r
+ $(REMOVE) $(OBJ)\r
+ $(REMOVE) $(LST)\r
+ $(REMOVE) $(SRC:.c=.s)\r
+ $(REMOVE) $(SRC:.c=.d)\r
+\r
+\r
+# Automatically generate C source code dependencies. \r
+# (Code originally taken from the GNU make user manual and modified \r
+# (See README.txt Credits).)\r
+#\r
+# Note that this will work with sh (bash) and sed that is shipped with WinAVR\r
+# (see the SHELL variable defined above).\r
+# This may not work with other shells or other seds.\r
+#\r
+%.d: %.c\r
+ set -e; $(CC) -MM $(ALL_CFLAGS) $< \\r
+ | sed 's,\(.*\)\.o[ :]*,\1.o \1.d : ,g' > $@; \\r
+ [ -s $@ ] || rm -f $@\r
+\r
+\r
+# Remove the '-' if you want to see the dependency files generated.\r
+-include $(SRC:.c=.d)\r
+\r
+\r
+\r
+# Listing of phony targets.\r
+.PHONY : all begin finish end sizebefore sizeafter gccversion coff extcoff \\r
+ clean clean_list program\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+Changes from V1.2.3\r
+\r
+ + The function xPortInitMinimal() has been renamed to \r
+ xSerialPortInitMinimal() and the function xPortInit() has been renamed\r
+ to xSerialPortInit().\r
+\r
+Changes from V2.0.0\r
+\r
+ + Delay periods are now specified using variables and constants of\r
+ portTickType rather than unsigned portLONG.\r
+ + xQueueReceiveFromISR() used in place of xQueueReceive() within the ISR.\r
+\r
+Changes from V2.6.0\r
+\r
+ + Replaced the inb() and outb() functions with direct memory\r
+ access. This allows the port to be built with the 20050414 build of\r
+ WinAVR.\r
+*/\r
+\r
+/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER. */\r
+\r
+\r
+#include <stdlib.h>\r
+#include <avr/interrupt.h>\r
+#include "FreeRTOS.h"\r
+#include "queue.h"\r
+#include "task.h"\r
+#include "serial.h"\r
+\r
+#define serBAUD_DIV_CONSTANT ( ( unsigned portLONG ) 16 )\r
+\r
+/* Constants for writing to UCSRB. */\r
+#define serRX_INT_ENABLE ( ( unsigned portCHAR ) 0x80 )\r
+#define serRX_ENABLE ( ( unsigned portCHAR ) 0x10 )\r
+#define serTX_ENABLE ( ( unsigned portCHAR ) 0x08 )\r
+#define serTX_INT_ENABLE ( ( unsigned portCHAR ) 0x20 )\r
+\r
+/* Constants for writing to UCSRC. */\r
+#define serUCSRC_SELECT ( ( unsigned portCHAR ) 0x80 )\r
+#define serEIGHT_DATA_BITS ( ( unsigned portCHAR ) 0x06 )\r
+\r
+static xQueueHandle xRxedChars; \r
+static xQueueHandle xCharsForTx; \r
+\r
+#define vInterruptOn() \\r
+{ \\r
+ unsigned portCHAR ucByte; \\r
+ \\r
+ ucByte = UCSRB; \\r
+ ucByte |= serTX_INT_ENABLE; \\r
+ UCSRB = ucByte; \\r
+} \r
+/*-----------------------------------------------------------*/\r
+\r
+#define vInterruptOff() \\r
+{ \\r
+ unsigned portCHAR ucInByte; \\r
+ \\r
+ ucInByte = UCSRB; \\r
+ ucInByte &= ~serTX_INT_ENABLE; \\r
+ UCSRB = ucInByte; \\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )\r
+{\r
+unsigned portLONG ulBaudRateCounter;\r
+unsigned portCHAR ucByte;\r
+\r
+ portENTER_CRITICAL();\r
+ {\r
+ /* Create the queues used by the com test task. */\r
+ xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );\r
+ xCharsForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );\r
+\r
+ /* Calculate the baud rate register value from the equation in the\r
+ data sheet. */\r
+ ulBaudRateCounter = ( configCPU_CLOCK_HZ / ( serBAUD_DIV_CONSTANT * ulWantedBaud ) ) - ( unsigned portLONG ) 1;\r
+\r
+ /* Set the baud rate. */ \r
+ ucByte = ( unsigned portCHAR ) ( ulBaudRateCounter & ( unsigned portLONG ) 0xff ); \r
+ UBRRL = ucByte;\r
+\r
+ ulBaudRateCounter >>= ( unsigned portLONG ) 8;\r
+ ucByte = ( unsigned portCHAR ) ( ulBaudRateCounter & ( unsigned portLONG ) 0xff ); \r
+ UBRRH = ucByte;\r
+\r
+ /* Enable the Rx interrupt. The Tx interrupt will get enabled\r
+ later. Also enable the Rx and Tx. */\r
+ UCSRB = ( serRX_INT_ENABLE | serRX_ENABLE | serTX_ENABLE );\r
+\r
+ /* Set the data bits to 8. */\r
+ UCSRC = ( serUCSRC_SELECT | serEIGHT_DATA_BITS );\r
+ }\r
+ portEXIT_CRITICAL();\r
+ \r
+ /* Unlike other ports, this serial code does not allow for more than one\r
+ com port. We therefore don't return a pointer to a port structure and can\r
+ instead just return NULL. */\r
+ return NULL;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )\r
+{\r
+ /* Only one port is supported. */\r
+ ( void ) pxPort;\r
+\r
+ /* Get the next character from the buffer. Return false if no characters\r
+ are available, or arrive before xBlockTime expires. */\r
+ if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )\r
+ {\r
+ return pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ return pdFALSE;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )\r
+{\r
+ /* Only one port is supported. */\r
+ ( void ) pxPort;\r
+\r
+ /* Return false if after the block time there is no room on the Tx queue. */\r
+ if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )\r
+ {\r
+ return pdFAIL;\r
+ }\r
+\r
+ vInterruptOn();\r
+\r
+ return pdPASS;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSerialClose( xComPortHandle xPort )\r
+{\r
+unsigned portCHAR ucByte;\r
+\r
+ /* The parameter is not used. */\r
+ ( void ) xPort;\r
+\r
+ /* Turn off the interrupts. We may also want to delete the queues and/or\r
+ re-install the original ISR. */\r
+\r
+ portENTER_CRITICAL();\r
+ {\r
+ vInterruptOff();\r
+ ucByte = UCSRB;\r
+ ucByte &= ~serRX_INT_ENABLE;\r
+ UCSRB = ucByte;\r
+ }\r
+ portEXIT_CRITICAL();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+SIGNAL( SIG_UART_RECV )\r
+{\r
+signed portCHAR cChar;\r
+\r
+ /* Get the character and post it on the queue of Rxed characters.\r
+ If the post causes a task to wake force a context switch as the woken task\r
+ may have a higher priority than the task we have interrupted. */\r
+ cChar = UDR;\r
+\r
+ if( xQueueSendFromISR( xRxedChars, &cChar, pdFALSE ) )\r
+ {\r
+ taskYIELD();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+SIGNAL( SIG_UART_DATA )\r
+{\r
+signed portCHAR cChar, cTaskWoken;\r
+\r
+ if( xQueueReceiveFromISR( xCharsForTx, &cChar, &cTaskWoken ) == pdTRUE )\r
+ {\r
+ /* Send the next character queued for Tx. */\r
+ UDR = cChar;\r
+ }\r
+ else\r
+ {\r
+ /* Queue empty, nothing to send. */\r
+ vInterruptOff();\r
+ }\r
+}\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. \r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 1\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 20000000 )\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 59 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1468 ) )\r
+#define configMAX_TASK_NAME_LEN ( 3 )\r
+#define configUSE_TRACE_FACILITY 0\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 0\r
+#define configUSE_CO_ROUTINES 1\r
+\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 )\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet 0\r
+#define INCLUDE_uxTaskPriorityGet 0\r
+#define INCLUDE_vTaskDelete 0\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 0\r
+#define INCLUDE_vTaskDelayUntil 0\r
+#define INCLUDE_vTaskDelay 1\r
+\r
+\r
+\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* \r
+ * This demo application creates six co-routines and two tasks (three including \r
+ * the idle task). The co-routines execute as part of the idle task hook.\r
+ *\r
+ * Five of the created co-routines are the standard 'co-routine flash' \r
+ * co-routines contained within the Demo/Common/Minimal/crflash.c file and \r
+ * documented on the FreeRTOS.org WEB site. \r
+ *\r
+ * The 'LCD Task' rotates a string on the LCD, delaying between each character\r
+ * as necessitated by the slow interface, and delaying between each string just\r
+ * long enough to enable the text to be read.\r
+ *\r
+ * The sixth co-routine and final task control the transmission and reception\r
+ * of a string to UART 0. The co-routine periodically sends the first \r
+ * character of the string to the UART, with the UART's TxEnd interrupt being\r
+ * used to transmit the remaining characters. The UART's RxEnd interrupt \r
+ * receives the characters and places them on a queue to be processed by the \r
+ * 'COMs Rx' task. An error is latched should an unexpected character be \r
+ * received, or any character be received out of sequence. \r
+ *\r
+ * A loopback connector is required to ensure that each character transmitted \r
+ * on the UART is also received on the same UART. For test purposes the UART\r
+ * FIFO's are not utalised in order to maximise the interrupt overhead. Also\r
+ * a pseudo random interval is used between the start of each transmission in \r
+ * order that the resultant interrupts are more randomly distributed and \r
+ * therefore more likely to highlight any problems.\r
+ *\r
+ * The flash co-routines control LED's zero to four. LED five is toggled each\r
+ * time the string is transmitted on the UART. LED six is toggled each time\r
+ * the string is CORRECTLY received on the UART. LED seven is latched on should\r
+ * an error be detected in any task or co-routine.\r
+ *\r
+ * In addition the idle task makes repetative calls to \r
+ * prvSetAndCheckRegisters(). This simply loads the general purpose registers \r
+ * with a known value, then checks each register to ensure the held value is \r
+ * still correct. As a low priority task this checking routine is likely to \r
+ * get repeatedly swapped in and out. A register being found to contain an \r
+ * incorrect value is therefore indicative of an error in the task switching \r
+ * mechansim.\r
+ *\r
+ */\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+#include "croutine.h"\r
+\r
+/* Demo application include files. */\r
+#include "partest.h"\r
+#include "crflash.h"\r
+\r
+/* Library include files. */\r
+#include "DriverLib.h"\r
+\r
+/* The time to delay between writing each character to the LCD. */\r
+#define mainCHAR_WRITE_DELAY ( 2 / portTICK_RATE_MS )\r
+\r
+/* The time to delay between writing each string to the LCD. */\r
+#define mainSTRING_WRITE_DELAY ( 400 / portTICK_RATE_MS )\r
+\r
+/* The number of flash co-routines to create. */\r
+#define mainNUM_FLASH_CO_ROUTINES ( 5 )\r
+\r
+/* The length of the queue used to pass received characters to the Comms Rx\r
+task. */\r
+#define mainRX_QUEUE_LEN ( 5 )\r
+\r
+/* The priority of the co-routine used to initiate the transmission of the \r
+string on UART 0. */\r
+#define mainTX_CO_ROUTINE_PRIORITY ( 1 )\r
+\r
+/* Only one co-routine is created so its index is not important. */\r
+#define mainTX_CO_ROUTINE_INDEX ( 0 )\r
+\r
+/* The time between transmissions of the string on UART 0. This is pseudo\r
+random in order to generate a bit or randomness to when the interrupts occur.*/\r
+#define mainMIN_TX_DELAY ( 40 / portTICK_RATE_MS )\r
+#define mainMAX_TX_DELAY ( ( portTickType ) 0x7f )\r
+#define mainOFFSET_TIME ( ( portTickType ) 3 )\r
+\r
+/* The time the Comms Rx task should wait to receive a character. This should\r
+be slightly longer than the time between transmissions. If we do not receive\r
+a character after this time then there must be an error in the transmission or\r
+the timing of the transmission. */\r
+#define mainCOMMS_RX_DELAY ( mainMAX_TX_DELAY + 20 )\r
+\r
+/* The task priorites. */\r
+#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+#define mainCOMMS_RX_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+\r
+/* The LED's toggled by the various tasks. */\r
+#define mainCOMMS_FAIL_LED ( 7 )\r
+#define mainCOMMS_RX_LED ( 6 )\r
+#define mainCOMMS_TX_LED ( 5 )\r
+\r
+/* The baud rate used by the UART comms tasks/co-routine. */\r
+#define mainBAUD_RATE ( 57600 )\r
+\r
+/* FIFO setting for the UART. The FIFO is not used to create a better test. */\r
+#define mainFIFO_SET ( 0x10 )\r
+\r
+/* The string that is transmitted on the UART contains sequentially the \r
+characters from mainFIRST_TX_CHAR to mainLAST_TX_CHAR. */\r
+#define mainFIRST_TX_CHAR '0'\r
+#define mainLAST_TX_CHAR 'z'\r
+\r
+/* Just used to walk through the program memory in order that some random data\r
+can be generated. */\r
+#define mainTOTAL_PROGRAM_MEMORY ( ( unsigned portLONG * ) ( 8 * 1024 ) )\r
+#define mainFIRST_PROGRAM_BYTES ( ( unsigned portLONG * ) 4 )\r
+\r
+/* The error routine that is called if the driver library encounters an error. */\r
+#ifdef DEBUG\r
+void\r
+__error__(char *pcFilename, unsigned long ulLine)\r
+{\r
+}\r
+#endif\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The task that rotates text on the LCD.\r
+ */\r
+static void vLCDTask( void * pvParameters );\r
+\r
+/*\r
+ * The task that receives the characters from UART 0.\r
+ */\r
+static void vCommsRxTask( void * pvParameters );\r
+\r
+/*\r
+ * The co-routine that periodically initiates the transmission of the string on\r
+ * the UART.\r
+ */\r
+static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex );\r
+\r
+/* \r
+ * Writes a string the the LCD.\r
+ */\r
+static void prvWriteString( const portCHAR *pcString );\r
+\r
+/*\r
+ * Initialisation routine for the UART.\r
+ */\r
+static void vSerialInit( void );\r
+\r
+/*\r
+ * Thread safe write to the PDC.\r
+ */\r
+static void prvPDCWrite( portCHAR cAddress, portCHAR cData );\r
+\r
+/*\r
+ * Function to simply set a known value into the general purpose registers\r
+ * then read them back to ensure they remain set correctly. An incorrect value\r
+ * being indicative of an error in the task switching mechanism.\r
+ */\r
+void prvSetAndCheckRegisters( void );\r
+\r
+/*\r
+ * Latch the LED that indicates that an error has occurred. \r
+ */\r
+void vSetErrorLED( void );\r
+\r
+/*\r
+ * Sets up the PLL and ports used by the demo.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Error flag set to pdFAIL if an error is encountered in the tasks/co-routines\r
+defined within this file. */\r
+unsigned portBASE_TYPE uxErrorStatus = pdPASS;\r
+\r
+/* The next character to transmit. */\r
+static portCHAR cNextChar;\r
+\r
+/* The queue used to transmit characters from the interrupt to the Comms Rx\r
+task. */\r
+static xQueueHandle xCommsQueue;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void Main( void )\r
+{\r
+ /* Create the queue used to communicate between the UART ISR and the Comms\r
+ Rx task. */\r
+ xCommsQueue = xQueueCreate( mainRX_QUEUE_LEN, sizeof( portCHAR ) );\r
+\r
+ /* Setup the ports used by the demo and the clock. */\r
+ prvSetupHardware();\r
+\r
+ /* Create the co-routines that flash the LED's. */\r
+ vStartFlashCoRoutines( mainNUM_FLASH_CO_ROUTINES );\r
+\r
+ /* Create the co-routine that initiates the transmission of characters\r
+ on the UART. */\r
+ xCoRoutineCreate( vSerialTxCoRoutine, mainTX_CO_ROUTINE_PRIORITY, mainTX_CO_ROUTINE_INDEX );\r
+\r
+ /* Create the LCD and Comms Rx tasks. */\r
+ xTaskCreate( vLCDTask, "LCD", configMINIMAL_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL );\r
+ xTaskCreate( vCommsRxTask, "CMS", configMINIMAL_STACK_SIZE, NULL, mainCOMMS_RX_TASK_PRIORITY, NULL );\r
+\r
+ /* Start the scheduler running the tasks and co-routines just created. */\r
+ vTaskStartScheduler();\r
+\r
+ /* Should not get here unless we did not have enough memory to start the\r
+ scheduler. */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+ /* Setup the PLL. */\r
+ SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ );\r
+\r
+ /* Initialise the hardware used to talk to the LCD, LED's and UART. */\r
+ PDCInit();\r
+ vParTestInitialise();\r
+ vSerialInit();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationIdleHook( void )\r
+{\r
+ /* The co-routines are executed in the idle task using the idle task \r
+ hook. */\r
+ for( ;; )\r
+ {\r
+ /* Schedule the co-routines. */\r
+ vCoRoutineSchedule();\r
+\r
+ /* Run the register check function between each co-routine. */\r
+ prvSetAndCheckRegisters();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvWriteString( const portCHAR *pcString )\r
+{\r
+ /* Write pcString to the LED, pausing between each character. */\r
+ prvPDCWrite(PDC_LCD_CSR, LCD_CLEAR); \r
+ while( *pcString )\r
+ {\r
+ vTaskDelay( mainCHAR_WRITE_DELAY );\r
+ prvPDCWrite( PDC_LCD_RAM, *pcString );\r
+ pcString++;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vLCDTask( void * pvParameters )\r
+{\r
+unsigned portBASE_TYPE uxIndex;\r
+const unsigned portCHAR ucCFGData[] = { \r
+ 0x30, /* Set data bus to 8-bits. */\r
+ 0x30,\r
+ 0x30,\r
+ 0x3C, /* Number of lines/font. */\r
+ 0x08, /* Display off. */\r
+ 0x01, /* Display clear. */\r
+ 0x06, /* Entry mode [cursor dir][shift]. */\r
+ 0x0C /* Display on [display on][curson on][blinking on]. */\r
+ }; \r
+\r
+/* The strings that are written to the LCD. */\r
+const portCHAR *pcStringsToDisplay[] = { \r
+ "Stellaris",\r
+ "Demo",\r
+ "One",\r
+ "www.FreeRTOS.org",\r
+ ""\r
+ };\r
+\r
+ /* Configure the LCD. */\r
+ uxIndex = 0;\r
+ while( uxIndex < sizeof( ucCFGData ) )\r
+ {\r
+ prvPDCWrite( PDC_LCD_CSR, ucCFGData[ uxIndex ] );\r
+ uxIndex++;\r
+ vTaskDelay( mainCHAR_WRITE_DELAY );\r
+ }\r
+\r
+ /* Turn the LCD Backlight on. */\r
+ prvPDCWrite( PDC_CSR, 0x01 );\r
+\r
+ /* Clear display. */\r
+ vTaskDelay( mainCHAR_WRITE_DELAY );\r
+ prvPDCWrite( PDC_LCD_CSR, LCD_CLEAR ); \r
+\r
+ uxIndex = 0;\r
+ for( ;; ) \r
+ {\r
+ /* Display the string on the LCD. */\r
+ prvWriteString( pcStringsToDisplay[ uxIndex ] );\r
+ \r
+ /* Move on to the next string - wrapping if necessary. */\r
+ uxIndex++;\r
+ if( *( pcStringsToDisplay[ uxIndex ] ) == 0x00 )\r
+ {\r
+ uxIndex = 0;\r
+ /* Longer pause on the last string to be sent. */\r
+ vTaskDelay( mainSTRING_WRITE_DELAY * 2 );\r
+ }\r
+\r
+ /* Wait until it is time to move onto the next string. */\r
+ vTaskDelay( mainSTRING_WRITE_DELAY );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vCommsRxTask( void * pvParameters )\r
+{\r
+static portCHAR cRxedChar, cExpectedChar;\r
+\r
+ /* Set the char we expect to receive to the start of the string. */\r
+ cExpectedChar = mainFIRST_TX_CHAR;\r
+\r
+ for( ;; )\r
+ {\r
+ /* Wait for a character to be received. */\r
+ xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY );\r
+\r
+ /* Was the character recived (if any) the expected character. */\r
+ if( cRxedChar != cExpectedChar )\r
+ {\r
+ /* Got an unexpected character. This can sometimes occur when\r
+ reseting the system using the debugger leaving characters already\r
+ in the UART regsters. */\r
+ uxErrorStatus = pdFAIL;\r
+\r
+ /* Resync by waiting for the end of the current string. */\r
+ while( cRxedChar != mainLAST_TX_CHAR )\r
+ {\r
+ while( !xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, portMAX_DELAY ) );\r
+ }\r
+\r
+ /* The next expected character is the start of the string again. */\r
+ cExpectedChar = mainFIRST_TX_CHAR;\r
+ }\r
+ else\r
+ {\r
+ if( cExpectedChar == mainLAST_TX_CHAR )\r
+ {\r
+ /* We have reached the end of the string - we now expect to \r
+ receive the first character in the string again. The LED is \r
+ toggled to indicate that the entire string was received without\r
+ error. */\r
+ vParTestToggleLED( mainCOMMS_RX_LED );\r
+ cExpectedChar = mainFIRST_TX_CHAR;\r
+ }\r
+ else\r
+ {\r
+ /* We got the expected character, we now expect to receive the\r
+ next character in the string. */\r
+ cExpectedChar++;\r
+ }\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )\r
+{\r
+portTickType xDelayPeriod;\r
+static unsigned portLONG *pulRandomBytes = mainFIRST_PROGRAM_BYTES;\r
+\r
+ /* Co-routine MUST start with a call to crSTART. */\r
+ crSTART( xHandle );\r
+\r
+ for(;;)\r
+ { \r
+ /* Was the previously transmitted string received correctly? */\r
+ if( uxErrorStatus != pdPASS )\r
+ {\r
+ /* An error was encountered so set the error LED. */\r
+ vSetErrorLED();\r
+ }\r
+\r
+ /* The next character to Tx is the first in the string. */\r
+ cNextChar = mainFIRST_TX_CHAR;\r
+\r
+ UARTIntDisable( UART0_BASE, UART_INT_TX );\r
+ {\r
+ /* Send the first character. */\r
+ if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) )\r
+ {\r
+ HWREG( UART0_BASE + UART_O_DR ) = cNextChar;\r
+ }\r
+\r
+ /* Move the variable to the char to Tx on so the ISR transmits\r
+ the next character in the string once this one has completed. */\r
+ cNextChar++;\r
+ }\r
+ UARTIntEnable(UART0_BASE, UART_INT_TX);\r
+\r
+ /* Toggle the LED to show a new string is being transmitted. */\r
+ vParTestToggleLED( mainCOMMS_TX_LED );\r
+\r
+ /* Delay before we start the string off again. A pseudo-random delay\r
+ is used as this will provide a better test. */\r
+ xDelayPeriod = xTaskGetTickCount() + ( *pulRandomBytes );\r
+\r
+ pulRandomBytes++;\r
+ if( pulRandomBytes > mainTOTAL_PROGRAM_MEMORY )\r
+ {\r
+ pulRandomBytes = mainFIRST_PROGRAM_BYTES;\r
+ }\r
+\r
+ /* Make sure we don't wait too long... */\r
+ xDelayPeriod &= mainMAX_TX_DELAY;\r
+\r
+ /* ...but we do want to wait. */\r
+ if( xDelayPeriod < mainMIN_TX_DELAY )\r
+ {\r
+ xDelayPeriod = mainMIN_TX_DELAY;\r
+ }\r
+\r
+ /* Block for the random(ish) time. */\r
+ crDELAY( xHandle, xDelayPeriod );\r
+ }\r
+\r
+ /* Co-routine MUST end with a call to crEND. */\r
+ crEND();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vSerialInit( void )\r
+{\r
+ /* Enable the UART. GPIOA has already been initialised. */\r
+ SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);\r
+\r
+ /* Set GPIO A0 and A1 as peripheral function. They are used to output the\r
+ UART signals. */\r
+ GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW );\r
+\r
+ /* Configure the UART for 8-N-1 operation. */\r
+ UARTConfigSet( UART0_BASE, mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE );\r
+\r
+ /* We dont want to use the fifo. This is for test purposes to generate\r
+ as many interrupts as possible. */\r
+ HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET;\r
+\r
+ /* Enable both Rx and Tx interrupts. */\r
+ HWREG( UART0_BASE + UART_O_IM ) |= ( UART_INT_TX | UART_INT_RX );\r
+ IntEnable( INT_UART0 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vUART_ISR(void)\r
+{\r
+unsigned portLONG ulStatus;\r
+portCHAR cRxedChar;\r
+portBASE_TYPE xTaskWokenByPost = pdFALSE;\r
+\r
+ /* What caused the interrupt. */\r
+ ulStatus = UARTIntStatus( UART0_BASE, pdTRUE );\r
+\r
+ /* Clear the interrupt. */\r
+ UARTIntClear( UART0_BASE, ulStatus );\r
+\r
+ /* Was an Rx interrpt pending? */\r
+ if( ulStatus & UART_INT_RX )\r
+ {\r
+ if( ( HWREG(UART0_BASE + UART_O_FR ) & UART_FR_RXFF ) )\r
+ {\r
+ /* Get the char from the buffer and post it onto the queue of\r
+ Rxed chars. Posting the character should wake the task that is \r
+ blocked on the queue waiting for characters. */\r
+ cRxedChar = ( portCHAR ) HWREG( UART0_BASE + UART_O_DR );\r
+ xTaskWokenByPost = xQueueSendFromISR( xCommsQueue, &cRxedChar, xTaskWokenByPost );\r
+ } \r
+ }\r
+\r
+ /* Was a Tx interrupt pending? */\r
+ if( ulStatus & UART_INT_TX )\r
+ {\r
+ /* Send the next character in the string. We are not using the FIFO. */\r
+ if( cNextChar <= mainLAST_TX_CHAR )\r
+ {\r
+ if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) )\r
+ {\r
+ HWREG( UART0_BASE + UART_O_DR ) = cNextChar;\r
+ }\r
+ cNextChar++;\r
+ }\r
+ }\r
+ \r
+ if( xTaskWokenByPost )\r
+ {\r
+ /* If a task was woken by the character being received then we force\r
+ a context switch to occur in case the task is of higher priority than\r
+ the currently executing task (i.e. the task that this interrupt \r
+ interrupted.) */\r
+ portEND_SWITCHING_ISR( xTaskWokenByPost );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvPDCWrite( portCHAR cAddress, portCHAR cData )\r
+{\r
+ vTaskSuspendAll();\r
+ {\r
+ PDCWrite( cAddress, cData );\r
+ }\r
+ xTaskResumeAll();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSetErrorLED( void )\r
+{\r
+ vParTestSetLED( mainCOMMS_FAIL_LED, pdTRUE );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void prvSetAndCheckRegisters( void )\r
+{\r
+ /* Fill the general purpose registers with known values. */\r
+ __asm volatile( " mov r11, #10\n"\r
+ " add r0, r11, #1\n"\r
+ " add r1, r11, #2\n"\r
+ " add r2, r11, #3\n"\r
+ " add r3, r11, #4\n"\r
+ " add r4, r11, #5\n"\r
+ " add r5, r11, #6\n"\r
+ " add r6, r11, #7\n"\r
+ " add r7, r11, #8\n"\r
+ " add r8, r11, #9\n"\r
+ " add r9, r11, #10\n"\r
+ " add r10, r11, #11\n"\r
+ " add r12, r11, #12" );\r
+\r
+ /* Check the values are as expected. */\r
+ __asm volatile( " cmp r11, #10\n"\r
+ " bne set_error_led\n"\r
+ " cmp r0, #11\n"\r
+ " bne set_error_led\n"\r
+ " cmp r1, #12\n"\r
+ " bne set_error_led\n"\r
+ " cmp r2, #13\n"\r
+ " bne set_error_led\n"\r
+ " cmp r3, #14\n"\r
+ " bne set_error_led\n"\r
+ " cmp r4, #15\n"\r
+ " bne set_error_led\n"\r
+ " cmp r5, #16\n"\r
+ " bne set_error_led\n"\r
+ " cmp r6, #17\n"\r
+ " bne set_error_led\n"\r
+ " cmp r7, #18\n"\r
+ " bne set_error_led\n"\r
+ " cmp r8, #19\n"\r
+ " bne set_error_led\n"\r
+ " cmp r9, #20\n"\r
+ " bne set_error_led\n"\r
+ " cmp r10, #21\n"\r
+ " bne set_error_led\n"\r
+ " cmp r12, #22\n"\r
+ " bne set_error_led\n"\r
+ " bx lr" );\r
+\r
+ __asm volatile( "set_error_led:\n"\r
+ " push {r14}\n"\r
+ " ldr r1, =vSetErrorLED\n"\r
+ " blx r1\n"\r
+ " pop {r14}\n"\r
+ " bx lr" );\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+Move these two fines into the Demo/CORTEX_LM3S102_GCC directory to run Demo 1.\r
+\r
+See the port documentation on the www.FreeRTOS.org site for more information.\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. \r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 1\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 20000000 )\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 59 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1240 ) )\r
+#define configMAX_TASK_NAME_LEN ( 3 )\r
+#define configUSE_TRACE_FACILITY 0\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 0\r
+#define configUSE_CO_ROUTINES 1\r
+\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 )\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 3 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet 0\r
+#define INCLUDE_uxTaskPriorityGet 0\r
+#define INCLUDE_vTaskDelete 0\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 0\r
+#define INCLUDE_vTaskDelayUntil 0\r
+#define INCLUDE_vTaskDelay 1\r
+\r
+\r
+\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* \r
+ * This demo application creates seven co-routines and one task (two including \r
+ * the idle task). The co-routines execute as part of the idle task hook.\r
+ *\r
+ * Five of the created co-routines are the standard 'co-routine flash' \r
+ * co-routines contained within the Demo/Common/Minimal/crflash.c file and \r
+ * documented on the FreeRTOS.org WEB site. \r
+ *\r
+ * The 'LCD Task' rotates a string on the LCD, delaying between each character\r
+ * as necessitated by the slow interface, and delaying between each string just\r
+ * long enough to enable the text to be read.\r
+ *\r
+ * The sixth co-routine controls the transmission of a string to UART 0. The \r
+ * co-routine periodically sends the first character of the string to the UART, \r
+ * with the UART's TxEnd interrupt being used to transmit the remaining \r
+ * characters. The UART's RxEnd interrupt receives the characters and places \r
+ * them on a queue to be processed by the seventh and final co-routine. An \r
+ * error is latched should an unexpected character be received, or any \r
+ * character be received out of sequence. \r
+ *\r
+ * A loopback connector is required to ensure that each character transmitted \r
+ * on the UART is also received on the same UART. For test purposes the UART\r
+ * FIFO's are not utalised in order to maximise the interrupt overhead. Also\r
+ * a pseudo random interval is used between the start of each transmission in \r
+ * order that the resultant interrupts are more randomly distributed and \r
+ * therefore more likely to highlight any problems.\r
+ *\r
+ * The flash co-routines control LED's zero to four. LED five is toggled each\r
+ * time the string is transmitted on the UART. LED six is toggled each time\r
+ * the string is CORRECTLY received on the UART. LED seven is latched on should\r
+ * an error be detected in any task or co-routine.\r
+ *\r
+ * In addition the idle task makes repetative calls to \r
+ * prvSetAndCheckRegisters(). This simply loads the general purpose registers \r
+ * with a known value, then checks each register to ensure the held value is \r
+ * still correct. As a low priority task this checking routine is likely to \r
+ * get repeatedly swapped in and out. A register being found to contain an \r
+ * incorrect value is therefore indicative of an error in the task switching \r
+ * mechansim.\r
+ *\r
+ */\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+#include "croutine.h"\r
+\r
+/* Demo application include files. */\r
+#include "partest.h"\r
+#include "crflash.h"\r
+\r
+/* Library include files. */\r
+#include "DriverLib.h"\r
+\r
+/* The time to delay between writing each character to the LCD. */\r
+#define mainCHAR_WRITE_DELAY ( 2 / portTICK_RATE_MS )\r
+\r
+/* The time to delay between writing each string to the LCD. */\r
+#define mainSTRING_WRITE_DELAY ( 400 / portTICK_RATE_MS )\r
+\r
+/* The number of flash co-routines to create. */\r
+#define mainNUM_FLASH_CO_ROUTINES ( 5 )\r
+\r
+/* The length of the queue used to pass received characters to the Comms Rx\r
+task. */\r
+#define mainRX_QUEUE_LEN ( 5 )\r
+\r
+/* The priority of the co-routine used to initiate the transmission of the \r
+string on UART 0. */\r
+#define mainTX_CO_ROUTINE_PRIORITY ( 1 )\r
+\r
+/* The priority of the co-routine used to receive characters from the UART. */\r
+#define mainRX_CO_ROUTINE_PRIORITY ( 2 )\r
+\r
+/* Only one co-routine is created so its index is not important. */\r
+#define mainTX_CO_ROUTINE_INDEX ( 0 )\r
+#define mainRX_CO_ROUTINE_INDEX ( 0 )\r
+\r
+/* The time between transmissions of the string on UART 0. This is pseudo\r
+random in order to generate a bit or randomness to when the interrupts occur.*/\r
+#define mainMIN_TX_DELAY ( 40 / portTICK_RATE_MS )\r
+#define mainMAX_TX_DELAY ( ( portTickType ) 0x7f )\r
+#define mainOFFSET_TIME ( ( portTickType ) 3 )\r
+\r
+/* The time the Comms Rx task should wait to receive a character. This should\r
+be slightly longer than the time between transmissions. If we do not receive\r
+a character after this time then there must be an error in the transmission or\r
+the timing of the transmission. */\r
+#define mainCOMMS_RX_DELAY ( mainMAX_TX_DELAY + 20 )\r
+\r
+/* The task priorites. */\r
+#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+#define mainCOMMS_RX_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+\r
+/* The LED's toggled by the various tasks. */\r
+#define mainCOMMS_FAIL_LED ( 7 )\r
+#define mainCOMMS_RX_LED ( 6 )\r
+#define mainCOMMS_TX_LED ( 5 )\r
+\r
+/* The baud rate used by the UART comms tasks/co-routine. */\r
+#define mainBAUD_RATE ( 57600 )\r
+\r
+/* FIFO setting for the UART. The FIFO is not used to create a better test. */\r
+#define mainFIFO_SET ( 0x10 )\r
+\r
+/* The string that is transmitted on the UART contains sequentially the \r
+characters from mainFIRST_TX_CHAR to mainLAST_TX_CHAR. */\r
+#define mainFIRST_TX_CHAR '0'\r
+#define mainLAST_TX_CHAR 'z'\r
+\r
+/* Just used to walk through the program memory in order that some random data\r
+can be generated. */\r
+#define mainTOTAL_PROGRAM_MEMORY ( ( unsigned portLONG * ) ( 8 * 1024 ) )\r
+#define mainFIRST_PROGRAM_BYTES ( ( unsigned portLONG * ) 4 )\r
+\r
+/* The error routine that is called if the driver library encounters an error. */\r
+#ifdef DEBUG\r
+void\r
+__error__(char *pcFilename, unsigned long ulLine)\r
+{\r
+}\r
+#endif\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The task that rotates text on the LCD.\r
+ */\r
+static void vLCDTask( void * pvParameters );\r
+\r
+/*\r
+ * The task that receives the characters from UART 0.\r
+ */\r
+static void vCommsRxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex );\r
+\r
+/*\r
+ * The co-routine that periodically initiates the transmission of the string on\r
+ * the UART.\r
+ */\r
+static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex );\r
+\r
+/* \r
+ * Writes a string the the LCD.\r
+ */\r
+static void prvWriteString( const portCHAR *pcString );\r
+\r
+/*\r
+ * Initialisation routine for the UART.\r
+ */\r
+static void vSerialInit( void );\r
+\r
+/*\r
+ * Thread safe write to the PDC.\r
+ */\r
+static void prvPDCWrite( portCHAR cAddress, portCHAR cData );\r
+\r
+/*\r
+ * Function to simply set a known value into the general purpose registers\r
+ * then read them back to ensure they remain set correctly. An incorrect value\r
+ * being indicative of an error in the task switching mechanism.\r
+ */\r
+void prvSetAndCheckRegisters( void );\r
+\r
+/*\r
+ * Latch the LED that indicates that an error has occurred. \r
+ */\r
+void vSetErrorLED( void );\r
+\r
+/*\r
+ * Sets up the PLL and ports used by the demo.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Error flag set to pdFAIL if an error is encountered in the tasks/co-routines\r
+defined within this file. */\r
+unsigned portBASE_TYPE uxErrorStatus = pdPASS;\r
+\r
+/* The next character to transmit. */\r
+static portCHAR cNextChar;\r
+\r
+/* The queue used to transmit characters from the interrupt to the Comms Rx\r
+task. */\r
+static xQueueHandle xCommsQueue;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void Main( void )\r
+{\r
+ /* Create the queue used to communicate between the UART ISR and the Comms\r
+ Rx task. */\r
+ xCommsQueue = xQueueCreate( mainRX_QUEUE_LEN, sizeof( portCHAR ) );\r
+\r
+ /* Setup the ports used by the demo and the clock. */\r
+ prvSetupHardware();\r
+\r
+ /* Create the co-routines that flash the LED's. */\r
+ vStartFlashCoRoutines( mainNUM_FLASH_CO_ROUTINES );\r
+\r
+ /* Create the co-routine that initiates the transmission of characters\r
+ on the UART. */\r
+ xCoRoutineCreate( vSerialTxCoRoutine, mainTX_CO_ROUTINE_PRIORITY, mainTX_CO_ROUTINE_INDEX );\r
+\r
+ /* Create the co-routine that receives characters from the UART. */\r
+ xCoRoutineCreate( vCommsRxCoRoutine, mainRX_CO_ROUTINE_PRIORITY, mainRX_CO_ROUTINE_INDEX );\r
+\r
+ /* Create the LCD task. */\r
+ xTaskCreate( vLCDTask, "LCD", configMINIMAL_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL );\r
+\r
+ /* Start the scheduler running the tasks and co-routines just created. */\r
+ vTaskStartScheduler();\r
+\r
+ /* Should not get here unless we did not have enough memory to start the\r
+ scheduler. */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+ /* Setup the PLL. */\r
+ SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ );\r
+\r
+ /* Initialise the hardware used to talk to the LCD, LED's and UART. */\r
+ PDCInit();\r
+ vParTestInitialise();\r
+ vSerialInit();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationIdleHook( void )\r
+{\r
+ /* The co-routines are executed in the idle task using the idle task \r
+ hook. */\r
+ for( ;; )\r
+ {\r
+ /* Schedule the co-routines. */\r
+ vCoRoutineSchedule();\r
+\r
+ /* Run the register check function between each co-routine. */\r
+ prvSetAndCheckRegisters();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvWriteString( const portCHAR *pcString )\r
+{\r
+ /* Write pcString to the LED, pausing between each character. */\r
+ prvPDCWrite(PDC_LCD_CSR, LCD_CLEAR); \r
+ while( *pcString )\r
+ {\r
+ vTaskDelay( mainCHAR_WRITE_DELAY );\r
+ prvPDCWrite( PDC_LCD_RAM, *pcString );\r
+ pcString++;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vLCDTask( void * pvParameters )\r
+{\r
+unsigned portBASE_TYPE uxIndex;\r
+const unsigned portCHAR ucCFGData[] = { \r
+ 0x30, /* Set data bus to 8-bits. */\r
+ 0x30,\r
+ 0x30,\r
+ 0x3C, /* Number of lines/font. */\r
+ 0x08, /* Display off. */\r
+ 0x01, /* Display clear. */\r
+ 0x06, /* Entry mode [cursor dir][shift]. */\r
+ 0x0C /* Display on [display on][curson on][blinking on]. */\r
+ }; \r
+\r
+/* The strings that are written to the LCD. */\r
+const portCHAR *pcStringsToDisplay[] = { \r
+ "Stellaris",\r
+ "Demo",\r
+ "Two",\r
+ "www.FreeRTOS.org",\r
+ ""\r
+ };\r
+\r
+ /* Configure the LCD. */\r
+ uxIndex = 0;\r
+ while( uxIndex < sizeof( ucCFGData ) )\r
+ {\r
+ prvPDCWrite( PDC_LCD_CSR, ucCFGData[ uxIndex ] );\r
+ uxIndex++;\r
+ vTaskDelay( mainCHAR_WRITE_DELAY );\r
+ }\r
+\r
+ /* Turn the LCD Backlight on. */\r
+ prvPDCWrite( PDC_CSR, 0x01 );\r
+\r
+ /* Clear display. */\r
+ vTaskDelay( mainCHAR_WRITE_DELAY );\r
+ prvPDCWrite( PDC_LCD_CSR, LCD_CLEAR ); \r
+\r
+ uxIndex = 0;\r
+ for( ;; ) \r
+ {\r
+ /* Display the string on the LCD. */\r
+ prvWriteString( pcStringsToDisplay[ uxIndex ] );\r
+ \r
+ /* Move on to the next string - wrapping if necessary. */\r
+ uxIndex++;\r
+ if( *( pcStringsToDisplay[ uxIndex ] ) == 0x00 )\r
+ {\r
+ uxIndex = 0;\r
+ /* Longer pause on the last string to be sent. */\r
+ vTaskDelay( mainSTRING_WRITE_DELAY * 2 );\r
+ }\r
+\r
+ /* Wait until it is time to move onto the next string. */\r
+ vTaskDelay( mainSTRING_WRITE_DELAY );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vCommsRxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )\r
+{\r
+static portCHAR cRxedChar, cExpectedChar = mainFIRST_TX_CHAR;\r
+portBASE_TYPE xResult;\r
+\r
+ crSTART( xHandle );\r
+\r
+ for( ;; )\r
+ {\r
+ /* Wait for a character to be received. */\r
+ crQUEUE_RECEIVE( xHandle, xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY, &xResult );\r
+\r
+ /* Was the character recived (if any) the expected character. */\r
+ if( ( cRxedChar != cExpectedChar ) || ( xResult != pdPASS ) )\r
+ {\r
+ /* Got an unexpected character. This can sometimes occur when\r
+ reseting the system using the debugger leaving characters already\r
+ in the UART regsters. */\r
+ uxErrorStatus = pdFAIL;\r
+\r
+ /* Resync by waiting for the end of the current string. */\r
+ while( cRxedChar != mainLAST_TX_CHAR )\r
+ {\r
+ crQUEUE_RECEIVE( xHandle, xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY, &xResult );\r
+ }\r
+\r
+ /* The next expected character is the start of the string again. */\r
+ cExpectedChar = mainFIRST_TX_CHAR;\r
+ }\r
+ else\r
+ {\r
+ if( cExpectedChar == mainLAST_TX_CHAR )\r
+ {\r
+ /* We have reached the end of the string - we now expect to \r
+ receive the first character in the string again. The LED is \r
+ toggled to indicate that the entire string was received without\r
+ error. */\r
+ vParTestToggleLED( mainCOMMS_RX_LED );\r
+ cExpectedChar = mainFIRST_TX_CHAR;\r
+ }\r
+ else\r
+ {\r
+ /* We got the expected character, we now expect to receive the\r
+ next character in the string. */\r
+ cExpectedChar++;\r
+ }\r
+ }\r
+ }\r
+\r
+ crEND();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )\r
+{\r
+portTickType xDelayPeriod;\r
+static unsigned portLONG *pulRandomBytes = mainFIRST_PROGRAM_BYTES;\r
+\r
+ /* Co-routine MUST start with a call to crSTART. */\r
+ crSTART( xHandle );\r
+\r
+ for(;;)\r
+ { \r
+ /* Was the previously transmitted string received correctly? */\r
+ if( uxErrorStatus != pdPASS )\r
+ {\r
+ /* An error was encountered so set the error LED. */\r
+ vSetErrorLED();\r
+ }\r
+\r
+ /* The next character to Tx is the first in the string. */\r
+ cNextChar = mainFIRST_TX_CHAR;\r
+\r
+ UARTIntDisable( UART0_BASE, UART_INT_TX );\r
+ {\r
+ /* Send the first character. */\r
+ if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) )\r
+ {\r
+ HWREG( UART0_BASE + UART_O_DR ) = cNextChar;\r
+ }\r
+\r
+ /* Move the variable to the char to Tx on so the ISR transmits\r
+ the next character in the string once this one has completed. */\r
+ cNextChar++;\r
+ }\r
+ UARTIntEnable(UART0_BASE, UART_INT_TX);\r
+\r
+ /* Toggle the LED to show a new string is being transmitted. */\r
+ vParTestToggleLED( mainCOMMS_TX_LED );\r
+\r
+ /* Delay before we start the string off again. A pseudo-random delay\r
+ is used as this will provide a better test. */\r
+ xDelayPeriod = xTaskGetTickCount() + ( *pulRandomBytes );\r
+\r
+ pulRandomBytes++;\r
+ if( pulRandomBytes > mainTOTAL_PROGRAM_MEMORY )\r
+ {\r
+ pulRandomBytes = mainFIRST_PROGRAM_BYTES;\r
+ }\r
+\r
+ /* Make sure we don't wait too long... */\r
+ xDelayPeriod &= mainMAX_TX_DELAY;\r
+\r
+ /* ...but we do want to wait. */\r
+ if( xDelayPeriod < mainMIN_TX_DELAY )\r
+ {\r
+ xDelayPeriod = mainMIN_TX_DELAY;\r
+ }\r
+\r
+ /* Block for the random(ish) time. */\r
+ crDELAY( xHandle, xDelayPeriod );\r
+ }\r
+\r
+ /* Co-routine MUST end with a call to crEND. */\r
+ crEND();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vSerialInit( void )\r
+{\r
+ /* Enable the UART. GPIOA has already been initialised. */\r
+ SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);\r
+\r
+ /* Set GPIO A0 and A1 as peripheral function. They are used to output the\r
+ UART signals. */\r
+ GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW );\r
+\r
+ /* Configure the UART for 8-N-1 operation. */\r
+ UARTConfigSet( UART0_BASE, mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE );\r
+\r
+ /* We dont want to use the fifo. This is for test purposes to generate\r
+ as many interrupts as possible. */\r
+ HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET;\r
+\r
+ /* Enable both Rx and Tx interrupts. */\r
+ HWREG( UART0_BASE + UART_O_IM ) |= ( UART_INT_TX | UART_INT_RX );\r
+ IntEnable( INT_UART0 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vUART_ISR(void)\r
+{\r
+unsigned portLONG ulStatus;\r
+portCHAR cRxedChar;\r
+portBASE_TYPE xTaskWokenByPost = pdFALSE;\r
+\r
+ /* What caused the interrupt. */\r
+ ulStatus = UARTIntStatus( UART0_BASE, pdTRUE );\r
+\r
+ /* Clear the interrupt. */\r
+ UARTIntClear( UART0_BASE, ulStatus );\r
+\r
+ /* Was an Rx interrpt pending? */\r
+ if( ulStatus & UART_INT_RX )\r
+ {\r
+ if( ( HWREG(UART0_BASE + UART_O_FR ) & UART_FR_RXFF ) )\r
+ {\r
+ /* Get the char from the buffer and post it onto the queue of\r
+ Rxed chars. Posting the character should wake the task that is \r
+ blocked on the queue waiting for characters. */\r
+ cRxedChar = ( portCHAR ) HWREG( UART0_BASE + UART_O_DR );\r
+ xTaskWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsQueue, &cRxedChar, xTaskWokenByPost );\r
+ } \r
+ }\r
+\r
+ /* Was a Tx interrupt pending? */\r
+ if( ulStatus & UART_INT_TX )\r
+ {\r
+ /* Send the next character in the string. We are not using the FIFO. */\r
+ if( cNextChar <= mainLAST_TX_CHAR )\r
+ {\r
+ if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) )\r
+ {\r
+ HWREG( UART0_BASE + UART_O_DR ) = cNextChar;\r
+ }\r
+ cNextChar++;\r
+ }\r
+ }\r
+ \r
+ if( xTaskWokenByPost )\r
+ {\r
+ /* We are posting to a co-routine rather than a task so don't bother\r
+ causing a task switch. */\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvPDCWrite( portCHAR cAddress, portCHAR cData )\r
+{\r
+ vTaskSuspendAll();\r
+ {\r
+ PDCWrite( cAddress, cData );\r
+ }\r
+ xTaskResumeAll();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSetErrorLED( void )\r
+{\r
+ vParTestSetLED( mainCOMMS_FAIL_LED, pdTRUE );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void prvSetAndCheckRegisters( void )\r
+{\r
+ /* Fill the general purpose registers with known values. */\r
+ __asm volatile( " mov r11, #10\n"\r
+ " add r0, r11, #1\n"\r
+ " add r1, r11, #2\n"\r
+ " add r2, r11, #3\n"\r
+ " add r3, r11, #4\n"\r
+ " add r4, r11, #5\n"\r
+ " add r5, r11, #6\n"\r
+ " add r6, r11, #7\n"\r
+ " add r7, r11, #8\n"\r
+ " add r12, r11, #12" );\r
+\r
+ /* Check the values are as expected. */\r
+ __asm volatile( " cmp r11, #10\n"\r
+ " bne set_error_led\n"\r
+ " cmp r0, #11\n"\r
+ " bne set_error_led\n"\r
+ " cmp r1, #12\n"\r
+ " bne set_error_led\n"\r
+ " cmp r2, #13\n"\r
+ " bne set_error_led\n"\r
+ " cmp r3, #14\n"\r
+ " bne set_error_led\n"\r
+ " cmp r4, #15\n"\r
+ " bne set_error_led\n"\r
+ " cmp r5, #16\n"\r
+ " bne set_error_led\n"\r
+ " cmp r6, #17\n"\r
+ " bne set_error_led\n"\r
+ " cmp r7, #18\n"\r
+ " bne set_error_led\n"\r
+ " cmp r12, #22\n"\r
+ " bne set_error_led\n"\r
+ " bx lr" );\r
+\r
+ __asm volatile( "set_error_led:\n"\r
+ " push {r14}\n"\r
+ " ldr r1, =vSetErrorLED\n"\r
+ " blx r1\n"\r
+ " pop {r14}\n"\r
+ " bx lr" );\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+Move these two fines into the Demo/CORTEX_LM3S102_GCC directory to run Demo 2.\r
+\r
+See the port documentation on the www.FreeRTOS.org site for more information.\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. \r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 1\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 20000000 )\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 59 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1468 ) )\r
+#define configMAX_TASK_NAME_LEN ( 3 )\r
+#define configUSE_TRACE_FACILITY 0\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 0\r
+#define configUSE_CO_ROUTINES 1\r
+\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 )\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet 0\r
+#define INCLUDE_uxTaskPriorityGet 0\r
+#define INCLUDE_vTaskDelete 0\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 0\r
+#define INCLUDE_vTaskDelayUntil 0\r
+#define INCLUDE_vTaskDelay 1\r
+\r
+\r
+\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+#******************************************************************************
+#
+# Makefile - Rules for building the driver library and examples.
+#
+# Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
+#
+# Software License Agreement
+#
+# Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+# exclusively on LMI's Stellaris Family of microcontroller products.
+#
+# The software is owned by LMI and/or its suppliers, and is protected under
+# applicable copyright laws. All rights are reserved. Any use in violation
+# of the foregoing restrictions may subject the user to criminal sanctions
+# under applicable laws, as well as to civil liability for the breach of the
+# terms and conditions of this license.
+#
+# THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+# OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+# LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+# CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+#
+#******************************************************************************
+
+include makedefs
+
+RTOS_SOURCE_DIR=../../Source
+DEMO_SOURCE_DIR=../Common/Minimal
+
+CFLAGS+=-I hw_include -I . -I ${RTOS_SOURCE_DIR}/include -I ${RTOS_SOURCE_DIR}/portable/GCC/ARM_CM3 -I ../Common/include -D GCC_ARMCM3_LM3S102 -D inline=
+
+VPATH=${RTOS_SOURCE_DIR}:${RTOS_SOURCE_DIR}/portable/MemMang:${RTOS_SOURCE_DIR}/portable/GCC/ARM_CM3:${DEMO_SOURCE_DIR}:init:ParTest:hw_include
+
+
+OBJS= ${COMPILER}/main.o \
+ ${COMPILER}/pdc.o \
+ ${COMPILER}/list.o \
+ ${COMPILER}/queue.o \
+ ${COMPILER}/tasks.o \
+ ${COMPILER}/port.o \
+ ${COMPILER}/heap_1.o \
+ ${COMPILER}/ParTest.o \
+ ${COMPILER}/crflash.o \
+ ${COMPILER}/croutine.o
+# ${COMPILER}/pendsv_handler.o
+
+INIT_OBJS= ${COMPILER}/startup.o
+
+LIBS= hw_include/libdriver.a
+
+
+#
+# The default rule, which causes init to be built.
+#
+all: ${COMPILER} \
+ ${COMPILER}/RTOSDemo.axf \
+
+#
+# The rule to clean out all the build products
+#
+
+clean:
+ @rm -rf ${COMPILER} ${wildcard *.bin} RTOSDemo.axf
+
+#
+# The rule to create the target directory
+#
+${COMPILER}:
+ @mkdir ${COMPILER}
+
+${COMPILER}/RTOSDemo.axf: ${INIT_OBJS} ${OBJS} ${LIBS}
+SCATTER_RTOSDemo=standalone.ld
+ENTRY_RTOSDemo=ResetISR
+
+#
+#
+# Include the automatically generated dependency files.
+#
+-include ${wildcard ${COMPILER}/*.d} __dummy__
+
+
+
+
+
+
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple parallel port IO routines.\r
+ *-----------------------------------------------------------*/\r
+\r
+/*\r
+*/\r
+\r
+\r
+#include "FreeRTOS.h"\r
+#include "Task.h"\r
+#include "partest.h"\r
+\r
+#include "pdc.h"\r
+\r
+#define partstPINS (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 Z | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7)\r
+\r
+#define partstALL_OUTPUTS_OFF ( ( unsigned portCHAR ) 0x00 )\r
+#define partstMAX_OUTPUT_LED ( ( unsigned portCHAR ) 8 )\r
+\r
+static volatile unsigned portCHAR ucOutputValue = partstALL_OUTPUTS_OFF;\r
+\r
+void vParTestInitialise( void )\r
+{\r
+ PDCInit();\r
+ PDCWrite( PDC_LED, ucOutputValue );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )\r
+{\r
+unsigned portCHAR ucBit = ( unsigned portCHAR ) 1;\r
+\r
+ vTaskSuspendAll();\r
+ {\r
+ if( uxLED < partstMAX_OUTPUT_LED )\r
+ {\r
+ ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED;\r
+\r
+ if( xValue == pdFALSE )\r
+ {\r
+ ucBit ^= ( unsigned portCHAR ) 0xff;\r
+ ucOutputValue &= ucBit;\r
+ }\r
+ else\r
+ {\r
+ ucOutputValue |= ucBit;\r
+ }\r
+\r
+ PDCWrite( PDC_LED, ucOutputValue );\r
+ } \r
+ }\r
+ xTaskResumeAll();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+unsigned portCHAR ucBit;\r
+\r
+ vTaskSuspendAll();\r
+ {\r
+ if( uxLED < partstMAX_OUTPUT_LED )\r
+ {\r
+ ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED;\r
+\r
+ if( ucOutputValue & ucBit )\r
+ {\r
+ ucOutputValue &= ~ucBit;\r
+ }\r
+ else\r
+ {\r
+ ucOutputValue |= ucBit;\r
+ }\r
+\r
+ PDCWrite( PDC_LED, ucOutputValue );\r
+ }\r
+ }\r
+ xTaskResumeAll();\r
+}\r
+\r
--- /dev/null
+#ifndef INCLUDE_DRIVER_LIB_H\r
+#define INCLUDE_DRIVER_LIB_H\r
+\r
+#include "hw_ints.h"\r
+#include "hw_uart.h"\r
+#include "hw_memmap.h"\r
+#include "hw_types.h"\r
+#include "hw_nvic.h"\r
+#include "hw_ssi.h"\r
+\r
+#include "gpio.h"\r
+#include "interrupt.h"\r
+#include "sysctl.h"\r
+#include "uart.h"\r
+#include "ssi.h"\r
+#include "pdc.h"\r
+\r
+#endif\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// debug.h - Macros for assisting debug of the driver library.\r
+//\r
+// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 523 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __DEBUG_H__\r
+#define __DEBUG_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototype for the function that is called when an invalid argument is passed\r
+// to an API. This is only used when doing a DEBUG build.\r
+//\r
+//*****************************************************************************\r
+extern void __error__(char *pcFilename, unsigned long ulLine);\r
+\r
+//*****************************************************************************\r
+//\r
+// The ASSERT macro, which does the actual assertion checking. Typically, this\r
+// will be for procedure arguments.\r
+//\r
+//*****************************************************************************\r
+#ifdef DEBUG\r
+#define ASSERT(expr) { \\r
+ if(!(expr)) \\r
+ { \\r
+ __error__(__FILE__, __LINE__); \\r
+ } \\r
+ }\r
+#else\r
+#define ASSERT(expr)\r
+#endif\r
+\r
+#endif // __DEBUG_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// gpio.h - Defines and Macros for GPIO API.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 523 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __GPIO_H__\r
+#define __GPIO_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// The following values define the bit field for the ucPins argument to several\r
+// of the APIs.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_PIN_0 0x00000001 // GPIO pin 0\r
+#define GPIO_PIN_1 0x00000002 // GPIO pin 1\r
+#define GPIO_PIN_2 0x00000004 // GPIO pin 2\r
+#define GPIO_PIN_3 0x00000008 // GPIO pin 3\r
+#define GPIO_PIN_4 0x00000010 // GPIO pin 4\r
+#define GPIO_PIN_5 0x00000020 // GPIO pin 5\r
+#define GPIO_PIN_6 0x00000040 // GPIO pin 6\r
+#define GPIO_PIN_7 0x00000080 // GPIO pin 7\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and\r
+// returned from GPIODirModeGet.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input\r
+#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output\r
+#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and\r
+// returned from GPIOIntTypeGet.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge\r
+#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge\r
+#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges\r
+#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level\r
+#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter,\r
+// and returned by GPIOPadConfigGet in the *pulStrength parameter.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength\r
+#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength\r
+#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength\r
+#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter,\r
+// and returned by GPIOPadConfigGet in the *pulPadType parameter.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull\r
+#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up\r
+#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down\r
+#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain\r
+#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up\r
+#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down\r
+#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins,\r
+ unsigned long ulPinIO);\r
+extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin);\r
+extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins,\r
+ unsigned long ulIntType);\r
+extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin);\r
+extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins,\r
+ unsigned long ulStrength,\r
+ unsigned long ulPadType);\r
+extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin,\r
+ unsigned long *pulStrength,\r
+ unsigned long *pulPadType);\r
+extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins);\r
+extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked);\r
+extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPortIntRegister(unsigned long ulPort,\r
+ void (*pfIntHandler)(void));\r
+extern void GPIOPortIntUnregister(unsigned long ulPort);\r
+extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins,\r
+ unsigned char ucVal);\r
+extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __GPIO_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_ints.h - Macros that define the interrupt assignment on Stellaris.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 523 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_INTS_H__\r
+#define __HW_INTS_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the fault assignments.\r
+//\r
+//*****************************************************************************\r
+#define FAULT_NMI 2 // NMI fault\r
+#define FAULT_HARD 3 // Hard fault\r
+#define FAULT_MPU 4 // MPU fault\r
+#define FAULT_BUS 5 // Bus fault\r
+#define FAULT_USAGE 6 // Usage fault\r
+#define FAULT_SVCALL 11 // SVCall\r
+#define FAULT_DEBUG 12 // Debug monitor\r
+#define FAULT_PENDSV 14 // PendSV\r
+#define FAULT_SYSTICK 15 // System Tick\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the interrupt assignments.\r
+//\r
+//*****************************************************************************\r
+#define INT_GPIOA 16 // GPIO Port A\r
+#define INT_GPIOB 17 // GPIO Port B\r
+#define INT_GPIOC 18 // GPIO Port C\r
+#define INT_UART0 21 // UART0 Rx and Tx\r
+#define INT_SSI 23 // SSI Rx and Tx\r
+#define INT_I2C 24 // I2C Master and Slave\r
+#define INT_WATCHDOG 34 // Watchdog timer\r
+#define INT_TIMER0A 35 // Timer 0 subtimer A\r
+#define INT_TIMER0B 36 // Timer 0 subtimer B\r
+#define INT_TIMER1A 37 // Timer 1 subtimer A\r
+#define INT_TIMER1B 38 // Timer 1 subtimer B\r
+#define INT_COMP0 41 // Analog Comparator 0\r
+#define INT_COMP1 42 // Analog Comparator 1\r
+#define INT_SYSCTL 44 // System Control (PLL, OSC, BO)\r
+#define INT_FLASH 45 // FLASH Control\r
+\r
+//*****************************************************************************\r
+//\r
+// The total number of interrupts.\r
+//\r
+//*****************************************************************************\r
+#define NUM_INTERRUPTS 46\r
+\r
+//*****************************************************************************\r
+//\r
+// The total number of priority levels.\r
+//\r
+//*****************************************************************************\r
+#define NUM_PRIORITY 8\r
+#define NUM_PRIORITY_BITS 3\r
+\r
+#endif // __HW_INTS_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_memmap.h - Macros defining the memory map of Stellaris.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 523 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_MEMMAP_H__\r
+#define __HW_MEMMAP_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the base address of the memories and peripherals.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_BASE 0x00000000 // FLASH memory\r
+#define SRAM_BASE 0x20000000 // SRAM memory\r
+#define WATCHDOG_BASE 0x40000000 // Watchdog\r
+#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A\r
+#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B\r
+#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C\r
+#define SSI_BASE 0x40008000 // SSI\r
+#define UART0_BASE 0x4000C000 // UART0\r
+#define I2C_MASTER_BASE 0x40020000 // I2C Master\r
+#define I2C_SLAVE_BASE 0x40020800 // I2C Slave\r
+#define TIMER0_BASE 0x40030000 // Timer0\r
+#define TIMER1_BASE 0x40031000 // Timer1\r
+#define COMP_BASE 0x4003C000 // Analog comparators\r
+#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller\r
+#define SYSCTL_BASE 0x400FE000 // System Control\r
+#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell\r
+#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace\r
+#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint\r
+#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl\r
+#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit\r
+\r
+#endif // __HW_MEMMAP_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_nvic.h - Macros used when accessing the NVIC hardware.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 523 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_NVIC_H__\r
+#define __HW_NVIC_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the addresses of the NVIC registers.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg.\r
+#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status Reg.\r
+#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register\r
+#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register\r
+#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg.\r
+#define NVIC_EN0 0xE000E100 // IRQ 0 to 31 Set Enable Register\r
+#define NVIC_DIS0 0xE000E180 // IRQ 0 to 31 Clear Enable Reg.\r
+#define NVIC_PEND0 0xE000E200 // IRQ 0 to 31 Set Pending Register\r
+#define NVIC_UNPEND0 0xE000E280 // IRQ 0 to 31 Clear Pending Reg.\r
+#define NVIC_ACTIVE0 0xE000E300 // IRQ 0 to 31 Active Register\r
+#define NVIC_PRI0 0xE000E400 // IRQ 0 to 3 Priority Register\r
+#define NVIC_PRI1 0xE000E404 // IRQ 4 to 7 Priority Register\r
+#define NVIC_PRI2 0xE000E408 // IRQ 8 to 11 Priority Register\r
+#define NVIC_PRI3 0xE000E40C // IRQ 12 to 15 Priority Register\r
+#define NVIC_PRI4 0xE000E410 // IRQ 16 to 19 Priority Register\r
+#define NVIC_PRI5 0xE000E414 // IRQ 20 to 23 Priority Register\r
+#define NVIC_PRI6 0xE000E418 // IRQ 24 to 27 Priority Register\r
+#define NVIC_PRI7 0xE000E41C // IRQ 28 to 31 Priority Register\r
+#define NVIC_CPUID 0xE000ED00 // CPUID Base Register\r
+#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control State Register\r
+#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset Register\r
+#define NVIC_APINT 0xE000ED0C // App. Int & Reset Control Reg.\r
+#define NVIC_SYS_CTRL 0xE000ED10 // System Control Register\r
+#define NVIC_CFG_CTRL 0xE000ED14 // Configuration Control Register\r
+#define NVIC_SYS_PRI1 0xE000ED18 // Sys. Handlers 4 to 7 Priority\r
+#define NVIC_SYS_PRI2 0xE000ED1C // Sys. Handlers 8 to 11 Priority\r
+#define NVIC_SYS_PRI3 0xE000ED20 // Sys. Handlers 12 to 15 Priority\r
+#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State\r
+#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status Reg.\r
+#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status Register\r
+#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register\r
+#define NVIC_MM_ADDR 0xE000ED34 // Mem Manage Address Register\r
+#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address Register\r
+#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type Register\r
+#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control Register\r
+#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number Register\r
+#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address Register\r
+#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute & Size Reg.\r
+#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg.\r
+#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select\r
+#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data\r
+#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control\r
+#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt Reg.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_INT_TYPE register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32)\r
+#define NVIC_INT_TYPE_LINES_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ST_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ST_CTRL_COUNT 0x00010000 // Count flag\r
+#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source\r
+#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt enable\r
+#define NVIC_ST_CTRL_ENABLE 0x00000001 // Counter mode\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ST_RELOAD register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ST_RELOAD_M 0x00FFFFFF // Counter load value\r
+#define NVIC_ST_RELOAD_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ST_CURRENT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ST_CURRENT_M 0x00FFFFFF // Counter current value\r
+#define NVIC_ST_CURRENT_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ST_CAL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock\r
+#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew\r
+#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value\r
+#define NVIC_ST_CAL_ONEMS_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_EN0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable\r
+#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable\r
+#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable\r
+#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable\r
+#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable\r
+#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable\r
+#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable\r
+#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable\r
+#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable\r
+#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable\r
+#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable\r
+#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable\r
+#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable\r
+#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable\r
+#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable\r
+#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable\r
+#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable\r
+#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable\r
+#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable\r
+#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable\r
+#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable\r
+#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable\r
+#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable\r
+#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable\r
+#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable\r
+#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable\r
+#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable\r
+#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable\r
+#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable\r
+#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable\r
+#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable\r
+#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DIS0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable\r
+#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable\r
+#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable\r
+#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable\r
+#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable\r
+#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable\r
+#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable\r
+#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable\r
+#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable\r
+#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable\r
+#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable\r
+#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable\r
+#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable\r
+#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable\r
+#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable\r
+#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable\r
+#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable\r
+#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable\r
+#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable\r
+#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable\r
+#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable\r
+#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable\r
+#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable\r
+#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable\r
+#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable\r
+#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable\r
+#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable\r
+#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable\r
+#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable\r
+#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable\r
+#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable\r
+#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PEND0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend\r
+#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend\r
+#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend\r
+#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend\r
+#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend\r
+#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend\r
+#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend\r
+#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend\r
+#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend\r
+#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend\r
+#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend\r
+#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend\r
+#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend\r
+#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend\r
+#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend\r
+#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend\r
+#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend\r
+#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend\r
+#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend\r
+#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend\r
+#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend\r
+#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend\r
+#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend\r
+#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend\r
+#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend\r
+#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend\r
+#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend\r
+#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend\r
+#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend\r
+#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend\r
+#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend\r
+#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_UNPEND0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend\r
+#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend\r
+#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend\r
+#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend\r
+#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend\r
+#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend\r
+#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend\r
+#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend\r
+#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend\r
+#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend\r
+#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend\r
+#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend\r
+#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend\r
+#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend\r
+#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend\r
+#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend\r
+#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend\r
+#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend\r
+#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend\r
+#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend\r
+#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend\r
+#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend\r
+#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend\r
+#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend\r
+#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend\r
+#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend\r
+#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend\r
+#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend\r
+#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend\r
+#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend\r
+#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend\r
+#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ACTIVE0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active\r
+#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active\r
+#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active\r
+#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active\r
+#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active\r
+#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active\r
+#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active\r
+#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active\r
+#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active\r
+#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active\r
+#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active\r
+#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active\r
+#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active\r
+#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active\r
+#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active\r
+#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active\r
+#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active\r
+#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active\r
+#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active\r
+#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active\r
+#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active\r
+#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active\r
+#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active\r
+#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active\r
+#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active\r
+#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active\r
+#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active\r
+#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active\r
+#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active\r
+#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active\r
+#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active\r
+#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI0_INT3_M 0xFF000000 // Interrupt 3 priority mask\r
+#define NVIC_PRI0_INT2_M 0x00FF0000 // Interrupt 2 priority mask\r
+#define NVIC_PRI0_INT1_M 0x0000FF00 // Interrupt 1 priority mask\r
+#define NVIC_PRI0_INT0_M 0x000000FF // Interrupt 0 priority mask\r
+#define NVIC_PRI0_INT3_S 24\r
+#define NVIC_PRI0_INT2_S 16\r
+#define NVIC_PRI0_INT1_S 8\r
+#define NVIC_PRI0_INT0_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI1 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI1_INT7_M 0xFF000000 // Interrupt 7 priority mask\r
+#define NVIC_PRI1_INT6_M 0x00FF0000 // Interrupt 6 priority mask\r
+#define NVIC_PRI1_INT5_M 0x0000FF00 // Interrupt 5 priority mask\r
+#define NVIC_PRI1_INT4_M 0x000000FF // Interrupt 4 priority mask\r
+#define NVIC_PRI1_INT7_S 24\r
+#define NVIC_PRI1_INT6_S 16\r
+#define NVIC_PRI1_INT5_S 8\r
+#define NVIC_PRI1_INT4_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI2 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI2_INT11_M 0xFF000000 // Interrupt 11 priority mask\r
+#define NVIC_PRI2_INT10_M 0x00FF0000 // Interrupt 10 priority mask\r
+#define NVIC_PRI2_INT9_M 0x0000FF00 // Interrupt 9 priority mask\r
+#define NVIC_PRI2_INT8_M 0x000000FF // Interrupt 8 priority mask\r
+#define NVIC_PRI2_INT11_S 24\r
+#define NVIC_PRI2_INT10_S 16\r
+#define NVIC_PRI2_INT9_S 8\r
+#define NVIC_PRI2_INT8_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI3 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI3_INT15_M 0xFF000000 // Interrupt 15 priority mask\r
+#define NVIC_PRI3_INT14_M 0x00FF0000 // Interrupt 14 priority mask\r
+#define NVIC_PRI3_INT13_M 0x0000FF00 // Interrupt 13 priority mask\r
+#define NVIC_PRI3_INT12_M 0x000000FF // Interrupt 12 priority mask\r
+#define NVIC_PRI3_INT15_S 24\r
+#define NVIC_PRI3_INT14_S 16\r
+#define NVIC_PRI3_INT13_S 8\r
+#define NVIC_PRI3_INT12_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI4 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI4_INT19_M 0xFF000000 // Interrupt 19 priority mask\r
+#define NVIC_PRI4_INT18_M 0x00FF0000 // Interrupt 18 priority mask\r
+#define NVIC_PRI4_INT17_M 0x0000FF00 // Interrupt 17 priority mask\r
+#define NVIC_PRI4_INT16_M 0x000000FF // Interrupt 16 priority mask\r
+#define NVIC_PRI4_INT19_S 24\r
+#define NVIC_PRI4_INT18_S 16\r
+#define NVIC_PRI4_INT17_S 8\r
+#define NVIC_PRI4_INT16_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI5 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI5_INT23_M 0xFF000000 // Interrupt 23 priority mask\r
+#define NVIC_PRI5_INT22_M 0x00FF0000 // Interrupt 22 priority mask\r
+#define NVIC_PRI5_INT21_M 0x0000FF00 // Interrupt 21 priority mask\r
+#define NVIC_PRI5_INT20_M 0x000000FF // Interrupt 20 priority mask\r
+#define NVIC_PRI5_INT23_S 24\r
+#define NVIC_PRI5_INT22_S 16\r
+#define NVIC_PRI5_INT21_S 8\r
+#define NVIC_PRI5_INT20_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI6 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI6_INT27_M 0xFF000000 // Interrupt 27 priority mask\r
+#define NVIC_PRI6_INT26_M 0x00FF0000 // Interrupt 26 priority mask\r
+#define NVIC_PRI6_INT25_M 0x0000FF00 // Interrupt 25 priority mask\r
+#define NVIC_PRI6_INT24_M 0x000000FF // Interrupt 24 priority mask\r
+#define NVIC_PRI6_INT27_S 24\r
+#define NVIC_PRI6_INT26_S 16\r
+#define NVIC_PRI6_INT25_S 8\r
+#define NVIC_PRI6_INT24_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI7 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI7_INT31_M 0xFF000000 // Interrupt 31 priority mask\r
+#define NVIC_PRI7_INT30_M 0x00FF0000 // Interrupt 30 priority mask\r
+#define NVIC_PRI7_INT29_M 0x0000FF00 // Interrupt 29 priority mask\r
+#define NVIC_PRI7_INT28_M 0x000000FF // Interrupt 28 priority mask\r
+#define NVIC_PRI7_INT31_S 24\r
+#define NVIC_PRI7_INT30_S 16\r
+#define NVIC_PRI7_INT29_S 8\r
+#define NVIC_PRI7_INT28_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_CPUID register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer\r
+#define NVIC_CPUID_VAR_M 0x00F00000 // Variant\r
+#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Processor part number\r
+#define NVIC_CPUID_REV_M 0x0000000F // Revision\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_INT_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_INT_CTRL_NMI_SET 0x80000000 // Pend a NMI\r
+#define NVIC_INT_CTRL_PEND_SV 0x10000000 // Pend a PendSV\r
+#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // Unpend a PendSV\r
+#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug interrupt handling\r
+#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Debug interrupt pending\r
+#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 // Highest pending exception\r
+#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to base\r
+#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF // Current active exception\r
+#define NVIC_INT_CTRL_VEC_PEN_S 12\r
+#define NVIC_INT_CTRL_VEC_ACT_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_VTABLE register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_VTABLE_BASE 0x20000000 // Vector table base\r
+#define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 // Vector table offset\r
+#define NVIC_VTABLE_OFFSET_S 8\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_APINT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Vector key mask\r
+#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key\r
+#define NVIC_APINT_ENDIANESS 0x00008000 // Data endianess\r
+#define NVIC_APINT_PRIGROUP_M 0x00000700 // Priority group\r
+#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split\r
+#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split\r
+#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split\r
+#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split\r
+#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split\r
+#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split\r
+#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split\r
+#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split\r
+#define NVIC_APINT_SYSRESETREQ 0x00000004 // System reset request\r
+#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear active NMI/fault info\r
+#define NVIC_APINT_VECT_RESET 0x00000001 // System reset\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SYS_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wakeup on pend\r
+#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep sleep enable\r
+#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR exit\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_CFG_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault\r
+#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on divide by 0\r
+#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on unaligned access\r
+#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 // Allow deep interrupt trigger\r
+#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow main interrupt trigger\r
+#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread state control\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SYS_PRI1 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SYS_PRI1_RES_M 0xFF000000 // Priority of reserved handler\r
+#define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 // Priority of usage fault handler\r
+#define NVIC_SYS_PRI1_BUS_M 0x0000FF00 // Priority of bus fault handler\r
+#define NVIC_SYS_PRI1_MEM_M 0x000000FF // Priority of mem manage handler\r
+#define NVIC_SYS_PRI1_USAGE_S 16\r
+#define NVIC_SYS_PRI1_BUS_S 8\r
+#define NVIC_SYS_PRI1_MEM_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SYS_PRI2 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SYS_PRI2_SVC_M 0xFF000000 // Priority of SVCall handler\r
+#define NVIC_SYS_PRI2_RES_M 0x00FFFFFF // Priority of reserved handlers\r
+#define NVIC_SYS_PRI2_SVC_S 24\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SYS_PRI3 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SYS_PRI3_TICK_M 0xFF000000 // Priority of Sys Tick handler\r
+#define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 // Priority of PendSV handler\r
+#define NVIC_SYS_PRI3_RES_M 0x0000FF00 // Priority of reserved handler\r
+#define NVIC_SYS_PRI3_DEBUG_M 0x000000FF // Priority of debug handler\r
+#define NVIC_SYS_PRI3_TICK_S 24\r
+#define NVIC_SYS_PRI3_PENDSV_S 16\r
+#define NVIC_SYS_PRI3_DEBUG_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SYS_HND_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage fault enable\r
+#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus fault enable\r
+#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Mem manage fault enable\r
+#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVCall is pended\r
+#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus fault is pended\r
+#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // Sys tick is active\r
+#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV is active\r
+#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Monitor is active\r
+#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVCall is active\r
+#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage fault is active\r
+#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus fault is active\r
+#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Mem manage is active\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_FAULT_STAT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide by zero fault\r
+#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned access fault\r
+#define NVIC_FAULT_STAT_NOCP 0x00080000 // No coprocessor fault\r
+#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC fault\r
+#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid state fault\r
+#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined instruction fault\r
+#define NVIC_FAULT_STAT_BFARV 0x00008000 // BFAR is valid\r
+#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack bus fault\r
+#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack bus fault\r
+#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise data bus error\r
+#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise data bus error\r
+#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction bus fault\r
+#define NVIC_FAULT_STAT_MMARV 0x00000080 // MMAR is valid\r
+#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack access violation\r
+#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack access violation\r
+#define NVIC_FAULT_STAT_DERR 0x00000002 // Data access violation\r
+#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction access violation\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_HFAULT_STAT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug event\r
+#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Cannot execute fault handler\r
+#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector table read fault\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DEBUG_STAT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted\r
+#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch\r
+#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match\r
+#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction\r
+#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MM_ADDR register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MM_ADDR_M 0xFFFFFFFF // Data fault address\r
+#define NVIC_MM_ADDR_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_FAULT_ADDR register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Data bus fault address\r
+#define NVIC_FAULT_ADDR_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_EXC_STACK register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_EXC_STACK_DEEP 0x00000001 // Exception stack\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_EXC_NUM register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_EXC_NUM_M 0x000003FF // Exception number\r
+#define NVIC_EXC_NUM_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_COPRO register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_COPRO_15_M 0xC0000000 // Coprocessor 15 access mask\r
+#define NVIC_COPRO_15_DENIED 0x00000000 // Coprocessor 15 access denied\r
+#define NVIC_COPRO_15_PRIV 0x40000000 // Coprocessor 15 privileged addess\r
+#define NVIC_COPRO_15_FULL 0xC0000000 // Coprocessor 15 full access\r
+#define NVIC_COPRO_14_M 0x30000000 // Coprocessor 14 access mask\r
+#define NVIC_COPRO_14_DENIED 0x00000000 // Coprocessor 14 access denied\r
+#define NVIC_COPRO_14_PRIV 0x10000000 // Coprocessor 14 privileged addess\r
+#define NVIC_COPRO_14_FULL 0x30000000 // Coprocessor 14 full access\r
+#define NVIC_COPRO_13_M 0x0C000000 // Coprocessor 13 access mask\r
+#define NVIC_COPRO_13_DENIED 0x00000000 // Coprocessor 13 access denied\r
+#define NVIC_COPRO_13_PRIV 0x04000000 // Coprocessor 13 privileged addess\r
+#define NVIC_COPRO_13_FULL 0x0C000000 // Coprocessor 13 full access\r
+#define NVIC_COPRO_12_M 0x03000000 // Coprocessor 12 access mask\r
+#define NVIC_COPRO_12_DENIED 0x00000000 // Coprocessor 12 access denied\r
+#define NVIC_COPRO_12_PRIV 0x01000000 // Coprocessor 12 privileged addess\r
+#define NVIC_COPRO_12_FULL 0x03000000 // Coprocessor 12 full access\r
+#define NVIC_COPRO_11_M 0x00C00000 // Coprocessor 11 access mask\r
+#define NVIC_COPRO_11_DENIED 0x00000000 // Coprocessor 11 access denied\r
+#define NVIC_COPRO_11_PRIV 0x00400000 // Coprocessor 11 privileged addess\r
+#define NVIC_COPRO_11_FULL 0x00C00000 // Coprocessor 11 full access\r
+#define NVIC_COPRO_10_M 0x00300000 // Coprocessor 10 access mask\r
+#define NVIC_COPRO_10_DENIED 0x00000000 // Coprocessor 10 access denied\r
+#define NVIC_COPRO_10_PRIV 0x00100000 // Coprocessor 10 privileged addess\r
+#define NVIC_COPRO_10_FULL 0x00300000 // Coprocessor 10 full access\r
+#define NVIC_COPRO_9_M 0x000C0000 // Coprocessor 9 access mask\r
+#define NVIC_COPRO_9_DENIED 0x00000000 // Coprocessor 9 access denied\r
+#define NVIC_COPRO_9_PRIV 0x00040000 // Coprocessor 9 privileged addess\r
+#define NVIC_COPRO_9_FULL 0x000C0000 // Coprocessor 9 full access\r
+#define NVIC_COPRO_8_M 0x00030000 // Coprocessor 8 access mask\r
+#define NVIC_COPRO_8_DENIED 0x00000000 // Coprocessor 8 access denied\r
+#define NVIC_COPRO_8_PRIV 0x00010000 // Coprocessor 8 privileged addess\r
+#define NVIC_COPRO_8_FULL 0x00030000 // Coprocessor 8 full access\r
+#define NVIC_COPRO_7_M 0x0000C000 // Coprocessor 7 access mask\r
+#define NVIC_COPRO_7_DENIED 0x00000000 // Coprocessor 7 access denied\r
+#define NVIC_COPRO_7_PRIV 0x00004000 // Coprocessor 7 privileged addess\r
+#define NVIC_COPRO_7_FULL 0x0000C000 // Coprocessor 7 full access\r
+#define NVIC_COPRO_6_M 0x00003000 // Coprocessor 6 access mask\r
+#define NVIC_COPRO_6_DENIED 0x00000000 // Coprocessor 6 access denied\r
+#define NVIC_COPRO_6_PRIV 0x00001000 // Coprocessor 6 privileged addess\r
+#define NVIC_COPRO_6_FULL 0x00003000 // Coprocessor 6 full access\r
+#define NVIC_COPRO_5_M 0x00000C00 // Coprocessor 5 access mask\r
+#define NVIC_COPRO_5_DENIED 0x00000000 // Coprocessor 5 access denied\r
+#define NVIC_COPRO_5_PRIV 0x00000400 // Coprocessor 5 privileged addess\r
+#define NVIC_COPRO_5_FULL 0x00000C00 // Coprocessor 5 full access\r
+#define NVIC_COPRO_4_M 0x00000300 // Coprocessor 4 access mask\r
+#define NVIC_COPRO_4_DENIED 0x00000000 // Coprocessor 4 access denied\r
+#define NVIC_COPRO_4_PRIV 0x00000100 // Coprocessor 4 privileged addess\r
+#define NVIC_COPRO_4_FULL 0x00000300 // Coprocessor 4 full access\r
+#define NVIC_COPRO_3_M 0x000000C0 // Coprocessor 3 access mask\r
+#define NVIC_COPRO_3_DENIED 0x00000000 // Coprocessor 3 access denied\r
+#define NVIC_COPRO_3_PRIV 0x00000040 // Coprocessor 3 privileged addess\r
+#define NVIC_COPRO_3_FULL 0x000000C0 // Coprocessor 3 full access\r
+#define NVIC_COPRO_2_M 0x00000030 // Coprocessor 2 access mask\r
+#define NVIC_COPRO_2_DENIED 0x00000000 // Coprocessor 2 access denied\r
+#define NVIC_COPRO_2_PRIV 0x00000010 // Coprocessor 2 privileged addess\r
+#define NVIC_COPRO_2_FULL 0x00000030 // Coprocessor 2 full access\r
+#define NVIC_COPRO_1_M 0x0000000C // Coprocessor 1 access mask\r
+#define NVIC_COPRO_1_DENIED 0x00000000 // Coprocessor 1 access denied\r
+#define NVIC_COPRO_1_PRIV 0x00000004 // Coprocessor 1 privileged addess\r
+#define NVIC_COPRO_1_FULL 0x0000000C // Coprocessor 1 full access\r
+#define NVIC_COPRO_0_M 0x00000003 // Coprocessor 0 access mask\r
+#define NVIC_COPRO_0_DENIED 0x00000000 // Coprocessor 0 access denied\r
+#define NVIC_COPRO_0_PRIV 0x00000001 // Coprocessor 0 privileged addess\r
+#define NVIC_COPRO_0_FULL 0x00000003 // Coprocessor 0 full access\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MPU_TYPE register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I regions\r
+#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D regions\r
+#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or unified MPU\r
+#define NVIC_MPU_TYPE_IREGION_S 16\r
+#define NVIC_MPU_TYPE_DREGION_S 8\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MPU_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU enabled during faults\r
+#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MPU_NUMBER register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MPU_NUMBER_M 0x000000FF // MPU region to access\r
+#define NVIC_MPU_NUMBER_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MPU_BASE register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MPU_BASE_ADDR_M 0xFFFFFF00 // Base address\r
+#define NVIC_MPU_BASE_VALID 0x00000010 // Region number valid\r
+#define NVIC_MPU_BASE_REGION_M 0x0000000F // Region number\r
+#define NVIC_MPU_BASE_ADDR_S 8\r
+#define NVIC_MPU_BASE_REGION_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MPU_ATTR register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MPU_ATTR_ATTRS 0xFFFF0000 // Attributes\r
+#define NVIC_MPU_ATTR_SRD 0x0000FF00 // Sub-region disable\r
+#define NVIC_MPU_ATTR_SZENABLE 0x000000FF // Region size\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DBG_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask\r
+#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key\r
+#define NVIC_DBG_CTRL_MON_PEND 0x00008000 // Pend the monitor\r
+#define NVIC_DBG_CTRL_MON_REQ 0x00004000 // Monitor request\r
+#define NVIC_DBG_CTRL_MON_EN 0x00002000 // Debug monitor enable\r
+#define NVIC_DBG_CTRL_MONSTEP 0x00001000 // Monitor step the core\r
+#define NVIC_DBG_CTRL_S_SLEEP 0x00000400 // Core is sleeping\r
+#define NVIC_DBG_CTRL_S_HALT 0x00000200 // Core status on halt\r
+#define NVIC_DBG_CTRL_S_REGRDY 0x00000100 // Register read/write available\r
+#define NVIC_DBG_CTRL_S_LOCKUP 0x00000080 // Core is locked up\r
+#define NVIC_DBG_CTRL_C_RESET 0x00000010 // Reset the core\r
+#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping\r
+#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core\r
+#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core\r
+#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DBG_XFER register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read\r
+#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register\r
+#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0\r
+#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1\r
+#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2\r
+#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3\r
+#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4\r
+#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5\r
+#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6\r
+#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7\r
+#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8\r
+#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9\r
+#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10\r
+#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11\r
+#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12\r
+#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13\r
+#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14\r
+#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15\r
+#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register\r
+#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP\r
+#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP\r
+#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP\r
+#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DBG_DATA register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache\r
+#define NVIC_DBG_DATA_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DBG_INT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault\r
+#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors\r
+#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error\r
+#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state\r
+#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check\r
+#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error\r
+#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault\r
+#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status\r
+#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset\r
+#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending\r
+#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SW_TRIG register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SW_TRIG_INTID_M 0x000003FF // Interrupt to trigger\r
+#define NVIC_SW_TRIG_INTID_S 0\r
+\r
+#endif // __HW_NVIC_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_ssi.h - Macros used when accessing the SSI hardware.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 523 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_SSI_H__\r
+#define __HW_SSI_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the SSI registers.\r
+//\r
+//*****************************************************************************\r
+#define SSI_O_CR0 0x00000000 // Control register 0\r
+#define SSI_O_CR1 0x00000004 // Control register 1\r
+#define SSI_O_DR 0x00000008 // Data register\r
+#define SSI_O_SR 0x0000000C // Status register\r
+#define SSI_O_CPSR 0x00000010 // Clock prescale register\r
+#define SSI_O_IM 0x00000014 // Int mask set and clear register\r
+#define SSI_O_RIS 0x00000018 // Raw interrupt register\r
+#define SSI_O_MIS 0x0000001C // Masked interrupt register\r
+#define SSI_O_ICR 0x00000020 // Interrupt clear register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SSI Control register 0.\r
+//\r
+//*****************************************************************************\r
+#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate\r
+#define SSI_CR0_SPH 0x00000080 // SSPCLKOUT phase\r
+#define SSI_CR0_SPO 0x00000040 // SSPCLKOUT polarity\r
+#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask\r
+#define SSI_CR0_FRF_MOTO 0x00000000 // Motorola SPI frame format\r
+#define SSI_CR0_FRF_TI 0x00000010 // TI sync serial frame format\r
+#define SSI_CR0_FRF_NMW 0x00000020 // National Microwire frame format\r
+#define SSI_CR0_DSS 0x0000000F // Data size select\r
+#define SSI_CR0_DSS_4 0x00000003 // 4 bit data\r
+#define SSI_CR0_DSS_5 0x00000004 // 5 bit data\r
+#define SSI_CR0_DSS_6 0x00000005 // 6 bit data\r
+#define SSI_CR0_DSS_7 0x00000006 // 7 bit data\r
+#define SSI_CR0_DSS_8 0x00000007 // 8 bit data\r
+#define SSI_CR0_DSS_9 0x00000008 // 9 bit data\r
+#define SSI_CR0_DSS_10 0x00000009 // 10 bit data\r
+#define SSI_CR0_DSS_11 0x0000000A // 11 bit data\r
+#define SSI_CR0_DSS_12 0x0000000B // 12 bit data\r
+#define SSI_CR0_DSS_13 0x0000000C // 13 bit data\r
+#define SSI_CR0_DSS_14 0x0000000D // 14 bit data\r
+#define SSI_CR0_DSS_15 0x0000000E // 15 bit data\r
+#define SSI_CR0_DSS_16 0x0000000F // 16 bit data\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SSI Control register 1.\r
+//\r
+//*****************************************************************************\r
+#define SSI_CR1_SOD 0x00000008 // Slave mode output disable\r
+#define SSI_CR1_MS 0x00000004 // Master or slave mode select\r
+#define SSI_CR1_SSE 0x00000002 // Sync serial port enable\r
+#define SSI_CR1_LBM 0x00000001 // Loopback mode\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SSI Status register\r
+//\r
+//*****************************************************************************\r
+#define SSI_SR_BSY 0x00000010 // SSI busy\r
+#define SSI_SR_RFF 0x00000008 // RX FIFO full\r
+#define SSI_SR_RNE 0x00000004 // RX FIFO not empty\r
+#define SSI_SR_TNF 0x00000002 // TX FIFO not full\r
+#define SSI_SR_TFE 0x00000001 // TX FIFO empty\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define information concerning the SSI Data register.\r
+//\r
+//*****************************************************************************\r
+#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO\r
+#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the interrupt mask set and clear,\r
+// raw interrupt, masked interrupt, and interrupt clear registers.\r
+//\r
+//*****************************************************************************\r
+#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt\r
+#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt\r
+#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt\r
+#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt\r
+\r
+#endif // __HW_SSI_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_sysctl.h - Macros used when accessing the system control hardware.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 523 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_SYSCTL_H__\r
+#define __HW_SYSCTL_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the system control registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DID0 0x400fe000 // Device identification register 0\r
+#define SYSCTL_DID1 0x400fe004 // Device identification register 1\r
+#define SYSCTL_DC0 0x400fe008 // Device capabilities register 0\r
+#define SYSCTL_DC1 0x400fe010 // Device capabilities register 1\r
+#define SYSCTL_DC2 0x400fe014 // Device capabilities register 2\r
+#define SYSCTL_DC3 0x400fe018 // Device capabilities register 3\r
+#define SYSCTL_DC4 0x400fe01C // Device capabilities register 4\r
+#define SYSCTL_PBORCTL 0x400fe030 // POR/BOR reset control register\r
+#define SYSCTL_LDOPCTL 0x400fe034 // LDO power control register\r
+#define SYSCTL_SRCR0 0x400fe040 // Software reset control reg 0\r
+#define SYSCTL_SRCR1 0x400fe044 // Software reset control reg 1\r
+#define SYSCTL_SRCR2 0x400fe048 // Software reset control reg 2\r
+#define SYSCTL_RIS 0x400fe050 // Raw interrupt status register\r
+#define SYSCTL_IMC 0x400fe054 // Interrupt mask/control register\r
+#define SYSCTL_MISC 0x400fe058 // Interrupt status register\r
+#define SYSCTL_RESC 0x400fe05c // Reset cause register\r
+#define SYSCTL_RCC 0x400fe060 // Run-mode clock config register\r
+#define SYSCTL_PLLCFG 0x400fe064 // PLL configuration register\r
+#define SYSCTL_RCGC0 0x400fe100 // Run-mode clock gating register 0\r
+#define SYSCTL_RCGC1 0x400fe104 // Run-mode clock gating register 1\r
+#define SYSCTL_RCGC2 0x400fe108 // Run-mode clock gating register 2\r
+#define SYSCTL_SCGC0 0x400fe110 // Sleep-mode clock gating reg 0\r
+#define SYSCTL_SCGC1 0x400fe114 // Sleep-mode clock gating reg 1\r
+#define SYSCTL_SCGC2 0x400fe118 // Sleep-mode clock gating reg 2\r
+#define SYSCTL_DCGC0 0x400fe120 // Deep Sleep-mode clock gate reg 0\r
+#define SYSCTL_DCGC1 0x400fe124 // Deep Sleep-mode clock gate reg 1\r
+#define SYSCTL_DCGC2 0x400fe128 // Deep Sleep-mode clock gate reg 2\r
+#define SYSCTL_CLKVCLR 0x400fe150 // Clock verifcation clear register\r
+#define SYSCTL_LDOARST 0x400fe160 // LDO reset control register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DID0 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask\r
+#define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A\r
+#define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B\r
+#define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask\r
+#define SYSCTL_DID0_MIN_0 0x00000000 // Minor revision 0\r
+#define SYSCTL_DID0_MIN_1 0x00000001 // Minor revision 1\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DID1 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask\r
+#define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask\r
+#define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family\r
+#define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask\r
+#define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101\r
+#define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102\r
+#define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask\r
+#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temp range (0..70C)\r
+#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temp range (-40..85C)\r
+#define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask\r
+#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // 28-pin SOIC\r
+#define SYSCTL_DID1_ROHS 0x00000004 // Part is RoHS compliant\r
+#define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask\r
+#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering sample (unqualified)\r
+#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot production (unqualified)\r
+#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully qualified\r
+#define SYSCTL_DID1_PRTNO_SHIFT 16\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DC0 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask\r
+#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2kB of SRAM\r
+#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask\r
+#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8kB of flash\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DC1 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask\r
+#define SYSCTL_DC1_MPU 0x00000080 // Cortex M3 MPU present\r
+#define SYSCTL_DC1_PLL 0x00000010 // PLL present\r
+#define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present\r
+#define SYSCTL_DC1_SWO 0x00000004 // Serial wire output present\r
+#define SYSCTL_DC1_SWD 0x00000002 // Serial wire debug present\r
+#define SYSCTL_DC1_JTAG 0x00000001 // JTAG debug present\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DC2 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC2_COMP1 0x02000000 // Analog comparator 1 present\r
+#define SYSCTL_DC2_COMP0 0x01000000 // Analog comparator 0 present\r
+#define SYSCTL_DC2_TIMER1 0x00020000 // Timer 1 present\r
+#define SYSCTL_DC2_TIMER0 0x00010000 // Timer 0 present\r
+#define SYSCTL_DC2_I2C 0x00001000 // I2C present\r
+#define SYSCTL_DC2_SSI 0x00000010 // SSI present\r
+#define SYSCTL_DC2_UART0 0x00000001 // UART 0 present\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DC3 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC3_32KHZ 0x80000000 // 32kHz pin present\r
+#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 pin present\r
+#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 pin present\r
+#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- pin present\r
+#define SYSCTL_DC3_C0O 0x00000100 // C0o pin present\r
+#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ pin present\r
+#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- pin present\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DC4 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO port C present\r
+#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO port B present\r
+#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO port A present\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_PBORCTL register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC // BOR wait timer\r
+#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR interrupt or reset\r
+#define SYSCTL_PBORCTL_BORWT 0x00000001 // BOR wait and check for noise\r
+#define SYSCTL_PBORCTL_BOR_SH 2\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_LDOPCTL register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_LDOPCTL_MASK 0x0000003F // Voltage adjust mask\r
+#define SYSCTL_LDOPCTL_2_25V 0x00000005 // LDO output of 2.25V\r
+#define SYSCTL_LDOPCTL_2_30V 0x00000004 // LDO output of 2.30V\r
+#define SYSCTL_LDOPCTL_2_35V 0x00000003 // LDO output of 2.35V\r
+#define SYSCTL_LDOPCTL_2_40V 0x00000002 // LDO output of 2.40V\r
+#define SYSCTL_LDOPCTL_2_45V 0x00000001 // LDO output of 2.45V\r
+#define SYSCTL_LDOPCTL_2_50V 0x00000000 // LDO output of 2.50V\r
+#define SYSCTL_LDOPCTL_2_55V 0x0000001F // LDO output of 2.55V\r
+#define SYSCTL_LDOPCTL_2_60V 0x0000001E // LDO output of 2.60V\r
+#define SYSCTL_LDOPCTL_2_65V 0x0000001D // LDO output of 2.65V\r
+#define SYSCTL_LDOPCTL_2_70V 0x0000001C // LDO output of 2.70V\r
+#define SYSCTL_LDOPCTL_2_75V 0x0000001B // LDO output of 2.75V\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_SRCR0, SYSCTL_RCGC0,\r
+// SYSCTL_SCGC0, and SYSCTL_DCGC0 registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_SET0_WDOG 0x00000008 // Watchdog module\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_SRCR1, SYSCTL_RCGC1,\r
+// SYSCTL_SCGC1, and SYSCTL_DCGC1 registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_SET1_COMP1 0x02000000 // Analog comparator module 1\r
+#define SYSCTL_SET1_COMP0 0x01000000 // Analog comparator module 0\r
+#define SYSCTL_SET1_TIMER1 0x00020000 // Timer module 1\r
+#define SYSCTL_SET1_TIMER0 0x00010000 // Timer module 0\r
+#define SYSCTL_SET1_I2C 0x00001000 // I2C module\r
+#define SYSCTL_SET1_SSI 0x00000010 // SSI module\r
+#define SYSCTL_SET1_UART0 0x00000001 // UART module 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_SRCR2, SYSCTL_RCGC2,\r
+// SYSCTL_SCGC2, and SYSCTL_DCGC2 registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_SET2_GPIOC 0x00000004 // GPIO C module\r
+#define SYSCTL_SET2_GPIOB 0x00000002 // GPIO B module\r
+#define SYSCTL_SET2_GPIOA 0x00000001 // GIPO A module\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_RIS, SYSCTL_IMC, and\r
+// SYSCTL_IMS registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt\r
+#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt\r
+#define SYSCTL_INT_BOSC_FAIL 0x00000010 // Boot oscillator failure int\r
+#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int\r
+#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt\r
+#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt\r
+#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_RESC register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_RESC_LDO 0x00000020 // LDO power OK lost reset\r
+#define SYSCTL_RESC_SW 0x00000010 // Software reset\r
+#define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset\r
+#define SYSCTL_RESC_BOR 0x00000004 // Brown-out reset\r
+#define SYSCTL_RESC_POR 0x00000002 // Power on reset\r
+#define SYSCTL_RESC_EXT 0x00000001 // External reset\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_RCC register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_RCC_ACG 0x08000000 // Automatic clock gating\r
+#define SYSCTL_RCC_SYSDIV_MASK 0x07800000 // System clock divider\r
+#define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2\r
+#define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3\r
+#define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4\r
+#define SYSCTL_RCC_SYSDIV_5 0x02000000 // System clock /5\r
+#define SYSCTL_RCC_SYSDIV_6 0x02800000 // System clock /6\r
+#define SYSCTL_RCC_SYSDIV_7 0x03000000 // System clock /7\r
+#define SYSCTL_RCC_SYSDIV_8 0x03800000 // System clock /8\r
+#define SYSCTL_RCC_SYSDIV_9 0x04000000 // System clock /9\r
+#define SYSCTL_RCC_SYSDIV_10 0x04800000 // System clock /10\r
+#define SYSCTL_RCC_SYSDIV_11 0x05000000 // System clock /11\r
+#define SYSCTL_RCC_SYSDIV_12 0x05800000 // System clock /12\r
+#define SYSCTL_RCC_SYSDIV_13 0x06000000 // System clock /13\r
+#define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14\r
+#define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15\r
+#define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16\r
+#define SYSCTL_RCC_USE_SYSDIV 0x00400000 // Use sytem clock divider\r
+#define SYSCTL_RCC_PWRDN 0x00002000 // PLL power down\r
+#define SYSCTL_RCC_OE 0x00001000 // PLL output enable\r
+#define SYSCTL_RCC_BYPASS 0x00000800 // PLL bypass\r
+#define SYSCTL_RCC_PLLVER 0x00000400 // PLL verification timer enable\r
+#define SYSCTL_RCC_XTAL_MASK 0x000003C0 // Crystal attached to main osc\r
+#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // Using a 3.579545MHz crystal\r
+#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 // Using a 3.6864MHz crystal\r
+#define SYSCTL_RCC_XTAL_4MHz 0x00000180 // Using a 4MHz crystal\r
+#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // Using a 4.096MHz crystal\r
+#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // Using a 4.9152MHz crystal\r
+#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // Using a 5MHz crystal\r
+#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // Using a 5.12MHz crystal\r
+#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // Using a 6MHz crystal\r
+#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // Using a 6.144MHz crystal\r
+#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // Using a 7.3728MHz crystal\r
+#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // Using a 8MHz crystal\r
+#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // Using a 8.192MHz crystal\r
+#define SYSCTL_RCC_OSCSRC_MASK 0x00000030 // Oscillator input select\r
+#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // Use the main oscillator\r
+#define SYSCTL_RCC_OSCSRC_BOOT 0x00000010 // Use the boot oscillator\r
+#define SYSCTL_RCC_OSCSRC_BOOT4 0x00000020 // Use the boot oscillator / 4\r
+#define SYSCTL_RCC_BOSCVER 0x00000008 // Boot osc. verification timer en\r
+#define SYSCTL_RCC_MOSCVER 0x00000004 // Main osc. verification timer en\r
+#define SYSCTL_RCC_BOSCDIS 0x00000002 // Boot oscillator disable\r
+#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main oscillator disable\r
+#define SYSCTL_RCC_SYSDIV_SHIFT 23 // Shift to the SYSDIV field\r
+#define SYSCTL_RCC_XTAL_SHIFT 6 // Shift to the XTAL field\r
+#define SYSCTL_RCC_OSCSRC_SHIFT 4 // Shift to the OSCSRC field\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_PLLCFG register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_PLLCFG_OD_MASK 0x0000C000 // Output divider\r
+#define SYSCTL_PLLCFG_OD_1 0x00000000 // Output divider is 1\r
+#define SYSCTL_PLLCFG_OD_2 0x00004000 // Output divider is 2\r
+#define SYSCTL_PLLCFG_OD_4 0x00008000 // Output divider is 4\r
+#define SYSCTL_PLLCFG_F_MASK 0x00003FE0 // PLL multiplier\r
+#define SYSCTL_PLLCFG_R_MASK 0x0000001F // Input predivider\r
+#define SYSCTL_PLLCFG_F_SHIFT 5\r
+#define SYSCTL_PLLCFG_R_SHIFT 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_CLKVCLR register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_CLKVCLR_CLR 0x00000001 // Clear clock verification fault\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_LDOARST register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_LDOARST_ARST 0x00000001 // Allow LDO to reset device\r
+\r
+#endif // __HW_SYSCTL_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_types.h - Common types and macros.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 523 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_TYPES_H__\r
+#define __HW_TYPES_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// Define a boolean type, and values for true and false.\r
+//\r
+//*****************************************************************************\r
+typedef unsigned char tBoolean;\r
+\r
+#ifndef true\r
+#define true 1\r
+#endif\r
+\r
+#ifndef false\r
+#define false 0\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Macros for hardware access, both direct and via the bit-band region.\r
+//\r
+//*****************************************************************************\r
+#define HWREG(x) \\r
+ (*((volatile unsigned long *)(x)))\r
+#define HWREGBITW(x, b) \\r
+ HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \\r
+ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))\r
+#define HWREGBITH(x, b) \\r
+ HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \\r
+ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))\r
+#define HWREGBITB(x, b) \\r
+ HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \\r
+ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))\r
+\r
+#endif // __HW_TYPES_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_uart.h - Macros and defines used when accessing the UART hardware\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 523 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_UART_H__\r
+#define __HW_UART_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// UART Register Offsets.\r
+//\r
+//*****************************************************************************\r
+#define UART_O_DR 0x00000000 // Data Register\r
+#define UART_O_RSR 0x00000004 // Receive Status Register (read)\r
+#define UART_O_ECR 0x00000004 // Error Clear Register (write)\r
+#define UART_O_FR 0x00000018 // Flag Register (read only)\r
+#define UART_O_IBRD 0x00000024 // Integer Baud Rate Divisor Reg\r
+#define UART_O_FBRD 0x00000028 // Fractional Baud Rate Divisor Reg\r
+#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte\r
+#define UART_O_CTL 0x00000030 // Control Register\r
+#define UART_O_IFLS 0x00000034 // Interrupt FIFO Level Select Reg\r
+#define UART_O_IM 0x00000038 // Interrupt Mask Set/Clear Reg\r
+#define UART_O_RIS 0x0000003C // Raw Interrupt Status Register\r
+#define UART_O_MIS 0x00000040 // Masked Interrupt Status Register\r
+#define UART_O_ICR 0x00000044 // Interrupt Clear Register\r
+\r
+//*****************************************************************************\r
+//\r
+// Data Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_DR_OE 0x00000800 // Overrun Error\r
+#define UART_DR_BE 0x00000400 // Break Error\r
+#define UART_DR_PE 0x00000200 // Parity Error\r
+#define UART_DR_FE 0x00000100 // Framing Error\r
+\r
+//*****************************************************************************\r
+//\r
+// Receive Status Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_RSR_OE 0x00000008 // Overrun Error\r
+#define UART_RSR_BE 0x00000004 // Break Error\r
+#define UART_RSR_PE 0x00000002 // Parity Error\r
+#define UART_RSR_FE 0x00000001 // Framing Error\r
+\r
+//*****************************************************************************\r
+//\r
+// Flag Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_FR_RI 0x100 // Ring Indicator\r
+#define UART_FR_TXFE 0x080 // TX FIFO Empty\r
+#define UART_FR_RXFF 0x040 // RX FIFO Full\r
+#define UART_FR_TXFF 0x020 // TX FIFO Full\r
+#define UART_FR_RXFE 0x010 // RX FIFO Empty\r
+#define UART_FR_BUSY 0x008 // UART Busy\r
+\r
+//*****************************************************************************\r
+//\r
+// Line Control Register High bits\r
+//\r
+//*****************************************************************************\r
+#define UART_LCR_H_SPS 0x80 // Stick Parity Select\r
+#define UART_LCR_H_WLEN 0x60 // Word length\r
+#define UART_LCR_H_WLEN_8 0x60 // 8 bit data\r
+#define UART_LCR_H_WLEN_7 0x40 // 7 bit data\r
+#define UART_LCR_H_WLEN_6 0x20 // 6 bit data\r
+#define UART_LCR_H_WLEN_5 0x00 // 5 bit data\r
+#define UART_LCR_H_FEN 0x10 // Enable FIFO\r
+#define UART_LCR_H_STP2 0x08 // Two Stop Bits Select\r
+#define UART_LCR_H_EPS 0x04 // Even Parity Select\r
+#define UART_LCR_H_PEN 0x02 // Parity Enable\r
+#define UART_LCR_H_BRK 0x01 // Send Break\r
+\r
+//*****************************************************************************\r
+//\r
+// Control Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_CTL_CTSEN 0x8000 // CTS Hardware Flow Control\r
+#define UART_CTL_RTSEN 0x4000 // RTS Hardware Flow Control\r
+#define UART_CTL_OUT2 0x2000 // OUT2\r
+#define UART_CTL_OUT1 0x1000 // OUT1\r
+#define UART_CTL_RTS 0x0800 // Request To Send\r
+#define UART_CTL_DTR 0x0400 // Data Terminal Ready\r
+#define UART_CTL_RXE 0x0200 // Receive Enable\r
+#define UART_CTL_TXE 0x0100 // Transmit Enable\r
+#define UART_CTL_LBE 0x0080 // Loopback Enable\r
+#define UART_CTL_IIRLP 0x0004 // IrDA SIR low power mode\r
+#define UART_CTL_SIREN 0x0002 // SIR Enable\r
+#define UART_CTL_UARTEN 0x0001 // UART Enable\r
+\r
+//*****************************************************************************\r
+//\r
+// Interrupt FIFO Level Select Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_IFLS_RX1_8 0x00 // 1/8 Full\r
+#define UART_IFLS_RX2_8 0x10 // 1/4 Full\r
+#define UART_IFLS_RX4_8 0x20 // 1/2 Full\r
+#define UART_IFLS_RX6_8 0x30 // 3/4 Full\r
+#define UART_IFLS_RX7_8 0x40 // 7/8 Full\r
+#define UART_IFLS_TX1_8 0x00 // 1/8 Full\r
+#define UART_IFLS_TX2_8 0x01 // 1/4 Full\r
+#define UART_IFLS_TX4_8 0x02 // 1/2 Full\r
+#define UART_IFLS_TX6_8 0x03 // 3/4 Full\r
+#define UART_IFLS_TX7_8 0x04 // 7/8 Full\r
+\r
+//*****************************************************************************\r
+//\r
+// Interrupt Mask Set/Clear Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_IM_OEIM 0x400 // Overrun Error Interrupt Mask\r
+#define UART_IM_BEIM 0x200 // Break Error Interrupt Mask\r
+#define UART_IM_PEIM 0x100 // Parity Error Interrupt Mask\r
+#define UART_IM_FEIM 0x080 // Framing Error Interrupt Mask\r
+#define UART_IM_RTIM 0x040 // Receive Timeout Interrupt Mask\r
+#define UART_IM_TXIM 0x020 // Transmit Interrupt Mask\r
+#define UART_IM_RXIM 0x010 // Receive Interrupt Mask\r
+#define UART_IM_DSRMIM 0x008 // DSR Interrupt Mask\r
+#define UART_IM_DCDMIM 0x004 // DCD Interrupt Mask\r
+#define UART_IM_CTSMIM 0x002 // CTS Interrupt Mask\r
+#define UART_IM_RIMIM 0x001 // RI Interrupt Mask\r
+\r
+//*****************************************************************************\r
+//\r
+// Raw Interrupt Status Register\r
+//\r
+//*****************************************************************************\r
+#define UART_RIS_OERIS 0x400 // Overrun Error Interrupt Status\r
+#define UART_RIS_BERIS 0x200 // Break Error Interrupt Status\r
+#define UART_RIS_PERIS 0x100 // Parity Error Interrupt Status\r
+#define UART_RIS_FERIS 0x080 // Framing Error Interrupt Status\r
+#define UART_RIS_RTRIS 0x040 // Receive Timeout Interrupt Status\r
+#define UART_RIS_TXRIS 0x020 // Transmit Interrupt Status\r
+#define UART_RIS_RXRIS 0x010 // Receive Interrupt Status\r
+#define UART_RIS_DSRRMIS 0x008 // DSR Interrupt Status\r
+#define UART_RIS_DCDRMIS 0x004 // DCD Interrupt Status\r
+#define UART_RIS_CTSRMIS 0x002 // CTS Interrupt Status\r
+#define UART_RIS_RIRMIS 0x001 // RI Interrupt Status\r
+\r
+//*****************************************************************************\r
+//\r
+// Masked Interrupt Status Register\r
+//\r
+//*****************************************************************************\r
+#define UART_MIS_OEMIS 0x400 // Overrun Error Interrupt Status\r
+#define UART_MIS_BEMIS 0x200 // Break Error Interrupt Status\r
+#define UART_MIS_PEMIS 0x100 // Parity Error Interrupt Status\r
+#define UART_MIS_FEMIS 0x080 // Framing Error Interrupt Status\r
+#define UART_MIS_RTMIS 0x040 // Receive Timeout Interrupt Status\r
+#define UART_MIS_TXMIS 0x020 // Transmit Interrupt Status\r
+#define UART_MIS_RXMIS 0x010 // Receive Interrupt Status\r
+#define UART_MIS_DSRMMIS 0x008 // DSR Interrupt Status\r
+#define UART_MIS_DCDMMIS 0x004 // DCD Interrupt Status\r
+#define UART_MIS_CTSMMIS 0x002 // CTS Interrupt Status\r
+#define UART_MIS_RIMMIS 0x001 // RI Interrupt Status\r
+\r
+//*****************************************************************************\r
+//\r
+// Interrupt Clear Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_ICR_OEIC 0x200 // Overrun Error Interrupt Clear\r
+#define UART_ICR_BEIC 0x200 // Break Error Interrupt Clear\r
+#define UART_ICR_PEIC 0x200 // Parity Error Interrupt Clear\r
+#define UART_ICR_FEIC 0x200 // Framing Error Interrupt Clear\r
+#define UART_ICR_RTIC 0x200 // Receive Timeout Interrupt Clear\r
+#define UART_ICR_TXIC 0x200 // Transmit Interrupt Clear\r
+#define UART_ICR_RXIC 0x200 // Receive Interrupt Clear\r
+#define UART_ICR_DSRMIC 0x200 // DSR Interrupt Clear\r
+#define UART_ICR_DCDMIC 0x200 // DCD Interrupt Clear\r
+#define UART_ICR_CTSMIC 0x200 // CTS Interrupt Clear\r
+#define UART_ICR_RIMIC 0x200 // RI Interrupt Clear\r
+\r
+//*****************************************************************************\r
+//\r
+// DMA Control Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_DMACRDMAONERR 0x04 // Disable DMA On Error\r
+#define UART_DMACRTXDMAE 0x02 // Enable Transmit DMA\r
+#define UART_DMACRRXDMAE 0x01 // Enable Receive DMA\r
+\r
+#define UART_RSR_ANY (UART_RSR_OE | \\r
+ UART_RSR_BE | \\r
+ UART_RSR_PE | \\r
+ UART_RSR_FE)\r
+\r
+//*****************************************************************************\r
+//\r
+// Reset Values for UART Registers.\r
+//\r
+//*****************************************************************************\r
+#define UART_RV_DR 0\r
+#define UART_RV_RSR 0x0\r
+#define UART_RV_ECR 0\r
+#define UART_RV_FR 0x90\r
+#define UART_RV_IBRD 0x0000\r
+#define UART_RV_FBRD 0x00\r
+#define UART_RV_LCR_H 0x00\r
+#define UART_RV_CTL 0x0300\r
+#define UART_RV_IFLS 0x12\r
+#define UART_RV_IM 0x000\r
+#define UART_RV_RIS 0x000\r
+#define UART_RV_MIS 0x000\r
+#define UART_RV_ICR 0x000\r
+\r
+#endif // __HW_UART_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 523 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __INTERRUPT_H__\r
+#define __INTERRUPT_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void IntMasterEnable(void);\r
+extern void IntMasterDisable(void);\r
+extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void));\r
+extern void IntUnregister(unsigned long ulInterrupt);\r
+extern void IntPriorityGroupingSet(unsigned long ulBits);\r
+extern unsigned long IntPriorityGroupingGet(void);\r
+extern void IntPrioritySet(unsigned long ulInterrupt,\r
+ unsigned char ucPriority);\r
+extern long IntPriorityGet(unsigned long ulInterrupt);\r
+extern void IntEnable(unsigned long ulInterrupt);\r
+extern void IntDisable(unsigned long ulInterrupt);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __INTERRUPT_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// pdc.c - Driver for the Peripheral Device Controller (PDC) on the Stellaris\r
+// development board.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 523 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup utilities_api\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+#include "hw_memmap.h"\r
+#include "hw_types.h"\r
+#include "gpio.h"\r
+#include "ssi.h"\r
+#include "sysctl.h"\r
+#include "pdc.h"\r
+\r
+//*****************************************************************************\r
+//\r
+//! Initializes the connection to the PDC.\r
+//!\r
+//! This function will enable clocking to the SSI and GPIO A modules, configure\r
+//! the GPIO pins to be used for an SSI interface, and it will configure the\r
+//! SSI as a 1Mb master device, operating in MOTO mode. It will also enable\r
+//! the SSI module, and will enable the chip select for the PDC on the\r
+//! Stellaris development board.\r
+//!\r
+//! This function is contained in <tt>utils/pdc.c</tt>, with\r
+//! <tt>utils/pdc.h</tt> containing the API definition for use by applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+PDCInit(void)\r
+{\r
+ //\r
+ // Enable the peripherals used to drive the PDC.\r
+ //\r
+ SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI);\r
+ SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);\r
+\r
+ //\r
+ // Configure the appropriate pins to be SSI instead of GPIO.\r
+ //\r
+ GPIODirModeSet(GPIO_PORTA_BASE, SSI_CLK | SSI_TX | SSI_RX,\r
+ GPIO_DIR_MODE_HW);\r
+ GPIODirModeSet(GPIO_PORTA_BASE, SSI_CS, GPIO_DIR_MODE_OUT);\r
+ GPIOPadConfigSet(GPIO_PORTA_BASE, SSI_CLK, GPIO_STRENGTH_4MA,\r
+ GPIO_PIN_TYPE_STD_WPU);\r
+\r
+ //\r
+ // Configure the SSI port.\r
+ //\r
+ SSIConfig(SSI_BASE, SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 1000000, 8);\r
+ SSIEnable(SSI_BASE);\r
+\r
+ //\r
+ // Reset the PDC SSI state machine. The chip select needs to be held low\r
+ // for 100ns; the procedure call overhead more than accounts for this time.\r
+ //\r
+ GPIOPinWrite(GPIO_PORTA_BASE, PDC_CS, 0);\r
+ GPIOPinWrite(GPIO_PORTA_BASE, PDC_CS, PDC_CS);\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Write a PDC register.\r
+//!\r
+//! \param ucAddr specifies the PDC register to write.\r
+//! \param ucData specifies the data to write.\r
+//!\r
+//! This function will perform the SSI transfers required to write a register\r
+//! in the PDC on the Stellaris development board.\r
+//!\r
+//! This function is contained in <tt>utils/pdc.c</tt>, with\r
+//! <tt>utils/pdc.h</tt> containing the API definition for use by applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+PDCWrite(unsigned char ucAddr, unsigned char ucData)\r
+{\r
+ unsigned long ulTemp;\r
+\r
+ //\r
+ // Send address and write command.\r
+ //\r
+ SSIDataPut(SSI_BASE, (ucAddr & 0x0F) | PDC_WR);\r
+\r
+ //\r
+ // Write the data.\r
+ //\r
+ SSIDataPut(SSI_BASE, ucData);\r
+\r
+ //\r
+ // Flush data read during address write.\r
+ //\r
+ SSIDataGet(SSI_BASE, &ulTemp);\r
+\r
+ //\r
+ // Flush data read during data write.\r
+ //\r
+ SSIDataGet(SSI_BASE, &ulTemp);\r
+}\r
+\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// pdc.h - Stellaris development board Peripheral Device Controller definitions\r
+// and prototypes.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 523 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __PDC_H__\r
+#define __PDC_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// The registers within the peripheral device controller.\r
+//\r
+//*****************************************************************************\r
+#define PDC_VER 0x0 // Version register\r
+#define PDC_CSR 0x1 // Command/Status register\r
+#define PDC_DSW 0x4 // DIP Switch register\r
+#define PDC_LED 0x5 // LED register\r
+#define PDC_LCD_CSR 0x6 // LCD Command/Status register\r
+#define PDC_LCD_RAM 0x7 // LCD RAM register\r
+#define PDC_GPXDAT 0x8 // GPIO X Data register\r
+#define PDC_GPXDIR 0x9 // GPIO X Direction register\r
+#define PDC_GPYDAT 0xA // GPIO Y Data register\r
+#define PDC_GPYDIR 0xB // GPIO Y Direction register\r
+#define PDC_GPZDAT 0xC // GPIO Z Data register\r
+#define PDC_GPZDIR 0xD // GPIO Z Direction register\r
+\r
+//*****************************************************************************\r
+//\r
+// Flags indicating a read or write to the peripheral device controller.\r
+//\r
+//*****************************************************************************\r
+#define PDC_RD 0x80 // PDC read command\r
+#define PDC_WR 0x00 // PDC write command\r
+\r
+//*****************************************************************************\r
+//\r
+// LCD panel (Crystalfontz CFAH1602B) commands, RS = 0\r
+//\r
+//*****************************************************************************\r
+#define LCD_CLEAR 0x01 // Clear display (0 fill DDRAM).\r
+#define LCD_HOME 0x02 // Cursor home.\r
+#define LCD_MODE 0x04 // Set entry mode (cursor dir)\r
+#define LCD_ON 0x08 // Set display, cursor, blinking\r
+ // on/off\r
+#define LCD_CUR 0x10 // Cursor, display shift\r
+#define LCD_IF 0x20 // Set interface data length,\r
+ // lines, font\r
+#define LCD_CGADDR 0x40 // Set CGRAM AC address\r
+#define LCD_DDADDR 0x80 // Set DDRAM AC address\r
+\r
+//*****************************************************************************\r
+//\r
+// LCD Status bit\r
+//\r
+//*****************************************************************************\r
+#define LCD_B_BUSY 0x80 // Busy flag.\r
+\r
+//*****************************************************************************\r
+//\r
+// The GPIO port A pin numbers for the various SSI signals.\r
+//\r
+//*****************************************************************************\r
+#define SSI_CS GPIO_PIN_3\r
+#define PDC_CS GPIO_PIN_3\r
+#define SSI_CLK GPIO_PIN_2\r
+#define SSI_TX GPIO_PIN_5\r
+#define SSI_RX GPIO_PIN_4\r
+\r
+//*****************************************************************************\r
+//\r
+// Function Prototypes\r
+//\r
+//*****************************************************************************\r
+extern void PDCInit(void);\r
+extern unsigned char PDCRead(unsigned char ucAddr);\r
+extern void PDCWrite(unsigned char ucAddr, unsigned char ucData);\r
+extern unsigned char PDCDIPRead(void);\r
+extern void PDCLEDWrite(unsigned char ucLED);\r
+extern unsigned char PDCLEDRead(void);\r
+extern void PDCLCDInit(void);\r
+extern void PDCLCDBacklightOn(void);\r
+extern void PDCLCDBacklightOff(void);\r
+extern void PDCLCDClear(void);\r
+extern void PDCLCDCreateChar(unsigned char ucChar, unsigned char *pucData);\r
+extern void PDCLCDSetPos(unsigned char ucX, unsigned char ucY);\r
+extern void PDCLCDWrite(const char *pcStr, unsigned long ulCount);\r
+extern unsigned char PDCGPIODirRead(unsigned char ucIdx);\r
+extern void PDCGPIODirWrite(unsigned char ucIdx, unsigned char ucValue);\r
+extern unsigned char PDCGPIORead(unsigned char ucIdx);\r
+extern void PDCGPIOWrite(unsigned char ucIdx, unsigned char ucValue);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __PDC_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// ssi.h - Prototypes for the Synchronous Serial Interface Driver.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 523 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __SSI_H__\r
+#define __SSI_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear\r
+// as the ulIntFlags parameter, and returned by SSIIntStatus.\r
+//\r
+//*****************************************************************************\r
+#define SSI_TXFF 0x00000008 // TX FIFO half empty or less\r
+#define SSI_RXFF 0x00000004 // RX FIFO half full or less\r
+#define SSI_RXTO 0x00000002 // RX timeout\r
+#define SSI_RXOR 0x00000001 // RX overrun\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to SSIConfig.\r
+//\r
+//*****************************************************************************\r
+#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0\r
+#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1\r
+#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0\r
+#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1\r
+#define SSI_FRF_TI 0x00000010 // TI frame format\r
+#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format\r
+\r
+#define SSI_MODE_MASTER 0x00000000 // SSI master\r
+#define SSI_MODE_SLAVE 0x00000001 // SSI slave\r
+#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void SSIConfig(unsigned long ulBase, unsigned long ulProtocol,\r
+ unsigned long ulMode, unsigned long ulBitRate,\r
+ unsigned long ulDataWidth);\r
+extern void SSIDataGet(unsigned long ulBase, unsigned long *ulData);\r
+extern long SSIDataNonBlockingGet(unsigned long ulBase, unsigned long *ulData);\r
+extern void SSIDataPut(unsigned long ulBase, unsigned long ulData);\r
+extern long SSIDataNonBlockingPut(unsigned long ulBase, unsigned long ulData);\r
+extern void SSIDisable(unsigned long ulBase);\r
+extern void SSIEnable(unsigned long ulBase);\r
+extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void));\r
+extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void SSIIntUnregister(unsigned long ulBase);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __SSI_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// sysctl.h - Prototypes for the system control driver.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 523 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __SYSCTL_H__\r
+#define __SYSCTL_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the\r
+// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(),\r
+// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the\r
+// ulPeripheral parameter. The peripherals in the fourth group (upper nibble\r
+// is 3) can only be used with the SysCtlPeripheralPresent() API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog\r
+#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0\r
+#define SYSCTL_PERIPH_SSI 0x10000010 // SSI\r
+#define SYSCTL_PERIPH_I2C 0x10001000 // I2C\r
+#define SYSCTL_PERIPH_TIMER0 0x10010000 // Timer 0\r
+#define SYSCTL_PERIPH_TIMER1 0x10020000 // Timer 1\r
+#define SYSCTL_PERIPH_COMP0 0x11000000 // Analog comparator 0\r
+#define SYSCTL_PERIPH_COMP1 0x12000000 // Analog comparator 1\r
+#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A\r
+#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B\r
+#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C\r
+#define SYSCTL_PERIPH_PLL 0x30000010 // PLL\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlPinPresent() API\r
+// as the ulPin parameter.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin\r
+#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin\r
+#define SYSCTL_PIN_C0O 0x00000100 // C0o pin\r
+#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin\r
+#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin\r
+#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin\r
+#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlLDOSet() API as\r
+// the ulVoltage value, or returned by the SysCtlLDOGet() API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V\r
+#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V\r
+#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V\r
+#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V\r
+#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V\r
+#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V\r
+#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V\r
+#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V\r
+#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V\r
+#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V\r
+#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlLDOConfigSet() API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset\r
+#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlIntEnable(),\r
+// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask\r
+// by the SysCtlIntStatus() API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt\r
+#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt\r
+#define SYSCTL_INT_BOSC_FAIL 0x00000010 // Boot oscillator failure int\r
+#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int\r
+#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt\r
+#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt\r
+#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlResetCauseClear()\r
+// API or returned by the SysCtlResetCauseGet() API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset\r
+#define SYSCTL_CAUSE_SW 0x00000010 // Software reset\r
+#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset\r
+#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset\r
+#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset\r
+#define SYSCTL_CAUSE_EXT 0x00000001 // External reset\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlBrownOutConfigSet()\r
+// API as the ulConfig parameter.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting\r
+#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlClockSet() API as\r
+// the ulConfig parameter.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1\r
+#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2\r
+#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3\r
+#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4\r
+#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5\r
+#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6\r
+#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7\r
+#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8\r
+#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9\r
+#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10\r
+#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11\r
+#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12\r
+#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13\r
+#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14\r
+#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15\r
+#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16\r
+#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock\r
+#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock\r
+#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz\r
+#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz\r
+#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz\r
+#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz\r
+#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz\r
+#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz\r
+#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz\r
+#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz\r
+#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz\r
+#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz\r
+#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz\r
+#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz\r
+#define SYSCTL_OSC_MAIN 0x00000000 // Oscillator source is main osc\r
+#define SYSCTL_OSC_BOOT 0x00000010 // Oscillator source is boot osc\r
+#define SYSCTL_OSC_BOOT4 0x00000020 // Oscillator source is boot osc /4\r
+#define SYSCTL_BOOT_OSC_DIS 0x00000002 // Disable boot oscillator\r
+#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern unsigned long SysCtlSRAMSizeGet(void);\r
+extern unsigned long SysCtlFlashSizeGet(void);\r
+extern tBoolean SysCtlPinPresent(unsigned long ulPin);\r
+extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralReset(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralEnable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralDisable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralClockGating(tBoolean bEnable);\r
+extern void SysCtlIntRegister(void (*pfnHandler)(void));\r
+extern void SysCtlIntUnregister(void);\r
+extern void SysCtlIntEnable(unsigned long ulInts);\r
+extern void SysCtlIntDisable(unsigned long ulInts);\r
+extern void SysCtlIntClear(unsigned long ulInts);\r
+extern unsigned long SysCtlIntStatus(tBoolean bMasked);\r
+extern void SysCtlLDOSet(unsigned long ulVoltage);\r
+extern unsigned long SysCtlLDOGet(void);\r
+extern void SysCtlLDOConfigSet(unsigned long ulConfig);\r
+extern void SysCtlReset(void);\r
+extern void SysCtlSleep(void);\r
+extern void SysCtlDeepSleep(void);\r
+extern unsigned long SysCtlResetCauseGet(void);\r
+extern void SysCtlResetCauseClear(unsigned long ulCauses);\r
+extern void SysCtlBrownOutConfigSet(unsigned long ulConfig,\r
+ unsigned long ulDelay);\r
+extern void SysCtlClockSet(unsigned long ulConfig);\r
+extern unsigned long SysCtlClockGet(void);\r
+extern void SysCtlBOSCVerificationSet(tBoolean bEnable);\r
+extern void SysCtlMOSCVerificationSet(tBoolean bEnable);\r
+extern void SysCtlPLLVerificationSet(tBoolean bEnable);\r
+extern void SysCtlClkVerificationClear(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __SYSCTL_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// uart.h - Defines and Macros for the UART.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 523 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __UART_H__\r
+#define __UART_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear\r
+// as the ulIntFlags parameter, and returned from UARTIntStatus.\r
+//\r
+//*****************************************************************************\r
+#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask\r
+#define UART_INT_BE 0x200 // Break Error Interrupt Mask\r
+#define UART_INT_PE 0x100 // Parity Error Interrupt Mask\r
+#define UART_INT_FE 0x080 // Framing Error Interrupt Mask\r
+#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask\r
+#define UART_INT_TX 0x020 // Transmit Interrupt Mask\r
+#define UART_INT_RX 0x010 // Receive Interrupt Mask\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to UARTConfigSet as the ulConfig parameter and\r
+// returned by UARTConfigGet in the pulConfig parameter. Additionally, the\r
+// UART_CONFIG_PAR_* subset can be passed to UARTParityModeSet as the ulParity\r
+// parameter, and are returned by UARTParityModeGet.\r
+//\r
+//*****************************************************************************\r
+#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data\r
+#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data\r
+#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data\r
+#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data\r
+#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit\r
+#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits\r
+#define UART_CONFIG_PAR_NONE 0x00000000 // No parity\r
+#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity\r
+#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity\r
+#define UART_CONFIG_PAR_ONE 0x00000086 // Parity bit is one\r
+#define UART_CONFIG_PAR_ZERO 0x00000082 // Parity bit is zero\r
+\r
+//*****************************************************************************\r
+//\r
+// API Function prototypes\r
+//\r
+//*****************************************************************************\r
+extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity);\r
+extern unsigned long UARTParityModeGet(unsigned long ulBase);\r
+extern void UARTConfigSet(unsigned long ulBase, unsigned long ulBaud,\r
+ unsigned long ulConfig);\r
+extern void UARTConfigGet(unsigned long ulBase, unsigned long *pulBaud,\r
+ unsigned long *pulConfig);\r
+extern void UARTEnable(unsigned long ulBase);\r
+extern void UARTDisable(unsigned long ulBase);\r
+extern tBoolean UARTCharsAvail(unsigned long ulBase);\r
+extern tBoolean UARTSpaceAvail(unsigned long ulBase);\r
+extern long UARTCharNonBlockingGet(unsigned long ulBase);\r
+extern long UARTCharGet(unsigned long ulBase);\r
+extern tBoolean UARTCharNonBlockingPut(unsigned long ulBase,\r
+ unsigned char ucData);\r
+extern void UARTCharPut(unsigned long ulBase, unsigned char ucData);\r
+extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState);\r
+extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void));\r
+extern void UARTIntUnregister(unsigned long ulBase);\r
+extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __UART_H__\r
--- /dev/null
+//*****************************************************************************
+//
+// startup.c - Boot code for Stellaris.
+//
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
+//
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's Stellaris Family of microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. Any use in violation
+// of the foregoing restrictions may subject the user to criminal sanctions
+// under applicable laws, as well as to civil liability for the breach of the
+// terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Forward declaration of the default fault handlers.
+//
+//*****************************************************************************
+void ResetISR(void);
+static void NmiSR(void);
+void FaultISR(void);
+extern void xPortPendSVHandler(void);
+extern void xPortSysTickHandler(void);
+extern void vUART_ISR( void );
+
+//*****************************************************************************
+//
+// The entry point for the application.
+//
+//*****************************************************************************
+extern void entry(void);
+
+//*****************************************************************************
+//
+// Reserve space for the system stack.
+//
+//*****************************************************************************
+#ifndef STACK_SIZE
+#define STACK_SIZE 51
+#endif
+static unsigned long pulMainStack[STACK_SIZE];
+
+//*****************************************************************************
+//
+// The minimal vector table for a Cortex M3. Note that the proper constructs
+// must be placed on this to ensure that it ends up at physical address
+// 0x0000.0000.
+//
+//*****************************************************************************
+__attribute__ ((section("vectors")))
+void (* const g_pfnVectors[])(void) =
+{
+ (void (*)(void))((unsigned long)pulMainStack + sizeof(pulMainStack)),
+ ResetISR,
+ NmiSR,
+ FaultISR, //FAULT
+ 0, // The MPU fault handler
+ 0, // The bus fault handler
+ 0, // The usage fault handler
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // SVCall handler
+ 0, // Debug monitor handler
+ 0, // Reserved
+ xPortPendSVHandler, // The PendSV handler
+ xPortSysTickHandler, // The SysTick handler
+ 0, // GPIO Port A
+ 0, // GPIO Port B
+ 0, // GPIO Port C
+ 0, // GPIO Port D
+ 0, // GPIO Port E
+ vUART_ISR // UART0 Rx and Tx
+};
+
+//*****************************************************************************
+//
+// The following are constructs created by the linker, indicating where the
+// the "data" and "bss" segments reside in memory. The initializers for the
+// for the "data" segment resides immediately following the "text" segment.
+//
+//*****************************************************************************
+extern unsigned long _etext;
+extern unsigned long _data;
+extern unsigned long _edata;
+extern unsigned long _bss;
+extern unsigned long _ebss;
+
+//*****************************************************************************
+//
+// This is the code that gets called when the processor first starts execution
+// following a reset event. Only the absolutely necessary set is performed,
+// after which the application supplied entry() routine is called. Any fancy
+// actions (such as making decisions based on the reset cause register, and
+// resetting the bits in that register) are left solely in the hands of the
+// application.
+//
+//*****************************************************************************
+void
+ResetISR(void)
+{
+ unsigned long *pulSrc, *pulDest;
+
+ //
+ // Copy the data segment initializers from flash to SRAM.
+ //
+ pulSrc = &_etext;
+ for(pulDest = &_data; pulDest < &_edata; )
+ {
+ *pulDest++ = *pulSrc++;
+ }
+
+ //
+ // Zero fill the bss segment.
+ //
+ for(pulDest = &_bss; pulDest < &_ebss; )
+ {
+ *pulDest++ = 0;
+ }
+
+ //
+ // Call the application's entry point.
+ //
+ Main();
+}
+
+//*****************************************************************************
+//
+// This is the code that gets called when the processor receives a NMI. This
+// simply enters an infinite loop, preserving the system state for examination
+// by a debugger.
+//
+//*****************************************************************************
+static void
+NmiSR(void)
+{
+ //
+ // Enter an infinite loop.
+ //
+ while(1)
+ {
+ }
+}
+
+//*****************************************************************************
+//
+// This is the code that gets called when the processor receives a fault
+// interrupt. This simply enters an infinite loop, preserving the system state
+// for examination by a debugger.
+//
+//*****************************************************************************
+void
+FaultISR(void)
+{
+ //
+ // Enter an infinite loop.
+ //
+ while(1)
+ {
+ }
+}
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* \r
+ * This demo application creates six co-routines and two tasks (three including \r
+ * the idle task). The co-routines execute as part of the idle task hook.\r
+ *\r
+ * Five of the created co-routines are the standard 'co-routine flash' \r
+ * co-routines contained within the Demo/Common/Minimal/crflash.c file and \r
+ * documented on the FreeRTOS.org WEB site. \r
+ *\r
+ * The 'LCD Task' rotates a string on the LCD, delaying between each character\r
+ * as necessitated by the slow interface, and delaying between each string just\r
+ * long enough to enable the text to be read.\r
+ *\r
+ * The sixth co-routine and final task control the transmission and reception\r
+ * of a string to UART 0. The co-routine periodically sends the first \r
+ * character of the string to the UART, with the UART's TxEnd interrupt being\r
+ * used to transmit the remaining characters. The UART's RxEnd interrupt \r
+ * receives the characters and places them on a queue to be processed by the \r
+ * 'COMs Rx' task. An error is latched should an unexpected character be \r
+ * received, or any character be received out of sequence. \r
+ *\r
+ * A loopback connector is required to ensure that each character transmitted \r
+ * on the UART is also received on the same UART. For test purposes the UART\r
+ * FIFO's are not utalised in order to maximise the interrupt overhead. Also\r
+ * a pseudo random interval is used between the start of each transmission in \r
+ * order that the resultant interrupts are more randomly distributed and \r
+ * therefore more likely to highlight any problems.\r
+ *\r
+ * The flash co-routines control LED's zero to four. LED five is toggled each\r
+ * time the string is transmitted on the UART. LED six is toggled each time\r
+ * the string is CORRECTLY received on the UART. LED seven is latched on should\r
+ * an error be detected in any task or co-routine.\r
+ *\r
+ * In addition the idle task makes repetative calls to \r
+ * prvSetAndCheckRegisters(). This simply loads the general purpose registers \r
+ * with a known value, then checks each register to ensure the held value is \r
+ * still correct. As a low priority task this checking routine is likely to \r
+ * get repeatedly swapped in and out. A register being found to contain an \r
+ * incorrect value is therefore indicative of an error in the task switching \r
+ * mechansim.\r
+ *\r
+ */\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+#include "croutine.h"\r
+\r
+/* Demo application include files. */\r
+#include "partest.h"\r
+#include "crflash.h"\r
+\r
+/* Library include files. */\r
+#include "DriverLib.h"\r
+\r
+/* The time to delay between writing each character to the LCD. */\r
+#define mainCHAR_WRITE_DELAY ( 2 / portTICK_RATE_MS )\r
+\r
+/* The time to delay between writing each string to the LCD. */\r
+#define mainSTRING_WRITE_DELAY ( 400 / portTICK_RATE_MS )\r
+\r
+/* The number of flash co-routines to create. */\r
+#define mainNUM_FLASH_CO_ROUTINES ( 5 )\r
+\r
+/* The length of the queue used to pass received characters to the Comms Rx\r
+task. */\r
+#define mainRX_QUEUE_LEN ( 5 )\r
+\r
+/* The priority of the co-routine used to initiate the transmission of the \r
+string on UART 0. */\r
+#define mainTX_CO_ROUTINE_PRIORITY ( 1 )\r
+\r
+/* Only one co-routine is created so its index is not important. */\r
+#define mainTX_CO_ROUTINE_INDEX ( 0 )\r
+\r
+/* The time between transmissions of the string on UART 0. This is pseudo\r
+random in order to generate a bit or randomness to when the interrupts occur.*/\r
+#define mainMIN_TX_DELAY ( 40 / portTICK_RATE_MS )\r
+#define mainMAX_TX_DELAY ( ( portTickType ) 0x7f )\r
+#define mainOFFSET_TIME ( ( portTickType ) 3 )\r
+\r
+/* The time the Comms Rx task should wait to receive a character. This should\r
+be slightly longer than the time between transmissions. If we do not receive\r
+a character after this time then there must be an error in the transmission or\r
+the timing of the transmission. */\r
+#define mainCOMMS_RX_DELAY ( mainMAX_TX_DELAY + 20 )\r
+\r
+/* The task priorites. */\r
+#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+#define mainCOMMS_RX_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+\r
+/* The LED's toggled by the various tasks. */\r
+#define mainCOMMS_FAIL_LED ( 7 )\r
+#define mainCOMMS_RX_LED ( 6 )\r
+#define mainCOMMS_TX_LED ( 5 )\r
+\r
+/* The baud rate used by the UART comms tasks/co-routine. */\r
+#define mainBAUD_RATE ( 57600 )\r
+\r
+/* FIFO setting for the UART. The FIFO is not used to create a better test. */\r
+#define mainFIFO_SET ( 0x10 )\r
+\r
+/* The string that is transmitted on the UART contains sequentially the \r
+characters from mainFIRST_TX_CHAR to mainLAST_TX_CHAR. */\r
+#define mainFIRST_TX_CHAR '0'\r
+#define mainLAST_TX_CHAR 'z'\r
+\r
+/* Just used to walk through the program memory in order that some random data\r
+can be generated. */\r
+#define mainTOTAL_PROGRAM_MEMORY ( ( unsigned portLONG * ) ( 8 * 1024 ) )\r
+#define mainFIRST_PROGRAM_BYTES ( ( unsigned portLONG * ) 4 )\r
+\r
+/* The error routine that is called if the driver library encounters an error. */\r
+#ifdef DEBUG\r
+void\r
+__error__(char *pcFilename, unsigned long ulLine)\r
+{\r
+}\r
+#endif\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The task that rotates text on the LCD.\r
+ */\r
+static void vLCDTask( void * pvParameters );\r
+\r
+/*\r
+ * The task that receives the characters from UART 0.\r
+ */\r
+static void vCommsRxTask( void * pvParameters );\r
+\r
+/*\r
+ * The co-routine that periodically initiates the transmission of the string on\r
+ * the UART.\r
+ */\r
+static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex );\r
+\r
+/* \r
+ * Writes a string the the LCD.\r
+ */\r
+static void prvWriteString( const portCHAR *pcString );\r
+\r
+/*\r
+ * Initialisation routine for the UART.\r
+ */\r
+static void vSerialInit( void );\r
+\r
+/*\r
+ * Thread safe write to the PDC.\r
+ */\r
+static void prvPDCWrite( portCHAR cAddress, portCHAR cData );\r
+\r
+/*\r
+ * Function to simply set a known value into the general purpose registers\r
+ * then read them back to ensure they remain set correctly. An incorrect value\r
+ * being indicative of an error in the task switching mechanism.\r
+ */\r
+void prvSetAndCheckRegisters( void );\r
+\r
+/*\r
+ * Latch the LED that indicates that an error has occurred. \r
+ */\r
+void vSetErrorLED( void );\r
+\r
+/*\r
+ * Sets up the PLL and ports used by the demo.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Error flag set to pdFAIL if an error is encountered in the tasks/co-routines\r
+defined within this file. */\r
+unsigned portBASE_TYPE uxErrorStatus = pdPASS;\r
+\r
+/* The next character to transmit. */\r
+static portCHAR cNextChar;\r
+\r
+/* The queue used to transmit characters from the interrupt to the Comms Rx\r
+task. */\r
+static xQueueHandle xCommsQueue;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void Main( void )\r
+{\r
+ /* Create the queue used to communicate between the UART ISR and the Comms\r
+ Rx task. */\r
+ xCommsQueue = xQueueCreate( mainRX_QUEUE_LEN, sizeof( portCHAR ) );\r
+\r
+ /* Setup the ports used by the demo and the clock. */\r
+ prvSetupHardware();\r
+\r
+ /* Create the co-routines that flash the LED's. */\r
+ vStartFlashCoRoutines( mainNUM_FLASH_CO_ROUTINES );\r
+\r
+ /* Create the co-routine that initiates the transmission of characters\r
+ on the UART. */\r
+ xCoRoutineCreate( vSerialTxCoRoutine, mainTX_CO_ROUTINE_PRIORITY, mainTX_CO_ROUTINE_INDEX );\r
+\r
+ /* Create the LCD and Comms Rx tasks. */\r
+ xTaskCreate( vLCDTask, "LCD", configMINIMAL_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL );\r
+ xTaskCreate( vCommsRxTask, "CMS", configMINIMAL_STACK_SIZE, NULL, mainCOMMS_RX_TASK_PRIORITY, NULL );\r
+\r
+ /* Start the scheduler running the tasks and co-routines just created. */\r
+ vTaskStartScheduler();\r
+\r
+ /* Should not get here unless we did not have enough memory to start the\r
+ scheduler. */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+ /* Setup the PLL. */\r
+ SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ );\r
+\r
+ /* Initialise the hardware used to talk to the LCD, LED's and UART. */\r
+ PDCInit();\r
+ vParTestInitialise();\r
+ vSerialInit();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationIdleHook( void )\r
+{\r
+ /* The co-routines are executed in the idle task using the idle task \r
+ hook. */\r
+ for( ;; )\r
+ {\r
+ /* Schedule the co-routines. */\r
+ vCoRoutineSchedule();\r
+\r
+ /* Run the register check function between each co-routine. */\r
+ prvSetAndCheckRegisters();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvWriteString( const portCHAR *pcString )\r
+{\r
+ /* Write pcString to the LED, pausing between each character. */\r
+ prvPDCWrite(PDC_LCD_CSR, LCD_CLEAR); \r
+ while( *pcString )\r
+ {\r
+ vTaskDelay( mainCHAR_WRITE_DELAY );\r
+ prvPDCWrite( PDC_LCD_RAM, *pcString );\r
+ pcString++;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vLCDTask( void * pvParameters )\r
+{\r
+unsigned portBASE_TYPE uxIndex;\r
+const unsigned portCHAR ucCFGData[] = { \r
+ 0x30, /* Set data bus to 8-bits. */\r
+ 0x30,\r
+ 0x30,\r
+ 0x3C, /* Number of lines/font. */\r
+ 0x08, /* Display off. */\r
+ 0x01, /* Display clear. */\r
+ 0x06, /* Entry mode [cursor dir][shift]. */\r
+ 0x0C /* Display on [display on][curson on][blinking on]. */\r
+ }; \r
+\r
+/* The strings that are written to the LCD. */\r
+const portCHAR *pcStringsToDisplay[] = { \r
+ "Stellaris",\r
+ "Demo",\r
+ "One",\r
+ "www.FreeRTOS.org",\r
+ ""\r
+ };\r
+\r
+ /* Configure the LCD. */\r
+ uxIndex = 0;\r
+ while( uxIndex < sizeof( ucCFGData ) )\r
+ {\r
+ prvPDCWrite( PDC_LCD_CSR, ucCFGData[ uxIndex ] );\r
+ uxIndex++;\r
+ vTaskDelay( mainCHAR_WRITE_DELAY );\r
+ }\r
+\r
+ /* Turn the LCD Backlight on. */\r
+ prvPDCWrite( PDC_CSR, 0x01 );\r
+\r
+ /* Clear display. */\r
+ vTaskDelay( mainCHAR_WRITE_DELAY );\r
+ prvPDCWrite( PDC_LCD_CSR, LCD_CLEAR ); \r
+\r
+ uxIndex = 0;\r
+ for( ;; ) \r
+ {\r
+ /* Display the string on the LCD. */\r
+ prvWriteString( pcStringsToDisplay[ uxIndex ] );\r
+ \r
+ /* Move on to the next string - wrapping if necessary. */\r
+ uxIndex++;\r
+ if( *( pcStringsToDisplay[ uxIndex ] ) == 0x00 )\r
+ {\r
+ uxIndex = 0;\r
+ /* Longer pause on the last string to be sent. */\r
+ vTaskDelay( mainSTRING_WRITE_DELAY * 2 );\r
+ }\r
+\r
+ /* Wait until it is time to move onto the next string. */\r
+ vTaskDelay( mainSTRING_WRITE_DELAY );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vCommsRxTask( void * pvParameters )\r
+{\r
+static portCHAR cRxedChar, cExpectedChar;\r
+\r
+ /* Set the char we expect to receive to the start of the string. */\r
+ cExpectedChar = mainFIRST_TX_CHAR;\r
+\r
+ for( ;; )\r
+ {\r
+ /* Wait for a character to be received. */\r
+ xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY );\r
+\r
+ /* Was the character recived (if any) the expected character. */\r
+ if( cRxedChar != cExpectedChar )\r
+ {\r
+ /* Got an unexpected character. This can sometimes occur when\r
+ reseting the system using the debugger leaving characters already\r
+ in the UART regsters. */\r
+ uxErrorStatus = pdFAIL;\r
+\r
+ /* Resync by waiting for the end of the current string. */\r
+ while( cRxedChar != mainLAST_TX_CHAR )\r
+ {\r
+ while( !xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, portMAX_DELAY ) );\r
+ }\r
+\r
+ /* The next expected character is the start of the string again. */\r
+ cExpectedChar = mainFIRST_TX_CHAR;\r
+ }\r
+ else\r
+ {\r
+ if( cExpectedChar == mainLAST_TX_CHAR )\r
+ {\r
+ /* We have reached the end of the string - we now expect to \r
+ receive the first character in the string again. The LED is \r
+ toggled to indicate that the entire string was received without\r
+ error. */\r
+ vParTestToggleLED( mainCOMMS_RX_LED );\r
+ cExpectedChar = mainFIRST_TX_CHAR;\r
+ }\r
+ else\r
+ {\r
+ /* We got the expected character, we now expect to receive the\r
+ next character in the string. */\r
+ cExpectedChar++;\r
+ }\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )\r
+{\r
+portTickType xDelayPeriod;\r
+static unsigned portLONG *pulRandomBytes = mainFIRST_PROGRAM_BYTES;\r
+\r
+ /* Co-routine MUST start with a call to crSTART. */\r
+ crSTART( xHandle );\r
+\r
+ for(;;)\r
+ { \r
+ /* Was the previously transmitted string received correctly? */\r
+ if( uxErrorStatus != pdPASS )\r
+ {\r
+ /* An error was encountered so set the error LED. */\r
+ vSetErrorLED();\r
+ }\r
+\r
+ /* The next character to Tx is the first in the string. */\r
+ cNextChar = mainFIRST_TX_CHAR;\r
+\r
+ UARTIntDisable( UART0_BASE, UART_INT_TX );\r
+ {\r
+ /* Send the first character. */\r
+ if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) )\r
+ {\r
+ HWREG( UART0_BASE + UART_O_DR ) = cNextChar;\r
+ }\r
+\r
+ /* Move the variable to the char to Tx on so the ISR transmits\r
+ the next character in the string once this one has completed. */\r
+ cNextChar++;\r
+ }\r
+ UARTIntEnable(UART0_BASE, UART_INT_TX);\r
+\r
+ /* Toggle the LED to show a new string is being transmitted. */\r
+ vParTestToggleLED( mainCOMMS_TX_LED );\r
+\r
+ /* Delay before we start the string off again. A pseudo-random delay\r
+ is used as this will provide a better test. */\r
+ xDelayPeriod = xTaskGetTickCount() + ( *pulRandomBytes );\r
+\r
+ pulRandomBytes++;\r
+ if( pulRandomBytes > mainTOTAL_PROGRAM_MEMORY )\r
+ {\r
+ pulRandomBytes = mainFIRST_PROGRAM_BYTES;\r
+ }\r
+\r
+ /* Make sure we don't wait too long... */\r
+ xDelayPeriod &= mainMAX_TX_DELAY;\r
+\r
+ /* ...but we do want to wait. */\r
+ if( xDelayPeriod < mainMIN_TX_DELAY )\r
+ {\r
+ xDelayPeriod = mainMIN_TX_DELAY;\r
+ }\r
+\r
+ /* Block for the random(ish) time. */\r
+ crDELAY( xHandle, xDelayPeriod );\r
+ }\r
+\r
+ /* Co-routine MUST end with a call to crEND. */\r
+ crEND();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vSerialInit( void )\r
+{\r
+ /* Enable the UART. GPIOA has already been initialised. */\r
+ SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);\r
+\r
+ /* Set GPIO A0 and A1 as peripheral function. They are used to output the\r
+ UART signals. */\r
+ GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW );\r
+\r
+ /* Configure the UART for 8-N-1 operation. */\r
+ UARTConfigSet( UART0_BASE, mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE );\r
+\r
+ /* We dont want to use the fifo. This is for test purposes to generate\r
+ as many interrupts as possible. */\r
+ HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET;\r
+\r
+ /* Enable both Rx and Tx interrupts. */\r
+ HWREG( UART0_BASE + UART_O_IM ) |= ( UART_INT_TX | UART_INT_RX );\r
+ IntEnable( INT_UART0 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vUART_ISR(void)\r
+{\r
+unsigned portLONG ulStatus;\r
+portCHAR cRxedChar;\r
+portBASE_TYPE xTaskWokenByPost = pdFALSE;\r
+\r
+ /* What caused the interrupt. */\r
+ ulStatus = UARTIntStatus( UART0_BASE, pdTRUE );\r
+\r
+ /* Clear the interrupt. */\r
+ UARTIntClear( UART0_BASE, ulStatus );\r
+\r
+ /* Was an Rx interrpt pending? */\r
+ if( ulStatus & UART_INT_RX )\r
+ {\r
+ if( ( HWREG(UART0_BASE + UART_O_FR ) & UART_FR_RXFF ) )\r
+ {\r
+ /* Get the char from the buffer and post it onto the queue of\r
+ Rxed chars. Posting the character should wake the task that is \r
+ blocked on the queue waiting for characters. */\r
+ cRxedChar = ( portCHAR ) HWREG( UART0_BASE + UART_O_DR );\r
+ xTaskWokenByPost = xQueueSendFromISR( xCommsQueue, &cRxedChar, xTaskWokenByPost );\r
+ } \r
+ }\r
+\r
+ /* Was a Tx interrupt pending? */\r
+ if( ulStatus & UART_INT_TX )\r
+ {\r
+ /* Send the next character in the string. We are not using the FIFO. */\r
+ if( cNextChar <= mainLAST_TX_CHAR )\r
+ {\r
+ if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) )\r
+ {\r
+ HWREG( UART0_BASE + UART_O_DR ) = cNextChar;\r
+ }\r
+ cNextChar++;\r
+ }\r
+ }\r
+ \r
+ if( xTaskWokenByPost )\r
+ {\r
+ /* If a task was woken by the character being received then we force\r
+ a context switch to occur in case the task is of higher priority than\r
+ the currently executing task (i.e. the task that this interrupt \r
+ interrupted.) */\r
+ portEND_SWITCHING_ISR( xTaskWokenByPost );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvPDCWrite( portCHAR cAddress, portCHAR cData )\r
+{\r
+ vTaskSuspendAll();\r
+ {\r
+ PDCWrite( cAddress, cData );\r
+ }\r
+ xTaskResumeAll();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSetErrorLED( void )\r
+{\r
+ vParTestSetLED( mainCOMMS_FAIL_LED, pdTRUE );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void prvSetAndCheckRegisters( void )\r
+{\r
+ /* Fill the general purpose registers with known values. */\r
+ __asm volatile( " mov r11, #10\n"\r
+ " add r0, r11, #1\n"\r
+ " add r1, r11, #2\n"\r
+ " add r2, r11, #3\n"\r
+ " add r3, r11, #4\n"\r
+ " add r4, r11, #5\n"\r
+ " add r5, r11, #6\n"\r
+ " add r6, r11, #7\n"\r
+ " add r7, r11, #8\n"\r
+ " add r8, r11, #9\n"\r
+ " add r9, r11, #10\n"\r
+ " add r10, r11, #11\n"\r
+ " add r12, r11, #12" );\r
+\r
+ /* Check the values are as expected. */\r
+ __asm volatile( " cmp r11, #10\n"\r
+ " bne set_error_led\n"\r
+ " cmp r0, #11\n"\r
+ " bne set_error_led\n"\r
+ " cmp r1, #12\n"\r
+ " bne set_error_led\n"\r
+ " cmp r2, #13\n"\r
+ " bne set_error_led\n"\r
+ " cmp r3, #14\n"\r
+ " bne set_error_led\n"\r
+ " cmp r4, #15\n"\r
+ " bne set_error_led\n"\r
+ " cmp r5, #16\n"\r
+ " bne set_error_led\n"\r
+ " cmp r6, #17\n"\r
+ " bne set_error_led\n"\r
+ " cmp r7, #18\n"\r
+ " bne set_error_led\n"\r
+ " cmp r8, #19\n"\r
+ " bne set_error_led\n"\r
+ " cmp r9, #20\n"\r
+ " bne set_error_led\n"\r
+ " cmp r10, #21\n"\r
+ " bne set_error_led\n"\r
+ " cmp r12, #22\n"\r
+ " bne set_error_led\n"\r
+ " bx lr" );\r
+\r
+ __asm volatile( "set_error_led:\n"\r
+ " push {r14}\n"\r
+ " ldr r1, =vSetErrorLED\n"\r
+ " blx r1\n"\r
+ " pop {r14}\n"\r
+ " bx lr" );\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+#******************************************************************************
+#
+# makedefs - Definitions common to all makefiles.
+#
+# Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
+#
+# Software License Agreement
+#
+# Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+# exclusively on LMI's Stellaris Family of microcontroller products.
+#
+# The software is owned by LMI and/or its suppliers, and is protected under
+# applicable copyright laws. All rights are reserved. Any use in violation
+# of the foregoing restrictions may subject the user to criminal sanctions
+# under applicable laws, as well as to civil liability for the breach of the
+# terms and conditions of this license.
+#
+# THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+# OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+# LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+# CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+#
+#******************************************************************************
+
+#******************************************************************************
+#
+# The compiler to be used.
+#
+#******************************************************************************
+ifndef COMPILER
+COMPILER=gcc
+endif
+
+#******************************************************************************
+#
+# The debugger to be used.
+#
+#******************************************************************************
+ifndef DEBUGGER
+DEBUGGER=gdb
+endif
+
+#******************************************************************************
+#
+# Definitions for using GCC.
+#
+#******************************************************************************
+ifeq (${COMPILER}, gcc)
+
+#
+# The command for calling the compiler.
+#
+CC=arm-stellaris-eabi-gcc
+
+#
+# The flags passed to the assembler.
+#
+AFLAGS=-mthumb \
+ -mcpu=cortex-m3 \
+ -MD
+
+#
+# The flags passed to the compiler.
+#
+CFLAGS=-mthumb \
+ -mcpu=cortex-m3 \
+ -O2 \
+ -MD
+
+#
+# The command for calling the library archiver.
+#
+AR=arm-stellaris-eabi-ar
+
+#
+# The command for calling the linker.
+#
+LD=arm-stellaris-eabi-ld
+
+#
+# The flags passed to the linker.
+#
+LDFLAGS= -Map gcc/out.map
+
+#
+# Get the location of libgcc.a from the GCC front-end.
+#
+LIBGCC=${shell ${CC} -mthumb -march=armv6t2 -print-libgcc-file-name}
+
+#
+# Get the location of libc.a from the GCC front-end.
+#
+LIBC=${shell ${CC} -mthumb -march=armv6t2 -print-file-name=libc.a}
+
+#
+# The command for extracting images from the linked executables.
+#
+OBJCOPY=arm-stellaris-eabi-objcopy
+
+endif
+
+#******************************************************************************
+#
+# Tell the compiler to include debugging information if the DEBUG environment
+# variable is set.
+#
+#******************************************************************************
+ifdef DEBUG
+CFLAGS += -g
+endif
+
+#******************************************************************************
+#
+# The rule for building the object file from each C source file.
+#
+#******************************************************************************
+${COMPILER}/%.o: %.c
+ @if [ 'x${VERBOSE}' = x ]; \
+ then \
+ echo " CC ${<}"; \
+ else \
+ echo ${CC} ${CFLAGS} -D${COMPILER} -o ${@} -c ${<}; \
+ fi
+ @${CC} ${CFLAGS} -D${COMPILER} -o ${@} -c ${<}
+ifeq (${COMPILER}, rvds)
+ @mv -f ${notdir ${@:.o=.d}} ${COMPILER}
+endif
+
+#******************************************************************************
+#
+# The rule for building the object file from each assembly source file.
+#
+#******************************************************************************
+${COMPILER}/%.o: %.S
+ @if [ 'x${VERBOSE}' = x ]; \
+ then \
+ echo " CC ${<}"; \
+ else \
+ echo ${CC} ${AFLAGS} -D${COMPILER} -o ${@} -c ${<}; \
+ fi
+ifeq (${COMPILER}, rvds)
+ @${CC} ${AFLAGS} -D${COMPILER} -E ${<} > ${@:.o=_.S}
+ @${CC} ${AFLAGS} -o ${@} -c ${@:.o=_.S}
+ @rm ${@:.o=_.S}
+ @${CC} ${AFLAGS} -D${COMPILER} --md -E ${<}
+ @sed 's,<stdout>,${@},g' ${notdir ${<:.S=.d}} > ${@:.o=.d}
+ @rm ${notdir ${<:.S=.d}}
+endif
+ifeq (${COMPILER}, gcc)
+ @${CC} ${AFLAGS} -D${COMPILER} -o ${@} -c ${<}
+endif
+
+#******************************************************************************
+#
+# The rule for creating an object library.
+#
+#******************************************************************************
+${COMPILER}/%.a:
+ @if [ 'x${VERBOSE}' = x ]; \
+ then \
+ echo " AR ${@}"; \
+ else \
+ echo ${AR} -cr ${@} ${^}; \
+ fi
+ @${AR} -cr ${@} ${^}
+
+#******************************************************************************
+#
+# The rule for linking the application.
+#
+#******************************************************************************
+${COMPILER}/%.axf:
+ @if [ 'x${VERBOSE}' = x ]; \
+ then \
+ echo " LD ${@}"; \
+ fi
+ifeq (${COMPILER}, gcc)
+ @if [ 'x${VERBOSE}' != x ]; \
+ then \
+ echo ${LD} -T ${SCATTER_${notdir ${@:.axf=}}} \
+ --entry ${ENTRY_${notdir ${@:.axf=}}} \
+ ${LDFLAGSgcc_${notdir ${@:.axf=}}} \
+ ${LDFLAGS} -o ${@} ${^} \
+ '${LIBC}' '${LIBGCC}'; \
+ fi
+ @${LD} -T ${SCATTER_${notdir ${@:.axf=}}} \
+ --entry ${ENTRY_${notdir ${@:.axf=}}} \
+ ${LDFLAGSgcc_${notdir ${@:.axf=}}} \
+ ${LDFLAGS} -o ${@} ${^} \
+ '${LIBC}' '${LIBGCC}'
+ @${OBJCOPY} -O binary ${@} ${@:.axf=.bin}
+endif
--- /dev/null
+/******************************************************************************
+ *
+ * standalone.ld - Linker script for applications using startup.c and
+ * DriverLib.
+ *
+ * Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
+ *
+ * Software License Agreement
+ *
+ * Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+ * exclusively on LMI's Stellaris Family of microcontroller products.
+ *
+ * The software is owned by LMI and/or its suppliers, and is protected under
+ * applicable copyright laws. All rights are reserved. Any use in violation
+ * of the foregoing restrictions may subject the user to criminal sanctions
+ * under applicable laws, as well as to civil liability for the breach of the
+ * terms and conditions of this license.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ *****************************************************************************/
+
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 8K
+ SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 2K
+}
+
+SECTIONS
+{
+ .text :
+ {
+ *(vectors)
+ *(.text)
+ *(.rodata*)
+ *(.constdata*)
+ _etext = .;
+ } > FLASH
+
+ .data : AT (ADDR(.text) + SIZEOF(.text))
+ {
+ _data = .;
+ *(vtable)
+ *(.data)
+ _edata = .;
+ } > SRAM
+
+ .bss :
+ {
+ _bss = .;
+ *(.bss)
+ _ebss = .;
+ } > SRAM
+}
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. \r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 1\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 20000000 )\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 59 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1468 ) )\r
+#define configMAX_TASK_NAME_LEN ( 3 )\r
+#define configUSE_TRACE_FACILITY 0\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 0\r
+#define configUSE_CO_ROUTINES 1\r
+\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 )\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet 0\r
+#define INCLUDE_uxTaskPriorityGet 0\r
+#define INCLUDE_vTaskDelete 0\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 0\r
+#define INCLUDE_vTaskDelayUntil 0\r
+#define INCLUDE_vTaskDelay 1\r
+\r
+\r
+\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* \r
+ * This demo application creates six co-routines and two tasks (three including \r
+ * the idle task). The co-routines execute as part of the idle task hook.\r
+ *\r
+ * Five of the created co-routines are the standard 'co-routine flash' \r
+ * co-routines contained within the Demo/Common/Minimal/crflash.c file and \r
+ * documented on the FreeRTOS.org WEB site. \r
+ *\r
+ * The 'LCD Task' rotates a string on the LCD, delaying between each character\r
+ * as necessitated by the slow interface, and delaying between each string just\r
+ * long enough to enable the text to be read.\r
+ *\r
+ * The sixth co-routine and final task control the transmission and reception\r
+ * of a string to UART 0. The co-routine periodically sends the first \r
+ * character of the string to the UART, with the UART's TxEnd interrupt being\r
+ * used to transmit the remaining characters. The UART's RxEnd interrupt \r
+ * receives the characters and places them on a queue to be processed by the \r
+ * 'COMs Rx' task. An error is latched should an unexpected character be \r
+ * received, or any character be received out of sequence. \r
+ *\r
+ * A loopback connector is required to ensure that each character transmitted \r
+ * on the UART is also received on the same UART. For test purposes the UART\r
+ * FIFO's are not utalised in order to maximise the interrupt overhead. Also\r
+ * a pseudo random interval is used between the start of each transmission in \r
+ * order that the resultant interrupts are more randomly distributed and \r
+ * therefore more likely to highlight any problems.\r
+ *\r
+ * The flash co-routines control LED's zero to four. LED five is toggled each\r
+ * time the string is transmitted on the UART. LED six is toggled each time\r
+ * the string is CORRECTLY received on the UART. LED seven is latched on should\r
+ * an error be detected in any task or co-routine.\r
+ *\r
+ * In addition the idle task makes repetative calls to \r
+ * prvSetAndCheckRegisters(). This simply loads the general purpose registers \r
+ * with a known value, then checks each register to ensure the held value is \r
+ * still correct. As a low priority task this checking routine is likely to \r
+ * get repeatedly swapped in and out. A register being found to contain an \r
+ * incorrect value is therefore indicative of an error in the task switching \r
+ * mechansim.\r
+ *\r
+ */\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+#include "croutine.h"\r
+\r
+/* Demo application include files. */\r
+#include "partest.h"\r
+#include "crflash.h"\r
+\r
+/* Library include files. */\r
+#include "LM3Sxxx.h"\r
+#include "pdc.h"\r
+\r
+/* The time to delay between writing each character to the LCD. */\r
+#define mainCHAR_WRITE_DELAY ( 2 / portTICK_RATE_MS )\r
+\r
+/* The time to delay between writing each string to the LCD. */\r
+#define mainSTRING_WRITE_DELAY ( 400 / portTICK_RATE_MS )\r
+\r
+/* The number of flash co-routines to create. */\r
+#define mainNUM_FLASH_CO_ROUTINES ( 5 )\r
+\r
+/* The length of the queue used to pass received characters to the Comms Rx\r
+task. */\r
+#define mainRX_QUEUE_LEN ( 5 )\r
+\r
+/* The priority of the co-routine used to initiate the transmission of the \r
+string on UART 0. */\r
+#define mainTX_CO_ROUTINE_PRIORITY ( 1 )\r
+\r
+/* Only one co-routine is created so its index is not important. */\r
+#define mainTX_CO_ROUTINE_INDEX ( 0 )\r
+\r
+/* The time between transmissions of the string on UART 0. This is pseudo\r
+random in order to generate a bit or randomness to when the interrupts occur.*/\r
+#define mainMIN_TX_DELAY ( 40 / portTICK_RATE_MS )\r
+#define mainMAX_TX_DELAY ( ( portTickType ) 0x7f )\r
+#define mainOFFSET_TIME ( ( portTickType ) 3 )\r
+\r
+/* The time the Comms Rx task should wait to receive a character. This should\r
+be slightly longer than the time between transmissions. If we do not receive\r
+a character after this time then there must be an error in the transmission or\r
+the timing of the transmission. */\r
+#define mainCOMMS_RX_DELAY ( mainMAX_TX_DELAY + 20 )\r
+\r
+/* The task priorites. */\r
+#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+#define mainCOMMS_RX_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+\r
+/* The LED's toggled by the various tasks. */\r
+#define mainCOMMS_FAIL_LED ( 7 )\r
+#define mainCOMMS_RX_LED ( 6 )\r
+#define mainCOMMS_TX_LED ( 5 )\r
+\r
+/* The baud rate used by the UART comms tasks/co-routine. */\r
+#define mainBAUD_RATE ( 57600 )\r
+\r
+/* FIFO setting for the UART. The FIFO is not used to create a better test. */\r
+#define mainFIFO_SET ( 0x10 )\r
+\r
+/* The string that is transmitted on the UART contains sequentially the \r
+characters from mainFIRST_TX_CHAR to mainLAST_TX_CHAR. */\r
+#define mainFIRST_TX_CHAR '0'\r
+#define mainLAST_TX_CHAR 'z'\r
+\r
+/* Just used to walk through the program memory in order that some random data\r
+can be generated. */\r
+#define mainTOTAL_PROGRAM_MEMORY ( ( unsigned portLONG * ) ( 8 * 1024 ) )\r
+#define mainFIRST_PROGRAM_BYTES ( ( unsigned portLONG * ) 4 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The task that rotates text on the LCD.\r
+ */\r
+static void vLCDTask( void * pvParameters );\r
+\r
+/*\r
+ * The task that receives the characters from UART 0.\r
+ */\r
+static void vCommsRxTask( void * pvParameters );\r
+\r
+/*\r
+ * The co-routine that periodically initiates the transmission of the string on\r
+ * the UART.\r
+ */\r
+static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex );\r
+\r
+/* \r
+ * Writes a string the the LCD.\r
+ */\r
+static void prvWriteString( const portCHAR *pcString );\r
+\r
+/*\r
+ * Initialisation routine for the UART.\r
+ */\r
+static void vSerialInit( void );\r
+\r
+/*\r
+ * Thread safe write to the PDC.\r
+ */\r
+static void prvPDCWrite( portCHAR cAddress, portCHAR cData );\r
+\r
+/*\r
+ * Function to simply set a known value into the general purpose registers\r
+ * then read them back to ensure they remain set correctly. An incorrect value\r
+ * being indicative of an error in the task switching mechanism.\r
+ */\r
+void prvSetAndCheckRegisters( void );\r
+\r
+/*\r
+ * Latch the LED that indicates that an error has occurred. \r
+ */\r
+void vSetErrorLED( void );\r
+\r
+/*\r
+ * Sets up the PLL and ports used by the demo.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Error flag set to pdFAIL if an error is encountered in the tasks/co-routines\r
+defined within this file. */\r
+unsigned portBASE_TYPE uxErrorStatus = pdPASS;\r
+\r
+/* The next character to transmit. */\r
+static portCHAR cNextChar;\r
+\r
+/* The queue used to transmit characters from the interrupt to the Comms Rx\r
+task. */\r
+static xQueueHandle xCommsQueue;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+int main( void )\r
+{\r
+ /* Create the queue used to communicate between the UART ISR and the Comms\r
+ Rx task. */\r
+ xCommsQueue = xQueueCreate( mainRX_QUEUE_LEN, sizeof( portCHAR ) );\r
+\r
+ /* Setup the ports used by the demo and the clock. */\r
+ prvSetupHardware();\r
+\r
+ /* Create the co-routines that flash the LED's. */\r
+ vStartFlashCoRoutines( mainNUM_FLASH_CO_ROUTINES );\r
+\r
+ /* Create the co-routine that initiates the transmission of characters\r
+ on the UART. */\r
+ xCoRoutineCreate( vSerialTxCoRoutine, mainTX_CO_ROUTINE_PRIORITY, mainTX_CO_ROUTINE_INDEX );\r
+\r
+ /* Create the LCD and Comms Rx tasks. */\r
+ xTaskCreate( vLCDTask, "LCD", configMINIMAL_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL );\r
+ xTaskCreate( vCommsRxTask, "CMS", configMINIMAL_STACK_SIZE, NULL, mainCOMMS_RX_TASK_PRIORITY, NULL );\r
+\r
+ /* Start the scheduler running the tasks and co-routines just created. */\r
+ vTaskStartScheduler();\r
+\r
+ /* Should not get here unless we did not have enough memory to start the\r
+ scheduler. */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+ /* Setup the PLL. */\r
+ SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ );\r
+\r
+ /* Initialise the hardware used to talk to the LCD, LED's and UART. */\r
+ PDCInit();\r
+ vParTestInitialise();\r
+ vSerialInit();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationIdleHook( void )\r
+{\r
+ /* The co-routines are executed in the idle task using the idle task \r
+ hook. */\r
+ for( ;; )\r
+ {\r
+ /* Schedule the co-routines. */\r
+ vCoRoutineSchedule();\r
+\r
+ /* Run the register check function between each co-routine. */\r
+ prvSetAndCheckRegisters();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvWriteString( const portCHAR *pcString )\r
+{\r
+ /* Write pcString to the LED, pausing between each character. */\r
+ prvPDCWrite(PDC_LCD_CSR, LCD_CLEAR); \r
+ while( *pcString )\r
+ {\r
+ vTaskDelay( mainCHAR_WRITE_DELAY );\r
+ prvPDCWrite( PDC_LCD_RAM, *pcString );\r
+ pcString++;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vLCDTask( void * pvParameters )\r
+{\r
+unsigned portBASE_TYPE uxIndex;\r
+const unsigned portCHAR ucCFGData[] = { \r
+ 0x30, /* Set data bus to 8-bits. */\r
+ 0x30,\r
+ 0x30,\r
+ 0x3C, /* Number of lines/font. */\r
+ 0x08, /* Display off. */\r
+ 0x01, /* Display clear. */\r
+ 0x06, /* Entry mode [cursor dir][shift]. */\r
+ 0x0C /* Display on [display on][curson on][blinking on]. */\r
+ }; \r
+\r
+/* The strings that are written to the LCD. */\r
+const portCHAR *pcStringsToDisplay[] = { \r
+ "Stellaris",\r
+ "Demo",\r
+ "One",\r
+ "www.FreeRTOS.org",\r
+ ""\r
+ };\r
+\r
+ /* Configure the LCD. */\r
+ uxIndex = 0;\r
+ while( uxIndex < sizeof( ucCFGData ) )\r
+ {\r
+ prvPDCWrite( PDC_LCD_CSR, ucCFGData[ uxIndex ] );\r
+ uxIndex++;\r
+ vTaskDelay( mainCHAR_WRITE_DELAY );\r
+ }\r
+\r
+ /* Turn the LCD Backlight on. */\r
+ prvPDCWrite( PDC_CSR, 0x01 );\r
+\r
+ /* Clear display. */\r
+ vTaskDelay( mainCHAR_WRITE_DELAY );\r
+ prvPDCWrite( PDC_LCD_CSR, LCD_CLEAR ); \r
+\r
+ uxIndex = 0;\r
+ for( ;; ) \r
+ {\r
+ /* Display the string on the LCD. */\r
+ prvWriteString( pcStringsToDisplay[ uxIndex ] );\r
+ \r
+ /* Move on to the next string - wrapping if necessary. */\r
+ uxIndex++;\r
+ if( *( pcStringsToDisplay[ uxIndex ] ) == 0x00 )\r
+ {\r
+ uxIndex = 0;\r
+ /* Longer pause on the last string to be sent. */\r
+ vTaskDelay( mainSTRING_WRITE_DELAY * 2 );\r
+ }\r
+\r
+ /* Wait until it is time to move onto the next string. */\r
+ vTaskDelay( mainSTRING_WRITE_DELAY );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vCommsRxTask( void * pvParameters )\r
+{\r
+static portCHAR cRxedChar, cExpectedChar;\r
+\r
+ /* Set the char we expect to receive to the start of the string. */\r
+ cExpectedChar = mainFIRST_TX_CHAR;\r
+\r
+ for( ;; )\r
+ {\r
+ /* Wait for a character to be received. */\r
+ xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY );\r
+\r
+ /* Was the character recived (if any) the expected character. */\r
+ if( cRxedChar != cExpectedChar )\r
+ {\r
+ /* Got an unexpected character. This can sometimes occur when\r
+ reseting the system using the debugger leaving characters already\r
+ in the UART regsters. */\r
+ uxErrorStatus = pdFAIL;\r
+\r
+ /* Resync by waiting for the end of the current string. */\r
+ while( cRxedChar != mainLAST_TX_CHAR )\r
+ {\r
+ while( !xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, portMAX_DELAY ) );\r
+ }\r
+\r
+ /* The next expected character is the start of the string again. */\r
+ cExpectedChar = mainFIRST_TX_CHAR;\r
+ }\r
+ else\r
+ {\r
+ if( cExpectedChar == mainLAST_TX_CHAR )\r
+ {\r
+ /* We have reached the end of the string - we now expect to \r
+ receive the first character in the string again. The LED is \r
+ toggled to indicate that the entire string was received without\r
+ error. */\r
+ vParTestToggleLED( mainCOMMS_RX_LED );\r
+ cExpectedChar = mainFIRST_TX_CHAR;\r
+ }\r
+ else\r
+ {\r
+ /* We got the expected character, we now expect to receive the\r
+ next character in the string. */\r
+ cExpectedChar++;\r
+ }\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )\r
+{\r
+portTickType xDelayPeriod;\r
+static unsigned portLONG *pulRandomBytes = mainFIRST_PROGRAM_BYTES;\r
+\r
+ /* Co-routine MUST start with a call to crSTART. */\r
+ crSTART( xHandle );\r
+\r
+ for(;;)\r
+ { \r
+ /* Was the previously transmitted string received correctly? */\r
+ if( uxErrorStatus != pdPASS )\r
+ {\r
+ /* An error was encountered so set the error LED. */\r
+ vSetErrorLED();\r
+ }\r
+\r
+ /* The next character to Tx is the first in the string. */\r
+ cNextChar = mainFIRST_TX_CHAR;\r
+\r
+ UARTIntDisable( UART0_BASE, UART_INT_TX );\r
+ {\r
+ /* Send the first character. */\r
+ if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) )\r
+ {\r
+ HWREG( UART0_BASE + UART_O_DR ) = cNextChar;\r
+ }\r
+\r
+ /* Move the variable to the char to Tx on so the ISR transmits\r
+ the next character in the string once this one has completed. */\r
+ cNextChar++;\r
+ }\r
+ UARTIntEnable(UART0_BASE, UART_INT_TX);\r
+\r
+ /* Toggle the LED to show a new string is being transmitted. */\r
+ vParTestToggleLED( mainCOMMS_TX_LED );\r
+\r
+ /* Delay before we start the string off again. A pseudo-random delay\r
+ is used as this will provide a better test. */\r
+ xDelayPeriod = xTaskGetTickCount() + ( *pulRandomBytes );\r
+\r
+ pulRandomBytes++;\r
+ if( pulRandomBytes > mainTOTAL_PROGRAM_MEMORY )\r
+ {\r
+ pulRandomBytes = mainFIRST_PROGRAM_BYTES;\r
+ }\r
+\r
+ /* Make sure we don't wait too long... */\r
+ xDelayPeriod &= mainMAX_TX_DELAY;\r
+\r
+ /* ...but we do want to wait. */\r
+ if( xDelayPeriod < mainMIN_TX_DELAY )\r
+ {\r
+ xDelayPeriod = mainMIN_TX_DELAY;\r
+ }\r
+\r
+ /* Block for the random(ish) time. */\r
+ crDELAY( xHandle, xDelayPeriod );\r
+ }\r
+\r
+ /* Co-routine MUST end with a call to crEND. */\r
+ crEND();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vSerialInit( void )\r
+{\r
+ /* Enable the UART. GPIOA has already been initialised. */\r
+ SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);\r
+\r
+ /* Set GPIO A0 and A1 as peripheral function. They are used to output the\r
+ UART signals. */\r
+ GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW );\r
+\r
+ /* Configure the UART for 8-N-1 operation. */\r
+ UARTConfigSet( UART0_BASE, mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE );\r
+\r
+ /* We dont want to use the fifo. This is for test purposes to generate\r
+ as many interrupts as possible. */\r
+ HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET;\r
+\r
+ /* Enable both Rx and Tx interrupts. */\r
+ HWREG( UART0_BASE + UART_O_IM ) |= ( UART_INT_TX | UART_INT_RX );\r
+ IntEnable( INT_UART0 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vUART_ISR(void)\r
+{\r
+unsigned portLONG ulStatus;\r
+portCHAR cRxedChar;\r
+portBASE_TYPE xTaskWokenByPost = pdFALSE;\r
+\r
+ /* What caused the interrupt. */\r
+ ulStatus = UARTIntStatus( UART0_BASE, pdTRUE );\r
+\r
+ /* Clear the interrupt. */\r
+ UARTIntClear( UART0_BASE, ulStatus );\r
+\r
+ /* Was an Rx interrpt pending? */\r
+ if( ulStatus & UART_INT_RX )\r
+ {\r
+ if( ( HWREG(UART0_BASE + UART_O_FR ) & UART_FR_RXFF ) )\r
+ {\r
+ /* Get the char from the buffer and post it onto the queue of\r
+ Rxed chars. Posting the character should wake the task that is \r
+ blocked on the queue waiting for characters. */\r
+ cRxedChar = ( portCHAR ) HWREG( UART0_BASE + UART_O_DR );\r
+ xTaskWokenByPost = xQueueSendFromISR( xCommsQueue, &cRxedChar, xTaskWokenByPost );\r
+ } \r
+ }\r
+\r
+ /* Was a Tx interrupt pending? */\r
+ if( ulStatus & UART_INT_TX )\r
+ {\r
+ /* Send the next character in the string. We are not using the FIFO. */\r
+ if( cNextChar <= mainLAST_TX_CHAR )\r
+ {\r
+ if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) )\r
+ {\r
+ HWREG( UART0_BASE + UART_O_DR ) = cNextChar;\r
+ }\r
+ cNextChar++;\r
+ }\r
+ }\r
+ \r
+ if( xTaskWokenByPost )\r
+ {\r
+ /* If a task was woken by the character being received then we force\r
+ a context switch to occur in case the task is of higher priority than\r
+ the currently executing task (i.e. the task that this interrupt \r
+ interrupted.) */\r
+ portEND_SWITCHING_ISR( xTaskWokenByPost );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvPDCWrite( portCHAR cAddress, portCHAR cData )\r
+{\r
+ vTaskSuspendAll();\r
+ {\r
+ PDCWrite( cAddress, cData );\r
+ }\r
+ xTaskResumeAll();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSetErrorLED( void )\r
+{\r
+ vParTestSetLED( mainCOMMS_FAIL_LED, pdTRUE );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+__asm void prvSetAndCheckRegisters( void )\r
+{\r
+ extern vSetErrorLED\r
+\r
+ /* Fill the general purpose registers with known values. */\r
+ mov r11, #10\r
+ add r0, r11, #1\r
+ add r1, r11, #2\r
+ add r2, r11, #3\r
+ add r3, r11, #4\r
+ add r4, r11, #5\r
+ add r5, r11, #6\r
+ add r6, r11, #7\r
+ add r7, r11, #8\r
+ add r8, r11, #9\r
+ add r9, r11, #10\r
+ add r10, r11, #11\r
+ add r12, r11, #12\r
+\r
+ /* Check the values are as expected. */\r
+ cmp r11, #10\r
+ bne set_error_led\r
+ cmp r0, #11\r
+ bne set_error_led\r
+ cmp r1, #12\r
+ bne set_error_led\r
+ cmp r2, #13\r
+ bne set_error_led\r
+ cmp r3, #14\r
+ bne set_error_led\r
+ cmp r4, #15\r
+ bne set_error_led\r
+ cmp r5, #16\r
+ bne set_error_led\r
+ cmp r6, #17\r
+ bne set_error_led\r
+ cmp r7, #18\r
+ bne set_error_led\r
+ cmp r8, #19\r
+ bne set_error_led\r
+ cmp r9, #20\r
+ bne set_error_led\r
+ cmp r10, #21\r
+ bne set_error_led\r
+ cmp r12, #22\r
+ bne set_error_led\r
+ bx lr\r
+\r
+set_error_led;\r
+ push {r14}\r
+ ldr r1, =vSetErrorLED\r
+ blx r1\r
+ pop {r14}\r
+ bx lr;\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+Move these two fines into the Demo/CORTEX_LM3S102_KEIL directory to run Demo 1.\r
+\r
+See the port documentation on the www.FreeRTOS.org site for more information.\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. \r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 1\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 20000000 )\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 59 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1240 ) )\r
+#define configMAX_TASK_NAME_LEN ( 3 )\r
+#define configUSE_TRACE_FACILITY 0\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 0\r
+#define configUSE_CO_ROUTINES 1\r
+\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 )\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 3 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet 0\r
+#define INCLUDE_uxTaskPriorityGet 0\r
+#define INCLUDE_vTaskDelete 0\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 0\r
+#define INCLUDE_vTaskDelayUntil 0\r
+#define INCLUDE_vTaskDelay 1\r
+\r
+\r
+\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* \r
+ * This demo application creates seven co-routines and one task (two including \r
+ * the idle task). The co-routines execute as part of the idle task hook.\r
+ *\r
+ * Five of the created co-routines are the standard 'co-routine flash' \r
+ * co-routines contained within the Demo/Common/Minimal/crflash.c file and \r
+ * documented on the FreeRTOS.org WEB site. \r
+ *\r
+ * The 'LCD Task' rotates a string on the LCD, delaying between each character\r
+ * as necessitated by the slow interface, and delaying between each string just\r
+ * long enough to enable the text to be read.\r
+ *\r
+ * The sixth co-routine controls the transmission of a string to UART 0. The \r
+ * co-routine periodically sends the first character of the string to the UART, \r
+ * with the UART's TxEnd interrupt being used to transmit the remaining \r
+ * characters. The UART's RxEnd interrupt receives the characters and places \r
+ * them on a queue to be processed by the seventh and final co-routine. An \r
+ * error is latched should an unexpected character be received, or any \r
+ * character be received out of sequence. \r
+ *\r
+ * A loopback connector is required to ensure that each character transmitted \r
+ * on the UART is also received on the same UART. For test purposes the UART\r
+ * FIFO's are not utalised in order to maximise the interrupt overhead. Also\r
+ * a pseudo random interval is used between the start of each transmission in \r
+ * order that the resultant interrupts are more randomly distributed and \r
+ * therefore more likely to highlight any problems.\r
+ *\r
+ * The flash co-routines control LED's zero to four. LED five is toggled each\r
+ * time the string is transmitted on the UART. LED six is toggled each time\r
+ * the string is CORRECTLY received on the UART. LED seven is latched on should\r
+ * an error be detected in any task or co-routine.\r
+ *\r
+ * In addition the idle task makes repetative calls to \r
+ * prvSetAndCheckRegisters(). This simply loads the general purpose registers \r
+ * with a known value, then checks each register to ensure the held value is \r
+ * still correct. As a low priority task this checking routine is likely to \r
+ * get repeatedly swapped in and out. A register being found to contain an \r
+ * incorrect value is therefore indicative of an error in the task switching \r
+ * mechansim.\r
+ *\r
+ */\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+#include "croutine.h"\r
+\r
+/* Demo application include files. */\r
+#include "partest.h"\r
+#include "crflash.h"\r
+\r
+/* Library include files. */\r
+#include "LM3Sxxx.h"\r
+#include "pdc.h"\r
+\r
+/* The time to delay between writing each character to the LCD. */\r
+#define mainCHAR_WRITE_DELAY ( 2 / portTICK_RATE_MS )\r
+\r
+/* The time to delay between writing each string to the LCD. */\r
+#define mainSTRING_WRITE_DELAY ( 400 / portTICK_RATE_MS )\r
+\r
+/* The number of flash co-routines to create. */\r
+#define mainNUM_FLASH_CO_ROUTINES ( 5 )\r
+\r
+/* The length of the queue used to pass received characters to the Comms Rx\r
+task. */\r
+#define mainRX_QUEUE_LEN ( 5 )\r
+\r
+/* The priority of the co-routine used to initiate the transmission of the \r
+string on UART 0. */\r
+#define mainTX_CO_ROUTINE_PRIORITY ( 1 )\r
+\r
+/* The priority of the co-routine used to receive characters from the UART. */\r
+#define mainRX_CO_ROUTINE_PRIORITY ( 2 )\r
+\r
+/* Only one co-routine is created so its index is not important. */\r
+#define mainTX_CO_ROUTINE_INDEX ( 0 )\r
+#define mainRX_CO_ROUTINE_INDEX ( 0 )\r
+\r
+/* The time between transmissions of the string on UART 0. This is pseudo\r
+random in order to generate a bit or randomness to when the interrupts occur.*/\r
+#define mainMIN_TX_DELAY ( 40 / portTICK_RATE_MS )\r
+#define mainMAX_TX_DELAY ( ( portTickType ) 0x7f )\r
+#define mainOFFSET_TIME ( ( portTickType ) 3 )\r
+\r
+/* The time the Comms Rx task should wait to receive a character. This should\r
+be slightly longer than the time between transmissions. If we do not receive\r
+a character after this time then there must be an error in the transmission or\r
+the timing of the transmission. */\r
+#define mainCOMMS_RX_DELAY ( mainMAX_TX_DELAY + 20 )\r
+\r
+/* The task priorites. */\r
+#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+#define mainCOMMS_RX_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+\r
+/* The LED's toggled by the various tasks. */\r
+#define mainCOMMS_FAIL_LED ( 7 )\r
+#define mainCOMMS_RX_LED ( 6 )\r
+#define mainCOMMS_TX_LED ( 5 )\r
+\r
+/* The baud rate used by the UART comms tasks/co-routine. */\r
+#define mainBAUD_RATE ( 57600 )\r
+\r
+/* FIFO setting for the UART. The FIFO is not used to create a better test. */\r
+#define mainFIFO_SET ( 0x10 )\r
+\r
+/* The string that is transmitted on the UART contains sequentially the \r
+characters from mainFIRST_TX_CHAR to mainLAST_TX_CHAR. */\r
+#define mainFIRST_TX_CHAR '0'\r
+#define mainLAST_TX_CHAR 'z'\r
+\r
+/* Just used to walk through the program memory in order that some random data\r
+can be generated. */\r
+#define mainTOTAL_PROGRAM_MEMORY ( ( unsigned portLONG * ) ( 8 * 1024 ) )\r
+#define mainFIRST_PROGRAM_BYTES ( ( unsigned portLONG * ) 4 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The task that rotates text on the LCD.\r
+ */\r
+static void vLCDTask( void * pvParameters );\r
+\r
+/*\r
+ * The task that receives the characters from UART 0.\r
+ */\r
+static void vCommsRxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex );\r
+\r
+/*\r
+ * The co-routine that periodically initiates the transmission of the string on\r
+ * the UART.\r
+ */\r
+static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex );\r
+\r
+/* \r
+ * Writes a string the the LCD.\r
+ */\r
+static void prvWriteString( const portCHAR *pcString );\r
+\r
+/*\r
+ * Initialisation routine for the UART.\r
+ */\r
+static void vSerialInit( void );\r
+\r
+/*\r
+ * Thread safe write to the PDC.\r
+ */\r
+static void prvPDCWrite( portCHAR cAddress, portCHAR cData );\r
+\r
+/*\r
+ * Function to simply set a known value into the general purpose registers\r
+ * then read them back to ensure they remain set correctly. An incorrect value\r
+ * being indicative of an error in the task switching mechanism.\r
+ */\r
+void prvSetAndCheckRegisters( void );\r
+\r
+/*\r
+ * Latch the LED that indicates that an error has occurred. \r
+ */\r
+void vSetErrorLED( void );\r
+\r
+/*\r
+ * Sets up the PLL and ports used by the demo.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Error flag set to pdFAIL if an error is encountered in the tasks/co-routines\r
+defined within this file. */\r
+unsigned portBASE_TYPE uxErrorStatus = pdPASS;\r
+\r
+/* The next character to transmit. */\r
+static portCHAR cNextChar;\r
+\r
+/* The queue used to transmit characters from the interrupt to the Comms Rx\r
+task. */\r
+static xQueueHandle xCommsQueue;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+int main( void )\r
+{\r
+ /* Create the queue used to communicate between the UART ISR and the Comms\r
+ Rx task. */\r
+ xCommsQueue = xQueueCreate( mainRX_QUEUE_LEN, sizeof( portCHAR ) );\r
+\r
+ /* Setup the ports used by the demo and the clock. */\r
+ prvSetupHardware();\r
+\r
+ /* Create the co-routines that flash the LED's. */\r
+ vStartFlashCoRoutines( mainNUM_FLASH_CO_ROUTINES );\r
+\r
+ /* Create the co-routine that initiates the transmission of characters\r
+ on the UART. */\r
+ xCoRoutineCreate( vSerialTxCoRoutine, mainTX_CO_ROUTINE_PRIORITY, mainTX_CO_ROUTINE_INDEX );\r
+\r
+ /* Create the co-routine that receives characters from the UART. */\r
+ xCoRoutineCreate( vCommsRxCoRoutine, mainRX_CO_ROUTINE_PRIORITY, mainRX_CO_ROUTINE_INDEX );\r
+\r
+ /* Create the LCD task. */\r
+ xTaskCreate( vLCDTask, "LCD", configMINIMAL_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL );\r
+\r
+ /* Start the scheduler running the tasks and co-routines just created. */\r
+ vTaskStartScheduler();\r
+\r
+ /* Should not get here unless we did not have enough memory to start the\r
+ scheduler. */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+ /* Setup the PLL. */\r
+ SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ );\r
+\r
+ /* Initialise the hardware used to talk to the LCD, LED's and UART. */\r
+ PDCInit();\r
+ vParTestInitialise();\r
+ vSerialInit();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationIdleHook( void )\r
+{\r
+ /* The co-routines are executed in the idle task using the idle task \r
+ hook. */\r
+ for( ;; )\r
+ {\r
+ /* Schedule the co-routines. */\r
+ vCoRoutineSchedule();\r
+\r
+ /* Run the register check function between each co-routine. */\r
+ prvSetAndCheckRegisters();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvWriteString( const portCHAR *pcString )\r
+{\r
+ /* Write pcString to the LED, pausing between each character. */\r
+ prvPDCWrite(PDC_LCD_CSR, LCD_CLEAR); \r
+ while( *pcString )\r
+ {\r
+ vTaskDelay( mainCHAR_WRITE_DELAY );\r
+ prvPDCWrite( PDC_LCD_RAM, *pcString );\r
+ pcString++;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vLCDTask( void * pvParameters )\r
+{\r
+unsigned portBASE_TYPE uxIndex;\r
+const unsigned portCHAR ucCFGData[] = { \r
+ 0x30, /* Set data bus to 8-bits. */\r
+ 0x30,\r
+ 0x30,\r
+ 0x3C, /* Number of lines/font. */\r
+ 0x08, /* Display off. */\r
+ 0x01, /* Display clear. */\r
+ 0x06, /* Entry mode [cursor dir][shift]. */\r
+ 0x0C /* Display on [display on][curson on][blinking on]. */\r
+ }; \r
+\r
+/* The strings that are written to the LCD. */\r
+const portCHAR *pcStringsToDisplay[] = { \r
+ "Stellaris",\r
+ "Demo",\r
+ "Two",\r
+ "www.FreeRTOS.org",\r
+ ""\r
+ };\r
+\r
+ /* Configure the LCD. */\r
+ uxIndex = 0;\r
+ while( uxIndex < sizeof( ucCFGData ) )\r
+ {\r
+ prvPDCWrite( PDC_LCD_CSR, ucCFGData[ uxIndex ] );\r
+ uxIndex++;\r
+ vTaskDelay( mainCHAR_WRITE_DELAY );\r
+ }\r
+\r
+ /* Turn the LCD Backlight on. */\r
+ prvPDCWrite( PDC_CSR, 0x01 );\r
+\r
+ /* Clear display. */\r
+ vTaskDelay( mainCHAR_WRITE_DELAY );\r
+ prvPDCWrite( PDC_LCD_CSR, LCD_CLEAR ); \r
+\r
+ uxIndex = 0;\r
+ for( ;; ) \r
+ {\r
+ /* Display the string on the LCD. */\r
+ prvWriteString( pcStringsToDisplay[ uxIndex ] );\r
+ \r
+ /* Move on to the next string - wrapping if necessary. */\r
+ uxIndex++;\r
+ if( *( pcStringsToDisplay[ uxIndex ] ) == 0x00 )\r
+ {\r
+ uxIndex = 0;\r
+ /* Longer pause on the last string to be sent. */\r
+ vTaskDelay( mainSTRING_WRITE_DELAY * 2 );\r
+ }\r
+\r
+ /* Wait until it is time to move onto the next string. */\r
+ vTaskDelay( mainSTRING_WRITE_DELAY );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vCommsRxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )\r
+{\r
+static portCHAR cRxedChar, cExpectedChar = mainFIRST_TX_CHAR;\r
+portBASE_TYPE xResult;\r
+\r
+ crSTART( xHandle );\r
+\r
+ for( ;; )\r
+ {\r
+ /* Wait for a character to be received. */\r
+ crQUEUE_RECEIVE( xHandle, xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY, &xResult );\r
+\r
+ /* Was the character recived (if any) the expected character. */\r
+ if( ( cRxedChar != cExpectedChar ) || ( xResult != pdPASS ) )\r
+ {\r
+ /* Got an unexpected character. This can sometimes occur when\r
+ reseting the system using the debugger leaving characters already\r
+ in the UART regsters. */\r
+ uxErrorStatus = pdFAIL;\r
+\r
+ /* Resync by waiting for the end of the current string. */\r
+ while( cRxedChar != mainLAST_TX_CHAR )\r
+ {\r
+ crQUEUE_RECEIVE( xHandle, xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY, &xResult );\r
+ }\r
+\r
+ /* The next expected character is the start of the string again. */\r
+ cExpectedChar = mainFIRST_TX_CHAR;\r
+ }\r
+ else\r
+ {\r
+ if( cExpectedChar == mainLAST_TX_CHAR )\r
+ {\r
+ /* We have reached the end of the string - we now expect to \r
+ receive the first character in the string again. The LED is \r
+ toggled to indicate that the entire string was received without\r
+ error. */\r
+ vParTestToggleLED( mainCOMMS_RX_LED );\r
+ cExpectedChar = mainFIRST_TX_CHAR;\r
+ }\r
+ else\r
+ {\r
+ /* We got the expected character, we now expect to receive the\r
+ next character in the string. */\r
+ cExpectedChar++;\r
+ }\r
+ }\r
+ }\r
+\r
+ crEND();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )\r
+{\r
+portTickType xDelayPeriod;\r
+static unsigned portLONG *pulRandomBytes = mainFIRST_PROGRAM_BYTES;\r
+\r
+ /* Co-routine MUST start with a call to crSTART. */\r
+ crSTART( xHandle );\r
+\r
+ for(;;)\r
+ { \r
+ /* Was the previously transmitted string received correctly? */\r
+ if( uxErrorStatus != pdPASS )\r
+ {\r
+ /* An error was encountered so set the error LED. */\r
+ vSetErrorLED();\r
+ }\r
+\r
+ /* The next character to Tx is the first in the string. */\r
+ cNextChar = mainFIRST_TX_CHAR;\r
+\r
+ UARTIntDisable( UART0_BASE, UART_INT_TX );\r
+ {\r
+ /* Send the first character. */\r
+ if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) )\r
+ {\r
+ HWREG( UART0_BASE + UART_O_DR ) = cNextChar;\r
+ }\r
+\r
+ /* Move the variable to the char to Tx on so the ISR transmits\r
+ the next character in the string once this one has completed. */\r
+ cNextChar++;\r
+ }\r
+ UARTIntEnable(UART0_BASE, UART_INT_TX);\r
+\r
+ /* Toggle the LED to show a new string is being transmitted. */\r
+ vParTestToggleLED( mainCOMMS_TX_LED );\r
+\r
+ /* Delay before we start the string off again. A pseudo-random delay\r
+ is used as this will provide a better test. */\r
+ xDelayPeriod = xTaskGetTickCount() + ( *pulRandomBytes );\r
+\r
+ pulRandomBytes++;\r
+ if( pulRandomBytes > mainTOTAL_PROGRAM_MEMORY )\r
+ {\r
+ pulRandomBytes = mainFIRST_PROGRAM_BYTES;\r
+ }\r
+\r
+ /* Make sure we don't wait too long... */\r
+ xDelayPeriod &= mainMAX_TX_DELAY;\r
+\r
+ /* ...but we do want to wait. */\r
+ if( xDelayPeriod < mainMIN_TX_DELAY )\r
+ {\r
+ xDelayPeriod = mainMIN_TX_DELAY;\r
+ }\r
+\r
+ /* Block for the random(ish) time. */\r
+ crDELAY( xHandle, xDelayPeriod );\r
+ }\r
+\r
+ /* Co-routine MUST end with a call to crEND. */\r
+ crEND();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vSerialInit( void )\r
+{\r
+ /* Enable the UART. GPIOA has already been initialised. */\r
+ SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);\r
+\r
+ /* Set GPIO A0 and A1 as peripheral function. They are used to output the\r
+ UART signals. */\r
+ GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW );\r
+\r
+ /* Configure the UART for 8-N-1 operation. */\r
+ UARTConfigSet( UART0_BASE, mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE );\r
+\r
+ /* We dont want to use the fifo. This is for test purposes to generate\r
+ as many interrupts as possible. */\r
+ HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET;\r
+\r
+ /* Enable both Rx and Tx interrupts. */\r
+ HWREG( UART0_BASE + UART_O_IM ) |= ( UART_INT_TX | UART_INT_RX );\r
+ IntEnable( INT_UART0 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vUART_ISR(void)\r
+{\r
+unsigned portLONG ulStatus;\r
+portCHAR cRxedChar;\r
+portBASE_TYPE xTaskWokenByPost = pdFALSE;\r
+\r
+ /* What caused the interrupt. */\r
+ ulStatus = UARTIntStatus( UART0_BASE, pdTRUE );\r
+\r
+ /* Clear the interrupt. */\r
+ UARTIntClear( UART0_BASE, ulStatus );\r
+\r
+ /* Was an Rx interrpt pending? */\r
+ if( ulStatus & UART_INT_RX )\r
+ {\r
+ if( ( HWREG(UART0_BASE + UART_O_FR ) & UART_FR_RXFF ) )\r
+ {\r
+ /* Get the char from the buffer and post it onto the queue of\r
+ Rxed chars. Posting the character should wake the task that is \r
+ blocked on the queue waiting for characters. */\r
+ cRxedChar = ( portCHAR ) HWREG( UART0_BASE + UART_O_DR );\r
+ xTaskWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsQueue, &cRxedChar, xTaskWokenByPost );\r
+ } \r
+ }\r
+\r
+ /* Was a Tx interrupt pending? */\r
+ if( ulStatus & UART_INT_TX )\r
+ {\r
+ /* Send the next character in the string. We are not using the FIFO. */\r
+ if( cNextChar <= mainLAST_TX_CHAR )\r
+ {\r
+ if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) )\r
+ {\r
+ HWREG( UART0_BASE + UART_O_DR ) = cNextChar;\r
+ }\r
+ cNextChar++;\r
+ }\r
+ }\r
+ \r
+ if( xTaskWokenByPost )\r
+ {\r
+ /* We are posting to a co-routine rather than a task so don't bother\r
+ causing a task switch. */\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvPDCWrite( portCHAR cAddress, portCHAR cData )\r
+{\r
+ vTaskSuspendAll();\r
+ {\r
+ PDCWrite( cAddress, cData );\r
+ }\r
+ xTaskResumeAll();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSetErrorLED( void )\r
+{\r
+ vParTestSetLED( mainCOMMS_FAIL_LED, pdTRUE );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+__asm void prvSetAndCheckRegisters( void )\r
+{\r
+ extern vSetErrorLED\r
+\r
+ /* Fill the general purpose registers with known values. */\r
+ mov r11, #10\r
+ add r0, r11, #1\r
+ add r1, r11, #2\r
+ add r2, r11, #3\r
+ add r3, r11, #4\r
+ add r4, r11, #5\r
+ add r5, r11, #6\r
+ add r6, r11, #7\r
+ add r7, r11, #8\r
+ add r8, r11, #9\r
+ add r9, r11, #10\r
+ add r10, r11, #11\r
+ add r12, r11, #12\r
+\r
+ /* Check the values are as expected. */\r
+ cmp r11, #10\r
+ bne set_error_led\r
+ cmp r0, #11\r
+ bne set_error_led\r
+ cmp r1, #12\r
+ bne set_error_led\r
+ cmp r2, #13\r
+ bne set_error_led\r
+ cmp r3, #14\r
+ bne set_error_led\r
+ cmp r4, #15\r
+ bne set_error_led\r
+ cmp r5, #16\r
+ bne set_error_led\r
+ cmp r6, #17\r
+ bne set_error_led\r
+ cmp r7, #18\r
+ bne set_error_led\r
+ cmp r8, #19\r
+ bne set_error_led\r
+ cmp r9, #20\r
+ bne set_error_led\r
+ cmp r10, #21\r
+ bne set_error_led\r
+ cmp r12, #22\r
+ bne set_error_led\r
+ bx lr\r
+\r
+set_error_led;\r
+ push {r14}\r
+ ldr r1, =vSetErrorLED\r
+ blx r1\r
+ pop {r14}\r
+ bx lr;\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+Move these two fines into the Demo/CORTEX_LM3S102_KEIL directory to run Demo 2.\r
+\r
+See the port documentation on the www.FreeRTOS.org site for more information.\r
--- /dev/null
+### uVision2 Project, (C) Keil Software\r
+### Do not modify !\r
+\r
+ cExt (*.c)\r
+ aExt (*.s*; *.src; *.a*)\r
+ oExt (*.obj)\r
+ lExt (*.lib)\r
+ tExt (*.txt; *.h; *.inc)\r
+ pExt (*.plm)\r
+ CppX (*.cpp)\r
+ DaveTm { 0,0,0,0,0,0,0,0 }\r
+\r
+Target (LM3S1xx), 0x0004 // Tools: 'ARM-ADS'\r
+GRPOPT 1,(Source),1,0,0\r
+GRPOPT 2,(Demo),1,0,0\r
+\r
+OPTFFF 1,1,1,0,0,0,0,0,<..\..\Source\croutine.c><croutine.c> \r
+OPTFFF 1,2,1,0,0,0,0,0,<..\..\Source\list.c><list.c> \r
+OPTFFF 1,3,1,0,0,0,0,0,<..\..\Source\queue.c><queue.c> \r
+OPTFFF 1,4,1,0,0,0,0,0,<..\..\Source\tasks.c><tasks.c> \r
+OPTFFF 1,5,1,0,0,0,0,0,<..\..\Source\portable\MemMang\heap_1.c><heap_1.c> \r
+OPTFFF 1,6,1,0,0,0,0,0,<..\..\Source\portable\RVDS\ARM_CM3\port.c><port.c> \r
+OPTFFF 2,7,1,0,0,0,0,0,<.\main.c><main.c> \r
+OPTFFF 2,8,2,0,0,0,0,0,<.\init\Startup.s><Startup.s> \r
+OPTFFF 2,9,1,0,0,0,0,0,<..\Common\Minimal\crflash.c><crflash.c> \r
+OPTFFF 2,10,1,0,0,0,0,0,<.\ParTest\ParTest.c><ParTest.c> \r
+OPTFFF 2,11,1,0,0,0,0,0,<.\include\pdc.c><pdc.c> \r
+OPTFFF 2,12,4,0,0,0,0,0,<C:\Keil\ARM\RV30\LIB\Luminary\DriverLib.lib><DriverLib.lib> \r
+\r
+\r
+TARGOPT 1, (LM3S1xx)\r
+ ADSCLK=20000000\r
+ OPTTT 1,1,1,0\r
+ OPTHX 1,65535,0,0,0\r
+ OPTLX 79,66,8,<.\uvision\>\r
+ OPTOX 16\r
+ OPTLT 1,1,1,0,1,1,0,1,0,0,0,0\r
+ OPTXL 1,1,1,1,1,1,1,0,0\r
+ OPTFL 1,0,1\r
+ OPTDL (SARMCM3.DLL)()(DLM.DLL)(-pLM3S101)(SARMCM3.DLL)()(TLM.DLL)(-pLM3S101)\r
+ OPTDBG 49150,1,()()()()()()()()()() (BIN\UL2CM3.DLL)()()()\r
+ OPTKEY 0,(UL2CM3)(-U -O14 -S0 -C-1 -FO7 -FD20000000 -FC800 -FN1 -FF0LM3S_8 -FS00 -FL02000)\r
+ OPTDF 0x0\r
+ OPTLE <>\r
+ OPTLC <>\r
+EndOpt\r
+\r
--- /dev/null
+### uVision2 Project, (C) Keil Software\r
+### Do not modify !\r
+\r
+Target (LM3S1xx), 0x0004 // Tools: 'ARM-ADS'\r
+\r
+Group (Source)\r
+Group (Demo)\r
+\r
+File 1,1,<..\..\Source\croutine.c><croutine.c> 0x440790D8 \r
+File 1,1,<..\..\Source\list.c><list.c> 0x440790D8 \r
+File 1,1,<..\..\Source\queue.c><queue.c> 0x440790D8 \r
+File 1,1,<..\..\Source\tasks.c><tasks.c> 0x440790D8 \r
+File 1,1,<..\..\Source\portable\MemMang\heap_1.c><heap_1.c> 0x440790D8 \r
+File 1,1,<..\..\Source\portable\RVDS\ARM_CM3\port.c><port.c> 0x440790D8 \r
+File 2,1,<.\main.c><main.c> 0x441EE317 \r
+File 2,2,<.\init\Startup.s><Startup.s> 0x44172A20 \r
+File 2,1,<..\Common\Minimal\crflash.c><crflash.c> 0x440790D8 \r
+File 2,1,<.\ParTest\ParTest.c><ParTest.c> 0x440790D8 \r
+File 2,1,<.\include\pdc.c><pdc.c> 0x44187439 \r
+File 2,4,<C:\Keil\ARM\RV30\LIB\Luminary\DriverLib.lib><DriverLib.lib> 0x44206F94 \r
+\r
+\r
+Options 1,0,0 // Target 'LM3S1xx'\r
+ Device (LM3S101)\r
+ Vendor (Luminary Micro)\r
+ Cpu (IRAM(0x20000000-0x200007FF) IROM(0-0x1FFF) CLOCK(20000000) CPUTYPE("Cortex-M3"))\r
+ FlashUt ()\r
+ StupF ("STARTUP\Luminary\Startup.s" ("Luminary Startup Code"))\r
+ FlashDR (UL2CM3(-U40296420 -O7 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0LM3S_8 -FS00 -FL02000))\r
+ DevID (4079)\r
+ Rgf (LM3Sxxx.H)\r
+ Mem ()\r
+ C ()\r
+ A ()\r
+ RL ()\r
+ OH ()\r
+ DBC_IFX ()\r
+ DBC_CMS ()\r
+ DBC_AMS ()\r
+ DBC_LMS ()\r
+ UseEnv=0\r
+ EnvBin ()\r
+ EnvInc ()\r
+ EnvLib ()\r
+ EnvReg (ÿLuminary\)\r
+ OrgReg (ÿLuminary\)\r
+ TgStat=0\r
+ OutDir (.\uvision\)\r
+ OutName (RTOSDemo)\r
+ GenApp=1\r
+ GenLib=0\r
+ GenHex=0\r
+ Debug=1\r
+ Browse=1\r
+ LstDir (.\uvision\)\r
+ HexSel=1\r
+ MG32K=0\r
+ TGMORE=0\r
+ RunUsr 0 0 <>\r
+ RunUsr 1 0 <>\r
+ BrunUsr 0 0 <>\r
+ BrunUsr 1 0 <>\r
+ SVCSID <>\r
+ GLFLAGS=1790\r
+ ADSFLGA { 243,31,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ ACPUTYP (Cortex-M3)\r
+ ADSTFLGA { 0,12,0,0,99,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ OCMADSOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ OCMADSIRAM { 0,0,0,0,32,0,8,0,0 }\r
+ OCMADSIROM { 1,0,0,0,0,0,32,0,0 }\r
+ OCMADSXRAM { 0,0,0,0,0,0,0,0,0 }\r
+ OCR_RVCT { 1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,32,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,8,0,0,0,0,0,0,0,0,0,0,0 }\r
+ RV_STAVEC ()\r
+ ADSCCFLG { 8,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ ADSCMISC ()\r
+ ADSCDEFN (RVDS_ARMCM3_LM3S102)\r
+ ADSCUDEF ()\r
+ ADSCINCD (C:\Keil\ARM\RV30\LIB\Luminary;..\CORTEX_LM3S102_KEIL;..\..\Source\portable\RVDS\ARM_CM3;..\..\Source\include;..\Common\include;.\include)\r
+ ADSASFLG { 65,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ ADSAMISC (--diag_suppress 1581)\r
+ ADSADEFN ()\r
+ ADSAUDEF ()\r
+ ADSAINCD ()\r
+ PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ IncBld=1\r
+ AlwaysBuild=0\r
+ GenAsm=0\r
+ AsmAsm=0\r
+ PublicsOnly=0\r
+ StopCode=3\r
+ CustArgs ()\r
+ LibMods ()\r
+ ADSLDFG { 16,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ ADSLDTA (0x00000000)\r
+ ADSLDDA (0x20000000)\r
+ ADSLDSC ()\r
+ ADSLDIB ()\r
+ ADSLDIC ()\r
+ ADSLDMC (--entry Reset_Handler)\r
+ ADSLDIF ()\r
+ ADSLDDW (6306)\r
+ OPTDL (SARMCM3.DLL)()(DLM.DLL)(-pLM3S101)(SARMCM3.DLL)()(TLM.DLL)(-pLM3S101)\r
+ OPTDBG 49150,1,()()()()()()()()()() (BIN\UL2CM3.DLL)()()()\r
+ FLASH1 { 1,0,0,0,1,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0 }\r
+ FLASH2 (BIN\UL2CM3.DLL)\r
+ FLASH3 ("" ())\r
+ FLASH4 ()\r
+EndOpt\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. \r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 1\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 20000000 )\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 59 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1468 ) )\r
+#define configMAX_TASK_NAME_LEN ( 3 )\r
+#define configUSE_TRACE_FACILITY 0\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 0\r
+#define configUSE_CO_ROUTINES 1\r
+\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 )\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet 0\r
+#define INCLUDE_uxTaskPriorityGet 0\r
+#define INCLUDE_vTaskDelete 0\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 0\r
+#define INCLUDE_vTaskDelayUntil 0\r
+#define INCLUDE_vTaskDelay 1\r
+\r
+\r
+\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple parallel port IO routines.\r
+ *-----------------------------------------------------------*/\r
+\r
+/*\r
+*/\r
+\r
+\r
+#include "FreeRTOS.h"\r
+#include "Task.h"\r
+#include "partest.h"\r
+\r
+#include "pdc.h"\r
+\r
+#define partstPINS (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 Z | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7)\r
+\r
+#define partstALL_OUTPUTS_OFF ( ( unsigned portCHAR ) 0x00 )\r
+#define partstMAX_OUTPUT_LED ( ( unsigned portCHAR ) 8 )\r
+\r
+static volatile unsigned portCHAR ucOutputValue = partstALL_OUTPUTS_OFF;\r
+\r
+void vParTestInitialise( void )\r
+{\r
+ PDCInit();\r
+ PDCWrite( PDC_LED, ucOutputValue );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )\r
+{\r
+unsigned portCHAR ucBit = ( unsigned portCHAR ) 1;\r
+\r
+ vTaskSuspendAll();\r
+ {\r
+ if( uxLED < partstMAX_OUTPUT_LED )\r
+ {\r
+ ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED;\r
+\r
+ if( xValue == pdFALSE )\r
+ {\r
+ ucBit ^= ( unsigned portCHAR ) 0xff;\r
+ ucOutputValue &= ucBit;\r
+ }\r
+ else\r
+ {\r
+ ucOutputValue |= ucBit;\r
+ }\r
+\r
+ PDCWrite( PDC_LED, ucOutputValue );\r
+ } \r
+ }\r
+ xTaskResumeAll();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+unsigned portCHAR ucBit;\r
+\r
+ vTaskSuspendAll();\r
+ {\r
+ if( uxLED < partstMAX_OUTPUT_LED )\r
+ {\r
+ ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED;\r
+\r
+ if( ucOutputValue & ucBit )\r
+ {\r
+ ucOutputValue &= ~ucBit;\r
+ }\r
+ else\r
+ {\r
+ ucOutputValue |= ucBit;\r
+ }\r
+\r
+ PDCWrite( PDC_LED, ucOutputValue );\r
+ }\r
+ }\r
+ xTaskResumeAll();\r
+}\r
+\r
--- /dev/null
+//*****************************************************************************
+//
+// pdc.c - Driver for the Peripheral Device Controller (PDC) on the Stellaris
+// development board.
+//
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
+//
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's Stellaris Family of microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. Any use in violation
+// of the foregoing restrictions may subject the user to criminal sanctions
+// under applicable laws, as well as to civil liability for the breach of the
+// terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+//*****************************************************************************
+
+#include "LM3Sxxx.h"
+#include "pdc.h"
+
+//*****************************************************************************
+//
+//! Initializes the connection to the PDC.
+//!
+//! This function will enable clocking to the SSI and GPIO A modules, configure
+//! the GPIO pins to be used for an SSI interface, and it will configure the
+//! SSI as a 1Mb master device, operating in MOTO mode. It will also enable
+//! the SSI module, and will enable the chip select for the PDC on the
+//! Stellaris development board.
+//!
+//! This function is contained in <tt>utils/pdc.c</tt>, with
+//! <tt>utils/pdc.h</tt> containing the API definition for use by applications.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PDCInit(void)
+{
+ //
+ // Enable the peripherals used to drive the PDC.
+ //
+ SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI);
+ SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
+
+ //
+ // Configure the appropriate pins to be SSI instead of GPIO.
+ //
+ GPIODirModeSet(GPIO_PORTA_BASE, SSI_CLK | SSI_TX | SSI_RX,
+ GPIO_DIR_MODE_HW);
+ GPIODirModeSet(GPIO_PORTA_BASE, SSI_CS, GPIO_DIR_MODE_OUT);
+ GPIOPadConfigSet(GPIO_PORTA_BASE, SSI_CLK, GPIO_STRENGTH_4MA,
+ GPIO_PIN_TYPE_STD_WPU);
+
+ //
+ // Configure the SSI port.
+ //
+ SSIConfig(SSI_BASE, SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 1000000, 8);
+ SSIEnable(SSI_BASE);
+
+ //
+ // Reset the PDC SSI state machine. The chip select needs to be held low
+ // for 100ns; the procedure call overhead more than accounts for this time.
+ //
+ GPIOPinWrite(GPIO_PORTA_BASE, PDC_CS, 0);
+ GPIOPinWrite(GPIO_PORTA_BASE, PDC_CS, PDC_CS);
+}
+
+//*****************************************************************************
+//
+//! Write a PDC register.
+//!
+//! \param ucAddr specifies the PDC register to write.
+//! \param ucData specifies the data to write.
+//!
+//! This function will perform the SSI transfers required to write a register
+//! in the PDC on the Stellaris development board.
+//!
+//! This function is contained in <tt>utils/pdc.c</tt>, with
+//! <tt>utils/pdc.h</tt> containing the API definition for use by applications.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PDCWrite(unsigned char ucAddr, unsigned char ucData)
+{
+ unsigned long ulTemp;
+
+ //
+ // Send address and write command.
+ //
+ SSIDataPut(SSI_BASE, (ucAddr & 0x0F) | PDC_WR);
+
+ //
+ // Write the data.
+ //
+ SSIDataPut(SSI_BASE, ucData);
+
+ //
+ // Flush data read during address write.
+ //
+ SSIDataGet(SSI_BASE, &ulTemp);
+
+ //
+ // Flush data read during data write.
+ //
+ SSIDataGet(SSI_BASE, &ulTemp);
+}\r
--- /dev/null
+//*****************************************************************************
+//
+// pdc.h - Stellaris development board Peripheral Device Controller definitions
+// and prototypes.
+//
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
+//
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's Stellaris Family of microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. Any use in violation
+// of the foregoing restrictions may subject the user to criminal sanctions
+// under applicable laws, as well as to civil liability for the breach of the
+// terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+//*****************************************************************************
+
+#ifndef __PDC_H__
+#define __PDC_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// The registers within the peripheral device controller.
+//
+//*****************************************************************************
+#define PDC_VER 0x0 // Version register
+#define PDC_CSR 0x1 // Command/Status register
+#define PDC_DSW 0x4 // DIP Switch register
+#define PDC_LED 0x5 // LED register
+#define PDC_LCD_CSR 0x6 // LCD Command/Status register
+#define PDC_LCD_RAM 0x7 // LCD RAM register
+#define PDC_GPXDAT 0x8 // GPIO X Data register
+#define PDC_GPXDIR 0x9 // GPIO X Direction register
+#define PDC_GPYDAT 0xA // GPIO Y Data register
+#define PDC_GPYDIR 0xB // GPIO Y Direction register
+#define PDC_GPZDAT 0xC // GPIO Z Data register
+#define PDC_GPZDIR 0xD // GPIO Z Direction register
+
+//*****************************************************************************
+//
+// Flags indicating a read or write to the peripheral device controller.
+//
+//*****************************************************************************
+#define PDC_RD 0x80 // PDC read command
+#define PDC_WR 0x00 // PDC write command
+
+//*****************************************************************************
+//
+// LCD panel (Crystalfontz CFAH1602B) commands, RS = 0
+//
+//*****************************************************************************
+#define LCD_CLEAR 0x01 // Clear display (0 fill DDRAM).
+#define LCD_HOME 0x02 // Cursor home.
+#define LCD_MODE 0x04 // Set entry mode (cursor dir)
+#define LCD_ON 0x08 // Set display, cursor, blinking
+ // on/off
+#define LCD_CUR 0x10 // Cursor, display shift
+#define LCD_IF 0x20 // Set interface data length,
+ // lines, font
+#define LCD_CGADDR 0x40 // Set CGRAM AC address
+#define LCD_DDADDR 0x80 // Set DDRAM AC address
+
+//*****************************************************************************
+//
+// LCD Status bit
+//
+//*****************************************************************************
+#define LCD_B_BUSY 0x80 // Busy flag.
+
+//*****************************************************************************
+//
+// The GPIO port A pin numbers for the various SSI signals.
+//
+//*****************************************************************************
+#define SSI_CS GPIO_PIN_3
+#define PDC_CS GPIO_PIN_3
+#define SSI_CLK GPIO_PIN_2
+#define SSI_TX GPIO_PIN_5
+#define SSI_RX GPIO_PIN_4
+
+//*****************************************************************************
+//
+// Function Prototypes
+//
+//*****************************************************************************
+extern void PDCInit(void);
+extern unsigned char PDCRead(unsigned char ucAddr);
+extern void PDCWrite(unsigned char ucAddr, unsigned char ucData);
+extern unsigned char PDCDIPRead(void);
+extern void PDCLEDWrite(unsigned char ucLED);
+extern unsigned char PDCLEDRead(void);
+extern void PDCLCDInit(void);
+extern void PDCLCDBacklightOn(void);
+extern void PDCLCDBacklightOff(void);
+extern void PDCLCDClear(void);
+extern void PDCLCDCreateChar(unsigned char ucChar, unsigned char *pucData);
+extern void PDCLCDSetPos(unsigned char ucX, unsigned char ucY);
+extern void PDCLCDWrite(const char *pcStr, unsigned long ulCount);
+extern unsigned char PDCGPIODirRead(unsigned char ucIdx);
+extern void PDCGPIODirWrite(unsigned char ucIdx, unsigned char ucValue);
+extern unsigned char PDCGPIORead(unsigned char ucIdx);
+extern void PDCGPIOWrite(unsigned char ucIdx, unsigned char ucValue);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __PDC_H__
--- /dev/null
+;/*****************************************************************************/\r
+;/* STARTUP.S: Startup file for Luminary Micro LM3Sxxx */\r
+;/*****************************************************************************/\r
+;/* <<< Use Configuration Wizard in Context Menu >>> */ \r
+;/*****************************************************************************/\r
+;/* This file is part of the uVision/ARM development tools. */\r
+;/* Copyright (c) 2005-2006 Keil Software. All rights reserved. */\r
+;/* This software may only be used under the terms of a valid, current, */\r
+;/* end user licence from KEIL for a compatible version of KEIL software */\r
+;/* development tools. Nothing else gives you the right to use this software. */\r
+;/*****************************************************************************/\r
+\r
+\r
+;/*\r
+; * The STARTUP.S code is executed after CPU Reset. \r
+; */\r
+\r
+\r
+;// <h> Stack Configuration\r
+;// <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
+;// </h>\r
+\r
+Stack_Size EQU 51\r
+\r
+ AREA STACK, NOINIT, READWRITE, ALIGN=3\r
+Stack_Mem SPACE Stack_Size\r
+\r
+\r
+;// <h> Heap Configuration\r
+;// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
+;// </h>\r
+\r
+Heap_Size EQU 0x00000000\r
+\r
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3\r
+Heap_Mem SPACE Heap_Size\r
+\r
+\r
+; System Control Register Addresses\r
+SYSCTL_BASE EQU 0x400FE000 ; System Control Base Address\r
+PBORCTL_OFS EQU 0x0030 ; Power-On & Brown-Out Reset Control\r
+LDOPC_OFS EQU 0x0034 ; LDO Power\r
+SRCR0_OFS EQU 0x0040 ; Software Reset Control 0\r
+SRCR1_OFS EQU 0x0044 ; Software Reset Control 1\r
+SRCR2_OFS EQU 0x0048 ; Software Reset Control 2\r
+RCC_OFS EQU 0x0060 ; Run-Mode Clock Control\r
+RCGC0_OFS EQU 0x0100 ; Run-Mode Clock Gating Control 0\r
+RCGC1_OFS EQU 0x0104 ; Run-Mode Clock Gating Control 1\r
+RCGC2_OFS EQU 0x0108 ; Run-Mode Clock Gating Control 2\r
+SCGC0_OFS EQU 0x0110 ; Sleep-Mode Clock Gating Control 0\r
+SCGC1_OFS EQU 0x0114 ; Sleep-Mode Clock Gating Control 1\r
+SCGC2_OFS EQU 0x0118 ; Sleep-Mode Clock Gating Control 2\r
+DCGC0_OFS EQU 0x0120 ; Deep-Sleep-Mode Clock Gating Control 0\r
+DCGC1_OFS EQU 0x0124 ; Deep-Sleep-Mode Clock Gating Control 1\r
+DCGC2_OFS EQU 0x0128 ; Deep-Sleep-Mode Clock Gating Control 2\r
+\r
+\r
+ PRESERVE8\r
+ \r
+\r
+; Area Definition and Entry Point\r
+; Startup Code must be linked first at Address 0.\r
+\r
+ AREA RESET, CODE, READONLY\r
+ THUMB\r
+\r
+ IMPORT xPortPendSVHandler\r
+ IMPORT xPortSysTickHandler\r
+ IMPORT vUART_ISR\r
+\r
+; Vector Table\r
+Vectors DCD Stack_Mem + Stack_Size ; Top of Stack\r
+ DCD Reset_Handler ; Reset Handler\r
+ DCD NmiSR ; NMI Handler\r
+ DCD DefaultISR ; Hard Fault Handler\r
+ DCD DefaultISR ; MPU Fault Handler\r
+ DCD DefaultISR ; Bus Fault Handler\r
+ DCD DefaultISR ; Usage Fault Handler\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; SVCall Handler\r
+ DCD DefaultISR ; Debug Monitor Handler\r
+ DCD 0 ; Reserved\r
+ DCD xPortPendSVHandler ; PendSV Handler\r
+ DCD xPortSysTickHandler ; SysTick Handler\r
+ DCD DefaultISR ; GPIO Port A Handler\r
+ DCD DefaultISR ; GPIO Port B Handler\r
+ DCD DefaultISR ; GPIO Port C Handler\r
+ DCD DefaultISR ; GPIO Port D Handler\r
+ DCD DefaultISR ; GPIO Port E Handler\r
+ DCD vUART_ISR ; UART0 Rx/Tx Handler\r
+ DCD DefaultISR ; UART1 Rx/Tx Handler\r
+ DCD DefaultISR ; SSI Rx/Tx Handler\r
+ DCD DefaultISR ; I2C Master/Slave Handler\r
+ DCD DefaultISR ; PWM Fault Handler\r
+ DCD DefaultISR ; PWM Generator 0 Handler\r
+ DCD DefaultISR ; PWM Generator 1 Handler\r
+ DCD DefaultISR ; PWM Generator 2 Handler\r
+ DCD DefaultISR ; Quadrature Encoder Handler\r
+ DCD DefaultISR ; ADC Sequence 0 Handler\r
+ DCD DefaultISR ; ADC Sequence 1 Handler\r
+ DCD DefaultISR ; ADC Sequence 2 Handler\r
+ DCD DefaultISR ; ADC Sequence 3 Handler\r
+ DCD DefaultISR ; Watchdog Timer Handler\r
+ DCD DefaultISR ; Timer 0 Subtimer A Handler\r
+ DCD DefaultISR ; Timer 0 Subtimer B Handler\r
+ DCD DefaultISR ; Timer 1 Subtimer A Handler\r
+ DCD DefaultISR ; Timer 1 Subtimer B Handler\r
+ DCD DefaultISR ; Timer 2 Subtimer A Handler\r
+ DCD DefaultISR ; Timer 2 Subtimer B Handler\r
+ DCD DefaultISR ; Analog Comparator 0 Handler\r
+ DCD DefaultISR ; Analog Comparator 1 Handler\r
+ DCD DefaultISR ; Analog Comparator 2 Handler\r
+ DCD DefaultISR ; System Control Handler\r
+ DCD DefaultISR ; Flash Control Handler\r
+\r
+; Dummy Handlers are implemented as infinite loops which can be modified.\r
+\r
+NmiSR B NmiSR\r
+FaultISR B FaultISR\r
+ EXPORT FaultISR\r
+DefaultISR B DefaultISR\r
+\r
+\r
+; Reset Handler\r
+\r
+ EXPORT Reset_Handler\r
+Reset_Handler \r
+\r
+; Enable Clock Gating for Peripherals\r
+; LDR R0, =SYSCTL_BASE ; System Control Base Address\r
+; MVN R1, #0 ; Value 0xFFFFFFFF\r
+; STR R1, [R0,#RCGC0_OFS] ; Run-Mode Clock Gating Ctrl 0\r
+; STR R1, [R0,#RCGC1_OFS] ; Run-Mode Clock Gating Ctrl 1\r
+; STR R1, [R0,#RCGC2_OFS] ; Run-Mode Clock Gating Ctrl 2\r
+\r
+; Enter the C code\r
+\r
+ IMPORT __main\r
+ LDR R0, =__main\r
+ BX R0\r
+\r
+\r
+; User Initial Stack & Heap\r
+ AREA |.text|, CODE, READONLY\r
+\r
+ IMPORT __use_two_region_memory\r
+ EXPORT __user_initial_stackheap\r
+__user_initial_stackheap\r
+\r
+ LDR R0, = Heap_Mem\r
+ LDR R1, =(Stack_Mem + Stack_Size)\r
+ LDR R2, = (Heap_Mem + Heap_Size)\r
+ LDR R3, = Stack_Mem\r
+ BX LR\r
+\r
+ ALIGN\r
+\r
+\r
+ END\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* \r
+ * This demo application creates six co-routines and two tasks (three including \r
+ * the idle task). The co-routines execute as part of the idle task hook.\r
+ *\r
+ * Five of the created co-routines are the standard 'co-routine flash' \r
+ * co-routines contained within the Demo/Common/Minimal/crflash.c file and \r
+ * documented on the FreeRTOS.org WEB site. \r
+ *\r
+ * The 'LCD Task' rotates a string on the LCD, delaying between each character\r
+ * as necessitated by the slow interface, and delaying between each string just\r
+ * long enough to enable the text to be read.\r
+ *\r
+ * The sixth co-routine and final task control the transmission and reception\r
+ * of a string to UART 0. The co-routine periodically sends the first \r
+ * character of the string to the UART, with the UART's TxEnd interrupt being\r
+ * used to transmit the remaining characters. The UART's RxEnd interrupt \r
+ * receives the characters and places them on a queue to be processed by the \r
+ * 'COMs Rx' task. An error is latched should an unexpected character be \r
+ * received, or any character be received out of sequence. \r
+ *\r
+ * A loopback connector is required to ensure that each character transmitted \r
+ * on the UART is also received on the same UART. For test purposes the UART\r
+ * FIFO's are not utalised in order to maximise the interrupt overhead. Also\r
+ * a pseudo random interval is used between the start of each transmission in \r
+ * order that the resultant interrupts are more randomly distributed and \r
+ * therefore more likely to highlight any problems.\r
+ *\r
+ * The flash co-routines control LED's zero to four. LED five is toggled each\r
+ * time the string is transmitted on the UART. LED six is toggled each time\r
+ * the string is CORRECTLY received on the UART. LED seven is latched on should\r
+ * an error be detected in any task or co-routine.\r
+ *\r
+ * In addition the idle task makes repetative calls to \r
+ * prvSetAndCheckRegisters(). This simply loads the general purpose registers \r
+ * with a known value, then checks each register to ensure the held value is \r
+ * still correct. As a low priority task this checking routine is likely to \r
+ * get repeatedly swapped in and out. A register being found to contain an \r
+ * incorrect value is therefore indicative of an error in the task switching \r
+ * mechansim.\r
+ *\r
+ */\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+#include "croutine.h"\r
+\r
+/* Demo application include files. */\r
+#include "partest.h"\r
+#include "crflash.h"\r
+\r
+/* Library include files. */\r
+#include "LM3Sxxx.h"\r
+#include "pdc.h"\r
+\r
+/* The time to delay between writing each character to the LCD. */\r
+#define mainCHAR_WRITE_DELAY ( 2 / portTICK_RATE_MS )\r
+\r
+/* The time to delay between writing each string to the LCD. */\r
+#define mainSTRING_WRITE_DELAY ( 400 / portTICK_RATE_MS )\r
+\r
+/* The number of flash co-routines to create. */\r
+#define mainNUM_FLASH_CO_ROUTINES ( 5 )\r
+\r
+/* The length of the queue used to pass received characters to the Comms Rx\r
+task. */\r
+#define mainRX_QUEUE_LEN ( 5 )\r
+\r
+/* The priority of the co-routine used to initiate the transmission of the \r
+string on UART 0. */\r
+#define mainTX_CO_ROUTINE_PRIORITY ( 1 )\r
+\r
+/* Only one co-routine is created so its index is not important. */\r
+#define mainTX_CO_ROUTINE_INDEX ( 0 )\r
+\r
+/* The time between transmissions of the string on UART 0. This is pseudo\r
+random in order to generate a bit or randomness to when the interrupts occur.*/\r
+#define mainMIN_TX_DELAY ( 40 / portTICK_RATE_MS )\r
+#define mainMAX_TX_DELAY ( ( portTickType ) 0x7f )\r
+#define mainOFFSET_TIME ( ( portTickType ) 3 )\r
+\r
+/* The time the Comms Rx task should wait to receive a character. This should\r
+be slightly longer than the time between transmissions. If we do not receive\r
+a character after this time then there must be an error in the transmission or\r
+the timing of the transmission. */\r
+#define mainCOMMS_RX_DELAY ( mainMAX_TX_DELAY + 20 )\r
+\r
+/* The task priorites. */\r
+#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+#define mainCOMMS_RX_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+\r
+/* The LED's toggled by the various tasks. */\r
+#define mainCOMMS_FAIL_LED ( 7 )\r
+#define mainCOMMS_RX_LED ( 6 )\r
+#define mainCOMMS_TX_LED ( 5 )\r
+\r
+/* The baud rate used by the UART comms tasks/co-routine. */\r
+#define mainBAUD_RATE ( 57600 )\r
+\r
+/* FIFO setting for the UART. The FIFO is not used to create a better test. */\r
+#define mainFIFO_SET ( 0x10 )\r
+\r
+/* The string that is transmitted on the UART contains sequentially the \r
+characters from mainFIRST_TX_CHAR to mainLAST_TX_CHAR. */\r
+#define mainFIRST_TX_CHAR '0'\r
+#define mainLAST_TX_CHAR 'z'\r
+\r
+/* Just used to walk through the program memory in order that some random data\r
+can be generated. */\r
+#define mainTOTAL_PROGRAM_MEMORY ( ( unsigned portLONG * ) ( 8 * 1024 ) )\r
+#define mainFIRST_PROGRAM_BYTES ( ( unsigned portLONG * ) 4 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The task that rotates text on the LCD.\r
+ */\r
+static void vLCDTask( void * pvParameters );\r
+\r
+/*\r
+ * The task that receives the characters from UART 0.\r
+ */\r
+static void vCommsRxTask( void * pvParameters );\r
+\r
+/*\r
+ * The co-routine that periodically initiates the transmission of the string on\r
+ * the UART.\r
+ */\r
+static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex );\r
+\r
+/* \r
+ * Writes a string the the LCD.\r
+ */\r
+static void prvWriteString( const portCHAR *pcString );\r
+\r
+/*\r
+ * Initialisation routine for the UART.\r
+ */\r
+static void vSerialInit( void );\r
+\r
+/*\r
+ * Thread safe write to the PDC.\r
+ */\r
+static void prvPDCWrite( portCHAR cAddress, portCHAR cData );\r
+\r
+/*\r
+ * Function to simply set a known value into the general purpose registers\r
+ * then read them back to ensure they remain set correctly. An incorrect value\r
+ * being indicative of an error in the task switching mechanism.\r
+ */\r
+void prvSetAndCheckRegisters( void );\r
+\r
+/*\r
+ * Latch the LED that indicates that an error has occurred. \r
+ */\r
+void vSetErrorLED( void );\r
+\r
+/*\r
+ * Sets up the PLL and ports used by the demo.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Error flag set to pdFAIL if an error is encountered in the tasks/co-routines\r
+defined within this file. */\r
+unsigned portBASE_TYPE uxErrorStatus = pdPASS;\r
+\r
+/* The next character to transmit. */\r
+static portCHAR cNextChar;\r
+\r
+/* The queue used to transmit characters from the interrupt to the Comms Rx\r
+task. */\r
+static xQueueHandle xCommsQueue;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+int main( void )\r
+{\r
+ /* Create the queue used to communicate between the UART ISR and the Comms\r
+ Rx task. */\r
+ xCommsQueue = xQueueCreate( mainRX_QUEUE_LEN, sizeof( portCHAR ) );\r
+\r
+ /* Setup the ports used by the demo and the clock. */\r
+ prvSetupHardware();\r
+\r
+ /* Create the co-routines that flash the LED's. */\r
+ vStartFlashCoRoutines( mainNUM_FLASH_CO_ROUTINES );\r
+\r
+ /* Create the co-routine that initiates the transmission of characters\r
+ on the UART. */\r
+ xCoRoutineCreate( vSerialTxCoRoutine, mainTX_CO_ROUTINE_PRIORITY, mainTX_CO_ROUTINE_INDEX );\r
+\r
+ /* Create the LCD and Comms Rx tasks. */\r
+ xTaskCreate( vLCDTask, "LCD", configMINIMAL_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL );\r
+ xTaskCreate( vCommsRxTask, "CMS", configMINIMAL_STACK_SIZE, NULL, mainCOMMS_RX_TASK_PRIORITY, NULL );\r
+\r
+ /* Start the scheduler running the tasks and co-routines just created. */\r
+ vTaskStartScheduler();\r
+\r
+ /* Should not get here unless we did not have enough memory to start the\r
+ scheduler. */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+ /* Setup the PLL. */\r
+ SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ );\r
+\r
+ /* Initialise the hardware used to talk to the LCD, LED's and UART. */\r
+ PDCInit();\r
+ vParTestInitialise();\r
+ vSerialInit();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationIdleHook( void )\r
+{\r
+ /* The co-routines are executed in the idle task using the idle task \r
+ hook. */\r
+ for( ;; )\r
+ {\r
+ /* Schedule the co-routines. */\r
+ vCoRoutineSchedule();\r
+\r
+ /* Run the register check function between each co-routine. */\r
+ prvSetAndCheckRegisters();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvWriteString( const portCHAR *pcString )\r
+{\r
+ /* Write pcString to the LED, pausing between each character. */\r
+ prvPDCWrite(PDC_LCD_CSR, LCD_CLEAR); \r
+ while( *pcString )\r
+ {\r
+ vTaskDelay( mainCHAR_WRITE_DELAY );\r
+ prvPDCWrite( PDC_LCD_RAM, *pcString );\r
+ pcString++;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vLCDTask( void * pvParameters )\r
+{\r
+unsigned portBASE_TYPE uxIndex;\r
+const unsigned portCHAR ucCFGData[] = { \r
+ 0x30, /* Set data bus to 8-bits. */\r
+ 0x30,\r
+ 0x30,\r
+ 0x3C, /* Number of lines/font. */\r
+ 0x08, /* Display off. */\r
+ 0x01, /* Display clear. */\r
+ 0x06, /* Entry mode [cursor dir][shift]. */\r
+ 0x0C /* Display on [display on][curson on][blinking on]. */\r
+ }; \r
+\r
+/* The strings that are written to the LCD. */\r
+const portCHAR *pcStringsToDisplay[] = { \r
+ "Stellaris",\r
+ "Demo",\r
+ "One",\r
+ "www.FreeRTOS.org",\r
+ ""\r
+ };\r
+\r
+ /* Configure the LCD. */\r
+ uxIndex = 0;\r
+ while( uxIndex < sizeof( ucCFGData ) )\r
+ {\r
+ prvPDCWrite( PDC_LCD_CSR, ucCFGData[ uxIndex ] );\r
+ uxIndex++;\r
+ vTaskDelay( mainCHAR_WRITE_DELAY );\r
+ }\r
+\r
+ /* Turn the LCD Backlight on. */\r
+ prvPDCWrite( PDC_CSR, 0x01 );\r
+\r
+ /* Clear display. */\r
+ vTaskDelay( mainCHAR_WRITE_DELAY );\r
+ prvPDCWrite( PDC_LCD_CSR, LCD_CLEAR ); \r
+\r
+ uxIndex = 0;\r
+ for( ;; ) \r
+ {\r
+ /* Display the string on the LCD. */\r
+ prvWriteString( pcStringsToDisplay[ uxIndex ] );\r
+ \r
+ /* Move on to the next string - wrapping if necessary. */\r
+ uxIndex++;\r
+ if( *( pcStringsToDisplay[ uxIndex ] ) == 0x00 )\r
+ {\r
+ uxIndex = 0;\r
+ /* Longer pause on the last string to be sent. */\r
+ vTaskDelay( mainSTRING_WRITE_DELAY * 2 );\r
+ }\r
+\r
+ /* Wait until it is time to move onto the next string. */\r
+ vTaskDelay( mainSTRING_WRITE_DELAY );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vCommsRxTask( void * pvParameters )\r
+{\r
+static portCHAR cRxedChar, cExpectedChar;\r
+\r
+ /* Set the char we expect to receive to the start of the string. */\r
+ cExpectedChar = mainFIRST_TX_CHAR;\r
+\r
+ for( ;; )\r
+ {\r
+ /* Wait for a character to be received. */\r
+ xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY );\r
+\r
+ /* Was the character recived (if any) the expected character. */\r
+ if( cRxedChar != cExpectedChar )\r
+ {\r
+ /* Got an unexpected character. This can sometimes occur when\r
+ reseting the system using the debugger leaving characters already\r
+ in the UART regsters. */\r
+ uxErrorStatus = pdFAIL;\r
+\r
+ /* Resync by waiting for the end of the current string. */\r
+ while( cRxedChar != mainLAST_TX_CHAR )\r
+ {\r
+ while( !xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, portMAX_DELAY ) );\r
+ }\r
+\r
+ /* The next expected character is the start of the string again. */\r
+ cExpectedChar = mainFIRST_TX_CHAR;\r
+ }\r
+ else\r
+ {\r
+ if( cExpectedChar == mainLAST_TX_CHAR )\r
+ {\r
+ /* We have reached the end of the string - we now expect to \r
+ receive the first character in the string again. The LED is \r
+ toggled to indicate that the entire string was received without\r
+ error. */\r
+ vParTestToggleLED( mainCOMMS_RX_LED );\r
+ cExpectedChar = mainFIRST_TX_CHAR;\r
+ }\r
+ else\r
+ {\r
+ /* We got the expected character, we now expect to receive the\r
+ next character in the string. */\r
+ cExpectedChar++;\r
+ }\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )\r
+{\r
+portTickType xDelayPeriod;\r
+static unsigned portLONG *pulRandomBytes = mainFIRST_PROGRAM_BYTES;\r
+\r
+ /* Co-routine MUST start with a call to crSTART. */\r
+ crSTART( xHandle );\r
+\r
+ for(;;)\r
+ { \r
+ /* Was the previously transmitted string received correctly? */\r
+ if( uxErrorStatus != pdPASS )\r
+ {\r
+ /* An error was encountered so set the error LED. */\r
+ vSetErrorLED();\r
+ }\r
+\r
+ /* The next character to Tx is the first in the string. */\r
+ cNextChar = mainFIRST_TX_CHAR;\r
+\r
+ UARTIntDisable( UART0_BASE, UART_INT_TX );\r
+ {\r
+ /* Send the first character. */\r
+ if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) )\r
+ {\r
+ HWREG( UART0_BASE + UART_O_DR ) = cNextChar;\r
+ }\r
+\r
+ /* Move the variable to the char to Tx on so the ISR transmits\r
+ the next character in the string once this one has completed. */\r
+ cNextChar++;\r
+ }\r
+ UARTIntEnable(UART0_BASE, UART_INT_TX);\r
+\r
+ /* Toggle the LED to show a new string is being transmitted. */\r
+ vParTestToggleLED( mainCOMMS_TX_LED );\r
+\r
+ /* Delay before we start the string off again. A pseudo-random delay\r
+ is used as this will provide a better test. */\r
+ xDelayPeriod = xTaskGetTickCount() + ( *pulRandomBytes );\r
+\r
+ pulRandomBytes++;\r
+ if( pulRandomBytes > mainTOTAL_PROGRAM_MEMORY )\r
+ {\r
+ pulRandomBytes = mainFIRST_PROGRAM_BYTES;\r
+ }\r
+\r
+ /* Make sure we don't wait too long... */\r
+ xDelayPeriod &= mainMAX_TX_DELAY;\r
+\r
+ /* ...but we do want to wait. */\r
+ if( xDelayPeriod < mainMIN_TX_DELAY )\r
+ {\r
+ xDelayPeriod = mainMIN_TX_DELAY;\r
+ }\r
+\r
+ /* Block for the random(ish) time. */\r
+ crDELAY( xHandle, xDelayPeriod );\r
+ }\r
+\r
+ /* Co-routine MUST end with a call to crEND. */\r
+ crEND();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vSerialInit( void )\r
+{\r
+ /* Enable the UART. GPIOA has already been initialised. */\r
+ SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);\r
+\r
+ /* Set GPIO A0 and A1 as peripheral function. They are used to output the\r
+ UART signals. */\r
+ GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW );\r
+\r
+ /* Configure the UART for 8-N-1 operation. */\r
+ UARTConfigSet( UART0_BASE, mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE );\r
+\r
+ /* We dont want to use the fifo. This is for test purposes to generate\r
+ as many interrupts as possible. */\r
+ HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET;\r
+\r
+ /* Enable both Rx and Tx interrupts. */\r
+ HWREG( UART0_BASE + UART_O_IM ) |= ( UART_INT_TX | UART_INT_RX );\r
+ IntEnable( INT_UART0 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vUART_ISR(void)\r
+{\r
+unsigned portLONG ulStatus;\r
+portCHAR cRxedChar;\r
+portBASE_TYPE xTaskWokenByPost = pdFALSE;\r
+\r
+ /* What caused the interrupt. */\r
+ ulStatus = UARTIntStatus( UART0_BASE, pdTRUE );\r
+\r
+ /* Clear the interrupt. */\r
+ UARTIntClear( UART0_BASE, ulStatus );\r
+\r
+ /* Was an Rx interrpt pending? */\r
+ if( ulStatus & UART_INT_RX )\r
+ {\r
+ if( ( HWREG(UART0_BASE + UART_O_FR ) & UART_FR_RXFF ) )\r
+ {\r
+ /* Get the char from the buffer and post it onto the queue of\r
+ Rxed chars. Posting the character should wake the task that is \r
+ blocked on the queue waiting for characters. */\r
+ cRxedChar = ( portCHAR ) HWREG( UART0_BASE + UART_O_DR );\r
+ xTaskWokenByPost = xQueueSendFromISR( xCommsQueue, &cRxedChar, xTaskWokenByPost );\r
+ } \r
+ }\r
+\r
+ /* Was a Tx interrupt pending? */\r
+ if( ulStatus & UART_INT_TX )\r
+ {\r
+ /* Send the next character in the string. We are not using the FIFO. */\r
+ if( cNextChar <= mainLAST_TX_CHAR )\r
+ {\r
+ if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) )\r
+ {\r
+ HWREG( UART0_BASE + UART_O_DR ) = cNextChar;\r
+ }\r
+ cNextChar++;\r
+ }\r
+ }\r
+ \r
+ if( xTaskWokenByPost )\r
+ {\r
+ /* If a task was woken by the character being received then we force\r
+ a context switch to occur in case the task is of higher priority than\r
+ the currently executing task (i.e. the task that this interrupt \r
+ interrupted.) */\r
+ portEND_SWITCHING_ISR( xTaskWokenByPost );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvPDCWrite( portCHAR cAddress, portCHAR cData )\r
+{\r
+ vTaskSuspendAll();\r
+ {\r
+ PDCWrite( cAddress, cData );\r
+ }\r
+ xTaskResumeAll();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSetErrorLED( void )\r
+{\r
+ vParTestSetLED( mainCOMMS_FAIL_LED, pdTRUE );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+__asm void prvSetAndCheckRegisters( void )\r
+{\r
+ extern vSetErrorLED\r
+\r
+ /* Fill the general purpose registers with known values. */\r
+ mov r11, #10\r
+ add r0, r11, #1\r
+ add r1, r11, #2\r
+ add r2, r11, #3\r
+ add r3, r11, #4\r
+ add r4, r11, #5\r
+ add r5, r11, #6\r
+ add r6, r11, #7\r
+ add r7, r11, #8\r
+ add r8, r11, #9\r
+ add r9, r11, #10\r
+ add r10, r11, #11\r
+ add r12, r11, #12\r
+\r
+ /* Check the values are as expected. */\r
+ cmp r11, #10\r
+ bne set_error_led\r
+ cmp r0, #11\r
+ bne set_error_led\r
+ cmp r1, #12\r
+ bne set_error_led\r
+ cmp r2, #13\r
+ bne set_error_led\r
+ cmp r3, #14\r
+ bne set_error_led\r
+ cmp r4, #15\r
+ bne set_error_led\r
+ cmp r5, #16\r
+ bne set_error_led\r
+ cmp r6, #17\r
+ bne set_error_led\r
+ cmp r7, #18\r
+ bne set_error_led\r
+ cmp r8, #19\r
+ bne set_error_led\r
+ cmp r9, #20\r
+ bne set_error_led\r
+ cmp r10, #21\r
+ bne set_error_led\r
+ cmp r12, #22\r
+ bne set_error_led\r
+ bx lr\r
+\r
+set_error_led;\r
+ push {r14}\r
+ ldr r1, =vSetErrorLED\r
+ blx r1\r
+ pop {r14}\r
+ bx lr;\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. \r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 1\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 20000000 )\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 59 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1468 ) )\r
+#define configMAX_TASK_NAME_LEN ( 3 )\r
+#define configUSE_TRACE_FACILITY 0\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 0\r
+#define configUSE_CO_ROUTINES 1\r
+\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 )\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet 0\r
+#define INCLUDE_uxTaskPriorityGet 0\r
+#define INCLUDE_vTaskDelete 0\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 0\r
+#define INCLUDE_vTaskDelayUntil 0\r
+#define INCLUDE_vTaskDelay 1\r
+\r
+\r
+\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple parallel port IO routines.\r
+ *-----------------------------------------------------------*/\r
+\r
+/*\r
+*/\r
+\r
+\r
+#include "FreeRTOS.h"\r
+#include "Task.h"\r
+#include "partest.h"\r
+\r
+#include "pdc.h"\r
+\r
+#define partstPINS (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 Z | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7)\r
+\r
+#define partstALL_OUTPUTS_OFF ( ( unsigned portCHAR ) 0x00 )\r
+#define partstMAX_OUTPUT_LED ( ( unsigned portCHAR ) 8 )\r
+\r
+static volatile unsigned portCHAR ucOutputValue = partstALL_OUTPUTS_OFF;\r
+\r
+void vParTestInitialise( void )\r
+{\r
+ PDCInit();\r
+ PDCWrite( PDC_LED, ucOutputValue );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )\r
+{\r
+unsigned portCHAR ucBit = ( unsigned portCHAR ) 1;\r
+\r
+ vTaskSuspendAll();\r
+ {\r
+ if( uxLED < partstMAX_OUTPUT_LED )\r
+ {\r
+ ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED;\r
+\r
+ if( xValue == pdFALSE )\r
+ {\r
+ ucBit ^= ( unsigned portCHAR ) 0xff;\r
+ ucOutputValue &= ucBit;\r
+ }\r
+ else\r
+ {\r
+ ucOutputValue |= ucBit;\r
+ }\r
+\r
+ PDCWrite( PDC_LED, ucOutputValue );\r
+ } \r
+ }\r
+ xTaskResumeAll();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+unsigned portCHAR ucBit;\r
+\r
+ vTaskSuspendAll();\r
+ {\r
+ if( uxLED < partstMAX_OUTPUT_LED )\r
+ {\r
+ ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED;\r
+\r
+ if( ucOutputValue & ucBit )\r
+ {\r
+ ucOutputValue &= ~ucBit;\r
+ }\r
+ else\r
+ {\r
+ ucOutputValue |= ucBit;\r
+ }\r
+\r
+ PDCWrite( PDC_LED, ucOutputValue );\r
+ }\r
+ }\r
+ xTaskResumeAll();\r
+}\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* \r
+ * This demo application creates six co-routines and two tasks (three including \r
+ * the idle task). The co-routines execute as part of the idle task hook.\r
+ *\r
+ * Five of the created co-routines are the standard 'co-routine flash' \r
+ * co-routines contained within the Demo/Common/Minimal/crflash.c file and \r
+ * documented on the FreeRTOS.org WEB site. \r
+ *\r
+ * The 'LCD Task' rotates a string on the LCD, delaying between each character\r
+ * as necessitated by the slow interface, and delaying between each string just\r
+ * long enough to enable the text to be read.\r
+ *\r
+ * The sixth co-routine and final task control the transmission and reception\r
+ * of a string to UART 0. The co-routine periodically sends the first \r
+ * character of the string to the UART, with the UART's TxEnd interrupt being\r
+ * used to transmit the remaining characters. The UART's RxEnd interrupt \r
+ * receives the characters and places them on a queue to be processed by the \r
+ * 'COMs Rx' task. An error is latched should an unexpected character be \r
+ * received, or any character be received out of sequence. \r
+ *\r
+ * A loopback connector is required to ensure that each character transmitted \r
+ * on the UART is also received on the same UART. For test purposes the UART\r
+ * FIFO's are not utalised in order to maximise the interrupt overhead. Also\r
+ * a pseudo random interval is used between the start of each transmission in \r
+ * order that the resultant interrupts are more randomly distributed and \r
+ * therefore more likely to highlight any problems.\r
+ *\r
+ * The flash co-routines control LED's zero to four. LED five is toggled each\r
+ * time the string is transmitted on the UART. LED six is toggled each time\r
+ * the string is CORRECTLY received on the UART. LED seven is latched on should\r
+ * an error be detected in any task or co-routine.\r
+ *\r
+ * In addition the idle task makes repetative calls to \r
+ * prvSetAndCheckRegisters(). This simply loads the general purpose registers \r
+ * with a known value, then checks each register to ensure the held value is \r
+ * still correct. As a low priority task this checking routine is likely to \r
+ * get repeatedly swapped in and out. A register being found to contain an \r
+ * incorrect value is therefore indicative of an error in the task switching \r
+ * mechansim.\r
+ *\r
+ */\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+#include "croutine.h"\r
+\r
+/* Demo application include files. */\r
+#include "partest.h"\r
+#include "crflash.h"\r
+\r
+/* Library include files. */\r
+#include "DriverLib.h"\r
+\r
+/* The time to delay between writing each character to the LCD. */\r
+#define mainCHAR_WRITE_DELAY ( 2 / portTICK_RATE_MS )\r
+\r
+/* The time to delay between writing each string to the LCD. */\r
+#define mainSTRING_WRITE_DELAY ( 400 / portTICK_RATE_MS )\r
+\r
+/* The number of flash co-routines to create. */\r
+#define mainNUM_FLASH_CO_ROUTINES ( 5 )\r
+\r
+/* The length of the queue used to pass received characters to the Comms Rx\r
+task. */\r
+#define mainRX_QUEUE_LEN ( 5 )\r
+\r
+/* The priority of the co-routine used to initiate the transmission of the \r
+string on UART 0. */\r
+#define mainTX_CO_ROUTINE_PRIORITY ( 1 )\r
+\r
+/* Only one co-routine is created so its index is not important. */\r
+#define mainTX_CO_ROUTINE_INDEX ( 0 )\r
+\r
+/* The time between transmissions of the string on UART 0. This is pseudo\r
+random in order to generate a bit or randomness to when the interrupts occur.*/\r
+#define mainMIN_TX_DELAY ( 40 / portTICK_RATE_MS )\r
+#define mainMAX_TX_DELAY ( ( portTickType ) 0x7f )\r
+#define mainOFFSET_TIME ( ( portTickType ) 3 )\r
+\r
+/* The time the Comms Rx task should wait to receive a character. This should\r
+be slightly longer than the time between transmissions. If we do not receive\r
+a character after this time then there must be an error in the transmission or\r
+the timing of the transmission. */\r
+#define mainCOMMS_RX_DELAY ( mainMAX_TX_DELAY + 20 )\r
+\r
+/* The task priorites. */\r
+#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+#define mainCOMMS_RX_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+\r
+/* The LED's toggled by the various tasks. */\r
+#define mainCOMMS_FAIL_LED ( 7 )\r
+#define mainCOMMS_RX_LED ( 6 )\r
+#define mainCOMMS_TX_LED ( 5 )\r
+\r
+/* The baud rate used by the UART comms tasks/co-routine. */\r
+#define mainBAUD_RATE ( 57600 )\r
+\r
+/* FIFO setting for the UART. The FIFO is not used to create a better test. */\r
+#define mainFIFO_SET ( 0x10 )\r
+\r
+/* The string that is transmitted on the UART contains sequentially the \r
+characters from mainFIRST_TX_CHAR to mainLAST_TX_CHAR. */\r
+#define mainFIRST_TX_CHAR '0'\r
+#define mainLAST_TX_CHAR 'z'\r
+\r
+/* Just used to walk through the program memory in order that some random data\r
+can be generated. */\r
+#define mainTOTAL_PROGRAM_MEMORY ( ( unsigned portLONG * ) ( 8 * 1024 ) )\r
+#define mainFIRST_PROGRAM_BYTES ( ( unsigned portLONG * ) 4 )\r
+\r
+/* The error routine that is called if the driver library encounters an error. */\r
+#ifdef DEBUG\r
+void\r
+__error__(char *pcFilename, unsigned long ulLine)\r
+{\r
+}\r
+#endif\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The task that rotates text on the LCD.\r
+ */\r
+static void vLCDTask( void * pvParameters );\r
+\r
+/*\r
+ * The task that receives the characters from UART 0.\r
+ */\r
+static void vCommsRxTask( void * pvParameters );\r
+\r
+/*\r
+ * The co-routine that periodically initiates the transmission of the string on\r
+ * the UART.\r
+ */\r
+static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex );\r
+\r
+/* \r
+ * Writes a string the the LCD.\r
+ */\r
+static void prvWriteString( const portCHAR *pcString );\r
+\r
+/*\r
+ * Initialisation routine for the UART.\r
+ */\r
+static void vSerialInit( void );\r
+\r
+/*\r
+ * Thread safe write to the PDC.\r
+ */\r
+static void prvPDCWrite( portCHAR cAddress, portCHAR cData );\r
+\r
+/*\r
+ * Function to simply set a known value into the general purpose registers\r
+ * then read them back to ensure they remain set correctly. An incorrect value\r
+ * being indicative of an error in the task switching mechanism.\r
+ */\r
+void prvSetAndCheckRegisters( void );\r
+\r
+/*\r
+ * Latch the LED that indicates that an error has occurred. \r
+ */\r
+void vSetErrorLED( void );\r
+\r
+/*\r
+ * Sets up the PLL and ports used by the demo.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Error flag set to pdFAIL if an error is encountered in the tasks/co-routines\r
+defined within this file. */\r
+unsigned portBASE_TYPE uxErrorStatus = pdPASS;\r
+\r
+/* The next character to transmit. */\r
+static portCHAR cNextChar;\r
+\r
+/* The queue used to transmit characters from the interrupt to the Comms Rx\r
+task. */\r
+static xQueueHandle xCommsQueue;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+int main( void )\r
+{\r
+ /* Create the queue used to communicate between the UART ISR and the Comms\r
+ Rx task. */\r
+ xCommsQueue = xQueueCreate( mainRX_QUEUE_LEN, sizeof( portCHAR ) );\r
+\r
+ /* Setup the ports used by the demo and the clock. */\r
+ prvSetupHardware();\r
+\r
+ /* Create the co-routines that flash the LED's. */\r
+ vStartFlashCoRoutines( mainNUM_FLASH_CO_ROUTINES );\r
+\r
+ /* Create the co-routine that initiates the transmission of characters\r
+ on the UART. */\r
+ xCoRoutineCreate( vSerialTxCoRoutine, mainTX_CO_ROUTINE_PRIORITY, mainTX_CO_ROUTINE_INDEX );\r
+\r
+ /* Create the LCD and Comms Rx tasks. */\r
+ xTaskCreate( vLCDTask, "LCD", configMINIMAL_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL );\r
+ xTaskCreate( vCommsRxTask, "CMS", configMINIMAL_STACK_SIZE, NULL, mainCOMMS_RX_TASK_PRIORITY, NULL );\r
+\r
+ /* Start the scheduler running the tasks and co-routines just created. */\r
+ vTaskStartScheduler();\r
+\r
+ /* Should not get here unless we did not have enough memory to start the\r
+ scheduler. */\r
+ for( ;; );\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+ /* Setup the PLL. */\r
+ SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ );\r
+\r
+ /* Initialise the hardware used to talk to the LCD, LED's and UART. */\r
+ PDCInit();\r
+ vParTestInitialise();\r
+ vSerialInit();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationIdleHook( void )\r
+{\r
+ /* The co-routines are executed in the idle task using the idle task \r
+ hook. */\r
+ for( ;; )\r
+ {\r
+ /* Schedule the co-routines. */\r
+ vCoRoutineSchedule();\r
+\r
+ /* Run the register check function between each co-routine. */\r
+ prvSetAndCheckRegisters();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvWriteString( const portCHAR *pcString )\r
+{\r
+ /* Write pcString to the LED, pausing between each character. */\r
+ prvPDCWrite(PDC_LCD_CSR, LCD_CLEAR); \r
+ while( *pcString )\r
+ {\r
+ vTaskDelay( mainCHAR_WRITE_DELAY );\r
+ prvPDCWrite( PDC_LCD_RAM, *pcString );\r
+ pcString++;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vLCDTask( void * pvParameters )\r
+{\r
+unsigned portBASE_TYPE uxIndex;\r
+const unsigned portCHAR ucCFGData[] = { \r
+ 0x30, /* Set data bus to 8-bits. */\r
+ 0x30,\r
+ 0x30,\r
+ 0x3C, /* Number of lines/font. */\r
+ 0x08, /* Display off. */\r
+ 0x01, /* Display clear. */\r
+ 0x06, /* Entry mode [cursor dir][shift]. */\r
+ 0x0C /* Display on [display on][curson on][blinking on]. */\r
+ }; \r
+\r
+/* The strings that are written to the LCD. */\r
+const portCHAR *pcStringsToDisplay[] = { \r
+ "Stellaris",\r
+ "Demo",\r
+ "One",\r
+ "www.FreeRTOS.org",\r
+ ""\r
+ };\r
+\r
+ /* Configure the LCD. */\r
+ uxIndex = 0;\r
+ while( uxIndex < sizeof( ucCFGData ) )\r
+ {\r
+ prvPDCWrite( PDC_LCD_CSR, ucCFGData[ uxIndex ] );\r
+ uxIndex++;\r
+ vTaskDelay( mainCHAR_WRITE_DELAY );\r
+ }\r
+\r
+ /* Turn the LCD Backlight on. */\r
+ prvPDCWrite( PDC_CSR, 0x01 );\r
+\r
+ /* Clear display. */\r
+ vTaskDelay( mainCHAR_WRITE_DELAY );\r
+ prvPDCWrite( PDC_LCD_CSR, LCD_CLEAR ); \r
+\r
+ uxIndex = 0;\r
+ for( ;; ) \r
+ {\r
+ /* Display the string on the LCD. */\r
+ prvWriteString( pcStringsToDisplay[ uxIndex ] );\r
+ \r
+ /* Move on to the next string - wrapping if necessary. */\r
+ uxIndex++;\r
+ if( *( pcStringsToDisplay[ uxIndex ] ) == 0x00 )\r
+ {\r
+ uxIndex = 0;\r
+ /* Longer pause on the last string to be sent. */\r
+ vTaskDelay( mainSTRING_WRITE_DELAY * 2 );\r
+ }\r
+\r
+ /* Wait until it is time to move onto the next string. */\r
+ vTaskDelay( mainSTRING_WRITE_DELAY );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vCommsRxTask( void * pvParameters )\r
+{\r
+static portCHAR cRxedChar, cExpectedChar;\r
+\r
+ /* Set the char we expect to receive to the start of the string. */\r
+ cExpectedChar = mainFIRST_TX_CHAR;\r
+\r
+ for( ;; )\r
+ {\r
+ /* Wait for a character to be received. */\r
+ xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY );\r
+\r
+ /* Was the character recived (if any) the expected character. */\r
+ if( cRxedChar != cExpectedChar )\r
+ {\r
+ /* Got an unexpected character. This can sometimes occur when\r
+ reseting the system using the debugger leaving characters already\r
+ in the UART regsters. */\r
+ uxErrorStatus = pdFAIL;\r
+\r
+ /* Resync by waiting for the end of the current string. */\r
+ while( cRxedChar != mainLAST_TX_CHAR )\r
+ {\r
+ while( !xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, portMAX_DELAY ) );\r
+ }\r
+\r
+ /* The next expected character is the start of the string again. */\r
+ cExpectedChar = mainFIRST_TX_CHAR;\r
+ }\r
+ else\r
+ {\r
+ if( cExpectedChar == mainLAST_TX_CHAR )\r
+ {\r
+ /* We have reached the end of the string - we now expect to \r
+ receive the first character in the string again. The LED is \r
+ toggled to indicate that the entire string was received without\r
+ error. */\r
+ vParTestToggleLED( mainCOMMS_RX_LED );\r
+ cExpectedChar = mainFIRST_TX_CHAR;\r
+ }\r
+ else\r
+ {\r
+ /* We got the expected character, we now expect to receive the\r
+ next character in the string. */\r
+ cExpectedChar++;\r
+ }\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )\r
+{\r
+portTickType xDelayPeriod;\r
+static unsigned portLONG *pulRandomBytes = mainFIRST_PROGRAM_BYTES;\r
+\r
+ /* Co-routine MUST start with a call to crSTART. */\r
+ crSTART( xHandle );\r
+\r
+ for(;;)\r
+ { \r
+ /* Was the previously transmitted string received correctly? */\r
+ if( uxErrorStatus != pdPASS )\r
+ {\r
+ /* An error was encountered so set the error LED. */\r
+ vSetErrorLED();\r
+ }\r
+\r
+ /* The next character to Tx is the first in the string. */\r
+ cNextChar = mainFIRST_TX_CHAR;\r
+\r
+ UARTIntDisable( UART0_BASE, UART_INT_TX );\r
+ {\r
+ /* Send the first character. */\r
+ if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) )\r
+ {\r
+ HWREG( UART0_BASE + UART_O_DR ) = cNextChar;\r
+ }\r
+\r
+ /* Move the variable to the char to Tx on so the ISR transmits\r
+ the next character in the string once this one has completed. */\r
+ cNextChar++;\r
+ }\r
+ UARTIntEnable(UART0_BASE, UART_INT_TX);\r
+\r
+ /* Toggle the LED to show a new string is being transmitted. */\r
+ vParTestToggleLED( mainCOMMS_TX_LED );\r
+\r
+ /* Delay before we start the string off again. A pseudo-random delay\r
+ is used as this will provide a better test. */\r
+ xDelayPeriod = xTaskGetTickCount() + ( *pulRandomBytes );\r
+\r
+ pulRandomBytes++;\r
+ if( pulRandomBytes > mainTOTAL_PROGRAM_MEMORY )\r
+ {\r
+ pulRandomBytes = mainFIRST_PROGRAM_BYTES;\r
+ }\r
+\r
+ /* Make sure we don't wait too long... */\r
+ xDelayPeriod &= mainMAX_TX_DELAY;\r
+\r
+ /* ...but we do want to wait. */\r
+ if( xDelayPeriod < mainMIN_TX_DELAY )\r
+ {\r
+ xDelayPeriod = mainMIN_TX_DELAY;\r
+ }\r
+\r
+ /* Block for the random(ish) time. */\r
+ crDELAY( xHandle, xDelayPeriod );\r
+ }\r
+\r
+ /* Co-routine MUST end with a call to crEND. */\r
+ crEND();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vSerialInit( void )\r
+{\r
+ /* Enable the UART. GPIOA has already been initialised. */\r
+ SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);\r
+\r
+ /* Set GPIO A0 and A1 as peripheral function. They are used to output the\r
+ UART signals. */\r
+ GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW );\r
+\r
+ /* Configure the UART for 8-N-1 operation. */\r
+ UARTConfigSet( UART0_BASE, mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE );\r
+\r
+ /* We dont want to use the fifo. This is for test purposes to generate\r
+ as many interrupts as possible. */\r
+ HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET;\r
+\r
+ /* Enable both Rx and Tx interrupts. */\r
+ HWREG( UART0_BASE + UART_O_IM ) |= ( UART_INT_TX | UART_INT_RX );\r
+ IntEnable( INT_UART0 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vUART_ISR(void)\r
+{\r
+unsigned portLONG ulStatus;\r
+portCHAR cRxedChar;\r
+portBASE_TYPE xTaskWokenByPost = pdFALSE;\r
+\r
+ /* What caused the interrupt. */\r
+ ulStatus = UARTIntStatus( UART0_BASE, pdTRUE );\r
+\r
+ /* Clear the interrupt. */\r
+ UARTIntClear( UART0_BASE, ulStatus );\r
+\r
+ /* Was an Rx interrpt pending? */\r
+ if( ulStatus & UART_INT_RX )\r
+ {\r
+ if( ( HWREG(UART0_BASE + UART_O_FR ) & UART_FR_RXFF ) )\r
+ {\r
+ /* Get the char from the buffer and post it onto the queue of\r
+ Rxed chars. Posting the character should wake the task that is \r
+ blocked on the queue waiting for characters. */\r
+ cRxedChar = ( portCHAR ) HWREG( UART0_BASE + UART_O_DR );\r
+ xTaskWokenByPost = xQueueSendFromISR( xCommsQueue, &cRxedChar, xTaskWokenByPost );\r
+ } \r
+ }\r
+\r
+ /* Was a Tx interrupt pending? */\r
+ if( ulStatus & UART_INT_TX )\r
+ {\r
+ /* Send the next character in the string. We are not using the FIFO. */\r
+ if( cNextChar <= mainLAST_TX_CHAR )\r
+ {\r
+ if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) )\r
+ {\r
+ HWREG( UART0_BASE + UART_O_DR ) = cNextChar;\r
+ }\r
+ cNextChar++;\r
+ }\r
+ }\r
+ \r
+ if( xTaskWokenByPost )\r
+ {\r
+ /* If a task was woken by the character being received then we force\r
+ a context switch to occur in case the task is of higher priority than\r
+ the currently executing task (i.e. the task that this interrupt \r
+ interrupted.) */\r
+ portEND_SWITCHING_ISR( xTaskWokenByPost );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvPDCWrite( portCHAR cAddress, portCHAR cData )\r
+{\r
+ vTaskSuspendAll();\r
+ {\r
+ PDCWrite( cAddress, cData );\r
+ }\r
+ xTaskResumeAll();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSetErrorLED( void )\r
+{\r
+ vParTestSetLED( mainCOMMS_FAIL_LED, pdTRUE );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void prvSetAndCheckRegisters( void )\r
+{\r
+ /* Fill the general purpose registers with known values. */\r
+ __asm volatile\r
+ ( \r
+ " mov r11, #10 \n"\r
+ " add r0, r11, #1 \n"\r
+ " add r1, r11, #2 \n"\r
+ " add r2, r11, #3 \n"\r
+ " add r3, r11, #4 \n"\r
+ " add r4, r11, #5 \n"\r
+ " add r5, r11, #6 \n"\r
+ " add r6, r11, #7 \n"\r
+ " add r7, r11, #8 \n"\r
+ " add r8, r11, #9 \n"\r
+ " add r9, r11, #10 \n"\r
+ " add r10, r11, #11 \n"\r
+ " add r12, r11, #12" \r
+ );\r
+\r
+ /* Check the values are as expected. */\r
+ __asm volatile\r
+ ( \r
+ " cmp r11, #10 \n"\r
+ " bne set_error_led \n"\r
+ " cmp r0, #11 \n"\r
+ " bne set_error_led \n"\r
+ " cmp r1, #12 \n"\r
+ " bne set_error_led \n"\r
+ " cmp r2, #13 \n"\r
+ " bne set_error_led \n"\r
+ " cmp r3, #14 \n"\r
+ " bne set_error_led \n"\r
+ " cmp r4, #15 \n"\r
+ " bne set_error_led \n"\r
+ " cmp r5, #16 \n"\r
+ " bne set_error_led \n"\r
+ " cmp r6, #17 \n"\r
+ " bne set_error_led \n"\r
+ " cmp r7, #18 \n"\r
+ " bne set_error_led \n"\r
+ " cmp r8, #19 \n"\r
+ " bne set_error_led \n"\r
+ " cmp r9, #20 \n"\r
+ " bne set_error_led \n"\r
+ " cmp r10, #21 \n"\r
+ " bne set_error_led \n"\r
+ " cmp r12, #22 \n"\r
+ " bne set_error_led \n"\r
+ " bx lr" \r
+ );\r
+\r
+ __asm volatile\r
+ (\r
+ "set_error_led: \n"\r
+ " push {r14} \n"\r
+ " ldr r1, vSetErrorLEDConst\n"\r
+ " blx r1 \n"\r
+ " pop {r14} \n"\r
+ " bx lr \n"\r
+ " \n"\r
+ " .align 2 \n"\r
+ "vSetErrorLEDConst: .word vSetErrorLED"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*****************************************************************************\r
+ * Copyright (c) 2006 Rowley Associates Limited. *\r
+ * *\r
+ * This file may be distributed under the terms of the License Agreement *\r
+ * provided with this software. *\r
+ * *\r
+ * THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE *\r
+ * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *\r
+ *****************************************************************************/\r
+ .section .vectors, "ax"\r
+ .code 16\r
+ .align 0\r
+ .global _vectors\r
+\r
+ .extern xPortPendSVHandler\r
+ .extern xPortSysTickHandler\r
+ .extern vUART_ISR\r
+\r
+.macro DEFAULT_ISR_HANDLER name=\r
+ .thumb_func\r
+ .weak \name\r
+\name:\r
+1: b 1b /* endless loop */\r
+.endm\r
+\r
+_vectors:\r
+ .word __stack_end__\r
+ .word reset_handler\r
+ .word NmiISR\r
+ .word FaultISR\r
+ .word 0 // Populate if using MemManage (MPU)\r
+ .word 0 // Populate if using Bus fault\r
+ .word 0 // Populate if using Usage fault\r
+ .word 0 // Reserved\r
+ .word 0 // Reserved\r
+ .word 0 // Reserved\r
+ .word 0 // Reserved\r
+ .word 0\r
+ .word 0 // Populate if using a debug monitor\r
+ .word 0 // Reserved\r
+ .word xPortPendSVHandler // Populate if using pendable service request\r
+ .word xPortSysTickHandler\r
+ // External interrupts start her \r
+ .word GPIO_Port_A_ISR\r
+ .word GPIO_Port_B_ISR\r
+ .word GPIO_Port_C_ISR\r
+ .word GPIO_Port_D_ISR\r
+ .word GPIO_Port_E_ISR\r
+ .word vUART_ISR\r
+ .word UART1_ISR\r
+ .word SSI_ISR\r
+ .word I2C_ISR\r
+ .word PWM_Fault_ISR\r
+ .word PWM_Generator_0_ISR\r
+ .word PWM_Generator_1_ISR\r
+ .word PWM_Generator_2_ISR\r
+ .word QEI_ISR\r
+ .word ADC_Sequence_0_ISR\r
+ .word ADC_Sequence_1_ISR\r
+ .word ADC_Sequence_2_ISR\r
+ .word ADC_Sequence_3_ISR\r
+ .word Watchdog_timer_ISR\r
+ .word Timer0a_ISR\r
+ .word Timer0b_ISR\r
+ .word Timer1a_ISR\r
+ .word Timer1b_ISR\r
+ .word Timer2a_ISR\r
+ .word Timer2b_ISR\r
+ .word Analog_Comparator_0_ISR\r
+ .word Analog_Comparator_1_ISR\r
+ .word Analog_Comparator_2_ISR\r
+ .word System_Control_ISR\r
+ .word FLASH_Control_ISR\r
+\r
+ .section .init, "ax"\r
+ .thumb_func\r
+\r
+DEFAULT_ISR_HANDLER NmiISR\r
+DEFAULT_ISR_HANDLER FaultISR\r
+DEFAULT_ISR_HANDLER SVCallISR\r
+DEFAULT_ISR_HANDLER SysTickISR\r
+DEFAULT_ISR_HANDLER GPIO_Port_A_ISR\r
+DEFAULT_ISR_HANDLER GPIO_Port_B_ISR\r
+DEFAULT_ISR_HANDLER GPIO_Port_C_ISR\r
+DEFAULT_ISR_HANDLER GPIO_Port_D_ISR\r
+DEFAULT_ISR_HANDLER GPIO_Port_E_ISR\r
+DEFAULT_ISR_HANDLER UART0_ISR\r
+DEFAULT_ISR_HANDLER UART1_ISR\r
+DEFAULT_ISR_HANDLER SSI_ISR\r
+DEFAULT_ISR_HANDLER I2C_ISR\r
+DEFAULT_ISR_HANDLER PWM_Fault_ISR\r
+DEFAULT_ISR_HANDLER PWM_Generator_0_ISR\r
+DEFAULT_ISR_HANDLER PWM_Generator_1_ISR\r
+DEFAULT_ISR_HANDLER PWM_Generator_2_ISR\r
+DEFAULT_ISR_HANDLER QEI_ISR\r
+DEFAULT_ISR_HANDLER ADC_Sequence_0_ISR\r
+DEFAULT_ISR_HANDLER ADC_Sequence_1_ISR\r
+DEFAULT_ISR_HANDLER ADC_Sequence_2_ISR\r
+DEFAULT_ISR_HANDLER ADC_Sequence_3_ISR\r
+DEFAULT_ISR_HANDLER Watchdog_timer_ISR\r
+DEFAULT_ISR_HANDLER Timer0a_ISR\r
+DEFAULT_ISR_HANDLER Timer0b_ISR\r
+DEFAULT_ISR_HANDLER Timer1a_ISR\r
+DEFAULT_ISR_HANDLER Timer1b_ISR\r
+DEFAULT_ISR_HANDLER Timer2a_ISR\r
+DEFAULT_ISR_HANDLER Timer2b_ISR\r
+DEFAULT_ISR_HANDLER Analog_Comparator_0_ISR\r
+DEFAULT_ISR_HANDLER Analog_Comparator_1_ISR\r
+DEFAULT_ISR_HANDLER Analog_Comparator_2_ISR\r
+DEFAULT_ISR_HANDLER System_Control_ISR\r
+DEFAULT_ISR_HANDLER FLASH_Control_ISR\r
+\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. \r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 1\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 20000000 )\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 59 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1240 ) )\r
+#define configMAX_TASK_NAME_LEN ( 3 )\r
+#define configUSE_TRACE_FACILITY 0\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 0\r
+#define configUSE_CO_ROUTINES 1\r
+\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 )\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 3 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet 0\r
+#define INCLUDE_uxTaskPriorityGet 0\r
+#define INCLUDE_vTaskDelete 0\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 0\r
+#define INCLUDE_vTaskDelayUntil 0\r
+#define INCLUDE_vTaskDelay 1\r
+\r
+\r
+\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple parallel port IO routines.\r
+ *-----------------------------------------------------------*/\r
+\r
+/*\r
+*/\r
+\r
+\r
+#include "FreeRTOS.h"\r
+#include "Task.h"\r
+#include "partest.h"\r
+\r
+#include "pdc.h"\r
+\r
+#define partstPINS (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 Z | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7)\r
+\r
+#define partstALL_OUTPUTS_OFF ( ( unsigned portCHAR ) 0x00 )\r
+#define partstMAX_OUTPUT_LED ( ( unsigned portCHAR ) 8 )\r
+\r
+static volatile unsigned portCHAR ucOutputValue = partstALL_OUTPUTS_OFF;\r
+\r
+void vParTestInitialise( void )\r
+{\r
+ PDCInit();\r
+ PDCWrite( PDC_LED, ucOutputValue );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )\r
+{\r
+unsigned portCHAR ucBit = ( unsigned portCHAR ) 1;\r
+\r
+ vTaskSuspendAll();\r
+ {\r
+ if( uxLED < partstMAX_OUTPUT_LED )\r
+ {\r
+ ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED;\r
+\r
+ if( xValue == pdFALSE )\r
+ {\r
+ ucBit ^= ( unsigned portCHAR ) 0xff;\r
+ ucOutputValue &= ucBit;\r
+ }\r
+ else\r
+ {\r
+ ucOutputValue |= ucBit;\r
+ }\r
+\r
+ PDCWrite( PDC_LED, ucOutputValue );\r
+ } \r
+ }\r
+ xTaskResumeAll();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+unsigned portCHAR ucBit;\r
+\r
+ vTaskSuspendAll();\r
+ {\r
+ if( uxLED < partstMAX_OUTPUT_LED )\r
+ {\r
+ ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED;\r
+\r
+ if( ucOutputValue & ucBit )\r
+ {\r
+ ucOutputValue &= ~ucBit;\r
+ }\r
+ else\r
+ {\r
+ ucOutputValue |= ucBit;\r
+ }\r
+\r
+ PDCWrite( PDC_LED, ucOutputValue );\r
+ }\r
+ }\r
+ xTaskResumeAll();\r
+}\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* \r
+ * This demo application creates seven co-routines and one task (two including \r
+ * the idle task). The co-routines execute as part of the idle task hook.\r
+ *\r
+ * Five of the created co-routines are the standard 'co-routine flash' \r
+ * co-routines contained within the Demo/Common/Minimal/crflash.c file and \r
+ * documented on the FreeRTOS.org WEB site. \r
+ *\r
+ * The 'LCD Task' rotates a string on the LCD, delaying between each character\r
+ * as necessitated by the slow interface, and delaying between each string just\r
+ * long enough to enable the text to be read.\r
+ *\r
+ * The sixth co-routine controls the transmission of a string to UART 0. The \r
+ * co-routine periodically sends the first character of the string to the UART, \r
+ * with the UART's TxEnd interrupt being used to transmit the remaining \r
+ * characters. The UART's RxEnd interrupt receives the characters and places \r
+ * them on a queue to be processed by the seventh and final co-routine. An \r
+ * error is latched should an unexpected character be received, or any \r
+ * character be received out of sequence. \r
+ *\r
+ * A loopback connector is required to ensure that each character transmitted \r
+ * on the UART is also received on the same UART. For test purposes the UART\r
+ * FIFO's are not utalised in order to maximise the interrupt overhead. Also\r
+ * a pseudo random interval is used between the start of each transmission in \r
+ * order that the resultant interrupts are more randomly distributed and \r
+ * therefore more likely to highlight any problems.\r
+ *\r
+ * The flash co-routines control LED's zero to four. LED five is toggled each\r
+ * time the string is transmitted on the UART. LED six is toggled each time\r
+ * the string is CORRECTLY received on the UART. LED seven is latched on should\r
+ * an error be detected in any task or co-routine.\r
+ *\r
+ * In addition the idle task makes repetative calls to \r
+ * prvSetAndCheckRegisters(). This simply loads the general purpose registers \r
+ * with a known value, then checks each register to ensure the held value is \r
+ * still correct. As a low priority task this checking routine is likely to \r
+ * get repeatedly swapped in and out. A register being found to contain an \r
+ * incorrect value is therefore indicative of an error in the task switching \r
+ * mechansim.\r
+ *\r
+ */\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+#include "croutine.h"\r
+\r
+/* Demo application include files. */\r
+#include "partest.h"\r
+#include "crflash.h"\r
+\r
+/* Library include files. */\r
+#include "DriverLib.h"\r
+\r
+/* The time to delay between writing each character to the LCD. */\r
+#define mainCHAR_WRITE_DELAY ( 2 / portTICK_RATE_MS )\r
+\r
+/* The time to delay between writing each string to the LCD. */\r
+#define mainSTRING_WRITE_DELAY ( 400 / portTICK_RATE_MS )\r
+\r
+/* The number of flash co-routines to create. */\r
+#define mainNUM_FLASH_CO_ROUTINES ( 5 )\r
+\r
+/* The length of the queue used to pass received characters to the Comms Rx\r
+task. */\r
+#define mainRX_QUEUE_LEN ( 5 )\r
+\r
+/* The priority of the co-routine used to initiate the transmission of the \r
+string on UART 0. */\r
+#define mainTX_CO_ROUTINE_PRIORITY ( 1 )\r
+\r
+/* The priority of the co-routine used to receive characters from the UART. */\r
+#define mainRX_CO_ROUTINE_PRIORITY ( 2 )\r
+\r
+/* Only one co-routine is created so its index is not important. */\r
+#define mainTX_CO_ROUTINE_INDEX ( 0 )\r
+#define mainRX_CO_ROUTINE_INDEX ( 0 )\r
+\r
+/* The time between transmissions of the string on UART 0. This is pseudo\r
+random in order to generate a bit or randomness to when the interrupts occur.*/\r
+#define mainMIN_TX_DELAY ( 40 / portTICK_RATE_MS )\r
+#define mainMAX_TX_DELAY ( ( portTickType ) 0x7f )\r
+#define mainOFFSET_TIME ( ( portTickType ) 3 )\r
+\r
+/* The time the Comms Rx task should wait to receive a character. This should\r
+be slightly longer than the time between transmissions. If we do not receive\r
+a character after this time then there must be an error in the transmission or\r
+the timing of the transmission. */\r
+#define mainCOMMS_RX_DELAY ( mainMAX_TX_DELAY + 20 )\r
+\r
+/* The task priorites. */\r
+#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+#define mainCOMMS_RX_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+\r
+/* The LED's toggled by the various tasks. */\r
+#define mainCOMMS_FAIL_LED ( 7 )\r
+#define mainCOMMS_RX_LED ( 6 )\r
+#define mainCOMMS_TX_LED ( 5 )\r
+\r
+/* The baud rate used by the UART comms tasks/co-routine. */\r
+#define mainBAUD_RATE ( 57600 )\r
+\r
+/* FIFO setting for the UART. The FIFO is not used to create a better test. */\r
+#define mainFIFO_SET ( 0x10 )\r
+\r
+/* The string that is transmitted on the UART contains sequentially the \r
+characters from mainFIRST_TX_CHAR to mainLAST_TX_CHAR. */\r
+#define mainFIRST_TX_CHAR '0'\r
+#define mainLAST_TX_CHAR 'z'\r
+\r
+/* Just used to walk through the program memory in order that some random data\r
+can be generated. */\r
+#define mainTOTAL_PROGRAM_MEMORY ( ( unsigned portLONG * ) ( 8 * 1024 ) )\r
+#define mainFIRST_PROGRAM_BYTES ( ( unsigned portLONG * ) 4 )\r
+\r
+/* The error routine that is called if the driver library encounters an error. */\r
+#ifdef DEBUG\r
+void\r
+__error__(char *pcFilename, unsigned long ulLine)\r
+{\r
+}\r
+#endif\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The task that rotates text on the LCD.\r
+ */\r
+static void vLCDTask( void * pvParameters );\r
+\r
+/*\r
+ * The task that receives the characters from UART 0.\r
+ */\r
+static void vCommsRxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex );\r
+\r
+/*\r
+ * The co-routine that periodically initiates the transmission of the string on\r
+ * the UART.\r
+ */\r
+static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex );\r
+\r
+/* \r
+ * Writes a string the the LCD.\r
+ */\r
+static void prvWriteString( const portCHAR *pcString );\r
+\r
+/*\r
+ * Initialisation routine for the UART.\r
+ */\r
+static void vSerialInit( void );\r
+\r
+/*\r
+ * Thread safe write to the PDC.\r
+ */\r
+static void prvPDCWrite( portCHAR cAddress, portCHAR cData );\r
+\r
+/*\r
+ * Function to simply set a known value into the general purpose registers\r
+ * then read them back to ensure they remain set correctly. An incorrect value\r
+ * being indicative of an error in the task switching mechanism.\r
+ */\r
+void prvSetAndCheckRegisters( void );\r
+\r
+/*\r
+ * Latch the LED that indicates that an error has occurred. \r
+ */\r
+void vSetErrorLED( void );\r
+\r
+/*\r
+ * Sets up the PLL and ports used by the demo.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Error flag set to pdFAIL if an error is encountered in the tasks/co-routines\r
+defined within this file. */\r
+unsigned portBASE_TYPE uxErrorStatus = pdPASS;\r
+\r
+/* The next character to transmit. */\r
+static portCHAR cNextChar;\r
+\r
+/* The queue used to transmit characters from the interrupt to the Comms Rx\r
+task. */\r
+static xQueueHandle xCommsQueue;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+int main( void )\r
+{\r
+ /* Create the queue used to communicate between the UART ISR and the Comms\r
+ Rx task. */\r
+ xCommsQueue = xQueueCreate( mainRX_QUEUE_LEN, sizeof( portCHAR ) );\r
+\r
+ /* Setup the ports used by the demo and the clock. */\r
+ prvSetupHardware();\r
+\r
+ /* Create the co-routines that flash the LED's. */\r
+ vStartFlashCoRoutines( mainNUM_FLASH_CO_ROUTINES );\r
+\r
+ /* Create the co-routine that initiates the transmission of characters\r
+ on the UART. */\r
+ xCoRoutineCreate( vSerialTxCoRoutine, mainTX_CO_ROUTINE_PRIORITY, mainTX_CO_ROUTINE_INDEX );\r
+\r
+ /* Create the co-routine that receives characters from the UART. */\r
+ xCoRoutineCreate( vCommsRxCoRoutine, mainRX_CO_ROUTINE_PRIORITY, mainRX_CO_ROUTINE_INDEX );\r
+\r
+ /* Create the LCD task. */\r
+ xTaskCreate( vLCDTask, "LCD", configMINIMAL_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL );\r
+\r
+ /* Start the scheduler running the tasks and co-routines just created. */\r
+ vTaskStartScheduler();\r
+\r
+ /* Should not get here unless we did not have enough memory to start the\r
+ scheduler. */\r
+ for( ;; );\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+ /* Setup the PLL. */\r
+ SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ );\r
+\r
+ /* Initialise the hardware used to talk to the LCD, LED's and UART. */\r
+ PDCInit();\r
+ vParTestInitialise();\r
+ vSerialInit();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationIdleHook( void )\r
+{\r
+ /* The co-routines are executed in the idle task using the idle task \r
+ hook. */\r
+ for( ;; )\r
+ {\r
+ /* Schedule the co-routines. */\r
+ vCoRoutineSchedule();\r
+\r
+ /* Run the register check function between each co-routine. */\r
+ prvSetAndCheckRegisters();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvWriteString( const portCHAR *pcString )\r
+{\r
+ /* Write pcString to the LED, pausing between each character. */\r
+ prvPDCWrite(PDC_LCD_CSR, LCD_CLEAR); \r
+ while( *pcString )\r
+ {\r
+ vTaskDelay( mainCHAR_WRITE_DELAY );\r
+ prvPDCWrite( PDC_LCD_RAM, *pcString );\r
+ pcString++;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vLCDTask( void * pvParameters )\r
+{\r
+unsigned portBASE_TYPE uxIndex;\r
+const unsigned portCHAR ucCFGData[] = { \r
+ 0x30, /* Set data bus to 8-bits. */\r
+ 0x30,\r
+ 0x30,\r
+ 0x3C, /* Number of lines/font. */\r
+ 0x08, /* Display off. */\r
+ 0x01, /* Display clear. */\r
+ 0x06, /* Entry mode [cursor dir][shift]. */\r
+ 0x0C /* Display on [display on][curson on][blinking on]. */\r
+ }; \r
+\r
+/* The strings that are written to the LCD. */\r
+const portCHAR *pcStringsToDisplay[] = { \r
+ "Stellaris",\r
+ "Demo",\r
+ "Two",\r
+ "www.FreeRTOS.org",\r
+ ""\r
+ };\r
+\r
+ /* Configure the LCD. */\r
+ uxIndex = 0;\r
+ while( uxIndex < sizeof( ucCFGData ) )\r
+ {\r
+ prvPDCWrite( PDC_LCD_CSR, ucCFGData[ uxIndex ] );\r
+ uxIndex++;\r
+ vTaskDelay( mainCHAR_WRITE_DELAY );\r
+ }\r
+\r
+ /* Turn the LCD Backlight on. */\r
+ prvPDCWrite( PDC_CSR, 0x01 );\r
+\r
+ /* Clear display. */\r
+ vTaskDelay( mainCHAR_WRITE_DELAY );\r
+ prvPDCWrite( PDC_LCD_CSR, LCD_CLEAR ); \r
+\r
+ uxIndex = 0;\r
+ for( ;; ) \r
+ {\r
+ /* Display the string on the LCD. */\r
+ prvWriteString( pcStringsToDisplay[ uxIndex ] );\r
+ \r
+ /* Move on to the next string - wrapping if necessary. */\r
+ uxIndex++;\r
+ if( *( pcStringsToDisplay[ uxIndex ] ) == 0x00 )\r
+ {\r
+ uxIndex = 0;\r
+ /* Longer pause on the last string to be sent. */\r
+ vTaskDelay( mainSTRING_WRITE_DELAY * 2 );\r
+ }\r
+\r
+ /* Wait until it is time to move onto the next string. */\r
+ vTaskDelay( mainSTRING_WRITE_DELAY );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vCommsRxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )\r
+{\r
+static portCHAR cRxedChar, cExpectedChar = mainFIRST_TX_CHAR;\r
+portBASE_TYPE xResult;\r
+\r
+ crSTART( xHandle );\r
+\r
+ for( ;; )\r
+ {\r
+ /* Wait for a character to be received. */\r
+ crQUEUE_RECEIVE( xHandle, xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY, &xResult );\r
+\r
+ /* Was the character recived (if any) the expected character. */\r
+ if( ( cRxedChar != cExpectedChar ) || ( xResult != pdPASS ) )\r
+ {\r
+ /* Got an unexpected character. This can sometimes occur when\r
+ reseting the system using the debugger leaving characters already\r
+ in the UART regsters. */\r
+ uxErrorStatus = pdFAIL;\r
+\r
+ /* Resync by waiting for the end of the current string. */\r
+ while( cRxedChar != mainLAST_TX_CHAR )\r
+ {\r
+ crQUEUE_RECEIVE( xHandle, xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY, &xResult );\r
+ }\r
+\r
+ /* The next expected character is the start of the string again. */\r
+ cExpectedChar = mainFIRST_TX_CHAR;\r
+ }\r
+ else\r
+ {\r
+ if( cExpectedChar == mainLAST_TX_CHAR )\r
+ {\r
+ /* We have reached the end of the string - we now expect to \r
+ receive the first character in the string again. The LED is \r
+ toggled to indicate that the entire string was received without\r
+ error. */\r
+ vParTestToggleLED( mainCOMMS_RX_LED );\r
+ cExpectedChar = mainFIRST_TX_CHAR;\r
+ }\r
+ else\r
+ {\r
+ /* We got the expected character, we now expect to receive the\r
+ next character in the string. */\r
+ cExpectedChar++;\r
+ }\r
+ }\r
+ }\r
+\r
+ crEND();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )\r
+{\r
+portTickType xDelayPeriod;\r
+static unsigned portLONG *pulRandomBytes = mainFIRST_PROGRAM_BYTES;\r
+\r
+ /* Co-routine MUST start with a call to crSTART. */\r
+ crSTART( xHandle );\r
+\r
+ for(;;)\r
+ { \r
+ /* Was the previously transmitted string received correctly? */\r
+ if( uxErrorStatus != pdPASS )\r
+ {\r
+ /* An error was encountered so set the error LED. */\r
+ vSetErrorLED();\r
+ }\r
+\r
+ /* The next character to Tx is the first in the string. */\r
+ cNextChar = mainFIRST_TX_CHAR;\r
+\r
+ UARTIntDisable( UART0_BASE, UART_INT_TX );\r
+ {\r
+ /* Send the first character. */\r
+ if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) )\r
+ {\r
+ HWREG( UART0_BASE + UART_O_DR ) = cNextChar;\r
+ }\r
+\r
+ /* Move the variable to the char to Tx on so the ISR transmits\r
+ the next character in the string once this one has completed. */\r
+ cNextChar++;\r
+ }\r
+ UARTIntEnable(UART0_BASE, UART_INT_TX);\r
+\r
+ /* Toggle the LED to show a new string is being transmitted. */\r
+ vParTestToggleLED( mainCOMMS_TX_LED );\r
+\r
+ /* Delay before we start the string off again. A pseudo-random delay\r
+ is used as this will provide a better test. */\r
+ xDelayPeriod = xTaskGetTickCount() + ( *pulRandomBytes );\r
+\r
+ pulRandomBytes++;\r
+ if( pulRandomBytes > mainTOTAL_PROGRAM_MEMORY )\r
+ {\r
+ pulRandomBytes = mainFIRST_PROGRAM_BYTES;\r
+ }\r
+\r
+ /* Make sure we don't wait too long... */\r
+ xDelayPeriod &= mainMAX_TX_DELAY;\r
+\r
+ /* ...but we do want to wait. */\r
+ if( xDelayPeriod < mainMIN_TX_DELAY )\r
+ {\r
+ xDelayPeriod = mainMIN_TX_DELAY;\r
+ }\r
+\r
+ /* Block for the random(ish) time. */\r
+ crDELAY( xHandle, xDelayPeriod );\r
+ }\r
+\r
+ /* Co-routine MUST end with a call to crEND. */\r
+ crEND();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vSerialInit( void )\r
+{\r
+ /* Enable the UART. GPIOA has already been initialised. */\r
+ SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);\r
+\r
+ /* Set GPIO A0 and A1 as peripheral function. They are used to output the\r
+ UART signals. */\r
+ GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW );\r
+\r
+ /* Configure the UART for 8-N-1 operation. */\r
+ UARTConfigSet( UART0_BASE, mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE );\r
+\r
+ /* We dont want to use the fifo. This is for test purposes to generate\r
+ as many interrupts as possible. */\r
+ HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET;\r
+\r
+ /* Enable both Rx and Tx interrupts. */\r
+ HWREG( UART0_BASE + UART_O_IM ) |= ( UART_INT_TX | UART_INT_RX );\r
+ IntEnable( INT_UART0 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vUART_ISR(void)\r
+{\r
+unsigned portLONG ulStatus;\r
+portCHAR cRxedChar;\r
+portBASE_TYPE xTaskWokenByPost = pdFALSE;\r
+\r
+ /* What caused the interrupt. */\r
+ ulStatus = UARTIntStatus( UART0_BASE, pdTRUE );\r
+\r
+ /* Clear the interrupt. */\r
+ UARTIntClear( UART0_BASE, ulStatus );\r
+\r
+ /* Was an Rx interrpt pending? */\r
+ if( ulStatus & UART_INT_RX )\r
+ {\r
+ if( ( HWREG(UART0_BASE + UART_O_FR ) & UART_FR_RXFF ) )\r
+ {\r
+ /* Get the char from the buffer and post it onto the queue of\r
+ Rxed chars. Posting the character should wake the task that is \r
+ blocked on the queue waiting for characters. */\r
+ cRxedChar = ( portCHAR ) HWREG( UART0_BASE + UART_O_DR );\r
+ xTaskWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsQueue, &cRxedChar, xTaskWokenByPost );\r
+ } \r
+ }\r
+\r
+ /* Was a Tx interrupt pending? */\r
+ if( ulStatus & UART_INT_TX )\r
+ {\r
+ /* Send the next character in the string. We are not using the FIFO. */\r
+ if( cNextChar <= mainLAST_TX_CHAR )\r
+ {\r
+ if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) )\r
+ {\r
+ HWREG( UART0_BASE + UART_O_DR ) = cNextChar;\r
+ }\r
+ cNextChar++;\r
+ }\r
+ }\r
+ \r
+ if( xTaskWokenByPost )\r
+ {\r
+ /* We are posting to a co-routine rather than a task so don't bother\r
+ causing a task switch. */\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvPDCWrite( portCHAR cAddress, portCHAR cData )\r
+{\r
+ vTaskSuspendAll();\r
+ {\r
+ PDCWrite( cAddress, cData );\r
+ }\r
+ xTaskResumeAll();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSetErrorLED( void )\r
+{\r
+ vParTestSetLED( mainCOMMS_FAIL_LED, pdTRUE );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void prvSetAndCheckRegisters( void )\r
+{\r
+ /* Fill the general purpose registers with known values. */\r
+ __asm volatile\r
+ ( \r
+ " mov r11, #10 \n"\r
+ " add r0, r11, #1 \n"\r
+ " add r1, r11, #2 \n"\r
+ " add r2, r11, #3 \n"\r
+ " add r3, r11, #4 \n"\r
+ " add r4, r11, #5 \n"\r
+ " add r5, r11, #6 \n"\r
+ " add r6, r11, #7 \n"\r
+ " add r7, r11, #8 \n"\r
+ " add r8, r11, #9 \n"\r
+ " add r9, r11, #10 \n"\r
+ " add r10, r11, #11 \n"\r
+ " add r12, r11, #12" \r
+ );\r
+\r
+ /* Check the values are as expected. */\r
+ __asm volatile\r
+ ( \r
+ " cmp r11, #10 \n"\r
+ " bne set_error_led \n"\r
+ " cmp r0, #11 \n"\r
+ " bne set_error_led \n"\r
+ " cmp r1, #12 \n"\r
+ " bne set_error_led \n"\r
+ " cmp r2, #13 \n"\r
+ " bne set_error_led \n"\r
+ " cmp r3, #14 \n"\r
+ " bne set_error_led \n"\r
+ " cmp r4, #15 \n"\r
+ " bne set_error_led \n"\r
+ " cmp r5, #16 \n"\r
+ " bne set_error_led \n"\r
+ " cmp r6, #17 \n"\r
+ " bne set_error_led \n"\r
+ " cmp r7, #18 \n"\r
+ " bne set_error_led \n"\r
+ " cmp r8, #19 \n"\r
+ " bne set_error_led \n"\r
+ " cmp r9, #20 \n"\r
+ " bne set_error_led \n"\r
+ " cmp r10, #21 \n"\r
+ " bne set_error_led \n"\r
+ " cmp r12, #22 \n"\r
+ " bne set_error_led \n"\r
+ " bx lr" \r
+ );\r
+\r
+ __asm volatile\r
+ (\r
+ "set_error_led: \n"\r
+ " push {r14} \n"\r
+ " ldr r1, vSetErrorLEDConst\n"\r
+ " blx r1 \n"\r
+ " pop {r14} \n"\r
+ " bx lr \n"\r
+ " \n"\r
+ " .align 2 \n"\r
+ "vSetErrorLEDConst: .word vSetErrorLED"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*****************************************************************************\r
+ * Copyright (c) 2006 Rowley Associates Limited. *\r
+ * *\r
+ * This file may be distributed under the terms of the License Agreement *\r
+ * provided with this software. *\r
+ * *\r
+ * THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE *\r
+ * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *\r
+ *****************************************************************************/\r
+ .section .vectors, "ax"\r
+ .code 16\r
+ .align 0\r
+ .global _vectors\r
+\r
+ .extern xPortPendSVHandler\r
+ .extern xPortSysTickHandler\r
+ .extern vUART_ISR\r
+\r
+.macro DEFAULT_ISR_HANDLER name=\r
+ .thumb_func\r
+ .weak \name\r
+\name:\r
+1: b 1b /* endless loop */\r
+.endm\r
+\r
+_vectors:\r
+ .word __stack_end__\r
+ .word reset_handler\r
+ .word NmiISR\r
+ .word FaultISR\r
+ .word 0 // Populate if using MemManage (MPU)\r
+ .word 0 // Populate if using Bus fault\r
+ .word 0 // Populate if using Usage fault\r
+ .word 0 // Reserved\r
+ .word 0 // Reserved\r
+ .word 0 // Reserved\r
+ .word 0 // Reserved\r
+ .word 0\r
+ .word 0 // Populate if using a debug monitor\r
+ .word 0 // Reserved\r
+ .word xPortPendSVHandler // Populate if using pendable service request\r
+ .word xPortSysTickHandler\r
+ // External interrupts start her \r
+ .word GPIO_Port_A_ISR\r
+ .word GPIO_Port_B_ISR\r
+ .word GPIO_Port_C_ISR\r
+ .word GPIO_Port_D_ISR\r
+ .word GPIO_Port_E_ISR\r
+ .word vUART_ISR\r
+ .word UART1_ISR\r
+ .word SSI_ISR\r
+ .word I2C_ISR\r
+ .word PWM_Fault_ISR\r
+ .word PWM_Generator_0_ISR\r
+ .word PWM_Generator_1_ISR\r
+ .word PWM_Generator_2_ISR\r
+ .word QEI_ISR\r
+ .word ADC_Sequence_0_ISR\r
+ .word ADC_Sequence_1_ISR\r
+ .word ADC_Sequence_2_ISR\r
+ .word ADC_Sequence_3_ISR\r
+ .word Watchdog_timer_ISR\r
+ .word Timer0a_ISR\r
+ .word Timer0b_ISR\r
+ .word Timer1a_ISR\r
+ .word Timer1b_ISR\r
+ .word Timer2a_ISR\r
+ .word Timer2b_ISR\r
+ .word Analog_Comparator_0_ISR\r
+ .word Analog_Comparator_1_ISR\r
+ .word Analog_Comparator_2_ISR\r
+ .word System_Control_ISR\r
+ .word FLASH_Control_ISR\r
+\r
+ .section .init, "ax"\r
+ .thumb_func\r
+\r
+DEFAULT_ISR_HANDLER NmiISR\r
+DEFAULT_ISR_HANDLER FaultISR\r
+DEFAULT_ISR_HANDLER SVCallISR\r
+DEFAULT_ISR_HANDLER SysTickISR\r
+DEFAULT_ISR_HANDLER GPIO_Port_A_ISR\r
+DEFAULT_ISR_HANDLER GPIO_Port_B_ISR\r
+DEFAULT_ISR_HANDLER GPIO_Port_C_ISR\r
+DEFAULT_ISR_HANDLER GPIO_Port_D_ISR\r
+DEFAULT_ISR_HANDLER GPIO_Port_E_ISR\r
+DEFAULT_ISR_HANDLER UART0_ISR\r
+DEFAULT_ISR_HANDLER UART1_ISR\r
+DEFAULT_ISR_HANDLER SSI_ISR\r
+DEFAULT_ISR_HANDLER I2C_ISR\r
+DEFAULT_ISR_HANDLER PWM_Fault_ISR\r
+DEFAULT_ISR_HANDLER PWM_Generator_0_ISR\r
+DEFAULT_ISR_HANDLER PWM_Generator_1_ISR\r
+DEFAULT_ISR_HANDLER PWM_Generator_2_ISR\r
+DEFAULT_ISR_HANDLER QEI_ISR\r
+DEFAULT_ISR_HANDLER ADC_Sequence_0_ISR\r
+DEFAULT_ISR_HANDLER ADC_Sequence_1_ISR\r
+DEFAULT_ISR_HANDLER ADC_Sequence_2_ISR\r
+DEFAULT_ISR_HANDLER ADC_Sequence_3_ISR\r
+DEFAULT_ISR_HANDLER Watchdog_timer_ISR\r
+DEFAULT_ISR_HANDLER Timer0a_ISR\r
+DEFAULT_ISR_HANDLER Timer0b_ISR\r
+DEFAULT_ISR_HANDLER Timer1a_ISR\r
+DEFAULT_ISR_HANDLER Timer1b_ISR\r
+DEFAULT_ISR_HANDLER Timer2a_ISR\r
+DEFAULT_ISR_HANDLER Timer2b_ISR\r
+DEFAULT_ISR_HANDLER Analog_Comparator_0_ISR\r
+DEFAULT_ISR_HANDLER Analog_Comparator_1_ISR\r
+DEFAULT_ISR_HANDLER Analog_Comparator_2_ISR\r
+DEFAULT_ISR_HANDLER System_Control_ISR\r
+DEFAULT_ISR_HANDLER FLASH_Control_ISR\r
+\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. \r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 0\r
+#define configUSE_IDLE_HOOK 1\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 20000000 )\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 59 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1240 ) )\r
+#define configMAX_TASK_NAME_LEN ( 3 )\r
+#define configUSE_TRACE_FACILITY 0\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 0\r
+#define configUSE_CO_ROUTINES 1\r
+\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 )\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet 0\r
+#define INCLUDE_uxTaskPriorityGet 0\r
+#define INCLUDE_vTaskDelete 0\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 0\r
+#define INCLUDE_vTaskDelayUntil 0\r
+#define INCLUDE_vTaskDelay 0\r
+\r
+\r
+\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple parallel port IO routines.\r
+ *-----------------------------------------------------------*/\r
+\r
+/*\r
+*/\r
+\r
+/* Kernel include files. */\r
+#include "FreeRTOS.h"\r
+#include "Task.h"\r
+#include "partest.h"\r
+\r
+/* Hardware specific include files. */\r
+#include "DriverLib.h"\r
+\r
+static const unsigned portLONG ulLEDs[] =\r
+{\r
+ GPIO_PIN_6, GPIO_PIN_1, GPIO_PIN_0\r
+};\r
+\r
+#define partstLED_PINS ( GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_6 )\r
+\r
+#define partstMAX_OUTPUT_LED ( ( unsigned portCHAR ) 3 )\r
+\r
+/*-----------------------------------------------------------*/\r
+void vParTestInitialise( void )\r
+{\r
+portBASE_TYPE xLED;\r
+\r
+ /* The LED's are on port B. */\r
+ GPIODirModeSet( GPIO_PORTB_BASE, partstLED_PINS, GPIO_DIR_MODE_OUT );\r
+\r
+ for( xLED = 0; xLED < partstMAX_OUTPUT_LED; xLED++ )\r
+ {\r
+ vParTestSetLED( xLED, pdFALSE );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )\r
+{\r
+ vTaskSuspendAll();\r
+ {\r
+ if( uxLED < partstMAX_OUTPUT_LED )\r
+ {\r
+ if( xValue == pdFALSE )\r
+ {\r
+ GPIOPinWrite( GPIO_PORTB_BASE, ulLEDs[ uxLED ], ulLEDs[ uxLED ] );\r
+ }\r
+ else\r
+ {\r
+ GPIOPinWrite( GPIO_PORTB_BASE, ulLEDs[ uxLED ], ~ulLEDs[ uxLED ] );\r
+ }\r
+ } \r
+ }\r
+ xTaskResumeAll();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+portBASE_TYPE xCurrentValue;\r
+\r
+ vTaskSuspendAll();\r
+ {\r
+ if( uxLED < partstMAX_OUTPUT_LED )\r
+ {\r
+ xCurrentValue = GPIOPinRead( GPIO_PORTB_BASE, ulLEDs[ uxLED ] );\r
+ if( xCurrentValue )\r
+ {\r
+ GPIOPinWrite( GPIO_PORTB_BASE, ulLEDs[ uxLED ], ~ulLEDs[ uxLED ] );\r
+ }\r
+ else\r
+ {\r
+ GPIOPinWrite( GPIO_PORTB_BASE, ulLEDs[ uxLED ], ulLEDs[ uxLED ] );\r
+ }\r
+ }\r
+ }\r
+ xTaskResumeAll();\r
+}\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+\r
+/*\r
+ * This is a mini co-routine demo for the Rowley CrossFire LM3S102 development\r
+ * board. It makes use of the boards tri-colour LED and analogue input.\r
+ *\r
+ * Four co-routines are created - an 'I2C' co-routine and three 'flash'\r
+ * co-routines.\r
+ *\r
+ * The I2C co-routine triggers an ADC conversion then blocks on a queue to \r
+ * wait for the conversion result - which it receives on the queue directly\r
+ * from the I2C interrupt service routine. The conversion result is then\r
+ * scalled to a delay period. The I2C interrupt then wakes each of the \r
+ * flash co-routines before itself delaying for the calculated period and\r
+ * then repeating the whole process.\r
+ *\r
+ * When woken by the I2C co-routine the flash co-routines each block for \r
+ * a given period, illuminate an LED for a fixed period, then go back to\r
+ * sleep to wait for the next cycle. The uxIndex parameter of the flash\r
+ * co-routines is used to ensure that each flashes a different LED, and that\r
+ * the delay periods are such that the LED's get flashed in sequence.\r
+ */\r
+\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+#include "croutine.h"\r
+\r
+/* Demo application include files. */\r
+#include "partest.h"\r
+\r
+/* Library include files. */\r
+#include "DriverLib.h"\r
+\r
+/* States of the I2C master interface. */\r
+#define mainI2C_IDLE 0\r
+#define mainI2C_READ_1 1\r
+#define mainI2C_READ_2 2\r
+#define mainI2C_READ_DONE 3\r
+\r
+#define mainZERO_LENGTH 0\r
+\r
+/* Address of the A2D IC on the CrossFire board. */\r
+#define mainI2CAddress 0x4D\r
+\r
+/* The queue used to send data from the I2C ISR to the co-routine should never\r
+contain more than one item as the same co-routine is used to trigger the I2C\r
+activity. */\r
+#define mainQUEUE_LENGTH 1\r
+\r
+/* The CrossFire board contains a tri-colour LED. */\r
+#define mainNUM_LEDs 3\r
+\r
+/* The I2C co-routine has a higher priority than the flash co-routines. This\r
+is not really necessary as when the I2C co-routine is active the other \r
+co-routines are delaying. */\r
+#define mainI2c_CO_ROUTINE_PRIORITY 1\r
+\r
+\r
+/* The current state of the I2C master. */\r
+static volatile unsigned portBASE_TYPE uxState = mainI2C_IDLE;\r
+\r
+/* The delay period derived from the A2D value. */\r
+static volatile portBASE_TYPE uxDelay = 250;\r
+\r
+/* The queue used to communicate between the I2C interrupt and the I2C \r
+co-routine. */\r
+static xQueueHandle xADCQueue;\r
+\r
+/* The queue used to synchronise the flash co-routines. */\r
+static xQueueHandle xDelayQueue;\r
+\r
+/*\r
+ * Sets up the PLL, I2C and GPIO used by the demo.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/* The co-routines as described at the top of the file. */\r
+static void vI2CCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex );\r
+static void vFlashCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+int main( void )\r
+{\r
+unsigned portBASE_TYPE uxCoRoutine;\r
+\r
+ /* Setup all the hardware used by this demo. */\r
+ prvSetupHardware();\r
+\r
+ /* Create the queue used to communicate between the ISR and I2C co-routine.\r
+ This can only ever contain one value. */\r
+ xADCQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( portTickType ) );\r
+\r
+ /* Create the queue used to synchronise the flash co-routines. The queue\r
+ is used to trigger three tasks, but is for synchronisation only and does\r
+ not pass any data. It therefore has three position each of zero length. */\r
+ xDelayQueue = xQueueCreate( mainNUM_LEDs, mainZERO_LENGTH );\r
+\r
+ /* Create the co-routine that initiates the i2c. */\r
+ xCoRoutineCreate( vI2CCoRoutine, mainI2c_CO_ROUTINE_PRIORITY, 0 );\r
+\r
+ /* Create the flash co-routines. */\r
+ for( uxCoRoutine = 0; uxCoRoutine < mainNUM_LEDs; uxCoRoutine++ )\r
+ {\r
+ xCoRoutineCreate( vFlashCoRoutine, tskIDLE_PRIORITY, uxCoRoutine ); \r
+ }\r
+\r
+ /* Start the scheduler. From this point on the co-routines should \r
+ execute. */\r
+ vTaskStartScheduler();\r
+\r
+ /* Should not get here unless we did not have enough memory to start the\r
+ scheduler. */\r
+ for( ;; );\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+ /* Setup the PLL. */\r
+ SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ );\r
+\r
+ /* Enable the I2C used to read the pot. */\r
+ SysCtlPeripheralEnable( SYSCTL_PERIPH_I2C );\r
+ SysCtlPeripheralEnable( SYSCTL_PERIPH_GPIOB );\r
+ GPIOPinTypeI2C( GPIO_PORTB_BASE, GPIO_PIN_2 | GPIO_PIN_3 );\r
+\r
+ /* Initialize the I2C master. */\r
+ I2CMasterInit( I2C_MASTER_BASE, pdFALSE );\r
+ \r
+ /* Enable the I2C master interrupt. */\r
+ I2CMasterIntEnable( I2C_MASTER_BASE );\r
+ IntEnable( INT_I2C );\r
+\r
+ /* Initialise the hardware used to talk to the LED's. */\r
+ vParTestInitialise();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vI2CCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )\r
+{\r
+portTickType xADCResult;\r
+static portBASE_TYPE xResult = 0, xMilliSecs, xLED;\r
+\r
+ crSTART( xHandle );\r
+\r
+ for( ;; )\r
+ {\r
+ /* Start the I2C off to read the ADC. */\r
+ uxState = mainI2C_READ_1;\r
+ I2CMasterSlaveAddrSet( I2C_MASTER_BASE, mainI2CAddress, pdTRUE ); \r
+ I2CMasterControl( I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_RECEIVE_START );\r
+\r
+ /* Wait to receive the conversion result. */\r
+ crQUEUE_RECEIVE( xHandle, xADCQueue, &xADCResult, portMAX_DELAY, &xResult );\r
+\r
+ /* Scale the result to give a useful range of values for a visual \r
+ demo. */\r
+ xADCResult >>= 2;\r
+ xMilliSecs = xADCResult / portTICK_RATE_MS;\r
+\r
+ /* The delay is split between the four co-routines so they remain in\r
+ synch. */\r
+ uxDelay = xMilliSecs / ( mainNUM_LEDs + 1 );\r
+\r
+ /* Trigger each of the flash co-routines. */\r
+ for( xLED = 0; xLED < mainNUM_LEDs; xLED++ )\r
+ {\r
+ crQUEUE_SEND( xHandle, xDelayQueue, &xLED, 0, &xResult );\r
+ }\r
+\r
+ /* Wait for the full delay time then start again. This delay is long \r
+ enough to ensure the flash co-routines have done their thing and gone\r
+ back to sleep. */\r
+ crDELAY( xHandle, xMilliSecs );\r
+ }\r
+\r
+ crEND();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vFlashCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )\r
+{\r
+portBASE_TYPE xResult, xNothing;\r
+\r
+ crSTART( xHandle );\r
+\r
+ for( ;; )\r
+ {\r
+ /* Wait for start of next round. */\r
+ crQUEUE_RECEIVE( xHandle, xDelayQueue, &xNothing, portMAX_DELAY, &xResult );\r
+\r
+ /* Wait until it is this co-routines turn to flash. */\r
+ crDELAY( xHandle, uxDelay * uxIndex );\r
+\r
+ /* Turn on the LED for a fixed period. */\r
+ vParTestSetLED( uxIndex, pdTRUE );\r
+ crDELAY( xHandle, uxDelay );\r
+ vParTestSetLED( uxIndex, pdFALSE );\r
+\r
+ /* Go back and wait for the next round. */\r
+ }\r
+\r
+ crEND();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vI2C_ISR(void)\r
+{\r
+static portTickType xReading;\r
+\r
+ /* Clear the interrupt. */\r
+ I2CMasterIntClear( I2C_MASTER_BASE );\r
+\r
+ /* Determine what to do based on the current uxState. */\r
+ switch (uxState)\r
+ {\r
+ case mainI2C_IDLE: break;\r
+ \r
+ case mainI2C_READ_1: /* Read ADC result high byte. */\r
+ xReading = I2CMasterDataGet( I2C_MASTER_BASE );\r
+ xReading <<= 8;\r
+ \r
+ /* Continue the burst read. */\r
+ I2CMasterControl( I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_RECEIVE_CONT );\r
+ uxState = mainI2C_READ_2;\r
+ break;\r
+ \r
+ case mainI2C_READ_2: /* Read ADC result low byte. */\r
+ xReading |= I2CMasterDataGet( I2C_MASTER_BASE ); \r
+ \r
+ /* Finish the burst read. */\r
+ I2CMasterControl( I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_RECEIVE_FINISH );\r
+ uxState = mainI2C_READ_DONE;\r
+ break;\r
+ \r
+ case mainI2C_READ_DONE: /* Complete. */\r
+ I2CMasterDataGet( I2C_MASTER_BASE );\r
+ uxState = mainI2C_IDLE;\r
+\r
+ /* Send the result to the co-routine. */\r
+ crQUEUE_SEND_FROM_ISR( xADCQueue, &xReading, pdFALSE );\r
+ break;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationIdleHook( void )\r
+{\r
+ for( ;; )\r
+ {\r
+ vCoRoutineSchedule();\r
+ }\r
+}\r
+\r
--- /dev/null
+/*****************************************************************************\r
+ * Copyright (c) 2006 Rowley Associates Limited. *\r
+ * *\r
+ * This file may be distributed under the terms of the License Agreement *\r
+ * provided with this software. *\r
+ * *\r
+ * THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE *\r
+ * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *\r
+ *****************************************************************************/\r
+ .section .vectors, "ax"\r
+ .code 16\r
+ .align 0\r
+ .global _vectors\r
+\r
+ .extern xPortPendSVHandler\r
+ .extern xPortSysTickHandler\r
+ .extern vI2C_ISR\r
+ .extern faultisr\r
+\r
+.macro DEFAULT_ISR_HANDLER name=\r
+ .thumb_func\r
+ .weak \name\r
+\name:\r
+1: b 1b /* endless loop */\r
+.endm\r
+\r
+_vectors:\r
+ .word __stack_end__\r
+ .word reset_handler\r
+ .word NmiISR\r
+ .word FaultISR\r
+ .word 0 // Populate if using MemManage (MPU)\r
+ .word 0 // Populate if using Bus fault\r
+ .word 0 // Populate if using Usage fault\r
+ .word 0 // Reserved\r
+ .word 0 // Reserved\r
+ .word 0 // Reserved\r
+ .word 0 // Reserved\r
+ .word 0\r
+ .word 0 // Populate if using a debug monitor\r
+ .word 0 // Reserved\r
+ .word xPortPendSVHandler // Populate if using pendable service request\r
+ .word xPortSysTickHandler\r
+ // External interrupts start her \r
+ .word GPIO_Port_A_ISR\r
+ .word GPIO_Port_B_ISR\r
+ .word GPIO_Port_C_ISR\r
+ .word GPIO_Port_D_ISR\r
+ .word GPIO_Port_E_ISR\r
+ .word UART0_ISR\r
+ .word UART1_ISR\r
+ .word SSI_ISR\r
+ .word vI2C_ISR\r
+ .word PWM_Fault_ISR\r
+ .word PWM_Generator_0_ISR\r
+ .word PWM_Generator_1_ISR\r
+ .word PWM_Generator_2_ISR\r
+ .word QEI_ISR\r
+ .word ADC_Sequence_0_ISR\r
+ .word ADC_Sequence_1_ISR\r
+ .word ADC_Sequence_2_ISR\r
+ .word ADC_Sequence_3_ISR\r
+ .word Watchdog_timer_ISR\r
+ .word Timer0a_ISR\r
+ .word Timer0b_ISR\r
+ .word Timer1a_ISR\r
+ .word Timer1b_ISR\r
+ .word Timer2a_ISR\r
+ .word Timer2b_ISR\r
+ .word Analog_Comparator_0_ISR\r
+ .word Analog_Comparator_1_ISR\r
+ .word Analog_Comparator_2_ISR\r
+ .word System_Control_ISR\r
+ .word FLASH_Control_ISR\r
+\r
+ .section .init, "ax"\r
+ .thumb_func\r
+\r
+DEFAULT_ISR_HANDLER NmiISR\r
+DEFAULT_ISR_HANDLER FaultISR\r
+DEFAULT_ISR_HANDLER SVCallISR\r
+DEFAULT_ISR_HANDLER SysTickISR\r
+DEFAULT_ISR_HANDLER GPIO_Port_A_ISR\r
+DEFAULT_ISR_HANDLER GPIO_Port_B_ISR\r
+DEFAULT_ISR_HANDLER GPIO_Port_C_ISR\r
+DEFAULT_ISR_HANDLER GPIO_Port_D_ISR\r
+DEFAULT_ISR_HANDLER GPIO_Port_E_ISR\r
+DEFAULT_ISR_HANDLER UART0_ISR\r
+DEFAULT_ISR_HANDLER UART1_ISR\r
+DEFAULT_ISR_HANDLER SSI_ISR\r
+DEFAULT_ISR_HANDLER I2C_ISR\r
+DEFAULT_ISR_HANDLER PWM_Fault_ISR\r
+DEFAULT_ISR_HANDLER PWM_Generator_0_ISR\r
+DEFAULT_ISR_HANDLER PWM_Generator_1_ISR\r
+DEFAULT_ISR_HANDLER PWM_Generator_2_ISR\r
+DEFAULT_ISR_HANDLER QEI_ISR\r
+DEFAULT_ISR_HANDLER ADC_Sequence_0_ISR\r
+DEFAULT_ISR_HANDLER ADC_Sequence_1_ISR\r
+DEFAULT_ISR_HANDLER ADC_Sequence_2_ISR\r
+DEFAULT_ISR_HANDLER ADC_Sequence_3_ISR\r
+DEFAULT_ISR_HANDLER Watchdog_timer_ISR\r
+DEFAULT_ISR_HANDLER Timer0a_ISR\r
+DEFAULT_ISR_HANDLER Timer0b_ISR\r
+DEFAULT_ISR_HANDLER Timer1a_ISR\r
+DEFAULT_ISR_HANDLER Timer1b_ISR\r
+DEFAULT_ISR_HANDLER Timer2a_ISR\r
+DEFAULT_ISR_HANDLER Timer2b_ISR\r
+DEFAULT_ISR_HANDLER Analog_Comparator_0_ISR\r
+DEFAULT_ISR_HANDLER Analog_Comparator_1_ISR\r
+DEFAULT_ISR_HANDLER Analog_Comparator_2_ISR\r
+DEFAULT_ISR_HANDLER System_Control_ISR\r
+DEFAULT_ISR_HANDLER FLASH_Control_ISR\r
+\r
+\r
+\r
+\r
--- /dev/null
+<!DOCTYPE CrossStudio_Project_File>
+<solution version="1" Name="RTOSDemo" >
+ <project Name="Demo1" >
+ <configuration arm_library_instruction_set="Thumb" Target="LM3S101" property_groups_file_path="$(StudioDir)/targets/Luminary_LM3S/propertyGroups.xml" linker_memory_map_file="$(StudioDir)/targets/Luminary_LM3S/LM3S101_MemoryMap.xml" gcc_entry_point="reset_handler" build_remove_unused_symbols="Yes" arm_linker_fiq_stack_size="0" arm_architecture="v7M" project_directory="" arm_linker_irq_stack_size="0" link_include_startup_code="No" arm_target_flash_loader_type="LIBMEM RPC Loader" arm_instruction_set="Thumb" project_type="Executable" linker_printf_width_precision_supported="No" arm_linker_stack_size="128" Name="Common" arm_target_debug_interface_type="ADIv5" arm_linker_heap_size="128" />
+ <configuration arm_target_flash_loader_file_path="$(StudioDir)/targets/Luminary_LM3S/Release/Loader.elf" linker_section_placement_file="$(StudioDir)/targets/flash_placement.xml" target_reset_script="FLASHReset()" Name="Flash" Placement="Flash" />
+ <configuration linker_section_placement_file="$(StudioDir)/targets/sram_placement.xml" Name="RAM" Placement="RAM" />
+ <folder Name="Source Files" >
+ <configuration filter="c;cpp;cxx;cc;h;s;asm;inc" Name="Common" />
+ <folder Name="Demo Source" >
+ <file file_name="../Common/Minimal/crflash.c" Name="crflash.c" />
+ <file file_name="Demo1/main.c" Name="main.c" />
+ <file file_name="Demo1/ParTest.c" Name="ParTest.c" />
+ </folder>
+ <folder Name="RTOS Source" >
+ <file file_name="../../Source/tasks.c" Name="tasks.c" />
+ <file file_name="../../Source/croutine.c" Name="croutine.c" />
+ <file file_name="../../Source/list.c" Name="list.c" />
+ <file file_name="../../Source/queue.c" Name="queue.c" />
+ <file file_name="../../Source/portable/GCC/ARM_CM3/port.c" Name="port.c" >
+ <configuration gcc_optimization_level="Level 2" Name="Flash Release" />
+ </file>
+ <file file_name="../../Source/portable/MemMang/heap_1.c" Name="heap_1.c" />
+ </folder>
+ <folder Name="Library" >
+ <file file_name="hw_include/pdc.c" Name="pdc.c" />
+ </folder>
+ </folder>
+ <folder Name="System Files" >
+ <file file_name="$(StudioDir)/source/thumb_crt0.s" Name="thumb_crt0.s" />
+ <file file_name="$(StudioDir)/targets/Luminary_LM3S/LM3S_Target.js" Name="LM3S_Target.js" >
+ <configuration Name="Common" file_type="Reset Script" />
+ </file>
+ <file file_name="Demo1/vectors.s" Name="vectors.s" />
+ </folder>
+ <configuration build_remove_unused_symbols="Yes" build_quietly="No" c_preprocessor_definitions="GCC_ARMCM3_LM3S102" linker_additional_files="$(ProjectDir)/hw_include/libdriver.a" c_user_include_directories="$(ProjectDir)/demo1;$(ProjectDir)/../common/include;$(ProjectDir)/hw_include" link_include_standard_libraries="Yes" gcc_optimization_level="Level 2" build_debug_information="Yes" arm_linker_stack_size="200" Name="Flash Release" c_system_include_directories="$(StudioDir)/include;$(ProjectDir)/../../source/include;$(ProjectDir)/../../source/portable/gcc/ARM_CM3" arm_use_gcc_libraries="No" linker_output_format="None" arm_linker_heap_size="0" />
+ </project>
+ <configuration inherited_configurations="Flash;Release" Name="Flash Release" />
+ <configuration c_preprocessor_definitions="__FLASH_BUILD" hidden="Yes" Name="Flash" />
+ <configuration c_preprocessor_definitions="NDEBUG" link_include_startup_code="No" gcc_optimization_level="Level 1" build_debug_information="No" hidden="Yes" Name="Release" />
+ <project Name="Demo2" >
+ <configuration arm_library_instruction_set="Thumb" Target="LM3S101" property_groups_file_path="$(StudioDir)/targets/Luminary_LM3S/propertyGroups.xml" linker_memory_map_file="$(StudioDir)/targets/Luminary_LM3S/LM3S101_MemoryMap.xml" gcc_entry_point="reset_handler" build_remove_unused_symbols="Yes" arm_linker_fiq_stack_size="0" arm_architecture="v7M" project_directory="" arm_linker_irq_stack_size="0" link_include_startup_code="No" arm_target_flash_loader_type="LIBMEM RPC Loader" arm_instruction_set="Thumb" project_type="Executable" linker_printf_width_precision_supported="No" arm_linker_stack_size="128" Name="Common" arm_target_debug_interface_type="ADIv5" arm_linker_heap_size="128" />
+ <configuration arm_target_flash_loader_file_path="$(StudioDir)/targets/Luminary_LM3S/Release/Loader.elf" linker_section_placement_file="$(StudioDir)/targets/flash_placement.xml" target_reset_script="FLASHReset()" Name="Flash" Placement="Flash" />
+ <configuration linker_section_placement_file="$(StudioDir)/targets/sram_placement.xml" Name="RAM" Placement="RAM" />
+ <folder Name="Source Files" >
+ <configuration filter="c;cpp;cxx;cc;h;s;asm;inc" Name="Common" />
+ <folder Name="Demo Source" >
+ <file file_name="../Common/Minimal/crflash.c" Name="crflash.c" />
+ <file file_name="Demo2/main.c" Name="main.c" />
+ <file file_name="Demo2/ParTest.c" Name="ParTest.c" />
+ </folder>
+ <folder Name="RTOS Source" >
+ <file file_name="../../Source/tasks.c" Name="tasks.c" />
+ <file file_name="../../Source/croutine.c" Name="croutine.c" />
+ <file file_name="../../Source/list.c" Name="list.c" />
+ <file file_name="../../Source/queue.c" Name="queue.c" />
+ <file file_name="../../Source/portable/GCC/ARM_CM3/port.c" Name="port.c" >
+ <configuration gcc_optimization_level="Level 2" Name="Flash Release" />
+ </file>
+ <file file_name="../../Source/portable/MemMang/heap_1.c" Name="heap_1.c" />
+ </folder>
+ <folder Name="Library" >
+ <file file_name="hw_include/pdc.c" Name="pdc.c" />
+ </folder>
+ </folder>
+ <folder Name="System Files" >
+ <file file_name="$(StudioDir)/source/thumb_crt0.s" Name="thumb_crt0.s" />
+ <file file_name="$(StudioDir)/targets/Luminary_LM3S/LM3S_Target.js" Name="LM3S_Target.js" >
+ <configuration Name="Common" file_type="Reset Script" />
+ </file>
+ <file file_name="Demo2/vectors.s" Name="vectors.s" />
+ </folder>
+ <configuration build_remove_unused_symbols="Yes" build_quietly="No" c_preprocessor_definitions="GCC_ARMCM3_LM3S102" linker_additional_files="$(ProjectDir)/hw_include/libdriver.a" c_user_include_directories="$(ProjectDir)/demo2;$(ProjectDir)/../common/include;$(ProjectDir)/hw_include" link_include_standard_libraries="Yes" gcc_optimization_level="Level 2" build_debug_information="Yes" arm_linker_stack_size="200" Name="Flash Release" c_system_include_directories="$(StudioDir)/include;$(ProjectDir)/../../source/include;$(ProjectDir)/../../source/portable/gcc/ARM_CM3" arm_use_gcc_libraries="No" linker_output_format="None" arm_linker_heap_size="0" />
+ </project>
+ <project Name="Demo3" >
+ <configuration arm_library_instruction_set="Thumb" Target="LM3S101" property_groups_file_path="$(StudioDir)/targets/Luminary_LM3S/propertyGroups.xml" linker_memory_map_file="$(StudioDir)/targets/Luminary_LM3S/LM3S101_MemoryMap.xml" gcc_entry_point="reset_handler" build_remove_unused_symbols="Yes" arm_linker_fiq_stack_size="0" arm_architecture="v7M" project_directory="" arm_linker_irq_stack_size="0" link_include_startup_code="No" arm_target_flash_loader_type="LIBMEM RPC Loader" arm_instruction_set="Thumb" project_type="Executable" linker_printf_width_precision_supported="No" arm_linker_stack_size="128" Name="Common" arm_target_debug_interface_type="ADIv5" arm_linker_heap_size="128" />
+ <configuration arm_target_flash_loader_file_path="$(StudioDir)/targets/Luminary_LM3S/Release/Loader.elf" linker_section_placement_file="$(StudioDir)/targets/flash_placement.xml" target_reset_script="FLASHReset()" Name="Flash" Placement="Flash" />
+ <configuration linker_section_placement_file="$(StudioDir)/targets/sram_placement.xml" Name="RAM" Placement="RAM" />
+ <folder Name="Source Files" >
+ <configuration filter="c;cpp;cxx;cc;h;s;asm;inc" Name="Common" />
+ <folder Name="Demo Source" >
+ <file file_name="Demo3/main.c" Name="main.c" />
+ <file file_name="Demo3/ParTest.c" Name="ParTest.c" />
+ </folder>
+ <folder Name="RTOS Source" >
+ <file file_name="../../Source/tasks.c" Name="tasks.c" />
+ <file file_name="../../Source/croutine.c" Name="croutine.c" />
+ <file file_name="../../Source/list.c" Name="list.c" />
+ <file file_name="../../Source/queue.c" Name="queue.c" />
+ <file file_name="../../Source/portable/GCC/ARM_CM3/port.c" Name="port.c" >
+ <configuration gcc_optimization_level="None" Name="Flash Release" />
+ </file>
+ <file file_name="../../Source/portable/MemMang/heap_1.c" Name="heap_1.c" />
+ </folder>
+ </folder>
+ <folder Name="System Files" >
+ <file file_name="$(StudioDir)/source/thumb_crt0.s" Name="thumb_crt0.s" />
+ <file file_name="$(StudioDir)/targets/Luminary_LM3S/LM3S_Target.js" Name="LM3S_Target.js" >
+ <configuration Name="Common" file_type="Reset Script" />
+ </file>
+ <file file_name="Demo3/vectors.s" Name="vectors.s" />
+ </folder>
+ <configuration build_remove_unused_symbols="Yes" build_quietly="No" c_preprocessor_definitions="GCC_ARMCM3_LM3S102" linker_additional_files="$(ProjectDir)/hw_include/libdriver.a" c_user_include_directories="$(ProjectDir)/demo3;$(ProjectDir)/../common/include;$(ProjectDir)/hw_include" link_include_standard_libraries="Yes" gcc_optimization_level="Level 1" build_debug_information="Yes" arm_linker_stack_size="200" Name="Flash Release" c_system_include_directories="$(StudioDir)/include;$(ProjectDir)/../../source/include;$(ProjectDir)/../../source/portable/gcc/ARM_CM3" arm_use_gcc_libraries="No" linker_output_format="None" arm_linker_heap_size="0" />
+ </project>
+</solution>
--- /dev/null
+<!DOCTYPE CrossStudio_for_ARM_Session_File>
+<session>
+ <Autos>
+ <Watches active="0" />
+ </Autos>
+ <Bookmarks/>
+ <Breakpoints>
+ <BreakpointListItem actiontype="0" chainFrom="" line="-1" length="0" triggertype="0" useHWbreakpoint="false" group="ARM Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="2" mask="0" comparison="0" expression="D_Abort" filename="" />
+ <BreakpointListItem actiontype="0" chainFrom="" line="-1" length="0" triggertype="0" useHWbreakpoint="false" group="ARM Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="2" mask="0" comparison="0" expression="FIQ" filename="" />
+ <BreakpointListItem actiontype="0" chainFrom="" line="-1" length="0" triggertype="0" useHWbreakpoint="false" group="ARM Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="2" mask="0" comparison="0" expression="IRQ" filename="" />
+ <BreakpointListItem actiontype="0" chainFrom="" line="-1" length="0" triggertype="0" useHWbreakpoint="false" group="ARM Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="2" mask="0" comparison="0" expression="P_Abort" filename="" />
+ <BreakpointListItem actiontype="0" chainFrom="" line="-1" length="0" triggertype="0" useHWbreakpoint="false" group="ARM Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="2" mask="0" comparison="0" expression="Reset" filename="" />
+ <BreakpointListItem actiontype="0" chainFrom="" line="-1" length="0" triggertype="0" useHWbreakpoint="false" group="ARM Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="2" mask="0" comparison="0" expression="SWI" filename="" />
+ <BreakpointListItem actiontype="0" chainFrom="" line="-1" length="0" triggertype="0" useHWbreakpoint="false" group="ARM Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="2" mask="0" comparison="0" expression="Undef" filename="" />
+ <BreakpointListItem actiontype="0" chainFrom="" line="-1" length="0" triggertype="0" useHWbreakpoint="false" group="Cortex-M3 Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="2" mask="0" comparison="0" expression="BusFault" filename="" />
+ <BreakpointListItem actiontype="0" chainFrom="" line="-1" length="0" triggertype="0" useHWbreakpoint="false" group="Cortex-M3 Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="2" mask="0" comparison="0" expression="ExceptionEntryReturnFault" filename="" />
+ <BreakpointListItem actiontype="0" chainFrom="" line="-1" length="0" triggertype="0" useHWbreakpoint="false" group="Cortex-M3 Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="2" mask="0" comparison="0" expression="HardFault" filename="" />
+ <BreakpointListItem actiontype="0" chainFrom="" line="-1" length="0" triggertype="0" useHWbreakpoint="false" group="Cortex-M3 Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="2" mask="0" comparison="0" expression="MemManage" filename="" />
+ <BreakpointListItem actiontype="0" chainFrom="" line="-1" length="0" triggertype="0" useHWbreakpoint="false" group="Cortex-M3 Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="2" mask="0" comparison="0" expression="Reset" filename="" />
+ <BreakpointListItem actiontype="0" chainFrom="" line="-1" length="0" triggertype="0" useHWbreakpoint="false" group="Cortex-M3 Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="2" mask="0" comparison="0" expression="UsageFault_CheckingError" filename="" />
+ <BreakpointListItem actiontype="0" chainFrom="" line="-1" length="0" triggertype="0" useHWbreakpoint="false" group="Cortex-M3 Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="2" mask="0" comparison="0" expression="UsageFault_Coprocessor" filename="" />
+ <BreakpointListItem actiontype="0" chainFrom="" line="-1" length="0" triggertype="0" useHWbreakpoint="false" group="Cortex-M3 Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="2" mask="0" comparison="0" expression="UsageFault_StateError" filename="" />
+ </Breakpoints>
+ <ExecutionCountWindow/>
+ <Memory1>
+ <MemoryWindow autoEvaluate="0" addressText="0xe000e014" numColumns="8" sizeText="4" dataSize="1" radix="16" addressSpace="" />
+ </Memory1>
+ <Memory2>
+ <MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" addressSpace="" />
+ </Memory2>
+ <Memory3>
+ <MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" addressSpace="" />
+ </Memory3>
+ <Memory4>
+ <MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" addressSpace="" />
+ </Memory4>
+ <Project>
+ <ProjectSessionItem path="RTOSDemo" name="unnamed" />
+ <ProjectSessionItem path="RTOSDemo;Demo1" name="unnamed" />
+ <ProjectSessionItem path="RTOSDemo;Demo1;Source Files" name="unnamed" />
+ <ProjectSessionItem path="RTOSDemo;Demo1;Source Files;RTOS Source" name="unnamed" />
+ <ProjectSessionItem path="RTOSDemo;Demo3" name="unnamed" />
+ <ProjectSessionItem path="RTOSDemo;Demo3;Source Files" name="unnamed" />
+ <ProjectSessionItem path="RTOSDemo;Demo3;Source Files;Demo Source" name="unnamed" />
+ <ProjectSessionItem path="RTOSDemo;Demo3;System Files" name="unnamed" />
+ </Project>
+ <Register1>
+ <RegisterWindow unsignedDisplays="" asciiDisplays="" octalDisplays="" openGroups="CPU - Current Mode" visibleGroups="CPU - Current Mode" decimalDisplays="" binaryDisplays="" />
+ </Register1>
+ <Register2>
+ <RegisterWindow unsignedDisplays="" asciiDisplays="" octalDisplays="" openGroups="" visibleGroups="" decimalDisplays="" binaryDisplays="" />
+ </Register2>
+ <Register3>
+ <RegisterWindow unsignedDisplays="" asciiDisplays="" octalDisplays="" openGroups="" visibleGroups="" decimalDisplays="" binaryDisplays="" />
+ </Register3>
+ <Register4>
+ <RegisterWindow unsignedDisplays="" asciiDisplays="" octalDisplays="" openGroups="" visibleGroups="" decimalDisplays="" binaryDisplays="" />
+ </Register4>
+ <SourceNavigatorWindow/>
+ <TraceWindow>
+ <Trace wrap="Yes" type="1" enabled="Yes" />
+ </TraceWindow>
+ <Watch1>
+ <Watches active="1" >
+ <Watchpoint evalMode="0" linenumber="0" evalType="1" radix="-1" name="pxTopOfStack" expression="pxTopOfStack" filename="" />
+ <Watchpoint linenumber="0" radix="-1" name="uxCriticalNesting" expression="uxCriticalNesting" filename="" />
+ <Watchpoint evalMode="1" linenumber="0" evalType="1" radix="-1" name="xHandle" expression="xHandle" filename="" />
+ <Watchpoint linenumber="0" radix="-1" name="xTickCount" expression="xTickCount" filename="" />
+ </Watches>
+ </Watch1>
+ <Watch2>
+ <Watches active="0" />
+ </Watch2>
+ <Watch3>
+ <Watches active="0" />
+ </Watch3>
+ <Watch4>
+ <Watches active="0" />
+ </Watch4>
+ <Files>
+ <SessionOpenFile useTextEdit="1" useBinaryEdit="0" x="1" debugPath="C:\E\Dev\FreeRTOS\Source\portable\GCC\ARM_CM3\port.c" y="102" useHTMLEdit="0" path="C:\E\Dev\FreeRTOS\Source\portable\GCC\ARM_CM3\port.c" left="0" selected="1" name="unnamed" top="257" />
+ <SessionOpenFile useTextEdit="1" useBinaryEdit="0" x="0" debugPath="C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S102_Rowley\Demo3\main.c" y="117" useHTMLEdit="0" path="C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S102_Rowley\Demo3\main.c" left="0" selected="0" name="unnamed" top="82" />
+ <SessionOpenFile useTextEdit="1" useBinaryEdit="0" x="0" debugPath="C:\E\Dev\FreeRTOS\Source\croutine.c" y="275" useHTMLEdit="0" path="C:\E\Dev\FreeRTOS\Source\croutine.c" left="0" selected="0" name="unnamed" top="258" />
+ <SessionOpenFile useTextEdit="1" useBinaryEdit="0" x="0" debugPath="C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S102_Rowley\Demo3\vectors.s" y="79" useHTMLEdit="0" path="C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S102_Rowley\Demo3\vectors.s" left="0" selected="0" name="unnamed" top="44" />
+ <SessionOpenFile useTextEdit="1" useBinaryEdit="0" x="0" debugPath="C:\E\Dev\FreeRTOS\Source\tasks.c" y="1181" useHTMLEdit="0" path="C:\E\Dev\FreeRTOS\Source\tasks.c" left="0" selected="0" name="unnamed" top="1166" />
+ <SessionOpenFile useTextEdit="1" useBinaryEdit="0" x="51" debugPath="C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S102_Rowley\demo3\FreeRTOSConfig.h" y="49" useHTMLEdit="0" path="C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S102_Rowley\demo3\FreeRTOSConfig.h" left="0" selected="0" name="unnamed" top="24" />
+ <SessionOpenFile useTextEdit="1" useBinaryEdit="0" x="24" debugPath="C:\E\Dev\FreeRTOS\Source\portable\GCC\ARM_CM3\portmacro.h" y="66" useHTMLEdit="0" path="C:\E\Dev\FreeRTOS\Source\portable\GCC\ARM_CM3\portmacro.h" left="0" selected="0" name="unnamed" top="56" />
+ <SessionOpenFile useTextEdit="1" useBinaryEdit="0" x="13" debugPath="C:\E\Dev\FreeRTOS\source\include\croutine.h" y="294" useHTMLEdit="0" path="C:\E\Dev\FreeRTOS\source\include\croutine.h" left="0" selected="0" name="unnamed" top="271" />
+ <SessionOpenFile useTextEdit="1" useBinaryEdit="0" x="35" debugPath="C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S102_Rowley\Demo3\ParTest.c" y="49" useHTMLEdit="0" path="C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S102_Rowley\Demo3\ParTest.c" left="0" selected="0" name="unnamed" top="28" />
+ </Files>
+ <ARMCrossStudioWindow activeProject="Demo3" autoConnectTarget="/CrossFire LM3S102" debugSearchFileMap="C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S102_Rowley\hw_include\src\gpio.c
+C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S102_Rowley_\hw_include\src\gpio.c
+C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S102_Rowley\hw_include\src\interrupt.c
+C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S102_Rowley_\hw_include\src\interrupt.c
+C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S102_Rowley\hw_include\src\ssi.c
+C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S102_Rowley_\hw_include\src\ssi.c
+C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S102_Rowley\hw_include\src\sysctl.c
+
+C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S102_Rowley\hw_include\src\uart.c
+C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S102_Rowley_\hw_include\src\uart.c" fileDialogInitialDirectory="C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S102_Rowley\Demo3" fileDialogDefaultFilter="*.asm;*.s;*.inc" autoConnectCapabilities="1919" debugSearchPath="" buildConfiguration="Flash Release" />
+</session>
--- /dev/null
+#ifndef INCLUDE_DRIVER_LIB_H\r
+#define INCLUDE_DRIVER_LIB_H\r
+\r
+#include "hw_ints.h"\r
+#include "hw_uart.h"\r
+#include "hw_memmap.h"\r
+#include "hw_types.h"\r
+#include "hw_nvic.h"\r
+#include "hw_ssi.h"\r
+#include "hw_i2c.h"\r
+\r
+#include "gpio.h"\r
+#include "interrupt.h"\r
+#include "sysctl.h"\r
+#include "uart.h"\r
+#include "ssi.h"\r
+#include "pdc.h"\r
+#include "i2c.h"\r
+\r
+#endif\r
--- /dev/null
+IMPORTANT. Read the following LMI Software License Agreement ("Agreement")\r
+completely.\r
+\r
+LUMINARY MICRO SOFTWARE LICENSE AGREEMENT\r
+\r
+ This is a legal agreement between you (either as an individual or as an\r
+authorized representative of your employer) and Luminary Micro, Inc. ("LMI").\r
+It concerns your rights to use this file and any accompanying written materials\r
+(the "Software"). In consideration for LMI allowing you to access the\r
+Software, you are agreeing to be bound by the terms of this Agreement. If you\r
+do not agree to all of the terms of this Agreement, do not download or use the\r
+Software. If you change your mind later, stop using the Software and delete\r
+all copies of the Software in your possession or control. Any copies of the\r
+Software that you have already distributed, where permitted, and do not destroy\r
+will continue to be governed by this Agreement. Your prior use will also\r
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+\r
+1. LICENSE GRANT. LMI grants to you, free of charge, the non-exclusive,\r
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+distributed Software. If you violate any of the terms or restrictions of this\r
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+\r
+2. COPYRIGHT. The Software is licensed to you, not sold. LMI owns the\r
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+3. SUPPORT. LMI is NOT obligated to provide any support, upgrades or new\r
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+and provide suggestions regarding the Software. LMI has no obligation\r
+whatsoever to respond in any way to such a problem report or suggestion. LMI\r
+may make changes to the Software at any time, without any obligation to notify\r
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+\r
+4. INDEMNITY. You agree to fully defend and indemnify LMI from any and\r
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+related to (1) your use (including your sub-licensee\92s use, if permitted) of\r
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+Agreement.\r
+\r
+5. HIGH RISK ACTIVITIES. You acknowledge that the Software is not fault\r
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+hazardous, dangerous to life or potentially life-threatening environments\r
+requiring fail-safe performance, such as in the operation of nuclear\r
+facilities, aircraft navigation or communication systems, air traffic control,\r
+direct life support machines or weapons systems, in which the failure of\r
+products could lead directly to death, personal injury or severe physical or\r
+environmental damage ("High Risk Activities"). You specifically represent and\r
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+Software for High Risk Activities.\r
+\r
+6. PRODUCT LABELING. You are not authorized to use any LMI trademarks,\r
+brand names, or logos.\r
+\r
+7. COMPLIANCE WITH LAWS; EXPORT RESTRICTIONS. You must use the Software\r
+in accordance with all applicable U.S. laws, regulations and statutes. You\r
+agree that neither you nor your licensees (if any) intend to or will, directly\r
+or indirectly, export or transmit the Software to any country in violation of\r
+U.S. export restrictions.\r
+\r
+8. GOVERNMENT USE. Use of the Software and any corresponding\r
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+disclosure by the Government is subject to restrictions as set forth in\r
+subparagraph (c)(1)(ii) of The Rights in Technical Data and Computer Software\r
+clause at DFARS 252.227-7013 or subparagraphs (c)(l) and (2) of the Commercial\r
+Computer Software--Restricted Rights at 48 CFR 52.227-19, as applicable.\r
+Manufacturer is Luminary Micro, Inc., 2499 S. Capital of Texas Hwy Ste A-100,\r
+Austin, Texas 78746.\r
+\r
+9. DISCLAIMER OF WARRANTY. TO THE MAXIMUM EXTENT PERMITTED BY LAW, LMI\r
+EXPRESSLY DISCLAIMS ANY WARRANTY FOR THE SOFTWARE. THE SOFTWARE IS PROVIDED\r
+"AS IS", WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING,\r
+WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A\r
+PARTICULAR PURPOSE, OR NON-INFRINGEMENT. YOU ASSUME THE ENTIRE RISK ARISING\r
+OUT OF THE USE OR PERFORMANCE OF THE SOFTWARE, OR ANY SYSTEMS YOU DESIGN USING\r
+THE SOFTWARE (IF ANY). NOTHING IN THIS AGREEMENT MAY BE CONSTRUED AS A\r
+WARRANTY OR REPRESENTATION BY LMI THAT THE SOFTWARE OR ANY DERIVATIVE WORK\r
+DEVELOPED WITH OR INCORPORATING THE SOFTWARE WILL BE FREE FROM INFRINGEMENT OF\r
+THE INTELLECTUAL PROPERTY RIGHTS OF THIRD PARTIES.\r
+\r
+10. LIMITATION OF LIABILITY. IN NO EVENT WILL LMI BE LIABLE, WHETHER IN\r
+CONTRACT, TORT, OR OTHERWISE, FOR ANY INCIDENTAL, SPECIAL, INDIRECT,\r
+CONSEQUENTIAL OR PUNITIVE DAMAGES, INCLUDING, BUT NOT LIMITED TO, DAMAGES FOR\r
+ANY LOSS OF USE, LOSS OF TIME, INCONVENIENCE, COMMERCIAL LOSS, OR LOST PROFITS,\r
+SAVINGS, OR REVENUES TO THE FULL EXTENT SUCH MAY BE DISCLAIMED BY LAW.\r
+\r
+11. CHOICE OF LAW; VENUE; LIMITATIONS. You agree that the statutes and\r
+laws of the United States and the State of Texas, USA, without regard to\r
+conflicts of laws principles, will apply to all matters relating to this\r
+Agreement or the Software, and you agree that any litigation will be subject to\r
+the exclusive jurisdiction of the state or federal courts in Austin, Travis\r
+County, Texas, USA. You agree that regardless of any statute or law to the\r
+contrary, any claim or cause of action arising out of or related to this\r
+Agreement or the Software must be filed within one (1) year after such claim or\r
+cause of action arose or be forever barred.\r
+\r
+12. ENTIRE AGREEMENT. This Agreement constitutes the entire agreement\r
+between you and LMI regarding the subject matter of this Agreement, and\r
+supersedes all prior communications, negotiations, understandings, agreements\r
+or representations, either written or oral, if any. This Agreement may only be\r
+amended in written form, executed by you and LMI.\r
+\r
+13. SEVERABILITY. If any provision of this Agreement is held for any\r
+reason to be invalid or unenforceable, then the remaining provisions of this\r
+Agreement will be unimpaired and, unless a modification or replacement of the\r
+invalid or unenforceable provision is further held to deprive you or LMI of a\r
+material benefit, in which case the Agreement will immediately terminate, the\r
+invalid or unenforceable provision will be replaced with a provision that is\r
+valid and enforceable and that comes closest to the intention underlying the\r
+invalid or unenforceable provision.\r
+\r
+14. NO WAIVER. The waiver by LMI of any breach of any provision of this\r
+Agreement will not operate or be construed as a waiver of any other or a\r
+subsequent breach of the same or a different provision.\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// comp.h - Prototypes for the analog comparator driver.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 523 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __COMP_H__\r
+#define __COMP_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to ComparatorConfigure() as the ulConfig\r
+// parameter. For each group (i.e. COMP_INT_xxx, COMP_ASRCP_xxx, etc.), one of\r
+// the values may be selected and ORed together will values from the other\r
+// groups.\r
+//\r
+//*****************************************************************************\r
+#define COMP_INT_HIGH 0x00000010 // Interrupt when high\r
+#define COMP_INT_LOW 0x00000000 // Interrupt when low\r
+#define COMP_INT_FALL 0x00000004 // Interrupt on falling edge\r
+#define COMP_INT_RISE 0x00000008 // Interrupt on rising edge\r
+#define COMP_INT_BOTH 0x0000000C // Interrupt on both edges\r
+#define COMP_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin\r
+#define COMP_ASRCP_PIN0 0x00000200 // Comp0+ pin\r
+#define COMP_ASRCP_REF 0x00000400 // Internal voltage reference\r
+#define COMP_OUTPUT_NONE 0x00000000 // No comparator output\r
+#define COMP_OUTPUT_NORMAL 0x00000100 // Comparator output normal\r
+#define COMP_OUTPUT_INVERT 0x00000102 // Comparator output inverted\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to ComparatorSetRef() as the ulRef parameter.\r
+//\r
+//*****************************************************************************\r
+#define COMP_REF_OFF 0x00000000 // Turn off the internal reference\r
+#define COMP_REF_0V 0x00000300 // Internal reference of 0V\r
+#define COMP_REF_0_1375V 0x00000301 // Internal reference of 0.1375V\r
+#define COMP_REF_0_275V 0x00000302 // Internal reference of 0.275V\r
+#define COMP_REF_0_4125V 0x00000303 // Internal reference of 0.4125V\r
+#define COMP_REF_0_55V 0x00000304 // Internal reference of 0.55V\r
+#define COMP_REF_0_6875V 0x00000305 // Internal reference of 0.6875V\r
+#define COMP_REF_0_825V 0x00000306 // Internal reference of 0.825V\r
+#define COMP_REF_0_928125V 0x00000201 // Internal reference of 0.928125V\r
+#define COMP_REF_0_9625V 0x00000307 // Internal reference of 0.9625V\r
+#define COMP_REF_1_03125V 0x00000202 // Internal reference of 1.03125V\r
+#define COMP_REF_1_134375V 0x00000203 // Internal reference of 1.134375V\r
+#define COMP_REF_1_1V 0x00000308 // Internal reference of 1.1V\r
+#define COMP_REF_1_2375V 0x00000309 // Internal reference of 1.2375V\r
+#define COMP_REF_1_340625V 0x00000205 // Internal reference of 1.340625V\r
+#define COMP_REF_1_375V 0x0000030A // Internal reference of 1.375V\r
+#define COMP_REF_1_44375V 0x00000206 // Internal reference of 1.44375V\r
+#define COMP_REF_1_5125V 0x0000030B // Internal reference of 1.5125V\r
+#define COMP_REF_1_546875V 0x00000207 // Internal reference of 1.546875V\r
+#define COMP_REF_1_65V 0x0000030C // Internal reference of 1.65V\r
+#define COMP_REF_1_753125V 0x00000209 // Internal reference of 1.753125V\r
+#define COMP_REF_1_7875V 0x0000030D // Internal reference of 1.7875V\r
+#define COMP_REF_1_85625V 0x0000020A // Internal reference of 1.85625V\r
+#define COMP_REF_1_925V 0x0000030E // Internal reference of 1.925V\r
+#define COMP_REF_1_959375V 0x0000020B // Internal reference of 1.959375V\r
+#define COMP_REF_2_0625V 0x0000030F // Internal reference of 2.0625V\r
+#define COMP_REF_2_165625V 0x0000020D // Internal reference of 2.165625V\r
+#define COMP_REF_2_26875V 0x0000020E // Internal reference of 2.26875V\r
+#define COMP_REF_2_371875V 0x0000020F // Internal reference of 2.371875V\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void ComparatorConfigure(unsigned long ulBase, unsigned long ulComp,\r
+ unsigned long ulConfig);\r
+extern void ComparatorRefSet(unsigned long ulBase, unsigned long ulRef);\r
+extern tBoolean ComparatorValueGet(unsigned long ulBase, unsigned long ulComp);\r
+extern void ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp,\r
+ void (*pfnHandler)(void));\r
+extern void ComparatorIntUnregister(unsigned long ulBase,\r
+ unsigned long ulComp);\r
+extern tBoolean ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp,\r
+ tBoolean bMasked);\r
+extern void ComparatorIntClear(unsigned long ulBase, unsigned long ulComp);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __COMP_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// cpu.h - Prototypes for the CPU instruction wrapper functions.\r
+//\r
+// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 523 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __CPU_H__\r
+#define __CPU_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes.\r
+//\r
+//*****************************************************************************\r
+extern void CPUcpsid(void);\r
+extern void CPUcpsie(void);\r
+extern void CPUwfi(void);\r
+\r
+#endif // __CPU_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// debug.h - Macros for assisting debug of the driver library.\r
+//\r
+// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 523 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __DEBUG_H__\r
+#define __DEBUG_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototype for the function that is called when an invalid argument is passed\r
+// to an API. This is only used when doing a DEBUG build.\r
+//\r
+//*****************************************************************************\r
+extern void __error__(char *pcFilename, unsigned long ulLine);\r
+\r
+//*****************************************************************************\r
+//\r
+// The ASSERT macro, which does the actual assertion checking. Typically, this\r
+// will be for procedure arguments.\r
+//\r
+//*****************************************************************************\r
+#ifdef DEBUG\r
+#define ASSERT(expr) { \\r
+ if(!(expr)) \\r
+ { \\r
+ __error__(__FILE__, __LINE__); \\r
+ } \\r
+ }\r
+#else\r
+#define ASSERT(expr)\r
+#endif\r
+\r
+#endif // __DEBUG_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// flash.h - Prototypes for the flash driver.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 523 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __FLASH_H__\r
+#define __FLASH_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to FlashProtectSet(), and returned by\r
+// FlashProtectGet().\r
+//\r
+//*****************************************************************************\r
+typedef enum\r
+{\r
+ FlashReadWrite, // Flash can be read and written\r
+ FlashReadOnly, // Flash can only be read\r
+ FlashExecuteOnly // Flash can only be executed\r
+}\r
+tFlashProtection;\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern unsigned long FlashUsecGet(void);\r
+extern void FlashUsecSet(unsigned long ulClocks);\r
+extern long FlashErase(unsigned long ulAddress);\r
+extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress,\r
+ unsigned long ulCount);\r
+extern tFlashProtection FlashProtectGet(unsigned long ulAddress);\r
+extern long FlashProtectSet(unsigned long ulAddress,\r
+ tFlashProtection eProtect);\r
+extern long FlashProtectSave(void);\r
+extern void FlashIntRegister(void (*pfnHandler)(void));\r
+extern void FlashIntUnregister(void);\r
+extern void FlashIntEnable(unsigned long ulIntFlags);\r
+extern void FlashIntDisable(unsigned long ulIntFlags);\r
+extern unsigned long FlashIntGetStatus(tBoolean bMasked);\r
+extern void FlashIntClear(unsigned long ulIntFlags);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __FLASH_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// gpio.h - Defines and Macros for GPIO API.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 523 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __GPIO_H__\r
+#define __GPIO_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// The following values define the bit field for the ucPins argument to several\r
+// of the APIs.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_PIN_0 0x00000001 // GPIO pin 0\r
+#define GPIO_PIN_1 0x00000002 // GPIO pin 1\r
+#define GPIO_PIN_2 0x00000004 // GPIO pin 2\r
+#define GPIO_PIN_3 0x00000008 // GPIO pin 3\r
+#define GPIO_PIN_4 0x00000010 // GPIO pin 4\r
+#define GPIO_PIN_5 0x00000020 // GPIO pin 5\r
+#define GPIO_PIN_6 0x00000040 // GPIO pin 6\r
+#define GPIO_PIN_7 0x00000080 // GPIO pin 7\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and\r
+// returned from GPIODirModeGet.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input\r
+#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output\r
+#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and\r
+// returned from GPIOIntTypeGet.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge\r
+#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge\r
+#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges\r
+#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level\r
+#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter,\r
+// and returned by GPIOPadConfigGet in the *pulStrength parameter.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength\r
+#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength\r
+#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength\r
+#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter,\r
+// and returned by GPIOPadConfigGet in the *pulPadType parameter.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull\r
+#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up\r
+#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down\r
+#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain\r
+#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up\r
+#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down\r
+#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins,\r
+ unsigned long ulPinIO);\r
+extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin);\r
+extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins,\r
+ unsigned long ulIntType);\r
+extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin);\r
+extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins,\r
+ unsigned long ulStrength,\r
+ unsigned long ulPadType);\r
+extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin,\r
+ unsigned long *pulStrength,\r
+ unsigned long *pulPadType);\r
+extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins);\r
+extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked);\r
+extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPortIntRegister(unsigned long ulPort,\r
+ void (*pfIntHandler)(void));\r
+extern void GPIOPortIntUnregister(unsigned long ulPort);\r
+extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins,\r
+ unsigned char ucVal);\r
+extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __GPIO_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_comp.h - Macros used when accessing the comparator hardware.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 523 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_COMP_H__\r
+#define __HW_COMP_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the comparator registers.\r
+//\r
+//*****************************************************************************\r
+#define COMP_O_MIS 0x00000000 // Interrupt status register\r
+#define COMP_O_RIS 0x00000004 // Raw interrupt status register\r
+#define COMP_O_INTEN 0x00000008 // Interrupt enable register\r
+#define COMP_O_REFCTL 0x00000010 // Reference voltage control reg.\r
+#define COMP_O_ACSTAT0 0x00000020 // Comp0 status register\r
+#define COMP_O_ACCTL0 0x00000024 // Comp0 control register\r
+#define COMP_O_ACSTAT1 0x00000040 // Comp1 status register\r
+#define COMP_O_ACCTL1 0x00000044 // Comp1 control register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the COMP_MIS, COMP_RIS, and\r
+// COMP_INTEN registers.\r
+//\r
+//*****************************************************************************\r
+#define COMP_INT_1 0x00000002 // Comp1 interrupt\r
+#define COMP_INT_0 0x00000001 // Comp0 interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the COMP_REFCTL register.\r
+//\r
+//*****************************************************************************\r
+#define COMP_REFCTL_EN 0x00000200 // Reference voltage enable\r
+#define COMP_REFCTL_RNG 0x00000100 // Reference voltage range\r
+#define COMP_REFCTL_VREF_MASK 0x0000000F // Reference voltage select mask\r
+#define COMP_REFCTL_VREF_SHIFT 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the COMP_ACSTAT0 and COMP_ACSTAT1\r
+// registers.\r
+//\r
+//*****************************************************************************\r
+#define COMP_ACSTAT_OVAL 0x00000002 // Comparator output value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the COMP_ACCTL0 and COMP_ACCTL1\r
+// registers.\r
+//\r
+//*****************************************************************************\r
+#define COMP_ACCTL_TMASK 0x00000800 // Trigger enable\r
+#define COMP_ACCTL_ASRCP_MASK 0x00000600 // Vin+ source select mask\r
+#define COMP_ACCTL_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin\r
+#define COMP_ACCTL_ASRCP_PIN0 0x00000200 // Comp0+ pin\r
+#define COMP_ACCTL_ASRCP_REF 0x00000400 // Internal voltage reference\r
+#define COMP_ACCTL_ASRCP_RES 0x00000600 // Reserved\r
+#define COMP_ACCTL_OEN 0x00000100 // Comparator output enable\r
+#define COMP_ACCTL_TSVAL 0x00000080 // Trigger polarity select\r
+#define COMP_ACCTL_TSEN_MASK 0x00000060 // Trigger sense mask\r
+#define COMP_ACCTL_TSEN_LEVEL 0x00000000 // Trigger is level sense\r
+#define COMP_ACCTL_TSEN_FALL 0x00000020 // Trigger is falling edge\r
+#define COMP_ACCTL_TSEN_RISE 0x00000040 // Trigger is rising edge\r
+#define COMP_ACCTL_TSEN_BOTH 0x00000060 // Trigger is both edges\r
+#define COMP_ACCTL_ISLVAL 0x00000010 // Interrupt polarity select\r
+#define COMP_ACCTL_ISEN_MASK 0x0000000C // Interrupt sense mask\r
+#define COMP_ACCTL_ISEN_LEVEL 0x00000000 // Interrupt is level sense\r
+#define COMP_ACCTL_ISEN_FALL 0x00000004 // Interrupt is falling edge\r
+#define COMP_ACCTL_ISEN_RISE 0x00000008 // Interrupt is rising edge\r
+#define COMP_ACCTL_ISEN_BOTH 0x0000000C // Interrupt is both edges\r
+#define COMP_ACCTL_CINV 0x00000002 // Comparator output invert\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the reset values for the comparator registers.\r
+//\r
+//*****************************************************************************\r
+#define COMP_RV_MIS 0x00000000 // Interrupt status register\r
+#define COMP_RV_RIS 0x00000000 // Raw interrupt status register\r
+#define COMP_RV_INTEN 0x00000000 // Interrupt enable register\r
+#define COMP_RV_REFCTL 0x00000000 // Reference voltage control reg.\r
+#define COMP_RV_ACSTAT0 0x00000000 // Comp0 status register\r
+#define COMP_RV_ACCTL0 0x00000000 // Comp0 control register\r
+#define COMP_RV_ACSTAT1 0x00000000 // Comp1 status register\r
+#define COMP_RV_ACCTL1 0x00000000 // Comp1 control register\r
+\r
+#endif // __HW_COMP_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_flash.h - Macros used when accessing the flash controller.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 523 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_FLASH_H__\r
+#define __HW_FLASH_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the FLASH registers.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FMA 0x400FD000 // Memory address register\r
+#define FLASH_FMD 0x400FD004 // Memory data register\r
+#define FLASH_FMC 0x400FD008 // Memory control register\r
+#define FLASH_FCRIS 0x400FD00c // Raw interrupt status register\r
+#define FLASH_FCIM 0x400FD010 // Interrupt mask register\r
+#define FLASH_FCMISC 0x400FD014 // Interrupt status register\r
+#define FLASH_FMPRE 0x400FE130 // FLASH read protect register\r
+#define FLASH_FMPPE 0x400FE134 // FLASH program protect register\r
+#define FLASH_USECRL 0x400FE140 // uSec reload register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_FMC register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FMC_WRKEY_MASK 0xFFFF0000 // FLASH write key mask\r
+#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key\r
+#define FLASH_FMC_REG_MASK 0x00000F00 // Register select mask\r
+#define FLASH_FMC_REG_UDFP 0x00000000 // Select FLASH protection register\r
+#define FLASH_FMC_COMT 0x00000008 // Commit user register\r
+#define FLASH_FMC_MERASE 0x00000004 // Mass erase FLASH\r
+#define FLASH_FMC_ERASE 0x00000002 // Erase FLASH page\r
+#define FLASH_FMC_WRITE 0x00000001 // Write FLASH word\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_FCRIS register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FCRIS_PROGRAM 0x00000002 // Programming status\r
+#define FLASH_FCRIS_ACCESS 0x00000001 // Invalid access status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_FCIM register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FCIM_PROGRAM 0x00000002 // Programming mask\r
+#define FLASH_FCIM_ACCESS 0x00000001 // Invalid access mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_FMIS register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FCMISC_PROGRAM 0x00000002 // Programming status\r
+#define FLASH_FCMISC_ACCESS 0x00000001 // Invalid access status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_FMPRE and FLASH_FMPPE\r
+// registers.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FMP_BLOCK_31 0x80000000 // Enable for block 31\r
+#define FLASH_FMP_BLOCK_30 0x40000000 // Enable for block 30\r
+#define FLASH_FMP_BLOCK_29 0x20000000 // Enable for block 29\r
+#define FLASH_FMP_BLOCK_28 0x10000000 // Enable for block 28\r
+#define FLASH_FMP_BLOCK_27 0x08000000 // Enable for block 27\r
+#define FLASH_FMP_BLOCK_26 0x04000000 // Enable for block 26\r
+#define FLASH_FMP_BLOCK_25 0x02000000 // Enable for block 25\r
+#define FLASH_FMP_BLOCK_24 0x01000000 // Enable for block 24\r
+#define FLASH_FMP_BLOCK_23 0x00800000 // Enable for block 23\r
+#define FLASH_FMP_BLOCK_22 0x00400000 // Enable for block 22\r
+#define FLASH_FMP_BLOCK_21 0x00200000 // Enable for block 21\r
+#define FLASH_FMP_BLOCK_20 0x00100000 // Enable for block 20\r
+#define FLASH_FMP_BLOCK_19 0x00080000 // Enable for block 19\r
+#define FLASH_FMP_BLOCK_18 0x00040000 // Enable for block 18\r
+#define FLASH_FMP_BLOCK_17 0x00020000 // Enable for block 17\r
+#define FLASH_FMP_BLOCK_16 0x00010000 // Enable for block 16\r
+#define FLASH_FMP_BLOCK_15 0x00008000 // Enable for block 15\r
+#define FLASH_FMP_BLOCK_14 0x00004000 // Enable for block 14\r
+#define FLASH_FMP_BLOCK_13 0x00002000 // Enable for block 13\r
+#define FLASH_FMP_BLOCK_12 0x00001000 // Enable for block 12\r
+#define FLASH_FMP_BLOCK_11 0x00000800 // Enable for block 11\r
+#define FLASH_FMP_BLOCK_10 0x00000400 // Enable for block 10\r
+#define FLASH_FMP_BLOCK_9 0x00000200 // Enable for block 9\r
+#define FLASH_FMP_BLOCK_8 0x00000100 // Enable for block 8\r
+#define FLASH_FMP_BLOCK_7 0x00000080 // Enable for block 7\r
+#define FLASH_FMP_BLOCK_6 0x00000040 // Enable for block 6\r
+#define FLASH_FMP_BLOCK_5 0x00000020 // Enable for block 5\r
+#define FLASH_FMP_BLOCK_4 0x00000010 // Enable for block 4\r
+#define FLASH_FMP_BLOCK_3 0x00000008 // Enable for block 3\r
+#define FLASH_FMP_BLOCK_2 0x00000004 // Enable for block 2\r
+#define FLASH_FMP_BLOCK_1 0x00000002 // Enable for block 1\r
+#define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_USECRL register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_USECRL_MASK 0x000000FF // Clock per uSec\r
+#define FLASH_USECRL_SHIFT 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The erase size is the size of the FLASH block that is erased by an erase\r
+// operation, and the protect size is the size of the FLASH block that is\r
+// protected by each protection register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_ERASE_SIZE 0x00000400\r
+#define FLASH_PROTECT_SIZE 0x00000800\r
+\r
+#endif // __HW_FLASH_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_gpio.h - Defines and Macros for GPIO hardware.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 523 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_GPIO_H__\r
+#define __HW_GPIO_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// GPIO Register Offsets.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_O_DATA 0x00000000 // Data register.\r
+#define GPIO_O_DIR 0x00000400 // Data direction register.\r
+#define GPIO_O_IS 0x00000404 // Interrupt sense register.\r
+#define GPIO_O_IBE 0x00000408 // Interrupt both edges register.\r
+#define GPIO_O_IEV 0x0000040C // Intterupt event register.\r
+#define GPIO_O_IM 0x00000410 // Interrupt mask register.\r
+#define GPIO_O_RIS 0x00000414 // Raw interrupt status register.\r
+#define GPIO_O_MIS 0x00000418 // Masked interrupt status reg.\r
+#define GPIO_O_ICR 0x0000041C // Interrupt clear register.\r
+#define GPIO_O_AFSEL 0x00000420 // Mode control select register.\r
+#define GPIO_O_DR2R 0x00000500 // 2ma drive select register.\r
+#define GPIO_O_DR4R 0x00000504 // 4ma drive select register.\r
+#define GPIO_O_DR8R 0x00000508 // 8ma drive select register.\r
+#define GPIO_O_ODR 0x0000050C // Open drain select register.\r
+#define GPIO_O_PUR 0x00000510 // Pull up select register.\r
+#define GPIO_O_PDR 0x00000514 // Pull down select register.\r
+#define GPIO_O_SLR 0x00000518 // Slew rate control enable reg.\r
+#define GPIO_O_DEN 0x0000051C // Digital input enable register.\r
+#define GPIO_O_PeriphID0 0x00000FE0 //\r
+#define GPIO_O_PeriphID1 0x00000FE4 //\r
+#define GPIO_O_PeriphID2 0x00000FE8 //\r
+#define GPIO_O_PeriphID3 0x00000FEC //\r
+#define GPIO_O_PCellID0 0x00000FF0 //\r
+#define GPIO_O_PCellID1 0x00000FF4 //\r
+#define GPIO_O_PCellID2 0x00000FF8 //\r
+#define GPIO_O_PCellID3 0x00000FFC //\r
+\r
+//*****************************************************************************\r
+//\r
+// GPIO Register reset values.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_RV_DATA 0x00000000 // Data register reset value.\r
+#define GPIO_RV_DIR 0x00000000 // Data direction reg RV.\r
+#define GPIO_RV_IS 0x00000000 // Interrupt sense reg RV.\r
+#define GPIO_RV_IBE 0x00000000 // Interrupt both edges reg RV.\r
+#define GPIO_RV_IEV 0x00000000 // Intterupt event reg RV.\r
+#define GPIO_RV_IM 0x00000000 // Interrupt mask reg RV.\r
+#define GPIO_RV_RIS 0x00000000 // Raw interrupt status reg RV.\r
+#define GPIO_RV_MIS 0x00000000 // Masked interrupt status reg RV.\r
+#define GPIO_RV_IC 0x00000000 // Interrupt clear reg RV.\r
+#define GPIO_RV_AFSEL 0x00000000 // Mode control select reg RV.\r
+#define GPIO_RV_DR2R 0x000000FF // 2ma drive select reg RV.\r
+#define GPIO_RV_DR4R 0x00000000 // 4ma drive select reg RV.\r
+#define GPIO_RV_DR8R 0x00000000 // 8ma drive select reg RV.\r
+#define GPIO_RV_ODR 0x00000000 // Open drain select reg RV.\r
+#define GPIO_RV_PUR 0x000000FF // Pull up select reg RV.\r
+#define GPIO_RV_PDR 0x00000000 // Pull down select reg RV.\r
+#define GPIO_RV_SLR 0x00000000 // Slew rate control enable reg RV.\r
+#define GPIO_RV_DEN 0x000000FF // Digital input enable reg RV.\r
+#define GPIO_RV_PeriphID0 0x00000061 //\r
+#define GPIO_RV_PeriphID1 0x00000010 //\r
+#define GPIO_RV_PeriphID2 0x00000004 //\r
+#define GPIO_RV_PeriphID3 0x00000000 //\r
+#define GPIO_RV_PCellID0 0x0000000D //\r
+#define GPIO_RV_PCellID1 0x000000F0 //\r
+#define GPIO_RV_PCellID2 0x00000005 //\r
+#define GPIO_RV_PCellID3 0x000000B1 //\r
+\r
+#endif // __HW_GPIO_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_i2c.h - Macros used when accessing the I2C master and slave hardware.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 523 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_I2C_H__\r
+#define __HW_I2C_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the I2C master registers.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_O_SA 0x00000000 // Slave address register\r
+#define I2C_MASTER_O_CS 0x00000004 // Control and Status register\r
+#define I2C_MASTER_O_DR 0x00000008 // Data register\r
+#define I2C_MASTER_O_TPR 0x0000000C // Timer period register\r
+#define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register\r
+#define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register\r
+#define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg\r
+#define I2C_MASTER_O_ICR 0x0000001c // Interrupt clear register\r
+#define I2C_MASTER_O_CR 0x00000020 // Configuration register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the I2C slave registers.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_O_OAR 0x00000000 // Own address register\r
+#define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register\r
+#define I2C_SLAVE_O_DR 0x00000008 // Data register\r
+#define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register\r
+#define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register\r
+#define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg\r
+#define I2C_SLAVE_O_ICR 0x00000018 // Interrupt clear register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Control and Status\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde\r
+#define I2C_MASTER_CS_STOP 0x00000004 // Stop\r
+#define I2C_MASTER_CS_START 0x00000002 // Start\r
+#define I2C_MASTER_CS_RUN 0x00000001 // Run\r
+#define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy\r
+#define I2C_MASTER_CS_IDLE 0x00000020 // Idle\r
+#define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration\r
+#define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged\r
+#define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged\r
+#define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred\r
+#define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data\r
+#define I2C_MASTER_CS_ERR_MASK 0x0000001C\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define values used in determining the contents of the I2C\r
+// Master Timer Period register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period\r
+#define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period\r
+#define I2C_SCL_STANDARD 100000 // SCL standard frequency\r
+#define I2C_SCL_FAST 400000 // SCL fast frequency\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Interrupt Mask\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Raw Interrupt Status\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Masked Interrupt\r
+// Status register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Configuration\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable\r
+#define I2C_MASTER_CR_MFE 0x00000010 // Master function enable\r
+#define I2C_MASTER_CR_LPBK 0x00000001 // Loopback enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Control/Status\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device\r
+#define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received\r
+#define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Interrupt Mask\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Raw Interrupt Status\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Masked Interrupt\r
+// Status register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_MIS_MIS 0x00000001 // Master masked interrupt status\r
+\r
+#endif // __HW_I2C_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_ints.h - Macros that define the interrupt assignment on Stellaris.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 523 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_INTS_H__\r
+#define __HW_INTS_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the fault assignments.\r
+//\r
+//*****************************************************************************\r
+#define FAULT_NMI 2 // NMI fault\r
+#define FAULT_HARD 3 // Hard fault\r
+#define FAULT_MPU 4 // MPU fault\r
+#define FAULT_BUS 5 // Bus fault\r
+#define FAULT_USAGE 6 // Usage fault\r
+#define FAULT_SVCALL 11 // SVCall\r
+#define FAULT_DEBUG 12 // Debug monitor\r
+#define FAULT_PENDSV 14 // PendSV\r
+#define FAULT_SYSTICK 15 // System Tick\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the interrupt assignments.\r
+//\r
+//*****************************************************************************\r
+#define INT_GPIOA 16 // GPIO Port A\r
+#define INT_GPIOB 17 // GPIO Port B\r
+#define INT_GPIOC 18 // GPIO Port C\r
+#define INT_UART0 21 // UART0 Rx and Tx\r
+#define INT_SSI 23 // SSI Rx and Tx\r
+#define INT_I2C 24 // I2C Master and Slave\r
+#define INT_WATCHDOG 34 // Watchdog timer\r
+#define INT_TIMER0A 35 // Timer 0 subtimer A\r
+#define INT_TIMER0B 36 // Timer 0 subtimer B\r
+#define INT_TIMER1A 37 // Timer 1 subtimer A\r
+#define INT_TIMER1B 38 // Timer 1 subtimer B\r
+#define INT_COMP0 41 // Analog Comparator 0\r
+#define INT_COMP1 42 // Analog Comparator 1\r
+#define INT_SYSCTL 44 // System Control (PLL, OSC, BO)\r
+#define INT_FLASH 45 // FLASH Control\r
+\r
+//*****************************************************************************\r
+//\r
+// The total number of interrupts.\r
+//\r
+//*****************************************************************************\r
+#define NUM_INTERRUPTS 46\r
+\r
+//*****************************************************************************\r
+//\r
+// The total number of priority levels.\r
+//\r
+//*****************************************************************************\r
+#define NUM_PRIORITY 8\r
+#define NUM_PRIORITY_BITS 3\r
+\r
+#endif // __HW_INTS_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_memmap.h - Macros defining the memory map of Stellaris.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 523 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_MEMMAP_H__\r
+#define __HW_MEMMAP_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the base address of the memories and peripherals.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_BASE 0x00000000 // FLASH memory\r
+#define SRAM_BASE 0x20000000 // SRAM memory\r
+#define WATCHDOG_BASE 0x40000000 // Watchdog\r
+#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A\r
+#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B\r
+#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C\r
+#define SSI_BASE 0x40008000 // SSI\r
+#define UART0_BASE 0x4000C000 // UART0\r
+#define I2C_MASTER_BASE 0x40020000 // I2C Master\r
+#define I2C_SLAVE_BASE 0x40020800 // I2C Slave\r
+#define TIMER0_BASE 0x40030000 // Timer0\r
+#define TIMER1_BASE 0x40031000 // Timer1\r
+#define COMP_BASE 0x4003C000 // Analog comparators\r
+#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller\r
+#define SYSCTL_BASE 0x400FE000 // System Control\r
+#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell\r
+#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace\r
+#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint\r
+#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl\r
+#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit\r
+\r
+#endif // __HW_MEMMAP_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_nvic.h - Macros used when accessing the NVIC hardware.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 523 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_NVIC_H__\r
+#define __HW_NVIC_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the addresses of the NVIC registers.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg.\r
+#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status Reg.\r
+#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register\r
+#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register\r
+#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg.\r
+#define NVIC_EN0 0xE000E100 // IRQ 0 to 31 Set Enable Register\r
+#define NVIC_DIS0 0xE000E180 // IRQ 0 to 31 Clear Enable Reg.\r
+#define NVIC_PEND0 0xE000E200 // IRQ 0 to 31 Set Pending Register\r
+#define NVIC_UNPEND0 0xE000E280 // IRQ 0 to 31 Clear Pending Reg.\r
+#define NVIC_ACTIVE0 0xE000E300 // IRQ 0 to 31 Active Register\r
+#define NVIC_PRI0 0xE000E400 // IRQ 0 to 3 Priority Register\r
+#define NVIC_PRI1 0xE000E404 // IRQ 4 to 7 Priority Register\r
+#define NVIC_PRI2 0xE000E408 // IRQ 8 to 11 Priority Register\r
+#define NVIC_PRI3 0xE000E40C // IRQ 12 to 15 Priority Register\r
+#define NVIC_PRI4 0xE000E410 // IRQ 16 to 19 Priority Register\r
+#define NVIC_PRI5 0xE000E414 // IRQ 20 to 23 Priority Register\r
+#define NVIC_PRI6 0xE000E418 // IRQ 24 to 27 Priority Register\r
+#define NVIC_PRI7 0xE000E41C // IRQ 28 to 31 Priority Register\r
+#define NVIC_CPUID 0xE000ED00 // CPUID Base Register\r
+#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control State Register\r
+#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset Register\r
+#define NVIC_APINT 0xE000ED0C // App. Int & Reset Control Reg.\r
+#define NVIC_SYS_CTRL 0xE000ED10 // System Control Register\r
+#define NVIC_CFG_CTRL 0xE000ED14 // Configuration Control Register\r
+#define NVIC_SYS_PRI1 0xE000ED18 // Sys. Handlers 4 to 7 Priority\r
+#define NVIC_SYS_PRI2 0xE000ED1C // Sys. Handlers 8 to 11 Priority\r
+#define NVIC_SYS_PRI3 0xE000ED20 // Sys. Handlers 12 to 15 Priority\r
+#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State\r
+#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status Reg.\r
+#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status Register\r
+#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register\r
+#define NVIC_MM_ADDR 0xE000ED34 // Mem Manage Address Register\r
+#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address Register\r
+#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type Register\r
+#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control Register\r
+#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number Register\r
+#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address Register\r
+#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute & Size Reg.\r
+#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg.\r
+#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select\r
+#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data\r
+#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control\r
+#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt Reg.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_INT_TYPE register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32)\r
+#define NVIC_INT_TYPE_LINES_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ST_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ST_CTRL_COUNT 0x00010000 // Count flag\r
+#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source\r
+#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt enable\r
+#define NVIC_ST_CTRL_ENABLE 0x00000001 // Counter mode\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ST_RELOAD register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ST_RELOAD_M 0x00FFFFFF // Counter load value\r
+#define NVIC_ST_RELOAD_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ST_CURRENT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ST_CURRENT_M 0x00FFFFFF // Counter current value\r
+#define NVIC_ST_CURRENT_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ST_CAL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock\r
+#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew\r
+#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value\r
+#define NVIC_ST_CAL_ONEMS_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_EN0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable\r
+#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable\r
+#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable\r
+#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable\r
+#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable\r
+#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable\r
+#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable\r
+#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable\r
+#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable\r
+#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable\r
+#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable\r
+#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable\r
+#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable\r
+#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable\r
+#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable\r
+#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable\r
+#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable\r
+#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable\r
+#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable\r
+#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable\r
+#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable\r
+#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable\r
+#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable\r
+#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable\r
+#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable\r
+#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable\r
+#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable\r
+#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable\r
+#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable\r
+#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable\r
+#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable\r
+#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DIS0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable\r
+#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable\r
+#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable\r
+#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable\r
+#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable\r
+#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable\r
+#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable\r
+#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable\r
+#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable\r
+#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable\r
+#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable\r
+#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable\r
+#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable\r
+#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable\r
+#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable\r
+#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable\r
+#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable\r
+#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable\r
+#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable\r
+#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable\r
+#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable\r
+#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable\r
+#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable\r
+#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable\r
+#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable\r
+#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable\r
+#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable\r
+#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable\r
+#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable\r
+#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable\r
+#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable\r
+#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PEND0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend\r
+#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend\r
+#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend\r
+#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend\r
+#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend\r
+#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend\r
+#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend\r
+#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend\r
+#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend\r
+#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend\r
+#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend\r
+#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend\r
+#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend\r
+#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend\r
+#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend\r
+#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend\r
+#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend\r
+#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend\r
+#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend\r
+#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend\r
+#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend\r
+#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend\r
+#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend\r
+#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend\r
+#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend\r
+#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend\r
+#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend\r
+#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend\r
+#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend\r
+#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend\r
+#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend\r
+#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_UNPEND0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend\r
+#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend\r
+#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend\r
+#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend\r
+#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend\r
+#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend\r
+#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend\r
+#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend\r
+#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend\r
+#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend\r
+#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend\r
+#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend\r
+#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend\r
+#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend\r
+#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend\r
+#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend\r
+#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend\r
+#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend\r
+#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend\r
+#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend\r
+#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend\r
+#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend\r
+#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend\r
+#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend\r
+#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend\r
+#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend\r
+#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend\r
+#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend\r
+#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend\r
+#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend\r
+#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend\r
+#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ACTIVE0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active\r
+#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active\r
+#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active\r
+#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active\r
+#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active\r
+#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active\r
+#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active\r
+#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active\r
+#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active\r
+#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active\r
+#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active\r
+#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active\r
+#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active\r
+#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active\r
+#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active\r
+#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active\r
+#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active\r
+#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active\r
+#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active\r
+#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active\r
+#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active\r
+#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active\r
+#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active\r
+#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active\r
+#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active\r
+#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active\r
+#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active\r
+#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active\r
+#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active\r
+#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active\r
+#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active\r
+#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI0_INT3_M 0xFF000000 // Interrupt 3 priority mask\r
+#define NVIC_PRI0_INT2_M 0x00FF0000 // Interrupt 2 priority mask\r
+#define NVIC_PRI0_INT1_M 0x0000FF00 // Interrupt 1 priority mask\r
+#define NVIC_PRI0_INT0_M 0x000000FF // Interrupt 0 priority mask\r
+#define NVIC_PRI0_INT3_S 24\r
+#define NVIC_PRI0_INT2_S 16\r
+#define NVIC_PRI0_INT1_S 8\r
+#define NVIC_PRI0_INT0_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI1 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI1_INT7_M 0xFF000000 // Interrupt 7 priority mask\r
+#define NVIC_PRI1_INT6_M 0x00FF0000 // Interrupt 6 priority mask\r
+#define NVIC_PRI1_INT5_M 0x0000FF00 // Interrupt 5 priority mask\r
+#define NVIC_PRI1_INT4_M 0x000000FF // Interrupt 4 priority mask\r
+#define NVIC_PRI1_INT7_S 24\r
+#define NVIC_PRI1_INT6_S 16\r
+#define NVIC_PRI1_INT5_S 8\r
+#define NVIC_PRI1_INT4_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI2 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI2_INT11_M 0xFF000000 // Interrupt 11 priority mask\r
+#define NVIC_PRI2_INT10_M 0x00FF0000 // Interrupt 10 priority mask\r
+#define NVIC_PRI2_INT9_M 0x0000FF00 // Interrupt 9 priority mask\r
+#define NVIC_PRI2_INT8_M 0x000000FF // Interrupt 8 priority mask\r
+#define NVIC_PRI2_INT11_S 24\r
+#define NVIC_PRI2_INT10_S 16\r
+#define NVIC_PRI2_INT9_S 8\r
+#define NVIC_PRI2_INT8_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI3 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI3_INT15_M 0xFF000000 // Interrupt 15 priority mask\r
+#define NVIC_PRI3_INT14_M 0x00FF0000 // Interrupt 14 priority mask\r
+#define NVIC_PRI3_INT13_M 0x0000FF00 // Interrupt 13 priority mask\r
+#define NVIC_PRI3_INT12_M 0x000000FF // Interrupt 12 priority mask\r
+#define NVIC_PRI3_INT15_S 24\r
+#define NVIC_PRI3_INT14_S 16\r
+#define NVIC_PRI3_INT13_S 8\r
+#define NVIC_PRI3_INT12_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI4 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI4_INT19_M 0xFF000000 // Interrupt 19 priority mask\r
+#define NVIC_PRI4_INT18_M 0x00FF0000 // Interrupt 18 priority mask\r
+#define NVIC_PRI4_INT17_M 0x0000FF00 // Interrupt 17 priority mask\r
+#define NVIC_PRI4_INT16_M 0x000000FF // Interrupt 16 priority mask\r
+#define NVIC_PRI4_INT19_S 24\r
+#define NVIC_PRI4_INT18_S 16\r
+#define NVIC_PRI4_INT17_S 8\r
+#define NVIC_PRI4_INT16_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI5 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI5_INT23_M 0xFF000000 // Interrupt 23 priority mask\r
+#define NVIC_PRI5_INT22_M 0x00FF0000 // Interrupt 22 priority mask\r
+#define NVIC_PRI5_INT21_M 0x0000FF00 // Interrupt 21 priority mask\r
+#define NVIC_PRI5_INT20_M 0x000000FF // Interrupt 20 priority mask\r
+#define NVIC_PRI5_INT23_S 24\r
+#define NVIC_PRI5_INT22_S 16\r
+#define NVIC_PRI5_INT21_S 8\r
+#define NVIC_PRI5_INT20_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI6 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI6_INT27_M 0xFF000000 // Interrupt 27 priority mask\r
+#define NVIC_PRI6_INT26_M 0x00FF0000 // Interrupt 26 priority mask\r
+#define NVIC_PRI6_INT25_M 0x0000FF00 // Interrupt 25 priority mask\r
+#define NVIC_PRI6_INT24_M 0x000000FF // Interrupt 24 priority mask\r
+#define NVIC_PRI6_INT27_S 24\r
+#define NVIC_PRI6_INT26_S 16\r
+#define NVIC_PRI6_INT25_S 8\r
+#define NVIC_PRI6_INT24_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI7 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI7_INT31_M 0xFF000000 // Interrupt 31 priority mask\r
+#define NVIC_PRI7_INT30_M 0x00FF0000 // Interrupt 30 priority mask\r
+#define NVIC_PRI7_INT29_M 0x0000FF00 // Interrupt 29 priority mask\r
+#define NVIC_PRI7_INT28_M 0x000000FF // Interrupt 28 priority mask\r
+#define NVIC_PRI7_INT31_S 24\r
+#define NVIC_PRI7_INT30_S 16\r
+#define NVIC_PRI7_INT29_S 8\r
+#define NVIC_PRI7_INT28_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_CPUID register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer\r
+#define NVIC_CPUID_VAR_M 0x00F00000 // Variant\r
+#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Processor part number\r
+#define NVIC_CPUID_REV_M 0x0000000F // Revision\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_INT_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_INT_CTRL_NMI_SET 0x80000000 // Pend a NMI\r
+#define NVIC_INT_CTRL_PEND_SV 0x10000000 // Pend a PendSV\r
+#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // Unpend a PendSV\r
+#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug interrupt handling\r
+#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Debug interrupt pending\r
+#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 // Highest pending exception\r
+#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to base\r
+#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF // Current active exception\r
+#define NVIC_INT_CTRL_VEC_PEN_S 12\r
+#define NVIC_INT_CTRL_VEC_ACT_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_VTABLE register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_VTABLE_BASE 0x20000000 // Vector table base\r
+#define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 // Vector table offset\r
+#define NVIC_VTABLE_OFFSET_S 8\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_APINT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Vector key mask\r
+#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key\r
+#define NVIC_APINT_ENDIANESS 0x00008000 // Data endianess\r
+#define NVIC_APINT_PRIGROUP_M 0x00000700 // Priority group\r
+#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split\r
+#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split\r
+#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split\r
+#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split\r
+#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split\r
+#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split\r
+#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split\r
+#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split\r
+#define NVIC_APINT_SYSRESETREQ 0x00000004 // System reset request\r
+#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear active NMI/fault info\r
+#define NVIC_APINT_VECT_RESET 0x00000001 // System reset\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SYS_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wakeup on pend\r
+#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep sleep enable\r
+#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR exit\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_CFG_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault\r
+#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on divide by 0\r
+#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on unaligned access\r
+#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 // Allow deep interrupt trigger\r
+#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow main interrupt trigger\r
+#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread state control\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SYS_PRI1 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SYS_PRI1_RES_M 0xFF000000 // Priority of reserved handler\r
+#define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 // Priority of usage fault handler\r
+#define NVIC_SYS_PRI1_BUS_M 0x0000FF00 // Priority of bus fault handler\r
+#define NVIC_SYS_PRI1_MEM_M 0x000000FF // Priority of mem manage handler\r
+#define NVIC_SYS_PRI1_USAGE_S 16\r
+#define NVIC_SYS_PRI1_BUS_S 8\r
+#define NVIC_SYS_PRI1_MEM_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SYS_PRI2 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SYS_PRI2_SVC_M 0xFF000000 // Priority of SVCall handler\r
+#define NVIC_SYS_PRI2_RES_M 0x00FFFFFF // Priority of reserved handlers\r
+#define NVIC_SYS_PRI2_SVC_S 24\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SYS_PRI3 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SYS_PRI3_TICK_M 0xFF000000 // Priority of Sys Tick handler\r
+#define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 // Priority of PendSV handler\r
+#define NVIC_SYS_PRI3_RES_M 0x0000FF00 // Priority of reserved handler\r
+#define NVIC_SYS_PRI3_DEBUG_M 0x000000FF // Priority of debug handler\r
+#define NVIC_SYS_PRI3_TICK_S 24\r
+#define NVIC_SYS_PRI3_PENDSV_S 16\r
+#define NVIC_SYS_PRI3_DEBUG_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SYS_HND_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage fault enable\r
+#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus fault enable\r
+#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Mem manage fault enable\r
+#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVCall is pended\r
+#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus fault is pended\r
+#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // Sys tick is active\r
+#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV is active\r
+#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Monitor is active\r
+#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVCall is active\r
+#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage fault is active\r
+#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus fault is active\r
+#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Mem manage is active\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_FAULT_STAT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide by zero fault\r
+#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned access fault\r
+#define NVIC_FAULT_STAT_NOCP 0x00080000 // No coprocessor fault\r
+#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC fault\r
+#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid state fault\r
+#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined instruction fault\r
+#define NVIC_FAULT_STAT_BFARV 0x00008000 // BFAR is valid\r
+#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack bus fault\r
+#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack bus fault\r
+#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise data bus error\r
+#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise data bus error\r
+#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction bus fault\r
+#define NVIC_FAULT_STAT_MMARV 0x00000080 // MMAR is valid\r
+#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack access violation\r
+#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack access violation\r
+#define NVIC_FAULT_STAT_DERR 0x00000002 // Data access violation\r
+#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction access violation\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_HFAULT_STAT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug event\r
+#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Cannot execute fault handler\r
+#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector table read fault\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DEBUG_STAT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted\r
+#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch\r
+#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match\r
+#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction\r
+#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MM_ADDR register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MM_ADDR_M 0xFFFFFFFF // Data fault address\r
+#define NVIC_MM_ADDR_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_FAULT_ADDR register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Data bus fault address\r
+#define NVIC_FAULT_ADDR_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_EXC_STACK register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_EXC_STACK_DEEP 0x00000001 // Exception stack\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_EXC_NUM register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_EXC_NUM_M 0x000003FF // Exception number\r
+#define NVIC_EXC_NUM_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_COPRO register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_COPRO_15_M 0xC0000000 // Coprocessor 15 access mask\r
+#define NVIC_COPRO_15_DENIED 0x00000000 // Coprocessor 15 access denied\r
+#define NVIC_COPRO_15_PRIV 0x40000000 // Coprocessor 15 privileged addess\r
+#define NVIC_COPRO_15_FULL 0xC0000000 // Coprocessor 15 full access\r
+#define NVIC_COPRO_14_M 0x30000000 // Coprocessor 14 access mask\r
+#define NVIC_COPRO_14_DENIED 0x00000000 // Coprocessor 14 access denied\r
+#define NVIC_COPRO_14_PRIV 0x10000000 // Coprocessor 14 privileged addess\r
+#define NVIC_COPRO_14_FULL 0x30000000 // Coprocessor 14 full access\r
+#define NVIC_COPRO_13_M 0x0C000000 // Coprocessor 13 access mask\r
+#define NVIC_COPRO_13_DENIED 0x00000000 // Coprocessor 13 access denied\r
+#define NVIC_COPRO_13_PRIV 0x04000000 // Coprocessor 13 privileged addess\r
+#define NVIC_COPRO_13_FULL 0x0C000000 // Coprocessor 13 full access\r
+#define NVIC_COPRO_12_M 0x03000000 // Coprocessor 12 access mask\r
+#define NVIC_COPRO_12_DENIED 0x00000000 // Coprocessor 12 access denied\r
+#define NVIC_COPRO_12_PRIV 0x01000000 // Coprocessor 12 privileged addess\r
+#define NVIC_COPRO_12_FULL 0x03000000 // Coprocessor 12 full access\r
+#define NVIC_COPRO_11_M 0x00C00000 // Coprocessor 11 access mask\r
+#define NVIC_COPRO_11_DENIED 0x00000000 // Coprocessor 11 access denied\r
+#define NVIC_COPRO_11_PRIV 0x00400000 // Coprocessor 11 privileged addess\r
+#define NVIC_COPRO_11_FULL 0x00C00000 // Coprocessor 11 full access\r
+#define NVIC_COPRO_10_M 0x00300000 // Coprocessor 10 access mask\r
+#define NVIC_COPRO_10_DENIED 0x00000000 // Coprocessor 10 access denied\r
+#define NVIC_COPRO_10_PRIV 0x00100000 // Coprocessor 10 privileged addess\r
+#define NVIC_COPRO_10_FULL 0x00300000 // Coprocessor 10 full access\r
+#define NVIC_COPRO_9_M 0x000C0000 // Coprocessor 9 access mask\r
+#define NVIC_COPRO_9_DENIED 0x00000000 // Coprocessor 9 access denied\r
+#define NVIC_COPRO_9_PRIV 0x00040000 // Coprocessor 9 privileged addess\r
+#define NVIC_COPRO_9_FULL 0x000C0000 // Coprocessor 9 full access\r
+#define NVIC_COPRO_8_M 0x00030000 // Coprocessor 8 access mask\r
+#define NVIC_COPRO_8_DENIED 0x00000000 // Coprocessor 8 access denied\r
+#define NVIC_COPRO_8_PRIV 0x00010000 // Coprocessor 8 privileged addess\r
+#define NVIC_COPRO_8_FULL 0x00030000 // Coprocessor 8 full access\r
+#define NVIC_COPRO_7_M 0x0000C000 // Coprocessor 7 access mask\r
+#define NVIC_COPRO_7_DENIED 0x00000000 // Coprocessor 7 access denied\r
+#define NVIC_COPRO_7_PRIV 0x00004000 // Coprocessor 7 privileged addess\r
+#define NVIC_COPRO_7_FULL 0x0000C000 // Coprocessor 7 full access\r
+#define NVIC_COPRO_6_M 0x00003000 // Coprocessor 6 access mask\r
+#define NVIC_COPRO_6_DENIED 0x00000000 // Coprocessor 6 access denied\r
+#define NVIC_COPRO_6_PRIV 0x00001000 // Coprocessor 6 privileged addess\r
+#define NVIC_COPRO_6_FULL 0x00003000 // Coprocessor 6 full access\r
+#define NVIC_COPRO_5_M 0x00000C00 // Coprocessor 5 access mask\r
+#define NVIC_COPRO_5_DENIED 0x00000000 // Coprocessor 5 access denied\r
+#define NVIC_COPRO_5_PRIV 0x00000400 // Coprocessor 5 privileged addess\r
+#define NVIC_COPRO_5_FULL 0x00000C00 // Coprocessor 5 full access\r
+#define NVIC_COPRO_4_M 0x00000300 // Coprocessor 4 access mask\r
+#define NVIC_COPRO_4_DENIED 0x00000000 // Coprocessor 4 access denied\r
+#define NVIC_COPRO_4_PRIV 0x00000100 // Coprocessor 4 privileged addess\r
+#define NVIC_COPRO_4_FULL 0x00000300 // Coprocessor 4 full access\r
+#define NVIC_COPRO_3_M 0x000000C0 // Coprocessor 3 access mask\r
+#define NVIC_COPRO_3_DENIED 0x00000000 // Coprocessor 3 access denied\r
+#define NVIC_COPRO_3_PRIV 0x00000040 // Coprocessor 3 privileged addess\r
+#define NVIC_COPRO_3_FULL 0x000000C0 // Coprocessor 3 full access\r
+#define NVIC_COPRO_2_M 0x00000030 // Coprocessor 2 access mask\r
+#define NVIC_COPRO_2_DENIED 0x00000000 // Coprocessor 2 access denied\r
+#define NVIC_COPRO_2_PRIV 0x00000010 // Coprocessor 2 privileged addess\r
+#define NVIC_COPRO_2_FULL 0x00000030 // Coprocessor 2 full access\r
+#define NVIC_COPRO_1_M 0x0000000C // Coprocessor 1 access mask\r
+#define NVIC_COPRO_1_DENIED 0x00000000 // Coprocessor 1 access denied\r
+#define NVIC_COPRO_1_PRIV 0x00000004 // Coprocessor 1 privileged addess\r
+#define NVIC_COPRO_1_FULL 0x0000000C // Coprocessor 1 full access\r
+#define NVIC_COPRO_0_M 0x00000003 // Coprocessor 0 access mask\r
+#define NVIC_COPRO_0_DENIED 0x00000000 // Coprocessor 0 access denied\r
+#define NVIC_COPRO_0_PRIV 0x00000001 // Coprocessor 0 privileged addess\r
+#define NVIC_COPRO_0_FULL 0x00000003 // Coprocessor 0 full access\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MPU_TYPE register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I regions\r
+#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D regions\r
+#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or unified MPU\r
+#define NVIC_MPU_TYPE_IREGION_S 16\r
+#define NVIC_MPU_TYPE_DREGION_S 8\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MPU_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU enabled during faults\r
+#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MPU_NUMBER register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MPU_NUMBER_M 0x000000FF // MPU region to access\r
+#define NVIC_MPU_NUMBER_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MPU_BASE register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MPU_BASE_ADDR_M 0xFFFFFF00 // Base address\r
+#define NVIC_MPU_BASE_VALID 0x00000010 // Region number valid\r
+#define NVIC_MPU_BASE_REGION_M 0x0000000F // Region number\r
+#define NVIC_MPU_BASE_ADDR_S 8\r
+#define NVIC_MPU_BASE_REGION_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MPU_ATTR register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MPU_ATTR_ATTRS 0xFFFF0000 // Attributes\r
+#define NVIC_MPU_ATTR_SRD 0x0000FF00 // Sub-region disable\r
+#define NVIC_MPU_ATTR_SZENABLE 0x000000FF // Region size\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DBG_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask\r
+#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key\r
+#define NVIC_DBG_CTRL_MON_PEND 0x00008000 // Pend the monitor\r
+#define NVIC_DBG_CTRL_MON_REQ 0x00004000 // Monitor request\r
+#define NVIC_DBG_CTRL_MON_EN 0x00002000 // Debug monitor enable\r
+#define NVIC_DBG_CTRL_MONSTEP 0x00001000 // Monitor step the core\r
+#define NVIC_DBG_CTRL_S_SLEEP 0x00000400 // Core is sleeping\r
+#define NVIC_DBG_CTRL_S_HALT 0x00000200 // Core status on halt\r
+#define NVIC_DBG_CTRL_S_REGRDY 0x00000100 // Register read/write available\r
+#define NVIC_DBG_CTRL_S_LOCKUP 0x00000080 // Core is locked up\r
+#define NVIC_DBG_CTRL_C_RESET 0x00000010 // Reset the core\r
+#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping\r
+#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core\r
+#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core\r
+#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DBG_XFER register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read\r
+#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register\r
+#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0\r
+#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1\r
+#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2\r
+#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3\r
+#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4\r
+#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5\r
+#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6\r
+#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7\r
+#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8\r
+#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9\r
+#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10\r
+#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11\r
+#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12\r
+#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13\r
+#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14\r
+#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15\r
+#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register\r
+#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP\r
+#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP\r
+#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP\r
+#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DBG_DATA register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache\r
+#define NVIC_DBG_DATA_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DBG_INT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault\r
+#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors\r
+#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error\r
+#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state\r
+#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check\r
+#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error\r
+#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault\r
+#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status\r
+#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset\r
+#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending\r
+#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SW_TRIG register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SW_TRIG_INTID_M 0x000003FF // Interrupt to trigger\r
+#define NVIC_SW_TRIG_INTID_S 0\r
+\r
+#endif // __HW_NVIC_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_ssi.h - Macros used when accessing the SSI hardware.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 523 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_SSI_H__\r
+#define __HW_SSI_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the SSI registers.\r
+//\r
+//*****************************************************************************\r
+#define SSI_O_CR0 0x00000000 // Control register 0\r
+#define SSI_O_CR1 0x00000004 // Control register 1\r
+#define SSI_O_DR 0x00000008 // Data register\r
+#define SSI_O_SR 0x0000000C // Status register\r
+#define SSI_O_CPSR 0x00000010 // Clock prescale register\r
+#define SSI_O_IM 0x00000014 // Int mask set and clear register\r
+#define SSI_O_RIS 0x00000018 // Raw interrupt register\r
+#define SSI_O_MIS 0x0000001C // Masked interrupt register\r
+#define SSI_O_ICR 0x00000020 // Interrupt clear register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SSI Control register 0.\r
+//\r
+//*****************************************************************************\r
+#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate\r
+#define SSI_CR0_SPH 0x00000080 // SSPCLKOUT phase\r
+#define SSI_CR0_SPO 0x00000040 // SSPCLKOUT polarity\r
+#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask\r
+#define SSI_CR0_FRF_MOTO 0x00000000 // Motorola SPI frame format\r
+#define SSI_CR0_FRF_TI 0x00000010 // TI sync serial frame format\r
+#define SSI_CR0_FRF_NMW 0x00000020 // National Microwire frame format\r
+#define SSI_CR0_DSS 0x0000000F // Data size select\r
+#define SSI_CR0_DSS_4 0x00000003 // 4 bit data\r
+#define SSI_CR0_DSS_5 0x00000004 // 5 bit data\r
+#define SSI_CR0_DSS_6 0x00000005 // 6 bit data\r
+#define SSI_CR0_DSS_7 0x00000006 // 7 bit data\r
+#define SSI_CR0_DSS_8 0x00000007 // 8 bit data\r
+#define SSI_CR0_DSS_9 0x00000008 // 9 bit data\r
+#define SSI_CR0_DSS_10 0x00000009 // 10 bit data\r
+#define SSI_CR0_DSS_11 0x0000000A // 11 bit data\r
+#define SSI_CR0_DSS_12 0x0000000B // 12 bit data\r
+#define SSI_CR0_DSS_13 0x0000000C // 13 bit data\r
+#define SSI_CR0_DSS_14 0x0000000D // 14 bit data\r
+#define SSI_CR0_DSS_15 0x0000000E // 15 bit data\r
+#define SSI_CR0_DSS_16 0x0000000F // 16 bit data\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SSI Control register 1.\r
+//\r
+//*****************************************************************************\r
+#define SSI_CR1_SOD 0x00000008 // Slave mode output disable\r
+#define SSI_CR1_MS 0x00000004 // Master or slave mode select\r
+#define SSI_CR1_SSE 0x00000002 // Sync serial port enable\r
+#define SSI_CR1_LBM 0x00000001 // Loopback mode\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SSI Status register\r
+//\r
+//*****************************************************************************\r
+#define SSI_SR_BSY 0x00000010 // SSI busy\r
+#define SSI_SR_RFF 0x00000008 // RX FIFO full\r
+#define SSI_SR_RNE 0x00000004 // RX FIFO not empty\r
+#define SSI_SR_TNF 0x00000002 // TX FIFO not full\r
+#define SSI_SR_TFE 0x00000001 // TX FIFO empty\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define information concerning the SSI Data register.\r
+//\r
+//*****************************************************************************\r
+#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO\r
+#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the interrupt mask set and clear,\r
+// raw interrupt, masked interrupt, and interrupt clear registers.\r
+//\r
+//*****************************************************************************\r
+#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt\r
+#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt\r
+#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt\r
+#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt\r
+\r
+#endif // __HW_SSI_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_sysctl.h - Macros used when accessing the system control hardware.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 523 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_SYSCTL_H__\r
+#define __HW_SYSCTL_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the system control registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DID0 0x400fe000 // Device identification register 0\r
+#define SYSCTL_DID1 0x400fe004 // Device identification register 1\r
+#define SYSCTL_DC0 0x400fe008 // Device capabilities register 0\r
+#define SYSCTL_DC1 0x400fe010 // Device capabilities register 1\r
+#define SYSCTL_DC2 0x400fe014 // Device capabilities register 2\r
+#define SYSCTL_DC3 0x400fe018 // Device capabilities register 3\r
+#define SYSCTL_DC4 0x400fe01C // Device capabilities register 4\r
+#define SYSCTL_PBORCTL 0x400fe030 // POR/BOR reset control register\r
+#define SYSCTL_LDOPCTL 0x400fe034 // LDO power control register\r
+#define SYSCTL_SRCR0 0x400fe040 // Software reset control reg 0\r
+#define SYSCTL_SRCR1 0x400fe044 // Software reset control reg 1\r
+#define SYSCTL_SRCR2 0x400fe048 // Software reset control reg 2\r
+#define SYSCTL_RIS 0x400fe050 // Raw interrupt status register\r
+#define SYSCTL_IMC 0x400fe054 // Interrupt mask/control register\r
+#define SYSCTL_MISC 0x400fe058 // Interrupt status register\r
+#define SYSCTL_RESC 0x400fe05c // Reset cause register\r
+#define SYSCTL_RCC 0x400fe060 // Run-mode clock config register\r
+#define SYSCTL_PLLCFG 0x400fe064 // PLL configuration register\r
+#define SYSCTL_RCGC0 0x400fe100 // Run-mode clock gating register 0\r
+#define SYSCTL_RCGC1 0x400fe104 // Run-mode clock gating register 1\r
+#define SYSCTL_RCGC2 0x400fe108 // Run-mode clock gating register 2\r
+#define SYSCTL_SCGC0 0x400fe110 // Sleep-mode clock gating reg 0\r
+#define SYSCTL_SCGC1 0x400fe114 // Sleep-mode clock gating reg 1\r
+#define SYSCTL_SCGC2 0x400fe118 // Sleep-mode clock gating reg 2\r
+#define SYSCTL_DCGC0 0x400fe120 // Deep Sleep-mode clock gate reg 0\r
+#define SYSCTL_DCGC1 0x400fe124 // Deep Sleep-mode clock gate reg 1\r
+#define SYSCTL_DCGC2 0x400fe128 // Deep Sleep-mode clock gate reg 2\r
+#define SYSCTL_CLKVCLR 0x400fe150 // Clock verifcation clear register\r
+#define SYSCTL_LDOARST 0x400fe160 // LDO reset control register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DID0 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask\r
+#define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A\r
+#define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B\r
+#define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask\r
+#define SYSCTL_DID0_MIN_0 0x00000000 // Minor revision 0\r
+#define SYSCTL_DID0_MIN_1 0x00000001 // Minor revision 1\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DID1 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask\r
+#define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask\r
+#define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family\r
+#define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask\r
+#define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101\r
+#define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102\r
+#define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask\r
+#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temp range (0..70C)\r
+#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temp range (-40..85C)\r
+#define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask\r
+#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // 28-pin SOIC\r
+#define SYSCTL_DID1_ROHS 0x00000004 // Part is RoHS compliant\r
+#define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask\r
+#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering sample (unqualified)\r
+#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot production (unqualified)\r
+#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully qualified\r
+#define SYSCTL_DID1_PRTNO_SHIFT 16\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DC0 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask\r
+#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2kB of SRAM\r
+#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask\r
+#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8kB of flash\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DC1 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask\r
+#define SYSCTL_DC1_MPU 0x00000080 // Cortex M3 MPU present\r
+#define SYSCTL_DC1_PLL 0x00000010 // PLL present\r
+#define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present\r
+#define SYSCTL_DC1_SWO 0x00000004 // Serial wire output present\r
+#define SYSCTL_DC1_SWD 0x00000002 // Serial wire debug present\r
+#define SYSCTL_DC1_JTAG 0x00000001 // JTAG debug present\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DC2 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC2_COMP1 0x02000000 // Analog comparator 1 present\r
+#define SYSCTL_DC2_COMP0 0x01000000 // Analog comparator 0 present\r
+#define SYSCTL_DC2_TIMER1 0x00020000 // Timer 1 present\r
+#define SYSCTL_DC2_TIMER0 0x00010000 // Timer 0 present\r
+#define SYSCTL_DC2_I2C 0x00001000 // I2C present\r
+#define SYSCTL_DC2_SSI 0x00000010 // SSI present\r
+#define SYSCTL_DC2_UART0 0x00000001 // UART 0 present\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DC3 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC3_32KHZ 0x80000000 // 32kHz pin present\r
+#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 pin present\r
+#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 pin present\r
+#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- pin present\r
+#define SYSCTL_DC3_C0O 0x00000100 // C0o pin present\r
+#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ pin present\r
+#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- pin present\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DC4 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO port C present\r
+#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO port B present\r
+#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO port A present\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_PBORCTL register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC // BOR wait timer\r
+#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR interrupt or reset\r
+#define SYSCTL_PBORCTL_BORWT 0x00000001 // BOR wait and check for noise\r
+#define SYSCTL_PBORCTL_BOR_SH 2\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_LDOPCTL register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_LDOPCTL_MASK 0x0000003F // Voltage adjust mask\r
+#define SYSCTL_LDOPCTL_2_25V 0x00000005 // LDO output of 2.25V\r
+#define SYSCTL_LDOPCTL_2_30V 0x00000004 // LDO output of 2.30V\r
+#define SYSCTL_LDOPCTL_2_35V 0x00000003 // LDO output of 2.35V\r
+#define SYSCTL_LDOPCTL_2_40V 0x00000002 // LDO output of 2.40V\r
+#define SYSCTL_LDOPCTL_2_45V 0x00000001 // LDO output of 2.45V\r
+#define SYSCTL_LDOPCTL_2_50V 0x00000000 // LDO output of 2.50V\r
+#define SYSCTL_LDOPCTL_2_55V 0x0000001F // LDO output of 2.55V\r
+#define SYSCTL_LDOPCTL_2_60V 0x0000001E // LDO output of 2.60V\r
+#define SYSCTL_LDOPCTL_2_65V 0x0000001D // LDO output of 2.65V\r
+#define SYSCTL_LDOPCTL_2_70V 0x0000001C // LDO output of 2.70V\r
+#define SYSCTL_LDOPCTL_2_75V 0x0000001B // LDO output of 2.75V\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_SRCR0, SYSCTL_RCGC0,\r
+// SYSCTL_SCGC0, and SYSCTL_DCGC0 registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_SET0_WDOG 0x00000008 // Watchdog module\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_SRCR1, SYSCTL_RCGC1,\r
+// SYSCTL_SCGC1, and SYSCTL_DCGC1 registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_SET1_COMP1 0x02000000 // Analog comparator module 1\r
+#define SYSCTL_SET1_COMP0 0x01000000 // Analog comparator module 0\r
+#define SYSCTL_SET1_TIMER1 0x00020000 // Timer module 1\r
+#define SYSCTL_SET1_TIMER0 0x00010000 // Timer module 0\r
+#define SYSCTL_SET1_I2C 0x00001000 // I2C module\r
+#define SYSCTL_SET1_SSI 0x00000010 // SSI module\r
+#define SYSCTL_SET1_UART0 0x00000001 // UART module 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_SRCR2, SYSCTL_RCGC2,\r
+// SYSCTL_SCGC2, and SYSCTL_DCGC2 registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_SET2_GPIOC 0x00000004 // GPIO C module\r
+#define SYSCTL_SET2_GPIOB 0x00000002 // GPIO B module\r
+#define SYSCTL_SET2_GPIOA 0x00000001 // GIPO A module\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_RIS, SYSCTL_IMC, and\r
+// SYSCTL_IMS registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt\r
+#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt\r
+#define SYSCTL_INT_BOSC_FAIL 0x00000010 // Boot oscillator failure int\r
+#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int\r
+#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt\r
+#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt\r
+#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_RESC register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_RESC_LDO 0x00000020 // LDO power OK lost reset\r
+#define SYSCTL_RESC_SW 0x00000010 // Software reset\r
+#define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset\r
+#define SYSCTL_RESC_BOR 0x00000004 // Brown-out reset\r
+#define SYSCTL_RESC_POR 0x00000002 // Power on reset\r
+#define SYSCTL_RESC_EXT 0x00000001 // External reset\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_RCC register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_RCC_ACG 0x08000000 // Automatic clock gating\r
+#define SYSCTL_RCC_SYSDIV_MASK 0x07800000 // System clock divider\r
+#define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2\r
+#define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3\r
+#define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4\r
+#define SYSCTL_RCC_SYSDIV_5 0x02000000 // System clock /5\r
+#define SYSCTL_RCC_SYSDIV_6 0x02800000 // System clock /6\r
+#define SYSCTL_RCC_SYSDIV_7 0x03000000 // System clock /7\r
+#define SYSCTL_RCC_SYSDIV_8 0x03800000 // System clock /8\r
+#define SYSCTL_RCC_SYSDIV_9 0x04000000 // System clock /9\r
+#define SYSCTL_RCC_SYSDIV_10 0x04800000 // System clock /10\r
+#define SYSCTL_RCC_SYSDIV_11 0x05000000 // System clock /11\r
+#define SYSCTL_RCC_SYSDIV_12 0x05800000 // System clock /12\r
+#define SYSCTL_RCC_SYSDIV_13 0x06000000 // System clock /13\r
+#define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14\r
+#define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15\r
+#define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16\r
+#define SYSCTL_RCC_USE_SYSDIV 0x00400000 // Use sytem clock divider\r
+#define SYSCTL_RCC_PWRDN 0x00002000 // PLL power down\r
+#define SYSCTL_RCC_OE 0x00001000 // PLL output enable\r
+#define SYSCTL_RCC_BYPASS 0x00000800 // PLL bypass\r
+#define SYSCTL_RCC_PLLVER 0x00000400 // PLL verification timer enable\r
+#define SYSCTL_RCC_XTAL_MASK 0x000003C0 // Crystal attached to main osc\r
+#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // Using a 3.579545MHz crystal\r
+#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 // Using a 3.6864MHz crystal\r
+#define SYSCTL_RCC_XTAL_4MHz 0x00000180 // Using a 4MHz crystal\r
+#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // Using a 4.096MHz crystal\r
+#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // Using a 4.9152MHz crystal\r
+#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // Using a 5MHz crystal\r
+#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // Using a 5.12MHz crystal\r
+#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // Using a 6MHz crystal\r
+#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // Using a 6.144MHz crystal\r
+#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // Using a 7.3728MHz crystal\r
+#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // Using a 8MHz crystal\r
+#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // Using a 8.192MHz crystal\r
+#define SYSCTL_RCC_OSCSRC_MASK 0x00000030 // Oscillator input select\r
+#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // Use the main oscillator\r
+#define SYSCTL_RCC_OSCSRC_BOOT 0x00000010 // Use the boot oscillator\r
+#define SYSCTL_RCC_OSCSRC_BOOT4 0x00000020 // Use the boot oscillator / 4\r
+#define SYSCTL_RCC_BOSCVER 0x00000008 // Boot osc. verification timer en\r
+#define SYSCTL_RCC_MOSCVER 0x00000004 // Main osc. verification timer en\r
+#define SYSCTL_RCC_BOSCDIS 0x00000002 // Boot oscillator disable\r
+#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main oscillator disable\r
+#define SYSCTL_RCC_SYSDIV_SHIFT 23 // Shift to the SYSDIV field\r
+#define SYSCTL_RCC_XTAL_SHIFT 6 // Shift to the XTAL field\r
+#define SYSCTL_RCC_OSCSRC_SHIFT 4 // Shift to the OSCSRC field\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_PLLCFG register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_PLLCFG_OD_MASK 0x0000C000 // Output divider\r
+#define SYSCTL_PLLCFG_OD_1 0x00000000 // Output divider is 1\r
+#define SYSCTL_PLLCFG_OD_2 0x00004000 // Output divider is 2\r
+#define SYSCTL_PLLCFG_OD_4 0x00008000 // Output divider is 4\r
+#define SYSCTL_PLLCFG_F_MASK 0x00003FE0 // PLL multiplier\r
+#define SYSCTL_PLLCFG_R_MASK 0x0000001F // Input predivider\r
+#define SYSCTL_PLLCFG_F_SHIFT 5\r
+#define SYSCTL_PLLCFG_R_SHIFT 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_CLKVCLR register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_CLKVCLR_CLR 0x00000001 // Clear clock verification fault\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_LDOARST register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_LDOARST_ARST 0x00000001 // Allow LDO to reset device\r
+\r
+#endif // __HW_SYSCTL_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_timer.h - Defines and macros used when accessing the timer.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 523 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_TIMER_H__\r
+#define __HW_TIMER_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the timer registers.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_O_CFG 0x00000000 // Configuration register\r
+#define TIMER_O_TAMR 0x00000004 // TimerA mode register\r
+#define TIMER_O_TBMR 0x00000008 // TimerB mode register\r
+#define TIMER_O_CTL 0x0000000C // Control register\r
+#define TIMER_O_IMR 0x00000018 // Interrupt mask register\r
+#define TIMER_O_RIS 0x0000001C // Interrupt status register\r
+#define TIMER_O_MIS 0x00000020 // Masked interrupt status reg.\r
+#define TIMER_O_ICR 0x00000024 // Interrupt clear register\r
+#define TIMER_O_TAILR 0x00000028 // TimerA interval load register\r
+#define TIMER_O_TBILR 0x0000002C // TimerB interval load register\r
+#define TIMER_O_TAMATCHR 0x00000030 // TimerA match register\r
+#define TIMER_O_TBMATCHR 0x00000034 // TimerB match register\r
+#define TIMER_O_TAPR 0x00000038 // TimerA prescale register\r
+#define TIMER_O_TBPR 0x0000003C // TimerB prescale register\r
+#define TIMER_O_TAPMR 0x00000040 // TimerA prescale match register\r
+#define TIMER_O_TBPMR 0x00000044 // TimerB prescale match register\r
+#define TIMER_O_TAR 0x00000048 // TimerA register\r
+#define TIMER_O_TBR 0x0000004C // TimerB register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the reset values of the timer registers.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_RV_CFG 0x00000000 // Configuration register RV\r
+#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV\r
+#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV\r
+#define TIMER_RV_CTL 0x00000000 // Control register RV\r
+#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV\r
+#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV\r
+#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV\r
+#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV\r
+#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV\r
+#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV\r
+#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV\r
+#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV\r
+#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV\r
+#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV\r
+#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV\r
+#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV\r
+#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV\r
+#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_CFG register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask\r
+#define TIMER_CFG_16_BIT 0x00000004 // Two 16 bit timers\r
+#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32 bit RTC\r
+#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32 bit timer\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_TnMR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select\r
+#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time\r
+#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask\r
+#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture\r
+#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic\r
+#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_CTL register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_CTL_TBPWML 0x00004000 // TimerB PWM output level invert\r
+#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask\r
+#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // TimerB event mode - both edges\r
+#define TIMER_CTL_TBEVENT_NEG 0x00000400 // TimerB event mode - neg edge\r
+#define TIMER_CTL_TBEVENT_POS 0x00000000 // TimerB event mode - pos edge\r
+#define TIMER_CTL_TBSTALL 0x00000200 // TimerB stall enable\r
+#define TIMER_CTL_TBEN 0x00000100 // TimerB enable\r
+#define TIMER_CTL_TAPWML 0x00000040 // TimerA PWM output level invert\r
+#define TIMER_CTL_RTCEN 0x00000010 // RTC counter enable\r
+#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask\r
+#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // TimerA event mode - both edges\r
+#define TIMER_CTL_TAEVENT_NEG 0x00000004 // TimerA event mode - neg edge\r
+#define TIMER_CTL_TAEVENT_POS 0x00000000 // TimerA event mode - pos edge\r
+#define TIMER_CTL_TASTALL 0x00000002 // TimerA stall enable\r
+#define TIMER_CTL_TAEN 0x00000001 // TimerA enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_IMR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_IMR_CBEIM 0x00000400 // CaptureB event interrupt mask\r
+#define TIMER_IMR_CBMIM 0x00000200 // CaptureB match interrupt mask\r
+#define TIMER_IMR_TBTOIM 0x00000100 // TimerB time out interrupt mask\r
+#define TIMER_IMR_RTCIM 0x00000008 // RTC interrupt mask\r
+#define TIMER_IMR_CAEIM 0x00000004 // CaptureA event interrupt mask\r
+#define TIMER_IMR_CAMIM 0x00000002 // CaptureA match interrupt mask\r
+#define TIMER_IMR_TATOIM 0x00000001 // TimerA time out interrupt mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_RIS register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_RIS_CBERIS 0x00000400 // CaptureB event raw int status\r
+#define TIMER_RIS_CBMRIS 0x00000200 // CaptureB match raw int status\r
+#define TIMER_RIS_TBTORIS 0x00000100 // TimerB time out raw int status\r
+#define TIMER_RIS_RTCRIS 0x00000008 // RTC raw int status\r
+#define TIMER_RIS_CAERIS 0x00000004 // CaptureA event raw int status\r
+#define TIMER_RIS_CAMRIS 0x00000002 // CaptureA match raw int status\r
+#define TIMER_RIS_TATORIS 0x00000001 // TimerA time out raw int status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_MIS register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status\r
+#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status\r
+#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat\r
+#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status\r
+#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status\r
+#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status\r
+#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_ICR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_ICR_CBECINT 0x00000400 // CaptureB event interrupt clear\r
+#define TIMER_ICR_CBMCINT 0x00000200 // CaptureB match interrupt clear\r
+#define TIMER_ICR_TBTOCINT 0x00000100 // TimerB time out interrupt clear\r
+#define TIMER_ICR_RTCCINT 0x00000008 // RTC interrupt clear\r
+#define TIMER_ICR_CAECINT 0x00000004 // CaptureA event interrupt clear\r
+#define TIMER_ICR_CAMCINT 0x00000002 // CaptureA match interrupt clear\r
+#define TIMER_ICR_TATOCINT 0x00000001 // TimerA time out interrupt clear\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_TAILR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode\r
+#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the bit fields in the TIMER_TBILR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_TAMATCHR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode\r
+#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the bit fields in the TIMER_TBMATCHR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the bit fields in the TIMER_TnPR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TNPR_TNPSR 0x0000000F // TimerN prescale value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the bit fields in the TIMER_TnPMR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TNPMR_TNPSMR 0x0000000F // TimerN prescale match value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_TAR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode\r
+#define TIMER_TAR_TARL 0x0000FFFF // TimerA value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the bit fields in the TIMER_TBR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value\r
+\r
+#endif // __HW_TIMER_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_types.h - Common types and macros.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 523 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_TYPES_H__\r
+#define __HW_TYPES_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// Define a boolean type, and values for true and false.\r
+//\r
+//*****************************************************************************\r
+typedef unsigned char tBoolean;\r
+\r
+#ifndef true\r
+#define true 1\r
+#endif\r
+\r
+#ifndef false\r
+#define false 0\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Macros for hardware access, both direct and via the bit-band region.\r
+//\r
+//*****************************************************************************\r
+#define HWREG(x) \\r
+ (*((volatile unsigned long *)(x)))\r
+#define HWREGBITW(x, b) \\r
+ HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \\r
+ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))\r
+#define HWREGBITH(x, b) \\r
+ HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \\r
+ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))\r
+#define HWREGBITB(x, b) \\r
+ HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \\r
+ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))\r
+\r
+#endif // __HW_TYPES_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_uart.h - Macros and defines used when accessing the UART hardware\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 523 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_UART_H__\r
+#define __HW_UART_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// UART Register Offsets.\r
+//\r
+//*****************************************************************************\r
+#define UART_O_DR 0x00000000 // Data Register\r
+#define UART_O_RSR 0x00000004 // Receive Status Register (read)\r
+#define UART_O_ECR 0x00000004 // Error Clear Register (write)\r
+#define UART_O_FR 0x00000018 // Flag Register (read only)\r
+#define UART_O_IBRD 0x00000024 // Integer Baud Rate Divisor Reg\r
+#define UART_O_FBRD 0x00000028 // Fractional Baud Rate Divisor Reg\r
+#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte\r
+#define UART_O_CTL 0x00000030 // Control Register\r
+#define UART_O_IFLS 0x00000034 // Interrupt FIFO Level Select Reg\r
+#define UART_O_IM 0x00000038 // Interrupt Mask Set/Clear Reg\r
+#define UART_O_RIS 0x0000003C // Raw Interrupt Status Register\r
+#define UART_O_MIS 0x00000040 // Masked Interrupt Status Register\r
+#define UART_O_ICR 0x00000044 // Interrupt Clear Register\r
+\r
+//*****************************************************************************\r
+//\r
+// Data Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_DR_OE 0x00000800 // Overrun Error\r
+#define UART_DR_BE 0x00000400 // Break Error\r
+#define UART_DR_PE 0x00000200 // Parity Error\r
+#define UART_DR_FE 0x00000100 // Framing Error\r
+\r
+//*****************************************************************************\r
+//\r
+// Receive Status Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_RSR_OE 0x00000008 // Overrun Error\r
+#define UART_RSR_BE 0x00000004 // Break Error\r
+#define UART_RSR_PE 0x00000002 // Parity Error\r
+#define UART_RSR_FE 0x00000001 // Framing Error\r
+\r
+//*****************************************************************************\r
+//\r
+// Flag Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_FR_RI 0x100 // Ring Indicator\r
+#define UART_FR_TXFE 0x080 // TX FIFO Empty\r
+#define UART_FR_RXFF 0x040 // RX FIFO Full\r
+#define UART_FR_TXFF 0x020 // TX FIFO Full\r
+#define UART_FR_RXFE 0x010 // RX FIFO Empty\r
+#define UART_FR_BUSY 0x008 // UART Busy\r
+\r
+//*****************************************************************************\r
+//\r
+// Line Control Register High bits\r
+//\r
+//*****************************************************************************\r
+#define UART_LCR_H_SPS 0x80 // Stick Parity Select\r
+#define UART_LCR_H_WLEN 0x60 // Word length\r
+#define UART_LCR_H_WLEN_8 0x60 // 8 bit data\r
+#define UART_LCR_H_WLEN_7 0x40 // 7 bit data\r
+#define UART_LCR_H_WLEN_6 0x20 // 6 bit data\r
+#define UART_LCR_H_WLEN_5 0x00 // 5 bit data\r
+#define UART_LCR_H_FEN 0x10 // Enable FIFO\r
+#define UART_LCR_H_STP2 0x08 // Two Stop Bits Select\r
+#define UART_LCR_H_EPS 0x04 // Even Parity Select\r
+#define UART_LCR_H_PEN 0x02 // Parity Enable\r
+#define UART_LCR_H_BRK 0x01 // Send Break\r
+\r
+//*****************************************************************************\r
+//\r
+// Control Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_CTL_CTSEN 0x8000 // CTS Hardware Flow Control\r
+#define UART_CTL_RTSEN 0x4000 // RTS Hardware Flow Control\r
+#define UART_CTL_OUT2 0x2000 // OUT2\r
+#define UART_CTL_OUT1 0x1000 // OUT1\r
+#define UART_CTL_RTS 0x0800 // Request To Send\r
+#define UART_CTL_DTR 0x0400 // Data Terminal Ready\r
+#define UART_CTL_RXE 0x0200 // Receive Enable\r
+#define UART_CTL_TXE 0x0100 // Transmit Enable\r
+#define UART_CTL_LBE 0x0080 // Loopback Enable\r
+#define UART_CTL_IIRLP 0x0004 // IrDA SIR low power mode\r
+#define UART_CTL_SIREN 0x0002 // SIR Enable\r
+#define UART_CTL_UARTEN 0x0001 // UART Enable\r
+\r
+//*****************************************************************************\r
+//\r
+// Interrupt FIFO Level Select Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_IFLS_RX1_8 0x00 // 1/8 Full\r
+#define UART_IFLS_RX2_8 0x10 // 1/4 Full\r
+#define UART_IFLS_RX4_8 0x20 // 1/2 Full\r
+#define UART_IFLS_RX6_8 0x30 // 3/4 Full\r
+#define UART_IFLS_RX7_8 0x40 // 7/8 Full\r
+#define UART_IFLS_TX1_8 0x00 // 1/8 Full\r
+#define UART_IFLS_TX2_8 0x01 // 1/4 Full\r
+#define UART_IFLS_TX4_8 0x02 // 1/2 Full\r
+#define UART_IFLS_TX6_8 0x03 // 3/4 Full\r
+#define UART_IFLS_TX7_8 0x04 // 7/8 Full\r
+\r
+//*****************************************************************************\r
+//\r
+// Interrupt Mask Set/Clear Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_IM_OEIM 0x400 // Overrun Error Interrupt Mask\r
+#define UART_IM_BEIM 0x200 // Break Error Interrupt Mask\r
+#define UART_IM_PEIM 0x100 // Parity Error Interrupt Mask\r
+#define UART_IM_FEIM 0x080 // Framing Error Interrupt Mask\r
+#define UART_IM_RTIM 0x040 // Receive Timeout Interrupt Mask\r
+#define UART_IM_TXIM 0x020 // Transmit Interrupt Mask\r
+#define UART_IM_RXIM 0x010 // Receive Interrupt Mask\r
+#define UART_IM_DSRMIM 0x008 // DSR Interrupt Mask\r
+#define UART_IM_DCDMIM 0x004 // DCD Interrupt Mask\r
+#define UART_IM_CTSMIM 0x002 // CTS Interrupt Mask\r
+#define UART_IM_RIMIM 0x001 // RI Interrupt Mask\r
+\r
+//*****************************************************************************\r
+//\r
+// Raw Interrupt Status Register\r
+//\r
+//*****************************************************************************\r
+#define UART_RIS_OERIS 0x400 // Overrun Error Interrupt Status\r
+#define UART_RIS_BERIS 0x200 // Break Error Interrupt Status\r
+#define UART_RIS_PERIS 0x100 // Parity Error Interrupt Status\r
+#define UART_RIS_FERIS 0x080 // Framing Error Interrupt Status\r
+#define UART_RIS_RTRIS 0x040 // Receive Timeout Interrupt Status\r
+#define UART_RIS_TXRIS 0x020 // Transmit Interrupt Status\r
+#define UART_RIS_RXRIS 0x010 // Receive Interrupt Status\r
+#define UART_RIS_DSRRMIS 0x008 // DSR Interrupt Status\r
+#define UART_RIS_DCDRMIS 0x004 // DCD Interrupt Status\r
+#define UART_RIS_CTSRMIS 0x002 // CTS Interrupt Status\r
+#define UART_RIS_RIRMIS 0x001 // RI Interrupt Status\r
+\r
+//*****************************************************************************\r
+//\r
+// Masked Interrupt Status Register\r
+//\r
+//*****************************************************************************\r
+#define UART_MIS_OEMIS 0x400 // Overrun Error Interrupt Status\r
+#define UART_MIS_BEMIS 0x200 // Break Error Interrupt Status\r
+#define UART_MIS_PEMIS 0x100 // Parity Error Interrupt Status\r
+#define UART_MIS_FEMIS 0x080 // Framing Error Interrupt Status\r
+#define UART_MIS_RTMIS 0x040 // Receive Timeout Interrupt Status\r
+#define UART_MIS_TXMIS 0x020 // Transmit Interrupt Status\r
+#define UART_MIS_RXMIS 0x010 // Receive Interrupt Status\r
+#define UART_MIS_DSRMMIS 0x008 // DSR Interrupt Status\r
+#define UART_MIS_DCDMMIS 0x004 // DCD Interrupt Status\r
+#define UART_MIS_CTSMMIS 0x002 // CTS Interrupt Status\r
+#define UART_MIS_RIMMIS 0x001 // RI Interrupt Status\r
+\r
+//*****************************************************************************\r
+//\r
+// Interrupt Clear Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_ICR_OEIC 0x200 // Overrun Error Interrupt Clear\r
+#define UART_ICR_BEIC 0x200 // Break Error Interrupt Clear\r
+#define UART_ICR_PEIC 0x200 // Parity Error Interrupt Clear\r
+#define UART_ICR_FEIC 0x200 // Framing Error Interrupt Clear\r
+#define UART_ICR_RTIC 0x200 // Receive Timeout Interrupt Clear\r
+#define UART_ICR_TXIC 0x200 // Transmit Interrupt Clear\r
+#define UART_ICR_RXIC 0x200 // Receive Interrupt Clear\r
+#define UART_ICR_DSRMIC 0x200 // DSR Interrupt Clear\r
+#define UART_ICR_DCDMIC 0x200 // DCD Interrupt Clear\r
+#define UART_ICR_CTSMIC 0x200 // CTS Interrupt Clear\r
+#define UART_ICR_RIMIC 0x200 // RI Interrupt Clear\r
+\r
+//*****************************************************************************\r
+//\r
+// DMA Control Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_DMACRDMAONERR 0x04 // Disable DMA On Error\r
+#define UART_DMACRTXDMAE 0x02 // Enable Transmit DMA\r
+#define UART_DMACRRXDMAE 0x01 // Enable Receive DMA\r
+\r
+#define UART_RSR_ANY (UART_RSR_OE | \\r
+ UART_RSR_BE | \\r
+ UART_RSR_PE | \\r
+ UART_RSR_FE)\r
+\r
+//*****************************************************************************\r
+//\r
+// Reset Values for UART Registers.\r
+//\r
+//*****************************************************************************\r
+#define UART_RV_DR 0\r
+#define UART_RV_RSR 0x0\r
+#define UART_RV_ECR 0\r
+#define UART_RV_FR 0x90\r
+#define UART_RV_IBRD 0x0000\r
+#define UART_RV_FBRD 0x00\r
+#define UART_RV_LCR_H 0x00\r
+#define UART_RV_CTL 0x0300\r
+#define UART_RV_IFLS 0x12\r
+#define UART_RV_IM 0x000\r
+#define UART_RV_RIS 0x000\r
+#define UART_RV_MIS 0x000\r
+#define UART_RV_ICR 0x000\r
+\r
+#endif // __HW_UART_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 523 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_WATCHDOG_H__\r
+#define __HW_WATCHDOG_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the Watchdog Timer registers.\r
+//\r
+//*****************************************************************************\r
+#define WDT_O_LOAD 0x00000000 // Load register\r
+#define WDT_O_VALUE 0x00000004 // Current value register\r
+#define WDT_O_CTL 0x00000008 // Control register\r
+#define WDT_O_ICR 0x0000000C // Interrupt clear register\r
+#define WDT_O_RIS 0x00000010 // Raw interrupt status register\r
+#define WDT_O_MIS 0x00000014 // Masked interrupt status register\r
+#define WDT_O_TEST 0x00000418 // Test register\r
+#define WDT_O_CAUSE 0x0000041C // Cause register\r
+#define WDT_O_LOCK 0x00000C00 // Lock register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the WDT_CTL register.\r
+//\r
+//*****************************************************************************\r
+#define WDT_CTL_RESEN 0x00000002 // Enable reset output\r
+#define WDT_CTL_INTEN 0x00000001 // Enable the WDT counter and int\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the WDT_ISR, WDT_RIS, and WDT_MIS\r
+// registers.\r
+//\r
+//*****************************************************************************\r
+#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the WDT_TEST register.\r
+//\r
+//*****************************************************************************\r
+#define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable\r
+#define WDT_TEST_TEST_EN 0x00000001 // Watchdog timer reset int test\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the WDT_CAUSE register.\r
+//\r
+//*****************************************************************************\r
+#define WDT_CAUSE_WDR 0x00000002 // Watchdog timer reset occurred\r
+#define WDT_CAUSE_WDI 0x00000001 // Watchdog timer int occurred\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the WDT_LOCK register.\r
+//\r
+//*****************************************************************************\r
+#define WDT_LOCK_LOCKED 0x00000001 // Watchdog timer is locked\r
+#define WDT_LOCK_UNLOCKED 0x00000000 // Watchdog timer is unlocked\r
+#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the reset values for the WDT registers.\r
+//\r
+//*****************************************************************************\r
+#define WDT_RV_LOAD 0xFFFFFFFF // Load register\r
+#define WDT_RV_VALUE 0xFFFFFFFF // Current value register\r
+#define WDT_RV_CTL 0x00000000 // Control register\r
+#define WDT_RV_RIS 0x00000000 // Raw interrupt status register\r
+#define WDT_RV_MIS 0x00000000 // Masked interrupt status register\r
+#define WDT_RV_LOCK 0x00000000 // Lock register\r
+\r
+#endif // __HW_WATCHDOG_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// i2c.h - Prototypes for the I2C Driver.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 523 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __I2C_H__\r
+#define __I2C_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Defines for the API.\r
+//\r
+//*****************************************************************************\r
+//*****************************************************************************\r
+//\r
+// Interrupt defines.\r
+//\r
+//*****************************************************************************\r
+#define I2C_INT_MASTER 0x00000001\r
+#define I2C_INT_SLAVE 0x00000002\r
+\r
+//*****************************************************************************\r
+//\r
+// I2C Master commands.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_CMD_SINGLE_SEND \\r
+ (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_SINGLE_RECEIVE \\r
+ (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_SEND_START \\r
+ (I2C_MASTER_CS_START | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_SEND_CONT \\r
+ (I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_SEND_FINISH \\r
+ (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \\r
+ (I2C_MASTER_CS_STOP)\r
+#define I2C_MASTER_CMD_BURST_RECEIVE_START \\r
+ (I2C_MASTER_CS_ACK | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \\r
+ (I2C_MASTER_CS_ACK | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \\r
+ (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \\r
+ (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN)\r
+\r
+//*****************************************************************************\r
+//\r
+// I2C Master error status.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_ERR_NONE 0\r
+#define I2C_MASTER_ERR_ADDR_ACK 0x00000004\r
+#define I2C_MASTER_ERR_DATA_ACK 0x00000008\r
+#define I2C_MASTER_ERR_ARB_LOST 0x00000010\r
+\r
+//*****************************************************************************\r
+//\r
+// I2C Slave action requests\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_ACT_NONE 0\r
+#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data\r
+#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data\r
+\r
+//*****************************************************************************\r
+// Miscellaneous I2C driver definitions.\r
+//*****************************************************************************\r
+#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void I2CIntRegister(unsigned long ulBase, void(fnHandler)(void));\r
+extern void I2CIntUnregister(unsigned long ulBase);\r
+extern tBoolean I2CMasterBusBusy(unsigned long ulBase);\r
+extern tBoolean I2CMasterBusy(unsigned long ulBase);\r
+extern void I2CMasterControl(unsigned long ulBase, unsigned long ulCmd);\r
+extern unsigned long I2CMasterDataGet(unsigned long ulBase);\r
+extern void I2CMasterDataPut(unsigned long ulBase, unsigned char ucData);\r
+extern void I2CMasterDisable(unsigned long ulBase);\r
+extern void I2CMasterEnable(unsigned long ulBase);\r
+extern unsigned long I2CMasterErr(unsigned long ulBase);\r
+extern void I2CMasterInit(unsigned long ulBase, tBoolean bFast);\r
+extern void I2CMasterIntClear(unsigned long ulBase);\r
+extern void I2CMasterIntDisable(unsigned long ulBase);\r
+extern void I2CMasterIntEnable(unsigned long ulBase);\r
+extern tBoolean I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void I2CMasterSlaveAddrSet(unsigned long ulBase,\r
+ unsigned char ucSlaveAddr,\r
+ tBoolean bReceive);\r
+extern unsigned long I2CSlaveDataGet(unsigned long ulBase);\r
+extern void I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData);\r
+extern void I2CSlaveDisable(unsigned long ulBase);\r
+extern void I2CSlaveEnable(unsigned long ulBase);\r
+extern void I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr);\r
+extern void I2CSlaveIntClear(unsigned long ulBase);\r
+extern void I2CSlaveIntDisable(unsigned long ulBase);\r
+extern void I2CSlaveIntEnable(unsigned long ulBase);\r
+extern tBoolean I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern unsigned long I2CSlaveStatus(unsigned long ulBase);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __I2C_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 523 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __INTERRUPT_H__\r
+#define __INTERRUPT_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void IntMasterEnable(void);\r
+extern void IntMasterDisable(void);\r
+extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void));\r
+extern void IntUnregister(unsigned long ulInterrupt);\r
+extern void IntPriorityGroupingSet(unsigned long ulBits);\r
+extern unsigned long IntPriorityGroupingGet(void);\r
+extern void IntPrioritySet(unsigned long ulInterrupt,\r
+ unsigned char ucPriority);\r
+extern long IntPriorityGet(unsigned long ulInterrupt);\r
+extern void IntEnable(unsigned long ulInterrupt);\r
+extern void IntDisable(unsigned long ulInterrupt);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __INTERRUPT_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// pdc.c - Driver for the Peripheral Device Controller (PDC) on the Stellaris\r
+// development board.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 523 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup utilities_api\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+#include "hw_memmap.h"\r
+#include "hw_types.h"\r
+#include "gpio.h"\r
+#include "ssi.h"\r
+#include "sysctl.h"\r
+#include "pdc.h"\r
+\r
+//*****************************************************************************\r
+//\r
+//! Initializes the connection to the PDC.\r
+//!\r
+//! This function will enable clocking to the SSI and GPIO A modules, configure\r
+//! the GPIO pins to be used for an SSI interface, and it will configure the\r
+//! SSI as a 1Mb master device, operating in MOTO mode. It will also enable\r
+//! the SSI module, and will enable the chip select for the PDC on the\r
+//! Stellaris development board.\r
+//!\r
+//! This function is contained in <tt>utils/pdc.c</tt>, with\r
+//! <tt>utils/pdc.h</tt> containing the API definition for use by applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+PDCInit(void)\r
+{\r
+ //\r
+ // Enable the peripherals used to drive the PDC.\r
+ //\r
+ SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI);\r
+ SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);\r
+\r
+ //\r
+ // Configure the appropriate pins to be SSI instead of GPIO.\r
+ //\r
+ GPIODirModeSet(GPIO_PORTA_BASE, SSI_CLK | SSI_TX | SSI_RX,\r
+ GPIO_DIR_MODE_HW);\r
+ GPIODirModeSet(GPIO_PORTA_BASE, SSI_CS, GPIO_DIR_MODE_OUT);\r
+ GPIOPadConfigSet(GPIO_PORTA_BASE, SSI_CLK, GPIO_STRENGTH_4MA,\r
+ GPIO_PIN_TYPE_STD_WPU);\r
+\r
+ //\r
+ // Configure the SSI port.\r
+ //\r
+ SSIConfig(SSI_BASE, SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 1000000, 8);\r
+ SSIEnable(SSI_BASE);\r
+\r
+ //\r
+ // Reset the PDC SSI state machine. The chip select needs to be held low\r
+ // for 100ns; the procedure call overhead more than accounts for this time.\r
+ //\r
+ GPIOPinWrite(GPIO_PORTA_BASE, PDC_CS, 0);\r
+ GPIOPinWrite(GPIO_PORTA_BASE, PDC_CS, PDC_CS);\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Write a PDC register.\r
+//!\r
+//! \param ucAddr specifies the PDC register to write.\r
+//! \param ucData specifies the data to write.\r
+//!\r
+//! This function will perform the SSI transfers required to write a register\r
+//! in the PDC on the Stellaris development board.\r
+//!\r
+//! This function is contained in <tt>utils/pdc.c</tt>, with\r
+//! <tt>utils/pdc.h</tt> containing the API definition for use by applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+PDCWrite(unsigned char ucAddr, unsigned char ucData)\r
+{\r
+ unsigned long ulTemp;\r
+\r
+ //\r
+ // Send address and write command.\r
+ //\r
+ SSIDataPut(SSI_BASE, (ucAddr & 0x0F) | PDC_WR);\r
+\r
+ //\r
+ // Write the data.\r
+ //\r
+ SSIDataPut(SSI_BASE, ucData);\r
+\r
+ //\r
+ // Flush data read during address write.\r
+ //\r
+ SSIDataGet(SSI_BASE, &ulTemp);\r
+\r
+ //\r
+ // Flush data read during data write.\r
+ //\r
+ SSIDataGet(SSI_BASE, &ulTemp);\r
+}\r
+\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// pdc.h - Stellaris development board Peripheral Device Controller definitions\r
+// and prototypes.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 523 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __PDC_H__\r
+#define __PDC_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// The registers within the peripheral device controller.\r
+//\r
+//*****************************************************************************\r
+#define PDC_VER 0x0 // Version register\r
+#define PDC_CSR 0x1 // Command/Status register\r
+#define PDC_DSW 0x4 // DIP Switch register\r
+#define PDC_LED 0x5 // LED register\r
+#define PDC_LCD_CSR 0x6 // LCD Command/Status register\r
+#define PDC_LCD_RAM 0x7 // LCD RAM register\r
+#define PDC_GPXDAT 0x8 // GPIO X Data register\r
+#define PDC_GPXDIR 0x9 // GPIO X Direction register\r
+#define PDC_GPYDAT 0xA // GPIO Y Data register\r
+#define PDC_GPYDIR 0xB // GPIO Y Direction register\r
+#define PDC_GPZDAT 0xC // GPIO Z Data register\r
+#define PDC_GPZDIR 0xD // GPIO Z Direction register\r
+\r
+//*****************************************************************************\r
+//\r
+// Flags indicating a read or write to the peripheral device controller.\r
+//\r
+//*****************************************************************************\r
+#define PDC_RD 0x80 // PDC read command\r
+#define PDC_WR 0x00 // PDC write command\r
+\r
+//*****************************************************************************\r
+//\r
+// LCD panel (Crystalfontz CFAH1602B) commands, RS = 0\r
+//\r
+//*****************************************************************************\r
+#define LCD_CLEAR 0x01 // Clear display (0 fill DDRAM).\r
+#define LCD_HOME 0x02 // Cursor home.\r
+#define LCD_MODE 0x04 // Set entry mode (cursor dir)\r
+#define LCD_ON 0x08 // Set display, cursor, blinking\r
+ // on/off\r
+#define LCD_CUR 0x10 // Cursor, display shift\r
+#define LCD_IF 0x20 // Set interface data length,\r
+ // lines, font\r
+#define LCD_CGADDR 0x40 // Set CGRAM AC address\r
+#define LCD_DDADDR 0x80 // Set DDRAM AC address\r
+\r
+//*****************************************************************************\r
+//\r
+// LCD Status bit\r
+//\r
+//*****************************************************************************\r
+#define LCD_B_BUSY 0x80 // Busy flag.\r
+\r
+//*****************************************************************************\r
+//\r
+// The GPIO port A pin numbers for the various SSI signals.\r
+//\r
+//*****************************************************************************\r
+#define SSI_CS GPIO_PIN_3\r
+#define PDC_CS GPIO_PIN_3\r
+#define SSI_CLK GPIO_PIN_2\r
+#define SSI_TX GPIO_PIN_5\r
+#define SSI_RX GPIO_PIN_4\r
+\r
+//*****************************************************************************\r
+//\r
+// Function Prototypes\r
+//\r
+//*****************************************************************************\r
+extern void PDCInit(void);\r
+extern unsigned char PDCRead(unsigned char ucAddr);\r
+extern void PDCWrite(unsigned char ucAddr, unsigned char ucData);\r
+extern unsigned char PDCDIPRead(void);\r
+extern void PDCLEDWrite(unsigned char ucLED);\r
+extern unsigned char PDCLEDRead(void);\r
+extern void PDCLCDInit(void);\r
+extern void PDCLCDBacklightOn(void);\r
+extern void PDCLCDBacklightOff(void);\r
+extern void PDCLCDClear(void);\r
+extern void PDCLCDCreateChar(unsigned char ucChar, unsigned char *pucData);\r
+extern void PDCLCDSetPos(unsigned char ucX, unsigned char ucY);\r
+extern void PDCLCDWrite(const char *pcStr, unsigned long ulCount);\r
+extern unsigned char PDCGPIODirRead(unsigned char ucIdx);\r
+extern void PDCGPIODirWrite(unsigned char ucIdx, unsigned char ucValue);\r
+extern unsigned char PDCGPIORead(unsigned char ucIdx);\r
+extern void PDCGPIOWrite(unsigned char ucIdx, unsigned char ucValue);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __PDC_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// ssi.h - Prototypes for the Synchronous Serial Interface Driver.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 523 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __SSI_H__\r
+#define __SSI_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear\r
+// as the ulIntFlags parameter, and returned by SSIIntStatus.\r
+//\r
+//*****************************************************************************\r
+#define SSI_TXFF 0x00000008 // TX FIFO half empty or less\r
+#define SSI_RXFF 0x00000004 // RX FIFO half full or less\r
+#define SSI_RXTO 0x00000002 // RX timeout\r
+#define SSI_RXOR 0x00000001 // RX overrun\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to SSIConfig.\r
+//\r
+//*****************************************************************************\r
+#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0\r
+#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1\r
+#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0\r
+#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1\r
+#define SSI_FRF_TI 0x00000010 // TI frame format\r
+#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format\r
+\r
+#define SSI_MODE_MASTER 0x00000000 // SSI master\r
+#define SSI_MODE_SLAVE 0x00000001 // SSI slave\r
+#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void SSIConfig(unsigned long ulBase, unsigned long ulProtocol,\r
+ unsigned long ulMode, unsigned long ulBitRate,\r
+ unsigned long ulDataWidth);\r
+extern void SSIDataGet(unsigned long ulBase, unsigned long *ulData);\r
+extern long SSIDataNonBlockingGet(unsigned long ulBase, unsigned long *ulData);\r
+extern void SSIDataPut(unsigned long ulBase, unsigned long ulData);\r
+extern long SSIDataNonBlockingPut(unsigned long ulBase, unsigned long ulData);\r
+extern void SSIDisable(unsigned long ulBase);\r
+extern void SSIEnable(unsigned long ulBase);\r
+extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void));\r
+extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void SSIIntUnregister(unsigned long ulBase);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __SSI_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// sysctl.h - Prototypes for the system control driver.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 523 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __SYSCTL_H__\r
+#define __SYSCTL_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the\r
+// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(),\r
+// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the\r
+// ulPeripheral parameter. The peripherals in the fourth group (upper nibble\r
+// is 3) can only be used with the SysCtlPeripheralPresent() API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog\r
+#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0\r
+#define SYSCTL_PERIPH_SSI 0x10000010 // SSI\r
+#define SYSCTL_PERIPH_I2C 0x10001000 // I2C\r
+#define SYSCTL_PERIPH_TIMER0 0x10010000 // Timer 0\r
+#define SYSCTL_PERIPH_TIMER1 0x10020000 // Timer 1\r
+#define SYSCTL_PERIPH_COMP0 0x11000000 // Analog comparator 0\r
+#define SYSCTL_PERIPH_COMP1 0x12000000 // Analog comparator 1\r
+#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A\r
+#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B\r
+#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C\r
+#define SYSCTL_PERIPH_PLL 0x30000010 // PLL\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlPinPresent() API\r
+// as the ulPin parameter.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin\r
+#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin\r
+#define SYSCTL_PIN_C0O 0x00000100 // C0o pin\r
+#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin\r
+#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin\r
+#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin\r
+#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlLDOSet() API as\r
+// the ulVoltage value, or returned by the SysCtlLDOGet() API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V\r
+#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V\r
+#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V\r
+#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V\r
+#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V\r
+#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V\r
+#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V\r
+#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V\r
+#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V\r
+#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V\r
+#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlLDOConfigSet() API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset\r
+#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlIntEnable(),\r
+// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask\r
+// by the SysCtlIntStatus() API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt\r
+#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt\r
+#define SYSCTL_INT_BOSC_FAIL 0x00000010 // Boot oscillator failure int\r
+#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int\r
+#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt\r
+#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt\r
+#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlResetCauseClear()\r
+// API or returned by the SysCtlResetCauseGet() API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset\r
+#define SYSCTL_CAUSE_SW 0x00000010 // Software reset\r
+#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset\r
+#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset\r
+#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset\r
+#define SYSCTL_CAUSE_EXT 0x00000001 // External reset\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlBrownOutConfigSet()\r
+// API as the ulConfig parameter.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting\r
+#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlClockSet() API as\r
+// the ulConfig parameter.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1\r
+#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2\r
+#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3\r
+#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4\r
+#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5\r
+#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6\r
+#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7\r
+#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8\r
+#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9\r
+#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10\r
+#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11\r
+#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12\r
+#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13\r
+#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14\r
+#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15\r
+#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16\r
+#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock\r
+#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock\r
+#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz\r
+#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz\r
+#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz\r
+#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz\r
+#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz\r
+#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz\r
+#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz\r
+#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz\r
+#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz\r
+#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz\r
+#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz\r
+#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz\r
+#define SYSCTL_OSC_MAIN 0x00000000 // Oscillator source is main osc\r
+#define SYSCTL_OSC_BOOT 0x00000010 // Oscillator source is boot osc\r
+#define SYSCTL_OSC_BOOT4 0x00000020 // Oscillator source is boot osc /4\r
+#define SYSCTL_BOOT_OSC_DIS 0x00000002 // Disable boot oscillator\r
+#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern unsigned long SysCtlSRAMSizeGet(void);\r
+extern unsigned long SysCtlFlashSizeGet(void);\r
+extern tBoolean SysCtlPinPresent(unsigned long ulPin);\r
+extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralReset(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralEnable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralDisable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralClockGating(tBoolean bEnable);\r
+extern void SysCtlIntRegister(void (*pfnHandler)(void));\r
+extern void SysCtlIntUnregister(void);\r
+extern void SysCtlIntEnable(unsigned long ulInts);\r
+extern void SysCtlIntDisable(unsigned long ulInts);\r
+extern void SysCtlIntClear(unsigned long ulInts);\r
+extern unsigned long SysCtlIntStatus(tBoolean bMasked);\r
+extern void SysCtlLDOSet(unsigned long ulVoltage);\r
+extern unsigned long SysCtlLDOGet(void);\r
+extern void SysCtlLDOConfigSet(unsigned long ulConfig);\r
+extern void SysCtlReset(void);\r
+extern void SysCtlSleep(void);\r
+extern void SysCtlDeepSleep(void);\r
+extern unsigned long SysCtlResetCauseGet(void);\r
+extern void SysCtlResetCauseClear(unsigned long ulCauses);\r
+extern void SysCtlBrownOutConfigSet(unsigned long ulConfig,\r
+ unsigned long ulDelay);\r
+extern void SysCtlClockSet(unsigned long ulConfig);\r
+extern unsigned long SysCtlClockGet(void);\r
+extern void SysCtlBOSCVerificationSet(tBoolean bEnable);\r
+extern void SysCtlMOSCVerificationSet(tBoolean bEnable);\r
+extern void SysCtlPLLVerificationSet(tBoolean bEnable);\r
+extern void SysCtlClkVerificationClear(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __SYSCTL_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// systick.h - Prototypes for the SysTick driver.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 523 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __SYSTICK_H__\r
+#define __SYSTICK_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void SysTickEnable(void);\r
+extern void SysTickDisable(void);\r
+extern void SysTickIntRegister(void (*pfnHandler)(void));\r
+extern void SysTickIntUnregister(void);\r
+extern void SysTickPeriodSet(unsigned long ulPeriod);\r
+extern unsigned long SysTickPeriodGet(void);\r
+extern unsigned long SysTickValueGet(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __SYSTICK_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// timer.h - Prototypes for the timer module\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 523 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __TIMER_H__\r
+#define __TIMER_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to TimerConfigure as the ulConfig parameter.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer\r
+#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer\r
+#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer\r
+#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers\r
+#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer\r
+#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer\r
+#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter\r
+#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer\r
+#define TIMER_CFG_A_PWM 0x0000000F // Timer A PWM output\r
+#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer\r
+#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer\r
+#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter\r
+#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer\r
+#define TIMER_CFG_B_PWM 0x00000F00 // Timer B PWM output\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to TimerIntEnable, TimerIntDisable, and\r
+// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt\r
+#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt\r
+#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt\r
+#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask\r
+#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt\r
+#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt\r
+#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerB time out interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to TimerControlEvent as the ulEvent parameter.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges\r
+#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges\r
+#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to most of the timer APIs as the ulTimer\r
+// parameter.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_A 0x000000ff // Timer A\r
+#define TIMER_B 0x0000ff00 // Timer B\r
+#define TIMER_BOTH 0x0000ffff // Timer Both\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer);\r
+extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer);\r
+extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig);\r
+extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer,\r
+ tBoolean bInvert);\r
+extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer,\r
+ tBoolean bEnable);\r
+extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulEvent);\r
+extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer,\r
+ tBoolean bStall);\r
+extern void TimerRTCEnable(unsigned long ulBase);\r
+extern void TimerRTCDisable(unsigned long ulBase);\r
+extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerPrescaleGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer);\r
+extern unsigned long TimerValueGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerMatchGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer,\r
+ void (*pfnHandler)(void));\r
+extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer);\r
+extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void TimerQuiesce(unsigned long ulBase);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __TIMER_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// uart.h - Defines and Macros for the UART.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 523 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __UART_H__\r
+#define __UART_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear\r
+// as the ulIntFlags parameter, and returned from UARTIntStatus.\r
+//\r
+//*****************************************************************************\r
+#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask\r
+#define UART_INT_BE 0x200 // Break Error Interrupt Mask\r
+#define UART_INT_PE 0x100 // Parity Error Interrupt Mask\r
+#define UART_INT_FE 0x080 // Framing Error Interrupt Mask\r
+#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask\r
+#define UART_INT_TX 0x020 // Transmit Interrupt Mask\r
+#define UART_INT_RX 0x010 // Receive Interrupt Mask\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to UARTConfigSet as the ulConfig parameter and\r
+// returned by UARTConfigGet in the pulConfig parameter. Additionally, the\r
+// UART_CONFIG_PAR_* subset can be passed to UARTParityModeSet as the ulParity\r
+// parameter, and are returned by UARTParityModeGet.\r
+//\r
+//*****************************************************************************\r
+#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data\r
+#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data\r
+#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data\r
+#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data\r
+#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit\r
+#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits\r
+#define UART_CONFIG_PAR_NONE 0x00000000 // No parity\r
+#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity\r
+#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity\r
+#define UART_CONFIG_PAR_ONE 0x00000086 // Parity bit is one\r
+#define UART_CONFIG_PAR_ZERO 0x00000082 // Parity bit is zero\r
+\r
+//*****************************************************************************\r
+//\r
+// API Function prototypes\r
+//\r
+//*****************************************************************************\r
+extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity);\r
+extern unsigned long UARTParityModeGet(unsigned long ulBase);\r
+extern void UARTConfigSet(unsigned long ulBase, unsigned long ulBaud,\r
+ unsigned long ulConfig);\r
+extern void UARTConfigGet(unsigned long ulBase, unsigned long *pulBaud,\r
+ unsigned long *pulConfig);\r
+extern void UARTEnable(unsigned long ulBase);\r
+extern void UARTDisable(unsigned long ulBase);\r
+extern tBoolean UARTCharsAvail(unsigned long ulBase);\r
+extern tBoolean UARTSpaceAvail(unsigned long ulBase);\r
+extern long UARTCharNonBlockingGet(unsigned long ulBase);\r
+extern long UARTCharGet(unsigned long ulBase);\r
+extern tBoolean UARTCharNonBlockingPut(unsigned long ulBase,\r
+ unsigned char ucData);\r
+extern void UARTCharPut(unsigned long ulBase, unsigned char ucData);\r
+extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState);\r
+extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void));\r
+extern void UARTIntUnregister(unsigned long ulBase);\r
+extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __UART_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// watchdog.h - Prototypes for the Watchdog Timer API\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 523 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __WATCHDOG_H__\r
+#define __WATCHDOG_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern tBoolean WatchdogRunning(unsigned long ulBase);\r
+extern void WatchdogEnable(unsigned long ulBase);\r
+extern void WatchdogResetEnable(unsigned long ulBase);\r
+extern void WatchdogResetDisable(unsigned long ulBase);\r
+extern void WatchdogLock(unsigned long ulBase);\r
+extern void WatchdogUnlock(unsigned long ulBase);\r
+extern tBoolean WatchdogLockState(unsigned long ulBase);\r
+extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal);\r
+extern unsigned long WatchdogReloadGet(unsigned long ulBase);\r
+extern unsigned long WatchdogValueGet(unsigned long ulBase);\r
+extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void));\r
+extern void WatchdogIntUnregister(unsigned long ulBase);\r
+extern void WatchdogIntEnable(unsigned long ulBase);\r
+extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void WatchdogIntClear(unsigned long ulBase);\r
+extern void WatchdogStallDisable(unsigned long ulBase);\r
+extern void WatchdogStallDisable(unsigned long ulBase);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __WATCHDOG_H__\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/**\r
+ * Creates six tasks that operate on three queues as follows:\r
+ *\r
+ * The first two tasks send and receive an incrementing number to/from a queue. \r
+ * One task acts as a producer and the other as the consumer. The consumer is a \r
+ * higher priority than the producer and is set to block on queue reads. The queue \r
+ * only has space for one item - as soon as the producer posts a message on the \r
+ * queue the consumer will unblock, pre-empt the producer, and remove the item.\r
+ * \r
+ * The second two tasks work the other way around. Again the queue used only has\r
+ * enough space for one item. This time the consumer has a lower priority than the \r
+ * producer. The producer will try to post on the queue blocking when the queue is \r
+ * full. When the consumer wakes it will remove the item from the queue, causing \r
+ * the producer to unblock, pre-empt the consumer, and immediately re-fill the \r
+ * queue.\r
+ * \r
+ * The last two tasks use the same queue producer and consumer functions. This time the queue has\r
+ * enough space for lots of items and the tasks operate at the same priority. The \r
+ * producer will execute, placing items into the queue. The consumer will start \r
+ * executing when either the queue becomes full (causing the producer to block) or \r
+ * a context switch occurs (tasks of the same priority will time slice).\r
+ *\r
+ * \page BlockQC blockQ.c\r
+ * \ingroup DemoFiles\r
+ * <HR>\r
+ */\r
+\r
+/*\r
+Changes from V1.00:\r
+ \r
+ + Reversed the priority and block times of the second two demo tasks so\r
+ they operate as per the description above.\r
+\r
+Changes from V2.0.0\r
+\r
+ + Delay periods are now specified using variables and constants of\r
+ portTickType rather than unsigned portLONG.\r
+*/\r
+\r
+\r
+#include <stdlib.h>\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+\r
+/* Demo program include files. */\r
+#include "BlockQ.h"\r
+#include "print.h"\r
+\r
+#define blckqSTACK_SIZE ( ( unsigned portSHORT ) 128 )\r
+#define blckqNUM_TASK_SETS ( 3 )\r
+\r
+/* Structure used to pass parameters to the blocking queue tasks. */\r
+typedef struct BLOCKING_QUEUE_PARAMETERS\r
+{\r
+ xQueueHandle xQueue; /*< The queue to be used by the task. */\r
+ portTickType xBlockTime; /*< The block time to use on queue reads/writes. */\r
+ volatile portSHORT *psCheckVariable; /*< Incremented on each successful cycle to check the task is still running. */\r
+} xBlockingQueueParameters;\r
+\r
+/* Task function that creates an incrementing number and posts it on a queue. */\r
+static void vBlockingQueueProducer( void *pvParameters );\r
+\r
+/* Task function that removes the incrementing number from a queue and checks that \r
+it is the expected number. */\r
+static void vBlockingQueueConsumer( void *pvParameters );\r
+\r
+/* Variables which are incremented each time an item is removed from a queue, and \r
+found to be the expected value. \r
+These are used to check that the tasks are still running. */\r
+static volatile portSHORT sBlockingConsumerCount[ blckqNUM_TASK_SETS ] = { ( portSHORT ) 0, ( portSHORT ) 0, ( portSHORT ) 0 };\r
+\r
+/* Variable which are incremented each time an item is posted on a queue. These \r
+are used to check that the tasks are still running. */\r
+static volatile portSHORT sBlockingProducerCount[ blckqNUM_TASK_SETS ] = { ( portSHORT ) 0, ( portSHORT ) 0, ( portSHORT ) 0 };\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vStartBlockingQueueTasks( unsigned portBASE_TYPE uxPriority )\r
+{\r
+xBlockingQueueParameters *pxQueueParameters1, *pxQueueParameters2;\r
+xBlockingQueueParameters *pxQueueParameters3, *pxQueueParameters4;\r
+xBlockingQueueParameters *pxQueueParameters5, *pxQueueParameters6;\r
+const unsigned portBASE_TYPE uxQueueSize1 = 1, uxQueueSize5 = 5;\r
+const portTickType xBlockTime = ( portTickType ) 1000 / portTICK_RATE_MS;\r
+const portTickType xDontBlock = ( portTickType ) 0;\r
+\r
+ /* Create the first two tasks as described at the top of the file. */ \r
+ \r
+ /* First create the structure used to pass parameters to the consumer tasks. */\r
+ pxQueueParameters1 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );\r
+\r
+ /* Create the queue used by the first two tasks to pass the incrementing number. \r
+ Pass a pointer to the queue in the parameter structure. */\r
+ pxQueueParameters1->xQueue = xQueueCreate( uxQueueSize1, ( unsigned portBASE_TYPE ) sizeof( unsigned portSHORT ) );\r
+\r
+ /* The consumer is created first so gets a block time as described above. */\r
+ pxQueueParameters1->xBlockTime = xBlockTime;\r
+\r
+ /* Pass in the variable that this task is going to increment so we can check it \r
+ is still running. */\r
+ pxQueueParameters1->psCheckVariable = &( sBlockingConsumerCount[ 0 ] );\r
+ \r
+ /* Create the structure used to pass parameters to the producer task. */\r
+ pxQueueParameters2 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );\r
+\r
+ /* Pass the queue to this task also, using the parameter structure. */\r
+ pxQueueParameters2->xQueue = pxQueueParameters1->xQueue;\r
+\r
+ /* The producer is not going to block - as soon as it posts the consumer will \r
+ wake and remove the item so the producer should always have room to post. */\r
+ pxQueueParameters2->xBlockTime = xDontBlock;\r
+\r
+ /* Pass in the variable that this task is going to increment so we can check \r
+ it is still running. */\r
+ pxQueueParameters2->psCheckVariable = &( sBlockingProducerCount[ 0 ] );\r
+\r
+\r
+ /* Note the producer has a lower priority than the consumer when the tasks are \r
+ spawned. */\r
+ xTaskCreate( vBlockingQueueConsumer, "QConsB1", blckqSTACK_SIZE, ( void * ) pxQueueParameters1, uxPriority, NULL );\r
+ xTaskCreate( vBlockingQueueProducer, "QProdB2", blckqSTACK_SIZE, ( void * ) pxQueueParameters2, tskIDLE_PRIORITY, NULL );\r
+\r
+ \r
+\r
+ /* Create the second two tasks as described at the top of the file. This uses \r
+ the same mechanism but reverses the task priorities. */\r
+\r
+ pxQueueParameters3 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );\r
+ pxQueueParameters3->xQueue = xQueueCreate( uxQueueSize1, ( unsigned portBASE_TYPE ) sizeof( unsigned portSHORT ) );\r
+ pxQueueParameters3->xBlockTime = xDontBlock;\r
+ pxQueueParameters3->psCheckVariable = &( sBlockingProducerCount[ 1 ] );\r
+\r
+ pxQueueParameters4 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );\r
+ pxQueueParameters4->xQueue = pxQueueParameters3->xQueue;\r
+ pxQueueParameters4->xBlockTime = xBlockTime;\r
+ pxQueueParameters4->psCheckVariable = &( sBlockingConsumerCount[ 1 ] );\r
+\r
+ xTaskCreate( vBlockingQueueProducer, "QProdB3", blckqSTACK_SIZE, ( void * ) pxQueueParameters3, tskIDLE_PRIORITY, NULL );\r
+ xTaskCreate( vBlockingQueueConsumer, "QConsB4", blckqSTACK_SIZE, ( void * ) pxQueueParameters4, uxPriority, NULL );\r
+\r
+\r
+\r
+ /* Create the last two tasks as described above. The mechanism is again just \r
+ the same. This time both parameter structures are given a block time. */\r
+ pxQueueParameters5 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );\r
+ pxQueueParameters5->xQueue = xQueueCreate( uxQueueSize5, ( unsigned portBASE_TYPE ) sizeof( unsigned portSHORT ) );\r
+ pxQueueParameters5->xBlockTime = xBlockTime;\r
+ pxQueueParameters5->psCheckVariable = &( sBlockingProducerCount[ 2 ] );\r
+\r
+ pxQueueParameters6 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );\r
+ pxQueueParameters6->xQueue = pxQueueParameters5->xQueue;\r
+ pxQueueParameters6->xBlockTime = xBlockTime;\r
+ pxQueueParameters6->psCheckVariable = &( sBlockingConsumerCount[ 2 ] ); \r
+\r
+ xTaskCreate( vBlockingQueueProducer, "QProdB5", blckqSTACK_SIZE, ( void * ) pxQueueParameters5, tskIDLE_PRIORITY, NULL );\r
+ xTaskCreate( vBlockingQueueConsumer, "QConsB6", blckqSTACK_SIZE, ( void * ) pxQueueParameters6, tskIDLE_PRIORITY, NULL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vBlockingQueueProducer( void *pvParameters )\r
+{\r
+unsigned portSHORT usValue = 0;\r
+xBlockingQueueParameters *pxQueueParameters;\r
+const portCHAR * const pcTaskStartMsg = "Blocking queue producer started.\r\n";\r
+const portCHAR * const pcTaskErrorMsg = "Could not post on blocking queue\r\n";\r
+portSHORT sErrorEverOccurred = pdFALSE;\r
+\r
+ pxQueueParameters = ( xBlockingQueueParameters * ) pvParameters;\r
+\r
+ /* Queue a message for printing to say the task has started. */\r
+ vPrintDisplayMessage( &pcTaskStartMsg );\r
+\r
+ for( ;; )\r
+ { \r
+ if( xQueueSend( pxQueueParameters->xQueue, ( void * ) &usValue, pxQueueParameters->xBlockTime ) != pdPASS )\r
+ {\r
+ vPrintDisplayMessage( &pcTaskErrorMsg );\r
+ sErrorEverOccurred = pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ /* We have successfully posted a message, so increment the variable \r
+ used to check we are still running. */\r
+ if( sErrorEverOccurred == pdFALSE )\r
+ {\r
+ ( *pxQueueParameters->psCheckVariable )++;\r
+ }\r
+\r
+ /* Increment the variable we are going to post next time round. The \r
+ consumer will expect the numbers to follow in numerical order. */\r
+ ++usValue;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vBlockingQueueConsumer( void *pvParameters )\r
+{\r
+unsigned portSHORT usData, usExpectedValue = 0;\r
+xBlockingQueueParameters *pxQueueParameters;\r
+const portCHAR * const pcTaskStartMsg = "Blocking queue consumer started.\r\n";\r
+const portCHAR * const pcTaskErrorMsg = "Incorrect value received on blocking queue.\r\n";\r
+portSHORT sErrorEverOccurred = pdFALSE;\r
+\r
+ /* Queue a message for printing to say the task has started. */\r
+ vPrintDisplayMessage( &pcTaskStartMsg );\r
+\r
+ pxQueueParameters = ( xBlockingQueueParameters * ) pvParameters;\r
+\r
+ for( ;; )\r
+ { \r
+ if( xQueueReceive( pxQueueParameters->xQueue, &usData, pxQueueParameters->xBlockTime ) == pdPASS )\r
+ {\r
+ if( usData != usExpectedValue )\r
+ {\r
+ vPrintDisplayMessage( &pcTaskErrorMsg );\r
+\r
+ /* Catch-up. */\r
+ usExpectedValue = usData;\r
+\r
+ sErrorEverOccurred = pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ /* We have successfully received a message, so increment the \r
+ variable used to check we are still running. */ \r
+ if( sErrorEverOccurred == pdFALSE )\r
+ {\r
+ ( *pxQueueParameters->psCheckVariable )++;\r
+ }\r
+ \r
+ /* Increment the value we expect to remove from the queue next time \r
+ round. */\r
+ ++usExpectedValue;\r
+ } \r
+ } \r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This is called to check that all the created tasks are still running. */\r
+portBASE_TYPE xAreBlockingQueuesStillRunning( void )\r
+{\r
+static portSHORT sLastBlockingConsumerCount[ blckqNUM_TASK_SETS ] = { ( portSHORT ) 0, ( portSHORT ) 0, ( portSHORT ) 0 };\r
+static portSHORT sLastBlockingProducerCount[ blckqNUM_TASK_SETS ] = { ( portSHORT ) 0, ( portSHORT ) 0, ( portSHORT ) 0 };\r
+portBASE_TYPE xReturn = pdPASS, xTasks;\r
+\r
+ /* Not too worried about mutual exclusion on these variables as they are 16 \r
+ bits and we are only reading them. We also only care to see if they have \r
+ changed or not.\r
+ \r
+ Loop through each check variable and return pdFALSE if any are found not \r
+ to have changed since the last call. */\r
+\r
+ for( xTasks = 0; xTasks < blckqNUM_TASK_SETS; xTasks++ )\r
+ {\r
+ if( sBlockingConsumerCount[ xTasks ] == sLastBlockingConsumerCount[ xTasks ] )\r
+ {\r
+ xReturn = pdFALSE;\r
+ }\r
+ sLastBlockingConsumerCount[ xTasks ] = sBlockingConsumerCount[ xTasks ];\r
+\r
+\r
+ if( sBlockingProducerCount[ xTasks ] == sLastBlockingProducerCount[ xTasks ] )\r
+ {\r
+ xReturn = pdFALSE;\r
+ }\r
+ sLastBlockingProducerCount[ xTasks ] = sBlockingProducerCount[ xTasks ];\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+\r
+/**\r
+ * This is a very simple queue test. See the BlockQ. c documentation for a more \r
+ * comprehensive version.\r
+ *\r
+ * Creates two tasks that communicate over a single queue. One task acts as a \r
+ * producer, the other a consumer. \r
+ *\r
+ * The producer loops for three iteration, posting an incrementing number onto the \r
+ * queue each cycle. It then delays for a fixed period before doing exactly the \r
+ * same again.\r
+ *\r
+ * The consumer loops emptying the queue. Each item removed from the queue is \r
+ * checked to ensure it contains the expected value. When the queue is empty it \r
+ * blocks for a fixed period, then does the same again.\r
+ *\r
+ * All queue access is performed without blocking. The consumer completely empties \r
+ * the queue each time it runs so the producer should never find the queue full. \r
+ *\r
+ * An error is flagged if the consumer obtains an unexpected value or the producer \r
+ * find the queue is full.\r
+ *\r
+ * \page PollQC pollQ.c\r
+ * \ingroup DemoFiles\r
+ * <HR>\r
+ */\r
+\r
+/*\r
+Changes from V2.0.0\r
+\r
+ + Delay periods are now specified using variables and constants of\r
+ portTickType rather than unsigned portLONG.\r
+*/\r
+\r
+#include <stdlib.h>\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+#include "print.h"\r
+\r
+/* Demo program include files. */\r
+#include "PollQ.h"\r
+\r
+#define pollqSTACK_SIZE ( ( unsigned portSHORT ) 128 )\r
+\r
+/* The task that posts the incrementing number onto the queue. */\r
+static void vPolledQueueProducer( void *pvParameters );\r
+\r
+/* The task that empties the queue. */\r
+static void vPolledQueueConsumer( void *pvParameters );\r
+\r
+/* Variables that are used to check that the tasks are still running with no errors. */\r
+static volatile portSHORT sPollingConsumerCount = 0, sPollingProducerCount = 0;\r
+/*-----------------------------------------------------------*/\r
+\r
+void vStartPolledQueueTasks( unsigned portBASE_TYPE uxPriority )\r
+{\r
+static xQueueHandle xPolledQueue;\r
+const unsigned portBASE_TYPE uxQueueSize = 10;\r
+\r
+ /* Create the queue used by the producer and consumer. */\r
+ xPolledQueue = xQueueCreate( uxQueueSize, ( unsigned portBASE_TYPE ) sizeof( unsigned portSHORT ) );\r
+\r
+ /* Spawn the producer and consumer. */\r
+ xTaskCreate( vPolledQueueConsumer, "QConsNB", pollqSTACK_SIZE, ( void * ) &xPolledQueue, uxPriority, NULL );\r
+ xTaskCreate( vPolledQueueProducer, "QProdNB", pollqSTACK_SIZE, ( void * ) &xPolledQueue, uxPriority, NULL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vPolledQueueProducer( void *pvParameters )\r
+{\r
+unsigned portSHORT usValue = 0, usLoop;\r
+xQueueHandle *pxQueue;\r
+const portTickType xDelay = ( portTickType ) 200 / portTICK_RATE_MS;\r
+const unsigned portSHORT usNumToProduce = 3;\r
+const portCHAR * const pcTaskStartMsg = "Polled queue producer started.\r\n";\r
+const portCHAR * const pcTaskErrorMsg = "Could not post on polled queue.\r\n";\r
+portSHORT sError = pdFALSE;\r
+\r
+ /* Queue a message for printing to say the task has started. */\r
+ vPrintDisplayMessage( &pcTaskStartMsg );\r
+\r
+ /* The queue being used is passed in as the parameter. */\r
+ pxQueue = ( xQueueHandle * ) pvParameters;\r
+\r
+ for( ;; )\r
+ { \r
+ for( usLoop = 0; usLoop < usNumToProduce; ++usLoop )\r
+ {\r
+ /* Send an incrementing number on the queue without blocking. */\r
+ if( xQueueSend( *pxQueue, ( void * ) &usValue, ( portTickType ) 0 ) != pdPASS )\r
+ {\r
+ /* We should never find the queue full - this is an error. */\r
+ vPrintDisplayMessage( &pcTaskErrorMsg );\r
+ sError = pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ if( sError == pdFALSE )\r
+ {\r
+ /* If an error has ever been recorded we stop incrementing the \r
+ check variable. */\r
+ ++sPollingProducerCount;\r
+ }\r
+\r
+ /* Update the value we are going to post next time around. */\r
+ ++usValue;\r
+ }\r
+ }\r
+\r
+ /* Wait before we start posting again to ensure the consumer runs and \r
+ empties the queue. */\r
+ vTaskDelay( xDelay );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vPolledQueueConsumer( void *pvParameters )\r
+{\r
+unsigned portSHORT usData, usExpectedValue = 0;\r
+xQueueHandle *pxQueue;\r
+const portTickType xDelay = ( portTickType ) 200 / portTICK_RATE_MS;\r
+const portCHAR * const pcTaskStartMsg = "Polled queue consumer started.\r\n";\r
+const portCHAR * const pcTaskErrorMsg = "Incorrect value received on polled queue.\r\n";\r
+portSHORT sError = pdFALSE;\r
+\r
+ /* Queue a message for printing to say the task has started. */\r
+ vPrintDisplayMessage( &pcTaskStartMsg );\r
+\r
+ /* The queue being used is passed in as the parameter. */\r
+ pxQueue = ( xQueueHandle * ) pvParameters;\r
+\r
+ for( ;; )\r
+ { \r
+ /* Loop until the queue is empty. */\r
+ while( uxQueueMessagesWaiting( *pxQueue ) )\r
+ {\r
+ if( xQueueReceive( *pxQueue, &usData, ( portTickType ) 0 ) == pdPASS )\r
+ {\r
+ if( usData != usExpectedValue )\r
+ {\r
+ /* This is not what we expected to receive so an error has \r
+ occurred. */\r
+ vPrintDisplayMessage( &pcTaskErrorMsg );\r
+ sError = pdTRUE;\r
+ /* Catch-up to the value we received so our next expected value \r
+ should again be correct. */\r
+ usExpectedValue = usData;\r
+ }\r
+ else\r
+ {\r
+ if( sError == pdFALSE )\r
+ {\r
+ /* Only increment the check variable if no errors have \r
+ occurred. */\r
+ ++sPollingConsumerCount;\r
+ }\r
+ }\r
+ ++usExpectedValue;\r
+ }\r
+ }\r
+\r
+ /* Now the queue is empty we block, allowing the producer to place more \r
+ items in the queue. */\r
+ vTaskDelay( xDelay );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This is called to check that all the created tasks are still running with no errors. */\r
+portBASE_TYPE xArePollingQueuesStillRunning( void )\r
+{\r
+static portSHORT sLastPollingConsumerCount = 0, sLastPollingProducerCount = 0;\r
+portBASE_TYPE xReturn;\r
+\r
+ if( ( sLastPollingConsumerCount == sPollingConsumerCount ) ||\r
+ ( sLastPollingProducerCount == sPollingProducerCount ) \r
+ )\r
+ {\r
+ xReturn = pdFALSE;\r
+ }\r
+ else\r
+ {\r
+ xReturn = pdTRUE;\r
+ }\r
+\r
+ sLastPollingConsumerCount = sPollingConsumerCount;\r
+ sLastPollingProducerCount = sPollingProducerCount;\r
+\r
+ return xReturn;\r
+}\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/**\r
+ * Creates two tasks that operate on an interrupt driven serial port. A loopback \r
+ * connector should be used so that everything that is transmitted is also received. \r
+ * The serial port does not use any flow control. On a standard 9way 'D' connector \r
+ * pins two and three should be connected together.\r
+ *\r
+ * The first task repeatedly sends a string to a queue, character at a time. The \r
+ * serial port interrupt will empty the queue and transmit the characters. The \r
+ * task blocks for a pseudo random period before resending the string.\r
+ *\r
+ * The second task blocks on a queue waiting for a character to be received. \r
+ * Characters received by the serial port interrupt routine are posted onto the \r
+ * queue - unblocking the task making it ready to execute. If this is then the \r
+ * highest priority task ready to run it will run immediately - with a context \r
+ * switch occurring at the end of the interrupt service routine. The task \r
+ * receiving characters is spawned with a higher priority than the task \r
+ * transmitting the characters.\r
+ *\r
+ * With the loop back connector in place, one task will transmit a string and the \r
+ * other will immediately receive it. The receiving task knows the string it \r
+ * expects to receive so can detect an error.\r
+ *\r
+ * This also creates a third task. This is used to test semaphore usage from an\r
+ * ISR and does nothing interesting. \r
+ * \r
+ * \page ComTestC comtest.c\r
+ * \ingroup DemoFiles\r
+ * <HR>\r
+ */\r
+\r
+/*\r
+Changes from V1.00:\r
+ \r
+ + The priority of the Rx task has been lowered. Received characters are\r
+ now processed (read from the queue) at the idle priority, allowing low\r
+ priority tasks to run evenly at times of a high communications overhead.\r
+\r
+Changes from V1.01:\r
+\r
+ + The Tx task now waits a pseudo random time between transissions.\r
+ Previously a fixed period was used but this was not such a good test as\r
+ interrupts fired at regular intervals.\r
+\r
+Changes From V1.2.0:\r
+\r
+ + Use vSerialPutString() instead of single character puts.\r
+ + Only stop the check variable incrementing after two consecutive errors. \r
+\r
+Changed from V1.2.5\r
+\r
+ + Made the Rx task 2 priorities higher than the Tx task. Previously it was\r
+ only 1. This is done to tie in better with the other demo application \r
+ tasks.\r
+\r
+Changes from V2.0.0\r
+\r
+ + Delay periods are now specified using variables and constants of\r
+ portTickType rather than unsigned portLONG.\r
+ + Slight modification to task priorities.\r
+\r
+*/\r
+\r
+\r
+/* Scheduler include files. */\r
+#include <stdlib.h>\r
+#include <string.h>\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo program include files. */\r
+#include "serial.h"\r
+#include "comtest.h"\r
+#include "print.h"\r
+\r
+/* The Tx task will transmit the sequence of characters at a pseudo random\r
+interval. This is the maximum and minimum block time between sends. */\r
+#define comTX_MAX_BLOCK_TIME ( ( portTickType ) 0x15e )\r
+#define comTX_MIN_BLOCK_TIME ( ( portTickType ) 0xc8 )\r
+\r
+#define comMAX_CONSECUTIVE_ERRORS ( 2 )\r
+\r
+#define comSTACK_SIZE ( ( unsigned portSHORT ) 256 )\r
+\r
+#define comRX_RELATIVE_PRIORITY ( 1 )\r
+\r
+/* Handle to the com port used by both tasks. */\r
+static xComPortHandle xPort;\r
+\r
+/* The transmit function as described at the top of the file. */\r
+static void vComTxTask( void *pvParameters );\r
+\r
+/* The receive function as described at the top of the file. */\r
+static void vComRxTask( void *pvParameters );\r
+\r
+/* The semaphore test function as described at the top of the file. */\r
+static void vSemTestTask( void * pvParameters );\r
+\r
+/* The string that is repeatedly transmitted. */\r
+const portCHAR * const pcMessageToExchange = "Send this message over and over again to check communications interrupts. "\r
+ "0123456789abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ\r\n";\r
+\r
+/* Variables that are incremented on each cycle of each task. These are used to \r
+check that both tasks are still executing. */\r
+volatile portSHORT sTxCount = 0, sRxCount = 0, sSemCount = 0;\r
+\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vStartComTestTasks( unsigned portBASE_TYPE uxPriority, eCOMPort ePort, eBaud eBaudRate )\r
+{\r
+const unsigned portBASE_TYPE uxBufferLength = 255;\r
+\r
+ /* Initialise the com port then spawn both tasks. */\r
+ xPort = xSerialPortInit( ePort, eBaudRate, serNO_PARITY, serBITS_8, serSTOP_1, uxBufferLength );\r
+ xTaskCreate( vComTxTask, "COMTx", comSTACK_SIZE, NULL, uxPriority, NULL );\r
+ xTaskCreate( vComRxTask, "COMRx", comSTACK_SIZE, NULL, uxPriority + comRX_RELATIVE_PRIORITY, NULL );\r
+ xTaskCreate( vSemTestTask, "ISRSemTst", comSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vComTxTask( void *pvParameters )\r
+{\r
+const portCHAR * const pcTaskStartMsg = "COM Tx task started.\r\n";\r
+portTickType xTimeToWait;\r
+\r
+ /* Stop warnings. */\r
+ ( void ) pvParameters;\r
+\r
+ /* Queue a message for printing to say the task has started. */\r
+ vPrintDisplayMessage( &pcTaskStartMsg );\r
+\r
+ for( ;; )\r
+ {\r
+ /* Send the string to the serial port. */\r
+ vSerialPutString( xPort, pcMessageToExchange, strlen( pcMessageToExchange ) );\r
+\r
+ /* We have posted all the characters in the string - increment the variable \r
+ used to check that this task is still running, then wait before re-sending \r
+ the string. */\r
+ sTxCount++;\r
+\r
+ xTimeToWait = xTaskGetTickCount();\r
+\r
+ /* Make sure we don't wait too long... */\r
+ xTimeToWait %= comTX_MAX_BLOCK_TIME;\r
+\r
+ /* ...but we do want to wait. */\r
+ if( xTimeToWait < comTX_MIN_BLOCK_TIME )\r
+ {\r
+ xTimeToWait = comTX_MIN_BLOCK_TIME;\r
+ }\r
+\r
+ vTaskDelay( xTimeToWait );\r
+ }\r
+} /*lint !e715 !e818 pvParameters is required for a task function even if it is not referenced. */\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vComRxTask( void *pvParameters )\r
+{\r
+const portCHAR * const pcTaskStartMsg = "COM Rx task started.\r\n";\r
+const portCHAR * const pcTaskErrorMsg = "COM read error\r\n";\r
+const portCHAR * const pcTaskRestartMsg = "COM resynced\r\n";\r
+const portCHAR * const pcTaskTimeoutMsg = "COM Rx timed out\r\n";\r
+const portTickType xBlockTime = ( portTickType ) 0xffff / portTICK_RATE_MS;\r
+const portCHAR *pcExpectedChar;\r
+portBASE_TYPE xGotChar;\r
+portCHAR cRxedChar;\r
+portSHORT sResyncRequired, sConsecutiveErrors, sLatchedError;\r
+\r
+ /* Stop warnings. */\r
+ ( void ) pvParameters;\r
+\r
+ /* Queue a message for printing to say the task has started. */\r
+ vPrintDisplayMessage( &pcTaskStartMsg );\r
+ \r
+ /* The first expected character is the first character in the string. */\r
+ pcExpectedChar = pcMessageToExchange;\r
+ sResyncRequired = pdFALSE;\r
+ sConsecutiveErrors = 0;\r
+ sLatchedError = pdFALSE;\r
+\r
+ for( ;; )\r
+ {\r
+ /* Receive a message from the com port interrupt routine. If a message is \r
+ not yet available the call will block the task. */\r
+ xGotChar = xSerialGetChar( xPort, &cRxedChar, xBlockTime );\r
+ if( xGotChar == pdTRUE )\r
+ {\r
+ if( sResyncRequired == pdTRUE )\r
+ {\r
+ /* We got out of sequence and are waiting for the start of the next \r
+ transmission of the string. */\r
+ if( cRxedChar == '\n' )\r
+ {\r
+ /* This is the end of the message so we can start again - with \r
+ the first character in the string being the next thing we expect \r
+ to receive. */\r
+ pcExpectedChar = pcMessageToExchange;\r
+ sResyncRequired = pdFALSE;\r
+\r
+ /* Queue a message for printing to say that we are going to try \r
+ again. */\r
+ vPrintDisplayMessage( &pcTaskRestartMsg );\r
+\r
+ /* Stop incrementing the check variable, if consecutive errors occur. */\r
+ sConsecutiveErrors++;\r
+ if( sConsecutiveErrors >= comMAX_CONSECUTIVE_ERRORS )\r
+ {\r
+ sLatchedError = pdTRUE;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* We have received a character, but is it the expected character? */\r
+ if( cRxedChar != *pcExpectedChar )\r
+ {\r
+ /* This was not the expected character so post a message for \r
+ printing to say that an error has occurred. We will then wait \r
+ to resynchronise. */\r
+ vPrintDisplayMessage( &pcTaskErrorMsg ); \r
+ sResyncRequired = pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ /* This was the expected character so next time we will expect \r
+ the next character in the string. Wrap back to the beginning \r
+ of the string when the null terminator has been reached. */\r
+ pcExpectedChar++;\r
+ if( *pcExpectedChar == '\0' )\r
+ {\r
+ pcExpectedChar = pcMessageToExchange;\r
+\r
+ /* We have got through the entire string without error. */\r
+ sConsecutiveErrors = 0;\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Increment the count that is used to check that this task is still \r
+ running. This is only done if an error has never occurred. */\r
+ if( sLatchedError == pdFALSE )\r
+ {\r
+ sRxCount++; \r
+ }\r
+ }\r
+ else\r
+ {\r
+ vPrintDisplayMessage( &pcTaskTimeoutMsg );\r
+ }\r
+ }\r
+} /*lint !e715 !e818 pvParameters is required for a task function even if it is not referenced. */\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vSemTestTask( void * pvParameters )\r
+{\r
+const portCHAR * const pcTaskStartMsg = "ISR Semaphore test started.\r\n";\r
+\r
+ /* Stop warnings. */\r
+ ( void ) pvParameters;\r
+\r
+ /* Queue a message for printing to say the task has started. */\r
+ vPrintDisplayMessage( &pcTaskStartMsg );\r
+\r
+ for( ;; )\r
+ {\r
+ if( xSerialWaitForSemaphore( xPort ) )\r
+ {\r
+ sSemCount++; \r
+ }\r
+ }\r
+} /*lint !e715 !e830 !e818 pvParameters not used but function prototype must be standard for task function. */\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This is called to check that all the created tasks are still running. */\r
+portBASE_TYPE xAreComTestTasksStillRunning( void )\r
+{\r
+static portSHORT sLastTxCount = 0, sLastRxCount = 0, sLastSemCount = 0;\r
+portBASE_TYPE xReturn;\r
+\r
+ /* Not too worried about mutual exclusion on these variables as they are 16 \r
+ bits and we are only reading them. We also only care to see if they have \r
+ changed or not. */\r
+\r
+ if( ( sTxCount == sLastTxCount ) || ( sRxCount == sLastRxCount ) || ( sSemCount == sLastSemCount ) )\r
+ {\r
+ xReturn = pdFALSE;\r
+ }\r
+ else\r
+ {\r
+ xReturn = pdTRUE;\r
+ }\r
+\r
+ sLastTxCount = sTxCount;\r
+ sLastRxCount = sRxCount;\r
+ sLastSemCount = sSemCount;\r
+\r
+ return xReturn;\r
+}\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/**\r
+ * Create a single persistent task which periodically dynamically creates another \r
+ * four tasks. The original task is called the creator task, the four tasks it \r
+ * creates are called suicidal tasks.\r
+ *\r
+ * Two of the created suicidal tasks kill one other suicidal task before killing \r
+ * themselves - leaving just the original task remaining. \r
+ *\r
+ * The creator task must be spawned after all of the other demo application tasks \r
+ * as it keeps a check on the number of tasks under the scheduler control. The \r
+ * number of tasks it expects to see running should never be greater than the \r
+ * number of tasks that were in existence when the creator task was spawned, plus \r
+ * one set of four suicidal tasks. If this number is exceeded an error is flagged.\r
+ *\r
+ * \page DeathC death.c\r
+ * \ingroup DemoFiles\r
+ * <HR>\r
+ */\r
+\r
+/*\r
+Changes from V2.0.0\r
+\r
+ + Delay periods are now specified using variables and constants of\r
+ portTickType rather than unsigned portLONG.\r
+*/\r
+\r
+#include <stdlib.h>\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo program include files. */\r
+#include "death.h"\r
+#include "print.h"\r
+\r
+#define deathSTACK_SIZE ( ( unsigned portSHORT ) 512 )\r
+\r
+/* The task originally created which is responsible for periodically dynamically \r
+creating another four tasks. */\r
+static void vCreateTasks( void *pvParameters );\r
+\r
+/* The task function of the dynamically created tasks. */\r
+static void vSuicidalTask( void *pvParameters );\r
+\r
+/* A variable which is incremented every time the dynamic tasks are created. This \r
+is used to check that the task is still running. */\r
+static volatile portSHORT sCreationCount = 0;\r
+\r
+/* Used to store the number of tasks that were originally running so the creator \r
+task can tell if any of the suicidal tasks have failed to die. */\r
+static volatile unsigned portBASE_TYPE uxTasksRunningAtStart = 0;\r
+static const unsigned portBASE_TYPE uxMaxNumberOfExtraTasksRunning = 5;\r
+\r
+/* Used to store a handle to the tasks that should be killed by a suicidal task, \r
+before it kills itself. */\r
+xTaskHandle xCreatedTask1, xCreatedTask2;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vCreateSuicidalTasks( unsigned portBASE_TYPE uxPriority )\r
+{\r
+unsigned portBASE_TYPE *puxPriority;\r
+\r
+ /* Create the Creator tasks - passing in as a parameter the priority at which \r
+ the suicidal tasks should be created. */\r
+ puxPriority = ( unsigned portBASE_TYPE * ) pvPortMalloc( sizeof( unsigned portBASE_TYPE ) );\r
+ *puxPriority = uxPriority;\r
+\r
+ xTaskCreate( vCreateTasks, "CREATOR", deathSTACK_SIZE, ( void * ) puxPriority, uxPriority, NULL );\r
+\r
+ /* Record the number of tasks that are running now so we know if any of the \r
+ suicidal tasks have failed to be killed. */\r
+ uxTasksRunningAtStart = uxTaskGetNumberOfTasks();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vSuicidalTask( void *pvParameters )\r
+{\r
+portDOUBLE d1, d2;\r
+xTaskHandle xTaskToKill;\r
+const portTickType xDelay = ( portTickType ) 500 / portTICK_RATE_MS;\r
+\r
+ if( pvParameters != NULL )\r
+ {\r
+ /* This task is periodically created four times. Tow created tasks are \r
+ passed a handle to the other task so it can kill it before killing itself. \r
+ The other task is passed in null. */\r
+ xTaskToKill = *( xTaskHandle* )pvParameters;\r
+ }\r
+ else\r
+ {\r
+ xTaskToKill = NULL;\r
+ }\r
+\r
+ for( ;; )\r
+ {\r
+ /* Do something random just to use some stack and registers. */\r
+ d1 = 2.4;\r
+ d2 = 89.2;\r
+ d2 *= d1;\r
+ vTaskDelay( xDelay );\r
+\r
+ if( xTaskToKill != NULL )\r
+ {\r
+ /* Make sure the other task has a go before we delete it. */\r
+ vTaskDelay( ( portTickType ) 0 );\r
+ /* Kill the other task that was created by vCreateTasks(). */\r
+ vTaskDelete( xTaskToKill );\r
+ /* Kill ourselves. */\r
+ vTaskDelete( NULL );\r
+ }\r
+ }\r
+}/*lint !e818 !e550 Function prototype must be as per standard for task functions. */\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vCreateTasks( void *pvParameters )\r
+{\r
+const portTickType xDelay = ( portTickType ) 1000 / portTICK_RATE_MS;\r
+unsigned portBASE_TYPE uxPriority;\r
+const portCHAR * const pcTaskStartMsg = "Create task started.\r\n";\r
+\r
+ /* Queue a message for printing to say the task has started. */\r
+ vPrintDisplayMessage( &pcTaskStartMsg );\r
+\r
+ uxPriority = *( unsigned portBASE_TYPE * ) pvParameters;\r
+ vPortFree( pvParameters );\r
+\r
+ for( ;; )\r
+ {\r
+ /* Just loop round, delaying then creating the four suicidal tasks. */\r
+ vTaskDelay( xDelay );\r
+\r
+ xTaskCreate( vSuicidalTask, "SUICIDE1", deathSTACK_SIZE, NULL, uxPriority, &xCreatedTask1 );\r
+ xTaskCreate( vSuicidalTask, "SUICIDE2", deathSTACK_SIZE, &xCreatedTask1, uxPriority, NULL );\r
+\r
+ xTaskCreate( vSuicidalTask, "SUICIDE1", deathSTACK_SIZE, NULL, uxPriority, &xCreatedTask2 );\r
+ xTaskCreate( vSuicidalTask, "SUICIDE2", deathSTACK_SIZE, &xCreatedTask2, uxPriority, NULL );\r
+\r
+ ++sCreationCount;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This is called to check that the creator task is still running and that there \r
+are not any more than four extra tasks. */\r
+portBASE_TYPE xIsCreateTaskStillRunning( void )\r
+{\r
+static portSHORT sLastCreationCount = 0;\r
+portSHORT sReturn = pdTRUE;\r
+unsigned portBASE_TYPE uxTasksRunningNow;\r
+\r
+ if( sLastCreationCount == sCreationCount )\r
+ {\r
+ sReturn = pdFALSE;\r
+ }\r
+ \r
+ uxTasksRunningNow = uxTaskGetNumberOfTasks();\r
+\r
+ if( uxTasksRunningNow < uxTasksRunningAtStart )\r
+ {\r
+ sReturn = pdFALSE;\r
+ }\r
+ else if( ( uxTasksRunningNow - uxTasksRunningAtStart ) > uxMaxNumberOfExtraTasksRunning )\r
+ {\r
+ sReturn = pdFALSE;\r
+ }\r
+ else\r
+ {\r
+ /* Everything is okay. */\r
+ }\r
+\r
+ return sReturn;\r
+}\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/**\r
+ * The first test creates three tasks - two counter tasks (one continuous count \r
+ * and one limited count) and one controller. A "count" variable is shared \r
+ * between all three tasks. The two counter tasks should never be in a "ready" \r
+ * state at the same time. The controller task runs at the same priority as \r
+ * the continuous count task, and at a lower priority than the limited count \r
+ * task.\r
+ *\r
+ * One counter task loops indefinitely, incrementing the shared count variable\r
+ * on each iteration. To ensure it has exclusive access to the variable it\r
+ * raises it's priority above that of the controller task before each \r
+ * increment, lowering it again to it's original priority before starting the\r
+ * next iteration.\r
+ *\r
+ * The other counter task increments the shared count variable on each\r
+ * iteration of it's loop until the count has reached a limit of 0xff - at\r
+ * which point it suspends itself. It will not start a new loop until the \r
+ * controller task has made it "ready" again by calling vTaskResume (). \r
+ * This second counter task operates at a higher priority than controller \r
+ * task so does not need to worry about mutual exclusion of the counter \r
+ * variable.\r
+ *\r
+ * The controller task is in two sections. The first section controls and\r
+ * monitors the continuous count task. When this section is operational the \r
+ * limited count task is suspended. Likewise, the second section controls \r
+ * and monitors the limited count task. When this section is operational the \r
+ * continuous count task is suspended.\r
+ *\r
+ * In the first section the controller task first takes a copy of the shared\r
+ * count variable. To ensure mutual exclusion on the count variable it\r
+ * suspends the continuous count task, resuming it again when the copy has been\r
+ * taken. The controller task then sleeps for a fixed period - during which\r
+ * the continuous count task will execute and increment the shared variable.\r
+ * When the controller task wakes it checks that the continuous count task\r
+ * has executed by comparing the copy of the shared variable with its current\r
+ * value. This time, to ensure mutual exclusion, the scheduler itself is \r
+ * suspended with a call to vTaskSuspendAll (). This is for demonstration \r
+ * purposes only and is not a recommended technique due to its inefficiency.\r
+ *\r
+ * After a fixed number of iterations the controller task suspends the \r
+ * continuous count task, and moves on to its second section.\r
+ *\r
+ * At the start of the second section the shared variable is cleared to zero.\r
+ * The limited count task is then woken from it's suspension by a call to\r
+ * vTaskResume (). As this counter task operates at a higher priority than\r
+ * the controller task the controller task should not run again until the\r
+ * shared variable has been counted up to the limited value causing the counter\r
+ * task to suspend itself. The next line after vTaskResume () is therefore\r
+ * a check on the shared variable to ensure everything is as expected.\r
+ *\r
+ *\r
+ * The second test consists of a couple of very simple tasks that post onto a \r
+ * queue while the scheduler is suspended. This test was added to test parts\r
+ * of the scheduler not exercised by the first test.\r
+ *\r
+ *\r
+ * The final set of two tasks implements a third test. This simply raises the\r
+ * priority of a task while the scheduler is suspended. Again this test was\r
+ * added to exercise parts of the code not covered by the first test.\r
+ *\r
+ * \page Priorities dynamic.c\r
+ * \ingroup DemoFiles\r
+ * <HR>\r
+ */\r
+\r
+/*\r
+Changes from V2.0.0\r
+\r
+ + Delay periods are now specified using variables and constants of\r
+ portTickType rather than unsigned portLONG.\r
+ + Added a second, simple test that uses the functions \r
+ vQueueReceiveWhenSuspendedTask() and vQueueSendWhenSuspendedTask().\r
+\r
+Changes from V3.1.1\r
+\r
+ + Added a third simple test that uses the vTaskPrioritySet() function\r
+ while the scheduler is suspended.\r
+ + Modified the controller task slightly to test the calling of \r
+ vTaskResumeAll() while the scheduler is suspended.\r
+*/\r
+\r
+#include <stdlib.h>\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "semphr.h"\r
+\r
+/* Demo app include files. */\r
+#include "dynamic.h"\r
+#include "print.h"\r
+\r
+/* Function that implements the "limited count" task as described above. */\r
+static void vLimitedIncrementTask( void * pvParameters );\r
+\r
+/* Function that implements the "continuous count" task as described above. */\r
+static void vContinuousIncrementTask( void * pvParameters );\r
+\r
+/* Function that implements the controller task as described above. */\r
+static void vCounterControlTask( void * pvParameters );\r
+\r
+/* The simple test functions that check sending and receiving while the\r
+scheduler is suspended. */\r
+static void vQueueReceiveWhenSuspendedTask( void *pvParameters );\r
+static void vQueueSendWhenSuspendedTask( void *pvParameters );\r
+\r
+/* The simple test functions that check raising and lowering of task priorities\r
+while the scheduler is suspended. */\r
+static void prvChangePriorityWhenSuspendedTask( void *pvParameters );\r
+static void prvChangePriorityHelperTask( void *pvParameters );\r
+\r
+\r
+/* Demo task specific constants. */\r
+#define priSTACK_SIZE ( ( unsigned portSHORT ) 128 )\r
+#define priSLEEP_TIME ( ( portTickType ) 50 )\r
+#define priLOOPS ( 5 )\r
+#define priMAX_COUNT ( ( unsigned portLONG ) 0xff )\r
+#define priNO_BLOCK ( ( portTickType ) 0 )\r
+#define priSUSPENDED_QUEUE_LENGTH ( 1 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Handles to the two counter tasks. These could be passed in as parameters\r
+to the controller task to prevent them having to be file scope. */\r
+static xTaskHandle xContinuousIncrementHandle, xLimitedIncrementHandle, xChangePriorityWhenSuspendedHandle;\r
+\r
+/* The shared counter variable. This is passed in as a parameter to the two \r
+counter variables for demonstration purposes. */\r
+static unsigned portLONG ulCounter;\r
+\r
+/* Variable used in a similar way by the test that checks the raising and\r
+lowering of task priorities while the scheduler is suspended. */\r
+static unsigned portLONG ulPrioritySetCounter;\r
+\r
+/* Variables used to check that the tasks are still operating without error.\r
+Each complete iteration of the controller task increments this variable\r
+provided no errors have been found. The variable maintaining the same value\r
+is therefore indication of an error. */\r
+static unsigned portSHORT usCheckVariable = ( unsigned portSHORT ) 0;\r
+static portBASE_TYPE xSuspendedQueueSendError = pdFALSE;\r
+static portBASE_TYPE xSuspendedQueueReceiveError = pdFALSE;\r
+static portBASE_TYPE xPriorityRaiseWhenSuspendedError = pdFALSE;\r
+\r
+/* Queue used by the second test. */\r
+xQueueHandle xSuspendedTestQueue;\r
+\r
+/*-----------------------------------------------------------*/\r
+/*\r
+ * Start the seven tasks as described at the top of the file.\r
+ * Note that the limited count task is given a higher priority.\r
+ */\r
+void vStartDynamicPriorityTasks( void )\r
+{\r
+ xSuspendedTestQueue = xQueueCreate( priSUSPENDED_QUEUE_LENGTH, sizeof( unsigned portLONG ) );\r
+ xTaskCreate( vContinuousIncrementTask, "CONT_INC", priSTACK_SIZE, ( void * ) &ulCounter, tskIDLE_PRIORITY, &xContinuousIncrementHandle );\r
+ xTaskCreate( vLimitedIncrementTask, "LIM_INC", priSTACK_SIZE, ( void * ) &ulCounter, tskIDLE_PRIORITY + 1, &xLimitedIncrementHandle );\r
+ xTaskCreate( vCounterControlTask, "C_CTRL", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );\r
+ xTaskCreate( vQueueSendWhenSuspendedTask, "SUSP_SEND", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );\r
+ xTaskCreate( vQueueReceiveWhenSuspendedTask, "SUSP_RECV", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );\r
+ xTaskCreate( prvChangePriorityWhenSuspendedTask, "1st_P_CHANGE", priSTACK_SIZE, NULL, tskIDLE_PRIORITY + 1, NULL );\r
+ xTaskCreate( prvChangePriorityHelperTask, "2nt_P_CHANGE", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, &xChangePriorityWhenSuspendedHandle );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Just loops around incrementing the shared variable until the limit has been\r
+ * reached. Once the limit has been reached it suspends itself. \r
+ */\r
+static void vLimitedIncrementTask( void * pvParameters )\r
+{\r
+unsigned portLONG *pulCounter;\r
+\r
+ /* Take a pointer to the shared variable from the parameters passed into\r
+ the task. */\r
+ pulCounter = ( unsigned portLONG * ) pvParameters;\r
+\r
+ /* This will run before the control task, so the first thing it does is\r
+ suspend - the control task will resume it when ready. */\r
+ vTaskSuspend( NULL );\r
+\r
+ for( ;; )\r
+ {\r
+ /* Just count up to a value then suspend. */\r
+ ( *pulCounter )++; \r
+ \r
+ if( *pulCounter >= priMAX_COUNT )\r
+ {\r
+ vTaskSuspend( NULL );\r
+ } \r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Just keep counting the shared variable up. The control task will suspend\r
+ * this task when it wants.\r
+ */\r
+static void vContinuousIncrementTask( void * pvParameters )\r
+{\r
+unsigned portLONG *pulCounter;\r
+unsigned portBASE_TYPE uxOurPriority;\r
+\r
+ /* Take a pointer to the shared variable from the parameters passed into\r
+ the task. */\r
+ pulCounter = ( unsigned portLONG * ) pvParameters;\r
+\r
+ /* Query our priority so we can raise it when exclusive access to the \r
+ shared variable is required. */\r
+ uxOurPriority = uxTaskPriorityGet( NULL );\r
+\r
+ for( ;; )\r
+ {\r
+ /* Raise our priority above the controller task to ensure a context\r
+ switch does not occur while we are accessing this variable. */\r
+ vTaskPrioritySet( NULL, uxOurPriority + 1 );\r
+ ( *pulCounter )++; \r
+ vTaskPrioritySet( NULL, uxOurPriority );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Controller task as described above.\r
+ */\r
+static void vCounterControlTask( void * pvParameters )\r
+{\r
+unsigned portLONG ulLastCounter;\r
+portSHORT sLoops;\r
+portSHORT sError = pdFALSE;\r
+const portCHAR * const pcTaskStartMsg = "Priority manipulation tasks started.\r\n";\r
+const portCHAR * const pcTaskFailMsg = "Priority manipulation Task Failed\r\n";\r
+\r
+ /* Just to stop warning messages. */\r
+ ( void ) pvParameters;\r
+\r
+ /* Queue a message for printing to say the task has started. */\r
+ vPrintDisplayMessage( &pcTaskStartMsg );\r
+\r
+ for( ;; )\r
+ {\r
+ /* Start with the counter at zero. */\r
+ ulCounter = ( unsigned portLONG ) 0;\r
+\r
+ /* First section : */\r
+\r
+ /* Check the continuous count task is running. */\r
+ for( sLoops = 0; sLoops < priLOOPS; sLoops++ )\r
+ {\r
+ /* Suspend the continuous count task so we can take a mirror of the\r
+ shared variable without risk of corruption. */\r
+ vTaskSuspend( xContinuousIncrementHandle );\r
+ ulLastCounter = ulCounter;\r
+ vTaskResume( xContinuousIncrementHandle );\r
+ \r
+ /* Now delay to ensure the other task has processor time. */\r
+ vTaskDelay( priSLEEP_TIME );\r
+\r
+ /* Check the shared variable again. This time to ensure mutual \r
+ exclusion the whole scheduler will be locked. This is just for\r
+ demo purposes! */\r
+ vTaskSuspendAll();\r
+ {\r
+ if( ulLastCounter == ulCounter )\r
+ {\r
+ /* The shared variable has not changed. There is a problem\r
+ with the continuous count task so flag an error. */\r
+ sError = pdTRUE;\r
+ xTaskResumeAll();\r
+ vPrintDisplayMessage( &pcTaskFailMsg );\r
+ vTaskSuspendAll();\r
+ }\r
+ }\r
+ xTaskResumeAll();\r
+ }\r
+\r
+\r
+ /* Second section: */\r
+\r
+ /* Suspend the continuous counter task so it stops accessing the shared variable. */\r
+ vTaskSuspend( xContinuousIncrementHandle );\r
+\r
+ /* Reset the variable. */\r
+ ulCounter = ( unsigned portLONG ) 0;\r
+\r
+ /* Resume the limited count task which has a higher priority than us.\r
+ We should therefore not return from this call until the limited count\r
+ task has suspended itself with a known value in the counter variable. \r
+ The scheduler suspension is not necessary but is included for test\r
+ purposes. */\r
+ vTaskSuspendAll();\r
+ vTaskResume( xLimitedIncrementHandle );\r
+ xTaskResumeAll();\r
+\r
+ /* Does the counter variable have the expected value? */\r
+ if( ulCounter != priMAX_COUNT )\r
+ {\r
+ sError = pdTRUE;\r
+ vPrintDisplayMessage( &pcTaskFailMsg );\r
+ }\r
+\r
+ if( sError == pdFALSE )\r
+ {\r
+ /* If no errors have occurred then increment the check variable. */\r
+ portENTER_CRITICAL();\r
+ usCheckVariable++;\r
+ portEXIT_CRITICAL();\r
+ }\r
+\r
+ /* Resume the continuous count task and do it all again. */\r
+ vTaskResume( xContinuousIncrementHandle );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vQueueSendWhenSuspendedTask( void *pvParameters )\r
+{\r
+static unsigned portLONG ulValueToSend = ( unsigned portLONG ) 0;\r
+const portCHAR * const pcTaskStartMsg = "Queue send while suspended task started.\r\n";\r
+const portCHAR * const pcTaskFailMsg = "Queue send while suspended failed.\r\n";\r
+\r
+ /* Just to stop warning messages. */\r
+ ( void ) pvParameters;\r
+\r
+ /* Queue a message for printing to say the task has started. */\r
+ vPrintDisplayMessage( &pcTaskStartMsg );\r
+\r
+ for( ;; )\r
+ {\r
+ vTaskSuspendAll();\r
+ {\r
+ /* We must not block while the scheduler is suspended! */\r
+ if( xQueueSend( xSuspendedTestQueue, ( void * ) &ulValueToSend, priNO_BLOCK ) != pdTRUE )\r
+ {\r
+ if( xSuspendedQueueSendError == pdFALSE )\r
+ {\r
+ xTaskResumeAll();\r
+ vPrintDisplayMessage( &pcTaskFailMsg );\r
+ vTaskSuspendAll();\r
+ }\r
+\r
+ xSuspendedQueueSendError = pdTRUE;\r
+ }\r
+ }\r
+ xTaskResumeAll();\r
+\r
+ vTaskDelay( priSLEEP_TIME );\r
+\r
+ ++ulValueToSend;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vQueueReceiveWhenSuspendedTask( void *pvParameters )\r
+{\r
+static unsigned portLONG ulExpectedValue = ( unsigned portLONG ) 0, ulReceivedValue;\r
+const portCHAR * const pcTaskStartMsg = "Queue receive while suspended task started.\r\n";\r
+const portCHAR * const pcTaskFailMsg = "Queue receive while suspended failed.\r\n";\r
+portBASE_TYPE xGotValue;\r
+\r
+ /* Just to stop warning messages. */\r
+ ( void ) pvParameters;\r
+\r
+ /* Queue a message for printing to say the task has started. */\r
+ vPrintDisplayMessage( &pcTaskStartMsg );\r
+\r
+ for( ;; )\r
+ {\r
+ do\r
+ {\r
+ /* Suspending the scheduler here is fairly pointless and \r
+ undesirable for a normal application. It is done here purely\r
+ to test the scheduler. The inner xTaskResumeAll() should\r
+ never return pdTRUE as the scheduler is still locked by the\r
+ outer call. */\r
+ vTaskSuspendAll();\r
+ {\r
+ vTaskSuspendAll();\r
+ {\r
+ xGotValue = xQueueReceive( xSuspendedTestQueue, ( void * ) &ulReceivedValue, priNO_BLOCK );\r
+ }\r
+ if( xTaskResumeAll() )\r
+ {\r
+ xSuspendedQueueReceiveError = pdTRUE;\r
+ }\r
+ }\r
+ xTaskResumeAll();\r
+\r
+ } while( xGotValue == pdFALSE );\r
+\r
+ if( ulReceivedValue != ulExpectedValue )\r
+ {\r
+ if( xSuspendedQueueReceiveError == pdFALSE )\r
+ {\r
+ vPrintDisplayMessage( &pcTaskFailMsg );\r
+ }\r
+ xSuspendedQueueReceiveError = pdTRUE;\r
+ }\r
+\r
+ ++ulExpectedValue;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvChangePriorityWhenSuspendedTask( void *pvParameters )\r
+{\r
+const portCHAR * const pcTaskStartMsg = "Priority change when suspended task started.\r\n";\r
+const portCHAR * const pcTaskFailMsg = "Priority change when suspended task failed.\r\n";\r
+\r
+ /* Just to stop warning messages. */\r
+ ( void ) pvParameters;\r
+\r
+ /* Queue a message for printing to say the task has started. */\r
+ vPrintDisplayMessage( &pcTaskStartMsg ); \r
+ \r
+ for( ;; )\r
+ {\r
+ /* Start with the counter at 0 so we know what the counter should be\r
+ when we check it next. */\r
+ ulPrioritySetCounter = ( unsigned portLONG ) 0;\r
+\r
+ /* Resume the helper task. At this time it has a priority lower than\r
+ ours so no context switch should occur. */\r
+ vTaskResume( xChangePriorityWhenSuspendedHandle );\r
+\r
+ /* Check to ensure the task just resumed has not executed. */\r
+ portENTER_CRITICAL();\r
+ {\r
+ if( ulPrioritySetCounter != ( unsigned portLONG ) 0 )\r
+ {\r
+ xPriorityRaiseWhenSuspendedError = pdTRUE;\r
+ vPrintDisplayMessage( &pcTaskFailMsg );\r
+ }\r
+ }\r
+ portEXIT_CRITICAL();\r
+\r
+ /* Now try raising the priority while the scheduler is suspended. */\r
+ vTaskSuspendAll();\r
+ {\r
+ vTaskPrioritySet( xChangePriorityWhenSuspendedHandle, ( configMAX_PRIORITIES - 1 ) );\r
+\r
+ /* Again, even though the helper task has a priority greater than \r
+ ours, it should not have executed yet because the scheduler is\r
+ suspended. */\r
+ portENTER_CRITICAL();\r
+ {\r
+ if( ulPrioritySetCounter != ( unsigned portLONG ) 0 )\r
+ {\r
+ xPriorityRaiseWhenSuspendedError = pdTRUE;\r
+ vPrintDisplayMessage( &pcTaskFailMsg );\r
+ }\r
+ }\r
+ portEXIT_CRITICAL();\r
+ }\r
+ xTaskResumeAll();\r
+ \r
+ /* Now the scheduler has been resumed the helper task should \r
+ immediately preempt us and execute. When it executes it will increment\r
+ the ulPrioritySetCounter exactly once before suspending itself.\r
+\r
+ We should now always find the counter set to 1. */\r
+ portENTER_CRITICAL();\r
+ {\r
+ if( ulPrioritySetCounter != ( unsigned portLONG ) 1 )\r
+ {\r
+ xPriorityRaiseWhenSuspendedError = pdTRUE;\r
+ vPrintDisplayMessage( &pcTaskFailMsg );\r
+ }\r
+ }\r
+ portEXIT_CRITICAL();\r
+\r
+ /* Delay until we try this again. */ \r
+ vTaskDelay( priSLEEP_TIME * 2 );\r
+ \r
+ /* Set the priority of the helper task back ready for the next \r
+ execution of this task. */\r
+ vTaskSuspendAll();\r
+ vTaskPrioritySet( xChangePriorityWhenSuspendedHandle, tskIDLE_PRIORITY ); \r
+ xTaskResumeAll(); \r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvChangePriorityHelperTask( void *pvParameters )\r
+{\r
+ /* Just to stop warning messages. */\r
+ ( void ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ /* This is the helper task for prvChangePriorityWhenSuspendedTask().\r
+ It has it's priority raised and lowered. When it runs it simply \r
+ increments the counter then suspends itself again. This allows\r
+ prvChangePriorityWhenSuspendedTask() to know how many times it has\r
+ executed. */\r
+ ulPrioritySetCounter++;\r
+ vTaskSuspend( NULL );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Called to check that all the created tasks are still running without error. */\r
+portBASE_TYPE xAreDynamicPriorityTasksStillRunning( void )\r
+{\r
+/* Keep a history of the check variables so we know if it has been incremented \r
+since the last call. */\r
+static unsigned portSHORT usLastTaskCheck = ( unsigned portSHORT ) 0;\r
+portBASE_TYPE xReturn = pdTRUE;\r
+\r
+ /* Check the tasks are still running by ensuring the check variable\r
+ is still incrementing. */\r
+\r
+ if( usCheckVariable == usLastTaskCheck )\r
+ {\r
+ /* The check has not incremented so an error exists. */\r
+ xReturn = pdFALSE;\r
+ }\r
+\r
+ if( xSuspendedQueueSendError == pdTRUE )\r
+ {\r
+ xReturn = pdFALSE;\r
+ }\r
+\r
+ if( xSuspendedQueueReceiveError == pdTRUE )\r
+ {\r
+ xReturn = pdFALSE;\r
+ }\r
+\r
+ if( xPriorityRaiseWhenSuspendedError == pdTRUE )\r
+ {\r
+ xReturn = pdFALSE;\r
+ }\r
+\r
+ usLastTaskCheck = usCheckVariable;\r
+ return xReturn;\r
+}\r
+\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/**\r
+ * This file exercises the event mechanism whereby more than one task is\r
+ * blocked waiting for the same event.\r
+ *\r
+ * The demo creates five tasks - four 'event' tasks, and a controlling task.\r
+ * The event tasks have various different priorities and all block on reading\r
+ * the same queue. The controlling task writes data to the queue, then checks\r
+ * to see which of the event tasks read the data from the queue. The\r
+ * controlling task has the lowest priority of all the tasks so is guaranteed\r
+ * to always get preempted immediately upon writhing to the queue.\r
+ *\r
+ * By selectively suspending and resuming the event tasks the controlling task\r
+ * can check that the highest priority task that is blocked on the queue is the\r
+ * task that reads the posted data from the queue.\r
+ *\r
+ * Two of the event tasks share the same priority. When neither of these tasks\r
+ * are suspended they should alternate - one reading one message from the queue,\r
+ * the other the next message, etc.\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdlib.h>\r
+#include <stdio.h>\r
+#include <string.h>\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+\r
+/* Demo program include files. */\r
+#include "mevents.h"\r
+#include "print.h"\r
+\r
+/* Demo specific constants. */\r
+#define evtSTACK_SIZE ( ( unsigned portBASE_TYPE ) 128 )\r
+#define evtNUM_TASKS ( 4 )\r
+#define evtQUEUE_LENGTH ( ( unsigned portBASE_TYPE ) 3 )\r
+#define evtNO_DELAY 0\r
+\r
+/* Just indexes used to uniquely identify the tasks. Note that two tasks are\r
+'highest' priority. */\r
+#define evtHIGHEST_PRIORITY_INDEX_2 3\r
+#define evtHIGHEST_PRIORITY_INDEX_1 2\r
+#define evtMEDIUM_PRIORITY_INDEX 1\r
+#define evtLOWEST_PRIORITY_INDEX 0\r
+\r
+/* Each event task increments one of these counters each time it reads data\r
+from the queue. */\r
+static volatile portBASE_TYPE xTaskCounters[ evtNUM_TASKS ] = { 0, 0, 0, 0 };\r
+\r
+/* Each time the controlling task posts onto the queue it increments the \r
+expected count of the task that it expected to read the data from the queue \r
+(i.e. the task with the highest priority that should be blocked on the queue). \r
+\r
+xExpectedTaskCounters are incremented from the controlling task, and \r
+xTaskCounters are incremented from the individual event tasks - therefore\r
+comparing xTaskCounters to xExpectedTaskCounters shows whether or not the \r
+correct task was unblocked by the post. */\r
+static portBASE_TYPE xExpectedTaskCounters[ evtNUM_TASKS ] = { 0, 0, 0, 0 };\r
+\r
+/* Handles to the four event tasks. These are required to suspend and resume\r
+the tasks. */\r
+static xTaskHandle xCreatedTasks[ evtNUM_TASKS ];\r
+\r
+/* The single queue onto which the controlling task posts, and the four event\r
+tasks block. */\r
+static xQueueHandle xQueue;\r
+\r
+/* Flag used to indicate whether or not an error has occurred at any time.\r
+An error is either the queue being full when not expected, or an unexpected\r
+task reading data from the queue. */\r
+static portBASE_TYPE xHealthStatus = pdPASS;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Function that implements the event task. This is created four times. */\r
+static void prvMultiEventTask( void *pvParameters );\r
+\r
+/* Function that implements the controlling task. */\r
+static void prvEventControllerTask( void *pvParameters );\r
+\r
+/* This is a utility function that posts data to the queue, then compares \r
+xExpectedTaskCounters with xTaskCounters to ensure everything worked as \r
+expected.\r
+\r
+The event tasks all have higher priorities the controlling task. Therefore\r
+the controlling task will always get preempted between writhing to the queue\r
+and checking the task counters. \r
+\r
+@param xExpectedTask The index to the task that the controlling task thinks\r
+ should be the highest priority task waiting for data, and\r
+ therefore the task that will unblock.\r
+ \r
+@param xIncrement The number of items that should be written to the queue.\r
+*/\r
+static void prvCheckTaskCounters( portBASE_TYPE xExpectedTask, portBASE_TYPE xIncrement );\r
+\r
+/* This is just incremented each cycle of the controlling tasks function so\r
+the main application can ensure the test is still running. */\r
+static portBASE_TYPE xCheckVariable = 0;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vStartMultiEventTasks( void )\r
+{\r
+ /* Create the queue to be used for all the communications. */\r
+ xQueue = xQueueCreate( evtQUEUE_LENGTH, ( unsigned portBASE_TYPE ) sizeof( unsigned portBASE_TYPE ) );\r
+\r
+ /* Start the controlling task. This has the idle priority to ensure it is\r
+ always preempted by the event tasks. */\r
+ xTaskCreate( prvEventControllerTask, "EvntCTRL", evtSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );\r
+\r
+ /* Start the four event tasks. Note that two have priority 3, one \r
+ priority 2 and the other priority 1. */\r
+ xTaskCreate( prvMultiEventTask, "Event0", evtSTACK_SIZE, ( void * ) &( xTaskCounters[ 0 ] ), 1, &( xCreatedTasks[ evtLOWEST_PRIORITY_INDEX ] ) );\r
+ xTaskCreate( prvMultiEventTask, "Event1", evtSTACK_SIZE, ( void * ) &( xTaskCounters[ 1 ] ), 2, &( xCreatedTasks[ evtMEDIUM_PRIORITY_INDEX ] ) );\r
+ xTaskCreate( prvMultiEventTask, "Event2", evtSTACK_SIZE, ( void * ) &( xTaskCounters[ 2 ] ), 3, &( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] ) );\r
+ xTaskCreate( prvMultiEventTask, "Event3", evtSTACK_SIZE, ( void * ) &( xTaskCounters[ 3 ] ), 3, &( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_2 ] ) );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvMultiEventTask( void *pvParameters )\r
+{\r
+portBASE_TYPE *pxCounter;\r
+unsigned portBASE_TYPE uxDummy;\r
+const portCHAR * const pcTaskStartMsg = "Multi event task started.\r\n";\r
+\r
+ /* The variable this task will increment is passed in as a parameter. */\r
+ pxCounter = ( portBASE_TYPE * ) pvParameters;\r
+\r
+ vPrintDisplayMessage( &pcTaskStartMsg );\r
+\r
+ for( ;; )\r
+ {\r
+ /* Block on the queue. */\r
+ if( xQueueReceive( xQueue, &uxDummy, portMAX_DELAY ) )\r
+ {\r
+ /* We unblocked by reading the queue - so simply increment\r
+ the counter specific to this task instance. */\r
+ ( *pxCounter )++;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvEventControllerTask( void *pvParameters )\r
+{\r
+const portCHAR * const pcTaskStartMsg = "Multi event controller task started.\r\n";\r
+portBASE_TYPE xDummy = 0;\r
+\r
+ /* Just to stop warnings. */\r
+ ( void ) pvParameters;\r
+\r
+ vPrintDisplayMessage( &pcTaskStartMsg );\r
+\r
+ for( ;; )\r
+ {\r
+ /* All tasks are blocked on the queue. When a message is posted one of\r
+ the two tasks that share the highest priority should unblock to read\r
+ the queue. The next message written should unblock the other task with\r
+ the same high priority, and so on in order. No other task should \r
+ unblock to read data as they have lower priorities. */\r
+\r
+ prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 );\r
+ prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_2, 1 );\r
+ prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 );\r
+ prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_2, 1 );\r
+ prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 );\r
+\r
+ /* For the rest of these tests we don't need the second 'highest' \r
+ priority task - so it is suspended. */\r
+ vTaskSuspend( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_2 ] );\r
+\r
+\r
+\r
+ /* Now suspend the other highest priority task. The medium priority \r
+ task will then be the task with the highest priority that remains \r
+ blocked on the queue. */\r
+ vTaskSuspend( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] );\r
+ \r
+ /* This time, when we post onto the queue we will expect the medium\r
+ priority task to unblock and preempt us. */\r
+ prvCheckTaskCounters( evtMEDIUM_PRIORITY_INDEX, 1 );\r
+\r
+ /* Now try resuming the highest priority task while the scheduler is\r
+ suspended. The task should start executing as soon as the scheduler\r
+ is resumed - therefore when we post to the queue again, the highest\r
+ priority task should again preempt us. */\r
+ vTaskSuspendAll();\r
+ vTaskResume( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] );\r
+ xTaskResumeAll();\r
+ prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 );\r
+ \r
+ /* Now we are going to suspend the high and medium priority tasks. The\r
+ low priority task should then preempt us. Again the task suspension is \r
+ done with the whole scheduler suspended just for test purposes. */\r
+ vTaskSuspendAll();\r
+ vTaskSuspend( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] );\r
+ vTaskSuspend( xCreatedTasks[ evtMEDIUM_PRIORITY_INDEX ] );\r
+ xTaskResumeAll();\r
+ prvCheckTaskCounters( evtLOWEST_PRIORITY_INDEX, 1 );\r
+ \r
+ \r
+ \r
+ /* Do the same basic test another few times - selectively suspending\r
+ and resuming tasks and each time calling prvCheckTaskCounters() passing\r
+ to the function the number of the task we expected to be unblocked by \r
+ the post. */\r
+\r
+ vTaskResume( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] );\r
+ prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 );\r
+ \r
+ vTaskSuspendAll(); /* Just for test. */\r
+ vTaskSuspendAll(); /* Just for test. */\r
+ vTaskSuspendAll(); /* Just for even more test. */\r
+ vTaskSuspend( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] );\r
+ xTaskResumeAll();\r
+ xTaskResumeAll();\r
+ xTaskResumeAll();\r
+ prvCheckTaskCounters( evtLOWEST_PRIORITY_INDEX, 1 );\r
+ \r
+ vTaskResume( xCreatedTasks[ evtMEDIUM_PRIORITY_INDEX ] );\r
+ prvCheckTaskCounters( evtMEDIUM_PRIORITY_INDEX, 1 );\r
+ \r
+ vTaskResume( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] );\r
+ prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 );\r
+\r
+\r
+\r
+\r
+\r
+ /* Now a slight change, first suspend all tasks. */\r
+ vTaskSuspend( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] );\r
+ vTaskSuspend( xCreatedTasks[ evtMEDIUM_PRIORITY_INDEX ] );\r
+ vTaskSuspend( xCreatedTasks[ evtLOWEST_PRIORITY_INDEX ] );\r
+ \r
+ /* Now when we resume the low priority task and write to the queue 3 \r
+ times. We expect the low priority task to service the queue three\r
+ times. */\r
+ vTaskResume( xCreatedTasks[ evtLOWEST_PRIORITY_INDEX ] );\r
+ prvCheckTaskCounters( evtLOWEST_PRIORITY_INDEX, evtQUEUE_LENGTH );\r
+ \r
+ /* Again suspend all tasks (only the low priority task is not suspended\r
+ already). */\r
+ vTaskSuspend( xCreatedTasks[ evtLOWEST_PRIORITY_INDEX ] );\r
+ \r
+ /* This time we are going to suspend the scheduler, resume the low\r
+ priority task, then resume the high priority task. In this state we\r
+ will write to the queue three times. When the scheduler is resumed\r
+ we expect the high priority task to service all three messages. */\r
+ vTaskSuspendAll();\r
+ {\r
+ vTaskResume( xCreatedTasks[ evtLOWEST_PRIORITY_INDEX ] );\r
+ vTaskResume( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] );\r
+ \r
+ for( xDummy = 0; xDummy < evtQUEUE_LENGTH; xDummy++ )\r
+ {\r
+ if( xQueueSend( xQueue, &xDummy, evtNO_DELAY ) != pdTRUE )\r
+ {\r
+ xHealthStatus = pdFAIL;\r
+ }\r
+ } \r
+ \r
+ /* The queue should not have been serviced yet!. The scheduler\r
+ is still suspended. */\r
+ if( memcmp( ( void * ) xExpectedTaskCounters, ( void * ) xTaskCounters, sizeof( xExpectedTaskCounters ) ) )\r
+ {\r
+ xHealthStatus = pdFAIL;\r
+ }\r
+ }\r
+ xTaskResumeAll();\r
+ \r
+ /* We should have been preempted by resuming the scheduler - so by the\r
+ time we are running again we expect the high priority task to have \r
+ removed three items from the queue. */\r
+ xExpectedTaskCounters[ evtHIGHEST_PRIORITY_INDEX_1 ] += evtQUEUE_LENGTH;\r
+ if( memcmp( ( void * ) xExpectedTaskCounters, ( void * ) xTaskCounters, sizeof( xExpectedTaskCounters ) ) )\r
+ {\r
+ xHealthStatus = pdFAIL;\r
+ }\r
+ \r
+ /* The medium priority and second high priority tasks are still \r
+ suspended. Make sure to resume them before starting again. */\r
+ vTaskResume( xCreatedTasks[ evtMEDIUM_PRIORITY_INDEX ] );\r
+ vTaskResume( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_2 ] );\r
+\r
+ /* Just keep incrementing to show the task is still executing. */\r
+ xCheckVariable++;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCheckTaskCounters( portBASE_TYPE xExpectedTask, portBASE_TYPE xIncrement )\r
+{\r
+portBASE_TYPE xDummy = 0;\r
+\r
+ /* Write to the queue the requested number of times. The data written is\r
+ not important. */\r
+ for( xDummy = 0; xDummy < xIncrement; xDummy++ )\r
+ {\r
+ if( xQueueSend( xQueue, &xDummy, evtNO_DELAY ) != pdTRUE )\r
+ {\r
+ /* Did not expect to ever find the queue full. */\r
+ xHealthStatus = pdFAIL;\r
+ }\r
+ }\r
+\r
+ /* All the tasks blocked on the queue have a priority higher than the \r
+ controlling task. Writing to the queue will therefore have caused this\r
+ task to be preempted. By the time this line executes the event task will\r
+ have executed and incremented its counter. Increment the expected counter\r
+ to the same value. */\r
+ ( xExpectedTaskCounters[ xExpectedTask ] ) += xIncrement;\r
+\r
+ /* Check the actual counts and expected counts really are the same. */\r
+ if( memcmp( ( void * ) xExpectedTaskCounters, ( void * ) xTaskCounters, sizeof( xExpectedTaskCounters ) ) )\r
+ {\r
+ /* The counters were not the same. This means a task we did not expect\r
+ to unblock actually did unblock. */\r
+ xHealthStatus = pdFAIL;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portBASE_TYPE xAreMultiEventTasksStillRunning( void )\r
+{\r
+static portBASE_TYPE xPreviousCheckVariable = 0;\r
+\r
+ /* Called externally to periodically check that this test is still\r
+ operational. */\r
+\r
+ if( xPreviousCheckVariable == xCheckVariable )\r
+ {\r
+ xHealthStatus = pdFAIL;\r
+ }\r
+ \r
+ xPreviousCheckVariable = xCheckVariable;\r
+ \r
+ return xHealthStatus; \r
+}\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+\r
+/**\r
+ * Creates eight tasks, each of which flash an LED at a different rate. The first \r
+ * LED flashes every 125ms, the second every 250ms, the third every 375ms, etc.\r
+ *\r
+ * The LED flash tasks provide instant visual feedback. They show that the scheduler \r
+ * is still operational.\r
+ *\r
+ * The PC port uses the standard parallel port for outputs, the Flashlite 186 port \r
+ * uses IO port F.\r
+ *\r
+ * \page flashC flash.c\r
+ * \ingroup DemoFiles\r
+ * <HR>\r
+ */\r
+\r
+/*\r
+Changes from V2.0.0\r
+\r
+ + Delay periods are now specified using variables and constants of\r
+ portTickType rather than unsigned portLONG.\r
+\r
+Changes from V2.1.1\r
+\r
+ + The stack size now uses configMINIMAL_STACK_SIZE.\r
+ + String constants made file scope to decrease stack depth on 8051 port.\r
+*/\r
+\r
+#include <stdlib.h>\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo program include files. */\r
+#include "partest.h"\r
+#include "flash.h"\r
+#include "print.h"\r
+\r
+#define ledSTACK_SIZE configMINIMAL_STACK_SIZE\r
+\r
+/* Structure used to pass parameters to the LED tasks. */\r
+typedef struct LED_PARAMETERS\r
+{\r
+ unsigned portBASE_TYPE uxLED; /*< The output the task should use. */\r
+ portTickType xFlashRate; /*< The rate at which the LED should flash. */\r
+} xLEDParameters;\r
+\r
+/* The task that is created eight times - each time with a different xLEDParaemtes \r
+structure passed in as the parameter. */\r
+static void vLEDFlashTask( void *pvParameters );\r
+\r
+/* String to print if USE_STDIO is defined. */\r
+const portCHAR * const pcTaskStartMsg = "LED flash task started.\r\n";\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vStartLEDFlashTasks( unsigned portBASE_TYPE uxPriority )\r
+{\r
+unsigned portBASE_TYPE uxLEDTask;\r
+xLEDParameters *pxLEDParameters;\r
+const unsigned portBASE_TYPE uxNumOfLEDs = 8;\r
+const portTickType xFlashRate = 125;\r
+\r
+ /* Create the eight tasks. */\r
+ for( uxLEDTask = 0; uxLEDTask < uxNumOfLEDs; ++uxLEDTask )\r
+ {\r
+ /* Create and complete the structure used to pass parameters to the next \r
+ created task. */\r
+ pxLEDParameters = ( xLEDParameters * ) pvPortMalloc( sizeof( xLEDParameters ) );\r
+ pxLEDParameters->uxLED = uxLEDTask;\r
+ pxLEDParameters->xFlashRate = ( xFlashRate + ( xFlashRate * ( portTickType ) uxLEDTask ) );\r
+ pxLEDParameters->xFlashRate /= portTICK_RATE_MS;\r
+\r
+ /* Spawn the task. */\r
+ xTaskCreate( vLEDFlashTask, "LEDx", ledSTACK_SIZE, ( void * ) pxLEDParameters, uxPriority, ( xTaskHandle * ) NULL );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vLEDFlashTask( void *pvParameters )\r
+{\r
+xLEDParameters *pxParameters;\r
+\r
+ /* Queue a message for printing to say the task has started. */\r
+ vPrintDisplayMessage( &pcTaskStartMsg );\r
+\r
+ pxParameters = ( xLEDParameters * ) pvParameters;\r
+\r
+ for(;;)\r
+ {\r
+ /* Delay for half the flash period then turn the LED on. */\r
+ vTaskDelay( pxParameters->xFlashRate / ( portTickType ) 2 );\r
+ vParTestToggleLED( pxParameters->uxLED );\r
+\r
+ /* Delay for half the flash period then turn the LED off. */\r
+ vTaskDelay( pxParameters->xFlashRate / ( portTickType ) 2 );\r
+ vParTestToggleLED( pxParameters->uxLED );\r
+ }\r
+}\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+Changes from V1.2.3\r
+ \r
+ + The created tasks now include calls to tskYIELD(), allowing them to be used\r
+ with the cooperative scheduler.\r
+*/\r
+\r
+/**\r
+ * Creates eight tasks, each of which loops continuously performing an (emulated) \r
+ * floating point calculation.\r
+ *\r
+ * All the tasks run at the idle priority and never block or yield. This causes \r
+ * all eight tasks to time slice with the idle task. Running at the idle priority \r
+ * means that these tasks will get pre-empted any time another task is ready to run\r
+ * or a time slice occurs. More often than not the pre-emption will occur mid \r
+ * calculation, creating a good test of the schedulers context switch mechanism - a \r
+ * calculation producing an unexpected result could be a symptom of a corruption in \r
+ * the context of a task.\r
+ *\r
+ * \page FlopC flop.c\r
+ * \ingroup DemoFiles\r
+ * <HR>\r
+ */\r
+\r
+#include <stdlib.h>\r
+#include <math.h>\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "print.h"\r
+\r
+/* Demo program include files. */\r
+#include "flop.h"\r
+\r
+#define mathSTACK_SIZE ( ( unsigned portSHORT ) 512 )\r
+#define mathNUMBER_OF_TASKS ( 8 )\r
+\r
+/* Four tasks, each of which performs a different floating point calculation. \r
+Each of the four is created twice. */\r
+static void vCompetingMathTask1( void *pvParameters );\r
+static void vCompetingMathTask2( void *pvParameters );\r
+static void vCompetingMathTask3( void *pvParameters );\r
+static void vCompetingMathTask4( void *pvParameters );\r
+\r
+/* These variables are used to check that all the tasks are still running. If a \r
+task gets a calculation wrong it will\r
+stop incrementing its check variable. */\r
+static volatile unsigned portSHORT usTaskCheck[ mathNUMBER_OF_TASKS ] = { ( unsigned portSHORT ) 0 };\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vStartMathTasks( unsigned portBASE_TYPE uxPriority )\r
+{\r
+ xTaskCreate( vCompetingMathTask1, "Math1", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 0 ] ), uxPriority, NULL );\r
+ xTaskCreate( vCompetingMathTask2, "Math2", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 1 ] ), uxPriority, NULL );\r
+ xTaskCreate( vCompetingMathTask3, "Math3", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 2 ] ), uxPriority, NULL );\r
+ xTaskCreate( vCompetingMathTask4, "Math4", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 3 ] ), uxPriority, NULL );\r
+ xTaskCreate( vCompetingMathTask1, "Math5", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 4 ] ), uxPriority, NULL );\r
+ xTaskCreate( vCompetingMathTask2, "Math6", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 5 ] ), uxPriority, NULL );\r
+ xTaskCreate( vCompetingMathTask3, "Math7", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 6 ] ), uxPriority, NULL );\r
+ xTaskCreate( vCompetingMathTask4, "Math8", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 7 ] ), uxPriority, NULL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vCompetingMathTask1( void *pvParameters )\r
+{\r
+portDOUBLE d1, d2, d3, d4;\r
+volatile unsigned portSHORT *pusTaskCheckVariable;\r
+const portDOUBLE dAnswer = ( 123.4567 + 2345.6789 ) * -918.222;\r
+const portCHAR * const pcTaskStartMsg = "Math task 1 started.\r\n";\r
+const portCHAR * const pcTaskFailMsg = "Math task 1 failed.\r\n";\r
+portSHORT sError = pdFALSE;\r
+\r
+ /* Queue a message for printing to say the task has started. */\r
+ vPrintDisplayMessage( &pcTaskStartMsg );\r
+\r
+ /* The variable this task increments to show it is still running is passed in \r
+ as the parameter. */\r
+ pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters;\r
+\r
+ /* Keep performing a calculation and checking the result against a constant. */\r
+ for(;;)\r
+ {\r
+ d1 = 123.4567;\r
+ d2 = 2345.6789;\r
+ d3 = -918.222;\r
+\r
+ d4 = ( d1 + d2 ) * d3;\r
+\r
+ taskYIELD();\r
+\r
+ /* If the calculation does not match the expected constant, stop the \r
+ increment of the check variable. */\r
+ if( fabs( d4 - dAnswer ) > 0.001 )\r
+ {\r
+ vPrintDisplayMessage( &pcTaskFailMsg );\r
+ sError = pdTRUE;\r
+ }\r
+\r
+ if( sError == pdFALSE )\r
+ {\r
+ /* If the calculation has always been correct, increment the check \r
+ variable so we know this task is still running okay. */\r
+ ( *pusTaskCheckVariable )++;\r
+ }\r
+\r
+ taskYIELD();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vCompetingMathTask2( void *pvParameters )\r
+{\r
+portDOUBLE d1, d2, d3, d4;\r
+volatile unsigned portSHORT *pusTaskCheckVariable;\r
+const portDOUBLE dAnswer = ( -389.38 / 32498.2 ) * -2.0001;\r
+const portCHAR * const pcTaskStartMsg = "Math task 2 started.\r\n";\r
+const portCHAR * const pcTaskFailMsg = "Math task 2 failed.\r\n";\r
+portSHORT sError = pdFALSE;\r
+\r
+ /* Queue a message for printing to say the task has started. */\r
+ vPrintDisplayMessage( &pcTaskStartMsg );\r
+\r
+ /* The variable this task increments to show it is still running is passed in \r
+ as the parameter. */\r
+ pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters;\r
+\r
+ /* Keep performing a calculation and checking the result against a constant. */\r
+ for( ;; )\r
+ {\r
+ d1 = -389.38;\r
+ d2 = 32498.2;\r
+ d3 = -2.0001;\r
+\r
+ d4 = ( d1 / d2 ) * d3;\r
+\r
+ taskYIELD();\r
+ \r
+ /* If the calculation does not match the expected constant, stop the \r
+ increment of the check variable. */\r
+ if( fabs( d4 - dAnswer ) > 0.001 )\r
+ {\r
+ vPrintDisplayMessage( &pcTaskFailMsg );\r
+ sError = pdTRUE;\r
+ }\r
+\r
+ if( sError == pdFALSE )\r
+ {\r
+ /* If the calculation has always been correct, increment the check \r
+ variable so we know\r
+ this task is still running okay. */\r
+ ( *pusTaskCheckVariable )++;\r
+ }\r
+\r
+ taskYIELD();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vCompetingMathTask3( void *pvParameters )\r
+{\r
+portDOUBLE *pdArray, dTotal1, dTotal2, dDifference;\r
+volatile unsigned portSHORT *pusTaskCheckVariable;\r
+const unsigned portSHORT usArraySize = 250;\r
+unsigned portSHORT usPosition;\r
+const portCHAR * const pcTaskStartMsg = "Math task 3 started.\r\n";\r
+const portCHAR * const pcTaskFailMsg = "Math task 3 failed.\r\n";\r
+portSHORT sError = pdFALSE;\r
+\r
+ /* Queue a message for printing to say the task has started. */\r
+ vPrintDisplayMessage( &pcTaskStartMsg );\r
+\r
+ /* The variable this task increments to show it is still running is passed in \r
+ as the parameter. */\r
+ pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters;\r
+\r
+ pdArray = ( portDOUBLE * ) pvPortMalloc( ( size_t ) 250 * sizeof( portDOUBLE ) );\r
+\r
+ /* Keep filling an array, keeping a running total of the values placed in the \r
+ array. Then run through the array adding up all the values. If the two totals \r
+ do not match, stop the check variable from incrementing. */\r
+ for( ;; )\r
+ {\r
+ dTotal1 = 0.0;\r
+ dTotal2 = 0.0;\r
+\r
+ for( usPosition = 0; usPosition < usArraySize; usPosition++ )\r
+ {\r
+ pdArray[ usPosition ] = ( portDOUBLE ) usPosition + 5.5;\r
+ dTotal1 += ( portDOUBLE ) usPosition + 5.5; \r
+ }\r
+\r
+ taskYIELD();\r
+\r
+ for( usPosition = 0; usPosition < usArraySize; usPosition++ )\r
+ {\r
+ dTotal2 += pdArray[ usPosition ];\r
+ }\r
+\r
+ dDifference = dTotal1 - dTotal2;\r
+ if( fabs( dDifference ) > 0.001 )\r
+ {\r
+ vPrintDisplayMessage( &pcTaskFailMsg );\r
+ sError = pdTRUE;\r
+ }\r
+\r
+ taskYIELD();\r
+\r
+ if( sError == pdFALSE )\r
+ {\r
+ /* If the calculation has always been correct, increment the check \r
+ variable so we know this task is still running okay. */\r
+ ( *pusTaskCheckVariable )++;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vCompetingMathTask4( void *pvParameters )\r
+{\r
+portDOUBLE *pdArray, dTotal1, dTotal2, dDifference;\r
+volatile unsigned portSHORT *pusTaskCheckVariable;\r
+const unsigned portSHORT usArraySize = 250;\r
+unsigned portSHORT usPosition;\r
+const portCHAR * const pcTaskStartMsg = "Math task 4 started.\r\n";\r
+const portCHAR * const pcTaskFailMsg = "Math task 4 failed.\r\n";\r
+portSHORT sError = pdFALSE;\r
+\r
+ /* Queue a message for printing to say the task has started. */\r
+ vPrintDisplayMessage( &pcTaskStartMsg );\r
+\r
+ /* The variable this task increments to show it is still running is passed in \r
+ as the parameter. */\r
+ pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters;\r
+\r
+ pdArray = ( portDOUBLE * ) pvPortMalloc( ( size_t ) 250 * sizeof( portDOUBLE ) );\r
+\r
+ /* Keep filling an array, keeping a running total of the values placed in the \r
+ array. Then run through the array adding up all the values. If the two totals \r
+ do not match, stop the check variable from incrementing. */\r
+ for( ;; )\r
+ {\r
+ dTotal1 = 0.0;\r
+ dTotal2 = 0.0;\r
+\r
+ for( usPosition = 0; usPosition < usArraySize; usPosition++ )\r
+ {\r
+ pdArray[ usPosition ] = ( portDOUBLE ) usPosition * 12.123;\r
+ dTotal1 += ( portDOUBLE ) usPosition * 12.123; \r
+ }\r
+\r
+ taskYIELD();\r
+\r
+ for( usPosition = 0; usPosition < usArraySize; usPosition++ )\r
+ {\r
+ dTotal2 += pdArray[ usPosition ];\r
+ }\r
+\r
+ dDifference = dTotal1 - dTotal2;\r
+ if( fabs( dDifference ) > 0.001 )\r
+ {\r
+ vPrintDisplayMessage( &pcTaskFailMsg );\r
+ sError = pdTRUE;\r
+ }\r
+\r
+ taskYIELD();\r
+\r
+ if( sError == pdFALSE )\r
+ {\r
+ /* If the calculation has always been correct, increment the check \r
+ variable so we know this task is still running okay. */\r
+ ( *pusTaskCheckVariable )++;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This is called to check that all the created tasks are still running. */\r
+portBASE_TYPE xAreMathsTaskStillRunning( void )\r
+{\r
+/* Keep a history of the check variables so we know if they have been incremented \r
+since the last call. */\r
+static unsigned portSHORT usLastTaskCheck[ mathNUMBER_OF_TASKS ] = { ( unsigned portSHORT ) 0 };\r
+portBASE_TYPE xReturn = pdTRUE, xTask;\r
+\r
+ /* Check the maths tasks are still running by ensuring their check variables \r
+ are still incrementing. */\r
+ for( xTask = 0; xTask < mathNUMBER_OF_TASKS; xTask++ )\r
+ {\r
+ if( usTaskCheck[ xTask ] == usLastTaskCheck[ xTask ] )\r
+ {\r
+ /* The check has not incremented so an error exists. */\r
+ xReturn = pdFALSE;\r
+ }\r
+\r
+ usLastTaskCheck[ xTask ] = usTaskCheck[ xTask ];\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+Changes from V1.2.3\r
+ \r
+ + The created tasks now include calls to tskYIELD(), allowing them to be used\r
+ with the cooperative scheduler.\r
+*/\r
+\r
+/**\r
+ * This does the same as flop. c, but uses variables of type long instead of \r
+ * type double. \r
+ *\r
+ * As with flop. c, the tasks created in this file are a good test of the \r
+ * scheduler context switch mechanism. The processor has to access 32bit \r
+ * variables in two or four chunks (depending on the processor). The low \r
+ * priority of these tasks means there is a high probability that a context \r
+ * switch will occur mid calculation. See the flop. c documentation for \r
+ * more information.\r
+ *\r
+ * \page IntegerC integer.c\r
+ * \ingroup DemoFiles\r
+ * <HR>\r
+ */\r
+\r
+/*\r
+Changes from V1.2.1\r
+\r
+ + The constants used in the calculations are larger to ensure the\r
+ optimiser does not truncate them to 16 bits.\r
+*/\r
+\r
+#include <stdlib.h>\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "print.h"\r
+\r
+/* Demo program include files. */\r
+#include "integer.h"\r
+\r
+#define intgSTACK_SIZE ( ( unsigned portSHORT ) 256 )\r
+#define intgNUMBER_OF_TASKS ( 8 )\r
+\r
+/* Four tasks, each of which performs a different calculation on four byte \r
+variables. Each of the four is created twice. */\r
+static void vCompeteingIntMathTask1( void *pvParameters );\r
+static void vCompeteingIntMathTask2( void *pvParameters );\r
+static void vCompeteingIntMathTask3( void *pvParameters );\r
+static void vCompeteingIntMathTask4( void *pvParameters );\r
+\r
+/* These variables are used to check that all the tasks are still running. If a \r
+task gets a calculation wrong it will stop incrementing its check variable. */\r
+static volatile unsigned portSHORT usTaskCheck[ intgNUMBER_OF_TASKS ] = { ( unsigned portSHORT ) 0 };\r
+/*-----------------------------------------------------------*/\r
+\r
+void vStartIntegerMathTasks( unsigned portBASE_TYPE uxPriority )\r
+{\r
+ xTaskCreate( vCompeteingIntMathTask1, "IntMath1", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 0 ] ), uxPriority, NULL );\r
+ xTaskCreate( vCompeteingIntMathTask2, "IntMath2", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 1 ] ), uxPriority, NULL );\r
+ xTaskCreate( vCompeteingIntMathTask3, "IntMath3", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 2 ] ), uxPriority, NULL );\r
+ xTaskCreate( vCompeteingIntMathTask4, "IntMath4", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 3 ] ), uxPriority, NULL );\r
+ xTaskCreate( vCompeteingIntMathTask1, "IntMath5", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 4 ] ), uxPriority, NULL );\r
+ xTaskCreate( vCompeteingIntMathTask2, "IntMath6", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 5 ] ), uxPriority, NULL );\r
+ xTaskCreate( vCompeteingIntMathTask3, "IntMath7", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 6 ] ), uxPriority, NULL );\r
+ xTaskCreate( vCompeteingIntMathTask4, "IntMath8", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 7 ] ), uxPriority, NULL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vCompeteingIntMathTask1( void *pvParameters )\r
+{\r
+portLONG l1, l2, l3, l4;\r
+portSHORT sError = pdFALSE;\r
+volatile unsigned portSHORT *pusTaskCheckVariable;\r
+const portLONG lAnswer = ( ( portLONG ) 74565L + ( portLONG ) 1234567L ) * ( portLONG ) -918L;\r
+const portCHAR * const pcTaskStartMsg = "Integer math task 1 started.\r\n";\r
+const portCHAR * const pcTaskFailMsg = "Integer math task 1 failed.\r\n";\r
+\r
+ /* Queue a message for printing to say the task has started. */\r
+ vPrintDisplayMessage( &pcTaskStartMsg );\r
+\r
+ /* The variable this task increments to show it is still running is passed in\r
+ as the parameter. */\r
+ pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters;\r
+\r
+ /* Keep performing a calculation and checking the result against a constant. */\r
+ for(;;)\r
+ {\r
+ l1 = ( portLONG ) 74565L;\r
+ l2 = ( portLONG ) 1234567L;\r
+ l3 = ( portLONG ) -918L;\r
+\r
+ l4 = ( l1 + l2 ) * l3;\r
+\r
+ taskYIELD();\r
+\r
+ /* If the calculation does not match the expected constant, stop the\r
+ increment of the check variable. */\r
+ if( l4 != lAnswer )\r
+ {\r
+ vPrintDisplayMessage( &pcTaskFailMsg );\r
+ sError = pdTRUE;\r
+ }\r
+\r
+ if( sError == pdFALSE )\r
+ {\r
+ /* If the calculation has always been correct, increment the check\r
+ variable so we know this task is still running okay. */\r
+ ( *pusTaskCheckVariable )++;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vCompeteingIntMathTask2( void *pvParameters )\r
+{\r
+portLONG l1, l2, l3, l4;\r
+portSHORT sError = pdFALSE;\r
+volatile unsigned portSHORT *pusTaskCheckVariable;\r
+const portLONG lAnswer = ( ( portLONG ) -389000L / ( portLONG ) 329999L ) * ( portLONG ) -89L;\r
+const portCHAR * const pcTaskStartMsg = "Integer math task 2 started.\r\n";\r
+const portCHAR * const pcTaskFailMsg = "Integer math task 2 failed.\r\n";\r
+\r
+ /* Queue a message for printing to say the task has started. */\r
+ vPrintDisplayMessage( &pcTaskStartMsg );\r
+\r
+ /* The variable this task increments to show it is still running is passed in\r
+ as the parameter. */\r
+ pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters;\r
+\r
+ /* Keep performing a calculation and checking the result against a constant. */\r
+ for( ;; )\r
+ {\r
+ l1 = -389000L;\r
+ l2 = 329999L;\r
+ l3 = -89L;\r
+\r
+ l4 = ( l1 / l2 ) * l3;\r
+\r
+ taskYIELD();\r
+\r
+ /* If the calculation does not match the expected constant, stop the\r
+ increment of the check variable. */\r
+ if( l4 != lAnswer )\r
+ {\r
+ vPrintDisplayMessage( &pcTaskFailMsg );\r
+ sError = pdTRUE;\r
+ }\r
+\r
+ if( sError == pdFALSE )\r
+ {\r
+ /* If the calculation has always been correct, increment the check\r
+ variable so we know this task is still running okay. */\r
+ ( *pusTaskCheckVariable )++;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vCompeteingIntMathTask3( void *pvParameters )\r
+{\r
+portLONG *plArray, lTotal1, lTotal2;\r
+portSHORT sError = pdFALSE;\r
+volatile unsigned portSHORT *pusTaskCheckVariable;\r
+const unsigned portSHORT usArraySize = ( unsigned portSHORT ) 250;\r
+unsigned portSHORT usPosition;\r
+const portCHAR * const pcTaskStartMsg = "Integer math task 3 started.\r\n";\r
+const portCHAR * const pcTaskFailMsg = "Integer math task 3 failed.\r\n";\r
+\r
+ /* Queue a message for printing to say the task has started. */\r
+ vPrintDisplayMessage( &pcTaskStartMsg );\r
+\r
+ /* The variable this task increments to show it is still running is passed in\r
+ as the parameter. */\r
+ pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters;\r
+\r
+ /* Create the array we are going to use for our check calculation. */\r
+ plArray = ( portLONG * ) pvPortMalloc( ( size_t ) 250 * sizeof( portLONG ) );\r
+\r
+ /* Keep filling the array, keeping a running total of the values placed in the\r
+ array. Then run through the array adding up all the values. If the two totals\r
+ do not match, stop the check variable from incrementing. */\r
+ for( ;; )\r
+ {\r
+ lTotal1 = ( portLONG ) 0;\r
+ lTotal2 = ( portLONG ) 0;\r
+\r
+ for( usPosition = 0; usPosition < usArraySize; usPosition++ )\r
+ {\r
+ plArray[ usPosition ] = ( portLONG ) usPosition + ( portLONG ) 5;\r
+ lTotal1 += ( portLONG ) usPosition + ( portLONG ) 5;\r
+ }\r
+\r
+ taskYIELD();\r
+\r
+ for( usPosition = 0; usPosition < usArraySize; usPosition++ )\r
+ {\r
+ lTotal2 += plArray[ usPosition ];\r
+ }\r
+\r
+ if( lTotal1 != lTotal2 )\r
+ {\r
+ vPrintDisplayMessage( &pcTaskFailMsg );\r
+ sError = pdTRUE;\r
+ }\r
+\r
+ taskYIELD();\r
+\r
+ if( sError == pdFALSE )\r
+ {\r
+ /* If the calculation has always been correct, increment the check\r
+ variable so we know this task is still running okay. */\r
+ ( *pusTaskCheckVariable )++;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vCompeteingIntMathTask4( void *pvParameters )\r
+{\r
+portLONG *plArray, lTotal1, lTotal2;\r
+portSHORT sError = pdFALSE;\r
+volatile unsigned portSHORT *pusTaskCheckVariable;\r
+const unsigned portSHORT usArraySize = 250;\r
+unsigned portSHORT usPosition;\r
+const portCHAR * const pcTaskStartMsg = "Integer math task 4 started.\r\n";\r
+const portCHAR * const pcTaskFailMsg = "Integer math task 4 failed.\r\n";\r
+\r
+ /* Queue a message for printing to say the task has started. */\r
+ vPrintDisplayMessage( &pcTaskStartMsg );\r
+\r
+ /* The variable this task increments to show it is still running is passed in\r
+ as the parameter. */\r
+ pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters;\r
+\r
+ /* Create the array we are going to use for our check calculation. */\r
+ plArray = ( portLONG * ) pvPortMalloc( ( size_t ) 250 * sizeof( portLONG ) );\r
+\r
+ /* Keep filling the array, keeping a running total of the values placed in the \r
+ array. Then run through the array adding up all the values. If the two totals \r
+ do not match, stop the check variable from incrementing. */\r
+ for( ;; )\r
+ {\r
+ lTotal1 = ( portLONG ) 0;\r
+ lTotal2 = ( portLONG ) 0;\r
+\r
+ for( usPosition = 0; usPosition < usArraySize; usPosition++ )\r
+ {\r
+ plArray[ usPosition ] = ( portLONG ) usPosition * ( portLONG ) 12;\r
+ lTotal1 += ( portLONG ) usPosition * ( portLONG ) 12; \r
+ }\r
+\r
+ taskYIELD();\r
+ \r
+ for( usPosition = 0; usPosition < usArraySize; usPosition++ )\r
+ {\r
+ lTotal2 += plArray[ usPosition ];\r
+ }\r
+\r
+\r
+ if( lTotal1 != lTotal2 )\r
+ {\r
+ vPrintDisplayMessage( &pcTaskFailMsg );\r
+ sError = pdTRUE;\r
+ }\r
+\r
+ taskYIELD();\r
+\r
+ if( sError == pdFALSE )\r
+ {\r
+ /* If the calculation has always been correct, increment the check \r
+ variable so we know this task is still running okay. */\r
+ ( *pusTaskCheckVariable )++;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This is called to check that all the created tasks are still running. */\r
+portBASE_TYPE xAreIntegerMathsTaskStillRunning( void )\r
+{\r
+/* Keep a history of the check variables so we know if they have been incremented \r
+since the last call. */\r
+static unsigned portSHORT usLastTaskCheck[ intgNUMBER_OF_TASKS ] = { ( unsigned portSHORT ) 0 };\r
+portBASE_TYPE xReturn = pdTRUE, xTask;\r
+\r
+ /* Check the maths tasks are still running by ensuring their check variables \r
+ are still incrementing. */\r
+ for( xTask = 0; xTask < intgNUMBER_OF_TASKS; xTask++ )\r
+ {\r
+ if( usTaskCheck[ xTask ] == usLastTaskCheck[ xTask ] )\r
+ {\r
+ /* The check has not incremented so an error exists. */\r
+ xReturn = pdFALSE;\r
+ }\r
+\r
+ usLastTaskCheck[ xTask ] = usTaskCheck[ xTask ];\r
+ }\r
+\r
+ return xReturn;\r
+}\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/**\r
+ * Manages a queue of strings that are waiting to be displayed. This is used to \r
+ * ensure mutual exclusion of console output.\r
+ *\r
+ * A task wishing to display a message will call vPrintDisplayMessage (), with a \r
+ * pointer to the string as the parameter. The pointer is posted onto the \r
+ * xPrintQueue queue.\r
+ *\r
+ * The task spawned in main. c blocks on xPrintQueue. When a message becomes \r
+ * available it calls pcPrintGetNextMessage () to obtain a pointer to the next \r
+ * string, then uses the functions defined in the portable layer FileIO. c to \r
+ * display the message.\r
+ *\r
+ * <b>NOTE:</b>\r
+ * Using console IO can disrupt real time performance - depending on the port. \r
+ * Standard C IO routines are not designed for real time applications. While \r
+ * standard IO is useful for demonstration and debugging an alternative method \r
+ * should be used if you actually require console IO as part of your application.\r
+ *\r
+ * \page PrintC print.c\r
+ * \ingroup DemoFiles\r
+ * <HR>\r
+ */\r
+\r
+/*\r
+Changes from V2.0.0\r
+\r
+ + Delay periods are now specified using variables and constants of\r
+ portTickType rather than unsigned portLONG.\r
+*/\r
+\r
+#include <stdlib.h>\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "queue.h"\r
+\r
+/* Demo program include files. */\r
+#include "print.h"\r
+\r
+static xQueueHandle xPrintQueue;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPrintInitialise( void )\r
+{\r
+const unsigned portBASE_TYPE uxQueueSize = 20;\r
+\r
+ /* Create the queue on which errors will be reported. */\r
+ xPrintQueue = xQueueCreate( uxQueueSize, ( unsigned portBASE_TYPE ) sizeof( portCHAR * ) );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPrintDisplayMessage( const portCHAR * const * ppcMessageToSend )\r
+{\r
+ #ifdef USE_STDIO\r
+ xQueueSend( xPrintQueue, ( void * ) ppcMessageToSend, ( portTickType ) 0 );\r
+ #else\r
+ /* Stop warnings. */\r
+ ( void ) ppcMessageToSend;\r
+ #endif\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+const portCHAR *pcPrintGetNextMessage( portTickType xPrintRate )\r
+{\r
+portCHAR *pcMessage;\r
+\r
+ if( xQueueReceive( xPrintQueue, &pcMessage, xPrintRate ) == pdPASS )\r
+ {\r
+ return pcMessage;\r
+ }\r
+ else\r
+ {\r
+ return NULL;\r
+ }\r
+}\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/**\r
+ * Creates two sets of two tasks. The tasks within a set share a variable, access \r
+ * to which is guarded by a semaphore.\r
+ * \r
+ * Each task starts by attempting to obtain the semaphore. On obtaining a \r
+ * semaphore a task checks to ensure that the guarded variable has an expected \r
+ * value. It then clears the variable to zero before counting it back up to the \r
+ * expected value in increments of 1. After each increment the variable is checked \r
+ * to ensure it contains the value to which it was just set. When the starting \r
+ * value is again reached the task releases the semaphore giving the other task in \r
+ * the set a chance to do exactly the same thing. The starting value is high \r
+ * enough to ensure that a tick is likely to occur during the incrementing loop.\r
+ *\r
+ * An error is flagged if at any time during the process a shared variable is \r
+ * found to have a value other than that expected. Such an occurrence would \r
+ * suggest an error in the mutual exclusion mechanism by which access to the \r
+ * variable is restricted.\r
+ *\r
+ * The first set of two tasks poll their semaphore. The second set use blocking \r
+ * calls.\r
+ *\r
+ * \page SemTestC semtest.c\r
+ * \ingroup DemoFiles\r
+ * <HR>\r
+ */\r
+\r
+/*\r
+Changes from V1.2.0:\r
+\r
+ + The tasks that operate at the idle priority now use a lower expected\r
+ count than those running at a higher priority. This prevents the low\r
+ priority tasks from signaling an error because they have not been \r
+ scheduled enough time for each of them to count the shared variable to\r
+ the high value.\r
+\r
+Changes from V2.0.0\r
+\r
+ + Delay periods are now specified using variables and constants of\r
+ portTickType rather than unsigned portLONG.\r
+\r
+Changes from V2.1.1\r
+\r
+ + The stack size now uses configMINIMAL_STACK_SIZE.\r
+ + String constants made file scope to decrease stack depth on 8051 port.\r
+*/\r
+\r
+#include <stdlib.h>\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "semphr.h"\r
+\r
+/* Demo app include files. */\r
+#include "semtest.h"\r
+#include "print.h"\r
+\r
+/* The value to which the shared variables are counted. */\r
+#define semtstBLOCKING_EXPECTED_VALUE ( ( unsigned portLONG ) 0xfff )\r
+#define semtstNON_BLOCKING_EXPECTED_VALUE ( ( unsigned portLONG ) 0xff )\r
+\r
+#define semtstSTACK_SIZE configMINIMAL_STACK_SIZE\r
+\r
+#define semtstNUM_TASKS ( 4 )\r
+\r
+#define semtstDELAY_FACTOR ( ( portTickType ) 10 )\r
+\r
+/* The task function as described at the top of the file. */\r
+static void prvSemaphoreTest( void *pvParameters );\r
+\r
+/* Structure used to pass parameters to each task. */\r
+typedef struct SEMAPHORE_PARAMETERS\r
+{\r
+ xSemaphoreHandle xSemaphore;\r
+ volatile unsigned portLONG *pulSharedVariable;\r
+ portTickType xBlockTime;\r
+} xSemaphoreParameters;\r
+\r
+/* Variables used to check that all the tasks are still running without errors. */\r
+static volatile portSHORT sCheckVariables[ semtstNUM_TASKS ] = { 0 };\r
+static volatile portSHORT sNextCheckVariable = 0;\r
+\r
+/* Strings to print if USE_STDIO is defined. */\r
+const portCHAR * const pcPollingSemaphoreTaskError = "Guarded shared variable in unexpected state.\r\n";\r
+const portCHAR * const pcSemaphoreTaskStart = "Guarded shared variable task started.\r\n";\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vStartSemaphoreTasks( unsigned portBASE_TYPE uxPriority )\r
+{\r
+xSemaphoreParameters *pxFirstSemaphoreParameters, *pxSecondSemaphoreParameters;\r
+const portTickType xBlockTime = ( portTickType ) 100;\r
+\r
+ /* Create the structure used to pass parameters to the first two tasks. */\r
+ pxFirstSemaphoreParameters = ( xSemaphoreParameters * ) pvPortMalloc( sizeof( xSemaphoreParameters ) );\r
+\r
+ if( pxFirstSemaphoreParameters != NULL )\r
+ {\r
+ /* Create the semaphore used by the first two tasks. */\r
+ vSemaphoreCreateBinary( pxFirstSemaphoreParameters->xSemaphore );\r
+\r
+ if( pxFirstSemaphoreParameters->xSemaphore != NULL )\r
+ {\r
+ /* Create the variable which is to be shared by the first two tasks. */\r
+ pxFirstSemaphoreParameters->pulSharedVariable = ( unsigned portLONG * ) pvPortMalloc( sizeof( unsigned portLONG ) );\r
+\r
+ /* Initialise the share variable to the value the tasks expect. */\r
+ *( pxFirstSemaphoreParameters->pulSharedVariable ) = semtstNON_BLOCKING_EXPECTED_VALUE;\r
+\r
+ /* The first two tasks do not block on semaphore calls. */\r
+ pxFirstSemaphoreParameters->xBlockTime = ( portTickType ) 0;\r
+\r
+ /* Spawn the first two tasks. As they poll they operate at the idle priority. */\r
+ xTaskCreate( prvSemaphoreTest, "PolSEM1", semtstSTACK_SIZE, ( void * ) pxFirstSemaphoreParameters, tskIDLE_PRIORITY, ( xTaskHandle * ) NULL );\r
+ xTaskCreate( prvSemaphoreTest, "PolSEM2", semtstSTACK_SIZE, ( void * ) pxFirstSemaphoreParameters, tskIDLE_PRIORITY, ( xTaskHandle * ) NULL );\r
+ }\r
+ }\r
+\r
+ /* Do exactly the same to create the second set of tasks, only this time \r
+ provide a block time for the semaphore calls. */\r
+ pxSecondSemaphoreParameters = ( xSemaphoreParameters * ) pvPortMalloc( sizeof( xSemaphoreParameters ) );\r
+ if( pxSecondSemaphoreParameters != NULL )\r
+ {\r
+ vSemaphoreCreateBinary( pxSecondSemaphoreParameters->xSemaphore );\r
+\r
+ if( pxSecondSemaphoreParameters->xSemaphore != NULL )\r
+ {\r
+ pxSecondSemaphoreParameters->pulSharedVariable = ( unsigned portLONG * ) pvPortMalloc( sizeof( unsigned portLONG ) );\r
+ *( pxSecondSemaphoreParameters->pulSharedVariable ) = semtstBLOCKING_EXPECTED_VALUE;\r
+ pxSecondSemaphoreParameters->xBlockTime = xBlockTime / portTICK_RATE_MS;\r
+\r
+ xTaskCreate( prvSemaphoreTest, "BlkSEM1", semtstSTACK_SIZE, ( void * ) pxSecondSemaphoreParameters, uxPriority, ( xTaskHandle * ) NULL );\r
+ xTaskCreate( prvSemaphoreTest, "BlkSEM2", semtstSTACK_SIZE, ( void * ) pxSecondSemaphoreParameters, uxPriority, ( xTaskHandle * ) NULL );\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSemaphoreTest( void *pvParameters )\r
+{\r
+xSemaphoreParameters *pxParameters;\r
+volatile unsigned portLONG *pulSharedVariable, ulExpectedValue;\r
+unsigned portLONG ulCounter;\r
+portSHORT sError = pdFALSE, sCheckVariableToUse;\r
+\r
+ /* See which check variable to use. sNextCheckVariable is not semaphore \r
+ protected! */\r
+ portENTER_CRITICAL();\r
+ sCheckVariableToUse = sNextCheckVariable;\r
+ sNextCheckVariable++;\r
+ portEXIT_CRITICAL();\r
+\r
+ /* Queue a message for printing to say the task has started. */\r
+ vPrintDisplayMessage( &pcSemaphoreTaskStart );\r
+\r
+ /* A structure is passed in as the parameter. This contains the shared \r
+ variable being guarded. */\r
+ pxParameters = ( xSemaphoreParameters * ) pvParameters;\r
+ pulSharedVariable = pxParameters->pulSharedVariable;\r
+\r
+ /* If we are blocking we use a much higher count to ensure loads of context\r
+ switches occur during the count. */\r
+ if( pxParameters->xBlockTime > ( portTickType ) 0 )\r
+ {\r
+ ulExpectedValue = semtstBLOCKING_EXPECTED_VALUE;\r
+ }\r
+ else\r
+ {\r
+ ulExpectedValue = semtstNON_BLOCKING_EXPECTED_VALUE;\r
+ }\r
+\r
+ for( ;; )\r
+ {\r
+ /* Try to obtain the semaphore. */\r
+ if( xSemaphoreTake( pxParameters->xSemaphore, pxParameters->xBlockTime ) == pdPASS )\r
+ {\r
+ /* We have the semaphore and so expect any other tasks using the\r
+ shared variable to have left it in the state we expect to find\r
+ it. */\r
+ if( *pulSharedVariable != ulExpectedValue )\r
+ {\r
+ vPrintDisplayMessage( &pcPollingSemaphoreTaskError );\r
+ sError = pdTRUE;\r
+ }\r
+ \r
+ /* Clear the variable, then count it back up to the expected value\r
+ before releasing the semaphore. Would expect a context switch or\r
+ two during this time. */\r
+ for( ulCounter = ( unsigned portLONG ) 0; ulCounter <= ulExpectedValue; ulCounter++ )\r
+ {\r
+ *pulSharedVariable = ulCounter;\r
+ if( *pulSharedVariable != ulCounter )\r
+ {\r
+ if( sError == pdFALSE )\r
+ {\r
+ vPrintDisplayMessage( &pcPollingSemaphoreTaskError );\r
+ }\r
+ sError = pdTRUE;\r
+ }\r
+ }\r
+\r
+ /* Release the semaphore, and if no errors have occurred increment the check\r
+ variable. */\r
+ if( xSemaphoreGive( pxParameters->xSemaphore ) == pdFALSE )\r
+ {\r
+ vPrintDisplayMessage( &pcPollingSemaphoreTaskError );\r
+ sError = pdTRUE;\r
+ }\r
+\r
+ if( sError == pdFALSE )\r
+ {\r
+ if( sCheckVariableToUse < semtstNUM_TASKS )\r
+ {\r
+ ( sCheckVariables[ sCheckVariableToUse ] )++;\r
+ }\r
+ }\r
+\r
+ /* If we have a block time then we are running at a priority higher\r
+ than the idle priority. This task takes a long time to complete\r
+ a cycle (deliberately so to test the guarding) so will be starving\r
+ out lower priority tasks. Block for some time to allow give lower\r
+ priority tasks some processor time. */\r
+ vTaskDelay( pxParameters->xBlockTime * semtstDELAY_FACTOR );\r
+ }\r
+ else\r
+ {\r
+ if( pxParameters->xBlockTime == ( portTickType ) 0 )\r
+ {\r
+ /* We have not got the semaphore yet, so no point using the\r
+ processor. We are not blocking when attempting to obtain the\r
+ semaphore. */\r
+ taskYIELD();\r
+ }\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This is called to check that all the created tasks are still running. */\r
+portBASE_TYPE xAreSemaphoreTasksStillRunning( void )\r
+{\r
+static portSHORT sLastCheckVariables[ semtstNUM_TASKS ] = { 0 };\r
+portBASE_TYPE xTask, xReturn = pdTRUE;\r
+\r
+ for( xTask = 0; xTask < semtstNUM_TASKS; xTask++ )\r
+ {\r
+ if( sLastCheckVariables[ xTask ] == sCheckVariables[ xTask ] )\r
+ {\r
+ xReturn = pdFALSE;\r
+ }\r
+\r
+ sLastCheckVariables[ xTask ] = sCheckVariables[ xTask ];\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+ * Creates six tasks that operate on three queues as follows:\r
+ *\r
+ * The first two tasks send and receive an incrementing number to/from a queue.\r
+ * One task acts as a producer and the other as the consumer. The consumer is a\r
+ * higher priority than the producer and is set to block on queue reads. The queue\r
+ * only has space for one item - as soon as the producer posts a message on the\r
+ * queue the consumer will unblock, pre-empt the producer, and remove the item.\r
+ *\r
+ * The second two tasks work the other way around. Again the queue used only has\r
+ * enough space for one item. This time the consumer has a lower priority than the\r
+ * producer. The producer will try to post on the queue blocking when the queue is\r
+ * full. When the consumer wakes it will remove the item from the queue, causing\r
+ * the producer to unblock, pre-empt the consumer, and immediately re-fill the\r
+ * queue.\r
+ *\r
+ * The last two tasks use the same queue producer and consumer functions. This time the queue has\r
+ * enough space for lots of items and the tasks operate at the same priority. The\r
+ * producer will execute, placing items into the queue. The consumer will start\r
+ * executing when either the queue becomes full (causing the producer to block) or\r
+ * a context switch occurs (tasks of the same priority will time slice).\r
+ *\r
+ */\r
+\r
+\r
+\r
+#include <stdlib.h>\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+\r
+/* Demo program include files. */\r
+#include "BlockQ.h"\r
+\r
+#define blckqSTACK_SIZE configMINIMAL_STACK_SIZE\r
+#define blckqNUM_TASK_SETS ( 3 )\r
+\r
+/* Structure used to pass parameters to the blocking queue tasks. */\r
+typedef struct BLOCKING_QUEUE_PARAMETERS\r
+{\r
+ xQueueHandle xQueue; /*< The queue to be used by the task. */\r
+ portTickType xBlockTime; /*< The block time to use on queue reads/writes. */\r
+ volatile portSHORT *psCheckVariable; /*< Incremented on each successful cycle to check the task is still running. */\r
+} xBlockingQueueParameters;\r
+\r
+/* Task function that creates an incrementing number and posts it on a queue. */\r
+static portTASK_FUNCTION_PROTO( vBlockingQueueProducer, pvParameters );\r
+\r
+/* Task function that removes the incrementing number from a queue and checks that\r
+it is the expected number. */\r
+static portTASK_FUNCTION_PROTO( vBlockingQueueConsumer, pvParameters );\r
+\r
+/* Variables which are incremented each time an item is removed from a queue, and\r
+found to be the expected value.\r
+These are used to check that the tasks are still running. */\r
+static volatile portSHORT sBlockingConsumerCount[ blckqNUM_TASK_SETS ] = { ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0 };\r
+\r
+/* Variable which are incremented each time an item is posted on a queue. These\r
+are used to check that the tasks are still running. */\r
+static volatile portSHORT sBlockingProducerCount[ blckqNUM_TASK_SETS ] = { ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0 };\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vStartBlockingQueueTasks( unsigned portBASE_TYPE uxPriority )\r
+{\r
+xBlockingQueueParameters *pxQueueParameters1, *pxQueueParameters2;\r
+xBlockingQueueParameters *pxQueueParameters3, *pxQueueParameters4;\r
+xBlockingQueueParameters *pxQueueParameters5, *pxQueueParameters6;\r
+const unsigned portBASE_TYPE uxQueueSize1 = 1, uxQueueSize5 = 5;\r
+const portTickType xBlockTime = ( portTickType ) 1000 / portTICK_RATE_MS;\r
+const portTickType xDontBlock = ( portTickType ) 0;\r
+\r
+ /* Create the first two tasks as described at the top of the file. */\r
+ \r
+ /* First create the structure used to pass parameters to the consumer tasks. */\r
+ pxQueueParameters1 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );\r
+\r
+ /* Create the queue used by the first two tasks to pass the incrementing number.\r
+ Pass a pointer to the queue in the parameter structure. */\r
+ pxQueueParameters1->xQueue = xQueueCreate( uxQueueSize1, ( unsigned portBASE_TYPE ) sizeof( unsigned portSHORT ) );\r
+\r
+ /* The consumer is created first so gets a block time as described above. */\r
+ pxQueueParameters1->xBlockTime = xBlockTime;\r
+\r
+ /* Pass in the variable that this task is going to increment so we can check it\r
+ is still running. */\r
+ pxQueueParameters1->psCheckVariable = &( sBlockingConsumerCount[ 0 ] );\r
+ \r
+ /* Create the structure used to pass parameters to the producer task. */\r
+ pxQueueParameters2 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );\r
+\r
+ /* Pass the queue to this task also, using the parameter structure. */\r
+ pxQueueParameters2->xQueue = pxQueueParameters1->xQueue;\r
+\r
+ /* The producer is not going to block - as soon as it posts the consumer will\r
+ wake and remove the item so the producer should always have room to post. */\r
+ pxQueueParameters2->xBlockTime = xDontBlock;\r
+\r
+ /* Pass in the variable that this task is going to increment so we can check\r
+ it is still running. */\r
+ pxQueueParameters2->psCheckVariable = &( sBlockingProducerCount[ 0 ] );\r
+\r
+\r
+ /* Note the producer has a lower priority than the consumer when the tasks are\r
+ spawned. */\r
+ xTaskCreate( vBlockingQueueConsumer, ( signed portCHAR * ) "QConsB1", blckqSTACK_SIZE, ( void * ) pxQueueParameters1, uxPriority, NULL );\r
+ xTaskCreate( vBlockingQueueProducer, ( signed portCHAR * ) "QProdB2", blckqSTACK_SIZE, ( void * ) pxQueueParameters2, tskIDLE_PRIORITY, NULL );\r
+\r
+ \r
+\r
+ /* Create the second two tasks as described at the top of the file. This uses\r
+ the same mechanism but reverses the task priorities. */\r
+\r
+ pxQueueParameters3 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );\r
+ pxQueueParameters3->xQueue = xQueueCreate( uxQueueSize1, ( unsigned portBASE_TYPE ) sizeof( unsigned portSHORT ) );\r
+ pxQueueParameters3->xBlockTime = xDontBlock;\r
+ pxQueueParameters3->psCheckVariable = &( sBlockingProducerCount[ 1 ] );\r
+\r
+ pxQueueParameters4 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );\r
+ pxQueueParameters4->xQueue = pxQueueParameters3->xQueue;\r
+ pxQueueParameters4->xBlockTime = xBlockTime;\r
+ pxQueueParameters4->psCheckVariable = &( sBlockingConsumerCount[ 1 ] );\r
+\r
+ xTaskCreate( vBlockingQueueProducer, ( signed portCHAR * ) "QProdB3", blckqSTACK_SIZE, ( void * ) pxQueueParameters3, tskIDLE_PRIORITY, NULL );\r
+ xTaskCreate( vBlockingQueueConsumer, ( signed portCHAR * ) "QConsB4", blckqSTACK_SIZE, ( void * ) pxQueueParameters4, uxPriority, NULL );\r
+\r
+\r
+\r
+ /* Create the last two tasks as described above. The mechanism is again just\r
+ the same. This time both parameter structures are given a block time. */\r
+ pxQueueParameters5 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );\r
+ pxQueueParameters5->xQueue = xQueueCreate( uxQueueSize5, ( unsigned portBASE_TYPE ) sizeof( unsigned portSHORT ) );\r
+ pxQueueParameters5->xBlockTime = xBlockTime;\r
+ pxQueueParameters5->psCheckVariable = &( sBlockingProducerCount[ 2 ] );\r
+\r
+ pxQueueParameters6 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );\r
+ pxQueueParameters6->xQueue = pxQueueParameters5->xQueue;\r
+ pxQueueParameters6->xBlockTime = xBlockTime;\r
+ pxQueueParameters6->psCheckVariable = &( sBlockingConsumerCount[ 2 ] ); \r
+\r
+ xTaskCreate( vBlockingQueueProducer, ( signed portCHAR * ) "QProdB5", blckqSTACK_SIZE, ( void * ) pxQueueParameters5, tskIDLE_PRIORITY, NULL );\r
+ xTaskCreate( vBlockingQueueConsumer, ( signed portCHAR * ) "QConsB6", blckqSTACK_SIZE, ( void * ) pxQueueParameters6, tskIDLE_PRIORITY, NULL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portTASK_FUNCTION( vBlockingQueueProducer, pvParameters )\r
+{\r
+unsigned portSHORT usValue = 0;\r
+xBlockingQueueParameters *pxQueueParameters;\r
+portSHORT sErrorEverOccurred = pdFALSE;\r
+\r
+ pxQueueParameters = ( xBlockingQueueParameters * ) pvParameters;\r
+\r
+ for( ;; )\r
+ { \r
+ if( xQueueSend( pxQueueParameters->xQueue, ( void * ) &usValue, pxQueueParameters->xBlockTime ) != pdPASS )\r
+ {\r
+ sErrorEverOccurred = pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ /* We have successfully posted a message, so increment the variable\r
+ used to check we are still running. */\r
+ if( sErrorEverOccurred == pdFALSE )\r
+ {\r
+ ( *pxQueueParameters->psCheckVariable )++;\r
+ }\r
+\r
+ /* Increment the variable we are going to post next time round. The\r
+ consumer will expect the numbers to follow in numerical order. */\r
+ ++usValue;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portTASK_FUNCTION( vBlockingQueueConsumer, pvParameters )\r
+{\r
+unsigned portSHORT usData, usExpectedValue = 0;\r
+xBlockingQueueParameters *pxQueueParameters;\r
+portSHORT sErrorEverOccurred = pdFALSE;\r
+\r
+ pxQueueParameters = ( xBlockingQueueParameters * ) pvParameters;\r
+\r
+ for( ;; )\r
+ { \r
+ if( xQueueReceive( pxQueueParameters->xQueue, &usData, pxQueueParameters->xBlockTime ) == pdPASS )\r
+ {\r
+ if( usData != usExpectedValue )\r
+ {\r
+ /* Catch-up. */\r
+ usExpectedValue = usData;\r
+\r
+ sErrorEverOccurred = pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ /* We have successfully received a message, so increment the\r
+ variable used to check we are still running. */ \r
+ if( sErrorEverOccurred == pdFALSE )\r
+ {\r
+ ( *pxQueueParameters->psCheckVariable )++;\r
+ }\r
+ \r
+ /* Increment the value we expect to remove from the queue next time\r
+ round. */\r
+ ++usExpectedValue;\r
+ } \r
+ } \r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This is called to check that all the created tasks are still running. */\r
+portBASE_TYPE xAreBlockingQueuesStillRunning( void )\r
+{\r
+static portSHORT sLastBlockingConsumerCount[ blckqNUM_TASK_SETS ] = { ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0 };\r
+static portSHORT sLastBlockingProducerCount[ blckqNUM_TASK_SETS ] = { ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0 };\r
+portBASE_TYPE xReturn = pdPASS, xTasks;\r
+\r
+ /* Not too worried about mutual exclusion on these variables as they are 16\r
+ bits and we are only reading them. We also only care to see if they have\r
+ changed or not.\r
+ \r
+ Loop through each check variable to and return pdFALSE if any are found not\r
+ to have changed since the last call. */\r
+\r
+ for( xTasks = 0; xTasks < blckqNUM_TASK_SETS; xTasks++ )\r
+ {\r
+ if( sBlockingConsumerCount[ xTasks ] == sLastBlockingConsumerCount[ xTasks ] )\r
+ {\r
+ xReturn = pdFALSE;\r
+ }\r
+ sLastBlockingConsumerCount[ xTasks ] = sBlockingConsumerCount[ xTasks ];\r
+\r
+\r
+ if( sBlockingProducerCount[ xTasks ] == sLastBlockingProducerCount[ xTasks ] )\r
+ {\r
+ xReturn = pdFALSE;\r
+ }\r
+ sLastBlockingProducerCount[ xTasks ] = sBlockingProducerCount[ xTasks ];\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+ * This version of PollQ. c is for use on systems that have limited stack\r
+ * space and no display facilities. The complete version can be found in\r
+ * the Demo/Common/Full directory.\r
+ *\r
+ * Creates two tasks that communicate over a single queue. One task acts as a\r
+ * producer, the other a consumer.\r
+ *\r
+ * The producer loops for three iteration, posting an incrementing number onto the\r
+ * queue each cycle. It then delays for a fixed period before doing exactly the\r
+ * same again.\r
+ *\r
+ * The consumer loops emptying the queue. Each item removed from the queue is\r
+ * checked to ensure it contains the expected value. When the queue is empty it\r
+ * blocks for a fixed period, then does the same again.\r
+ *\r
+ * All queue access is performed without blocking. The consumer completely empties\r
+ * the queue each time it runs so the producer should never find the queue full.\r
+ *\r
+ * An error is flagged if the consumer obtains an unexpected value or the producer\r
+ * find the queue is full.\r
+ */\r
+\r
+/*\r
+Changes from V2.0.0\r
+\r
+ + Delay periods are now specified using variables and constants of\r
+ portTickType rather than unsigned portLONG.\r
+*/\r
+\r
+#include <stdlib.h>\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+\r
+/* Demo program include files. */\r
+#include "PollQ.h"\r
+\r
+#define pollqSTACK_SIZE configMINIMAL_STACK_SIZE\r
+#define pollqQUEUE_SIZE ( 10 )\r
+#define pollqDELAY ( ( portTickType ) 200 / portTICK_RATE_MS )\r
+#define pollqNO_DELAY ( ( portTickType ) 0 )\r
+#define pollqVALUES_TO_PRODUCE ( ( signed portBASE_TYPE ) 3 )\r
+#define pollqINITIAL_VALUE ( ( signed portBASE_TYPE ) 0 )\r
+\r
+/* The task that posts the incrementing number onto the queue. */\r
+static portTASK_FUNCTION_PROTO( vPolledQueueProducer, pvParameters );\r
+\r
+/* The task that empties the queue. */\r
+static portTASK_FUNCTION_PROTO( vPolledQueueConsumer, pvParameters );\r
+\r
+/* Variables that are used to check that the tasks are still running with no\r
+errors. */\r
+static volatile signed portBASE_TYPE xPollingConsumerCount = pollqINITIAL_VALUE, xPollingProducerCount = pollqINITIAL_VALUE;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vStartPolledQueueTasks( unsigned portBASE_TYPE uxPriority )\r
+{\r
+static xQueueHandle xPolledQueue;\r
+\r
+ /* Create the queue used by the producer and consumer. */\r
+ xPolledQueue = xQueueCreate( pollqQUEUE_SIZE, ( unsigned portBASE_TYPE ) sizeof( unsigned portSHORT ) );\r
+\r
+ /* Spawn the producer and consumer. */\r
+ xTaskCreate( vPolledQueueConsumer, ( const signed portCHAR * const ) "QConsNB", pollqSTACK_SIZE, ( void * ) &xPolledQueue, uxPriority, ( xTaskHandle * ) NULL );\r
+ xTaskCreate( vPolledQueueProducer, ( const signed portCHAR * const ) "QProdNB", pollqSTACK_SIZE, ( void * ) &xPolledQueue, uxPriority, ( xTaskHandle * ) NULL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portTASK_FUNCTION( vPolledQueueProducer, pvParameters )\r
+{\r
+unsigned portSHORT usValue = ( unsigned portSHORT ) 0;\r
+signed portBASE_TYPE xError = pdFALSE, xLoop;\r
+\r
+ for( ;; )\r
+ { \r
+ for( xLoop = 0; xLoop < pollqVALUES_TO_PRODUCE; xLoop++ )\r
+ {\r
+ /* Send an incrementing number on the queue without blocking. */\r
+ if( xQueueSend( *( ( xQueueHandle * ) pvParameters ), ( void * ) &usValue, pollqNO_DELAY ) != pdPASS )\r
+ {\r
+ /* We should never find the queue full so if we get here there\r
+ has been an error. */\r
+ xError = pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ if( xError == pdFALSE )\r
+ {\r
+ /* If an error has ever been recorded we stop incrementing the\r
+ check variable. */\r
+ portENTER_CRITICAL();\r
+ xPollingProducerCount++;\r
+ portEXIT_CRITICAL();\r
+ }\r
+\r
+ /* Update the value we are going to post next time around. */\r
+ usValue++;\r
+ }\r
+ }\r
+\r
+ /* Wait before we start posting again to ensure the consumer runs and\r
+ empties the queue. */\r
+ vTaskDelay( pollqDELAY );\r
+ }\r
+} /*lint !e818 Function prototype must conform to API. */\r
+/*-----------------------------------------------------------*/\r
+\r
+static portTASK_FUNCTION( vPolledQueueConsumer, pvParameters )\r
+{\r
+unsigned portSHORT usData, usExpectedValue = ( unsigned portSHORT ) 0;\r
+signed portBASE_TYPE xError = pdFALSE;\r
+\r
+ for( ;; )\r
+ { \r
+ /* Loop until the queue is empty. */\r
+ while( uxQueueMessagesWaiting( *( ( xQueueHandle * ) pvParameters ) ) )\r
+ {\r
+ if( xQueueReceive( *( ( xQueueHandle * ) pvParameters ), &usData, pollqNO_DELAY ) == pdPASS )\r
+ {\r
+ if( usData != usExpectedValue )\r
+ {\r
+ /* This is not what we expected to receive so an error has\r
+ occurred. */\r
+ xError = pdTRUE;\r
+\r
+ /* Catch-up to the value we received so our next expected\r
+ value should again be correct. */\r
+ usExpectedValue = usData;\r
+ }\r
+ else\r
+ {\r
+ if( xError == pdFALSE )\r
+ {\r
+ /* Only increment the check variable if no errors have\r
+ occurred. */\r
+ portENTER_CRITICAL();\r
+ xPollingConsumerCount++;\r
+ portEXIT_CRITICAL();\r
+ }\r
+ }\r
+\r
+ /* Next time round we would expect the number to be one higher. */\r
+ usExpectedValue++;\r
+ }\r
+ }\r
+\r
+ /* Now the queue is empty we block, allowing the producer to place more\r
+ items in the queue. */\r
+ vTaskDelay( pollqDELAY );\r
+ }\r
+} /*lint !e818 Function prototype must conform to API. */\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This is called to check that all the created tasks are still running with no errors. */\r
+portBASE_TYPE xArePollingQueuesStillRunning( void )\r
+{\r
+portBASE_TYPE xReturn;\r
+\r
+ /* Check both the consumer and producer poll count to check they have both\r
+ been changed since out last trip round. We do not need a critical section\r
+ around the check variables as this is called from a higher priority than\r
+ the other tasks that access the same variables. */\r
+ if( ( xPollingConsumerCount == pollqINITIAL_VALUE ) ||\r
+ ( xPollingProducerCount == pollqINITIAL_VALUE )\r
+ )\r
+ {\r
+ xReturn = pdFALSE;\r
+ }\r
+ else\r
+ {\r
+ xReturn = pdTRUE;\r
+ }\r
+\r
+ /* Set the check variables back down so we know if they have been\r
+ incremented the next time around. */\r
+ xPollingConsumerCount = pollqINITIAL_VALUE;\r
+ xPollingProducerCount = pollqINITIAL_VALUE;\r
+\r
+ return xReturn;\r
+}\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+\r
+/*\r
+ * This version of comtest. c is for use on systems that have limited stack\r
+ * space and no display facilities. The complete version can be found in\r
+ * the Demo/Common/Full directory.\r
+ *\r
+ * Creates two tasks that operate on an interrupt driven serial port. A\r
+ * loopback connector should be used so that everything that is transmitted is\r
+ * also received. The serial port does not use any flow control. On a\r
+ * standard 9way 'D' connector pins two and three should be connected together.\r
+ *\r
+ * The first task posts a sequence of characters to the Tx queue, toggling an\r
+ * LED on each successful post. At the end of the sequence it sleeps for a\r
+ * pseudo-random period before resending the same sequence.\r
+ *\r
+ * The UART Tx end interrupt is enabled whenever data is available in the Tx\r
+ * queue. The Tx end ISR removes a single character from the Tx queue and\r
+ * passes it to the UART for transmission.\r
+ *\r
+ * The second task blocks on the Rx queue waiting for a character to become\r
+ * available. When the UART Rx end interrupt receives a character it places\r
+ * it in the Rx queue, waking the second task. The second task checks that the\r
+ * characters removed from the Rx queue form the same sequence as those posted\r
+ * to the Tx queue, and toggles an LED for each correct character.\r
+ *\r
+ * The receiving task is spawned with a higher priority than the transmitting\r
+ * task. The receiver will therefore wake every time a character is\r
+ * transmitted so neither the Tx or Rx queue should ever hold more than a few\r
+ * characters.\r
+ *\r
+ */\r
+\r
+/*\r
+Changes from V1.2.0:\r
+\r
+ + Reduced the maximum time between successive transmissions. This provides\r
+ for a more rigorous test.\r
+\r
+Changes from V2.0.0\r
+\r
+ + Delay periods are now specified using variables and constants of\r
+ portTickType rather than unsigned portLONG.\r
+\r
+Changes from V2.5.1\r
+\r
+ + The constant comOFFSET_TIME added to the delay period to ensure a more\r
+ random delay period is used.\r
+*/\r
+\r
+/* Scheduler include files. */\r
+#include <stdlib.h>\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo program include files. */\r
+#include "serial.h"\r
+#include "comtest.h"\r
+#include "partest.h"\r
+\r
+#define comSTACK_SIZE configMINIMAL_STACK_SIZE\r
+#define comTX_LED_OFFSET ( 0 )\r
+#define comRX_LED_OFFSET ( 1 )\r
+#define comTOTAL_PERMISSIBLE_ERRORS ( 2 )\r
+\r
+/* The Tx task will transmit the sequence of characters at a pseudo random\r
+interval. This is the maximum and minimum block time between sends. */\r
+#define comTX_MAX_BLOCK_TIME ( ( portTickType ) 0x96 )\r
+#define comTX_MIN_BLOCK_TIME ( ( portTickType ) 0x32 )\r
+#define comOFFSET_TIME ( ( portTickType ) 3 )\r
+\r
+/* We should find that each character can be queued for Tx immediately and we\r
+don't have to block to send. */\r
+#define comNO_BLOCK ( ( portTickType ) 0 )\r
+\r
+/* The Rx task will block on the Rx queue for a long period. */\r
+#define comRX_BLOCK_TIME ( ( portTickType ) 0xffff )\r
+\r
+/* The sequence transmitted is from comFIRST_BYTE to and including comLAST_BYTE. */\r
+#define comFIRST_BYTE ( 'A' )\r
+#define comLAST_BYTE ( 'X' )\r
+\r
+#define comBUFFER_LEN ( ( unsigned portBASE_TYPE ) ( comLAST_BYTE - comFIRST_BYTE ) + ( unsigned portBASE_TYPE ) 1 )\r
+#define comINITIAL_RX_COUNT_VALUE ( 0 )\r
+\r
+/* Handle to the com port used by both tasks. */\r
+static xComPortHandle xPort = NULL;\r
+\r
+/* The transmit task as described at the top of the file. */\r
+static portTASK_FUNCTION_PROTO( vComTxTask, pvParameters );\r
+\r
+/* The receive task as described at the top of the file. */\r
+static portTASK_FUNCTION_PROTO( vComRxTask, pvParameters );\r
+\r
+/* The LED that should be toggled by the Rx and Tx tasks. The Rx task will\r
+toggle LED ( uxBaseLED + comRX_LED_OFFSET). The Tx task will toggle LED\r
+( uxBaseLED + comTX_LED_OFFSET ). */\r
+static unsigned portBASE_TYPE uxBaseLED = 0;\r
+\r
+/* Check variable used to ensure no error have occurred. The Rx task will\r
+increment this variable after every successfully received sequence. If at any\r
+time the sequence is incorrect the the variable will stop being incremented. */\r
+static volatile unsigned portBASE_TYPE uxRxLoops = comINITIAL_RX_COUNT_VALUE;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vAltStartComTestTasks( unsigned portBASE_TYPE uxPriority, unsigned portLONG ulBaudRate, unsigned portBASE_TYPE uxLED )\r
+{\r
+ /* Initialise the com port then spawn the Rx and Tx tasks. */\r
+ uxBaseLED = uxLED;\r
+ xSerialPortInitMinimal( ulBaudRate, comBUFFER_LEN );\r
+\r
+ /* The Tx task is spawned with a lower priority than the Rx task. */\r
+ xTaskCreate( vComTxTask, ( const signed portCHAR * const ) "COMTx", comSTACK_SIZE, NULL, uxPriority - 1, ( xTaskHandle * ) NULL );\r
+ xTaskCreate( vComRxTask, ( const signed portCHAR * const ) "COMRx", comSTACK_SIZE, NULL, uxPriority, ( xTaskHandle * ) NULL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portTASK_FUNCTION( vComTxTask, pvParameters )\r
+{\r
+signed portCHAR cByteToSend;\r
+portTickType xTimeToWait;\r
+\r
+ /* Just to stop compiler warnings. */\r
+ ( void ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ /* Simply transmit a sequence of characters from comFIRST_BYTE to\r
+ comLAST_BYTE. */\r
+ for( cByteToSend = comFIRST_BYTE; cByteToSend <= comLAST_BYTE; cByteToSend++ )\r
+ {\r
+ if( xSerialPutChar( xPort, cByteToSend, comNO_BLOCK ) == pdPASS )\r
+ {\r
+ vParTestToggleLED( uxBaseLED + comTX_LED_OFFSET );\r
+ }\r
+ }\r
+\r
+ /* Turn the LED off while we are not doing anything. */\r
+ vParTestSetLED( uxBaseLED + comTX_LED_OFFSET, pdFALSE );\r
+\r
+ /* We have posted all the characters in the string - wait before\r
+ re-sending. Wait a pseudo-random time as this will provide a better\r
+ test. */\r
+ xTimeToWait = xTaskGetTickCount() + comOFFSET_TIME;\r
+\r
+ /* Make sure we don't wait too long... */\r
+ xTimeToWait %= comTX_MAX_BLOCK_TIME;\r
+\r
+ /* ...but we do want to wait. */\r
+ if( xTimeToWait < comTX_MIN_BLOCK_TIME )\r
+ {\r
+ xTimeToWait = comTX_MIN_BLOCK_TIME;\r
+ }\r
+\r
+ vTaskDelay( xTimeToWait );\r
+ }\r
+} /*lint !e715 !e818 pvParameters is required for a task function even if it is not referenced. */\r
+/*-----------------------------------------------------------*/\r
+\r
+static portTASK_FUNCTION( vComRxTask, pvParameters )\r
+{\r
+signed portCHAR cExpectedByte, cByteRxed;\r
+portBASE_TYPE xResyncRequired = pdFALSE, xErrorOccurred = pdFALSE;\r
+\r
+ /* Just to stop compiler warnings. */\r
+ ( void ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ /* We expect to receive the characters from comFIRST_BYTE to\r
+ comLAST_BYTE in an incrementing order. Loop to receive each byte. */\r
+ for( cExpectedByte = comFIRST_BYTE; cExpectedByte <= comLAST_BYTE; cExpectedByte++ )\r
+ {\r
+ /* Block on the queue that contains received bytes until a byte is\r
+ available. */\r
+ if( xSerialGetChar( xPort, &cByteRxed, comRX_BLOCK_TIME ) )\r
+ {\r
+ /* Was this the byte we were expecting? If so, toggle the LED,\r
+ otherwise we are out on sync and should break out of the loop\r
+ until the expected character sequence is about to restart. */\r
+ if( cByteRxed == cExpectedByte )\r
+ {\r
+ vParTestToggleLED( uxBaseLED + comRX_LED_OFFSET );\r
+ }\r
+ else\r
+ {\r
+ xResyncRequired = pdTRUE;\r
+ break; /*lint !e960 Non-switch break allowed. */\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Turn the LED off while we are not doing anything. */\r
+ vParTestSetLED( uxBaseLED + comRX_LED_OFFSET, pdFALSE );\r
+\r
+ /* Did we break out of the loop because the characters were received in\r
+ an unexpected order? If so wait here until the character sequence is\r
+ about to restart. */\r
+ if( xResyncRequired == pdTRUE )\r
+ {\r
+ while( cByteRxed != comLAST_BYTE )\r
+ {\r
+ /* Block until the next char is available. */\r
+ xSerialGetChar( xPort, &cByteRxed, comRX_BLOCK_TIME );\r
+ }\r
+\r
+ /* Note that an error occurred which caused us to have to resync.\r
+ We use this to stop incrementing the loop counter so\r
+ sAreComTestTasksStillRunning() will return false - indicating an\r
+ error. */\r
+ xErrorOccurred++;\r
+\r
+ /* We have now resynced with the Tx task and can continue. */\r
+ xResyncRequired = pdFALSE;\r
+ }\r
+ else\r
+ {\r
+ if( xErrorOccurred < comTOTAL_PERMISSIBLE_ERRORS )\r
+ {\r
+ /* Increment the count of successful loops. As error\r
+ occurring (i.e. an unexpected character being received) will\r
+ prevent this counter being incremented for the rest of the\r
+ execution. Don't worry about mutual exclusion on this\r
+ variable - it doesn't really matter as we just want it\r
+ to change. */\r
+ uxRxLoops++;\r
+ }\r
+ }\r
+ }\r
+} /*lint !e715 !e818 pvParameters is required for a task function even if it is not referenced. */\r
+/*-----------------------------------------------------------*/\r
+\r
+portBASE_TYPE xAreComTestTasksStillRunning( void )\r
+{\r
+portBASE_TYPE xReturn;\r
+\r
+ /* If the count of successful reception loops has not changed than at\r
+ some time an error occurred (i.e. a character was received out of sequence)\r
+ and we will return false. */\r
+ if( uxRxLoops == comINITIAL_RX_COUNT_VALUE )\r
+ {\r
+ xReturn = pdFALSE;\r
+ }\r
+ else\r
+ {\r
+ xReturn = pdTRUE;\r
+ }\r
+\r
+ /* Reset the count of successful Rx loops. When this function is called\r
+ again we expect this to have been incremented. */\r
+ uxRxLoops = comINITIAL_RX_COUNT_VALUE;\r
+\r
+ return xReturn;\r
+}\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* \r
+ * This demo application file demonstrates the use of queues to pass data\r
+ * between co-routines.\r
+ *\r
+ * N represents the number of 'fixed delay' co-routines that are created and\r
+ * is set during initialisation.\r
+ *\r
+ * N 'fixed delay' co-routines are created that just block for a fixed \r
+ * period then post the number of an LED onto a queue. Each such co-routine\r
+ * uses a different block period. A single 'flash' co-routine is also created \r
+ * that blocks on the same queue, waiting for the number of the next LED it \r
+ * should flash. Upon receiving a number it simply toggle the instructed LED \r
+ * then blocks on the queue once more. In this manner each LED from LED 0 to \r
+ * LED N-1 is caused to flash at a different rate.\r
+ *\r
+ * The 'fixed delay' co-routines are created with co-routine priority 0. The\r
+ * flash co-routine is created with co-routine priority 1. This means that\r
+ * the queue should never contain more than a single item. This is because\r
+ * posting to the queue will unblock the 'flash' co-routine, and as this has\r
+ * a priority greater than the tasks posting to the queue it is guaranteed to \r
+ * have emptied the queue and blocked once again before the queue can contain\r
+ * any more date. An error is indicated if an attempt to post data to the \r
+ * queue fails - indicating that the queue is already full.\r
+ *\r
+ */\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "croutine.h"\r
+#include "queue.h"\r
+\r
+/* Demo application includes. */\r
+#include "partest.h"\r
+#include "crflash.h"\r
+\r
+/* The queue should only need to be of length 1. See the description at the\r
+top of the file. */\r
+#define crfQUEUE_LENGTH 1\r
+\r
+#define crfFIXED_DELAY_PRIORITY 0\r
+#define crfFLASH_PRIORITY 1\r
+\r
+/* Only one flash co-routine is created so the index is not significant. */\r
+#define crfFLASH_INDEX 0\r
+\r
+/* Don't allow more than crfMAX_FLASH_TASKS 'fixed delay' co-routines to be\r
+created. */\r
+#define crfMAX_FLASH_TASKS 8\r
+\r
+/* We don't want to block when posting to the queue. */\r
+#define crfPOSTING_BLOCK_TIME 0\r
+\r
+/* \r
+ * The 'fixed delay' co-routine as described at the top of the file.\r
+ */\r
+static void prvFixedDelayCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex );\r
+\r
+/*\r
+ * The 'flash' co-routine as described at the top of the file.\r
+ */\r
+static void prvFlashCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex );\r
+\r
+/* The queue used to pass data between the 'fixed delay' co-routines and the\r
+'flash' co-routine. */\r
+static xQueueHandle xFlashQueue;\r
+\r
+/* This will be set to pdFALSE if we detect an error. */\r
+static unsigned portBASE_TYPE uxCoRoutineFlashStatus = pdPASS;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * See the header file for details.\r
+ */\r
+void vStartFlashCoRoutines( unsigned portBASE_TYPE uxNumberToCreate )\r
+{\r
+unsigned portBASE_TYPE uxIndex;\r
+\r
+ if( uxNumberToCreate > crfMAX_FLASH_TASKS )\r
+ {\r
+ uxNumberToCreate = crfMAX_FLASH_TASKS;\r
+ }\r
+\r
+ /* Create the queue used to pass data between the co-routines. */\r
+ xFlashQueue = xQueueCreate( crfQUEUE_LENGTH, sizeof( unsigned portBASE_TYPE ) );\r
+\r
+ if( xFlashQueue )\r
+ {\r
+ /* Create uxNumberToCreate 'fixed delay' co-routines. */\r
+ for( uxIndex = 0; uxIndex < uxNumberToCreate; uxIndex++ )\r
+ {\r
+ xCoRoutineCreate( prvFixedDelayCoRoutine, crfFIXED_DELAY_PRIORITY, uxIndex );\r
+ }\r
+\r
+ /* Create the 'flash' co-routine. */\r
+ xCoRoutineCreate( prvFlashCoRoutine, crfFLASH_PRIORITY, crfFLASH_INDEX );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvFixedDelayCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )\r
+{\r
+/* Even though this is a co-routine the xResult variable does not need to be\r
+static as we do not need it to maintain its state between blocks. */\r
+portBASE_TYPE xResult;\r
+/* The uxIndex parameter of the co-routine function is used as an index into \r
+the xFlashRates array to obtain the delay period to use. */\r
+static const portTickType xFlashRates[ crfMAX_FLASH_TASKS ] = { 150 / portTICK_RATE_MS, \r
+ 200 / portTICK_RATE_MS, \r
+ 250 / portTICK_RATE_MS, \r
+ 300 / portTICK_RATE_MS, \r
+ 350 / portTICK_RATE_MS,\r
+ 400 / portTICK_RATE_MS, \r
+ 450 / portTICK_RATE_MS, \r
+ 500 / portTICK_RATE_MS };\r
+\r
+ /* Co-routines MUST start with a call to crSTART. */\r
+ crSTART( xHandle );\r
+\r
+ for( ;; )\r
+ {\r
+ /* Post our uxIndex value onto the queue. This is used as the LED to \r
+ flash. */\r
+ crQUEUE_SEND( xHandle, xFlashQueue, ( void * ) &uxIndex, crfPOSTING_BLOCK_TIME, &xResult );\r
+\r
+ if( xResult != pdPASS )\r
+ {\r
+ /* For the reasons stated at the top of the file we should always\r
+ find that we can post to the queue. If we could not then an error\r
+ has occurred. */\r
+ uxCoRoutineFlashStatus = pdFAIL;\r
+ }\r
+\r
+ crDELAY( xHandle, xFlashRates[ uxIndex ] );\r
+ }\r
+\r
+ /* Co-routines MUST end with a call to crEND. */\r
+ crEND();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvFlashCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )\r
+{\r
+/* Even though this is a co-routine the variable do not need to be\r
+static as we do not need it to maintain their state between blocks. */\r
+portBASE_TYPE xResult;\r
+unsigned portBASE_TYPE uxLEDToFlash;\r
+\r
+ /* Co-routines MUST start with a call to crSTART. */\r
+ crSTART( xHandle );\r
+\r
+ for( ;; )\r
+ {\r
+ /* Block to wait for the number of the LED to flash. */\r
+ crQUEUE_RECEIVE( xHandle, xFlashQueue, &uxLEDToFlash, portMAX_DELAY, &xResult ); \r
+\r
+ if( xResult != pdPASS )\r
+ {\r
+ /* We would not expect to wake unless we received something. */\r
+ uxCoRoutineFlashStatus = pdFAIL;\r
+ }\r
+ else\r
+ {\r
+ /* We received the number of an LED to flash - flash it! */\r
+ vParTestToggleLED( uxLEDToFlash );\r
+ }\r
+ }\r
+\r
+ /* Co-routines MUST end with a call to crEND. */\r
+ crEND();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portBASE_TYPE xAreFlashCoRoutinesStillRunning( void )\r
+{\r
+ /* Return pdPASS or pdFAIL depending on whether an error has been detected\r
+ or not. */\r
+ return uxCoRoutineFlashStatus;\r
+}\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+ * This demo file demonstrates how to send data between an ISR and a \r
+ * co-routine. A tick hook function is used to periodically pass data between\r
+ * the RTOS tick and a set of 'hook' co-routines.\r
+ *\r
+ * hookNUM_HOOK_CO_ROUTINES co-routines are created. Each co-routine blocks\r
+ * to wait for a character to be received on a queue from the tick ISR, checks\r
+ * to ensure the character received was that expected, then sends the number\r
+ * back to the tick ISR on a different queue.\r
+ * \r
+ * The tick ISR checks the numbers received back from the 'hook' co-routines \r
+ * matches the number previously sent.\r
+ *\r
+ * If at any time a queue function returns unexpectedly, or an incorrect value\r
+ * is received either by the tick hook or a co-routine then an error is \r
+ * latched.\r
+ *\r
+ * This demo relies on each 'hook' co-routine to execute between each \r
+ * hookTICK_CALLS_BEFORE_POST tick interrupts. This and the heavy use of \r
+ * queues from within an interrupt may result in an error being detected on \r
+ * slower targets simply due to timing.\r
+ */\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "croutine.h"\r
+#include "queue.h"\r
+\r
+/* Demo application includes. */\r
+#include "crhook.h"\r
+\r
+/* The number of 'hook' co-routines that are to be created. */\r
+#define hookNUM_HOOK_CO_ROUTINES ( 4 )\r
+\r
+/* The number of times the tick hook should be called before a character is \r
+posted to the 'hook' co-routines. */\r
+#define hookTICK_CALLS_BEFORE_POST ( 250 )\r
+\r
+/* There should never be more than one item in any queue at any time. */\r
+#define hookHOOK_QUEUE_LENGTH ( 1 )\r
+\r
+/* Don't block when initially posting to the queue. */\r
+#define hookNO_BLOCK_TIME ( 0 )\r
+\r
+/* The priority relative to other co-routines (rather than tasks) that the\r
+'hook' co-routines should take. */\r
+#define mainHOOK_CR_PRIORITY ( 1 )\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The co-routine function itself.\r
+ */\r
+static void prvHookCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex );\r
+\r
+\r
+/*\r
+ * The tick hook function. This receives a number from each 'hook' co-routine\r
+ * then sends a number to each co-routine. An error is flagged if a send or \r
+ * receive fails, or an unexpected number is received.\r
+ */\r
+void vApplicationTickHook( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Queues used to send data FROM a co-routine TO the tick hook function.\r
+The hook functions received (Rx's) on these queues. One queue per\r
+'hook' co-routine. */\r
+static xQueueHandle xHookRxQueues[ hookNUM_HOOK_CO_ROUTINES ];\r
+\r
+/* Queues used to send data FROM the tick hook TO a co-routine function.\r
+The hood function transmits (Tx's) on these queues. One queue per\r
+'hook' co-routine. */\r
+static xQueueHandle xHookTxQueues[ hookNUM_HOOK_CO_ROUTINES ];\r
+\r
+/* Set to true if an error is detected at any time. */\r
+static portBASE_TYPE xCoRoutineErrorDetected = pdFALSE;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vStartHookCoRoutines( void )\r
+{\r
+unsigned portBASE_TYPE uxIndex, uxValueToPost = 0;\r
+\r
+ for( uxIndex = 0; uxIndex < hookNUM_HOOK_CO_ROUTINES; uxIndex++ )\r
+ {\r
+ /* Create a queue to transmit to and receive from each 'hook' \r
+ co-routine. */\r
+ xHookRxQueues[ uxIndex ] = xQueueCreate( hookHOOK_QUEUE_LENGTH, sizeof( unsigned portBASE_TYPE ) );\r
+ xHookTxQueues[ uxIndex ] = xQueueCreate( hookHOOK_QUEUE_LENGTH, sizeof( unsigned portBASE_TYPE ) );\r
+\r
+ /* To start things off the tick hook function expects the queue it \r
+ uses to receive data to contain a value. */\r
+ xQueueSend( xHookRxQueues[ uxIndex ], &uxValueToPost, hookNO_BLOCK_TIME );\r
+\r
+ /* Create the 'hook' co-routine itself. */\r
+ xCoRoutineCreate( prvHookCoRoutine, mainHOOK_CR_PRIORITY, uxIndex );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static unsigned portBASE_TYPE uxCallCounter = 0, uxNumberToPost = 0;\r
+void vApplicationTickHook( void )\r
+{\r
+unsigned portBASE_TYPE uxReceivedNumber;\r
+signed portBASE_TYPE xIndex, xCoRoutineWoken;\r
+\r
+ /* Is it time to talk to the 'hook' co-routines again? */\r
+ uxCallCounter++;\r
+ if( uxCallCounter >= hookTICK_CALLS_BEFORE_POST )\r
+ {\r
+ uxCallCounter = 0;\r
+\r
+ for( xIndex = 0; xIndex < hookNUM_HOOK_CO_ROUTINES; xIndex++ )\r
+ {\r
+ xCoRoutineWoken = pdFALSE;\r
+ if( crQUEUE_RECEIVE_FROM_ISR( xHookRxQueues[ xIndex ], &uxReceivedNumber, &xCoRoutineWoken ) != pdPASS )\r
+ {\r
+ /* There is no reason why we would not expect the queue to \r
+ contain a value. */\r
+ xCoRoutineErrorDetected = pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ /* Each queue used to receive data from the 'hook' co-routines \r
+ should contain the number we last posted to the same co-routine. */\r
+ if( uxReceivedNumber != uxNumberToPost )\r
+ {\r
+ xCoRoutineErrorDetected = pdTRUE;\r
+ }\r
+\r
+ /* Nothing should be blocked waiting to post to the queue. */\r
+ if( xCoRoutineWoken != pdFALSE )\r
+ {\r
+ xCoRoutineErrorDetected = pdTRUE;\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Start the next cycle by posting the next number onto each Tx queue. */\r
+ uxNumberToPost++;\r
+\r
+ for( xIndex = 0; xIndex < hookNUM_HOOK_CO_ROUTINES; xIndex++ )\r
+ {\r
+ if( crQUEUE_SEND_FROM_ISR( xHookTxQueues[ xIndex ], &uxNumberToPost, pdFALSE ) != pdTRUE )\r
+ {\r
+ /* Posting to the queue should have woken the co-routine that \r
+ was blocked on the queue. */\r
+ xCoRoutineErrorDetected = pdTRUE;\r
+ }\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvHookCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )\r
+{\r
+static unsigned portBASE_TYPE uxReceivedValue[ hookNUM_HOOK_CO_ROUTINES ];\r
+portBASE_TYPE xResult;\r
+\r
+ /* Each co-routine MUST start with a call to crSTART(); */\r
+ crSTART( xHandle );\r
+\r
+ for( ;; )\r
+ {\r
+ /* Wait to receive a value from the tick hook. */\r
+ xResult = pdFAIL;\r
+ crQUEUE_RECEIVE( xHandle, xHookTxQueues[ uxIndex ], &( uxReceivedValue[ uxIndex ] ), portMAX_DELAY, &xResult );\r
+\r
+ /* There is no reason why we should not have received something on\r
+ the queue. */\r
+ if( xResult != pdPASS )\r
+ {\r
+ xCoRoutineErrorDetected = pdTRUE;\r
+ }\r
+\r
+ /* Send the same number back to the idle hook so it can verify it. */\r
+ xResult = pdFAIL;\r
+ crQUEUE_SEND( xHandle, xHookRxQueues[ uxIndex ], &( uxReceivedValue[ uxIndex ] ), hookNO_BLOCK_TIME, &xResult );\r
+ if( xResult != pdPASS )\r
+ {\r
+ /* There is no reason why we should not have been able to post to \r
+ the queue. */\r
+ xCoRoutineErrorDetected = pdTRUE;\r
+ }\r
+ }\r
+\r
+ /* Each co-routine MUST end with a call to crEND(). */\r
+ crEND();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portBASE_TYPE xAreHookCoRoutinesStillRunning( void )\r
+{\r
+ if( xCoRoutineErrorDetected )\r
+ {\r
+ return pdFALSE;\r
+ }\r
+ else\r
+ {\r
+ return pdTRUE;\r
+ }\r
+}\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/**\r
+ * Create a single persistent task which periodically dynamically creates another\r
+ * four tasks. The original task is called the creator task, the four tasks it\r
+ * creates are called suicidal tasks.\r
+ *\r
+ * Two of the created suicidal tasks kill one other suicidal task before killing\r
+ * themselves - leaving just the original task remaining.\r
+ *\r
+ * The creator task must be spawned after all of the other demo application tasks\r
+ * as it keeps a check on the number of tasks under the scheduler control. The\r
+ * number of tasks it expects to see running should never be greater than the\r
+ * number of tasks that were in existence when the creator task was spawned, plus\r
+ * one set of four suicidal tasks. If this number is exceeded an error is flagged.\r
+ *\r
+ * \page DeathC death.c\r
+ * \ingroup DemoFiles\r
+ * <HR>\r
+ */\r
+\r
+/*\r
+Changes from V3.0.0\r
+ + CreationCount sizes changed from unsigned portBASE_TYPE to\r
+ unsigned portSHORT to minimize the risk of overflowing.\r
+ \r
+ + Reset of usLastCreationCount added\r
+ \r
+Changes from V3.1.0\r
+ + Changed the dummy calculation to use variables of type long, rather than\r
+ float. This allows the file to be used with ports that do not support\r
+ floating point.\r
+\r
+*/\r
+\r
+#include <stdlib.h>\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo program include files. */\r
+#include "death.h"\r
+\r
+#define deathSTACK_SIZE ( configMINIMAL_STACK_SIZE + 24 )\r
+\r
+/* The task originally created which is responsible for periodically dynamically\r
+creating another four tasks. */\r
+static portTASK_FUNCTION_PROTO( vCreateTasks, pvParameters );\r
+\r
+/* The task function of the dynamically created tasks. */\r
+static portTASK_FUNCTION_PROTO( vSuicidalTask, pvParameters );\r
+\r
+/* A variable which is incremented every time the dynamic tasks are created. This\r
+is used to check that the task is still running. */\r
+static volatile unsigned portSHORT usCreationCount = 0;\r
+\r
+/* Used to store the number of tasks that were originally running so the creator\r
+task can tell if any of the suicidal tasks have failed to die.\r
+*/\r
+static volatile unsigned portBASE_TYPE uxTasksRunningAtStart = 0;\r
+\r
+/* Tasks are deleted by the idle task. Under heavy load the idle task might\r
+not get much processing time, so it would be legitimate for several tasks to\r
+remain undeleted for a short period. */\r
+static const unsigned portBASE_TYPE uxMaxNumberOfExtraTasksRunning = 4;\r
+\r
+/* Used to store a handle to the tasks that should be killed by a suicidal task,\r
+before it kills itself. */\r
+xTaskHandle xCreatedTask1, xCreatedTask2;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vCreateSuicidalTasks( unsigned portBASE_TYPE uxPriority )\r
+{\r
+unsigned portBASE_TYPE *puxPriority;\r
+\r
+ /* Create the Creator tasks - passing in as a parameter the priority at which\r
+ the suicidal tasks should be created. */\r
+ puxPriority = ( unsigned portBASE_TYPE * ) pvPortMalloc( sizeof( unsigned portBASE_TYPE ) );\r
+ *puxPriority = uxPriority;\r
+\r
+ xTaskCreate( vCreateTasks, "CREATOR", deathSTACK_SIZE, ( void * ) puxPriority, uxPriority, NULL );\r
+\r
+ /* Record the number of tasks that are running now so we know if any of the\r
+ suicidal tasks have failed to be killed. */\r
+ uxTasksRunningAtStart = ( unsigned portBASE_TYPE ) uxTaskGetNumberOfTasks();\r
+ \r
+ /* FreeRTOS versions before V3.0 started the idle-task as the very\r
+ first task. The idle task was then already included in uxTasksRunningAtStart.\r
+ From FreeRTOS V3.0 on, the idle task is started when the scheduler is\r
+ started. Therefore the idle task is not yet accounted for. We correct\r
+ this by increasing uxTasksRunningAtStart by 1. */\r
+ uxTasksRunningAtStart++;\r
+}\r
+/*-----------------------------------------------------------*/\r
+ \r
+static portTASK_FUNCTION( vSuicidalTask, pvParameters )\r
+{\r
+volatile portLONG l1, l2;\r
+xTaskHandle xTaskToKill;\r
+const portTickType xDelay = ( portTickType ) 200 / portTICK_RATE_MS;\r
+\r
+ if( pvParameters != NULL )\r
+ {\r
+ /* This task is periodically created four times. Two created tasks are\r
+ passed a handle to the other task so it can kill it before killing itself.\r
+ The other task is passed in null. */\r
+ xTaskToKill = *( xTaskHandle* )pvParameters;\r
+ }\r
+ else\r
+ {\r
+ xTaskToKill = NULL;\r
+ }\r
+\r
+ for( ;; )\r
+ {\r
+ /* Do something random just to use some stack and registers. */\r
+ l1 = 2;\r
+ l2 = 89;\r
+ l2 *= l1;\r
+ vTaskDelay( xDelay );\r
+\r
+ if( xTaskToKill != NULL )\r
+ {\r
+ /* Make sure the other task has a go before we delete it. */\r
+ vTaskDelay( ( portTickType ) 0 );\r
+ /* Kill the other task that was created by vCreateTasks(). */\r
+ vTaskDelete( xTaskToKill );\r
+ /* Kill ourselves. */\r
+ vTaskDelete( NULL );\r
+ }\r
+ }\r
+}/*lint !e818 !e550 Function prototype must be as per standard for task functions. */\r
+/*-----------------------------------------------------------*/\r
+\r
+static portTASK_FUNCTION( vCreateTasks, pvParameters )\r
+{\r
+const portTickType xDelay = ( portTickType ) 1000 / portTICK_RATE_MS;\r
+unsigned portBASE_TYPE uxPriority;\r
+\r
+ uxPriority = *( unsigned portBASE_TYPE * ) pvParameters;\r
+ vPortFree( pvParameters );\r
+\r
+ for( ;; )\r
+ {\r
+ /* Just loop round, delaying then creating the four suicidal tasks. */\r
+ vTaskDelay( xDelay );\r
+\r
+ xTaskCreate( vSuicidalTask, "SUICID1", deathSTACK_SIZE, NULL, uxPriority, &xCreatedTask1 );\r
+ xTaskCreate( vSuicidalTask, "SUICID2", deathSTACK_SIZE, &xCreatedTask1, uxPriority, NULL );\r
+\r
+ xTaskCreate( vSuicidalTask, "SUICID1", deathSTACK_SIZE, NULL, uxPriority, &xCreatedTask2 );\r
+ xTaskCreate( vSuicidalTask, "SUICID2", deathSTACK_SIZE, &xCreatedTask2, uxPriority, NULL );\r
+\r
+ ++usCreationCount;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This is called to check that the creator task is still running and that there\r
+are not any more than four extra tasks. */\r
+portBASE_TYPE xIsCreateTaskStillRunning( void )\r
+{\r
+static portSHORT usLastCreationCount = -1;\r
+portBASE_TYPE xReturn = pdTRUE;\r
+static unsigned portBASE_TYPE uxTasksRunningNow;\r
+\r
+ if( usLastCreationCount == usCreationCount )\r
+ {\r
+ xReturn = pdFALSE;\r
+ }\r
+ else\r
+ {\r
+ usLastCreationCount = usCreationCount;\r
+ }\r
+ \r
+ uxTasksRunningNow = ( unsigned portBASE_TYPE ) uxTaskGetNumberOfTasks();\r
+\r
+ if( uxTasksRunningNow < uxTasksRunningAtStart )\r
+ {\r
+ xReturn = pdFALSE;\r
+ }\r
+ else if( ( uxTasksRunningNow - uxTasksRunningAtStart ) > uxMaxNumberOfExtraTasksRunning )\r
+ {\r
+ xReturn = pdFALSE;\r
+ }\r
+ else\r
+ {\r
+ /* Everything is okay. */\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+ * The first test creates three tasks - two counter tasks (one continuous count \r
+ * and one limited count) and one controller. A "count" variable is shared \r
+ * between all three tasks. The two counter tasks should never be in a "ready" \r
+ * state at the same time. The controller task runs at the same priority as \r
+ * the continuous count task, and at a lower priority than the limited count \r
+ * task.\r
+ *\r
+ * One counter task loops indefinitely, incrementing the shared count variable\r
+ * on each iteration. To ensure it has exclusive access to the variable it\r
+ * raises it's priority above that of the controller task before each \r
+ * increment, lowering it again to it's original priority before starting the\r
+ * next iteration.\r
+ *\r
+ * The other counter task increments the shared count variable on each\r
+ * iteration of it's loop until the count has reached a limit of 0xff - at\r
+ * which point it suspends itself. It will not start a new loop until the \r
+ * controller task has made it "ready" again by calling vTaskResume (). \r
+ * This second counter task operates at a higher priority than controller \r
+ * task so does not need to worry about mutual exclusion of the counter \r
+ * variable.\r
+ *\r
+ * The controller task is in two sections. The first section controls and\r
+ * monitors the continuous count task. When this section is operational the \r
+ * limited count task is suspended. Likewise, the second section controls \r
+ * and monitors the limited count task. When this section is operational the \r
+ * continuous count task is suspended.\r
+ *\r
+ * In the first section the controller task first takes a copy of the shared\r
+ * count variable. To ensure mutual exclusion on the count variable it\r
+ * suspends the continuous count task, resuming it again when the copy has been\r
+ * taken. The controller task then sleeps for a fixed period - during which\r
+ * the continuous count task will execute and increment the shared variable.\r
+ * When the controller task wakes it checks that the continuous count task\r
+ * has executed by comparing the copy of the shared variable with its current\r
+ * value. This time, to ensure mutual exclusion, the scheduler itself is \r
+ * suspended with a call to vTaskSuspendAll (). This is for demonstration \r
+ * purposes only and is not a recommended technique due to its inefficiency.\r
+ *\r
+ * After a fixed number of iterations the controller task suspends the \r
+ * continuous count task, and moves on to its second section.\r
+ *\r
+ * At the start of the second section the shared variable is cleared to zero.\r
+ * The limited count task is then woken from it's suspension by a call to\r
+ * vTaskResume (). As this counter task operates at a higher priority than\r
+ * the controller task the controller task should not run again until the\r
+ * shared variable has been counted up to the limited value causing the counter\r
+ * task to suspend itself. The next line after vTaskResume () is therefore\r
+ * a check on the shared variable to ensure everything is as expected.\r
+ *\r
+ *\r
+ * The second test consists of a couple of very simple tasks that post onto a \r
+ * queue while the scheduler is suspended. This test was added to test parts\r
+ * of the scheduler not exercised by the first test.\r
+ *\r
+ */\r
+\r
+#include <stdlib.h>\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "semphr.h"\r
+\r
+/* Demo app include files. */\r
+#include "dynamic.h"\r
+\r
+/* Function that implements the "limited count" task as described above. */\r
+static portTASK_FUNCTION_PROTO( vLimitedIncrementTask, pvParameters );\r
+\r
+/* Function that implements the "continuous count" task as described above. */\r
+static portTASK_FUNCTION_PROTO( vContinuousIncrementTask, pvParameters );\r
+\r
+/* Function that implements the controller task as described above. */\r
+static portTASK_FUNCTION_PROTO( vCounterControlTask, pvParameters );\r
+\r
+static portTASK_FUNCTION_PROTO( vQueueReceiveWhenSuspendedTask, pvParameters );\r
+static portTASK_FUNCTION_PROTO( vQueueSendWhenSuspendedTask, pvParameters );\r
+\r
+/* Demo task specific constants. */\r
+#define priSTACK_SIZE ( ( unsigned portSHORT ) 128 )\r
+#define priSLEEP_TIME ( ( portTickType ) 50 )\r
+#define priLOOPS ( 5 )\r
+#define priMAX_COUNT ( ( unsigned portLONG ) 0xff )\r
+#define priNO_BLOCK ( ( portTickType ) 0 )\r
+#define priSUSPENDED_QUEUE_LENGTH ( 1 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Handles to the two counter tasks. These could be passed in as parameters\r
+to the controller task to prevent them having to be file scope. */\r
+static xTaskHandle xContinousIncrementHandle, xLimitedIncrementHandle;\r
+\r
+/* The shared counter variable. This is passed in as a parameter to the two \r
+counter variables for demonstration purposes. */\r
+static unsigned portLONG ulCounter;\r
+\r
+/* Variables used to check that the tasks are still operating without error.\r
+Each complete iteration of the controller task increments this variable\r
+provided no errors have been found. The variable maintaining the same value\r
+is therefore indication of an error. */\r
+static unsigned portSHORT usCheckVariable = ( unsigned portSHORT ) 0;\r
+static portBASE_TYPE xSuspendedQueueSendError = pdFALSE;\r
+static portBASE_TYPE xSuspendedQueueReceiveError = pdFALSE;\r
+\r
+/* Queue used by the second test. */\r
+xQueueHandle xSuspendedTestQueue;\r
+\r
+/*-----------------------------------------------------------*/\r
+/*\r
+ * Start the three tasks as described at the top of the file.\r
+ * Note that the limited count task is given a higher priority.\r
+ */\r
+void vStartDynamicPriorityTasks( void )\r
+{\r
+ xSuspendedTestQueue = xQueueCreate( priSUSPENDED_QUEUE_LENGTH, sizeof( unsigned portLONG ) );\r
+ xTaskCreate( vContinuousIncrementTask, ( signed portCHAR * ) "CNT_INC", priSTACK_SIZE, ( void * ) &ulCounter, tskIDLE_PRIORITY, &xContinousIncrementHandle );\r
+ xTaskCreate( vLimitedIncrementTask, ( signed portCHAR * ) "LIM_INC", priSTACK_SIZE, ( void * ) &ulCounter, tskIDLE_PRIORITY + 1, &xLimitedIncrementHandle );\r
+ xTaskCreate( vCounterControlTask, ( signed portCHAR * ) "C_CTRL", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );\r
+ xTaskCreate( vQueueSendWhenSuspendedTask, ( signed portCHAR * ) "SUSP_TX", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );\r
+ xTaskCreate( vQueueReceiveWhenSuspendedTask, ( signed portCHAR * ) "SUSP_RX", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Just loops around incrementing the shared variable until the limit has been\r
+ * reached. Once the limit has been reached it suspends itself. \r
+ */\r
+static portTASK_FUNCTION( vLimitedIncrementTask, pvParameters )\r
+{\r
+unsigned portLONG *pulCounter;\r
+\r
+ /* Take a pointer to the shared variable from the parameters passed into\r
+ the task. */\r
+ pulCounter = ( unsigned portLONG * ) pvParameters;\r
+\r
+ /* This will run before the control task, so the first thing it does is\r
+ suspend - the control task will resume it when ready. */\r
+ vTaskSuspend( NULL );\r
+\r
+ for( ;; )\r
+ {\r
+ /* Just count up to a value then suspend. */\r
+ ( *pulCounter )++; \r
+ \r
+ if( *pulCounter >= priMAX_COUNT )\r
+ {\r
+ vTaskSuspend( NULL );\r
+ } \r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Just keep counting the shared variable up. The control task will suspend\r
+ * this task when it wants.\r
+ */\r
+static portTASK_FUNCTION( vContinuousIncrementTask, pvParameters )\r
+{\r
+unsigned portLONG *pulCounter;\r
+unsigned portBASE_TYPE uxOurPriority;\r
+\r
+ /* Take a pointer to the shared variable from the parameters passed into\r
+ the task. */\r
+ pulCounter = ( unsigned portLONG * ) pvParameters;\r
+\r
+ /* Query our priority so we can raise it when exclusive access to the \r
+ shared variable is required. */\r
+ uxOurPriority = uxTaskPriorityGet( NULL );\r
+\r
+ for( ;; )\r
+ {\r
+ /* Raise our priority above the controller task to ensure a context\r
+ switch does not occur while we are accessing this variable. */\r
+ vTaskPrioritySet( NULL, uxOurPriority + 1 );\r
+ ( *pulCounter )++; \r
+ vTaskPrioritySet( NULL, uxOurPriority );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Controller task as described above.\r
+ */\r
+static portTASK_FUNCTION( vCounterControlTask, pvParameters )\r
+{\r
+unsigned portLONG ulLastCounter;\r
+portSHORT sLoops;\r
+portSHORT sError = pdFALSE;\r
+\r
+ /* Just to stop warning messages. */\r
+ ( void ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ /* Start with the counter at zero. */\r
+ ulCounter = ( unsigned portLONG ) 0;\r
+\r
+ /* First section : */\r
+\r
+ /* Check the continuous count task is running. */\r
+ for( sLoops = 0; sLoops < priLOOPS; sLoops++ )\r
+ {\r
+ /* Suspend the continuous count task so we can take a mirror of the\r
+ shared variable without risk of corruption. */\r
+ vTaskSuspend( xContinousIncrementHandle );\r
+ ulLastCounter = ulCounter;\r
+ vTaskResume( xContinousIncrementHandle );\r
+ \r
+ /* Now delay to ensure the other task has processor time. */\r
+ vTaskDelay( priSLEEP_TIME );\r
+\r
+ /* Check the shared variable again. This time to ensure mutual \r
+ exclusion the whole scheduler will be locked. This is just for\r
+ demo purposes! */\r
+ vTaskSuspendAll();\r
+ {\r
+ if( ulLastCounter == ulCounter )\r
+ {\r
+ /* The shared variable has not changed. There is a problem\r
+ with the continuous count task so flag an error. */\r
+ sError = pdTRUE;\r
+ }\r
+ }\r
+ xTaskResumeAll();\r
+ }\r
+\r
+\r
+ /* Second section: */\r
+\r
+ /* Suspend the continuous counter task so it stops accessing the shared variable. */\r
+ vTaskSuspend( xContinousIncrementHandle );\r
+\r
+ /* Reset the variable. */\r
+ ulCounter = ( unsigned portLONG ) 0;\r
+\r
+ /* Resume the limited count task which has a higher priority than us.\r
+ We should therefore not return from this call until the limited count\r
+ task has suspended itself with a known value in the counter variable. */\r
+ vTaskResume( xLimitedIncrementHandle );\r
+\r
+ /* Does the counter variable have the expected value? */\r
+ if( ulCounter != priMAX_COUNT )\r
+ {\r
+ sError = pdTRUE;\r
+ }\r
+\r
+ if( sError == pdFALSE )\r
+ {\r
+ /* If no errors have occurred then increment the check variable. */\r
+ portENTER_CRITICAL();\r
+ usCheckVariable++;\r
+ portEXIT_CRITICAL();\r
+ }\r
+\r
+ /* Resume the continuous count task and do it all again. */\r
+ vTaskResume( xContinousIncrementHandle );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portTASK_FUNCTION( vQueueSendWhenSuspendedTask, pvParameters )\r
+{\r
+static unsigned portLONG ulValueToSend = ( unsigned portLONG ) 0;\r
+\r
+ /* Just to stop warning messages. */\r
+ ( void ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ vTaskSuspendAll();\r
+ {\r
+ /* We must not block while the scheduler is suspended! */\r
+ if( xQueueSend( xSuspendedTestQueue, ( void * ) &ulValueToSend, priNO_BLOCK ) != pdTRUE )\r
+ {\r
+ xSuspendedQueueSendError = pdTRUE;\r
+ }\r
+ }\r
+ xTaskResumeAll();\r
+\r
+ vTaskDelay( priSLEEP_TIME );\r
+\r
+ ++ulValueToSend;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portTASK_FUNCTION( vQueueReceiveWhenSuspendedTask, pvParameters )\r
+{\r
+static unsigned portLONG ulExpectedValue = ( unsigned portLONG ) 0, ulReceivedValue;\r
+portBASE_TYPE xGotValue;\r
+\r
+ /* Just to stop warning messages. */\r
+ ( void ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ do\r
+ {\r
+ /* Suspending the scheduler here is fairly pointless and \r
+ undesirable for a normal application. It is done here purely\r
+ to test the scheduler. The inner xTaskResumeAll() should\r
+ never return pdTRUE as the scheduler is still locked by the\r
+ outer call. */\r
+ vTaskSuspendAll();\r
+ {\r
+ vTaskSuspendAll();\r
+ {\r
+ xGotValue = xQueueReceive( xSuspendedTestQueue, ( void * ) &ulReceivedValue, priNO_BLOCK );\r
+ }\r
+ if( xTaskResumeAll() )\r
+ {\r
+ xSuspendedQueueReceiveError = pdTRUE;\r
+ }\r
+ }\r
+ xTaskResumeAll();\r
+\r
+ } while( xGotValue == pdFALSE );\r
+\r
+ if( ulReceivedValue != ulExpectedValue )\r
+ {\r
+ xSuspendedQueueReceiveError = pdTRUE;\r
+ }\r
+\r
+ ++ulExpectedValue;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Called to check that all the created tasks are still running without error. */\r
+portBASE_TYPE xAreDynamicPriorityTasksStillRunning( void )\r
+{\r
+/* Keep a history of the check variables so we know if it has been incremented \r
+since the last call. */\r
+static unsigned portSHORT usLastTaskCheck = ( unsigned portSHORT ) 0;\r
+portBASE_TYPE xReturn = pdTRUE;\r
+\r
+ /* Check the tasks are still running by ensuring the check variable\r
+ is still incrementing. */\r
+\r
+ if( usCheckVariable == usLastTaskCheck )\r
+ {\r
+ /* The check has not incremented so an error exists. */\r
+ xReturn = pdFALSE;\r
+ }\r
+\r
+ if( xSuspendedQueueSendError == pdTRUE )\r
+ {\r
+ xReturn = pdFALSE;\r
+ }\r
+\r
+ if( xSuspendedQueueReceiveError == pdTRUE )\r
+ {\r
+ xReturn = pdFALSE;\r
+ }\r
+\r
+ usLastTaskCheck = usCheckVariable;\r
+ return xReturn;\r
+}\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/**\r
+ * This version of flash .c is for use on systems that have limited stack space\r
+ * and no display facilities. The complete version can be found in the \r
+ * Demo/Common/Full directory.\r
+ * \r
+ * Three tasks are created, each of which flash an LED at a different rate. The first \r
+ * LED flashes every 200ms, the second every 400ms, the third every 600ms.\r
+ *\r
+ * The LED flash tasks provide instant visual feedback. They show that the scheduler \r
+ * is still operational.\r
+ *\r
+ * The PC port uses the standard parallel port for outputs, the Flashlite 186 port \r
+ * uses IO port F and the AVR port port B.\r
+ *\r
+ */\r
+\r
+/*\r
+Changes from V2.0.0\r
+\r
+ + Delay periods are now specified using variables and constants of\r
+ portTickType rather than unsigned portLONG.\r
+\r
+Changes from V2.5.5\r
+\r
+ + Calls to vTaskDelay() have been replaced with vTaskDelayUntil().\r
+\r
+*/\r
+\r
+#include <stdlib.h>\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo program include files. */\r
+#include "partest.h"\r
+#include "flash.h"\r
+\r
+#define ledSTACK_SIZE configMINIMAL_STACK_SIZE\r
+#define ledNUMBER_OF_LEDS ( 3 )\r
+#define ledFLASH_RATE_BASE ( ( portTickType ) 333 )\r
+\r
+/* Variable used by the created tasks to calculate the LED number to use, and\r
+the rate at which they should flash the LED. */\r
+static volatile unsigned portBASE_TYPE uxFlashTaskNumber = 0;\r
+\r
+/* The task that is created three times. */\r
+static portTASK_FUNCTION_PROTO( vLEDFlashTask, pvParameters );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vStartLEDFlashTasks( unsigned portBASE_TYPE uxPriority )\r
+{\r
+signed portBASE_TYPE xLEDTask;\r
+\r
+ /* Create the three tasks. */\r
+ for( xLEDTask = 0; xLEDTask < ledNUMBER_OF_LEDS; ++xLEDTask )\r
+ {\r
+ /* Spawn the task. */\r
+ xTaskCreate( vLEDFlashTask, ( const signed portCHAR * const ) "LEDx", ledSTACK_SIZE, NULL, uxPriority, ( xTaskHandle * ) NULL );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portTASK_FUNCTION( vLEDFlashTask, pvParameters )\r
+{\r
+portTickType xFlashRate, xLastFlashTime;\r
+unsigned portBASE_TYPE uxLED;\r
+\r
+ /* The parameters are not used. */\r
+ ( void ) pvParameters;\r
+\r
+ /* Calculate the LED and flash rate. */\r
+ portENTER_CRITICAL();\r
+ {\r
+ /* See which of the eight LED's we should use. */\r
+ uxLED = uxFlashTaskNumber;\r
+\r
+ /* Update so the next task uses the next LED. */\r
+ uxFlashTaskNumber++;\r
+ }\r
+ portEXIT_CRITICAL();\r
+\r
+ xFlashRate = ledFLASH_RATE_BASE + ( ledFLASH_RATE_BASE * ( portTickType ) uxLED );\r
+ xFlashRate /= portTICK_RATE_MS;\r
+\r
+ /* We will turn the LED on and off again in the delay period, so each\r
+ delay is only half the total period. */\r
+ xFlashRate /= ( portTickType ) 2;\r
+\r
+ /* We need to initialise xLastFlashTime prior to the first call to \r
+ vTaskDelayUntil(). */\r
+ xLastFlashTime = xTaskGetTickCount();\r
+\r
+ for(;;)\r
+ {\r
+ /* Delay for half the flash period then turn the LED on. */\r
+ vTaskDelayUntil( &xLastFlashTime, xFlashRate );\r
+ vParTestToggleLED( uxLED );\r
+\r
+ /* Delay for half the flash period then turn the LED off. */\r
+ vTaskDelayUntil( &xLastFlashTime, xFlashRate );\r
+ vParTestToggleLED( uxLED );\r
+ }\r
+} /*lint !e715 !e818 !e830 Function definition must be standard for task creation. */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+ * Creates eight tasks, each of which loops continuously performing an (emulated) \r
+ * floating point calculation.\r
+ *\r
+ * All the tasks run at the idle priority and never block or yield. This causes \r
+ * all eight tasks to time slice with the idle task. Running at the idle priority \r
+ * means that these tasks will get pre-empted any time another task is ready to run\r
+ * or a time slice occurs. More often than not the pre-emption will occur mid \r
+ * calculation, creating a good test of the schedulers context switch mechanism - a \r
+ * calculation producing an unexpected result could be a symptom of a corruption in \r
+ * the context of a task.\r
+ */\r
+\r
+#include <stdlib.h>\r
+#include <math.h>\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo program include files. */\r
+#include "flop.h"\r
+\r
+#define mathSTACK_SIZE configMINIMAL_STACK_SIZE\r
+#define mathNUMBER_OF_TASKS ( 8 )\r
+\r
+/* Four tasks, each of which performs a different floating point calculation. \r
+Each of the four is created twice. */\r
+static portTASK_FUNCTION_PROTO( vCompetingMathTask1, pvParameters );\r
+static portTASK_FUNCTION_PROTO( vCompetingMathTask2, pvParameters );\r
+static portTASK_FUNCTION_PROTO( vCompetingMathTask3, pvParameters );\r
+static portTASK_FUNCTION_PROTO( vCompetingMathTask4, pvParameters );\r
+\r
+/* These variables are used to check that all the tasks are still running. If a \r
+task gets a calculation wrong it will\r
+stop incrementing its check variable. */\r
+static volatile unsigned portSHORT usTaskCheck[ mathNUMBER_OF_TASKS ] = { ( unsigned portSHORT ) 0 };\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vStartMathTasks( unsigned portBASE_TYPE uxPriority )\r
+{\r
+ xTaskCreate( vCompetingMathTask1, ( signed portCHAR * ) "Math1", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 0 ] ), uxPriority, NULL );\r
+ xTaskCreate( vCompetingMathTask2, ( signed portCHAR * ) "Math2", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 1 ] ), uxPriority, NULL );\r
+ xTaskCreate( vCompetingMathTask3, ( signed portCHAR * ) "Math3", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 2 ] ), uxPriority, NULL );\r
+ xTaskCreate( vCompetingMathTask4, ( signed portCHAR * ) "Math4", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 3 ] ), uxPriority, NULL );\r
+ xTaskCreate( vCompetingMathTask1, ( signed portCHAR * ) "Math5", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 4 ] ), uxPriority, NULL );\r
+ xTaskCreate( vCompetingMathTask2, ( signed portCHAR * ) "Math6", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 5 ] ), uxPriority, NULL );\r
+ xTaskCreate( vCompetingMathTask3, ( signed portCHAR * ) "Math7", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 6 ] ), uxPriority, NULL );\r
+ xTaskCreate( vCompetingMathTask4, ( signed portCHAR * ) "Math8", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 7 ] ), uxPriority, NULL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portTASK_FUNCTION( vCompetingMathTask1, pvParameters )\r
+{\r
+volatile portDOUBLE d1, d2, d3, d4;\r
+volatile unsigned portSHORT *pusTaskCheckVariable;\r
+volatile portDOUBLE dAnswer;\r
+portSHORT sError = pdFALSE;\r
+\r
+ d1 = 123.4567;\r
+ d2 = 2345.6789;\r
+ d3 = -918.222;\r
+\r
+ dAnswer = ( d1 + d2 ) * d3;\r
+\r
+ /* The variable this task increments to show it is still running is passed in \r
+ as the parameter. */\r
+ pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters;\r
+\r
+ /* Keep performing a calculation and checking the result against a constant. */\r
+ for(;;)\r
+ {\r
+ d1 = 123.4567;\r
+ d2 = 2345.6789;\r
+ d3 = -918.222;\r
+\r
+ d4 = ( d1 + d2 ) * d3;\r
+\r
+ #if configUSE_PREEMPTION == 0\r
+ taskYIELD();\r
+ #endif\r
+\r
+ /* If the calculation does not match the expected constant, stop the \r
+ increment of the check variable. */\r
+ if( fabs( d4 - dAnswer ) > 0.001 )\r
+ {\r
+ sError = pdTRUE;\r
+ }\r
+\r
+ if( sError == pdFALSE )\r
+ {\r
+ /* If the calculation has always been correct, increment the check \r
+ variable so we know this task is still running okay. */\r
+ ( *pusTaskCheckVariable )++;\r
+ }\r
+\r
+ #if configUSE_PREEMPTION == 0\r
+ taskYIELD();\r
+ #endif\r
+\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portTASK_FUNCTION( vCompetingMathTask2, pvParameters )\r
+{\r
+volatile portDOUBLE d1, d2, d3, d4;\r
+volatile unsigned portSHORT *pusTaskCheckVariable;\r
+volatile portDOUBLE dAnswer;\r
+portSHORT sError = pdFALSE;\r
+\r
+ d1 = -389.38;\r
+ d2 = 32498.2;\r
+ d3 = -2.0001;\r
+\r
+ dAnswer = ( d1 / d2 ) * d3;\r
+\r
+\r
+ /* The variable this task increments to show it is still running is passed in \r
+ as the parameter. */\r
+ pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters;\r
+\r
+ /* Keep performing a calculation and checking the result against a constant. */\r
+ for( ;; )\r
+ {\r
+ d1 = -389.38;\r
+ d2 = 32498.2;\r
+ d3 = -2.0001;\r
+\r
+ d4 = ( d1 / d2 ) * d3;\r
+\r
+ #if configUSE_PREEMPTION == 0\r
+ taskYIELD();\r
+ #endif\r
+ \r
+ /* If the calculation does not match the expected constant, stop the \r
+ increment of the check variable. */\r
+ if( fabs( d4 - dAnswer ) > 0.001 )\r
+ {\r
+ sError = pdTRUE;\r
+ }\r
+\r
+ if( sError == pdFALSE )\r
+ {\r
+ /* If the calculation has always been correct, increment the check \r
+ variable so we know\r
+ this task is still running okay. */\r
+ ( *pusTaskCheckVariable )++;\r
+ }\r
+\r
+ #if configUSE_PREEMPTION == 0\r
+ taskYIELD();\r
+ #endif\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portTASK_FUNCTION( vCompetingMathTask3, pvParameters )\r
+{\r
+volatile portDOUBLE *pdArray, dTotal1, dTotal2, dDifference;\r
+volatile unsigned portSHORT *pusTaskCheckVariable;\r
+const size_t xArraySize = 10;\r
+size_t xPosition;\r
+portSHORT sError = pdFALSE;\r
+\r
+ /* The variable this task increments to show it is still running is passed in \r
+ as the parameter. */\r
+ pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters;\r
+\r
+ pdArray = ( portDOUBLE * ) pvPortMalloc( xArraySize * sizeof( portDOUBLE ) );\r
+\r
+ /* Keep filling an array, keeping a running total of the values placed in the \r
+ array. Then run through the array adding up all the values. If the two totals \r
+ do not match, stop the check variable from incrementing. */\r
+ for( ;; )\r
+ {\r
+ dTotal1 = 0.0;\r
+ dTotal2 = 0.0;\r
+\r
+ for( xPosition = 0; xPosition < xArraySize; xPosition++ )\r
+ {\r
+ pdArray[ xPosition ] = ( portDOUBLE ) xPosition + 5.5;\r
+ dTotal1 += ( portDOUBLE ) xPosition + 5.5; \r
+ }\r
+\r
+ #if configUSE_PREEMPTION == 0\r
+ taskYIELD();\r
+ #endif\r
+\r
+ for( xPosition = 0; xPosition < xArraySize; xPosition++ )\r
+ {\r
+ dTotal2 += pdArray[ xPosition ];\r
+ }\r
+\r
+ dDifference = dTotal1 - dTotal2;\r
+ if( fabs( dDifference ) > 0.001 )\r
+ {\r
+ sError = pdTRUE;\r
+ }\r
+\r
+ #if configUSE_PREEMPTION == 0\r
+ taskYIELD();\r
+ #endif\r
+\r
+ if( sError == pdFALSE )\r
+ {\r
+ /* If the calculation has always been correct, increment the check \r
+ variable so we know this task is still running okay. */\r
+ ( *pusTaskCheckVariable )++;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portTASK_FUNCTION( vCompetingMathTask4, pvParameters )\r
+{\r
+volatile portDOUBLE *pdArray, dTotal1, dTotal2, dDifference;\r
+volatile unsigned portSHORT *pusTaskCheckVariable;\r
+const size_t xArraySize = 10;\r
+size_t xPosition;\r
+portSHORT sError = pdFALSE;\r
+\r
+ /* The variable this task increments to show it is still running is passed in \r
+ as the parameter. */\r
+ pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters;\r
+\r
+ pdArray = ( portDOUBLE * ) pvPortMalloc( xArraySize * sizeof( portDOUBLE ) );\r
+\r
+ /* Keep filling an array, keeping a running total of the values placed in the \r
+ array. Then run through the array adding up all the values. If the two totals \r
+ do not match, stop the check variable from incrementing. */\r
+ for( ;; )\r
+ {\r
+ dTotal1 = 0.0;\r
+ dTotal2 = 0.0;\r
+\r
+ for( xPosition = 0; xPosition < xArraySize; xPosition++ )\r
+ {\r
+ pdArray[ xPosition ] = ( portDOUBLE ) xPosition * 12.123;\r
+ dTotal1 += ( portDOUBLE ) xPosition * 12.123; \r
+ }\r
+\r
+ #if configUSE_PREEMPTION == 0\r
+ taskYIELD();\r
+ #endif\r
+\r
+ for( xPosition = 0; xPosition < xArraySize; xPosition++ )\r
+ {\r
+ dTotal2 += pdArray[ xPosition ];\r
+ }\r
+\r
+ dDifference = dTotal1 - dTotal2;\r
+ if( fabs( dDifference ) > 0.001 )\r
+ {\r
+ sError = pdTRUE;\r
+ }\r
+\r
+ #if configUSE_PREEMPTION == 0\r
+ taskYIELD();\r
+ #endif\r
+\r
+ if( sError == pdFALSE )\r
+ {\r
+ /* If the calculation has always been correct, increment the check \r
+ variable so we know this task is still running okay. */\r
+ ( *pusTaskCheckVariable )++;\r
+ }\r
+ }\r
+} \r
+/*-----------------------------------------------------------*/\r
+\r
+/* This is called to check that all the created tasks are still running. */\r
+portBASE_TYPE xAreMathsTaskStillRunning( void )\r
+{\r
+/* Keep a history of the check variables so we know if they have been incremented \r
+since the last call. */\r
+static unsigned portSHORT usLastTaskCheck[ mathNUMBER_OF_TASKS ] = { ( unsigned portSHORT ) 0 };\r
+portBASE_TYPE xReturn = pdTRUE, xTask;\r
+\r
+ /* Check the maths tasks are still running by ensuring their check variables \r
+ are still incrementing. */\r
+ for( xTask = 0; xTask < mathNUMBER_OF_TASKS; xTask++ )\r
+ {\r
+ if( usTaskCheck[ xTask ] == usLastTaskCheck[ xTask ] )\r
+ {\r
+ /* The check has not incremented so an error exists. */\r
+ xReturn = pdFALSE;\r
+ }\r
+\r
+ usLastTaskCheck[ xTask ] = usTaskCheck[ xTask ];\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+ * This version of integer. c is for use on systems that have limited stack\r
+ * space and no display facilities. The complete version can be found in\r
+ * the Demo/Common/Full directory.\r
+ *\r
+ * As with the full version, the tasks created in this file are a good test \r
+ * of the scheduler context switch mechanism. The processor has to access \r
+ * 32bit variables in two or four chunks (depending on the processor). The low \r
+ * priority of these tasks means there is a high probability that a context \r
+ * switch will occur mid calculation. See flop. c documentation for \r
+ * more information.\r
+ *\r
+ */\r
+\r
+/*\r
+Changes from V1.2.1\r
+\r
+ + The constants used in the calculations are larger to ensure the\r
+ optimiser does not truncate them to 16 bits.\r
+\r
+Changes from V1.2.3\r
+\r
+ + uxTaskCheck is now just used as a boolean. Instead of incrementing\r
+ the variable each cycle of the task, the variable is simply set to\r
+ true. sAreIntegerMathsTaskStillRunning() sets it back to false and\r
+ expects it to have been set back to true by the time it is called\r
+ again.\r
+ + A division has been included in the calculation.\r
+*/\r
+\r
+#include <stdlib.h>\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo program include files. */\r
+#include "integer.h"\r
+\r
+/* The constants used in the calculation. */\r
+#define intgCONST1 ( ( portLONG ) 123 )\r
+#define intgCONST2 ( ( portLONG ) 234567 )\r
+#define intgCONST3 ( ( portLONG ) -3 )\r
+#define intgCONST4 ( ( portLONG ) 7 )\r
+#define intgEXPECTED_ANSWER ( ( ( intgCONST1 + intgCONST2 ) * intgCONST3 ) / intgCONST4 )\r
+\r
+#define intgSTACK_SIZE configMINIMAL_STACK_SIZE\r
+\r
+/* As this is the minimal version, we will only create one task. */\r
+#define intgNUMBER_OF_TASKS ( 1 )\r
+\r
+/* The task function. Repeatedly performs a 32 bit calculation, checking the\r
+result against the expected result. If the result is incorrect then the\r
+context switch must have caused some corruption. */\r
+static portTASK_FUNCTION_PROTO( vCompeteingIntMathTask, pvParameters );\r
+\r
+/* Variables that are set to true within the calculation task to indicate\r
+that the task is still executing. The check task sets the variable back to\r
+false, flagging an error if the variable is still false the next time it\r
+is called. */\r
+static volatile signed portBASE_TYPE xTaskCheck[ intgNUMBER_OF_TASKS ] = { ( signed portBASE_TYPE ) pdFALSE };\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vStartIntegerMathTasks( unsigned portBASE_TYPE uxPriority )\r
+{\r
+portSHORT sTask;\r
+\r
+ for( sTask = 0; sTask < intgNUMBER_OF_TASKS; sTask++ )\r
+ {\r
+ xTaskCreate( vCompeteingIntMathTask, ( const signed portCHAR * const ) "IntMath", intgSTACK_SIZE, ( void * ) &( xTaskCheck[ sTask ] ), uxPriority, ( xTaskHandle * ) NULL );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portTASK_FUNCTION( vCompeteingIntMathTask, pvParameters )\r
+{\r
+/* These variables are all effectively set to constants so they are volatile to\r
+ensure the compiler does not just get rid of them. */\r
+volatile portLONG lValue;\r
+portSHORT sError = pdFALSE;\r
+volatile signed portBASE_TYPE *pxTaskHasExecuted;\r
+\r
+ /* Set a pointer to the variable we are going to set to true each\r
+ iteration. This is also a good test of the parameter passing mechanism\r
+ within each port. */\r
+ pxTaskHasExecuted = ( volatile signed portBASE_TYPE * ) pvParameters;\r
+\r
+ /* Keep performing a calculation and checking the result against a constant. */\r
+ for( ;; )\r
+ {\r
+ /* Perform the calculation. This will store partial value in\r
+ registers, resulting in a good test of the context switch mechanism. */\r
+ lValue = intgCONST1;\r
+ lValue += intgCONST2;\r
+\r
+ /* Yield in case cooperative scheduling is being used. */\r
+ #if configUSE_PREEMPTION == 0\r
+ {\r
+ taskYIELD();\r
+ }\r
+ #endif\r
+\r
+ /* Finish off the calculation. */\r
+ lValue *= intgCONST3;\r
+ lValue /= intgCONST4;\r
+\r
+ /* If the calculation is found to be incorrect we stop setting the \r
+ TaskHasExecuted variable so the check task can see an error has \r
+ occurred. */\r
+ if( lValue != intgEXPECTED_ANSWER ) /*lint !e774 volatile used to prevent this being optimised out. */\r
+ {\r
+ sError = pdTRUE;\r
+ }\r
+\r
+ if( sError == pdFALSE )\r
+ {\r
+ /* We have not encountered any errors, so set the flag that show\r
+ we are still executing. This will be periodically cleared by\r
+ the check task. */\r
+ portENTER_CRITICAL();\r
+ *pxTaskHasExecuted = pdTRUE;\r
+ portEXIT_CRITICAL();\r
+ }\r
+\r
+ /* Yield in case cooperative scheduling is being used. */\r
+ #if configUSE_PREEMPTION == 0\r
+ {\r
+ taskYIELD();\r
+ }\r
+ #endif\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This is called to check that all the created tasks are still running. */\r
+portBASE_TYPE xAreIntegerMathsTaskStillRunning( void )\r
+{\r
+portBASE_TYPE xReturn = pdTRUE;\r
+portSHORT sTask;\r
+\r
+ /* Check the maths tasks are still running by ensuring their check variables \r
+ are still being set to true. */\r
+ for( sTask = 0; sTask < intgNUMBER_OF_TASKS; sTask++ )\r
+ {\r
+ if( xTaskCheck[ sTask ] == pdFALSE )\r
+ {\r
+ /* The check has not incremented so an error exists. */\r
+ xReturn = pdFALSE;\r
+ }\r
+\r
+ /* Reset the check variable so we can tell if it has been set by\r
+ the next time around. */\r
+ xTaskCheck[ sTask ] = pdFALSE;\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+ * Creates two sets of two tasks. The tasks within a set share a variable, access \r
+ * to which is guarded by a semaphore.\r
+ * \r
+ * Each task starts by attempting to obtain the semaphore. On obtaining a \r
+ * semaphore a task checks to ensure that the guarded variable has an expected \r
+ * value. It then clears the variable to zero before counting it back up to the \r
+ * expected value in increments of 1. After each increment the variable is checked \r
+ * to ensure it contains the value to which it was just set. When the starting \r
+ * value is again reached the task releases the semaphore giving the other task in \r
+ * the set a chance to do exactly the same thing. The starting value is high \r
+ * enough to ensure that a tick is likely to occur during the incrementing loop.\r
+ *\r
+ * An error is flagged if at any time during the process a shared variable is \r
+ * found to have a value other than that expected. Such an occurrence would \r
+ * suggest an error in the mutual exclusion mechanism by which access to the \r
+ * variable is restricted.\r
+ *\r
+ * The first set of two tasks poll their semaphore. The second set use blocking \r
+ * calls.\r
+ *\r
+ */\r
+\r
+\r
+#include <stdlib.h>\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "semphr.h"\r
+\r
+/* Demo app include files. */\r
+#include "semtest.h"\r
+\r
+/* The value to which the shared variables are counted. */\r
+#define semtstBLOCKING_EXPECTED_VALUE ( ( unsigned portLONG ) 0xfff )\r
+#define semtstNON_BLOCKING_EXPECTED_VALUE ( ( unsigned portLONG ) 0xff )\r
+\r
+#define semtstSTACK_SIZE configMINIMAL_STACK_SIZE\r
+\r
+#define semtstNUM_TASKS ( 4 )\r
+\r
+#define semtstDELAY_FACTOR ( ( portTickType ) 10 )\r
+\r
+/* The task function as described at the top of the file. */\r
+static portTASK_FUNCTION_PROTO( prvSemaphoreTest, pvParameters );\r
+\r
+/* Structure used to pass parameters to each task. */\r
+typedef struct SEMAPHORE_PARAMETERS\r
+{\r
+ xSemaphoreHandle xSemaphore;\r
+ volatile unsigned portLONG *pulSharedVariable;\r
+ portTickType xBlockTime;\r
+} xSemaphoreParameters;\r
+\r
+/* Variables used to check that all the tasks are still running without errors. */\r
+static volatile portSHORT sCheckVariables[ semtstNUM_TASKS ] = { 0 };\r
+static volatile portSHORT sNextCheckVariable = 0;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vStartSemaphoreTasks( unsigned portBASE_TYPE uxPriority )\r
+{\r
+xSemaphoreParameters *pxFirstSemaphoreParameters, *pxSecondSemaphoreParameters;\r
+const portTickType xBlockTime = ( portTickType ) 100;\r
+\r
+ /* Create the structure used to pass parameters to the first two tasks. */\r
+ pxFirstSemaphoreParameters = ( xSemaphoreParameters * ) pvPortMalloc( sizeof( xSemaphoreParameters ) );\r
+\r
+ if( pxFirstSemaphoreParameters != NULL )\r
+ {\r
+ /* Create the semaphore used by the first two tasks. */\r
+ vSemaphoreCreateBinary( pxFirstSemaphoreParameters->xSemaphore );\r
+\r
+ if( pxFirstSemaphoreParameters->xSemaphore != NULL )\r
+ {\r
+ /* Create the variable which is to be shared by the first two tasks. */\r
+ pxFirstSemaphoreParameters->pulSharedVariable = ( unsigned portLONG * ) pvPortMalloc( sizeof( unsigned portLONG ) );\r
+\r
+ /* Initialise the share variable to the value the tasks expect. */\r
+ *( pxFirstSemaphoreParameters->pulSharedVariable ) = semtstNON_BLOCKING_EXPECTED_VALUE;\r
+\r
+ /* The first two tasks do not block on semaphore calls. */\r
+ pxFirstSemaphoreParameters->xBlockTime = ( portTickType ) 0;\r
+\r
+ /* Spawn the first two tasks. As they poll they operate at the idle priority. */\r
+ xTaskCreate( prvSemaphoreTest, ( signed portCHAR * ) "PolSEM1", semtstSTACK_SIZE, ( void * ) pxFirstSemaphoreParameters, tskIDLE_PRIORITY, ( xTaskHandle * ) NULL );\r
+ xTaskCreate( prvSemaphoreTest, ( signed portCHAR * ) "PolSEM2", semtstSTACK_SIZE, ( void * ) pxFirstSemaphoreParameters, tskIDLE_PRIORITY, ( xTaskHandle * ) NULL );\r
+ }\r
+ }\r
+\r
+ /* Do exactly the same to create the second set of tasks, only this time \r
+ provide a block time for the semaphore calls. */\r
+ pxSecondSemaphoreParameters = ( xSemaphoreParameters * ) pvPortMalloc( sizeof( xSemaphoreParameters ) );\r
+ if( pxSecondSemaphoreParameters != NULL )\r
+ {\r
+ vSemaphoreCreateBinary( pxSecondSemaphoreParameters->xSemaphore );\r
+\r
+ if( pxSecondSemaphoreParameters->xSemaphore != NULL )\r
+ {\r
+ pxSecondSemaphoreParameters->pulSharedVariable = ( unsigned portLONG * ) pvPortMalloc( sizeof( unsigned portLONG ) );\r
+ *( pxSecondSemaphoreParameters->pulSharedVariable ) = semtstBLOCKING_EXPECTED_VALUE;\r
+ pxSecondSemaphoreParameters->xBlockTime = xBlockTime / portTICK_RATE_MS;\r
+\r
+ xTaskCreate( prvSemaphoreTest, ( signed portCHAR * ) "BlkSEM1", semtstSTACK_SIZE, ( void * ) pxSecondSemaphoreParameters, uxPriority, ( xTaskHandle * ) NULL );\r
+ xTaskCreate( prvSemaphoreTest, ( signed portCHAR * ) "BlkSEM2", semtstSTACK_SIZE, ( void * ) pxSecondSemaphoreParameters, uxPriority, ( xTaskHandle * ) NULL );\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portTASK_FUNCTION( prvSemaphoreTest, pvParameters )\r
+{\r
+xSemaphoreParameters *pxParameters;\r
+volatile unsigned portLONG *pulSharedVariable, ulExpectedValue;\r
+unsigned portLONG ulCounter;\r
+portSHORT sError = pdFALSE, sCheckVariableToUse;\r
+\r
+ /* See which check variable to use. sNextCheckVariable is not semaphore \r
+ protected! */\r
+ portENTER_CRITICAL();\r
+ sCheckVariableToUse = sNextCheckVariable;\r
+ sNextCheckVariable++;\r
+ portEXIT_CRITICAL();\r
+\r
+ /* A structure is passed in as the parameter. This contains the shared \r
+ variable being guarded. */\r
+ pxParameters = ( xSemaphoreParameters * ) pvParameters;\r
+ pulSharedVariable = pxParameters->pulSharedVariable;\r
+\r
+ /* If we are blocking we use a much higher count to ensure loads of context\r
+ switches occur during the count. */\r
+ if( pxParameters->xBlockTime > ( portTickType ) 0 )\r
+ {\r
+ ulExpectedValue = semtstBLOCKING_EXPECTED_VALUE;\r
+ }\r
+ else\r
+ {\r
+ ulExpectedValue = semtstNON_BLOCKING_EXPECTED_VALUE;\r
+ }\r
+\r
+ for( ;; )\r
+ {\r
+ /* Try to obtain the semaphore. */\r
+ if( xSemaphoreTake( pxParameters->xSemaphore, pxParameters->xBlockTime ) == pdPASS )\r
+ {\r
+ /* We have the semaphore and so expect any other tasks using the\r
+ shared variable to have left it in the state we expect to find\r
+ it. */\r
+ if( *pulSharedVariable != ulExpectedValue )\r
+ {\r
+ sError = pdTRUE;\r
+ }\r
+ \r
+ /* Clear the variable, then count it back up to the expected value\r
+ before releasing the semaphore. Would expect a context switch or\r
+ two during this time. */\r
+ for( ulCounter = ( unsigned portLONG ) 0; ulCounter <= ulExpectedValue; ulCounter++ )\r
+ {\r
+ *pulSharedVariable = ulCounter;\r
+ if( *pulSharedVariable != ulCounter )\r
+ {\r
+ sError = pdTRUE;\r
+ }\r
+ }\r
+\r
+ /* Release the semaphore, and if no errors have occurred increment the check\r
+ variable. */\r
+ if( xSemaphoreGive( pxParameters->xSemaphore ) == pdFALSE )\r
+ {\r
+ sError = pdTRUE;\r
+ }\r
+\r
+ if( sError == pdFALSE )\r
+ {\r
+ if( sCheckVariableToUse < semtstNUM_TASKS )\r
+ {\r
+ ( sCheckVariables[ sCheckVariableToUse ] )++;\r
+ }\r
+ }\r
+\r
+ /* If we have a block time then we are running at a priority higher\r
+ than the idle priority. This task takes a long time to complete\r
+ a cycle (deliberately so to test the guarding) so will be starving\r
+ out lower priority tasks. Block for some time to allow give lower\r
+ priority tasks some processor time. */\r
+ vTaskDelay( pxParameters->xBlockTime * semtstDELAY_FACTOR );\r
+ }\r
+ else\r
+ {\r
+ if( pxParameters->xBlockTime == ( portTickType ) 0 )\r
+ {\r
+ /* We have not got the semaphore yet, so no point using the\r
+ processor. We are not blocking when attempting to obtain the\r
+ semaphore. */\r
+ taskYIELD();\r
+ }\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This is called to check that all the created tasks are still running. */\r
+portBASE_TYPE xAreSemaphoreTasksStillRunning( void )\r
+{\r
+static portSHORT sLastCheckVariables[ semtstNUM_TASKS ] = { 0 };\r
+portBASE_TYPE xTask, xReturn = pdTRUE;\r
+\r
+ for( xTask = 0; xTask < semtstNUM_TASKS; xTask++ )\r
+ {\r
+ if( sLastCheckVariables[ xTask ] == sCheckVariables[ xTask ] )\r
+ {\r
+ xReturn = pdFALSE;\r
+ }\r
+\r
+ sLastCheckVariables[ xTask ] = sCheckVariables[ xTask ];\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef BLOCK_Q_H\r
+#define BLOCK_Q_H\r
+\r
+void vStartBlockingQueueTasks( unsigned portBASE_TYPE uxPriority );\r
+portBASE_TYPE xAreBlockingQueuesStillRunning( void );\r
+\r
+#endif\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef POLLED_Q_H\r
+#define POLLED_Q_H\r
+\r
+void vStartPolledQueueTasks( unsigned portBASE_TYPE uxPriority );\r
+portBASE_TYPE xArePollingQueuesStillRunning( void );\r
+\r
+#endif\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef COMTEST_H\r
+#define COMTEST_H\r
+\r
+void vAltStartComTestTasks( unsigned portBASE_TYPE uxPriority, unsigned portLONG ulBaudRate, unsigned portBASE_TYPE uxLED );\r
+void vStartComTestTasks( unsigned portBASE_TYPE uxPriority, eCOMPort ePort, eBaud eBaudRate );\r
+portBASE_TYPE xAreComTestTasksStillRunning( void );\r
+\r
+#endif\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef COMTEST_H\r
+#define COMTEST_H\r
+\r
+void vAltStartComTestTasks( unsigned portBASE_TYPE uxPriority, unsigned portLONG ulBaudRate, unsigned portBASE_TYPE uxLED );\r
+portBASE_TYPE xAreComTestTasksStillRunning( void );\r
+\r
+#endif\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef CRFLASH_LED_H\r
+#define CRFLASH_LED_H\r
+\r
+/*\r
+ * Create the co-routines used to flash the LED's at different rates.\r
+ *\r
+ * @param uxPriority The number of 'fixed delay' co-routines to create. This\r
+ * also effects the number of LED's that will be utilised. For example,\r
+ * passing in 3 will cause LED's 0 to 2 to be utilised.\r
+ */\r
+void vStartFlashCoRoutines( unsigned portBASE_TYPE uxPriority );\r
+\r
+/*\r
+ * Return pdPASS or pdFAIL depending on whether an error has been detected\r
+ * or not.\r
+ */\r
+portBASE_TYPE xAreFlashCoRoutinesStillRunning( void );\r
+\r
+#endif\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef CRHOOK_H\r
+#define CRHOOK_H\r
+\r
+/*\r
+ * Create the co-routines used to communicate wit the tick hook.\r
+ */\r
+void vStartHookCoRoutines( void );\r
+\r
+/*\r
+ * Return pdPASS or pdFAIL depending on whether an error has been detected\r
+ * or not.\r
+ */\r
+portBASE_TYPE xAreHookCoRoutinesStillRunning( void );\r
+\r
+#endif\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef SUICIDE_TASK_H\r
+#define SUICIDE_TASK_H\r
+\r
+void vCreateSuicidalTasks( unsigned portBASE_TYPE uxPriority );\r
+portBASE_TYPE xIsCreateTaskStillRunning( void );\r
+\r
+#endif\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef DYNAMIC_MANIPULATION_H\r
+#define DYNAMIC_MANIPULATION_H\r
+\r
+void vStartDynamicPriorityTasks( void );\r
+portBASE_TYPE xAreDynamicPriorityTasksStillRunning( void );\r
+\r
+#endif\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef FILE_IO_H\r
+#define FILE_OI_H\r
+\r
+void vDisplayMessage( const portCHAR * const pcMessageToPrint );\r
+void vWriteMessageToDisk( const portCHAR * const pcMessage );\r
+void vWriteBufferToDisk( const portCHAR * const pcBuffer, unsigned portLONG ulBufferLength );\r
+\r
+#endif\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef FLASH_LED_H\r
+#define FLASH_LED_H\r
+\r
+void vStartLEDFlashTasks( unsigned portBASE_TYPE uxPriority );\r
+\r
+#endif\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef FLOP_TASKS_H\r
+#define FLOP_TASKS_H\r
+\r
+void vStartMathTasks( unsigned portBASE_TYPE uxPriority );\r
+portBASE_TYPE xAreMathsTaskStillRunning( void );\r
+\r
+#endif\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef INTEGER_TASKS_H\r
+#define INTEGER_TASKS_H\r
+\r
+void vStartIntegerMathTasks( unsigned portBASE_TYPE uxPriority );\r
+portBASE_TYPE xAreIntegerMathsTaskStillRunning( void );\r
+\r
+#endif\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef EVENTS_TEST_H\r
+#define EVENTS_TEST_H\r
+\r
+void vStartMultiEventTasks( void );\r
+portBASE_TYPE xAreMultiEventTasksStillRunning( void );\r
+\r
+#endif\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef PARTEST_H\r
+#define PARTEST_H\r
+\r
+#define partstDEFAULT_PORT_ADDRESS ( ( unsigned portSHORT ) 0x378 )\r
+\r
+void vParTestInitialise( void );\r
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue );\r
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED );\r
+\r
+#endif\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef PRINT_H\r
+#define PRINT_H\r
+\r
+void vPrintInitialise( void );\r
+void vPrintDisplayMessage( const portCHAR * const * pcMessageToSend );\r
+const portCHAR *pcPrintGetNextMessage( portTickType xPrintRate );\r
+\r
+#endif\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef SEMAPHORE_TEST_H\r
+#define SEMAPHORE_TEST_H\r
+\r
+void vStartSemaphoreTasks( unsigned portBASE_TYPE uxPriority );\r
+portBASE_TYPE xAreSemaphoreTasksStillRunning( void );\r
+\r
+#endif\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef SERIAL_COMMS_H\r
+#define SERIAL_COMMS_H\r
+\r
+typedef void * xComPortHandle;\r
+\r
+typedef enum\r
+{ \r
+ serCOM1, \r
+ serCOM2, \r
+ serCOM3, \r
+ serCOM4, \r
+ serCOM5, \r
+ serCOM6, \r
+ serCOM7, \r
+ serCOM8 \r
+} eCOMPort;\r
+\r
+typedef enum \r
+{ \r
+ serNO_PARITY, \r
+ serODD_PARITY, \r
+ serEVEN_PARITY, \r
+ serMARK_PARITY, \r
+ serSPACE_PARITY \r
+} eParity;\r
+\r
+typedef enum \r
+{ \r
+ serSTOP_1, \r
+ serSTOP_2 \r
+} eStopBits;\r
+\r
+typedef enum \r
+{ \r
+ serBITS_5, \r
+ serBITS_6, \r
+ serBITS_7, \r
+ serBITS_8 \r
+} eDataBits;\r
+\r
+typedef enum \r
+{ \r
+ ser50, \r
+ ser75, \r
+ ser110, \r
+ ser134, \r
+ ser150, \r
+ ser200,\r
+ ser300, \r
+ ser600, \r
+ ser1200, \r
+ ser1800, \r
+ ser2400, \r
+ ser4800,\r
+ ser9600, \r
+ ser19200, \r
+ ser38400, \r
+ ser57600, \r
+ ser115200\r
+} eBaud;\r
+\r
+xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength );\r
+xComPortHandle xSerialPortInit( eCOMPort ePort, eBaud eWantedBaud, eParity eWantedParity, eDataBits eWantedDataBits, eStopBits eWantedStopBits, unsigned portBASE_TYPE uxBufferLength );\r
+void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength );\r
+signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime );\r
+signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime );\r
+portBASE_TYPE xSerialWaitForSemaphore( xComPortHandle xPort );\r
+void vSerialClose( xComPortHandle xPort );\r
+\r
+#endif\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+#include "c8051f120.h"\r
+\r
+/* THE VALUE FOR configSTACK_START MUST BE OBTAINED FROM THE .MEM FILE. */\r
+#define configSTACK_START ( 0x0e )\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. \r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 98000000 )\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 4 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 200 - ( unsigned portSHORT ) configSTACK_START )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 6 * 1024 ) )\r
+#define configMAX_TASK_NAME_LEN ( 8 )\r
+#define configUSE_TRACE_FACILITY 0\r
+#define configUSE_16_BIT_TICKS 1\r
+#define configIDLE_SHOULD_YIELD 1\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet 0\r
+#define INCLUDE_uxTaskPriorityGet 0\r
+#define INCLUDE_vTaskDelete 0\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 0\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+# FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+#\r
+# This file is part of the FreeRTOS distribution.\r
+#\r
+# FreeRTOS is free software; you can redistribute it and/or modify\r
+# it under the terms of the GNU General Public License as published by\r
+# the Free Software Foundation; either version 2 of the License, or\r
+# (at your option) any later version.\r
+#\r
+# FreeRTOS is distributed in the hope that it will be useful,\r
+# but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+# GNU General Public License for more details.\r
+#\r
+# You should have received a copy of the GNU General Public License\r
+# along with FreeRTOS; if not, write to the Free Software\r
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+#\r
+# A special exception to the GPL can be applied should you wish to distribute\r
+# a combined work that includes FreeRTOS, without being obliged to provide\r
+# the source code for any proprietary components. See the licensing section \r
+# of http://www.FreeRTOS.org for full details of how and when the exception\r
+# can be applied.\r
+#\r
+# ***************************************************************************\r
+# See http://www.FreeRTOS.org for documentation, latest information, license \r
+# and contact details. Please ensure to read the configuration and relevant \r
+# port sections of the online documentation.\r
+# ***************************************************************************\r
+\r
+\r
+CC=sdcc\r
+NO_OPT=--nogcse --noinvariant --noinduction --nojtbound --noloopreverse --nolabelopt --nooverlay --peep-asm\r
+DEBUG=--debug\r
+\r
+CFLAGS=--model-large -I. -I../Common/include -I../include -I../../Source/include \\r
+ -DSDCC_CYGNAL $(DEBUG) --less-pedantic --xram-size 8448 --stack-auto \\r
+ --no-peep --int-long-reent --float-reent\r
+\r
+DEMO_DIR = ../Common\r
+SOURCE_DIR = ../../Source\r
+PORT_DIR = ../../Source/portable/SDCC/Cygnal\r
+\r
+SRC = \\r
+ParTest/ParTest.c \\r
+serial/serial.c \\r
+$(DEMO_DIR)/Full/flash.c \\r
+$(DEMO_DIR)/Full/print.c \\r
+$(DEMO_DIR)/Minimal/integer.c \\r
+$(DEMO_DIR)/Minimal/PollQ.c \\r
+$(DEMO_DIR)/Minimal/comtest.c \\r
+$(DEMO_DIR)/Full/semtest.c \\r
+$(SOURCE_DIR)/tasks.c \\r
+$(SOURCE_DIR)/queue.c \\r
+$(SOURCE_DIR)/list.c \\r
+$(SOURCE_DIR)/portable/MemMang/heap_1.c \\r
+$(PORT_DIR)/port.c\r
+\r
+\r
+# Define all object files.\r
+OBJ = $(SRC:.c=.rel)\r
+\r
+\r
+\r
+\r
+\r
+######################################\r
+# THIS VERSION WILL ONLY BUILD FILES THAT HAVE CHANGED, BUT MAY HAVE A DANGEROUS\r
+# COMMAND LINE. IT WORKS FINE UNDER WINDOWS, BUT I HAVE COMMENTED IT OUT IN\r
+# CASE IT CAUSES PROBLEMS ON OTHER SYSTEMS.\r
+\r
+#main : main.c Makefile ../../Source/portable/SDCC/Cygnal/portmacro.h $(OBJ)\r
+# $(CC) $(CFLAGS) main.c $(OBJ)\r
+\r
+#%.rel : %.c Makefile ../../Source/portable/SDCC/Cygnal/portmacro.h\r
+# $(CC) -c $(CFLAGS) -o$< $<\r
+\r
+\r
+\r
+\r
+\r
+######################################\r
+# INSTEAD OF THE FOUR LINES ABOVE, THIS VERSION CAN BE USED BUT WILL CAUSE ALL\r
+# FILES TO BUILD EVERY TIME.\r
+\r
+main : main.c Makefile ../../Source/portable/SDCC/Cygnal/portmacro.h $(OBJ)\r
+ $(CC) $(CFLAGS) main.c $(OBJ)\r
+\r
+%.rel : %.c Makefile ../../Source/portable/SDCC/Cygnal/portmacro.h\r
+ $(CC) -c $(CFLAGS) $<\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+ \r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+#include <c8051f120.h>\r
+\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "partest.h"\r
+\r
+#define partstPUSH_PULL ( ( unsigned portCHAR ) 0xff )\r
+#define partstALL_OUTPUTS_OFF ( ( unsigned portCHAR ) 0xff )\r
+\r
+/* LED to output is dependent on how the LED's are wired. */\r
+#define partstOUTPUT_0 ( ( unsigned portCHAR ) 0x02 )\r
+#define partstOUTPUT_1 ( ( unsigned portCHAR ) 0x08 )\r
+#define partstOUTPUT_2 ( ( unsigned portCHAR ) 0x20 )\r
+#define partstOUTPUT_3 ( ( unsigned portCHAR ) 0x01 )\r
+#define partstOUTPUT_4 ( ( unsigned portCHAR ) 0x04 )\r
+#define partstOUTPUT_5 ( ( unsigned portCHAR ) 0x10 )\r
+#define partstOUTPUT_6 ( ( unsigned portCHAR ) 0x40 )\r
+#define partstOUTPUT_7 ( ( unsigned portCHAR ) 0x80 )\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple parallel port IO routines.\r
+ *-----------------------------------------------------------*/\r
+\r
+void vParTestInitialise( void )\r
+{\r
+unsigned portCHAR ucOriginalSFRPage;\r
+\r
+ /* Remember the SFR page before it is changed so it can get set back\r
+ before the function exits. */\r
+ ucOriginalSFRPage = SFRPAGE;\r
+\r
+ /* Setup the SFR page to access the config SFR's. */\r
+ SFRPAGE = CONFIG_PAGE;\r
+\r
+ /* Set the on board LED to push pull. */\r
+ P3MDOUT |= partstPUSH_PULL;\r
+\r
+ /* Return the SFR page. */\r
+ SFRPAGE = ucOriginalSFRPage;\r
+\r
+ P3 = partstALL_OUTPUTS_OFF;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, portBASE_TYPE xValue )\r
+{\r
+portBASE_TYPE xError = pdFALSE;\r
+\r
+ vTaskSuspendAll();\r
+ {\r
+ if( xValue == pdFALSE )\r
+ {\r
+ switch( uxLED )\r
+ {\r
+ case 0 : P3 |= partstOUTPUT_0;\r
+ break;\r
+ case 1 : P3 |= partstOUTPUT_1;\r
+ break;\r
+ case 2 : P3 |= partstOUTPUT_2;\r
+ break;\r
+ case 3 : P3 |= partstOUTPUT_3;\r
+ break;\r
+ case 4 : P3 |= partstOUTPUT_4;\r
+ break;\r
+ case 5 : P3 |= partstOUTPUT_5;\r
+ break;\r
+ case 6 : P3 |= partstOUTPUT_6;\r
+ break;\r
+ case 7 : P3 |= partstOUTPUT_7;\r
+ break;\r
+ default : /* There are no other LED's wired in. */\r
+ xError = pdTRUE;\r
+ break;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ switch( uxLED )\r
+ {\r
+ case 0 : P3 &= ~partstOUTPUT_0;\r
+ break;\r
+ case 1 : P3 &= ~partstOUTPUT_1;\r
+ break;\r
+ case 2 : P3 &= ~partstOUTPUT_2;\r
+ break;\r
+ case 3 : P3 &= ~partstOUTPUT_3;\r
+ break;\r
+ case 4 : P3 &= ~partstOUTPUT_4;\r
+ break;\r
+ case 5 : P3 &= ~partstOUTPUT_5;\r
+ break;\r
+ case 6 : P3 &= ~partstOUTPUT_6;\r
+ break;\r
+ case 7 : P3 &= ~partstOUTPUT_7;\r
+ break;\r
+ default : /* There are no other LED's wired in. */\r
+ break;\r
+ }\r
+ }\r
+ }\r
+ xTaskResumeAll();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+unsigned portCHAR ucBit;\r
+portBASE_TYPE xError = pdFALSE;\r
+\r
+ vTaskSuspendAll();\r
+ {\r
+ switch( uxLED )\r
+ {\r
+ case 0 : ucBit = partstOUTPUT_0;\r
+ break;\r
+ case 1 : ucBit = partstOUTPUT_1;\r
+ break;\r
+ case 2 : ucBit = partstOUTPUT_2;\r
+ break;\r
+ case 3 : ucBit = partstOUTPUT_3;\r
+ break;\r
+ case 4 : ucBit = partstOUTPUT_4;\r
+ break;\r
+ case 5 : ucBit = partstOUTPUT_5;\r
+ break;\r
+ case 6 : ucBit = partstOUTPUT_6;\r
+ break;\r
+ case 7 : ucBit = partstOUTPUT_7;\r
+ break;\r
+ default : /* There are no other LED's wired in. */\r
+ xError = pdTRUE;\r
+ break;\r
+ }\r
+\r
+ if( xError != pdTRUE )\r
+ {\r
+ if( P3 & ucBit )\r
+ {\r
+ P3 &= ~ucBit;\r
+ }\r
+ else\r
+ {\r
+ P3 |= ucBit;\r
+ }\r
+ }\r
+ }\r
+ xTaskResumeAll();\r
+}\r
+\r
+\r
--- /dev/null
+/*-------------------------------------------------------------------------
+ Register Declarations for the Cygnal C8051F12x Processor Range
+
+ Copyright (C) 2003 - Maarten Brock, sourceforge.brock@dse.nl
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-------------------------------------------------------------------------*/
+
+#ifndef C8051F120_H
+#define C8051F120_H
+
+
+/* BYTE Registers */
+
+/* All Pages */
+sfr at 0x80 P0 ; /* PORT 0 */
+sfr at 0x81 SP ; /* STACK POINTER */
+sfr at 0x82 DPL ; /* DATA POINTER - LOW BYTE */
+sfr at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */
+sfr at 0x84 SFRPAGE ; /* SFR PAGE SELECT */
+sfr at 0x85 SFRNEXT ; /* SFR STACK NEXT PAGE */
+sfr at 0x86 SFRLAST ; /* SFR STACK LAST PAGE */
+sfr at 0x87 PCON ; /* POWER CONTROL */
+sfr at 0x90 P1 ; /* PORT 1 */
+sfr at 0xA0 P2 ; /* PORT 2 */
+sfr at 0xA8 IE ; /* INTERRUPT ENABLE */
+sfr at 0xB0 P3 ; /* PORT 3 */
+sfr at 0xB1 PSBANK ; /* FLASH BANK SELECT */
+sfr at 0xB8 IP ; /* INTERRUPT PRIORITY */
+sfr at 0xD0 PSW ; /* PROGRAM STATUS WORD */
+sfr at 0xE0 ACC ; /* ACCUMULATOR */
+sfr at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
+sfr at 0xE7 EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */
+sfr at 0xF0 B ; /* B REGISTER */
+sfr at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
+sfr at 0xF7 EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
+sfr at 0xFF WDTCN ; /* WATCHDOG TIMER CONTROL */
+
+/* Page 0x00 */
+sfr at 0x88 TCON ; /* TIMER CONTROL */
+sfr at 0x89 TMOD ; /* TIMER MODE */
+sfr at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */
+sfr at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */
+sfr at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */
+sfr at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */
+sfr at 0x8E CKCON ; /* TIMER 0/1 CLOCK CONTROL */
+sfr at 0x8F PSCTL ; /* FLASH WRITE/ERASE CONTROL */
+sfr at 0x91 SSTA0 ; /* UART 0 STATUS */
+sfr at 0x98 SCON0 ; /* UART 0 CONTROL */
+sfr at 0x98 SCON ; /* UART 0 CONTROL */
+sfr at 0x99 SBUF0 ; /* UART 0 BUFFER */
+sfr at 0x99 SBUF ; /* UART 0 BUFFER */
+sfr at 0x9A SPI0CFG ; /* SPI 0 CONFIGURATION */
+sfr at 0x9B SPI0DAT ; /* SPI 0 DATA */
+sfr at 0x9D SPI0CKR ; /* SPI 0 CLOCK RATE CONTROL */
+sfr at 0xA1 EMI0TC ; /* EMIF TIMING CONTROL */
+sfr at 0xA2 EMI0CN ; /* EMIF CONTROL */
+sfr at 0xA2 _XPAGE ; /* XDATA/PDATA PAGE */
+sfr at 0xA3 EMI0CF ; /* EMIF CONFIGURATION */
+sfr at 0xA9 SADDR0 ; /* UART 0 SLAVE ADDRESS */
+sfr at 0xB7 FLSCL ; /* FLASH SCALE */
+sfr at 0xB9 SADEN0 ; /* UART 0 SLAVE ADDRESS MASK */
+sfr at 0xBA AMX0CF ; /* ADC 0 MUX CONFIGURATION */
+sfr at 0xBB AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */
+sfr at 0xBC ADC0CF ; /* ADC 0 CONFIGURATION */
+sfr at 0xBE ADC0L ; /* ADC 0 DATA - LOW BYTE */
+sfr at 0xBF ADC0H ; /* ADC 0 DATA - HIGH BYTE */
+sfr at 0xC0 SMB0CN ; /* SMBUS 0 CONTROL */
+sfr at 0xC1 SMB0STA ; /* SMBUS 0 STATUS */
+sfr at 0xC2 SMB0DAT ; /* SMBUS 0 DATA */
+sfr at 0xC3 SMB0ADR ; /* SMBUS 0 SLAVE ADDRESS */
+sfr at 0xC4 ADC0GTL ; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */
+sfr at 0xC5 ADC0GTH ; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */
+sfr at 0xC6 ADC0LTL ; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */
+sfr at 0xC7 ADC0LTH ; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */
+sfr at 0xC8 TMR2CN ; /* TIMER 2 CONTROL */
+sfr at 0xC9 TMR2CF ; /* TIMER 2 CONFIGURATION */
+sfr at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
+sfr at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
+sfr at 0xCC TMR2L ; /* TIMER 2 - LOW BYTE */
+sfr at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */
+sfr at 0xCD TMR2H ; /* TIMER 2 - HIGH BYTE */
+sfr at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */
+sfr at 0xCF SMB0CR ; /* SMBUS 0 CLOCK RATE */
+sfr at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
+sfr at 0xD2 DAC0L ; /* DAC 0 REGISTER - LOW BYTE */
+sfr at 0xD3 DAC0H ; /* DAC 0 REGISTER - HIGH BYTE */
+sfr at 0xD4 DAC0CN ; /* DAC 0 CONTROL */
+sfr at 0xD8 PCA0CN ; /* PCA 0 COUNTER CONTROL */
+sfr at 0xD9 PCA0MD ; /* PCA 0 COUNTER MODE */
+sfr at 0xDA PCA0CPM0 ; /* PCA 0 MODULE 0 CONTROL */
+sfr at 0xDB PCA0CPM1 ; /* PCA 0 MODULE 1 CONTROL */
+sfr at 0xDC PCA0CPM2 ; /* PCA 0 MODULE 2 CONTROL */
+sfr at 0xDD PCA0CPM3 ; /* PCA 0 MODULE 3 CONTROL */
+sfr at 0xDE PCA0CPM4 ; /* PCA 0 MODULE 4 CONTROL */
+sfr at 0xDF PCA0CPM5 ; /* PCA 0 MODULE 5 CONTROL */
+sfr at 0xE1 PCA0CPL5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE - LOW BYTE */
+sfr at 0xE2 PCA0CPH5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE - HIGH BYTE */
+sfr at 0xE8 ADC0CN ; /* ADC 0 CONTROL */
+sfr at 0xE9 PCA0CPL2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE - LOW BYTE */
+sfr at 0xEA PCA0CPH2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE - HIGH BYTE */
+sfr at 0xEB PCA0CPL3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE - LOW BYTE */
+sfr at 0xEC PCA0CPH3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE - HIGH BYTE */
+sfr at 0xED PCA0CPL4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE - LOW BYTE */
+sfr at 0xEE PCA0CPH4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE - HIGH BYTE */
+sfr at 0xEF RSTSRC ; /* RESET SOURCE */
+sfr at 0xF8 SPI0CN ; /* SPI 0 CONTROL */
+sfr at 0xF9 PCA0L ; /* PCA 0 TIMER - LOW BYTE */
+sfr at 0xFA PCA0H ; /* PCA 0 TIMER - HIGH BYTE */
+sfr at 0xFB PCA0CPL0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE - LOW BYTE */
+sfr at 0xFC PCA0CPH0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE - HIGH BYTE */
+sfr at 0xFD PCA0CPL1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE - LOW BYTE */
+sfr at 0xFE PCA0CPH1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE - HIGH BYTE */
+
+/* Page 0x01 */
+sfr at 0x88 CPT0CN ; /* COMPARATOR 0 CONTROL */
+sfr at 0x89 CPT0MD ; /* COMPARATOR 0 CONFIGURATION */
+sfr at 0x98 SCON1 ; /* UART 1 CONTROL */
+sfr at 0x99 SBUF1 ; /* UART 1 BUFFER */
+sfr at 0xC8 TMR3CN ; /* TIMER 3 CONTROL */
+sfr at 0xC9 TMR3CF ; /* TIMER 3 CONFIGURATION */
+sfr at 0xCA RCAP3L ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */
+sfr at 0xCB RCAP3H ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */
+sfr at 0xCC TMR3L ; /* TIMER 3 - LOW BYTE */
+sfr at 0xCD TMR3H ; /* TIMER 3 - HIGH BYTE */
+sfr at 0xD2 DAC1L ; /* DAC 1 REGISTER - LOW BYTE */
+sfr at 0xD3 DAC1H ; /* DAC 1 REGISTER - HIGH BYTE */
+sfr at 0xD4 DAC1CN ; /* DAC 1 CONTROL */
+
+/* Page 0x02 */
+sfr at 0x88 CPT1CN ; /* COMPARATOR 1 CONTROL */
+sfr at 0x89 CPT1MD ; /* COMPARATOR 1 CONFIGURATION */
+sfr at 0xBA AMX2CF ; /* ADC 2 MUX CONFIGURATION */
+sfr at 0xBB AMX2SL ; /* ADC 2 MUX CHANNEL SELECTION */
+sfr at 0xBC ADC2CF ; /* ADC 2 CONFIGURATION */
+sfr at 0xBE ADC2 ; /* ADC 2 DATA */
+sfr at 0xC4 ADC2GT ; /* ADC 2 GREATER-THAN REGISTER */
+sfr at 0xC6 ADC2LT ; /* ADC 2 LESS-THAN REGISTER */
+sfr at 0xC8 TMR4CN ; /* TIMER 4 CONTROL */
+sfr at 0xC9 TMR4CF ; /* TIMER 4 CONFIGURATION */
+sfr at 0xCA RCAP4L ; /* TIMER 4 CAPTURE REGISTER - LOW BYTE */
+sfr at 0xCB RCAP4H ; /* TIMER 4 CAPTURE REGISTER - HIGH BYTE */
+sfr at 0xCC TMR4L ; /* TIMER 4 - LOW BYTE */
+sfr at 0xCD TMR4H ; /* TIMER 4 - HIGH BYTE */
+
+/* Page 0x02 */
+sfr at 0x91 MAC0BL ; /* MAC0 B Register Low Byte */
+sfr at 0x92 MAC0BH ; /* MAC0 B Register High Byte */
+sfr at 0x93 MAC0ACC0 ; /* MAC0 Accumulator Byte 0 (LSB) */
+sfr at 0x94 MAC0ACC1 ; /* MAC0 Accumulator Byte 1 */
+sfr at 0x95 MAC0ACC2 ; /* MAC0 Accumulator Byte 2 */
+sfr at 0x96 MAC0ACC3 ; /* MAC0 Accumulator Byte 3 (MSB) */
+sfr at 0x97 MAC0OVR ; /* MAC0 Accumulator Overflow */
+sfr at 0xC0 MAC0STA ; /* MAC0 Status Register */
+sfr at 0xC1 MAC0AL ; /* MAC0 A Register Low Byte */
+sfr at 0xC2 MAC0AH ; /* MAC0 A Register High Byte */
+sfr at 0xC3 MAC0CF ; /* MAC0 Configuration */
+sfr at 0xCE MAC0RNDL ; /* MAC0 Rounding Register Low Byte */
+sfr at 0xCF MAC0RNDH ; /* MAC0 Rounding Register High Byte */
+
+/* Page 0x0F */
+sfr at 0x88 FLSTAT ; /* FLASH STATUS */
+sfr at 0x89 PLL0CN ; /* PLL 0 CONTROL */
+sfr at 0x8A OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
+sfr at 0x8B OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */
+sfr at 0x8C OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
+sfr at 0x8D PLL0DIV ; /* PLL 0 DIVIDER */
+sfr at 0x8E PLL0MUL ; /* PLL 0 MULTIPLIER */
+sfr at 0x8F PLL0FLT ; /* PLL 0 FILTER */
+sfr at 0x96 SFRPGCN ; /* SFR PAGE CONTROL */
+sfr at 0x97 CLKSEL ; /* SYSTEM CLOCK SELECT */
+sfr at 0x9A CCH0MA ; /* CACHE MISS ACCUMULATOR */
+sfr at 0x9C P4MDOUT ; /* PORT 4 OUTPUT MODE */
+sfr at 0x9D P5MDOUT ; /* PORT 5 OUTPUT MODE */
+sfr at 0x9E P6MDOUT ; /* PORT 6 OUTPUT MODE */
+sfr at 0x9F P7MDOUT ; /* PORT 7 OUTPUT MODE */
+sfr at 0xA1 CCH0CN ; /* CACHE CONTROL */
+sfr at 0xA2 CCH0TN ; /* CACHE TUNING REGISTER */
+sfr at 0xA3 CCH0LC ; /* CACHE LOCK */
+sfr at 0xA4 P0MDOUT ; /* PORT 0 OUTPUT MODE */
+sfr at 0xA5 P1MDOUT ; /* PORT 1 OUTPUT MODE */
+sfr at 0xA6 P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */
+sfr at 0xA7 P3MDOUT ; /* PORT 3 OUTPUT MODE CONFIGURATION */
+sfr at 0xAD P1MDIN ; /* PORT 1 INPUT MODE */
+sfr at 0xB7 FLACL ; /* FLASH ACCESS LIMIT */
+sfr at 0xC8 P4 ; /* PORT 4 */
+sfr at 0xD8 P5 ; /* PORT 5 */
+sfr at 0xE1 XBR0 ; /* CROSSBAR CONFIGURATION REGISTER 0 */
+sfr at 0xE2 XBR1 ; /* CROSSBAR CONFIGURATION REGISTER 1 */
+sfr at 0xE3 XBR2 ; /* CROSSBAR CONFIGURATION REGISTER 2 */
+sfr at 0xE8 ADC2CN ; /* ADC 2 CONTROL */
+sfr at 0xE8 P6 ; /* PORT 6 */
+sfr at 0xF8 P7 ; /* PORT 7 */
+
+
+/* BIT Registers */
+
+/* P0 0x80 */
+sbit at 0x80 P0_0 ;
+sbit at 0x81 P0_1 ;
+sbit at 0x82 P0_2 ;
+sbit at 0x83 P0_3 ;
+sbit at 0x84 P0_4 ;
+sbit at 0x85 P0_5 ;
+sbit at 0x86 P0_6 ;
+sbit at 0x87 P0_7 ;
+
+/* TCON 0x88 */
+sbit at 0x88 IT0 ; /* EXT. INTERRUPT 0 TYPE */
+sbit at 0x89 IE0 ; /* EXT. INTERRUPT 0 EDGE FLAG */
+sbit at 0x8A IT1 ; /* EXT. INTERRUPT 1 TYPE */
+sbit at 0x8B IE1 ; /* EXT. INTERRUPT 1 EDGE FLAG */
+sbit at 0x8C TR0 ; /* TIMER 0 ON/OFF CONTROL */
+sbit at 0x8D TF0 ; /* TIMER 0 OVERFLOW FLAG */
+sbit at 0x8E TR1 ; /* TIMER 1 ON/OFF CONTROL */
+sbit at 0x8F TF1 ; /* TIMER 1 OVERFLOW FLAG */
+
+/* CPT0CN 0x88 */
+sbit at 0x88 CP0HYN0 ; /* COMPARATOR 0 NEGATIVE HYSTERESIS 0 */
+sbit at 0x89 CP0HYN1 ; /* COMPARATOR 0 NEGATIVE HYSTERESIS 1 */
+sbit at 0x8A CP0HYP0 ; /* COMPARATOR 0 POSITIVE HYSTERESIS 0 */
+sbit at 0x8B CP0HYP1 ; /* COMPARATOR 0 POSITIVE HYSTERESIS 1 */
+sbit at 0x8C CP0FIF ; /* COMPARATOR 0 FALLING EDGE INTERRUPT */
+sbit at 0x8D CP0RIF ; /* COMPARATOR 0 RISING EDGE INTERRUPT */
+sbit at 0x8E CP0OUT ; /* COMPARATOR 0 OUTPUT */
+sbit at 0x8F CP0EN ; /* COMPARATOR 0 ENABLE */
+
+/* CPT1CN 0x88 */
+sbit at 0x88 CP1HYN0 ; /* COMPARATOR 1 NEGATIVE HYSTERESIS 0 */
+sbit at 0x89 CP1HYN1 ; /* COMPARATOR 1 NEGATIVE HYSTERESIS 1 */
+sbit at 0x8A CP1HYP0 ; /* COMPARATOR 1 POSITIVE HYSTERESIS 0 */
+sbit at 0x8B CP1HYP1 ; /* COMPARATOR 1 POSITIVE HYSTERESIS 1 */
+sbit at 0x8C CP1FIF ; /* COMPARATOR 1 FALLING EDGE INTERRUPT */
+sbit at 0x8D CP1RIF ; /* COMPARATOR 1 RISING EDGE INTERRUPT */
+sbit at 0x8E CP1OUT ; /* COMPARATOR 1 OUTPUT */
+sbit at 0x8F CP1EN ; /* COMPARATOR 1 ENABLE */
+
+/* FLSTAT 0x88 */
+sbit at 0x88 FLHBUSY ; /* FLASH BUSY */
+
+/* SCON0 0x98 */
+sbit at 0x98 RI0 ; /* UART 0 RX INTERRUPT FLAG */
+sbit at 0x98 RI ; /* UART 0 RX INTERRUPT FLAG */
+sbit at 0x99 TI0 ; /* UART 0 TX INTERRUPT FLAG */
+sbit at 0x99 TI ; /* UART 0 TX INTERRUPT FLAG */
+sbit at 0x9A RB80 ; /* UART 0 RX BIT 8 */
+sbit at 0x9B TB80 ; /* UART 0 TX BIT 8 */
+sbit at 0x9C REN0 ; /* UART 0 RX ENABLE */
+sbit at 0x9C REN ; /* UART 0 RX ENABLE */
+sbit at 0x9D SM20 ; /* UART 0 MULTIPROCESSOR EN */
+sbit at 0x9E SM10 ; /* UART 0 MODE 1 */
+sbit at 0x9F SM00 ; /* UART 0 MODE 0 */
+
+/* SCON1 0x98 */
+sbit at 0x98 RI1 ; /* UART 1 RX INTERRUPT FLAG */
+sbit at 0x99 TI1 ; /* UART 1 TX INTERRUPT FLAG */
+sbit at 0x9A RB81 ; /* UART 1 RX BIT 8 */
+sbit at 0x9B TB81 ; /* UART 1 TX BIT 8 */
+sbit at 0x9C REN1 ; /* UART 1 RX ENABLE */
+sbit at 0x9D MCE1 ; /* UART 1 MCE */
+sbit at 0x9F S1MODE ; /* UART 1 MODE */
+
+/* IE 0xA8 */
+sbit at 0xA8 EX0 ; /* EXTERNAL INTERRUPT 0 ENABLE */
+sbit at 0xA9 ET0 ; /* TIMER 0 INTERRUPT ENABLE */
+sbit at 0xAA EX1 ; /* EXTERNAL INTERRUPT 1 ENABLE */
+sbit at 0xAB ET1 ; /* TIMER 1 INTERRUPT ENABLE */
+sbit at 0xAC ES0 ; /* UART0 INTERRUPT ENABLE */
+sbit at 0xAC ES ; /* UART0 INTERRUPT ENABLE */
+sbit at 0xAD ET2 ; /* TIMER 2 INTERRUPT ENABLE */
+sbit at 0xAF EA ; /* GLOBAL INTERRUPT ENABLE */
+
+/* IP 0xB8 */
+sbit at 0xB8 PX0 ; /* EXTERNAL INTERRUPT 0 PRIORITY */
+sbit at 0xB9 PT0 ; /* TIMER 0 PRIORITY */
+sbit at 0xBA PX1 ; /* EXTERNAL INTERRUPT 1 PRIORITY */
+sbit at 0xBB PT1 ; /* TIMER 1 PRIORITY */
+sbit at 0xBC PS ; /* SERIAL PORT PRIORITY */
+sbit at 0xBD PT2 ; /* TIMER 2 PRIORITY */
+
+/* SMB0CN 0xC0 */
+sbit at 0xC0 SMBTOE ; /* SMBUS 0 TIMEOUT ENABLE */
+sbit at 0xC1 SMBFTE ; /* SMBUS 0 FREE TIMER ENABLE */
+sbit at 0xC2 AA ; /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */
+sbit at 0xC3 SI ; /* SMBUS 0 INTERRUPT PENDING FLAG */
+sbit at 0xC4 STO ; /* SMBUS 0 STOP FLAG */
+sbit at 0xC5 STA ; /* SMBUS 0 START FLAG */
+sbit at 0xC6 ENSMB ; /* SMBUS 0 ENABLE */
+sbit at 0xC7 BUSY ; /* SMBUS 0 BUSY */
+
+/* TMR2CN 0xC8 */
+sbit at 0xC8 CPRL2 ; /* TIMER 2 CAPTURE SELECT */
+sbit at 0xC9 CT2 ; /* TIMER 2 COUNTER SELECT */
+sbit at 0xCA TR2 ; /* TIMER 2 ON/OFF CONTROL */
+sbit at 0xCB EXEN2 ; /* TIMER 2 EXTERNAL ENABLE FLAG */
+sbit at 0xCE EXF2 ; /* TIMER 2 EXTERNAL FLAG */
+sbit at 0xCF TF2 ; /* TIMER 2 OVERFLOW FLAG */
+
+/* TMR3CN 0xC8 */
+sbit at 0xC8 CPRL3 ; /* TIMER 3 CAPTURE SELECT */
+sbit at 0xC9 CT3 ; /* TIMER 3 COUNTER SELECT */
+sbit at 0xCA TR3 ; /* TIMER 3 ON/OFF CONTROL */
+sbit at 0xCB EXEN3 ; /* TIMER 3 EXTERNAL ENABLE FLAG */
+sbit at 0xCE EXF3 ; /* TIMER 3 EXTERNAL FLAG */
+sbit at 0xCF TF3 ; /* TIMER 3 OVERFLOW FLAG */
+
+/* TMR4CN 0xC8 */
+sbit at 0xC8 CPRL4 ; /* TIMER 4 CAPTURE SELECT */
+sbit at 0xC9 CT4 ; /* TIMER 4 COUNTER SELECT */
+sbit at 0xCA TR4 ; /* TIMER 4 ON/OFF CONTROL */
+sbit at 0xCB EXEN4 ; /* TIMER 4 EXTERNAL ENABLE FLAG */
+sbit at 0xCE EXF4 ; /* TIMER 4 EXTERNAL FLAG */
+sbit at 0xCF TF4 ; /* TIMER 4 OVERFLOW FLAG */
+
+/* P4 0xC8 */
+sbit at 0xC8 P4_0 ;
+sbit at 0xC9 P4_1 ;
+sbit at 0xCA P4_2 ;
+sbit at 0xCB P4_3 ;
+sbit at 0xCC P4_4 ;
+sbit at 0xCD P4_5 ;
+sbit at 0xCE P4_6 ;
+sbit at 0xCF P4_7 ;
+
+/* PSW 0xD0 */
+sbit at 0xD0 P ; /* ACCUMULATOR PARITY FLAG */
+sbit at 0xD1 F1 ; /* USER FLAG 1 */
+sbit at 0xD2 OV ; /* OVERFLOW FLAG */
+sbit at 0xD3 RS0 ; /* REGISTER BANK SELECT 0 */
+sbit at 0xD4 RS1 ; /* REGISTER BANK SELECT 1 */
+sbit at 0xD5 F0 ; /* USER FLAG 0 */
+sbit at 0xD6 AC ; /* AUXILIARY CARRY FLAG */
+sbit at 0xD7 CY ; /* CARRY FLAG */
+
+/* PCA0CN D8H */
+sbit at 0xD8 CCF0 ; /* PCA 0 MODULE 0 INTERRUPT FLAG */
+sbit at 0xD9 CCF1 ; /* PCA 0 MODULE 1 INTERRUPT FLAG */
+sbit at 0xDA CCF2 ; /* PCA 0 MODULE 2 INTERRUPT FLAG */
+sbit at 0xDB CCF3 ; /* PCA 0 MODULE 3 INTERRUPT FLAG */
+sbit at 0xDC CCF4 ; /* PCA 0 MODULE 4 INTERRUPT FLAG */
+sbit at 0xDD CCF5 ; /* PCA 0 MODULE 5 INTERRUPT FLAG */
+sbit at 0xDE CR ; /* PCA 0 COUNTER RUN CONTROL BIT */
+sbit at 0xDF CF ; /* PCA 0 COUNTER OVERFLOW FLAG */
+
+/* P5 0xD8 */
+sbit at 0xD8 P5_0 ;
+sbit at 0xD9 P5_1 ;
+sbit at 0xDA P5_2 ;
+sbit at 0xDB P5_3 ;
+sbit at 0xDC P5_4 ;
+sbit at 0xDD P5_5 ;
+sbit at 0xDE P5_6 ;
+sbit at 0xDF P5_7 ;
+
+/* ADC0CN E8H */
+sbit at 0xE8 AD0LJST ; /* ADC 0 RIGHT JUSTIFY DATA BIT */
+sbit at 0xE9 AD0WINT ; /* ADC 0 WINDOW INTERRUPT FLAG */
+sbit at 0xEA AD0CM0 ; /* ADC 0 CONVERT START MODE BIT 0 */
+sbit at 0xEB AD0CM1 ; /* ADC 0 CONVERT START MODE BIT 1 */
+sbit at 0xEC AD0BUSY ; /* ADC 0 BUSY FLAG */
+sbit at 0xED AD0INT ; /* ADC 0 EOC INTERRUPT FLAG */
+sbit at 0xEE AD0TM ; /* ADC 0 TRACK MODE */
+sbit at 0xEF AD0EN ; /* ADC 0 ENABLE */
+
+/* ADC2CN E8H */
+sbit at 0xE8 AD2WINT ; /* ADC 2 WINDOW INTERRUPT FLAG */
+sbit at 0xE9 AD2CM0 ; /* ADC 2 CONVERT START MODE BIT 0 */
+sbit at 0xEA AD2CM1 ; /* ADC 2 CONVERT START MODE BIT 1 */
+sbit at 0xEB AD2CM2 ; /* ADC 2 CONVERT START MODE BIT 2 */
+sbit at 0xEC AD2BUSY ; /* ADC 2 BUSY FLAG */
+sbit at 0xED AD2INT ; /* ADC 2 EOC INTERRUPT FLAG */
+sbit at 0xEE AD2TM ; /* ADC 2 TRACK MODE */
+sbit at 0xEF AD2EN ; /* ADC 2 ENABLE */
+
+/* P6 0xE8 */
+sbit at 0xE8 P6_0 ;
+sbit at 0xE9 P6_1 ;
+sbit at 0xEA P6_2 ;
+sbit at 0xEB P6_3 ;
+sbit at 0xEC P6_4 ;
+sbit at 0xED P6_5 ;
+sbit at 0xEE P6_6 ;
+sbit at 0xEF P6_7 ;
+
+/* SPI0CN F8H */
+sbit at 0xF8 SPIEN ; /* SPI 0 SPI ENABLE */
+sbit at 0xF9 TXBMT ; /* SPI 0 TX BUFFER EMPTY FLAG */
+sbit at 0xFA NSSMD0 ; /* SPI 0 SLAVE SELECT MODE 0 */
+sbit at 0xFB NSSMD1 ; /* SPI 0 SLAVE SELECT MODE 1 */
+sbit at 0xFC RXOVRN ; /* SPI 0 RX OVERRUN FLAG */
+sbit at 0xFD MODF ; /* SPI 0 MODE FAULT FLAG */
+sbit at 0xFE WCOL ; /* SPI 0 WRITE COLLISION FLAG */
+sbit at 0xFF SPIF ; /* SPI 0 INTERRUPT FLAG */
+
+/* P7 0xF8 */
+sbit at 0xF8 P7_0 ;
+sbit at 0xF9 P7_1 ;
+sbit at 0xFA P7_2 ;
+sbit at 0xFB P7_3 ;
+sbit at 0xFC P7_4 ;
+sbit at 0xFD P7_5 ;
+sbit at 0xFE P7_6 ;
+sbit at 0xFF P7_7 ;
+
+
+/* Predefined SFR Bit Masks */
+
+#define IDLE 0x01 /* PCON */
+#define STOP 0x02 /* PCON */
+#define ECCF 0x01 /* PCA0CPMn */
+#define PWM 0x02 /* PCA0CPMn */
+#define TOG 0x04 /* PCA0CPMn */
+#define MAT 0x08 /* PCA0CPMn */
+#define CAPN 0x10 /* PCA0CPMn */
+#define CAPP 0x20 /* PCA0CPMn */
+#define ECOM 0x40 /* PCA0CPMn */
+#define PWM16 0x80 /* PCA0CPMn */
+#define PORSF 0x02 /* RSTSRC */
+#define SWRSF 0x10 /* RSTSRC */
+
+
+/* SFR PAGE DEFINITIONS */
+
+#define CONFIG_PAGE 0x0F /* SYSTEM AND PORT CONFIGURATION PAGE */
+#define LEGACY_PAGE 0x00 /* LEGACY SFR PAGE */
+#define TIMER01_PAGE 0x00 /* TIMER 0 AND TIMER 1 */
+#define CPT0_PAGE 0x01 /* COMPARATOR 0 */
+#define CPT1_PAGE 0x02 /* COMPARATOR 1 */
+#define UART0_PAGE 0x00 /* UART 0 */
+#define UART1_PAGE 0x01 /* UART 1 */
+#define SPI0_PAGE 0x00 /* SPI 0 */
+#define EMI0_PAGE 0x00 /* EXTERNAL MEMORY INTERFACE */
+#define ADC0_PAGE 0x00 /* ADC 0 */
+#define ADC2_PAGE 0x02 /* ADC 2 */
+#define SMB0_PAGE 0x00 /* SMBUS 0 */
+#define TMR2_PAGE 0x00 /* TIMER 2 */
+#define TMR3_PAGE 0x01 /* TIMER 3 */
+#define TMR4_PAGE 0x02 /* TIMER 4 */
+#define DAC0_PAGE 0x00 /* DAC 0 */
+#define DAC1_PAGE 0x01 /* DAC 1 */
+#define PCA0_PAGE 0x00 /* PCA 0 */
+#define PLL0_PAGE 0x0F /* PLL 0 */
+
+#endif
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+ * Creates the demo application tasks, then starts the scheduler. The WEB\r
+ * documentation provides more details of the demo application tasks.\r
+ * \r
+ * Main. c also creates four other tasks:\r
+ * \r
+ * 1) vErrorChecks()\r
+ * This only executes every few seconds but has the highest priority so is \r
+ * guaranteed to get processor time. Its main function is to check that all \r
+ * the standard demo application tasks are still operational and have not\r
+ * experienced any errors. vErrorChecks() will toggle the on board LED\r
+ * every mainNO_ERROR_FLASH_PERIOD milliseconds if none of the demo application\r
+ * tasks have reported an error. Should any task report an error at any time\r
+ * the rate at which the on board LED is toggled is increased to \r
+ * mainERROR_FLASH_PERIOD - providing visual feedback that something has gone\r
+ * wrong.\r
+ *\r
+ * 2) vRegisterCheck()\r
+ * This is a very simple task that checks that all the registers are always\r
+ * in their expected state. The task only makes use of the A register, so\r
+ * all the other registers should always contain their initial values.\r
+ * An incorrect value indicates an error in the context switch mechanism.\r
+ * The task operates at the idle priority so will be preempted regularly.\r
+ * Any error will cause the toggle rate of the on board LED to increase to\r
+ * mainERROR_FLASH_PERIOD milliseconds.\r
+ *\r
+ * 3 and 4) vFLOPCheck1() and vFLOPCheck2()\r
+ * These are very basic versions of the standard FLOP tasks. They are good\r
+ * at detecting errors in the context switch mechanism, and also check that\r
+ * the floating point libraries are correctly built to be re-enterant. The\r
+ * stack restrictions of the 8051 prevent the use of the standard FLOP demo\r
+ * tasks.\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdlib.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo application includes. */\r
+#include "partest.h"\r
+#include "flash.h"\r
+#include "integer.h"\r
+#include "PollQ.h"\r
+#include "comtest2.h"\r
+#include "semtest.h"\r
+\r
+/* Demo task priorities. */\r
+#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainINTEGER_PRIORITY tskIDLE_PRIORITY\r
+\r
+/* Constants required to disable the watchdog. */\r
+#define mainDISABLE_BYTE_1 ( ( unsigned portCHAR ) 0xde )\r
+#define mainDISABLE_BYTE_2 ( ( unsigned portCHAR ) 0xad )\r
+\r
+/* Constants to setup and use the on board LED. */\r
+#define ucLED_BIT ( ( unsigned portCHAR ) 0x40 )\r
+#define mainPORT_1_BIT_6 ( ( unsigned portCHAR ) 0x40 )\r
+#define mainENABLE_CROSS_BAR ( ( unsigned portCHAR ) 0x40 )\r
+\r
+/* Constants to set the clock frequency. */\r
+#define mainSELECT_INTERNAL_OSC ( ( unsigned portCHAR ) 0x80 )\r
+#define mainDIVIDE_CLOCK_BY_1 ( ( unsigned portCHAR ) 0x03 )\r
+#define mainPLL_USES_INTERNAL_OSC ( ( unsigned portCHAR ) 0x04 )\r
+#define mainFLASH_READ_TIMING ( ( unsigned portCHAR ) 0x30 )\r
+#define mainPLL_POWER_ON ( ( unsigned portCHAR ) 0x01 )\r
+#define mainPLL_NO_PREDIVIDE ( ( unsigned portCHAR ) 0x01 )\r
+#define mainPLL_FILTER ( ( unsigned portCHAR ) 0x01 )\r
+#define mainPLL_MULTIPLICATION ( ( unsigned portCHAR ) 0x04 )\r
+#define mainENABLE_PLL ( ( unsigned portCHAR ) 0x02 )\r
+#define mainPLL_LOCKED ( ( unsigned portCHAR ) 0x10 )\r
+#define mainSELECT_PLL_AS_SOURCE ( ( unsigned portCHAR ) 0x02 )\r
+\r
+/* Toggle rate for the on board LED - which is dependent on whether or not\r
+an error has been detected. */\r
+#define mainNO_ERROR_FLASH_PERIOD ( ( portTickType ) 5000 )\r
+#define mainERROR_FLASH_PERIOD ( ( portTickType ) 250 )\r
+\r
+/* Baud rate used by the serial port tasks. */\r
+#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 115200 )\r
+\r
+/* Pass an invalid LED number to the COM test task as we don't want it to flash\r
+an LED. There are only 8 LEDs (excluding the on board LED) wired in and these\r
+are all used by the flash tasks. */\r
+#define mainCOM_TEST_LED ( 200 )\r
+\r
+/* We want the Cygnal to act as much as possible as a standard 8052. */\r
+#define mainAUTO_SFR_OFF ( ( unsigned portCHAR ) 0 )\r
+\r
+/* Constants required to setup the IO pins for serial comms. */\r
+#define mainENABLE_COMS ( ( unsigned portCHAR ) 0x04 )\r
+#define mainCOMS_LINES_TO_PUSH_PULL ( ( unsigned portCHAR ) 0x03 )\r
+\r
+/* Pointer passed as a parameter to vRegisterCheck() just so it has some know\r
+values to check for in the DPH, DPL and B registers. */\r
+#define mainDUMMY_POINTER ( ( xdata void * ) 0xabcd )\r
+\r
+/* Macro that lets vErrorChecks() know that one of the tasks defined in\r
+main. c has detected an error. A critical region is used around xLatchError\r
+as it is accessed from vErrorChecks(), which has a higher priority. */ \r
+#define mainLATCH_ERROR() \\r
+{ \\r
+ portENTER_CRITICAL(); \\r
+ xLatchedError = pdTRUE; \\r
+ portEXIT_CRITICAL(); \\r
+}\r
+\r
+/*\r
+ * Setup the Cygnal microcontroller for its fastest operation. \r
+ */\r
+static void prvSetupSystemClock( void );\r
+\r
+/*\r
+ * Setup the peripherals, including the on board LED. \r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*\r
+ * Toggle the state of the on board LED. \r
+ */\r
+static void prvToggleOnBoardLED( void );\r
+\r
+/*\r
+ * See comments at the top of the file for details. \r
+ */\r
+static void vErrorChecks( void *pvParameters );\r
+\r
+/*\r
+ * See comments at the top of the file for details. \r
+ */\r
+static void vRegisterCheck( void *pvParameters );\r
+\r
+/*\r
+ * See comments at the top of the file for details. \r
+ */\r
+static void vFLOPCheck1( void *pvParameters );\r
+\r
+/*\r
+ * See comments at the top of the file for details. \r
+ */\r
+static void vFLOPCheck2( void *pvParameters );\r
+\r
+/* File scope variable used to communicate the occurrence of an error between\r
+tasks. */\r
+static portBASE_TYPE xLatchedError = pdFALSE;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Starts all the other tasks, then starts the scheduler. \r
+ */\r
+void main( void )\r
+{\r
+ /* Initialise the hardware including the system clock and on board\r
+ LED. */\r
+ prvSetupHardware();\r
+\r
+ /* Initialise the port that controls the external LED's utilized by the\r
+ flash tasks. */\r
+ vParTestInitialise();\r
+\r
+ /* Start the used standard demo tasks. */\r
+ vStartLEDFlashTasks( mainLED_TASK_PRIORITY );\r
+ vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
+ vStartIntegerMathTasks( mainINTEGER_PRIORITY );\r
+ vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED );\r
+ vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
+\r
+ /* Start the tasks defined in this file. The first three never block so\r
+ must not be used with the co-operative scheduler. */\r
+ #if configUSE_PREEMPTION == 1\r
+ {\r
+ xTaskCreate( vRegisterCheck, "RegChck", configMINIMAL_STACK_SIZE, mainDUMMY_POINTER, tskIDLE_PRIORITY, ( xTaskHandle * ) NULL );\r
+ xTaskCreate( vFLOPCheck1, "FLOP", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, ( xTaskHandle * ) NULL );\r
+ xTaskCreate( vFLOPCheck2, "FLOP", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, ( xTaskHandle * ) NULL );\r
+ }\r
+ #endif \r
+\r
+ xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, ( xTaskHandle * ) NULL );\r
+\r
+ /* Finally kick off the scheduler. This function should never return. */\r
+ vTaskStartScheduler();\r
+\r
+ /* Should never reach here as the tasks will now be executing under control\r
+ of the scheduler. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Setup the hardware prior to using the scheduler. Most of the Cygnal\r
+ * specific initialisation is performed here leaving standard 8052 setup\r
+ * only in the driver code.\r
+ */\r
+static void prvSetupHardware( void )\r
+{\r
+unsigned portCHAR ucOriginalSFRPage;\r
+\r
+ /* Remember the SFR page before it is changed so it can get set back\r
+ before the function exits. */\r
+ ucOriginalSFRPage = SFRPAGE;\r
+\r
+ /* Setup the SFR page to access the config SFR's. */\r
+ SFRPAGE = CONFIG_PAGE;\r
+\r
+ /* Don't allow the microcontroller to automatically switch SFR page, as the\r
+ SFR page is not stored as part of the task context. */\r
+ SFRPGCN = mainAUTO_SFR_OFF;\r
+\r
+ /* Disable the watchdog. */\r
+ WDTCN = mainDISABLE_BYTE_1;\r
+ WDTCN = mainDISABLE_BYTE_2;\r
+\r
+ /* Set the on board LED to push pull. */\r
+ P1MDOUT |= mainPORT_1_BIT_6;\r
+\r
+ /* Setup the cross bar to enable serial comms here as it is not part of the \r
+ standard 8051 setup and therefore is not in the driver code. */\r
+ XBR0 |= mainENABLE_COMS;\r
+ P0MDOUT |= mainCOMS_LINES_TO_PUSH_PULL;\r
+\r
+ /* Enable the cross bar so our hardware setup takes effect. */\r
+ XBR2 = mainENABLE_CROSS_BAR;\r
+\r
+ /* Setup a fast system clock. */\r
+ prvSetupSystemClock();\r
+\r
+ /* Return the SFR page. */\r
+ SFRPAGE = ucOriginalSFRPage;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupSystemClock( void )\r
+{\r
+volatile unsigned portSHORT usWait;\r
+const unsigned portSHORT usWaitTime = ( unsigned portSHORT ) 0x2ff;\r
+unsigned portCHAR ucOriginalSFRPage;\r
+\r
+ /* Remember the SFR page so we can set it back at the end. */\r
+ ucOriginalSFRPage = SFRPAGE;\r
+ SFRPAGE = CONFIG_PAGE;\r
+\r
+ /* Use the internal oscillator set to its fasted frequency. */\r
+ OSCICN = mainSELECT_INTERNAL_OSC | mainDIVIDE_CLOCK_BY_1;\r
+\r
+ /* Ensure the clock is stable. */\r
+ for( usWait = 0; usWait < usWaitTime; usWait++ );\r
+\r
+ /* Setup the clock source for the PLL. */\r
+ PLL0CN &= ~mainPLL_USES_INTERNAL_OSC;\r
+\r
+ /* Change the read timing for the flash ready for the fast clock. */\r
+ SFRPAGE = LEGACY_PAGE;\r
+ FLSCL |= mainFLASH_READ_TIMING;\r
+\r
+ /* Turn on the PLL power. */\r
+ SFRPAGE = CONFIG_PAGE;\r
+ PLL0CN |= mainPLL_POWER_ON;\r
+\r
+ /* Don't predivide the clock. */\r
+ PLL0DIV = mainPLL_NO_PREDIVIDE;\r
+\r
+ /* Set filter for fastest clock. */\r
+ PLL0FLT = mainPLL_FILTER;\r
+ PLL0MUL = mainPLL_MULTIPLICATION;\r
+\r
+ /* Ensure the clock is stable. */\r
+ for( usWait = 0; usWait < usWaitTime; usWait++ );\r
+\r
+ /* Enable the PLL and wait for it to lock. */\r
+ PLL0CN |= mainENABLE_PLL;\r
+ for( usWait = 0; usWait < usWaitTime; usWait++ )\r
+ {\r
+ if( PLL0CN & mainPLL_LOCKED )\r
+ {\r
+ break;\r
+ }\r
+ }\r
+\r
+ /* Select the PLL as the clock source. */\r
+ CLKSEL |= mainSELECT_PLL_AS_SOURCE;\r
+\r
+ /* Return the SFR back to its original value. */\r
+ SFRPAGE = ucOriginalSFRPage;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvToggleOnBoardLED( void )\r
+{\r
+ /* If the on board LED is on, turn it off and visa versa. */\r
+ if( P1 & ucLED_BIT )\r
+ {\r
+ P1 &= ~ucLED_BIT;\r
+ }\r
+ else\r
+ {\r
+ P1 |= ucLED_BIT;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * See the documentation at the top of this file. \r
+ */\r
+static void vErrorChecks( void *pvParameters )\r
+{\r
+portBASE_TYPE xErrorHasOccurred = pdFALSE;\r
+ \r
+ /* Just to prevent compiler warnings. */\r
+ ( void ) pvParameters;\r
+ \r
+ /* Cycle for ever, delaying then checking all the other tasks are still\r
+ operating without error. The delay period depends on whether an error\r
+ has ever been detected. */\r
+ for( ;; )\r
+ {\r
+ if( xLatchedError == pdFALSE )\r
+ { \r
+ /* No errors have been detected so delay for a longer period. The\r
+ on board LED will get toggled every mainNO_ERROR_FLASH_PERIOD ms. */\r
+ vTaskDelay( mainNO_ERROR_FLASH_PERIOD );\r
+ }\r
+ else\r
+ {\r
+ /* We have at some time recognised an error in one of the demo\r
+ application tasks, delay for a shorter period. The on board LED\r
+ will get toggled every mainERROR_FLASH_PERIOD ms. */\r
+ vTaskDelay( mainERROR_FLASH_PERIOD );\r
+ }\r
+\r
+ \r
+ \r
+ /* Check the demo application tasks for errors. */\r
+\r
+ if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ xErrorHasOccurred = pdTRUE;\r
+ }\r
+\r
+ if( xArePollingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ xErrorHasOccurred = pdTRUE;\r
+ }\r
+\r
+ if( xAreComTestTasksStillRunning() != pdTRUE )\r
+ {\r
+ xErrorHasOccurred = pdTRUE;\r
+ }\r
+\r
+ if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ xErrorHasOccurred = pdTRUE;\r
+ }\r
+\r
+ /* If an error has occurred, latch it to cause the LED flash rate to \r
+ increase. */\r
+ if( xErrorHasOccurred == pdTRUE )\r
+ {\r
+ xLatchedError = pdTRUE;\r
+ }\r
+\r
+ /* Toggle the LED to indicate the completion of a check cycle. The\r
+ frequency of check cycles is dependent on whether or not we have \r
+ latched an error. */\r
+ prvToggleOnBoardLED();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * See the documentation at the top of this file. Also see the standard FLOP\r
+ * demo task documentation for the rationale of these tasks.\r
+ */\r
+static void vFLOPCheck1( void *pvParameters )\r
+{\r
+volatile portFLOAT fVal1, fVal2, fResult;\r
+\r
+ ( void ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ fVal1 = ( portFLOAT ) -1234.5678;\r
+ fVal2 = ( portFLOAT ) 2345.6789;\r
+\r
+ fResult = fVal1 + fVal2;\r
+ if( ( fResult > ( portFLOAT ) 1111.15 ) || ( fResult < ( portFLOAT ) 1111.05 ) )\r
+ {\r
+ mainLATCH_ERROR();\r
+ }\r
+\r
+ fResult = fVal1 / fVal2;\r
+ if( ( fResult > ( portFLOAT ) -0.51 ) || ( fResult < ( portFLOAT ) -0.53 ) )\r
+ {\r
+ mainLATCH_ERROR();\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * See the documentation at the top of this file.\r
+ */\r
+static void vFLOPCheck2( void *pvParameters )\r
+{\r
+volatile portFLOAT fVal1, fVal2, fResult;\r
+\r
+ ( void ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ fVal1 = ( portFLOAT ) -12340.5678;\r
+ fVal2 = ( portFLOAT ) 23450.6789;\r
+\r
+ fResult = fVal1 + fVal2;\r
+ if( ( fResult > ( portFLOAT ) 11110.15 ) || ( fResult < ( portFLOAT ) 11110.05 ) )\r
+ {\r
+ mainLATCH_ERROR();\r
+ }\r
+\r
+ fResult = fVal1 / -fVal2;\r
+ if( ( fResult > ( portFLOAT ) 0.53 ) || ( fResult < ( portFLOAT ) 0.51 ) )\r
+ {\r
+ mainLATCH_ERROR();\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * See the documentation at the top of this file. \r
+ */\r
+static void vRegisterCheck( void *pvParameters )\r
+{\r
+ ( void ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ if( SP != configSTACK_START )\r
+ {\r
+ mainLATCH_ERROR();\r
+ }\r
+\r
+ _asm\r
+ MOV ACC, ar0\r
+ _endasm;\r
+\r
+ if( ACC != 0 )\r
+ {\r
+ mainLATCH_ERROR();\r
+ }\r
+\r
+ _asm\r
+ MOV ACC, ar1\r
+ _endasm;\r
+\r
+ if( ACC != 1 )\r
+ {\r
+ mainLATCH_ERROR();\r
+ }\r
+ _asm\r
+ MOV ACC, ar2\r
+ _endasm;\r
+\r
+ if( ACC != 2 )\r
+ {\r
+ mainLATCH_ERROR();\r
+ }\r
+ _asm\r
+ MOV ACC, ar3\r
+ _endasm;\r
+\r
+ if( ACC != 3 )\r
+ {\r
+ mainLATCH_ERROR();\r
+ }\r
+ _asm\r
+ MOV ACC, ar4\r
+ _endasm;\r
+\r
+ if( ACC != 4 )\r
+ {\r
+ mainLATCH_ERROR();\r
+ }\r
+ _asm\r
+ MOV ACC, ar5\r
+ _endasm;\r
+\r
+ if( ACC != 5 )\r
+ {\r
+ mainLATCH_ERROR();\r
+ }\r
+ _asm\r
+ MOV ACC, ar6\r
+ _endasm;\r
+\r
+ if( ACC != 6 )\r
+ {\r
+ mainLATCH_ERROR();\r
+ }\r
+ _asm\r
+ MOV ACC, ar7\r
+ _endasm;\r
+\r
+ if( ACC != 7 )\r
+ {\r
+ mainLATCH_ERROR();\r
+ }\r
+\r
+ if( DPL != 0xcd )\r
+ {\r
+ mainLATCH_ERROR();\r
+ }\r
+\r
+ if( DPH != 0xab )\r
+ {\r
+ mainLATCH_ERROR();\r
+ }\r
+\r
+ if( B != 0x01 )\r
+ {\r
+ mainLATCH_ERROR();\r
+ } \r
+ }\r
+}\r
+\r
+\r
--- /dev/null
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--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+\r
+/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR DEMO PURPOSES */\r
+#include <stdlib.h>\r
+#include "FreeRTOS.h"\r
+#include "queue.h"\r
+#include "task.h"\r
+#include "serial.h"\r
+\r
+/* Constants required to setup the serial control register. */\r
+#define ser8_BIT_MODE ( ( unsigned portCHAR ) 0x40 )\r
+#define serRX_ENABLE ( ( unsigned portCHAR ) 0x10 )\r
+\r
+/* Constants to setup the timer used to generate the baud rate. */\r
+#define serCLOCK_DIV_48 ( ( unsigned portCHAR ) 0x03 )\r
+#define serUSE_PRESCALED_CLOCK ( ( unsigned portCHAR ) 0x10 )\r
+#define ser8BIT_WITH_RELOAD ( ( unsigned portCHAR ) 0x20 )\r
+#define serSMOD ( ( unsigned portCHAR ) 0x10 )\r
+\r
+static xQueueHandle xRxedChars; \r
+static xQueueHandle xCharsForTx; \r
+\r
+data static unsigned portBASE_TYPE uxTxEmpty;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )\r
+{\r
+unsigned portLONG ulReloadValue;\r
+const portFLOAT fBaudConst = ( portFLOAT ) configCPU_CLOCK_HZ * ( portFLOAT ) 2.0;\r
+unsigned portCHAR ucOriginalSFRPage;\r
+\r
+ portENTER_CRITICAL();\r
+ {\r
+ ucOriginalSFRPage = SFRPAGE;\r
+ SFRPAGE = 0;\r
+\r
+ uxTxEmpty = pdTRUE;\r
+\r
+ /* Create the queues used by the com test task. */\r
+ xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( portCHAR ) );\r
+ xCharsForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( portCHAR ) );\r
+ \r
+ /* Calculate the baud rate to use timer 1. */\r
+ ulReloadValue = ( unsigned portLONG ) ( ( ( portFLOAT ) 256 - ( fBaudConst / ( portFLOAT ) ( 32 * ulWantedBaud ) ) ) + ( portFLOAT ) 0.5 );\r
+\r
+ /* Set timer one for desired mode of operation. */\r
+ TMOD &= 0x08;\r
+ TMOD |= ser8BIT_WITH_RELOAD;\r
+ SSTA0 |= serSMOD;\r
+\r
+ /* Set the reload and start values for the time. */\r
+ TL1 = ( unsigned portCHAR ) ulReloadValue;\r
+ TH1 = ( unsigned portCHAR ) ulReloadValue;\r
+\r
+ /* Setup the control register for standard n, 8, 1 - variable baud rate. */\r
+ SCON = ser8_BIT_MODE | serRX_ENABLE;\r
+\r
+ /* Enable the serial port interrupts */\r
+ ES = 1;\r
+\r
+ /* Start the timer. */\r
+ TR1 = 1;\r
+\r
+ SFRPAGE = ucOriginalSFRPage;\r
+ }\r
+ portEXIT_CRITICAL();\r
+ \r
+ /* Unlike some ports, this serial code does not allow for more than one\r
+ com port. We therefore don't return a pointer to a port structure and can\r
+ instead just return NULL. */\r
+ return NULL;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSerialISR( void ) interrupt 4\r
+{\r
+portCHAR cChar;\r
+portBASE_TYPE xTaskWokenByRx = pdFALSE, xTaskWokenByTx = pdFALSE;\r
+\r
+ /* 8051 port interrupt routines MUST be placed within a critical section\r
+ if taskYIELD() is used within the ISR! */\r
+\r
+ portENTER_CRITICAL();\r
+ {\r
+ if( RI ) \r
+ {\r
+ /* Get the character and post it on the queue of Rxed characters.\r
+ If the post causes a task to wake force a context switch as the woken task\r
+ may have a higher priority than the task we have interrupted. */\r
+ cChar = SBUF;\r
+ RI = 0;\r
+\r
+ if( xQueueSendFromISR( xRxedChars, &cChar, pdFALSE ) )\r
+ {\r
+ xTaskWokenByRx = ( portBASE_TYPE ) pdTRUE;\r
+ }\r
+ }\r
+\r
+ if( TI ) \r
+ {\r
+ if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWokenByTx ) == ( portBASE_TYPE ) pdTRUE )\r
+ {\r
+ /* Send the next character queued for Tx. */\r
+ SBUF = cChar;\r
+ }\r
+ else\r
+ {\r
+ /* Queue empty, nothing to send. */\r
+ uxTxEmpty = pdTRUE;\r
+ }\r
+\r
+ TI = 0;\r
+ }\r
+ \r
+ if( xTaskWokenByRx || xTaskWokenByTx )\r
+ {\r
+ portYIELD();\r
+ }\r
+ }\r
+ portEXIT_CRITICAL();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )\r
+{\r
+ /* There is only one port supported. */\r
+ ( void ) pxPort;\r
+\r
+ /* Get the next character from the buffer. Return false if no characters\r
+ are available, or arrive before xBlockTime expires. */\r
+ if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )\r
+ {\r
+ return ( portBASE_TYPE ) pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ return ( portBASE_TYPE ) pdFALSE;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )\r
+{\r
+portBASE_TYPE xReturn;\r
+\r
+ /* There is only one port supported. */\r
+ ( void ) pxPort;\r
+\r
+ portENTER_CRITICAL();\r
+ {\r
+ if( uxTxEmpty == pdTRUE )\r
+ {\r
+ SBUF = cOutChar;\r
+ uxTxEmpty = pdFALSE;\r
+ xReturn = ( portBASE_TYPE ) pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ xReturn = xQueueSend( xCharsForTx, &cOutChar, xBlockTime );\r
+\r
+ if( xReturn == ( portBASE_TYPE ) pdFALSE )\r
+ {\r
+ xReturn = ( portBASE_TYPE ) pdTRUE;\r
+ }\r
+ }\r
+ }\r
+ portEXIT_CRITICAL();\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSerialClose( xComPortHandle xPort )\r
+{\r
+ /* Not implemented in this port. */\r
+ ( void ) xPort;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+#include <conio.h>\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions for the x86 port.\r
+ *----------------------------------------------------------*/\r
+\r
+/* These are the only definitions that can be modified!. */\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 10 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 128 ) /* This can be made smaller if required. */\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 32 * 1024 ) ) \r
+#define configMAX_TASK_NAME_LEN ( 16 )\r
+#define configUSE_TRACE_FACILITY 0\r
+#define configUSE_16_BIT_TICKS 1\r
+#define configIDLE_SHOULD_YIELD 1\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* The maximum number of characters a task name can take, \r
+including the null terminator. */\r
+#define configMAX_TASK_NAME_LEN ( 16 )\r
+\r
+/* Set the following definitions to 1 to include the component, or zero\r
+to exclude the component. */\r
+\r
+/* Include/exclude the stated API function. */\r
+#define INCLUDE_vTaskPrioritySet 0\r
+#define INCLUDE_uxTaskPriorityGet 0\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 1\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+\r
+\r
+/* Use/don't use the trace visualisation. */\r
+#define configUSE_TRACE_FACILITY 0\r
+\r
+/* \r
+ * The tick count (and times defined in tick count units) can be either a 16bit\r
+ * or a 32 bit value. See documentation on http://www.FreeRTOS.org to decide\r
+ * which to use.\r
+ */\r
+#define configUSE_16_BIT_TICKS 1\r
+\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#include <stdio.h>\r
+#include <conio.h>\r
+#include <string.h>\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo program include files. */\r
+#include "fileio.h"\r
+\r
+void vDisplayMessage( const portCHAR * const pcMessageToPrint )\r
+{\r
+ #ifdef USE_STDIO\r
+ taskENTER_CRITICAL();\r
+ printf( "%s", pcMessageToPrint );\r
+ fflush( stdout );\r
+ taskEXIT_CRITICAL();\r
+ #else\r
+ /* Stop warnings. */\r
+ ( void ) pcMessageToPrint;\r
+ #endif\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vWriteMessageToDisk( const portCHAR * const pcMessage )\r
+{\r
+#ifdef USE_STDIO\r
+const portCHAR * const pcFileName = "c:\\RTOSlog.txt";\r
+const portCHAR * const pcSeparator = "\r\n-----------------------\r\n";\r
+FILE *pf;\r
+\r
+ taskENTER_CRITICAL();\r
+ { \r
+ pf = fopen( pcFileName, "a" );\r
+ if( pf != NULL )\r
+ {\r
+ fwrite( pcMessage, strlen( pcMessage ), ( unsigned portSHORT ) 1, pf );\r
+ fwrite( pcSeparator, strlen( pcSeparator ), ( unsigned portSHORT ) 1, pf );\r
+ fclose( pf );\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+#else\r
+ /* Stop warnings. */\r
+ ( void ) pcMessage;\r
+#endif /*USE_STDIO*/\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vWriteBufferToDisk( const portCHAR * const pcBuffer, unsigned portLONG ulBufferLength )\r
+{\r
+#ifdef USE_STDIO\r
+const portCHAR * const pcFileName = "c:\\trace.bin";\r
+FILE *pf;\r
+\r
+ taskENTER_CRITICAL();\r
+ {\r
+ pf = fopen( pcFileName, "wb" );\r
+ if( pf )\r
+ {\r
+ fwrite( pcBuffer, ( size_t ) ulBufferLength, ( unsigned portSHORT ) 1, pf );\r
+ fclose( pf );\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+#else\r
+ /* Stop warnings. */\r
+ ( void ) pcBuffer;\r
+ ( void ) ulBufferLength;\r
+#endif /*USE_STDIO*/\r
+}\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+#include <i86.h>\r
+#include <conio.h>\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. \r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 10 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 128 ) /* This can be made smaller if required. */\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 32 * 1024 ) ) \r
+#define configMAX_TASK_NAME_LEN ( 16 )\r
+#define configUSE_TRACE_FACILITY 0\r
+#define configUSE_16_BIT_TICKS 1\r
+#define configIDLE_SHOULD_YIELD 1\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet 0\r
+#define INCLUDE_uxTaskPriorityGet 0\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 1\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+\r
+\r
+\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+Changes from V1.01:\r
+\r
+ + Types used updated.\r
+ + Add vParTestToggleLED();\r
+\r
+Changes from V2.0.0\r
+\r
+ + Use scheduler suspends in place of critical sections.\r
+*/\r
+\r
+\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "partest.h"\r
+\r
+#define partstALL_OUTPUTS_OFF ( ( unsigned portSHORT) 0x00 )\r
+#define partstMAX_OUTPUT_LED ( ( unsigned portCHAR ) 7 )\r
+#define partstPORT_F_ADDR ( ( unsigned portSHORT ) 0x605 )\r
+#define partstPORT_DIRECTION_REG ( ( unsigned portSHORT ) 0x606 )\r
+#define partstPORT_F_DIR_BIT ( ( unsigned portSHORT ) 0x20 )\r
+\r
+/*lint -e956 File scope parameters okay here. */\r
+static volatile unsigned portCHAR ucCurrentOutputValue = partstALL_OUTPUTS_OFF;\r
+/*lint +e956 */\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple parallel port IO routines.\r
+ *-----------------------------------------------------------*/\r
+\r
+void vParTestInitialise( void )\r
+{\r
+unsigned portSHORT usInput;\r
+\r
+ ucCurrentOutputValue = partstALL_OUTPUTS_OFF;\r
+\r
+ /* Set the direction to output for port F. */\r
+ usInput = portINPUT_BYTE( partstPORT_DIRECTION_REG );\r
+ usInput |= partstPORT_F_DIR_BIT;\r
+ portOUTPUT_BYTE( partstPORT_DIRECTION_REG, usInput );\r
+\r
+ /* Start with all outputs off. */\r
+ portOUTPUT_BYTE( partstPORT_F_ADDR, partstALL_OUTPUTS_OFF );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, portBASE_TYPE xValue )\r
+{\r
+unsigned portCHAR ucBit = ( unsigned portCHAR ) 1;\r
+\r
+ if( uxLED <= partstMAX_OUTPUT_LED )\r
+ {\r
+ ucBit <<= uxLED;\r
+ } \r
+\r
+ vTaskSuspendAll();\r
+ {\r
+ if( xValue == pdTRUE )\r
+ {\r
+ ucBit ^= ( unsigned portCHAR ) 0xff;\r
+ ucCurrentOutputValue &= ucBit;\r
+ }\r
+ else\r
+ {\r
+ ucCurrentOutputValue |= ucBit;\r
+ }\r
+\r
+ portOUTPUT_BYTE( partstPORT_F_ADDR, ( unsigned ) ucCurrentOutputValue );\r
+ }\r
+ xTaskResumeAll();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+unsigned portCHAR ucBit;\r
+\r
+ if( uxLED <= partstMAX_OUTPUT_LED )\r
+ {\r
+ ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED;\r
+\r
+ vTaskSuspendAll();\r
+ {\r
+ if( ucCurrentOutputValue & ucBit )\r
+ {\r
+ ucCurrentOutputValue &= ~ucBit;\r
+ }\r
+ else\r
+ {\r
+ ucCurrentOutputValue |= ucBit;\r
+ }\r
+\r
+ portOUTPUT_BYTE( partstPORT_F_ADDR, ( unsigned ) ucCurrentOutputValue );\r
+ }\r
+ xTaskResumeAll(); \r
+ }\r
+}\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+ * Creates all the demo application tasks, then starts the scheduler.\r
+ *\r
+ * Main. c also creates a task called "Print". This only executes every five \r
+ * seconds but has the highest priority so is guaranteed to get processor time. \r
+ * Its main function is to check that all the other tasks are still operational. \r
+ * Nearly all the tasks in the demo application maintain a unique count that is \r
+ * incremented each time the task successfully completes its function. Should any \r
+ * error occur within the task the count is permanently halted. The print task \r
+ * checks the count of each task to ensure it has changed since the last time the \r
+ * print task executed. If any count is found not to have changed the print task\r
+ * displays an appropriate message, halts, and flashes the on board LED rapidly.\r
+ * If all the tasks are still incrementing their unique counts the print task\r
+ * displays an "OK" message.\r
+ *\r
+ * The LED flash tasks do not maintain a count as they already provide visual\r
+ * feedback of their status.\r
+ *\r
+ * The print task blocks on the queue into which messages that require displaying\r
+ * are posted. It will therefore only block for the full 5 seconds if no messages\r
+ * are posted onto the queue.\r
+ *\r
+ * Main. c also provides a demonstration of how the trace visualisation utility can\r
+ * be used, and how the scheduler can be stopped.\r
+ *\r
+ * On the Flashlite it is preferable not to try to write to the console during\r
+ * real time operation. The built in LED is toggled every cycle of the print task\r
+ * that does not encounter any errors, so the console IO may be removed if required.\r
+ * The build in LED will start flashing rapidly if any task reports an error.\r
+ */\r
+\r
+/*\r
+Changes from V1.01:\r
+\r
+ + Previously, if an error occurred in a task the on board LED was stopped from\r
+ toggling. Now if an error occurs the check task enters an infinite loop,\r
+ toggling the LED rapidly.\r
+\r
+Changes from V1.2.3\r
+\r
+ + The integer and comtest tasks are now used when the cooperative scheduler \r
+ is being used. Previously they were only used with the preemptive\r
+ scheduler.\r
+\r
+Changes from V1.2.5\r
+\r
+ + Made the communications RX task a higher priority.\r
+\r
+Changes from V2.0.0\r
+\r
+ + Delay periods are now specified using variables and constants of\r
+ portTickType rather than unsigned portLONG.\r
+*/\r
+\r
+#include <stdlib.h>\r
+#include <conio.h>\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "partest.h"\r
+#include "serial.h"\r
+\r
+/* Demo file headers. */\r
+#include "BlockQ.h"\r
+#include "PollQ.h"\r
+#include "death.h"\r
+#include "flash.h"\r
+#include "integer.h"\r
+#include "print.h"\r
+#include "comtest.h"\r
+#include "fileio.h"\r
+#include "semtest.h"\r
+\r
+/* Priority definitions for all the tasks in the demo application. */\r
+#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+#define mainPRINT_TASK_PRIORITY ( tskIDLE_PRIORITY + 5 )\r
+#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainQUEUE_BLOCK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+#define mainSEMAPHORE_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+\r
+#define mainPRINT_STACK_SIZE ( ( unsigned portSHORT ) 256 )\r
+#define mainDEBUG_LOG_BUFFER_SIZE ( ( unsigned portSHORT ) 20480 )\r
+\r
+/* Constant definitions for accessing the build in LED on the Flashlite 186. */\r
+#define mainLED_REG_DIR ( ( unsigned portSHORT ) 0xff78 )\r
+#define mainLED_REG ( ( unsigned portSHORT ) 0xff7a )\r
+\r
+/* If an error is detected in a task then the vErrorChecks() task will enter\r
+an infinite loop flashing the LED at this rate. */\r
+#define mainERROR_FLASH_RATE ( ( portTickType ) 100 / portTICK_RATE_MS )\r
+\r
+/* Task function for the "Print" task as described at the top of the file. */\r
+static void vErrorChecks( void *pvParameters );\r
+\r
+/* Function that checks the unique count of all the other tasks as described at\r
+the top of the file. */\r
+static void prvCheckOtherTasksAreStillRunning( void );\r
+\r
+/* Functions to setup and use the built in LED on the Flashlite 186 board. */\r
+static void prvToggleLED( void );\r
+static void prvInitLED( void );\r
+\r
+/* Key presses can be used to start/stop the trace visualisation utility or stop\r
+the scheduler. */\r
+static void prvCheckForKeyPresses( void );\r
+\r
+/* Buffer used by the trace visualisation utility. */\r
+static portCHAR pcWriteBuffer[ mainDEBUG_LOG_BUFFER_SIZE ];\r
+\r
+/*-----------------------------------------------------------*/\r
+portSHORT main( void )\r
+{\r
+ /* Initialise hardware and utilities. */\r
+ vParTestInitialise();\r
+ vPrintInitialise();\r
+ prvInitLED();\r
+\r
+ /* CREATE ALL THE DEMO APPLICATION TASKS. */\r
+\r
+ vStartComTestTasks( mainCOM_TEST_PRIORITY, serCOM2, ser38400 );\r
+ vStartIntegerMathTasks( tskIDLE_PRIORITY );\r
+ vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
+ vStartBlockingQueueTasks( mainQUEUE_BLOCK_PRIORITY );\r
+ vStartLEDFlashTasks( mainLED_TASK_PRIORITY );\r
+ vStartSemaphoreTasks( mainSEMAPHORE_TASK_PRIORITY );\r
+\r
+ /* Create the "Print" task as described at the top of the file. */\r
+ xTaskCreate( vErrorChecks, "Print", mainPRINT_STACK_SIZE, NULL, mainPRINT_TASK_PRIORITY, NULL );\r
+\r
+ /* This task has to be created last as it keeps account of the number of tasks\r
+ it expects to see running. */\r
+ vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );\r
+\r
+ /* Set the scheduler running. This function will not return unless a task\r
+ calls vTaskEndScheduler(). */\r
+ vTaskStartScheduler();\r
+\r
+ return 1;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vErrorChecks( void *pvParameters )\r
+{\r
+portTickType xExpectedWakeTime;\r
+const portTickType xPrintRate = ( portTickType ) 5000 / portTICK_RATE_MS;\r
+const portLONG lMaxAllowableTimeDifference = ( portLONG ) 0;\r
+portTickType xWakeTime;\r
+portLONG lTimeDifference;\r
+const portCHAR *pcReceivedMessage;\r
+const portCHAR * const pcTaskBlockedTooLongMsg = "Print task blocked too long!\r\n";\r
+\r
+ /* Stop warnings. */\r
+ ( void ) pvParameters;\r
+\r
+ /* Loop continuously, blocking, then checking all the other tasks are still\r
+ running, before blocking once again. This task blocks on the queue of messages\r
+ that require displaying so will wake either by its time out expiring, or a\r
+ message becoming available. */\r
+ for( ;; )\r
+ {\r
+ /* Calculate the time we will unblock if no messages are received\r
+ on the queue. This is used to check that we have not blocked for too long. */\r
+ xExpectedWakeTime = xTaskGetTickCount();\r
+ xExpectedWakeTime += xPrintRate;\r
+\r
+ /* Block waiting for either a time out or a message to be posted that\r
+ required displaying. */\r
+ pcReceivedMessage = pcPrintGetNextMessage( xPrintRate );\r
+\r
+ /* Was a message received? */\r
+ if( pcReceivedMessage == NULL )\r
+ {\r
+ /* A message was not received so we timed out, did we unblock at the\r
+ expected time? */\r
+ xWakeTime = xTaskGetTickCount();\r
+\r
+ /* Calculate the difference between the time we unblocked and the\r
+ time we should have unblocked. */\r
+ if( xWakeTime > xExpectedWakeTime )\r
+ {\r
+ lTimeDifference = ( portLONG ) ( xWakeTime - xExpectedWakeTime );\r
+ }\r
+ else\r
+ {\r
+ lTimeDifference = ( portLONG ) ( xExpectedWakeTime - xWakeTime );\r
+ }\r
+\r
+ if( lTimeDifference > lMaxAllowableTimeDifference )\r
+ {\r
+ /* We blocked too long - create a message that will get\r
+ printed out the next time around. */\r
+ vPrintDisplayMessage( &pcTaskBlockedTooLongMsg );\r
+ }\r
+\r
+ /* Check the other tasks are still running, just in case. */\r
+ prvCheckOtherTasksAreStillRunning();\r
+ }\r
+ else\r
+ {\r
+ /* We unblocked due to a message becoming available. Send the message\r
+ for printing. */\r
+ vDisplayMessage( pcReceivedMessage );\r
+ }\r
+\r
+ /* Key presses are used to invoke the trace visualisation utility, or\r
+ end the program. */\r
+ prvCheckForKeyPresses();\r
+ }\r
+} /*lint !e715 !e818 pvParameters is not used but all task functions must take this form. */\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCheckForKeyPresses( void )\r
+{\r
+ #ifdef USE_STDIO\r
+\r
+ portSHORT sIn;\r
+\r
+ \r
+ taskENTER_CRITICAL();\r
+ sIn = kbhit();\r
+ taskEXIT_CRITICAL();\r
+\r
+ if( sIn )\r
+ {\r
+ unsigned portLONG ulBufferLength;\r
+\r
+ /* Key presses can be used to start/stop the trace utility, or end the\r
+ program. */\r
+ sIn = getch();\r
+ switch( sIn )\r
+ {\r
+ /* Only define keys for turning on and off the trace if the trace\r
+ is being used. */\r
+ #if configUSE_TRACE_FACILITY == 1\r
+ case 't' : vTaskList( pcWriteBuffer );\r
+ vWriteMessageToDisk( pcWriteBuffer );\r
+ break;\r
+\r
+ case 's' : vTaskStartTrace( pcWriteBuffer, mainDEBUG_LOG_BUFFER_SIZE );\r
+ break;\r
+\r
+ case 'e' : ulBufferLength = ulTaskEndTrace();\r
+ vWriteBufferToDisk( pcWriteBuffer, ulBufferLength );\r
+ break;\r
+ #endif\r
+\r
+ default : vTaskEndScheduler();\r
+ break;\r
+ }\r
+ }\r
+\r
+ #else\r
+ ( void ) pcWriteBuffer;\r
+ #endif\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCheckOtherTasksAreStillRunning( void )\r
+{\r
+portSHORT sErrorHasOccurred = pdFALSE;\r
+\r
+ if( xAreComTestTasksStillRunning() != pdTRUE )\r
+ {\r
+ vDisplayMessage( "Com test count unchanged!\r\n" );\r
+ sErrorHasOccurred = pdTRUE;\r
+ }\r
+\r
+ if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ vDisplayMessage( "Integer maths task count unchanged!\r\n" );\r
+ sErrorHasOccurred = pdTRUE;\r
+ }\r
+\r
+ if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ vDisplayMessage( "Blocking queues count unchanged!\r\n" );\r
+ sErrorHasOccurred = pdTRUE;\r
+ }\r
+\r
+ if( xArePollingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ vDisplayMessage( "Polling queue count unchanged!\r\n" );\r
+ sErrorHasOccurred = pdTRUE;\r
+ }\r
+\r
+ if( xIsCreateTaskStillRunning() != pdTRUE )\r
+ {\r
+ vDisplayMessage( "Incorrect number of tasks running!\r\n" );\r
+ sErrorHasOccurred = pdTRUE;\r
+ }\r
+\r
+ if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ vDisplayMessage( "Semaphore take count unchanged!\r\n" );\r
+ sErrorHasOccurred = pdTRUE;\r
+ }\r
+\r
+ if( sErrorHasOccurred == pdFALSE )\r
+ {\r
+ vDisplayMessage( "OK " );\r
+ /* Toggle the LED if everything is okay so we know if an error occurs even if not\r
+ using console IO. */\r
+ prvToggleLED();\r
+ }\r
+ else\r
+ {\r
+ for( ;; )\r
+ {\r
+ /* An error has occurred in one of the tasks. Don't go any further and\r
+ flash the LED rapidly in case console IO is not being used. */\r
+ prvToggleLED();\r
+ vTaskDelay( mainERROR_FLASH_RATE );\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvInitLED( void )\r
+{\r
+unsigned portSHORT usPortDirection;\r
+const unsigned portSHORT usLEDOut = 0x400;\r
+\r
+ /* Set the LED bit to an output. */\r
+\r
+ usPortDirection = inpw( mainLED_REG_DIR );\r
+ usPortDirection &= ~usLEDOut;\r
+ outpw( mainLED_REG_DIR, usPortDirection );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvToggleLED( void )\r
+{\r
+static portSHORT sLED = pdTRUE;\r
+unsigned portSHORT usLEDState;\r
+const unsigned portSHORT usLEDBit = 0x400;\r
+\r
+ /* Flip the state of the LED. */\r
+ usLEDState = inpw( mainLED_REG );\r
+ if( sLED )\r
+ {\r
+ usLEDState &= ~usLEDBit;\r
+ }\r
+ else\r
+ {\r
+ usLEDState |= usLEDBit;\r
+ }\r
+ outpw( mainLED_REG, usLEDState );\r
+\r
+ sLED = !sLED;\r
+}\r
+\r
+\r
--- /dev/null
+FIL list.obj,heap_2.obj,portcomn.obj,port.obj,queue.obj,tasks.obj,blockq.obj,comtest.obj,death.obj,flash.obj,integer.obj,pollq.obj,print.obj,semtest.obj,fileio.obj,main.obj,partest.obj,serial.obj\r
+\r
--- /dev/null
+project : E:\Dev\FreeRTOS\Demo\Flshlite\rtosdemo.exe .SYMBOLIC\r
+\r
+!include E:\Dev\FreeRTOS\Demo\Flshlite\rtosdemo.mk1\r
--- /dev/null
+!define BLANK ""\r
+E:\Dev\FreeRTOS\Demo\Flshlite\list.obj : E:\Dev\FreeRTOS\source\list.c .AUTO&\r
+DEPEND\r
+ @E:\r
+ cd E:\Dev\FreeRTOS\Demo\Flshlite\r
+ *wcc ..\..\source\list.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;..\..\&\r
+source\include;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -za -s&\r
+ -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=dos -m&\r
+l\r
+\r
+E:\Dev\FreeRTOS\Demo\Flshlite\heap_2.obj : E:\Dev\FreeRTOS\SOURCE\PORTABLE\M&\r
+EMMANG\heap_2.c .AUTODEPEND\r
+ @E:\r
+ cd E:\Dev\FreeRTOS\Demo\Flshlite\r
+ *wcc ..\..\SOURCE\PORTABLE\MEMMANG\heap_2.c -i=D:\DEVTOOLS\OPENWA~1\h;..\co&\r
+mmon\include;..\..\source\include;..\..\source\portable\owatcom\16bitdos\com&\r
+mon -w4 -e25 -za -s -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fp&\r
+c -zu -1 -bt=dos -ml\r
+\r
+E:\Dev\FreeRTOS\Demo\Flshlite\portcomn.obj : E:\Dev\FreeRTOS\source\portable&\r
+\owatcom\16bitdos\common\portcomn.c .AUTODEPEND\r
+ @E:\r
+ cd E:\Dev\FreeRTOS\Demo\Flshlite\r
+ *wcc ..\..\source\portable\owatcom\16bitdos\common\portcomn.c -i=D:\DEVTOOL&\r
+S\OPENWA~1\h;..\common\include;..\..\source\include;..\..\source\portable\ow&\r
+atcom\16bitdos\common -w4 -e25 -za -s -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -&\r
+zq -otexan -of -fpc -zu -1 -bt=dos -ml\r
+\r
+E:\Dev\FreeRTOS\Demo\Flshlite\port.obj : E:\Dev\FreeRTOS\source\portable\owa&\r
+tcom\16bitdos\flsh186\port.c .AUTODEPEND\r
+ @E:\r
+ cd E:\Dev\FreeRTOS\Demo\Flshlite\r
+ *wcc ..\..\source\portable\owatcom\16bitdos\flsh186\port.c -i=D:\DEVTOOLS\O&\r
+PENWA~1\h;..\common\include;..\..\source\include;..\..\source\portable\owatc&\r
+om\16bitdos\common -w4 -e25 -za -s -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -zq &\r
+-otexan -of -fpc -zu -1 -bt=dos -ml\r
+\r
+E:\Dev\FreeRTOS\Demo\Flshlite\queue.obj : E:\Dev\FreeRTOS\source\queue.c .AU&\r
+TODEPEND\r
+ @E:\r
+ cd E:\Dev\FreeRTOS\Demo\Flshlite\r
+ *wcc ..\..\source\queue.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;..\..&\r
+\source\include;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -za -&\r
+s -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=dos -&\r
+ml\r
+\r
+E:\Dev\FreeRTOS\Demo\Flshlite\tasks.obj : E:\Dev\FreeRTOS\source\tasks.c .AU&\r
+TODEPEND\r
+ @E:\r
+ cd E:\Dev\FreeRTOS\Demo\Flshlite\r
+ *wcc ..\..\source\tasks.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;..\..&\r
+\source\include;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -za -&\r
+s -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=dos -&\r
+ml\r
+\r
+E:\Dev\FreeRTOS\Demo\Flshlite\blockq.obj : E:\Dev\FreeRTOS\Demo\common\full\&\r
+blockq.c .AUTODEPEND\r
+ @E:\r
+ cd E:\Dev\FreeRTOS\Demo\Flshlite\r
+ *wcc ..\common\full\blockq.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;..&\r
+\..\source\include;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -z&\r
+a -s -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=do&\r
+s -ml\r
+\r
+E:\Dev\FreeRTOS\Demo\Flshlite\comtest.obj : E:\Dev\FreeRTOS\Demo\common\full&\r
+\comtest.c .AUTODEPEND\r
+ @E:\r
+ cd E:\Dev\FreeRTOS\Demo\Flshlite\r
+ *wcc ..\common\full\comtest.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;.&\r
+.\..\source\include;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -&\r
+za -s -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=d&\r
+os -ml\r
+\r
+E:\Dev\FreeRTOS\Demo\Flshlite\death.obj : E:\Dev\FreeRTOS\Demo\common\full\d&\r
+eath.c .AUTODEPEND\r
+ @E:\r
+ cd E:\Dev\FreeRTOS\Demo\Flshlite\r
+ *wcc ..\common\full\death.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;..\&\r
+..\source\include;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -za&\r
+ -s -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=dos&\r
+ -ml\r
+\r
+E:\Dev\FreeRTOS\Demo\Flshlite\flash.obj : E:\Dev\FreeRTOS\Demo\common\full\f&\r
+lash.c .AUTODEPEND\r
+ @E:\r
+ cd E:\Dev\FreeRTOS\Demo\Flshlite\r
+ *wcc ..\common\full\flash.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;..\&\r
+..\source\include;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -za&\r
+ -s -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=dos&\r
+ -ml\r
+\r
+E:\Dev\FreeRTOS\Demo\Flshlite\integer.obj : E:\Dev\FreeRTOS\Demo\common\full&\r
+\integer.c .AUTODEPEND\r
+ @E:\r
+ cd E:\Dev\FreeRTOS\Demo\Flshlite\r
+ *wcc ..\common\full\integer.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;.&\r
+.\..\source\include;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -&\r
+za -s -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=d&\r
+os -ml\r
+\r
+E:\Dev\FreeRTOS\Demo\Flshlite\pollq.obj : E:\Dev\FreeRTOS\Demo\common\full\p&\r
+ollq.c .AUTODEPEND\r
+ @E:\r
+ cd E:\Dev\FreeRTOS\Demo\Flshlite\r
+ *wcc ..\common\full\pollq.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;..\&\r
+..\source\include;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -za&\r
+ -s -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=dos&\r
+ -ml\r
+\r
+E:\Dev\FreeRTOS\Demo\Flshlite\print.obj : E:\Dev\FreeRTOS\Demo\common\full\p&\r
+rint.c .AUTODEPEND\r
+ @E:\r
+ cd E:\Dev\FreeRTOS\Demo\Flshlite\r
+ *wcc ..\common\full\print.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;..\&\r
+..\source\include;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -za&\r
+ -s -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=dos&\r
+ -ml\r
+\r
+E:\Dev\FreeRTOS\Demo\Flshlite\semtest.obj : E:\Dev\FreeRTOS\Demo\common\full&\r
+\semtest.c .AUTODEPEND\r
+ @E:\r
+ cd E:\Dev\FreeRTOS\Demo\Flshlite\r
+ *wcc ..\common\full\semtest.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;.&\r
+.\..\source\include;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -&\r
+za -s -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=d&\r
+os -ml\r
+\r
+E:\Dev\FreeRTOS\Demo\Flshlite\fileio.obj : E:\Dev\FreeRTOS\Demo\Flshlite\fil&\r
+eio\fileio.c .AUTODEPEND\r
+ @E:\r
+ cd E:\Dev\FreeRTOS\Demo\Flshlite\r
+ *wcc fileio\fileio.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;..\..\sour&\r
+ce\include;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -za -s -dO&\r
+PEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=dos -ml\r
+\r
+E:\Dev\FreeRTOS\Demo\Flshlite\main.obj : E:\Dev\FreeRTOS\Demo\Flshlite\main.&\r
+c .AUTODEPEND\r
+ @E:\r
+ cd E:\Dev\FreeRTOS\Demo\Flshlite\r
+ *wcc main.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;..\..\source\includ&\r
+e;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -za -s -dOPEN_WATCO&\r
+M_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=dos -ml\r
+\r
+E:\Dev\FreeRTOS\Demo\Flshlite\partest.obj : E:\Dev\FreeRTOS\Demo\Flshlite\pa&\r
+rtest\partest.c .AUTODEPEND\r
+ @E:\r
+ cd E:\Dev\FreeRTOS\Demo\Flshlite\r
+ *wcc partest\partest.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;..\..\so&\r
+urce\include;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -za -s -&\r
+dOPEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=dos -ml\r
+\r
+E:\Dev\FreeRTOS\Demo\Flshlite\serial.obj : E:\Dev\FreeRTOS\Demo\Flshlite\ser&\r
+ial\serial.c .AUTODEPEND\r
+ @E:\r
+ cd E:\Dev\FreeRTOS\Demo\Flshlite\r
+ *wcc serial\serial.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;..\..\sour&\r
+ce\include;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -za -s -dO&\r
+PEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=dos -ml\r
+\r
+E:\Dev\FreeRTOS\Demo\Flshlite\rtosdemo.exe : E:\Dev\FreeRTOS\Demo\Flshlite\l&\r
+ist.obj E:\Dev\FreeRTOS\Demo\Flshlite\heap_2.obj E:\Dev\FreeRTOS\Demo\Flshli&\r
+te\portcomn.obj E:\Dev\FreeRTOS\Demo\Flshlite\port.obj E:\Dev\FreeRTOS\Demo\&\r
+Flshlite\queue.obj E:\Dev\FreeRTOS\Demo\Flshlite\tasks.obj E:\Dev\FreeRTOS\D&\r
+emo\Flshlite\blockq.obj E:\Dev\FreeRTOS\Demo\Flshlite\comtest.obj E:\Dev\Fre&\r
+eRTOS\Demo\Flshlite\death.obj E:\Dev\FreeRTOS\Demo\Flshlite\flash.obj E:\Dev&\r
+\FreeRTOS\Demo\Flshlite\integer.obj E:\Dev\FreeRTOS\Demo\Flshlite\pollq.obj &\r
+E:\Dev\FreeRTOS\Demo\Flshlite\print.obj E:\Dev\FreeRTOS\Demo\Flshlite\semtes&\r
+t.obj E:\Dev\FreeRTOS\Demo\Flshlite\fileio.obj E:\Dev\FreeRTOS\Demo\Flshlite&\r
+\main.obj E:\Dev\FreeRTOS\Demo\Flshlite\partest.obj E:\Dev\FreeRTOS\Demo\Fls&\r
+hlite\serial.obj E:\Dev\FreeRTOS\source\include\list.h E:\Dev\FreeRTOS\sourc&\r
+e\include\portable.h E:\Dev\FreeRTOS\source\include\projdefs.h E:\Dev\FreeRT&\r
+OS\source\include\queue.h E:\Dev\FreeRTOS\source\include\semphr.h E:\Dev\Fre&\r
+eRTOS\source\include\task.h E:\Dev\FreeRTOS\source\portable\owatcom\16bitdos&\r
+\common\portasm.h E:\Dev\FreeRTOS\source\portable\owatcom\16bitdos\flsh186\p&\r
+ortmacro.h E:\Dev\FreeRTOS\Demo\common\include\blockq.h E:\Dev\FreeRTOS\Demo&\r
+\common\include\comtest.h E:\Dev\FreeRTOS\Demo\common\include\death.h E:\Dev&\r
+\FreeRTOS\Demo\common\include\fileio.h E:\Dev\FreeRTOS\Demo\common\include\f&\r
+lash.h E:\Dev\FreeRTOS\Demo\common\include\flop.h E:\Dev\FreeRTOS\Demo\commo&\r
+n\include\partest.h E:\Dev\FreeRTOS\Demo\common\include\pollq.h E:\Dev\FreeR&\r
+TOS\Demo\common\include\print.h E:\Dev\FreeRTOS\Demo\common\include\semtest.&\r
+h E:\Dev\FreeRTOS\Demo\common\include\serial.h E:\Dev\FreeRTOS\Demo\Flshlite&\r
+\FreeRTOSConfig.h .AUTODEPEND\r
+ @E:\r
+ cd E:\Dev\FreeRTOS\Demo\Flshlite\r
+ @%write rtosdemo.lk1 FIL list.obj,heap_2.obj,portcomn.obj,port.obj,queue.ob&\r
+j,tasks.obj,blockq.obj,comtest.obj,death.obj,flash.obj,integer.obj,pollq.obj&\r
+,print.obj,semtest.obj,fileio.obj,main.obj,partest.obj,serial.obj\r
+ @%append rtosdemo.lk1 \r
+ *wlink name rtosdemo SYS dos op m op maxe=25 op d op q op symf op el @rtosd&\r
+emo.lk1\r
+\r
--- /dev/null
+40\r
+targetIdent\r
+0\r
+MProject\r
+1\r
+MComponent\r
+0\r
+2\r
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+3\r
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+1\r
+0\r
+0\r
+4\r
+MCommand\r
+0\r
+5\r
+MCommand\r
+0\r
+6\r
+MItem\r
+12\r
+rtosdemo.exe\r
+7\r
+WString\r
+3\r
+EXE\r
+8\r
+WVList\r
+4\r
+9\r
+MRState\r
+10\r
+WString\r
+5\r
+WLINK\r
+11\r
+WString\r
+14\r
+?????Debug All\r
+1\r
+0\r
+12\r
+MRState\r
+13\r
+WString\r
+5\r
+WLINK\r
+14\r
+WString\r
+16\r
+?????Debug Dwarf\r
+1\r
+1\r
+15\r
+MCState\r
+16\r
+WString\r
+5\r
+WLINK\r
+17\r
+WString\r
+11\r
+?????Dosseg\r
+0\r
+1\r
+18\r
+MCState\r
+19\r
+WString\r
+5\r
+WLINK\r
+20\r
+WString\r
+24\r
+?????Eliminate dead code\r
+0\r
+1\r
+21\r
+WVList\r
+2\r
+22\r
+ActionStates\r
+23\r
+WString\r
+6\r
+&Debug\r
+24\r
+WVList\r
+0\r
+25\r
+ActionStates\r
+26\r
+WString\r
+5\r
+&Make\r
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+-1\r
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+1\r
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+WPickList\r
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+*.c\r
+30\r
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+COBJ\r
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+26\r
+32\r
+MVState\r
+33\r
+WString\r
+3\r
+WCC\r
+34\r
+WString\r
+25\r
+d????Include directories:\r
+1\r
+35\r
+WString\r
+97\r
+$(%watcom)\h;..\common\include;..\..\source\include;..\..\source\portable\owatcom\16bitdos\common\r
+0\r
+36\r
+MCState\r
+37\r
+WString\r
+3\r
+WCC\r
+38\r
+WString\r
+26\r
+?????Force ANSI compliance\r
+1\r
+1\r
+39\r
+MCState\r
+40\r
+WString\r
+3\r
+WCC\r
+41\r
+WString\r
+33\r
+?????Disable stack depth checking\r
+1\r
+1\r
+42\r
+MVState\r
+43\r
+WString\r
+3\r
+WCC\r
+44\r
+WString\r
+23\r
+?????Macro definitions:\r
+1\r
+45\r
+WString\r
+43\r
+OPEN_WATCOM_FLASH_LITE_186_PORT DEBUG_BUILD\r
+0\r
+46\r
+MCState\r
+47\r
+WString\r
+3\r
+WCC\r
+48\r
+WString\r
+34\r
+?????Change char default to signed\r
+1\r
+1\r
+49\r
+MRState\r
+50\r
+WString\r
+3\r
+WCC\r
+51\r
+WString\r
+21\r
+?????Compiler default\r
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+52\r
+MRState\r
+53\r
+WString\r
+3\r
+WCC\r
+54\r
+WString\r
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+56\r
+WString\r
+3\r
+WCC\r
+57\r
+WString\r
+25\r
+?????Floating-point calls\r
+1\r
+1\r
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--- /dev/null
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--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+Changes from V1.00:\r
+ \r
+ + Call to the more efficient portSWITCH_CONTEXT() replaces the call to \r
+ taskYIELD() in the ISR.\r
+\r
+Changes from V1.01:\r
+\r
+ + The semaphore task is not operational. This does nothing but check\r
+ the semaphore from ISR functionality.\r
+ + ISR modified slightly so only Rx or Tx is serviced per ISR - not both.\r
+\r
+Changes from V1.2.0:\r
+\r
+ + Change so Tx uses a DMA channel, and Rx uses an interrupt.\r
+\r
+Changes from V1.2.3\r
+\r
+ + The function xPortInitMinimal() has been renamed to \r
+ xSerialPortInitMinimal() and the function xPortInit() has been renamed\r
+ to xSerialPortInit().\r
+\r
+Changes from V1.2.5\r
+\r
+ + Reverted back to the non-DMA serial port driver, with a slightly modified\r
+ ISR. This is a better test of the scheduler mechanisms.\r
+ + A critical section is now used in vInterruptOn().\r
+ + Flag sTxInterruptOn has been added to the port structure. This allows\r
+ checking of the interrupt enable status without performing any IO.\r
+\r
+Changes from V2.0.0\r
+\r
+ + Use portTickType in place of unsigned pdLONG for delay periods.\r
+ + Slightly more efficient vSerialSendString() implementation.\r
+ + cQueueReieveFromISR() used in place of xQueueReceive() in ISR.\r
+*/\r
+\r
+#include <stdlib.h>\r
+#include <dos.h>\r
+#include "FreeRTOS.h"\r
+#include "queue.h"\r
+#include "task.h"\r
+#include "portasm.h"\r
+#include "semphr.h"\r
+\r
+#define serMAX_PORTS ( ( unsigned portSHORT ) 2 )\r
+\r
+#define serPORT_0_INT_REG ( 0xff44 )\r
+#define serPORT_0_BAUD_REG ( 0xff88 )\r
+#define serPORT_0_RX_REG ( 0xff86 )\r
+#define serPORT_0_TX_REG ( 0xff84 )\r
+#define serPORT_0_STATUS_REG ( 0xff82 )\r
+#define serPORT_0_CTRL_REG ( 0xff80 )\r
+#define serPORT_0_IRQ ( 0x14 )\r
+\r
+#define serPORT_1_INT_REG ( 0xff42 )\r
+#define serPORT_1_BAUD_REG ( 0xff18 )\r
+#define serPORT_1_RX_REG ( 0xff16 )\r
+#define serPORT_1_TX_REG ( 0xff14 )\r
+#define serPORT_1_STATUS_REG ( 0xff12 )\r
+#define serPORT_1_CTRL_REG ( 0xff10 )\r
+#define serPORT_1_IRQ ( 0x11 )\r
+\r
+#define serTX_EMPTY ( ( unsigned portSHORT ) 0x40 )\r
+#define serRX_READY ( ( unsigned portSHORT ) 0x80 )\r
+\r
+#define serRESET_PIC( usEOI_TYPE ) portOUTPUT_WORD( ( unsigned portSHORT ) 0xff22, usEOI_TYPE )\r
+#define serTX_HOLD_EMPTY_INT ( ( unsigned portSHORT ) 0x100 )\r
+\r
+#define serENABLE_INTERRUPTS ( ( unsigned portSHORT ) 0x80 )\r
+#define serMODE ( ( unsigned portSHORT ) 0x01 )\r
+#define serENABLE_TX_MACHINES ( ( unsigned portSHORT ) 0x40 )\r
+#define serENABLE_RX_MACHINES ( ( unsigned portSHORT ) 0x20 )\r
+#define serINTERRUPT_MASK ( ( unsigned portSHORT ) 0x08 )\r
+#define serCLEAR_ALL_STATUS_BITS ( ( unsigned portSHORT ) 0x00 )\r
+#define serINTERRUPT_PRIORITY ( ( unsigned portSHORT ) 0x01 ) /*< Just below the scheduler priority. */\r
+\r
+#define serDONT_BLOCK ( ( portTickType ) 0 )\r
+\r
+typedef enum\r
+{ \r
+ serCOM1 = 0, \r
+ serCOM2, \r
+ serCOM3, \r
+ serCOM4, \r
+ serCOM5, \r
+ serCOM6, \r
+ serCOM7, \r
+ serCOM8 \r
+} eCOMPort;\r
+\r
+typedef enum \r
+{ \r
+ serNO_PARITY, \r
+ serODD_PARITY, \r
+ serEVEN_PARITY, \r
+ serMARK_PARITY, \r
+ serSPACE_PARITY \r
+} eParity;\r
+\r
+typedef enum \r
+{ \r
+ serSTOP_1, \r
+ serSTOP_2 \r
+} eStopBits;\r
+\r
+typedef enum \r
+{ \r
+ serBITS_5, \r
+ serBITS_6, \r
+ serBITS_7, \r
+ serBITS_8 \r
+} eDataBits;\r
+\r
+typedef enum \r
+{ \r
+ ser50 = 0,\r
+ ser75, \r
+ ser110, \r
+ ser134, \r
+ ser150, \r
+ ser200,\r
+ ser300, \r
+ ser600, \r
+ ser1200, \r
+ ser1800, \r
+ ser2400, \r
+ ser4800,\r
+ ser9600, \r
+ ser19200, \r
+ ser38400, \r
+ ser57600, \r
+ ser115200\r
+} eBaud;\r
+\r
+/* Must be same order as eBaud definitions. */\r
+static const unsigned portSHORT usBaudRateDivisor[] = \r
+{\r
+ 0, /* Not sure if the first 6 are correct. First cannot be used. */\r
+ 29127,\r
+ 19859,\r
+ 16302,\r
+ 14564,\r
+ 10923, \r
+ 6879,\r
+ 3437,\r
+ 1718,\r
+ 1145,\r
+ 859,\r
+ 429,\r
+ 214,\r
+ 107,\r
+ 54,\r
+ 35,\r
+ 18\r
+};\r
+\r
+\r
+typedef struct xCOM_PORT\r
+{\r
+ /* Hardware parameters for this port. */\r
+ portSHORT sTxInterruptOn;\r
+ unsigned portSHORT usIntReg;\r
+ unsigned portSHORT usBaudReg;\r
+ unsigned portSHORT usRxReg;\r
+ unsigned portSHORT usTxReg;\r
+ unsigned portSHORT usStatusReg;\r
+ unsigned portSHORT usCtrlReg;\r
+\r
+ unsigned portSHORT usIRQVector;\r
+\r
+ /* Queues used for communications with com test task. */\r
+ xQueueHandle xRxedChars; \r
+ xQueueHandle xCharsForTx;\r
+\r
+ /* This semaphore does nothing useful except test a feature of the\r
+ scheduler. */\r
+ xSemaphoreHandle xTestSem;\r
+\r
+} xComPort;\r
+\r
+static xComPort xPorts[ serMAX_PORTS ] = \r
+{\r
+ { pdFALSE, serPORT_0_INT_REG, serPORT_0_BAUD_REG, serPORT_0_RX_REG, serPORT_0_TX_REG, serPORT_0_STATUS_REG, serPORT_0_CTRL_REG, serPORT_0_IRQ, NULL, NULL, NULL },\r
+ { pdFALSE, serPORT_1_INT_REG, serPORT_1_BAUD_REG, serPORT_1_RX_REG, serPORT_1_TX_REG, serPORT_1_STATUS_REG, serPORT_1_CTRL_REG, serPORT_1_IRQ, NULL, NULL, NULL }\r
+};\r
+\r
+typedef xComPort * xComPortHandle;\r
+\r
+/* These prototypes are repeated here so we don't have to include the serial header. This allows\r
+the xComPortHandle structure details to be private to this file. */\r
+xComPortHandle xSerialPortInit( eCOMPort ePort, eBaud eWantedBaud, eParity eWantedParity, eDataBits eWantedDataBits, eStopBits eWantedStopBits, unsigned portBASE_TYPE uxBufferLength );\r
+portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, portCHAR *pcRxedChar, portTickType xBlockTime );\r
+portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, portCHAR cOutChar, portTickType xBlockTime );\r
+void vSerialClose( xComPortHandle xPort );\r
+portSHORT sSerialWaitForSemaphore( xComPortHandle xPort );\r
+/*-----------------------------------------------------------*/\r
+\r
+static portSHORT xComPortISR( xComPort * const pxPort );\r
+\r
+#define vInterruptOn( pxPort, usInterrupt ) \\r
+{ \\r
+unsigned portSHORT usIn; \\r
+ \\r
+ portENTER_CRITICAL(); \\r
+ { \\r
+ if( pxPort->sTxInterruptOn == pdFALSE ) \\r
+ { \\r
+ usIn = portINPUT_WORD( pxPort->usCtrlReg ); \\r
+ portOUTPUT_WORD( pxPort->usCtrlReg, usIn | usInterrupt ); \\r
+ \\r
+ pxPort->sTxInterruptOn = pdTRUE; \\r
+ } \\r
+ } \\r
+ portEXIT_CRITICAL(); \\r
+} \r
+/*-----------------------------------------------------------*/\r
+\r
+#define vInterruptOff( pxPort, usInterrupt ) \\r
+{ \\r
+ unsigned portSHORT usIn = portINPUT_WORD( pxPort->usCtrlReg ); \\r
+ if( usIn & usInterrupt ) \\r
+ { \\r
+ portOUTPUT_WORD( pxPort->usCtrlReg, usIn & ~usInterrupt); \\r
+ pxPort->sTxInterruptOn = pdFALSE; \\r
+ } \\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+/* Define an interrupt handler for each port */\r
+#define COM_IRQ_WRAPPER(N) \\r
+ static void __interrupt COM_IRQ##N##_WRAPPER( void ) \\r
+ { \\r
+ if( xComPortISR( &( xPorts[##N##] ) ) ) \\r
+ { \\r
+ portSWITCH_CONTEXT(); \\r
+ } \\r
+ }\r
+\r
+ \r
+\r
+COM_IRQ_WRAPPER( 0 )\r
+COM_IRQ_WRAPPER( 1 )\r
+\r
+static pxISR xISRs[ serMAX_PORTS ] = \r
+{\r
+ COM_IRQ0_WRAPPER, \r
+ COM_IRQ1_WRAPPER\r
+};\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+xComPortHandle xSerialPortInit( eCOMPort ePort, eBaud eWantedBaud, eParity eWantedParity, eDataBits eWantedDataBits, eStopBits eWantedStopBits, unsigned portBASE_TYPE uxBufferLength )\r
+{\r
+unsigned portSHORT usPort;\r
+xComPortHandle pxPort = NULL;\r
+\r
+/* BAUDDIV = ( Microprocessor Clock / Baud Rate ) / 16 */\r
+\r
+ /* Only n, 8, 1 is supported so these parameters are not required for this\r
+ port. */\r
+ ( void ) eWantedParity;\r
+ ( void ) eWantedDataBits;\r
+ ( void ) eWantedStopBits;\r
+\r
+ /* Currently only n,8,1 is supported. */\r
+\r
+ usPort = ( unsigned portSHORT ) ePort;\r
+ \r
+ if( usPort < serMAX_PORTS )\r
+ {\r
+ pxPort = &( xPorts[ usPort ] );\r
+\r
+ portENTER_CRITICAL();\r
+ {\r
+ unsigned portSHORT usInWord;\r
+\r
+ /* Create the queues used by the com test task. */\r
+ pxPort->xRxedChars = xQueueCreate( uxBufferLength, ( unsigned portBASE_TYPE ) sizeof( portCHAR ) );\r
+ pxPort->xCharsForTx = xQueueCreate( uxBufferLength, ( unsigned portBASE_TYPE ) sizeof( portCHAR ) );\r
+\r
+ /* Create the test semaphore. This does nothing useful except test a feature of the scheduler. */\r
+ vSemaphoreCreateBinary( pxPort->xTestSem );\r
+\r
+ /* There is no ISR here already to restore later. */\r
+ _dos_setvect( ( portSHORT ) pxPort->usIRQVector, xISRs[ usPort ] );\r
+\r
+ usInWord = portINPUT_WORD( pxPort->usIntReg );\r
+ usInWord &= ~serINTERRUPT_MASK;\r
+ usInWord |= serINTERRUPT_PRIORITY;\r
+ portOUTPUT_WORD( pxPort->usIntReg, usInWord );\r
+\r
+ portOUTPUT_WORD( pxPort->usBaudReg, usBaudRateDivisor[ eWantedBaud ] );\r
+ portOUTPUT_WORD( pxPort->usCtrlReg, serENABLE_INTERRUPTS | serMODE | serENABLE_TX_MACHINES | serENABLE_RX_MACHINES );\r
+\r
+ portOUTPUT_WORD( pxPort->usStatusReg, serCLEAR_ALL_STATUS_BITS );\r
+ }\r
+ portEXIT_CRITICAL();\r
+ }\r
+\r
+ return pxPort;\r
+} /*lint !e715 Some parameters are not used as only a subset of the serial port functionality is currently implemented. */\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSerialPutString( xComPortHandle pxPort, const portCHAR * const pcString, unsigned portSHORT usStringLength )\r
+{\r
+unsigned portSHORT usByte;\r
+portCHAR *pcNextChar;\r
+\r
+ pcNextChar = ( portCHAR * ) pcString;\r
+\r
+ for( usByte = 0; usByte < usStringLength; usByte++ )\r
+ {\r
+ xQueueSend( pxPort->xCharsForTx, pcNextChar, serDONT_BLOCK );\r
+ pcNextChar++;\r
+ }\r
+\r
+ vInterruptOn( pxPort, serTX_HOLD_EMPTY_INT );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, portCHAR *pcRxedChar, portTickType xBlockTime )\r
+{\r
+ /* Get the next character from the buffer, note that this routine is only \r
+ called having checked that the is (at least) one to get */\r
+ if( xQueueReceive( pxPort->xRxedChars, pcRxedChar, xBlockTime ) )\r
+ {\r
+ return pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ return pdFALSE;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, portCHAR cOutChar, portTickType xBlockTime )\r
+{\r
+ if( xQueueSend( pxPort->xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )\r
+ {\r
+ return pdFAIL;\r
+ }\r
+\r
+ vInterruptOn( pxPort, serTX_HOLD_EMPTY_INT );\r
+\r
+ return pdPASS;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portBASE_TYPE xSerialWaitForSemaphore( xComPortHandle xPort )\r
+{\r
+const portTickType xBlockTime = ( portTickType ) 0xffff;\r
+\r
+ /* This function does nothing interesting, but test the \r
+ semaphore from ISR mechanism. */\r
+ return xSemaphoreTake( xPort->xTestSem, xBlockTime );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSerialClose( xComPortHandle xPort )\r
+{\r
+unsigned portSHORT usOutput;\r
+\r
+ /* Turn off the interrupts. We may also want to delete the queues and/or\r
+ re-install the original ISR. */\r
+\r
+ portENTER_CRITICAL();\r
+ {\r
+ usOutput = portINPUT_WORD( xPort->usCtrlReg );\r
+\r
+ usOutput &= ~serENABLE_INTERRUPTS;\r
+ usOutput &= ~serENABLE_TX_MACHINES;\r
+ usOutput &= ~serENABLE_RX_MACHINES;\r
+ portOUTPUT_WORD( xPort->usCtrlReg, usOutput );\r
+\r
+ usOutput = portINPUT_WORD( xPort->usIntReg );\r
+ usOutput |= serINTERRUPT_MASK;\r
+ portOUTPUT_WORD( xPort->usIntReg, usOutput );\r
+ }\r
+ portEXIT_CRITICAL();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portBASE_TYPE xComPortISR( xComPort * const pxPort )\r
+{\r
+unsigned portSHORT usStatusRegister;\r
+portCHAR cChar;\r
+portBASE_TYPE xTaskWokenByPost = pdFALSE, xAnotherTaskWokenByPost = pdFALSE, xTaskWokenByTx = pdFALSE, xContinue = pdTRUE;\r
+\r
+ /* NOTE: THIS IS NOT AN EFFICIENT ISR AS IT IS DESIGNED SOLELY TO TEST\r
+ THE SCHEDULER FUNCTIONALITY. REAL APPLICATIONS SHOULD NOT USE THIS\r
+ FUNCTION. */\r
+\r
+\r
+ while( xContinue == pdTRUE )\r
+ {\r
+ xContinue = pdFALSE;\r
+ usStatusRegister = portINPUT_WORD( pxPort->usStatusReg );\r
+\r
+ if( usStatusRegister & serRX_READY )\r
+ {\r
+ cChar = ( portCHAR ) portINPUT_WORD( pxPort->usRxReg );\r
+ xTaskWokenByPost = xQueueSendFromISR( pxPort->xRxedChars, &cChar, xTaskWokenByPost );\r
+\r
+ /* Also release the semaphore - this does nothing interesting and is just a test. */\r
+ xAnotherTaskWokenByPost = xSemaphoreGiveFromISR( pxPort->xTestSem, xAnotherTaskWokenByPost );\r
+\r
+ /* We have performed an action this cycle - there may be other to perform. */\r
+ xContinue = pdTRUE;\r
+ }\r
+\r
+ if( pxPort->sTxInterruptOn && ( usStatusRegister & serTX_EMPTY ) )\r
+ {\r
+ if( xQueueReceiveFromISR( pxPort->xCharsForTx, &cChar, &xTaskWokenByTx ) == pdTRUE )\r
+ {\r
+ portOUTPUT_WORD( pxPort->usTxReg, ( unsigned portSHORT ) cChar );\r
+\r
+ /* We have performed an action this cycle - there may be others to perform. */\r
+ xContinue = pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ /* Queue empty, nothing to send */\r
+ vInterruptOff( pxPort, serTX_HOLD_EMPTY_INT );\r
+ }\r
+ }\r
+ }\r
+\r
+ serRESET_PIC( pxPort->usIRQVector );\r
+\r
+ /* If posting to the queue woke a task that was blocked on the queue we may\r
+ want to switch to the woken task - depending on its priority relative to\r
+ the task interrupted by this ISR. */\r
+ if( xTaskWokenByPost || xAnotherTaskWokenByPost || xTaskWokenByTx)\r
+ {\r
+ return pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ return pdFALSE;\r
+ }\r
+}\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+[HIMDBVersion]\r
+2.0\r
+[DATABASE_VERSION]\r
+"7.0" \r
+[WORKSPACE_DETAILS]\r
+"RTOSDemo" "C:\E\Dev\FreeRTOS\Demo\H8S" "C:\E\Dev\FreeRTOS\Demo\H8S\RTOSDemo.hws" "H8S,H8/300" "KPIT GNUH8 [ELF]" \r
+[SHARED_WORKSPACE_CONTROL_STATUS]\r
+"" "" "" \r
+"" "" "" \r
+[PROJECTS]\r
+"RTOSDemo" "C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo" "C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\rtosdemo.hwp" 0 \r
+[INFORMATION]\r
+"No workspace information available" \r
+[SCRAP]\r
+[PROJECT_DEPENDENCY]\r
+[WORKSPACE_PROPERTIES]\r
+[VCS]\r
+"" "" "" 0 \r
+[VCS_PROJECT]\r
+[HELP_FILES]\r
+[GENERAL_DATA_PROJECT]\r
+[SYSMENUTOOLS]\r
+"GNUH8 Archive Editor" "1.1" \r
+"Hitachi Mapview" "1.0" \r
+"Hitachi H Series Librarian Interface" "1.1" \r
+"Hitachi Call Walker" "1.1" \r
+[USERMENUTOOLS]\r
+[CUSTOMPLACEHOLDERS]\r
+[MAKEFILE_BUILD_INFO]\r
+"$(WORKSPDIR)\make\$(WORKSPNAME).mak" "" 0 0 \r
+[VD_CONFIGURATION_OPTIONS]\r
+"ACTIVE_DESKTOP" "0" \r
+[VD_CONFIGURATIONS]\r
+"0" "Default1" "1" \r
+"1" "Default2" "1" \r
+"2" "Default3" "1" \r
+"3" "Default4" "1" \r
+[END]\r
--- /dev/null
+[HIMDBVersion]\r
+2.0\r
+[DATABASE_VERSION]\r
+"1.0" \r
+[CURRENT_PROJECT]\r
+"RTOSDemo" \r
+[GENERAL_DATA]\r
+"EDITOR_WINDOWS_MAXIMISED" "1" \r
+[BREAKPOINTS]\r
+[OPEN_WORKSPACE_FILES]\r
+"C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\partest\partest.c" \r
+"c:\e\Dev\FreeRTOS\Source\queue.c" \r
+"C:\E\Dev\FreeRTOS\Source\portable\GCC\H8S2329\portmacro.h" \r
+"C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\serial\serial.c" \r
+"c:\e\Dev\FreeRTOS\Source\portable\GCC\H8S2329\port.c" \r
+"C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\main.c" \r
+"C:\E\Dev\FreeRTOS\Source\include\portable.h" \r
+"c:\e\Dev\FreeRTOS\Demo\Common\Minimal\BlockQ.c" \r
+[WORKSPACE_FILE_STATES]\r
+"c:\e\Dev\FreeRTOS\Demo\Common\Minimal\BlockQ.c" "0,0,954,459,0" \r
+"C:\E\Dev\FreeRTOS\Source\include\portable.h" "44,66,958,463,0" \r
+"C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\partest\partest.c" "-4,-34,1098,699,1" \r
+"C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\main.c" "66,99,958,463,0" \r
+"c:\e\Dev\FreeRTOS\Source\portable\GCC\H8S2329\port.c" "88,132,958,463,0" \r
+"C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\serial\serial.c" "110,165,958,463,0" \r
+"C:\E\Dev\FreeRTOS\Source\portable\GCC\H8S2329\portmacro.h" "132,198,958,463,0" \r
+"c:\e\Dev\FreeRTOS\Source\queue.c" "0,0,958,463,0" \r
+[END]\r
--- /dev/null
+#ifndef INC_2329_H\r
+#define INC_2329_H\r
+\r
+/* DATA TYPES MIGHT NOT BE CORRECT. */\r
+\r
+#define BASE2329 0xFF0000\r
+\r
+/* Definitions for GPIO. */\r
+\r
+#define P1DDR ( *( ( volatile unsigned char * ) 0xFFFEB0 ) )\r
+#define P1DR ( *( ( volatile unsigned char * ) 0xFFFF60 ) )\r
+#define PORT1 ( *( ( volatile unsigned char * ) 0xFFFF50 ) )\r
+#define P2DDR ( *( ( volatile unsigned char * ) 0xFFFEB1 ) )\r
+#define P2DR ( *( ( volatile unsigned char * ) 0xFFFF61 ) )\r
+#define PORT2 ( *( ( volatile unsigned char * ) 0xFFFF51 ) )\r
+#define P3DDR ( *( ( volatile unsigned char * ) 0xFFFEB2 ) )\r
+#define P3DR ( *( ( volatile unsigned char * ) 0xFFFF62 ) )\r
+#define PORT3 ( *( ( volatile unsigned char * ) 0xFFFF52 ) )\r
+#define P3ODR ( *( ( volatile unsigned char * ) 0xFFFF76 ) )\r
+#define PORT4 ( *( ( volatile unsigned char * ) 0xFFFF53 ) )\r
+#define P5DDR ( *( ( volatile unsigned char * ) 0xFFFEB4 ) )\r
+#define P5DR ( *( ( volatile unsigned char * ) 0xFFFF64 ) )\r
+#define PORT5 ( *( ( volatile unsigned char * ) 0xFFFF54 ) )\r
+#define PFCR2 ( *( ( volatile unsigned char * ) 0xFFFFAC ) )\r
+#define SYSCR ( *( ( volatile unsigned char * ) 0xFFFF39 ) )\r
+#define P6DDR ( *( ( volatile unsigned char * ) 0xFFFEB5 ) )\r
+#define P6DR ( *( ( volatile unsigned char * ) 0xFFFF65 ) )\r
+#define PORT6 ( *( ( volatile unsigned char * ) 0xFFFF55 ) )\r
+#define PFCR2 ( *( ( volatile unsigned char * ) 0xFFFFAC ) )\r
+#define PADDR ( *( ( volatile unsigned char * ) 0xFFFEB9 ) )\r
+#define PADR ( *( ( volatile unsigned char * ) 0xFFFF69 ) )\r
+#define PORTA ( *( ( volatile unsigned char * ) 0xFFFF59 ) )\r
+#define PAPCR ( *( ( volatile unsigned char * ) 0xFFFF70 ) )\r
+#define PAODR ( *( ( volatile unsigned char * ) 0xFFFF77 ) )\r
+#define PFCR1 ( *( ( volatile unsigned char * ) 0xFFFF45 ) )\r
+#define PBDDR ( *( ( volatile unsigned char * ) 0xFFFEBA ) )\r
+#define PBDR ( *( ( volatile unsigned char * ) 0xFFFF6A ) )\r
+#define PORTB ( *( ( volatile unsigned char * ) 0xFFFF5A ) )\r
+#define PBPCR ( *( ( volatile unsigned char * ) 0xFFFF71 ) )\r
+#define PCDDR ( *( ( volatile unsigned char * ) 0xFFFEBB ) )\r
+#define PCDR ( *( ( volatile unsigned char * ) 0xFFFF6B ) )\r
+#define PORTC ( *( ( volatile unsigned char * ) 0xFFFF5B ) )\r
+#define PCPCR ( *( ( volatile unsigned char * ) 0xFFFF72 ) )\r
+#define PDDDR ( *( ( volatile unsigned char * ) 0xFFFEBC ) )\r
+#define PDDR ( *( ( volatile unsigned char * ) 0xFFFF6C ) )\r
+#define PORTD ( *( ( volatile unsigned char * ) 0xFFFF5C ) )\r
+#define PDPCR ( *( ( volatile unsigned char * ) 0xFFFF73 ) )\r
+#define PEDDR ( *( ( volatile unsigned char * ) 0xFFFEBD ) )\r
+#define PEDR ( *( ( volatile unsigned char * ) 0xFFFF6D ) )\r
+#define PORTE ( *( ( volatile unsigned char * ) 0xFFFF5D ) )\r
+#define PEPCR ( *( ( volatile unsigned char * ) 0xFFFF74 ) )\r
+#define PFDDR ( *( ( volatile unsigned char * ) 0xFFFEBE ) )\r
+#define PFDR ( *( ( volatile unsigned char * ) 0xFFFF6E ) )\r
+#define PORTF ( *( ( volatile unsigned char * ) 0xFFFF5E ) )\r
+#define PFCR2 ( *( ( volatile unsigned char * ) 0xFFFFAC ) )\r
+#define SYSCR ( *( ( volatile unsigned char * ) 0xFFFF39 ) )\r
+#define PGDDR ( *( ( volatile unsigned char * ) 0xFFFEBF ) )\r
+#define PGDR ( *( ( volatile unsigned char * ) 0xFFFF6F ) )\r
+#define PORTG ( *( ( volatile unsigned char * ) 0xFFFF5F ) )\r
+#define PFCR2 ( *( ( volatile unsigned char * ) 0xFFFFAC ) )\r
+\r
+\r
+/* Definitions for TPU. */\r
+\r
+#define TCR0 ( *( ( volatile unsigned char * ) 0xFFFFD0 ) )\r
+#define TMDR0 ( *( ( volatile unsigned char * ) 0xFFFFD1 ) )\r
+#define TIOR0H ( *( ( volatile unsigned char * ) 0xFFFFD2 ) )\r
+#define TIOR0L ( *( ( volatile unsigned char * ) 0xFFFFD3 ) )\r
+#define TIER0 ( *( ( volatile unsigned char * ) 0xFFFFD4 ) )\r
+#define TSR0 ( *( ( volatile unsigned char * ) 0xFFFFD5 ) )\r
+#define TCNT0 ( *( ( volatile unsigned short * ) 0xFFFFD6 ) )\r
+#define TGR0A ( *( ( volatile unsigned short * ) 0xFFFFD8 ) )\r
+#define TGR0B ( *( ( volatile unsigned short * ) 0xFFFFDA ) )\r
+#define TGR0C ( *( ( volatile unsigned short * ) 0xFFFFDC ) )\r
+#define TGR0D ( *( ( volatile unsigned short * ) 0xFFFFDE ) )\r
+#define TCR1 ( *( ( volatile unsigned char * ) 0xFFFFE0 ) )\r
+#define TMDR1 ( *( ( volatile unsigned char * ) 0xFFFFE1 ) )\r
+#define TIOR1 ( *( ( volatile unsigned char * ) 0xFFFFE2 ) )\r
+#define TIER1 ( *( ( volatile unsigned char * ) 0xFFFFE4 ) )\r
+#define TSR1 ( *( ( volatile unsigned char * ) 0xFFFFE5 ) )\r
+#define TCNT1 ( *( ( volatile unsigned short * ) 0xFFFFE6 ) )\r
+#define TGR1A ( *( ( volatile unsigned short * ) 0xFFFFE8 ) )\r
+#define TGR1B ( *( ( volatile unsigned short * ) 0xFFFFEA ) )\r
+#define TCR2 ( *( ( volatile unsigned char * ) 0xFFFFF0 ) )\r
+#define TMDR2 ( *( ( volatile unsigned char * ) 0xFFFFF1 ) )\r
+#define TIOR2 ( *( ( volatile unsigned char * ) 0xFFFFF2 ) )\r
+#define TIER2 ( *( ( volatile unsigned char * ) 0xFFFFF4 ) )\r
+#define TSR2 ( *( ( volatile unsigned char * ) 0xFFFFF5 ) )\r
+#define TCNT2 ( *( ( volatile unsigned short * ) 0xFFFFF6 ) )\r
+#define TGR2A ( *( ( volatile unsigned short * ) 0xFFFFF8 ) )\r
+#define TGR2B ( *( ( volatile unsigned short * ) 0xFFFFFA ) )\r
+#define TCR3 ( *( ( volatile unsigned char * ) 0xFFFE80 ) )\r
+#define TMDR3 ( *( ( volatile unsigned char * ) 0xFFFE81 ) )\r
+#define TIOR3H ( *( ( volatile unsigned char * ) 0xFFFE82 ) )\r
+#define TIOR3L ( *( ( volatile unsigned char * ) 0xFFFE83 ) )\r
+#define TIER3 ( *( ( volatile unsigned char * ) 0xFFFE84 ) )\r
+#define TSR3 ( *( ( volatile unsigned char * ) 0xFFFE85 ) )\r
+#define TCNT3 ( *( ( volatile unsigned short * ) 0xFFFE86 ) )\r
+#define TGR3A ( *( ( volatile unsigned short * ) 0xFFFE88 ) )\r
+#define TGR3B ( *( ( volatile unsigned short * ) 0xFFFE8A ) )\r
+#define TGR3C ( *( ( volatile unsigned short * ) 0xFFFE8C ) )\r
+#define TGR3D ( *( ( volatile unsigned short * ) 0xFFFE8E ) )\r
+#define TCR4 ( *( ( volatile unsigned char * ) 0xFFFE90 ) )\r
+#define TMDR4 ( *( ( volatile unsigned char * ) 0xFFFE91 ) )\r
+#define TIOR4 ( *( ( volatile unsigned char * ) 0xFFFE92 ) )\r
+#define TIER4 ( *( ( volatile unsigned char * ) 0xFFFE94 ) )\r
+#define TSR4 ( *( ( volatile unsigned char * ) 0xFFFE95 ) )\r
+#define TCNT4 ( *( ( volatile unsigned short * ) 0xFFFE96 ) )\r
+#define TGR4A ( *( ( volatile unsigned short * ) 0xFFFE98 ) )\r
+#define TGR4B ( *( ( volatile unsigned short * ) 0xFFFE9A ) )\r
+#define TCR5 ( *( ( volatile unsigned char * ) 0xFFFEA0 ) )\r
+#define TMDR5 ( *( ( volatile unsigned char * ) 0xFFFEA1 ) )\r
+#define TIOR5 ( *( ( volatile unsigned char * ) 0xFFFEA2 ) )\r
+#define TIER5 ( *( ( volatile unsigned char * ) 0xFFFEA4 ) )\r
+#define TSR5 ( *( ( volatile unsigned char * ) 0xFFFEA5 ) )\r
+#define TCNT5 ( *( ( volatile unsigned short * ) 0xFFFEA6 ) )\r
+#define TGR5A ( *( ( volatile unsigned short * ) 0xFFFEA8 ) )\r
+#define TGR5B ( *( ( volatile unsigned short * ) 0xFFFEAA ) )\r
+#define TSTR ( *( ( volatile unsigned char * ) 0xFFFFC0 ) )\r
+#define TSYR ( *( ( volatile unsigned char * ) 0xFFFFC1 ) )\r
+\r
+\r
+#define MSTPCR ( *( ( volatile unsigned short * ) 0xFFFF3C ) )\r
+#define SCKCR ( *( ( volatile unsigned short * ) 0xFFFF3A ) )\r
+\r
+/* Serial port. */\r
+\r
+#define SMR0 ( *( ( volatile unsigned char * ) 0xFFFF78 ) )\r
+#define BRR0 ( *( ( volatile unsigned char * ) 0xFFFF79 ) )\r
+#define SCR0 ( *( ( volatile unsigned char * ) 0xFFFF7A ) )\r
+#define TDR0 ( *( ( volatile unsigned char * ) 0xFFFF7B ) )\r
+#define SSR0 ( *( ( volatile unsigned char * ) 0xFFFF7C ) )\r
+#define RDR0 ( *( ( volatile unsigned char * ) 0xFFFF7D ) )\r
+#define SCMR0 ( *( ( volatile unsigned char * ) 0xFFFF7E ) )\r
+#define SMR1 ( *( ( volatile unsigned char * ) 0xFFFF80 ) )\r
+#define BRR1 ( *( ( volatile unsigned char * ) 0xFFFF81 ) )\r
+#define SCR1 ( *( ( volatile unsigned char * ) 0xFFFF82 ) )\r
+#define TDR1 ( *( ( volatile unsigned char * ) 0xFFFF83 ) )\r
+#define SSR1 ( *( ( volatile unsigned char * ) 0xFFFF84 ) )\r
+#define RDR1 ( *( ( volatile unsigned char * ) 0xFFFF85 ) )\r
+\r
+#endif\r
--- /dev/null
+[HEWGNUBARNEYMCGREW]\r
+SELECTEDCPU=H8/S2000\r
+SELECTEDMODE=Advanced\r
+INT32=N\r
+SELECTEDRENESAS=N\r
+SELECTEDENDIAN=Big endian\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/* IO definitions for the chosen device. */\r
+#include <2329S.h>\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. \r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 22118400 )\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 4 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 200 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 15 * 1024 ) )\r
+#define configMAX_TASK_NAME_LEN ( 8 )\r
+#define configUSE_TRACE_FACILITY 0\r
+#define configUSE_16_BIT_TICKS 1\r
+#define configIDLE_SHOULD_YIELD 1\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+\r
+\r
+\r
+\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "portable.h"\r
+\r
+/* Demo application include files. */\r
+#include "partest.h"\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple parallel port IO routines.\r
+ *\r
+ * This is for the demo application which uses port 2 for LED outputs.\r
+ *-----------------------------------------------------------*/\r
+\r
+/* Value for the LED to be off. */\r
+#define partstLED_OUTPUTS ( ( unsigned portCHAR ) 0xff )\r
+\r
+/* P2.0 is not used as an output so there are only 7 LEDs on port 2. */\r
+#define partstMAX_LEDs ( 7 )\r
+#define partstALL_OUTPUTS_OFF ( ( unsigned portCHAR ) 0 )\r
+\r
+/* Maps the LED outputs used by the standard demo application files to\r
+convenient outputs for the EDK2329. Mainly this insures that the LED\r
+used by the Check task is one of the on board LEDs so the demo can be\r
+executed on an EDK without any modification. */\r
+static inline unsigned portCHAR prvMapLED( unsigned portBASE_TYPE uxLED );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestInitialise( void )\r
+{\r
+ /* LED's are connected to port 2. P2.1 and P2.2 are built onto the EDK.\r
+ P2.3 to P2.7 are soldered onto the expansion port. */\r
+ P2DDR = partstLED_OUTPUTS;\r
+ P2DR = partstALL_OUTPUTS_OFF;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Described at the top of the file.\r
+ */\r
+static inline unsigned portCHAR prvMapLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+ switch( uxLED )\r
+ {\r
+ case 0 : return ( unsigned portCHAR ) 2;\r
+ case 1 : return ( unsigned portCHAR ) 3;\r
+ case 2 : return ( unsigned portCHAR ) 4;\r
+ case 3 : return ( unsigned portCHAR ) 5;\r
+ case 4 : return ( unsigned portCHAR ) 6;\r
+ case 5 : return ( unsigned portCHAR ) 0;\r
+ case 6 : return ( unsigned portCHAR ) 1;\r
+ default : return 0;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Turn an LED on or off.\r
+ */\r
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )\r
+{\r
+unsigned portCHAR ucLED;\r
+\r
+ if( uxLED < partstMAX_LEDs )\r
+ {\r
+ ucLED = prvMapLED( uxLED );\r
+\r
+ /* Set a bit in the required LED position. LED 0 is bit 1. */\r
+ ucLED = ( unsigned portCHAR ) 1 << ( ucLED + 1 );\r
+\r
+ if( xValue )\r
+ {\r
+ portENTER_CRITICAL();\r
+ P2DR |= ucLED;\r
+ portEXIT_CRITICAL();\r
+ }\r
+ else\r
+ {\r
+ portENTER_CRITICAL();\r
+ P2DR &= ~ucLED;\r
+ portEXIT_CRITICAL();\r
+ } \r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+unsigned portCHAR ucLED;\r
+\r
+ if( uxLED < partstMAX_LEDs )\r
+ {\r
+ ucLED = prvMapLED( uxLED );\r
+\r
+ /* Set a bit in the required LED position. LED 0 is bit 1. */\r
+ ucLED = ( unsigned portCHAR ) 1 << ( ucLED + 1 );\r
+\r
+ portENTER_CRITICAL();\r
+ {\r
+ if( P2DR & ucLED )\r
+ {\r
+ P2DR &= ~ucLED;\r
+ }\r
+ else\r
+ {\r
+ P2DR |= ucLED;\r
+ }\r
+ }\r
+ portEXIT_CRITICAL();\r
+ } \r
+}\r
+\r
+\r
+\r
--- /dev/null
+[HIMDBVersion]\r
+2.0\r
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+"2.7" \r
+[PROJECT_DETAILS]\r
+"RTOSDemo" "C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo" "C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\rtosdemo.hwp" "H8S,H8/300" "KPIT GNUH8 [ELF]" "C Application" "" "" \r
+[INFORMATION]\r
+"No project information available" \r
+[TOOL_CHAIN]\r
+"KPIT GNUH8 [ELF] Toolchain" "v0601" \r
+[CONFIGURATIONS]\r
+"Release" "C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\release" \r
+"Debug" "C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\debug" \r
+[BUILD_PHASES]\r
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+"C++ header file" "HPP" \r
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+"C++ source file" "CC" \r
+"C++ source file" "CPP" \r
+"C++ source file" "CXX" \r
+"C header file" "H" \r
+"C source file" "C" \r
+"Object file" "O" \r
+"Assembly source file" "SRC" \r
+"Assembly source file" "S" \r
+"Assembly header file" "INC" \r
+"Assembly list file" "LST" \r
+"Linker map file" "MAP" \r
+"Archive file" "A" \r
+"S-Record file" "MOT" \r
+"Linker output file" "X" \r
+[FILE_GROUPS]\r
+"Preprocess Assembly file" "TEXT" "EDITOR" "" \r
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+"Linker output file" "BIN" "NONE" "" \r
+[ASSOCIATED_APPLICATIONS]\r
+[TOOLCHAIN_PHASE]\r
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+"GNU Compiler" 1 \r
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+"GNU Assembler" 1 \r
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+[MAPPINGS]\r
+"Object file" "GNU Linker" "GNU Assembler" \r
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+"C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\main.c" "User" "Demo App Source" 2 \r
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+[FOLDER]\r
+"Preprocess Assembly file" "Preprocess Assembly file" \r
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+[GENERAL_DATA_PROJECT]\r
+"FDT_Comments" "" \r
+"FDT_BaseDevice" "2329" \r
+"FDT_UseDefaultBaudRate" "TRUE" \r
+"FDT_Interface" "Direct Connection" \r
+"FDT_ResetOnDisconnect" "No" \r
+"FDT_ConnectionResetSuppression" "FFFFFFFF" \r
+"FDT_ResetPinOutputs" "FFFFFFFF" \r
+"FDT_ResetPinSettings" "FFFFFFFF" \r
+"FDT_UPMPinSettings" "FFFFFFFF" \r
+"FDT_KernelResident" "FALSE" \r
+"FDT_KernelPath" "D:\DevTools\Hitachi\FDT2.2\Kernels\ProtB\2329\hitachi\1_1_00\" \r
+"FDT_UserPinSettings" "FFFFFFFF" \r
+"FDT_UserPinOutputs" "FFFFFFFF" \r
+"FDT_ClockMode" "0" \r
+"FDT_CKM" "1" \r
+"FDT_UseInternalKernel" "FALSE" \r
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+"FDT_MessageLevel" "1" \r
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+"FDT_BaudRate" "115200" \r
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+"FDT_ReinterrogateGenericDevice" "No" \r
+"FDT_DoReadbackVerification" "No" \r
+"FDT_Frequency" "2212.0000" \r
+"FDT_AutoConnect" "0" \r
+"FDT_Device" "H8S/2329BF" \r
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+"Single Shot" "035cc29ffd646c10" 5 \r
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+"" 0 \r
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+ 0 0 0 0 0 1 _bss <<FEND>> 0 .bss All files <<FEND>> 0 COMMON All files <<FEND>> 1 _ebss <<FEND>> 1 _end <<FEND>> <<CEND>> <<GEND>> .stack 0 0 1 0x00FFFBFE 0 0 1 _stack <<FEND>> <<CEND>> <<GEND>> \r
+ ] [B|OPTMEM|1] [B|ODEBSYM|1] [S|APPTXT|-e _start] " 5 \r
+[OPTIONS_Debug_GNU Assembler]\r
+"Assembly source file" "0345a29ffd646c10" 4 \r
+[OPTIONS_Debug_GNU Compiler]\r
+"c:\e\Dev\FreeRTOS\Source\portable\MemMang\heap_2.c" "0345a29ffd646c10" 1 \r
+"Preprocess Assembly file" "0345a29ffd646c10" 2 \r
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+"c:\e\Dev\FreeRTOS\Demo\Common\Minimal\comtest.c" "0345a29ffd646c10" 1 \r
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+"c:\e\Dev\FreeRTOS\Demo\Common\Minimal\dynamic.c" "0345a29ffd646c10" 1 \r
+[OPTIONS_Debug_GNU Linker]\r
+"Single Shot" "0345a29ffd646c10" 5 \r
+[OPTIONS_Debug]\r
+"" 0 \r
+"[V|VERSION|1] [B|DONTLINK|1] [B|TREATC|1] [S|INCDIR|$(TCINSTALL)\h8300-elf\include*$(TCINSTALL)\h8300-elf\h8300-elf\include*$(TCINSTALL)\h8300-elf\lib\gcc\h8300-elf\4.0-GNUH8_v0601\include*$(PROJDIR)\..\..\..\source\include*$(PROJDIR)*$(PROJDIR)\..\..\common\include] [S|DEFINES|GCC_H8S*DEBUG] [S|OBJPATH|$(CONFIGDIR)\$(FILELEAF).o] [I|DEBUGLV|2] [S|DEBUGFT|DWARF] [B|LOUTLIST|1] [B|LINCHLS|1] [B|LINCASS|1] [S|LFILE|^"$(CONFIGDIR)\$(FILELEAF).lst^"] [S|CPU|Sample H8/S2000 Device] [S|CPUTYPE|H8/S2000] [S|ENDIAN|Big endian] [B|MALIGN300|0] [B|MRELAX|0] [B|MNORMAL|0] [B|MSLOWBYTE|0] [B|MQUICKCALL|0] [B|MINT32|0] [B|MSIZE|0] " 1 \r
+"[V|VERSION|1] [B|DONTLINK|1] [B|TREATPREASS|1] [S|INCDIR|$(TCINSTALL)\h8300-elf\include*$(TCINSTALL)\h8300-elf\h8300-elf\include*$(TCINSTALL)\h8300-elf\lib\gcc\h8300-elf\4.0-GNUH8_v0601\include*$(PROJDIR)\..\..\..\source\include*$(PROJDIR)*$(PROJDIR)\..\..\common\include] [S|DEFINES|GCC_H8S*DEBUG] [S|OBJPATH|$(CONFIGDIR)\$(FILELEAF).o] [I|DEBUGLV|2] [S|DEBUGFT|DWARF] [B|LOUTLIST|1] [B|LINCHLS|1] [B|LINCASS|1] [S|LFILE|^"$(CONFIGDIR)\$(FILELEAF).lst^"] [S|CPU|Sample H8/S2000 Device] [S|CPUTYPE|H8/S2000] [S|ENDIAN|Big endian] [B|MALIGN300|0] [B|MRELAX|0] [B|MNORMAL|0] [B|MSLOWBYTE|0] [B|MQUICKCALL|0] [B|MINT32|0] [B|MSIZE|0] " 2 \r
+"[V|VERSION|1] [B|DONTLINK|1] [B|TREATCPP|1] [S|INCDIR|$(TCINSTALL)\h8300-elf\include*$(TCINSTALL)\h8300-elf\h8300-elf\include*$(TCINSTALL)\h8300-elf\lib\gcc\h8300-elf\4.0-GNUH8_v0601\include*$(PROJDIR)\..\..\..\source\include*$(PROJDIR)*$(PROJDIR)\..\..\common\include] [S|DEFINES|GCC_H8S*DEBUG] [S|OBJPATH|$(CONFIGDIR)\$(FILELEAF).o] [I|DEBUGLV|2] [S|DEBUGFT|DWARF] [B|LOUTLIST|1] [B|LINCHLS|1] [B|LINCASS|1] [S|LFILE|^"$(CONFIGDIR)\$(FILELEAF).lst^"] [S|CPU|Sample H8/S2000 Device] [S|CPUTYPE|H8/S2000] [S|ENDIAN|Big endian] [B|MALIGN300|0] [B|MRELAX|0] [B|MNORMAL|0] [B|MSLOWBYTE|0] [B|MQUICKCALL|0] [B|MINT32|0] [B|MSIZE|0] " 3 \r
+"[V|VERSION|1] [S|OBJPATH|$(CONFIGDIR)\$(FILELEAF).o] [S|ENDIAN|Big endian] [S|DEBUGLEVEL|Dwarf2 (ELF toolchain only)] [B|LINCHLS|1] [B|LINCASS|1] [B|LINCSYM|1] [S|LFILE|$(CONFIGDIR)\$(FILELEAF).lst] " 4 \r
+"[V|VERSION|1] [S|ARCHIVE|m*c*gcc] [S|INCDIR|$(TCINSTALL)\h8300-elf\lib\gcc\h8300-elf\4.0-GNUH8_v0601\h8300s*$(TCINSTALL)\h8300-elf\h8300-elf\lib\h8300s] [B|RSARCH|1] [S|OUTFILE|$(CONFIGDIR)\$(PROJECTNAME).x] [S|ENDIAN|Big endian] [S|OUTFORM|Default] [B|MFILEGEN|1] [S|PLMFILE|$(CONFIGDIR)\$(PROJECTNAME).map] [S|GROUPDET|.vects 0 0 1 0x00000000 0 1 <<CEND>> <<GEND>> .text 0 0 1 0x00000200 0 0 0 .text All files <<FEND>> 0 .text.* All files <<FEND>> 1 etext <<FEND>> <<CEND>> <<GEND>> .init 0 0 0 0 0 0 .init All files <<FEND>> <<CEND>> <<GEND>> .fini 0 0 0 0 0 0 .fini All files <<FEND>> <<CEND>> <<GEND>> .got 0 0 0 0 0 0 .got All files <<FEND>> 0 .got.plt All files <<FEND>> <<CEND>> <<GEND>> .rodata 0 0 0 0 0 0 .rodata All files <<FEND>> 0 .rodata.* All files <<FEND>> 1 _erodata <<FEND>> <<CEND>> <<GEND>> .eh_frame_hdr 0 0 0 0 0 0 .eh_frame_hdr All files <<FEND>> <<CEND>> <<GEND>> .eh_frame 0 0 0 0 0 0 .eh_frame All files <<FEND>> <<CEND>> <<GEND>> .jcr 0 0 0 0 0 0 .jcr All files <<FEND>> <<CEND>> <<GEND>> .tors 0 0 0 0 0 1 __CTOR_LIST__ <<FEND>> 1 ___ctors <<FEND>> 0 .ctors All files <<FEND>> 1 ___ctors_end <<FEND>> 1 __CTOR_END__ <<FEND>> 1 __DTOR_LIST__ <<FEND>> 1 ___dtors <<FEND>> 0 .dtors All files <<FEND>> 1 ___dtors_end <<FEND>> 1 __DTOR_END__ <<FEND>> 1 _mdata <<FEND>> <<CEND>> <<GEND>> .data 0 0 _mdata 1 0x00FF7C00 0 0 1 _data <<FEND>> 0 .data All files <<FEND>> 0 .data.* All files <<FEND>> 1 _edata <<FEND>> <<CEND>> <<GEND>> .gcc_exc 0 0 0 0 0 0 .gcc_exc All files <<FEND>> <<CEND>> \r
+<<GEND>> .bss 0 0 0 0 0 1 _bss <<FEND>> 0 .bss All files <<FEND>> 0 COMMON All files <<FEND>> 1 _ebss <<FEND>> 1 _end <<FEND>> <<CEND>> <<GEND>> .stack 0 0 1 0x00FFFBFE 0 0 1 _stack <<FEND>> <<CEND>> <<GEND>> \r
+ ] [S|APPTXT|-e _start] " 5 \r
+[SESSION_DATA_CONFIGURATION_SESSION_Release_Release session]\r
+"MEMORY_MAPPING_OPTIONS" "" \r
+[SESSION_DATA_CONFIGURATION_SESSION_Release_Simulator]\r
+"MEMORY_MAPPING_OPTIONS" "" \r
+[SESSION_DATA_CONFIGURATION_SESSION_Debug_Release session]\r
+"MEMORY_MAPPING_OPTIONS" "" \r
+[SESSION_DATA_CONFIGURATION_SESSION_Debug_Simulator]\r
+"MEMORY_MAPPING_OPTIONS" "" \r
+[EXT_DEBUGGER_INFO]\r
+0 "" "" "" "" \r
+[EXCLUDED_FILES_Debug]\r
+[BUILD_FILE_ORDER_Assembly list file]\r
+[BUILD_FILE_ORDER_Assembly header file]\r
+[LINKAGE_ORDER_Debug]\r
+[BUILD_FILE_ORDER_Linker output file]\r
+[BUILD_FILE_ORDER_C header file]\r
+[BUILD_FILE_ORDER_S-Record file]\r
+[BUILD_FILE_ORDER_Linker map file]\r
+[GENERAL_DATA_CONFIGURATION_Release]\r
+[BUILD_FILE_ORDER_Object file]\r
+[GENERAL_DATA_CONFIGURATION_SESSION_Debug_Simulator]\r
+[GENERAL_DATA_CONFIGURATION_SESSION_Release_Release session]\r
+[GENERAL_DATA_CONFIGURATION_SESSION_Release_Simulator]\r
+[GENERAL_DATA_CONFIGURATION_SESSION_Debug_Release session]\r
+[BUILD_FILE_ORDER_Archive file]\r
+[EXCLUDED_FILES_Release]\r
+[BUILD_FILE_ORDER_C++ header file]\r
+[GENERAL_DATA_CONFIGURATION_Debug]\r
+[LINKAGE_ORDER_Release]\r
+[END]\r
--- /dev/null
+[HIMDBVersion]\r
+2.0\r
+[DATABASE_VERSION]\r
+"1.1" \r
+[SESSIONS_]\r
+"Release session" \r
+"Simulator" \r
+[CONFIGURATIONS]\r
+"Debug" \r
+"Release" \r
+[CURRENT_CONFIGURATION]\r
+"Release" \r
+[CURRENT_SESSION]\r
+"Release session" \r
+[GENERAL_DATA_PROJECT]\r
+"FDT_UserBootAreaFiles" "" \r
+[GENERAL_DATA_CONFIGURATION_Debug]\r
+"PROJECT_FILES_MODIFIED_DATA_TAG" "TRUE" \r
+[SESSIONS_Debug]\r
+"Release session" \r
+"Simulator" \r
+[GENERAL_DATA_CONFIGURATION_Release]\r
+"PROJECT_FILES_MODIFIED_DATA_TAG" "FALSE" \r
+[SESSIONS_Release]\r
+"Release session" \r
+"Simulator" \r
+[GENERAL_DATA_CONFIGURATION_SESSION_Debug_Simulator]\r
+[GENERAL_DATA_SESSION_Release session]\r
+[GENERAL_DATA_CONFIGURATION_SESSION_Release_Release session]\r
+[GENERAL_DATA_CONFIGURATION_SESSION_Release_Simulator]\r
+[GENERAL_DATA_SESSION_Simulator]\r
+[GENERAL_DATA_CONFIGURATION_SESSION_Debug_Release session]\r
+[END]\r
--- /dev/null
+[HIMDBVersion]\r
+2.0\r
+[DATABASE_VERSION]\r
+"2.0" \r
+[SESSION_DETAILS]\r
+"" \r
+[INFORMATION]\r
+"" \r
+[GENERAL_DATA]\r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ColWidth1" "200" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewAInstanceKey0" "{WK_00000001_MEMORY}" \r
+"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_BREAK_BREAK_SEQUENCE_COUNT" "0" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MEMORY_MODE" "0" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONTROL_REGS_CREG1" "0x00FFFF32,1,0x00000000" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_RESOURCE_MEMORY_RESOURCE_COUNT" "1" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_BREAK_BREAK_REGISTER_COUNT" "0" \r
+"{2BA6A3EE-6488-11D5-80D4-00C04F68EAD7}LabelCtrlViews" "0" \r
+"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd2ScrollVert" "0" \r
+"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_COLOR" "0,0,0,0" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ScrollHorz" "0" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ColWidth2" "200" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWndInstanceKey0" "{WK_00000001_WATCH}" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWnd0ECX_REGISTER_DISPLAYED" "1,1,1,1,1,1,1,1,1,1,1" \r
+"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_MAP_PRG_WIDTH" "24" \r
+"{313F4FC1-6566-11D5-8BBE-0004E2013C71}TclTkCtrlLogFileName" "" \r
+"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_0" "0000000000000000" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONFIG_DIVISOR" "DISABLE" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONTROL_REGS_CREG2" "0x00FFFD95,1,0x00000000" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryCtrlViews" "0" \r
+"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd2ColWidth0" "250" \r
+"{633553C0-6FE9-11D5-B7CE-00E029352378}ProfileCtrlChartMultiOpen" "0" \r
+"{7FA2E460-7EC0-11D5-8EB6-00004CC34E9D}SimIOWndInstanceKey0" "{WK_00000001_SIMIO}RTOSDemoSimulator" \r
+"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_BREAK_BREAK_ACCESS_COUNT" "0" \r
+"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_1" "0000000011111111" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_SYSTEM_CALL_SYSTEM_CALL_FLAG" "OFF" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_BREAK_BREAK_DATA_COUNT" "0" \r
+"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd1ScrollHorz" "0" \r
+"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd2ColWidth1" "250" \r
+"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_VIEW" "0,0,0,0,0,0" \r
+"{8A898260-6F1D-11D5-8EB6-00004CC34E9D}ECX_WAVE" "00000000,00000000,0,0" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ECX_WATCH" "" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWnd0ColWidth0" "100" \r
+"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_BREAK_BREAK_REGISTER_COUNT" "0" \r
+"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_MAP_MAP0" "0x00000000,0x0005FFFF,16, 2,ROM" \r
+"{287A8023-99B5-49E1-A54E-4DDCA43D7959}MapCtrlViews" "0" \r
+"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_2" "0000000000000000" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_EXEC_STEP_RATE" "40000" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_EXEC_MULT_VAL" "00000000" \r
+"{EEDC9300-6FBE-11D5-8613-00A024591A38}LocalsCtrlViews" "0" \r
+"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0ScrollVert" "0" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ColWidth0" "200" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWnd0ColWidth1" "1600" \r
+"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_MAP_MAP1" "0x00FF7C00,0x00FFFBFF,16, 2,RAM" \r
+"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_3" "0000000033333333" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONTROL_REGS_SYSCR_ADR" "0x00FFFF39" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ColWidth1" "200" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ScrollVert" "0" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWndViewB0ScrollHorz" "0" \r
+"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_MAP_MEMORY_MODE" "0" \r
+"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_4" "0000000044444444" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_EXEC_EXEC_MODE" "STOP" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_BUS_WIDTH" "24" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_ADDRESS_MAP" "24" \r
+"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusCtrlViews" "1" \r
+"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_COMB_ADDRESS" ",,,," \r
+"{48FF5DA0-6FFA-11D5-B7CE-00E029352378}CoverageFileName" "0" \r
+"{85AC95E0-0CE6-11D6-8EB6-00004CC34E9D}TriggerCtrlViews" "0" \r
+"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_MAP_MAP2" "0x00FFFE50,0x00FFFF07,16, 2,I/O" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ColWidth2" "200" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ScrollHorz" "0" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewBInstanceKey0" "{WK_00000001_MEMORY}ViewB" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryCtrlViews0" "16743424" \r
+"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_BREAK_BREAK_DATA_COUNT" "0" \r
+"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlViews" "0" \r
+"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_5" "0000000055555555" \r
+"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_10" "000000000000007F" \r
+"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd1ScrollVert" "0" \r
+"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_COMB_PALETTE" ",,,," \r
+"{7FA2E460-7EC0-11D5-8EB6-00004CC34E9D}SimIOCtrlViews" "1" \r
+"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_MAP_MAP3" "0x00FFFF28,0x00FFFFFF,16, 2,I/O" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ScrollHorz" "0" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0Exp0" "0" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryCtrlOneLineBytesCount0" "16" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWndViewB0ColWidth0" "100" \r
+"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_MAP_MEMORY_MAP_COUNT" "4" \r
+"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_6" "0000000000FF820C" \r
+"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_11" "0000000000000000" \r
+"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd0ScrollHorz" "0" \r
+"{5F75FDA0-6FF0-11D5-B7CE-00E029352378}PACtrlViews" "0" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ColWidth0" "200" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ECX_WATCH" "" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWndViewB0ColWidth1" "1600" \r
+"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_SESSION_IS_SAVED" "YES" \r
+"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_MAP_BUS_WIDTH" "24" \r
+"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_7" "0000000000FF8200" \r
+"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_12" "00000000FFFFFF00" \r
+"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOCtrlViews" "1" \r
+"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_BUFFER" "00000000,00000000,0,0" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ColWidth1" "200" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryCtrlProperty0" "5" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWndViewB0ScrollVert" "0" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWndViewB0ECX_REGISTER_DISPLAYED" "1,1,1,1,1,1,1,1,1,1,1" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWndViewB0ECX_REGISTER_COUNT" "11" \r
+"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_RESOURCE_MEMORY_RESOURCE_COUNT" "4" \r
+"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_8" "0000000000004E9C" \r
+"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_13" "0000000000000000" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONFIG_FETCH_MODE" "32" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_RESOURCE_MEMRES0" "0x00000000,0x0005FFFF,14" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_TRACE_TRACE_ACQUISITION" "0,1024,0,0" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_SESSION_IS_SAVED" "YES" \r
+"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd0ColWidth0" "250" \r
+"{D595F9C0-EF22-11D5-B7DB-0000E10B3DA9}EventCtrlViews" "0" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchCtrlViews" "0" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ColWidth2" "200" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ScrollVert" "0" \r
+"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_TRACE_TRACE_ACQUISITION" "0,1024,0,0" \r
+"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_RESOURCE_MEMRES0" "0x00000000,0x00005FFF,14" \r
+"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_SYSTEM_CALL_SYSTEM_CALL_FLAG" "OFF" \r
+"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_9" "0000000000000080" \r
+"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_14" "0000000000000000" \r
+"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd0ColWidth1" "250" \r
+"{8A898260-6F1D-11D5-8EB6-00004CC34E9D}ECX_WAVE_COMB_ADDRESS" ",,,," \r
+"{5F75FDA0-6FF0-11D5-B7CE-00E029352378}PACtrlPAState" "0" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ScrollVert" "0" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ColWidth0" "200" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryCtrlViews30" "16776191" \r
+"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_RESOURCE_MEMRES1" "0x00FF7C00,0x00FFFBFF,15" \r
+"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_CONTROL_REGS_CREG_CNT" "0" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONFIG_ENDIAN" "BIG" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONFIG_MULTIPLIER" "DISABLE" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_BREAK_PC_BREAK_COUNT" "0" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_BREAK_BREAK_CYCLE_COUNT" "0" \r
+"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd0ScrollVert" "0" \r
+"{30F726A1-F13D-4E21-9A4F-FD7FF70EDFDA}TraceCtrlViews" "0" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ScrollHorz" "0" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ColWidth1" "200" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryCtrlViews20" "16743424" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWnd0ScrollHorz" "0" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWnd0ECX_REGISTER_COUNT" "11" \r
+"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_BREAK_BREAK_CYCLE_COUNT" "0" \r
+"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlBatchFileName" "" \r
+"{313F4FC0-6566-11D5-8BBE-0004E2013C71}DisassemblyCtrlViews" "0" \r
+"{8A898260-6F1D-11D5-8EB6-00004CC34E9D}WaveformCtrlViews" "0" \r
+"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_RESOURCE_MEMRES2" "0x00FFFE50,0x00FFFF07,7" \r
+"{7943C44E-7D44-422A-9140-4CF55C88F7D3}DifferenceCtrlViews" "0" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ECX_WATCH" "" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ColWidth2" "200" \r
+"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_EXEC_STEP_RATE" "40000" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterCtrlViews" "0" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONFIG_ROUND" "RM_NEAR" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MAP0" "0x00000000,0x0005FFFF, 8, 3,ROM" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONTROL_REGS_CREG_CNT" "3" \r
+"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd1ColWidth0" "250" \r
+"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd2ScrollHorz" "0" \r
+"{633553C0-6FE9-11D5-B7CE-00E029352378}ProfileCtrlEnable" "0" \r
+"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_RESOURCE_MEMRES3" "0x00FFFF28,0x00FFFFFF,7" \r
+"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0ColWidth0" "200" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryCtrlDataCount0" "4" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWndViewBInstanceKey0" "{WK_00000001_REGISTER}ViewB" \r
+"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_BREAK_PC_BREAK_COUNT" "0" \r
+"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_SYSTEM_CALL_SYSTEM_CALL_ADDRESS" "0x00000000" \r
+"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_CONFIG_ENDIAN" "BIG" \r
+"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_COUNT" "11" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MAP1" "0x00FF7C00,0x00FFFBFF, 8, 3,RAM" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_BREAK_BREAK_SEQUENCE_COUNT" "0" \r
+"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd1ColWidth1" "250" \r
+"{8A898260-6F1D-11D5-8EB6-00004CC34E9D}ECX_WAVE_COMB_BUFFER" ",,,," \r
+"{48FF5DA0-6FFA-11D5-B7CE-00E029352378}CoverageCtrlViews" "0" \r
+"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0ColWidth1" "100" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH" "pxCreatedTask," \r
+"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_EXEC_EXEC_MODE" "STOP" \r
+"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlLogFileName" "" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_PRG_WIDTH" "24" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MEMORY_MAP_COUNT" "4" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MAP2" "0x00FFFE50,0x00FFFF07, 8, 2,RAM" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_BREAK_BREAK_ACCESS_COUNT" "0" \r
+"{633553C0-6FE9-11D5-B7CE-00E029352378}ProfileCtrlViews" "0" \r
+"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0ColWidth2" "100" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ScrollVert" "0" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ColWidth0" "200" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWndInstanceKey0" "{WK_00000001_REGISTER}" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWnd0ScrollVert" "0" \r
+"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_CONFIG_ROUND" "RM_NEAR" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_SYSTEM_CALL_SYSTEM_CALL_ADDRESS" "0x00000000" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MAP3" "0x00FFFF28,0x00FFFFFF, 8, 2,RAM" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONTROL_REGS_CREG0" "0x00FFFF39,2,0x00000101" \r
+"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ImageCtrlViews" "0" \r
+"{48FF5DA0-6FFA-11D5-B7CE-00E029352378}CoverageCtrlViewsFromDiffFile" "0" \r
+"{EEDC9301-6FBE-11D5-8613-00A024591A38}StackTraceCtrlViews" "0" \r
+"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0ColWidth3" "100" \r
+"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0ScrollHorz" "0" \r
+[LANGUAGE]\r
+"English" \r
+[CONFIG_INFO_VD1]\r
+1 \r
+[CONFIG_INFO_VD2]\r
+0 \r
+[CONFIG_INFO_VD3]\r
+0 \r
+[CONFIG_INFO_VD4]\r
+0 \r
+[WINDOW_POSITION_STATE_DATA_VD1]\r
+"{WK_TB00000009_VERSIONCONTROL}" "TOOLBAR 0" 59419 0 4 "0.00" 0 0 0 0 0 17 0 "" "0.0" \r
+"{WK_TB00000004_TEMPLATES}" "TOOLBAR 0" 59419 0 8 "0.00" 0 0 0 0 0 18 0 "" "0.0" \r
+"TCL Toolkit" "WINDOW" 59422 1 0 "-1.000000" -1 -1000 -1000 -1 -1 17 0 "" "-1" \r
+"{WK_TB00000002_EDITOR}" "TOOLBAR 0" 59419 0 2 "0.00" 0 0 0 0 0 18 0 "" "0.0" \r
+"{WK_TB00000012_MAP}" "TOOLBAR 0" 59419 0 3 "0.00" 0 0 0 0 0 18 0 "" "0.0" \r
+"{WK_TB00000017_FDT}" "TOOLBAR 0" 59419 0 1 "0.00" 0 0 0 0 0 18 0 "" "0.0" \r
+"{WK_00000001_MAP}RTOSDemoRelease session" "WINDOW" 59421 -1 -1 "-1.000000" -1 -1000 -1000 -1 -1 18 0 "" "-1" \r
+"{WK_TB00000003_BOOKMARKS}" "TOOLBAR 0" 59419 1 0 "0.00" 0 0 0 0 0 18 0 "" "0.0" \r
+"{WK_TB00000018_DEFAULTWINDOW}" "TOOLBAR 0" 59419 1 1 "0.00" 0 0 0 0 0 17 0 "" "0.0" \r
+"{WK_TB00000008_DEBUGRUN}" "TOOLBAR 0" 59419 0 5 "0.00" 0 0 0 0 0 17 0 "" "0.0" \r
+"{WK_TB00000005_SEARCH}" "TOOLBAR 0" 59419 0 7 "0.00" 0 0 0 0 0 18 0 "" "0.0" \r
+"{WK_00000001_OUTPUT}" "WINDOW" 59422 0 0 "1.00" 180 0 0 350 200 18 0 "" "0.0" \r
+"{WK_00000002_WORKSPACE}" "WINDOW" 59420 0 0 "1.00" 280 0 0 350 200 18 0 "" "0.0" \r
+"{WK_TB00000001_STANDARD}" "TOOLBAR 0" 59419 0 0 "0.00" 0 0 0 0 0 18 0 "" "0.0" \r
+"{WK_TB00000007_DEBUG}" "TOOLBAR 0" 59419 0 6 "0.00" 0 0 0 0 0 17 0 "" "0.0" \r
+[WINDOW_POSITION_STATE_DATA_VD2]\r
+[WINDOW_POSITION_STATE_DATA_VD3]\r
+[WINDOW_POSITION_STATE_DATA_VD4]\r
+[WINDOW_Z_ORDER]\r
+"C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\partest\partest.c" \r
+"C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\serial\serial.c" \r
+"c:\e\Dev\FreeRTOS\Source\queue.c" \r
+"C:\E\Dev\FreeRTOS\Source\portable\GCC\H8S2329\portmacro.h" \r
+"c:\e\Dev\FreeRTOS\Source\portable\GCC\H8S2329\port.c" \r
+"C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\main.c" \r
+"C:\E\Dev\FreeRTOS\Source\include\portable.h" \r
+"c:\e\Dev\FreeRTOS\Demo\Common\Minimal\BlockQ.c" \r
+[TARGET_NAME]\r
+"" \r
+[DEBUGGER_OPTIONS]\r
+"" \r
+[DOWNLOAD_MODULES]\r
+[CONNECT_ON_GO]\r
+"TRUE" \r
+[DOWNLOAD_MODULES_AFTER_BUILD]\r
+"TRUE" \r
+[REMOVE_BREAKPOINTS_ON_DOWNLOAD]\r
+"FALSE" \r
+[COMMAND_FILES]\r
+[DEFAULT_DEBUG_FORMAT]\r
+"" \r
+[FLASH_DETAILS]\r
+"2212.000000" 1 -127 "B" 0 "COM1" 115200 1 "H8S/2329BF" 1 0 0 0 1 0 0 "D:\DevTools\Hitachi\FDT2.2\Kernels\ProtB\2329\hitachi\1_1_00\" "" "" "" "" \r
+[BREAKPOINTS]\r
+[END]\r
--- /dev/null
+[HEWGNUBARNEYMCGREW]\r
+SELECTEDCPU=H8/S2000\r
+SELECTEDMODE=Advanced\r
+INT32=N\r
+SELECTEDRENESAS=N\r
+SELECTEDENDIAN=Big endian\r
--- /dev/null
+[HIMDBVersion]\r
+2.0\r
+[DATABASE_VERSION]\r
+"2.0" \r
+[SESSION_DETAILS]\r
+"" \r
+[INFORMATION]\r
+"" \r
+[GENERAL_DATA]\r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ColWidth1" "200" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewAInstanceKey0" "{WK_00000001_MEMORY}RTOSDemoSimulator" \r
+"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd2ScrollVert" "0" \r
+"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_COLOR" "0,0,0,0" \r
+"{2BA6A3EE-6488-11D5-80D4-00C04F68EAD7}LabelCtrlViews" "0" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_BREAK_BREAK_REGISTER_COUNT" "0" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_RESOURCE_MEMORY_RESOURCE_COUNT" "1" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONTROL_REGS_CREG1" "0x00FFFF32,1,0x00000000" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MAP4" "0x00E00000,0x00EFFFFF, 8, 3,EXT" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MEMORY_MODE" "0" \r
+"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_BREAK_BREAK_SEQUENCE_COUNT" "0" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ScrollHorz" "0" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ColWidth2" "200" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWndInstanceKey0" "{WK_00000001_WATCH}RTOSDemoSimulator" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWnd0ECX_REGISTER_DISPLAYED" "1,1,1,1,1,1,1,1,1,1,1" \r
+"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd2ColWidth0" "250" \r
+"{633553C0-6FE9-11D5-B7CE-00E029352378}ProfileCtrlChartMultiOpen" "0" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryCtrlViews" "0" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONTROL_REGS_CREG2" "0x00FFFD95,1,0x00000000" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MAP5" "0x00F00000,0x00FDBFFF, 8, 3,EXT" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONFIG_DIVISOR" "DISABLE" \r
+"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_0" "0000000000000000" \r
+"{313F4FC1-6566-11D5-8BBE-0004E2013C71}TclTkCtrlLogFileName" "" \r
+"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_MAP_PRG_WIDTH" "24" \r
+"{7FA2E460-7EC0-11D5-8EB6-00004CC34E9D}SimIOWndInstanceKey0" "{WK_00000001_SIMIO}RTOSDemoSimulator" \r
+"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd2ColWidth1" "250" \r
+"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd1ScrollHorz" "0" \r
+"{8A898260-6F1D-11D5-8EB6-00004CC34E9D}ECX_WAVE" "00000000,00000000,0,0" \r
+"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_VIEW" "0,0,0,0,0,0" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_BREAK_BREAK_DATA_COUNT" "0" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MAP6" "0x00FDC000,0x00FEBFFF,16, 3,RAM" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_SYSTEM_CALL_SYSTEM_CALL_FLAG" "OFF" \r
+"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_1" "0000000011111111" \r
+"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_BREAK_BREAK_ACCESS_COUNT" "0" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ECX_WATCH" "" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWnd0ColWidth0" "100" \r
+"{EEDC9300-6FBE-11D5-8613-00A024591A38}LocalsCtrlViews" "0" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MAP7" "0x00FEC000,0x00FFBFFF,16, 1,RAM" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_EXEC_MULT_VAL" "00000000" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_EXEC_STEP_RATE" "40000" \r
+"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_2" "0000000000000001" \r
+"{287A8023-99B5-49E1-A54E-4DDCA43D7959}MapCtrlViews" "0" \r
+"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_MAP_MAP0" "0x00000000,0x0005FFFF,16, 2,ROM" \r
+"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_BREAK_BREAK_REGISTER_COUNT" "0" \r
+"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0ScrollVert" "0" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ColWidth0" "200" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWnd0ColWidth1" "1600" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONTROL_REGS_SYSCR_ADR" "0x00FFFF39" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MAP8" "0x00FFC000,0x00FFDFFF, 8, 3,EXT" \r
+"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_3" "0000000033333333" \r
+"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_MAP_MAP1" "0x00FF7C00,0x00FFFBFF,16, 2,RAM" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ColWidth1" "200" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ScrollVert" "0" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWndViewB0ScrollHorz" "0" \r
+"{85AC95E0-0CE6-11D6-8EB6-00004CC34E9D}TriggerCtrlViews" "0" \r
+"{48FF5DA0-6FFA-11D5-B7CE-00E029352378}CoverageFileName" "0" \r
+"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_COMB_ADDRESS" ",,,," \r
+"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusCtrlViews" "1" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_ADDRESS_MAP" "24" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MAP9" "0x00FFE000,0x00FFE9FF, 8, 3,EXT" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_BUS_WIDTH" "24" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_EXEC_EXEC_MODE" "STOP" \r
+"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_4" "0000000044444444" \r
+"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_MAP_MEMORY_MODE" "0" \r
+"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_MAP_MAP2" "0x00FFFE50,0x00FFFF07,16, 2,I/O" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ColWidth2" "200" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ScrollHorz" "0" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewBInstanceKey0" "{WK_00000001_MEMORY}RTOSDemoSimulatorViewB" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryCtrlViews0" "16756480" \r
+"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd1ScrollVert" "0" \r
+"{7FA2E460-7EC0-11D5-8EB6-00004CC34E9D}SimIOCtrlViews" "1" \r
+"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_COMB_PALETTE" ",,,," \r
+"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_10" "000000000000007F" \r
+"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_5" "0000000055555555" \r
+"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlViews" "0" \r
+"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_BREAK_BREAK_DATA_COUNT" "0" \r
+"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_MAP_MAP3" "0x00FFFF28,0x00FFFFFF,16, 2,I/O" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ScrollHorz" "0" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0Exp0" "0" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryCtrlOneLineBytesCount0" "16" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWndViewB0ColWidth0" "100" \r
+"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd0ScrollHorz" "0" \r
+"{5F75FDA0-6FF0-11D5-B7CE-00E029352378}PACtrlViews" "0" \r
+"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_11" "0000000000000000" \r
+"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_6" "0000000000FF81E4" \r
+"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_MAP_MEMORY_MAP_COUNT" "4" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ColWidth0" "200" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ECX_WATCH" "" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWndViewB0ColWidth1" "1600" \r
+"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_BUFFER" "00000000,00000000,0,0" \r
+"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOCtrlViews" "1" \r
+"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_12" "00000000FFFFFF00" \r
+"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_7" "0000000000FF81E4" \r
+"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_MAP_BUS_WIDTH" "24" \r
+"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_SESSION_IS_SAVED" "YES" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ColWidth1" "200" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryCtrlProperty0" "5" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWndViewB0ScrollVert" "0" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWndViewB0ECX_REGISTER_DISPLAYED" "1,1,1,1,1,1,1,1,1,1,1" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWndViewB0ECX_REGISTER_COUNT" "11" \r
+"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd0ColWidth0" "250" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_RESOURCE_MEMRES0" "0x00000000,0x0005FFFF,14" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchCtrlViews" "0" \r
+"{D595F9C0-EF22-11D5-B7DB-0000E10B3DA9}EventCtrlViews" "0" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_SESSION_IS_SAVED" "YES" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_TRACE_TRACE_ACQUISITION" "0,1024,0,0" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONFIG_FETCH_MODE" "32" \r
+"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_13" "0000000000000000" \r
+"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_8" "0000000000003F48" \r
+"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_RESOURCE_MEMORY_RESOURCE_COUNT" "4" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ColWidth2" "200" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ScrollVert" "0" \r
+"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd0ColWidth1" "250" \r
+"{5F75FDA0-6FF0-11D5-B7CE-00E029352378}PACtrlPAState" "0" \r
+"{8A898260-6F1D-11D5-8EB6-00004CC34E9D}ECX_WAVE_COMB_ADDRESS" ",,,," \r
+"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_14" "0000000000000000" \r
+"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_9" "0000000000000021" \r
+"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_SYSTEM_CALL_SYSTEM_CALL_FLAG" "OFF" \r
+"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_TRACE_TRACE_ACQUISITION" "0,1024,0,0" \r
+"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_RESOURCE_MEMRES0" "0x00000000,0x00005FFF,14" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ScrollVert" "0" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ColWidth0" "200" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryCtrlViews30" "16773120" \r
+"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd0ScrollVert" "0" \r
+"{30F726A1-F13D-4E21-9A4F-FD7FF70EDFDA}TraceCtrlViews" "0" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_BREAK_BREAK_CYCLE_COUNT" "0" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_BREAK_PC_BREAK_COUNT" "0" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONFIG_MULTIPLIER" "DISABLE" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONFIG_ENDIAN" "BIG" \r
+"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_CONTROL_REGS_CREG_CNT" "0" \r
+"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_RESOURCE_MEMRES1" "0x00FF7C00,0x00FFFBFF,15" \r
+"{7943C44E-7D44-422A-9140-4CF55C88F7D3}DifferenceCtrlViews" "0" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ScrollHorz" "0" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ColWidth1" "200" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryCtrlViews20" "16756480" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWnd0ScrollHorz" "0" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWnd0ECX_REGISTER_COUNT" "11" \r
+"{8A898260-6F1D-11D5-8EB6-00004CC34E9D}WaveformCtrlViews" "0" \r
+"{313F4FC0-6566-11D5-8BBE-0004E2013C71}DisassemblyCtrlViews" "0" \r
+"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlBatchFileName" "" \r
+"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_BREAK_BREAK_CYCLE_COUNT" "0" \r
+"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_RESOURCE_MEMRES2" "0x00FFFE50,0x00FFFF07,7" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ECX_WATCH" "" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ColWidth2" "200" \r
+"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd2ScrollHorz" "0" \r
+"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd1ColWidth0" "250" \r
+"{633553C0-6FE9-11D5-B7CE-00E029352378}ProfileCtrlEnable" "0" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONTROL_REGS_CREG_CNT" "3" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MAP10" "0x00FFEA00,0x00FFFEFF, 8, 2,I/O" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MAP0" "0x00000000,0x0005FFFF, 8, 3,ROM" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONFIG_ROUND" "RM_NEAR" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterCtrlViews" "0" \r
+"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_EXEC_STEP_RATE" "40000" \r
+"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_RESOURCE_MEMRES3" "0x00FFFF28,0x00FFFFFF,7" \r
+"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0ColWidth0" "200" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryCtrlDataCount0" "4" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWndViewBInstanceKey0" "{WK_00000001_REGISTER}RTOSDemoSimulatorViewB" \r
+"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd1ColWidth1" "250" \r
+"{48FF5DA0-6FFA-11D5-B7CE-00E029352378}CoverageCtrlViews" "0" \r
+"{8A898260-6F1D-11D5-8EB6-00004CC34E9D}ECX_WAVE_COMB_BUFFER" ",,,," \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_BREAK_BREAK_SEQUENCE_COUNT" "0" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MAP11" "0x00FFFF00,0x00FFFF1F, 8, 3,EXT" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MAP1" "0x00FF7C00,0x00FFFBFF, 8, 3,RAM" \r
+"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_COUNT" "11" \r
+"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_CONFIG_ENDIAN" "BIG" \r
+"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_SYSTEM_CALL_SYSTEM_CALL_ADDRESS" "0x00000000" \r
+"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_BREAK_PC_BREAK_COUNT" "0" \r
+"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0ColWidth1" "100" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH" "pxTCB," \r
+"{633553C0-6FE9-11D5-B7CE-00E029352378}ProfileCtrlViews" "0" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_BREAK_BREAK_ACCESS_COUNT" "0" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MAP12" "0x00FFFF20,0x00FFFFFF, 8, 2,I/O" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MAP2" "0x00FFFE50,0x00FFFF07, 8, 2,RAM" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MEMORY_MAP_COUNT" "4" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_PRG_WIDTH" "24" \r
+"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlLogFileName" "" \r
+"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_EXEC_EXEC_MODE" "STOP" \r
+"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0ColWidth2" "100" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ScrollVert" "0" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ColWidth0" "200" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWndInstanceKey0" "{WK_00000001_REGISTER}RTOSDemoSimulator" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWnd0ScrollVert" "0" \r
+"{EEDC9301-6FBE-11D5-8613-00A024591A38}StackTraceCtrlViews" "0" \r
+"{48FF5DA0-6FFA-11D5-B7CE-00E029352378}CoverageCtrlViewsFromDiffFile" "0" \r
+"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ImageCtrlViews" "0" \r
+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONTROL_REGS_CREG0" "0x00FFFF39,2,0x00000101" \r
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+"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_CONFIG_ROUND" "RM_NEAR" \r
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+"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0ScrollHorz" "0" \r
+[LANGUAGE]\r
+"English" \r
+[CONFIG_INFO_VD1]\r
+0 \r
+[CONFIG_INFO_VD2]\r
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+[CONFIG_INFO_VD3]\r
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+[WINDOW_POSITION_STATE_DATA_VD1]\r
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+"H8S/2000A Simulator" \r
+[DEBUGGER_OPTIONS]\r
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+[CONNECT_ON_GO]\r
+"TRUE" \r
+[DOWNLOAD_MODULES_AFTER_BUILD]\r
+"TRUE" \r
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+[BREAKPOINTS]\r
+[END]\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+ * Creates all the demo application tasks, then starts the scheduler. The WEB\r
+ * documentation provides more details of the demo application tasks.\r
+ * \r
+ * Main.c also creates a task called "Check". This only executes every three \r
+ * seconds but has the highest priority so is guaranteed to get processor time. \r
+ * Its main function is to check that all the other tasks are still operational.\r
+ * Each task (other than the "flash" tasks) maintains a unique count that is \r
+ * incremented each time the task successfully completes its function. Should \r
+ * any error occur within such a task the count is permanently halted. The \r
+ * check task inspects the count of each task to ensure it has changed since\r
+ * the last time the check task executed. If all the count variables have \r
+ * changed all the tasks are still executing error free, and the check task\r
+ * toggles the onboard LED. Should any task contain an error at any time \r
+ * the LED toggle rate will change from 3 seconds to 500ms.\r
+ *\r
+ * To check the operation of the memory allocator the check task also \r
+ * dynamically creates a task before delaying, and deletes it again when it \r
+ * wakes. If memory cannot be allocated for the new task the call to xTaskCreate\r
+ * will fail and an error is signalled. The dynamically created task itself\r
+ * allocates and frees memory just to give the allocator a bit more exercise.\r
+ *\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdlib.h>\r
+#include <string.h>\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo application file headers. */\r
+#include "flash.h"\r
+#include "integer.h"\r
+#include "PollQ.h"\r
+#include "comtest2.h"\r
+#include "semtest.h"\r
+#include "flop.h"\r
+#include "dynamic.h"\r
+#include "BlockQ.h"\r
+#include "serial.h"\r
+#include "partest.h"\r
+\r
+/* Priority definitions for most of the tasks in the demo application. Some\r
+tasks just use the idle priority. */\r
+#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+\r
+/* Baud rate used by the serial port tasks (ComTest tasks). */\r
+#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 115200 )\r
+\r
+/* LED used by the serial port tasks. This is toggled on each character Tx,\r
+and mainCOM_TEST_LED + 1 is toggles on each character Rx. */\r
+#define mainCOM_TEST_LED ( 3 )\r
+\r
+/* LED that is toggled by the check task. The check task periodically checks\r
+that all the other tasks are operating without error. If no errors are found\r
+the LED is toggled with mainCHECK_PERIOD frequency. If an error is found \r
+the the toggle rate increases to mainERROR_CHECK_PERIOD. */\r
+#define mainCHECK_TASK_LED ( 5 )\r
+#define mainCHECK_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS )\r
+#define mainERROR_CHECK_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS )\r
+\r
+/* Constants used by the vMemCheckTask() task. */\r
+#define mainCOUNT_INITIAL_VALUE ( ( unsigned portLONG ) 0 )\r
+#define mainNO_TASK ( 0 )\r
+\r
+/* The size of the memory blocks allocated by the vMemCheckTask() task. */\r
+#define mainMEM_CHECK_SIZE_1 ( ( size_t ) 51 )\r
+#define mainMEM_CHECK_SIZE_2 ( ( size_t ) 52 )\r
+#define mainMEM_CHECK_SIZE_3 ( ( size_t ) 151 )\r
+\r
+/*\r
+ * The 'Check' task.\r
+ */\r
+static void vErrorChecks( void *pvParameters );\r
+\r
+/*\r
+ * Checks the unique counts of other tasks to ensure they are still operational.\r
+ */\r
+static portLONG prvCheckOtherTasksAreStillRunning( unsigned portLONG ulMemCheckTaskCount );\r
+\r
+/*\r
+ * Dynamically created and deleted during each cycle of the vErrorChecks()\r
+ * task. This is done to check the operation of the memory allocator.\r
+ * See the top of vErrorChecks for more details.\r
+ */\r
+static void vMemCheckTask( void *pvParameters );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Start all the tasks then start the scheduler.\r
+ */\r
+int main( void )\r
+{\r
+ /* Setup the LED's for output. */\r
+ vParTestInitialise();\r
+\r
+ /* Start the various standard demo application tasks. */\r
+ vStartIntegerMathTasks( tskIDLE_PRIORITY );\r
+ vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED );\r
+ vStartLEDFlashTasks( mainLED_TASK_PRIORITY );\r
+ vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
+ vStartMathTasks( tskIDLE_PRIORITY );\r
+ vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
+ vStartDynamicPriorityTasks();\r
+ vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
+\r
+ /* Start the 'Check' task. */\r
+ xTaskCreate( vErrorChecks, ( signed portCHAR * )"Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
+\r
+ /* In this port, to use preemptive scheduler define configUSE_PREEMPTION \r
+ as 1 in portmacro.h. To use the cooperative scheduler define \r
+ configUSE_PREEMPTION as 0. */\r
+ vTaskStartScheduler();\r
+\r
+ /* Should never get here! */\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Cycle for ever, delaying then checking all the other tasks are still\r
+ * operating without error. If an error is detected then the delay period\r
+ * is decreased from mainCHECK_PERIOD to mainERROR_CHECK_PERIOD so\r
+ * the on board LED flash rate will increase. \r
+ *\r
+ * In addition to the standard tests the memory allocator is tested through\r
+ * the dynamic creation and deletion of a task each cycle. Each time the \r
+ * task is created memory must be allocated for its stack. When the task is\r
+ * deleted this memory is returned to the heap. If the task cannot be created \r
+ * then it is likely that the memory allocation failed. In addition the\r
+ * dynamically created task allocates and frees memory while it runs. \r
+ */\r
+static void vErrorChecks( void *pvParameters )\r
+{\r
+portTickType xDelayPeriod = mainCHECK_PERIOD;\r
+volatile unsigned portLONG ulMemCheckTaskRunningCount;\r
+xTaskHandle xCreatedTask;\r
+portTickType xLastWakeTime;\r
+\r
+ /* Initialise xLastWakeTime to ensure the first call to vTaskDelayUntil()\r
+ functions correctly. */\r
+ xLastWakeTime = xTaskGetTickCount();\r
+\r
+ for( ;; )\r
+ {\r
+ /* Set ulMemCheckTaskRunningCount to a known value so we can check\r
+ later that it has changed. */\r
+ ulMemCheckTaskRunningCount = mainCOUNT_INITIAL_VALUE;\r
+\r
+ /* Dynamically create a task - passing ulMemCheckTaskRunningCount as a \r
+ parameter. */ \r
+ xCreatedTask = mainNO_TASK;\r
+ if( xTaskCreate( vMemCheckTask, ( signed portCHAR * ) "MEM_CHECK", configMINIMAL_STACK_SIZE, ( void * ) &ulMemCheckTaskRunningCount, tskIDLE_PRIORITY, &xCreatedTask ) != pdPASS )\r
+ {\r
+ /* Could not create the task - we have probably run out of heap. */\r
+ xDelayPeriod = mainERROR_CHECK_PERIOD;\r
+ }\r
+\r
+\r
+ /* Delay until it is time to execute again. The delay period is \r
+ shorter following an error. */\r
+ vTaskDelayUntil( &xLastWakeTime, xDelayPeriod );\r
+\r
+ \r
+ /* Delete the dynamically created task. */\r
+ if( xCreatedTask != mainNO_TASK )\r
+ {\r
+ vTaskDelete( xCreatedTask );\r
+ }\r
+\r
+ /* Check all the standard demo application tasks are executing without \r
+ error. ulMemCheckTaskRunningCount is checked to ensure it was\r
+ modified by the task just deleted. */\r
+ if( prvCheckOtherTasksAreStillRunning( ulMemCheckTaskRunningCount ) != pdPASS )\r
+ {\r
+ /* An error has been detected in one of the tasks - flash faster. */\r
+ xDelayPeriod = mainERROR_CHECK_PERIOD;\r
+ }\r
+\r
+ vParTestToggleLED( mainCHECK_TASK_LED );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Check each set of tasks in turn to see if they have experienced any\r
+ * error conditions. \r
+ */\r
+static portLONG prvCheckOtherTasksAreStillRunning( unsigned portLONG ulMemCheckTaskCount )\r
+{\r
+portLONG lNoErrorsDiscovered = ( portLONG ) pdTRUE;\r
+\r
+ if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ lNoErrorsDiscovered = pdFALSE;\r
+ }\r
+\r
+ if( xAreComTestTasksStillRunning() != pdTRUE )\r
+ {\r
+ lNoErrorsDiscovered = pdFALSE;\r
+ }\r
+\r
+ if( xArePollingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ lNoErrorsDiscovered = pdFALSE;\r
+ }\r
+\r
+ if( xAreMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ lNoErrorsDiscovered = pdFALSE;\r
+ }\r
+\r
+ if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ lNoErrorsDiscovered = pdFALSE;\r
+ }\r
+\r
+ if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )\r
+ {\r
+ lNoErrorsDiscovered = pdFALSE;\r
+ }\r
+\r
+ if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ lNoErrorsDiscovered = pdFALSE;\r
+ }\r
+\r
+ if( ulMemCheckTaskCount == mainCOUNT_INITIAL_VALUE )\r
+ {\r
+ /* The vMemCheckTask task did not increment the counter - it must\r
+ have failed. */\r
+ lNoErrorsDiscovered = pdFALSE;\r
+ }\r
+\r
+ return lNoErrorsDiscovered;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vMemCheckTask( void *pvParameters )\r
+{\r
+unsigned portLONG *pulMemCheckTaskRunningCounter;\r
+void *pvMem1, *pvMem2, *pvMem3;\r
+static portLONG lErrorOccurred = pdFALSE;\r
+\r
+ /* This task is dynamically created then deleted during each cycle of the\r
+ vErrorChecks task to check the operation of the memory allocator. Each time\r
+ the task is created memory is allocated for the stack and TCB. Each time\r
+ the task is deleted this memory is returned to the heap. This task itself\r
+ exercises the allocator by allocating and freeing blocks. \r
+ \r
+ The task executes at the idle priority so does not require a delay. \r
+ \r
+ pulMemCheckTaskRunningCounter is incremented each cycle to indicate to the\r
+ vErrorChecks() task that this task is still executing without error. */\r
+\r
+ pulMemCheckTaskRunningCounter = ( unsigned portLONG * ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ if( lErrorOccurred == pdFALSE )\r
+ {\r
+ /* We have never seen an error so increment the counter. */\r
+ ( *pulMemCheckTaskRunningCounter )++;\r
+ }\r
+ else\r
+ {\r
+ /* Reset the count so an error is detected by the \r
+ prvCheckOtherTasksAreStillRunning() function. */\r
+ *pulMemCheckTaskRunningCounter = mainCOUNT_INITIAL_VALUE;\r
+ }\r
+\r
+ /* Allocate some memory - just to give the allocator some extra \r
+ exercise. This has to be in a critical section to ensure the\r
+ task does not get deleted while it has memory allocated. */\r
+ vTaskSuspendAll();\r
+ {\r
+ pvMem1 = pvPortMalloc( mainMEM_CHECK_SIZE_1 );\r
+ if( pvMem1 == NULL )\r
+ {\r
+ lErrorOccurred = pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ memset( pvMem1, 0xaa, mainMEM_CHECK_SIZE_1 );\r
+ vPortFree( pvMem1 );\r
+ }\r
+ }\r
+ xTaskResumeAll();\r
+\r
+ /* Again - with a different size block. */\r
+ vTaskSuspendAll();\r
+ {\r
+ pvMem2 = pvPortMalloc( mainMEM_CHECK_SIZE_2 );\r
+ if( pvMem2 == NULL )\r
+ {\r
+ lErrorOccurred = pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ memset( pvMem2, 0xaa, mainMEM_CHECK_SIZE_2 );\r
+ vPortFree( pvMem2 );\r
+ }\r
+ }\r
+ xTaskResumeAll();\r
+\r
+ /* Again - with a different size block. */\r
+ vTaskSuspendAll();\r
+ {\r
+ pvMem3 = pvPortMalloc( mainMEM_CHECK_SIZE_3 );\r
+ if( pvMem3 == NULL )\r
+ {\r
+ lErrorOccurred = pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ memset( pvMem3, 0xaa, mainMEM_CHECK_SIZE_3 );\r
+ vPortFree( pvMem3 );\r
+ }\r
+ }\r
+ xTaskResumeAll();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Called by the startup code. Initial processor setup can be placed in this\r
+ * function.\r
+ */\r
+void hw_initialise (void)\r
+{\r
+}\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+\r
+/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER for port 1.\r
+\r
+Note that this driver is written to test the RTOS port and is not intended\r
+to represent an optimised solution. In particular no use is made of the DMA\r
+peripheral. */\r
+\r
+/* Standard include files. */\r
+#include <stdlib.h>\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "queue.h"\r
+#include "task.h"\r
+\r
+/* Demo application include files. */\r
+#include "serial.h"\r
+\r
+/* The queues used to communicate between the task code and the interrupt\r
+service routines. */\r
+static xQueueHandle xRxedChars; \r
+static xQueueHandle xCharsForTx; \r
+\r
+/* Hardware specific constants. */\r
+#define serTX_INTERRUPT ( ( unsigned portCHAR ) 0x80 )\r
+#define serRX_INTERRUPT ( ( unsigned portCHAR ) 0x40 )\r
+#define serTX_ENABLE ( ( unsigned portCHAR ) 0x20 )\r
+#define serRX_ENABLE ( ( unsigned portCHAR ) 0x10 )\r
+\r
+/* Macros to turn on and off the serial port THRE interrupt while leaving the\r
+other register bits in their correct state. The Rx interrupt is always \r
+enabled. */\r
+#define serTX_INTERRUPT_ON() SCR1 = serTX_INTERRUPT | serRX_INTERRUPT | serTX_ENABLE | serRX_ENABLE; \r
+#define serTX_INTERRUPT_OFF() SCR1 = serRX_INTERRUPT | serTX_ENABLE | serRX_ENABLE;\r
+\r
+/* Bit used to switch on the channel 1 serial port in the module stop \r
+register. */\r
+#define serMSTP6 ( ( unsigned portSHORT ) 0x0040 )\r
+\r
+/* Interrupt service routines. Note that the Rx and Tx service routines can \r
+cause a context switch and are therefore defined with the saveall attribute in\r
+addition to the interrupt_handler attribute. See the FreeRTOS.org WEB site \r
+documentation for a full explanation.*/\r
+void vCOM_1_Rx_ISR( void ) __attribute__ ( ( saveall, interrupt_handler ) );\r
+void vCOM_1_Tx_ISR( void ) __attribute__ ( ( saveall, interrupt_handler ) );\r
+void vCOM_1_Error_ISR( void ) __attribute__ ( ( interrupt_handler ) );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Initialise port 1 for interrupt driven communications.\r
+ */\r
+xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )\r
+{\r
+ /* Create the queues used to communicate between the tasks and the\r
+ interrupt service routines. */\r
+ xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );\r
+ xCharsForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );\r
+\r
+ /* No parity, 8 data bits and 1 stop bit is the default so does not require \r
+ configuration - setup the remains of the hardware. */\r
+ portENTER_CRITICAL();\r
+ {\r
+ /* Turn channel 1 on. */\r
+ MSTPCR &= ~serMSTP6;\r
+\r
+ /* Enable the channels and the Rx interrupt. The Tx interrupt is only \r
+ enabled when data is being transmitted. */\r
+ SCR1 = serRX_INTERRUPT | serTX_ENABLE | serRX_ENABLE;\r
+\r
+ /* Bit rate settings for 22.1184MHz clock only!. */\r
+ switch( ulWantedBaud )\r
+ {\r
+ case 4800 : BRR1 = 143;\r
+ break;\r
+ case 9600 : BRR1 = 71;\r
+ break;\r
+ case 19200 : BRR1 = 35;\r
+ break;\r
+ case 38400 : BRR1 = 17;\r
+ break;\r
+ case 57600 : BRR1 = 11;\r
+ break;\r
+ case 115200 : BRR1 = 5;\r
+ break;\r
+ default : BRR1 = 5;\r
+ break;\r
+ }\r
+ }\r
+ portEXIT_CRITICAL(); \r
+\r
+ /* Unlike some ports, this driver code does not allow for more than one\r
+ com port. We therefore don't return a pointer to a port structure and can\r
+ instead just return NULL. */\r
+ return NULL;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )\r
+{\r
+ /* Get the next character from the buffer queue. Return false if no characters\r
+ are available, or arrive before xBlockTime expires. */\r
+ if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )\r
+ {\r
+ return pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ return pdFALSE;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )\r
+{\r
+signed portBASE_TYPE xReturn = pdPASS;\r
+\r
+ /* Return false if after the block time there is no room on the Tx queue. */\r
+ portENTER_CRITICAL();\r
+ {\r
+ /* Send a character to the queue of characters waiting transmission.\r
+ The queue is serviced by the Tx ISR. */\r
+ if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )\r
+ {\r
+ /* Could not post onto the queue. */\r
+ xReturn = pdFAIL;\r
+ }\r
+ else\r
+ {\r
+ /* The message was posted onto the queue so we turn on the Tx\r
+ interrupt to allow the Tx ISR to remove the character from the\r
+ queue. */\r
+ serTX_INTERRUPT_ON();\r
+ }\r
+ }\r
+ portEXIT_CRITICAL();\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSerialClose( xComPortHandle xPort )\r
+{ \r
+ /* Not supported. */\r
+ ( void ) xPort;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vCOM_1_Rx_ISR( void )\r
+{\r
+ /* This can cause a context switch so this macro must be the first line\r
+ in the function. */\r
+ portENTER_SWITCHING_ISR();\r
+\r
+ /* As this is a switching ISR the local variables must be declared as \r
+ static. */\r
+ static portCHAR cRxByte;\r
+ static portBASE_TYPE xTaskWokenByPost;\r
+\r
+ /* Get the character. */\r
+ cRxByte = RDR1;\r
+\r
+ /* Post the character onto the queue of received characters - noting\r
+ whether or not this wakes a task. */\r
+ xTaskWokenByPost = xQueueSendFromISR( xRxedChars, &cRxByte, pdFALSE ); \r
+\r
+ /* Clear the interrupt. */\r
+ SSR1 &= ~serRX_INTERRUPT;\r
+\r
+ /* This must be the last line in the function. We pass cTaskWokenByPost so \r
+ a context switch will occur if the received character woke a task that has\r
+ a priority higher than the task we interrupted. */\r
+ portEXIT_SWITCHING_ISR( xTaskWokenByPost );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vCOM_1_Tx_ISR( void )\r
+{\r
+ /* This can cause a context switch so this macro must be the first line\r
+ in the function. */\r
+ portENTER_SWITCHING_ISR();\r
+\r
+ /* As this is a switching ISR the local variables must be declared as \r
+ static. */\r
+ static portCHAR cTxByte;\r
+ static signed portBASE_TYPE xTaskWokenByTx;\r
+\r
+ /* This variable is static so must be explicitly reinitialised each\r
+ time the function executes. */\r
+ xTaskWokenByTx = pdFALSE;\r
+\r
+ /* The interrupt was caused by the THR becoming empty. Are there any\r
+ more characters to transmit? Note whether or not the Tx interrupt has\r
+ woken a task. */\r
+ if( xQueueReceiveFromISR( xCharsForTx, &cTxByte, &xTaskWokenByTx ) == pdTRUE )\r
+ {\r
+ /* A character was retrieved from the queue so can be sent to the\r
+ THR now. */ \r
+ TDR1 = cTxByte;\r
+\r
+ /* Clear the interrupt. */\r
+ SSR1 &= ~serTX_INTERRUPT;\r
+ }\r
+ else\r
+ {\r
+ /* Queue empty, nothing to send so turn off the Tx interrupt. */\r
+ serTX_INTERRUPT_OFF();\r
+ } \r
+\r
+ /* This must be the last line in the function. We pass cTaskWokenByTx so \r
+ a context switch will occur if the Tx'ed character woke a task that has\r
+ a priority higher than the task we interrupted. */\r
+ portEXIT_SWITCHING_ISR( xTaskWokenByTx );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * This ISR cannot cause a context switch so requires no special \r
+ * considerations. \r
+ */\r
+void vCOM_1_Error_ISR( void )\r
+{\r
+volatile unsigned portCHAR ucIn;\r
+\r
+ ucIn = SSR1;\r
+ SSR1 = 0;\r
+}\r
+\r
--- /dev/null
+;/****************************************************************\r
+;KPIT Cummins Infosystems Ltd, Pune, India. - 4th September 2003.\r
+;\r
+;This program is distributed in the hope that it will be useful,\r
+;but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+;MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE\r
+;\r
+;*****************************************************************/\r
+\r
+\r
+;*********************************************************************\r
+; File: start.asm\r
+;\r
+;\r
+; desc:\r
+; \r
+; System initialisation routine - entry point for the application.\r
+; The stack pointer is initialised, then the hardware initialisation\r
+; routine called. The static data areas are then initialised, before\r
+; the main function is executed. A simple exit funtion is also\r
+; supplied\r
+;\r
+;*********************************************************************\r
+\r
+#ifdef __H8300H__ \r
+\r
+#ifdef __NORMAL_MODE__\r
+ .h8300hn\r
+#else\r
+ .h8300h\r
+#endif\r
+\r
+#endif /*_H8300H_ */\r
+\r
+#ifdef __H8300S__\r
+\r
+#ifdef __NORMAL_MODE__\r
+ .h8300sn\r
+#else\r
+ .h8300s\r
+#endif\r
+\r
+#endif /* __H8300S__ */\r
+ \r
+ .section .text\r
+ .global _start\r
+#if DEBUG \r
+ .extern _exit\r
+#endif\r
+\r
+ .extern _hw_initialise\r
+ .extern _main\r
+\r
+ .extern _data\r
+ .extern _mdata\r
+ .extern _edata\r
+ .extern _bss\r
+ .extern _ebss\r
+ .extern _stack\r
+\r
+_start:\r
+ ; initialise the SP for non-vectored code\r
+ mov.l #_stack,er7\r
+ ; call the hardware initialiser\r
+ jsr @_hw_initialise\r
+#ifdef ROMSTART \r
+ ; get the boundaries for the .data section initialisation\r
+ mov.l #_data,er0\r
+ mov.l #_edata,er1\r
+ mov.l #_mdata,er2\r
+ cmp.l er0,er1\r
+ beq start_1\r
+start_l:\r
+ mov.b @er2,r3l ;get from src\r
+ mov.b r3l,@er0 ;place in dest\r
+ inc.l #1,er2 ;inc src\r
+ inc.l #1,er0 ;inc dest\r
+ cmp.l er0,er1 ;dest == edata?\r
+ bne start_l\r
+start_1:\r
+#endif //ROMSTART\r
+ ; zero out bss\r
+ mov.l #_bss,er0\r
+ mov.l #_ebss,er1\r
+ cmp.l er0,er1 \r
+ beq start_3\r
+ sub.b r2l,r2l\r
+start_2:\r
+ mov.b r2l,@er0\r
+ inc.l #1,er0\r
+ cmp.l er0,er1\r
+ bne start_2\r
+start_3:\r
+#ifdef CPPAPP \r
+ ;Initialize global constructor \r
+ jsr @___main\r
+#endif\r
+ \r
+ ; call the mainline \r
+ jsr @_main\r
+\r
+ \r
+ mov.l er0,er4\r
+ \r
+ ;call to exit\r
+#if DEBUG\r
+ jsr @_exit\r
+#endif\r
+#if RELEASE\r
+ exit:\r
+ bra exit\r
+#endif\r
+\r
+ \r
+\r
--- /dev/null
+/****************************************************************\r
+KPIT Cummins Infosystems Ltd, Pune, India. - 19-June-2003.\r
+\r
+This program is distributed in the hope that it will be useful,\r
+but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\r
+*****************************************************************/\r
+\r
+void start(void); /* Startup code (in start.asm) */\r
+\r
+/*\r
+ * Manual context switch trap function.\r
+ */\r
+void vPortYield( void );\r
+\r
+/*\r
+ * The RTOS tick ISR.\r
+ */\r
+void vTickISR( void );\r
+\r
+/* \r
+ * Serial port ISR functions.\r
+ */\r
+void vCOM_1_Rx_ISR( void );\r
+void vCOM_1_Tx_ISR( void );\r
+void vCOM_1_Error_ISR( void );\r
+\r
+\r
+typedef void (*fp) (void);\r
+#define VECT_SECT __attribute__ ((section (".vects")))\r
+\r
+const fp HardwareVectors[] VECT_SECT = {\r
+start, /* vector 0 */\r
+(fp)(0), /* vector 1 */\r
+(fp)(0), /* vector 2 */\r
+(fp)(0), /* vector 3 */\r
+(fp)(0), /* vector 4 */\r
+(fp)(0), /* vector 5 */\r
+(fp)(0), /* vector 6 */\r
+(fp)(0), /* vector 7 */\r
+vPortYield, /* vector 8 */\r
+(fp)(0), /* vector 9 */\r
+(fp)(0), /* vector 10 */\r
+(fp)(0), /* vector 11 */\r
+(fp)(0), /* vector 12 */\r
+(fp)(0), /* vector 13 */\r
+(fp)(0), /* vector 14 */\r
+(fp)(0), /* vector 15 */\r
+(fp)(0), /* vector 16 */\r
+(fp)(0), /* vector 17 */\r
+(fp)(0), /* vector 18 */\r
+(fp)(0), /* vector 19 */\r
+(fp)(0), /* vector 20 */\r
+(fp)(0), /* vector 21 */\r
+(fp)(0), /* vector 22 */\r
+(fp)(0), /* vector 23 */\r
+(fp)(0), /* vector 24 */\r
+(fp)(0), /* vector 25 */\r
+(fp)(0), /* vector 26 */\r
+(fp)(0), /* vector 27 */\r
+(fp)(0), /* vector 28 */\r
+(fp)(0), /* vector 29 */\r
+(fp)(0), /* vector 30 */\r
+(fp)(0), /* vector 31 */\r
+(fp)(0), /* vector 32 */\r
+(fp)(0), /* vector 33 */\r
+(fp)(0), /* vector 34 */\r
+(fp)(0), /* vector 35 */\r
+(fp)(0), /* vector 36 */\r
+(fp)(0), /* vector 37 */\r
+(fp)(0), /* vector 38 */\r
+(fp)(0), /* vector 39 */\r
+vTickISR, /* vector 40 */\r
+(fp)(0), /* vector 41 */\r
+(fp)(0), /* vector 42 */\r
+(fp)(0), /* vector 43 */\r
+(fp)(0), /* vector 44 */\r
+(fp)(0), /* vector 45 */\r
+(fp)(0), /* vector 46 */\r
+(fp)(0), /* vector 47 */\r
+(fp)(0), /* vector 48 */\r
+(fp)(0), /* vector 49 */\r
+(fp)(0), /* vector 50 */\r
+(fp)(0), /* vector 51 */\r
+(fp)(0), /* vector 52 */\r
+(fp)(0), /* vector 53 */\r
+(fp)(0), /* vector 54 */\r
+(fp)(0), /* vector 55 */\r
+(fp)(0), /* vector 56 */\r
+(fp)(0), /* vector 57 */\r
+(fp)(0), /* vector 58 */\r
+(fp)(0), /* vector 59 */\r
+(fp)(0), /* vector 60 */\r
+(fp)(0), /* vector 61 */\r
+(fp)(0), /* vector 62 */\r
+(fp)(0), /* vector 63 */\r
+(fp)(0), /* vector 64 */\r
+(fp)(0), /* vector 65 */\r
+(fp)(0), /* vector 66 */\r
+(fp)(0), /* vector 67 */\r
+(fp)(0), /* vector 68 */\r
+(fp)(0), /* vector 69 */\r
+(fp)(0), /* vector 70 */\r
+(fp)(0), /* vector 71 */\r
+(fp)(0), /* vector 72 */\r
+(fp)(0), /* vector 73 */\r
+(fp)(0), /* vector 74 */\r
+(fp)(0), /* vector 75 */\r
+(fp)(0), /* vector 76 */\r
+(fp)(0), /* vector 77 */\r
+(fp)(0), /* vector 78 */\r
+(fp)(0), /* vector 79 */\r
+(fp)(0), /* vector 80 */\r
+(fp)(0), /* vector 81 */\r
+(fp)(0), /* vector 82 */\r
+(fp)(0), /* vector 83 */\r
+vCOM_1_Error_ISR, /* vector 84 */\r
+vCOM_1_Rx_ISR, /* vector 85 */\r
+vCOM_1_Tx_ISR, /* vector 86 */\r
+(fp)(0), /* vector 87 */\r
+(fp)(0), /* vector 88 */\r
+(fp)(0), /* vector 89 */\r
+(fp)(0), /* vector 90 */\r
+(fp)(0), /* vector 91 */\r
+(fp)(0), /* vector 92 */\r
+(fp)(0), /* vector 93 */\r
+(fp)(0), /* vector 94 */\r
+(fp)(0), /* vector 95 */\r
+(fp)(0), /* vector 96 */\r
+(fp)(0), /* vector 97 */\r
+(fp)(0), /* vector 98 */\r
+(fp)(0), /* vector 99 */\r
+(fp)(0), /* vector 100 */\r
+(fp)(0), /* vector 101 */\r
+(fp)(0), /* vector 102 */\r
+(fp)(0) /* vector 103 */\r
+};\r
--- /dev/null
+/** ###################################################################\r
+** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.\r
+** Filename : Byte1.C\r
+** Project : RTOSDemo\r
+** Processor : MC9S12DP256BCPV\r
+** Beantype : ByteIO\r
+** Version : Bean 02.019, Driver 01.03, CPU db: 2.87.283\r
+** Compiler : Metrowerks HC12 C Compiler\r
+** Date/Time : 16/06/2005, 21:10\r
+** Abstract :\r
+** This bean "ByteIO" implements an one-byte input/output.\r
+** It uses one 8-bit port.\r
+** Note: This bean is set to work in Output direction only.\r
+** Methods of this bean are mostly implemented as a macros \r
+** (if supported by target langauage and compiler).\r
+** Settings :\r
+** Port name : B\r
+**\r
+** Initial direction : Output (direction cannot be changed)\r
+** Initial output value : 255 = 0FFH\r
+** Initial pull option : off\r
+**\r
+** 8-bit data register : PORTB [1]\r
+** 8-bit control register : DDRB [3]\r
+**\r
+** ----------------------------------------------------\r
+** Bit | Pin | Name\r
+** ----------------------------------------------------\r
+** 0 | 24 | PB0_ADDR0_DATA0\r
+** 1 | 25 | PB1_ADDR1_DATA1\r
+** 2 | 26 | PB2_ADDR2_DATA2\r
+** 3 | 27 | PB3_ADDR3_DATA3\r
+** 4 | 28 | PB4_ADDR4_DATA4\r
+** 5 | 29 | PB5_ADDR5_DATA5\r
+** 6 | 30 | PB6_ADDR6_DATA6\r
+** 7 | 31 | PB7_ADDR7_DATA7\r
+** ----------------------------------------------------\r
+** Contents :\r
+** PutBit - void Byte1_PutBit(byte Bit,bool Val);\r
+** NegBit - void Byte1_NegBit(byte Bit);\r
+**\r
+** (c) Copyright UNIS, spol. s r.o. 1997-2002\r
+** UNIS, spol. s r.o.\r
+** Jundrovska 33\r
+** 624 00 Brno\r
+** Czech Republic\r
+** http : www.processorexpert.com\r
+** mail : info@processorexpert.com\r
+** ###################################################################*/\r
+\r
+\r
+/* MODULE Byte1. */\r
+\r
+#include "Byte1.h"\r
+/*Including shared modules, which are used for all project*/\r
+#include "PE_Types.h"\r
+#include "PE_Error.h"\r
+#include "PE_Const.h"\r
+#include "IO_Map.h"\r
+#include "PE_Timer.h"\r
+\r
+#include "Cpu.h"\r
+\r
+/* Definition of DATA and CODE segments for this bean. User can specify where\r
+ these segments will be located on "Build options" tab of the selected CPU bean. */\r
+#pragma DATA_SEG Byte1_DATA /* Data section for this module. */\r
+#pragma CODE_SEG Byte1_CODE /* Code section for this module. */\r
+\r
+/*\r
+** ===================================================================\r
+** Method : Byte1_GetMsk (bean ByteIO)\r
+**\r
+** Description :\r
+** This method is internal. It is used by Processor Expert\r
+** only.\r
+** ===================================================================\r
+*/\r
+byte Byte1_Table[8]={ 1, 2, 4, 8, 16, 32, 64, 128 }; /* Table of mask constants */\r
+\r
+byte Byte1_GetMsk(byte Value)\r
+{\r
+ return((Value<8)?Byte1_Table[Value]:0); /* Return appropriate bit mask */\r
+}\r
+\r
+/*\r
+** ===================================================================\r
+** Method : Byte1_PutBit (bean ByteIO)\r
+**\r
+** Description :\r
+** This method writes the new value to the specified bit\r
+** of the output value.\r
+** Parameters :\r
+** NAME - DESCRIPTION\r
+** Bitnum - Number of the bit (0 to 7)\r
+** Val - New value of the bit (FALSE or TRUE)\r
+** FALSE = "0" or "Low", TRUE = "1" or "High"\r
+** Returns : Nothing\r
+** ===================================================================\r
+*/\r
+void Byte1_PutBit(byte BitNum, byte Value)\r
+{\r
+ byte Mask=Byte1_GetMsk(BitNum); /* Temporary variable - bit mask */\r
+\r
+ if (Mask) /* Is bit mask correct? */\r
+ if (Value) { /* Is it one to be written? */\r
+ PORTB |= Mask; /* Set appropriate bit on port */\r
+ }\r
+ else { /* Is it zero to be written? */\r
+ PORTB &= ~Mask; /* Clear appropriate bit on port */\r
+ }\r
+}\r
+\r
+/*\r
+** ===================================================================\r
+** Method : Byte1_NegBit (bean ByteIO)\r
+**\r
+** Description :\r
+** This method negates (invertes) the specified bit of the\r
+** output value.\r
+** Parameters :\r
+** NAME - DESCRIPTION\r
+** Bit - Number of the bit to invert (0 to 7)\r
+** Returns : Nothing\r
+** ===================================================================\r
+*/\r
+void Byte1_NegBit(byte BitNum)\r
+{\r
+ byte Mask=Byte1_GetMsk(BitNum); /* Temporary variable - bit mask */\r
+\r
+ if (Mask) { /* Is bit mask correct? */\r
+ PORTB ^= Mask; /* Negate appropriate bit on port */\r
+ }\r
+}\r
+\r
+\r
+/* END Byte1. */\r
+\r
+/*\r
+** ###################################################################\r
+**\r
+** This file was created by UNIS Processor Expert 03.33 for \r
+** the Motorola HCS12 series of microcontrollers.\r
+**\r
+** ###################################################################\r
+*/\r
--- /dev/null
+/** ###################################################################\r
+** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.\r
+** Filename : Byte1.H\r
+** Project : RTOSDemo\r
+** Processor : MC9S12DP256BCPV\r
+** Beantype : ByteIO\r
+** Version : Bean 02.019, Driver 01.03, CPU db: 2.87.283\r
+** Compiler : Metrowerks HC12 C Compiler\r
+** Date/Time : 16/06/2005, 21:10\r
+** Abstract :\r
+** This bean "ByteIO" implements an one-byte input/output.\r
+** It uses one 8-bit port.\r
+** Note: This bean is set to work in Output direction only.\r
+** Methods of this bean are mostly implemented as a macros \r
+** (if supported by target langauage and compiler).\r
+** Settings :\r
+** Port name : B\r
+**\r
+** Initial direction : Output (direction cannot be changed)\r
+** Initial output value : 255 = 0FFH\r
+** Initial pull option : off\r
+**\r
+** 8-bit data register : PORTB [1]\r
+** 8-bit control register : DDRB [3]\r
+**\r
+** ----------------------------------------------------\r
+** Bit | Pin | Name\r
+** ----------------------------------------------------\r
+** 0 | 24 | PB0_ADDR0_DATA0\r
+** 1 | 25 | PB1_ADDR1_DATA1\r
+** 2 | 26 | PB2_ADDR2_DATA2\r
+** 3 | 27 | PB3_ADDR3_DATA3\r
+** 4 | 28 | PB4_ADDR4_DATA4\r
+** 5 | 29 | PB5_ADDR5_DATA5\r
+** 6 | 30 | PB6_ADDR6_DATA6\r
+** 7 | 31 | PB7_ADDR7_DATA7\r
+** ----------------------------------------------------\r
+** Contents :\r
+** PutBit - void Byte1_PutBit(byte Bit,bool Val);\r
+** NegBit - void Byte1_NegBit(byte Bit);\r
+**\r
+** (c) Copyright UNIS, spol. s r.o. 1997-2002\r
+** UNIS, spol. s r.o.\r
+** Jundrovska 33\r
+** 624 00 Brno\r
+** Czech Republic\r
+** http : www.processorexpert.com\r
+** mail : info@processorexpert.com\r
+** ###################################################################*/\r
+\r
+#ifndef __Byte1_H\r
+#define __Byte1_H\r
+\r
+/* MODULE Byte1. */\r
+\r
+/*Including shared modules, which are used in the whole project*/\r
+#include "PE_Types.h"\r
+#include "PE_Error.h"\r
+#include "PE_Const.h"\r
+#include "IO_Map.h"\r
+#include "PE_Timer.h"\r
+\r
+#include "Cpu.h"\r
+\r
+#pragma CODE_SEG Byte1_CODE /* Code section for this module. */\r
+\r
+/*\r
+** ===================================================================\r
+** Method : Byte1_PutBit (bean ByteIO)\r
+**\r
+** Description :\r
+** This method writes the new value to the specified bit\r
+** of the output value.\r
+** Parameters :\r
+** NAME - DESCRIPTION\r
+** BitNum - Number of the bit (0 to 7)\r
+** Val - New value of the bit (FALSE or TRUE)\r
+** FALSE = "0" or "Low", TRUE = "1" or "High"\r
+** Returns : Nothing\r
+** ===================================================================\r
+*/\r
+void Byte1_PutBit(byte BitNum, byte Value);\r
+\r
+/*\r
+** ===================================================================\r
+** Method : Byte1_NegBit (bean ByteIO)\r
+**\r
+** Description :\r
+** This method negates (invertes) the specified bit of the\r
+** output value.\r
+** Parameters :\r
+** NAME - DESCRIPTION\r
+** BitNum - Number of the bit to invert (0 to 7)\r
+** Returns : Nothing\r
+** ===================================================================\r
+*/\r
+void Byte1_NegBit(byte BitNum);\r
+\r
+#pragma CODE_SEG DEFAULT /* Change code section to DEFAULT. */\r
+\r
+/* END Byte1. */\r
+\r
+#endif /* __Byte1_H*/\r
+/*\r
+** ###################################################################\r
+**\r
+** This file was created by UNIS Processor Expert 03.33 for \r
+** the Motorola HCS12 series of microcontrollers.\r
+**\r
+** ###################################################################\r
+*/\r
--- /dev/null
+/** ###################################################################\r
+** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.\r
+** Filename : COM0.C\r
+** Project : RTOSDemo\r
+** Processor : MC9S12DP256BCPV\r
+** Beantype : AsynchroSerial\r
+** Version : Bean 02.231, Driver 01.08, CPU db: 2.87.283\r
+** Compiler : Metrowerks HC12 C Compiler\r
+** Date/Time : 19/06/2005, 15:07\r
+** Abstract :\r
+** This bean "AsynchroSerial" implements an asynchronous serial\r
+** communication. The bean supports different settings of \r
+** parity, word width, stop-bit and communication speed,\r
+** user can select interrupt or polling handler.\r
+** Communication speed can be changed also in runtime.\r
+** The bean requires one on-chip asynchronous serial channel.\r
+** Settings :\r
+** Serial channel : SCI0\r
+**\r
+** Protocol\r
+** Init baud rate : 38400baud\r
+** Width : 8 bits\r
+** Stop bits : 1\r
+** Parity : none\r
+** Breaks : Disabled\r
+**\r
+** Registers\r
+** Input buffer : SCI0DRL [207]\r
+** Output buffer : SCI0DRL [207]\r
+** Control register : SCI0CR1 [202]\r
+** Mode register : SCI0CR2 [203]\r
+** Baud setting reg. : SCI0BD [200]\r
+** Special register : SCI0SR1 [204]\r
+**\r
+** Input interrupt\r
+** Vector name : INT_SCI0\r
+** Priority : 1\r
+**\r
+** Output interrupt\r
+** Vector name : INT_SCI0\r
+** Priority : 1\r
+**\r
+** Used pins : \r
+** ----------------------------------------------------\r
+** Function | On package | Name\r
+** ----------------------------------------------------\r
+** Input | 89 | PS0_RxD0\r
+** Output | 90 | PS1_TxD0\r
+** ----------------------------------------------------\r
+**\r
+**\r
+** Used baud modes :\r
+** ----------------------------------------------------\r
+** No. | Mode ID | Baud rate\r
+** ----------------------------------------------------\r
+** 0 | Bm_38400baud | 38400baud\r
+** 1 | Bm_19200baud | 19200baud\r
+** 2 | Bm_9600baud | 9600baud\r
+** 3 | Bm_4800baud | 4800baud\r
+** ----------------------------------------------------\r
+** Contents :\r
+** SetBaudRateMode - byte COM0_SetBaudRateMode(byte Mod);\r
+**\r
+** (c) Copyright UNIS, spol. s r.o. 1997-2002\r
+** UNIS, spol. s r.o.\r
+** Jundrovska 33\r
+** 624 00 Brno\r
+** Czech Republic\r
+** http : www.processorexpert.com\r
+** mail : info@processorexpert.com\r
+** ###################################################################*/\r
+\r
+/* MODULE COM0. */\r
+\r
+#pragma MESSAGE DISABLE C4002 /* WARNING C4002: Result not used is ignored */\r
+#pragma MESSAGE DISABLE C4301 /* INFORMATION C4301: Inline expansion done for function call */\r
+\r
+#include "COM0.h"\r
+#include "TickTimer.h"\r
+#include "Byte1.h"\r
+\r
+/* Definition of DATA and CODE segments for this bean. User can specify where\r
+ these segments will be located on "Build options" tab of the selected CPU bean. */\r
+#pragma DATA_SEG COM0_DATA /* Data section for this module. */\r
+#pragma CODE_SEG COM0_CODE /* Code section for this module. */\r
+\r
+\r
+#define OVERRUN_ERR 1 /* Overrun error flag bit */\r
+#define FRAMING_ERR 2 /* Framing error flag bit */\r
+#define PARITY_ERR 4 /* Parity error flag bit */\r
+#define CHAR_IN_RX 8 /* Char is in RX buffer */\r
+#define FULL_TX 16 /* Full transmit buffer */\r
+#define RUNINT_FROM_TX 32 /* Interrupt is in progress */\r
+#define FULL_RX 64 /* Full receive buffer */\r
+#define NOISE_ERR 128 /* Noise erorr flag bit */\r
+#define IDLE_ERR 256 /* Idle character flag bit */\r
+#define BREAK_ERR 512 /* Break detect */\r
+\r
+static word SerFlag; /* Flags for serial communication */\r
+ /* Bits: 0 - OverRun error */\r
+ /* 1 - Framing error */\r
+ /* 2 - Parity error */\r
+ /* 3 - Char in RX buffer */\r
+ /* 4 - Full TX buffer */\r
+ /* 5 - Running int from TX */\r
+ /* 6 - Full RX buffer */\r
+ /* 7 - Noise error */\r
+ /* 8 - Idle character */\r
+ /* 9 - Break detected */\r
+ /* 10 - Unused */\r
+static word PrescHigh;\r
+static byte NumMode; /* Number of selected baud mode */\r
+\r
+\r
+/*\r
+** ===================================================================\r
+** Method : HWEnDi (bean AsynchroSerial)\r
+**\r
+** Description :\r
+** This method is internal. It is used by Processor Expert\r
+** only.\r
+** ===================================================================\r
+*/\r
+static void HWEnDi(void)\r
+{\r
+ SCI0CR2_TE = 1; /* Enable transmitter */\r
+ SCI0CR2_RE = 1; /* Enable receiver */\r
+ SCI0CR2_RIE = 1; /* Enable recieve interrupt */\r
+}\r
+\r
+/*\r
+** ===================================================================\r
+** Method : COM0_SetBaudRateMode (bean AsynchroSerial)\r
+**\r
+** Description :\r
+** This method changes the channel communication speed (baud\r
+** rate). This method can be used only if you specify a list\r
+** of possible period settings at design time (see <Timing\r
+** dialog box> - Runtime setting - from a list of values).\r
+** Each of these settings constitutes a mode and Processor\r
+** Expert^[TM] assigns them a mode identifier. The prescaler\r
+** and compare values corresponding to each mode are\r
+** calculated at design time. You may switch modes at\r
+** runtime by referring only to a mode identifier. No\r
+** run-time calculations are performed, all the calculations\r
+** are performed at design time.\r
+** Parameters :\r
+** NAME - DESCRIPTION\r
+** Mod - Timing mode to set\r
+** Returns :\r
+** --- - Error code, possible codes:\r
+** ERR_OK - OK\r
+** ERR_SPEED - This device does not work in\r
+** the active speed mode\r
+** ===================================================================\r
+*/\r
+byte COM0_SetBaudRateMode(byte Mod)\r
+{\r
+ static const word COM0_PrescHigh[4] = {41,81,163,326};\r
+\r
+ if(Mod >= 4) /* Is mode in baud mode list */\r
+ return ERR_VALUE; /* If no then error */\r
+ NumMode = Mod; /* New baud mode */\r
+ PrescHigh = COM0_PrescHigh[Mod]; /* Prescaler in high speed mode */\r
+ SCI0BD = PrescHigh; /* Set prescaler bits */\r
+ return ERR_OK; /* OK */\r
+}\r
+\r
+/*\r
+** ===================================================================\r
+** Method : COM0_Init (bean AsynchroSerial)\r
+**\r
+** Description :\r
+** This method is internal. It is used by Processor Expert\r
+** only.\r
+** ===================================================================\r
+*/\r
+void COM0_Init(void)\r
+{\r
+ PrescHigh = 41; /* Precaler in high speed mode */\r
+ SerFlag = 0; /* Reset flags */\r
+ NumMode = 0; /* Number of selected baud mode */\r
+ /* SCI0CR1: LOOPS=0,SCISWAI=1,RSRC=0,M=0,WAKE=0,ILT=0,PE=0,PT=0 */\r
+ SCI0CR1 = 64; /* Set the SCI configuration */\r
+ /* SCI0SR2: ??=0,??=0,??=0,??=0,??=0,BRK13=0,TXDIR=0,RAF=0 */\r
+ SCI0SR2 = 0; /* Set the Break Character Length and Transmitter pin data direction in Single-wire mode */\r
+ SCI0SR1; /* Reset interrupt request flags */\r
+ /* SCI0CR2: SCTIE=0,TCIE=0,RIE=0,ILIE=0,TE=0,RE=0,RWU=0,SBK=0 */\r
+ SCI0CR2 = 0; /* Disable error interrupts */\r
+ SCI0BD = PrescHigh; /* Set prescaler bits */\r
+ HWEnDi(); /* Enable/disable device according to status flags */\r
+}\r
+\r
+\r
+/* END COM0. */\r
+\r
+\r
+/*\r
+** ###################################################################\r
+**\r
+** This file was created by UNIS Processor Expert 03.33 for \r
+** the Motorola HCS12 series of microcontrollers.\r
+**\r
+** ###################################################################\r
+*/\r
--- /dev/null
+/** ###################################################################\r
+** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.\r
+** Filename : COM0.H\r
+** Project : RTOSDemo\r
+** Processor : MC9S12DP256BCPV\r
+** Beantype : AsynchroSerial\r
+** Version : Bean 02.231, Driver 01.08, CPU db: 2.87.283\r
+** Compiler : Metrowerks HC12 C Compiler\r
+** Date/Time : 19/06/2005, 15:07\r
+** Abstract :\r
+** This bean "AsynchroSerial" implements an asynchronous serial\r
+** communication. The bean supports different settings of \r
+** parity, word width, stop-bit and communication speed,\r
+** user can select interrupt or polling handler.\r
+** Communication speed can be changed also in runtime.\r
+** The bean requires one on-chip asynchronous serial channel.\r
+** Settings :\r
+** Serial channel : SCI0\r
+**\r
+** Protocol\r
+** Init baud rate : 38400baud\r
+** Width : 8 bits\r
+** Stop bits : 1\r
+** Parity : none\r
+** Breaks : Disabled\r
+**\r
+** Registers\r
+** Input buffer : SCI0DRL [207]\r
+** Output buffer : SCI0DRL [207]\r
+** Control register : SCI0CR1 [202]\r
+** Mode register : SCI0CR2 [203]\r
+** Baud setting reg. : SCI0BD [200]\r
+** Special register : SCI0SR1 [204]\r
+**\r
+** Input interrupt\r
+** Vector name : INT_SCI0\r
+** Priority : 1\r
+**\r
+** Output interrupt\r
+** Vector name : INT_SCI0\r
+** Priority : 1\r
+**\r
+** Used pins : \r
+** ----------------------------------------------------\r
+** Function | On package | Name\r
+** ----------------------------------------------------\r
+** Input | 89 | PS0_RxD0\r
+** Output | 90 | PS1_TxD0\r
+** ----------------------------------------------------\r
+**\r
+**\r
+** Used baud modes :\r
+** ----------------------------------------------------\r
+** No. | Mode ID | Baud rate\r
+** ----------------------------------------------------\r
+** 0 | Bm_38400baud | 38400baud\r
+** 1 | Bm_19200baud | 19200baud\r
+** 2 | Bm_9600baud | 9600baud\r
+** 3 | Bm_4800baud | 4800baud\r
+** ----------------------------------------------------\r
+** Contents :\r
+** SetBaudRateMode - byte COM0_SetBaudRateMode(byte Mod);\r
+**\r
+** (c) Copyright UNIS, spol. s r.o. 1997-2002\r
+** UNIS, spol. s r.o.\r
+** Jundrovska 33\r
+** 624 00 Brno\r
+** Czech Republic\r
+** http : www.processorexpert.com\r
+** mail : info@processorexpert.com\r
+** ###################################################################*/\r
+\r
+#ifndef __COM0\r
+#define __COM0\r
+\r
+/* MODULE COM0. */\r
+\r
+#include "Cpu.h"\r
+\r
+#define COM0_Bm_38400baud 0 /* Constant for switch to mode 0 */\r
+#define COM0_Bm_19200baud 1 /* Constant for switch to mode 1 */\r
+#define COM0_Bm_9600baud 2 /* Constant for switch to mode 2 */\r
+#define COM0_Bm_4800baud 3 /* Constant for switch to mode 3 */\r
+\r
+\r
+\r
+#ifndef __BWUserType_tItem\r
+#define __BWUserType_tItem\r
+ typedef struct { /* Item of the index table for possible baudrates */\r
+ word div; /* divisior */\r
+ byte val; /* values of the prescalers */\r
+ } tItem;\r
+#endif\r
+#ifndef __BWUserType_COM0_TError\r
+#define __BWUserType_COM0_TError\r
+typedef union {\r
+ byte err;\r
+ struct {\r
+ bool OverRun : 1; /* OverRun error flag */\r
+ bool Framing : 1; /* Framing error flag */\r
+ bool Parity : 1; /* Parity error flag */\r
+ bool RxBufOvf : 1; /* Rx buffer full error flag */\r
+ bool Noise : 1; /* Noise error */\r
+ bool Break : 1; /* Break detect */\r
+ bool Idle : 1; /* Idle characted */\r
+ }errName;\r
+} COM0_TError;\r
+#endif\r
+#ifndef __BWUserType_TDirection\r
+#define __BWUserType_TDirection\r
+ typedef enum { /* */\r
+ TXD_INPUT,\r
+ TXD_OUTPUT\r
+ } TDirection;\r
+#endif\r
+\r
+#ifndef __BWUserType_COM0_TComData\r
+#define __BWUserType_COM0_TComData\r
+ typedef byte COM0_TComData ; /* User type for communication. Size of this type depends on the communication data witdh. */\r
+#endif\r
+\r
+#pragma CODE_SEG COM0_CODE /* Code section for this module. */\r
+\r
+byte COM0_SetBaudRateMode(byte Mod);\r
+/*\r
+** ===================================================================\r
+** Method : COM0_SetBaudRateMode (bean AsynchroSerial)\r
+**\r
+** Description :\r
+** This method changes the channel communication speed (baud\r
+** rate). This method can be used only if you specify a list\r
+** of possible period settings at design time (see <Timing\r
+** dialog box> - Runtime setting - from a list of values).\r
+** Each of these settings constitutes a mode and Processor\r
+** Expert^[TM] assigns them a mode identifier. The prescaler\r
+** and compare values corresponding to each mode are\r
+** calculated at design time. You may switch modes at\r
+** runtime by referring only to a mode identifier. No\r
+** run-time calculations are performed, all the calculations\r
+** are performed at design time.\r
+** Parameters :\r
+** NAME - DESCRIPTION\r
+** Mod - Timing mode to set\r
+** Returns :\r
+** --- - Error code, possible codes:\r
+** ERR_OK - OK\r
+** ERR_SPEED - This device does not work in\r
+** the active speed mode\r
+** ===================================================================\r
+*/\r
+\r
+#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */\r
+__interrupt void COM0_Interrupt(void);\r
+#pragma CODE_SEG COM0_CODE /* Code section for this module. */\r
+/*\r
+** ===================================================================\r
+** Method : COM0_Interrupt (bean AsynchroSerial)\r
+**\r
+** Description :\r
+** This method is internal. It is used by Processor Expert\r
+** only.\r
+** ===================================================================\r
+*/\r
+\r
+\r
+void COM0_Init(void);\r
+/*\r
+** ===================================================================\r
+** Method : COM0_Init (bean AsynchroSerial)\r
+**\r
+** Description :\r
+** This method is internal. It is used by Processor Expert\r
+** only.\r
+** ===================================================================\r
+*/\r
+\r
+\r
+#pragma CODE_SEG DEFAULT /* Change code section to DEFAULT. */\r
+\r
+/* END COM0. */\r
+\r
+/*\r
+** ###################################################################\r
+**\r
+** This file was created by UNIS Processor Expert 03.33 for \r
+** the Motorola HCS12 series of microcontrollers.\r
+**\r
+** ###################################################################\r
+*/\r
+\r
+#endif /* ifndef __COM0 */\r
--- /dev/null
+/** ###################################################################\r
+** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.\r
+** Filename : Cpu.C\r
+** Project : RTOSDemo\r
+** Processor : MC9S12DP256BCPV\r
+** Beantype : MC9S12DP256_112\r
+** Version : Bean 01.148, Driver 01.09, CPU db: 2.87.283\r
+** Compiler : Metrowerks HC12 C Compiler\r
+** Date/Time : 16/06/2005, 19:18\r
+** Abstract :\r
+** This bean "MC9S12DP256_112" implements properties, methods,\r
+** and events of the CPU.\r
+** Settings :\r
+**\r
+** Contents :\r
+** EnableInt - void Cpu_EnableInt(void);\r
+** DisableInt - void Cpu_DisableInt(void);\r
+**\r
+** (c) Copyright UNIS, spol. s r.o. 1997-2002\r
+** UNIS, spol. s r.o.\r
+** Jundrovska 33\r
+** 624 00 Brno\r
+** Czech Republic\r
+** http : www.processorexpert.com\r
+** mail : info@processorexpert.com\r
+** ###################################################################*/\r
+\r
+\r
+#include "Cpu.h"\r
+#include "TickTimer.h"\r
+#include "Byte1.h"\r
+\r
+extern void near _EntryPoint(void); /* Startup routine */\r
+extern void near vPortTickInterrupt( void );\r
+extern void near vPortYield( void );\r
+extern void near vCOM0_ISR( void );\r
+\r
+typedef void (*near tIsrFunc)(void);\r
+const tIsrFunc _vect[] @0xFF80 = { /* Interrupt table */\r
+ Cpu_Interrupt, /* 0 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 1 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 2 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 3 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 4 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 5 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 6 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 7 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 8 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 9 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 10 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 11 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 12 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 13 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 14 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 15 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 16 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 17 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 18 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 19 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 20 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 21 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 22 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 23 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 24 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 25 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 26 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 27 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 28 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 29 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 30 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 31 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 32 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 33 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 34 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 35 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 36 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 37 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 38 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 39 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 40 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 41 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 42 Default (unused) interrupt */\r
+ vCOM0_ISR,\r
+ Cpu_Interrupt, /* 44 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 45 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 46 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 47 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 48 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 49 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 50 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 51 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 52 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 53 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 54 Default (unused) interrupt */\r
+ vPortTickInterrupt,\r
+ Cpu_Interrupt, /* 56 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 57 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 58 Default (unused) interrupt */\r
+ vPortYield, /* 59 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 60 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 61 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 62 Default (unused) interrupt */\r
+ _EntryPoint /* Reset vector */\r
+ };\r
+/*\r
+** ###################################################################\r
+**\r
+** This file was created by UNIS Processor Expert 03.33 for \r
+** the Motorola HCS12 series of microcontrollers.\r
+**\r
+** ###################################################################\r
+*/\r
--- /dev/null
+/** ###################################################################\r
+** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.\r
+** Filename : Cpu.C\r
+** Project : RTOSDemo\r
+** Processor : MC9S12DP256BCPV\r
+** Beantype : MC9S12DP256_112\r
+** Version : Bean 01.148, Driver 01.09, CPU db: 2.87.283\r
+** Compiler : Metrowerks HC12 C Compiler\r
+** Date/Time : 18/06/2005, 16:21\r
+** Abstract :\r
+** This bean "MC9S12DP256_112" implements properties, methods,\r
+** and events of the CPU.\r
+** Settings :\r
+**\r
+** Contents :\r
+** EnableInt - void Cpu_EnableInt(void);\r
+** DisableInt - void Cpu_DisableInt(void);\r
+**\r
+** (c) Copyright UNIS, spol. s r.o. 1997-2002\r
+** UNIS, spol. s r.o.\r
+** Jundrovska 33\r
+** 624 00 Brno\r
+** Czech Republic\r
+** http : www.processorexpert.com\r
+** mail : info@processorexpert.com\r
+** ###################################################################*/\r
+\r
+/* MODULE Cpu. */\r
+\r
+#include "TickTimer.h"\r
+#include "Byte1.h"\r
+#include "COM0.h"\r
+#include "PE_Types.h"\r
+#include "PE_Error.h"\r
+#include "PE_Const.h"\r
+#include "IO_Map.h"\r
+#include "PE_Timer.h"\r
+#include "Events.h"\r
+#include "Cpu.h"\r
+\r
+#define CGM_DELAY 3071UL\r
+\r
+\r
+/* Global variables */\r
+volatile byte CCR_reg; /* Current CCR reegister */\r
+byte CpuMode = HIGH_SPEED; /* Current speed mode */\r
+\r
+\r
+/*\r
+** ===================================================================\r
+** Method : Cpu_Interrupt (bean MC9S12DP256_112)\r
+**\r
+** Description :\r
+** This method is internal. It is used by Processor Expert\r
+** only.\r
+** ===================================================================\r
+*/\r
+#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */\r
+\r
+__interrupt void Cpu_Interrupt(void)\r
+{\r
+}\r
+\r
+#pragma CODE_SEG DEFAULT /* Change code section to DEFAULT. */\r
+\r
+/*\r
+** ===================================================================\r
+** Method : Cpu_DisableInt (bean MC9S12DP256_112)\r
+**\r
+** Description :\r
+** Disable maskable interrupts\r
+** Parameters : None\r
+** Returns : Nothing\r
+** ===================================================================\r
+*/\r
+/*\r
+void Cpu_DisableInt(void)\r
+\r
+** This method is implemented as macro in the header module. **\r
+*/\r
+\r
+/*\r
+** ===================================================================\r
+** Method : Cpu_EnableInt (bean MC9S12DP256_112)\r
+**\r
+** Description :\r
+** Enable maskable interrupts\r
+** Parameters : None\r
+** Returns : Nothing\r
+** ===================================================================\r
+*/\r
+/*\r
+void Cpu_EnableInt(void)\r
+\r
+** This method is implemented as macro in the header module. **\r
+*/\r
+\r
+/*\r
+** ===================================================================\r
+** Method : _EntryPoint (bean MC9S12DP256_112)\r
+**\r
+** Description :\r
+** This method is internal. It is used by Processor Expert\r
+** only.\r
+** ===================================================================\r
+*/\r
+extern void _Startup(void); /* Forward declaration of external startup function declared in file Start12.c */\r
+#define INITRG_ADR 0x0011 /* Register map position register */\r
+#pragma NO_FRAME\r
+#pragma NO_EXIT\r
+void _EntryPoint(void)\r
+{\r
+ /*** ### MC9S12DP256_112 "Cpu" init code ... ***/\r
+ /*** PE initialization code after reset ***/\r
+ /* Initialization of the registers INITRG, INITRM, INITEE is done to protect them to be written accidentally later by the application */\r
+ *(byte*)INITRG_ADR = 0; /* Set the register map position */\r
+ asm nop; /* nop instruction */\r
+ INITRM=1; /* Set the RAM map position */\r
+ INITEE=1; /* Set the EEPROM map position */\r
+ /* MISC: ??=0,??=0,??=0,??=0,EXSTR1=0,EXSTR0=0,ROMHM=0,ROMON=1 */\r
+ MISC=1;\r
+ /* System clock initialization */\r
+ CLKSEL=0;\r
+ CLKSEL_PLLSEL = 0; /* Select clock source from XTAL */\r
+ PLLCTL_PLLON = 0; /* Disable the PLL */\r
+ SYNR = 24; /* Set the multiplier register */\r
+ REFDV = 15; /* Set the divider register */\r
+ PLLCTL = 192;\r
+ PLLCTL_PLLON = 1; /* Enable the PLL */\r
+ while(!CRGFLG_LOCK); /* Wait */\r
+ CLKSEL_PLLSEL = 1; /* Select clock source from PLL */\r
+ /*** End of PE initialization code after reset ***/\r
+\r
+ __asm jmp _Startup; /* Jump to C startup code */\r
+}\r
+\r
+/*\r
+** ===================================================================\r
+** Method : PE_low_level_init (bean MC9S12DP256_112)\r
+**\r
+** Description :\r
+** This method is internal. It is used by Processor Expert\r
+** only.\r
+** ===================================================================\r
+*/\r
+void PE_low_level_init(void)\r
+{\r
+ /* Common initialization of the CPU registers */\r
+/* TSCR1: TEN=0,TSWAI=0,TSFRZ=1 */\r
+ output( TSCR1, input( TSCR1 ) & ~192 | 32 );\r
+/* TCTL2: OM0=0,OL0=0 */\r
+ output( TCTL2, input( TCTL2 ) & ~3 );\r
+/* TCTL1: OM7=0,OL7=0 */\r
+ output( TCTL1, input( TCTL1 ) & ~192 );\r
+/* TIE: C0I=0 */\r
+ output( TIE, input( TIE ) & ~1 );\r
+/* TTOV: TOV0=0 */\r
+ output( TTOV, input( TTOV ) & ~1 );\r
+/* TSCR2: TOI=0,TCRE=1 */\r
+ output( TSCR2, input( TSCR2 ) & ~128 | 8 );\r
+/* TIOS: IOS7=1,IOS0=1 */\r
+ output( TIOS, input( TIOS ) | 129 );\r
+/* PWMCTL: PSWAI=0,PFRZ=0 */\r
+ output( PWMCTL, input( PWMCTL ) & ~12 );\r
+/* PWMSDN: PWMIF=0,PWMIE=0,PWMRSTRT=0,PWMLVL=0,??=0,PWM7IN=0,PWM7INL=0,PWM7ENA=0 */\r
+ output( PWMSDN, 0 );\r
+/* ICSYS: SH37=0,SH26=0,SH15=0,SH04=0,TFMOD=0,PACMX=0,BUFEN=0,LATQ=0 */\r
+ output( ICSYS, 0 );\r
+/* MCCTL: MODMC=1 */\r
+ output( MCCTL, input( MCCTL ) | 64 );\r
+ /* ### MC9S12DP256_112 "Cpu" init code ... */\r
+ /* ### TimerInt "TickTimer" init code ... */\r
+ TickTimer_Init();\r
+ /* ### ByteIO "Byte1" init code ... */\r
+ PORTB = 255; /* Prepare value for output */\r
+ DDRB = 255; /* Set direction to output */\r
+ /* ### Asynchro serial "COM0" init code ... */\r
+ DDRS &= ~1;\r
+ PTS |= 2;\r
+ DDRS |= 2;\r
+ COM0_Init();\r
+ /* Common peripheral initialization - ENABLE */\r
+/* TSCR1: TEN=1 */\r
+ output( TSCR1, input( TSCR1 ) | 128 );\r
+ INTCR_IRQEN = 0; /* Disable the IRQ interrupt. IRQ interrupt is enabled after CPU reset by default. */\r
+ __DI(); /* Disable interrupts */\r
+}\r
+\r
+/* END Cpu. */\r
+\r
+/*\r
+** ###################################################################\r
+**\r
+** This file was created by UNIS Processor Expert 03.33 for \r
+** the Motorola HCS12 series of microcontrollers.\r
+**\r
+** ###################################################################\r
+*/\r
--- /dev/null
+/** ###################################################################\r
+** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.\r
+** Filename : Cpu.H\r
+** Project : RTOSDemo\r
+** Processor : MC9S12DP256BCPV\r
+** Beantype : MC9S12DP256_112\r
+** Version : Bean 01.148, Driver 01.09, CPU db: 2.87.283\r
+** Compiler : Metrowerks HC12 C Compiler\r
+** Date/Time : 14/06/2005, 16:34\r
+** Abstract :\r
+** This bean "MC9S12DP256_112" implements properties, methods,\r
+** and events of the CPU.\r
+** Settings :\r
+**\r
+** Contents :\r
+** EnableInt - void Cpu_EnableInt(void);\r
+** DisableInt - void Cpu_DisableInt(void);\r
+**\r
+** (c) Copyright UNIS, spol. s r.o. 1997-2002\r
+** UNIS, spol. s r.o.\r
+** Jundrovska 33\r
+** 624 00 Brno\r
+** Czech Republic\r
+** http : www.processorexpert.com\r
+** mail : info@processorexpert.com\r
+** ###################################################################*/\r
+\r
+#ifndef __Cpu\r
+#define __Cpu\r
+\r
+/* Active configuration define symbol */\r
+#define PEcfg_112pin 1\r
+\r
+/*Include shared modules, which are used for whole project*/\r
+#include "PE_Types.h"\r
+#include "PE_Error.h"\r
+#include "PE_Const.h"\r
+#include "IO_Map.h"\r
+#include "PE_Timer.h"\r
+\r
+/* MODULE Cpu. */\r
+\r
+\r
+/* Global variables */\r
+extern volatile byte CCR_reg; /* Current CCR reegister */\r
+extern byte CpuMode; /* Current speed mode */\r
+\r
+\r
+\r
+\r
+#define Cpu_DisableInt() __DI() /* Disable interrupts */\r
+/*\r
+** ===================================================================\r
+** Method : Cpu_DisableInt (bean MC9S12DP256_112)\r
+**\r
+** Description :\r
+** Disable maskable interrupts\r
+** Parameters : None\r
+** Returns : Nothing\r
+** ===================================================================\r
+*/\r
+\r
+#define Cpu_EnableInt() __EI() /* Enable interrupts */\r
+/*\r
+** ===================================================================\r
+** Method : Cpu_EnableInt (bean MC9S12DP256_112)\r
+**\r
+** Description :\r
+** Enable maskable interrupts\r
+** Parameters : None\r
+** Returns : Nothing\r
+** ===================================================================\r
+*/\r
+\r
+#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */\r
+\r
+__interrupt void Cpu_Interrupt(void);\r
+/*\r
+** ===================================================================\r
+** Method : Cpu_Interrupt (bean MC9S12DP256_112)\r
+**\r
+** Description :\r
+** This method is internal. It is used by Processor Expert\r
+** only.\r
+** ===================================================================\r
+*/\r
+\r
+#pragma CODE_SEG DEFAULT /* Change code section to DEFAULT. */\r
+\r
+void PE_low_level_init(void);\r
+/*\r
+** ===================================================================\r
+** Method : PE_low_level_init (bean MC9S12DP256_112)\r
+**\r
+** Description :\r
+** This method is internal. It is used by Processor Expert\r
+** only.\r
+** ===================================================================\r
+*/\r
+\r
+/* END Cpu. */\r
+\r
+#endif /* ifndef __Cpu */\r
+/*\r
+** ###################################################################\r
+**\r
+** This file was created by UNIS Processor Expert 03.33 for \r
+** the Motorola HCS12 series of microcontrollers.\r
+**\r
+** ###################################################################\r
+*/\r
--- /dev/null
+/** ###################################################################\r
+** Filename : Events.C\r
+** Project : RTOSDemo\r
+** Processor : MC9S12DP256BCPV\r
+** Beantype : Events\r
+** Version : Driver 01.01\r
+** Compiler : Metrowerks HC12 C Compiler\r
+** Date/Time : 14/06/2005, 16:34\r
+** Abstract :\r
+** This is user's event module.\r
+** Put your event handler code here.\r
+** Settings :\r
+** Contents :\r
+** TickTimer_OnInterrupt - void TickTimer_OnInterrupt(void);\r
+**\r
+** (c) Copyright UNIS, spol. s r.o. 1997-2002\r
+** UNIS, spol. s r.o.\r
+** Jundrovska 33\r
+** 624 00 Brno\r
+** Czech Republic\r
+** http : www.processorexpert.com\r
+** mail : info@processorexpert.com\r
+** ###################################################################*/\r
+/* MODULE Events */\r
+\r
+\r
+/*Including used modules for compilling procedure*/\r
+#include "Cpu.h"\r
+#include "Events.h"\r
+#include "TickTimer.h"\r
+#include "Byte1.h"\r
+#include "COM0.h"\r
+\r
+/*Include shared modules, which are used for whole project*/\r
+#include "PE_Types.h"\r
+#include "PE_Error.h"\r
+#include "PE_Const.h"\r
+#include "IO_Map.h"\r
+#include "PE_Timer.h"\r
+\r
+/*\r
+** ===================================================================\r
+** Event : TickTimer_OnInterrupt (module Events)\r
+**\r
+** From bean : TickTimer [TimerInt]\r
+** Description :\r
+** When a timer interrupt occurs this event is called (only\r
+** when the bean is enabled - "Enable" and the events are\r
+** enabled - "EnableEvent").\r
+** Parameters : None\r
+** Returns : Nothing\r
+** ===================================================================\r
+*/\r
+void TickTimer_OnInterrupt(void)\r
+{\r
+ /* Write your code here ... */\r
+}\r
+\r
+\r
+/*\r
+** ===================================================================\r
+** Event : COM0_OnError (module Events)\r
+**\r
+** From bean : COM0 [AsynchroSerial]\r
+** Description :\r
+** This event is called when a channel error (not the error\r
+** returned by a given method) occurs. The errors can be\r
+** read using <GetError> method.\r
+** Parameters : None\r
+** Returns : Nothing\r
+** ===================================================================\r
+*/\r
+void COM0_OnError(void)\r
+{\r
+ /* Write your code here ... */\r
+}\r
+\r
+/*\r
+** ===================================================================\r
+** Event : COM0_OnRxChar (module Events)\r
+**\r
+** From bean : COM0 [AsynchroSerial]\r
+** Description :\r
+** This event is called after a correct character is\r
+** received. This\r
+** Parameters : None\r
+** Returns : Nothing\r
+** ===================================================================\r
+*/\r
+void COM0_OnRxChar(void)\r
+{\r
+ /* Write your code here ... */\r
+}\r
+\r
+/*\r
+** ===================================================================\r
+** Event : COM0_OnTxChar (module Events)\r
+**\r
+** From bean : COM0 [AsynchroSerial]\r
+** Description :\r
+** This event is called after a character is transmitted.\r
+** Parameters : None\r
+** Returns : Nothing\r
+** ===================================================================\r
+*/\r
+void COM0_OnTxChar(void)\r
+{\r
+ /* Write your code here ... */\r
+}\r
+\r
+/*\r
+** ===================================================================\r
+** Event : COM0_OnFullRxBuf (module Events)\r
+**\r
+** From bean : COM0 [AsynchroSerial]\r
+** Description :\r
+** This event is called when the input buffer is full.\r
+** Parameters : None\r
+** Returns : Nothing\r
+** ===================================================================\r
+*/\r
+void COM0_OnFullRxBuf(void)\r
+{\r
+ /* Write your code here ... */\r
+}\r
+\r
+/*\r
+** ===================================================================\r
+** Event : COM0_OnFreeTxBuf (module Events)\r
+**\r
+** From bean : COM0 [AsynchroSerial]\r
+** Description :\r
+** This event is called after the last character in output\r
+** buffer is transmitted.\r
+** Parameters : None\r
+** Returns : Nothing\r
+** ===================================================================\r
+*/\r
+void COM0_OnFreeTxBuf(void)\r
+{\r
+ /* Write your code here ... */\r
+}\r
+\r
+/* END Events */\r
+\r
+/*\r
+** ###################################################################\r
+**\r
+** This file was created by UNIS Processor Expert 03.33 for \r
+** the Motorola HCS12 series of microcontrollers.\r
+**\r
+** ###################################################################\r
+*/\r
--- /dev/null
+/** ###################################################################\r
+** Filename : Events.H\r
+** Project : RTOSDemo\r
+** Processor : MC9S12DP256BCPV\r
+** Beantype : Events\r
+** Version : Driver 01.01\r
+** Compiler : Metrowerks HC12 C Compiler\r
+** Date/Time : 14/06/2005, 16:34\r
+** Abstract :\r
+** This is user's event module.\r
+** Put your event handler code here.\r
+** Settings :\r
+** Contents :\r
+** TickTimer_OnInterrupt - void TickTimer_OnInterrupt(void);\r
+**\r
+** (c) Copyright UNIS, spol. s r.o. 1997-2002\r
+** UNIS, spol. s r.o.\r
+** Jundrovska 33\r
+** 624 00 Brno\r
+** Czech Republic\r
+** http : www.processorexpert.com\r
+** mail : info@processorexpert.com\r
+** ###################################################################*/\r
+\r
+#ifndef __Events_H\r
+#define __Events_H\r
+/* MODULE Events */\r
+\r
+#include "PE_Types.h"\r
+#include "PE_Error.h"\r
+#include "PE_Const.h"\r
+#include "IO_Map.h"\r
+#include "PE_Timer.h"\r
+\r
+void TickTimer_OnInterrupt(void);\r
+/*\r
+** ===================================================================\r
+** Event : TickTimer_OnInterrupt (module Events)\r
+**\r
+** From bean : TickTimer [TimerInt]\r
+** Description :\r
+** When a timer interrupt occurs this event is called (only\r
+** when the bean is enabled - "Enable" and the events are\r
+** enabled - "EnableEvent").\r
+** Parameters : None\r
+** Returns : Nothing\r
+** ===================================================================\r
+*/\r
+\r
+\r
+void COM0_OnError(void);\r
+/*\r
+** ===================================================================\r
+** Event : COM0_OnError (module Events)\r
+**\r
+** From bean : COM0 [AsynchroSerial]\r
+** Description :\r
+** This event is called when a channel error (not the error\r
+** returned by a given method) occurs. The errors can be\r
+** read using <GetError> method.\r
+** Parameters : None\r
+** Returns : Nothing\r
+** ===================================================================\r
+*/\r
+\r
+void COM0_OnRxChar(void);\r
+/*\r
+** ===================================================================\r
+** Event : COM0_OnRxChar (module Events)\r
+**\r
+** From bean : COM0 [AsynchroSerial]\r
+** Description :\r
+** This event is called after a correct character is\r
+** received. This\r
+** Parameters : None\r
+** Returns : Nothing\r
+** ===================================================================\r
+*/\r
+\r
+void COM0_OnTxChar(void);\r
+/*\r
+** ===================================================================\r
+** Event : COM0_OnTxChar (module Events)\r
+**\r
+** From bean : COM0 [AsynchroSerial]\r
+** Description :\r
+** This event is called after a character is transmitted.\r
+** Parameters : None\r
+** Returns : Nothing\r
+** ===================================================================\r
+*/\r
+\r
+void COM0_OnFullRxBuf(void);\r
+/*\r
+** ===================================================================\r
+** Event : COM0_OnFullRxBuf (module Events)\r
+**\r
+** From bean : COM0 [AsynchroSerial]\r
+** Description :\r
+** This event is called when the input buffer is full.\r
+** Parameters : None\r
+** Returns : Nothing\r
+** ===================================================================\r
+*/\r
+\r
+void COM0_OnFreeTxBuf(void);\r
+/*\r
+** ===================================================================\r
+** Event : COM0_OnFreeTxBuf (module Events)\r
+**\r
+** From bean : COM0 [AsynchroSerial]\r
+** Description :\r
+** This event is called after the last character in output\r
+** buffer is transmitted.\r
+** Parameters : None\r
+** Returns : Nothing\r
+** ===================================================================\r
+*/\r
+\r
+/* END Events */\r
+#endif /* __Events_H*/\r
+\r
+/*\r
+** ###################################################################\r
+**\r
+** This file was created by UNIS Processor Expert 03.33 for \r
+** the Motorola HCS12 series of microcontrollers.\r
+**\r
+** ###################################################################\r
+*/\r
--- /dev/null
+/** ###################################################################\r
+** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.\r
+** Filename : IO_Map.C\r
+** Project : RTOSDemo\r
+** Processor : MC9S12DP256BCPV\r
+** Beantype : IO_Map\r
+** Version : Driver 01.01\r
+** Compiler : Metrowerks HC12 C Compiler\r
+** Date/Time : 13/06/2005, 20:14\r
+** Abstract :\r
+** This bean "IO_Map" implements an IO devices mapping.\r
+** Settings :\r
+**\r
+** Contents :\r
+** No public methods\r
+**\r
+** (c) Copyright UNIS, spol. s r.o. 1997-2002\r
+** UNIS, spol. s r.o.\r
+** Jundrovska 33\r
+** 624 00 Brno\r
+** Czech Republic\r
+** http : www.processorexpert.com\r
+** mail : info@processorexpert.com\r
+** ###################################################################*/\r
+/* Based on CPU DB MC9S12DP256_112, version 2.87.278 */\r
+#include "PE_types.h"\r
+#include "IO_Map.h"\r
+\r
+volatile ARMCOPSTR _ARMCOP; /* CRG COP Timer Arm/Reset Register */\r
+volatile ATD0DIENSTR _ATD0DIEN; /* ATD 0 Input Enable Mask Register */\r
+volatile ATD0STAT0STR _ATD0STAT0; /* ATD 0 Status Register 0 */\r
+volatile ATD0STAT1STR _ATD0STAT1; /* ATD 0 Status Register 1 */\r
+volatile ATD1DIENSTR _ATD1DIEN; /* ATD 1 Input Enable Mask Register */\r
+volatile ATD1STAT0STR _ATD1STAT0; /* ATD 1 Status Register 0 */\r
+volatile ATD1STAT1STR _ATD1STAT1; /* ATD 1 Status Register 1 */\r
+volatile BDMCCRSTR _BDMCCR; /* BDM CCR Holding Register */\r
+volatile BDMINRSTR _BDMINR; /* BDM Internal Register Position Register */\r
+volatile BDMSTSSTR _BDMSTS; /* BDM Status Register */\r
+volatile BKP0HSTR _BKP0H; /* First Address High Byte Breakpoint Register */\r
+volatile BKP0LSTR _BKP0L; /* First Address Low Byte Breakpoint Register */\r
+volatile BKP0XSTR _BKP0X; /* First Address Memory Expansion Breakpoint Register */\r
+volatile BKP1HSTR _BKP1H; /* Data (Second Address) High Byte Breakpoint Register */\r
+volatile BKP1LSTR _BKP1L; /* Data (Second Address) Low Byte Breakpoint Register */\r
+volatile BKP1XSTR _BKP1X; /* Second Address Memory Expansion Breakpoint Register */\r
+volatile BKPCT0STR _BKPCT0; /* Breakpoint Control Register 0 */\r
+volatile BKPCT1STR _BKPCT1; /* Breakpoint Control Register 1 */\r
+volatile CAN0BTR0STR _CAN0BTR0; /* MSCAN 0 Bus Timing Register 0 */\r
+volatile CAN0BTR1STR _CAN0BTR1; /* MSCAN 0 Bus Timing Register 1 */\r
+volatile CAN0CTL0STR _CAN0CTL0; /* MSCAN 0 Control 0 Register */\r
+volatile CAN0CTL1STR _CAN0CTL1; /* MSCAN 0 Control 1 Register */\r
+volatile CAN0IDACSTR _CAN0IDAC; /* MSCAN 0 Identifier Acceptance Control Register */\r
+volatile CAN0IDAR0STR _CAN0IDAR0; /* MSCAN 0 Identifier Acceptance Register 0 */\r
+volatile CAN0IDAR1STR _CAN0IDAR1; /* MSCAN 0 Identifier Acceptance Register 1 */\r
+volatile CAN0IDAR2STR _CAN0IDAR2; /* MSCAN 0 Identifier Acceptance Register 2 */\r
+volatile CAN0IDAR3STR _CAN0IDAR3; /* MSCAN 0 Identifier Acceptance Register 3 */\r
+volatile CAN0IDAR4STR _CAN0IDAR4; /* MSCAN 0 Identifier Acceptance Register 4 */\r
+volatile CAN0IDAR5STR _CAN0IDAR5; /* MSCAN 0 Identifier Acceptance Register 5 */\r
+volatile CAN0IDAR6STR _CAN0IDAR6; /* MSCAN 0 Identifier Acceptance Register 6 */\r
+volatile CAN0IDAR7STR _CAN0IDAR7; /* MSCAN 0 Identifier Acceptance Register 7 */\r
+volatile CAN0IDMR0STR _CAN0IDMR0; /* MSCAN 0 Identifier Mask Register 0 */\r
+volatile CAN0IDMR1STR _CAN0IDMR1; /* MSCAN 0 Identifier Mask Register 1 */\r
+volatile CAN0IDMR2STR _CAN0IDMR2; /* MSCAN 0 Identifier Mask Register 2 */\r
+volatile CAN0IDMR3STR _CAN0IDMR3; /* MSCAN 0 Identifier Mask Register 3 */\r
+volatile CAN0IDMR4STR _CAN0IDMR4; /* MSCAN 0 Identifier Mask Register 4 */\r
+volatile CAN0IDMR5STR _CAN0IDMR5; /* MSCAN 0 Identifier Mask Register 5 */\r
+volatile CAN0IDMR6STR _CAN0IDMR6; /* MSCAN 0 Identifier Mask Register 6 */\r
+volatile CAN0IDMR7STR _CAN0IDMR7; /* MSCAN 0 Identifier Mask Register 7 */\r
+volatile CAN0RFLGSTR _CAN0RFLG; /* MSCAN 0 Receiver Flag Register */\r
+volatile CAN0RIERSTR _CAN0RIER; /* MSCAN 0 Receiver Interrupt Enable Register */\r
+volatile CAN0RXDLRSTR _CAN0RXDLR; /* MSCAN 0 Receive Data Length Register */\r
+volatile CAN0RXDSR0STR _CAN0RXDSR0; /* MSCAN 0 Receive Data Segment Register 0 */\r
+volatile CAN0RXDSR1STR _CAN0RXDSR1; /* MSCAN 0 Receive Data Segment Register 1 */\r
+volatile CAN0RXDSR2STR _CAN0RXDSR2; /* MSCAN 0 Receive Data Segment Register 2 */\r
+volatile CAN0RXDSR3STR _CAN0RXDSR3; /* MSCAN 0 Receive Data Segment Register 3 */\r
+volatile CAN0RXDSR4STR _CAN0RXDSR4; /* MSCAN 0 Receive Data Segment Register 4 */\r
+volatile CAN0RXDSR5STR _CAN0RXDSR5; /* MSCAN 0 Receive Data Segment Register 5 */\r
+volatile CAN0RXDSR6STR _CAN0RXDSR6; /* MSCAN 0 Receive Data Segment Register 6 */\r
+volatile CAN0RXDSR7STR _CAN0RXDSR7; /* MSCAN 0 Receive Data Segment Register 7 */\r
+volatile CAN0RXERRSTR _CAN0RXERR; /* MSCAN 0 Receive Error Counter Register */\r
+volatile CAN0RXIDR0STR _CAN0RXIDR0; /* MSCAN 0 Receive Identifier Register 0 */\r
+volatile CAN0RXIDR1STR _CAN0RXIDR1; /* MSCAN 0 Receive Identifier Register 1 */\r
+volatile CAN0RXIDR2STR _CAN0RXIDR2; /* MSCAN 0 Receive Identifier Register 2 */\r
+volatile CAN0RXIDR3STR _CAN0RXIDR3; /* MSCAN 0 Receive Identifier Register 3 */\r
+volatile CAN0TAAKSTR _CAN0TAAK; /* MSCAN 0 Transmitter Message Abort Control */\r
+volatile CAN0TARQSTR _CAN0TARQ; /* MSCAN 0 Transmitter Message Abort Request */\r
+volatile CAN0TBSELSTR _CAN0TBSEL; /* MSCAN 0 Transmit Buffer Selection */\r
+volatile CAN0TFLGSTR _CAN0TFLG; /* MSCAN 0 Transmitter Flag Register */\r
+volatile CAN0TIERSTR _CAN0TIER; /* MSCAN 0 Transmitter Interrupt Enable Register */\r
+volatile CAN0TXDLRSTR _CAN0TXDLR; /* MSCAN 0 Transmit Data Length Register */\r
+volatile CAN0TXDSR0STR _CAN0TXDSR0; /* MSCAN 0 Transmit Data Segment Register 0 */\r
+volatile CAN0TXDSR1STR _CAN0TXDSR1; /* MSCAN 0 Transmit Data Segment Register 1 */\r
+volatile CAN0TXDSR2STR _CAN0TXDSR2; /* MSCAN 0 Transmit Data Segment Register 2 */\r
+volatile CAN0TXDSR3STR _CAN0TXDSR3; /* MSCAN 0 Transmit Data Segment Register 3 */\r
+volatile CAN0TXDSR4STR _CAN0TXDSR4; /* MSCAN 0 Transmit Data Segment Register 4 */\r
+volatile CAN0TXDSR5STR _CAN0TXDSR5; /* MSCAN 0 Transmit Data Segment Register 5 */\r
+volatile CAN0TXDSR6STR _CAN0TXDSR6; /* MSCAN 0 Transmit Data Segment Register 6 */\r
+volatile CAN0TXDSR7STR _CAN0TXDSR7; /* MSCAN 0 Transmit Data Segment Register 7 */\r
+volatile CAN0TXERRSTR _CAN0TXERR; /* MSCAN 0 Transmit Error Counter Register */\r
+volatile CAN0TXIDR0STR _CAN0TXIDR0; /* MSCAN 0 Transmit Identifier Register 0 */\r
+volatile CAN0TXIDR1STR _CAN0TXIDR1; /* MSCAN 0 Transmit Identifier Register 1 */\r
+volatile CAN0TXIDR2STR _CAN0TXIDR2; /* MSCAN 0 Transmit Identifier Register 2 */\r
+volatile CAN0TXIDR3STR _CAN0TXIDR3; /* MSCAN 0 Transmit Identifier Register 3 */\r
+volatile CAN0TXTBPRSTR _CAN0TXTBPR; /* MSCAN 0 Transmit Buffer Priority */\r
+volatile CAN1BTR0STR _CAN1BTR0; /* MSCAN 1 Bus Timing Register 0 */\r
+volatile CAN1BTR1STR _CAN1BTR1; /* MSCAN 1 Bus Timing Register 1 */\r
+volatile CAN1CTL0STR _CAN1CTL0; /* MSCAN 1 Control 0 Register */\r
+volatile CAN1CTL1STR _CAN1CTL1; /* MSCAN 1 Control 1 Register */\r
+volatile CAN1IDACSTR _CAN1IDAC; /* MSCAN 1 Identifier Acceptance Control Register */\r
+volatile CAN1IDAR0STR _CAN1IDAR0; /* MSCAN 1 Identifier Acceptance Register 0 */\r
+volatile CAN1IDAR1STR _CAN1IDAR1; /* MSCAN 1 Identifier Acceptance Register 1 */\r
+volatile CAN1IDAR2STR _CAN1IDAR2; /* MSCAN 1 Identifier Acceptance Register 2 */\r
+volatile CAN1IDAR3STR _CAN1IDAR3; /* MSCAN 1 Identifier Acceptance Register 3 */\r
+volatile CAN1IDAR4STR _CAN1IDAR4; /* MSCAN 1 Identifier Acceptance Register 4 */\r
+volatile CAN1IDAR5STR _CAN1IDAR5; /* MSCAN 1 Identifier Acceptance Register 5 */\r
+volatile CAN1IDAR6STR _CAN1IDAR6; /* MSCAN 1 Identifier Acceptance Register 6 */\r
+volatile CAN1IDAR7STR _CAN1IDAR7; /* MSCAN 1 Identifier Acceptance Register 7 */\r
+volatile CAN1IDMR0STR _CAN1IDMR0; /* MSCAN 1 Identifier Mask Register 0 */\r
+volatile CAN1IDMR1STR _CAN1IDMR1; /* MSCAN 1 Identifier Mask Register 1 */\r
+volatile CAN1IDMR2STR _CAN1IDMR2; /* MSCAN 1 Identifier Mask Register 2 */\r
+volatile CAN1IDMR3STR _CAN1IDMR3; /* MSCAN 1 Identifier Mask Register 3 */\r
+volatile CAN1IDMR4STR _CAN1IDMR4; /* MSCAN 1 Identifier Mask Register 4 */\r
+volatile CAN1IDMR5STR _CAN1IDMR5; /* MSCAN 1 Identifier Mask Register 5 */\r
+volatile CAN1IDMR6STR _CAN1IDMR6; /* MSCAN 1 Identifier Mask Register 6 */\r
+volatile CAN1IDMR7STR _CAN1IDMR7; /* MSCAN 1 Identifier Mask Register 7 */\r
+volatile CAN1RFLGSTR _CAN1RFLG; /* MSCAN 1 Receiver Flag Register */\r
+volatile CAN1RIERSTR _CAN1RIER; /* MSCAN 1 Receiver Interrupt Enable Register */\r
+volatile CAN1RXDLRSTR _CAN1RXDLR; /* MSCAN 1 Receive Data Length Register */\r
+volatile CAN1RXDSR0STR _CAN1RXDSR0; /* MSCAN 1 Receive Data Segment Register 0 */\r
+volatile CAN1RXDSR1STR _CAN1RXDSR1; /* MSCAN 1 Receive Data Segment Register 1 */\r
+volatile CAN1RXDSR2STR _CAN1RXDSR2; /* MSCAN 1 Receive Data Segment Register 2 */\r
+volatile CAN1RXDSR3STR _CAN1RXDSR3; /* MSCAN 1 Receive Data Segment Register 3 */\r
+volatile CAN1RXDSR4STR _CAN1RXDSR4; /* MSCAN 1 Receive Data Segment Register 4 */\r
+volatile CAN1RXDSR5STR _CAN1RXDSR5; /* MSCAN 1 Receive Data Segment Register 5 */\r
+volatile CAN1RXDSR6STR _CAN1RXDSR6; /* MSCAN 1 Receive Data Segment Register 6 */\r
+volatile CAN1RXDSR7STR _CAN1RXDSR7; /* MSCAN 1 Receive Data Segment Register 7 */\r
+volatile CAN1RXERRSTR _CAN1RXERR; /* MSCAN 1 Receive Error Counter Register */\r
+volatile CAN1RXIDR0STR _CAN1RXIDR0; /* MSCAN 1 Receive Identifier Register 0 */\r
+volatile CAN1RXIDR1STR _CAN1RXIDR1; /* MSCAN 1 Receive Identifier Register 1 */\r
+volatile CAN1RXIDR2STR _CAN1RXIDR2; /* MSCAN 1 Receive Identifier Register 2 */\r
+volatile CAN1RXIDR3STR _CAN1RXIDR3; /* MSCAN 1 Receive Identifier Register 3 */\r
+volatile CAN1TAAKSTR _CAN1TAAK; /* MSCAN 1 Transmitter Message Abort Control */\r
+volatile CAN1TARQSTR _CAN1TARQ; /* MSCAN 1 Transmitter Message Abort Request */\r
+volatile CAN1TBSELSTR _CAN1TBSEL; /* MSCAN 1 Transmit Buffer Selection */\r
+volatile CAN1TFLGSTR _CAN1TFLG; /* MSCAN 1 Transmitter Flag Register */\r
+volatile CAN1TIERSTR _CAN1TIER; /* MSCAN 1 Transmitter Interrupt Enable Register */\r
+volatile CAN1TXDLRSTR _CAN1TXDLR; /* MSCAN 1 Transmit Data Length Register */\r
+volatile CAN1TXDSR0STR _CAN1TXDSR0; /* MSCAN 1 Transmit Data Segment Register 0 */\r
+volatile CAN1TXDSR1STR _CAN1TXDSR1; /* MSCAN 1 Transmit Data Segment Register 1 */\r
+volatile CAN1TXDSR2STR _CAN1TXDSR2; /* MSCAN 1 Transmit Data Segment Register 2 */\r
+volatile CAN1TXDSR3STR _CAN1TXDSR3; /* MSCAN 1 Transmit Data Segment Register 3 */\r
+volatile CAN1TXDSR4STR _CAN1TXDSR4; /* MSCAN 1 Transmit Data Segment Register 4 */\r
+volatile CAN1TXDSR5STR _CAN1TXDSR5; /* MSCAN 1 Transmit Data Segment Register 5 */\r
+volatile CAN1TXDSR6STR _CAN1TXDSR6; /* MSCAN 1 Transmit Data Segment Register 6 */\r
+volatile CAN1TXDSR7STR _CAN1TXDSR7; /* MSCAN 1 Transmit Data Segment Register 7 */\r
+volatile CAN1TXERRSTR _CAN1TXERR; /* MSCAN 1 Transmit Error Counter Register */\r
+volatile CAN1TXIDR0STR _CAN1TXIDR0; /* MSCAN 1 Transmit Identifier Register 0 */\r
+volatile CAN1TXIDR1STR _CAN1TXIDR1; /* MSCAN 1 Transmit Identifier Register 1 */\r
+volatile CAN1TXIDR2STR _CAN1TXIDR2; /* MSCAN 1 Transmit Identifier Register 2 */\r
+volatile CAN1TXIDR3STR _CAN1TXIDR3; /* MSCAN 1 Transmit Identifier Register 3 */\r
+volatile CAN1TXTBPRSTR _CAN1TXTBPR; /* MSCAN 1 Transmit Buffer Priority */\r
+volatile CAN2BTR0STR _CAN2BTR0; /* MSCAN 2 Bus Timing Register 0 */\r
+volatile CAN2BTR1STR _CAN2BTR1; /* MSCAN 2 Bus Timing Register 1 */\r
+volatile CAN2CTL0STR _CAN2CTL0; /* MSCAN 2 Control 0 Register */\r
+volatile CAN2CTL1STR _CAN2CTL1; /* MSCAN 2 Control 1 Register */\r
+volatile CAN2IDACSTR _CAN2IDAC; /* MSCAN 2 Identifier Acceptance Control Register */\r
+volatile CAN2IDAR0STR _CAN2IDAR0; /* MSCAN 2 Identifier Acceptance Register 0 */\r
+volatile CAN2IDAR1STR _CAN2IDAR1; /* MSCAN 2 Identifier Acceptance Register 1 */\r
+volatile CAN2IDAR2STR _CAN2IDAR2; /* MSCAN 2 Identifier Acceptance Register 2 */\r
+volatile CAN2IDAR3STR _CAN2IDAR3; /* MSCAN 2 Identifier Acceptance Register 3 */\r
+volatile CAN2IDAR4STR _CAN2IDAR4; /* MSCAN 2 Identifier Acceptance Register 4 */\r
+volatile CAN2IDAR5STR _CAN2IDAR5; /* MSCAN 2 Identifier Acceptance Register 5 */\r
+volatile CAN2IDAR6STR _CAN2IDAR6; /* MSCAN 2 Identifier Acceptance Register 6 */\r
+volatile CAN2IDAR7STR _CAN2IDAR7; /* MSCAN 2 Identifier Acceptance Register 7 */\r
+volatile CAN2IDMR0STR _CAN2IDMR0; /* MSCAN 2 Identifier Mask Register 0 */\r
+volatile CAN2IDMR1STR _CAN2IDMR1; /* MSCAN 2 Identifier Mask Register 1 */\r
+volatile CAN2IDMR2STR _CAN2IDMR2; /* MSCAN 2 Identifier Mask Register 2 */\r
+volatile CAN2IDMR3STR _CAN2IDMR3; /* MSCAN 2 Identifier Mask Register 3 */\r
+volatile CAN2IDMR4STR _CAN2IDMR4; /* MSCAN 2 Identifier Mask Register 4 */\r
+volatile CAN2IDMR5STR _CAN2IDMR5; /* MSCAN 2 Identifier Mask Register 5 */\r
+volatile CAN2IDMR6STR _CAN2IDMR6; /* MSCAN 2 Identifier Mask Register 6 */\r
+volatile CAN2IDMR7STR _CAN2IDMR7; /* MSCAN 2 Identifier Mask Register 7 */\r
+volatile CAN2RFLGSTR _CAN2RFLG; /* MSCAN 2 Receiver Flag Register */\r
+volatile CAN2RIERSTR _CAN2RIER; /* MSCAN 2 Receiver Interrupt Enable Register */\r
+volatile CAN2RXDLRSTR _CAN2RXDLR; /* MSCAN 2 Receive Data Length Register */\r
+volatile CAN2RXDSR0STR _CAN2RXDSR0; /* MSCAN 2 Receive Data Segment Register 0 */\r
+volatile CAN2RXDSR1STR _CAN2RXDSR1; /* MSCAN 2 Receive Data Segment Register 1 */\r
+volatile CAN2RXDSR2STR _CAN2RXDSR2; /* MSCAN 2 Receive Data Segment Register 2 */\r
+volatile CAN2RXDSR3STR _CAN2RXDSR3; /* MSCAN 2 Receive Data Segment Register 3 */\r
+volatile CAN2RXDSR4STR _CAN2RXDSR4; /* MSCAN 2 Receive Data Segment Register 4 */\r
+volatile CAN2RXDSR5STR _CAN2RXDSR5; /* MSCAN 2 Receive Data Segment Register 5 */\r
+volatile CAN2RXDSR6STR _CAN2RXDSR6; /* MSCAN 2 Receive Data Segment Register 6 */\r
+volatile CAN2RXDSR7STR _CAN2RXDSR7; /* MSCAN 2 Receive Data Segment Register 7 */\r
+volatile CAN2RXERRSTR _CAN2RXERR; /* MSCAN 2 Receive Error Counter Register */\r
+volatile CAN2RXIDR0STR _CAN2RXIDR0; /* MSCAN 2 Receive Identifier Register 0 */\r
+volatile CAN2RXIDR1STR _CAN2RXIDR1; /* MSCAN 2 Receive Identifier Register 1 */\r
+volatile CAN2RXIDR2STR _CAN2RXIDR2; /* MSCAN 2 Receive Identifier Register 2 */\r
+volatile CAN2RXIDR3STR _CAN2RXIDR3; /* MSCAN 2 Receive Identifier Register 3 */\r
+volatile CAN2TAAKSTR _CAN2TAAK; /* MSCAN 2 Transmitter Message Abort Control */\r
+volatile CAN2TARQSTR _CAN2TARQ; /* MSCAN 2 Transmitter Message Abort Request */\r
+volatile CAN2TBSELSTR _CAN2TBSEL; /* MSCAN 2 Transmit Buffer Selection */\r
+volatile CAN2TFLGSTR _CAN2TFLG; /* MSCAN 2 Transmitter Flag Register */\r
+volatile CAN2TIERSTR _CAN2TIER; /* MSCAN 2 Transmitter Interrupt Enable Register */\r
+volatile CAN2TXDLRSTR _CAN2TXDLR; /* MSCAN 2 Transmit Data Length Register */\r
+volatile CAN2TXDSR0STR _CAN2TXDSR0; /* MSCAN 2 Transmit Data Segment Register 0 */\r
+volatile CAN2TXDSR1STR _CAN2TXDSR1; /* MSCAN 2 Transmit Data Segment Register 1 */\r
+volatile CAN2TXDSR2STR _CAN2TXDSR2; /* MSCAN 2 Transmit Data Segment Register 2 */\r
+volatile CAN2TXDSR3STR _CAN2TXDSR3; /* MSCAN 2 Transmit Data Segment Register 3 */\r
+volatile CAN2TXDSR4STR _CAN2TXDSR4; /* MSCAN 2 Transmit Data Segment Register 4 */\r
+volatile CAN2TXDSR5STR _CAN2TXDSR5; /* MSCAN 2 Transmit Data Segment Register 5 */\r
+volatile CAN2TXDSR6STR _CAN2TXDSR6; /* MSCAN 2 Transmit Data Segment Register 6 */\r
+volatile CAN2TXDSR7STR _CAN2TXDSR7; /* MSCAN 2 Transmit Data Segment Register 7 */\r
+volatile CAN2TXERRSTR _CAN2TXERR; /* MSCAN 2 Transmit Error Counter Register */\r
+volatile CAN2TXIDR0STR _CAN2TXIDR0; /* MSCAN 2 Transmit Identifier Register 0 */\r
+volatile CAN2TXIDR1STR _CAN2TXIDR1; /* MSCAN 2 Transmit Identifier Register 1 */\r
+volatile CAN2TXIDR2STR _CAN2TXIDR2; /* MSCAN 2 Transmit Identifier Register 2 */\r
+volatile CAN2TXIDR3STR _CAN2TXIDR3; /* MSCAN 2 Transmit Identifier Register 3 */\r
+volatile CAN2TXTBPRSTR _CAN2TXTBPR; /* MSCAN 2 Transmit Buffer Priority */\r
+volatile CAN3BTR0STR _CAN3BTR0; /* MSCAN 3 Bus Timing Register 0 */\r
+volatile CAN3BTR1STR _CAN3BTR1; /* MSCAN 3 Bus Timing Register 1 */\r
+volatile CAN3CTL0STR _CAN3CTL0; /* MSCAN 3 Control 0 Register */\r
+volatile CAN3CTL1STR _CAN3CTL1; /* MSCAN 3 Control 1 Register */\r
+volatile CAN3IDACSTR _CAN3IDAC; /* MSCAN 3 Identifier Acceptance Control Register */\r
+volatile CAN3IDAR0STR _CAN3IDAR0; /* MSCAN 3 Identifier Acceptance Register 0 */\r
+volatile CAN3IDAR1STR _CAN3IDAR1; /* MSCAN 3 Identifier Acceptance Register 1 */\r
+volatile CAN3IDAR2STR _CAN3IDAR2; /* MSCAN 3 Identifier Acceptance Register 2 */\r
+volatile CAN3IDAR3STR _CAN3IDAR3; /* MSCAN 3 Identifier Acceptance Register 3 */\r
+volatile CAN3IDAR4STR _CAN3IDAR4; /* MSCAN 3 Identifier Acceptance Register 4 */\r
+volatile CAN3IDAR5STR _CAN3IDAR5; /* MSCAN 3 Identifier Acceptance Register 5 */\r
+volatile CAN3IDAR6STR _CAN3IDAR6; /* MSCAN 3 Identifier Acceptance Register 6 */\r
+volatile CAN3IDAR7STR _CAN3IDAR7; /* MSCAN 3 Identifier Acceptance Register 7 */\r
+volatile CAN3IDMR0STR _CAN3IDMR0; /* MSCAN 3 Identifier Mask Register 0 */\r
+volatile CAN3IDMR1STR _CAN3IDMR1; /* MSCAN 3 Identifier Mask Register 1 */\r
+volatile CAN3IDMR2STR _CAN3IDMR2; /* MSCAN 3 Identifier Mask Register 2 */\r
+volatile CAN3IDMR3STR _CAN3IDMR3; /* MSCAN 3 Identifier Mask Register 3 */\r
+volatile CAN3IDMR4STR _CAN3IDMR4; /* MSCAN 3 Identifier Mask Register 4 */\r
+volatile CAN3IDMR5STR _CAN3IDMR5; /* MSCAN 3 Identifier Mask Register 5 */\r
+volatile CAN3IDMR6STR _CAN3IDMR6; /* MSCAN 3 Identifier Mask Register 6 */\r
+volatile CAN3IDMR7STR _CAN3IDMR7; /* MSCAN 3 Identifier Mask Register 7 */\r
+volatile CAN3RFLGSTR _CAN3RFLG; /* MSCAN 3 Receiver Flag Register */\r
+volatile CAN3RIERSTR _CAN3RIER; /* MSCAN 3 Receiver Interrupt Enable Register */\r
+volatile CAN3RXDLRSTR _CAN3RXDLR; /* MSCAN 3 Receive Data Length Register */\r
+volatile CAN3RXDSR0STR _CAN3RXDSR0; /* MSCAN 3 Receive Data Segment Register 0 */\r
+volatile CAN3RXDSR1STR _CAN3RXDSR1; /* MSCAN 3 Receive Data Segment Register 1 */\r
+volatile CAN3RXDSR2STR _CAN3RXDSR2; /* MSCAN 3 Receive Data Segment Register 2 */\r
+volatile CAN3RXDSR3STR _CAN3RXDSR3; /* MSCAN 3 Receive Data Segment Register 3 */\r
+volatile CAN3RXDSR4STR _CAN3RXDSR4; /* MSCAN 3 Receive Data Segment Register 4 */\r
+volatile CAN3RXDSR5STR _CAN3RXDSR5; /* MSCAN 3 Receive Data Segment Register 5 */\r
+volatile CAN3RXDSR6STR _CAN3RXDSR6; /* MSCAN 3 Receive Data Segment Register 6 */\r
+volatile CAN3RXDSR7STR _CAN3RXDSR7; /* MSCAN 3 Receive Data Segment Register 7 */\r
+volatile CAN3RXERRSTR _CAN3RXERR; /* MSCAN 3 Receive Error Counter Register */\r
+volatile CAN3RXIDR0STR _CAN3RXIDR0; /* MSCAN 3 Receive Identifier Register 0 */\r
+volatile CAN3RXIDR1STR _CAN3RXIDR1; /* MSCAN 3 Receive Identifier Register 1 */\r
+volatile CAN3RXIDR2STR _CAN3RXIDR2; /* MSCAN 3 Receive Identifier Register 2 */\r
+volatile CAN3RXIDR3STR _CAN3RXIDR3; /* MSCAN 3 Receive Identifier Register 3 */\r
+volatile CAN3TAAKSTR _CAN3TAAK; /* MSCAN 3 Transmitter Message Abort Control */\r
+volatile CAN3TARQSTR _CAN3TARQ; /* MSCAN 3 Transmitter Message Abort Request */\r
+volatile CAN3TBSELSTR _CAN3TBSEL; /* MSCAN 3 Transmit Buffer Selection */\r
+volatile CAN3TFLGSTR _CAN3TFLG; /* MSCAN 3 Transmitter Flag Register */\r
+volatile CAN3TIERSTR _CAN3TIER; /* MSCAN 3 Transmitter Interrupt Enable Register */\r
+volatile CAN3TXDLRSTR _CAN3TXDLR; /* MSCAN 3 Transmit Data Length Register */\r
+volatile CAN3TXDSR0STR _CAN3TXDSR0; /* MSCAN 3 Transmit Data Segment Register 0 */\r
+volatile CAN3TXDSR1STR _CAN3TXDSR1; /* MSCAN 3 Transmit Data Segment Register 1 */\r
+volatile CAN3TXDSR2STR _CAN3TXDSR2; /* MSCAN 3 Transmit Data Segment Register 2 */\r
+volatile CAN3TXDSR3STR _CAN3TXDSR3; /* MSCAN 3 Transmit Data Segment Register 3 */\r
+volatile CAN3TXDSR4STR _CAN3TXDSR4; /* MSCAN 3 Transmit Data Segment Register 4 */\r
+volatile CAN3TXDSR5STR _CAN3TXDSR5; /* MSCAN 3 Transmit Data Segment Register 5 */\r
+volatile CAN3TXDSR6STR _CAN3TXDSR6; /* MSCAN 3 Transmit Data Segment Register 6 */\r
+volatile CAN3TXDSR7STR _CAN3TXDSR7; /* MSCAN 3 Transmit Data Segment Register 7 */\r
+volatile CAN3TXERRSTR _CAN3TXERR; /* MSCAN 3 Transmit Error Counter Register */\r
+volatile CAN3TXIDR0STR _CAN3TXIDR0; /* MSCAN 3 Transmit Identifier Register 0 */\r
+volatile CAN3TXIDR1STR _CAN3TXIDR1; /* MSCAN 3 Transmit Identifier Register 1 */\r
+volatile CAN3TXIDR2STR _CAN3TXIDR2; /* MSCAN 3 Transmit Identifier Register 2 */\r
+volatile CAN3TXIDR3STR _CAN3TXIDR3; /* MSCAN 3 Transmit Identifier Register 3 */\r
+volatile CAN3TXTBPRSTR _CAN3TXTBPR; /* MSCAN 3 Transmit Buffer Priority */\r
+volatile CAN4BTR0STR _CAN4BTR0; /* MSCAN4 Bus Timing Register 0 */\r
+volatile CAN4BTR1STR _CAN4BTR1; /* MSCAN4 Bus Timing Register 1 */\r
+volatile CAN4CTL0STR _CAN4CTL0; /* MSCAN4 Control 0 Register */\r
+volatile CAN4CTL1STR _CAN4CTL1; /* MSCAN4 Control 1 Register */\r
+volatile CAN4IDACSTR _CAN4IDAC; /* MSCAN4 Identifier Acceptance Control Register */\r
+volatile CAN4IDAR0STR _CAN4IDAR0; /* MSCAN4 Identifier Acceptance Register 0 */\r
+volatile CAN4IDAR1STR _CAN4IDAR1; /* MSCAN4 Identifier Acceptance Register 1 */\r
+volatile CAN4IDAR2STR _CAN4IDAR2; /* MSCAN4 Identifier Acceptance Register 2 */\r
+volatile CAN4IDAR3STR _CAN4IDAR3; /* MSCAN4 Identifier Acceptance Register 3 */\r
+volatile CAN4IDAR4STR _CAN4IDAR4; /* MSCAN4 Identifier Acceptance Register 4 */\r
+volatile CAN4IDAR5STR _CAN4IDAR5; /* MSCAN4 Identifier Acceptance Register 5 */\r
+volatile CAN4IDAR6STR _CAN4IDAR6; /* MSCAN4 Identifier Acceptance Register 6 */\r
+volatile CAN4IDAR7STR _CAN4IDAR7; /* MSCAN4 Identifier Acceptance Register 7 */\r
+volatile CAN4IDMR0STR _CAN4IDMR0; /* MSCAN4 Identifier Mask Register 0 */\r
+volatile CAN4IDMR1STR _CAN4IDMR1; /* MSCAN4 Identifier Mask Register 1 */\r
+volatile CAN4IDMR2STR _CAN4IDMR2; /* MSCAN4 Identifier Mask Register 2 */\r
+volatile CAN4IDMR3STR _CAN4IDMR3; /* MSCAN4 Identifier Mask Register 3 */\r
+volatile CAN4IDMR4STR _CAN4IDMR4; /* MSCAN4 Identifier Mask Register 4 */\r
+volatile CAN4IDMR5STR _CAN4IDMR5; /* MSCAN4 Identifier Mask Register 5 */\r
+volatile CAN4IDMR6STR _CAN4IDMR6; /* MSCAN4 Identifier Mask Register 6 */\r
+volatile CAN4IDMR7STR _CAN4IDMR7; /* MSCAN4 Identifier Mask Register 7 */\r
+volatile CAN4RFLGSTR _CAN4RFLG; /* MSCAN4 Receiver Flag Register */\r
+volatile CAN4RIERSTR _CAN4RIER; /* MSCAN4 Receiver Interrupt Enable Register */\r
+volatile CAN4RXDLRSTR _CAN4RXDLR; /* MSCAN4 Receive Data Length Register */\r
+volatile CAN4RXDSR0STR _CAN4RXDSR0; /* MSCAN4 Receive Data Segment Register 0 */\r
+volatile CAN4RXDSR1STR _CAN4RXDSR1; /* MSCAN4 Receive Data Segment Register 1 */\r
+volatile CAN4RXDSR2STR _CAN4RXDSR2; /* MSCAN4 Receive Data Segment Register 2 */\r
+volatile CAN4RXDSR3STR _CAN4RXDSR3; /* MSCAN4 Receive Data Segment Register 3 */\r
+volatile CAN4RXDSR4STR _CAN4RXDSR4; /* MSCAN4 Receive Data Segment Register 4 */\r
+volatile CAN4RXDSR5STR _CAN4RXDSR5; /* MSCAN4 Receive Data Segment Register 5 */\r
+volatile CAN4RXDSR6STR _CAN4RXDSR6; /* MSCAN4 Receive Data Segment Register 6 */\r
+volatile CAN4RXDSR7STR _CAN4RXDSR7; /* MSCAN4 Receive Data Segment Register 7 */\r
+volatile CAN4RXERRSTR _CAN4RXERR; /* MSCAN4 Receive Error Counter Register */\r
+volatile CAN4RXIDR0STR _CAN4RXIDR0; /* MSCAN4 Receive Identifier Register 0 */\r
+volatile CAN4RXIDR1STR _CAN4RXIDR1; /* MSCAN4 Receive Identifier Register 1 */\r
+volatile CAN4RXIDR2STR _CAN4RXIDR2; /* MSCAN4 Receive Identifier Register 2 */\r
+volatile CAN4RXIDR3STR _CAN4RXIDR3; /* MSCAN4 Receive Identifier Register 3 */\r
+volatile CAN4TAAKSTR _CAN4TAAK; /* MSCAN4 Transmitter Message Abort Control */\r
+volatile CAN4TARQSTR _CAN4TARQ; /* MSCAN 4 Transmitter Message Abort Request */\r
+volatile CAN4TBSELSTR _CAN4TBSEL; /* MSCAN4 Transmit Buffer Selection */\r
+volatile CAN4TFLGSTR _CAN4TFLG; /* MSCAN4 Transmitter Flag Register */\r
+volatile CAN4TIERSTR _CAN4TIER; /* MSCAN4 Transmitter Interrupt Enable Register */\r
+volatile CAN4TXDLRSTR _CAN4TXDLR; /* MSCAN4 Transmit Data Length Register */\r
+volatile CAN4TXDSR0STR _CAN4TXDSR0; /* MSCAN4 Transmit Data Segment Register 0 */\r
+volatile CAN4TXDSR1STR _CAN4TXDSR1; /* MSCAN4 Transmit Data Segment Register 1 */\r
+volatile CAN4TXDSR2STR _CAN4TXDSR2; /* MSCAN4 Transmit Data Segment Register 2 */\r
+volatile CAN4TXDSR3STR _CAN4TXDSR3; /* MSCAN4 Transmit Data Segment Register 3 */\r
+volatile CAN4TXDSR4STR _CAN4TXDSR4; /* MSCAN4 Transmit Data Segment Register 4 */\r
+volatile CAN4TXDSR5STR _CAN4TXDSR5; /* MSCAN4 Transmit Data Segment Register 5 */\r
+volatile CAN4TXDSR6STR _CAN4TXDSR6; /* MSCAN4 Transmit Data Segment Register 6 */\r
+volatile CAN4TXDSR7STR _CAN4TXDSR7; /* MSCAN4 Transmit Data Segment Register 7 */\r
+volatile CAN4TXERRSTR _CAN4TXERR; /* MSCAN4 Transmit Error Counter Register */\r
+volatile CAN4TXIDR0STR _CAN4TXIDR0; /* MSCAN4 Transmit Identifier Register 0 */\r
+volatile CAN4TXIDR1STR _CAN4TXIDR1; /* MSCAN4 Transmit Identifier Register 1 */\r
+volatile CAN4TXIDR2STR _CAN4TXIDR2; /* MSCAN4 Transmit Identifier Register 2 */\r
+volatile CAN4TXIDR3STR _CAN4TXIDR3; /* MSCAN4 Transmit Identifier Register 3 */\r
+volatile CAN4TXTBPRSTR _CAN4TXTBPR; /* MSCAN4 Transmit Transmit Buffer Priority */\r
+volatile CFORCSTR _CFORC; /* Timer Compare Force Register */\r
+volatile CLKSELSTR _CLKSEL; /* CRG Clock Select Register */\r
+volatile COPCTLSTR _COPCTL; /* CRG COP Control Register */\r
+volatile CRGFLGSTR _CRGFLG; /* CRG Flags Register */\r
+volatile CRGINTSTR _CRGINT; /* CRG Interrupt Enable Register */\r
+volatile CTCTLSTR _CTCTL; /* CRG Test Control Register */\r
+volatile CTFLGSTR _CTFLG; /* CRG Test Flags Register */\r
+volatile DDRESTR _DDRE; /* Port E Data Direction Register */\r
+volatile DDRHSTR _DDRH; /* Port H Data Direction Register */\r
+volatile DDRJSTR _DDRJ; /* Port J Data Direction Register */\r
+volatile DDRKSTR _DDRK; /* Port K Data Direction Register */\r
+volatile DDRMSTR _DDRM; /* Port M Data Direction Register */\r
+volatile DDRPSTR _DDRP; /* Port P Data Direction Register */\r
+volatile DDRSSTR _DDRS; /* Port S Data Direction Register */\r
+volatile DDRTSTR _DDRT; /* Port T Data Direction Register */\r
+volatile DLCBARDSTR _DLCBARD; /* BDLC Analog Round Trip Delay Register */\r
+volatile DLCBCR1STR _DLCBCR1; /* BDLC Control Register 1 */\r
+volatile DLCBCR2STR _DLCBCR2; /* BDLC Control Register 2 */\r
+volatile DLCBDRSTR _DLCBDR; /* BDLC Data Register */\r
+volatile DLCBRSRSTR _DLCBRSR; /* BDLC Rate Select Register */\r
+volatile DLCBSVRSTR _DLCBSVR; /* BDLC State Vector Register */\r
+volatile DLCSCRSTR _DLCSCR; /* BDLC Control Register */\r
+volatile DLYCTSTR _DLYCT; /* Delay Counter Control Register */\r
+volatile EBICTLSTR _EBICTL; /* External Bus Interface Control */\r
+volatile ECLKDIVSTR _ECLKDIV; /* EEPROM Clock Divider Register */\r
+volatile ECMDSTR _ECMD; /* EEPROM Command Buffer and Register */\r
+volatile ECNFGSTR _ECNFG; /* EEPROM Configuration Register */\r
+volatile EPROTSTR _EPROT; /* EEPROM Protection Register */\r
+volatile ESTATSTR _ESTAT; /* EEPROM Status Register */\r
+volatile FCLKDIVSTR _FCLKDIV; /* Flash Clock Divider Register */\r
+volatile FCMDSTR _FCMD; /* Flash Command Buffer and Register */\r
+volatile FCNFGSTR _FCNFG; /* Flash Configuration Register */\r
+volatile FORBYPSTR _FORBYP; /* Crg force and bypass test register */\r
+volatile FPROTSTR _FPROT; /* Flash Protection Register */\r
+volatile FSECSTR _FSEC; /* Flash Security Register */\r
+volatile FSTATSTR _FSTAT; /* Flash Status Register */\r
+volatile HPRIOSTR _HPRIO; /* Highest Priority I Interrupt */\r
+volatile IBADSTR _IBAD; /* IIC Address Register */\r
+volatile IBCRSTR _IBCR; /* IIC Control Register */\r
+volatile IBDRSTR _IBDR; /* IIC Data I/O Register */\r
+volatile IBFDSTR _IBFD; /* IIC Frequency Divider Register */\r
+volatile IBSRSTR _IBSR; /* IIC Status Register */\r
+volatile ICOVWSTR _ICOVW; /* Input Control Overwrite Register */\r
+volatile ICPARSTR _ICPAR; /* Input Control Pulse Accumulator Register */\r
+volatile ICSYSSTR _ICSYS; /* Input Control System Control Register */\r
+volatile INITEESTR _INITEE; /* Initialization of Internal EEPROM Position Register */\r
+volatile INITRGSTR _INITRG; /* Initialization of Internal Register Position Register */\r
+volatile INITRMSTR _INITRM; /* Initialization of Internal RAM Position Register */\r
+volatile INTCRSTR _INTCR; /* Interrupt Control Register */\r
+volatile ITCRSTR _ITCR; /* Interrupt Test Control Register */\r
+volatile ITESTSTR _ITEST; /* Interrupt Test Register */\r
+volatile MCCTLSTR _MCCTL; /* Modulus Down Counter underflow */\r
+volatile MCFLGSTR _MCFLG; /* 16-Bit Modulus Down Counter Flag Register */\r
+volatile MEMSIZ0STR _MEMSIZ0; /* Memory Size Register Zero */\r
+volatile MEMSIZ1STR _MEMSIZ1; /* Memory Size Register One */\r
+volatile MISCSTR _MISC; /* Miscellaneous Mapping Control Register */\r
+volatile MODESTR _MODE; /* Mode Register */\r
+volatile MODRRSTR _MODRR; /* Module Routing Register */\r
+volatile MTST0STR _MTST0; /* MTST0 */\r
+volatile MTST1STR _MTST1; /* MTST1 */\r
+volatile OC7DSTR _OC7D; /* Output Compare 7 Data Register */\r
+volatile OC7MSTR _OC7M; /* Output Compare 7 Mask Register */\r
+volatile PACTLSTR _PACTL; /* 16-Bit Pulse Accumulator A Control Register */\r
+volatile PAFLGSTR _PAFLG; /* Pulse Accumulator A Flag Register */\r
+volatile PARTIDHSTR _PARTIDH; /* Part ID Register High */\r
+volatile PARTIDLSTR _PARTIDL; /* Part ID Register Low */\r
+volatile PBCTLSTR _PBCTL; /* 16-Bit Pulse Accumulator B Control Register */\r
+volatile PBFLGSTR _PBFLG; /* Pulse Accumulator B Flag Register */\r
+volatile PEARSTR _PEAR; /* Port E Assignment Register */\r
+volatile PERHSTR _PERH; /* Port H Pull Device Enable Register */\r
+volatile PERJSTR _PERJ; /* Port J Pull Device Enable Register */\r
+volatile PERMSTR _PERM; /* Port M Pull Device Enable Register */\r
+volatile PERPSTR _PERP; /* Port P Pull Device Enable Register */\r
+volatile PERSSTR _PERS; /* Port S Pull Device Enable Register */\r
+volatile PERTSTR _PERT; /* Port T Pull Device Enable Register */\r
+volatile PIEHSTR _PIEH; /* Port H Interrupt Enable Register */\r
+volatile PIEJSTR _PIEJ; /* Port J Interrupt Enable Register */\r
+volatile PIEPSTR _PIEP; /* Port P Interrupt Enable Register */\r
+volatile PIFHSTR _PIFH; /* Port H Interrupt Flag Register */\r
+volatile PIFJSTR _PIFJ; /* Port J Interrupt Flag Register */\r
+volatile PIFPSTR _PIFP; /* Port P Interrupt Flag Register */\r
+volatile PLLCTLSTR _PLLCTL; /* CRG PLL Control Register */\r
+volatile PORTAD0STR _PORTAD0; /* Port AD0 Register */\r
+volatile PORTAD1STR _PORTAD1; /* Port AD1 Register */\r
+volatile PORTESTR _PORTE; /* Port E Register */\r
+volatile PORTKSTR _PORTK; /* Port K Data Register */\r
+volatile PPAGESTR _PPAGE; /* Page Index Register */\r
+volatile PPSHSTR _PPSH; /* Port H Polarity Select Register */\r
+volatile PPSJSTR _PPSJ; /* PortJP Polarity Select Register */\r
+volatile PPSMSTR _PPSM; /* Port M Polarity Select Register */\r
+volatile PPSPSTR _PPSP; /* Port P Polarity Select Register */\r
+volatile PPSSSTR _PPSS; /* Port S Polarity Select Register */\r
+volatile PPSTSTR _PPST; /* Port T Polarity Select Register */\r
+volatile PTHSTR _PTH; /* Port H I/O Register */\r
+volatile PTIHSTR _PTIH; /* Port H Input Register */\r
+volatile PTIJSTR _PTIJ; /* Port J Input Register */\r
+volatile PTIMSTR _PTIM; /* Port M Input */\r
+volatile PTIPSTR _PTIP; /* Port P Input */\r
+volatile PTISSTR _PTIS; /* Port S Input */\r
+volatile PTITSTR _PTIT; /* Port T Input */\r
+volatile PTJSTR _PTJ; /* Port J I/O Register */\r
+volatile PTMSTR _PTM; /* Port M I/O Register */\r
+volatile PTPSTR _PTP; /* Port P I/O Register */\r
+volatile PTSSTR _PTS; /* Port S I/O Register */\r
+volatile PTTSTR _PTT; /* Port T I/O Register */\r
+volatile PUCRSTR _PUCR; /* Pull-Up Control Register */\r
+volatile PWMCAESTR _PWMCAE; /* PWM Center Align Enable Register */\r
+volatile PWMCLKSTR _PWMCLK; /* PWM Clock Select Register */\r
+volatile PWMCTLSTR _PWMCTL; /* PWM Control Register */\r
+volatile PWMESTR _PWME; /* PWM Enable Register */\r
+volatile PWMPOLSTR _PWMPOL; /* PWM Polarity Register */\r
+volatile PWMPRCLKSTR _PWMPRCLK; /* PWM Prescale Clock Select Register */\r
+volatile PWMSCLASTR _PWMSCLA; /* PWM Scale A Register */\r
+volatile PWMSCLBSTR _PWMSCLB; /* PWM Scale B Register */\r
+volatile PWMSDNSTR _PWMSDN; /* PWM Shutdown Register */\r
+volatile RDRHSTR _RDRH; /* Port H Reduced Drive Register */\r
+volatile RDRIVSTR _RDRIV; /* Reduced Drive of I/O Lines */\r
+volatile RDRJSTR _RDRJ; /* Port J Reduced Drive Register */\r
+volatile RDRMSTR _RDRM; /* Port M Reduced Drive Register */\r
+volatile RDRPSTR _RDRP; /* Port P Reduced Drive Register */\r
+volatile RDRSSTR _RDRS; /* Port S Reduced Drive Register */\r
+volatile RDRTSTR _RDRT; /* Port T Reduced Drive Register */\r
+volatile REFDVSTR _REFDV; /* CRG Reference Divider Register */\r
+volatile RTICTLSTR _RTICTL; /* CRG RTI Control Register */\r
+volatile SCI0CR1STR _SCI0CR1; /* SCI 0 Control Register 1 */\r
+volatile SCI0CR2STR _SCI0CR2; /* SCI 0 Control Register 2 */\r
+volatile SCI0DRHSTR _SCI0DRH; /* SCI 0 Data Register High */\r
+volatile SCI0DRLSTR _SCI0DRL; /* SCI 0 Data Register Low */\r
+volatile SCI0SR1STR _SCI0SR1; /* SCI 0 Status Register 1 */\r
+volatile SCI0SR2STR _SCI0SR2; /* SCI 0 Status Register 2 */\r
+volatile SCI1CR1STR _SCI1CR1; /* SCI 1 Control Register 1 */\r
+volatile SCI1CR2STR _SCI1CR2; /* SCI 1 Control Register 2 */\r
+volatile SCI1DRHSTR _SCI1DRH; /* SCI 1 Data Register High */\r
+volatile SCI1DRLSTR _SCI1DRL; /* SCI 1 Data Register Low */\r
+volatile SCI1SR1STR _SCI1SR1; /* SCI 1 Status Register 1 */\r
+volatile SCI1SR2STR _SCI1SR2; /* SCI 1 Status Register 2 */\r
+volatile SPI0BRSTR _SPI0BR; /* SPI 0 Baud Rate Register */\r
+volatile SPI0CR1STR _SPI0CR1; /* SPI 0 Control Register */\r
+volatile SPI0CR2STR _SPI0CR2; /* SPI 0 Control Register 2 */\r
+volatile SPI0DRSTR _SPI0DR; /* SPI 0 Data Register */\r
+volatile SPI0SRSTR _SPI0SR; /* SPI 0 Status Register */\r
+volatile SPI1BRSTR _SPI1BR; /* SPI 1 Baud Rate Register */\r
+volatile SPI1CR1STR _SPI1CR1; /* SPI 1 Control Register */\r
+volatile SPI1CR2STR _SPI1CR2; /* SPI 1 Control Register 2 */\r
+volatile SPI1DRSTR _SPI1DR; /* SPI 1 Data Register */\r
+volatile SPI1SRSTR _SPI1SR; /* SPI 1 Status Register */\r
+volatile SPI2BRSTR _SPI2BR; /* SPI 2 Baud Rate Register */\r
+volatile SPI2CR1STR _SPI2CR1; /* SPI 2 Control Register */\r
+volatile SPI2CR2STR _SPI2CR2; /* SPI 2 Control Register 2 */\r
+volatile SPI2DRSTR _SPI2DR; /* SPI 2 Data Register */\r
+volatile SPI2SRSTR _SPI2SR; /* SPI 2 Status Register */\r
+volatile SYNRSTR _SYNR; /* CRG Synthesizer Register */\r
+volatile TCTL1STR _TCTL1; /* Timer Control Registers 1 */\r
+volatile TCTL2STR _TCTL2; /* Timer Control Registers 2 */\r
+volatile TCTL3STR _TCTL3; /* Timer Control Register 3 */\r
+volatile TCTL4STR _TCTL4; /* Timer Control Register 4 */\r
+volatile TFLG1STR _TFLG1; /* Main Timer Interrupt Flag 1 */\r
+volatile TFLG2STR _TFLG2; /* Main Timer Interrupt Flag 2 */\r
+volatile TIESTR _TIE; /* Timer Interrupt Enable Register */\r
+volatile TIMTSTSTR _TIMTST; /* Timer Test Register */\r
+volatile TIOSSTR _TIOS; /* Timer Input Capture/Output Compare Select */\r
+volatile TSCR1STR _TSCR1; /* Timer System Control Register1 */\r
+volatile TSCR2STR _TSCR2; /* Timer System Control Register 2 */\r
+volatile TTOVSTR _TTOV; /* Timer Toggle On Overflow Register */\r
+volatile WOMMSTR _WOMM; /* Port M Wired-Or Mode Register */\r
+volatile WOMSSTR _WOMS; /* Port S Wired-Or Mode Register */\r
+volatile ATD0CTL23STR _ATD0CTL23; /* ATD 0 Control Register 23 */\r
+volatile ATD0CTL45STR _ATD0CTL45; /* ATD 0 Control Register 45 */\r
+volatile ATD0DR0STR _ATD0DR0; /* ATD 0 Conversion Result Register 0 */\r
+volatile ATD0DR1STR _ATD0DR1; /* ATD 0 Conversion Result Register 1 */\r
+volatile ATD0DR2STR _ATD0DR2; /* ATD 0 Conversion Result Register 2 */\r
+volatile ATD0DR3STR _ATD0DR3; /* ATD 0 Conversion Result Register 3 */\r
+volatile ATD0DR4STR _ATD0DR4; /* ATD 0 Conversion Result Register 4 */\r
+volatile ATD0DR5STR _ATD0DR5; /* ATD 0 Conversion Result Register 5 */\r
+volatile ATD0DR6STR _ATD0DR6; /* ATD 0 Conversion Result Register 6 */\r
+volatile ATD0DR7STR _ATD0DR7; /* ATD 0 Conversion Result Register 7 */\r
+volatile ATD1CTL23STR _ATD1CTL23; /* ATD 1 Control Register 23 */\r
+volatile ATD1CTL45STR _ATD1CTL45; /* ATD 1 Control Register 45 */\r
+volatile ATD1DR0STR _ATD1DR0; /* ATD 1 Conversion Result Register 0 */\r
+volatile ATD1DR1STR _ATD1DR1; /* ATD 1 Conversion Result Register 1 */\r
+volatile ATD1DR2STR _ATD1DR2; /* ATD 1 Conversion Result Register 2 */\r
+volatile ATD1DR3STR _ATD1DR3; /* ATD 1 Conversion Result Register 3 */\r
+volatile ATD1DR4STR _ATD1DR4; /* ATD 1 Conversion Result Register 4 */\r
+volatile ATD1DR5STR _ATD1DR5; /* ATD 1 Conversion Result Register 5 */\r
+volatile ATD1DR6STR _ATD1DR6; /* ATD 1 Conversion Result Register 6 */\r
+volatile ATD1DR7STR _ATD1DR7; /* ATD 1 Conversion Result Register 7 */\r
+volatile DDRABSTR _DDRAB; /* Port AB Data Direction Register */\r
+volatile MCCNTSTR _MCCNT; /* Modulus Down-Counter Count Register */\r
+volatile PA10HSTR _PA10H; /* 8-Bit Pulse Accumulators Holding 10 Register */\r
+volatile PA32HSTR _PA32H; /* 8-Bit Pulse Accumulators Holding 32 Register */\r
+volatile PACN10STR _PACN10; /* Pulse Accumulators Count 10 Register */\r
+volatile PACN32STR _PACN32; /* Pulse Accumulators Count 32 Register */\r
+volatile PORTABSTR _PORTAB; /* Port AB Register */\r
+volatile PWMCNT01STR _PWMCNT01; /* PWM Channel Counter 01 Register */\r
+volatile PWMCNT23STR _PWMCNT23; /* PWM Channel Counter 23 Register */\r
+volatile PWMCNT45STR _PWMCNT45; /* PWM Channel Counter 45 Register */\r
+volatile PWMCNT67STR _PWMCNT67; /* PWM Channel Counter 67 Register */\r
+volatile PWMDTY01STR _PWMDTY01; /* PWM Channel Duty 01 Register */\r
+volatile PWMDTY23STR _PWMDTY23; /* PWM Channel Duty 23 Register */\r
+volatile PWMDTY45STR _PWMDTY45; /* PWM Channel Duty 45 Register */\r
+volatile PWMDTY67STR _PWMDTY67; /* PWM Channel Duty 67 Register */\r
+volatile PWMPER01STR _PWMPER01; /* PWM Channel Period 01 Register */\r
+volatile PWMPER23STR _PWMPER23; /* PWM Channel Period 23 Register */\r
+volatile PWMPER45STR _PWMPER45; /* PWM Channel Period 45 Register */\r
+volatile PWMPER67STR _PWMPER67; /* PWM Channel Period 67 Register */\r
+volatile SCI0BDSTR _SCI0BD; /* SCI 0 Baud Rate Register */\r
+volatile SCI1BDSTR _SCI1BD; /* SCI 1 Baud Rate Register */\r
+volatile TC0STR _TC0; /* Timer Input Capture/Output Compare Register 0 */\r
+volatile TC0HSTR _TC0H; /* Timer Input Capture Holding Registers 0 */\r
+volatile TC1STR _TC1; /* Timer Input Capture/Output Compare Register 1 */\r
+volatile TC1HSTR _TC1H; /* Timer Input Capture Holding Registers 1 */\r
+volatile TC2STR _TC2; /* Timer Input Capture/Output Compare Register 2 */\r
+volatile TC2HSTR _TC2H; /* Timer Input Capture Holding Registers 2 */\r
+volatile TC3STR _TC3; /* Timer Input Capture/Output Compare Register 3 */\r
+volatile TC3HSTR _TC3H; /* Timer Input Capture Holding Registers 3 */\r
+volatile TC4STR _TC4; /* Timer Input Capture/Output Compare Register 4 */\r
+volatile TC5STR _TC5; /* Timer Input Capture/Output Compare Register 5 */\r
+volatile TC6STR _TC6; /* Timer Input Capture/Output Compare Register 6 */\r
+volatile TC7STR _TC7; /* Timer Input Capture/Output Compare Register 7 */\r
+volatile TCNTSTR _TCNT; /* Timer Count Register */\r
+/*\r
+** ###################################################################\r
+**\r
+** This file was created by UNIS Processor Expert 03.33 for \r
+** the Motorola HCS12 series of microcontrollers.\r
+**\r
+** ###################################################################\r
+*/\r
--- /dev/null
+/** ###################################################################\r
+** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.\r
+** Filename : IO_Map.H\r
+** Project : RTOSDemo\r
+** Processor : MC9S12DP256BCPV\r
+** Beantype : IO_Map\r
+** Version : Driver 01.01\r
+** Compiler : Metrowerks HC12 C Compiler\r
+** Date/Time : 13/06/2005, 20:14\r
+** Abstract :\r
+** This bean "IO_Map" implements an IO devices mapping.\r
+** Settings :\r
+**\r
+** Contents :\r
+** No public methods\r
+**\r
+** (c) Copyright UNIS, spol. s r.o. 1997-2002\r
+** UNIS, spol. s r.o.\r
+** Jundrovska 33\r
+** 624 00 Brno\r
+** Czech Republic\r
+** http : www.processorexpert.com\r
+** mail : info@processorexpert.com\r
+** ###################################################################*/\r
+\r
+/* Linker pragmas */\r
+#pragma LINK_INFO DERIVATIVE "MC9S12DP256B"\r
+#pragma LINK_INFO OSCFREQUENCY "16000000"\r
+\r
+\r
+#define REG_BASE 0x0000 /* Base address for the I/O register block */\r
+\r
+/* Based on CPU DB MC9S12DP256_112, version 2.87.278 (RegistersPrg V1.027) */\r
+#ifndef _MC9S12DP256_112_H\r
+#define _MC9S12DP256_112_H\r
+\r
+#include "PE_Types.h"\r
+\r
+#pragma MESSAGE DISABLE C1106 /* WARNING C1106: Non-standard bitfield type */\r
+\r
+/*********************************************/\r
+/* */\r
+/* PE I/O map format */\r
+/* */\r
+/*********************************************/\r
+\r
+/*** PORTAB - Port AB Register; 0x00000000 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** PORTA - Port A Register; 0x00000000 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* Port A Bit0, ADDR8, DATA8, DATA0 */\r
+ byte BIT1 :1; /* Port A Bit1, ADDR9, DATA9 DATA1 */\r
+ byte BIT2 :1; /* Port A Bit2, ADDR10, DATA10, DATA2 */\r
+ byte BIT3 :1; /* Port A Bit3, ADDR11, DATA11, DATA3 */\r
+ byte BIT4 :1; /* Port A Bit4, ADDR12, DATA12, DATA4 */\r
+ byte BIT5 :1; /* Port A Bit5, ADDR13, DATA13, DATA5 */\r
+ byte BIT6 :1; /* Port A Bit6, ADDR14, DATA14, DATA6 */\r
+ byte BIT7 :1; /* Port A Bit7, ADDR15, DATA15, DATA7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } PORTASTR;\r
+ #define PORTA _PORTAB.Overlap_STR.PORTASTR.Byte\r
+ #define PORTA_BIT0 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT0\r
+ #define PORTA_BIT1 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT1\r
+ #define PORTA_BIT2 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT2\r
+ #define PORTA_BIT3 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT3\r
+ #define PORTA_BIT4 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT4\r
+ #define PORTA_BIT5 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT5\r
+ #define PORTA_BIT6 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT6\r
+ #define PORTA_BIT7 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT7\r
+ #define PORTA_BIT _PORTAB.Overlap_STR.PORTASTR.MergedBits.grpBIT\r
+ \r
+ /*** PORTB - Port B Register; 0x00000001 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* Port B Bit 0, ADDR0, DATA0 */\r
+ byte BIT1 :1; /* Port B Bit1, ADDR1, DATA1 */\r
+ byte BIT2 :1; /* Port B Bit2, ADDR2, DATA2 */\r
+ byte BIT3 :1; /* Port B Bit3, ADDR3, DATA3 */\r
+ byte BIT4 :1; /* Port B Bit4, ADDR4, DATA4 */\r
+ byte BIT5 :1; /* Port B Bit5, ADDR5, DATA5 */\r
+ byte BIT6 :1; /* Port B Bit6, ADDR6, DATA6 */\r
+ byte BIT7 :1; /* Port B Bit7, ADDR7, DATA7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } PORTBSTR;\r
+ #define PORTB _PORTAB.Overlap_STR.PORTBSTR.Byte\r
+ #define PORTB_BIT0 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT0\r
+ #define PORTB_BIT1 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT1\r
+ #define PORTB_BIT2 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT2\r
+ #define PORTB_BIT3 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT3\r
+ #define PORTB_BIT4 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT4\r
+ #define PORTB_BIT5 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT5\r
+ #define PORTB_BIT6 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT6\r
+ #define PORTB_BIT7 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT7\r
+ #define PORTB_BIT _PORTAB.Overlap_STR.PORTBSTR.MergedBits.grpBIT\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word BIT0 :1; /* Port B Bit 0, ADDR0, DATA0 */\r
+ word BIT1 :1; /* Port B Bit1, ADDR1, DATA1 */\r
+ word BIT2 :1; /* Port B Bit2, ADDR2, DATA2 */\r
+ word BIT3 :1; /* Port B Bit3, ADDR3, DATA3 */\r
+ word BIT4 :1; /* Port B Bit4, ADDR4, DATA4 */\r
+ word BIT5 :1; /* Port B Bit5, ADDR5, DATA5 */\r
+ word BIT6 :1; /* Port B Bit6, ADDR6, DATA6 */\r
+ word BIT7 :1; /* Port B Bit7, ADDR7, DATA7 */\r
+ word BIT8 :1; /* Port A Bit0, ADDR8, DATA8, DATA0 */\r
+ word BIT9 :1; /* Port A Bit1, ADDR9, DATA9 DATA1 */\r
+ word BIT10 :1; /* Port A Bit2, ADDR10, DATA10, DATA2 */\r
+ word BIT11 :1; /* Port A Bit3, ADDR11, DATA11, DATA3 */\r
+ word BIT12 :1; /* Port A Bit4, ADDR12, DATA12, DATA4 */\r
+ word BIT13 :1; /* Port A Bit5, ADDR13, DATA13, DATA5 */\r
+ word BIT14 :1; /* Port A Bit6, ADDR14, DATA14, DATA6 */\r
+ word BIT15 :1; /* Port A Bit7, ADDR15, DATA15, DATA7 */\r
+ } Bits;\r
+ struct {\r
+ word grpBIT :16;\r
+ } MergedBits;\r
+} PORTABSTR;\r
+extern volatile PORTABSTR _PORTAB @(REG_BASE + 0x00000000);\r
+#define PORTAB _PORTAB.Word\r
+#define PORTAB_BIT0 _PORTAB.Bits.BIT0\r
+#define PORTAB_BIT1 _PORTAB.Bits.BIT1\r
+#define PORTAB_BIT2 _PORTAB.Bits.BIT2\r
+#define PORTAB_BIT3 _PORTAB.Bits.BIT3\r
+#define PORTAB_BIT4 _PORTAB.Bits.BIT4\r
+#define PORTAB_BIT5 _PORTAB.Bits.BIT5\r
+#define PORTAB_BIT6 _PORTAB.Bits.BIT6\r
+#define PORTAB_BIT7 _PORTAB.Bits.BIT7\r
+#define PORTAB_BIT8 _PORTAB.Bits.BIT8\r
+#define PORTAB_BIT9 _PORTAB.Bits.BIT9\r
+#define PORTAB_BIT10 _PORTAB.Bits.BIT10\r
+#define PORTAB_BIT11 _PORTAB.Bits.BIT11\r
+#define PORTAB_BIT12 _PORTAB.Bits.BIT12\r
+#define PORTAB_BIT13 _PORTAB.Bits.BIT13\r
+#define PORTAB_BIT14 _PORTAB.Bits.BIT14\r
+#define PORTAB_BIT15 _PORTAB.Bits.BIT15\r
+#define PORTAB_BIT _PORTAB.MergedBits.grpBIT\r
+\r
+\r
+/*** DDRAB - Port AB Data Direction Register; 0x00000002 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** DDRA - Port A Data Direction Register; 0x00000002 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* Data Direction Port A Bit 0 */\r
+ byte BIT1 :1; /* Data Direction Port A Bit 1 */\r
+ byte BIT2 :1; /* Data Direction Port A Bit 2 */\r
+ byte BIT3 :1; /* Data Direction Port A Bit 3 */\r
+ byte BIT4 :1; /* Data Direction Port A Bit 4 */\r
+ byte BIT5 :1; /* Data Direction Port A Bit 5 */\r
+ byte BIT6 :1; /* Data Direction Port A Bit 6 */\r
+ byte BIT7 :1; /* Data Direction Port A Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } DDRASTR;\r
+ #define DDRA _DDRAB.Overlap_STR.DDRASTR.Byte\r
+ #define DDRA_BIT0 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT0\r
+ #define DDRA_BIT1 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT1\r
+ #define DDRA_BIT2 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT2\r
+ #define DDRA_BIT3 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT3\r
+ #define DDRA_BIT4 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT4\r
+ #define DDRA_BIT5 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT5\r
+ #define DDRA_BIT6 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT6\r
+ #define DDRA_BIT7 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT7\r
+ #define DDRA_BIT _DDRAB.Overlap_STR.DDRASTR.MergedBits.grpBIT\r
+ \r
+ /*** DDRB - Port B Data Direction Register; 0x00000003 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* Data Direction Port B Bit 0 */\r
+ byte BIT1 :1; /* Data Direction Port B Bit 1 */\r
+ byte BIT2 :1; /* Data Direction Port B Bit 2 */\r
+ byte BIT3 :1; /* Data Direction Port B Bit 3 */\r
+ byte BIT4 :1; /* Data Direction Port B Bit 4 */\r
+ byte BIT5 :1; /* Data Direction Port B Bit 5 */\r
+ byte BIT6 :1; /* Data Direction Port B Bit 6 */\r
+ byte BIT7 :1; /* Data Direction Port B Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } DDRBSTR;\r
+ #define DDRB _DDRAB.Overlap_STR.DDRBSTR.Byte\r
+ #define DDRB_BIT0 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT0\r
+ #define DDRB_BIT1 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT1\r
+ #define DDRB_BIT2 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT2\r
+ #define DDRB_BIT3 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT3\r
+ #define DDRB_BIT4 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT4\r
+ #define DDRB_BIT5 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT5\r
+ #define DDRB_BIT6 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT6\r
+ #define DDRB_BIT7 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT7\r
+ #define DDRB_BIT _DDRAB.Overlap_STR.DDRBSTR.MergedBits.grpBIT\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word BIT0 :1; /* Data Direction Port B Bit 0 */\r
+ word BIT1 :1; /* Data Direction Port B Bit 1 */\r
+ word BIT2 :1; /* Data Direction Port B Bit 2 */\r
+ word BIT3 :1; /* Data Direction Port B Bit 3 */\r
+ word BIT4 :1; /* Data Direction Port B Bit 4 */\r
+ word BIT5 :1; /* Data Direction Port B Bit 5 */\r
+ word BIT6 :1; /* Data Direction Port B Bit 6 */\r
+ word BIT7 :1; /* Data Direction Port B Bit 7 */\r
+ word BIT8 :1; /* Data Direction Port A Bit 8 */\r
+ word BIT9 :1; /* Data Direction Port A Bit 9 */\r
+ word BIT10 :1; /* Data Direction Port A Bit 10 */\r
+ word BIT11 :1; /* Data Direction Port A Bit 11 */\r
+ word BIT12 :1; /* Data Direction Port A Bit 12 */\r
+ word BIT13 :1; /* Data Direction Port A Bit 13 */\r
+ word BIT14 :1; /* Data Direction Port A Bit 14 */\r
+ word BIT15 :1; /* Data Direction Port A Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ word grpBIT :16;\r
+ } MergedBits;\r
+} DDRABSTR;\r
+extern volatile DDRABSTR _DDRAB @(REG_BASE + 0x00000002);\r
+#define DDRAB _DDRAB.Word\r
+#define DDRAB_BIT0 _DDRAB.Bits.BIT0\r
+#define DDRAB_BIT1 _DDRAB.Bits.BIT1\r
+#define DDRAB_BIT2 _DDRAB.Bits.BIT2\r
+#define DDRAB_BIT3 _DDRAB.Bits.BIT3\r
+#define DDRAB_BIT4 _DDRAB.Bits.BIT4\r
+#define DDRAB_BIT5 _DDRAB.Bits.BIT5\r
+#define DDRAB_BIT6 _DDRAB.Bits.BIT6\r
+#define DDRAB_BIT7 _DDRAB.Bits.BIT7\r
+#define DDRAB_BIT8 _DDRAB.Bits.BIT8\r
+#define DDRAB_BIT9 _DDRAB.Bits.BIT9\r
+#define DDRAB_BIT10 _DDRAB.Bits.BIT10\r
+#define DDRAB_BIT11 _DDRAB.Bits.BIT11\r
+#define DDRAB_BIT12 _DDRAB.Bits.BIT12\r
+#define DDRAB_BIT13 _DDRAB.Bits.BIT13\r
+#define DDRAB_BIT14 _DDRAB.Bits.BIT14\r
+#define DDRAB_BIT15 _DDRAB.Bits.BIT15\r
+#define DDRAB_BIT _DDRAB.MergedBits.grpBIT\r
+\r
+\r
+/*** TCNT - Timer Count Register; 0x00000044 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** TCNTHi - Timer Count Register High; 0x00000044 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT15 :1; /* Timer Count Register Bit 15 */\r
+ byte BIT14 :1; /* Timer Count Register Bit 14 */\r
+ byte BIT13 :1; /* Timer Count Register Bit 13 */\r
+ byte BIT12 :1; /* Timer Count Register Bit 12 */\r
+ byte BIT11 :1; /* Timer Count Register Bit 11 */\r
+ byte BIT10 :1; /* Timer Count Register Bit 10 */\r
+ byte BIT9 :1; /* Timer Count Register Bit 9 */\r
+ byte BIT8 :1; /* Timer Count Register Bit 8 */\r
+ } Bits;\r
+ } TCNTHiSTR;\r
+ #define TCNTHi _TCNT.Overlap_STR.TCNTHiSTR.Byte\r
+ #define TCNTHi_BIT15 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT15\r
+ #define TCNTHi_BIT14 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT14\r
+ #define TCNTHi_BIT13 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT13\r
+ #define TCNTHi_BIT12 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT12\r
+ #define TCNTHi_BIT11 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT11\r
+ #define TCNTHi_BIT10 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT10\r
+ #define TCNTHi_BIT9 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT9\r
+ #define TCNTHi_BIT8 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT8\r
+ \r
+ /*** TCNTLo - Timer Count Register Low; 0x00000045 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* Timer Count Register Bit 0 */\r
+ byte BIT1 :1; /* Timer Count Register Bit 1 */\r
+ byte BIT2 :1; /* Timer Count Register Bit 2 */\r
+ byte BIT3 :1; /* Timer Count Register Bit 3 */\r
+ byte BIT4 :1; /* Timer Count Bit Register 4 */\r
+ byte BIT5 :1; /* Timer Count Bit Register 5 */\r
+ byte BIT6 :1; /* Timer Count Bit Register 6 */\r
+ byte BIT7 :1; /* Timer Count Bit Register 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } TCNTLoSTR;\r
+ #define TCNTLo _TCNT.Overlap_STR.TCNTLoSTR.Byte\r
+ #define TCNTLo_BIT0 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT0\r
+ #define TCNTLo_BIT1 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT1\r
+ #define TCNTLo_BIT2 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT2\r
+ #define TCNTLo_BIT3 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT3\r
+ #define TCNTLo_BIT4 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT4\r
+ #define TCNTLo_BIT5 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT5\r
+ #define TCNTLo_BIT6 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT6\r
+ #define TCNTLo_BIT7 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT7\r
+ #define TCNTLo_BIT _TCNT.Overlap_STR.TCNTLoSTR.MergedBits.grpBIT\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word grpBIT :16;\r
+ } MergedBits;\r
+} TCNTSTR;\r
+extern volatile TCNTSTR _TCNT @(REG_BASE + 0x00000044);\r
+#define TCNT _TCNT.Word\r
+#define TCNT_BIT _TCNT.MergedBits.grpBIT\r
+\r
+\r
+/*** TC0 - Timer Input Capture/Output Compare Register 0; 0x00000050 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** TC0Hi - Timer Input Capture/Output Compare Register 0 High; 0x00000050 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT8 :1; /* Timer Input Capture/Output Compare Register 0 Bit 8 */\r
+ byte BIT9 :1; /* Timer Input Capture/Output Compare Register 0 Bit 9 */\r
+ byte BIT10 :1; /* Timer Input Capture/Output Compare Register 0 Bit 10 */\r
+ byte BIT11 :1; /* Timer Input Capture/Output Compare Register 0 Bit 11 */\r
+ byte BIT12 :1; /* Timer Input Capture/Output Compare Register 0 Bit 12 */\r
+ byte BIT13 :1; /* Timer Input Capture/Output Compare Register 0 Bit 13 */\r
+ byte BIT14 :1; /* Timer Input Capture/Output Compare Register 0 Bit 14 */\r
+ byte BIT15 :1; /* Timer Input Capture/Output Compare Register 0 Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT_8 :8;\r
+ } MergedBits;\r
+ } TC0HiSTR;\r
+ #define TC0Hi _TC0.Overlap_STR.TC0HiSTR.Byte\r
+ #define TC0Hi_BIT8 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT8\r
+ #define TC0Hi_BIT9 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT9\r
+ #define TC0Hi_BIT10 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT10\r
+ #define TC0Hi_BIT11 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT11\r
+ #define TC0Hi_BIT12 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT12\r
+ #define TC0Hi_BIT13 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT13\r
+ #define TC0Hi_BIT14 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT14\r
+ #define TC0Hi_BIT15 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT15\r
+ #define TC0Hi_BIT_8 _TC0.Overlap_STR.TC0HiSTR.MergedBits.grpBIT_8\r
+ #define TC0Hi_BIT TC0Hi_BIT_8\r
+ \r
+ /*** TC0Lo - Timer Input Capture/Output Compare Register 0 Low; 0x00000051 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* Timer Input Capture/Output Compare Register 0 Bit 0 */\r
+ byte BIT1 :1; /* Timer Input Capture/Output Compare Register 0 Bit 1 */\r
+ byte BIT2 :1; /* Timer Input Capture/Output Compare Register 0 Bit 2 */\r
+ byte BIT3 :1; /* Timer Input Capture/Output Compare Register 0 Bit 3 */\r
+ byte BIT4 :1; /* Timer Input Capture/Output Compare Register 0 Bit 4 */\r
+ byte BIT5 :1; /* Timer Input Capture/Output Compare Register 0 Bit 5 */\r
+ byte BIT6 :1; /* Timer Input Capture/Output Compare Register 0 Bit 6 */\r
+ byte BIT7 :1; /* Timer Input Capture/Output Compare Register 0 Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } TC0LoSTR;\r
+ #define TC0Lo _TC0.Overlap_STR.TC0LoSTR.Byte\r
+ #define TC0Lo_BIT0 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT0\r
+ #define TC0Lo_BIT1 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT1\r
+ #define TC0Lo_BIT2 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT2\r
+ #define TC0Lo_BIT3 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT3\r
+ #define TC0Lo_BIT4 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT4\r
+ #define TC0Lo_BIT5 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT5\r
+ #define TC0Lo_BIT6 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT6\r
+ #define TC0Lo_BIT7 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT7\r
+ #define TC0Lo_BIT _TC0.Overlap_STR.TC0LoSTR.MergedBits.grpBIT\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word grpBIT :16;\r
+ } MergedBits;\r
+} TC0STR;\r
+extern volatile TC0STR _TC0 @(REG_BASE + 0x00000050);\r
+#define TC0 _TC0.Word\r
+#define TC0_BIT _TC0.MergedBits.grpBIT\r
+\r
+\r
+/*** TC1 - Timer Input Capture/Output Compare Register 1; 0x00000052 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** TC1Hi - Timer Input Capture/Output Compare Register 1 High; 0x00000052 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT8 :1; /* Timer Input Capture/Output Compare Register 1 Bit 8 */\r
+ byte BIT9 :1; /* Timer Input Capture/Output Compare Register 1 Bit 9 */\r
+ byte BIT10 :1; /* Timer Input Capture/Output Compare Register 1 Bit 10 */\r
+ byte BIT11 :1; /* Timer Input Capture/Output Compare Register 1 Bit 11 */\r
+ byte BIT12 :1; /* Timer Input Capture/Output Compare Register 1 Bit 12 */\r
+ byte BIT13 :1; /* Timer Input Capture/Output Compare Register 1 Bit 13 */\r
+ byte BIT14 :1; /* Timer Input Capture/Output Compare Register 1 Bit 14 */\r
+ byte BIT15 :1; /* Timer Input Capture/Output Compare Register 1 Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT_8 :8;\r
+ } MergedBits;\r
+ } TC1HiSTR;\r
+ #define TC1Hi _TC1.Overlap_STR.TC1HiSTR.Byte\r
+ #define TC1Hi_BIT8 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT8\r
+ #define TC1Hi_BIT9 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT9\r
+ #define TC1Hi_BIT10 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT10\r
+ #define TC1Hi_BIT11 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT11\r
+ #define TC1Hi_BIT12 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT12\r
+ #define TC1Hi_BIT13 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT13\r
+ #define TC1Hi_BIT14 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT14\r
+ #define TC1Hi_BIT15 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT15\r
+ #define TC1Hi_BIT_8 _TC1.Overlap_STR.TC1HiSTR.MergedBits.grpBIT_8\r
+ #define TC1Hi_BIT TC1Hi_BIT_8\r
+ \r
+ /*** TC1Lo - Timer Input Capture/Output Compare Register 1 Low; 0x00000053 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* Timer Input Capture/Output Compare Register 1 Bit 0 */\r
+ byte BIT1 :1; /* Timer Input Capture/Output Compare Register 1 Bit 1 */\r
+ byte BIT2 :1; /* Timer Input Capture/Output Compare Register 1 Bit 2 */\r
+ byte BIT3 :1; /* Timer Input Capture/Output Compare Register 1 Bit 3 */\r
+ byte BIT4 :1; /* Timer Input Capture/Output Compare Register 1 Bit 4 */\r
+ byte BIT5 :1; /* Timer Input Capture/Output Compare Register 1 Bit 5 */\r
+ byte BIT6 :1; /* Timer Input Capture/Output Compare Register 1 Bit 6 */\r
+ byte BIT7 :1; /* Timer Input Capture/Output Compare Register 1 Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } TC1LoSTR;\r
+ #define TC1Lo _TC1.Overlap_STR.TC1LoSTR.Byte\r
+ #define TC1Lo_BIT0 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT0\r
+ #define TC1Lo_BIT1 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT1\r
+ #define TC1Lo_BIT2 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT2\r
+ #define TC1Lo_BIT3 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT3\r
+ #define TC1Lo_BIT4 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT4\r
+ #define TC1Lo_BIT5 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT5\r
+ #define TC1Lo_BIT6 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT6\r
+ #define TC1Lo_BIT7 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT7\r
+ #define TC1Lo_BIT _TC1.Overlap_STR.TC1LoSTR.MergedBits.grpBIT\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word grpBIT :16;\r
+ } MergedBits;\r
+} TC1STR;\r
+extern volatile TC1STR _TC1 @(REG_BASE + 0x00000052);\r
+#define TC1 _TC1.Word\r
+#define TC1_BIT _TC1.MergedBits.grpBIT\r
+\r
+\r
+/*** TC2 - Timer Input Capture/Output Compare Register 2; 0x00000054 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** TC2Hi - Timer Input Capture/Output Compare Register 2 High; 0x00000054 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT8 :1; /* Timer Input Capture/Output Compare Register 2 Bit 8 */\r
+ byte BIT9 :1; /* Timer Input Capture/Output Compare Register 2 Bit 9 */\r
+ byte BIT10 :1; /* Timer Input Capture/Output Compare Register 2 Bit 10 */\r
+ byte BIT11 :1; /* Timer Input Capture/Output Compare Register 2 Bit 11 */\r
+ byte BIT12 :1; /* Timer Input Capture/Output Compare Register 2 Bit 12 */\r
+ byte BIT13 :1; /* Timer Input Capture/Output Compare Register 2 Bit 13 */\r
+ byte BIT14 :1; /* Timer Input Capture/Output Compare Register 2 Bit 14 */\r
+ byte BIT15 :1; /* Timer Input Capture/Output Compare Register 2 Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT_8 :8;\r
+ } MergedBits;\r
+ } TC2HiSTR;\r
+ #define TC2Hi _TC2.Overlap_STR.TC2HiSTR.Byte\r
+ #define TC2Hi_BIT8 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT8\r
+ #define TC2Hi_BIT9 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT9\r
+ #define TC2Hi_BIT10 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT10\r
+ #define TC2Hi_BIT11 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT11\r
+ #define TC2Hi_BIT12 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT12\r
+ #define TC2Hi_BIT13 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT13\r
+ #define TC2Hi_BIT14 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT14\r
+ #define TC2Hi_BIT15 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT15\r
+ #define TC2Hi_BIT_8 _TC2.Overlap_STR.TC2HiSTR.MergedBits.grpBIT_8\r
+ #define TC2Hi_BIT TC2Hi_BIT_8\r
+ \r
+ /*** TC2Lo - Timer Input Capture/Output Compare Register 2 Low; 0x00000055 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* Timer Input Capture/Output Compare Register 2 Bit 0 */\r
+ byte BIT1 :1; /* Timer Input Capture/Output Compare Register 2 Bit 1 */\r
+ byte BIT2 :1; /* Timer Input Capture/Output Compare Register 2 Bit 2 */\r
+ byte BIT3 :1; /* Timer Input Capture/Output Compare Register 2 Bit 3 */\r
+ byte BIT4 :1; /* Timer Input Capture/Output Compare Register 2 Bit 4 */\r
+ byte BIT5 :1; /* Timer Input Capture/Output Compare Register 2 Bit 5 */\r
+ byte BIT6 :1; /* Timer Input Capture/Output Compare Register 2 Bit 6 */\r
+ byte BIT7 :1; /* Timer Input Capture/Output Compare Register 2 Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } TC2LoSTR;\r
+ #define TC2Lo _TC2.Overlap_STR.TC2LoSTR.Byte\r
+ #define TC2Lo_BIT0 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT0\r
+ #define TC2Lo_BIT1 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT1\r
+ #define TC2Lo_BIT2 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT2\r
+ #define TC2Lo_BIT3 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT3\r
+ #define TC2Lo_BIT4 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT4\r
+ #define TC2Lo_BIT5 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT5\r
+ #define TC2Lo_BIT6 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT6\r
+ #define TC2Lo_BIT7 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT7\r
+ #define TC2Lo_BIT _TC2.Overlap_STR.TC2LoSTR.MergedBits.grpBIT\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word grpBIT :16;\r
+ } MergedBits;\r
+} TC2STR;\r
+extern volatile TC2STR _TC2 @(REG_BASE + 0x00000054);\r
+#define TC2 _TC2.Word\r
+#define TC2_BIT _TC2.MergedBits.grpBIT\r
+\r
+\r
+/*** TC3 - Timer Input Capture/Output Compare Register 3; 0x00000056 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** TC3Hi - Timer Input Capture/Output Compare Register 3 High; 0x00000056 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT8 :1; /* Timer Input Capture/Output Compare Register 3 Bit 8 */\r
+ byte BIT9 :1; /* Timer Input Capture/Output Compare Register 3 Bit 9 */\r
+ byte BIT10 :1; /* Timer Input Capture/Output Compare Register 3 Bit 10 */\r
+ byte BIT11 :1; /* Timer Input Capture/Output Compare Register 3 Bit 11 */\r
+ byte BIT12 :1; /* Timer Input Capture/Output Compare Register 3 Bit 12 */\r
+ byte BIT13 :1; /* Timer Input Capture/Output Compare Register 3 Bit 13 */\r
+ byte BIT14 :1; /* Timer Input Capture/Output Compare Register 3 Bit 14 */\r
+ byte BIT15 :1; /* Timer Input Capture/Output Compare Register 3 Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT_8 :8;\r
+ } MergedBits;\r
+ } TC3HiSTR;\r
+ #define TC3Hi _TC3.Overlap_STR.TC3HiSTR.Byte\r
+ #define TC3Hi_BIT8 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT8\r
+ #define TC3Hi_BIT9 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT9\r
+ #define TC3Hi_BIT10 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT10\r
+ #define TC3Hi_BIT11 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT11\r
+ #define TC3Hi_BIT12 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT12\r
+ #define TC3Hi_BIT13 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT13\r
+ #define TC3Hi_BIT14 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT14\r
+ #define TC3Hi_BIT15 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT15\r
+ #define TC3Hi_BIT_8 _TC3.Overlap_STR.TC3HiSTR.MergedBits.grpBIT_8\r
+ #define TC3Hi_BIT TC3Hi_BIT_8\r
+ \r
+ /*** TC3Lo - Timer Input Capture/Output Compare Register 3 Low; 0x00000057 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* Timer Input Capture/Output Compare Register 3 Bit 0 */\r
+ byte BIT1 :1; /* Timer Input Capture/Output Compare Register 3 Bit 1 */\r
+ byte BIT2 :1; /* Timer Input Capture/Output Compare Register 3 Bit 2 */\r
+ byte BIT3 :1; /* Timer Input Capture/Output Compare Register 3 Bit 3 */\r
+ byte BIT4 :1; /* Timer Input Capture/Output Compare Register 3 Bit 4 */\r
+ byte BIT5 :1; /* Timer Input Capture/Output Compare Register 3 Bit 5 */\r
+ byte BIT6 :1; /* Timer Input Capture/Output Compare Register 3 Bit 6 */\r
+ byte BIT7 :1; /* Timer Input Capture/Output Compare Register 3 Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } TC3LoSTR;\r
+ #define TC3Lo _TC3.Overlap_STR.TC3LoSTR.Byte\r
+ #define TC3Lo_BIT0 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT0\r
+ #define TC3Lo_BIT1 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT1\r
+ #define TC3Lo_BIT2 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT2\r
+ #define TC3Lo_BIT3 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT3\r
+ #define TC3Lo_BIT4 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT4\r
+ #define TC3Lo_BIT5 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT5\r
+ #define TC3Lo_BIT6 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT6\r
+ #define TC3Lo_BIT7 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT7\r
+ #define TC3Lo_BIT _TC3.Overlap_STR.TC3LoSTR.MergedBits.grpBIT\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word grpBIT :16;\r
+ } MergedBits;\r
+} TC3STR;\r
+extern volatile TC3STR _TC3 @(REG_BASE + 0x00000056);\r
+#define TC3 _TC3.Word\r
+#define TC3_BIT _TC3.MergedBits.grpBIT\r
+\r
+\r
+/*** TC4 - Timer Input Capture/Output Compare Register 4; 0x00000058 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** TC4Hi - Timer Input Capture/Output Compare Register 4 High; 0x00000058 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT8 :1; /* Timer Input Capture/Output Compare Register 4 Bit 8 */\r
+ byte BIT9 :1; /* Timer Input Capture/Output Compare Register 4 Bit 9 */\r
+ byte BIT10 :1; /* Timer Input Capture/Output Compare Register 4 Bit 10 */\r
+ byte BIT11 :1; /* Timer Input Capture/Output Compare Register 4 Bit 11 */\r
+ byte BIT12 :1; /* Timer Input Capture/Output Compare Register 4 Bit 12 */\r
+ byte BIT13 :1; /* Timer Input Capture/Output Compare Register 4 Bit 13 */\r
+ byte BIT14 :1; /* Timer Input Capture/Output Compare Register 4 Bit 14 */\r
+ byte BIT15 :1; /* Timer Input Capture/Output Compare Register 4 Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT_8 :8;\r
+ } MergedBits;\r
+ } TC4HiSTR;\r
+ #define TC4Hi _TC4.Overlap_STR.TC4HiSTR.Byte\r
+ #define TC4Hi_BIT8 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT8\r
+ #define TC4Hi_BIT9 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT9\r
+ #define TC4Hi_BIT10 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT10\r
+ #define TC4Hi_BIT11 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT11\r
+ #define TC4Hi_BIT12 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT12\r
+ #define TC4Hi_BIT13 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT13\r
+ #define TC4Hi_BIT14 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT14\r
+ #define TC4Hi_BIT15 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT15\r
+ #define TC4Hi_BIT_8 _TC4.Overlap_STR.TC4HiSTR.MergedBits.grpBIT_8\r
+ #define TC4Hi_BIT TC4Hi_BIT_8\r
+ \r
+ /*** TC4Lo - Timer Input Capture/Output Compare Register 4 Low; 0x00000059 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* Timer Input Capture/Output Compare Register 4 Bit 0 */\r
+ byte BIT1 :1; /* Timer Input Capture/Output Compare Register 4 Bit 1 */\r
+ byte BIT2 :1; /* Timer Input Capture/Output Compare Register 4 Bit 2 */\r
+ byte BIT3 :1; /* Timer Input Capture/Output Compare Register 4 Bit 3 */\r
+ byte BIT4 :1; /* Timer Input Capture/Output Compare Register 4 Bit 4 */\r
+ byte BIT5 :1; /* Timer Input Capture/Output Compare Register 4 Bit 5 */\r
+ byte BIT6 :1; /* Timer Input Capture/Output Compare Register 4 Bit 6 */\r
+ byte BIT7 :1; /* Timer Input Capture/Output Compare Register 4 Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } TC4LoSTR;\r
+ #define TC4Lo _TC4.Overlap_STR.TC4LoSTR.Byte\r
+ #define TC4Lo_BIT0 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT0\r
+ #define TC4Lo_BIT1 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT1\r
+ #define TC4Lo_BIT2 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT2\r
+ #define TC4Lo_BIT3 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT3\r
+ #define TC4Lo_BIT4 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT4\r
+ #define TC4Lo_BIT5 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT5\r
+ #define TC4Lo_BIT6 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT6\r
+ #define TC4Lo_BIT7 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT7\r
+ #define TC4Lo_BIT _TC4.Overlap_STR.TC4LoSTR.MergedBits.grpBIT\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word grpBIT :16;\r
+ } MergedBits;\r
+} TC4STR;\r
+extern volatile TC4STR _TC4 @(REG_BASE + 0x00000058);\r
+#define TC4 _TC4.Word\r
+#define TC4_BIT _TC4.MergedBits.grpBIT\r
+\r
+\r
+/*** TC5 - Timer Input Capture/Output Compare Register 5; 0x0000005A ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** TC5Hi - Timer Input Capture/Output Compare Register 5 High; 0x0000005A ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT8 :1; /* Timer Input Capture/Output Compare Register 5 Bit 8 */\r
+ byte BIT9 :1; /* Timer Input Capture/Output Compare Register 5 Bit 9 */\r
+ byte BIT10 :1; /* Timer Input Capture/Output Compare Register 5 Bit 10 */\r
+ byte BIT11 :1; /* Timer Input Capture/Output Compare Register 5 Bit 11 */\r
+ byte BIT12 :1; /* Timer Input Capture/Output Compare Register 5 Bit 12 */\r
+ byte BIT13 :1; /* Timer Input Capture/Output Compare Register 5 Bit 13 */\r
+ byte BIT14 :1; /* Timer Input Capture/Output Compare Register 5 Bit 14 */\r
+ byte BIT15 :1; /* Timer Input Capture/Output Compare Register 5 Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT_8 :8;\r
+ } MergedBits;\r
+ } TC5HiSTR;\r
+ #define TC5Hi _TC5.Overlap_STR.TC5HiSTR.Byte\r
+ #define TC5Hi_BIT8 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT8\r
+ #define TC5Hi_BIT9 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT9\r
+ #define TC5Hi_BIT10 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT10\r
+ #define TC5Hi_BIT11 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT11\r
+ #define TC5Hi_BIT12 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT12\r
+ #define TC5Hi_BIT13 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT13\r
+ #define TC5Hi_BIT14 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT14\r
+ #define TC5Hi_BIT15 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT15\r
+ #define TC5Hi_BIT_8 _TC5.Overlap_STR.TC5HiSTR.MergedBits.grpBIT_8\r
+ #define TC5Hi_BIT TC5Hi_BIT_8\r
+ \r
+ /*** TC5Lo - Timer Input Capture/Output Compare Register 5 Low; 0x0000005B ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* Timer Input Capture/Output Compare Register 5 Bit 0 */\r
+ byte BIT1 :1; /* Timer Input Capture/Output Compare Register 5 Bit 1 */\r
+ byte BIT2 :1; /* Timer Input Capture/Output Compare Register 5 Bit 2 */\r
+ byte BIT3 :1; /* Timer Input Capture/Output Compare Register 5 Bit 3 */\r
+ byte BIT4 :1; /* Timer Input Capture/Output Compare Register 5 Bit 4 */\r
+ byte BIT5 :1; /* Timer Input Capture/Output Compare Register 5 Bit 5 */\r
+ byte BIT6 :1; /* Timer Input Capture/Output Compare Register 5 Bit 6 */\r
+ byte BIT7 :1; /* Timer Input Capture/Output Compare Register 5 Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } TC5LoSTR;\r
+ #define TC5Lo _TC5.Overlap_STR.TC5LoSTR.Byte\r
+ #define TC5Lo_BIT0 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT0\r
+ #define TC5Lo_BIT1 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT1\r
+ #define TC5Lo_BIT2 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT2\r
+ #define TC5Lo_BIT3 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT3\r
+ #define TC5Lo_BIT4 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT4\r
+ #define TC5Lo_BIT5 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT5\r
+ #define TC5Lo_BIT6 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT6\r
+ #define TC5Lo_BIT7 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT7\r
+ #define TC5Lo_BIT _TC5.Overlap_STR.TC5LoSTR.MergedBits.grpBIT\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word grpBIT :16;\r
+ } MergedBits;\r
+} TC5STR;\r
+extern volatile TC5STR _TC5 @(REG_BASE + 0x0000005A);\r
+#define TC5 _TC5.Word\r
+#define TC5_BIT _TC5.MergedBits.grpBIT\r
+\r
+\r
+/*** TC6 - Timer Input Capture/Output Compare Register 6; 0x0000005C ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** TC6Hi - Timer Input Capture/Output Compare Register 6 High; 0x0000005C ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT8 :1; /* Timer Input Capture/Output Compare Register 6 Bit 8 */\r
+ byte BIT9 :1; /* Timer Input Capture/Output Compare Register 6 Bit 9 */\r
+ byte BIT10 :1; /* Timer Input Capture/Output Compare Register 6 Bit 10 */\r
+ byte BIT11 :1; /* Timer Input Capture/Output Compare Register 6 Bit 11 */\r
+ byte BIT12 :1; /* Timer Input Capture/Output Compare Register 6 Bit 12 */\r
+ byte BIT13 :1; /* Timer Input Capture/Output Compare Register 6 Bit 13 */\r
+ byte BIT14 :1; /* Timer Input Capture/Output Compare Register 6 Bit 14 */\r
+ byte BIT15 :1; /* Timer Input Capture/Output Compare Register 6 Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT_8 :8;\r
+ } MergedBits;\r
+ } TC6HiSTR;\r
+ #define TC6Hi _TC6.Overlap_STR.TC6HiSTR.Byte\r
+ #define TC6Hi_BIT8 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT8\r
+ #define TC6Hi_BIT9 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT9\r
+ #define TC6Hi_BIT10 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT10\r
+ #define TC6Hi_BIT11 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT11\r
+ #define TC6Hi_BIT12 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT12\r
+ #define TC6Hi_BIT13 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT13\r
+ #define TC6Hi_BIT14 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT14\r
+ #define TC6Hi_BIT15 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT15\r
+ #define TC6Hi_BIT_8 _TC6.Overlap_STR.TC6HiSTR.MergedBits.grpBIT_8\r
+ #define TC6Hi_BIT TC6Hi_BIT_8\r
+ \r
+ /*** TC6Lo - Timer Input Capture/Output Compare Register 6 Low; 0x0000005D ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* Timer Input Capture/Output Compare Register 6 Bit 0 */\r
+ byte BIT1 :1; /* Timer Input Capture/Output Compare Register 6 Bit 1 */\r
+ byte BIT2 :1; /* Timer Input Capture/Output Compare Register 6 Bit 2 */\r
+ byte BIT3 :1; /* Timer Input Capture/Output Compare Register 6 Bit 3 */\r
+ byte BIT4 :1; /* Timer Input Capture/Output Compare Register 6 Bit 4 */\r
+ byte BIT5 :1; /* Timer Input Capture/Output Compare Register 6 Bit 5 */\r
+ byte BIT6 :1; /* Timer Input Capture/Output Compare Register 6 Bit 6 */\r
+ byte BIT7 :1; /* Timer Input Capture/Output Compare Register 6 Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } TC6LoSTR;\r
+ #define TC6Lo _TC6.Overlap_STR.TC6LoSTR.Byte\r
+ #define TC6Lo_BIT0 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT0\r
+ #define TC6Lo_BIT1 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT1\r
+ #define TC6Lo_BIT2 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT2\r
+ #define TC6Lo_BIT3 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT3\r
+ #define TC6Lo_BIT4 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT4\r
+ #define TC6Lo_BIT5 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT5\r
+ #define TC6Lo_BIT6 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT6\r
+ #define TC6Lo_BIT7 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT7\r
+ #define TC6Lo_BIT _TC6.Overlap_STR.TC6LoSTR.MergedBits.grpBIT\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word grpBIT :16;\r
+ } MergedBits;\r
+} TC6STR;\r
+extern volatile TC6STR _TC6 @(REG_BASE + 0x0000005C);\r
+#define TC6 _TC6.Word\r
+#define TC6_BIT _TC6.MergedBits.grpBIT\r
+\r
+\r
+/*** TC7 - Timer Input Capture/Output Compare Register 7; 0x0000005E ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** TC7Hi - Timer Input Capture/Output Compare Register 7 High; 0x0000005E ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT8 :1; /* Timer Input Capture/Output Compare Register 7 Bit 8 */\r
+ byte BIT9 :1; /* Timer Input Capture/Output Compare Register 7 Bit 9 */\r
+ byte BIT10 :1; /* Timer Input Capture/Output Compare Register 7 Bit 10 */\r
+ byte BIT11 :1; /* Timer Input Capture/Output Compare Register 7 Bit 11 */\r
+ byte BIT12 :1; /* Timer Input Capture/Output Compare Register 7 Bit 12 */\r
+ byte BIT13 :1; /* Timer Input Capture/Output Compare Register 7 Bit 13 */\r
+ byte BIT14 :1; /* Timer Input Capture/Output Compare Register 7 Bit 14 */\r
+ byte BIT15 :1; /* Timer Input Capture/Output Compare Register 7 Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT_8 :8;\r
+ } MergedBits;\r
+ } TC7HiSTR;\r
+ #define TC7Hi _TC7.Overlap_STR.TC7HiSTR.Byte\r
+ #define TC7Hi_BIT8 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT8\r
+ #define TC7Hi_BIT9 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT9\r
+ #define TC7Hi_BIT10 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT10\r
+ #define TC7Hi_BIT11 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT11\r
+ #define TC7Hi_BIT12 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT12\r
+ #define TC7Hi_BIT13 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT13\r
+ #define TC7Hi_BIT14 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT14\r
+ #define TC7Hi_BIT15 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT15\r
+ #define TC7Hi_BIT_8 _TC7.Overlap_STR.TC7HiSTR.MergedBits.grpBIT_8\r
+ #define TC7Hi_BIT TC7Hi_BIT_8\r
+ \r
+ /*** TC7Lo - Timer Input Capture/Output Compare Register 7 Low; 0x0000005F ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* Timer Input Capture/Output Compare Register 7 Bit 0 */\r
+ byte BIT1 :1; /* Timer Input Capture/Output Compare Register 7 Bit 1 */\r
+ byte BIT2 :1; /* Timer Input Capture/Output Compare Register 7 Bit 2 */\r
+ byte BIT3 :1; /* Timer Input Capture/Output Compare Register 7 Bit 3 */\r
+ byte BIT4 :1; /* Timer Input Capture/Output Compare Register 7 Bit 4 */\r
+ byte BIT5 :1; /* Timer Input Capture/Output Compare Register 7 Bit 5 */\r
+ byte BIT6 :1; /* Timer Input Capture/Output Compare Register 7 Bit 6 */\r
+ byte BIT7 :1; /* Timer Input Capture/Output Compare Register 7 Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } TC7LoSTR;\r
+ #define TC7Lo _TC7.Overlap_STR.TC7LoSTR.Byte\r
+ #define TC7Lo_BIT0 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT0\r
+ #define TC7Lo_BIT1 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT1\r
+ #define TC7Lo_BIT2 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT2\r
+ #define TC7Lo_BIT3 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT3\r
+ #define TC7Lo_BIT4 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT4\r
+ #define TC7Lo_BIT5 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT5\r
+ #define TC7Lo_BIT6 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT6\r
+ #define TC7Lo_BIT7 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT7\r
+ #define TC7Lo_BIT _TC7.Overlap_STR.TC7LoSTR.MergedBits.grpBIT\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word grpBIT :16;\r
+ } MergedBits;\r
+} TC7STR;\r
+extern volatile TC7STR _TC7 @(REG_BASE + 0x0000005E);\r
+#define TC7 _TC7.Word\r
+#define TC7_BIT _TC7.MergedBits.grpBIT\r
+\r
+\r
+/*** PACN32 - Pulse Accumulators Count 32 Register; 0x00000062 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** PACN3 - Pulse Accumulators Count 3 Register; 0x00000062 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } PACN3STR;\r
+ #define PACN3 _PACN32.Overlap_STR.PACN3STR.Byte\r
+ #define PACN3_BIT _PACN32.Overlap_STR.PACN3STR.MergedBits.grpBIT\r
+ \r
+ /*** PACN2 - Pulse Accumulators Count 2 Register; 0x00000063 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } PACN2STR;\r
+ #define PACN2 _PACN32.Overlap_STR.PACN2STR.Byte\r
+ #define PACN2_BIT _PACN32.Overlap_STR.PACN2STR.MergedBits.grpBIT\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word grpBIT :16;\r
+ } MergedBits;\r
+} PACN32STR;\r
+extern volatile PACN32STR _PACN32 @(REG_BASE + 0x00000062);\r
+#define PACN32 _PACN32.Word\r
+#define PACN32_BIT _PACN32.MergedBits.grpBIT\r
+\r
+\r
+/*** PACN10 - Pulse Accumulators Count 10 Register; 0x00000064 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** PACN1 - Pulse Accumulators Count 1 Register; 0x00000064 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } PACN1STR;\r
+ #define PACN1 _PACN10.Overlap_STR.PACN1STR.Byte\r
+ #define PACN1_BIT _PACN10.Overlap_STR.PACN1STR.MergedBits.grpBIT\r
+ \r
+ /*** PACN0 - Pulse Accumulators Count 0 Register; 0x00000065 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } PACN0STR;\r
+ #define PACN0 _PACN10.Overlap_STR.PACN0STR.Byte\r
+ #define PACN0_BIT _PACN10.Overlap_STR.PACN0STR.MergedBits.grpBIT\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word grpBIT :16;\r
+ } MergedBits;\r
+} PACN10STR;\r
+extern volatile PACN10STR _PACN10 @(REG_BASE + 0x00000064);\r
+#define PACN10 _PACN10.Word\r
+#define PACN10_BIT _PACN10.MergedBits.grpBIT\r
+\r
+\r
+/*** PA32H - 8-Bit Pulse Accumulators Holding 32 Register; 0x00000072 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** PA3H - 8-Bit Pulse Accumulators Holding 3 Register; 0x00000072 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* Pulse Accumulator Bit 0 */\r
+ byte BIT1 :1; /* Pulse Accumulator Bit 1 */\r
+ byte BIT2 :1; /* Pulse Accumulator Bit 2 */\r
+ byte BIT3 :1; /* Pulse Accumulator Bit 3 */\r
+ byte BIT4 :1; /* Pulse Accumulator Bit 4 */\r
+ byte BIT5 :1; /* Pulse Accumulator Bit 5 */\r
+ byte BIT6 :1; /* Pulse Accumulator Bit 6 */\r
+ byte BIT7 :1; /* Pulse Accumulator Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } PA3HSTR;\r
+ #define PA3H _PA32H.Overlap_STR.PA3HSTR.Byte\r
+ #define PA3H_BIT0 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT0\r
+ #define PA3H_BIT1 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT1\r
+ #define PA3H_BIT2 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT2\r
+ #define PA3H_BIT3 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT3\r
+ #define PA3H_BIT4 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT4\r
+ #define PA3H_BIT5 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT5\r
+ #define PA3H_BIT6 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT6\r
+ #define PA3H_BIT7 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT7\r
+ #define PA3H_BIT _PA32H.Overlap_STR.PA3HSTR.MergedBits.grpBIT\r
+ \r
+ /*** PA2H - 8-Bit Pulse Accumulators Holding 2 Register; 0x00000073 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* Pulse Accumulator Bit 0 */\r
+ byte BIT1 :1; /* Pulse Accumulator Bit 1 */\r
+ byte BIT2 :1; /* Pulse Accumulator Bit 2 */\r
+ byte BIT3 :1; /* Pulse Accumulator Bit 3 */\r
+ byte BIT4 :1; /* Pulse Accumulator Bit 4 */\r
+ byte BIT5 :1; /* Pulse Accumulator Bit 5 */\r
+ byte BIT6 :1; /* Pulse Accumulator Bit 6 */\r
+ byte BIT7 :1; /* Pulse Accumulator Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } PA2HSTR;\r
+ #define PA2H _PA32H.Overlap_STR.PA2HSTR.Byte\r
+ #define PA2H_BIT0 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT0\r
+ #define PA2H_BIT1 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT1\r
+ #define PA2H_BIT2 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT2\r
+ #define PA2H_BIT3 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT3\r
+ #define PA2H_BIT4 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT4\r
+ #define PA2H_BIT5 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT5\r
+ #define PA2H_BIT6 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT6\r
+ #define PA2H_BIT7 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT7\r
+ #define PA2H_BIT _PA32H.Overlap_STR.PA2HSTR.MergedBits.grpBIT\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word BIT0 :1; /* Pulse Accumulator Bit 0 */\r
+ word BIT1 :1; /* Pulse Accumulator Bit 1 */\r
+ word BIT2 :1; /* Pulse Accumulator Bit 2 */\r
+ word BIT3 :1; /* Pulse Accumulator Bit 3 */\r
+ word BIT4 :1; /* Pulse Accumulator Bit 4 */\r
+ word BIT5 :1; /* Pulse Accumulator Bit 5 */\r
+ word BIT6 :1; /* Pulse Accumulator Bit 6 */\r
+ word BIT7 :1; /* Pulse Accumulator Bit 7 */\r
+ word BIT8 :1; /* Pulse Accumulator Bit 8 */\r
+ word BIT9 :1; /* Pulse Accumulator Bit 9 */\r
+ word BIT10 :1; /* Pulse Accumulator Bit 10 */\r
+ word BIT11 :1; /* Pulse Accumulator Bit 11 */\r
+ word BIT12 :1; /* Pulse Accumulator Bit 12 */\r
+ word BIT13 :1; /* Pulse Accumulator Bit 13 */\r
+ word BIT14 :1; /* Pulse Accumulator Bit 14 */\r
+ word BIT15 :1; /* Pulse Accumulator Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ word grpBIT :16;\r
+ } MergedBits;\r
+} PA32HSTR;\r
+extern volatile PA32HSTR _PA32H @(REG_BASE + 0x00000072);\r
+#define PA32H _PA32H.Word\r
+#define PA32H_BIT0 _PA32H.Bits.BIT0\r
+#define PA32H_BIT1 _PA32H.Bits.BIT1\r
+#define PA32H_BIT2 _PA32H.Bits.BIT2\r
+#define PA32H_BIT3 _PA32H.Bits.BIT3\r
+#define PA32H_BIT4 _PA32H.Bits.BIT4\r
+#define PA32H_BIT5 _PA32H.Bits.BIT5\r
+#define PA32H_BIT6 _PA32H.Bits.BIT6\r
+#define PA32H_BIT7 _PA32H.Bits.BIT7\r
+#define PA32H_BIT8 _PA32H.Bits.BIT8\r
+#define PA32H_BIT9 _PA32H.Bits.BIT9\r
+#define PA32H_BIT10 _PA32H.Bits.BIT10\r
+#define PA32H_BIT11 _PA32H.Bits.BIT11\r
+#define PA32H_BIT12 _PA32H.Bits.BIT12\r
+#define PA32H_BIT13 _PA32H.Bits.BIT13\r
+#define PA32H_BIT14 _PA32H.Bits.BIT14\r
+#define PA32H_BIT15 _PA32H.Bits.BIT15\r
+#define PA32H_BIT _PA32H.MergedBits.grpBIT\r
+\r
+\r
+/*** PA10H - 8-Bit Pulse Accumulators Holding 10 Register; 0x00000074 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** PA1H - 8-Bit Pulse Accumulators Holding 1 Register; 0x00000074 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* Pulse Accumulator Bit 0 */\r
+ byte BIT1 :1; /* Pulse Accumulator Bit 1 */\r
+ byte BIT2 :1; /* Pulse Accumulator Bit 2 */\r
+ byte BIT3 :1; /* Pulse Accumulator Bit 3 */\r
+ byte BIT4 :1; /* Pulse Accumulator Bit 4 */\r
+ byte BIT5 :1; /* Pulse Accumulator Bit 5 */\r
+ byte BIT6 :1; /* Pulse Accumulator Bit 6 */\r
+ byte BIT7 :1; /* Pulse Accumulator Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } PA1HSTR;\r
+ #define PA1H _PA10H.Overlap_STR.PA1HSTR.Byte\r
+ #define PA1H_BIT0 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT0\r
+ #define PA1H_BIT1 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT1\r
+ #define PA1H_BIT2 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT2\r
+ #define PA1H_BIT3 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT3\r
+ #define PA1H_BIT4 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT4\r
+ #define PA1H_BIT5 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT5\r
+ #define PA1H_BIT6 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT6\r
+ #define PA1H_BIT7 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT7\r
+ #define PA1H_BIT _PA10H.Overlap_STR.PA1HSTR.MergedBits.grpBIT\r
+ \r
+ /*** PA0H - 8-Bit Pulse Accumulators Holding 0 Register; 0x00000075 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* Pulse Accumulator Bit 0 */\r
+ byte BIT1 :1; /* Pulse Accumulator Bit 1 */\r
+ byte BIT2 :1; /* Pulse Accumulator Bit 2 */\r
+ byte BIT3 :1; /* Pulse Accumulator Bit 3 */\r
+ byte BIT4 :1; /* Pulse Accumulator Bit 4 */\r
+ byte BIT5 :1; /* Pulse Accumulator Bit 5 */\r
+ byte BIT6 :1; /* Pulse Accumulator Bit 6 */\r
+ byte BIT7 :1; /* Pulse Accumulator Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } PA0HSTR;\r
+ #define PA0H _PA10H.Overlap_STR.PA0HSTR.Byte\r
+ #define PA0H_BIT0 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT0\r
+ #define PA0H_BIT1 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT1\r
+ #define PA0H_BIT2 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT2\r
+ #define PA0H_BIT3 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT3\r
+ #define PA0H_BIT4 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT4\r
+ #define PA0H_BIT5 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT5\r
+ #define PA0H_BIT6 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT6\r
+ #define PA0H_BIT7 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT7\r
+ #define PA0H_BIT _PA10H.Overlap_STR.PA0HSTR.MergedBits.grpBIT\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word BIT0 :1; /* Pulse Accumulator Bit 0 */\r
+ word BIT1 :1; /* Pulse Accumulator Bit 1 */\r
+ word BIT2 :1; /* Pulse Accumulator Bit 2 */\r
+ word BIT3 :1; /* Pulse Accumulator Bit 3 */\r
+ word BIT4 :1; /* Pulse Accumulator Bit 4 */\r
+ word BIT5 :1; /* Pulse Accumulator Bit 5 */\r
+ word BIT6 :1; /* Pulse Accumulator Bit 6 */\r
+ word BIT7 :1; /* Pulse Accumulator Bit 7 */\r
+ word BIT8 :1; /* Pulse Accumulator Bit 8 */\r
+ word BIT9 :1; /* Pulse Accumulator Bit 9 */\r
+ word BIT10 :1; /* Pulse Accumulator Bit 10 */\r
+ word BIT11 :1; /* Pulse Accumulator Bit 11 */\r
+ word BIT12 :1; /* Pulse Accumulator Bit 12 */\r
+ word BIT13 :1; /* Pulse Accumulator Bit 13 */\r
+ word BIT14 :1; /* Pulse Accumulator Bit 14 */\r
+ word BIT15 :1; /* Pulse Accumulator Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ word grpBIT :16;\r
+ } MergedBits;\r
+} PA10HSTR;\r
+extern volatile PA10HSTR _PA10H @(REG_BASE + 0x00000074);\r
+#define PA10H _PA10H.Word\r
+#define PA10H_BIT0 _PA10H.Bits.BIT0\r
+#define PA10H_BIT1 _PA10H.Bits.BIT1\r
+#define PA10H_BIT2 _PA10H.Bits.BIT2\r
+#define PA10H_BIT3 _PA10H.Bits.BIT3\r
+#define PA10H_BIT4 _PA10H.Bits.BIT4\r
+#define PA10H_BIT5 _PA10H.Bits.BIT5\r
+#define PA10H_BIT6 _PA10H.Bits.BIT6\r
+#define PA10H_BIT7 _PA10H.Bits.BIT7\r
+#define PA10H_BIT8 _PA10H.Bits.BIT8\r
+#define PA10H_BIT9 _PA10H.Bits.BIT9\r
+#define PA10H_BIT10 _PA10H.Bits.BIT10\r
+#define PA10H_BIT11 _PA10H.Bits.BIT11\r
+#define PA10H_BIT12 _PA10H.Bits.BIT12\r
+#define PA10H_BIT13 _PA10H.Bits.BIT13\r
+#define PA10H_BIT14 _PA10H.Bits.BIT14\r
+#define PA10H_BIT15 _PA10H.Bits.BIT15\r
+#define PA10H_BIT _PA10H.MergedBits.grpBIT\r
+\r
+\r
+/*** MCCNT - Modulus Down-Counter Count Register; 0x00000076 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** MCCNThi - Modulus Down-Counter Count Register High; 0x00000076 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT8 :1; /* Modulus Down-Counter Bit 8 */\r
+ byte BIT9 :1; /* Modulus Down-Counter Bit 9 */\r
+ byte BIT10 :1; /* Modulus Down-Counter Bit 10 */\r
+ byte BIT11 :1; /* Modulus Down-Counter Bit 11 */\r
+ byte BIT12 :1; /* Modulus Down-Counter Bit 12 */\r
+ byte BIT13 :1; /* Modulus Down-Counter Bit 13 */\r
+ byte BIT14 :1; /* Modulus Down-Counter Bit 14 */\r
+ byte BIT15 :1; /* Modulus Down-Counter Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT_8 :8;\r
+ } MergedBits;\r
+ } MCCNThiSTR;\r
+ #define MCCNThi _MCCNT.Overlap_STR.MCCNThiSTR.Byte\r
+ #define MCCNThi_BIT8 _MCCNT.Overlap_STR.MCCNThiSTR.Bits.BIT8\r
+ #define MCCNThi_BIT9 _MCCNT.Overlap_STR.MCCNThiSTR.Bits.BIT9\r
+ #define MCCNThi_BIT10 _MCCNT.Overlap_STR.MCCNThiSTR.Bits.BIT10\r
+ #define MCCNThi_BIT11 _MCCNT.Overlap_STR.MCCNThiSTR.Bits.BIT11\r
+ #define MCCNThi_BIT12 _MCCNT.Overlap_STR.MCCNThiSTR.Bits.BIT12\r
+ #define MCCNThi_BIT13 _MCCNT.Overlap_STR.MCCNThiSTR.Bits.BIT13\r
+ #define MCCNThi_BIT14 _MCCNT.Overlap_STR.MCCNThiSTR.Bits.BIT14\r
+ #define MCCNThi_BIT15 _MCCNT.Overlap_STR.MCCNThiSTR.Bits.BIT15\r
+ #define MCCNThi_BIT_8 _MCCNT.Overlap_STR.MCCNThiSTR.MergedBits.grpBIT_8\r
+ #define MCCNThi_BIT MCCNThi_BIT_8\r
+ \r
+ /*** MCCNTlo - Modulus Down-Counter Count Register Low; 0x00000077 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* Modulus Down-Counter Bit 0 */\r
+ byte BIT1 :1; /* Modulus Down-Counter Bit 1 */\r
+ byte BIT2 :1; /* Modulus Down-Counter Bit 2 */\r
+ byte BIT3 :1; /* Modulus Down-Counter Bit 3 */\r
+ byte BIT4 :1; /* Modulus Down-Counter Bit 4 */\r
+ byte BIT5 :1; /* Modulus Down-Counter Bit 5 */\r
+ byte BIT6 :1; /* Modulus Down-Counter Bit 6 */\r
+ byte BIT7 :1; /* Modulus Down-Counter Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } MCCNTloSTR;\r
+ #define MCCNTlo _MCCNT.Overlap_STR.MCCNTloSTR.Byte\r
+ #define MCCNTlo_BIT0 _MCCNT.Overlap_STR.MCCNTloSTR.Bits.BIT0\r
+ #define MCCNTlo_BIT1 _MCCNT.Overlap_STR.MCCNTloSTR.Bits.BIT1\r
+ #define MCCNTlo_BIT2 _MCCNT.Overlap_STR.MCCNTloSTR.Bits.BIT2\r
+ #define MCCNTlo_BIT3 _MCCNT.Overlap_STR.MCCNTloSTR.Bits.BIT3\r
+ #define MCCNTlo_BIT4 _MCCNT.Overlap_STR.MCCNTloSTR.Bits.BIT4\r
+ #define MCCNTlo_BIT5 _MCCNT.Overlap_STR.MCCNTloSTR.Bits.BIT5\r
+ #define MCCNTlo_BIT6 _MCCNT.Overlap_STR.MCCNTloSTR.Bits.BIT6\r
+ #define MCCNTlo_BIT7 _MCCNT.Overlap_STR.MCCNTloSTR.Bits.BIT7\r
+ #define MCCNTlo_BIT _MCCNT.Overlap_STR.MCCNTloSTR.MergedBits.grpBIT\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word grpBIT :16;\r
+ } MergedBits;\r
+} MCCNTSTR;\r
+extern volatile MCCNTSTR _MCCNT @(REG_BASE + 0x00000076);\r
+#define MCCNT _MCCNT.Word\r
+#define MCCNT_BIT _MCCNT.MergedBits.grpBIT\r
+\r
+\r
+/*** TC0H - Timer Input Capture Holding Registers 0; 0x00000078 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** TC0Hhi - Timer Input Capture Holding Registers 0 High; 0x00000078 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT8 :1; /* Timer Input Capture Holding Bit 8 */\r
+ byte BIT9 :1; /* Timer Input Capture Holding Bit 9 */\r
+ byte BIT10 :1; /* Timer Input Capture Holding Bit 10 */\r
+ byte BIT11 :1; /* Timer Input Capture Holding Bit 11 */\r
+ byte BIT12 :1; /* Timer Input Capture Holding Bit 12 */\r
+ byte BIT13 :1; /* Timer Input Capture Holding Bit 13 */\r
+ byte BIT14 :1; /* Timer Input Capture Holding Bit 14 */\r
+ byte BIT15 :1; /* Timer Input Capture Holding Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT_8 :8;\r
+ } MergedBits;\r
+ } TC0HhiSTR;\r
+ #define TC0Hhi _TC0H.Overlap_STR.TC0HhiSTR.Byte\r
+ #define TC0Hhi_BIT8 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT8\r
+ #define TC0Hhi_BIT9 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT9\r
+ #define TC0Hhi_BIT10 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT10\r
+ #define TC0Hhi_BIT11 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT11\r
+ #define TC0Hhi_BIT12 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT12\r
+ #define TC0Hhi_BIT13 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT13\r
+ #define TC0Hhi_BIT14 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT14\r
+ #define TC0Hhi_BIT15 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT15\r
+ #define TC0Hhi_BIT_8 _TC0H.Overlap_STR.TC0HhiSTR.MergedBits.grpBIT_8\r
+ #define TC0Hhi_BIT TC0Hhi_BIT_8\r
+ \r
+ /*** TC0Hlo - Timer Input Capture Holding Registers 0 Low; 0x00000079 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* Timer Input Capture Holding Bit 0 */\r
+ byte BIT1 :1; /* Timer Input Capture Holding Bit 1 */\r
+ byte BIT2 :1; /* Timer Input Capture Holding Bit 2 */\r
+ byte BIT3 :1; /* Timer Input Capture Holding Bit 3 */\r
+ byte BIT4 :1; /* Timer Input Capture Holding Bit 4 */\r
+ byte BIT5 :1; /* Timer Input Capture Holding Bit 5 */\r
+ byte BIT6 :1; /* Timer Input Capture Holding Bit 6 */\r
+ byte BIT7 :1; /* Timer Input Capture Holding Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } TC0HloSTR;\r
+ #define TC0Hlo _TC0H.Overlap_STR.TC0HloSTR.Byte\r
+ #define TC0Hlo_BIT0 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT0\r
+ #define TC0Hlo_BIT1 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT1\r
+ #define TC0Hlo_BIT2 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT2\r
+ #define TC0Hlo_BIT3 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT3\r
+ #define TC0Hlo_BIT4 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT4\r
+ #define TC0Hlo_BIT5 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT5\r
+ #define TC0Hlo_BIT6 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT6\r
+ #define TC0Hlo_BIT7 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT7\r
+ #define TC0Hlo_BIT _TC0H.Overlap_STR.TC0HloSTR.MergedBits.grpBIT\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word BIT0 :1; /* Timer Input Capture Holding Bit 0 */\r
+ word BIT1 :1; /* Timer Input Capture Holding Bit 1 */\r
+ word BIT2 :1; /* Timer Input Capture Holding Bit 2 */\r
+ word BIT3 :1; /* Timer Input Capture Holding Bit 3 */\r
+ word BIT4 :1; /* Timer Input Capture Holding Bit 4 */\r
+ word BIT5 :1; /* Timer Input Capture Holding Bit 5 */\r
+ word BIT6 :1; /* Timer Input Capture Holding Bit 6 */\r
+ word BIT7 :1; /* Timer Input Capture Holding Bit 7 */\r
+ word BIT8 :1; /* Timer Input Capture Holding Bit 8 */\r
+ word BIT9 :1; /* Timer Input Capture Holding Bit 9 */\r
+ word BIT10 :1; /* Timer Input Capture Holding Bit 10 */\r
+ word BIT11 :1; /* Timer Input Capture Holding Bit 11 */\r
+ word BIT12 :1; /* Timer Input Capture Holding Bit 12 */\r
+ word BIT13 :1; /* Timer Input Capture Holding Bit 13 */\r
+ word BIT14 :1; /* Timer Input Capture Holding Bit 14 */\r
+ word BIT15 :1; /* Timer Input Capture Holding Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ word grpBIT :16;\r
+ } MergedBits;\r
+} TC0HSTR;\r
+extern volatile TC0HSTR _TC0H @(REG_BASE + 0x00000078);\r
+#define TC0H _TC0H.Word\r
+#define TC0H_BIT0 _TC0H.Bits.BIT0\r
+#define TC0H_BIT1 _TC0H.Bits.BIT1\r
+#define TC0H_BIT2 _TC0H.Bits.BIT2\r
+#define TC0H_BIT3 _TC0H.Bits.BIT3\r
+#define TC0H_BIT4 _TC0H.Bits.BIT4\r
+#define TC0H_BIT5 _TC0H.Bits.BIT5\r
+#define TC0H_BIT6 _TC0H.Bits.BIT6\r
+#define TC0H_BIT7 _TC0H.Bits.BIT7\r
+#define TC0H_BIT8 _TC0H.Bits.BIT8\r
+#define TC0H_BIT9 _TC0H.Bits.BIT9\r
+#define TC0H_BIT10 _TC0H.Bits.BIT10\r
+#define TC0H_BIT11 _TC0H.Bits.BIT11\r
+#define TC0H_BIT12 _TC0H.Bits.BIT12\r
+#define TC0H_BIT13 _TC0H.Bits.BIT13\r
+#define TC0H_BIT14 _TC0H.Bits.BIT14\r
+#define TC0H_BIT15 _TC0H.Bits.BIT15\r
+#define TC0H_BIT _TC0H.MergedBits.grpBIT\r
+\r
+\r
+/*** TC1H - Timer Input Capture Holding Registers 1; 0x0000007A ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** TC1Hhi - Timer Input Capture Holding Registers 1 High; 0x0000007A ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT8 :1; /* Timer Input Capture Holding Bit 8 */\r
+ byte BIT9 :1; /* Timer Input Capture Holding Bit 9 */\r
+ byte BIT10 :1; /* Timer Input Capture Holding Bit 10 */\r
+ byte BIT11 :1; /* Timer Input Capture Holding Bit 11 */\r
+ byte BIT12 :1; /* Timer Input Capture Holding Bit 12 */\r
+ byte BIT13 :1; /* Timer Input Capture Holding Bit 13 */\r
+ byte BIT14 :1; /* Timer Input Capture Holding Bit 14 */\r
+ byte BIT15 :1; /* Timer Input Capture Holding Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT_8 :8;\r
+ } MergedBits;\r
+ } TC1HhiSTR;\r
+ #define TC1Hhi _TC1H.Overlap_STR.TC1HhiSTR.Byte\r
+ #define TC1Hhi_BIT8 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT8\r
+ #define TC1Hhi_BIT9 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT9\r
+ #define TC1Hhi_BIT10 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT10\r
+ #define TC1Hhi_BIT11 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT11\r
+ #define TC1Hhi_BIT12 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT12\r
+ #define TC1Hhi_BIT13 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT13\r
+ #define TC1Hhi_BIT14 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT14\r
+ #define TC1Hhi_BIT15 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT15\r
+ #define TC1Hhi_BIT_8 _TC1H.Overlap_STR.TC1HhiSTR.MergedBits.grpBIT_8\r
+ #define TC1Hhi_BIT TC1Hhi_BIT_8\r
+ \r
+ /*** TC1Hlo - Timer Input Capture Holding Registers 1 Low; 0x0000007B ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* Timer Input Capture Holding Bit 0 */\r
+ byte BIT1 :1; /* Timer Input Capture Holding Bit 1 */\r
+ byte BIT2 :1; /* Timer Input Capture Holding Bit 2 */\r
+ byte BIT3 :1; /* Timer Input Capture Holding Bit 3 */\r
+ byte BIT4 :1; /* Timer Input Capture Holding Bit 4 */\r
+ byte BIT5 :1; /* Timer Input Capture Holding Bit 5 */\r
+ byte BIT6 :1; /* Timer Input Capture Holding Bit 6 */\r
+ byte BIT7 :1; /* Timer Input Capture Holding Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } TC1HloSTR;\r
+ #define TC1Hlo _TC1H.Overlap_STR.TC1HloSTR.Byte\r
+ #define TC1Hlo_BIT0 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT0\r
+ #define TC1Hlo_BIT1 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT1\r
+ #define TC1Hlo_BIT2 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT2\r
+ #define TC1Hlo_BIT3 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT3\r
+ #define TC1Hlo_BIT4 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT4\r
+ #define TC1Hlo_BIT5 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT5\r
+ #define TC1Hlo_BIT6 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT6\r
+ #define TC1Hlo_BIT7 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT7\r
+ #define TC1Hlo_BIT _TC1H.Overlap_STR.TC1HloSTR.MergedBits.grpBIT\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word BIT0 :1; /* Timer Input Capture Holding Bit 0 */\r
+ word BIT1 :1; /* Timer Input Capture Holding Bit 1 */\r
+ word BIT2 :1; /* Timer Input Capture Holding Bit 2 */\r
+ word BIT3 :1; /* Timer Input Capture Holding Bit 3 */\r
+ word BIT4 :1; /* Timer Input Capture Holding Bit 4 */\r
+ word BIT5 :1; /* Timer Input Capture Holding Bit 5 */\r
+ word BIT6 :1; /* Timer Input Capture Holding Bit 6 */\r
+ word BIT7 :1; /* Timer Input Capture Holding Bit 7 */\r
+ word BIT8 :1; /* Timer Input Capture Holding Bit 8 */\r
+ word BIT9 :1; /* Timer Input Capture Holding Bit 9 */\r
+ word BIT10 :1; /* Timer Input Capture Holding Bit 10 */\r
+ word BIT11 :1; /* Timer Input Capture Holding Bit 11 */\r
+ word BIT12 :1; /* Timer Input Capture Holding Bit 12 */\r
+ word BIT13 :1; /* Timer Input Capture Holding Bit 13 */\r
+ word BIT14 :1; /* Timer Input Capture Holding Bit 14 */\r
+ word BIT15 :1; /* Timer Input Capture Holding Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ word grpBIT :16;\r
+ } MergedBits;\r
+} TC1HSTR;\r
+extern volatile TC1HSTR _TC1H @(REG_BASE + 0x0000007A);\r
+#define TC1H _TC1H.Word\r
+#define TC1H_BIT0 _TC1H.Bits.BIT0\r
+#define TC1H_BIT1 _TC1H.Bits.BIT1\r
+#define TC1H_BIT2 _TC1H.Bits.BIT2\r
+#define TC1H_BIT3 _TC1H.Bits.BIT3\r
+#define TC1H_BIT4 _TC1H.Bits.BIT4\r
+#define TC1H_BIT5 _TC1H.Bits.BIT5\r
+#define TC1H_BIT6 _TC1H.Bits.BIT6\r
+#define TC1H_BIT7 _TC1H.Bits.BIT7\r
+#define TC1H_BIT8 _TC1H.Bits.BIT8\r
+#define TC1H_BIT9 _TC1H.Bits.BIT9\r
+#define TC1H_BIT10 _TC1H.Bits.BIT10\r
+#define TC1H_BIT11 _TC1H.Bits.BIT11\r
+#define TC1H_BIT12 _TC1H.Bits.BIT12\r
+#define TC1H_BIT13 _TC1H.Bits.BIT13\r
+#define TC1H_BIT14 _TC1H.Bits.BIT14\r
+#define TC1H_BIT15 _TC1H.Bits.BIT15\r
+#define TC1H_BIT _TC1H.MergedBits.grpBIT\r
+\r
+\r
+/*** TC2H - Timer Input Capture Holding Registers 2; 0x0000007C ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** TC2Hhi - Timer Input Capture Holding Registers 2 High; 0x0000007C ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT8 :1; /* Timer Input Capture Holding Bit 8 */\r
+ byte BIT9 :1; /* Timer Input Capture Holding Bit 9 */\r
+ byte BIT10 :1; /* Timer Input Capture Holding Bit 10 */\r
+ byte BIT11 :1; /* Timer Input Capture Holding Bit 11 */\r
+ byte BIT12 :1; /* Timer Input Capture Holding Bit 12 */\r
+ byte BIT13 :1; /* Timer Input Capture Holding Bit 13 */\r
+ byte BIT14 :1; /* Timer Input Capture Holding Bit 14 */\r
+ byte BIT15 :1; /* Timer Input Capture Holding Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT_8 :8;\r
+ } MergedBits;\r
+ } TC2HhiSTR;\r
+ #define TC2Hhi _TC2H.Overlap_STR.TC2HhiSTR.Byte\r
+ #define TC2Hhi_BIT8 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT8\r
+ #define TC2Hhi_BIT9 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT9\r
+ #define TC2Hhi_BIT10 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT10\r
+ #define TC2Hhi_BIT11 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT11\r
+ #define TC2Hhi_BIT12 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT12\r
+ #define TC2Hhi_BIT13 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT13\r
+ #define TC2Hhi_BIT14 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT14\r
+ #define TC2Hhi_BIT15 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT15\r
+ #define TC2Hhi_BIT_8 _TC2H.Overlap_STR.TC2HhiSTR.MergedBits.grpBIT_8\r
+ #define TC2Hhi_BIT TC2Hhi_BIT_8\r
+ \r
+ /*** TC2Hlo - Timer Input Capture Holding Registers 2 Low; 0x0000007D ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* Timer Input Capture Holding Bit 0 */\r
+ byte BIT1 :1; /* Timer Input Capture Holding Bit 1 */\r
+ byte BIT2 :1; /* Timer Input Capture Holding Bit 2 */\r
+ byte BIT3 :1; /* Timer Input Capture Holding Bit 3 */\r
+ byte BIT4 :1; /* Timer Input Capture Holding Bit 4 */\r
+ byte BIT5 :1; /* Timer Input Capture Holding Bit 5 */\r
+ byte BIT6 :1; /* Timer Input Capture Holding Bit 6 */\r
+ byte BIT7 :1; /* Timer Input Capture Holding Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } TC2HloSTR;\r
+ #define TC2Hlo _TC2H.Overlap_STR.TC2HloSTR.Byte\r
+ #define TC2Hlo_BIT0 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT0\r
+ #define TC2Hlo_BIT1 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT1\r
+ #define TC2Hlo_BIT2 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT2\r
+ #define TC2Hlo_BIT3 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT3\r
+ #define TC2Hlo_BIT4 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT4\r
+ #define TC2Hlo_BIT5 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT5\r
+ #define TC2Hlo_BIT6 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT6\r
+ #define TC2Hlo_BIT7 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT7\r
+ #define TC2Hlo_BIT _TC2H.Overlap_STR.TC2HloSTR.MergedBits.grpBIT\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word BIT0 :1; /* Timer Input Capture Holding Bit 0 */\r
+ word BIT1 :1; /* Timer Input Capture Holding Bit 1 */\r
+ word BIT2 :1; /* Timer Input Capture Holding Bit 2 */\r
+ word BIT3 :1; /* Timer Input Capture Holding Bit 3 */\r
+ word BIT4 :1; /* Timer Input Capture Holding Bit 4 */\r
+ word BIT5 :1; /* Timer Input Capture Holding Bit 5 */\r
+ word BIT6 :1; /* Timer Input Capture Holding Bit 6 */\r
+ word BIT7 :1; /* Timer Input Capture Holding Bit 7 */\r
+ word BIT8 :1; /* Timer Input Capture Holding Bit 8 */\r
+ word BIT9 :1; /* Timer Input Capture Holding Bit 9 */\r
+ word BIT10 :1; /* Timer Input Capture Holding Bit 10 */\r
+ word BIT11 :1; /* Timer Input Capture Holding Bit 11 */\r
+ word BIT12 :1; /* Timer Input Capture Holding Bit 12 */\r
+ word BIT13 :1; /* Timer Input Capture Holding Bit 13 */\r
+ word BIT14 :1; /* Timer Input Capture Holding Bit 14 */\r
+ word BIT15 :1; /* Timer Input Capture Holding Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ word grpBIT :16;\r
+ } MergedBits;\r
+} TC2HSTR;\r
+extern volatile TC2HSTR _TC2H @(REG_BASE + 0x0000007C);\r
+#define TC2H _TC2H.Word\r
+#define TC2H_BIT0 _TC2H.Bits.BIT0\r
+#define TC2H_BIT1 _TC2H.Bits.BIT1\r
+#define TC2H_BIT2 _TC2H.Bits.BIT2\r
+#define TC2H_BIT3 _TC2H.Bits.BIT3\r
+#define TC2H_BIT4 _TC2H.Bits.BIT4\r
+#define TC2H_BIT5 _TC2H.Bits.BIT5\r
+#define TC2H_BIT6 _TC2H.Bits.BIT6\r
+#define TC2H_BIT7 _TC2H.Bits.BIT7\r
+#define TC2H_BIT8 _TC2H.Bits.BIT8\r
+#define TC2H_BIT9 _TC2H.Bits.BIT9\r
+#define TC2H_BIT10 _TC2H.Bits.BIT10\r
+#define TC2H_BIT11 _TC2H.Bits.BIT11\r
+#define TC2H_BIT12 _TC2H.Bits.BIT12\r
+#define TC2H_BIT13 _TC2H.Bits.BIT13\r
+#define TC2H_BIT14 _TC2H.Bits.BIT14\r
+#define TC2H_BIT15 _TC2H.Bits.BIT15\r
+#define TC2H_BIT _TC2H.MergedBits.grpBIT\r
+\r
+\r
+/*** TC3H - Timer Input Capture Holding Registers 3; 0x0000007E ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** TC3Hhi - Timer Input Capture Holding Registers 3 High; 0x0000007E ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT8 :1; /* Timer Input Capture Holding Bit 8 */\r
+ byte BIT9 :1; /* Timer Input Capture Holding Bit 9 */\r
+ byte BIT10 :1; /* Timer Input Capture Holding Bit 10 */\r
+ byte BIT11 :1; /* Timer Input Capture Holding Bit 11 */\r
+ byte BIT12 :1; /* Timer Input Capture Holding Bit 12 */\r
+ byte BIT13 :1; /* Timer Input Capture Holding Bit 13 */\r
+ byte BIT14 :1; /* Timer Input Capture Holding Bit 14 */\r
+ byte BIT15 :1; /* Timer Input Capture Holding Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT_8 :8;\r
+ } MergedBits;\r
+ } TC3HhiSTR;\r
+ #define TC3Hhi _TC3H.Overlap_STR.TC3HhiSTR.Byte\r
+ #define TC3Hhi_BIT8 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT8\r
+ #define TC3Hhi_BIT9 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT9\r
+ #define TC3Hhi_BIT10 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT10\r
+ #define TC3Hhi_BIT11 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT11\r
+ #define TC3Hhi_BIT12 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT12\r
+ #define TC3Hhi_BIT13 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT13\r
+ #define TC3Hhi_BIT14 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT14\r
+ #define TC3Hhi_BIT15 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT15\r
+ #define TC3Hhi_BIT_8 _TC3H.Overlap_STR.TC3HhiSTR.MergedBits.grpBIT_8\r
+ #define TC3Hhi_BIT TC3Hhi_BIT_8\r
+ \r
+ /*** TC3Hlo - Timer Input Capture Holding Registers 3 Low; 0x0000007F ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* Timer Input Capture Holding Bit 0 */\r
+ byte BIT1 :1; /* Timer Input Capture Holding Bit 1 */\r
+ byte BIT2 :1; /* Timer Input Capture Holding Bit 2 */\r
+ byte BIT3 :1; /* Timer Input Capture Holding Bit 3 */\r
+ byte BIT4 :1; /* Timer Input Capture Holding Bit 4 */\r
+ byte BIT5 :1; /* Timer Input Capture Holding Bit 5 */\r
+ byte BIT6 :1; /* Timer Input Capture Holding Bit 6 */\r
+ byte BIT7 :1; /* Timer Input Capture Holding Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } TC3HloSTR;\r
+ #define TC3Hlo _TC3H.Overlap_STR.TC3HloSTR.Byte\r
+ #define TC3Hlo_BIT0 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT0\r
+ #define TC3Hlo_BIT1 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT1\r
+ #define TC3Hlo_BIT2 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT2\r
+ #define TC3Hlo_BIT3 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT3\r
+ #define TC3Hlo_BIT4 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT4\r
+ #define TC3Hlo_BIT5 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT5\r
+ #define TC3Hlo_BIT6 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT6\r
+ #define TC3Hlo_BIT7 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT7\r
+ #define TC3Hlo_BIT _TC3H.Overlap_STR.TC3HloSTR.MergedBits.grpBIT\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word BIT0 :1; /* Timer Input Capture Holding Bit 0 */\r
+ word BIT1 :1; /* Timer Input Capture Holding Bit 1 */\r
+ word BIT2 :1; /* Timer Input Capture Holding Bit 2 */\r
+ word BIT3 :1; /* Timer Input Capture Holding Bit 3 */\r
+ word BIT4 :1; /* Timer Input Capture Holding Bit 4 */\r
+ word BIT5 :1; /* Timer Input Capture Holding Bit 5 */\r
+ word BIT6 :1; /* Timer Input Capture Holding Bit 6 */\r
+ word BIT7 :1; /* Timer Input Capture Holding Bit 7 */\r
+ word BIT8 :1; /* Timer Input Capture Holding Bit 8 */\r
+ word BIT9 :1; /* Timer Input Capture Holding Bit 9 */\r
+ word BIT10 :1; /* Timer Input Capture Holding Bit 10 */\r
+ word BIT11 :1; /* Timer Input Capture Holding Bit 11 */\r
+ word BIT12 :1; /* Timer Input Capture Holding Bit 12 */\r
+ word BIT13 :1; /* Timer Input Capture Holding Bit 13 */\r
+ word BIT14 :1; /* Timer Input Capture Holding Bit 14 */\r
+ word BIT15 :1; /* Timer Input Capture Holding Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ word grpBIT :16;\r
+ } MergedBits;\r
+} TC3HSTR;\r
+extern volatile TC3HSTR _TC3H @(REG_BASE + 0x0000007E);\r
+#define TC3H _TC3H.Word\r
+#define TC3H_BIT0 _TC3H.Bits.BIT0\r
+#define TC3H_BIT1 _TC3H.Bits.BIT1\r
+#define TC3H_BIT2 _TC3H.Bits.BIT2\r
+#define TC3H_BIT3 _TC3H.Bits.BIT3\r
+#define TC3H_BIT4 _TC3H.Bits.BIT4\r
+#define TC3H_BIT5 _TC3H.Bits.BIT5\r
+#define TC3H_BIT6 _TC3H.Bits.BIT6\r
+#define TC3H_BIT7 _TC3H.Bits.BIT7\r
+#define TC3H_BIT8 _TC3H.Bits.BIT8\r
+#define TC3H_BIT9 _TC3H.Bits.BIT9\r
+#define TC3H_BIT10 _TC3H.Bits.BIT10\r
+#define TC3H_BIT11 _TC3H.Bits.BIT11\r
+#define TC3H_BIT12 _TC3H.Bits.BIT12\r
+#define TC3H_BIT13 _TC3H.Bits.BIT13\r
+#define TC3H_BIT14 _TC3H.Bits.BIT14\r
+#define TC3H_BIT15 _TC3H.Bits.BIT15\r
+#define TC3H_BIT _TC3H.MergedBits.grpBIT\r
+\r
+\r
+/*** ATD0CTL23 - ATD 0 Control Register 23; 0x00000082 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** ATD0CTL2 - ATD 0 Control Register 2; 0x00000082 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte ASCIF :1; /* ATD 0 Sequence Complete Interrupt Flag */\r
+ byte ASCIE :1; /* ATD 0 Sequence Complete Interrupt Enable */\r
+ byte ETRIGE :1; /* External Trigger Mode enable */\r
+ byte ETRIGP :1; /* External Trigger Polarity */\r
+ byte ETRIGLE :1; /* External Trigger Level/Edge control */\r
+ byte AWAI :1; /* ATD 0 Wait Mode */\r
+ byte AFFC :1; /* ATD 0 Fast Conversion Complete Flag Clear */\r
+ byte ADPU :1; /* ATD 0 Disable / Power Down */\r
+ } Bits;\r
+ } ATD0CTL2STR;\r
+ #define ATD0CTL2 _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Byte\r
+ #define ATD0CTL2_ASCIF _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ASCIF\r
+ #define ATD0CTL2_ASCIE _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ASCIE\r
+ #define ATD0CTL2_ETRIGE _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ETRIGE\r
+ #define ATD0CTL2_ETRIGP _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ETRIGP\r
+ #define ATD0CTL2_ETRIGLE _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ETRIGLE\r
+ #define ATD0CTL2_AWAI _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.AWAI\r
+ #define ATD0CTL2_AFFC _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.AFFC\r
+ #define ATD0CTL2_ADPU _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ADPU\r
+ \r
+ /*** ATD0CTL3 - ATD 0 Control Register 3; 0x00000083 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte FRZ0 :1; /* Background Debug Freeze Enable */\r
+ byte FRZ1 :1; /* Background Debug Freeze Enable */\r
+ byte FIFO :1; /* Result Register FIFO Mode */\r
+ byte S1C :1; /* Conversion Sequence Length 1 */\r
+ byte S2C :1; /* Conversion Sequence Length 2 */\r
+ byte S4C :1; /* Conversion Sequence Length 4 */\r
+ byte S8C :1; /* Conversion Sequence Length 8 */\r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpFRZ :2;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+ } ATD0CTL3STR;\r
+ #define ATD0CTL3 _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Byte\r
+ #define ATD0CTL3_FRZ0 _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.FRZ0\r
+ #define ATD0CTL3_FRZ1 _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.FRZ1\r
+ #define ATD0CTL3_FIFO _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.FIFO\r
+ #define ATD0CTL3_S1C _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.S1C\r
+ #define ATD0CTL3_S2C _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.S2C\r
+ #define ATD0CTL3_S4C _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.S4C\r
+ #define ATD0CTL3_S8C _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.S8C\r
+ #define ATD0CTL3_FRZ _ATD0CTL23.Overlap_STR.ATD0CTL3STR.MergedBits.grpFRZ\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word FRZ0 :1; /* Background Debug Freeze Enable */\r
+ word FRZ1 :1; /* Background Debug Freeze Enable */\r
+ word FIFO :1; /* Result Register FIFO Mode */\r
+ word S1C :1; /* Conversion Sequence Length 1 */\r
+ word S2C :1; /* Conversion Sequence Length 2 */\r
+ word S4C :1; /* Conversion Sequence Length 4 */\r
+ word S8C :1; /* Conversion Sequence Length 8 */\r
+ word :1; \r
+ word ASCIF :1; /* ATD 0 Sequence Complete Interrupt Flag */\r
+ word ASCIE :1; /* ATD 0 Sequence Complete Interrupt Enable */\r
+ word ETRIGE :1; /* External Trigger Mode enable */\r
+ word ETRIGP :1; /* External Trigger Polarity */\r
+ word ETRIGLE :1; /* External Trigger Level/Edge control */\r
+ word AWAI :1; /* ATD 0 Wait Mode */\r
+ word AFFC :1; /* ATD 0 Fast Conversion Complete Flag Clear */\r
+ word ADPU :1; /* ATD 0 Disable / Power Down */\r
+ } Bits;\r
+ struct {\r
+ word grpFRZ :2;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ } MergedBits;\r
+} ATD0CTL23STR;\r
+extern volatile ATD0CTL23STR _ATD0CTL23 @(REG_BASE + 0x00000082);\r
+#define ATD0CTL23 _ATD0CTL23.Word\r
+#define ATD0CTL23_FRZ0 _ATD0CTL23.Bits.FRZ0\r
+#define ATD0CTL23_FRZ1 _ATD0CTL23.Bits.FRZ1\r
+#define ATD0CTL23_FIFO _ATD0CTL23.Bits.FIFO\r
+#define ATD0CTL23_S1C _ATD0CTL23.Bits.S1C\r
+#define ATD0CTL23_S2C _ATD0CTL23.Bits.S2C\r
+#define ATD0CTL23_S4C _ATD0CTL23.Bits.S4C\r
+#define ATD0CTL23_S8C _ATD0CTL23.Bits.S8C\r
+#define ATD0CTL23_ASCIF _ATD0CTL23.Bits.ASCIF\r
+#define ATD0CTL23_ASCIE _ATD0CTL23.Bits.ASCIE\r
+#define ATD0CTL23_ETRIGE _ATD0CTL23.Bits.ETRIGE\r
+#define ATD0CTL23_ETRIGP _ATD0CTL23.Bits.ETRIGP\r
+#define ATD0CTL23_ETRIGLE _ATD0CTL23.Bits.ETRIGLE\r
+#define ATD0CTL23_AWAI _ATD0CTL23.Bits.AWAI\r
+#define ATD0CTL23_AFFC _ATD0CTL23.Bits.AFFC\r
+#define ATD0CTL23_ADPU _ATD0CTL23.Bits.ADPU\r
+#define ATD0CTL23_FRZ _ATD0CTL23.MergedBits.grpFRZ\r
+\r
+\r
+/*** ATD0CTL45 - ATD 0 Control Register 45; 0x00000084 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** ATD0CTL4 - ATD 0 Control Register 4; 0x00000084 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte PRS0 :1; /* ATD 0 Clock Prescaler 0 */\r
+ byte PRS1 :1; /* ATD 0 Clock Prescaler 1 */\r
+ byte PRS2 :1; /* ATD 0 Clock Prescaler 2 */\r
+ byte PRS3 :1; /* ATD 0 Clock Prescaler 3 */\r
+ byte PRS4 :1; /* ATD 0 Clock Prescaler 4 */\r
+ byte SMP0 :1; /* Sample Time Select 0 */\r
+ byte SMP1 :1; /* Sample Time Select 1 */\r
+ byte SRES8 :1; /* ATD 0 Resolution Select */\r
+ } Bits;\r
+ struct {\r
+ byte grpPRS :5;\r
+ byte grpSMP :2;\r
+ byte grpSRES_8 :1;\r
+ } MergedBits;\r
+ } ATD0CTL4STR;\r
+ #define ATD0CTL4 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Byte\r
+ #define ATD0CTL4_PRS0 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.PRS0\r
+ #define ATD0CTL4_PRS1 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.PRS1\r
+ #define ATD0CTL4_PRS2 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.PRS2\r
+ #define ATD0CTL4_PRS3 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.PRS3\r
+ #define ATD0CTL4_PRS4 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.PRS4\r
+ #define ATD0CTL4_SMP0 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.SMP0\r
+ #define ATD0CTL4_SMP1 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.SMP1\r
+ #define ATD0CTL4_SRES8 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.SRES8\r
+ #define ATD0CTL4_PRS _ATD0CTL45.Overlap_STR.ATD0CTL4STR.MergedBits.grpPRS\r
+ #define ATD0CTL4_SMP _ATD0CTL45.Overlap_STR.ATD0CTL4STR.MergedBits.grpSMP\r
+ \r
+ /*** ATD0CTL5 - ATD 0 Control Register 5; 0x00000085 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte CA :1; /* Analog Input Channel Select Code A */\r
+ byte CB :1; /* Analog Input Channel Select Code B */\r
+ byte CC :1; /* Analog Input Channel Select Code C */\r
+ byte :1; \r
+ byte MULT :1; /* Multi-Channel Sample Mode */\r
+ byte SCAN :1; /* Continuous Conversion Sequence Mode */\r
+ byte DSGN :1; /* Signed/Unsigned Result Data Mode */\r
+ byte DJM :1; /* Result Register Data Justification Mode */\r
+ } Bits;\r
+ } ATD0CTL5STR;\r
+ #define ATD0CTL5 _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Byte\r
+ #define ATD0CTL5_CA _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.CA\r
+ #define ATD0CTL5_CB _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.CB\r
+ #define ATD0CTL5_CC _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.CC\r
+ #define ATD0CTL5_MULT _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.MULT\r
+ #define ATD0CTL5_SCAN _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.SCAN\r
+ #define ATD0CTL5_DSGN _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.DSGN\r
+ #define ATD0CTL5_DJM _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.DJM\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word CA :1; /* Analog Input Channel Select Code A */\r
+ word CB :1; /* Analog Input Channel Select Code B */\r
+ word CC :1; /* Analog Input Channel Select Code C */\r
+ word :1; \r
+ word MULT :1; /* Multi-Channel Sample Mode */\r
+ word SCAN :1; /* Continuous Conversion Sequence Mode */\r
+ word DSGN :1; /* Signed/Unsigned Result Data Mode */\r
+ word DJM :1; /* Result Register Data Justification Mode */\r
+ word PRS0 :1; /* ATD 0 Clock Prescaler 0 */\r
+ word PRS1 :1; /* ATD 0 Clock Prescaler 1 */\r
+ word PRS2 :1; /* ATD 0 Clock Prescaler 2 */\r
+ word PRS3 :1; /* ATD 0 Clock Prescaler 3 */\r
+ word PRS4 :1; /* ATD 0 Clock Prescaler 4 */\r
+ word SMP0 :1; /* Sample Time Select 0 */\r
+ word SMP1 :1; /* Sample Time Select 1 */\r
+ word SRES8 :1; /* ATD 0 Resolution Select */\r
+ } Bits;\r
+ struct {\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word grpPRS :5;\r
+ word grpSMP :2;\r
+ word grpSRES_8 :1;\r
+ } MergedBits;\r
+} ATD0CTL45STR;\r
+extern volatile ATD0CTL45STR _ATD0CTL45 @(REG_BASE + 0x00000084);\r
+#define ATD0CTL45 _ATD0CTL45.Word\r
+#define ATD0CTL45_CA _ATD0CTL45.Bits.CA\r
+#define ATD0CTL45_CB _ATD0CTL45.Bits.CB\r
+#define ATD0CTL45_CC _ATD0CTL45.Bits.CC\r
+#define ATD0CTL45_MULT _ATD0CTL45.Bits.MULT\r
+#define ATD0CTL45_SCAN _ATD0CTL45.Bits.SCAN\r
+#define ATD0CTL45_DSGN _ATD0CTL45.Bits.DSGN\r
+#define ATD0CTL45_DJM _ATD0CTL45.Bits.DJM\r
+#define ATD0CTL45_PRS0 _ATD0CTL45.Bits.PRS0\r
+#define ATD0CTL45_PRS1 _ATD0CTL45.Bits.PRS1\r
+#define ATD0CTL45_PRS2 _ATD0CTL45.Bits.PRS2\r
+#define ATD0CTL45_PRS3 _ATD0CTL45.Bits.PRS3\r
+#define ATD0CTL45_PRS4 _ATD0CTL45.Bits.PRS4\r
+#define ATD0CTL45_SMP0 _ATD0CTL45.Bits.SMP0\r
+#define ATD0CTL45_SMP1 _ATD0CTL45.Bits.SMP1\r
+#define ATD0CTL45_SRES8 _ATD0CTL45.Bits.SRES8\r
+#define ATD0CTL45_PRS _ATD0CTL45.MergedBits.grpPRS\r
+#define ATD0CTL45_SMP _ATD0CTL45.MergedBits.grpSMP\r
+\r
+\r
+/*** ATD0DR0 - ATD 0 Conversion Result Register 0; 0x00000090 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** ATD0DR0H - ATD 0 Conversion Result Register 0 High; 0x00000090 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT8 :1; /* Bit 8 */\r
+ byte BIT9 :1; /* Bit 9 */\r
+ byte BIT10 :1; /* Bit 10 */\r
+ byte BIT11 :1; /* Bit 11 */\r
+ byte BIT12 :1; /* Bit 12 */\r
+ byte BIT13 :1; /* Bit 13 */\r
+ byte BIT14 :1; /* Bit 14 */\r
+ byte BIT15 :1; /* Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT_8 :8;\r
+ } MergedBits;\r
+ } ATD0DR0HSTR;\r
+ #define ATD0DR0H _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Byte\r
+ #define ATD0DR0H_BIT8 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT8\r
+ #define ATD0DR0H_BIT9 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT9\r
+ #define ATD0DR0H_BIT10 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT10\r
+ #define ATD0DR0H_BIT11 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT11\r
+ #define ATD0DR0H_BIT12 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT12\r
+ #define ATD0DR0H_BIT13 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT13\r
+ #define ATD0DR0H_BIT14 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT14\r
+ #define ATD0DR0H_BIT15 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT15\r
+ #define ATD0DR0H_BIT_8 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.MergedBits.grpBIT_8\r
+ #define ATD0DR0H_BIT ATD0DR0H_BIT_8\r
+ \r
+ /*** ATD0DR0L - ATD 0 Conversion Result Register 0 Low; 0x00000091 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte BIT6 :1; /* Bit 6 */\r
+ byte BIT7 :1; /* Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpBIT_6 :2;\r
+ } MergedBits;\r
+ } ATD0DR0LSTR;\r
+ #define ATD0DR0L _ATD0DR0.Overlap_STR.ATD0DR0LSTR.Byte\r
+ #define ATD0DR0L_BIT6 _ATD0DR0.Overlap_STR.ATD0DR0LSTR.Bits.BIT6\r
+ #define ATD0DR0L_BIT7 _ATD0DR0.Overlap_STR.ATD0DR0LSTR.Bits.BIT7\r
+ #define ATD0DR0L_BIT_6 _ATD0DR0.Overlap_STR.ATD0DR0LSTR.MergedBits.grpBIT_6\r
+ #define ATD0DR0L_BIT ATD0DR0L_BIT_6\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word BIT6 :1; /* Bit 6 */\r
+ word BIT7 :1; /* Bit 7 */\r
+ word BIT8 :1; /* Bit 8 */\r
+ word BIT9 :1; /* Bit 9 */\r
+ word BIT10 :1; /* Bit 10 */\r
+ word BIT11 :1; /* Bit 11 */\r
+ word BIT12 :1; /* Bit 12 */\r
+ word BIT13 :1; /* Bit 13 */\r
+ word BIT14 :1; /* Bit 14 */\r
+ word BIT15 :1; /* Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word grpBIT_6 :10;\r
+ } MergedBits;\r
+} ATD0DR0STR;\r
+extern volatile ATD0DR0STR _ATD0DR0 @(REG_BASE + 0x00000090);\r
+#define ATD0DR0 _ATD0DR0.Word\r
+#define ATD0DR0_BIT6 _ATD0DR0.Bits.BIT6\r
+#define ATD0DR0_BIT7 _ATD0DR0.Bits.BIT7\r
+#define ATD0DR0_BIT8 _ATD0DR0.Bits.BIT8\r
+#define ATD0DR0_BIT9 _ATD0DR0.Bits.BIT9\r
+#define ATD0DR0_BIT10 _ATD0DR0.Bits.BIT10\r
+#define ATD0DR0_BIT11 _ATD0DR0.Bits.BIT11\r
+#define ATD0DR0_BIT12 _ATD0DR0.Bits.BIT12\r
+#define ATD0DR0_BIT13 _ATD0DR0.Bits.BIT13\r
+#define ATD0DR0_BIT14 _ATD0DR0.Bits.BIT14\r
+#define ATD0DR0_BIT15 _ATD0DR0.Bits.BIT15\r
+#define ATD0DR0_BIT_6 _ATD0DR0.MergedBits.grpBIT_6\r
+#define ATD0DR0_BIT ATD0DR0_BIT_6\r
+\r
+\r
+/*** ATD0DR1 - ATD 0 Conversion Result Register 1; 0x00000092 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** ATD0DR1H - ATD 0 Conversion Result Register 1 High; 0x00000092 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT8 :1; /* Bit 8 */\r
+ byte BIT9 :1; /* Bit 9 */\r
+ byte BIT10 :1; /* Bit 10 */\r
+ byte BIT11 :1; /* Bit 11 */\r
+ byte BIT12 :1; /* Bit 12 */\r
+ byte BIT13 :1; /* Bit 13 */\r
+ byte BIT14 :1; /* Bit 14 */\r
+ byte BIT15 :1; /* Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT_8 :8;\r
+ } MergedBits;\r
+ } ATD0DR1HSTR;\r
+ #define ATD0DR1H _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Byte\r
+ #define ATD0DR1H_BIT8 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT8\r
+ #define ATD0DR1H_BIT9 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT9\r
+ #define ATD0DR1H_BIT10 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT10\r
+ #define ATD0DR1H_BIT11 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT11\r
+ #define ATD0DR1H_BIT12 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT12\r
+ #define ATD0DR1H_BIT13 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT13\r
+ #define ATD0DR1H_BIT14 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT14\r
+ #define ATD0DR1H_BIT15 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT15\r
+ #define ATD0DR1H_BIT_8 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.MergedBits.grpBIT_8\r
+ #define ATD0DR1H_BIT ATD0DR1H_BIT_8\r
+ \r
+ /*** ATD0DR1L - ATD 0 Conversion Result Register 1 Low; 0x00000093 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte BIT6 :1; /* Bit 6 */\r
+ byte BIT7 :1; /* Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpBIT_6 :2;\r
+ } MergedBits;\r
+ } ATD0DR1LSTR;\r
+ #define ATD0DR1L _ATD0DR1.Overlap_STR.ATD0DR1LSTR.Byte\r
+ #define ATD0DR1L_BIT6 _ATD0DR1.Overlap_STR.ATD0DR1LSTR.Bits.BIT6\r
+ #define ATD0DR1L_BIT7 _ATD0DR1.Overlap_STR.ATD0DR1LSTR.Bits.BIT7\r
+ #define ATD0DR1L_BIT_6 _ATD0DR1.Overlap_STR.ATD0DR1LSTR.MergedBits.grpBIT_6\r
+ #define ATD0DR1L_BIT ATD0DR1L_BIT_6\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word BIT6 :1; /* Bit 6 */\r
+ word BIT7 :1; /* Bit 7 */\r
+ word BIT8 :1; /* Bit 8 */\r
+ word BIT9 :1; /* Bit 9 */\r
+ word BIT10 :1; /* Bit 10 */\r
+ word BIT11 :1; /* Bit 11 */\r
+ word BIT12 :1; /* Bit 12 */\r
+ word BIT13 :1; /* Bit 13 */\r
+ word BIT14 :1; /* Bit 14 */\r
+ word BIT15 :1; /* Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word grpBIT_6 :10;\r
+ } MergedBits;\r
+} ATD0DR1STR;\r
+extern volatile ATD0DR1STR _ATD0DR1 @(REG_BASE + 0x00000092);\r
+#define ATD0DR1 _ATD0DR1.Word\r
+#define ATD0DR1_BIT6 _ATD0DR1.Bits.BIT6\r
+#define ATD0DR1_BIT7 _ATD0DR1.Bits.BIT7\r
+#define ATD0DR1_BIT8 _ATD0DR1.Bits.BIT8\r
+#define ATD0DR1_BIT9 _ATD0DR1.Bits.BIT9\r
+#define ATD0DR1_BIT10 _ATD0DR1.Bits.BIT10\r
+#define ATD0DR1_BIT11 _ATD0DR1.Bits.BIT11\r
+#define ATD0DR1_BIT12 _ATD0DR1.Bits.BIT12\r
+#define ATD0DR1_BIT13 _ATD0DR1.Bits.BIT13\r
+#define ATD0DR1_BIT14 _ATD0DR1.Bits.BIT14\r
+#define ATD0DR1_BIT15 _ATD0DR1.Bits.BIT15\r
+#define ATD0DR1_BIT_6 _ATD0DR1.MergedBits.grpBIT_6\r
+#define ATD0DR1_BIT ATD0DR1_BIT_6\r
+\r
+\r
+/*** ATD0DR2 - ATD 0 Conversion Result Register 2; 0x00000094 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** ATD0DR2H - ATD 0 Conversion Result Register 2 High; 0x00000094 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT8 :1; /* Bit 8 */\r
+ byte BIT9 :1; /* Bit 9 */\r
+ byte BIT10 :1; /* Bit 10 */\r
+ byte BIT11 :1; /* Bit 11 */\r
+ byte BIT12 :1; /* Bit 12 */\r
+ byte BIT13 :1; /* Bit 13 */\r
+ byte BIT14 :1; /* Bit 14 */\r
+ byte BIT15 :1; /* Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT_8 :8;\r
+ } MergedBits;\r
+ } ATD0DR2HSTR;\r
+ #define ATD0DR2H _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Byte\r
+ #define ATD0DR2H_BIT8 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT8\r
+ #define ATD0DR2H_BIT9 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT9\r
+ #define ATD0DR2H_BIT10 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT10\r
+ #define ATD0DR2H_BIT11 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT11\r
+ #define ATD0DR2H_BIT12 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT12\r
+ #define ATD0DR2H_BIT13 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT13\r
+ #define ATD0DR2H_BIT14 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT14\r
+ #define ATD0DR2H_BIT15 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT15\r
+ #define ATD0DR2H_BIT_8 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.MergedBits.grpBIT_8\r
+ #define ATD0DR2H_BIT ATD0DR2H_BIT_8\r
+ \r
+ /*** ATD0DR2L - ATD 0 Conversion Result Register 2 Low; 0x00000095 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte BIT6 :1; /* Bit 6 */\r
+ byte BIT7 :1; /* Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpBIT_6 :2;\r
+ } MergedBits;\r
+ } ATD0DR2LSTR;\r
+ #define ATD0DR2L _ATD0DR2.Overlap_STR.ATD0DR2LSTR.Byte\r
+ #define ATD0DR2L_BIT6 _ATD0DR2.Overlap_STR.ATD0DR2LSTR.Bits.BIT6\r
+ #define ATD0DR2L_BIT7 _ATD0DR2.Overlap_STR.ATD0DR2LSTR.Bits.BIT7\r
+ #define ATD0DR2L_BIT_6 _ATD0DR2.Overlap_STR.ATD0DR2LSTR.MergedBits.grpBIT_6\r
+ #define ATD0DR2L_BIT ATD0DR2L_BIT_6\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word BIT6 :1; /* Bit 6 */\r
+ word BIT7 :1; /* Bit 7 */\r
+ word BIT8 :1; /* Bit 8 */\r
+ word BIT9 :1; /* Bit 9 */\r
+ word BIT10 :1; /* Bit 10 */\r
+ word BIT11 :1; /* Bit 11 */\r
+ word BIT12 :1; /* Bit 12 */\r
+ word BIT13 :1; /* Bit 13 */\r
+ word BIT14 :1; /* Bit 14 */\r
+ word BIT15 :1; /* Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word grpBIT_6 :10;\r
+ } MergedBits;\r
+} ATD0DR2STR;\r
+extern volatile ATD0DR2STR _ATD0DR2 @(REG_BASE + 0x00000094);\r
+#define ATD0DR2 _ATD0DR2.Word\r
+#define ATD0DR2_BIT6 _ATD0DR2.Bits.BIT6\r
+#define ATD0DR2_BIT7 _ATD0DR2.Bits.BIT7\r
+#define ATD0DR2_BIT8 _ATD0DR2.Bits.BIT8\r
+#define ATD0DR2_BIT9 _ATD0DR2.Bits.BIT9\r
+#define ATD0DR2_BIT10 _ATD0DR2.Bits.BIT10\r
+#define ATD0DR2_BIT11 _ATD0DR2.Bits.BIT11\r
+#define ATD0DR2_BIT12 _ATD0DR2.Bits.BIT12\r
+#define ATD0DR2_BIT13 _ATD0DR2.Bits.BIT13\r
+#define ATD0DR2_BIT14 _ATD0DR2.Bits.BIT14\r
+#define ATD0DR2_BIT15 _ATD0DR2.Bits.BIT15\r
+#define ATD0DR2_BIT_6 _ATD0DR2.MergedBits.grpBIT_6\r
+#define ATD0DR2_BIT ATD0DR2_BIT_6\r
+\r
+\r
+/*** ATD0DR3 - ATD 0 Conversion Result Register 3; 0x00000096 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** ATD0DR3H - ATD 0 Conversion Result Register 3 High; 0x00000096 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT8 :1; /* Bit 8 */\r
+ byte BIT9 :1; /* Bit 9 */\r
+ byte BIT10 :1; /* Bit 10 */\r
+ byte BIT11 :1; /* Bit 11 */\r
+ byte BIT12 :1; /* Bit 12 */\r
+ byte BIT13 :1; /* Bit 13 */\r
+ byte BIT14 :1; /* Bit 14 */\r
+ byte BIT15 :1; /* Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT_8 :8;\r
+ } MergedBits;\r
+ } ATD0DR3HSTR;\r
+ #define ATD0DR3H _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Byte\r
+ #define ATD0DR3H_BIT8 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT8\r
+ #define ATD0DR3H_BIT9 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT9\r
+ #define ATD0DR3H_BIT10 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT10\r
+ #define ATD0DR3H_BIT11 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT11\r
+ #define ATD0DR3H_BIT12 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT12\r
+ #define ATD0DR3H_BIT13 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT13\r
+ #define ATD0DR3H_BIT14 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT14\r
+ #define ATD0DR3H_BIT15 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT15\r
+ #define ATD0DR3H_BIT_8 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.MergedBits.grpBIT_8\r
+ #define ATD0DR3H_BIT ATD0DR3H_BIT_8\r
+ \r
+ /*** ATD0DR3L - ATD 0 Conversion Result Register 3 Low; 0x00000097 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte BIT6 :1; /* Bit 6 */\r
+ byte BIT7 :1; /* Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpBIT_6 :2;\r
+ } MergedBits;\r
+ } ATD0DR3LSTR;\r
+ #define ATD0DR3L _ATD0DR3.Overlap_STR.ATD0DR3LSTR.Byte\r
+ #define ATD0DR3L_BIT6 _ATD0DR3.Overlap_STR.ATD0DR3LSTR.Bits.BIT6\r
+ #define ATD0DR3L_BIT7 _ATD0DR3.Overlap_STR.ATD0DR3LSTR.Bits.BIT7\r
+ #define ATD0DR3L_BIT_6 _ATD0DR3.Overlap_STR.ATD0DR3LSTR.MergedBits.grpBIT_6\r
+ #define ATD0DR3L_BIT ATD0DR3L_BIT_6\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word BIT6 :1; /* Bit 6 */\r
+ word BIT7 :1; /* Bit 7 */\r
+ word BIT8 :1; /* Bit 8 */\r
+ word BIT9 :1; /* Bit 9 */\r
+ word BIT10 :1; /* Bit 10 */\r
+ word BIT11 :1; /* Bit 11 */\r
+ word BIT12 :1; /* Bit 12 */\r
+ word BIT13 :1; /* Bit 13 */\r
+ word BIT14 :1; /* Bit 14 */\r
+ word BIT15 :1; /* Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word grpBIT_6 :10;\r
+ } MergedBits;\r
+} ATD0DR3STR;\r
+extern volatile ATD0DR3STR _ATD0DR3 @(REG_BASE + 0x00000096);\r
+#define ATD0DR3 _ATD0DR3.Word\r
+#define ATD0DR3_BIT6 _ATD0DR3.Bits.BIT6\r
+#define ATD0DR3_BIT7 _ATD0DR3.Bits.BIT7\r
+#define ATD0DR3_BIT8 _ATD0DR3.Bits.BIT8\r
+#define ATD0DR3_BIT9 _ATD0DR3.Bits.BIT9\r
+#define ATD0DR3_BIT10 _ATD0DR3.Bits.BIT10\r
+#define ATD0DR3_BIT11 _ATD0DR3.Bits.BIT11\r
+#define ATD0DR3_BIT12 _ATD0DR3.Bits.BIT12\r
+#define ATD0DR3_BIT13 _ATD0DR3.Bits.BIT13\r
+#define ATD0DR3_BIT14 _ATD0DR3.Bits.BIT14\r
+#define ATD0DR3_BIT15 _ATD0DR3.Bits.BIT15\r
+#define ATD0DR3_BIT_6 _ATD0DR3.MergedBits.grpBIT_6\r
+#define ATD0DR3_BIT ATD0DR3_BIT_6\r
+\r
+\r
+/*** ATD0DR4 - ATD 0 Conversion Result Register 4; 0x00000098 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** ATD0DR4H - ATD 0 Conversion Result Register 4 High; 0x00000098 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT8 :1; /* Bit 8 */\r
+ byte BIT9 :1; /* Bit 9 */\r
+ byte BIT10 :1; /* Bit 10 */\r
+ byte BIT11 :1; /* Bit 11 */\r
+ byte BIT12 :1; /* Bit 12 */\r
+ byte BIT13 :1; /* Bit 13 */\r
+ byte BIT14 :1; /* Bit 14 */\r
+ byte BIT15 :1; /* Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT_8 :8;\r
+ } MergedBits;\r
+ } ATD0DR4HSTR;\r
+ #define ATD0DR4H _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Byte\r
+ #define ATD0DR4H_BIT8 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT8\r
+ #define ATD0DR4H_BIT9 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT9\r
+ #define ATD0DR4H_BIT10 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT10\r
+ #define ATD0DR4H_BIT11 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT11\r
+ #define ATD0DR4H_BIT12 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT12\r
+ #define ATD0DR4H_BIT13 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT13\r
+ #define ATD0DR4H_BIT14 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT14\r
+ #define ATD0DR4H_BIT15 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT15\r
+ #define ATD0DR4H_BIT_8 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.MergedBits.grpBIT_8\r
+ #define ATD0DR4H_BIT ATD0DR4H_BIT_8\r
+ \r
+ /*** ATD0DR4L - ATD 0 Conversion Result Register 4 Low; 0x00000099 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte BIT6 :1; /* Bit 6 */\r
+ byte BIT7 :1; /* Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpBIT_6 :2;\r
+ } MergedBits;\r
+ } ATD0DR4LSTR;\r
+ #define ATD0DR4L _ATD0DR4.Overlap_STR.ATD0DR4LSTR.Byte\r
+ #define ATD0DR4L_BIT6 _ATD0DR4.Overlap_STR.ATD0DR4LSTR.Bits.BIT6\r
+ #define ATD0DR4L_BIT7 _ATD0DR4.Overlap_STR.ATD0DR4LSTR.Bits.BIT7\r
+ #define ATD0DR4L_BIT_6 _ATD0DR4.Overlap_STR.ATD0DR4LSTR.MergedBits.grpBIT_6\r
+ #define ATD0DR4L_BIT ATD0DR4L_BIT_6\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word BIT6 :1; /* Bit 6 */\r
+ word BIT7 :1; /* Bit 7 */\r
+ word BIT8 :1; /* Bit 8 */\r
+ word BIT9 :1; /* Bit 9 */\r
+ word BIT10 :1; /* Bit 10 */\r
+ word BIT11 :1; /* Bit 11 */\r
+ word BIT12 :1; /* Bit 12 */\r
+ word BIT13 :1; /* Bit 13 */\r
+ word BIT14 :1; /* Bit 14 */\r
+ word BIT15 :1; /* Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word grpBIT_6 :10;\r
+ } MergedBits;\r
+} ATD0DR4STR;\r
+extern volatile ATD0DR4STR _ATD0DR4 @(REG_BASE + 0x00000098);\r
+#define ATD0DR4 _ATD0DR4.Word\r
+#define ATD0DR4_BIT6 _ATD0DR4.Bits.BIT6\r
+#define ATD0DR4_BIT7 _ATD0DR4.Bits.BIT7\r
+#define ATD0DR4_BIT8 _ATD0DR4.Bits.BIT8\r
+#define ATD0DR4_BIT9 _ATD0DR4.Bits.BIT9\r
+#define ATD0DR4_BIT10 _ATD0DR4.Bits.BIT10\r
+#define ATD0DR4_BIT11 _ATD0DR4.Bits.BIT11\r
+#define ATD0DR4_BIT12 _ATD0DR4.Bits.BIT12\r
+#define ATD0DR4_BIT13 _ATD0DR4.Bits.BIT13\r
+#define ATD0DR4_BIT14 _ATD0DR4.Bits.BIT14\r
+#define ATD0DR4_BIT15 _ATD0DR4.Bits.BIT15\r
+#define ATD0DR4_BIT_6 _ATD0DR4.MergedBits.grpBIT_6\r
+#define ATD0DR4_BIT ATD0DR4_BIT_6\r
+\r
+\r
+/*** ATD0DR5 - ATD 0 Conversion Result Register 5; 0x0000009A ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** ATD0DR5H - ATD 0 Conversion Result Register 5 High; 0x0000009A ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT8 :1; /* Bit 8 */\r
+ byte BIT9 :1; /* Bit 9 */\r
+ byte BIT10 :1; /* Bit 10 */\r
+ byte BIT11 :1; /* Bit 11 */\r
+ byte BIT12 :1; /* Bit 12 */\r
+ byte BIT13 :1; /* Bit 13 */\r
+ byte BIT14 :1; /* Bit 14 */\r
+ byte BIT15 :1; /* Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT_8 :8;\r
+ } MergedBits;\r
+ } ATD0DR5HSTR;\r
+ #define ATD0DR5H _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Byte\r
+ #define ATD0DR5H_BIT8 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT8\r
+ #define ATD0DR5H_BIT9 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT9\r
+ #define ATD0DR5H_BIT10 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT10\r
+ #define ATD0DR5H_BIT11 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT11\r
+ #define ATD0DR5H_BIT12 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT12\r
+ #define ATD0DR5H_BIT13 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT13\r
+ #define ATD0DR5H_BIT14 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT14\r
+ #define ATD0DR5H_BIT15 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT15\r
+ #define ATD0DR5H_BIT_8 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.MergedBits.grpBIT_8\r
+ #define ATD0DR5H_BIT ATD0DR5H_BIT_8\r
+ \r
+ /*** ATD0DR5L - ATD 0 Conversion Result Register 5 Low; 0x0000009B ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte BIT6 :1; /* Bit 6 */\r
+ byte BIT7 :1; /* Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpBIT_6 :2;\r
+ } MergedBits;\r
+ } ATD0DR5LSTR;\r
+ #define ATD0DR5L _ATD0DR5.Overlap_STR.ATD0DR5LSTR.Byte\r
+ #define ATD0DR5L_BIT6 _ATD0DR5.Overlap_STR.ATD0DR5LSTR.Bits.BIT6\r
+ #define ATD0DR5L_BIT7 _ATD0DR5.Overlap_STR.ATD0DR5LSTR.Bits.BIT7\r
+ #define ATD0DR5L_BIT_6 _ATD0DR5.Overlap_STR.ATD0DR5LSTR.MergedBits.grpBIT_6\r
+ #define ATD0DR5L_BIT ATD0DR5L_BIT_6\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word BIT6 :1; /* Bit 6 */\r
+ word BIT7 :1; /* Bit 7 */\r
+ word BIT8 :1; /* Bit 8 */\r
+ word BIT9 :1; /* Bit 9 */\r
+ word BIT10 :1; /* Bit 10 */\r
+ word BIT11 :1; /* Bit 11 */\r
+ word BIT12 :1; /* Bit 12 */\r
+ word BIT13 :1; /* Bit 13 */\r
+ word BIT14 :1; /* Bit 14 */\r
+ word BIT15 :1; /* Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word grpBIT_6 :10;\r
+ } MergedBits;\r
+} ATD0DR5STR;\r
+extern volatile ATD0DR5STR _ATD0DR5 @(REG_BASE + 0x0000009A);\r
+#define ATD0DR5 _ATD0DR5.Word\r
+#define ATD0DR5_BIT6 _ATD0DR5.Bits.BIT6\r
+#define ATD0DR5_BIT7 _ATD0DR5.Bits.BIT7\r
+#define ATD0DR5_BIT8 _ATD0DR5.Bits.BIT8\r
+#define ATD0DR5_BIT9 _ATD0DR5.Bits.BIT9\r
+#define ATD0DR5_BIT10 _ATD0DR5.Bits.BIT10\r
+#define ATD0DR5_BIT11 _ATD0DR5.Bits.BIT11\r
+#define ATD0DR5_BIT12 _ATD0DR5.Bits.BIT12\r
+#define ATD0DR5_BIT13 _ATD0DR5.Bits.BIT13\r
+#define ATD0DR5_BIT14 _ATD0DR5.Bits.BIT14\r
+#define ATD0DR5_BIT15 _ATD0DR5.Bits.BIT15\r
+#define ATD0DR5_BIT_6 _ATD0DR5.MergedBits.grpBIT_6\r
+#define ATD0DR5_BIT ATD0DR5_BIT_6\r
+\r
+\r
+/*** ATD0DR6 - ATD 0 Conversion Result Register 6; 0x0000009C ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** ATD0DR6H - ATD 0 Conversion Result Register 6 High; 0x0000009C ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT8 :1; /* Bit 8 */\r
+ byte BIT9 :1; /* Bit 9 */\r
+ byte BIT10 :1; /* Bit 10 */\r
+ byte BIT11 :1; /* Bit 11 */\r
+ byte BIT12 :1; /* Bit 12 */\r
+ byte BIT13 :1; /* Bit 13 */\r
+ byte BIT14 :1; /* Bit 14 */\r
+ byte BIT15 :1; /* Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT_8 :8;\r
+ } MergedBits;\r
+ } ATD0DR6HSTR;\r
+ #define ATD0DR6H _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Byte\r
+ #define ATD0DR6H_BIT8 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT8\r
+ #define ATD0DR6H_BIT9 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT9\r
+ #define ATD0DR6H_BIT10 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT10\r
+ #define ATD0DR6H_BIT11 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT11\r
+ #define ATD0DR6H_BIT12 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT12\r
+ #define ATD0DR6H_BIT13 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT13\r
+ #define ATD0DR6H_BIT14 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT14\r
+ #define ATD0DR6H_BIT15 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT15\r
+ #define ATD0DR6H_BIT_8 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.MergedBits.grpBIT_8\r
+ #define ATD0DR6H_BIT ATD0DR6H_BIT_8\r
+ \r
+ /*** ATD0DR6L - ATD 0 Conversion Result Register 6 Low; 0x0000009D ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte BIT6 :1; /* Bit 6 */\r
+ byte BIT7 :1; /* Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpBIT_6 :2;\r
+ } MergedBits;\r
+ } ATD0DR6LSTR;\r
+ #define ATD0DR6L _ATD0DR6.Overlap_STR.ATD0DR6LSTR.Byte\r
+ #define ATD0DR6L_BIT6 _ATD0DR6.Overlap_STR.ATD0DR6LSTR.Bits.BIT6\r
+ #define ATD0DR6L_BIT7 _ATD0DR6.Overlap_STR.ATD0DR6LSTR.Bits.BIT7\r
+ #define ATD0DR6L_BIT_6 _ATD0DR6.Overlap_STR.ATD0DR6LSTR.MergedBits.grpBIT_6\r
+ #define ATD0DR6L_BIT ATD0DR6L_BIT_6\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word BIT6 :1; /* Bit 6 */\r
+ word BIT7 :1; /* Bit 7 */\r
+ word BIT8 :1; /* Bit 8 */\r
+ word BIT9 :1; /* Bit 9 */\r
+ word BIT10 :1; /* Bit 10 */\r
+ word BIT11 :1; /* Bit 11 */\r
+ word BIT12 :1; /* Bit 12 */\r
+ word BIT13 :1; /* Bit 13 */\r
+ word BIT14 :1; /* Bit 14 */\r
+ word BIT15 :1; /* Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word grpBIT_6 :10;\r
+ } MergedBits;\r
+} ATD0DR6STR;\r
+extern volatile ATD0DR6STR _ATD0DR6 @(REG_BASE + 0x0000009C);\r
+#define ATD0DR6 _ATD0DR6.Word\r
+#define ATD0DR6_BIT6 _ATD0DR6.Bits.BIT6\r
+#define ATD0DR6_BIT7 _ATD0DR6.Bits.BIT7\r
+#define ATD0DR6_BIT8 _ATD0DR6.Bits.BIT8\r
+#define ATD0DR6_BIT9 _ATD0DR6.Bits.BIT9\r
+#define ATD0DR6_BIT10 _ATD0DR6.Bits.BIT10\r
+#define ATD0DR6_BIT11 _ATD0DR6.Bits.BIT11\r
+#define ATD0DR6_BIT12 _ATD0DR6.Bits.BIT12\r
+#define ATD0DR6_BIT13 _ATD0DR6.Bits.BIT13\r
+#define ATD0DR6_BIT14 _ATD0DR6.Bits.BIT14\r
+#define ATD0DR6_BIT15 _ATD0DR6.Bits.BIT15\r
+#define ATD0DR6_BIT_6 _ATD0DR6.MergedBits.grpBIT_6\r
+#define ATD0DR6_BIT ATD0DR6_BIT_6\r
+\r
+\r
+/*** ATD0DR7 - ATD 0 Conversion Result Register 7; 0x0000009E ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** ATD0DR7H - ATD 0 Conversion Result Register 7 High; 0x0000009E ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT8 :1; /* Bit 8 */\r
+ byte BIT9 :1; /* Bit 9 */\r
+ byte BIT10 :1; /* Bit 10 */\r
+ byte BIT11 :1; /* Bit 11 */\r
+ byte BIT12 :1; /* Bit 12 */\r
+ byte BIT13 :1; /* Bit 13 */\r
+ byte BIT14 :1; /* Bit 14 */\r
+ byte BIT15 :1; /* Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT_8 :8;\r
+ } MergedBits;\r
+ } ATD0DR7HSTR;\r
+ #define ATD0DR7H _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Byte\r
+ #define ATD0DR7H_BIT8 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT8\r
+ #define ATD0DR7H_BIT9 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT9\r
+ #define ATD0DR7H_BIT10 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT10\r
+ #define ATD0DR7H_BIT11 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT11\r
+ #define ATD0DR7H_BIT12 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT12\r
+ #define ATD0DR7H_BIT13 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT13\r
+ #define ATD0DR7H_BIT14 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT14\r
+ #define ATD0DR7H_BIT15 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT15\r
+ #define ATD0DR7H_BIT_8 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.MergedBits.grpBIT_8\r
+ #define ATD0DR7H_BIT ATD0DR7H_BIT_8\r
+ \r
+ /*** ATD0DR7L - ATD 0 Conversion Result Register 7 Low; 0x0000009F ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte BIT6 :1; /* Bit 6 */\r
+ byte BIT7 :1; /* Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpBIT_6 :2;\r
+ } MergedBits;\r
+ } ATD0DR7LSTR;\r
+ #define ATD0DR7L _ATD0DR7.Overlap_STR.ATD0DR7LSTR.Byte\r
+ #define ATD0DR7L_BIT6 _ATD0DR7.Overlap_STR.ATD0DR7LSTR.Bits.BIT6\r
+ #define ATD0DR7L_BIT7 _ATD0DR7.Overlap_STR.ATD0DR7LSTR.Bits.BIT7\r
+ #define ATD0DR7L_BIT_6 _ATD0DR7.Overlap_STR.ATD0DR7LSTR.MergedBits.grpBIT_6\r
+ #define ATD0DR7L_BIT ATD0DR7L_BIT_6\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word BIT6 :1; /* Bit 6 */\r
+ word BIT7 :1; /* Bit 7 */\r
+ word BIT8 :1; /* Bit 8 */\r
+ word BIT9 :1; /* Bit 9 */\r
+ word BIT10 :1; /* Bit 10 */\r
+ word BIT11 :1; /* Bit 11 */\r
+ word BIT12 :1; /* Bit 12 */\r
+ word BIT13 :1; /* Bit 13 */\r
+ word BIT14 :1; /* Bit 14 */\r
+ word BIT15 :1; /* Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word grpBIT_6 :10;\r
+ } MergedBits;\r
+} ATD0DR7STR;\r
+extern volatile ATD0DR7STR _ATD0DR7 @(REG_BASE + 0x0000009E);\r
+#define ATD0DR7 _ATD0DR7.Word\r
+#define ATD0DR7_BIT6 _ATD0DR7.Bits.BIT6\r
+#define ATD0DR7_BIT7 _ATD0DR7.Bits.BIT7\r
+#define ATD0DR7_BIT8 _ATD0DR7.Bits.BIT8\r
+#define ATD0DR7_BIT9 _ATD0DR7.Bits.BIT9\r
+#define ATD0DR7_BIT10 _ATD0DR7.Bits.BIT10\r
+#define ATD0DR7_BIT11 _ATD0DR7.Bits.BIT11\r
+#define ATD0DR7_BIT12 _ATD0DR7.Bits.BIT12\r
+#define ATD0DR7_BIT13 _ATD0DR7.Bits.BIT13\r
+#define ATD0DR7_BIT14 _ATD0DR7.Bits.BIT14\r
+#define ATD0DR7_BIT15 _ATD0DR7.Bits.BIT15\r
+#define ATD0DR7_BIT_6 _ATD0DR7.MergedBits.grpBIT_6\r
+#define ATD0DR7_BIT ATD0DR7_BIT_6\r
+\r
+\r
+/*** PWMCNT01 - PWM Channel Counter 01 Register; 0x000000AC ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** PWMCNT0 - PWM Channel Counter 0 Register; 0x000000AC ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } PWMCNT0STR;\r
+ #define PWMCNT0 _PWMCNT01.Overlap_STR.PWMCNT0STR.Byte\r
+ #define PWMCNT0_BIT _PWMCNT01.Overlap_STR.PWMCNT0STR.MergedBits.grpBIT\r
+ \r
+ /*** PWMCNT1 - PWM Channel Counter 1 Register; 0x000000AD ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } PWMCNT1STR;\r
+ #define PWMCNT1 _PWMCNT01.Overlap_STR.PWMCNT1STR.Byte\r
+ #define PWMCNT1_BIT _PWMCNT01.Overlap_STR.PWMCNT1STR.MergedBits.grpBIT\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word grpBIT :16;\r
+ } MergedBits;\r
+} PWMCNT01STR;\r
+extern volatile PWMCNT01STR _PWMCNT01 @(REG_BASE + 0x000000AC);\r
+#define PWMCNT01 _PWMCNT01.Word\r
+#define PWMCNT01_BIT _PWMCNT01.MergedBits.grpBIT\r
+\r
+\r
+/*** PWMCNT23 - PWM Channel Counter 23 Register; 0x000000AE ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** PWMCNT2 - PWM Channel Counter 2 Register; 0x000000AE ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } PWMCNT2STR;\r
+ #define PWMCNT2 _PWMCNT23.Overlap_STR.PWMCNT2STR.Byte\r
+ #define PWMCNT2_BIT _PWMCNT23.Overlap_STR.PWMCNT2STR.MergedBits.grpBIT\r
+ \r
+ /*** PWMCNT3 - PWM Channel Counter 3 Register; 0x000000AF ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } PWMCNT3STR;\r
+ #define PWMCNT3 _PWMCNT23.Overlap_STR.PWMCNT3STR.Byte\r
+ #define PWMCNT3_BIT _PWMCNT23.Overlap_STR.PWMCNT3STR.MergedBits.grpBIT\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word grpBIT :16;\r
+ } MergedBits;\r
+} PWMCNT23STR;\r
+extern volatile PWMCNT23STR _PWMCNT23 @(REG_BASE + 0x000000AE);\r
+#define PWMCNT23 _PWMCNT23.Word\r
+#define PWMCNT23_BIT _PWMCNT23.MergedBits.grpBIT\r
+\r
+\r
+/*** PWMCNT45 - PWM Channel Counter 45 Register; 0x000000B0 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** PWMCNT4 - PWM Channel Counter 4 Register; 0x000000B0 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } PWMCNT4STR;\r
+ #define PWMCNT4 _PWMCNT45.Overlap_STR.PWMCNT4STR.Byte\r
+ #define PWMCNT4_BIT _PWMCNT45.Overlap_STR.PWMCNT4STR.MergedBits.grpBIT\r
+ \r
+ /*** PWMCNT5 - PWM Channel Counter 5 Register; 0x000000B1 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } PWMCNT5STR;\r
+ #define PWMCNT5 _PWMCNT45.Overlap_STR.PWMCNT5STR.Byte\r
+ #define PWMCNT5_BIT _PWMCNT45.Overlap_STR.PWMCNT5STR.MergedBits.grpBIT\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word grpBIT :16;\r
+ } MergedBits;\r
+} PWMCNT45STR;\r
+extern volatile PWMCNT45STR _PWMCNT45 @(REG_BASE + 0x000000B0);\r
+#define PWMCNT45 _PWMCNT45.Word\r
+#define PWMCNT45_BIT _PWMCNT45.MergedBits.grpBIT\r
+\r
+\r
+/*** PWMCNT67 - PWM Channel Counter 67 Register; 0x000000B2 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** PWMCNT6 - PWM Channel Counter 6 Register; 0x000000B2 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } PWMCNT6STR;\r
+ #define PWMCNT6 _PWMCNT67.Overlap_STR.PWMCNT6STR.Byte\r
+ #define PWMCNT6_BIT _PWMCNT67.Overlap_STR.PWMCNT6STR.MergedBits.grpBIT\r
+ \r
+ /*** PWMCNT7 - PWM Channel Counter 7 Register; 0x000000B3 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } PWMCNT7STR;\r
+ #define PWMCNT7 _PWMCNT67.Overlap_STR.PWMCNT7STR.Byte\r
+ #define PWMCNT7_BIT _PWMCNT67.Overlap_STR.PWMCNT7STR.MergedBits.grpBIT\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word grpBIT :16;\r
+ } MergedBits;\r
+} PWMCNT67STR;\r
+extern volatile PWMCNT67STR _PWMCNT67 @(REG_BASE + 0x000000B2);\r
+#define PWMCNT67 _PWMCNT67.Word\r
+#define PWMCNT67_BIT _PWMCNT67.MergedBits.grpBIT\r
+\r
+\r
+/*** PWMPER01 - PWM Channel Period 01 Register; 0x000000B4 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** PWMPER0 - PWM Channel Period 0 Register; 0x000000B4 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } PWMPER0STR;\r
+ #define PWMPER0 _PWMPER01.Overlap_STR.PWMPER0STR.Byte\r
+ #define PWMPER0_BIT _PWMPER01.Overlap_STR.PWMPER0STR.MergedBits.grpBIT\r
+ \r
+ /*** PWMPER1 - PWM Channel Period 1 Register; 0x000000B5 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } PWMPER1STR;\r
+ #define PWMPER1 _PWMPER01.Overlap_STR.PWMPER1STR.Byte\r
+ #define PWMPER1_BIT _PWMPER01.Overlap_STR.PWMPER1STR.MergedBits.grpBIT\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word grpBIT :16;\r
+ } MergedBits;\r
+} PWMPER01STR;\r
+extern volatile PWMPER01STR _PWMPER01 @(REG_BASE + 0x000000B4);\r
+#define PWMPER01 _PWMPER01.Word\r
+#define PWMPER01_BIT _PWMPER01.MergedBits.grpBIT\r
+\r
+\r
+/*** PWMPER23 - PWM Channel Period 23 Register; 0x000000B6 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** PWMPER2 - PWM Channel Period 2 Register; 0x000000B6 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } PWMPER2STR;\r
+ #define PWMPER2 _PWMPER23.Overlap_STR.PWMPER2STR.Byte\r
+ #define PWMPER2_BIT _PWMPER23.Overlap_STR.PWMPER2STR.MergedBits.grpBIT\r
+ \r
+ /*** PWMPER3 - PWM Channel Period 3 Register; 0x000000B7 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } PWMPER3STR;\r
+ #define PWMPER3 _PWMPER23.Overlap_STR.PWMPER3STR.Byte\r
+ #define PWMPER3_BIT _PWMPER23.Overlap_STR.PWMPER3STR.MergedBits.grpBIT\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word grpBIT :16;\r
+ } MergedBits;\r
+} PWMPER23STR;\r
+extern volatile PWMPER23STR _PWMPER23 @(REG_BASE + 0x000000B6);\r
+#define PWMPER23 _PWMPER23.Word\r
+#define PWMPER23_BIT _PWMPER23.MergedBits.grpBIT\r
+\r
+\r
+/*** PWMPER45 - PWM Channel Period 45 Register; 0x000000B8 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** PWMPER4 - PWM Channel Period 4 Register; 0x000000B8 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } PWMPER4STR;\r
+ #define PWMPER4 _PWMPER45.Overlap_STR.PWMPER4STR.Byte\r
+ #define PWMPER4_BIT _PWMPER45.Overlap_STR.PWMPER4STR.MergedBits.grpBIT\r
+ \r
+ /*** PWMPER5 - PWM Channel Period 5 Register; 0x000000B9 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } PWMPER5STR;\r
+ #define PWMPER5 _PWMPER45.Overlap_STR.PWMPER5STR.Byte\r
+ #define PWMPER5_BIT _PWMPER45.Overlap_STR.PWMPER5STR.MergedBits.grpBIT\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word grpBIT :16;\r
+ } MergedBits;\r
+} PWMPER45STR;\r
+extern volatile PWMPER45STR _PWMPER45 @(REG_BASE + 0x000000B8);\r
+#define PWMPER45 _PWMPER45.Word\r
+#define PWMPER45_BIT _PWMPER45.MergedBits.grpBIT\r
+\r
+\r
+/*** PWMPER67 - PWM Channel Period 67 Register; 0x000000BA ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** PWMPER6 - PWM Channel Period 6 Register; 0x000000BA ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } PWMPER6STR;\r
+ #define PWMPER6 _PWMPER67.Overlap_STR.PWMPER6STR.Byte\r
+ #define PWMPER6_BIT _PWMPER67.Overlap_STR.PWMPER6STR.MergedBits.grpBIT\r
+ \r
+ /*** PWMPER7 - PWM Channel Period 7 Register; 0x000000BB ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } PWMPER7STR;\r
+ #define PWMPER7 _PWMPER67.Overlap_STR.PWMPER7STR.Byte\r
+ #define PWMPER7_BIT _PWMPER67.Overlap_STR.PWMPER7STR.MergedBits.grpBIT\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word grpBIT :16;\r
+ } MergedBits;\r
+} PWMPER67STR;\r
+extern volatile PWMPER67STR _PWMPER67 @(REG_BASE + 0x000000BA);\r
+#define PWMPER67 _PWMPER67.Word\r
+#define PWMPER67_BIT _PWMPER67.MergedBits.grpBIT\r
+\r
+\r
+/*** PWMDTY01 - PWM Channel Duty 01 Register; 0x000000BC ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** PWMDTY0 - PWM Channel Duty 0 Register; 0x000000BC ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } PWMDTY0STR;\r
+ #define PWMDTY0 _PWMDTY01.Overlap_STR.PWMDTY0STR.Byte\r
+ #define PWMDTY0_BIT _PWMDTY01.Overlap_STR.PWMDTY0STR.MergedBits.grpBIT\r
+ \r
+ /*** PWMDTY1 - PWM Channel Duty 1 Register; 0x000000BD ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } PWMDTY1STR;\r
+ #define PWMDTY1 _PWMDTY01.Overlap_STR.PWMDTY1STR.Byte\r
+ #define PWMDTY1_BIT _PWMDTY01.Overlap_STR.PWMDTY1STR.MergedBits.grpBIT\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word grpBIT :16;\r
+ } MergedBits;\r
+} PWMDTY01STR;\r
+extern volatile PWMDTY01STR _PWMDTY01 @(REG_BASE + 0x000000BC);\r
+#define PWMDTY01 _PWMDTY01.Word\r
+#define PWMDTY01_BIT _PWMDTY01.MergedBits.grpBIT\r
+\r
+\r
+/*** PWMDTY23 - PWM Channel Duty 23 Register; 0x000000BE ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** PWMDTY2 - PWM Channel Duty 2 Register; 0x000000BE ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } PWMDTY2STR;\r
+ #define PWMDTY2 _PWMDTY23.Overlap_STR.PWMDTY2STR.Byte\r
+ #define PWMDTY2_BIT _PWMDTY23.Overlap_STR.PWMDTY2STR.MergedBits.grpBIT\r
+ \r
+ /*** PWMDTY3 - PWM Channel Duty 3 Register; 0x000000BF ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } PWMDTY3STR;\r
+ #define PWMDTY3 _PWMDTY23.Overlap_STR.PWMDTY3STR.Byte\r
+ #define PWMDTY3_BIT _PWMDTY23.Overlap_STR.PWMDTY3STR.MergedBits.grpBIT\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word grpBIT :16;\r
+ } MergedBits;\r
+} PWMDTY23STR;\r
+extern volatile PWMDTY23STR _PWMDTY23 @(REG_BASE + 0x000000BE);\r
+#define PWMDTY23 _PWMDTY23.Word\r
+#define PWMDTY23_BIT _PWMDTY23.MergedBits.grpBIT\r
+\r
+\r
+/*** PWMDTY45 - PWM Channel Duty 45 Register; 0x000000C0 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** PWMDTY4 - PWM Channel Duty 4 Register; 0x000000C0 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } PWMDTY4STR;\r
+ #define PWMDTY4 _PWMDTY45.Overlap_STR.PWMDTY4STR.Byte\r
+ #define PWMDTY4_BIT _PWMDTY45.Overlap_STR.PWMDTY4STR.MergedBits.grpBIT\r
+ \r
+ /*** PWMDTY5 - PWM Channel Duty 5 Register; 0x000000C1 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } PWMDTY5STR;\r
+ #define PWMDTY5 _PWMDTY45.Overlap_STR.PWMDTY5STR.Byte\r
+ #define PWMDTY5_BIT _PWMDTY45.Overlap_STR.PWMDTY5STR.MergedBits.grpBIT\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word grpBIT :16;\r
+ } MergedBits;\r
+} PWMDTY45STR;\r
+extern volatile PWMDTY45STR _PWMDTY45 @(REG_BASE + 0x000000C0);\r
+#define PWMDTY45 _PWMDTY45.Word\r
+#define PWMDTY45_BIT _PWMDTY45.MergedBits.grpBIT\r
+\r
+\r
+/*** PWMDTY67 - PWM Channel Duty 67 Register; 0x000000C2 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** PWMDTY6 - PWM Channel Duty 6 Register; 0x000000C2 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } PWMDTY6STR;\r
+ #define PWMDTY6 _PWMDTY67.Overlap_STR.PWMDTY6STR.Byte\r
+ #define PWMDTY6_BIT _PWMDTY67.Overlap_STR.PWMDTY6STR.MergedBits.grpBIT\r
+ \r
+ /*** PWMDTY7 - PWM Channel Duty 7 Register; 0x000000C3 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } PWMDTY7STR;\r
+ #define PWMDTY7 _PWMDTY67.Overlap_STR.PWMDTY7STR.Byte\r
+ #define PWMDTY7_BIT _PWMDTY67.Overlap_STR.PWMDTY7STR.MergedBits.grpBIT\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word grpBIT :16;\r
+ } MergedBits;\r
+} PWMDTY67STR;\r
+extern volatile PWMDTY67STR _PWMDTY67 @(REG_BASE + 0x000000C2);\r
+#define PWMDTY67 _PWMDTY67.Word\r
+#define PWMDTY67_BIT _PWMDTY67.MergedBits.grpBIT\r
+\r
+\r
+/*** SCI0BD - SCI 0 Baud Rate Register; 0x000000C8 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** SCI0BDH - SCI 0 Baud Rate Register High; 0x000000C8 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte SBR8 :1; /* SCI 0 baud rate Bit 8 */\r
+ byte SBR9 :1; /* SCI 0 baud rate Bit 9 */\r
+ byte SBR10 :1; /* SCI 0 baud rate Bit 10 */\r
+ byte SBR11 :1; /* SCI 0 baud rate Bit 11 */\r
+ byte SBR12 :1; /* SCI 0 baud rate Bit 12 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpSBR_8 :5;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+ } SCI0BDHSTR;\r
+ #define SCI0BDH _SCI0BD.Overlap_STR.SCI0BDHSTR.Byte\r
+ #define SCI0BDH_SBR8 _SCI0BD.Overlap_STR.SCI0BDHSTR.Bits.SBR8\r
+ #define SCI0BDH_SBR9 _SCI0BD.Overlap_STR.SCI0BDHSTR.Bits.SBR9\r
+ #define SCI0BDH_SBR10 _SCI0BD.Overlap_STR.SCI0BDHSTR.Bits.SBR10\r
+ #define SCI0BDH_SBR11 _SCI0BD.Overlap_STR.SCI0BDHSTR.Bits.SBR11\r
+ #define SCI0BDH_SBR12 _SCI0BD.Overlap_STR.SCI0BDHSTR.Bits.SBR12\r
+ #define SCI0BDH_SBR_8 _SCI0BD.Overlap_STR.SCI0BDHSTR.MergedBits.grpSBR_8\r
+ #define SCI0BDH_SBR SCI0BDH_SBR_8\r
+ \r
+ /*** SCI0BDL - SCI 0 Baud Rate Register Low; 0x000000C9 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte SBR0 :1; /* SCI 0 baud rate Bit 0 */\r
+ byte SBR1 :1; /* SCI 0 baud rate Bit 1 */\r
+ byte SBR2 :1; /* SCI 0 baud rate Bit 2 */\r
+ byte SBR3 :1; /* SCI 0 baud rate Bit 3 */\r
+ byte SBR4 :1; /* SCI 0 baud rate Bit 4 */\r
+ byte SBR5 :1; /* SCI 0 baud rate Bit 5 */\r
+ byte SBR6 :1; /* SCI 0 baud rate Bit 6 */\r
+ byte SBR7 :1; /* SCI 0 baud rate Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpSBR :8;\r
+ } MergedBits;\r
+ } SCI0BDLSTR;\r
+ #define SCI0BDL _SCI0BD.Overlap_STR.SCI0BDLSTR.Byte\r
+ #define SCI0BDL_SBR0 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR0\r
+ #define SCI0BDL_SBR1 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR1\r
+ #define SCI0BDL_SBR2 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR2\r
+ #define SCI0BDL_SBR3 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR3\r
+ #define SCI0BDL_SBR4 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR4\r
+ #define SCI0BDL_SBR5 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR5\r
+ #define SCI0BDL_SBR6 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR6\r
+ #define SCI0BDL_SBR7 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR7\r
+ #define SCI0BDL_SBR _SCI0BD.Overlap_STR.SCI0BDLSTR.MergedBits.grpSBR\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word SBR0 :1; /* SCI 0 baud rate Bit 0 */\r
+ word SBR1 :1; /* SCI 0 baud rate Bit 1 */\r
+ word SBR2 :1; /* SCI 0 baud rate Bit 2 */\r
+ word SBR3 :1; /* SCI 0 baud rate Bit 3 */\r
+ word SBR4 :1; /* SCI 0 baud rate Bit 4 */\r
+ word SBR5 :1; /* SCI 0 baud rate Bit 5 */\r
+ word SBR6 :1; /* SCI 0 baud rate Bit 6 */\r
+ word SBR7 :1; /* SCI 0 baud rate Bit 7 */\r
+ word SBR8 :1; /* SCI 0 baud rate Bit 8 */\r
+ word SBR9 :1; /* SCI 0 baud rate Bit 9 */\r
+ word SBR10 :1; /* SCI 0 baud rate Bit 10 */\r
+ word SBR11 :1; /* SCI 0 baud rate Bit 11 */\r
+ word SBR12 :1; /* SCI 0 baud rate Bit 12 */\r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ } Bits;\r
+ struct {\r
+ word grpSBR :13;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ } MergedBits;\r
+} SCI0BDSTR;\r
+extern volatile SCI0BDSTR _SCI0BD @(REG_BASE + 0x000000C8);\r
+#define SCI0BD _SCI0BD.Word\r
+#define SCI0BD_SBR0 _SCI0BD.Bits.SBR0\r
+#define SCI0BD_SBR1 _SCI0BD.Bits.SBR1\r
+#define SCI0BD_SBR2 _SCI0BD.Bits.SBR2\r
+#define SCI0BD_SBR3 _SCI0BD.Bits.SBR3\r
+#define SCI0BD_SBR4 _SCI0BD.Bits.SBR4\r
+#define SCI0BD_SBR5 _SCI0BD.Bits.SBR5\r
+#define SCI0BD_SBR6 _SCI0BD.Bits.SBR6\r
+#define SCI0BD_SBR7 _SCI0BD.Bits.SBR7\r
+#define SCI0BD_SBR8 _SCI0BD.Bits.SBR8\r
+#define SCI0BD_SBR9 _SCI0BD.Bits.SBR9\r
+#define SCI0BD_SBR10 _SCI0BD.Bits.SBR10\r
+#define SCI0BD_SBR11 _SCI0BD.Bits.SBR11\r
+#define SCI0BD_SBR12 _SCI0BD.Bits.SBR12\r
+#define SCI0BD_SBR _SCI0BD.MergedBits.grpSBR\r
+\r
+\r
+/*** SCI1BD - SCI 1 Baud Rate Register; 0x000000D0 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** SCI1BDH - SCI 1 Baud Rate Register High; 0x000000D0 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte SBR8 :1; /* SCI 1 baud rate Bit 8 */\r
+ byte SBR9 :1; /* SCI 1 baud rate Bit 9 */\r
+ byte SBR10 :1; /* SCI 1 baud rate Bit 10 */\r
+ byte SBR11 :1; /* SCI 1 baud rate Bit 11 */\r
+ byte SBR12 :1; /* SCI 1 baud rate Bit 12 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpSBR_8 :5;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+ } SCI1BDHSTR;\r
+ #define SCI1BDH _SCI1BD.Overlap_STR.SCI1BDHSTR.Byte\r
+ #define SCI1BDH_SBR8 _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.SBR8\r
+ #define SCI1BDH_SBR9 _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.SBR9\r
+ #define SCI1BDH_SBR10 _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.SBR10\r
+ #define SCI1BDH_SBR11 _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.SBR11\r
+ #define SCI1BDH_SBR12 _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.SBR12\r
+ #define SCI1BDH_SBR_8 _SCI1BD.Overlap_STR.SCI1BDHSTR.MergedBits.grpSBR_8\r
+ #define SCI1BDH_SBR SCI1BDH_SBR_8\r
+ \r
+ /*** SCI1BDL - SCI 1 Baud Rate Register Low; 0x000000D1 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte SBR0 :1; /* SCI 1 baud rate Bit 0 */\r
+ byte SBR1 :1; /* SCI 1 baud rate Bit 1 */\r
+ byte SBR2 :1; /* SCI 1 baud rate Bit 2 */\r
+ byte SBR3 :1; /* SCI 1 baud rate Bit 3 */\r
+ byte SBR4 :1; /* SCI 1 baud rate Bit 4 */\r
+ byte SBR5 :1; /* SCI 1 baud rate Bit 5 */\r
+ byte SBR6 :1; /* SCI 1 baud rate Bit 6 */\r
+ byte SBR7 :1; /* SCI 1 baud rate Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpSBR :8;\r
+ } MergedBits;\r
+ } SCI1BDLSTR;\r
+ #define SCI1BDL _SCI1BD.Overlap_STR.SCI1BDLSTR.Byte\r
+ #define SCI1BDL_SBR0 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR0\r
+ #define SCI1BDL_SBR1 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR1\r
+ #define SCI1BDL_SBR2 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR2\r
+ #define SCI1BDL_SBR3 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR3\r
+ #define SCI1BDL_SBR4 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR4\r
+ #define SCI1BDL_SBR5 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR5\r
+ #define SCI1BDL_SBR6 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR6\r
+ #define SCI1BDL_SBR7 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR7\r
+ #define SCI1BDL_SBR _SCI1BD.Overlap_STR.SCI1BDLSTR.MergedBits.grpSBR\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word SBR0 :1; /* SCI 1 baud rate Bit 0 */\r
+ word SBR1 :1; /* SCI 1 baud rate Bit 1 */\r
+ word SBR2 :1; /* SCI 1 baud rate Bit 2 */\r
+ word SBR3 :1; /* SCI 1 baud rate Bit 3 */\r
+ word SBR4 :1; /* SCI 1 baud rate Bit 4 */\r
+ word SBR5 :1; /* SCI 1 baud rate Bit 5 */\r
+ word SBR6 :1; /* SCI 1 baud rate Bit 6 */\r
+ word SBR7 :1; /* SCI 1 baud rate Bit 7 */\r
+ word SBR8 :1; /* SCI 1 baud rate Bit 8 */\r
+ word SBR9 :1; /* SCI 1 baud rate Bit 9 */\r
+ word SBR10 :1; /* SCI 1 baud rate Bit 10 */\r
+ word SBR11 :1; /* SCI 1 baud rate Bit 11 */\r
+ word SBR12 :1; /* SCI 1 baud rate Bit 12 */\r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ } Bits;\r
+ struct {\r
+ word grpSBR :13;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ } MergedBits;\r
+} SCI1BDSTR;\r
+extern volatile SCI1BDSTR _SCI1BD @(REG_BASE + 0x000000D0);\r
+#define SCI1BD _SCI1BD.Word\r
+#define SCI1BD_SBR0 _SCI1BD.Bits.SBR0\r
+#define SCI1BD_SBR1 _SCI1BD.Bits.SBR1\r
+#define SCI1BD_SBR2 _SCI1BD.Bits.SBR2\r
+#define SCI1BD_SBR3 _SCI1BD.Bits.SBR3\r
+#define SCI1BD_SBR4 _SCI1BD.Bits.SBR4\r
+#define SCI1BD_SBR5 _SCI1BD.Bits.SBR5\r
+#define SCI1BD_SBR6 _SCI1BD.Bits.SBR6\r
+#define SCI1BD_SBR7 _SCI1BD.Bits.SBR7\r
+#define SCI1BD_SBR8 _SCI1BD.Bits.SBR8\r
+#define SCI1BD_SBR9 _SCI1BD.Bits.SBR9\r
+#define SCI1BD_SBR10 _SCI1BD.Bits.SBR10\r
+#define SCI1BD_SBR11 _SCI1BD.Bits.SBR11\r
+#define SCI1BD_SBR12 _SCI1BD.Bits.SBR12\r
+#define SCI1BD_SBR _SCI1BD.MergedBits.grpSBR\r
+\r
+\r
+/*** ATD1CTL23 - ATD 1 Control Register 23; 0x00000122 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** ATD1CTL2 - ATD 1 Control Register 2; 0x00000122 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte ASCIF :1; /* ATD 1 Sequence Complete Interrupt Flag */\r
+ byte ASCIE :1; /* ATD 1 Sequence Complete Interrupt Enable */\r
+ byte ETRIGE :1; /* External Trigger Mode enable */\r
+ byte ETRIGP :1; /* External Trigger Polarity */\r
+ byte ETRIGLE :1; /* External Trigger Level/Edge control */\r
+ byte AWAI :1; /* ATD 1 Wait Mode */\r
+ byte AFFC :1; /* ATD 1 Fast Conversion Complete Flag Clear */\r
+ byte ADPU :1; /* ATD 1 Disable / Power Down */\r
+ } Bits;\r
+ } ATD1CTL2STR;\r
+ #define ATD1CTL2 _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Byte\r
+ #define ATD1CTL2_ASCIF _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.ASCIF\r
+ #define ATD1CTL2_ASCIE _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.ASCIE\r
+ #define ATD1CTL2_ETRIGE _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.ETRIGE\r
+ #define ATD1CTL2_ETRIGP _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.ETRIGP\r
+ #define ATD1CTL2_ETRIGLE _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.ETRIGLE\r
+ #define ATD1CTL2_AWAI _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.AWAI\r
+ #define ATD1CTL2_AFFC _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.AFFC\r
+ #define ATD1CTL2_ADPU _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.ADPU\r
+ \r
+ /*** ATD1CTL3 - ATD 1 Control Register 3; 0x00000123 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte FRZ0 :1; /* Background Debug Freeze Enable */\r
+ byte FRZ1 :1; /* Background Debug Freeze Enable */\r
+ byte FIFO :1; /* Result Register FIFO Mode */\r
+ byte S1C :1; /* Conversion Sequence Length 1 */\r
+ byte S2C :1; /* Conversion Sequence Length 2 */\r
+ byte S4C :1; /* Conversion Sequence Length 4 */\r
+ byte S8C :1; /* Conversion Sequence Length 8 */\r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpFRZ :2;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+ } ATD1CTL3STR;\r
+ #define ATD1CTL3 _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Byte\r
+ #define ATD1CTL3_FRZ0 _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.FRZ0\r
+ #define ATD1CTL3_FRZ1 _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.FRZ1\r
+ #define ATD1CTL3_FIFO _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.FIFO\r
+ #define ATD1CTL3_S1C _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.S1C\r
+ #define ATD1CTL3_S2C _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.S2C\r
+ #define ATD1CTL3_S4C _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.S4C\r
+ #define ATD1CTL3_S8C _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.S8C\r
+ #define ATD1CTL3_FRZ _ATD1CTL23.Overlap_STR.ATD1CTL3STR.MergedBits.grpFRZ\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word FRZ0 :1; /* Background Debug Freeze Enable */\r
+ word FRZ1 :1; /* Background Debug Freeze Enable */\r
+ word FIFO :1; /* Result Register FIFO Mode */\r
+ word S1C :1; /* Conversion Sequence Length 1 */\r
+ word S2C :1; /* Conversion Sequence Length 2 */\r
+ word S4C :1; /* Conversion Sequence Length 4 */\r
+ word S8C :1; /* Conversion Sequence Length 8 */\r
+ word :1; \r
+ word ASCIF :1; /* ATD 1 Sequence Complete Interrupt Flag */\r
+ word ASCIE :1; /* ATD 1 Sequence Complete Interrupt Enable */\r
+ word ETRIGE :1; /* External Trigger Mode enable */\r
+ word ETRIGP :1; /* External Trigger Polarity */\r
+ word ETRIGLE :1; /* External Trigger Level/Edge control */\r
+ word AWAI :1; /* ATD 1 Wait Mode */\r
+ word AFFC :1; /* ATD 1 Fast Conversion Complete Flag Clear */\r
+ word ADPU :1; /* ATD 1 Disable / Power Down */\r
+ } Bits;\r
+ struct {\r
+ word grpFRZ :2;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ } MergedBits;\r
+} ATD1CTL23STR;\r
+extern volatile ATD1CTL23STR _ATD1CTL23 @(REG_BASE + 0x00000122);\r
+#define ATD1CTL23 _ATD1CTL23.Word\r
+#define ATD1CTL23_FRZ0 _ATD1CTL23.Bits.FRZ0\r
+#define ATD1CTL23_FRZ1 _ATD1CTL23.Bits.FRZ1\r
+#define ATD1CTL23_FIFO _ATD1CTL23.Bits.FIFO\r
+#define ATD1CTL23_S1C _ATD1CTL23.Bits.S1C\r
+#define ATD1CTL23_S2C _ATD1CTL23.Bits.S2C\r
+#define ATD1CTL23_S4C _ATD1CTL23.Bits.S4C\r
+#define ATD1CTL23_S8C _ATD1CTL23.Bits.S8C\r
+#define ATD1CTL23_ASCIF _ATD1CTL23.Bits.ASCIF\r
+#define ATD1CTL23_ASCIE _ATD1CTL23.Bits.ASCIE\r
+#define ATD1CTL23_ETRIGE _ATD1CTL23.Bits.ETRIGE\r
+#define ATD1CTL23_ETRIGP _ATD1CTL23.Bits.ETRIGP\r
+#define ATD1CTL23_ETRIGLE _ATD1CTL23.Bits.ETRIGLE\r
+#define ATD1CTL23_AWAI _ATD1CTL23.Bits.AWAI\r
+#define ATD1CTL23_AFFC _ATD1CTL23.Bits.AFFC\r
+#define ATD1CTL23_ADPU _ATD1CTL23.Bits.ADPU\r
+#define ATD1CTL23_FRZ _ATD1CTL23.MergedBits.grpFRZ\r
+\r
+\r
+/*** ATD1CTL45 - ATD 1 Control Register 45; 0x00000124 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** ATD1CTL4 - ATD 1 Control Register 4; 0x00000124 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte PRS0 :1; /* ATD 1 Clock Prescaler 0 */\r
+ byte PRS1 :1; /* ATD 1 Clock Prescaler 1 */\r
+ byte PRS2 :1; /* ATD 1 Clock Prescaler 2 */\r
+ byte PRS3 :1; /* ATD 1 Clock Prescaler 3 */\r
+ byte PRS4 :1; /* ATD 1 Clock Prescaler 4 */\r
+ byte SMP0 :1; /* Sample Time Select 0 */\r
+ byte SMP1 :1; /* Sample Time Select 1 */\r
+ byte SRES8 :1; /* ATD 1 Resolution Select */\r
+ } Bits;\r
+ struct {\r
+ byte grpPRS :5;\r
+ byte grpSMP :2;\r
+ byte grpSRES_8 :1;\r
+ } MergedBits;\r
+ } ATD1CTL4STR;\r
+ #define ATD1CTL4 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Byte\r
+ #define ATD1CTL4_PRS0 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.PRS0\r
+ #define ATD1CTL4_PRS1 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.PRS1\r
+ #define ATD1CTL4_PRS2 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.PRS2\r
+ #define ATD1CTL4_PRS3 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.PRS3\r
+ #define ATD1CTL4_PRS4 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.PRS4\r
+ #define ATD1CTL4_SMP0 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.SMP0\r
+ #define ATD1CTL4_SMP1 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.SMP1\r
+ #define ATD1CTL4_SRES8 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.SRES8\r
+ #define ATD1CTL4_PRS _ATD1CTL45.Overlap_STR.ATD1CTL4STR.MergedBits.grpPRS\r
+ #define ATD1CTL4_SMP _ATD1CTL45.Overlap_STR.ATD1CTL4STR.MergedBits.grpSMP\r
+ \r
+ /*** ATD1CTL5 - ATD 1 Control Register 5; 0x00000125 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte CA :1; /* Analog Input Channel Select Code A */\r
+ byte CB :1; /* Analog Input Channel Select Code B */\r
+ byte CC :1; /* Analog Input Channel Select Code C */\r
+ byte :1; \r
+ byte MULT :1; /* Multi-Channel Sample Mode */\r
+ byte SCAN :1; /* Continuous Conversion Sequence Mode */\r
+ byte DSGN :1; /* Signed/Unsigned Result Data Mode */\r
+ byte DJM :1; /* Result Register Data Justification Mode */\r
+ } Bits;\r
+ } ATD1CTL5STR;\r
+ #define ATD1CTL5 _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Byte\r
+ #define ATD1CTL5_CA _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.CA\r
+ #define ATD1CTL5_CB _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.CB\r
+ #define ATD1CTL5_CC _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.CC\r
+ #define ATD1CTL5_MULT _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.MULT\r
+ #define ATD1CTL5_SCAN _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.SCAN\r
+ #define ATD1CTL5_DSGN _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.DSGN\r
+ #define ATD1CTL5_DJM _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.DJM\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word CA :1; /* Analog Input Channel Select Code A */\r
+ word CB :1; /* Analog Input Channel Select Code B */\r
+ word CC :1; /* Analog Input Channel Select Code C */\r
+ word :1; \r
+ word MULT :1; /* Multi-Channel Sample Mode */\r
+ word SCAN :1; /* Continuous Conversion Sequence Mode */\r
+ word DSGN :1; /* Signed/Unsigned Result Data Mode */\r
+ word DJM :1; /* Result Register Data Justification Mode */\r
+ word PRS0 :1; /* ATD 1 Clock Prescaler 0 */\r
+ word PRS1 :1; /* ATD 1 Clock Prescaler 1 */\r
+ word PRS2 :1; /* ATD 1 Clock Prescaler 2 */\r
+ word PRS3 :1; /* ATD 1 Clock Prescaler 3 */\r
+ word PRS4 :1; /* ATD 1 Clock Prescaler 4 */\r
+ word SMP0 :1; /* Sample Time Select 0 */\r
+ word SMP1 :1; /* Sample Time Select 1 */\r
+ word SRES8 :1; /* ATD 1 Resolution Select */\r
+ } Bits;\r
+ struct {\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word grpPRS :5;\r
+ word grpSMP :2;\r
+ word grpSRES_8 :1;\r
+ } MergedBits;\r
+} ATD1CTL45STR;\r
+extern volatile ATD1CTL45STR _ATD1CTL45 @(REG_BASE + 0x00000124);\r
+#define ATD1CTL45 _ATD1CTL45.Word\r
+#define ATD1CTL45_CA _ATD1CTL45.Bits.CA\r
+#define ATD1CTL45_CB _ATD1CTL45.Bits.CB\r
+#define ATD1CTL45_CC _ATD1CTL45.Bits.CC\r
+#define ATD1CTL45_MULT _ATD1CTL45.Bits.MULT\r
+#define ATD1CTL45_SCAN _ATD1CTL45.Bits.SCAN\r
+#define ATD1CTL45_DSGN _ATD1CTL45.Bits.DSGN\r
+#define ATD1CTL45_DJM _ATD1CTL45.Bits.DJM\r
+#define ATD1CTL45_PRS0 _ATD1CTL45.Bits.PRS0\r
+#define ATD1CTL45_PRS1 _ATD1CTL45.Bits.PRS1\r
+#define ATD1CTL45_PRS2 _ATD1CTL45.Bits.PRS2\r
+#define ATD1CTL45_PRS3 _ATD1CTL45.Bits.PRS3\r
+#define ATD1CTL45_PRS4 _ATD1CTL45.Bits.PRS4\r
+#define ATD1CTL45_SMP0 _ATD1CTL45.Bits.SMP0\r
+#define ATD1CTL45_SMP1 _ATD1CTL45.Bits.SMP1\r
+#define ATD1CTL45_SRES8 _ATD1CTL45.Bits.SRES8\r
+#define ATD1CTL45_PRS _ATD1CTL45.MergedBits.grpPRS\r
+#define ATD1CTL45_SMP _ATD1CTL45.MergedBits.grpSMP\r
+\r
+\r
+/*** ATD1DR0 - ATD 1 Conversion Result Register 0; 0x00000130 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** ATD1DR0H - ATD 1 Conversion Result Register 0 High; 0x00000130 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT8 :1; /* Bit 8 */\r
+ byte BIT9 :1; /* Bit 9 */\r
+ byte BIT10 :1; /* Bit 10 */\r
+ byte BIT11 :1; /* Bit 11 */\r
+ byte BIT12 :1; /* Bit 12 */\r
+ byte BIT13 :1; /* Bit 13 */\r
+ byte BIT14 :1; /* Bit 14 */\r
+ byte BIT15 :1; /* Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT_8 :8;\r
+ } MergedBits;\r
+ } ATD1DR0HSTR;\r
+ #define ATD1DR0H _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Byte\r
+ #define ATD1DR0H_BIT8 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT8\r
+ #define ATD1DR0H_BIT9 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT9\r
+ #define ATD1DR0H_BIT10 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT10\r
+ #define ATD1DR0H_BIT11 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT11\r
+ #define ATD1DR0H_BIT12 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT12\r
+ #define ATD1DR0H_BIT13 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT13\r
+ #define ATD1DR0H_BIT14 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT14\r
+ #define ATD1DR0H_BIT15 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT15\r
+ #define ATD1DR0H_BIT_8 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.MergedBits.grpBIT_8\r
+ #define ATD1DR0H_BIT ATD1DR0H_BIT_8\r
+ \r
+ /*** ATD1DR0L - ATD 1 Conversion Result Register 0 Low; 0x00000131 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte BIT6 :1; /* Bit 6 */\r
+ byte BIT7 :1; /* Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpBIT_6 :2;\r
+ } MergedBits;\r
+ } ATD1DR0LSTR;\r
+ #define ATD1DR0L _ATD1DR0.Overlap_STR.ATD1DR0LSTR.Byte\r
+ #define ATD1DR0L_BIT6 _ATD1DR0.Overlap_STR.ATD1DR0LSTR.Bits.BIT6\r
+ #define ATD1DR0L_BIT7 _ATD1DR0.Overlap_STR.ATD1DR0LSTR.Bits.BIT7\r
+ #define ATD1DR0L_BIT_6 _ATD1DR0.Overlap_STR.ATD1DR0LSTR.MergedBits.grpBIT_6\r
+ #define ATD1DR0L_BIT ATD1DR0L_BIT_6\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word BIT6 :1; /* Bit 6 */\r
+ word BIT7 :1; /* Bit 7 */\r
+ word BIT8 :1; /* Bit 8 */\r
+ word BIT9 :1; /* Bit 9 */\r
+ word BIT10 :1; /* Bit 10 */\r
+ word BIT11 :1; /* Bit 11 */\r
+ word BIT12 :1; /* Bit 12 */\r
+ word BIT13 :1; /* Bit 13 */\r
+ word BIT14 :1; /* Bit 14 */\r
+ word BIT15 :1; /* Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word grpBIT_6 :10;\r
+ } MergedBits;\r
+} ATD1DR0STR;\r
+extern volatile ATD1DR0STR _ATD1DR0 @(REG_BASE + 0x00000130);\r
+#define ATD1DR0 _ATD1DR0.Word\r
+#define ATD1DR0_BIT6 _ATD1DR0.Bits.BIT6\r
+#define ATD1DR0_BIT7 _ATD1DR0.Bits.BIT7\r
+#define ATD1DR0_BIT8 _ATD1DR0.Bits.BIT8\r
+#define ATD1DR0_BIT9 _ATD1DR0.Bits.BIT9\r
+#define ATD1DR0_BIT10 _ATD1DR0.Bits.BIT10\r
+#define ATD1DR0_BIT11 _ATD1DR0.Bits.BIT11\r
+#define ATD1DR0_BIT12 _ATD1DR0.Bits.BIT12\r
+#define ATD1DR0_BIT13 _ATD1DR0.Bits.BIT13\r
+#define ATD1DR0_BIT14 _ATD1DR0.Bits.BIT14\r
+#define ATD1DR0_BIT15 _ATD1DR0.Bits.BIT15\r
+#define ATD1DR0_BIT_6 _ATD1DR0.MergedBits.grpBIT_6\r
+#define ATD1DR0_BIT ATD1DR0_BIT_6\r
+\r
+\r
+/*** ATD1DR1 - ATD 1 Conversion Result Register 1; 0x00000132 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** ATD1DR1H - ATD 1 Conversion Result Register 1 High; 0x00000132 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT8 :1; /* Bit 8 */\r
+ byte BIT9 :1; /* Bit 9 */\r
+ byte BIT10 :1; /* Bit 10 */\r
+ byte BIT11 :1; /* Bit 11 */\r
+ byte BIT12 :1; /* Bit 12 */\r
+ byte BIT13 :1; /* Bit 13 */\r
+ byte BIT14 :1; /* Bit 14 */\r
+ byte BIT15 :1; /* Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT_8 :8;\r
+ } MergedBits;\r
+ } ATD1DR1HSTR;\r
+ #define ATD1DR1H _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Byte\r
+ #define ATD1DR1H_BIT8 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT8\r
+ #define ATD1DR1H_BIT9 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT9\r
+ #define ATD1DR1H_BIT10 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT10\r
+ #define ATD1DR1H_BIT11 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT11\r
+ #define ATD1DR1H_BIT12 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT12\r
+ #define ATD1DR1H_BIT13 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT13\r
+ #define ATD1DR1H_BIT14 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT14\r
+ #define ATD1DR1H_BIT15 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT15\r
+ #define ATD1DR1H_BIT_8 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.MergedBits.grpBIT_8\r
+ #define ATD1DR1H_BIT ATD1DR1H_BIT_8\r
+ \r
+ /*** ATD1DR1L - ATD 1 Conversion Result Register 1 Low; 0x00000133 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte BIT6 :1; /* Bit 6 */\r
+ byte BIT7 :1; /* Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpBIT_6 :2;\r
+ } MergedBits;\r
+ } ATD1DR1LSTR;\r
+ #define ATD1DR1L _ATD1DR1.Overlap_STR.ATD1DR1LSTR.Byte\r
+ #define ATD1DR1L_BIT6 _ATD1DR1.Overlap_STR.ATD1DR1LSTR.Bits.BIT6\r
+ #define ATD1DR1L_BIT7 _ATD1DR1.Overlap_STR.ATD1DR1LSTR.Bits.BIT7\r
+ #define ATD1DR1L_BIT_6 _ATD1DR1.Overlap_STR.ATD1DR1LSTR.MergedBits.grpBIT_6\r
+ #define ATD1DR1L_BIT ATD1DR1L_BIT_6\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word BIT6 :1; /* Bit 6 */\r
+ word BIT7 :1; /* Bit 7 */\r
+ word BIT8 :1; /* Bit 8 */\r
+ word BIT9 :1; /* Bit 9 */\r
+ word BIT10 :1; /* Bit 10 */\r
+ word BIT11 :1; /* Bit 11 */\r
+ word BIT12 :1; /* Bit 12 */\r
+ word BIT13 :1; /* Bit 13 */\r
+ word BIT14 :1; /* Bit 14 */\r
+ word BIT15 :1; /* Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word grpBIT_6 :10;\r
+ } MergedBits;\r
+} ATD1DR1STR;\r
+extern volatile ATD1DR1STR _ATD1DR1 @(REG_BASE + 0x00000132);\r
+#define ATD1DR1 _ATD1DR1.Word\r
+#define ATD1DR1_BIT6 _ATD1DR1.Bits.BIT6\r
+#define ATD1DR1_BIT7 _ATD1DR1.Bits.BIT7\r
+#define ATD1DR1_BIT8 _ATD1DR1.Bits.BIT8\r
+#define ATD1DR1_BIT9 _ATD1DR1.Bits.BIT9\r
+#define ATD1DR1_BIT10 _ATD1DR1.Bits.BIT10\r
+#define ATD1DR1_BIT11 _ATD1DR1.Bits.BIT11\r
+#define ATD1DR1_BIT12 _ATD1DR1.Bits.BIT12\r
+#define ATD1DR1_BIT13 _ATD1DR1.Bits.BIT13\r
+#define ATD1DR1_BIT14 _ATD1DR1.Bits.BIT14\r
+#define ATD1DR1_BIT15 _ATD1DR1.Bits.BIT15\r
+#define ATD1DR1_BIT_6 _ATD1DR1.MergedBits.grpBIT_6\r
+#define ATD1DR1_BIT ATD1DR1_BIT_6\r
+\r
+\r
+/*** ATD1DR2 - ATD 1 Conversion Result Register 2; 0x00000134 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** ATD1DR2H - ATD 1 Conversion Result Register 2 High; 0x00000134 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT8 :1; /* Bit 8 */\r
+ byte BIT9 :1; /* Bit 9 */\r
+ byte BIT10 :1; /* Bit 10 */\r
+ byte BIT11 :1; /* Bit 11 */\r
+ byte BIT12 :1; /* Bit 12 */\r
+ byte BIT13 :1; /* Bit 13 */\r
+ byte BIT14 :1; /* Bit 14 */\r
+ byte BIT15 :1; /* Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT_8 :8;\r
+ } MergedBits;\r
+ } ATD1DR2HSTR;\r
+ #define ATD1DR2H _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Byte\r
+ #define ATD1DR2H_BIT8 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT8\r
+ #define ATD1DR2H_BIT9 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT9\r
+ #define ATD1DR2H_BIT10 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT10\r
+ #define ATD1DR2H_BIT11 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT11\r
+ #define ATD1DR2H_BIT12 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT12\r
+ #define ATD1DR2H_BIT13 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT13\r
+ #define ATD1DR2H_BIT14 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT14\r
+ #define ATD1DR2H_BIT15 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT15\r
+ #define ATD1DR2H_BIT_8 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.MergedBits.grpBIT_8\r
+ #define ATD1DR2H_BIT ATD1DR2H_BIT_8\r
+ \r
+ /*** ATD1DR2L - ATD 1 Conversion Result Register 2 Low; 0x00000135 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte BIT6 :1; /* Bit 6 */\r
+ byte BIT7 :1; /* Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpBIT_6 :2;\r
+ } MergedBits;\r
+ } ATD1DR2LSTR;\r
+ #define ATD1DR2L _ATD1DR2.Overlap_STR.ATD1DR2LSTR.Byte\r
+ #define ATD1DR2L_BIT6 _ATD1DR2.Overlap_STR.ATD1DR2LSTR.Bits.BIT6\r
+ #define ATD1DR2L_BIT7 _ATD1DR2.Overlap_STR.ATD1DR2LSTR.Bits.BIT7\r
+ #define ATD1DR2L_BIT_6 _ATD1DR2.Overlap_STR.ATD1DR2LSTR.MergedBits.grpBIT_6\r
+ #define ATD1DR2L_BIT ATD1DR2L_BIT_6\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word BIT6 :1; /* Bit 6 */\r
+ word BIT7 :1; /* Bit 7 */\r
+ word BIT8 :1; /* Bit 8 */\r
+ word BIT9 :1; /* Bit 9 */\r
+ word BIT10 :1; /* Bit 10 */\r
+ word BIT11 :1; /* Bit 11 */\r
+ word BIT12 :1; /* Bit 12 */\r
+ word BIT13 :1; /* Bit 13 */\r
+ word BIT14 :1; /* Bit 14 */\r
+ word BIT15 :1; /* Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word grpBIT_6 :10;\r
+ } MergedBits;\r
+} ATD1DR2STR;\r
+extern volatile ATD1DR2STR _ATD1DR2 @(REG_BASE + 0x00000134);\r
+#define ATD1DR2 _ATD1DR2.Word\r
+#define ATD1DR2_BIT6 _ATD1DR2.Bits.BIT6\r
+#define ATD1DR2_BIT7 _ATD1DR2.Bits.BIT7\r
+#define ATD1DR2_BIT8 _ATD1DR2.Bits.BIT8\r
+#define ATD1DR2_BIT9 _ATD1DR2.Bits.BIT9\r
+#define ATD1DR2_BIT10 _ATD1DR2.Bits.BIT10\r
+#define ATD1DR2_BIT11 _ATD1DR2.Bits.BIT11\r
+#define ATD1DR2_BIT12 _ATD1DR2.Bits.BIT12\r
+#define ATD1DR2_BIT13 _ATD1DR2.Bits.BIT13\r
+#define ATD1DR2_BIT14 _ATD1DR2.Bits.BIT14\r
+#define ATD1DR2_BIT15 _ATD1DR2.Bits.BIT15\r
+#define ATD1DR2_BIT_6 _ATD1DR2.MergedBits.grpBIT_6\r
+#define ATD1DR2_BIT ATD1DR2_BIT_6\r
+\r
+\r
+/*** ATD1DR3 - ATD 1 Conversion Result Register 3; 0x00000136 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** ATD1DR3H - ATD 1 Conversion Result Register 3 High; 0x00000136 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT8 :1; /* Bit 8 */\r
+ byte BIT9 :1; /* Bit 9 */\r
+ byte BIT10 :1; /* Bit 10 */\r
+ byte BIT11 :1; /* Bit 11 */\r
+ byte BIT12 :1; /* Bit 12 */\r
+ byte BIT13 :1; /* Bit 13 */\r
+ byte BIT14 :1; /* Bit 14 */\r
+ byte BIT15 :1; /* Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT_8 :8;\r
+ } MergedBits;\r
+ } ATD1DR3HSTR;\r
+ #define ATD1DR3H _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Byte\r
+ #define ATD1DR3H_BIT8 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT8\r
+ #define ATD1DR3H_BIT9 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT9\r
+ #define ATD1DR3H_BIT10 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT10\r
+ #define ATD1DR3H_BIT11 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT11\r
+ #define ATD1DR3H_BIT12 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT12\r
+ #define ATD1DR3H_BIT13 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT13\r
+ #define ATD1DR3H_BIT14 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT14\r
+ #define ATD1DR3H_BIT15 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT15\r
+ #define ATD1DR3H_BIT_8 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.MergedBits.grpBIT_8\r
+ #define ATD1DR3H_BIT ATD1DR3H_BIT_8\r
+ \r
+ /*** ATD1DR3L - ATD 1 Conversion Result Register 3 Low; 0x00000137 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte BIT6 :1; /* Bit 6 */\r
+ byte BIT7 :1; /* Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpBIT_6 :2;\r
+ } MergedBits;\r
+ } ATD1DR3LSTR;\r
+ #define ATD1DR3L _ATD1DR3.Overlap_STR.ATD1DR3LSTR.Byte\r
+ #define ATD1DR3L_BIT6 _ATD1DR3.Overlap_STR.ATD1DR3LSTR.Bits.BIT6\r
+ #define ATD1DR3L_BIT7 _ATD1DR3.Overlap_STR.ATD1DR3LSTR.Bits.BIT7\r
+ #define ATD1DR3L_BIT_6 _ATD1DR3.Overlap_STR.ATD1DR3LSTR.MergedBits.grpBIT_6\r
+ #define ATD1DR3L_BIT ATD1DR3L_BIT_6\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word BIT6 :1; /* Bit 6 */\r
+ word BIT7 :1; /* Bit 7 */\r
+ word BIT8 :1; /* Bit 8 */\r
+ word BIT9 :1; /* Bit 9 */\r
+ word BIT10 :1; /* Bit 10 */\r
+ word BIT11 :1; /* Bit 11 */\r
+ word BIT12 :1; /* Bit 12 */\r
+ word BIT13 :1; /* Bit 13 */\r
+ word BIT14 :1; /* Bit 14 */\r
+ word BIT15 :1; /* Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word grpBIT_6 :10;\r
+ } MergedBits;\r
+} ATD1DR3STR;\r
+extern volatile ATD1DR3STR _ATD1DR3 @(REG_BASE + 0x00000136);\r
+#define ATD1DR3 _ATD1DR3.Word\r
+#define ATD1DR3_BIT6 _ATD1DR3.Bits.BIT6\r
+#define ATD1DR3_BIT7 _ATD1DR3.Bits.BIT7\r
+#define ATD1DR3_BIT8 _ATD1DR3.Bits.BIT8\r
+#define ATD1DR3_BIT9 _ATD1DR3.Bits.BIT9\r
+#define ATD1DR3_BIT10 _ATD1DR3.Bits.BIT10\r
+#define ATD1DR3_BIT11 _ATD1DR3.Bits.BIT11\r
+#define ATD1DR3_BIT12 _ATD1DR3.Bits.BIT12\r
+#define ATD1DR3_BIT13 _ATD1DR3.Bits.BIT13\r
+#define ATD1DR3_BIT14 _ATD1DR3.Bits.BIT14\r
+#define ATD1DR3_BIT15 _ATD1DR3.Bits.BIT15\r
+#define ATD1DR3_BIT_6 _ATD1DR3.MergedBits.grpBIT_6\r
+#define ATD1DR3_BIT ATD1DR3_BIT_6\r
+\r
+\r
+/*** ATD1DR4 - ATD 1 Conversion Result Register 4; 0x00000138 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** ATD1DR4H - ATD 1 Conversion Result Register 4 High; 0x00000138 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT8 :1; /* Bit 8 */\r
+ byte BIT9 :1; /* Bit 9 */\r
+ byte BIT10 :1; /* Bit 10 */\r
+ byte BIT11 :1; /* Bit 11 */\r
+ byte BIT12 :1; /* Bit 12 */\r
+ byte BIT13 :1; /* Bit 13 */\r
+ byte BIT14 :1; /* Bit 14 */\r
+ byte BIT15 :1; /* Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT_8 :8;\r
+ } MergedBits;\r
+ } ATD1DR4HSTR;\r
+ #define ATD1DR4H _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Byte\r
+ #define ATD1DR4H_BIT8 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT8\r
+ #define ATD1DR4H_BIT9 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT9\r
+ #define ATD1DR4H_BIT10 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT10\r
+ #define ATD1DR4H_BIT11 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT11\r
+ #define ATD1DR4H_BIT12 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT12\r
+ #define ATD1DR4H_BIT13 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT13\r
+ #define ATD1DR4H_BIT14 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT14\r
+ #define ATD1DR4H_BIT15 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT15\r
+ #define ATD1DR4H_BIT_8 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.MergedBits.grpBIT_8\r
+ #define ATD1DR4H_BIT ATD1DR4H_BIT_8\r
+ \r
+ /*** ATD1DR4L - ATD 1 Conversion Result Register 4 Low; 0x00000139 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte BIT6 :1; /* Bit 6 */\r
+ byte BIT7 :1; /* Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpBIT_6 :2;\r
+ } MergedBits;\r
+ } ATD1DR4LSTR;\r
+ #define ATD1DR4L _ATD1DR4.Overlap_STR.ATD1DR4LSTR.Byte\r
+ #define ATD1DR4L_BIT6 _ATD1DR4.Overlap_STR.ATD1DR4LSTR.Bits.BIT6\r
+ #define ATD1DR4L_BIT7 _ATD1DR4.Overlap_STR.ATD1DR4LSTR.Bits.BIT7\r
+ #define ATD1DR4L_BIT_6 _ATD1DR4.Overlap_STR.ATD1DR4LSTR.MergedBits.grpBIT_6\r
+ #define ATD1DR4L_BIT ATD1DR4L_BIT_6\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word BIT6 :1; /* Bit 6 */\r
+ word BIT7 :1; /* Bit 7 */\r
+ word BIT8 :1; /* Bit 8 */\r
+ word BIT9 :1; /* Bit 9 */\r
+ word BIT10 :1; /* Bit 10 */\r
+ word BIT11 :1; /* Bit 11 */\r
+ word BIT12 :1; /* Bit 12 */\r
+ word BIT13 :1; /* Bit 13 */\r
+ word BIT14 :1; /* Bit 14 */\r
+ word BIT15 :1; /* Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word grpBIT_6 :10;\r
+ } MergedBits;\r
+} ATD1DR4STR;\r
+extern volatile ATD1DR4STR _ATD1DR4 @(REG_BASE + 0x00000138);\r
+#define ATD1DR4 _ATD1DR4.Word\r
+#define ATD1DR4_BIT6 _ATD1DR4.Bits.BIT6\r
+#define ATD1DR4_BIT7 _ATD1DR4.Bits.BIT7\r
+#define ATD1DR4_BIT8 _ATD1DR4.Bits.BIT8\r
+#define ATD1DR4_BIT9 _ATD1DR4.Bits.BIT9\r
+#define ATD1DR4_BIT10 _ATD1DR4.Bits.BIT10\r
+#define ATD1DR4_BIT11 _ATD1DR4.Bits.BIT11\r
+#define ATD1DR4_BIT12 _ATD1DR4.Bits.BIT12\r
+#define ATD1DR4_BIT13 _ATD1DR4.Bits.BIT13\r
+#define ATD1DR4_BIT14 _ATD1DR4.Bits.BIT14\r
+#define ATD1DR4_BIT15 _ATD1DR4.Bits.BIT15\r
+#define ATD1DR4_BIT_6 _ATD1DR4.MergedBits.grpBIT_6\r
+#define ATD1DR4_BIT ATD1DR4_BIT_6\r
+\r
+\r
+/*** ATD1DR5 - ATD 1 Conversion Result Register 5; 0x0000013A ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** ATD1DR5H - ATD 1 Conversion Result Register 5 High; 0x0000013A ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT8 :1; /* Bit 8 */\r
+ byte BIT9 :1; /* Bit 9 */\r
+ byte BIT10 :1; /* Bit 10 */\r
+ byte BIT11 :1; /* Bit 11 */\r
+ byte BIT12 :1; /* Bit 12 */\r
+ byte BIT13 :1; /* Bit 13 */\r
+ byte BIT14 :1; /* Bit 14 */\r
+ byte BIT15 :1; /* Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT_8 :8;\r
+ } MergedBits;\r
+ } ATD1DR5HSTR;\r
+ #define ATD1DR5H _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Byte\r
+ #define ATD1DR5H_BIT8 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT8\r
+ #define ATD1DR5H_BIT9 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT9\r
+ #define ATD1DR5H_BIT10 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT10\r
+ #define ATD1DR5H_BIT11 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT11\r
+ #define ATD1DR5H_BIT12 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT12\r
+ #define ATD1DR5H_BIT13 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT13\r
+ #define ATD1DR5H_BIT14 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT14\r
+ #define ATD1DR5H_BIT15 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT15\r
+ #define ATD1DR5H_BIT_8 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.MergedBits.grpBIT_8\r
+ #define ATD1DR5H_BIT ATD1DR5H_BIT_8\r
+ \r
+ /*** ATD1DR5L - ATD 1 Conversion Result Register 5 Low; 0x0000013B ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte BIT6 :1; /* Bit 6 */\r
+ byte BIT7 :1; /* Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpBIT_6 :2;\r
+ } MergedBits;\r
+ } ATD1DR5LSTR;\r
+ #define ATD1DR5L _ATD1DR5.Overlap_STR.ATD1DR5LSTR.Byte\r
+ #define ATD1DR5L_BIT6 _ATD1DR5.Overlap_STR.ATD1DR5LSTR.Bits.BIT6\r
+ #define ATD1DR5L_BIT7 _ATD1DR5.Overlap_STR.ATD1DR5LSTR.Bits.BIT7\r
+ #define ATD1DR5L_BIT_6 _ATD1DR5.Overlap_STR.ATD1DR5LSTR.MergedBits.grpBIT_6\r
+ #define ATD1DR5L_BIT ATD1DR5L_BIT_6\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word BIT6 :1; /* Bit 6 */\r
+ word BIT7 :1; /* Bit 7 */\r
+ word BIT8 :1; /* Bit 8 */\r
+ word BIT9 :1; /* Bit 9 */\r
+ word BIT10 :1; /* Bit 10 */\r
+ word BIT11 :1; /* Bit 11 */\r
+ word BIT12 :1; /* Bit 12 */\r
+ word BIT13 :1; /* Bit 13 */\r
+ word BIT14 :1; /* Bit 14 */\r
+ word BIT15 :1; /* Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word grpBIT_6 :10;\r
+ } MergedBits;\r
+} ATD1DR5STR;\r
+extern volatile ATD1DR5STR _ATD1DR5 @(REG_BASE + 0x0000013A);\r
+#define ATD1DR5 _ATD1DR5.Word\r
+#define ATD1DR5_BIT6 _ATD1DR5.Bits.BIT6\r
+#define ATD1DR5_BIT7 _ATD1DR5.Bits.BIT7\r
+#define ATD1DR5_BIT8 _ATD1DR5.Bits.BIT8\r
+#define ATD1DR5_BIT9 _ATD1DR5.Bits.BIT9\r
+#define ATD1DR5_BIT10 _ATD1DR5.Bits.BIT10\r
+#define ATD1DR5_BIT11 _ATD1DR5.Bits.BIT11\r
+#define ATD1DR5_BIT12 _ATD1DR5.Bits.BIT12\r
+#define ATD1DR5_BIT13 _ATD1DR5.Bits.BIT13\r
+#define ATD1DR5_BIT14 _ATD1DR5.Bits.BIT14\r
+#define ATD1DR5_BIT15 _ATD1DR5.Bits.BIT15\r
+#define ATD1DR5_BIT_6 _ATD1DR5.MergedBits.grpBIT_6\r
+#define ATD1DR5_BIT ATD1DR5_BIT_6\r
+\r
+\r
+/*** ATD1DR6 - ATD 1 Conversion Result Register 6; 0x0000013C ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** ATD1DR6H - ATD 1 Conversion Result Register 6 High; 0x0000013C ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT8 :1; /* Bit 8 */\r
+ byte BIT9 :1; /* Bit 9 */\r
+ byte BIT10 :1; /* Bit 10 */\r
+ byte BIT11 :1; /* Bit 11 */\r
+ byte BIT12 :1; /* Bit 12 */\r
+ byte BIT13 :1; /* Bit 13 */\r
+ byte BIT14 :1; /* Bit 14 */\r
+ byte BIT15 :1; /* Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT_8 :8;\r
+ } MergedBits;\r
+ } ATD1DR6HSTR;\r
+ #define ATD1DR6H _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Byte\r
+ #define ATD1DR6H_BIT8 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT8\r
+ #define ATD1DR6H_BIT9 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT9\r
+ #define ATD1DR6H_BIT10 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT10\r
+ #define ATD1DR6H_BIT11 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT11\r
+ #define ATD1DR6H_BIT12 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT12\r
+ #define ATD1DR6H_BIT13 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT13\r
+ #define ATD1DR6H_BIT14 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT14\r
+ #define ATD1DR6H_BIT15 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT15\r
+ #define ATD1DR6H_BIT_8 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.MergedBits.grpBIT_8\r
+ #define ATD1DR6H_BIT ATD1DR6H_BIT_8\r
+ \r
+ /*** ATD1DR6L - ATD 1 Conversion Result Register 6 Low; 0x0000013D ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte BIT6 :1; /* Bit 6 */\r
+ byte BIT7 :1; /* Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpBIT_6 :2;\r
+ } MergedBits;\r
+ } ATD1DR6LSTR;\r
+ #define ATD1DR6L _ATD1DR6.Overlap_STR.ATD1DR6LSTR.Byte\r
+ #define ATD1DR6L_BIT6 _ATD1DR6.Overlap_STR.ATD1DR6LSTR.Bits.BIT6\r
+ #define ATD1DR6L_BIT7 _ATD1DR6.Overlap_STR.ATD1DR6LSTR.Bits.BIT7\r
+ #define ATD1DR6L_BIT_6 _ATD1DR6.Overlap_STR.ATD1DR6LSTR.MergedBits.grpBIT_6\r
+ #define ATD1DR6L_BIT ATD1DR6L_BIT_6\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word BIT6 :1; /* Bit 6 */\r
+ word BIT7 :1; /* Bit 7 */\r
+ word BIT8 :1; /* Bit 8 */\r
+ word BIT9 :1; /* Bit 9 */\r
+ word BIT10 :1; /* Bit 10 */\r
+ word BIT11 :1; /* Bit 11 */\r
+ word BIT12 :1; /* Bit 12 */\r
+ word BIT13 :1; /* Bit 13 */\r
+ word BIT14 :1; /* Bit 14 */\r
+ word BIT15 :1; /* Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word grpBIT_6 :10;\r
+ } MergedBits;\r
+} ATD1DR6STR;\r
+extern volatile ATD1DR6STR _ATD1DR6 @(REG_BASE + 0x0000013C);\r
+#define ATD1DR6 _ATD1DR6.Word\r
+#define ATD1DR6_BIT6 _ATD1DR6.Bits.BIT6\r
+#define ATD1DR6_BIT7 _ATD1DR6.Bits.BIT7\r
+#define ATD1DR6_BIT8 _ATD1DR6.Bits.BIT8\r
+#define ATD1DR6_BIT9 _ATD1DR6.Bits.BIT9\r
+#define ATD1DR6_BIT10 _ATD1DR6.Bits.BIT10\r
+#define ATD1DR6_BIT11 _ATD1DR6.Bits.BIT11\r
+#define ATD1DR6_BIT12 _ATD1DR6.Bits.BIT12\r
+#define ATD1DR6_BIT13 _ATD1DR6.Bits.BIT13\r
+#define ATD1DR6_BIT14 _ATD1DR6.Bits.BIT14\r
+#define ATD1DR6_BIT15 _ATD1DR6.Bits.BIT15\r
+#define ATD1DR6_BIT_6 _ATD1DR6.MergedBits.grpBIT_6\r
+#define ATD1DR6_BIT ATD1DR6_BIT_6\r
+\r
+\r
+/*** ATD1DR7 - ATD 1 Conversion Result Register 7; 0x0000013E ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** ATD1DR7H - ATD 1 Conversion Result Register 7 High; 0x0000013E ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT8 :1; /* Bit 8 */\r
+ byte BIT9 :1; /* Bit 9 */\r
+ byte BIT10 :1; /* Bit 10 */\r
+ byte BIT11 :1; /* Bit 11 */\r
+ byte BIT12 :1; /* Bit 12 */\r
+ byte BIT13 :1; /* Bit 13 */\r
+ byte BIT14 :1; /* Bit 14 */\r
+ byte BIT15 :1; /* Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT_8 :8;\r
+ } MergedBits;\r
+ } ATD1DR7HSTR;\r
+ #define ATD1DR7H _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Byte\r
+ #define ATD1DR7H_BIT8 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT8\r
+ #define ATD1DR7H_BIT9 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT9\r
+ #define ATD1DR7H_BIT10 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT10\r
+ #define ATD1DR7H_BIT11 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT11\r
+ #define ATD1DR7H_BIT12 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT12\r
+ #define ATD1DR7H_BIT13 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT13\r
+ #define ATD1DR7H_BIT14 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT14\r
+ #define ATD1DR7H_BIT15 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT15\r
+ #define ATD1DR7H_BIT_8 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.MergedBits.grpBIT_8\r
+ #define ATD1DR7H_BIT ATD1DR7H_BIT_8\r
+ \r
+ /*** ATD1DR7L - ATD 1 Conversion Result Register 7 Low; 0x0000013F ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte BIT6 :1; /* Bit 6 */\r
+ byte BIT7 :1; /* Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpBIT_6 :2;\r
+ } MergedBits;\r
+ } ATD1DR7LSTR;\r
+ #define ATD1DR7L _ATD1DR7.Overlap_STR.ATD1DR7LSTR.Byte\r
+ #define ATD1DR7L_BIT6 _ATD1DR7.Overlap_STR.ATD1DR7LSTR.Bits.BIT6\r
+ #define ATD1DR7L_BIT7 _ATD1DR7.Overlap_STR.ATD1DR7LSTR.Bits.BIT7\r
+ #define ATD1DR7L_BIT_6 _ATD1DR7.Overlap_STR.ATD1DR7LSTR.MergedBits.grpBIT_6\r
+ #define ATD1DR7L_BIT ATD1DR7L_BIT_6\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word BIT6 :1; /* Bit 6 */\r
+ word BIT7 :1; /* Bit 7 */\r
+ word BIT8 :1; /* Bit 8 */\r
+ word BIT9 :1; /* Bit 9 */\r
+ word BIT10 :1; /* Bit 10 */\r
+ word BIT11 :1; /* Bit 11 */\r
+ word BIT12 :1; /* Bit 12 */\r
+ word BIT13 :1; /* Bit 13 */\r
+ word BIT14 :1; /* Bit 14 */\r
+ word BIT15 :1; /* Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word grpBIT_6 :10;\r
+ } MergedBits;\r
+} ATD1DR7STR;\r
+extern volatile ATD1DR7STR _ATD1DR7 @(REG_BASE + 0x0000013E);\r
+#define ATD1DR7 _ATD1DR7.Word\r
+#define ATD1DR7_BIT6 _ATD1DR7.Bits.BIT6\r
+#define ATD1DR7_BIT7 _ATD1DR7.Bits.BIT7\r
+#define ATD1DR7_BIT8 _ATD1DR7.Bits.BIT8\r
+#define ATD1DR7_BIT9 _ATD1DR7.Bits.BIT9\r
+#define ATD1DR7_BIT10 _ATD1DR7.Bits.BIT10\r
+#define ATD1DR7_BIT11 _ATD1DR7.Bits.BIT11\r
+#define ATD1DR7_BIT12 _ATD1DR7.Bits.BIT12\r
+#define ATD1DR7_BIT13 _ATD1DR7.Bits.BIT13\r
+#define ATD1DR7_BIT14 _ATD1DR7.Bits.BIT14\r
+#define ATD1DR7_BIT15 _ATD1DR7.Bits.BIT15\r
+#define ATD1DR7_BIT_6 _ATD1DR7.MergedBits.grpBIT_6\r
+#define ATD1DR7_BIT ATD1DR7_BIT_6\r
+\r
+\r
+/*** PORTE - Port E Register; 0x00000008 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* Port E Bit 0, XIRQ */\r
+ byte BIT1 :1; /* Port E Bit 1, IRQ */\r
+ byte BIT2 :1; /* Port E Bit 2, R/W */\r
+ byte BIT3 :1; /* Port E Bit 3, LSTRB, TAGLO */\r
+ byte BIT4 :1; /* Port E Bit 4, ECLK */\r
+ byte BIT5 :1; /* Port E Bit 5, MODA, IPIPE0, RCRTO */\r
+ byte BIT6 :1; /* Port E Bit 6, MODB, IPIPE1, SCGTO */\r
+ byte BIT7 :1; /* Port E Bit 7, XCLKS, NOACC */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+} PORTESTR;\r
+extern volatile PORTESTR _PORTE @(REG_BASE + 0x00000008);\r
+#define PORTE _PORTE.Byte\r
+#define PORTE_BIT0 _PORTE.Bits.BIT0\r
+#define PORTE_BIT1 _PORTE.Bits.BIT1\r
+#define PORTE_BIT2 _PORTE.Bits.BIT2\r
+#define PORTE_BIT3 _PORTE.Bits.BIT3\r
+#define PORTE_BIT4 _PORTE.Bits.BIT4\r
+#define PORTE_BIT5 _PORTE.Bits.BIT5\r
+#define PORTE_BIT6 _PORTE.Bits.BIT6\r
+#define PORTE_BIT7 _PORTE.Bits.BIT7\r
+#define PORTE_BIT _PORTE.MergedBits.grpBIT\r
+\r
+\r
+/*** DDRE - Port E Data Direction Register; 0x00000009 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* Data Direction Port A Bit 0 */\r
+ byte BIT1 :1; /* Data Direction Port A Bit 1 */\r
+ byte BIT2 :1; /* Data Direction Port A Bit 2 */\r
+ byte BIT3 :1; /* Data Direction Port A Bit 3 */\r
+ byte BIT4 :1; /* Data Direction Port A Bit 4 */\r
+ byte BIT5 :1; /* Data Direction Port A Bit 5 */\r
+ byte BIT6 :1; /* Data Direction Port A Bit 6 */\r
+ byte BIT7 :1; /* Data Direction Port A Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+} DDRESTR;\r
+extern volatile DDRESTR _DDRE @(REG_BASE + 0x00000009);\r
+#define DDRE _DDRE.Byte\r
+#define DDRE_BIT0 _DDRE.Bits.BIT0\r
+#define DDRE_BIT1 _DDRE.Bits.BIT1\r
+#define DDRE_BIT2 _DDRE.Bits.BIT2\r
+#define DDRE_BIT3 _DDRE.Bits.BIT3\r
+#define DDRE_BIT4 _DDRE.Bits.BIT4\r
+#define DDRE_BIT5 _DDRE.Bits.BIT5\r
+#define DDRE_BIT6 _DDRE.Bits.BIT6\r
+#define DDRE_BIT7 _DDRE.Bits.BIT7\r
+#define DDRE_BIT _DDRE.MergedBits.grpBIT\r
+\r
+\r
+/*** PEAR - Port E Assignment Register; 0x0000000A ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte RDWE :1; /* Read / Write Enable */\r
+ byte LSTRE :1; /* Low Strobe (LSTRB) Enable */\r
+ byte NECLK :1; /* No External E Clock */\r
+ byte PIPOE :1; /* Pipe Status Signal Output Enable */\r
+ byte :1; \r
+ byte NOACCE :1; /* CPU No Access Output Enable */\r
+ } Bits;\r
+} PEARSTR;\r
+extern volatile PEARSTR _PEAR @(REG_BASE + 0x0000000A);\r
+#define PEAR _PEAR.Byte\r
+#define PEAR_RDWE _PEAR.Bits.RDWE\r
+#define PEAR_LSTRE _PEAR.Bits.LSTRE\r
+#define PEAR_NECLK _PEAR.Bits.NECLK\r
+#define PEAR_PIPOE _PEAR.Bits.PIPOE\r
+#define PEAR_NOACCE _PEAR.Bits.NOACCE\r
+\r
+\r
+/*** MODE - Mode Register; 0x0000000B ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte EME :1; /* Emulate Port E */\r
+ byte EMK :1; /* Emulate Port K */\r
+ byte :1; \r
+ byte IVIS :1; /* Internal Visibility */\r
+ byte :1; \r
+ byte MODA :1; /* Mode Select Bit A */\r
+ byte MODB :1; /* Mode Select Bit B */\r
+ byte MODC :1; /* Mode Select Bit C */\r
+ } Bits;\r
+} MODESTR;\r
+extern volatile MODESTR _MODE @(REG_BASE + 0x0000000B);\r
+#define MODE _MODE.Byte\r
+#define MODE_EME _MODE.Bits.EME\r
+#define MODE_EMK _MODE.Bits.EMK\r
+#define MODE_IVIS _MODE.Bits.IVIS\r
+#define MODE_MODA _MODE.Bits.MODA\r
+#define MODE_MODB _MODE.Bits.MODB\r
+#define MODE_MODC _MODE.Bits.MODC\r
+\r
+\r
+/*** PUCR - Pull-Up Control Register; 0x0000000C ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PUPAE :1; /* Pull-Up Port A Enable */\r
+ byte PUPBE :1; /* Pull-Up Port B Enable */\r
+ byte :1; \r
+ byte :1; \r
+ byte PUPEE :1; /* Pull-Up Port E Enable */\r
+ byte :1; \r
+ byte :1; \r
+ byte PUPKE :1; /* Pull-Up Port K Enable */\r
+ } Bits;\r
+} PUCRSTR;\r
+extern volatile PUCRSTR _PUCR @(REG_BASE + 0x0000000C);\r
+#define PUCR _PUCR.Byte\r
+#define PUCR_PUPAE _PUCR.Bits.PUPAE\r
+#define PUCR_PUPBE _PUCR.Bits.PUPBE\r
+#define PUCR_PUPEE _PUCR.Bits.PUPEE\r
+#define PUCR_PUPKE _PUCR.Bits.PUPKE\r
+\r
+\r
+/*** RDRIV - Reduced Drive of I/O Lines; 0x0000000D ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte RDPA :1; /* Reduced Drive of Port A */\r
+ byte RDPB :1; /* Reduced Drive of Port B */\r
+ byte :1; \r
+ byte :1; \r
+ byte RDPE :1; /* Reduced Drive of Port E */\r
+ byte :1; \r
+ byte :1; \r
+ byte RDPK :1; /* Reduced Drive of Port K */\r
+ } Bits;\r
+} RDRIVSTR;\r
+extern volatile RDRIVSTR _RDRIV @(REG_BASE + 0x0000000D);\r
+#define RDRIV _RDRIV.Byte\r
+#define RDRIV_RDPA _RDRIV.Bits.RDPA\r
+#define RDRIV_RDPB _RDRIV.Bits.RDPB\r
+#define RDRIV_RDPE _RDRIV.Bits.RDPE\r
+#define RDRIV_RDPK _RDRIV.Bits.RDPK\r
+\r
+\r
+/*** EBICTL - External Bus Interface Control; 0x0000000E ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ESTR :1; /* E Stretches */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+} EBICTLSTR;\r
+extern volatile EBICTLSTR _EBICTL @(REG_BASE + 0x0000000E);\r
+#define EBICTL _EBICTL.Byte\r
+#define EBICTL_ESTR _EBICTL.Bits.ESTR\r
+\r
+\r
+/*** INITRM - Initialization of Internal RAM Position Register; 0x00000010 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte RAMHAL :1; /* Internal RAM map alignment */\r
+ byte :1; \r
+ byte :1; \r
+ byte RAM11 :1; /* Internal RAM map position Bit 11 */\r
+ byte RAM12 :1; /* Internal RAM map position Bit 12 */\r
+ byte RAM13 :1; /* Internal RAM map position Bit 13 */\r
+ byte RAM14 :1; /* Internal RAM map position Bit 14 */\r
+ byte RAM15 :1; /* Internal RAM map position Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpRAM_11 :5;\r
+ } MergedBits;\r
+} INITRMSTR;\r
+extern volatile INITRMSTR _INITRM @(REG_BASE + 0x00000010);\r
+#define INITRM _INITRM.Byte\r
+#define INITRM_RAMHAL _INITRM.Bits.RAMHAL\r
+#define INITRM_RAM11 _INITRM.Bits.RAM11\r
+#define INITRM_RAM12 _INITRM.Bits.RAM12\r
+#define INITRM_RAM13 _INITRM.Bits.RAM13\r
+#define INITRM_RAM14 _INITRM.Bits.RAM14\r
+#define INITRM_RAM15 _INITRM.Bits.RAM15\r
+#define INITRM_RAM_11 _INITRM.MergedBits.grpRAM_11\r
+#define INITRM_RAM INITRM_RAM_11\r
+\r
+\r
+/*** INITRG - Initialization of Internal Register Position Register; 0x00000011 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte REG11 :1; /* Internal register map position REG11 */\r
+ byte REG12 :1; /* Internal register map position REG12 */\r
+ byte REG13 :1; /* Internal register map position REG13 */\r
+ byte REG14 :1; /* Internal register map position REG14 */\r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpREG_11 :4;\r
+ byte :1;\r
+ } MergedBits;\r
+} INITRGSTR;\r
+extern volatile INITRGSTR _INITRG @(REG_BASE + 0x00000011);\r
+#define INITRG _INITRG.Byte\r
+#define INITRG_REG11 _INITRG.Bits.REG11\r
+#define INITRG_REG12 _INITRG.Bits.REG12\r
+#define INITRG_REG13 _INITRG.Bits.REG13\r
+#define INITRG_REG14 _INITRG.Bits.REG14\r
+#define INITRG_REG_11 _INITRG.MergedBits.grpREG_11\r
+#define INITRG_REG INITRG_REG_11\r
+\r
+\r
+/*** INITEE - Initialization of Internal EEPROM Position Register; 0x00000012 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte EEON :1; /* Internal EEPROM On */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte EE12 :1; /* Internal EEPROM map position Bit 12 */\r
+ byte EE13 :1; /* Internal EEPROM map position Bit 13 */\r
+ byte EE14 :1; /* Internal EEPROM map position Bit 14 */\r
+ byte EE15 :1; /* Internal EEPROM map position Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpEE_12 :4;\r
+ } MergedBits;\r
+} INITEESTR;\r
+extern volatile INITEESTR _INITEE @(REG_BASE + 0x00000012);\r
+#define INITEE _INITEE.Byte\r
+#define INITEE_EEON _INITEE.Bits.EEON\r
+#define INITEE_EE12 _INITEE.Bits.EE12\r
+#define INITEE_EE13 _INITEE.Bits.EE13\r
+#define INITEE_EE14 _INITEE.Bits.EE14\r
+#define INITEE_EE15 _INITEE.Bits.EE15\r
+#define INITEE_EE_12 _INITEE.MergedBits.grpEE_12\r
+#define INITEE_EE INITEE_EE_12\r
+\r
+\r
+/*** MISC - Miscellaneous Mapping Control Register; 0x00000013 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ROMON :1; /* Enable Flash EEPROM */\r
+ byte ROMHM :1; /* Flash EEPROM only in second half of memory map */\r
+ byte EXSTR0 :1; /* External Access Stretch Bit 0 */\r
+ byte EXSTR1 :1; /* External Access Stretch Bit 1 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte grpEXSTR :2;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} MISCSTR;\r
+extern volatile MISCSTR _MISC @(REG_BASE + 0x00000013);\r
+#define MISC _MISC.Byte\r
+#define MISC_ROMON _MISC.Bits.ROMON\r
+#define MISC_ROMHM _MISC.Bits.ROMHM\r
+#define MISC_EXSTR0 _MISC.Bits.EXSTR0\r
+#define MISC_EXSTR1 _MISC.Bits.EXSTR1\r
+#define MISC_EXSTR _MISC.MergedBits.grpEXSTR\r
+\r
+\r
+/*** MTST0 - MTST0; 0x00000014 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* MTST0 Bit 0 */\r
+ byte BIT1 :1; /* MTST0 Bit 1 */\r
+ byte BIT2 :1; /* MTST0 Bit 2 */\r
+ byte BIT3 :1; /* MTST0 Bit 3 */\r
+ byte BIT4 :1; /* MTST0 Bit 4 */\r
+ byte BIT5 :1; /* MTST0 Bit 5 */\r
+ byte BIT6 :1; /* MTST0 Bit 6 */\r
+ byte BIT7 :1; /* MTST0 Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+} MTST0STR;\r
+extern volatile MTST0STR _MTST0 @(REG_BASE + 0x00000014);\r
+#define MTST0 _MTST0.Byte\r
+#define MTST0_BIT0 _MTST0.Bits.BIT0\r
+#define MTST0_BIT1 _MTST0.Bits.BIT1\r
+#define MTST0_BIT2 _MTST0.Bits.BIT2\r
+#define MTST0_BIT3 _MTST0.Bits.BIT3\r
+#define MTST0_BIT4 _MTST0.Bits.BIT4\r
+#define MTST0_BIT5 _MTST0.Bits.BIT5\r
+#define MTST0_BIT6 _MTST0.Bits.BIT6\r
+#define MTST0_BIT7 _MTST0.Bits.BIT7\r
+#define MTST0_BIT _MTST0.MergedBits.grpBIT\r
+\r
+\r
+/*** ITCR - Interrupt Test Control Register; 0x00000015 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ADR0 :1; /* Test register select Bit 0 */\r
+ byte ADR1 :1; /* Test register select Bit 1 */\r
+ byte ADR2 :1; /* Test register select Bit 2 */\r
+ byte ADR3 :1; /* Test register select Bit 3 */\r
+ byte WRTINT :1; /* Write to the Interrupt Test Registers */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpADR :4;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} ITCRSTR;\r
+extern volatile ITCRSTR _ITCR @(REG_BASE + 0x00000015);\r
+#define ITCR _ITCR.Byte\r
+#define ITCR_ADR0 _ITCR.Bits.ADR0\r
+#define ITCR_ADR1 _ITCR.Bits.ADR1\r
+#define ITCR_ADR2 _ITCR.Bits.ADR2\r
+#define ITCR_ADR3 _ITCR.Bits.ADR3\r
+#define ITCR_WRTINT _ITCR.Bits.WRTINT\r
+#define ITCR_ADR _ITCR.MergedBits.grpADR\r
+\r
+\r
+/*** ITEST - Interrupt Test Register; 0x00000016 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte INT0 :1; /* Interrupt Test Register Bit 0 */\r
+ byte INT2 :1; /* Interrupt Test Register Bit 1 */\r
+ byte INT4 :1; /* Interrupt Test Register Bit 2 */\r
+ byte INT6 :1; /* Interrupt Test Register Bit 3 */\r
+ byte INT8 :1; /* Interrupt Test Register Bit 4 */\r
+ byte INTA :1; /* Interrupt Test Register Bit 5 */\r
+ byte INTC :1; /* Interrupt Test Register Bit 6 */\r
+ byte INTE :1; /* Interrupt Test Register Bit 7 */\r
+ } Bits;\r
+} ITESTSTR;\r
+extern volatile ITESTSTR _ITEST @(REG_BASE + 0x00000016);\r
+#define ITEST _ITEST.Byte\r
+#define ITEST_INT0 _ITEST.Bits.INT0\r
+#define ITEST_INT2 _ITEST.Bits.INT2\r
+#define ITEST_INT4 _ITEST.Bits.INT4\r
+#define ITEST_INT6 _ITEST.Bits.INT6\r
+#define ITEST_INT8 _ITEST.Bits.INT8\r
+#define ITEST_INTA _ITEST.Bits.INTA\r
+#define ITEST_INTC _ITEST.Bits.INTC\r
+#define ITEST_INTE _ITEST.Bits.INTE\r
+\r
+\r
+/*** MTST1 - MTST1; 0x00000017 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* MTST1 Bit 0 */\r
+ byte BIT1 :1; /* MTST1 Bit 1 */\r
+ byte BIT2 :1; /* MTST1 Bit 2 */\r
+ byte BIT3 :1; /* MTST1 Bit 3 */\r
+ byte BIT4 :1; /* MTST1 Bit 4 */\r
+ byte BIT5 :1; /* MTST1 Bit 5 */\r
+ byte BIT6 :1; /* MTST1 Bit 6 */\r
+ byte BIT7 :1; /* MTST1 Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+} MTST1STR;\r
+extern volatile MTST1STR _MTST1 @(REG_BASE + 0x00000017);\r
+#define MTST1 _MTST1.Byte\r
+#define MTST1_BIT0 _MTST1.Bits.BIT0\r
+#define MTST1_BIT1 _MTST1.Bits.BIT1\r
+#define MTST1_BIT2 _MTST1.Bits.BIT2\r
+#define MTST1_BIT3 _MTST1.Bits.BIT3\r
+#define MTST1_BIT4 _MTST1.Bits.BIT4\r
+#define MTST1_BIT5 _MTST1.Bits.BIT5\r
+#define MTST1_BIT6 _MTST1.Bits.BIT6\r
+#define MTST1_BIT7 _MTST1.Bits.BIT7\r
+#define MTST1_BIT _MTST1.MergedBits.grpBIT\r
+\r
+\r
+/*** PARTIDH - Part ID Register High; 0x0000001A ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ID15 :1; /* Part ID Register Bit 15 */\r
+ byte ID14 :1; /* Part ID Register Bit 14 */\r
+ byte ID13 :1; /* Part ID Register Bit 13 */\r
+ byte ID12 :1; /* Part ID Register Bit 12 */\r
+ byte ID11 :1; /* Part ID Register Bit 11 */\r
+ byte ID10 :1; /* Part ID Register Bit 10 */\r
+ byte ID9 :1; /* Part ID Register Bit 9 */\r
+ byte ID8 :1; /* Part ID Register Bit 8 */\r
+ } Bits;\r
+} PARTIDHSTR;\r
+extern volatile PARTIDHSTR _PARTIDH @(REG_BASE + 0x0000001A);\r
+#define PARTIDH _PARTIDH.Byte\r
+#define PARTIDH_ID15 _PARTIDH.Bits.ID15\r
+#define PARTIDH_ID14 _PARTIDH.Bits.ID14\r
+#define PARTIDH_ID13 _PARTIDH.Bits.ID13\r
+#define PARTIDH_ID12 _PARTIDH.Bits.ID12\r
+#define PARTIDH_ID11 _PARTIDH.Bits.ID11\r
+#define PARTIDH_ID10 _PARTIDH.Bits.ID10\r
+#define PARTIDH_ID9 _PARTIDH.Bits.ID9\r
+#define PARTIDH_ID8 _PARTIDH.Bits.ID8\r
+\r
+\r
+/*** PARTIDL - Part ID Register Low; 0x0000001B ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ID0 :1; /* Part ID Register Bit 0 */\r
+ byte ID1 :1; /* Part ID Register Bit 1 */\r
+ byte ID2 :1; /* Part ID Register Bit 2 */\r
+ byte ID3 :1; /* Part ID Register Bit 3 */\r
+ byte ID4 :1; /* Part ID Register Bit 4 */\r
+ byte ID5 :1; /* Part ID Register Bit 5 */\r
+ byte ID6 :1; /* Part ID Register Bit 6 */\r
+ byte ID7 :1; /* Part ID Register Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpID :8;\r
+ } MergedBits;\r
+} PARTIDLSTR;\r
+extern volatile PARTIDLSTR _PARTIDL @(REG_BASE + 0x0000001B);\r
+#define PARTIDL _PARTIDL.Byte\r
+#define PARTIDL_ID0 _PARTIDL.Bits.ID0\r
+#define PARTIDL_ID1 _PARTIDL.Bits.ID1\r
+#define PARTIDL_ID2 _PARTIDL.Bits.ID2\r
+#define PARTIDL_ID3 _PARTIDL.Bits.ID3\r
+#define PARTIDL_ID4 _PARTIDL.Bits.ID4\r
+#define PARTIDL_ID5 _PARTIDL.Bits.ID5\r
+#define PARTIDL_ID6 _PARTIDL.Bits.ID6\r
+#define PARTIDL_ID7 _PARTIDL.Bits.ID7\r
+#define PARTIDL_ID _PARTIDL.MergedBits.grpID\r
+\r
+\r
+/*** MEMSIZ0 - Memory Size Register Zero; 0x0000001C ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ram_sw0 :1; /* Allocated RAM Memory Space Bit 0 */\r
+ byte ram_sw1 :1; /* Allocated RAM Memory Space Bit 1 */\r
+ byte ram_sw2 :1; /* Allocated RAM Memory Space Bit 2 */\r
+ byte :1; \r
+ byte eep_sw0 :1; /* Allocated EEPROM Memory Space Bit 0 */\r
+ byte eep_sw1 :1; /* Allocated EEPROM Memory Space Bit 1 */\r
+ byte :1; \r
+ byte reg_sw0 :1; /* Allocated System Register Space */\r
+ } Bits;\r
+ struct {\r
+ byte grpram_sw :3;\r
+ byte :1;\r
+ byte grpeep_sw :2;\r
+ byte :1;\r
+ byte grpreg_sw :1;\r
+ } MergedBits;\r
+} MEMSIZ0STR;\r
+extern volatile MEMSIZ0STR _MEMSIZ0 @(REG_BASE + 0x0000001C);\r
+#define MEMSIZ0 _MEMSIZ0.Byte\r
+#define MEMSIZ0_ram_sw0 _MEMSIZ0.Bits.ram_sw0\r
+#define MEMSIZ0_ram_sw1 _MEMSIZ0.Bits.ram_sw1\r
+#define MEMSIZ0_ram_sw2 _MEMSIZ0.Bits.ram_sw2\r
+#define MEMSIZ0_eep_sw0 _MEMSIZ0.Bits.eep_sw0\r
+#define MEMSIZ0_eep_sw1 _MEMSIZ0.Bits.eep_sw1\r
+#define MEMSIZ0_reg_sw0 _MEMSIZ0.Bits.reg_sw0\r
+#define MEMSIZ0_ram_sw _MEMSIZ0.MergedBits.grpram_sw\r
+#define MEMSIZ0_eep_sw _MEMSIZ0.MergedBits.grpeep_sw\r
+\r
+\r
+/*** MEMSIZ1 - Memory Size Register One; 0x0000001D ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte pag_sw0 :1; /* Allocated Off-Chip Memory Options Bit 0 */\r
+ byte pag_sw1 :1; /* Allocated Off-Chip Memory Options Bit 1 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte rom_sw0 :1; /* Allocated Flash EEPROM/ROM Physical Memory Space Bit 0 */\r
+ byte rom_sw1 :1; /* Allocated Flash EEPROM/ROM Physical Memory Space Bit 1 */\r
+ } Bits;\r
+ struct {\r
+ byte grppag_sw :2;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte grprom_sw :2;\r
+ } MergedBits;\r
+} MEMSIZ1STR;\r
+extern volatile MEMSIZ1STR _MEMSIZ1 @(REG_BASE + 0x0000001D);\r
+#define MEMSIZ1 _MEMSIZ1.Byte\r
+#define MEMSIZ1_pag_sw0 _MEMSIZ1.Bits.pag_sw0\r
+#define MEMSIZ1_pag_sw1 _MEMSIZ1.Bits.pag_sw1\r
+#define MEMSIZ1_rom_sw0 _MEMSIZ1.Bits.rom_sw0\r
+#define MEMSIZ1_rom_sw1 _MEMSIZ1.Bits.rom_sw1\r
+#define MEMSIZ1_pag_sw _MEMSIZ1.MergedBits.grppag_sw\r
+#define MEMSIZ1_rom_sw _MEMSIZ1.MergedBits.grprom_sw\r
+\r
+\r
+/*** INTCR - Interrupt Control Register; 0x0000001E ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte IRQEN :1; /* External IRQ Enable */\r
+ byte IRQE :1; /* IRQ Select Edge Sensitive Only */\r
+ } Bits;\r
+} INTCRSTR;\r
+extern volatile INTCRSTR _INTCR @(REG_BASE + 0x0000001E);\r
+#define INTCR _INTCR.Byte\r
+#define INTCR_IRQEN _INTCR.Bits.IRQEN\r
+#define INTCR_IRQE _INTCR.Bits.IRQE\r
+\r
+\r
+/*** HPRIO - Highest Priority I Interrupt; 0x0000001F ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte PSEL1 :1; /* Highest Priority I Interrupt Bit 1 */\r
+ byte PSEL2 :1; /* Highest Priority I Interrupt Bit 2 */\r
+ byte PSEL3 :1; /* Highest Priority I Interrupt Bit 3 */\r
+ byte PSEL4 :1; /* Highest Priority I Interrupt Bit 4 */\r
+ byte PSEL5 :1; /* Highest Priority I Interrupt Bit 5 */\r
+ byte PSEL6 :1; /* Highest Priority I Interrupt Bit 6 */\r
+ byte PSEL7 :1; /* Highest Priority I Interrupt Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte grpPSEL_1 :7;\r
+ } MergedBits;\r
+} HPRIOSTR;\r
+extern volatile HPRIOSTR _HPRIO @(REG_BASE + 0x0000001F);\r
+#define HPRIO _HPRIO.Byte\r
+#define HPRIO_PSEL1 _HPRIO.Bits.PSEL1\r
+#define HPRIO_PSEL2 _HPRIO.Bits.PSEL2\r
+#define HPRIO_PSEL3 _HPRIO.Bits.PSEL3\r
+#define HPRIO_PSEL4 _HPRIO.Bits.PSEL4\r
+#define HPRIO_PSEL5 _HPRIO.Bits.PSEL5\r
+#define HPRIO_PSEL6 _HPRIO.Bits.PSEL6\r
+#define HPRIO_PSEL7 _HPRIO.Bits.PSEL7\r
+#define HPRIO_PSEL_1 _HPRIO.MergedBits.grpPSEL_1\r
+#define HPRIO_PSEL HPRIO_PSEL_1\r
+\r
+\r
+/*** BKPCT0 - Breakpoint Control Register 0; 0x00000028 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte BKTAG :1; /* Breakpoint on Tag */\r
+ byte BKBDM :1; /* Breakpoint Background Debug Mode Enable */\r
+ byte BKFULL :1; /* Full Breakpoint Mode Enable */\r
+ byte BKEN :1; /* Breakpoint Enable */\r
+ } Bits;\r
+} BKPCT0STR;\r
+extern volatile BKPCT0STR _BKPCT0 @(REG_BASE + 0x00000028);\r
+#define BKPCT0 _BKPCT0.Byte\r
+#define BKPCT0_BKTAG _BKPCT0.Bits.BKTAG\r
+#define BKPCT0_BKBDM _BKPCT0.Bits.BKBDM\r
+#define BKPCT0_BKFULL _BKPCT0.Bits.BKFULL\r
+#define BKPCT0_BKEN _BKPCT0.Bits.BKEN\r
+\r
+\r
+/*** BKPCT1 - Breakpoint Control Register 1; 0x00000029 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte BK1RW :1; /* R/W Compare Value 1 */\r
+ byte BK1RWE :1; /* R/W Compare Enable 1 */\r
+ byte BK0RW :1; /* R/W Compare Value 0 */\r
+ byte BK0RWE :1; /* R/W Compare Enable 0 */\r
+ byte BK1MBL :1; /* Breakpoint Mask Low Byte for Second Address */\r
+ byte BK1MBH :1; /* Breakpoint Mask High Byte for Second Address */\r
+ byte BK0MBL :1; /* Breakpoint Mask Low Byte for First Address */\r
+ byte BK0MBH :1; /* Breakpoint Mask High Byte for First Address */\r
+ } Bits;\r
+} BKPCT1STR;\r
+extern volatile BKPCT1STR _BKPCT1 @(REG_BASE + 0x00000029);\r
+#define BKPCT1 _BKPCT1.Byte\r
+#define BKPCT1_BK1RW _BKPCT1.Bits.BK1RW\r
+#define BKPCT1_BK1RWE _BKPCT1.Bits.BK1RWE\r
+#define BKPCT1_BK0RW _BKPCT1.Bits.BK0RW\r
+#define BKPCT1_BK0RWE _BKPCT1.Bits.BK0RWE\r
+#define BKPCT1_BK1MBL _BKPCT1.Bits.BK1MBL\r
+#define BKPCT1_BK1MBH _BKPCT1.Bits.BK1MBH\r
+#define BKPCT1_BK0MBL _BKPCT1.Bits.BK0MBL\r
+#define BKPCT1_BK0MBH _BKPCT1.Bits.BK0MBH\r
+\r
+\r
+/*** BKP0X - First Address Memory Expansion Breakpoint Register; 0x0000002A ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte BK0V0 :1; /* First Address Breakpoint Expansion Address Value Bit 0 */\r
+ byte BK0V1 :1; /* First Address Breakpoint Expansion Address Value Bit 1 */\r
+ byte BK0V2 :1; /* First Address Breakpoint Expansion Address Value Bit 2 */\r
+ byte BK0V3 :1; /* First Address Breakpoint Expansion Address Value Bit 3 */\r
+ byte BK0V4 :1; /* First Address Breakpoint Expansion Address Value Bit 4 */\r
+ byte BK0V5 :1; /* First Address Breakpoint Expansion Address Value Bit 5 */\r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpBK0V :6;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} BKP0XSTR;\r
+extern volatile BKP0XSTR _BKP0X @(REG_BASE + 0x0000002A);\r
+#define BKP0X _BKP0X.Byte\r
+#define BKP0X_BK0V0 _BKP0X.Bits.BK0V0\r
+#define BKP0X_BK0V1 _BKP0X.Bits.BK0V1\r
+#define BKP0X_BK0V2 _BKP0X.Bits.BK0V2\r
+#define BKP0X_BK0V3 _BKP0X.Bits.BK0V3\r
+#define BKP0X_BK0V4 _BKP0X.Bits.BK0V4\r
+#define BKP0X_BK0V5 _BKP0X.Bits.BK0V5\r
+#define BKP0X_BK0V _BKP0X.MergedBits.grpBK0V\r
+\r
+\r
+/*** BKP0H - First Address High Byte Breakpoint Register; 0x0000002B ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT8 :1; /* First Address Breakpoint Register Bit 8 */\r
+ byte BIT9 :1; /* First Address Breakpoint Register Bit 9 */\r
+ byte BIT10 :1; /* First Address Breakpoint Register Bit 10 */\r
+ byte BIT11 :1; /* First Address Breakpoint Register Bit 11 */\r
+ byte BIT12 :1; /* First Address Breakpoint Register Bit 12 */\r
+ byte BIT13 :1; /* First Address Breakpoint Register Bit 13 */\r
+ byte BIT14 :1; /* First Address Breakpoint Register Bit 14 */\r
+ byte BIT15 :1; /* First Address Breakpoint Register Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT_8 :8;\r
+ } MergedBits;\r
+} BKP0HSTR;\r
+extern volatile BKP0HSTR _BKP0H @(REG_BASE + 0x0000002B);\r
+#define BKP0H _BKP0H.Byte\r
+#define BKP0H_BIT8 _BKP0H.Bits.BIT8\r
+#define BKP0H_BIT9 _BKP0H.Bits.BIT9\r
+#define BKP0H_BIT10 _BKP0H.Bits.BIT10\r
+#define BKP0H_BIT11 _BKP0H.Bits.BIT11\r
+#define BKP0H_BIT12 _BKP0H.Bits.BIT12\r
+#define BKP0H_BIT13 _BKP0H.Bits.BIT13\r
+#define BKP0H_BIT14 _BKP0H.Bits.BIT14\r
+#define BKP0H_BIT15 _BKP0H.Bits.BIT15\r
+#define BKP0H_BIT_8 _BKP0H.MergedBits.grpBIT_8\r
+#define BKP0H_BIT BKP0H_BIT_8\r
+\r
+\r
+/*** BKP0L - First Address Low Byte Breakpoint Register; 0x0000002C ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* First Address Breakpoint Register Bit 0 */\r
+ byte BIT1 :1; /* First Address Breakpoint Register Bit 1 */\r
+ byte BIT2 :1; /* First Address Breakpoint Register Bit 2 */\r
+ byte BIT3 :1; /* First Address Breakpoint Register Bit 3 */\r
+ byte BIT4 :1; /* First Address Breakpoint Register Bit 4 */\r
+ byte BIT5 :1; /* First Address Breakpoint Register Bit 5 */\r
+ byte BIT6 :1; /* First Address Breakpoint Register Bit 6 */\r
+ byte BIT7 :1; /* First Address Breakpoint Register Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+} BKP0LSTR;\r
+extern volatile BKP0LSTR _BKP0L @(REG_BASE + 0x0000002C);\r
+#define BKP0L _BKP0L.Byte\r
+#define BKP0L_BIT0 _BKP0L.Bits.BIT0\r
+#define BKP0L_BIT1 _BKP0L.Bits.BIT1\r
+#define BKP0L_BIT2 _BKP0L.Bits.BIT2\r
+#define BKP0L_BIT3 _BKP0L.Bits.BIT3\r
+#define BKP0L_BIT4 _BKP0L.Bits.BIT4\r
+#define BKP0L_BIT5 _BKP0L.Bits.BIT5\r
+#define BKP0L_BIT6 _BKP0L.Bits.BIT6\r
+#define BKP0L_BIT7 _BKP0L.Bits.BIT7\r
+#define BKP0L_BIT _BKP0L.MergedBits.grpBIT\r
+\r
+\r
+/*** BKP1X - Second Address Memory Expansion Breakpoint Register; 0x0000002D ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte BK1V0 :1; /* Second Address Breakpoint Expansion Address Value Bit 0 */\r
+ byte BK1V1 :1; /* Second Address Breakpoint Expansion Address Value Bit 1 */\r
+ byte BK1V2 :1; /* Second Address Breakpoint Expansion Address Value Bit 2 */\r
+ byte BK1V3 :1; /* Second Address Breakpoint Expansion Address Value Bit 3 */\r
+ byte BK1V4 :1; /* Second Address Breakpoint Expansion Address Value Bit 4 */\r
+ byte BK1V5 :1; /* Second Address Breakpoint Expansion Address Value Bit 5 */\r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpBK1V :6;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} BKP1XSTR;\r
+extern volatile BKP1XSTR _BKP1X @(REG_BASE + 0x0000002D);\r
+#define BKP1X _BKP1X.Byte\r
+#define BKP1X_BK1V0 _BKP1X.Bits.BK1V0\r
+#define BKP1X_BK1V1 _BKP1X.Bits.BK1V1\r
+#define BKP1X_BK1V2 _BKP1X.Bits.BK1V2\r
+#define BKP1X_BK1V3 _BKP1X.Bits.BK1V3\r
+#define BKP1X_BK1V4 _BKP1X.Bits.BK1V4\r
+#define BKP1X_BK1V5 _BKP1X.Bits.BK1V5\r
+#define BKP1X_BK1V _BKP1X.MergedBits.grpBK1V\r
+\r
+\r
+/*** BKP1H - Data (Second Address) High Byte Breakpoint Register; 0x0000002E ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT8 :1; /* Data (Second Address) Breakpoint Register Bit 8 */\r
+ byte BIT9 :1; /* Data (Second Address) Breakpoint Register Bit 9 */\r
+ byte BIT10 :1; /* Data (Second Address) Breakpoint Register Bit 10 */\r
+ byte BIT11 :1; /* Data (Second Address) Breakpoint Register Bit 11 */\r
+ byte BIT12 :1; /* Data (Second Address) Breakpoint Register Bit 12 */\r
+ byte BIT13 :1; /* Data (Second Address) Breakpoint Register Bit 13 */\r
+ byte BIT14 :1; /* Data (Second Address) Breakpoint Register Bit 14 */\r
+ byte BIT15 :1; /* Data (Second Address) Breakpoint Register Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT_8 :8;\r
+ } MergedBits;\r
+} BKP1HSTR;\r
+extern volatile BKP1HSTR _BKP1H @(REG_BASE + 0x0000002E);\r
+#define BKP1H _BKP1H.Byte\r
+#define BKP1H_BIT8 _BKP1H.Bits.BIT8\r
+#define BKP1H_BIT9 _BKP1H.Bits.BIT9\r
+#define BKP1H_BIT10 _BKP1H.Bits.BIT10\r
+#define BKP1H_BIT11 _BKP1H.Bits.BIT11\r
+#define BKP1H_BIT12 _BKP1H.Bits.BIT12\r
+#define BKP1H_BIT13 _BKP1H.Bits.BIT13\r
+#define BKP1H_BIT14 _BKP1H.Bits.BIT14\r
+#define BKP1H_BIT15 _BKP1H.Bits.BIT15\r
+#define BKP1H_BIT_8 _BKP1H.MergedBits.grpBIT_8\r
+#define BKP1H_BIT BKP1H_BIT_8\r
+\r
+\r
+/*** BKP1L - Data (Second Address) Low Byte Breakpoint Register; 0x0000002F ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* Data (Second Address) Breakpoint Register Bit 0 */\r
+ byte BIT1 :1; /* Data (Second Address) Breakpoint Register Bit 1 */\r
+ byte BIT2 :1; /* Data (Second Address) Breakpoint Register Bit 2 */\r
+ byte BIT3 :1; /* Data (Second Address) Breakpoint Register Bit 3 */\r
+ byte BIT4 :1; /* Data (Second Address) Breakpoint Register Bit 4 */\r
+ byte BIT5 :1; /* Data (Second Address) Breakpoint Register Bit 5 */\r
+ byte BIT6 :1; /* Data (Second Address) Breakpoint Register Bit 6 */\r
+ byte BIT7 :1; /* Data (Second Address) Breakpoint Register Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+} BKP1LSTR;\r
+extern volatile BKP1LSTR _BKP1L @(REG_BASE + 0x0000002F);\r
+#define BKP1L _BKP1L.Byte\r
+#define BKP1L_BIT0 _BKP1L.Bits.BIT0\r
+#define BKP1L_BIT1 _BKP1L.Bits.BIT1\r
+#define BKP1L_BIT2 _BKP1L.Bits.BIT2\r
+#define BKP1L_BIT3 _BKP1L.Bits.BIT3\r
+#define BKP1L_BIT4 _BKP1L.Bits.BIT4\r
+#define BKP1L_BIT5 _BKP1L.Bits.BIT5\r
+#define BKP1L_BIT6 _BKP1L.Bits.BIT6\r
+#define BKP1L_BIT7 _BKP1L.Bits.BIT7\r
+#define BKP1L_BIT _BKP1L.MergedBits.grpBIT\r
+\r
+\r
+/*** PPAGE - Page Index Register; 0x00000030 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PIX0 :1; /* Page Index Register Bit 0 */\r
+ byte PIX1 :1; /* Page Index Register Bit 1 */\r
+ byte PIX2 :1; /* Page Index Register Bit 2 */\r
+ byte PIX3 :1; /* Page Index Register Bit 3 */\r
+ byte PIX4 :1; /* Page Index Register Bit 4 */\r
+ byte PIX5 :1; /* Page Index Register Bit 5 */\r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpPIX :6;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} PPAGESTR;\r
+extern volatile PPAGESTR _PPAGE @(REG_BASE + 0x00000030);\r
+#define PPAGE _PPAGE.Byte\r
+#define PPAGE_PIX0 _PPAGE.Bits.PIX0\r
+#define PPAGE_PIX1 _PPAGE.Bits.PIX1\r
+#define PPAGE_PIX2 _PPAGE.Bits.PIX2\r
+#define PPAGE_PIX3 _PPAGE.Bits.PIX3\r
+#define PPAGE_PIX4 _PPAGE.Bits.PIX4\r
+#define PPAGE_PIX5 _PPAGE.Bits.PIX5\r
+#define PPAGE_PIX _PPAGE.MergedBits.grpPIX\r
+\r
+\r
+/*** PORTK - Port K Data Register; 0x00000032 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* Port K Bit 0 */\r
+ byte BIT1 :1; /* Port K Bit 1 */\r
+ byte BIT2 :1; /* Port K Bit 2 */\r
+ byte BIT3 :1; /* Port K Bit 3 */\r
+ byte BIT4 :1; /* Port K Bit 4 */\r
+ byte BIT5 :1; /* Port K Bit 5 */\r
+ byte :1; \r
+ byte BIT7 :1; /* Port K Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :6;\r
+ byte :1;\r
+ byte grpBIT_7 :1;\r
+ } MergedBits;\r
+} PORTKSTR;\r
+extern volatile PORTKSTR _PORTK @(REG_BASE + 0x00000032);\r
+#define PORTK _PORTK.Byte\r
+#define PORTK_BIT0 _PORTK.Bits.BIT0\r
+#define PORTK_BIT1 _PORTK.Bits.BIT1\r
+#define PORTK_BIT2 _PORTK.Bits.BIT2\r
+#define PORTK_BIT3 _PORTK.Bits.BIT3\r
+#define PORTK_BIT4 _PORTK.Bits.BIT4\r
+#define PORTK_BIT5 _PORTK.Bits.BIT5\r
+#define PORTK_BIT7 _PORTK.Bits.BIT7\r
+#define PORTK_BIT _PORTK.MergedBits.grpBIT\r
+\r
+\r
+/*** DDRK - Port K Data Direction Register; 0x00000033 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DDK0 :1; /* Port K Data Direction Bit 0 */\r
+ byte DDK1 :1; /* Port K Data Direction Bit 1 */\r
+ byte DDK2 :1; /* Port K Data Direction Bit 2 */\r
+ byte DDK3 :1; /* Port K Data Direction Bit 3 */\r
+ byte DDK4 :1; /* Port K Data Direction Bit 4 */\r
+ byte DDK5 :1; /* Port K Data Direction Bit 5 */\r
+ byte :1; \r
+ byte DDK7 :1; /* Port K Data Direction Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDDK :6;\r
+ byte :1;\r
+ byte grpDDK_7 :1;\r
+ } MergedBits;\r
+} DDRKSTR;\r
+extern volatile DDRKSTR _DDRK @(REG_BASE + 0x00000033);\r
+#define DDRK _DDRK.Byte\r
+#define DDRK_DDK0 _DDRK.Bits.DDK0\r
+#define DDRK_DDK1 _DDRK.Bits.DDK1\r
+#define DDRK_DDK2 _DDRK.Bits.DDK2\r
+#define DDRK_DDK3 _DDRK.Bits.DDK3\r
+#define DDRK_DDK4 _DDRK.Bits.DDK4\r
+#define DDRK_DDK5 _DDRK.Bits.DDK5\r
+#define DDRK_DDK7 _DDRK.Bits.DDK7\r
+#define DDRK_DDK _DDRK.MergedBits.grpDDK\r
+\r
+\r
+/*** SYNR - CRG Synthesizer Register; 0x00000034 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte SYN0 :1; /* CRG Synthesizer Bit 0 */\r
+ byte SYN1 :1; /* CRG Synthesizer Bit 1 */\r
+ byte SYN2 :1; /* CRG Synthesizer Bit 2 */\r
+ byte SYN3 :1; /* CRG Synthesizer Bit 3 */\r
+ byte SYN4 :1; /* CRG Synthesizer Bit 4 */\r
+ byte SYN5 :1; /* CRG Synthesizer Bit 5 */\r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpSYN :6;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} SYNRSTR;\r
+extern volatile SYNRSTR _SYNR @(REG_BASE + 0x00000034);\r
+#define SYNR _SYNR.Byte\r
+#define SYNR_SYN0 _SYNR.Bits.SYN0\r
+#define SYNR_SYN1 _SYNR.Bits.SYN1\r
+#define SYNR_SYN2 _SYNR.Bits.SYN2\r
+#define SYNR_SYN3 _SYNR.Bits.SYN3\r
+#define SYNR_SYN4 _SYNR.Bits.SYN4\r
+#define SYNR_SYN5 _SYNR.Bits.SYN5\r
+#define SYNR_SYN _SYNR.MergedBits.grpSYN\r
+\r
+\r
+/*** REFDV - CRG Reference Divider Register; 0x00000035 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte REFDV0 :1; /* CRG Reference Divider Bit 0 */\r
+ byte REFDV1 :1; /* CRG Reference Divider Bit 1 */\r
+ byte REFDV2 :1; /* CRG Reference Divider Bit 2 */\r
+ byte REFDV3 :1; /* CRG Reference Divider Bit 3 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpREFDV :4;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} REFDVSTR;\r
+extern volatile REFDVSTR _REFDV @(REG_BASE + 0x00000035);\r
+#define REFDV _REFDV.Byte\r
+#define REFDV_REFDV0 _REFDV.Bits.REFDV0\r
+#define REFDV_REFDV1 _REFDV.Bits.REFDV1\r
+#define REFDV_REFDV2 _REFDV.Bits.REFDV2\r
+#define REFDV_REFDV3 _REFDV.Bits.REFDV3\r
+#define REFDV_REFDV _REFDV.MergedBits.grpREFDV\r
+\r
+\r
+/*** CTFLG - CRG Test Flags Register; 0x00000036 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte TOUT0 :1; /* CRG Test Flags Bit 0 */\r
+ byte TOUT1 :1; /* CRG Test Flags Bit 1 */\r
+ byte TOUT2 :1; /* CRG Test Flags Bit 2 */\r
+ byte TOUT3 :1; /* CRG Test Flags Bit 3 */\r
+ byte TOUT4 :1; /* CRG Test Flags Bit 4 */\r
+ byte TOUT5 :1; /* CRG Test Flags Bit 5 */\r
+ byte TOUT6 :1; /* CRG Test Flags Bit 6 */\r
+ byte TOUT7 :1; /* CRG Test Flags Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpTOUT :8;\r
+ } MergedBits;\r
+} CTFLGSTR;\r
+extern volatile CTFLGSTR _CTFLG @(REG_BASE + 0x00000036);\r
+#define CTFLG _CTFLG.Byte\r
+#define CTFLG_TOUT0 _CTFLG.Bits.TOUT0\r
+#define CTFLG_TOUT1 _CTFLG.Bits.TOUT1\r
+#define CTFLG_TOUT2 _CTFLG.Bits.TOUT2\r
+#define CTFLG_TOUT3 _CTFLG.Bits.TOUT3\r
+#define CTFLG_TOUT4 _CTFLG.Bits.TOUT4\r
+#define CTFLG_TOUT5 _CTFLG.Bits.TOUT5\r
+#define CTFLG_TOUT6 _CTFLG.Bits.TOUT6\r
+#define CTFLG_TOUT7 _CTFLG.Bits.TOUT7\r
+#define CTFLG_TOUT _CTFLG.MergedBits.grpTOUT\r
+\r
+\r
+/*** CRGFLG - CRG Flags Register; 0x00000037 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte SCM :1; /* Self-clock mode Status */\r
+ byte SCMIF :1; /* Self-clock mode Interrupt Flag */\r
+ byte TRACK :1; /* Track Status */\r
+ byte LOCK :1; /* Lock Status */\r
+ byte LOCKIF :1; /* PLL Lock Interrupt Flag */\r
+ byte :1; \r
+ byte PORF :1; /* Power on Reset Flag */\r
+ byte RTIF :1; /* Real Time Interrupt Flag */\r
+ } Bits;\r
+} CRGFLGSTR;\r
+extern volatile CRGFLGSTR _CRGFLG @(REG_BASE + 0x00000037);\r
+#define CRGFLG _CRGFLG.Byte\r
+#define CRGFLG_SCM _CRGFLG.Bits.SCM\r
+#define CRGFLG_SCMIF _CRGFLG.Bits.SCMIF\r
+#define CRGFLG_TRACK _CRGFLG.Bits.TRACK\r
+#define CRGFLG_LOCK _CRGFLG.Bits.LOCK\r
+#define CRGFLG_LOCKIF _CRGFLG.Bits.LOCKIF\r
+#define CRGFLG_PORF _CRGFLG.Bits.PORF\r
+#define CRGFLG_RTIF _CRGFLG.Bits.RTIF\r
+\r
+\r
+/*** CRGINT - CRG Interrupt Enable Register; 0x00000038 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte SCMIE :1; /* Self-clock mode Interrupt Enable */\r
+ byte :1; \r
+ byte :1; \r
+ byte LOCKIE :1; /* Lock Interrupt Enable */\r
+ byte :1; \r
+ byte :1; \r
+ byte RTIE :1; /* Real Time Interrupt Enable */\r
+ } Bits;\r
+} CRGINTSTR;\r
+extern volatile CRGINTSTR _CRGINT @(REG_BASE + 0x00000038);\r
+#define CRGINT _CRGINT.Byte\r
+#define CRGINT_SCMIE _CRGINT.Bits.SCMIE\r
+#define CRGINT_LOCKIE _CRGINT.Bits.LOCKIE\r
+#define CRGINT_RTIE _CRGINT.Bits.RTIE\r
+\r
+\r
+/*** CLKSEL - CRG Clock Select Register; 0x00000039 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte COPWAI :1; /* COP stops in WAIT mode */\r
+ byte RTIWAI :1; /* RTI stops in WAIT mode */\r
+ byte CWAI :1; /* CLK24 and CLK23 stop in WAIT mode */\r
+ byte PLLWAI :1; /* PLL stops in WAIT mode */\r
+ byte ROAWAI :1; /* Reduced Oscillator Amplitude in WAIT mode */\r
+ byte SYSWAI :1; /* System clocks stop in WAIT mode */\r
+ byte PSTP :1; /* Pseudo Stop */\r
+ byte PLLSEL :1; /* PLL selected for system clock */\r
+ } Bits;\r
+} CLKSELSTR;\r
+extern volatile CLKSELSTR _CLKSEL @(REG_BASE + 0x00000039);\r
+#define CLKSEL _CLKSEL.Byte\r
+#define CLKSEL_COPWAI _CLKSEL.Bits.COPWAI\r
+#define CLKSEL_RTIWAI _CLKSEL.Bits.RTIWAI\r
+#define CLKSEL_CWAI _CLKSEL.Bits.CWAI\r
+#define CLKSEL_PLLWAI _CLKSEL.Bits.PLLWAI\r
+#define CLKSEL_ROAWAI _CLKSEL.Bits.ROAWAI\r
+#define CLKSEL_SYSWAI _CLKSEL.Bits.SYSWAI\r
+#define CLKSEL_PSTP _CLKSEL.Bits.PSTP\r
+#define CLKSEL_PLLSEL _CLKSEL.Bits.PLLSEL\r
+\r
+\r
+/*** PLLCTL - CRG PLL Control Register; 0x0000003A ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte SCME :1; /* Self-clock mode enable */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte ACQ :1; /* Acquisition */\r
+ byte AUTO :1; /* Automatic Bandwidth Control */\r
+ byte PLLON :1; /* Phase Lock Loop On */\r
+ byte CME :1; /* Crystal Monitor Enable */\r
+ } Bits;\r
+} PLLCTLSTR;\r
+extern volatile PLLCTLSTR _PLLCTL @(REG_BASE + 0x0000003A);\r
+#define PLLCTL _PLLCTL.Byte\r
+#define PLLCTL_SCME _PLLCTL.Bits.SCME\r
+#define PLLCTL_ACQ _PLLCTL.Bits.ACQ\r
+#define PLLCTL_AUTO _PLLCTL.Bits.AUTO\r
+#define PLLCTL_PLLON _PLLCTL.Bits.PLLON\r
+#define PLLCTL_CME _PLLCTL.Bits.CME\r
+\r
+\r
+/*** RTICTL - CRG RTI Control Register; 0x0000003B ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte RTR0 :1; /* Real Time Interrupt Modulus Counter Select */\r
+ byte RTR1 :1; /* Real Time Interrupt Modulus Counter Select */\r
+ byte RTR2 :1; /* Real Time Interrupt Modulus Counter Select */\r
+ byte RTR3 :1; /* Real Time Interrupt Modulus Counter Select */\r
+ byte RTR4 :1; /* Real Time Interrupt Prescale Rate Select */\r
+ byte RTR5 :1; /* Real Time Interrupt Prescale Rate Select */\r
+ byte RTR6 :1; /* Real Time Interrupt Prescale Rate Select */\r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpRTR :7;\r
+ byte :1;\r
+ } MergedBits;\r
+} RTICTLSTR;\r
+extern volatile RTICTLSTR _RTICTL @(REG_BASE + 0x0000003B);\r
+#define RTICTL _RTICTL.Byte\r
+#define RTICTL_RTR0 _RTICTL.Bits.RTR0\r
+#define RTICTL_RTR1 _RTICTL.Bits.RTR1\r
+#define RTICTL_RTR2 _RTICTL.Bits.RTR2\r
+#define RTICTL_RTR3 _RTICTL.Bits.RTR3\r
+#define RTICTL_RTR4 _RTICTL.Bits.RTR4\r
+#define RTICTL_RTR5 _RTICTL.Bits.RTR5\r
+#define RTICTL_RTR6 _RTICTL.Bits.RTR6\r
+#define RTICTL_RTR _RTICTL.MergedBits.grpRTR\r
+\r
+\r
+/*** COPCTL - CRG COP Control Register; 0x0000003C ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte CR0 :1; /* COP Watchdog Timer Rate select Bit 0 */\r
+ byte CR1 :1; /* COP Watchdog Timer Rate select Bit 1 */\r
+ byte CR2 :1; /* COP Watchdog Timer Rate select Bit 2 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte RSBCK :1; /* COP and RTI stop in Active BDM mode Bit */\r
+ byte WCOP :1; /* Window COP mode */\r
+ } Bits;\r
+ struct {\r
+ byte grpCR :3;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} COPCTLSTR;\r
+extern volatile COPCTLSTR _COPCTL @(REG_BASE + 0x0000003C);\r
+#define COPCTL _COPCTL.Byte\r
+#define COPCTL_CR0 _COPCTL.Bits.CR0\r
+#define COPCTL_CR1 _COPCTL.Bits.CR1\r
+#define COPCTL_CR2 _COPCTL.Bits.CR2\r
+#define COPCTL_RSBCK _COPCTL.Bits.RSBCK\r
+#define COPCTL_WCOP _COPCTL.Bits.WCOP\r
+#define COPCTL_CR _COPCTL.MergedBits.grpCR\r
+\r
+\r
+/*** FORBYP - Crg force and bypass test register; 0x0000003D ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* Bit 0 */\r
+ byte BIT1 :1; /* Bit 1 */\r
+ byte BIT2 :1; /* Bit 2 */\r
+ byte BIT3 :1; /* Bit 3 */\r
+ byte BIT4 :1; /* Bit 4 */\r
+ byte BIT5 :1; /* Bit 5 */\r
+ byte BIT6 :1; /* Bit 6 */\r
+ byte BIT7 :1; /* Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+} FORBYPSTR;\r
+extern volatile FORBYPSTR _FORBYP @(REG_BASE + 0x0000003D);\r
+#define FORBYP _FORBYP.Byte\r
+#define FORBYP_BIT0 _FORBYP.Bits.BIT0\r
+#define FORBYP_BIT1 _FORBYP.Bits.BIT1\r
+#define FORBYP_BIT2 _FORBYP.Bits.BIT2\r
+#define FORBYP_BIT3 _FORBYP.Bits.BIT3\r
+#define FORBYP_BIT4 _FORBYP.Bits.BIT4\r
+#define FORBYP_BIT5 _FORBYP.Bits.BIT5\r
+#define FORBYP_BIT6 _FORBYP.Bits.BIT6\r
+#define FORBYP_BIT7 _FORBYP.Bits.BIT7\r
+#define FORBYP_BIT _FORBYP.MergedBits.grpBIT\r
+\r
+\r
+/*** CTCTL - CRG Test Control Register; 0x0000003E ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte TCTL0 :1; /* CRG Test Control Bit 0 */\r
+ byte TCTL1 :1; /* CRG Test Control Bit 1 */\r
+ byte TCTL2 :1; /* CRG Test Control Bit 2 */\r
+ byte TCTL3 :1; /* CRG Test Control Bit 3 */\r
+ byte TCTL4 :1; /* CRG Test Control Bit 4 */\r
+ byte TCTL5 :1; /* CRG Test Control Bit 5 */\r
+ byte TCTL6 :1; /* CRG Test Control Bit 6 */\r
+ byte TCTL7 :1; /* CRG Test Control Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpTCTL :8;\r
+ } MergedBits;\r
+} CTCTLSTR;\r
+extern volatile CTCTLSTR _CTCTL @(REG_BASE + 0x0000003E);\r
+#define CTCTL _CTCTL.Byte\r
+#define CTCTL_TCTL0 _CTCTL.Bits.TCTL0\r
+#define CTCTL_TCTL1 _CTCTL.Bits.TCTL1\r
+#define CTCTL_TCTL2 _CTCTL.Bits.TCTL2\r
+#define CTCTL_TCTL3 _CTCTL.Bits.TCTL3\r
+#define CTCTL_TCTL4 _CTCTL.Bits.TCTL4\r
+#define CTCTL_TCTL5 _CTCTL.Bits.TCTL5\r
+#define CTCTL_TCTL6 _CTCTL.Bits.TCTL6\r
+#define CTCTL_TCTL7 _CTCTL.Bits.TCTL7\r
+#define CTCTL_TCTL _CTCTL.MergedBits.grpTCTL\r
+\r
+\r
+/*** ARMCOP - CRG COP Timer Arm/Reset Register; 0x0000003F ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* CRG COP Timer Arm/Reset Bit 0 */\r
+ byte BIT1 :1; /* CRG COP Timer Arm/Reset Bit 1 */\r
+ byte BIT2 :1; /* CRG COP Timer Arm/Reset Bit 2 */\r
+ byte BIT3 :1; /* CRG COP Timer Arm/Reset Bit 3 */\r
+ byte BIT4 :1; /* CRG COP Timer Arm/Reset Bit 4 */\r
+ byte BIT5 :1; /* CRG COP Timer Arm/Reset Bit 5 */\r
+ byte BIT6 :1; /* CRG COP Timer Arm/Reset Bit 6 */\r
+ byte BIT7 :1; /* CRG COP Timer Arm/Reset Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+} ARMCOPSTR;\r
+extern volatile ARMCOPSTR _ARMCOP @(REG_BASE + 0x0000003F);\r
+#define ARMCOP _ARMCOP.Byte\r
+#define ARMCOP_BIT0 _ARMCOP.Bits.BIT0\r
+#define ARMCOP_BIT1 _ARMCOP.Bits.BIT1\r
+#define ARMCOP_BIT2 _ARMCOP.Bits.BIT2\r
+#define ARMCOP_BIT3 _ARMCOP.Bits.BIT3\r
+#define ARMCOP_BIT4 _ARMCOP.Bits.BIT4\r
+#define ARMCOP_BIT5 _ARMCOP.Bits.BIT5\r
+#define ARMCOP_BIT6 _ARMCOP.Bits.BIT6\r
+#define ARMCOP_BIT7 _ARMCOP.Bits.BIT7\r
+#define ARMCOP_BIT _ARMCOP.MergedBits.grpBIT\r
+\r
+\r
+/*** TIOS - Timer Input Capture/Output Compare Select; 0x00000040 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte IOS0 :1; /* Input Capture or Output Compare Channel Configuration Bit 0 */\r
+ byte IOS1 :1; /* Input Capture or Output Compare Channel Configuration Bit 1 */\r
+ byte IOS2 :1; /* Input Capture or Output Compare Channel Configuration Bit 2 */\r
+ byte IOS3 :1; /* Input Capture or Output Compare Channel Configuration Bit 3 */\r
+ byte IOS4 :1; /* Input Capture or Output Compare Channel Configuration Bit 4 */\r
+ byte IOS5 :1; /* Input Capture or Output Compare Channel Configuration Bit 5 */\r
+ byte IOS6 :1; /* Input Capture or Output Compare Channel Configuration Bit 6 */\r
+ byte IOS7 :1; /* Input Capture or Output Compare Channel Configuration Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpIOS :8;\r
+ } MergedBits;\r
+} TIOSSTR;\r
+extern volatile TIOSSTR _TIOS @(REG_BASE + 0x00000040);\r
+#define TIOS _TIOS.Byte\r
+#define TIOS_IOS0 _TIOS.Bits.IOS0\r
+#define TIOS_IOS1 _TIOS.Bits.IOS1\r
+#define TIOS_IOS2 _TIOS.Bits.IOS2\r
+#define TIOS_IOS3 _TIOS.Bits.IOS3\r
+#define TIOS_IOS4 _TIOS.Bits.IOS4\r
+#define TIOS_IOS5 _TIOS.Bits.IOS5\r
+#define TIOS_IOS6 _TIOS.Bits.IOS6\r
+#define TIOS_IOS7 _TIOS.Bits.IOS7\r
+#define TIOS_IOS _TIOS.MergedBits.grpIOS\r
+\r
+\r
+/*** CFORC - Timer Compare Force Register; 0x00000041 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte FOC0 :1; /* Force Output Compare Action for Channel 0 */\r
+ byte FOC1 :1; /* Force Output Compare Action for Channel 1 */\r
+ byte FOC2 :1; /* Force Output Compare Action for Channel 2 */\r
+ byte FOC3 :1; /* Force Output Compare Action for Channel 3 */\r
+ byte FOC4 :1; /* Force Output Compare Action for Channel 4 */\r
+ byte FOC5 :1; /* Force Output Compare Action for Channel 5 */\r
+ byte FOC6 :1; /* Force Output Compare Action for Channel 6 */\r
+ byte FOC7 :1; /* Force Output Compare Action for Channel 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpFOC :8;\r
+ } MergedBits;\r
+} CFORCSTR;\r
+extern volatile CFORCSTR _CFORC @(REG_BASE + 0x00000041);\r
+#define CFORC _CFORC.Byte\r
+#define CFORC_FOC0 _CFORC.Bits.FOC0\r
+#define CFORC_FOC1 _CFORC.Bits.FOC1\r
+#define CFORC_FOC2 _CFORC.Bits.FOC2\r
+#define CFORC_FOC3 _CFORC.Bits.FOC3\r
+#define CFORC_FOC4 _CFORC.Bits.FOC4\r
+#define CFORC_FOC5 _CFORC.Bits.FOC5\r
+#define CFORC_FOC6 _CFORC.Bits.FOC6\r
+#define CFORC_FOC7 _CFORC.Bits.FOC7\r
+#define CFORC_FOC _CFORC.MergedBits.grpFOC\r
+\r
+\r
+/*** OC7M - Output Compare 7 Mask Register; 0x00000042 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte OC7M0 :1; /* Output Compare 7 Mask Bit 0 */\r
+ byte OC7M1 :1; /* Output Compare 7 Mask Bit 1 */\r
+ byte OC7M2 :1; /* Output Compare 7 Mask Bit 2 */\r
+ byte OC7M3 :1; /* Output Compare 7 Mask Bit 3 */\r
+ byte OC7M4 :1; /* Output Compare 7 Mask Bit 4 */\r
+ byte OC7M5 :1; /* Output Compare 7 Mask Bit 5 */\r
+ byte OC7M6 :1; /* Output Compare 7 Mask Bit 6 */\r
+ byte OC7M7 :1; /* Output Compare 7 Mask Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpOC7M :8;\r
+ } MergedBits;\r
+} OC7MSTR;\r
+extern volatile OC7MSTR _OC7M @(REG_BASE + 0x00000042);\r
+#define OC7M _OC7M.Byte\r
+#define OC7M_OC7M0 _OC7M.Bits.OC7M0\r
+#define OC7M_OC7M1 _OC7M.Bits.OC7M1\r
+#define OC7M_OC7M2 _OC7M.Bits.OC7M2\r
+#define OC7M_OC7M3 _OC7M.Bits.OC7M3\r
+#define OC7M_OC7M4 _OC7M.Bits.OC7M4\r
+#define OC7M_OC7M5 _OC7M.Bits.OC7M5\r
+#define OC7M_OC7M6 _OC7M.Bits.OC7M6\r
+#define OC7M_OC7M7 _OC7M.Bits.OC7M7\r
+#define OC7M_OC7M _OC7M.MergedBits.grpOC7M\r
+\r
+\r
+/*** OC7D - Output Compare 7 Data Register; 0x00000043 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte grpOC7D :8;\r
+ } MergedBits;\r
+} OC7DSTR;\r
+extern volatile OC7DSTR _OC7D @(REG_BASE + 0x00000043);\r
+#define OC7D _OC7D.Byte\r
+#define OC7D_OC7D _OC7D.MergedBits.grpOC7D\r
+\r
+\r
+/*** TSCR1 - Timer System Control Register1; 0x00000046 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte TFFCA :1; /* Timer Fast Flag Clear All */\r
+ byte TSFRZ :1; /* Timer and Modulus Counter Stop While in Freeze Mode */\r
+ byte TSWAI :1; /* Timer Module Stops While in Wait */\r
+ byte TEN :1; /* Timer Enable */\r
+ } Bits;\r
+} TSCR1STR;\r
+extern volatile TSCR1STR _TSCR1 @(REG_BASE + 0x00000046);\r
+#define TSCR1 _TSCR1.Byte\r
+#define TSCR1_TFFCA _TSCR1.Bits.TFFCA\r
+#define TSCR1_TSFRZ _TSCR1.Bits.TSFRZ\r
+#define TSCR1_TSWAI _TSCR1.Bits.TSWAI\r
+#define TSCR1_TEN _TSCR1.Bits.TEN\r
+\r
+\r
+/*** TTOV - Timer Toggle On Overflow Register; 0x00000047 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte TOV0 :1; /* Toggle On Overflow Bit 0 */\r
+ byte TOV1 :1; /* Toggle On Overflow Bit 1 */\r
+ byte TOV2 :1; /* Toggle On Overflow Bit 2 */\r
+ byte TOV3 :1; /* Toggle On Overflow Bit 3 */\r
+ byte TOV4 :1; /* Toggle On Overflow Bit 4 */\r
+ byte TOV5 :1; /* Toggle On Overflow Bit 5 */\r
+ byte TOV6 :1; /* Toggle On Overflow Bit 6 */\r
+ byte TOV7 :1; /* Toggle On Overflow Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpTOV :8;\r
+ } MergedBits;\r
+} TTOVSTR;\r
+extern volatile TTOVSTR _TTOV @(REG_BASE + 0x00000047);\r
+#define TTOV _TTOV.Byte\r
+#define TTOV_TOV0 _TTOV.Bits.TOV0\r
+#define TTOV_TOV1 _TTOV.Bits.TOV1\r
+#define TTOV_TOV2 _TTOV.Bits.TOV2\r
+#define TTOV_TOV3 _TTOV.Bits.TOV3\r
+#define TTOV_TOV4 _TTOV.Bits.TOV4\r
+#define TTOV_TOV5 _TTOV.Bits.TOV5\r
+#define TTOV_TOV6 _TTOV.Bits.TOV6\r
+#define TTOV_TOV7 _TTOV.Bits.TOV7\r
+#define TTOV_TOV _TTOV.MergedBits.grpTOV\r
+\r
+\r
+/*** TCTL1 - Timer Control Registers 1; 0x00000048 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte OL4 :1; /* Output Level Bit 4 */\r
+ byte OM4 :1; /* Output Mode Bit 4 */\r
+ byte OL5 :1; /* Output Level Bit 5 */\r
+ byte OM5 :1; /* Output Mode Bit 5 */\r
+ byte OL6 :1; /* Output Level Bit 6 */\r
+ byte OM6 :1; /* Output Mode Bit 6 */\r
+ byte OL7 :1; /* Output Level Bit 7 */\r
+ byte OM7 :1; /* Output Mode Bit 7 */\r
+ } Bits;\r
+} TCTL1STR;\r
+extern volatile TCTL1STR _TCTL1 @(REG_BASE + 0x00000048);\r
+#define TCTL1 _TCTL1.Byte\r
+#define TCTL1_OL4 _TCTL1.Bits.OL4\r
+#define TCTL1_OM4 _TCTL1.Bits.OM4\r
+#define TCTL1_OL5 _TCTL1.Bits.OL5\r
+#define TCTL1_OM5 _TCTL1.Bits.OM5\r
+#define TCTL1_OL6 _TCTL1.Bits.OL6\r
+#define TCTL1_OM6 _TCTL1.Bits.OM6\r
+#define TCTL1_OL7 _TCTL1.Bits.OL7\r
+#define TCTL1_OM7 _TCTL1.Bits.OM7\r
+\r
+\r
+/*** TCTL2 - Timer Control Registers 2; 0x00000049 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte OL0 :1; /* Output Level Bit 0 */\r
+ byte OM0 :1; /* Output Mode Bit 0 */\r
+ byte OL1 :1; /* Output Level Bit 1 */\r
+ byte OM1 :1; /* Output Mode Bit 1 */\r
+ byte OL2 :1; /* Output Level Bit 2 */\r
+ byte OM2 :1; /* Output Mode Bit 2 */\r
+ byte OL3 :1; /* Output Level Bit 3 */\r
+ byte OM3 :1; /* Output Mode Bit 3 */\r
+ } Bits;\r
+} TCTL2STR;\r
+extern volatile TCTL2STR _TCTL2 @(REG_BASE + 0x00000049);\r
+#define TCTL2 _TCTL2.Byte\r
+#define TCTL2_OL0 _TCTL2.Bits.OL0\r
+#define TCTL2_OM0 _TCTL2.Bits.OM0\r
+#define TCTL2_OL1 _TCTL2.Bits.OL1\r
+#define TCTL2_OM1 _TCTL2.Bits.OM1\r
+#define TCTL2_OL2 _TCTL2.Bits.OL2\r
+#define TCTL2_OM2 _TCTL2.Bits.OM2\r
+#define TCTL2_OL3 _TCTL2.Bits.OL3\r
+#define TCTL2_OM3 _TCTL2.Bits.OM3\r
+\r
+\r
+/*** TCTL3 - Timer Control Register 3; 0x0000004A ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte EDG4A :1; /* Input Capture Edge Control 4A */\r
+ byte EDG4B :1; /* Input Capture Edge Control 4B */\r
+ byte EDG5A :1; /* Input Capture Edge Control 5A */\r
+ byte EDG5B :1; /* Input Capture Edge Control 5B */\r
+ byte EDG6A :1; /* Input Capture Edge Control 6A */\r
+ byte EDG6B :1; /* Input Capture Edge Control 6B */\r
+ byte EDG7A :1; /* Input Capture Edge Control 7A */\r
+ byte EDG7B :1; /* Input Capture Edge Control 7B */\r
+ } Bits;\r
+} TCTL3STR;\r
+extern volatile TCTL3STR _TCTL3 @(REG_BASE + 0x0000004A);\r
+#define TCTL3 _TCTL3.Byte\r
+#define TCTL3_EDG4A _TCTL3.Bits.EDG4A\r
+#define TCTL3_EDG4B _TCTL3.Bits.EDG4B\r
+#define TCTL3_EDG5A _TCTL3.Bits.EDG5A\r
+#define TCTL3_EDG5B _TCTL3.Bits.EDG5B\r
+#define TCTL3_EDG6A _TCTL3.Bits.EDG6A\r
+#define TCTL3_EDG6B _TCTL3.Bits.EDG6B\r
+#define TCTL3_EDG7A _TCTL3.Bits.EDG7A\r
+#define TCTL3_EDG7B _TCTL3.Bits.EDG7B\r
+\r
+\r
+/*** TCTL4 - Timer Control Register 4; 0x0000004B ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte EDG0A :1; /* Input Capture Edge Control 0A */\r
+ byte EDG0B :1; /* Input Capture Edge Control 0B */\r
+ byte EDG1A :1; /* Input Capture Edge Control 1A */\r
+ byte EDG1B :1; /* Input Capture Edge Control 1B */\r
+ byte EDG2A :1; /* Input Capture Edge Control 2A */\r
+ byte EDG2B :1; /* Input Capture Edge Control 2B */\r
+ byte EDG3A :1; /* Input Capture Edge Control 3A */\r
+ byte EDG3B :1; /* Input Capture Edge Control 3B */\r
+ } Bits;\r
+} TCTL4STR;\r
+extern volatile TCTL4STR _TCTL4 @(REG_BASE + 0x0000004B);\r
+#define TCTL4 _TCTL4.Byte\r
+#define TCTL4_EDG0A _TCTL4.Bits.EDG0A\r
+#define TCTL4_EDG0B _TCTL4.Bits.EDG0B\r
+#define TCTL4_EDG1A _TCTL4.Bits.EDG1A\r
+#define TCTL4_EDG1B _TCTL4.Bits.EDG1B\r
+#define TCTL4_EDG2A _TCTL4.Bits.EDG2A\r
+#define TCTL4_EDG2B _TCTL4.Bits.EDG2B\r
+#define TCTL4_EDG3A _TCTL4.Bits.EDG3A\r
+#define TCTL4_EDG3B _TCTL4.Bits.EDG3B\r
+\r
+\r
+/*** TIE - Timer Interrupt Enable Register; 0x0000004C ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte C0I :1; /* Input Capture/Output Compare Interrupt Enable Bit 0 */\r
+ byte C1I :1; /* Input Capture/Output Compare Interrupt Enable Bit 1 */\r
+ byte C2I :1; /* Input Capture/Output Compare Interrupt Enable Bit 2 */\r
+ byte C3I :1; /* Input Capture/Output Compare Interrupt Enable Bit 3 */\r
+ byte C4I :1; /* Input Capture/Output Compare Interrupt Enable Bit 4 */\r
+ byte C5I :1; /* Input Capture/Output Compare Interrupt Enable Bit 5 */\r
+ byte C6I :1; /* Input Capture/Output Compare Interrupt Enable Bit 6 */\r
+ byte C7I :1; /* Input Capture/Output Compare Interrupt Enable Bit 7 */\r
+ } Bits;\r
+} TIESTR;\r
+extern volatile TIESTR _TIE @(REG_BASE + 0x0000004C);\r
+#define TIE _TIE.Byte\r
+#define TIE_C0I _TIE.Bits.C0I\r
+#define TIE_C1I _TIE.Bits.C1I\r
+#define TIE_C2I _TIE.Bits.C2I\r
+#define TIE_C3I _TIE.Bits.C3I\r
+#define TIE_C4I _TIE.Bits.C4I\r
+#define TIE_C5I _TIE.Bits.C5I\r
+#define TIE_C6I _TIE.Bits.C6I\r
+#define TIE_C7I _TIE.Bits.C7I\r
+\r
+\r
+/*** TSCR2 - Timer System Control Register 2; 0x0000004D ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PR0 :1; /* Timer Prescaler Select Bit 0 */\r
+ byte PR1 :1; /* Timer Prescaler Select Bit 1 */\r
+ byte PR2 :1; /* Timer Prescaler Select Bit 2 */\r
+ byte TCRE :1; /* Timer Counter Reset Enable */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte TOI :1; /* Timer Overflow Interrupt Enable */\r
+ } Bits;\r
+ struct {\r
+ byte grpPR :3;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} TSCR2STR;\r
+extern volatile TSCR2STR _TSCR2 @(REG_BASE + 0x0000004D);\r
+#define TSCR2 _TSCR2.Byte\r
+#define TSCR2_PR0 _TSCR2.Bits.PR0\r
+#define TSCR2_PR1 _TSCR2.Bits.PR1\r
+#define TSCR2_PR2 _TSCR2.Bits.PR2\r
+#define TSCR2_TCRE _TSCR2.Bits.TCRE\r
+#define TSCR2_TOI _TSCR2.Bits.TOI\r
+#define TSCR2_PR _TSCR2.MergedBits.grpPR\r
+\r
+\r
+/*** TFLG1 - Main Timer Interrupt Flag 1; 0x0000004E ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte C0F :1; /* Input Capture/Output Compare Channel Flag 0 */\r
+ byte C1F :1; /* Input Capture/Output Compare Channel Flag 1 */\r
+ byte C2F :1; /* Input Capture/Output Compare Channel Flag 2 */\r
+ byte C3F :1; /* Input Capture/Output Compare Channel Flag 3 */\r
+ byte C4F :1; /* Input Capture/Output Compare Channel Flag 4 */\r
+ byte C5F :1; /* Input Capture/Output Compare Channel Flag 5 */\r
+ byte C6F :1; /* Input Capture/Output Compare Channel Flag 6 */\r
+ byte C7F :1; /* Input Capture/Output Compare Channel Flag 7 */\r
+ } Bits;\r
+} TFLG1STR;\r
+extern volatile TFLG1STR _TFLG1 @(REG_BASE + 0x0000004E);\r
+#define TFLG1 _TFLG1.Byte\r
+#define TFLG1_C0F _TFLG1.Bits.C0F\r
+#define TFLG1_C1F _TFLG1.Bits.C1F\r
+#define TFLG1_C2F _TFLG1.Bits.C2F\r
+#define TFLG1_C3F _TFLG1.Bits.C3F\r
+#define TFLG1_C4F _TFLG1.Bits.C4F\r
+#define TFLG1_C5F _TFLG1.Bits.C5F\r
+#define TFLG1_C6F _TFLG1.Bits.C6F\r
+#define TFLG1_C7F _TFLG1.Bits.C7F\r
+\r
+\r
+/*** TFLG2 - Main Timer Interrupt Flag 2; 0x0000004F ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte TOF :1; /* Timer Overflow Flag */\r
+ } Bits;\r
+} TFLG2STR;\r
+extern volatile TFLG2STR _TFLG2 @(REG_BASE + 0x0000004F);\r
+#define TFLG2 _TFLG2.Byte\r
+#define TFLG2_TOF _TFLG2.Bits.TOF\r
+\r
+\r
+/*** PACTL - 16-Bit Pulse Accumulator A Control Register; 0x00000060 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PAI :1; /* Pulse Accumulator Input Interrupt enable */\r
+ byte PAOVI :1; /* Pulse Accumulator A Overflow Interrupt enable */\r
+ byte CLK0 :1; /* Clock Select Bit 0 */\r
+ byte CLK1 :1; /* Clock Select Bit 1 */\r
+ byte PEDGE :1; /* Pulse Accumulator Edge Control */\r
+ byte PAMOD :1; /* Pulse Accumulator Mode */\r
+ byte PAEN :1; /* Pulse Accumulator A System Enable */\r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte grpCLK :2;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} PACTLSTR;\r
+extern volatile PACTLSTR _PACTL @(REG_BASE + 0x00000060);\r
+#define PACTL _PACTL.Byte\r
+#define PACTL_PAI _PACTL.Bits.PAI\r
+#define PACTL_PAOVI _PACTL.Bits.PAOVI\r
+#define PACTL_CLK0 _PACTL.Bits.CLK0\r
+#define PACTL_CLK1 _PACTL.Bits.CLK1\r
+#define PACTL_PEDGE _PACTL.Bits.PEDGE\r
+#define PACTL_PAMOD _PACTL.Bits.PAMOD\r
+#define PACTL_PAEN _PACTL.Bits.PAEN\r
+#define PACTL_CLK _PACTL.MergedBits.grpCLK\r
+\r
+\r
+/*** PAFLG - Pulse Accumulator A Flag Register; 0x00000061 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PAIF :1; /* Pulse Accumulator Input edge Flag */\r
+ byte PAOVF :1; /* Pulse Accumulator A Overflow Flag */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+} PAFLGSTR;\r
+extern volatile PAFLGSTR _PAFLG @(REG_BASE + 0x00000061);\r
+#define PAFLG _PAFLG.Byte\r
+#define PAFLG_PAIF _PAFLG.Bits.PAIF\r
+#define PAFLG_PAOVF _PAFLG.Bits.PAOVF\r
+\r
+\r
+/*** MCCTL - Modulus Down Counter underflow; 0x00000066 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte MCPR0 :1; /* Modulus Counter Prescaler select 0 */\r
+ byte MCPR1 :1; /* Modulus Counter Prescaler select 1 */\r
+ byte MCEN :1; /* Modulus Down-Counter Enable */\r
+ byte FLMC :1; /* Force Load Register into the Modulus Counter Count Register */\r
+ byte ICLAT :1; /* Input Capture Force Latch Action */\r
+ byte RDMCL :1; /* Read Modulus Down-Counter Load */\r
+ byte MODMC :1; /* Modulus Mode Enable */\r
+ byte MCZI :1; /* Modulus Counter Underflow Interrupt Enable */\r
+ } Bits;\r
+ struct {\r
+ byte grpMCPR :2;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} MCCTLSTR;\r
+extern volatile MCCTLSTR _MCCTL @(REG_BASE + 0x00000066);\r
+#define MCCTL _MCCTL.Byte\r
+#define MCCTL_MCPR0 _MCCTL.Bits.MCPR0\r
+#define MCCTL_MCPR1 _MCCTL.Bits.MCPR1\r
+#define MCCTL_MCEN _MCCTL.Bits.MCEN\r
+#define MCCTL_FLMC _MCCTL.Bits.FLMC\r
+#define MCCTL_ICLAT _MCCTL.Bits.ICLAT\r
+#define MCCTL_RDMCL _MCCTL.Bits.RDMCL\r
+#define MCCTL_MODMC _MCCTL.Bits.MODMC\r
+#define MCCTL_MCZI _MCCTL.Bits.MCZI\r
+#define MCCTL_MCPR _MCCTL.MergedBits.grpMCPR\r
+\r
+\r
+/*** MCFLG - 16-Bit Modulus Down Counter Flag Register; 0x00000067 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte POLF0 :1; /* First Input Capture Polarity Status 0 */\r
+ byte POLF1 :1; /* First Input Capture Polarity Status 1 */\r
+ byte POLF2 :1; /* First Input Capture Polarity Status 2 */\r
+ byte POLF3 :1; /* First Input Capture Polarity Status 3 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte MCZF :1; /* Modulus Counter Underflow Flag */\r
+ } Bits;\r
+ struct {\r
+ byte grpPOLF :4;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} MCFLGSTR;\r
+extern volatile MCFLGSTR _MCFLG @(REG_BASE + 0x00000067);\r
+#define MCFLG _MCFLG.Byte\r
+#define MCFLG_POLF0 _MCFLG.Bits.POLF0\r
+#define MCFLG_POLF1 _MCFLG.Bits.POLF1\r
+#define MCFLG_POLF2 _MCFLG.Bits.POLF2\r
+#define MCFLG_POLF3 _MCFLG.Bits.POLF3\r
+#define MCFLG_MCZF _MCFLG.Bits.MCZF\r
+#define MCFLG_POLF _MCFLG.MergedBits.grpPOLF\r
+\r
+\r
+/*** ICPAR - Input Control Pulse Accumulator Register; 0x00000068 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PA0EN :1; /* 8-Bit Pulse Accumulator 0 Enable */\r
+ byte PA1EN :1; /* 8-Bit Pulse Accumulator 1 Enable */\r
+ byte PA2EN :1; /* 8-Bit Pulse Accumulator 2 Enable */\r
+ byte PA3EN :1; /* 8-Bit Pulse Accumulator 3 Enable */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+} ICPARSTR;\r
+extern volatile ICPARSTR _ICPAR @(REG_BASE + 0x00000068);\r
+#define ICPAR _ICPAR.Byte\r
+#define ICPAR_PA0EN _ICPAR.Bits.PA0EN\r
+#define ICPAR_PA1EN _ICPAR.Bits.PA1EN\r
+#define ICPAR_PA2EN _ICPAR.Bits.PA2EN\r
+#define ICPAR_PA3EN _ICPAR.Bits.PA3EN\r
+\r
+\r
+/*** DLYCT - Delay Counter Control Register; 0x00000069 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DLY0 :1; /* Delay Counter Select 0 */\r
+ byte DLY1 :1; /* Delay Counter Select 1 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpDLY :2;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} DLYCTSTR;\r
+extern volatile DLYCTSTR _DLYCT @(REG_BASE + 0x00000069);\r
+#define DLYCT _DLYCT.Byte\r
+#define DLYCT_DLY0 _DLYCT.Bits.DLY0\r
+#define DLYCT_DLY1 _DLYCT.Bits.DLY1\r
+#define DLYCT_DLY _DLYCT.MergedBits.grpDLY\r
+\r
+\r
+/*** ICOVW - Input Control Overwrite Register; 0x0000006A ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte NOVW0 :1; /* No Input Capture Overwrite 0 */\r
+ byte NOVW1 :1; /* No Input Capture Overwrite 1 */\r
+ byte NOVW2 :1; /* No Input Capture Overwrite 2 */\r
+ byte NOVW3 :1; /* No Input Capture Overwrite 3 */\r
+ byte NOVW4 :1; /* No Input Capture Overwrite 4 */\r
+ byte NOVW5 :1; /* No Input Capture Overwrite 5 */\r
+ byte NOVW6 :1; /* No Input Capture Overwrite 6 */\r
+ byte NOVW7 :1; /* No Input Capture Overwrite 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpNOVW :8;\r
+ } MergedBits;\r
+} ICOVWSTR;\r
+extern volatile ICOVWSTR _ICOVW @(REG_BASE + 0x0000006A);\r
+#define ICOVW _ICOVW.Byte\r
+#define ICOVW_NOVW0 _ICOVW.Bits.NOVW0\r
+#define ICOVW_NOVW1 _ICOVW.Bits.NOVW1\r
+#define ICOVW_NOVW2 _ICOVW.Bits.NOVW2\r
+#define ICOVW_NOVW3 _ICOVW.Bits.NOVW3\r
+#define ICOVW_NOVW4 _ICOVW.Bits.NOVW4\r
+#define ICOVW_NOVW5 _ICOVW.Bits.NOVW5\r
+#define ICOVW_NOVW6 _ICOVW.Bits.NOVW6\r
+#define ICOVW_NOVW7 _ICOVW.Bits.NOVW7\r
+#define ICOVW_NOVW _ICOVW.MergedBits.grpNOVW\r
+\r
+\r
+/*** ICSYS - Input Control System Control Register; 0x0000006B ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte LATQ :1; /* Input Control Latch or Queue Mode Enable */\r
+ byte BUFEN :1; /* IC Buffer Enable */\r
+ byte PACMX :1; /* 8-Bit Pulse Accumulators Maximum Count */\r
+ byte TFMOD :1; /* Timer Flag-setting Mode */\r
+ byte SH04 :1; /* Share Input action of Input Capture Channels 0 and 4 */\r
+ byte SH15 :1; /* Share Input action of Input Capture Channels 1 and 5 */\r
+ byte SH26 :1; /* Share Input action of Input Capture Channels 2 and 6 */\r
+ byte SH37 :1; /* Share Input action of Input Capture Channels 3 and 7 */\r
+ } Bits;\r
+} ICSYSSTR;\r
+extern volatile ICSYSSTR _ICSYS @(REG_BASE + 0x0000006B);\r
+#define ICSYS _ICSYS.Byte\r
+#define ICSYS_LATQ _ICSYS.Bits.LATQ\r
+#define ICSYS_BUFEN _ICSYS.Bits.BUFEN\r
+#define ICSYS_PACMX _ICSYS.Bits.PACMX\r
+#define ICSYS_TFMOD _ICSYS.Bits.TFMOD\r
+#define ICSYS_SH04 _ICSYS.Bits.SH04\r
+#define ICSYS_SH15 _ICSYS.Bits.SH15\r
+#define ICSYS_SH26 _ICSYS.Bits.SH26\r
+#define ICSYS_SH37 _ICSYS.Bits.SH37\r
+\r
+\r
+/*** TIMTST - Timer Test Register; 0x0000006D ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte TCBYP :1; /* Main Timer Divider Chain Bypass */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+} TIMTSTSTR;\r
+extern volatile TIMTSTSTR _TIMTST @(REG_BASE + 0x0000006D);\r
+#define TIMTST _TIMTST.Byte\r
+#define TIMTST_TCBYP _TIMTST.Bits.TCBYP\r
+\r
+\r
+/*** PBCTL - 16-Bit Pulse Accumulator B Control Register; 0x00000070 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte PBOVI :1; /* Pulse Accumulator B Overflow Interrupt enable */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte PBEN :1; /* Pulse Accumulator B System Enable */\r
+ byte :1; \r
+ } Bits;\r
+} PBCTLSTR;\r
+extern volatile PBCTLSTR _PBCTL @(REG_BASE + 0x00000070);\r
+#define PBCTL _PBCTL.Byte\r
+#define PBCTL_PBOVI _PBCTL.Bits.PBOVI\r
+#define PBCTL_PBEN _PBCTL.Bits.PBEN\r
+\r
+\r
+/*** PBFLG - Pulse Accumulator B Flag Register; 0x00000071 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte PBOVF :1; /* Pulse Accumulator B Overflow Flag */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+} PBFLGSTR;\r
+extern volatile PBFLGSTR _PBFLG @(REG_BASE + 0x00000071);\r
+#define PBFLG _PBFLG.Byte\r
+#define PBFLG_PBOVF _PBFLG.Bits.PBOVF\r
+\r
+\r
+/*** ATD0STAT0 - ATD 0 Status Register 0; 0x00000086 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte CC0 :1; /* Conversion Counter 0 */\r
+ byte CC1 :1; /* Conversion Counter 1 */\r
+ byte CC2 :1; /* Conversion Counter 2 */\r
+ byte :1; \r
+ byte FIFOR :1; /* FIFO Over Run Flag */\r
+ byte ETORF :1; /* External Trigger Overrun Flag */\r
+ byte :1; \r
+ byte SCF :1; /* Sequence Complete Flag */\r
+ } Bits;\r
+ struct {\r
+ byte grpCC :3;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} ATD0STAT0STR;\r
+extern volatile ATD0STAT0STR _ATD0STAT0 @(REG_BASE + 0x00000086);\r
+#define ATD0STAT0 _ATD0STAT0.Byte\r
+#define ATD0STAT0_CC0 _ATD0STAT0.Bits.CC0\r
+#define ATD0STAT0_CC1 _ATD0STAT0.Bits.CC1\r
+#define ATD0STAT0_CC2 _ATD0STAT0.Bits.CC2\r
+#define ATD0STAT0_FIFOR _ATD0STAT0.Bits.FIFOR\r
+#define ATD0STAT0_ETORF _ATD0STAT0.Bits.ETORF\r
+#define ATD0STAT0_SCF _ATD0STAT0.Bits.SCF\r
+#define ATD0STAT0_CC _ATD0STAT0.MergedBits.grpCC\r
+\r
+\r
+/*** ATD0STAT1 - ATD 0 Status Register 1; 0x0000008B ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte CCF0 :1; /* Conversion Complete Flag 0 */\r
+ byte CCF1 :1; /* Conversion Complete Flag 1 */\r
+ byte CCF2 :1; /* Conversion Complete Flag 2 */\r
+ byte CCF3 :1; /* Conversion Complete Flag 3 */\r
+ byte CCF4 :1; /* Conversion Complete Flag 4 */\r
+ byte CCF5 :1; /* Conversion Complete Flag 5 */\r
+ byte CCF6 :1; /* Conversion Complete Flag 6 */\r
+ byte CCF7 :1; /* Conversion Complete Flag 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpCCF :8;\r
+ } MergedBits;\r
+} ATD0STAT1STR;\r
+extern volatile ATD0STAT1STR _ATD0STAT1 @(REG_BASE + 0x0000008B);\r
+#define ATD0STAT1 _ATD0STAT1.Byte\r
+#define ATD0STAT1_CCF0 _ATD0STAT1.Bits.CCF0\r
+#define ATD0STAT1_CCF1 _ATD0STAT1.Bits.CCF1\r
+#define ATD0STAT1_CCF2 _ATD0STAT1.Bits.CCF2\r
+#define ATD0STAT1_CCF3 _ATD0STAT1.Bits.CCF3\r
+#define ATD0STAT1_CCF4 _ATD0STAT1.Bits.CCF4\r
+#define ATD0STAT1_CCF5 _ATD0STAT1.Bits.CCF5\r
+#define ATD0STAT1_CCF6 _ATD0STAT1.Bits.CCF6\r
+#define ATD0STAT1_CCF7 _ATD0STAT1.Bits.CCF7\r
+#define ATD0STAT1_CCF _ATD0STAT1.MergedBits.grpCCF\r
+\r
+\r
+/*** ATD0DIEN - ATD 0 Input Enable Mask Register; 0x0000008D ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* Disable/Enable Digital Input Buffer Bit 0 */\r
+ byte BIT1 :1; /* Disable/Enable Digital Input Buffer Bit 1 */\r
+ byte BIT2 :1; /* Disable/Enable Digital Input Buffer Bit 2 */\r
+ byte BIT3 :1; /* Disable/Enable Digital Input Buffer Bit 3 */\r
+ byte BIT4 :1; /* Disable/Enable Digital Input Buffer Bit 4 */\r
+ byte BIT5 :1; /* Disable/Enable Digital Input Buffer Bit 5 */\r
+ byte BIT6 :1; /* Disable/Enable Digital Input Buffer Bit 6 */\r
+ byte BIT7 :1; /* Disable/Enable Digital Input Buffer Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+} ATD0DIENSTR;\r
+extern volatile ATD0DIENSTR _ATD0DIEN @(REG_BASE + 0x0000008D);\r
+#define ATD0DIEN _ATD0DIEN.Byte\r
+#define ATD0DIEN_BIT0 _ATD0DIEN.Bits.BIT0\r
+#define ATD0DIEN_BIT1 _ATD0DIEN.Bits.BIT1\r
+#define ATD0DIEN_BIT2 _ATD0DIEN.Bits.BIT2\r
+#define ATD0DIEN_BIT3 _ATD0DIEN.Bits.BIT3\r
+#define ATD0DIEN_BIT4 _ATD0DIEN.Bits.BIT4\r
+#define ATD0DIEN_BIT5 _ATD0DIEN.Bits.BIT5\r
+#define ATD0DIEN_BIT6 _ATD0DIEN.Bits.BIT6\r
+#define ATD0DIEN_BIT7 _ATD0DIEN.Bits.BIT7\r
+#define ATD0DIEN_BIT _ATD0DIEN.MergedBits.grpBIT\r
+\r
+\r
+/*** PORTAD0 - Port AD0 Register; 0x0000008F ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* AN0 */\r
+ byte BIT1 :1; /* AN1 */\r
+ byte BIT2 :1; /* AN2 */\r
+ byte BIT3 :1; /* AN3 */\r
+ byte BIT4 :1; /* AN4 */\r
+ byte BIT5 :1; /* AN5 */\r
+ byte BIT6 :1; /* AN6 */\r
+ byte BIT7 :1; /* AN7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+} PORTAD0STR;\r
+extern volatile PORTAD0STR _PORTAD0 @(REG_BASE + 0x0000008F);\r
+#define PORTAD0 _PORTAD0.Byte\r
+#define PORTAD0_BIT0 _PORTAD0.Bits.BIT0\r
+#define PORTAD0_BIT1 _PORTAD0.Bits.BIT1\r
+#define PORTAD0_BIT2 _PORTAD0.Bits.BIT2\r
+#define PORTAD0_BIT3 _PORTAD0.Bits.BIT3\r
+#define PORTAD0_BIT4 _PORTAD0.Bits.BIT4\r
+#define PORTAD0_BIT5 _PORTAD0.Bits.BIT5\r
+#define PORTAD0_BIT6 _PORTAD0.Bits.BIT6\r
+#define PORTAD0_BIT7 _PORTAD0.Bits.BIT7\r
+#define PORTAD0_BIT _PORTAD0.MergedBits.grpBIT\r
+\r
+\r
+/*** PWME - PWM Enable Register; 0x000000A0 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PWME0 :1; /* Pulse Width Channel 0 Enable */\r
+ byte PWME1 :1; /* Pulse Width Channel 1 Enable */\r
+ byte PWME2 :1; /* Pulse Width Channel 2 Enable */\r
+ byte PWME3 :1; /* Pulse Width Channel 3 Enable */\r
+ byte PWME4 :1; /* Pulse Width Channel 4 Enable */\r
+ byte PWME5 :1; /* Pulse Width Channel 5 Enable */\r
+ byte PWME6 :1; /* Pulse Width Channel 6 Enable */\r
+ byte PWME7 :1; /* Pulse Width Channel 7 Enable */\r
+ } Bits;\r
+ struct {\r
+ byte grpPWME :8;\r
+ } MergedBits;\r
+} PWMESTR;\r
+extern volatile PWMESTR _PWME @(REG_BASE + 0x000000A0);\r
+#define PWME _PWME.Byte\r
+#define PWME_PWME0 _PWME.Bits.PWME0\r
+#define PWME_PWME1 _PWME.Bits.PWME1\r
+#define PWME_PWME2 _PWME.Bits.PWME2\r
+#define PWME_PWME3 _PWME.Bits.PWME3\r
+#define PWME_PWME4 _PWME.Bits.PWME4\r
+#define PWME_PWME5 _PWME.Bits.PWME5\r
+#define PWME_PWME6 _PWME.Bits.PWME6\r
+#define PWME_PWME7 _PWME.Bits.PWME7\r
+#define PWME_PWME _PWME.MergedBits.grpPWME\r
+\r
+\r
+/*** PWMPOL - PWM Polarity Register; 0x000000A1 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PPOL0 :1; /* Pulse Width Channel 0 Polarity */\r
+ byte PPOL1 :1; /* Pulse Width Channel 1 Polarity */\r
+ byte PPOL2 :1; /* Pulse Width Channel 2 Polarity */\r
+ byte PPOL3 :1; /* Pulse Width Channel 3 Polarity */\r
+ byte PPOL4 :1; /* Pulse Width Channel 4 Polarity */\r
+ byte PPOL5 :1; /* Pulse Width Channel 5 Polarity */\r
+ byte PPOL6 :1; /* Pulse Width Channel 6 Polarity */\r
+ byte PPOL7 :1; /* Pulse Width Channel 7 Polarity */\r
+ } Bits;\r
+ struct {\r
+ byte grpPPOL :8;\r
+ } MergedBits;\r
+} PWMPOLSTR;\r
+extern volatile PWMPOLSTR _PWMPOL @(REG_BASE + 0x000000A1);\r
+#define PWMPOL _PWMPOL.Byte\r
+#define PWMPOL_PPOL0 _PWMPOL.Bits.PPOL0\r
+#define PWMPOL_PPOL1 _PWMPOL.Bits.PPOL1\r
+#define PWMPOL_PPOL2 _PWMPOL.Bits.PPOL2\r
+#define PWMPOL_PPOL3 _PWMPOL.Bits.PPOL3\r
+#define PWMPOL_PPOL4 _PWMPOL.Bits.PPOL4\r
+#define PWMPOL_PPOL5 _PWMPOL.Bits.PPOL5\r
+#define PWMPOL_PPOL6 _PWMPOL.Bits.PPOL6\r
+#define PWMPOL_PPOL7 _PWMPOL.Bits.PPOL7\r
+#define PWMPOL_PPOL _PWMPOL.MergedBits.grpPPOL\r
+\r
+\r
+/*** PWMCLK - PWM Clock Select Register; 0x000000A2 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PCLK0 :1; /* Pulse Width Channel 0 Clock Select */\r
+ byte PCLK1 :1; /* Pulse Width Channel 1 Clock Select */\r
+ byte PCLK2 :1; /* Pulse Width Channel 2 Clock Select */\r
+ byte PCLK3 :1; /* Pulse Width Channel 3 Clock Select */\r
+ byte PCLK4 :1; /* Pulse Width Channel 4 Clock Select */\r
+ byte PCLK5 :1; /* Pulse Width Channel 5 Clock Select */\r
+ byte PCLK6 :1; /* Pulse Width Channel 6 Clock Select */\r
+ byte PCLK7 :1; /* Pulse Width Channel 7 Clock Select */\r
+ } Bits;\r
+ struct {\r
+ byte grpPCLK :8;\r
+ } MergedBits;\r
+} PWMCLKSTR;\r
+extern volatile PWMCLKSTR _PWMCLK @(REG_BASE + 0x000000A2);\r
+#define PWMCLK _PWMCLK.Byte\r
+#define PWMCLK_PCLK0 _PWMCLK.Bits.PCLK0\r
+#define PWMCLK_PCLK1 _PWMCLK.Bits.PCLK1\r
+#define PWMCLK_PCLK2 _PWMCLK.Bits.PCLK2\r
+#define PWMCLK_PCLK3 _PWMCLK.Bits.PCLK3\r
+#define PWMCLK_PCLK4 _PWMCLK.Bits.PCLK4\r
+#define PWMCLK_PCLK5 _PWMCLK.Bits.PCLK5\r
+#define PWMCLK_PCLK6 _PWMCLK.Bits.PCLK6\r
+#define PWMCLK_PCLK7 _PWMCLK.Bits.PCLK7\r
+#define PWMCLK_PCLK _PWMCLK.MergedBits.grpPCLK\r
+\r
+\r
+/*** PWMPRCLK - PWM Prescale Clock Select Register; 0x000000A3 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PCKA0 :1; /* Prescaler Select for Clock A 0 */\r
+ byte PCKA1 :1; /* Prescaler Select for Clock A 1 */\r
+ byte PCKA2 :1; /* Prescaler Select for Clock A 2 */\r
+ byte :1; \r
+ byte PCKB0 :1; /* Prescaler Select for Clock B 0 */\r
+ byte PCKB1 :1; /* Prescaler Select for Clock B 1 */\r
+ byte PCKB2 :1; /* Prescaler Select for Clock B 2 */\r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpPCKA :3;\r
+ byte :1;\r
+ byte grpPCKB :3;\r
+ byte :1;\r
+ } MergedBits;\r
+} PWMPRCLKSTR;\r
+extern volatile PWMPRCLKSTR _PWMPRCLK @(REG_BASE + 0x000000A3);\r
+#define PWMPRCLK _PWMPRCLK.Byte\r
+#define PWMPRCLK_PCKA0 _PWMPRCLK.Bits.PCKA0\r
+#define PWMPRCLK_PCKA1 _PWMPRCLK.Bits.PCKA1\r
+#define PWMPRCLK_PCKA2 _PWMPRCLK.Bits.PCKA2\r
+#define PWMPRCLK_PCKB0 _PWMPRCLK.Bits.PCKB0\r
+#define PWMPRCLK_PCKB1 _PWMPRCLK.Bits.PCKB1\r
+#define PWMPRCLK_PCKB2 _PWMPRCLK.Bits.PCKB2\r
+#define PWMPRCLK_PCKA _PWMPRCLK.MergedBits.grpPCKA\r
+#define PWMPRCLK_PCKB _PWMPRCLK.MergedBits.grpPCKB\r
+\r
+\r
+/*** PWMCAE - PWM Center Align Enable Register; 0x000000A4 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte CAE0 :1; /* Center Aligned Output Mode on channel 0 */\r
+ byte CAE1 :1; /* Center Aligned Output Mode on channel 1 */\r
+ byte CAE2 :1; /* Center Aligned Output Mode on channel 2 */\r
+ byte CAE3 :1; /* Center Aligned Output Mode on channel 3 */\r
+ byte CAE4 :1; /* Center Aligned Output Mode on channel 4 */\r
+ byte CAE5 :1; /* Center Aligned Output Mode on channel 5 */\r
+ byte CAE6 :1; /* Center Aligned Output Mode on channel 6 */\r
+ byte CAE7 :1; /* Center Aligned Output Mode on channel 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpCAE :8;\r
+ } MergedBits;\r
+} PWMCAESTR;\r
+extern volatile PWMCAESTR _PWMCAE @(REG_BASE + 0x000000A4);\r
+#define PWMCAE _PWMCAE.Byte\r
+#define PWMCAE_CAE0 _PWMCAE.Bits.CAE0\r
+#define PWMCAE_CAE1 _PWMCAE.Bits.CAE1\r
+#define PWMCAE_CAE2 _PWMCAE.Bits.CAE2\r
+#define PWMCAE_CAE3 _PWMCAE.Bits.CAE3\r
+#define PWMCAE_CAE4 _PWMCAE.Bits.CAE4\r
+#define PWMCAE_CAE5 _PWMCAE.Bits.CAE5\r
+#define PWMCAE_CAE6 _PWMCAE.Bits.CAE6\r
+#define PWMCAE_CAE7 _PWMCAE.Bits.CAE7\r
+#define PWMCAE_CAE _PWMCAE.MergedBits.grpCAE\r
+\r
+\r
+/*** PWMCTL - PWM Control Register; 0x000000A5 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte PFRZ :1; /* PWM Counters Stop in Freeze Mode */\r
+ byte PSWAI :1; /* PWM Stops in Wait Mode */\r
+ byte CON01 :1; /* Concatenate channels 0 and 1 */\r
+ byte CON23 :1; /* Concatenate channels 2 and 3 */\r
+ byte CON45 :1; /* Concatenate channels 4 and 5 */\r
+ byte CON67 :1; /* Concatenate channels 6 and 7 */\r
+ } Bits;\r
+} PWMCTLSTR;\r
+extern volatile PWMCTLSTR _PWMCTL @(REG_BASE + 0x000000A5);\r
+#define PWMCTL _PWMCTL.Byte\r
+#define PWMCTL_PFRZ _PWMCTL.Bits.PFRZ\r
+#define PWMCTL_PSWAI _PWMCTL.Bits.PSWAI\r
+#define PWMCTL_CON01 _PWMCTL.Bits.CON01\r
+#define PWMCTL_CON23 _PWMCTL.Bits.CON23\r
+#define PWMCTL_CON45 _PWMCTL.Bits.CON45\r
+#define PWMCTL_CON67 _PWMCTL.Bits.CON67\r
+\r
+\r
+/*** PWMSCLA - PWM Scale A Register; 0x000000A8 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* PWM Scale A Bit 0 */\r
+ byte BIT1 :1; /* PWM Scale A Bit 1 */\r
+ byte BIT2 :1; /* PWM Scale A Bit 2 */\r
+ byte BIT3 :1; /* PWM Scale A Bit 3 */\r
+ byte BIT4 :1; /* PWM Scale A Bit 4 */\r
+ byte BIT5 :1; /* PWM Scale A Bit 5 */\r
+ byte BIT6 :1; /* PWM Scale A Bit 6 */\r
+ byte BIT7 :1; /* PWM Scale A Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+} PWMSCLASTR;\r
+extern volatile PWMSCLASTR _PWMSCLA @(REG_BASE + 0x000000A8);\r
+#define PWMSCLA _PWMSCLA.Byte\r
+#define PWMSCLA_BIT0 _PWMSCLA.Bits.BIT0\r
+#define PWMSCLA_BIT1 _PWMSCLA.Bits.BIT1\r
+#define PWMSCLA_BIT2 _PWMSCLA.Bits.BIT2\r
+#define PWMSCLA_BIT3 _PWMSCLA.Bits.BIT3\r
+#define PWMSCLA_BIT4 _PWMSCLA.Bits.BIT4\r
+#define PWMSCLA_BIT5 _PWMSCLA.Bits.BIT5\r
+#define PWMSCLA_BIT6 _PWMSCLA.Bits.BIT6\r
+#define PWMSCLA_BIT7 _PWMSCLA.Bits.BIT7\r
+#define PWMSCLA_BIT _PWMSCLA.MergedBits.grpBIT\r
+\r
+\r
+/*** PWMSCLB - PWM Scale B Register; 0x000000A9 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* PWM Scale B Bit 0 */\r
+ byte BIT1 :1; /* PWM Scale B Bit 1 */\r
+ byte BIT2 :1; /* PWM Scale B Bit 2 */\r
+ byte BIT3 :1; /* PWM Scale B Bit 3 */\r
+ byte BIT4 :1; /* PWM Scale B Bit 4 */\r
+ byte BIT5 :1; /* PWM Scale B Bit 5 */\r
+ byte BIT6 :1; /* PWM Scale B Bit 6 */\r
+ byte BIT7 :1; /* PWM Scale B Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+} PWMSCLBSTR;\r
+extern volatile PWMSCLBSTR _PWMSCLB @(REG_BASE + 0x000000A9);\r
+#define PWMSCLB _PWMSCLB.Byte\r
+#define PWMSCLB_BIT0 _PWMSCLB.Bits.BIT0\r
+#define PWMSCLB_BIT1 _PWMSCLB.Bits.BIT1\r
+#define PWMSCLB_BIT2 _PWMSCLB.Bits.BIT2\r
+#define PWMSCLB_BIT3 _PWMSCLB.Bits.BIT3\r
+#define PWMSCLB_BIT4 _PWMSCLB.Bits.BIT4\r
+#define PWMSCLB_BIT5 _PWMSCLB.Bits.BIT5\r
+#define PWMSCLB_BIT6 _PWMSCLB.Bits.BIT6\r
+#define PWMSCLB_BIT7 _PWMSCLB.Bits.BIT7\r
+#define PWMSCLB_BIT _PWMSCLB.MergedBits.grpBIT\r
+\r
+\r
+/*** PWMSDN - PWM Shutdown Register; 0x000000C4 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PWM7ENA :1; /* PWM emergency shutdown Enable */\r
+ byte PWM7INL :1; /* PWM shutdown active input level for ch. 7 */\r
+ byte PWM7IN :1; /* PWM channel 7 input status */\r
+ byte :1; \r
+ byte PWMLVL :1; /* PWM shutdown output Level */\r
+ byte PWMRSTRT :1; /* PWM Restart */\r
+ byte PWMIE :1; /* PWM Interrupt Enable */\r
+ byte PWMIF :1; /* PWM Interrupt Flag */\r
+ } Bits;\r
+} PWMSDNSTR;\r
+extern volatile PWMSDNSTR _PWMSDN @(REG_BASE + 0x000000C4);\r
+#define PWMSDN _PWMSDN.Byte\r
+#define PWMSDN_PWM7ENA _PWMSDN.Bits.PWM7ENA\r
+#define PWMSDN_PWM7INL _PWMSDN.Bits.PWM7INL\r
+#define PWMSDN_PWM7IN _PWMSDN.Bits.PWM7IN\r
+#define PWMSDN_PWMLVL _PWMSDN.Bits.PWMLVL\r
+#define PWMSDN_PWMRSTRT _PWMSDN.Bits.PWMRSTRT\r
+#define PWMSDN_PWMIE _PWMSDN.Bits.PWMIE\r
+#define PWMSDN_PWMIF _PWMSDN.Bits.PWMIF\r
+\r
+\r
+/*** SCI0CR1 - SCI 0 Control Register 1; 0x000000CA ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PT :1; /* Parity Type Bit */\r
+ byte PE :1; /* Parity Enable Bit */\r
+ byte ILT :1; /* Idle Line Type Bit */\r
+ byte WAKE :1; /* Wakeup Condition Bit */\r
+ byte M :1; /* Data Format Mode Bit */\r
+ byte RSRC :1; /* Receiver Source Bit */\r
+ byte SCISWAI :1; /* SCI 0 Stop in Wait Mode Bit */\r
+ byte LOOPS :1; /* Loop Select Bit */\r
+ } Bits;\r
+} SCI0CR1STR;\r
+extern volatile SCI0CR1STR _SCI0CR1 @(REG_BASE + 0x000000CA);\r
+#define SCI0CR1 _SCI0CR1.Byte\r
+#define SCI0CR1_PT _SCI0CR1.Bits.PT\r
+#define SCI0CR1_PE _SCI0CR1.Bits.PE\r
+#define SCI0CR1_ILT _SCI0CR1.Bits.ILT\r
+#define SCI0CR1_WAKE _SCI0CR1.Bits.WAKE\r
+#define SCI0CR1_M _SCI0CR1.Bits.M\r
+#define SCI0CR1_RSRC _SCI0CR1.Bits.RSRC\r
+#define SCI0CR1_SCISWAI _SCI0CR1.Bits.SCISWAI\r
+#define SCI0CR1_LOOPS _SCI0CR1.Bits.LOOPS\r
+\r
+\r
+/*** SCI0CR2 - SCI 0 Control Register 2; 0x000000CB ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte SBK :1; /* Send Break Bit */\r
+ byte RWU :1; /* Receiver Wakeup Bit */\r
+ byte RE :1; /* Receiver Enable Bit */\r
+ byte TE :1; /* Transmitter Enable Bit */\r
+ byte ILIE :1; /* Idle Line Interrupt Enable Bit */\r
+ byte RIE :1; /* Receiver Full Interrupt Enable Bit */\r
+ byte TCIE :1; /* Transmission Complete Interrupt Enable Bit */\r
+ byte SCTIE :1; /* Transmitter Interrupt Enable Bit */\r
+ } Bits;\r
+} SCI0CR2STR;\r
+extern volatile SCI0CR2STR _SCI0CR2 @(REG_BASE + 0x000000CB);\r
+#define SCI0CR2 _SCI0CR2.Byte\r
+#define SCI0CR2_SBK _SCI0CR2.Bits.SBK\r
+#define SCI0CR2_RWU _SCI0CR2.Bits.RWU\r
+#define SCI0CR2_RE _SCI0CR2.Bits.RE\r
+#define SCI0CR2_TE _SCI0CR2.Bits.TE\r
+#define SCI0CR2_ILIE _SCI0CR2.Bits.ILIE\r
+#define SCI0CR2_RIE _SCI0CR2.Bits.RIE\r
+#define SCI0CR2_TCIE _SCI0CR2.Bits.TCIE\r
+#define SCI0CR2_SCTIE _SCI0CR2.Bits.SCTIE\r
+\r
+\r
+/*** SCI0SR1 - SCI 0 Status Register 1; 0x000000CC ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PF :1; /* Parity Error Flag */\r
+ byte FE :1; /* Framing Error Flag */\r
+ byte NF :1; /* Noise Flag */\r
+ byte OR :1; /* Overrun Flag */\r
+ byte IDLE :1; /* Idle Line Flag */\r
+ byte RDRF :1; /* Receive Data Register Full Flag */\r
+ byte TC :1; /* Transmit Complete Flag */\r
+ byte TDRE :1; /* Transmit Data Register Empty Flag */\r
+ } Bits;\r
+} SCI0SR1STR;\r
+extern volatile SCI0SR1STR _SCI0SR1 @(REG_BASE + 0x000000CC);\r
+#define SCI0SR1 _SCI0SR1.Byte\r
+#define SCI0SR1_PF _SCI0SR1.Bits.PF\r
+#define SCI0SR1_FE _SCI0SR1.Bits.FE\r
+#define SCI0SR1_NF _SCI0SR1.Bits.NF\r
+#define SCI0SR1_OR _SCI0SR1.Bits.OR\r
+#define SCI0SR1_IDLE _SCI0SR1.Bits.IDLE\r
+#define SCI0SR1_RDRF _SCI0SR1.Bits.RDRF\r
+#define SCI0SR1_TC _SCI0SR1.Bits.TC\r
+#define SCI0SR1_TDRE _SCI0SR1.Bits.TDRE\r
+\r
+\r
+/*** SCI0SR2 - SCI 0 Status Register 2; 0x000000CD ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte RAF :1; /* Receiver Active Flag */\r
+ byte TXDIR :1; /* Transmitter pin data direction in Single-Wire mode */\r
+ byte BRK13 :1; /* Break Transmit character length */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+} SCI0SR2STR;\r
+extern volatile SCI0SR2STR _SCI0SR2 @(REG_BASE + 0x000000CD);\r
+#define SCI0SR2 _SCI0SR2.Byte\r
+#define SCI0SR2_RAF _SCI0SR2.Bits.RAF\r
+#define SCI0SR2_TXDIR _SCI0SR2.Bits.TXDIR\r
+#define SCI0SR2_BRK13 _SCI0SR2.Bits.BRK13\r
+\r
+\r
+/*** SCI0DRH - SCI 0 Data Register High; 0x000000CE ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte T8 :1; /* Transmit Bit 8 */\r
+ byte R8 :1; /* Received Bit 8 */\r
+ } Bits;\r
+} SCI0DRHSTR;\r
+extern volatile SCI0DRHSTR _SCI0DRH @(REG_BASE + 0x000000CE);\r
+#define SCI0DRH _SCI0DRH.Byte\r
+#define SCI0DRH_T8 _SCI0DRH.Bits.T8\r
+#define SCI0DRH_R8 _SCI0DRH.Bits.R8\r
+\r
+\r
+/*** SCI0DRL - SCI 0 Data Register Low; 0x000000CF ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte R0_T0 :1; /* Received bit 0 or Transmit bit 0 */\r
+ byte R1_T1 :1; /* Received bit 1 or Transmit bit 1 */\r
+ byte R2_T2 :1; /* Received bit 2 or Transmit bit 2 */\r
+ byte R3_T3 :1; /* Received bit 3 or Transmit bit 3 */\r
+ byte R4_T4 :1; /* Received bit 4 or Transmit bit 4 */\r
+ byte R5_T5 :1; /* Received bit 5 or Transmit bit 5 */\r
+ byte R6_T6 :1; /* Received bit 6 or Transmit bit 6 */\r
+ byte R7_T7 :1; /* Received bit 7 or Transmit bit 7 */\r
+ } Bits;\r
+} SCI0DRLSTR;\r
+extern volatile SCI0DRLSTR _SCI0DRL @(REG_BASE + 0x000000CF);\r
+#define SCI0DRL _SCI0DRL.Byte\r
+#define SCI0DRL_R0_T0 _SCI0DRL.Bits.R0_T0\r
+#define SCI0DRL_R1_T1 _SCI0DRL.Bits.R1_T1\r
+#define SCI0DRL_R2_T2 _SCI0DRL.Bits.R2_T2\r
+#define SCI0DRL_R3_T3 _SCI0DRL.Bits.R3_T3\r
+#define SCI0DRL_R4_T4 _SCI0DRL.Bits.R4_T4\r
+#define SCI0DRL_R5_T5 _SCI0DRL.Bits.R5_T5\r
+#define SCI0DRL_R6_T6 _SCI0DRL.Bits.R6_T6\r
+#define SCI0DRL_R7_T7 _SCI0DRL.Bits.R7_T7\r
+\r
+\r
+/*** SCI1CR1 - SCI 1 Control Register 1; 0x000000D2 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PT :1; /* Parity Type Bit */\r
+ byte PE :1; /* Parity Enable Bit */\r
+ byte ILT :1; /* Idle Line Type Bit */\r
+ byte WAKE :1; /* Wakeup Condition Bit */\r
+ byte M :1; /* Data Format Mode Bit */\r
+ byte RSRC :1; /* Receiver Source Bit */\r
+ byte SCISWAI :1; /* SCI 1 Stop in Wait Mode Bit */\r
+ byte LOOPS :1; /* Loop Select Bit */\r
+ } Bits;\r
+} SCI1CR1STR;\r
+extern volatile SCI1CR1STR _SCI1CR1 @(REG_BASE + 0x000000D2);\r
+#define SCI1CR1 _SCI1CR1.Byte\r
+#define SCI1CR1_PT _SCI1CR1.Bits.PT\r
+#define SCI1CR1_PE _SCI1CR1.Bits.PE\r
+#define SCI1CR1_ILT _SCI1CR1.Bits.ILT\r
+#define SCI1CR1_WAKE _SCI1CR1.Bits.WAKE\r
+#define SCI1CR1_M _SCI1CR1.Bits.M\r
+#define SCI1CR1_RSRC _SCI1CR1.Bits.RSRC\r
+#define SCI1CR1_SCISWAI _SCI1CR1.Bits.SCISWAI\r
+#define SCI1CR1_LOOPS _SCI1CR1.Bits.LOOPS\r
+\r
+\r
+/*** SCI1CR2 - SCI 1 Control Register 2; 0x000000D3 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte SBK :1; /* Send Break Bit */\r
+ byte RWU :1; /* Receiver Wakeup Bit */\r
+ byte RE :1; /* Receiver Enable Bit */\r
+ byte TE :1; /* Transmitter Enable Bit */\r
+ byte ILIE :1; /* Idle Line Interrupt Enable Bit */\r
+ byte RIE :1; /* Receiver Full Interrupt Enable Bit */\r
+ byte TCIE :1; /* Transmission Complete Interrupt Enable Bit */\r
+ byte SCTIE :1; /* Transmitter Interrupt Enable Bit */\r
+ } Bits;\r
+} SCI1CR2STR;\r
+extern volatile SCI1CR2STR _SCI1CR2 @(REG_BASE + 0x000000D3);\r
+#define SCI1CR2 _SCI1CR2.Byte\r
+#define SCI1CR2_SBK _SCI1CR2.Bits.SBK\r
+#define SCI1CR2_RWU _SCI1CR2.Bits.RWU\r
+#define SCI1CR2_RE _SCI1CR2.Bits.RE\r
+#define SCI1CR2_TE _SCI1CR2.Bits.TE\r
+#define SCI1CR2_ILIE _SCI1CR2.Bits.ILIE\r
+#define SCI1CR2_RIE _SCI1CR2.Bits.RIE\r
+#define SCI1CR2_TCIE _SCI1CR2.Bits.TCIE\r
+#define SCI1CR2_SCTIE _SCI1CR2.Bits.SCTIE\r
+\r
+\r
+/*** SCI1SR1 - SCI 1 Status Register 1; 0x000000D4 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PF :1; /* Parity Error Flag */\r
+ byte FE :1; /* Framing Error Flag */\r
+ byte NF :1; /* Noise Flag */\r
+ byte OR :1; /* Overrun Flag */\r
+ byte IDLE :1; /* Idle Line Flag */\r
+ byte RDRF :1; /* Receive Data Register Full Flag */\r
+ byte TC :1; /* Transmit Complete Flag */\r
+ byte TDRE :1; /* Transmit Data Register Empty Flag */\r
+ } Bits;\r
+} SCI1SR1STR;\r
+extern volatile SCI1SR1STR _SCI1SR1 @(REG_BASE + 0x000000D4);\r
+#define SCI1SR1 _SCI1SR1.Byte\r
+#define SCI1SR1_PF _SCI1SR1.Bits.PF\r
+#define SCI1SR1_FE _SCI1SR1.Bits.FE\r
+#define SCI1SR1_NF _SCI1SR1.Bits.NF\r
+#define SCI1SR1_OR _SCI1SR1.Bits.OR\r
+#define SCI1SR1_IDLE _SCI1SR1.Bits.IDLE\r
+#define SCI1SR1_RDRF _SCI1SR1.Bits.RDRF\r
+#define SCI1SR1_TC _SCI1SR1.Bits.TC\r
+#define SCI1SR1_TDRE _SCI1SR1.Bits.TDRE\r
+\r
+\r
+/*** SCI1SR2 - SCI 1 Status Register 2; 0x000000D5 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte RAF :1; /* Receiver Active Flag */\r
+ byte TXDIR :1; /* Transmitter pin data direction in Single-Wire mode */\r
+ byte BRK13 :1; /* Break Transmit character length */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+} SCI1SR2STR;\r
+extern volatile SCI1SR2STR _SCI1SR2 @(REG_BASE + 0x000000D5);\r
+#define SCI1SR2 _SCI1SR2.Byte\r
+#define SCI1SR2_RAF _SCI1SR2.Bits.RAF\r
+#define SCI1SR2_TXDIR _SCI1SR2.Bits.TXDIR\r
+#define SCI1SR2_BRK13 _SCI1SR2.Bits.BRK13\r
+\r
+\r
+/*** SCI1DRH - SCI 1 Data Register High; 0x000000D6 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte T8 :1; /* Transmit Bit 8 */\r
+ byte R8 :1; /* Received Bit 8 */\r
+ } Bits;\r
+} SCI1DRHSTR;\r
+extern volatile SCI1DRHSTR _SCI1DRH @(REG_BASE + 0x000000D6);\r
+#define SCI1DRH _SCI1DRH.Byte\r
+#define SCI1DRH_T8 _SCI1DRH.Bits.T8\r
+#define SCI1DRH_R8 _SCI1DRH.Bits.R8\r
+\r
+\r
+/*** SCI1DRL - SCI 1 Data Register Low; 0x000000D7 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte R0_T0 :1; /* Received bit 0 or Transmit bit 0 */\r
+ byte R1_T1 :1; /* Received bit 1 or Transmit bit 1 */\r
+ byte R2_T2 :1; /* Received bit 2 or Transmit bit 2 */\r
+ byte R3_T3 :1; /* Received bit 3 or Transmit bit 3 */\r
+ byte R4_T4 :1; /* Received bit 4 or Transmit bit 4 */\r
+ byte R5_T5 :1; /* Received bit 5 or Transmit bit 5 */\r
+ byte R6_T6 :1; /* Received bit 6 or Transmit bit 6 */\r
+ byte R7_T7 :1; /* Received bit 7 or Transmit bit 7 */\r
+ } Bits;\r
+} SCI1DRLSTR;\r
+extern volatile SCI1DRLSTR _SCI1DRL @(REG_BASE + 0x000000D7);\r
+#define SCI1DRL _SCI1DRL.Byte\r
+#define SCI1DRL_R0_T0 _SCI1DRL.Bits.R0_T0\r
+#define SCI1DRL_R1_T1 _SCI1DRL.Bits.R1_T1\r
+#define SCI1DRL_R2_T2 _SCI1DRL.Bits.R2_T2\r
+#define SCI1DRL_R3_T3 _SCI1DRL.Bits.R3_T3\r
+#define SCI1DRL_R4_T4 _SCI1DRL.Bits.R4_T4\r
+#define SCI1DRL_R5_T5 _SCI1DRL.Bits.R5_T5\r
+#define SCI1DRL_R6_T6 _SCI1DRL.Bits.R6_T6\r
+#define SCI1DRL_R7_T7 _SCI1DRL.Bits.R7_T7\r
+\r
+\r
+/*** SPI0CR1 - SPI 0 Control Register; 0x000000D8 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte LSBFE :1; /* SPI 0 LSB-First Enable */\r
+ byte SSOE :1; /* Slave Select Output Enable */\r
+ byte CPHA :1; /* SPI 0 Clock Phase Bit */\r
+ byte CPOL :1; /* SPI 0 Clock Polarity Bit */\r
+ byte MSTR :1; /* SPI 0 Master/Slave Mode Select Bit */\r
+ byte SPTIE :1; /* SPI 0 Transmit Interrupt Enable */\r
+ byte SPE :1; /* SPI 0 System Enable Bit */\r
+ byte SPIE :1; /* SPI 0 Interrupt Enable Bit */\r
+ } Bits;\r
+} SPI0CR1STR;\r
+extern volatile SPI0CR1STR _SPI0CR1 @(REG_BASE + 0x000000D8);\r
+#define SPI0CR1 _SPI0CR1.Byte\r
+#define SPI0CR1_LSBFE _SPI0CR1.Bits.LSBFE\r
+#define SPI0CR1_SSOE _SPI0CR1.Bits.SSOE\r
+#define SPI0CR1_CPHA _SPI0CR1.Bits.CPHA\r
+#define SPI0CR1_CPOL _SPI0CR1.Bits.CPOL\r
+#define SPI0CR1_MSTR _SPI0CR1.Bits.MSTR\r
+#define SPI0CR1_SPTIE _SPI0CR1.Bits.SPTIE\r
+#define SPI0CR1_SPE _SPI0CR1.Bits.SPE\r
+#define SPI0CR1_SPIE _SPI0CR1.Bits.SPIE\r
+\r
+\r
+/*** SPI0CR2 - SPI 0 Control Register 2; 0x000000D9 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte SPC0 :1; /* Serial Pin Control Bit 0 */\r
+ byte SPISWAI :1; /* SPI 0 Stop in Wait Mode Bit */\r
+ byte :1; \r
+ byte BIDIROE :1; /* Output enable in the Bidirectional mode of operation */\r
+ byte MODFEN :1; /* Mode Fault Enable Bit */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+} SPI0CR2STR;\r
+extern volatile SPI0CR2STR _SPI0CR2 @(REG_BASE + 0x000000D9);\r
+#define SPI0CR2 _SPI0CR2.Byte\r
+#define SPI0CR2_SPC0 _SPI0CR2.Bits.SPC0\r
+#define SPI0CR2_SPISWAI _SPI0CR2.Bits.SPISWAI\r
+#define SPI0CR2_BIDIROE _SPI0CR2.Bits.BIDIROE\r
+#define SPI0CR2_MODFEN _SPI0CR2.Bits.MODFEN\r
+\r
+\r
+/*** SPI0BR - SPI 0 Baud Rate Register; 0x000000DA ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte SPR0 :1; /* SPI 0 Baud Rate Selection Bit 0 */\r
+ byte SPR1 :1; /* SPI 0 Baud Rate Selection Bit 1 */\r
+ byte SPR2 :1; /* SPI 0 Baud Rate Selection Bit 2 */\r
+ byte :1; \r
+ byte SPPR0 :1; /* SPI 0 Baud Rate Preselection Bits 0 */\r
+ byte SPPR1 :1; /* SPI 0 Baud Rate Preselection Bits 1 */\r
+ byte SPPR2 :1; /* SPI 0 Baud Rate Preselection Bits 2 */\r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpSPR :3;\r
+ byte :1;\r
+ byte grpSPPR :3;\r
+ byte :1;\r
+ } MergedBits;\r
+} SPI0BRSTR;\r
+extern volatile SPI0BRSTR _SPI0BR @(REG_BASE + 0x000000DA);\r
+#define SPI0BR _SPI0BR.Byte\r
+#define SPI0BR_SPR0 _SPI0BR.Bits.SPR0\r
+#define SPI0BR_SPR1 _SPI0BR.Bits.SPR1\r
+#define SPI0BR_SPR2 _SPI0BR.Bits.SPR2\r
+#define SPI0BR_SPPR0 _SPI0BR.Bits.SPPR0\r
+#define SPI0BR_SPPR1 _SPI0BR.Bits.SPPR1\r
+#define SPI0BR_SPPR2 _SPI0BR.Bits.SPPR2\r
+#define SPI0BR_SPR _SPI0BR.MergedBits.grpSPR\r
+#define SPI0BR_SPPR _SPI0BR.MergedBits.grpSPPR\r
+\r
+\r
+/*** SPI0SR - SPI 0 Status Register; 0x000000DB ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte MODF :1; /* Mode Fault Flag */\r
+ byte SPTEF :1; /* SPI 0 Transmit Empty Interrupt Flag */\r
+ byte :1; \r
+ byte SPIF :1; /* SPIF Receive Interrupt Flag */\r
+ } Bits;\r
+} SPI0SRSTR;\r
+extern volatile SPI0SRSTR _SPI0SR @(REG_BASE + 0x000000DB);\r
+#define SPI0SR _SPI0SR.Byte\r
+#define SPI0SR_MODF _SPI0SR.Bits.MODF\r
+#define SPI0SR_SPTEF _SPI0SR.Bits.SPTEF\r
+#define SPI0SR_SPIF _SPI0SR.Bits.SPIF\r
+\r
+\r
+/*** SPI0DR - SPI 0 Data Register; 0x000000DD ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+} SPI0DRSTR;\r
+extern volatile SPI0DRSTR _SPI0DR @(REG_BASE + 0x000000DD);\r
+#define SPI0DR _SPI0DR.Byte\r
+#define SPI0DR_BIT _SPI0DR.MergedBits.grpBIT\r
+\r
+\r
+/*** IBAD - IIC Address Register; 0x000000E0 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte ADR1 :1; /* Slave Address Bit 1 */\r
+ byte ADR2 :1; /* Slave Address Bit 2 */\r
+ byte ADR3 :1; /* Slave Address Bit 3 */\r
+ byte ADR4 :1; /* Slave Address Bit 4 */\r
+ byte ADR5 :1; /* Slave Address Bit 5 */\r
+ byte ADR6 :1; /* Slave Address Bit 6 */\r
+ byte ADR7 :1; /* Slave Address Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte grpADR_1 :7;\r
+ } MergedBits;\r
+} IBADSTR;\r
+extern volatile IBADSTR _IBAD @(REG_BASE + 0x000000E0);\r
+#define IBAD _IBAD.Byte\r
+#define IBAD_ADR1 _IBAD.Bits.ADR1\r
+#define IBAD_ADR2 _IBAD.Bits.ADR2\r
+#define IBAD_ADR3 _IBAD.Bits.ADR3\r
+#define IBAD_ADR4 _IBAD.Bits.ADR4\r
+#define IBAD_ADR5 _IBAD.Bits.ADR5\r
+#define IBAD_ADR6 _IBAD.Bits.ADR6\r
+#define IBAD_ADR7 _IBAD.Bits.ADR7\r
+#define IBAD_ADR_1 _IBAD.MergedBits.grpADR_1\r
+#define IBAD_ADR IBAD_ADR_1\r
+\r
+\r
+/*** IBFD - IIC Frequency Divider Register; 0x000000E1 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte IBC0 :1; /* I-Bus Clock Rate 0 */\r
+ byte IBC1 :1; /* I-Bus Clock Rate 1 */\r
+ byte IBC2 :1; /* I-Bus Clock Rate 2 */\r
+ byte IBC3 :1; /* I-Bus Clock Rate 3 */\r
+ byte IBC4 :1; /* I-Bus Clock Rate 4 */\r
+ byte IBC5 :1; /* I-Bus Clock Rate 5 */\r
+ byte IBC6 :1; /* I-Bus Clock Rate 6 */\r
+ byte IBC7 :1; /* I-Bus Clock Rate 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpIBC :8;\r
+ } MergedBits;\r
+} IBFDSTR;\r
+extern volatile IBFDSTR _IBFD @(REG_BASE + 0x000000E1);\r
+#define IBFD _IBFD.Byte\r
+#define IBFD_IBC0 _IBFD.Bits.IBC0\r
+#define IBFD_IBC1 _IBFD.Bits.IBC1\r
+#define IBFD_IBC2 _IBFD.Bits.IBC2\r
+#define IBFD_IBC3 _IBFD.Bits.IBC3\r
+#define IBFD_IBC4 _IBFD.Bits.IBC4\r
+#define IBFD_IBC5 _IBFD.Bits.IBC5\r
+#define IBFD_IBC6 _IBFD.Bits.IBC6\r
+#define IBFD_IBC7 _IBFD.Bits.IBC7\r
+#define IBFD_IBC _IBFD.MergedBits.grpIBC\r
+\r
+\r
+/*** IBCR - IIC Control Register; 0x000000E2 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte IBSWAI :1; /* I-Bus Interface Stop in WAIT mode */\r
+ byte :1; \r
+ byte RSTA :1; /* Repeat Start */\r
+ byte TXAK :1; /* Transmit Acknowledge enable */\r
+ byte TX_RX :1; /* Transmit/Receive mode select bit */\r
+ byte MS_SL :1; /* Master/Slave mode select bit */\r
+ byte IBIE :1; /* I-Bus Interrupt Enable */\r
+ byte IBEN :1; /* I-Bus Enable */\r
+ } Bits;\r
+} IBCRSTR;\r
+extern volatile IBCRSTR _IBCR @(REG_BASE + 0x000000E2);\r
+#define IBCR _IBCR.Byte\r
+#define IBCR_IBSWAI _IBCR.Bits.IBSWAI\r
+#define IBCR_RSTA _IBCR.Bits.RSTA\r
+#define IBCR_TXAK _IBCR.Bits.TXAK\r
+#define IBCR_TX_RX _IBCR.Bits.TX_RX\r
+#define IBCR_MS_SL _IBCR.Bits.MS_SL\r
+#define IBCR_IBIE _IBCR.Bits.IBIE\r
+#define IBCR_IBEN _IBCR.Bits.IBEN\r
+\r
+\r
+/*** IBSR - IIC Status Register; 0x000000E3 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte RXAK :1; /* Received Acknowledge */\r
+ byte IBIF :1; /* I-Bus Interrupt */\r
+ byte SRW :1; /* Slave Read/Write */\r
+ byte :1; \r
+ byte IBAL :1; /* Arbitration Lost */\r
+ byte IBB :1; /* Bus busy bit */\r
+ byte IAAS :1; /* Addressed as a slave bit */\r
+ byte TCF :1; /* Data transferring bit */\r
+ } Bits;\r
+} IBSRSTR;\r
+extern volatile IBSRSTR _IBSR @(REG_BASE + 0x000000E3);\r
+#define IBSR _IBSR.Byte\r
+#define IBSR_RXAK _IBSR.Bits.RXAK\r
+#define IBSR_IBIF _IBSR.Bits.IBIF\r
+#define IBSR_SRW _IBSR.Bits.SRW\r
+#define IBSR_IBAL _IBSR.Bits.IBAL\r
+#define IBSR_IBB _IBSR.Bits.IBB\r
+#define IBSR_IAAS _IBSR.Bits.IAAS\r
+#define IBSR_TCF _IBSR.Bits.TCF\r
+\r
+\r
+/*** IBDR - IIC Data I/O Register; 0x000000E4 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte D0 :1; /* IIC Data Bit 0 */\r
+ byte D1 :1; /* IIC Data Bit 1 */\r
+ byte D2 :1; /* IIC Data Bit 2 */\r
+ byte D3 :1; /* IIC Data Bit 3 */\r
+ byte D4 :1; /* IIC Data Bit 4 */\r
+ byte D5 :1; /* IIC Data Bit 5 */\r
+ byte D6 :1; /* IIC Data Bit 6 */\r
+ byte D7 :1; /* IIC Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpD :8;\r
+ } MergedBits;\r
+} IBDRSTR;\r
+extern volatile IBDRSTR _IBDR @(REG_BASE + 0x000000E4);\r
+#define IBDR _IBDR.Byte\r
+#define IBDR_D0 _IBDR.Bits.D0\r
+#define IBDR_D1 _IBDR.Bits.D1\r
+#define IBDR_D2 _IBDR.Bits.D2\r
+#define IBDR_D3 _IBDR.Bits.D3\r
+#define IBDR_D4 _IBDR.Bits.D4\r
+#define IBDR_D5 _IBDR.Bits.D5\r
+#define IBDR_D6 _IBDR.Bits.D6\r
+#define IBDR_D7 _IBDR.Bits.D7\r
+#define IBDR_D _IBDR.MergedBits.grpD\r
+\r
+\r
+/*** DLCBCR1 - BDLC Control Register 1; 0x000000E8 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte WCM :1; /* Wait Clock Mode */\r
+ byte IE :1; /* Interrupt Enable */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte CLKS :1; /* Clock Select */\r
+ byte IMSG :1; /* Ignore Message */\r
+ } Bits;\r
+} DLCBCR1STR;\r
+extern volatile DLCBCR1STR _DLCBCR1 @(REG_BASE + 0x000000E8);\r
+#define DLCBCR1 _DLCBCR1.Byte\r
+#define DLCBCR1_WCM _DLCBCR1.Bits.WCM\r
+#define DLCBCR1_IE _DLCBCR1.Bits.IE\r
+#define DLCBCR1_CLKS _DLCBCR1.Bits.CLKS\r
+#define DLCBCR1_IMSG _DLCBCR1.Bits.IMSG\r
+\r
+\r
+/*** DLCBSVR - BDLC State Vector Register; 0x000000E9 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte I0 :1; /* Interrupt State Vector Bit 0 */\r
+ byte I1 :1; /* Interrupt State Vector Bit 1 */\r
+ byte I2 :1; /* Interrupt State Vector Bit 2 */\r
+ byte I3 :1; /* Interrupt State Vector Bit 3 */\r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte grpI :4;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} DLCBSVRSTR;\r
+extern volatile DLCBSVRSTR _DLCBSVR @(REG_BASE + 0x000000E9);\r
+#define DLCBSVR _DLCBSVR.Byte\r
+#define DLCBSVR_I0 _DLCBSVR.Bits.I0\r
+#define DLCBSVR_I1 _DLCBSVR.Bits.I1\r
+#define DLCBSVR_I2 _DLCBSVR.Bits.I2\r
+#define DLCBSVR_I3 _DLCBSVR.Bits.I3\r
+#define DLCBSVR_I _DLCBSVR.MergedBits.grpI\r
+\r
+\r
+/*** DLCBCR2 - BDLC Control Register 2; 0x000000EA ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte TMIFR0 :1; /* Transmit In-Frame Response Control 0 */\r
+ byte TMIFR1 :1; /* Transmit In-Frame Response Control 1 */\r
+ byte TSIFR :1; /* Transmit In-Frame Response Control 2 */\r
+ byte TEOD :1; /* Transmit End of Data */\r
+ byte NBFS :1; /* Normalization Bit Format Select */\r
+ byte RX4XE :1; /* Receive 4X Enable */\r
+ byte DLOOP :1; /* Digital Loopback Mode */\r
+ byte SMRST :1; /* State Machine Reset */\r
+ } Bits;\r
+ struct {\r
+ byte grpTMIFR :2;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} DLCBCR2STR;\r
+extern volatile DLCBCR2STR _DLCBCR2 @(REG_BASE + 0x000000EA);\r
+#define DLCBCR2 _DLCBCR2.Byte\r
+#define DLCBCR2_TMIFR0 _DLCBCR2.Bits.TMIFR0\r
+#define DLCBCR2_TMIFR1 _DLCBCR2.Bits.TMIFR1\r
+#define DLCBCR2_TSIFR _DLCBCR2.Bits.TSIFR\r
+#define DLCBCR2_TEOD _DLCBCR2.Bits.TEOD\r
+#define DLCBCR2_NBFS _DLCBCR2.Bits.NBFS\r
+#define DLCBCR2_RX4XE _DLCBCR2.Bits.RX4XE\r
+#define DLCBCR2_DLOOP _DLCBCR2.Bits.DLOOP\r
+#define DLCBCR2_SMRST _DLCBCR2.Bits.SMRST\r
+#define DLCBCR2_TMIFR _DLCBCR2.MergedBits.grpTMIFR\r
+\r
+\r
+/*** DLCBDR - BDLC Data Register; 0x000000EB ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte D0 :1; /* Receive/Transmit Data Bit 0 */\r
+ byte D1 :1; /* Receive/Transmit Data Bit 1 */\r
+ byte D2 :1; /* Receive/Transmit Data Bit 2 */\r
+ byte D3 :1; /* Receive/Transmit Data Bit 3 */\r
+ byte D4 :1; /* Receive/Transmit Data Bit 4 */\r
+ byte D5 :1; /* Receive/Transmit Data Bit 5 */\r
+ byte D6 :1; /* Receive/Transmit Data Bit 6 */\r
+ byte D7 :1; /* Receive/Transmit Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpD :8;\r
+ } MergedBits;\r
+} DLCBDRSTR;\r
+extern volatile DLCBDRSTR _DLCBDR @(REG_BASE + 0x000000EB);\r
+#define DLCBDR _DLCBDR.Byte\r
+#define DLCBDR_D0 _DLCBDR.Bits.D0\r
+#define DLCBDR_D1 _DLCBDR.Bits.D1\r
+#define DLCBDR_D2 _DLCBDR.Bits.D2\r
+#define DLCBDR_D3 _DLCBDR.Bits.D3\r
+#define DLCBDR_D4 _DLCBDR.Bits.D4\r
+#define DLCBDR_D5 _DLCBDR.Bits.D5\r
+#define DLCBDR_D6 _DLCBDR.Bits.D6\r
+#define DLCBDR_D7 _DLCBDR.Bits.D7\r
+#define DLCBDR_D _DLCBDR.MergedBits.grpD\r
+\r
+\r
+/*** DLCBARD - BDLC Analog Round Trip Delay Register; 0x000000EC ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte BO0 :1; /* BDLC Analog Roundtrip Delay Offset Field 0 */\r
+ byte BO1 :1; /* BDLC Analog Roundtrip Delay Offset Field 1 */\r
+ byte BO2 :1; /* BDLC Analog Roundtrip Delay Offset Field 2 */\r
+ byte BO3 :1; /* BDLC Analog Roundtrip Delay Offset Field 3 */\r
+ byte :1; \r
+ byte :1; \r
+ byte RXPOL :1; /* Receive Pin Polarity */\r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpBO :4;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} DLCBARDSTR;\r
+extern volatile DLCBARDSTR _DLCBARD @(REG_BASE + 0x000000EC);\r
+#define DLCBARD _DLCBARD.Byte\r
+#define DLCBARD_BO0 _DLCBARD.Bits.BO0\r
+#define DLCBARD_BO1 _DLCBARD.Bits.BO1\r
+#define DLCBARD_BO2 _DLCBARD.Bits.BO2\r
+#define DLCBARD_BO3 _DLCBARD.Bits.BO3\r
+#define DLCBARD_RXPOL _DLCBARD.Bits.RXPOL\r
+#define DLCBARD_BO _DLCBARD.MergedBits.grpBO\r
+\r
+\r
+/*** DLCBRSR - BDLC Rate Select Register; 0x000000ED ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte R0 :1; /* Rate Select 0 */\r
+ byte R1 :1; /* Rate Select 1 */\r
+ byte R2 :1; /* Rate Select 2 */\r
+ byte R3 :1; /* Rate Select 3 */\r
+ byte R4 :1; /* Rate Select 4 */\r
+ byte R5 :1; /* Rate Select 5 */\r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpR :6;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} DLCBRSRSTR;\r
+extern volatile DLCBRSRSTR _DLCBRSR @(REG_BASE + 0x000000ED);\r
+#define DLCBRSR _DLCBRSR.Byte\r
+#define DLCBRSR_R0 _DLCBRSR.Bits.R0\r
+#define DLCBRSR_R1 _DLCBRSR.Bits.R1\r
+#define DLCBRSR_R2 _DLCBRSR.Bits.R2\r
+#define DLCBRSR_R3 _DLCBRSR.Bits.R3\r
+#define DLCBRSR_R4 _DLCBRSR.Bits.R4\r
+#define DLCBRSR_R5 _DLCBRSR.Bits.R5\r
+#define DLCBRSR_R _DLCBRSR.MergedBits.grpR\r
+\r
+\r
+/*** DLCSCR - BDLC Control Register; 0x000000EE ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte BDLCE :1; /* BDLC Enable */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+} DLCSCRSTR;\r
+extern volatile DLCSCRSTR _DLCSCR @(REG_BASE + 0x000000EE);\r
+#define DLCSCR _DLCSCR.Byte\r
+#define DLCSCR_BDLCE _DLCSCR.Bits.BDLCE\r
+\r
+\r
+/*** SPI1CR1 - SPI 1 Control Register; 0x000000F0 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte LSBFE :1; /* SPI 1 LSB-First Enable */\r
+ byte SSOE :1; /* Slave Select Output Enable */\r
+ byte CPHA :1; /* SPI 1 Clock Phase Bit */\r
+ byte CPOL :1; /* SPI 1 Clock Polarity Bit */\r
+ byte MSTR :1; /* SPI 1 Master/Slave Mode Select Bit */\r
+ byte SPTIE :1; /* SPI 1 Transmit Interrupt Enable */\r
+ byte SPE :1; /* SPI 1 System Enable Bit */\r
+ byte SPIE :1; /* SPI 1 Interrupt Enable Bit */\r
+ } Bits;\r
+} SPI1CR1STR;\r
+extern volatile SPI1CR1STR _SPI1CR1 @(REG_BASE + 0x000000F0);\r
+#define SPI1CR1 _SPI1CR1.Byte\r
+#define SPI1CR1_LSBFE _SPI1CR1.Bits.LSBFE\r
+#define SPI1CR1_SSOE _SPI1CR1.Bits.SSOE\r
+#define SPI1CR1_CPHA _SPI1CR1.Bits.CPHA\r
+#define SPI1CR1_CPOL _SPI1CR1.Bits.CPOL\r
+#define SPI1CR1_MSTR _SPI1CR1.Bits.MSTR\r
+#define SPI1CR1_SPTIE _SPI1CR1.Bits.SPTIE\r
+#define SPI1CR1_SPE _SPI1CR1.Bits.SPE\r
+#define SPI1CR1_SPIE _SPI1CR1.Bits.SPIE\r
+\r
+\r
+/*** SPI1CR2 - SPI 1 Control Register 2; 0x000000F1 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte SPC0 :1; /* Serial Pin Control Bit 0 */\r
+ byte SPISWAI :1; /* SPI 1 Stop in Wait Mode Bit */\r
+ byte :1; \r
+ byte BIDIROE :1; /* Output enable in the Bidirectional mode of operation */\r
+ byte MODFEN :1; /* Mode Fault Enable Bit */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+} SPI1CR2STR;\r
+extern volatile SPI1CR2STR _SPI1CR2 @(REG_BASE + 0x000000F1);\r
+#define SPI1CR2 _SPI1CR2.Byte\r
+#define SPI1CR2_SPC0 _SPI1CR2.Bits.SPC0\r
+#define SPI1CR2_SPISWAI _SPI1CR2.Bits.SPISWAI\r
+#define SPI1CR2_BIDIROE _SPI1CR2.Bits.BIDIROE\r
+#define SPI1CR2_MODFEN _SPI1CR2.Bits.MODFEN\r
+\r
+\r
+/*** SPI1BR - SPI 1 Baud Rate Register; 0x000000F2 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte SPR0 :1; /* SPI 1 Baud Rate Selection Bit 0 */\r
+ byte SPR1 :1; /* SPI 1 Baud Rate Selection Bit 1 */\r
+ byte SPR2 :1; /* SPI 1 Baud Rate Selection Bit 2 */\r
+ byte :1; \r
+ byte SPPR0 :1; /* SPI 1 Baud Rate Preselection Bits 0 */\r
+ byte SPPR1 :1; /* SPI 1 Baud Rate Preselection Bits 1 */\r
+ byte SPPR2 :1; /* SPI 1 Baud Rate Preselection Bits 2 */\r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpSPR :3;\r
+ byte :1;\r
+ byte grpSPPR :3;\r
+ byte :1;\r
+ } MergedBits;\r
+} SPI1BRSTR;\r
+extern volatile SPI1BRSTR _SPI1BR @(REG_BASE + 0x000000F2);\r
+#define SPI1BR _SPI1BR.Byte\r
+#define SPI1BR_SPR0 _SPI1BR.Bits.SPR0\r
+#define SPI1BR_SPR1 _SPI1BR.Bits.SPR1\r
+#define SPI1BR_SPR2 _SPI1BR.Bits.SPR2\r
+#define SPI1BR_SPPR0 _SPI1BR.Bits.SPPR0\r
+#define SPI1BR_SPPR1 _SPI1BR.Bits.SPPR1\r
+#define SPI1BR_SPPR2 _SPI1BR.Bits.SPPR2\r
+#define SPI1BR_SPR _SPI1BR.MergedBits.grpSPR\r
+#define SPI1BR_SPPR _SPI1BR.MergedBits.grpSPPR\r
+\r
+\r
+/*** SPI1SR - SPI 1 Status Register; 0x000000F3 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte MODF :1; /* Mode Fault Flag */\r
+ byte SPTEF :1; /* SPI 1 Transmit Empty Interrupt Flag */\r
+ byte :1; \r
+ byte SPIF :1; /* SPIF Receive Interrupt Flag */\r
+ } Bits;\r
+} SPI1SRSTR;\r
+extern volatile SPI1SRSTR _SPI1SR @(REG_BASE + 0x000000F3);\r
+#define SPI1SR _SPI1SR.Byte\r
+#define SPI1SR_MODF _SPI1SR.Bits.MODF\r
+#define SPI1SR_SPTEF _SPI1SR.Bits.SPTEF\r
+#define SPI1SR_SPIF _SPI1SR.Bits.SPIF\r
+\r
+\r
+/*** SPI1DR - SPI 1 Data Register; 0x000000F5 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+} SPI1DRSTR;\r
+extern volatile SPI1DRSTR _SPI1DR @(REG_BASE + 0x000000F5);\r
+#define SPI1DR _SPI1DR.Byte\r
+#define SPI1DR_BIT _SPI1DR.MergedBits.grpBIT\r
+\r
+\r
+/*** SPI2CR1 - SPI 2 Control Register; 0x000000F8 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte LSBFE :1; /* SPI 2 LSB-First Enable */\r
+ byte SSOE :1; /* Slave Select Output Enable */\r
+ byte CPHA :1; /* SPI 2 Clock Phase Bit */\r
+ byte CPOL :1; /* SPI 2 Clock Polarity Bit */\r
+ byte MSTR :1; /* SPI 2 Master/Slave Mode Select Bit */\r
+ byte SPTIE :1; /* SPI 2 Transmit Interrupt Enable */\r
+ byte SPE :1; /* SPI 2 System Enable Bit */\r
+ byte SPIE :1; /* SPI 2 Interrupt Enable Bit */\r
+ } Bits;\r
+} SPI2CR1STR;\r
+extern volatile SPI2CR1STR _SPI2CR1 @(REG_BASE + 0x000000F8);\r
+#define SPI2CR1 _SPI2CR1.Byte\r
+#define SPI2CR1_LSBFE _SPI2CR1.Bits.LSBFE\r
+#define SPI2CR1_SSOE _SPI2CR1.Bits.SSOE\r
+#define SPI2CR1_CPHA _SPI2CR1.Bits.CPHA\r
+#define SPI2CR1_CPOL _SPI2CR1.Bits.CPOL\r
+#define SPI2CR1_MSTR _SPI2CR1.Bits.MSTR\r
+#define SPI2CR1_SPTIE _SPI2CR1.Bits.SPTIE\r
+#define SPI2CR1_SPE _SPI2CR1.Bits.SPE\r
+#define SPI2CR1_SPIE _SPI2CR1.Bits.SPIE\r
+\r
+\r
+/*** SPI2CR2 - SPI 2 Control Register 2; 0x000000F9 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte SPC0 :1; /* Serial Pin Control Bit 0 */\r
+ byte SPISWAI :1; /* SPI 2 Stop in Wait Mode Bit */\r
+ byte :1; \r
+ byte BIDIROE :1; /* Output enable in the Bidirectional mode of operation */\r
+ byte MODFEN :1; /* Mode Fault Enable Bit */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+} SPI2CR2STR;\r
+extern volatile SPI2CR2STR _SPI2CR2 @(REG_BASE + 0x000000F9);\r
+#define SPI2CR2 _SPI2CR2.Byte\r
+#define SPI2CR2_SPC0 _SPI2CR2.Bits.SPC0\r
+#define SPI2CR2_SPISWAI _SPI2CR2.Bits.SPISWAI\r
+#define SPI2CR2_BIDIROE _SPI2CR2.Bits.BIDIROE\r
+#define SPI2CR2_MODFEN _SPI2CR2.Bits.MODFEN\r
+\r
+\r
+/*** SPI2BR - SPI 2 Baud Rate Register; 0x000000FA ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte SPR0 :1; /* SPI 2 Baud Rate Selection Bit 0 */\r
+ byte SPR1 :1; /* SPI 2 Baud Rate Selection Bit 1 */\r
+ byte SPR2 :1; /* SPI 2 Baud Rate Selection Bit 2 */\r
+ byte :1; \r
+ byte SPPR0 :1; /* SPI 2 Baud Rate Preselection Bits 0 */\r
+ byte SPPR1 :1; /* SPI 2 Baud Rate Preselection Bits 1 */\r
+ byte SPPR2 :1; /* SPI 2 Baud Rate Preselection Bits 2 */\r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpSPR :3;\r
+ byte :1;\r
+ byte grpSPPR :3;\r
+ byte :1;\r
+ } MergedBits;\r
+} SPI2BRSTR;\r
+extern volatile SPI2BRSTR _SPI2BR @(REG_BASE + 0x000000FA);\r
+#define SPI2BR _SPI2BR.Byte\r
+#define SPI2BR_SPR0 _SPI2BR.Bits.SPR0\r
+#define SPI2BR_SPR1 _SPI2BR.Bits.SPR1\r
+#define SPI2BR_SPR2 _SPI2BR.Bits.SPR2\r
+#define SPI2BR_SPPR0 _SPI2BR.Bits.SPPR0\r
+#define SPI2BR_SPPR1 _SPI2BR.Bits.SPPR1\r
+#define SPI2BR_SPPR2 _SPI2BR.Bits.SPPR2\r
+#define SPI2BR_SPR _SPI2BR.MergedBits.grpSPR\r
+#define SPI2BR_SPPR _SPI2BR.MergedBits.grpSPPR\r
+\r
+\r
+/*** SPI2SR - SPI 2 Status Register; 0x000000FB ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte MODF :1; /* Mode Fault Flag */\r
+ byte SPTEF :1; /* SPI 2 Transmit Empty Interrupt Flag */\r
+ byte :1; \r
+ byte SPIF :1; /* SPIF Receive Interrupt Flag */\r
+ } Bits;\r
+} SPI2SRSTR;\r
+extern volatile SPI2SRSTR _SPI2SR @(REG_BASE + 0x000000FB);\r
+#define SPI2SR _SPI2SR.Byte\r
+#define SPI2SR_MODF _SPI2SR.Bits.MODF\r
+#define SPI2SR_SPTEF _SPI2SR.Bits.SPTEF\r
+#define SPI2SR_SPIF _SPI2SR.Bits.SPIF\r
+\r
+\r
+/*** SPI2DR - SPI 2 Data Register; 0x000000FD ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+} SPI2DRSTR;\r
+extern volatile SPI2DRSTR _SPI2DR @(REG_BASE + 0x000000FD);\r
+#define SPI2DR _SPI2DR.Byte\r
+#define SPI2DR_BIT _SPI2DR.MergedBits.grpBIT\r
+\r
+\r
+/*** FCLKDIV - Flash Clock Divider Register; 0x00000100 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte FDIV0 :1; /* Flash Clock Divider Bit 0 */\r
+ byte FDIV1 :1; /* Flash Clock Divider Bit 1 */\r
+ byte FDIV2 :1; /* Flash Clock Divider Bit 2 */\r
+ byte FDIV3 :1; /* Flash Clock Divider Bit 3 */\r
+ byte FDIV4 :1; /* Flash Clock Divider Bit 4 */\r
+ byte FDIV5 :1; /* Flash Clock Divider Bit 5 */\r
+ byte PRDIV8 :1; /* Enable Prescaler by 8 */\r
+ byte FDIVLD :1; /* Flash Clock Divider Loaded */\r
+ } Bits;\r
+ struct {\r
+ byte grpFDIV :6;\r
+ byte grpPRDIV_8 :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} FCLKDIVSTR;\r
+extern volatile FCLKDIVSTR _FCLKDIV @(REG_BASE + 0x00000100);\r
+#define FCLKDIV _FCLKDIV.Byte\r
+#define FCLKDIV_FDIV0 _FCLKDIV.Bits.FDIV0\r
+#define FCLKDIV_FDIV1 _FCLKDIV.Bits.FDIV1\r
+#define FCLKDIV_FDIV2 _FCLKDIV.Bits.FDIV2\r
+#define FCLKDIV_FDIV3 _FCLKDIV.Bits.FDIV3\r
+#define FCLKDIV_FDIV4 _FCLKDIV.Bits.FDIV4\r
+#define FCLKDIV_FDIV5 _FCLKDIV.Bits.FDIV5\r
+#define FCLKDIV_PRDIV8 _FCLKDIV.Bits.PRDIV8\r
+#define FCLKDIV_FDIVLD _FCLKDIV.Bits.FDIVLD\r
+#define FCLKDIV_FDIV _FCLKDIV.MergedBits.grpFDIV\r
+\r
+\r
+/*** FSEC - Flash Security Register; 0x00000101 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte SEC0 :1; /* Memory security bit 0 */\r
+ byte SEC1 :1; /* Memory security bit 1 */\r
+ byte NV2 :1; /* Non Volatile flag bit 2 */\r
+ byte NV3 :1; /* Non Volatile flag bit 3 */\r
+ byte NV4 :1; /* Non Volatile flag bit 4 */\r
+ byte NV5 :1; /* Non Volatile flag bit 5 */\r
+ byte NV6 :1; /* Non Volatile flag bit 6 */\r
+ byte KEYEN :1; /* Enable backdoor key to security */\r
+ } Bits;\r
+ struct {\r
+ byte grpSEC :2;\r
+ byte grpNV_2 :5;\r
+ byte :1;\r
+ } MergedBits;\r
+} FSECSTR;\r
+extern volatile FSECSTR _FSEC @(REG_BASE + 0x00000101);\r
+#define FSEC _FSEC.Byte\r
+#define FSEC_SEC0 _FSEC.Bits.SEC0\r
+#define FSEC_SEC1 _FSEC.Bits.SEC1\r
+#define FSEC_NV2 _FSEC.Bits.NV2\r
+#define FSEC_NV3 _FSEC.Bits.NV3\r
+#define FSEC_NV4 _FSEC.Bits.NV4\r
+#define FSEC_NV5 _FSEC.Bits.NV5\r
+#define FSEC_NV6 _FSEC.Bits.NV6\r
+#define FSEC_KEYEN _FSEC.Bits.KEYEN\r
+#define FSEC_SEC _FSEC.MergedBits.grpSEC\r
+#define FSEC_NV_2 _FSEC.MergedBits.grpNV_2\r
+#define FSEC_NV FSEC_NV_2\r
+\r
+\r
+/*** FCNFG - Flash Configuration Register; 0x00000103 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte BKSEL0 :1; /* Register bank select 0 */\r
+ byte BKSEL1 :1; /* Register bank select 1 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte KEYACC :1; /* Enable Security Key Writing */\r
+ byte CCIE :1; /* Command Complete Interrupt Enable */\r
+ byte CBEIE :1; /* Command Buffers Empty Interrupt Enable */\r
+ } Bits;\r
+ struct {\r
+ byte grpBKSEL :2;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} FCNFGSTR;\r
+extern volatile FCNFGSTR _FCNFG @(REG_BASE + 0x00000103);\r
+#define FCNFG _FCNFG.Byte\r
+#define FCNFG_BKSEL0 _FCNFG.Bits.BKSEL0\r
+#define FCNFG_BKSEL1 _FCNFG.Bits.BKSEL1\r
+#define FCNFG_KEYACC _FCNFG.Bits.KEYACC\r
+#define FCNFG_CCIE _FCNFG.Bits.CCIE\r
+#define FCNFG_CBEIE _FCNFG.Bits.CBEIE\r
+#define FCNFG_BKSEL _FCNFG.MergedBits.grpBKSEL\r
+\r
+\r
+/*** FPROT - Flash Protection Register; 0x00000104 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte FPLS0 :1; /* Flash Protection Lower Address size 0 */\r
+ byte FPLS1 :1; /* Flash Protection Lower Address size 1 */\r
+ byte FPLDIS :1; /* Flash Protection Lower address range disable */\r
+ byte FPHS0 :1; /* Flash Protection Higher address size 0 */\r
+ byte FPHS1 :1; /* Flash Protection Higher address size 1 */\r
+ byte FPHDIS :1; /* Flash Protection Higher address range disable */\r
+ byte NV6 :1; /* Non Volatile Flag Bit */\r
+ byte FPOPEN :1; /* Opens the flash block or subsections of it for program or erase */\r
+ } Bits;\r
+ struct {\r
+ byte grpFPLS :2;\r
+ byte :1;\r
+ byte grpFPHS :2;\r
+ byte :1;\r
+ byte grpNV_6 :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} FPROTSTR;\r
+extern volatile FPROTSTR _FPROT @(REG_BASE + 0x00000104);\r
+#define FPROT _FPROT.Byte\r
+#define FPROT_FPLS0 _FPROT.Bits.FPLS0\r
+#define FPROT_FPLS1 _FPROT.Bits.FPLS1\r
+#define FPROT_FPLDIS _FPROT.Bits.FPLDIS\r
+#define FPROT_FPHS0 _FPROT.Bits.FPHS0\r
+#define FPROT_FPHS1 _FPROT.Bits.FPHS1\r
+#define FPROT_FPHDIS _FPROT.Bits.FPHDIS\r
+#define FPROT_NV6 _FPROT.Bits.NV6\r
+#define FPROT_FPOPEN _FPROT.Bits.FPOPEN\r
+#define FPROT_FPLS _FPROT.MergedBits.grpFPLS\r
+#define FPROT_FPHS _FPROT.MergedBits.grpFPHS\r
+\r
+\r
+/*** FSTAT - Flash Status Register; 0x00000105 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte BLANK :1; /* Blank Verify Flag */\r
+ byte :1; \r
+ byte ACCERR :1; /* Access error */\r
+ byte PVIOL :1; /* Protection violation */\r
+ byte CCIF :1; /* Command Complete Interrupt Flag */\r
+ byte CBEIF :1; /* Command Buffers Empty Interrupt Flag */\r
+ } Bits;\r
+} FSTATSTR;\r
+extern volatile FSTATSTR _FSTAT @(REG_BASE + 0x00000105);\r
+#define FSTAT _FSTAT.Byte\r
+#define FSTAT_BLANK _FSTAT.Bits.BLANK\r
+#define FSTAT_ACCERR _FSTAT.Bits.ACCERR\r
+#define FSTAT_PVIOL _FSTAT.Bits.PVIOL\r
+#define FSTAT_CCIF _FSTAT.Bits.CCIF\r
+#define FSTAT_CBEIF _FSTAT.Bits.CBEIF\r
+\r
+\r
+/*** FCMD - Flash Command Buffer and Register; 0x00000106 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte CMDB0 :1; /* NVM User Mode Command Bit 0 */\r
+ byte :1; \r
+ byte CMDB2 :1; /* NVM User Mode Command Bit 2 */\r
+ byte :1; \r
+ byte :1; \r
+ byte CMDB5 :1; /* NVM User Mode Command Bit 5 */\r
+ byte CMDB6 :1; /* NVM User Mode Command Bit 6 */\r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpCMDB :1;\r
+ byte :1;\r
+ byte grpCMDB_2 :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpCMDB_5 :2;\r
+ byte :1;\r
+ } MergedBits;\r
+} FCMDSTR;\r
+extern volatile FCMDSTR _FCMD @(REG_BASE + 0x00000106);\r
+#define FCMD _FCMD.Byte\r
+#define FCMD_CMDB0 _FCMD.Bits.CMDB0\r
+#define FCMD_CMDB2 _FCMD.Bits.CMDB2\r
+#define FCMD_CMDB5 _FCMD.Bits.CMDB5\r
+#define FCMD_CMDB6 _FCMD.Bits.CMDB6\r
+#define FCMD_CMDB_5 _FCMD.MergedBits.grpCMDB_5\r
+#define FCMD_CMDB FCMD_CMDB_5\r
+\r
+\r
+/*** ECLKDIV - EEPROM Clock Divider Register; 0x00000110 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte EDIV0 :1; /* EEPROM Clock Divider 0 */\r
+ byte EDIV1 :1; /* EEPROM Clock Divider 1 */\r
+ byte EDIV2 :1; /* EEPROM Clock Divider 2 */\r
+ byte EDIV3 :1; /* EEPROM Clock Divider 3 */\r
+ byte EDIV4 :1; /* EEPROM Clock Divider 4 */\r
+ byte EDIV5 :1; /* EEPROM Clock Divider 5 */\r
+ byte PRDIV8 :1; /* Enable Prescaler by 8 */\r
+ byte EDIVLD :1; /* EEPROM Clock Divider Loaded */\r
+ } Bits;\r
+ struct {\r
+ byte grpEDIV :6;\r
+ byte grpPRDIV_8 :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} ECLKDIVSTR;\r
+extern volatile ECLKDIVSTR _ECLKDIV @(REG_BASE + 0x00000110);\r
+#define ECLKDIV _ECLKDIV.Byte\r
+#define ECLKDIV_EDIV0 _ECLKDIV.Bits.EDIV0\r
+#define ECLKDIV_EDIV1 _ECLKDIV.Bits.EDIV1\r
+#define ECLKDIV_EDIV2 _ECLKDIV.Bits.EDIV2\r
+#define ECLKDIV_EDIV3 _ECLKDIV.Bits.EDIV3\r
+#define ECLKDIV_EDIV4 _ECLKDIV.Bits.EDIV4\r
+#define ECLKDIV_EDIV5 _ECLKDIV.Bits.EDIV5\r
+#define ECLKDIV_PRDIV8 _ECLKDIV.Bits.PRDIV8\r
+#define ECLKDIV_EDIVLD _ECLKDIV.Bits.EDIVLD\r
+#define ECLKDIV_EDIV _ECLKDIV.MergedBits.grpEDIV\r
+\r
+\r
+/*** ECNFG - EEPROM Configuration Register; 0x00000113 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte CCIE :1; /* Command Complete Interrupt Enable */\r
+ byte CBEIE :1; /* Command Buffers Empty Interrupt Enable */\r
+ } Bits;\r
+} ECNFGSTR;\r
+extern volatile ECNFGSTR _ECNFG @(REG_BASE + 0x00000113);\r
+#define ECNFG _ECNFG.Byte\r
+#define ECNFG_CCIE _ECNFG.Bits.CCIE\r
+#define ECNFG_CBEIE _ECNFG.Bits.CBEIE\r
+\r
+\r
+/*** EPROT - EEPROM Protection Register; 0x00000114 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte EP0 :1; /* EEPROM Protection address size 0 */\r
+ byte EP1 :1; /* EEPROM Protection address size 1 */\r
+ byte EP2 :1; /* EEPROM Protection address size 2 */\r
+ byte EPDIS :1; /* EEPROM Protection disable */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte EPOPEN :1; /* Opens the EEPROM block or a subsection of it for program or erase */\r
+ } Bits;\r
+ struct {\r
+ byte grpEP :3;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} EPROTSTR;\r
+extern volatile EPROTSTR _EPROT @(REG_BASE + 0x00000114);\r
+#define EPROT _EPROT.Byte\r
+#define EPROT_EP0 _EPROT.Bits.EP0\r
+#define EPROT_EP1 _EPROT.Bits.EP1\r
+#define EPROT_EP2 _EPROT.Bits.EP2\r
+#define EPROT_EPDIS _EPROT.Bits.EPDIS\r
+#define EPROT_EPOPEN _EPROT.Bits.EPOPEN\r
+#define EPROT_EP _EPROT.MergedBits.grpEP\r
+\r
+\r
+/*** ESTAT - EEPROM Status Register; 0x00000115 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte BLANK :1; /* Blank Verify Flag */\r
+ byte :1; \r
+ byte ACCERR :1; /* Access error */\r
+ byte PVIOL :1; /* Protection violation */\r
+ byte CCIF :1; /* Command Complete Interrupt Flag */\r
+ byte CBEIF :1; /* Command Buffer Empty Interrupt Flag */\r
+ } Bits;\r
+} ESTATSTR;\r
+extern volatile ESTATSTR _ESTAT @(REG_BASE + 0x00000115);\r
+#define ESTAT _ESTAT.Byte\r
+#define ESTAT_BLANK _ESTAT.Bits.BLANK\r
+#define ESTAT_ACCERR _ESTAT.Bits.ACCERR\r
+#define ESTAT_PVIOL _ESTAT.Bits.PVIOL\r
+#define ESTAT_CCIF _ESTAT.Bits.CCIF\r
+#define ESTAT_CBEIF _ESTAT.Bits.CBEIF\r
+\r
+\r
+/*** ECMD - EEPROM Command Buffer and Register; 0x00000116 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte CMDB0 :1; /* EEPROM User Mode Command 0 */\r
+ byte :1; \r
+ byte CMDB2 :1; /* EEPROM User Mode Command 2 */\r
+ byte :1; \r
+ byte :1; \r
+ byte CMDB5 :1; /* EEPROM User Mode Command 5 */\r
+ byte CMDB6 :1; /* EEPROM User Mode Command 6 */\r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpCMDB :1;\r
+ byte :1;\r
+ byte grpCMDB_2 :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpCMDB_5 :2;\r
+ byte :1;\r
+ } MergedBits;\r
+} ECMDSTR;\r
+extern volatile ECMDSTR _ECMD @(REG_BASE + 0x00000116);\r
+#define ECMD _ECMD.Byte\r
+#define ECMD_CMDB0 _ECMD.Bits.CMDB0\r
+#define ECMD_CMDB2 _ECMD.Bits.CMDB2\r
+#define ECMD_CMDB5 _ECMD.Bits.CMDB5\r
+#define ECMD_CMDB6 _ECMD.Bits.CMDB6\r
+#define ECMD_CMDB_5 _ECMD.MergedBits.grpCMDB_5\r
+#define ECMD_CMDB ECMD_CMDB_5\r
+\r
+\r
+/*** ATD1STAT0 - ATD 1 Status Register 0; 0x00000126 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte CC0 :1; /* Conversion Counter 0 */\r
+ byte CC1 :1; /* Conversion Counter 1 */\r
+ byte CC2 :1; /* Conversion Counter 2 */\r
+ byte :1; \r
+ byte FIFOR :1; /* FIFO Over Run Flag */\r
+ byte ETORF :1; /* External Trigger Overrun Flag */\r
+ byte :1; \r
+ byte SCF :1; /* Sequence Complete Flag */\r
+ } Bits;\r
+ struct {\r
+ byte grpCC :3;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} ATD1STAT0STR;\r
+extern volatile ATD1STAT0STR _ATD1STAT0 @(REG_BASE + 0x00000126);\r
+#define ATD1STAT0 _ATD1STAT0.Byte\r
+#define ATD1STAT0_CC0 _ATD1STAT0.Bits.CC0\r
+#define ATD1STAT0_CC1 _ATD1STAT0.Bits.CC1\r
+#define ATD1STAT0_CC2 _ATD1STAT0.Bits.CC2\r
+#define ATD1STAT0_FIFOR _ATD1STAT0.Bits.FIFOR\r
+#define ATD1STAT0_ETORF _ATD1STAT0.Bits.ETORF\r
+#define ATD1STAT0_SCF _ATD1STAT0.Bits.SCF\r
+#define ATD1STAT0_CC _ATD1STAT0.MergedBits.grpCC\r
+\r
+\r
+/*** ATD1STAT1 - ATD 1 Status Register 1; 0x0000012B ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte CCF0 :1; /* Conversion Complete Flag 0 */\r
+ byte CCF1 :1; /* Conversion Complete Flag 1 */\r
+ byte CCF2 :1; /* Conversion Complete Flag 2 */\r
+ byte CCF3 :1; /* Conversion Complete Flag 3 */\r
+ byte CCF4 :1; /* Conversion Complete Flag 4 */\r
+ byte CCF5 :1; /* Conversion Complete Flag 5 */\r
+ byte CCF6 :1; /* Conversion Complete Flag 6 */\r
+ byte CCF7 :1; /* Conversion Complete Flag 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpCCF :8;\r
+ } MergedBits;\r
+} ATD1STAT1STR;\r
+extern volatile ATD1STAT1STR _ATD1STAT1 @(REG_BASE + 0x0000012B);\r
+#define ATD1STAT1 _ATD1STAT1.Byte\r
+#define ATD1STAT1_CCF0 _ATD1STAT1.Bits.CCF0\r
+#define ATD1STAT1_CCF1 _ATD1STAT1.Bits.CCF1\r
+#define ATD1STAT1_CCF2 _ATD1STAT1.Bits.CCF2\r
+#define ATD1STAT1_CCF3 _ATD1STAT1.Bits.CCF3\r
+#define ATD1STAT1_CCF4 _ATD1STAT1.Bits.CCF4\r
+#define ATD1STAT1_CCF5 _ATD1STAT1.Bits.CCF5\r
+#define ATD1STAT1_CCF6 _ATD1STAT1.Bits.CCF6\r
+#define ATD1STAT1_CCF7 _ATD1STAT1.Bits.CCF7\r
+#define ATD1STAT1_CCF _ATD1STAT1.MergedBits.grpCCF\r
+\r
+\r
+/*** ATD1DIEN - ATD 1 Input Enable Mask Register; 0x0000012D ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* Disable/Enable Digital Input Buffer Bit 0 */\r
+ byte BIT1 :1; /* Disable/Enable Digital Input Buffer Bit 1 */\r
+ byte BIT2 :1; /* Disable/Enable Digital Input Buffer Bit 2 */\r
+ byte BIT3 :1; /* Disable/Enable Digital Input Buffer Bit 3 */\r
+ byte BIT4 :1; /* Disable/Enable Digital Input Buffer Bit 4 */\r
+ byte BIT5 :1; /* Disable/Enable Digital Input Buffer Bit 5 */\r
+ byte BIT6 :1; /* Disable/Enable Digital Input Buffer Bit 6 */\r
+ byte BIT7 :1; /* Disable/Enable Digital Input Buffer Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+} ATD1DIENSTR;\r
+extern volatile ATD1DIENSTR _ATD1DIEN @(REG_BASE + 0x0000012D);\r
+#define ATD1DIEN _ATD1DIEN.Byte\r
+#define ATD1DIEN_BIT0 _ATD1DIEN.Bits.BIT0\r
+#define ATD1DIEN_BIT1 _ATD1DIEN.Bits.BIT1\r
+#define ATD1DIEN_BIT2 _ATD1DIEN.Bits.BIT2\r
+#define ATD1DIEN_BIT3 _ATD1DIEN.Bits.BIT3\r
+#define ATD1DIEN_BIT4 _ATD1DIEN.Bits.BIT4\r
+#define ATD1DIEN_BIT5 _ATD1DIEN.Bits.BIT5\r
+#define ATD1DIEN_BIT6 _ATD1DIEN.Bits.BIT6\r
+#define ATD1DIEN_BIT7 _ATD1DIEN.Bits.BIT7\r
+#define ATD1DIEN_BIT _ATD1DIEN.MergedBits.grpBIT\r
+\r
+\r
+/*** PORTAD1 - Port AD1 Register; 0x0000012F ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* AN0 */\r
+ byte BIT1 :1; /* AN1 */\r
+ byte BIT2 :1; /* AN2 */\r
+ byte BIT3 :1; /* AN3 */\r
+ byte BIT4 :1; /* AN4 */\r
+ byte BIT5 :1; /* AN5 */\r
+ byte BIT6 :1; /* AN6 */\r
+ byte BIT7 :1; /* AN7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+} PORTAD1STR;\r
+extern volatile PORTAD1STR _PORTAD1 @(REG_BASE + 0x0000012F);\r
+#define PORTAD1 _PORTAD1.Byte\r
+#define PORTAD1_BIT0 _PORTAD1.Bits.BIT0\r
+#define PORTAD1_BIT1 _PORTAD1.Bits.BIT1\r
+#define PORTAD1_BIT2 _PORTAD1.Bits.BIT2\r
+#define PORTAD1_BIT3 _PORTAD1.Bits.BIT3\r
+#define PORTAD1_BIT4 _PORTAD1.Bits.BIT4\r
+#define PORTAD1_BIT5 _PORTAD1.Bits.BIT5\r
+#define PORTAD1_BIT6 _PORTAD1.Bits.BIT6\r
+#define PORTAD1_BIT7 _PORTAD1.Bits.BIT7\r
+#define PORTAD1_BIT _PORTAD1.MergedBits.grpBIT\r
+\r
+\r
+/*** CAN0CTL0 - MSCAN 0 Control 0 Register; 0x00000140 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte INITRQ :1; /* Initialization Mode Request */\r
+ byte SLPRQ :1; /* Sleep Mode Request */\r
+ byte WUPE :1; /* Wake-Up Enable */\r
+ byte TIME :1; /* Timer Enable */\r
+ byte SYNCH :1; /* Synchronized Status */\r
+ byte CSWAI :1; /* CAN Stops in Wait Mode */\r
+ byte RXACT :1; /* Receiver Active Status */\r
+ byte RXFRM :1; /* Received Frame Flag */\r
+ } Bits;\r
+} CAN0CTL0STR;\r
+extern volatile CAN0CTL0STR _CAN0CTL0 @(REG_BASE + 0x00000140);\r
+#define CAN0CTL0 _CAN0CTL0.Byte\r
+#define CAN0CTL0_INITRQ _CAN0CTL0.Bits.INITRQ\r
+#define CAN0CTL0_SLPRQ _CAN0CTL0.Bits.SLPRQ\r
+#define CAN0CTL0_WUPE _CAN0CTL0.Bits.WUPE\r
+#define CAN0CTL0_TIME _CAN0CTL0.Bits.TIME\r
+#define CAN0CTL0_SYNCH _CAN0CTL0.Bits.SYNCH\r
+#define CAN0CTL0_CSWAI _CAN0CTL0.Bits.CSWAI\r
+#define CAN0CTL0_RXACT _CAN0CTL0.Bits.RXACT\r
+#define CAN0CTL0_RXFRM _CAN0CTL0.Bits.RXFRM\r
+\r
+\r
+/*** CAN0CTL1 - MSCAN 0 Control 1 Register; 0x00000141 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte INITAK :1; /* Initialization Mode Acknowledge */\r
+ byte SLPAK :1; /* Sleep Mode Acknowledge */\r
+ byte WUPM :1; /* Wake-Up Mode */\r
+ byte :1; \r
+ byte LISTEN :1; /* Listen Only Mode */\r
+ byte LOOPB :1; /* Loop Back Self Test Mode */\r
+ byte CLKSRC :1; /* MSCAN 0 Clock Source */\r
+ byte CANE :1; /* MSCAN 0 Enable */\r
+ } Bits;\r
+} CAN0CTL1STR;\r
+extern volatile CAN0CTL1STR _CAN0CTL1 @(REG_BASE + 0x00000141);\r
+#define CAN0CTL1 _CAN0CTL1.Byte\r
+#define CAN0CTL1_INITAK _CAN0CTL1.Bits.INITAK\r
+#define CAN0CTL1_SLPAK _CAN0CTL1.Bits.SLPAK\r
+#define CAN0CTL1_WUPM _CAN0CTL1.Bits.WUPM\r
+#define CAN0CTL1_LISTEN _CAN0CTL1.Bits.LISTEN\r
+#define CAN0CTL1_LOOPB _CAN0CTL1.Bits.LOOPB\r
+#define CAN0CTL1_CLKSRC _CAN0CTL1.Bits.CLKSRC\r
+#define CAN0CTL1_CANE _CAN0CTL1.Bits.CANE\r
+\r
+\r
+/*** CAN0BTR0 - MSCAN 0 Bus Timing Register 0; 0x00000142 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte BRP0 :1; /* Baud Rate Prescaler 0 */\r
+ byte BRP1 :1; /* Baud Rate Prescaler 1 */\r
+ byte BRP2 :1; /* Baud Rate Prescaler 2 */\r
+ byte BRP3 :1; /* Baud Rate Prescaler 3 */\r
+ byte BRP4 :1; /* Baud Rate Prescaler 4 */\r
+ byte BRP5 :1; /* Baud Rate Prescaler 5 */\r
+ byte SJW0 :1; /* Synchronization Jump Width 0 */\r
+ byte SJW1 :1; /* Synchronization Jump Width 1 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBRP :6;\r
+ byte grpSJW :2;\r
+ } MergedBits;\r
+} CAN0BTR0STR;\r
+extern volatile CAN0BTR0STR _CAN0BTR0 @(REG_BASE + 0x00000142);\r
+#define CAN0BTR0 _CAN0BTR0.Byte\r
+#define CAN0BTR0_BRP0 _CAN0BTR0.Bits.BRP0\r
+#define CAN0BTR0_BRP1 _CAN0BTR0.Bits.BRP1\r
+#define CAN0BTR0_BRP2 _CAN0BTR0.Bits.BRP2\r
+#define CAN0BTR0_BRP3 _CAN0BTR0.Bits.BRP3\r
+#define CAN0BTR0_BRP4 _CAN0BTR0.Bits.BRP4\r
+#define CAN0BTR0_BRP5 _CAN0BTR0.Bits.BRP5\r
+#define CAN0BTR0_SJW0 _CAN0BTR0.Bits.SJW0\r
+#define CAN0BTR0_SJW1 _CAN0BTR0.Bits.SJW1\r
+#define CAN0BTR0_BRP _CAN0BTR0.MergedBits.grpBRP\r
+#define CAN0BTR0_SJW _CAN0BTR0.MergedBits.grpSJW\r
+\r
+\r
+/*** CAN0BTR1 - MSCAN 0 Bus Timing Register 1; 0x00000143 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte TSEG10 :1; /* Time Segment 1 */\r
+ byte TSEG11 :1; /* Time Segment 1 */\r
+ byte TSEG12 :1; /* Time Segment 1 */\r
+ byte TSEG13 :1; /* Time Segment 1 */\r
+ byte TSEG20 :1; /* Time Segment 2 */\r
+ byte TSEG21 :1; /* Time Segment 2 */\r
+ byte TSEG22 :1; /* Time Segment 2 */\r
+ byte SAMP :1; /* Sampling */\r
+ } Bits;\r
+ struct {\r
+ byte grpTSEG_10 :4;\r
+ byte grpTSEG_20 :3;\r
+ byte :1;\r
+ } MergedBits;\r
+} CAN0BTR1STR;\r
+extern volatile CAN0BTR1STR _CAN0BTR1 @(REG_BASE + 0x00000143);\r
+#define CAN0BTR1 _CAN0BTR1.Byte\r
+#define CAN0BTR1_TSEG10 _CAN0BTR1.Bits.TSEG10\r
+#define CAN0BTR1_TSEG11 _CAN0BTR1.Bits.TSEG11\r
+#define CAN0BTR1_TSEG12 _CAN0BTR1.Bits.TSEG12\r
+#define CAN0BTR1_TSEG13 _CAN0BTR1.Bits.TSEG13\r
+#define CAN0BTR1_TSEG20 _CAN0BTR1.Bits.TSEG20\r
+#define CAN0BTR1_TSEG21 _CAN0BTR1.Bits.TSEG21\r
+#define CAN0BTR1_TSEG22 _CAN0BTR1.Bits.TSEG22\r
+#define CAN0BTR1_SAMP _CAN0BTR1.Bits.SAMP\r
+#define CAN0BTR1_TSEG_10 _CAN0BTR1.MergedBits.grpTSEG_10\r
+#define CAN0BTR1_TSEG_20 _CAN0BTR1.MergedBits.grpTSEG_20\r
+#define CAN0BTR1_TSEG CAN0BTR1_TSEG_10\r
+\r
+\r
+/*** CAN0RFLG - MSCAN 0 Receiver Flag Register; 0x00000144 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte RXF :1; /* Receive Buffer Full */\r
+ byte OVRIF :1; /* Overrun Interrupt Flag */\r
+ byte TSTAT0 :1; /* Transmitter Status Bit 0 */\r
+ byte TSTAT1 :1; /* Transmitter Status Bit 1 */\r
+ byte RSTAT0 :1; /* Receiver Status Bit 0 */\r
+ byte RSTAT1 :1; /* Receiver Status Bit 1 */\r
+ byte CSCIF :1; /* CAN Status Change Interrupt Flag */\r
+ byte WUPIF :1; /* Wake-up Interrupt Flag */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte grpTSTAT :2;\r
+ byte grpRSTAT :2;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CAN0RFLGSTR;\r
+extern volatile CAN0RFLGSTR _CAN0RFLG @(REG_BASE + 0x00000144);\r
+#define CAN0RFLG _CAN0RFLG.Byte\r
+#define CAN0RFLG_RXF _CAN0RFLG.Bits.RXF\r
+#define CAN0RFLG_OVRIF _CAN0RFLG.Bits.OVRIF\r
+#define CAN0RFLG_TSTAT0 _CAN0RFLG.Bits.TSTAT0\r
+#define CAN0RFLG_TSTAT1 _CAN0RFLG.Bits.TSTAT1\r
+#define CAN0RFLG_RSTAT0 _CAN0RFLG.Bits.RSTAT0\r
+#define CAN0RFLG_RSTAT1 _CAN0RFLG.Bits.RSTAT1\r
+#define CAN0RFLG_CSCIF _CAN0RFLG.Bits.CSCIF\r
+#define CAN0RFLG_WUPIF _CAN0RFLG.Bits.WUPIF\r
+#define CAN0RFLG_TSTAT _CAN0RFLG.MergedBits.grpTSTAT\r
+#define CAN0RFLG_RSTAT _CAN0RFLG.MergedBits.grpRSTAT\r
+\r
+\r
+/*** CAN0RIER - MSCAN 0 Receiver Interrupt Enable Register; 0x00000145 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte RXFIE :1; /* Receiver Full Interrupt Enable */\r
+ byte OVRIE :1; /* Overrun Interrupt Enable */\r
+ byte TSTATE0 :1; /* Transmitter Status Change Enable 0 */\r
+ byte TSTATE1 :1; /* Transmitter Status Change Enable 1 */\r
+ byte RSTATE0 :1; /* Receiver Status Change Enable 0 */\r
+ byte RSTATE1 :1; /* Receiver Status Change Enable 1 */\r
+ byte CSCIE :1; /* CAN Status Change Interrupt Enable */\r
+ byte WUPIE :1; /* Wake-up Interrupt Enable */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte grpTSTATE :2;\r
+ byte grpRSTATE :2;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CAN0RIERSTR;\r
+extern volatile CAN0RIERSTR _CAN0RIER @(REG_BASE + 0x00000145);\r
+#define CAN0RIER _CAN0RIER.Byte\r
+#define CAN0RIER_RXFIE _CAN0RIER.Bits.RXFIE\r
+#define CAN0RIER_OVRIE _CAN0RIER.Bits.OVRIE\r
+#define CAN0RIER_TSTATE0 _CAN0RIER.Bits.TSTATE0\r
+#define CAN0RIER_TSTATE1 _CAN0RIER.Bits.TSTATE1\r
+#define CAN0RIER_RSTATE0 _CAN0RIER.Bits.RSTATE0\r
+#define CAN0RIER_RSTATE1 _CAN0RIER.Bits.RSTATE1\r
+#define CAN0RIER_CSCIE _CAN0RIER.Bits.CSCIE\r
+#define CAN0RIER_WUPIE _CAN0RIER.Bits.WUPIE\r
+#define CAN0RIER_TSTATE _CAN0RIER.MergedBits.grpTSTATE\r
+#define CAN0RIER_RSTATE _CAN0RIER.MergedBits.grpRSTATE\r
+\r
+\r
+/*** CAN0TFLG - MSCAN 0 Transmitter Flag Register; 0x00000146 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte TXE0 :1; /* Transmitter Buffer Empty 0 */\r
+ byte TXE1 :1; /* Transmitter Buffer Empty 1 */\r
+ byte TXE2 :1; /* Transmitter Buffer Empty 2 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpTXE :3;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CAN0TFLGSTR;\r
+extern volatile CAN0TFLGSTR _CAN0TFLG @(REG_BASE + 0x00000146);\r
+#define CAN0TFLG _CAN0TFLG.Byte\r
+#define CAN0TFLG_TXE0 _CAN0TFLG.Bits.TXE0\r
+#define CAN0TFLG_TXE1 _CAN0TFLG.Bits.TXE1\r
+#define CAN0TFLG_TXE2 _CAN0TFLG.Bits.TXE2\r
+#define CAN0TFLG_TXE _CAN0TFLG.MergedBits.grpTXE\r
+\r
+\r
+/*** CAN0TIER - MSCAN 0 Transmitter Interrupt Enable Register; 0x00000147 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte TXEIE0 :1; /* Transmitter Empty Interrupt Enable 0 */\r
+ byte TXEIE1 :1; /* Transmitter Empty Interrupt Enable 1 */\r
+ byte TXEIE2 :1; /* Transmitter Empty Interrupt Enable 2 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpTXEIE :3;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CAN0TIERSTR;\r
+extern volatile CAN0TIERSTR _CAN0TIER @(REG_BASE + 0x00000147);\r
+#define CAN0TIER _CAN0TIER.Byte\r
+#define CAN0TIER_TXEIE0 _CAN0TIER.Bits.TXEIE0\r
+#define CAN0TIER_TXEIE1 _CAN0TIER.Bits.TXEIE1\r
+#define CAN0TIER_TXEIE2 _CAN0TIER.Bits.TXEIE2\r
+#define CAN0TIER_TXEIE _CAN0TIER.MergedBits.grpTXEIE\r
+\r
+\r
+/*** CAN0TARQ - MSCAN 0 Transmitter Message Abort Request; 0x00000148 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ABTRQ0 :1; /* Abort Request 0 */\r
+ byte ABTRQ1 :1; /* Abort Request 1 */\r
+ byte ABTRQ2 :1; /* Abort Request 2 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpABTRQ :3;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CAN0TARQSTR;\r
+extern volatile CAN0TARQSTR _CAN0TARQ @(REG_BASE + 0x00000148);\r
+#define CAN0TARQ _CAN0TARQ.Byte\r
+#define CAN0TARQ_ABTRQ0 _CAN0TARQ.Bits.ABTRQ0\r
+#define CAN0TARQ_ABTRQ1 _CAN0TARQ.Bits.ABTRQ1\r
+#define CAN0TARQ_ABTRQ2 _CAN0TARQ.Bits.ABTRQ2\r
+#define CAN0TARQ_ABTRQ _CAN0TARQ.MergedBits.grpABTRQ\r
+\r
+\r
+/*** CAN0TAAK - MSCAN 0 Transmitter Message Abort Control; 0x00000149 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ABTAK0 :1; /* Abort Acknowledge 0 */\r
+ byte ABTAK1 :1; /* Abort Acknowledge 1 */\r
+ byte ABTAK2 :1; /* Abort Acknowledge 2 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpABTAK :3;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CAN0TAAKSTR;\r
+extern volatile CAN0TAAKSTR _CAN0TAAK @(REG_BASE + 0x00000149);\r
+#define CAN0TAAK _CAN0TAAK.Byte\r
+#define CAN0TAAK_ABTAK0 _CAN0TAAK.Bits.ABTAK0\r
+#define CAN0TAAK_ABTAK1 _CAN0TAAK.Bits.ABTAK1\r
+#define CAN0TAAK_ABTAK2 _CAN0TAAK.Bits.ABTAK2\r
+#define CAN0TAAK_ABTAK _CAN0TAAK.MergedBits.grpABTAK\r
+\r
+\r
+/*** CAN0TBSEL - MSCAN 0 Transmit Buffer Selection; 0x0000014A ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte TX0 :1; /* Transmit Buffer Select 0 */\r
+ byte TX1 :1; /* Transmit Buffer Select 1 */\r
+ byte TX2 :1; /* Transmit Buffer Select 2 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpTX :3;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CAN0TBSELSTR;\r
+extern volatile CAN0TBSELSTR _CAN0TBSEL @(REG_BASE + 0x0000014A);\r
+#define CAN0TBSEL _CAN0TBSEL.Byte\r
+#define CAN0TBSEL_TX0 _CAN0TBSEL.Bits.TX0\r
+#define CAN0TBSEL_TX1 _CAN0TBSEL.Bits.TX1\r
+#define CAN0TBSEL_TX2 _CAN0TBSEL.Bits.TX2\r
+#define CAN0TBSEL_TX _CAN0TBSEL.MergedBits.grpTX\r
+\r
+\r
+/*** CAN0IDAC - MSCAN 0 Identifier Acceptance Control Register; 0x0000014B ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte IDHIT0 :1; /* Identifier Acceptance Hit Indicator 0 */\r
+ byte IDHIT1 :1; /* Identifier Acceptance Hit Indicator 1 */\r
+ byte IDHIT2 :1; /* Identifier Acceptance Hit Indicator 2 */\r
+ byte :1; \r
+ byte IDAM0 :1; /* Identifier Acceptance Mode 0 */\r
+ byte IDAM1 :1; /* Identifier Acceptance Mode 1 */\r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpIDHIT :3;\r
+ byte :1;\r
+ byte grpIDAM :2;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CAN0IDACSTR;\r
+extern volatile CAN0IDACSTR _CAN0IDAC @(REG_BASE + 0x0000014B);\r
+#define CAN0IDAC _CAN0IDAC.Byte\r
+#define CAN0IDAC_IDHIT0 _CAN0IDAC.Bits.IDHIT0\r
+#define CAN0IDAC_IDHIT1 _CAN0IDAC.Bits.IDHIT1\r
+#define CAN0IDAC_IDHIT2 _CAN0IDAC.Bits.IDHIT2\r
+#define CAN0IDAC_IDAM0 _CAN0IDAC.Bits.IDAM0\r
+#define CAN0IDAC_IDAM1 _CAN0IDAC.Bits.IDAM1\r
+#define CAN0IDAC_IDHIT _CAN0IDAC.MergedBits.grpIDHIT\r
+#define CAN0IDAC_IDAM _CAN0IDAC.MergedBits.grpIDAM\r
+\r
+\r
+/*** CAN0RXERR - MSCAN 0 Receive Error Counter Register; 0x0000014E ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte RXERR0 :1; /* Bit 0 */\r
+ byte RXERR1 :1; /* Bit 1 */\r
+ byte RXERR2 :1; /* Bit 2 */\r
+ byte RXERR3 :1; /* Bit 3 */\r
+ byte RXERR4 :1; /* Bit 4 */\r
+ byte RXERR5 :1; /* Bit 5 */\r
+ byte RXERR6 :1; /* Bit 6 */\r
+ byte RXERR7 :1; /* Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpRXERR :8;\r
+ } MergedBits;\r
+} CAN0RXERRSTR;\r
+extern volatile CAN0RXERRSTR _CAN0RXERR @(REG_BASE + 0x0000014E);\r
+#define CAN0RXERR _CAN0RXERR.Byte\r
+#define CAN0RXERR_RXERR0 _CAN0RXERR.Bits.RXERR0\r
+#define CAN0RXERR_RXERR1 _CAN0RXERR.Bits.RXERR1\r
+#define CAN0RXERR_RXERR2 _CAN0RXERR.Bits.RXERR2\r
+#define CAN0RXERR_RXERR3 _CAN0RXERR.Bits.RXERR3\r
+#define CAN0RXERR_RXERR4 _CAN0RXERR.Bits.RXERR4\r
+#define CAN0RXERR_RXERR5 _CAN0RXERR.Bits.RXERR5\r
+#define CAN0RXERR_RXERR6 _CAN0RXERR.Bits.RXERR6\r
+#define CAN0RXERR_RXERR7 _CAN0RXERR.Bits.RXERR7\r
+#define CAN0RXERR_RXERR _CAN0RXERR.MergedBits.grpRXERR\r
+\r
+\r
+/*** CAN0TXERR - MSCAN 0 Transmit Error Counter Register; 0x0000014F ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte TXERR0 :1; /* Bit 0 */\r
+ byte TXERR1 :1; /* Bit 1 */\r
+ byte TXERR2 :1; /* Bit 2 */\r
+ byte TXERR3 :1; /* Bit 3 */\r
+ byte TXERR4 :1; /* Bit 4 */\r
+ byte TXERR5 :1; /* Bit 5 */\r
+ byte TXERR6 :1; /* Bit 6 */\r
+ byte TXERR7 :1; /* Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpTXERR :8;\r
+ } MergedBits;\r
+} CAN0TXERRSTR;\r
+extern volatile CAN0TXERRSTR _CAN0TXERR @(REG_BASE + 0x0000014F);\r
+#define CAN0TXERR _CAN0TXERR.Byte\r
+#define CAN0TXERR_TXERR0 _CAN0TXERR.Bits.TXERR0\r
+#define CAN0TXERR_TXERR1 _CAN0TXERR.Bits.TXERR1\r
+#define CAN0TXERR_TXERR2 _CAN0TXERR.Bits.TXERR2\r
+#define CAN0TXERR_TXERR3 _CAN0TXERR.Bits.TXERR3\r
+#define CAN0TXERR_TXERR4 _CAN0TXERR.Bits.TXERR4\r
+#define CAN0TXERR_TXERR5 _CAN0TXERR.Bits.TXERR5\r
+#define CAN0TXERR_TXERR6 _CAN0TXERR.Bits.TXERR6\r
+#define CAN0TXERR_TXERR7 _CAN0TXERR.Bits.TXERR7\r
+#define CAN0TXERR_TXERR _CAN0TXERR.MergedBits.grpTXERR\r
+\r
+\r
+/*** CAN0IDAR0 - MSCAN 0 Identifier Acceptance Register 0; 0x00000150 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AC0 :1; /* Acceptance Code Bit 0 */\r
+ byte AC1 :1; /* Acceptance Code Bit 1 */\r
+ byte AC2 :1; /* Acceptance Code Bit 2 */\r
+ byte AC3 :1; /* Acceptance Code Bit 3 */\r
+ byte AC4 :1; /* Acceptance Code Bit 4 */\r
+ byte AC5 :1; /* Acceptance Code Bit 5 */\r
+ byte AC6 :1; /* Acceptance Code Bit 6 */\r
+ byte AC7 :1; /* Acceptance Code Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAC :8;\r
+ } MergedBits;\r
+} CAN0IDAR0STR;\r
+extern volatile CAN0IDAR0STR _CAN0IDAR0 @(REG_BASE + 0x00000150);\r
+#define CAN0IDAR0 _CAN0IDAR0.Byte\r
+#define CAN0IDAR0_AC0 _CAN0IDAR0.Bits.AC0\r
+#define CAN0IDAR0_AC1 _CAN0IDAR0.Bits.AC1\r
+#define CAN0IDAR0_AC2 _CAN0IDAR0.Bits.AC2\r
+#define CAN0IDAR0_AC3 _CAN0IDAR0.Bits.AC3\r
+#define CAN0IDAR0_AC4 _CAN0IDAR0.Bits.AC4\r
+#define CAN0IDAR0_AC5 _CAN0IDAR0.Bits.AC5\r
+#define CAN0IDAR0_AC6 _CAN0IDAR0.Bits.AC6\r
+#define CAN0IDAR0_AC7 _CAN0IDAR0.Bits.AC7\r
+#define CAN0IDAR0_AC _CAN0IDAR0.MergedBits.grpAC\r
+\r
+\r
+/*** CAN0IDAR1 - MSCAN 0 Identifier Acceptance Register 1; 0x00000151 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AC0 :1; /* Acceptance Code Bit 0 */\r
+ byte AC1 :1; /* Acceptance Code Bit 1 */\r
+ byte AC2 :1; /* Acceptance Code Bit 2 */\r
+ byte AC3 :1; /* Acceptance Code Bit 3 */\r
+ byte AC4 :1; /* Acceptance Code Bit 4 */\r
+ byte AC5 :1; /* Acceptance Code Bit 5 */\r
+ byte AC6 :1; /* Acceptance Code Bit 6 */\r
+ byte AC7 :1; /* Acceptance Code Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAC :8;\r
+ } MergedBits;\r
+} CAN0IDAR1STR;\r
+extern volatile CAN0IDAR1STR _CAN0IDAR1 @(REG_BASE + 0x00000151);\r
+#define CAN0IDAR1 _CAN0IDAR1.Byte\r
+#define CAN0IDAR1_AC0 _CAN0IDAR1.Bits.AC0\r
+#define CAN0IDAR1_AC1 _CAN0IDAR1.Bits.AC1\r
+#define CAN0IDAR1_AC2 _CAN0IDAR1.Bits.AC2\r
+#define CAN0IDAR1_AC3 _CAN0IDAR1.Bits.AC3\r
+#define CAN0IDAR1_AC4 _CAN0IDAR1.Bits.AC4\r
+#define CAN0IDAR1_AC5 _CAN0IDAR1.Bits.AC5\r
+#define CAN0IDAR1_AC6 _CAN0IDAR1.Bits.AC6\r
+#define CAN0IDAR1_AC7 _CAN0IDAR1.Bits.AC7\r
+#define CAN0IDAR1_AC _CAN0IDAR1.MergedBits.grpAC\r
+\r
+\r
+/*** CAN0IDAR2 - MSCAN 0 Identifier Acceptance Register 2; 0x00000152 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AC0 :1; /* Acceptance Code Bit 0 */\r
+ byte AC1 :1; /* Acceptance Code Bit 1 */\r
+ byte AC2 :1; /* Acceptance Code Bit 2 */\r
+ byte AC3 :1; /* Acceptance Code Bit 3 */\r
+ byte AC4 :1; /* Acceptance Code Bit 4 */\r
+ byte AC5 :1; /* Acceptance Code Bit 5 */\r
+ byte AC6 :1; /* Acceptance Code Bit 6 */\r
+ byte AC7 :1; /* Acceptance Code Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAC :8;\r
+ } MergedBits;\r
+} CAN0IDAR2STR;\r
+extern volatile CAN0IDAR2STR _CAN0IDAR2 @(REG_BASE + 0x00000152);\r
+#define CAN0IDAR2 _CAN0IDAR2.Byte\r
+#define CAN0IDAR2_AC0 _CAN0IDAR2.Bits.AC0\r
+#define CAN0IDAR2_AC1 _CAN0IDAR2.Bits.AC1\r
+#define CAN0IDAR2_AC2 _CAN0IDAR2.Bits.AC2\r
+#define CAN0IDAR2_AC3 _CAN0IDAR2.Bits.AC3\r
+#define CAN0IDAR2_AC4 _CAN0IDAR2.Bits.AC4\r
+#define CAN0IDAR2_AC5 _CAN0IDAR2.Bits.AC5\r
+#define CAN0IDAR2_AC6 _CAN0IDAR2.Bits.AC6\r
+#define CAN0IDAR2_AC7 _CAN0IDAR2.Bits.AC7\r
+#define CAN0IDAR2_AC _CAN0IDAR2.MergedBits.grpAC\r
+\r
+\r
+/*** CAN0IDAR3 - MSCAN 0 Identifier Acceptance Register 3; 0x00000153 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AC0 :1; /* Acceptance Code Bit 0 */\r
+ byte AC1 :1; /* Acceptance Code Bit 1 */\r
+ byte AC2 :1; /* Acceptance Code Bit 2 */\r
+ byte AC3 :1; /* Acceptance Code Bit 3 */\r
+ byte AC4 :1; /* Acceptance Code Bit 4 */\r
+ byte AC5 :1; /* Acceptance Code Bit 5 */\r
+ byte AC6 :1; /* Acceptance Code Bit 6 */\r
+ byte AC7 :1; /* Acceptance Code Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAC :8;\r
+ } MergedBits;\r
+} CAN0IDAR3STR;\r
+extern volatile CAN0IDAR3STR _CAN0IDAR3 @(REG_BASE + 0x00000153);\r
+#define CAN0IDAR3 _CAN0IDAR3.Byte\r
+#define CAN0IDAR3_AC0 _CAN0IDAR3.Bits.AC0\r
+#define CAN0IDAR3_AC1 _CAN0IDAR3.Bits.AC1\r
+#define CAN0IDAR3_AC2 _CAN0IDAR3.Bits.AC2\r
+#define CAN0IDAR3_AC3 _CAN0IDAR3.Bits.AC3\r
+#define CAN0IDAR3_AC4 _CAN0IDAR3.Bits.AC4\r
+#define CAN0IDAR3_AC5 _CAN0IDAR3.Bits.AC5\r
+#define CAN0IDAR3_AC6 _CAN0IDAR3.Bits.AC6\r
+#define CAN0IDAR3_AC7 _CAN0IDAR3.Bits.AC7\r
+#define CAN0IDAR3_AC _CAN0IDAR3.MergedBits.grpAC\r
+\r
+\r
+/*** CAN0IDMR0 - MSCAN 0 Identifier Mask Register 0; 0x00000154 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AM0 :1; /* Acceptance Mask Bit 0 */\r
+ byte AM1 :1; /* Acceptance Mask Bit 1 */\r
+ byte AM2 :1; /* Acceptance Mask Bit 2 */\r
+ byte AM3 :1; /* Acceptance Mask Bit 3 */\r
+ byte AM4 :1; /* Acceptance Mask Bit 4 */\r
+ byte AM5 :1; /* Acceptance Mask Bit 5 */\r
+ byte AM6 :1; /* Acceptance Mask Bit 6 */\r
+ byte AM7 :1; /* Acceptance Mask Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAM :8;\r
+ } MergedBits;\r
+} CAN0IDMR0STR;\r
+extern volatile CAN0IDMR0STR _CAN0IDMR0 @(REG_BASE + 0x00000154);\r
+#define CAN0IDMR0 _CAN0IDMR0.Byte\r
+#define CAN0IDMR0_AM0 _CAN0IDMR0.Bits.AM0\r
+#define CAN0IDMR0_AM1 _CAN0IDMR0.Bits.AM1\r
+#define CAN0IDMR0_AM2 _CAN0IDMR0.Bits.AM2\r
+#define CAN0IDMR0_AM3 _CAN0IDMR0.Bits.AM3\r
+#define CAN0IDMR0_AM4 _CAN0IDMR0.Bits.AM4\r
+#define CAN0IDMR0_AM5 _CAN0IDMR0.Bits.AM5\r
+#define CAN0IDMR0_AM6 _CAN0IDMR0.Bits.AM6\r
+#define CAN0IDMR0_AM7 _CAN0IDMR0.Bits.AM7\r
+#define CAN0IDMR0_AM _CAN0IDMR0.MergedBits.grpAM\r
+\r
+\r
+/*** CAN0IDMR1 - MSCAN 0 Identifier Mask Register 1; 0x00000155 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AM0 :1; /* Acceptance Mask Bit 0 */\r
+ byte AM1 :1; /* Acceptance Mask Bit 1 */\r
+ byte AM2 :1; /* Acceptance Mask Bit 2 */\r
+ byte AM3 :1; /* Acceptance Mask Bit 3 */\r
+ byte AM4 :1; /* Acceptance Mask Bit 4 */\r
+ byte AM5 :1; /* Acceptance Mask Bit 5 */\r
+ byte AM6 :1; /* Acceptance Mask Bit 6 */\r
+ byte AM7 :1; /* Acceptance Mask Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAM :8;\r
+ } MergedBits;\r
+} CAN0IDMR1STR;\r
+extern volatile CAN0IDMR1STR _CAN0IDMR1 @(REG_BASE + 0x00000155);\r
+#define CAN0IDMR1 _CAN0IDMR1.Byte\r
+#define CAN0IDMR1_AM0 _CAN0IDMR1.Bits.AM0\r
+#define CAN0IDMR1_AM1 _CAN0IDMR1.Bits.AM1\r
+#define CAN0IDMR1_AM2 _CAN0IDMR1.Bits.AM2\r
+#define CAN0IDMR1_AM3 _CAN0IDMR1.Bits.AM3\r
+#define CAN0IDMR1_AM4 _CAN0IDMR1.Bits.AM4\r
+#define CAN0IDMR1_AM5 _CAN0IDMR1.Bits.AM5\r
+#define CAN0IDMR1_AM6 _CAN0IDMR1.Bits.AM6\r
+#define CAN0IDMR1_AM7 _CAN0IDMR1.Bits.AM7\r
+#define CAN0IDMR1_AM _CAN0IDMR1.MergedBits.grpAM\r
+\r
+\r
+/*** CAN0IDMR2 - MSCAN 0 Identifier Mask Register 2; 0x00000156 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AM0 :1; /* Acceptance Mask Bit 0 */\r
+ byte AM1 :1; /* Acceptance Mask Bit 1 */\r
+ byte AM2 :1; /* Acceptance Mask Bit 2 */\r
+ byte AM3 :1; /* Acceptance Mask Bit 3 */\r
+ byte AM4 :1; /* Acceptance Mask Bit 4 */\r
+ byte AM5 :1; /* Acceptance Mask Bit 5 */\r
+ byte AM6 :1; /* Acceptance Mask Bit 6 */\r
+ byte AM7 :1; /* Acceptance Mask Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAM :8;\r
+ } MergedBits;\r
+} CAN0IDMR2STR;\r
+extern volatile CAN0IDMR2STR _CAN0IDMR2 @(REG_BASE + 0x00000156);\r
+#define CAN0IDMR2 _CAN0IDMR2.Byte\r
+#define CAN0IDMR2_AM0 _CAN0IDMR2.Bits.AM0\r
+#define CAN0IDMR2_AM1 _CAN0IDMR2.Bits.AM1\r
+#define CAN0IDMR2_AM2 _CAN0IDMR2.Bits.AM2\r
+#define CAN0IDMR2_AM3 _CAN0IDMR2.Bits.AM3\r
+#define CAN0IDMR2_AM4 _CAN0IDMR2.Bits.AM4\r
+#define CAN0IDMR2_AM5 _CAN0IDMR2.Bits.AM5\r
+#define CAN0IDMR2_AM6 _CAN0IDMR2.Bits.AM6\r
+#define CAN0IDMR2_AM7 _CAN0IDMR2.Bits.AM7\r
+#define CAN0IDMR2_AM _CAN0IDMR2.MergedBits.grpAM\r
+\r
+\r
+/*** CAN0IDMR3 - MSCAN 0 Identifier Mask Register 3; 0x00000157 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AM0 :1; /* Acceptance Mask Bit 0 */\r
+ byte AM1 :1; /* Acceptance Mask Bit 1 */\r
+ byte AM2 :1; /* Acceptance Mask Bit 2 */\r
+ byte AM3 :1; /* Acceptance Mask Bit 3 */\r
+ byte AM4 :1; /* Acceptance Mask Bit 4 */\r
+ byte AM5 :1; /* Acceptance Mask Bit 5 */\r
+ byte AM6 :1; /* Acceptance Mask Bit 6 */\r
+ byte AM7 :1; /* Acceptance Mask Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAM :8;\r
+ } MergedBits;\r
+} CAN0IDMR3STR;\r
+extern volatile CAN0IDMR3STR _CAN0IDMR3 @(REG_BASE + 0x00000157);\r
+#define CAN0IDMR3 _CAN0IDMR3.Byte\r
+#define CAN0IDMR3_AM0 _CAN0IDMR3.Bits.AM0\r
+#define CAN0IDMR3_AM1 _CAN0IDMR3.Bits.AM1\r
+#define CAN0IDMR3_AM2 _CAN0IDMR3.Bits.AM2\r
+#define CAN0IDMR3_AM3 _CAN0IDMR3.Bits.AM3\r
+#define CAN0IDMR3_AM4 _CAN0IDMR3.Bits.AM4\r
+#define CAN0IDMR3_AM5 _CAN0IDMR3.Bits.AM5\r
+#define CAN0IDMR3_AM6 _CAN0IDMR3.Bits.AM6\r
+#define CAN0IDMR3_AM7 _CAN0IDMR3.Bits.AM7\r
+#define CAN0IDMR3_AM _CAN0IDMR3.MergedBits.grpAM\r
+\r
+\r
+/*** CAN0IDAR4 - MSCAN 0 Identifier Acceptance Register 4; 0x00000158 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AC0 :1; /* Acceptance Code Bit 0 */\r
+ byte AC1 :1; /* Acceptance Code Bit 1 */\r
+ byte AC2 :1; /* Acceptance Code Bit 2 */\r
+ byte AC3 :1; /* Acceptance Code Bit 3 */\r
+ byte AC4 :1; /* Acceptance Code Bit 4 */\r
+ byte AC5 :1; /* Acceptance Code Bit 5 */\r
+ byte AC6 :1; /* Acceptance Code Bit 6 */\r
+ byte AC7 :1; /* Acceptance Code Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAC :8;\r
+ } MergedBits;\r
+} CAN0IDAR4STR;\r
+extern volatile CAN0IDAR4STR _CAN0IDAR4 @(REG_BASE + 0x00000158);\r
+#define CAN0IDAR4 _CAN0IDAR4.Byte\r
+#define CAN0IDAR4_AC0 _CAN0IDAR4.Bits.AC0\r
+#define CAN0IDAR4_AC1 _CAN0IDAR4.Bits.AC1\r
+#define CAN0IDAR4_AC2 _CAN0IDAR4.Bits.AC2\r
+#define CAN0IDAR4_AC3 _CAN0IDAR4.Bits.AC3\r
+#define CAN0IDAR4_AC4 _CAN0IDAR4.Bits.AC4\r
+#define CAN0IDAR4_AC5 _CAN0IDAR4.Bits.AC5\r
+#define CAN0IDAR4_AC6 _CAN0IDAR4.Bits.AC6\r
+#define CAN0IDAR4_AC7 _CAN0IDAR4.Bits.AC7\r
+#define CAN0IDAR4_AC _CAN0IDAR4.MergedBits.grpAC\r
+\r
+\r
+/*** CAN0IDAR5 - MSCAN 0 Identifier Acceptance Register 5; 0x00000159 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AC0 :1; /* Acceptance Code Bit 0 */\r
+ byte AC1 :1; /* Acceptance Code Bit 1 */\r
+ byte AC2 :1; /* Acceptance Code Bit 2 */\r
+ byte AC3 :1; /* Acceptance Code Bit 3 */\r
+ byte AC4 :1; /* Acceptance Code Bit 4 */\r
+ byte AC5 :1; /* Acceptance Code Bit 5 */\r
+ byte AC6 :1; /* Acceptance Code Bit 6 */\r
+ byte AC7 :1; /* Acceptance Code Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAC :8;\r
+ } MergedBits;\r
+} CAN0IDAR5STR;\r
+extern volatile CAN0IDAR5STR _CAN0IDAR5 @(REG_BASE + 0x00000159);\r
+#define CAN0IDAR5 _CAN0IDAR5.Byte\r
+#define CAN0IDAR5_AC0 _CAN0IDAR5.Bits.AC0\r
+#define CAN0IDAR5_AC1 _CAN0IDAR5.Bits.AC1\r
+#define CAN0IDAR5_AC2 _CAN0IDAR5.Bits.AC2\r
+#define CAN0IDAR5_AC3 _CAN0IDAR5.Bits.AC3\r
+#define CAN0IDAR5_AC4 _CAN0IDAR5.Bits.AC4\r
+#define CAN0IDAR5_AC5 _CAN0IDAR5.Bits.AC5\r
+#define CAN0IDAR5_AC6 _CAN0IDAR5.Bits.AC6\r
+#define CAN0IDAR5_AC7 _CAN0IDAR5.Bits.AC7\r
+#define CAN0IDAR5_AC _CAN0IDAR5.MergedBits.grpAC\r
+\r
+\r
+/*** CAN0IDAR6 - MSCAN 0 Identifier Acceptance Register 6; 0x0000015A ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AC0 :1; /* Acceptance Code Bit 0 */\r
+ byte AC1 :1; /* Acceptance Code Bit 1 */\r
+ byte AC2 :1; /* Acceptance Code Bit 2 */\r
+ byte AC3 :1; /* Acceptance Code Bit 3 */\r
+ byte AC4 :1; /* Acceptance Code Bit 4 */\r
+ byte AC5 :1; /* Acceptance Code Bit 5 */\r
+ byte AC6 :1; /* Acceptance Code Bit 6 */\r
+ byte AC7 :1; /* Acceptance Code Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAC :8;\r
+ } MergedBits;\r
+} CAN0IDAR6STR;\r
+extern volatile CAN0IDAR6STR _CAN0IDAR6 @(REG_BASE + 0x0000015A);\r
+#define CAN0IDAR6 _CAN0IDAR6.Byte\r
+#define CAN0IDAR6_AC0 _CAN0IDAR6.Bits.AC0\r
+#define CAN0IDAR6_AC1 _CAN0IDAR6.Bits.AC1\r
+#define CAN0IDAR6_AC2 _CAN0IDAR6.Bits.AC2\r
+#define CAN0IDAR6_AC3 _CAN0IDAR6.Bits.AC3\r
+#define CAN0IDAR6_AC4 _CAN0IDAR6.Bits.AC4\r
+#define CAN0IDAR6_AC5 _CAN0IDAR6.Bits.AC5\r
+#define CAN0IDAR6_AC6 _CAN0IDAR6.Bits.AC6\r
+#define CAN0IDAR6_AC7 _CAN0IDAR6.Bits.AC7\r
+#define CAN0IDAR6_AC _CAN0IDAR6.MergedBits.grpAC\r
+\r
+\r
+/*** CAN0IDAR7 - MSCAN 0 Identifier Acceptance Register 7; 0x0000015B ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AC0 :1; /* Acceptance Code Bit 0 */\r
+ byte AC1 :1; /* Acceptance Code Bit 1 */\r
+ byte AC2 :1; /* Acceptance Code Bit 2 */\r
+ byte AC3 :1; /* Acceptance Code Bit 3 */\r
+ byte AC4 :1; /* Acceptance Code Bit 4 */\r
+ byte AC5 :1; /* Acceptance Code Bit 5 */\r
+ byte AC6 :1; /* Acceptance Code Bit 6 */\r
+ byte AC7 :1; /* Acceptance Code Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAC :8;\r
+ } MergedBits;\r
+} CAN0IDAR7STR;\r
+extern volatile CAN0IDAR7STR _CAN0IDAR7 @(REG_BASE + 0x0000015B);\r
+#define CAN0IDAR7 _CAN0IDAR7.Byte\r
+#define CAN0IDAR7_AC0 _CAN0IDAR7.Bits.AC0\r
+#define CAN0IDAR7_AC1 _CAN0IDAR7.Bits.AC1\r
+#define CAN0IDAR7_AC2 _CAN0IDAR7.Bits.AC2\r
+#define CAN0IDAR7_AC3 _CAN0IDAR7.Bits.AC3\r
+#define CAN0IDAR7_AC4 _CAN0IDAR7.Bits.AC4\r
+#define CAN0IDAR7_AC5 _CAN0IDAR7.Bits.AC5\r
+#define CAN0IDAR7_AC6 _CAN0IDAR7.Bits.AC6\r
+#define CAN0IDAR7_AC7 _CAN0IDAR7.Bits.AC7\r
+#define CAN0IDAR7_AC _CAN0IDAR7.MergedBits.grpAC\r
+\r
+\r
+/*** CAN0IDMR4 - MSCAN 0 Identifier Mask Register 4; 0x0000015C ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AM0 :1; /* Acceptance Mask Bit 0 */\r
+ byte AM1 :1; /* Acceptance Mask Bit 1 */\r
+ byte AM2 :1; /* Acceptance Mask Bit 2 */\r
+ byte AM3 :1; /* Acceptance Mask Bit 3 */\r
+ byte AM4 :1; /* Acceptance Mask Bit 4 */\r
+ byte AM5 :1; /* Acceptance Mask Bit 5 */\r
+ byte AM6 :1; /* Acceptance Mask Bit 6 */\r
+ byte AM7 :1; /* Acceptance Mask Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAM :8;\r
+ } MergedBits;\r
+} CAN0IDMR4STR;\r
+extern volatile CAN0IDMR4STR _CAN0IDMR4 @(REG_BASE + 0x0000015C);\r
+#define CAN0IDMR4 _CAN0IDMR4.Byte\r
+#define CAN0IDMR4_AM0 _CAN0IDMR4.Bits.AM0\r
+#define CAN0IDMR4_AM1 _CAN0IDMR4.Bits.AM1\r
+#define CAN0IDMR4_AM2 _CAN0IDMR4.Bits.AM2\r
+#define CAN0IDMR4_AM3 _CAN0IDMR4.Bits.AM3\r
+#define CAN0IDMR4_AM4 _CAN0IDMR4.Bits.AM4\r
+#define CAN0IDMR4_AM5 _CAN0IDMR4.Bits.AM5\r
+#define CAN0IDMR4_AM6 _CAN0IDMR4.Bits.AM6\r
+#define CAN0IDMR4_AM7 _CAN0IDMR4.Bits.AM7\r
+#define CAN0IDMR4_AM _CAN0IDMR4.MergedBits.grpAM\r
+\r
+\r
+/*** CAN0IDMR5 - MSCAN 0 Identifier Mask Register 5; 0x0000015D ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AM0 :1; /* Acceptance Mask Bit 0 */\r
+ byte AM1 :1; /* Acceptance Mask Bit 1 */\r
+ byte AM2 :1; /* Acceptance Mask Bit 2 */\r
+ byte AM3 :1; /* Acceptance Mask Bit 3 */\r
+ byte AM4 :1; /* Acceptance Mask Bit 4 */\r
+ byte AM5 :1; /* Acceptance Mask Bit 5 */\r
+ byte AM6 :1; /* Acceptance Mask Bit 6 */\r
+ byte AM7 :1; /* Acceptance Mask Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAM :8;\r
+ } MergedBits;\r
+} CAN0IDMR5STR;\r
+extern volatile CAN0IDMR5STR _CAN0IDMR5 @(REG_BASE + 0x0000015D);\r
+#define CAN0IDMR5 _CAN0IDMR5.Byte\r
+#define CAN0IDMR5_AM0 _CAN0IDMR5.Bits.AM0\r
+#define CAN0IDMR5_AM1 _CAN0IDMR5.Bits.AM1\r
+#define CAN0IDMR5_AM2 _CAN0IDMR5.Bits.AM2\r
+#define CAN0IDMR5_AM3 _CAN0IDMR5.Bits.AM3\r
+#define CAN0IDMR5_AM4 _CAN0IDMR5.Bits.AM4\r
+#define CAN0IDMR5_AM5 _CAN0IDMR5.Bits.AM5\r
+#define CAN0IDMR5_AM6 _CAN0IDMR5.Bits.AM6\r
+#define CAN0IDMR5_AM7 _CAN0IDMR5.Bits.AM7\r
+#define CAN0IDMR5_AM _CAN0IDMR5.MergedBits.grpAM\r
+\r
+\r
+/*** CAN0IDMR6 - MSCAN 0 Identifier Mask Register 6; 0x0000015E ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AM0 :1; /* Acceptance Mask Bit 0 */\r
+ byte AM1 :1; /* Acceptance Mask Bit 1 */\r
+ byte AM2 :1; /* Acceptance Mask Bit 2 */\r
+ byte AM3 :1; /* Acceptance Mask Bit 3 */\r
+ byte AM4 :1; /* Acceptance Mask Bit 4 */\r
+ byte AM5 :1; /* Acceptance Mask Bit 5 */\r
+ byte AM6 :1; /* Acceptance Mask Bit 6 */\r
+ byte AM7 :1; /* Acceptance Mask Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAM :8;\r
+ } MergedBits;\r
+} CAN0IDMR6STR;\r
+extern volatile CAN0IDMR6STR _CAN0IDMR6 @(REG_BASE + 0x0000015E);\r
+#define CAN0IDMR6 _CAN0IDMR6.Byte\r
+#define CAN0IDMR6_AM0 _CAN0IDMR6.Bits.AM0\r
+#define CAN0IDMR6_AM1 _CAN0IDMR6.Bits.AM1\r
+#define CAN0IDMR6_AM2 _CAN0IDMR6.Bits.AM2\r
+#define CAN0IDMR6_AM3 _CAN0IDMR6.Bits.AM3\r
+#define CAN0IDMR6_AM4 _CAN0IDMR6.Bits.AM4\r
+#define CAN0IDMR6_AM5 _CAN0IDMR6.Bits.AM5\r
+#define CAN0IDMR6_AM6 _CAN0IDMR6.Bits.AM6\r
+#define CAN0IDMR6_AM7 _CAN0IDMR6.Bits.AM7\r
+#define CAN0IDMR6_AM _CAN0IDMR6.MergedBits.grpAM\r
+\r
+\r
+/*** CAN0IDMR7 - MSCAN 0 Identifier Mask Register 7; 0x0000015F ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AM0 :1; /* Acceptance Mask Bit 0 */\r
+ byte AM1 :1; /* Acceptance Mask Bit 1 */\r
+ byte AM2 :1; /* Acceptance Mask Bit 2 */\r
+ byte AM3 :1; /* Acceptance Mask Bit 3 */\r
+ byte AM4 :1; /* Acceptance Mask Bit 4 */\r
+ byte AM5 :1; /* Acceptance Mask Bit 5 */\r
+ byte AM6 :1; /* Acceptance Mask Bit 6 */\r
+ byte AM7 :1; /* Acceptance Mask Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAM :8;\r
+ } MergedBits;\r
+} CAN0IDMR7STR;\r
+extern volatile CAN0IDMR7STR _CAN0IDMR7 @(REG_BASE + 0x0000015F);\r
+#define CAN0IDMR7 _CAN0IDMR7.Byte\r
+#define CAN0IDMR7_AM0 _CAN0IDMR7.Bits.AM0\r
+#define CAN0IDMR7_AM1 _CAN0IDMR7.Bits.AM1\r
+#define CAN0IDMR7_AM2 _CAN0IDMR7.Bits.AM2\r
+#define CAN0IDMR7_AM3 _CAN0IDMR7.Bits.AM3\r
+#define CAN0IDMR7_AM4 _CAN0IDMR7.Bits.AM4\r
+#define CAN0IDMR7_AM5 _CAN0IDMR7.Bits.AM5\r
+#define CAN0IDMR7_AM6 _CAN0IDMR7.Bits.AM6\r
+#define CAN0IDMR7_AM7 _CAN0IDMR7.Bits.AM7\r
+#define CAN0IDMR7_AM _CAN0IDMR7.MergedBits.grpAM\r
+\r
+\r
+/*** CAN0RXIDR0 - MSCAN 0 Receive Identifier Register 0; 0x00000160 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ID21 :1; /* Extended format identifier Bit 21 */\r
+ byte ID22 :1; /* Extended format identifier Bit 22 */\r
+ byte ID23 :1; /* Extended format identifier Bit 23 */\r
+ byte ID24 :1; /* Extended format identifier Bit 24 */\r
+ byte ID25 :1; /* Extended format identifier Bit 25 */\r
+ byte ID26 :1; /* Extended format identifier Bit 26 */\r
+ byte ID27 :1; /* Extended format identifier Bit 27 */\r
+ byte ID28 :1; /* Extended format identifier Bit 28 */\r
+ } Bits;\r
+ struct {\r
+ byte grpID_21 :8;\r
+ } MergedBits;\r
+} CAN0RXIDR0STR;\r
+extern volatile CAN0RXIDR0STR _CAN0RXIDR0 @(REG_BASE + 0x00000160);\r
+#define CAN0RXIDR0 _CAN0RXIDR0.Byte\r
+#define CAN0RXIDR0_ID21 _CAN0RXIDR0.Bits.ID21\r
+#define CAN0RXIDR0_ID22 _CAN0RXIDR0.Bits.ID22\r
+#define CAN0RXIDR0_ID23 _CAN0RXIDR0.Bits.ID23\r
+#define CAN0RXIDR0_ID24 _CAN0RXIDR0.Bits.ID24\r
+#define CAN0RXIDR0_ID25 _CAN0RXIDR0.Bits.ID25\r
+#define CAN0RXIDR0_ID26 _CAN0RXIDR0.Bits.ID26\r
+#define CAN0RXIDR0_ID27 _CAN0RXIDR0.Bits.ID27\r
+#define CAN0RXIDR0_ID28 _CAN0RXIDR0.Bits.ID28\r
+#define CAN0RXIDR0_ID_21 _CAN0RXIDR0.MergedBits.grpID_21\r
+#define CAN0RXIDR0_ID CAN0RXIDR0_ID_21\r
+\r
+\r
+/*** CAN0RXIDR1 - MSCAN 0 Receive Identifier Register 1; 0x00000161 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ID15 :1; /* Extended format identifier Bit 15 */\r
+ byte ID16 :1; /* Extended format identifier Bit 16 */\r
+ byte ID17 :1; /* Extended format identifier Bit 17 */\r
+ byte IDE :1; /* ID Extended */\r
+ byte SRR :1; /* Substitute Remote Request */\r
+ byte ID18 :1; /* Extended format identifier Bit 18 */\r
+ byte ID19 :1; /* Extended format identifier Bit 19 */\r
+ byte ID20 :1; /* Extended format identifier Bit 20 */\r
+ } Bits;\r
+ struct {\r
+ byte grpID_15 :3;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpID_18 :3;\r
+ } MergedBits;\r
+} CAN0RXIDR1STR;\r
+extern volatile CAN0RXIDR1STR _CAN0RXIDR1 @(REG_BASE + 0x00000161);\r
+#define CAN0RXIDR1 _CAN0RXIDR1.Byte\r
+#define CAN0RXIDR1_ID15 _CAN0RXIDR1.Bits.ID15\r
+#define CAN0RXIDR1_ID16 _CAN0RXIDR1.Bits.ID16\r
+#define CAN0RXIDR1_ID17 _CAN0RXIDR1.Bits.ID17\r
+#define CAN0RXIDR1_IDE _CAN0RXIDR1.Bits.IDE\r
+#define CAN0RXIDR1_SRR _CAN0RXIDR1.Bits.SRR\r
+#define CAN0RXIDR1_ID18 _CAN0RXIDR1.Bits.ID18\r
+#define CAN0RXIDR1_ID19 _CAN0RXIDR1.Bits.ID19\r
+#define CAN0RXIDR1_ID20 _CAN0RXIDR1.Bits.ID20\r
+#define CAN0RXIDR1_ID_15 _CAN0RXIDR1.MergedBits.grpID_15\r
+#define CAN0RXIDR1_ID_18 _CAN0RXIDR1.MergedBits.grpID_18\r
+#define CAN0RXIDR1_ID CAN0RXIDR1_ID_15\r
+\r
+\r
+/*** CAN0RXIDR2 - MSCAN 0 Receive Identifier Register 2; 0x00000162 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ID7 :1; /* Extended format identifier Bit 7 */\r
+ byte ID8 :1; /* Extended format identifier Bit 8 */\r
+ byte ID9 :1; /* Extended format identifier Bit 9 */\r
+ byte ID10 :1; /* Extended format identifier Bit 10 */\r
+ byte ID11 :1; /* Extended format identifier Bit 11 */\r
+ byte ID12 :1; /* Extended format identifier Bit 12 */\r
+ byte ID13 :1; /* Extended format identifier Bit 13 */\r
+ byte ID14 :1; /* Extended format identifier Bit 14 */\r
+ } Bits;\r
+ struct {\r
+ byte grpID_7 :8;\r
+ } MergedBits;\r
+} CAN0RXIDR2STR;\r
+extern volatile CAN0RXIDR2STR _CAN0RXIDR2 @(REG_BASE + 0x00000162);\r
+#define CAN0RXIDR2 _CAN0RXIDR2.Byte\r
+#define CAN0RXIDR2_ID7 _CAN0RXIDR2.Bits.ID7\r
+#define CAN0RXIDR2_ID8 _CAN0RXIDR2.Bits.ID8\r
+#define CAN0RXIDR2_ID9 _CAN0RXIDR2.Bits.ID9\r
+#define CAN0RXIDR2_ID10 _CAN0RXIDR2.Bits.ID10\r
+#define CAN0RXIDR2_ID11 _CAN0RXIDR2.Bits.ID11\r
+#define CAN0RXIDR2_ID12 _CAN0RXIDR2.Bits.ID12\r
+#define CAN0RXIDR2_ID13 _CAN0RXIDR2.Bits.ID13\r
+#define CAN0RXIDR2_ID14 _CAN0RXIDR2.Bits.ID14\r
+#define CAN0RXIDR2_ID_7 _CAN0RXIDR2.MergedBits.grpID_7\r
+#define CAN0RXIDR2_ID CAN0RXIDR2_ID_7\r
+\r
+\r
+/*** CAN0RXIDR3 - MSCAN 0 Receive Identifier Register 3; 0x00000163 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte RTR :1; /* Remote Transmission Request */\r
+ byte ID0 :1; /* Extended format identifier Bit 0 */\r
+ byte ID1 :1; /* Extended format identifier Bit 1 */\r
+ byte ID2 :1; /* Extended format identifier Bit 2 */\r
+ byte ID3 :1; /* Extended format identifier Bit 3 */\r
+ byte ID4 :1; /* Extended format identifier Bit 4 */\r
+ byte ID5 :1; /* Extended format identifier Bit 5 */\r
+ byte ID6 :1; /* Extended format identifier Bit 6 */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte grpID :7;\r
+ } MergedBits;\r
+} CAN0RXIDR3STR;\r
+extern volatile CAN0RXIDR3STR _CAN0RXIDR3 @(REG_BASE + 0x00000163);\r
+#define CAN0RXIDR3 _CAN0RXIDR3.Byte\r
+#define CAN0RXIDR3_RTR _CAN0RXIDR3.Bits.RTR\r
+#define CAN0RXIDR3_ID0 _CAN0RXIDR3.Bits.ID0\r
+#define CAN0RXIDR3_ID1 _CAN0RXIDR3.Bits.ID1\r
+#define CAN0RXIDR3_ID2 _CAN0RXIDR3.Bits.ID2\r
+#define CAN0RXIDR3_ID3 _CAN0RXIDR3.Bits.ID3\r
+#define CAN0RXIDR3_ID4 _CAN0RXIDR3.Bits.ID4\r
+#define CAN0RXIDR3_ID5 _CAN0RXIDR3.Bits.ID5\r
+#define CAN0RXIDR3_ID6 _CAN0RXIDR3.Bits.ID6\r
+#define CAN0RXIDR3_ID _CAN0RXIDR3.MergedBits.grpID\r
+\r
+\r
+/*** CAN0RXDSR0 - MSCAN 0 Receive Data Segment Register 0; 0x00000164 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN0RXDSR0STR;\r
+extern volatile CAN0RXDSR0STR _CAN0RXDSR0 @(REG_BASE + 0x00000164);\r
+#define CAN0RXDSR0 _CAN0RXDSR0.Byte\r
+#define CAN0RXDSR0_DB0 _CAN0RXDSR0.Bits.DB0\r
+#define CAN0RXDSR0_DB1 _CAN0RXDSR0.Bits.DB1\r
+#define CAN0RXDSR0_DB2 _CAN0RXDSR0.Bits.DB2\r
+#define CAN0RXDSR0_DB3 _CAN0RXDSR0.Bits.DB3\r
+#define CAN0RXDSR0_DB4 _CAN0RXDSR0.Bits.DB4\r
+#define CAN0RXDSR0_DB5 _CAN0RXDSR0.Bits.DB5\r
+#define CAN0RXDSR0_DB6 _CAN0RXDSR0.Bits.DB6\r
+#define CAN0RXDSR0_DB7 _CAN0RXDSR0.Bits.DB7\r
+#define CAN0RXDSR0_DB _CAN0RXDSR0.MergedBits.grpDB\r
+\r
+\r
+/*** CAN0RXDSR1 - MSCAN 0 Receive Data Segment Register 1; 0x00000165 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN0RXDSR1STR;\r
+extern volatile CAN0RXDSR1STR _CAN0RXDSR1 @(REG_BASE + 0x00000165);\r
+#define CAN0RXDSR1 _CAN0RXDSR1.Byte\r
+#define CAN0RXDSR1_DB0 _CAN0RXDSR1.Bits.DB0\r
+#define CAN0RXDSR1_DB1 _CAN0RXDSR1.Bits.DB1\r
+#define CAN0RXDSR1_DB2 _CAN0RXDSR1.Bits.DB2\r
+#define CAN0RXDSR1_DB3 _CAN0RXDSR1.Bits.DB3\r
+#define CAN0RXDSR1_DB4 _CAN0RXDSR1.Bits.DB4\r
+#define CAN0RXDSR1_DB5 _CAN0RXDSR1.Bits.DB5\r
+#define CAN0RXDSR1_DB6 _CAN0RXDSR1.Bits.DB6\r
+#define CAN0RXDSR1_DB7 _CAN0RXDSR1.Bits.DB7\r
+#define CAN0RXDSR1_DB _CAN0RXDSR1.MergedBits.grpDB\r
+\r
+\r
+/*** CAN0RXDSR2 - MSCAN 0 Receive Data Segment Register 2; 0x00000166 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN0RXDSR2STR;\r
+extern volatile CAN0RXDSR2STR _CAN0RXDSR2 @(REG_BASE + 0x00000166);\r
+#define CAN0RXDSR2 _CAN0RXDSR2.Byte\r
+#define CAN0RXDSR2_DB0 _CAN0RXDSR2.Bits.DB0\r
+#define CAN0RXDSR2_DB1 _CAN0RXDSR2.Bits.DB1\r
+#define CAN0RXDSR2_DB2 _CAN0RXDSR2.Bits.DB2\r
+#define CAN0RXDSR2_DB3 _CAN0RXDSR2.Bits.DB3\r
+#define CAN0RXDSR2_DB4 _CAN0RXDSR2.Bits.DB4\r
+#define CAN0RXDSR2_DB5 _CAN0RXDSR2.Bits.DB5\r
+#define CAN0RXDSR2_DB6 _CAN0RXDSR2.Bits.DB6\r
+#define CAN0RXDSR2_DB7 _CAN0RXDSR2.Bits.DB7\r
+#define CAN0RXDSR2_DB _CAN0RXDSR2.MergedBits.grpDB\r
+\r
+\r
+/*** CAN0RXDSR3 - MSCAN 0 Receive Data Segment Register 3; 0x00000167 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN0RXDSR3STR;\r
+extern volatile CAN0RXDSR3STR _CAN0RXDSR3 @(REG_BASE + 0x00000167);\r
+#define CAN0RXDSR3 _CAN0RXDSR3.Byte\r
+#define CAN0RXDSR3_DB0 _CAN0RXDSR3.Bits.DB0\r
+#define CAN0RXDSR3_DB1 _CAN0RXDSR3.Bits.DB1\r
+#define CAN0RXDSR3_DB2 _CAN0RXDSR3.Bits.DB2\r
+#define CAN0RXDSR3_DB3 _CAN0RXDSR3.Bits.DB3\r
+#define CAN0RXDSR3_DB4 _CAN0RXDSR3.Bits.DB4\r
+#define CAN0RXDSR3_DB5 _CAN0RXDSR3.Bits.DB5\r
+#define CAN0RXDSR3_DB6 _CAN0RXDSR3.Bits.DB6\r
+#define CAN0RXDSR3_DB7 _CAN0RXDSR3.Bits.DB7\r
+#define CAN0RXDSR3_DB _CAN0RXDSR3.MergedBits.grpDB\r
+\r
+\r
+/*** CAN0RXDSR4 - MSCAN 0 Receive Data Segment Register 4; 0x00000168 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN0RXDSR4STR;\r
+extern volatile CAN0RXDSR4STR _CAN0RXDSR4 @(REG_BASE + 0x00000168);\r
+#define CAN0RXDSR4 _CAN0RXDSR4.Byte\r
+#define CAN0RXDSR4_DB0 _CAN0RXDSR4.Bits.DB0\r
+#define CAN0RXDSR4_DB1 _CAN0RXDSR4.Bits.DB1\r
+#define CAN0RXDSR4_DB2 _CAN0RXDSR4.Bits.DB2\r
+#define CAN0RXDSR4_DB3 _CAN0RXDSR4.Bits.DB3\r
+#define CAN0RXDSR4_DB4 _CAN0RXDSR4.Bits.DB4\r
+#define CAN0RXDSR4_DB5 _CAN0RXDSR4.Bits.DB5\r
+#define CAN0RXDSR4_DB6 _CAN0RXDSR4.Bits.DB6\r
+#define CAN0RXDSR4_DB7 _CAN0RXDSR4.Bits.DB7\r
+#define CAN0RXDSR4_DB _CAN0RXDSR4.MergedBits.grpDB\r
+\r
+\r
+/*** CAN0RXDSR5 - MSCAN 0 Receive Data Segment Register 5; 0x00000169 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN0RXDSR5STR;\r
+extern volatile CAN0RXDSR5STR _CAN0RXDSR5 @(REG_BASE + 0x00000169);\r
+#define CAN0RXDSR5 _CAN0RXDSR5.Byte\r
+#define CAN0RXDSR5_DB0 _CAN0RXDSR5.Bits.DB0\r
+#define CAN0RXDSR5_DB1 _CAN0RXDSR5.Bits.DB1\r
+#define CAN0RXDSR5_DB2 _CAN0RXDSR5.Bits.DB2\r
+#define CAN0RXDSR5_DB3 _CAN0RXDSR5.Bits.DB3\r
+#define CAN0RXDSR5_DB4 _CAN0RXDSR5.Bits.DB4\r
+#define CAN0RXDSR5_DB5 _CAN0RXDSR5.Bits.DB5\r
+#define CAN0RXDSR5_DB6 _CAN0RXDSR5.Bits.DB6\r
+#define CAN0RXDSR5_DB7 _CAN0RXDSR5.Bits.DB7\r
+#define CAN0RXDSR5_DB _CAN0RXDSR5.MergedBits.grpDB\r
+\r
+\r
+/*** CAN0RXDSR6 - MSCAN 0 Receive Data Segment Register 6; 0x0000016A ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN0RXDSR6STR;\r
+extern volatile CAN0RXDSR6STR _CAN0RXDSR6 @(REG_BASE + 0x0000016A);\r
+#define CAN0RXDSR6 _CAN0RXDSR6.Byte\r
+#define CAN0RXDSR6_DB0 _CAN0RXDSR6.Bits.DB0\r
+#define CAN0RXDSR6_DB1 _CAN0RXDSR6.Bits.DB1\r
+#define CAN0RXDSR6_DB2 _CAN0RXDSR6.Bits.DB2\r
+#define CAN0RXDSR6_DB3 _CAN0RXDSR6.Bits.DB3\r
+#define CAN0RXDSR6_DB4 _CAN0RXDSR6.Bits.DB4\r
+#define CAN0RXDSR6_DB5 _CAN0RXDSR6.Bits.DB5\r
+#define CAN0RXDSR6_DB6 _CAN0RXDSR6.Bits.DB6\r
+#define CAN0RXDSR6_DB7 _CAN0RXDSR6.Bits.DB7\r
+#define CAN0RXDSR6_DB _CAN0RXDSR6.MergedBits.grpDB\r
+\r
+\r
+/*** CAN0RXDSR7 - MSCAN 0 Receive Data Segment Register 7; 0x0000016B ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN0RXDSR7STR;\r
+extern volatile CAN0RXDSR7STR _CAN0RXDSR7 @(REG_BASE + 0x0000016B);\r
+#define CAN0RXDSR7 _CAN0RXDSR7.Byte\r
+#define CAN0RXDSR7_DB0 _CAN0RXDSR7.Bits.DB0\r
+#define CAN0RXDSR7_DB1 _CAN0RXDSR7.Bits.DB1\r
+#define CAN0RXDSR7_DB2 _CAN0RXDSR7.Bits.DB2\r
+#define CAN0RXDSR7_DB3 _CAN0RXDSR7.Bits.DB3\r
+#define CAN0RXDSR7_DB4 _CAN0RXDSR7.Bits.DB4\r
+#define CAN0RXDSR7_DB5 _CAN0RXDSR7.Bits.DB5\r
+#define CAN0RXDSR7_DB6 _CAN0RXDSR7.Bits.DB6\r
+#define CAN0RXDSR7_DB7 _CAN0RXDSR7.Bits.DB7\r
+#define CAN0RXDSR7_DB _CAN0RXDSR7.MergedBits.grpDB\r
+\r
+\r
+/*** CAN0RXDLR - MSCAN 0 Receive Data Length Register; 0x0000016C ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DLC0 :1; /* Data Length Code Bit 0 */\r
+ byte DLC1 :1; /* Data Length Code Bit 1 */\r
+ byte DLC2 :1; /* Data Length Code Bit 2 */\r
+ byte DLC3 :1; /* Data Length Code Bit 3 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpDLC :4;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CAN0RXDLRSTR;\r
+extern volatile CAN0RXDLRSTR _CAN0RXDLR @(REG_BASE + 0x0000016C);\r
+#define CAN0RXDLR _CAN0RXDLR.Byte\r
+#define CAN0RXDLR_DLC0 _CAN0RXDLR.Bits.DLC0\r
+#define CAN0RXDLR_DLC1 _CAN0RXDLR.Bits.DLC1\r
+#define CAN0RXDLR_DLC2 _CAN0RXDLR.Bits.DLC2\r
+#define CAN0RXDLR_DLC3 _CAN0RXDLR.Bits.DLC3\r
+#define CAN0RXDLR_DLC _CAN0RXDLR.MergedBits.grpDLC\r
+\r
+\r
+/*** CAN0TXIDR0 - MSCAN 0 Transmit Identifier Register 0; 0x00000170 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ID21 :1; /* Extended format identifier Bit 21 */\r
+ byte ID22 :1; /* Extended format identifier Bit 22 */\r
+ byte ID23 :1; /* Extended format identifier Bit 23 */\r
+ byte ID24 :1; /* Extended format identifier Bit 24 */\r
+ byte ID25 :1; /* Extended format identifier Bit 25 */\r
+ byte ID26 :1; /* Extended format identifier Bit 26 */\r
+ byte ID27 :1; /* Extended format identifier Bit 27 */\r
+ byte ID28 :1; /* Extended format identifier Bit 28 */\r
+ } Bits;\r
+ struct {\r
+ byte grpID_21 :8;\r
+ } MergedBits;\r
+} CAN0TXIDR0STR;\r
+extern volatile CAN0TXIDR0STR _CAN0TXIDR0 @(REG_BASE + 0x00000170);\r
+#define CAN0TXIDR0 _CAN0TXIDR0.Byte\r
+#define CAN0TXIDR0_ID21 _CAN0TXIDR0.Bits.ID21\r
+#define CAN0TXIDR0_ID22 _CAN0TXIDR0.Bits.ID22\r
+#define CAN0TXIDR0_ID23 _CAN0TXIDR0.Bits.ID23\r
+#define CAN0TXIDR0_ID24 _CAN0TXIDR0.Bits.ID24\r
+#define CAN0TXIDR0_ID25 _CAN0TXIDR0.Bits.ID25\r
+#define CAN0TXIDR0_ID26 _CAN0TXIDR0.Bits.ID26\r
+#define CAN0TXIDR0_ID27 _CAN0TXIDR0.Bits.ID27\r
+#define CAN0TXIDR0_ID28 _CAN0TXIDR0.Bits.ID28\r
+#define CAN0TXIDR0_ID_21 _CAN0TXIDR0.MergedBits.grpID_21\r
+#define CAN0TXIDR0_ID CAN0TXIDR0_ID_21\r
+\r
+\r
+/*** CAN0TXIDR1 - MSCAN 0 Transmit Identifier Register 1; 0x00000171 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ID15 :1; /* Extended format identifier Bit 15 */\r
+ byte ID16 :1; /* Extended format identifier Bit 16 */\r
+ byte ID17 :1; /* Extended format identifier Bit 17 */\r
+ byte IDE :1; /* ID Extended */\r
+ byte SRR :1; /* Substitute Remote Request */\r
+ byte ID18 :1; /* Extended format identifier Bit 18 */\r
+ byte ID19 :1; /* Extended format identifier Bit 19 */\r
+ byte ID20 :1; /* Extended format identifier Bit 20 */\r
+ } Bits;\r
+ struct {\r
+ byte grpID_15 :3;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpID_18 :3;\r
+ } MergedBits;\r
+} CAN0TXIDR1STR;\r
+extern volatile CAN0TXIDR1STR _CAN0TXIDR1 @(REG_BASE + 0x00000171);\r
+#define CAN0TXIDR1 _CAN0TXIDR1.Byte\r
+#define CAN0TXIDR1_ID15 _CAN0TXIDR1.Bits.ID15\r
+#define CAN0TXIDR1_ID16 _CAN0TXIDR1.Bits.ID16\r
+#define CAN0TXIDR1_ID17 _CAN0TXIDR1.Bits.ID17\r
+#define CAN0TXIDR1_IDE _CAN0TXIDR1.Bits.IDE\r
+#define CAN0TXIDR1_SRR _CAN0TXIDR1.Bits.SRR\r
+#define CAN0TXIDR1_ID18 _CAN0TXIDR1.Bits.ID18\r
+#define CAN0TXIDR1_ID19 _CAN0TXIDR1.Bits.ID19\r
+#define CAN0TXIDR1_ID20 _CAN0TXIDR1.Bits.ID20\r
+#define CAN0TXIDR1_ID_15 _CAN0TXIDR1.MergedBits.grpID_15\r
+#define CAN0TXIDR1_ID_18 _CAN0TXIDR1.MergedBits.grpID_18\r
+#define CAN0TXIDR1_ID CAN0TXIDR1_ID_15\r
+\r
+\r
+/*** CAN0TXIDR2 - MSCAN 0 Transmit Identifier Register 2; 0x00000172 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ID7 :1; /* Extended format identifier Bit 7 */\r
+ byte ID8 :1; /* Extended format identifier Bit 8 */\r
+ byte ID9 :1; /* Extended format identifier Bit 9 */\r
+ byte ID10 :1; /* Extended format identifier Bit 10 */\r
+ byte ID11 :1; /* Extended format identifier Bit 11 */\r
+ byte ID12 :1; /* Extended format identifier Bit 12 */\r
+ byte ID13 :1; /* Extended format identifier Bit 13 */\r
+ byte ID14 :1; /* Extended format identifier Bit 14 */\r
+ } Bits;\r
+ struct {\r
+ byte grpID_7 :8;\r
+ } MergedBits;\r
+} CAN0TXIDR2STR;\r
+extern volatile CAN0TXIDR2STR _CAN0TXIDR2 @(REG_BASE + 0x00000172);\r
+#define CAN0TXIDR2 _CAN0TXIDR2.Byte\r
+#define CAN0TXIDR2_ID7 _CAN0TXIDR2.Bits.ID7\r
+#define CAN0TXIDR2_ID8 _CAN0TXIDR2.Bits.ID8\r
+#define CAN0TXIDR2_ID9 _CAN0TXIDR2.Bits.ID9\r
+#define CAN0TXIDR2_ID10 _CAN0TXIDR2.Bits.ID10\r
+#define CAN0TXIDR2_ID11 _CAN0TXIDR2.Bits.ID11\r
+#define CAN0TXIDR2_ID12 _CAN0TXIDR2.Bits.ID12\r
+#define CAN0TXIDR2_ID13 _CAN0TXIDR2.Bits.ID13\r
+#define CAN0TXIDR2_ID14 _CAN0TXIDR2.Bits.ID14\r
+#define CAN0TXIDR2_ID_7 _CAN0TXIDR2.MergedBits.grpID_7\r
+#define CAN0TXIDR2_ID CAN0TXIDR2_ID_7\r
+\r
+\r
+/*** CAN0TXIDR3 - MSCAN 0 Transmit Identifier Register 3; 0x00000173 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte RTR :1; /* Remote Transmission Request */\r
+ byte ID0 :1; /* Extended format identifier Bit 0 */\r
+ byte ID1 :1; /* Extended format identifier Bit 1 */\r
+ byte ID2 :1; /* Extended format identifier Bit 2 */\r
+ byte ID3 :1; /* Extended format identifier Bit 3 */\r
+ byte ID4 :1; /* Extended format identifier Bit 4 */\r
+ byte ID5 :1; /* Extended format identifier Bit 5 */\r
+ byte ID6 :1; /* Extended format identifier Bit 6 */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte grpID :7;\r
+ } MergedBits;\r
+} CAN0TXIDR3STR;\r
+extern volatile CAN0TXIDR3STR _CAN0TXIDR3 @(REG_BASE + 0x00000173);\r
+#define CAN0TXIDR3 _CAN0TXIDR3.Byte\r
+#define CAN0TXIDR3_RTR _CAN0TXIDR3.Bits.RTR\r
+#define CAN0TXIDR3_ID0 _CAN0TXIDR3.Bits.ID0\r
+#define CAN0TXIDR3_ID1 _CAN0TXIDR3.Bits.ID1\r
+#define CAN0TXIDR3_ID2 _CAN0TXIDR3.Bits.ID2\r
+#define CAN0TXIDR3_ID3 _CAN0TXIDR3.Bits.ID3\r
+#define CAN0TXIDR3_ID4 _CAN0TXIDR3.Bits.ID4\r
+#define CAN0TXIDR3_ID5 _CAN0TXIDR3.Bits.ID5\r
+#define CAN0TXIDR3_ID6 _CAN0TXIDR3.Bits.ID6\r
+#define CAN0TXIDR3_ID _CAN0TXIDR3.MergedBits.grpID\r
+\r
+\r
+/*** CAN0TXDSR0 - MSCAN 0 Transmit Data Segment Register 0; 0x00000174 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN0TXDSR0STR;\r
+extern volatile CAN0TXDSR0STR _CAN0TXDSR0 @(REG_BASE + 0x00000174);\r
+#define CAN0TXDSR0 _CAN0TXDSR0.Byte\r
+#define CAN0TXDSR0_DB0 _CAN0TXDSR0.Bits.DB0\r
+#define CAN0TXDSR0_DB1 _CAN0TXDSR0.Bits.DB1\r
+#define CAN0TXDSR0_DB2 _CAN0TXDSR0.Bits.DB2\r
+#define CAN0TXDSR0_DB3 _CAN0TXDSR0.Bits.DB3\r
+#define CAN0TXDSR0_DB4 _CAN0TXDSR0.Bits.DB4\r
+#define CAN0TXDSR0_DB5 _CAN0TXDSR0.Bits.DB5\r
+#define CAN0TXDSR0_DB6 _CAN0TXDSR0.Bits.DB6\r
+#define CAN0TXDSR0_DB7 _CAN0TXDSR0.Bits.DB7\r
+#define CAN0TXDSR0_DB _CAN0TXDSR0.MergedBits.grpDB\r
+\r
+\r
+/*** CAN0TXDSR1 - MSCAN 0 Transmit Data Segment Register 1; 0x00000175 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN0TXDSR1STR;\r
+extern volatile CAN0TXDSR1STR _CAN0TXDSR1 @(REG_BASE + 0x00000175);\r
+#define CAN0TXDSR1 _CAN0TXDSR1.Byte\r
+#define CAN0TXDSR1_DB0 _CAN0TXDSR1.Bits.DB0\r
+#define CAN0TXDSR1_DB1 _CAN0TXDSR1.Bits.DB1\r
+#define CAN0TXDSR1_DB2 _CAN0TXDSR1.Bits.DB2\r
+#define CAN0TXDSR1_DB3 _CAN0TXDSR1.Bits.DB3\r
+#define CAN0TXDSR1_DB4 _CAN0TXDSR1.Bits.DB4\r
+#define CAN0TXDSR1_DB5 _CAN0TXDSR1.Bits.DB5\r
+#define CAN0TXDSR1_DB6 _CAN0TXDSR1.Bits.DB6\r
+#define CAN0TXDSR1_DB7 _CAN0TXDSR1.Bits.DB7\r
+#define CAN0TXDSR1_DB _CAN0TXDSR1.MergedBits.grpDB\r
+\r
+\r
+/*** CAN0TXDSR2 - MSCAN 0 Transmit Data Segment Register 2; 0x00000176 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN0TXDSR2STR;\r
+extern volatile CAN0TXDSR2STR _CAN0TXDSR2 @(REG_BASE + 0x00000176);\r
+#define CAN0TXDSR2 _CAN0TXDSR2.Byte\r
+#define CAN0TXDSR2_DB0 _CAN0TXDSR2.Bits.DB0\r
+#define CAN0TXDSR2_DB1 _CAN0TXDSR2.Bits.DB1\r
+#define CAN0TXDSR2_DB2 _CAN0TXDSR2.Bits.DB2\r
+#define CAN0TXDSR2_DB3 _CAN0TXDSR2.Bits.DB3\r
+#define CAN0TXDSR2_DB4 _CAN0TXDSR2.Bits.DB4\r
+#define CAN0TXDSR2_DB5 _CAN0TXDSR2.Bits.DB5\r
+#define CAN0TXDSR2_DB6 _CAN0TXDSR2.Bits.DB6\r
+#define CAN0TXDSR2_DB7 _CAN0TXDSR2.Bits.DB7\r
+#define CAN0TXDSR2_DB _CAN0TXDSR2.MergedBits.grpDB\r
+\r
+\r
+/*** CAN0TXDSR3 - MSCAN 0 Transmit Data Segment Register 3; 0x00000177 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN0TXDSR3STR;\r
+extern volatile CAN0TXDSR3STR _CAN0TXDSR3 @(REG_BASE + 0x00000177);\r
+#define CAN0TXDSR3 _CAN0TXDSR3.Byte\r
+#define CAN0TXDSR3_DB0 _CAN0TXDSR3.Bits.DB0\r
+#define CAN0TXDSR3_DB1 _CAN0TXDSR3.Bits.DB1\r
+#define CAN0TXDSR3_DB2 _CAN0TXDSR3.Bits.DB2\r
+#define CAN0TXDSR3_DB3 _CAN0TXDSR3.Bits.DB3\r
+#define CAN0TXDSR3_DB4 _CAN0TXDSR3.Bits.DB4\r
+#define CAN0TXDSR3_DB5 _CAN0TXDSR3.Bits.DB5\r
+#define CAN0TXDSR3_DB6 _CAN0TXDSR3.Bits.DB6\r
+#define CAN0TXDSR3_DB7 _CAN0TXDSR3.Bits.DB7\r
+#define CAN0TXDSR3_DB _CAN0TXDSR3.MergedBits.grpDB\r
+\r
+\r
+/*** CAN0TXDSR4 - MSCAN 0 Transmit Data Segment Register 4; 0x00000178 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN0TXDSR4STR;\r
+extern volatile CAN0TXDSR4STR _CAN0TXDSR4 @(REG_BASE + 0x00000178);\r
+#define CAN0TXDSR4 _CAN0TXDSR4.Byte\r
+#define CAN0TXDSR4_DB0 _CAN0TXDSR4.Bits.DB0\r
+#define CAN0TXDSR4_DB1 _CAN0TXDSR4.Bits.DB1\r
+#define CAN0TXDSR4_DB2 _CAN0TXDSR4.Bits.DB2\r
+#define CAN0TXDSR4_DB3 _CAN0TXDSR4.Bits.DB3\r
+#define CAN0TXDSR4_DB4 _CAN0TXDSR4.Bits.DB4\r
+#define CAN0TXDSR4_DB5 _CAN0TXDSR4.Bits.DB5\r
+#define CAN0TXDSR4_DB6 _CAN0TXDSR4.Bits.DB6\r
+#define CAN0TXDSR4_DB7 _CAN0TXDSR4.Bits.DB7\r
+#define CAN0TXDSR4_DB _CAN0TXDSR4.MergedBits.grpDB\r
+\r
+\r
+/*** CAN0TXDSR5 - MSCAN 0 Transmit Data Segment Register 5; 0x00000179 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN0TXDSR5STR;\r
+extern volatile CAN0TXDSR5STR _CAN0TXDSR5 @(REG_BASE + 0x00000179);\r
+#define CAN0TXDSR5 _CAN0TXDSR5.Byte\r
+#define CAN0TXDSR5_DB0 _CAN0TXDSR5.Bits.DB0\r
+#define CAN0TXDSR5_DB1 _CAN0TXDSR5.Bits.DB1\r
+#define CAN0TXDSR5_DB2 _CAN0TXDSR5.Bits.DB2\r
+#define CAN0TXDSR5_DB3 _CAN0TXDSR5.Bits.DB3\r
+#define CAN0TXDSR5_DB4 _CAN0TXDSR5.Bits.DB4\r
+#define CAN0TXDSR5_DB5 _CAN0TXDSR5.Bits.DB5\r
+#define CAN0TXDSR5_DB6 _CAN0TXDSR5.Bits.DB6\r
+#define CAN0TXDSR5_DB7 _CAN0TXDSR5.Bits.DB7\r
+#define CAN0TXDSR5_DB _CAN0TXDSR5.MergedBits.grpDB\r
+\r
+\r
+/*** CAN0TXDSR6 - MSCAN 0 Transmit Data Segment Register 6; 0x0000017A ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN0TXDSR6STR;\r
+extern volatile CAN0TXDSR6STR _CAN0TXDSR6 @(REG_BASE + 0x0000017A);\r
+#define CAN0TXDSR6 _CAN0TXDSR6.Byte\r
+#define CAN0TXDSR6_DB0 _CAN0TXDSR6.Bits.DB0\r
+#define CAN0TXDSR6_DB1 _CAN0TXDSR6.Bits.DB1\r
+#define CAN0TXDSR6_DB2 _CAN0TXDSR6.Bits.DB2\r
+#define CAN0TXDSR6_DB3 _CAN0TXDSR6.Bits.DB3\r
+#define CAN0TXDSR6_DB4 _CAN0TXDSR6.Bits.DB4\r
+#define CAN0TXDSR6_DB5 _CAN0TXDSR6.Bits.DB5\r
+#define CAN0TXDSR6_DB6 _CAN0TXDSR6.Bits.DB6\r
+#define CAN0TXDSR6_DB7 _CAN0TXDSR6.Bits.DB7\r
+#define CAN0TXDSR6_DB _CAN0TXDSR6.MergedBits.grpDB\r
+\r
+\r
+/*** CAN0TXDSR7 - MSCAN 0 Transmit Data Segment Register 7; 0x0000017B ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN0TXDSR7STR;\r
+extern volatile CAN0TXDSR7STR _CAN0TXDSR7 @(REG_BASE + 0x0000017B);\r
+#define CAN0TXDSR7 _CAN0TXDSR7.Byte\r
+#define CAN0TXDSR7_DB0 _CAN0TXDSR7.Bits.DB0\r
+#define CAN0TXDSR7_DB1 _CAN0TXDSR7.Bits.DB1\r
+#define CAN0TXDSR7_DB2 _CAN0TXDSR7.Bits.DB2\r
+#define CAN0TXDSR7_DB3 _CAN0TXDSR7.Bits.DB3\r
+#define CAN0TXDSR7_DB4 _CAN0TXDSR7.Bits.DB4\r
+#define CAN0TXDSR7_DB5 _CAN0TXDSR7.Bits.DB5\r
+#define CAN0TXDSR7_DB6 _CAN0TXDSR7.Bits.DB6\r
+#define CAN0TXDSR7_DB7 _CAN0TXDSR7.Bits.DB7\r
+#define CAN0TXDSR7_DB _CAN0TXDSR7.MergedBits.grpDB\r
+\r
+\r
+/*** CAN0TXDLR - MSCAN 0 Transmit Data Length Register; 0x0000017C ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DLC0 :1; /* Data Length Code Bit 0 */\r
+ byte DLC1 :1; /* Data Length Code Bit 1 */\r
+ byte DLC2 :1; /* Data Length Code Bit 2 */\r
+ byte DLC3 :1; /* Data Length Code Bit 3 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpDLC :4;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CAN0TXDLRSTR;\r
+extern volatile CAN0TXDLRSTR _CAN0TXDLR @(REG_BASE + 0x0000017C);\r
+#define CAN0TXDLR _CAN0TXDLR.Byte\r
+#define CAN0TXDLR_DLC0 _CAN0TXDLR.Bits.DLC0\r
+#define CAN0TXDLR_DLC1 _CAN0TXDLR.Bits.DLC1\r
+#define CAN0TXDLR_DLC2 _CAN0TXDLR.Bits.DLC2\r
+#define CAN0TXDLR_DLC3 _CAN0TXDLR.Bits.DLC3\r
+#define CAN0TXDLR_DLC _CAN0TXDLR.MergedBits.grpDLC\r
+\r
+\r
+/*** CAN0TXTBPR - MSCAN 0 Transmit Buffer Priority; 0x0000017F ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PRIO0 :1; /* Transmit Buffer Priority Bit 0 */\r
+ byte PRIO1 :1; /* Transmit Buffer Priority Bit 1 */\r
+ byte PRIO2 :1; /* Transmit Buffer Priority Bit 2 */\r
+ byte PRIO3 :1; /* Transmit Buffer Priority Bit 3 */\r
+ byte PRIO4 :1; /* Transmit Buffer Priority Bit 4 */\r
+ byte PRIO5 :1; /* Transmit Buffer Priority Bit 5 */\r
+ byte PRIO6 :1; /* Transmit Buffer Priority Bit 6 */\r
+ byte PRIO7 :1; /* Transmit Buffer Priority Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpPRIO :8;\r
+ } MergedBits;\r
+} CAN0TXTBPRSTR;\r
+extern volatile CAN0TXTBPRSTR _CAN0TXTBPR @(REG_BASE + 0x0000017F);\r
+#define CAN0TXTBPR _CAN0TXTBPR.Byte\r
+#define CAN0TXTBPR_PRIO0 _CAN0TXTBPR.Bits.PRIO0\r
+#define CAN0TXTBPR_PRIO1 _CAN0TXTBPR.Bits.PRIO1\r
+#define CAN0TXTBPR_PRIO2 _CAN0TXTBPR.Bits.PRIO2\r
+#define CAN0TXTBPR_PRIO3 _CAN0TXTBPR.Bits.PRIO3\r
+#define CAN0TXTBPR_PRIO4 _CAN0TXTBPR.Bits.PRIO4\r
+#define CAN0TXTBPR_PRIO5 _CAN0TXTBPR.Bits.PRIO5\r
+#define CAN0TXTBPR_PRIO6 _CAN0TXTBPR.Bits.PRIO6\r
+#define CAN0TXTBPR_PRIO7 _CAN0TXTBPR.Bits.PRIO7\r
+#define CAN0TXTBPR_PRIO _CAN0TXTBPR.MergedBits.grpPRIO\r
+\r
+\r
+/*** CAN1CTL0 - MSCAN 1 Control 0 Register; 0x00000180 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte INITRQ :1; /* Initialization Mode Request */\r
+ byte SLPRQ :1; /* Sleep Mode Request */\r
+ byte WUPE :1; /* Wake-Up Enable */\r
+ byte TIME :1; /* Timer Enable */\r
+ byte SYNCH :1; /* Synchronized Status */\r
+ byte CSWAI :1; /* CAN Stops in Wait Mode */\r
+ byte RXACT :1; /* Receiver Active Status */\r
+ byte RXFRM :1; /* Received Frame Flag */\r
+ } Bits;\r
+} CAN1CTL0STR;\r
+extern volatile CAN1CTL0STR _CAN1CTL0 @(REG_BASE + 0x00000180);\r
+#define CAN1CTL0 _CAN1CTL0.Byte\r
+#define CAN1CTL0_INITRQ _CAN1CTL0.Bits.INITRQ\r
+#define CAN1CTL0_SLPRQ _CAN1CTL0.Bits.SLPRQ\r
+#define CAN1CTL0_WUPE _CAN1CTL0.Bits.WUPE\r
+#define CAN1CTL0_TIME _CAN1CTL0.Bits.TIME\r
+#define CAN1CTL0_SYNCH _CAN1CTL0.Bits.SYNCH\r
+#define CAN1CTL0_CSWAI _CAN1CTL0.Bits.CSWAI\r
+#define CAN1CTL0_RXACT _CAN1CTL0.Bits.RXACT\r
+#define CAN1CTL0_RXFRM _CAN1CTL0.Bits.RXFRM\r
+\r
+\r
+/*** CAN1CTL1 - MSCAN 1 Control 1 Register; 0x00000181 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte INITAK :1; /* Initialization Mode Acknowledge */\r
+ byte SLPAK :1; /* Sleep Mode Acknowledge */\r
+ byte WUPM :1; /* Wake-Up Mode */\r
+ byte :1; \r
+ byte LISTEN :1; /* Listen Only Mode */\r
+ byte LOOPB :1; /* Loop Back Self Test Mode */\r
+ byte CLKSRC :1; /* MSCAN 1 Clock Source */\r
+ byte CANE :1; /* MSCAN 1 Enable */\r
+ } Bits;\r
+} CAN1CTL1STR;\r
+extern volatile CAN1CTL1STR _CAN1CTL1 @(REG_BASE + 0x00000181);\r
+#define CAN1CTL1 _CAN1CTL1.Byte\r
+#define CAN1CTL1_INITAK _CAN1CTL1.Bits.INITAK\r
+#define CAN1CTL1_SLPAK _CAN1CTL1.Bits.SLPAK\r
+#define CAN1CTL1_WUPM _CAN1CTL1.Bits.WUPM\r
+#define CAN1CTL1_LISTEN _CAN1CTL1.Bits.LISTEN\r
+#define CAN1CTL1_LOOPB _CAN1CTL1.Bits.LOOPB\r
+#define CAN1CTL1_CLKSRC _CAN1CTL1.Bits.CLKSRC\r
+#define CAN1CTL1_CANE _CAN1CTL1.Bits.CANE\r
+\r
+\r
+/*** CAN1BTR0 - MSCAN 1 Bus Timing Register 0; 0x00000182 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte BRP0 :1; /* Baud Rate Prescaler 0 */\r
+ byte BRP1 :1; /* Baud Rate Prescaler 1 */\r
+ byte BRP2 :1; /* Baud Rate Prescaler 2 */\r
+ byte BRP3 :1; /* Baud Rate Prescaler 3 */\r
+ byte BRP4 :1; /* Baud Rate Prescaler 4 */\r
+ byte BRP5 :1; /* Baud Rate Prescaler 5 */\r
+ byte SJW0 :1; /* Synchronization Jump Width 0 */\r
+ byte SJW1 :1; /* Synchronization Jump Width 1 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBRP :6;\r
+ byte grpSJW :2;\r
+ } MergedBits;\r
+} CAN1BTR0STR;\r
+extern volatile CAN1BTR0STR _CAN1BTR0 @(REG_BASE + 0x00000182);\r
+#define CAN1BTR0 _CAN1BTR0.Byte\r
+#define CAN1BTR0_BRP0 _CAN1BTR0.Bits.BRP0\r
+#define CAN1BTR0_BRP1 _CAN1BTR0.Bits.BRP1\r
+#define CAN1BTR0_BRP2 _CAN1BTR0.Bits.BRP2\r
+#define CAN1BTR0_BRP3 _CAN1BTR0.Bits.BRP3\r
+#define CAN1BTR0_BRP4 _CAN1BTR0.Bits.BRP4\r
+#define CAN1BTR0_BRP5 _CAN1BTR0.Bits.BRP5\r
+#define CAN1BTR0_SJW0 _CAN1BTR0.Bits.SJW0\r
+#define CAN1BTR0_SJW1 _CAN1BTR0.Bits.SJW1\r
+#define CAN1BTR0_BRP _CAN1BTR0.MergedBits.grpBRP\r
+#define CAN1BTR0_SJW _CAN1BTR0.MergedBits.grpSJW\r
+\r
+\r
+/*** CAN1BTR1 - MSCAN 1 Bus Timing Register 1; 0x00000183 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte TSEG10 :1; /* Time Segment 1 */\r
+ byte TSEG11 :1; /* Time Segment 1 */\r
+ byte TSEG12 :1; /* Time Segment 1 */\r
+ byte TSEG13 :1; /* Time Segment 1 */\r
+ byte TSEG20 :1; /* Time Segment 2 */\r
+ byte TSEG21 :1; /* Time Segment 2 */\r
+ byte TSEG22 :1; /* Time Segment 2 */\r
+ byte SAMP :1; /* Sampling */\r
+ } Bits;\r
+ struct {\r
+ byte grpTSEG_10 :4;\r
+ byte grpTSEG_20 :3;\r
+ byte :1;\r
+ } MergedBits;\r
+} CAN1BTR1STR;\r
+extern volatile CAN1BTR1STR _CAN1BTR1 @(REG_BASE + 0x00000183);\r
+#define CAN1BTR1 _CAN1BTR1.Byte\r
+#define CAN1BTR1_TSEG10 _CAN1BTR1.Bits.TSEG10\r
+#define CAN1BTR1_TSEG11 _CAN1BTR1.Bits.TSEG11\r
+#define CAN1BTR1_TSEG12 _CAN1BTR1.Bits.TSEG12\r
+#define CAN1BTR1_TSEG13 _CAN1BTR1.Bits.TSEG13\r
+#define CAN1BTR1_TSEG20 _CAN1BTR1.Bits.TSEG20\r
+#define CAN1BTR1_TSEG21 _CAN1BTR1.Bits.TSEG21\r
+#define CAN1BTR1_TSEG22 _CAN1BTR1.Bits.TSEG22\r
+#define CAN1BTR1_SAMP _CAN1BTR1.Bits.SAMP\r
+#define CAN1BTR1_TSEG_10 _CAN1BTR1.MergedBits.grpTSEG_10\r
+#define CAN1BTR1_TSEG_20 _CAN1BTR1.MergedBits.grpTSEG_20\r
+#define CAN1BTR1_TSEG CAN1BTR1_TSEG_10\r
+\r
+\r
+/*** CAN1RFLG - MSCAN 1 Receiver Flag Register; 0x00000184 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte RXF :1; /* Receive Buffer Full */\r
+ byte OVRIF :1; /* Overrun Interrupt Flag */\r
+ byte TSTAT0 :1; /* Transmitter Status Bit 0 */\r
+ byte TSTAT1 :1; /* Transmitter Status Bit 1 */\r
+ byte RSTAT0 :1; /* Receiver Status Bit 0 */\r
+ byte RSTAT1 :1; /* Receiver Status Bit 1 */\r
+ byte CSCIF :1; /* CAN Status Change Interrupt Flag */\r
+ byte WUPIF :1; /* Wake-up Interrupt Flag */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte grpTSTAT :2;\r
+ byte grpRSTAT :2;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CAN1RFLGSTR;\r
+extern volatile CAN1RFLGSTR _CAN1RFLG @(REG_BASE + 0x00000184);\r
+#define CAN1RFLG _CAN1RFLG.Byte\r
+#define CAN1RFLG_RXF _CAN1RFLG.Bits.RXF\r
+#define CAN1RFLG_OVRIF _CAN1RFLG.Bits.OVRIF\r
+#define CAN1RFLG_TSTAT0 _CAN1RFLG.Bits.TSTAT0\r
+#define CAN1RFLG_TSTAT1 _CAN1RFLG.Bits.TSTAT1\r
+#define CAN1RFLG_RSTAT0 _CAN1RFLG.Bits.RSTAT0\r
+#define CAN1RFLG_RSTAT1 _CAN1RFLG.Bits.RSTAT1\r
+#define CAN1RFLG_CSCIF _CAN1RFLG.Bits.CSCIF\r
+#define CAN1RFLG_WUPIF _CAN1RFLG.Bits.WUPIF\r
+#define CAN1RFLG_TSTAT _CAN1RFLG.MergedBits.grpTSTAT\r
+#define CAN1RFLG_RSTAT _CAN1RFLG.MergedBits.grpRSTAT\r
+\r
+\r
+/*** CAN1RIER - MSCAN 1 Receiver Interrupt Enable Register; 0x00000185 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte RXFIE :1; /* Receiver Full Interrupt Enable */\r
+ byte OVRIE :1; /* Overrun Interrupt Enable */\r
+ byte TSTATE0 :1; /* Transmitter Status Change Enable 0 */\r
+ byte TSTATE1 :1; /* Transmitter Status Change Enable 1 */\r
+ byte RSTATE0 :1; /* Receiver Status Change Enable 0 */\r
+ byte RSTATE1 :1; /* Receiver Status Change Enable 1 */\r
+ byte CSCIE :1; /* CAN Status Change Interrupt Enable */\r
+ byte WUPIE :1; /* Wake-up Interrupt Enable */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte grpTSTATE :2;\r
+ byte grpRSTATE :2;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CAN1RIERSTR;\r
+extern volatile CAN1RIERSTR _CAN1RIER @(REG_BASE + 0x00000185);\r
+#define CAN1RIER _CAN1RIER.Byte\r
+#define CAN1RIER_RXFIE _CAN1RIER.Bits.RXFIE\r
+#define CAN1RIER_OVRIE _CAN1RIER.Bits.OVRIE\r
+#define CAN1RIER_TSTATE0 _CAN1RIER.Bits.TSTATE0\r
+#define CAN1RIER_TSTATE1 _CAN1RIER.Bits.TSTATE1\r
+#define CAN1RIER_RSTATE0 _CAN1RIER.Bits.RSTATE0\r
+#define CAN1RIER_RSTATE1 _CAN1RIER.Bits.RSTATE1\r
+#define CAN1RIER_CSCIE _CAN1RIER.Bits.CSCIE\r
+#define CAN1RIER_WUPIE _CAN1RIER.Bits.WUPIE\r
+#define CAN1RIER_TSTATE _CAN1RIER.MergedBits.grpTSTATE\r
+#define CAN1RIER_RSTATE _CAN1RIER.MergedBits.grpRSTATE\r
+\r
+\r
+/*** CAN1TFLG - MSCAN 1 Transmitter Flag Register; 0x00000186 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte TXE0 :1; /* Transmitter Buffer Empty 0 */\r
+ byte TXE1 :1; /* Transmitter Buffer Empty 1 */\r
+ byte TXE2 :1; /* Transmitter Buffer Empty 2 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpTXE :3;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CAN1TFLGSTR;\r
+extern volatile CAN1TFLGSTR _CAN1TFLG @(REG_BASE + 0x00000186);\r
+#define CAN1TFLG _CAN1TFLG.Byte\r
+#define CAN1TFLG_TXE0 _CAN1TFLG.Bits.TXE0\r
+#define CAN1TFLG_TXE1 _CAN1TFLG.Bits.TXE1\r
+#define CAN1TFLG_TXE2 _CAN1TFLG.Bits.TXE2\r
+#define CAN1TFLG_TXE _CAN1TFLG.MergedBits.grpTXE\r
+\r
+\r
+/*** CAN1TIER - MSCAN 1 Transmitter Interrupt Enable Register; 0x00000187 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte TXEIE0 :1; /* Transmitter Empty Interrupt Enable 0 */\r
+ byte TXEIE1 :1; /* Transmitter Empty Interrupt Enable 1 */\r
+ byte TXEIE2 :1; /* Transmitter Empty Interrupt Enable 2 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpTXEIE :3;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CAN1TIERSTR;\r
+extern volatile CAN1TIERSTR _CAN1TIER @(REG_BASE + 0x00000187);\r
+#define CAN1TIER _CAN1TIER.Byte\r
+#define CAN1TIER_TXEIE0 _CAN1TIER.Bits.TXEIE0\r
+#define CAN1TIER_TXEIE1 _CAN1TIER.Bits.TXEIE1\r
+#define CAN1TIER_TXEIE2 _CAN1TIER.Bits.TXEIE2\r
+#define CAN1TIER_TXEIE _CAN1TIER.MergedBits.grpTXEIE\r
+\r
+\r
+/*** CAN1TARQ - MSCAN 1 Transmitter Message Abort Request; 0x00000188 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ABTRQ0 :1; /* Abort Request 0 */\r
+ byte ABTRQ1 :1; /* Abort Request 1 */\r
+ byte ABTRQ2 :1; /* Abort Request 2 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpABTRQ :3;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CAN1TARQSTR;\r
+extern volatile CAN1TARQSTR _CAN1TARQ @(REG_BASE + 0x00000188);\r
+#define CAN1TARQ _CAN1TARQ.Byte\r
+#define CAN1TARQ_ABTRQ0 _CAN1TARQ.Bits.ABTRQ0\r
+#define CAN1TARQ_ABTRQ1 _CAN1TARQ.Bits.ABTRQ1\r
+#define CAN1TARQ_ABTRQ2 _CAN1TARQ.Bits.ABTRQ2\r
+#define CAN1TARQ_ABTRQ _CAN1TARQ.MergedBits.grpABTRQ\r
+\r
+\r
+/*** CAN1TAAK - MSCAN 1 Transmitter Message Abort Control; 0x00000189 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ABTAK0 :1; /* Abort Acknowledge 0 */\r
+ byte ABTAK1 :1; /* Abort Acknowledge 1 */\r
+ byte ABTAK2 :1; /* Abort Acknowledge 2 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpABTAK :3;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CAN1TAAKSTR;\r
+extern volatile CAN1TAAKSTR _CAN1TAAK @(REG_BASE + 0x00000189);\r
+#define CAN1TAAK _CAN1TAAK.Byte\r
+#define CAN1TAAK_ABTAK0 _CAN1TAAK.Bits.ABTAK0\r
+#define CAN1TAAK_ABTAK1 _CAN1TAAK.Bits.ABTAK1\r
+#define CAN1TAAK_ABTAK2 _CAN1TAAK.Bits.ABTAK2\r
+#define CAN1TAAK_ABTAK _CAN1TAAK.MergedBits.grpABTAK\r
+\r
+\r
+/*** CAN1TBSEL - MSCAN 1 Transmit Buffer Selection; 0x0000018A ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte TX0 :1; /* Transmit Buffer Select 0 */\r
+ byte TX1 :1; /* Transmit Buffer Select 1 */\r
+ byte TX2 :1; /* Transmit Buffer Select 2 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpTX :3;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CAN1TBSELSTR;\r
+extern volatile CAN1TBSELSTR _CAN1TBSEL @(REG_BASE + 0x0000018A);\r
+#define CAN1TBSEL _CAN1TBSEL.Byte\r
+#define CAN1TBSEL_TX0 _CAN1TBSEL.Bits.TX0\r
+#define CAN1TBSEL_TX1 _CAN1TBSEL.Bits.TX1\r
+#define CAN1TBSEL_TX2 _CAN1TBSEL.Bits.TX2\r
+#define CAN1TBSEL_TX _CAN1TBSEL.MergedBits.grpTX\r
+\r
+\r
+/*** CAN1IDAC - MSCAN 1 Identifier Acceptance Control Register; 0x0000018B ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte IDHIT0 :1; /* Identifier Acceptance Hit Indicator 0 */\r
+ byte IDHIT1 :1; /* Identifier Acceptance Hit Indicator 1 */\r
+ byte IDHIT2 :1; /* Identifier Acceptance Hit Indicator 2 */\r
+ byte :1; \r
+ byte IDAM0 :1; /* Identifier Acceptance Mode 0 */\r
+ byte IDAM1 :1; /* Identifier Acceptance Mode 1 */\r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpIDHIT :3;\r
+ byte :1;\r
+ byte grpIDAM :2;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CAN1IDACSTR;\r
+extern volatile CAN1IDACSTR _CAN1IDAC @(REG_BASE + 0x0000018B);\r
+#define CAN1IDAC _CAN1IDAC.Byte\r
+#define CAN1IDAC_IDHIT0 _CAN1IDAC.Bits.IDHIT0\r
+#define CAN1IDAC_IDHIT1 _CAN1IDAC.Bits.IDHIT1\r
+#define CAN1IDAC_IDHIT2 _CAN1IDAC.Bits.IDHIT2\r
+#define CAN1IDAC_IDAM0 _CAN1IDAC.Bits.IDAM0\r
+#define CAN1IDAC_IDAM1 _CAN1IDAC.Bits.IDAM1\r
+#define CAN1IDAC_IDHIT _CAN1IDAC.MergedBits.grpIDHIT\r
+#define CAN1IDAC_IDAM _CAN1IDAC.MergedBits.grpIDAM\r
+\r
+\r
+/*** CAN1RXERR - MSCAN 1 Receive Error Counter Register; 0x0000018E ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte RXERR0 :1; /* Bit 0 */\r
+ byte RXERR1 :1; /* Bit 1 */\r
+ byte RXERR2 :1; /* Bit 2 */\r
+ byte RXERR3 :1; /* Bit 3 */\r
+ byte RXERR4 :1; /* Bit 4 */\r
+ byte RXERR5 :1; /* Bit 5 */\r
+ byte RXERR6 :1; /* Bit 6 */\r
+ byte RXERR7 :1; /* Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpRXERR :8;\r
+ } MergedBits;\r
+} CAN1RXERRSTR;\r
+extern volatile CAN1RXERRSTR _CAN1RXERR @(REG_BASE + 0x0000018E);\r
+#define CAN1RXERR _CAN1RXERR.Byte\r
+#define CAN1RXERR_RXERR0 _CAN1RXERR.Bits.RXERR0\r
+#define CAN1RXERR_RXERR1 _CAN1RXERR.Bits.RXERR1\r
+#define CAN1RXERR_RXERR2 _CAN1RXERR.Bits.RXERR2\r
+#define CAN1RXERR_RXERR3 _CAN1RXERR.Bits.RXERR3\r
+#define CAN1RXERR_RXERR4 _CAN1RXERR.Bits.RXERR4\r
+#define CAN1RXERR_RXERR5 _CAN1RXERR.Bits.RXERR5\r
+#define CAN1RXERR_RXERR6 _CAN1RXERR.Bits.RXERR6\r
+#define CAN1RXERR_RXERR7 _CAN1RXERR.Bits.RXERR7\r
+#define CAN1RXERR_RXERR _CAN1RXERR.MergedBits.grpRXERR\r
+\r
+\r
+/*** CAN1TXERR - MSCAN 1 Transmit Error Counter Register; 0x0000018F ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte TXERR0 :1; /* Bit 0 */\r
+ byte TXERR1 :1; /* Bit 1 */\r
+ byte TXERR2 :1; /* Bit 2 */\r
+ byte TXERR3 :1; /* Bit 3 */\r
+ byte TXERR4 :1; /* Bit 4 */\r
+ byte TXERR5 :1; /* Bit 5 */\r
+ byte TXERR6 :1; /* Bit 6 */\r
+ byte TXERR7 :1; /* Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpTXERR :8;\r
+ } MergedBits;\r
+} CAN1TXERRSTR;\r
+extern volatile CAN1TXERRSTR _CAN1TXERR @(REG_BASE + 0x0000018F);\r
+#define CAN1TXERR _CAN1TXERR.Byte\r
+#define CAN1TXERR_TXERR0 _CAN1TXERR.Bits.TXERR0\r
+#define CAN1TXERR_TXERR1 _CAN1TXERR.Bits.TXERR1\r
+#define CAN1TXERR_TXERR2 _CAN1TXERR.Bits.TXERR2\r
+#define CAN1TXERR_TXERR3 _CAN1TXERR.Bits.TXERR3\r
+#define CAN1TXERR_TXERR4 _CAN1TXERR.Bits.TXERR4\r
+#define CAN1TXERR_TXERR5 _CAN1TXERR.Bits.TXERR5\r
+#define CAN1TXERR_TXERR6 _CAN1TXERR.Bits.TXERR6\r
+#define CAN1TXERR_TXERR7 _CAN1TXERR.Bits.TXERR7\r
+#define CAN1TXERR_TXERR _CAN1TXERR.MergedBits.grpTXERR\r
+\r
+\r
+/*** CAN1IDAR0 - MSCAN 1 Identifier Acceptance Register 0; 0x00000190 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AC0 :1; /* Acceptance Code Bit 0 */\r
+ byte AC1 :1; /* Acceptance Code Bit 1 */\r
+ byte AC2 :1; /* Acceptance Code Bit 2 */\r
+ byte AC3 :1; /* Acceptance Code Bit 3 */\r
+ byte AC4 :1; /* Acceptance Code Bit 4 */\r
+ byte AC5 :1; /* Acceptance Code Bit 5 */\r
+ byte AC6 :1; /* Acceptance Code Bit 6 */\r
+ byte AC7 :1; /* Acceptance Code Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAC :8;\r
+ } MergedBits;\r
+} CAN1IDAR0STR;\r
+extern volatile CAN1IDAR0STR _CAN1IDAR0 @(REG_BASE + 0x00000190);\r
+#define CAN1IDAR0 _CAN1IDAR0.Byte\r
+#define CAN1IDAR0_AC0 _CAN1IDAR0.Bits.AC0\r
+#define CAN1IDAR0_AC1 _CAN1IDAR0.Bits.AC1\r
+#define CAN1IDAR0_AC2 _CAN1IDAR0.Bits.AC2\r
+#define CAN1IDAR0_AC3 _CAN1IDAR0.Bits.AC3\r
+#define CAN1IDAR0_AC4 _CAN1IDAR0.Bits.AC4\r
+#define CAN1IDAR0_AC5 _CAN1IDAR0.Bits.AC5\r
+#define CAN1IDAR0_AC6 _CAN1IDAR0.Bits.AC6\r
+#define CAN1IDAR0_AC7 _CAN1IDAR0.Bits.AC7\r
+#define CAN1IDAR0_AC _CAN1IDAR0.MergedBits.grpAC\r
+\r
+\r
+/*** CAN1IDAR1 - MSCAN 1 Identifier Acceptance Register 1; 0x00000191 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AC0 :1; /* Acceptance Code Bit 0 */\r
+ byte AC1 :1; /* Acceptance Code Bit 1 */\r
+ byte AC2 :1; /* Acceptance Code Bit 2 */\r
+ byte AC3 :1; /* Acceptance Code Bit 3 */\r
+ byte AC4 :1; /* Acceptance Code Bit 4 */\r
+ byte AC5 :1; /* Acceptance Code Bit 5 */\r
+ byte AC6 :1; /* Acceptance Code Bit 6 */\r
+ byte AC7 :1; /* Acceptance Code Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAC :8;\r
+ } MergedBits;\r
+} CAN1IDAR1STR;\r
+extern volatile CAN1IDAR1STR _CAN1IDAR1 @(REG_BASE + 0x00000191);\r
+#define CAN1IDAR1 _CAN1IDAR1.Byte\r
+#define CAN1IDAR1_AC0 _CAN1IDAR1.Bits.AC0\r
+#define CAN1IDAR1_AC1 _CAN1IDAR1.Bits.AC1\r
+#define CAN1IDAR1_AC2 _CAN1IDAR1.Bits.AC2\r
+#define CAN1IDAR1_AC3 _CAN1IDAR1.Bits.AC3\r
+#define CAN1IDAR1_AC4 _CAN1IDAR1.Bits.AC4\r
+#define CAN1IDAR1_AC5 _CAN1IDAR1.Bits.AC5\r
+#define CAN1IDAR1_AC6 _CAN1IDAR1.Bits.AC6\r
+#define CAN1IDAR1_AC7 _CAN1IDAR1.Bits.AC7\r
+#define CAN1IDAR1_AC _CAN1IDAR1.MergedBits.grpAC\r
+\r
+\r
+/*** CAN1IDAR2 - MSCAN 1 Identifier Acceptance Register 2; 0x00000192 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AC0 :1; /* Acceptance Code Bit 0 */\r
+ byte AC1 :1; /* Acceptance Code Bit 1 */\r
+ byte AC2 :1; /* Acceptance Code Bit 2 */\r
+ byte AC3 :1; /* Acceptance Code Bit 3 */\r
+ byte AC4 :1; /* Acceptance Code Bit 4 */\r
+ byte AC5 :1; /* Acceptance Code Bit 5 */\r
+ byte AC6 :1; /* Acceptance Code Bit 6 */\r
+ byte AC7 :1; /* Acceptance Code Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAC :8;\r
+ } MergedBits;\r
+} CAN1IDAR2STR;\r
+extern volatile CAN1IDAR2STR _CAN1IDAR2 @(REG_BASE + 0x00000192);\r
+#define CAN1IDAR2 _CAN1IDAR2.Byte\r
+#define CAN1IDAR2_AC0 _CAN1IDAR2.Bits.AC0\r
+#define CAN1IDAR2_AC1 _CAN1IDAR2.Bits.AC1\r
+#define CAN1IDAR2_AC2 _CAN1IDAR2.Bits.AC2\r
+#define CAN1IDAR2_AC3 _CAN1IDAR2.Bits.AC3\r
+#define CAN1IDAR2_AC4 _CAN1IDAR2.Bits.AC4\r
+#define CAN1IDAR2_AC5 _CAN1IDAR2.Bits.AC5\r
+#define CAN1IDAR2_AC6 _CAN1IDAR2.Bits.AC6\r
+#define CAN1IDAR2_AC7 _CAN1IDAR2.Bits.AC7\r
+#define CAN1IDAR2_AC _CAN1IDAR2.MergedBits.grpAC\r
+\r
+\r
+/*** CAN1IDAR3 - MSCAN 1 Identifier Acceptance Register 3; 0x00000193 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AC0 :1; /* Acceptance Code Bit 0 */\r
+ byte AC1 :1; /* Acceptance Code Bit 1 */\r
+ byte AC2 :1; /* Acceptance Code Bit 2 */\r
+ byte AC3 :1; /* Acceptance Code Bit 3 */\r
+ byte AC4 :1; /* Acceptance Code Bit 4 */\r
+ byte AC5 :1; /* Acceptance Code Bit 5 */\r
+ byte AC6 :1; /* Acceptance Code Bit 6 */\r
+ byte AC7 :1; /* Acceptance Code Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAC :8;\r
+ } MergedBits;\r
+} CAN1IDAR3STR;\r
+extern volatile CAN1IDAR3STR _CAN1IDAR3 @(REG_BASE + 0x00000193);\r
+#define CAN1IDAR3 _CAN1IDAR3.Byte\r
+#define CAN1IDAR3_AC0 _CAN1IDAR3.Bits.AC0\r
+#define CAN1IDAR3_AC1 _CAN1IDAR3.Bits.AC1\r
+#define CAN1IDAR3_AC2 _CAN1IDAR3.Bits.AC2\r
+#define CAN1IDAR3_AC3 _CAN1IDAR3.Bits.AC3\r
+#define CAN1IDAR3_AC4 _CAN1IDAR3.Bits.AC4\r
+#define CAN1IDAR3_AC5 _CAN1IDAR3.Bits.AC5\r
+#define CAN1IDAR3_AC6 _CAN1IDAR3.Bits.AC6\r
+#define CAN1IDAR3_AC7 _CAN1IDAR3.Bits.AC7\r
+#define CAN1IDAR3_AC _CAN1IDAR3.MergedBits.grpAC\r
+\r
+\r
+/*** CAN1IDMR0 - MSCAN 1 Identifier Mask Register 0; 0x00000194 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AM0 :1; /* Acceptance Mask Bit 0 */\r
+ byte AM1 :1; /* Acceptance Mask Bit 1 */\r
+ byte AM2 :1; /* Acceptance Mask Bit 2 */\r
+ byte AM3 :1; /* Acceptance Mask Bit 3 */\r
+ byte AM4 :1; /* Acceptance Mask Bit 4 */\r
+ byte AM5 :1; /* Acceptance Mask Bit 5 */\r
+ byte AM6 :1; /* Acceptance Mask Bit 6 */\r
+ byte AM7 :1; /* Acceptance Mask Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAM :8;\r
+ } MergedBits;\r
+} CAN1IDMR0STR;\r
+extern volatile CAN1IDMR0STR _CAN1IDMR0 @(REG_BASE + 0x00000194);\r
+#define CAN1IDMR0 _CAN1IDMR0.Byte\r
+#define CAN1IDMR0_AM0 _CAN1IDMR0.Bits.AM0\r
+#define CAN1IDMR0_AM1 _CAN1IDMR0.Bits.AM1\r
+#define CAN1IDMR0_AM2 _CAN1IDMR0.Bits.AM2\r
+#define CAN1IDMR0_AM3 _CAN1IDMR0.Bits.AM3\r
+#define CAN1IDMR0_AM4 _CAN1IDMR0.Bits.AM4\r
+#define CAN1IDMR0_AM5 _CAN1IDMR0.Bits.AM5\r
+#define CAN1IDMR0_AM6 _CAN1IDMR0.Bits.AM6\r
+#define CAN1IDMR0_AM7 _CAN1IDMR0.Bits.AM7\r
+#define CAN1IDMR0_AM _CAN1IDMR0.MergedBits.grpAM\r
+\r
+\r
+/*** CAN1IDMR1 - MSCAN 1 Identifier Mask Register 1; 0x00000195 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AM0 :1; /* Acceptance Mask Bit 0 */\r
+ byte AM1 :1; /* Acceptance Mask Bit 1 */\r
+ byte AM2 :1; /* Acceptance Mask Bit 2 */\r
+ byte AM3 :1; /* Acceptance Mask Bit 3 */\r
+ byte AM4 :1; /* Acceptance Mask Bit 4 */\r
+ byte AM5 :1; /* Acceptance Mask Bit 5 */\r
+ byte AM6 :1; /* Acceptance Mask Bit 6 */\r
+ byte AM7 :1; /* Acceptance Mask Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAM :8;\r
+ } MergedBits;\r
+} CAN1IDMR1STR;\r
+extern volatile CAN1IDMR1STR _CAN1IDMR1 @(REG_BASE + 0x00000195);\r
+#define CAN1IDMR1 _CAN1IDMR1.Byte\r
+#define CAN1IDMR1_AM0 _CAN1IDMR1.Bits.AM0\r
+#define CAN1IDMR1_AM1 _CAN1IDMR1.Bits.AM1\r
+#define CAN1IDMR1_AM2 _CAN1IDMR1.Bits.AM2\r
+#define CAN1IDMR1_AM3 _CAN1IDMR1.Bits.AM3\r
+#define CAN1IDMR1_AM4 _CAN1IDMR1.Bits.AM4\r
+#define CAN1IDMR1_AM5 _CAN1IDMR1.Bits.AM5\r
+#define CAN1IDMR1_AM6 _CAN1IDMR1.Bits.AM6\r
+#define CAN1IDMR1_AM7 _CAN1IDMR1.Bits.AM7\r
+#define CAN1IDMR1_AM _CAN1IDMR1.MergedBits.grpAM\r
+\r
+\r
+/*** CAN1IDMR2 - MSCAN 1 Identifier Mask Register 2; 0x00000196 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AM0 :1; /* Acceptance Mask Bit 0 */\r
+ byte AM1 :1; /* Acceptance Mask Bit 1 */\r
+ byte AM2 :1; /* Acceptance Mask Bit 2 */\r
+ byte AM3 :1; /* Acceptance Mask Bit 3 */\r
+ byte AM4 :1; /* Acceptance Mask Bit 4 */\r
+ byte AM5 :1; /* Acceptance Mask Bit 5 */\r
+ byte AM6 :1; /* Acceptance Mask Bit 6 */\r
+ byte AM7 :1; /* Acceptance Mask Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAM :8;\r
+ } MergedBits;\r
+} CAN1IDMR2STR;\r
+extern volatile CAN1IDMR2STR _CAN1IDMR2 @(REG_BASE + 0x00000196);\r
+#define CAN1IDMR2 _CAN1IDMR2.Byte\r
+#define CAN1IDMR2_AM0 _CAN1IDMR2.Bits.AM0\r
+#define CAN1IDMR2_AM1 _CAN1IDMR2.Bits.AM1\r
+#define CAN1IDMR2_AM2 _CAN1IDMR2.Bits.AM2\r
+#define CAN1IDMR2_AM3 _CAN1IDMR2.Bits.AM3\r
+#define CAN1IDMR2_AM4 _CAN1IDMR2.Bits.AM4\r
+#define CAN1IDMR2_AM5 _CAN1IDMR2.Bits.AM5\r
+#define CAN1IDMR2_AM6 _CAN1IDMR2.Bits.AM6\r
+#define CAN1IDMR2_AM7 _CAN1IDMR2.Bits.AM7\r
+#define CAN1IDMR2_AM _CAN1IDMR2.MergedBits.grpAM\r
+\r
+\r
+/*** CAN1IDMR3 - MSCAN 1 Identifier Mask Register 3; 0x00000197 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AM0 :1; /* Acceptance Mask Bit 0 */\r
+ byte AM1 :1; /* Acceptance Mask Bit 1 */\r
+ byte AM2 :1; /* Acceptance Mask Bit 2 */\r
+ byte AM3 :1; /* Acceptance Mask Bit 3 */\r
+ byte AM4 :1; /* Acceptance Mask Bit 4 */\r
+ byte AM5 :1; /* Acceptance Mask Bit 5 */\r
+ byte AM6 :1; /* Acceptance Mask Bit 6 */\r
+ byte AM7 :1; /* Acceptance Mask Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAM :8;\r
+ } MergedBits;\r
+} CAN1IDMR3STR;\r
+extern volatile CAN1IDMR3STR _CAN1IDMR3 @(REG_BASE + 0x00000197);\r
+#define CAN1IDMR3 _CAN1IDMR3.Byte\r
+#define CAN1IDMR3_AM0 _CAN1IDMR3.Bits.AM0\r
+#define CAN1IDMR3_AM1 _CAN1IDMR3.Bits.AM1\r
+#define CAN1IDMR3_AM2 _CAN1IDMR3.Bits.AM2\r
+#define CAN1IDMR3_AM3 _CAN1IDMR3.Bits.AM3\r
+#define CAN1IDMR3_AM4 _CAN1IDMR3.Bits.AM4\r
+#define CAN1IDMR3_AM5 _CAN1IDMR3.Bits.AM5\r
+#define CAN1IDMR3_AM6 _CAN1IDMR3.Bits.AM6\r
+#define CAN1IDMR3_AM7 _CAN1IDMR3.Bits.AM7\r
+#define CAN1IDMR3_AM _CAN1IDMR3.MergedBits.grpAM\r
+\r
+\r
+/*** CAN1IDAR4 - MSCAN 1 Identifier Acceptance Register 4; 0x00000198 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AC0 :1; /* Acceptance Code Bit 0 */\r
+ byte AC1 :1; /* Acceptance Code Bit 1 */\r
+ byte AC2 :1; /* Acceptance Code Bit 2 */\r
+ byte AC3 :1; /* Acceptance Code Bit 3 */\r
+ byte AC4 :1; /* Acceptance Code Bit 4 */\r
+ byte AC5 :1; /* Acceptance Code Bit 5 */\r
+ byte AC6 :1; /* Acceptance Code Bit 6 */\r
+ byte AC7 :1; /* Acceptance Code Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAC :8;\r
+ } MergedBits;\r
+} CAN1IDAR4STR;\r
+extern volatile CAN1IDAR4STR _CAN1IDAR4 @(REG_BASE + 0x00000198);\r
+#define CAN1IDAR4 _CAN1IDAR4.Byte\r
+#define CAN1IDAR4_AC0 _CAN1IDAR4.Bits.AC0\r
+#define CAN1IDAR4_AC1 _CAN1IDAR4.Bits.AC1\r
+#define CAN1IDAR4_AC2 _CAN1IDAR4.Bits.AC2\r
+#define CAN1IDAR4_AC3 _CAN1IDAR4.Bits.AC3\r
+#define CAN1IDAR4_AC4 _CAN1IDAR4.Bits.AC4\r
+#define CAN1IDAR4_AC5 _CAN1IDAR4.Bits.AC5\r
+#define CAN1IDAR4_AC6 _CAN1IDAR4.Bits.AC6\r
+#define CAN1IDAR4_AC7 _CAN1IDAR4.Bits.AC7\r
+#define CAN1IDAR4_AC _CAN1IDAR4.MergedBits.grpAC\r
+\r
+\r
+/*** CAN1IDAR5 - MSCAN 1 Identifier Acceptance Register 5; 0x00000199 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AC0 :1; /* Acceptance Code Bit 0 */\r
+ byte AC1 :1; /* Acceptance Code Bit 1 */\r
+ byte AC2 :1; /* Acceptance Code Bit 2 */\r
+ byte AC3 :1; /* Acceptance Code Bit 3 */\r
+ byte AC4 :1; /* Acceptance Code Bit 4 */\r
+ byte AC5 :1; /* Acceptance Code Bit 5 */\r
+ byte AC6 :1; /* Acceptance Code Bit 6 */\r
+ byte AC7 :1; /* Acceptance Code Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAC :8;\r
+ } MergedBits;\r
+} CAN1IDAR5STR;\r
+extern volatile CAN1IDAR5STR _CAN1IDAR5 @(REG_BASE + 0x00000199);\r
+#define CAN1IDAR5 _CAN1IDAR5.Byte\r
+#define CAN1IDAR5_AC0 _CAN1IDAR5.Bits.AC0\r
+#define CAN1IDAR5_AC1 _CAN1IDAR5.Bits.AC1\r
+#define CAN1IDAR5_AC2 _CAN1IDAR5.Bits.AC2\r
+#define CAN1IDAR5_AC3 _CAN1IDAR5.Bits.AC3\r
+#define CAN1IDAR5_AC4 _CAN1IDAR5.Bits.AC4\r
+#define CAN1IDAR5_AC5 _CAN1IDAR5.Bits.AC5\r
+#define CAN1IDAR5_AC6 _CAN1IDAR5.Bits.AC6\r
+#define CAN1IDAR5_AC7 _CAN1IDAR5.Bits.AC7\r
+#define CAN1IDAR5_AC _CAN1IDAR5.MergedBits.grpAC\r
+\r
+\r
+/*** CAN1IDAR6 - MSCAN 1 Identifier Acceptance Register 6; 0x0000019A ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AC0 :1; /* Acceptance Code Bit 0 */\r
+ byte AC1 :1; /* Acceptance Code Bit 1 */\r
+ byte AC2 :1; /* Acceptance Code Bit 2 */\r
+ byte AC3 :1; /* Acceptance Code Bit 3 */\r
+ byte AC4 :1; /* Acceptance Code Bit 4 */\r
+ byte AC5 :1; /* Acceptance Code Bit 5 */\r
+ byte AC6 :1; /* Acceptance Code Bit 6 */\r
+ byte AC7 :1; /* Acceptance Code Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAC :8;\r
+ } MergedBits;\r
+} CAN1IDAR6STR;\r
+extern volatile CAN1IDAR6STR _CAN1IDAR6 @(REG_BASE + 0x0000019A);\r
+#define CAN1IDAR6 _CAN1IDAR6.Byte\r
+#define CAN1IDAR6_AC0 _CAN1IDAR6.Bits.AC0\r
+#define CAN1IDAR6_AC1 _CAN1IDAR6.Bits.AC1\r
+#define CAN1IDAR6_AC2 _CAN1IDAR6.Bits.AC2\r
+#define CAN1IDAR6_AC3 _CAN1IDAR6.Bits.AC3\r
+#define CAN1IDAR6_AC4 _CAN1IDAR6.Bits.AC4\r
+#define CAN1IDAR6_AC5 _CAN1IDAR6.Bits.AC5\r
+#define CAN1IDAR6_AC6 _CAN1IDAR6.Bits.AC6\r
+#define CAN1IDAR6_AC7 _CAN1IDAR6.Bits.AC7\r
+#define CAN1IDAR6_AC _CAN1IDAR6.MergedBits.grpAC\r
+\r
+\r
+/*** CAN1IDAR7 - MSCAN 1 Identifier Acceptance Register 7; 0x0000019B ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AC0 :1; /* Acceptance Code Bit 0 */\r
+ byte AC1 :1; /* Acceptance Code Bit 1 */\r
+ byte AC2 :1; /* Acceptance Code Bit 2 */\r
+ byte AC3 :1; /* Acceptance Code Bit 3 */\r
+ byte AC4 :1; /* Acceptance Code Bit 4 */\r
+ byte AC5 :1; /* Acceptance Code Bit 5 */\r
+ byte AC6 :1; /* Acceptance Code Bit 6 */\r
+ byte AC7 :1; /* Acceptance Code Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAC :8;\r
+ } MergedBits;\r
+} CAN1IDAR7STR;\r
+extern volatile CAN1IDAR7STR _CAN1IDAR7 @(REG_BASE + 0x0000019B);\r
+#define CAN1IDAR7 _CAN1IDAR7.Byte\r
+#define CAN1IDAR7_AC0 _CAN1IDAR7.Bits.AC0\r
+#define CAN1IDAR7_AC1 _CAN1IDAR7.Bits.AC1\r
+#define CAN1IDAR7_AC2 _CAN1IDAR7.Bits.AC2\r
+#define CAN1IDAR7_AC3 _CAN1IDAR7.Bits.AC3\r
+#define CAN1IDAR7_AC4 _CAN1IDAR7.Bits.AC4\r
+#define CAN1IDAR7_AC5 _CAN1IDAR7.Bits.AC5\r
+#define CAN1IDAR7_AC6 _CAN1IDAR7.Bits.AC6\r
+#define CAN1IDAR7_AC7 _CAN1IDAR7.Bits.AC7\r
+#define CAN1IDAR7_AC _CAN1IDAR7.MergedBits.grpAC\r
+\r
+\r
+/*** CAN1IDMR4 - MSCAN 1 Identifier Mask Register 4; 0x0000019C ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AM0 :1; /* Acceptance Mask Bit 0 */\r
+ byte AM1 :1; /* Acceptance Mask Bit 1 */\r
+ byte AM2 :1; /* Acceptance Mask Bit 2 */\r
+ byte AM3 :1; /* Acceptance Mask Bit 3 */\r
+ byte AM4 :1; /* Acceptance Mask Bit 4 */\r
+ byte AM5 :1; /* Acceptance Mask Bit 5 */\r
+ byte AM6 :1; /* Acceptance Mask Bit 6 */\r
+ byte AM7 :1; /* Acceptance Mask Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAM :8;\r
+ } MergedBits;\r
+} CAN1IDMR4STR;\r
+extern volatile CAN1IDMR4STR _CAN1IDMR4 @(REG_BASE + 0x0000019C);\r
+#define CAN1IDMR4 _CAN1IDMR4.Byte\r
+#define CAN1IDMR4_AM0 _CAN1IDMR4.Bits.AM0\r
+#define CAN1IDMR4_AM1 _CAN1IDMR4.Bits.AM1\r
+#define CAN1IDMR4_AM2 _CAN1IDMR4.Bits.AM2\r
+#define CAN1IDMR4_AM3 _CAN1IDMR4.Bits.AM3\r
+#define CAN1IDMR4_AM4 _CAN1IDMR4.Bits.AM4\r
+#define CAN1IDMR4_AM5 _CAN1IDMR4.Bits.AM5\r
+#define CAN1IDMR4_AM6 _CAN1IDMR4.Bits.AM6\r
+#define CAN1IDMR4_AM7 _CAN1IDMR4.Bits.AM7\r
+#define CAN1IDMR4_AM _CAN1IDMR4.MergedBits.grpAM\r
+\r
+\r
+/*** CAN1IDMR5 - MSCAN 1 Identifier Mask Register 5; 0x0000019D ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AM0 :1; /* Acceptance Mask Bit 0 */\r
+ byte AM1 :1; /* Acceptance Mask Bit 1 */\r
+ byte AM2 :1; /* Acceptance Mask Bit 2 */\r
+ byte AM3 :1; /* Acceptance Mask Bit 3 */\r
+ byte AM4 :1; /* Acceptance Mask Bit 4 */\r
+ byte AM5 :1; /* Acceptance Mask Bit 5 */\r
+ byte AM6 :1; /* Acceptance Mask Bit 6 */\r
+ byte AM7 :1; /* Acceptance Mask Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAM :8;\r
+ } MergedBits;\r
+} CAN1IDMR5STR;\r
+extern volatile CAN1IDMR5STR _CAN1IDMR5 @(REG_BASE + 0x0000019D);\r
+#define CAN1IDMR5 _CAN1IDMR5.Byte\r
+#define CAN1IDMR5_AM0 _CAN1IDMR5.Bits.AM0\r
+#define CAN1IDMR5_AM1 _CAN1IDMR5.Bits.AM1\r
+#define CAN1IDMR5_AM2 _CAN1IDMR5.Bits.AM2\r
+#define CAN1IDMR5_AM3 _CAN1IDMR5.Bits.AM3\r
+#define CAN1IDMR5_AM4 _CAN1IDMR5.Bits.AM4\r
+#define CAN1IDMR5_AM5 _CAN1IDMR5.Bits.AM5\r
+#define CAN1IDMR5_AM6 _CAN1IDMR5.Bits.AM6\r
+#define CAN1IDMR5_AM7 _CAN1IDMR5.Bits.AM7\r
+#define CAN1IDMR5_AM _CAN1IDMR5.MergedBits.grpAM\r
+\r
+\r
+/*** CAN1IDMR6 - MSCAN 1 Identifier Mask Register 6; 0x0000019E ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AM0 :1; /* Acceptance Mask Bit 0 */\r
+ byte AM1 :1; /* Acceptance Mask Bit 1 */\r
+ byte AM2 :1; /* Acceptance Mask Bit 2 */\r
+ byte AM3 :1; /* Acceptance Mask Bit 3 */\r
+ byte AM4 :1; /* Acceptance Mask Bit 4 */\r
+ byte AM5 :1; /* Acceptance Mask Bit 5 */\r
+ byte AM6 :1; /* Acceptance Mask Bit 6 */\r
+ byte AM7 :1; /* Acceptance Mask Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAM :8;\r
+ } MergedBits;\r
+} CAN1IDMR6STR;\r
+extern volatile CAN1IDMR6STR _CAN1IDMR6 @(REG_BASE + 0x0000019E);\r
+#define CAN1IDMR6 _CAN1IDMR6.Byte\r
+#define CAN1IDMR6_AM0 _CAN1IDMR6.Bits.AM0\r
+#define CAN1IDMR6_AM1 _CAN1IDMR6.Bits.AM1\r
+#define CAN1IDMR6_AM2 _CAN1IDMR6.Bits.AM2\r
+#define CAN1IDMR6_AM3 _CAN1IDMR6.Bits.AM3\r
+#define CAN1IDMR6_AM4 _CAN1IDMR6.Bits.AM4\r
+#define CAN1IDMR6_AM5 _CAN1IDMR6.Bits.AM5\r
+#define CAN1IDMR6_AM6 _CAN1IDMR6.Bits.AM6\r
+#define CAN1IDMR6_AM7 _CAN1IDMR6.Bits.AM7\r
+#define CAN1IDMR6_AM _CAN1IDMR6.MergedBits.grpAM\r
+\r
+\r
+/*** CAN1IDMR7 - MSCAN 1 Identifier Mask Register 7; 0x0000019F ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AM0 :1; /* Acceptance Mask Bit 0 */\r
+ byte AM1 :1; /* Acceptance Mask Bit 1 */\r
+ byte AM2 :1; /* Acceptance Mask Bit 2 */\r
+ byte AM3 :1; /* Acceptance Mask Bit 3 */\r
+ byte AM4 :1; /* Acceptance Mask Bit 4 */\r
+ byte AM5 :1; /* Acceptance Mask Bit 5 */\r
+ byte AM6 :1; /* Acceptance Mask Bit 6 */\r
+ byte AM7 :1; /* Acceptance Mask Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAM :8;\r
+ } MergedBits;\r
+} CAN1IDMR7STR;\r
+extern volatile CAN1IDMR7STR _CAN1IDMR7 @(REG_BASE + 0x0000019F);\r
+#define CAN1IDMR7 _CAN1IDMR7.Byte\r
+#define CAN1IDMR7_AM0 _CAN1IDMR7.Bits.AM0\r
+#define CAN1IDMR7_AM1 _CAN1IDMR7.Bits.AM1\r
+#define CAN1IDMR7_AM2 _CAN1IDMR7.Bits.AM2\r
+#define CAN1IDMR7_AM3 _CAN1IDMR7.Bits.AM3\r
+#define CAN1IDMR7_AM4 _CAN1IDMR7.Bits.AM4\r
+#define CAN1IDMR7_AM5 _CAN1IDMR7.Bits.AM5\r
+#define CAN1IDMR7_AM6 _CAN1IDMR7.Bits.AM6\r
+#define CAN1IDMR7_AM7 _CAN1IDMR7.Bits.AM7\r
+#define CAN1IDMR7_AM _CAN1IDMR7.MergedBits.grpAM\r
+\r
+\r
+/*** CAN1RXIDR0 - MSCAN 1 Receive Identifier Register 0; 0x000001A0 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ID21 :1; /* Extended format identifier Bit 21 */\r
+ byte ID22 :1; /* Extended format identifier Bit 22 */\r
+ byte ID23 :1; /* Extended format identifier Bit 23 */\r
+ byte ID24 :1; /* Extended format identifier Bit 24 */\r
+ byte ID25 :1; /* Extended format identifier Bit 25 */\r
+ byte ID26 :1; /* Extended format identifier Bit 26 */\r
+ byte ID27 :1; /* Extended format identifier Bit 27 */\r
+ byte ID28 :1; /* Extended format identifier Bit 28 */\r
+ } Bits;\r
+ struct {\r
+ byte grpID_21 :8;\r
+ } MergedBits;\r
+} CAN1RXIDR0STR;\r
+extern volatile CAN1RXIDR0STR _CAN1RXIDR0 @(REG_BASE + 0x000001A0);\r
+#define CAN1RXIDR0 _CAN1RXIDR0.Byte\r
+#define CAN1RXIDR0_ID21 _CAN1RXIDR0.Bits.ID21\r
+#define CAN1RXIDR0_ID22 _CAN1RXIDR0.Bits.ID22\r
+#define CAN1RXIDR0_ID23 _CAN1RXIDR0.Bits.ID23\r
+#define CAN1RXIDR0_ID24 _CAN1RXIDR0.Bits.ID24\r
+#define CAN1RXIDR0_ID25 _CAN1RXIDR0.Bits.ID25\r
+#define CAN1RXIDR0_ID26 _CAN1RXIDR0.Bits.ID26\r
+#define CAN1RXIDR0_ID27 _CAN1RXIDR0.Bits.ID27\r
+#define CAN1RXIDR0_ID28 _CAN1RXIDR0.Bits.ID28\r
+#define CAN1RXIDR0_ID_21 _CAN1RXIDR0.MergedBits.grpID_21\r
+#define CAN1RXIDR0_ID CAN1RXIDR0_ID_21\r
+\r
+\r
+/*** CAN1RXIDR1 - MSCAN 1 Receive Identifier Register 1; 0x000001A1 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ID15 :1; /* Extended format identifier Bit 15 */\r
+ byte ID16 :1; /* Extended format identifier Bit 16 */\r
+ byte ID17 :1; /* Extended format identifier Bit 17 */\r
+ byte IDE :1; /* ID Extended */\r
+ byte SRR :1; /* Substitute Remote Request */\r
+ byte ID18 :1; /* Extended format identifier Bit 18 */\r
+ byte ID19 :1; /* Extended format identifier Bit 19 */\r
+ byte ID20 :1; /* Extended format identifier Bit 20 */\r
+ } Bits;\r
+ struct {\r
+ byte grpID_15 :3;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpID_18 :3;\r
+ } MergedBits;\r
+} CAN1RXIDR1STR;\r
+extern volatile CAN1RXIDR1STR _CAN1RXIDR1 @(REG_BASE + 0x000001A1);\r
+#define CAN1RXIDR1 _CAN1RXIDR1.Byte\r
+#define CAN1RXIDR1_ID15 _CAN1RXIDR1.Bits.ID15\r
+#define CAN1RXIDR1_ID16 _CAN1RXIDR1.Bits.ID16\r
+#define CAN1RXIDR1_ID17 _CAN1RXIDR1.Bits.ID17\r
+#define CAN1RXIDR1_IDE _CAN1RXIDR1.Bits.IDE\r
+#define CAN1RXIDR1_SRR _CAN1RXIDR1.Bits.SRR\r
+#define CAN1RXIDR1_ID18 _CAN1RXIDR1.Bits.ID18\r
+#define CAN1RXIDR1_ID19 _CAN1RXIDR1.Bits.ID19\r
+#define CAN1RXIDR1_ID20 _CAN1RXIDR1.Bits.ID20\r
+#define CAN1RXIDR1_ID_15 _CAN1RXIDR1.MergedBits.grpID_15\r
+#define CAN1RXIDR1_ID_18 _CAN1RXIDR1.MergedBits.grpID_18\r
+#define CAN1RXIDR1_ID CAN1RXIDR1_ID_15\r
+\r
+\r
+/*** CAN1RXIDR2 - MSCAN 1 Receive Identifier Register 2; 0x000001A2 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ID7 :1; /* Extended format identifier Bit 7 */\r
+ byte ID8 :1; /* Extended format identifier Bit 8 */\r
+ byte ID9 :1; /* Extended format identifier Bit 9 */\r
+ byte ID10 :1; /* Extended format identifier Bit 10 */\r
+ byte ID11 :1; /* Extended format identifier Bit 11 */\r
+ byte ID12 :1; /* Extended format identifier Bit 12 */\r
+ byte ID13 :1; /* Extended format identifier Bit 13 */\r
+ byte ID14 :1; /* Extended format identifier Bit 14 */\r
+ } Bits;\r
+ struct {\r
+ byte grpID_7 :8;\r
+ } MergedBits;\r
+} CAN1RXIDR2STR;\r
+extern volatile CAN1RXIDR2STR _CAN1RXIDR2 @(REG_BASE + 0x000001A2);\r
+#define CAN1RXIDR2 _CAN1RXIDR2.Byte\r
+#define CAN1RXIDR2_ID7 _CAN1RXIDR2.Bits.ID7\r
+#define CAN1RXIDR2_ID8 _CAN1RXIDR2.Bits.ID8\r
+#define CAN1RXIDR2_ID9 _CAN1RXIDR2.Bits.ID9\r
+#define CAN1RXIDR2_ID10 _CAN1RXIDR2.Bits.ID10\r
+#define CAN1RXIDR2_ID11 _CAN1RXIDR2.Bits.ID11\r
+#define CAN1RXIDR2_ID12 _CAN1RXIDR2.Bits.ID12\r
+#define CAN1RXIDR2_ID13 _CAN1RXIDR2.Bits.ID13\r
+#define CAN1RXIDR2_ID14 _CAN1RXIDR2.Bits.ID14\r
+#define CAN1RXIDR2_ID_7 _CAN1RXIDR2.MergedBits.grpID_7\r
+#define CAN1RXIDR2_ID CAN1RXIDR2_ID_7\r
+\r
+\r
+/*** CAN1RXIDR3 - MSCAN 1 Receive Identifier Register 3; 0x000001A3 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte RTR :1; /* Remote Transmission Request */\r
+ byte ID0 :1; /* Extended format identifier Bit 0 */\r
+ byte ID1 :1; /* Extended format identifier Bit 1 */\r
+ byte ID2 :1; /* Extended format identifier Bit 2 */\r
+ byte ID3 :1; /* Extended format identifier Bit 3 */\r
+ byte ID4 :1; /* Extended format identifier Bit 4 */\r
+ byte ID5 :1; /* Extended format identifier Bit 5 */\r
+ byte ID6 :1; /* Extended format identifier Bit 6 */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte grpID :7;\r
+ } MergedBits;\r
+} CAN1RXIDR3STR;\r
+extern volatile CAN1RXIDR3STR _CAN1RXIDR3 @(REG_BASE + 0x000001A3);\r
+#define CAN1RXIDR3 _CAN1RXIDR3.Byte\r
+#define CAN1RXIDR3_RTR _CAN1RXIDR3.Bits.RTR\r
+#define CAN1RXIDR3_ID0 _CAN1RXIDR3.Bits.ID0\r
+#define CAN1RXIDR3_ID1 _CAN1RXIDR3.Bits.ID1\r
+#define CAN1RXIDR3_ID2 _CAN1RXIDR3.Bits.ID2\r
+#define CAN1RXIDR3_ID3 _CAN1RXIDR3.Bits.ID3\r
+#define CAN1RXIDR3_ID4 _CAN1RXIDR3.Bits.ID4\r
+#define CAN1RXIDR3_ID5 _CAN1RXIDR3.Bits.ID5\r
+#define CAN1RXIDR3_ID6 _CAN1RXIDR3.Bits.ID6\r
+#define CAN1RXIDR3_ID _CAN1RXIDR3.MergedBits.grpID\r
+\r
+\r
+/*** CAN1RXDSR0 - MSCAN 1 Receive Data Segment Register 0; 0x000001A4 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN1RXDSR0STR;\r
+extern volatile CAN1RXDSR0STR _CAN1RXDSR0 @(REG_BASE + 0x000001A4);\r
+#define CAN1RXDSR0 _CAN1RXDSR0.Byte\r
+#define CAN1RXDSR0_DB0 _CAN1RXDSR0.Bits.DB0\r
+#define CAN1RXDSR0_DB1 _CAN1RXDSR0.Bits.DB1\r
+#define CAN1RXDSR0_DB2 _CAN1RXDSR0.Bits.DB2\r
+#define CAN1RXDSR0_DB3 _CAN1RXDSR0.Bits.DB3\r
+#define CAN1RXDSR0_DB4 _CAN1RXDSR0.Bits.DB4\r
+#define CAN1RXDSR0_DB5 _CAN1RXDSR0.Bits.DB5\r
+#define CAN1RXDSR0_DB6 _CAN1RXDSR0.Bits.DB6\r
+#define CAN1RXDSR0_DB7 _CAN1RXDSR0.Bits.DB7\r
+#define CAN1RXDSR0_DB _CAN1RXDSR0.MergedBits.grpDB\r
+\r
+\r
+/*** CAN1RXDSR1 - MSCAN 1 Receive Data Segment Register 1; 0x000001A5 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN1RXDSR1STR;\r
+extern volatile CAN1RXDSR1STR _CAN1RXDSR1 @(REG_BASE + 0x000001A5);\r
+#define CAN1RXDSR1 _CAN1RXDSR1.Byte\r
+#define CAN1RXDSR1_DB0 _CAN1RXDSR1.Bits.DB0\r
+#define CAN1RXDSR1_DB1 _CAN1RXDSR1.Bits.DB1\r
+#define CAN1RXDSR1_DB2 _CAN1RXDSR1.Bits.DB2\r
+#define CAN1RXDSR1_DB3 _CAN1RXDSR1.Bits.DB3\r
+#define CAN1RXDSR1_DB4 _CAN1RXDSR1.Bits.DB4\r
+#define CAN1RXDSR1_DB5 _CAN1RXDSR1.Bits.DB5\r
+#define CAN1RXDSR1_DB6 _CAN1RXDSR1.Bits.DB6\r
+#define CAN1RXDSR1_DB7 _CAN1RXDSR1.Bits.DB7\r
+#define CAN1RXDSR1_DB _CAN1RXDSR1.MergedBits.grpDB\r
+\r
+\r
+/*** CAN1RXDSR2 - MSCAN 1 Receive Data Segment Register 2; 0x000001A6 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN1RXDSR2STR;\r
+extern volatile CAN1RXDSR2STR _CAN1RXDSR2 @(REG_BASE + 0x000001A6);\r
+#define CAN1RXDSR2 _CAN1RXDSR2.Byte\r
+#define CAN1RXDSR2_DB0 _CAN1RXDSR2.Bits.DB0\r
+#define CAN1RXDSR2_DB1 _CAN1RXDSR2.Bits.DB1\r
+#define CAN1RXDSR2_DB2 _CAN1RXDSR2.Bits.DB2\r
+#define CAN1RXDSR2_DB3 _CAN1RXDSR2.Bits.DB3\r
+#define CAN1RXDSR2_DB4 _CAN1RXDSR2.Bits.DB4\r
+#define CAN1RXDSR2_DB5 _CAN1RXDSR2.Bits.DB5\r
+#define CAN1RXDSR2_DB6 _CAN1RXDSR2.Bits.DB6\r
+#define CAN1RXDSR2_DB7 _CAN1RXDSR2.Bits.DB7\r
+#define CAN1RXDSR2_DB _CAN1RXDSR2.MergedBits.grpDB\r
+\r
+\r
+/*** CAN1RXDSR3 - MSCAN 1 Receive Data Segment Register 3; 0x000001A7 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN1RXDSR3STR;\r
+extern volatile CAN1RXDSR3STR _CAN1RXDSR3 @(REG_BASE + 0x000001A7);\r
+#define CAN1RXDSR3 _CAN1RXDSR3.Byte\r
+#define CAN1RXDSR3_DB0 _CAN1RXDSR3.Bits.DB0\r
+#define CAN1RXDSR3_DB1 _CAN1RXDSR3.Bits.DB1\r
+#define CAN1RXDSR3_DB2 _CAN1RXDSR3.Bits.DB2\r
+#define CAN1RXDSR3_DB3 _CAN1RXDSR3.Bits.DB3\r
+#define CAN1RXDSR3_DB4 _CAN1RXDSR3.Bits.DB4\r
+#define CAN1RXDSR3_DB5 _CAN1RXDSR3.Bits.DB5\r
+#define CAN1RXDSR3_DB6 _CAN1RXDSR3.Bits.DB6\r
+#define CAN1RXDSR3_DB7 _CAN1RXDSR3.Bits.DB7\r
+#define CAN1RXDSR3_DB _CAN1RXDSR3.MergedBits.grpDB\r
+\r
+\r
+/*** CAN1RXDSR4 - MSCAN 1 Receive Data Segment Register 4; 0x000001A8 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN1RXDSR4STR;\r
+extern volatile CAN1RXDSR4STR _CAN1RXDSR4 @(REG_BASE + 0x000001A8);\r
+#define CAN1RXDSR4 _CAN1RXDSR4.Byte\r
+#define CAN1RXDSR4_DB0 _CAN1RXDSR4.Bits.DB0\r
+#define CAN1RXDSR4_DB1 _CAN1RXDSR4.Bits.DB1\r
+#define CAN1RXDSR4_DB2 _CAN1RXDSR4.Bits.DB2\r
+#define CAN1RXDSR4_DB3 _CAN1RXDSR4.Bits.DB3\r
+#define CAN1RXDSR4_DB4 _CAN1RXDSR4.Bits.DB4\r
+#define CAN1RXDSR4_DB5 _CAN1RXDSR4.Bits.DB5\r
+#define CAN1RXDSR4_DB6 _CAN1RXDSR4.Bits.DB6\r
+#define CAN1RXDSR4_DB7 _CAN1RXDSR4.Bits.DB7\r
+#define CAN1RXDSR4_DB _CAN1RXDSR4.MergedBits.grpDB\r
+\r
+\r
+/*** CAN1RXDSR5 - MSCAN 1 Receive Data Segment Register 5; 0x000001A9 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN1RXDSR5STR;\r
+extern volatile CAN1RXDSR5STR _CAN1RXDSR5 @(REG_BASE + 0x000001A9);\r
+#define CAN1RXDSR5 _CAN1RXDSR5.Byte\r
+#define CAN1RXDSR5_DB0 _CAN1RXDSR5.Bits.DB0\r
+#define CAN1RXDSR5_DB1 _CAN1RXDSR5.Bits.DB1\r
+#define CAN1RXDSR5_DB2 _CAN1RXDSR5.Bits.DB2\r
+#define CAN1RXDSR5_DB3 _CAN1RXDSR5.Bits.DB3\r
+#define CAN1RXDSR5_DB4 _CAN1RXDSR5.Bits.DB4\r
+#define CAN1RXDSR5_DB5 _CAN1RXDSR5.Bits.DB5\r
+#define CAN1RXDSR5_DB6 _CAN1RXDSR5.Bits.DB6\r
+#define CAN1RXDSR5_DB7 _CAN1RXDSR5.Bits.DB7\r
+#define CAN1RXDSR5_DB _CAN1RXDSR5.MergedBits.grpDB\r
+\r
+\r
+/*** CAN1RXDSR6 - MSCAN 1 Receive Data Segment Register 6; 0x000001AA ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN1RXDSR6STR;\r
+extern volatile CAN1RXDSR6STR _CAN1RXDSR6 @(REG_BASE + 0x000001AA);\r
+#define CAN1RXDSR6 _CAN1RXDSR6.Byte\r
+#define CAN1RXDSR6_DB0 _CAN1RXDSR6.Bits.DB0\r
+#define CAN1RXDSR6_DB1 _CAN1RXDSR6.Bits.DB1\r
+#define CAN1RXDSR6_DB2 _CAN1RXDSR6.Bits.DB2\r
+#define CAN1RXDSR6_DB3 _CAN1RXDSR6.Bits.DB3\r
+#define CAN1RXDSR6_DB4 _CAN1RXDSR6.Bits.DB4\r
+#define CAN1RXDSR6_DB5 _CAN1RXDSR6.Bits.DB5\r
+#define CAN1RXDSR6_DB6 _CAN1RXDSR6.Bits.DB6\r
+#define CAN1RXDSR6_DB7 _CAN1RXDSR6.Bits.DB7\r
+#define CAN1RXDSR6_DB _CAN1RXDSR6.MergedBits.grpDB\r
+\r
+\r
+/*** CAN1RXDSR7 - MSCAN 1 Receive Data Segment Register 7; 0x000001AB ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN1RXDSR7STR;\r
+extern volatile CAN1RXDSR7STR _CAN1RXDSR7 @(REG_BASE + 0x000001AB);\r
+#define CAN1RXDSR7 _CAN1RXDSR7.Byte\r
+#define CAN1RXDSR7_DB0 _CAN1RXDSR7.Bits.DB0\r
+#define CAN1RXDSR7_DB1 _CAN1RXDSR7.Bits.DB1\r
+#define CAN1RXDSR7_DB2 _CAN1RXDSR7.Bits.DB2\r
+#define CAN1RXDSR7_DB3 _CAN1RXDSR7.Bits.DB3\r
+#define CAN1RXDSR7_DB4 _CAN1RXDSR7.Bits.DB4\r
+#define CAN1RXDSR7_DB5 _CAN1RXDSR7.Bits.DB5\r
+#define CAN1RXDSR7_DB6 _CAN1RXDSR7.Bits.DB6\r
+#define CAN1RXDSR7_DB7 _CAN1RXDSR7.Bits.DB7\r
+#define CAN1RXDSR7_DB _CAN1RXDSR7.MergedBits.grpDB\r
+\r
+\r
+/*** CAN1RXDLR - MSCAN 1 Receive Data Length Register; 0x000001AC ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DLC0 :1; /* Data Length Code Bit 0 */\r
+ byte DLC1 :1; /* Data Length Code Bit 1 */\r
+ byte DLC2 :1; /* Data Length Code Bit 2 */\r
+ byte DLC3 :1; /* Data Length Code Bit 3 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpDLC :4;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CAN1RXDLRSTR;\r
+extern volatile CAN1RXDLRSTR _CAN1RXDLR @(REG_BASE + 0x000001AC);\r
+#define CAN1RXDLR _CAN1RXDLR.Byte\r
+#define CAN1RXDLR_DLC0 _CAN1RXDLR.Bits.DLC0\r
+#define CAN1RXDLR_DLC1 _CAN1RXDLR.Bits.DLC1\r
+#define CAN1RXDLR_DLC2 _CAN1RXDLR.Bits.DLC2\r
+#define CAN1RXDLR_DLC3 _CAN1RXDLR.Bits.DLC3\r
+#define CAN1RXDLR_DLC _CAN1RXDLR.MergedBits.grpDLC\r
+\r
+\r
+/*** CAN1TXIDR0 - MSCAN 1 Transmit Identifier Register 0; 0x000001B0 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ID21 :1; /* Extended format identifier Bit 21 */\r
+ byte ID22 :1; /* Extended format identifier Bit 22 */\r
+ byte ID23 :1; /* Extended format identifier Bit 23 */\r
+ byte ID24 :1; /* Extended format identifier Bit 24 */\r
+ byte ID25 :1; /* Extended format identifier Bit 25 */\r
+ byte ID26 :1; /* Extended format identifier Bit 26 */\r
+ byte ID27 :1; /* Extended format identifier Bit 27 */\r
+ byte ID28 :1; /* Extended format identifier Bit 28 */\r
+ } Bits;\r
+ struct {\r
+ byte grpID_21 :8;\r
+ } MergedBits;\r
+} CAN1TXIDR0STR;\r
+extern volatile CAN1TXIDR0STR _CAN1TXIDR0 @(REG_BASE + 0x000001B0);\r
+#define CAN1TXIDR0 _CAN1TXIDR0.Byte\r
+#define CAN1TXIDR0_ID21 _CAN1TXIDR0.Bits.ID21\r
+#define CAN1TXIDR0_ID22 _CAN1TXIDR0.Bits.ID22\r
+#define CAN1TXIDR0_ID23 _CAN1TXIDR0.Bits.ID23\r
+#define CAN1TXIDR0_ID24 _CAN1TXIDR0.Bits.ID24\r
+#define CAN1TXIDR0_ID25 _CAN1TXIDR0.Bits.ID25\r
+#define CAN1TXIDR0_ID26 _CAN1TXIDR0.Bits.ID26\r
+#define CAN1TXIDR0_ID27 _CAN1TXIDR0.Bits.ID27\r
+#define CAN1TXIDR0_ID28 _CAN1TXIDR0.Bits.ID28\r
+#define CAN1TXIDR0_ID_21 _CAN1TXIDR0.MergedBits.grpID_21\r
+#define CAN1TXIDR0_ID CAN1TXIDR0_ID_21\r
+\r
+\r
+/*** CAN1TXIDR1 - MSCAN 1 Transmit Identifier Register 1; 0x000001B1 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ID15 :1; /* Extended format identifier Bit 15 */\r
+ byte ID16 :1; /* Extended format identifier Bit 16 */\r
+ byte ID17 :1; /* Extended format identifier Bit 17 */\r
+ byte IDE :1; /* ID Extended */\r
+ byte SRR :1; /* Substitute Remote Request */\r
+ byte ID18 :1; /* Extended format identifier Bit 18 */\r
+ byte ID19 :1; /* Extended format identifier Bit 19 */\r
+ byte ID20 :1; /* Extended format identifier Bit 20 */\r
+ } Bits;\r
+ struct {\r
+ byte grpID_15 :3;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpID_18 :3;\r
+ } MergedBits;\r
+} CAN1TXIDR1STR;\r
+extern volatile CAN1TXIDR1STR _CAN1TXIDR1 @(REG_BASE + 0x000001B1);\r
+#define CAN1TXIDR1 _CAN1TXIDR1.Byte\r
+#define CAN1TXIDR1_ID15 _CAN1TXIDR1.Bits.ID15\r
+#define CAN1TXIDR1_ID16 _CAN1TXIDR1.Bits.ID16\r
+#define CAN1TXIDR1_ID17 _CAN1TXIDR1.Bits.ID17\r
+#define CAN1TXIDR1_IDE _CAN1TXIDR1.Bits.IDE\r
+#define CAN1TXIDR1_SRR _CAN1TXIDR1.Bits.SRR\r
+#define CAN1TXIDR1_ID18 _CAN1TXIDR1.Bits.ID18\r
+#define CAN1TXIDR1_ID19 _CAN1TXIDR1.Bits.ID19\r
+#define CAN1TXIDR1_ID20 _CAN1TXIDR1.Bits.ID20\r
+#define CAN1TXIDR1_ID_15 _CAN1TXIDR1.MergedBits.grpID_15\r
+#define CAN1TXIDR1_ID_18 _CAN1TXIDR1.MergedBits.grpID_18\r
+#define CAN1TXIDR1_ID CAN1TXIDR1_ID_15\r
+\r
+\r
+/*** CAN1TXIDR2 - MSCAN 1 Transmit Identifier Register 2; 0x000001B2 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ID7 :1; /* Extended format identifier Bit 7 */\r
+ byte ID8 :1; /* Extended format identifier Bit 8 */\r
+ byte ID9 :1; /* Extended format identifier Bit 9 */\r
+ byte ID10 :1; /* Extended format identifier Bit 10 */\r
+ byte ID11 :1; /* Extended format identifier Bit 11 */\r
+ byte ID12 :1; /* Extended format identifier Bit 12 */\r
+ byte ID13 :1; /* Extended format identifier Bit 13 */\r
+ byte ID14 :1; /* Extended format identifier Bit 14 */\r
+ } Bits;\r
+ struct {\r
+ byte grpID_7 :8;\r
+ } MergedBits;\r
+} CAN1TXIDR2STR;\r
+extern volatile CAN1TXIDR2STR _CAN1TXIDR2 @(REG_BASE + 0x000001B2);\r
+#define CAN1TXIDR2 _CAN1TXIDR2.Byte\r
+#define CAN1TXIDR2_ID7 _CAN1TXIDR2.Bits.ID7\r
+#define CAN1TXIDR2_ID8 _CAN1TXIDR2.Bits.ID8\r
+#define CAN1TXIDR2_ID9 _CAN1TXIDR2.Bits.ID9\r
+#define CAN1TXIDR2_ID10 _CAN1TXIDR2.Bits.ID10\r
+#define CAN1TXIDR2_ID11 _CAN1TXIDR2.Bits.ID11\r
+#define CAN1TXIDR2_ID12 _CAN1TXIDR2.Bits.ID12\r
+#define CAN1TXIDR2_ID13 _CAN1TXIDR2.Bits.ID13\r
+#define CAN1TXIDR2_ID14 _CAN1TXIDR2.Bits.ID14\r
+#define CAN1TXIDR2_ID_7 _CAN1TXIDR2.MergedBits.grpID_7\r
+#define CAN1TXIDR2_ID CAN1TXIDR2_ID_7\r
+\r
+\r
+/*** CAN1TXIDR3 - MSCAN 1 Transmit Identifier Register 3; 0x000001B3 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte RTR :1; /* Remote Transmission Request */\r
+ byte ID0 :1; /* Extended format identifier Bit 0 */\r
+ byte ID1 :1; /* Extended format identifier Bit 1 */\r
+ byte ID2 :1; /* Extended format identifier Bit 2 */\r
+ byte ID3 :1; /* Extended format identifier Bit 3 */\r
+ byte ID4 :1; /* Extended format identifier Bit 4 */\r
+ byte ID5 :1; /* Extended format identifier Bit 5 */\r
+ byte ID6 :1; /* Extended format identifier Bit 6 */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte grpID :7;\r
+ } MergedBits;\r
+} CAN1TXIDR3STR;\r
+extern volatile CAN1TXIDR3STR _CAN1TXIDR3 @(REG_BASE + 0x000001B3);\r
+#define CAN1TXIDR3 _CAN1TXIDR3.Byte\r
+#define CAN1TXIDR3_RTR _CAN1TXIDR3.Bits.RTR\r
+#define CAN1TXIDR3_ID0 _CAN1TXIDR3.Bits.ID0\r
+#define CAN1TXIDR3_ID1 _CAN1TXIDR3.Bits.ID1\r
+#define CAN1TXIDR3_ID2 _CAN1TXIDR3.Bits.ID2\r
+#define CAN1TXIDR3_ID3 _CAN1TXIDR3.Bits.ID3\r
+#define CAN1TXIDR3_ID4 _CAN1TXIDR3.Bits.ID4\r
+#define CAN1TXIDR3_ID5 _CAN1TXIDR3.Bits.ID5\r
+#define CAN1TXIDR3_ID6 _CAN1TXIDR3.Bits.ID6\r
+#define CAN1TXIDR3_ID _CAN1TXIDR3.MergedBits.grpID\r
+\r
+\r
+/*** CAN1TXDSR0 - MSCAN 1 Transmit Data Segment Register 0; 0x000001B4 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN1TXDSR0STR;\r
+extern volatile CAN1TXDSR0STR _CAN1TXDSR0 @(REG_BASE + 0x000001B4);\r
+#define CAN1TXDSR0 _CAN1TXDSR0.Byte\r
+#define CAN1TXDSR0_DB0 _CAN1TXDSR0.Bits.DB0\r
+#define CAN1TXDSR0_DB1 _CAN1TXDSR0.Bits.DB1\r
+#define CAN1TXDSR0_DB2 _CAN1TXDSR0.Bits.DB2\r
+#define CAN1TXDSR0_DB3 _CAN1TXDSR0.Bits.DB3\r
+#define CAN1TXDSR0_DB4 _CAN1TXDSR0.Bits.DB4\r
+#define CAN1TXDSR0_DB5 _CAN1TXDSR0.Bits.DB5\r
+#define CAN1TXDSR0_DB6 _CAN1TXDSR0.Bits.DB6\r
+#define CAN1TXDSR0_DB7 _CAN1TXDSR0.Bits.DB7\r
+#define CAN1TXDSR0_DB _CAN1TXDSR0.MergedBits.grpDB\r
+\r
+\r
+/*** CAN1TXDSR1 - MSCAN 1 Transmit Data Segment Register 1; 0x000001B5 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN1TXDSR1STR;\r
+extern volatile CAN1TXDSR1STR _CAN1TXDSR1 @(REG_BASE + 0x000001B5);\r
+#define CAN1TXDSR1 _CAN1TXDSR1.Byte\r
+#define CAN1TXDSR1_DB0 _CAN1TXDSR1.Bits.DB0\r
+#define CAN1TXDSR1_DB1 _CAN1TXDSR1.Bits.DB1\r
+#define CAN1TXDSR1_DB2 _CAN1TXDSR1.Bits.DB2\r
+#define CAN1TXDSR1_DB3 _CAN1TXDSR1.Bits.DB3\r
+#define CAN1TXDSR1_DB4 _CAN1TXDSR1.Bits.DB4\r
+#define CAN1TXDSR1_DB5 _CAN1TXDSR1.Bits.DB5\r
+#define CAN1TXDSR1_DB6 _CAN1TXDSR1.Bits.DB6\r
+#define CAN1TXDSR1_DB7 _CAN1TXDSR1.Bits.DB7\r
+#define CAN1TXDSR1_DB _CAN1TXDSR1.MergedBits.grpDB\r
+\r
+\r
+/*** CAN1TXDSR2 - MSCAN 1 Transmit Data Segment Register 2; 0x000001B6 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN1TXDSR2STR;\r
+extern volatile CAN1TXDSR2STR _CAN1TXDSR2 @(REG_BASE + 0x000001B6);\r
+#define CAN1TXDSR2 _CAN1TXDSR2.Byte\r
+#define CAN1TXDSR2_DB0 _CAN1TXDSR2.Bits.DB0\r
+#define CAN1TXDSR2_DB1 _CAN1TXDSR2.Bits.DB1\r
+#define CAN1TXDSR2_DB2 _CAN1TXDSR2.Bits.DB2\r
+#define CAN1TXDSR2_DB3 _CAN1TXDSR2.Bits.DB3\r
+#define CAN1TXDSR2_DB4 _CAN1TXDSR2.Bits.DB4\r
+#define CAN1TXDSR2_DB5 _CAN1TXDSR2.Bits.DB5\r
+#define CAN1TXDSR2_DB6 _CAN1TXDSR2.Bits.DB6\r
+#define CAN1TXDSR2_DB7 _CAN1TXDSR2.Bits.DB7\r
+#define CAN1TXDSR2_DB _CAN1TXDSR2.MergedBits.grpDB\r
+\r
+\r
+/*** CAN1TXDSR3 - MSCAN 1 Transmit Data Segment Register 3; 0x000001B7 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN1TXDSR3STR;\r
+extern volatile CAN1TXDSR3STR _CAN1TXDSR3 @(REG_BASE + 0x000001B7);\r
+#define CAN1TXDSR3 _CAN1TXDSR3.Byte\r
+#define CAN1TXDSR3_DB0 _CAN1TXDSR3.Bits.DB0\r
+#define CAN1TXDSR3_DB1 _CAN1TXDSR3.Bits.DB1\r
+#define CAN1TXDSR3_DB2 _CAN1TXDSR3.Bits.DB2\r
+#define CAN1TXDSR3_DB3 _CAN1TXDSR3.Bits.DB3\r
+#define CAN1TXDSR3_DB4 _CAN1TXDSR3.Bits.DB4\r
+#define CAN1TXDSR3_DB5 _CAN1TXDSR3.Bits.DB5\r
+#define CAN1TXDSR3_DB6 _CAN1TXDSR3.Bits.DB6\r
+#define CAN1TXDSR3_DB7 _CAN1TXDSR3.Bits.DB7\r
+#define CAN1TXDSR3_DB _CAN1TXDSR3.MergedBits.grpDB\r
+\r
+\r
+/*** CAN1TXDSR4 - MSCAN 1 Transmit Data Segment Register 4; 0x000001B8 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN1TXDSR4STR;\r
+extern volatile CAN1TXDSR4STR _CAN1TXDSR4 @(REG_BASE + 0x000001B8);\r
+#define CAN1TXDSR4 _CAN1TXDSR4.Byte\r
+#define CAN1TXDSR4_DB0 _CAN1TXDSR4.Bits.DB0\r
+#define CAN1TXDSR4_DB1 _CAN1TXDSR4.Bits.DB1\r
+#define CAN1TXDSR4_DB2 _CAN1TXDSR4.Bits.DB2\r
+#define CAN1TXDSR4_DB3 _CAN1TXDSR4.Bits.DB3\r
+#define CAN1TXDSR4_DB4 _CAN1TXDSR4.Bits.DB4\r
+#define CAN1TXDSR4_DB5 _CAN1TXDSR4.Bits.DB5\r
+#define CAN1TXDSR4_DB6 _CAN1TXDSR4.Bits.DB6\r
+#define CAN1TXDSR4_DB7 _CAN1TXDSR4.Bits.DB7\r
+#define CAN1TXDSR4_DB _CAN1TXDSR4.MergedBits.grpDB\r
+\r
+\r
+/*** CAN1TXDSR5 - MSCAN 1 Transmit Data Segment Register 5; 0x000001B9 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN1TXDSR5STR;\r
+extern volatile CAN1TXDSR5STR _CAN1TXDSR5 @(REG_BASE + 0x000001B9);\r
+#define CAN1TXDSR5 _CAN1TXDSR5.Byte\r
+#define CAN1TXDSR5_DB0 _CAN1TXDSR5.Bits.DB0\r
+#define CAN1TXDSR5_DB1 _CAN1TXDSR5.Bits.DB1\r
+#define CAN1TXDSR5_DB2 _CAN1TXDSR5.Bits.DB2\r
+#define CAN1TXDSR5_DB3 _CAN1TXDSR5.Bits.DB3\r
+#define CAN1TXDSR5_DB4 _CAN1TXDSR5.Bits.DB4\r
+#define CAN1TXDSR5_DB5 _CAN1TXDSR5.Bits.DB5\r
+#define CAN1TXDSR5_DB6 _CAN1TXDSR5.Bits.DB6\r
+#define CAN1TXDSR5_DB7 _CAN1TXDSR5.Bits.DB7\r
+#define CAN1TXDSR5_DB _CAN1TXDSR5.MergedBits.grpDB\r
+\r
+\r
+/*** CAN1TXDSR6 - MSCAN 1 Transmit Data Segment Register 6; 0x000001BA ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN1TXDSR6STR;\r
+extern volatile CAN1TXDSR6STR _CAN1TXDSR6 @(REG_BASE + 0x000001BA);\r
+#define CAN1TXDSR6 _CAN1TXDSR6.Byte\r
+#define CAN1TXDSR6_DB0 _CAN1TXDSR6.Bits.DB0\r
+#define CAN1TXDSR6_DB1 _CAN1TXDSR6.Bits.DB1\r
+#define CAN1TXDSR6_DB2 _CAN1TXDSR6.Bits.DB2\r
+#define CAN1TXDSR6_DB3 _CAN1TXDSR6.Bits.DB3\r
+#define CAN1TXDSR6_DB4 _CAN1TXDSR6.Bits.DB4\r
+#define CAN1TXDSR6_DB5 _CAN1TXDSR6.Bits.DB5\r
+#define CAN1TXDSR6_DB6 _CAN1TXDSR6.Bits.DB6\r
+#define CAN1TXDSR6_DB7 _CAN1TXDSR6.Bits.DB7\r
+#define CAN1TXDSR6_DB _CAN1TXDSR6.MergedBits.grpDB\r
+\r
+\r
+/*** CAN1TXDSR7 - MSCAN 1 Transmit Data Segment Register 7; 0x000001BB ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN1TXDSR7STR;\r
+extern volatile CAN1TXDSR7STR _CAN1TXDSR7 @(REG_BASE + 0x000001BB);\r
+#define CAN1TXDSR7 _CAN1TXDSR7.Byte\r
+#define CAN1TXDSR7_DB0 _CAN1TXDSR7.Bits.DB0\r
+#define CAN1TXDSR7_DB1 _CAN1TXDSR7.Bits.DB1\r
+#define CAN1TXDSR7_DB2 _CAN1TXDSR7.Bits.DB2\r
+#define CAN1TXDSR7_DB3 _CAN1TXDSR7.Bits.DB3\r
+#define CAN1TXDSR7_DB4 _CAN1TXDSR7.Bits.DB4\r
+#define CAN1TXDSR7_DB5 _CAN1TXDSR7.Bits.DB5\r
+#define CAN1TXDSR7_DB6 _CAN1TXDSR7.Bits.DB6\r
+#define CAN1TXDSR7_DB7 _CAN1TXDSR7.Bits.DB7\r
+#define CAN1TXDSR7_DB _CAN1TXDSR7.MergedBits.grpDB\r
+\r
+\r
+/*** CAN1TXDLR - MSCAN 1 Transmit Data Length Register; 0x000001BC ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DLC0 :1; /* Data Length Code Bit 0 */\r
+ byte DLC1 :1; /* Data Length Code Bit 1 */\r
+ byte DLC2 :1; /* Data Length Code Bit 2 */\r
+ byte DLC3 :1; /* Data Length Code Bit 3 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpDLC :4;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CAN1TXDLRSTR;\r
+extern volatile CAN1TXDLRSTR _CAN1TXDLR @(REG_BASE + 0x000001BC);\r
+#define CAN1TXDLR _CAN1TXDLR.Byte\r
+#define CAN1TXDLR_DLC0 _CAN1TXDLR.Bits.DLC0\r
+#define CAN1TXDLR_DLC1 _CAN1TXDLR.Bits.DLC1\r
+#define CAN1TXDLR_DLC2 _CAN1TXDLR.Bits.DLC2\r
+#define CAN1TXDLR_DLC3 _CAN1TXDLR.Bits.DLC3\r
+#define CAN1TXDLR_DLC _CAN1TXDLR.MergedBits.grpDLC\r
+\r
+\r
+/*** CAN1TXTBPR - MSCAN 1 Transmit Buffer Priority; 0x000001BF ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PRIO0 :1; /* Transmit Buffer Priority Bit 0 */\r
+ byte PRIO1 :1; /* Transmit Buffer Priority Bit 1 */\r
+ byte PRIO2 :1; /* Transmit Buffer Priority Bit 2 */\r
+ byte PRIO3 :1; /* Transmit Buffer Priority Bit 3 */\r
+ byte PRIO4 :1; /* Transmit Buffer Priority Bit 4 */\r
+ byte PRIO5 :1; /* Transmit Buffer Priority Bit 5 */\r
+ byte PRIO6 :1; /* Transmit Buffer Priority Bit 6 */\r
+ byte PRIO7 :1; /* Transmit Buffer Priority Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpPRIO :8;\r
+ } MergedBits;\r
+} CAN1TXTBPRSTR;\r
+extern volatile CAN1TXTBPRSTR _CAN1TXTBPR @(REG_BASE + 0x000001BF);\r
+#define CAN1TXTBPR _CAN1TXTBPR.Byte\r
+#define CAN1TXTBPR_PRIO0 _CAN1TXTBPR.Bits.PRIO0\r
+#define CAN1TXTBPR_PRIO1 _CAN1TXTBPR.Bits.PRIO1\r
+#define CAN1TXTBPR_PRIO2 _CAN1TXTBPR.Bits.PRIO2\r
+#define CAN1TXTBPR_PRIO3 _CAN1TXTBPR.Bits.PRIO3\r
+#define CAN1TXTBPR_PRIO4 _CAN1TXTBPR.Bits.PRIO4\r
+#define CAN1TXTBPR_PRIO5 _CAN1TXTBPR.Bits.PRIO5\r
+#define CAN1TXTBPR_PRIO6 _CAN1TXTBPR.Bits.PRIO6\r
+#define CAN1TXTBPR_PRIO7 _CAN1TXTBPR.Bits.PRIO7\r
+#define CAN1TXTBPR_PRIO _CAN1TXTBPR.MergedBits.grpPRIO\r
+\r
+\r
+/*** CAN2CTL0 - MSCAN 2 Control 0 Register; 0x000001C0 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte INITRQ :1; /* Initialization Mode Request */\r
+ byte SLPRQ :1; /* Sleep Mode Request */\r
+ byte WUPE :1; /* Wake-Up Enable */\r
+ byte TIME :1; /* Timer Enable */\r
+ byte SYNCH :1; /* Synchronized Status */\r
+ byte CSWAI :1; /* CAN Stops in Wait Mode */\r
+ byte RXACT :1; /* Receiver Active Status */\r
+ byte RXFRM :1; /* Received Frame Flag */\r
+ } Bits;\r
+} CAN2CTL0STR;\r
+extern volatile CAN2CTL0STR _CAN2CTL0 @(REG_BASE + 0x000001C0);\r
+#define CAN2CTL0 _CAN2CTL0.Byte\r
+#define CAN2CTL0_INITRQ _CAN2CTL0.Bits.INITRQ\r
+#define CAN2CTL0_SLPRQ _CAN2CTL0.Bits.SLPRQ\r
+#define CAN2CTL0_WUPE _CAN2CTL0.Bits.WUPE\r
+#define CAN2CTL0_TIME _CAN2CTL0.Bits.TIME\r
+#define CAN2CTL0_SYNCH _CAN2CTL0.Bits.SYNCH\r
+#define CAN2CTL0_CSWAI _CAN2CTL0.Bits.CSWAI\r
+#define CAN2CTL0_RXACT _CAN2CTL0.Bits.RXACT\r
+#define CAN2CTL0_RXFRM _CAN2CTL0.Bits.RXFRM\r
+\r
+\r
+/*** CAN2CTL1 - MSCAN 2 Control 1 Register; 0x000001C1 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte INITAK :1; /* Initialization Mode Acknowledge */\r
+ byte SLPAK :1; /* Sleep Mode Acknowledge */\r
+ byte WUPM :1; /* Wake-Up Mode */\r
+ byte :1; \r
+ byte LISTEN :1; /* Listen Only Mode */\r
+ byte LOOPB :1; /* Loop Back Self Test Mode */\r
+ byte CLKSRC :1; /* MSCAN 2 Clock Source */\r
+ byte CANE :1; /* MSCAN 2 Enable */\r
+ } Bits;\r
+} CAN2CTL1STR;\r
+extern volatile CAN2CTL1STR _CAN2CTL1 @(REG_BASE + 0x000001C1);\r
+#define CAN2CTL1 _CAN2CTL1.Byte\r
+#define CAN2CTL1_INITAK _CAN2CTL1.Bits.INITAK\r
+#define CAN2CTL1_SLPAK _CAN2CTL1.Bits.SLPAK\r
+#define CAN2CTL1_WUPM _CAN2CTL1.Bits.WUPM\r
+#define CAN2CTL1_LISTEN _CAN2CTL1.Bits.LISTEN\r
+#define CAN2CTL1_LOOPB _CAN2CTL1.Bits.LOOPB\r
+#define CAN2CTL1_CLKSRC _CAN2CTL1.Bits.CLKSRC\r
+#define CAN2CTL1_CANE _CAN2CTL1.Bits.CANE\r
+\r
+\r
+/*** CAN2BTR0 - MSCAN 2 Bus Timing Register 0; 0x000001C2 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte BRP0 :1; /* Baud Rate Prescaler 0 */\r
+ byte BRP1 :1; /* Baud Rate Prescaler 1 */\r
+ byte BRP2 :1; /* Baud Rate Prescaler 2 */\r
+ byte BRP3 :1; /* Baud Rate Prescaler 3 */\r
+ byte BRP4 :1; /* Baud Rate Prescaler 4 */\r
+ byte BRP5 :1; /* Baud Rate Prescaler 5 */\r
+ byte SJW0 :1; /* Synchronization Jump Width 0 */\r
+ byte SJW1 :1; /* Synchronization Jump Width 1 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBRP :6;\r
+ byte grpSJW :2;\r
+ } MergedBits;\r
+} CAN2BTR0STR;\r
+extern volatile CAN2BTR0STR _CAN2BTR0 @(REG_BASE + 0x000001C2);\r
+#define CAN2BTR0 _CAN2BTR0.Byte\r
+#define CAN2BTR0_BRP0 _CAN2BTR0.Bits.BRP0\r
+#define CAN2BTR0_BRP1 _CAN2BTR0.Bits.BRP1\r
+#define CAN2BTR0_BRP2 _CAN2BTR0.Bits.BRP2\r
+#define CAN2BTR0_BRP3 _CAN2BTR0.Bits.BRP3\r
+#define CAN2BTR0_BRP4 _CAN2BTR0.Bits.BRP4\r
+#define CAN2BTR0_BRP5 _CAN2BTR0.Bits.BRP5\r
+#define CAN2BTR0_SJW0 _CAN2BTR0.Bits.SJW0\r
+#define CAN2BTR0_SJW1 _CAN2BTR0.Bits.SJW1\r
+#define CAN2BTR0_BRP _CAN2BTR0.MergedBits.grpBRP\r
+#define CAN2BTR0_SJW _CAN2BTR0.MergedBits.grpSJW\r
+\r
+\r
+/*** CAN2BTR1 - MSCAN 2 Bus Timing Register 1; 0x000001C3 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte TSEG10 :1; /* Time Segment 1 */\r
+ byte TSEG11 :1; /* Time Segment 1 */\r
+ byte TSEG12 :1; /* Time Segment 1 */\r
+ byte TSEG13 :1; /* Time Segment 1 */\r
+ byte TSEG20 :1; /* Time Segment 2 */\r
+ byte TSEG21 :1; /* Time Segment 2 */\r
+ byte TSEG22 :1; /* Time Segment 2 */\r
+ byte SAMP :1; /* Sampling */\r
+ } Bits;\r
+ struct {\r
+ byte grpTSEG_10 :4;\r
+ byte grpTSEG_20 :3;\r
+ byte :1;\r
+ } MergedBits;\r
+} CAN2BTR1STR;\r
+extern volatile CAN2BTR1STR _CAN2BTR1 @(REG_BASE + 0x000001C3);\r
+#define CAN2BTR1 _CAN2BTR1.Byte\r
+#define CAN2BTR1_TSEG10 _CAN2BTR1.Bits.TSEG10\r
+#define CAN2BTR1_TSEG11 _CAN2BTR1.Bits.TSEG11\r
+#define CAN2BTR1_TSEG12 _CAN2BTR1.Bits.TSEG12\r
+#define CAN2BTR1_TSEG13 _CAN2BTR1.Bits.TSEG13\r
+#define CAN2BTR1_TSEG20 _CAN2BTR1.Bits.TSEG20\r
+#define CAN2BTR1_TSEG21 _CAN2BTR1.Bits.TSEG21\r
+#define CAN2BTR1_TSEG22 _CAN2BTR1.Bits.TSEG22\r
+#define CAN2BTR1_SAMP _CAN2BTR1.Bits.SAMP\r
+#define CAN2BTR1_TSEG_10 _CAN2BTR1.MergedBits.grpTSEG_10\r
+#define CAN2BTR1_TSEG_20 _CAN2BTR1.MergedBits.grpTSEG_20\r
+#define CAN2BTR1_TSEG CAN2BTR1_TSEG_10\r
+\r
+\r
+/*** CAN2RFLG - MSCAN 2 Receiver Flag Register; 0x000001C4 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte RXF :1; /* Receive Buffer Full */\r
+ byte OVRIF :1; /* Overrun Interrupt Flag */\r
+ byte TSTAT0 :1; /* Transmitter Status Bit 0 */\r
+ byte TSTAT1 :1; /* Transmitter Status Bit 1 */\r
+ byte RSTAT0 :1; /* Receiver Status Bit 0 */\r
+ byte RSTAT1 :1; /* Receiver Status Bit 1 */\r
+ byte CSCIF :1; /* CAN Status Change Interrupt Flag */\r
+ byte WUPIF :1; /* Wake-up Interrupt Flag */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte grpTSTAT :2;\r
+ byte grpRSTAT :2;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CAN2RFLGSTR;\r
+extern volatile CAN2RFLGSTR _CAN2RFLG @(REG_BASE + 0x000001C4);\r
+#define CAN2RFLG _CAN2RFLG.Byte\r
+#define CAN2RFLG_RXF _CAN2RFLG.Bits.RXF\r
+#define CAN2RFLG_OVRIF _CAN2RFLG.Bits.OVRIF\r
+#define CAN2RFLG_TSTAT0 _CAN2RFLG.Bits.TSTAT0\r
+#define CAN2RFLG_TSTAT1 _CAN2RFLG.Bits.TSTAT1\r
+#define CAN2RFLG_RSTAT0 _CAN2RFLG.Bits.RSTAT0\r
+#define CAN2RFLG_RSTAT1 _CAN2RFLG.Bits.RSTAT1\r
+#define CAN2RFLG_CSCIF _CAN2RFLG.Bits.CSCIF\r
+#define CAN2RFLG_WUPIF _CAN2RFLG.Bits.WUPIF\r
+#define CAN2RFLG_TSTAT _CAN2RFLG.MergedBits.grpTSTAT\r
+#define CAN2RFLG_RSTAT _CAN2RFLG.MergedBits.grpRSTAT\r
+\r
+\r
+/*** CAN2RIER - MSCAN 2 Receiver Interrupt Enable Register; 0x000001C5 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte RXFIE :1; /* Receiver Full Interrupt Enable */\r
+ byte OVRIE :1; /* Overrun Interrupt Enable */\r
+ byte TSTATE0 :1; /* Transmitter Status Change Enable 0 */\r
+ byte TSTATE1 :1; /* Transmitter Status Change Enable 1 */\r
+ byte RSTATE0 :1; /* Receiver Status Change Enable 0 */\r
+ byte RSTATE1 :1; /* Receiver Status Change Enable 1 */\r
+ byte CSCIE :1; /* CAN Status Change Interrupt Enable */\r
+ byte WUPIE :1; /* Wake-up Interrupt Enable */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte grpTSTATE :2;\r
+ byte grpRSTATE :2;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CAN2RIERSTR;\r
+extern volatile CAN2RIERSTR _CAN2RIER @(REG_BASE + 0x000001C5);\r
+#define CAN2RIER _CAN2RIER.Byte\r
+#define CAN2RIER_RXFIE _CAN2RIER.Bits.RXFIE\r
+#define CAN2RIER_OVRIE _CAN2RIER.Bits.OVRIE\r
+#define CAN2RIER_TSTATE0 _CAN2RIER.Bits.TSTATE0\r
+#define CAN2RIER_TSTATE1 _CAN2RIER.Bits.TSTATE1\r
+#define CAN2RIER_RSTATE0 _CAN2RIER.Bits.RSTATE0\r
+#define CAN2RIER_RSTATE1 _CAN2RIER.Bits.RSTATE1\r
+#define CAN2RIER_CSCIE _CAN2RIER.Bits.CSCIE\r
+#define CAN2RIER_WUPIE _CAN2RIER.Bits.WUPIE\r
+#define CAN2RIER_TSTATE _CAN2RIER.MergedBits.grpTSTATE\r
+#define CAN2RIER_RSTATE _CAN2RIER.MergedBits.grpRSTATE\r
+\r
+\r
+/*** CAN2TFLG - MSCAN 2 Transmitter Flag Register; 0x000001C6 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte TXE0 :1; /* Transmitter Buffer Empty 0 */\r
+ byte TXE1 :1; /* Transmitter Buffer Empty 1 */\r
+ byte TXE2 :1; /* Transmitter Buffer Empty 2 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpTXE :3;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CAN2TFLGSTR;\r
+extern volatile CAN2TFLGSTR _CAN2TFLG @(REG_BASE + 0x000001C6);\r
+#define CAN2TFLG _CAN2TFLG.Byte\r
+#define CAN2TFLG_TXE0 _CAN2TFLG.Bits.TXE0\r
+#define CAN2TFLG_TXE1 _CAN2TFLG.Bits.TXE1\r
+#define CAN2TFLG_TXE2 _CAN2TFLG.Bits.TXE2\r
+#define CAN2TFLG_TXE _CAN2TFLG.MergedBits.grpTXE\r
+\r
+\r
+/*** CAN2TIER - MSCAN 2 Transmitter Interrupt Enable Register; 0x000001C7 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte TXEIE0 :1; /* Transmitter Empty Interrupt Enable 0 */\r
+ byte TXEIE1 :1; /* Transmitter Empty Interrupt Enable 1 */\r
+ byte TXEIE2 :1; /* Transmitter Empty Interrupt Enable 2 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpTXEIE :3;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CAN2TIERSTR;\r
+extern volatile CAN2TIERSTR _CAN2TIER @(REG_BASE + 0x000001C7);\r
+#define CAN2TIER _CAN2TIER.Byte\r
+#define CAN2TIER_TXEIE0 _CAN2TIER.Bits.TXEIE0\r
+#define CAN2TIER_TXEIE1 _CAN2TIER.Bits.TXEIE1\r
+#define CAN2TIER_TXEIE2 _CAN2TIER.Bits.TXEIE2\r
+#define CAN2TIER_TXEIE _CAN2TIER.MergedBits.grpTXEIE\r
+\r
+\r
+/*** CAN2TARQ - MSCAN 2 Transmitter Message Abort Request; 0x000001C8 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ABTRQ0 :1; /* Abort Request 0 */\r
+ byte ABTRQ1 :1; /* Abort Request 1 */\r
+ byte ABTRQ2 :1; /* Abort Request 2 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpABTRQ :3;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CAN2TARQSTR;\r
+extern volatile CAN2TARQSTR _CAN2TARQ @(REG_BASE + 0x000001C8);\r
+#define CAN2TARQ _CAN2TARQ.Byte\r
+#define CAN2TARQ_ABTRQ0 _CAN2TARQ.Bits.ABTRQ0\r
+#define CAN2TARQ_ABTRQ1 _CAN2TARQ.Bits.ABTRQ1\r
+#define CAN2TARQ_ABTRQ2 _CAN2TARQ.Bits.ABTRQ2\r
+#define CAN2TARQ_ABTRQ _CAN2TARQ.MergedBits.grpABTRQ\r
+\r
+\r
+/*** CAN2TAAK - MSCAN 2 Transmitter Message Abort Control; 0x000001C9 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ABTAK0 :1; /* Abort Acknowledge 0 */\r
+ byte ABTAK1 :1; /* Abort Acknowledge 1 */\r
+ byte ABTAK2 :1; /* Abort Acknowledge 2 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpABTAK :3;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CAN2TAAKSTR;\r
+extern volatile CAN2TAAKSTR _CAN2TAAK @(REG_BASE + 0x000001C9);\r
+#define CAN2TAAK _CAN2TAAK.Byte\r
+#define CAN2TAAK_ABTAK0 _CAN2TAAK.Bits.ABTAK0\r
+#define CAN2TAAK_ABTAK1 _CAN2TAAK.Bits.ABTAK1\r
+#define CAN2TAAK_ABTAK2 _CAN2TAAK.Bits.ABTAK2\r
+#define CAN2TAAK_ABTAK _CAN2TAAK.MergedBits.grpABTAK\r
+\r
+\r
+/*** CAN2TBSEL - MSCAN 2 Transmit Buffer Selection; 0x000001CA ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte TX0 :1; /* Transmit Buffer Select 0 */\r
+ byte TX1 :1; /* Transmit Buffer Select 1 */\r
+ byte TX2 :1; /* Transmit Buffer Select 2 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpTX :3;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CAN2TBSELSTR;\r
+extern volatile CAN2TBSELSTR _CAN2TBSEL @(REG_BASE + 0x000001CA);\r
+#define CAN2TBSEL _CAN2TBSEL.Byte\r
+#define CAN2TBSEL_TX0 _CAN2TBSEL.Bits.TX0\r
+#define CAN2TBSEL_TX1 _CAN2TBSEL.Bits.TX1\r
+#define CAN2TBSEL_TX2 _CAN2TBSEL.Bits.TX2\r
+#define CAN2TBSEL_TX _CAN2TBSEL.MergedBits.grpTX\r
+\r
+\r
+/*** CAN2IDAC - MSCAN 2 Identifier Acceptance Control Register; 0x000001CB ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte IDHIT0 :1; /* Identifier Acceptance Hit Indicator 0 */\r
+ byte IDHIT1 :1; /* Identifier Acceptance Hit Indicator 1 */\r
+ byte IDHIT2 :1; /* Identifier Acceptance Hit Indicator 2 */\r
+ byte :1; \r
+ byte IDAM0 :1; /* Identifier Acceptance Mode 0 */\r
+ byte IDAM1 :1; /* Identifier Acceptance Mode 1 */\r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpIDHIT :3;\r
+ byte :1;\r
+ byte grpIDAM :2;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CAN2IDACSTR;\r
+extern volatile CAN2IDACSTR _CAN2IDAC @(REG_BASE + 0x000001CB);\r
+#define CAN2IDAC _CAN2IDAC.Byte\r
+#define CAN2IDAC_IDHIT0 _CAN2IDAC.Bits.IDHIT0\r
+#define CAN2IDAC_IDHIT1 _CAN2IDAC.Bits.IDHIT1\r
+#define CAN2IDAC_IDHIT2 _CAN2IDAC.Bits.IDHIT2\r
+#define CAN2IDAC_IDAM0 _CAN2IDAC.Bits.IDAM0\r
+#define CAN2IDAC_IDAM1 _CAN2IDAC.Bits.IDAM1\r
+#define CAN2IDAC_IDHIT _CAN2IDAC.MergedBits.grpIDHIT\r
+#define CAN2IDAC_IDAM _CAN2IDAC.MergedBits.grpIDAM\r
+\r
+\r
+/*** CAN2RXERR - MSCAN 2 Receive Error Counter Register; 0x000001CE ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte RXERR0 :1; /* Bit 0 */\r
+ byte RXERR1 :1; /* Bit 1 */\r
+ byte RXERR2 :1; /* Bit 2 */\r
+ byte RXERR3 :1; /* Bit 3 */\r
+ byte RXERR4 :1; /* Bit 4 */\r
+ byte RXERR5 :1; /* Bit 5 */\r
+ byte RXERR6 :1; /* Bit 6 */\r
+ byte RXERR7 :1; /* Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpRXERR :8;\r
+ } MergedBits;\r
+} CAN2RXERRSTR;\r
+extern volatile CAN2RXERRSTR _CAN2RXERR @(REG_BASE + 0x000001CE);\r
+#define CAN2RXERR _CAN2RXERR.Byte\r
+#define CAN2RXERR_RXERR0 _CAN2RXERR.Bits.RXERR0\r
+#define CAN2RXERR_RXERR1 _CAN2RXERR.Bits.RXERR1\r
+#define CAN2RXERR_RXERR2 _CAN2RXERR.Bits.RXERR2\r
+#define CAN2RXERR_RXERR3 _CAN2RXERR.Bits.RXERR3\r
+#define CAN2RXERR_RXERR4 _CAN2RXERR.Bits.RXERR4\r
+#define CAN2RXERR_RXERR5 _CAN2RXERR.Bits.RXERR5\r
+#define CAN2RXERR_RXERR6 _CAN2RXERR.Bits.RXERR6\r
+#define CAN2RXERR_RXERR7 _CAN2RXERR.Bits.RXERR7\r
+#define CAN2RXERR_RXERR _CAN2RXERR.MergedBits.grpRXERR\r
+\r
+\r
+/*** CAN2TXERR - MSCAN 2 Transmit Error Counter Register; 0x000001CF ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte TXERR0 :1; /* Bit 0 */\r
+ byte TXERR1 :1; /* Bit 1 */\r
+ byte TXERR2 :1; /* Bit 2 */\r
+ byte TXERR3 :1; /* Bit 3 */\r
+ byte TXERR4 :1; /* Bit 4 */\r
+ byte TXERR5 :1; /* Bit 5 */\r
+ byte TXERR6 :1; /* Bit 6 */\r
+ byte TXERR7 :1; /* Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpTXERR :8;\r
+ } MergedBits;\r
+} CAN2TXERRSTR;\r
+extern volatile CAN2TXERRSTR _CAN2TXERR @(REG_BASE + 0x000001CF);\r
+#define CAN2TXERR _CAN2TXERR.Byte\r
+#define CAN2TXERR_TXERR0 _CAN2TXERR.Bits.TXERR0\r
+#define CAN2TXERR_TXERR1 _CAN2TXERR.Bits.TXERR1\r
+#define CAN2TXERR_TXERR2 _CAN2TXERR.Bits.TXERR2\r
+#define CAN2TXERR_TXERR3 _CAN2TXERR.Bits.TXERR3\r
+#define CAN2TXERR_TXERR4 _CAN2TXERR.Bits.TXERR4\r
+#define CAN2TXERR_TXERR5 _CAN2TXERR.Bits.TXERR5\r
+#define CAN2TXERR_TXERR6 _CAN2TXERR.Bits.TXERR6\r
+#define CAN2TXERR_TXERR7 _CAN2TXERR.Bits.TXERR7\r
+#define CAN2TXERR_TXERR _CAN2TXERR.MergedBits.grpTXERR\r
+\r
+\r
+/*** CAN2IDAR0 - MSCAN 2 Identifier Acceptance Register 0; 0x000001D0 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AC0 :1; /* Acceptance Code Bit 0 */\r
+ byte AC1 :1; /* Acceptance Code Bit 1 */\r
+ byte AC2 :1; /* Acceptance Code Bit 2 */\r
+ byte AC3 :1; /* Acceptance Code Bit 3 */\r
+ byte AC4 :1; /* Acceptance Code Bit 4 */\r
+ byte AC5 :1; /* Acceptance Code Bit 5 */\r
+ byte AC6 :1; /* Acceptance Code Bit 6 */\r
+ byte AC7 :1; /* Acceptance Code Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAC :8;\r
+ } MergedBits;\r
+} CAN2IDAR0STR;\r
+extern volatile CAN2IDAR0STR _CAN2IDAR0 @(REG_BASE + 0x000001D0);\r
+#define CAN2IDAR0 _CAN2IDAR0.Byte\r
+#define CAN2IDAR0_AC0 _CAN2IDAR0.Bits.AC0\r
+#define CAN2IDAR0_AC1 _CAN2IDAR0.Bits.AC1\r
+#define CAN2IDAR0_AC2 _CAN2IDAR0.Bits.AC2\r
+#define CAN2IDAR0_AC3 _CAN2IDAR0.Bits.AC3\r
+#define CAN2IDAR0_AC4 _CAN2IDAR0.Bits.AC4\r
+#define CAN2IDAR0_AC5 _CAN2IDAR0.Bits.AC5\r
+#define CAN2IDAR0_AC6 _CAN2IDAR0.Bits.AC6\r
+#define CAN2IDAR0_AC7 _CAN2IDAR0.Bits.AC7\r
+#define CAN2IDAR0_AC _CAN2IDAR0.MergedBits.grpAC\r
+\r
+\r
+/*** CAN2IDAR1 - MSCAN 2 Identifier Acceptance Register 1; 0x000001D1 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AC0 :1; /* Acceptance Code Bit 0 */\r
+ byte AC1 :1; /* Acceptance Code Bit 1 */\r
+ byte AC2 :1; /* Acceptance Code Bit 2 */\r
+ byte AC3 :1; /* Acceptance Code Bit 3 */\r
+ byte AC4 :1; /* Acceptance Code Bit 4 */\r
+ byte AC5 :1; /* Acceptance Code Bit 5 */\r
+ byte AC6 :1; /* Acceptance Code Bit 6 */\r
+ byte AC7 :1; /* Acceptance Code Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAC :8;\r
+ } MergedBits;\r
+} CAN2IDAR1STR;\r
+extern volatile CAN2IDAR1STR _CAN2IDAR1 @(REG_BASE + 0x000001D1);\r
+#define CAN2IDAR1 _CAN2IDAR1.Byte\r
+#define CAN2IDAR1_AC0 _CAN2IDAR1.Bits.AC0\r
+#define CAN2IDAR1_AC1 _CAN2IDAR1.Bits.AC1\r
+#define CAN2IDAR1_AC2 _CAN2IDAR1.Bits.AC2\r
+#define CAN2IDAR1_AC3 _CAN2IDAR1.Bits.AC3\r
+#define CAN2IDAR1_AC4 _CAN2IDAR1.Bits.AC4\r
+#define CAN2IDAR1_AC5 _CAN2IDAR1.Bits.AC5\r
+#define CAN2IDAR1_AC6 _CAN2IDAR1.Bits.AC6\r
+#define CAN2IDAR1_AC7 _CAN2IDAR1.Bits.AC7\r
+#define CAN2IDAR1_AC _CAN2IDAR1.MergedBits.grpAC\r
+\r
+\r
+/*** CAN2IDAR2 - MSCAN 2 Identifier Acceptance Register 2; 0x000001D2 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AC0 :1; /* Acceptance Code Bit 0 */\r
+ byte AC1 :1; /* Acceptance Code Bit 1 */\r
+ byte AC2 :1; /* Acceptance Code Bit 2 */\r
+ byte AC3 :1; /* Acceptance Code Bit 3 */\r
+ byte AC4 :1; /* Acceptance Code Bit 4 */\r
+ byte AC5 :1; /* Acceptance Code Bit 5 */\r
+ byte AC6 :1; /* Acceptance Code Bit 6 */\r
+ byte AC7 :1; /* Acceptance Code Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAC :8;\r
+ } MergedBits;\r
+} CAN2IDAR2STR;\r
+extern volatile CAN2IDAR2STR _CAN2IDAR2 @(REG_BASE + 0x000001D2);\r
+#define CAN2IDAR2 _CAN2IDAR2.Byte\r
+#define CAN2IDAR2_AC0 _CAN2IDAR2.Bits.AC0\r
+#define CAN2IDAR2_AC1 _CAN2IDAR2.Bits.AC1\r
+#define CAN2IDAR2_AC2 _CAN2IDAR2.Bits.AC2\r
+#define CAN2IDAR2_AC3 _CAN2IDAR2.Bits.AC3\r
+#define CAN2IDAR2_AC4 _CAN2IDAR2.Bits.AC4\r
+#define CAN2IDAR2_AC5 _CAN2IDAR2.Bits.AC5\r
+#define CAN2IDAR2_AC6 _CAN2IDAR2.Bits.AC6\r
+#define CAN2IDAR2_AC7 _CAN2IDAR2.Bits.AC7\r
+#define CAN2IDAR2_AC _CAN2IDAR2.MergedBits.grpAC\r
+\r
+\r
+/*** CAN2IDAR3 - MSCAN 2 Identifier Acceptance Register 3; 0x000001D3 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AC0 :1; /* Acceptance Code Bit 0 */\r
+ byte AC1 :1; /* Acceptance Code Bit 1 */\r
+ byte AC2 :1; /* Acceptance Code Bit 2 */\r
+ byte AC3 :1; /* Acceptance Code Bit 3 */\r
+ byte AC4 :1; /* Acceptance Code Bit 4 */\r
+ byte AC5 :1; /* Acceptance Code Bit 5 */\r
+ byte AC6 :1; /* Acceptance Code Bit 6 */\r
+ byte AC7 :1; /* Acceptance Code Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAC :8;\r
+ } MergedBits;\r
+} CAN2IDAR3STR;\r
+extern volatile CAN2IDAR3STR _CAN2IDAR3 @(REG_BASE + 0x000001D3);\r
+#define CAN2IDAR3 _CAN2IDAR3.Byte\r
+#define CAN2IDAR3_AC0 _CAN2IDAR3.Bits.AC0\r
+#define CAN2IDAR3_AC1 _CAN2IDAR3.Bits.AC1\r
+#define CAN2IDAR3_AC2 _CAN2IDAR3.Bits.AC2\r
+#define CAN2IDAR3_AC3 _CAN2IDAR3.Bits.AC3\r
+#define CAN2IDAR3_AC4 _CAN2IDAR3.Bits.AC4\r
+#define CAN2IDAR3_AC5 _CAN2IDAR3.Bits.AC5\r
+#define CAN2IDAR3_AC6 _CAN2IDAR3.Bits.AC6\r
+#define CAN2IDAR3_AC7 _CAN2IDAR3.Bits.AC7\r
+#define CAN2IDAR3_AC _CAN2IDAR3.MergedBits.grpAC\r
+\r
+\r
+/*** CAN2IDMR0 - MSCAN 2 Identifier Mask Register 0; 0x000001D4 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AM0 :1; /* Acceptance Mask Bit 0 */\r
+ byte AM1 :1; /* Acceptance Mask Bit 1 */\r
+ byte AM2 :1; /* Acceptance Mask Bit 2 */\r
+ byte AM3 :1; /* Acceptance Mask Bit 3 */\r
+ byte AM4 :1; /* Acceptance Mask Bit 4 */\r
+ byte AM5 :1; /* Acceptance Mask Bit 5 */\r
+ byte AM6 :1; /* Acceptance Mask Bit 6 */\r
+ byte AM7 :1; /* Acceptance Mask Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAM :8;\r
+ } MergedBits;\r
+} CAN2IDMR0STR;\r
+extern volatile CAN2IDMR0STR _CAN2IDMR0 @(REG_BASE + 0x000001D4);\r
+#define CAN2IDMR0 _CAN2IDMR0.Byte\r
+#define CAN2IDMR0_AM0 _CAN2IDMR0.Bits.AM0\r
+#define CAN2IDMR0_AM1 _CAN2IDMR0.Bits.AM1\r
+#define CAN2IDMR0_AM2 _CAN2IDMR0.Bits.AM2\r
+#define CAN2IDMR0_AM3 _CAN2IDMR0.Bits.AM3\r
+#define CAN2IDMR0_AM4 _CAN2IDMR0.Bits.AM4\r
+#define CAN2IDMR0_AM5 _CAN2IDMR0.Bits.AM5\r
+#define CAN2IDMR0_AM6 _CAN2IDMR0.Bits.AM6\r
+#define CAN2IDMR0_AM7 _CAN2IDMR0.Bits.AM7\r
+#define CAN2IDMR0_AM _CAN2IDMR0.MergedBits.grpAM\r
+\r
+\r
+/*** CAN2IDMR1 - MSCAN 2 Identifier Mask Register 1; 0x000001D5 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AM0 :1; /* Acceptance Mask Bit 0 */\r
+ byte AM1 :1; /* Acceptance Mask Bit 1 */\r
+ byte AM2 :1; /* Acceptance Mask Bit 2 */\r
+ byte AM3 :1; /* Acceptance Mask Bit 3 */\r
+ byte AM4 :1; /* Acceptance Mask Bit 4 */\r
+ byte AM5 :1; /* Acceptance Mask Bit 5 */\r
+ byte AM6 :1; /* Acceptance Mask Bit 6 */\r
+ byte AM7 :1; /* Acceptance Mask Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAM :8;\r
+ } MergedBits;\r
+} CAN2IDMR1STR;\r
+extern volatile CAN2IDMR1STR _CAN2IDMR1 @(REG_BASE + 0x000001D5);\r
+#define CAN2IDMR1 _CAN2IDMR1.Byte\r
+#define CAN2IDMR1_AM0 _CAN2IDMR1.Bits.AM0\r
+#define CAN2IDMR1_AM1 _CAN2IDMR1.Bits.AM1\r
+#define CAN2IDMR1_AM2 _CAN2IDMR1.Bits.AM2\r
+#define CAN2IDMR1_AM3 _CAN2IDMR1.Bits.AM3\r
+#define CAN2IDMR1_AM4 _CAN2IDMR1.Bits.AM4\r
+#define CAN2IDMR1_AM5 _CAN2IDMR1.Bits.AM5\r
+#define CAN2IDMR1_AM6 _CAN2IDMR1.Bits.AM6\r
+#define CAN2IDMR1_AM7 _CAN2IDMR1.Bits.AM7\r
+#define CAN2IDMR1_AM _CAN2IDMR1.MergedBits.grpAM\r
+\r
+\r
+/*** CAN2IDMR2 - MSCAN 2 Identifier Mask Register 2; 0x000001D6 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AM0 :1; /* Acceptance Mask Bit 0 */\r
+ byte AM1 :1; /* Acceptance Mask Bit 1 */\r
+ byte AM2 :1; /* Acceptance Mask Bit 2 */\r
+ byte AM3 :1; /* Acceptance Mask Bit 3 */\r
+ byte AM4 :1; /* Acceptance Mask Bit 4 */\r
+ byte AM5 :1; /* Acceptance Mask Bit 5 */\r
+ byte AM6 :1; /* Acceptance Mask Bit 6 */\r
+ byte AM7 :1; /* Acceptance Mask Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAM :8;\r
+ } MergedBits;\r
+} CAN2IDMR2STR;\r
+extern volatile CAN2IDMR2STR _CAN2IDMR2 @(REG_BASE + 0x000001D6);\r
+#define CAN2IDMR2 _CAN2IDMR2.Byte\r
+#define CAN2IDMR2_AM0 _CAN2IDMR2.Bits.AM0\r
+#define CAN2IDMR2_AM1 _CAN2IDMR2.Bits.AM1\r
+#define CAN2IDMR2_AM2 _CAN2IDMR2.Bits.AM2\r
+#define CAN2IDMR2_AM3 _CAN2IDMR2.Bits.AM3\r
+#define CAN2IDMR2_AM4 _CAN2IDMR2.Bits.AM4\r
+#define CAN2IDMR2_AM5 _CAN2IDMR2.Bits.AM5\r
+#define CAN2IDMR2_AM6 _CAN2IDMR2.Bits.AM6\r
+#define CAN2IDMR2_AM7 _CAN2IDMR2.Bits.AM7\r
+#define CAN2IDMR2_AM _CAN2IDMR2.MergedBits.grpAM\r
+\r
+\r
+/*** CAN2IDMR3 - MSCAN 2 Identifier Mask Register 3; 0x000001D7 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AM0 :1; /* Acceptance Mask Bit 0 */\r
+ byte AM1 :1; /* Acceptance Mask Bit 1 */\r
+ byte AM2 :1; /* Acceptance Mask Bit 2 */\r
+ byte AM3 :1; /* Acceptance Mask Bit 3 */\r
+ byte AM4 :1; /* Acceptance Mask Bit 4 */\r
+ byte AM5 :1; /* Acceptance Mask Bit 5 */\r
+ byte AM6 :1; /* Acceptance Mask Bit 6 */\r
+ byte AM7 :1; /* Acceptance Mask Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAM :8;\r
+ } MergedBits;\r
+} CAN2IDMR3STR;\r
+extern volatile CAN2IDMR3STR _CAN2IDMR3 @(REG_BASE + 0x000001D7);\r
+#define CAN2IDMR3 _CAN2IDMR3.Byte\r
+#define CAN2IDMR3_AM0 _CAN2IDMR3.Bits.AM0\r
+#define CAN2IDMR3_AM1 _CAN2IDMR3.Bits.AM1\r
+#define CAN2IDMR3_AM2 _CAN2IDMR3.Bits.AM2\r
+#define CAN2IDMR3_AM3 _CAN2IDMR3.Bits.AM3\r
+#define CAN2IDMR3_AM4 _CAN2IDMR3.Bits.AM4\r
+#define CAN2IDMR3_AM5 _CAN2IDMR3.Bits.AM5\r
+#define CAN2IDMR3_AM6 _CAN2IDMR3.Bits.AM6\r
+#define CAN2IDMR3_AM7 _CAN2IDMR3.Bits.AM7\r
+#define CAN2IDMR3_AM _CAN2IDMR3.MergedBits.grpAM\r
+\r
+\r
+/*** CAN2IDAR4 - MSCAN 2 Identifier Acceptance Register 4; 0x000001D8 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AC0 :1; /* Acceptance Code Bit 0 */\r
+ byte AC1 :1; /* Acceptance Code Bit 1 */\r
+ byte AC2 :1; /* Acceptance Code Bit 2 */\r
+ byte AC3 :1; /* Acceptance Code Bit 3 */\r
+ byte AC4 :1; /* Acceptance Code Bit 4 */\r
+ byte AC5 :1; /* Acceptance Code Bit 5 */\r
+ byte AC6 :1; /* Acceptance Code Bit 6 */\r
+ byte AC7 :1; /* Acceptance Code Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAC :8;\r
+ } MergedBits;\r
+} CAN2IDAR4STR;\r
+extern volatile CAN2IDAR4STR _CAN2IDAR4 @(REG_BASE + 0x000001D8);\r
+#define CAN2IDAR4 _CAN2IDAR4.Byte\r
+#define CAN2IDAR4_AC0 _CAN2IDAR4.Bits.AC0\r
+#define CAN2IDAR4_AC1 _CAN2IDAR4.Bits.AC1\r
+#define CAN2IDAR4_AC2 _CAN2IDAR4.Bits.AC2\r
+#define CAN2IDAR4_AC3 _CAN2IDAR4.Bits.AC3\r
+#define CAN2IDAR4_AC4 _CAN2IDAR4.Bits.AC4\r
+#define CAN2IDAR4_AC5 _CAN2IDAR4.Bits.AC5\r
+#define CAN2IDAR4_AC6 _CAN2IDAR4.Bits.AC6\r
+#define CAN2IDAR4_AC7 _CAN2IDAR4.Bits.AC7\r
+#define CAN2IDAR4_AC _CAN2IDAR4.MergedBits.grpAC\r
+\r
+\r
+/*** CAN2IDAR5 - MSCAN 2 Identifier Acceptance Register 5; 0x000001D9 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AC0 :1; /* Acceptance Code Bit 0 */\r
+ byte AC1 :1; /* Acceptance Code Bit 1 */\r
+ byte AC2 :1; /* Acceptance Code Bit 2 */\r
+ byte AC3 :1; /* Acceptance Code Bit 3 */\r
+ byte AC4 :1; /* Acceptance Code Bit 4 */\r
+ byte AC5 :1; /* Acceptance Code Bit 5 */\r
+ byte AC6 :1; /* Acceptance Code Bit 6 */\r
+ byte AC7 :1; /* Acceptance Code Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAC :8;\r
+ } MergedBits;\r
+} CAN2IDAR5STR;\r
+extern volatile CAN2IDAR5STR _CAN2IDAR5 @(REG_BASE + 0x000001D9);\r
+#define CAN2IDAR5 _CAN2IDAR5.Byte\r
+#define CAN2IDAR5_AC0 _CAN2IDAR5.Bits.AC0\r
+#define CAN2IDAR5_AC1 _CAN2IDAR5.Bits.AC1\r
+#define CAN2IDAR5_AC2 _CAN2IDAR5.Bits.AC2\r
+#define CAN2IDAR5_AC3 _CAN2IDAR5.Bits.AC3\r
+#define CAN2IDAR5_AC4 _CAN2IDAR5.Bits.AC4\r
+#define CAN2IDAR5_AC5 _CAN2IDAR5.Bits.AC5\r
+#define CAN2IDAR5_AC6 _CAN2IDAR5.Bits.AC6\r
+#define CAN2IDAR5_AC7 _CAN2IDAR5.Bits.AC7\r
+#define CAN2IDAR5_AC _CAN2IDAR5.MergedBits.grpAC\r
+\r
+\r
+/*** CAN2IDAR6 - MSCAN 2 Identifier Acceptance Register 6; 0x000001DA ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AC0 :1; /* Acceptance Code Bit 0 */\r
+ byte AC1 :1; /* Acceptance Code Bit 1 */\r
+ byte AC2 :1; /* Acceptance Code Bit 2 */\r
+ byte AC3 :1; /* Acceptance Code Bit 3 */\r
+ byte AC4 :1; /* Acceptance Code Bit 4 */\r
+ byte AC5 :1; /* Acceptance Code Bit 5 */\r
+ byte AC6 :1; /* Acceptance Code Bit 6 */\r
+ byte AC7 :1; /* Acceptance Code Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAC :8;\r
+ } MergedBits;\r
+} CAN2IDAR6STR;\r
+extern volatile CAN2IDAR6STR _CAN2IDAR6 @(REG_BASE + 0x000001DA);\r
+#define CAN2IDAR6 _CAN2IDAR6.Byte\r
+#define CAN2IDAR6_AC0 _CAN2IDAR6.Bits.AC0\r
+#define CAN2IDAR6_AC1 _CAN2IDAR6.Bits.AC1\r
+#define CAN2IDAR6_AC2 _CAN2IDAR6.Bits.AC2\r
+#define CAN2IDAR6_AC3 _CAN2IDAR6.Bits.AC3\r
+#define CAN2IDAR6_AC4 _CAN2IDAR6.Bits.AC4\r
+#define CAN2IDAR6_AC5 _CAN2IDAR6.Bits.AC5\r
+#define CAN2IDAR6_AC6 _CAN2IDAR6.Bits.AC6\r
+#define CAN2IDAR6_AC7 _CAN2IDAR6.Bits.AC7\r
+#define CAN2IDAR6_AC _CAN2IDAR6.MergedBits.grpAC\r
+\r
+\r
+/*** CAN2IDAR7 - MSCAN 2 Identifier Acceptance Register 7; 0x000001DB ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AC0 :1; /* Acceptance Code Bit 0 */\r
+ byte AC1 :1; /* Acceptance Code Bit 1 */\r
+ byte AC2 :1; /* Acceptance Code Bit 2 */\r
+ byte AC3 :1; /* Acceptance Code Bit 3 */\r
+ byte AC4 :1; /* Acceptance Code Bit 4 */\r
+ byte AC5 :1; /* Acceptance Code Bit 5 */\r
+ byte AC6 :1; /* Acceptance Code Bit 6 */\r
+ byte AC7 :1; /* Acceptance Code Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAC :8;\r
+ } MergedBits;\r
+} CAN2IDAR7STR;\r
+extern volatile CAN2IDAR7STR _CAN2IDAR7 @(REG_BASE + 0x000001DB);\r
+#define CAN2IDAR7 _CAN2IDAR7.Byte\r
+#define CAN2IDAR7_AC0 _CAN2IDAR7.Bits.AC0\r
+#define CAN2IDAR7_AC1 _CAN2IDAR7.Bits.AC1\r
+#define CAN2IDAR7_AC2 _CAN2IDAR7.Bits.AC2\r
+#define CAN2IDAR7_AC3 _CAN2IDAR7.Bits.AC3\r
+#define CAN2IDAR7_AC4 _CAN2IDAR7.Bits.AC4\r
+#define CAN2IDAR7_AC5 _CAN2IDAR7.Bits.AC5\r
+#define CAN2IDAR7_AC6 _CAN2IDAR7.Bits.AC6\r
+#define CAN2IDAR7_AC7 _CAN2IDAR7.Bits.AC7\r
+#define CAN2IDAR7_AC _CAN2IDAR7.MergedBits.grpAC\r
+\r
+\r
+/*** CAN2IDMR4 - MSCAN 2 Identifier Mask Register 4; 0x000001DC ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AM0 :1; /* Acceptance Mask Bit 0 */\r
+ byte AM1 :1; /* Acceptance Mask Bit 1 */\r
+ byte AM2 :1; /* Acceptance Mask Bit 2 */\r
+ byte AM3 :1; /* Acceptance Mask Bit 3 */\r
+ byte AM4 :1; /* Acceptance Mask Bit 4 */\r
+ byte AM5 :1; /* Acceptance Mask Bit 5 */\r
+ byte AM6 :1; /* Acceptance Mask Bit 6 */\r
+ byte AM7 :1; /* Acceptance Mask Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAM :8;\r
+ } MergedBits;\r
+} CAN2IDMR4STR;\r
+extern volatile CAN2IDMR4STR _CAN2IDMR4 @(REG_BASE + 0x000001DC);\r
+#define CAN2IDMR4 _CAN2IDMR4.Byte\r
+#define CAN2IDMR4_AM0 _CAN2IDMR4.Bits.AM0\r
+#define CAN2IDMR4_AM1 _CAN2IDMR4.Bits.AM1\r
+#define CAN2IDMR4_AM2 _CAN2IDMR4.Bits.AM2\r
+#define CAN2IDMR4_AM3 _CAN2IDMR4.Bits.AM3\r
+#define CAN2IDMR4_AM4 _CAN2IDMR4.Bits.AM4\r
+#define CAN2IDMR4_AM5 _CAN2IDMR4.Bits.AM5\r
+#define CAN2IDMR4_AM6 _CAN2IDMR4.Bits.AM6\r
+#define CAN2IDMR4_AM7 _CAN2IDMR4.Bits.AM7\r
+#define CAN2IDMR4_AM _CAN2IDMR4.MergedBits.grpAM\r
+\r
+\r
+/*** CAN2IDMR5 - MSCAN 2 Identifier Mask Register 5; 0x000001DD ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AM0 :1; /* Acceptance Mask Bit 0 */\r
+ byte AM1 :1; /* Acceptance Mask Bit 1 */\r
+ byte AM2 :1; /* Acceptance Mask Bit 2 */\r
+ byte AM3 :1; /* Acceptance Mask Bit 3 */\r
+ byte AM4 :1; /* Acceptance Mask Bit 4 */\r
+ byte AM5 :1; /* Acceptance Mask Bit 5 */\r
+ byte AM6 :1; /* Acceptance Mask Bit 6 */\r
+ byte AM7 :1; /* Acceptance Mask Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAM :8;\r
+ } MergedBits;\r
+} CAN2IDMR5STR;\r
+extern volatile CAN2IDMR5STR _CAN2IDMR5 @(REG_BASE + 0x000001DD);\r
+#define CAN2IDMR5 _CAN2IDMR5.Byte\r
+#define CAN2IDMR5_AM0 _CAN2IDMR5.Bits.AM0\r
+#define CAN2IDMR5_AM1 _CAN2IDMR5.Bits.AM1\r
+#define CAN2IDMR5_AM2 _CAN2IDMR5.Bits.AM2\r
+#define CAN2IDMR5_AM3 _CAN2IDMR5.Bits.AM3\r
+#define CAN2IDMR5_AM4 _CAN2IDMR5.Bits.AM4\r
+#define CAN2IDMR5_AM5 _CAN2IDMR5.Bits.AM5\r
+#define CAN2IDMR5_AM6 _CAN2IDMR5.Bits.AM6\r
+#define CAN2IDMR5_AM7 _CAN2IDMR5.Bits.AM7\r
+#define CAN2IDMR5_AM _CAN2IDMR5.MergedBits.grpAM\r
+\r
+\r
+/*** CAN2IDMR6 - MSCAN 2 Identifier Mask Register 6; 0x000001DE ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AM0 :1; /* Acceptance Mask Bit 0 */\r
+ byte AM1 :1; /* Acceptance Mask Bit 1 */\r
+ byte AM2 :1; /* Acceptance Mask Bit 2 */\r
+ byte AM3 :1; /* Acceptance Mask Bit 3 */\r
+ byte AM4 :1; /* Acceptance Mask Bit 4 */\r
+ byte AM5 :1; /* Acceptance Mask Bit 5 */\r
+ byte AM6 :1; /* Acceptance Mask Bit 6 */\r
+ byte AM7 :1; /* Acceptance Mask Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAM :8;\r
+ } MergedBits;\r
+} CAN2IDMR6STR;\r
+extern volatile CAN2IDMR6STR _CAN2IDMR6 @(REG_BASE + 0x000001DE);\r
+#define CAN2IDMR6 _CAN2IDMR6.Byte\r
+#define CAN2IDMR6_AM0 _CAN2IDMR6.Bits.AM0\r
+#define CAN2IDMR6_AM1 _CAN2IDMR6.Bits.AM1\r
+#define CAN2IDMR6_AM2 _CAN2IDMR6.Bits.AM2\r
+#define CAN2IDMR6_AM3 _CAN2IDMR6.Bits.AM3\r
+#define CAN2IDMR6_AM4 _CAN2IDMR6.Bits.AM4\r
+#define CAN2IDMR6_AM5 _CAN2IDMR6.Bits.AM5\r
+#define CAN2IDMR6_AM6 _CAN2IDMR6.Bits.AM6\r
+#define CAN2IDMR6_AM7 _CAN2IDMR6.Bits.AM7\r
+#define CAN2IDMR6_AM _CAN2IDMR6.MergedBits.grpAM\r
+\r
+\r
+/*** CAN2IDMR7 - MSCAN 2 Identifier Mask Register 7; 0x000001DF ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AM0 :1; /* Acceptance Mask Bit 0 */\r
+ byte AM1 :1; /* Acceptance Mask Bit 1 */\r
+ byte AM2 :1; /* Acceptance Mask Bit 2 */\r
+ byte AM3 :1; /* Acceptance Mask Bit 3 */\r
+ byte AM4 :1; /* Acceptance Mask Bit 4 */\r
+ byte AM5 :1; /* Acceptance Mask Bit 5 */\r
+ byte AM6 :1; /* Acceptance Mask Bit 6 */\r
+ byte AM7 :1; /* Acceptance Mask Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAM :8;\r
+ } MergedBits;\r
+} CAN2IDMR7STR;\r
+extern volatile CAN2IDMR7STR _CAN2IDMR7 @(REG_BASE + 0x000001DF);\r
+#define CAN2IDMR7 _CAN2IDMR7.Byte\r
+#define CAN2IDMR7_AM0 _CAN2IDMR7.Bits.AM0\r
+#define CAN2IDMR7_AM1 _CAN2IDMR7.Bits.AM1\r
+#define CAN2IDMR7_AM2 _CAN2IDMR7.Bits.AM2\r
+#define CAN2IDMR7_AM3 _CAN2IDMR7.Bits.AM3\r
+#define CAN2IDMR7_AM4 _CAN2IDMR7.Bits.AM4\r
+#define CAN2IDMR7_AM5 _CAN2IDMR7.Bits.AM5\r
+#define CAN2IDMR7_AM6 _CAN2IDMR7.Bits.AM6\r
+#define CAN2IDMR7_AM7 _CAN2IDMR7.Bits.AM7\r
+#define CAN2IDMR7_AM _CAN2IDMR7.MergedBits.grpAM\r
+\r
+\r
+/*** CAN2RXIDR0 - MSCAN 2 Receive Identifier Register 0; 0x000001E0 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ID21 :1; /* Extended format identifier Bit 21 */\r
+ byte ID22 :1; /* Extended format identifier Bit 22 */\r
+ byte ID23 :1; /* Extended format identifier Bit 23 */\r
+ byte ID24 :1; /* Extended format identifier Bit 24 */\r
+ byte ID25 :1; /* Extended format identifier Bit 25 */\r
+ byte ID26 :1; /* Extended format identifier Bit 26 */\r
+ byte ID27 :1; /* Extended format identifier Bit 27 */\r
+ byte ID28 :1; /* Extended format identifier Bit 28 */\r
+ } Bits;\r
+ struct {\r
+ byte grpID_21 :8;\r
+ } MergedBits;\r
+} CAN2RXIDR0STR;\r
+extern volatile CAN2RXIDR0STR _CAN2RXIDR0 @(REG_BASE + 0x000001E0);\r
+#define CAN2RXIDR0 _CAN2RXIDR0.Byte\r
+#define CAN2RXIDR0_ID21 _CAN2RXIDR0.Bits.ID21\r
+#define CAN2RXIDR0_ID22 _CAN2RXIDR0.Bits.ID22\r
+#define CAN2RXIDR0_ID23 _CAN2RXIDR0.Bits.ID23\r
+#define CAN2RXIDR0_ID24 _CAN2RXIDR0.Bits.ID24\r
+#define CAN2RXIDR0_ID25 _CAN2RXIDR0.Bits.ID25\r
+#define CAN2RXIDR0_ID26 _CAN2RXIDR0.Bits.ID26\r
+#define CAN2RXIDR0_ID27 _CAN2RXIDR0.Bits.ID27\r
+#define CAN2RXIDR0_ID28 _CAN2RXIDR0.Bits.ID28\r
+#define CAN2RXIDR0_ID_21 _CAN2RXIDR0.MergedBits.grpID_21\r
+#define CAN2RXIDR0_ID CAN2RXIDR0_ID_21\r
+\r
+\r
+/*** CAN2RXIDR1 - MSCAN 2 Receive Identifier Register 1; 0x000001E1 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ID15 :1; /* Extended format identifier Bit 15 */\r
+ byte ID16 :1; /* Extended format identifier Bit 16 */\r
+ byte ID17 :1; /* Extended format identifier Bit 17 */\r
+ byte IDE :1; /* ID Extended */\r
+ byte SRR :1; /* Substitute Remote Request */\r
+ byte ID18 :1; /* Extended format identifier Bit 18 */\r
+ byte ID19 :1; /* Extended format identifier Bit 19 */\r
+ byte ID20 :1; /* Extended format identifier Bit 20 */\r
+ } Bits;\r
+ struct {\r
+ byte grpID_15 :3;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpID_18 :3;\r
+ } MergedBits;\r
+} CAN2RXIDR1STR;\r
+extern volatile CAN2RXIDR1STR _CAN2RXIDR1 @(REG_BASE + 0x000001E1);\r
+#define CAN2RXIDR1 _CAN2RXIDR1.Byte\r
+#define CAN2RXIDR1_ID15 _CAN2RXIDR1.Bits.ID15\r
+#define CAN2RXIDR1_ID16 _CAN2RXIDR1.Bits.ID16\r
+#define CAN2RXIDR1_ID17 _CAN2RXIDR1.Bits.ID17\r
+#define CAN2RXIDR1_IDE _CAN2RXIDR1.Bits.IDE\r
+#define CAN2RXIDR1_SRR _CAN2RXIDR1.Bits.SRR\r
+#define CAN2RXIDR1_ID18 _CAN2RXIDR1.Bits.ID18\r
+#define CAN2RXIDR1_ID19 _CAN2RXIDR1.Bits.ID19\r
+#define CAN2RXIDR1_ID20 _CAN2RXIDR1.Bits.ID20\r
+#define CAN2RXIDR1_ID_15 _CAN2RXIDR1.MergedBits.grpID_15\r
+#define CAN2RXIDR1_ID_18 _CAN2RXIDR1.MergedBits.grpID_18\r
+#define CAN2RXIDR1_ID CAN2RXIDR1_ID_15\r
+\r
+\r
+/*** CAN2RXIDR2 - MSCAN 2 Receive Identifier Register 2; 0x000001E2 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ID7 :1; /* Extended format identifier Bit 7 */\r
+ byte ID8 :1; /* Extended format identifier Bit 8 */\r
+ byte ID9 :1; /* Extended format identifier Bit 9 */\r
+ byte ID10 :1; /* Extended format identifier Bit 10 */\r
+ byte ID11 :1; /* Extended format identifier Bit 11 */\r
+ byte ID12 :1; /* Extended format identifier Bit 12 */\r
+ byte ID13 :1; /* Extended format identifier Bit 13 */\r
+ byte ID14 :1; /* Extended format identifier Bit 14 */\r
+ } Bits;\r
+ struct {\r
+ byte grpID_7 :8;\r
+ } MergedBits;\r
+} CAN2RXIDR2STR;\r
+extern volatile CAN2RXIDR2STR _CAN2RXIDR2 @(REG_BASE + 0x000001E2);\r
+#define CAN2RXIDR2 _CAN2RXIDR2.Byte\r
+#define CAN2RXIDR2_ID7 _CAN2RXIDR2.Bits.ID7\r
+#define CAN2RXIDR2_ID8 _CAN2RXIDR2.Bits.ID8\r
+#define CAN2RXIDR2_ID9 _CAN2RXIDR2.Bits.ID9\r
+#define CAN2RXIDR2_ID10 _CAN2RXIDR2.Bits.ID10\r
+#define CAN2RXIDR2_ID11 _CAN2RXIDR2.Bits.ID11\r
+#define CAN2RXIDR2_ID12 _CAN2RXIDR2.Bits.ID12\r
+#define CAN2RXIDR2_ID13 _CAN2RXIDR2.Bits.ID13\r
+#define CAN2RXIDR2_ID14 _CAN2RXIDR2.Bits.ID14\r
+#define CAN2RXIDR2_ID_7 _CAN2RXIDR2.MergedBits.grpID_7\r
+#define CAN2RXIDR2_ID CAN2RXIDR2_ID_7\r
+\r
+\r
+/*** CAN2RXIDR3 - MSCAN 2 Receive Identifier Register 3; 0x000001E3 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte RTR :1; /* Remote Transmission Request */\r
+ byte ID0 :1; /* Extended format identifier Bit 0 */\r
+ byte ID1 :1; /* Extended format identifier Bit 1 */\r
+ byte ID2 :1; /* Extended format identifier Bit 2 */\r
+ byte ID3 :1; /* Extended format identifier Bit 3 */\r
+ byte ID4 :1; /* Extended format identifier Bit 4 */\r
+ byte ID5 :1; /* Extended format identifier Bit 5 */\r
+ byte ID6 :1; /* Extended format identifier Bit 6 */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte grpID :7;\r
+ } MergedBits;\r
+} CAN2RXIDR3STR;\r
+extern volatile CAN2RXIDR3STR _CAN2RXIDR3 @(REG_BASE + 0x000001E3);\r
+#define CAN2RXIDR3 _CAN2RXIDR3.Byte\r
+#define CAN2RXIDR3_RTR _CAN2RXIDR3.Bits.RTR\r
+#define CAN2RXIDR3_ID0 _CAN2RXIDR3.Bits.ID0\r
+#define CAN2RXIDR3_ID1 _CAN2RXIDR3.Bits.ID1\r
+#define CAN2RXIDR3_ID2 _CAN2RXIDR3.Bits.ID2\r
+#define CAN2RXIDR3_ID3 _CAN2RXIDR3.Bits.ID3\r
+#define CAN2RXIDR3_ID4 _CAN2RXIDR3.Bits.ID4\r
+#define CAN2RXIDR3_ID5 _CAN2RXIDR3.Bits.ID5\r
+#define CAN2RXIDR3_ID6 _CAN2RXIDR3.Bits.ID6\r
+#define CAN2RXIDR3_ID _CAN2RXIDR3.MergedBits.grpID\r
+\r
+\r
+/*** CAN2RXDSR0 - MSCAN 2 Receive Data Segment Register 0; 0x000001E4 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN2RXDSR0STR;\r
+extern volatile CAN2RXDSR0STR _CAN2RXDSR0 @(REG_BASE + 0x000001E4);\r
+#define CAN2RXDSR0 _CAN2RXDSR0.Byte\r
+#define CAN2RXDSR0_DB0 _CAN2RXDSR0.Bits.DB0\r
+#define CAN2RXDSR0_DB1 _CAN2RXDSR0.Bits.DB1\r
+#define CAN2RXDSR0_DB2 _CAN2RXDSR0.Bits.DB2\r
+#define CAN2RXDSR0_DB3 _CAN2RXDSR0.Bits.DB3\r
+#define CAN2RXDSR0_DB4 _CAN2RXDSR0.Bits.DB4\r
+#define CAN2RXDSR0_DB5 _CAN2RXDSR0.Bits.DB5\r
+#define CAN2RXDSR0_DB6 _CAN2RXDSR0.Bits.DB6\r
+#define CAN2RXDSR0_DB7 _CAN2RXDSR0.Bits.DB7\r
+#define CAN2RXDSR0_DB _CAN2RXDSR0.MergedBits.grpDB\r
+\r
+\r
+/*** CAN2RXDSR1 - MSCAN 2 Receive Data Segment Register 1; 0x000001E5 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN2RXDSR1STR;\r
+extern volatile CAN2RXDSR1STR _CAN2RXDSR1 @(REG_BASE + 0x000001E5);\r
+#define CAN2RXDSR1 _CAN2RXDSR1.Byte\r
+#define CAN2RXDSR1_DB0 _CAN2RXDSR1.Bits.DB0\r
+#define CAN2RXDSR1_DB1 _CAN2RXDSR1.Bits.DB1\r
+#define CAN2RXDSR1_DB2 _CAN2RXDSR1.Bits.DB2\r
+#define CAN2RXDSR1_DB3 _CAN2RXDSR1.Bits.DB3\r
+#define CAN2RXDSR1_DB4 _CAN2RXDSR1.Bits.DB4\r
+#define CAN2RXDSR1_DB5 _CAN2RXDSR1.Bits.DB5\r
+#define CAN2RXDSR1_DB6 _CAN2RXDSR1.Bits.DB6\r
+#define CAN2RXDSR1_DB7 _CAN2RXDSR1.Bits.DB7\r
+#define CAN2RXDSR1_DB _CAN2RXDSR1.MergedBits.grpDB\r
+\r
+\r
+/*** CAN2RXDSR2 - MSCAN 2 Receive Data Segment Register 2; 0x000001E6 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN2RXDSR2STR;\r
+extern volatile CAN2RXDSR2STR _CAN2RXDSR2 @(REG_BASE + 0x000001E6);\r
+#define CAN2RXDSR2 _CAN2RXDSR2.Byte\r
+#define CAN2RXDSR2_DB0 _CAN2RXDSR2.Bits.DB0\r
+#define CAN2RXDSR2_DB1 _CAN2RXDSR2.Bits.DB1\r
+#define CAN2RXDSR2_DB2 _CAN2RXDSR2.Bits.DB2\r
+#define CAN2RXDSR2_DB3 _CAN2RXDSR2.Bits.DB3\r
+#define CAN2RXDSR2_DB4 _CAN2RXDSR2.Bits.DB4\r
+#define CAN2RXDSR2_DB5 _CAN2RXDSR2.Bits.DB5\r
+#define CAN2RXDSR2_DB6 _CAN2RXDSR2.Bits.DB6\r
+#define CAN2RXDSR2_DB7 _CAN2RXDSR2.Bits.DB7\r
+#define CAN2RXDSR2_DB _CAN2RXDSR2.MergedBits.grpDB\r
+\r
+\r
+/*** CAN2RXDSR3 - MSCAN 2 Receive Data Segment Register 3; 0x000001E7 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN2RXDSR3STR;\r
+extern volatile CAN2RXDSR3STR _CAN2RXDSR3 @(REG_BASE + 0x000001E7);\r
+#define CAN2RXDSR3 _CAN2RXDSR3.Byte\r
+#define CAN2RXDSR3_DB0 _CAN2RXDSR3.Bits.DB0\r
+#define CAN2RXDSR3_DB1 _CAN2RXDSR3.Bits.DB1\r
+#define CAN2RXDSR3_DB2 _CAN2RXDSR3.Bits.DB2\r
+#define CAN2RXDSR3_DB3 _CAN2RXDSR3.Bits.DB3\r
+#define CAN2RXDSR3_DB4 _CAN2RXDSR3.Bits.DB4\r
+#define CAN2RXDSR3_DB5 _CAN2RXDSR3.Bits.DB5\r
+#define CAN2RXDSR3_DB6 _CAN2RXDSR3.Bits.DB6\r
+#define CAN2RXDSR3_DB7 _CAN2RXDSR3.Bits.DB7\r
+#define CAN2RXDSR3_DB _CAN2RXDSR3.MergedBits.grpDB\r
+\r
+\r
+/*** CAN2RXDSR4 - MSCAN 2 Receive Data Segment Register 4; 0x000001E8 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN2RXDSR4STR;\r
+extern volatile CAN2RXDSR4STR _CAN2RXDSR4 @(REG_BASE + 0x000001E8);\r
+#define CAN2RXDSR4 _CAN2RXDSR4.Byte\r
+#define CAN2RXDSR4_DB0 _CAN2RXDSR4.Bits.DB0\r
+#define CAN2RXDSR4_DB1 _CAN2RXDSR4.Bits.DB1\r
+#define CAN2RXDSR4_DB2 _CAN2RXDSR4.Bits.DB2\r
+#define CAN2RXDSR4_DB3 _CAN2RXDSR4.Bits.DB3\r
+#define CAN2RXDSR4_DB4 _CAN2RXDSR4.Bits.DB4\r
+#define CAN2RXDSR4_DB5 _CAN2RXDSR4.Bits.DB5\r
+#define CAN2RXDSR4_DB6 _CAN2RXDSR4.Bits.DB6\r
+#define CAN2RXDSR4_DB7 _CAN2RXDSR4.Bits.DB7\r
+#define CAN2RXDSR4_DB _CAN2RXDSR4.MergedBits.grpDB\r
+\r
+\r
+/*** CAN2RXDSR5 - MSCAN 2 Receive Data Segment Register 5; 0x000001E9 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN2RXDSR5STR;\r
+extern volatile CAN2RXDSR5STR _CAN2RXDSR5 @(REG_BASE + 0x000001E9);\r
+#define CAN2RXDSR5 _CAN2RXDSR5.Byte\r
+#define CAN2RXDSR5_DB0 _CAN2RXDSR5.Bits.DB0\r
+#define CAN2RXDSR5_DB1 _CAN2RXDSR5.Bits.DB1\r
+#define CAN2RXDSR5_DB2 _CAN2RXDSR5.Bits.DB2\r
+#define CAN2RXDSR5_DB3 _CAN2RXDSR5.Bits.DB3\r
+#define CAN2RXDSR5_DB4 _CAN2RXDSR5.Bits.DB4\r
+#define CAN2RXDSR5_DB5 _CAN2RXDSR5.Bits.DB5\r
+#define CAN2RXDSR5_DB6 _CAN2RXDSR5.Bits.DB6\r
+#define CAN2RXDSR5_DB7 _CAN2RXDSR5.Bits.DB7\r
+#define CAN2RXDSR5_DB _CAN2RXDSR5.MergedBits.grpDB\r
+\r
+\r
+/*** CAN2RXDSR6 - MSCAN 2 Receive Data Segment Register 6; 0x000001EA ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN2RXDSR6STR;\r
+extern volatile CAN2RXDSR6STR _CAN2RXDSR6 @(REG_BASE + 0x000001EA);\r
+#define CAN2RXDSR6 _CAN2RXDSR6.Byte\r
+#define CAN2RXDSR6_DB0 _CAN2RXDSR6.Bits.DB0\r
+#define CAN2RXDSR6_DB1 _CAN2RXDSR6.Bits.DB1\r
+#define CAN2RXDSR6_DB2 _CAN2RXDSR6.Bits.DB2\r
+#define CAN2RXDSR6_DB3 _CAN2RXDSR6.Bits.DB3\r
+#define CAN2RXDSR6_DB4 _CAN2RXDSR6.Bits.DB4\r
+#define CAN2RXDSR6_DB5 _CAN2RXDSR6.Bits.DB5\r
+#define CAN2RXDSR6_DB6 _CAN2RXDSR6.Bits.DB6\r
+#define CAN2RXDSR6_DB7 _CAN2RXDSR6.Bits.DB7\r
+#define CAN2RXDSR6_DB _CAN2RXDSR6.MergedBits.grpDB\r
+\r
+\r
+/*** CAN2RXDSR7 - MSCAN 2 Receive Data Segment Register 7; 0x000001EB ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN2RXDSR7STR;\r
+extern volatile CAN2RXDSR7STR _CAN2RXDSR7 @(REG_BASE + 0x000001EB);\r
+#define CAN2RXDSR7 _CAN2RXDSR7.Byte\r
+#define CAN2RXDSR7_DB0 _CAN2RXDSR7.Bits.DB0\r
+#define CAN2RXDSR7_DB1 _CAN2RXDSR7.Bits.DB1\r
+#define CAN2RXDSR7_DB2 _CAN2RXDSR7.Bits.DB2\r
+#define CAN2RXDSR7_DB3 _CAN2RXDSR7.Bits.DB3\r
+#define CAN2RXDSR7_DB4 _CAN2RXDSR7.Bits.DB4\r
+#define CAN2RXDSR7_DB5 _CAN2RXDSR7.Bits.DB5\r
+#define CAN2RXDSR7_DB6 _CAN2RXDSR7.Bits.DB6\r
+#define CAN2RXDSR7_DB7 _CAN2RXDSR7.Bits.DB7\r
+#define CAN2RXDSR7_DB _CAN2RXDSR7.MergedBits.grpDB\r
+\r
+\r
+/*** CAN2RXDLR - MSCAN 2 Receive Data Length Register; 0x000001EC ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DLC0 :1; /* Data Length Code Bit 0 */\r
+ byte DLC1 :1; /* Data Length Code Bit 1 */\r
+ byte DLC2 :1; /* Data Length Code Bit 2 */\r
+ byte DLC3 :1; /* Data Length Code Bit 3 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpDLC :4;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CAN2RXDLRSTR;\r
+extern volatile CAN2RXDLRSTR _CAN2RXDLR @(REG_BASE + 0x000001EC);\r
+#define CAN2RXDLR _CAN2RXDLR.Byte\r
+#define CAN2RXDLR_DLC0 _CAN2RXDLR.Bits.DLC0\r
+#define CAN2RXDLR_DLC1 _CAN2RXDLR.Bits.DLC1\r
+#define CAN2RXDLR_DLC2 _CAN2RXDLR.Bits.DLC2\r
+#define CAN2RXDLR_DLC3 _CAN2RXDLR.Bits.DLC3\r
+#define CAN2RXDLR_DLC _CAN2RXDLR.MergedBits.grpDLC\r
+\r
+\r
+/*** CAN2TXIDR0 - MSCAN 2 Transmit Identifier Register 0; 0x000001F0 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ID21 :1; /* Extended format identifier Bit 21 */\r
+ byte ID22 :1; /* Extended format identifier Bit 22 */\r
+ byte ID23 :1; /* Extended format identifier Bit 23 */\r
+ byte ID24 :1; /* Extended format identifier Bit 24 */\r
+ byte ID25 :1; /* Extended format identifier Bit 25 */\r
+ byte ID26 :1; /* Extended format identifier Bit 26 */\r
+ byte ID27 :1; /* Extended format identifier Bit 27 */\r
+ byte ID28 :1; /* Extended format identifier Bit 28 */\r
+ } Bits;\r
+ struct {\r
+ byte grpID_21 :8;\r
+ } MergedBits;\r
+} CAN2TXIDR0STR;\r
+extern volatile CAN2TXIDR0STR _CAN2TXIDR0 @(REG_BASE + 0x000001F0);\r
+#define CAN2TXIDR0 _CAN2TXIDR0.Byte\r
+#define CAN2TXIDR0_ID21 _CAN2TXIDR0.Bits.ID21\r
+#define CAN2TXIDR0_ID22 _CAN2TXIDR0.Bits.ID22\r
+#define CAN2TXIDR0_ID23 _CAN2TXIDR0.Bits.ID23\r
+#define CAN2TXIDR0_ID24 _CAN2TXIDR0.Bits.ID24\r
+#define CAN2TXIDR0_ID25 _CAN2TXIDR0.Bits.ID25\r
+#define CAN2TXIDR0_ID26 _CAN2TXIDR0.Bits.ID26\r
+#define CAN2TXIDR0_ID27 _CAN2TXIDR0.Bits.ID27\r
+#define CAN2TXIDR0_ID28 _CAN2TXIDR0.Bits.ID28\r
+#define CAN2TXIDR0_ID_21 _CAN2TXIDR0.MergedBits.grpID_21\r
+#define CAN2TXIDR0_ID CAN2TXIDR0_ID_21\r
+\r
+\r
+/*** CAN2TXIDR1 - MSCAN 2 Transmit Identifier Register 1; 0x000001F1 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ID15 :1; /* Extended format identifier Bit 15 */\r
+ byte ID16 :1; /* Extended format identifier Bit 16 */\r
+ byte ID17 :1; /* Extended format identifier Bit 17 */\r
+ byte IDE :1; /* ID Extended */\r
+ byte SRR :1; /* Substitute Remote Request */\r
+ byte ID18 :1; /* Extended format identifier Bit 18 */\r
+ byte ID19 :1; /* Extended format identifier Bit 19 */\r
+ byte ID20 :1; /* Extended format identifier Bit 20 */\r
+ } Bits;\r
+ struct {\r
+ byte grpID_15 :3;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpID_18 :3;\r
+ } MergedBits;\r
+} CAN2TXIDR1STR;\r
+extern volatile CAN2TXIDR1STR _CAN2TXIDR1 @(REG_BASE + 0x000001F1);\r
+#define CAN2TXIDR1 _CAN2TXIDR1.Byte\r
+#define CAN2TXIDR1_ID15 _CAN2TXIDR1.Bits.ID15\r
+#define CAN2TXIDR1_ID16 _CAN2TXIDR1.Bits.ID16\r
+#define CAN2TXIDR1_ID17 _CAN2TXIDR1.Bits.ID17\r
+#define CAN2TXIDR1_IDE _CAN2TXIDR1.Bits.IDE\r
+#define CAN2TXIDR1_SRR _CAN2TXIDR1.Bits.SRR\r
+#define CAN2TXIDR1_ID18 _CAN2TXIDR1.Bits.ID18\r
+#define CAN2TXIDR1_ID19 _CAN2TXIDR1.Bits.ID19\r
+#define CAN2TXIDR1_ID20 _CAN2TXIDR1.Bits.ID20\r
+#define CAN2TXIDR1_ID_15 _CAN2TXIDR1.MergedBits.grpID_15\r
+#define CAN2TXIDR1_ID_18 _CAN2TXIDR1.MergedBits.grpID_18\r
+#define CAN2TXIDR1_ID CAN2TXIDR1_ID_15\r
+\r
+\r
+/*** CAN2TXIDR2 - MSCAN 2 Transmit Identifier Register 2; 0x000001F2 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ID7 :1; /* Extended format identifier Bit 7 */\r
+ byte ID8 :1; /* Extended format identifier Bit 8 */\r
+ byte ID9 :1; /* Extended format identifier Bit 9 */\r
+ byte ID10 :1; /* Extended format identifier Bit 10 */\r
+ byte ID11 :1; /* Extended format identifier Bit 11 */\r
+ byte ID12 :1; /* Extended format identifier Bit 12 */\r
+ byte ID13 :1; /* Extended format identifier Bit 13 */\r
+ byte ID14 :1; /* Extended format identifier Bit 14 */\r
+ } Bits;\r
+ struct {\r
+ byte grpID_7 :8;\r
+ } MergedBits;\r
+} CAN2TXIDR2STR;\r
+extern volatile CAN2TXIDR2STR _CAN2TXIDR2 @(REG_BASE + 0x000001F2);\r
+#define CAN2TXIDR2 _CAN2TXIDR2.Byte\r
+#define CAN2TXIDR2_ID7 _CAN2TXIDR2.Bits.ID7\r
+#define CAN2TXIDR2_ID8 _CAN2TXIDR2.Bits.ID8\r
+#define CAN2TXIDR2_ID9 _CAN2TXIDR2.Bits.ID9\r
+#define CAN2TXIDR2_ID10 _CAN2TXIDR2.Bits.ID10\r
+#define CAN2TXIDR2_ID11 _CAN2TXIDR2.Bits.ID11\r
+#define CAN2TXIDR2_ID12 _CAN2TXIDR2.Bits.ID12\r
+#define CAN2TXIDR2_ID13 _CAN2TXIDR2.Bits.ID13\r
+#define CAN2TXIDR2_ID14 _CAN2TXIDR2.Bits.ID14\r
+#define CAN2TXIDR2_ID_7 _CAN2TXIDR2.MergedBits.grpID_7\r
+#define CAN2TXIDR2_ID CAN2TXIDR2_ID_7\r
+\r
+\r
+/*** CAN2TXIDR3 - MSCAN 2 Transmit Identifier Register 3; 0x000001F3 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte RTR :1; /* Remote Transmission Request */\r
+ byte ID0 :1; /* Extended format identifier Bit 0 */\r
+ byte ID1 :1; /* Extended format identifier Bit 1 */\r
+ byte ID2 :1; /* Extended format identifier Bit 2 */\r
+ byte ID3 :1; /* Extended format identifier Bit 3 */\r
+ byte ID4 :1; /* Extended format identifier Bit 4 */\r
+ byte ID5 :1; /* Extended format identifier Bit 5 */\r
+ byte ID6 :1; /* Extended format identifier Bit 6 */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte grpID :7;\r
+ } MergedBits;\r
+} CAN2TXIDR3STR;\r
+extern volatile CAN2TXIDR3STR _CAN2TXIDR3 @(REG_BASE + 0x000001F3);\r
+#define CAN2TXIDR3 _CAN2TXIDR3.Byte\r
+#define CAN2TXIDR3_RTR _CAN2TXIDR3.Bits.RTR\r
+#define CAN2TXIDR3_ID0 _CAN2TXIDR3.Bits.ID0\r
+#define CAN2TXIDR3_ID1 _CAN2TXIDR3.Bits.ID1\r
+#define CAN2TXIDR3_ID2 _CAN2TXIDR3.Bits.ID2\r
+#define CAN2TXIDR3_ID3 _CAN2TXIDR3.Bits.ID3\r
+#define CAN2TXIDR3_ID4 _CAN2TXIDR3.Bits.ID4\r
+#define CAN2TXIDR3_ID5 _CAN2TXIDR3.Bits.ID5\r
+#define CAN2TXIDR3_ID6 _CAN2TXIDR3.Bits.ID6\r
+#define CAN2TXIDR3_ID _CAN2TXIDR3.MergedBits.grpID\r
+\r
+\r
+/*** CAN2TXDSR0 - MSCAN 2 Transmit Data Segment Register 0; 0x000001F4 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN2TXDSR0STR;\r
+extern volatile CAN2TXDSR0STR _CAN2TXDSR0 @(REG_BASE + 0x000001F4);\r
+#define CAN2TXDSR0 _CAN2TXDSR0.Byte\r
+#define CAN2TXDSR0_DB0 _CAN2TXDSR0.Bits.DB0\r
+#define CAN2TXDSR0_DB1 _CAN2TXDSR0.Bits.DB1\r
+#define CAN2TXDSR0_DB2 _CAN2TXDSR0.Bits.DB2\r
+#define CAN2TXDSR0_DB3 _CAN2TXDSR0.Bits.DB3\r
+#define CAN2TXDSR0_DB4 _CAN2TXDSR0.Bits.DB4\r
+#define CAN2TXDSR0_DB5 _CAN2TXDSR0.Bits.DB5\r
+#define CAN2TXDSR0_DB6 _CAN2TXDSR0.Bits.DB6\r
+#define CAN2TXDSR0_DB7 _CAN2TXDSR0.Bits.DB7\r
+#define CAN2TXDSR0_DB _CAN2TXDSR0.MergedBits.grpDB\r
+\r
+\r
+/*** CAN2TXDSR1 - MSCAN 2 Transmit Data Segment Register 1; 0x000001F5 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN2TXDSR1STR;\r
+extern volatile CAN2TXDSR1STR _CAN2TXDSR1 @(REG_BASE + 0x000001F5);\r
+#define CAN2TXDSR1 _CAN2TXDSR1.Byte\r
+#define CAN2TXDSR1_DB0 _CAN2TXDSR1.Bits.DB0\r
+#define CAN2TXDSR1_DB1 _CAN2TXDSR1.Bits.DB1\r
+#define CAN2TXDSR1_DB2 _CAN2TXDSR1.Bits.DB2\r
+#define CAN2TXDSR1_DB3 _CAN2TXDSR1.Bits.DB3\r
+#define CAN2TXDSR1_DB4 _CAN2TXDSR1.Bits.DB4\r
+#define CAN2TXDSR1_DB5 _CAN2TXDSR1.Bits.DB5\r
+#define CAN2TXDSR1_DB6 _CAN2TXDSR1.Bits.DB6\r
+#define CAN2TXDSR1_DB7 _CAN2TXDSR1.Bits.DB7\r
+#define CAN2TXDSR1_DB _CAN2TXDSR1.MergedBits.grpDB\r
+\r
+\r
+/*** CAN2TXDSR2 - MSCAN 2 Transmit Data Segment Register 2; 0x000001F6 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN2TXDSR2STR;\r
+extern volatile CAN2TXDSR2STR _CAN2TXDSR2 @(REG_BASE + 0x000001F6);\r
+#define CAN2TXDSR2 _CAN2TXDSR2.Byte\r
+#define CAN2TXDSR2_DB0 _CAN2TXDSR2.Bits.DB0\r
+#define CAN2TXDSR2_DB1 _CAN2TXDSR2.Bits.DB1\r
+#define CAN2TXDSR2_DB2 _CAN2TXDSR2.Bits.DB2\r
+#define CAN2TXDSR2_DB3 _CAN2TXDSR2.Bits.DB3\r
+#define CAN2TXDSR2_DB4 _CAN2TXDSR2.Bits.DB4\r
+#define CAN2TXDSR2_DB5 _CAN2TXDSR2.Bits.DB5\r
+#define CAN2TXDSR2_DB6 _CAN2TXDSR2.Bits.DB6\r
+#define CAN2TXDSR2_DB7 _CAN2TXDSR2.Bits.DB7\r
+#define CAN2TXDSR2_DB _CAN2TXDSR2.MergedBits.grpDB\r
+\r
+\r
+/*** CAN2TXDSR3 - MSCAN 2 Transmit Data Segment Register 3; 0x000001F7 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN2TXDSR3STR;\r
+extern volatile CAN2TXDSR3STR _CAN2TXDSR3 @(REG_BASE + 0x000001F7);\r
+#define CAN2TXDSR3 _CAN2TXDSR3.Byte\r
+#define CAN2TXDSR3_DB0 _CAN2TXDSR3.Bits.DB0\r
+#define CAN2TXDSR3_DB1 _CAN2TXDSR3.Bits.DB1\r
+#define CAN2TXDSR3_DB2 _CAN2TXDSR3.Bits.DB2\r
+#define CAN2TXDSR3_DB3 _CAN2TXDSR3.Bits.DB3\r
+#define CAN2TXDSR3_DB4 _CAN2TXDSR3.Bits.DB4\r
+#define CAN2TXDSR3_DB5 _CAN2TXDSR3.Bits.DB5\r
+#define CAN2TXDSR3_DB6 _CAN2TXDSR3.Bits.DB6\r
+#define CAN2TXDSR3_DB7 _CAN2TXDSR3.Bits.DB7\r
+#define CAN2TXDSR3_DB _CAN2TXDSR3.MergedBits.grpDB\r
+\r
+\r
+/*** CAN2TXDSR4 - MSCAN 2 Transmit Data Segment Register 4; 0x000001F8 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN2TXDSR4STR;\r
+extern volatile CAN2TXDSR4STR _CAN2TXDSR4 @(REG_BASE + 0x000001F8);\r
+#define CAN2TXDSR4 _CAN2TXDSR4.Byte\r
+#define CAN2TXDSR4_DB0 _CAN2TXDSR4.Bits.DB0\r
+#define CAN2TXDSR4_DB1 _CAN2TXDSR4.Bits.DB1\r
+#define CAN2TXDSR4_DB2 _CAN2TXDSR4.Bits.DB2\r
+#define CAN2TXDSR4_DB3 _CAN2TXDSR4.Bits.DB3\r
+#define CAN2TXDSR4_DB4 _CAN2TXDSR4.Bits.DB4\r
+#define CAN2TXDSR4_DB5 _CAN2TXDSR4.Bits.DB5\r
+#define CAN2TXDSR4_DB6 _CAN2TXDSR4.Bits.DB6\r
+#define CAN2TXDSR4_DB7 _CAN2TXDSR4.Bits.DB7\r
+#define CAN2TXDSR4_DB _CAN2TXDSR4.MergedBits.grpDB\r
+\r
+\r
+/*** CAN2TXDSR5 - MSCAN 2 Transmit Data Segment Register 5; 0x000001F9 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN2TXDSR5STR;\r
+extern volatile CAN2TXDSR5STR _CAN2TXDSR5 @(REG_BASE + 0x000001F9);\r
+#define CAN2TXDSR5 _CAN2TXDSR5.Byte\r
+#define CAN2TXDSR5_DB0 _CAN2TXDSR5.Bits.DB0\r
+#define CAN2TXDSR5_DB1 _CAN2TXDSR5.Bits.DB1\r
+#define CAN2TXDSR5_DB2 _CAN2TXDSR5.Bits.DB2\r
+#define CAN2TXDSR5_DB3 _CAN2TXDSR5.Bits.DB3\r
+#define CAN2TXDSR5_DB4 _CAN2TXDSR5.Bits.DB4\r
+#define CAN2TXDSR5_DB5 _CAN2TXDSR5.Bits.DB5\r
+#define CAN2TXDSR5_DB6 _CAN2TXDSR5.Bits.DB6\r
+#define CAN2TXDSR5_DB7 _CAN2TXDSR5.Bits.DB7\r
+#define CAN2TXDSR5_DB _CAN2TXDSR5.MergedBits.grpDB\r
+\r
+\r
+/*** CAN2TXDSR6 - MSCAN 2 Transmit Data Segment Register 6; 0x000001FA ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN2TXDSR6STR;\r
+extern volatile CAN2TXDSR6STR _CAN2TXDSR6 @(REG_BASE + 0x000001FA);\r
+#define CAN2TXDSR6 _CAN2TXDSR6.Byte\r
+#define CAN2TXDSR6_DB0 _CAN2TXDSR6.Bits.DB0\r
+#define CAN2TXDSR6_DB1 _CAN2TXDSR6.Bits.DB1\r
+#define CAN2TXDSR6_DB2 _CAN2TXDSR6.Bits.DB2\r
+#define CAN2TXDSR6_DB3 _CAN2TXDSR6.Bits.DB3\r
+#define CAN2TXDSR6_DB4 _CAN2TXDSR6.Bits.DB4\r
+#define CAN2TXDSR6_DB5 _CAN2TXDSR6.Bits.DB5\r
+#define CAN2TXDSR6_DB6 _CAN2TXDSR6.Bits.DB6\r
+#define CAN2TXDSR6_DB7 _CAN2TXDSR6.Bits.DB7\r
+#define CAN2TXDSR6_DB _CAN2TXDSR6.MergedBits.grpDB\r
+\r
+\r
+/*** CAN2TXDSR7 - MSCAN 2 Transmit Data Segment Register 7; 0x000001FB ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN2TXDSR7STR;\r
+extern volatile CAN2TXDSR7STR _CAN2TXDSR7 @(REG_BASE + 0x000001FB);\r
+#define CAN2TXDSR7 _CAN2TXDSR7.Byte\r
+#define CAN2TXDSR7_DB0 _CAN2TXDSR7.Bits.DB0\r
+#define CAN2TXDSR7_DB1 _CAN2TXDSR7.Bits.DB1\r
+#define CAN2TXDSR7_DB2 _CAN2TXDSR7.Bits.DB2\r
+#define CAN2TXDSR7_DB3 _CAN2TXDSR7.Bits.DB3\r
+#define CAN2TXDSR7_DB4 _CAN2TXDSR7.Bits.DB4\r
+#define CAN2TXDSR7_DB5 _CAN2TXDSR7.Bits.DB5\r
+#define CAN2TXDSR7_DB6 _CAN2TXDSR7.Bits.DB6\r
+#define CAN2TXDSR7_DB7 _CAN2TXDSR7.Bits.DB7\r
+#define CAN2TXDSR7_DB _CAN2TXDSR7.MergedBits.grpDB\r
+\r
+\r
+/*** CAN2TXDLR - MSCAN 2 Transmit Data Length Register; 0x000001FC ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DLC0 :1; /* Data Length Code Bit 0 */\r
+ byte DLC1 :1; /* Data Length Code Bit 1 */\r
+ byte DLC2 :1; /* Data Length Code Bit 2 */\r
+ byte DLC3 :1; /* Data Length Code Bit 3 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpDLC :4;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CAN2TXDLRSTR;\r
+extern volatile CAN2TXDLRSTR _CAN2TXDLR @(REG_BASE + 0x000001FC);\r
+#define CAN2TXDLR _CAN2TXDLR.Byte\r
+#define CAN2TXDLR_DLC0 _CAN2TXDLR.Bits.DLC0\r
+#define CAN2TXDLR_DLC1 _CAN2TXDLR.Bits.DLC1\r
+#define CAN2TXDLR_DLC2 _CAN2TXDLR.Bits.DLC2\r
+#define CAN2TXDLR_DLC3 _CAN2TXDLR.Bits.DLC3\r
+#define CAN2TXDLR_DLC _CAN2TXDLR.MergedBits.grpDLC\r
+\r
+\r
+/*** CAN2TXTBPR - MSCAN 2 Transmit Buffer Priority; 0x000001FF ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PRIO0 :1; /* Transmit Buffer Priority Bit 0 */\r
+ byte PRIO1 :1; /* Transmit Buffer Priority Bit 1 */\r
+ byte PRIO2 :1; /* Transmit Buffer Priority Bit 2 */\r
+ byte PRIO3 :1; /* Transmit Buffer Priority Bit 3 */\r
+ byte PRIO4 :1; /* Transmit Buffer Priority Bit 4 */\r
+ byte PRIO5 :1; /* Transmit Buffer Priority Bit 5 */\r
+ byte PRIO6 :1; /* Transmit Buffer Priority Bit 6 */\r
+ byte PRIO7 :1; /* Transmit Buffer Priority Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpPRIO :8;\r
+ } MergedBits;\r
+} CAN2TXTBPRSTR;\r
+extern volatile CAN2TXTBPRSTR _CAN2TXTBPR @(REG_BASE + 0x000001FF);\r
+#define CAN2TXTBPR _CAN2TXTBPR.Byte\r
+#define CAN2TXTBPR_PRIO0 _CAN2TXTBPR.Bits.PRIO0\r
+#define CAN2TXTBPR_PRIO1 _CAN2TXTBPR.Bits.PRIO1\r
+#define CAN2TXTBPR_PRIO2 _CAN2TXTBPR.Bits.PRIO2\r
+#define CAN2TXTBPR_PRIO3 _CAN2TXTBPR.Bits.PRIO3\r
+#define CAN2TXTBPR_PRIO4 _CAN2TXTBPR.Bits.PRIO4\r
+#define CAN2TXTBPR_PRIO5 _CAN2TXTBPR.Bits.PRIO5\r
+#define CAN2TXTBPR_PRIO6 _CAN2TXTBPR.Bits.PRIO6\r
+#define CAN2TXTBPR_PRIO7 _CAN2TXTBPR.Bits.PRIO7\r
+#define CAN2TXTBPR_PRIO _CAN2TXTBPR.MergedBits.grpPRIO\r
+\r
+\r
+/*** CAN3CTL0 - MSCAN 3 Control 0 Register; 0x00000200 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte INITRQ :1; /* Initialization Mode Request */\r
+ byte SLPRQ :1; /* Sleep Mode Request */\r
+ byte WUPE :1; /* Wake-Up Enable */\r
+ byte TIME :1; /* Timer Enable */\r
+ byte SYNCH :1; /* Synchronized Status */\r
+ byte CSWAI :1; /* CAN Stops in Wait Mode */\r
+ byte RXACT :1; /* Receiver Active Status */\r
+ byte RXFRM :1; /* Received Frame Flag */\r
+ } Bits;\r
+} CAN3CTL0STR;\r
+extern volatile CAN3CTL0STR _CAN3CTL0 @(REG_BASE + 0x00000200);\r
+#define CAN3CTL0 _CAN3CTL0.Byte\r
+#define CAN3CTL0_INITRQ _CAN3CTL0.Bits.INITRQ\r
+#define CAN3CTL0_SLPRQ _CAN3CTL0.Bits.SLPRQ\r
+#define CAN3CTL0_WUPE _CAN3CTL0.Bits.WUPE\r
+#define CAN3CTL0_TIME _CAN3CTL0.Bits.TIME\r
+#define CAN3CTL0_SYNCH _CAN3CTL0.Bits.SYNCH\r
+#define CAN3CTL0_CSWAI _CAN3CTL0.Bits.CSWAI\r
+#define CAN3CTL0_RXACT _CAN3CTL0.Bits.RXACT\r
+#define CAN3CTL0_RXFRM _CAN3CTL0.Bits.RXFRM\r
+\r
+\r
+/*** CAN3CTL1 - MSCAN 3 Control 1 Register; 0x00000201 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte INITAK :1; /* Initialization Mode Acknowledge */\r
+ byte SLPAK :1; /* Sleep Mode Acknowledge */\r
+ byte WUPM :1; /* Wake-Up Mode */\r
+ byte :1; \r
+ byte LISTEN :1; /* Listen Only Mode */\r
+ byte LOOPB :1; /* Loop Back Self Test Mode */\r
+ byte CLKSRC :1; /* MSCAN 3 Clock Source */\r
+ byte CANE :1; /* MSCAN 3 Enable */\r
+ } Bits;\r
+} CAN3CTL1STR;\r
+extern volatile CAN3CTL1STR _CAN3CTL1 @(REG_BASE + 0x00000201);\r
+#define CAN3CTL1 _CAN3CTL1.Byte\r
+#define CAN3CTL1_INITAK _CAN3CTL1.Bits.INITAK\r
+#define CAN3CTL1_SLPAK _CAN3CTL1.Bits.SLPAK\r
+#define CAN3CTL1_WUPM _CAN3CTL1.Bits.WUPM\r
+#define CAN3CTL1_LISTEN _CAN3CTL1.Bits.LISTEN\r
+#define CAN3CTL1_LOOPB _CAN3CTL1.Bits.LOOPB\r
+#define CAN3CTL1_CLKSRC _CAN3CTL1.Bits.CLKSRC\r
+#define CAN3CTL1_CANE _CAN3CTL1.Bits.CANE\r
+\r
+\r
+/*** CAN3BTR0 - MSCAN 3 Bus Timing Register 0; 0x00000202 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte BRP0 :1; /* Baud Rate Prescaler 0 */\r
+ byte BRP1 :1; /* Baud Rate Prescaler 1 */\r
+ byte BRP2 :1; /* Baud Rate Prescaler 2 */\r
+ byte BRP3 :1; /* Baud Rate Prescaler 3 */\r
+ byte BRP4 :1; /* Baud Rate Prescaler 4 */\r
+ byte BRP5 :1; /* Baud Rate Prescaler 5 */\r
+ byte SJW0 :1; /* Synchronization Jump Width 0 */\r
+ byte SJW1 :1; /* Synchronization Jump Width 1 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBRP :6;\r
+ byte grpSJW :2;\r
+ } MergedBits;\r
+} CAN3BTR0STR;\r
+extern volatile CAN3BTR0STR _CAN3BTR0 @(REG_BASE + 0x00000202);\r
+#define CAN3BTR0 _CAN3BTR0.Byte\r
+#define CAN3BTR0_BRP0 _CAN3BTR0.Bits.BRP0\r
+#define CAN3BTR0_BRP1 _CAN3BTR0.Bits.BRP1\r
+#define CAN3BTR0_BRP2 _CAN3BTR0.Bits.BRP2\r
+#define CAN3BTR0_BRP3 _CAN3BTR0.Bits.BRP3\r
+#define CAN3BTR0_BRP4 _CAN3BTR0.Bits.BRP4\r
+#define CAN3BTR0_BRP5 _CAN3BTR0.Bits.BRP5\r
+#define CAN3BTR0_SJW0 _CAN3BTR0.Bits.SJW0\r
+#define CAN3BTR0_SJW1 _CAN3BTR0.Bits.SJW1\r
+#define CAN3BTR0_BRP _CAN3BTR0.MergedBits.grpBRP\r
+#define CAN3BTR0_SJW _CAN3BTR0.MergedBits.grpSJW\r
+\r
+\r
+/*** CAN3BTR1 - MSCAN 3 Bus Timing Register 1; 0x00000203 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte TSEG10 :1; /* Time Segment 1 */\r
+ byte TSEG11 :1; /* Time Segment 1 */\r
+ byte TSEG12 :1; /* Time Segment 1 */\r
+ byte TSEG13 :1; /* Time Segment 1 */\r
+ byte TSEG20 :1; /* Time Segment 2 */\r
+ byte TSEG21 :1; /* Time Segment 2 */\r
+ byte TSEG22 :1; /* Time Segment 2 */\r
+ byte SAMP :1; /* Sampling */\r
+ } Bits;\r
+ struct {\r
+ byte grpTSEG_10 :4;\r
+ byte grpTSEG_20 :3;\r
+ byte :1;\r
+ } MergedBits;\r
+} CAN3BTR1STR;\r
+extern volatile CAN3BTR1STR _CAN3BTR1 @(REG_BASE + 0x00000203);\r
+#define CAN3BTR1 _CAN3BTR1.Byte\r
+#define CAN3BTR1_TSEG10 _CAN3BTR1.Bits.TSEG10\r
+#define CAN3BTR1_TSEG11 _CAN3BTR1.Bits.TSEG11\r
+#define CAN3BTR1_TSEG12 _CAN3BTR1.Bits.TSEG12\r
+#define CAN3BTR1_TSEG13 _CAN3BTR1.Bits.TSEG13\r
+#define CAN3BTR1_TSEG20 _CAN3BTR1.Bits.TSEG20\r
+#define CAN3BTR1_TSEG21 _CAN3BTR1.Bits.TSEG21\r
+#define CAN3BTR1_TSEG22 _CAN3BTR1.Bits.TSEG22\r
+#define CAN3BTR1_SAMP _CAN3BTR1.Bits.SAMP\r
+#define CAN3BTR1_TSEG_10 _CAN3BTR1.MergedBits.grpTSEG_10\r
+#define CAN3BTR1_TSEG_20 _CAN3BTR1.MergedBits.grpTSEG_20\r
+#define CAN3BTR1_TSEG CAN3BTR1_TSEG_10\r
+\r
+\r
+/*** CAN3RFLG - MSCAN 3 Receiver Flag Register; 0x00000204 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte RXF :1; /* Receive Buffer Full */\r
+ byte OVRIF :1; /* Overrun Interrupt Flag */\r
+ byte TSTAT0 :1; /* Transmitter Status Bit 0 */\r
+ byte TSTAT1 :1; /* Transmitter Status Bit 1 */\r
+ byte RSTAT0 :1; /* Receiver Status Bit 0 */\r
+ byte RSTAT1 :1; /* Receiver Status Bit 1 */\r
+ byte CSCIF :1; /* CAN Status Change Interrupt Flag */\r
+ byte WUPIF :1; /* Wake-up Interrupt Flag */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte grpTSTAT :2;\r
+ byte grpRSTAT :2;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CAN3RFLGSTR;\r
+extern volatile CAN3RFLGSTR _CAN3RFLG @(REG_BASE + 0x00000204);\r
+#define CAN3RFLG _CAN3RFLG.Byte\r
+#define CAN3RFLG_RXF _CAN3RFLG.Bits.RXF\r
+#define CAN3RFLG_OVRIF _CAN3RFLG.Bits.OVRIF\r
+#define CAN3RFLG_TSTAT0 _CAN3RFLG.Bits.TSTAT0\r
+#define CAN3RFLG_TSTAT1 _CAN3RFLG.Bits.TSTAT1\r
+#define CAN3RFLG_RSTAT0 _CAN3RFLG.Bits.RSTAT0\r
+#define CAN3RFLG_RSTAT1 _CAN3RFLG.Bits.RSTAT1\r
+#define CAN3RFLG_CSCIF _CAN3RFLG.Bits.CSCIF\r
+#define CAN3RFLG_WUPIF _CAN3RFLG.Bits.WUPIF\r
+#define CAN3RFLG_TSTAT _CAN3RFLG.MergedBits.grpTSTAT\r
+#define CAN3RFLG_RSTAT _CAN3RFLG.MergedBits.grpRSTAT\r
+\r
+\r
+/*** CAN3RIER - MSCAN 3 Receiver Interrupt Enable Register; 0x00000205 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte RXFIE :1; /* Receiver Full Interrupt Enable */\r
+ byte OVRIE :1; /* Overrun Interrupt Enable */\r
+ byte TSTATE0 :1; /* Transmitter Status Change Enable 0 */\r
+ byte TSTATE1 :1; /* Transmitter Status Change Enable 1 */\r
+ byte RSTATE0 :1; /* Receiver Status Change Enable 0 */\r
+ byte RSTATE1 :1; /* Receiver Status Change Enable 1 */\r
+ byte CSCIE :1; /* CAN Status Change Interrupt Enable */\r
+ byte WUPIE :1; /* Wake-up Interrupt Enable */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte grpTSTATE :2;\r
+ byte grpRSTATE :2;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CAN3RIERSTR;\r
+extern volatile CAN3RIERSTR _CAN3RIER @(REG_BASE + 0x00000205);\r
+#define CAN3RIER _CAN3RIER.Byte\r
+#define CAN3RIER_RXFIE _CAN3RIER.Bits.RXFIE\r
+#define CAN3RIER_OVRIE _CAN3RIER.Bits.OVRIE\r
+#define CAN3RIER_TSTATE0 _CAN3RIER.Bits.TSTATE0\r
+#define CAN3RIER_TSTATE1 _CAN3RIER.Bits.TSTATE1\r
+#define CAN3RIER_RSTATE0 _CAN3RIER.Bits.RSTATE0\r
+#define CAN3RIER_RSTATE1 _CAN3RIER.Bits.RSTATE1\r
+#define CAN3RIER_CSCIE _CAN3RIER.Bits.CSCIE\r
+#define CAN3RIER_WUPIE _CAN3RIER.Bits.WUPIE\r
+#define CAN3RIER_TSTATE _CAN3RIER.MergedBits.grpTSTATE\r
+#define CAN3RIER_RSTATE _CAN3RIER.MergedBits.grpRSTATE\r
+\r
+\r
+/*** CAN3TFLG - MSCAN 3 Transmitter Flag Register; 0x00000206 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte TXE0 :1; /* Transmitter Buffer Empty 0 */\r
+ byte TXE1 :1; /* Transmitter Buffer Empty 1 */\r
+ byte TXE2 :1; /* Transmitter Buffer Empty 2 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpTXE :3;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CAN3TFLGSTR;\r
+extern volatile CAN3TFLGSTR _CAN3TFLG @(REG_BASE + 0x00000206);\r
+#define CAN3TFLG _CAN3TFLG.Byte\r
+#define CAN3TFLG_TXE0 _CAN3TFLG.Bits.TXE0\r
+#define CAN3TFLG_TXE1 _CAN3TFLG.Bits.TXE1\r
+#define CAN3TFLG_TXE2 _CAN3TFLG.Bits.TXE2\r
+#define CAN3TFLG_TXE _CAN3TFLG.MergedBits.grpTXE\r
+\r
+\r
+/*** CAN3TIER - MSCAN 3 Transmitter Interrupt Enable Register; 0x00000207 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte TXEIE0 :1; /* Transmitter Empty Interrupt Enable 0 */\r
+ byte TXEIE1 :1; /* Transmitter Empty Interrupt Enable 1 */\r
+ byte TXEIE2 :1; /* Transmitter Empty Interrupt Enable 2 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpTXEIE :3;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CAN3TIERSTR;\r
+extern volatile CAN3TIERSTR _CAN3TIER @(REG_BASE + 0x00000207);\r
+#define CAN3TIER _CAN3TIER.Byte\r
+#define CAN3TIER_TXEIE0 _CAN3TIER.Bits.TXEIE0\r
+#define CAN3TIER_TXEIE1 _CAN3TIER.Bits.TXEIE1\r
+#define CAN3TIER_TXEIE2 _CAN3TIER.Bits.TXEIE2\r
+#define CAN3TIER_TXEIE _CAN3TIER.MergedBits.grpTXEIE\r
+\r
+\r
+/*** CAN3TARQ - MSCAN 3 Transmitter Message Abort Request; 0x00000208 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ABTRQ0 :1; /* Abort Request 0 */\r
+ byte ABTRQ1 :1; /* Abort Request 1 */\r
+ byte ABTRQ2 :1; /* Abort Request 2 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpABTRQ :3;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CAN3TARQSTR;\r
+extern volatile CAN3TARQSTR _CAN3TARQ @(REG_BASE + 0x00000208);\r
+#define CAN3TARQ _CAN3TARQ.Byte\r
+#define CAN3TARQ_ABTRQ0 _CAN3TARQ.Bits.ABTRQ0\r
+#define CAN3TARQ_ABTRQ1 _CAN3TARQ.Bits.ABTRQ1\r
+#define CAN3TARQ_ABTRQ2 _CAN3TARQ.Bits.ABTRQ2\r
+#define CAN3TARQ_ABTRQ _CAN3TARQ.MergedBits.grpABTRQ\r
+\r
+\r
+/*** CAN3TAAK - MSCAN 3 Transmitter Message Abort Control; 0x00000209 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ABTAK0 :1; /* Abort Acknowledge 0 */\r
+ byte ABTAK1 :1; /* Abort Acknowledge 1 */\r
+ byte ABTAK2 :1; /* Abort Acknowledge 2 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpABTAK :3;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CAN3TAAKSTR;\r
+extern volatile CAN3TAAKSTR _CAN3TAAK @(REG_BASE + 0x00000209);\r
+#define CAN3TAAK _CAN3TAAK.Byte\r
+#define CAN3TAAK_ABTAK0 _CAN3TAAK.Bits.ABTAK0\r
+#define CAN3TAAK_ABTAK1 _CAN3TAAK.Bits.ABTAK1\r
+#define CAN3TAAK_ABTAK2 _CAN3TAAK.Bits.ABTAK2\r
+#define CAN3TAAK_ABTAK _CAN3TAAK.MergedBits.grpABTAK\r
+\r
+\r
+/*** CAN3TBSEL - MSCAN 3 Transmit Buffer Selection; 0x0000020A ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte TX0 :1; /* Transmit Buffer Select 0 */\r
+ byte TX1 :1; /* Transmit Buffer Select 1 */\r
+ byte TX2 :1; /* Transmit Buffer Select 2 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpTX :3;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CAN3TBSELSTR;\r
+extern volatile CAN3TBSELSTR _CAN3TBSEL @(REG_BASE + 0x0000020A);\r
+#define CAN3TBSEL _CAN3TBSEL.Byte\r
+#define CAN3TBSEL_TX0 _CAN3TBSEL.Bits.TX0\r
+#define CAN3TBSEL_TX1 _CAN3TBSEL.Bits.TX1\r
+#define CAN3TBSEL_TX2 _CAN3TBSEL.Bits.TX2\r
+#define CAN3TBSEL_TX _CAN3TBSEL.MergedBits.grpTX\r
+\r
+\r
+/*** CAN3IDAC - MSCAN 3 Identifier Acceptance Control Register; 0x0000020B ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte IDHIT0 :1; /* Identifier Acceptance Hit Indicator 0 */\r
+ byte IDHIT1 :1; /* Identifier Acceptance Hit Indicator 1 */\r
+ byte IDHIT2 :1; /* Identifier Acceptance Hit Indicator 2 */\r
+ byte :1; \r
+ byte IDAM0 :1; /* Identifier Acceptance Mode 0 */\r
+ byte IDAM1 :1; /* Identifier Acceptance Mode 1 */\r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpIDHIT :3;\r
+ byte :1;\r
+ byte grpIDAM :2;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CAN3IDACSTR;\r
+extern volatile CAN3IDACSTR _CAN3IDAC @(REG_BASE + 0x0000020B);\r
+#define CAN3IDAC _CAN3IDAC.Byte\r
+#define CAN3IDAC_IDHIT0 _CAN3IDAC.Bits.IDHIT0\r
+#define CAN3IDAC_IDHIT1 _CAN3IDAC.Bits.IDHIT1\r
+#define CAN3IDAC_IDHIT2 _CAN3IDAC.Bits.IDHIT2\r
+#define CAN3IDAC_IDAM0 _CAN3IDAC.Bits.IDAM0\r
+#define CAN3IDAC_IDAM1 _CAN3IDAC.Bits.IDAM1\r
+#define CAN3IDAC_IDHIT _CAN3IDAC.MergedBits.grpIDHIT\r
+#define CAN3IDAC_IDAM _CAN3IDAC.MergedBits.grpIDAM\r
+\r
+\r
+/*** CAN3RXERR - MSCAN 3 Receive Error Counter Register; 0x0000020E ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte RXERR0 :1; /* Bit 0 */\r
+ byte RXERR1 :1; /* Bit 1 */\r
+ byte RXERR2 :1; /* Bit 2 */\r
+ byte RXERR3 :1; /* Bit 3 */\r
+ byte RXERR4 :1; /* Bit 4 */\r
+ byte RXERR5 :1; /* Bit 5 */\r
+ byte RXERR6 :1; /* Bit 6 */\r
+ byte RXERR7 :1; /* Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpRXERR :8;\r
+ } MergedBits;\r
+} CAN3RXERRSTR;\r
+extern volatile CAN3RXERRSTR _CAN3RXERR @(REG_BASE + 0x0000020E);\r
+#define CAN3RXERR _CAN3RXERR.Byte\r
+#define CAN3RXERR_RXERR0 _CAN3RXERR.Bits.RXERR0\r
+#define CAN3RXERR_RXERR1 _CAN3RXERR.Bits.RXERR1\r
+#define CAN3RXERR_RXERR2 _CAN3RXERR.Bits.RXERR2\r
+#define CAN3RXERR_RXERR3 _CAN3RXERR.Bits.RXERR3\r
+#define CAN3RXERR_RXERR4 _CAN3RXERR.Bits.RXERR4\r
+#define CAN3RXERR_RXERR5 _CAN3RXERR.Bits.RXERR5\r
+#define CAN3RXERR_RXERR6 _CAN3RXERR.Bits.RXERR6\r
+#define CAN3RXERR_RXERR7 _CAN3RXERR.Bits.RXERR7\r
+#define CAN3RXERR_RXERR _CAN3RXERR.MergedBits.grpRXERR\r
+\r
+\r
+/*** CAN3TXERR - MSCAN 3 Transmit Error Counter Register; 0x0000020F ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte TXERR0 :1; /* Bit 0 */\r
+ byte TXERR1 :1; /* Bit 1 */\r
+ byte TXERR2 :1; /* Bit 2 */\r
+ byte TXERR3 :1; /* Bit 3 */\r
+ byte TXERR4 :1; /* Bit 4 */\r
+ byte TXERR5 :1; /* Bit 5 */\r
+ byte TXERR6 :1; /* Bit 6 */\r
+ byte TXERR7 :1; /* Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpTXERR :8;\r
+ } MergedBits;\r
+} CAN3TXERRSTR;\r
+extern volatile CAN3TXERRSTR _CAN3TXERR @(REG_BASE + 0x0000020F);\r
+#define CAN3TXERR _CAN3TXERR.Byte\r
+#define CAN3TXERR_TXERR0 _CAN3TXERR.Bits.TXERR0\r
+#define CAN3TXERR_TXERR1 _CAN3TXERR.Bits.TXERR1\r
+#define CAN3TXERR_TXERR2 _CAN3TXERR.Bits.TXERR2\r
+#define CAN3TXERR_TXERR3 _CAN3TXERR.Bits.TXERR3\r
+#define CAN3TXERR_TXERR4 _CAN3TXERR.Bits.TXERR4\r
+#define CAN3TXERR_TXERR5 _CAN3TXERR.Bits.TXERR5\r
+#define CAN3TXERR_TXERR6 _CAN3TXERR.Bits.TXERR6\r
+#define CAN3TXERR_TXERR7 _CAN3TXERR.Bits.TXERR7\r
+#define CAN3TXERR_TXERR _CAN3TXERR.MergedBits.grpTXERR\r
+\r
+\r
+/*** CAN3IDAR0 - MSCAN 3 Identifier Acceptance Register 0; 0x00000210 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AC0 :1; /* Acceptance Code Bit 0 */\r
+ byte AC1 :1; /* Acceptance Code Bit 1 */\r
+ byte AC2 :1; /* Acceptance Code Bit 2 */\r
+ byte AC3 :1; /* Acceptance Code Bit 3 */\r
+ byte AC4 :1; /* Acceptance Code Bit 4 */\r
+ byte AC5 :1; /* Acceptance Code Bit 5 */\r
+ byte AC6 :1; /* Acceptance Code Bit 6 */\r
+ byte AC7 :1; /* Acceptance Code Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAC :8;\r
+ } MergedBits;\r
+} CAN3IDAR0STR;\r
+extern volatile CAN3IDAR0STR _CAN3IDAR0 @(REG_BASE + 0x00000210);\r
+#define CAN3IDAR0 _CAN3IDAR0.Byte\r
+#define CAN3IDAR0_AC0 _CAN3IDAR0.Bits.AC0\r
+#define CAN3IDAR0_AC1 _CAN3IDAR0.Bits.AC1\r
+#define CAN3IDAR0_AC2 _CAN3IDAR0.Bits.AC2\r
+#define CAN3IDAR0_AC3 _CAN3IDAR0.Bits.AC3\r
+#define CAN3IDAR0_AC4 _CAN3IDAR0.Bits.AC4\r
+#define CAN3IDAR0_AC5 _CAN3IDAR0.Bits.AC5\r
+#define CAN3IDAR0_AC6 _CAN3IDAR0.Bits.AC6\r
+#define CAN3IDAR0_AC7 _CAN3IDAR0.Bits.AC7\r
+#define CAN3IDAR0_AC _CAN3IDAR0.MergedBits.grpAC\r
+\r
+\r
+/*** CAN3IDAR1 - MSCAN 3 Identifier Acceptance Register 1; 0x00000211 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AC0 :1; /* Acceptance Code Bit 0 */\r
+ byte AC1 :1; /* Acceptance Code Bit 1 */\r
+ byte AC2 :1; /* Acceptance Code Bit 2 */\r
+ byte AC3 :1; /* Acceptance Code Bit 3 */\r
+ byte AC4 :1; /* Acceptance Code Bit 4 */\r
+ byte AC5 :1; /* Acceptance Code Bit 5 */\r
+ byte AC6 :1; /* Acceptance Code Bit 6 */\r
+ byte AC7 :1; /* Acceptance Code Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAC :8;\r
+ } MergedBits;\r
+} CAN3IDAR1STR;\r
+extern volatile CAN3IDAR1STR _CAN3IDAR1 @(REG_BASE + 0x00000211);\r
+#define CAN3IDAR1 _CAN3IDAR1.Byte\r
+#define CAN3IDAR1_AC0 _CAN3IDAR1.Bits.AC0\r
+#define CAN3IDAR1_AC1 _CAN3IDAR1.Bits.AC1\r
+#define CAN3IDAR1_AC2 _CAN3IDAR1.Bits.AC2\r
+#define CAN3IDAR1_AC3 _CAN3IDAR1.Bits.AC3\r
+#define CAN3IDAR1_AC4 _CAN3IDAR1.Bits.AC4\r
+#define CAN3IDAR1_AC5 _CAN3IDAR1.Bits.AC5\r
+#define CAN3IDAR1_AC6 _CAN3IDAR1.Bits.AC6\r
+#define CAN3IDAR1_AC7 _CAN3IDAR1.Bits.AC7\r
+#define CAN3IDAR1_AC _CAN3IDAR1.MergedBits.grpAC\r
+\r
+\r
+/*** CAN3IDAR2 - MSCAN 3 Identifier Acceptance Register 2; 0x00000212 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AC0 :1; /* Acceptance Code Bit 0 */\r
+ byte AC1 :1; /* Acceptance Code Bit 1 */\r
+ byte AC2 :1; /* Acceptance Code Bit 2 */\r
+ byte AC3 :1; /* Acceptance Code Bit 3 */\r
+ byte AC4 :1; /* Acceptance Code Bit 4 */\r
+ byte AC5 :1; /* Acceptance Code Bit 5 */\r
+ byte AC6 :1; /* Acceptance Code Bit 6 */\r
+ byte AC7 :1; /* Acceptance Code Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAC :8;\r
+ } MergedBits;\r
+} CAN3IDAR2STR;\r
+extern volatile CAN3IDAR2STR _CAN3IDAR2 @(REG_BASE + 0x00000212);\r
+#define CAN3IDAR2 _CAN3IDAR2.Byte\r
+#define CAN3IDAR2_AC0 _CAN3IDAR2.Bits.AC0\r
+#define CAN3IDAR2_AC1 _CAN3IDAR2.Bits.AC1\r
+#define CAN3IDAR2_AC2 _CAN3IDAR2.Bits.AC2\r
+#define CAN3IDAR2_AC3 _CAN3IDAR2.Bits.AC3\r
+#define CAN3IDAR2_AC4 _CAN3IDAR2.Bits.AC4\r
+#define CAN3IDAR2_AC5 _CAN3IDAR2.Bits.AC5\r
+#define CAN3IDAR2_AC6 _CAN3IDAR2.Bits.AC6\r
+#define CAN3IDAR2_AC7 _CAN3IDAR2.Bits.AC7\r
+#define CAN3IDAR2_AC _CAN3IDAR2.MergedBits.grpAC\r
+\r
+\r
+/*** CAN3IDAR3 - MSCAN 3 Identifier Acceptance Register 3; 0x00000213 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AC0 :1; /* Acceptance Code Bit 0 */\r
+ byte AC1 :1; /* Acceptance Code Bit 1 */\r
+ byte AC2 :1; /* Acceptance Code Bit 2 */\r
+ byte AC3 :1; /* Acceptance Code Bit 3 */\r
+ byte AC4 :1; /* Acceptance Code Bit 4 */\r
+ byte AC5 :1; /* Acceptance Code Bit 5 */\r
+ byte AC6 :1; /* Acceptance Code Bit 6 */\r
+ byte AC7 :1; /* Acceptance Code Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAC :8;\r
+ } MergedBits;\r
+} CAN3IDAR3STR;\r
+extern volatile CAN3IDAR3STR _CAN3IDAR3 @(REG_BASE + 0x00000213);\r
+#define CAN3IDAR3 _CAN3IDAR3.Byte\r
+#define CAN3IDAR3_AC0 _CAN3IDAR3.Bits.AC0\r
+#define CAN3IDAR3_AC1 _CAN3IDAR3.Bits.AC1\r
+#define CAN3IDAR3_AC2 _CAN3IDAR3.Bits.AC2\r
+#define CAN3IDAR3_AC3 _CAN3IDAR3.Bits.AC3\r
+#define CAN3IDAR3_AC4 _CAN3IDAR3.Bits.AC4\r
+#define CAN3IDAR3_AC5 _CAN3IDAR3.Bits.AC5\r
+#define CAN3IDAR3_AC6 _CAN3IDAR3.Bits.AC6\r
+#define CAN3IDAR3_AC7 _CAN3IDAR3.Bits.AC7\r
+#define CAN3IDAR3_AC _CAN3IDAR3.MergedBits.grpAC\r
+\r
+\r
+/*** CAN3IDMR0 - MSCAN 3 Identifier Mask Register 0; 0x00000214 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AM0 :1; /* Acceptance Mask Bit 0 */\r
+ byte AM1 :1; /* Acceptance Mask Bit 1 */\r
+ byte AM2 :1; /* Acceptance Mask Bit 2 */\r
+ byte AM3 :1; /* Acceptance Mask Bit 3 */\r
+ byte AM4 :1; /* Acceptance Mask Bit 4 */\r
+ byte AM5 :1; /* Acceptance Mask Bit 5 */\r
+ byte AM6 :1; /* Acceptance Mask Bit 6 */\r
+ byte AM7 :1; /* Acceptance Mask Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAM :8;\r
+ } MergedBits;\r
+} CAN3IDMR0STR;\r
+extern volatile CAN3IDMR0STR _CAN3IDMR0 @(REG_BASE + 0x00000214);\r
+#define CAN3IDMR0 _CAN3IDMR0.Byte\r
+#define CAN3IDMR0_AM0 _CAN3IDMR0.Bits.AM0\r
+#define CAN3IDMR0_AM1 _CAN3IDMR0.Bits.AM1\r
+#define CAN3IDMR0_AM2 _CAN3IDMR0.Bits.AM2\r
+#define CAN3IDMR0_AM3 _CAN3IDMR0.Bits.AM3\r
+#define CAN3IDMR0_AM4 _CAN3IDMR0.Bits.AM4\r
+#define CAN3IDMR0_AM5 _CAN3IDMR0.Bits.AM5\r
+#define CAN3IDMR0_AM6 _CAN3IDMR0.Bits.AM6\r
+#define CAN3IDMR0_AM7 _CAN3IDMR0.Bits.AM7\r
+#define CAN3IDMR0_AM _CAN3IDMR0.MergedBits.grpAM\r
+\r
+\r
+/*** CAN3IDMR1 - MSCAN 3 Identifier Mask Register 1; 0x00000215 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AM0 :1; /* Acceptance Mask Bit 0 */\r
+ byte AM1 :1; /* Acceptance Mask Bit 1 */\r
+ byte AM2 :1; /* Acceptance Mask Bit 2 */\r
+ byte AM3 :1; /* Acceptance Mask Bit 3 */\r
+ byte AM4 :1; /* Acceptance Mask Bit 4 */\r
+ byte AM5 :1; /* Acceptance Mask Bit 5 */\r
+ byte AM6 :1; /* Acceptance Mask Bit 6 */\r
+ byte AM7 :1; /* Acceptance Mask Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAM :8;\r
+ } MergedBits;\r
+} CAN3IDMR1STR;\r
+extern volatile CAN3IDMR1STR _CAN3IDMR1 @(REG_BASE + 0x00000215);\r
+#define CAN3IDMR1 _CAN3IDMR1.Byte\r
+#define CAN3IDMR1_AM0 _CAN3IDMR1.Bits.AM0\r
+#define CAN3IDMR1_AM1 _CAN3IDMR1.Bits.AM1\r
+#define CAN3IDMR1_AM2 _CAN3IDMR1.Bits.AM2\r
+#define CAN3IDMR1_AM3 _CAN3IDMR1.Bits.AM3\r
+#define CAN3IDMR1_AM4 _CAN3IDMR1.Bits.AM4\r
+#define CAN3IDMR1_AM5 _CAN3IDMR1.Bits.AM5\r
+#define CAN3IDMR1_AM6 _CAN3IDMR1.Bits.AM6\r
+#define CAN3IDMR1_AM7 _CAN3IDMR1.Bits.AM7\r
+#define CAN3IDMR1_AM _CAN3IDMR1.MergedBits.grpAM\r
+\r
+\r
+/*** CAN3IDMR2 - MSCAN 3 Identifier Mask Register 2; 0x00000216 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AM0 :1; /* Acceptance Mask Bit 0 */\r
+ byte AM1 :1; /* Acceptance Mask Bit 1 */\r
+ byte AM2 :1; /* Acceptance Mask Bit 2 */\r
+ byte AM3 :1; /* Acceptance Mask Bit 3 */\r
+ byte AM4 :1; /* Acceptance Mask Bit 4 */\r
+ byte AM5 :1; /* Acceptance Mask Bit 5 */\r
+ byte AM6 :1; /* Acceptance Mask Bit 6 */\r
+ byte AM7 :1; /* Acceptance Mask Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAM :8;\r
+ } MergedBits;\r
+} CAN3IDMR2STR;\r
+extern volatile CAN3IDMR2STR _CAN3IDMR2 @(REG_BASE + 0x00000216);\r
+#define CAN3IDMR2 _CAN3IDMR2.Byte\r
+#define CAN3IDMR2_AM0 _CAN3IDMR2.Bits.AM0\r
+#define CAN3IDMR2_AM1 _CAN3IDMR2.Bits.AM1\r
+#define CAN3IDMR2_AM2 _CAN3IDMR2.Bits.AM2\r
+#define CAN3IDMR2_AM3 _CAN3IDMR2.Bits.AM3\r
+#define CAN3IDMR2_AM4 _CAN3IDMR2.Bits.AM4\r
+#define CAN3IDMR2_AM5 _CAN3IDMR2.Bits.AM5\r
+#define CAN3IDMR2_AM6 _CAN3IDMR2.Bits.AM6\r
+#define CAN3IDMR2_AM7 _CAN3IDMR2.Bits.AM7\r
+#define CAN3IDMR2_AM _CAN3IDMR2.MergedBits.grpAM\r
+\r
+\r
+/*** CAN3IDMR3 - MSCAN 3 Identifier Mask Register 3; 0x00000217 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AM0 :1; /* Acceptance Mask Bit 0 */\r
+ byte AM1 :1; /* Acceptance Mask Bit 1 */\r
+ byte AM2 :1; /* Acceptance Mask Bit 2 */\r
+ byte AM3 :1; /* Acceptance Mask Bit 3 */\r
+ byte AM4 :1; /* Acceptance Mask Bit 4 */\r
+ byte AM5 :1; /* Acceptance Mask Bit 5 */\r
+ byte AM6 :1; /* Acceptance Mask Bit 6 */\r
+ byte AM7 :1; /* Acceptance Mask Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAM :8;\r
+ } MergedBits;\r
+} CAN3IDMR3STR;\r
+extern volatile CAN3IDMR3STR _CAN3IDMR3 @(REG_BASE + 0x00000217);\r
+#define CAN3IDMR3 _CAN3IDMR3.Byte\r
+#define CAN3IDMR3_AM0 _CAN3IDMR3.Bits.AM0\r
+#define CAN3IDMR3_AM1 _CAN3IDMR3.Bits.AM1\r
+#define CAN3IDMR3_AM2 _CAN3IDMR3.Bits.AM2\r
+#define CAN3IDMR3_AM3 _CAN3IDMR3.Bits.AM3\r
+#define CAN3IDMR3_AM4 _CAN3IDMR3.Bits.AM4\r
+#define CAN3IDMR3_AM5 _CAN3IDMR3.Bits.AM5\r
+#define CAN3IDMR3_AM6 _CAN3IDMR3.Bits.AM6\r
+#define CAN3IDMR3_AM7 _CAN3IDMR3.Bits.AM7\r
+#define CAN3IDMR3_AM _CAN3IDMR3.MergedBits.grpAM\r
+\r
+\r
+/*** CAN3IDAR4 - MSCAN 3 Identifier Acceptance Register 4; 0x00000218 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AC0 :1; /* Acceptance Code Bit 0 */\r
+ byte AC1 :1; /* Acceptance Code Bit 1 */\r
+ byte AC2 :1; /* Acceptance Code Bit 2 */\r
+ byte AC3 :1; /* Acceptance Code Bit 3 */\r
+ byte AC4 :1; /* Acceptance Code Bit 4 */\r
+ byte AC5 :1; /* Acceptance Code Bit 5 */\r
+ byte AC6 :1; /* Acceptance Code Bit 6 */\r
+ byte AC7 :1; /* Acceptance Code Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAC :8;\r
+ } MergedBits;\r
+} CAN3IDAR4STR;\r
+extern volatile CAN3IDAR4STR _CAN3IDAR4 @(REG_BASE + 0x00000218);\r
+#define CAN3IDAR4 _CAN3IDAR4.Byte\r
+#define CAN3IDAR4_AC0 _CAN3IDAR4.Bits.AC0\r
+#define CAN3IDAR4_AC1 _CAN3IDAR4.Bits.AC1\r
+#define CAN3IDAR4_AC2 _CAN3IDAR4.Bits.AC2\r
+#define CAN3IDAR4_AC3 _CAN3IDAR4.Bits.AC3\r
+#define CAN3IDAR4_AC4 _CAN3IDAR4.Bits.AC4\r
+#define CAN3IDAR4_AC5 _CAN3IDAR4.Bits.AC5\r
+#define CAN3IDAR4_AC6 _CAN3IDAR4.Bits.AC6\r
+#define CAN3IDAR4_AC7 _CAN3IDAR4.Bits.AC7\r
+#define CAN3IDAR4_AC _CAN3IDAR4.MergedBits.grpAC\r
+\r
+\r
+/*** CAN3IDAR5 - MSCAN 3 Identifier Acceptance Register 5; 0x00000219 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AC0 :1; /* Acceptance Code Bit 0 */\r
+ byte AC1 :1; /* Acceptance Code Bit 1 */\r
+ byte AC2 :1; /* Acceptance Code Bit 2 */\r
+ byte AC3 :1; /* Acceptance Code Bit 3 */\r
+ byte AC4 :1; /* Acceptance Code Bit 4 */\r
+ byte AC5 :1; /* Acceptance Code Bit 5 */\r
+ byte AC6 :1; /* Acceptance Code Bit 6 */\r
+ byte AC7 :1; /* Acceptance Code Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAC :8;\r
+ } MergedBits;\r
+} CAN3IDAR5STR;\r
+extern volatile CAN3IDAR5STR _CAN3IDAR5 @(REG_BASE + 0x00000219);\r
+#define CAN3IDAR5 _CAN3IDAR5.Byte\r
+#define CAN3IDAR5_AC0 _CAN3IDAR5.Bits.AC0\r
+#define CAN3IDAR5_AC1 _CAN3IDAR5.Bits.AC1\r
+#define CAN3IDAR5_AC2 _CAN3IDAR5.Bits.AC2\r
+#define CAN3IDAR5_AC3 _CAN3IDAR5.Bits.AC3\r
+#define CAN3IDAR5_AC4 _CAN3IDAR5.Bits.AC4\r
+#define CAN3IDAR5_AC5 _CAN3IDAR5.Bits.AC5\r
+#define CAN3IDAR5_AC6 _CAN3IDAR5.Bits.AC6\r
+#define CAN3IDAR5_AC7 _CAN3IDAR5.Bits.AC7\r
+#define CAN3IDAR5_AC _CAN3IDAR5.MergedBits.grpAC\r
+\r
+\r
+/*** CAN3IDAR6 - MSCAN 3 Identifier Acceptance Register 6; 0x0000021A ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AC0 :1; /* Acceptance Code Bit 0 */\r
+ byte AC1 :1; /* Acceptance Code Bit 1 */\r
+ byte AC2 :1; /* Acceptance Code Bit 2 */\r
+ byte AC3 :1; /* Acceptance Code Bit 3 */\r
+ byte AC4 :1; /* Acceptance Code Bit 4 */\r
+ byte AC5 :1; /* Acceptance Code Bit 5 */\r
+ byte AC6 :1; /* Acceptance Code Bit 6 */\r
+ byte AC7 :1; /* Acceptance Code Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAC :8;\r
+ } MergedBits;\r
+} CAN3IDAR6STR;\r
+extern volatile CAN3IDAR6STR _CAN3IDAR6 @(REG_BASE + 0x0000021A);\r
+#define CAN3IDAR6 _CAN3IDAR6.Byte\r
+#define CAN3IDAR6_AC0 _CAN3IDAR6.Bits.AC0\r
+#define CAN3IDAR6_AC1 _CAN3IDAR6.Bits.AC1\r
+#define CAN3IDAR6_AC2 _CAN3IDAR6.Bits.AC2\r
+#define CAN3IDAR6_AC3 _CAN3IDAR6.Bits.AC3\r
+#define CAN3IDAR6_AC4 _CAN3IDAR6.Bits.AC4\r
+#define CAN3IDAR6_AC5 _CAN3IDAR6.Bits.AC5\r
+#define CAN3IDAR6_AC6 _CAN3IDAR6.Bits.AC6\r
+#define CAN3IDAR6_AC7 _CAN3IDAR6.Bits.AC7\r
+#define CAN3IDAR6_AC _CAN3IDAR6.MergedBits.grpAC\r
+\r
+\r
+/*** CAN3IDAR7 - MSCAN 3 Identifier Acceptance Register 7; 0x0000021B ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AC0 :1; /* Acceptance Code Bit 0 */\r
+ byte AC1 :1; /* Acceptance Code Bit 1 */\r
+ byte AC2 :1; /* Acceptance Code Bit 2 */\r
+ byte AC3 :1; /* Acceptance Code Bit 3 */\r
+ byte AC4 :1; /* Acceptance Code Bit 4 */\r
+ byte AC5 :1; /* Acceptance Code Bit 5 */\r
+ byte AC6 :1; /* Acceptance Code Bit 6 */\r
+ byte AC7 :1; /* Acceptance Code Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAC :8;\r
+ } MergedBits;\r
+} CAN3IDAR7STR;\r
+extern volatile CAN3IDAR7STR _CAN3IDAR7 @(REG_BASE + 0x0000021B);\r
+#define CAN3IDAR7 _CAN3IDAR7.Byte\r
+#define CAN3IDAR7_AC0 _CAN3IDAR7.Bits.AC0\r
+#define CAN3IDAR7_AC1 _CAN3IDAR7.Bits.AC1\r
+#define CAN3IDAR7_AC2 _CAN3IDAR7.Bits.AC2\r
+#define CAN3IDAR7_AC3 _CAN3IDAR7.Bits.AC3\r
+#define CAN3IDAR7_AC4 _CAN3IDAR7.Bits.AC4\r
+#define CAN3IDAR7_AC5 _CAN3IDAR7.Bits.AC5\r
+#define CAN3IDAR7_AC6 _CAN3IDAR7.Bits.AC6\r
+#define CAN3IDAR7_AC7 _CAN3IDAR7.Bits.AC7\r
+#define CAN3IDAR7_AC _CAN3IDAR7.MergedBits.grpAC\r
+\r
+\r
+/*** CAN3IDMR4 - MSCAN 3 Identifier Mask Register 4; 0x0000021C ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AM0 :1; /* Acceptance Mask Bit 0 */\r
+ byte AM1 :1; /* Acceptance Mask Bit 1 */\r
+ byte AM2 :1; /* Acceptance Mask Bit 2 */\r
+ byte AM3 :1; /* Acceptance Mask Bit 3 */\r
+ byte AM4 :1; /* Acceptance Mask Bit 4 */\r
+ byte AM5 :1; /* Acceptance Mask Bit 5 */\r
+ byte AM6 :1; /* Acceptance Mask Bit 6 */\r
+ byte AM7 :1; /* Acceptance Mask Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAM :8;\r
+ } MergedBits;\r
+} CAN3IDMR4STR;\r
+extern volatile CAN3IDMR4STR _CAN3IDMR4 @(REG_BASE + 0x0000021C);\r
+#define CAN3IDMR4 _CAN3IDMR4.Byte\r
+#define CAN3IDMR4_AM0 _CAN3IDMR4.Bits.AM0\r
+#define CAN3IDMR4_AM1 _CAN3IDMR4.Bits.AM1\r
+#define CAN3IDMR4_AM2 _CAN3IDMR4.Bits.AM2\r
+#define CAN3IDMR4_AM3 _CAN3IDMR4.Bits.AM3\r
+#define CAN3IDMR4_AM4 _CAN3IDMR4.Bits.AM4\r
+#define CAN3IDMR4_AM5 _CAN3IDMR4.Bits.AM5\r
+#define CAN3IDMR4_AM6 _CAN3IDMR4.Bits.AM6\r
+#define CAN3IDMR4_AM7 _CAN3IDMR4.Bits.AM7\r
+#define CAN3IDMR4_AM _CAN3IDMR4.MergedBits.grpAM\r
+\r
+\r
+/*** CAN3IDMR5 - MSCAN 3 Identifier Mask Register 5; 0x0000021D ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AM0 :1; /* Acceptance Mask Bit 0 */\r
+ byte AM1 :1; /* Acceptance Mask Bit 1 */\r
+ byte AM2 :1; /* Acceptance Mask Bit 2 */\r
+ byte AM3 :1; /* Acceptance Mask Bit 3 */\r
+ byte AM4 :1; /* Acceptance Mask Bit 4 */\r
+ byte AM5 :1; /* Acceptance Mask Bit 5 */\r
+ byte AM6 :1; /* Acceptance Mask Bit 6 */\r
+ byte AM7 :1; /* Acceptance Mask Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAM :8;\r
+ } MergedBits;\r
+} CAN3IDMR5STR;\r
+extern volatile CAN3IDMR5STR _CAN3IDMR5 @(REG_BASE + 0x0000021D);\r
+#define CAN3IDMR5 _CAN3IDMR5.Byte\r
+#define CAN3IDMR5_AM0 _CAN3IDMR5.Bits.AM0\r
+#define CAN3IDMR5_AM1 _CAN3IDMR5.Bits.AM1\r
+#define CAN3IDMR5_AM2 _CAN3IDMR5.Bits.AM2\r
+#define CAN3IDMR5_AM3 _CAN3IDMR5.Bits.AM3\r
+#define CAN3IDMR5_AM4 _CAN3IDMR5.Bits.AM4\r
+#define CAN3IDMR5_AM5 _CAN3IDMR5.Bits.AM5\r
+#define CAN3IDMR5_AM6 _CAN3IDMR5.Bits.AM6\r
+#define CAN3IDMR5_AM7 _CAN3IDMR5.Bits.AM7\r
+#define CAN3IDMR5_AM _CAN3IDMR5.MergedBits.grpAM\r
+\r
+\r
+/*** CAN3IDMR6 - MSCAN 3 Identifier Mask Register 6; 0x0000021E ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AM0 :1; /* Acceptance Mask Bit 0 */\r
+ byte AM1 :1; /* Acceptance Mask Bit 1 */\r
+ byte AM2 :1; /* Acceptance Mask Bit 2 */\r
+ byte AM3 :1; /* Acceptance Mask Bit 3 */\r
+ byte AM4 :1; /* Acceptance Mask Bit 4 */\r
+ byte AM5 :1; /* Acceptance Mask Bit 5 */\r
+ byte AM6 :1; /* Acceptance Mask Bit 6 */\r
+ byte AM7 :1; /* Acceptance Mask Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAM :8;\r
+ } MergedBits;\r
+} CAN3IDMR6STR;\r
+extern volatile CAN3IDMR6STR _CAN3IDMR6 @(REG_BASE + 0x0000021E);\r
+#define CAN3IDMR6 _CAN3IDMR6.Byte\r
+#define CAN3IDMR6_AM0 _CAN3IDMR6.Bits.AM0\r
+#define CAN3IDMR6_AM1 _CAN3IDMR6.Bits.AM1\r
+#define CAN3IDMR6_AM2 _CAN3IDMR6.Bits.AM2\r
+#define CAN3IDMR6_AM3 _CAN3IDMR6.Bits.AM3\r
+#define CAN3IDMR6_AM4 _CAN3IDMR6.Bits.AM4\r
+#define CAN3IDMR6_AM5 _CAN3IDMR6.Bits.AM5\r
+#define CAN3IDMR6_AM6 _CAN3IDMR6.Bits.AM6\r
+#define CAN3IDMR6_AM7 _CAN3IDMR6.Bits.AM7\r
+#define CAN3IDMR6_AM _CAN3IDMR6.MergedBits.grpAM\r
+\r
+\r
+/*** CAN3IDMR7 - MSCAN 3 Identifier Mask Register 7; 0x0000021F ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AM0 :1; /* Acceptance Mask Bit 0 */\r
+ byte AM1 :1; /* Acceptance Mask Bit 1 */\r
+ byte AM2 :1; /* Acceptance Mask Bit 2 */\r
+ byte AM3 :1; /* Acceptance Mask Bit 3 */\r
+ byte AM4 :1; /* Acceptance Mask Bit 4 */\r
+ byte AM5 :1; /* Acceptance Mask Bit 5 */\r
+ byte AM6 :1; /* Acceptance Mask Bit 6 */\r
+ byte AM7 :1; /* Acceptance Mask Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAM :8;\r
+ } MergedBits;\r
+} CAN3IDMR7STR;\r
+extern volatile CAN3IDMR7STR _CAN3IDMR7 @(REG_BASE + 0x0000021F);\r
+#define CAN3IDMR7 _CAN3IDMR7.Byte\r
+#define CAN3IDMR7_AM0 _CAN3IDMR7.Bits.AM0\r
+#define CAN3IDMR7_AM1 _CAN3IDMR7.Bits.AM1\r
+#define CAN3IDMR7_AM2 _CAN3IDMR7.Bits.AM2\r
+#define CAN3IDMR7_AM3 _CAN3IDMR7.Bits.AM3\r
+#define CAN3IDMR7_AM4 _CAN3IDMR7.Bits.AM4\r
+#define CAN3IDMR7_AM5 _CAN3IDMR7.Bits.AM5\r
+#define CAN3IDMR7_AM6 _CAN3IDMR7.Bits.AM6\r
+#define CAN3IDMR7_AM7 _CAN3IDMR7.Bits.AM7\r
+#define CAN3IDMR7_AM _CAN3IDMR7.MergedBits.grpAM\r
+\r
+\r
+/*** CAN3RXIDR0 - MSCAN 3 Receive Identifier Register 0; 0x00000220 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ID21 :1; /* Extended format identifier Bit 21 */\r
+ byte ID22 :1; /* Extended format identifier Bit 22 */\r
+ byte ID23 :1; /* Extended format identifier Bit 23 */\r
+ byte ID24 :1; /* Extended format identifier Bit 24 */\r
+ byte ID25 :1; /* Extended format identifier Bit 25 */\r
+ byte ID26 :1; /* Extended format identifier Bit 26 */\r
+ byte ID27 :1; /* Extended format identifier Bit 27 */\r
+ byte ID28 :1; /* Extended format identifier Bit 28 */\r
+ } Bits;\r
+ struct {\r
+ byte grpID_21 :8;\r
+ } MergedBits;\r
+} CAN3RXIDR0STR;\r
+extern volatile CAN3RXIDR0STR _CAN3RXIDR0 @(REG_BASE + 0x00000220);\r
+#define CAN3RXIDR0 _CAN3RXIDR0.Byte\r
+#define CAN3RXIDR0_ID21 _CAN3RXIDR0.Bits.ID21\r
+#define CAN3RXIDR0_ID22 _CAN3RXIDR0.Bits.ID22\r
+#define CAN3RXIDR0_ID23 _CAN3RXIDR0.Bits.ID23\r
+#define CAN3RXIDR0_ID24 _CAN3RXIDR0.Bits.ID24\r
+#define CAN3RXIDR0_ID25 _CAN3RXIDR0.Bits.ID25\r
+#define CAN3RXIDR0_ID26 _CAN3RXIDR0.Bits.ID26\r
+#define CAN3RXIDR0_ID27 _CAN3RXIDR0.Bits.ID27\r
+#define CAN3RXIDR0_ID28 _CAN3RXIDR0.Bits.ID28\r
+#define CAN3RXIDR0_ID_21 _CAN3RXIDR0.MergedBits.grpID_21\r
+#define CAN3RXIDR0_ID CAN3RXIDR0_ID_21\r
+\r
+\r
+/*** CAN3RXIDR1 - MSCAN 3 Receive Identifier Register 1; 0x00000221 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ID15 :1; /* Extended format identifier Bit 15 */\r
+ byte ID16 :1; /* Extended format identifier Bit 16 */\r
+ byte ID17 :1; /* Extended format identifier Bit 17 */\r
+ byte IDE :1; /* ID Extended */\r
+ byte SRR :1; /* Substitute Remote Request */\r
+ byte ID18 :1; /* Extended format identifier Bit 18 */\r
+ byte ID19 :1; /* Extended format identifier Bit 19 */\r
+ byte ID20 :1; /* Extended format identifier Bit 20 */\r
+ } Bits;\r
+ struct {\r
+ byte grpID_15 :3;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpID_18 :3;\r
+ } MergedBits;\r
+} CAN3RXIDR1STR;\r
+extern volatile CAN3RXIDR1STR _CAN3RXIDR1 @(REG_BASE + 0x00000221);\r
+#define CAN3RXIDR1 _CAN3RXIDR1.Byte\r
+#define CAN3RXIDR1_ID15 _CAN3RXIDR1.Bits.ID15\r
+#define CAN3RXIDR1_ID16 _CAN3RXIDR1.Bits.ID16\r
+#define CAN3RXIDR1_ID17 _CAN3RXIDR1.Bits.ID17\r
+#define CAN3RXIDR1_IDE _CAN3RXIDR1.Bits.IDE\r
+#define CAN3RXIDR1_SRR _CAN3RXIDR1.Bits.SRR\r
+#define CAN3RXIDR1_ID18 _CAN3RXIDR1.Bits.ID18\r
+#define CAN3RXIDR1_ID19 _CAN3RXIDR1.Bits.ID19\r
+#define CAN3RXIDR1_ID20 _CAN3RXIDR1.Bits.ID20\r
+#define CAN3RXIDR1_ID_15 _CAN3RXIDR1.MergedBits.grpID_15\r
+#define CAN3RXIDR1_ID_18 _CAN3RXIDR1.MergedBits.grpID_18\r
+#define CAN3RXIDR1_ID CAN3RXIDR1_ID_15\r
+\r
+\r
+/*** CAN3RXIDR2 - MSCAN 3 Receive Identifier Register 2; 0x00000222 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ID7 :1; /* Extended format identifier Bit 7 */\r
+ byte ID8 :1; /* Extended format identifier Bit 8 */\r
+ byte ID9 :1; /* Extended format identifier Bit 9 */\r
+ byte ID10 :1; /* Extended format identifier Bit 10 */\r
+ byte ID11 :1; /* Extended format identifier Bit 11 */\r
+ byte ID12 :1; /* Extended format identifier Bit 12 */\r
+ byte ID13 :1; /* Extended format identifier Bit 13 */\r
+ byte ID14 :1; /* Extended format identifier Bit 14 */\r
+ } Bits;\r
+ struct {\r
+ byte grpID_7 :8;\r
+ } MergedBits;\r
+} CAN3RXIDR2STR;\r
+extern volatile CAN3RXIDR2STR _CAN3RXIDR2 @(REG_BASE + 0x00000222);\r
+#define CAN3RXIDR2 _CAN3RXIDR2.Byte\r
+#define CAN3RXIDR2_ID7 _CAN3RXIDR2.Bits.ID7\r
+#define CAN3RXIDR2_ID8 _CAN3RXIDR2.Bits.ID8\r
+#define CAN3RXIDR2_ID9 _CAN3RXIDR2.Bits.ID9\r
+#define CAN3RXIDR2_ID10 _CAN3RXIDR2.Bits.ID10\r
+#define CAN3RXIDR2_ID11 _CAN3RXIDR2.Bits.ID11\r
+#define CAN3RXIDR2_ID12 _CAN3RXIDR2.Bits.ID12\r
+#define CAN3RXIDR2_ID13 _CAN3RXIDR2.Bits.ID13\r
+#define CAN3RXIDR2_ID14 _CAN3RXIDR2.Bits.ID14\r
+#define CAN3RXIDR2_ID_7 _CAN3RXIDR2.MergedBits.grpID_7\r
+#define CAN3RXIDR2_ID CAN3RXIDR2_ID_7\r
+\r
+\r
+/*** CAN3RXIDR3 - MSCAN 3 Receive Identifier Register 3; 0x00000223 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte RTR :1; /* Remote Transmission Request */\r
+ byte ID0 :1; /* Extended format identifier Bit 0 */\r
+ byte ID1 :1; /* Extended format identifier Bit 1 */\r
+ byte ID2 :1; /* Extended format identifier Bit 2 */\r
+ byte ID3 :1; /* Extended format identifier Bit 3 */\r
+ byte ID4 :1; /* Extended format identifier Bit 4 */\r
+ byte ID5 :1; /* Extended format identifier Bit 5 */\r
+ byte ID6 :1; /* Extended format identifier Bit 6 */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte grpID :7;\r
+ } MergedBits;\r
+} CAN3RXIDR3STR;\r
+extern volatile CAN3RXIDR3STR _CAN3RXIDR3 @(REG_BASE + 0x00000223);\r
+#define CAN3RXIDR3 _CAN3RXIDR3.Byte\r
+#define CAN3RXIDR3_RTR _CAN3RXIDR3.Bits.RTR\r
+#define CAN3RXIDR3_ID0 _CAN3RXIDR3.Bits.ID0\r
+#define CAN3RXIDR3_ID1 _CAN3RXIDR3.Bits.ID1\r
+#define CAN3RXIDR3_ID2 _CAN3RXIDR3.Bits.ID2\r
+#define CAN3RXIDR3_ID3 _CAN3RXIDR3.Bits.ID3\r
+#define CAN3RXIDR3_ID4 _CAN3RXIDR3.Bits.ID4\r
+#define CAN3RXIDR3_ID5 _CAN3RXIDR3.Bits.ID5\r
+#define CAN3RXIDR3_ID6 _CAN3RXIDR3.Bits.ID6\r
+#define CAN3RXIDR3_ID _CAN3RXIDR3.MergedBits.grpID\r
+\r
+\r
+/*** CAN3RXDSR0 - MSCAN 3 Receive Data Segment Register 0; 0x00000224 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN3RXDSR0STR;\r
+extern volatile CAN3RXDSR0STR _CAN3RXDSR0 @(REG_BASE + 0x00000224);\r
+#define CAN3RXDSR0 _CAN3RXDSR0.Byte\r
+#define CAN3RXDSR0_DB0 _CAN3RXDSR0.Bits.DB0\r
+#define CAN3RXDSR0_DB1 _CAN3RXDSR0.Bits.DB1\r
+#define CAN3RXDSR0_DB2 _CAN3RXDSR0.Bits.DB2\r
+#define CAN3RXDSR0_DB3 _CAN3RXDSR0.Bits.DB3\r
+#define CAN3RXDSR0_DB4 _CAN3RXDSR0.Bits.DB4\r
+#define CAN3RXDSR0_DB5 _CAN3RXDSR0.Bits.DB5\r
+#define CAN3RXDSR0_DB6 _CAN3RXDSR0.Bits.DB6\r
+#define CAN3RXDSR0_DB7 _CAN3RXDSR0.Bits.DB7\r
+#define CAN3RXDSR0_DB _CAN3RXDSR0.MergedBits.grpDB\r
+\r
+\r
+/*** CAN3RXDSR1 - MSCAN 3 Receive Data Segment Register 1; 0x00000225 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN3RXDSR1STR;\r
+extern volatile CAN3RXDSR1STR _CAN3RXDSR1 @(REG_BASE + 0x00000225);\r
+#define CAN3RXDSR1 _CAN3RXDSR1.Byte\r
+#define CAN3RXDSR1_DB0 _CAN3RXDSR1.Bits.DB0\r
+#define CAN3RXDSR1_DB1 _CAN3RXDSR1.Bits.DB1\r
+#define CAN3RXDSR1_DB2 _CAN3RXDSR1.Bits.DB2\r
+#define CAN3RXDSR1_DB3 _CAN3RXDSR1.Bits.DB3\r
+#define CAN3RXDSR1_DB4 _CAN3RXDSR1.Bits.DB4\r
+#define CAN3RXDSR1_DB5 _CAN3RXDSR1.Bits.DB5\r
+#define CAN3RXDSR1_DB6 _CAN3RXDSR1.Bits.DB6\r
+#define CAN3RXDSR1_DB7 _CAN3RXDSR1.Bits.DB7\r
+#define CAN3RXDSR1_DB _CAN3RXDSR1.MergedBits.grpDB\r
+\r
+\r
+/*** CAN3RXDSR2 - MSCAN 3 Receive Data Segment Register 2; 0x00000226 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN3RXDSR2STR;\r
+extern volatile CAN3RXDSR2STR _CAN3RXDSR2 @(REG_BASE + 0x00000226);\r
+#define CAN3RXDSR2 _CAN3RXDSR2.Byte\r
+#define CAN3RXDSR2_DB0 _CAN3RXDSR2.Bits.DB0\r
+#define CAN3RXDSR2_DB1 _CAN3RXDSR2.Bits.DB1\r
+#define CAN3RXDSR2_DB2 _CAN3RXDSR2.Bits.DB2\r
+#define CAN3RXDSR2_DB3 _CAN3RXDSR2.Bits.DB3\r
+#define CAN3RXDSR2_DB4 _CAN3RXDSR2.Bits.DB4\r
+#define CAN3RXDSR2_DB5 _CAN3RXDSR2.Bits.DB5\r
+#define CAN3RXDSR2_DB6 _CAN3RXDSR2.Bits.DB6\r
+#define CAN3RXDSR2_DB7 _CAN3RXDSR2.Bits.DB7\r
+#define CAN3RXDSR2_DB _CAN3RXDSR2.MergedBits.grpDB\r
+\r
+\r
+/*** CAN3RXDSR3 - MSCAN 3 Receive Data Segment Register 3; 0x00000227 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN3RXDSR3STR;\r
+extern volatile CAN3RXDSR3STR _CAN3RXDSR3 @(REG_BASE + 0x00000227);\r
+#define CAN3RXDSR3 _CAN3RXDSR3.Byte\r
+#define CAN3RXDSR3_DB0 _CAN3RXDSR3.Bits.DB0\r
+#define CAN3RXDSR3_DB1 _CAN3RXDSR3.Bits.DB1\r
+#define CAN3RXDSR3_DB2 _CAN3RXDSR3.Bits.DB2\r
+#define CAN3RXDSR3_DB3 _CAN3RXDSR3.Bits.DB3\r
+#define CAN3RXDSR3_DB4 _CAN3RXDSR3.Bits.DB4\r
+#define CAN3RXDSR3_DB5 _CAN3RXDSR3.Bits.DB5\r
+#define CAN3RXDSR3_DB6 _CAN3RXDSR3.Bits.DB6\r
+#define CAN3RXDSR3_DB7 _CAN3RXDSR3.Bits.DB7\r
+#define CAN3RXDSR3_DB _CAN3RXDSR3.MergedBits.grpDB\r
+\r
+\r
+/*** CAN3RXDSR4 - MSCAN 3 Receive Data Segment Register 4; 0x00000228 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN3RXDSR4STR;\r
+extern volatile CAN3RXDSR4STR _CAN3RXDSR4 @(REG_BASE + 0x00000228);\r
+#define CAN3RXDSR4 _CAN3RXDSR4.Byte\r
+#define CAN3RXDSR4_DB0 _CAN3RXDSR4.Bits.DB0\r
+#define CAN3RXDSR4_DB1 _CAN3RXDSR4.Bits.DB1\r
+#define CAN3RXDSR4_DB2 _CAN3RXDSR4.Bits.DB2\r
+#define CAN3RXDSR4_DB3 _CAN3RXDSR4.Bits.DB3\r
+#define CAN3RXDSR4_DB4 _CAN3RXDSR4.Bits.DB4\r
+#define CAN3RXDSR4_DB5 _CAN3RXDSR4.Bits.DB5\r
+#define CAN3RXDSR4_DB6 _CAN3RXDSR4.Bits.DB6\r
+#define CAN3RXDSR4_DB7 _CAN3RXDSR4.Bits.DB7\r
+#define CAN3RXDSR4_DB _CAN3RXDSR4.MergedBits.grpDB\r
+\r
+\r
+/*** CAN3RXDSR5 - MSCAN 3 Receive Data Segment Register 5; 0x00000229 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN3RXDSR5STR;\r
+extern volatile CAN3RXDSR5STR _CAN3RXDSR5 @(REG_BASE + 0x00000229);\r
+#define CAN3RXDSR5 _CAN3RXDSR5.Byte\r
+#define CAN3RXDSR5_DB0 _CAN3RXDSR5.Bits.DB0\r
+#define CAN3RXDSR5_DB1 _CAN3RXDSR5.Bits.DB1\r
+#define CAN3RXDSR5_DB2 _CAN3RXDSR5.Bits.DB2\r
+#define CAN3RXDSR5_DB3 _CAN3RXDSR5.Bits.DB3\r
+#define CAN3RXDSR5_DB4 _CAN3RXDSR5.Bits.DB4\r
+#define CAN3RXDSR5_DB5 _CAN3RXDSR5.Bits.DB5\r
+#define CAN3RXDSR5_DB6 _CAN3RXDSR5.Bits.DB6\r
+#define CAN3RXDSR5_DB7 _CAN3RXDSR5.Bits.DB7\r
+#define CAN3RXDSR5_DB _CAN3RXDSR5.MergedBits.grpDB\r
+\r
+\r
+/*** CAN3RXDSR6 - MSCAN 3 Receive Data Segment Register 6; 0x0000022A ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN3RXDSR6STR;\r
+extern volatile CAN3RXDSR6STR _CAN3RXDSR6 @(REG_BASE + 0x0000022A);\r
+#define CAN3RXDSR6 _CAN3RXDSR6.Byte\r
+#define CAN3RXDSR6_DB0 _CAN3RXDSR6.Bits.DB0\r
+#define CAN3RXDSR6_DB1 _CAN3RXDSR6.Bits.DB1\r
+#define CAN3RXDSR6_DB2 _CAN3RXDSR6.Bits.DB2\r
+#define CAN3RXDSR6_DB3 _CAN3RXDSR6.Bits.DB3\r
+#define CAN3RXDSR6_DB4 _CAN3RXDSR6.Bits.DB4\r
+#define CAN3RXDSR6_DB5 _CAN3RXDSR6.Bits.DB5\r
+#define CAN3RXDSR6_DB6 _CAN3RXDSR6.Bits.DB6\r
+#define CAN3RXDSR6_DB7 _CAN3RXDSR6.Bits.DB7\r
+#define CAN3RXDSR6_DB _CAN3RXDSR6.MergedBits.grpDB\r
+\r
+\r
+/*** CAN3RXDSR7 - MSCAN 3 Receive Data Segment Register 7; 0x0000022B ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN3RXDSR7STR;\r
+extern volatile CAN3RXDSR7STR _CAN3RXDSR7 @(REG_BASE + 0x0000022B);\r
+#define CAN3RXDSR7 _CAN3RXDSR7.Byte\r
+#define CAN3RXDSR7_DB0 _CAN3RXDSR7.Bits.DB0\r
+#define CAN3RXDSR7_DB1 _CAN3RXDSR7.Bits.DB1\r
+#define CAN3RXDSR7_DB2 _CAN3RXDSR7.Bits.DB2\r
+#define CAN3RXDSR7_DB3 _CAN3RXDSR7.Bits.DB3\r
+#define CAN3RXDSR7_DB4 _CAN3RXDSR7.Bits.DB4\r
+#define CAN3RXDSR7_DB5 _CAN3RXDSR7.Bits.DB5\r
+#define CAN3RXDSR7_DB6 _CAN3RXDSR7.Bits.DB6\r
+#define CAN3RXDSR7_DB7 _CAN3RXDSR7.Bits.DB7\r
+#define CAN3RXDSR7_DB _CAN3RXDSR7.MergedBits.grpDB\r
+\r
+\r
+/*** CAN3RXDLR - MSCAN 3 Receive Data Length Register; 0x0000022C ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DLC0 :1; /* Data Length Code Bit 0 */\r
+ byte DLC1 :1; /* Data Length Code Bit 1 */\r
+ byte DLC2 :1; /* Data Length Code Bit 2 */\r
+ byte DLC3 :1; /* Data Length Code Bit 3 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpDLC :4;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CAN3RXDLRSTR;\r
+extern volatile CAN3RXDLRSTR _CAN3RXDLR @(REG_BASE + 0x0000022C);\r
+#define CAN3RXDLR _CAN3RXDLR.Byte\r
+#define CAN3RXDLR_DLC0 _CAN3RXDLR.Bits.DLC0\r
+#define CAN3RXDLR_DLC1 _CAN3RXDLR.Bits.DLC1\r
+#define CAN3RXDLR_DLC2 _CAN3RXDLR.Bits.DLC2\r
+#define CAN3RXDLR_DLC3 _CAN3RXDLR.Bits.DLC3\r
+#define CAN3RXDLR_DLC _CAN3RXDLR.MergedBits.grpDLC\r
+\r
+\r
+/*** CAN3TXIDR0 - MSCAN 3 Transmit Identifier Register 0; 0x00000230 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ID21 :1; /* Extended format identifier Bit 21 */\r
+ byte ID22 :1; /* Extended format identifier Bit 22 */\r
+ byte ID23 :1; /* Extended format identifier Bit 23 */\r
+ byte ID24 :1; /* Extended format identifier Bit 24 */\r
+ byte ID25 :1; /* Extended format identifier Bit 25 */\r
+ byte ID26 :1; /* Extended format identifier Bit 26 */\r
+ byte ID27 :1; /* Extended format identifier Bit 27 */\r
+ byte ID28 :1; /* Extended format identifier Bit 28 */\r
+ } Bits;\r
+ struct {\r
+ byte grpID_21 :8;\r
+ } MergedBits;\r
+} CAN3TXIDR0STR;\r
+extern volatile CAN3TXIDR0STR _CAN3TXIDR0 @(REG_BASE + 0x00000230);\r
+#define CAN3TXIDR0 _CAN3TXIDR0.Byte\r
+#define CAN3TXIDR0_ID21 _CAN3TXIDR0.Bits.ID21\r
+#define CAN3TXIDR0_ID22 _CAN3TXIDR0.Bits.ID22\r
+#define CAN3TXIDR0_ID23 _CAN3TXIDR0.Bits.ID23\r
+#define CAN3TXIDR0_ID24 _CAN3TXIDR0.Bits.ID24\r
+#define CAN3TXIDR0_ID25 _CAN3TXIDR0.Bits.ID25\r
+#define CAN3TXIDR0_ID26 _CAN3TXIDR0.Bits.ID26\r
+#define CAN3TXIDR0_ID27 _CAN3TXIDR0.Bits.ID27\r
+#define CAN3TXIDR0_ID28 _CAN3TXIDR0.Bits.ID28\r
+#define CAN3TXIDR0_ID_21 _CAN3TXIDR0.MergedBits.grpID_21\r
+#define CAN3TXIDR0_ID CAN3TXIDR0_ID_21\r
+\r
+\r
+/*** CAN3TXIDR1 - MSCAN 3 Transmit Identifier Register 1; 0x00000231 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ID15 :1; /* Extended format identifier Bit 15 */\r
+ byte ID16 :1; /* Extended format identifier Bit 16 */\r
+ byte ID17 :1; /* Extended format identifier Bit 17 */\r
+ byte IDE :1; /* ID Extended */\r
+ byte SRR :1; /* Substitute Remote Request */\r
+ byte ID18 :1; /* Extended format identifier Bit 18 */\r
+ byte ID19 :1; /* Extended format identifier Bit 19 */\r
+ byte ID20 :1; /* Extended format identifier Bit 20 */\r
+ } Bits;\r
+ struct {\r
+ byte grpID_15 :3;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpID_18 :3;\r
+ } MergedBits;\r
+} CAN3TXIDR1STR;\r
+extern volatile CAN3TXIDR1STR _CAN3TXIDR1 @(REG_BASE + 0x00000231);\r
+#define CAN3TXIDR1 _CAN3TXIDR1.Byte\r
+#define CAN3TXIDR1_ID15 _CAN3TXIDR1.Bits.ID15\r
+#define CAN3TXIDR1_ID16 _CAN3TXIDR1.Bits.ID16\r
+#define CAN3TXIDR1_ID17 _CAN3TXIDR1.Bits.ID17\r
+#define CAN3TXIDR1_IDE _CAN3TXIDR1.Bits.IDE\r
+#define CAN3TXIDR1_SRR _CAN3TXIDR1.Bits.SRR\r
+#define CAN3TXIDR1_ID18 _CAN3TXIDR1.Bits.ID18\r
+#define CAN3TXIDR1_ID19 _CAN3TXIDR1.Bits.ID19\r
+#define CAN3TXIDR1_ID20 _CAN3TXIDR1.Bits.ID20\r
+#define CAN3TXIDR1_ID_15 _CAN3TXIDR1.MergedBits.grpID_15\r
+#define CAN3TXIDR1_ID_18 _CAN3TXIDR1.MergedBits.grpID_18\r
+#define CAN3TXIDR1_ID CAN3TXIDR1_ID_15\r
+\r
+\r
+/*** CAN3TXIDR2 - MSCAN 3 Transmit Identifier Register 2; 0x00000232 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ID7 :1; /* Extended format identifier Bit 7 */\r
+ byte ID8 :1; /* Extended format identifier Bit 8 */\r
+ byte ID9 :1; /* Extended format identifier Bit 9 */\r
+ byte ID10 :1; /* Extended format identifier Bit 10 */\r
+ byte ID11 :1; /* Extended format identifier Bit 11 */\r
+ byte ID12 :1; /* Extended format identifier Bit 12 */\r
+ byte ID13 :1; /* Extended format identifier Bit 13 */\r
+ byte ID14 :1; /* Extended format identifier Bit 14 */\r
+ } Bits;\r
+ struct {\r
+ byte grpID_7 :8;\r
+ } MergedBits;\r
+} CAN3TXIDR2STR;\r
+extern volatile CAN3TXIDR2STR _CAN3TXIDR2 @(REG_BASE + 0x00000232);\r
+#define CAN3TXIDR2 _CAN3TXIDR2.Byte\r
+#define CAN3TXIDR2_ID7 _CAN3TXIDR2.Bits.ID7\r
+#define CAN3TXIDR2_ID8 _CAN3TXIDR2.Bits.ID8\r
+#define CAN3TXIDR2_ID9 _CAN3TXIDR2.Bits.ID9\r
+#define CAN3TXIDR2_ID10 _CAN3TXIDR2.Bits.ID10\r
+#define CAN3TXIDR2_ID11 _CAN3TXIDR2.Bits.ID11\r
+#define CAN3TXIDR2_ID12 _CAN3TXIDR2.Bits.ID12\r
+#define CAN3TXIDR2_ID13 _CAN3TXIDR2.Bits.ID13\r
+#define CAN3TXIDR2_ID14 _CAN3TXIDR2.Bits.ID14\r
+#define CAN3TXIDR2_ID_7 _CAN3TXIDR2.MergedBits.grpID_7\r
+#define CAN3TXIDR2_ID CAN3TXIDR2_ID_7\r
+\r
+\r
+/*** CAN3TXIDR3 - MSCAN 3 Transmit Identifier Register 3; 0x00000233 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte RTR :1; /* Remote Transmission Request */\r
+ byte ID0 :1; /* Extended format identifier Bit 0 */\r
+ byte ID1 :1; /* Extended format identifier Bit 1 */\r
+ byte ID2 :1; /* Extended format identifier Bit 2 */\r
+ byte ID3 :1; /* Extended format identifier Bit 3 */\r
+ byte ID4 :1; /* Extended format identifier Bit 4 */\r
+ byte ID5 :1; /* Extended format identifier Bit 5 */\r
+ byte ID6 :1; /* Extended format identifier Bit 6 */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte grpID :7;\r
+ } MergedBits;\r
+} CAN3TXIDR3STR;\r
+extern volatile CAN3TXIDR3STR _CAN3TXIDR3 @(REG_BASE + 0x00000233);\r
+#define CAN3TXIDR3 _CAN3TXIDR3.Byte\r
+#define CAN3TXIDR3_RTR _CAN3TXIDR3.Bits.RTR\r
+#define CAN3TXIDR3_ID0 _CAN3TXIDR3.Bits.ID0\r
+#define CAN3TXIDR3_ID1 _CAN3TXIDR3.Bits.ID1\r
+#define CAN3TXIDR3_ID2 _CAN3TXIDR3.Bits.ID2\r
+#define CAN3TXIDR3_ID3 _CAN3TXIDR3.Bits.ID3\r
+#define CAN3TXIDR3_ID4 _CAN3TXIDR3.Bits.ID4\r
+#define CAN3TXIDR3_ID5 _CAN3TXIDR3.Bits.ID5\r
+#define CAN3TXIDR3_ID6 _CAN3TXIDR3.Bits.ID6\r
+#define CAN3TXIDR3_ID _CAN3TXIDR3.MergedBits.grpID\r
+\r
+\r
+/*** CAN3TXDSR0 - MSCAN 3 Transmit Data Segment Register 0; 0x00000234 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN3TXDSR0STR;\r
+extern volatile CAN3TXDSR0STR _CAN3TXDSR0 @(REG_BASE + 0x00000234);\r
+#define CAN3TXDSR0 _CAN3TXDSR0.Byte\r
+#define CAN3TXDSR0_DB0 _CAN3TXDSR0.Bits.DB0\r
+#define CAN3TXDSR0_DB1 _CAN3TXDSR0.Bits.DB1\r
+#define CAN3TXDSR0_DB2 _CAN3TXDSR0.Bits.DB2\r
+#define CAN3TXDSR0_DB3 _CAN3TXDSR0.Bits.DB3\r
+#define CAN3TXDSR0_DB4 _CAN3TXDSR0.Bits.DB4\r
+#define CAN3TXDSR0_DB5 _CAN3TXDSR0.Bits.DB5\r
+#define CAN3TXDSR0_DB6 _CAN3TXDSR0.Bits.DB6\r
+#define CAN3TXDSR0_DB7 _CAN3TXDSR0.Bits.DB7\r
+#define CAN3TXDSR0_DB _CAN3TXDSR0.MergedBits.grpDB\r
+\r
+\r
+/*** CAN3TXDSR1 - MSCAN 3 Transmit Data Segment Register 1; 0x00000235 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN3TXDSR1STR;\r
+extern volatile CAN3TXDSR1STR _CAN3TXDSR1 @(REG_BASE + 0x00000235);\r
+#define CAN3TXDSR1 _CAN3TXDSR1.Byte\r
+#define CAN3TXDSR1_DB0 _CAN3TXDSR1.Bits.DB0\r
+#define CAN3TXDSR1_DB1 _CAN3TXDSR1.Bits.DB1\r
+#define CAN3TXDSR1_DB2 _CAN3TXDSR1.Bits.DB2\r
+#define CAN3TXDSR1_DB3 _CAN3TXDSR1.Bits.DB3\r
+#define CAN3TXDSR1_DB4 _CAN3TXDSR1.Bits.DB4\r
+#define CAN3TXDSR1_DB5 _CAN3TXDSR1.Bits.DB5\r
+#define CAN3TXDSR1_DB6 _CAN3TXDSR1.Bits.DB6\r
+#define CAN3TXDSR1_DB7 _CAN3TXDSR1.Bits.DB7\r
+#define CAN3TXDSR1_DB _CAN3TXDSR1.MergedBits.grpDB\r
+\r
+\r
+/*** CAN3TXDSR2 - MSCAN 3 Transmit Data Segment Register 2; 0x00000236 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN3TXDSR2STR;\r
+extern volatile CAN3TXDSR2STR _CAN3TXDSR2 @(REG_BASE + 0x00000236);\r
+#define CAN3TXDSR2 _CAN3TXDSR2.Byte\r
+#define CAN3TXDSR2_DB0 _CAN3TXDSR2.Bits.DB0\r
+#define CAN3TXDSR2_DB1 _CAN3TXDSR2.Bits.DB1\r
+#define CAN3TXDSR2_DB2 _CAN3TXDSR2.Bits.DB2\r
+#define CAN3TXDSR2_DB3 _CAN3TXDSR2.Bits.DB3\r
+#define CAN3TXDSR2_DB4 _CAN3TXDSR2.Bits.DB4\r
+#define CAN3TXDSR2_DB5 _CAN3TXDSR2.Bits.DB5\r
+#define CAN3TXDSR2_DB6 _CAN3TXDSR2.Bits.DB6\r
+#define CAN3TXDSR2_DB7 _CAN3TXDSR2.Bits.DB7\r
+#define CAN3TXDSR2_DB _CAN3TXDSR2.MergedBits.grpDB\r
+\r
+\r
+/*** CAN3TXDSR3 - MSCAN 3 Transmit Data Segment Register 3; 0x00000237 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN3TXDSR3STR;\r
+extern volatile CAN3TXDSR3STR _CAN3TXDSR3 @(REG_BASE + 0x00000237);\r
+#define CAN3TXDSR3 _CAN3TXDSR3.Byte\r
+#define CAN3TXDSR3_DB0 _CAN3TXDSR3.Bits.DB0\r
+#define CAN3TXDSR3_DB1 _CAN3TXDSR3.Bits.DB1\r
+#define CAN3TXDSR3_DB2 _CAN3TXDSR3.Bits.DB2\r
+#define CAN3TXDSR3_DB3 _CAN3TXDSR3.Bits.DB3\r
+#define CAN3TXDSR3_DB4 _CAN3TXDSR3.Bits.DB4\r
+#define CAN3TXDSR3_DB5 _CAN3TXDSR3.Bits.DB5\r
+#define CAN3TXDSR3_DB6 _CAN3TXDSR3.Bits.DB6\r
+#define CAN3TXDSR3_DB7 _CAN3TXDSR3.Bits.DB7\r
+#define CAN3TXDSR3_DB _CAN3TXDSR3.MergedBits.grpDB\r
+\r
+\r
+/*** CAN3TXDSR4 - MSCAN 3 Transmit Data Segment Register 4; 0x00000238 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN3TXDSR4STR;\r
+extern volatile CAN3TXDSR4STR _CAN3TXDSR4 @(REG_BASE + 0x00000238);\r
+#define CAN3TXDSR4 _CAN3TXDSR4.Byte\r
+#define CAN3TXDSR4_DB0 _CAN3TXDSR4.Bits.DB0\r
+#define CAN3TXDSR4_DB1 _CAN3TXDSR4.Bits.DB1\r
+#define CAN3TXDSR4_DB2 _CAN3TXDSR4.Bits.DB2\r
+#define CAN3TXDSR4_DB3 _CAN3TXDSR4.Bits.DB3\r
+#define CAN3TXDSR4_DB4 _CAN3TXDSR4.Bits.DB4\r
+#define CAN3TXDSR4_DB5 _CAN3TXDSR4.Bits.DB5\r
+#define CAN3TXDSR4_DB6 _CAN3TXDSR4.Bits.DB6\r
+#define CAN3TXDSR4_DB7 _CAN3TXDSR4.Bits.DB7\r
+#define CAN3TXDSR4_DB _CAN3TXDSR4.MergedBits.grpDB\r
+\r
+\r
+/*** CAN3TXDSR5 - MSCAN 3 Transmit Data Segment Register 5; 0x00000239 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN3TXDSR5STR;\r
+extern volatile CAN3TXDSR5STR _CAN3TXDSR5 @(REG_BASE + 0x00000239);\r
+#define CAN3TXDSR5 _CAN3TXDSR5.Byte\r
+#define CAN3TXDSR5_DB0 _CAN3TXDSR5.Bits.DB0\r
+#define CAN3TXDSR5_DB1 _CAN3TXDSR5.Bits.DB1\r
+#define CAN3TXDSR5_DB2 _CAN3TXDSR5.Bits.DB2\r
+#define CAN3TXDSR5_DB3 _CAN3TXDSR5.Bits.DB3\r
+#define CAN3TXDSR5_DB4 _CAN3TXDSR5.Bits.DB4\r
+#define CAN3TXDSR5_DB5 _CAN3TXDSR5.Bits.DB5\r
+#define CAN3TXDSR5_DB6 _CAN3TXDSR5.Bits.DB6\r
+#define CAN3TXDSR5_DB7 _CAN3TXDSR5.Bits.DB7\r
+#define CAN3TXDSR5_DB _CAN3TXDSR5.MergedBits.grpDB\r
+\r
+\r
+/*** CAN3TXDSR6 - MSCAN 3 Transmit Data Segment Register 6; 0x0000023A ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN3TXDSR6STR;\r
+extern volatile CAN3TXDSR6STR _CAN3TXDSR6 @(REG_BASE + 0x0000023A);\r
+#define CAN3TXDSR6 _CAN3TXDSR6.Byte\r
+#define CAN3TXDSR6_DB0 _CAN3TXDSR6.Bits.DB0\r
+#define CAN3TXDSR6_DB1 _CAN3TXDSR6.Bits.DB1\r
+#define CAN3TXDSR6_DB2 _CAN3TXDSR6.Bits.DB2\r
+#define CAN3TXDSR6_DB3 _CAN3TXDSR6.Bits.DB3\r
+#define CAN3TXDSR6_DB4 _CAN3TXDSR6.Bits.DB4\r
+#define CAN3TXDSR6_DB5 _CAN3TXDSR6.Bits.DB5\r
+#define CAN3TXDSR6_DB6 _CAN3TXDSR6.Bits.DB6\r
+#define CAN3TXDSR6_DB7 _CAN3TXDSR6.Bits.DB7\r
+#define CAN3TXDSR6_DB _CAN3TXDSR6.MergedBits.grpDB\r
+\r
+\r
+/*** CAN3TXDSR7 - MSCAN 3 Transmit Data Segment Register 7; 0x0000023B ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN3TXDSR7STR;\r
+extern volatile CAN3TXDSR7STR _CAN3TXDSR7 @(REG_BASE + 0x0000023B);\r
+#define CAN3TXDSR7 _CAN3TXDSR7.Byte\r
+#define CAN3TXDSR7_DB0 _CAN3TXDSR7.Bits.DB0\r
+#define CAN3TXDSR7_DB1 _CAN3TXDSR7.Bits.DB1\r
+#define CAN3TXDSR7_DB2 _CAN3TXDSR7.Bits.DB2\r
+#define CAN3TXDSR7_DB3 _CAN3TXDSR7.Bits.DB3\r
+#define CAN3TXDSR7_DB4 _CAN3TXDSR7.Bits.DB4\r
+#define CAN3TXDSR7_DB5 _CAN3TXDSR7.Bits.DB5\r
+#define CAN3TXDSR7_DB6 _CAN3TXDSR7.Bits.DB6\r
+#define CAN3TXDSR7_DB7 _CAN3TXDSR7.Bits.DB7\r
+#define CAN3TXDSR7_DB _CAN3TXDSR7.MergedBits.grpDB\r
+\r
+\r
+/*** CAN3TXDLR - MSCAN 3 Transmit Data Length Register; 0x0000023C ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DLC0 :1; /* Data Length Code Bit 0 */\r
+ byte DLC1 :1; /* Data Length Code Bit 1 */\r
+ byte DLC2 :1; /* Data Length Code Bit 2 */\r
+ byte DLC3 :1; /* Data Length Code Bit 3 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpDLC :4;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CAN3TXDLRSTR;\r
+extern volatile CAN3TXDLRSTR _CAN3TXDLR @(REG_BASE + 0x0000023C);\r
+#define CAN3TXDLR _CAN3TXDLR.Byte\r
+#define CAN3TXDLR_DLC0 _CAN3TXDLR.Bits.DLC0\r
+#define CAN3TXDLR_DLC1 _CAN3TXDLR.Bits.DLC1\r
+#define CAN3TXDLR_DLC2 _CAN3TXDLR.Bits.DLC2\r
+#define CAN3TXDLR_DLC3 _CAN3TXDLR.Bits.DLC3\r
+#define CAN3TXDLR_DLC _CAN3TXDLR.MergedBits.grpDLC\r
+\r
+\r
+/*** CAN3TXTBPR - MSCAN 3 Transmit Buffer Priority; 0x0000023F ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PRIO0 :1; /* Transmit Buffer Priority Bit 0 */\r
+ byte PRIO1 :1; /* Transmit Buffer Priority Bit 1 */\r
+ byte PRIO2 :1; /* Transmit Buffer Priority Bit 2 */\r
+ byte PRIO3 :1; /* Transmit Buffer Priority Bit 3 */\r
+ byte PRIO4 :1; /* Transmit Buffer Priority Bit 4 */\r
+ byte PRIO5 :1; /* Transmit Buffer Priority Bit 5 */\r
+ byte PRIO6 :1; /* Transmit Buffer Priority Bit 6 */\r
+ byte PRIO7 :1; /* Transmit Buffer Priority Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpPRIO :8;\r
+ } MergedBits;\r
+} CAN3TXTBPRSTR;\r
+extern volatile CAN3TXTBPRSTR _CAN3TXTBPR @(REG_BASE + 0x0000023F);\r
+#define CAN3TXTBPR _CAN3TXTBPR.Byte\r
+#define CAN3TXTBPR_PRIO0 _CAN3TXTBPR.Bits.PRIO0\r
+#define CAN3TXTBPR_PRIO1 _CAN3TXTBPR.Bits.PRIO1\r
+#define CAN3TXTBPR_PRIO2 _CAN3TXTBPR.Bits.PRIO2\r
+#define CAN3TXTBPR_PRIO3 _CAN3TXTBPR.Bits.PRIO3\r
+#define CAN3TXTBPR_PRIO4 _CAN3TXTBPR.Bits.PRIO4\r
+#define CAN3TXTBPR_PRIO5 _CAN3TXTBPR.Bits.PRIO5\r
+#define CAN3TXTBPR_PRIO6 _CAN3TXTBPR.Bits.PRIO6\r
+#define CAN3TXTBPR_PRIO7 _CAN3TXTBPR.Bits.PRIO7\r
+#define CAN3TXTBPR_PRIO _CAN3TXTBPR.MergedBits.grpPRIO\r
+\r
+\r
+/*** PTT - Port T I/O Register; 0x00000240 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PTT0 :1; /* Port T Bit 0 */\r
+ byte PTT1 :1; /* Port T Bit 1 */\r
+ byte PTT2 :1; /* Port T Bit 2 */\r
+ byte PTT3 :1; /* Port T Bit 3 */\r
+ byte PTT4 :1; /* Port T Bit 4 */\r
+ byte PTT5 :1; /* Port T Bit 5 */\r
+ byte PTT6 :1; /* Port T Bit 6 */\r
+ byte PTT7 :1; /* Port T Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpPTT :8;\r
+ } MergedBits;\r
+} PTTSTR;\r
+extern volatile PTTSTR _PTT @(REG_BASE + 0x00000240);\r
+#define PTT _PTT.Byte\r
+#define PTT_PTT0 _PTT.Bits.PTT0\r
+#define PTT_PTT1 _PTT.Bits.PTT1\r
+#define PTT_PTT2 _PTT.Bits.PTT2\r
+#define PTT_PTT3 _PTT.Bits.PTT3\r
+#define PTT_PTT4 _PTT.Bits.PTT4\r
+#define PTT_PTT5 _PTT.Bits.PTT5\r
+#define PTT_PTT6 _PTT.Bits.PTT6\r
+#define PTT_PTT7 _PTT.Bits.PTT7\r
+#define PTT_PTT _PTT.MergedBits.grpPTT\r
+\r
+\r
+/*** PTIT - Port T Input; 0x00000241 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PTIT0 :1; /* Port T Bit 0 */\r
+ byte PTIT1 :1; /* Port T Bit 1 */\r
+ byte PTIT2 :1; /* Port T Bit 2 */\r
+ byte PTIT3 :1; /* Port T Bit 3 */\r
+ byte PTIT4 :1; /* Port T Bit 4 */\r
+ byte PTIT5 :1; /* Port T Bit 5 */\r
+ byte PTIT6 :1; /* Port T Bit 6 */\r
+ byte PTIT7 :1; /* Port T Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpPTIT :8;\r
+ } MergedBits;\r
+} PTITSTR;\r
+extern volatile PTITSTR _PTIT @(REG_BASE + 0x00000241);\r
+#define PTIT _PTIT.Byte\r
+#define PTIT_PTIT0 _PTIT.Bits.PTIT0\r
+#define PTIT_PTIT1 _PTIT.Bits.PTIT1\r
+#define PTIT_PTIT2 _PTIT.Bits.PTIT2\r
+#define PTIT_PTIT3 _PTIT.Bits.PTIT3\r
+#define PTIT_PTIT4 _PTIT.Bits.PTIT4\r
+#define PTIT_PTIT5 _PTIT.Bits.PTIT5\r
+#define PTIT_PTIT6 _PTIT.Bits.PTIT6\r
+#define PTIT_PTIT7 _PTIT.Bits.PTIT7\r
+#define PTIT_PTIT _PTIT.MergedBits.grpPTIT\r
+\r
+\r
+/*** DDRT - Port T Data Direction Register; 0x00000242 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DDRT0 :1; /* Data Direction Port T Bit 0 */\r
+ byte DDRT1 :1; /* Data Direction Port T Bit 1 */\r
+ byte DDRT2 :1; /* Data Direction Port T Bit 2 */\r
+ byte DDRT3 :1; /* Data Direction Port T Bit 3 */\r
+ byte DDRT4 :1; /* Data Direction Port T Bit 4 */\r
+ byte DDRT5 :1; /* Data Direction Port T Bit 5 */\r
+ byte DDRT6 :1; /* Data Direction Port T Bit 6 */\r
+ byte DDRT7 :1; /* Data Direction Port T Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDDRT :8;\r
+ } MergedBits;\r
+} DDRTSTR;\r
+extern volatile DDRTSTR _DDRT @(REG_BASE + 0x00000242);\r
+#define DDRT _DDRT.Byte\r
+#define DDRT_DDRT0 _DDRT.Bits.DDRT0\r
+#define DDRT_DDRT1 _DDRT.Bits.DDRT1\r
+#define DDRT_DDRT2 _DDRT.Bits.DDRT2\r
+#define DDRT_DDRT3 _DDRT.Bits.DDRT3\r
+#define DDRT_DDRT4 _DDRT.Bits.DDRT4\r
+#define DDRT_DDRT5 _DDRT.Bits.DDRT5\r
+#define DDRT_DDRT6 _DDRT.Bits.DDRT6\r
+#define DDRT_DDRT7 _DDRT.Bits.DDRT7\r
+#define DDRT_DDRT _DDRT.MergedBits.grpDDRT\r
+\r
+\r
+/*** RDRT - Port T Reduced Drive Register; 0x00000243 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte RDRT0 :1; /* Reduced Drive Port T Bit 0 */\r
+ byte RDRT1 :1; /* Reduced Drive Port T Bit 1 */\r
+ byte RDRT2 :1; /* Reduced Drive Port T Bit 2 */\r
+ byte RDRT3 :1; /* Reduced Drive Port T Bit 3 */\r
+ byte RDRT4 :1; /* Reduced Drive Port T Bit 4 */\r
+ byte RDRT5 :1; /* Reduced Drive Port T Bit 5 */\r
+ byte RDRT6 :1; /* Reduced Drive Port T Bit 6 */\r
+ byte RDRT7 :1; /* Reduced Drive Port T Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpRDRT :8;\r
+ } MergedBits;\r
+} RDRTSTR;\r
+extern volatile RDRTSTR _RDRT @(REG_BASE + 0x00000243);\r
+#define RDRT _RDRT.Byte\r
+#define RDRT_RDRT0 _RDRT.Bits.RDRT0\r
+#define RDRT_RDRT1 _RDRT.Bits.RDRT1\r
+#define RDRT_RDRT2 _RDRT.Bits.RDRT2\r
+#define RDRT_RDRT3 _RDRT.Bits.RDRT3\r
+#define RDRT_RDRT4 _RDRT.Bits.RDRT4\r
+#define RDRT_RDRT5 _RDRT.Bits.RDRT5\r
+#define RDRT_RDRT6 _RDRT.Bits.RDRT6\r
+#define RDRT_RDRT7 _RDRT.Bits.RDRT7\r
+#define RDRT_RDRT _RDRT.MergedBits.grpRDRT\r
+\r
+\r
+/*** PERT - Port T Pull Device Enable Register; 0x00000244 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PERT0 :1; /* Pull Device Enable Port T Bit 0 */\r
+ byte PERT1 :1; /* Pull Device Enable Port T Bit 1 */\r
+ byte PERT2 :1; /* Pull Device Enable Port T Bit 2 */\r
+ byte PERT3 :1; /* Pull Device Enable Port T Bit 3 */\r
+ byte PERT4 :1; /* Pull Device Enable Port T Bit 4 */\r
+ byte PERT5 :1; /* Pull Device Enable Port T Bit 5 */\r
+ byte PERT6 :1; /* Pull Device Enable Port T Bit 6 */\r
+ byte PERT7 :1; /* Pull Device Enable Port T Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpPERT :8;\r
+ } MergedBits;\r
+} PERTSTR;\r
+extern volatile PERTSTR _PERT @(REG_BASE + 0x00000244);\r
+#define PERT _PERT.Byte\r
+#define PERT_PERT0 _PERT.Bits.PERT0\r
+#define PERT_PERT1 _PERT.Bits.PERT1\r
+#define PERT_PERT2 _PERT.Bits.PERT2\r
+#define PERT_PERT3 _PERT.Bits.PERT3\r
+#define PERT_PERT4 _PERT.Bits.PERT4\r
+#define PERT_PERT5 _PERT.Bits.PERT5\r
+#define PERT_PERT6 _PERT.Bits.PERT6\r
+#define PERT_PERT7 _PERT.Bits.PERT7\r
+#define PERT_PERT _PERT.MergedBits.grpPERT\r
+\r
+\r
+/*** PPST - Port T Polarity Select Register; 0x00000245 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PPST0 :1; /* Pull Select Port T Bit 0 */\r
+ byte PPST1 :1; /* Pull Select Port T Bit 1 */\r
+ byte PPST2 :1; /* Pull Select Port T Bit 2 */\r
+ byte PPST3 :1; /* Pull Select Port T Bit 3 */\r
+ byte PPST4 :1; /* Pull Select Port T Bit 4 */\r
+ byte PPST5 :1; /* Pull Select Port T Bit 5 */\r
+ byte PPST6 :1; /* Pull Select Port T Bit 6 */\r
+ byte PPST7 :1; /* Pull Select Port T Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpPPST :8;\r
+ } MergedBits;\r
+} PPSTSTR;\r
+extern volatile PPSTSTR _PPST @(REG_BASE + 0x00000245);\r
+#define PPST _PPST.Byte\r
+#define PPST_PPST0 _PPST.Bits.PPST0\r
+#define PPST_PPST1 _PPST.Bits.PPST1\r
+#define PPST_PPST2 _PPST.Bits.PPST2\r
+#define PPST_PPST3 _PPST.Bits.PPST3\r
+#define PPST_PPST4 _PPST.Bits.PPST4\r
+#define PPST_PPST5 _PPST.Bits.PPST5\r
+#define PPST_PPST6 _PPST.Bits.PPST6\r
+#define PPST_PPST7 _PPST.Bits.PPST7\r
+#define PPST_PPST _PPST.MergedBits.grpPPST\r
+\r
+\r
+/*** PTS - Port S I/O Register; 0x00000248 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PTS0 :1; /* Port S Bit 0 */\r
+ byte PTS1 :1; /* Port S Bit 1 */\r
+ byte PTS2 :1; /* Port S Bit 2 */\r
+ byte PTS3 :1; /* Port S Bit 3 */\r
+ byte PTS4 :1; /* Port S Bit 4 */\r
+ byte PTS5 :1; /* Port S Bit 5 */\r
+ byte PTS6 :1; /* Port S Bit 6 */\r
+ byte PTS7 :1; /* Port S Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpPTS :8;\r
+ } MergedBits;\r
+} PTSSTR;\r
+extern volatile PTSSTR _PTS @(REG_BASE + 0x00000248);\r
+#define PTS _PTS.Byte\r
+#define PTS_PTS0 _PTS.Bits.PTS0\r
+#define PTS_PTS1 _PTS.Bits.PTS1\r
+#define PTS_PTS2 _PTS.Bits.PTS2\r
+#define PTS_PTS3 _PTS.Bits.PTS3\r
+#define PTS_PTS4 _PTS.Bits.PTS4\r
+#define PTS_PTS5 _PTS.Bits.PTS5\r
+#define PTS_PTS6 _PTS.Bits.PTS6\r
+#define PTS_PTS7 _PTS.Bits.PTS7\r
+#define PTS_PTS _PTS.MergedBits.grpPTS\r
+\r
+\r
+/*** PTIS - Port S Input; 0x00000249 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PTIS0 :1; /* Port S Bit 0 */\r
+ byte PTIS1 :1; /* Port S Bit 1 */\r
+ byte PTIS2 :1; /* Port S Bit 2 */\r
+ byte PTIS3 :1; /* Port S Bit 3 */\r
+ byte PTIS4 :1; /* Port S Bit 4 */\r
+ byte PTIS5 :1; /* Port S Bit 5 */\r
+ byte PTIS6 :1; /* Port S Bit 6 */\r
+ byte PTIS7 :1; /* Port S Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpPTIS :8;\r
+ } MergedBits;\r
+} PTISSTR;\r
+extern volatile PTISSTR _PTIS @(REG_BASE + 0x00000249);\r
+#define PTIS _PTIS.Byte\r
+#define PTIS_PTIS0 _PTIS.Bits.PTIS0\r
+#define PTIS_PTIS1 _PTIS.Bits.PTIS1\r
+#define PTIS_PTIS2 _PTIS.Bits.PTIS2\r
+#define PTIS_PTIS3 _PTIS.Bits.PTIS3\r
+#define PTIS_PTIS4 _PTIS.Bits.PTIS4\r
+#define PTIS_PTIS5 _PTIS.Bits.PTIS5\r
+#define PTIS_PTIS6 _PTIS.Bits.PTIS6\r
+#define PTIS_PTIS7 _PTIS.Bits.PTIS7\r
+#define PTIS_PTIS _PTIS.MergedBits.grpPTIS\r
+\r
+\r
+/*** DDRS - Port S Data Direction Register; 0x0000024A ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DDRS0 :1; /* Data Direction Port S Bit 0 */\r
+ byte DDRS1 :1; /* Data Direction Port S Bit 1 */\r
+ byte DDRS2 :1; /* Data Direction Port S Bit 2 */\r
+ byte DDRS3 :1; /* Data Direction Port S Bit 3 */\r
+ byte DDRS4 :1; /* Data Direction Port S Bit 4 */\r
+ byte DDRS5 :1; /* Data Direction Port S Bit 5 */\r
+ byte DDRS6 :1; /* Data Direction Port S Bit 6 */\r
+ byte DDRS7 :1; /* Data Direction Port S Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDDRS :8;\r
+ } MergedBits;\r
+} DDRSSTR;\r
+extern volatile DDRSSTR _DDRS @(REG_BASE + 0x0000024A);\r
+#define DDRS _DDRS.Byte\r
+#define DDRS_DDRS0 _DDRS.Bits.DDRS0\r
+#define DDRS_DDRS1 _DDRS.Bits.DDRS1\r
+#define DDRS_DDRS2 _DDRS.Bits.DDRS2\r
+#define DDRS_DDRS3 _DDRS.Bits.DDRS3\r
+#define DDRS_DDRS4 _DDRS.Bits.DDRS4\r
+#define DDRS_DDRS5 _DDRS.Bits.DDRS5\r
+#define DDRS_DDRS6 _DDRS.Bits.DDRS6\r
+#define DDRS_DDRS7 _DDRS.Bits.DDRS7\r
+#define DDRS_DDRS _DDRS.MergedBits.grpDDRS\r
+\r
+\r
+/*** RDRS - Port S Reduced Drive Register; 0x0000024B ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte RDRS0 :1; /* Reduced Drive Port S Bit 0 */\r
+ byte RDRS1 :1; /* Reduced Drive Port S Bit 1 */\r
+ byte RDRS2 :1; /* Reduced Drive Port S Bit 2 */\r
+ byte RDRS3 :1; /* Reduced Drive Port S Bit 3 */\r
+ byte RDRS4 :1; /* Reduced Drive Port S Bit 4 */\r
+ byte RDRS5 :1; /* Reduced Drive Port S Bit 5 */\r
+ byte RDRS6 :1; /* Reduced Drive Port S Bit 6 */\r
+ byte RDRS7 :1; /* Reduced Drive Port S Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpRDRS :8;\r
+ } MergedBits;\r
+} RDRSSTR;\r
+extern volatile RDRSSTR _RDRS @(REG_BASE + 0x0000024B);\r
+#define RDRS _RDRS.Byte\r
+#define RDRS_RDRS0 _RDRS.Bits.RDRS0\r
+#define RDRS_RDRS1 _RDRS.Bits.RDRS1\r
+#define RDRS_RDRS2 _RDRS.Bits.RDRS2\r
+#define RDRS_RDRS3 _RDRS.Bits.RDRS3\r
+#define RDRS_RDRS4 _RDRS.Bits.RDRS4\r
+#define RDRS_RDRS5 _RDRS.Bits.RDRS5\r
+#define RDRS_RDRS6 _RDRS.Bits.RDRS6\r
+#define RDRS_RDRS7 _RDRS.Bits.RDRS7\r
+#define RDRS_RDRS _RDRS.MergedBits.grpRDRS\r
+\r
+\r
+/*** PERS - Port S Pull Device Enable Register; 0x0000024C ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PERS0 :1; /* Pull Device Enable Port S Bit 0 */\r
+ byte PERS1 :1; /* Pull Device Enable Port S Bit 1 */\r
+ byte PERS2 :1; /* Pull Device Enable Port S Bit 2 */\r
+ byte PERS3 :1; /* Pull Device Enable Port S Bit 3 */\r
+ byte PERS4 :1; /* Pull Device Enable Port S Bit 4 */\r
+ byte PERS5 :1; /* Pull Device Enable Port S Bit 5 */\r
+ byte PERS6 :1; /* Pull Device Enable Port S Bit 6 */\r
+ byte PERS7 :1; /* Pull Device Enable Port S Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpPERS :8;\r
+ } MergedBits;\r
+} PERSSTR;\r
+extern volatile PERSSTR _PERS @(REG_BASE + 0x0000024C);\r
+#define PERS _PERS.Byte\r
+#define PERS_PERS0 _PERS.Bits.PERS0\r
+#define PERS_PERS1 _PERS.Bits.PERS1\r
+#define PERS_PERS2 _PERS.Bits.PERS2\r
+#define PERS_PERS3 _PERS.Bits.PERS3\r
+#define PERS_PERS4 _PERS.Bits.PERS4\r
+#define PERS_PERS5 _PERS.Bits.PERS5\r
+#define PERS_PERS6 _PERS.Bits.PERS6\r
+#define PERS_PERS7 _PERS.Bits.PERS7\r
+#define PERS_PERS _PERS.MergedBits.grpPERS\r
+\r
+\r
+/*** PPSS - Port S Polarity Select Register; 0x0000024D ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PPSS0 :1; /* Pull Select Port S Bit 0 */\r
+ byte PPSS1 :1; /* Pull Select Port S Bit 1 */\r
+ byte PPSS2 :1; /* Pull Select Port S Bit 2 */\r
+ byte PPSS3 :1; /* Pull Select Port S Bit 3 */\r
+ byte PPSS4 :1; /* Pull Select Port S Bit 4 */\r
+ byte PPSS5 :1; /* Pull Select Port S Bit 5 */\r
+ byte PPSS6 :1; /* Pull Select Port S Bit 6 */\r
+ byte PPSS7 :1; /* Pull Select Port S Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpPPSS :8;\r
+ } MergedBits;\r
+} PPSSSTR;\r
+extern volatile PPSSSTR _PPSS @(REG_BASE + 0x0000024D);\r
+#define PPSS _PPSS.Byte\r
+#define PPSS_PPSS0 _PPSS.Bits.PPSS0\r
+#define PPSS_PPSS1 _PPSS.Bits.PPSS1\r
+#define PPSS_PPSS2 _PPSS.Bits.PPSS2\r
+#define PPSS_PPSS3 _PPSS.Bits.PPSS3\r
+#define PPSS_PPSS4 _PPSS.Bits.PPSS4\r
+#define PPSS_PPSS5 _PPSS.Bits.PPSS5\r
+#define PPSS_PPSS6 _PPSS.Bits.PPSS6\r
+#define PPSS_PPSS7 _PPSS.Bits.PPSS7\r
+#define PPSS_PPSS _PPSS.MergedBits.grpPPSS\r
+\r
+\r
+/*** WOMS - Port S Wired-Or Mode Register; 0x0000024E ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte WOMS0 :1; /* Wired-Or Mode Port S Bit 0 */\r
+ byte WOMS1 :1; /* Wired-Or Mode Port S Bit 1 */\r
+ byte WOMS2 :1; /* Wired-Or Mode Port S Bit 2 */\r
+ byte WOMS3 :1; /* Wired-Or Mode Port S Bit 3 */\r
+ byte WOMS4 :1; /* Wired-Or Mode Port S Bit 4 */\r
+ byte WOMS5 :1; /* Wired-Or Mode Port S Bit 5 */\r
+ byte WOMS6 :1; /* Wired-Or Mode Port S Bit 6 */\r
+ byte WOMS7 :1; /* Wired-Or Mode Port S Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpWOMS :8;\r
+ } MergedBits;\r
+} WOMSSTR;\r
+extern volatile WOMSSTR _WOMS @(REG_BASE + 0x0000024E);\r
+#define WOMS _WOMS.Byte\r
+#define WOMS_WOMS0 _WOMS.Bits.WOMS0\r
+#define WOMS_WOMS1 _WOMS.Bits.WOMS1\r
+#define WOMS_WOMS2 _WOMS.Bits.WOMS2\r
+#define WOMS_WOMS3 _WOMS.Bits.WOMS3\r
+#define WOMS_WOMS4 _WOMS.Bits.WOMS4\r
+#define WOMS_WOMS5 _WOMS.Bits.WOMS5\r
+#define WOMS_WOMS6 _WOMS.Bits.WOMS6\r
+#define WOMS_WOMS7 _WOMS.Bits.WOMS7\r
+#define WOMS_WOMS _WOMS.MergedBits.grpWOMS\r
+\r
+\r
+/*** PTM - Port M I/O Register; 0x00000250 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PTM0 :1; /* Port T Bit 0 */\r
+ byte PTM1 :1; /* Port T Bit 1 */\r
+ byte PTM2 :1; /* Port T Bit 2 */\r
+ byte PTM3 :1; /* Port T Bit 3 */\r
+ byte PTM4 :1; /* Port T Bit 4 */\r
+ byte PTM5 :1; /* Port T Bit 5 */\r
+ byte PTM6 :1; /* Port T Bit 6 */\r
+ byte PTM7 :1; /* Port T Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpPTM :8;\r
+ } MergedBits;\r
+} PTMSTR;\r
+extern volatile PTMSTR _PTM @(REG_BASE + 0x00000250);\r
+#define PTM _PTM.Byte\r
+#define PTM_PTM0 _PTM.Bits.PTM0\r
+#define PTM_PTM1 _PTM.Bits.PTM1\r
+#define PTM_PTM2 _PTM.Bits.PTM2\r
+#define PTM_PTM3 _PTM.Bits.PTM3\r
+#define PTM_PTM4 _PTM.Bits.PTM4\r
+#define PTM_PTM5 _PTM.Bits.PTM5\r
+#define PTM_PTM6 _PTM.Bits.PTM6\r
+#define PTM_PTM7 _PTM.Bits.PTM7\r
+#define PTM_PTM _PTM.MergedBits.grpPTM\r
+\r
+\r
+/*** PTIM - Port M Input; 0x00000251 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PTIM0 :1; /* Port M Bit 0 */\r
+ byte PTIM1 :1; /* Port M Bit 1 */\r
+ byte PTIM2 :1; /* Port M Bit 2 */\r
+ byte PTIM3 :1; /* Port M Bit 3 */\r
+ byte PTIM4 :1; /* Port M Bit 4 */\r
+ byte PTIM5 :1; /* Port M Bit 5 */\r
+ byte PTIM6 :1; /* Port M Bit 6 */\r
+ byte PTIM7 :1; /* Port M Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpPTIM :8;\r
+ } MergedBits;\r
+} PTIMSTR;\r
+extern volatile PTIMSTR _PTIM @(REG_BASE + 0x00000251);\r
+#define PTIM _PTIM.Byte\r
+#define PTIM_PTIM0 _PTIM.Bits.PTIM0\r
+#define PTIM_PTIM1 _PTIM.Bits.PTIM1\r
+#define PTIM_PTIM2 _PTIM.Bits.PTIM2\r
+#define PTIM_PTIM3 _PTIM.Bits.PTIM3\r
+#define PTIM_PTIM4 _PTIM.Bits.PTIM4\r
+#define PTIM_PTIM5 _PTIM.Bits.PTIM5\r
+#define PTIM_PTIM6 _PTIM.Bits.PTIM6\r
+#define PTIM_PTIM7 _PTIM.Bits.PTIM7\r
+#define PTIM_PTIM _PTIM.MergedBits.grpPTIM\r
+\r
+\r
+/*** DDRM - Port M Data Direction Register; 0x00000252 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DDRM0 :1; /* Data Direction Port M Bit 0 */\r
+ byte DDRM1 :1; /* Data Direction Port M Bit 1 */\r
+ byte DDRM2 :1; /* Data Direction Port M Bit 2 */\r
+ byte DDRM3 :1; /* Data Direction Port M Bit 3 */\r
+ byte DDRM4 :1; /* Data Direction Port M Bit 4 */\r
+ byte DDRM5 :1; /* Data Direction Port M Bit 5 */\r
+ byte DDRM6 :1; /* Data Direction Port M Bit 6 */\r
+ byte DDRM7 :1; /* Data Direction Port M Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDDRM :8;\r
+ } MergedBits;\r
+} DDRMSTR;\r
+extern volatile DDRMSTR _DDRM @(REG_BASE + 0x00000252);\r
+#define DDRM _DDRM.Byte\r
+#define DDRM_DDRM0 _DDRM.Bits.DDRM0\r
+#define DDRM_DDRM1 _DDRM.Bits.DDRM1\r
+#define DDRM_DDRM2 _DDRM.Bits.DDRM2\r
+#define DDRM_DDRM3 _DDRM.Bits.DDRM3\r
+#define DDRM_DDRM4 _DDRM.Bits.DDRM4\r
+#define DDRM_DDRM5 _DDRM.Bits.DDRM5\r
+#define DDRM_DDRM6 _DDRM.Bits.DDRM6\r
+#define DDRM_DDRM7 _DDRM.Bits.DDRM7\r
+#define DDRM_DDRM _DDRM.MergedBits.grpDDRM\r
+\r
+\r
+/*** RDRM - Port M Reduced Drive Register; 0x00000253 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte RDRM0 :1; /* Reduced Drive Port M Bit 0 */\r
+ byte RDRM1 :1; /* Reduced Drive Port M Bit 1 */\r
+ byte RDRM2 :1; /* Reduced Drive Port M Bit 2 */\r
+ byte RDRM3 :1; /* Reduced Drive Port M Bit 3 */\r
+ byte RDRM4 :1; /* Reduced Drive Port M Bit 4 */\r
+ byte RDRM5 :1; /* Reduced Drive Port M Bit 5 */\r
+ byte RDRM6 :1; /* Reduced Drive Port M Bit 6 */\r
+ byte RDRM7 :1; /* Reduced Drive Port M Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpRDRM :8;\r
+ } MergedBits;\r
+} RDRMSTR;\r
+extern volatile RDRMSTR _RDRM @(REG_BASE + 0x00000253);\r
+#define RDRM _RDRM.Byte\r
+#define RDRM_RDRM0 _RDRM.Bits.RDRM0\r
+#define RDRM_RDRM1 _RDRM.Bits.RDRM1\r
+#define RDRM_RDRM2 _RDRM.Bits.RDRM2\r
+#define RDRM_RDRM3 _RDRM.Bits.RDRM3\r
+#define RDRM_RDRM4 _RDRM.Bits.RDRM4\r
+#define RDRM_RDRM5 _RDRM.Bits.RDRM5\r
+#define RDRM_RDRM6 _RDRM.Bits.RDRM6\r
+#define RDRM_RDRM7 _RDRM.Bits.RDRM7\r
+#define RDRM_RDRM _RDRM.MergedBits.grpRDRM\r
+\r
+\r
+/*** PERM - Port M Pull Device Enable Register; 0x00000254 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PERM0 :1; /* Pull Device Enable Port M Bit 0 */\r
+ byte PERM1 :1; /* Pull Device Enable Port M Bit 1 */\r
+ byte PERM2 :1; /* Pull Device Enable Port M Bit 2 */\r
+ byte PERM3 :1; /* Pull Device Enable Port M Bit 3 */\r
+ byte PERM4 :1; /* Pull Device Enable Port M Bit 4 */\r
+ byte PERM5 :1; /* Pull Device Enable Port M Bit 5 */\r
+ byte PERM6 :1; /* Pull Device Enable Port M Bit 6 */\r
+ byte PERM7 :1; /* Pull Device Enable Port M Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpPERM :8;\r
+ } MergedBits;\r
+} PERMSTR;\r
+extern volatile PERMSTR _PERM @(REG_BASE + 0x00000254);\r
+#define PERM _PERM.Byte\r
+#define PERM_PERM0 _PERM.Bits.PERM0\r
+#define PERM_PERM1 _PERM.Bits.PERM1\r
+#define PERM_PERM2 _PERM.Bits.PERM2\r
+#define PERM_PERM3 _PERM.Bits.PERM3\r
+#define PERM_PERM4 _PERM.Bits.PERM4\r
+#define PERM_PERM5 _PERM.Bits.PERM5\r
+#define PERM_PERM6 _PERM.Bits.PERM6\r
+#define PERM_PERM7 _PERM.Bits.PERM7\r
+#define PERM_PERM _PERM.MergedBits.grpPERM\r
+\r
+\r
+/*** PPSM - Port M Polarity Select Register; 0x00000255 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PPSM0 :1; /* Pull Select Port M Bit 0 */\r
+ byte PPSM1 :1; /* Pull Select Port M Bit 1 */\r
+ byte PPSM2 :1; /* Pull Select Port M Bit 2 */\r
+ byte PPSM3 :1; /* Pull Select Port M Bit 3 */\r
+ byte PPSM4 :1; /* Pull Select Port M Bit 4 */\r
+ byte PPSM5 :1; /* Pull Select Port M Bit 5 */\r
+ byte PPSM6 :1; /* Pull Select Port M Bit 6 */\r
+ byte PPSM7 :1; /* Pull Select Port M Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpPPSM :8;\r
+ } MergedBits;\r
+} PPSMSTR;\r
+extern volatile PPSMSTR _PPSM @(REG_BASE + 0x00000255);\r
+#define PPSM _PPSM.Byte\r
+#define PPSM_PPSM0 _PPSM.Bits.PPSM0\r
+#define PPSM_PPSM1 _PPSM.Bits.PPSM1\r
+#define PPSM_PPSM2 _PPSM.Bits.PPSM2\r
+#define PPSM_PPSM3 _PPSM.Bits.PPSM3\r
+#define PPSM_PPSM4 _PPSM.Bits.PPSM4\r
+#define PPSM_PPSM5 _PPSM.Bits.PPSM5\r
+#define PPSM_PPSM6 _PPSM.Bits.PPSM6\r
+#define PPSM_PPSM7 _PPSM.Bits.PPSM7\r
+#define PPSM_PPSM _PPSM.MergedBits.grpPPSM\r
+\r
+\r
+/*** WOMM - Port M Wired-Or Mode Register; 0x00000256 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte WOMM0 :1; /* Wired-Or Mode Port M Bit 0 */\r
+ byte WOMM1 :1; /* Wired-Or Mode Port M Bit 1 */\r
+ byte WOMM2 :1; /* Wired-Or Mode Port M Bit 2 */\r
+ byte WOMM3 :1; /* Wired-Or Mode Port M Bit 3 */\r
+ byte WOMM4 :1; /* Wired-Or Mode Port M Bit 4 */\r
+ byte WOMM5 :1; /* Wired-Or Mode Port M Bit 5 */\r
+ byte WOMM6 :1; /* Wired-Or Mode Port M Bit 6 */\r
+ byte WOMM7 :1; /* Wired-Or Mode Port M Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpWOMM :8;\r
+ } MergedBits;\r
+} WOMMSTR;\r
+extern volatile WOMMSTR _WOMM @(REG_BASE + 0x00000256);\r
+#define WOMM _WOMM.Byte\r
+#define WOMM_WOMM0 _WOMM.Bits.WOMM0\r
+#define WOMM_WOMM1 _WOMM.Bits.WOMM1\r
+#define WOMM_WOMM2 _WOMM.Bits.WOMM2\r
+#define WOMM_WOMM3 _WOMM.Bits.WOMM3\r
+#define WOMM_WOMM4 _WOMM.Bits.WOMM4\r
+#define WOMM_WOMM5 _WOMM.Bits.WOMM5\r
+#define WOMM_WOMM6 _WOMM.Bits.WOMM6\r
+#define WOMM_WOMM7 _WOMM.Bits.WOMM7\r
+#define WOMM_WOMM _WOMM.MergedBits.grpWOMM\r
+\r
+\r
+/*** MODRR - Module Routing Register; 0x00000257 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte MODRR0 :1; /* CAN0 Routing */\r
+ byte MODRR1 :1; /* CAN0 Routing */\r
+ byte MODRR2 :1; /* CAN4 Routing */\r
+ byte MODRR3 :1; /* CAN4 Routing */\r
+ byte MODRR4 :1; /* SPI0 Routing */\r
+ byte MODRR5 :1; /* SPI1 Routing */\r
+ byte MODRR6 :1; /* SPI2 Routing */\r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpMODRR :7;\r
+ byte :1;\r
+ } MergedBits;\r
+} MODRRSTR;\r
+extern volatile MODRRSTR _MODRR @(REG_BASE + 0x00000257);\r
+#define MODRR _MODRR.Byte\r
+#define MODRR_MODRR0 _MODRR.Bits.MODRR0\r
+#define MODRR_MODRR1 _MODRR.Bits.MODRR1\r
+#define MODRR_MODRR2 _MODRR.Bits.MODRR2\r
+#define MODRR_MODRR3 _MODRR.Bits.MODRR3\r
+#define MODRR_MODRR4 _MODRR.Bits.MODRR4\r
+#define MODRR_MODRR5 _MODRR.Bits.MODRR5\r
+#define MODRR_MODRR6 _MODRR.Bits.MODRR6\r
+#define MODRR_MODRR _MODRR.MergedBits.grpMODRR\r
+\r
+\r
+/*** PTP - Port P I/O Register; 0x00000258 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PTP0 :1; /* Port P Bit 0 */\r
+ byte PTP1 :1; /* Port P Bit 1 */\r
+ byte PTP2 :1; /* Port P Bit 2 */\r
+ byte PTP3 :1; /* Port P Bit 3 */\r
+ byte PTP4 :1; /* Port P Bit 4 */\r
+ byte PTP5 :1; /* Port P Bit 5 */\r
+ byte PTP6 :1; /* Port P Bit 6 */\r
+ byte PTP7 :1; /* Port P Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpPTP :8;\r
+ } MergedBits;\r
+} PTPSTR;\r
+extern volatile PTPSTR _PTP @(REG_BASE + 0x00000258);\r
+#define PTP _PTP.Byte\r
+#define PTP_PTP0 _PTP.Bits.PTP0\r
+#define PTP_PTP1 _PTP.Bits.PTP1\r
+#define PTP_PTP2 _PTP.Bits.PTP2\r
+#define PTP_PTP3 _PTP.Bits.PTP3\r
+#define PTP_PTP4 _PTP.Bits.PTP4\r
+#define PTP_PTP5 _PTP.Bits.PTP5\r
+#define PTP_PTP6 _PTP.Bits.PTP6\r
+#define PTP_PTP7 _PTP.Bits.PTP7\r
+#define PTP_PTP _PTP.MergedBits.grpPTP\r
+\r
+\r
+/*** PTIP - Port P Input; 0x00000259 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PTIP0 :1; /* Port P Bit 0 */\r
+ byte PTIP1 :1; /* Port P Bit 1 */\r
+ byte PTIP2 :1; /* Port P Bit 2 */\r
+ byte PTIP3 :1; /* Port P Bit 3 */\r
+ byte PTIP4 :1; /* Port P Bit 4 */\r
+ byte PTIP5 :1; /* Port P Bit 5 */\r
+ byte PTIP6 :1; /* Port P Bit 6 */\r
+ byte PTIP7 :1; /* Port P Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpPTIP :8;\r
+ } MergedBits;\r
+} PTIPSTR;\r
+extern volatile PTIPSTR _PTIP @(REG_BASE + 0x00000259);\r
+#define PTIP _PTIP.Byte\r
+#define PTIP_PTIP0 _PTIP.Bits.PTIP0\r
+#define PTIP_PTIP1 _PTIP.Bits.PTIP1\r
+#define PTIP_PTIP2 _PTIP.Bits.PTIP2\r
+#define PTIP_PTIP3 _PTIP.Bits.PTIP3\r
+#define PTIP_PTIP4 _PTIP.Bits.PTIP4\r
+#define PTIP_PTIP5 _PTIP.Bits.PTIP5\r
+#define PTIP_PTIP6 _PTIP.Bits.PTIP6\r
+#define PTIP_PTIP7 _PTIP.Bits.PTIP7\r
+#define PTIP_PTIP _PTIP.MergedBits.grpPTIP\r
+\r
+\r
+/*** DDRP - Port P Data Direction Register; 0x0000025A ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DDRP0 :1; /* Data Direction Port P Bit 0 */\r
+ byte DDRP1 :1; /* Data Direction Port P Bit 1 */\r
+ byte DDRP2 :1; /* Data Direction Port P Bit 2 */\r
+ byte DDRP3 :1; /* Data Direction Port P Bit 3 */\r
+ byte DDRP4 :1; /* Data Direction Port P Bit 4 */\r
+ byte DDRP5 :1; /* Data Direction Port P Bit 5 */\r
+ byte DDRP6 :1; /* Data Direction Port P Bit 6 */\r
+ byte DDRP7 :1; /* Data Direction Port P Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDDRP :8;\r
+ } MergedBits;\r
+} DDRPSTR;\r
+extern volatile DDRPSTR _DDRP @(REG_BASE + 0x0000025A);\r
+#define DDRP _DDRP.Byte\r
+#define DDRP_DDRP0 _DDRP.Bits.DDRP0\r
+#define DDRP_DDRP1 _DDRP.Bits.DDRP1\r
+#define DDRP_DDRP2 _DDRP.Bits.DDRP2\r
+#define DDRP_DDRP3 _DDRP.Bits.DDRP3\r
+#define DDRP_DDRP4 _DDRP.Bits.DDRP4\r
+#define DDRP_DDRP5 _DDRP.Bits.DDRP5\r
+#define DDRP_DDRP6 _DDRP.Bits.DDRP6\r
+#define DDRP_DDRP7 _DDRP.Bits.DDRP7\r
+#define DDRP_DDRP _DDRP.MergedBits.grpDDRP\r
+\r
+\r
+/*** RDRP - Port P Reduced Drive Register; 0x0000025B ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte RDRP0 :1; /* Reduced Drive Port P Bit 0 */\r
+ byte RDRP1 :1; /* Reduced Drive Port P Bit 1 */\r
+ byte RDRP2 :1; /* Reduced Drive Port P Bit 2 */\r
+ byte RDRP3 :1; /* Reduced Drive Port P Bit 3 */\r
+ byte RDRP4 :1; /* Reduced Drive Port P Bit 4 */\r
+ byte RDRP5 :1; /* Reduced Drive Port P Bit 5 */\r
+ byte RDRP6 :1; /* Reduced Drive Port P Bit 6 */\r
+ byte RDRP7 :1; /* Reduced Drive Port P Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpRDRP :8;\r
+ } MergedBits;\r
+} RDRPSTR;\r
+extern volatile RDRPSTR _RDRP @(REG_BASE + 0x0000025B);\r
+#define RDRP _RDRP.Byte\r
+#define RDRP_RDRP0 _RDRP.Bits.RDRP0\r
+#define RDRP_RDRP1 _RDRP.Bits.RDRP1\r
+#define RDRP_RDRP2 _RDRP.Bits.RDRP2\r
+#define RDRP_RDRP3 _RDRP.Bits.RDRP3\r
+#define RDRP_RDRP4 _RDRP.Bits.RDRP4\r
+#define RDRP_RDRP5 _RDRP.Bits.RDRP5\r
+#define RDRP_RDRP6 _RDRP.Bits.RDRP6\r
+#define RDRP_RDRP7 _RDRP.Bits.RDRP7\r
+#define RDRP_RDRP _RDRP.MergedBits.grpRDRP\r
+\r
+\r
+/*** PERP - Port P Pull Device Enable Register; 0x0000025C ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PERP0 :1; /* Pull Device Enable Port P Bit 0 */\r
+ byte PERP1 :1; /* Pull Device Enable Port P Bit 1 */\r
+ byte PERP2 :1; /* Pull Device Enable Port P Bit 2 */\r
+ byte PERP3 :1; /* Pull Device Enable Port P Bit 3 */\r
+ byte PERP4 :1; /* Pull Device Enable Port P Bit 4 */\r
+ byte PERP5 :1; /* Pull Device Enable Port P Bit 5 */\r
+ byte PERP6 :1; /* Pull Device Enable Port P Bit 6 */\r
+ byte PERP7 :1; /* Pull Device Enable Port P Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpPERP :8;\r
+ } MergedBits;\r
+} PERPSTR;\r
+extern volatile PERPSTR _PERP @(REG_BASE + 0x0000025C);\r
+#define PERP _PERP.Byte\r
+#define PERP_PERP0 _PERP.Bits.PERP0\r
+#define PERP_PERP1 _PERP.Bits.PERP1\r
+#define PERP_PERP2 _PERP.Bits.PERP2\r
+#define PERP_PERP3 _PERP.Bits.PERP3\r
+#define PERP_PERP4 _PERP.Bits.PERP4\r
+#define PERP_PERP5 _PERP.Bits.PERP5\r
+#define PERP_PERP6 _PERP.Bits.PERP6\r
+#define PERP_PERP7 _PERP.Bits.PERP7\r
+#define PERP_PERP _PERP.MergedBits.grpPERP\r
+\r
+\r
+/*** PPSP - Port P Polarity Select Register; 0x0000025D ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PPSP0 :1; /* Pull Select Port P Bit 0 */\r
+ byte PPSP1 :1; /* Pull Select Port P Bit 1 */\r
+ byte PPSP2 :1; /* Pull Select Port P Bit 2 */\r
+ byte PPSP3 :1; /* Pull Select Port P Bit 3 */\r
+ byte PPSP4 :1; /* Pull Select Port P Bit 4 */\r
+ byte PPSP5 :1; /* Pull Select Port P Bit 5 */\r
+ byte PPSP6 :1; /* Pull Select Port P Bit 6 */\r
+ byte PPSP7 :1; /* Pull Select Port P Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpPPSP :8;\r
+ } MergedBits;\r
+} PPSPSTR;\r
+extern volatile PPSPSTR _PPSP @(REG_BASE + 0x0000025D);\r
+#define PPSP _PPSP.Byte\r
+#define PPSP_PPSP0 _PPSP.Bits.PPSP0\r
+#define PPSP_PPSP1 _PPSP.Bits.PPSP1\r
+#define PPSP_PPSP2 _PPSP.Bits.PPSP2\r
+#define PPSP_PPSP3 _PPSP.Bits.PPSP3\r
+#define PPSP_PPSP4 _PPSP.Bits.PPSP4\r
+#define PPSP_PPSP5 _PPSP.Bits.PPSP5\r
+#define PPSP_PPSP6 _PPSP.Bits.PPSP6\r
+#define PPSP_PPSP7 _PPSP.Bits.PPSP7\r
+#define PPSP_PPSP _PPSP.MergedBits.grpPPSP\r
+\r
+\r
+/*** PIEP - Port P Interrupt Enable Register; 0x0000025E ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PIEP0 :1; /* Interrupt Enable Port P Bit 0 */\r
+ byte PIEP1 :1; /* Interrupt Enable Port P Bit 1 */\r
+ byte PIEP2 :1; /* Interrupt Enable Port P Bit 2 */\r
+ byte PIEP3 :1; /* Interrupt Enable Port P Bit 3 */\r
+ byte PIEP4 :1; /* Interrupt Enable Port P Bit 4 */\r
+ byte PIEP5 :1; /* Interrupt Enable Port P Bit 5 */\r
+ byte PIEP6 :1; /* Interrupt Enable Port P Bit 6 */\r
+ byte PIEP7 :1; /* Interrupt Enable Port P Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpPIEP :8;\r
+ } MergedBits;\r
+} PIEPSTR;\r
+extern volatile PIEPSTR _PIEP @(REG_BASE + 0x0000025E);\r
+#define PIEP _PIEP.Byte\r
+#define PIEP_PIEP0 _PIEP.Bits.PIEP0\r
+#define PIEP_PIEP1 _PIEP.Bits.PIEP1\r
+#define PIEP_PIEP2 _PIEP.Bits.PIEP2\r
+#define PIEP_PIEP3 _PIEP.Bits.PIEP3\r
+#define PIEP_PIEP4 _PIEP.Bits.PIEP4\r
+#define PIEP_PIEP5 _PIEP.Bits.PIEP5\r
+#define PIEP_PIEP6 _PIEP.Bits.PIEP6\r
+#define PIEP_PIEP7 _PIEP.Bits.PIEP7\r
+#define PIEP_PIEP _PIEP.MergedBits.grpPIEP\r
+\r
+\r
+/*** PIFP - Port P Interrupt Flag Register; 0x0000025F ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PIFP0 :1; /* Interrupt Flags Port P Bit 0 */\r
+ byte PIFP1 :1; /* Interrupt Flags Port P Bit 1 */\r
+ byte PIFP2 :1; /* Interrupt Flags Port P Bit 2 */\r
+ byte PIFP3 :1; /* Interrupt Flags Port P Bit 3 */\r
+ byte PIFP4 :1; /* Interrupt Flags Port P Bit 4 */\r
+ byte PIFP5 :1; /* Interrupt Flags Port P Bit 5 */\r
+ byte PIFP6 :1; /* Interrupt Flags Port P Bit 6 */\r
+ byte PIFP7 :1; /* Interrupt Flags Port P Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpPIFP :8;\r
+ } MergedBits;\r
+} PIFPSTR;\r
+extern volatile PIFPSTR _PIFP @(REG_BASE + 0x0000025F);\r
+#define PIFP _PIFP.Byte\r
+#define PIFP_PIFP0 _PIFP.Bits.PIFP0\r
+#define PIFP_PIFP1 _PIFP.Bits.PIFP1\r
+#define PIFP_PIFP2 _PIFP.Bits.PIFP2\r
+#define PIFP_PIFP3 _PIFP.Bits.PIFP3\r
+#define PIFP_PIFP4 _PIFP.Bits.PIFP4\r
+#define PIFP_PIFP5 _PIFP.Bits.PIFP5\r
+#define PIFP_PIFP6 _PIFP.Bits.PIFP6\r
+#define PIFP_PIFP7 _PIFP.Bits.PIFP7\r
+#define PIFP_PIFP _PIFP.MergedBits.grpPIFP\r
+\r
+\r
+/*** PTH - Port H I/O Register; 0x00000260 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PTH0 :1; /* Port H Bit 0 */\r
+ byte PTH1 :1; /* Port H Bit 1 */\r
+ byte PTH2 :1; /* Port H Bit 2 */\r
+ byte PTH3 :1; /* Port H Bit 3 */\r
+ byte PTH4 :1; /* Port H Bit 4 */\r
+ byte PTH5 :1; /* Port H Bit 5 */\r
+ byte PTH6 :1; /* Port H Bit 6 */\r
+ byte PTH7 :1; /* Port H Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpPTH :8;\r
+ } MergedBits;\r
+} PTHSTR;\r
+extern volatile PTHSTR _PTH @(REG_BASE + 0x00000260);\r
+#define PTH _PTH.Byte\r
+#define PTH_PTH0 _PTH.Bits.PTH0\r
+#define PTH_PTH1 _PTH.Bits.PTH1\r
+#define PTH_PTH2 _PTH.Bits.PTH2\r
+#define PTH_PTH3 _PTH.Bits.PTH3\r
+#define PTH_PTH4 _PTH.Bits.PTH4\r
+#define PTH_PTH5 _PTH.Bits.PTH5\r
+#define PTH_PTH6 _PTH.Bits.PTH6\r
+#define PTH_PTH7 _PTH.Bits.PTH7\r
+#define PTH_PTH _PTH.MergedBits.grpPTH\r
+\r
+\r
+/*** PTIH - Port H Input Register; 0x00000261 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PTIH0 :1; /* Port H Bit 0 */\r
+ byte PTIH1 :1; /* Port H Bit 1 */\r
+ byte PTIH2 :1; /* Port H Bit 2 */\r
+ byte PTIH3 :1; /* Port H Bit 3 */\r
+ byte PTIH4 :1; /* Port H Bit 4 */\r
+ byte PTIH5 :1; /* Port H Bit 5 */\r
+ byte PTIH6 :1; /* Port H Bit 6 */\r
+ byte PTIH7 :1; /* Port H Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpPTIH :8;\r
+ } MergedBits;\r
+} PTIHSTR;\r
+extern volatile PTIHSTR _PTIH @(REG_BASE + 0x00000261);\r
+#define PTIH _PTIH.Byte\r
+#define PTIH_PTIH0 _PTIH.Bits.PTIH0\r
+#define PTIH_PTIH1 _PTIH.Bits.PTIH1\r
+#define PTIH_PTIH2 _PTIH.Bits.PTIH2\r
+#define PTIH_PTIH3 _PTIH.Bits.PTIH3\r
+#define PTIH_PTIH4 _PTIH.Bits.PTIH4\r
+#define PTIH_PTIH5 _PTIH.Bits.PTIH5\r
+#define PTIH_PTIH6 _PTIH.Bits.PTIH6\r
+#define PTIH_PTIH7 _PTIH.Bits.PTIH7\r
+#define PTIH_PTIH _PTIH.MergedBits.grpPTIH\r
+\r
+\r
+/*** DDRH - Port H Data Direction Register; 0x00000262 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DDRH0 :1; /* Data Direction Port H Bit 0 */\r
+ byte DDRH1 :1; /* Data Direction Port H Bit 1 */\r
+ byte DDRH2 :1; /* Data Direction Port H Bit 2 */\r
+ byte DDRH3 :1; /* Data Direction Port H Bit 3 */\r
+ byte DDRH4 :1; /* Data Direction Port H Bit 4 */\r
+ byte DDRH5 :1; /* Data Direction Port H Bit 5 */\r
+ byte DDRH6 :1; /* Data Direction Port H Bit 6 */\r
+ byte DDRH7 :1; /* Data Direction Port H Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDDRH :8;\r
+ } MergedBits;\r
+} DDRHSTR;\r
+extern volatile DDRHSTR _DDRH @(REG_BASE + 0x00000262);\r
+#define DDRH _DDRH.Byte\r
+#define DDRH_DDRH0 _DDRH.Bits.DDRH0\r
+#define DDRH_DDRH1 _DDRH.Bits.DDRH1\r
+#define DDRH_DDRH2 _DDRH.Bits.DDRH2\r
+#define DDRH_DDRH3 _DDRH.Bits.DDRH3\r
+#define DDRH_DDRH4 _DDRH.Bits.DDRH4\r
+#define DDRH_DDRH5 _DDRH.Bits.DDRH5\r
+#define DDRH_DDRH6 _DDRH.Bits.DDRH6\r
+#define DDRH_DDRH7 _DDRH.Bits.DDRH7\r
+#define DDRH_DDRH _DDRH.MergedBits.grpDDRH\r
+\r
+\r
+/*** RDRH - Port H Reduced Drive Register; 0x00000263 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte RDRH0 :1; /* Reduced Drive Port H Bit 0 */\r
+ byte RDRH1 :1; /* Reduced Drive Port H Bit 1 */\r
+ byte RDRH2 :1; /* Reduced Drive Port H Bit 2 */\r
+ byte RDRH3 :1; /* Reduced Drive Port H Bit 3 */\r
+ byte RDRH4 :1; /* Reduced Drive Port H Bit 4 */\r
+ byte RDRH5 :1; /* Reduced Drive Port H Bit 5 */\r
+ byte RDRH6 :1; /* Reduced Drive Port H Bit 6 */\r
+ byte RDRH7 :1; /* Reduced Drive Port H Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpRDRH :8;\r
+ } MergedBits;\r
+} RDRHSTR;\r
+extern volatile RDRHSTR _RDRH @(REG_BASE + 0x00000263);\r
+#define RDRH _RDRH.Byte\r
+#define RDRH_RDRH0 _RDRH.Bits.RDRH0\r
+#define RDRH_RDRH1 _RDRH.Bits.RDRH1\r
+#define RDRH_RDRH2 _RDRH.Bits.RDRH2\r
+#define RDRH_RDRH3 _RDRH.Bits.RDRH3\r
+#define RDRH_RDRH4 _RDRH.Bits.RDRH4\r
+#define RDRH_RDRH5 _RDRH.Bits.RDRH5\r
+#define RDRH_RDRH6 _RDRH.Bits.RDRH6\r
+#define RDRH_RDRH7 _RDRH.Bits.RDRH7\r
+#define RDRH_RDRH _RDRH.MergedBits.grpRDRH\r
+\r
+\r
+/*** PERH - Port H Pull Device Enable Register; 0x00000264 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PERH0 :1; /* Pull Device Enable Port H Bit 0 */\r
+ byte PERH1 :1; /* Pull Device Enable Port H Bit 1 */\r
+ byte PERH2 :1; /* Pull Device Enable Port H Bit 2 */\r
+ byte PERH3 :1; /* Pull Device Enable Port H Bit 3 */\r
+ byte PERH4 :1; /* Pull Device Enable Port H Bit 4 */\r
+ byte PERH5 :1; /* Pull Device Enable Port H Bit 5 */\r
+ byte PERH6 :1; /* Pull Device Enable Port H Bit 6 */\r
+ byte PERH7 :1; /* Pull Device Enable Port H Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpPERH :8;\r
+ } MergedBits;\r
+} PERHSTR;\r
+extern volatile PERHSTR _PERH @(REG_BASE + 0x00000264);\r
+#define PERH _PERH.Byte\r
+#define PERH_PERH0 _PERH.Bits.PERH0\r
+#define PERH_PERH1 _PERH.Bits.PERH1\r
+#define PERH_PERH2 _PERH.Bits.PERH2\r
+#define PERH_PERH3 _PERH.Bits.PERH3\r
+#define PERH_PERH4 _PERH.Bits.PERH4\r
+#define PERH_PERH5 _PERH.Bits.PERH5\r
+#define PERH_PERH6 _PERH.Bits.PERH6\r
+#define PERH_PERH7 _PERH.Bits.PERH7\r
+#define PERH_PERH _PERH.MergedBits.grpPERH\r
+\r
+\r
+/*** PPSH - Port H Polarity Select Register; 0x00000265 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PPSH0 :1; /* Pull Select Port H Bit 0 */\r
+ byte PPSH1 :1; /* Pull Select Port H Bit 1 */\r
+ byte PPSH2 :1; /* Pull Select Port H Bit 2 */\r
+ byte PPSH3 :1; /* Pull Select Port H Bit 3 */\r
+ byte PPSH4 :1; /* Pull Select Port H Bit 4 */\r
+ byte PPSH5 :1; /* Pull Select Port H Bit 5 */\r
+ byte PPSH6 :1; /* Pull Select Port H Bit 6 */\r
+ byte PPSH7 :1; /* Pull Select Port H Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpPPSH :8;\r
+ } MergedBits;\r
+} PPSHSTR;\r
+extern volatile PPSHSTR _PPSH @(REG_BASE + 0x00000265);\r
+#define PPSH _PPSH.Byte\r
+#define PPSH_PPSH0 _PPSH.Bits.PPSH0\r
+#define PPSH_PPSH1 _PPSH.Bits.PPSH1\r
+#define PPSH_PPSH2 _PPSH.Bits.PPSH2\r
+#define PPSH_PPSH3 _PPSH.Bits.PPSH3\r
+#define PPSH_PPSH4 _PPSH.Bits.PPSH4\r
+#define PPSH_PPSH5 _PPSH.Bits.PPSH5\r
+#define PPSH_PPSH6 _PPSH.Bits.PPSH6\r
+#define PPSH_PPSH7 _PPSH.Bits.PPSH7\r
+#define PPSH_PPSH _PPSH.MergedBits.grpPPSH\r
+\r
+\r
+/*** PIEH - Port H Interrupt Enable Register; 0x00000266 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PIEH0 :1; /* Interrupt Enable Port H Bit 0 */\r
+ byte PIEH1 :1; /* Interrupt Enable Port H Bit 1 */\r
+ byte PIEH2 :1; /* Interrupt Enable Port H Bit 2 */\r
+ byte PIEH3 :1; /* Interrupt Enable Port H Bit 3 */\r
+ byte PIEH4 :1; /* Interrupt Enable Port H Bit 4 */\r
+ byte PIEH5 :1; /* Interrupt Enable Port H Bit 5 */\r
+ byte PIEH6 :1; /* Interrupt Enable Port H Bit 6 */\r
+ byte PIEH7 :1; /* Interrupt Enable Port H Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpPIEH :8;\r
+ } MergedBits;\r
+} PIEHSTR;\r
+extern volatile PIEHSTR _PIEH @(REG_BASE + 0x00000266);\r
+#define PIEH _PIEH.Byte\r
+#define PIEH_PIEH0 _PIEH.Bits.PIEH0\r
+#define PIEH_PIEH1 _PIEH.Bits.PIEH1\r
+#define PIEH_PIEH2 _PIEH.Bits.PIEH2\r
+#define PIEH_PIEH3 _PIEH.Bits.PIEH3\r
+#define PIEH_PIEH4 _PIEH.Bits.PIEH4\r
+#define PIEH_PIEH5 _PIEH.Bits.PIEH5\r
+#define PIEH_PIEH6 _PIEH.Bits.PIEH6\r
+#define PIEH_PIEH7 _PIEH.Bits.PIEH7\r
+#define PIEH_PIEH _PIEH.MergedBits.grpPIEH\r
+\r
+\r
+/*** PIFH - Port H Interrupt Flag Register; 0x00000267 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PIFH0 :1; /* Interrupt Flags Port H Bit 0 */\r
+ byte PIFH1 :1; /* Interrupt Flags Port H Bit 1 */\r
+ byte PIFH2 :1; /* Interrupt Flags Port H Bit 2 */\r
+ byte PIFH3 :1; /* Interrupt Flags Port H Bit 3 */\r
+ byte PIFH4 :1; /* Interrupt Flags Port H Bit 4 */\r
+ byte PIFH5 :1; /* Interrupt Flags Port H Bit 5 */\r
+ byte PIFH6 :1; /* Interrupt Flags Port H Bit 6 */\r
+ byte PIFH7 :1; /* Interrupt Flags Port H Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpPIFH :8;\r
+ } MergedBits;\r
+} PIFHSTR;\r
+extern volatile PIFHSTR _PIFH @(REG_BASE + 0x00000267);\r
+#define PIFH _PIFH.Byte\r
+#define PIFH_PIFH0 _PIFH.Bits.PIFH0\r
+#define PIFH_PIFH1 _PIFH.Bits.PIFH1\r
+#define PIFH_PIFH2 _PIFH.Bits.PIFH2\r
+#define PIFH_PIFH3 _PIFH.Bits.PIFH3\r
+#define PIFH_PIFH4 _PIFH.Bits.PIFH4\r
+#define PIFH_PIFH5 _PIFH.Bits.PIFH5\r
+#define PIFH_PIFH6 _PIFH.Bits.PIFH6\r
+#define PIFH_PIFH7 _PIFH.Bits.PIFH7\r
+#define PIFH_PIFH _PIFH.MergedBits.grpPIFH\r
+\r
+\r
+/*** PTJ - Port J I/O Register; 0x00000268 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PTJ0 :1; /* Port J Bit 0 */\r
+ byte PTJ1 :1; /* Port J Bit 1 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte PTJ6 :1; /* Port J Bit 6 */\r
+ byte PTJ7 :1; /* Port J Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpPTJ :2;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpPTJ_6 :2;\r
+ } MergedBits;\r
+} PTJSTR;\r
+extern volatile PTJSTR _PTJ @(REG_BASE + 0x00000268);\r
+#define PTJ _PTJ.Byte\r
+#define PTJ_PTJ0 _PTJ.Bits.PTJ0\r
+#define PTJ_PTJ1 _PTJ.Bits.PTJ1\r
+#define PTJ_PTJ6 _PTJ.Bits.PTJ6\r
+#define PTJ_PTJ7 _PTJ.Bits.PTJ7\r
+#define PTJ_PTJ _PTJ.MergedBits.grpPTJ\r
+#define PTJ_PTJ_6 _PTJ.MergedBits.grpPTJ_6\r
+\r
+\r
+/*** PTIJ - Port J Input Register; 0x00000269 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PTIJ0 :1; /* Port J Bit 0 */\r
+ byte PTIJ1 :1; /* Port J Bit 1 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte PTIJ6 :1; /* Port J Bit 6 */\r
+ byte PTIJ7 :1; /* Port J Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpPTIJ :2;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpPTIJ_6 :2;\r
+ } MergedBits;\r
+} PTIJSTR;\r
+extern volatile PTIJSTR _PTIJ @(REG_BASE + 0x00000269);\r
+#define PTIJ _PTIJ.Byte\r
+#define PTIJ_PTIJ0 _PTIJ.Bits.PTIJ0\r
+#define PTIJ_PTIJ1 _PTIJ.Bits.PTIJ1\r
+#define PTIJ_PTIJ6 _PTIJ.Bits.PTIJ6\r
+#define PTIJ_PTIJ7 _PTIJ.Bits.PTIJ7\r
+#define PTIJ_PTIJ _PTIJ.MergedBits.grpPTIJ\r
+#define PTIJ_PTIJ_6 _PTIJ.MergedBits.grpPTIJ_6\r
+\r
+\r
+/*** DDRJ - Port J Data Direction Register; 0x0000026A ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DDRJ0 :1; /* Data Direction Port J Bit 0 */\r
+ byte DDRJ1 :1; /* Data Direction Port J Bit 1 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte DDRJ6 :1; /* Data Direction Port J Bit 6 */\r
+ byte DDRJ7 :1; /* Data Direction Port J Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDDRJ :2;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpDDRJ_6 :2;\r
+ } MergedBits;\r
+} DDRJSTR;\r
+extern volatile DDRJSTR _DDRJ @(REG_BASE + 0x0000026A);\r
+#define DDRJ _DDRJ.Byte\r
+#define DDRJ_DDRJ0 _DDRJ.Bits.DDRJ0\r
+#define DDRJ_DDRJ1 _DDRJ.Bits.DDRJ1\r
+#define DDRJ_DDRJ6 _DDRJ.Bits.DDRJ6\r
+#define DDRJ_DDRJ7 _DDRJ.Bits.DDRJ7\r
+#define DDRJ_DDRJ _DDRJ.MergedBits.grpDDRJ\r
+#define DDRJ_DDRJ_6 _DDRJ.MergedBits.grpDDRJ_6\r
+\r
+\r
+/*** RDRJ - Port J Reduced Drive Register; 0x0000026B ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte RDRJ0 :1; /* Reduced Drive Port J Bit 0 */\r
+ byte RDRJ1 :1; /* Reduced Drive Port J Bit 1 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte RDRJ6 :1; /* Reduced Drive Port J Bit 6 */\r
+ byte RDRJ7 :1; /* Reduced Drive Port J Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpRDRJ :2;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpRDRJ_6 :2;\r
+ } MergedBits;\r
+} RDRJSTR;\r
+extern volatile RDRJSTR _RDRJ @(REG_BASE + 0x0000026B);\r
+#define RDRJ _RDRJ.Byte\r
+#define RDRJ_RDRJ0 _RDRJ.Bits.RDRJ0\r
+#define RDRJ_RDRJ1 _RDRJ.Bits.RDRJ1\r
+#define RDRJ_RDRJ6 _RDRJ.Bits.RDRJ6\r
+#define RDRJ_RDRJ7 _RDRJ.Bits.RDRJ7\r
+#define RDRJ_RDRJ _RDRJ.MergedBits.grpRDRJ\r
+#define RDRJ_RDRJ_6 _RDRJ.MergedBits.grpRDRJ_6\r
+\r
+\r
+/*** PERJ - Port J Pull Device Enable Register; 0x0000026C ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PERJ0 :1; /* Pull Device Enable Port J Bit 0 */\r
+ byte PERJ1 :1; /* Pull Device Enable Port J Bit 1 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte PERJ6 :1; /* Pull Device Enable Port J Bit 6 */\r
+ byte PERJ7 :1; /* Pull Device Enable Port J Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpPERJ :2;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpPERJ_6 :2;\r
+ } MergedBits;\r
+} PERJSTR;\r
+extern volatile PERJSTR _PERJ @(REG_BASE + 0x0000026C);\r
+#define PERJ _PERJ.Byte\r
+#define PERJ_PERJ0 _PERJ.Bits.PERJ0\r
+#define PERJ_PERJ1 _PERJ.Bits.PERJ1\r
+#define PERJ_PERJ6 _PERJ.Bits.PERJ6\r
+#define PERJ_PERJ7 _PERJ.Bits.PERJ7\r
+#define PERJ_PERJ _PERJ.MergedBits.grpPERJ\r
+#define PERJ_PERJ_6 _PERJ.MergedBits.grpPERJ_6\r
+\r
+\r
+/*** PPSJ - PortJP Polarity Select Register; 0x0000026D ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PPSJ0 :1; /* Pull Select Port J Bit 0 */\r
+ byte PPSJ1 :1; /* Pull Select Port J Bit 1 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte PPSJ6 :1; /* Pull Select Port J Bit 6 */\r
+ byte PPSJ7 :1; /* Pull Select Port J Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpPPSJ :2;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpPPSJ_6 :2;\r
+ } MergedBits;\r
+} PPSJSTR;\r
+extern volatile PPSJSTR _PPSJ @(REG_BASE + 0x0000026D);\r
+#define PPSJ _PPSJ.Byte\r
+#define PPSJ_PPSJ0 _PPSJ.Bits.PPSJ0\r
+#define PPSJ_PPSJ1 _PPSJ.Bits.PPSJ1\r
+#define PPSJ_PPSJ6 _PPSJ.Bits.PPSJ6\r
+#define PPSJ_PPSJ7 _PPSJ.Bits.PPSJ7\r
+#define PPSJ_PPSJ _PPSJ.MergedBits.grpPPSJ\r
+#define PPSJ_PPSJ_6 _PPSJ.MergedBits.grpPPSJ_6\r
+\r
+\r
+/*** PIEJ - Port J Interrupt Enable Register; 0x0000026E ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PIEJ0 :1; /* Interrupt Enable Port J Bit 0 */\r
+ byte PIEJ1 :1; /* Interrupt Enable Port J Bit 1 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte PIEJ6 :1; /* Interrupt Enable Port J Bit 6 */\r
+ byte PIEJ7 :1; /* Interrupt Enable Port J Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpPIEJ :2;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpPIEJ_6 :2;\r
+ } MergedBits;\r
+} PIEJSTR;\r
+extern volatile PIEJSTR _PIEJ @(REG_BASE + 0x0000026E);\r
+#define PIEJ _PIEJ.Byte\r
+#define PIEJ_PIEJ0 _PIEJ.Bits.PIEJ0\r
+#define PIEJ_PIEJ1 _PIEJ.Bits.PIEJ1\r
+#define PIEJ_PIEJ6 _PIEJ.Bits.PIEJ6\r
+#define PIEJ_PIEJ7 _PIEJ.Bits.PIEJ7\r
+#define PIEJ_PIEJ _PIEJ.MergedBits.grpPIEJ\r
+#define PIEJ_PIEJ_6 _PIEJ.MergedBits.grpPIEJ_6\r
+\r
+\r
+/*** PIFJ - Port J Interrupt Flag Register; 0x0000026F ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PIFJ0 :1; /* Interrupt Flags Port J Bit 0 */\r
+ byte PIFJ1 :1; /* Interrupt Flags Port J Bit 1 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte PIFJ6 :1; /* Interrupt Flags Port J Bit 6 */\r
+ byte PIFJ7 :1; /* Interrupt Flags Port J Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpPIFJ :2;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpPIFJ_6 :2;\r
+ } MergedBits;\r
+} PIFJSTR;\r
+extern volatile PIFJSTR _PIFJ @(REG_BASE + 0x0000026F);\r
+#define PIFJ _PIFJ.Byte\r
+#define PIFJ_PIFJ0 _PIFJ.Bits.PIFJ0\r
+#define PIFJ_PIFJ1 _PIFJ.Bits.PIFJ1\r
+#define PIFJ_PIFJ6 _PIFJ.Bits.PIFJ6\r
+#define PIFJ_PIFJ7 _PIFJ.Bits.PIFJ7\r
+#define PIFJ_PIFJ _PIFJ.MergedBits.grpPIFJ\r
+#define PIFJ_PIFJ_6 _PIFJ.MergedBits.grpPIFJ_6\r
+\r
+\r
+/*** CAN4CTL0 - MSCAN4 Control 0 Register; 0x00000280 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte INITRQ :1; /* Initialization Mode Request */\r
+ byte SLPRQ :1; /* Sleep Mode Request */\r
+ byte WUPE :1; /* Wake-Up Enable */\r
+ byte TIME :1; /* Timer Enable */\r
+ byte SYNCH :1; /* Synchronized Status */\r
+ byte CSWAI :1; /* CAN Stops in Wait Mode */\r
+ byte RXACT :1; /* Receiver Active Status */\r
+ byte RXFRM :1; /* Received Frame Flag */\r
+ } Bits;\r
+} CAN4CTL0STR;\r
+extern volatile CAN4CTL0STR _CAN4CTL0 @(REG_BASE + 0x00000280);\r
+#define CAN4CTL0 _CAN4CTL0.Byte\r
+#define CAN4CTL0_INITRQ _CAN4CTL0.Bits.INITRQ\r
+#define CAN4CTL0_SLPRQ _CAN4CTL0.Bits.SLPRQ\r
+#define CAN4CTL0_WUPE _CAN4CTL0.Bits.WUPE\r
+#define CAN4CTL0_TIME _CAN4CTL0.Bits.TIME\r
+#define CAN4CTL0_SYNCH _CAN4CTL0.Bits.SYNCH\r
+#define CAN4CTL0_CSWAI _CAN4CTL0.Bits.CSWAI\r
+#define CAN4CTL0_RXACT _CAN4CTL0.Bits.RXACT\r
+#define CAN4CTL0_RXFRM _CAN4CTL0.Bits.RXFRM\r
+\r
+\r
+/*** CAN4CTL1 - MSCAN4 Control 1 Register; 0x00000281 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte INITAK :1; /* Initialization Mode Acknowledge */\r
+ byte SLPAK :1; /* Sleep Mode Acknowledge */\r
+ byte WUPM :1; /* Wake-Up Mode */\r
+ byte :1; \r
+ byte LISTEN :1; /* Listen Only Mode */\r
+ byte LOOPB :1; /* Loop Back Self Test Mode */\r
+ byte CLKSRC :1; /* MSCAN4 Clock Source */\r
+ byte CANE :1; /* MSCAN4 Enable */\r
+ } Bits;\r
+} CAN4CTL1STR;\r
+extern volatile CAN4CTL1STR _CAN4CTL1 @(REG_BASE + 0x00000281);\r
+#define CAN4CTL1 _CAN4CTL1.Byte\r
+#define CAN4CTL1_INITAK _CAN4CTL1.Bits.INITAK\r
+#define CAN4CTL1_SLPAK _CAN4CTL1.Bits.SLPAK\r
+#define CAN4CTL1_WUPM _CAN4CTL1.Bits.WUPM\r
+#define CAN4CTL1_LISTEN _CAN4CTL1.Bits.LISTEN\r
+#define CAN4CTL1_LOOPB _CAN4CTL1.Bits.LOOPB\r
+#define CAN4CTL1_CLKSRC _CAN4CTL1.Bits.CLKSRC\r
+#define CAN4CTL1_CANE _CAN4CTL1.Bits.CANE\r
+\r
+\r
+/*** CAN4BTR0 - MSCAN4 Bus Timing Register 0; 0x00000282 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte BRP0 :1; /* Baud Rate Prescaler 0 */\r
+ byte BRP1 :1; /* Baud Rate Prescaler 1 */\r
+ byte BRP2 :1; /* Baud Rate Prescaler 2 */\r
+ byte BRP3 :1; /* Baud Rate Prescaler 3 */\r
+ byte BRP4 :1; /* Baud Rate Prescaler 4 */\r
+ byte BRP5 :1; /* Baud Rate Prescaler 5 */\r
+ byte SJW0 :1; /* Synchronization Jump Width 0 */\r
+ byte SJW1 :1; /* Synchronization Jump Width 1 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBRP :6;\r
+ byte grpSJW :2;\r
+ } MergedBits;\r
+} CAN4BTR0STR;\r
+extern volatile CAN4BTR0STR _CAN4BTR0 @(REG_BASE + 0x00000282);\r
+#define CAN4BTR0 _CAN4BTR0.Byte\r
+#define CAN4BTR0_BRP0 _CAN4BTR0.Bits.BRP0\r
+#define CAN4BTR0_BRP1 _CAN4BTR0.Bits.BRP1\r
+#define CAN4BTR0_BRP2 _CAN4BTR0.Bits.BRP2\r
+#define CAN4BTR0_BRP3 _CAN4BTR0.Bits.BRP3\r
+#define CAN4BTR0_BRP4 _CAN4BTR0.Bits.BRP4\r
+#define CAN4BTR0_BRP5 _CAN4BTR0.Bits.BRP5\r
+#define CAN4BTR0_SJW0 _CAN4BTR0.Bits.SJW0\r
+#define CAN4BTR0_SJW1 _CAN4BTR0.Bits.SJW1\r
+#define CAN4BTR0_BRP _CAN4BTR0.MergedBits.grpBRP\r
+#define CAN4BTR0_SJW _CAN4BTR0.MergedBits.grpSJW\r
+\r
+\r
+/*** CAN4BTR1 - MSCAN4 Bus Timing Register 1; 0x00000283 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte TSEG10 :1; /* Time Segment 1 */\r
+ byte TSEG11 :1; /* Time Segment 1 */\r
+ byte TSEG12 :1; /* Time Segment 1 */\r
+ byte TSEG13 :1; /* Time Segment 1 */\r
+ byte TSEG20 :1; /* Time Segment 2 */\r
+ byte TSEG21 :1; /* Time Segment 2 */\r
+ byte TSEG22 :1; /* Time Segment 2 */\r
+ byte SAMP :1; /* Sampling */\r
+ } Bits;\r
+ struct {\r
+ byte grpTSEG_10 :4;\r
+ byte grpTSEG_20 :3;\r
+ byte :1;\r
+ } MergedBits;\r
+} CAN4BTR1STR;\r
+extern volatile CAN4BTR1STR _CAN4BTR1 @(REG_BASE + 0x00000283);\r
+#define CAN4BTR1 _CAN4BTR1.Byte\r
+#define CAN4BTR1_TSEG10 _CAN4BTR1.Bits.TSEG10\r
+#define CAN4BTR1_TSEG11 _CAN4BTR1.Bits.TSEG11\r
+#define CAN4BTR1_TSEG12 _CAN4BTR1.Bits.TSEG12\r
+#define CAN4BTR1_TSEG13 _CAN4BTR1.Bits.TSEG13\r
+#define CAN4BTR1_TSEG20 _CAN4BTR1.Bits.TSEG20\r
+#define CAN4BTR1_TSEG21 _CAN4BTR1.Bits.TSEG21\r
+#define CAN4BTR1_TSEG22 _CAN4BTR1.Bits.TSEG22\r
+#define CAN4BTR1_SAMP _CAN4BTR1.Bits.SAMP\r
+#define CAN4BTR1_TSEG_10 _CAN4BTR1.MergedBits.grpTSEG_10\r
+#define CAN4BTR1_TSEG_20 _CAN4BTR1.MergedBits.grpTSEG_20\r
+#define CAN4BTR1_TSEG CAN4BTR1_TSEG_10\r
+\r
+\r
+/*** CAN4RFLG - MSCAN4 Receiver Flag Register; 0x00000284 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte RXF :1; /* Receive Buffer Full */\r
+ byte OVRIF :1; /* Overrun Interrupt Flag */\r
+ byte TSTAT0 :1; /* Transmitter Status Bit 0 */\r
+ byte TSTAT1 :1; /* Transmitter Status Bit 1 */\r
+ byte RSTAT0 :1; /* Receiver Status Bit 0 */\r
+ byte RSTAT1 :1; /* Receiver Status Bit 1 */\r
+ byte CSCIF :1; /* CAN Status Change Interrupt Flag */\r
+ byte WUPIF :1; /* Wake-up Interrupt Flag */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte grpTSTAT :2;\r
+ byte grpRSTAT :2;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CAN4RFLGSTR;\r
+extern volatile CAN4RFLGSTR _CAN4RFLG @(REG_BASE + 0x00000284);\r
+#define CAN4RFLG _CAN4RFLG.Byte\r
+#define CAN4RFLG_RXF _CAN4RFLG.Bits.RXF\r
+#define CAN4RFLG_OVRIF _CAN4RFLG.Bits.OVRIF\r
+#define CAN4RFLG_TSTAT0 _CAN4RFLG.Bits.TSTAT0\r
+#define CAN4RFLG_TSTAT1 _CAN4RFLG.Bits.TSTAT1\r
+#define CAN4RFLG_RSTAT0 _CAN4RFLG.Bits.RSTAT0\r
+#define CAN4RFLG_RSTAT1 _CAN4RFLG.Bits.RSTAT1\r
+#define CAN4RFLG_CSCIF _CAN4RFLG.Bits.CSCIF\r
+#define CAN4RFLG_WUPIF _CAN4RFLG.Bits.WUPIF\r
+#define CAN4RFLG_TSTAT _CAN4RFLG.MergedBits.grpTSTAT\r
+#define CAN4RFLG_RSTAT _CAN4RFLG.MergedBits.grpRSTAT\r
+\r
+\r
+/*** CAN4RIER - MSCAN4 Receiver Interrupt Enable Register; 0x00000285 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte RXFIE :1; /* Receiver Full Interrupt Enable */\r
+ byte OVRIE :1; /* Overrun Interrupt Enable */\r
+ byte TSTATE0 :1; /* Transmitter Status Change Enable 0 */\r
+ byte TSTATE1 :1; /* Transmitter Status Change Enable 1 */\r
+ byte RSTATE0 :1; /* Receiver Status Change Enable 0 */\r
+ byte RSTATE1 :1; /* Receiver Status Change Enable 1 */\r
+ byte CSCIE :1; /* CAN Status Change Interrupt Enable */\r
+ byte WUPIE :1; /* Wake-up Interrupt Enable */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte grpTSTATE :2;\r
+ byte grpRSTATE :2;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CAN4RIERSTR;\r
+extern volatile CAN4RIERSTR _CAN4RIER @(REG_BASE + 0x00000285);\r
+#define CAN4RIER _CAN4RIER.Byte\r
+#define CAN4RIER_RXFIE _CAN4RIER.Bits.RXFIE\r
+#define CAN4RIER_OVRIE _CAN4RIER.Bits.OVRIE\r
+#define CAN4RIER_TSTATE0 _CAN4RIER.Bits.TSTATE0\r
+#define CAN4RIER_TSTATE1 _CAN4RIER.Bits.TSTATE1\r
+#define CAN4RIER_RSTATE0 _CAN4RIER.Bits.RSTATE0\r
+#define CAN4RIER_RSTATE1 _CAN4RIER.Bits.RSTATE1\r
+#define CAN4RIER_CSCIE _CAN4RIER.Bits.CSCIE\r
+#define CAN4RIER_WUPIE _CAN4RIER.Bits.WUPIE\r
+#define CAN4RIER_TSTATE _CAN4RIER.MergedBits.grpTSTATE\r
+#define CAN4RIER_RSTATE _CAN4RIER.MergedBits.grpRSTATE\r
+\r
+\r
+/*** CAN4TFLG - MSCAN4 Transmitter Flag Register; 0x00000286 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte TXE0 :1; /* Transmitter Buffer Empty 0 */\r
+ byte TXE1 :1; /* Transmitter Buffer Empty 1 */\r
+ byte TXE2 :1; /* Transmitter Buffer Empty 2 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpTXE :3;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CAN4TFLGSTR;\r
+extern volatile CAN4TFLGSTR _CAN4TFLG @(REG_BASE + 0x00000286);\r
+#define CAN4TFLG _CAN4TFLG.Byte\r
+#define CAN4TFLG_TXE0 _CAN4TFLG.Bits.TXE0\r
+#define CAN4TFLG_TXE1 _CAN4TFLG.Bits.TXE1\r
+#define CAN4TFLG_TXE2 _CAN4TFLG.Bits.TXE2\r
+#define CAN4TFLG_TXE _CAN4TFLG.MergedBits.grpTXE\r
+\r
+\r
+/*** CAN4TIER - MSCAN4 Transmitter Interrupt Enable Register; 0x00000287 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte TXEIE0 :1; /* Transmitter Empty Interrupt Enable 0 */\r
+ byte TXEIE1 :1; /* Transmitter Empty Interrupt Enable 1 */\r
+ byte TXEIE2 :1; /* Transmitter Empty Interrupt Enable 2 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpTXEIE :3;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CAN4TIERSTR;\r
+extern volatile CAN4TIERSTR _CAN4TIER @(REG_BASE + 0x00000287);\r
+#define CAN4TIER _CAN4TIER.Byte\r
+#define CAN4TIER_TXEIE0 _CAN4TIER.Bits.TXEIE0\r
+#define CAN4TIER_TXEIE1 _CAN4TIER.Bits.TXEIE1\r
+#define CAN4TIER_TXEIE2 _CAN4TIER.Bits.TXEIE2\r
+#define CAN4TIER_TXEIE _CAN4TIER.MergedBits.grpTXEIE\r
+\r
+\r
+/*** CAN4TARQ - MSCAN 4 Transmitter Message Abort Request; 0x00000288 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ABTRQ0 :1; /* Abort Request 0 */\r
+ byte ABTRQ1 :1; /* Abort Request 1 */\r
+ byte ABTRQ2 :1; /* Abort Request 2 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpABTRQ :3;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CAN4TARQSTR;\r
+extern volatile CAN4TARQSTR _CAN4TARQ @(REG_BASE + 0x00000288);\r
+#define CAN4TARQ _CAN4TARQ.Byte\r
+#define CAN4TARQ_ABTRQ0 _CAN4TARQ.Bits.ABTRQ0\r
+#define CAN4TARQ_ABTRQ1 _CAN4TARQ.Bits.ABTRQ1\r
+#define CAN4TARQ_ABTRQ2 _CAN4TARQ.Bits.ABTRQ2\r
+#define CAN4TARQ_ABTRQ _CAN4TARQ.MergedBits.grpABTRQ\r
+\r
+\r
+/*** CAN4TAAK - MSCAN4 Transmitter Message Abort Control; 0x00000289 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ABTAK0 :1; /* Abort Acknowledge 0 */\r
+ byte ABTAK1 :1; /* Abort Acknowledge 1 */\r
+ byte ABTAK2 :1; /* Abort Acknowledge 2 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpABTAK :3;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CAN4TAAKSTR;\r
+extern volatile CAN4TAAKSTR _CAN4TAAK @(REG_BASE + 0x00000289);\r
+#define CAN4TAAK _CAN4TAAK.Byte\r
+#define CAN4TAAK_ABTAK0 _CAN4TAAK.Bits.ABTAK0\r
+#define CAN4TAAK_ABTAK1 _CAN4TAAK.Bits.ABTAK1\r
+#define CAN4TAAK_ABTAK2 _CAN4TAAK.Bits.ABTAK2\r
+#define CAN4TAAK_ABTAK _CAN4TAAK.MergedBits.grpABTAK\r
+\r
+\r
+/*** CAN4TBSEL - MSCAN4 Transmit Buffer Selection; 0x0000028A ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte TX0 :1; /* Transmit Buffer Select 0 */\r
+ byte TX1 :1; /* Transmit Buffer Select 1 */\r
+ byte TX2 :1; /* Transmit Buffer Select 2 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpTX :3;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CAN4TBSELSTR;\r
+extern volatile CAN4TBSELSTR _CAN4TBSEL @(REG_BASE + 0x0000028A);\r
+#define CAN4TBSEL _CAN4TBSEL.Byte\r
+#define CAN4TBSEL_TX0 _CAN4TBSEL.Bits.TX0\r
+#define CAN4TBSEL_TX1 _CAN4TBSEL.Bits.TX1\r
+#define CAN4TBSEL_TX2 _CAN4TBSEL.Bits.TX2\r
+#define CAN4TBSEL_TX _CAN4TBSEL.MergedBits.grpTX\r
+\r
+\r
+/*** CAN4IDAC - MSCAN4 Identifier Acceptance Control Register; 0x0000028B ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte IDHIT0 :1; /* Identifier Acceptance Hit Indicator 0 */\r
+ byte IDHIT1 :1; /* Identifier Acceptance Hit Indicator 1 */\r
+ byte IDHIT2 :1; /* Identifier Acceptance Hit Indicator 2 */\r
+ byte :1; \r
+ byte IDAM0 :1; /* Identifier Acceptance Mode 0 */\r
+ byte IDAM1 :1; /* Identifier Acceptance Mode 1 */\r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpIDHIT :3;\r
+ byte :1;\r
+ byte grpIDAM :2;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CAN4IDACSTR;\r
+extern volatile CAN4IDACSTR _CAN4IDAC @(REG_BASE + 0x0000028B);\r
+#define CAN4IDAC _CAN4IDAC.Byte\r
+#define CAN4IDAC_IDHIT0 _CAN4IDAC.Bits.IDHIT0\r
+#define CAN4IDAC_IDHIT1 _CAN4IDAC.Bits.IDHIT1\r
+#define CAN4IDAC_IDHIT2 _CAN4IDAC.Bits.IDHIT2\r
+#define CAN4IDAC_IDAM0 _CAN4IDAC.Bits.IDAM0\r
+#define CAN4IDAC_IDAM1 _CAN4IDAC.Bits.IDAM1\r
+#define CAN4IDAC_IDHIT _CAN4IDAC.MergedBits.grpIDHIT\r
+#define CAN4IDAC_IDAM _CAN4IDAC.MergedBits.grpIDAM\r
+\r
+\r
+/*** CAN4RXERR - MSCAN4 Receive Error Counter Register; 0x0000028E ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte RXERR0 :1; /* Bit 0 */\r
+ byte RXERR1 :1; /* Bit 1 */\r
+ byte RXERR2 :1; /* Bit 2 */\r
+ byte RXERR3 :1; /* Bit 3 */\r
+ byte RXERR4 :1; /* Bit 4 */\r
+ byte RXERR5 :1; /* Bit 5 */\r
+ byte RXERR6 :1; /* Bit 6 */\r
+ byte RXERR7 :1; /* Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpRXERR :8;\r
+ } MergedBits;\r
+} CAN4RXERRSTR;\r
+extern volatile CAN4RXERRSTR _CAN4RXERR @(REG_BASE + 0x0000028E);\r
+#define CAN4RXERR _CAN4RXERR.Byte\r
+#define CAN4RXERR_RXERR0 _CAN4RXERR.Bits.RXERR0\r
+#define CAN4RXERR_RXERR1 _CAN4RXERR.Bits.RXERR1\r
+#define CAN4RXERR_RXERR2 _CAN4RXERR.Bits.RXERR2\r
+#define CAN4RXERR_RXERR3 _CAN4RXERR.Bits.RXERR3\r
+#define CAN4RXERR_RXERR4 _CAN4RXERR.Bits.RXERR4\r
+#define CAN4RXERR_RXERR5 _CAN4RXERR.Bits.RXERR5\r
+#define CAN4RXERR_RXERR6 _CAN4RXERR.Bits.RXERR6\r
+#define CAN4RXERR_RXERR7 _CAN4RXERR.Bits.RXERR7\r
+#define CAN4RXERR_RXERR _CAN4RXERR.MergedBits.grpRXERR\r
+\r
+\r
+/*** CAN4TXERR - MSCAN4 Transmit Error Counter Register; 0x0000028F ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte TXERR0 :1; /* Bit 0 */\r
+ byte TXERR1 :1; /* Bit 1 */\r
+ byte TXERR2 :1; /* Bit 2 */\r
+ byte TXERR3 :1; /* Bit 3 */\r
+ byte TXERR4 :1; /* Bit 4 */\r
+ byte TXERR5 :1; /* Bit 5 */\r
+ byte TXERR6 :1; /* Bit 6 */\r
+ byte TXERR7 :1; /* Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpTXERR :8;\r
+ } MergedBits;\r
+} CAN4TXERRSTR;\r
+extern volatile CAN4TXERRSTR _CAN4TXERR @(REG_BASE + 0x0000028F);\r
+#define CAN4TXERR _CAN4TXERR.Byte\r
+#define CAN4TXERR_TXERR0 _CAN4TXERR.Bits.TXERR0\r
+#define CAN4TXERR_TXERR1 _CAN4TXERR.Bits.TXERR1\r
+#define CAN4TXERR_TXERR2 _CAN4TXERR.Bits.TXERR2\r
+#define CAN4TXERR_TXERR3 _CAN4TXERR.Bits.TXERR3\r
+#define CAN4TXERR_TXERR4 _CAN4TXERR.Bits.TXERR4\r
+#define CAN4TXERR_TXERR5 _CAN4TXERR.Bits.TXERR5\r
+#define CAN4TXERR_TXERR6 _CAN4TXERR.Bits.TXERR6\r
+#define CAN4TXERR_TXERR7 _CAN4TXERR.Bits.TXERR7\r
+#define CAN4TXERR_TXERR _CAN4TXERR.MergedBits.grpTXERR\r
+\r
+\r
+/*** CAN4IDAR0 - MSCAN4 Identifier Acceptance Register 0; 0x00000290 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AC0 :1; /* Acceptance Code Bit 0 */\r
+ byte AC1 :1; /* Acceptance Code Bit 1 */\r
+ byte AC2 :1; /* Acceptance Code Bit 2 */\r
+ byte AC3 :1; /* Acceptance Code Bit 3 */\r
+ byte AC4 :1; /* Acceptance Code Bit 4 */\r
+ byte AC5 :1; /* Acceptance Code Bit 5 */\r
+ byte AC6 :1; /* Acceptance Code Bit 6 */\r
+ byte AC7 :1; /* Acceptance Code Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAC :8;\r
+ } MergedBits;\r
+} CAN4IDAR0STR;\r
+extern volatile CAN4IDAR0STR _CAN4IDAR0 @(REG_BASE + 0x00000290);\r
+#define CAN4IDAR0 _CAN4IDAR0.Byte\r
+#define CAN4IDAR0_AC0 _CAN4IDAR0.Bits.AC0\r
+#define CAN4IDAR0_AC1 _CAN4IDAR0.Bits.AC1\r
+#define CAN4IDAR0_AC2 _CAN4IDAR0.Bits.AC2\r
+#define CAN4IDAR0_AC3 _CAN4IDAR0.Bits.AC3\r
+#define CAN4IDAR0_AC4 _CAN4IDAR0.Bits.AC4\r
+#define CAN4IDAR0_AC5 _CAN4IDAR0.Bits.AC5\r
+#define CAN4IDAR0_AC6 _CAN4IDAR0.Bits.AC6\r
+#define CAN4IDAR0_AC7 _CAN4IDAR0.Bits.AC7\r
+#define CAN4IDAR0_AC _CAN4IDAR0.MergedBits.grpAC\r
+\r
+\r
+/*** CAN4IDAR1 - MSCAN4 Identifier Acceptance Register 1; 0x00000291 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AC0 :1; /* Acceptance Code Bit 0 */\r
+ byte AC1 :1; /* Acceptance Code Bit 1 */\r
+ byte AC2 :1; /* Acceptance Code Bit 2 */\r
+ byte AC3 :1; /* Acceptance Code Bit 3 */\r
+ byte AC4 :1; /* Acceptance Code Bit 4 */\r
+ byte AC5 :1; /* Acceptance Code Bit 5 */\r
+ byte AC6 :1; /* Acceptance Code Bit 6 */\r
+ byte AC7 :1; /* Acceptance Code Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAC :8;\r
+ } MergedBits;\r
+} CAN4IDAR1STR;\r
+extern volatile CAN4IDAR1STR _CAN4IDAR1 @(REG_BASE + 0x00000291);\r
+#define CAN4IDAR1 _CAN4IDAR1.Byte\r
+#define CAN4IDAR1_AC0 _CAN4IDAR1.Bits.AC0\r
+#define CAN4IDAR1_AC1 _CAN4IDAR1.Bits.AC1\r
+#define CAN4IDAR1_AC2 _CAN4IDAR1.Bits.AC2\r
+#define CAN4IDAR1_AC3 _CAN4IDAR1.Bits.AC3\r
+#define CAN4IDAR1_AC4 _CAN4IDAR1.Bits.AC4\r
+#define CAN4IDAR1_AC5 _CAN4IDAR1.Bits.AC5\r
+#define CAN4IDAR1_AC6 _CAN4IDAR1.Bits.AC6\r
+#define CAN4IDAR1_AC7 _CAN4IDAR1.Bits.AC7\r
+#define CAN4IDAR1_AC _CAN4IDAR1.MergedBits.grpAC\r
+\r
+\r
+/*** CAN4IDAR2 - MSCAN4 Identifier Acceptance Register 2; 0x00000292 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AC0 :1; /* Acceptance Code Bit 0 */\r
+ byte AC1 :1; /* Acceptance Code Bit 1 */\r
+ byte AC2 :1; /* Acceptance Code Bit 2 */\r
+ byte AC3 :1; /* Acceptance Code Bit 3 */\r
+ byte AC4 :1; /* Acceptance Code Bit 4 */\r
+ byte AC5 :1; /* Acceptance Code Bit 5 */\r
+ byte AC6 :1; /* Acceptance Code Bit 6 */\r
+ byte AC7 :1; /* Acceptance Code Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAC :8;\r
+ } MergedBits;\r
+} CAN4IDAR2STR;\r
+extern volatile CAN4IDAR2STR _CAN4IDAR2 @(REG_BASE + 0x00000292);\r
+#define CAN4IDAR2 _CAN4IDAR2.Byte\r
+#define CAN4IDAR2_AC0 _CAN4IDAR2.Bits.AC0\r
+#define CAN4IDAR2_AC1 _CAN4IDAR2.Bits.AC1\r
+#define CAN4IDAR2_AC2 _CAN4IDAR2.Bits.AC2\r
+#define CAN4IDAR2_AC3 _CAN4IDAR2.Bits.AC3\r
+#define CAN4IDAR2_AC4 _CAN4IDAR2.Bits.AC4\r
+#define CAN4IDAR2_AC5 _CAN4IDAR2.Bits.AC5\r
+#define CAN4IDAR2_AC6 _CAN4IDAR2.Bits.AC6\r
+#define CAN4IDAR2_AC7 _CAN4IDAR2.Bits.AC7\r
+#define CAN4IDAR2_AC _CAN4IDAR2.MergedBits.grpAC\r
+\r
+\r
+/*** CAN4IDAR3 - MSCAN4 Identifier Acceptance Register 3; 0x00000293 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AC0 :1; /* Acceptance Code Bit 0 */\r
+ byte AC1 :1; /* Acceptance Code Bit 1 */\r
+ byte AC2 :1; /* Acceptance Code Bit 2 */\r
+ byte AC3 :1; /* Acceptance Code Bit 3 */\r
+ byte AC4 :1; /* Acceptance Code Bit 4 */\r
+ byte AC5 :1; /* Acceptance Code Bit 5 */\r
+ byte AC6 :1; /* Acceptance Code Bit 6 */\r
+ byte AC7 :1; /* Acceptance Code Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAC :8;\r
+ } MergedBits;\r
+} CAN4IDAR3STR;\r
+extern volatile CAN4IDAR3STR _CAN4IDAR3 @(REG_BASE + 0x00000293);\r
+#define CAN4IDAR3 _CAN4IDAR3.Byte\r
+#define CAN4IDAR3_AC0 _CAN4IDAR3.Bits.AC0\r
+#define CAN4IDAR3_AC1 _CAN4IDAR3.Bits.AC1\r
+#define CAN4IDAR3_AC2 _CAN4IDAR3.Bits.AC2\r
+#define CAN4IDAR3_AC3 _CAN4IDAR3.Bits.AC3\r
+#define CAN4IDAR3_AC4 _CAN4IDAR3.Bits.AC4\r
+#define CAN4IDAR3_AC5 _CAN4IDAR3.Bits.AC5\r
+#define CAN4IDAR3_AC6 _CAN4IDAR3.Bits.AC6\r
+#define CAN4IDAR3_AC7 _CAN4IDAR3.Bits.AC7\r
+#define CAN4IDAR3_AC _CAN4IDAR3.MergedBits.grpAC\r
+\r
+\r
+/*** CAN4IDMR0 - MSCAN4 Identifier Mask Register 0; 0x00000294 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AM0 :1; /* Acceptance Mask Bit 0 */\r
+ byte AM1 :1; /* Acceptance Mask Bit 1 */\r
+ byte AM2 :1; /* Acceptance Mask Bit 2 */\r
+ byte AM3 :1; /* Acceptance Mask Bit 3 */\r
+ byte AM4 :1; /* Acceptance Mask Bit 4 */\r
+ byte AM5 :1; /* Acceptance Mask Bit 5 */\r
+ byte AM6 :1; /* Acceptance Mask Bit 6 */\r
+ byte AM7 :1; /* Acceptance Mask Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAM :8;\r
+ } MergedBits;\r
+} CAN4IDMR0STR;\r
+extern volatile CAN4IDMR0STR _CAN4IDMR0 @(REG_BASE + 0x00000294);\r
+#define CAN4IDMR0 _CAN4IDMR0.Byte\r
+#define CAN4IDMR0_AM0 _CAN4IDMR0.Bits.AM0\r
+#define CAN4IDMR0_AM1 _CAN4IDMR0.Bits.AM1\r
+#define CAN4IDMR0_AM2 _CAN4IDMR0.Bits.AM2\r
+#define CAN4IDMR0_AM3 _CAN4IDMR0.Bits.AM3\r
+#define CAN4IDMR0_AM4 _CAN4IDMR0.Bits.AM4\r
+#define CAN4IDMR0_AM5 _CAN4IDMR0.Bits.AM5\r
+#define CAN4IDMR0_AM6 _CAN4IDMR0.Bits.AM6\r
+#define CAN4IDMR0_AM7 _CAN4IDMR0.Bits.AM7\r
+#define CAN4IDMR0_AM _CAN4IDMR0.MergedBits.grpAM\r
+\r
+\r
+/*** CAN4IDMR1 - MSCAN4 Identifier Mask Register 1; 0x00000295 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AM0 :1; /* Acceptance Mask Bit 0 */\r
+ byte AM1 :1; /* Acceptance Mask Bit 1 */\r
+ byte AM2 :1; /* Acceptance Mask Bit 2 */\r
+ byte AM3 :1; /* Acceptance Mask Bit 3 */\r
+ byte AM4 :1; /* Acceptance Mask Bit 4 */\r
+ byte AM5 :1; /* Acceptance Mask Bit 5 */\r
+ byte AM6 :1; /* Acceptance Mask Bit 6 */\r
+ byte AM7 :1; /* Acceptance Mask Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAM :8;\r
+ } MergedBits;\r
+} CAN4IDMR1STR;\r
+extern volatile CAN4IDMR1STR _CAN4IDMR1 @(REG_BASE + 0x00000295);\r
+#define CAN4IDMR1 _CAN4IDMR1.Byte\r
+#define CAN4IDMR1_AM0 _CAN4IDMR1.Bits.AM0\r
+#define CAN4IDMR1_AM1 _CAN4IDMR1.Bits.AM1\r
+#define CAN4IDMR1_AM2 _CAN4IDMR1.Bits.AM2\r
+#define CAN4IDMR1_AM3 _CAN4IDMR1.Bits.AM3\r
+#define CAN4IDMR1_AM4 _CAN4IDMR1.Bits.AM4\r
+#define CAN4IDMR1_AM5 _CAN4IDMR1.Bits.AM5\r
+#define CAN4IDMR1_AM6 _CAN4IDMR1.Bits.AM6\r
+#define CAN4IDMR1_AM7 _CAN4IDMR1.Bits.AM7\r
+#define CAN4IDMR1_AM _CAN4IDMR1.MergedBits.grpAM\r
+\r
+\r
+/*** CAN4IDMR2 - MSCAN4 Identifier Mask Register 2; 0x00000296 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AM0 :1; /* Acceptance Mask Bit 0 */\r
+ byte AM1 :1; /* Acceptance Mask Bit 1 */\r
+ byte AM2 :1; /* Acceptance Mask Bit 2 */\r
+ byte AM3 :1; /* Acceptance Mask Bit 3 */\r
+ byte AM4 :1; /* Acceptance Mask Bit 4 */\r
+ byte AM5 :1; /* Acceptance Mask Bit 5 */\r
+ byte AM6 :1; /* Acceptance Mask Bit 6 */\r
+ byte AM7 :1; /* Acceptance Mask Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAM :8;\r
+ } MergedBits;\r
+} CAN4IDMR2STR;\r
+extern volatile CAN4IDMR2STR _CAN4IDMR2 @(REG_BASE + 0x00000296);\r
+#define CAN4IDMR2 _CAN4IDMR2.Byte\r
+#define CAN4IDMR2_AM0 _CAN4IDMR2.Bits.AM0\r
+#define CAN4IDMR2_AM1 _CAN4IDMR2.Bits.AM1\r
+#define CAN4IDMR2_AM2 _CAN4IDMR2.Bits.AM2\r
+#define CAN4IDMR2_AM3 _CAN4IDMR2.Bits.AM3\r
+#define CAN4IDMR2_AM4 _CAN4IDMR2.Bits.AM4\r
+#define CAN4IDMR2_AM5 _CAN4IDMR2.Bits.AM5\r
+#define CAN4IDMR2_AM6 _CAN4IDMR2.Bits.AM6\r
+#define CAN4IDMR2_AM7 _CAN4IDMR2.Bits.AM7\r
+#define CAN4IDMR2_AM _CAN4IDMR2.MergedBits.grpAM\r
+\r
+\r
+/*** CAN4IDMR3 - MSCAN4 Identifier Mask Register 3; 0x00000297 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AM0 :1; /* Acceptance Mask Bit 0 */\r
+ byte AM1 :1; /* Acceptance Mask Bit 1 */\r
+ byte AM2 :1; /* Acceptance Mask Bit 2 */\r
+ byte AM3 :1; /* Acceptance Mask Bit 3 */\r
+ byte AM4 :1; /* Acceptance Mask Bit 4 */\r
+ byte AM5 :1; /* Acceptance Mask Bit 5 */\r
+ byte AM6 :1; /* Acceptance Mask Bit 6 */\r
+ byte AM7 :1; /* Acceptance Mask Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAM :8;\r
+ } MergedBits;\r
+} CAN4IDMR3STR;\r
+extern volatile CAN4IDMR3STR _CAN4IDMR3 @(REG_BASE + 0x00000297);\r
+#define CAN4IDMR3 _CAN4IDMR3.Byte\r
+#define CAN4IDMR3_AM0 _CAN4IDMR3.Bits.AM0\r
+#define CAN4IDMR3_AM1 _CAN4IDMR3.Bits.AM1\r
+#define CAN4IDMR3_AM2 _CAN4IDMR3.Bits.AM2\r
+#define CAN4IDMR3_AM3 _CAN4IDMR3.Bits.AM3\r
+#define CAN4IDMR3_AM4 _CAN4IDMR3.Bits.AM4\r
+#define CAN4IDMR3_AM5 _CAN4IDMR3.Bits.AM5\r
+#define CAN4IDMR3_AM6 _CAN4IDMR3.Bits.AM6\r
+#define CAN4IDMR3_AM7 _CAN4IDMR3.Bits.AM7\r
+#define CAN4IDMR3_AM _CAN4IDMR3.MergedBits.grpAM\r
+\r
+\r
+/*** CAN4IDAR4 - MSCAN4 Identifier Acceptance Register 4; 0x00000298 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AC0 :1; /* Acceptance Code Bit 0 */\r
+ byte AC1 :1; /* Acceptance Code Bit 1 */\r
+ byte AC2 :1; /* Acceptance Code Bit 2 */\r
+ byte AC3 :1; /* Acceptance Code Bit 3 */\r
+ byte AC4 :1; /* Acceptance Code Bit 4 */\r
+ byte AC5 :1; /* Acceptance Code Bit 5 */\r
+ byte AC6 :1; /* Acceptance Code Bit 6 */\r
+ byte AC7 :1; /* Acceptance Code Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAC :8;\r
+ } MergedBits;\r
+} CAN4IDAR4STR;\r
+extern volatile CAN4IDAR4STR _CAN4IDAR4 @(REG_BASE + 0x00000298);\r
+#define CAN4IDAR4 _CAN4IDAR4.Byte\r
+#define CAN4IDAR4_AC0 _CAN4IDAR4.Bits.AC0\r
+#define CAN4IDAR4_AC1 _CAN4IDAR4.Bits.AC1\r
+#define CAN4IDAR4_AC2 _CAN4IDAR4.Bits.AC2\r
+#define CAN4IDAR4_AC3 _CAN4IDAR4.Bits.AC3\r
+#define CAN4IDAR4_AC4 _CAN4IDAR4.Bits.AC4\r
+#define CAN4IDAR4_AC5 _CAN4IDAR4.Bits.AC5\r
+#define CAN4IDAR4_AC6 _CAN4IDAR4.Bits.AC6\r
+#define CAN4IDAR4_AC7 _CAN4IDAR4.Bits.AC7\r
+#define CAN4IDAR4_AC _CAN4IDAR4.MergedBits.grpAC\r
+\r
+\r
+/*** CAN4IDAR5 - MSCAN4 Identifier Acceptance Register 5; 0x00000299 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AC0 :1; /* Acceptance Code Bit 0 */\r
+ byte AC1 :1; /* Acceptance Code Bit 1 */\r
+ byte AC2 :1; /* Acceptance Code Bit 2 */\r
+ byte AC3 :1; /* Acceptance Code Bit 3 */\r
+ byte AC4 :1; /* Acceptance Code Bit 4 */\r
+ byte AC5 :1; /* Acceptance Code Bit 5 */\r
+ byte AC6 :1; /* Acceptance Code Bit 6 */\r
+ byte AC7 :1; /* Acceptance Code Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAC :8;\r
+ } MergedBits;\r
+} CAN4IDAR5STR;\r
+extern volatile CAN4IDAR5STR _CAN4IDAR5 @(REG_BASE + 0x00000299);\r
+#define CAN4IDAR5 _CAN4IDAR5.Byte\r
+#define CAN4IDAR5_AC0 _CAN4IDAR5.Bits.AC0\r
+#define CAN4IDAR5_AC1 _CAN4IDAR5.Bits.AC1\r
+#define CAN4IDAR5_AC2 _CAN4IDAR5.Bits.AC2\r
+#define CAN4IDAR5_AC3 _CAN4IDAR5.Bits.AC3\r
+#define CAN4IDAR5_AC4 _CAN4IDAR5.Bits.AC4\r
+#define CAN4IDAR5_AC5 _CAN4IDAR5.Bits.AC5\r
+#define CAN4IDAR5_AC6 _CAN4IDAR5.Bits.AC6\r
+#define CAN4IDAR5_AC7 _CAN4IDAR5.Bits.AC7\r
+#define CAN4IDAR5_AC _CAN4IDAR5.MergedBits.grpAC\r
+\r
+\r
+/*** CAN4IDAR6 - MSCAN4 Identifier Acceptance Register 6; 0x0000029A ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AC0 :1; /* Acceptance Code Bit 0 */\r
+ byte AC1 :1; /* Acceptance Code Bit 1 */\r
+ byte AC2 :1; /* Acceptance Code Bit 2 */\r
+ byte AC3 :1; /* Acceptance Code Bit 3 */\r
+ byte AC4 :1; /* Acceptance Code Bit 4 */\r
+ byte AC5 :1; /* Acceptance Code Bit 5 */\r
+ byte AC6 :1; /* Acceptance Code Bit 6 */\r
+ byte AC7 :1; /* Acceptance Code Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAC :8;\r
+ } MergedBits;\r
+} CAN4IDAR6STR;\r
+extern volatile CAN4IDAR6STR _CAN4IDAR6 @(REG_BASE + 0x0000029A);\r
+#define CAN4IDAR6 _CAN4IDAR6.Byte\r
+#define CAN4IDAR6_AC0 _CAN4IDAR6.Bits.AC0\r
+#define CAN4IDAR6_AC1 _CAN4IDAR6.Bits.AC1\r
+#define CAN4IDAR6_AC2 _CAN4IDAR6.Bits.AC2\r
+#define CAN4IDAR6_AC3 _CAN4IDAR6.Bits.AC3\r
+#define CAN4IDAR6_AC4 _CAN4IDAR6.Bits.AC4\r
+#define CAN4IDAR6_AC5 _CAN4IDAR6.Bits.AC5\r
+#define CAN4IDAR6_AC6 _CAN4IDAR6.Bits.AC6\r
+#define CAN4IDAR6_AC7 _CAN4IDAR6.Bits.AC7\r
+#define CAN4IDAR6_AC _CAN4IDAR6.MergedBits.grpAC\r
+\r
+\r
+/*** CAN4IDAR7 - MSCAN4 Identifier Acceptance Register 7; 0x0000029B ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AC0 :1; /* Acceptance Code Bit 0 */\r
+ byte AC1 :1; /* Acceptance Code Bit 1 */\r
+ byte AC2 :1; /* Acceptance Code Bit 2 */\r
+ byte AC3 :1; /* Acceptance Code Bit 3 */\r
+ byte AC4 :1; /* Acceptance Code Bit 4 */\r
+ byte AC5 :1; /* Acceptance Code Bit 5 */\r
+ byte AC6 :1; /* Acceptance Code Bit 6 */\r
+ byte AC7 :1; /* Acceptance Code Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAC :8;\r
+ } MergedBits;\r
+} CAN4IDAR7STR;\r
+extern volatile CAN4IDAR7STR _CAN4IDAR7 @(REG_BASE + 0x0000029B);\r
+#define CAN4IDAR7 _CAN4IDAR7.Byte\r
+#define CAN4IDAR7_AC0 _CAN4IDAR7.Bits.AC0\r
+#define CAN4IDAR7_AC1 _CAN4IDAR7.Bits.AC1\r
+#define CAN4IDAR7_AC2 _CAN4IDAR7.Bits.AC2\r
+#define CAN4IDAR7_AC3 _CAN4IDAR7.Bits.AC3\r
+#define CAN4IDAR7_AC4 _CAN4IDAR7.Bits.AC4\r
+#define CAN4IDAR7_AC5 _CAN4IDAR7.Bits.AC5\r
+#define CAN4IDAR7_AC6 _CAN4IDAR7.Bits.AC6\r
+#define CAN4IDAR7_AC7 _CAN4IDAR7.Bits.AC7\r
+#define CAN4IDAR7_AC _CAN4IDAR7.MergedBits.grpAC\r
+\r
+\r
+/*** CAN4IDMR4 - MSCAN4 Identifier Mask Register 4; 0x0000029C ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AM0 :1; /* Acceptance Mask Bit 0 */\r
+ byte AM1 :1; /* Acceptance Mask Bit 1 */\r
+ byte AM2 :1; /* Acceptance Mask Bit 2 */\r
+ byte AM3 :1; /* Acceptance Mask Bit 3 */\r
+ byte AM4 :1; /* Acceptance Mask Bit 4 */\r
+ byte AM5 :1; /* Acceptance Mask Bit 5 */\r
+ byte AM6 :1; /* Acceptance Mask Bit 6 */\r
+ byte AM7 :1; /* Acceptance Mask Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAM :8;\r
+ } MergedBits;\r
+} CAN4IDMR4STR;\r
+extern volatile CAN4IDMR4STR _CAN4IDMR4 @(REG_BASE + 0x0000029C);\r
+#define CAN4IDMR4 _CAN4IDMR4.Byte\r
+#define CAN4IDMR4_AM0 _CAN4IDMR4.Bits.AM0\r
+#define CAN4IDMR4_AM1 _CAN4IDMR4.Bits.AM1\r
+#define CAN4IDMR4_AM2 _CAN4IDMR4.Bits.AM2\r
+#define CAN4IDMR4_AM3 _CAN4IDMR4.Bits.AM3\r
+#define CAN4IDMR4_AM4 _CAN4IDMR4.Bits.AM4\r
+#define CAN4IDMR4_AM5 _CAN4IDMR4.Bits.AM5\r
+#define CAN4IDMR4_AM6 _CAN4IDMR4.Bits.AM6\r
+#define CAN4IDMR4_AM7 _CAN4IDMR4.Bits.AM7\r
+#define CAN4IDMR4_AM _CAN4IDMR4.MergedBits.grpAM\r
+\r
+\r
+/*** CAN4IDMR5 - MSCAN4 Identifier Mask Register 5; 0x0000029D ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AM0 :1; /* Acceptance Mask Bit 0 */\r
+ byte AM1 :1; /* Acceptance Mask Bit 1 */\r
+ byte AM2 :1; /* Acceptance Mask Bit 2 */\r
+ byte AM3 :1; /* Acceptance Mask Bit 3 */\r
+ byte AM4 :1; /* Acceptance Mask Bit 4 */\r
+ byte AM5 :1; /* Acceptance Mask Bit 5 */\r
+ byte AM6 :1; /* Acceptance Mask Bit 6 */\r
+ byte AM7 :1; /* Acceptance Mask Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAM :8;\r
+ } MergedBits;\r
+} CAN4IDMR5STR;\r
+extern volatile CAN4IDMR5STR _CAN4IDMR5 @(REG_BASE + 0x0000029D);\r
+#define CAN4IDMR5 _CAN4IDMR5.Byte\r
+#define CAN4IDMR5_AM0 _CAN4IDMR5.Bits.AM0\r
+#define CAN4IDMR5_AM1 _CAN4IDMR5.Bits.AM1\r
+#define CAN4IDMR5_AM2 _CAN4IDMR5.Bits.AM2\r
+#define CAN4IDMR5_AM3 _CAN4IDMR5.Bits.AM3\r
+#define CAN4IDMR5_AM4 _CAN4IDMR5.Bits.AM4\r
+#define CAN4IDMR5_AM5 _CAN4IDMR5.Bits.AM5\r
+#define CAN4IDMR5_AM6 _CAN4IDMR5.Bits.AM6\r
+#define CAN4IDMR5_AM7 _CAN4IDMR5.Bits.AM7\r
+#define CAN4IDMR5_AM _CAN4IDMR5.MergedBits.grpAM\r
+\r
+\r
+/*** CAN4IDMR6 - MSCAN4 Identifier Mask Register 6; 0x0000029E ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AM0 :1; /* Acceptance Mask Bit 0 */\r
+ byte AM1 :1; /* Acceptance Mask Bit 1 */\r
+ byte AM2 :1; /* Acceptance Mask Bit 2 */\r
+ byte AM3 :1; /* Acceptance Mask Bit 3 */\r
+ byte AM4 :1; /* Acceptance Mask Bit 4 */\r
+ byte AM5 :1; /* Acceptance Mask Bit 5 */\r
+ byte AM6 :1; /* Acceptance Mask Bit 6 */\r
+ byte AM7 :1; /* Acceptance Mask Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAM :8;\r
+ } MergedBits;\r
+} CAN4IDMR6STR;\r
+extern volatile CAN4IDMR6STR _CAN4IDMR6 @(REG_BASE + 0x0000029E);\r
+#define CAN4IDMR6 _CAN4IDMR6.Byte\r
+#define CAN4IDMR6_AM0 _CAN4IDMR6.Bits.AM0\r
+#define CAN4IDMR6_AM1 _CAN4IDMR6.Bits.AM1\r
+#define CAN4IDMR6_AM2 _CAN4IDMR6.Bits.AM2\r
+#define CAN4IDMR6_AM3 _CAN4IDMR6.Bits.AM3\r
+#define CAN4IDMR6_AM4 _CAN4IDMR6.Bits.AM4\r
+#define CAN4IDMR6_AM5 _CAN4IDMR6.Bits.AM5\r
+#define CAN4IDMR6_AM6 _CAN4IDMR6.Bits.AM6\r
+#define CAN4IDMR6_AM7 _CAN4IDMR6.Bits.AM7\r
+#define CAN4IDMR6_AM _CAN4IDMR6.MergedBits.grpAM\r
+\r
+\r
+/*** CAN4IDMR7 - MSCAN4 Identifier Mask Register 7; 0x0000029F ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AM0 :1; /* Acceptance Mask Bit 0 */\r
+ byte AM1 :1; /* Acceptance Mask Bit 1 */\r
+ byte AM2 :1; /* Acceptance Mask Bit 2 */\r
+ byte AM3 :1; /* Acceptance Mask Bit 3 */\r
+ byte AM4 :1; /* Acceptance Mask Bit 4 */\r
+ byte AM5 :1; /* Acceptance Mask Bit 5 */\r
+ byte AM6 :1; /* Acceptance Mask Bit 6 */\r
+ byte AM7 :1; /* Acceptance Mask Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAM :8;\r
+ } MergedBits;\r
+} CAN4IDMR7STR;\r
+extern volatile CAN4IDMR7STR _CAN4IDMR7 @(REG_BASE + 0x0000029F);\r
+#define CAN4IDMR7 _CAN4IDMR7.Byte\r
+#define CAN4IDMR7_AM0 _CAN4IDMR7.Bits.AM0\r
+#define CAN4IDMR7_AM1 _CAN4IDMR7.Bits.AM1\r
+#define CAN4IDMR7_AM2 _CAN4IDMR7.Bits.AM2\r
+#define CAN4IDMR7_AM3 _CAN4IDMR7.Bits.AM3\r
+#define CAN4IDMR7_AM4 _CAN4IDMR7.Bits.AM4\r
+#define CAN4IDMR7_AM5 _CAN4IDMR7.Bits.AM5\r
+#define CAN4IDMR7_AM6 _CAN4IDMR7.Bits.AM6\r
+#define CAN4IDMR7_AM7 _CAN4IDMR7.Bits.AM7\r
+#define CAN4IDMR7_AM _CAN4IDMR7.MergedBits.grpAM\r
+\r
+\r
+/*** CAN4RXIDR0 - MSCAN4 Receive Identifier Register 0; 0x000002A0 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ID21 :1; /* Extended format identifier Bit 21 */\r
+ byte ID22 :1; /* Extended format identifier Bit 22 */\r
+ byte ID23 :1; /* Extended format identifier Bit 23 */\r
+ byte ID24 :1; /* Extended format identifier Bit 24 */\r
+ byte ID25 :1; /* Extended format identifier Bit 25 */\r
+ byte ID26 :1; /* Extended format identifier Bit 26 */\r
+ byte ID27 :1; /* Extended format identifier Bit 27 */\r
+ byte ID28 :1; /* Extended format identifier Bit 28 */\r
+ } Bits;\r
+ struct {\r
+ byte grpID_21 :8;\r
+ } MergedBits;\r
+} CAN4RXIDR0STR;\r
+extern volatile CAN4RXIDR0STR _CAN4RXIDR0 @(REG_BASE + 0x000002A0);\r
+#define CAN4RXIDR0 _CAN4RXIDR0.Byte\r
+#define CAN4RXIDR0_ID21 _CAN4RXIDR0.Bits.ID21\r
+#define CAN4RXIDR0_ID22 _CAN4RXIDR0.Bits.ID22\r
+#define CAN4RXIDR0_ID23 _CAN4RXIDR0.Bits.ID23\r
+#define CAN4RXIDR0_ID24 _CAN4RXIDR0.Bits.ID24\r
+#define CAN4RXIDR0_ID25 _CAN4RXIDR0.Bits.ID25\r
+#define CAN4RXIDR0_ID26 _CAN4RXIDR0.Bits.ID26\r
+#define CAN4RXIDR0_ID27 _CAN4RXIDR0.Bits.ID27\r
+#define CAN4RXIDR0_ID28 _CAN4RXIDR0.Bits.ID28\r
+#define CAN4RXIDR0_ID_21 _CAN4RXIDR0.MergedBits.grpID_21\r
+#define CAN4RXIDR0_ID CAN4RXIDR0_ID_21\r
+\r
+\r
+/*** CAN4RXIDR1 - MSCAN4 Receive Identifier Register 1; 0x000002A1 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ID15 :1; /* Extended format identifier Bit 15 */\r
+ byte ID16 :1; /* Extended format identifier Bit 16 */\r
+ byte ID17 :1; /* Extended format identifier Bit 17 */\r
+ byte IDE :1; /* ID Extended */\r
+ byte SRR :1; /* Substitute Remote Request */\r
+ byte ID18 :1; /* Extended format identifier Bit 18 */\r
+ byte ID19 :1; /* Extended format identifier Bit 19 */\r
+ byte ID20 :1; /* Extended format identifier Bit 20 */\r
+ } Bits;\r
+ struct {\r
+ byte grpID_15 :3;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpID_18 :3;\r
+ } MergedBits;\r
+} CAN4RXIDR1STR;\r
+extern volatile CAN4RXIDR1STR _CAN4RXIDR1 @(REG_BASE + 0x000002A1);\r
+#define CAN4RXIDR1 _CAN4RXIDR1.Byte\r
+#define CAN4RXIDR1_ID15 _CAN4RXIDR1.Bits.ID15\r
+#define CAN4RXIDR1_ID16 _CAN4RXIDR1.Bits.ID16\r
+#define CAN4RXIDR1_ID17 _CAN4RXIDR1.Bits.ID17\r
+#define CAN4RXIDR1_IDE _CAN4RXIDR1.Bits.IDE\r
+#define CAN4RXIDR1_SRR _CAN4RXIDR1.Bits.SRR\r
+#define CAN4RXIDR1_ID18 _CAN4RXIDR1.Bits.ID18\r
+#define CAN4RXIDR1_ID19 _CAN4RXIDR1.Bits.ID19\r
+#define CAN4RXIDR1_ID20 _CAN4RXIDR1.Bits.ID20\r
+#define CAN4RXIDR1_ID_15 _CAN4RXIDR1.MergedBits.grpID_15\r
+#define CAN4RXIDR1_ID_18 _CAN4RXIDR1.MergedBits.grpID_18\r
+#define CAN4RXIDR1_ID CAN4RXIDR1_ID_15\r
+\r
+\r
+/*** CAN4RXIDR2 - MSCAN4 Receive Identifier Register 2; 0x000002A2 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ID7 :1; /* Extended format identifier Bit 7 */\r
+ byte ID8 :1; /* Extended format identifier Bit 8 */\r
+ byte ID9 :1; /* Extended format identifier Bit 9 */\r
+ byte ID10 :1; /* Extended format identifier Bit 10 */\r
+ byte ID11 :1; /* Extended format identifier Bit 11 */\r
+ byte ID12 :1; /* Extended format identifier Bit 12 */\r
+ byte ID13 :1; /* Extended format identifier Bit 13 */\r
+ byte ID14 :1; /* Extended format identifier Bit 14 */\r
+ } Bits;\r
+ struct {\r
+ byte grpID_7 :8;\r
+ } MergedBits;\r
+} CAN4RXIDR2STR;\r
+extern volatile CAN4RXIDR2STR _CAN4RXIDR2 @(REG_BASE + 0x000002A2);\r
+#define CAN4RXIDR2 _CAN4RXIDR2.Byte\r
+#define CAN4RXIDR2_ID7 _CAN4RXIDR2.Bits.ID7\r
+#define CAN4RXIDR2_ID8 _CAN4RXIDR2.Bits.ID8\r
+#define CAN4RXIDR2_ID9 _CAN4RXIDR2.Bits.ID9\r
+#define CAN4RXIDR2_ID10 _CAN4RXIDR2.Bits.ID10\r
+#define CAN4RXIDR2_ID11 _CAN4RXIDR2.Bits.ID11\r
+#define CAN4RXIDR2_ID12 _CAN4RXIDR2.Bits.ID12\r
+#define CAN4RXIDR2_ID13 _CAN4RXIDR2.Bits.ID13\r
+#define CAN4RXIDR2_ID14 _CAN4RXIDR2.Bits.ID14\r
+#define CAN4RXIDR2_ID_7 _CAN4RXIDR2.MergedBits.grpID_7\r
+#define CAN4RXIDR2_ID CAN4RXIDR2_ID_7\r
+\r
+\r
+/*** CAN4RXIDR3 - MSCAN4 Receive Identifier Register 3; 0x000002A3 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte RTR :1; /* Remote Transmission Request */\r
+ byte ID0 :1; /* Extended format identifier Bit 0 */\r
+ byte ID1 :1; /* Extended format identifier Bit 1 */\r
+ byte ID2 :1; /* Extended format identifier Bit 2 */\r
+ byte ID3 :1; /* Extended format identifier Bit 3 */\r
+ byte ID4 :1; /* Extended format identifier Bit 4 */\r
+ byte ID5 :1; /* Extended format identifier Bit 5 */\r
+ byte ID6 :1; /* Extended format identifier Bit 6 */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte grpID :7;\r
+ } MergedBits;\r
+} CAN4RXIDR3STR;\r
+extern volatile CAN4RXIDR3STR _CAN4RXIDR3 @(REG_BASE + 0x000002A3);\r
+#define CAN4RXIDR3 _CAN4RXIDR3.Byte\r
+#define CAN4RXIDR3_RTR _CAN4RXIDR3.Bits.RTR\r
+#define CAN4RXIDR3_ID0 _CAN4RXIDR3.Bits.ID0\r
+#define CAN4RXIDR3_ID1 _CAN4RXIDR3.Bits.ID1\r
+#define CAN4RXIDR3_ID2 _CAN4RXIDR3.Bits.ID2\r
+#define CAN4RXIDR3_ID3 _CAN4RXIDR3.Bits.ID3\r
+#define CAN4RXIDR3_ID4 _CAN4RXIDR3.Bits.ID4\r
+#define CAN4RXIDR3_ID5 _CAN4RXIDR3.Bits.ID5\r
+#define CAN4RXIDR3_ID6 _CAN4RXIDR3.Bits.ID6\r
+#define CAN4RXIDR3_ID _CAN4RXIDR3.MergedBits.grpID\r
+\r
+\r
+/*** CAN4RXDSR0 - MSCAN4 Receive Data Segment Register 0; 0x000002A4 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN4RXDSR0STR;\r
+extern volatile CAN4RXDSR0STR _CAN4RXDSR0 @(REG_BASE + 0x000002A4);\r
+#define CAN4RXDSR0 _CAN4RXDSR0.Byte\r
+#define CAN4RXDSR0_DB0 _CAN4RXDSR0.Bits.DB0\r
+#define CAN4RXDSR0_DB1 _CAN4RXDSR0.Bits.DB1\r
+#define CAN4RXDSR0_DB2 _CAN4RXDSR0.Bits.DB2\r
+#define CAN4RXDSR0_DB3 _CAN4RXDSR0.Bits.DB3\r
+#define CAN4RXDSR0_DB4 _CAN4RXDSR0.Bits.DB4\r
+#define CAN4RXDSR0_DB5 _CAN4RXDSR0.Bits.DB5\r
+#define CAN4RXDSR0_DB6 _CAN4RXDSR0.Bits.DB6\r
+#define CAN4RXDSR0_DB7 _CAN4RXDSR0.Bits.DB7\r
+#define CAN4RXDSR0_DB _CAN4RXDSR0.MergedBits.grpDB\r
+\r
+\r
+/*** CAN4RXDSR1 - MSCAN4 Receive Data Segment Register 1; 0x000002A5 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN4RXDSR1STR;\r
+extern volatile CAN4RXDSR1STR _CAN4RXDSR1 @(REG_BASE + 0x000002A5);\r
+#define CAN4RXDSR1 _CAN4RXDSR1.Byte\r
+#define CAN4RXDSR1_DB0 _CAN4RXDSR1.Bits.DB0\r
+#define CAN4RXDSR1_DB1 _CAN4RXDSR1.Bits.DB1\r
+#define CAN4RXDSR1_DB2 _CAN4RXDSR1.Bits.DB2\r
+#define CAN4RXDSR1_DB3 _CAN4RXDSR1.Bits.DB3\r
+#define CAN4RXDSR1_DB4 _CAN4RXDSR1.Bits.DB4\r
+#define CAN4RXDSR1_DB5 _CAN4RXDSR1.Bits.DB5\r
+#define CAN4RXDSR1_DB6 _CAN4RXDSR1.Bits.DB6\r
+#define CAN4RXDSR1_DB7 _CAN4RXDSR1.Bits.DB7\r
+#define CAN4RXDSR1_DB _CAN4RXDSR1.MergedBits.grpDB\r
+\r
+\r
+/*** CAN4RXDSR2 - MSCAN4 Receive Data Segment Register 2; 0x000002A6 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN4RXDSR2STR;\r
+extern volatile CAN4RXDSR2STR _CAN4RXDSR2 @(REG_BASE + 0x000002A6);\r
+#define CAN4RXDSR2 _CAN4RXDSR2.Byte\r
+#define CAN4RXDSR2_DB0 _CAN4RXDSR2.Bits.DB0\r
+#define CAN4RXDSR2_DB1 _CAN4RXDSR2.Bits.DB1\r
+#define CAN4RXDSR2_DB2 _CAN4RXDSR2.Bits.DB2\r
+#define CAN4RXDSR2_DB3 _CAN4RXDSR2.Bits.DB3\r
+#define CAN4RXDSR2_DB4 _CAN4RXDSR2.Bits.DB4\r
+#define CAN4RXDSR2_DB5 _CAN4RXDSR2.Bits.DB5\r
+#define CAN4RXDSR2_DB6 _CAN4RXDSR2.Bits.DB6\r
+#define CAN4RXDSR2_DB7 _CAN4RXDSR2.Bits.DB7\r
+#define CAN4RXDSR2_DB _CAN4RXDSR2.MergedBits.grpDB\r
+\r
+\r
+/*** CAN4RXDSR3 - MSCAN4 Receive Data Segment Register 3; 0x000002A7 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN4RXDSR3STR;\r
+extern volatile CAN4RXDSR3STR _CAN4RXDSR3 @(REG_BASE + 0x000002A7);\r
+#define CAN4RXDSR3 _CAN4RXDSR3.Byte\r
+#define CAN4RXDSR3_DB0 _CAN4RXDSR3.Bits.DB0\r
+#define CAN4RXDSR3_DB1 _CAN4RXDSR3.Bits.DB1\r
+#define CAN4RXDSR3_DB2 _CAN4RXDSR3.Bits.DB2\r
+#define CAN4RXDSR3_DB3 _CAN4RXDSR3.Bits.DB3\r
+#define CAN4RXDSR3_DB4 _CAN4RXDSR3.Bits.DB4\r
+#define CAN4RXDSR3_DB5 _CAN4RXDSR3.Bits.DB5\r
+#define CAN4RXDSR3_DB6 _CAN4RXDSR3.Bits.DB6\r
+#define CAN4RXDSR3_DB7 _CAN4RXDSR3.Bits.DB7\r
+#define CAN4RXDSR3_DB _CAN4RXDSR3.MergedBits.grpDB\r
+\r
+\r
+/*** CAN4RXDSR4 - MSCAN4 Receive Data Segment Register 4; 0x000002A8 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN4RXDSR4STR;\r
+extern volatile CAN4RXDSR4STR _CAN4RXDSR4 @(REG_BASE + 0x000002A8);\r
+#define CAN4RXDSR4 _CAN4RXDSR4.Byte\r
+#define CAN4RXDSR4_DB0 _CAN4RXDSR4.Bits.DB0\r
+#define CAN4RXDSR4_DB1 _CAN4RXDSR4.Bits.DB1\r
+#define CAN4RXDSR4_DB2 _CAN4RXDSR4.Bits.DB2\r
+#define CAN4RXDSR4_DB3 _CAN4RXDSR4.Bits.DB3\r
+#define CAN4RXDSR4_DB4 _CAN4RXDSR4.Bits.DB4\r
+#define CAN4RXDSR4_DB5 _CAN4RXDSR4.Bits.DB5\r
+#define CAN4RXDSR4_DB6 _CAN4RXDSR4.Bits.DB6\r
+#define CAN4RXDSR4_DB7 _CAN4RXDSR4.Bits.DB7\r
+#define CAN4RXDSR4_DB _CAN4RXDSR4.MergedBits.grpDB\r
+\r
+\r
+/*** CAN4RXDSR5 - MSCAN4 Receive Data Segment Register 5; 0x000002A9 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN4RXDSR5STR;\r
+extern volatile CAN4RXDSR5STR _CAN4RXDSR5 @(REG_BASE + 0x000002A9);\r
+#define CAN4RXDSR5 _CAN4RXDSR5.Byte\r
+#define CAN4RXDSR5_DB0 _CAN4RXDSR5.Bits.DB0\r
+#define CAN4RXDSR5_DB1 _CAN4RXDSR5.Bits.DB1\r
+#define CAN4RXDSR5_DB2 _CAN4RXDSR5.Bits.DB2\r
+#define CAN4RXDSR5_DB3 _CAN4RXDSR5.Bits.DB3\r
+#define CAN4RXDSR5_DB4 _CAN4RXDSR5.Bits.DB4\r
+#define CAN4RXDSR5_DB5 _CAN4RXDSR5.Bits.DB5\r
+#define CAN4RXDSR5_DB6 _CAN4RXDSR5.Bits.DB6\r
+#define CAN4RXDSR5_DB7 _CAN4RXDSR5.Bits.DB7\r
+#define CAN4RXDSR5_DB _CAN4RXDSR5.MergedBits.grpDB\r
+\r
+\r
+/*** CAN4RXDSR6 - MSCAN4 Receive Data Segment Register 6; 0x000002AA ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN4RXDSR6STR;\r
+extern volatile CAN4RXDSR6STR _CAN4RXDSR6 @(REG_BASE + 0x000002AA);\r
+#define CAN4RXDSR6 _CAN4RXDSR6.Byte\r
+#define CAN4RXDSR6_DB0 _CAN4RXDSR6.Bits.DB0\r
+#define CAN4RXDSR6_DB1 _CAN4RXDSR6.Bits.DB1\r
+#define CAN4RXDSR6_DB2 _CAN4RXDSR6.Bits.DB2\r
+#define CAN4RXDSR6_DB3 _CAN4RXDSR6.Bits.DB3\r
+#define CAN4RXDSR6_DB4 _CAN4RXDSR6.Bits.DB4\r
+#define CAN4RXDSR6_DB5 _CAN4RXDSR6.Bits.DB5\r
+#define CAN4RXDSR6_DB6 _CAN4RXDSR6.Bits.DB6\r
+#define CAN4RXDSR6_DB7 _CAN4RXDSR6.Bits.DB7\r
+#define CAN4RXDSR6_DB _CAN4RXDSR6.MergedBits.grpDB\r
+\r
+\r
+/*** CAN4RXDSR7 - MSCAN4 Receive Data Segment Register 7; 0x000002AB ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN4RXDSR7STR;\r
+extern volatile CAN4RXDSR7STR _CAN4RXDSR7 @(REG_BASE + 0x000002AB);\r
+#define CAN4RXDSR7 _CAN4RXDSR7.Byte\r
+#define CAN4RXDSR7_DB0 _CAN4RXDSR7.Bits.DB0\r
+#define CAN4RXDSR7_DB1 _CAN4RXDSR7.Bits.DB1\r
+#define CAN4RXDSR7_DB2 _CAN4RXDSR7.Bits.DB2\r
+#define CAN4RXDSR7_DB3 _CAN4RXDSR7.Bits.DB3\r
+#define CAN4RXDSR7_DB4 _CAN4RXDSR7.Bits.DB4\r
+#define CAN4RXDSR7_DB5 _CAN4RXDSR7.Bits.DB5\r
+#define CAN4RXDSR7_DB6 _CAN4RXDSR7.Bits.DB6\r
+#define CAN4RXDSR7_DB7 _CAN4RXDSR7.Bits.DB7\r
+#define CAN4RXDSR7_DB _CAN4RXDSR7.MergedBits.grpDB\r
+\r
+\r
+/*** CAN4RXDLR - MSCAN4 Receive Data Length Register; 0x000002AC ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DLC0 :1; /* Data Length Code Bit 0 */\r
+ byte DLC1 :1; /* Data Length Code Bit 1 */\r
+ byte DLC2 :1; /* Data Length Code Bit 2 */\r
+ byte DLC3 :1; /* Data Length Code Bit 3 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpDLC :4;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CAN4RXDLRSTR;\r
+extern volatile CAN4RXDLRSTR _CAN4RXDLR @(REG_BASE + 0x000002AC);\r
+#define CAN4RXDLR _CAN4RXDLR.Byte\r
+#define CAN4RXDLR_DLC0 _CAN4RXDLR.Bits.DLC0\r
+#define CAN4RXDLR_DLC1 _CAN4RXDLR.Bits.DLC1\r
+#define CAN4RXDLR_DLC2 _CAN4RXDLR.Bits.DLC2\r
+#define CAN4RXDLR_DLC3 _CAN4RXDLR.Bits.DLC3\r
+#define CAN4RXDLR_DLC _CAN4RXDLR.MergedBits.grpDLC\r
+\r
+\r
+/*** CAN4TXIDR0 - MSCAN4 Transmit Identifier Register 0; 0x000002B0 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ID21 :1; /* Extended format identifier Bit 21 */\r
+ byte ID22 :1; /* Extended format identifier Bit 22 */\r
+ byte ID23 :1; /* Extended format identifier Bit 23 */\r
+ byte ID24 :1; /* Extended format identifier Bit 24 */\r
+ byte ID25 :1; /* Extended format identifier Bit 25 */\r
+ byte ID26 :1; /* Extended format identifier Bit 26 */\r
+ byte ID27 :1; /* Extended format identifier Bit 27 */\r
+ byte ID28 :1; /* Extended format identifier Bit 28 */\r
+ } Bits;\r
+ struct {\r
+ byte grpID_21 :8;\r
+ } MergedBits;\r
+} CAN4TXIDR0STR;\r
+extern volatile CAN4TXIDR0STR _CAN4TXIDR0 @(REG_BASE + 0x000002B0);\r
+#define CAN4TXIDR0 _CAN4TXIDR0.Byte\r
+#define CAN4TXIDR0_ID21 _CAN4TXIDR0.Bits.ID21\r
+#define CAN4TXIDR0_ID22 _CAN4TXIDR0.Bits.ID22\r
+#define CAN4TXIDR0_ID23 _CAN4TXIDR0.Bits.ID23\r
+#define CAN4TXIDR0_ID24 _CAN4TXIDR0.Bits.ID24\r
+#define CAN4TXIDR0_ID25 _CAN4TXIDR0.Bits.ID25\r
+#define CAN4TXIDR0_ID26 _CAN4TXIDR0.Bits.ID26\r
+#define CAN4TXIDR0_ID27 _CAN4TXIDR0.Bits.ID27\r
+#define CAN4TXIDR0_ID28 _CAN4TXIDR0.Bits.ID28\r
+#define CAN4TXIDR0_ID_21 _CAN4TXIDR0.MergedBits.grpID_21\r
+#define CAN4TXIDR0_ID CAN4TXIDR0_ID_21\r
+\r
+\r
+/*** CAN4TXIDR1 - MSCAN4 Transmit Identifier Register 1; 0x000002B1 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ID15 :1; /* Extended format identifier Bit 15 */\r
+ byte ID16 :1; /* Extended format identifier Bit 16 */\r
+ byte ID17 :1; /* Extended format identifier Bit 17 */\r
+ byte IDE :1; /* ID Extended */\r
+ byte SRR :1; /* Substitute Remote Request */\r
+ byte ID18 :1; /* Extended format identifier Bit 18 */\r
+ byte ID19 :1; /* Extended format identifier Bit 19 */\r
+ byte ID20 :1; /* Extended format identifier Bit 20 */\r
+ } Bits;\r
+ struct {\r
+ byte grpID_15 :3;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpID_18 :3;\r
+ } MergedBits;\r
+} CAN4TXIDR1STR;\r
+extern volatile CAN4TXIDR1STR _CAN4TXIDR1 @(REG_BASE + 0x000002B1);\r
+#define CAN4TXIDR1 _CAN4TXIDR1.Byte\r
+#define CAN4TXIDR1_ID15 _CAN4TXIDR1.Bits.ID15\r
+#define CAN4TXIDR1_ID16 _CAN4TXIDR1.Bits.ID16\r
+#define CAN4TXIDR1_ID17 _CAN4TXIDR1.Bits.ID17\r
+#define CAN4TXIDR1_IDE _CAN4TXIDR1.Bits.IDE\r
+#define CAN4TXIDR1_SRR _CAN4TXIDR1.Bits.SRR\r
+#define CAN4TXIDR1_ID18 _CAN4TXIDR1.Bits.ID18\r
+#define CAN4TXIDR1_ID19 _CAN4TXIDR1.Bits.ID19\r
+#define CAN4TXIDR1_ID20 _CAN4TXIDR1.Bits.ID20\r
+#define CAN4TXIDR1_ID_15 _CAN4TXIDR1.MergedBits.grpID_15\r
+#define CAN4TXIDR1_ID_18 _CAN4TXIDR1.MergedBits.grpID_18\r
+#define CAN4TXIDR1_ID CAN4TXIDR1_ID_15\r
+\r
+\r
+/*** CAN4TXIDR2 - MSCAN4 Transmit Identifier Register 2; 0x000002B2 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ID7 :1; /* Extended format identifier Bit 7 */\r
+ byte ID8 :1; /* Extended format identifier Bit 8 */\r
+ byte ID9 :1; /* Extended format identifier Bit 9 */\r
+ byte ID10 :1; /* Extended format identifier Bit 10 */\r
+ byte ID11 :1; /* Extended format identifier Bit 11 */\r
+ byte ID12 :1; /* Extended format identifier Bit 12 */\r
+ byte ID13 :1; /* Extended format identifier Bit 13 */\r
+ byte ID14 :1; /* Extended format identifier Bit 14 */\r
+ } Bits;\r
+ struct {\r
+ byte grpID_7 :8;\r
+ } MergedBits;\r
+} CAN4TXIDR2STR;\r
+extern volatile CAN4TXIDR2STR _CAN4TXIDR2 @(REG_BASE + 0x000002B2);\r
+#define CAN4TXIDR2 _CAN4TXIDR2.Byte\r
+#define CAN4TXIDR2_ID7 _CAN4TXIDR2.Bits.ID7\r
+#define CAN4TXIDR2_ID8 _CAN4TXIDR2.Bits.ID8\r
+#define CAN4TXIDR2_ID9 _CAN4TXIDR2.Bits.ID9\r
+#define CAN4TXIDR2_ID10 _CAN4TXIDR2.Bits.ID10\r
+#define CAN4TXIDR2_ID11 _CAN4TXIDR2.Bits.ID11\r
+#define CAN4TXIDR2_ID12 _CAN4TXIDR2.Bits.ID12\r
+#define CAN4TXIDR2_ID13 _CAN4TXIDR2.Bits.ID13\r
+#define CAN4TXIDR2_ID14 _CAN4TXIDR2.Bits.ID14\r
+#define CAN4TXIDR2_ID_7 _CAN4TXIDR2.MergedBits.grpID_7\r
+#define CAN4TXIDR2_ID CAN4TXIDR2_ID_7\r
+\r
+\r
+/*** CAN4TXIDR3 - MSCAN4 Transmit Identifier Register 3; 0x000002B3 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte RTR :1; /* Remote Transmission Request */\r
+ byte ID0 :1; /* Extended format identifier Bit 0 */\r
+ byte ID1 :1; /* Extended format identifier Bit 1 */\r
+ byte ID2 :1; /* Extended format identifier Bit 2 */\r
+ byte ID3 :1; /* Extended format identifier Bit 3 */\r
+ byte ID4 :1; /* Extended format identifier Bit 4 */\r
+ byte ID5 :1; /* Extended format identifier Bit 5 */\r
+ byte ID6 :1; /* Extended format identifier Bit 6 */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte grpID :7;\r
+ } MergedBits;\r
+} CAN4TXIDR3STR;\r
+extern volatile CAN4TXIDR3STR _CAN4TXIDR3 @(REG_BASE + 0x000002B3);\r
+#define CAN4TXIDR3 _CAN4TXIDR3.Byte\r
+#define CAN4TXIDR3_RTR _CAN4TXIDR3.Bits.RTR\r
+#define CAN4TXIDR3_ID0 _CAN4TXIDR3.Bits.ID0\r
+#define CAN4TXIDR3_ID1 _CAN4TXIDR3.Bits.ID1\r
+#define CAN4TXIDR3_ID2 _CAN4TXIDR3.Bits.ID2\r
+#define CAN4TXIDR3_ID3 _CAN4TXIDR3.Bits.ID3\r
+#define CAN4TXIDR3_ID4 _CAN4TXIDR3.Bits.ID4\r
+#define CAN4TXIDR3_ID5 _CAN4TXIDR3.Bits.ID5\r
+#define CAN4TXIDR3_ID6 _CAN4TXIDR3.Bits.ID6\r
+#define CAN4TXIDR3_ID _CAN4TXIDR3.MergedBits.grpID\r
+\r
+\r
+/*** CAN4TXDSR0 - MSCAN4 Transmit Data Segment Register 0; 0x000002B4 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN4TXDSR0STR;\r
+extern volatile CAN4TXDSR0STR _CAN4TXDSR0 @(REG_BASE + 0x000002B4);\r
+#define CAN4TXDSR0 _CAN4TXDSR0.Byte\r
+#define CAN4TXDSR0_DB0 _CAN4TXDSR0.Bits.DB0\r
+#define CAN4TXDSR0_DB1 _CAN4TXDSR0.Bits.DB1\r
+#define CAN4TXDSR0_DB2 _CAN4TXDSR0.Bits.DB2\r
+#define CAN4TXDSR0_DB3 _CAN4TXDSR0.Bits.DB3\r
+#define CAN4TXDSR0_DB4 _CAN4TXDSR0.Bits.DB4\r
+#define CAN4TXDSR0_DB5 _CAN4TXDSR0.Bits.DB5\r
+#define CAN4TXDSR0_DB6 _CAN4TXDSR0.Bits.DB6\r
+#define CAN4TXDSR0_DB7 _CAN4TXDSR0.Bits.DB7\r
+#define CAN4TXDSR0_DB _CAN4TXDSR0.MergedBits.grpDB\r
+\r
+\r
+/*** CAN4TXDSR1 - MSCAN4 Transmit Data Segment Register 1; 0x000002B5 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN4TXDSR1STR;\r
+extern volatile CAN4TXDSR1STR _CAN4TXDSR1 @(REG_BASE + 0x000002B5);\r
+#define CAN4TXDSR1 _CAN4TXDSR1.Byte\r
+#define CAN4TXDSR1_DB0 _CAN4TXDSR1.Bits.DB0\r
+#define CAN4TXDSR1_DB1 _CAN4TXDSR1.Bits.DB1\r
+#define CAN4TXDSR1_DB2 _CAN4TXDSR1.Bits.DB2\r
+#define CAN4TXDSR1_DB3 _CAN4TXDSR1.Bits.DB3\r
+#define CAN4TXDSR1_DB4 _CAN4TXDSR1.Bits.DB4\r
+#define CAN4TXDSR1_DB5 _CAN4TXDSR1.Bits.DB5\r
+#define CAN4TXDSR1_DB6 _CAN4TXDSR1.Bits.DB6\r
+#define CAN4TXDSR1_DB7 _CAN4TXDSR1.Bits.DB7\r
+#define CAN4TXDSR1_DB _CAN4TXDSR1.MergedBits.grpDB\r
+\r
+\r
+/*** CAN4TXDSR2 - MSCAN4 Transmit Data Segment Register 2; 0x000002B6 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN4TXDSR2STR;\r
+extern volatile CAN4TXDSR2STR _CAN4TXDSR2 @(REG_BASE + 0x000002B6);\r
+#define CAN4TXDSR2 _CAN4TXDSR2.Byte\r
+#define CAN4TXDSR2_DB0 _CAN4TXDSR2.Bits.DB0\r
+#define CAN4TXDSR2_DB1 _CAN4TXDSR2.Bits.DB1\r
+#define CAN4TXDSR2_DB2 _CAN4TXDSR2.Bits.DB2\r
+#define CAN4TXDSR2_DB3 _CAN4TXDSR2.Bits.DB3\r
+#define CAN4TXDSR2_DB4 _CAN4TXDSR2.Bits.DB4\r
+#define CAN4TXDSR2_DB5 _CAN4TXDSR2.Bits.DB5\r
+#define CAN4TXDSR2_DB6 _CAN4TXDSR2.Bits.DB6\r
+#define CAN4TXDSR2_DB7 _CAN4TXDSR2.Bits.DB7\r
+#define CAN4TXDSR2_DB _CAN4TXDSR2.MergedBits.grpDB\r
+\r
+\r
+/*** CAN4TXDSR3 - MSCAN4 Transmit Data Segment Register 3; 0x000002B7 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN4TXDSR3STR;\r
+extern volatile CAN4TXDSR3STR _CAN4TXDSR3 @(REG_BASE + 0x000002B7);\r
+#define CAN4TXDSR3 _CAN4TXDSR3.Byte\r
+#define CAN4TXDSR3_DB0 _CAN4TXDSR3.Bits.DB0\r
+#define CAN4TXDSR3_DB1 _CAN4TXDSR3.Bits.DB1\r
+#define CAN4TXDSR3_DB2 _CAN4TXDSR3.Bits.DB2\r
+#define CAN4TXDSR3_DB3 _CAN4TXDSR3.Bits.DB3\r
+#define CAN4TXDSR3_DB4 _CAN4TXDSR3.Bits.DB4\r
+#define CAN4TXDSR3_DB5 _CAN4TXDSR3.Bits.DB5\r
+#define CAN4TXDSR3_DB6 _CAN4TXDSR3.Bits.DB6\r
+#define CAN4TXDSR3_DB7 _CAN4TXDSR3.Bits.DB7\r
+#define CAN4TXDSR3_DB _CAN4TXDSR3.MergedBits.grpDB\r
+\r
+\r
+/*** CAN4TXDSR4 - MSCAN4 Transmit Data Segment Register 4; 0x000002B8 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN4TXDSR4STR;\r
+extern volatile CAN4TXDSR4STR _CAN4TXDSR4 @(REG_BASE + 0x000002B8);\r
+#define CAN4TXDSR4 _CAN4TXDSR4.Byte\r
+#define CAN4TXDSR4_DB0 _CAN4TXDSR4.Bits.DB0\r
+#define CAN4TXDSR4_DB1 _CAN4TXDSR4.Bits.DB1\r
+#define CAN4TXDSR4_DB2 _CAN4TXDSR4.Bits.DB2\r
+#define CAN4TXDSR4_DB3 _CAN4TXDSR4.Bits.DB3\r
+#define CAN4TXDSR4_DB4 _CAN4TXDSR4.Bits.DB4\r
+#define CAN4TXDSR4_DB5 _CAN4TXDSR4.Bits.DB5\r
+#define CAN4TXDSR4_DB6 _CAN4TXDSR4.Bits.DB6\r
+#define CAN4TXDSR4_DB7 _CAN4TXDSR4.Bits.DB7\r
+#define CAN4TXDSR4_DB _CAN4TXDSR4.MergedBits.grpDB\r
+\r
+\r
+/*** CAN4TXDSR5 - MSCAN4 Transmit Data Segment Register 5; 0x000002B9 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN4TXDSR5STR;\r
+extern volatile CAN4TXDSR5STR _CAN4TXDSR5 @(REG_BASE + 0x000002B9);\r
+#define CAN4TXDSR5 _CAN4TXDSR5.Byte\r
+#define CAN4TXDSR5_DB0 _CAN4TXDSR5.Bits.DB0\r
+#define CAN4TXDSR5_DB1 _CAN4TXDSR5.Bits.DB1\r
+#define CAN4TXDSR5_DB2 _CAN4TXDSR5.Bits.DB2\r
+#define CAN4TXDSR5_DB3 _CAN4TXDSR5.Bits.DB3\r
+#define CAN4TXDSR5_DB4 _CAN4TXDSR5.Bits.DB4\r
+#define CAN4TXDSR5_DB5 _CAN4TXDSR5.Bits.DB5\r
+#define CAN4TXDSR5_DB6 _CAN4TXDSR5.Bits.DB6\r
+#define CAN4TXDSR5_DB7 _CAN4TXDSR5.Bits.DB7\r
+#define CAN4TXDSR5_DB _CAN4TXDSR5.MergedBits.grpDB\r
+\r
+\r
+/*** CAN4TXDSR6 - MSCAN4 Transmit Data Segment Register 6; 0x000002BA ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN4TXDSR6STR;\r
+extern volatile CAN4TXDSR6STR _CAN4TXDSR6 @(REG_BASE + 0x000002BA);\r
+#define CAN4TXDSR6 _CAN4TXDSR6.Byte\r
+#define CAN4TXDSR6_DB0 _CAN4TXDSR6.Bits.DB0\r
+#define CAN4TXDSR6_DB1 _CAN4TXDSR6.Bits.DB1\r
+#define CAN4TXDSR6_DB2 _CAN4TXDSR6.Bits.DB2\r
+#define CAN4TXDSR6_DB3 _CAN4TXDSR6.Bits.DB3\r
+#define CAN4TXDSR6_DB4 _CAN4TXDSR6.Bits.DB4\r
+#define CAN4TXDSR6_DB5 _CAN4TXDSR6.Bits.DB5\r
+#define CAN4TXDSR6_DB6 _CAN4TXDSR6.Bits.DB6\r
+#define CAN4TXDSR6_DB7 _CAN4TXDSR6.Bits.DB7\r
+#define CAN4TXDSR6_DB _CAN4TXDSR6.MergedBits.grpDB\r
+\r
+\r
+/*** CAN4TXDSR7 - MSCAN4 Transmit Data Segment Register 7; 0x000002BB ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CAN4TXDSR7STR;\r
+extern volatile CAN4TXDSR7STR _CAN4TXDSR7 @(REG_BASE + 0x000002BB);\r
+#define CAN4TXDSR7 _CAN4TXDSR7.Byte\r
+#define CAN4TXDSR7_DB0 _CAN4TXDSR7.Bits.DB0\r
+#define CAN4TXDSR7_DB1 _CAN4TXDSR7.Bits.DB1\r
+#define CAN4TXDSR7_DB2 _CAN4TXDSR7.Bits.DB2\r
+#define CAN4TXDSR7_DB3 _CAN4TXDSR7.Bits.DB3\r
+#define CAN4TXDSR7_DB4 _CAN4TXDSR7.Bits.DB4\r
+#define CAN4TXDSR7_DB5 _CAN4TXDSR7.Bits.DB5\r
+#define CAN4TXDSR7_DB6 _CAN4TXDSR7.Bits.DB6\r
+#define CAN4TXDSR7_DB7 _CAN4TXDSR7.Bits.DB7\r
+#define CAN4TXDSR7_DB _CAN4TXDSR7.MergedBits.grpDB\r
+\r
+\r
+/*** CAN4TXDLR - MSCAN4 Transmit Data Length Register; 0x000002BC ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DLC0 :1; /* Data Length Code Bit 0 */\r
+ byte DLC1 :1; /* Data Length Code Bit 1 */\r
+ byte DLC2 :1; /* Data Length Code Bit 2 */\r
+ byte DLC3 :1; /* Data Length Code Bit 3 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpDLC :4;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CAN4TXDLRSTR;\r
+extern volatile CAN4TXDLRSTR _CAN4TXDLR @(REG_BASE + 0x000002BC);\r
+#define CAN4TXDLR _CAN4TXDLR.Byte\r
+#define CAN4TXDLR_DLC0 _CAN4TXDLR.Bits.DLC0\r
+#define CAN4TXDLR_DLC1 _CAN4TXDLR.Bits.DLC1\r
+#define CAN4TXDLR_DLC2 _CAN4TXDLR.Bits.DLC2\r
+#define CAN4TXDLR_DLC3 _CAN4TXDLR.Bits.DLC3\r
+#define CAN4TXDLR_DLC _CAN4TXDLR.MergedBits.grpDLC\r
+\r
+\r
+/*** CAN4TXTBPR - MSCAN4 Transmit Transmit Buffer Priority; 0x000002BF ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PRIO0 :1; /* Transmit Buffer Priority Bit 0 */\r
+ byte PRIO1 :1; /* Transmit Buffer Priority Bit 1 */\r
+ byte PRIO2 :1; /* Transmit Buffer Priority Bit 2 */\r
+ byte PRIO3 :1; /* Transmit Buffer Priority Bit 3 */\r
+ byte PRIO4 :1; /* Transmit Buffer Priority Bit 4 */\r
+ byte PRIO5 :1; /* Transmit Buffer Priority Bit 5 */\r
+ byte PRIO6 :1; /* Transmit Buffer Priority Bit 6 */\r
+ byte PRIO7 :1; /* Transmit Buffer Priority Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpPRIO :8;\r
+ } MergedBits;\r
+} CAN4TXTBPRSTR;\r
+extern volatile CAN4TXTBPRSTR _CAN4TXTBPR @(REG_BASE + 0x000002BF);\r
+#define CAN4TXTBPR _CAN4TXTBPR.Byte\r
+#define CAN4TXTBPR_PRIO0 _CAN4TXTBPR.Bits.PRIO0\r
+#define CAN4TXTBPR_PRIO1 _CAN4TXTBPR.Bits.PRIO1\r
+#define CAN4TXTBPR_PRIO2 _CAN4TXTBPR.Bits.PRIO2\r
+#define CAN4TXTBPR_PRIO3 _CAN4TXTBPR.Bits.PRIO3\r
+#define CAN4TXTBPR_PRIO4 _CAN4TXTBPR.Bits.PRIO4\r
+#define CAN4TXTBPR_PRIO5 _CAN4TXTBPR.Bits.PRIO5\r
+#define CAN4TXTBPR_PRIO6 _CAN4TXTBPR.Bits.PRIO6\r
+#define CAN4TXTBPR_PRIO7 _CAN4TXTBPR.Bits.PRIO7\r
+#define CAN4TXTBPR_PRIO _CAN4TXTBPR.MergedBits.grpPRIO\r
+\r
+\r
+/*** BDMSTS - BDM Status Register; 0x0000FF01 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte UNSEC :1; /* Unsecure */\r
+ byte CLKSW :1; /* Clock switch */\r
+ byte TRACE :1; /* TRACE1 BDM firmware command is being executed */\r
+ byte SDV :1; /* Shift data valid */\r
+ byte ENTAG :1; /* Tagging enable */\r
+ byte BDMACT :1; /* BDM active status */\r
+ byte ENBDM :1; /* Enable BDM */\r
+ } Bits;\r
+} BDMSTSSTR;\r
+extern volatile BDMSTSSTR _BDMSTS @(0x0000FF01);\r
+#define BDMSTS _BDMSTS.Byte\r
+#define BDMSTS_UNSEC _BDMSTS.Bits.UNSEC\r
+#define BDMSTS_CLKSW _BDMSTS.Bits.CLKSW\r
+#define BDMSTS_TRACE _BDMSTS.Bits.TRACE\r
+#define BDMSTS_SDV _BDMSTS.Bits.SDV\r
+#define BDMSTS_ENTAG _BDMSTS.Bits.ENTAG\r
+#define BDMSTS_BDMACT _BDMSTS.Bits.BDMACT\r
+#define BDMSTS_ENBDM _BDMSTS.Bits.ENBDM\r
+\r
+\r
+/*** BDMCCR - BDM CCR Holding Register; 0x0000FF06 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte CCR0 :1; /* BDM CCR Holding Bit 0 */\r
+ byte CCR1 :1; /* BDM CCR Holding Bit 1 */\r
+ byte CCR2 :1; /* BDM CCR Holding Bit 2 */\r
+ byte CCR3 :1; /* BDM CCR Holding Bit 3 */\r
+ byte CCR4 :1; /* BDM CCR Holding Bit 4 */\r
+ byte CCR5 :1; /* BDM CCR Holding Bit 5 */\r
+ byte CCR6 :1; /* BDM CCR Holding Bit 6 */\r
+ byte CCR7 :1; /* BDM CCR Holding Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpCCR :8;\r
+ } MergedBits;\r
+} BDMCCRSTR;\r
+extern volatile BDMCCRSTR _BDMCCR @(0x0000FF06);\r
+#define BDMCCR _BDMCCR.Byte\r
+#define BDMCCR_CCR0 _BDMCCR.Bits.CCR0\r
+#define BDMCCR_CCR1 _BDMCCR.Bits.CCR1\r
+#define BDMCCR_CCR2 _BDMCCR.Bits.CCR2\r
+#define BDMCCR_CCR3 _BDMCCR.Bits.CCR3\r
+#define BDMCCR_CCR4 _BDMCCR.Bits.CCR4\r
+#define BDMCCR_CCR5 _BDMCCR.Bits.CCR5\r
+#define BDMCCR_CCR6 _BDMCCR.Bits.CCR6\r
+#define BDMCCR_CCR7 _BDMCCR.Bits.CCR7\r
+#define BDMCCR_CCR _BDMCCR.MergedBits.grpCCR\r
+\r
+\r
+/*** BDMINR - BDM Internal Register Position Register; 0x0000FF07 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte REG11 :1; /* Internal register map position */\r
+ byte REG12 :1; /* Internal register map position */\r
+ byte REG13 :1; /* Internal register map position */\r
+ byte REG14 :1; /* Internal register map position */\r
+ byte REG15 :1; /* Internal register map position */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpREG_11 :5;\r
+ } MergedBits;\r
+} BDMINRSTR;\r
+extern volatile BDMINRSTR _BDMINR @(0x0000FF07);\r
+#define BDMINR _BDMINR.Byte\r
+#define BDMINR_REG11 _BDMINR.Bits.REG11\r
+#define BDMINR_REG12 _BDMINR.Bits.REG12\r
+#define BDMINR_REG13 _BDMINR.Bits.REG13\r
+#define BDMINR_REG14 _BDMINR.Bits.REG14\r
+#define BDMINR_REG15 _BDMINR.Bits.REG15\r
+#define BDMINR_REG_11 _BDMINR.MergedBits.grpREG_11\r
+#define BDMINR_REG BDMINR_REG_11\r
+\r
+\r
+ /* Watchdog reset macro */\r
+#ifdef _lint\r
+ #define __RESET_WATCHDOG() /* empty */\r
+#else\r
+ #define __RESET_WATCHDOG() {asm sta COPCTL;} /* Just write a byte to feed the dog */\r
+#endif\r
+\r
+#endif\r
+\r
+/*\r
+** ###################################################################\r
+**\r
+** This file was created by UNIS Processor Expert 03.33 for \r
+** the Motorola HCS12 series of microcontrollers.\r
+**\r
+** ###################################################################\r
+*/\r
+\r
--- /dev/null
+/* ================================================================================================================================= **\r
+** ================================================================================================================================= **\r
+** CONFIGURATION FILE FOR PESL LIBRARY **\r
+** ================================================================================================================================= **\r
+** ================================================================================================================================= */\r
+\r
+#define _MC9S12A128_112 1\r
+#define _MC9S12A128_80 2\r
+#define _MC9S12A256_112 3\r
+#define _MC9S12A256_80 4\r
+#define _MC9S12A64_112 5\r
+#define _MC9S12A64_80 6\r
+#define _MC9S12C32_48 7\r
+#define _MC9S12C32_52 8\r
+#define _MC9S12C32_80 9\r
+#define _MC9S12D64_112 10\r
+#define _MC9S12D64_80 11\r
+#define _MC9S12DB128_112 12\r
+#define _MC9S12DG128_112 13\r
+#define _MC9S12DG128_80 14\r
+#define _MC9S12DG256_112 15\r
+#define _MC9S12DJ128_112 16\r
+#define _MC9S12DJ128_80 17\r
+#define _MC9S12DJ256_112 18\r
+#define _MC9S12DJ256_80 19\r
+#define _MC9S12DJ64_112 20\r
+#define _MC9S12DJ64_80 21\r
+#define _MC9S12DP256_112 22\r
+#define _MC9S12DT128_112 23\r
+#define _MC9S12DT256_112 24\r
+#define _MC9S12A32_80 25\r
+#define _MC9S12D32_80 26\r
+#define _MC9S12DP512_112 27\r
+#define _MC9S12A512_112 28\r
+#define _MC9S12E128_112 29\r
+#define _MC9S12E128_80 30\r
+#define _MC9S12E64_112 31\r
+\r
+\r
+/* Selected target MCU */\r
+\r
+#define CPUtype _MC9S12DP256_112\r
+\r
+\r
+/* PESL library */\r
+\r
+#pragma MESSAGE DISABLE C4000 /* WARNING C4000: Condition is always TRUE */\r
+#pragma MESSAGE DISABLE C4001 /* WARNING C4001: Condition is always FALSE */\r
+\r
+#include "PESLlib.h"\r
+\r
+\r
--- /dev/null
+/** ###################################################################\r
+** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.\r
+** Filename : PE_Const.H\r
+** Project : RTOSDemo\r
+** Processor : MC9S12DP256BCPV\r
+** Beantype : PE_Const\r
+** Version : Driver 01.00\r
+** Compiler : Metrowerks HC12 C Compiler\r
+** Date/Time : 13/06/2005, 20:14\r
+** Abstract :\r
+** This bean "PE_Const" contains internal definitions\r
+** of the constants.\r
+** Settings :\r
+** Contents :\r
+** No public methods\r
+**\r
+** (c) Copyright UNIS, spol. s r.o. 1997-2002\r
+** UNIS, spol. s r.o.\r
+** Jundrovska 33\r
+** 624 00 Brno\r
+** Czech Republic\r
+** http : www.processorexpert.com\r
+** mail : info@processorexpert.com\r
+** ###################################################################*/\r
+\r
+#ifndef __PE_Const_H\r
+#define __PE_Const_H\r
+\r
+/* Constants for detecting running mode */\r
+#define HIGH_SPEED 0 /* High speed */\r
+#define LOW_SPEED 1 /* Low speed */\r
+#define SLOW_SPEED 2 /* Slow speed */\r
+\r
+/* Reset cause constants */\r
+#define RSTSRC_POR 1 /* Power-on reset */\r
+#define RSTSRC_PIN 8 /* External reset bit */\r
+#define RSTSRC_COP 4 /* COP reset */\r
+#define RSTSRC_ILOP 2 /* Illegal opcode reset */\r
+#define RSTSRC_ILAD 16 /* Illegal address reset */\r
+#define RSTSRC_LVI 32 /* Low voltage inhibit reset */\r
+\r
+#endif /* _PE_Const_H */\r
+/*\r
+** ###################################################################\r
+**\r
+** This file was created by UNIS Processor Expert 03.33 for \r
+** the Motorola HCS12 series of microcontrollers.\r
+**\r
+** ###################################################################\r
+*/\r
--- /dev/null
+/** ###################################################################\r
+** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.\r
+** Filename : PE_Error.H\r
+** Project : RTOSDemo\r
+** Processor : MC9S12DP256BCPV\r
+** Beantype : PE_Error\r
+** Version : Driver 01.00\r
+** Compiler : Metrowerks HC12 C Compiler\r
+** Date/Time : 13/06/2005, 20:14\r
+** Abstract :\r
+** This bean "PE_Error" contains internal definitions\r
+** of the error constants.\r
+** Settings :\r
+** Contents :\r
+** No public methods\r
+**\r
+** (c) Copyright UNIS, spol. s r.o. 1997-2002\r
+** UNIS, spol. s r.o.\r
+** Jundrovska 33\r
+** 624 00 Brno\r
+** Czech Republic\r
+** http : www.processorexpert.com\r
+** mail : info@processorexpert.com\r
+** ###################################################################*/\r
+\r
+#ifndef __PE_Error_H\r
+#define __PE_Error_H\r
+\r
+#define ERR_OK 0 /* OK */\r
+#define ERR_SPEED 1 /* This device does not work in the active speed mode. */\r
+#define ERR_RANGE 2 /* Parameter out of range. */\r
+#define ERR_VALUE 3 /* Parameter of incorrect value. */\r
+#define ERR_OVERFLOW 4 /* Timer overflow. */\r
+#define ERR_MATH 5 /* Overflow during evaluation. */\r
+#define ERR_ENABLED 6 /* Device is enabled. */\r
+#define ERR_DISABLED 7 /* Device is disabled. */\r
+#define ERR_BUSY 8 /* Device is busy. */\r
+#define ERR_NOTAVAIL 9 /* Requested value or method not available. */\r
+#define ERR_RXEMPTY 10 /* No data in receiver. */\r
+#define ERR_TXFULL 11 /* Transmitter is full. */\r
+#define ERR_BUSOFF 12 /* Bus not available. */\r
+#define ERR_OVERRUN 13 /* Overrun error is detected. */\r
+#define ERR_FRAMING 14 /* Framing error is detected. */\r
+#define ERR_PARITY 15 /* Parity error is detected. */\r
+#define ERR_NOISE 16 /* Noise error is detected. */\r
+#define ERR_IDLE 17 /* Idle error is detectes. */\r
+#define ERR_FAULT 18 /* Fault error is detected. */\r
+#define ERR_BREAK 19 /* Break char is received during communication. */\r
+#define ERR_CRC 20 /* CRC error is detected. */\r
+#define ERR_ARBITR 21 /* A node losts arbitration. This error occurs if two nodes start transmission at the same time. */\r
+#define ERR_PROTECT 22 /* Protection error is detected. */\r
+\r
+#endif __PE_Error_H\r
--- /dev/null
+/** ###################################################################\r
+** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.\r
+** Filename : PE_Timer.C\r
+** Project : RTOSDemo\r
+** Processor : MC9S12DP256BCPV\r
+** Beantype : PE_Timer\r
+** Version : Driver 01.00\r
+** Compiler : Metrowerks HC12 C Compiler\r
+** Date/Time : 14/06/2005, 16:34\r
+** Abstract :\r
+** This bean "PE_Timer" implements internal methods and definitions\r
+** used by beans working with timers.\r
+** Settings :\r
+** Contents :\r
+** No public methods\r
+**\r
+** (c) Copyright UNIS, spol. s r.o. 1997-2002\r
+** UNIS, spol. s r.o.\r
+** Jundrovska 33\r
+** 624 00 Brno\r
+** Czech Republic\r
+** http : www.processorexpert.com\r
+** mail : info@processorexpert.com\r
+** ###################################################################*/\r
+\r
+\r
+/* MODULE PE_Timer. */\r
+\r
+#include "PE_Timer.h"\r
+\r
+\r
+\r
+typedef unsigned long UINT32;\r
+\r
+typedef union {\r
+ UINT32 val;\r
+ struct {\r
+ unsigned short hi16,lo16;\r
+ } s;\r
+} OP_UINT32;\r
+\r
+typedef struct {\r
+ unsigned short dummy;\r
+ UINT32 mid;\r
+} M_UINT32;\r
+\r
+typedef struct {\r
+ UINT32 hi32, lo32;\r
+} UINT64;\r
+\r
+typedef union {\r
+ UINT64 val;\r
+ M_UINT32 m; \r
+} OP_UINT64;\r
+\r
+/*\r
+** ===================================================================\r
+** Method : PE_Timer_LngMul (bean PE_Timer)\r
+**\r
+** Description :\r
+** This method is internal. It is used by Processor Expert\r
+** only.\r
+** ===================================================================\r
+*/\r
+void PE_Timer_LngMul(dword va1, dword va2, dlong *var)\r
+{\r
+ OP_UINT32 *va = (OP_UINT32*)&va1;\r
+ OP_UINT32 *vb = (OP_UINT32*)&va2;\r
+ OP_UINT64 *vr = (OP_UINT64*)var;\r
+ \r
+ vr->val.hi32 = 0UL;\r
+ vr->val.lo32 = ((UINT32)va->s.lo16)*((UINT32)vb->s.lo16);\r
+ {\r
+ OP_UINT32 tmp;\r
+ \r
+ tmp.val = ((UINT32)va->s.lo16)*((UINT32)vb->s.hi16);\r
+ vr->m.mid += (UINT32)tmp.s.lo16;\r
+ vr->val.hi32 += (UINT32)tmp.s.hi16;\r
+ }\r
+ {\r
+ OP_UINT32 tmp;\r
+ \r
+ tmp.val = ((UINT32)va->s.hi16)*((UINT32)vb->s.lo16);\r
+ vr->m.mid += (UINT32)tmp.s.lo16;\r
+ vr->val.hi32 += (UINT32)tmp.s.hi16;\r
+ }\r
+ vr->val.hi32 += ((UINT32)va->s.hi16)*((UINT32)vb->s.hi16);\r
+}\r
+\r
+/*\r
+** ===================================================================\r
+** Method : PE_Timer_LngHi1 (bean PE_Timer)\r
+**\r
+** Description :\r
+** This method is internal. It is used by Processor Expert\r
+** only.\r
+** ===================================================================\r
+*/\r
+bool PE_Timer_LngHi1(dword High, dword Low, word *Out) \r
+{\r
+ if ((High == 0) && ((Low >> 24) == 0)) \r
+ if ((Low & 0x80) != 0) {\r
+ if ((Low >> 8) < 0xFFFF) {\r
+ *Out = ((unsigned int)(Low >> 8))+1;\r
+ return FALSE;\r
+ } \r
+ } \r
+ else {\r
+ *Out = (unsigned int)(Low >> 8);\r
+ return FALSE;\r
+ } \r
+ *Out = (unsigned int)(Low >> 8);\r
+ return TRUE;\r
+}\r
+\r
+/*\r
+** ===================================================================\r
+** Method : PE_Timer_LngHi2 (bean PE_Timer)\r
+**\r
+** Description :\r
+** This method is internal. It is used by Processor Expert\r
+** only.\r
+** ===================================================================\r
+*/\r
+bool PE_Timer_LngHi2(dword High, dword Low, word *Out) \r
+{\r
+ if (High == 0) \r
+ if ((Low & 0x8000) != 0) {\r
+ if ((Low >> 16) < 0xFFFF) {\r
+ *Out = ((unsigned int)(Low >> 16))+1;\r
+ return FALSE;\r
+ } \r
+ }\r
+ else {\r
+ *Out = (unsigned int)(Low >> 16);\r
+ return FALSE;\r
+ } \r
+ *Out = (unsigned int)(Low >> 16);\r
+ return TRUE;\r
+}\r
+\r
+/*\r
+** ===================================================================\r
+** Method : PE_Timer_LngHi3 (bean PE_Timer)\r
+**\r
+** Description :\r
+** This method is internal. It is used by Processor Expert\r
+** only.\r
+** ===================================================================\r
+*/\r
+bool PE_Timer_LngHi3(dword High, dword Low, word *Out) \r
+{\r
+ if ((High >> 8) == 0)\r
+ if ((Low & 0x800000) != 0) {\r
+ if (((Low >> 24) | (High << 8)) < 0xFFFF) {\r
+ *Out = ((unsigned int)((Low >> 24) | (High << 8)))+1;\r
+ return FALSE;\r
+ } \r
+ } \r
+ else { \r
+ *Out = (unsigned int)((Low >> 24) | (High << 8));\r
+ return FALSE;\r
+ } \r
+ *Out = (unsigned int)((Low >> 24) | (High << 8));\r
+ return TRUE;\r
+}\r
+\r
+/*\r
+** ===================================================================\r
+** Method : PE_Timer_LngHi4 (bean PE_Timer)\r
+**\r
+** Description :\r
+** This method is internal. It is used by Processor Expert\r
+** only.\r
+** ===================================================================\r
+*/\r
+bool PE_Timer_LngHi4(dword High, dword Low, word *Out) \r
+{\r
+ if ((High >> 16) == 0) \r
+ if ((Low & 0x80000000) != 0) {\r
+ if (High < 0xFFFF) {\r
+ *Out = ((unsigned int)High)+1;\r
+ return FALSE;\r
+ } \r
+ } \r
+ else { \r
+ *Out = (unsigned int)High;\r
+ return FALSE;\r
+ } \r
+ *Out = (unsigned int)High;\r
+ return TRUE;\r
+}\r
+\r
+\r
+\r
+/* END PE_Timer. */\r
+\r
+/*\r
+** ###################################################################\r
+**\r
+** This file was created by UNIS Processor Expert 03.33 for \r
+** the Motorola HCS12 series of microcontrollers.\r
+**\r
+** ###################################################################\r
+*/\r
--- /dev/null
+/** ###################################################################\r
+** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.\r
+** Filename : PE_Timer.H\r
+** Project : RTOSDemo\r
+** Processor : MC9S12DP256BCPV\r
+** Beantype : PE_Timer\r
+** Version : Driver 01.00\r
+** Compiler : Metrowerks HC12 C Compiler\r
+** Date/Time : 14/06/2005, 16:34\r
+** Abstract :\r
+** This bean "PE_Timer" implements internal methods and definitions\r
+** used by beans working with timers.\r
+** Settings :\r
+** Contents :\r
+** No public methods\r
+**\r
+** (c) Copyright UNIS, spol. s r.o. 1997-2002\r
+** UNIS, spol. s r.o.\r
+** Jundrovska 33\r
+** 624 00 Brno\r
+** Czech Republic\r
+** http : www.processorexpert.com\r
+** mail : info@processorexpert.com\r
+** ###################################################################*/\r
+#ifndef __PE_Timer\r
+#define __PE_Timer\r
+/*Include shared modules, which are used for whole project*/\r
+#include "PE_types.h"\r
+#include "PE_const.h"\r
+\r
+/* MODULE PE_Timer. */\r
+\r
+void PE_Timer_LngMul(dword va1, dword va2, dlong *var);\r
+/*\r
+** ===================================================================\r
+** Method : PE_Timer_LngMul (bean PE_Timer)\r
+**\r
+** Description :\r
+** This method is internal. It is used by Processor Expert\r
+** only.\r
+** ===================================================================\r
+*/\r
+\r
+bool PE_Timer_LngHi1(dword Low, dword High, word *Out);\r
+/*\r
+** ===================================================================\r
+** Method : PE_Timer_LngHi1 (bean PE_Timer)\r
+**\r
+** Description :\r
+** This method is internal. It is used by Processor Expert\r
+** only.\r
+** ===================================================================\r
+*/\r
+\r
+bool PE_Timer_LngHi2(dword Low, dword High, word *Out);\r
+/*\r
+** ===================================================================\r
+** Method : PE_Timer_LngHi2 (bean PE_Timer)\r
+**\r
+** Description :\r
+** This method is internal. It is used by Processor Expert\r
+** only.\r
+** ===================================================================\r
+*/\r
+\r
+bool PE_Timer_LngHi3(dword Low, dword High, word *Out);\r
+/*\r
+** ===================================================================\r
+** Method : PE_Timer_LngHi3 (bean PE_Timer)\r
+**\r
+** Description :\r
+** This method is internal. It is used by Processor Expert\r
+** only.\r
+** ===================================================================\r
+*/\r
+\r
+bool PE_Timer_LngHi4(dword Low, dword High, word *Out);\r
+/*\r
+** ===================================================================\r
+** Method : PE_Timer_LngHi4 (bean PE_Timer)\r
+**\r
+** Description :\r
+** This method is internal. It is used by Processor Expert\r
+** only.\r
+** ===================================================================\r
+*/\r
+\r
+\r
+#endif /* END PE_Timer. */\r
+/*\r
+** ###################################################################\r
+**\r
+** This file was created by UNIS Processor Expert 03.33 for \r
+** the Motorola HCS12 series of microcontrollers.\r
+**\r
+** ###################################################################\r
+*/\r
--- /dev/null
+/** ###################################################################\r
+** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.\r
+** Filename : PE_Types.H\r
+** Project : RTOSDemo\r
+** Processor : MC9S12DP256BCPV\r
+** Beantype : PE_Types\r
+** Version : Driver 01.04\r
+** Compiler : Metrowerks HC12 C Compiler\r
+** Date/Time : 13/06/2005, 20:14\r
+** Abstract :\r
+** This bean "PE_Types" contains internal definitions\r
+** of the types.\r
+** Settings :\r
+** Contents :\r
+** No public methods\r
+**\r
+** (c) Copyright UNIS, spol. s r.o. 1997-2002\r
+** UNIS, spol. s r.o.\r
+** Jundrovska 33\r
+** 624 00 Brno\r
+** Czech Republic\r
+** http : www.processorexpert.com\r
+** mail : info@processorexpert.com\r
+** ###################################################################*/\r
+\r
+#ifndef __PE_Types_H\r
+#define __PE_Types_H\r
+\r
+#define FALSE 0\r
+#define TRUE 1\r
+\r
+/*Types definition*/\r
+typedef unsigned char bool;\r
+typedef unsigned char byte;\r
+typedef unsigned int word;\r
+typedef unsigned long dword;\r
+typedef unsigned long dlong[2];\r
+typedef void (*tIntFunc)(void);\r
+\r
+/* Motorola types */\r
+typedef unsigned char VUINT8;\r
+typedef signed char VINT8;\r
+typedef unsigned short int VUINT16;\r
+typedef signed short int VINT16;\r
+typedef unsigned long int VUINT32;\r
+\r
+#define in16(var,l,h) var = ((word)(l)) | (((word)(h)) << 8)\r
+#define out16(l,h,val) { l = (byte)val; h = (byte)(val >> 8); }\r
+\r
+#define output(P, V) P = (V)\r
+#define input(P) (P)\r
+\r
+#define __DI() { asm sei; } /* Disable global interrupts */\r
+#define __EI() { asm cli; } /* Enable global interrupts */\r
+#define EnterCritical() { __asm pshc; __asm sei; __asm movb 1,SP+,CCR_reg; } /* This macro is used by Processor Expert. It saves CCR register and disable global interrupts. */\r
+#define ExitCritical() { __asm movb CCR_reg, 1,-SP; __asm pulc; } /* This macro is used by Processor Expert. It restores CCR register saved in SaveStatusReg(). */\r
+/* obsolete definition for backward compatibility */\r
+#define SaveStatusReg() EnterCritical()\r
+#define RestoreStatusReg() ExitCritical()\r
+\r
+\r
+typedef struct { /* Black&White Image */\r
+ word width; /* Image width */\r
+ word height; /* Image height */\r
+ byte *pixmap; /* Image pixel bitmap */\r
+ word size; /* Image size */\r
+ char *name; /* Image name */\r
+} TIMAGE;\r
+typedef TIMAGE* PIMAGE ; /* Pointer to image */\r
+\r
+/* 16-bit register (Motorola format - big endian) */\r
+typedef union {\r
+ word w;\r
+ struct {\r
+ byte high,low;\r
+ } b;\r
+} TWREG;\r
+\r
+#endif /* __PE_Types_H */\r
+/*\r
+** ###################################################################\r
+**\r
+** This file was created by UNIS Processor Expert 03.33 for \r
+** the Motorola HCS12 series of microcontrollers.\r
+**\r
+** ###################################################################\r
+*/\r
--- /dev/null
+/** ###################################################################\r
+** Filename : RTOSDemo.C\r
+** Project : RTOSDemo\r
+** Processor : MC9S12DP256BCPV\r
+** Version : Driver 01.05\r
+** Compiler : Metrowerks HC12 C Compiler\r
+** Date/Time : 13/06/2005, 20:14\r
+** Abstract :\r
+** Main module. \r
+** Here is to be placed user's code.\r
+** Settings :\r
+** Contents :\r
+** No public methods\r
+**\r
+** (c) Copyright UNIS, spol. s r.o. 1997-2002\r
+** UNIS, spol. s r.o.\r
+** Jundrovska 33\r
+** 624 00 Brno\r
+** Czech Republic\r
+** http : www.processorexpert.com\r
+** mail : info@processorexpert.com\r
+** ###################################################################*/\r
+/* MODULE RTOSDemo */\r
+\r
+/* Including used modules for compilling procedure */\r
+#include "Cpu.h"\r
+#include "Events.h"\r
+#include "TickTimer.h"\r
+#include "Byte1.h"\r
+#include "COM0.h"\r
+/* Include shared modules, which are used for whole project */\r
+#include "PE_Types.h"\r
+#include "PE_Error.h"\r
+#include "PE_Const.h"\r
+#include "IO_Map.h"\r
+\r
+extern void vMain( void );\r
+\r
+void main(void)\r
+{\r
+ /*** Processor Expert internal initialization. DON'T REMOVE THIS CODE!!! ***/\r
+ PE_low_level_init();\r
+ /*** End of Processor Expert internal initialization. ***/\r
+\r
+ /*Write your code here*/\r
+\r
+ /* Just jump to the real main(). */\r
+ __asm\r
+ {\r
+ jmp vMain\r
+ }\r
+ \r
+\r
+ /*** Processor Expert end of main routine. DON'T MODIFY THIS CODE!!! ***/\r
+ for(;;);\r
+ /*** Processor Expert end of main routine. DON'T WRITE CODE BELOW!!! ***/\r
+} /*** End of main routine. DO NOT MODIFY THIS TEXT!!! ***/\r
+\r
+/* END RTOSDemo */\r
+/*\r
+** ###################################################################\r
+**\r
+** This file was created by UNIS Processor Expert 03.33 for \r
+** the Motorola HCS12 series of microcontrollers.\r
+**\r
+** ###################################################################\r
+*/\r
--- /dev/null
+/*\r
+** ###################################################################\r
+** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.\r
+** Filename : RTOSDemo.PRM\r
+** Project : RTOSDemo\r
+** Processor : MC9S12DP256BCPV\r
+** Compiler : Metrowerks HC12 C Compiler\r
+** Date/Time : 19/06/2005, 15:54\r
+** Abstract :\r
+** This file is used by the linker. It describes files to be linked,\r
+** memory ranges, stack size, etc. For detailed description of the PRM file\r
+** see CodeWarrior documentation. This file is generated by default.\r
+** You can switch off generation by setting the property\r
+** "Generate PRM file = no" on the "Build options" tab in CPU bean and then modify\r
+** this file if needed.\r
+**\r
+** (c) Copyright UNIS, spol. s r.o. 1997-2002\r
+** UNIS, spol. s r.o.\r
+** Jundrovska 33\r
+** 624 00 Brno\r
+** Czech Republic\r
+** http : www.processorexpert.com\r
+** mail : info@processorexpert.com\r
+** ###################################################################\r
+*/\r
+\r
+NAMES\r
+\r
+END\r
+\r
+SECTIONS\r
+ /* List of all sections specified on the "Build options" tab */\r
+ RAM = READ_WRITE 0x00001000 TO 0x00003FFF;\r
+ ROM_C000 = READ_ONLY 0x0000C000 TO 0x0000C511;\r
+ ROM_4000 = READ_ONLY 0x00004000 TO 0x00004255;\r
+ ROM_PAGE30 = READ_ONLY 0x00308000 TO 0x00308255;\r
+ ROM_PAGE31 = READ_ONLY 0x00318000 TO 0x00318255;\r
+ ROM_PAGE32 = READ_ONLY 0x00328000 TO 0x00328255;\r
+ ROM_PAGE33 = READ_ONLY 0x00338000 TO 0x00338255;\r
+ ROM_PAGE34 = READ_ONLY 0x00348000 TO 0x00348255;\r
+ ROM_PAGE35 = READ_ONLY 0x00358000 TO 0x00358255;\r
+ ROM_PAGE36 = READ_ONLY 0x00368000 TO 0x00368255;\r
+ ROM_PAGE37 = READ_ONLY 0x00378000 TO 0x00378255;\r
+ ROM_PAGE38 = READ_ONLY 0x00388000 TO 0x00388255;\r
+ ROM_PAGE39 = READ_ONLY 0x00398000 TO 0x00398255;\r
+ ROM_PAGE3A = READ_ONLY 0x003A8000 TO 0x003A8255;\r
+ ROM_PAGE3B = READ_ONLY 0x003B8000 TO 0x003B8255;\r
+ ROM_PAGE3C = READ_ONLY 0x003C8000 TO 0x003C8255;\r
+ ROM_PAGE3D = READ_ONLY 0x003D8000 TO 0x003D8255;\r
+END\r
+\r
+PLACEMENT\r
+ DEFAULT_RAM INTO RAM;\r
+ DEFAULT_ROM INTO ROM_PAGE30, ROM_PAGE31, ROM_PAGE32, ROM_PAGE33, ROM_PAGE34, ROM_PAGE35, ROM_PAGE36,\r
+ROM_PAGE37, ROM_PAGE38, ROM_PAGE39, ROM_PAGE3A, ROM_PAGE3B, ROM_PAGE3C, ROM_PAGE3D;\r
+ _PRESTART, STARTUP,\r
+ ROM_VAR, STRINGS,\r
+ NON_BANKED, COPY INTO ROM_C000, ROM_4000;\r
+END\r
+\r
+INIT _EntryPoint /* The entry point of the application. This function is generated into the CPU module. */\r
+\r
+STACKSIZE 0x0080 /* Size of the system stack. Value can be changed on the "Build options" tab */\r
+\r
--- /dev/null
+/** ###################################################################\r
+** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.\r
+** Filename : TickTimer.C\r
+** Project : RTOSDemo\r
+** Processor : MC9S12DP256BCPV\r
+** Beantype : TimerInt\r
+** Version : Bean 02.063, Driver 01.05, CPU db: 2.87.283\r
+** Compiler : Metrowerks HC12 C Compiler\r
+** Date/Time : 18/06/2005, 16:21\r
+** Abstract :\r
+** This bean "TimerInt" implements a periodic interrupt.\r
+** When the bean and its events are enabled, the "OnInterrupt"\r
+** event is called periodically with the period that you specify.\r
+** TimerInt supports also changing the period in runtime.\r
+** The source of periodic interrupt can be timer compare or reload \r
+** register or timer-overflow interrupt (of free running counter).\r
+** Settings :\r
+** Timer name : ECT (16-bit)\r
+** Compare name : TC0\r
+** Counter shared : No\r
+**\r
+** High-speed CPU mode\r
+** Prescaler : divide-by-8\r
+** Clock : 3124000 Hz\r
+** Initial period/frequency\r
+** Xtal ticks : 16000\r
+** microseconds : 1000\r
+** milliseconds : 1\r
+** seconds (real) : 0.0010000\r
+** Hz : 1000\r
+** kHz : 1\r
+**\r
+** Runtime setting : period/frequency interval (continual setting)\r
+** ticks : 16000 to 320000 ticks\r
+** microseconds : 1000 to 20000 microseconds\r
+** milliseconds : 1 to 20 milliseconds\r
+** seconds (real) : 0.0010000 to 0.0200000 seconds\r
+** Hz : 50 to 1000 Hz\r
+**\r
+** Initialization:\r
+** Timer : Enabled\r
+** Events : Enabled\r
+**\r
+** Timer registers\r
+** Counter : TCNT [68]\r
+** Mode : TIOS [64]\r
+** Run : TSCR1 [70]\r
+** Prescaler : TSCR2 [77]\r
+**\r
+** Compare registers\r
+** Compare : TC0 [80]\r
+**\r
+** Flip-flop registers\r
+** Mode : TCTL2 [73]\r
+** Contents :\r
+** Enable - byte TickTimer_Enable(void);\r
+** SetPeriodTicks16 - byte TickTimer_SetPeriodTicks16(word Ticks);\r
+** SetPeriodTicks32 - byte TickTimer_SetPeriodTicks32(dword Ticks);\r
+** SetPeriodUS - byte TickTimer_SetPeriodUS(word Time);\r
+** SetPeriodMS - byte TickTimer_SetPeriodMS(word Time);\r
+** SetFreqHz - byte TickTimer_SetFreqHz(word Freq);\r
+**\r
+** (c) Copyright UNIS, spol. s r.o. 1997-2002\r
+** UNIS, spol. s r.o.\r
+** Jundrovska 33\r
+** 624 00 Brno\r
+** Czech Republic\r
+** http : www.processorexpert.com\r
+** mail : info@processorexpert.com\r
+** ###################################################################*/\r
+\r
+\r
+/* MODULE TickTimer. */\r
+\r
+#include "Events.h"\r
+#include "TickTimer.h"\r
+\r
+/* Definition of DATA and CODE segments for this bean. User can specify where\r
+ these segments will be located on "Build options" tab of the selected CPU bean. */\r
+#pragma DATA_SEG TickTimer_DATA /* Data section for this module. */\r
+#pragma CODE_SEG TickTimer_CODE /* Code section for this module. */\r
+\r
+static word CmpHighVal; /* Compare register value for high speed CPU mode */\r
+\r
+\r
+/*\r
+** ===================================================================\r
+** Method : SetCV (bean TimerInt)\r
+**\r
+** Description :\r
+** This method is internal. It is used by Processor Expert\r
+** only.\r
+** ===================================================================\r
+*/\r
+static void SetCV(word Val)\r
+{\r
+ if (Val == 0) /* If the given value is zero */\r
+ Val = 65535; /* then change it to the maximal one */\r
+ TC0 = Val; /* Store given value to the compare register */\r
+ TC7 = Val; /* Store given value to the modulo register */\r
+}\r
+\r
+/*\r
+** ===================================================================\r
+** Method : SetPV (bean TimerInt)\r
+**\r
+** Description :\r
+** This method is internal. It is used by Processor Expert\r
+** only.\r
+** ===================================================================\r
+*/\r
+static void SetPV(byte Val)\r
+{\r
+ TSCR2_PR = Val; /* Store given value to the prescaler */\r
+}\r
+\r
+/*\r
+** ===================================================================\r
+** Method : HWEnDi (bean TimerInt)\r
+**\r
+** Description :\r
+** This method is internal. It is used by Processor Expert\r
+** only.\r
+** ===================================================================\r
+*/\r
+static void HWEnDi(void)\r
+{\r
+ TFLG1 = 1; /* Reset interrupt request flag */\r
+ TIE_C0I = 1; /* Enable interrupt */\r
+}\r
+\r
+/*\r
+** ===================================================================\r
+** Method : TickTimer_Enable (bean TimerInt)\r
+**\r
+** Description :\r
+** Enable the bean - it starts the timer. Events may be\r
+** generated ("DisableEvent"/"EnableEvent").\r
+** Parameters : None\r
+** Returns :\r
+** --- - Error code, possible codes:\r
+** ERR_OK - OK\r
+** ERR_SPEED - This device does not work in\r
+** the active speed mode\r
+** ===================================================================\r
+*/\r
+byte TickTimer_Enable(void)\r
+{\r
+ HWEnDi(); /* Enable the device */\r
+ return ERR_OK; /* OK */\r
+}\r
+\r
+/*\r
+** ===================================================================\r
+** Method : TickTimer_SetPeriodTicks16 (bean TimerInt)\r
+**\r
+** Description :\r
+** This method sets the new period of the generated events.\r
+** The period is expressed in Xtal ticks as a 16-bit unsigned\r
+** integer number.\r
+** This method is available only if runtime setting type\r
+** 'from interval' is selected in the Timing dialog box in\r
+** Runtime setting area.\r
+** Parameters :\r
+** NAME - DESCRIPTION\r
+** Ticks - Period to set [in Xtal ticks]\r
+** (16000 to 65535 ticks)\r
+** Returns :\r
+** --- - Error code, possible codes:\r
+** ERR_OK - OK\r
+** ERR_SPEED - This device does not work in\r
+** the active speed mode\r
+** ERR_MATH - Overflow during evaluation\r
+** ERR_RANGE - Parameter out of range\r
+** ===================================================================\r
+*/\r
+byte TickTimer_SetPeriodTicks16(word Ticks)\r
+{\r
+ dlong rtval; /* Result of two 32-bit numbers multiplication */\r
+ word rtword; /* Result of 64-bit number division */\r
+\r
+ if (Ticks < 16000) /* Is the given value out of range? */\r
+ return ERR_RANGE; /* If yes then error */\r
+ PE_Timer_LngMul((dword)Ticks,838592365,&rtval); /* Multiply given value and high speed CPU mode coefficient */\r
+ if (PE_Timer_LngHi4(rtval[0],rtval[1],&rtword)) /* Is the result greater or equal than 65536 ? */\r
+ rtword = 65535; /* If yes then use maximal possible value */\r
+ CmpHighVal = rtword; /* Store result (compare register value for high speed CPU mode) to the variable CmpHighVal */\r
+ SetCV(CmpHighVal); /* Store appropriate value to the compare register according to the selected high speed CPU mode */\r
+ return ERR_OK; /* OK */\r
+}\r
+\r
+/*\r
+** ===================================================================\r
+** Method : TickTimer_SetPeriodTicks32 (bean TimerInt)\r
+**\r
+** Description :\r
+** This method sets the new period of the generated events.\r
+** The period is expressed in Xtal ticks as a 32-bit unsigned\r
+** integer number.\r
+** This method is available only if runtime setting type\r
+** 'from interval' is selected in the Timing dialog box in\r
+** Runtime setting area.\r
+** Parameters :\r
+** NAME - DESCRIPTION\r
+** Ticks - Period to set [in Xtal ticks]\r
+** (16000 to 320000 ticks)\r
+** Returns :\r
+** --- - Error code, possible codes:\r
+** ERR_OK - OK\r
+** ERR_SPEED - This device does not work in\r
+** the active speed mode\r
+** ERR_MATH - Overflow during evaluation\r
+** ERR_RANGE - Parameter out of range\r
+** ===================================================================\r
+*/\r
+byte TickTimer_SetPeriodTicks32(dword Ticks)\r
+{\r
+ dlong rtval; /* Result of two 32-bit numbers multiplication */\r
+ word rtword; /* Result of 64-bit number division */\r
+\r
+ if ((Ticks > 320000) || (Ticks < 16000)) /* Is the given value out of range? */\r
+ return ERR_RANGE; /* Range error */\r
+ PE_Timer_LngMul(Ticks,838592365,&rtval); /* Multiply given value and high speed CPU mode coefficient */\r
+ if (PE_Timer_LngHi4(rtval[0],rtval[1],&rtword)) /* Is the result greater or equal than 65536 ? */\r
+ rtword = 65535; /* If yes then use maximal possible value */\r
+ CmpHighVal = rtword; /* Store result (compare register value for high speed CPU mode) to the variable CmpHighVal */\r
+ SetCV(CmpHighVal); /* Store appropriate value to the compare register according to the selected high speed CPU mode */\r
+ return ERR_OK; /* OK */\r
+}\r
+\r
+/*\r
+** ===================================================================\r
+** Method : TickTimer_SetPeriodUS (bean TimerInt)\r
+**\r
+** Description :\r
+** This method sets the new period of the generated events.\r
+** The period is expressed in microseconds as a 16-bit\r
+** unsigned integer number.\r
+** This method is available only if runtime setting type\r
+** 'from interval' is selected in the Timing dialog box in\r
+** Runtime setting area.\r
+** Parameters :\r
+** NAME - DESCRIPTION\r
+** Time - Period to set [in microseconds]\r
+** (1000 to 20000 microseconds)\r
+** Returns :\r
+** --- - Error code, possible codes:\r
+** ERR_OK - OK\r
+** ERR_SPEED - This device does not work in\r
+** the active speed mode\r
+** ERR_MATH - Overflow during evaluation\r
+** ERR_RANGE - Parameter out of range\r
+** ===================================================================\r
+*/\r
+byte TickTimer_SetPeriodUS(word Time)\r
+{\r
+ dlong rtval; /* Result of two 32-bit numbers multiplication */\r
+ word rtword; /* Result of 64-bit number division */\r
+\r
+ if ((Time > 20000) || (Time < 1000)) /* Is the given value out of range? */\r
+ return ERR_RANGE; /* If yes then error */\r
+ PE_Timer_LngMul((dword)Time,52412023,&rtval); /* Multiply given value and high speed CPU mode coefficient */\r
+ if (PE_Timer_LngHi3(rtval[0],rtval[1],&rtword)) /* Is the result greater or equal than 65536 ? */\r
+ rtword = 65535; /* If yes then use maximal possible value */\r
+ CmpHighVal = rtword; /* Store result (compare register value for high speed CPU mode) to the variable CmpHighVal */\r
+ SetCV(CmpHighVal); /* Store appropriate value to the compare register according to the selected high speed CPU mode */\r
+ return ERR_OK; /* OK */\r
+}\r
+\r
+/*\r
+** ===================================================================\r
+** Method : TickTimer_SetPeriodMS (bean TimerInt)\r
+**\r
+** Description :\r
+** This method sets the new period of the generated events.\r
+** The period is expressed in miliseconds as a 16-bit\r
+** unsigned integer number.\r
+** This method is available only if runtime setting type\r
+** 'from interval' is selected in the Timing dialog box in\r
+** Runtime setting area.\r
+** Parameters :\r
+** NAME - DESCRIPTION\r
+** Time - Period to set [in miliseconds]\r
+** (1 to 20 milliseconds)\r
+** Returns :\r
+** --- - Error code, possible codes:\r
+** ERR_OK - OK\r
+** ERR_SPEED - This device does not work in\r
+** the active speed mode\r
+** ERR_MATH - Overflow during evaluation\r
+** ERR_RANGE - Parameter out of range\r
+** ===================================================================\r
+*/\r
+byte TickTimer_SetPeriodMS(word Time)\r
+{\r
+ dlong rtval; /* Result of two 32-bit numbers multiplication */\r
+ word rtword; /* Result of 64-bit number division */\r
+\r
+ if ((Time > 20) || (Time < 1)) /* Is the given value out of range? */\r
+ return ERR_RANGE; /* If yes then error */\r
+ PE_Timer_LngMul((dword)Time,204734464,&rtval); /* Multiply given value and high speed CPU mode coefficient */\r
+ if (PE_Timer_LngHi2(rtval[0],rtval[1],&rtword)) /* Is the result greater or equal than 65536 ? */\r
+ rtword = 65535; /* If yes then use maximal possible value */\r
+ CmpHighVal = rtword; /* Store result (compare register value for high speed CPU mode) to the variable CmpHighVal */\r
+ SetCV(CmpHighVal); /* Store appropriate value to the compare register according to the selected high speed CPU mode */\r
+ return ERR_OK; /* OK */\r
+}\r
+\r
+/*\r
+** ===================================================================\r
+** Method : TickTimer_SetFreqHz (bean TimerInt)\r
+**\r
+** Description :\r
+** This method sets the new frequency of the generated\r
+** events. The frequency is expressed in Hz as a 16-bit\r
+** unsigned integer number.\r
+** This method is available only if runtime setting type\r
+** 'from interval' is selected in the Timing dialog box in\r
+** Runtime setting area.\r
+** Parameters :\r
+** NAME - DESCRIPTION\r
+** Freq - Frequency to set [in Hz]\r
+** (50 to 1000 Hz)\r
+** Returns :\r
+** --- - Error code, possible codes:\r
+** ERR_OK - OK\r
+** ERR_SPEED - This device does not work in\r
+** the active speed mode\r
+** ERR_MATH - Overflow during evaluation\r
+** ERR_RANGE - Parameter out of range\r
+** ===================================================================\r
+*/\r
+byte TickTimer_SetFreqHz(word Freq)\r
+{\r
+ dlong rtval; /* Result of two 32-bit numbers division */\r
+ word rtword; /* Result of 64-bit number division */\r
+\r
+ if ((Freq > 1000) || (Freq < 50)) /* Is the given value out of range? */\r
+ return ERR_RANGE; /* If yes then error */\r
+ rtval[1] = 799744000 / (dword)Freq; /* Divide high speed CPU mode coefficient by the given value */\r
+ rtval[0] = 0; /* Convert result to the type dlong */\r
+ if (PE_Timer_LngHi1(rtval[0],rtval[1],&rtword)) /* Is the result greater or equal than 65536 ? */\r
+ rtword = 65535; /* If yes then use maximal possible value */\r
+ CmpHighVal = rtword; /* Store result (compare register value for high speed CPU mode) to the variable CmpHighVal */\r
+ SetCV(CmpHighVal); /* Store appropriate value to the compare register according to the selected high speed CPU mode */\r
+ return ERR_OK; /* OK */\r
+}\r
+\r
+/*\r
+** ===================================================================\r
+** Method : TickTimer_Init (bean TimerInt)\r
+**\r
+** Description :\r
+** This method is internal. It is used by Processor Expert\r
+** only.\r
+** ===================================================================\r
+*/\r
+void TickTimer_Init(void)\r
+{\r
+ CmpHighVal = 3124; /* Compare register value for high speed CPU mode */\r
+ SetCV(CmpHighVal); /* Store appropriate value to the compare register according to the selected high speed CPU mode */\r
+ SetPV(3); /* Set prescaler register according to the selected high speed CPU mode */\r
+ HWEnDi(); /* Enable/disable device according to status flags */\r
+}\r
+\r
+/*\r
+** ===================================================================\r
+** Method : TickTimer_Interrupt (bean TimerInt)\r
+**\r
+** Description :\r
+** This method is internal. It is used by Processor Expert\r
+** only.\r
+** ===================================================================\r
+*/\r
+#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */\r
+__interrupt void TickTimer_Interrupt(void)\r
+{\r
+ TFLG1 = 1; /* Reset interrupt request flag */\r
+ TickTimer_OnInterrupt(); /* Invoke user event */\r
+}\r
+\r
+#pragma CODE_SEG TickTimer_CODE /* Code section for this module. */\r
+\r
+/* END TickTimer. */\r
+\r
+/*\r
+** ###################################################################\r
+**\r
+** This file was created by UNIS Processor Expert 03.33 for \r
+** the Motorola HCS12 series of microcontrollers.\r
+**\r
+** ###################################################################\r
+*/\r
--- /dev/null
+/** ###################################################################\r
+** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.\r
+** Filename : TickTimer.H\r
+** Project : RTOSDemo\r
+** Processor : MC9S12DP256BCPV\r
+** Beantype : TimerInt\r
+** Version : Bean 02.063, Driver 01.05, CPU db: 2.87.283\r
+** Compiler : Metrowerks HC12 C Compiler\r
+** Date/Time : 18/06/2005, 16:21\r
+** Abstract :\r
+** This bean "TimerInt" implements a periodic interrupt.\r
+** When the bean and its events are enabled, the "OnInterrupt"\r
+** event is called periodically with the period that you specify.\r
+** TimerInt supports also changing the period in runtime.\r
+** The source of periodic interrupt can be timer compare or reload \r
+** register or timer-overflow interrupt (of free running counter).\r
+** Settings :\r
+** Timer name : ECT (16-bit)\r
+** Compare name : TC0\r
+** Counter shared : No\r
+**\r
+** High-speed CPU mode\r
+** Prescaler : divide-by-8\r
+** Clock : 3124000 Hz\r
+** Initial period/frequency\r
+** Xtal ticks : 16000\r
+** microseconds : 1000\r
+** milliseconds : 1\r
+** seconds (real) : 0.0010000\r
+** Hz : 1000\r
+** kHz : 1\r
+**\r
+** Runtime setting : period/frequency interval (continual setting)\r
+** ticks : 16000 to 320000 ticks\r
+** microseconds : 1000 to 20000 microseconds\r
+** milliseconds : 1 to 20 milliseconds\r
+** seconds (real) : 0.0010000 to 0.0200000 seconds\r
+** Hz : 50 to 1000 Hz\r
+**\r
+** Initialization:\r
+** Timer : Enabled\r
+** Events : Enabled\r
+**\r
+** Timer registers\r
+** Counter : TCNT [68]\r
+** Mode : TIOS [64]\r
+** Run : TSCR1 [70]\r
+** Prescaler : TSCR2 [77]\r
+**\r
+** Compare registers\r
+** Compare : TC0 [80]\r
+**\r
+** Flip-flop registers\r
+** Mode : TCTL2 [73]\r
+** Contents :\r
+** Enable - byte TickTimer_Enable(void);\r
+** SetPeriodTicks16 - byte TickTimer_SetPeriodTicks16(word Ticks);\r
+** SetPeriodTicks32 - byte TickTimer_SetPeriodTicks32(dword Ticks);\r
+** SetPeriodUS - byte TickTimer_SetPeriodUS(word Time);\r
+** SetPeriodMS - byte TickTimer_SetPeriodMS(word Time);\r
+** SetFreqHz - byte TickTimer_SetFreqHz(word Freq);\r
+**\r
+** (c) Copyright UNIS, spol. s r.o. 1997-2002\r
+** UNIS, spol. s r.o.\r
+** Jundrovska 33\r
+** 624 00 Brno\r
+** Czech Republic\r
+** http : www.processorexpert.com\r
+** mail : info@processorexpert.com\r
+** ###################################################################*/\r
+\r
+#ifndef __TickTimer\r
+#define __TickTimer\r
+\r
+/* MODULE TickTimer. */\r
+\r
+#include "Cpu.h"\r
+\r
+#pragma CODE_SEG TickTimer_CODE /* Code section for this module. */\r
+\r
+#define TickTimer_SPT16Min 16000 /* Lower bound of interval for method SetPeriodTicks16 */\r
+#define TickTimer_SPT16Max 65535 /* Upper bound of interval for method SetPeriodTicks16 */\r
+#define TickTimer_SPT32Min 16000 /* Lower bound of interval for method SetPeriodTicks32 */\r
+#define TickTimer_SPT32Max 320000 /* Upper bound of interval for method SetPeriodTicks32 */\r
+#define TickTimer_SPUSMin 1000 /* Lower bound of interval for method SetPeriodUS */\r
+#define TickTimer_SPUSMax 20000 /* Upper bound of interval for method SetPeriodUS */\r
+#define TickTimer_SPMSMin 1 /* Lower bound of interval for method SetPeriodMS */\r
+#define TickTimer_SPMSMax 20 /* Upper bound of interval for method SetPeriodMS */\r
+#define TickTimer_SFHzMin 50 /* Lower bound of interval for method SetFreqHz */\r
+#define TickTimer_SFHzMax 1000 /* Upper bound of interval for method SetFreqHz */\r
+\r
+\r
+byte TickTimer_Enable(void);\r
+/*\r
+** ===================================================================\r
+** Method : TickTimer_Enable (bean TimerInt)\r
+**\r
+** Description :\r
+** Enable the bean - it starts the timer. Events may be\r
+** generated ("DisableEvent"/"EnableEvent").\r
+** Parameters : None\r
+** Returns :\r
+** --- - Error code, possible codes:\r
+** ERR_OK - OK\r
+** ERR_SPEED - This device does not work in\r
+** the active speed mode\r
+** ===================================================================\r
+*/\r
+\r
+byte TickTimer_SetPeriodTicks16(word Ticks);\r
+/*\r
+** ===================================================================\r
+** Method : TickTimer_SetPeriodTicks16 (bean TimerInt)\r
+**\r
+** Description :\r
+** This method sets the new period of the generated events.\r
+** The period is expressed in Xtal ticks as a 16-bit unsigned\r
+** integer number.\r
+** This method is available only if runtime setting type\r
+** 'from interval' is selected in the Timing dialog box in\r
+** Runtime setting area.\r
+** Parameters :\r
+** NAME - DESCRIPTION\r
+** Ticks - Period to set [in Xtal ticks]\r
+** (16000 to 65535 ticks)\r
+** Returns :\r
+** --- - Error code, possible codes:\r
+** ERR_OK - OK\r
+** ERR_SPEED - This device does not work in\r
+** the active speed mode\r
+** ERR_MATH - Overflow during evaluation\r
+** ERR_RANGE - Parameter out of range\r
+** ===================================================================\r
+*/\r
+\r
+byte TickTimer_SetPeriodTicks32(dword Ticks);\r
+/*\r
+** ===================================================================\r
+** Method : TickTimer_SetPeriodTicks32 (bean TimerInt)\r
+**\r
+** Description :\r
+** This method sets the new period of the generated events.\r
+** The period is expressed in Xtal ticks as a 32-bit unsigned\r
+** integer number.\r
+** This method is available only if runtime setting type\r
+** 'from interval' is selected in the Timing dialog box in\r
+** Runtime setting area.\r
+** Parameters :\r
+** NAME - DESCRIPTION\r
+** Ticks - Period to set [in Xtal ticks]\r
+** (16000 to 320000 ticks)\r
+** Returns :\r
+** --- - Error code, possible codes:\r
+** ERR_OK - OK\r
+** ERR_SPEED - This device does not work in\r
+** the active speed mode\r
+** ERR_MATH - Overflow during evaluation\r
+** ERR_RANGE - Parameter out of range\r
+** ===================================================================\r
+*/\r
+\r
+byte TickTimer_SetPeriodUS(word Time);\r
+/*\r
+** ===================================================================\r
+** Method : TickTimer_SetPeriodUS (bean TimerInt)\r
+**\r
+** Description :\r
+** This method sets the new period of the generated events.\r
+** The period is expressed in microseconds as a 16-bit\r
+** unsigned integer number.\r
+** This method is available only if runtime setting type\r
+** 'from interval' is selected in the Timing dialog box in\r
+** Runtime setting area.\r
+** Parameters :\r
+** NAME - DESCRIPTION\r
+** Time - Period to set [in microseconds]\r
+** (1000 to 20000 microseconds)\r
+** Returns :\r
+** --- - Error code, possible codes:\r
+** ERR_OK - OK\r
+** ERR_SPEED - This device does not work in\r
+** the active speed mode\r
+** ERR_MATH - Overflow during evaluation\r
+** ERR_RANGE - Parameter out of range\r
+** ===================================================================\r
+*/\r
+\r
+byte TickTimer_SetPeriodMS(word Time);\r
+/*\r
+** ===================================================================\r
+** Method : TickTimer_SetPeriodMS (bean TimerInt)\r
+**\r
+** Description :\r
+** This method sets the new period of the generated events.\r
+** The period is expressed in miliseconds as a 16-bit\r
+** unsigned integer number.\r
+** This method is available only if runtime setting type\r
+** 'from interval' is selected in the Timing dialog box in\r
+** Runtime setting area.\r
+** Parameters :\r
+** NAME - DESCRIPTION\r
+** Time - Period to set [in miliseconds]\r
+** (1 to 20 milliseconds)\r
+** Returns :\r
+** --- - Error code, possible codes:\r
+** ERR_OK - OK\r
+** ERR_SPEED - This device does not work in\r
+** the active speed mode\r
+** ERR_MATH - Overflow during evaluation\r
+** ERR_RANGE - Parameter out of range\r
+** ===================================================================\r
+*/\r
+\r
+byte TickTimer_SetFreqHz(word Freq);\r
+/*\r
+** ===================================================================\r
+** Method : TickTimer_SetFreqHz (bean TimerInt)\r
+**\r
+** Description :\r
+** This method sets the new frequency of the generated\r
+** events. The frequency is expressed in Hz as a 16-bit\r
+** unsigned integer number.\r
+** This method is available only if runtime setting type\r
+** 'from interval' is selected in the Timing dialog box in\r
+** Runtime setting area.\r
+** Parameters :\r
+** NAME - DESCRIPTION\r
+** Freq - Frequency to set [in Hz]\r
+** (50 to 1000 Hz)\r
+** Returns :\r
+** --- - Error code, possible codes:\r
+** ERR_OK - OK\r
+** ERR_SPEED - This device does not work in\r
+** the active speed mode\r
+** ERR_MATH - Overflow during evaluation\r
+** ERR_RANGE - Parameter out of range\r
+** ===================================================================\r
+*/\r
+\r
+#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */\r
+__interrupt void TickTimer_Interrupt(void);\r
+#pragma CODE_SEG TickTimer_CODE /* Code section for this module. */\r
+/*\r
+** ===================================================================\r
+** Method : TickTimer_Interrupt (bean TimerInt)\r
+**\r
+** Description :\r
+** This method is internal. It is used by Processor Expert\r
+** only.\r
+** ===================================================================\r
+*/\r
+\r
+void TickTimer_Init(void);\r
+/*\r
+** ===================================================================\r
+** Method : TickTimer_Init (bean TimerInt)\r
+**\r
+** Description :\r
+** This method is internal. It is used by Processor Expert\r
+** only.\r
+** ===================================================================\r
+*/\r
+\r
+#pragma CODE_SEG DEFAULT /* Change code section to DEFAULT. */\r
+\r
+/* END TickTimer. */\r
+\r
+#endif /* ifndef __TickTimer */\r
+/*\r
+** ###################################################################\r
+**\r
+** This file was created by UNIS Processor Expert 03.33 for \r
+** the Motorola HCS12 series of microcontrollers.\r
+**\r
+** ###################################################################\r
+*/\r
--- /dev/null
+/** ###################################################################\r
+** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.\r
+** Filename : Cpu.C\r
+** Project : RTOSDemo\r
+** Processor : MC9S12DP256BCPV\r
+** Beantype : MC9S12DP256_112\r
+** Version : Bean 01.148, Driver 01.09, CPU db: 2.87.283\r
+** Compiler : Metrowerks HC12 C Compiler\r
+** Date/Time : 16/06/2005, 19:18\r
+** Abstract :\r
+** This bean "MC9S12DP256_112" implements properties, methods,\r
+** and events of the CPU.\r
+** Settings :\r
+**\r
+** Contents :\r
+** EnableInt - void Cpu_EnableInt(void);\r
+** DisableInt - void Cpu_DisableInt(void);\r
+**\r
+** (c) Copyright UNIS, spol. s r.o. 1997-2002\r
+** UNIS, spol. s r.o.\r
+** Jundrovska 33\r
+** 624 00 Brno\r
+** Czech Republic\r
+** http : www.processorexpert.com\r
+** mail : info@processorexpert.com\r
+** ###################################################################*/\r
+\r
+\r
+#include "Cpu.h"\r
+#include "TickTimer.h"\r
+#include "Byte1.h"\r
+\r
+extern void near _EntryPoint(void); /* Startup routine */\r
+extern void near vPortTickInterrupt( void );\r
+extern void near vPortYield( void );\r
+extern void near vCOM0_ISR( void );\r
+\r
+typedef void (*near tIsrFunc)(void);\r
+const tIsrFunc _vect[] @0xFF80 = { /* Interrupt table */\r
+ Cpu_Interrupt, /* 0 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 1 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 2 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 3 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 4 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 5 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 6 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 7 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 8 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 9 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 10 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 11 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 12 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 13 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 14 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 15 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 16 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 17 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 18 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 19 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 20 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 21 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 22 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 23 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 24 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 25 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 26 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 27 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 28 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 29 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 30 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 31 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 32 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 33 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 34 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 35 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 36 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 37 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 38 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 39 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 40 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 41 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 42 Default (unused) interrupt */\r
+ vCOM0_ISR, /* Defined in Demo/serial/serial.c */\r
+ Cpu_Interrupt, /* 44 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 45 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 46 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 47 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 48 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 49 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 50 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 51 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 52 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 53 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 54 Default (unused) interrupt */\r
+ vPortTickInterrupt, /* The RTOS tick. */\r
+ Cpu_Interrupt, /* 56 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 57 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 58 Default (unused) interrupt */\r
+ vPortYield, /* RTOS yield software interrupt. */\r
+ Cpu_Interrupt, /* 60 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 61 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 62 Default (unused) interrupt */\r
+ _EntryPoint /* Reset vector */\r
+ };\r
+/*\r
+** ###################################################################\r
+**\r
+** This file was created by UNIS Processor Expert 03.33 for \r
+** the Motorola HCS12 series of microcontrollers.\r
+**\r
+** ###################################################################\r
+*/\r
--- /dev/null
+OPEN source 0 0 60 39\r
+Source < attributes MARKS off\r
+OPEN assembly 60 0 40 31\r
+Assembly < attributes ADR on,CODE off,ABSADR on,SYMB off,TOPPC 0xF88C\r
+OPEN procedure 0 39 60 17\r
+Procedure < attributes VALUES on,TYPES off\r
+OPEN register 60 31 40 25\r
+Register < attributes FORMAT AUTO,COMPLEMENT None\r
+OPEN memory 60 56 40 22\r
+Memory < attributes FORMAT hex,COMPLEMENT None,WORD 1,ASC on,ADR on,ADDRESS 0x80\r
+OPEN data 0 56 60 22\r
+Data:1 < attributes SCOPE global,COMPLEMENT None,FORMAT Symb,MODE automatic,UPDATERATE 10,NAMEWIDTH 16\r
+OPEN data 0 78 60 22\r
+Data:2 < attributes SCOPE local,COMPLEMENT None,FORMAT Symb,MODE automatic,UPDATERATE 10,NAMEWIDTH 16\r
+OPEN command 60 78 40 22\r
+Command < attributes CACHESIZE 1000\r
+bckcolor 50331647\r
+font 'Courier New' 9 BLACK\r
+AUTOSIZE on\r
+ACTIVATE Data:2 Command Procedure Data:1 Source Register Assembly Memory\r
--- /dev/null
+=================================================================\r
+This file was generated from Processor Expert 03.33\r
+ project "RTOSDemo", 19/06/2005, 15:54\r
+-----------------------------------------------------------------\r
+There is no signal defined in this project.\r
+ Hint: Signals may be defined in the Bean Inspector (advanced or expert view)\r
+=================================================================\r
+\r
+=================================================================\r
+ SIGNAL LIST\r
+-----------------------------------------------------------------\r
+ SIGNAL NAME => PIN NAME\r
+-----------------------------------------------------------------\r
+=================================================================\r
+\r
+\r
+=================================================================\r
+ PIN LIST\r
+-----------------------------------------------------------------\r
+ PIN NAME => SIGNAL NAME\r
+-----------------------------------------------------------------\r
+=================================================================\r
+\r
--- /dev/null
+=============================================================================\r
+List of methods in project: RTOSDemo\r
+\r
+THIS TEXT DESCRIPTION IS GENERATED BY THE TOOL. DO NOT MODIFY IT.\r
+=============================================================================\r
+\r
+Module "TickTimer" (bean TimerInt)\r
+ TickTimer_Enable -Enable the bean - it starts the timer. Events may be generated ("DisableEvent"/"EnableEvent").\r
+ TickTimer_SetPeriodTicks16 -This method sets the new period of the generated events. The period is expressed in CPU [ticks] \r
+ as a 16-bit unsigned integer number. This method is available only if runtime setting type 'from interval' is \r
+ selected in the <Timing dialog box> in Runtime setting area.\r
+ TickTimer_SetPeriodTicks32 -This method sets the new period of the generated events. The period is expressed in CPU [ticks] \r
+ as a 32-bit unsigned integer number. This method is available only if runtime setting type 'from interval' is \r
+ selected in the <Timing dialog box> in Runtime setting area.\r
+ TickTimer_SetPeriodUS -This method sets the new period of the generated events. The period is expressed in [microseconds] as \r
+ a 16-bit unsigned integer number. This method is available only if runtime setting type 'from interval' is \r
+ selected in the <Timing dialog box> in Runtime setting area.\r
+ TickTimer_SetPeriodMS -This method sets the new period of the generated events. The period is expressed in [miliseconds] as \r
+ a 16-bit unsigned integer number. This method is available only if runtime setting type 'from interval' is \r
+ selected in the <Timing dialog box> in Runtime setting area.\r
+ TickTimer_SetFreqHz -This method sets the new frequency of the generated events. The frequency is expressed in [Hz] as a \r
+ 16-bit unsigned integer number. This method is available only if runtime setting type 'from interval' is \r
+ selected in the <Timing dialog box> in Runtime setting area.\r
+\r
+Module "Byte1" (bean ByteIO)\r
+ Byte1_PutBit -Put the specified value to the specified bit/pin of the Input/Output bean. If direction is [input] saves the \r
+ value to a memory or a register, this value will be written to the pin after switching to the output mode - \r
+ using [SetDir(TRUE)]. If direction is [output] writes the value to the pin.\r
+ Byte1_NegBit -Negate (invert) the specified bit of the Input/Output bean. It is the same as [PutBit(Bit,!GetBit(Bit))].\r
+\r
+Module "COM0" (bean AsynchroSerial)\r
+ COM0_SetBaudRateMode -This method changes the channel communication speed (baud rate). This method can be used only if you \r
+ specify a list of possible period settings at design time (see <Timing dialog box> - Runtime setting - from a \r
+ list of values). Each of these settings constitutes a mode and Processor Expert^[TM] assigns them a mode \r
+ identifier. The prescaler and compare values corresponding to each mode are calculated at design time. You may \r
+ switch modes at runtime by referring only to a mode identifier. No run-time calculations are performed, all the \r
+ calculations are performed at design time.\r
+\r
+Module "Cpu" (bean MC9S12DP256_112)\r
+ Cpu_EnableInt -Enable maskable interrupts\r
+ Cpu_DisableInt -Disable maskable interrupts\r
+\r
+=============================================================================\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+#include <hidef.h> /* common defines and macros */\r
+#include "TickTimer.h"\r
+\r
+/* This port requires the compiler to generate code for the BANKED memory\r
+model. */\r
+#define BANKED_MODEL\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. \r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 1\r
+#define configUSE_TICK_HOOK 0\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 4 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 80 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 10240 ) )\r
+#define configMAX_TASK_NAME_LEN ( 1 )\r
+#define configUSE_TRACE_FACILITY 0\r
+#define configUSE_16_BIT_TICKS 1\r
+#define configIDLE_SHOULD_YIELD 1\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* This parameter is normally required in order to set the RTOS tick timer.\r
+This port is a bit different in that hardware setup uses the code generated by \r
+the Processor Expert, making this definition obsolete.\r
+\r
+#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 25000000 )\r
+*/\r
+\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+\r
+\r
+\r
+\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+[Environment Variables]\r
+GENPATH={Compiler}lib\HC12c\src;{Compiler}lib\HC12c\include;{Compiler}lib\HC12c\lib\r
+LIBPATH={Compiler}lib\HC12c\include\r
+OBJPATH={Project}bin\r
+TEXTPATH={Project}bin\r
+ABSPATH={Project}bin\r
+\r
+[HI-WAVE]\r
+Target=icd12\r
+Layout=C_layout.hwl\r
+LoadDialogOptions=AUTOERASEANDFLASH \r
+CPU=HC12\r
+MainFrame=2,3,-1,-1,-1,-1,54,54,1254,908\r
+TOOLBAR=57600 57601 32795 0 57635 57634 57637 0 57671 57669 0 32777 32776 32782 32780 32781 32778 0 32806\r
+AEFWarningDialog=FALSE\r
+\r
+[ICD12]\r
+CMDFILE0=CMDFILE STARTUP ON ".\cmd\p&e_icd_startup.cmd"\r
+CMDFILE1=CMDFILE RESET ON ".\cmd\p&e_icd_reset.cmd"\r
+CMDFILE2=CMDFILE PRELOAD ON ".\cmd\p&e_icd_preload.cmd"\r
+CMDFILE3=CMDFILE POSTLOAD ON ".\cmd\p&e_icd_postload.cmd"\r
+CMDFILE4=CMDFILE VPPON ON ".\cmd\p&e_icd_vppon.cmd"\r
+CMDFILE5=CMDFILE VPPOFF ON ".\cmd\p&e_icd_vppoff.cmd"\r
+CMDFILE6=CMDFILE UNSECURE ON ".\cmd\P&E_ICD_erase_unsecure_hcs12.cmd"\r
+MCUID=0x3C6\r
+CHIPSECURE=CHIPSECURE SETUP 0xFF0F 0x3 0x2\r
+BDMClockSpeed=14\r
+BNKA_MCUID03C6_BANKWINDOW0=BANKWINDOW PPAGE ON 0x8000..0xBFFF 0x30 16 0x30\r
+BNKA_MCUID03C6_BANKWINDOW1=BANKWINDOW DPAGE OFF 0x7000..0x7FFF 0x34 256 0x0\r
+BNKA_MCUID03C6_BANKWINDOW2=BANKWINDOW EPAGE OFF 0x400..0x7FF 0x36 256 0x0\r
+HWBPD_MCUID03C6_HWBPM0=HWBPM MODE AUTOMATIC BPM22BITS 0x28 SKIP_OFF\r
+HWBPD_MCUID03C6_BKPT_REMAP0=HWBPM REMAP_22BITS RANGE 0x4000 0x7FFF 0x3E\r
+HWBPD_MCUID03C6_BKPT_REMAP1=HWBPM REMAP_22BITS RANGE 0xC000 0xFFFF 0x3F\r
+HWBPD_MCUID03C6_HWBPM1=HWBPM SET16BITS 0x0 0x0 0x0 0x0\r
+HWBPD_MCUID03C6_HWBPM2=HWBPM SET22BITS 0x0 0x0 0x0 0x0\r
+BDMAutoSpeed=0\r
+COMDEVICE=SETCOMM COMPORT USB "USB-PE5014402"\r
+SETCLKSW=1\r
+DETECTRUNNING=0\r
+ISRDISABLEDSTEP=0\r
+SHOWPROT=1\r
+NV_PARAMETER_FILE=C:\devtools\Metrowerks\CodeWarrior CW12_V3.1\prog\FPP\mcu03C6.fpp\r
+NV_SAVE_WSP=0\r
+NV_AUTO_ID=1\r
+DMM_MCUID03C6_MODULE0=Registers 0x0 0x400 1 4 0 2 1 1\r
+DMM_MCUID03C6_MODULE1=Ram 0x1000 0x3000 2 5 0 3 1 1\r
+DMM_MCUID03C6_MODULE2=Eeprom 0x0 0x1000 3 5 1 4 1 1\r
+DMM_MCUID03C6_MODULE3=Banked£memory 0x8000 0x2f4000 100 6 0 6 1 0\r
+DMM_MCUID03C6_MODULE4=Banked£flash 0x308000 0xf4000 101 6 1 5 1 0\r
+DMM_MCUID03C6_MODULE5=Unbanked£flash£4000 0x4000 0x4000 102 5 1 5 1 1\r
+DMM_MCUID03C6_MODULE6=Unbanked£flash£C000 0xc000 0x4000 103 5 1 5 1 1\r
+HOTPLUGGING=0\r
+REALTIMEHWBP=0\r
+NOREADWHILERUNNING=0\r
+RESYNCONCOPRESET=0\r
+\r
+[Recent Applications File List]\r
+File1=E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior_banked\bin\P&E_ICD.abs\r
+File2=E:\Dev\FreeRTOS\Demo\MC9S12DP256_CodeWarrior\bin\P&E_ICD.abs\r
+File3=\r
+File4=\r
+LoadFlags1=4099\r
+LoadFlags2=4099\r
+LoadFlags3=0\r
+LoadFlags4=0\r
+\r
+[Recent Layout File List]\r
+File1=C_layout.hwl\r
+File2=\r
+File3=\r
+File4=\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "portable.h"\r
+\r
+/* Processor Expert created headers. */\r
+#include "byte1.h"\r
+\r
+/* Demo application include files. */\r
+#include "partest.h"\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple parallel port IO routines.\r
+ *-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )\r
+{\r
+ /* This function is required as it is called from the standard demo \r
+ application files. All it does however is call the Processor Expert\r
+ created function. */\r
+ portENTER_CRITICAL();\r
+ Byte1_PutBit( uxLED, !xValue );\r
+ portEXIT_CRITICAL();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+ /* This function is required as it is called from the standard demo\r
+ application files. All it does however is call the processor Expert\r
+ created function. */\r
+ portENTER_CRITICAL();\r
+ Byte1_NegBit( uxLED );\r
+ portEXIT_CRITICAL();\r
+}\r
+\r
+\r
+\r
--- /dev/null
+;Please do not modify this file!\r
+;The file contains internal information about the Processor Expert project generation\r
+[Options]\r
+ProjectName=RTOSDemo\r
+ProjectDirectory=E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior_banked\\r
+DestEventsDirectory=CODE\\r
+DestDriversSubDirectory=\r
+DestDocumentationDirectory=DOC\\r
+DestCompiledFilesSubDirectory=\r
+DestFpgaSubDirectory=\r
+DestTemporaryDirectory=\r
+[GenFiles]\r
+LinkerFileGenerated=Yes\r
+MakefileGenerated=No\r
+GenSharedModules=5\r
+Line=PE_Types\r
+Line=PE_Error\r
+Line=PE_Const\r
+Line=IO_Map\r
+Line=PE_Timer\r
+ShrdHeaderAge0=852337107\r
+ShrdCodeAge0=-1\r
+ShrdAsemblAge0=-1\r
+ShrdHeaderAge1=852337107\r
+ShrdCodeAge1=-1\r
+ShrdAsemblAge1=-1\r
+ShrdHeaderAge2=852337107\r
+ShrdCodeAge2=-1\r
+ShrdAsemblAge2=-1\r
+ShrdHeaderAge3=852337107\r
+ShrdCodeAge3=852337107\r
+ShrdAsemblAge3=-1\r
+ShrdHeaderAge4=852395090\r
+ShrdCodeAge4=852395090\r
+ShrdAsemblAge4=-1\r
+GenExtraFiles=2\r
+Line=E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior_banked\CODE\Vectors.c\r
+Line=E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior_banked\CODE\PESL.h\r
+XtraAge0=852534276\r
+XtraAge1=852337108\r
+GenExtraFileType1=4\r
+GenExtraFileType0=4\r
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--- /dev/null
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--- /dev/null
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+Value=No\r
+LastSelection=No\r
+LastUserSel=never\r
+UsrMethodName=DisableEvent\r
+[ItemState]\r
+ItemSymbol=RecvChar\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=BASIC\r
+Index=1\r
+Value=No\r
+LastSelection=No\r
+LastUserSel=no\r
+UsrMethodName=RecvChar\r
+[ItemState]\r
+ItemSymbol=SendChar\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=BASIC\r
+Index=1\r
+Value=No\r
+LastSelection=No\r
+LastUserSel=no\r
+UsrMethodName=SendChar\r
+[ItemState]\r
+ItemSymbol=RecvBlock\r
+ReadOnly=Yes\r
+UserReadOnly=No\r
+BasAdvHid=BASIC\r
+Index=1\r
+Value=No\r
+LastSelection=No\r
+LastUserSel=never\r
+UsrMethodName=RecvBlock\r
+[ItemState]\r
+ItemSymbol=SendBlock\r
+ReadOnly=Yes\r
+UserReadOnly=No\r
+BasAdvHid=BASIC\r
+Index=1\r
+Value=No\r
+LastSelection=No\r
+LastUserSel=never\r
+UsrMethodName=SendBlock\r
+[ItemState]\r
+ItemSymbol=ClearRxBuf\r
+ReadOnly=Yes\r
+UserReadOnly=No\r
+BasAdvHid=BASIC\r
+Index=1\r
+Value=No\r
+LastSelection=No\r
+LastUserSel=never\r
+UsrMethodName=ClearRxBuf\r
+[ItemState]\r
+ItemSymbol=ClearTxBuf\r
+ReadOnly=Yes\r
+UserReadOnly=No\r
+BasAdvHid=BASIC\r
+Index=1\r
+Value=No\r
+LastSelection=No\r
+LastUserSel=never\r
+UsrMethodName=ClearTxBuf\r
+[ItemState]\r
+ItemSymbol=CharsInRxBuf\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=EXPERT\r
+Index=1\r
+Value=No\r
+LastSelection=No\r
+LastUserSel=no\r
+UsrMethodName=CharsInRxBuf\r
+[ItemState]\r
+ItemSymbol=GetCharsInRxBuf\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=BASIC\r
+Index=1\r
+Value=No\r
+LastSelection=No\r
+LastUserSel=no\r
+UsrMethodName=GetCharsInRxBuf\r
+[ItemState]\r
+ItemSymbol=CharsInTxBuf\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=EXPERT\r
+Index=1\r
+Value=No\r
+LastSelection=No\r
+LastUserSel=no\r
+UsrMethodName=CharsInTxBuf\r
+[ItemState]\r
+ItemSymbol=GetCharsInTxBuf\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=BASIC\r
+Index=1\r
+Value=No\r
+LastSelection=No\r
+LastUserSel=no\r
+UsrMethodName=GetCharsInTxBuf\r
+[ItemState]\r
+ItemSymbol=SetBaudRateMode\r
+ReadOnly=Yes\r
+UserReadOnly=No\r
+BasAdvHid=BASIC\r
+Index=0\r
+Value=Yes\r
+LastSelection=Yes\r
+LastUserSel=always\r
+UsrMethodName=SetBaudRateMode\r
+[ItemState]\r
+ItemSymbol=GetError\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=BASIC\r
+Index=1\r
+Value=No\r
+LastSelection=No\r
+LastUserSel=no\r
+UsrMethodName=GetError\r
+[ItemState]\r
+ItemSymbol=GetBreak\r
+ReadOnly=Yes\r
+UserReadOnly=No\r
+BasAdvHid=ADVANCED\r
+Index=1\r
+Value=No\r
+LastSelection=Yes\r
+LastUserSel=never\r
+UsrMethodName=GetBreak\r
+[ItemState]\r
+ItemSymbol=CPUCond2\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=BASIC\r
+\r
+[Childs]\r
+List=GrupItem\r
+[ItemState]\r
+ItemSymbol=SetBreak0\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=ADVANCED\r
+Index=0\r
+Value=Yes\r
+LastSelection=No\r
+LastUserSel=yes\r
+UsrMethodName=SetBreak\r
+\r
+[EndOfChilds]\r
+[ItemState]\r
+ItemSymbol=SetBreak\r
+ReadOnly=Yes\r
+UserReadOnly=No\r
+BasAdvHid=ADVANCED\r
+Index=1\r
+Value=No\r
+LastSelection=Yes\r
+LastUserSel=never\r
+UsrMethodName=SetBreak\r
+[ItemState]\r
+ItemSymbol=SetAttentionMode\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=@ HIDDEN @\r
+Index=1\r
+Value=No\r
+LastSelection=No\r
+LastUserSel=no\r
+UsrMethodName=SetAttentionMode\r
+[ItemState]\r
+ItemSymbol=TurnTxOn\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=EXPERT\r
+Index=1\r
+Value=No\r
+LastSelection=No\r
+LastUserSel=no\r
+UsrMethodName=TurnTxOn\r
+[ItemState]\r
+ItemSymbol=TurnTxOff\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=EXPERT\r
+Index=1\r
+Value=No\r
+LastSelection=No\r
+LastUserSel=no\r
+UsrMethodName=TurnTxOff\r
+[ItemState]\r
+ItemSymbol=SetRxBaudGenerator\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=@ HIDDEN @\r
+Index=1\r
+Value=No\r
+LastSelection=No\r
+LastUserSel=no\r
+UsrMethodName=SetRxBaudGenerator\r
+[ItemState]\r
+ItemSymbol=SetTxBaudGenerator\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=@ HIDDEN @\r
+Index=1\r
+Value=No\r
+LastSelection=No\r
+LastUserSel=no\r
+UsrMethodName=SetTxBaudGenerator\r
+[ItemState]\r
+ItemSymbol=CPUCond\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=BASIC\r
+\r
+[Childs]\r
+List=GrupItem\r
+[ItemState]\r
+ItemSymbol=TurnRxOn\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=EXPERT\r
+Index=1\r
+Value=No\r
+LastSelection=No\r
+LastUserSel=no\r
+UsrMethodName=TurnRxOn\r
+[ItemState]\r
+ItemSymbol=TurnRxOff\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=EXPERT\r
+Index=1\r
+Value=No\r
+LastSelection=No\r
+LastUserSel=no\r
+UsrMethodName=TurnRxOff\r
+[ItemState]\r
+ItemSymbol=SetIdle\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=ADVANCED\r
+Index=1\r
+Value=No\r
+LastSelection=No\r
+LastUserSel=no\r
+UsrMethodName=SetIdle\r
+[ItemState]\r
+ItemSymbol=LoopMode\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=ADVANCED\r
+Index=1\r
+Value=No\r
+LastSelection=No\r
+LastUserSel=no\r
+UsrMethodName=LoopMode\r
+\r
+[EndOfChilds]\r
+[ItemState]\r
+ItemSymbol=CPUCond1\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=BASIC\r
+\r
+[Childs]\r
+List=GrupItem\r
+[ItemState]\r
+ItemSymbol=Standby\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=ADVANCED\r
+Index=1\r
+Value=No\r
+LastSelection=No\r
+LastUserSel=no\r
+UsrMethodName=Standby\r
+\r
+[EndOfChilds]\r
+[ItemState]\r
+ItemSymbol=ESCIMethodsGrp\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=BASIC\r
+\r
+[Childs]\r
+List=GrupItem\r
+[ItemState]\r
+ItemSymbol=GetArbiterStatus\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=BASIC\r
+Index=1\r
+Value=No\r
+LastSelection=No\r
+LastUserSel=no\r
+UsrMethodName=GetArbiterStatus\r
+[ItemState]\r
+ItemSymbol=ResetArbiterCounter\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=ADVANCED\r
+Index=1\r
+Value=No\r
+LastSelection=No\r
+LastUserSel=no\r
+UsrMethodName=ResetArbiterCounter\r
+[ItemState]\r
+ItemSymbol=GetArbiterCounter\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=ADVANCED\r
+Index=1\r
+Value=No\r
+LastSelection=No\r
+LastUserSel=no\r
+UsrMethodName=GetArbiterCounter\r
+[ItemState]\r
+ItemSymbol=SetFallingEdgesMeasurement\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=BASIC\r
+Index=1\r
+Value=No\r
+LastSelection=No\r
+LastUserSel=no\r
+UsrMethodName=SetFallingEdgesMeasurement\r
+[ItemState]\r
+ItemSymbol=SetLowLevelMeasurement\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=BASIC\r
+Index=1\r
+Value=No\r
+LastSelection=No\r
+LastUserSel=no\r
+UsrMethodName=SetLowLevelMeasurement\r
+[ItemState]\r
+ItemSymbol=ClearArbiterFlags\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=BASIC\r
+Index=1\r
+Value=No\r
+LastSelection=No\r
+LastUserSel=no\r
+UsrMethodName=ClearArbiterFlags\r
+[ItemState]\r
+ItemSymbol=SetArbitrationMode\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=BASIC\r
+Index=1\r
+Value=No\r
+LastSelection=No\r
+LastUserSel=no\r
+UsrMethodName=SetArbitrationMode\r
+[ItemState]\r
+ItemSymbol=AdjustBaudRate\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=BASIC\r
+Index=1\r
+Value=No\r
+LastSelection=No\r
+LastUserSel=no\r
+UsrMethodName=AdjustBaudRate\r
+\r
+[EndOfChilds]\r
+[ItemState]\r
+ItemSymbol=CPU_HCS08_HCS12\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=BASIC\r
+\r
+[Childs]\r
+List=GrupItem\r
+[ItemState]\r
+ItemSymbol=SetDirection\r
+ReadOnly=Yes\r
+UserReadOnly=No\r
+BasAdvHid=BASIC\r
+Index=1\r
+Value=No\r
+LastSelection=No\r
+LastUserSel=never\r
+UsrMethodName=SetDirection\r
+\r
+[EndOfChilds]\r
+[ItemState]\r
+ItemSymbol=56800grp\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=BASIC\r
+\r
+[Childs]\r
+List=GrupItem\r
+[ItemState]\r
+ItemSymbol=ConnectPin\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=EXPERT\r
+Index=1\r
+Value=No\r
+LastSelection=No\r
+LastUserSel=no\r
+UsrMethodName=ConnectPin\r
+\r
+[EndOfChilds]\r
+\r
+[Events]\r
+List=Event\r
+[ItemState]\r
+ItemSymbol=EventModule\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=ADVANCED\r
+Value=Events\r
+[ItemState]\r
+ItemSymbol=BeforeNewSpeed\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=EXPERT\r
+Value=No\r
+\r
+[Childs]\r
+List=GrupItem\r
+[ItemState]\r
+ItemSymbol=Name\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=BASIC\r
+Value=COM0_BeforeNewSpeed\r
+\r
+[EndOfChilds]\r
+LastSelection=No\r
+LastUserSel=no\r
+[ItemState]\r
+ItemSymbol=AfterNewSpeed\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=EXPERT\r
+Value=No\r
+\r
+[Childs]\r
+List=GrupItem\r
+[ItemState]\r
+ItemSymbol=Name\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=BASIC\r
+Value=COM0_AfterNewSpeed\r
+\r
+[EndOfChilds]\r
+LastSelection=No\r
+LastUserSel=no\r
+[ItemState]\r
+ItemSymbol=OnError\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=BASIC\r
+Value=No\r
+\r
+[Childs]\r
+List=GrupItem\r
+[ItemState]\r
+ItemSymbol=Name\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=BASIC\r
+Value=COM0_OnError\r
+[ItemState]\r
+ItemSymbol=Priority\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=ADVANCED\r
+Value=same as interrupt\r
+\r
+[EndOfChilds]\r
+LastSelection=Yes\r
+LastUserSel=no\r
+[ItemState]\r
+ItemSymbol=OnRxChar\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=BASIC\r
+Value=No\r
+\r
+[Childs]\r
+List=GrupItem\r
+[ItemState]\r
+ItemSymbol=Name\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=BASIC\r
+Value=COM0_OnRxChar\r
+[ItemState]\r
+ItemSymbol=Priority\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=ADVANCED\r
+Value=same as interrupt\r
+\r
+[EndOfChilds]\r
+LastSelection=Yes\r
+LastUserSel=no\r
+[ItemState]\r
+ItemSymbol=OnTxChar\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=BASIC\r
+Value=No\r
+\r
+[Childs]\r
+List=GrupItem\r
+[ItemState]\r
+ItemSymbol=Name\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=BASIC\r
+Value=COM0_OnTxChar\r
+[ItemState]\r
+ItemSymbol=Priority\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=ADVANCED\r
+Value=same as interrupt\r
+\r
+[EndOfChilds]\r
+LastSelection=Yes\r
+LastUserSel=no\r
+[ItemState]\r
+ItemSymbol=OnFullRxBuf\r
+ReadOnly=Yes\r
+UserReadOnly=No\r
+BasAdvHid=BASIC\r
+Value=No\r
+\r
+[Childs]\r
+List=GrupItem\r
+[ItemState]\r
+ItemSymbol=Name\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=BASIC\r
+Value=COM0_OnFullRxBuf\r
+[ItemState]\r
+ItemSymbol=Priority\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=ADVANCED\r
+Value=same as interrupt\r
+\r
+[EndOfChilds]\r
+LastSelection=Yes\r
+LastUserSel=never\r
+[ItemState]\r
+ItemSymbol=OnFreeTxBuf\r
+ReadOnly=Yes\r
+UserReadOnly=No\r
+BasAdvHid=BASIC\r
+Value=No\r
+\r
+[Childs]\r
+List=GrupItem\r
+[ItemState]\r
+ItemSymbol=Name\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=BASIC\r
+Value=COM0_OnFreeTxBuf\r
+[ItemState]\r
+ItemSymbol=Priority\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=ADVANCED\r
+Value=same as interrupt\r
+\r
+[EndOfChilds]\r
+LastSelection=Yes\r
+LastUserSel=never\r
+[ItemState]\r
+ItemSymbol=OnBreak\r
+ReadOnly=Yes\r
+UserReadOnly=No\r
+BasAdvHid=ADVANCED\r
+Value=No\r
+\r
+[Childs]\r
+List=GrupItem\r
+[ItemState]\r
+ItemSymbol=Name\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=BASIC\r
+Value=COM0_OnBreak\r
+[ItemState]\r
+ItemSymbol=Priority\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=ADVANCED\r
+Value=same as interrupt\r
+\r
+[EndOfChilds]\r
+LastSelection=Yes\r
+LastUserSel=never\r
+[ItemState]\r
+ItemSymbol=CPUCond0\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=BASIC\r
+\r
+[Childs]\r
+List=GrupItem\r
+[ItemState]\r
+ItemSymbol=OnIdle\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=ADVANCED\r
+Value=No\r
+\r
+[Childs]\r
+List=GrupItem\r
+[ItemState]\r
+ItemSymbol=Name\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=BASIC\r
+Value=COM0_OnIdle\r
+[ItemState]\r
+ItemSymbol=Priority\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=ADVANCED\r
+Value=same as interrupt\r
+\r
+[EndOfChilds]\r
+LastSelection=No\r
+LastUserSel=no\r
+\r
+[EndOfChilds]\r
+\r
+[Program]\r
+ProgType=event\r
+ProgNumb=2\r
+List=Property\r
+EventModule=Events\r
+\r
+[_end_]\r
--- /dev/null
+[Environment Variables]\r
+GENPATH={Compiler}lib\HC12c\src;{Compiler}lib\HC12c\include;{Compiler}lib\HC12c\lib\r
+LIBPATH={Compiler}lib\HC12c\include\r
+OBJPATH={Project}bin\r
+TEXTPATH={Project}bin\r
+ABSPATH={Project}bin\r
+\r
+[HI-WAVE]\r
+Target=sim\r
+Layout=C_layout.hwl\r
+LoadDialogOptions= AUTOERASEANDFLASH\r
+CPU=HC12\r
+MainFrame=2,3,-1,-1,-1,-1,108,108,1308,962\r
+TOOLBAR=57600 57601 32795 0 57635 57634 57637 0 57671 57669 0 32777 32776 32782 32780 32781 32778 0 32806\r
+\r
+[Simulator]\r
+CMDFILE0=CMDFILE STARTUP ON ".\cmd\simulator_startup.cmd"\r
+\r
+[Simulator HC12]\r
+CMDFILE0=CMDFILE RESET ON ".\cmd\simulator_reset.cmd"\r
+CMDFILE1=CMDFILE PRELOAD ON ".\cmd\simulator_preload.cmd"\r
+CMDFILE2=CMDFILE POSTLOAD ON ".\cmd\simulator_postload.cmd"\r
+CMDFILE3=CMDFILE SETCPU ON ".\cmd\simulator_setcpu.cmd"\r
+HCS12_SUPPORT=1\r
+FCS=MC9S12DP256B\r
--- /dev/null
+/*****************************************************\r
+ start12.c - standard startup code\r
+ The startup code may be optimized to special user requests\r
+ ----------------------------------------------------\r
+ Copyright (c) Metrowerks, Basel, Switzerland\r
+ All rights reserved\r
+ Do not modify!\r
+\r
+Note: ROM libraries are not implemented in this startup code\r
+Note: C++ destructors of global objects are NOT yet supported in the HIWARE Object File Format.\r
+ To use this feature, please build your application with the ELF object file format.\r
+ *****************************************************/\r
+\r
+#include "hidef.h"\r
+#include "start12.h"\r
+\r
+/* Macros to control how the startup code handles the COP: */\r
+/* #define _DO_FEED_COP_ : do feed the COP */\r
+/* #define _DO_ENABLE_COP_: do enable the COP */\r
+/* #define _DO_DISABLE_COP_: disable the COP */\r
+/* Without defining any of these, the startup code does NOT handle the COP */\r
+\r
+#pragma DATA_SEG __NEAR_SEG STARTUP_DATA /* _startupData can be accessed using 16 bit accesses. This is needed because it contains the stack top, and without stack, far data cannot be accessed */\r
+struct _tagStartup _startupData; /* read-only: */\r
+ /* _startupData is allocated in ROM and */\r
+ /* initialized by the linker */\r
+#pragma DATA_SEG DEFAULT\r
+#if defined(FAR_DATA)\r
+#include "non_bank.sgm"\r
+/* the init function must be in non banked memory if banked variables are used */\r
+/* because _SET_PAGE is called, which may change any page register. */\r
+\r
+#ifdef __cplusplus\r
+ extern "C"\r
+#endif\r
+void _SET_PAGE(void); /* the inline assembler needs a prototype */\r
+ /* this is a runtime routine with a special */\r
+ /* calling convention, dont use it in c code! */\r
+static void Init(void);\r
+static void Fini(void);\r
+#else\r
+#include "default.sgm"\r
+#if defined( __BANKED__) || defined(__LARGE__)\r
+static void __far Init(void);\r
+static void __far Fini(void);\r
+#endif /* defined( __BANKED__) || defined(__LARGE__) */\r
+#endif /* FAR_DATA */\r
+\r
+\r
+/* define value and bits for Windef Register */\r
+#ifdef HC812A4\r
+#define WINDEF (*(volatile unsigned char*) 0x37)\r
+#if defined( __BANKED__) || defined(__LARGE__) || defined(__PPAGE__)\r
+#define __ENABLE_PPAGE__ 0x40\r
+#else\r
+#define __ENABLE_PPAGE__ 0x0\r
+#endif\r
+#if defined(__DPAGE__)\r
+#define __ENABLE_DPAGE__ 0x80\r
+#else\r
+#define __ENABLE_DPAGE__ 0x0\r
+#endif\r
+#if defined(__EPAGE__)\r
+#define __ENABLE_EPAGE__ 0x20\r
+#else\r
+#define __ENABLE_EPAGE__ 0x0\r
+#endif\r
+#endif /* HC812A4 */\r
+\r
+#ifdef _HCS12_SERIALMON\r
+ /* for Monitor based software remap the RAM & EEPROM to adhere\r
+ to EB386. Edit RAM and EEPROM sections in PRM file to match these. */\r
+#define ___INITRM (*(volatile unsigned char *) 0x0010)\r
+#define ___INITRG (*(volatile unsigned char *) 0x0011)\r
+#define ___INITEE (*(volatile unsigned char *) 0x0012)\r
+#endif\r
+\r
+#if defined(_DO_FEED_COP_)\r
+#define __FEED_COP_IN_HLI() } __asm movb #0x55, _COP_RST_ADR; __asm movb #0xAA, _COP_RST_ADR; __asm {\r
+#else\r
+#define __FEED_COP_IN_HLI() /* do nothing */\r
+#endif\r
+\r
+#if !defined(FAR_DATA) && (defined( __BANKED__) || defined(__LARGE__))\r
+static void __far Init(void)\r
+#else\r
+static void Init(void)\r
+#endif\r
+ {\r
+/* purpose: 1) zero out RAM-areas where data is allocated */\r
+/* 2) copy initialization data from ROM to RAM */\r
+/* 3) call global constructors in C++ */\r
+/* called from: _Startup, LibInits */\r
+ __asm {\r
+ZeroOut:\r
+#if defined(__HIWARE_OBJECT_FILE_FORMAT__) && defined(__LARGE__)\r
+ LDX _startupData.pZeroOut:1 ; in the large memory model in the HIWARE format, pZeroOut is a 24 bit pointer\r
+#else\r
+ LDX _startupData.pZeroOut ; *pZeroOut\r
+#endif\r
+ LDY _startupData.nofZeroOuts ; nofZeroOuts\r
+ BEQ CopyDown ; if nothing to zero out\r
+\r
+NextZeroOut: PSHY ; save nofZeroOuts\r
+#ifdef FAR_DATA\r
+ LDAB 1,X+ ; load page of destination address\r
+ LDY 2,X+ ; load offset of destination address\r
+ __PIC_JSR(_SET_PAGE) ; sets the page in the correct page register\r
+#else /* FAR_DATA */\r
+ LDY 2,X+ ; start address and advance *pZeroOut (X = X+4)\r
+#endif /* FAR_DATA */\r
+ LDD 2,X+ ; byte count\r
+#ifdef __OPTIMIZE_FOR_SIZE__ /* -os, default */\r
+NextWord: CLR 1,Y+ ; clear memory byte\r
+ __FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */\r
+ DBNE D, NextWord ; dec byte count\r
+#else\r
+ LSRD ; /2 and save bit 0 in the carry\r
+ PSHX\r
+ LDX #0\r
+LoopClrW: STX 2,Y+ ; Word-Clear\r
+ __FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */\r
+ DBNE D, LoopClrW\r
+ PULX\r
+ BCC LastClr ; handle last byte\r
+ CLR 1,Y+\r
+LastClr:\r
+#endif\r
+ PULY ; restore nofZeroOuts\r
+ DEY ; dec nofZeroOuts\r
+ BNE NextZeroOut\r
+CopyDown:\r
+#ifdef __ELF_OBJECT_FILE_FORMAT__\r
+ LDX _startupData.toCopyDownBeg ; load address of copy down desc.\r
+#else\r
+ LDX _startupData.toCopyDownBeg:2 ; load address of copy down desc.\r
+#endif\r
+NextBlock:\r
+ LDD 2,X+ ; size of init-data -> D\r
+ BEQ funcInits ; end of copy down desc.\r
+#ifdef FAR_DATA\r
+ PSHD ; save counter\r
+ LDAB 1,X+ ; load destination page\r
+ LDY 2,X+ ; destination address\r
+ __PIC_JSR(_SET_PAGE) ; sets the destinations page register\r
+ PULD ; restore counter\r
+#else /* FAR_DATA */\r
+ LDY 2,X+ ; load destination address\r
+#endif /* FAR_DATA */\r
+\r
+#ifdef __OPTIMIZE_FOR_SIZE__ /* -os, default */\r
+Copy: MOVB 1,X+,1,Y+ ; move a byte from ROM to the data area\r
+ __FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */\r
+ DBNE D,Copy ; copy-byte loop\r
+#else\r
+ LSRD ; /2 and save bit 0 in the carry\r
+Copy: MOVW 2,X+,2,Y+ ; move a word from ROM to the data area\r
+ __FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */\r
+ DBNE D,Copy ; copy-word loop\r
+ BCC NextBlock ; handle last byte?\r
+ MOVB 1,X+,1,Y+ ; copy the last byte\r
+#endif\r
+ BRA NextBlock\r
+funcInits: ; call of global construtors is only in c++ necessary\r
+#if defined(__cplusplus)\r
+#if defined(__ELF_OBJECT_FILE_FORMAT__)\r
+#if defined( __BANKED__) || defined(__LARGE__)\r
+ LDY _startupData.nofInitBodies; load number of cpp.\r
+ BEQ done ; if cppcount == 0, goto done\r
+ LDX _startupData.initBodies ; load address of first module to initialize\r
+nextInit:\r
+ LEAX 3,X ; increment to next init\r
+ PSHX ; save address of next function to initialize\r
+ PSHY ; save cpp counter\r
+ CALL [-3,X] ; use double indirect call to load the page register also\r
+ PULY ; restore cpp counter\r
+ PULX ; restore actual address\r
+ DEY ; decrement cpp counter\r
+ BNE nextInit\r
+#else /* defined( __BANKED__) || defined(__LARGE__) */\r
+\r
+ LDD _startupData.nofInitBodies; load number of cpp.\r
+ BEQ done ; if cppcount == 0, goto done\r
+ LDX _startupData.initBodies ; load address of first module to initialize\r
+nextInit:\r
+ LDY 2,X+ ; load address of first module to initialize\r
+ PSHD\r
+ PSHX ; save actual address\r
+ JSR 0,Y ; call initialization function\r
+ PULX ; restore actual address\r
+ PULD ; restore cpp counter\r
+ DBNE D, nextInit\r
+#endif /* defined( __BANKED__) || defined(__LARGE__) */\r
+#else /* __ELF_OBJECT_FILE_FORMAT__ */\r
+ LDX _startupData.mInits ; load address of first module to initialize\r
+#if defined( __BANKED__) || defined(__LARGE__)\r
+nextInit: LDY 3,X+ ; load address of initialization function\r
+ BEQ done ; stop when address == 0\r
+ ; in common environments the offset of a function is never 0, so this test could be avoided\r
+#ifdef __InitFunctionsMayHaveOffset0__\r
+ BRCLR -1,X, done, 0xff ; stop when address == 0\r
+#endif /* __InitFunctionsMayHaveOffset0__ */\r
+ PSHX ; save address of next function to initialize\r
+ CALL [-3,X] ; use double indirect call to load the page register also\r
+#else /* defined( __BANKED__) || defined(__LARGE__) */\r
+nextInit:\r
+ LDY 2,X+ ; load address of first module to initialize\r
+ BEQ done ; stop when address of function == 0\r
+ PSHX ; save actual address\r
+ JSR 0,Y ; call initialization function\r
+#endif /* defined( __BANKED__) || defined(__LARGE__) */\r
+ PULX ; restore actual address\r
+ BRA nextInit\r
+#endif /* __ELF_OBJECT_FILE_FORMAT__ */\r
+done:\r
+#endif /* __cplusplus */\r
+ }\r
+}\r
+\r
+#if defined( __ELF_OBJECT_FILE_FORMAT__) && defined(__cplusplus )\r
+\r
+#if !defined(FAR_DATA) && (defined( __BANKED__) || defined(__LARGE__))\r
+static void __far Fini(void)\r
+#else\r
+static void Fini(void)\r
+#endif\r
+{\r
+/* purpose: 1) call global destructors in C++ */\r
+ __asm {\r
+#if defined( __BANKED__) || defined(__LARGE__)\r
+\r
+ LDY _startupData.nofFiniBodies; load number of cpp.\r
+ BEQ done ; if cppcount == 0, goto done\r
+ LDX _startupData.finiBodies ; load address of first module to finalize\r
+nextInit2:\r
+ LEAX 3,X ; increment to next init\r
+ PSHX ; save address of next function to finalize\r
+ PSHY ; save cpp counter\r
+ CALL [-3,X] ; use double indirect call to load the page register also\r
+ PULY ; restore cpp counter\r
+ PULX ; restore actual address\r
+ DEY ; decrement cpp counter\r
+ BNE nextInit2\r
+#else /* defined( __BANKED__) || defined(__LARGE__) */\r
+\r
+ LDD _startupData.nofFiniBodies; load number of cpp.\r
+ BEQ done ; if cppcount == 0, goto done\r
+ LDX _startupData.finiBodies ; load address of first module to finalize\r
+nextInit2:\r
+ LDY 2,X+ ; load address of first module to finalize\r
+ PSHD\r
+ PSHX ; save actual address\r
+ JSR 0,Y ; call finalize function\r
+ PULX ; restore actual address\r
+ PULD ; restore cpp counter\r
+ DBNE D, nextInit2\r
+#endif /* defined( __BANKED__) || defined(__LARGE__) */\r
+done:;\r
+ }\r
+}\r
+#endif\r
+\r
+\r
+#include "non_bank.sgm"\r
+\r
+#pragma MESSAGE DISABLE C12053 /* Stack-pointer change not in debugging-information */\r
+#pragma NO_FRAME\r
+#pragma NO_ENTRY\r
+#pragma NO_EXIT\r
+\r
+#ifdef __cplusplus\r
+ extern "C"\r
+#endif\r
+\r
+/* The function _Startup must be called in order to initialize global variables and to call main */\r
+/* You can adapt this function or call it from your startup code to implement a different startup */\r
+/* functionality. */\r
+\r
+/* You should also setup the needed IO registers as WINDEF (HC12A4 only) or the COP registers to run */\r
+/* on hardware */\r
+\r
+/* to set the reset vector several ways are possible : */\r
+/* 1. define the function with "interrupt 0" as done below in the first case */\r
+/* 2. add the following line to your prm file : VECTOR ADDRESS 0xfffe _Startup */\r
+/* of course, even more posibilities exists */\r
+/* the reset vector must be set so that the application has a defined entry point */\r
+\r
+#define STARTUP_FLAGS_NOT_INIT_SP (1<<1)\r
+\r
+#if defined(__SET_RESET_VECTOR__)\r
+void __interrupt 0 _Startup(void) {\r
+#else\r
+void _Startup(void) {\r
+#endif\r
+/* purpose: 1) initialize the stack\r
+ 2) initialize the RAM, copy down init data etc (Init)\r
+ 3) call main;\r
+ parameters: NONE\r
+ called from: _PRESTART-code generated by the Linker \r
+ or directly referenced by the reset vector */\r
+ for(;;) { /* forever: initialize the program; call the root-procedure */\r
+ if (!(_startupData.flags&STARTUP_FLAGS_NOT_INIT_SP)) {\r
+ /* initialize the stack pointer */\r
+ INIT_SP_FROM_STARTUP_DESC(); /*lint !e522 asm code */ /* HLI macro definition in hidef.h */\r
+ }\r
+\r
+#ifdef _HCS12_SERIALMON\r
+ /* for Monitor based software remap the RAM & EEPROM to adhere\r
+ to EB386. Edit RAM and EEPROM sections in PRM file to match these. */\r
+ ___INITRG = 0x00; /* lock registers block to 0x0000 */\r
+ ___INITRM = 0x39; /* lock Ram to end at 0x3FFF */\r
+ ___INITEE = 0x09; /* lock EEPROM block to end at 0x0fff */\r
+#endif\r
+ \r
+ /* Here user defined code could be inserted, the stack could be used */\r
+#if defined(_DO_DISABLE_COP_)\r
+ _DISABLE_COP();\r
+#endif \r
+\r
+ /* Example : Set up WinDef Register to allow Paging */\r
+#ifdef HC812A4 /* HC12 A4 derivative needs WINDEF to configure which pages are available */\r
+#if (__ENABLE_EPAGE__ != 0 || __ENABLE_DPAGE__ != 0 || __ENABLE_PPAGE__ != 0)\r
+ WINDEF= __ENABLE_EPAGE__ | __ENABLE_DPAGE__ | __ENABLE_PPAGE__;\r
+#endif\r
+#endif\r
+ Init(); /* zero out, copy down, call constructors */\r
+ /* Here user defined code could be inserted, all global variables are initilized */\r
+#if defined(_DO_ENABLE_COP_)\r
+ _ENABLE_COP(1);\r
+#endif\r
+\r
+ /* call main() */\r
+ (*_startupData.main)();\r
+\r
+ /* call destructors. Only done when this file is compiled as C++ and for the ELF object file format */\r
+ /* the HIWARE object file format does not support this */\r
+#if defined( __ELF_OBJECT_FILE_FORMAT__) && defined(__cplusplus )\r
+ Fini();\r
+#endif\r
+\r
+ } /* end loop forever */\r
+}\r
--- /dev/null
+/******************************************************************************\r
+ FILE : datapage.c\r
+ PURPOSE : paged data access runtime routines\r
+ MACHINE : Motorola 68HC12 (Target)\r
+ LANGUAGE : ANSI-C\r
+ HISTORY : 21.7.96 first version created\r
+******************************************************************************/\r
+\r
+/*\r
+ According to the -Cp option of the compiler the\r
+ __DPAGE__, __PPAGE__ and __EPAGE__ macros are defined.\r
+ If none of them is given as argument, then no page accesses should occur and\r
+ this runtime routine should not be used !\r
+ To be on the save side, the runtime routines are created anyway.\r
+ If some of the -Cp options are given an adapted versions which only covers the\r
+ needed cases is produced.\r
+*/\r
+\r
+/* if no compiler option -Cp is given, it is assumed that all possible are given : */\r
+\r
+/* Compile with option -DHCS12 to activate this code */\r
+#if defined(HCS12) || defined(_HCS12) /* HCS12 family has PPAGE register only at 0x30 */\r
+#define PPAGE_ADDR (0x30+REGISTER_BASE)\r
+#ifndef __PPAGE__ /* may be set already by option -CPPPAGE */\r
+#define __PPAGE__\r
+#endif\r
+/* Compile with option -DDG128 to activate this code */\r
+#elif defined DG128 /* HC912DG128 derivative has PPAGE register only at 0xFF */\r
+#define PPAGE_ADDR (0xFF+REGISTER_BASE)\r
+#ifndef __PPAGE__ /* may be set already by option -CPPPAGE */\r
+#define __PPAGE__\r
+#endif\r
+#elif defined(HC812A4)\r
+/* all setting default to A4 already */\r
+#endif\r
+\r
+\r
+#if !defined(__EPAGE__) && !defined(__PPAGE__) && !defined(__DPAGE__)\r
+/* as default use all page registers */\r
+#define __DPAGE__\r
+#define __EPAGE__\r
+#define __PPAGE__\r
+#endif\r
+\r
+/* modify the following defines to your memory configuration */\r
+\r
+#define EPAGE_LOW_BOUND 0x400u\r
+#define EPAGE_HIGH_BOUND 0x7ffu\r
+\r
+#define DPAGE_LOW_BOUND 0x7000u\r
+#define DPAGE_HIGH_BOUND 0x7fffu\r
+\r
+#define PPAGE_LOW_BOUND (DPAGE_HIGH_BOUND+1)\r
+#define PPAGE_HIGH_BOUND 0xBFFFu\r
+\r
+#define REGISTER_BASE 0x0u\r
+#ifndef DPAGE_ADDR\r
+#define DPAGE_ADDR (0x34u+REGISTER_BASE)\r
+#endif\r
+#ifndef EPAGE_ADDR\r
+#define EPAGE_ADDR (0x36u+REGISTER_BASE)\r
+#endif\r
+#ifndef PPAGE_ADDR\r
+#define PPAGE_ADDR (0x35u+REGISTER_BASE)\r
+#endif\r
+\r
+/*\r
+ The following parts about the defines are assumed in the code of _GET_PAGE_REG :\r
+ - the memory region controlled by DPAGE is above the area controlled by the EPAGE and\r
+ below the area controlled by the PPAGE.\r
+ - the lower bound of the PPAGE area is equal to be the higher bound of the DPAGE area + 1\r
+*/\r
+#if EPAGE_LOW_BOUND >= EPAGE_HIGH_BOUND || EPAGE_HIGH_BOUND >= DPAGE_LOW_BOUND || DPAGE_LOW_BOUND >= DPAGE_HIGH_BOUND || DPAGE_HIGH_BOUND >= PPAGE_LOW_BOUND || PPAGE_LOW_BOUND >= PPAGE_HIGH_BOUND\r
+#error /* please adapt _GET_PAGE_REG for this non default page configuration */\r
+#endif\r
+\r
+#if DPAGE_HIGH_BOUND+1 != PPAGE_LOW_BOUND\r
+#error /* please adapt _GET_PAGE_REG for this non default page configuration */\r
+#endif\r
+\r
+#include "hidef.h"\r
+#include "non_bank.sgm"\r
+#include "runtime.sgm"\r
+\r
+/* this module does either control if any access is in the bounds of the specified page or */\r
+/* ,if only one page is specified, just use this page. */\r
+/* This behavior is controlled by the define USE_SEVERAL_PAGES. */\r
+/* If !USE_SEVERAL_PAGES does increase the performance significantly */\r
+/* NOTE : When !USE_SEVERAL_PAGES, the page is also set for accesses outside of the area controlled */\r
+/* by this single page. But this is usually no problem because the page is set again before any other access */\r
+\r
+#if !defined(__DPAGE__) && !defined(__EPAGE__) && !defined(__PPAGE__)\r
+/* no page at all is specified */\r
+/* only specifing the right pages will speed up these functions a lot */\r
+#define USE_SEVERAL_PAGES 1\r
+#elif defined(__DPAGE__) && defined(__EPAGE__) || defined(__DPAGE__) && defined(__PPAGE__) || defined(__EPAGE__) && defined(__PPAGE__)\r
+/* more than one page register is used */\r
+#define USE_SEVERAL_PAGES 1\r
+#else\r
+\r
+#define USE_SEVERAL_PAGES 0\r
+\r
+#if defined(__DPAGE__) /* check which pages are used */\r
+#define PAGE_ADDR PPAGE_ADDR\r
+#elif defined(__EPAGE__)\r
+#define PAGE_ADDR EPAGE_ADDR\r
+#elif defined(__PPAGE__)\r
+#define PAGE_ADDR PPAGE_ADDR\r
+#else /* we dont know which page, decide it at runtime */\r
+#error /* must not happen */\r
+#endif\r
+\r
+#endif\r
+\r
+\r
+#if USE_SEVERAL_PAGES /* only needed for several pages support */\r
+/*--------------------------- _GET_PAGE_REG --------------------------------\r
+ Runtime routine to detect the right register depending on the 16 bit offset part\r
+ of an address.\r
+ This function is only used by the functions below.\r
+\r
+ Depending on the compiler options -Cp different versions of _GET_PAGE_REG are produced.\r
+\r
+ Arguments :\r
+ - Y : offset part of an address\r
+\r
+ Result :\r
+ if address Y is controlled by a page register :\r
+ - X : address of page register if Y is controlled by an page register\r
+ - Zero flag cleared\r
+ - all other registers remain unchanged\r
+\r
+ if address Y is not controlled by a page register :\r
+ - Zero flag is set\r
+ - all registers remain unchanged\r
+\r
+ --------------------------- _GET_PAGE_REG ----------------------------------*/\r
+\r
+#if defined(__DPAGE__)\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+#endif\r
+#pragma NO_ENTRY\r
+#pragma NO_EXIT\r
+#pragma NO_FRAME\r
+\r
+static void NEAR _GET_PAGE_REG(void) { /*lint -esym(528, _GET_PAGE_REG) used in asm code */\r
+ asm {\r
+L_DPAGE:\r
+ CPY #DPAGE_LOW_BOUND ; test of lower bound of DPAGE\r
+#if defined(__EPAGE__)\r
+ BLO L_EPAGE ; EPAGE accesses are possible\r
+#else\r
+ BLO L_NOPAGE ; no paged memory below accesses\r
+#endif\r
+ CPY #DPAGE_HIGH_BOUND ; test of higher bound DPAGE/lower bound PPAGE\r
+#if defined(__PPAGE__)\r
+ BHI L_PPAGE ; EPAGE accesses are possible\r
+#else\r
+ BHI L_NOPAGE ; no paged memory above accesses\r
+#endif\r
+FOUND_DPAGE:\r
+ LDX #DPAGE_ADDR ; load page register address and clear zero flag\r
+ RTS\r
+\r
+#if defined(__PPAGE__)\r
+L_PPAGE:\r
+ CPY #PPAGE_HIGH_BOUND ; test of higher bound of PPAGE\r
+ BHI L_NOPAGE\r
+FOUND_PPAGE:\r
+ LDX #PPAGE_ADDR ; load page register address and clear zero flag\r
+ RTS\r
+#endif\r
+\r
+#if defined(__EPAGE__)\r
+L_EPAGE:\r
+ CPY #EPAGE_LOW_BOUND ; test of lower bound of EPAGE\r
+ BLO L_NOPAGE\r
+ CPY #EPAGE_HIGH_BOUND ; test of higher bound of EPAGE\r
+ BHI L_NOPAGE\r
+\r
+FOUND_EPAGE:\r
+ LDX #EPAGE_ADDR ; load page register address and clear zero flag\r
+ RTS\r
+#endif\r
+\r
+L_NOPAGE:\r
+ ORCC #0x04 ; sets zero flag\r
+ RTS\r
+ }\r
+}\r
+\r
+#else /* !defined(__DPAGE__) */\r
+\r
+#if defined( __PPAGE__ )\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+#endif\r
+#pragma NO_ENTRY\r
+#pragma NO_EXIT\r
+#pragma NO_FRAME\r
+\r
+static void NEAR _GET_PAGE_REG(void) { /*lint -esym(528, _GET_PAGE_REG) used in asm code */\r
+ asm {\r
+L_PPAGE:\r
+ CPY #PPAGE_LOW_BOUND ; test of lower bound of PPAGE\r
+#if defined( __EPAGE__ )\r
+ BLO L_EPAGE\r
+#else\r
+ BLO L_NOPAGE ; no paged memory below\r
+#endif\r
+ CPY #PPAGE_HIGH_BOUND ; test of higher bound PPAGE\r
+ BHI L_NOPAGE\r
+FOUND_PPAGE:\r
+ LDX #PPAGE_ADDR ; load page register address and clear zero flag\r
+ RTS\r
+#if defined( __EPAGE__ )\r
+L_EPAGE:\r
+ CPY #EPAGE_LOW_BOUND ; test of lower bound of EPAGE\r
+ BLO L_NOPAGE\r
+ CPY #EPAGE_HIGH_BOUND ; test of higher bound of EPAGE\r
+ BHI L_NOPAGE\r
+FOUND_EPAGE:\r
+ LDX #EPAGE_ADDR ; load page register address and clear zero flag\r
+ RTS\r
+#endif\r
+\r
+L_NOPAGE: ; not in any allowed page area\r
+ ; its a far access to a non paged variable\r
+ ORCC #0x04 ; sets zero flag\r
+ RTS\r
+ }\r
+}\r
+\r
+#else /* !defined(__DPAGE__ ) && !defined( __PPAGE__) */\r
+#if defined(__EPAGE__)\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+#endif\r
+#pragma NO_ENTRY\r
+#pragma NO_EXIT\r
+#pragma NO_FRAME\r
+\r
+static void NEAR _GET_PAGE_REG(void) { /*lint -esym(528, _GET_PAGE_REG) used in asm code */\r
+ asm {\r
+L_EPAGE:\r
+ CPY #EPAGE_LOW_BOUND ; test of lower bound of EPAGE\r
+ BLO L_NOPAGE\r
+ CPY #EPAGE_HIGH_BOUND ; test of higher bound of EPAGE\r
+ BHI L_NOPAGE\r
+FOUND_EPAGE:\r
+ LDX #EPAGE_ADDR ; load page register address and clear zero flag\r
+ RTS\r
+\r
+L_NOPAGE: ; not in any allowed page area\r
+ ; its a far access to a non paged variable\r
+ ORCC #0x04 ; sets zero flag\r
+ RTS\r
+ }\r
+}\r
+\r
+#endif /* defined(__EPAGE__) */\r
+#endif /* defined(__PPAGE__) */\r
+#endif /* defined(__DPAGE__) */\r
+\r
+#endif /* USE_SEVERAL_PAGES */\r
+\r
+/*--------------------------- _SET_PAGE --------------------------------\r
+ Runtime routine to set the right page register. This routine is used if the compiler\r
+ does not know the right page register, i.e. if the option -Cp is used for more than\r
+ one pageregister or if the runtime option is used for one of the -Cp options.\r
+\r
+ Arguments :\r
+ - offset part of an address in the Y register\r
+ - page part of an address in the B register\r
+\r
+ Result :\r
+ - page part written into the correct page register.\r
+ - the old page register content is destroyed\r
+ - all processor registers remains unchanged\r
+ --------------------------- _SET_PAGE ----------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+#endif\r
+#pragma NO_ENTRY\r
+#pragma NO_EXIT\r
+#pragma NO_FRAME\r
+\r
+void NEAR _SET_PAGE(void) {\r
+#if USE_SEVERAL_PAGES\r
+ asm {\r
+ PSHX ; save X register\r
+ __PIC_JSR(_GET_PAGE_REG)\r
+ BEQ L_NOPAGE\r
+ STAB 0,X ; set page register\r
+L_NOPAGE:\r
+ PULX ; restore X register\r
+ RTS\r
+ }\r
+#else /* USE_SEVERAL_PAGES */\r
+ asm {\r
+ STAB PAGE_ADDR ; set page register\r
+ RTS\r
+ }\r
+#endif /* USE_SEVERAL_PAGES */\r
+}\r
+\r
+/*--------------------------- _LOAD_FAR_8 --------------------------------\r
+ This runtime routine is used to access paged memory via a runtime function.\r
+ It may also be used if the compiler option -Cp is not used with the runtime argument.\r
+\r
+ Arguments :\r
+ - offset part of an address in the Y register\r
+ - page part of an address in the B register\r
+\r
+ Result :\r
+ - value to be read in the B register\r
+ - all other registers remains unchanged\r
+ - all page register still contain the same value\r
+ --------------------------- _LOAD_FAR_8 ----------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+#endif\r
+#pragma NO_ENTRY\r
+#pragma NO_EXIT\r
+#pragma NO_FRAME\r
+\r
+void NEAR _LOAD_FAR_8(void) {\r
+#if USE_SEVERAL_PAGES\r
+ asm {\r
+ PSHX ; save X register\r
+ __PIC_JSR(_GET_PAGE_REG)\r
+ BEQ L_NOPAGE\r
+ PSHA ; save A register\r
+ LDAA 0,X ; save page register\r
+ STAB 0,X ; set page register\r
+ LDAB 0,Y ; actual load, overwrites page\r
+ STAA 0,X ; restore page register\r
+ PULA ; restore A register\r
+ PULX ; restore X register\r
+ RTS\r
+L_NOPAGE:\r
+ LDAB 0,Y ; actual load, overwrites page\r
+ PULX ; restore X register\r
+ RTS\r
+ }\r
+#else /* USE_SEVERAL_PAGES */\r
+ asm {\r
+ PSHA ; save A register\r
+ LDAA PAGE_ADDR ; save page register\r
+ STAB PAGE_ADDR ; set page register\r
+ LDAB 0,Y ; actual load, overwrites page\r
+ STAA PAGE_ADDR ; restore page register\r
+ PULA ; restore A register\r
+ RTS\r
+ }\r
+#endif /* USE_SEVERAL_PAGES */\r
+}\r
+\r
+/*--------------------------- _LOAD_FAR_16 --------------------------------\r
+ This runtime routine is used to access paged memory via a runtime function.\r
+ It may also be used if the compiler option -Cp is not used with the runtime argument.\r
+\r
+ Arguments :\r
+ - offset part of an address in the Y register\r
+ - page part of an address in the B register\r
+\r
+ Result :\r
+ - value to be read in the Y register\r
+ - all other registers remains unchanged\r
+ - all page register still contain the same value\r
+ --------------------------- _LOAD_FAR_16 ----------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+#endif\r
+#pragma NO_ENTRY\r
+#pragma NO_EXIT\r
+#pragma NO_FRAME\r
+\r
+void NEAR _LOAD_FAR_16(void) {\r
+#if USE_SEVERAL_PAGES\r
+ asm {\r
+ PSHX ; save X register\r
+ __PIC_JSR(_GET_PAGE_REG)\r
+ BEQ L_NOPAGE\r
+ PSHA ; save A register\r
+ LDAA 0,X ; save page register\r
+ STAB 0,X ; set page register\r
+ LDY 0,Y ; actual load, overwrites address\r
+ STAA 0,X ; restore page register\r
+ PULA ; restore A register\r
+ PULX ; restore X register\r
+ RTS\r
+L_NOPAGE:\r
+ LDY 0,Y ; actual load, overwrites address\r
+ PULX ; restore X register\r
+ RTS\r
+ }\r
+#else /* USE_SEVERAL_PAGES */\r
+ asm {\r
+ PSHA ; save A register\r
+ LDAA PAGE_ADDR ; save page register\r
+ STAB PAGE_ADDR ; set page register\r
+ LDY 0,Y ; actual load, overwrites address\r
+ STAA PAGE_ADDR ; restore page register\r
+ PULA ; restore A register\r
+ RTS\r
+ }\r
+#endif /* USE_SEVERAL_PAGES */\r
+}\r
+/*--------------------------- _LOAD_FAR_24 --------------------------------\r
+ This runtime routine is used to access paged memory via a runtime function.\r
+ It may also be used if the compiler option -Cp is not used with the runtime argument.\r
+\r
+ Arguments :\r
+ - offset part of an address in the Y register\r
+ - page part of an address in the B register\r
+\r
+ Result :\r
+ - value to be read in the Y:B registers\r
+ - all other registers remains unchanged\r
+ - all page register still contain the same value\r
+ --------------------------- _LOAD_FAR_24 ----------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+#endif\r
+#pragma NO_ENTRY\r
+#pragma NO_EXIT\r
+#pragma NO_FRAME\r
+\r
+void NEAR _LOAD_FAR_24(void) {\r
+#if USE_SEVERAL_PAGES\r
+ asm {\r
+ PSHX ; save X register\r
+ __PIC_JSR(_GET_PAGE_REG)\r
+ BEQ L_NOPAGE\r
+ PSHA ; save A register\r
+ LDAA 0,X ; save page register\r
+ STAB 0,X ; set page register\r
+ LDAB 0,Y ; actual load, overwrites page of address\r
+ LDY 1,Y ; actual load, overwrites offset of address\r
+ STAA 0,X ; restore page register\r
+ PULA ; restore A register\r
+ PULX ; restore X register\r
+ RTS\r
+L_NOPAGE:\r
+ LDAB 0,Y ; actual load, overwrites page of address\r
+ LDY 1,Y ; actual load, overwrites offset of address\r
+ PULX ; restore X register\r
+ RTS\r
+ }\r
+#else /* USE_SEVERAL_PAGES */\r
+ asm {\r
+ PSHA ; save A register\r
+ LDAA PAGE_ADDR ; save page register\r
+ STAB PAGE_ADDR ; set page register\r
+ LDAB 0,Y ; actual load, overwrites page of address\r
+ LDY 1,Y ; actual load, overwrites offset of address\r
+ STAA PAGE_ADDR ; restore page register\r
+ PULA ; restore A register\r
+ RTS\r
+ }\r
+#endif /* USE_SEVERAL_PAGES */\r
+\r
+}\r
+\r
+/*--------------------------- _LOAD_FAR_32 --------------------------------\r
+ This runtime routine is used to access paged memory via a runtime function.\r
+ It may also be used if the compiler option -Cp is not used with the runtime argument.\r
+\r
+ Arguments :\r
+ - offset part of an address in the Y register\r
+ - page part of an address in the B register\r
+\r
+ Result :\r
+ - low 16 bit of value to be read in the D registers\r
+ - high 16 bit of value to be read in the Y registers\r
+ - all other registers remains unchanged\r
+ - all page register still contain the same value\r
+ --------------------------- _LOAD_FAR_32 ----------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+#endif\r
+#pragma NO_ENTRY\r
+#pragma NO_EXIT\r
+#pragma NO_FRAME\r
+\r
+void NEAR _LOAD_FAR_32(void) {\r
+#if USE_SEVERAL_PAGES\r
+ asm {\r
+ PSHX ; save X register\r
+ __PIC_JSR(_GET_PAGE_REG)\r
+ BEQ L_NOPAGE\r
+ LDAA 0,X ; save page register\r
+ PSHA ; put it onto the stack\r
+ STAB 0,X ; set page register\r
+ LDD 2,Y ; actual load, low word\r
+ LDY 0,Y ; actual load, high word\r
+ MOVB 1,SP+,0,X ; restore page register\r
+ PULX ; restore X register\r
+ RTS\r
+L_NOPAGE:\r
+ LDD 2,Y ; actual load, low word\r
+ LDY 0,Y ; actual load, high word\r
+ PULX ; restore X register\r
+ RTS\r
+ }\r
+#else /* USE_SEVERAL_PAGES */\r
+ asm {\r
+ LDAA PAGE_ADDR ; save page register\r
+ PSHA ; put it onto the stack\r
+ STAB PAGE_ADDR ; set page register\r
+ LDD 2,Y ; actual load, low word\r
+ LDY 0,Y ; actual load, high word\r
+ MOVB 1,SP+,PAGE_ADDR; restore page register\r
+ RTS\r
+ }\r
+#endif /* USE_SEVERAL_PAGES */\r
+}\r
+\r
+/*--------------------------- _STORE_FAR_8 --------------------------------\r
+ This runtime routine is used to access paged memory via a runtime function.\r
+ It may also be used if the compiler option -Cp is not used with the runtime argument.\r
+\r
+ Arguments :\r
+ - offset part of an address in the Y register\r
+ - page part of an address in the B register\r
+ - value to be stored in the B register\r
+\r
+ Result :\r
+ - value stored at the address\r
+ - all registers remains unchanged\r
+ - all page register still contain the same value\r
+ --------------------------- _STORE_FAR_8 ----------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+#endif\r
+#pragma NO_ENTRY\r
+#pragma NO_EXIT\r
+#pragma NO_FRAME\r
+\r
+void NEAR _STORE_FAR_8(void) {\r
+#if USE_SEVERAL_PAGES\r
+ asm {\r
+ PSHX ; save X register\r
+ __PIC_JSR(_GET_PAGE_REG)\r
+ BEQ L_NOPAGE\r
+ PSHB ; save B register\r
+ LDAB 0,X ; save page register\r
+ MOVB 0,SP, 0,X ; set page register\r
+ STAA 0,Y ; store the value passed in A\r
+ STAB 0,X ; restore page register\r
+ PULB ; restore B register\r
+ PULX ; restore X register\r
+ RTS\r
+L_NOPAGE:\r
+ STAA 0,Y ; store the value passed in A\r
+ PULX ; restore X register\r
+ RTS\r
+ }\r
+#else /* USE_SEVERAL_PAGES */\r
+ asm {\r
+ PSHB ; save A register\r
+ LDAB PAGE_ADDR ; save page register\r
+ MOVB 0,SP,PAGE_ADDR ; set page register\r
+ STAA 0,Y ; store the value passed in A\r
+ STAB PAGE_ADDR ; restore page register\r
+ PULB ; restore B register\r
+ RTS\r
+ }\r
+#endif /* USE_SEVERAL_PAGES */\r
+}\r
+\r
+/*--------------------------- _STORE_FAR_16 --------------------------------\r
+ This runtime routine is used to access paged memory via a runtime function.\r
+ It may also be used if the compiler option -Cp is not used with the runtime argument.\r
+\r
+ Arguments :\r
+ - offset part of an address in the Y register\r
+ - page part of an address in the B register\r
+ - value to be stored in the X register\r
+\r
+ Result :\r
+ - value stored at the address\r
+ - all registers remains unchanged\r
+ - all page register still contain the same value\r
+ --------------------------- _STORE_FAR_16 ----------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+#endif\r
+#pragma NO_ENTRY\r
+#pragma NO_EXIT\r
+#pragma NO_FRAME\r
+\r
+void NEAR _STORE_FAR_16(void) {\r
+#if USE_SEVERAL_PAGES\r
+ asm {\r
+ PSHX ; save X register\r
+ __PIC_JSR(_GET_PAGE_REG)\r
+ BEQ L_NOPAGE\r
+\r
+ PSHA\r
+ LDAA 0,X ; save page register\r
+ STAB 0,X ; set page register\r
+ MOVW 1,SP, 0,Y ; store the value passed in X\r
+ STAA 0,X ; restore page register\r
+ PULA ; restore A register\r
+ PULX ; restore X register\r
+ RTS\r
+\r
+L_NOPAGE:\r
+ STX 0,Y ; store the value passed in X\r
+ PULX ; restore X register\r
+ RTS\r
+ }\r
+#else /* USE_SEVERAL_PAGES */\r
+ asm {\r
+ PSHA ; save A register\r
+ LDAA PAGE_ADDR ; save page register\r
+ STAB PAGE_ADDR ; set page register\r
+ STX 0,Y ; store the value passed in X\r
+ STAA PAGE_ADDR ; restore page register\r
+ PULA ; restore A register\r
+ RTS\r
+ }\r
+#endif /* USE_SEVERAL_PAGES */\r
+}\r
+/*--------------------------- _STORE_FAR_24 --------------------------------\r
+ This runtime routine is used to access paged memory via a runtime function.\r
+ It may also be used if the compiler option -Cp is not used with the runtime argument.\r
+\r
+ Arguments :\r
+ - offset part of an address in the Y register\r
+ - page part of an address in the B register\r
+ - value to be stored in the X:A registers (X : low 16 bit, A : high 8 bit)\r
+\r
+ Result :\r
+ - value stored at the address\r
+ - all registers remains unchanged\r
+ - all page register still contain the same value\r
+ --------------------------- _STORE_FAR_24 ----------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+#endif\r
+#pragma NO_ENTRY\r
+#pragma NO_EXIT\r
+#pragma NO_FRAME\r
+\r
+void NEAR _STORE_FAR_24(void) {\r
+#if USE_SEVERAL_PAGES\r
+ asm {\r
+ PSHX ; save X register\r
+ __PIC_JSR(_GET_PAGE_REG)\r
+ BEQ L_NOPAGE\r
+\r
+ PSHA\r
+ LDAA 0,X ; save page register\r
+ STAB 0,X ; set page register\r
+ MOVW 1,SP, 1,Y ; store the value passed in X\r
+ MOVB 0,SP, 0,Y ; store the value passed in A\r
+ STAA 0,X ; restore page register\r
+ PULA ; restore A register\r
+ PULX ; restore X register\r
+ RTS\r
+\r
+L_NOPAGE:\r
+ STX 1,Y ; store the value passed in X\r
+ STAA 0,Y ; store the value passed in X\r
+ PULX ; restore X register\r
+ RTS\r
+ }\r
+#else /* USE_SEVERAL_PAGES */\r
+ asm {\r
+ PSHA ; save A register\r
+ LDAA PAGE_ADDR ; save page register\r
+ STAB PAGE_ADDR ; set page register\r
+ MOVB 0,SP, 0,Y ; store the value passed in A\r
+ STX 1,Y ; store the value passed in X\r
+ STAA PAGE_ADDR ; restore page register\r
+ PULA ; restore A register\r
+ RTS\r
+ }\r
+#endif /* USE_SEVERAL_PAGES */\r
+}\r
+/*--------------------------- _STORE_FAR_32 --------------------------------\r
+ This runtime routine is used to access paged memory via a runtime function.\r
+ It may also be used if the compiler option -Cp is not used with the runtime argument.\r
+\r
+ Arguments :\r
+ - offset part of an address in the Y register\r
+ - page part of an address is on the stack at 3,SP (just below the return address)\r
+ - value to be stored in the X:D registers (D : low 16 bit, X : high 16 bit)\r
+\r
+ Result :\r
+ - value stored at the address\r
+ - all registers remains unchanged\r
+ - the page part is removed from the stack\r
+ - all page register still contain the same value\r
+ --------------------------- _STORE_FAR_32 ----------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+#endif\r
+#pragma NO_ENTRY\r
+#pragma NO_EXIT\r
+#pragma NO_FRAME\r
+\r
+void NEAR _STORE_FAR_32(void) {\r
+#if USE_SEVERAL_PAGES\r
+ asm {\r
+ PSHX ; save X register\r
+ __PIC_JSR(_GET_PAGE_REG)\r
+ BEQ L_NOPAGE\r
+\r
+ PSHD\r
+ LDAA 0,X ; save page register\r
+ MOVB 6,SP, 0,X ; set page register\r
+ MOVW 2,SP, 0,Y ; store the value passed in X (high word)\r
+ MOVW 0,SP, 2,Y ; store the value passed in D (low word)\r
+ STAA 0,X ; restore page register\r
+ PULD ; restore A register\r
+ BRA done\r
+\r
+L_NOPAGE:\r
+ MOVW 0,SP, 0,Y ; store the value passed in X (high word)\r
+ STD 2,Y ; store the value passed in D (low word)\r
+done:\r
+ PULX ; restore X register\r
+ MOVW 0,SP, 1,+SP ; move return address\r
+ RTS\r
+ }\r
+#else /* USE_SEVERAL_PAGES */\r
+ asm {\r
+ PSHD ; save D register\r
+ LDAA PAGE_ADDR ; save page register\r
+ LDAB 4,SP ; load page part of address\r
+ STAB PAGE_ADDR ; set page register\r
+ STX 0,Y ; store the value passed in X\r
+ MOVW 0,SP, 2,Y ; store the value passed in D (low word)\r
+ STAA PAGE_ADDR ; restore page register\r
+ PULD ; restore D register\r
+ MOVW 0,SP, 1,+SP ; move return address\r
+ RTS\r
+ }\r
+#endif /* USE_SEVERAL_PAGES */\r
+}\r
+\r
+/*--------------------------- _FAR_COPY --------------------------------\r
+ This runtime routine is used to access paged memory via a runtime function.\r
+ It may also be used if the compiler option -Cp is not used with the runtime argument.\r
+\r
+ Arguments :\r
+ - offset part of the source int the X register\r
+ - page part of the source in the A register\r
+ - offset part of the dest int the Y register\r
+ - page part of the dest in the B register\r
+ - number of bytes to be copied at 2,SP. The number of bytes is always > 0\r
+\r
+ Result :\r
+ - memory area copied\r
+ - no registers are saved, i.e. all registers may be destroied\r
+ - all page register still contain the same value\r
+\r
+\r
+ stack-structure at the loop-label:\r
+ 0,SP : destination offset\r
+ 2,SP : source page\r
+ 3,SP : destination page\r
+ 4,SP : source offset\r
+ 6,SP : return address\r
+ 8,SP : counter, > 0\r
+ --------------------------- _FAR_COPY ----------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+#endif\r
+#pragma NO_ENTRY\r
+#pragma NO_EXIT\r
+#pragma NO_FRAME\r
+\r
+void NEAR _FAR_COPY(void) {\r
+#if USE_SEVERAL_PAGES\r
+ asm {\r
+ DEX ; source addr-=1, because loop counter ends at 1\r
+ PSHX ; save source offset\r
+ PSHD ; save both pages\r
+ DEY ; destination addr-=1, because loop counter ends at 1\r
+ PSHY ; save destination offset\r
+ LDX 8,SP ; load counter, assuming counter > 0\r
+\r
+loop:\r
+ LDD 4,SP ; load source offset\r
+ LEAY D,X ; calcutate actual source address\r
+ LDAB 2,SP ; load source page\r
+ __PIC_JSR (_LOAD_FAR_8); load 1 source byte\r
+ PSHB ; save value\r
+ LDD 0+1,SP ; load destination offset\r
+ LEAY D,X ; calcutate acual destination address\r
+ PULA ; restore value\r
+ LDAB 3,SP ; load destination page\r
+ __PIC_JSR (_STORE_FAR_8); store one byte\r
+ DEX\r
+ BNE loop\r
+ LDX 6,SP ; load return address\r
+ LEAS 10,SP ; release stack\r
+ JMP 0,X ; return\r
+ }\r
+#else\r
+ asm {\r
+ PSHD ; store page registers\r
+ TFR X,D\r
+ ADDD 4,SP ; calculate source end address\r
+ STD 4,SP\r
+ PULB ; reload source page\r
+ LDAA PAGE_ADDR ; save page register\r
+ PSHA\r
+loop:\r
+ STAB PAGE_ADDR ; set source page\r
+ LDAA 1,X+ ; load value\r
+ MOVB 1,SP, PAGE_ADDR ; set destination page\r
+ STAA 1,Y+\r
+ CPX 4,SP\r
+ BNE loop\r
+\r
+ LDAA 2,SP+ ; restore old page value and release stack\r
+ STAA PAGE_ADDR ; store it into page register\r
+ LDX 4,SP+ ; release stack and load return address\r
+ JMP 0,X ; return\r
+ }\r
+#endif\r
+}\r
+\r
--- /dev/null
+\r
+PROGRAM "E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior_banked\bin\P&E_ICD.abs"\r
+\r
+*********************************************************************************************\r
+TARGET SECTION\r
+---------------------------------------------------------------------------------------------\r
+Processor : Motorola HC12\r
+Memory Model: BANKED\r
+File Format : ELF\Dwarf 2.0\r
+Linker : SmartLinker V-5.0.22 Build 4047, Feb 17 2004\r
+\r
+*********************************************************************************************\r
+FILE SECTION\r
+---------------------------------------------------------------------------------------------\r
+Start12.c.o Model: BANKED, Lang: ANSI-C\r
+STRING.C.o (ansibi.lib) Model: BANKED, Lang: ANSI-C\r
+rtshc12.c.o (ansibi.lib) Model: BANKED, Lang: ANSI-C\r
+Cpu.C.o Model: BANKED, Lang: ANSI-C\r
+IO_Map.C.o Model: BANKED, Lang: ANSI-C\r
+Vectors.c.o Model: BANKED, Lang: ANSI-C\r
+RTOSDemo.C.o Model: BANKED, Lang: ANSI-C\r
+main.c.o Model: BANKED, Lang: ANSI-C\r
+ParTest.c.o Model: BANKED, Lang: ANSI-C\r
+serial.c.o Model: BANKED, Lang: ANSI-C\r
+tasks.c.o Model: BANKED, Lang: ANSI-C\r
+queue.c.o Model: BANKED, Lang: ANSI-C\r
+list.c.o Model: BANKED, Lang: ANSI-C\r
+heap_2.c.o Model: BANKED, Lang: ANSI-C\r
+flash.c.o Model: BANKED, Lang: ANSI-C\r
+dynamic.c.o Model: BANKED, Lang: ANSI-C\r
+PollQ.c.o Model: BANKED, Lang: ANSI-C\r
+TickTimer.C.o Model: BANKED, Lang: ANSI-C\r
+Byte1.C.o Model: BANKED, Lang: ANSI-C\r
+PE_Timer.C.o Model: BANKED, Lang: ANSI-C\r
+comtest.c.o Model: BANKED, Lang: ANSI-C\r
+COM0.C.o Model: BANKED, Lang: ANSI-C\r
+port.c.o Model: BANKED, Lang: ANSI-C\r
+integer.c.o Model: BANKED, Lang: ANSI-C\r
+BlockQ.c.o Model: BANKED, Lang: ANSI-C\r
+death.c.o Model: BANKED, Lang: ANSI-C\r
+\r
+*********************************************************************************************\r
+STARTUP SECTION\r
+---------------------------------------------------------------------------------------------\r
+Entry point: 0xC000 (_EntryPoint)\r
+_startupData is allocated at 0xC07C and uses 24 Bytes\r
+extern struct _tagStartup {\r
+ unsigned flags 0\r
+ _PFunc main 0x30809A (main)\r
+ long stackOffset 0x3988\r
+ unsigned nofZeroOut 1\r
+ _Range pZeroOut 0x1000 10505\r
+ _Copy *toCopyDownBeg 0xC3B5\r
+ int nofLibInits 0\r
+ _LibInit *libInits 0xC098\r
+ int nofInitBodies 0\r
+ _Cpp *initBodies 0xC09A\r
+ int nofFiniBodies 0\r
+ _Cpp *finiBodies 0xC09A\r
+} _startupData;\r
+\r
+*********************************************************************************************\r
+SECTION-ALLOCATION SECTION\r
+Section Name Size Type From To Segment\r
+---------------------------------------------------------------------------------------------\r
+.data 1 R/W 0x1000 0x1000 RAM\r
+.text 587 R 0x308000 0x30824A ROM_PAGE30\r
+.init 124 R 0xC000 0xC07B ROM_C000\r
+.startData 30 R 0xC07C 0xC099 ROM_C000\r
+.rodata1 183 R 0xC09A 0xC150 ROM_C000\r
+NON_BANKED 612 R 0xC151 0xC3B4 ROM_C000\r
+.copy 27 R 0xC3B5 0xC3CF ROM_C000\r
+.abs_section_3f 1 N/I 0x3F 0x3F .absSeg0\r
+.abs_section_8d 1 N/I 0x8D 0x8D .absSeg1\r
+.abs_section_86 1 N/I 0x86 0x86 .absSeg2\r
+.abs_section_8b 1 N/I 0x8B 0x8B .absSeg3\r
+.abs_section_12d 1 N/I 0x12D 0x12D .absSeg4\r
+.abs_section_126 1 N/I 0x126 0x126 .absSeg5\r
+.abs_section_12b 1 N/I 0x12B 0x12B .absSeg6\r
+.abs_section_ff06 1 N/I 0xFF06 0xFF06 .absSeg7\r
+.abs_section_ff07 1 N/I 0xFF07 0xFF07 .absSeg8\r
+.abs_section_ff01 1 N/I 0xFF01 0xFF01 .absSeg9\r
+.abs_section_2b 1 N/I 0x2B 0x2B .absSeg10\r
+.abs_section_2c 1 N/I 0x2C 0x2C .absSeg11\r
+.abs_section_2a 1 N/I 0x2A 0x2A .absSeg12\r
+.abs_section_2e 1 N/I 0x2E 0x2E .absSeg13\r
+.abs_section_2f 1 N/I 0x2F 0x2F .absSeg14\r
+.abs_section_2d 1 N/I 0x2D 0x2D .absSeg15\r
+.abs_section_28 1 N/I 0x28 0x28 .absSeg16\r
+.abs_section_29 1 N/I 0x29 0x29 .absSeg17\r
+.abs_section_142 1 N/I 0x142 0x142 .absSeg18\r
+.abs_section_143 1 N/I 0x143 0x143 .absSeg19\r
+.abs_section_140 1 N/I 0x140 0x140 .absSeg20\r
+.abs_section_141 1 N/I 0x141 0x141 .absSeg21\r
+.abs_section_14b 1 N/I 0x14B 0x14B .absSeg22\r
+.abs_section_150 1 N/I 0x150 0x150 .absSeg23\r
+.abs_section_151 1 N/I 0x151 0x151 .absSeg24\r
+.abs_section_152 1 N/I 0x152 0x152 .absSeg25\r
+.abs_section_153 1 N/I 0x153 0x153 .absSeg26\r
+.abs_section_158 1 N/I 0x158 0x158 .absSeg27\r
+.abs_section_159 1 N/I 0x159 0x159 .absSeg28\r
+.abs_section_15a 1 N/I 0x15A 0x15A .absSeg29\r
+.abs_section_15b 1 N/I 0x15B 0x15B .absSeg30\r
+.abs_section_154 1 N/I 0x154 0x154 .absSeg31\r
+.abs_section_155 1 N/I 0x155 0x155 .absSeg32\r
+.abs_section_156 1 N/I 0x156 0x156 .absSeg33\r
+.abs_section_157 1 N/I 0x157 0x157 .absSeg34\r
+.abs_section_15c 1 N/I 0x15C 0x15C .absSeg35\r
+.abs_section_15d 1 N/I 0x15D 0x15D .absSeg36\r
+.abs_section_15e 1 N/I 0x15E 0x15E .absSeg37\r
+.abs_section_15f 1 N/I 0x15F 0x15F .absSeg38\r
+.abs_section_144 1 N/I 0x144 0x144 .absSeg39\r
+.abs_section_145 1 N/I 0x145 0x145 .absSeg40\r
+.abs_section_16c 1 N/I 0x16C 0x16C .absSeg41\r
+.abs_section_164 1 N/I 0x164 0x164 .absSeg42\r
+.abs_section_165 1 N/I 0x165 0x165 .absSeg43\r
+.abs_section_166 1 N/I 0x166 0x166 .absSeg44\r
+.abs_section_167 1 N/I 0x167 0x167 .absSeg45\r
+.abs_section_168 1 N/I 0x168 0x168 .absSeg46\r
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+.abs_section_1d 1 N/I 0x1D 0x1D .absSeg357\r
+.abs_section_13 1 N/I 0x13 0x13 .absSeg358\r
+.abs_section_b 1 N/I 0xB 0xB .absSeg359\r
+.abs_section_257 1 N/I 0x257 0x257 .absSeg360\r
+.abs_section_14 1 N/I 0x14 0x14 .absSeg361\r
+.abs_section_17 1 N/I 0x17 0x17 .absSeg362\r
+.abs_section_43 1 N/I 0x43 0x43 .absSeg363\r
+.abs_section_42 1 N/I 0x42 0x42 .absSeg364\r
+.abs_section_60 1 N/I 0x60 0x60 .absSeg365\r
+.abs_section_61 1 N/I 0x61 0x61 .absSeg366\r
+.abs_section_1a 1 N/I 0x1A 0x1A .absSeg367\r
+.abs_section_1b 1 N/I 0x1B 0x1B .absSeg368\r
+.abs_section_70 1 N/I 0x70 0x70 .absSeg369\r
+.abs_section_71 1 N/I 0x71 0x71 .absSeg370\r
+.abs_section_a 1 N/I 0xA 0xA .absSeg371\r
+.abs_section_264 1 N/I 0x264 0x264 .absSeg372\r
+.abs_section_26c 1 N/I 0x26C 0x26C .absSeg373\r
+.abs_section_254 1 N/I 0x254 0x254 .absSeg374\r
+.abs_section_25c 1 N/I 0x25C 0x25C .absSeg375\r
+.abs_section_24c 1 N/I 0x24C 0x24C .absSeg376\r
+.abs_section_244 1 N/I 0x244 0x244 .absSeg377\r
+.abs_section_266 1 N/I 0x266 0x266 .absSeg378\r
+.abs_section_26e 1 N/I 0x26E 0x26E .absSeg379\r
+.abs_section_25e 1 N/I 0x25E 0x25E .absSeg380\r
+.abs_section_267 1 N/I 0x267 0x267 .absSeg381\r
+.abs_section_26f 1 N/I 0x26F 0x26F .absSeg382\r
+.abs_section_25f 1 N/I 0x25F 0x25F .absSeg383\r
+.abs_section_3a 1 N/I 0x3A 0x3A .absSeg384\r
+.abs_section_8f 1 N/I 0x8F 0x8F .absSeg385\r
+.abs_section_12f 1 N/I 0x12F 0x12F .absSeg386\r
+.abs_section_8 1 N/I 0x8 0x8 .absSeg387\r
+.abs_section_32 1 N/I 0x32 0x32 .absSeg388\r
+.abs_section_30 1 N/I 0x30 0x30 .absSeg389\r
+.abs_section_265 1 N/I 0x265 0x265 .absSeg390\r
+.abs_section_26d 1 N/I 0x26D 0x26D .absSeg391\r
+.abs_section_255 1 N/I 0x255 0x255 .absSeg392\r
+.abs_section_25d 1 N/I 0x25D 0x25D .absSeg393\r
+.abs_section_24d 1 N/I 0x24D 0x24D .absSeg394\r
+.abs_section_245 1 N/I 0x245 0x245 .absSeg395\r
+.abs_section_260 1 N/I 0x260 0x260 .absSeg396\r
+.abs_section_261 1 N/I 0x261 0x261 .absSeg397\r
+.abs_section_269 1 N/I 0x269 0x269 .absSeg398\r
+.abs_section_251 1 N/I 0x251 0x251 .absSeg399\r
+.abs_section_259 1 N/I 0x259 0x259 .absSeg400\r
+.abs_section_249 1 N/I 0x249 0x249 .absSeg401\r
+.abs_section_241 1 N/I 0x241 0x241 .absSeg402\r
+.abs_section_268 1 N/I 0x268 0x268 .absSeg403\r
+.abs_section_250 1 N/I 0x250 0x250 .absSeg404\r
+.abs_section_258 1 N/I 0x258 0x258 .absSeg405\r
+.abs_section_248 1 N/I 0x248 0x248 .absSeg406\r
+.abs_section_240 1 N/I 0x240 0x240 .absSeg407\r
+.abs_section_c 1 N/I 0xC 0xC .absSeg408\r
+.abs_section_a4 1 N/I 0xA4 0xA4 .absSeg409\r
+.abs_section_a2 1 N/I 0xA2 0xA2 .absSeg410\r
+.abs_section_a5 1 N/I 0xA5 0xA5 .absSeg411\r
+.abs_section_a0 1 N/I 0xA0 0xA0 .absSeg412\r
+.abs_section_a1 1 N/I 0xA1 0xA1 .absSeg413\r
+.abs_section_a3 1 N/I 0xA3 0xA3 .absSeg414\r
+.abs_section_a8 1 N/I 0xA8 0xA8 .absSeg415\r
+.abs_section_a9 1 N/I 0xA9 0xA9 .absSeg416\r
+.abs_section_c4 1 N/I 0xC4 0xC4 .absSeg417\r
+.abs_section_263 1 N/I 0x263 0x263 .absSeg418\r
+.abs_section_d 1 N/I 0xD 0xD .absSeg419\r
+.abs_section_26b 1 N/I 0x26B 0x26B .absSeg420\r
+.abs_section_253 1 N/I 0x253 0x253 .absSeg421\r
+.abs_section_25b 1 N/I 0x25B 0x25B .absSeg422\r
+.abs_section_24b 1 N/I 0x24B 0x24B .absSeg423\r
+.abs_section_243 1 N/I 0x243 0x243 .absSeg424\r
+.abs_section_35 1 N/I 0x35 0x35 .absSeg425\r
+.abs_section_3b 1 N/I 0x3B 0x3B .absSeg426\r
+.abs_section_ca 1 N/I 0xCA 0xCA .absSeg427\r
+.abs_section_cb 1 N/I 0xCB 0xCB .absSeg428\r
+.abs_section_ce 1 N/I 0xCE 0xCE .absSeg429\r
+.abs_section_cf 1 N/I 0xCF 0xCF .absSeg430\r
+.abs_section_cc 1 N/I 0xCC 0xCC .absSeg431\r
+.abs_section_cd 1 N/I 0xCD 0xCD .absSeg432\r
+.abs_section_d2 1 N/I 0xD2 0xD2 .absSeg433\r
+.abs_section_d3 1 N/I 0xD3 0xD3 .absSeg434\r
+.abs_section_d6 1 N/I 0xD6 0xD6 .absSeg435\r
+.abs_section_d7 1 N/I 0xD7 0xD7 .absSeg436\r
+.abs_section_d4 1 N/I 0xD4 0xD4 .absSeg437\r
+.abs_section_d5 1 N/I 0xD5 0xD5 .absSeg438\r
+.abs_section_da 1 N/I 0xDA 0xDA .absSeg439\r
+.abs_section_d8 1 N/I 0xD8 0xD8 .absSeg440\r
+.abs_section_d9 1 N/I 0xD9 0xD9 .absSeg441\r
+.abs_section_dd 1 N/I 0xDD 0xDD .absSeg442\r
+.abs_section_db 1 N/I 0xDB 0xDB .absSeg443\r
+.abs_section_f2 1 N/I 0xF2 0xF2 .absSeg444\r
+.abs_section_f0 1 N/I 0xF0 0xF0 .absSeg445\r
+.abs_section_f1 1 N/I 0xF1 0xF1 .absSeg446\r
+.abs_section_f5 1 N/I 0xF5 0xF5 .absSeg447\r
+.abs_section_f3 1 N/I 0xF3 0xF3 .absSeg448\r
+.abs_section_fa 1 N/I 0xFA 0xFA .absSeg449\r
+.abs_section_f8 1 N/I 0xF8 0xF8 .absSeg450\r
+.abs_section_f9 1 N/I 0xF9 0xF9 .absSeg451\r
+.abs_section_fd 1 N/I 0xFD 0xFD .absSeg452\r
+.abs_section_fb 1 N/I 0xFB 0xFB .absSeg453\r
+.abs_section_34 1 N/I 0x34 0x34 .absSeg454\r
+.abs_section_48 1 N/I 0x48 0x48 .absSeg455\r
+.abs_section_49 1 N/I 0x49 0x49 .absSeg456\r
+.abs_section_4a 1 N/I 0x4A 0x4A .absSeg457\r
+.abs_section_4b 1 N/I 0x4B 0x4B .absSeg458\r
+.abs_section_4e 1 N/I 0x4E 0x4E .absSeg459\r
+.abs_section_4f 1 N/I 0x4F 0x4F .absSeg460\r
+.abs_section_4c 1 N/I 0x4C 0x4C .absSeg461\r
+.abs_section_6d 1 N/I 0x6D 0x6D .absSeg462\r
+.abs_section_40 1 N/I 0x40 0x40 .absSeg463\r
+.abs_section_46 1 N/I 0x46 0x46 .absSeg464\r
+.abs_section_4d 1 N/I 0x4D 0x4D .absSeg465\r
+.abs_section_47 1 N/I 0x47 0x47 .absSeg466\r
+.abs_section_256 1 N/I 0x256 0x256 .absSeg467\r
+.abs_section_24e 1 N/I 0x24E 0x24E .absSeg468\r
+.abs_section_82 2 N/I 0x82 0x83 .absSeg469\r
+.abs_section_84 2 N/I 0x84 0x85 .absSeg470\r
+.abs_section_90 2 N/I 0x90 0x91 .absSeg471\r
+.abs_section_92 2 N/I 0x92 0x93 .absSeg472\r
+.abs_section_94 2 N/I 0x94 0x95 .absSeg473\r
+.abs_section_96 2 N/I 0x96 0x97 .absSeg474\r
+.abs_section_98 2 N/I 0x98 0x99 .absSeg475\r
+.abs_section_9a 2 N/I 0x9A 0x9B .absSeg476\r
+.abs_section_9c 2 N/I 0x9C 0x9D .absSeg477\r
+.abs_section_9e 2 N/I 0x9E 0x9F .absSeg478\r
+.abs_section_122 2 N/I 0x122 0x123 .absSeg479\r
+.abs_section_124 2 N/I 0x124 0x125 .absSeg480\r
+.abs_section_130 2 N/I 0x130 0x131 .absSeg481\r
+.abs_section_132 2 N/I 0x132 0x133 .absSeg482\r
+.abs_section_134 2 N/I 0x134 0x135 .absSeg483\r
+.abs_section_136 2 N/I 0x136 0x137 .absSeg484\r
+.abs_section_138 2 N/I 0x138 0x139 .absSeg485\r
+.abs_section_13a 2 N/I 0x13A 0x13B .absSeg486\r
+.abs_section_13c 2 N/I 0x13C 0x13D .absSeg487\r
+.abs_section_13e 2 N/I 0x13E 0x13F .absSeg488\r
+.abs_section_2 2 N/I 0x2 0x3 .absSeg489\r
+.abs_section_76 2 N/I 0x76 0x77 .absSeg490\r
+.abs_section_74 2 N/I 0x74 0x75 .absSeg491\r
+.abs_section_72 2 N/I 0x72 0x73 .absSeg492\r
+.abs_section_64 2 N/I 0x64 0x65 .absSeg493\r
+.abs_section_62 2 N/I 0x62 0x63 .absSeg494\r
+.abs_section_0 2 N/I 0x0 0x1 .absSeg495\r
+.abs_section_ac 2 N/I 0xAC 0xAD .absSeg496\r
+.abs_section_ae 2 N/I 0xAE 0xAF .absSeg497\r
+.abs_section_b0 2 N/I 0xB0 0xB1 .absSeg498\r
+.abs_section_b2 2 N/I 0xB2 0xB3 .absSeg499\r
+.abs_section_bc 2 N/I 0xBC 0xBD .absSeg500\r
+.abs_section_be 2 N/I 0xBE 0xBF .absSeg501\r
+.abs_section_c0 2 N/I 0xC0 0xC1 .absSeg502\r
+.abs_section_c2 2 N/I 0xC2 0xC3 .absSeg503\r
+.abs_section_b4 2 N/I 0xB4 0xB5 .absSeg504\r
+.abs_section_b6 2 N/I 0xB6 0xB7 .absSeg505\r
+.abs_section_b8 2 N/I 0xB8 0xB9 .absSeg506\r
+.abs_section_ba 2 N/I 0xBA 0xBB .absSeg507\r
+.abs_section_c8 2 N/I 0xC8 0xC9 .absSeg508\r
+.abs_section_d0 2 N/I 0xD0 0xD1 .absSeg509\r
+.abs_section_50 2 N/I 0x50 0x51 .absSeg510\r
+.abs_section_78 2 N/I 0x78 0x79 .absSeg511\r
+.abs_section_52 2 N/I 0x52 0x53 .absSeg512\r
+.abs_section_7a 2 N/I 0x7A 0x7B .absSeg513\r
+.abs_section_54 2 N/I 0x54 0x55 .absSeg514\r
+.abs_section_7c 2 N/I 0x7C 0x7D .absSeg515\r
+.abs_section_56 2 N/I 0x56 0x57 .absSeg516\r
+.abs_section_7e 2 N/I 0x7E 0x7F .absSeg517\r
+.abs_section_58 2 N/I 0x58 0x59 .absSeg518\r
+.abs_section_5a 2 N/I 0x5A 0x5B .absSeg519\r
+.abs_section_5c 2 N/I 0x5C 0x5D .absSeg520\r
+.abs_section_5e 2 N/I 0x5E 0x5F .absSeg521\r
+.abs_section_44 2 N/I 0x44 0x45 .absSeg522\r
+.abs_section_ff80 128 R 0xFF80 0xFFFF .absSeg523\r
+.bss 10475 R/W 0x1001 0x38EB RAM\r
+.common 6 R/W 0x38EC 0x38F1 RAM\r
+TickTimer_CODE 123 R 0x3B8124 0x3B819E ROM_PAGE3B\r
+Byte1_CODE 53 R 0x3B819F 0x3B81D3 ROM_PAGE3B\r
+COM0_CODE 62 R 0x3B81D4 0x3B8211 ROM_PAGE3B\r
+TickTimer_DATA 2 R/W 0x38F2 0x38F3 RAM\r
+Byte1_DATA 8 R/W 0x38F4 0x38FB RAM\r
+COM0_DATA 13 R/W 0x38FC 0x3908 RAM\r
+.stack 128 R/W 0x3909 0x3988 RAM\r
+ROM_PAGE31_524 553 R 0x318000 0x318228 ROM_PAGE31\r
+ROM_PAGE32_525 541 R 0x328000 0x32821C ROM_PAGE32\r
+ROM_PAGE33_526 548 R 0x338000 0x338223 ROM_PAGE33\r
+ROM_PAGE34_527 587 R 0x348000 0x34824A ROM_PAGE34\r
+ROM_PAGE35_528 591 R 0x358000 0x35824E ROM_PAGE35\r
+ROM_PAGE36_529 509 R 0x368000 0x3681FC ROM_PAGE36\r
+ROM_PAGE37_530 593 R 0x378000 0x378250 ROM_PAGE37\r
+ROM_PAGE38_531 498 R 0x388000 0x3881F1 ROM_PAGE38\r
+ROM_PAGE39_532 407 R 0x398000 0x398196 ROM_PAGE39\r
+ROM_PAGE3A_533 588 R 0x3A8000 0x3A824B ROM_PAGE3A\r
+ROM_PAGE3B_534 292 R 0x3B8000 0x3B8123 ROM_PAGE3B\r
+\r
+Summary of section sizes per section type:\r
+READ_ONLY (R): 1DD4 (dec: 7636)\r
+READ_WRITE (R/W): 2989 (dec: 10633)\r
+NO_INIT (N/I): 241 (dec: 577)\r
+\r
+*********************************************************************************************\r
+VECTOR-ALLOCATION SECTION\r
+ Address InitValue InitFunction\r
+---------------------------------------------------------------------------------------------\r
+\r
+*********************************************************************************************\r
+OBJECT-ALLOCATION SECTION\r
+ Name Module Addr hSize dSize Ref Section RLIB\r
+---------------------------------------------------------------------------------------------\r
+MODULE: -- Start12.c.o --\r
+- PROCEDURES:\r
+ Init 308000 29 41 2 .text \r
+ _Startup C151 12 18 1 NON_BANKED \r
+- VARIABLES:\r
+ _startupData C07C 18 24 6 .startData \r
+MODULE: -- STRING.C.o (ansibi.lib) --\r
+- PROCEDURES:\r
+ memcpy 308029 26 38 8 .text \r
+ memset 30804F 1E 30 2 .text \r
+ strncpy 30806D 2D 45 2 .text \r
+- VARIABLES:\r
+MODULE: -- rtshc12.c.o (ansibi.lib) --\r
+- PROCEDURES:\r
+ _LCMP C163 19 25 2 NON_BANKED \r
+ _LCMP_P C17C 15 21 3 NON_BANKED \r
+ _LNEG C191 D 13 2 NON_BANKED \r
+ _LINC C19E 5 5 4 NON_BANKED \r
+ _LMUL C1A3 27 39 1 NON_BANKED \r
+ _lDivMod C1CA E3 227 3 NON_BANKED \r
+ _LDIVU C2AD E 14 1 NON_BANKED \r
+ _NEG_P C2BB F 15 4 NON_BANKED \r
+ _LDIVS C2CA 35 53 2 NON_BANKED \r
+- VARIABLES:\r
+MODULE: -- Cpu.C.o --\r
+- PROCEDURES:\r
+ _EntryPoint C000 2E 46 1 .init \r
+ PE_low_level_init C02E 4E 78 2 .init \r
+ Cpu_Interrupt C2FF 1 1 60 NON_BANKED \r
+- VARIABLES:\r
+MODULE: -- IO_Map.C.o --\r
+- PROCEDURES:\r
+- VARIABLES:\r
+ _ARMCOP 3F 1 1 0 .abs_section_3f\r
+ _ATD0DIEN 8D 1 1 0 .abs_section_8d\r
+ _ATD0STAT0 86 1 1 0 .abs_section_86\r
+ _ATD0STAT1 8B 1 1 0 .abs_section_8b\r
+ _ATD1DIEN 12D 1 1 0 .abs_section_12d\r
+ _ATD1STAT0 126 1 1 0 .abs_section_126\r
+ _ATD1STAT1 12B 1 1 0 .abs_section_12b\r
+ _BDMCCR FF06 1 1 0 .abs_section_ff06\r
+ _BDMINR FF07 1 1 0 .abs_section_ff07\r
+ _BDMSTS FF01 1 1 0 .abs_section_ff01\r
+ _BKP0H 2B 1 1 0 .abs_section_2b\r
+ _BKP0L 2C 1 1 0 .abs_section_2c\r
+ _BKP0X 2A 1 1 0 .abs_section_2a\r
+ _BKP1H 2E 1 1 0 .abs_section_2e\r
+ _BKP1L 2F 1 1 0 .abs_section_2f\r
+ _BKP1X 2D 1 1 0 .abs_section_2d\r
+ _BKPCT0 28 1 1 0 .abs_section_28\r
+ _BKPCT1 29 1 1 0 .abs_section_29\r
+ _CAN0BTR0 142 1 1 0 .abs_section_142\r
+ _CAN0BTR1 143 1 1 0 .abs_section_143\r
+ _CAN0CTL0 140 1 1 0 .abs_section_140\r
+ _CAN0CTL1 141 1 1 0 .abs_section_141\r
+ _CAN0IDAC 14B 1 1 0 .abs_section_14b\r
+ _CAN0IDAR0 150 1 1 0 .abs_section_150\r
+ _CAN0IDAR1 151 1 1 0 .abs_section_151\r
+ _CAN0IDAR2 152 1 1 0 .abs_section_152\r
+ _CAN0IDAR3 153 1 1 0 .abs_section_153\r
+ _CAN0IDAR4 158 1 1 0 .abs_section_158\r
+ _CAN0IDAR5 159 1 1 0 .abs_section_159\r
+ _CAN0IDAR6 15A 1 1 0 .abs_section_15a\r
+ _CAN0IDAR7 15B 1 1 0 .abs_section_15b\r
+ _CAN0IDMR0 154 1 1 0 .abs_section_154\r
+ _CAN0IDMR1 155 1 1 0 .abs_section_155\r
+ _CAN0IDMR2 156 1 1 0 .abs_section_156\r
+ _CAN0IDMR3 157 1 1 0 .abs_section_157\r
+ _CAN0IDMR4 15C 1 1 0 .abs_section_15c\r
+ _CAN0IDMR5 15D 1 1 0 .abs_section_15d\r
+ _CAN0IDMR6 15E 1 1 0 .abs_section_15e\r
+ _CAN0IDMR7 15F 1 1 0 .abs_section_15f\r
+ _CAN0RFLG 144 1 1 0 .abs_section_144\r
+ _CAN0RIER 145 1 1 0 .abs_section_145\r
+ _CAN0RXDLR 16C 1 1 0 .abs_section_16c\r
+ _CAN0RXDSR0 164 1 1 0 .abs_section_164\r
+ _CAN0RXDSR1 165 1 1 0 .abs_section_165\r
+ _CAN0RXDSR2 166 1 1 0 .abs_section_166\r
+ _CAN0RXDSR3 167 1 1 0 .abs_section_167\r
+ _CAN0RXDSR4 168 1 1 0 .abs_section_168\r
+ _CAN0RXDSR5 169 1 1 0 .abs_section_169\r
+ _CAN0RXDSR6 16A 1 1 0 .abs_section_16a\r
+ _CAN0RXDSR7 16B 1 1 0 .abs_section_16b\r
+ _CAN0RXERR 14E 1 1 0 .abs_section_14e\r
+ _CAN0RXIDR0 160 1 1 0 .abs_section_160\r
+ _CAN0RXIDR1 161 1 1 0 .abs_section_161\r
+ _CAN0RXIDR2 162 1 1 0 .abs_section_162\r
+ _CAN0RXIDR3 163 1 1 0 .abs_section_163\r
+ _CAN0TAAK 149 1 1 0 .abs_section_149\r
+ _CAN0TARQ 148 1 1 0 .abs_section_148\r
+ _CAN0TBSEL 14A 1 1 0 .abs_section_14a\r
+ _CAN0TFLG 146 1 1 0 .abs_section_146\r
+ _CAN0TIER 147 1 1 0 .abs_section_147\r
+ _CAN0TXDLR 17C 1 1 0 .abs_section_17c\r
+ _CAN0TXDSR0 174 1 1 0 .abs_section_174\r
+ _CAN0TXDSR1 175 1 1 0 .abs_section_175\r
+ _CAN0TXDSR2 176 1 1 0 .abs_section_176\r
+ _CAN0TXDSR3 177 1 1 0 .abs_section_177\r
+ _CAN0TXDSR4 178 1 1 0 .abs_section_178\r
+ _CAN0TXDSR5 179 1 1 0 .abs_section_179\r
+ _CAN0TXDSR6 17A 1 1 0 .abs_section_17a\r
+ _CAN0TXDSR7 17B 1 1 0 .abs_section_17b\r
+ _CAN0TXERR 14F 1 1 0 .abs_section_14f\r
+ _CAN0TXIDR0 170 1 1 0 .abs_section_170\r
+ _CAN0TXIDR1 171 1 1 0 .abs_section_171\r
+ _CAN0TXIDR2 172 1 1 0 .abs_section_172\r
+ _CAN0TXIDR3 173 1 1 0 .abs_section_173\r
+ _CAN0TXTBPR 17F 1 1 0 .abs_section_17f\r
+ _CAN1BTR0 182 1 1 0 .abs_section_182\r
+ _CAN1BTR1 183 1 1 0 .abs_section_183\r
+ _CAN1CTL0 180 1 1 0 .abs_section_180\r
+ _CAN1CTL1 181 1 1 0 .abs_section_181\r
+ _CAN1IDAC 18B 1 1 0 .abs_section_18b\r
+ _CAN1IDAR0 190 1 1 0 .abs_section_190\r
+ _CAN1IDAR1 191 1 1 0 .abs_section_191\r
+ _CAN1IDAR2 192 1 1 0 .abs_section_192\r
+ _CAN1IDAR3 193 1 1 0 .abs_section_193\r
+ _CAN1IDAR4 198 1 1 0 .abs_section_198\r
+ _CAN1IDAR5 199 1 1 0 .abs_section_199\r
+ _CAN1IDAR6 19A 1 1 0 .abs_section_19a\r
+ _CAN1IDAR7 19B 1 1 0 .abs_section_19b\r
+ _CAN1IDMR0 194 1 1 0 .abs_section_194\r
+ _CAN1IDMR1 195 1 1 0 .abs_section_195\r
+ _CAN1IDMR2 196 1 1 0 .abs_section_196\r
+ _CAN1IDMR3 197 1 1 0 .abs_section_197\r
+ _CAN1IDMR4 19C 1 1 0 .abs_section_19c\r
+ _CAN1IDMR5 19D 1 1 0 .abs_section_19d\r
+ _CAN1IDMR6 19E 1 1 0 .abs_section_19e\r
+ _CAN1IDMR7 19F 1 1 0 .abs_section_19f\r
+ _CAN1RFLG 184 1 1 0 .abs_section_184\r
+ _CAN1RIER 185 1 1 0 .abs_section_185\r
+ _CAN1RXDLR 1AC 1 1 0 .abs_section_1ac\r
+ _CAN1RXDSR0 1A4 1 1 0 .abs_section_1a4\r
+ _CAN1RXDSR1 1A5 1 1 0 .abs_section_1a5\r
+ _CAN1RXDSR2 1A6 1 1 0 .abs_section_1a6\r
+ _CAN1RXDSR3 1A7 1 1 0 .abs_section_1a7\r
+ _CAN1RXDSR4 1A8 1 1 0 .abs_section_1a8\r
+ _CAN1RXDSR5 1A9 1 1 0 .abs_section_1a9\r
+ _CAN1RXDSR6 1AA 1 1 0 .abs_section_1aa\r
+ _CAN1RXDSR7 1AB 1 1 0 .abs_section_1ab\r
+ _CAN1RXERR 18E 1 1 0 .abs_section_18e\r
+ _CAN1RXIDR0 1A0 1 1 0 .abs_section_1a0\r
+ _CAN1RXIDR1 1A1 1 1 0 .abs_section_1a1\r
+ _CAN1RXIDR2 1A2 1 1 0 .abs_section_1a2\r
+ _CAN1RXIDR3 1A3 1 1 0 .abs_section_1a3\r
+ _CAN1TAAK 189 1 1 0 .abs_section_189\r
+ _CAN1TARQ 188 1 1 0 .abs_section_188\r
+ _CAN1TBSEL 18A 1 1 0 .abs_section_18a\r
+ _CAN1TFLG 186 1 1 0 .abs_section_186\r
+ _CAN1TIER 187 1 1 0 .abs_section_187\r
+ _CAN1TXDLR 1BC 1 1 0 .abs_section_1bc\r
+ _CAN1TXDSR0 1B4 1 1 0 .abs_section_1b4\r
+ _CAN1TXDSR1 1B5 1 1 0 .abs_section_1b5\r
+ _CAN1TXDSR2 1B6 1 1 0 .abs_section_1b6\r
+ _CAN1TXDSR3 1B7 1 1 0 .abs_section_1b7\r
+ _CAN1TXDSR4 1B8 1 1 0 .abs_section_1b8\r
+ _CAN1TXDSR5 1B9 1 1 0 .abs_section_1b9\r
+ _CAN1TXDSR6 1BA 1 1 0 .abs_section_1ba\r
+ _CAN1TXDSR7 1BB 1 1 0 .abs_section_1bb\r
+ _CAN1TXERR 18F 1 1 0 .abs_section_18f\r
+ _CAN1TXIDR0 1B0 1 1 0 .abs_section_1b0\r
+ _CAN1TXIDR1 1B1 1 1 0 .abs_section_1b1\r
+ _CAN1TXIDR2 1B2 1 1 0 .abs_section_1b2\r
+ _CAN1TXIDR3 1B3 1 1 0 .abs_section_1b3\r
+ _CAN1TXTBPR 1BF 1 1 0 .abs_section_1bf\r
+ _CAN2BTR0 1C2 1 1 0 .abs_section_1c2\r
+ _CAN2BTR1 1C3 1 1 0 .abs_section_1c3\r
+ _CAN2CTL0 1C0 1 1 0 .abs_section_1c0\r
+ _CAN2CTL1 1C1 1 1 0 .abs_section_1c1\r
+ _CAN2IDAC 1CB 1 1 0 .abs_section_1cb\r
+ _CAN2IDAR0 1D0 1 1 0 .abs_section_1d0\r
+ _CAN2IDAR1 1D1 1 1 0 .abs_section_1d1\r
+ _CAN2IDAR2 1D2 1 1 0 .abs_section_1d2\r
+ _CAN2IDAR3 1D3 1 1 0 .abs_section_1d3\r
+ _CAN2IDAR4 1D8 1 1 0 .abs_section_1d8\r
+ _CAN2IDAR5 1D9 1 1 0 .abs_section_1d9\r
+ _CAN2IDAR6 1DA 1 1 0 .abs_section_1da\r
+ _CAN2IDAR7 1DB 1 1 0 .abs_section_1db\r
+ _CAN2IDMR0 1D4 1 1 0 .abs_section_1d4\r
+ _CAN2IDMR1 1D5 1 1 0 .abs_section_1d5\r
+ _CAN2IDMR2 1D6 1 1 0 .abs_section_1d6\r
+ _CAN2IDMR3 1D7 1 1 0 .abs_section_1d7\r
+ _CAN2IDMR4 1DC 1 1 0 .abs_section_1dc\r
+ _CAN2IDMR5 1DD 1 1 0 .abs_section_1dd\r
+ _CAN2IDMR6 1DE 1 1 0 .abs_section_1de\r
+ _CAN2IDMR7 1DF 1 1 0 .abs_section_1df\r
+ _CAN2RFLG 1C4 1 1 0 .abs_section_1c4\r
+ _CAN2RIER 1C5 1 1 0 .abs_section_1c5\r
+ _CAN2RXDLR 1EC 1 1 0 .abs_section_1ec\r
+ _CAN2RXDSR0 1E4 1 1 0 .abs_section_1e4\r
+ _CAN2RXDSR1 1E5 1 1 0 .abs_section_1e5\r
+ _CAN2RXDSR2 1E6 1 1 0 .abs_section_1e6\r
+ _CAN2RXDSR3 1E7 1 1 0 .abs_section_1e7\r
+ _CAN2RXDSR4 1E8 1 1 0 .abs_section_1e8\r
+ _CAN2RXDSR5 1E9 1 1 0 .abs_section_1e9\r
+ _CAN2RXDSR6 1EA 1 1 0 .abs_section_1ea\r
+ _CAN2RXDSR7 1EB 1 1 0 .abs_section_1eb\r
+ _CAN2RXERR 1CE 1 1 0 .abs_section_1ce\r
+ _CAN2RXIDR0 1E0 1 1 0 .abs_section_1e0\r
+ _CAN2RXIDR1 1E1 1 1 0 .abs_section_1e1\r
+ _CAN2RXIDR2 1E2 1 1 0 .abs_section_1e2\r
+ _CAN2RXIDR3 1E3 1 1 0 .abs_section_1e3\r
+ _CAN2TAAK 1C9 1 1 0 .abs_section_1c9\r
+ _CAN2TARQ 1C8 1 1 0 .abs_section_1c8\r
+ _CAN2TBSEL 1CA 1 1 0 .abs_section_1ca\r
+ _CAN2TFLG 1C6 1 1 0 .abs_section_1c6\r
+ _CAN2TIER 1C7 1 1 0 .abs_section_1c7\r
+ _CAN2TXDLR 1FC 1 1 0 .abs_section_1fc\r
+ _CAN2TXDSR0 1F4 1 1 0 .abs_section_1f4\r
+ _CAN2TXDSR1 1F5 1 1 0 .abs_section_1f5\r
+ _CAN2TXDSR2 1F6 1 1 0 .abs_section_1f6\r
+ _CAN2TXDSR3 1F7 1 1 0 .abs_section_1f7\r
+ _CAN2TXDSR4 1F8 1 1 0 .abs_section_1f8\r
+ _CAN2TXDSR5 1F9 1 1 0 .abs_section_1f9\r
+ _CAN2TXDSR6 1FA 1 1 0 .abs_section_1fa\r
+ _CAN2TXDSR7 1FB 1 1 0 .abs_section_1fb\r
+ _CAN2TXERR 1CF 1 1 0 .abs_section_1cf\r
+ _CAN2TXIDR0 1F0 1 1 0 .abs_section_1f0\r
+ _CAN2TXIDR1 1F1 1 1 0 .abs_section_1f1\r
+ _CAN2TXIDR2 1F2 1 1 0 .abs_section_1f2\r
+ _CAN2TXIDR3 1F3 1 1 0 .abs_section_1f3\r
+ _CAN2TXTBPR 1FF 1 1 0 .abs_section_1ff\r
+ _CAN3BTR0 202 1 1 0 .abs_section_202\r
+ _CAN3BTR1 203 1 1 0 .abs_section_203\r
+ _CAN3CTL0 200 1 1 0 .abs_section_200\r
+ _CAN3CTL1 201 1 1 0 .abs_section_201\r
+ _CAN3IDAC 20B 1 1 0 .abs_section_20b\r
+ _CAN3IDAR0 210 1 1 0 .abs_section_210\r
+ _CAN3IDAR1 211 1 1 0 .abs_section_211\r
+ _CAN3IDAR2 212 1 1 0 .abs_section_212\r
+ _CAN3IDAR3 213 1 1 0 .abs_section_213\r
+ _CAN3IDAR4 218 1 1 0 .abs_section_218\r
+ _CAN3IDAR5 219 1 1 0 .abs_section_219\r
+ _CAN3IDAR6 21A 1 1 0 .abs_section_21a\r
+ _CAN3IDAR7 21B 1 1 0 .abs_section_21b\r
+ _CAN3IDMR0 214 1 1 0 .abs_section_214\r
+ _CAN3IDMR1 215 1 1 0 .abs_section_215\r
+ _CAN3IDMR2 216 1 1 0 .abs_section_216\r
+ _CAN3IDMR3 217 1 1 0 .abs_section_217\r
+ _CAN3IDMR4 21C 1 1 0 .abs_section_21c\r
+ _CAN3IDMR5 21D 1 1 0 .abs_section_21d\r
+ _CAN3IDMR6 21E 1 1 0 .abs_section_21e\r
+ _CAN3IDMR7 21F 1 1 0 .abs_section_21f\r
+ _CAN3RFLG 204 1 1 0 .abs_section_204\r
+ _CAN3RIER 205 1 1 0 .abs_section_205\r
+ _CAN3RXDLR 22C 1 1 0 .abs_section_22c\r
+ _CAN3RXDSR0 224 1 1 0 .abs_section_224\r
+ _CAN3RXDSR1 225 1 1 0 .abs_section_225\r
+ _CAN3RXDSR2 226 1 1 0 .abs_section_226\r
+ _CAN3RXDSR3 227 1 1 0 .abs_section_227\r
+ _CAN3RXDSR4 228 1 1 0 .abs_section_228\r
+ _CAN3RXDSR5 229 1 1 0 .abs_section_229\r
+ _CAN3RXDSR6 22A 1 1 0 .abs_section_22a\r
+ _CAN3RXDSR7 22B 1 1 0 .abs_section_22b\r
+ _CAN3RXERR 20E 1 1 0 .abs_section_20e\r
+ _CAN3RXIDR0 220 1 1 0 .abs_section_220\r
+ _CAN3RXIDR1 221 1 1 0 .abs_section_221\r
+ _CAN3RXIDR2 222 1 1 0 .abs_section_222\r
+ _CAN3RXIDR3 223 1 1 0 .abs_section_223\r
+ _CAN3TAAK 209 1 1 0 .abs_section_209\r
+ _CAN3TARQ 208 1 1 0 .abs_section_208\r
+ _CAN3TBSEL 20A 1 1 0 .abs_section_20a\r
+ _CAN3TFLG 206 1 1 0 .abs_section_206\r
+ _CAN3TIER 207 1 1 0 .abs_section_207\r
+ _CAN3TXDLR 23C 1 1 0 .abs_section_23c\r
+ _CAN3TXDSR0 234 1 1 0 .abs_section_234\r
+ _CAN3TXDSR1 235 1 1 0 .abs_section_235\r
+ _CAN3TXDSR2 236 1 1 0 .abs_section_236\r
+ _CAN3TXDSR3 237 1 1 0 .abs_section_237\r
+ _CAN3TXDSR4 238 1 1 0 .abs_section_238\r
+ _CAN3TXDSR5 239 1 1 0 .abs_section_239\r
+ _CAN3TXDSR6 23A 1 1 0 .abs_section_23a\r
+ _CAN3TXDSR7 23B 1 1 0 .abs_section_23b\r
+ _CAN3TXERR 20F 1 1 0 .abs_section_20f\r
+ _CAN3TXIDR0 230 1 1 0 .abs_section_230\r
+ _CAN3TXIDR1 231 1 1 0 .abs_section_231\r
+ _CAN3TXIDR2 232 1 1 0 .abs_section_232\r
+ _CAN3TXIDR3 233 1 1 0 .abs_section_233\r
+ _CAN3TXTBPR 23F 1 1 0 .abs_section_23f\r
+ _CAN4BTR0 282 1 1 0 .abs_section_282\r
+ _CAN4BTR1 283 1 1 0 .abs_section_283\r
+ _CAN4CTL0 280 1 1 0 .abs_section_280\r
+ _CAN4CTL1 281 1 1 0 .abs_section_281\r
+ _CAN4IDAC 28B 1 1 0 .abs_section_28b\r
+ _CAN4IDAR0 290 1 1 0 .abs_section_290\r
+ _CAN4IDAR1 291 1 1 0 .abs_section_291\r
+ _CAN4IDAR2 292 1 1 0 .abs_section_292\r
+ _CAN4IDAR3 293 1 1 0 .abs_section_293\r
+ _CAN4IDAR4 298 1 1 0 .abs_section_298\r
+ _CAN4IDAR5 299 1 1 0 .abs_section_299\r
+ _CAN4IDAR6 29A 1 1 0 .abs_section_29a\r
+ _CAN4IDAR7 29B 1 1 0 .abs_section_29b\r
+ _CAN4IDMR0 294 1 1 0 .abs_section_294\r
+ _CAN4IDMR1 295 1 1 0 .abs_section_295\r
+ _CAN4IDMR2 296 1 1 0 .abs_section_296\r
+ _CAN4IDMR3 297 1 1 0 .abs_section_297\r
+ _CAN4IDMR4 29C 1 1 0 .abs_section_29c\r
+ _CAN4IDMR5 29D 1 1 0 .abs_section_29d\r
+ _CAN4IDMR6 29E 1 1 0 .abs_section_29e\r
+ _CAN4IDMR7 29F 1 1 0 .abs_section_29f\r
+ _CAN4RFLG 284 1 1 0 .abs_section_284\r
+ _CAN4RIER 285 1 1 0 .abs_section_285\r
+ _CAN4RXDLR 2AC 1 1 0 .abs_section_2ac\r
+ _CAN4RXDSR0 2A4 1 1 0 .abs_section_2a4\r
+ _CAN4RXDSR1 2A5 1 1 0 .abs_section_2a5\r
+ _CAN4RXDSR2 2A6 1 1 0 .abs_section_2a6\r
+ _CAN4RXDSR3 2A7 1 1 0 .abs_section_2a7\r
+ _CAN4RXDSR4 2A8 1 1 0 .abs_section_2a8\r
+ _CAN4RXDSR5 2A9 1 1 0 .abs_section_2a9\r
+ _CAN4RXDSR6 2AA 1 1 0 .abs_section_2aa\r
+ _CAN4RXDSR7 2AB 1 1 0 .abs_section_2ab\r
+ _CAN4RXERR 28E 1 1 0 .abs_section_28e\r
+ _CAN4RXIDR0 2A0 1 1 0 .abs_section_2a0\r
+ _CAN4RXIDR1 2A1 1 1 0 .abs_section_2a1\r
+ _CAN4RXIDR2 2A2 1 1 0 .abs_section_2a2\r
+ _CAN4RXIDR3 2A3 1 1 0 .abs_section_2a3\r
+ _CAN4TAAK 289 1 1 0 .abs_section_289\r
+ _CAN4TARQ 288 1 1 0 .abs_section_288\r
+ _CAN4TBSEL 28A 1 1 0 .abs_section_28a\r
+ _CAN4TFLG 286 1 1 0 .abs_section_286\r
+ _CAN4TIER 287 1 1 0 .abs_section_287\r
+ _CAN4TXDLR 2BC 1 1 0 .abs_section_2bc\r
+ _CAN4TXDSR0 2B4 1 1 0 .abs_section_2b4\r
+ _CAN4TXDSR1 2B5 1 1 0 .abs_section_2b5\r
+ _CAN4TXDSR2 2B6 1 1 0 .abs_section_2b6\r
+ _CAN4TXDSR3 2B7 1 1 0 .abs_section_2b7\r
+ _CAN4TXDSR4 2B8 1 1 0 .abs_section_2b8\r
+ _CAN4TXDSR5 2B9 1 1 0 .abs_section_2b9\r
+ _CAN4TXDSR6 2BA 1 1 0 .abs_section_2ba\r
+ _CAN4TXDSR7 2BB 1 1 0 .abs_section_2bb\r
+ _CAN4TXERR 28F 1 1 0 .abs_section_28f\r
+ _CAN4TXIDR0 2B0 1 1 0 .abs_section_2b0\r
+ _CAN4TXIDR1 2B1 1 1 0 .abs_section_2b1\r
+ _CAN4TXIDR2 2B2 1 1 0 .abs_section_2b2\r
+ _CAN4TXIDR3 2B3 1 1 0 .abs_section_2b3\r
+ _CAN4TXTBPR 2BF 1 1 0 .abs_section_2bf\r
+ _CFORC 41 1 1 0 .abs_section_41\r
+ _CLKSEL 39 1 1 3 .abs_section_39\r
+ _COPCTL 3C 1 1 0 .abs_section_3c\r
+ _CRGFLG 37 1 1 1 .abs_section_37\r
+ _CRGINT 38 1 1 0 .abs_section_38\r
+ _CTCTL 3E 1 1 0 .abs_section_3e\r
+ _CTFLG 36 1 1 0 .abs_section_36\r
+ _DDRE 9 1 1 0 .abs_section_9\r
+ _DDRH 262 1 1 0 .abs_section_262\r
+ _DDRJ 26A 1 1 0 .abs_section_26a\r
+ _DDRK 33 1 1 0 .abs_section_33\r
+ _DDRM 252 1 1 0 .abs_section_252\r
+ _DDRP 25A 1 1 0 .abs_section_25a\r
+ _DDRS 24A 1 1 2 .abs_section_24a\r
+ _DDRT 242 1 1 0 .abs_section_242\r
+ _DLCBARD EC 1 1 0 .abs_section_ec\r
+ _DLCBCR1 E8 1 1 0 .abs_section_e8\r
+ _DLCBCR2 EA 1 1 0 .abs_section_ea\r
+ _DLCBDR EB 1 1 0 .abs_section_eb\r
+ _DLCBRSR ED 1 1 0 .abs_section_ed\r
+ _DLCBSVR E9 1 1 0 .abs_section_e9\r
+ _DLCSCR EE 1 1 0 .abs_section_ee\r
+ _DLYCT 69 1 1 0 .abs_section_69\r
+ _EBICTL E 1 1 0 .abs_section_e\r
+ _ECLKDIV 110 1 1 0 .abs_section_110\r
+ _ECMD 116 1 1 0 .abs_section_116\r
+ _ECNFG 113 1 1 0 .abs_section_113\r
+ _EPROT 114 1 1 0 .abs_section_114\r
+ _ESTAT 115 1 1 0 .abs_section_115\r
+ _FCLKDIV 100 1 1 0 .abs_section_100\r
+ _FCMD 106 1 1 0 .abs_section_106\r
+ _FCNFG 103 1 1 0 .abs_section_103\r
+ _FORBYP 3D 1 1 0 .abs_section_3d\r
+ _FPROT 104 1 1 0 .abs_section_104\r
+ _FSEC 101 1 1 0 .abs_section_101\r
+ _FSTAT 105 1 1 0 .abs_section_105\r
+ _HPRIO 1F 1 1 0 .abs_section_1f\r
+ _IBAD E0 1 1 0 .abs_section_e0\r
+ _IBCR E2 1 1 0 .abs_section_e2\r
+ _IBDR E4 1 1 0 .abs_section_e4\r
+ _IBFD E1 1 1 0 .abs_section_e1\r
+ _IBSR E3 1 1 0 .abs_section_e3\r
+ _ICOVW 6A 1 1 0 .abs_section_6a\r
+ _ICPAR 68 1 1 0 .abs_section_68\r
+ _ICSYS 6B 1 1 1 .abs_section_6b\r
+ _INITEE 12 1 1 1 .abs_section_12\r
+ _INITRG 11 1 1 0 .abs_section_11\r
+ _INITRM 10 1 1 1 .abs_section_10\r
+ _INTCR 1E 1 1 1 .abs_section_1e\r
+ _ITCR 15 1 1 0 .abs_section_15\r
+ _ITEST 16 1 1 0 .abs_section_16\r
+ _MCCTL 66 1 1 1 .abs_section_66\r
+ _MCFLG 67 1 1 0 .abs_section_67\r
+ _MEMSIZ0 1C 1 1 0 .abs_section_1c\r
+ _MEMSIZ1 1D 1 1 0 .abs_section_1d\r
+ _MISC 13 1 1 1 .abs_section_13\r
+ _MODE B 1 1 0 .abs_section_b\r
+ _MODRR 257 1 1 0 .abs_section_257\r
+ _MTST0 14 1 1 0 .abs_section_14\r
+ _MTST1 17 1 1 0 .abs_section_17\r
+ _OC7D 43 1 1 0 .abs_section_43\r
+ _OC7M 42 1 1 0 .abs_section_42\r
+ _PACTL 60 1 1 0 .abs_section_60\r
+ _PAFLG 61 1 1 0 .abs_section_61\r
+ _PARTIDH 1A 1 1 0 .abs_section_1a\r
+ _PARTIDL 1B 1 1 0 .abs_section_1b\r
+ _PBCTL 70 1 1 0 .abs_section_70\r
+ _PBFLG 71 1 1 0 .abs_section_71\r
+ _PEAR A 1 1 0 .abs_section_a\r
+ _PERH 264 1 1 0 .abs_section_264\r
+ _PERJ 26C 1 1 0 .abs_section_26c\r
+ _PERM 254 1 1 0 .abs_section_254\r
+ _PERP 25C 1 1 0 .abs_section_25c\r
+ _PERS 24C 1 1 0 .abs_section_24c\r
+ _PERT 244 1 1 0 .abs_section_244\r
+ _PIEH 266 1 1 0 .abs_section_266\r
+ _PIEJ 26E 1 1 0 .abs_section_26e\r
+ _PIEP 25E 1 1 0 .abs_section_25e\r
+ _PIFH 267 1 1 0 .abs_section_267\r
+ _PIFJ 26F 1 1 0 .abs_section_26f\r
+ _PIFP 25F 1 1 0 .abs_section_25f\r
+ _PLLCTL 3A 1 1 3 .abs_section_3a\r
+ _PORTAD0 8F 1 1 0 .abs_section_8f\r
+ _PORTAD1 12F 1 1 0 .abs_section_12f\r
+ _PORTE 8 1 1 0 .abs_section_8\r
+ _PORTK 32 1 1 0 .abs_section_32\r
+ _PPAGE 30 1 1 0 .abs_section_30\r
+ _PPSH 265 1 1 0 .abs_section_265\r
+ _PPSJ 26D 1 1 0 .abs_section_26d\r
+ _PPSM 255 1 1 0 .abs_section_255\r
+ _PPSP 25D 1 1 0 .abs_section_25d\r
+ _PPSS 24D 1 1 0 .abs_section_24d\r
+ _PPST 245 1 1 0 .abs_section_245\r
+ _PTH 260 1 1 0 .abs_section_260\r
+ _PTIH 261 1 1 0 .abs_section_261\r
+ _PTIJ 269 1 1 0 .abs_section_269\r
+ _PTIM 251 1 1 0 .abs_section_251\r
+ _PTIP 259 1 1 0 .abs_section_259\r
+ _PTIS 249 1 1 0 .abs_section_249\r
+ _PTIT 241 1 1 0 .abs_section_241\r
+ _PTJ 268 1 1 0 .abs_section_268\r
+ _PTM 250 1 1 0 .abs_section_250\r
+ _PTP 258 1 1 0 .abs_section_258\r
+ _PTS 248 1 1 1 .abs_section_248\r
+ _PTT 240 1 1 0 .abs_section_240\r
+ _PUCR C 1 1 0 .abs_section_c\r
+ _PWMCAE A4 1 1 0 .abs_section_a4\r
+ _PWMCLK A2 1 1 0 .abs_section_a2\r
+ _PWMCTL A5 1 1 1 .abs_section_a5\r
+ _PWME A0 1 1 0 .abs_section_a0\r
+ _PWMPOL A1 1 1 0 .abs_section_a1\r
+ _PWMPRCLK A3 1 1 0 .abs_section_a3\r
+ _PWMSCLA A8 1 1 0 .abs_section_a8\r
+ _PWMSCLB A9 1 1 0 .abs_section_a9\r
+ _PWMSDN C4 1 1 1 .abs_section_c4\r
+ _RDRH 263 1 1 0 .abs_section_263\r
+ _RDRIV D 1 1 0 .abs_section_d\r
+ _RDRJ 26B 1 1 0 .abs_section_26b\r
+ _RDRM 253 1 1 0 .abs_section_253\r
+ _RDRP 25B 1 1 0 .abs_section_25b\r
+ _RDRS 24B 1 1 0 .abs_section_24b\r
+ _RDRT 243 1 1 0 .abs_section_243\r
+ _REFDV 35 1 1 1 .abs_section_35\r
+ _RTICTL 3B 1 1 0 .abs_section_3b\r
+ _SCI0CR1 CA 1 1 1 .abs_section_ca\r
+ _SCI0CR2 CB 1 1 7 .abs_section_cb\r
+ _SCI0DRH CE 1 1 0 .abs_section_ce\r
+ _SCI0DRL CF 1 1 3 .abs_section_cf\r
+ _SCI0SR1 CC 1 1 2 .abs_section_cc\r
+ _SCI0SR2 CD 1 1 1 .abs_section_cd\r
+ _SCI1CR1 D2 1 1 0 .abs_section_d2\r
+ _SCI1CR2 D3 1 1 0 .abs_section_d3\r
+ _SCI1DRH D6 1 1 0 .abs_section_d6\r
+ _SCI1DRL D7 1 1 0 .abs_section_d7\r
+ _SCI1SR1 D4 1 1 0 .abs_section_d4\r
+ _SCI1SR2 D5 1 1 0 .abs_section_d5\r
+ _SPI0BR DA 1 1 0 .abs_section_da\r
+ _SPI0CR1 D8 1 1 0 .abs_section_d8\r
+ _SPI0CR2 D9 1 1 0 .abs_section_d9\r
+ _SPI0DR DD 1 1 0 .abs_section_dd\r
+ _SPI0SR DB 1 1 0 .abs_section_db\r
+ _SPI1BR F2 1 1 0 .abs_section_f2\r
+ _SPI1CR1 F0 1 1 0 .abs_section_f0\r
+ _SPI1CR2 F1 1 1 0 .abs_section_f1\r
+ _SPI1DR F5 1 1 0 .abs_section_f5\r
+ _SPI1SR F3 1 1 0 .abs_section_f3\r
+ _SPI2BR FA 1 1 0 .abs_section_fa\r
+ _SPI2CR1 F8 1 1 0 .abs_section_f8\r
+ _SPI2CR2 F9 1 1 0 .abs_section_f9\r
+ _SPI2DR FD 1 1 0 .abs_section_fd\r
+ _SPI2SR FB 1 1 0 .abs_section_fb\r
+ _SYNR 34 1 1 1 .abs_section_34\r
+ _TCTL1 48 1 1 1 .abs_section_48\r
+ _TCTL2 49 1 1 1 .abs_section_49\r
+ _TCTL3 4A 1 1 0 .abs_section_4a\r
+ _TCTL4 4B 1 1 0 .abs_section_4b\r
+ _TFLG1 4E 1 1 3 .abs_section_4e\r
+ _TFLG2 4F 1 1 0 .abs_section_4f\r
+ _TIE 4C 1 1 3 .abs_section_4c\r
+ _TIMTST 6D 1 1 0 .abs_section_6d\r
+ _TIOS 40 1 1 1 .abs_section_40\r
+ _TSCR1 46 1 1 3 .abs_section_46\r
+ _TSCR2 4D 1 1 5 .abs_section_4d\r
+ _TTOV 47 1 1 1 .abs_section_47\r
+ _WOMM 256 1 1 0 .abs_section_256\r
+ _WOMS 24E 1 1 0 .abs_section_24e\r
+ _ATD0CTL23 82 2 2 0 .abs_section_82\r
+ _ATD0CTL45 84 2 2 0 .abs_section_84\r
+ _ATD0DR0 90 2 2 0 .abs_section_90\r
+ _ATD0DR1 92 2 2 0 .abs_section_92\r
+ _ATD0DR2 94 2 2 0 .abs_section_94\r
+ _ATD0DR3 96 2 2 0 .abs_section_96\r
+ _ATD0DR4 98 2 2 0 .abs_section_98\r
+ _ATD0DR5 9A 2 2 0 .abs_section_9a\r
+ _ATD0DR6 9C 2 2 0 .abs_section_9c\r
+ _ATD0DR7 9E 2 2 0 .abs_section_9e\r
+ _ATD1CTL23 122 2 2 0 .abs_section_122\r
+ _ATD1CTL45 124 2 2 0 .abs_section_124\r
+ _ATD1DR0 130 2 2 0 .abs_section_130\r
+ _ATD1DR1 132 2 2 0 .abs_section_132\r
+ _ATD1DR2 134 2 2 0 .abs_section_134\r
+ _ATD1DR3 136 2 2 0 .abs_section_136\r
+ _ATD1DR4 138 2 2 0 .abs_section_138\r
+ _ATD1DR5 13A 2 2 0 .abs_section_13a\r
+ _ATD1DR6 13C 2 2 0 .abs_section_13c\r
+ _ATD1DR7 13E 2 2 0 .abs_section_13e\r
+ _DDRAB 2 2 2 1 .abs_section_2\r
+ _MCCNT 76 2 2 0 .abs_section_76\r
+ _PA10H 74 2 2 0 .abs_section_74\r
+ _PA32H 72 2 2 0 .abs_section_72\r
+ _PACN10 64 2 2 0 .abs_section_64\r
+ _PACN32 62 2 2 0 .abs_section_62\r
+ _PORTAB 0 2 2 6 .abs_section_0\r
+ _PWMCNT01 AC 2 2 0 .abs_section_ac\r
+ _PWMCNT23 AE 2 2 0 .abs_section_ae\r
+ _PWMCNT45 B0 2 2 0 .abs_section_b0\r
+ _PWMCNT67 B2 2 2 0 .abs_section_b2\r
+ _PWMDTY01 BC 2 2 0 .abs_section_bc\r
+ _PWMDTY23 BE 2 2 0 .abs_section_be\r
+ _PWMDTY45 C0 2 2 0 .abs_section_c0\r
+ _PWMDTY67 C2 2 2 0 .abs_section_c2\r
+ _PWMPER01 B4 2 2 0 .abs_section_b4\r
+ _PWMPER23 B6 2 2 0 .abs_section_b6\r
+ _PWMPER45 B8 2 2 0 .abs_section_b8\r
+ _PWMPER67 BA 2 2 0 .abs_section_ba\r
+ _SCI0BD C8 2 2 2 .abs_section_c8\r
+ _SCI1BD D0 2 2 0 .abs_section_d0\r
+ _TC0 50 2 2 2 .abs_section_50\r
+ _TC0H 78 2 2 0 .abs_section_78\r
+ _TC1 52 2 2 0 .abs_section_52\r
+ _TC1H 7A 2 2 0 .abs_section_7a\r
+ _TC2 54 2 2 0 .abs_section_54\r
+ _TC2H 7C 2 2 0 .abs_section_7c\r
+ _TC3 56 2 2 0 .abs_section_56\r
+ _TC3H 7E 2 2 0 .abs_section_7e\r
+ _TC4 58 2 2 0 .abs_section_58\r
+ _TC5 5A 2 2 0 .abs_section_5a\r
+ _TC6 5C 2 2 0 .abs_section_5c\r
+ _TC7 5E 2 2 2 .abs_section_5e\r
+ _TCNT 44 2 2 0 .abs_section_44\r
+MODULE: -- Vectors.c.o --\r
+- PROCEDURES:\r
+- VARIABLES:\r
+ _vect FF80 80 128 0 .abs_section_ff80\r
+MODULE: -- RTOSDemo.C.o --\r
+- PROCEDURES:\r
+ main 30809A 9 9 0 .text \r
+- VARIABLES:\r
+MODULE: -- main.c.o --\r
+- PROCEDURES:\r
+ vMain 3080A3 52 82 1 .text \r
+ vErrorChecks 3080F5 39 57 3 .text \r
+ prvCheckOtherTasksAreStillRunning 30812E 50 80 2 .text \r
+ vApplicationIdleHook 30817E 70 112 2 .text \r
+- VARIABLES:\r
+ STRING.Check.1 C09A 6 6 1 .rodata1 \r
+ xLocalError 1001 1 1 2 .bss \r
+MODULE: -- ParTest.c.o --\r
+- PROCEDURES:\r
+ vParTestSetLED 3081EE 23 35 4 .text \r
+ vParTestToggleLED 308211 14 20 10 .text \r
+- VARIABLES:\r
+MODULE: -- serial.c.o --\r
+- PROCEDURES:\r
+ xSerialPortInitMinimal 308225 26 38 2 .text \r
+ xSerialGetChar 318000 13 19 4 ROM_PAGE31_524\r
+ xSerialPutChar 318013 18 24 2 ROM_PAGE31_524\r
+ vCOM0_ISR C300 59 89 1 NON_BANKED \r
+- VARIABLES:\r
+ xRxedChars 1002 2 2 3 .bss \r
+ xCharsForTx 1004 2 2 3 .bss \r
+MODULE: -- tasks.c.o --\r
+- PROCEDURES:\r
+ xTaskCreate 31802B D5 213 48 ROM_PAGE31_524\r
+ vTaskDelete 318100 4A 74 4 ROM_PAGE31_524\r
+ vTaskDelayUntil 31814A 77 119 6 ROM_PAGE31_524\r
+ vTaskDelay 3181C1 46 70 16 ROM_PAGE31_524\r
+ uxTaskPriorityGet 318207 22 34 2 ROM_PAGE31_524\r
+ vTaskPrioritySet 328000 69 105 4 ROM_PAGE32_525\r
+ vTaskSuspend 328069 47 71 6 ROM_PAGE32_525\r
+ vTaskResume 3280B0 5C 92 6 ROM_PAGE32_525\r
+ vTaskStartScheduler 32810C 31 49 2 ROM_PAGE32_525\r
+ vTaskSuspendAll 32813D 13 19 26 ROM_PAGE32_525\r
+ xTaskResumeAll 328150 9F 159 30 ROM_PAGE32_525\r
+ xTaskGetTickCount 3281EF 17 23 6 ROM_PAGE32_525\r
+ uxTaskGetNumberOfTasks 328206 17 23 4 ROM_PAGE32_525\r
+ vTaskIncrementTick 338000 84 132 4 ROM_PAGE33_526\r
+ vTaskSwitchContext 338084 5B 91 4 ROM_PAGE33_526\r
+ vTaskPlaceOnEventList 3380DF 41 65 4 ROM_PAGE33_526\r
+ xTaskRemoveFromEventList 338120 69 105 8 ROM_PAGE33_526\r
+ prvIdleTask 338189 12 18 3 ROM_PAGE33_526\r
+ prvInitialiseTCBVariables 33819B 4D 77 2 ROM_PAGE33_526\r
+ prvInitialiseTaskLists 3381E8 3C 60 2 ROM_PAGE33_526\r
+ prvCheckTasksWaitingTermination 348000 53 83 2 ROM_PAGE34_527\r
+ prvAllocateTCBAndStack 348053 3D 61 2 ROM_PAGE34_527\r
+ prvDeleteTCB 348090 F 15 2 ROM_PAGE34_527\r
+- VARIABLES:\r
+ STRING.IDLE.2 C0A0 5 5 1 .rodata1 \r
+ pxCurrentTCB 1006 2 2 28 .bss \r
+ uxTasksDeleted 1008 1 1 3 .bss \r
+ uxCurrentNumberOfTasks 1009 1 1 5 .bss \r
+ xTickCount 100A 2 2 14 .bss \r
+ uxTopUsedPriority 100C 1 1 2 .bss \r
+ uxTopReadyPriority 100D 1 1 15 .bss \r
+ xSchedulerRunning 100E 1 1 3 .bss \r
+ uxSchedulerSuspended 100F 1 1 6 .bss \r
+ uxMissedTicks 1010 1 1 4 .bss \r
+ uxTaskNumber.1 1011 1 1 2 .bss \r
+ pxReadyTasksLists 1012 3C 60 11 .bss \r
+ xDelayedTaskList1 104E F 15 2 .bss \r
+ xDelayedTaskList2 105D F 15 2 .bss \r
+ pxDelayedTaskList 106C 2 2 8 .bss \r
+ pxOverflowDelayedTaskList 106E 2 2 6 .bss \r
+ xPendingReadyList 1070 F 15 4 .bss \r
+ xTasksWaitingTermination 107F F 15 5 .bss \r
+ xSuspendedTaskList 108E F 15 2 .bss \r
+MODULE: -- queue.c.o --\r
+- PROCEDURES:\r
+ xQueueCreate 34809F 7B 123 14 ROM_PAGE34_527\r
+ xQueueSend 34811A D4 212 9 ROM_PAGE34_527\r
+ xQueueSendFromISR 3481EE 5D 93 2 ROM_PAGE34_527\r
+ xQueueReceive 358000 CF 207 9 ROM_PAGE35_528\r
+ xQueueReceiveFromISR 3580CF 61 97 2 ROM_PAGE35_528\r
+ uxQueueMessagesWaiting 358130 1B 27 2 ROM_PAGE35_528\r
+ prvUnlockQueue 35814B 71 113 8 ROM_PAGE35_528\r
+ prvIsQueueEmpty 3581BC 22 34 2 ROM_PAGE35_528\r
+ prvIsQueueFull 3581DE 25 37 2 ROM_PAGE35_528\r
+- VARIABLES:\r
+MODULE: -- list.c.o --\r
+- PROCEDURES:\r
+ vListInitialise 358203 20 32 6 ROM_PAGE35_528\r
+ vListInitialiseItem 358223 7 7 6 ROM_PAGE35_528\r
+ vListInsertEnd 35822A 25 37 16 ROM_PAGE35_528\r
+ vListInsert 368000 55 85 8 ROM_PAGE36_529\r
+ vListRemove 368055 23 35 32 ROM_PAGE36_529\r
+- VARIABLES:\r
+MODULE: -- heap_2.c.o --\r
+- PROCEDURES:\r
+ pvPortMalloc 368078 C1 193 14 ROM_PAGE36_529\r
+ vPortFree 368139 3B 59 10 ROM_PAGE36_529\r
+- VARIABLES:\r
+ xHeapHasBeenInitialised.1 109D 1 1 2 .bss \r
+ xHeap 109E 2804 10244 2 .bss \r
+ xStart 38A2 4 4 6 .bss \r
+ xEnd 38A6 4 4 4 .bss \r
+MODULE: -- flash.c.o --\r
+- PROCEDURES:\r
+ vStartLEDFlashTasks 368174 32 50 2 ROM_PAGE36_529\r
+ vLEDFlashTask 3681A6 57 87 3 ROM_PAGE36_529\r
+- VARIABLES:\r
+ STRING.LEDx.1 C0A5 5 5 1 .rodata1 \r
+ uxFlashTaskNumber 38AA 1 1 2 .bss \r
+MODULE: -- dynamic.c.o --\r
+- PROCEDURES:\r
+ vStartDynamicPriorityTasks 378000 9B 155 2 ROM_PAGE37_530\r
+ vLimitedIncrementTask 37809B 27 39 3 ROM_PAGE37_530\r
+ vContinuousIncrementTask 3780C2 38 56 3 ROM_PAGE37_530\r
+ vCounterControlTask 3780FA A0 160 5 ROM_PAGE37_530\r
+ vQueueSendWhenSuspendedTask 37819A 38 56 3 ROM_PAGE37_530\r
+ vQueueReceiveWhenSuspendedTask 3781D2 54 84 3 ROM_PAGE37_530\r
+ xAreDynamicPriorityTasksStillRunning 378226 2B 43 2 ROM_PAGE37_530\r
+- VARIABLES:\r
+ STRING.CNT_INC.1 C0AA 8 8 1 .rodata1 \r
+ STRING.LIM_INC.2 C0B2 8 8 1 .rodata1 \r
+ STRING.C_CTRL.3 C0BA 7 7 1 .rodata1 \r
+ STRING.SUSP_TX.4 C0C1 8 8 1 .rodata1 \r
+ STRING.SUSP_RX.5 C0C9 8 8 1 .rodata1 \r
+ usCheckVariable 38AB 2 2 3 .bss \r
+ xSuspendedQueueSendError 38AD 1 1 2 .bss \r
+ xSuspendedQueueReceiveError 38AE 1 1 3 .bss \r
+ ulValueToSend.6 38AF 4 4 5 .bss \r
+ ulExpectedValue.7 38B3 4 4 6 .bss \r
+ usLastTaskCheck.9 38B7 2 2 2 .bss \r
+ xContinousIncrementHandle 38B9 2 2 5 .bss \r
+ xLimitedIncrementHandle 38BB 2 2 2 .bss \r
+ ulCounter 38BD 4 4 10 .bss \r
+ ulReceivedValue.8 38C1 4 4 3 .bss \r
+ xSuspendedTestQueue 38EC 2 2 3 .common \r
+MODULE: -- PollQ.c.o --\r
+- PROCEDURES:\r
+ vStartPolledQueueTasks 388000 4B 75 2 ROM_PAGE38_531\r
+ vPolledQueueProducer 38804B 4F 79 3 ROM_PAGE38_531\r
+ vPolledQueueConsumer 38809A 5C 92 3 ROM_PAGE38_531\r
+ xArePollingQueuesStillRunning 3880F6 16 22 2 ROM_PAGE38_531\r
+- VARIABLES:\r
+ STRING.QConsNB.2 C0D1 8 8 1 .rodata1 \r
+ STRING.QProdNB.3 C0D9 8 8 1 .rodata1 \r
+ xPollingConsumerCount 38C5 1 1 3 .bss \r
+ xPollingProducerCount 38C6 1 1 3 .bss \r
+ xPolledQueue.1 38C7 2 2 3 .bss \r
+MODULE: -- TickTimer.C.o --\r
+- PROCEDURES:\r
+ TickTimer_Enable 3B8124 9 9 2 TickTimer_CODE\r
+ TickTimer_SetFreqHz 3B812D 56 86 2 TickTimer_CODE\r
+ TickTimer_Init 3B8183 1C 28 2 TickTimer_CODE\r
+- VARIABLES:\r
+ CmpHighVal 38F2 2 2 2 TickTimer_DATA\r
+MODULE: -- Byte1.C.o --\r
+- PROCEDURES:\r
+ Byte1_PutBit 3B819F 21 33 2 Byte1_CODE \r
+ Byte1_NegBit 3B81C0 14 20 2 Byte1_CODE \r
+- VARIABLES:\r
+ Byte1_Table 38F4 8 8 2 Byte1_DATA \r
+MODULE: -- PE_Timer.C.o --\r
+- PROCEDURES:\r
+ PE_Timer_LngHi1 38810C 4A 74 2 ROM_PAGE38_531\r
+- VARIABLES:\r
+MODULE: -- comtest.c.o --\r
+- PROCEDURES:\r
+ vAltStartComTestTasks 388156 4D 77 2 ROM_PAGE38_531\r
+ vComTxTask 3881A3 4F 79 3 ROM_PAGE38_531\r
+ vComRxTask 398000 7B 123 3 ROM_PAGE39_532\r
+ xAreComTestTasksStillRunning 39807B D 13 2 ROM_PAGE39_532\r
+- VARIABLES:\r
+ STRING.COMTx.1 C0E1 6 6 1 .rodata1 \r
+ STRING.COMRx.2 C0E7 6 6 1 .rodata1 \r
+ xPort 38C9 2 2 3 .bss \r
+ uxBaseLED 38CB 1 1 5 .bss \r
+ uxRxLoops 38CC 1 1 3 .bss \r
+MODULE: -- COM0.C.o --\r
+- PROCEDURES:\r
+ COM0_SetBaudRateMode 3B81D4 19 25 2 COM0_CODE \r
+ COM0_Init 3B81ED 25 37 2 COM0_CODE \r
+- VARIABLES:\r
+ COM0_PrescHigh.1 38FC 8 8 1 COM0_DATA \r
+ SerFlag 3904 2 2 1 COM0_DATA \r
+ PrescHigh 3906 2 2 2 COM0_DATA \r
+ NumMode 3908 1 1 2 COM0_DATA \r
+MODULE: -- port.c.o --\r
+- PROCEDURES:\r
+ pxPortInitialiseStack 398088 31 49 2 ROM_PAGE39_532\r
+ xPortStartScheduler 3980B9 4 4 2 ROM_PAGE39_532\r
+ xBankedStartScheduler C359 1A 26 1 NON_BANKED \r
+ vPortYield C373 1D 29 1 NON_BANKED \r
+ vPortTickInterrupt C390 25 37 1 NON_BANKED \r
+- VARIABLES:\r
+ uxCriticalNesting 1000 1 1 101 .data \r
+MODULE: -- integer.c.o --\r
+- PROCEDURES:\r
+ vStartIntegerMathTasks 3980BD 33 51 2 ROM_PAGE39_532\r
+ vCompeteingIntMathTask 3980F0 87 135 3 ROM_PAGE39_532\r
+ xAreIntegerMathsTaskStillRunning 398177 20 32 2 ROM_PAGE39_532\r
+- VARIABLES:\r
+ STRING.IntMath.1 C0ED 8 8 1 .rodata1 \r
+ xTaskCheck 38CD 1 1 3 .bss \r
+MODULE: -- BlockQ.c.o --\r
+- PROCEDURES:\r
+ vStartBlockingQueueTasks 3A8000 143 323 7 ROM_PAGE3A_533\r
+ vBlockingQueueProducer 3A8143 3F 63 9 ROM_PAGE3A_533\r
+ vBlockingQueueConsumer 3A8182 47 71 9 ROM_PAGE3A_533\r
+ xAreBlockingQueuesStillRunning 3A81C9 52 82 2 ROM_PAGE3A_533\r
+- VARIABLES:\r
+ STRING.QConsB1.1 C0F5 8 8 1 .rodata1 \r
+ STRING.QProdB2.2 C0FD 8 8 1 .rodata1 \r
+ STRING.QProdB3.3 C105 8 8 1 .rodata1 \r
+ STRING.QConsB4.4 C10D 8 8 1 .rodata1 \r
+ STRING.QProdB5.5 C115 8 8 1 .rodata1 \r
+ STRING.QConsB6.6 C11D 8 8 1 .rodata1 \r
+ sBlockingConsumerCount 38CE 6 6 4 .bss \r
+ sBlockingProducerCount 38D4 6 6 5 .bss \r
+ sLastBlockingConsumerCount.7 38DA 6 6 2 .bss \r
+ sLastBlockingProducerCount.8 38E0 6 6 2 .bss \r
+MODULE: -- death.c.o --\r
+- PROCEDURES:\r
+ vCreateSuicidalTasks 3A821B 31 49 2 ROM_PAGE3A_533\r
+ vSuicidalTask 3B8000 58 88 12 ROM_PAGE3B_534\r
+ vCreateTasks 3B8058 92 146 4 ROM_PAGE3B_534\r
+ xIsCreateTaskStillRunning 3B80EA 3A 58 2 ROM_PAGE3B_534\r
+- VARIABLES:\r
+ STRING.CREATOR.1 C125 8 8 1 .rodata1 \r
+ STRING.SUICIDE1.2 C12D 9 9 1 .rodata1 \r
+ STRING.SUICIDE2.3 C136 9 9 1 .rodata1 \r
+ STRING.SUICIDE1.4 C13F 9 9 1 .rodata1 \r
+ STRING.SUICIDE2.5 C148 9 9 1 .rodata1 \r
+ usCreationCount 38E6 2 2 4 .bss \r
+ uxTasksRunningAtStart 38E8 1 1 4 .bss \r
+ usLastCreationCount.6 38E9 2 2 2 .bss \r
+ uxTasksRunningNow.7 38EB 1 1 1 .bss \r
+ xCreatedTask1 38EE 2 2 2 .common \r
+ xCreatedTask2 38F0 2 2 2 .common \r
+\r
+*********************************************************************************************\r
+MODULE STATISTIC\r
+ Name Data Code Const\r
+---------------------------------------------------------------------------------------------\r
+ Start12.c.o 0 59 0\r
+ STRING.C.o (ansibi.lib) 0 113 0\r
+ rtshc12.c.o (ansibi.lib) 0 412 0\r
+ Cpu.C.o 0 125 0\r
+ IO_Map.C.o 577 0 0\r
+ Vectors.c.o 0 0 128\r
+ RTOSDemo.C.o 0 9 0\r
+ main.c.o 1 331 6\r
+ ParTest.c.o 0 55 0\r
+ serial.c.o 4 170 0\r
+ tasks.c.o 151 1758 5\r
+ queue.c.o 0 943 0\r
+ list.c.o 0 196 0\r
+ heap_2.c.o 10253 252 0\r
+ flash.c.o 1 137 5\r
+ dynamic.c.o 28 593 39\r
+ PollQ.c.o 4 268 16\r
+ TickTimer.C.o 2 123 0\r
+ Byte1.C.o 8 53 0\r
+ PE_Timer.C.o 0 74 0\r
+ comtest.c.o 4 292 12\r
+ COM0.C.o 13 62 0\r
+ port.c.o 1 145 0\r
+ integer.c.o 1 218 8\r
+ BlockQ.c.o 24 539 48\r
+ death.c.o 10 341 44\r
+ other 128 30 27\r
+\r
+*********************************************************************************************\r
+SECTION USE IN OBJECT-ALLOCATION SECTION\r
+---------------------------------------------------------------------------------------------\r
+SECTION: ".text"\r
+ Init memcpy memset strncpy main vMain vErrorChecks \r
+ prvCheckOtherTasksAreStillRunning vApplicationIdleHook vParTestSetLED \r
+ vParTestToggleLED xSerialPortInitMinimal \r
+SECTION: ".data"\r
+ uxCriticalNesting \r
+SECTION: ".bss"\r
+ xLocalError xRxedChars xCharsForTx pxCurrentTCB uxTasksDeleted \r
+ uxCurrentNumberOfTasks xTickCount uxTopUsedPriority uxTopReadyPriority \r
+ xSchedulerRunning uxSchedulerSuspended uxMissedTicks uxTaskNumber.1 \r
+ pxReadyTasksLists xDelayedTaskList1 xDelayedTaskList2 pxDelayedTaskList \r
+ pxOverflowDelayedTaskList xPendingReadyList xTasksWaitingTermination \r
+ xSuspendedTaskList xHeapHasBeenInitialised.1 xHeap xStart xEnd \r
+ uxFlashTaskNumber usCheckVariable xSuspendedQueueSendError \r
+ xSuspendedQueueReceiveError ulValueToSend.6 ulExpectedValue.7 \r
+ usLastTaskCheck.9 xContinousIncrementHandle xLimitedIncrementHandle ulCounter \r
+ ulReceivedValue.8 xPollingConsumerCount xPollingProducerCount xPolledQueue.1 \r
+ xPort uxBaseLED uxRxLoops xTaskCheck sBlockingConsumerCount \r
+ sBlockingProducerCount sLastBlockingConsumerCount.7 \r
+ sLastBlockingProducerCount.8 usCreationCount uxTasksRunningAtStart \r
+ usLastCreationCount.6 uxTasksRunningNow.7 \r
+SECTION: ".init"\r
+ _EntryPoint PE_low_level_init \r
+SECTION: ".rodata1"\r
+ STRING.Check.1 STRING.IDLE.2 STRING.LEDx.1 STRING.CNT_INC.1 STRING.LIM_INC.2 \r
+ STRING.C_CTRL.3 STRING.SUSP_TX.4 STRING.SUSP_RX.5 STRING.QConsNB.2 \r
+ STRING.QProdNB.3 STRING.COMTx.1 STRING.COMRx.2 STRING.IntMath.1 \r
+ STRING.QConsB1.1 STRING.QProdB2.2 STRING.QProdB3.3 STRING.QConsB4.4 \r
+ STRING.QProdB5.5 STRING.QConsB6.6 STRING.CREATOR.1 STRING.SUICIDE1.2 \r
+ STRING.SUICIDE2.3 STRING.SUICIDE1.4 STRING.SUICIDE2.5 \r
+SECTION: "NON_BANKED"\r
+ _Startup _LCMP _LCMP_P _LNEG _LINC _LMUL _lDivMod _LDIVU _NEG_P _LDIVS \r
+ Cpu_Interrupt vCOM0_ISR xBankedStartScheduler vPortYield vPortTickInterrupt \r
+SECTION: ".common"\r
+ xSuspendedTestQueue xCreatedTask1 xCreatedTask2 \r
+SECTION: "TickTimer_CODE"\r
+ TickTimer_Enable TickTimer_SetFreqHz TickTimer_Init \r
+SECTION: "Byte1_CODE"\r
+ Byte1_PutBit Byte1_NegBit \r
+SECTION: "COM0_CODE"\r
+ COM0_SetBaudRateMode COM0_Init \r
+SECTION: ".abs_section_3f"\r
+ _ARMCOP \r
+SECTION: ".abs_section_8d"\r
+ _ATD0DIEN \r
+SECTION: ".abs_section_86"\r
+ _ATD0STAT0 \r
+SECTION: ".abs_section_8b"\r
+ _ATD0STAT1 \r
+SECTION: ".abs_section_12d"\r
+ _ATD1DIEN \r
+SECTION: ".abs_section_126"\r
+ _ATD1STAT0 \r
+SECTION: ".abs_section_12b"\r
+ _ATD1STAT1 \r
+SECTION: ".abs_section_ff06"\r
+ _BDMCCR \r
+SECTION: ".abs_section_ff07"\r
+ _BDMINR \r
+SECTION: ".abs_section_ff01"\r
+ _BDMSTS \r
+SECTION: ".abs_section_2b"\r
+ _BKP0H \r
+SECTION: ".abs_section_2c"\r
+ _BKP0L \r
+SECTION: ".abs_section_2a"\r
+ _BKP0X \r
+SECTION: ".abs_section_2e"\r
+ _BKP1H \r
+SECTION: ".abs_section_2f"\r
+ _BKP1L \r
+SECTION: ".abs_section_2d"\r
+ _BKP1X \r
+SECTION: ".abs_section_28"\r
+ _BKPCT0 \r
+SECTION: ".abs_section_29"\r
+ _BKPCT1 \r
+SECTION: ".abs_section_142"\r
+ _CAN0BTR0 \r
+SECTION: ".abs_section_143"\r
+ _CAN0BTR1 \r
+SECTION: ".abs_section_140"\r
+ _CAN0CTL0 \r
+SECTION: ".abs_section_141"\r
+ _CAN0CTL1 \r
+SECTION: ".abs_section_14b"\r
+ _CAN0IDAC \r
+SECTION: ".abs_section_150"\r
+ _CAN0IDAR0 \r
+SECTION: ".abs_section_151"\r
+ _CAN0IDAR1 \r
+SECTION: ".abs_section_152"\r
+ _CAN0IDAR2 \r
+SECTION: ".abs_section_153"\r
+ _CAN0IDAR3 \r
+SECTION: ".abs_section_158"\r
+ _CAN0IDAR4 \r
+SECTION: ".abs_section_159"\r
+ _CAN0IDAR5 \r
+SECTION: ".abs_section_15a"\r
+ _CAN0IDAR6 \r
+SECTION: ".abs_section_15b"\r
+ _CAN0IDAR7 \r
+SECTION: ".abs_section_154"\r
+ _CAN0IDMR0 \r
+SECTION: ".abs_section_155"\r
+ _CAN0IDMR1 \r
+SECTION: ".abs_section_156"\r
+ _CAN0IDMR2 \r
+SECTION: ".abs_section_157"\r
+ _CAN0IDMR3 \r
+SECTION: ".abs_section_15c"\r
+ _CAN0IDMR4 \r
+SECTION: ".abs_section_15d"\r
+ _CAN0IDMR5 \r
+SECTION: ".abs_section_15e"\r
+ _CAN0IDMR6 \r
+SECTION: ".abs_section_15f"\r
+ _CAN0IDMR7 \r
+SECTION: ".abs_section_144"\r
+ _CAN0RFLG \r
+SECTION: ".abs_section_145"\r
+ _CAN0RIER \r
+SECTION: ".abs_section_16c"\r
+ _CAN0RXDLR \r
+SECTION: ".abs_section_164"\r
+ _CAN0RXDSR0 \r
+SECTION: ".abs_section_165"\r
+ _CAN0RXDSR1 \r
+SECTION: ".abs_section_166"\r
+ _CAN0RXDSR2 \r
+SECTION: ".abs_section_167"\r
+ _CAN0RXDSR3 \r
+SECTION: ".abs_section_168"\r
+ _CAN0RXDSR4 \r
+SECTION: ".abs_section_169"\r
+ _CAN0RXDSR5 \r
+SECTION: ".abs_section_16a"\r
+ _CAN0RXDSR6 \r
+SECTION: ".abs_section_16b"\r
+ _CAN0RXDSR7 \r
+SECTION: ".abs_section_14e"\r
+ _CAN0RXERR \r
+SECTION: ".abs_section_160"\r
+ _CAN0RXIDR0 \r
+SECTION: ".abs_section_161"\r
+ _CAN0RXIDR1 \r
+SECTION: ".abs_section_162"\r
+ _CAN0RXIDR2 \r
+SECTION: ".abs_section_163"\r
+ _CAN0RXIDR3 \r
+SECTION: ".abs_section_149"\r
+ _CAN0TAAK \r
+SECTION: ".abs_section_148"\r
+ _CAN0TARQ \r
+SECTION: ".abs_section_14a"\r
+ _CAN0TBSEL \r
+SECTION: ".abs_section_146"\r
+ _CAN0TFLG \r
+SECTION: ".abs_section_147"\r
+ _CAN0TIER \r
+SECTION: ".abs_section_17c"\r
+ _CAN0TXDLR \r
+SECTION: ".abs_section_174"\r
+ _CAN0TXDSR0 \r
+SECTION: ".abs_section_175"\r
+ _CAN0TXDSR1 \r
+SECTION: ".abs_section_176"\r
+ _CAN0TXDSR2 \r
+SECTION: ".abs_section_177"\r
+ _CAN0TXDSR3 \r
+SECTION: ".abs_section_178"\r
+ _CAN0TXDSR4 \r
+SECTION: ".abs_section_179"\r
+ _CAN0TXDSR5 \r
+SECTION: ".abs_section_17a"\r
+ _CAN0TXDSR6 \r
+SECTION: ".abs_section_17b"\r
+ _CAN0TXDSR7 \r
+SECTION: ".abs_section_14f"\r
+ _CAN0TXERR \r
+SECTION: ".abs_section_170"\r
+ _CAN0TXIDR0 \r
+SECTION: ".abs_section_171"\r
+ _CAN0TXIDR1 \r
+SECTION: ".abs_section_172"\r
+ _CAN0TXIDR2 \r
+SECTION: ".abs_section_173"\r
+ _CAN0TXIDR3 \r
+SECTION: ".abs_section_17f"\r
+ _CAN0TXTBPR \r
+SECTION: ".abs_section_182"\r
+ _CAN1BTR0 \r
+SECTION: ".abs_section_183"\r
+ _CAN1BTR1 \r
+SECTION: ".abs_section_180"\r
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+ _PTIP \r
+SECTION: ".abs_section_249"\r
+ _PTIS \r
+SECTION: ".abs_section_241"\r
+ _PTIT \r
+SECTION: ".abs_section_268"\r
+ _PTJ \r
+SECTION: ".abs_section_250"\r
+ _PTM \r
+SECTION: ".abs_section_258"\r
+ _PTP \r
+SECTION: ".abs_section_248"\r
+ _PTS \r
+SECTION: ".abs_section_240"\r
+ _PTT \r
+SECTION: ".abs_section_c"\r
+ _PUCR \r
+SECTION: ".abs_section_a4"\r
+ _PWMCAE \r
+SECTION: ".abs_section_a2"\r
+ _PWMCLK \r
+SECTION: ".abs_section_a5"\r
+ _PWMCTL \r
+SECTION: ".abs_section_a0"\r
+ _PWME \r
+SECTION: ".abs_section_a1"\r
+ _PWMPOL \r
+SECTION: ".abs_section_a3"\r
+ _PWMPRCLK \r
+SECTION: ".abs_section_a8"\r
+ _PWMSCLA \r
+SECTION: ".abs_section_a9"\r
+ _PWMSCLB \r
+SECTION: ".abs_section_c4"\r
+ _PWMSDN \r
+SECTION: ".abs_section_263"\r
+ _RDRH \r
+SECTION: ".abs_section_d"\r
+ _RDRIV \r
+SECTION: ".abs_section_26b"\r
+ _RDRJ \r
+SECTION: ".abs_section_253"\r
+ _RDRM \r
+SECTION: ".abs_section_25b"\r
+ _RDRP \r
+SECTION: ".abs_section_24b"\r
+ _RDRS \r
+SECTION: ".abs_section_243"\r
+ _RDRT \r
+SECTION: ".abs_section_35"\r
+ _REFDV \r
+SECTION: ".abs_section_3b"\r
+ _RTICTL \r
+SECTION: ".abs_section_ca"\r
+ _SCI0CR1 \r
+SECTION: ".abs_section_cb"\r
+ _SCI0CR2 \r
+SECTION: ".abs_section_ce"\r
+ _SCI0DRH \r
+SECTION: ".abs_section_cf"\r
+ _SCI0DRL \r
+SECTION: ".abs_section_cc"\r
+ _SCI0SR1 \r
+SECTION: ".abs_section_cd"\r
+ _SCI0SR2 \r
+SECTION: ".abs_section_d2"\r
+ _SCI1CR1 \r
+SECTION: ".abs_section_d3"\r
+ _SCI1CR2 \r
+SECTION: ".abs_section_d6"\r
+ _SCI1DRH \r
+SECTION: ".abs_section_d7"\r
+ _SCI1DRL \r
+SECTION: ".abs_section_d4"\r
+ _SCI1SR1 \r
+SECTION: ".abs_section_d5"\r
+ _SCI1SR2 \r
+SECTION: ".abs_section_da"\r
+ _SPI0BR \r
+SECTION: ".abs_section_d8"\r
+ _SPI0CR1 \r
+SECTION: ".abs_section_d9"\r
+ _SPI0CR2 \r
+SECTION: ".abs_section_dd"\r
+ _SPI0DR \r
+SECTION: ".abs_section_db"\r
+ _SPI0SR \r
+SECTION: ".abs_section_f2"\r
+ _SPI1BR \r
+SECTION: ".abs_section_f0"\r
+ _SPI1CR1 \r
+SECTION: ".abs_section_f1"\r
+ _SPI1CR2 \r
+SECTION: ".abs_section_f5"\r
+ _SPI1DR \r
+SECTION: ".abs_section_f3"\r
+ _SPI1SR \r
+SECTION: ".abs_section_fa"\r
+ _SPI2BR \r
+SECTION: ".abs_section_f8"\r
+ _SPI2CR1 \r
+SECTION: ".abs_section_f9"\r
+ _SPI2CR2 \r
+SECTION: ".abs_section_fd"\r
+ _SPI2DR \r
+SECTION: ".abs_section_fb"\r
+ _SPI2SR \r
+SECTION: ".abs_section_34"\r
+ _SYNR \r
+SECTION: ".abs_section_48"\r
+ _TCTL1 \r
+SECTION: ".abs_section_49"\r
+ _TCTL2 \r
+SECTION: ".abs_section_4a"\r
+ _TCTL3 \r
+SECTION: ".abs_section_4b"\r
+ _TCTL4 \r
+SECTION: ".abs_section_4e"\r
+ _TFLG1 \r
+SECTION: ".abs_section_4f"\r
+ _TFLG2 \r
+SECTION: ".abs_section_4c"\r
+ _TIE \r
+SECTION: ".abs_section_6d"\r
+ _TIMTST \r
+SECTION: ".abs_section_40"\r
+ _TIOS \r
+SECTION: ".abs_section_46"\r
+ _TSCR1 \r
+SECTION: ".abs_section_4d"\r
+ _TSCR2 \r
+SECTION: ".abs_section_47"\r
+ _TTOV \r
+SECTION: ".abs_section_256"\r
+ _WOMM \r
+SECTION: ".abs_section_24e"\r
+ _WOMS \r
+SECTION: ".abs_section_82"\r
+ _ATD0CTL23 \r
+SECTION: ".abs_section_84"\r
+ _ATD0CTL45 \r
+SECTION: ".abs_section_90"\r
+ _ATD0DR0 \r
+SECTION: ".abs_section_92"\r
+ _ATD0DR1 \r
+SECTION: ".abs_section_94"\r
+ _ATD0DR2 \r
+SECTION: ".abs_section_96"\r
+ _ATD0DR3 \r
+SECTION: ".abs_section_98"\r
+ _ATD0DR4 \r
+SECTION: ".abs_section_9a"\r
+ _ATD0DR5 \r
+SECTION: ".abs_section_9c"\r
+ _ATD0DR6 \r
+SECTION: ".abs_section_9e"\r
+ _ATD0DR7 \r
+SECTION: ".abs_section_122"\r
+ _ATD1CTL23 \r
+SECTION: ".abs_section_124"\r
+ _ATD1CTL45 \r
+SECTION: ".abs_section_130"\r
+ _ATD1DR0 \r
+SECTION: ".abs_section_132"\r
+ _ATD1DR1 \r
+SECTION: ".abs_section_134"\r
+ _ATD1DR2 \r
+SECTION: ".abs_section_136"\r
+ _ATD1DR3 \r
+SECTION: ".abs_section_138"\r
+ _ATD1DR4 \r
+SECTION: ".abs_section_13a"\r
+ _ATD1DR5 \r
+SECTION: ".abs_section_13c"\r
+ _ATD1DR6 \r
+SECTION: ".abs_section_13e"\r
+ _ATD1DR7 \r
+SECTION: ".abs_section_2"\r
+ _DDRAB \r
+SECTION: ".abs_section_76"\r
+ _MCCNT \r
+SECTION: ".abs_section_74"\r
+ _PA10H \r
+SECTION: ".abs_section_72"\r
+ _PA32H \r
+SECTION: ".abs_section_64"\r
+ _PACN10 \r
+SECTION: ".abs_section_62"\r
+ _PACN32 \r
+SECTION: ".abs_section_0"\r
+ _PORTAB \r
+SECTION: ".abs_section_ac"\r
+ _PWMCNT01 \r
+SECTION: ".abs_section_ae"\r
+ _PWMCNT23 \r
+SECTION: ".abs_section_b0"\r
+ _PWMCNT45 \r
+SECTION: ".abs_section_b2"\r
+ _PWMCNT67 \r
+SECTION: ".abs_section_bc"\r
+ _PWMDTY01 \r
+SECTION: ".abs_section_be"\r
+ _PWMDTY23 \r
+SECTION: ".abs_section_c0"\r
+ _PWMDTY45 \r
+SECTION: ".abs_section_c2"\r
+ _PWMDTY67 \r
+SECTION: ".abs_section_b4"\r
+ _PWMPER01 \r
+SECTION: ".abs_section_b6"\r
+ _PWMPER23 \r
+SECTION: ".abs_section_b8"\r
+ _PWMPER45 \r
+SECTION: ".abs_section_ba"\r
+ _PWMPER67 \r
+SECTION: ".abs_section_c8"\r
+ _SCI0BD \r
+SECTION: ".abs_section_d0"\r
+ _SCI1BD \r
+SECTION: ".abs_section_50"\r
+ _TC0 \r
+SECTION: ".abs_section_78"\r
+ _TC0H \r
+SECTION: ".abs_section_52"\r
+ _TC1 \r
+SECTION: ".abs_section_7a"\r
+ _TC1H \r
+SECTION: ".abs_section_54"\r
+ _TC2 \r
+SECTION: ".abs_section_7c"\r
+ _TC2H \r
+SECTION: ".abs_section_56"\r
+ _TC3 \r
+SECTION: ".abs_section_7e"\r
+ _TC3H \r
+SECTION: ".abs_section_58"\r
+ _TC4 \r
+SECTION: ".abs_section_5a"\r
+ _TC5 \r
+SECTION: ".abs_section_5c"\r
+ _TC6 \r
+SECTION: ".abs_section_5e"\r
+ _TC7 \r
+SECTION: ".abs_section_44"\r
+ _TCNT \r
+SECTION: ".abs_section_ff80"\r
+ _vect \r
+SECTION: "TickTimer_DATA"\r
+ CmpHighVal \r
+SECTION: "Byte1_DATA"\r
+ Byte1_Table \r
+SECTION: "COM0_DATA"\r
+ COM0_PrescHigh.1 SerFlag PrescHigh NumMode \r
+SECTION: "ROM_PAGE31_524"\r
+ xSerialGetChar xSerialPutChar xTaskCreate vTaskDelete vTaskDelayUntil \r
+ vTaskDelay uxTaskPriorityGet \r
+SECTION: "ROM_PAGE32_525"\r
+ vTaskPrioritySet vTaskSuspend vTaskResume vTaskStartScheduler \r
+ vTaskSuspendAll xTaskResumeAll xTaskGetTickCount uxTaskGetNumberOfTasks \r
+SECTION: "ROM_PAGE33_526"\r
+ vTaskIncrementTick vTaskSwitchContext vTaskPlaceOnEventList \r
+ xTaskRemoveFromEventList prvIdleTask prvInitialiseTCBVariables \r
+ prvInitialiseTaskLists \r
+SECTION: "ROM_PAGE34_527"\r
+ prvCheckTasksWaitingTermination prvAllocateTCBAndStack prvDeleteTCB \r
+ xQueueCreate xQueueSend xQueueSendFromISR \r
+SECTION: "ROM_PAGE35_528"\r
+ xQueueReceive xQueueReceiveFromISR uxQueueMessagesWaiting prvUnlockQueue \r
+ prvIsQueueEmpty prvIsQueueFull vListInitialise vListInitialiseItem \r
+ vListInsertEnd \r
+SECTION: "ROM_PAGE36_529"\r
+ vListInsert vListRemove pvPortMalloc vPortFree vStartLEDFlashTasks \r
+ vLEDFlashTask \r
+SECTION: "ROM_PAGE37_530"\r
+ vStartDynamicPriorityTasks vLimitedIncrementTask vContinuousIncrementTask \r
+ vCounterControlTask vQueueSendWhenSuspendedTask \r
+ vQueueReceiveWhenSuspendedTask xAreDynamicPriorityTasksStillRunning \r
+SECTION: "ROM_PAGE38_531"\r
+ vStartPolledQueueTasks vPolledQueueProducer vPolledQueueConsumer \r
+ xArePollingQueuesStillRunning PE_Timer_LngHi1 vAltStartComTestTasks \r
+ vComTxTask \r
+SECTION: "ROM_PAGE39_532"\r
+ vComRxTask xAreComTestTasksStillRunning pxPortInitialiseStack \r
+ xPortStartScheduler vStartIntegerMathTasks vCompeteingIntMathTask \r
+ xAreIntegerMathsTaskStillRunning \r
+SECTION: "ROM_PAGE3A_533"\r
+ vStartBlockingQueueTasks vBlockingQueueProducer vBlockingQueueConsumer \r
+ xAreBlockingQueuesStillRunning vCreateSuicidalTasks \r
+SECTION: "ROM_PAGE3B_534"\r
+ vSuicidalTask vCreateTasks xIsCreateTaskStillRunning \r
+\r
+*********************************************************************************************\r
+OBJECT LIST SORTED BY ADDRESS\r
+ Name Addr hSize dSize Ref Section RLIB\r
+---------------------------------------------------------------------------------------------\r
+ _PORTAB 0 2 2 6 .abs_section_0\r
+ _DDRAB 2 2 2 1 .abs_section_2\r
+ _PORTE 8 1 1 0 .abs_section_8\r
+ _DDRE 9 1 1 0 .abs_section_9\r
+ _PEAR A 1 1 0 .abs_section_a\r
+ _MODE B 1 1 0 .abs_section_b\r
+ _PUCR C 1 1 0 .abs_section_c\r
+ _RDRIV D 1 1 0 .abs_section_d\r
+ _EBICTL E 1 1 0 .abs_section_e\r
+ _INITRM 10 1 1 1 .abs_section_10\r
+ _INITRG 11 1 1 0 .abs_section_11\r
+ _INITEE 12 1 1 1 .abs_section_12\r
+ _MISC 13 1 1 1 .abs_section_13\r
+ _MTST0 14 1 1 0 .abs_section_14\r
+ _ITCR 15 1 1 0 .abs_section_15\r
+ _ITEST 16 1 1 0 .abs_section_16\r
+ _MTST1 17 1 1 0 .abs_section_17\r
+ _PARTIDH 1A 1 1 0 .abs_section_1a\r
+ _PARTIDL 1B 1 1 0 .abs_section_1b\r
+ _MEMSIZ0 1C 1 1 0 .abs_section_1c\r
+ _MEMSIZ1 1D 1 1 0 .abs_section_1d\r
+ _INTCR 1E 1 1 1 .abs_section_1e\r
+ _HPRIO 1F 1 1 0 .abs_section_1f\r
+ _BKPCT0 28 1 1 0 .abs_section_28\r
+ _BKPCT1 29 1 1 0 .abs_section_29\r
+ _BKP0X 2A 1 1 0 .abs_section_2a\r
+ _BKP0H 2B 1 1 0 .abs_section_2b\r
+ _BKP0L 2C 1 1 0 .abs_section_2c\r
+ _BKP1X 2D 1 1 0 .abs_section_2d\r
+ _BKP1H 2E 1 1 0 .abs_section_2e\r
+ _BKP1L 2F 1 1 0 .abs_section_2f\r
+ _PPAGE 30 1 1 0 .abs_section_30\r
+ _PORTK 32 1 1 0 .abs_section_32\r
+ _DDRK 33 1 1 0 .abs_section_33\r
+ _SYNR 34 1 1 1 .abs_section_34\r
+ _REFDV 35 1 1 1 .abs_section_35\r
+ _CTFLG 36 1 1 0 .abs_section_36\r
+ _CRGFLG 37 1 1 1 .abs_section_37\r
+ _CRGINT 38 1 1 0 .abs_section_38\r
+ _CLKSEL 39 1 1 3 .abs_section_39\r
+ _PLLCTL 3A 1 1 3 .abs_section_3a\r
+ _RTICTL 3B 1 1 0 .abs_section_3b\r
+ _COPCTL 3C 1 1 0 .abs_section_3c\r
+ _FORBYP 3D 1 1 0 .abs_section_3d\r
+ _CTCTL 3E 1 1 0 .abs_section_3e\r
+ _ARMCOP 3F 1 1 0 .abs_section_3f\r
+ _TIOS 40 1 1 1 .abs_section_40\r
+ _CFORC 41 1 1 0 .abs_section_41\r
+ _OC7M 42 1 1 0 .abs_section_42\r
+ _OC7D 43 1 1 0 .abs_section_43\r
+ _TCNT 44 2 2 0 .abs_section_44\r
+ _TSCR1 46 1 1 3 .abs_section_46\r
+ _TTOV 47 1 1 1 .abs_section_47\r
+ _TCTL1 48 1 1 1 .abs_section_48\r
+ _TCTL2 49 1 1 1 .abs_section_49\r
+ _TCTL3 4A 1 1 0 .abs_section_4a\r
+ _TCTL4 4B 1 1 0 .abs_section_4b\r
+ _TIE 4C 1 1 3 .abs_section_4c\r
+ _TSCR2 4D 1 1 5 .abs_section_4d\r
+ _TFLG1 4E 1 1 3 .abs_section_4e\r
+ _TFLG2 4F 1 1 0 .abs_section_4f\r
+ _TC0 50 2 2 2 .abs_section_50\r
+ _TC1 52 2 2 0 .abs_section_52\r
+ _TC2 54 2 2 0 .abs_section_54\r
+ _TC3 56 2 2 0 .abs_section_56\r
+ _TC4 58 2 2 0 .abs_section_58\r
+ _TC5 5A 2 2 0 .abs_section_5a\r
+ _TC6 5C 2 2 0 .abs_section_5c\r
+ _TC7 5E 2 2 2 .abs_section_5e\r
+ _PACTL 60 1 1 0 .abs_section_60\r
+ _PAFLG 61 1 1 0 .abs_section_61\r
+ _PACN32 62 2 2 0 .abs_section_62\r
+ _PACN10 64 2 2 0 .abs_section_64\r
+ _MCCTL 66 1 1 1 .abs_section_66\r
+ _MCFLG 67 1 1 0 .abs_section_67\r
+ _ICPAR 68 1 1 0 .abs_section_68\r
+ _DLYCT 69 1 1 0 .abs_section_69\r
+ _ICOVW 6A 1 1 0 .abs_section_6a\r
+ _ICSYS 6B 1 1 1 .abs_section_6b\r
+ _TIMTST 6D 1 1 0 .abs_section_6d\r
+ _PBCTL 70 1 1 0 .abs_section_70\r
+ _PBFLG 71 1 1 0 .abs_section_71\r
+ _PA32H 72 2 2 0 .abs_section_72\r
+ _PA10H 74 2 2 0 .abs_section_74\r
+ _MCCNT 76 2 2 0 .abs_section_76\r
+ _TC0H 78 2 2 0 .abs_section_78\r
+ _TC1H 7A 2 2 0 .abs_section_7a\r
+ _TC2H 7C 2 2 0 .abs_section_7c\r
+ _TC3H 7E 2 2 0 .abs_section_7e\r
+ _ATD0CTL23 82 2 2 0 .abs_section_82\r
+ _ATD0CTL45 84 2 2 0 .abs_section_84\r
+ _ATD0STAT0 86 1 1 0 .abs_section_86\r
+ _ATD0STAT1 8B 1 1 0 .abs_section_8b\r
+ _ATD0DIEN 8D 1 1 0 .abs_section_8d\r
+ _PORTAD0 8F 1 1 0 .abs_section_8f\r
+ _ATD0DR0 90 2 2 0 .abs_section_90\r
+ _ATD0DR1 92 2 2 0 .abs_section_92\r
+ _ATD0DR2 94 2 2 0 .abs_section_94\r
+ _ATD0DR3 96 2 2 0 .abs_section_96\r
+ _ATD0DR4 98 2 2 0 .abs_section_98\r
+ _ATD0DR5 9A 2 2 0 .abs_section_9a\r
+ _ATD0DR6 9C 2 2 0 .abs_section_9c\r
+ _ATD0DR7 9E 2 2 0 .abs_section_9e\r
+ _PWME A0 1 1 0 .abs_section_a0\r
+ _PWMPOL A1 1 1 0 .abs_section_a1\r
+ _PWMCLK A2 1 1 0 .abs_section_a2\r
+ _PWMPRCLK A3 1 1 0 .abs_section_a3\r
+ _PWMCAE A4 1 1 0 .abs_section_a4\r
+ _PWMCTL A5 1 1 1 .abs_section_a5\r
+ _PWMSCLA A8 1 1 0 .abs_section_a8\r
+ _PWMSCLB A9 1 1 0 .abs_section_a9\r
+ _PWMCNT01 AC 2 2 0 .abs_section_ac\r
+ _PWMCNT23 AE 2 2 0 .abs_section_ae\r
+ _PWMCNT45 B0 2 2 0 .abs_section_b0\r
+ _PWMCNT67 B2 2 2 0 .abs_section_b2\r
+ _PWMPER01 B4 2 2 0 .abs_section_b4\r
+ _PWMPER23 B6 2 2 0 .abs_section_b6\r
+ _PWMPER45 B8 2 2 0 .abs_section_b8\r
+ _PWMPER67 BA 2 2 0 .abs_section_ba\r
+ _PWMDTY01 BC 2 2 0 .abs_section_bc\r
+ _PWMDTY23 BE 2 2 0 .abs_section_be\r
+ _PWMDTY45 C0 2 2 0 .abs_section_c0\r
+ _PWMDTY67 C2 2 2 0 .abs_section_c2\r
+ _PWMSDN C4 1 1 1 .abs_section_c4\r
+ _SCI0BD C8 2 2 2 .abs_section_c8\r
+ _SCI0CR1 CA 1 1 1 .abs_section_ca\r
+ _SCI0CR2 CB 1 1 7 .abs_section_cb\r
+ _SCI0SR1 CC 1 1 2 .abs_section_cc\r
+ _SCI0SR2 CD 1 1 1 .abs_section_cd\r
+ _SCI0DRH CE 1 1 0 .abs_section_ce\r
+ _SCI0DRL CF 1 1 3 .abs_section_cf\r
+ _SCI1BD D0 2 2 0 .abs_section_d0\r
+ _SCI1CR1 D2 1 1 0 .abs_section_d2\r
+ _SCI1CR2 D3 1 1 0 .abs_section_d3\r
+ _SCI1SR1 D4 1 1 0 .abs_section_d4\r
+ _SCI1SR2 D5 1 1 0 .abs_section_d5\r
+ _SCI1DRH D6 1 1 0 .abs_section_d6\r
+ _SCI1DRL D7 1 1 0 .abs_section_d7\r
+ _SPI0CR1 D8 1 1 0 .abs_section_d8\r
+ _SPI0CR2 D9 1 1 0 .abs_section_d9\r
+ _SPI0BR DA 1 1 0 .abs_section_da\r
+ _SPI0SR DB 1 1 0 .abs_section_db\r
+ _SPI0DR DD 1 1 0 .abs_section_dd\r
+ _IBAD E0 1 1 0 .abs_section_e0\r
+ _IBFD E1 1 1 0 .abs_section_e1\r
+ _IBCR E2 1 1 0 .abs_section_e2\r
+ _IBSR E3 1 1 0 .abs_section_e3\r
+ _IBDR E4 1 1 0 .abs_section_e4\r
+ _DLCBCR1 E8 1 1 0 .abs_section_e8\r
+ _DLCBSVR E9 1 1 0 .abs_section_e9\r
+ _DLCBCR2 EA 1 1 0 .abs_section_ea\r
+ _DLCBDR EB 1 1 0 .abs_section_eb\r
+ _DLCBARD EC 1 1 0 .abs_section_ec\r
+ _DLCBRSR ED 1 1 0 .abs_section_ed\r
+ _DLCSCR EE 1 1 0 .abs_section_ee\r
+ _SPI1CR1 F0 1 1 0 .abs_section_f0\r
+ _SPI1CR2 F1 1 1 0 .abs_section_f1\r
+ _SPI1BR F2 1 1 0 .abs_section_f2\r
+ _SPI1SR F3 1 1 0 .abs_section_f3\r
+ _SPI1DR F5 1 1 0 .abs_section_f5\r
+ _SPI2CR1 F8 1 1 0 .abs_section_f8\r
+ _SPI2CR2 F9 1 1 0 .abs_section_f9\r
+ _SPI2BR FA 1 1 0 .abs_section_fa\r
+ _SPI2SR FB 1 1 0 .abs_section_fb\r
+ _SPI2DR FD 1 1 0 .abs_section_fd\r
+ _FCLKDIV 100 1 1 0 .abs_section_100\r
+ _FSEC 101 1 1 0 .abs_section_101\r
+ _FCNFG 103 1 1 0 .abs_section_103\r
+ _FPROT 104 1 1 0 .abs_section_104\r
+ _FSTAT 105 1 1 0 .abs_section_105\r
+ _FCMD 106 1 1 0 .abs_section_106\r
+ _ECLKDIV 110 1 1 0 .abs_section_110\r
+ _ECNFG 113 1 1 0 .abs_section_113\r
+ _EPROT 114 1 1 0 .abs_section_114\r
+ _ESTAT 115 1 1 0 .abs_section_115\r
+ _ECMD 116 1 1 0 .abs_section_116\r
+ _ATD1CTL23 122 2 2 0 .abs_section_122\r
+ _ATD1CTL45 124 2 2 0 .abs_section_124\r
+ _ATD1STAT0 126 1 1 0 .abs_section_126\r
+ _ATD1STAT1 12B 1 1 0 .abs_section_12b\r
+ _ATD1DIEN 12D 1 1 0 .abs_section_12d\r
+ _PORTAD1 12F 1 1 0 .abs_section_12f\r
+ _ATD1DR0 130 2 2 0 .abs_section_130\r
+ _ATD1DR1 132 2 2 0 .abs_section_132\r
+ _ATD1DR2 134 2 2 0 .abs_section_134\r
+ _ATD1DR3 136 2 2 0 .abs_section_136\r
+ _ATD1DR4 138 2 2 0 .abs_section_138\r
+ _ATD1DR5 13A 2 2 0 .abs_section_13a\r
+ _ATD1DR6 13C 2 2 0 .abs_section_13c\r
+ _ATD1DR7 13E 2 2 0 .abs_section_13e\r
+ _CAN0CTL0 140 1 1 0 .abs_section_140\r
+ _CAN0CTL1 141 1 1 0 .abs_section_141\r
+ _CAN0BTR0 142 1 1 0 .abs_section_142\r
+ _CAN0BTR1 143 1 1 0 .abs_section_143\r
+ _CAN0RFLG 144 1 1 0 .abs_section_144\r
+ _CAN0RIER 145 1 1 0 .abs_section_145\r
+ _CAN0TFLG 146 1 1 0 .abs_section_146\r
+ _CAN0TIER 147 1 1 0 .abs_section_147\r
+ _CAN0TARQ 148 1 1 0 .abs_section_148\r
+ _CAN0TAAK 149 1 1 0 .abs_section_149\r
+ _CAN0TBSEL 14A 1 1 0 .abs_section_14a\r
+ _CAN0IDAC 14B 1 1 0 .abs_section_14b\r
+ _CAN0RXERR 14E 1 1 0 .abs_section_14e\r
+ _CAN0TXERR 14F 1 1 0 .abs_section_14f\r
+ _CAN0IDAR0 150 1 1 0 .abs_section_150\r
+ _CAN0IDAR1 151 1 1 0 .abs_section_151\r
+ _CAN0IDAR2 152 1 1 0 .abs_section_152\r
+ _CAN0IDAR3 153 1 1 0 .abs_section_153\r
+ _CAN0IDMR0 154 1 1 0 .abs_section_154\r
+ _CAN0IDMR1 155 1 1 0 .abs_section_155\r
+ _CAN0IDMR2 156 1 1 0 .abs_section_156\r
+ _CAN0IDMR3 157 1 1 0 .abs_section_157\r
+ _CAN0IDAR4 158 1 1 0 .abs_section_158\r
+ _CAN0IDAR5 159 1 1 0 .abs_section_159\r
+ _CAN0IDAR6 15A 1 1 0 .abs_section_15a\r
+ _CAN0IDAR7 15B 1 1 0 .abs_section_15b\r
+ _CAN0IDMR4 15C 1 1 0 .abs_section_15c\r
+ _CAN0IDMR5 15D 1 1 0 .abs_section_15d\r
+ _CAN0IDMR6 15E 1 1 0 .abs_section_15e\r
+ _CAN0IDMR7 15F 1 1 0 .abs_section_15f\r
+ _CAN0RXIDR0 160 1 1 0 .abs_section_160\r
+ _CAN0RXIDR1 161 1 1 0 .abs_section_161\r
+ _CAN0RXIDR2 162 1 1 0 .abs_section_162\r
+ _CAN0RXIDR3 163 1 1 0 .abs_section_163\r
+ _CAN0RXDSR0 164 1 1 0 .abs_section_164\r
+ _CAN0RXDSR1 165 1 1 0 .abs_section_165\r
+ _CAN0RXDSR2 166 1 1 0 .abs_section_166\r
+ _CAN0RXDSR3 167 1 1 0 .abs_section_167\r
+ _CAN0RXDSR4 168 1 1 0 .abs_section_168\r
+ _CAN0RXDSR5 169 1 1 0 .abs_section_169\r
+ _CAN0RXDSR6 16A 1 1 0 .abs_section_16a\r
+ _CAN0RXDSR7 16B 1 1 0 .abs_section_16b\r
+ _CAN0RXDLR 16C 1 1 0 .abs_section_16c\r
+ _CAN0TXIDR0 170 1 1 0 .abs_section_170\r
+ _CAN0TXIDR1 171 1 1 0 .abs_section_171\r
+ _CAN0TXIDR2 172 1 1 0 .abs_section_172\r
+ _CAN0TXIDR3 173 1 1 0 .abs_section_173\r
+ _CAN0TXDSR0 174 1 1 0 .abs_section_174\r
+ _CAN0TXDSR1 175 1 1 0 .abs_section_175\r
+ _CAN0TXDSR2 176 1 1 0 .abs_section_176\r
+ _CAN0TXDSR3 177 1 1 0 .abs_section_177\r
+ _CAN0TXDSR4 178 1 1 0 .abs_section_178\r
+ _CAN0TXDSR5 179 1 1 0 .abs_section_179\r
+ _CAN0TXDSR6 17A 1 1 0 .abs_section_17a\r
+ _CAN0TXDSR7 17B 1 1 0 .abs_section_17b\r
+ _CAN0TXDLR 17C 1 1 0 .abs_section_17c\r
+ _CAN0TXTBPR 17F 1 1 0 .abs_section_17f\r
+ _CAN1CTL0 180 1 1 0 .abs_section_180\r
+ _CAN1CTL1 181 1 1 0 .abs_section_181\r
+ _CAN1BTR0 182 1 1 0 .abs_section_182\r
+ _CAN1BTR1 183 1 1 0 .abs_section_183\r
+ _CAN1RFLG 184 1 1 0 .abs_section_184\r
+ _CAN1RIER 185 1 1 0 .abs_section_185\r
+ _CAN1TFLG 186 1 1 0 .abs_section_186\r
+ _CAN1TIER 187 1 1 0 .abs_section_187\r
+ _CAN1TARQ 188 1 1 0 .abs_section_188\r
+ _CAN1TAAK 189 1 1 0 .abs_section_189\r
+ _CAN1TBSEL 18A 1 1 0 .abs_section_18a\r
+ _CAN1IDAC 18B 1 1 0 .abs_section_18b\r
+ _CAN1RXERR 18E 1 1 0 .abs_section_18e\r
+ _CAN1TXERR 18F 1 1 0 .abs_section_18f\r
+ _CAN1IDAR0 190 1 1 0 .abs_section_190\r
+ _CAN1IDAR1 191 1 1 0 .abs_section_191\r
+ _CAN1IDAR2 192 1 1 0 .abs_section_192\r
+ _CAN1IDAR3 193 1 1 0 .abs_section_193\r
+ _CAN1IDMR0 194 1 1 0 .abs_section_194\r
+ _CAN1IDMR1 195 1 1 0 .abs_section_195\r
+ _CAN1IDMR2 196 1 1 0 .abs_section_196\r
+ _CAN1IDMR3 197 1 1 0 .abs_section_197\r
+ _CAN1IDAR4 198 1 1 0 .abs_section_198\r
+ _CAN1IDAR5 199 1 1 0 .abs_section_199\r
+ _CAN1IDAR6 19A 1 1 0 .abs_section_19a\r
+ _CAN1IDAR7 19B 1 1 0 .abs_section_19b\r
+ _CAN1IDMR4 19C 1 1 0 .abs_section_19c\r
+ _CAN1IDMR5 19D 1 1 0 .abs_section_19d\r
+ _CAN1IDMR6 19E 1 1 0 .abs_section_19e\r
+ _CAN1IDMR7 19F 1 1 0 .abs_section_19f\r
+ _CAN1RXIDR0 1A0 1 1 0 .abs_section_1a0\r
+ _CAN1RXIDR1 1A1 1 1 0 .abs_section_1a1\r
+ _CAN1RXIDR2 1A2 1 1 0 .abs_section_1a2\r
+ _CAN1RXIDR3 1A3 1 1 0 .abs_section_1a3\r
+ _CAN1RXDSR0 1A4 1 1 0 .abs_section_1a4\r
+ _CAN1RXDSR1 1A5 1 1 0 .abs_section_1a5\r
+ _CAN1RXDSR2 1A6 1 1 0 .abs_section_1a6\r
+ _CAN1RXDSR3 1A7 1 1 0 .abs_section_1a7\r
+ _CAN1RXDSR4 1A8 1 1 0 .abs_section_1a8\r
+ _CAN1RXDSR5 1A9 1 1 0 .abs_section_1a9\r
+ _CAN1RXDSR6 1AA 1 1 0 .abs_section_1aa\r
+ _CAN1RXDSR7 1AB 1 1 0 .abs_section_1ab\r
+ _CAN1RXDLR 1AC 1 1 0 .abs_section_1ac\r
+ _CAN1TXIDR0 1B0 1 1 0 .abs_section_1b0\r
+ _CAN1TXIDR1 1B1 1 1 0 .abs_section_1b1\r
+ _CAN1TXIDR2 1B2 1 1 0 .abs_section_1b2\r
+ _CAN1TXIDR3 1B3 1 1 0 .abs_section_1b3\r
+ _CAN1TXDSR0 1B4 1 1 0 .abs_section_1b4\r
+ _CAN1TXDSR1 1B5 1 1 0 .abs_section_1b5\r
+ _CAN1TXDSR2 1B6 1 1 0 .abs_section_1b6\r
+ _CAN1TXDSR3 1B7 1 1 0 .abs_section_1b7\r
+ _CAN1TXDSR4 1B8 1 1 0 .abs_section_1b8\r
+ _CAN1TXDSR5 1B9 1 1 0 .abs_section_1b9\r
+ _CAN1TXDSR6 1BA 1 1 0 .abs_section_1ba\r
+ _CAN1TXDSR7 1BB 1 1 0 .abs_section_1bb\r
+ _CAN1TXDLR 1BC 1 1 0 .abs_section_1bc\r
+ _CAN1TXTBPR 1BF 1 1 0 .abs_section_1bf\r
+ _CAN2CTL0 1C0 1 1 0 .abs_section_1c0\r
+ _CAN2CTL1 1C1 1 1 0 .abs_section_1c1\r
+ _CAN2BTR0 1C2 1 1 0 .abs_section_1c2\r
+ _CAN2BTR1 1C3 1 1 0 .abs_section_1c3\r
+ _CAN2RFLG 1C4 1 1 0 .abs_section_1c4\r
+ _CAN2RIER 1C5 1 1 0 .abs_section_1c5\r
+ _CAN2TFLG 1C6 1 1 0 .abs_section_1c6\r
+ _CAN2TIER 1C7 1 1 0 .abs_section_1c7\r
+ _CAN2TARQ 1C8 1 1 0 .abs_section_1c8\r
+ _CAN2TAAK 1C9 1 1 0 .abs_section_1c9\r
+ _CAN2TBSEL 1CA 1 1 0 .abs_section_1ca\r
+ _CAN2IDAC 1CB 1 1 0 .abs_section_1cb\r
+ _CAN2RXERR 1CE 1 1 0 .abs_section_1ce\r
+ _CAN2TXERR 1CF 1 1 0 .abs_section_1cf\r
+ _CAN2IDAR0 1D0 1 1 0 .abs_section_1d0\r
+ _CAN2IDAR1 1D1 1 1 0 .abs_section_1d1\r
+ _CAN2IDAR2 1D2 1 1 0 .abs_section_1d2\r
+ _CAN2IDAR3 1D3 1 1 0 .abs_section_1d3\r
+ _CAN2IDMR0 1D4 1 1 0 .abs_section_1d4\r
+ _CAN2IDMR1 1D5 1 1 0 .abs_section_1d5\r
+ _CAN2IDMR2 1D6 1 1 0 .abs_section_1d6\r
+ _CAN2IDMR3 1D7 1 1 0 .abs_section_1d7\r
+ _CAN2IDAR4 1D8 1 1 0 .abs_section_1d8\r
+ _CAN2IDAR5 1D9 1 1 0 .abs_section_1d9\r
+ _CAN2IDAR6 1DA 1 1 0 .abs_section_1da\r
+ _CAN2IDAR7 1DB 1 1 0 .abs_section_1db\r
+ _CAN2IDMR4 1DC 1 1 0 .abs_section_1dc\r
+ _CAN2IDMR5 1DD 1 1 0 .abs_section_1dd\r
+ _CAN2IDMR6 1DE 1 1 0 .abs_section_1de\r
+ _CAN2IDMR7 1DF 1 1 0 .abs_section_1df\r
+ _CAN2RXIDR0 1E0 1 1 0 .abs_section_1e0\r
+ _CAN2RXIDR1 1E1 1 1 0 .abs_section_1e1\r
+ _CAN2RXIDR2 1E2 1 1 0 .abs_section_1e2\r
+ _CAN2RXIDR3 1E3 1 1 0 .abs_section_1e3\r
+ _CAN2RXDSR0 1E4 1 1 0 .abs_section_1e4\r
+ _CAN2RXDSR1 1E5 1 1 0 .abs_section_1e5\r
+ _CAN2RXDSR2 1E6 1 1 0 .abs_section_1e6\r
+ _CAN2RXDSR3 1E7 1 1 0 .abs_section_1e7\r
+ _CAN2RXDSR4 1E8 1 1 0 .abs_section_1e8\r
+ _CAN2RXDSR5 1E9 1 1 0 .abs_section_1e9\r
+ _CAN2RXDSR6 1EA 1 1 0 .abs_section_1ea\r
+ _CAN2RXDSR7 1EB 1 1 0 .abs_section_1eb\r
+ _CAN2RXDLR 1EC 1 1 0 .abs_section_1ec\r
+ _CAN2TXIDR0 1F0 1 1 0 .abs_section_1f0\r
+ _CAN2TXIDR1 1F1 1 1 0 .abs_section_1f1\r
+ _CAN2TXIDR2 1F2 1 1 0 .abs_section_1f2\r
+ _CAN2TXIDR3 1F3 1 1 0 .abs_section_1f3\r
+ _CAN2TXDSR0 1F4 1 1 0 .abs_section_1f4\r
+ _CAN2TXDSR1 1F5 1 1 0 .abs_section_1f5\r
+ _CAN2TXDSR2 1F6 1 1 0 .abs_section_1f6\r
+ _CAN2TXDSR3 1F7 1 1 0 .abs_section_1f7\r
+ _CAN2TXDSR4 1F8 1 1 0 .abs_section_1f8\r
+ _CAN2TXDSR5 1F9 1 1 0 .abs_section_1f9\r
+ _CAN2TXDSR6 1FA 1 1 0 .abs_section_1fa\r
+ _CAN2TXDSR7 1FB 1 1 0 .abs_section_1fb\r
+ _CAN2TXDLR 1FC 1 1 0 .abs_section_1fc\r
+ _CAN2TXTBPR 1FF 1 1 0 .abs_section_1ff\r
+ _CAN3CTL0 200 1 1 0 .abs_section_200\r
+ _CAN3CTL1 201 1 1 0 .abs_section_201\r
+ _CAN3BTR0 202 1 1 0 .abs_section_202\r
+ _CAN3BTR1 203 1 1 0 .abs_section_203\r
+ _CAN3RFLG 204 1 1 0 .abs_section_204\r
+ _CAN3RIER 205 1 1 0 .abs_section_205\r
+ _CAN3TFLG 206 1 1 0 .abs_section_206\r
+ _CAN3TIER 207 1 1 0 .abs_section_207\r
+ _CAN3TARQ 208 1 1 0 .abs_section_208\r
+ _CAN3TAAK 209 1 1 0 .abs_section_209\r
+ _CAN3TBSEL 20A 1 1 0 .abs_section_20a\r
+ _CAN3IDAC 20B 1 1 0 .abs_section_20b\r
+ _CAN3RXERR 20E 1 1 0 .abs_section_20e\r
+ _CAN3TXERR 20F 1 1 0 .abs_section_20f\r
+ _CAN3IDAR0 210 1 1 0 .abs_section_210\r
+ _CAN3IDAR1 211 1 1 0 .abs_section_211\r
+ _CAN3IDAR2 212 1 1 0 .abs_section_212\r
+ _CAN3IDAR3 213 1 1 0 .abs_section_213\r
+ _CAN3IDMR0 214 1 1 0 .abs_section_214\r
+ _CAN3IDMR1 215 1 1 0 .abs_section_215\r
+ _CAN3IDMR2 216 1 1 0 .abs_section_216\r
+ _CAN3IDMR3 217 1 1 0 .abs_section_217\r
+ _CAN3IDAR4 218 1 1 0 .abs_section_218\r
+ _CAN3IDAR5 219 1 1 0 .abs_section_219\r
+ _CAN3IDAR6 21A 1 1 0 .abs_section_21a\r
+ _CAN3IDAR7 21B 1 1 0 .abs_section_21b\r
+ _CAN3IDMR4 21C 1 1 0 .abs_section_21c\r
+ _CAN3IDMR5 21D 1 1 0 .abs_section_21d\r
+ _CAN3IDMR6 21E 1 1 0 .abs_section_21e\r
+ _CAN3IDMR7 21F 1 1 0 .abs_section_21f\r
+ _CAN3RXIDR0 220 1 1 0 .abs_section_220\r
+ _CAN3RXIDR1 221 1 1 0 .abs_section_221\r
+ _CAN3RXIDR2 222 1 1 0 .abs_section_222\r
+ _CAN3RXIDR3 223 1 1 0 .abs_section_223\r
+ _CAN3RXDSR0 224 1 1 0 .abs_section_224\r
+ _CAN3RXDSR1 225 1 1 0 .abs_section_225\r
+ _CAN3RXDSR2 226 1 1 0 .abs_section_226\r
+ _CAN3RXDSR3 227 1 1 0 .abs_section_227\r
+ _CAN3RXDSR4 228 1 1 0 .abs_section_228\r
+ _CAN3RXDSR5 229 1 1 0 .abs_section_229\r
+ _CAN3RXDSR6 22A 1 1 0 .abs_section_22a\r
+ _CAN3RXDSR7 22B 1 1 0 .abs_section_22b\r
+ _CAN3RXDLR 22C 1 1 0 .abs_section_22c\r
+ _CAN3TXIDR0 230 1 1 0 .abs_section_230\r
+ _CAN3TXIDR1 231 1 1 0 .abs_section_231\r
+ _CAN3TXIDR2 232 1 1 0 .abs_section_232\r
+ _CAN3TXIDR3 233 1 1 0 .abs_section_233\r
+ _CAN3TXDSR0 234 1 1 0 .abs_section_234\r
+ _CAN3TXDSR1 235 1 1 0 .abs_section_235\r
+ _CAN3TXDSR2 236 1 1 0 .abs_section_236\r
+ _CAN3TXDSR3 237 1 1 0 .abs_section_237\r
+ _CAN3TXDSR4 238 1 1 0 .abs_section_238\r
+ _CAN3TXDSR5 239 1 1 0 .abs_section_239\r
+ _CAN3TXDSR6 23A 1 1 0 .abs_section_23a\r
+ _CAN3TXDSR7 23B 1 1 0 .abs_section_23b\r
+ _CAN3TXDLR 23C 1 1 0 .abs_section_23c\r
+ _CAN3TXTBPR 23F 1 1 0 .abs_section_23f\r
+ _PTT 240 1 1 0 .abs_section_240\r
+ _PTIT 241 1 1 0 .abs_section_241\r
+ _DDRT 242 1 1 0 .abs_section_242\r
+ _RDRT 243 1 1 0 .abs_section_243\r
+ _PERT 244 1 1 0 .abs_section_244\r
+ _PPST 245 1 1 0 .abs_section_245\r
+ _PTS 248 1 1 1 .abs_section_248\r
+ _PTIS 249 1 1 0 .abs_section_249\r
+ _DDRS 24A 1 1 2 .abs_section_24a\r
+ _RDRS 24B 1 1 0 .abs_section_24b\r
+ _PERS 24C 1 1 0 .abs_section_24c\r
+ _PPSS 24D 1 1 0 .abs_section_24d\r
+ _WOMS 24E 1 1 0 .abs_section_24e\r
+ _PTM 250 1 1 0 .abs_section_250\r
+ _PTIM 251 1 1 0 .abs_section_251\r
+ _DDRM 252 1 1 0 .abs_section_252\r
+ _RDRM 253 1 1 0 .abs_section_253\r
+ _PERM 254 1 1 0 .abs_section_254\r
+ _PPSM 255 1 1 0 .abs_section_255\r
+ _WOMM 256 1 1 0 .abs_section_256\r
+ _MODRR 257 1 1 0 .abs_section_257\r
+ _PTP 258 1 1 0 .abs_section_258\r
+ _PTIP 259 1 1 0 .abs_section_259\r
+ _DDRP 25A 1 1 0 .abs_section_25a\r
+ _RDRP 25B 1 1 0 .abs_section_25b\r
+ _PERP 25C 1 1 0 .abs_section_25c\r
+ _PPSP 25D 1 1 0 .abs_section_25d\r
+ _PIEP 25E 1 1 0 .abs_section_25e\r
+ _PIFP 25F 1 1 0 .abs_section_25f\r
+ _PTH 260 1 1 0 .abs_section_260\r
+ _PTIH 261 1 1 0 .abs_section_261\r
+ _DDRH 262 1 1 0 .abs_section_262\r
+ _RDRH 263 1 1 0 .abs_section_263\r
+ _PERH 264 1 1 0 .abs_section_264\r
+ _PPSH 265 1 1 0 .abs_section_265\r
+ _PIEH 266 1 1 0 .abs_section_266\r
+ _PIFH 267 1 1 0 .abs_section_267\r
+ _PTJ 268 1 1 0 .abs_section_268\r
+ _PTIJ 269 1 1 0 .abs_section_269\r
+ _DDRJ 26A 1 1 0 .abs_section_26a\r
+ _RDRJ 26B 1 1 0 .abs_section_26b\r
+ _PERJ 26C 1 1 0 .abs_section_26c\r
+ _PPSJ 26D 1 1 0 .abs_section_26d\r
+ _PIEJ 26E 1 1 0 .abs_section_26e\r
+ _PIFJ 26F 1 1 0 .abs_section_26f\r
+ _CAN4CTL0 280 1 1 0 .abs_section_280\r
+ _CAN4CTL1 281 1 1 0 .abs_section_281\r
+ _CAN4BTR0 282 1 1 0 .abs_section_282\r
+ _CAN4BTR1 283 1 1 0 .abs_section_283\r
+ _CAN4RFLG 284 1 1 0 .abs_section_284\r
+ _CAN4RIER 285 1 1 0 .abs_section_285\r
+ _CAN4TFLG 286 1 1 0 .abs_section_286\r
+ _CAN4TIER 287 1 1 0 .abs_section_287\r
+ _CAN4TARQ 288 1 1 0 .abs_section_288\r
+ _CAN4TAAK 289 1 1 0 .abs_section_289\r
+ _CAN4TBSEL 28A 1 1 0 .abs_section_28a\r
+ _CAN4IDAC 28B 1 1 0 .abs_section_28b\r
+ _CAN4RXERR 28E 1 1 0 .abs_section_28e\r
+ _CAN4TXERR 28F 1 1 0 .abs_section_28f\r
+ _CAN4IDAR0 290 1 1 0 .abs_section_290\r
+ _CAN4IDAR1 291 1 1 0 .abs_section_291\r
+ _CAN4IDAR2 292 1 1 0 .abs_section_292\r
+ _CAN4IDAR3 293 1 1 0 .abs_section_293\r
+ _CAN4IDMR0 294 1 1 0 .abs_section_294\r
+ _CAN4IDMR1 295 1 1 0 .abs_section_295\r
+ _CAN4IDMR2 296 1 1 0 .abs_section_296\r
+ _CAN4IDMR3 297 1 1 0 .abs_section_297\r
+ _CAN4IDAR4 298 1 1 0 .abs_section_298\r
+ _CAN4IDAR5 299 1 1 0 .abs_section_299\r
+ _CAN4IDAR6 29A 1 1 0 .abs_section_29a\r
+ _CAN4IDAR7 29B 1 1 0 .abs_section_29b\r
+ _CAN4IDMR4 29C 1 1 0 .abs_section_29c\r
+ _CAN4IDMR5 29D 1 1 0 .abs_section_29d\r
+ _CAN4IDMR6 29E 1 1 0 .abs_section_29e\r
+ _CAN4IDMR7 29F 1 1 0 .abs_section_29f\r
+ _CAN4RXIDR0 2A0 1 1 0 .abs_section_2a0\r
+ _CAN4RXIDR1 2A1 1 1 0 .abs_section_2a1\r
+ _CAN4RXIDR2 2A2 1 1 0 .abs_section_2a2\r
+ _CAN4RXIDR3 2A3 1 1 0 .abs_section_2a3\r
+ _CAN4RXDSR0 2A4 1 1 0 .abs_section_2a4\r
+ _CAN4RXDSR1 2A5 1 1 0 .abs_section_2a5\r
+ _CAN4RXDSR2 2A6 1 1 0 .abs_section_2a6\r
+ _CAN4RXDSR3 2A7 1 1 0 .abs_section_2a7\r
+ _CAN4RXDSR4 2A8 1 1 0 .abs_section_2a8\r
+ _CAN4RXDSR5 2A9 1 1 0 .abs_section_2a9\r
+ _CAN4RXDSR6 2AA 1 1 0 .abs_section_2aa\r
+ _CAN4RXDSR7 2AB 1 1 0 .abs_section_2ab\r
+ _CAN4RXDLR 2AC 1 1 0 .abs_section_2ac\r
+ _CAN4TXIDR0 2B0 1 1 0 .abs_section_2b0\r
+ _CAN4TXIDR1 2B1 1 1 0 .abs_section_2b1\r
+ _CAN4TXIDR2 2B2 1 1 0 .abs_section_2b2\r
+ _CAN4TXIDR3 2B3 1 1 0 .abs_section_2b3\r
+ _CAN4TXDSR0 2B4 1 1 0 .abs_section_2b4\r
+ _CAN4TXDSR1 2B5 1 1 0 .abs_section_2b5\r
+ _CAN4TXDSR2 2B6 1 1 0 .abs_section_2b6\r
+ _CAN4TXDSR3 2B7 1 1 0 .abs_section_2b7\r
+ _CAN4TXDSR4 2B8 1 1 0 .abs_section_2b8\r
+ _CAN4TXDSR5 2B9 1 1 0 .abs_section_2b9\r
+ _CAN4TXDSR6 2BA 1 1 0 .abs_section_2ba\r
+ _CAN4TXDSR7 2BB 1 1 0 .abs_section_2bb\r
+ _CAN4TXDLR 2BC 1 1 0 .abs_section_2bc\r
+ _CAN4TXTBPR 2BF 1 1 0 .abs_section_2bf\r
+ uxCriticalNesting 1000 1 1 101 .data \r
+ xLocalError 1001 1 1 2 .bss \r
+ xRxedChars 1002 2 2 3 .bss \r
+ xCharsForTx 1004 2 2 3 .bss \r
+ pxCurrentTCB 1006 2 2 28 .bss \r
+ uxTasksDeleted 1008 1 1 3 .bss \r
+ uxCurrentNumberOfTasks 1009 1 1 5 .bss \r
+ xTickCount 100A 2 2 14 .bss \r
+ uxTopUsedPriority 100C 1 1 2 .bss \r
+ uxTopReadyPriority 100D 1 1 15 .bss \r
+ xSchedulerRunning 100E 1 1 3 .bss \r
+ uxSchedulerSuspended 100F 1 1 6 .bss \r
+ uxMissedTicks 1010 1 1 4 .bss \r
+ uxTaskNumber.1 1011 1 1 2 .bss \r
+ pxReadyTasksLists 1012 3C 60 11 .bss \r
+ xDelayedTaskList1 104E F 15 2 .bss \r
+ xDelayedTaskList2 105D F 15 2 .bss \r
+ pxDelayedTaskList 106C 2 2 8 .bss \r
+ pxOverflowDelayedTaskList 106E 2 2 6 .bss \r
+ xPendingReadyList 1070 F 15 4 .bss \r
+ xTasksWaitingTermination 107F F 15 5 .bss \r
+ xSuspendedTaskList 108E F 15 2 .bss \r
+ xHeapHasBeenInitialised.1 109D 1 1 2 .bss \r
+ xHeap 109E 2804 10244 2 .bss \r
+ xStart 38A2 4 4 6 .bss \r
+ xEnd 38A6 4 4 4 .bss \r
+ uxFlashTaskNumber 38AA 1 1 2 .bss \r
+ usCheckVariable 38AB 2 2 3 .bss \r
+ xSuspendedQueueSendError 38AD 1 1 2 .bss \r
+ xSuspendedQueueReceiveError 38AE 1 1 3 .bss \r
+ ulValueToSend.6 38AF 4 4 5 .bss \r
+ ulExpectedValue.7 38B3 4 4 6 .bss \r
+ usLastTaskCheck.9 38B7 2 2 2 .bss \r
+ xContinousIncrementHandle 38B9 2 2 5 .bss \r
+ xLimitedIncrementHandle 38BB 2 2 2 .bss \r
+ ulCounter 38BD 4 4 10 .bss \r
+ ulReceivedValue.8 38C1 4 4 3 .bss \r
+ xPollingConsumerCount 38C5 1 1 3 .bss \r
+ xPollingProducerCount 38C6 1 1 3 .bss \r
+ xPolledQueue.1 38C7 2 2 3 .bss \r
+ xPort 38C9 2 2 3 .bss \r
+ uxBaseLED 38CB 1 1 5 .bss \r
+ uxRxLoops 38CC 1 1 3 .bss \r
+ xTaskCheck 38CD 1 1 3 .bss \r
+ sBlockingConsumerCount 38CE 6 6 4 .bss \r
+ sBlockingProducerCount 38D4 6 6 5 .bss \r
+ sLastBlockingConsumerCount.7 38DA 6 6 2 .bss \r
+ sLastBlockingProducerCount.8 38E0 6 6 2 .bss \r
+ usCreationCount 38E6 2 2 4 .bss \r
+ uxTasksRunningAtStart 38E8 1 1 4 .bss \r
+ usLastCreationCount.6 38E9 2 2 2 .bss \r
+ uxTasksRunningNow.7 38EB 1 1 1 .bss \r
+ xSuspendedTestQueue 38EC 2 2 3 .common \r
+ xCreatedTask1 38EE 2 2 2 .common \r
+ xCreatedTask2 38F0 2 2 2 .common \r
+ CmpHighVal 38F2 2 2 2 TickTimer_DATA\r
+ Byte1_Table 38F4 8 8 2 Byte1_DATA \r
+ COM0_PrescHigh.1 38FC 8 8 1 COM0_DATA \r
+ SerFlag 3904 2 2 1 COM0_DATA \r
+ PrescHigh 3906 2 2 2 COM0_DATA \r
+ NumMode 3908 1 1 2 COM0_DATA \r
+ _EntryPoint C000 2E 46 1 .init \r
+ PE_low_level_init C02E 4E 78 2 .init \r
+ STRING.Check.1 C09A 6 6 1 .rodata1 \r
+ STRING.IDLE.2 C0A0 5 5 1 .rodata1 \r
+ STRING.LEDx.1 C0A5 5 5 1 .rodata1 \r
+ STRING.CNT_INC.1 C0AA 8 8 1 .rodata1 \r
+ STRING.LIM_INC.2 C0B2 8 8 1 .rodata1 \r
+ STRING.C_CTRL.3 C0BA 7 7 1 .rodata1 \r
+ STRING.SUSP_TX.4 C0C1 8 8 1 .rodata1 \r
+ STRING.SUSP_RX.5 C0C9 8 8 1 .rodata1 \r
+ STRING.QConsNB.2 C0D1 8 8 1 .rodata1 \r
+ STRING.QProdNB.3 C0D9 8 8 1 .rodata1 \r
+ STRING.COMTx.1 C0E1 6 6 1 .rodata1 \r
+ STRING.COMRx.2 C0E7 6 6 1 .rodata1 \r
+ STRING.IntMath.1 C0ED 8 8 1 .rodata1 \r
+ STRING.QConsB1.1 C0F5 8 8 1 .rodata1 \r
+ STRING.QProdB2.2 C0FD 8 8 1 .rodata1 \r
+ STRING.QProdB3.3 C105 8 8 1 .rodata1 \r
+ STRING.QConsB4.4 C10D 8 8 1 .rodata1 \r
+ STRING.QProdB5.5 C115 8 8 1 .rodata1 \r
+ STRING.QConsB6.6 C11D 8 8 1 .rodata1 \r
+ STRING.CREATOR.1 C125 8 8 1 .rodata1 \r
+ STRING.SUICIDE1.2 C12D 9 9 1 .rodata1 \r
+ STRING.SUICIDE2.3 C136 9 9 1 .rodata1 \r
+ STRING.SUICIDE1.4 C13F 9 9 1 .rodata1 \r
+ STRING.SUICIDE2.5 C148 9 9 1 .rodata1 \r
+ _Startup C151 12 18 1 NON_BANKED \r
+ _LCMP C163 19 25 2 NON_BANKED \r
+ _LCMP_P C17C 15 21 3 NON_BANKED \r
+ _LNEG C191 D 13 2 NON_BANKED \r
+ _LINC C19E 5 5 4 NON_BANKED \r
+ _LMUL C1A3 27 39 1 NON_BANKED \r
+ _lDivMod C1CA E3 227 3 NON_BANKED \r
+ _LDIVU C2AD E 14 1 NON_BANKED \r
+ _NEG_P C2BB F 15 4 NON_BANKED \r
+ _LDIVS C2CA 35 53 2 NON_BANKED \r
+ Cpu_Interrupt C2FF 1 1 60 NON_BANKED \r
+ vCOM0_ISR C300 59 89 1 NON_BANKED \r
+ xBankedStartScheduler C359 1A 26 1 NON_BANKED \r
+ vPortYield C373 1D 29 1 NON_BANKED \r
+ vPortTickInterrupt C390 25 37 1 NON_BANKED \r
+ _BDMSTS FF01 1 1 0 .abs_section_ff01\r
+ _BDMCCR FF06 1 1 0 .abs_section_ff06\r
+ _BDMINR FF07 1 1 0 .abs_section_ff07\r
+ _vect FF80 80 128 0 .abs_section_ff80\r
+ Init 308000 29 41 2 .text \r
+ memcpy 308029 26 38 8 .text \r
+ memset 30804F 1E 30 2 .text \r
+ strncpy 30806D 2D 45 2 .text \r
+ main 30809A 9 9 0 .text \r
+ vMain 3080A3 52 82 1 .text \r
+ vErrorChecks 3080F5 39 57 3 .text \r
+ prvCheckOtherTasksAreStillRunning 30812E 50 80 2 .text \r
+ vApplicationIdleHook 30817E 70 112 2 .text \r
+ vParTestSetLED 3081EE 23 35 4 .text \r
+ vParTestToggleLED 308211 14 20 10 .text \r
+ xSerialPortInitMinimal 308225 26 38 2 .text \r
+ xSerialGetChar 318000 13 19 4 ROM_PAGE31_524\r
+ xSerialPutChar 318013 18 24 2 ROM_PAGE31_524\r
+ xTaskCreate 31802B D5 213 48 ROM_PAGE31_524\r
+ vTaskDelete 318100 4A 74 4 ROM_PAGE31_524\r
+ vTaskDelayUntil 31814A 77 119 6 ROM_PAGE31_524\r
+ vTaskDelay 3181C1 46 70 16 ROM_PAGE31_524\r
+ uxTaskPriorityGet 318207 22 34 2 ROM_PAGE31_524\r
+ vTaskPrioritySet 328000 69 105 4 ROM_PAGE32_525\r
+ vTaskSuspend 328069 47 71 6 ROM_PAGE32_525\r
+ vTaskResume 3280B0 5C 92 6 ROM_PAGE32_525\r
+ vTaskStartScheduler 32810C 31 49 2 ROM_PAGE32_525\r
+ vTaskSuspendAll 32813D 13 19 26 ROM_PAGE32_525\r
+ xTaskResumeAll 328150 9F 159 30 ROM_PAGE32_525\r
+ xTaskGetTickCount 3281EF 17 23 6 ROM_PAGE32_525\r
+ uxTaskGetNumberOfTasks 328206 17 23 4 ROM_PAGE32_525\r
+ vTaskIncrementTick 338000 84 132 4 ROM_PAGE33_526\r
+ vTaskSwitchContext 338084 5B 91 4 ROM_PAGE33_526\r
+ vTaskPlaceOnEventList 3380DF 41 65 4 ROM_PAGE33_526\r
+ xTaskRemoveFromEventList 338120 69 105 8 ROM_PAGE33_526\r
+ prvIdleTask 338189 12 18 3 ROM_PAGE33_526\r
+ prvInitialiseTCBVariables 33819B 4D 77 2 ROM_PAGE33_526\r
+ prvInitialiseTaskLists 3381E8 3C 60 2 ROM_PAGE33_526\r
+ prvCheckTasksWaitingTermination 348000 53 83 2 ROM_PAGE34_527\r
+ prvAllocateTCBAndStack 348053 3D 61 2 ROM_PAGE34_527\r
+ prvDeleteTCB 348090 F 15 2 ROM_PAGE34_527\r
+ xQueueCreate 34809F 7B 123 14 ROM_PAGE34_527\r
+ xQueueSend 34811A D4 212 9 ROM_PAGE34_527\r
+ xQueueSendFromISR 3481EE 5D 93 2 ROM_PAGE34_527\r
+ xQueueReceive 358000 CF 207 9 ROM_PAGE35_528\r
+ xQueueReceiveFromISR 3580CF 61 97 2 ROM_PAGE35_528\r
+ uxQueueMessagesWaiting 358130 1B 27 2 ROM_PAGE35_528\r
+ prvUnlockQueue 35814B 71 113 8 ROM_PAGE35_528\r
+ prvIsQueueEmpty 3581BC 22 34 2 ROM_PAGE35_528\r
+ prvIsQueueFull 3581DE 25 37 2 ROM_PAGE35_528\r
+ vListInitialise 358203 20 32 6 ROM_PAGE35_528\r
+ vListInitialiseItem 358223 7 7 6 ROM_PAGE35_528\r
+ vListInsertEnd 35822A 25 37 16 ROM_PAGE35_528\r
+ vListInsert 368000 55 85 8 ROM_PAGE36_529\r
+ vListRemove 368055 23 35 32 ROM_PAGE36_529\r
+ pvPortMalloc 368078 C1 193 14 ROM_PAGE36_529\r
+ vPortFree 368139 3B 59 10 ROM_PAGE36_529\r
+ vStartLEDFlashTasks 368174 32 50 2 ROM_PAGE36_529\r
+ vLEDFlashTask 3681A6 57 87 3 ROM_PAGE36_529\r
+ vStartDynamicPriorityTasks 378000 9B 155 2 ROM_PAGE37_530\r
+ vLimitedIncrementTask 37809B 27 39 3 ROM_PAGE37_530\r
+ vContinuousIncrementTask 3780C2 38 56 3 ROM_PAGE37_530\r
+ vCounterControlTask 3780FA A0 160 5 ROM_PAGE37_530\r
+ vQueueSendWhenSuspendedTask 37819A 38 56 3 ROM_PAGE37_530\r
+ vQueueReceiveWhenSuspendedTask 3781D2 54 84 3 ROM_PAGE37_530\r
+ xAreDynamicPriorityTasksStillRunning 378226 2B 43 2 ROM_PAGE37_530\r
+ vStartPolledQueueTasks 388000 4B 75 2 ROM_PAGE38_531\r
+ vPolledQueueProducer 38804B 4F 79 3 ROM_PAGE38_531\r
+ vPolledQueueConsumer 38809A 5C 92 3 ROM_PAGE38_531\r
+ xArePollingQueuesStillRunning 3880F6 16 22 2 ROM_PAGE38_531\r
+ PE_Timer_LngHi1 38810C 4A 74 2 ROM_PAGE38_531\r
+ vAltStartComTestTasks 388156 4D 77 2 ROM_PAGE38_531\r
+ vComTxTask 3881A3 4F 79 3 ROM_PAGE38_531\r
+ vComRxTask 398000 7B 123 3 ROM_PAGE39_532\r
+ xAreComTestTasksStillRunning 39807B D 13 2 ROM_PAGE39_532\r
+ pxPortInitialiseStack 398088 31 49 2 ROM_PAGE39_532\r
+ xPortStartScheduler 3980B9 4 4 2 ROM_PAGE39_532\r
+ vStartIntegerMathTasks 3980BD 33 51 2 ROM_PAGE39_532\r
+ vCompeteingIntMathTask 3980F0 87 135 3 ROM_PAGE39_532\r
+ xAreIntegerMathsTaskStillRunning 398177 20 32 2 ROM_PAGE39_532\r
+ vStartBlockingQueueTasks 3A8000 143 323 7 ROM_PAGE3A_533\r
+ vBlockingQueueProducer 3A8143 3F 63 9 ROM_PAGE3A_533\r
+ vBlockingQueueConsumer 3A8182 47 71 9 ROM_PAGE3A_533\r
+ xAreBlockingQueuesStillRunning 3A81C9 52 82 2 ROM_PAGE3A_533\r
+ vCreateSuicidalTasks 3A821B 31 49 2 ROM_PAGE3A_533\r
+ vSuicidalTask 3B8000 58 88 12 ROM_PAGE3B_534\r
+ vCreateTasks 3B8058 92 146 4 ROM_PAGE3B_534\r
+ xIsCreateTaskStillRunning 3B80EA 3A 58 2 ROM_PAGE3B_534\r
+ TickTimer_Enable 3B8124 9 9 2 TickTimer_CODE\r
+ TickTimer_SetFreqHz 3B812D 56 86 2 TickTimer_CODE\r
+ TickTimer_Init 3B8183 1C 28 2 TickTimer_CODE\r
+ Byte1_PutBit 3B819F 21 33 2 Byte1_CODE \r
+ Byte1_NegBit 3B81C0 14 20 2 Byte1_CODE \r
+ COM0_SetBaudRateMode 3B81D4 19 25 2 COM0_CODE \r
+ COM0_Init 3B81ED 25 37 2 COM0_CODE \r
+\r
+*********************************************************************************************\r
+UNUSED-OBJECTS SECTION\r
+---------------------------------------------------------------------------------------------\r
+NOT USED PROCEDURES\r
+STRING.C.o (ansibi.lib):\r
+ strerror memchr memcmp memcpy2 _memcpy_8bitCount memmove \r
+ _memset_clear_8bitCount strlen strset strcat strncat strcpy strcmp strncmp \r
+ strchr strrchr strspn strcspn strpbrk strstr strtok strcoll strxfrm \r
+rtshc12.c.o (ansibi.lib):\r
+ _BSHL _BSHRS _BSHRU _BDIVMODU _BDIVMODS _ISHL _ISHRU _ISHRS _LSHL _LSHRU \r
+ _LSHRS _LADD _LSUB _LAND _LOR _LXOR _LCMP_PP _LABS _LCOM _LDEC _LMODU _LMODS \r
+ _ILSEXT _LTEST _COPY _CASE_DIRECT _CASE_DIRECT_BYTE _CASE_CHECKED \r
+ _CASE_CHECKED_BYTE _CASE_SEARCH _CASE_SEARCH_BYTE _CASE_SEARCH_8 \r
+ _CASE_SEARCH_8_BYTE _FCALL _FPCMP \r
+serial.c.o:\r
+ vSerialClose \r
+tasks.c.o:\r
+ vTaskEndScheduler \r
+queue.c.o:\r
+ vQueueDelete \r
+TickTimer.C.o:\r
+ TickTimer_Interrupt SetCV SetPV HWEnDi TickTimer_SetPeriodTicks16 \r
+ TickTimer_SetPeriodTicks32 TickTimer_SetPeriodUS TickTimer_SetPeriodMS \r
+Byte1.C.o:\r
+ Byte1_GetMsk \r
+PE_Timer.C.o:\r
+ PE_Timer_LngMul PE_Timer_LngHi2 PE_Timer_LngHi3 PE_Timer_LngHi4 \r
+COM0.C.o:\r
+ HWEnDi \r
+port.c.o:\r
+ vPortEndScheduler prvSetupTimerInterrupt \r
+NOT USED VARIABLES\r
+STRING.C.o (ansibi.lib):\r
+ STRING..1 next.2 \r
+rtshc12.c.o (ansibi.lib):\r
+ _PowOfTwo_8 _PowOfTwo_16 _PowOfTwo_32 \r
+Cpu.C.o:\r
+ CpuMode CCR_reg \r
+heap_2.c.o:\r
+ heapSTRUCT_SIZE \r
+death.c.o:\r
+ uxMaxNumberOfExtraTasksRunning \r
+\r
+*********************************************************************************************\r
+COPYDOWN SECTION\r
+---------------------------------------------------------------------------------------------\r
+------- ROM-ADDRESS: 0xC3B5 ---- SIZE 4 ---\r
+Filling bytes inserted\r
+ 00011000\r
+------- ROM-ADDRESS: 0xC3B9 ---- RAM-ADDRESS: 0x1000 ---- SIZE 1 ---\r
+Name of initialized Object : uxCriticalNesting\r
+ FF\r
+------- ROM-ADDRESS: 0xC3BA ---- SIZE 4 ---\r
+Filling bytes inserted\r
+ 001038F4\r
+------- ROM-ADDRESS: 0xC3BE ---- RAM-ADDRESS: 0x38F4 ---- SIZE 8 ---\r
+Name of initialized Object : Byte1_Table\r
+ 0102040810 204080\r
+------- ROM-ADDRESS: 0xC3C6 ---- SIZE 1 ---\r
+Filling bytes inserted\r
+ 00\r
+------- ROM-ADDRESS: 0xC3C7 ---- RAM-ADDRESS: 0x38FD ---- SIZE 7 ---\r
+Name of initialized Object : COM0_PrescHigh.1:1\r
+ 29005100A3 0146\r
+------- ROM-ADDRESS: 0xC3CE ---- SIZE 2 ---\r
+Filling bytes inserted\r
+ 0000\r
+\r
+*********************************************************************************************\r
+OBJECT-DEPENDENCIES SECTION\r
+---------------------------------------------------------------------------------------------\r
+_EntryPoint USES _INITRM _INITEE _MISC _CLKSEL _PLLCTL _SYNR \r
+ _REFDV _CRGFLG _Startup \r
+PE_low_level_init USES _TSCR1 _TCTL2 _TCTL1 _TIE _TTOV _TSCR2 _TIOS \r
+ _PWMCTL _PWMSDN _ICSYS _MCCTL TickTimer_Init _PORTAB \r
+ _DDRAB _DDRS _PTS COM0_Init _INTCR \r
+_Startup USES _startupData Init \r
+_LDIVU USES _lDivMod \r
+_LDIVS USES _NEG_P _lDivMod \r
+vCOM0_ISR USES _SCI0SR1 _SCI0DRL xRxedChars xQueueSendFromISR \r
+ _SCI0CR2 xCharsForTx xQueueReceiveFromISR \r
+xBankedStartScheduler USES TickTimer_SetFreqHz TickTimer_Enable \r
+ pxCurrentTCB uxCriticalNesting \r
+vPortYield USES uxCriticalNesting pxCurrentTCB \r
+ vTaskSwitchContext \r
+vPortTickInterrupt USES uxCriticalNesting pxCurrentTCB \r
+ vTaskIncrementTick vTaskSwitchContext _TFLG1 \r
+_vect USES Cpu_Interrupt vCOM0_ISR vPortTickInterrupt \r
+ vPortYield _EntryPoint \r
+Init USES _startupData \r
+main USES PE_low_level_init vMain \r
+vMain USES vStartLEDFlashTasks vStartPolledQueueTasks \r
+ vStartDynamicPriorityTasks vAltStartComTestTasks vStartBlockingQueueTasks \r
+ vStartIntegerMathTasks vCreateSuicidalTasks vErrorChecks \r
+ STRING.Check.1 xTaskCreate vTaskStartScheduler \r
+vErrorChecks USES xTaskGetTickCount vTaskDelayUntil \r
+ prvCheckOtherTasksAreStillRunning _LCMP vParTestToggleLED \r
+prvCheckOtherTasksAreStillRunning USES xArePollingQueuesStillRunning \r
+ xAreDynamicPriorityTasksStillRunning xAreComTestTasksStillRunning \r
+ xAreIntegerMathsTaskStillRunning xAreBlockingQueuesStillRunning \r
+ xIsCreateTaskStillRunning xLocalError \r
+vApplicationIdleHook USES _LNEG _LDIVS _LCMP_P uxCriticalNesting \r
+ xLocalError \r
+vParTestSetLED USES uxCriticalNesting Byte1_PutBit \r
+vParTestToggleLED USES uxCriticalNesting Byte1_NegBit \r
+xSerialPortInitMinimal USES xQueueCreate xRxedChars xCharsForTx \r
+ COM0_SetBaudRateMode \r
+xSerialGetChar USES xRxedChars xQueueReceive \r
+xSerialPutChar USES xCharsForTx xQueueSend _SCI0CR2 \r
+xTaskCreate USES prvAllocateTCBAndStack \r
+ prvInitialiseTCBVariables pxPortInitialiseStack uxCriticalNesting \r
+ uxCurrentNumberOfTasks pxCurrentTCB prvInitialiseTaskLists \r
+ xSchedulerRunning uxTopUsedPriority uxTaskNumber.1 \r
+ uxTopReadyPriority pxReadyTasksLists vListInsertEnd \r
+vTaskDelete USES uxCriticalNesting pxCurrentTCB vListRemove \r
+ xTasksWaitingTermination vListInsertEnd uxTasksDeleted \r
+vTaskDelayUntil USES vTaskSuspendAll xTickCount pxCurrentTCB \r
+ vListRemove pxOverflowDelayedTaskList pxDelayedTaskList \r
+ vListInsert xTaskResumeAll \r
+vTaskDelay USES vTaskSuspendAll xTickCount pxCurrentTCB \r
+ vListRemove pxOverflowDelayedTaskList pxDelayedTaskList \r
+ vListInsert xTaskResumeAll \r
+uxTaskPriorityGet USES uxCriticalNesting pxCurrentTCB \r
+vTaskPrioritySet USES uxCriticalNesting pxCurrentTCB \r
+ pxReadyTasksLists vListRemove uxTopReadyPriority vListInsertEnd \r
+vTaskSuspend USES uxCriticalNesting pxCurrentTCB vListRemove \r
+ xSuspendedTaskList vListInsertEnd \r
+vTaskResume USES uxCriticalNesting pxCurrentTCB vListRemove \r
+ uxTopReadyPriority pxReadyTasksLists vListInsertEnd \r
+vTaskStartScheduler USES pxCurrentTCB prvIdleTask STRING.IDLE.2 \r
+ xTaskCreate xSchedulerRunning xTickCount \r
+ xPortStartScheduler \r
+vTaskSuspendAll USES uxCriticalNesting uxSchedulerSuspended \r
+xTaskResumeAll USES uxCriticalNesting uxSchedulerSuspended \r
+ uxCurrentNumberOfTasks vListRemove uxTopReadyPriority \r
+ pxReadyTasksLists vListInsertEnd pxCurrentTCB xPendingReadyList \r
+ uxMissedTicks vTaskIncrementTick \r
+xTaskGetTickCount USES uxCriticalNesting xTickCount \r
+uxTaskGetNumberOfTasks USES uxCriticalNesting uxCurrentNumberOfTasks \r
+vTaskIncrementTick USES uxSchedulerSuspended xTickCount \r
+ pxDelayedTaskList pxOverflowDelayedTaskList vListRemove \r
+ uxTopReadyPriority pxReadyTasksLists vListInsertEnd uxMissedTicks \r
+vTaskSwitchContext USES uxSchedulerSuspended uxTopReadyPriority \r
+ pxCurrentTCB pxReadyTasksLists \r
+vTaskPlaceOnEventList USES pxCurrentTCB vListInsert xTickCount vListRemove \r
+ pxOverflowDelayedTaskList pxDelayedTaskList \r
+xTaskRemoveFromEventList USES vListRemove uxSchedulerSuspended \r
+ uxTopReadyPriority pxReadyTasksLists xPendingReadyList \r
+ vListInsertEnd pxCurrentTCB \r
+prvIdleTask USES prvCheckTasksWaitingTermination \r
+ pxReadyTasksLists vApplicationIdleHook \r
+prvInitialiseTCBVariables USES strncpy vListInitialiseItem \r
+prvInitialiseTaskLists USES pxReadyTasksLists xDelayedTaskList1 \r
+ xDelayedTaskList2 xPendingReadyList xTasksWaitingTermination \r
+ xSuspendedTaskList pxDelayedTaskList pxOverflowDelayedTaskList \r
+ vListInitialise \r
+prvCheckTasksWaitingTermination USES uxTasksDeleted vTaskSuspendAll \r
+ xTasksWaitingTermination xTaskResumeAll uxCriticalNesting vListRemove \r
+ uxCurrentNumberOfTasks prvDeleteTCB \r
+prvAllocateTCBAndStack USES pvPortMalloc vPortFree memset \r
+prvDeleteTCB USES vPortFree \r
+xQueueCreate USES pvPortMalloc vListInitialise vPortFree \r
+xQueueSend USES vTaskSuspendAll uxCriticalNesting xQueueSend \r
+ prvIsQueueFull vTaskPlaceOnEventList prvUnlockQueue \r
+ xTaskResumeAll memcpy \r
+xQueueSendFromISR USES memcpy xTaskRemoveFromEventList \r
+xQueueReceive USES vTaskSuspendAll uxCriticalNesting xQueueReceive \r
+ prvIsQueueEmpty vTaskPlaceOnEventList prvUnlockQueue \r
+ xTaskResumeAll memcpy \r
+xQueueReceiveFromISR USES memcpy xTaskRemoveFromEventList \r
+uxQueueMessagesWaiting USES uxCriticalNesting \r
+prvUnlockQueue USES uxCriticalNesting xTaskRemoveFromEventList \r
+prvIsQueueEmpty USES uxCriticalNesting \r
+prvIsQueueFull USES uxCriticalNesting \r
+vListInitialise USES vListInitialiseItem \r
+pvPortMalloc USES vTaskSuspendAll xHeapHasBeenInitialised.1 xHeap \r
+ xStart xEnd xTaskResumeAll \r
+vPortFree USES vTaskSuspendAll xStart xTaskResumeAll \r
+vStartLEDFlashTasks USES vLEDFlashTask STRING.LEDx.1 xTaskCreate \r
+vLEDFlashTask USES uxCriticalNesting uxFlashTaskNumber \r
+ xTaskGetTickCount vTaskDelayUntil vParTestToggleLED \r
+vStartDynamicPriorityTasks USES xQueueCreate xSuspendedTestQueue \r
+ vContinuousIncrementTask STRING.CNT_INC.1 ulCounter \r
+ xContinousIncrementHandle xTaskCreate vLimitedIncrementTask \r
+ STRING.LIM_INC.2 xLimitedIncrementHandle vCounterControlTask \r
+ STRING.C_CTRL.3 vQueueSendWhenSuspendedTask STRING.SUSP_TX.4 \r
+ vQueueReceiveWhenSuspendedTask STRING.SUSP_RX.5 \r
+vLimitedIncrementTask USES _LINC _LCMP_P vTaskSuspend \r
+vContinuousIncrementTask USES uxTaskPriorityGet vTaskPrioritySet _LINC \r
+vCounterControlTask USES vCounterControlTask xContinousIncrementHandle \r
+ vTaskSuspend ulCounter vTaskResume vTaskDelay \r
+ vTaskSuspendAll xTaskResumeAll xLimitedIncrementHandle \r
+ uxCriticalNesting usCheckVariable \r
+vQueueSendWhenSuspendedTask USES vTaskSuspendAll xSuspendedTestQueue \r
+ ulValueToSend.6 xQueueSend xSuspendedQueueSendError \r
+ xTaskResumeAll vTaskDelay _LINC \r
+vQueueReceiveWhenSuspendedTask USES vTaskSuspendAll xSuspendedTestQueue \r
+ ulReceivedValue.8 xQueueReceive xTaskResumeAll \r
+ xSuspendedQueueReceiveError ulExpectedValue.7 _LINC \r
+xAreDynamicPriorityTasksStillRunning USES usCheckVariable usLastTaskCheck.9 \r
+ xSuspendedQueueSendError xSuspendedQueueReceiveError \r
+vStartPolledQueueTasks USES xQueueCreate xPolledQueue.1 \r
+ vPolledQueueConsumer STRING.QConsNB.2 xTaskCreate \r
+ vPolledQueueProducer STRING.QProdNB.3 \r
+vPolledQueueProducer USES xQueueSend uxCriticalNesting \r
+ xPollingProducerCount vTaskDelay \r
+vPolledQueueConsumer USES xQueueReceive uxCriticalNesting \r
+ xPollingConsumerCount uxQueueMessagesWaiting vTaskDelay \r
+xArePollingQueuesStillRunning USES xPollingConsumerCount xPollingProducerCount \r
+PE_Timer_LngHi1 USES _LCMP \r
+vAltStartComTestTasks USES uxBaseLED xSerialPortInitMinimal vComTxTask \r
+ STRING.COMTx.1 xTaskCreate vComRxTask STRING.COMRx.2 \r
+vComTxTask USES xPort xSerialPutChar uxBaseLED \r
+ vParTestToggleLED vParTestSetLED xTaskGetTickCount vTaskDelay \r
+vComRxTask USES xPort xSerialGetChar uxBaseLED \r
+ vParTestToggleLED vParTestSetLED uxRxLoops \r
+xAreComTestTasksStillRunning USES uxRxLoops \r
+xPortStartScheduler USES xBankedStartScheduler \r
+vStartIntegerMathTasks USES vCompeteingIntMathTask STRING.IntMath.1 \r
+ xTaskCheck xTaskCreate \r
+vCompeteingIntMathTask USES _LNEG _LDIVS _LCMP_P uxCriticalNesting \r
+xAreIntegerMathsTaskStillRunning USES xTaskCheck \r
+vStartBlockingQueueTasks USES vStartBlockingQueueTasks xQueueCreate \r
+ sBlockingConsumerCount sBlockingProducerCount vBlockingQueueConsumer \r
+ STRING.QConsB1.1 xTaskCreate vBlockingQueueProducer \r
+ STRING.QProdB2.2 STRING.QProdB3.3 STRING.QConsB4.4 \r
+ STRING.QProdB5.5 STRING.QConsB6.6 pvPortMalloc \r
+vBlockingQueueProducer USES xQueueSend \r
+vBlockingQueueConsumer USES xQueueReceive \r
+xAreBlockingQueuesStillRunning USES sLastBlockingConsumerCount.7 \r
+ sBlockingProducerCount sLastBlockingProducerCount.8 \r
+ sBlockingConsumerCount \r
+vCreateSuicidalTasks USES pvPortMalloc vCreateTasks STRING.CREATOR.1 \r
+ xTaskCreate uxTaskGetNumberOfTasks uxTasksRunningAtStart \r
+vSuicidalTask USES _LMUL vTaskDelay vTaskDelete \r
+vCreateTasks USES vPortFree vTaskDelay vSuicidalTask \r
+ STRING.SUICIDE1.2 xCreatedTask1 xTaskCreate STRING.SUICIDE2.3 \r
+ STRING.SUICIDE1.4 xCreatedTask2 STRING.SUICIDE2.5 \r
+ usCreationCount vCreateTasks \r
+xIsCreateTaskStillRunning USES usLastCreationCount.6 usCreationCount \r
+ uxTaskGetNumberOfTasks uxTasksRunningNow.7 uxTasksRunningAtStart \r
+TickTimer_Enable USES _TFLG1 _TIE \r
+TickTimer_SetFreqHz USES _LDIVU PE_Timer_LngHi1 CmpHighVal _TC0 _TC7 \r
+TickTimer_Init USES CmpHighVal _TC0 _TC7 _TSCR2 _TFLG1 _TIE \r
+Byte1_PutBit USES Byte1_Table _PORTAB \r
+Byte1_NegBit USES Byte1_Table _PORTAB \r
+COM0_SetBaudRateMode USES NumMode COM0_PrescHigh.1 PrescHigh _SCI0BD \r
+COM0_Init USES PrescHigh SerFlag NumMode _SCI0CR1 _SCI0SR2 \r
+ _SCI0SR1 _SCI0CR2 _SCI0BD \r
+\r
+*********************************************************************************************\r
+DEPENDENCY TREE\r
+*********************************************************************************************\r
+ main and _Startup Group\r
+ | \r
+ +- main \r
+ | | \r
+ | +- PE_low_level_init \r
+ | | | \r
+ | | +- TickTimer_Init \r
+ | | | \r
+ | | +- COM0_Init \r
+ | | \r
+ | +- vMain \r
+ | | \r
+ | +- vStartLEDFlashTasks \r
+ | | | \r
+ | | +- vLEDFlashTask \r
+ | | | | \r
+ | | | +- xTaskGetTickCount \r
+ | | | | \r
+ | | | +- vTaskDelayUntil \r
+ | | | | | \r
+ | | | | +- vTaskSuspendAll \r
+ | | | | | \r
+ | | | | +- vListRemove \r
+ | | | | | \r
+ | | | | +- vListInsert \r
+ | | | | | \r
+ | | | | +- xTaskResumeAll \r
+ | | | | | \r
+ | | | | +- vListRemove (see above)\r
+ | | | | | \r
+ | | | | +- vListInsertEnd \r
+ | | | | | \r
+ | | | | +- vTaskIncrementTick \r
+ | | | | | \r
+ | | | | +- vListRemove (see above)\r
+ | | | | | \r
+ | | | | +- vListInsertEnd (see above)\r
+ | | | | \r
+ | | | +- vParTestToggleLED \r
+ | | | | \r
+ | | | +- Byte1_NegBit \r
+ | | | \r
+ | | +- xTaskCreate \r
+ | | | \r
+ | | +- prvAllocateTCBAndStack\r
+ | | | | \r
+ | | | +- pvPortMalloc \r
+ | | | | | \r
+ | | | | +- vTaskSuspendAll (see above)\r
+ | | | | | \r
+ | | | | +- xTaskResumeAll (see above)\r
+ | | | | \r
+ | | | +- vPortFree \r
+ | | | | | \r
+ | | | | +- vTaskSuspendAll (see above)\r
+ | | | | | \r
+ | | | | +- xTaskResumeAll (see above)\r
+ | | | | \r
+ | | | +- memset \r
+ | | | \r
+ | | +- prvInitialiseTCBVariables\r
+ | | | | \r
+ | | | +- strncpy \r
+ | | | | \r
+ | | | +- vListInitialiseItem \r
+ | | | \r
+ | | +- pxPortInitialiseStack\r
+ | | | \r
+ | | +- prvInitialiseTaskLists\r
+ | | | | \r
+ | | | +- vListInitialise \r
+ | | | | \r
+ | | | +- vListInitialiseItem (see above)\r
+ | | | \r
+ | | +- vListInsertEnd (see above)\r
+ | | \r
+ | +- vStartPolledQueueTasks\r
+ | | | \r
+ | | +- xQueueCreate \r
+ | | | | \r
+ | | | +- pvPortMalloc (see above)\r
+ | | | | \r
+ | | | +- vListInitialise (see above)\r
+ | | | | \r
+ | | | +- vPortFree (see above)\r
+ | | | \r
+ | | +- vPolledQueueConsumer\r
+ | | | | \r
+ | | | +- xQueueReceive \r
+ | | | | | \r
+ | | | | +- vTaskSuspendAll (see above)\r
+ | | | | | \r
+ | | | | +- prvIsQueueEmpty \r
+ | | | | | \r
+ | | | | +- vTaskPlaceOnEventList\r
+ | | | | | | \r
+ | | | | | +- vListInsert (see above)\r
+ | | | | | | \r
+ | | | | | +- vListRemove (see above)\r
+ | | | | | \r
+ | | | | +- prvUnlockQueue \r
+ | | | | | | \r
+ | | | | | +- xTaskRemoveFromEventList\r
+ | | | | | | \r
+ | | | | | +- vListRemove (see above)\r
+ | | | | | | \r
+ | | | | | +- vListInsertEnd (see above)\r
+ | | | | | \r
+ | | | | +- xTaskResumeAll (see above)\r
+ | | | | | \r
+ | | | | +- memcpy \r
+ | | | | \r
+ | | | +- uxQueueMessagesWaiting\r
+ | | | | \r
+ | | | +- vTaskDelay \r
+ | | | | \r
+ | | | +- vTaskSuspendAll (see above)\r
+ | | | | \r
+ | | | +- vListRemove (see above)\r
+ | | | | \r
+ | | | +- vListInsert (see above)\r
+ | | | | \r
+ | | | +- xTaskResumeAll (see above)\r
+ | | | \r
+ | | +- xTaskCreate (see above)\r
+ | | | \r
+ | | +- vPolledQueueProducer\r
+ | | | \r
+ | | +- xQueueSend \r
+ | | | | \r
+ | | | +- vTaskSuspendAll (see above)\r
+ | | | | \r
+ | | | +- prvIsQueueFull \r
+ | | | | \r
+ | | | +- vTaskPlaceOnEventList (see above)\r
+ | | | | \r
+ | | | +- prvUnlockQueue (see above)\r
+ | | | | \r
+ | | | +- xTaskResumeAll (see above)\r
+ | | | | \r
+ | | | +- memcpy (see above)\r
+ | | | \r
+ | | +- vTaskDelay (see above)\r
+ | | \r
+ | +- vStartDynamicPriorityTasks\r
+ | | | \r
+ | | +- xQueueCreate (see above)\r
+ | | | \r
+ | | +- vContinuousIncrementTask\r
+ | | | | \r
+ | | | +- uxTaskPriorityGet \r
+ | | | | \r
+ | | | +- vTaskPrioritySet \r
+ | | | | | \r
+ | | | | +- vListRemove (see above)\r
+ | | | | | \r
+ | | | | +- vListInsertEnd (see above)\r
+ | | | | \r
+ | | | +- _LINC \r
+ | | | \r
+ | | +- xTaskCreate (see above)\r
+ | | | \r
+ | | +- vLimitedIncrementTask\r
+ | | | | \r
+ | | | +- _LINC (see above)\r
+ | | | | \r
+ | | | +- _LCMP_P \r
+ | | | | \r
+ | | | +- vTaskSuspend \r
+ | | | | \r
+ | | | +- vListRemove (see above)\r
+ | | | | \r
+ | | | +- vListInsertEnd (see above)\r
+ | | | \r
+ | | +- vCounterControlTask \r
+ | | | | \r
+ | | | +- vTaskSuspend (see above)\r
+ | | | | \r
+ | | | +- vTaskResume \r
+ | | | | | \r
+ | | | | +- vListRemove (see above)\r
+ | | | | | \r
+ | | | | +- vListInsertEnd (see above)\r
+ | | | | \r
+ | | | +- vTaskDelay (see above)\r
+ | | | | \r
+ | | | +- vTaskSuspendAll (see above)\r
+ | | | | \r
+ | | | +- xTaskResumeAll (see above)\r
+ | | | \r
+ | | +- vQueueSendWhenSuspendedTask\r
+ | | | | \r
+ | | | +- vTaskSuspendAll (see above)\r
+ | | | | \r
+ | | | +- xQueueSend (see above)\r
+ | | | | \r
+ | | | +- xTaskResumeAll (see above)\r
+ | | | | \r
+ | | | +- vTaskDelay (see above)\r
+ | | | | \r
+ | | | +- _LINC (see above)\r
+ | | | \r
+ | | +- vQueueReceiveWhenSuspendedTask\r
+ | | | \r
+ | | +- vTaskSuspendAll (see above)\r
+ | | | \r
+ | | +- xQueueReceive (see above)\r
+ | | | \r
+ | | +- xTaskResumeAll (see above)\r
+ | | | \r
+ | | +- _LINC (see above)\r
+ | | \r
+ | +- vAltStartComTestTasks\r
+ | | | \r
+ | | +- xSerialPortInitMinimal\r
+ | | | | \r
+ | | | +- xQueueCreate (see above)\r
+ | | | | \r
+ | | | +- COM0_SetBaudRateMode\r
+ | | | \r
+ | | +- vComTxTask \r
+ | | | | \r
+ | | | +- xSerialPutChar \r
+ | | | | | \r
+ | | | | +- xQueueSend (see above)\r
+ | | | | \r
+ | | | +- vParTestToggleLED (see above)\r
+ | | | | \r
+ | | | +- vParTestSetLED \r
+ | | | | | \r
+ | | | | +- Byte1_PutBit \r
+ | | | | \r
+ | | | +- xTaskGetTickCount (see above)\r
+ | | | | \r
+ | | | +- vTaskDelay (see above)\r
+ | | | \r
+ | | +- xTaskCreate (see above)\r
+ | | | \r
+ | | +- vComRxTask \r
+ | | | \r
+ | | +- xSerialGetChar \r
+ | | | | \r
+ | | | +- xQueueReceive (see above)\r
+ | | | \r
+ | | +- vParTestToggleLED (see above)\r
+ | | | \r
+ | | +- vParTestSetLED (see above)\r
+ | | \r
+ | +- vStartBlockingQueueTasks\r
+ | | | \r
+ | | +- xQueueCreate (see above)\r
+ | | | \r
+ | | +- vBlockingQueueConsumer\r
+ | | | | \r
+ | | | +- xQueueReceive (see above)\r
+ | | | \r
+ | | +- xTaskCreate (see above)\r
+ | | | \r
+ | | +- vBlockingQueueProducer\r
+ | | | | \r
+ | | | +- xQueueSend (see above)\r
+ | | | \r
+ | | +- pvPortMalloc (see above)\r
+ | | \r
+ | +- vStartIntegerMathTasks\r
+ | | | \r
+ | | +- vCompeteingIntMathTask\r
+ | | | | \r
+ | | | +- _LNEG \r
+ | | | | \r
+ | | | +- _LDIVS \r
+ | | | | | \r
+ | | | | +- _NEG_P \r
+ | | | | | \r
+ | | | | +- _lDivMod \r
+ | | | | \r
+ | | | +- _LCMP_P (see above)\r
+ | | | \r
+ | | +- xTaskCreate (see above)\r
+ | | \r
+ | +- vCreateSuicidalTasks\r
+ | | | \r
+ | | +- pvPortMalloc (see above)\r
+ | | | \r
+ | | +- vCreateTasks \r
+ | | | | \r
+ | | | +- vPortFree (see above)\r
+ | | | | \r
+ | | | +- vTaskDelay (see above)\r
+ | | | | \r
+ | | | +- vSuicidalTask \r
+ | | | | | \r
+ | | | | +- _LMUL \r
+ | | | | | \r
+ | | | | +- vTaskDelay (see above)\r
+ | | | | | \r
+ | | | | +- vTaskDelete \r
+ | | | | | \r
+ | | | | +- vListRemove (see above)\r
+ | | | | | \r
+ | | | | +- vListInsertEnd (see above)\r
+ | | | | \r
+ | | | +- xTaskCreate (see above)\r
+ | | | \r
+ | | +- xTaskCreate (see above)\r
+ | | | \r
+ | | +- uxTaskGetNumberOfTasks\r
+ | | \r
+ | +- vErrorChecks \r
+ | | | \r
+ | | +- xTaskGetTickCount (see above)\r
+ | | | \r
+ | | +- vTaskDelayUntil (see above)\r
+ | | | \r
+ | | +- prvCheckOtherTasksAreStillRunning\r
+ | | | | \r
+ | | | +- xArePollingQueuesStillRunning\r
+ | | | | \r
+ | | | +- xAreDynamicPriorityTasksStillRunning\r
+ | | | | \r
+ | | | +- xAreComTestTasksStillRunning\r
+ | | | | \r
+ | | | +- xAreIntegerMathsTaskStillRunning\r
+ | | | | \r
+ | | | +- xAreBlockingQueuesStillRunning\r
+ | | | | \r
+ | | | +- xIsCreateTaskStillRunning\r
+ | | | | \r
+ | | | +- uxTaskGetNumberOfTasks (see above)\r
+ | | | \r
+ | | +- _LCMP \r
+ | | | \r
+ | | +- vParTestToggleLED (see above)\r
+ | | \r
+ | +- xTaskCreate (see above)\r
+ | | \r
+ | +- vTaskStartScheduler \r
+ | | \r
+ | +- prvIdleTask \r
+ | | | \r
+ | | +- prvCheckTasksWaitingTermination\r
+ | | | | \r
+ | | | +- vTaskSuspendAll (see above)\r
+ | | | | \r
+ | | | +- xTaskResumeAll (see above)\r
+ | | | | \r
+ | | | +- vListRemove (see above)\r
+ | | | | \r
+ | | | +- prvDeleteTCB \r
+ | | | | \r
+ | | | +- vPortFree (see above)\r
+ | | | \r
+ | | +- vApplicationIdleHook\r
+ | | | \r
+ | | +- _LNEG (see above)\r
+ | | | \r
+ | | +- _LDIVS (see above)\r
+ | | | \r
+ | | +- _LCMP_P (see above)\r
+ | | \r
+ | +- xTaskCreate (see above)\r
+ | | \r
+ | +- xPortStartScheduler \r
+ | | \r
+ | +- xBankedStartScheduler\r
+ | | \r
+ | +- TickTimer_SetFreqHz \r
+ | | | \r
+ | | +- _LDIVU \r
+ | | | | \r
+ | | | +- _lDivMod (see above)\r
+ | | | \r
+ | | +- PE_Timer_LngHi1 \r
+ | | | \r
+ | | +- _LCMP (see above)\r
+ | | \r
+ | +- TickTimer_Enable \r
+ | \r
+ +- _EntryPoint \r
+ | \r
+ +- _Startup \r
+ | \r
+ +- Init \r
+ \r
+ _vect \r
+ | \r
+ +- Cpu_Interrupt \r
+ | \r
+ +- vCOM0_ISR \r
+ | | \r
+ | +- xQueueSendFromISR \r
+ | | | \r
+ | | +- memcpy (see above)\r
+ | | | \r
+ | | +- xTaskRemoveFromEventList (see above)\r
+ | | \r
+ | +- xQueueReceiveFromISR\r
+ | | \r
+ | +- memcpy (see above)\r
+ | | \r
+ | +- xTaskRemoveFromEventList (see above)\r
+ | \r
+ +- vPortTickInterrupt \r
+ | | \r
+ | +- vTaskIncrementTick (see above)\r
+ | | \r
+ | +- vTaskSwitchContext \r
+ | \r
+ +- vPortYield \r
+ | | \r
+ | +- vTaskSwitchContext (see above)\r
+ | \r
+ +- _EntryPoint (see above)\r
+ \r
+*********************************************************************************************\r
+STATISTIC SECTION\r
+---------------------------------------------------------------------------------------------\r
+\r
+ExeFile:\r
+--------\r
+Number of blocks to be downloaded: 18\r
+Total size of all blocks to be downloaded: 7636\r
+\r
--- /dev/null
+\r
+PROGRAM "E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior_banked\bin\Simulator.abs"\r
+\r
+*********************************************************************************************\r
+TARGET SECTION\r
+---------------------------------------------------------------------------------------------\r
+Processor : Motorola HC12\r
+Memory Model: BANKED\r
+File Format : ELF\Dwarf 2.0\r
+Linker : SmartLinker V-5.0.22 Build 4047, Feb 17 2004\r
+\r
+*********************************************************************************************\r
+FILE SECTION\r
+---------------------------------------------------------------------------------------------\r
+Start12.c.o Model: BANKED, Lang: ANSI-C\r
+STRING.C.o (ansibi.lib) Model: BANKED, Lang: ANSI-C\r
+rtshc12.c.o (ansibi.lib) Model: BANKED, Lang: ANSI-C\r
+Cpu.C.o Model: BANKED, Lang: ANSI-C\r
+IO_Map.C.o Model: BANKED, Lang: ANSI-C\r
+Vectors.c.o Model: BANKED, Lang: ANSI-C\r
+RTOSDemo.C.o Model: BANKED, Lang: ANSI-C\r
+main.c.o Model: BANKED, Lang: ANSI-C\r
+ParTest.c.o Model: BANKED, Lang: ANSI-C\r
+serial.c.o Model: BANKED, Lang: ANSI-C\r
+tasks.c.o Model: BANKED, Lang: ANSI-C\r
+queue.c.o Model: BANKED, Lang: ANSI-C\r
+list.c.o Model: BANKED, Lang: ANSI-C\r
+heap_2.c.o Model: BANKED, Lang: ANSI-C\r
+TickTimer.C.o Model: BANKED, Lang: ANSI-C\r
+PE_Timer.C.o Model: BANKED, Lang: ANSI-C\r
+Byte1.C.o Model: BANKED, Lang: ANSI-C\r
+flash.c.o Model: BANKED, Lang: ANSI-C\r
+dynamic.c.o Model: BANKED, Lang: ANSI-C\r
+PollQ.c.o Model: BANKED, Lang: ANSI-C\r
+comtest.c.o Model: BANKED, Lang: ANSI-C\r
+COM0.C.o Model: BANKED, Lang: ANSI-C\r
+port.c.o Model: BANKED, Lang: ANSI-C\r
+integer.c.o Model: BANKED, Lang: ANSI-C\r
+BlockQ.c.o Model: BANKED, Lang: ANSI-C\r
+death.c.o Model: BANKED, Lang: ANSI-C\r
+\r
+*********************************************************************************************\r
+STARTUP SECTION\r
+---------------------------------------------------------------------------------------------\r
+Entry point: 0xC000 (_EntryPoint)\r
+_startupData is allocated at 0xC07C and uses 24 Bytes\r
+extern struct _tagStartup {\r
+ unsigned flags 0\r
+ _PFunc main 0x30809A (main)\r
+ long stackOffset 0x3988\r
+ unsigned nofZeroOut 1\r
+ _Range pZeroOut 0x1000 10505\r
+ _Copy *toCopyDownBeg 0xC3AE\r
+ int nofLibInits 0\r
+ _LibInit *libInits 0xC098\r
+ int nofInitBodies 0\r
+ _Cpp *initBodies 0xC09A\r
+ int nofFiniBodies 0\r
+ _Cpp *finiBodies 0xC09A\r
+} _startupData;\r
+\r
+*********************************************************************************************\r
+SECTION-ALLOCATION SECTION\r
+Section Name Size Type From To Segment\r
+---------------------------------------------------------------------------------------------\r
+.data 1 R/W 0x1000 0x1000 RAM\r
+.text 594 R 0x308000 0x308251 ROM_PAGE30\r
+.init 124 R 0xC000 0xC07B ROM_C000\r
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+.abs_section_258 1 N/I 0x258 0x258 .absSeg405\r
+.abs_section_248 1 N/I 0x248 0x248 .absSeg406\r
+.abs_section_240 1 N/I 0x240 0x240 .absSeg407\r
+.abs_section_c 1 N/I 0xC 0xC .absSeg408\r
+.abs_section_a4 1 N/I 0xA4 0xA4 .absSeg409\r
+.abs_section_a2 1 N/I 0xA2 0xA2 .absSeg410\r
+.abs_section_a5 1 N/I 0xA5 0xA5 .absSeg411\r
+.abs_section_a0 1 N/I 0xA0 0xA0 .absSeg412\r
+.abs_section_a1 1 N/I 0xA1 0xA1 .absSeg413\r
+.abs_section_a3 1 N/I 0xA3 0xA3 .absSeg414\r
+.abs_section_a8 1 N/I 0xA8 0xA8 .absSeg415\r
+.abs_section_a9 1 N/I 0xA9 0xA9 .absSeg416\r
+.abs_section_c4 1 N/I 0xC4 0xC4 .absSeg417\r
+.abs_section_263 1 N/I 0x263 0x263 .absSeg418\r
+.abs_section_d 1 N/I 0xD 0xD .absSeg419\r
+.abs_section_26b 1 N/I 0x26B 0x26B .absSeg420\r
+.abs_section_253 1 N/I 0x253 0x253 .absSeg421\r
+.abs_section_25b 1 N/I 0x25B 0x25B .absSeg422\r
+.abs_section_24b 1 N/I 0x24B 0x24B .absSeg423\r
+.abs_section_243 1 N/I 0x243 0x243 .absSeg424\r
+.abs_section_35 1 N/I 0x35 0x35 .absSeg425\r
+.abs_section_3b 1 N/I 0x3B 0x3B .absSeg426\r
+.abs_section_ca 1 N/I 0xCA 0xCA .absSeg427\r
+.abs_section_cb 1 N/I 0xCB 0xCB .absSeg428\r
+.abs_section_ce 1 N/I 0xCE 0xCE .absSeg429\r
+.abs_section_cf 1 N/I 0xCF 0xCF .absSeg430\r
+.abs_section_cc 1 N/I 0xCC 0xCC .absSeg431\r
+.abs_section_cd 1 N/I 0xCD 0xCD .absSeg432\r
+.abs_section_d2 1 N/I 0xD2 0xD2 .absSeg433\r
+.abs_section_d3 1 N/I 0xD3 0xD3 .absSeg434\r
+.abs_section_d6 1 N/I 0xD6 0xD6 .absSeg435\r
+.abs_section_d7 1 N/I 0xD7 0xD7 .absSeg436\r
+.abs_section_d4 1 N/I 0xD4 0xD4 .absSeg437\r
+.abs_section_d5 1 N/I 0xD5 0xD5 .absSeg438\r
+.abs_section_da 1 N/I 0xDA 0xDA .absSeg439\r
+.abs_section_d8 1 N/I 0xD8 0xD8 .absSeg440\r
+.abs_section_d9 1 N/I 0xD9 0xD9 .absSeg441\r
+.abs_section_dd 1 N/I 0xDD 0xDD .absSeg442\r
+.abs_section_db 1 N/I 0xDB 0xDB .absSeg443\r
+.abs_section_f2 1 N/I 0xF2 0xF2 .absSeg444\r
+.abs_section_f0 1 N/I 0xF0 0xF0 .absSeg445\r
+.abs_section_f1 1 N/I 0xF1 0xF1 .absSeg446\r
+.abs_section_f5 1 N/I 0xF5 0xF5 .absSeg447\r
+.abs_section_f3 1 N/I 0xF3 0xF3 .absSeg448\r
+.abs_section_fa 1 N/I 0xFA 0xFA .absSeg449\r
+.abs_section_f8 1 N/I 0xF8 0xF8 .absSeg450\r
+.abs_section_f9 1 N/I 0xF9 0xF9 .absSeg451\r
+.abs_section_fd 1 N/I 0xFD 0xFD .absSeg452\r
+.abs_section_fb 1 N/I 0xFB 0xFB .absSeg453\r
+.abs_section_34 1 N/I 0x34 0x34 .absSeg454\r
+.abs_section_48 1 N/I 0x48 0x48 .absSeg455\r
+.abs_section_49 1 N/I 0x49 0x49 .absSeg456\r
+.abs_section_4a 1 N/I 0x4A 0x4A .absSeg457\r
+.abs_section_4b 1 N/I 0x4B 0x4B .absSeg458\r
+.abs_section_4e 1 N/I 0x4E 0x4E .absSeg459\r
+.abs_section_4f 1 N/I 0x4F 0x4F .absSeg460\r
+.abs_section_4c 1 N/I 0x4C 0x4C .absSeg461\r
+.abs_section_6d 1 N/I 0x6D 0x6D .absSeg462\r
+.abs_section_40 1 N/I 0x40 0x40 .absSeg463\r
+.abs_section_46 1 N/I 0x46 0x46 .absSeg464\r
+.abs_section_4d 1 N/I 0x4D 0x4D .absSeg465\r
+.abs_section_47 1 N/I 0x47 0x47 .absSeg466\r
+.abs_section_256 1 N/I 0x256 0x256 .absSeg467\r
+.abs_section_24e 1 N/I 0x24E 0x24E .absSeg468\r
+.abs_section_82 2 N/I 0x82 0x83 .absSeg469\r
+.abs_section_84 2 N/I 0x84 0x85 .absSeg470\r
+.abs_section_90 2 N/I 0x90 0x91 .absSeg471\r
+.abs_section_92 2 N/I 0x92 0x93 .absSeg472\r
+.abs_section_94 2 N/I 0x94 0x95 .absSeg473\r
+.abs_section_96 2 N/I 0x96 0x97 .absSeg474\r
+.abs_section_98 2 N/I 0x98 0x99 .absSeg475\r
+.abs_section_9a 2 N/I 0x9A 0x9B .absSeg476\r
+.abs_section_9c 2 N/I 0x9C 0x9D .absSeg477\r
+.abs_section_9e 2 N/I 0x9E 0x9F .absSeg478\r
+.abs_section_122 2 N/I 0x122 0x123 .absSeg479\r
+.abs_section_124 2 N/I 0x124 0x125 .absSeg480\r
+.abs_section_130 2 N/I 0x130 0x131 .absSeg481\r
+.abs_section_132 2 N/I 0x132 0x133 .absSeg482\r
+.abs_section_134 2 N/I 0x134 0x135 .absSeg483\r
+.abs_section_136 2 N/I 0x136 0x137 .absSeg484\r
+.abs_section_138 2 N/I 0x138 0x139 .absSeg485\r
+.abs_section_13a 2 N/I 0x13A 0x13B .absSeg486\r
+.abs_section_13c 2 N/I 0x13C 0x13D .absSeg487\r
+.abs_section_13e 2 N/I 0x13E 0x13F .absSeg488\r
+.abs_section_2 2 N/I 0x2 0x3 .absSeg489\r
+.abs_section_76 2 N/I 0x76 0x77 .absSeg490\r
+.abs_section_74 2 N/I 0x74 0x75 .absSeg491\r
+.abs_section_72 2 N/I 0x72 0x73 .absSeg492\r
+.abs_section_64 2 N/I 0x64 0x65 .absSeg493\r
+.abs_section_62 2 N/I 0x62 0x63 .absSeg494\r
+.abs_section_0 2 N/I 0x0 0x1 .absSeg495\r
+.abs_section_ac 2 N/I 0xAC 0xAD .absSeg496\r
+.abs_section_ae 2 N/I 0xAE 0xAF .absSeg497\r
+.abs_section_b0 2 N/I 0xB0 0xB1 .absSeg498\r
+.abs_section_b2 2 N/I 0xB2 0xB3 .absSeg499\r
+.abs_section_bc 2 N/I 0xBC 0xBD .absSeg500\r
+.abs_section_be 2 N/I 0xBE 0xBF .absSeg501\r
+.abs_section_c0 2 N/I 0xC0 0xC1 .absSeg502\r
+.abs_section_c2 2 N/I 0xC2 0xC3 .absSeg503\r
+.abs_section_b4 2 N/I 0xB4 0xB5 .absSeg504\r
+.abs_section_b6 2 N/I 0xB6 0xB7 .absSeg505\r
+.abs_section_b8 2 N/I 0xB8 0xB9 .absSeg506\r
+.abs_section_ba 2 N/I 0xBA 0xBB .absSeg507\r
+.abs_section_c8 2 N/I 0xC8 0xC9 .absSeg508\r
+.abs_section_d0 2 N/I 0xD0 0xD1 .absSeg509\r
+.abs_section_50 2 N/I 0x50 0x51 .absSeg510\r
+.abs_section_78 2 N/I 0x78 0x79 .absSeg511\r
+.abs_section_52 2 N/I 0x52 0x53 .absSeg512\r
+.abs_section_7a 2 N/I 0x7A 0x7B .absSeg513\r
+.abs_section_54 2 N/I 0x54 0x55 .absSeg514\r
+.abs_section_7c 2 N/I 0x7C 0x7D .absSeg515\r
+.abs_section_56 2 N/I 0x56 0x57 .absSeg516\r
+.abs_section_7e 2 N/I 0x7E 0x7F .absSeg517\r
+.abs_section_58 2 N/I 0x58 0x59 .absSeg518\r
+.abs_section_5a 2 N/I 0x5A 0x5B .absSeg519\r
+.abs_section_5c 2 N/I 0x5C 0x5D .absSeg520\r
+.abs_section_5e 2 N/I 0x5E 0x5F .absSeg521\r
+.abs_section_44 2 N/I 0x44 0x45 .absSeg522\r
+.abs_section_ff80 128 R 0xFF80 0xFFFF .absSeg523\r
+.bss 10475 R/W 0x1001 0x38EB RAM\r
+.common 6 R/W 0x38EC 0x38F1 RAM\r
+TickTimer_CODE 143 R 0x3B811C 0x3B81AA ROM_PAGE3B\r
+Byte1_CODE 61 R 0x3B81AB 0x3B81E7 ROM_PAGE3B\r
+COM0_CODE 67 R 0x3B81E8 0x3B822A ROM_PAGE3B\r
+TickTimer_DATA 2 R/W 0x38F2 0x38F3 RAM\r
+Byte1_DATA 8 R/W 0x38F4 0x38FB RAM\r
+COM0_DATA 13 R/W 0x38FC 0x3908 RAM\r
+.stack 128 R/W 0x3909 0x3988 RAM\r
+ROM_PAGE31_524 552 R 0x318000 0x318227 ROM_PAGE31\r
+ROM_PAGE32_525 552 R 0x328000 0x328227 ROM_PAGE32\r
+ROM_PAGE33_526 564 R 0x338000 0x338233 ROM_PAGE33\r
+ROM_PAGE34_527 579 R 0x348000 0x348242 ROM_PAGE34\r
+ROM_PAGE35_528 589 R 0x358000 0x35824C ROM_PAGE35\r
+ROM_PAGE36_529 555 R 0x368000 0x36822A ROM_PAGE36\r
+ROM_PAGE37_530 578 R 0x378000 0x378241 ROM_PAGE37\r
+ROM_PAGE38_531 558 R 0x388000 0x38822D ROM_PAGE38\r
+ROM_PAGE39_532 288 R 0x398000 0x39811F ROM_PAGE39\r
+ROM_PAGE3A_533 574 R 0x3A8000 0x3A823D ROM_PAGE3A\r
+ROM_PAGE3B_534 284 R 0x3B8000 0x3B811B ROM_PAGE3B\r
+\r
+Summary of section sizes per section type:\r
+READ_ONLY (R): 1DD3 (dec: 7635)\r
+READ_WRITE (R/W): 2989 (dec: 10633)\r
+NO_INIT (N/I): 241 (dec: 577)\r
+\r
+*********************************************************************************************\r
+VECTOR-ALLOCATION SECTION\r
+ Address InitValue InitFunction\r
+---------------------------------------------------------------------------------------------\r
+\r
+*********************************************************************************************\r
+OBJECT-ALLOCATION SECTION\r
+ Name Module Addr hSize dSize Ref Section RLIB\r
+---------------------------------------------------------------------------------------------\r
+MODULE: -- Start12.c.o --\r
+- PROCEDURES:\r
+ Init 308000 29 41 2 .text \r
+ _Startup C151 12 18 1 NON_BANKED \r
+- VARIABLES:\r
+ _startupData C07C 18 24 6 .startData \r
+MODULE: -- STRING.C.o (ansibi.lib) --\r
+- PROCEDURES:\r
+ memcpy 308029 26 38 8 .text \r
+ memset 30804F 1E 30 2 .text \r
+ strncpy 30806D 2D 45 2 .text \r
+- VARIABLES:\r
+MODULE: -- rtshc12.c.o (ansibi.lib) --\r
+- PROCEDURES:\r
+ _LCMP C163 19 25 2 NON_BANKED \r
+ _LCMP_P C17C 15 21 3 NON_BANKED \r
+ _LNEG C191 D 13 2 NON_BANKED \r
+ _LINC C19E 5 5 4 NON_BANKED \r
+ _LMUL C1A3 27 39 1 NON_BANKED \r
+ _lDivMod C1CA E3 227 3 NON_BANKED \r
+ _LDIVU C2AD E 14 1 NON_BANKED \r
+ _NEG_P C2BB F 15 4 NON_BANKED \r
+ _LDIVS C2CA 35 53 2 NON_BANKED \r
+- VARIABLES:\r
+MODULE: -- Cpu.C.o --\r
+- PROCEDURES:\r
+ _EntryPoint C000 2E 46 1 .init \r
+ PE_low_level_init C02E 4E 78 2 .init \r
+ Cpu_Interrupt C2FF 1 1 60 NON_BANKED \r
+- VARIABLES:\r
+MODULE: -- IO_Map.C.o --\r
+- PROCEDURES:\r
+- VARIABLES:\r
+ _ARMCOP 3F 1 1 0 .abs_section_3f\r
+ _ATD0DIEN 8D 1 1 0 .abs_section_8d\r
+ _ATD0STAT0 86 1 1 0 .abs_section_86\r
+ _ATD0STAT1 8B 1 1 0 .abs_section_8b\r
+ _ATD1DIEN 12D 1 1 0 .abs_section_12d\r
+ _ATD1STAT0 126 1 1 0 .abs_section_126\r
+ _ATD1STAT1 12B 1 1 0 .abs_section_12b\r
+ _BDMCCR FF06 1 1 0 .abs_section_ff06\r
+ _BDMINR FF07 1 1 0 .abs_section_ff07\r
+ _BDMSTS FF01 1 1 0 .abs_section_ff01\r
+ _BKP0H 2B 1 1 0 .abs_section_2b\r
+ _BKP0L 2C 1 1 0 .abs_section_2c\r
+ _BKP0X 2A 1 1 0 .abs_section_2a\r
+ _BKP1H 2E 1 1 0 .abs_section_2e\r
+ _BKP1L 2F 1 1 0 .abs_section_2f\r
+ _BKP1X 2D 1 1 0 .abs_section_2d\r
+ _BKPCT0 28 1 1 0 .abs_section_28\r
+ _BKPCT1 29 1 1 0 .abs_section_29\r
+ _CAN0BTR0 142 1 1 0 .abs_section_142\r
+ _CAN0BTR1 143 1 1 0 .abs_section_143\r
+ _CAN0CTL0 140 1 1 0 .abs_section_140\r
+ _CAN0CTL1 141 1 1 0 .abs_section_141\r
+ _CAN0IDAC 14B 1 1 0 .abs_section_14b\r
+ _CAN0IDAR0 150 1 1 0 .abs_section_150\r
+ _CAN0IDAR1 151 1 1 0 .abs_section_151\r
+ _CAN0IDAR2 152 1 1 0 .abs_section_152\r
+ _CAN0IDAR3 153 1 1 0 .abs_section_153\r
+ _CAN0IDAR4 158 1 1 0 .abs_section_158\r
+ _CAN0IDAR5 159 1 1 0 .abs_section_159\r
+ _CAN0IDAR6 15A 1 1 0 .abs_section_15a\r
+ _CAN0IDAR7 15B 1 1 0 .abs_section_15b\r
+ _CAN0IDMR0 154 1 1 0 .abs_section_154\r
+ _CAN0IDMR1 155 1 1 0 .abs_section_155\r
+ _CAN0IDMR2 156 1 1 0 .abs_section_156\r
+ _CAN0IDMR3 157 1 1 0 .abs_section_157\r
+ _CAN0IDMR4 15C 1 1 0 .abs_section_15c\r
+ _CAN0IDMR5 15D 1 1 0 .abs_section_15d\r
+ _CAN0IDMR6 15E 1 1 0 .abs_section_15e\r
+ _CAN0IDMR7 15F 1 1 0 .abs_section_15f\r
+ _CAN0RFLG 144 1 1 0 .abs_section_144\r
+ _CAN0RIER 145 1 1 0 .abs_section_145\r
+ _CAN0RXDLR 16C 1 1 0 .abs_section_16c\r
+ _CAN0RXDSR0 164 1 1 0 .abs_section_164\r
+ _CAN0RXDSR1 165 1 1 0 .abs_section_165\r
+ _CAN0RXDSR2 166 1 1 0 .abs_section_166\r
+ _CAN0RXDSR3 167 1 1 0 .abs_section_167\r
+ _CAN0RXDSR4 168 1 1 0 .abs_section_168\r
+ _CAN0RXDSR5 169 1 1 0 .abs_section_169\r
+ _CAN0RXDSR6 16A 1 1 0 .abs_section_16a\r
+ _CAN0RXDSR7 16B 1 1 0 .abs_section_16b\r
+ _CAN0RXERR 14E 1 1 0 .abs_section_14e\r
+ _CAN0RXIDR0 160 1 1 0 .abs_section_160\r
+ _CAN0RXIDR1 161 1 1 0 .abs_section_161\r
+ _CAN0RXIDR2 162 1 1 0 .abs_section_162\r
+ _CAN0RXIDR3 163 1 1 0 .abs_section_163\r
+ _CAN0TAAK 149 1 1 0 .abs_section_149\r
+ _CAN0TARQ 148 1 1 0 .abs_section_148\r
+ _CAN0TBSEL 14A 1 1 0 .abs_section_14a\r
+ _CAN0TFLG 146 1 1 0 .abs_section_146\r
+ _CAN0TIER 147 1 1 0 .abs_section_147\r
+ _CAN0TXDLR 17C 1 1 0 .abs_section_17c\r
+ _CAN0TXDSR0 174 1 1 0 .abs_section_174\r
+ _CAN0TXDSR1 175 1 1 0 .abs_section_175\r
+ _CAN0TXDSR2 176 1 1 0 .abs_section_176\r
+ _CAN0TXDSR3 177 1 1 0 .abs_section_177\r
+ _CAN0TXDSR4 178 1 1 0 .abs_section_178\r
+ _CAN0TXDSR5 179 1 1 0 .abs_section_179\r
+ _CAN0TXDSR6 17A 1 1 0 .abs_section_17a\r
+ _CAN0TXDSR7 17B 1 1 0 .abs_section_17b\r
+ _CAN0TXERR 14F 1 1 0 .abs_section_14f\r
+ _CAN0TXIDR0 170 1 1 0 .abs_section_170\r
+ _CAN0TXIDR1 171 1 1 0 .abs_section_171\r
+ _CAN0TXIDR2 172 1 1 0 .abs_section_172\r
+ _CAN0TXIDR3 173 1 1 0 .abs_section_173\r
+ _CAN0TXTBPR 17F 1 1 0 .abs_section_17f\r
+ _CAN1BTR0 182 1 1 0 .abs_section_182\r
+ _CAN1BTR1 183 1 1 0 .abs_section_183\r
+ _CAN1CTL0 180 1 1 0 .abs_section_180\r
+ _CAN1CTL1 181 1 1 0 .abs_section_181\r
+ _CAN1IDAC 18B 1 1 0 .abs_section_18b\r
+ _CAN1IDAR0 190 1 1 0 .abs_section_190\r
+ _CAN1IDAR1 191 1 1 0 .abs_section_191\r
+ _CAN1IDAR2 192 1 1 0 .abs_section_192\r
+ _CAN1IDAR3 193 1 1 0 .abs_section_193\r
+ _CAN1IDAR4 198 1 1 0 .abs_section_198\r
+ _CAN1IDAR5 199 1 1 0 .abs_section_199\r
+ _CAN1IDAR6 19A 1 1 0 .abs_section_19a\r
+ _CAN1IDAR7 19B 1 1 0 .abs_section_19b\r
+ _CAN1IDMR0 194 1 1 0 .abs_section_194\r
+ _CAN1IDMR1 195 1 1 0 .abs_section_195\r
+ _CAN1IDMR2 196 1 1 0 .abs_section_196\r
+ _CAN1IDMR3 197 1 1 0 .abs_section_197\r
+ _CAN1IDMR4 19C 1 1 0 .abs_section_19c\r
+ _CAN1IDMR5 19D 1 1 0 .abs_section_19d\r
+ _CAN1IDMR6 19E 1 1 0 .abs_section_19e\r
+ _CAN1IDMR7 19F 1 1 0 .abs_section_19f\r
+ _CAN1RFLG 184 1 1 0 .abs_section_184\r
+ _CAN1RIER 185 1 1 0 .abs_section_185\r
+ _CAN1RXDLR 1AC 1 1 0 .abs_section_1ac\r
+ _CAN1RXDSR0 1A4 1 1 0 .abs_section_1a4\r
+ _CAN1RXDSR1 1A5 1 1 0 .abs_section_1a5\r
+ _CAN1RXDSR2 1A6 1 1 0 .abs_section_1a6\r
+ _CAN1RXDSR3 1A7 1 1 0 .abs_section_1a7\r
+ _CAN1RXDSR4 1A8 1 1 0 .abs_section_1a8\r
+ _CAN1RXDSR5 1A9 1 1 0 .abs_section_1a9\r
+ _CAN1RXDSR6 1AA 1 1 0 .abs_section_1aa\r
+ _CAN1RXDSR7 1AB 1 1 0 .abs_section_1ab\r
+ _CAN1RXERR 18E 1 1 0 .abs_section_18e\r
+ _CAN1RXIDR0 1A0 1 1 0 .abs_section_1a0\r
+ _CAN1RXIDR1 1A1 1 1 0 .abs_section_1a1\r
+ _CAN1RXIDR2 1A2 1 1 0 .abs_section_1a2\r
+ _CAN1RXIDR3 1A3 1 1 0 .abs_section_1a3\r
+ _CAN1TAAK 189 1 1 0 .abs_section_189\r
+ _CAN1TARQ 188 1 1 0 .abs_section_188\r
+ _CAN1TBSEL 18A 1 1 0 .abs_section_18a\r
+ _CAN1TFLG 186 1 1 0 .abs_section_186\r
+ _CAN1TIER 187 1 1 0 .abs_section_187\r
+ _CAN1TXDLR 1BC 1 1 0 .abs_section_1bc\r
+ _CAN1TXDSR0 1B4 1 1 0 .abs_section_1b4\r
+ _CAN1TXDSR1 1B5 1 1 0 .abs_section_1b5\r
+ _CAN1TXDSR2 1B6 1 1 0 .abs_section_1b6\r
+ _CAN1TXDSR3 1B7 1 1 0 .abs_section_1b7\r
+ _CAN1TXDSR4 1B8 1 1 0 .abs_section_1b8\r
+ _CAN1TXDSR5 1B9 1 1 0 .abs_section_1b9\r
+ _CAN1TXDSR6 1BA 1 1 0 .abs_section_1ba\r
+ _CAN1TXDSR7 1BB 1 1 0 .abs_section_1bb\r
+ _CAN1TXERR 18F 1 1 0 .abs_section_18f\r
+ _CAN1TXIDR0 1B0 1 1 0 .abs_section_1b0\r
+ _CAN1TXIDR1 1B1 1 1 0 .abs_section_1b1\r
+ _CAN1TXIDR2 1B2 1 1 0 .abs_section_1b2\r
+ _CAN1TXIDR3 1B3 1 1 0 .abs_section_1b3\r
+ _CAN1TXTBPR 1BF 1 1 0 .abs_section_1bf\r
+ _CAN2BTR0 1C2 1 1 0 .abs_section_1c2\r
+ _CAN2BTR1 1C3 1 1 0 .abs_section_1c3\r
+ _CAN2CTL0 1C0 1 1 0 .abs_section_1c0\r
+ _CAN2CTL1 1C1 1 1 0 .abs_section_1c1\r
+ _CAN2IDAC 1CB 1 1 0 .abs_section_1cb\r
+ _CAN2IDAR0 1D0 1 1 0 .abs_section_1d0\r
+ _CAN2IDAR1 1D1 1 1 0 .abs_section_1d1\r
+ _CAN2IDAR2 1D2 1 1 0 .abs_section_1d2\r
+ _CAN2IDAR3 1D3 1 1 0 .abs_section_1d3\r
+ _CAN2IDAR4 1D8 1 1 0 .abs_section_1d8\r
+ _CAN2IDAR5 1D9 1 1 0 .abs_section_1d9\r
+ _CAN2IDAR6 1DA 1 1 0 .abs_section_1da\r
+ _CAN2IDAR7 1DB 1 1 0 .abs_section_1db\r
+ _CAN2IDMR0 1D4 1 1 0 .abs_section_1d4\r
+ _CAN2IDMR1 1D5 1 1 0 .abs_section_1d5\r
+ _CAN2IDMR2 1D6 1 1 0 .abs_section_1d6\r
+ _CAN2IDMR3 1D7 1 1 0 .abs_section_1d7\r
+ _CAN2IDMR4 1DC 1 1 0 .abs_section_1dc\r
+ _CAN2IDMR5 1DD 1 1 0 .abs_section_1dd\r
+ _CAN2IDMR6 1DE 1 1 0 .abs_section_1de\r
+ _CAN2IDMR7 1DF 1 1 0 .abs_section_1df\r
+ _CAN2RFLG 1C4 1 1 0 .abs_section_1c4\r
+ _CAN2RIER 1C5 1 1 0 .abs_section_1c5\r
+ _CAN2RXDLR 1EC 1 1 0 .abs_section_1ec\r
+ _CAN2RXDSR0 1E4 1 1 0 .abs_section_1e4\r
+ _CAN2RXDSR1 1E5 1 1 0 .abs_section_1e5\r
+ _CAN2RXDSR2 1E6 1 1 0 .abs_section_1e6\r
+ _CAN2RXDSR3 1E7 1 1 0 .abs_section_1e7\r
+ _CAN2RXDSR4 1E8 1 1 0 .abs_section_1e8\r
+ _CAN2RXDSR5 1E9 1 1 0 .abs_section_1e9\r
+ _CAN2RXDSR6 1EA 1 1 0 .abs_section_1ea\r
+ _CAN2RXDSR7 1EB 1 1 0 .abs_section_1eb\r
+ _CAN2RXERR 1CE 1 1 0 .abs_section_1ce\r
+ _CAN2RXIDR0 1E0 1 1 0 .abs_section_1e0\r
+ _CAN2RXIDR1 1E1 1 1 0 .abs_section_1e1\r
+ _CAN2RXIDR2 1E2 1 1 0 .abs_section_1e2\r
+ _CAN2RXIDR3 1E3 1 1 0 .abs_section_1e3\r
+ _CAN2TAAK 1C9 1 1 0 .abs_section_1c9\r
+ _CAN2TARQ 1C8 1 1 0 .abs_section_1c8\r
+ _CAN2TBSEL 1CA 1 1 0 .abs_section_1ca\r
+ _CAN2TFLG 1C6 1 1 0 .abs_section_1c6\r
+ _CAN2TIER 1C7 1 1 0 .abs_section_1c7\r
+ _CAN2TXDLR 1FC 1 1 0 .abs_section_1fc\r
+ _CAN2TXDSR0 1F4 1 1 0 .abs_section_1f4\r
+ _CAN2TXDSR1 1F5 1 1 0 .abs_section_1f5\r
+ _CAN2TXDSR2 1F6 1 1 0 .abs_section_1f6\r
+ _CAN2TXDSR3 1F7 1 1 0 .abs_section_1f7\r
+ _CAN2TXDSR4 1F8 1 1 0 .abs_section_1f8\r
+ _CAN2TXDSR5 1F9 1 1 0 .abs_section_1f9\r
+ _CAN2TXDSR6 1FA 1 1 0 .abs_section_1fa\r
+ _CAN2TXDSR7 1FB 1 1 0 .abs_section_1fb\r
+ _CAN2TXERR 1CF 1 1 0 .abs_section_1cf\r
+ _CAN2TXIDR0 1F0 1 1 0 .abs_section_1f0\r
+ _CAN2TXIDR1 1F1 1 1 0 .abs_section_1f1\r
+ _CAN2TXIDR2 1F2 1 1 0 .abs_section_1f2\r
+ _CAN2TXIDR3 1F3 1 1 0 .abs_section_1f3\r
+ _CAN2TXTBPR 1FF 1 1 0 .abs_section_1ff\r
+ _CAN3BTR0 202 1 1 0 .abs_section_202\r
+ _CAN3BTR1 203 1 1 0 .abs_section_203\r
+ _CAN3CTL0 200 1 1 0 .abs_section_200\r
+ _CAN3CTL1 201 1 1 0 .abs_section_201\r
+ _CAN3IDAC 20B 1 1 0 .abs_section_20b\r
+ _CAN3IDAR0 210 1 1 0 .abs_section_210\r
+ _CAN3IDAR1 211 1 1 0 .abs_section_211\r
+ _CAN3IDAR2 212 1 1 0 .abs_section_212\r
+ _CAN3IDAR3 213 1 1 0 .abs_section_213\r
+ _CAN3IDAR4 218 1 1 0 .abs_section_218\r
+ _CAN3IDAR5 219 1 1 0 .abs_section_219\r
+ _CAN3IDAR6 21A 1 1 0 .abs_section_21a\r
+ _CAN3IDAR7 21B 1 1 0 .abs_section_21b\r
+ _CAN3IDMR0 214 1 1 0 .abs_section_214\r
+ _CAN3IDMR1 215 1 1 0 .abs_section_215\r
+ _CAN3IDMR2 216 1 1 0 .abs_section_216\r
+ _CAN3IDMR3 217 1 1 0 .abs_section_217\r
+ _CAN3IDMR4 21C 1 1 0 .abs_section_21c\r
+ _CAN3IDMR5 21D 1 1 0 .abs_section_21d\r
+ _CAN3IDMR6 21E 1 1 0 .abs_section_21e\r
+ _CAN3IDMR7 21F 1 1 0 .abs_section_21f\r
+ _CAN3RFLG 204 1 1 0 .abs_section_204\r
+ _CAN3RIER 205 1 1 0 .abs_section_205\r
+ _CAN3RXDLR 22C 1 1 0 .abs_section_22c\r
+ _CAN3RXDSR0 224 1 1 0 .abs_section_224\r
+ _CAN3RXDSR1 225 1 1 0 .abs_section_225\r
+ _CAN3RXDSR2 226 1 1 0 .abs_section_226\r
+ _CAN3RXDSR3 227 1 1 0 .abs_section_227\r
+ _CAN3RXDSR4 228 1 1 0 .abs_section_228\r
+ _CAN3RXDSR5 229 1 1 0 .abs_section_229\r
+ _CAN3RXDSR6 22A 1 1 0 .abs_section_22a\r
+ _CAN3RXDSR7 22B 1 1 0 .abs_section_22b\r
+ _CAN3RXERR 20E 1 1 0 .abs_section_20e\r
+ _CAN3RXIDR0 220 1 1 0 .abs_section_220\r
+ _CAN3RXIDR1 221 1 1 0 .abs_section_221\r
+ _CAN3RXIDR2 222 1 1 0 .abs_section_222\r
+ _CAN3RXIDR3 223 1 1 0 .abs_section_223\r
+ _CAN3TAAK 209 1 1 0 .abs_section_209\r
+ _CAN3TARQ 208 1 1 0 .abs_section_208\r
+ _CAN3TBSEL 20A 1 1 0 .abs_section_20a\r
+ _CAN3TFLG 206 1 1 0 .abs_section_206\r
+ _CAN3TIER 207 1 1 0 .abs_section_207\r
+ _CAN3TXDLR 23C 1 1 0 .abs_section_23c\r
+ _CAN3TXDSR0 234 1 1 0 .abs_section_234\r
+ _CAN3TXDSR1 235 1 1 0 .abs_section_235\r
+ _CAN3TXDSR2 236 1 1 0 .abs_section_236\r
+ _CAN3TXDSR3 237 1 1 0 .abs_section_237\r
+ _CAN3TXDSR4 238 1 1 0 .abs_section_238\r
+ _CAN3TXDSR5 239 1 1 0 .abs_section_239\r
+ _CAN3TXDSR6 23A 1 1 0 .abs_section_23a\r
+ _CAN3TXDSR7 23B 1 1 0 .abs_section_23b\r
+ _CAN3TXERR 20F 1 1 0 .abs_section_20f\r
+ _CAN3TXIDR0 230 1 1 0 .abs_section_230\r
+ _CAN3TXIDR1 231 1 1 0 .abs_section_231\r
+ _CAN3TXIDR2 232 1 1 0 .abs_section_232\r
+ _CAN3TXIDR3 233 1 1 0 .abs_section_233\r
+ _CAN3TXTBPR 23F 1 1 0 .abs_section_23f\r
+ _CAN4BTR0 282 1 1 0 .abs_section_282\r
+ _CAN4BTR1 283 1 1 0 .abs_section_283\r
+ _CAN4CTL0 280 1 1 0 .abs_section_280\r
+ _CAN4CTL1 281 1 1 0 .abs_section_281\r
+ _CAN4IDAC 28B 1 1 0 .abs_section_28b\r
+ _CAN4IDAR0 290 1 1 0 .abs_section_290\r
+ _CAN4IDAR1 291 1 1 0 .abs_section_291\r
+ _CAN4IDAR2 292 1 1 0 .abs_section_292\r
+ _CAN4IDAR3 293 1 1 0 .abs_section_293\r
+ _CAN4IDAR4 298 1 1 0 .abs_section_298\r
+ _CAN4IDAR5 299 1 1 0 .abs_section_299\r
+ _CAN4IDAR6 29A 1 1 0 .abs_section_29a\r
+ _CAN4IDAR7 29B 1 1 0 .abs_section_29b\r
+ _CAN4IDMR0 294 1 1 0 .abs_section_294\r
+ _CAN4IDMR1 295 1 1 0 .abs_section_295\r
+ _CAN4IDMR2 296 1 1 0 .abs_section_296\r
+ _CAN4IDMR3 297 1 1 0 .abs_section_297\r
+ _CAN4IDMR4 29C 1 1 0 .abs_section_29c\r
+ _CAN4IDMR5 29D 1 1 0 .abs_section_29d\r
+ _CAN4IDMR6 29E 1 1 0 .abs_section_29e\r
+ _CAN4IDMR7 29F 1 1 0 .abs_section_29f\r
+ _CAN4RFLG 284 1 1 0 .abs_section_284\r
+ _CAN4RIER 285 1 1 0 .abs_section_285\r
+ _CAN4RXDLR 2AC 1 1 0 .abs_section_2ac\r
+ _CAN4RXDSR0 2A4 1 1 0 .abs_section_2a4\r
+ _CAN4RXDSR1 2A5 1 1 0 .abs_section_2a5\r
+ _CAN4RXDSR2 2A6 1 1 0 .abs_section_2a6\r
+ _CAN4RXDSR3 2A7 1 1 0 .abs_section_2a7\r
+ _CAN4RXDSR4 2A8 1 1 0 .abs_section_2a8\r
+ _CAN4RXDSR5 2A9 1 1 0 .abs_section_2a9\r
+ _CAN4RXDSR6 2AA 1 1 0 .abs_section_2aa\r
+ _CAN4RXDSR7 2AB 1 1 0 .abs_section_2ab\r
+ _CAN4RXERR 28E 1 1 0 .abs_section_28e\r
+ _CAN4RXIDR0 2A0 1 1 0 .abs_section_2a0\r
+ _CAN4RXIDR1 2A1 1 1 0 .abs_section_2a1\r
+ _CAN4RXIDR2 2A2 1 1 0 .abs_section_2a2\r
+ _CAN4RXIDR3 2A3 1 1 0 .abs_section_2a3\r
+ _CAN4TAAK 289 1 1 0 .abs_section_289\r
+ _CAN4TARQ 288 1 1 0 .abs_section_288\r
+ _CAN4TBSEL 28A 1 1 0 .abs_section_28a\r
+ _CAN4TFLG 286 1 1 0 .abs_section_286\r
+ _CAN4TIER 287 1 1 0 .abs_section_287\r
+ _CAN4TXDLR 2BC 1 1 0 .abs_section_2bc\r
+ _CAN4TXDSR0 2B4 1 1 0 .abs_section_2b4\r
+ _CAN4TXDSR1 2B5 1 1 0 .abs_section_2b5\r
+ _CAN4TXDSR2 2B6 1 1 0 .abs_section_2b6\r
+ _CAN4TXDSR3 2B7 1 1 0 .abs_section_2b7\r
+ _CAN4TXDSR4 2B8 1 1 0 .abs_section_2b8\r
+ _CAN4TXDSR5 2B9 1 1 0 .abs_section_2b9\r
+ _CAN4TXDSR6 2BA 1 1 0 .abs_section_2ba\r
+ _CAN4TXDSR7 2BB 1 1 0 .abs_section_2bb\r
+ _CAN4TXERR 28F 1 1 0 .abs_section_28f\r
+ _CAN4TXIDR0 2B0 1 1 0 .abs_section_2b0\r
+ _CAN4TXIDR1 2B1 1 1 0 .abs_section_2b1\r
+ _CAN4TXIDR2 2B2 1 1 0 .abs_section_2b2\r
+ _CAN4TXIDR3 2B3 1 1 0 .abs_section_2b3\r
+ _CAN4TXTBPR 2BF 1 1 0 .abs_section_2bf\r
+ _CFORC 41 1 1 0 .abs_section_41\r
+ _CLKSEL 39 1 1 3 .abs_section_39\r
+ _COPCTL 3C 1 1 0 .abs_section_3c\r
+ _CRGFLG 37 1 1 1 .abs_section_37\r
+ _CRGINT 38 1 1 0 .abs_section_38\r
+ _CTCTL 3E 1 1 0 .abs_section_3e\r
+ _CTFLG 36 1 1 0 .abs_section_36\r
+ _DDRE 9 1 1 0 .abs_section_9\r
+ _DDRH 262 1 1 0 .abs_section_262\r
+ _DDRJ 26A 1 1 0 .abs_section_26a\r
+ _DDRK 33 1 1 0 .abs_section_33\r
+ _DDRM 252 1 1 0 .abs_section_252\r
+ _DDRP 25A 1 1 0 .abs_section_25a\r
+ _DDRS 24A 1 1 2 .abs_section_24a\r
+ _DDRT 242 1 1 0 .abs_section_242\r
+ _DLCBARD EC 1 1 0 .abs_section_ec\r
+ _DLCBCR1 E8 1 1 0 .abs_section_e8\r
+ _DLCBCR2 EA 1 1 0 .abs_section_ea\r
+ _DLCBDR EB 1 1 0 .abs_section_eb\r
+ _DLCBRSR ED 1 1 0 .abs_section_ed\r
+ _DLCBSVR E9 1 1 0 .abs_section_e9\r
+ _DLCSCR EE 1 1 0 .abs_section_ee\r
+ _DLYCT 69 1 1 0 .abs_section_69\r
+ _EBICTL E 1 1 0 .abs_section_e\r
+ _ECLKDIV 110 1 1 0 .abs_section_110\r
+ _ECMD 116 1 1 0 .abs_section_116\r
+ _ECNFG 113 1 1 0 .abs_section_113\r
+ _EPROT 114 1 1 0 .abs_section_114\r
+ _ESTAT 115 1 1 0 .abs_section_115\r
+ _FCLKDIV 100 1 1 0 .abs_section_100\r
+ _FCMD 106 1 1 0 .abs_section_106\r
+ _FCNFG 103 1 1 0 .abs_section_103\r
+ _FORBYP 3D 1 1 0 .abs_section_3d\r
+ _FPROT 104 1 1 0 .abs_section_104\r
+ _FSEC 101 1 1 0 .abs_section_101\r
+ _FSTAT 105 1 1 0 .abs_section_105\r
+ _HPRIO 1F 1 1 0 .abs_section_1f\r
+ _IBAD E0 1 1 0 .abs_section_e0\r
+ _IBCR E2 1 1 0 .abs_section_e2\r
+ _IBDR E4 1 1 0 .abs_section_e4\r
+ _IBFD E1 1 1 0 .abs_section_e1\r
+ _IBSR E3 1 1 0 .abs_section_e3\r
+ _ICOVW 6A 1 1 0 .abs_section_6a\r
+ _ICPAR 68 1 1 0 .abs_section_68\r
+ _ICSYS 6B 1 1 1 .abs_section_6b\r
+ _INITEE 12 1 1 1 .abs_section_12\r
+ _INITRG 11 1 1 0 .abs_section_11\r
+ _INITRM 10 1 1 1 .abs_section_10\r
+ _INTCR 1E 1 1 1 .abs_section_1e\r
+ _ITCR 15 1 1 0 .abs_section_15\r
+ _ITEST 16 1 1 0 .abs_section_16\r
+ _MCCTL 66 1 1 1 .abs_section_66\r
+ _MCFLG 67 1 1 0 .abs_section_67\r
+ _MEMSIZ0 1C 1 1 0 .abs_section_1c\r
+ _MEMSIZ1 1D 1 1 0 .abs_section_1d\r
+ _MISC 13 1 1 1 .abs_section_13\r
+ _MODE B 1 1 0 .abs_section_b\r
+ _MODRR 257 1 1 0 .abs_section_257\r
+ _MTST0 14 1 1 0 .abs_section_14\r
+ _MTST1 17 1 1 0 .abs_section_17\r
+ _OC7D 43 1 1 0 .abs_section_43\r
+ _OC7M 42 1 1 0 .abs_section_42\r
+ _PACTL 60 1 1 0 .abs_section_60\r
+ _PAFLG 61 1 1 0 .abs_section_61\r
+ _PARTIDH 1A 1 1 0 .abs_section_1a\r
+ _PARTIDL 1B 1 1 0 .abs_section_1b\r
+ _PBCTL 70 1 1 0 .abs_section_70\r
+ _PBFLG 71 1 1 0 .abs_section_71\r
+ _PEAR A 1 1 0 .abs_section_a\r
+ _PERH 264 1 1 0 .abs_section_264\r
+ _PERJ 26C 1 1 0 .abs_section_26c\r
+ _PERM 254 1 1 0 .abs_section_254\r
+ _PERP 25C 1 1 0 .abs_section_25c\r
+ _PERS 24C 1 1 0 .abs_section_24c\r
+ _PERT 244 1 1 0 .abs_section_244\r
+ _PIEH 266 1 1 0 .abs_section_266\r
+ _PIEJ 26E 1 1 0 .abs_section_26e\r
+ _PIEP 25E 1 1 0 .abs_section_25e\r
+ _PIFH 267 1 1 0 .abs_section_267\r
+ _PIFJ 26F 1 1 0 .abs_section_26f\r
+ _PIFP 25F 1 1 0 .abs_section_25f\r
+ _PLLCTL 3A 1 1 3 .abs_section_3a\r
+ _PORTAD0 8F 1 1 0 .abs_section_8f\r
+ _PORTAD1 12F 1 1 0 .abs_section_12f\r
+ _PORTE 8 1 1 0 .abs_section_8\r
+ _PORTK 32 1 1 0 .abs_section_32\r
+ _PPAGE 30 1 1 0 .abs_section_30\r
+ _PPSH 265 1 1 0 .abs_section_265\r
+ _PPSJ 26D 1 1 0 .abs_section_26d\r
+ _PPSM 255 1 1 0 .abs_section_255\r
+ _PPSP 25D 1 1 0 .abs_section_25d\r
+ _PPSS 24D 1 1 0 .abs_section_24d\r
+ _PPST 245 1 1 0 .abs_section_245\r
+ _PTH 260 1 1 0 .abs_section_260\r
+ _PTIH 261 1 1 0 .abs_section_261\r
+ _PTIJ 269 1 1 0 .abs_section_269\r
+ _PTIM 251 1 1 0 .abs_section_251\r
+ _PTIP 259 1 1 0 .abs_section_259\r
+ _PTIS 249 1 1 0 .abs_section_249\r
+ _PTIT 241 1 1 0 .abs_section_241\r
+ _PTJ 268 1 1 0 .abs_section_268\r
+ _PTM 250 1 1 0 .abs_section_250\r
+ _PTP 258 1 1 0 .abs_section_258\r
+ _PTS 248 1 1 1 .abs_section_248\r
+ _PTT 240 1 1 0 .abs_section_240\r
+ _PUCR C 1 1 0 .abs_section_c\r
+ _PWMCAE A4 1 1 0 .abs_section_a4\r
+ _PWMCLK A2 1 1 0 .abs_section_a2\r
+ _PWMCTL A5 1 1 1 .abs_section_a5\r
+ _PWME A0 1 1 0 .abs_section_a0\r
+ _PWMPOL A1 1 1 0 .abs_section_a1\r
+ _PWMPRCLK A3 1 1 0 .abs_section_a3\r
+ _PWMSCLA A8 1 1 0 .abs_section_a8\r
+ _PWMSCLB A9 1 1 0 .abs_section_a9\r
+ _PWMSDN C4 1 1 1 .abs_section_c4\r
+ _RDRH 263 1 1 0 .abs_section_263\r
+ _RDRIV D 1 1 0 .abs_section_d\r
+ _RDRJ 26B 1 1 0 .abs_section_26b\r
+ _RDRM 253 1 1 0 .abs_section_253\r
+ _RDRP 25B 1 1 0 .abs_section_25b\r
+ _RDRS 24B 1 1 0 .abs_section_24b\r
+ _RDRT 243 1 1 0 .abs_section_243\r
+ _REFDV 35 1 1 1 .abs_section_35\r
+ _RTICTL 3B 1 1 0 .abs_section_3b\r
+ _SCI0CR1 CA 1 1 1 .abs_section_ca\r
+ _SCI0CR2 CB 1 1 7 .abs_section_cb\r
+ _SCI0DRH CE 1 1 0 .abs_section_ce\r
+ _SCI0DRL CF 1 1 3 .abs_section_cf\r
+ _SCI0SR1 CC 1 1 2 .abs_section_cc\r
+ _SCI0SR2 CD 1 1 1 .abs_section_cd\r
+ _SCI1CR1 D2 1 1 0 .abs_section_d2\r
+ _SCI1CR2 D3 1 1 0 .abs_section_d3\r
+ _SCI1DRH D6 1 1 0 .abs_section_d6\r
+ _SCI1DRL D7 1 1 0 .abs_section_d7\r
+ _SCI1SR1 D4 1 1 0 .abs_section_d4\r
+ _SCI1SR2 D5 1 1 0 .abs_section_d5\r
+ _SPI0BR DA 1 1 0 .abs_section_da\r
+ _SPI0CR1 D8 1 1 0 .abs_section_d8\r
+ _SPI0CR2 D9 1 1 0 .abs_section_d9\r
+ _SPI0DR DD 1 1 0 .abs_section_dd\r
+ _SPI0SR DB 1 1 0 .abs_section_db\r
+ _SPI1BR F2 1 1 0 .abs_section_f2\r
+ _SPI1CR1 F0 1 1 0 .abs_section_f0\r
+ _SPI1CR2 F1 1 1 0 .abs_section_f1\r
+ _SPI1DR F5 1 1 0 .abs_section_f5\r
+ _SPI1SR F3 1 1 0 .abs_section_f3\r
+ _SPI2BR FA 1 1 0 .abs_section_fa\r
+ _SPI2CR1 F8 1 1 0 .abs_section_f8\r
+ _SPI2CR2 F9 1 1 0 .abs_section_f9\r
+ _SPI2DR FD 1 1 0 .abs_section_fd\r
+ _SPI2SR FB 1 1 0 .abs_section_fb\r
+ _SYNR 34 1 1 1 .abs_section_34\r
+ _TCTL1 48 1 1 1 .abs_section_48\r
+ _TCTL2 49 1 1 1 .abs_section_49\r
+ _TCTL3 4A 1 1 0 .abs_section_4a\r
+ _TCTL4 4B 1 1 0 .abs_section_4b\r
+ _TFLG1 4E 1 1 2 .abs_section_4e\r
+ _TFLG2 4F 1 1 0 .abs_section_4f\r
+ _TIE 4C 1 1 2 .abs_section_4c\r
+ _TIMTST 6D 1 1 0 .abs_section_6d\r
+ _TIOS 40 1 1 1 .abs_section_40\r
+ _TSCR1 46 1 1 3 .abs_section_46\r
+ _TSCR2 4D 1 1 5 .abs_section_4d\r
+ _TTOV 47 1 1 1 .abs_section_47\r
+ _WOMM 256 1 1 0 .abs_section_256\r
+ _WOMS 24E 1 1 0 .abs_section_24e\r
+ _ATD0CTL23 82 2 2 0 .abs_section_82\r
+ _ATD0CTL45 84 2 2 0 .abs_section_84\r
+ _ATD0DR0 90 2 2 0 .abs_section_90\r
+ _ATD0DR1 92 2 2 0 .abs_section_92\r
+ _ATD0DR2 94 2 2 0 .abs_section_94\r
+ _ATD0DR3 96 2 2 0 .abs_section_96\r
+ _ATD0DR4 98 2 2 0 .abs_section_98\r
+ _ATD0DR5 9A 2 2 0 .abs_section_9a\r
+ _ATD0DR6 9C 2 2 0 .abs_section_9c\r
+ _ATD0DR7 9E 2 2 0 .abs_section_9e\r
+ _ATD1CTL23 122 2 2 0 .abs_section_122\r
+ _ATD1CTL45 124 2 2 0 .abs_section_124\r
+ _ATD1DR0 130 2 2 0 .abs_section_130\r
+ _ATD1DR1 132 2 2 0 .abs_section_132\r
+ _ATD1DR2 134 2 2 0 .abs_section_134\r
+ _ATD1DR3 136 2 2 0 .abs_section_136\r
+ _ATD1DR4 138 2 2 0 .abs_section_138\r
+ _ATD1DR5 13A 2 2 0 .abs_section_13a\r
+ _ATD1DR6 13C 2 2 0 .abs_section_13c\r
+ _ATD1DR7 13E 2 2 0 .abs_section_13e\r
+ _DDRAB 2 2 2 1 .abs_section_2\r
+ _MCCNT 76 2 2 0 .abs_section_76\r
+ _PA10H 74 2 2 0 .abs_section_74\r
+ _PA32H 72 2 2 0 .abs_section_72\r
+ _PACN10 64 2 2 0 .abs_section_64\r
+ _PACN32 62 2 2 0 .abs_section_62\r
+ _PORTAB 0 2 2 6 .abs_section_0\r
+ _PWMCNT01 AC 2 2 0 .abs_section_ac\r
+ _PWMCNT23 AE 2 2 0 .abs_section_ae\r
+ _PWMCNT45 B0 2 2 0 .abs_section_b0\r
+ _PWMCNT67 B2 2 2 0 .abs_section_b2\r
+ _PWMDTY01 BC 2 2 0 .abs_section_bc\r
+ _PWMDTY23 BE 2 2 0 .abs_section_be\r
+ _PWMDTY45 C0 2 2 0 .abs_section_c0\r
+ _PWMDTY67 C2 2 2 0 .abs_section_c2\r
+ _PWMPER01 B4 2 2 0 .abs_section_b4\r
+ _PWMPER23 B6 2 2 0 .abs_section_b6\r
+ _PWMPER45 B8 2 2 0 .abs_section_b8\r
+ _PWMPER67 BA 2 2 0 .abs_section_ba\r
+ _SCI0BD C8 2 2 2 .abs_section_c8\r
+ _SCI1BD D0 2 2 0 .abs_section_d0\r
+ _TC0 50 2 2 1 .abs_section_50\r
+ _TC0H 78 2 2 0 .abs_section_78\r
+ _TC1 52 2 2 0 .abs_section_52\r
+ _TC1H 7A 2 2 0 .abs_section_7a\r
+ _TC2 54 2 2 0 .abs_section_54\r
+ _TC2H 7C 2 2 0 .abs_section_7c\r
+ _TC3 56 2 2 0 .abs_section_56\r
+ _TC3H 7E 2 2 0 .abs_section_7e\r
+ _TC4 58 2 2 0 .abs_section_58\r
+ _TC5 5A 2 2 0 .abs_section_5a\r
+ _TC6 5C 2 2 0 .abs_section_5c\r
+ _TC7 5E 2 2 1 .abs_section_5e\r
+ _TCNT 44 2 2 0 .abs_section_44\r
+MODULE: -- Vectors.c.o --\r
+- PROCEDURES:\r
+- VARIABLES:\r
+ _vect FF80 80 128 0 .abs_section_ff80\r
+MODULE: -- RTOSDemo.C.o --\r
+- PROCEDURES:\r
+ main 30809A 9 9 0 .text \r
+- VARIABLES:\r
+MODULE: -- main.c.o --\r
+- PROCEDURES:\r
+ vMain 3080A3 52 82 1 .text \r
+ vErrorChecks 3080F5 33 51 3 .text \r
+ prvCheckOtherTasksAreStillRunning 308128 49 73 2 .text \r
+ vApplicationIdleHook 308171 70 112 2 .text \r
+- VARIABLES:\r
+ STRING.Check.1 C09A 6 6 1 .rodata1 \r
+ xLocalError 1001 1 1 2 .bss \r
+MODULE: -- ParTest.c.o --\r
+- PROCEDURES:\r
+ vParTestSetLED 3081E1 22 34 4 .text \r
+ vParTestToggleLED 308203 14 20 10 .text \r
+- VARIABLES:\r
+MODULE: -- serial.c.o --\r
+- PROCEDURES:\r
+ xSerialPortInitMinimal 308217 24 36 2 .text \r
+ xSerialGetChar 30823B 17 23 2 .text \r
+ xSerialPutChar 318000 1D 29 2 ROM_PAGE31_524\r
+ vCOM0_ISR C300 59 89 1 NON_BANKED \r
+- VARIABLES:\r
+ xRxedChars 1002 2 2 3 .bss \r
+ xCharsForTx 1004 2 2 3 .bss \r
+MODULE: -- tasks.c.o --\r
+- PROCEDURES:\r
+ xTaskCreate 31801D D9 217 48 ROM_PAGE31_524\r
+ vTaskDelete 3180F6 4A 74 4 ROM_PAGE31_524\r
+ vTaskDelayUntil 318140 78 120 6 ROM_PAGE31_524\r
+ vTaskDelay 3181B8 4A 74 16 ROM_PAGE31_524\r
+ uxTaskPriorityGet 318202 26 38 2 ROM_PAGE31_524\r
+ vTaskPrioritySet 328000 6B 107 4 ROM_PAGE32_525\r
+ vTaskSuspend 32806B 47 71 6 ROM_PAGE32_525\r
+ vTaskResume 3280B2 5B 91 6 ROM_PAGE32_525\r
+ vTaskStartScheduler 32810D 35 53 2 ROM_PAGE32_525\r
+ vTaskSuspendAll 328142 13 19 26 ROM_PAGE32_525\r
+ xTaskResumeAll 328155 A5 165 30 ROM_PAGE32_525\r
+ xTaskGetTickCount 3281FA 17 23 6 ROM_PAGE32_525\r
+ uxTaskGetNumberOfTasks 328211 17 23 4 ROM_PAGE32_525\r
+ vTaskIncrementTick 338000 84 132 4 ROM_PAGE33_526\r
+ vTaskSwitchContext 338084 5B 91 4 ROM_PAGE33_526\r
+ vTaskPlaceOnEventList 3380DF 44 68 4 ROM_PAGE33_526\r
+ xTaskRemoveFromEventList 338123 6F 111 8 ROM_PAGE33_526\r
+ prvIdleTask 338192 12 18 3 ROM_PAGE33_526\r
+ prvInitialiseTCBVariables 3381A4 4F 79 2 ROM_PAGE33_526\r
+ prvInitialiseTaskLists 3381F3 41 65 2 ROM_PAGE33_526\r
+ prvCheckTasksWaitingTermination 348000 55 85 2 ROM_PAGE34_527\r
+ prvAllocateTCBAndStack 348055 37 55 2 ROM_PAGE34_527\r
+ prvDeleteTCB 34808C 11 17 2 ROM_PAGE34_527\r
+- VARIABLES:\r
+ STRING.IDLE.2 C0A0 5 5 1 .rodata1 \r
+ pxCurrentTCB 1006 2 2 28 .bss \r
+ uxTasksDeleted 1008 1 1 3 .bss \r
+ uxCurrentNumberOfTasks 1009 1 1 5 .bss \r
+ xTickCount 100A 2 2 14 .bss \r
+ uxTopUsedPriority 100C 1 1 2 .bss \r
+ uxTopReadyPriority 100D 1 1 15 .bss \r
+ xSchedulerRunning 100E 1 1 3 .bss \r
+ uxSchedulerSuspended 100F 1 1 6 .bss \r
+ uxMissedTicks 1010 1 1 4 .bss \r
+ uxTaskNumber.1 1011 1 1 2 .bss \r
+ pxReadyTasksLists 1012 3C 60 11 .bss \r
+ xDelayedTaskList1 104E F 15 2 .bss \r
+ xDelayedTaskList2 105D F 15 2 .bss \r
+ pxDelayedTaskList 106C 2 2 8 .bss \r
+ pxOverflowDelayedTaskList 106E 2 2 6 .bss \r
+ xPendingReadyList 1070 F 15 4 .bss \r
+ xTasksWaitingTermination 107F F 15 5 .bss \r
+ xSuspendedTaskList 108E F 15 2 .bss \r
+MODULE: -- queue.c.o --\r
+- PROCEDURES:\r
+ xQueueCreate 34809D 7C 124 14 ROM_PAGE34_527\r
+ xQueueSend 348119 D4 212 9 ROM_PAGE34_527\r
+ xQueueSendFromISR 3481ED 56 86 2 ROM_PAGE34_527\r
+ xQueueReceive 358000 CE 206 9 ROM_PAGE35_528\r
+ xQueueReceiveFromISR 3580CE 60 96 2 ROM_PAGE35_528\r
+ uxQueueMessagesWaiting 35812E 1B 27 2 ROM_PAGE35_528\r
+ prvUnlockQueue 358149 71 113 8 ROM_PAGE35_528\r
+ prvIsQueueEmpty 3581BA 21 33 2 ROM_PAGE35_528\r
+ prvIsQueueFull 3581DB 24 36 2 ROM_PAGE35_528\r
+- VARIABLES:\r
+MODULE: -- list.c.o --\r
+- PROCEDURES:\r
+ vListInitialise 3581FF 20 32 6 ROM_PAGE35_528\r
+ vListInitialiseItem 35821F 7 7 6 ROM_PAGE35_528\r
+ vListInsertEnd 358226 27 39 16 ROM_PAGE35_528\r
+ vListInsert 368000 5A 90 8 ROM_PAGE36_529\r
+ vListRemove 36805A 23 35 32 ROM_PAGE36_529\r
+- VARIABLES:\r
+MODULE: -- heap_2.c.o --\r
+- PROCEDURES:\r
+ pvPortMalloc 36807D B6 182 14 ROM_PAGE36_529\r
+ vPortFree 368133 34 52 10 ROM_PAGE36_529\r
+- VARIABLES:\r
+ xHeapHasBeenInitialised.1 109D 1 1 2 .bss \r
+ xHeap 109E 2804 10244 2 .bss \r
+ xStart 38A2 4 4 6 .bss \r
+ xEnd 38A6 4 4 4 .bss \r
+MODULE: -- TickTimer.C.o --\r
+- PROCEDURES:\r
+ SetCV 3B811C F 15 4 TickTimer_CODE\r
+ SetPV 3B812B C 12 2 TickTimer_CODE\r
+ HWEnDi 3B8137 8 8 4 TickTimer_CODE\r
+ TickTimer_Enable 3B813F 6 6 2 TickTimer_CODE\r
+ TickTimer_SetFreqHz 3B8145 51 81 2 TickTimer_CODE\r
+ TickTimer_Init 3B8196 15 21 2 TickTimer_CODE\r
+- VARIABLES:\r
+ CmpHighVal 38F2 2 2 2 TickTimer_DATA\r
+MODULE: -- PE_Timer.C.o --\r
+- PROCEDURES:\r
+ PE_Timer_LngHi1 368167 43 67 2 ROM_PAGE36_529\r
+- VARIABLES:\r
+MODULE: -- Byte1.C.o --\r
+- PROCEDURES:\r
+ Byte1_GetMsk 3B81AB D 13 4 Byte1_CODE \r
+ Byte1_PutBit 3B81B8 1F 31 2 Byte1_CODE \r
+ Byte1_NegBit 3B81D7 11 17 2 Byte1_CODE \r
+- VARIABLES:\r
+ Byte1_Table 38F4 8 8 1 Byte1_DATA \r
+MODULE: -- flash.c.o --\r
+- PROCEDURES:\r
+ vStartLEDFlashTasks 3681AA 2A 42 2 ROM_PAGE36_529\r
+ vLEDFlashTask 3681D4 57 87 3 ROM_PAGE36_529\r
+- VARIABLES:\r
+ STRING.LEDx.1 C0A5 5 5 1 .rodata1 \r
+ uxFlashTaskNumber 38AA 1 1 2 .bss \r
+MODULE: -- dynamic.c.o --\r
+- PROCEDURES:\r
+ vStartDynamicPriorityTasks 378000 9B 155 2 ROM_PAGE37_530\r
+ vLimitedIncrementTask 37809B 22 34 3 ROM_PAGE37_530\r
+ vContinuousIncrementTask 3780BD 33 51 3 ROM_PAGE37_530\r
+ vCounterControlTask 3780F0 A0 160 5 ROM_PAGE37_530\r
+ vQueueSendWhenSuspendedTask 378190 38 56 3 ROM_PAGE37_530\r
+ vQueueReceiveWhenSuspendedTask 3781C8 53 83 3 ROM_PAGE37_530\r
+ xAreDynamicPriorityTasksStillRunning 37821B 27 39 2 ROM_PAGE37_530\r
+- VARIABLES:\r
+ STRING.CNT_INC.1 C0AA 8 8 1 .rodata1 \r
+ STRING.LIM_INC.2 C0B2 8 8 1 .rodata1 \r
+ STRING.C_CTRL.3 C0BA 7 7 1 .rodata1 \r
+ STRING.SUSP_TX.4 C0C1 8 8 1 .rodata1 \r
+ STRING.SUSP_RX.5 C0C9 8 8 1 .rodata1 \r
+ usCheckVariable 38AB 2 2 4 .bss \r
+ xSuspendedQueueSendError 38AD 1 1 2 .bss \r
+ xSuspendedQueueReceiveError 38AE 1 1 3 .bss \r
+ ulValueToSend.6 38AF 4 4 5 .bss \r
+ ulExpectedValue.7 38B3 4 4 6 .bss \r
+ usLastTaskCheck.9 38B7 2 2 2 .bss \r
+ xContinousIncrementHandle 38B9 2 2 5 .bss \r
+ xLimitedIncrementHandle 38BB 2 2 2 .bss \r
+ ulCounter 38BD 4 4 10 .bss \r
+ ulReceivedValue.8 38C1 4 4 3 .bss \r
+ xSuspendedTestQueue 38EC 2 2 3 .common \r
+MODULE: -- PollQ.c.o --\r
+- PROCEDURES:\r
+ vStartPolledQueueTasks 388000 49 73 2 ROM_PAGE38_531\r
+ vPolledQueueProducer 388049 4F 79 3 ROM_PAGE38_531\r
+ vPolledQueueConsumer 388098 5C 92 3 ROM_PAGE38_531\r
+ xArePollingQueuesStillRunning 3880F4 1D 29 2 ROM_PAGE38_531\r
+- VARIABLES:\r
+ STRING.QConsNB.2 C0D1 8 8 1 .rodata1 \r
+ STRING.QProdNB.3 C0D9 8 8 1 .rodata1 \r
+ xPollingConsumerCount 38C5 1 1 3 .bss \r
+ xPollingProducerCount 38C6 1 1 3 .bss \r
+ xPolledQueue.1 38C7 2 2 3 .bss \r
+MODULE: -- comtest.c.o --\r
+- PROCEDURES:\r
+ vAltStartComTestTasks 388111 4D 77 2 ROM_PAGE38_531\r
+ vComTxTask 38815E 51 81 3 ROM_PAGE38_531\r
+ vComRxTask 3881AF 6A 106 3 ROM_PAGE38_531\r
+ xAreComTestTasksStillRunning 388219 15 21 2 ROM_PAGE38_531\r
+- VARIABLES:\r
+ STRING.COMTx.1 C0E1 6 6 1 .rodata1 \r
+ STRING.COMRx.2 C0E7 6 6 1 .rodata1 \r
+ xPort 38C9 2 2 2 .bss \r
+ uxBaseLED 38CB 1 1 5 .bss \r
+ uxRxLoops 38CC 1 1 3 .bss \r
+MODULE: -- COM0.C.o --\r
+- PROCEDURES:\r
+ HWEnDi 3B81E8 A 10 2 COM0_CODE \r
+ COM0_SetBaudRateMode 3B81F2 19 25 2 COM0_CODE \r
+ COM0_Init 3B820B 20 32 2 COM0_CODE \r
+- VARIABLES:\r
+ COM0_PrescHigh.1 38FC 8 8 1 COM0_DATA \r
+ SerFlag 3904 2 2 1 COM0_DATA \r
+ PrescHigh 3906 2 2 2 COM0_DATA \r
+ NumMode 3908 1 1 2 COM0_DATA \r
+MODULE: -- port.c.o --\r
+- PROCEDURES:\r
+ pxPortInitialiseStack 398000 31 49 2 ROM_PAGE39_532\r
+ prvSetupTimerInterrupt 398031 C 12 2 ROM_PAGE39_532\r
+ xPortStartScheduler 39803D 4 4 2 ROM_PAGE39_532\r
+ xBankedStartScheduler C359 13 19 1 NON_BANKED \r
+ vPortYield C36C 1D 29 1 NON_BANKED \r
+ vPortTickInterrupt C389 25 37 1 NON_BANKED \r
+- VARIABLES:\r
+ uxCriticalNesting 1000 1 1 101 .data \r
+MODULE: -- integer.c.o --\r
+- PROCEDURES:\r
+ vStartIntegerMathTasks 398041 33 51 2 ROM_PAGE39_532\r
+ vCompeteingIntMathTask 398074 87 135 3 ROM_PAGE39_532\r
+ xAreIntegerMathsTaskStillRunning 3980FB 25 37 2 ROM_PAGE39_532\r
+- VARIABLES:\r
+ STRING.IntMath.1 C0ED 8 8 1 .rodata1 \r
+ xTaskCheck 38CD 1 1 3 .bss \r
+MODULE: -- BlockQ.c.o --\r
+- PROCEDURES:\r
+ vStartBlockingQueueTasks 3A8000 143 323 7 ROM_PAGE3A_533\r
+ vBlockingQueueProducer 3A8143 3A 58 9 ROM_PAGE3A_533\r
+ vBlockingQueueConsumer 3A817D 45 69 9 ROM_PAGE3A_533\r
+ xAreBlockingQueuesStillRunning 3A81C2 49 73 2 ROM_PAGE3A_533\r
+- VARIABLES:\r
+ STRING.QConsB1.1 C0F5 8 8 1 .rodata1 \r
+ STRING.QProdB2.2 C0FD 8 8 1 .rodata1 \r
+ STRING.QProdB3.3 C105 8 8 1 .rodata1 \r
+ STRING.QConsB4.4 C10D 8 8 1 .rodata1 \r
+ STRING.QProdB5.5 C115 8 8 1 .rodata1 \r
+ STRING.QConsB6.6 C11D 8 8 1 .rodata1 \r
+ sBlockingConsumerCount 38CE 6 6 5 .bss \r
+ sBlockingProducerCount 38D4 6 6 5 .bss \r
+ sLastBlockingConsumerCount.7 38DA 6 6 2 .bss \r
+ sLastBlockingProducerCount.8 38E0 6 6 2 .bss \r
+MODULE: -- death.c.o --\r
+- PROCEDURES:\r
+ vCreateSuicidalTasks 3A820B 33 51 2 ROM_PAGE3A_533\r
+ vSuicidalTask 3B8000 52 82 12 ROM_PAGE3B_534\r
+ vCreateTasks 3B8052 94 148 4 ROM_PAGE3B_534\r
+ xIsCreateTaskStillRunning 3B80E6 36 54 2 ROM_PAGE3B_534\r
+- VARIABLES:\r
+ STRING.CREATOR.1 C125 8 8 1 .rodata1 \r
+ STRING.SUICIDE1.2 C12D 9 9 1 .rodata1 \r
+ STRING.SUICIDE2.3 C136 9 9 1 .rodata1 \r
+ STRING.SUICIDE1.4 C13F 9 9 1 .rodata1 \r
+ STRING.SUICIDE2.5 C148 9 9 1 .rodata1 \r
+ usCreationCount 38E6 2 2 4 .bss \r
+ uxTasksRunningAtStart 38E8 1 1 4 .bss \r
+ usLastCreationCount.6 38E9 2 2 2 .bss \r
+ uxTasksRunningNow.7 38EB 1 1 1 .bss \r
+ xCreatedTask1 38EE 2 2 2 .common \r
+ xCreatedTask2 38F0 2 2 2 .common \r
+\r
+*********************************************************************************************\r
+MODULE STATISTIC\r
+ Name Data Code Const\r
+---------------------------------------------------------------------------------------------\r
+ Start12.c.o 0 59 0\r
+ STRING.C.o (ansibi.lib) 0 113 0\r
+ rtshc12.c.o (ansibi.lib) 0 412 0\r
+ Cpu.C.o 0 125 0\r
+ IO_Map.C.o 577 0 0\r
+ Vectors.c.o 0 0 128\r
+ RTOSDemo.C.o 0 9 0\r
+ main.c.o 1 318 6\r
+ ParTest.c.o 0 54 0\r
+ serial.c.o 4 177 0\r
+ tasks.c.o 151 1796 5\r
+ queue.c.o 0 933 0\r
+ list.c.o 0 203 0\r
+ heap_2.c.o 10253 234 0\r
+ TickTimer.C.o 2 143 0\r
+ PE_Timer.C.o 0 67 0\r
+ Byte1.C.o 8 61 0\r
+ flash.c.o 1 129 5\r
+ dynamic.c.o 28 578 39\r
+ PollQ.c.o 4 273 16\r
+ comtest.c.o 4 285 12\r
+ COM0.C.o 13 67 0\r
+ port.c.o 1 150 0\r
+ integer.c.o 1 223 8\r
+ BlockQ.c.o 24 523 48\r
+ death.c.o 10 335 44\r
+ other 128 30 27\r
+\r
+*********************************************************************************************\r
+SECTION USE IN OBJECT-ALLOCATION SECTION\r
+---------------------------------------------------------------------------------------------\r
+SECTION: ".text"\r
+ Init memcpy memset strncpy main vMain vErrorChecks \r
+ prvCheckOtherTasksAreStillRunning vApplicationIdleHook vParTestSetLED \r
+ vParTestToggleLED xSerialPortInitMinimal xSerialGetChar \r
+SECTION: ".data"\r
+ uxCriticalNesting \r
+SECTION: ".bss"\r
+ xLocalError xRxedChars xCharsForTx pxCurrentTCB uxTasksDeleted \r
+ uxCurrentNumberOfTasks xTickCount uxTopUsedPriority uxTopReadyPriority \r
+ xSchedulerRunning uxSchedulerSuspended uxMissedTicks uxTaskNumber.1 \r
+ pxReadyTasksLists xDelayedTaskList1 xDelayedTaskList2 pxDelayedTaskList \r
+ pxOverflowDelayedTaskList xPendingReadyList xTasksWaitingTermination \r
+ xSuspendedTaskList xHeapHasBeenInitialised.1 xHeap xStart xEnd \r
+ uxFlashTaskNumber usCheckVariable xSuspendedQueueSendError \r
+ xSuspendedQueueReceiveError ulValueToSend.6 ulExpectedValue.7 \r
+ usLastTaskCheck.9 xContinousIncrementHandle xLimitedIncrementHandle ulCounter \r
+ ulReceivedValue.8 xPollingConsumerCount xPollingProducerCount xPolledQueue.1 \r
+ xPort uxBaseLED uxRxLoops xTaskCheck sBlockingConsumerCount \r
+ sBlockingProducerCount sLastBlockingConsumerCount.7 \r
+ sLastBlockingProducerCount.8 usCreationCount uxTasksRunningAtStart \r
+ usLastCreationCount.6 uxTasksRunningNow.7 \r
+SECTION: ".init"\r
+ _EntryPoint PE_low_level_init \r
+SECTION: ".rodata1"\r
+ STRING.Check.1 STRING.IDLE.2 STRING.LEDx.1 STRING.CNT_INC.1 STRING.LIM_INC.2 \r
+ STRING.C_CTRL.3 STRING.SUSP_TX.4 STRING.SUSP_RX.5 STRING.QConsNB.2 \r
+ STRING.QProdNB.3 STRING.COMTx.1 STRING.COMRx.2 STRING.IntMath.1 \r
+ STRING.QConsB1.1 STRING.QProdB2.2 STRING.QProdB3.3 STRING.QConsB4.4 \r
+ STRING.QProdB5.5 STRING.QConsB6.6 STRING.CREATOR.1 STRING.SUICIDE1.2 \r
+ STRING.SUICIDE2.3 STRING.SUICIDE1.4 STRING.SUICIDE2.5 \r
+SECTION: "NON_BANKED"\r
+ _Startup _LCMP _LCMP_P _LNEG _LINC _LMUL _lDivMod _LDIVU _NEG_P _LDIVS \r
+ Cpu_Interrupt vCOM0_ISR xBankedStartScheduler vPortYield vPortTickInterrupt \r
+SECTION: ".common"\r
+ xSuspendedTestQueue xCreatedTask1 xCreatedTask2 \r
+SECTION: "TickTimer_CODE"\r
+ SetCV SetPV HWEnDi TickTimer_Enable TickTimer_SetFreqHz TickTimer_Init \r
+SECTION: "Byte1_CODE"\r
+ Byte1_GetMsk Byte1_PutBit Byte1_NegBit \r
+SECTION: "COM0_CODE"\r
+ HWEnDi COM0_SetBaudRateMode COM0_Init \r
+SECTION: ".abs_section_3f"\r
+ _ARMCOP \r
+SECTION: ".abs_section_8d"\r
+ _ATD0DIEN \r
+SECTION: ".abs_section_86"\r
+ _ATD0STAT0 \r
+SECTION: ".abs_section_8b"\r
+ _ATD0STAT1 \r
+SECTION: ".abs_section_12d"\r
+ _ATD1DIEN \r
+SECTION: ".abs_section_126"\r
+ _ATD1STAT0 \r
+SECTION: ".abs_section_12b"\r
+ _ATD1STAT1 \r
+SECTION: ".abs_section_ff06"\r
+ _BDMCCR \r
+SECTION: ".abs_section_ff07"\r
+ _BDMINR \r
+SECTION: ".abs_section_ff01"\r
+ _BDMSTS \r
+SECTION: ".abs_section_2b"\r
+ _BKP0H \r
+SECTION: ".abs_section_2c"\r
+ _BKP0L \r
+SECTION: ".abs_section_2a"\r
+ _BKP0X \r
+SECTION: ".abs_section_2e"\r
+ _BKP1H \r
+SECTION: ".abs_section_2f"\r
+ _BKP1L \r
+SECTION: ".abs_section_2d"\r
+ _BKP1X \r
+SECTION: ".abs_section_28"\r
+ _BKPCT0 \r
+SECTION: ".abs_section_29"\r
+ _BKPCT1 \r
+SECTION: ".abs_section_142"\r
+ _CAN0BTR0 \r
+SECTION: ".abs_section_143"\r
+ _CAN0BTR1 \r
+SECTION: ".abs_section_140"\r
+ _CAN0CTL0 \r
+SECTION: ".abs_section_141"\r
+ _CAN0CTL1 \r
+SECTION: ".abs_section_14b"\r
+ _CAN0IDAC \r
+SECTION: ".abs_section_150"\r
+ _CAN0IDAR0 \r
+SECTION: ".abs_section_151"\r
+ _CAN0IDAR1 \r
+SECTION: ".abs_section_152"\r
+ _CAN0IDAR2 \r
+SECTION: ".abs_section_153"\r
+ _CAN0IDAR3 \r
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+ _CAN0IDAR4 \r
+SECTION: ".abs_section_159"\r
+ _CAN0IDAR5 \r
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+ _CAN0IDAR6 \r
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+ _CAN0IDAR7 \r
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+ _CAN0IDMR0 \r
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+ _CAN0IDMR1 \r
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+ _CAN0IDMR4 \r
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+ _CAN0IDMR5 \r
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+ _CAN0IDMR6 \r
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+ _CAN0IDMR7 \r
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+ _CAN0RFLG \r
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+ _CAN0RIER \r
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+ _CAN0RXDLR \r
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+ _CAN0RXDSR0 \r
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+ _CAN0RXDSR1 \r
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+ _CAN0RXDSR2 \r
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+ _CAN0RXDSR3 \r
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+ _CAN0RXDSR4 \r
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+ _CAN0RXDSR5 \r
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+ _CAN0RXDSR6 \r
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+ _CAN0RXDSR7 \r
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+ _CAN0RXERR \r
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+ _CAN0RXIDR0 \r
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+ _CAN0RXIDR1 \r
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+ _CAN0RXIDR2 \r
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+ _CAN0RXIDR3 \r
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+ _CAN0TAAK \r
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+ _CAN0TARQ \r
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+ _CAN0TBSEL \r
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+ _CAN0TFLG \r
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+ _CAN0TIER \r
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+ _CAN0TXDLR \r
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+ _CAN0TXDSR0 \r
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+ _CAN0TXDSR1 \r
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+ _CAN0TXDSR2 \r
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+ _CAN0TXDSR3 \r
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+ _CAN0TXDSR4 \r
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+ _CAN0TXDSR5 \r
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+ _CAN0TXDSR6 \r
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+ _CAN0TXDSR7 \r
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+ _CAN0TXERR \r
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+ _CAN0TXIDR0 \r
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+ _CAN0TXIDR1 \r
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+ _CAN0TXIDR2 \r
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+ _CAN0TXIDR3 \r
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+ _CAN0TXTBPR \r
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+ _CAN1BTR0 \r
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+ _CAN1BTR1 \r
+SECTION: ".abs_section_180"\r
+ _CAN1CTL0 \r
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+ _CAN1CTL1 \r
+SECTION: ".abs_section_18b"\r
+ _CAN1IDAC \r
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+ _CAN1IDAR0 \r
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+ _CAN1IDAR1 \r
+SECTION: ".abs_section_192"\r
+ _CAN1IDAR2 \r
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+ _CAN1IDAR3 \r
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+ _CAN1IDAR4 \r
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+ _CAN1IDAR5 \r
+SECTION: ".abs_section_19a"\r
+ _CAN1IDAR6 \r
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+ _CAN1IDAR7 \r
+SECTION: ".abs_section_194"\r
+ _CAN1IDMR0 \r
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+ _CAN1IDMR1 \r
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+ _CAN1IDMR2 \r
+SECTION: ".abs_section_197"\r
+ _CAN1IDMR3 \r
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+ _CAN1IDMR4 \r
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+ _CAN1IDMR5 \r
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+ _CAN1IDMR6 \r
+SECTION: ".abs_section_19f"\r
+ _CAN1IDMR7 \r
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+ _CAN1RFLG \r
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+ _CAN1RIER \r
+SECTION: ".abs_section_1ac"\r
+ _CAN1RXDLR \r
+SECTION: ".abs_section_1a4"\r
+ _CAN1RXDSR0 \r
+SECTION: ".abs_section_1a5"\r
+ _CAN1RXDSR1 \r
+SECTION: ".abs_section_1a6"\r
+ _CAN1RXDSR2 \r
+SECTION: ".abs_section_1a7"\r
+ _CAN1RXDSR3 \r
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+ _CAN1RXDSR4 \r
+SECTION: ".abs_section_1a9"\r
+ _CAN1RXDSR5 \r
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+ _CAN1RXDSR6 \r
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+ _CAN1RXDSR7 \r
+SECTION: ".abs_section_18e"\r
+ _CAN1RXERR \r
+SECTION: ".abs_section_1a0"\r
+ _CAN1RXIDR0 \r
+SECTION: ".abs_section_1a1"\r
+ _CAN1RXIDR1 \r
+SECTION: ".abs_section_1a2"\r
+ _CAN1RXIDR2 \r
+SECTION: ".abs_section_1a3"\r
+ _CAN1RXIDR3 \r
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+ _CAN1TAAK \r
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+ _CAN1TARQ \r
+SECTION: ".abs_section_18a"\r
+ _CAN1TBSEL \r
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+ _CAN1TFLG \r
+SECTION: ".abs_section_187"\r
+ _CAN1TIER \r
+SECTION: ".abs_section_1bc"\r
+ _CAN1TXDLR \r
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+ _SPI1BR \r
+SECTION: ".abs_section_f0"\r
+ _SPI1CR1 \r
+SECTION: ".abs_section_f1"\r
+ _SPI1CR2 \r
+SECTION: ".abs_section_f5"\r
+ _SPI1DR \r
+SECTION: ".abs_section_f3"\r
+ _SPI1SR \r
+SECTION: ".abs_section_fa"\r
+ _SPI2BR \r
+SECTION: ".abs_section_f8"\r
+ _SPI2CR1 \r
+SECTION: ".abs_section_f9"\r
+ _SPI2CR2 \r
+SECTION: ".abs_section_fd"\r
+ _SPI2DR \r
+SECTION: ".abs_section_fb"\r
+ _SPI2SR \r
+SECTION: ".abs_section_34"\r
+ _SYNR \r
+SECTION: ".abs_section_48"\r
+ _TCTL1 \r
+SECTION: ".abs_section_49"\r
+ _TCTL2 \r
+SECTION: ".abs_section_4a"\r
+ _TCTL3 \r
+SECTION: ".abs_section_4b"\r
+ _TCTL4 \r
+SECTION: ".abs_section_4e"\r
+ _TFLG1 \r
+SECTION: ".abs_section_4f"\r
+ _TFLG2 \r
+SECTION: ".abs_section_4c"\r
+ _TIE \r
+SECTION: ".abs_section_6d"\r
+ _TIMTST \r
+SECTION: ".abs_section_40"\r
+ _TIOS \r
+SECTION: ".abs_section_46"\r
+ _TSCR1 \r
+SECTION: ".abs_section_4d"\r
+ _TSCR2 \r
+SECTION: ".abs_section_47"\r
+ _TTOV \r
+SECTION: ".abs_section_256"\r
+ _WOMM \r
+SECTION: ".abs_section_24e"\r
+ _WOMS \r
+SECTION: ".abs_section_82"\r
+ _ATD0CTL23 \r
+SECTION: ".abs_section_84"\r
+ _ATD0CTL45 \r
+SECTION: ".abs_section_90"\r
+ _ATD0DR0 \r
+SECTION: ".abs_section_92"\r
+ _ATD0DR1 \r
+SECTION: ".abs_section_94"\r
+ _ATD0DR2 \r
+SECTION: ".abs_section_96"\r
+ _ATD0DR3 \r
+SECTION: ".abs_section_98"\r
+ _ATD0DR4 \r
+SECTION: ".abs_section_9a"\r
+ _ATD0DR5 \r
+SECTION: ".abs_section_9c"\r
+ _ATD0DR6 \r
+SECTION: ".abs_section_9e"\r
+ _ATD0DR7 \r
+SECTION: ".abs_section_122"\r
+ _ATD1CTL23 \r
+SECTION: ".abs_section_124"\r
+ _ATD1CTL45 \r
+SECTION: ".abs_section_130"\r
+ _ATD1DR0 \r
+SECTION: ".abs_section_132"\r
+ _ATD1DR1 \r
+SECTION: ".abs_section_134"\r
+ _ATD1DR2 \r
+SECTION: ".abs_section_136"\r
+ _ATD1DR3 \r
+SECTION: ".abs_section_138"\r
+ _ATD1DR4 \r
+SECTION: ".abs_section_13a"\r
+ _ATD1DR5 \r
+SECTION: ".abs_section_13c"\r
+ _ATD1DR6 \r
+SECTION: ".abs_section_13e"\r
+ _ATD1DR7 \r
+SECTION: ".abs_section_2"\r
+ _DDRAB \r
+SECTION: ".abs_section_76"\r
+ _MCCNT \r
+SECTION: ".abs_section_74"\r
+ _PA10H \r
+SECTION: ".abs_section_72"\r
+ _PA32H \r
+SECTION: ".abs_section_64"\r
+ _PACN10 \r
+SECTION: ".abs_section_62"\r
+ _PACN32 \r
+SECTION: ".abs_section_0"\r
+ _PORTAB \r
+SECTION: ".abs_section_ac"\r
+ _PWMCNT01 \r
+SECTION: ".abs_section_ae"\r
+ _PWMCNT23 \r
+SECTION: ".abs_section_b0"\r
+ _PWMCNT45 \r
+SECTION: ".abs_section_b2"\r
+ _PWMCNT67 \r
+SECTION: ".abs_section_bc"\r
+ _PWMDTY01 \r
+SECTION: ".abs_section_be"\r
+ _PWMDTY23 \r
+SECTION: ".abs_section_c0"\r
+ _PWMDTY45 \r
+SECTION: ".abs_section_c2"\r
+ _PWMDTY67 \r
+SECTION: ".abs_section_b4"\r
+ _PWMPER01 \r
+SECTION: ".abs_section_b6"\r
+ _PWMPER23 \r
+SECTION: ".abs_section_b8"\r
+ _PWMPER45 \r
+SECTION: ".abs_section_ba"\r
+ _PWMPER67 \r
+SECTION: ".abs_section_c8"\r
+ _SCI0BD \r
+SECTION: ".abs_section_d0"\r
+ _SCI1BD \r
+SECTION: ".abs_section_50"\r
+ _TC0 \r
+SECTION: ".abs_section_78"\r
+ _TC0H \r
+SECTION: ".abs_section_52"\r
+ _TC1 \r
+SECTION: ".abs_section_7a"\r
+ _TC1H \r
+SECTION: ".abs_section_54"\r
+ _TC2 \r
+SECTION: ".abs_section_7c"\r
+ _TC2H \r
+SECTION: ".abs_section_56"\r
+ _TC3 \r
+SECTION: ".abs_section_7e"\r
+ _TC3H \r
+SECTION: ".abs_section_58"\r
+ _TC4 \r
+SECTION: ".abs_section_5a"\r
+ _TC5 \r
+SECTION: ".abs_section_5c"\r
+ _TC6 \r
+SECTION: ".abs_section_5e"\r
+ _TC7 \r
+SECTION: ".abs_section_44"\r
+ _TCNT \r
+SECTION: ".abs_section_ff80"\r
+ _vect \r
+SECTION: "TickTimer_DATA"\r
+ CmpHighVal \r
+SECTION: "Byte1_DATA"\r
+ Byte1_Table \r
+SECTION: "COM0_DATA"\r
+ COM0_PrescHigh.1 SerFlag PrescHigh NumMode \r
+SECTION: "ROM_PAGE31_524"\r
+ xSerialPutChar xTaskCreate vTaskDelete vTaskDelayUntil vTaskDelay \r
+ uxTaskPriorityGet \r
+SECTION: "ROM_PAGE32_525"\r
+ vTaskPrioritySet vTaskSuspend vTaskResume vTaskStartScheduler \r
+ vTaskSuspendAll xTaskResumeAll xTaskGetTickCount uxTaskGetNumberOfTasks \r
+SECTION: "ROM_PAGE33_526"\r
+ vTaskIncrementTick vTaskSwitchContext vTaskPlaceOnEventList \r
+ xTaskRemoveFromEventList prvIdleTask prvInitialiseTCBVariables \r
+ prvInitialiseTaskLists \r
+SECTION: "ROM_PAGE34_527"\r
+ prvCheckTasksWaitingTermination prvAllocateTCBAndStack prvDeleteTCB \r
+ xQueueCreate xQueueSend xQueueSendFromISR \r
+SECTION: "ROM_PAGE35_528"\r
+ xQueueReceive xQueueReceiveFromISR uxQueueMessagesWaiting prvUnlockQueue \r
+ prvIsQueueEmpty prvIsQueueFull vListInitialise vListInitialiseItem \r
+ vListInsertEnd \r
+SECTION: "ROM_PAGE36_529"\r
+ vListInsert vListRemove pvPortMalloc vPortFree PE_Timer_LngHi1 \r
+ vStartLEDFlashTasks vLEDFlashTask \r
+SECTION: "ROM_PAGE37_530"\r
+ vStartDynamicPriorityTasks vLimitedIncrementTask vContinuousIncrementTask \r
+ vCounterControlTask vQueueSendWhenSuspendedTask \r
+ vQueueReceiveWhenSuspendedTask xAreDynamicPriorityTasksStillRunning \r
+SECTION: "ROM_PAGE38_531"\r
+ vStartPolledQueueTasks vPolledQueueProducer vPolledQueueConsumer \r
+ xArePollingQueuesStillRunning vAltStartComTestTasks vComTxTask vComRxTask \r
+ xAreComTestTasksStillRunning \r
+SECTION: "ROM_PAGE39_532"\r
+ pxPortInitialiseStack prvSetupTimerInterrupt xPortStartScheduler \r
+ vStartIntegerMathTasks vCompeteingIntMathTask \r
+ xAreIntegerMathsTaskStillRunning \r
+SECTION: "ROM_PAGE3A_533"\r
+ vStartBlockingQueueTasks vBlockingQueueProducer vBlockingQueueConsumer \r
+ xAreBlockingQueuesStillRunning vCreateSuicidalTasks \r
+SECTION: "ROM_PAGE3B_534"\r
+ vSuicidalTask vCreateTasks xIsCreateTaskStillRunning \r
+\r
+*********************************************************************************************\r
+OBJECT LIST SORTED BY ADDRESS\r
+ Name Addr hSize dSize Ref Section RLIB\r
+---------------------------------------------------------------------------------------------\r
+ _PORTAB 0 2 2 6 .abs_section_0\r
+ _DDRAB 2 2 2 1 .abs_section_2\r
+ _PORTE 8 1 1 0 .abs_section_8\r
+ _DDRE 9 1 1 0 .abs_section_9\r
+ _PEAR A 1 1 0 .abs_section_a\r
+ _MODE B 1 1 0 .abs_section_b\r
+ _PUCR C 1 1 0 .abs_section_c\r
+ _RDRIV D 1 1 0 .abs_section_d\r
+ _EBICTL E 1 1 0 .abs_section_e\r
+ _INITRM 10 1 1 1 .abs_section_10\r
+ _INITRG 11 1 1 0 .abs_section_11\r
+ _INITEE 12 1 1 1 .abs_section_12\r
+ _MISC 13 1 1 1 .abs_section_13\r
+ _MTST0 14 1 1 0 .abs_section_14\r
+ _ITCR 15 1 1 0 .abs_section_15\r
+ _ITEST 16 1 1 0 .abs_section_16\r
+ _MTST1 17 1 1 0 .abs_section_17\r
+ _PARTIDH 1A 1 1 0 .abs_section_1a\r
+ _PARTIDL 1B 1 1 0 .abs_section_1b\r
+ _MEMSIZ0 1C 1 1 0 .abs_section_1c\r
+ _MEMSIZ1 1D 1 1 0 .abs_section_1d\r
+ _INTCR 1E 1 1 1 .abs_section_1e\r
+ _HPRIO 1F 1 1 0 .abs_section_1f\r
+ _BKPCT0 28 1 1 0 .abs_section_28\r
+ _BKPCT1 29 1 1 0 .abs_section_29\r
+ _BKP0X 2A 1 1 0 .abs_section_2a\r
+ _BKP0H 2B 1 1 0 .abs_section_2b\r
+ _BKP0L 2C 1 1 0 .abs_section_2c\r
+ _BKP1X 2D 1 1 0 .abs_section_2d\r
+ _BKP1H 2E 1 1 0 .abs_section_2e\r
+ _BKP1L 2F 1 1 0 .abs_section_2f\r
+ _PPAGE 30 1 1 0 .abs_section_30\r
+ _PORTK 32 1 1 0 .abs_section_32\r
+ _DDRK 33 1 1 0 .abs_section_33\r
+ _SYNR 34 1 1 1 .abs_section_34\r
+ _REFDV 35 1 1 1 .abs_section_35\r
+ _CTFLG 36 1 1 0 .abs_section_36\r
+ _CRGFLG 37 1 1 1 .abs_section_37\r
+ _CRGINT 38 1 1 0 .abs_section_38\r
+ _CLKSEL 39 1 1 3 .abs_section_39\r
+ _PLLCTL 3A 1 1 3 .abs_section_3a\r
+ _RTICTL 3B 1 1 0 .abs_section_3b\r
+ _COPCTL 3C 1 1 0 .abs_section_3c\r
+ _FORBYP 3D 1 1 0 .abs_section_3d\r
+ _CTCTL 3E 1 1 0 .abs_section_3e\r
+ _ARMCOP 3F 1 1 0 .abs_section_3f\r
+ _TIOS 40 1 1 1 .abs_section_40\r
+ _CFORC 41 1 1 0 .abs_section_41\r
+ _OC7M 42 1 1 0 .abs_section_42\r
+ _OC7D 43 1 1 0 .abs_section_43\r
+ _TCNT 44 2 2 0 .abs_section_44\r
+ _TSCR1 46 1 1 3 .abs_section_46\r
+ _TTOV 47 1 1 1 .abs_section_47\r
+ _TCTL1 48 1 1 1 .abs_section_48\r
+ _TCTL2 49 1 1 1 .abs_section_49\r
+ _TCTL3 4A 1 1 0 .abs_section_4a\r
+ _TCTL4 4B 1 1 0 .abs_section_4b\r
+ _TIE 4C 1 1 2 .abs_section_4c\r
+ _TSCR2 4D 1 1 5 .abs_section_4d\r
+ _TFLG1 4E 1 1 2 .abs_section_4e\r
+ _TFLG2 4F 1 1 0 .abs_section_4f\r
+ _TC0 50 2 2 1 .abs_section_50\r
+ _TC1 52 2 2 0 .abs_section_52\r
+ _TC2 54 2 2 0 .abs_section_54\r
+ _TC3 56 2 2 0 .abs_section_56\r
+ _TC4 58 2 2 0 .abs_section_58\r
+ _TC5 5A 2 2 0 .abs_section_5a\r
+ _TC6 5C 2 2 0 .abs_section_5c\r
+ _TC7 5E 2 2 1 .abs_section_5e\r
+ _PACTL 60 1 1 0 .abs_section_60\r
+ _PAFLG 61 1 1 0 .abs_section_61\r
+ _PACN32 62 2 2 0 .abs_section_62\r
+ _PACN10 64 2 2 0 .abs_section_64\r
+ _MCCTL 66 1 1 1 .abs_section_66\r
+ _MCFLG 67 1 1 0 .abs_section_67\r
+ _ICPAR 68 1 1 0 .abs_section_68\r
+ _DLYCT 69 1 1 0 .abs_section_69\r
+ _ICOVW 6A 1 1 0 .abs_section_6a\r
+ _ICSYS 6B 1 1 1 .abs_section_6b\r
+ _TIMTST 6D 1 1 0 .abs_section_6d\r
+ _PBCTL 70 1 1 0 .abs_section_70\r
+ _PBFLG 71 1 1 0 .abs_section_71\r
+ _PA32H 72 2 2 0 .abs_section_72\r
+ _PA10H 74 2 2 0 .abs_section_74\r
+ _MCCNT 76 2 2 0 .abs_section_76\r
+ _TC0H 78 2 2 0 .abs_section_78\r
+ _TC1H 7A 2 2 0 .abs_section_7a\r
+ _TC2H 7C 2 2 0 .abs_section_7c\r
+ _TC3H 7E 2 2 0 .abs_section_7e\r
+ _ATD0CTL23 82 2 2 0 .abs_section_82\r
+ _ATD0CTL45 84 2 2 0 .abs_section_84\r
+ _ATD0STAT0 86 1 1 0 .abs_section_86\r
+ _ATD0STAT1 8B 1 1 0 .abs_section_8b\r
+ _ATD0DIEN 8D 1 1 0 .abs_section_8d\r
+ _PORTAD0 8F 1 1 0 .abs_section_8f\r
+ _ATD0DR0 90 2 2 0 .abs_section_90\r
+ _ATD0DR1 92 2 2 0 .abs_section_92\r
+ _ATD0DR2 94 2 2 0 .abs_section_94\r
+ _ATD0DR3 96 2 2 0 .abs_section_96\r
+ _ATD0DR4 98 2 2 0 .abs_section_98\r
+ _ATD0DR5 9A 2 2 0 .abs_section_9a\r
+ _ATD0DR6 9C 2 2 0 .abs_section_9c\r
+ _ATD0DR7 9E 2 2 0 .abs_section_9e\r
+ _PWME A0 1 1 0 .abs_section_a0\r
+ _PWMPOL A1 1 1 0 .abs_section_a1\r
+ _PWMCLK A2 1 1 0 .abs_section_a2\r
+ _PWMPRCLK A3 1 1 0 .abs_section_a3\r
+ _PWMCAE A4 1 1 0 .abs_section_a4\r
+ _PWMCTL A5 1 1 1 .abs_section_a5\r
+ _PWMSCLA A8 1 1 0 .abs_section_a8\r
+ _PWMSCLB A9 1 1 0 .abs_section_a9\r
+ _PWMCNT01 AC 2 2 0 .abs_section_ac\r
+ _PWMCNT23 AE 2 2 0 .abs_section_ae\r
+ _PWMCNT45 B0 2 2 0 .abs_section_b0\r
+ _PWMCNT67 B2 2 2 0 .abs_section_b2\r
+ _PWMPER01 B4 2 2 0 .abs_section_b4\r
+ _PWMPER23 B6 2 2 0 .abs_section_b6\r
+ _PWMPER45 B8 2 2 0 .abs_section_b8\r
+ _PWMPER67 BA 2 2 0 .abs_section_ba\r
+ _PWMDTY01 BC 2 2 0 .abs_section_bc\r
+ _PWMDTY23 BE 2 2 0 .abs_section_be\r
+ _PWMDTY45 C0 2 2 0 .abs_section_c0\r
+ _PWMDTY67 C2 2 2 0 .abs_section_c2\r
+ _PWMSDN C4 1 1 1 .abs_section_c4\r
+ _SCI0BD C8 2 2 2 .abs_section_c8\r
+ _SCI0CR1 CA 1 1 1 .abs_section_ca\r
+ _SCI0CR2 CB 1 1 7 .abs_section_cb\r
+ _SCI0SR1 CC 1 1 2 .abs_section_cc\r
+ _SCI0SR2 CD 1 1 1 .abs_section_cd\r
+ _SCI0DRH CE 1 1 0 .abs_section_ce\r
+ _SCI0DRL CF 1 1 3 .abs_section_cf\r
+ _SCI1BD D0 2 2 0 .abs_section_d0\r
+ _SCI1CR1 D2 1 1 0 .abs_section_d2\r
+ _SCI1CR2 D3 1 1 0 .abs_section_d3\r
+ _SCI1SR1 D4 1 1 0 .abs_section_d4\r
+ _SCI1SR2 D5 1 1 0 .abs_section_d5\r
+ _SCI1DRH D6 1 1 0 .abs_section_d6\r
+ _SCI1DRL D7 1 1 0 .abs_section_d7\r
+ _SPI0CR1 D8 1 1 0 .abs_section_d8\r
+ _SPI0CR2 D9 1 1 0 .abs_section_d9\r
+ _SPI0BR DA 1 1 0 .abs_section_da\r
+ _SPI0SR DB 1 1 0 .abs_section_db\r
+ _SPI0DR DD 1 1 0 .abs_section_dd\r
+ _IBAD E0 1 1 0 .abs_section_e0\r
+ _IBFD E1 1 1 0 .abs_section_e1\r
+ _IBCR E2 1 1 0 .abs_section_e2\r
+ _IBSR E3 1 1 0 .abs_section_e3\r
+ _IBDR E4 1 1 0 .abs_section_e4\r
+ _DLCBCR1 E8 1 1 0 .abs_section_e8\r
+ _DLCBSVR E9 1 1 0 .abs_section_e9\r
+ _DLCBCR2 EA 1 1 0 .abs_section_ea\r
+ _DLCBDR EB 1 1 0 .abs_section_eb\r
+ _DLCBARD EC 1 1 0 .abs_section_ec\r
+ _DLCBRSR ED 1 1 0 .abs_section_ed\r
+ _DLCSCR EE 1 1 0 .abs_section_ee\r
+ _SPI1CR1 F0 1 1 0 .abs_section_f0\r
+ _SPI1CR2 F1 1 1 0 .abs_section_f1\r
+ _SPI1BR F2 1 1 0 .abs_section_f2\r
+ _SPI1SR F3 1 1 0 .abs_section_f3\r
+ _SPI1DR F5 1 1 0 .abs_section_f5\r
+ _SPI2CR1 F8 1 1 0 .abs_section_f8\r
+ _SPI2CR2 F9 1 1 0 .abs_section_f9\r
+ _SPI2BR FA 1 1 0 .abs_section_fa\r
+ _SPI2SR FB 1 1 0 .abs_section_fb\r
+ _SPI2DR FD 1 1 0 .abs_section_fd\r
+ _FCLKDIV 100 1 1 0 .abs_section_100\r
+ _FSEC 101 1 1 0 .abs_section_101\r
+ _FCNFG 103 1 1 0 .abs_section_103\r
+ _FPROT 104 1 1 0 .abs_section_104\r
+ _FSTAT 105 1 1 0 .abs_section_105\r
+ _FCMD 106 1 1 0 .abs_section_106\r
+ _ECLKDIV 110 1 1 0 .abs_section_110\r
+ _ECNFG 113 1 1 0 .abs_section_113\r
+ _EPROT 114 1 1 0 .abs_section_114\r
+ _ESTAT 115 1 1 0 .abs_section_115\r
+ _ECMD 116 1 1 0 .abs_section_116\r
+ _ATD1CTL23 122 2 2 0 .abs_section_122\r
+ _ATD1CTL45 124 2 2 0 .abs_section_124\r
+ _ATD1STAT0 126 1 1 0 .abs_section_126\r
+ _ATD1STAT1 12B 1 1 0 .abs_section_12b\r
+ _ATD1DIEN 12D 1 1 0 .abs_section_12d\r
+ _PORTAD1 12F 1 1 0 .abs_section_12f\r
+ _ATD1DR0 130 2 2 0 .abs_section_130\r
+ _ATD1DR1 132 2 2 0 .abs_section_132\r
+ _ATD1DR2 134 2 2 0 .abs_section_134\r
+ _ATD1DR3 136 2 2 0 .abs_section_136\r
+ _ATD1DR4 138 2 2 0 .abs_section_138\r
+ _ATD1DR5 13A 2 2 0 .abs_section_13a\r
+ _ATD1DR6 13C 2 2 0 .abs_section_13c\r
+ _ATD1DR7 13E 2 2 0 .abs_section_13e\r
+ _CAN0CTL0 140 1 1 0 .abs_section_140\r
+ _CAN0CTL1 141 1 1 0 .abs_section_141\r
+ _CAN0BTR0 142 1 1 0 .abs_section_142\r
+ _CAN0BTR1 143 1 1 0 .abs_section_143\r
+ _CAN0RFLG 144 1 1 0 .abs_section_144\r
+ _CAN0RIER 145 1 1 0 .abs_section_145\r
+ _CAN0TFLG 146 1 1 0 .abs_section_146\r
+ _CAN0TIER 147 1 1 0 .abs_section_147\r
+ _CAN0TARQ 148 1 1 0 .abs_section_148\r
+ _CAN0TAAK 149 1 1 0 .abs_section_149\r
+ _CAN0TBSEL 14A 1 1 0 .abs_section_14a\r
+ _CAN0IDAC 14B 1 1 0 .abs_section_14b\r
+ _CAN0RXERR 14E 1 1 0 .abs_section_14e\r
+ _CAN0TXERR 14F 1 1 0 .abs_section_14f\r
+ _CAN0IDAR0 150 1 1 0 .abs_section_150\r
+ _CAN0IDAR1 151 1 1 0 .abs_section_151\r
+ _CAN0IDAR2 152 1 1 0 .abs_section_152\r
+ _CAN0IDAR3 153 1 1 0 .abs_section_153\r
+ _CAN0IDMR0 154 1 1 0 .abs_section_154\r
+ _CAN0IDMR1 155 1 1 0 .abs_section_155\r
+ _CAN0IDMR2 156 1 1 0 .abs_section_156\r
+ _CAN0IDMR3 157 1 1 0 .abs_section_157\r
+ _CAN0IDAR4 158 1 1 0 .abs_section_158\r
+ _CAN0IDAR5 159 1 1 0 .abs_section_159\r
+ _CAN0IDAR6 15A 1 1 0 .abs_section_15a\r
+ _CAN0IDAR7 15B 1 1 0 .abs_section_15b\r
+ _CAN0IDMR4 15C 1 1 0 .abs_section_15c\r
+ _CAN0IDMR5 15D 1 1 0 .abs_section_15d\r
+ _CAN0IDMR6 15E 1 1 0 .abs_section_15e\r
+ _CAN0IDMR7 15F 1 1 0 .abs_section_15f\r
+ _CAN0RXIDR0 160 1 1 0 .abs_section_160\r
+ _CAN0RXIDR1 161 1 1 0 .abs_section_161\r
+ _CAN0RXIDR2 162 1 1 0 .abs_section_162\r
+ _CAN0RXIDR3 163 1 1 0 .abs_section_163\r
+ _CAN0RXDSR0 164 1 1 0 .abs_section_164\r
+ _CAN0RXDSR1 165 1 1 0 .abs_section_165\r
+ _CAN0RXDSR2 166 1 1 0 .abs_section_166\r
+ _CAN0RXDSR3 167 1 1 0 .abs_section_167\r
+ _CAN0RXDSR4 168 1 1 0 .abs_section_168\r
+ _CAN0RXDSR5 169 1 1 0 .abs_section_169\r
+ _CAN0RXDSR6 16A 1 1 0 .abs_section_16a\r
+ _CAN0RXDSR7 16B 1 1 0 .abs_section_16b\r
+ _CAN0RXDLR 16C 1 1 0 .abs_section_16c\r
+ _CAN0TXIDR0 170 1 1 0 .abs_section_170\r
+ _CAN0TXIDR1 171 1 1 0 .abs_section_171\r
+ _CAN0TXIDR2 172 1 1 0 .abs_section_172\r
+ _CAN0TXIDR3 173 1 1 0 .abs_section_173\r
+ _CAN0TXDSR0 174 1 1 0 .abs_section_174\r
+ _CAN0TXDSR1 175 1 1 0 .abs_section_175\r
+ _CAN0TXDSR2 176 1 1 0 .abs_section_176\r
+ _CAN0TXDSR3 177 1 1 0 .abs_section_177\r
+ _CAN0TXDSR4 178 1 1 0 .abs_section_178\r
+ _CAN0TXDSR5 179 1 1 0 .abs_section_179\r
+ _CAN0TXDSR6 17A 1 1 0 .abs_section_17a\r
+ _CAN0TXDSR7 17B 1 1 0 .abs_section_17b\r
+ _CAN0TXDLR 17C 1 1 0 .abs_section_17c\r
+ _CAN0TXTBPR 17F 1 1 0 .abs_section_17f\r
+ _CAN1CTL0 180 1 1 0 .abs_section_180\r
+ _CAN1CTL1 181 1 1 0 .abs_section_181\r
+ _CAN1BTR0 182 1 1 0 .abs_section_182\r
+ _CAN1BTR1 183 1 1 0 .abs_section_183\r
+ _CAN1RFLG 184 1 1 0 .abs_section_184\r
+ _CAN1RIER 185 1 1 0 .abs_section_185\r
+ _CAN1TFLG 186 1 1 0 .abs_section_186\r
+ _CAN1TIER 187 1 1 0 .abs_section_187\r
+ _CAN1TARQ 188 1 1 0 .abs_section_188\r
+ _CAN1TAAK 189 1 1 0 .abs_section_189\r
+ _CAN1TBSEL 18A 1 1 0 .abs_section_18a\r
+ _CAN1IDAC 18B 1 1 0 .abs_section_18b\r
+ _CAN1RXERR 18E 1 1 0 .abs_section_18e\r
+ _CAN1TXERR 18F 1 1 0 .abs_section_18f\r
+ _CAN1IDAR0 190 1 1 0 .abs_section_190\r
+ _CAN1IDAR1 191 1 1 0 .abs_section_191\r
+ _CAN1IDAR2 192 1 1 0 .abs_section_192\r
+ _CAN1IDAR3 193 1 1 0 .abs_section_193\r
+ _CAN1IDMR0 194 1 1 0 .abs_section_194\r
+ _CAN1IDMR1 195 1 1 0 .abs_section_195\r
+ _CAN1IDMR2 196 1 1 0 .abs_section_196\r
+ _CAN1IDMR3 197 1 1 0 .abs_section_197\r
+ _CAN1IDAR4 198 1 1 0 .abs_section_198\r
+ _CAN1IDAR5 199 1 1 0 .abs_section_199\r
+ _CAN1IDAR6 19A 1 1 0 .abs_section_19a\r
+ _CAN1IDAR7 19B 1 1 0 .abs_section_19b\r
+ _CAN1IDMR4 19C 1 1 0 .abs_section_19c\r
+ _CAN1IDMR5 19D 1 1 0 .abs_section_19d\r
+ _CAN1IDMR6 19E 1 1 0 .abs_section_19e\r
+ _CAN1IDMR7 19F 1 1 0 .abs_section_19f\r
+ _CAN1RXIDR0 1A0 1 1 0 .abs_section_1a0\r
+ _CAN1RXIDR1 1A1 1 1 0 .abs_section_1a1\r
+ _CAN1RXIDR2 1A2 1 1 0 .abs_section_1a2\r
+ _CAN1RXIDR3 1A3 1 1 0 .abs_section_1a3\r
+ _CAN1RXDSR0 1A4 1 1 0 .abs_section_1a4\r
+ _CAN1RXDSR1 1A5 1 1 0 .abs_section_1a5\r
+ _CAN1RXDSR2 1A6 1 1 0 .abs_section_1a6\r
+ _CAN1RXDSR3 1A7 1 1 0 .abs_section_1a7\r
+ _CAN1RXDSR4 1A8 1 1 0 .abs_section_1a8\r
+ _CAN1RXDSR5 1A9 1 1 0 .abs_section_1a9\r
+ _CAN1RXDSR6 1AA 1 1 0 .abs_section_1aa\r
+ _CAN1RXDSR7 1AB 1 1 0 .abs_section_1ab\r
+ _CAN1RXDLR 1AC 1 1 0 .abs_section_1ac\r
+ _CAN1TXIDR0 1B0 1 1 0 .abs_section_1b0\r
+ _CAN1TXIDR1 1B1 1 1 0 .abs_section_1b1\r
+ _CAN1TXIDR2 1B2 1 1 0 .abs_section_1b2\r
+ _CAN1TXIDR3 1B3 1 1 0 .abs_section_1b3\r
+ _CAN1TXDSR0 1B4 1 1 0 .abs_section_1b4\r
+ _CAN1TXDSR1 1B5 1 1 0 .abs_section_1b5\r
+ _CAN1TXDSR2 1B6 1 1 0 .abs_section_1b6\r
+ _CAN1TXDSR3 1B7 1 1 0 .abs_section_1b7\r
+ _CAN1TXDSR4 1B8 1 1 0 .abs_section_1b8\r
+ _CAN1TXDSR5 1B9 1 1 0 .abs_section_1b9\r
+ _CAN1TXDSR6 1BA 1 1 0 .abs_section_1ba\r
+ _CAN1TXDSR7 1BB 1 1 0 .abs_section_1bb\r
+ _CAN1TXDLR 1BC 1 1 0 .abs_section_1bc\r
+ _CAN1TXTBPR 1BF 1 1 0 .abs_section_1bf\r
+ _CAN2CTL0 1C0 1 1 0 .abs_section_1c0\r
+ _CAN2CTL1 1C1 1 1 0 .abs_section_1c1\r
+ _CAN2BTR0 1C2 1 1 0 .abs_section_1c2\r
+ _CAN2BTR1 1C3 1 1 0 .abs_section_1c3\r
+ _CAN2RFLG 1C4 1 1 0 .abs_section_1c4\r
+ _CAN2RIER 1C5 1 1 0 .abs_section_1c5\r
+ _CAN2TFLG 1C6 1 1 0 .abs_section_1c6\r
+ _CAN2TIER 1C7 1 1 0 .abs_section_1c7\r
+ _CAN2TARQ 1C8 1 1 0 .abs_section_1c8\r
+ _CAN2TAAK 1C9 1 1 0 .abs_section_1c9\r
+ _CAN2TBSEL 1CA 1 1 0 .abs_section_1ca\r
+ _CAN2IDAC 1CB 1 1 0 .abs_section_1cb\r
+ _CAN2RXERR 1CE 1 1 0 .abs_section_1ce\r
+ _CAN2TXERR 1CF 1 1 0 .abs_section_1cf\r
+ _CAN2IDAR0 1D0 1 1 0 .abs_section_1d0\r
+ _CAN2IDAR1 1D1 1 1 0 .abs_section_1d1\r
+ _CAN2IDAR2 1D2 1 1 0 .abs_section_1d2\r
+ _CAN2IDAR3 1D3 1 1 0 .abs_section_1d3\r
+ _CAN2IDMR0 1D4 1 1 0 .abs_section_1d4\r
+ _CAN2IDMR1 1D5 1 1 0 .abs_section_1d5\r
+ _CAN2IDMR2 1D6 1 1 0 .abs_section_1d6\r
+ _CAN2IDMR3 1D7 1 1 0 .abs_section_1d7\r
+ _CAN2IDAR4 1D8 1 1 0 .abs_section_1d8\r
+ _CAN2IDAR5 1D9 1 1 0 .abs_section_1d9\r
+ _CAN2IDAR6 1DA 1 1 0 .abs_section_1da\r
+ _CAN2IDAR7 1DB 1 1 0 .abs_section_1db\r
+ _CAN2IDMR4 1DC 1 1 0 .abs_section_1dc\r
+ _CAN2IDMR5 1DD 1 1 0 .abs_section_1dd\r
+ _CAN2IDMR6 1DE 1 1 0 .abs_section_1de\r
+ _CAN2IDMR7 1DF 1 1 0 .abs_section_1df\r
+ _CAN2RXIDR0 1E0 1 1 0 .abs_section_1e0\r
+ _CAN2RXIDR1 1E1 1 1 0 .abs_section_1e1\r
+ _CAN2RXIDR2 1E2 1 1 0 .abs_section_1e2\r
+ _CAN2RXIDR3 1E3 1 1 0 .abs_section_1e3\r
+ _CAN2RXDSR0 1E4 1 1 0 .abs_section_1e4\r
+ _CAN2RXDSR1 1E5 1 1 0 .abs_section_1e5\r
+ _CAN2RXDSR2 1E6 1 1 0 .abs_section_1e6\r
+ _CAN2RXDSR3 1E7 1 1 0 .abs_section_1e7\r
+ _CAN2RXDSR4 1E8 1 1 0 .abs_section_1e8\r
+ _CAN2RXDSR5 1E9 1 1 0 .abs_section_1e9\r
+ _CAN2RXDSR6 1EA 1 1 0 .abs_section_1ea\r
+ _CAN2RXDSR7 1EB 1 1 0 .abs_section_1eb\r
+ _CAN2RXDLR 1EC 1 1 0 .abs_section_1ec\r
+ _CAN2TXIDR0 1F0 1 1 0 .abs_section_1f0\r
+ _CAN2TXIDR1 1F1 1 1 0 .abs_section_1f1\r
+ _CAN2TXIDR2 1F2 1 1 0 .abs_section_1f2\r
+ _CAN2TXIDR3 1F3 1 1 0 .abs_section_1f3\r
+ _CAN2TXDSR0 1F4 1 1 0 .abs_section_1f4\r
+ _CAN2TXDSR1 1F5 1 1 0 .abs_section_1f5\r
+ _CAN2TXDSR2 1F6 1 1 0 .abs_section_1f6\r
+ _CAN2TXDSR3 1F7 1 1 0 .abs_section_1f7\r
+ _CAN2TXDSR4 1F8 1 1 0 .abs_section_1f8\r
+ _CAN2TXDSR5 1F9 1 1 0 .abs_section_1f9\r
+ _CAN2TXDSR6 1FA 1 1 0 .abs_section_1fa\r
+ _CAN2TXDSR7 1FB 1 1 0 .abs_section_1fb\r
+ _CAN2TXDLR 1FC 1 1 0 .abs_section_1fc\r
+ _CAN2TXTBPR 1FF 1 1 0 .abs_section_1ff\r
+ _CAN3CTL0 200 1 1 0 .abs_section_200\r
+ _CAN3CTL1 201 1 1 0 .abs_section_201\r
+ _CAN3BTR0 202 1 1 0 .abs_section_202\r
+ _CAN3BTR1 203 1 1 0 .abs_section_203\r
+ _CAN3RFLG 204 1 1 0 .abs_section_204\r
+ _CAN3RIER 205 1 1 0 .abs_section_205\r
+ _CAN3TFLG 206 1 1 0 .abs_section_206\r
+ _CAN3TIER 207 1 1 0 .abs_section_207\r
+ _CAN3TARQ 208 1 1 0 .abs_section_208\r
+ _CAN3TAAK 209 1 1 0 .abs_section_209\r
+ _CAN3TBSEL 20A 1 1 0 .abs_section_20a\r
+ _CAN3IDAC 20B 1 1 0 .abs_section_20b\r
+ _CAN3RXERR 20E 1 1 0 .abs_section_20e\r
+ _CAN3TXERR 20F 1 1 0 .abs_section_20f\r
+ _CAN3IDAR0 210 1 1 0 .abs_section_210\r
+ _CAN3IDAR1 211 1 1 0 .abs_section_211\r
+ _CAN3IDAR2 212 1 1 0 .abs_section_212\r
+ _CAN3IDAR3 213 1 1 0 .abs_section_213\r
+ _CAN3IDMR0 214 1 1 0 .abs_section_214\r
+ _CAN3IDMR1 215 1 1 0 .abs_section_215\r
+ _CAN3IDMR2 216 1 1 0 .abs_section_216\r
+ _CAN3IDMR3 217 1 1 0 .abs_section_217\r
+ _CAN3IDAR4 218 1 1 0 .abs_section_218\r
+ _CAN3IDAR5 219 1 1 0 .abs_section_219\r
+ _CAN3IDAR6 21A 1 1 0 .abs_section_21a\r
+ _CAN3IDAR7 21B 1 1 0 .abs_section_21b\r
+ _CAN3IDMR4 21C 1 1 0 .abs_section_21c\r
+ _CAN3IDMR5 21D 1 1 0 .abs_section_21d\r
+ _CAN3IDMR6 21E 1 1 0 .abs_section_21e\r
+ _CAN3IDMR7 21F 1 1 0 .abs_section_21f\r
+ _CAN3RXIDR0 220 1 1 0 .abs_section_220\r
+ _CAN3RXIDR1 221 1 1 0 .abs_section_221\r
+ _CAN3RXIDR2 222 1 1 0 .abs_section_222\r
+ _CAN3RXIDR3 223 1 1 0 .abs_section_223\r
+ _CAN3RXDSR0 224 1 1 0 .abs_section_224\r
+ _CAN3RXDSR1 225 1 1 0 .abs_section_225\r
+ _CAN3RXDSR2 226 1 1 0 .abs_section_226\r
+ _CAN3RXDSR3 227 1 1 0 .abs_section_227\r
+ _CAN3RXDSR4 228 1 1 0 .abs_section_228\r
+ _CAN3RXDSR5 229 1 1 0 .abs_section_229\r
+ _CAN3RXDSR6 22A 1 1 0 .abs_section_22a\r
+ _CAN3RXDSR7 22B 1 1 0 .abs_section_22b\r
+ _CAN3RXDLR 22C 1 1 0 .abs_section_22c\r
+ _CAN3TXIDR0 230 1 1 0 .abs_section_230\r
+ _CAN3TXIDR1 231 1 1 0 .abs_section_231\r
+ _CAN3TXIDR2 232 1 1 0 .abs_section_232\r
+ _CAN3TXIDR3 233 1 1 0 .abs_section_233\r
+ _CAN3TXDSR0 234 1 1 0 .abs_section_234\r
+ _CAN3TXDSR1 235 1 1 0 .abs_section_235\r
+ _CAN3TXDSR2 236 1 1 0 .abs_section_236\r
+ _CAN3TXDSR3 237 1 1 0 .abs_section_237\r
+ _CAN3TXDSR4 238 1 1 0 .abs_section_238\r
+ _CAN3TXDSR5 239 1 1 0 .abs_section_239\r
+ _CAN3TXDSR6 23A 1 1 0 .abs_section_23a\r
+ _CAN3TXDSR7 23B 1 1 0 .abs_section_23b\r
+ _CAN3TXDLR 23C 1 1 0 .abs_section_23c\r
+ _CAN3TXTBPR 23F 1 1 0 .abs_section_23f\r
+ _PTT 240 1 1 0 .abs_section_240\r
+ _PTIT 241 1 1 0 .abs_section_241\r
+ _DDRT 242 1 1 0 .abs_section_242\r
+ _RDRT 243 1 1 0 .abs_section_243\r
+ _PERT 244 1 1 0 .abs_section_244\r
+ _PPST 245 1 1 0 .abs_section_245\r
+ _PTS 248 1 1 1 .abs_section_248\r
+ _PTIS 249 1 1 0 .abs_section_249\r
+ _DDRS 24A 1 1 2 .abs_section_24a\r
+ _RDRS 24B 1 1 0 .abs_section_24b\r
+ _PERS 24C 1 1 0 .abs_section_24c\r
+ _PPSS 24D 1 1 0 .abs_section_24d\r
+ _WOMS 24E 1 1 0 .abs_section_24e\r
+ _PTM 250 1 1 0 .abs_section_250\r
+ _PTIM 251 1 1 0 .abs_section_251\r
+ _DDRM 252 1 1 0 .abs_section_252\r
+ _RDRM 253 1 1 0 .abs_section_253\r
+ _PERM 254 1 1 0 .abs_section_254\r
+ _PPSM 255 1 1 0 .abs_section_255\r
+ _WOMM 256 1 1 0 .abs_section_256\r
+ _MODRR 257 1 1 0 .abs_section_257\r
+ _PTP 258 1 1 0 .abs_section_258\r
+ _PTIP 259 1 1 0 .abs_section_259\r
+ _DDRP 25A 1 1 0 .abs_section_25a\r
+ _RDRP 25B 1 1 0 .abs_section_25b\r
+ _PERP 25C 1 1 0 .abs_section_25c\r
+ _PPSP 25D 1 1 0 .abs_section_25d\r
+ _PIEP 25E 1 1 0 .abs_section_25e\r
+ _PIFP 25F 1 1 0 .abs_section_25f\r
+ _PTH 260 1 1 0 .abs_section_260\r
+ _PTIH 261 1 1 0 .abs_section_261\r
+ _DDRH 262 1 1 0 .abs_section_262\r
+ _RDRH 263 1 1 0 .abs_section_263\r
+ _PERH 264 1 1 0 .abs_section_264\r
+ _PPSH 265 1 1 0 .abs_section_265\r
+ _PIEH 266 1 1 0 .abs_section_266\r
+ _PIFH 267 1 1 0 .abs_section_267\r
+ _PTJ 268 1 1 0 .abs_section_268\r
+ _PTIJ 269 1 1 0 .abs_section_269\r
+ _DDRJ 26A 1 1 0 .abs_section_26a\r
+ _RDRJ 26B 1 1 0 .abs_section_26b\r
+ _PERJ 26C 1 1 0 .abs_section_26c\r
+ _PPSJ 26D 1 1 0 .abs_section_26d\r
+ _PIEJ 26E 1 1 0 .abs_section_26e\r
+ _PIFJ 26F 1 1 0 .abs_section_26f\r
+ _CAN4CTL0 280 1 1 0 .abs_section_280\r
+ _CAN4CTL1 281 1 1 0 .abs_section_281\r
+ _CAN4BTR0 282 1 1 0 .abs_section_282\r
+ _CAN4BTR1 283 1 1 0 .abs_section_283\r
+ _CAN4RFLG 284 1 1 0 .abs_section_284\r
+ _CAN4RIER 285 1 1 0 .abs_section_285\r
+ _CAN4TFLG 286 1 1 0 .abs_section_286\r
+ _CAN4TIER 287 1 1 0 .abs_section_287\r
+ _CAN4TARQ 288 1 1 0 .abs_section_288\r
+ _CAN4TAAK 289 1 1 0 .abs_section_289\r
+ _CAN4TBSEL 28A 1 1 0 .abs_section_28a\r
+ _CAN4IDAC 28B 1 1 0 .abs_section_28b\r
+ _CAN4RXERR 28E 1 1 0 .abs_section_28e\r
+ _CAN4TXERR 28F 1 1 0 .abs_section_28f\r
+ _CAN4IDAR0 290 1 1 0 .abs_section_290\r
+ _CAN4IDAR1 291 1 1 0 .abs_section_291\r
+ _CAN4IDAR2 292 1 1 0 .abs_section_292\r
+ _CAN4IDAR3 293 1 1 0 .abs_section_293\r
+ _CAN4IDMR0 294 1 1 0 .abs_section_294\r
+ _CAN4IDMR1 295 1 1 0 .abs_section_295\r
+ _CAN4IDMR2 296 1 1 0 .abs_section_296\r
+ _CAN4IDMR3 297 1 1 0 .abs_section_297\r
+ _CAN4IDAR4 298 1 1 0 .abs_section_298\r
+ _CAN4IDAR5 299 1 1 0 .abs_section_299\r
+ _CAN4IDAR6 29A 1 1 0 .abs_section_29a\r
+ _CAN4IDAR7 29B 1 1 0 .abs_section_29b\r
+ _CAN4IDMR4 29C 1 1 0 .abs_section_29c\r
+ _CAN4IDMR5 29D 1 1 0 .abs_section_29d\r
+ _CAN4IDMR6 29E 1 1 0 .abs_section_29e\r
+ _CAN4IDMR7 29F 1 1 0 .abs_section_29f\r
+ _CAN4RXIDR0 2A0 1 1 0 .abs_section_2a0\r
+ _CAN4RXIDR1 2A1 1 1 0 .abs_section_2a1\r
+ _CAN4RXIDR2 2A2 1 1 0 .abs_section_2a2\r
+ _CAN4RXIDR3 2A3 1 1 0 .abs_section_2a3\r
+ _CAN4RXDSR0 2A4 1 1 0 .abs_section_2a4\r
+ _CAN4RXDSR1 2A5 1 1 0 .abs_section_2a5\r
+ _CAN4RXDSR2 2A6 1 1 0 .abs_section_2a6\r
+ _CAN4RXDSR3 2A7 1 1 0 .abs_section_2a7\r
+ _CAN4RXDSR4 2A8 1 1 0 .abs_section_2a8\r
+ _CAN4RXDSR5 2A9 1 1 0 .abs_section_2a9\r
+ _CAN4RXDSR6 2AA 1 1 0 .abs_section_2aa\r
+ _CAN4RXDSR7 2AB 1 1 0 .abs_section_2ab\r
+ _CAN4RXDLR 2AC 1 1 0 .abs_section_2ac\r
+ _CAN4TXIDR0 2B0 1 1 0 .abs_section_2b0\r
+ _CAN4TXIDR1 2B1 1 1 0 .abs_section_2b1\r
+ _CAN4TXIDR2 2B2 1 1 0 .abs_section_2b2\r
+ _CAN4TXIDR3 2B3 1 1 0 .abs_section_2b3\r
+ _CAN4TXDSR0 2B4 1 1 0 .abs_section_2b4\r
+ _CAN4TXDSR1 2B5 1 1 0 .abs_section_2b5\r
+ _CAN4TXDSR2 2B6 1 1 0 .abs_section_2b6\r
+ _CAN4TXDSR3 2B7 1 1 0 .abs_section_2b7\r
+ _CAN4TXDSR4 2B8 1 1 0 .abs_section_2b8\r
+ _CAN4TXDSR5 2B9 1 1 0 .abs_section_2b9\r
+ _CAN4TXDSR6 2BA 1 1 0 .abs_section_2ba\r
+ _CAN4TXDSR7 2BB 1 1 0 .abs_section_2bb\r
+ _CAN4TXDLR 2BC 1 1 0 .abs_section_2bc\r
+ _CAN4TXTBPR 2BF 1 1 0 .abs_section_2bf\r
+ uxCriticalNesting 1000 1 1 101 .data \r
+ xLocalError 1001 1 1 2 .bss \r
+ xRxedChars 1002 2 2 3 .bss \r
+ xCharsForTx 1004 2 2 3 .bss \r
+ pxCurrentTCB 1006 2 2 28 .bss \r
+ uxTasksDeleted 1008 1 1 3 .bss \r
+ uxCurrentNumberOfTasks 1009 1 1 5 .bss \r
+ xTickCount 100A 2 2 14 .bss \r
+ uxTopUsedPriority 100C 1 1 2 .bss \r
+ uxTopReadyPriority 100D 1 1 15 .bss \r
+ xSchedulerRunning 100E 1 1 3 .bss \r
+ uxSchedulerSuspended 100F 1 1 6 .bss \r
+ uxMissedTicks 1010 1 1 4 .bss \r
+ uxTaskNumber.1 1011 1 1 2 .bss \r
+ pxReadyTasksLists 1012 3C 60 11 .bss \r
+ xDelayedTaskList1 104E F 15 2 .bss \r
+ xDelayedTaskList2 105D F 15 2 .bss \r
+ pxDelayedTaskList 106C 2 2 8 .bss \r
+ pxOverflowDelayedTaskList 106E 2 2 6 .bss \r
+ xPendingReadyList 1070 F 15 4 .bss \r
+ xTasksWaitingTermination 107F F 15 5 .bss \r
+ xSuspendedTaskList 108E F 15 2 .bss \r
+ xHeapHasBeenInitialised.1 109D 1 1 2 .bss \r
+ xHeap 109E 2804 10244 2 .bss \r
+ xStart 38A2 4 4 6 .bss \r
+ xEnd 38A6 4 4 4 .bss \r
+ uxFlashTaskNumber 38AA 1 1 2 .bss \r
+ usCheckVariable 38AB 2 2 4 .bss \r
+ xSuspendedQueueSendError 38AD 1 1 2 .bss \r
+ xSuspendedQueueReceiveError 38AE 1 1 3 .bss \r
+ ulValueToSend.6 38AF 4 4 5 .bss \r
+ ulExpectedValue.7 38B3 4 4 6 .bss \r
+ usLastTaskCheck.9 38B7 2 2 2 .bss \r
+ xContinousIncrementHandle 38B9 2 2 5 .bss \r
+ xLimitedIncrementHandle 38BB 2 2 2 .bss \r
+ ulCounter 38BD 4 4 10 .bss \r
+ ulReceivedValue.8 38C1 4 4 3 .bss \r
+ xPollingConsumerCount 38C5 1 1 3 .bss \r
+ xPollingProducerCount 38C6 1 1 3 .bss \r
+ xPolledQueue.1 38C7 2 2 3 .bss \r
+ xPort 38C9 2 2 2 .bss \r
+ uxBaseLED 38CB 1 1 5 .bss \r
+ uxRxLoops 38CC 1 1 3 .bss \r
+ xTaskCheck 38CD 1 1 3 .bss \r
+ sBlockingConsumerCount 38CE 6 6 5 .bss \r
+ sBlockingProducerCount 38D4 6 6 5 .bss \r
+ sLastBlockingConsumerCount.7 38DA 6 6 2 .bss \r
+ sLastBlockingProducerCount.8 38E0 6 6 2 .bss \r
+ usCreationCount 38E6 2 2 4 .bss \r
+ uxTasksRunningAtStart 38E8 1 1 4 .bss \r
+ usLastCreationCount.6 38E9 2 2 2 .bss \r
+ uxTasksRunningNow.7 38EB 1 1 1 .bss \r
+ xSuspendedTestQueue 38EC 2 2 3 .common \r
+ xCreatedTask1 38EE 2 2 2 .common \r
+ xCreatedTask2 38F0 2 2 2 .common \r
+ CmpHighVal 38F2 2 2 2 TickTimer_DATA\r
+ Byte1_Table 38F4 8 8 1 Byte1_DATA \r
+ COM0_PrescHigh.1 38FC 8 8 1 COM0_DATA \r
+ SerFlag 3904 2 2 1 COM0_DATA \r
+ PrescHigh 3906 2 2 2 COM0_DATA \r
+ NumMode 3908 1 1 2 COM0_DATA \r
+ _EntryPoint C000 2E 46 1 .init \r
+ PE_low_level_init C02E 4E 78 2 .init \r
+ STRING.Check.1 C09A 6 6 1 .rodata1 \r
+ STRING.IDLE.2 C0A0 5 5 1 .rodata1 \r
+ STRING.LEDx.1 C0A5 5 5 1 .rodata1 \r
+ STRING.CNT_INC.1 C0AA 8 8 1 .rodata1 \r
+ STRING.LIM_INC.2 C0B2 8 8 1 .rodata1 \r
+ STRING.C_CTRL.3 C0BA 7 7 1 .rodata1 \r
+ STRING.SUSP_TX.4 C0C1 8 8 1 .rodata1 \r
+ STRING.SUSP_RX.5 C0C9 8 8 1 .rodata1 \r
+ STRING.QConsNB.2 C0D1 8 8 1 .rodata1 \r
+ STRING.QProdNB.3 C0D9 8 8 1 .rodata1 \r
+ STRING.COMTx.1 C0E1 6 6 1 .rodata1 \r
+ STRING.COMRx.2 C0E7 6 6 1 .rodata1 \r
+ STRING.IntMath.1 C0ED 8 8 1 .rodata1 \r
+ STRING.QConsB1.1 C0F5 8 8 1 .rodata1 \r
+ STRING.QProdB2.2 C0FD 8 8 1 .rodata1 \r
+ STRING.QProdB3.3 C105 8 8 1 .rodata1 \r
+ STRING.QConsB4.4 C10D 8 8 1 .rodata1 \r
+ STRING.QProdB5.5 C115 8 8 1 .rodata1 \r
+ STRING.QConsB6.6 C11D 8 8 1 .rodata1 \r
+ STRING.CREATOR.1 C125 8 8 1 .rodata1 \r
+ STRING.SUICIDE1.2 C12D 9 9 1 .rodata1 \r
+ STRING.SUICIDE2.3 C136 9 9 1 .rodata1 \r
+ STRING.SUICIDE1.4 C13F 9 9 1 .rodata1 \r
+ STRING.SUICIDE2.5 C148 9 9 1 .rodata1 \r
+ _Startup C151 12 18 1 NON_BANKED \r
+ _LCMP C163 19 25 2 NON_BANKED \r
+ _LCMP_P C17C 15 21 3 NON_BANKED \r
+ _LNEG C191 D 13 2 NON_BANKED \r
+ _LINC C19E 5 5 4 NON_BANKED \r
+ _LMUL C1A3 27 39 1 NON_BANKED \r
+ _lDivMod C1CA E3 227 3 NON_BANKED \r
+ _LDIVU C2AD E 14 1 NON_BANKED \r
+ _NEG_P C2BB F 15 4 NON_BANKED \r
+ _LDIVS C2CA 35 53 2 NON_BANKED \r
+ Cpu_Interrupt C2FF 1 1 60 NON_BANKED \r
+ vCOM0_ISR C300 59 89 1 NON_BANKED \r
+ xBankedStartScheduler C359 13 19 1 NON_BANKED \r
+ vPortYield C36C 1D 29 1 NON_BANKED \r
+ vPortTickInterrupt C389 25 37 1 NON_BANKED \r
+ _BDMSTS FF01 1 1 0 .abs_section_ff01\r
+ _BDMCCR FF06 1 1 0 .abs_section_ff06\r
+ _BDMINR FF07 1 1 0 .abs_section_ff07\r
+ _vect FF80 80 128 0 .abs_section_ff80\r
+ Init 308000 29 41 2 .text \r
+ memcpy 308029 26 38 8 .text \r
+ memset 30804F 1E 30 2 .text \r
+ strncpy 30806D 2D 45 2 .text \r
+ main 30809A 9 9 0 .text \r
+ vMain 3080A3 52 82 1 .text \r
+ vErrorChecks 3080F5 33 51 3 .text \r
+ prvCheckOtherTasksAreStillRunning 308128 49 73 2 .text \r
+ vApplicationIdleHook 308171 70 112 2 .text \r
+ vParTestSetLED 3081E1 22 34 4 .text \r
+ vParTestToggleLED 308203 14 20 10 .text \r
+ xSerialPortInitMinimal 308217 24 36 2 .text \r
+ xSerialGetChar 30823B 17 23 2 .text \r
+ xSerialPutChar 318000 1D 29 2 ROM_PAGE31_524\r
+ xTaskCreate 31801D D9 217 48 ROM_PAGE31_524\r
+ vTaskDelete 3180F6 4A 74 4 ROM_PAGE31_524\r
+ vTaskDelayUntil 318140 78 120 6 ROM_PAGE31_524\r
+ vTaskDelay 3181B8 4A 74 16 ROM_PAGE31_524\r
+ uxTaskPriorityGet 318202 26 38 2 ROM_PAGE31_524\r
+ vTaskPrioritySet 328000 6B 107 4 ROM_PAGE32_525\r
+ vTaskSuspend 32806B 47 71 6 ROM_PAGE32_525\r
+ vTaskResume 3280B2 5B 91 6 ROM_PAGE32_525\r
+ vTaskStartScheduler 32810D 35 53 2 ROM_PAGE32_525\r
+ vTaskSuspendAll 328142 13 19 26 ROM_PAGE32_525\r
+ xTaskResumeAll 328155 A5 165 30 ROM_PAGE32_525\r
+ xTaskGetTickCount 3281FA 17 23 6 ROM_PAGE32_525\r
+ uxTaskGetNumberOfTasks 328211 17 23 4 ROM_PAGE32_525\r
+ vTaskIncrementTick 338000 84 132 4 ROM_PAGE33_526\r
+ vTaskSwitchContext 338084 5B 91 4 ROM_PAGE33_526\r
+ vTaskPlaceOnEventList 3380DF 44 68 4 ROM_PAGE33_526\r
+ xTaskRemoveFromEventList 338123 6F 111 8 ROM_PAGE33_526\r
+ prvIdleTask 338192 12 18 3 ROM_PAGE33_526\r
+ prvInitialiseTCBVariables 3381A4 4F 79 2 ROM_PAGE33_526\r
+ prvInitialiseTaskLists 3381F3 41 65 2 ROM_PAGE33_526\r
+ prvCheckTasksWaitingTermination 348000 55 85 2 ROM_PAGE34_527\r
+ prvAllocateTCBAndStack 348055 37 55 2 ROM_PAGE34_527\r
+ prvDeleteTCB 34808C 11 17 2 ROM_PAGE34_527\r
+ xQueueCreate 34809D 7C 124 14 ROM_PAGE34_527\r
+ xQueueSend 348119 D4 212 9 ROM_PAGE34_527\r
+ xQueueSendFromISR 3481ED 56 86 2 ROM_PAGE34_527\r
+ xQueueReceive 358000 CE 206 9 ROM_PAGE35_528\r
+ xQueueReceiveFromISR 3580CE 60 96 2 ROM_PAGE35_528\r
+ uxQueueMessagesWaiting 35812E 1B 27 2 ROM_PAGE35_528\r
+ prvUnlockQueue 358149 71 113 8 ROM_PAGE35_528\r
+ prvIsQueueEmpty 3581BA 21 33 2 ROM_PAGE35_528\r
+ prvIsQueueFull 3581DB 24 36 2 ROM_PAGE35_528\r
+ vListInitialise 3581FF 20 32 6 ROM_PAGE35_528\r
+ vListInitialiseItem 35821F 7 7 6 ROM_PAGE35_528\r
+ vListInsertEnd 358226 27 39 16 ROM_PAGE35_528\r
+ vListInsert 368000 5A 90 8 ROM_PAGE36_529\r
+ vListRemove 36805A 23 35 32 ROM_PAGE36_529\r
+ pvPortMalloc 36807D B6 182 14 ROM_PAGE36_529\r
+ vPortFree 368133 34 52 10 ROM_PAGE36_529\r
+ PE_Timer_LngHi1 368167 43 67 2 ROM_PAGE36_529\r
+ vStartLEDFlashTasks 3681AA 2A 42 2 ROM_PAGE36_529\r
+ vLEDFlashTask 3681D4 57 87 3 ROM_PAGE36_529\r
+ vStartDynamicPriorityTasks 378000 9B 155 2 ROM_PAGE37_530\r
+ vLimitedIncrementTask 37809B 22 34 3 ROM_PAGE37_530\r
+ vContinuousIncrementTask 3780BD 33 51 3 ROM_PAGE37_530\r
+ vCounterControlTask 3780F0 A0 160 5 ROM_PAGE37_530\r
+ vQueueSendWhenSuspendedTask 378190 38 56 3 ROM_PAGE37_530\r
+ vQueueReceiveWhenSuspendedTask 3781C8 53 83 3 ROM_PAGE37_530\r
+ xAreDynamicPriorityTasksStillRunning 37821B 27 39 2 ROM_PAGE37_530\r
+ vStartPolledQueueTasks 388000 49 73 2 ROM_PAGE38_531\r
+ vPolledQueueProducer 388049 4F 79 3 ROM_PAGE38_531\r
+ vPolledQueueConsumer 388098 5C 92 3 ROM_PAGE38_531\r
+ xArePollingQueuesStillRunning 3880F4 1D 29 2 ROM_PAGE38_531\r
+ vAltStartComTestTasks 388111 4D 77 2 ROM_PAGE38_531\r
+ vComTxTask 38815E 51 81 3 ROM_PAGE38_531\r
+ vComRxTask 3881AF 6A 106 3 ROM_PAGE38_531\r
+ xAreComTestTasksStillRunning 388219 15 21 2 ROM_PAGE38_531\r
+ pxPortInitialiseStack 398000 31 49 2 ROM_PAGE39_532\r
+ prvSetupTimerInterrupt 398031 C 12 2 ROM_PAGE39_532\r
+ xPortStartScheduler 39803D 4 4 2 ROM_PAGE39_532\r
+ vStartIntegerMathTasks 398041 33 51 2 ROM_PAGE39_532\r
+ vCompeteingIntMathTask 398074 87 135 3 ROM_PAGE39_532\r
+ xAreIntegerMathsTaskStillRunning 3980FB 25 37 2 ROM_PAGE39_532\r
+ vStartBlockingQueueTasks 3A8000 143 323 7 ROM_PAGE3A_533\r
+ vBlockingQueueProducer 3A8143 3A 58 9 ROM_PAGE3A_533\r
+ vBlockingQueueConsumer 3A817D 45 69 9 ROM_PAGE3A_533\r
+ xAreBlockingQueuesStillRunning 3A81C2 49 73 2 ROM_PAGE3A_533\r
+ vCreateSuicidalTasks 3A820B 33 51 2 ROM_PAGE3A_533\r
+ vSuicidalTask 3B8000 52 82 12 ROM_PAGE3B_534\r
+ vCreateTasks 3B8052 94 148 4 ROM_PAGE3B_534\r
+ xIsCreateTaskStillRunning 3B80E6 36 54 2 ROM_PAGE3B_534\r
+ SetCV 3B811C F 15 4 TickTimer_CODE\r
+ SetPV 3B812B C 12 2 TickTimer_CODE\r
+ HWEnDi 3B8137 8 8 4 TickTimer_CODE\r
+ TickTimer_Enable 3B813F 6 6 2 TickTimer_CODE\r
+ TickTimer_SetFreqHz 3B8145 51 81 2 TickTimer_CODE\r
+ TickTimer_Init 3B8196 15 21 2 TickTimer_CODE\r
+ Byte1_GetMsk 3B81AB D 13 4 Byte1_CODE \r
+ Byte1_PutBit 3B81B8 1F 31 2 Byte1_CODE \r
+ Byte1_NegBit 3B81D7 11 17 2 Byte1_CODE \r
+ HWEnDi 3B81E8 A 10 2 COM0_CODE \r
+ COM0_SetBaudRateMode 3B81F2 19 25 2 COM0_CODE \r
+ COM0_Init 3B820B 20 32 2 COM0_CODE \r
+\r
+*********************************************************************************************\r
+UNUSED-OBJECTS SECTION\r
+---------------------------------------------------------------------------------------------\r
+NOT USED PROCEDURES\r
+STRING.C.o (ansibi.lib):\r
+ strerror memchr memcmp memcpy2 _memcpy_8bitCount memmove \r
+ _memset_clear_8bitCount strlen strset strcat strncat strcpy strcmp strncmp \r
+ strchr strrchr strspn strcspn strpbrk strstr strtok strcoll strxfrm \r
+rtshc12.c.o (ansibi.lib):\r
+ _BSHL _BSHRS _BSHRU _BDIVMODU _BDIVMODS _ISHL _ISHRU _ISHRS _LSHL _LSHRU \r
+ _LSHRS _LADD _LSUB _LAND _LOR _LXOR _LCMP_PP _LABS _LCOM _LDEC _LMODU _LMODS \r
+ _ILSEXT _LTEST _COPY _CASE_DIRECT _CASE_DIRECT_BYTE _CASE_CHECKED \r
+ _CASE_CHECKED_BYTE _CASE_SEARCH _CASE_SEARCH_BYTE _CASE_SEARCH_8 \r
+ _CASE_SEARCH_8_BYTE _FCALL _FPCMP \r
+serial.c.o:\r
+ vSerialClose \r
+tasks.c.o:\r
+ vTaskEndScheduler \r
+queue.c.o:\r
+ vQueueDelete \r
+TickTimer.C.o:\r
+ TickTimer_Interrupt TickTimer_SetPeriodTicks16 TickTimer_SetPeriodTicks32 \r
+ TickTimer_SetPeriodUS TickTimer_SetPeriodMS \r
+PE_Timer.C.o:\r
+ PE_Timer_LngMul PE_Timer_LngHi2 PE_Timer_LngHi3 PE_Timer_LngHi4 \r
+port.c.o:\r
+ vPortEndScheduler \r
+NOT USED VARIABLES\r
+STRING.C.o (ansibi.lib):\r
+ STRING..1 next.2 \r
+rtshc12.c.o (ansibi.lib):\r
+ _PowOfTwo_8 _PowOfTwo_16 _PowOfTwo_32 \r
+Cpu.C.o:\r
+ CpuMode CCR_reg \r
+heap_2.c.o:\r
+ heapSTRUCT_SIZE \r
+death.c.o:\r
+ uxMaxNumberOfExtraTasksRunning \r
+\r
+*********************************************************************************************\r
+COPYDOWN SECTION\r
+---------------------------------------------------------------------------------------------\r
+------- ROM-ADDRESS: 0xC3AE ---- SIZE 4 ---\r
+Filling bytes inserted\r
+ 00011000\r
+------- ROM-ADDRESS: 0xC3B2 ---- RAM-ADDRESS: 0x1000 ---- SIZE 1 ---\r
+Name of initialized Object : uxCriticalNesting\r
+ FF\r
+------- ROM-ADDRESS: 0xC3B3 ---- SIZE 4 ---\r
+Filling bytes inserted\r
+ 001038F4\r
+------- ROM-ADDRESS: 0xC3B7 ---- RAM-ADDRESS: 0x38F4 ---- SIZE 8 ---\r
+Name of initialized Object : Byte1_Table\r
+ 0102040810 204080\r
+------- ROM-ADDRESS: 0xC3BF ---- SIZE 1 ---\r
+Filling bytes inserted\r
+ 00\r
+------- ROM-ADDRESS: 0xC3C0 ---- RAM-ADDRESS: 0x38FD ---- SIZE 7 ---\r
+Name of initialized Object : COM0_PrescHigh.1:1\r
+ 29005100A3 0146\r
+------- ROM-ADDRESS: 0xC3C7 ---- SIZE 2 ---\r
+Filling bytes inserted\r
+ 0000\r
+\r
+*********************************************************************************************\r
+OBJECT-DEPENDENCIES SECTION\r
+---------------------------------------------------------------------------------------------\r
+_EntryPoint USES _INITRM _INITEE _MISC _CLKSEL _PLLCTL _SYNR \r
+ _REFDV _CRGFLG _Startup \r
+PE_low_level_init USES _TSCR1 _TCTL2 _TCTL1 _TIE _TTOV _TSCR2 _TIOS \r
+ _PWMCTL _PWMSDN _ICSYS _MCCTL TickTimer_Init _PORTAB \r
+ _DDRAB _DDRS _PTS COM0_Init _INTCR \r
+_Startup USES _startupData Init \r
+_LDIVU USES _lDivMod \r
+_LDIVS USES _NEG_P _lDivMod \r
+vCOM0_ISR USES _SCI0SR1 _SCI0DRL xRxedChars xQueueSendFromISR \r
+ _SCI0CR2 xCharsForTx xQueueReceiveFromISR \r
+xBankedStartScheduler USES prvSetupTimerInterrupt pxCurrentTCB \r
+ uxCriticalNesting \r
+vPortYield USES uxCriticalNesting pxCurrentTCB \r
+ vTaskSwitchContext \r
+vPortTickInterrupt USES uxCriticalNesting pxCurrentTCB \r
+ vTaskIncrementTick vTaskSwitchContext _TFLG1 \r
+_vect USES Cpu_Interrupt vCOM0_ISR vPortTickInterrupt \r
+ vPortYield _EntryPoint \r
+Init USES _startupData \r
+main USES PE_low_level_init vMain \r
+vMain USES vStartLEDFlashTasks vStartPolledQueueTasks \r
+ vStartDynamicPriorityTasks vAltStartComTestTasks vStartBlockingQueueTasks \r
+ vStartIntegerMathTasks vCreateSuicidalTasks vErrorChecks \r
+ STRING.Check.1 xTaskCreate vTaskStartScheduler \r
+vErrorChecks USES xTaskGetTickCount vTaskDelayUntil \r
+ prvCheckOtherTasksAreStillRunning _LCMP vParTestToggleLED \r
+prvCheckOtherTasksAreStillRunning USES xArePollingQueuesStillRunning \r
+ xAreDynamicPriorityTasksStillRunning xAreComTestTasksStillRunning \r
+ xAreIntegerMathsTaskStillRunning xAreBlockingQueuesStillRunning \r
+ xIsCreateTaskStillRunning xLocalError \r
+vApplicationIdleHook USES _LNEG _LDIVS _LCMP_P uxCriticalNesting \r
+ xLocalError \r
+vParTestSetLED USES uxCriticalNesting Byte1_PutBit \r
+vParTestToggleLED USES uxCriticalNesting Byte1_NegBit \r
+xSerialPortInitMinimal USES xQueueCreate xRxedChars xCharsForTx \r
+ COM0_SetBaudRateMode \r
+xSerialGetChar USES xRxedChars xQueueReceive \r
+xSerialPutChar USES xCharsForTx xQueueSend _SCI0CR2 \r
+xTaskCreate USES prvAllocateTCBAndStack \r
+ prvInitialiseTCBVariables pxPortInitialiseStack uxCriticalNesting \r
+ uxCurrentNumberOfTasks pxCurrentTCB prvInitialiseTaskLists \r
+ xSchedulerRunning uxTopUsedPriority uxTaskNumber.1 \r
+ uxTopReadyPriority pxReadyTasksLists vListInsertEnd \r
+vTaskDelete USES uxCriticalNesting pxCurrentTCB vListRemove \r
+ xTasksWaitingTermination vListInsertEnd uxTasksDeleted \r
+vTaskDelayUntil USES vTaskSuspendAll xTickCount pxCurrentTCB \r
+ vListRemove pxOverflowDelayedTaskList pxDelayedTaskList \r
+ vListInsert xTaskResumeAll \r
+vTaskDelay USES vTaskSuspendAll xTickCount pxCurrentTCB \r
+ vListRemove pxOverflowDelayedTaskList pxDelayedTaskList \r
+ vListInsert xTaskResumeAll \r
+uxTaskPriorityGet USES uxCriticalNesting pxCurrentTCB \r
+vTaskPrioritySet USES uxCriticalNesting pxCurrentTCB \r
+ pxReadyTasksLists vListRemove uxTopReadyPriority vListInsertEnd \r
+vTaskSuspend USES uxCriticalNesting pxCurrentTCB vListRemove \r
+ xSuspendedTaskList vListInsertEnd \r
+vTaskResume USES uxCriticalNesting pxCurrentTCB vListRemove \r
+ uxTopReadyPriority pxReadyTasksLists vListInsertEnd \r
+vTaskStartScheduler USES pxCurrentTCB prvIdleTask STRING.IDLE.2 \r
+ xTaskCreate xSchedulerRunning xTickCount \r
+ xPortStartScheduler \r
+vTaskSuspendAll USES uxCriticalNesting uxSchedulerSuspended \r
+xTaskResumeAll USES uxCriticalNesting uxSchedulerSuspended \r
+ uxCurrentNumberOfTasks vListRemove uxTopReadyPriority \r
+ pxReadyTasksLists vListInsertEnd pxCurrentTCB xPendingReadyList \r
+ uxMissedTicks vTaskIncrementTick \r
+xTaskGetTickCount USES uxCriticalNesting xTickCount \r
+uxTaskGetNumberOfTasks USES uxCriticalNesting uxCurrentNumberOfTasks \r
+vTaskIncrementTick USES uxSchedulerSuspended xTickCount \r
+ pxDelayedTaskList pxOverflowDelayedTaskList vListRemove \r
+ uxTopReadyPriority pxReadyTasksLists vListInsertEnd uxMissedTicks \r
+vTaskSwitchContext USES uxSchedulerSuspended uxTopReadyPriority \r
+ pxCurrentTCB pxReadyTasksLists \r
+vTaskPlaceOnEventList USES pxCurrentTCB vListInsert xTickCount vListRemove \r
+ pxOverflowDelayedTaskList pxDelayedTaskList \r
+xTaskRemoveFromEventList USES vListRemove uxSchedulerSuspended \r
+ uxTopReadyPriority pxReadyTasksLists xPendingReadyList \r
+ vListInsertEnd pxCurrentTCB \r
+prvIdleTask USES prvCheckTasksWaitingTermination \r
+ pxReadyTasksLists vApplicationIdleHook \r
+prvInitialiseTCBVariables USES strncpy vListInitialiseItem \r
+prvInitialiseTaskLists USES pxReadyTasksLists xDelayedTaskList1 \r
+ xDelayedTaskList2 xPendingReadyList xTasksWaitingTermination \r
+ xSuspendedTaskList pxDelayedTaskList pxOverflowDelayedTaskList \r
+ vListInitialise \r
+prvCheckTasksWaitingTermination USES uxTasksDeleted vTaskSuspendAll \r
+ xTasksWaitingTermination xTaskResumeAll uxCriticalNesting vListRemove \r
+ uxCurrentNumberOfTasks prvDeleteTCB \r
+prvAllocateTCBAndStack USES pvPortMalloc vPortFree memset \r
+prvDeleteTCB USES vPortFree \r
+xQueueCreate USES pvPortMalloc vListInitialise vPortFree \r
+xQueueSend USES vTaskSuspendAll uxCriticalNesting xQueueSend \r
+ prvIsQueueFull vTaskPlaceOnEventList prvUnlockQueue \r
+ xTaskResumeAll memcpy \r
+xQueueSendFromISR USES memcpy xTaskRemoveFromEventList \r
+xQueueReceive USES vTaskSuspendAll uxCriticalNesting xQueueReceive \r
+ prvIsQueueEmpty vTaskPlaceOnEventList prvUnlockQueue \r
+ xTaskResumeAll memcpy \r
+xQueueReceiveFromISR USES memcpy xTaskRemoveFromEventList \r
+uxQueueMessagesWaiting USES uxCriticalNesting \r
+prvUnlockQueue USES uxCriticalNesting xTaskRemoveFromEventList \r
+prvIsQueueEmpty USES uxCriticalNesting \r
+prvIsQueueFull USES uxCriticalNesting \r
+vListInitialise USES vListInitialiseItem \r
+pvPortMalloc USES vTaskSuspendAll xHeapHasBeenInitialised.1 xHeap \r
+ xStart xEnd xTaskResumeAll \r
+vPortFree USES vTaskSuspendAll xStart xTaskResumeAll \r
+PE_Timer_LngHi1 USES _LCMP \r
+vStartLEDFlashTasks USES vLEDFlashTask STRING.LEDx.1 xTaskCreate \r
+vLEDFlashTask USES uxCriticalNesting uxFlashTaskNumber \r
+ xTaskGetTickCount vTaskDelayUntil vParTestToggleLED \r
+vStartDynamicPriorityTasks USES xQueueCreate xSuspendedTestQueue \r
+ vContinuousIncrementTask STRING.CNT_INC.1 ulCounter \r
+ xContinousIncrementHandle xTaskCreate vLimitedIncrementTask \r
+ STRING.LIM_INC.2 xLimitedIncrementHandle vCounterControlTask \r
+ STRING.C_CTRL.3 vQueueSendWhenSuspendedTask STRING.SUSP_TX.4 \r
+ vQueueReceiveWhenSuspendedTask STRING.SUSP_RX.5 \r
+vLimitedIncrementTask USES _LINC _LCMP_P vTaskSuspend \r
+vContinuousIncrementTask USES uxTaskPriorityGet vTaskPrioritySet _LINC \r
+vCounterControlTask USES vCounterControlTask xContinousIncrementHandle \r
+ vTaskSuspend ulCounter vTaskResume vTaskDelay \r
+ vTaskSuspendAll xTaskResumeAll xLimitedIncrementHandle \r
+ uxCriticalNesting usCheckVariable \r
+vQueueSendWhenSuspendedTask USES vTaskSuspendAll xSuspendedTestQueue \r
+ ulValueToSend.6 xQueueSend xSuspendedQueueSendError \r
+ xTaskResumeAll vTaskDelay _LINC \r
+vQueueReceiveWhenSuspendedTask USES vTaskSuspendAll xSuspendedTestQueue \r
+ ulReceivedValue.8 xQueueReceive xTaskResumeAll \r
+ xSuspendedQueueReceiveError ulExpectedValue.7 _LINC \r
+xAreDynamicPriorityTasksStillRunning USES usCheckVariable usLastTaskCheck.9 \r
+ xSuspendedQueueSendError xSuspendedQueueReceiveError \r
+vStartPolledQueueTasks USES xQueueCreate xPolledQueue.1 \r
+ vPolledQueueConsumer STRING.QConsNB.2 xTaskCreate \r
+ vPolledQueueProducer STRING.QProdNB.3 \r
+vPolledQueueProducer USES xQueueSend uxCriticalNesting \r
+ xPollingProducerCount vTaskDelay \r
+vPolledQueueConsumer USES xQueueReceive uxCriticalNesting \r
+ xPollingConsumerCount uxQueueMessagesWaiting vTaskDelay \r
+xArePollingQueuesStillRunning USES xPollingConsumerCount xPollingProducerCount \r
+vAltStartComTestTasks USES uxBaseLED xSerialPortInitMinimal vComTxTask \r
+ STRING.COMTx.1 xTaskCreate vComRxTask STRING.COMRx.2 \r
+vComTxTask USES xPort xSerialPutChar uxBaseLED \r
+ vParTestToggleLED vParTestSetLED xTaskGetTickCount vTaskDelay \r
+vComRxTask USES uxBaseLED vParTestToggleLED vParTestSetLED \r
+ uxRxLoops xPort xSerialGetChar \r
+xAreComTestTasksStillRunning USES uxRxLoops \r
+prvSetupTimerInterrupt USES TickTimer_SetFreqHz TickTimer_Enable \r
+xPortStartScheduler USES xBankedStartScheduler \r
+vStartIntegerMathTasks USES vCompeteingIntMathTask STRING.IntMath.1 \r
+ xTaskCheck xTaskCreate \r
+vCompeteingIntMathTask USES _LNEG _LDIVS _LCMP_P uxCriticalNesting \r
+xAreIntegerMathsTaskStillRunning USES xTaskCheck \r
+vStartBlockingQueueTasks USES vStartBlockingQueueTasks xQueueCreate \r
+ sBlockingConsumerCount sBlockingProducerCount vBlockingQueueConsumer \r
+ STRING.QConsB1.1 xTaskCreate vBlockingQueueProducer \r
+ STRING.QProdB2.2 STRING.QProdB3.3 STRING.QConsB4.4 \r
+ STRING.QProdB5.5 STRING.QConsB6.6 pvPortMalloc \r
+vBlockingQueueProducer USES xQueueSend \r
+vBlockingQueueConsumer USES xQueueReceive \r
+xAreBlockingQueuesStillRunning USES sBlockingConsumerCount \r
+ sLastBlockingConsumerCount.7 sBlockingProducerCount \r
+ sLastBlockingProducerCount.8 \r
+vCreateSuicidalTasks USES pvPortMalloc vCreateTasks STRING.CREATOR.1 \r
+ xTaskCreate uxTaskGetNumberOfTasks uxTasksRunningAtStart \r
+vSuicidalTask USES _LMUL vTaskDelay vTaskDelete \r
+vCreateTasks USES vPortFree vTaskDelay vSuicidalTask \r
+ STRING.SUICIDE1.2 xCreatedTask1 xTaskCreate STRING.SUICIDE2.3 \r
+ STRING.SUICIDE1.4 xCreatedTask2 STRING.SUICIDE2.5 \r
+ usCreationCount vCreateTasks \r
+xIsCreateTaskStillRunning USES usLastCreationCount.6 usCreationCount \r
+ uxTaskGetNumberOfTasks uxTasksRunningNow.7 uxTasksRunningAtStart \r
+SetCV USES _TC0 _TC7 \r
+SetPV USES _TSCR2 \r
+HWEnDi USES _TFLG1 _TIE \r
+TickTimer_Enable USES HWEnDi \r
+TickTimer_SetFreqHz USES _LDIVU PE_Timer_LngHi1 CmpHighVal SetCV \r
+TickTimer_Init USES CmpHighVal SetCV SetPV HWEnDi \r
+Byte1_GetMsk USES Byte1_Table \r
+Byte1_PutBit USES Byte1_GetMsk _PORTAB \r
+Byte1_NegBit USES Byte1_GetMsk _PORTAB \r
+HWEnDi USES _SCI0CR2 \r
+COM0_SetBaudRateMode USES NumMode COM0_PrescHigh.1 PrescHigh _SCI0BD \r
+COM0_Init USES PrescHigh SerFlag NumMode _SCI0CR1 _SCI0SR2 \r
+ _SCI0SR1 _SCI0CR2 _SCI0BD HWEnDi \r
+\r
+*********************************************************************************************\r
+DEPENDENCY TREE\r
+*********************************************************************************************\r
+ main and _Startup Group\r
+ | \r
+ +- main \r
+ | | \r
+ | +- PE_low_level_init \r
+ | | | \r
+ | | +- TickTimer_Init \r
+ | | | | \r
+ | | | +- SetCV \r
+ | | | | \r
+ | | | +- SetPV \r
+ | | | | \r
+ | | | +- HWEnDi \r
+ | | | \r
+ | | +- COM0_Init \r
+ | | | \r
+ | | +- HWEnDi \r
+ | | \r
+ | +- vMain \r
+ | | \r
+ | +- vStartLEDFlashTasks \r
+ | | | \r
+ | | +- vLEDFlashTask \r
+ | | | | \r
+ | | | +- xTaskGetTickCount \r
+ | | | | \r
+ | | | +- vTaskDelayUntil \r
+ | | | | | \r
+ | | | | +- vTaskSuspendAll \r
+ | | | | | \r
+ | | | | +- vListRemove \r
+ | | | | | \r
+ | | | | +- vListInsert \r
+ | | | | | \r
+ | | | | +- xTaskResumeAll \r
+ | | | | | \r
+ | | | | +- vListRemove (see above)\r
+ | | | | | \r
+ | | | | +- vListInsertEnd \r
+ | | | | | \r
+ | | | | +- vTaskIncrementTick \r
+ | | | | | \r
+ | | | | +- vListRemove (see above)\r
+ | | | | | \r
+ | | | | +- vListInsertEnd (see above)\r
+ | | | | \r
+ | | | +- vParTestToggleLED \r
+ | | | | \r
+ | | | +- Byte1_NegBit \r
+ | | | | \r
+ | | | +- Byte1_GetMsk \r
+ | | | \r
+ | | +- xTaskCreate \r
+ | | | \r
+ | | +- prvAllocateTCBAndStack\r
+ | | | | \r
+ | | | +- pvPortMalloc \r
+ | | | | | \r
+ | | | | +- vTaskSuspendAll (see above)\r
+ | | | | | \r
+ | | | | +- xTaskResumeAll (see above)\r
+ | | | | \r
+ | | | +- vPortFree \r
+ | | | | | \r
+ | | | | +- vTaskSuspendAll (see above)\r
+ | | | | | \r
+ | | | | +- xTaskResumeAll (see above)\r
+ | | | | \r
+ | | | +- memset \r
+ | | | \r
+ | | +- prvInitialiseTCBVariables\r
+ | | | | \r
+ | | | +- strncpy \r
+ | | | | \r
+ | | | +- vListInitialiseItem \r
+ | | | \r
+ | | +- pxPortInitialiseStack\r
+ | | | \r
+ | | +- prvInitialiseTaskLists\r
+ | | | | \r
+ | | | +- vListInitialise \r
+ | | | | \r
+ | | | +- vListInitialiseItem (see above)\r
+ | | | \r
+ | | +- vListInsertEnd (see above)\r
+ | | \r
+ | +- vStartPolledQueueTasks\r
+ | | | \r
+ | | +- xQueueCreate \r
+ | | | | \r
+ | | | +- pvPortMalloc (see above)\r
+ | | | | \r
+ | | | +- vListInitialise (see above)\r
+ | | | | \r
+ | | | +- vPortFree (see above)\r
+ | | | \r
+ | | +- vPolledQueueConsumer\r
+ | | | | \r
+ | | | +- xQueueReceive \r
+ | | | | | \r
+ | | | | +- vTaskSuspendAll (see above)\r
+ | | | | | \r
+ | | | | +- prvIsQueueEmpty \r
+ | | | | | \r
+ | | | | +- vTaskPlaceOnEventList\r
+ | | | | | | \r
+ | | | | | +- vListInsert (see above)\r
+ | | | | | | \r
+ | | | | | +- vListRemove (see above)\r
+ | | | | | \r
+ | | | | +- prvUnlockQueue \r
+ | | | | | | \r
+ | | | | | +- xTaskRemoveFromEventList\r
+ | | | | | | \r
+ | | | | | +- vListRemove (see above)\r
+ | | | | | | \r
+ | | | | | +- vListInsertEnd (see above)\r
+ | | | | | \r
+ | | | | +- xTaskResumeAll (see above)\r
+ | | | | | \r
+ | | | | +- memcpy \r
+ | | | | \r
+ | | | +- uxQueueMessagesWaiting\r
+ | | | | \r
+ | | | +- vTaskDelay \r
+ | | | | \r
+ | | | +- vTaskSuspendAll (see above)\r
+ | | | | \r
+ | | | +- vListRemove (see above)\r
+ | | | | \r
+ | | | +- vListInsert (see above)\r
+ | | | | \r
+ | | | +- xTaskResumeAll (see above)\r
+ | | | \r
+ | | +- xTaskCreate (see above)\r
+ | | | \r
+ | | +- vPolledQueueProducer\r
+ | | | \r
+ | | +- xQueueSend \r
+ | | | | \r
+ | | | +- vTaskSuspendAll (see above)\r
+ | | | | \r
+ | | | +- prvIsQueueFull \r
+ | | | | \r
+ | | | +- vTaskPlaceOnEventList (see above)\r
+ | | | | \r
+ | | | +- prvUnlockQueue (see above)\r
+ | | | | \r
+ | | | +- xTaskResumeAll (see above)\r
+ | | | | \r
+ | | | +- memcpy (see above)\r
+ | | | \r
+ | | +- vTaskDelay (see above)\r
+ | | \r
+ | +- vStartDynamicPriorityTasks\r
+ | | | \r
+ | | +- xQueueCreate (see above)\r
+ | | | \r
+ | | +- vContinuousIncrementTask\r
+ | | | | \r
+ | | | +- uxTaskPriorityGet \r
+ | | | | \r
+ | | | +- vTaskPrioritySet \r
+ | | | | | \r
+ | | | | +- vListRemove (see above)\r
+ | | | | | \r
+ | | | | +- vListInsertEnd (see above)\r
+ | | | | \r
+ | | | +- _LINC \r
+ | | | \r
+ | | +- xTaskCreate (see above)\r
+ | | | \r
+ | | +- vLimitedIncrementTask\r
+ | | | | \r
+ | | | +- _LINC (see above)\r
+ | | | | \r
+ | | | +- _LCMP_P \r
+ | | | | \r
+ | | | +- vTaskSuspend \r
+ | | | | \r
+ | | | +- vListRemove (see above)\r
+ | | | | \r
+ | | | +- vListInsertEnd (see above)\r
+ | | | \r
+ | | +- vCounterControlTask \r
+ | | | | \r
+ | | | +- vTaskSuspend (see above)\r
+ | | | | \r
+ | | | +- vTaskResume \r
+ | | | | | \r
+ | | | | +- vListRemove (see above)\r
+ | | | | | \r
+ | | | | +- vListInsertEnd (see above)\r
+ | | | | \r
+ | | | +- vTaskDelay (see above)\r
+ | | | | \r
+ | | | +- vTaskSuspendAll (see above)\r
+ | | | | \r
+ | | | +- xTaskResumeAll (see above)\r
+ | | | \r
+ | | +- vQueueSendWhenSuspendedTask\r
+ | | | | \r
+ | | | +- vTaskSuspendAll (see above)\r
+ | | | | \r
+ | | | +- xQueueSend (see above)\r
+ | | | | \r
+ | | | +- xTaskResumeAll (see above)\r
+ | | | | \r
+ | | | +- vTaskDelay (see above)\r
+ | | | | \r
+ | | | +- _LINC (see above)\r
+ | | | \r
+ | | +- vQueueReceiveWhenSuspendedTask\r
+ | | | \r
+ | | +- vTaskSuspendAll (see above)\r
+ | | | \r
+ | | +- xQueueReceive (see above)\r
+ | | | \r
+ | | +- xTaskResumeAll (see above)\r
+ | | | \r
+ | | +- _LINC (see above)\r
+ | | \r
+ | +- vAltStartComTestTasks\r
+ | | | \r
+ | | +- xSerialPortInitMinimal\r
+ | | | | \r
+ | | | +- xQueueCreate (see above)\r
+ | | | | \r
+ | | | +- COM0_SetBaudRateMode\r
+ | | | \r
+ | | +- vComTxTask \r
+ | | | | \r
+ | | | +- xSerialPutChar \r
+ | | | | | \r
+ | | | | +- xQueueSend (see above)\r
+ | | | | \r
+ | | | +- vParTestToggleLED (see above)\r
+ | | | | \r
+ | | | +- vParTestSetLED \r
+ | | | | | \r
+ | | | | +- Byte1_PutBit \r
+ | | | | | \r
+ | | | | +- Byte1_GetMsk (see above)\r
+ | | | | \r
+ | | | +- xTaskGetTickCount (see above)\r
+ | | | | \r
+ | | | +- vTaskDelay (see above)\r
+ | | | \r
+ | | +- xTaskCreate (see above)\r
+ | | | \r
+ | | +- vComRxTask \r
+ | | | \r
+ | | +- vParTestToggleLED (see above)\r
+ | | | \r
+ | | +- vParTestSetLED (see above)\r
+ | | | \r
+ | | +- xSerialGetChar \r
+ | | | \r
+ | | +- xQueueReceive (see above)\r
+ | | \r
+ | +- vStartBlockingQueueTasks\r
+ | | | \r
+ | | +- xQueueCreate (see above)\r
+ | | | \r
+ | | +- vBlockingQueueConsumer\r
+ | | | | \r
+ | | | +- xQueueReceive (see above)\r
+ | | | \r
+ | | +- xTaskCreate (see above)\r
+ | | | \r
+ | | +- vBlockingQueueProducer\r
+ | | | | \r
+ | | | +- xQueueSend (see above)\r
+ | | | \r
+ | | +- pvPortMalloc (see above)\r
+ | | \r
+ | +- vStartIntegerMathTasks\r
+ | | | \r
+ | | +- vCompeteingIntMathTask\r
+ | | | | \r
+ | | | +- _LNEG \r
+ | | | | \r
+ | | | +- _LDIVS \r
+ | | | | | \r
+ | | | | +- _NEG_P \r
+ | | | | | \r
+ | | | | +- _lDivMod \r
+ | | | | \r
+ | | | +- _LCMP_P (see above)\r
+ | | | \r
+ | | +- xTaskCreate (see above)\r
+ | | \r
+ | +- vCreateSuicidalTasks\r
+ | | | \r
+ | | +- pvPortMalloc (see above)\r
+ | | | \r
+ | | +- vCreateTasks \r
+ | | | | \r
+ | | | +- vPortFree (see above)\r
+ | | | | \r
+ | | | +- vTaskDelay (see above)\r
+ | | | | \r
+ | | | +- vSuicidalTask \r
+ | | | | | \r
+ | | | | +- _LMUL \r
+ | | | | | \r
+ | | | | +- vTaskDelay (see above)\r
+ | | | | | \r
+ | | | | +- vTaskDelete \r
+ | | | | | \r
+ | | | | +- vListRemove (see above)\r
+ | | | | | \r
+ | | | | +- vListInsertEnd (see above)\r
+ | | | | \r
+ | | | +- xTaskCreate (see above)\r
+ | | | \r
+ | | +- xTaskCreate (see above)\r
+ | | | \r
+ | | +- uxTaskGetNumberOfTasks\r
+ | | \r
+ | +- vErrorChecks \r
+ | | | \r
+ | | +- xTaskGetTickCount (see above)\r
+ | | | \r
+ | | +- vTaskDelayUntil (see above)\r
+ | | | \r
+ | | +- prvCheckOtherTasksAreStillRunning\r
+ | | | | \r
+ | | | +- xArePollingQueuesStillRunning\r
+ | | | | \r
+ | | | +- xAreDynamicPriorityTasksStillRunning\r
+ | | | | \r
+ | | | +- xAreComTestTasksStillRunning\r
+ | | | | \r
+ | | | +- xAreIntegerMathsTaskStillRunning\r
+ | | | | \r
+ | | | +- xAreBlockingQueuesStillRunning\r
+ | | | | \r
+ | | | +- xIsCreateTaskStillRunning\r
+ | | | | \r
+ | | | +- uxTaskGetNumberOfTasks (see above)\r
+ | | | \r
+ | | +- _LCMP \r
+ | | | \r
+ | | +- vParTestToggleLED (see above)\r
+ | | \r
+ | +- xTaskCreate (see above)\r
+ | | \r
+ | +- vTaskStartScheduler \r
+ | | \r
+ | +- prvIdleTask \r
+ | | | \r
+ | | +- prvCheckTasksWaitingTermination\r
+ | | | | \r
+ | | | +- vTaskSuspendAll (see above)\r
+ | | | | \r
+ | | | +- xTaskResumeAll (see above)\r
+ | | | | \r
+ | | | +- vListRemove (see above)\r
+ | | | | \r
+ | | | +- prvDeleteTCB \r
+ | | | | \r
+ | | | +- vPortFree (see above)\r
+ | | | \r
+ | | +- vApplicationIdleHook\r
+ | | | \r
+ | | +- _LNEG (see above)\r
+ | | | \r
+ | | +- _LDIVS (see above)\r
+ | | | \r
+ | | +- _LCMP_P (see above)\r
+ | | \r
+ | +- xTaskCreate (see above)\r
+ | | \r
+ | +- xPortStartScheduler \r
+ | | \r
+ | +- xBankedStartScheduler\r
+ | | \r
+ | +- prvSetupTimerInterrupt\r
+ | | \r
+ | +- TickTimer_SetFreqHz \r
+ | | | \r
+ | | +- _LDIVU \r
+ | | | | \r
+ | | | +- _lDivMod (see above)\r
+ | | | \r
+ | | +- PE_Timer_LngHi1 \r
+ | | | | \r
+ | | | +- _LCMP (see above)\r
+ | | | \r
+ | | +- SetCV (see above)\r
+ | | \r
+ | +- TickTimer_Enable \r
+ | | \r
+ | +- HWEnDi (see above)\r
+ | \r
+ +- _EntryPoint \r
+ | \r
+ +- _Startup \r
+ | \r
+ +- Init \r
+ \r
+ _vect \r
+ | \r
+ +- Cpu_Interrupt \r
+ | \r
+ +- vCOM0_ISR \r
+ | | \r
+ | +- xQueueSendFromISR \r
+ | | | \r
+ | | +- memcpy (see above)\r
+ | | | \r
+ | | +- xTaskRemoveFromEventList (see above)\r
+ | | \r
+ | +- xQueueReceiveFromISR\r
+ | | \r
+ | +- memcpy (see above)\r
+ | | \r
+ | +- xTaskRemoveFromEventList (see above)\r
+ | \r
+ +- vPortTickInterrupt \r
+ | | \r
+ | +- vTaskIncrementTick (see above)\r
+ | | \r
+ | +- vTaskSwitchContext \r
+ | \r
+ +- vPortYield \r
+ | | \r
+ | +- vTaskSwitchContext (see above)\r
+ | \r
+ +- _EntryPoint (see above)\r
+ \r
+*********************************************************************************************\r
+STATISTIC SECTION\r
+---------------------------------------------------------------------------------------------\r
+\r
+ExeFile:\r
+--------\r
+Number of blocks to be downloaded: 19\r
+Total size of all blocks to be downloaded: 7635\r
+\r
--- /dev/null
+// HCS12 Core erasing + unsecuring command file:\r
+// These commands mass erase the chip then program the security byte to 0xFE (unsecured state).\r
+\r
+// Evaluate the clock divider to set in ECLKDIV/FCLKDIV registers:\r
+\r
+// An average programming clock of 175 kHz is chosen.\r
+\r
+// If the oscillator frequency is less than 10 MHz, the value to store\r
+// in ECLKDIV/FCLKDIV is equal to " oscillator frequency (kHz) / 175 ".\r
+\r
+// If the oscillator frequency is higher than 10 MHz, the value to store\r
+// in ECLKDIV/FCLKDIV is equal to " oscillator frequency (kHz) / 1400 + 0x40 (to set PRDIV8 flag)".\r
+\r
+// Datasheet proposed values:\r
+//\r
+// oscillator frequency ECLKDIV/FCLKDIV value (hexadecimal)\r
+//\r
+// 16 MHz $49\r
+// 8 MHz $27\r
+// 4 MHz $13\r
+// 2 MHz $9\r
+// 1 MHz $4\r
+\r
+define CLKDIV 0x49\r
+\r
+FLASH MEMUNMAP // do not interact with regular flash programming monitor\r
+\r
+//mass erase flash\r
+wb 0x100 CLKDIV // set FCLKDIV clock divider\r
+wb 0x103 0 // FCFNG select block 0\r
+wb 0x102 0x10 // set the WRALL bit in FTSTMOD to affect all blocks\r
+wb 0x104 0xFF // FPROT all protection disabled\r
+wb 0x105 0x30 // clear PVIOL and ACCERR in FSTAT register\r
+ww 0x108 0xD000 // write to FADDR address register\r
+ww 0x10A 0x0000 // write to FDATA data register\r
+wb 0x106 0x41 // write MASS ERASE command in FCMD register\r
+wb 0x105 0x80 // clear CBEIF in FSTAT register to execute the command\r
+wait 20 // wait for command to complete\r
+\r
+//mass erase eeprom\r
+wb 0x110 CLKDIV // set ECLKDV clock divider\r
+wb 0x114 0xFF // EPROT all protection disabled\r
+wb 0x115 0x30 // clear PVIOL and ACCERR in ESTAT register\r
+ww 0x118 0x0400 // write to EADDR eeprom address register\r
+ww 0x11A 0x0000 // write to EDATA eeprom data register\r
+wb 0x116 0x41 // write MASS ERASE command in ECMD register\r
+wb 0x115 0x80 // clear CBEIF in ESTAT register to execute the command\r
+wait 20 // wait for command to complete\r
+\r
+reset\r
+\r
+//reprogram Security byte to Unsecure state\r
+wb 0x100 CLKDIV // set FCLKDIV clock divider\r
+wb 0x103 0 // FCFNG select block 0\r
+wb 0x104 0xFF // FPROT all protection disabled\r
+wb 0x105 0x30 // clear PVIOL and ACCERR in FSTAT register\r
+ww 0xFF0E 0xFFFE // write security byte to "Unsecured" state\r
+wb 0x106 0x20 // write MEMORY PROGRAM command in FCMD register\r
+wb 0x105 0x80 // clear CBEIF in FSTAT register to execute the command\r
+wait 20 // wait for command to complete\r
+\r
+reset\r
+\r
+FLASH MEMMAP // restore regular flash programming monitor\r
+undef CLKDIV // undefine variable\r
+\r
--- /dev/null
+// After load the commands written below will be executed\r
+// Show main function at startup\r
+FindProc main\r
--- /dev/null
+// Before load the commands written below will be executed\r
--- /dev/null
+// After reset the commands written below will be executed\r
--- /dev/null
+// At startup the commands written below will be executed\r
--- /dev/null
+// After programming the flash, the commands written below will be executed\r
--- /dev/null
+// Before programming the flash, the commands written below will be executed\r
--- /dev/null
+// After load the commands written below will be executed\r
+// Show main function at startup\r
+FindProc main\r
--- /dev/null
+// Before load the commands written below will be executed\r
--- /dev/null
+// After reset the commands written below will be executed\r
--- /dev/null
+// At startup the commands written below will be executed\r
--- /dev/null
+// At startup the commands written below will be executed\r
--- /dev/null
+\r
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+\r
+/*\r
+ *\r
+ * vMain() is effectively the demo application entry point. It is called by\r
+ * the main() function generated by the Processor Expert application. \r
+ *\r
+ * vMain() creates all the demo application tasks, then starts the scheduler.\r
+ * The WEB documentation provides more details of the demo application tasks.\r
+ *\r
+ * Main.c also creates a task called "Check". This only executes every three \r
+ * seconds but has the highest priority so is guaranteed to get processor time. \r
+ * Its main function is to check that all the other tasks are still operational.\r
+ * Each task (other than the "flash" tasks) maintains a unique count that is \r
+ * incremented each time the task successfully completes its function. Should \r
+ * any error occur within such a task the count is permanently halted. The \r
+ * check task inspects the count of each task to ensure it has changed since\r
+ * the last time the check task executed. If all the count variables have \r
+ * changed all the tasks are still executing error free, and the check task\r
+ * toggles the onboard LED. Should any task contain an error at any time \r
+ * the LED toggle rate will change from 3 seconds to 500ms.\r
+ *\r
+ * This file also includes the functionality implemented within the \r
+ * standard demo application file integer.c. This is done to demonstrate the\r
+ * use of an idle hook. See the documentation within integer.c for the \r
+ * rationale of the integer task functionality.\r
+ * */\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+\r
+/* Demo application includes. */\r
+#include "flash.h"\r
+#include "PollQ.h"\r
+#include "dynamic.h"\r
+#include "partest.h"\r
+#include "comtest2.h"\r
+#include "BlockQ.h"\r
+#include "integer.h"\r
+#include "death.h"\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ Definitions.\r
+-----------------------------------------------------------*/\r
+\r
+/* Priorities assigned to demo application tasks. */\r
+#define mainFLASH_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainDEATH_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+\r
+/* LED that is toggled by the check task. The check task periodically checks\r
+that all the other tasks are operating without error. If no errors are found\r
+the LED is toggled with mainCHECK_PERIOD frequency. If an error is found \r
+then the toggle rate increases to mainERROR_CHECK_PERIOD. */\r
+#define mainCHECK_TASK_LED ( 7 )\r
+#define mainCHECK_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS )\r
+#define mainERROR_CHECK_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS )\r
+\r
+/* The constants used in the idle task calculation. */\r
+#define intgCONST1 ( ( portLONG ) 123 )\r
+#define intgCONST2 ( ( portLONG ) 234567 )\r
+#define intgCONST3 ( ( portLONG ) -3 )\r
+#define intgCONST4 ( ( portLONG ) 7 )\r
+#define intgEXPECTED_ANSWER ( ( ( intgCONST1 + intgCONST2 ) * intgCONST3 ) / intgCONST4 )\r
+\r
+\r
+/* Baud rate used by the serial port tasks (ComTest tasks).\r
+IMPORTANT: The function COM0_SetBaudRateValue() which is generated by the\r
+Processor Expert is used to set the baud rate. As configured in the FreeRTOS\r
+download this value must be one of the following:\r
+\r
+0 to configure for 38400 baud.\r
+1 to configure for 19200 baud.\r
+2 to configure for 9600 baud.\r
+3 to configure for 4800 baud. */\r
+#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 2 )\r
+\r
+/* LED used by the serial port tasks. This is toggled on each character Tx,\r
+and mainCOM_TEST_LED + 1 is toggles on each character Rx. */\r
+#define mainCOM_TEST_LED ( 3 )\r
+\r
+/*-----------------------------------------------------------\r
+ Local functions prototypes.\r
+-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The 'Check' task function. See the explanation at the top of the file.\r
+ */\r
+static void vErrorChecks( void* pvParameters );\r
+\r
+/*\r
+ * The idle task hook - in which the integer task is implemented. See the\r
+ * explanation at the top of the file.\r
+ */\r
+void vApplicationIdleHook( void );\r
+\r
+/*\r
+ * Checks the unique counts of other tasks to ensure they are still operational.\r
+ */\r
+static portLONG prvCheckOtherTasksAreStillRunning( void );\r
+\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ Local variables.\r
+-----------------------------------------------------------*/\r
+\r
+/* A few tasks are defined within this file. This flag is used to indicate\r
+their status. If an error is detected in one of the locally defined tasks then\r
+this flag is set to pdTRUE. */\r
+portBASE_TYPE xLocalError = pdFALSE;\r
+\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* \r
+ * This is called from the main() function generated by the Processor Expert.\r
+ */\r
+void vMain( void )\r
+{\r
+ /* Start some of the standard demo tasks. */\r
+ vStartLEDFlashTasks( mainFLASH_PRIORITY );\r
+ vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
+ vStartDynamicPriorityTasks();\r
+ vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED );\r
+ vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
+ vStartIntegerMathTasks( tskIDLE_PRIORITY );\r
+ \r
+ /* Start the locally defined tasks. There is also a task implemented as\r
+ the idle hook. */\r
+ xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
+ \r
+ /* Must be the last demo created. */\r
+ vCreateSuicidalTasks( mainDEATH_PRIORITY );\r
+\r
+ /* All the tasks have been created - start the scheduler. */\r
+ vTaskStartScheduler();\r
+ \r
+ /* Should not reach here! */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vErrorChecks( void *pvParameters )\r
+{\r
+portTickType xDelayPeriod = mainCHECK_PERIOD;\r
+portTickType xLastWakeTime;\r
+\r
+ /* Initialise xLastWakeTime to ensure the first call to vTaskDelayUntil()\r
+ functions correctly. */\r
+ xLastWakeTime = xTaskGetTickCount();\r
+\r
+ for( ;; )\r
+ {\r
+ /* Delay until it is time to execute again. The delay period is \r
+ shorter following an error. */\r
+ vTaskDelayUntil( &xLastWakeTime, xDelayPeriod );\r
+\r
+ /* Check all the demo application tasks are executing without \r
+ error. If an error is found the delay period is shortened - this\r
+ has the effect of increasing the flash rate of the 'check' task\r
+ LED. */\r
+ if( prvCheckOtherTasksAreStillRunning() == pdFAIL )\r
+ {\r
+ /* An error has been detected in one of the tasks - flash faster. */\r
+ xDelayPeriod = mainERROR_CHECK_PERIOD;\r
+ }\r
+\r
+ /* Toggle the LED each cycle round. */\r
+ vParTestToggleLED( mainCHECK_TASK_LED );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portLONG prvCheckOtherTasksAreStillRunning( void )\r
+{\r
+portBASE_TYPE xAllTasksPassed = pdPASS;\r
+\r
+ if( xArePollingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ xAllTasksPassed = pdFAIL;\r
+ }\r
+\r
+ if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )\r
+ {\r
+ xAllTasksPassed = pdFAIL;\r
+ }\r
+\r
+ if( xAreComTestTasksStillRunning() != pdTRUE )\r
+ {\r
+ xAllTasksPassed = pdFALSE;\r
+ }\r
+\r
+ if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ xAllTasksPassed = pdFALSE;\r
+ }\r
+ \r
+ if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ xAllTasksPassed = pdFALSE;\r
+ } \r
+\r
+ if( xIsCreateTaskStillRunning() != pdTRUE )\r
+ {\r
+ xAllTasksPassed = pdFALSE;\r
+ }\r
+\r
+ /* Also check the status flag for the tasks defined within this function. */\r
+ if( xLocalError != pdFALSE )\r
+ {\r
+ xAllTasksPassed = pdFAIL;\r
+ }\r
+ \r
+ return xAllTasksPassed;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationIdleHook( void )\r
+{\r
+/* This variable is effectively set to a constant so it is made volatile to\r
+ensure the compiler does not just get rid of it. */\r
+volatile portLONG lValue;\r
+\r
+ /* Keep performing a calculation and checking the result against a constant. */\r
+\r
+ /* Perform the calculation. This will store partial value in\r
+ registers, resulting in a good test of the context switch mechanism. */\r
+ lValue = intgCONST1;\r
+ lValue += intgCONST2;\r
+ lValue *= intgCONST3;\r
+ lValue /= intgCONST4;\r
+\r
+ /* Did we perform the calculation correctly with no corruption? */\r
+ if( lValue != intgEXPECTED_ANSWER )\r
+ {\r
+ /* Error! */\r
+ portENTER_CRITICAL();\r
+ xLocalError = pdTRUE;\r
+ portEXIT_CRITICAL();\r
+ }\r
+\r
+ /* Yield in case cooperative scheduling is being used. */\r
+ #if configUSE_PREEMPTION == 0\r
+ {\r
+ taskYIELD();\r
+ }\r
+ #endif \r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+\r
--- /dev/null
+/* logical s-record file */\r
+OPENFILE "%ABS_FILE%.s19"\r
+format=motorola\r
+busWidth=1\r
+origin=0\r
+len=0x1000000\r
+destination=0\r
+SRECORD=Sx\r
+SENDBYTE 1 "%ABS_FILE%"\r
+CLOSE\r
+\r
+/* physical s-record file */\r
+OPENFILE "%ABS_FILE%.phy"\r
+format = motorola\r
+busWidth = 1\r
+len = 0x4000\r
+\r
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+SENDBYTE 1 "%ABS_FILE%"\r
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+SENDBYTE 1 "%ABS_FILE%"\r
+\r
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+destination = 0x0F8000\r
+SENDBYTE 1 "%ABS_FILE%"\r
+origin = 0x004000\r
+destination = 0x0F8000\r
+SENDBYTE 1 "%ABS_FILE%"\r
+\r
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+SENDBYTE 1 "%ABS_FILE%"\r
+origin = 0x00C000\r
+destination = 0x0FC000\r
+SENDBYTE 1 "%ABS_FILE%"\r
+\r
+CLOSE\r
+\r
--- /dev/null
+//------------------------------------------------------------------------\r
+// Readme.txt\r
+//------------------------------------------------------------------------\r
+This project stationery is designed to get you up and running\r
+quickly with CodeWarrior for MC9S12DP256B.\r
+It is set up for the selected CPU and target connection,\r
+but can be easily modified.\r
+\r
+Sample code for the following language(s) is at your disposal:\r
+- C\r
+\r
+The wizard has prepared CodeWarrior target(s) with the connection methods of\r
+your choice:\r
+- Simulator:\r
+ This interface/target is prepared to use the FCS (Full Chip Simulation).\r
+\r
+- P&E ICD12:\r
+ This enables to debug with the P&E ICD12 target interface.\r
+ The P&E ICD12 target interface allows to debug using the\r
+ BDM connector with P&E BDM Multilink or Cable12 hardware.\r
+ The BDM Multilink and Cable12 connect to the host parallel port.\r
+ Please consult your hardware documentation for additional details.\r
+\r
+\r
+Additional connections can be chosen in the simulator/debugger,\r
+use the menu Component > Set Target.\r
+\r
+//------------------------------------------------------------------------\r
+// Processor Expert\r
+//------------------------------------------------------------------------\r
+This project is prepared to be designed with Processor Expert.\r
+The project has an additional 'tab' named 'Processor Expert' where you\r
+can configure the CPU and its beans.\r
+The CPU selected is inserted into the Processor Expert project panel, in\r
+the Debug and Release configurations.\r
+Change of the configuration is possible by the mouse double-click on it.\r
+All the installed Embedded Beans are accessible in the Bean Selector\r
+window, grouped into folders according to their function. The mouse\r
+double-click on selected Embedded Bean in the Bean Selector window adds\r
+the Bean to the project. The mouse double-click on the Bean icon in the\r
+Project panel opens the Bean Inspector window, which is used to set the\r
+Bean properties. Source code is generated after selecting the\r
+(Code Design 'Project_name.mcp') menu command from the CodeWarrior main\r
+window (Processor Expert > Code design 'Project_name.mcp').\r
+Use the bean methods and events to write your code in the main module\r
+'Project_name'.c and the event module Events.c.\r
+\r
+For more help please read Processor Expert help:\r
+ (Processor Expert > Help > 'Topic').\r
+\r
+The following folders are used in CodeWarrior project window for\r
+ProcessorExpert:\r
+- User modules: contains your sources. The main module 'Project_name'.c\r
+ and event module Events.c are located here after the Processor Expert\r
+ code generation.\r
+- Prm: Linker parameter file used for linking. Note that the file used\r
+ for the linker is specified in the Linker Preference Panel. To open\r
+ the Preference Panel, please press <ALT-F7> or open the\r
+ (Edit > 'Current Build Target Name' Settings...) menu item in the\r
+ CodeWarrior main window menu, while the project window is opened).\r
+ After Processor Expert code generation 'Project_name'.prm file\r
+ will be placed here. You can switch off the .prm file generation in\r
+ Processor Expert if you want (in the CPU bean, Build Options)\r
+- Generated code: this folder appears after the Processor Expert code\r
+ generation and contains generated code from Processor Expert.\r
+- Doc: other files generated from the Processor Expert (documentation)\r
+\r
+//------------------------------------------------------------------------\r
+// Getting Started\r
+//------------------------------------------------------------------------\r
+To build/debug your project, use the menu Project > Debug or press F5.\r
+This will open the simulator/debugger.\r
+Press again F5 in the debugger (or menu Run > Start/Continue) to start\r
+the application. The menu Run > Halt or F6 stops the application.\r
+In the debugger menu Component > Open you can load additional components.\r
+\r
+//------------------------------------------------------------------------\r
+// Project structure\r
+//------------------------------------------------------------------------\r
+The project generated contains various files/folders:\r
+- readme.txt: this file\r
+- Sources: folder with the application source code\r
+- Startup Code: C/C++ startup code\r
+- Prm:\r
+ - burner.bbl file to generate S-Records\r
+- Linker Map: the .map file generated by the linker\r
+- Libraries: needed library files (ANSI, derivative header/implementation files)\r
+- Debugger Project File: contains a .ini file for the debugger for each\r
+ connection\r
+- Debugger Cmd Files: contains sub-folders for each connection with command\r
+ files\r
+\r
+//------------------------------------------------------------------------\r
+// Adding your own code\r
+//------------------------------------------------------------------------\r
+Once everything is working as expected, you can begin adding your own code\r
+to the project. Keep in mind that we provide this as an example of how to\r
+get up and running quickly with CodeWarrior. There are certainly other\r
+ways to handle interrupts and set up your linker command file. Feel free\r
+to modify any of the source files provided.\r
+\r
+//------------------------------------------------------------------------\r
+// Simulator/Debugger: Additional components\r
+//------------------------------------------------------------------------\r
+In the simulator/debugger, you can load additional components. Try the menu\r
+Component > Open.\r
+\r
+//------------------------------------------------------------------------\r
+// Additional documentation\r
+//------------------------------------------------------------------------\r
+Check out the online documentation provided. Use in CodeWarrior IDE the\r
+menu Help > Online Manuals.\r
+\r
+//------------------------------------------------------------------------\r
+// Contacting Metrowerks\r
+//------------------------------------------------------------------------\r
+For bug reports, technical questions, and suggestions, please use the\r
+forms installed in the Release_Notes folder and send them to:\r
+USA: support@metrowerks.com\r
+EUROPE: support_europe@metrowerks.com\r
+ASIA/PACIFIC: j-emb-sup@metrowerks.com
\ No newline at end of file
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+\r
+/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER for port 1.\r
+\r
+Note that this driver is written to test the RTOS port and is not intended\r
+to represent an optimised solution. */\r
+\r
+/* Processor Expert generated includes. */\r
+#include "com0.h"\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "queue.h"\r
+#include "task.h"\r
+\r
+/* Demo application include files. */\r
+#include "serial.h"\r
+\r
+/* The queues used to communicate between the task code and the interrupt\r
+service routines. */\r
+static xQueueHandle xRxedChars; \r
+static xQueueHandle xCharsForTx; \r
+\r
+/* Interrupt identification bits. */\r
+#define serOVERRUN_INTERRUPT ( 0x08 )\r
+#define serRX_INTERRUPT ( 0x20 )\r
+#define serTX_INTERRUPT ( 0x80 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+/*\r
+ * Initialise port for interrupt driven communications.\r
+ */\r
+xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )\r
+{\r
+ /* Hardware setup is performed by the Processor Expert generated code. \r
+ This function just creates the queues used to communicate between the \r
+ interrupt code and the task code - then sets the required baud rate. */\r
+\r
+ xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );\r
+ xCharsForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );\r
+\r
+ COM0_SetBaudRateMode( ( portCHAR ) ulWantedBaud );\r
+\r
+ return NULL;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )\r
+{\r
+ /* Get the next character from the buffer queue. Return false if no characters\r
+ are available, or arrive before xBlockTime expires. */\r
+ if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )\r
+ {\r
+ return pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ return pdFALSE;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )\r
+{\r
+ /* Place the character in the queue of characters to be transmitted. */\r
+ if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )\r
+ {\r
+ return pdFAIL;\r
+ }\r
+\r
+ /* Turn on the Tx interrupt so the ISR will remove the character from the\r
+ queue and send it. This does not need to be in a critical section as\r
+ if the interrupt has already removed the character the next interrupt\r
+ will simply turn off the Tx interrupt again. */\r
+ SCI0CR2_SCTIE = 1;;\r
+\r
+ return pdPASS;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSerialClose( xComPortHandle xPort )\r
+{ \r
+ /* Not supported. */\r
+ ( void ) xPort;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+/* \r
+ * Interrupt service routine for the serial port. Must be in non-banked\r
+ * memory. \r
+ */\r
+\r
+#pragma CODE_SEG __NEAR_SEG NON_BANKED\r
+\r
+__interrupt void vCOM0_ISR( void )\r
+{\r
+volatile unsigned portCHAR ucByte, ucStatus;\r
+portBASE_TYPE xTaskWokenByPost = pdFALSE, xTaskWokenByTx = pdFALSE;\r
+\r
+ /* What caused the interrupt? */\r
+ ucStatus = SCI0SR1;\r
+ \r
+ if( ucStatus & serOVERRUN_INTERRUPT )\r
+ {\r
+ /* The interrupt was caused by an overrun. Clear the error by reading\r
+ the data register. */\r
+ ucByte = SCI0DRL;\r
+ }\r
+\r
+ if( ucStatus & serRX_INTERRUPT )\r
+ { \r
+ /* The interrupt was caused by a character being received.\r
+ Read the received byte. */\r
+ ucByte = SCI0DRL; \r
+\r
+ /* Post the character onto the queue of received characters - noting\r
+ whether or not this wakes a task. */\r
+ xTaskWokenByPost = xQueueSendFromISR( xRxedChars, ( void * ) &ucByte, pdFALSE ); \r
+ }\r
+ \r
+ if( ( ucStatus & serTX_INTERRUPT ) && ( SCI0CR2_SCTIE ) )\r
+ { \r
+ /* The interrupt was caused by a character being transmitted. */\r
+ if( xQueueReceiveFromISR( xCharsForTx, ( void * ) &ucByte, &xTaskWokenByTx ) == pdTRUE )\r
+ {\r
+ /* Clear the SCRF bit. */\r
+ SCI0DRL = ucByte;\r
+ }\r
+ else\r
+ {\r
+ /* Disable transmit interrupt */\r
+ SCI0CR2_SCTIE = 0; \r
+ }\r
+ }\r
+\r
+ if( ( xTaskWokenByPost ) || ( xTaskWokenByTx ) )\r
+ {\r
+ portYIELD();\r
+ }\r
+}\r
+\r
+#pragma CODE_SEG DEFAULT\r
+\r
--- /dev/null
+/** ###################################################################\r
+** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.\r
+** Filename : ButtonInterrupt.C\r
+** Project : RTOSDemo\r
+** Processor : MC9S12C32CFU\r
+** Beantype : ExtInt\r
+** Version : Bean 02.025, Driver 01.06, CPU db: 2.87.276\r
+** Compiler : Metrowerks HC12 C Compiler\r
+** Date/Time : 19/05/2005, 19:02\r
+** Abstract :\r
+** This bean "ExtInt" implements an external \r
+** interrupt, its control methods and interrupt/event \r
+** handling procedure.\r
+** The bean uses one pin which generates interrupt on \r
+** selected edge.\r
+** Settings :\r
+** Interrupt name : INT_PortP\r
+** User handling procedure : ButtonInterrupt_OnInterrupt\r
+**\r
+** Used pin : \r
+** ----------------------------------------------------\r
+** Number (on package) | Name\r
+** ----------------------------------------------------\r
+** 4 | PP0_PWM0_KWP0\r
+** ----------------------------------------------------\r
+**\r
+** Port name : P\r
+**\r
+** Bit number (in port) : 0\r
+** Bit mask of the port : 1\r
+**\r
+** Signal edge/level : falling\r
+** Priority : 1\r
+** Pull option : up\r
+** Initial state : Disabled\r
+**\r
+** Edge register : PPSP [605]\r
+** Priority register : HPRIO [31]\r
+** Enable register : PIEP [606]\r
+** Request register : PIFP [607]\r
+**\r
+** Port data register : PTP [600]\r
+** Port control register : DDRP [602]\r
+** Contents :\r
+** Enable - void ButtonInterrupt_Enable(void);\r
+**\r
+** (c) Copyright UNIS, spol. s r.o. 1997-2002\r
+** UNIS, spol. s r.o.\r
+** Jundrovska 33\r
+** 624 00 Brno\r
+** Czech Republic\r
+** http : www.processorexpert.com\r
+** mail : info@processorexpert.com\r
+** ###################################################################*/\r
+\r
+\r
+/* MODULE ButtonInterrupt. */\r
+\r
+#include "ButtonInterrupt.h"\r
+/*Including shared modules, which are used for all project*/\r
+#include "PE_Types.h"\r
+#include "PE_Error.h"\r
+#include "PE_Const.h"\r
+#include "IO_Map.h"\r
+#include "PE_Timer.h"\r
+#include "Events.h"\r
+#include "Cpu.h"\r
+\r
+/* Definition of DATA and CODE segments for this bean. User can specify where\r
+ these segments will be located on "Build options" tab of the selected CPU bean. */\r
+#pragma DATA_SEG ButtonInterrupt_DATA /* Data section for this module. */\r
+#pragma CODE_SEG ButtonInterrupt_CODE /* Code section for this module. */\r
+\r
+/*\r
+** ===================================================================\r
+** Method : ButtonInterrupt_Enable (bean ExtInt)\r
+**\r
+** Description :\r
+** Enable the bean - the external events are accepted.\r
+** Parameters : None\r
+** Returns : Nothing\r
+** ===================================================================\r
+*/\r
+void ButtonInterrupt_Enable(void)\r
+{\r
+ PIFP = 1; /* Clear flag */\r
+ PIEP_PIEP0 = 1; /* Enable interrupt */\r
+}\r
+\r
+/*\r
+** ===================================================================\r
+** Method : ButtonInterrupt_Interrupt (bean ExtInt)\r
+**\r
+** Description :\r
+** This method is internal. It is used by Processor Expert\r
+** only.\r
+** ===================================================================\r
+*/\r
+#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */\r
+__interrupt void ButtonInterrupt_Interrupt(void)\r
+{\r
+ PIFP = 1; /* Clear flag */\r
+ ButtonInterrupt_OnInterrupt();\r
+}\r
+\r
+#pragma CODE_SEG ButtonInterrupt_CODE /* Code section for this module. */\r
+\r
+/* END ButtonInterrupt. */\r
+\r
+/*\r
+** ###################################################################\r
+**\r
+** This file was created by UNIS Processor Expert 03.33 for \r
+** the Motorola HCS12 series of microcontrollers.\r
+**\r
+** ###################################################################\r
+*/\r
--- /dev/null
+/** ###################################################################\r
+** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.\r
+** Filename : ButtonInterrupt.H\r
+** Project : RTOSDemo\r
+** Processor : MC9S12C32CFU\r
+** Beantype : ExtInt\r
+** Version : Bean 02.025, Driver 01.06, CPU db: 2.87.276\r
+** Compiler : Metrowerks HC12 C Compiler\r
+** Date/Time : 19/05/2005, 19:02\r
+** Abstract :\r
+** This bean "ExtInt" implements an external \r
+** interrupt, its control methods and interrupt/event \r
+** handling procedure.\r
+** The bean uses one pin which generates interrupt on \r
+** selected edge.\r
+** Settings :\r
+** Interrupt name : INT_PortP\r
+** User handling procedure : ButtonInterrupt_OnInterrupt\r
+**\r
+** Used pin : \r
+** ----------------------------------------------------\r
+** Number (on package) | Name\r
+** ----------------------------------------------------\r
+** 4 | PP0_PWM0_KWP0\r
+** ----------------------------------------------------\r
+**\r
+** Port name : P\r
+**\r
+** Bit number (in port) : 0\r
+** Bit mask of the port : 1\r
+**\r
+** Signal edge/level : falling\r
+** Priority : 1\r
+** Pull option : up\r
+** Initial state : Disabled\r
+**\r
+** Edge register : PPSP [605]\r
+** Priority register : HPRIO [31]\r
+** Enable register : PIEP [606]\r
+** Request register : PIFP [607]\r
+**\r
+** Port data register : PTP [600]\r
+** Port control register : DDRP [602]\r
+** Contents :\r
+** Enable - void ButtonInterrupt_Enable(void);\r
+**\r
+** (c) Copyright UNIS, spol. s r.o. 1997-2002\r
+** UNIS, spol. s r.o.\r
+** Jundrovska 33\r
+** 624 00 Brno\r
+** Czech Republic\r
+** http : www.processorexpert.com\r
+** mail : info@processorexpert.com\r
+** ###################################################################*/\r
+\r
+#ifndef __ButtonInterrupt_H\r
+#define __ButtonInterrupt_H\r
+\r
+/* MODULE ButtonInterrupt. */\r
+\r
+/*Including shared modules, which are used in the whole project*/\r
+#include "PE_Types.h"\r
+#include "PE_Error.h"\r
+#include "PE_Const.h"\r
+#include "IO_Map.h"\r
+#include "PE_Timer.h"\r
+#include "Events.h"\r
+#include "Cpu.h"\r
+\r
+#pragma CODE_SEG ButtonInterrupt_CODE /* Code section for this module. */\r
+\r
+void ButtonInterrupt_Enable(void);\r
+/*\r
+** ===================================================================\r
+** Method : ButtonInterrupt_Enable (bean ExtInt)\r
+**\r
+** Description :\r
+** Enable the bean - the external events are accepted.\r
+** Parameters : None\r
+** Returns : Nothing\r
+** ===================================================================\r
+*/\r
+\r
+#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */\r
+__interrupt void ButtonInterrupt_Interrupt(void);\r
+#pragma CODE_SEG ButtonInterrupt_CODE /* Code section for this module. */\r
+/*\r
+** ===================================================================\r
+** Method : ButtonInterrupt_Interrupt (bean ExtInt)\r
+**\r
+** Description :\r
+** This method is internal. It is used by Processor Expert\r
+** only.\r
+** ===================================================================\r
+*/\r
+\r
+#pragma CODE_SEG DEFAULT /* Change code section to DEFAULT. */\r
+\r
+/* END ButtonInterrupt. */\r
+\r
+#endif /* __ButtonInterrupt_H*/\r
+/*\r
+** ###################################################################\r
+**\r
+** This file was created by UNIS Processor Expert 03.33 for \r
+** the Motorola HCS12 series of microcontrollers.\r
+**\r
+** ###################################################################\r
+*/\r
--- /dev/null
+/** ###################################################################\r
+** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.\r
+** Filename : Byte1.C\r
+** Project : RTOSDemo\r
+** Processor : MC9S12C32CFU\r
+** Beantype : ByteIO\r
+** Version : Bean 02.019, Driver 01.03, CPU db: 2.87.276\r
+** Compiler : Metrowerks HC12 C Compiler\r
+** Date/Time : 10/05/2005, 11:49\r
+** Abstract :\r
+** This bean "ByteIO" implements an one-byte input/output.\r
+** It uses one 8-bit port.\r
+** Note: This bean is set to work in Output direction only.\r
+** Methods of this bean are mostly implemented as a macros \r
+** (if supported by target langauage and compiler).\r
+** Settings :\r
+** Port name : B\r
+**\r
+** Initial direction : Output (direction cannot be changed)\r
+** Initial output value : 0 = 000H\r
+** Initial pull option : off\r
+**\r
+** 8-bit data register : PORTB [1]\r
+** 8-bit control register : DDRB [3]\r
+**\r
+** ----------------------------------------------------\r
+** Bit | Pin | Name\r
+** ----------------------------------------------------\r
+** 0 | 16 | PB0_ADDR0_DATA0\r
+** 1 | 17 | PB1_ADDR1_DATA1\r
+** 2 | 18 | PB2_ADDR2_DATA2\r
+** 3 | 19 | PB3_ADDR3_DATA3\r
+** 4 | 20 | PB4_ADDR4_DATA4\r
+** 5 | 21 | PB5_ADDR5_DATA5\r
+** 6 | 22 | PB6_ADDR6_DATA6\r
+** 7 | 23 | PB7_ADDR7_DATA7\r
+** ----------------------------------------------------\r
+** Contents :\r
+** PutBit - void Byte1_PutBit(byte Bit,bool Val);\r
+** NegBit - void Byte1_NegBit(byte Bit);\r
+**\r
+** (c) Copyright UNIS, spol. s r.o. 1997-2002\r
+** UNIS, spol. s r.o.\r
+** Jundrovska 33\r
+** 624 00 Brno\r
+** Czech Republic\r
+** http : www.processorexpert.com\r
+** mail : info@processorexpert.com\r
+** ###################################################################*/\r
+\r
+\r
+/* MODULE Byte1. */\r
+\r
+#include "Byte1.h"\r
+/*Including shared modules, which are used for all project*/\r
+#include "PE_Types.h"\r
+#include "PE_Error.h"\r
+#include "PE_Const.h"\r
+#include "IO_Map.h"\r
+\r
+#include "Cpu.h"\r
+\r
+/* Definition of DATA and CODE segments for this bean. User can specify where\r
+ these segments will be located on "Build options" tab of the selected CPU bean. */\r
+#pragma DATA_SEG Byte1_DATA /* Data section for this module. */\r
+#pragma CODE_SEG Byte1_CODE /* Code section for this module. */\r
+\r
+/*\r
+** ===================================================================\r
+** Method : Byte1_GetMsk (bean ByteIO)\r
+**\r
+** Description :\r
+** This method is internal. It is used by Processor Expert\r
+** only.\r
+** ===================================================================\r
+*/\r
+byte Byte1_Table[8]={ 1, 2, 4, 8, 16, 32, 64, 128 }; /* Table of mask constants */\r
+\r
+byte Byte1_GetMsk(byte Value)\r
+{\r
+ return((Value<8)?Byte1_Table[Value]:0); /* Return appropriate bit mask */\r
+}\r
+\r
+/*\r
+** ===================================================================\r
+** Method : Byte1_PutBit (bean ByteIO)\r
+**\r
+** Description :\r
+** This method writes the new value to the specified bit\r
+** of the output value.\r
+** Parameters :\r
+** NAME - DESCRIPTION\r
+** Bitnum - Number of the bit (0 to 7)\r
+** Val - New value of the bit (FALSE or TRUE)\r
+** FALSE = "0" or "Low", TRUE = "1" or "High"\r
+** Returns : Nothing\r
+** ===================================================================\r
+*/\r
+void Byte1_PutBit(byte BitNum, byte Value)\r
+{\r
+ byte Mask=Byte1_GetMsk(BitNum); /* Temporary variable - bit mask */\r
+\r
+ if (Mask) /* Is bit mask correct? */\r
+ if (Value) { /* Is it one to be written? */\r
+ PORTB |= Mask; /* Set appropriate bit on port */\r
+ }\r
+ else { /* Is it zero to be written? */\r
+ PORTB &= ~Mask; /* Clear appropriate bit on port */\r
+ }\r
+}\r
+\r
+/*\r
+** ===================================================================\r
+** Method : Byte1_NegBit (bean ByteIO)\r
+**\r
+** Description :\r
+** This method negates (invertes) the specified bit of the\r
+** output value.\r
+** Parameters :\r
+** NAME - DESCRIPTION\r
+** Bit - Number of the bit to invert (0 to 7)\r
+** Returns : Nothing\r
+** ===================================================================\r
+*/\r
+void Byte1_NegBit(byte BitNum)\r
+{\r
+ byte Mask=Byte1_GetMsk(BitNum); /* Temporary variable - bit mask */\r
+\r
+ if (Mask) { /* Is bit mask correct? */\r
+ PORTB ^= Mask; /* Negate appropriate bit on port */\r
+ }\r
+}\r
+\r
+\r
+/* END Byte1. */\r
+\r
+/*\r
+** ###################################################################\r
+**\r
+** This file was created by UNIS Processor Expert 03.33 for \r
+** the Motorola HCS12 series of microcontrollers.\r
+**\r
+** ###################################################################\r
+*/\r
--- /dev/null
+/** ###################################################################\r
+** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.\r
+** Filename : Byte1.H\r
+** Project : RTOSDemo\r
+** Processor : MC9S12C32CFU\r
+** Beantype : ByteIO\r
+** Version : Bean 02.019, Driver 01.03, CPU db: 2.87.276\r
+** Compiler : Metrowerks HC12 C Compiler\r
+** Date/Time : 10/05/2005, 11:49\r
+** Abstract :\r
+** This bean "ByteIO" implements an one-byte input/output.\r
+** It uses one 8-bit port.\r
+** Note: This bean is set to work in Output direction only.\r
+** Methods of this bean are mostly implemented as a macros \r
+** (if supported by target langauage and compiler).\r
+** Settings :\r
+** Port name : B\r
+**\r
+** Initial direction : Output (direction cannot be changed)\r
+** Initial output value : 0 = 000H\r
+** Initial pull option : off\r
+**\r
+** 8-bit data register : PORTB [1]\r
+** 8-bit control register : DDRB [3]\r
+**\r
+** ----------------------------------------------------\r
+** Bit | Pin | Name\r
+** ----------------------------------------------------\r
+** 0 | 16 | PB0_ADDR0_DATA0\r
+** 1 | 17 | PB1_ADDR1_DATA1\r
+** 2 | 18 | PB2_ADDR2_DATA2\r
+** 3 | 19 | PB3_ADDR3_DATA3\r
+** 4 | 20 | PB4_ADDR4_DATA4\r
+** 5 | 21 | PB5_ADDR5_DATA5\r
+** 6 | 22 | PB6_ADDR6_DATA6\r
+** 7 | 23 | PB7_ADDR7_DATA7\r
+** ----------------------------------------------------\r
+** Contents :\r
+** PutBit - void Byte1_PutBit(byte Bit,bool Val);\r
+** NegBit - void Byte1_NegBit(byte Bit);\r
+**\r
+** (c) Copyright UNIS, spol. s r.o. 1997-2002\r
+** UNIS, spol. s r.o.\r
+** Jundrovska 33\r
+** 624 00 Brno\r
+** Czech Republic\r
+** http : www.processorexpert.com\r
+** mail : info@processorexpert.com\r
+** ###################################################################*/\r
+\r
+#ifndef __Byte1_H\r
+#define __Byte1_H\r
+\r
+/* MODULE Byte1. */\r
+\r
+/*Including shared modules, which are used in the whole project*/\r
+#include "PE_Types.h"\r
+#include "PE_Error.h"\r
+#include "PE_Const.h"\r
+#include "IO_Map.h"\r
+\r
+#include "Cpu.h"\r
+\r
+#pragma CODE_SEG Byte1_CODE /* Code section for this module. */\r
+\r
+/*\r
+** ===================================================================\r
+** Method : Byte1_PutBit (bean ByteIO)\r
+**\r
+** Description :\r
+** This method writes the new value to the specified bit\r
+** of the output value.\r
+** Parameters :\r
+** NAME - DESCRIPTION\r
+** BitNum - Number of the bit (0 to 7)\r
+** Val - New value of the bit (FALSE or TRUE)\r
+** FALSE = "0" or "Low", TRUE = "1" or "High"\r
+** Returns : Nothing\r
+** ===================================================================\r
+*/\r
+void Byte1_PutBit(byte BitNum, byte Value);\r
+\r
+/*\r
+** ===================================================================\r
+** Method : Byte1_NegBit (bean ByteIO)\r
+**\r
+** Description :\r
+** This method negates (invertes) the specified bit of the\r
+** output value.\r
+** Parameters :\r
+** NAME - DESCRIPTION\r
+** BitNum - Number of the bit to invert (0 to 7)\r
+** Returns : Nothing\r
+** ===================================================================\r
+*/\r
+void Byte1_NegBit(byte BitNum);\r
+\r
+#pragma CODE_SEG DEFAULT /* Change code section to DEFAULT. */\r
+\r
+/* END Byte1. */\r
+\r
+#endif /* __Byte1_H*/\r
+/*\r
+** ###################################################################\r
+**\r
+** This file was created by UNIS Processor Expert 03.33 for \r
+** the Motorola HCS12 series of microcontrollers.\r
+**\r
+** ###################################################################\r
+*/\r
--- /dev/null
+/** ###################################################################\r
+** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.\r
+** Filename : Cpu.C\r
+** Project : RTOSDemo\r
+** Processor : MC9S12C32CFU\r
+** Beantype : MC9S12C32_80\r
+** Version : Bean 01.002, Driver 01.09, CPU db: 2.87.276\r
+** Compiler : Metrowerks HC12 C Compiler\r
+** Date/Time : 17/05/2005, 18:22\r
+** Abstract :\r
+** This bean "MC9S12C32_80" implements properties, methods,\r
+** and events of the CPU.\r
+** Settings :\r
+**\r
+** Contents :\r
+** EnableInt - void Cpu_EnableInt(void);\r
+** DisableInt - void Cpu_DisableInt(void);\r
+** SetWaitMode - void Cpu_SetWaitMode(void);\r
+** SetStopMode - void Cpu_SetStopMode(void);\r
+**\r
+** (c) Copyright UNIS, spol. s r.o. 1997-2002\r
+** UNIS, spol. s r.o.\r
+** Jundrovska 33\r
+** 624 00 Brno\r
+** Czech Republic\r
+** http : www.processorexpert.com\r
+** mail : info@processorexpert.com\r
+** ###################################################################*/\r
+\r
+\r
+#include "Cpu.h"\r
+#include "Byte1.h"\r
+#include "TickTimer.h"\r
+#include "ButtonInterrupt.h"\r
+\r
+extern void near _EntryPoint(void); /* Startup routine */\r
+extern void near vPortTickInterrupt( void );\r
+extern void near vPortYield( void );\r
+extern void near vButtonPush( void );\r
+\r
+typedef void (*near tIsrFunc)(void);\r
+const tIsrFunc _vect[] @0xFF80 = { /* Interrupt table */\r
+ Cpu_Interrupt, /* 0 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 1 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 2 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 3 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 4 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 5 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 6 Default (unused) interrupt */\r
+ vButtonPush, /* 7 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 8 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 9 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 10 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 11 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 12 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 13 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 14 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 15 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 16 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 17 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 18 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 19 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 20 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 21 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 22 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 23 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 24 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 25 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 26 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 27 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 28 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 29 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 30 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 31 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 32 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 33 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 34 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 35 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 36 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 37 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 38 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 39 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 40 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 41 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 42 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 43 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 44 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 45 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 46 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 47 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 48 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 49 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 50 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 51 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 52 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 53 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 54 Default (unused) interrupt */\r
+ vPortTickInterrupt,\r
+ Cpu_Interrupt, /* 56 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 57 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 58 Default (unused) interrupt */\r
+ vPortYield, /* 59 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 60 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 61 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 62 Default (unused) interrupt */\r
+ _EntryPoint /* Reset vector */\r
+ };\r
+/*\r
+** ###################################################################\r
+**\r
+** This file was created by UNIS Processor Expert 03.33 for \r
+** the Motorola HCS12 series of microcontrollers.\r
+**\r
+** ###################################################################\r
+*/
\ No newline at end of file
--- /dev/null
+/** ###################################################################\r
+** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.\r
+** Filename : Cpu.C\r
+** Project : RTOSDemo\r
+** Processor : MC9S12C32CFU\r
+** Beantype : MC9S12C32_80\r
+** Version : Bean 01.002, Driver 01.09, CPU db: 2.87.276\r
+** Compiler : Metrowerks HC12 C Compiler\r
+** Date/Time : 18/06/2005, 18:00\r
+** Abstract :\r
+** This bean "MC9S12C32_80" implements properties, methods,\r
+** and events of the CPU.\r
+** Settings :\r
+**\r
+** Contents :\r
+** EnableInt - void Cpu_EnableInt(void);\r
+** DisableInt - void Cpu_DisableInt(void);\r
+** SetWaitMode - void Cpu_SetWaitMode(void);\r
+** SetStopMode - void Cpu_SetStopMode(void);\r
+**\r
+** (c) Copyright UNIS, spol. s r.o. 1997-2002\r
+** UNIS, spol. s r.o.\r
+** Jundrovska 33\r
+** 624 00 Brno\r
+** Czech Republic\r
+** http : www.processorexpert.com\r
+** mail : info@processorexpert.com\r
+** ###################################################################*/\r
+\r
+/* MODULE Cpu. */\r
+\r
+#include "Byte1.h"\r
+#include "TickTimer.h"\r
+#include "ButtonInterrupt.h"\r
+#include "PE_Types.h"\r
+#include "PE_Error.h"\r
+#include "PE_Const.h"\r
+#include "IO_Map.h"\r
+#include "PE_Timer.h"\r
+#include "Events.h"\r
+#include "Cpu.h"\r
+\r
+#define CGM_DELAY 3071UL\r
+\r
+\r
+/* Global variables */\r
+volatile byte CCR_reg; /* Current CCR reegister */\r
+byte CpuMode = HIGH_SPEED; /* Current speed mode */\r
+\r
+\r
+/*\r
+** ===================================================================\r
+** Method : Cpu_Interrupt (bean MC9S12C32_80)\r
+**\r
+** Description :\r
+** This method is internal. It is used by Processor Expert\r
+** only.\r
+** ===================================================================\r
+*/\r
+#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */\r
+\r
+__interrupt void Cpu_Interrupt(void)\r
+{\r
+}\r
+\r
+#pragma CODE_SEG DEFAULT /* Change code section to DEFAULT. */\r
+\r
+/*\r
+** ===================================================================\r
+** Method : Cpu_DisableInt (bean MC9S12C32_80)\r
+**\r
+** Description :\r
+** Disable maskable interrupts\r
+** Parameters : None\r
+** Returns : Nothing\r
+** ===================================================================\r
+*/\r
+/*\r
+void Cpu_DisableInt(void)\r
+\r
+** This method is implemented as macro in the header module. **\r
+*/\r
+\r
+/*\r
+** ===================================================================\r
+** Method : Cpu_EnableInt (bean MC9S12C32_80)\r
+**\r
+** Description :\r
+** Enable maskable interrupts\r
+** Parameters : None\r
+** Returns : Nothing\r
+** ===================================================================\r
+*/\r
+/*\r
+void Cpu_EnableInt(void)\r
+\r
+** This method is implemented as macro in the header module. **\r
+*/\r
+\r
+/*\r
+** ===================================================================\r
+** Method : Cpu_SetStopMode (bean MC9S12C32_80)\r
+**\r
+** Description :\r
+** Set low power mode - Stop mode. For more information\r
+** about the stop mode see documentation of this CPU.\r
+** Parameters : None\r
+** Returns : Nothing\r
+** ===================================================================\r
+*/\r
+/*\r
+void Cpu_SetStopMode(void)\r
+\r
+** This method is implemented as macro in the header module. **\r
+*/\r
+\r
+/*\r
+** ===================================================================\r
+** Method : Cpu_SetWaitMode (bean MC9S12C32_80)\r
+**\r
+** Description :\r
+** Set low power mode - Wait mode. For more information\r
+** about the wait mode see documentation of this CPU.\r
+** Release from Watch mode: Reset or interrupt\r
+** Parameters : None\r
+** Returns : Nothing\r
+** ===================================================================\r
+*/\r
+/*\r
+void Cpu_SetWaitMode(void)\r
+\r
+** This method is implemented as macro in the header module. **\r
+*/\r
+\r
+/*\r
+** ===================================================================\r
+** Method : _EntryPoint (bean MC9S12C32_80)\r
+**\r
+** Description :\r
+** This method is internal. It is used by Processor Expert\r
+** only.\r
+** ===================================================================\r
+*/\r
+extern void _Startup(void); /* Forward declaration of external startup function declared in file Start12.c */\r
+#define INITRG_ADR 0x0011 /* Register map position register */\r
+#pragma NO_FRAME\r
+#pragma NO_EXIT\r
+void _EntryPoint(void)\r
+{\r
+ /*** ### MC9S12C32_80 "Cpu" init code ... ***/\r
+ /*** PE initialization code after reset ***/\r
+ /* Initialization of the registers INITRG, INITRM, INITEE is done to protect them to be written accidentally later by the application */\r
+ *(byte*)INITRG_ADR = 0; /* Set the register map position */\r
+ asm nop; /* nop instruction */\r
+ INITRM=8; /* Set the RAM map position */\r
+ /* MISC: ??=0,??=0,??=0,??=0,EXSTR1=0,EXSTR0=0,ROMHM=0,ROMON=1 */\r
+ MISC=1;\r
+ /* System clock initialization */\r
+ CLKSEL=0;\r
+ CLKSEL_PLLSEL = 0; /* Select clock source from XTAL */\r
+ PLLCTL_PLLON = 0; /* Disable the PLL */\r
+ SYNR = 23; /* Set the multiplier register */\r
+ REFDV = 15; /* Set the divider register */\r
+ PLLCTL = 192;\r
+ PLLCTL_PLLON = 1; /* Enable the PLL */\r
+ while(!CRGFLG_LOCK); /* Wait */\r
+ CLKSEL_PLLSEL = 1; /* Select clock source from PLL */\r
+ /*** End of PE initialization code after reset ***/\r
+\r
+ __asm jmp _Startup; /* Jump to C startup code */\r
+}\r
+\r
+/*\r
+** ===================================================================\r
+** Method : PE_low_level_init (bean MC9S12C32_80)\r
+**\r
+** Description :\r
+** This method is internal. It is used by Processor Expert\r
+** only.\r
+** ===================================================================\r
+*/\r
+void PE_low_level_init(void)\r
+{\r
+ /* Common initialization of the CPU registers */\r
+/* TSCR1: TEN=0,TSWAI=0,TSFRZ=1 */\r
+ output( TSCR1, input( TSCR1 ) & ~192 | 32 );\r
+/* TCTL2: OM0=0,OL0=0 */\r
+ output( TCTL2, input( TCTL2 ) & ~3 );\r
+/* TCTL1: OM7=0,OL7=0 */\r
+ output( TCTL1, input( TCTL1 ) & ~192 );\r
+/* TIE: C0I=0 */\r
+ output( TIE, input( TIE ) & ~1 );\r
+/* TTOV: TOV0=0 */\r
+ output( TTOV, input( TTOV ) & ~1 );\r
+/* TSCR2: TOI=0,TCRE=1 */\r
+ output( TSCR2, input( TSCR2 ) & ~128 | 8 );\r
+/* TIOS: IOS7=1,IOS0=1 */\r
+ output( TIOS, input( TIOS ) | 129 );\r
+/* PPSP: PPSP0=0 */\r
+ output( PPSP, input( PPSP ) & ~1 );\r
+/* PERP: PERP0=1 */\r
+ output( PERP, input( PERP ) | 1 );\r
+/* DDRP: DDRP0=0 */\r
+ output( DDRP, input( DDRP ) & ~1 );\r
+/* PWMCTL: PSWAI=0,PFRZ=0 */\r
+ output( PWMCTL, input( PWMCTL ) & ~12 );\r
+/* PWMSDN: PWMIF=0,PWMIE=0,PWMRSTRT=0,PWMLVL=0,??=0,PWM7IN=0,PWM7INL=0,PWM7ENA=0 */\r
+ output( PWMSDN, 0 );\r
+ /* ### MC9S12C32_80 "Cpu" init code ... */\r
+ /* ### ByteIO "Byte1" init code ... */\r
+ PORTB = 0; /* Prepare value for output */\r
+ DDRB = 255; /* Set direction to output */\r
+ /* ### TimerInt "TickTimer" init code ... */\r
+ TickTimer_Init();\r
+ /* ### External interrupt "ButtonInterrupt" init code ... */\r
+ PIEP_PIEP0 = 0; /* Disable interrupt */\r
+ /* Common peripheral initialization - ENABLE */\r
+/* TSCR1: TEN=1 */\r
+ output( TSCR1, input( TSCR1 ) | 128 );\r
+ INTCR_IRQEN = 0; /* Disable the IRQ interrupt. IRQ interrupt is enabled after CPU reset by default. */\r
+ __DI(); /* Disable interrupts */\r
+}\r
+\r
+/* END Cpu. */\r
+\r
+/*\r
+** ###################################################################\r
+**\r
+** This file was created by UNIS Processor Expert 03.33 for \r
+** the Motorola HCS12 series of microcontrollers.\r
+**\r
+** ###################################################################\r
+*/\r
--- /dev/null
+/** ###################################################################\r
+** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.\r
+** Filename : Cpu.H\r
+** Project : RTOSDemo\r
+** Processor : MC9S12C32CFU\r
+** Beantype : MC9S12C32_80\r
+** Version : Bean 01.002, Driver 01.09, CPU db: 2.87.276\r
+** Compiler : Metrowerks HC12 C Compiler\r
+** Date/Time : 17/05/2005, 08:36\r
+** Abstract :\r
+** This bean "MC9S12C32_80" implements properties, methods,\r
+** and events of the CPU.\r
+** Settings :\r
+**\r
+** Contents :\r
+** EnableInt - void Cpu_EnableInt(void);\r
+** DisableInt - void Cpu_DisableInt(void);\r
+** SetWaitMode - void Cpu_SetWaitMode(void);\r
+** SetStopMode - void Cpu_SetStopMode(void);\r
+**\r
+** (c) Copyright UNIS, spol. s r.o. 1997-2002\r
+** UNIS, spol. s r.o.\r
+** Jundrovska 33\r
+** 624 00 Brno\r
+** Czech Republic\r
+** http : www.processorexpert.com\r
+** mail : info@processorexpert.com\r
+** ###################################################################*/\r
+\r
+#ifndef __Cpu\r
+#define __Cpu\r
+\r
+/* Active configuration define symbol */\r
+#define PEcfg_80pin 1\r
+\r
+/*Include shared modules, which are used for whole project*/\r
+#include "PE_Types.h"\r
+#include "PE_Error.h"\r
+#include "PE_Const.h"\r
+#include "IO_Map.h"\r
+#include "PE_Timer.h"\r
+\r
+/* MODULE Cpu. */\r
+\r
+\r
+/* Global variables */\r
+extern volatile byte CCR_reg; /* Current CCR reegister */\r
+extern byte CpuMode; /* Current speed mode */\r
+\r
+\r
+#define Cpu_SetStopMode() __asm("STOP") /* Set STOP mode */\r
+/*\r
+** ===================================================================\r
+** Method : Cpu_SetStopMode (bean MC9S12C32_80)\r
+**\r
+** Description :\r
+** Set low power mode - Stop mode. For more information\r
+** about the stop mode see documentation of this CPU.\r
+** Parameters : None\r
+** Returns : Nothing\r
+** ===================================================================\r
+*/\r
+\r
+#define Cpu_SetWaitMode() __asm("WAIT") /* Set WAIT mode */\r
+/*\r
+** ===================================================================\r
+** Method : Cpu_SetWaitMode (bean MC9S12C32_80)\r
+**\r
+** Description :\r
+** Set low power mode - Wait mode. For more information\r
+** about the wait mode see documentation of this CPU.\r
+** Release from Watch mode: Reset or interrupt\r
+** Parameters : None\r
+** Returns : Nothing\r
+** ===================================================================\r
+*/\r
+\r
+\r
+\r
+#define Cpu_DisableInt() __DI() /* Disable interrupts */\r
+/*\r
+** ===================================================================\r
+** Method : Cpu_DisableInt (bean MC9S12C32_80)\r
+**\r
+** Description :\r
+** Disable maskable interrupts\r
+** Parameters : None\r
+** Returns : Nothing\r
+** ===================================================================\r
+*/\r
+\r
+#define Cpu_EnableInt() __EI() /* Enable interrupts */\r
+/*\r
+** ===================================================================\r
+** Method : Cpu_EnableInt (bean MC9S12C32_80)\r
+**\r
+** Description :\r
+** Enable maskable interrupts\r
+** Parameters : None\r
+** Returns : Nothing\r
+** ===================================================================\r
+*/\r
+\r
+#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */\r
+\r
+__interrupt void Cpu_Interrupt(void);\r
+/*\r
+** ===================================================================\r
+** Method : Cpu_Interrupt (bean MC9S12C32_80)\r
+**\r
+** Description :\r
+** This method is internal. It is used by Processor Expert\r
+** only.\r
+** ===================================================================\r
+*/\r
+\r
+#pragma CODE_SEG DEFAULT /* Change code section to DEFAULT. */\r
+\r
+void PE_low_level_init(void);\r
+/*\r
+** ===================================================================\r
+** Method : PE_low_level_init (bean MC9S12C32_80)\r
+**\r
+** Description :\r
+** This method is internal. It is used by Processor Expert\r
+** only.\r
+** ===================================================================\r
+*/\r
+\r
+/* END Cpu. */\r
+\r
+#endif /* ifndef __Cpu */\r
+/*\r
+** ###################################################################\r
+**\r
+** This file was created by UNIS Processor Expert 03.33 for \r
+** the Motorola HCS12 series of microcontrollers.\r
+**\r
+** ###################################################################\r
+*/\r
--- /dev/null
+/** ###################################################################\r
+** Filename : Events.C\r
+** Project : RTOSDemo\r
+** Processor : MC9S12C32CFU\r
+** Beantype : Events\r
+** Version : Driver 01.01\r
+** Compiler : Metrowerks HC12 C Compiler\r
+** Date/Time : 17/05/2005, 08:36\r
+** Abstract :\r
+** This is user's event module.\r
+** Put your event handler code here.\r
+** Settings :\r
+** Contents :\r
+** vTaskTickInterrupt - void vTaskTickInterrupt(void);\r
+**\r
+** (c) Copyright UNIS, spol. s r.o. 1997-2002\r
+** UNIS, spol. s r.o.\r
+** Jundrovska 33\r
+** 624 00 Brno\r
+** Czech Republic\r
+** http : www.processorexpert.com\r
+** mail : info@processorexpert.com\r
+** ###################################################################*/\r
+/* MODULE Events */\r
+\r
+\r
+/*Including used modules for compilling procedure*/\r
+#include "Cpu.h"\r
+#include "Events.h"\r
+#include "Byte1.h"\r
+#include "TickTimer.h"\r
+#include "ButtonInterrupt.h"\r
+\r
+/*Include shared modules, which are used for whole project*/\r
+#include "PE_Types.h"\r
+#include "PE_Error.h"\r
+#include "PE_Const.h"\r
+#include "IO_Map.h"\r
+#include "PE_Timer.h"\r
+\r
+/*\r
+** ===================================================================\r
+** Event : vTaskTickInterrupt (module Events)\r
+**\r
+** From bean : TickTimer [TimerInt]\r
+** Description :\r
+** When a timer interrupt occurs this event is called (only\r
+** when the bean is enabled - "Enable" and the events are\r
+** enabled - "EnableEvent").\r
+** Parameters : None\r
+** Returns : Nothing\r
+** ===================================================================\r
+*/\r
+void vTaskTickInterrupt(void)\r
+{\r
+ /* Write your code here ... */\r
+}\r
+\r
+\r
+/*\r
+** ===================================================================\r
+** Event : ButtonInterrupt_OnInterrupt (module Events)\r
+**\r
+** From bean : ButtonInterrupt [ExtInt]\r
+** Description :\r
+** This event is called when the active signal edge/level\r
+** occurs.\r
+** Parameters : None\r
+** Returns : Nothing\r
+** ===================================================================\r
+*/\r
+void ButtonInterrupt_OnInterrupt(void)\r
+{\r
+ /* place your ButtonInterrupt interrupt procedure body here */\r
+}\r
+\r
+\r
+/* END Events */\r
+\r
+/*\r
+** ###################################################################\r
+**\r
+** This file was created by UNIS Processor Expert 03.33 for \r
+** the Motorola HCS12 series of microcontrollers.\r
+**\r
+** ###################################################################\r
+*/\r
--- /dev/null
+/** ###################################################################\r
+** Filename : Events.H\r
+** Project : RTOSDemo\r
+** Processor : MC9S12C32CFU\r
+** Beantype : Events\r
+** Version : Driver 01.01\r
+** Compiler : Metrowerks HC12 C Compiler\r
+** Date/Time : 17/05/2005, 08:36\r
+** Abstract :\r
+** This is user's event module.\r
+** Put your event handler code here.\r
+** Settings :\r
+** Contents :\r
+** vTaskTickInterrupt - void vTaskTickInterrupt(void);\r
+**\r
+** (c) Copyright UNIS, spol. s r.o. 1997-2002\r
+** UNIS, spol. s r.o.\r
+** Jundrovska 33\r
+** 624 00 Brno\r
+** Czech Republic\r
+** http : www.processorexpert.com\r
+** mail : info@processorexpert.com\r
+** ###################################################################*/\r
+\r
+#ifndef __Events_H\r
+#define __Events_H\r
+/* MODULE Events */\r
+\r
+#include "PE_Types.h"\r
+#include "PE_Error.h"\r
+#include "PE_Const.h"\r
+#include "IO_Map.h"\r
+#include "PE_Timer.h"\r
+\r
+void vTaskTickInterrupt(void);\r
+/*\r
+** ===================================================================\r
+** Event : vTaskTickInterrupt (module Events)\r
+**\r
+** From bean : TickTimer [TimerInt]\r
+** Description :\r
+** When a timer interrupt occurs this event is called (only\r
+** when the bean is enabled - "Enable" and the events are\r
+** enabled - "EnableEvent").\r
+** Parameters : None\r
+** Returns : Nothing\r
+** ===================================================================\r
+*/\r
+\r
+\r
+void ButtonInterrupt_OnInterrupt(void);\r
+/*\r
+** ===================================================================\r
+** Event : ButtonInterrupt_OnInterrupt (module Events)\r
+**\r
+** From bean : ButtonInterrupt [ExtInt]\r
+** Description :\r
+** This event is called when the active signal edge/level\r
+** occurs.\r
+** Parameters : None\r
+** Returns : Nothing\r
+** ===================================================================\r
+*/\r
+/* END Events */\r
+#endif /* __Events_H*/\r
+\r
+/*\r
+** ###################################################################\r
+**\r
+** This file was created by UNIS Processor Expert 03.33 for \r
+** the Motorola HCS12 series of microcontrollers.\r
+**\r
+** ###################################################################\r
+*/\r
--- /dev/null
+/** ###################################################################\r
+** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.\r
+** Filename : IO_Map.C\r
+** Project : RTOSDemo\r
+** Processor : MC9S12C32CFU\r
+** Beantype : IO_Map\r
+** Version : Driver 01.01\r
+** Compiler : Metrowerks HC12 C Compiler\r
+** Date/Time : 10/05/2005, 11:11\r
+** Abstract :\r
+** This bean "IO_Map" implements an IO devices mapping.\r
+** Settings :\r
+**\r
+** Contents :\r
+** No public methods\r
+**\r
+** (c) Copyright UNIS, spol. s r.o. 1997-2002\r
+** UNIS, spol. s r.o.\r
+** Jundrovska 33\r
+** 624 00 Brno\r
+** Czech Republic\r
+** http : www.processorexpert.com\r
+** mail : info@processorexpert.com\r
+** ###################################################################*/\r
+/* Based on CPU DB MC9S12C32_80, version 2.87.264 */\r
+#include "PE_types.h"\r
+#include "IO_Map.h"\r
+\r
+volatile ARMCOPSTR _ARMCOP; /* CRG COP Timer Arm/Reset Register */\r
+volatile ATDDIENSTR _ATDDIEN; /* ATD Input Enable Mask Register */\r
+volatile ATDSTAT0STR _ATDSTAT0; /* A/D Status Register 0 */\r
+volatile ATDSTAT1STR _ATDSTAT1; /* A/D Status Register 1 */\r
+volatile BDMCCRSTR _BDMCCR; /* BDM CCR Holding Register */\r
+volatile BDMINRSTR _BDMINR; /* BDM Internal Register Position Register */\r
+volatile BDMSTSSTR _BDMSTS; /* BDM Status Register */\r
+volatile BKP0HSTR _BKP0H; /* First Address High Byte Breakpoint Register */\r
+volatile BKP0LSTR _BKP0L; /* First Address Low Byte Breakpoint Register */\r
+volatile BKP0XSTR _BKP0X; /* First Address Memory Expansion Breakpoint Register */\r
+volatile BKP1HSTR _BKP1H; /* Data (Second Address) High Byte Breakpoint Register */\r
+volatile BKP1LSTR _BKP1L; /* Data (Second Address) Low Byte Breakpoint Register */\r
+volatile BKP1XSTR _BKP1X; /* Second Address Memory Expansion Breakpoint Register */\r
+volatile BKPCT0STR _BKPCT0; /* Breakpoint Control Register 0 */\r
+volatile BKPCT1STR _BKPCT1; /* Breakpoint Control Register 1 */\r
+volatile CANBTR0STR _CANBTR0; /* MSCAN Bus Timing Register 0 */\r
+volatile CANBTR1STR _CANBTR1; /* MSCAN Bus Timing Register 1 */\r
+volatile CANCTL0STR _CANCTL0; /* MSCAN Control 0 Register */\r
+volatile CANCTL1STR _CANCTL1; /* MSCAN Control 1 Register */\r
+volatile CANIDACSTR _CANIDAC; /* MSCAN Identifier Acceptance Control Register */\r
+volatile CANIDAR0STR _CANIDAR0; /* MSCAN Identifier Acceptance Register 0 */\r
+volatile CANIDAR1STR _CANIDAR1; /* MSCAN Identifier Acceptance Register 1 */\r
+volatile CANIDAR2STR _CANIDAR2; /* MSCAN Identifier Acceptance Register 2 */\r
+volatile CANIDAR3STR _CANIDAR3; /* MSCAN Identifier Acceptance Register 3 */\r
+volatile CANIDAR4STR _CANIDAR4; /* MSCAN Identifier Acceptance Register 4 */\r
+volatile CANIDAR5STR _CANIDAR5; /* MSCAN Identifier Acceptance Register 5 */\r
+volatile CANIDAR6STR _CANIDAR6; /* MSCAN Identifier Acceptance Register 6 */\r
+volatile CANIDAR7STR _CANIDAR7; /* MSCAN Identifier Acceptance Register 7 */\r
+volatile CANIDMR0STR _CANIDMR0; /* MSCAN Identifier Mask Register 0 */\r
+volatile CANIDMR1STR _CANIDMR1; /* MSCAN Identifier Mask Register 1 */\r
+volatile CANIDMR2STR _CANIDMR2; /* MSCAN Identifier Mask Register 2 */\r
+volatile CANIDMR3STR _CANIDMR3; /* MSCAN Identifier Mask Register 3 */\r
+volatile CANIDMR4STR _CANIDMR4; /* MSCAN Identifier Mask Register 4 */\r
+volatile CANIDMR5STR _CANIDMR5; /* MSCAN Identifier Mask Register 5 */\r
+volatile CANIDMR6STR _CANIDMR6; /* MSCAN Identifier Mask Register 6 */\r
+volatile CANIDMR7STR _CANIDMR7; /* MSCAN Identifier Mask Register 7 */\r
+volatile CANRFLGSTR _CANRFLG; /* MSCAN Receiver Flag Register */\r
+volatile CANRIERSTR _CANRIER; /* MSCAN Receiver Interrupt Enable Register */\r
+volatile CANRXDLRSTR _CANRXDLR; /* MSCAN Receive Data Length Register */\r
+volatile CANRXDSR0STR _CANRXDSR0; /* MSCAN Receive Data Segment Register 0 */\r
+volatile CANRXDSR1STR _CANRXDSR1; /* MSCAN Receive Data Segment Register 1 */\r
+volatile CANRXDSR2STR _CANRXDSR2; /* MSCAN Receive Data Segment Register 2 */\r
+volatile CANRXDSR3STR _CANRXDSR3; /* MSCAN Receive Data Segment Register 3 */\r
+volatile CANRXDSR4STR _CANRXDSR4; /* MSCAN Receive Data Segment Register 4 */\r
+volatile CANRXDSR5STR _CANRXDSR5; /* MSCAN Receive Data Segment Register 5 */\r
+volatile CANRXDSR6STR _CANRXDSR6; /* MSCAN Receive Data Segment Register 6 */\r
+volatile CANRXDSR7STR _CANRXDSR7; /* MSCAN Receive Data Segment Register 7 */\r
+volatile CANRXERRSTR _CANRXERR; /* MSCAN Receive Error Counter Register */\r
+volatile CANRXIDR0STR _CANRXIDR0; /* MSCAN Receive Identifier Register 0 */\r
+volatile CANRXIDR1STR _CANRXIDR1; /* MSCAN Receive Identifier Register 1 */\r
+volatile CANRXIDR2STR _CANRXIDR2; /* MSCAN Receive Identifier Register 2 */\r
+volatile CANRXIDR3STR _CANRXIDR3; /* MSCAN Receive Identifier Register 3 */\r
+volatile CANTAAKSTR _CANTAAK; /* MSCAN Transmitter Message Abort Control */\r
+volatile CANTARQSTR _CANTARQ; /* MSCAN Transmitter Message Abort Request */\r
+volatile CANTBSELSTR _CANTBSEL; /* MSCAN Transmit Buffer Selection */\r
+volatile CANTFLGSTR _CANTFLG; /* MSCAN Transmitter Flag Register */\r
+volatile CANTIERSTR _CANTIER; /* MSCAN Transmitter Interrupt Enable Register */\r
+volatile CANTXDLRSTR _CANTXDLR; /* MSCAN Transmit Data Length Register */\r
+volatile CANTXDSR0STR _CANTXDSR0; /* MSCAN Transmit Data Segment Register 0 */\r
+volatile CANTXDSR1STR _CANTXDSR1; /* MSCAN Transmit Data Segment Register 1 */\r
+volatile CANTXDSR2STR _CANTXDSR2; /* MSCAN Transmit Data Segment Register 2 */\r
+volatile CANTXDSR3STR _CANTXDSR3; /* MSCAN Transmit Data Segment Register 3 */\r
+volatile CANTXDSR4STR _CANTXDSR4; /* MSCAN Transmit Data Segment Register 4 */\r
+volatile CANTXDSR5STR _CANTXDSR5; /* MSCAN Transmit Data Segment Register 5 */\r
+volatile CANTXDSR6STR _CANTXDSR6; /* MSCAN Transmit Data Segment Register 6 */\r
+volatile CANTXDSR7STR _CANTXDSR7; /* MSCAN Transmit Data Segment Register 7 */\r
+volatile CANTXERRSTR _CANTXERR; /* MSCAN Transmit Error Counter Register */\r
+volatile CANTXIDR0STR _CANTXIDR0; /* MSCAN Transmit Identifier Register 0 */\r
+volatile CANTXIDR1STR _CANTXIDR1; /* MSCAN Transmit Identifier Register 1 */\r
+volatile CANTXIDR2STR _CANTXIDR2; /* MSCAN Transmit Identifier Register 2 */\r
+volatile CANTXIDR3STR _CANTXIDR3; /* MSCAN Transmit Identifier Register 3 */\r
+volatile CANTXTBPRSTR _CANTXTBPR; /* MSCAN Transmit Buffer Priority */\r
+volatile CFORCSTR _CFORC; /* Timer Compare Force Register */\r
+volatile CLKSELSTR _CLKSEL; /* CRG Clock Select Register */\r
+volatile COPCTLSTR _COPCTL; /* CRG COP Control Register */\r
+volatile CRGFLGSTR _CRGFLG; /* CRG Flags Register */\r
+volatile CRGINTSTR _CRGINT; /* CRG Interrupt Enable Register */\r
+volatile CTCTLSTR _CTCTL; /* CRG Test Control Register */\r
+volatile CTFLGSTR _CTFLG; /* CRG Test Flags Register */\r
+volatile DDRADSTR _DDRAD; /* Port AD Data Direction Register */\r
+volatile DDRESTR _DDRE; /* Port E Data Direction Register */\r
+volatile DDRJSTR _DDRJ; /* Port J Data Direction Register */\r
+volatile DDRKSTR _DDRK; /* Port K Data Direction Register */\r
+volatile DDRMSTR _DDRM; /* Port M Data Direction Register */\r
+volatile DDRPSTR _DDRP; /* Port P Data Direction Register */\r
+volatile DDRSSTR _DDRS; /* Port S Data Direction Register */\r
+volatile DDRTSTR _DDRT; /* Port T Data Direction Register */\r
+volatile EBICTLSTR _EBICTL; /* External Bus Interface Control */\r
+volatile FCLKDIVSTR _FCLKDIV; /* Flash Clock Divider Register */\r
+volatile FCMDSTR _FCMD; /* Flash Command Buffer and Register */\r
+volatile FCNFGSTR _FCNFG; /* Flash Configuration Register */\r
+volatile FPROTSTR _FPROT; /* Flash Protection Register */\r
+volatile FSECSTR _FSEC; /* Flash Security Register */\r
+volatile FSTATSTR _FSTAT; /* Flash Status Register */\r
+volatile HPRIOSTR _HPRIO; /* Highest Priority I Interrupt */\r
+volatile INITEESTR _INITEE; /* Initialization of Internal EEPROM Position Register */\r
+volatile INITRGSTR _INITRG; /* Initialization of Internal Register Position Register */\r
+volatile INITRMSTR _INITRM; /* Initialization of Internal RAM Position Register */\r
+volatile INTCRSTR _INTCR; /* Interrupt Control Register */\r
+volatile ITCRSTR _ITCR; /* Interrupt Test Control Register */\r
+volatile ITESTSTR _ITEST; /* Interrupt Test Register */\r
+volatile MEMSIZ0STR _MEMSIZ0; /* Memory Size Register Zero */\r
+volatile MEMSIZ1STR _MEMSIZ1; /* Memory Size Register One */\r
+volatile MISCSTR _MISC; /* Miscellaneous Mapping Control Register */\r
+volatile MODESTR _MODE; /* Mode Register */\r
+volatile MODRRSTR _MODRR; /* Module Routing Register */\r
+volatile MTST0STR _MTST0; /* MTST0 */\r
+volatile MTST1STR _MTST1; /* MTST1 */\r
+volatile OC7DSTR _OC7D; /* Output Compare 7 Data Register */\r
+volatile OC7MSTR _OC7M; /* Output Compare 7 Mask Register */\r
+volatile PACTLSTR _PACTL; /* 16-Bit Pulse Accumulator A Control Register */\r
+volatile PAFLGSTR _PAFLG; /* Pulse Accumulator A Flag Register */\r
+volatile PARTIDHSTR _PARTIDH; /* Part ID Register High */\r
+volatile PARTIDLSTR _PARTIDL; /* Part ID Register Low */\r
+volatile PEARSTR _PEAR; /* Port E Assignment Register */\r
+volatile PERADSTR _PERAD; /* Port AD Pull Device Enable Register */\r
+volatile PERJSTR _PERJ; /* Port J Pull Device Enable Register */\r
+volatile PERMSTR _PERM; /* Port M Pull Device Enable Register */\r
+volatile PERPSTR _PERP; /* Port P Pull Device Enable Register */\r
+volatile PERSSTR _PERS; /* Port S Pull Device Enable Register */\r
+volatile PERTSTR _PERT; /* Port T Pull Device Enable Register */\r
+volatile PIEJSTR _PIEJ; /* Port J Interrupt Enable Register */\r
+volatile PIEPSTR _PIEP; /* Port P Interrupt Enable Register */\r
+volatile PIFJSTR _PIFJ; /* Port J Interrupt Flag Register */\r
+volatile PIFPSTR _PIFP; /* Port P Interrupt Flag Register */\r
+volatile PLLCTLSTR _PLLCTL; /* CRG PLL Control Register */\r
+volatile PORTAD0STR _PORTAD0; /* Port AD0 Register */\r
+volatile PORTESTR _PORTE; /* Port E Register */\r
+volatile PORTKSTR _PORTK; /* Port K Data Register */\r
+volatile PPAGESTR _PPAGE; /* Page Index Register */\r
+volatile PPSADSTR _PPSAD; /* Port AD Polarity Select Register */\r
+volatile PPSJSTR _PPSJ; /* PortJP Polarity Select Register */\r
+volatile PPSMSTR _PPSM; /* Port M Polarity Select Register */\r
+volatile PPSPSTR _PPSP; /* Port P Polarity Select Register */\r
+volatile PPSSSTR _PPSS; /* Port S Polarity Select Register */\r
+volatile PPSTSTR _PPST; /* Port T Polarity Select Register */\r
+volatile PTADSTR _PTAD; /* Port AD I/O Register */\r
+volatile PTIADSTR _PTIAD; /* Port AD Input Register */\r
+volatile PTIJSTR _PTIJ; /* Port J Input Register */\r
+volatile PTIMSTR _PTIM; /* Port M Input */\r
+volatile PTIPSTR _PTIP; /* Port P Input */\r
+volatile PTISSTR _PTIS; /* Port S Input */\r
+volatile PTITSTR _PTIT; /* Port T Input */\r
+volatile PTJSTR _PTJ; /* Port J I/O Register */\r
+volatile PTMSTR _PTM; /* Port M I/O Register */\r
+volatile PTPSTR _PTP; /* Port P I/O Register */\r
+volatile PTSSTR _PTS; /* Port S I/O Register */\r
+volatile PTTSTR _PTT; /* Port T I/O Register */\r
+volatile PUCRSTR _PUCR; /* Pull-Up Control Register */\r
+volatile PWMCAESTR _PWMCAE; /* PWM Center Align Enable Register */\r
+volatile PWMCLKSTR _PWMCLK; /* PWM Clock Select Register */\r
+volatile PWMCTLSTR _PWMCTL; /* PWM Control Register */\r
+volatile PWMESTR _PWME; /* PWM Enable Register */\r
+volatile PWMPOLSTR _PWMPOL; /* PWM Polarity Register */\r
+volatile PWMPRCLKSTR _PWMPRCLK; /* PWM Prescale Clock Select Register */\r
+volatile PWMSCLASTR _PWMSCLA; /* PWM Scale A Register */\r
+volatile PWMSCLBSTR _PWMSCLB; /* PWM Scale B Register */\r
+volatile PWMSDNSTR _PWMSDN; /* PWM Shutdown Register */\r
+volatile RDRADSTR _RDRAD; /* Port AD Reduced Drive Register */\r
+volatile RDRIVSTR _RDRIV; /* Reduced Drive of I/O Lines */\r
+volatile RDRJSTR _RDRJ; /* Port J Reduced Drive Register */\r
+volatile RDRMSTR _RDRM; /* Port M Reduced Drive Register */\r
+volatile RDRPSTR _RDRP; /* Port P Reduced Drive Register */\r
+volatile RDRSSTR _RDRS; /* Port S Reduced Drive Register */\r
+volatile RDRTSTR _RDRT; /* Port T Reduced Drive Register */\r
+volatile REFDVSTR _REFDV; /* CRG Reference Divider Register */\r
+volatile RTICTLSTR _RTICTL; /* CRG RTI Control Register */\r
+volatile SCICR1STR _SCICR1; /* SCI Control Register 1 */\r
+volatile SCICR2STR _SCICR2; /* SCI Control Register 2 */\r
+volatile SCIDRHSTR _SCIDRH; /* SCI Data Register High */\r
+volatile SCIDRLSTR _SCIDRL; /* SCI Data Register Low */\r
+volatile SCISR1STR _SCISR1; /* SCI Status Register 1 */\r
+volatile SCISR2STR _SCISR2; /* SCI Status Register 2 */\r
+volatile SPIBRSTR _SPIBR; /* SPI Baud Rate Register */\r
+volatile SPICR1STR _SPICR1; /* SPI Control Register */\r
+volatile SPICR2STR _SPICR2; /* SPI Control Register 2 */\r
+volatile SPIDRSTR _SPIDR; /* SPI Data Register */\r
+volatile SPISRSTR _SPISR; /* SPI Status Register */\r
+volatile SYNRSTR _SYNR; /* CRG Synthesizer Register */\r
+volatile TCTL1STR _TCTL1; /* Timer Control Register 1 */\r
+volatile TCTL2STR _TCTL2; /* Timer Control Register 2 */\r
+volatile TCTL3STR _TCTL3; /* Timer Control Register 3 */\r
+volatile TCTL4STR _TCTL4; /* Timer Control Register 4 */\r
+volatile TFLG1STR _TFLG1; /* Main Timer Interrupt Flag 1 */\r
+volatile TFLG2STR _TFLG2; /* Main Timer Interrupt Flag 2 */\r
+volatile TIESTR _TIE; /* Timer Interrupt Enable Register */\r
+volatile TIOSSTR _TIOS; /* Timer Input Capture/Output Compare Select */\r
+volatile TSCR1STR _TSCR1; /* Timer System Control Register1 */\r
+volatile TSCR2STR _TSCR2; /* Timer System Control Register 2 */\r
+volatile TTOVSTR _TTOV; /* Timer Toggle On Overflow Register */\r
+volatile WOMMSTR _WOMM; /* Port M Wired-Or Mode Register */\r
+volatile WOMSSTR _WOMS; /* Port S Wired-Or Mode Register */\r
+volatile ATDCTL23STR _ATDCTL23; /* ATD Control Register 23 */\r
+volatile ATDCTL45STR _ATDCTL45; /* ATD Control Register 45 */\r
+volatile ATDDR0STR _ATDDR0; /* A/D Conversion Result Register 0 */\r
+volatile ATDDR1STR _ATDDR1; /* A/D Conversion Result Register 1 */\r
+volatile ATDDR2STR _ATDDR2; /* A/D Conversion Result Register 2 */\r
+volatile ATDDR3STR _ATDDR3; /* A/D Conversion Result Register 3 */\r
+volatile ATDDR4STR _ATDDR4; /* A/D Conversion Result Register 4 */\r
+volatile ATDDR5STR _ATDDR5; /* A/D Conversion Result Register 5 */\r
+volatile ATDDR6STR _ATDDR6; /* A/D Conversion Result Register 6 */\r
+volatile ATDDR7STR _ATDDR7; /* A/D Conversion Result Register 7 */\r
+volatile DDRABSTR _DDRAB; /* Port AB Data Direction Register */\r
+volatile PACNTSTR _PACNT; /* Pulse Accumulators Count Register */\r
+volatile PORTABSTR _PORTAB; /* Port AB Register */\r
+volatile PWMCNT01STR _PWMCNT01; /* PWM Channel Counter 01 Register */\r
+volatile PWMCNT23STR _PWMCNT23; /* PWM Channel Counter 23 Register */\r
+volatile PWMCNT45STR _PWMCNT45; /* PWM Channel Counter 45 Register */\r
+volatile PWMDTY01STR _PWMDTY01; /* PWM Channel Duty 01 Register */\r
+volatile PWMDTY23STR _PWMDTY23; /* PWM Channel Duty 23 Register */\r
+volatile PWMDTY45STR _PWMDTY45; /* PWM Channel Duty 45 Register */\r
+volatile PWMPER01STR _PWMPER01; /* PWM Channel Period 01 Register */\r
+volatile PWMPER23STR _PWMPER23; /* PWM Channel Period 23 Register */\r
+volatile PWMPER45STR _PWMPER45; /* PWM Channel Period 45 Register */\r
+volatile SCIBDSTR _SCIBD; /* SCI Baud Rate Register */\r
+volatile TC0STR _TC0; /* Timer Input Capture/Output Compare Register 0 */\r
+volatile TC1STR _TC1; /* Timer Input Capture/Output Compare Register 1 */\r
+volatile TC2STR _TC2; /* Timer Input Capture/Output Compare Register 2 */\r
+volatile TC3STR _TC3; /* Timer Input Capture/Output Compare Register 3 */\r
+volatile TC4STR _TC4; /* Timer Input Capture/Output Compare Register 4 */\r
+volatile TC5STR _TC5; /* Timer Input Capture/Output Compare Register 5 */\r
+volatile TC6STR _TC6; /* Timer Input Capture/Output Compare Register 6 */\r
+volatile TC7STR _TC7; /* Timer Input Capture/Output Compare Register 7 */\r
+volatile TCNTSTR _TCNT; /* Timer Count Register */\r
+/*\r
+** ###################################################################\r
+**\r
+** This file was created by UNIS Processor Expert 03.33 for \r
+** the Motorola HCS12 series of microcontrollers.\r
+**\r
+** ###################################################################\r
+*/\r
--- /dev/null
+/** ###################################################################\r
+** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.\r
+** Filename : IO_Map.H\r
+** Project : RTOSDemo\r
+** Processor : MC9S12C32CFU\r
+** Beantype : IO_Map\r
+** Version : Driver 01.01\r
+** Compiler : Metrowerks HC12 C Compiler\r
+** Date/Time : 10/05/2005, 11:11\r
+** Abstract :\r
+** This bean "IO_Map" implements an IO devices mapping.\r
+** Settings :\r
+**\r
+** Contents :\r
+** No public methods\r
+**\r
+** (c) Copyright UNIS, spol. s r.o. 1997-2002\r
+** UNIS, spol. s r.o.\r
+** Jundrovska 33\r
+** 624 00 Brno\r
+** Czech Republic\r
+** http : www.processorexpert.com\r
+** mail : info@processorexpert.com\r
+** ###################################################################*/\r
+\r
+/* Linker pragmas */\r
+#pragma LINK_INFO DERIVATIVE "MC9S12C32"\r
+#pragma LINK_INFO OSCFREQUENCY "16000000"\r
+\r
+\r
+#define REG_BASE 0x0000 /* Base address for the I/O register block */\r
+\r
+/* Based on CPU DB MC9S12C32_80, version 2.87.264 (RegistersPrg V1.027) */\r
+#ifndef _MC9S12C32_80_H\r
+#define _MC9S12C32_80_H\r
+\r
+#include "PE_Types.h"\r
+\r
+#pragma MESSAGE DISABLE C1106 /* WARNING C1106: Non-standard bitfield type */\r
+\r
+/*********************************************/\r
+/* */\r
+/* PE I/O map format */\r
+/* */\r
+/*********************************************/\r
+\r
+/*** PORTAB - Port AB Register; 0x00000000 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** PORTA - Port A Register; 0x00000000 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* Port A Bit 0 */\r
+ byte BIT1 :1; /* Port A Bit 1 */\r
+ byte BIT2 :1; /* Port A Bit 2 */\r
+ byte BIT3 :1; /* Port A Bit 3 */\r
+ byte BIT4 :1; /* Port A Bit 4 */\r
+ byte BIT5 :1; /* Port A Bit 5 */\r
+ byte BIT6 :1; /* Port A Bit 6 */\r
+ byte BIT7 :1; /* Port A Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } PORTASTR;\r
+ #define PORTA _PORTAB.Overlap_STR.PORTASTR.Byte\r
+ #define PORTA_BIT0 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT0\r
+ #define PORTA_BIT1 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT1\r
+ #define PORTA_BIT2 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT2\r
+ #define PORTA_BIT3 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT3\r
+ #define PORTA_BIT4 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT4\r
+ #define PORTA_BIT5 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT5\r
+ #define PORTA_BIT6 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT6\r
+ #define PORTA_BIT7 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT7\r
+ #define PORTA_BIT _PORTAB.Overlap_STR.PORTASTR.MergedBits.grpBIT\r
+ \r
+ /*** PORTB - Port B Register; 0x00000001 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* Port B Bit 0 */\r
+ byte BIT1 :1; /* Port B Bit 1 */\r
+ byte BIT2 :1; /* Port B Bit 2 */\r
+ byte BIT3 :1; /* Port B Bit 3 */\r
+ byte BIT4 :1; /* Port B Bit 4 */\r
+ byte BIT5 :1; /* Port B Bit 5 */\r
+ byte BIT6 :1; /* Port B Bit 6 */\r
+ byte BIT7 :1; /* Port B Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } PORTBSTR;\r
+ #define PORTB _PORTAB.Overlap_STR.PORTBSTR.Byte\r
+ #define PORTB_BIT0 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT0\r
+ #define PORTB_BIT1 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT1\r
+ #define PORTB_BIT2 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT2\r
+ #define PORTB_BIT3 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT3\r
+ #define PORTB_BIT4 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT4\r
+ #define PORTB_BIT5 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT5\r
+ #define PORTB_BIT6 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT6\r
+ #define PORTB_BIT7 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT7\r
+ #define PORTB_BIT _PORTAB.Overlap_STR.PORTBSTR.MergedBits.grpBIT\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word BIT0 :1; /* Port AB Bit 0 */\r
+ word BIT1 :1; /* Port AB Bit 1 */\r
+ word BIT2 :1; /* Port AB Bit 2 */\r
+ word BIT3 :1; /* Port AB Bit 3 */\r
+ word BIT4 :1; /* Port AB Bit 4 */\r
+ word BIT5 :1; /* Port AB Bit 5 */\r
+ word BIT6 :1; /* Port AB Bit 6 */\r
+ word BIT7 :1; /* Port AB Bit 7 */\r
+ word BIT8 :1; /* Port AB Bit 8 */\r
+ word BIT9 :1; /* Port AB Bit 9 */\r
+ word BIT10 :1; /* Port AB Bit 10 */\r
+ word BIT11 :1; /* Port AB Bit 11 */\r
+ word BIT12 :1; /* Port AB Bit 12 */\r
+ word BIT13 :1; /* Port AB Bit 13 */\r
+ word BIT14 :1; /* Port AB Bit 14 */\r
+ word BIT15 :1; /* Port AB Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ word grpBIT :16;\r
+ } MergedBits;\r
+} PORTABSTR;\r
+extern volatile PORTABSTR _PORTAB @(REG_BASE + 0x00000000);\r
+#define PORTAB _PORTAB.Word\r
+#define PORTAB_BIT0 _PORTAB.Bits.BIT0\r
+#define PORTAB_BIT1 _PORTAB.Bits.BIT1\r
+#define PORTAB_BIT2 _PORTAB.Bits.BIT2\r
+#define PORTAB_BIT3 _PORTAB.Bits.BIT3\r
+#define PORTAB_BIT4 _PORTAB.Bits.BIT4\r
+#define PORTAB_BIT5 _PORTAB.Bits.BIT5\r
+#define PORTAB_BIT6 _PORTAB.Bits.BIT6\r
+#define PORTAB_BIT7 _PORTAB.Bits.BIT7\r
+#define PORTAB_BIT8 _PORTAB.Bits.BIT8\r
+#define PORTAB_BIT9 _PORTAB.Bits.BIT9\r
+#define PORTAB_BIT10 _PORTAB.Bits.BIT10\r
+#define PORTAB_BIT11 _PORTAB.Bits.BIT11\r
+#define PORTAB_BIT12 _PORTAB.Bits.BIT12\r
+#define PORTAB_BIT13 _PORTAB.Bits.BIT13\r
+#define PORTAB_BIT14 _PORTAB.Bits.BIT14\r
+#define PORTAB_BIT15 _PORTAB.Bits.BIT15\r
+#define PORTAB_BIT _PORTAB.MergedBits.grpBIT\r
+\r
+\r
+/*** DDRAB - Port AB Data Direction Register; 0x00000002 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** DDRA - Port A Data Direction Register; 0x00000002 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* Data Direction Port A Bit 0 */\r
+ byte BIT1 :1; /* Data Direction Port A Bit 1 */\r
+ byte BIT2 :1; /* Data Direction Port A Bit 2 */\r
+ byte BIT3 :1; /* Data Direction Port A Bit 3 */\r
+ byte BIT4 :1; /* Data Direction Port A Bit 4 */\r
+ byte BIT5 :1; /* Data Direction Port A Bit 5 */\r
+ byte BIT6 :1; /* Data Direction Port A Bit 6 */\r
+ byte BIT7 :1; /* Data Direction Port A Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } DDRASTR;\r
+ #define DDRA _DDRAB.Overlap_STR.DDRASTR.Byte\r
+ #define DDRA_BIT0 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT0\r
+ #define DDRA_BIT1 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT1\r
+ #define DDRA_BIT2 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT2\r
+ #define DDRA_BIT3 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT3\r
+ #define DDRA_BIT4 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT4\r
+ #define DDRA_BIT5 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT5\r
+ #define DDRA_BIT6 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT6\r
+ #define DDRA_BIT7 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT7\r
+ #define DDRA_BIT _DDRAB.Overlap_STR.DDRASTR.MergedBits.grpBIT\r
+ \r
+ /*** DDRB - Port B Data Direction Register; 0x00000003 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* Data Direction Port B Bit 0 */\r
+ byte BIT1 :1; /* Data Direction Port B Bit 1 */\r
+ byte BIT2 :1; /* Data Direction Port B Bit 2 */\r
+ byte BIT3 :1; /* Data Direction Port B Bit 3 */\r
+ byte BIT4 :1; /* Data Direction Port B Bit 4 */\r
+ byte BIT5 :1; /* Data Direction Port B Bit 5 */\r
+ byte BIT6 :1; /* Data Direction Port B Bit 6 */\r
+ byte BIT7 :1; /* Data Direction Port B Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } DDRBSTR;\r
+ #define DDRB _DDRAB.Overlap_STR.DDRBSTR.Byte\r
+ #define DDRB_BIT0 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT0\r
+ #define DDRB_BIT1 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT1\r
+ #define DDRB_BIT2 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT2\r
+ #define DDRB_BIT3 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT3\r
+ #define DDRB_BIT4 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT4\r
+ #define DDRB_BIT5 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT5\r
+ #define DDRB_BIT6 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT6\r
+ #define DDRB_BIT7 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT7\r
+ #define DDRB_BIT _DDRAB.Overlap_STR.DDRBSTR.MergedBits.grpBIT\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word BIT0 :1; /* Data Direction Port B Bit 0 */\r
+ word BIT1 :1; /* Data Direction Port B Bit 1 */\r
+ word BIT2 :1; /* Data Direction Port B Bit 2 */\r
+ word BIT3 :1; /* Data Direction Port B Bit 3 */\r
+ word BIT4 :1; /* Data Direction Port B Bit 4 */\r
+ word BIT5 :1; /* Data Direction Port B Bit 5 */\r
+ word BIT6 :1; /* Data Direction Port B Bit 6 */\r
+ word BIT7 :1; /* Data Direction Port B Bit 7 */\r
+ word BIT8 :1; /* Data Direction Port A Bit 8 */\r
+ word BIT9 :1; /* Data Direction Port A Bit 9 */\r
+ word BIT10 :1; /* Data Direction Port A Bit 10 */\r
+ word BIT11 :1; /* Data Direction Port A Bit 11 */\r
+ word BIT12 :1; /* Data Direction Port A Bit 12 */\r
+ word BIT13 :1; /* Data Direction Port A Bit 13 */\r
+ word BIT14 :1; /* Data Direction Port A Bit 14 */\r
+ word BIT15 :1; /* Data Direction Port A Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ word grpBIT :16;\r
+ } MergedBits;\r
+} DDRABSTR;\r
+extern volatile DDRABSTR _DDRAB @(REG_BASE + 0x00000002);\r
+#define DDRAB _DDRAB.Word\r
+#define DDRAB_BIT0 _DDRAB.Bits.BIT0\r
+#define DDRAB_BIT1 _DDRAB.Bits.BIT1\r
+#define DDRAB_BIT2 _DDRAB.Bits.BIT2\r
+#define DDRAB_BIT3 _DDRAB.Bits.BIT3\r
+#define DDRAB_BIT4 _DDRAB.Bits.BIT4\r
+#define DDRAB_BIT5 _DDRAB.Bits.BIT5\r
+#define DDRAB_BIT6 _DDRAB.Bits.BIT6\r
+#define DDRAB_BIT7 _DDRAB.Bits.BIT7\r
+#define DDRAB_BIT8 _DDRAB.Bits.BIT8\r
+#define DDRAB_BIT9 _DDRAB.Bits.BIT9\r
+#define DDRAB_BIT10 _DDRAB.Bits.BIT10\r
+#define DDRAB_BIT11 _DDRAB.Bits.BIT11\r
+#define DDRAB_BIT12 _DDRAB.Bits.BIT12\r
+#define DDRAB_BIT13 _DDRAB.Bits.BIT13\r
+#define DDRAB_BIT14 _DDRAB.Bits.BIT14\r
+#define DDRAB_BIT15 _DDRAB.Bits.BIT15\r
+#define DDRAB_BIT _DDRAB.MergedBits.grpBIT\r
+\r
+\r
+/*** TCNT - Timer Count Register; 0x00000044 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** TCNTHi - Timer Count Register High; 0x00000044 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT15 :1; /* Timer Count Register Bit 15 */\r
+ byte BIT14 :1; /* Timer Count Register Bit 14 */\r
+ byte BIT13 :1; /* Timer Count Register Bit 13 */\r
+ byte BIT12 :1; /* Timer Count Register Bit 12 */\r
+ byte BIT11 :1; /* Timer Count Register Bit 11 */\r
+ byte BIT10 :1; /* Timer Count Register Bit 10 */\r
+ byte BIT9 :1; /* Timer Count Register Bit 9 */\r
+ byte BIT8 :1; /* Timer Count Register Bit 8 */\r
+ } Bits;\r
+ } TCNTHiSTR;\r
+ #define TCNTHi _TCNT.Overlap_STR.TCNTHiSTR.Byte\r
+ #define TCNTHi_BIT15 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT15\r
+ #define TCNTHi_BIT14 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT14\r
+ #define TCNTHi_BIT13 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT13\r
+ #define TCNTHi_BIT12 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT12\r
+ #define TCNTHi_BIT11 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT11\r
+ #define TCNTHi_BIT10 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT10\r
+ #define TCNTHi_BIT9 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT9\r
+ #define TCNTHi_BIT8 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT8\r
+ \r
+ /*** TCNTLo - Timer Count Register Low; 0x00000045 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* Timer Count Register Bit 0 */\r
+ byte BIT1 :1; /* Timer Count Register Bit 1 */\r
+ byte BIT2 :1; /* Timer Count Register Bit 2 */\r
+ byte BIT3 :1; /* Timer Count Register Bit 3 */\r
+ byte BIT4 :1; /* Timer Count Bit Register 4 */\r
+ byte BIT5 :1; /* Timer Count Bit Register 5 */\r
+ byte BIT6 :1; /* Timer Count Bit Register 6 */\r
+ byte BIT7 :1; /* Timer Count Bit Register 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } TCNTLoSTR;\r
+ #define TCNTLo _TCNT.Overlap_STR.TCNTLoSTR.Byte\r
+ #define TCNTLo_BIT0 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT0\r
+ #define TCNTLo_BIT1 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT1\r
+ #define TCNTLo_BIT2 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT2\r
+ #define TCNTLo_BIT3 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT3\r
+ #define TCNTLo_BIT4 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT4\r
+ #define TCNTLo_BIT5 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT5\r
+ #define TCNTLo_BIT6 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT6\r
+ #define TCNTLo_BIT7 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT7\r
+ #define TCNTLo_BIT _TCNT.Overlap_STR.TCNTLoSTR.MergedBits.grpBIT\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word grpBIT :16;\r
+ } MergedBits;\r
+} TCNTSTR;\r
+extern volatile TCNTSTR _TCNT @(REG_BASE + 0x00000044);\r
+#define TCNT _TCNT.Word\r
+#define TCNT_BIT _TCNT.MergedBits.grpBIT\r
+\r
+\r
+/*** TC0 - Timer Input Capture/Output Compare Register 0; 0x00000050 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** TC0Hi - Timer Input Capture/Output Compare Register 0 High; 0x00000050 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT8 :1; /* Timer Input Capture/Output Compare Register 0 Bit 8 */\r
+ byte BIT9 :1; /* Timer Input Capture/Output Compare Register 0 Bit 9 */\r
+ byte BIT10 :1; /* Timer Input Capture/Output Compare Register 0 Bit 10 */\r
+ byte BIT11 :1; /* Timer Input Capture/Output Compare Register 0 Bit 11 */\r
+ byte BIT12 :1; /* Timer Input Capture/Output Compare Register 0 Bit 12 */\r
+ byte BIT13 :1; /* Timer Input Capture/Output Compare Register 0 Bit 13 */\r
+ byte BIT14 :1; /* Timer Input Capture/Output Compare Register 0 Bit 14 */\r
+ byte BIT15 :1; /* Timer Input Capture/Output Compare Register 0 Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT_8 :8;\r
+ } MergedBits;\r
+ } TC0HiSTR;\r
+ #define TC0Hi _TC0.Overlap_STR.TC0HiSTR.Byte\r
+ #define TC0Hi_BIT8 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT8\r
+ #define TC0Hi_BIT9 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT9\r
+ #define TC0Hi_BIT10 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT10\r
+ #define TC0Hi_BIT11 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT11\r
+ #define TC0Hi_BIT12 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT12\r
+ #define TC0Hi_BIT13 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT13\r
+ #define TC0Hi_BIT14 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT14\r
+ #define TC0Hi_BIT15 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT15\r
+ #define TC0Hi_BIT_8 _TC0.Overlap_STR.TC0HiSTR.MergedBits.grpBIT_8\r
+ #define TC0Hi_BIT TC0Hi_BIT_8\r
+ \r
+ /*** TC0Lo - Timer Input Capture/Output Compare Register 0 Low; 0x00000051 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* Timer Input Capture/Output Compare Register 0 Bit 0 */\r
+ byte BIT1 :1; /* Timer Input Capture/Output Compare Register 0 Bit 1 */\r
+ byte BIT2 :1; /* Timer Input Capture/Output Compare Register 0 Bit 2 */\r
+ byte BIT3 :1; /* Timer Input Capture/Output Compare Register 0 Bit 3 */\r
+ byte BIT4 :1; /* Timer Input Capture/Output Compare Register 0 Bit 4 */\r
+ byte BIT5 :1; /* Timer Input Capture/Output Compare Register 0 Bit 5 */\r
+ byte BIT6 :1; /* Timer Input Capture/Output Compare Register 0 Bit 6 */\r
+ byte BIT7 :1; /* Timer Input Capture/Output Compare Register 0 Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } TC0LoSTR;\r
+ #define TC0Lo _TC0.Overlap_STR.TC0LoSTR.Byte\r
+ #define TC0Lo_BIT0 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT0\r
+ #define TC0Lo_BIT1 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT1\r
+ #define TC0Lo_BIT2 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT2\r
+ #define TC0Lo_BIT3 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT3\r
+ #define TC0Lo_BIT4 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT4\r
+ #define TC0Lo_BIT5 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT5\r
+ #define TC0Lo_BIT6 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT6\r
+ #define TC0Lo_BIT7 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT7\r
+ #define TC0Lo_BIT _TC0.Overlap_STR.TC0LoSTR.MergedBits.grpBIT\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word grpBIT :16;\r
+ } MergedBits;\r
+} TC0STR;\r
+extern volatile TC0STR _TC0 @(REG_BASE + 0x00000050);\r
+#define TC0 _TC0.Word\r
+#define TC0_BIT _TC0.MergedBits.grpBIT\r
+\r
+\r
+/*** TC1 - Timer Input Capture/Output Compare Register 1; 0x00000052 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** TC1Hi - Timer Input Capture/Output Compare Register 1 High; 0x00000052 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT8 :1; /* Timer Input Capture/Output Compare Register 1 Bit 8 */\r
+ byte BIT9 :1; /* Timer Input Capture/Output Compare Register 1 Bit 9 */\r
+ byte BIT10 :1; /* Timer Input Capture/Output Compare Register 1 Bit 10 */\r
+ byte BIT11 :1; /* Timer Input Capture/Output Compare Register 1 Bit 11 */\r
+ byte BIT12 :1; /* Timer Input Capture/Output Compare Register 1 Bit 12 */\r
+ byte BIT13 :1; /* Timer Input Capture/Output Compare Register 1 Bit 13 */\r
+ byte BIT14 :1; /* Timer Input Capture/Output Compare Register 1 Bit 14 */\r
+ byte BIT15 :1; /* Timer Input Capture/Output Compare Register 1 Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT_8 :8;\r
+ } MergedBits;\r
+ } TC1HiSTR;\r
+ #define TC1Hi _TC1.Overlap_STR.TC1HiSTR.Byte\r
+ #define TC1Hi_BIT8 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT8\r
+ #define TC1Hi_BIT9 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT9\r
+ #define TC1Hi_BIT10 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT10\r
+ #define TC1Hi_BIT11 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT11\r
+ #define TC1Hi_BIT12 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT12\r
+ #define TC1Hi_BIT13 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT13\r
+ #define TC1Hi_BIT14 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT14\r
+ #define TC1Hi_BIT15 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT15\r
+ #define TC1Hi_BIT_8 _TC1.Overlap_STR.TC1HiSTR.MergedBits.grpBIT_8\r
+ #define TC1Hi_BIT TC1Hi_BIT_8\r
+ \r
+ /*** TC1Lo - Timer Input Capture/Output Compare Register 1 Low; 0x00000053 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* Timer Input Capture/Output Compare Register 1 Bit 0 */\r
+ byte BIT1 :1; /* Timer Input Capture/Output Compare Register 1 Bit 1 */\r
+ byte BIT2 :1; /* Timer Input Capture/Output Compare Register 1 Bit 2 */\r
+ byte BIT3 :1; /* Timer Input Capture/Output Compare Register 1 Bit 3 */\r
+ byte BIT4 :1; /* Timer Input Capture/Output Compare Register 1 Bit 4 */\r
+ byte BIT5 :1; /* Timer Input Capture/Output Compare Register 1 Bit 5 */\r
+ byte BIT6 :1; /* Timer Input Capture/Output Compare Register 1 Bit 6 */\r
+ byte BIT7 :1; /* Timer Input Capture/Output Compare Register 1 Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } TC1LoSTR;\r
+ #define TC1Lo _TC1.Overlap_STR.TC1LoSTR.Byte\r
+ #define TC1Lo_BIT0 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT0\r
+ #define TC1Lo_BIT1 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT1\r
+ #define TC1Lo_BIT2 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT2\r
+ #define TC1Lo_BIT3 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT3\r
+ #define TC1Lo_BIT4 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT4\r
+ #define TC1Lo_BIT5 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT5\r
+ #define TC1Lo_BIT6 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT6\r
+ #define TC1Lo_BIT7 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT7\r
+ #define TC1Lo_BIT _TC1.Overlap_STR.TC1LoSTR.MergedBits.grpBIT\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word grpBIT :16;\r
+ } MergedBits;\r
+} TC1STR;\r
+extern volatile TC1STR _TC1 @(REG_BASE + 0x00000052);\r
+#define TC1 _TC1.Word\r
+#define TC1_BIT _TC1.MergedBits.grpBIT\r
+\r
+\r
+/*** TC2 - Timer Input Capture/Output Compare Register 2; 0x00000054 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** TC2Hi - Timer Input Capture/Output Compare Register 2 High; 0x00000054 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT8 :1; /* Timer Input Capture/Output Compare Register 2 Bit 8 */\r
+ byte BIT9 :1; /* Timer Input Capture/Output Compare Register 2 Bit 9 */\r
+ byte BIT10 :1; /* Timer Input Capture/Output Compare Register 2 Bit 10 */\r
+ byte BIT11 :1; /* Timer Input Capture/Output Compare Register 2 Bit 11 */\r
+ byte BIT12 :1; /* Timer Input Capture/Output Compare Register 2 Bit 12 */\r
+ byte BIT13 :1; /* Timer Input Capture/Output Compare Register 2 Bit 13 */\r
+ byte BIT14 :1; /* Timer Input Capture/Output Compare Register 2 Bit 14 */\r
+ byte BIT15 :1; /* Timer Input Capture/Output Compare Register 2 Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT_8 :8;\r
+ } MergedBits;\r
+ } TC2HiSTR;\r
+ #define TC2Hi _TC2.Overlap_STR.TC2HiSTR.Byte\r
+ #define TC2Hi_BIT8 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT8\r
+ #define TC2Hi_BIT9 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT9\r
+ #define TC2Hi_BIT10 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT10\r
+ #define TC2Hi_BIT11 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT11\r
+ #define TC2Hi_BIT12 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT12\r
+ #define TC2Hi_BIT13 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT13\r
+ #define TC2Hi_BIT14 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT14\r
+ #define TC2Hi_BIT15 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT15\r
+ #define TC2Hi_BIT_8 _TC2.Overlap_STR.TC2HiSTR.MergedBits.grpBIT_8\r
+ #define TC2Hi_BIT TC2Hi_BIT_8\r
+ \r
+ /*** TC2Lo - Timer Input Capture/Output Compare Register 2 Low; 0x00000055 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* Timer Input Capture/Output Compare Register 2 Bit 0 */\r
+ byte BIT1 :1; /* Timer Input Capture/Output Compare Register 2 Bit 1 */\r
+ byte BIT2 :1; /* Timer Input Capture/Output Compare Register 2 Bit 2 */\r
+ byte BIT3 :1; /* Timer Input Capture/Output Compare Register 2 Bit 3 */\r
+ byte BIT4 :1; /* Timer Input Capture/Output Compare Register 2 Bit 4 */\r
+ byte BIT5 :1; /* Timer Input Capture/Output Compare Register 2 Bit 5 */\r
+ byte BIT6 :1; /* Timer Input Capture/Output Compare Register 2 Bit 6 */\r
+ byte BIT7 :1; /* Timer Input Capture/Output Compare Register 2 Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } TC2LoSTR;\r
+ #define TC2Lo _TC2.Overlap_STR.TC2LoSTR.Byte\r
+ #define TC2Lo_BIT0 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT0\r
+ #define TC2Lo_BIT1 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT1\r
+ #define TC2Lo_BIT2 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT2\r
+ #define TC2Lo_BIT3 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT3\r
+ #define TC2Lo_BIT4 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT4\r
+ #define TC2Lo_BIT5 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT5\r
+ #define TC2Lo_BIT6 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT6\r
+ #define TC2Lo_BIT7 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT7\r
+ #define TC2Lo_BIT _TC2.Overlap_STR.TC2LoSTR.MergedBits.grpBIT\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word grpBIT :16;\r
+ } MergedBits;\r
+} TC2STR;\r
+extern volatile TC2STR _TC2 @(REG_BASE + 0x00000054);\r
+#define TC2 _TC2.Word\r
+#define TC2_BIT _TC2.MergedBits.grpBIT\r
+\r
+\r
+/*** TC3 - Timer Input Capture/Output Compare Register 3; 0x00000056 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** TC3Hi - Timer Input Capture/Output Compare Register 3 High; 0x00000056 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT8 :1; /* Timer Input Capture/Output Compare Register 3 Bit 8 */\r
+ byte BIT9 :1; /* Timer Input Capture/Output Compare Register 3 Bit 9 */\r
+ byte BIT10 :1; /* Timer Input Capture/Output Compare Register 3 Bit 10 */\r
+ byte BIT11 :1; /* Timer Input Capture/Output Compare Register 3 Bit 11 */\r
+ byte BIT12 :1; /* Timer Input Capture/Output Compare Register 3 Bit 12 */\r
+ byte BIT13 :1; /* Timer Input Capture/Output Compare Register 3 Bit 13 */\r
+ byte BIT14 :1; /* Timer Input Capture/Output Compare Register 3 Bit 14 */\r
+ byte BIT15 :1; /* Timer Input Capture/Output Compare Register 3 Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT_8 :8;\r
+ } MergedBits;\r
+ } TC3HiSTR;\r
+ #define TC3Hi _TC3.Overlap_STR.TC3HiSTR.Byte\r
+ #define TC3Hi_BIT8 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT8\r
+ #define TC3Hi_BIT9 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT9\r
+ #define TC3Hi_BIT10 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT10\r
+ #define TC3Hi_BIT11 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT11\r
+ #define TC3Hi_BIT12 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT12\r
+ #define TC3Hi_BIT13 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT13\r
+ #define TC3Hi_BIT14 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT14\r
+ #define TC3Hi_BIT15 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT15\r
+ #define TC3Hi_BIT_8 _TC3.Overlap_STR.TC3HiSTR.MergedBits.grpBIT_8\r
+ #define TC3Hi_BIT TC3Hi_BIT_8\r
+ \r
+ /*** TC3Lo - Timer Input Capture/Output Compare Register 3 Low; 0x00000057 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* Timer Input Capture/Output Compare Register 3 Bit 0 */\r
+ byte BIT1 :1; /* Timer Input Capture/Output Compare Register 3 Bit 1 */\r
+ byte BIT2 :1; /* Timer Input Capture/Output Compare Register 3 Bit 2 */\r
+ byte BIT3 :1; /* Timer Input Capture/Output Compare Register 3 Bit 3 */\r
+ byte BIT4 :1; /* Timer Input Capture/Output Compare Register 3 Bit 4 */\r
+ byte BIT5 :1; /* Timer Input Capture/Output Compare Register 3 Bit 5 */\r
+ byte BIT6 :1; /* Timer Input Capture/Output Compare Register 3 Bit 6 */\r
+ byte BIT7 :1; /* Timer Input Capture/Output Compare Register 3 Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } TC3LoSTR;\r
+ #define TC3Lo _TC3.Overlap_STR.TC3LoSTR.Byte\r
+ #define TC3Lo_BIT0 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT0\r
+ #define TC3Lo_BIT1 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT1\r
+ #define TC3Lo_BIT2 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT2\r
+ #define TC3Lo_BIT3 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT3\r
+ #define TC3Lo_BIT4 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT4\r
+ #define TC3Lo_BIT5 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT5\r
+ #define TC3Lo_BIT6 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT6\r
+ #define TC3Lo_BIT7 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT7\r
+ #define TC3Lo_BIT _TC3.Overlap_STR.TC3LoSTR.MergedBits.grpBIT\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word grpBIT :16;\r
+ } MergedBits;\r
+} TC3STR;\r
+extern volatile TC3STR _TC3 @(REG_BASE + 0x00000056);\r
+#define TC3 _TC3.Word\r
+#define TC3_BIT _TC3.MergedBits.grpBIT\r
+\r
+\r
+/*** TC4 - Timer Input Capture/Output Compare Register 4; 0x00000058 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** TC4Hi - Timer Input Capture/Output Compare Register 4 High; 0x00000058 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT8 :1; /* Timer Input Capture/Output Compare Register 4 Bit 8 */\r
+ byte BIT9 :1; /* Timer Input Capture/Output Compare Register 4 Bit 9 */\r
+ byte BIT10 :1; /* Timer Input Capture/Output Compare Register 4 Bit 10 */\r
+ byte BIT11 :1; /* Timer Input Capture/Output Compare Register 4 Bit 11 */\r
+ byte BIT12 :1; /* Timer Input Capture/Output Compare Register 4 Bit 12 */\r
+ byte BIT13 :1; /* Timer Input Capture/Output Compare Register 4 Bit 13 */\r
+ byte BIT14 :1; /* Timer Input Capture/Output Compare Register 4 Bit 14 */\r
+ byte BIT15 :1; /* Timer Input Capture/Output Compare Register 4 Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT_8 :8;\r
+ } MergedBits;\r
+ } TC4HiSTR;\r
+ #define TC4Hi _TC4.Overlap_STR.TC4HiSTR.Byte\r
+ #define TC4Hi_BIT8 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT8\r
+ #define TC4Hi_BIT9 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT9\r
+ #define TC4Hi_BIT10 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT10\r
+ #define TC4Hi_BIT11 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT11\r
+ #define TC4Hi_BIT12 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT12\r
+ #define TC4Hi_BIT13 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT13\r
+ #define TC4Hi_BIT14 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT14\r
+ #define TC4Hi_BIT15 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT15\r
+ #define TC4Hi_BIT_8 _TC4.Overlap_STR.TC4HiSTR.MergedBits.grpBIT_8\r
+ #define TC4Hi_BIT TC4Hi_BIT_8\r
+ \r
+ /*** TC4Lo - Timer Input Capture/Output Compare Register 4 Low; 0x00000059 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* Timer Input Capture/Output Compare Register 4 Bit 0 */\r
+ byte BIT1 :1; /* Timer Input Capture/Output Compare Register 4 Bit 1 */\r
+ byte BIT2 :1; /* Timer Input Capture/Output Compare Register 4 Bit 2 */\r
+ byte BIT3 :1; /* Timer Input Capture/Output Compare Register 4 Bit 3 */\r
+ byte BIT4 :1; /* Timer Input Capture/Output Compare Register 4 Bit 4 */\r
+ byte BIT5 :1; /* Timer Input Capture/Output Compare Register 4 Bit 5 */\r
+ byte BIT6 :1; /* Timer Input Capture/Output Compare Register 4 Bit 6 */\r
+ byte BIT7 :1; /* Timer Input Capture/Output Compare Register 4 Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } TC4LoSTR;\r
+ #define TC4Lo _TC4.Overlap_STR.TC4LoSTR.Byte\r
+ #define TC4Lo_BIT0 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT0\r
+ #define TC4Lo_BIT1 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT1\r
+ #define TC4Lo_BIT2 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT2\r
+ #define TC4Lo_BIT3 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT3\r
+ #define TC4Lo_BIT4 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT4\r
+ #define TC4Lo_BIT5 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT5\r
+ #define TC4Lo_BIT6 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT6\r
+ #define TC4Lo_BIT7 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT7\r
+ #define TC4Lo_BIT _TC4.Overlap_STR.TC4LoSTR.MergedBits.grpBIT\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word grpBIT :16;\r
+ } MergedBits;\r
+} TC4STR;\r
+extern volatile TC4STR _TC4 @(REG_BASE + 0x00000058);\r
+#define TC4 _TC4.Word\r
+#define TC4_BIT _TC4.MergedBits.grpBIT\r
+\r
+\r
+/*** TC5 - Timer Input Capture/Output Compare Register 5; 0x0000005A ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** TC5Hi - Timer Input Capture/Output Compare Register 5 High; 0x0000005A ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT8 :1; /* Timer Input Capture/Output Compare Register 5 Bit 8 */\r
+ byte BIT9 :1; /* Timer Input Capture/Output Compare Register 5 Bit 9 */\r
+ byte BIT10 :1; /* Timer Input Capture/Output Compare Register 5 Bit 10 */\r
+ byte BIT11 :1; /* Timer Input Capture/Output Compare Register 5 Bit 11 */\r
+ byte BIT12 :1; /* Timer Input Capture/Output Compare Register 5 Bit 12 */\r
+ byte BIT13 :1; /* Timer Input Capture/Output Compare Register 5 Bit 13 */\r
+ byte BIT14 :1; /* Timer Input Capture/Output Compare Register 5 Bit 14 */\r
+ byte BIT15 :1; /* Timer Input Capture/Output Compare Register 5 Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT_8 :8;\r
+ } MergedBits;\r
+ } TC5HiSTR;\r
+ #define TC5Hi _TC5.Overlap_STR.TC5HiSTR.Byte\r
+ #define TC5Hi_BIT8 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT8\r
+ #define TC5Hi_BIT9 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT9\r
+ #define TC5Hi_BIT10 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT10\r
+ #define TC5Hi_BIT11 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT11\r
+ #define TC5Hi_BIT12 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT12\r
+ #define TC5Hi_BIT13 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT13\r
+ #define TC5Hi_BIT14 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT14\r
+ #define TC5Hi_BIT15 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT15\r
+ #define TC5Hi_BIT_8 _TC5.Overlap_STR.TC5HiSTR.MergedBits.grpBIT_8\r
+ #define TC5Hi_BIT TC5Hi_BIT_8\r
+ \r
+ /*** TC5Lo - Timer Input Capture/Output Compare Register 5 Low; 0x0000005B ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* Timer Input Capture/Output Compare Register 5 Bit 0 */\r
+ byte BIT1 :1; /* Timer Input Capture/Output Compare Register 5 Bit 1 */\r
+ byte BIT2 :1; /* Timer Input Capture/Output Compare Register 5 Bit 2 */\r
+ byte BIT3 :1; /* Timer Input Capture/Output Compare Register 5 Bit 3 */\r
+ byte BIT4 :1; /* Timer Input Capture/Output Compare Register 5 Bit 4 */\r
+ byte BIT5 :1; /* Timer Input Capture/Output Compare Register 5 Bit 5 */\r
+ byte BIT6 :1; /* Timer Input Capture/Output Compare Register 5 Bit 6 */\r
+ byte BIT7 :1; /* Timer Input Capture/Output Compare Register 5 Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } TC5LoSTR;\r
+ #define TC5Lo _TC5.Overlap_STR.TC5LoSTR.Byte\r
+ #define TC5Lo_BIT0 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT0\r
+ #define TC5Lo_BIT1 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT1\r
+ #define TC5Lo_BIT2 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT2\r
+ #define TC5Lo_BIT3 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT3\r
+ #define TC5Lo_BIT4 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT4\r
+ #define TC5Lo_BIT5 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT5\r
+ #define TC5Lo_BIT6 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT6\r
+ #define TC5Lo_BIT7 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT7\r
+ #define TC5Lo_BIT _TC5.Overlap_STR.TC5LoSTR.MergedBits.grpBIT\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word grpBIT :16;\r
+ } MergedBits;\r
+} TC5STR;\r
+extern volatile TC5STR _TC5 @(REG_BASE + 0x0000005A);\r
+#define TC5 _TC5.Word\r
+#define TC5_BIT _TC5.MergedBits.grpBIT\r
+\r
+\r
+/*** TC6 - Timer Input Capture/Output Compare Register 6; 0x0000005C ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** TC6Hi - Timer Input Capture/Output Compare Register 6 High; 0x0000005C ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT8 :1; /* Timer Input Capture/Output Compare Register 6 Bit 8 */\r
+ byte BIT9 :1; /* Timer Input Capture/Output Compare Register 6 Bit 9 */\r
+ byte BIT10 :1; /* Timer Input Capture/Output Compare Register 6 Bit 10 */\r
+ byte BIT11 :1; /* Timer Input Capture/Output Compare Register 6 Bit 11 */\r
+ byte BIT12 :1; /* Timer Input Capture/Output Compare Register 6 Bit 12 */\r
+ byte BIT13 :1; /* Timer Input Capture/Output Compare Register 6 Bit 13 */\r
+ byte BIT14 :1; /* Timer Input Capture/Output Compare Register 6 Bit 14 */\r
+ byte BIT15 :1; /* Timer Input Capture/Output Compare Register 6 Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT_8 :8;\r
+ } MergedBits;\r
+ } TC6HiSTR;\r
+ #define TC6Hi _TC6.Overlap_STR.TC6HiSTR.Byte\r
+ #define TC6Hi_BIT8 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT8\r
+ #define TC6Hi_BIT9 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT9\r
+ #define TC6Hi_BIT10 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT10\r
+ #define TC6Hi_BIT11 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT11\r
+ #define TC6Hi_BIT12 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT12\r
+ #define TC6Hi_BIT13 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT13\r
+ #define TC6Hi_BIT14 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT14\r
+ #define TC6Hi_BIT15 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT15\r
+ #define TC6Hi_BIT_8 _TC6.Overlap_STR.TC6HiSTR.MergedBits.grpBIT_8\r
+ #define TC6Hi_BIT TC6Hi_BIT_8\r
+ \r
+ /*** TC6Lo - Timer Input Capture/Output Compare Register 6 Low; 0x0000005D ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* Timer Input Capture/Output Compare Register 6 Bit 0 */\r
+ byte BIT1 :1; /* Timer Input Capture/Output Compare Register 6 Bit 1 */\r
+ byte BIT2 :1; /* Timer Input Capture/Output Compare Register 6 Bit 2 */\r
+ byte BIT3 :1; /* Timer Input Capture/Output Compare Register 6 Bit 3 */\r
+ byte BIT4 :1; /* Timer Input Capture/Output Compare Register 6 Bit 4 */\r
+ byte BIT5 :1; /* Timer Input Capture/Output Compare Register 6 Bit 5 */\r
+ byte BIT6 :1; /* Timer Input Capture/Output Compare Register 6 Bit 6 */\r
+ byte BIT7 :1; /* Timer Input Capture/Output Compare Register 6 Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } TC6LoSTR;\r
+ #define TC6Lo _TC6.Overlap_STR.TC6LoSTR.Byte\r
+ #define TC6Lo_BIT0 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT0\r
+ #define TC6Lo_BIT1 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT1\r
+ #define TC6Lo_BIT2 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT2\r
+ #define TC6Lo_BIT3 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT3\r
+ #define TC6Lo_BIT4 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT4\r
+ #define TC6Lo_BIT5 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT5\r
+ #define TC6Lo_BIT6 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT6\r
+ #define TC6Lo_BIT7 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT7\r
+ #define TC6Lo_BIT _TC6.Overlap_STR.TC6LoSTR.MergedBits.grpBIT\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word grpBIT :16;\r
+ } MergedBits;\r
+} TC6STR;\r
+extern volatile TC6STR _TC6 @(REG_BASE + 0x0000005C);\r
+#define TC6 _TC6.Word\r
+#define TC6_BIT _TC6.MergedBits.grpBIT\r
+\r
+\r
+/*** TC7 - Timer Input Capture/Output Compare Register 7; 0x0000005E ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** TC7Hi - Timer Input Capture/Output Compare Register 7 High; 0x0000005E ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT8 :1; /* Timer Input Capture/Output Compare Register 7 Bit 8 */\r
+ byte BIT9 :1; /* Timer Input Capture/Output Compare Register 7 Bit 9 */\r
+ byte BIT10 :1; /* Timer Input Capture/Output Compare Register 7 Bit 10 */\r
+ byte BIT11 :1; /* Timer Input Capture/Output Compare Register 7 Bit 11 */\r
+ byte BIT12 :1; /* Timer Input Capture/Output Compare Register 7 Bit 12 */\r
+ byte BIT13 :1; /* Timer Input Capture/Output Compare Register 7 Bit 13 */\r
+ byte BIT14 :1; /* Timer Input Capture/Output Compare Register 7 Bit 14 */\r
+ byte BIT15 :1; /* Timer Input Capture/Output Compare Register 7 Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT_8 :8;\r
+ } MergedBits;\r
+ } TC7HiSTR;\r
+ #define TC7Hi _TC7.Overlap_STR.TC7HiSTR.Byte\r
+ #define TC7Hi_BIT8 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT8\r
+ #define TC7Hi_BIT9 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT9\r
+ #define TC7Hi_BIT10 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT10\r
+ #define TC7Hi_BIT11 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT11\r
+ #define TC7Hi_BIT12 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT12\r
+ #define TC7Hi_BIT13 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT13\r
+ #define TC7Hi_BIT14 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT14\r
+ #define TC7Hi_BIT15 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT15\r
+ #define TC7Hi_BIT_8 _TC7.Overlap_STR.TC7HiSTR.MergedBits.grpBIT_8\r
+ #define TC7Hi_BIT TC7Hi_BIT_8\r
+ \r
+ /*** TC7Lo - Timer Input Capture/Output Compare Register 7 Low; 0x0000005F ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* Timer Input Capture/Output Compare Register 7 Bit 0 */\r
+ byte BIT1 :1; /* Timer Input Capture/Output Compare Register 7 Bit 1 */\r
+ byte BIT2 :1; /* Timer Input Capture/Output Compare Register 7 Bit 2 */\r
+ byte BIT3 :1; /* Timer Input Capture/Output Compare Register 7 Bit 3 */\r
+ byte BIT4 :1; /* Timer Input Capture/Output Compare Register 7 Bit 4 */\r
+ byte BIT5 :1; /* Timer Input Capture/Output Compare Register 7 Bit 5 */\r
+ byte BIT6 :1; /* Timer Input Capture/Output Compare Register 7 Bit 6 */\r
+ byte BIT7 :1; /* Timer Input Capture/Output Compare Register 7 Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } TC7LoSTR;\r
+ #define TC7Lo _TC7.Overlap_STR.TC7LoSTR.Byte\r
+ #define TC7Lo_BIT0 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT0\r
+ #define TC7Lo_BIT1 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT1\r
+ #define TC7Lo_BIT2 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT2\r
+ #define TC7Lo_BIT3 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT3\r
+ #define TC7Lo_BIT4 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT4\r
+ #define TC7Lo_BIT5 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT5\r
+ #define TC7Lo_BIT6 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT6\r
+ #define TC7Lo_BIT7 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT7\r
+ #define TC7Lo_BIT _TC7.Overlap_STR.TC7LoSTR.MergedBits.grpBIT\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word grpBIT :16;\r
+ } MergedBits;\r
+} TC7STR;\r
+extern volatile TC7STR _TC7 @(REG_BASE + 0x0000005E);\r
+#define TC7 _TC7.Word\r
+#define TC7_BIT _TC7.MergedBits.grpBIT\r
+\r
+\r
+/*** PACNT - Pulse Accumulators Count Register; 0x00000062 ***/\r
+typedef union {\r
+ word Word;\r
+ struct {\r
+ word grpBIT :16;\r
+ } MergedBits;\r
+} PACNTSTR;\r
+extern volatile PACNTSTR _PACNT @(REG_BASE + 0x00000062);\r
+#define PACNT _PACNT.Word\r
+#define PACNT_BIT _PACNT.MergedBits.grpBIT\r
+\r
+\r
+/*** ATDCTL23 - ATD Control Register 23; 0x00000082 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** ATDCTL2 - ATD Control Register 2; 0x00000082 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte ASCIF :1; /* ATD Sequence Complete Interrupt Flag */\r
+ byte ASCIE :1; /* ATD Sequence Complete Interrupt Enable */\r
+ byte ETRIGE :1; /* External Trigger Mode enable */\r
+ byte ETRIGP :1; /* External Trigger Polarity */\r
+ byte ETRIGLE :1; /* External Trigger Level/Edge control */\r
+ byte AWAI :1; /* ATD Wait Mode */\r
+ byte AFFC :1; /* ATD Fast Conversion Complete Flag Clear */\r
+ byte ADPU :1; /* ATD Disable / Power Down */\r
+ } Bits;\r
+ } ATDCTL2STR;\r
+ #define ATDCTL2 _ATDCTL23.Overlap_STR.ATDCTL2STR.Byte\r
+ #define ATDCTL2_ASCIF _ATDCTL23.Overlap_STR.ATDCTL2STR.Bits.ASCIF\r
+ #define ATDCTL2_ASCIE _ATDCTL23.Overlap_STR.ATDCTL2STR.Bits.ASCIE\r
+ #define ATDCTL2_ETRIGE _ATDCTL23.Overlap_STR.ATDCTL2STR.Bits.ETRIGE\r
+ #define ATDCTL2_ETRIGP _ATDCTL23.Overlap_STR.ATDCTL2STR.Bits.ETRIGP\r
+ #define ATDCTL2_ETRIGLE _ATDCTL23.Overlap_STR.ATDCTL2STR.Bits.ETRIGLE\r
+ #define ATDCTL2_AWAI _ATDCTL23.Overlap_STR.ATDCTL2STR.Bits.AWAI\r
+ #define ATDCTL2_AFFC _ATDCTL23.Overlap_STR.ATDCTL2STR.Bits.AFFC\r
+ #define ATDCTL2_ADPU _ATDCTL23.Overlap_STR.ATDCTL2STR.Bits.ADPU\r
+ \r
+ /*** ATDCTL3 - ATD Control Register 3; 0x00000083 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte FRZ0 :1; /* Background Debug Freeze Enable */\r
+ byte FRZ1 :1; /* Background Debug Freeze Enable */\r
+ byte FIFO :1; /* Result Register FIFO Mode */\r
+ byte S1C :1; /* Conversion Sequence Length 1 */\r
+ byte S2C :1; /* Conversion Sequence Length 2 */\r
+ byte S4C :1; /* Conversion Sequence Length 4 */\r
+ byte S8C :1; /* Conversion Sequence Length 8 */\r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpFRZ :2;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+ } ATDCTL3STR;\r
+ #define ATDCTL3 _ATDCTL23.Overlap_STR.ATDCTL3STR.Byte\r
+ #define ATDCTL3_FRZ0 _ATDCTL23.Overlap_STR.ATDCTL3STR.Bits.FRZ0\r
+ #define ATDCTL3_FRZ1 _ATDCTL23.Overlap_STR.ATDCTL3STR.Bits.FRZ1\r
+ #define ATDCTL3_FIFO _ATDCTL23.Overlap_STR.ATDCTL3STR.Bits.FIFO\r
+ #define ATDCTL3_S1C _ATDCTL23.Overlap_STR.ATDCTL3STR.Bits.S1C\r
+ #define ATDCTL3_S2C _ATDCTL23.Overlap_STR.ATDCTL3STR.Bits.S2C\r
+ #define ATDCTL3_S4C _ATDCTL23.Overlap_STR.ATDCTL3STR.Bits.S4C\r
+ #define ATDCTL3_S8C _ATDCTL23.Overlap_STR.ATDCTL3STR.Bits.S8C\r
+ #define ATDCTL3_FRZ _ATDCTL23.Overlap_STR.ATDCTL3STR.MergedBits.grpFRZ\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word FRZ0 :1; /* Background Debug Freeze Enable */\r
+ word FRZ1 :1; /* Background Debug Freeze Enable */\r
+ word FIFO :1; /* Result Register FIFO Mode */\r
+ word S1C :1; /* Conversion Sequence Length 1 */\r
+ word S2C :1; /* Conversion Sequence Length 2 */\r
+ word S4C :1; /* Conversion Sequence Length 4 */\r
+ word S8C :1; /* Conversion Sequence Length 8 */\r
+ word :1; \r
+ word ASCIF :1; /* ATD Sequence Complete Interrupt Flag */\r
+ word ASCIE :1; /* ATD Sequence Complete Interrupt Enable */\r
+ word ETRIGE :1; /* External Trigger Mode enable */\r
+ word ETRIGP :1; /* External Trigger Polarity */\r
+ word ETRIGLE :1; /* External Trigger Level/Edge control */\r
+ word AWAI :1; /* ATD Wait Mode */\r
+ word AFFC :1; /* ATD Fast Conversion Complete Flag Clear */\r
+ word ADPU :1; /* ATD Disable / Power Down */\r
+ } Bits;\r
+ struct {\r
+ word grpFRZ :2;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ } MergedBits;\r
+} ATDCTL23STR;\r
+extern volatile ATDCTL23STR _ATDCTL23 @(REG_BASE + 0x00000082);\r
+#define ATDCTL23 _ATDCTL23.Word\r
+#define ATDCTL23_FRZ0 _ATDCTL23.Bits.FRZ0\r
+#define ATDCTL23_FRZ1 _ATDCTL23.Bits.FRZ1\r
+#define ATDCTL23_FIFO _ATDCTL23.Bits.FIFO\r
+#define ATDCTL23_S1C _ATDCTL23.Bits.S1C\r
+#define ATDCTL23_S2C _ATDCTL23.Bits.S2C\r
+#define ATDCTL23_S4C _ATDCTL23.Bits.S4C\r
+#define ATDCTL23_S8C _ATDCTL23.Bits.S8C\r
+#define ATDCTL23_ASCIF _ATDCTL23.Bits.ASCIF\r
+#define ATDCTL23_ASCIE _ATDCTL23.Bits.ASCIE\r
+#define ATDCTL23_ETRIGE _ATDCTL23.Bits.ETRIGE\r
+#define ATDCTL23_ETRIGP _ATDCTL23.Bits.ETRIGP\r
+#define ATDCTL23_ETRIGLE _ATDCTL23.Bits.ETRIGLE\r
+#define ATDCTL23_AWAI _ATDCTL23.Bits.AWAI\r
+#define ATDCTL23_AFFC _ATDCTL23.Bits.AFFC\r
+#define ATDCTL23_ADPU _ATDCTL23.Bits.ADPU\r
+#define ATDCTL23_FRZ _ATDCTL23.MergedBits.grpFRZ\r
+\r
+\r
+/*** ATDCTL45 - ATD Control Register 45; 0x00000084 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** ATDCTL4 - ATD Control Register 4; 0x00000084 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte PRS0 :1; /* ATD Clock Prescaler 0 */\r
+ byte PRS1 :1; /* ATD Clock Prescaler 1 */\r
+ byte PRS2 :1; /* ATD Clock Prescaler 2 */\r
+ byte PRS3 :1; /* ATD Clock Prescaler 3 */\r
+ byte PRS4 :1; /* ATD Clock Prescaler 4 */\r
+ byte SMP0 :1; /* Sample Time Select 0 */\r
+ byte SMP1 :1; /* Sample Time Select 1 */\r
+ byte SRES8 :1; /* A/D Resolution Select */\r
+ } Bits;\r
+ struct {\r
+ byte grpPRS :5;\r
+ byte grpSMP :2;\r
+ byte grpSRES_8 :1;\r
+ } MergedBits;\r
+ } ATDCTL4STR;\r
+ #define ATDCTL4 _ATDCTL45.Overlap_STR.ATDCTL4STR.Byte\r
+ #define ATDCTL4_PRS0 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.PRS0\r
+ #define ATDCTL4_PRS1 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.PRS1\r
+ #define ATDCTL4_PRS2 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.PRS2\r
+ #define ATDCTL4_PRS3 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.PRS3\r
+ #define ATDCTL4_PRS4 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.PRS4\r
+ #define ATDCTL4_SMP0 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.SMP0\r
+ #define ATDCTL4_SMP1 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.SMP1\r
+ #define ATDCTL4_SRES8 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.SRES8\r
+ #define ATDCTL4_PRS _ATDCTL45.Overlap_STR.ATDCTL4STR.MergedBits.grpPRS\r
+ #define ATDCTL4_SMP _ATDCTL45.Overlap_STR.ATDCTL4STR.MergedBits.grpSMP\r
+ \r
+ /*** ATDCTL5 - ATD Control Register 5; 0x00000085 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte CA :1; /* Analog Input Channel Select Code A */\r
+ byte CB :1; /* Analog Input Channel Select Code B */\r
+ byte CC :1; /* Analog Input Channel Select Code C */\r
+ byte :1; \r
+ byte MULT :1; /* Multi-Channel Sample Mode */\r
+ byte SCAN :1; /* Continuous Conversion Sequence Mode */\r
+ byte DSGN :1; /* Signed/Unsigned Result Data Mode */\r
+ byte DJM :1; /* Result Register Data Justification Mode */\r
+ } Bits;\r
+ } ATDCTL5STR;\r
+ #define ATDCTL5 _ATDCTL45.Overlap_STR.ATDCTL5STR.Byte\r
+ #define ATDCTL5_CA _ATDCTL45.Overlap_STR.ATDCTL5STR.Bits.CA\r
+ #define ATDCTL5_CB _ATDCTL45.Overlap_STR.ATDCTL5STR.Bits.CB\r
+ #define ATDCTL5_CC _ATDCTL45.Overlap_STR.ATDCTL5STR.Bits.CC\r
+ #define ATDCTL5_MULT _ATDCTL45.Overlap_STR.ATDCTL5STR.Bits.MULT\r
+ #define ATDCTL5_SCAN _ATDCTL45.Overlap_STR.ATDCTL5STR.Bits.SCAN\r
+ #define ATDCTL5_DSGN _ATDCTL45.Overlap_STR.ATDCTL5STR.Bits.DSGN\r
+ #define ATDCTL5_DJM _ATDCTL45.Overlap_STR.ATDCTL5STR.Bits.DJM\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word CA :1; /* Analog Input Channel Select Code A */\r
+ word CB :1; /* Analog Input Channel Select Code B */\r
+ word CC :1; /* Analog Input Channel Select Code C */\r
+ word :1; \r
+ word MULT :1; /* Multi-Channel Sample Mode */\r
+ word SCAN :1; /* Continuous Conversion Sequence Mode */\r
+ word DSGN :1; /* Signed/Unsigned Result Data Mode */\r
+ word DJM :1; /* Result Register Data Justification Mode */\r
+ word PRS0 :1; /* ATD Clock Prescaler 0 */\r
+ word PRS1 :1; /* ATD Clock Prescaler 1 */\r
+ word PRS2 :1; /* ATD Clock Prescaler 2 */\r
+ word PRS3 :1; /* ATD Clock Prescaler 3 */\r
+ word PRS4 :1; /* ATD Clock Prescaler 4 */\r
+ word SMP0 :1; /* Sample Time Select 0 */\r
+ word SMP1 :1; /* Sample Time Select 1 */\r
+ word SRES8 :1; /* A/D Resolution Select */\r
+ } Bits;\r
+ struct {\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word grpPRS :5;\r
+ word grpSMP :2;\r
+ word grpSRES_8 :1;\r
+ } MergedBits;\r
+} ATDCTL45STR;\r
+extern volatile ATDCTL45STR _ATDCTL45 @(REG_BASE + 0x00000084);\r
+#define ATDCTL45 _ATDCTL45.Word\r
+#define ATDCTL45_CA _ATDCTL45.Bits.CA\r
+#define ATDCTL45_CB _ATDCTL45.Bits.CB\r
+#define ATDCTL45_CC _ATDCTL45.Bits.CC\r
+#define ATDCTL45_MULT _ATDCTL45.Bits.MULT\r
+#define ATDCTL45_SCAN _ATDCTL45.Bits.SCAN\r
+#define ATDCTL45_DSGN _ATDCTL45.Bits.DSGN\r
+#define ATDCTL45_DJM _ATDCTL45.Bits.DJM\r
+#define ATDCTL45_PRS0 _ATDCTL45.Bits.PRS0\r
+#define ATDCTL45_PRS1 _ATDCTL45.Bits.PRS1\r
+#define ATDCTL45_PRS2 _ATDCTL45.Bits.PRS2\r
+#define ATDCTL45_PRS3 _ATDCTL45.Bits.PRS3\r
+#define ATDCTL45_PRS4 _ATDCTL45.Bits.PRS4\r
+#define ATDCTL45_SMP0 _ATDCTL45.Bits.SMP0\r
+#define ATDCTL45_SMP1 _ATDCTL45.Bits.SMP1\r
+#define ATDCTL45_SRES8 _ATDCTL45.Bits.SRES8\r
+#define ATDCTL45_PRS _ATDCTL45.MergedBits.grpPRS\r
+#define ATDCTL45_SMP _ATDCTL45.MergedBits.grpSMP\r
+\r
+\r
+/*** ATDDR0 - A/D Conversion Result Register 0; 0x00000090 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** ATDDR0H - A/D Conversion Result Register 0 High; 0x00000090 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT8 :1; /* Bit 8 */\r
+ byte BIT9 :1; /* Bit 9 */\r
+ byte BIT10 :1; /* Bit 10 */\r
+ byte BIT11 :1; /* Bit 11 */\r
+ byte BIT12 :1; /* Bit 12 */\r
+ byte BIT13 :1; /* Bit 13 */\r
+ byte BIT14 :1; /* Bit 14 */\r
+ byte BIT15 :1; /* Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT_8 :8;\r
+ } MergedBits;\r
+ } ATDDR0HSTR;\r
+ #define ATDDR0H _ATDDR0.Overlap_STR.ATDDR0HSTR.Byte\r
+ #define ATDDR0H_BIT8 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT8\r
+ #define ATDDR0H_BIT9 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT9\r
+ #define ATDDR0H_BIT10 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT10\r
+ #define ATDDR0H_BIT11 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT11\r
+ #define ATDDR0H_BIT12 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT12\r
+ #define ATDDR0H_BIT13 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT13\r
+ #define ATDDR0H_BIT14 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT14\r
+ #define ATDDR0H_BIT15 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT15\r
+ #define ATDDR0H_BIT_8 _ATDDR0.Overlap_STR.ATDDR0HSTR.MergedBits.grpBIT_8\r
+ #define ATDDR0H_BIT ATDDR0H_BIT_8\r
+ \r
+ /*** ATDDR0L - A/D Conversion Result Register 0 Low; 0x00000091 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte BIT6 :1; /* Bit 6 */\r
+ byte BIT7 :1; /* Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpBIT_6 :2;\r
+ } MergedBits;\r
+ } ATDDR0LSTR;\r
+ #define ATDDR0L _ATDDR0.Overlap_STR.ATDDR0LSTR.Byte\r
+ #define ATDDR0L_BIT6 _ATDDR0.Overlap_STR.ATDDR0LSTR.Bits.BIT6\r
+ #define ATDDR0L_BIT7 _ATDDR0.Overlap_STR.ATDDR0LSTR.Bits.BIT7\r
+ #define ATDDR0L_BIT_6 _ATDDR0.Overlap_STR.ATDDR0LSTR.MergedBits.grpBIT_6\r
+ #define ATDDR0L_BIT ATDDR0L_BIT_6\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word BIT6 :1; /* Bit 6 */\r
+ word BIT7 :1; /* Bit 7 */\r
+ word BIT8 :1; /* Bit 8 */\r
+ word BIT9 :1; /* Bit 9 */\r
+ word BIT10 :1; /* Bit 10 */\r
+ word BIT11 :1; /* Bit 11 */\r
+ word BIT12 :1; /* Bit 12 */\r
+ word BIT13 :1; /* Bit 13 */\r
+ word BIT14 :1; /* Bit 14 */\r
+ word BIT15 :1; /* Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word grpBIT_6 :10;\r
+ } MergedBits;\r
+} ATDDR0STR;\r
+extern volatile ATDDR0STR _ATDDR0 @(REG_BASE + 0x00000090);\r
+#define ATDDR0 _ATDDR0.Word\r
+#define ATDDR0_BIT6 _ATDDR0.Bits.BIT6\r
+#define ATDDR0_BIT7 _ATDDR0.Bits.BIT7\r
+#define ATDDR0_BIT8 _ATDDR0.Bits.BIT8\r
+#define ATDDR0_BIT9 _ATDDR0.Bits.BIT9\r
+#define ATDDR0_BIT10 _ATDDR0.Bits.BIT10\r
+#define ATDDR0_BIT11 _ATDDR0.Bits.BIT11\r
+#define ATDDR0_BIT12 _ATDDR0.Bits.BIT12\r
+#define ATDDR0_BIT13 _ATDDR0.Bits.BIT13\r
+#define ATDDR0_BIT14 _ATDDR0.Bits.BIT14\r
+#define ATDDR0_BIT15 _ATDDR0.Bits.BIT15\r
+#define ATDDR0_BIT_6 _ATDDR0.MergedBits.grpBIT_6\r
+#define ATDDR0_BIT ATDDR0_BIT_6\r
+\r
+\r
+/*** ATDDR1 - A/D Conversion Result Register 1; 0x00000092 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** ATDDR1H - A/D Conversion Result Register 1 High; 0x00000092 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT8 :1; /* Bit 8 */\r
+ byte BIT9 :1; /* Bit 9 */\r
+ byte BIT10 :1; /* Bit 10 */\r
+ byte BIT11 :1; /* Bit 11 */\r
+ byte BIT12 :1; /* Bit 12 */\r
+ byte BIT13 :1; /* Bit 13 */\r
+ byte BIT14 :1; /* Bit 14 */\r
+ byte BIT15 :1; /* Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT_8 :8;\r
+ } MergedBits;\r
+ } ATDDR1HSTR;\r
+ #define ATDDR1H _ATDDR1.Overlap_STR.ATDDR1HSTR.Byte\r
+ #define ATDDR1H_BIT8 _ATDDR1.Overlap_STR.ATDDR1HSTR.Bits.BIT8\r
+ #define ATDDR1H_BIT9 _ATDDR1.Overlap_STR.ATDDR1HSTR.Bits.BIT9\r
+ #define ATDDR1H_BIT10 _ATDDR1.Overlap_STR.ATDDR1HSTR.Bits.BIT10\r
+ #define ATDDR1H_BIT11 _ATDDR1.Overlap_STR.ATDDR1HSTR.Bits.BIT11\r
+ #define ATDDR1H_BIT12 _ATDDR1.Overlap_STR.ATDDR1HSTR.Bits.BIT12\r
+ #define ATDDR1H_BIT13 _ATDDR1.Overlap_STR.ATDDR1HSTR.Bits.BIT13\r
+ #define ATDDR1H_BIT14 _ATDDR1.Overlap_STR.ATDDR1HSTR.Bits.BIT14\r
+ #define ATDDR1H_BIT15 _ATDDR1.Overlap_STR.ATDDR1HSTR.Bits.BIT15\r
+ #define ATDDR1H_BIT_8 _ATDDR1.Overlap_STR.ATDDR1HSTR.MergedBits.grpBIT_8\r
+ #define ATDDR1H_BIT ATDDR1H_BIT_8\r
+ \r
+ /*** ATDDR1L - A/D Conversion Result Register 1 Low; 0x00000093 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte BIT6 :1; /* Bit 6 */\r
+ byte BIT7 :1; /* Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpBIT_6 :2;\r
+ } MergedBits;\r
+ } ATDDR1LSTR;\r
+ #define ATDDR1L _ATDDR1.Overlap_STR.ATDDR1LSTR.Byte\r
+ #define ATDDR1L_BIT6 _ATDDR1.Overlap_STR.ATDDR1LSTR.Bits.BIT6\r
+ #define ATDDR1L_BIT7 _ATDDR1.Overlap_STR.ATDDR1LSTR.Bits.BIT7\r
+ #define ATDDR1L_BIT_6 _ATDDR1.Overlap_STR.ATDDR1LSTR.MergedBits.grpBIT_6\r
+ #define ATDDR1L_BIT ATDDR1L_BIT_6\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word BIT6 :1; /* Bit 6 */\r
+ word BIT7 :1; /* Bit 7 */\r
+ word BIT8 :1; /* Bit 8 */\r
+ word BIT9 :1; /* Bit 9 */\r
+ word BIT10 :1; /* Bit 10 */\r
+ word BIT11 :1; /* Bit 11 */\r
+ word BIT12 :1; /* Bit 12 */\r
+ word BIT13 :1; /* Bit 13 */\r
+ word BIT14 :1; /* Bit 14 */\r
+ word BIT15 :1; /* Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word grpBIT_6 :10;\r
+ } MergedBits;\r
+} ATDDR1STR;\r
+extern volatile ATDDR1STR _ATDDR1 @(REG_BASE + 0x00000092);\r
+#define ATDDR1 _ATDDR1.Word\r
+#define ATDDR1_BIT6 _ATDDR1.Bits.BIT6\r
+#define ATDDR1_BIT7 _ATDDR1.Bits.BIT7\r
+#define ATDDR1_BIT8 _ATDDR1.Bits.BIT8\r
+#define ATDDR1_BIT9 _ATDDR1.Bits.BIT9\r
+#define ATDDR1_BIT10 _ATDDR1.Bits.BIT10\r
+#define ATDDR1_BIT11 _ATDDR1.Bits.BIT11\r
+#define ATDDR1_BIT12 _ATDDR1.Bits.BIT12\r
+#define ATDDR1_BIT13 _ATDDR1.Bits.BIT13\r
+#define ATDDR1_BIT14 _ATDDR1.Bits.BIT14\r
+#define ATDDR1_BIT15 _ATDDR1.Bits.BIT15\r
+#define ATDDR1_BIT_6 _ATDDR1.MergedBits.grpBIT_6\r
+#define ATDDR1_BIT ATDDR1_BIT_6\r
+\r
+\r
+/*** ATDDR2 - A/D Conversion Result Register 2; 0x00000094 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** ATDDR2H - A/D Conversion Result Register 2 High; 0x00000094 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT8 :1; /* Bit 8 */\r
+ byte BIT9 :1; /* Bit 9 */\r
+ byte BIT10 :1; /* Bit 10 */\r
+ byte BIT11 :1; /* Bit 11 */\r
+ byte BIT12 :1; /* Bit 12 */\r
+ byte BIT13 :1; /* Bit 13 */\r
+ byte BIT14 :1; /* Bit 14 */\r
+ byte BIT15 :1; /* Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT_8 :8;\r
+ } MergedBits;\r
+ } ATDDR2HSTR;\r
+ #define ATDDR2H _ATDDR2.Overlap_STR.ATDDR2HSTR.Byte\r
+ #define ATDDR2H_BIT8 _ATDDR2.Overlap_STR.ATDDR2HSTR.Bits.BIT8\r
+ #define ATDDR2H_BIT9 _ATDDR2.Overlap_STR.ATDDR2HSTR.Bits.BIT9\r
+ #define ATDDR2H_BIT10 _ATDDR2.Overlap_STR.ATDDR2HSTR.Bits.BIT10\r
+ #define ATDDR2H_BIT11 _ATDDR2.Overlap_STR.ATDDR2HSTR.Bits.BIT11\r
+ #define ATDDR2H_BIT12 _ATDDR2.Overlap_STR.ATDDR2HSTR.Bits.BIT12\r
+ #define ATDDR2H_BIT13 _ATDDR2.Overlap_STR.ATDDR2HSTR.Bits.BIT13\r
+ #define ATDDR2H_BIT14 _ATDDR2.Overlap_STR.ATDDR2HSTR.Bits.BIT14\r
+ #define ATDDR2H_BIT15 _ATDDR2.Overlap_STR.ATDDR2HSTR.Bits.BIT15\r
+ #define ATDDR2H_BIT_8 _ATDDR2.Overlap_STR.ATDDR2HSTR.MergedBits.grpBIT_8\r
+ #define ATDDR2H_BIT ATDDR2H_BIT_8\r
+ \r
+ /*** ATDDR2L - A/D Conversion Result Register 2 Low; 0x00000095 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte BIT6 :1; /* Bit 6 */\r
+ byte BIT7 :1; /* Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpBIT_6 :2;\r
+ } MergedBits;\r
+ } ATDDR2LSTR;\r
+ #define ATDDR2L _ATDDR2.Overlap_STR.ATDDR2LSTR.Byte\r
+ #define ATDDR2L_BIT6 _ATDDR2.Overlap_STR.ATDDR2LSTR.Bits.BIT6\r
+ #define ATDDR2L_BIT7 _ATDDR2.Overlap_STR.ATDDR2LSTR.Bits.BIT7\r
+ #define ATDDR2L_BIT_6 _ATDDR2.Overlap_STR.ATDDR2LSTR.MergedBits.grpBIT_6\r
+ #define ATDDR2L_BIT ATDDR2L_BIT_6\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word BIT6 :1; /* Bit 6 */\r
+ word BIT7 :1; /* Bit 7 */\r
+ word BIT8 :1; /* Bit 8 */\r
+ word BIT9 :1; /* Bit 9 */\r
+ word BIT10 :1; /* Bit 10 */\r
+ word BIT11 :1; /* Bit 11 */\r
+ word BIT12 :1; /* Bit 12 */\r
+ word BIT13 :1; /* Bit 13 */\r
+ word BIT14 :1; /* Bit 14 */\r
+ word BIT15 :1; /* Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word grpBIT_6 :10;\r
+ } MergedBits;\r
+} ATDDR2STR;\r
+extern volatile ATDDR2STR _ATDDR2 @(REG_BASE + 0x00000094);\r
+#define ATDDR2 _ATDDR2.Word\r
+#define ATDDR2_BIT6 _ATDDR2.Bits.BIT6\r
+#define ATDDR2_BIT7 _ATDDR2.Bits.BIT7\r
+#define ATDDR2_BIT8 _ATDDR2.Bits.BIT8\r
+#define ATDDR2_BIT9 _ATDDR2.Bits.BIT9\r
+#define ATDDR2_BIT10 _ATDDR2.Bits.BIT10\r
+#define ATDDR2_BIT11 _ATDDR2.Bits.BIT11\r
+#define ATDDR2_BIT12 _ATDDR2.Bits.BIT12\r
+#define ATDDR2_BIT13 _ATDDR2.Bits.BIT13\r
+#define ATDDR2_BIT14 _ATDDR2.Bits.BIT14\r
+#define ATDDR2_BIT15 _ATDDR2.Bits.BIT15\r
+#define ATDDR2_BIT_6 _ATDDR2.MergedBits.grpBIT_6\r
+#define ATDDR2_BIT ATDDR2_BIT_6\r
+\r
+\r
+/*** ATDDR3 - A/D Conversion Result Register 3; 0x00000096 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** ATDDR3H - A/D Conversion Result Register 3 High; 0x00000096 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT8 :1; /* Bit 8 */\r
+ byte BIT9 :1; /* Bit 9 */\r
+ byte BIT10 :1; /* Bit 10 */\r
+ byte BIT11 :1; /* Bit 11 */\r
+ byte BIT12 :1; /* Bit 12 */\r
+ byte BIT13 :1; /* Bit 13 */\r
+ byte BIT14 :1; /* Bit 14 */\r
+ byte BIT15 :1; /* Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT_8 :8;\r
+ } MergedBits;\r
+ } ATDDR3HSTR;\r
+ #define ATDDR3H _ATDDR3.Overlap_STR.ATDDR3HSTR.Byte\r
+ #define ATDDR3H_BIT8 _ATDDR3.Overlap_STR.ATDDR3HSTR.Bits.BIT8\r
+ #define ATDDR3H_BIT9 _ATDDR3.Overlap_STR.ATDDR3HSTR.Bits.BIT9\r
+ #define ATDDR3H_BIT10 _ATDDR3.Overlap_STR.ATDDR3HSTR.Bits.BIT10\r
+ #define ATDDR3H_BIT11 _ATDDR3.Overlap_STR.ATDDR3HSTR.Bits.BIT11\r
+ #define ATDDR3H_BIT12 _ATDDR3.Overlap_STR.ATDDR3HSTR.Bits.BIT12\r
+ #define ATDDR3H_BIT13 _ATDDR3.Overlap_STR.ATDDR3HSTR.Bits.BIT13\r
+ #define ATDDR3H_BIT14 _ATDDR3.Overlap_STR.ATDDR3HSTR.Bits.BIT14\r
+ #define ATDDR3H_BIT15 _ATDDR3.Overlap_STR.ATDDR3HSTR.Bits.BIT15\r
+ #define ATDDR3H_BIT_8 _ATDDR3.Overlap_STR.ATDDR3HSTR.MergedBits.grpBIT_8\r
+ #define ATDDR3H_BIT ATDDR3H_BIT_8\r
+ \r
+ /*** ATDDR3L - A/D Conversion Result Register 3 Low; 0x00000097 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte BIT6 :1; /* Bit 6 */\r
+ byte BIT7 :1; /* Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpBIT_6 :2;\r
+ } MergedBits;\r
+ } ATDDR3LSTR;\r
+ #define ATDDR3L _ATDDR3.Overlap_STR.ATDDR3LSTR.Byte\r
+ #define ATDDR3L_BIT6 _ATDDR3.Overlap_STR.ATDDR3LSTR.Bits.BIT6\r
+ #define ATDDR3L_BIT7 _ATDDR3.Overlap_STR.ATDDR3LSTR.Bits.BIT7\r
+ #define ATDDR3L_BIT_6 _ATDDR3.Overlap_STR.ATDDR3LSTR.MergedBits.grpBIT_6\r
+ #define ATDDR3L_BIT ATDDR3L_BIT_6\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word BIT6 :1; /* Bit 6 */\r
+ word BIT7 :1; /* Bit 7 */\r
+ word BIT8 :1; /* Bit 8 */\r
+ word BIT9 :1; /* Bit 9 */\r
+ word BIT10 :1; /* Bit 10 */\r
+ word BIT11 :1; /* Bit 11 */\r
+ word BIT12 :1; /* Bit 12 */\r
+ word BIT13 :1; /* Bit 13 */\r
+ word BIT14 :1; /* Bit 14 */\r
+ word BIT15 :1; /* Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word grpBIT_6 :10;\r
+ } MergedBits;\r
+} ATDDR3STR;\r
+extern volatile ATDDR3STR _ATDDR3 @(REG_BASE + 0x00000096);\r
+#define ATDDR3 _ATDDR3.Word\r
+#define ATDDR3_BIT6 _ATDDR3.Bits.BIT6\r
+#define ATDDR3_BIT7 _ATDDR3.Bits.BIT7\r
+#define ATDDR3_BIT8 _ATDDR3.Bits.BIT8\r
+#define ATDDR3_BIT9 _ATDDR3.Bits.BIT9\r
+#define ATDDR3_BIT10 _ATDDR3.Bits.BIT10\r
+#define ATDDR3_BIT11 _ATDDR3.Bits.BIT11\r
+#define ATDDR3_BIT12 _ATDDR3.Bits.BIT12\r
+#define ATDDR3_BIT13 _ATDDR3.Bits.BIT13\r
+#define ATDDR3_BIT14 _ATDDR3.Bits.BIT14\r
+#define ATDDR3_BIT15 _ATDDR3.Bits.BIT15\r
+#define ATDDR3_BIT_6 _ATDDR3.MergedBits.grpBIT_6\r
+#define ATDDR3_BIT ATDDR3_BIT_6\r
+\r
+\r
+/*** ATDDR4 - A/D Conversion Result Register 4; 0x00000098 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** ATDDR4H - A/D Conversion Result Register 4 High; 0x00000098 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT8 :1; /* Bit 8 */\r
+ byte BIT9 :1; /* Bit 9 */\r
+ byte BIT10 :1; /* Bit 10 */\r
+ byte BIT11 :1; /* Bit 11 */\r
+ byte BIT12 :1; /* Bit 12 */\r
+ byte BIT13 :1; /* Bit 13 */\r
+ byte BIT14 :1; /* Bit 14 */\r
+ byte BIT15 :1; /* Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT_8 :8;\r
+ } MergedBits;\r
+ } ATDDR4HSTR;\r
+ #define ATDDR4H _ATDDR4.Overlap_STR.ATDDR4HSTR.Byte\r
+ #define ATDDR4H_BIT8 _ATDDR4.Overlap_STR.ATDDR4HSTR.Bits.BIT8\r
+ #define ATDDR4H_BIT9 _ATDDR4.Overlap_STR.ATDDR4HSTR.Bits.BIT9\r
+ #define ATDDR4H_BIT10 _ATDDR4.Overlap_STR.ATDDR4HSTR.Bits.BIT10\r
+ #define ATDDR4H_BIT11 _ATDDR4.Overlap_STR.ATDDR4HSTR.Bits.BIT11\r
+ #define ATDDR4H_BIT12 _ATDDR4.Overlap_STR.ATDDR4HSTR.Bits.BIT12\r
+ #define ATDDR4H_BIT13 _ATDDR4.Overlap_STR.ATDDR4HSTR.Bits.BIT13\r
+ #define ATDDR4H_BIT14 _ATDDR4.Overlap_STR.ATDDR4HSTR.Bits.BIT14\r
+ #define ATDDR4H_BIT15 _ATDDR4.Overlap_STR.ATDDR4HSTR.Bits.BIT15\r
+ #define ATDDR4H_BIT_8 _ATDDR4.Overlap_STR.ATDDR4HSTR.MergedBits.grpBIT_8\r
+ #define ATDDR4H_BIT ATDDR4H_BIT_8\r
+ \r
+ /*** ATDDR4L - A/D Conversion Result Register 4 Low; 0x00000099 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte BIT6 :1; /* Bit 6 */\r
+ byte BIT7 :1; /* Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpBIT_6 :2;\r
+ } MergedBits;\r
+ } ATDDR4LSTR;\r
+ #define ATDDR4L _ATDDR4.Overlap_STR.ATDDR4LSTR.Byte\r
+ #define ATDDR4L_BIT6 _ATDDR4.Overlap_STR.ATDDR4LSTR.Bits.BIT6\r
+ #define ATDDR4L_BIT7 _ATDDR4.Overlap_STR.ATDDR4LSTR.Bits.BIT7\r
+ #define ATDDR4L_BIT_6 _ATDDR4.Overlap_STR.ATDDR4LSTR.MergedBits.grpBIT_6\r
+ #define ATDDR4L_BIT ATDDR4L_BIT_6\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word BIT6 :1; /* Bit 6 */\r
+ word BIT7 :1; /* Bit 7 */\r
+ word BIT8 :1; /* Bit 8 */\r
+ word BIT9 :1; /* Bit 9 */\r
+ word BIT10 :1; /* Bit 10 */\r
+ word BIT11 :1; /* Bit 11 */\r
+ word BIT12 :1; /* Bit 12 */\r
+ word BIT13 :1; /* Bit 13 */\r
+ word BIT14 :1; /* Bit 14 */\r
+ word BIT15 :1; /* Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word grpBIT_6 :10;\r
+ } MergedBits;\r
+} ATDDR4STR;\r
+extern volatile ATDDR4STR _ATDDR4 @(REG_BASE + 0x00000098);\r
+#define ATDDR4 _ATDDR4.Word\r
+#define ATDDR4_BIT6 _ATDDR4.Bits.BIT6\r
+#define ATDDR4_BIT7 _ATDDR4.Bits.BIT7\r
+#define ATDDR4_BIT8 _ATDDR4.Bits.BIT8\r
+#define ATDDR4_BIT9 _ATDDR4.Bits.BIT9\r
+#define ATDDR4_BIT10 _ATDDR4.Bits.BIT10\r
+#define ATDDR4_BIT11 _ATDDR4.Bits.BIT11\r
+#define ATDDR4_BIT12 _ATDDR4.Bits.BIT12\r
+#define ATDDR4_BIT13 _ATDDR4.Bits.BIT13\r
+#define ATDDR4_BIT14 _ATDDR4.Bits.BIT14\r
+#define ATDDR4_BIT15 _ATDDR4.Bits.BIT15\r
+#define ATDDR4_BIT_6 _ATDDR4.MergedBits.grpBIT_6\r
+#define ATDDR4_BIT ATDDR4_BIT_6\r
+\r
+\r
+/*** ATDDR5 - A/D Conversion Result Register 5; 0x0000009A ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** ATDDR5H - A/D Conversion Result Register 5 High; 0x0000009A ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT8 :1; /* Bit 8 */\r
+ byte BIT9 :1; /* Bit 9 */\r
+ byte BIT10 :1; /* Bit 10 */\r
+ byte BIT11 :1; /* Bit 11 */\r
+ byte BIT12 :1; /* Bit 12 */\r
+ byte BIT13 :1; /* Bit 13 */\r
+ byte BIT14 :1; /* Bit 14 */\r
+ byte BIT15 :1; /* Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT_8 :8;\r
+ } MergedBits;\r
+ } ATDDR5HSTR;\r
+ #define ATDDR5H _ATDDR5.Overlap_STR.ATDDR5HSTR.Byte\r
+ #define ATDDR5H_BIT8 _ATDDR5.Overlap_STR.ATDDR5HSTR.Bits.BIT8\r
+ #define ATDDR5H_BIT9 _ATDDR5.Overlap_STR.ATDDR5HSTR.Bits.BIT9\r
+ #define ATDDR5H_BIT10 _ATDDR5.Overlap_STR.ATDDR5HSTR.Bits.BIT10\r
+ #define ATDDR5H_BIT11 _ATDDR5.Overlap_STR.ATDDR5HSTR.Bits.BIT11\r
+ #define ATDDR5H_BIT12 _ATDDR5.Overlap_STR.ATDDR5HSTR.Bits.BIT12\r
+ #define ATDDR5H_BIT13 _ATDDR5.Overlap_STR.ATDDR5HSTR.Bits.BIT13\r
+ #define ATDDR5H_BIT14 _ATDDR5.Overlap_STR.ATDDR5HSTR.Bits.BIT14\r
+ #define ATDDR5H_BIT15 _ATDDR5.Overlap_STR.ATDDR5HSTR.Bits.BIT15\r
+ #define ATDDR5H_BIT_8 _ATDDR5.Overlap_STR.ATDDR5HSTR.MergedBits.grpBIT_8\r
+ #define ATDDR5H_BIT ATDDR5H_BIT_8\r
+ \r
+ /*** ATDDR5L - A/D Conversion Result Register 5 Low; 0x0000009B ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte BIT6 :1; /* Bit 6 */\r
+ byte BIT7 :1; /* Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpBIT_6 :2;\r
+ } MergedBits;\r
+ } ATDDR5LSTR;\r
+ #define ATDDR5L _ATDDR5.Overlap_STR.ATDDR5LSTR.Byte\r
+ #define ATDDR5L_BIT6 _ATDDR5.Overlap_STR.ATDDR5LSTR.Bits.BIT6\r
+ #define ATDDR5L_BIT7 _ATDDR5.Overlap_STR.ATDDR5LSTR.Bits.BIT7\r
+ #define ATDDR5L_BIT_6 _ATDDR5.Overlap_STR.ATDDR5LSTR.MergedBits.grpBIT_6\r
+ #define ATDDR5L_BIT ATDDR5L_BIT_6\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word BIT6 :1; /* Bit 6 */\r
+ word BIT7 :1; /* Bit 7 */\r
+ word BIT8 :1; /* Bit 8 */\r
+ word BIT9 :1; /* Bit 9 */\r
+ word BIT10 :1; /* Bit 10 */\r
+ word BIT11 :1; /* Bit 11 */\r
+ word BIT12 :1; /* Bit 12 */\r
+ word BIT13 :1; /* Bit 13 */\r
+ word BIT14 :1; /* Bit 14 */\r
+ word BIT15 :1; /* Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word grpBIT_6 :10;\r
+ } MergedBits;\r
+} ATDDR5STR;\r
+extern volatile ATDDR5STR _ATDDR5 @(REG_BASE + 0x0000009A);\r
+#define ATDDR5 _ATDDR5.Word\r
+#define ATDDR5_BIT6 _ATDDR5.Bits.BIT6\r
+#define ATDDR5_BIT7 _ATDDR5.Bits.BIT7\r
+#define ATDDR5_BIT8 _ATDDR5.Bits.BIT8\r
+#define ATDDR5_BIT9 _ATDDR5.Bits.BIT9\r
+#define ATDDR5_BIT10 _ATDDR5.Bits.BIT10\r
+#define ATDDR5_BIT11 _ATDDR5.Bits.BIT11\r
+#define ATDDR5_BIT12 _ATDDR5.Bits.BIT12\r
+#define ATDDR5_BIT13 _ATDDR5.Bits.BIT13\r
+#define ATDDR5_BIT14 _ATDDR5.Bits.BIT14\r
+#define ATDDR5_BIT15 _ATDDR5.Bits.BIT15\r
+#define ATDDR5_BIT_6 _ATDDR5.MergedBits.grpBIT_6\r
+#define ATDDR5_BIT ATDDR5_BIT_6\r
+\r
+\r
+/*** ATDDR6 - A/D Conversion Result Register 6; 0x0000009C ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** ATDDR6H - A/D Conversion Result Register 6 High; 0x0000009C ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT8 :1; /* Bit 8 */\r
+ byte BIT9 :1; /* Bit 9 */\r
+ byte BIT10 :1; /* Bit 10 */\r
+ byte BIT11 :1; /* Bit 11 */\r
+ byte BIT12 :1; /* Bit 12 */\r
+ byte BIT13 :1; /* Bit 13 */\r
+ byte BIT14 :1; /* Bit 14 */\r
+ byte BIT15 :1; /* Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT_8 :8;\r
+ } MergedBits;\r
+ } ATDDR6HSTR;\r
+ #define ATDDR6H _ATDDR6.Overlap_STR.ATDDR6HSTR.Byte\r
+ #define ATDDR6H_BIT8 _ATDDR6.Overlap_STR.ATDDR6HSTR.Bits.BIT8\r
+ #define ATDDR6H_BIT9 _ATDDR6.Overlap_STR.ATDDR6HSTR.Bits.BIT9\r
+ #define ATDDR6H_BIT10 _ATDDR6.Overlap_STR.ATDDR6HSTR.Bits.BIT10\r
+ #define ATDDR6H_BIT11 _ATDDR6.Overlap_STR.ATDDR6HSTR.Bits.BIT11\r
+ #define ATDDR6H_BIT12 _ATDDR6.Overlap_STR.ATDDR6HSTR.Bits.BIT12\r
+ #define ATDDR6H_BIT13 _ATDDR6.Overlap_STR.ATDDR6HSTR.Bits.BIT13\r
+ #define ATDDR6H_BIT14 _ATDDR6.Overlap_STR.ATDDR6HSTR.Bits.BIT14\r
+ #define ATDDR6H_BIT15 _ATDDR6.Overlap_STR.ATDDR6HSTR.Bits.BIT15\r
+ #define ATDDR6H_BIT_8 _ATDDR6.Overlap_STR.ATDDR6HSTR.MergedBits.grpBIT_8\r
+ #define ATDDR6H_BIT ATDDR6H_BIT_8\r
+ \r
+ /*** ATDDR6L - A/D Conversion Result Register 6 Low; 0x0000009D ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte BIT6 :1; /* Bit 6 */\r
+ byte BIT7 :1; /* Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpBIT_6 :2;\r
+ } MergedBits;\r
+ } ATDDR6LSTR;\r
+ #define ATDDR6L _ATDDR6.Overlap_STR.ATDDR6LSTR.Byte\r
+ #define ATDDR6L_BIT6 _ATDDR6.Overlap_STR.ATDDR6LSTR.Bits.BIT6\r
+ #define ATDDR6L_BIT7 _ATDDR6.Overlap_STR.ATDDR6LSTR.Bits.BIT7\r
+ #define ATDDR6L_BIT_6 _ATDDR6.Overlap_STR.ATDDR6LSTR.MergedBits.grpBIT_6\r
+ #define ATDDR6L_BIT ATDDR6L_BIT_6\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word BIT6 :1; /* Bit 6 */\r
+ word BIT7 :1; /* Bit 7 */\r
+ word BIT8 :1; /* Bit 8 */\r
+ word BIT9 :1; /* Bit 9 */\r
+ word BIT10 :1; /* Bit 10 */\r
+ word BIT11 :1; /* Bit 11 */\r
+ word BIT12 :1; /* Bit 12 */\r
+ word BIT13 :1; /* Bit 13 */\r
+ word BIT14 :1; /* Bit 14 */\r
+ word BIT15 :1; /* Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word grpBIT_6 :10;\r
+ } MergedBits;\r
+} ATDDR6STR;\r
+extern volatile ATDDR6STR _ATDDR6 @(REG_BASE + 0x0000009C);\r
+#define ATDDR6 _ATDDR6.Word\r
+#define ATDDR6_BIT6 _ATDDR6.Bits.BIT6\r
+#define ATDDR6_BIT7 _ATDDR6.Bits.BIT7\r
+#define ATDDR6_BIT8 _ATDDR6.Bits.BIT8\r
+#define ATDDR6_BIT9 _ATDDR6.Bits.BIT9\r
+#define ATDDR6_BIT10 _ATDDR6.Bits.BIT10\r
+#define ATDDR6_BIT11 _ATDDR6.Bits.BIT11\r
+#define ATDDR6_BIT12 _ATDDR6.Bits.BIT12\r
+#define ATDDR6_BIT13 _ATDDR6.Bits.BIT13\r
+#define ATDDR6_BIT14 _ATDDR6.Bits.BIT14\r
+#define ATDDR6_BIT15 _ATDDR6.Bits.BIT15\r
+#define ATDDR6_BIT_6 _ATDDR6.MergedBits.grpBIT_6\r
+#define ATDDR6_BIT ATDDR6_BIT_6\r
+\r
+\r
+/*** ATDDR7 - A/D Conversion Result Register 7; 0x0000009E ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** ATDDR7H - A/D Conversion Result Register 7 High; 0x0000009E ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT8 :1; /* Bit 8 */\r
+ byte BIT9 :1; /* Bit 9 */\r
+ byte BIT10 :1; /* Bit 10 */\r
+ byte BIT11 :1; /* Bit 11 */\r
+ byte BIT12 :1; /* Bit 12 */\r
+ byte BIT13 :1; /* Bit 13 */\r
+ byte BIT14 :1; /* Bit 14 */\r
+ byte BIT15 :1; /* Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT_8 :8;\r
+ } MergedBits;\r
+ } ATDDR7HSTR;\r
+ #define ATDDR7H _ATDDR7.Overlap_STR.ATDDR7HSTR.Byte\r
+ #define ATDDR7H_BIT8 _ATDDR7.Overlap_STR.ATDDR7HSTR.Bits.BIT8\r
+ #define ATDDR7H_BIT9 _ATDDR7.Overlap_STR.ATDDR7HSTR.Bits.BIT9\r
+ #define ATDDR7H_BIT10 _ATDDR7.Overlap_STR.ATDDR7HSTR.Bits.BIT10\r
+ #define ATDDR7H_BIT11 _ATDDR7.Overlap_STR.ATDDR7HSTR.Bits.BIT11\r
+ #define ATDDR7H_BIT12 _ATDDR7.Overlap_STR.ATDDR7HSTR.Bits.BIT12\r
+ #define ATDDR7H_BIT13 _ATDDR7.Overlap_STR.ATDDR7HSTR.Bits.BIT13\r
+ #define ATDDR7H_BIT14 _ATDDR7.Overlap_STR.ATDDR7HSTR.Bits.BIT14\r
+ #define ATDDR7H_BIT15 _ATDDR7.Overlap_STR.ATDDR7HSTR.Bits.BIT15\r
+ #define ATDDR7H_BIT_8 _ATDDR7.Overlap_STR.ATDDR7HSTR.MergedBits.grpBIT_8\r
+ #define ATDDR7H_BIT ATDDR7H_BIT_8\r
+ \r
+ /*** ATDDR7L - A/D Conversion Result Register 7 Low; 0x0000009F ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte BIT6 :1; /* Bit 6 */\r
+ byte BIT7 :1; /* Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpBIT_6 :2;\r
+ } MergedBits;\r
+ } ATDDR7LSTR;\r
+ #define ATDDR7L _ATDDR7.Overlap_STR.ATDDR7LSTR.Byte\r
+ #define ATDDR7L_BIT6 _ATDDR7.Overlap_STR.ATDDR7LSTR.Bits.BIT6\r
+ #define ATDDR7L_BIT7 _ATDDR7.Overlap_STR.ATDDR7LSTR.Bits.BIT7\r
+ #define ATDDR7L_BIT_6 _ATDDR7.Overlap_STR.ATDDR7LSTR.MergedBits.grpBIT_6\r
+ #define ATDDR7L_BIT ATDDR7L_BIT_6\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ word BIT6 :1; /* Bit 6 */\r
+ word BIT7 :1; /* Bit 7 */\r
+ word BIT8 :1; /* Bit 8 */\r
+ word BIT9 :1; /* Bit 9 */\r
+ word BIT10 :1; /* Bit 10 */\r
+ word BIT11 :1; /* Bit 11 */\r
+ word BIT12 :1; /* Bit 12 */\r
+ word BIT13 :1; /* Bit 13 */\r
+ word BIT14 :1; /* Bit 14 */\r
+ word BIT15 :1; /* Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ word grpBIT_6 :10;\r
+ } MergedBits;\r
+} ATDDR7STR;\r
+extern volatile ATDDR7STR _ATDDR7 @(REG_BASE + 0x0000009E);\r
+#define ATDDR7 _ATDDR7.Word\r
+#define ATDDR7_BIT6 _ATDDR7.Bits.BIT6\r
+#define ATDDR7_BIT7 _ATDDR7.Bits.BIT7\r
+#define ATDDR7_BIT8 _ATDDR7.Bits.BIT8\r
+#define ATDDR7_BIT9 _ATDDR7.Bits.BIT9\r
+#define ATDDR7_BIT10 _ATDDR7.Bits.BIT10\r
+#define ATDDR7_BIT11 _ATDDR7.Bits.BIT11\r
+#define ATDDR7_BIT12 _ATDDR7.Bits.BIT12\r
+#define ATDDR7_BIT13 _ATDDR7.Bits.BIT13\r
+#define ATDDR7_BIT14 _ATDDR7.Bits.BIT14\r
+#define ATDDR7_BIT15 _ATDDR7.Bits.BIT15\r
+#define ATDDR7_BIT_6 _ATDDR7.MergedBits.grpBIT_6\r
+#define ATDDR7_BIT ATDDR7_BIT_6\r
+\r
+\r
+/*** SCIBD - SCI Baud Rate Register; 0x000000C8 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** SCIBDH - SCI Baud Rate Register High; 0x000000C8 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte SBR8 :1; /* SCI baud rate Bit 8 */\r
+ byte SBR9 :1; /* SCI baud rate Bit 9 */\r
+ byte SBR10 :1; /* SCI baud rate Bit 10 */\r
+ byte SBR11 :1; /* SCI baud rate Bit 11 */\r
+ byte SBR12 :1; /* SCI baud rate Bit 12 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpSBR_8 :5;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+ } SCIBDHSTR;\r
+ #define SCIBDH _SCIBD.Overlap_STR.SCIBDHSTR.Byte\r
+ #define SCIBDH_SBR8 _SCIBD.Overlap_STR.SCIBDHSTR.Bits.SBR8\r
+ #define SCIBDH_SBR9 _SCIBD.Overlap_STR.SCIBDHSTR.Bits.SBR9\r
+ #define SCIBDH_SBR10 _SCIBD.Overlap_STR.SCIBDHSTR.Bits.SBR10\r
+ #define SCIBDH_SBR11 _SCIBD.Overlap_STR.SCIBDHSTR.Bits.SBR11\r
+ #define SCIBDH_SBR12 _SCIBD.Overlap_STR.SCIBDHSTR.Bits.SBR12\r
+ #define SCIBDH_SBR_8 _SCIBD.Overlap_STR.SCIBDHSTR.MergedBits.grpSBR_8\r
+ #define SCIBDH_SBR SCIBDH_SBR_8\r
+ \r
+ /*** SCIBDL - SCI Baud Rate Register Low; 0x000000C9 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte SBR0 :1; /* SCI baud rate Bit 0 */\r
+ byte SBR1 :1; /* SCI baud rate Bit 1 */\r
+ byte SBR2 :1; /* SCI baud rate Bit 2 */\r
+ byte SBR3 :1; /* SCI baud rate Bit 3 */\r
+ byte SBR4 :1; /* SCI baud rate Bit 4 */\r
+ byte SBR5 :1; /* SCI baud rate Bit 5 */\r
+ byte SBR6 :1; /* SCI baud rate Bit 6 */\r
+ byte SBR7 :1; /* SCI baud rate Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpSBR :8;\r
+ } MergedBits;\r
+ } SCIBDLSTR;\r
+ #define SCIBDL _SCIBD.Overlap_STR.SCIBDLSTR.Byte\r
+ #define SCIBDL_SBR0 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR0\r
+ #define SCIBDL_SBR1 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR1\r
+ #define SCIBDL_SBR2 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR2\r
+ #define SCIBDL_SBR3 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR3\r
+ #define SCIBDL_SBR4 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR4\r
+ #define SCIBDL_SBR5 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR5\r
+ #define SCIBDL_SBR6 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR6\r
+ #define SCIBDL_SBR7 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR7\r
+ #define SCIBDL_SBR _SCIBD.Overlap_STR.SCIBDLSTR.MergedBits.grpSBR\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word SBR0 :1; /* SCI baud rate Bit 0 */\r
+ word SBR1 :1; /* SCI baud rate Bit 1 */\r
+ word SBR2 :1; /* SCI baud rate Bit 2 */\r
+ word SBR3 :1; /* SCI baud rate Bit 3 */\r
+ word SBR4 :1; /* SCI baud rate Bit 4 */\r
+ word SBR5 :1; /* SCI baud rate Bit 5 */\r
+ word SBR6 :1; /* SCI baud rate Bit 6 */\r
+ word SBR7 :1; /* SCI baud rate Bit 7 */\r
+ word SBR8 :1; /* SCI baud rate Bit 8 */\r
+ word SBR9 :1; /* SCI baud rate Bit 9 */\r
+ word SBR10 :1; /* SCI baud rate Bit 10 */\r
+ word SBR11 :1; /* SCI baud rate Bit 11 */\r
+ word SBR12 :1; /* SCI baud rate Bit 12 */\r
+ word :1; \r
+ word :1; \r
+ word :1; \r
+ } Bits;\r
+ struct {\r
+ word grpSBR :13;\r
+ word :1;\r
+ word :1;\r
+ word :1;\r
+ } MergedBits;\r
+} SCIBDSTR;\r
+extern volatile SCIBDSTR _SCIBD @(REG_BASE + 0x000000C8);\r
+#define SCIBD _SCIBD.Word\r
+#define SCIBD_SBR0 _SCIBD.Bits.SBR0\r
+#define SCIBD_SBR1 _SCIBD.Bits.SBR1\r
+#define SCIBD_SBR2 _SCIBD.Bits.SBR2\r
+#define SCIBD_SBR3 _SCIBD.Bits.SBR3\r
+#define SCIBD_SBR4 _SCIBD.Bits.SBR4\r
+#define SCIBD_SBR5 _SCIBD.Bits.SBR5\r
+#define SCIBD_SBR6 _SCIBD.Bits.SBR6\r
+#define SCIBD_SBR7 _SCIBD.Bits.SBR7\r
+#define SCIBD_SBR8 _SCIBD.Bits.SBR8\r
+#define SCIBD_SBR9 _SCIBD.Bits.SBR9\r
+#define SCIBD_SBR10 _SCIBD.Bits.SBR10\r
+#define SCIBD_SBR11 _SCIBD.Bits.SBR11\r
+#define SCIBD_SBR12 _SCIBD.Bits.SBR12\r
+#define SCIBD_SBR _SCIBD.MergedBits.grpSBR\r
+\r
+\r
+/*** PWMCNT01 - PWM Channel Counter 01 Register; 0x000000EC ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** PWMCNT0 - PWM Channel Counter 0 Register; 0x000000EC ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } PWMCNT0STR;\r
+ #define PWMCNT0 _PWMCNT01.Overlap_STR.PWMCNT0STR.Byte\r
+ #define PWMCNT0_BIT _PWMCNT01.Overlap_STR.PWMCNT0STR.MergedBits.grpBIT\r
+ \r
+ /*** PWMCNT1 - PWM Channel Counter 1 Register; 0x000000ED ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } PWMCNT1STR;\r
+ #define PWMCNT1 _PWMCNT01.Overlap_STR.PWMCNT1STR.Byte\r
+ #define PWMCNT1_BIT _PWMCNT01.Overlap_STR.PWMCNT1STR.MergedBits.grpBIT\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word grpBIT :16;\r
+ } MergedBits;\r
+} PWMCNT01STR;\r
+extern volatile PWMCNT01STR _PWMCNT01 @(REG_BASE + 0x000000EC);\r
+#define PWMCNT01 _PWMCNT01.Word\r
+#define PWMCNT01_BIT _PWMCNT01.MergedBits.grpBIT\r
+\r
+\r
+/*** PWMCNT23 - PWM Channel Counter 23 Register; 0x000000EE ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** PWMCNT2 - PWM Channel Counter 2 Register; 0x000000EE ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } PWMCNT2STR;\r
+ #define PWMCNT2 _PWMCNT23.Overlap_STR.PWMCNT2STR.Byte\r
+ #define PWMCNT2_BIT _PWMCNT23.Overlap_STR.PWMCNT2STR.MergedBits.grpBIT\r
+ \r
+ /*** PWMCNT3 - PWM Channel Counter 3 Register; 0x000000EF ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } PWMCNT3STR;\r
+ #define PWMCNT3 _PWMCNT23.Overlap_STR.PWMCNT3STR.Byte\r
+ #define PWMCNT3_BIT _PWMCNT23.Overlap_STR.PWMCNT3STR.MergedBits.grpBIT\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word grpBIT :16;\r
+ } MergedBits;\r
+} PWMCNT23STR;\r
+extern volatile PWMCNT23STR _PWMCNT23 @(REG_BASE + 0x000000EE);\r
+#define PWMCNT23 _PWMCNT23.Word\r
+#define PWMCNT23_BIT _PWMCNT23.MergedBits.grpBIT\r
+\r
+\r
+/*** PWMCNT45 - PWM Channel Counter 45 Register; 0x000000F0 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** PWMCNT4 - PWM Channel Counter 4 Register; 0x000000F0 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } PWMCNT4STR;\r
+ #define PWMCNT4 _PWMCNT45.Overlap_STR.PWMCNT4STR.Byte\r
+ #define PWMCNT4_BIT _PWMCNT45.Overlap_STR.PWMCNT4STR.MergedBits.grpBIT\r
+ \r
+ /*** PWMCNT5 - PWM Channel Counter 5 Register; 0x000000F1 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } PWMCNT5STR;\r
+ #define PWMCNT5 _PWMCNT45.Overlap_STR.PWMCNT5STR.Byte\r
+ #define PWMCNT5_BIT _PWMCNT45.Overlap_STR.PWMCNT5STR.MergedBits.grpBIT\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word grpBIT :16;\r
+ } MergedBits;\r
+} PWMCNT45STR;\r
+extern volatile PWMCNT45STR _PWMCNT45 @(REG_BASE + 0x000000F0);\r
+#define PWMCNT45 _PWMCNT45.Word\r
+#define PWMCNT45_BIT _PWMCNT45.MergedBits.grpBIT\r
+\r
+\r
+/*** PWMPER01 - PWM Channel Period 01 Register; 0x000000F2 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** PWMPER0 - PWM Channel Period 0 Register; 0x000000F2 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } PWMPER0STR;\r
+ #define PWMPER0 _PWMPER01.Overlap_STR.PWMPER0STR.Byte\r
+ #define PWMPER0_BIT _PWMPER01.Overlap_STR.PWMPER0STR.MergedBits.grpBIT\r
+ \r
+ /*** PWMPER1 - PWM Channel Period 1 Register; 0x000000F3 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } PWMPER1STR;\r
+ #define PWMPER1 _PWMPER01.Overlap_STR.PWMPER1STR.Byte\r
+ #define PWMPER1_BIT _PWMPER01.Overlap_STR.PWMPER1STR.MergedBits.grpBIT\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word grpBIT :16;\r
+ } MergedBits;\r
+} PWMPER01STR;\r
+extern volatile PWMPER01STR _PWMPER01 @(REG_BASE + 0x000000F2);\r
+#define PWMPER01 _PWMPER01.Word\r
+#define PWMPER01_BIT _PWMPER01.MergedBits.grpBIT\r
+\r
+\r
+/*** PWMPER23 - PWM Channel Period 23 Register; 0x000000F4 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** PWMPER2 - PWM Channel Period 2 Register; 0x000000F4 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } PWMPER2STR;\r
+ #define PWMPER2 _PWMPER23.Overlap_STR.PWMPER2STR.Byte\r
+ #define PWMPER2_BIT _PWMPER23.Overlap_STR.PWMPER2STR.MergedBits.grpBIT\r
+ \r
+ /*** PWMPER3 - PWM Channel Period 3 Register; 0x000000F5 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } PWMPER3STR;\r
+ #define PWMPER3 _PWMPER23.Overlap_STR.PWMPER3STR.Byte\r
+ #define PWMPER3_BIT _PWMPER23.Overlap_STR.PWMPER3STR.MergedBits.grpBIT\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word grpBIT :16;\r
+ } MergedBits;\r
+} PWMPER23STR;\r
+extern volatile PWMPER23STR _PWMPER23 @(REG_BASE + 0x000000F4);\r
+#define PWMPER23 _PWMPER23.Word\r
+#define PWMPER23_BIT _PWMPER23.MergedBits.grpBIT\r
+\r
+\r
+/*** PWMPER45 - PWM Channel Period 45 Register; 0x000000F6 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** PWMPER4 - PWM Channel Period 4 Register; 0x000000F6 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } PWMPER4STR;\r
+ #define PWMPER4 _PWMPER45.Overlap_STR.PWMPER4STR.Byte\r
+ #define PWMPER4_BIT _PWMPER45.Overlap_STR.PWMPER4STR.MergedBits.grpBIT\r
+ \r
+ /*** PWMPER5 - PWM Channel Period 5 Register; 0x000000F7 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } PWMPER5STR;\r
+ #define PWMPER5 _PWMPER45.Overlap_STR.PWMPER5STR.Byte\r
+ #define PWMPER5_BIT _PWMPER45.Overlap_STR.PWMPER5STR.MergedBits.grpBIT\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word grpBIT :16;\r
+ } MergedBits;\r
+} PWMPER45STR;\r
+extern volatile PWMPER45STR _PWMPER45 @(REG_BASE + 0x000000F6);\r
+#define PWMPER45 _PWMPER45.Word\r
+#define PWMPER45_BIT _PWMPER45.MergedBits.grpBIT\r
+\r
+\r
+/*** PWMDTY01 - PWM Channel Duty 01 Register; 0x000000F8 ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** PWMDTY0 - PWM Channel Duty 0 Register; 0x000000F8 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } PWMDTY0STR;\r
+ #define PWMDTY0 _PWMDTY01.Overlap_STR.PWMDTY0STR.Byte\r
+ #define PWMDTY0_BIT _PWMDTY01.Overlap_STR.PWMDTY0STR.MergedBits.grpBIT\r
+ \r
+ /*** PWMDTY1 - PWM Channel Duty 1 Register; 0x000000F9 ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } PWMDTY1STR;\r
+ #define PWMDTY1 _PWMDTY01.Overlap_STR.PWMDTY1STR.Byte\r
+ #define PWMDTY1_BIT _PWMDTY01.Overlap_STR.PWMDTY1STR.MergedBits.grpBIT\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word grpBIT :16;\r
+ } MergedBits;\r
+} PWMDTY01STR;\r
+extern volatile PWMDTY01STR _PWMDTY01 @(REG_BASE + 0x000000F8);\r
+#define PWMDTY01 _PWMDTY01.Word\r
+#define PWMDTY01_BIT _PWMDTY01.MergedBits.grpBIT\r
+\r
+\r
+/*** PWMDTY23 - PWM Channel Duty 23 Register; 0x000000FA ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** PWMDTY2 - PWM Channel Duty 2 Register; 0x000000FA ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } PWMDTY2STR;\r
+ #define PWMDTY2 _PWMDTY23.Overlap_STR.PWMDTY2STR.Byte\r
+ #define PWMDTY2_BIT _PWMDTY23.Overlap_STR.PWMDTY2STR.MergedBits.grpBIT\r
+ \r
+ /*** PWMDTY3 - PWM Channel Duty 3 Register; 0x000000FB ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } PWMDTY3STR;\r
+ #define PWMDTY3 _PWMDTY23.Overlap_STR.PWMDTY3STR.Byte\r
+ #define PWMDTY3_BIT _PWMDTY23.Overlap_STR.PWMDTY3STR.MergedBits.grpBIT\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word grpBIT :16;\r
+ } MergedBits;\r
+} PWMDTY23STR;\r
+extern volatile PWMDTY23STR _PWMDTY23 @(REG_BASE + 0x000000FA);\r
+#define PWMDTY23 _PWMDTY23.Word\r
+#define PWMDTY23_BIT _PWMDTY23.MergedBits.grpBIT\r
+\r
+\r
+/*** PWMDTY45 - PWM Channel Duty 45 Register; 0x000000FC ***/\r
+typedef union {\r
+ word Word;\r
+ /* Overlapped registers: */\r
+ struct {\r
+ /*** PWMDTY4 - PWM Channel Duty 4 Register; 0x000000FC ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } PWMDTY4STR;\r
+ #define PWMDTY4 _PWMDTY45.Overlap_STR.PWMDTY4STR.Byte\r
+ #define PWMDTY4_BIT _PWMDTY45.Overlap_STR.PWMDTY4STR.MergedBits.grpBIT\r
+ \r
+ /*** PWMDTY5 - PWM Channel Duty 5 Register; 0x000000FD ***/\r
+ union {\r
+ byte Byte;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+ } PWMDTY5STR;\r
+ #define PWMDTY5 _PWMDTY45.Overlap_STR.PWMDTY5STR.Byte\r
+ #define PWMDTY5_BIT _PWMDTY45.Overlap_STR.PWMDTY5STR.MergedBits.grpBIT\r
+ \r
+ } Overlap_STR;\r
+\r
+ struct {\r
+ word grpBIT :16;\r
+ } MergedBits;\r
+} PWMDTY45STR;\r
+extern volatile PWMDTY45STR _PWMDTY45 @(REG_BASE + 0x000000FC);\r
+#define PWMDTY45 _PWMDTY45.Word\r
+#define PWMDTY45_BIT _PWMDTY45.MergedBits.grpBIT\r
+\r
+\r
+/*** PORTE - Port E Register; 0x00000008 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* Port E Bit 0 */\r
+ byte BIT1 :1; /* Port E Bit 1 */\r
+ byte BIT2 :1; /* Port E Bit 2 */\r
+ byte BIT3 :1; /* Port E Bit 3 */\r
+ byte BIT4 :1; /* Port E Bit 4 */\r
+ byte BIT5 :1; /* Port E Bit 5 */\r
+ byte BIT6 :1; /* Port E Bit 6 */\r
+ byte BIT7 :1; /* Port E Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+} PORTESTR;\r
+extern volatile PORTESTR _PORTE @(REG_BASE + 0x00000008);\r
+#define PORTE _PORTE.Byte\r
+#define PORTE_BIT0 _PORTE.Bits.BIT0\r
+#define PORTE_BIT1 _PORTE.Bits.BIT1\r
+#define PORTE_BIT2 _PORTE.Bits.BIT2\r
+#define PORTE_BIT3 _PORTE.Bits.BIT3\r
+#define PORTE_BIT4 _PORTE.Bits.BIT4\r
+#define PORTE_BIT5 _PORTE.Bits.BIT5\r
+#define PORTE_BIT6 _PORTE.Bits.BIT6\r
+#define PORTE_BIT7 _PORTE.Bits.BIT7\r
+#define PORTE_BIT _PORTE.MergedBits.grpBIT\r
+\r
+\r
+/*** DDRE - Port E Data Direction Register; 0x00000009 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte BIT2 :1; /* Data Direction Port A Bit 2 */\r
+ byte BIT3 :1; /* Data Direction Port A Bit 3 */\r
+ byte BIT4 :1; /* Data Direction Port A Bit 4 */\r
+ byte BIT5 :1; /* Data Direction Port A Bit 5 */\r
+ byte BIT6 :1; /* Data Direction Port A Bit 6 */\r
+ byte BIT7 :1; /* Data Direction Port A Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte grpBIT_2 :6;\r
+ } MergedBits;\r
+} DDRESTR;\r
+extern volatile DDRESTR _DDRE @(REG_BASE + 0x00000009);\r
+#define DDRE _DDRE.Byte\r
+#define DDRE_BIT2 _DDRE.Bits.BIT2\r
+#define DDRE_BIT3 _DDRE.Bits.BIT3\r
+#define DDRE_BIT4 _DDRE.Bits.BIT4\r
+#define DDRE_BIT5 _DDRE.Bits.BIT5\r
+#define DDRE_BIT6 _DDRE.Bits.BIT6\r
+#define DDRE_BIT7 _DDRE.Bits.BIT7\r
+#define DDRE_BIT_2 _DDRE.MergedBits.grpBIT_2\r
+#define DDRE_BIT DDRE_BIT_2\r
+\r
+\r
+/*** PEAR - Port E Assignment Register; 0x0000000A ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte RDWE :1; /* Read / Write Enable */\r
+ byte LSTRE :1; /* Low Strobe (LSTRB) Enable */\r
+ byte NECLK :1; /* No External E Clock */\r
+ byte PIPOE :1; /* Pipe Status Signal Output Enable */\r
+ byte :1; \r
+ byte NOACCE :1; /* CPU No Access Output Enable */\r
+ } Bits;\r
+} PEARSTR;\r
+extern volatile PEARSTR _PEAR @(REG_BASE + 0x0000000A);\r
+#define PEAR _PEAR.Byte\r
+#define PEAR_RDWE _PEAR.Bits.RDWE\r
+#define PEAR_LSTRE _PEAR.Bits.LSTRE\r
+#define PEAR_NECLK _PEAR.Bits.NECLK\r
+#define PEAR_PIPOE _PEAR.Bits.PIPOE\r
+#define PEAR_NOACCE _PEAR.Bits.NOACCE\r
+\r
+\r
+/*** MODE - Mode Register; 0x0000000B ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte EME :1; /* Emulate Port E */\r
+ byte EMK :1; /* Emulate Port K */\r
+ byte :1; \r
+ byte IVIS :1; /* Internal Visibility */\r
+ byte :1; \r
+ byte MODA :1; /* Mode Select Bit A */\r
+ byte MODB :1; /* Mode Select Bit B */\r
+ byte MODC :1; /* Mode Select Bit C */\r
+ } Bits;\r
+} MODESTR;\r
+extern volatile MODESTR _MODE @(REG_BASE + 0x0000000B);\r
+#define MODE _MODE.Byte\r
+#define MODE_EME _MODE.Bits.EME\r
+#define MODE_EMK _MODE.Bits.EMK\r
+#define MODE_IVIS _MODE.Bits.IVIS\r
+#define MODE_MODA _MODE.Bits.MODA\r
+#define MODE_MODB _MODE.Bits.MODB\r
+#define MODE_MODC _MODE.Bits.MODC\r
+\r
+\r
+/*** PUCR - Pull-Up Control Register; 0x0000000C ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PUPAE :1; /* Pull-Up Port A Enable */\r
+ byte PUPBE :1; /* Pull-Up Port B Enable */\r
+ byte :1; \r
+ byte :1; \r
+ byte PUPEE :1; /* Pull-Up Port E Enable */\r
+ byte :1; \r
+ byte :1; \r
+ byte PUPKE :1; /* Pull-Up Port K Enable */\r
+ } Bits;\r
+} PUCRSTR;\r
+extern volatile PUCRSTR _PUCR @(REG_BASE + 0x0000000C);\r
+#define PUCR _PUCR.Byte\r
+#define PUCR_PUPAE _PUCR.Bits.PUPAE\r
+#define PUCR_PUPBE _PUCR.Bits.PUPBE\r
+#define PUCR_PUPEE _PUCR.Bits.PUPEE\r
+#define PUCR_PUPKE _PUCR.Bits.PUPKE\r
+\r
+\r
+/*** RDRIV - Reduced Drive of I/O Lines; 0x0000000D ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte RDPA :1; /* Reduced Drive of Port A */\r
+ byte RDPB :1; /* Reduced Drive of Port B */\r
+ byte :1; \r
+ byte :1; \r
+ byte RDPE :1; /* Reduced Drive of Port E */\r
+ byte :1; \r
+ byte :1; \r
+ byte RDPK :1; /* Reduced Drive of Port K */\r
+ } Bits;\r
+} RDRIVSTR;\r
+extern volatile RDRIVSTR _RDRIV @(REG_BASE + 0x0000000D);\r
+#define RDRIV _RDRIV.Byte\r
+#define RDRIV_RDPA _RDRIV.Bits.RDPA\r
+#define RDRIV_RDPB _RDRIV.Bits.RDPB\r
+#define RDRIV_RDPE _RDRIV.Bits.RDPE\r
+#define RDRIV_RDPK _RDRIV.Bits.RDPK\r
+\r
+\r
+/*** EBICTL - External Bus Interface Control; 0x0000000E ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ESTR :1; /* E Stretches */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+} EBICTLSTR;\r
+extern volatile EBICTLSTR _EBICTL @(REG_BASE + 0x0000000E);\r
+#define EBICTL _EBICTL.Byte\r
+#define EBICTL_ESTR _EBICTL.Bits.ESTR\r
+\r
+\r
+/*** INITRM - Initialization of Internal RAM Position Register; 0x00000010 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte RAMHAL :1; /* Internal RAM map alignment */\r
+ byte :1; \r
+ byte :1; \r
+ byte RAM11 :1; /* Internal RAM map position Bit 11 */\r
+ byte RAM12 :1; /* Internal RAM map position Bit 12 */\r
+ byte RAM13 :1; /* Internal RAM map position Bit 13 */\r
+ byte RAM14 :1; /* Internal RAM map position Bit 14 */\r
+ byte RAM15 :1; /* Internal RAM map position Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpRAM_11 :5;\r
+ } MergedBits;\r
+} INITRMSTR;\r
+extern volatile INITRMSTR _INITRM @(REG_BASE + 0x00000010);\r
+#define INITRM _INITRM.Byte\r
+#define INITRM_RAMHAL _INITRM.Bits.RAMHAL\r
+#define INITRM_RAM11 _INITRM.Bits.RAM11\r
+#define INITRM_RAM12 _INITRM.Bits.RAM12\r
+#define INITRM_RAM13 _INITRM.Bits.RAM13\r
+#define INITRM_RAM14 _INITRM.Bits.RAM14\r
+#define INITRM_RAM15 _INITRM.Bits.RAM15\r
+#define INITRM_RAM_11 _INITRM.MergedBits.grpRAM_11\r
+#define INITRM_RAM INITRM_RAM_11\r
+\r
+\r
+/*** INITRG - Initialization of Internal Register Position Register; 0x00000011 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte REG11 :1; /* Internal register map position REG11 */\r
+ byte REG12 :1; /* Internal register map position REG12 */\r
+ byte REG13 :1; /* Internal register map position REG13 */\r
+ byte REG14 :1; /* Internal register map position REG14 */\r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpREG_11 :4;\r
+ byte :1;\r
+ } MergedBits;\r
+} INITRGSTR;\r
+extern volatile INITRGSTR _INITRG @(REG_BASE + 0x00000011);\r
+#define INITRG _INITRG.Byte\r
+#define INITRG_REG11 _INITRG.Bits.REG11\r
+#define INITRG_REG12 _INITRG.Bits.REG12\r
+#define INITRG_REG13 _INITRG.Bits.REG13\r
+#define INITRG_REG14 _INITRG.Bits.REG14\r
+#define INITRG_REG_11 _INITRG.MergedBits.grpREG_11\r
+#define INITRG_REG INITRG_REG_11\r
+\r
+\r
+/*** INITEE - Initialization of Internal EEPROM Position Register; 0x00000012 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte EEON :1; /* Internal EEPROM On */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte EE12 :1; /* Internal EEPROM map position Bit 12 */\r
+ byte EE13 :1; /* Internal EEPROM map position Bit 13 */\r
+ byte EE14 :1; /* Internal EEPROM map position Bit 14 */\r
+ byte EE15 :1; /* Internal EEPROM map position Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpEE_12 :4;\r
+ } MergedBits;\r
+} INITEESTR;\r
+extern volatile INITEESTR _INITEE @(REG_BASE + 0x00000012);\r
+#define INITEE _INITEE.Byte\r
+#define INITEE_EEON _INITEE.Bits.EEON\r
+#define INITEE_EE12 _INITEE.Bits.EE12\r
+#define INITEE_EE13 _INITEE.Bits.EE13\r
+#define INITEE_EE14 _INITEE.Bits.EE14\r
+#define INITEE_EE15 _INITEE.Bits.EE15\r
+#define INITEE_EE_12 _INITEE.MergedBits.grpEE_12\r
+#define INITEE_EE INITEE_EE_12\r
+\r
+\r
+/*** MISC - Miscellaneous Mapping Control Register; 0x00000013 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ROMON :1; /* Enable Flash EEPROM */\r
+ byte ROMHM :1; /* Flash EEPROM only in second half of memory map */\r
+ byte EXSTR0 :1; /* External Access Stretch Bit 0 */\r
+ byte EXSTR1 :1; /* External Access Stretch Bit 1 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte grpEXSTR :2;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} MISCSTR;\r
+extern volatile MISCSTR _MISC @(REG_BASE + 0x00000013);\r
+#define MISC _MISC.Byte\r
+#define MISC_ROMON _MISC.Bits.ROMON\r
+#define MISC_ROMHM _MISC.Bits.ROMHM\r
+#define MISC_EXSTR0 _MISC.Bits.EXSTR0\r
+#define MISC_EXSTR1 _MISC.Bits.EXSTR1\r
+#define MISC_EXSTR _MISC.MergedBits.grpEXSTR\r
+\r
+\r
+/*** MTST0 - MTST0; 0x00000014 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* MTST0 Bit 0 */\r
+ byte BIT1 :1; /* MTST0 Bit 1 */\r
+ byte BIT2 :1; /* MTST0 Bit 2 */\r
+ byte BIT3 :1; /* MTST0 Bit 3 */\r
+ byte BIT4 :1; /* MTST0 Bit 4 */\r
+ byte BIT5 :1; /* MTST0 Bit 5 */\r
+ byte BIT6 :1; /* MTST0 Bit 6 */\r
+ byte BIT7 :1; /* MTST0 Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+} MTST0STR;\r
+extern volatile MTST0STR _MTST0 @(REG_BASE + 0x00000014);\r
+#define MTST0 _MTST0.Byte\r
+#define MTST0_BIT0 _MTST0.Bits.BIT0\r
+#define MTST0_BIT1 _MTST0.Bits.BIT1\r
+#define MTST0_BIT2 _MTST0.Bits.BIT2\r
+#define MTST0_BIT3 _MTST0.Bits.BIT3\r
+#define MTST0_BIT4 _MTST0.Bits.BIT4\r
+#define MTST0_BIT5 _MTST0.Bits.BIT5\r
+#define MTST0_BIT6 _MTST0.Bits.BIT6\r
+#define MTST0_BIT7 _MTST0.Bits.BIT7\r
+#define MTST0_BIT _MTST0.MergedBits.grpBIT\r
+\r
+\r
+/*** ITCR - Interrupt Test Control Register; 0x00000015 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ADR0 :1; /* Test register select Bit 0 */\r
+ byte ADR1 :1; /* Test register select Bit 1 */\r
+ byte ADR2 :1; /* Test register select Bit 2 */\r
+ byte ADR3 :1; /* Test register select Bit 3 */\r
+ byte WRTINT :1; /* Write to the Interrupt Test Registers */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpADR :4;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} ITCRSTR;\r
+extern volatile ITCRSTR _ITCR @(REG_BASE + 0x00000015);\r
+#define ITCR _ITCR.Byte\r
+#define ITCR_ADR0 _ITCR.Bits.ADR0\r
+#define ITCR_ADR1 _ITCR.Bits.ADR1\r
+#define ITCR_ADR2 _ITCR.Bits.ADR2\r
+#define ITCR_ADR3 _ITCR.Bits.ADR3\r
+#define ITCR_WRTINT _ITCR.Bits.WRTINT\r
+#define ITCR_ADR _ITCR.MergedBits.grpADR\r
+\r
+\r
+/*** ITEST - Interrupt Test Register; 0x00000016 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte INT0 :1; /* Interrupt Test Register Bit 0 */\r
+ byte INT2 :1; /* Interrupt Test Register Bit 1 */\r
+ byte INT4 :1; /* Interrupt Test Register Bit 2 */\r
+ byte INT6 :1; /* Interrupt Test Register Bit 3 */\r
+ byte INT8 :1; /* Interrupt Test Register Bit 4 */\r
+ byte INTA :1; /* Interrupt Test Register Bit 5 */\r
+ byte INTC :1; /* Interrupt Test Register Bit 6 */\r
+ byte INTE :1; /* Interrupt Test Register Bit 7 */\r
+ } Bits;\r
+} ITESTSTR;\r
+extern volatile ITESTSTR _ITEST @(REG_BASE + 0x00000016);\r
+#define ITEST _ITEST.Byte\r
+#define ITEST_INT0 _ITEST.Bits.INT0\r
+#define ITEST_INT2 _ITEST.Bits.INT2\r
+#define ITEST_INT4 _ITEST.Bits.INT4\r
+#define ITEST_INT6 _ITEST.Bits.INT6\r
+#define ITEST_INT8 _ITEST.Bits.INT8\r
+#define ITEST_INTA _ITEST.Bits.INTA\r
+#define ITEST_INTC _ITEST.Bits.INTC\r
+#define ITEST_INTE _ITEST.Bits.INTE\r
+\r
+\r
+/*** MTST1 - MTST1; 0x00000017 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* MTST1 Bit 0 */\r
+ byte BIT1 :1; /* MTST1 Bit 1 */\r
+ byte BIT2 :1; /* MTST1 Bit 2 */\r
+ byte BIT3 :1; /* MTST1 Bit 3 */\r
+ byte BIT4 :1; /* MTST1 Bit 4 */\r
+ byte BIT5 :1; /* MTST1 Bit 5 */\r
+ byte BIT6 :1; /* MTST1 Bit 6 */\r
+ byte BIT7 :1; /* MTST1 Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+} MTST1STR;\r
+extern volatile MTST1STR _MTST1 @(REG_BASE + 0x00000017);\r
+#define MTST1 _MTST1.Byte\r
+#define MTST1_BIT0 _MTST1.Bits.BIT0\r
+#define MTST1_BIT1 _MTST1.Bits.BIT1\r
+#define MTST1_BIT2 _MTST1.Bits.BIT2\r
+#define MTST1_BIT3 _MTST1.Bits.BIT3\r
+#define MTST1_BIT4 _MTST1.Bits.BIT4\r
+#define MTST1_BIT5 _MTST1.Bits.BIT5\r
+#define MTST1_BIT6 _MTST1.Bits.BIT6\r
+#define MTST1_BIT7 _MTST1.Bits.BIT7\r
+#define MTST1_BIT _MTST1.MergedBits.grpBIT\r
+\r
+\r
+/*** PARTIDH - Part ID Register High; 0x0000001A ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ID15 :1; /* Part ID Register Bit 15 */\r
+ byte ID14 :1; /* Part ID Register Bit 14 */\r
+ byte ID13 :1; /* Part ID Register Bit 13 */\r
+ byte ID12 :1; /* Part ID Register Bit 12 */\r
+ byte ID11 :1; /* Part ID Register Bit 11 */\r
+ byte ID10 :1; /* Part ID Register Bit 10 */\r
+ byte ID9 :1; /* Part ID Register Bit 9 */\r
+ byte ID8 :1; /* Part ID Register Bit 8 */\r
+ } Bits;\r
+} PARTIDHSTR;\r
+extern volatile PARTIDHSTR _PARTIDH @(REG_BASE + 0x0000001A);\r
+#define PARTIDH _PARTIDH.Byte\r
+#define PARTIDH_ID15 _PARTIDH.Bits.ID15\r
+#define PARTIDH_ID14 _PARTIDH.Bits.ID14\r
+#define PARTIDH_ID13 _PARTIDH.Bits.ID13\r
+#define PARTIDH_ID12 _PARTIDH.Bits.ID12\r
+#define PARTIDH_ID11 _PARTIDH.Bits.ID11\r
+#define PARTIDH_ID10 _PARTIDH.Bits.ID10\r
+#define PARTIDH_ID9 _PARTIDH.Bits.ID9\r
+#define PARTIDH_ID8 _PARTIDH.Bits.ID8\r
+\r
+\r
+/*** PARTIDL - Part ID Register Low; 0x0000001B ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ID0 :1; /* Part ID Register Bit 0 */\r
+ byte ID1 :1; /* Part ID Register Bit 1 */\r
+ byte ID2 :1; /* Part ID Register Bit 2 */\r
+ byte ID3 :1; /* Part ID Register Bit 3 */\r
+ byte ID4 :1; /* Part ID Register Bit 4 */\r
+ byte ID5 :1; /* Part ID Register Bit 5 */\r
+ byte ID6 :1; /* Part ID Register Bit 6 */\r
+ byte ID7 :1; /* Part ID Register Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpID :8;\r
+ } MergedBits;\r
+} PARTIDLSTR;\r
+extern volatile PARTIDLSTR _PARTIDL @(REG_BASE + 0x0000001B);\r
+#define PARTIDL _PARTIDL.Byte\r
+#define PARTIDL_ID0 _PARTIDL.Bits.ID0\r
+#define PARTIDL_ID1 _PARTIDL.Bits.ID1\r
+#define PARTIDL_ID2 _PARTIDL.Bits.ID2\r
+#define PARTIDL_ID3 _PARTIDL.Bits.ID3\r
+#define PARTIDL_ID4 _PARTIDL.Bits.ID4\r
+#define PARTIDL_ID5 _PARTIDL.Bits.ID5\r
+#define PARTIDL_ID6 _PARTIDL.Bits.ID6\r
+#define PARTIDL_ID7 _PARTIDL.Bits.ID7\r
+#define PARTIDL_ID _PARTIDL.MergedBits.grpID\r
+\r
+\r
+/*** MEMSIZ0 - Memory Size Register Zero; 0x0000001C ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ram_sw0 :1; /* Allocated RAM Memory Space Bit 0 */\r
+ byte ram_sw1 :1; /* Allocated RAM Memory Space Bit 1 */\r
+ byte ram_sw2 :1; /* Allocated RAM Memory Space Bit 2 */\r
+ byte :1; \r
+ byte eep_sw0 :1; /* Allocated EEPROM Memory Space Bit 0 */\r
+ byte eep_sw1 :1; /* Allocated EEPROM Memory Space Bit 1 */\r
+ byte :1; \r
+ byte reg_sw0 :1; /* Allocated System Register Space */\r
+ } Bits;\r
+ struct {\r
+ byte grpram_sw :3;\r
+ byte :1;\r
+ byte grpeep_sw :2;\r
+ byte :1;\r
+ byte grpreg_sw :1;\r
+ } MergedBits;\r
+} MEMSIZ0STR;\r
+extern volatile MEMSIZ0STR _MEMSIZ0 @(REG_BASE + 0x0000001C);\r
+#define MEMSIZ0 _MEMSIZ0.Byte\r
+#define MEMSIZ0_ram_sw0 _MEMSIZ0.Bits.ram_sw0\r
+#define MEMSIZ0_ram_sw1 _MEMSIZ0.Bits.ram_sw1\r
+#define MEMSIZ0_ram_sw2 _MEMSIZ0.Bits.ram_sw2\r
+#define MEMSIZ0_eep_sw0 _MEMSIZ0.Bits.eep_sw0\r
+#define MEMSIZ0_eep_sw1 _MEMSIZ0.Bits.eep_sw1\r
+#define MEMSIZ0_reg_sw0 _MEMSIZ0.Bits.reg_sw0\r
+#define MEMSIZ0_ram_sw _MEMSIZ0.MergedBits.grpram_sw\r
+#define MEMSIZ0_eep_sw _MEMSIZ0.MergedBits.grpeep_sw\r
+\r
+\r
+/*** MEMSIZ1 - Memory Size Register One; 0x0000001D ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte pag_sw0 :1; /* Allocated Off-Chip Memory Options Bit 0 */\r
+ byte pag_sw1 :1; /* Allocated Off-Chip Memory Options Bit 1 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte rom_sw0 :1; /* Allocated Flash EEPROM/ROM Physical Memory Space Bit 0 */\r
+ byte rom_sw1 :1; /* Allocated Flash EEPROM/ROM Physical Memory Space Bit 1 */\r
+ } Bits;\r
+ struct {\r
+ byte grppag_sw :2;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte grprom_sw :2;\r
+ } MergedBits;\r
+} MEMSIZ1STR;\r
+extern volatile MEMSIZ1STR _MEMSIZ1 @(REG_BASE + 0x0000001D);\r
+#define MEMSIZ1 _MEMSIZ1.Byte\r
+#define MEMSIZ1_pag_sw0 _MEMSIZ1.Bits.pag_sw0\r
+#define MEMSIZ1_pag_sw1 _MEMSIZ1.Bits.pag_sw1\r
+#define MEMSIZ1_rom_sw0 _MEMSIZ1.Bits.rom_sw0\r
+#define MEMSIZ1_rom_sw1 _MEMSIZ1.Bits.rom_sw1\r
+#define MEMSIZ1_pag_sw _MEMSIZ1.MergedBits.grppag_sw\r
+#define MEMSIZ1_rom_sw _MEMSIZ1.MergedBits.grprom_sw\r
+\r
+\r
+/*** INTCR - Interrupt Control Register; 0x0000001E ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte IRQEN :1; /* External IRQ Enable */\r
+ byte IRQE :1; /* IRQ Select Edge Sensitive Only */\r
+ } Bits;\r
+} INTCRSTR;\r
+extern volatile INTCRSTR _INTCR @(REG_BASE + 0x0000001E);\r
+#define INTCR _INTCR.Byte\r
+#define INTCR_IRQEN _INTCR.Bits.IRQEN\r
+#define INTCR_IRQE _INTCR.Bits.IRQE\r
+\r
+\r
+/*** HPRIO - Highest Priority I Interrupt; 0x0000001F ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte PSEL1 :1; /* Highest Priority I Interrupt Bit 1 */\r
+ byte PSEL2 :1; /* Highest Priority I Interrupt Bit 2 */\r
+ byte PSEL3 :1; /* Highest Priority I Interrupt Bit 3 */\r
+ byte PSEL4 :1; /* Highest Priority I Interrupt Bit 4 */\r
+ byte PSEL5 :1; /* Highest Priority I Interrupt Bit 5 */\r
+ byte PSEL6 :1; /* Highest Priority I Interrupt Bit 6 */\r
+ byte PSEL7 :1; /* Highest Priority I Interrupt Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte grpPSEL_1 :7;\r
+ } MergedBits;\r
+} HPRIOSTR;\r
+extern volatile HPRIOSTR _HPRIO @(REG_BASE + 0x0000001F);\r
+#define HPRIO _HPRIO.Byte\r
+#define HPRIO_PSEL1 _HPRIO.Bits.PSEL1\r
+#define HPRIO_PSEL2 _HPRIO.Bits.PSEL2\r
+#define HPRIO_PSEL3 _HPRIO.Bits.PSEL3\r
+#define HPRIO_PSEL4 _HPRIO.Bits.PSEL4\r
+#define HPRIO_PSEL5 _HPRIO.Bits.PSEL5\r
+#define HPRIO_PSEL6 _HPRIO.Bits.PSEL6\r
+#define HPRIO_PSEL7 _HPRIO.Bits.PSEL7\r
+#define HPRIO_PSEL_1 _HPRIO.MergedBits.grpPSEL_1\r
+#define HPRIO_PSEL HPRIO_PSEL_1\r
+\r
+\r
+/*** BKPCT0 - Breakpoint Control Register 0; 0x00000028 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte BKTAG :1; /* Breakpoint on Tag */\r
+ byte BKBDM :1; /* Breakpoint Background Debug Mode Enable */\r
+ byte BKFULL :1; /* Full Breakpoint Mode Enable */\r
+ byte BKEN :1; /* Breakpoint Enable */\r
+ } Bits;\r
+} BKPCT0STR;\r
+extern volatile BKPCT0STR _BKPCT0 @(REG_BASE + 0x00000028);\r
+#define BKPCT0 _BKPCT0.Byte\r
+#define BKPCT0_BKTAG _BKPCT0.Bits.BKTAG\r
+#define BKPCT0_BKBDM _BKPCT0.Bits.BKBDM\r
+#define BKPCT0_BKFULL _BKPCT0.Bits.BKFULL\r
+#define BKPCT0_BKEN _BKPCT0.Bits.BKEN\r
+\r
+\r
+/*** BKPCT1 - Breakpoint Control Register 1; 0x00000029 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte BK1RW :1; /* R/W Compare Value 1 */\r
+ byte BK1RWE :1; /* R/W Compare Enable 1 */\r
+ byte BK0RW :1; /* R/W Compare Value 0 */\r
+ byte BK0RWE :1; /* R/W Compare Enable 0 */\r
+ byte BK1MBL :1; /* Breakpoint Mask Low Byte for Second Address */\r
+ byte BK1MBH :1; /* Breakpoint Mask High Byte for Second Address */\r
+ byte BK0MBL :1; /* Breakpoint Mask Low Byte for First Address */\r
+ byte BK0MBH :1; /* Breakpoint Mask High Byte for First Address */\r
+ } Bits;\r
+} BKPCT1STR;\r
+extern volatile BKPCT1STR _BKPCT1 @(REG_BASE + 0x00000029);\r
+#define BKPCT1 _BKPCT1.Byte\r
+#define BKPCT1_BK1RW _BKPCT1.Bits.BK1RW\r
+#define BKPCT1_BK1RWE _BKPCT1.Bits.BK1RWE\r
+#define BKPCT1_BK0RW _BKPCT1.Bits.BK0RW\r
+#define BKPCT1_BK0RWE _BKPCT1.Bits.BK0RWE\r
+#define BKPCT1_BK1MBL _BKPCT1.Bits.BK1MBL\r
+#define BKPCT1_BK1MBH _BKPCT1.Bits.BK1MBH\r
+#define BKPCT1_BK0MBL _BKPCT1.Bits.BK0MBL\r
+#define BKPCT1_BK0MBH _BKPCT1.Bits.BK0MBH\r
+\r
+\r
+/*** BKP0X - First Address Memory Expansion Breakpoint Register; 0x0000002A ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte BK0V0 :1; /* First Address Breakpoint Expansion Address Value Bit 0 */\r
+ byte BK0V1 :1; /* First Address Breakpoint Expansion Address Value Bit 1 */\r
+ byte BK0V2 :1; /* First Address Breakpoint Expansion Address Value Bit 2 */\r
+ byte BK0V3 :1; /* First Address Breakpoint Expansion Address Value Bit 3 */\r
+ byte BK0V4 :1; /* First Address Breakpoint Expansion Address Value Bit 4 */\r
+ byte BK0V5 :1; /* First Address Breakpoint Expansion Address Value Bit 5 */\r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpBK0V :6;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} BKP0XSTR;\r
+extern volatile BKP0XSTR _BKP0X @(REG_BASE + 0x0000002A);\r
+#define BKP0X _BKP0X.Byte\r
+#define BKP0X_BK0V0 _BKP0X.Bits.BK0V0\r
+#define BKP0X_BK0V1 _BKP0X.Bits.BK0V1\r
+#define BKP0X_BK0V2 _BKP0X.Bits.BK0V2\r
+#define BKP0X_BK0V3 _BKP0X.Bits.BK0V3\r
+#define BKP0X_BK0V4 _BKP0X.Bits.BK0V4\r
+#define BKP0X_BK0V5 _BKP0X.Bits.BK0V5\r
+#define BKP0X_BK0V _BKP0X.MergedBits.grpBK0V\r
+\r
+\r
+/*** BKP0H - First Address High Byte Breakpoint Register; 0x0000002B ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT8 :1; /* First Address Breakpoint Register Bit 8 */\r
+ byte BIT9 :1; /* First Address Breakpoint Register Bit 9 */\r
+ byte BIT10 :1; /* First Address Breakpoint Register Bit 10 */\r
+ byte BIT11 :1; /* First Address Breakpoint Register Bit 11 */\r
+ byte BIT12 :1; /* First Address Breakpoint Register Bit 12 */\r
+ byte BIT13 :1; /* First Address Breakpoint Register Bit 13 */\r
+ byte BIT14 :1; /* First Address Breakpoint Register Bit 14 */\r
+ byte BIT15 :1; /* First Address Breakpoint Register Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT_8 :8;\r
+ } MergedBits;\r
+} BKP0HSTR;\r
+extern volatile BKP0HSTR _BKP0H @(REG_BASE + 0x0000002B);\r
+#define BKP0H _BKP0H.Byte\r
+#define BKP0H_BIT8 _BKP0H.Bits.BIT8\r
+#define BKP0H_BIT9 _BKP0H.Bits.BIT9\r
+#define BKP0H_BIT10 _BKP0H.Bits.BIT10\r
+#define BKP0H_BIT11 _BKP0H.Bits.BIT11\r
+#define BKP0H_BIT12 _BKP0H.Bits.BIT12\r
+#define BKP0H_BIT13 _BKP0H.Bits.BIT13\r
+#define BKP0H_BIT14 _BKP0H.Bits.BIT14\r
+#define BKP0H_BIT15 _BKP0H.Bits.BIT15\r
+#define BKP0H_BIT_8 _BKP0H.MergedBits.grpBIT_8\r
+#define BKP0H_BIT BKP0H_BIT_8\r
+\r
+\r
+/*** BKP0L - First Address Low Byte Breakpoint Register; 0x0000002C ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* First Address Breakpoint Register Bit 0 */\r
+ byte BIT1 :1; /* First Address Breakpoint Register Bit 1 */\r
+ byte BIT2 :1; /* First Address Breakpoint Register Bit 2 */\r
+ byte BIT3 :1; /* First Address Breakpoint Register Bit 3 */\r
+ byte BIT4 :1; /* First Address Breakpoint Register Bit 4 */\r
+ byte BIT5 :1; /* First Address Breakpoint Register Bit 5 */\r
+ byte BIT6 :1; /* First Address Breakpoint Register Bit 6 */\r
+ byte BIT7 :1; /* First Address Breakpoint Register Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+} BKP0LSTR;\r
+extern volatile BKP0LSTR _BKP0L @(REG_BASE + 0x0000002C);\r
+#define BKP0L _BKP0L.Byte\r
+#define BKP0L_BIT0 _BKP0L.Bits.BIT0\r
+#define BKP0L_BIT1 _BKP0L.Bits.BIT1\r
+#define BKP0L_BIT2 _BKP0L.Bits.BIT2\r
+#define BKP0L_BIT3 _BKP0L.Bits.BIT3\r
+#define BKP0L_BIT4 _BKP0L.Bits.BIT4\r
+#define BKP0L_BIT5 _BKP0L.Bits.BIT5\r
+#define BKP0L_BIT6 _BKP0L.Bits.BIT6\r
+#define BKP0L_BIT7 _BKP0L.Bits.BIT7\r
+#define BKP0L_BIT _BKP0L.MergedBits.grpBIT\r
+\r
+\r
+/*** BKP1X - Second Address Memory Expansion Breakpoint Register; 0x0000002D ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte BK1V0 :1; /* Second Address Breakpoint Expansion Address Value Bit 0 */\r
+ byte BK1V1 :1; /* Second Address Breakpoint Expansion Address Value Bit 1 */\r
+ byte BK1V2 :1; /* Second Address Breakpoint Expansion Address Value Bit 2 */\r
+ byte BK1V3 :1; /* Second Address Breakpoint Expansion Address Value Bit 3 */\r
+ byte BK1V4 :1; /* Second Address Breakpoint Expansion Address Value Bit 4 */\r
+ byte BK1V5 :1; /* Second Address Breakpoint Expansion Address Value Bit 5 */\r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpBK1V :6;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} BKP1XSTR;\r
+extern volatile BKP1XSTR _BKP1X @(REG_BASE + 0x0000002D);\r
+#define BKP1X _BKP1X.Byte\r
+#define BKP1X_BK1V0 _BKP1X.Bits.BK1V0\r
+#define BKP1X_BK1V1 _BKP1X.Bits.BK1V1\r
+#define BKP1X_BK1V2 _BKP1X.Bits.BK1V2\r
+#define BKP1X_BK1V3 _BKP1X.Bits.BK1V3\r
+#define BKP1X_BK1V4 _BKP1X.Bits.BK1V4\r
+#define BKP1X_BK1V5 _BKP1X.Bits.BK1V5\r
+#define BKP1X_BK1V _BKP1X.MergedBits.grpBK1V\r
+\r
+\r
+/*** BKP1H - Data (Second Address) High Byte Breakpoint Register; 0x0000002E ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT8 :1; /* Data (Second Address) Breakpoint Register Bit 8 */\r
+ byte BIT9 :1; /* Data (Second Address) Breakpoint Register Bit 9 */\r
+ byte BIT10 :1; /* Data (Second Address) Breakpoint Register Bit 10 */\r
+ byte BIT11 :1; /* Data (Second Address) Breakpoint Register Bit 11 */\r
+ byte BIT12 :1; /* Data (Second Address) Breakpoint Register Bit 12 */\r
+ byte BIT13 :1; /* Data (Second Address) Breakpoint Register Bit 13 */\r
+ byte BIT14 :1; /* Data (Second Address) Breakpoint Register Bit 14 */\r
+ byte BIT15 :1; /* Data (Second Address) Breakpoint Register Bit 15 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT_8 :8;\r
+ } MergedBits;\r
+} BKP1HSTR;\r
+extern volatile BKP1HSTR _BKP1H @(REG_BASE + 0x0000002E);\r
+#define BKP1H _BKP1H.Byte\r
+#define BKP1H_BIT8 _BKP1H.Bits.BIT8\r
+#define BKP1H_BIT9 _BKP1H.Bits.BIT9\r
+#define BKP1H_BIT10 _BKP1H.Bits.BIT10\r
+#define BKP1H_BIT11 _BKP1H.Bits.BIT11\r
+#define BKP1H_BIT12 _BKP1H.Bits.BIT12\r
+#define BKP1H_BIT13 _BKP1H.Bits.BIT13\r
+#define BKP1H_BIT14 _BKP1H.Bits.BIT14\r
+#define BKP1H_BIT15 _BKP1H.Bits.BIT15\r
+#define BKP1H_BIT_8 _BKP1H.MergedBits.grpBIT_8\r
+#define BKP1H_BIT BKP1H_BIT_8\r
+\r
+\r
+/*** BKP1L - Data (Second Address) Low Byte Breakpoint Register; 0x0000002F ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* Data (Second Address) Breakpoint Register Bit 0 */\r
+ byte BIT1 :1; /* Data (Second Address) Breakpoint Register Bit 1 */\r
+ byte BIT2 :1; /* Data (Second Address) Breakpoint Register Bit 2 */\r
+ byte BIT3 :1; /* Data (Second Address) Breakpoint Register Bit 3 */\r
+ byte BIT4 :1; /* Data (Second Address) Breakpoint Register Bit 4 */\r
+ byte BIT5 :1; /* Data (Second Address) Breakpoint Register Bit 5 */\r
+ byte BIT6 :1; /* Data (Second Address) Breakpoint Register Bit 6 */\r
+ byte BIT7 :1; /* Data (Second Address) Breakpoint Register Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+} BKP1LSTR;\r
+extern volatile BKP1LSTR _BKP1L @(REG_BASE + 0x0000002F);\r
+#define BKP1L _BKP1L.Byte\r
+#define BKP1L_BIT0 _BKP1L.Bits.BIT0\r
+#define BKP1L_BIT1 _BKP1L.Bits.BIT1\r
+#define BKP1L_BIT2 _BKP1L.Bits.BIT2\r
+#define BKP1L_BIT3 _BKP1L.Bits.BIT3\r
+#define BKP1L_BIT4 _BKP1L.Bits.BIT4\r
+#define BKP1L_BIT5 _BKP1L.Bits.BIT5\r
+#define BKP1L_BIT6 _BKP1L.Bits.BIT6\r
+#define BKP1L_BIT7 _BKP1L.Bits.BIT7\r
+#define BKP1L_BIT _BKP1L.MergedBits.grpBIT\r
+\r
+\r
+/*** PPAGE - Page Index Register; 0x00000030 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PIX0 :1; /* Page Index Register Bit 0 */\r
+ byte PIX1 :1; /* Page Index Register Bit 1 */\r
+ byte PIX2 :1; /* Page Index Register Bit 2 */\r
+ byte PIX3 :1; /* Page Index Register Bit 3 */\r
+ byte PIX4 :1; /* Page Index Register Bit 4 */\r
+ byte PIX5 :1; /* Page Index Register Bit 5 */\r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpPIX :6;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} PPAGESTR;\r
+extern volatile PPAGESTR _PPAGE @(REG_BASE + 0x00000030);\r
+#define PPAGE _PPAGE.Byte\r
+#define PPAGE_PIX0 _PPAGE.Bits.PIX0\r
+#define PPAGE_PIX1 _PPAGE.Bits.PIX1\r
+#define PPAGE_PIX2 _PPAGE.Bits.PIX2\r
+#define PPAGE_PIX3 _PPAGE.Bits.PIX3\r
+#define PPAGE_PIX4 _PPAGE.Bits.PIX4\r
+#define PPAGE_PIX5 _PPAGE.Bits.PIX5\r
+#define PPAGE_PIX _PPAGE.MergedBits.grpPIX\r
+\r
+\r
+/*** PORTK - Port K Data Register; 0x00000032 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* Port K Bit 0, XAB14 */\r
+ byte BIT1 :1; /* Port K Bit 1, XAB15 */\r
+ byte BIT2 :1; /* Port K Bit 2, XAB16 */\r
+ byte BIT3 :1; /* Port K Bit 3, XAB17 */\r
+ byte BIT4 :1; /* Port K Bit 4, XAB18 */\r
+ byte BIT5 :1; /* Port K Bit 5, XAB19 */\r
+ byte BIT6 :1; /* Port K Bit 6 */\r
+ byte BIT7 :1; /* Port K Bit 7, ECS/ROMONE */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+} PORTKSTR;\r
+extern volatile PORTKSTR _PORTK @(REG_BASE + 0x00000032);\r
+#define PORTK _PORTK.Byte\r
+#define PORTK_BIT0 _PORTK.Bits.BIT0\r
+#define PORTK_BIT1 _PORTK.Bits.BIT1\r
+#define PORTK_BIT2 _PORTK.Bits.BIT2\r
+#define PORTK_BIT3 _PORTK.Bits.BIT3\r
+#define PORTK_BIT4 _PORTK.Bits.BIT4\r
+#define PORTK_BIT5 _PORTK.Bits.BIT5\r
+#define PORTK_BIT6 _PORTK.Bits.BIT6\r
+#define PORTK_BIT7 _PORTK.Bits.BIT7\r
+#define PORTK_BIT _PORTK.MergedBits.grpBIT\r
+\r
+\r
+/*** DDRK - Port K Data Direction Register; 0x00000033 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DDK0 :1; /* Port K Data Direction Bit 0 */\r
+ byte DDK1 :1; /* Port K Data Direction Bit 1 */\r
+ byte DDK2 :1; /* Port K Data Direction Bit 2 */\r
+ byte DDK3 :1; /* Port K Data Direction Bit 3 */\r
+ byte DDK4 :1; /* Port K Data Direction Bit 4 */\r
+ byte DDK5 :1; /* Port K Data Direction Bit 5 */\r
+ byte :1; \r
+ byte DDK7 :1; /* Port K Data Direction Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDDK :6;\r
+ byte :1;\r
+ byte grpDDK_7 :1;\r
+ } MergedBits;\r
+} DDRKSTR;\r
+extern volatile DDRKSTR _DDRK @(REG_BASE + 0x00000033);\r
+#define DDRK _DDRK.Byte\r
+#define DDRK_DDK0 _DDRK.Bits.DDK0\r
+#define DDRK_DDK1 _DDRK.Bits.DDK1\r
+#define DDRK_DDK2 _DDRK.Bits.DDK2\r
+#define DDRK_DDK3 _DDRK.Bits.DDK3\r
+#define DDRK_DDK4 _DDRK.Bits.DDK4\r
+#define DDRK_DDK5 _DDRK.Bits.DDK5\r
+#define DDRK_DDK7 _DDRK.Bits.DDK7\r
+#define DDRK_DDK _DDRK.MergedBits.grpDDK\r
+\r
+\r
+/*** SYNR - CRG Synthesizer Register; 0x00000034 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte SYN0 :1; /* CRG Synthesizer Bit 0 */\r
+ byte SYN1 :1; /* CRG Synthesizer Bit 1 */\r
+ byte SYN2 :1; /* CRG Synthesizer Bit 2 */\r
+ byte SYN3 :1; /* CRG Synthesizer Bit 3 */\r
+ byte SYN4 :1; /* CRG Synthesizer Bit 4 */\r
+ byte SYN5 :1; /* CRG Synthesizer Bit 5 */\r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpSYN :6;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} SYNRSTR;\r
+extern volatile SYNRSTR _SYNR @(REG_BASE + 0x00000034);\r
+#define SYNR _SYNR.Byte\r
+#define SYNR_SYN0 _SYNR.Bits.SYN0\r
+#define SYNR_SYN1 _SYNR.Bits.SYN1\r
+#define SYNR_SYN2 _SYNR.Bits.SYN2\r
+#define SYNR_SYN3 _SYNR.Bits.SYN3\r
+#define SYNR_SYN4 _SYNR.Bits.SYN4\r
+#define SYNR_SYN5 _SYNR.Bits.SYN5\r
+#define SYNR_SYN _SYNR.MergedBits.grpSYN\r
+\r
+\r
+/*** REFDV - CRG Reference Divider Register; 0x00000035 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte REFDV0 :1; /* CRG Reference Divider Bit 0 */\r
+ byte REFDV1 :1; /* CRG Reference Divider Bit 1 */\r
+ byte REFDV2 :1; /* CRG Reference Divider Bit 2 */\r
+ byte REFDV3 :1; /* CRG Reference Divider Bit 3 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpREFDV :4;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} REFDVSTR;\r
+extern volatile REFDVSTR _REFDV @(REG_BASE + 0x00000035);\r
+#define REFDV _REFDV.Byte\r
+#define REFDV_REFDV0 _REFDV.Bits.REFDV0\r
+#define REFDV_REFDV1 _REFDV.Bits.REFDV1\r
+#define REFDV_REFDV2 _REFDV.Bits.REFDV2\r
+#define REFDV_REFDV3 _REFDV.Bits.REFDV3\r
+#define REFDV_REFDV _REFDV.MergedBits.grpREFDV\r
+\r
+\r
+/*** CTFLG - CRG Test Flags Register; 0x00000036 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte TOUT0 :1; /* CRG Test Flags Bit 0 */\r
+ byte TOUT1 :1; /* CRG Test Flags Bit 1 */\r
+ byte TOUT2 :1; /* CRG Test Flags Bit 2 */\r
+ byte TOUT3 :1; /* CRG Test Flags Bit 3 */\r
+ byte TOUT4 :1; /* CRG Test Flags Bit 4 */\r
+ byte TOUT5 :1; /* CRG Test Flags Bit 5 */\r
+ byte TOUT6 :1; /* CRG Test Flags Bit 6 */\r
+ byte TOUT7 :1; /* CRG Test Flags Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpTOUT :8;\r
+ } MergedBits;\r
+} CTFLGSTR;\r
+extern volatile CTFLGSTR _CTFLG @(REG_BASE + 0x00000036);\r
+#define CTFLG _CTFLG.Byte\r
+#define CTFLG_TOUT0 _CTFLG.Bits.TOUT0\r
+#define CTFLG_TOUT1 _CTFLG.Bits.TOUT1\r
+#define CTFLG_TOUT2 _CTFLG.Bits.TOUT2\r
+#define CTFLG_TOUT3 _CTFLG.Bits.TOUT3\r
+#define CTFLG_TOUT4 _CTFLG.Bits.TOUT4\r
+#define CTFLG_TOUT5 _CTFLG.Bits.TOUT5\r
+#define CTFLG_TOUT6 _CTFLG.Bits.TOUT6\r
+#define CTFLG_TOUT7 _CTFLG.Bits.TOUT7\r
+#define CTFLG_TOUT _CTFLG.MergedBits.grpTOUT\r
+\r
+\r
+/*** CRGFLG - CRG Flags Register; 0x00000037 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte SCM :1; /* Self-clock mode Status */\r
+ byte SCMIF :1; /* Self-clock mode Interrupt Flag */\r
+ byte TRACK :1; /* Track Status */\r
+ byte LOCK :1; /* Lock Status */\r
+ byte LOCKIF :1; /* PLL Lock Interrupt Flag */\r
+ byte :1; \r
+ byte PORF :1; /* Power on Reset Flag */\r
+ byte RTIF :1; /* Real Time Interrupt Flag */\r
+ } Bits;\r
+} CRGFLGSTR;\r
+extern volatile CRGFLGSTR _CRGFLG @(REG_BASE + 0x00000037);\r
+#define CRGFLG _CRGFLG.Byte\r
+#define CRGFLG_SCM _CRGFLG.Bits.SCM\r
+#define CRGFLG_SCMIF _CRGFLG.Bits.SCMIF\r
+#define CRGFLG_TRACK _CRGFLG.Bits.TRACK\r
+#define CRGFLG_LOCK _CRGFLG.Bits.LOCK\r
+#define CRGFLG_LOCKIF _CRGFLG.Bits.LOCKIF\r
+#define CRGFLG_PORF _CRGFLG.Bits.PORF\r
+#define CRGFLG_RTIF _CRGFLG.Bits.RTIF\r
+\r
+\r
+/*** CRGINT - CRG Interrupt Enable Register; 0x00000038 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte SCMIE :1; /* Self-clock mode Interrupt Enable */\r
+ byte :1; \r
+ byte :1; \r
+ byte LOCKIE :1; /* Lock Interrupt Enable */\r
+ byte :1; \r
+ byte :1; \r
+ byte RTIE :1; /* Real Time Interrupt Enable */\r
+ } Bits;\r
+} CRGINTSTR;\r
+extern volatile CRGINTSTR _CRGINT @(REG_BASE + 0x00000038);\r
+#define CRGINT _CRGINT.Byte\r
+#define CRGINT_SCMIE _CRGINT.Bits.SCMIE\r
+#define CRGINT_LOCKIE _CRGINT.Bits.LOCKIE\r
+#define CRGINT_RTIE _CRGINT.Bits.RTIE\r
+\r
+\r
+/*** CLKSEL - CRG Clock Select Register; 0x00000039 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte COPWAI :1; /* COP stops in WAIT mode */\r
+ byte RTIWAI :1; /* RTI stops in WAIT mode */\r
+ byte CWAI :1; /* CLK24 and CLK23 stop in WAIT mode */\r
+ byte PLLWAI :1; /* PLL stops in WAIT mode */\r
+ byte ROAWAI :1; /* Reduced Oscillator Amplitude in WAIT mode */\r
+ byte SYSWAI :1; /* System clocks stop in WAIT mode */\r
+ byte PSTP :1; /* Pseudo Stop */\r
+ byte PLLSEL :1; /* PLL selected for system clock */\r
+ } Bits;\r
+} CLKSELSTR;\r
+extern volatile CLKSELSTR _CLKSEL @(REG_BASE + 0x00000039);\r
+#define CLKSEL _CLKSEL.Byte\r
+#define CLKSEL_COPWAI _CLKSEL.Bits.COPWAI\r
+#define CLKSEL_RTIWAI _CLKSEL.Bits.RTIWAI\r
+#define CLKSEL_CWAI _CLKSEL.Bits.CWAI\r
+#define CLKSEL_PLLWAI _CLKSEL.Bits.PLLWAI\r
+#define CLKSEL_ROAWAI _CLKSEL.Bits.ROAWAI\r
+#define CLKSEL_SYSWAI _CLKSEL.Bits.SYSWAI\r
+#define CLKSEL_PSTP _CLKSEL.Bits.PSTP\r
+#define CLKSEL_PLLSEL _CLKSEL.Bits.PLLSEL\r
+\r
+\r
+/*** PLLCTL - CRG PLL Control Register; 0x0000003A ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte SCME :1; /* Self-clock mode enable */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte ACQ :1; /* Acquisition */\r
+ byte AUTO :1; /* Automatic Bandwidth Control */\r
+ byte PLLON :1; /* Phase Lock Loop On */\r
+ byte CME :1; /* Crystal Monitor Enable */\r
+ } Bits;\r
+} PLLCTLSTR;\r
+extern volatile PLLCTLSTR _PLLCTL @(REG_BASE + 0x0000003A);\r
+#define PLLCTL _PLLCTL.Byte\r
+#define PLLCTL_SCME _PLLCTL.Bits.SCME\r
+#define PLLCTL_ACQ _PLLCTL.Bits.ACQ\r
+#define PLLCTL_AUTO _PLLCTL.Bits.AUTO\r
+#define PLLCTL_PLLON _PLLCTL.Bits.PLLON\r
+#define PLLCTL_CME _PLLCTL.Bits.CME\r
+\r
+\r
+/*** RTICTL - CRG RTI Control Register; 0x0000003B ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte RTR0 :1; /* Real Time Interrupt Modulus Counter Select */\r
+ byte RTR1 :1; /* Real Time Interrupt Modulus Counter Select */\r
+ byte RTR2 :1; /* Real Time Interrupt Modulus Counter Select */\r
+ byte RTR3 :1; /* Real Time Interrupt Modulus Counter Select */\r
+ byte RTR4 :1; /* Real Time Interrupt Prescale Rate Select */\r
+ byte RTR5 :1; /* Real Time Interrupt Prescale Rate Select */\r
+ byte RTR6 :1; /* Real Time Interrupt Prescale Rate Select */\r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpRTR :7;\r
+ byte :1;\r
+ } MergedBits;\r
+} RTICTLSTR;\r
+extern volatile RTICTLSTR _RTICTL @(REG_BASE + 0x0000003B);\r
+#define RTICTL _RTICTL.Byte\r
+#define RTICTL_RTR0 _RTICTL.Bits.RTR0\r
+#define RTICTL_RTR1 _RTICTL.Bits.RTR1\r
+#define RTICTL_RTR2 _RTICTL.Bits.RTR2\r
+#define RTICTL_RTR3 _RTICTL.Bits.RTR3\r
+#define RTICTL_RTR4 _RTICTL.Bits.RTR4\r
+#define RTICTL_RTR5 _RTICTL.Bits.RTR5\r
+#define RTICTL_RTR6 _RTICTL.Bits.RTR6\r
+#define RTICTL_RTR _RTICTL.MergedBits.grpRTR\r
+\r
+\r
+/*** COPCTL - CRG COP Control Register; 0x0000003C ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte CR0 :1; /* COP Watchdog Timer Rate select Bit 0 */\r
+ byte CR1 :1; /* COP Watchdog Timer Rate select Bit 1 */\r
+ byte CR2 :1; /* COP Watchdog Timer Rate select Bit 2 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte RSBCK :1; /* COP and RTI stop in Active BDM mode Bit */\r
+ byte WCOP :1; /* Window COP mode */\r
+ } Bits;\r
+ struct {\r
+ byte grpCR :3;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} COPCTLSTR;\r
+extern volatile COPCTLSTR _COPCTL @(REG_BASE + 0x0000003C);\r
+#define COPCTL _COPCTL.Byte\r
+#define COPCTL_CR0 _COPCTL.Bits.CR0\r
+#define COPCTL_CR1 _COPCTL.Bits.CR1\r
+#define COPCTL_CR2 _COPCTL.Bits.CR2\r
+#define COPCTL_RSBCK _COPCTL.Bits.RSBCK\r
+#define COPCTL_WCOP _COPCTL.Bits.WCOP\r
+#define COPCTL_CR _COPCTL.MergedBits.grpCR\r
+\r
+\r
+/*** CTCTL - CRG Test Control Register; 0x0000003E ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte TCTL0 :1; /* CRG Test Control Bit 0 */\r
+ byte TCTL1 :1; /* CRG Test Control Bit 1 */\r
+ byte TCTL2 :1; /* CRG Test Control Bit 2 */\r
+ byte TCTL3 :1; /* CRG Test Control Bit 3 */\r
+ byte TCTL4 :1; /* CRG Test Control Bit 4 */\r
+ byte TCTL5 :1; /* CRG Test Control Bit 5 */\r
+ byte TCTL6 :1; /* CRG Test Control Bit 6 */\r
+ byte TCTL7 :1; /* CRG Test Control Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpTCTL :8;\r
+ } MergedBits;\r
+} CTCTLSTR;\r
+extern volatile CTCTLSTR _CTCTL @(REG_BASE + 0x0000003E);\r
+#define CTCTL _CTCTL.Byte\r
+#define CTCTL_TCTL0 _CTCTL.Bits.TCTL0\r
+#define CTCTL_TCTL1 _CTCTL.Bits.TCTL1\r
+#define CTCTL_TCTL2 _CTCTL.Bits.TCTL2\r
+#define CTCTL_TCTL3 _CTCTL.Bits.TCTL3\r
+#define CTCTL_TCTL4 _CTCTL.Bits.TCTL4\r
+#define CTCTL_TCTL5 _CTCTL.Bits.TCTL5\r
+#define CTCTL_TCTL6 _CTCTL.Bits.TCTL6\r
+#define CTCTL_TCTL7 _CTCTL.Bits.TCTL7\r
+#define CTCTL_TCTL _CTCTL.MergedBits.grpTCTL\r
+\r
+\r
+/*** ARMCOP - CRG COP Timer Arm/Reset Register; 0x0000003F ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* CRG COP Timer Arm/Reset Bit 0 */\r
+ byte BIT1 :1; /* CRG COP Timer Arm/Reset Bit 1 */\r
+ byte BIT2 :1; /* CRG COP Timer Arm/Reset Bit 2 */\r
+ byte BIT3 :1; /* CRG COP Timer Arm/Reset Bit 3 */\r
+ byte BIT4 :1; /* CRG COP Timer Arm/Reset Bit 4 */\r
+ byte BIT5 :1; /* CRG COP Timer Arm/Reset Bit 5 */\r
+ byte BIT6 :1; /* CRG COP Timer Arm/Reset Bit 6 */\r
+ byte BIT7 :1; /* CRG COP Timer Arm/Reset Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+} ARMCOPSTR;\r
+extern volatile ARMCOPSTR _ARMCOP @(REG_BASE + 0x0000003F);\r
+#define ARMCOP _ARMCOP.Byte\r
+#define ARMCOP_BIT0 _ARMCOP.Bits.BIT0\r
+#define ARMCOP_BIT1 _ARMCOP.Bits.BIT1\r
+#define ARMCOP_BIT2 _ARMCOP.Bits.BIT2\r
+#define ARMCOP_BIT3 _ARMCOP.Bits.BIT3\r
+#define ARMCOP_BIT4 _ARMCOP.Bits.BIT4\r
+#define ARMCOP_BIT5 _ARMCOP.Bits.BIT5\r
+#define ARMCOP_BIT6 _ARMCOP.Bits.BIT6\r
+#define ARMCOP_BIT7 _ARMCOP.Bits.BIT7\r
+#define ARMCOP_BIT _ARMCOP.MergedBits.grpBIT\r
+\r
+\r
+/*** TIOS - Timer Input Capture/Output Compare Select; 0x00000040 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte IOS0 :1; /* Input Capture or Output Compare Channel Configuration Bit 0 */\r
+ byte IOS1 :1; /* Input Capture or Output Compare Channel Configuration Bit 1 */\r
+ byte IOS2 :1; /* Input Capture or Output Compare Channel Configuration Bit 2 */\r
+ byte IOS3 :1; /* Input Capture or Output Compare Channel Configuration Bit 3 */\r
+ byte IOS4 :1; /* Input Capture or Output Compare Channel Configuration Bit 4 */\r
+ byte IOS5 :1; /* Input Capture or Output Compare Channel Configuration Bit 5 */\r
+ byte IOS6 :1; /* Input Capture or Output Compare Channel Configuration Bit 6 */\r
+ byte IOS7 :1; /* Input Capture or Output Compare Channel Configuration Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpIOS :8;\r
+ } MergedBits;\r
+} TIOSSTR;\r
+extern volatile TIOSSTR _TIOS @(REG_BASE + 0x00000040);\r
+#define TIOS _TIOS.Byte\r
+#define TIOS_IOS0 _TIOS.Bits.IOS0\r
+#define TIOS_IOS1 _TIOS.Bits.IOS1\r
+#define TIOS_IOS2 _TIOS.Bits.IOS2\r
+#define TIOS_IOS3 _TIOS.Bits.IOS3\r
+#define TIOS_IOS4 _TIOS.Bits.IOS4\r
+#define TIOS_IOS5 _TIOS.Bits.IOS5\r
+#define TIOS_IOS6 _TIOS.Bits.IOS6\r
+#define TIOS_IOS7 _TIOS.Bits.IOS7\r
+#define TIOS_IOS _TIOS.MergedBits.grpIOS\r
+\r
+\r
+/*** CFORC - Timer Compare Force Register; 0x00000041 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte FOC0 :1; /* Force Output Compare Action for Channel 0 */\r
+ byte FOC1 :1; /* Force Output Compare Action for Channel 1 */\r
+ byte FOC2 :1; /* Force Output Compare Action for Channel 2 */\r
+ byte FOC3 :1; /* Force Output Compare Action for Channel 3 */\r
+ byte FOC4 :1; /* Force Output Compare Action for Channel 4 */\r
+ byte FOC5 :1; /* Force Output Compare Action for Channel 5 */\r
+ byte FOC6 :1; /* Force Output Compare Action for Channel 6 */\r
+ byte FOC7 :1; /* Force Output Compare Action for Channel 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpFOC :8;\r
+ } MergedBits;\r
+} CFORCSTR;\r
+extern volatile CFORCSTR _CFORC @(REG_BASE + 0x00000041);\r
+#define CFORC _CFORC.Byte\r
+#define CFORC_FOC0 _CFORC.Bits.FOC0\r
+#define CFORC_FOC1 _CFORC.Bits.FOC1\r
+#define CFORC_FOC2 _CFORC.Bits.FOC2\r
+#define CFORC_FOC3 _CFORC.Bits.FOC3\r
+#define CFORC_FOC4 _CFORC.Bits.FOC4\r
+#define CFORC_FOC5 _CFORC.Bits.FOC5\r
+#define CFORC_FOC6 _CFORC.Bits.FOC6\r
+#define CFORC_FOC7 _CFORC.Bits.FOC7\r
+#define CFORC_FOC _CFORC.MergedBits.grpFOC\r
+\r
+\r
+/*** OC7M - Output Compare 7 Mask Register; 0x00000042 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte OC7M0 :1; /* Output Compare 7 Mask Bit 0 */\r
+ byte OC7M1 :1; /* Output Compare 7 Mask Bit 1 */\r
+ byte OC7M2 :1; /* Output Compare 7 Mask Bit 2 */\r
+ byte OC7M3 :1; /* Output Compare 7 Mask Bit 3 */\r
+ byte OC7M4 :1; /* Output Compare 7 Mask Bit 4 */\r
+ byte OC7M5 :1; /* Output Compare 7 Mask Bit 5 */\r
+ byte OC7M6 :1; /* Output Compare 7 Mask Bit 6 */\r
+ byte OC7M7 :1; /* Output Compare 7 Mask Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpOC7M :8;\r
+ } MergedBits;\r
+} OC7MSTR;\r
+extern volatile OC7MSTR _OC7M @(REG_BASE + 0x00000042);\r
+#define OC7M _OC7M.Byte\r
+#define OC7M_OC7M0 _OC7M.Bits.OC7M0\r
+#define OC7M_OC7M1 _OC7M.Bits.OC7M1\r
+#define OC7M_OC7M2 _OC7M.Bits.OC7M2\r
+#define OC7M_OC7M3 _OC7M.Bits.OC7M3\r
+#define OC7M_OC7M4 _OC7M.Bits.OC7M4\r
+#define OC7M_OC7M5 _OC7M.Bits.OC7M5\r
+#define OC7M_OC7M6 _OC7M.Bits.OC7M6\r
+#define OC7M_OC7M7 _OC7M.Bits.OC7M7\r
+#define OC7M_OC7M _OC7M.MergedBits.grpOC7M\r
+\r
+\r
+/*** OC7D - Output Compare 7 Data Register; 0x00000043 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte OC7D0 :1; /* Output Compare 7 Bit 0 */\r
+ byte OC7D1 :1; /* Output Compare 7 Bit 1 */\r
+ byte OC7D2 :1; /* Output Compare 7 Bit 2 */\r
+ byte OC7D3 :1; /* Output Compare 7 Bit 3 */\r
+ byte OC7D4 :1; /* Output Compare 7 Bit 4 */\r
+ byte OC7D5 :1; /* Output Compare 7 Bit 5 */\r
+ byte OC7D6 :1; /* Output Compare 7 Bit 6 */\r
+ byte OC7D7 :1; /* Output Compare 7 Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpOC7D :8;\r
+ } MergedBits;\r
+} OC7DSTR;\r
+extern volatile OC7DSTR _OC7D @(REG_BASE + 0x00000043);\r
+#define OC7D _OC7D.Byte\r
+#define OC7D_OC7D0 _OC7D.Bits.OC7D0\r
+#define OC7D_OC7D1 _OC7D.Bits.OC7D1\r
+#define OC7D_OC7D2 _OC7D.Bits.OC7D2\r
+#define OC7D_OC7D3 _OC7D.Bits.OC7D3\r
+#define OC7D_OC7D4 _OC7D.Bits.OC7D4\r
+#define OC7D_OC7D5 _OC7D.Bits.OC7D5\r
+#define OC7D_OC7D6 _OC7D.Bits.OC7D6\r
+#define OC7D_OC7D7 _OC7D.Bits.OC7D7\r
+#define OC7D_OC7D _OC7D.MergedBits.grpOC7D\r
+\r
+\r
+/*** TSCR1 - Timer System Control Register1; 0x00000046 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte TFFCA :1; /* Timer Fast Flag Clear All */\r
+ byte TSFRZ :1; /* Timer and Modulus Counter Stop While in Freeze Mode */\r
+ byte TSWAI :1; /* Timer Module Stops While in Wait */\r
+ byte TEN :1; /* Timer Enable */\r
+ } Bits;\r
+} TSCR1STR;\r
+extern volatile TSCR1STR _TSCR1 @(REG_BASE + 0x00000046);\r
+#define TSCR1 _TSCR1.Byte\r
+#define TSCR1_TFFCA _TSCR1.Bits.TFFCA\r
+#define TSCR1_TSFRZ _TSCR1.Bits.TSFRZ\r
+#define TSCR1_TSWAI _TSCR1.Bits.TSWAI\r
+#define TSCR1_TEN _TSCR1.Bits.TEN\r
+\r
+\r
+/*** TTOV - Timer Toggle On Overflow Register; 0x00000047 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte TOV0 :1; /* Toggle On Overflow Bit 0 */\r
+ byte TOV1 :1; /* Toggle On Overflow Bit 1 */\r
+ byte TOV2 :1; /* Toggle On Overflow Bit 2 */\r
+ byte TOV3 :1; /* Toggle On Overflow Bit 3 */\r
+ byte TOV4 :1; /* Toggle On Overflow Bit 4 */\r
+ byte TOV5 :1; /* Toggle On Overflow Bit 5 */\r
+ byte TOV6 :1; /* Toggle On Overflow Bit 6 */\r
+ byte TOV7 :1; /* Toggle On Overflow Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpTOV :8;\r
+ } MergedBits;\r
+} TTOVSTR;\r
+extern volatile TTOVSTR _TTOV @(REG_BASE + 0x00000047);\r
+#define TTOV _TTOV.Byte\r
+#define TTOV_TOV0 _TTOV.Bits.TOV0\r
+#define TTOV_TOV1 _TTOV.Bits.TOV1\r
+#define TTOV_TOV2 _TTOV.Bits.TOV2\r
+#define TTOV_TOV3 _TTOV.Bits.TOV3\r
+#define TTOV_TOV4 _TTOV.Bits.TOV4\r
+#define TTOV_TOV5 _TTOV.Bits.TOV5\r
+#define TTOV_TOV6 _TTOV.Bits.TOV6\r
+#define TTOV_TOV7 _TTOV.Bits.TOV7\r
+#define TTOV_TOV _TTOV.MergedBits.grpTOV\r
+\r
+\r
+/*** TCTL1 - Timer Control Register 1; 0x00000048 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte OL4 :1; /* Output Level Bit 4 */\r
+ byte OM4 :1; /* Output Mode Bit 4 */\r
+ byte OL5 :1; /* Output Level Bit 5 */\r
+ byte OM5 :1; /* Output Mode Bit 5 */\r
+ byte OL6 :1; /* Output Level Bit 6 */\r
+ byte OM6 :1; /* Output Mode Bit 6 */\r
+ byte OL7 :1; /* Output Level Bit 7 */\r
+ byte OM7 :1; /* Output Mode Bit 7 */\r
+ } Bits;\r
+} TCTL1STR;\r
+extern volatile TCTL1STR _TCTL1 @(REG_BASE + 0x00000048);\r
+#define TCTL1 _TCTL1.Byte\r
+#define TCTL1_OL4 _TCTL1.Bits.OL4\r
+#define TCTL1_OM4 _TCTL1.Bits.OM4\r
+#define TCTL1_OL5 _TCTL1.Bits.OL5\r
+#define TCTL1_OM5 _TCTL1.Bits.OM5\r
+#define TCTL1_OL6 _TCTL1.Bits.OL6\r
+#define TCTL1_OM6 _TCTL1.Bits.OM6\r
+#define TCTL1_OL7 _TCTL1.Bits.OL7\r
+#define TCTL1_OM7 _TCTL1.Bits.OM7\r
+\r
+\r
+/*** TCTL2 - Timer Control Register 2; 0x00000049 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte OL0 :1; /* Output Level Bit 0 */\r
+ byte OM0 :1; /* Output Mode Bit 0 */\r
+ byte OL1 :1; /* Output Level Bit 1 */\r
+ byte OM1 :1; /* Output Mode Bit 1 */\r
+ byte OL2 :1; /* Output Level Bit 2 */\r
+ byte OM2 :1; /* Output Mode Bit 2 */\r
+ byte OL3 :1; /* Output Level Bit 3 */\r
+ byte OM3 :1; /* Output Mode Bit 3 */\r
+ } Bits;\r
+} TCTL2STR;\r
+extern volatile TCTL2STR _TCTL2 @(REG_BASE + 0x00000049);\r
+#define TCTL2 _TCTL2.Byte\r
+#define TCTL2_OL0 _TCTL2.Bits.OL0\r
+#define TCTL2_OM0 _TCTL2.Bits.OM0\r
+#define TCTL2_OL1 _TCTL2.Bits.OL1\r
+#define TCTL2_OM1 _TCTL2.Bits.OM1\r
+#define TCTL2_OL2 _TCTL2.Bits.OL2\r
+#define TCTL2_OM2 _TCTL2.Bits.OM2\r
+#define TCTL2_OL3 _TCTL2.Bits.OL3\r
+#define TCTL2_OM3 _TCTL2.Bits.OM3\r
+\r
+\r
+/*** TCTL3 - Timer Control Register 3; 0x0000004A ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte EDG4A :1; /* Input Capture Edge Control 4A */\r
+ byte EDG4B :1; /* Input Capture Edge Control 4B */\r
+ byte EDG5A :1; /* Input Capture Edge Control 5A */\r
+ byte EDG5B :1; /* Input Capture Edge Control 5B */\r
+ byte EDG6A :1; /* Input Capture Edge Control 6A */\r
+ byte EDG6B :1; /* Input Capture Edge Control 6B */\r
+ byte EDG7A :1; /* Input Capture Edge Control 7A */\r
+ byte EDG7B :1; /* Input Capture Edge Control 7B */\r
+ } Bits;\r
+} TCTL3STR;\r
+extern volatile TCTL3STR _TCTL3 @(REG_BASE + 0x0000004A);\r
+#define TCTL3 _TCTL3.Byte\r
+#define TCTL3_EDG4A _TCTL3.Bits.EDG4A\r
+#define TCTL3_EDG4B _TCTL3.Bits.EDG4B\r
+#define TCTL3_EDG5A _TCTL3.Bits.EDG5A\r
+#define TCTL3_EDG5B _TCTL3.Bits.EDG5B\r
+#define TCTL3_EDG6A _TCTL3.Bits.EDG6A\r
+#define TCTL3_EDG6B _TCTL3.Bits.EDG6B\r
+#define TCTL3_EDG7A _TCTL3.Bits.EDG7A\r
+#define TCTL3_EDG7B _TCTL3.Bits.EDG7B\r
+\r
+\r
+/*** TCTL4 - Timer Control Register 4; 0x0000004B ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte EDG0A :1; /* Input Capture Edge Control 0A */\r
+ byte EDG0B :1; /* Input Capture Edge Control 0B */\r
+ byte EDG1A :1; /* Input Capture Edge Control 1A */\r
+ byte EDG1B :1; /* Input Capture Edge Control 1B */\r
+ byte EDG2A :1; /* Input Capture Edge Control 2A */\r
+ byte EDG2B :1; /* Input Capture Edge Control 2B */\r
+ byte EDG3A :1; /* Input Capture Edge Control 3A */\r
+ byte EDG3B :1; /* Input Capture Edge Control 3B */\r
+ } Bits;\r
+} TCTL4STR;\r
+extern volatile TCTL4STR _TCTL4 @(REG_BASE + 0x0000004B);\r
+#define TCTL4 _TCTL4.Byte\r
+#define TCTL4_EDG0A _TCTL4.Bits.EDG0A\r
+#define TCTL4_EDG0B _TCTL4.Bits.EDG0B\r
+#define TCTL4_EDG1A _TCTL4.Bits.EDG1A\r
+#define TCTL4_EDG1B _TCTL4.Bits.EDG1B\r
+#define TCTL4_EDG2A _TCTL4.Bits.EDG2A\r
+#define TCTL4_EDG2B _TCTL4.Bits.EDG2B\r
+#define TCTL4_EDG3A _TCTL4.Bits.EDG3A\r
+#define TCTL4_EDG3B _TCTL4.Bits.EDG3B\r
+\r
+\r
+/*** TIE - Timer Interrupt Enable Register; 0x0000004C ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte C0I :1; /* Input Capture/Output Compare Interrupt Enable Bit 0 */\r
+ byte C1I :1; /* Input Capture/Output Compare Interrupt Enable Bit 1 */\r
+ byte C2I :1; /* Input Capture/Output Compare Interrupt Enable Bit 2 */\r
+ byte C3I :1; /* Input Capture/Output Compare Interrupt Enable Bit 3 */\r
+ byte C4I :1; /* Input Capture/Output Compare Interrupt Enable Bit 4 */\r
+ byte C5I :1; /* Input Capture/Output Compare Interrupt Enable Bit 5 */\r
+ byte C6I :1; /* Input Capture/Output Compare Interrupt Enable Bit 6 */\r
+ byte C7I :1; /* Input Capture/Output Compare Interrupt Enable Bit 7 */\r
+ } Bits;\r
+} TIESTR;\r
+extern volatile TIESTR _TIE @(REG_BASE + 0x0000004C);\r
+#define TIE _TIE.Byte\r
+#define TIE_C0I _TIE.Bits.C0I\r
+#define TIE_C1I _TIE.Bits.C1I\r
+#define TIE_C2I _TIE.Bits.C2I\r
+#define TIE_C3I _TIE.Bits.C3I\r
+#define TIE_C4I _TIE.Bits.C4I\r
+#define TIE_C5I _TIE.Bits.C5I\r
+#define TIE_C6I _TIE.Bits.C6I\r
+#define TIE_C7I _TIE.Bits.C7I\r
+\r
+\r
+/*** TSCR2 - Timer System Control Register 2; 0x0000004D ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PR0 :1; /* Timer Prescaler Select Bit 0 */\r
+ byte PR1 :1; /* Timer Prescaler Select Bit 1 */\r
+ byte PR2 :1; /* Timer Prescaler Select Bit 2 */\r
+ byte TCRE :1; /* Timer Counter Reset Enable */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte TOI :1; /* Timer Overflow Interrupt Enable */\r
+ } Bits;\r
+ struct {\r
+ byte grpPR :3;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} TSCR2STR;\r
+extern volatile TSCR2STR _TSCR2 @(REG_BASE + 0x0000004D);\r
+#define TSCR2 _TSCR2.Byte\r
+#define TSCR2_PR0 _TSCR2.Bits.PR0\r
+#define TSCR2_PR1 _TSCR2.Bits.PR1\r
+#define TSCR2_PR2 _TSCR2.Bits.PR2\r
+#define TSCR2_TCRE _TSCR2.Bits.TCRE\r
+#define TSCR2_TOI _TSCR2.Bits.TOI\r
+#define TSCR2_PR _TSCR2.MergedBits.grpPR\r
+\r
+\r
+/*** TFLG1 - Main Timer Interrupt Flag 1; 0x0000004E ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte C0F :1; /* Input Capture/Output Compare Channel Flag 0 */\r
+ byte C1F :1; /* Input Capture/Output Compare Channel Flag 1 */\r
+ byte C2F :1; /* Input Capture/Output Compare Channel Flag 2 */\r
+ byte C3F :1; /* Input Capture/Output Compare Channel Flag 3 */\r
+ byte C4F :1; /* Input Capture/Output Compare Channel Flag 4 */\r
+ byte C5F :1; /* Input Capture/Output Compare Channel Flag 5 */\r
+ byte C6F :1; /* Input Capture/Output Compare Channel Flag 6 */\r
+ byte C7F :1; /* Input Capture/Output Compare Channel Flag 7 */\r
+ } Bits;\r
+} TFLG1STR;\r
+extern volatile TFLG1STR _TFLG1 @(REG_BASE + 0x0000004E);\r
+#define TFLG1 _TFLG1.Byte\r
+#define TFLG1_C0F _TFLG1.Bits.C0F\r
+#define TFLG1_C1F _TFLG1.Bits.C1F\r
+#define TFLG1_C2F _TFLG1.Bits.C2F\r
+#define TFLG1_C3F _TFLG1.Bits.C3F\r
+#define TFLG1_C4F _TFLG1.Bits.C4F\r
+#define TFLG1_C5F _TFLG1.Bits.C5F\r
+#define TFLG1_C6F _TFLG1.Bits.C6F\r
+#define TFLG1_C7F _TFLG1.Bits.C7F\r
+\r
+\r
+/*** TFLG2 - Main Timer Interrupt Flag 2; 0x0000004F ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte TOF :1; /* Timer Overflow Flag */\r
+ } Bits;\r
+} TFLG2STR;\r
+extern volatile TFLG2STR _TFLG2 @(REG_BASE + 0x0000004F);\r
+#define TFLG2 _TFLG2.Byte\r
+#define TFLG2_TOF _TFLG2.Bits.TOF\r
+\r
+\r
+/*** PACTL - 16-Bit Pulse Accumulator A Control Register; 0x00000060 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PAI :1; /* Pulse Accumulator Input Interrupt enable */\r
+ byte PAOVI :1; /* Pulse Accumulator A Overflow Interrupt enable */\r
+ byte CLK0 :1; /* Clock Select Bit 0 */\r
+ byte CLK1 :1; /* Clock Select Bit 1 */\r
+ byte PEDGE :1; /* Pulse Accumulator Edge Control */\r
+ byte PAMOD :1; /* Pulse Accumulator Mode */\r
+ byte PAEN :1; /* Pulse Accumulator A System Enable */\r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte grpCLK :2;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} PACTLSTR;\r
+extern volatile PACTLSTR _PACTL @(REG_BASE + 0x00000060);\r
+#define PACTL _PACTL.Byte\r
+#define PACTL_PAI _PACTL.Bits.PAI\r
+#define PACTL_PAOVI _PACTL.Bits.PAOVI\r
+#define PACTL_CLK0 _PACTL.Bits.CLK0\r
+#define PACTL_CLK1 _PACTL.Bits.CLK1\r
+#define PACTL_PEDGE _PACTL.Bits.PEDGE\r
+#define PACTL_PAMOD _PACTL.Bits.PAMOD\r
+#define PACTL_PAEN _PACTL.Bits.PAEN\r
+#define PACTL_CLK _PACTL.MergedBits.grpCLK\r
+\r
+\r
+/*** PAFLG - Pulse Accumulator A Flag Register; 0x00000061 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PAIF :1; /* Pulse Accumulator Input edge Flag */\r
+ byte PAOVF :1; /* Pulse Accumulator A Overflow Flag */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+} PAFLGSTR;\r
+extern volatile PAFLGSTR _PAFLG @(REG_BASE + 0x00000061);\r
+#define PAFLG _PAFLG.Byte\r
+#define PAFLG_PAIF _PAFLG.Bits.PAIF\r
+#define PAFLG_PAOVF _PAFLG.Bits.PAOVF\r
+\r
+\r
+/*** ATDSTAT0 - A/D Status Register 0; 0x00000086 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte CC0 :1; /* Conversion Counter 0 */\r
+ byte CC1 :1; /* Conversion Counter 1 */\r
+ byte CC2 :1; /* Conversion Counter 2 */\r
+ byte :1; \r
+ byte FIFOR :1; /* FIFO Over Run Flag */\r
+ byte ETORF :1; /* External Trigger Overrun Flag */\r
+ byte :1; \r
+ byte SCF :1; /* Sequence Complete Flag */\r
+ } Bits;\r
+ struct {\r
+ byte grpCC :3;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} ATDSTAT0STR;\r
+extern volatile ATDSTAT0STR _ATDSTAT0 @(REG_BASE + 0x00000086);\r
+#define ATDSTAT0 _ATDSTAT0.Byte\r
+#define ATDSTAT0_CC0 _ATDSTAT0.Bits.CC0\r
+#define ATDSTAT0_CC1 _ATDSTAT0.Bits.CC1\r
+#define ATDSTAT0_CC2 _ATDSTAT0.Bits.CC2\r
+#define ATDSTAT0_FIFOR _ATDSTAT0.Bits.FIFOR\r
+#define ATDSTAT0_ETORF _ATDSTAT0.Bits.ETORF\r
+#define ATDSTAT0_SCF _ATDSTAT0.Bits.SCF\r
+#define ATDSTAT0_CC _ATDSTAT0.MergedBits.grpCC\r
+\r
+\r
+/*** ATDSTAT1 - A/D Status Register 1; 0x0000008B ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte CCF0 :1; /* Conversion Complete Flag 0 */\r
+ byte CCF1 :1; /* Conversion Complete Flag 1 */\r
+ byte CCF2 :1; /* Conversion Complete Flag 2 */\r
+ byte CCF3 :1; /* Conversion Complete Flag 3 */\r
+ byte CCF4 :1; /* Conversion Complete Flag 4 */\r
+ byte CCF5 :1; /* Conversion Complete Flag 5 */\r
+ byte CCF6 :1; /* Conversion Complete Flag 6 */\r
+ byte CCF7 :1; /* Conversion Complete Flag 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpCCF :8;\r
+ } MergedBits;\r
+} ATDSTAT1STR;\r
+extern volatile ATDSTAT1STR _ATDSTAT1 @(REG_BASE + 0x0000008B);\r
+#define ATDSTAT1 _ATDSTAT1.Byte\r
+#define ATDSTAT1_CCF0 _ATDSTAT1.Bits.CCF0\r
+#define ATDSTAT1_CCF1 _ATDSTAT1.Bits.CCF1\r
+#define ATDSTAT1_CCF2 _ATDSTAT1.Bits.CCF2\r
+#define ATDSTAT1_CCF3 _ATDSTAT1.Bits.CCF3\r
+#define ATDSTAT1_CCF4 _ATDSTAT1.Bits.CCF4\r
+#define ATDSTAT1_CCF5 _ATDSTAT1.Bits.CCF5\r
+#define ATDSTAT1_CCF6 _ATDSTAT1.Bits.CCF6\r
+#define ATDSTAT1_CCF7 _ATDSTAT1.Bits.CCF7\r
+#define ATDSTAT1_CCF _ATDSTAT1.MergedBits.grpCCF\r
+\r
+\r
+/*** ATDDIEN - ATD Input Enable Mask Register; 0x0000008D ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* Disable/Enable digital input buffer */\r
+ byte BIT1 :1; /* Disable/Enable digital input buffer */\r
+ byte BIT2 :1; /* Disable/Enable digital input buffer */\r
+ byte BIT3 :1; /* Disable/Enable digital input buffer */\r
+ byte BIT4 :1; /* Disable/Enable digital input buffer */\r
+ byte BIT5 :1; /* Disable/Enable digital input buffer */\r
+ byte BIT6 :1; /* Disable/Enable digital input buffer */\r
+ byte BIT7 :1; /* Disable/Enable digital input buffer */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+} ATDDIENSTR;\r
+extern volatile ATDDIENSTR _ATDDIEN @(REG_BASE + 0x0000008D);\r
+#define ATDDIEN _ATDDIEN.Byte\r
+#define ATDDIEN_BIT0 _ATDDIEN.Bits.BIT0\r
+#define ATDDIEN_BIT1 _ATDDIEN.Bits.BIT1\r
+#define ATDDIEN_BIT2 _ATDDIEN.Bits.BIT2\r
+#define ATDDIEN_BIT3 _ATDDIEN.Bits.BIT3\r
+#define ATDDIEN_BIT4 _ATDDIEN.Bits.BIT4\r
+#define ATDDIEN_BIT5 _ATDDIEN.Bits.BIT5\r
+#define ATDDIEN_BIT6 _ATDDIEN.Bits.BIT6\r
+#define ATDDIEN_BIT7 _ATDDIEN.Bits.BIT7\r
+#define ATDDIEN_BIT _ATDDIEN.MergedBits.grpBIT\r
+\r
+\r
+/*** PORTAD0 - Port AD0 Register; 0x0000008F ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* AN0 */\r
+ byte BIT1 :1; /* AN1 */\r
+ byte BIT2 :1; /* AN2 */\r
+ byte BIT3 :1; /* AN3 */\r
+ byte BIT4 :1; /* AN4 */\r
+ byte BIT5 :1; /* AN5 */\r
+ byte BIT6 :1; /* AN6 */\r
+ byte BIT7 :1; /* AN7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+} PORTAD0STR;\r
+extern volatile PORTAD0STR _PORTAD0 @(REG_BASE + 0x0000008F);\r
+#define PORTAD0 _PORTAD0.Byte\r
+#define PORTAD0_BIT0 _PORTAD0.Bits.BIT0\r
+#define PORTAD0_BIT1 _PORTAD0.Bits.BIT1\r
+#define PORTAD0_BIT2 _PORTAD0.Bits.BIT2\r
+#define PORTAD0_BIT3 _PORTAD0.Bits.BIT3\r
+#define PORTAD0_BIT4 _PORTAD0.Bits.BIT4\r
+#define PORTAD0_BIT5 _PORTAD0.Bits.BIT5\r
+#define PORTAD0_BIT6 _PORTAD0.Bits.BIT6\r
+#define PORTAD0_BIT7 _PORTAD0.Bits.BIT7\r
+#define PORTAD0_BIT _PORTAD0.MergedBits.grpBIT\r
+\r
+\r
+/*** SCICR1 - SCI Control Register 1; 0x000000CA ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PT :1; /* Parity Type Bit */\r
+ byte PE :1; /* Parity Enable Bit */\r
+ byte ILT :1; /* Idle Line Type Bit */\r
+ byte WAKE :1; /* Wakeup Condition Bit */\r
+ byte M :1; /* Data Format Mode Bit */\r
+ byte RSRC :1; /* Receiver Source Bit */\r
+ byte SCISWAI :1; /* SCI Stop in Wait Mode Bit */\r
+ byte LOOPS :1; /* Loop Select Bit */\r
+ } Bits;\r
+} SCICR1STR;\r
+extern volatile SCICR1STR _SCICR1 @(REG_BASE + 0x000000CA);\r
+#define SCICR1 _SCICR1.Byte\r
+#define SCICR1_PT _SCICR1.Bits.PT\r
+#define SCICR1_PE _SCICR1.Bits.PE\r
+#define SCICR1_ILT _SCICR1.Bits.ILT\r
+#define SCICR1_WAKE _SCICR1.Bits.WAKE\r
+#define SCICR1_M _SCICR1.Bits.M\r
+#define SCICR1_RSRC _SCICR1.Bits.RSRC\r
+#define SCICR1_SCISWAI _SCICR1.Bits.SCISWAI\r
+#define SCICR1_LOOPS _SCICR1.Bits.LOOPS\r
+\r
+\r
+/*** SCICR2 - SCI Control Register 2; 0x000000CB ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte SBK :1; /* Send Break Bit */\r
+ byte RWU :1; /* Receiver Wakeup Bit */\r
+ byte RE :1; /* Receiver Enable Bit */\r
+ byte TE :1; /* Transmitter Enable Bit */\r
+ byte ILIE :1; /* Idle Line Interrupt Enable Bit */\r
+ byte RIE :1; /* Receiver Full Interrupt Enable Bit */\r
+ byte TCIE :1; /* Transmission Complete Interrupt Enable Bit */\r
+ byte SCTIE :1; /* Transmitter Interrupt Enable Bit */\r
+ } Bits;\r
+} SCICR2STR;\r
+extern volatile SCICR2STR _SCICR2 @(REG_BASE + 0x000000CB);\r
+#define SCICR2 _SCICR2.Byte\r
+#define SCICR2_SBK _SCICR2.Bits.SBK\r
+#define SCICR2_RWU _SCICR2.Bits.RWU\r
+#define SCICR2_RE _SCICR2.Bits.RE\r
+#define SCICR2_TE _SCICR2.Bits.TE\r
+#define SCICR2_ILIE _SCICR2.Bits.ILIE\r
+#define SCICR2_RIE _SCICR2.Bits.RIE\r
+#define SCICR2_TCIE _SCICR2.Bits.TCIE\r
+#define SCICR2_SCTIE _SCICR2.Bits.SCTIE\r
+\r
+\r
+/*** SCISR1 - SCI Status Register 1; 0x000000CC ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PF :1; /* Parity Error Flag */\r
+ byte FE :1; /* Framing Error Flag */\r
+ byte NF :1; /* Noise Flag */\r
+ byte OR :1; /* Overrun Flag */\r
+ byte IDLE :1; /* Idle Line Flag */\r
+ byte RDRF :1; /* Receive Data Register Full Flag */\r
+ byte TC :1; /* Transmit Complete Flag */\r
+ byte TDRE :1; /* Transmit Data Register Empty Flag */\r
+ } Bits;\r
+} SCISR1STR;\r
+extern volatile SCISR1STR _SCISR1 @(REG_BASE + 0x000000CC);\r
+#define SCISR1 _SCISR1.Byte\r
+#define SCISR1_PF _SCISR1.Bits.PF\r
+#define SCISR1_FE _SCISR1.Bits.FE\r
+#define SCISR1_NF _SCISR1.Bits.NF\r
+#define SCISR1_OR _SCISR1.Bits.OR\r
+#define SCISR1_IDLE _SCISR1.Bits.IDLE\r
+#define SCISR1_RDRF _SCISR1.Bits.RDRF\r
+#define SCISR1_TC _SCISR1.Bits.TC\r
+#define SCISR1_TDRE _SCISR1.Bits.TDRE\r
+\r
+\r
+/*** SCISR2 - SCI Status Register 2; 0x000000CD ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte RAF :1; /* Receiver Active Flag */\r
+ byte TXDIR :1; /* Transmitter pin data direction in Single-Wire mode */\r
+ byte BRK13 :1; /* Break Transmit character length */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+} SCISR2STR;\r
+extern volatile SCISR2STR _SCISR2 @(REG_BASE + 0x000000CD);\r
+#define SCISR2 _SCISR2.Byte\r
+#define SCISR2_RAF _SCISR2.Bits.RAF\r
+#define SCISR2_TXDIR _SCISR2.Bits.TXDIR\r
+#define SCISR2_BRK13 _SCISR2.Bits.BRK13\r
+\r
+\r
+/*** SCIDRH - SCI Data Register High; 0x000000CE ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte T8 :1; /* Transmit Bit 8 */\r
+ byte R8 :1; /* Received Bit 8 */\r
+ } Bits;\r
+} SCIDRHSTR;\r
+extern volatile SCIDRHSTR _SCIDRH @(REG_BASE + 0x000000CE);\r
+#define SCIDRH _SCIDRH.Byte\r
+#define SCIDRH_T8 _SCIDRH.Bits.T8\r
+#define SCIDRH_R8 _SCIDRH.Bits.R8\r
+\r
+\r
+/*** SCIDRL - SCI Data Register Low; 0x000000CF ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte R0_T0 :1; /* Received bit 0 or Transmit bit 0 */\r
+ byte R1_T1 :1; /* Received bit 1 or Transmit bit 1 */\r
+ byte R2_T2 :1; /* Received bit 2 or Transmit bit 2 */\r
+ byte R3_T3 :1; /* Received bit 3 or Transmit bit 3 */\r
+ byte R4_T4 :1; /* Received bit 4 or Transmit bit 4 */\r
+ byte R5_T5 :1; /* Received bit 5 or Transmit bit 5 */\r
+ byte R6_T6 :1; /* Received bit 6 or Transmit bit 6 */\r
+ byte R7_T7 :1; /* Received bit 7 or Transmit bit 7 */\r
+ } Bits;\r
+} SCIDRLSTR;\r
+extern volatile SCIDRLSTR _SCIDRL @(REG_BASE + 0x000000CF);\r
+#define SCIDRL _SCIDRL.Byte\r
+#define SCIDRL_R0_T0 _SCIDRL.Bits.R0_T0\r
+#define SCIDRL_R1_T1 _SCIDRL.Bits.R1_T1\r
+#define SCIDRL_R2_T2 _SCIDRL.Bits.R2_T2\r
+#define SCIDRL_R3_T3 _SCIDRL.Bits.R3_T3\r
+#define SCIDRL_R4_T4 _SCIDRL.Bits.R4_T4\r
+#define SCIDRL_R5_T5 _SCIDRL.Bits.R5_T5\r
+#define SCIDRL_R6_T6 _SCIDRL.Bits.R6_T6\r
+#define SCIDRL_R7_T7 _SCIDRL.Bits.R7_T7\r
+\r
+\r
+/*** SPICR1 - SPI Control Register; 0x000000D8 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte LSBFE :1; /* SPI LSB-First Enable */\r
+ byte SSOE :1; /* Slave Select Output Enable */\r
+ byte CPHA :1; /* SPI Clock Phase Bit */\r
+ byte CPOL :1; /* SPI Clock Polarity Bit */\r
+ byte MSTR :1; /* SPI Master/Slave Mode Select Bit */\r
+ byte SPTIE :1; /* SPI Transmit Interrupt Enable */\r
+ byte SPE :1; /* SPI System Enable Bit */\r
+ byte SPIE :1; /* SPI Interrupt Enable Bit */\r
+ } Bits;\r
+} SPICR1STR;\r
+extern volatile SPICR1STR _SPICR1 @(REG_BASE + 0x000000D8);\r
+#define SPICR1 _SPICR1.Byte\r
+#define SPICR1_LSBFE _SPICR1.Bits.LSBFE\r
+#define SPICR1_SSOE _SPICR1.Bits.SSOE\r
+#define SPICR1_CPHA _SPICR1.Bits.CPHA\r
+#define SPICR1_CPOL _SPICR1.Bits.CPOL\r
+#define SPICR1_MSTR _SPICR1.Bits.MSTR\r
+#define SPICR1_SPTIE _SPICR1.Bits.SPTIE\r
+#define SPICR1_SPE _SPICR1.Bits.SPE\r
+#define SPICR1_SPIE _SPICR1.Bits.SPIE\r
+\r
+\r
+/*** SPICR2 - SPI Control Register 2; 0x000000D9 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte SPC0 :1; /* Serial Pin Control Bit 0 */\r
+ byte SPISWAI :1; /* SPI Stop in Wait Mode Bit */\r
+ byte :1; \r
+ byte BIDIROE :1; /* Output enable in the Bidirectional mode of operation */\r
+ byte MODFEN :1; /* Mode Fault Enable Bit */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+} SPICR2STR;\r
+extern volatile SPICR2STR _SPICR2 @(REG_BASE + 0x000000D9);\r
+#define SPICR2 _SPICR2.Byte\r
+#define SPICR2_SPC0 _SPICR2.Bits.SPC0\r
+#define SPICR2_SPISWAI _SPICR2.Bits.SPISWAI\r
+#define SPICR2_BIDIROE _SPICR2.Bits.BIDIROE\r
+#define SPICR2_MODFEN _SPICR2.Bits.MODFEN\r
+\r
+\r
+/*** SPIBR - SPI Baud Rate Register; 0x000000DA ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte SPR0 :1; /* SPI Baud Rate Selection Bit 0 */\r
+ byte SPR1 :1; /* SPI Baud Rate Selection Bit 1 */\r
+ byte SPR2 :1; /* SPI Baud Rate Selection Bit 2 */\r
+ byte :1; \r
+ byte SPPR0 :1; /* SPI Baud Rate Preselection Bits 0 */\r
+ byte SPPR1 :1; /* SPI Baud Rate Preselection Bits 1 */\r
+ byte SPPR2 :1; /* SPI Baud Rate Preselection Bits 2 */\r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpSPR :3;\r
+ byte :1;\r
+ byte grpSPPR :3;\r
+ byte :1;\r
+ } MergedBits;\r
+} SPIBRSTR;\r
+extern volatile SPIBRSTR _SPIBR @(REG_BASE + 0x000000DA);\r
+#define SPIBR _SPIBR.Byte\r
+#define SPIBR_SPR0 _SPIBR.Bits.SPR0\r
+#define SPIBR_SPR1 _SPIBR.Bits.SPR1\r
+#define SPIBR_SPR2 _SPIBR.Bits.SPR2\r
+#define SPIBR_SPPR0 _SPIBR.Bits.SPPR0\r
+#define SPIBR_SPPR1 _SPIBR.Bits.SPPR1\r
+#define SPIBR_SPPR2 _SPIBR.Bits.SPPR2\r
+#define SPIBR_SPR _SPIBR.MergedBits.grpSPR\r
+#define SPIBR_SPPR _SPIBR.MergedBits.grpSPPR\r
+\r
+\r
+/*** SPISR - SPI Status Register; 0x000000DB ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte MODF :1; /* Mode Fault Flag */\r
+ byte SPTEF :1; /* SPI Transmit Empty Interrupt Flag */\r
+ byte :1; \r
+ byte SPIF :1; /* SPIF Receive Interrupt Flag */\r
+ } Bits;\r
+} SPISRSTR;\r
+extern volatile SPISRSTR _SPISR @(REG_BASE + 0x000000DB);\r
+#define SPISR _SPISR.Byte\r
+#define SPISR_MODF _SPISR.Bits.MODF\r
+#define SPISR_SPTEF _SPISR.Bits.SPTEF\r
+#define SPISR_SPIF _SPISR.Bits.SPIF\r
+\r
+\r
+/*** SPIDR - SPI Data Register; 0x000000DD ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+} SPIDRSTR;\r
+extern volatile SPIDRSTR _SPIDR @(REG_BASE + 0x000000DD);\r
+#define SPIDR _SPIDR.Byte\r
+#define SPIDR_BIT _SPIDR.MergedBits.grpBIT\r
+\r
+\r
+/*** PWME - PWM Enable Register; 0x000000E0 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PWME0 :1; /* Pulse Width Channel 0 Enable */\r
+ byte PWME1 :1; /* Pulse Width Channel 1 Enable */\r
+ byte PWME2 :1; /* Pulse Width Channel 2 Enable */\r
+ byte PWME3 :1; /* Pulse Width Channel 3 Enable */\r
+ byte PWME4 :1; /* Pulse Width Channel 4 Enable */\r
+ byte PWME5 :1; /* Pulse Width Channel 5 Enable */\r
+ byte PWME6 :1; /* Pulse Width Channel 6 Enable */\r
+ byte PWME7 :1; /* Pulse Width Channel 7 Enable */\r
+ } Bits;\r
+ struct {\r
+ byte grpPWME :8;\r
+ } MergedBits;\r
+} PWMESTR;\r
+extern volatile PWMESTR _PWME @(REG_BASE + 0x000000E0);\r
+#define PWME _PWME.Byte\r
+#define PWME_PWME0 _PWME.Bits.PWME0\r
+#define PWME_PWME1 _PWME.Bits.PWME1\r
+#define PWME_PWME2 _PWME.Bits.PWME2\r
+#define PWME_PWME3 _PWME.Bits.PWME3\r
+#define PWME_PWME4 _PWME.Bits.PWME4\r
+#define PWME_PWME5 _PWME.Bits.PWME5\r
+#define PWME_PWME6 _PWME.Bits.PWME6\r
+#define PWME_PWME7 _PWME.Bits.PWME7\r
+#define PWME_PWME _PWME.MergedBits.grpPWME\r
+\r
+\r
+/*** PWMPOL - PWM Polarity Register; 0x000000E1 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PPOL0 :1; /* Pulse Width Channel 0 Polarity */\r
+ byte PPOL1 :1; /* Pulse Width Channel 1 Polarity */\r
+ byte PPOL2 :1; /* Pulse Width Channel 2 Polarity */\r
+ byte PPOL3 :1; /* Pulse Width Channel 3 Polarity */\r
+ byte PPOL4 :1; /* Pulse Width Channel 4 Polarity */\r
+ byte PPOL5 :1; /* Pulse Width Channel 5 Polarity */\r
+ byte PPOL6 :1; /* Pulse Width Channel 6 Polarity */\r
+ byte PPOL7 :1; /* Pulse Width Channel 7 Polarity */\r
+ } Bits;\r
+ struct {\r
+ byte grpPPOL :8;\r
+ } MergedBits;\r
+} PWMPOLSTR;\r
+extern volatile PWMPOLSTR _PWMPOL @(REG_BASE + 0x000000E1);\r
+#define PWMPOL _PWMPOL.Byte\r
+#define PWMPOL_PPOL0 _PWMPOL.Bits.PPOL0\r
+#define PWMPOL_PPOL1 _PWMPOL.Bits.PPOL1\r
+#define PWMPOL_PPOL2 _PWMPOL.Bits.PPOL2\r
+#define PWMPOL_PPOL3 _PWMPOL.Bits.PPOL3\r
+#define PWMPOL_PPOL4 _PWMPOL.Bits.PPOL4\r
+#define PWMPOL_PPOL5 _PWMPOL.Bits.PPOL5\r
+#define PWMPOL_PPOL6 _PWMPOL.Bits.PPOL6\r
+#define PWMPOL_PPOL7 _PWMPOL.Bits.PPOL7\r
+#define PWMPOL_PPOL _PWMPOL.MergedBits.grpPPOL\r
+\r
+\r
+/*** PWMCLK - PWM Clock Select Register; 0x000000E2 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PCLK0 :1; /* Pulse Width Channel 0 Clock Select */\r
+ byte PCLK1 :1; /* Pulse Width Channel 1 Clock Select */\r
+ byte PCLK2 :1; /* Pulse Width Channel 2 Clock Select */\r
+ byte PCLK3 :1; /* Pulse Width Channel 3 Clock Select */\r
+ byte PCLK4 :1; /* Pulse Width Channel 4 Clock Select */\r
+ byte PCLK5 :1; /* Pulse Width Channel 5 Clock Select */\r
+ byte PCLK6 :1; /* Pulse Width Channel 6 Clock Select */\r
+ byte PCLK7 :1; /* Pulse Width Channel 7 Clock Select */\r
+ } Bits;\r
+ struct {\r
+ byte grpPCLK :8;\r
+ } MergedBits;\r
+} PWMCLKSTR;\r
+extern volatile PWMCLKSTR _PWMCLK @(REG_BASE + 0x000000E2);\r
+#define PWMCLK _PWMCLK.Byte\r
+#define PWMCLK_PCLK0 _PWMCLK.Bits.PCLK0\r
+#define PWMCLK_PCLK1 _PWMCLK.Bits.PCLK1\r
+#define PWMCLK_PCLK2 _PWMCLK.Bits.PCLK2\r
+#define PWMCLK_PCLK3 _PWMCLK.Bits.PCLK3\r
+#define PWMCLK_PCLK4 _PWMCLK.Bits.PCLK4\r
+#define PWMCLK_PCLK5 _PWMCLK.Bits.PCLK5\r
+#define PWMCLK_PCLK6 _PWMCLK.Bits.PCLK6\r
+#define PWMCLK_PCLK7 _PWMCLK.Bits.PCLK7\r
+#define PWMCLK_PCLK _PWMCLK.MergedBits.grpPCLK\r
+\r
+\r
+/*** PWMPRCLK - PWM Prescale Clock Select Register; 0x000000E3 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PCKA0 :1; /* Prescaler Select for Clock A 0 */\r
+ byte PCKA1 :1; /* Prescaler Select for Clock A 1 */\r
+ byte PCKA2 :1; /* Prescaler Select for Clock A 2 */\r
+ byte :1; \r
+ byte PCKB0 :1; /* Prescaler Select for Clock B 0 */\r
+ byte PCKB1 :1; /* Prescaler Select for Clock B 1 */\r
+ byte PCKB2 :1; /* Prescaler Select for Clock B 2 */\r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpPCKA :3;\r
+ byte :1;\r
+ byte grpPCKB :3;\r
+ byte :1;\r
+ } MergedBits;\r
+} PWMPRCLKSTR;\r
+extern volatile PWMPRCLKSTR _PWMPRCLK @(REG_BASE + 0x000000E3);\r
+#define PWMPRCLK _PWMPRCLK.Byte\r
+#define PWMPRCLK_PCKA0 _PWMPRCLK.Bits.PCKA0\r
+#define PWMPRCLK_PCKA1 _PWMPRCLK.Bits.PCKA1\r
+#define PWMPRCLK_PCKA2 _PWMPRCLK.Bits.PCKA2\r
+#define PWMPRCLK_PCKB0 _PWMPRCLK.Bits.PCKB0\r
+#define PWMPRCLK_PCKB1 _PWMPRCLK.Bits.PCKB1\r
+#define PWMPRCLK_PCKB2 _PWMPRCLK.Bits.PCKB2\r
+#define PWMPRCLK_PCKA _PWMPRCLK.MergedBits.grpPCKA\r
+#define PWMPRCLK_PCKB _PWMPRCLK.MergedBits.grpPCKB\r
+\r
+\r
+/*** PWMCAE - PWM Center Align Enable Register; 0x000000E4 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte CAE0 :1; /* Center Aligned Output Mode on channel 0 */\r
+ byte CAE1 :1; /* Center Aligned Output Mode on channel 1 */\r
+ byte CAE2 :1; /* Center Aligned Output Mode on channel 2 */\r
+ byte CAE3 :1; /* Center Aligned Output Mode on channel 3 */\r
+ byte CAE4 :1; /* Center Aligned Output Mode on channel 4 */\r
+ byte CAE5 :1; /* Center Aligned Output Mode on channel 5 */\r
+ byte CAE6 :1; /* Center Aligned Output Mode on channel 6 */\r
+ byte CAE7 :1; /* Center Aligned Output Mode on channel 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpCAE :8;\r
+ } MergedBits;\r
+} PWMCAESTR;\r
+extern volatile PWMCAESTR _PWMCAE @(REG_BASE + 0x000000E4);\r
+#define PWMCAE _PWMCAE.Byte\r
+#define PWMCAE_CAE0 _PWMCAE.Bits.CAE0\r
+#define PWMCAE_CAE1 _PWMCAE.Bits.CAE1\r
+#define PWMCAE_CAE2 _PWMCAE.Bits.CAE2\r
+#define PWMCAE_CAE3 _PWMCAE.Bits.CAE3\r
+#define PWMCAE_CAE4 _PWMCAE.Bits.CAE4\r
+#define PWMCAE_CAE5 _PWMCAE.Bits.CAE5\r
+#define PWMCAE_CAE6 _PWMCAE.Bits.CAE6\r
+#define PWMCAE_CAE7 _PWMCAE.Bits.CAE7\r
+#define PWMCAE_CAE _PWMCAE.MergedBits.grpCAE\r
+\r
+\r
+/*** PWMCTL - PWM Control Register; 0x000000E5 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte PFRZ :1; /* PWM Counters Stop in Freeze Mode */\r
+ byte PSWAI :1; /* PWM Stops in Wait Mode */\r
+ byte CON01 :1; /* Concatenate channels 0 and 1 */\r
+ byte CON23 :1; /* Concatenate channels 2 and 3 */\r
+ byte CON45 :1; /* Concatenate channels 4 and 5 */\r
+ byte CON67 :1; /* Concatenate channels 6 and 7 */\r
+ } Bits;\r
+} PWMCTLSTR;\r
+extern volatile PWMCTLSTR _PWMCTL @(REG_BASE + 0x000000E5);\r
+#define PWMCTL _PWMCTL.Byte\r
+#define PWMCTL_PFRZ _PWMCTL.Bits.PFRZ\r
+#define PWMCTL_PSWAI _PWMCTL.Bits.PSWAI\r
+#define PWMCTL_CON01 _PWMCTL.Bits.CON01\r
+#define PWMCTL_CON23 _PWMCTL.Bits.CON23\r
+#define PWMCTL_CON45 _PWMCTL.Bits.CON45\r
+#define PWMCTL_CON67 _PWMCTL.Bits.CON67\r
+\r
+\r
+/*** PWMSCLA - PWM Scale A Register; 0x000000E8 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* PWM Scale A Bit 0 */\r
+ byte BIT1 :1; /* PWM Scale A Bit 1 */\r
+ byte BIT2 :1; /* PWM Scale A Bit 2 */\r
+ byte BIT3 :1; /* PWM Scale A Bit 3 */\r
+ byte BIT4 :1; /* PWM Scale A Bit 4 */\r
+ byte BIT5 :1; /* PWM Scale A Bit 5 */\r
+ byte BIT6 :1; /* PWM Scale A Bit 6 */\r
+ byte BIT7 :1; /* PWM Scale A Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+} PWMSCLASTR;\r
+extern volatile PWMSCLASTR _PWMSCLA @(REG_BASE + 0x000000E8);\r
+#define PWMSCLA _PWMSCLA.Byte\r
+#define PWMSCLA_BIT0 _PWMSCLA.Bits.BIT0\r
+#define PWMSCLA_BIT1 _PWMSCLA.Bits.BIT1\r
+#define PWMSCLA_BIT2 _PWMSCLA.Bits.BIT2\r
+#define PWMSCLA_BIT3 _PWMSCLA.Bits.BIT3\r
+#define PWMSCLA_BIT4 _PWMSCLA.Bits.BIT4\r
+#define PWMSCLA_BIT5 _PWMSCLA.Bits.BIT5\r
+#define PWMSCLA_BIT6 _PWMSCLA.Bits.BIT6\r
+#define PWMSCLA_BIT7 _PWMSCLA.Bits.BIT7\r
+#define PWMSCLA_BIT _PWMSCLA.MergedBits.grpBIT\r
+\r
+\r
+/*** PWMSCLB - PWM Scale B Register; 0x000000E9 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte BIT0 :1; /* PWM Scale B Bit 0 */\r
+ byte BIT1 :1; /* PWM Scale B Bit 1 */\r
+ byte BIT2 :1; /* PWM Scale B Bit 2 */\r
+ byte BIT3 :1; /* PWM Scale B Bit 3 */\r
+ byte BIT4 :1; /* PWM Scale B Bit 4 */\r
+ byte BIT5 :1; /* PWM Scale B Bit 5 */\r
+ byte BIT6 :1; /* PWM Scale B Bit 6 */\r
+ byte BIT7 :1; /* PWM Scale B Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBIT :8;\r
+ } MergedBits;\r
+} PWMSCLBSTR;\r
+extern volatile PWMSCLBSTR _PWMSCLB @(REG_BASE + 0x000000E9);\r
+#define PWMSCLB _PWMSCLB.Byte\r
+#define PWMSCLB_BIT0 _PWMSCLB.Bits.BIT0\r
+#define PWMSCLB_BIT1 _PWMSCLB.Bits.BIT1\r
+#define PWMSCLB_BIT2 _PWMSCLB.Bits.BIT2\r
+#define PWMSCLB_BIT3 _PWMSCLB.Bits.BIT3\r
+#define PWMSCLB_BIT4 _PWMSCLB.Bits.BIT4\r
+#define PWMSCLB_BIT5 _PWMSCLB.Bits.BIT5\r
+#define PWMSCLB_BIT6 _PWMSCLB.Bits.BIT6\r
+#define PWMSCLB_BIT7 _PWMSCLB.Bits.BIT7\r
+#define PWMSCLB_BIT _PWMSCLB.MergedBits.grpBIT\r
+\r
+\r
+/*** PWMSDN - PWM Shutdown Register; 0x000000FE ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PWM7ENA :1; /* PWM emergency shutdown Enable */\r
+ byte PWM7INL :1; /* PWM shutdown active input level for ch. 7 */\r
+ byte PWM7IN :1; /* PWM channel 7 input status */\r
+ byte :1; \r
+ byte PWMLVL :1; /* PWM shutdown output Level */\r
+ byte PWMRSTRT :1; /* PWM Restart */\r
+ byte PWMIE :1; /* PWM Interrupt Enable */\r
+ byte PWMIF :1; /* PWM Interrupt Flag */\r
+ } Bits;\r
+} PWMSDNSTR;\r
+extern volatile PWMSDNSTR _PWMSDN @(REG_BASE + 0x000000FE);\r
+#define PWMSDN _PWMSDN.Byte\r
+#define PWMSDN_PWM7ENA _PWMSDN.Bits.PWM7ENA\r
+#define PWMSDN_PWM7INL _PWMSDN.Bits.PWM7INL\r
+#define PWMSDN_PWM7IN _PWMSDN.Bits.PWM7IN\r
+#define PWMSDN_PWMLVL _PWMSDN.Bits.PWMLVL\r
+#define PWMSDN_PWMRSTRT _PWMSDN.Bits.PWMRSTRT\r
+#define PWMSDN_PWMIE _PWMSDN.Bits.PWMIE\r
+#define PWMSDN_PWMIF _PWMSDN.Bits.PWMIF\r
+\r
+\r
+/*** FCLKDIV - Flash Clock Divider Register; 0x00000100 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte FDIV0 :1; /* Flash Clock Divider Bit 0 */\r
+ byte FDIV1 :1; /* Flash Clock Divider Bit 1 */\r
+ byte FDIV2 :1; /* Flash Clock Divider Bit 2 */\r
+ byte FDIV3 :1; /* Flash Clock Divider Bit 3 */\r
+ byte FDIV4 :1; /* Flash Clock Divider Bit 4 */\r
+ byte FDIV5 :1; /* Flash Clock Divider Bit 5 */\r
+ byte PRDIV8 :1; /* Enable Prescaler by 8 */\r
+ byte FDIVLD :1; /* Flash Clock Divider Loaded */\r
+ } Bits;\r
+ struct {\r
+ byte grpFDIV :6;\r
+ byte grpPRDIV_8 :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} FCLKDIVSTR;\r
+extern volatile FCLKDIVSTR _FCLKDIV @(REG_BASE + 0x00000100);\r
+#define FCLKDIV _FCLKDIV.Byte\r
+#define FCLKDIV_FDIV0 _FCLKDIV.Bits.FDIV0\r
+#define FCLKDIV_FDIV1 _FCLKDIV.Bits.FDIV1\r
+#define FCLKDIV_FDIV2 _FCLKDIV.Bits.FDIV2\r
+#define FCLKDIV_FDIV3 _FCLKDIV.Bits.FDIV3\r
+#define FCLKDIV_FDIV4 _FCLKDIV.Bits.FDIV4\r
+#define FCLKDIV_FDIV5 _FCLKDIV.Bits.FDIV5\r
+#define FCLKDIV_PRDIV8 _FCLKDIV.Bits.PRDIV8\r
+#define FCLKDIV_FDIVLD _FCLKDIV.Bits.FDIVLD\r
+#define FCLKDIV_FDIV _FCLKDIV.MergedBits.grpFDIV\r
+\r
+\r
+/*** FSEC - Flash Security Register; 0x00000101 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte SEC0 :1; /* Memory security bit 0 */\r
+ byte SEC1 :1; /* Memory security bit 1 */\r
+ byte NV2 :1; /* Non Volatile flag bit 2 */\r
+ byte NV3 :1; /* Non Volatile flag bit 3 */\r
+ byte NV4 :1; /* Non Volatile flag bit 4 */\r
+ byte NV5 :1; /* Non Volatile flag bit 5 */\r
+ byte NV6 :1; /* Non Volatile flag bit 6 */\r
+ byte KEYEN :1; /* Enable backdoor key to security */\r
+ } Bits;\r
+ struct {\r
+ byte grpSEC :2;\r
+ byte grpNV_2 :5;\r
+ byte :1;\r
+ } MergedBits;\r
+} FSECSTR;\r
+extern volatile FSECSTR _FSEC @(REG_BASE + 0x00000101);\r
+#define FSEC _FSEC.Byte\r
+#define FSEC_SEC0 _FSEC.Bits.SEC0\r
+#define FSEC_SEC1 _FSEC.Bits.SEC1\r
+#define FSEC_NV2 _FSEC.Bits.NV2\r
+#define FSEC_NV3 _FSEC.Bits.NV3\r
+#define FSEC_NV4 _FSEC.Bits.NV4\r
+#define FSEC_NV5 _FSEC.Bits.NV5\r
+#define FSEC_NV6 _FSEC.Bits.NV6\r
+#define FSEC_KEYEN _FSEC.Bits.KEYEN\r
+#define FSEC_SEC _FSEC.MergedBits.grpSEC\r
+#define FSEC_NV_2 _FSEC.MergedBits.grpNV_2\r
+#define FSEC_NV FSEC_NV_2\r
+\r
+\r
+/*** FCNFG - Flash Configuration Register; 0x00000103 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte BKSEL0 :1; /* Register bank select 0 */\r
+ byte BKSEL1 :1; /* Register bank select 1 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte KEYACC :1; /* Enable Security Key Writing */\r
+ byte CCIE :1; /* Command Complete Interrupt Enable */\r
+ byte CBEIE :1; /* Command Buffers Empty Interrupt Enable */\r
+ } Bits;\r
+ struct {\r
+ byte grpBKSEL :2;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} FCNFGSTR;\r
+extern volatile FCNFGSTR _FCNFG @(REG_BASE + 0x00000103);\r
+#define FCNFG _FCNFG.Byte\r
+#define FCNFG_BKSEL0 _FCNFG.Bits.BKSEL0\r
+#define FCNFG_BKSEL1 _FCNFG.Bits.BKSEL1\r
+#define FCNFG_KEYACC _FCNFG.Bits.KEYACC\r
+#define FCNFG_CCIE _FCNFG.Bits.CCIE\r
+#define FCNFG_CBEIE _FCNFG.Bits.CBEIE\r
+#define FCNFG_BKSEL _FCNFG.MergedBits.grpBKSEL\r
+\r
+\r
+/*** FPROT - Flash Protection Register; 0x00000104 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte FPLS0 :1; /* Flash Protection Lower Address size 0 */\r
+ byte FPLS1 :1; /* Flash Protection Lower Address size 1 */\r
+ byte FPLDIS :1; /* Flash Protection Lower address range disable */\r
+ byte FPHS0 :1; /* Flash Protection Higher address size 0 */\r
+ byte FPHS1 :1; /* Flash Protection Higher address size 1 */\r
+ byte FPHDIS :1; /* Flash Protection Higher address range disable */\r
+ byte NV6 :1; /* Non Volatile Flag Bit */\r
+ byte FPOPEN :1; /* Opens the flash block or subsections of it for program or erase */\r
+ } Bits;\r
+ struct {\r
+ byte grpFPLS :2;\r
+ byte :1;\r
+ byte grpFPHS :2;\r
+ byte :1;\r
+ byte grpNV_6 :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} FPROTSTR;\r
+extern volatile FPROTSTR _FPROT @(REG_BASE + 0x00000104);\r
+#define FPROT _FPROT.Byte\r
+#define FPROT_FPLS0 _FPROT.Bits.FPLS0\r
+#define FPROT_FPLS1 _FPROT.Bits.FPLS1\r
+#define FPROT_FPLDIS _FPROT.Bits.FPLDIS\r
+#define FPROT_FPHS0 _FPROT.Bits.FPHS0\r
+#define FPROT_FPHS1 _FPROT.Bits.FPHS1\r
+#define FPROT_FPHDIS _FPROT.Bits.FPHDIS\r
+#define FPROT_NV6 _FPROT.Bits.NV6\r
+#define FPROT_FPOPEN _FPROT.Bits.FPOPEN\r
+#define FPROT_FPLS _FPROT.MergedBits.grpFPLS\r
+#define FPROT_FPHS _FPROT.MergedBits.grpFPHS\r
+\r
+\r
+/*** FSTAT - Flash Status Register; 0x00000105 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte BLANK :1; /* Blank Verify Flag */\r
+ byte :1; \r
+ byte ACCERR :1; /* Access error */\r
+ byte PVIOL :1; /* Protection violation */\r
+ byte CCIF :1; /* Command Complete Interrupt Flag */\r
+ byte CBEIF :1; /* Command Buffers Empty Interrupt Flag */\r
+ } Bits;\r
+} FSTATSTR;\r
+extern volatile FSTATSTR _FSTAT @(REG_BASE + 0x00000105);\r
+#define FSTAT _FSTAT.Byte\r
+#define FSTAT_BLANK _FSTAT.Bits.BLANK\r
+#define FSTAT_ACCERR _FSTAT.Bits.ACCERR\r
+#define FSTAT_PVIOL _FSTAT.Bits.PVIOL\r
+#define FSTAT_CCIF _FSTAT.Bits.CCIF\r
+#define FSTAT_CBEIF _FSTAT.Bits.CBEIF\r
+\r
+\r
+/*** FCMD - Flash Command Buffer and Register; 0x00000106 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte CMDB0 :1; /* NVM User Mode Command Bit 0 */\r
+ byte :1; \r
+ byte CMDB2 :1; /* NVM User Mode Command Bit 2 */\r
+ byte :1; \r
+ byte :1; \r
+ byte CMDB5 :1; /* NVM User Mode Command Bit 5 */\r
+ byte CMDB6 :1; /* NVM User Mode Command Bit 6 */\r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpCMDB :1;\r
+ byte :1;\r
+ byte grpCMDB_2 :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpCMDB_5 :2;\r
+ byte :1;\r
+ } MergedBits;\r
+} FCMDSTR;\r
+extern volatile FCMDSTR _FCMD @(REG_BASE + 0x00000106);\r
+#define FCMD _FCMD.Byte\r
+#define FCMD_CMDB0 _FCMD.Bits.CMDB0\r
+#define FCMD_CMDB2 _FCMD.Bits.CMDB2\r
+#define FCMD_CMDB5 _FCMD.Bits.CMDB5\r
+#define FCMD_CMDB6 _FCMD.Bits.CMDB6\r
+#define FCMD_CMDB_5 _FCMD.MergedBits.grpCMDB_5\r
+#define FCMD_CMDB FCMD_CMDB_5\r
+\r
+\r
+/*** CANCTL0 - MSCAN Control 0 Register; 0x00000140 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte INITRQ :1; /* Initialization Mode Request */\r
+ byte SLPRQ :1; /* Sleep Mode Request */\r
+ byte WUPE :1; /* Wake-Up Enable */\r
+ byte TIME :1; /* Timer Enable */\r
+ byte SYNCH :1; /* Synchronized Status */\r
+ byte CSWAI :1; /* CAN Stops in Wait Mode */\r
+ byte RXACT :1; /* Receiver Active Status */\r
+ byte RXFRM :1; /* Received Frame Flag */\r
+ } Bits;\r
+} CANCTL0STR;\r
+extern volatile CANCTL0STR _CANCTL0 @(REG_BASE + 0x00000140);\r
+#define CANCTL0 _CANCTL0.Byte\r
+#define CANCTL0_INITRQ _CANCTL0.Bits.INITRQ\r
+#define CANCTL0_SLPRQ _CANCTL0.Bits.SLPRQ\r
+#define CANCTL0_WUPE _CANCTL0.Bits.WUPE\r
+#define CANCTL0_TIME _CANCTL0.Bits.TIME\r
+#define CANCTL0_SYNCH _CANCTL0.Bits.SYNCH\r
+#define CANCTL0_CSWAI _CANCTL0.Bits.CSWAI\r
+#define CANCTL0_RXACT _CANCTL0.Bits.RXACT\r
+#define CANCTL0_RXFRM _CANCTL0.Bits.RXFRM\r
+\r
+\r
+/*** CANCTL1 - MSCAN Control 1 Register; 0x00000141 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte INITAK :1; /* Initialization Mode Acknowledge */\r
+ byte SLPAK :1; /* Sleep Mode Acknowledge */\r
+ byte WUPM :1; /* Wake-Up Mode */\r
+ byte :1; \r
+ byte LISTEN :1; /* Listen Only Mode */\r
+ byte LOOPB :1; /* Loop Back Self Test Mode */\r
+ byte CLKSRC :1; /* MSCAN Clock Source */\r
+ byte CANE :1; /* MSCAN Enable */\r
+ } Bits;\r
+} CANCTL1STR;\r
+extern volatile CANCTL1STR _CANCTL1 @(REG_BASE + 0x00000141);\r
+#define CANCTL1 _CANCTL1.Byte\r
+#define CANCTL1_INITAK _CANCTL1.Bits.INITAK\r
+#define CANCTL1_SLPAK _CANCTL1.Bits.SLPAK\r
+#define CANCTL1_WUPM _CANCTL1.Bits.WUPM\r
+#define CANCTL1_LISTEN _CANCTL1.Bits.LISTEN\r
+#define CANCTL1_LOOPB _CANCTL1.Bits.LOOPB\r
+#define CANCTL1_CLKSRC _CANCTL1.Bits.CLKSRC\r
+#define CANCTL1_CANE _CANCTL1.Bits.CANE\r
+\r
+\r
+/*** CANBTR0 - MSCAN Bus Timing Register 0; 0x00000142 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte BRP0 :1; /* Baud Rate Prescaler 0 */\r
+ byte BRP1 :1; /* Baud Rate Prescaler 1 */\r
+ byte BRP2 :1; /* Baud Rate Prescaler 2 */\r
+ byte BRP3 :1; /* Baud Rate Prescaler 3 */\r
+ byte BRP4 :1; /* Baud Rate Prescaler 4 */\r
+ byte BRP5 :1; /* Baud Rate Prescaler 5 */\r
+ byte SJW0 :1; /* Synchronization Jump Width 0 */\r
+ byte SJW1 :1; /* Synchronization Jump Width 1 */\r
+ } Bits;\r
+ struct {\r
+ byte grpBRP :6;\r
+ byte grpSJW :2;\r
+ } MergedBits;\r
+} CANBTR0STR;\r
+extern volatile CANBTR0STR _CANBTR0 @(REG_BASE + 0x00000142);\r
+#define CANBTR0 _CANBTR0.Byte\r
+#define CANBTR0_BRP0 _CANBTR0.Bits.BRP0\r
+#define CANBTR0_BRP1 _CANBTR0.Bits.BRP1\r
+#define CANBTR0_BRP2 _CANBTR0.Bits.BRP2\r
+#define CANBTR0_BRP3 _CANBTR0.Bits.BRP3\r
+#define CANBTR0_BRP4 _CANBTR0.Bits.BRP4\r
+#define CANBTR0_BRP5 _CANBTR0.Bits.BRP5\r
+#define CANBTR0_SJW0 _CANBTR0.Bits.SJW0\r
+#define CANBTR0_SJW1 _CANBTR0.Bits.SJW1\r
+#define CANBTR0_BRP _CANBTR0.MergedBits.grpBRP\r
+#define CANBTR0_SJW _CANBTR0.MergedBits.grpSJW\r
+\r
+\r
+/*** CANBTR1 - MSCAN Bus Timing Register 1; 0x00000143 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte TSEG10 :1; /* Time Segment 1 */\r
+ byte TSEG11 :1; /* Time Segment 1 */\r
+ byte TSEG12 :1; /* Time Segment 1 */\r
+ byte TSEG13 :1; /* Time Segment 1 */\r
+ byte TSEG20 :1; /* Time Segment 2 */\r
+ byte TSEG21 :1; /* Time Segment 2 */\r
+ byte TSEG22 :1; /* Time Segment 2 */\r
+ byte SAMP :1; /* Sampling */\r
+ } Bits;\r
+ struct {\r
+ byte grpTSEG_10 :4;\r
+ byte grpTSEG_20 :3;\r
+ byte :1;\r
+ } MergedBits;\r
+} CANBTR1STR;\r
+extern volatile CANBTR1STR _CANBTR1 @(REG_BASE + 0x00000143);\r
+#define CANBTR1 _CANBTR1.Byte\r
+#define CANBTR1_TSEG10 _CANBTR1.Bits.TSEG10\r
+#define CANBTR1_TSEG11 _CANBTR1.Bits.TSEG11\r
+#define CANBTR1_TSEG12 _CANBTR1.Bits.TSEG12\r
+#define CANBTR1_TSEG13 _CANBTR1.Bits.TSEG13\r
+#define CANBTR1_TSEG20 _CANBTR1.Bits.TSEG20\r
+#define CANBTR1_TSEG21 _CANBTR1.Bits.TSEG21\r
+#define CANBTR1_TSEG22 _CANBTR1.Bits.TSEG22\r
+#define CANBTR1_SAMP _CANBTR1.Bits.SAMP\r
+#define CANBTR1_TSEG_10 _CANBTR1.MergedBits.grpTSEG_10\r
+#define CANBTR1_TSEG_20 _CANBTR1.MergedBits.grpTSEG_20\r
+#define CANBTR1_TSEG CANBTR1_TSEG_10\r
+\r
+\r
+/*** CANRFLG - MSCAN Receiver Flag Register; 0x00000144 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte RXF :1; /* Receive Buffer Full */\r
+ byte OVRIF :1; /* Overrun Interrupt Flag */\r
+ byte TSTAT0 :1; /* Transmitter Status Bit 0 */\r
+ byte TSTAT1 :1; /* Transmitter Status Bit 1 */\r
+ byte RSTAT0 :1; /* Receiver Status Bit 0 */\r
+ byte RSTAT1 :1; /* Receiver Status Bit 1 */\r
+ byte CSCIF :1; /* CAN Status Change Interrupt Flag */\r
+ byte WUPIF :1; /* Wake-up Interrupt Flag */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte grpTSTAT :2;\r
+ byte grpRSTAT :2;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CANRFLGSTR;\r
+extern volatile CANRFLGSTR _CANRFLG @(REG_BASE + 0x00000144);\r
+#define CANRFLG _CANRFLG.Byte\r
+#define CANRFLG_RXF _CANRFLG.Bits.RXF\r
+#define CANRFLG_OVRIF _CANRFLG.Bits.OVRIF\r
+#define CANRFLG_TSTAT0 _CANRFLG.Bits.TSTAT0\r
+#define CANRFLG_TSTAT1 _CANRFLG.Bits.TSTAT1\r
+#define CANRFLG_RSTAT0 _CANRFLG.Bits.RSTAT0\r
+#define CANRFLG_RSTAT1 _CANRFLG.Bits.RSTAT1\r
+#define CANRFLG_CSCIF _CANRFLG.Bits.CSCIF\r
+#define CANRFLG_WUPIF _CANRFLG.Bits.WUPIF\r
+#define CANRFLG_TSTAT _CANRFLG.MergedBits.grpTSTAT\r
+#define CANRFLG_RSTAT _CANRFLG.MergedBits.grpRSTAT\r
+\r
+\r
+/*** CANRIER - MSCAN Receiver Interrupt Enable Register; 0x00000145 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte RXFIE :1; /* Receiver Full Interrupt Enable */\r
+ byte OVRIE :1; /* Overrun Interrupt Enable */\r
+ byte TSTATE0 :1; /* Transmitter Status Change Enable 0 */\r
+ byte TSTATE1 :1; /* Transmitter Status Change Enable 1 */\r
+ byte RSTATE0 :1; /* Receiver Status Change Enable 0 */\r
+ byte RSTATE1 :1; /* Receiver Status Change Enable 1 */\r
+ byte CSCIE :1; /* CAN Status Change Interrupt Enable */\r
+ byte WUPIE :1; /* Wake-up Interrupt Enable */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte grpTSTATE :2;\r
+ byte grpRSTATE :2;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CANRIERSTR;\r
+extern volatile CANRIERSTR _CANRIER @(REG_BASE + 0x00000145);\r
+#define CANRIER _CANRIER.Byte\r
+#define CANRIER_RXFIE _CANRIER.Bits.RXFIE\r
+#define CANRIER_OVRIE _CANRIER.Bits.OVRIE\r
+#define CANRIER_TSTATE0 _CANRIER.Bits.TSTATE0\r
+#define CANRIER_TSTATE1 _CANRIER.Bits.TSTATE1\r
+#define CANRIER_RSTATE0 _CANRIER.Bits.RSTATE0\r
+#define CANRIER_RSTATE1 _CANRIER.Bits.RSTATE1\r
+#define CANRIER_CSCIE _CANRIER.Bits.CSCIE\r
+#define CANRIER_WUPIE _CANRIER.Bits.WUPIE\r
+#define CANRIER_TSTATE _CANRIER.MergedBits.grpTSTATE\r
+#define CANRIER_RSTATE _CANRIER.MergedBits.grpRSTATE\r
+\r
+\r
+/*** CANTFLG - MSCAN Transmitter Flag Register; 0x00000146 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte TXE0 :1; /* Transmitter Buffer Empty 0 */\r
+ byte TXE1 :1; /* Transmitter Buffer Empty 1 */\r
+ byte TXE2 :1; /* Transmitter Buffer Empty 2 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpTXE :3;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CANTFLGSTR;\r
+extern volatile CANTFLGSTR _CANTFLG @(REG_BASE + 0x00000146);\r
+#define CANTFLG _CANTFLG.Byte\r
+#define CANTFLG_TXE0 _CANTFLG.Bits.TXE0\r
+#define CANTFLG_TXE1 _CANTFLG.Bits.TXE1\r
+#define CANTFLG_TXE2 _CANTFLG.Bits.TXE2\r
+#define CANTFLG_TXE _CANTFLG.MergedBits.grpTXE\r
+\r
+\r
+/*** CANTIER - MSCAN Transmitter Interrupt Enable Register; 0x00000147 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte TXEIE0 :1; /* Transmitter Empty Interrupt Enable 0 */\r
+ byte TXEIE1 :1; /* Transmitter Empty Interrupt Enable 1 */\r
+ byte TXEIE2 :1; /* Transmitter Empty Interrupt Enable 2 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpTXEIE :3;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CANTIERSTR;\r
+extern volatile CANTIERSTR _CANTIER @(REG_BASE + 0x00000147);\r
+#define CANTIER _CANTIER.Byte\r
+#define CANTIER_TXEIE0 _CANTIER.Bits.TXEIE0\r
+#define CANTIER_TXEIE1 _CANTIER.Bits.TXEIE1\r
+#define CANTIER_TXEIE2 _CANTIER.Bits.TXEIE2\r
+#define CANTIER_TXEIE _CANTIER.MergedBits.grpTXEIE\r
+\r
+\r
+/*** CANTARQ - MSCAN Transmitter Message Abort Request; 0x00000148 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ABTRQ0 :1; /* Abort Request 0 */\r
+ byte ABTRQ1 :1; /* Abort Request 1 */\r
+ byte ABTRQ2 :1; /* Abort Request 2 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpABTRQ :3;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CANTARQSTR;\r
+extern volatile CANTARQSTR _CANTARQ @(REG_BASE + 0x00000148);\r
+#define CANTARQ _CANTARQ.Byte\r
+#define CANTARQ_ABTRQ0 _CANTARQ.Bits.ABTRQ0\r
+#define CANTARQ_ABTRQ1 _CANTARQ.Bits.ABTRQ1\r
+#define CANTARQ_ABTRQ2 _CANTARQ.Bits.ABTRQ2\r
+#define CANTARQ_ABTRQ _CANTARQ.MergedBits.grpABTRQ\r
+\r
+\r
+/*** CANTAAK - MSCAN Transmitter Message Abort Control; 0x00000149 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ABTAK0 :1; /* Abort Acknowledge 0 */\r
+ byte ABTAK1 :1; /* Abort Acknowledge 1 */\r
+ byte ABTAK2 :1; /* Abort Acknowledge 2 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpABTAK :3;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CANTAAKSTR;\r
+extern volatile CANTAAKSTR _CANTAAK @(REG_BASE + 0x00000149);\r
+#define CANTAAK _CANTAAK.Byte\r
+#define CANTAAK_ABTAK0 _CANTAAK.Bits.ABTAK0\r
+#define CANTAAK_ABTAK1 _CANTAAK.Bits.ABTAK1\r
+#define CANTAAK_ABTAK2 _CANTAAK.Bits.ABTAK2\r
+#define CANTAAK_ABTAK _CANTAAK.MergedBits.grpABTAK\r
+\r
+\r
+/*** CANTBSEL - MSCAN Transmit Buffer Selection; 0x0000014A ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte TX0 :1; /* Transmit Buffer Select 0 */\r
+ byte TX1 :1; /* Transmit Buffer Select 1 */\r
+ byte TX2 :1; /* Transmit Buffer Select 2 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpTX :3;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CANTBSELSTR;\r
+extern volatile CANTBSELSTR _CANTBSEL @(REG_BASE + 0x0000014A);\r
+#define CANTBSEL _CANTBSEL.Byte\r
+#define CANTBSEL_TX0 _CANTBSEL.Bits.TX0\r
+#define CANTBSEL_TX1 _CANTBSEL.Bits.TX1\r
+#define CANTBSEL_TX2 _CANTBSEL.Bits.TX2\r
+#define CANTBSEL_TX _CANTBSEL.MergedBits.grpTX\r
+\r
+\r
+/*** CANIDAC - MSCAN Identifier Acceptance Control Register; 0x0000014B ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte IDHIT0 :1; /* Identifier Acceptance Hit Indicator 0 */\r
+ byte IDHIT1 :1; /* Identifier Acceptance Hit Indicator 1 */\r
+ byte IDHIT2 :1; /* Identifier Acceptance Hit Indicator 2 */\r
+ byte :1; \r
+ byte IDAM0 :1; /* Identifier Acceptance Mode 0 */\r
+ byte IDAM1 :1; /* Identifier Acceptance Mode 1 */\r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpIDHIT :3;\r
+ byte :1;\r
+ byte grpIDAM :2;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CANIDACSTR;\r
+extern volatile CANIDACSTR _CANIDAC @(REG_BASE + 0x0000014B);\r
+#define CANIDAC _CANIDAC.Byte\r
+#define CANIDAC_IDHIT0 _CANIDAC.Bits.IDHIT0\r
+#define CANIDAC_IDHIT1 _CANIDAC.Bits.IDHIT1\r
+#define CANIDAC_IDHIT2 _CANIDAC.Bits.IDHIT2\r
+#define CANIDAC_IDAM0 _CANIDAC.Bits.IDAM0\r
+#define CANIDAC_IDAM1 _CANIDAC.Bits.IDAM1\r
+#define CANIDAC_IDHIT _CANIDAC.MergedBits.grpIDHIT\r
+#define CANIDAC_IDAM _CANIDAC.MergedBits.grpIDAM\r
+\r
+\r
+/*** CANRXERR - MSCAN Receive Error Counter Register; 0x0000014E ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte RXERR0 :1; /* Bit 0 */\r
+ byte RXERR1 :1; /* Bit 1 */\r
+ byte RXERR2 :1; /* Bit 2 */\r
+ byte RXERR3 :1; /* Bit 3 */\r
+ byte RXERR4 :1; /* Bit 4 */\r
+ byte RXERR5 :1; /* Bit 5 */\r
+ byte RXERR6 :1; /* Bit 6 */\r
+ byte RXERR7 :1; /* Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpRXERR :8;\r
+ } MergedBits;\r
+} CANRXERRSTR;\r
+extern volatile CANRXERRSTR _CANRXERR @(REG_BASE + 0x0000014E);\r
+#define CANRXERR _CANRXERR.Byte\r
+#define CANRXERR_RXERR0 _CANRXERR.Bits.RXERR0\r
+#define CANRXERR_RXERR1 _CANRXERR.Bits.RXERR1\r
+#define CANRXERR_RXERR2 _CANRXERR.Bits.RXERR2\r
+#define CANRXERR_RXERR3 _CANRXERR.Bits.RXERR3\r
+#define CANRXERR_RXERR4 _CANRXERR.Bits.RXERR4\r
+#define CANRXERR_RXERR5 _CANRXERR.Bits.RXERR5\r
+#define CANRXERR_RXERR6 _CANRXERR.Bits.RXERR6\r
+#define CANRXERR_RXERR7 _CANRXERR.Bits.RXERR7\r
+#define CANRXERR_RXERR _CANRXERR.MergedBits.grpRXERR\r
+\r
+\r
+/*** CANTXERR - MSCAN Transmit Error Counter Register; 0x0000014F ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte TXERR0 :1; /* Bit 0 */\r
+ byte TXERR1 :1; /* Bit 1 */\r
+ byte TXERR2 :1; /* Bit 2 */\r
+ byte TXERR3 :1; /* Bit 3 */\r
+ byte TXERR4 :1; /* Bit 4 */\r
+ byte TXERR5 :1; /* Bit 5 */\r
+ byte TXERR6 :1; /* Bit 6 */\r
+ byte TXERR7 :1; /* Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpTXERR :8;\r
+ } MergedBits;\r
+} CANTXERRSTR;\r
+extern volatile CANTXERRSTR _CANTXERR @(REG_BASE + 0x0000014F);\r
+#define CANTXERR _CANTXERR.Byte\r
+#define CANTXERR_TXERR0 _CANTXERR.Bits.TXERR0\r
+#define CANTXERR_TXERR1 _CANTXERR.Bits.TXERR1\r
+#define CANTXERR_TXERR2 _CANTXERR.Bits.TXERR2\r
+#define CANTXERR_TXERR3 _CANTXERR.Bits.TXERR3\r
+#define CANTXERR_TXERR4 _CANTXERR.Bits.TXERR4\r
+#define CANTXERR_TXERR5 _CANTXERR.Bits.TXERR5\r
+#define CANTXERR_TXERR6 _CANTXERR.Bits.TXERR6\r
+#define CANTXERR_TXERR7 _CANTXERR.Bits.TXERR7\r
+#define CANTXERR_TXERR _CANTXERR.MergedBits.grpTXERR\r
+\r
+\r
+/*** CANIDAR0 - MSCAN Identifier Acceptance Register 0; 0x00000150 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AC0 :1; /* Acceptance Code Bit 0 */\r
+ byte AC1 :1; /* Acceptance Code Bit 1 */\r
+ byte AC2 :1; /* Acceptance Code Bit 2 */\r
+ byte AC3 :1; /* Acceptance Code Bit 3 */\r
+ byte AC4 :1; /* Acceptance Code Bit 4 */\r
+ byte AC5 :1; /* Acceptance Code Bit 5 */\r
+ byte AC6 :1; /* Acceptance Code Bit 6 */\r
+ byte AC7 :1; /* Acceptance Code Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAC :8;\r
+ } MergedBits;\r
+} CANIDAR0STR;\r
+extern volatile CANIDAR0STR _CANIDAR0 @(REG_BASE + 0x00000150);\r
+#define CANIDAR0 _CANIDAR0.Byte\r
+#define CANIDAR0_AC0 _CANIDAR0.Bits.AC0\r
+#define CANIDAR0_AC1 _CANIDAR0.Bits.AC1\r
+#define CANIDAR0_AC2 _CANIDAR0.Bits.AC2\r
+#define CANIDAR0_AC3 _CANIDAR0.Bits.AC3\r
+#define CANIDAR0_AC4 _CANIDAR0.Bits.AC4\r
+#define CANIDAR0_AC5 _CANIDAR0.Bits.AC5\r
+#define CANIDAR0_AC6 _CANIDAR0.Bits.AC6\r
+#define CANIDAR0_AC7 _CANIDAR0.Bits.AC7\r
+#define CANIDAR0_AC _CANIDAR0.MergedBits.grpAC\r
+\r
+\r
+/*** CANIDAR1 - MSCAN Identifier Acceptance Register 1; 0x00000151 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AC0 :1; /* Acceptance Code Bit 0 */\r
+ byte AC1 :1; /* Acceptance Code Bit 1 */\r
+ byte AC2 :1; /* Acceptance Code Bit 2 */\r
+ byte AC3 :1; /* Acceptance Code Bit 3 */\r
+ byte AC4 :1; /* Acceptance Code Bit 4 */\r
+ byte AC5 :1; /* Acceptance Code Bit 5 */\r
+ byte AC6 :1; /* Acceptance Code Bit 6 */\r
+ byte AC7 :1; /* Acceptance Code Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAC :8;\r
+ } MergedBits;\r
+} CANIDAR1STR;\r
+extern volatile CANIDAR1STR _CANIDAR1 @(REG_BASE + 0x00000151);\r
+#define CANIDAR1 _CANIDAR1.Byte\r
+#define CANIDAR1_AC0 _CANIDAR1.Bits.AC0\r
+#define CANIDAR1_AC1 _CANIDAR1.Bits.AC1\r
+#define CANIDAR1_AC2 _CANIDAR1.Bits.AC2\r
+#define CANIDAR1_AC3 _CANIDAR1.Bits.AC3\r
+#define CANIDAR1_AC4 _CANIDAR1.Bits.AC4\r
+#define CANIDAR1_AC5 _CANIDAR1.Bits.AC5\r
+#define CANIDAR1_AC6 _CANIDAR1.Bits.AC6\r
+#define CANIDAR1_AC7 _CANIDAR1.Bits.AC7\r
+#define CANIDAR1_AC _CANIDAR1.MergedBits.grpAC\r
+\r
+\r
+/*** CANIDAR2 - MSCAN Identifier Acceptance Register 2; 0x00000152 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AC0 :1; /* Acceptance Code Bit 0 */\r
+ byte AC1 :1; /* Acceptance Code Bit 1 */\r
+ byte AC2 :1; /* Acceptance Code Bit 2 */\r
+ byte AC3 :1; /* Acceptance Code Bit 3 */\r
+ byte AC4 :1; /* Acceptance Code Bit 4 */\r
+ byte AC5 :1; /* Acceptance Code Bit 5 */\r
+ byte AC6 :1; /* Acceptance Code Bit 6 */\r
+ byte AC7 :1; /* Acceptance Code Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAC :8;\r
+ } MergedBits;\r
+} CANIDAR2STR;\r
+extern volatile CANIDAR2STR _CANIDAR2 @(REG_BASE + 0x00000152);\r
+#define CANIDAR2 _CANIDAR2.Byte\r
+#define CANIDAR2_AC0 _CANIDAR2.Bits.AC0\r
+#define CANIDAR2_AC1 _CANIDAR2.Bits.AC1\r
+#define CANIDAR2_AC2 _CANIDAR2.Bits.AC2\r
+#define CANIDAR2_AC3 _CANIDAR2.Bits.AC3\r
+#define CANIDAR2_AC4 _CANIDAR2.Bits.AC4\r
+#define CANIDAR2_AC5 _CANIDAR2.Bits.AC5\r
+#define CANIDAR2_AC6 _CANIDAR2.Bits.AC6\r
+#define CANIDAR2_AC7 _CANIDAR2.Bits.AC7\r
+#define CANIDAR2_AC _CANIDAR2.MergedBits.grpAC\r
+\r
+\r
+/*** CANIDAR3 - MSCAN Identifier Acceptance Register 3; 0x00000153 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AC0 :1; /* Acceptance Code Bit 0 */\r
+ byte AC1 :1; /* Acceptance Code Bit 1 */\r
+ byte AC2 :1; /* Acceptance Code Bit 2 */\r
+ byte AC3 :1; /* Acceptance Code Bit 3 */\r
+ byte AC4 :1; /* Acceptance Code Bit 4 */\r
+ byte AC5 :1; /* Acceptance Code Bit 5 */\r
+ byte AC6 :1; /* Acceptance Code Bit 6 */\r
+ byte AC7 :1; /* Acceptance Code Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAC :8;\r
+ } MergedBits;\r
+} CANIDAR3STR;\r
+extern volatile CANIDAR3STR _CANIDAR3 @(REG_BASE + 0x00000153);\r
+#define CANIDAR3 _CANIDAR3.Byte\r
+#define CANIDAR3_AC0 _CANIDAR3.Bits.AC0\r
+#define CANIDAR3_AC1 _CANIDAR3.Bits.AC1\r
+#define CANIDAR3_AC2 _CANIDAR3.Bits.AC2\r
+#define CANIDAR3_AC3 _CANIDAR3.Bits.AC3\r
+#define CANIDAR3_AC4 _CANIDAR3.Bits.AC4\r
+#define CANIDAR3_AC5 _CANIDAR3.Bits.AC5\r
+#define CANIDAR3_AC6 _CANIDAR3.Bits.AC6\r
+#define CANIDAR3_AC7 _CANIDAR3.Bits.AC7\r
+#define CANIDAR3_AC _CANIDAR3.MergedBits.grpAC\r
+\r
+\r
+/*** CANIDMR0 - MSCAN Identifier Mask Register 0; 0x00000154 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AM0 :1; /* Acceptance Mask Bit 0 */\r
+ byte AM1 :1; /* Acceptance Mask Bit 1 */\r
+ byte AM2 :1; /* Acceptance Mask Bit 2 */\r
+ byte AM3 :1; /* Acceptance Mask Bit 3 */\r
+ byte AM4 :1; /* Acceptance Mask Bit 4 */\r
+ byte AM5 :1; /* Acceptance Mask Bit 5 */\r
+ byte AM6 :1; /* Acceptance Mask Bit 6 */\r
+ byte AM7 :1; /* Acceptance Mask Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAM :8;\r
+ } MergedBits;\r
+} CANIDMR0STR;\r
+extern volatile CANIDMR0STR _CANIDMR0 @(REG_BASE + 0x00000154);\r
+#define CANIDMR0 _CANIDMR0.Byte\r
+#define CANIDMR0_AM0 _CANIDMR0.Bits.AM0\r
+#define CANIDMR0_AM1 _CANIDMR0.Bits.AM1\r
+#define CANIDMR0_AM2 _CANIDMR0.Bits.AM2\r
+#define CANIDMR0_AM3 _CANIDMR0.Bits.AM3\r
+#define CANIDMR0_AM4 _CANIDMR0.Bits.AM4\r
+#define CANIDMR0_AM5 _CANIDMR0.Bits.AM5\r
+#define CANIDMR0_AM6 _CANIDMR0.Bits.AM6\r
+#define CANIDMR0_AM7 _CANIDMR0.Bits.AM7\r
+#define CANIDMR0_AM _CANIDMR0.MergedBits.grpAM\r
+\r
+\r
+/*** CANIDMR1 - MSCAN Identifier Mask Register 1; 0x00000155 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AM0 :1; /* Acceptance Mask Bit 0 */\r
+ byte AM1 :1; /* Acceptance Mask Bit 1 */\r
+ byte AM2 :1; /* Acceptance Mask Bit 2 */\r
+ byte AM3 :1; /* Acceptance Mask Bit 3 */\r
+ byte AM4 :1; /* Acceptance Mask Bit 4 */\r
+ byte AM5 :1; /* Acceptance Mask Bit 5 */\r
+ byte AM6 :1; /* Acceptance Mask Bit 6 */\r
+ byte AM7 :1; /* Acceptance Mask Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAM :8;\r
+ } MergedBits;\r
+} CANIDMR1STR;\r
+extern volatile CANIDMR1STR _CANIDMR1 @(REG_BASE + 0x00000155);\r
+#define CANIDMR1 _CANIDMR1.Byte\r
+#define CANIDMR1_AM0 _CANIDMR1.Bits.AM0\r
+#define CANIDMR1_AM1 _CANIDMR1.Bits.AM1\r
+#define CANIDMR1_AM2 _CANIDMR1.Bits.AM2\r
+#define CANIDMR1_AM3 _CANIDMR1.Bits.AM3\r
+#define CANIDMR1_AM4 _CANIDMR1.Bits.AM4\r
+#define CANIDMR1_AM5 _CANIDMR1.Bits.AM5\r
+#define CANIDMR1_AM6 _CANIDMR1.Bits.AM6\r
+#define CANIDMR1_AM7 _CANIDMR1.Bits.AM7\r
+#define CANIDMR1_AM _CANIDMR1.MergedBits.grpAM\r
+\r
+\r
+/*** CANIDMR2 - MSCAN Identifier Mask Register 2; 0x00000156 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AM0 :1; /* Acceptance Mask Bit 0 */\r
+ byte AM1 :1; /* Acceptance Mask Bit 1 */\r
+ byte AM2 :1; /* Acceptance Mask Bit 2 */\r
+ byte AM3 :1; /* Acceptance Mask Bit 3 */\r
+ byte AM4 :1; /* Acceptance Mask Bit 4 */\r
+ byte AM5 :1; /* Acceptance Mask Bit 5 */\r
+ byte AM6 :1; /* Acceptance Mask Bit 6 */\r
+ byte AM7 :1; /* Acceptance Mask Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAM :8;\r
+ } MergedBits;\r
+} CANIDMR2STR;\r
+extern volatile CANIDMR2STR _CANIDMR2 @(REG_BASE + 0x00000156);\r
+#define CANIDMR2 _CANIDMR2.Byte\r
+#define CANIDMR2_AM0 _CANIDMR2.Bits.AM0\r
+#define CANIDMR2_AM1 _CANIDMR2.Bits.AM1\r
+#define CANIDMR2_AM2 _CANIDMR2.Bits.AM2\r
+#define CANIDMR2_AM3 _CANIDMR2.Bits.AM3\r
+#define CANIDMR2_AM4 _CANIDMR2.Bits.AM4\r
+#define CANIDMR2_AM5 _CANIDMR2.Bits.AM5\r
+#define CANIDMR2_AM6 _CANIDMR2.Bits.AM6\r
+#define CANIDMR2_AM7 _CANIDMR2.Bits.AM7\r
+#define CANIDMR2_AM _CANIDMR2.MergedBits.grpAM\r
+\r
+\r
+/*** CANIDMR3 - MSCAN Identifier Mask Register 3; 0x00000157 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AM0 :1; /* Acceptance Mask Bit 0 */\r
+ byte AM1 :1; /* Acceptance Mask Bit 1 */\r
+ byte AM2 :1; /* Acceptance Mask Bit 2 */\r
+ byte AM3 :1; /* Acceptance Mask Bit 3 */\r
+ byte AM4 :1; /* Acceptance Mask Bit 4 */\r
+ byte AM5 :1; /* Acceptance Mask Bit 5 */\r
+ byte AM6 :1; /* Acceptance Mask Bit 6 */\r
+ byte AM7 :1; /* Acceptance Mask Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAM :8;\r
+ } MergedBits;\r
+} CANIDMR3STR;\r
+extern volatile CANIDMR3STR _CANIDMR3 @(REG_BASE + 0x00000157);\r
+#define CANIDMR3 _CANIDMR3.Byte\r
+#define CANIDMR3_AM0 _CANIDMR3.Bits.AM0\r
+#define CANIDMR3_AM1 _CANIDMR3.Bits.AM1\r
+#define CANIDMR3_AM2 _CANIDMR3.Bits.AM2\r
+#define CANIDMR3_AM3 _CANIDMR3.Bits.AM3\r
+#define CANIDMR3_AM4 _CANIDMR3.Bits.AM4\r
+#define CANIDMR3_AM5 _CANIDMR3.Bits.AM5\r
+#define CANIDMR3_AM6 _CANIDMR3.Bits.AM6\r
+#define CANIDMR3_AM7 _CANIDMR3.Bits.AM7\r
+#define CANIDMR3_AM _CANIDMR3.MergedBits.grpAM\r
+\r
+\r
+/*** CANIDAR4 - MSCAN Identifier Acceptance Register 4; 0x00000158 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AC0 :1; /* Acceptance Code Bit 0 */\r
+ byte AC1 :1; /* Acceptance Code Bit 1 */\r
+ byte AC2 :1; /* Acceptance Code Bit 2 */\r
+ byte AC3 :1; /* Acceptance Code Bit 3 */\r
+ byte AC4 :1; /* Acceptance Code Bit 4 */\r
+ byte AC5 :1; /* Acceptance Code Bit 5 */\r
+ byte AC6 :1; /* Acceptance Code Bit 6 */\r
+ byte AC7 :1; /* Acceptance Code Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAC :8;\r
+ } MergedBits;\r
+} CANIDAR4STR;\r
+extern volatile CANIDAR4STR _CANIDAR4 @(REG_BASE + 0x00000158);\r
+#define CANIDAR4 _CANIDAR4.Byte\r
+#define CANIDAR4_AC0 _CANIDAR4.Bits.AC0\r
+#define CANIDAR4_AC1 _CANIDAR4.Bits.AC1\r
+#define CANIDAR4_AC2 _CANIDAR4.Bits.AC2\r
+#define CANIDAR4_AC3 _CANIDAR4.Bits.AC3\r
+#define CANIDAR4_AC4 _CANIDAR4.Bits.AC4\r
+#define CANIDAR4_AC5 _CANIDAR4.Bits.AC5\r
+#define CANIDAR4_AC6 _CANIDAR4.Bits.AC6\r
+#define CANIDAR4_AC7 _CANIDAR4.Bits.AC7\r
+#define CANIDAR4_AC _CANIDAR4.MergedBits.grpAC\r
+\r
+\r
+/*** CANIDAR5 - MSCAN Identifier Acceptance Register 5; 0x00000159 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AC0 :1; /* Acceptance Code Bit 0 */\r
+ byte AC1 :1; /* Acceptance Code Bit 1 */\r
+ byte AC2 :1; /* Acceptance Code Bit 2 */\r
+ byte AC3 :1; /* Acceptance Code Bit 3 */\r
+ byte AC4 :1; /* Acceptance Code Bit 4 */\r
+ byte AC5 :1; /* Acceptance Code Bit 5 */\r
+ byte AC6 :1; /* Acceptance Code Bit 6 */\r
+ byte AC7 :1; /* Acceptance Code Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAC :8;\r
+ } MergedBits;\r
+} CANIDAR5STR;\r
+extern volatile CANIDAR5STR _CANIDAR5 @(REG_BASE + 0x00000159);\r
+#define CANIDAR5 _CANIDAR5.Byte\r
+#define CANIDAR5_AC0 _CANIDAR5.Bits.AC0\r
+#define CANIDAR5_AC1 _CANIDAR5.Bits.AC1\r
+#define CANIDAR5_AC2 _CANIDAR5.Bits.AC2\r
+#define CANIDAR5_AC3 _CANIDAR5.Bits.AC3\r
+#define CANIDAR5_AC4 _CANIDAR5.Bits.AC4\r
+#define CANIDAR5_AC5 _CANIDAR5.Bits.AC5\r
+#define CANIDAR5_AC6 _CANIDAR5.Bits.AC6\r
+#define CANIDAR5_AC7 _CANIDAR5.Bits.AC7\r
+#define CANIDAR5_AC _CANIDAR5.MergedBits.grpAC\r
+\r
+\r
+/*** CANIDAR6 - MSCAN Identifier Acceptance Register 6; 0x0000015A ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AC0 :1; /* Acceptance Code Bit 0 */\r
+ byte AC1 :1; /* Acceptance Code Bit 1 */\r
+ byte AC2 :1; /* Acceptance Code Bit 2 */\r
+ byte AC3 :1; /* Acceptance Code Bit 3 */\r
+ byte AC4 :1; /* Acceptance Code Bit 4 */\r
+ byte AC5 :1; /* Acceptance Code Bit 5 */\r
+ byte AC6 :1; /* Acceptance Code Bit 6 */\r
+ byte AC7 :1; /* Acceptance Code Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAC :8;\r
+ } MergedBits;\r
+} CANIDAR6STR;\r
+extern volatile CANIDAR6STR _CANIDAR6 @(REG_BASE + 0x0000015A);\r
+#define CANIDAR6 _CANIDAR6.Byte\r
+#define CANIDAR6_AC0 _CANIDAR6.Bits.AC0\r
+#define CANIDAR6_AC1 _CANIDAR6.Bits.AC1\r
+#define CANIDAR6_AC2 _CANIDAR6.Bits.AC2\r
+#define CANIDAR6_AC3 _CANIDAR6.Bits.AC3\r
+#define CANIDAR6_AC4 _CANIDAR6.Bits.AC4\r
+#define CANIDAR6_AC5 _CANIDAR6.Bits.AC5\r
+#define CANIDAR6_AC6 _CANIDAR6.Bits.AC6\r
+#define CANIDAR6_AC7 _CANIDAR6.Bits.AC7\r
+#define CANIDAR6_AC _CANIDAR6.MergedBits.grpAC\r
+\r
+\r
+/*** CANIDAR7 - MSCAN Identifier Acceptance Register 7; 0x0000015B ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AC0 :1; /* Acceptance Code Bit 0 */\r
+ byte AC1 :1; /* Acceptance Code Bit 1 */\r
+ byte AC2 :1; /* Acceptance Code Bit 2 */\r
+ byte AC3 :1; /* Acceptance Code Bit 3 */\r
+ byte AC4 :1; /* Acceptance Code Bit 4 */\r
+ byte AC5 :1; /* Acceptance Code Bit 5 */\r
+ byte AC6 :1; /* Acceptance Code Bit 6 */\r
+ byte AC7 :1; /* Acceptance Code Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAC :8;\r
+ } MergedBits;\r
+} CANIDAR7STR;\r
+extern volatile CANIDAR7STR _CANIDAR7 @(REG_BASE + 0x0000015B);\r
+#define CANIDAR7 _CANIDAR7.Byte\r
+#define CANIDAR7_AC0 _CANIDAR7.Bits.AC0\r
+#define CANIDAR7_AC1 _CANIDAR7.Bits.AC1\r
+#define CANIDAR7_AC2 _CANIDAR7.Bits.AC2\r
+#define CANIDAR7_AC3 _CANIDAR7.Bits.AC3\r
+#define CANIDAR7_AC4 _CANIDAR7.Bits.AC4\r
+#define CANIDAR7_AC5 _CANIDAR7.Bits.AC5\r
+#define CANIDAR7_AC6 _CANIDAR7.Bits.AC6\r
+#define CANIDAR7_AC7 _CANIDAR7.Bits.AC7\r
+#define CANIDAR7_AC _CANIDAR7.MergedBits.grpAC\r
+\r
+\r
+/*** CANIDMR4 - MSCAN Identifier Mask Register 4; 0x0000015C ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AM0 :1; /* Acceptance Mask Bit 0 */\r
+ byte AM1 :1; /* Acceptance Mask Bit 1 */\r
+ byte AM2 :1; /* Acceptance Mask Bit 2 */\r
+ byte AM3 :1; /* Acceptance Mask Bit 3 */\r
+ byte AM4 :1; /* Acceptance Mask Bit 4 */\r
+ byte AM5 :1; /* Acceptance Mask Bit 5 */\r
+ byte AM6 :1; /* Acceptance Mask Bit 6 */\r
+ byte AM7 :1; /* Acceptance Mask Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAM :8;\r
+ } MergedBits;\r
+} CANIDMR4STR;\r
+extern volatile CANIDMR4STR _CANIDMR4 @(REG_BASE + 0x0000015C);\r
+#define CANIDMR4 _CANIDMR4.Byte\r
+#define CANIDMR4_AM0 _CANIDMR4.Bits.AM0\r
+#define CANIDMR4_AM1 _CANIDMR4.Bits.AM1\r
+#define CANIDMR4_AM2 _CANIDMR4.Bits.AM2\r
+#define CANIDMR4_AM3 _CANIDMR4.Bits.AM3\r
+#define CANIDMR4_AM4 _CANIDMR4.Bits.AM4\r
+#define CANIDMR4_AM5 _CANIDMR4.Bits.AM5\r
+#define CANIDMR4_AM6 _CANIDMR4.Bits.AM6\r
+#define CANIDMR4_AM7 _CANIDMR4.Bits.AM7\r
+#define CANIDMR4_AM _CANIDMR4.MergedBits.grpAM\r
+\r
+\r
+/*** CANIDMR5 - MSCAN Identifier Mask Register 5; 0x0000015D ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AM0 :1; /* Acceptance Mask Bit 0 */\r
+ byte AM1 :1; /* Acceptance Mask Bit 1 */\r
+ byte AM2 :1; /* Acceptance Mask Bit 2 */\r
+ byte AM3 :1; /* Acceptance Mask Bit 3 */\r
+ byte AM4 :1; /* Acceptance Mask Bit 4 */\r
+ byte AM5 :1; /* Acceptance Mask Bit 5 */\r
+ byte AM6 :1; /* Acceptance Mask Bit 6 */\r
+ byte AM7 :1; /* Acceptance Mask Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAM :8;\r
+ } MergedBits;\r
+} CANIDMR5STR;\r
+extern volatile CANIDMR5STR _CANIDMR5 @(REG_BASE + 0x0000015D);\r
+#define CANIDMR5 _CANIDMR5.Byte\r
+#define CANIDMR5_AM0 _CANIDMR5.Bits.AM0\r
+#define CANIDMR5_AM1 _CANIDMR5.Bits.AM1\r
+#define CANIDMR5_AM2 _CANIDMR5.Bits.AM2\r
+#define CANIDMR5_AM3 _CANIDMR5.Bits.AM3\r
+#define CANIDMR5_AM4 _CANIDMR5.Bits.AM4\r
+#define CANIDMR5_AM5 _CANIDMR5.Bits.AM5\r
+#define CANIDMR5_AM6 _CANIDMR5.Bits.AM6\r
+#define CANIDMR5_AM7 _CANIDMR5.Bits.AM7\r
+#define CANIDMR5_AM _CANIDMR5.MergedBits.grpAM\r
+\r
+\r
+/*** CANIDMR6 - MSCAN Identifier Mask Register 6; 0x0000015E ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AM0 :1; /* Acceptance Mask Bit 0 */\r
+ byte AM1 :1; /* Acceptance Mask Bit 1 */\r
+ byte AM2 :1; /* Acceptance Mask Bit 2 */\r
+ byte AM3 :1; /* Acceptance Mask Bit 3 */\r
+ byte AM4 :1; /* Acceptance Mask Bit 4 */\r
+ byte AM5 :1; /* Acceptance Mask Bit 5 */\r
+ byte AM6 :1; /* Acceptance Mask Bit 6 */\r
+ byte AM7 :1; /* Acceptance Mask Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAM :8;\r
+ } MergedBits;\r
+} CANIDMR6STR;\r
+extern volatile CANIDMR6STR _CANIDMR6 @(REG_BASE + 0x0000015E);\r
+#define CANIDMR6 _CANIDMR6.Byte\r
+#define CANIDMR6_AM0 _CANIDMR6.Bits.AM0\r
+#define CANIDMR6_AM1 _CANIDMR6.Bits.AM1\r
+#define CANIDMR6_AM2 _CANIDMR6.Bits.AM2\r
+#define CANIDMR6_AM3 _CANIDMR6.Bits.AM3\r
+#define CANIDMR6_AM4 _CANIDMR6.Bits.AM4\r
+#define CANIDMR6_AM5 _CANIDMR6.Bits.AM5\r
+#define CANIDMR6_AM6 _CANIDMR6.Bits.AM6\r
+#define CANIDMR6_AM7 _CANIDMR6.Bits.AM7\r
+#define CANIDMR6_AM _CANIDMR6.MergedBits.grpAM\r
+\r
+\r
+/*** CANIDMR7 - MSCAN Identifier Mask Register 7; 0x0000015F ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte AM0 :1; /* Acceptance Mask Bit 0 */\r
+ byte AM1 :1; /* Acceptance Mask Bit 1 */\r
+ byte AM2 :1; /* Acceptance Mask Bit 2 */\r
+ byte AM3 :1; /* Acceptance Mask Bit 3 */\r
+ byte AM4 :1; /* Acceptance Mask Bit 4 */\r
+ byte AM5 :1; /* Acceptance Mask Bit 5 */\r
+ byte AM6 :1; /* Acceptance Mask Bit 6 */\r
+ byte AM7 :1; /* Acceptance Mask Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpAM :8;\r
+ } MergedBits;\r
+} CANIDMR7STR;\r
+extern volatile CANIDMR7STR _CANIDMR7 @(REG_BASE + 0x0000015F);\r
+#define CANIDMR7 _CANIDMR7.Byte\r
+#define CANIDMR7_AM0 _CANIDMR7.Bits.AM0\r
+#define CANIDMR7_AM1 _CANIDMR7.Bits.AM1\r
+#define CANIDMR7_AM2 _CANIDMR7.Bits.AM2\r
+#define CANIDMR7_AM3 _CANIDMR7.Bits.AM3\r
+#define CANIDMR7_AM4 _CANIDMR7.Bits.AM4\r
+#define CANIDMR7_AM5 _CANIDMR7.Bits.AM5\r
+#define CANIDMR7_AM6 _CANIDMR7.Bits.AM6\r
+#define CANIDMR7_AM7 _CANIDMR7.Bits.AM7\r
+#define CANIDMR7_AM _CANIDMR7.MergedBits.grpAM\r
+\r
+\r
+/*** CANRXIDR0 - MSCAN Receive Identifier Register 0; 0x00000160 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ID21 :1; /* Extended format identifier Bit 21 */\r
+ byte ID22 :1; /* Extended format identifier Bit 22 */\r
+ byte ID23 :1; /* Extended format identifier Bit 23 */\r
+ byte ID24 :1; /* Extended format identifier Bit 24 */\r
+ byte ID25 :1; /* Extended format identifier Bit 25 */\r
+ byte ID26 :1; /* Extended format identifier Bit 26 */\r
+ byte ID27 :1; /* Extended format identifier Bit 27 */\r
+ byte ID28 :1; /* Extended format identifier Bit 28 */\r
+ } Bits;\r
+ struct {\r
+ byte grpID_21 :8;\r
+ } MergedBits;\r
+} CANRXIDR0STR;\r
+extern volatile CANRXIDR0STR _CANRXIDR0 @(REG_BASE + 0x00000160);\r
+#define CANRXIDR0 _CANRXIDR0.Byte\r
+#define CANRXIDR0_ID21 _CANRXIDR0.Bits.ID21\r
+#define CANRXIDR0_ID22 _CANRXIDR0.Bits.ID22\r
+#define CANRXIDR0_ID23 _CANRXIDR0.Bits.ID23\r
+#define CANRXIDR0_ID24 _CANRXIDR0.Bits.ID24\r
+#define CANRXIDR0_ID25 _CANRXIDR0.Bits.ID25\r
+#define CANRXIDR0_ID26 _CANRXIDR0.Bits.ID26\r
+#define CANRXIDR0_ID27 _CANRXIDR0.Bits.ID27\r
+#define CANRXIDR0_ID28 _CANRXIDR0.Bits.ID28\r
+#define CANRXIDR0_ID_21 _CANRXIDR0.MergedBits.grpID_21\r
+#define CANRXIDR0_ID CANRXIDR0_ID_21\r
+\r
+\r
+/*** CANRXIDR1 - MSCAN Receive Identifier Register 1; 0x00000161 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ID15 :1; /* Extended format identifier Bit 15 */\r
+ byte ID16 :1; /* Extended format identifier Bit 16 */\r
+ byte ID17 :1; /* Extended format identifier Bit 17 */\r
+ byte IDE :1; /* ID Extended */\r
+ byte SRR :1; /* Substitute Remote Request */\r
+ byte ID18 :1; /* Extended format identifier Bit 18 */\r
+ byte ID19 :1; /* Extended format identifier Bit 19 */\r
+ byte ID20 :1; /* Extended format identifier Bit 20 */\r
+ } Bits;\r
+ struct {\r
+ byte grpID_15 :3;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpID_18 :3;\r
+ } MergedBits;\r
+} CANRXIDR1STR;\r
+extern volatile CANRXIDR1STR _CANRXIDR1 @(REG_BASE + 0x00000161);\r
+#define CANRXIDR1 _CANRXIDR1.Byte\r
+#define CANRXIDR1_ID15 _CANRXIDR1.Bits.ID15\r
+#define CANRXIDR1_ID16 _CANRXIDR1.Bits.ID16\r
+#define CANRXIDR1_ID17 _CANRXIDR1.Bits.ID17\r
+#define CANRXIDR1_IDE _CANRXIDR1.Bits.IDE\r
+#define CANRXIDR1_SRR _CANRXIDR1.Bits.SRR\r
+#define CANRXIDR1_ID18 _CANRXIDR1.Bits.ID18\r
+#define CANRXIDR1_ID19 _CANRXIDR1.Bits.ID19\r
+#define CANRXIDR1_ID20 _CANRXIDR1.Bits.ID20\r
+#define CANRXIDR1_ID_15 _CANRXIDR1.MergedBits.grpID_15\r
+#define CANRXIDR1_ID_18 _CANRXIDR1.MergedBits.grpID_18\r
+#define CANRXIDR1_ID CANRXIDR1_ID_15\r
+\r
+\r
+/*** CANRXIDR2 - MSCAN Receive Identifier Register 2; 0x00000162 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ID7 :1; /* Extended format identifier Bit 7 */\r
+ byte ID8 :1; /* Extended format identifier Bit 8 */\r
+ byte ID9 :1; /* Extended format identifier Bit 9 */\r
+ byte ID10 :1; /* Extended format identifier Bit 10 */\r
+ byte ID11 :1; /* Extended format identifier Bit 11 */\r
+ byte ID12 :1; /* Extended format identifier Bit 12 */\r
+ byte ID13 :1; /* Extended format identifier Bit 13 */\r
+ byte ID14 :1; /* Extended format identifier Bit 14 */\r
+ } Bits;\r
+ struct {\r
+ byte grpID_7 :8;\r
+ } MergedBits;\r
+} CANRXIDR2STR;\r
+extern volatile CANRXIDR2STR _CANRXIDR2 @(REG_BASE + 0x00000162);\r
+#define CANRXIDR2 _CANRXIDR2.Byte\r
+#define CANRXIDR2_ID7 _CANRXIDR2.Bits.ID7\r
+#define CANRXIDR2_ID8 _CANRXIDR2.Bits.ID8\r
+#define CANRXIDR2_ID9 _CANRXIDR2.Bits.ID9\r
+#define CANRXIDR2_ID10 _CANRXIDR2.Bits.ID10\r
+#define CANRXIDR2_ID11 _CANRXIDR2.Bits.ID11\r
+#define CANRXIDR2_ID12 _CANRXIDR2.Bits.ID12\r
+#define CANRXIDR2_ID13 _CANRXIDR2.Bits.ID13\r
+#define CANRXIDR2_ID14 _CANRXIDR2.Bits.ID14\r
+#define CANRXIDR2_ID_7 _CANRXIDR2.MergedBits.grpID_7\r
+#define CANRXIDR2_ID CANRXIDR2_ID_7\r
+\r
+\r
+/*** CANRXIDR3 - MSCAN Receive Identifier Register 3; 0x00000163 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte RTR :1; /* Remote Transmission Request */\r
+ byte ID0 :1; /* Extended format identifier Bit 0 */\r
+ byte ID1 :1; /* Extended format identifier Bit 1 */\r
+ byte ID2 :1; /* Extended format identifier Bit 2 */\r
+ byte ID3 :1; /* Extended format identifier Bit 3 */\r
+ byte ID4 :1; /* Extended format identifier Bit 4 */\r
+ byte ID5 :1; /* Extended format identifier Bit 5 */\r
+ byte ID6 :1; /* Extended format identifier Bit 6 */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte grpID :7;\r
+ } MergedBits;\r
+} CANRXIDR3STR;\r
+extern volatile CANRXIDR3STR _CANRXIDR3 @(REG_BASE + 0x00000163);\r
+#define CANRXIDR3 _CANRXIDR3.Byte\r
+#define CANRXIDR3_RTR _CANRXIDR3.Bits.RTR\r
+#define CANRXIDR3_ID0 _CANRXIDR3.Bits.ID0\r
+#define CANRXIDR3_ID1 _CANRXIDR3.Bits.ID1\r
+#define CANRXIDR3_ID2 _CANRXIDR3.Bits.ID2\r
+#define CANRXIDR3_ID3 _CANRXIDR3.Bits.ID3\r
+#define CANRXIDR3_ID4 _CANRXIDR3.Bits.ID4\r
+#define CANRXIDR3_ID5 _CANRXIDR3.Bits.ID5\r
+#define CANRXIDR3_ID6 _CANRXIDR3.Bits.ID6\r
+#define CANRXIDR3_ID _CANRXIDR3.MergedBits.grpID\r
+\r
+\r
+/*** CANRXDSR0 - MSCAN Receive Data Segment Register 0; 0x00000164 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CANRXDSR0STR;\r
+extern volatile CANRXDSR0STR _CANRXDSR0 @(REG_BASE + 0x00000164);\r
+#define CANRXDSR0 _CANRXDSR0.Byte\r
+#define CANRXDSR0_DB0 _CANRXDSR0.Bits.DB0\r
+#define CANRXDSR0_DB1 _CANRXDSR0.Bits.DB1\r
+#define CANRXDSR0_DB2 _CANRXDSR0.Bits.DB2\r
+#define CANRXDSR0_DB3 _CANRXDSR0.Bits.DB3\r
+#define CANRXDSR0_DB4 _CANRXDSR0.Bits.DB4\r
+#define CANRXDSR0_DB5 _CANRXDSR0.Bits.DB5\r
+#define CANRXDSR0_DB6 _CANRXDSR0.Bits.DB6\r
+#define CANRXDSR0_DB7 _CANRXDSR0.Bits.DB7\r
+#define CANRXDSR0_DB _CANRXDSR0.MergedBits.grpDB\r
+\r
+\r
+/*** CANRXDSR1 - MSCAN Receive Data Segment Register 1; 0x00000165 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CANRXDSR1STR;\r
+extern volatile CANRXDSR1STR _CANRXDSR1 @(REG_BASE + 0x00000165);\r
+#define CANRXDSR1 _CANRXDSR1.Byte\r
+#define CANRXDSR1_DB0 _CANRXDSR1.Bits.DB0\r
+#define CANRXDSR1_DB1 _CANRXDSR1.Bits.DB1\r
+#define CANRXDSR1_DB2 _CANRXDSR1.Bits.DB2\r
+#define CANRXDSR1_DB3 _CANRXDSR1.Bits.DB3\r
+#define CANRXDSR1_DB4 _CANRXDSR1.Bits.DB4\r
+#define CANRXDSR1_DB5 _CANRXDSR1.Bits.DB5\r
+#define CANRXDSR1_DB6 _CANRXDSR1.Bits.DB6\r
+#define CANRXDSR1_DB7 _CANRXDSR1.Bits.DB7\r
+#define CANRXDSR1_DB _CANRXDSR1.MergedBits.grpDB\r
+\r
+\r
+/*** CANRXDSR2 - MSCAN Receive Data Segment Register 2; 0x00000166 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CANRXDSR2STR;\r
+extern volatile CANRXDSR2STR _CANRXDSR2 @(REG_BASE + 0x00000166);\r
+#define CANRXDSR2 _CANRXDSR2.Byte\r
+#define CANRXDSR2_DB0 _CANRXDSR2.Bits.DB0\r
+#define CANRXDSR2_DB1 _CANRXDSR2.Bits.DB1\r
+#define CANRXDSR2_DB2 _CANRXDSR2.Bits.DB2\r
+#define CANRXDSR2_DB3 _CANRXDSR2.Bits.DB3\r
+#define CANRXDSR2_DB4 _CANRXDSR2.Bits.DB4\r
+#define CANRXDSR2_DB5 _CANRXDSR2.Bits.DB5\r
+#define CANRXDSR2_DB6 _CANRXDSR2.Bits.DB6\r
+#define CANRXDSR2_DB7 _CANRXDSR2.Bits.DB7\r
+#define CANRXDSR2_DB _CANRXDSR2.MergedBits.grpDB\r
+\r
+\r
+/*** CANRXDSR3 - MSCAN Receive Data Segment Register 3; 0x00000167 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CANRXDSR3STR;\r
+extern volatile CANRXDSR3STR _CANRXDSR3 @(REG_BASE + 0x00000167);\r
+#define CANRXDSR3 _CANRXDSR3.Byte\r
+#define CANRXDSR3_DB0 _CANRXDSR3.Bits.DB0\r
+#define CANRXDSR3_DB1 _CANRXDSR3.Bits.DB1\r
+#define CANRXDSR3_DB2 _CANRXDSR3.Bits.DB2\r
+#define CANRXDSR3_DB3 _CANRXDSR3.Bits.DB3\r
+#define CANRXDSR3_DB4 _CANRXDSR3.Bits.DB4\r
+#define CANRXDSR3_DB5 _CANRXDSR3.Bits.DB5\r
+#define CANRXDSR3_DB6 _CANRXDSR3.Bits.DB6\r
+#define CANRXDSR3_DB7 _CANRXDSR3.Bits.DB7\r
+#define CANRXDSR3_DB _CANRXDSR3.MergedBits.grpDB\r
+\r
+\r
+/*** CANRXDSR4 - MSCAN Receive Data Segment Register 4; 0x00000168 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CANRXDSR4STR;\r
+extern volatile CANRXDSR4STR _CANRXDSR4 @(REG_BASE + 0x00000168);\r
+#define CANRXDSR4 _CANRXDSR4.Byte\r
+#define CANRXDSR4_DB0 _CANRXDSR4.Bits.DB0\r
+#define CANRXDSR4_DB1 _CANRXDSR4.Bits.DB1\r
+#define CANRXDSR4_DB2 _CANRXDSR4.Bits.DB2\r
+#define CANRXDSR4_DB3 _CANRXDSR4.Bits.DB3\r
+#define CANRXDSR4_DB4 _CANRXDSR4.Bits.DB4\r
+#define CANRXDSR4_DB5 _CANRXDSR4.Bits.DB5\r
+#define CANRXDSR4_DB6 _CANRXDSR4.Bits.DB6\r
+#define CANRXDSR4_DB7 _CANRXDSR4.Bits.DB7\r
+#define CANRXDSR4_DB _CANRXDSR4.MergedBits.grpDB\r
+\r
+\r
+/*** CANRXDSR5 - MSCAN Receive Data Segment Register 5; 0x00000169 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CANRXDSR5STR;\r
+extern volatile CANRXDSR5STR _CANRXDSR5 @(REG_BASE + 0x00000169);\r
+#define CANRXDSR5 _CANRXDSR5.Byte\r
+#define CANRXDSR5_DB0 _CANRXDSR5.Bits.DB0\r
+#define CANRXDSR5_DB1 _CANRXDSR5.Bits.DB1\r
+#define CANRXDSR5_DB2 _CANRXDSR5.Bits.DB2\r
+#define CANRXDSR5_DB3 _CANRXDSR5.Bits.DB3\r
+#define CANRXDSR5_DB4 _CANRXDSR5.Bits.DB4\r
+#define CANRXDSR5_DB5 _CANRXDSR5.Bits.DB5\r
+#define CANRXDSR5_DB6 _CANRXDSR5.Bits.DB6\r
+#define CANRXDSR5_DB7 _CANRXDSR5.Bits.DB7\r
+#define CANRXDSR5_DB _CANRXDSR5.MergedBits.grpDB\r
+\r
+\r
+/*** CANRXDSR6 - MSCAN Receive Data Segment Register 6; 0x0000016A ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CANRXDSR6STR;\r
+extern volatile CANRXDSR6STR _CANRXDSR6 @(REG_BASE + 0x0000016A);\r
+#define CANRXDSR6 _CANRXDSR6.Byte\r
+#define CANRXDSR6_DB0 _CANRXDSR6.Bits.DB0\r
+#define CANRXDSR6_DB1 _CANRXDSR6.Bits.DB1\r
+#define CANRXDSR6_DB2 _CANRXDSR6.Bits.DB2\r
+#define CANRXDSR6_DB3 _CANRXDSR6.Bits.DB3\r
+#define CANRXDSR6_DB4 _CANRXDSR6.Bits.DB4\r
+#define CANRXDSR6_DB5 _CANRXDSR6.Bits.DB5\r
+#define CANRXDSR6_DB6 _CANRXDSR6.Bits.DB6\r
+#define CANRXDSR6_DB7 _CANRXDSR6.Bits.DB7\r
+#define CANRXDSR6_DB _CANRXDSR6.MergedBits.grpDB\r
+\r
+\r
+/*** CANRXDSR7 - MSCAN Receive Data Segment Register 7; 0x0000016B ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CANRXDSR7STR;\r
+extern volatile CANRXDSR7STR _CANRXDSR7 @(REG_BASE + 0x0000016B);\r
+#define CANRXDSR7 _CANRXDSR7.Byte\r
+#define CANRXDSR7_DB0 _CANRXDSR7.Bits.DB0\r
+#define CANRXDSR7_DB1 _CANRXDSR7.Bits.DB1\r
+#define CANRXDSR7_DB2 _CANRXDSR7.Bits.DB2\r
+#define CANRXDSR7_DB3 _CANRXDSR7.Bits.DB3\r
+#define CANRXDSR7_DB4 _CANRXDSR7.Bits.DB4\r
+#define CANRXDSR7_DB5 _CANRXDSR7.Bits.DB5\r
+#define CANRXDSR7_DB6 _CANRXDSR7.Bits.DB6\r
+#define CANRXDSR7_DB7 _CANRXDSR7.Bits.DB7\r
+#define CANRXDSR7_DB _CANRXDSR7.MergedBits.grpDB\r
+\r
+\r
+/*** CANRXDLR - MSCAN Receive Data Length Register; 0x0000016C ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DLC0 :1; /* Data Length Code Bit 0 */\r
+ byte DLC1 :1; /* Data Length Code Bit 1 */\r
+ byte DLC2 :1; /* Data Length Code Bit 2 */\r
+ byte DLC3 :1; /* Data Length Code Bit 3 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpDLC :4;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CANRXDLRSTR;\r
+extern volatile CANRXDLRSTR _CANRXDLR @(REG_BASE + 0x0000016C);\r
+#define CANRXDLR _CANRXDLR.Byte\r
+#define CANRXDLR_DLC0 _CANRXDLR.Bits.DLC0\r
+#define CANRXDLR_DLC1 _CANRXDLR.Bits.DLC1\r
+#define CANRXDLR_DLC2 _CANRXDLR.Bits.DLC2\r
+#define CANRXDLR_DLC3 _CANRXDLR.Bits.DLC3\r
+#define CANRXDLR_DLC _CANRXDLR.MergedBits.grpDLC\r
+\r
+\r
+/*** CANTXIDR0 - MSCAN Transmit Identifier Register 0; 0x00000170 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ID21 :1; /* Extended format identifier Bit 21 */\r
+ byte ID22 :1; /* Extended format identifier Bit 22 */\r
+ byte ID23 :1; /* Extended format identifier Bit 23 */\r
+ byte ID24 :1; /* Extended format identifier Bit 24 */\r
+ byte ID25 :1; /* Extended format identifier Bit 25 */\r
+ byte ID26 :1; /* Extended format identifier Bit 26 */\r
+ byte ID27 :1; /* Extended format identifier Bit 27 */\r
+ byte ID28 :1; /* Extended format identifier Bit 28 */\r
+ } Bits;\r
+ struct {\r
+ byte grpID_21 :8;\r
+ } MergedBits;\r
+} CANTXIDR0STR;\r
+extern volatile CANTXIDR0STR _CANTXIDR0 @(REG_BASE + 0x00000170);\r
+#define CANTXIDR0 _CANTXIDR0.Byte\r
+#define CANTXIDR0_ID21 _CANTXIDR0.Bits.ID21\r
+#define CANTXIDR0_ID22 _CANTXIDR0.Bits.ID22\r
+#define CANTXIDR0_ID23 _CANTXIDR0.Bits.ID23\r
+#define CANTXIDR0_ID24 _CANTXIDR0.Bits.ID24\r
+#define CANTXIDR0_ID25 _CANTXIDR0.Bits.ID25\r
+#define CANTXIDR0_ID26 _CANTXIDR0.Bits.ID26\r
+#define CANTXIDR0_ID27 _CANTXIDR0.Bits.ID27\r
+#define CANTXIDR0_ID28 _CANTXIDR0.Bits.ID28\r
+#define CANTXIDR0_ID_21 _CANTXIDR0.MergedBits.grpID_21\r
+#define CANTXIDR0_ID CANTXIDR0_ID_21\r
+\r
+\r
+/*** CANTXIDR1 - MSCAN Transmit Identifier Register 1; 0x00000171 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ID15 :1; /* Extended format identifier Bit 15 */\r
+ byte ID16 :1; /* Extended format identifier Bit 16 */\r
+ byte ID17 :1; /* Extended format identifier Bit 17 */\r
+ byte IDE :1; /* ID Extended */\r
+ byte SRR :1; /* Substitute Remote Request */\r
+ byte ID18 :1; /* Extended format identifier Bit 18 */\r
+ byte ID19 :1; /* Extended format identifier Bit 19 */\r
+ byte ID20 :1; /* Extended format identifier Bit 20 */\r
+ } Bits;\r
+ struct {\r
+ byte grpID_15 :3;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpID_18 :3;\r
+ } MergedBits;\r
+} CANTXIDR1STR;\r
+extern volatile CANTXIDR1STR _CANTXIDR1 @(REG_BASE + 0x00000171);\r
+#define CANTXIDR1 _CANTXIDR1.Byte\r
+#define CANTXIDR1_ID15 _CANTXIDR1.Bits.ID15\r
+#define CANTXIDR1_ID16 _CANTXIDR1.Bits.ID16\r
+#define CANTXIDR1_ID17 _CANTXIDR1.Bits.ID17\r
+#define CANTXIDR1_IDE _CANTXIDR1.Bits.IDE\r
+#define CANTXIDR1_SRR _CANTXIDR1.Bits.SRR\r
+#define CANTXIDR1_ID18 _CANTXIDR1.Bits.ID18\r
+#define CANTXIDR1_ID19 _CANTXIDR1.Bits.ID19\r
+#define CANTXIDR1_ID20 _CANTXIDR1.Bits.ID20\r
+#define CANTXIDR1_ID_15 _CANTXIDR1.MergedBits.grpID_15\r
+#define CANTXIDR1_ID_18 _CANTXIDR1.MergedBits.grpID_18\r
+#define CANTXIDR1_ID CANTXIDR1_ID_15\r
+\r
+\r
+/*** CANTXIDR2 - MSCAN Transmit Identifier Register 2; 0x00000172 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte ID7 :1; /* Extended format identifier Bit 7 */\r
+ byte ID8 :1; /* Extended format identifier Bit 8 */\r
+ byte ID9 :1; /* Extended format identifier Bit 9 */\r
+ byte ID10 :1; /* Extended format identifier Bit 10 */\r
+ byte ID11 :1; /* Extended format identifier Bit 11 */\r
+ byte ID12 :1; /* Extended format identifier Bit 12 */\r
+ byte ID13 :1; /* Extended format identifier Bit 13 */\r
+ byte ID14 :1; /* Extended format identifier Bit 14 */\r
+ } Bits;\r
+ struct {\r
+ byte grpID_7 :8;\r
+ } MergedBits;\r
+} CANTXIDR2STR;\r
+extern volatile CANTXIDR2STR _CANTXIDR2 @(REG_BASE + 0x00000172);\r
+#define CANTXIDR2 _CANTXIDR2.Byte\r
+#define CANTXIDR2_ID7 _CANTXIDR2.Bits.ID7\r
+#define CANTXIDR2_ID8 _CANTXIDR2.Bits.ID8\r
+#define CANTXIDR2_ID9 _CANTXIDR2.Bits.ID9\r
+#define CANTXIDR2_ID10 _CANTXIDR2.Bits.ID10\r
+#define CANTXIDR2_ID11 _CANTXIDR2.Bits.ID11\r
+#define CANTXIDR2_ID12 _CANTXIDR2.Bits.ID12\r
+#define CANTXIDR2_ID13 _CANTXIDR2.Bits.ID13\r
+#define CANTXIDR2_ID14 _CANTXIDR2.Bits.ID14\r
+#define CANTXIDR2_ID_7 _CANTXIDR2.MergedBits.grpID_7\r
+#define CANTXIDR2_ID CANTXIDR2_ID_7\r
+\r
+\r
+/*** CANTXIDR3 - MSCAN Transmit Identifier Register 3; 0x00000173 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte RTR :1; /* Remote Transmission Request */\r
+ byte ID0 :1; /* Extended format identifier Bit 0 */\r
+ byte ID1 :1; /* Extended format identifier Bit 1 */\r
+ byte ID2 :1; /* Extended format identifier Bit 2 */\r
+ byte ID3 :1; /* Extended format identifier Bit 3 */\r
+ byte ID4 :1; /* Extended format identifier Bit 4 */\r
+ byte ID5 :1; /* Extended format identifier Bit 5 */\r
+ byte ID6 :1; /* Extended format identifier Bit 6 */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte grpID :7;\r
+ } MergedBits;\r
+} CANTXIDR3STR;\r
+extern volatile CANTXIDR3STR _CANTXIDR3 @(REG_BASE + 0x00000173);\r
+#define CANTXIDR3 _CANTXIDR3.Byte\r
+#define CANTXIDR3_RTR _CANTXIDR3.Bits.RTR\r
+#define CANTXIDR3_ID0 _CANTXIDR3.Bits.ID0\r
+#define CANTXIDR3_ID1 _CANTXIDR3.Bits.ID1\r
+#define CANTXIDR3_ID2 _CANTXIDR3.Bits.ID2\r
+#define CANTXIDR3_ID3 _CANTXIDR3.Bits.ID3\r
+#define CANTXIDR3_ID4 _CANTXIDR3.Bits.ID4\r
+#define CANTXIDR3_ID5 _CANTXIDR3.Bits.ID5\r
+#define CANTXIDR3_ID6 _CANTXIDR3.Bits.ID6\r
+#define CANTXIDR3_ID _CANTXIDR3.MergedBits.grpID\r
+\r
+\r
+/*** CANTXDSR0 - MSCAN Transmit Data Segment Register 0; 0x00000174 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CANTXDSR0STR;\r
+extern volatile CANTXDSR0STR _CANTXDSR0 @(REG_BASE + 0x00000174);\r
+#define CANTXDSR0 _CANTXDSR0.Byte\r
+#define CANTXDSR0_DB0 _CANTXDSR0.Bits.DB0\r
+#define CANTXDSR0_DB1 _CANTXDSR0.Bits.DB1\r
+#define CANTXDSR0_DB2 _CANTXDSR0.Bits.DB2\r
+#define CANTXDSR0_DB3 _CANTXDSR0.Bits.DB3\r
+#define CANTXDSR0_DB4 _CANTXDSR0.Bits.DB4\r
+#define CANTXDSR0_DB5 _CANTXDSR0.Bits.DB5\r
+#define CANTXDSR0_DB6 _CANTXDSR0.Bits.DB6\r
+#define CANTXDSR0_DB7 _CANTXDSR0.Bits.DB7\r
+#define CANTXDSR0_DB _CANTXDSR0.MergedBits.grpDB\r
+\r
+\r
+/*** CANTXDSR1 - MSCAN Transmit Data Segment Register 1; 0x00000175 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CANTXDSR1STR;\r
+extern volatile CANTXDSR1STR _CANTXDSR1 @(REG_BASE + 0x00000175);\r
+#define CANTXDSR1 _CANTXDSR1.Byte\r
+#define CANTXDSR1_DB0 _CANTXDSR1.Bits.DB0\r
+#define CANTXDSR1_DB1 _CANTXDSR1.Bits.DB1\r
+#define CANTXDSR1_DB2 _CANTXDSR1.Bits.DB2\r
+#define CANTXDSR1_DB3 _CANTXDSR1.Bits.DB3\r
+#define CANTXDSR1_DB4 _CANTXDSR1.Bits.DB4\r
+#define CANTXDSR1_DB5 _CANTXDSR1.Bits.DB5\r
+#define CANTXDSR1_DB6 _CANTXDSR1.Bits.DB6\r
+#define CANTXDSR1_DB7 _CANTXDSR1.Bits.DB7\r
+#define CANTXDSR1_DB _CANTXDSR1.MergedBits.grpDB\r
+\r
+\r
+/*** CANTXDSR2 - MSCAN Transmit Data Segment Register 2; 0x00000176 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CANTXDSR2STR;\r
+extern volatile CANTXDSR2STR _CANTXDSR2 @(REG_BASE + 0x00000176);\r
+#define CANTXDSR2 _CANTXDSR2.Byte\r
+#define CANTXDSR2_DB0 _CANTXDSR2.Bits.DB0\r
+#define CANTXDSR2_DB1 _CANTXDSR2.Bits.DB1\r
+#define CANTXDSR2_DB2 _CANTXDSR2.Bits.DB2\r
+#define CANTXDSR2_DB3 _CANTXDSR2.Bits.DB3\r
+#define CANTXDSR2_DB4 _CANTXDSR2.Bits.DB4\r
+#define CANTXDSR2_DB5 _CANTXDSR2.Bits.DB5\r
+#define CANTXDSR2_DB6 _CANTXDSR2.Bits.DB6\r
+#define CANTXDSR2_DB7 _CANTXDSR2.Bits.DB7\r
+#define CANTXDSR2_DB _CANTXDSR2.MergedBits.grpDB\r
+\r
+\r
+/*** CANTXDSR3 - MSCAN Transmit Data Segment Register 3; 0x00000177 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CANTXDSR3STR;\r
+extern volatile CANTXDSR3STR _CANTXDSR3 @(REG_BASE + 0x00000177);\r
+#define CANTXDSR3 _CANTXDSR3.Byte\r
+#define CANTXDSR3_DB0 _CANTXDSR3.Bits.DB0\r
+#define CANTXDSR3_DB1 _CANTXDSR3.Bits.DB1\r
+#define CANTXDSR3_DB2 _CANTXDSR3.Bits.DB2\r
+#define CANTXDSR3_DB3 _CANTXDSR3.Bits.DB3\r
+#define CANTXDSR3_DB4 _CANTXDSR3.Bits.DB4\r
+#define CANTXDSR3_DB5 _CANTXDSR3.Bits.DB5\r
+#define CANTXDSR3_DB6 _CANTXDSR3.Bits.DB6\r
+#define CANTXDSR3_DB7 _CANTXDSR3.Bits.DB7\r
+#define CANTXDSR3_DB _CANTXDSR3.MergedBits.grpDB\r
+\r
+\r
+/*** CANTXDSR4 - MSCAN Transmit Data Segment Register 4; 0x00000178 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CANTXDSR4STR;\r
+extern volatile CANTXDSR4STR _CANTXDSR4 @(REG_BASE + 0x00000178);\r
+#define CANTXDSR4 _CANTXDSR4.Byte\r
+#define CANTXDSR4_DB0 _CANTXDSR4.Bits.DB0\r
+#define CANTXDSR4_DB1 _CANTXDSR4.Bits.DB1\r
+#define CANTXDSR4_DB2 _CANTXDSR4.Bits.DB2\r
+#define CANTXDSR4_DB3 _CANTXDSR4.Bits.DB3\r
+#define CANTXDSR4_DB4 _CANTXDSR4.Bits.DB4\r
+#define CANTXDSR4_DB5 _CANTXDSR4.Bits.DB5\r
+#define CANTXDSR4_DB6 _CANTXDSR4.Bits.DB6\r
+#define CANTXDSR4_DB7 _CANTXDSR4.Bits.DB7\r
+#define CANTXDSR4_DB _CANTXDSR4.MergedBits.grpDB\r
+\r
+\r
+/*** CANTXDSR5 - MSCAN Transmit Data Segment Register 5; 0x00000179 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CANTXDSR5STR;\r
+extern volatile CANTXDSR5STR _CANTXDSR5 @(REG_BASE + 0x00000179);\r
+#define CANTXDSR5 _CANTXDSR5.Byte\r
+#define CANTXDSR5_DB0 _CANTXDSR5.Bits.DB0\r
+#define CANTXDSR5_DB1 _CANTXDSR5.Bits.DB1\r
+#define CANTXDSR5_DB2 _CANTXDSR5.Bits.DB2\r
+#define CANTXDSR5_DB3 _CANTXDSR5.Bits.DB3\r
+#define CANTXDSR5_DB4 _CANTXDSR5.Bits.DB4\r
+#define CANTXDSR5_DB5 _CANTXDSR5.Bits.DB5\r
+#define CANTXDSR5_DB6 _CANTXDSR5.Bits.DB6\r
+#define CANTXDSR5_DB7 _CANTXDSR5.Bits.DB7\r
+#define CANTXDSR5_DB _CANTXDSR5.MergedBits.grpDB\r
+\r
+\r
+/*** CANTXDSR6 - MSCAN Transmit Data Segment Register 6; 0x0000017A ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CANTXDSR6STR;\r
+extern volatile CANTXDSR6STR _CANTXDSR6 @(REG_BASE + 0x0000017A);\r
+#define CANTXDSR6 _CANTXDSR6.Byte\r
+#define CANTXDSR6_DB0 _CANTXDSR6.Bits.DB0\r
+#define CANTXDSR6_DB1 _CANTXDSR6.Bits.DB1\r
+#define CANTXDSR6_DB2 _CANTXDSR6.Bits.DB2\r
+#define CANTXDSR6_DB3 _CANTXDSR6.Bits.DB3\r
+#define CANTXDSR6_DB4 _CANTXDSR6.Bits.DB4\r
+#define CANTXDSR6_DB5 _CANTXDSR6.Bits.DB5\r
+#define CANTXDSR6_DB6 _CANTXDSR6.Bits.DB6\r
+#define CANTXDSR6_DB7 _CANTXDSR6.Bits.DB7\r
+#define CANTXDSR6_DB _CANTXDSR6.MergedBits.grpDB\r
+\r
+\r
+/*** CANTXDSR7 - MSCAN Transmit Data Segment Register 7; 0x0000017B ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DB0 :1; /* Data Bit 0 */\r
+ byte DB1 :1; /* Data Bit 1 */\r
+ byte DB2 :1; /* Data Bit 2 */\r
+ byte DB3 :1; /* Data Bit 3 */\r
+ byte DB4 :1; /* Data Bit 4 */\r
+ byte DB5 :1; /* Data Bit 5 */\r
+ byte DB6 :1; /* Data Bit 6 */\r
+ byte DB7 :1; /* Data Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDB :8;\r
+ } MergedBits;\r
+} CANTXDSR7STR;\r
+extern volatile CANTXDSR7STR _CANTXDSR7 @(REG_BASE + 0x0000017B);\r
+#define CANTXDSR7 _CANTXDSR7.Byte\r
+#define CANTXDSR7_DB0 _CANTXDSR7.Bits.DB0\r
+#define CANTXDSR7_DB1 _CANTXDSR7.Bits.DB1\r
+#define CANTXDSR7_DB2 _CANTXDSR7.Bits.DB2\r
+#define CANTXDSR7_DB3 _CANTXDSR7.Bits.DB3\r
+#define CANTXDSR7_DB4 _CANTXDSR7.Bits.DB4\r
+#define CANTXDSR7_DB5 _CANTXDSR7.Bits.DB5\r
+#define CANTXDSR7_DB6 _CANTXDSR7.Bits.DB6\r
+#define CANTXDSR7_DB7 _CANTXDSR7.Bits.DB7\r
+#define CANTXDSR7_DB _CANTXDSR7.MergedBits.grpDB\r
+\r
+\r
+/*** CANTXDLR - MSCAN Transmit Data Length Register; 0x0000017C ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DLC0 :1; /* Data Length Code Bit 0 */\r
+ byte DLC1 :1; /* Data Length Code Bit 1 */\r
+ byte DLC2 :1; /* Data Length Code Bit 2 */\r
+ byte DLC3 :1; /* Data Length Code Bit 3 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpDLC :4;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} CANTXDLRSTR;\r
+extern volatile CANTXDLRSTR _CANTXDLR @(REG_BASE + 0x0000017C);\r
+#define CANTXDLR _CANTXDLR.Byte\r
+#define CANTXDLR_DLC0 _CANTXDLR.Bits.DLC0\r
+#define CANTXDLR_DLC1 _CANTXDLR.Bits.DLC1\r
+#define CANTXDLR_DLC2 _CANTXDLR.Bits.DLC2\r
+#define CANTXDLR_DLC3 _CANTXDLR.Bits.DLC3\r
+#define CANTXDLR_DLC _CANTXDLR.MergedBits.grpDLC\r
+\r
+\r
+/*** CANTXTBPR - MSCAN Transmit Buffer Priority; 0x0000017F ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PRIO0 :1; /* Transmit Buffer Priority Bit 0 */\r
+ byte PRIO1 :1; /* Transmit Buffer Priority Bit 1 */\r
+ byte PRIO2 :1; /* Transmit Buffer Priority Bit 2 */\r
+ byte PRIO3 :1; /* Transmit Buffer Priority Bit 3 */\r
+ byte PRIO4 :1; /* Transmit Buffer Priority Bit 4 */\r
+ byte PRIO5 :1; /* Transmit Buffer Priority Bit 5 */\r
+ byte PRIO6 :1; /* Transmit Buffer Priority Bit 6 */\r
+ byte PRIO7 :1; /* Transmit Buffer Priority Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpPRIO :8;\r
+ } MergedBits;\r
+} CANTXTBPRSTR;\r
+extern volatile CANTXTBPRSTR _CANTXTBPR @(REG_BASE + 0x0000017F);\r
+#define CANTXTBPR _CANTXTBPR.Byte\r
+#define CANTXTBPR_PRIO0 _CANTXTBPR.Bits.PRIO0\r
+#define CANTXTBPR_PRIO1 _CANTXTBPR.Bits.PRIO1\r
+#define CANTXTBPR_PRIO2 _CANTXTBPR.Bits.PRIO2\r
+#define CANTXTBPR_PRIO3 _CANTXTBPR.Bits.PRIO3\r
+#define CANTXTBPR_PRIO4 _CANTXTBPR.Bits.PRIO4\r
+#define CANTXTBPR_PRIO5 _CANTXTBPR.Bits.PRIO5\r
+#define CANTXTBPR_PRIO6 _CANTXTBPR.Bits.PRIO6\r
+#define CANTXTBPR_PRIO7 _CANTXTBPR.Bits.PRIO7\r
+#define CANTXTBPR_PRIO _CANTXTBPR.MergedBits.grpPRIO\r
+\r
+\r
+/*** PTT - Port T I/O Register; 0x00000240 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PTT0 :1; /* Port T Bit 0 */\r
+ byte PTT1 :1; /* Port T Bit 1 */\r
+ byte PTT2 :1; /* Port T Bit 2 */\r
+ byte PTT3 :1; /* Port T Bit 3 */\r
+ byte PTT4 :1; /* Port T Bit 4 */\r
+ byte PTT5 :1; /* Port T Bit 5 */\r
+ byte PTT6 :1; /* Port T Bit 6 */\r
+ byte PTT7 :1; /* Port T Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpPTT :8;\r
+ } MergedBits;\r
+} PTTSTR;\r
+extern volatile PTTSTR _PTT @(REG_BASE + 0x00000240);\r
+#define PTT _PTT.Byte\r
+#define PTT_PTT0 _PTT.Bits.PTT0\r
+#define PTT_PTT1 _PTT.Bits.PTT1\r
+#define PTT_PTT2 _PTT.Bits.PTT2\r
+#define PTT_PTT3 _PTT.Bits.PTT3\r
+#define PTT_PTT4 _PTT.Bits.PTT4\r
+#define PTT_PTT5 _PTT.Bits.PTT5\r
+#define PTT_PTT6 _PTT.Bits.PTT6\r
+#define PTT_PTT7 _PTT.Bits.PTT7\r
+#define PTT_PTT _PTT.MergedBits.grpPTT\r
+\r
+\r
+/*** PTIT - Port T Input; 0x00000241 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PTIT0 :1; /* Port T Bit 0 */\r
+ byte PTIT1 :1; /* Port T Bit 1 */\r
+ byte PTIT2 :1; /* Port T Bit 2 */\r
+ byte PTIT3 :1; /* Port T Bit 3 */\r
+ byte PTIT4 :1; /* Port T Bit 4 */\r
+ byte PTIT5 :1; /* Port T Bit 5 */\r
+ byte PTIT6 :1; /* Port T Bit 6 */\r
+ byte PTIT7 :1; /* Port T Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpPTIT :8;\r
+ } MergedBits;\r
+} PTITSTR;\r
+extern volatile PTITSTR _PTIT @(REG_BASE + 0x00000241);\r
+#define PTIT _PTIT.Byte\r
+#define PTIT_PTIT0 _PTIT.Bits.PTIT0\r
+#define PTIT_PTIT1 _PTIT.Bits.PTIT1\r
+#define PTIT_PTIT2 _PTIT.Bits.PTIT2\r
+#define PTIT_PTIT3 _PTIT.Bits.PTIT3\r
+#define PTIT_PTIT4 _PTIT.Bits.PTIT4\r
+#define PTIT_PTIT5 _PTIT.Bits.PTIT5\r
+#define PTIT_PTIT6 _PTIT.Bits.PTIT6\r
+#define PTIT_PTIT7 _PTIT.Bits.PTIT7\r
+#define PTIT_PTIT _PTIT.MergedBits.grpPTIT\r
+\r
+\r
+/*** DDRT - Port T Data Direction Register; 0x00000242 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DDRT0 :1; /* Data Direction Port T Bit 0 */\r
+ byte DDRT1 :1; /* Data Direction Port T Bit 1 */\r
+ byte DDRT2 :1; /* Data Direction Port T Bit 2 */\r
+ byte DDRT3 :1; /* Data Direction Port T Bit 3 */\r
+ byte DDRT4 :1; /* Data Direction Port T Bit 4 */\r
+ byte DDRT5 :1; /* Data Direction Port T Bit 5 */\r
+ byte DDRT6 :1; /* Data Direction Port T Bit 6 */\r
+ byte DDRT7 :1; /* Data Direction Port T Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDDRT :8;\r
+ } MergedBits;\r
+} DDRTSTR;\r
+extern volatile DDRTSTR _DDRT @(REG_BASE + 0x00000242);\r
+#define DDRT _DDRT.Byte\r
+#define DDRT_DDRT0 _DDRT.Bits.DDRT0\r
+#define DDRT_DDRT1 _DDRT.Bits.DDRT1\r
+#define DDRT_DDRT2 _DDRT.Bits.DDRT2\r
+#define DDRT_DDRT3 _DDRT.Bits.DDRT3\r
+#define DDRT_DDRT4 _DDRT.Bits.DDRT4\r
+#define DDRT_DDRT5 _DDRT.Bits.DDRT5\r
+#define DDRT_DDRT6 _DDRT.Bits.DDRT6\r
+#define DDRT_DDRT7 _DDRT.Bits.DDRT7\r
+#define DDRT_DDRT _DDRT.MergedBits.grpDDRT\r
+\r
+\r
+/*** RDRT - Port T Reduced Drive Register; 0x00000243 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte RDRT0 :1; /* Reduced Drive Port T Bit 0 */\r
+ byte RDRT1 :1; /* Reduced Drive Port T Bit 1 */\r
+ byte RDRT2 :1; /* Reduced Drive Port T Bit 2 */\r
+ byte RDRT3 :1; /* Reduced Drive Port T Bit 3 */\r
+ byte RDRT4 :1; /* Reduced Drive Port T Bit 4 */\r
+ byte RDRT5 :1; /* Reduced Drive Port T Bit 5 */\r
+ byte RDRT6 :1; /* Reduced Drive Port T Bit 6 */\r
+ byte RDRT7 :1; /* Reduced Drive Port T Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpRDRT :8;\r
+ } MergedBits;\r
+} RDRTSTR;\r
+extern volatile RDRTSTR _RDRT @(REG_BASE + 0x00000243);\r
+#define RDRT _RDRT.Byte\r
+#define RDRT_RDRT0 _RDRT.Bits.RDRT0\r
+#define RDRT_RDRT1 _RDRT.Bits.RDRT1\r
+#define RDRT_RDRT2 _RDRT.Bits.RDRT2\r
+#define RDRT_RDRT3 _RDRT.Bits.RDRT3\r
+#define RDRT_RDRT4 _RDRT.Bits.RDRT4\r
+#define RDRT_RDRT5 _RDRT.Bits.RDRT5\r
+#define RDRT_RDRT6 _RDRT.Bits.RDRT6\r
+#define RDRT_RDRT7 _RDRT.Bits.RDRT7\r
+#define RDRT_RDRT _RDRT.MergedBits.grpRDRT\r
+\r
+\r
+/*** PERT - Port T Pull Device Enable Register; 0x00000244 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PERT0 :1; /* Pull Device Enable Port T Bit 0 */\r
+ byte PERT1 :1; /* Pull Device Enable Port T Bit 1 */\r
+ byte PERT2 :1; /* Pull Device Enable Port T Bit 2 */\r
+ byte PERT3 :1; /* Pull Device Enable Port T Bit 3 */\r
+ byte PERT4 :1; /* Pull Device Enable Port T Bit 4 */\r
+ byte PERT5 :1; /* Pull Device Enable Port T Bit 5 */\r
+ byte PERT6 :1; /* Pull Device Enable Port T Bit 6 */\r
+ byte PERT7 :1; /* Pull Device Enable Port T Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpPERT :8;\r
+ } MergedBits;\r
+} PERTSTR;\r
+extern volatile PERTSTR _PERT @(REG_BASE + 0x00000244);\r
+#define PERT _PERT.Byte\r
+#define PERT_PERT0 _PERT.Bits.PERT0\r
+#define PERT_PERT1 _PERT.Bits.PERT1\r
+#define PERT_PERT2 _PERT.Bits.PERT2\r
+#define PERT_PERT3 _PERT.Bits.PERT3\r
+#define PERT_PERT4 _PERT.Bits.PERT4\r
+#define PERT_PERT5 _PERT.Bits.PERT5\r
+#define PERT_PERT6 _PERT.Bits.PERT6\r
+#define PERT_PERT7 _PERT.Bits.PERT7\r
+#define PERT_PERT _PERT.MergedBits.grpPERT\r
+\r
+\r
+/*** PPST - Port T Polarity Select Register; 0x00000245 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PPST0 :1; /* Pull Select Port T Bit 0 */\r
+ byte PPST1 :1; /* Pull Select Port T Bit 1 */\r
+ byte PPST2 :1; /* Pull Select Port T Bit 2 */\r
+ byte PPST3 :1; /* Pull Select Port T Bit 3 */\r
+ byte PPST4 :1; /* Pull Select Port T Bit 4 */\r
+ byte PPST5 :1; /* Pull Select Port T Bit 5 */\r
+ byte PPST6 :1; /* Pull Select Port T Bit 6 */\r
+ byte PPST7 :1; /* Pull Select Port T Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpPPST :8;\r
+ } MergedBits;\r
+} PPSTSTR;\r
+extern volatile PPSTSTR _PPST @(REG_BASE + 0x00000245);\r
+#define PPST _PPST.Byte\r
+#define PPST_PPST0 _PPST.Bits.PPST0\r
+#define PPST_PPST1 _PPST.Bits.PPST1\r
+#define PPST_PPST2 _PPST.Bits.PPST2\r
+#define PPST_PPST3 _PPST.Bits.PPST3\r
+#define PPST_PPST4 _PPST.Bits.PPST4\r
+#define PPST_PPST5 _PPST.Bits.PPST5\r
+#define PPST_PPST6 _PPST.Bits.PPST6\r
+#define PPST_PPST7 _PPST.Bits.PPST7\r
+#define PPST_PPST _PPST.MergedBits.grpPPST\r
+\r
+\r
+/*** MODRR - Module Routing Register; 0x00000247 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte MODRR0 :1; /* Module Routing Bit 0 */\r
+ byte MODRR1 :1; /* Module Routing Bit 1 */\r
+ byte MODRR2 :1; /* Module Routing Bit 2 */\r
+ byte MODRR3 :1; /* Module Routing Bit 3 */\r
+ byte MODRR4 :1; /* Module Routing Bit 4 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpMODRR :5;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} MODRRSTR;\r
+extern volatile MODRRSTR _MODRR @(REG_BASE + 0x00000247);\r
+#define MODRR _MODRR.Byte\r
+#define MODRR_MODRR0 _MODRR.Bits.MODRR0\r
+#define MODRR_MODRR1 _MODRR.Bits.MODRR1\r
+#define MODRR_MODRR2 _MODRR.Bits.MODRR2\r
+#define MODRR_MODRR3 _MODRR.Bits.MODRR3\r
+#define MODRR_MODRR4 _MODRR.Bits.MODRR4\r
+#define MODRR_MODRR _MODRR.MergedBits.grpMODRR\r
+\r
+\r
+/*** PTS - Port S I/O Register; 0x00000248 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PTS0 :1; /* Port S Bit 0 */\r
+ byte PTS1 :1; /* Port S Bit 1 */\r
+ byte PTS2 :1; /* Port S Bit 2 */\r
+ byte PTS3 :1; /* Port S Bit 3 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpPTS :4;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} PTSSTR;\r
+extern volatile PTSSTR _PTS @(REG_BASE + 0x00000248);\r
+#define PTS _PTS.Byte\r
+#define PTS_PTS0 _PTS.Bits.PTS0\r
+#define PTS_PTS1 _PTS.Bits.PTS1\r
+#define PTS_PTS2 _PTS.Bits.PTS2\r
+#define PTS_PTS3 _PTS.Bits.PTS3\r
+#define PTS_PTS _PTS.MergedBits.grpPTS\r
+\r
+\r
+/*** PTIS - Port S Input; 0x00000249 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PTIS0 :1; /* Port S Bit 0 */\r
+ byte PTIS1 :1; /* Port S Bit 1 */\r
+ byte PTIS2 :1; /* Port S Bit 2 */\r
+ byte PTIS3 :1; /* Port S Bit 3 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpPTIS :4;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} PTISSTR;\r
+extern volatile PTISSTR _PTIS @(REG_BASE + 0x00000249);\r
+#define PTIS _PTIS.Byte\r
+#define PTIS_PTIS0 _PTIS.Bits.PTIS0\r
+#define PTIS_PTIS1 _PTIS.Bits.PTIS1\r
+#define PTIS_PTIS2 _PTIS.Bits.PTIS2\r
+#define PTIS_PTIS3 _PTIS.Bits.PTIS3\r
+#define PTIS_PTIS _PTIS.MergedBits.grpPTIS\r
+\r
+\r
+/*** DDRS - Port S Data Direction Register; 0x0000024A ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DDRS0 :1; /* Data Direction Port S Bit 0 */\r
+ byte DDRS1 :1; /* Data Direction Port S Bit 1 */\r
+ byte DDRS2 :1; /* Data Direction Port S Bit 2 */\r
+ byte DDRS3 :1; /* Data Direction Port S Bit 3 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpDDRS :4;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} DDRSSTR;\r
+extern volatile DDRSSTR _DDRS @(REG_BASE + 0x0000024A);\r
+#define DDRS _DDRS.Byte\r
+#define DDRS_DDRS0 _DDRS.Bits.DDRS0\r
+#define DDRS_DDRS1 _DDRS.Bits.DDRS1\r
+#define DDRS_DDRS2 _DDRS.Bits.DDRS2\r
+#define DDRS_DDRS3 _DDRS.Bits.DDRS3\r
+#define DDRS_DDRS _DDRS.MergedBits.grpDDRS\r
+\r
+\r
+/*** RDRS - Port S Reduced Drive Register; 0x0000024B ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte RDRS0 :1; /* Reduced Drive Port S Bit 0 */\r
+ byte RDRS1 :1; /* Reduced Drive Port S Bit 1 */\r
+ byte RDRS2 :1; /* Reduced Drive Port S Bit 2 */\r
+ byte RDRS3 :1; /* Reduced Drive Port S Bit 3 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpRDRS :4;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} RDRSSTR;\r
+extern volatile RDRSSTR _RDRS @(REG_BASE + 0x0000024B);\r
+#define RDRS _RDRS.Byte\r
+#define RDRS_RDRS0 _RDRS.Bits.RDRS0\r
+#define RDRS_RDRS1 _RDRS.Bits.RDRS1\r
+#define RDRS_RDRS2 _RDRS.Bits.RDRS2\r
+#define RDRS_RDRS3 _RDRS.Bits.RDRS3\r
+#define RDRS_RDRS _RDRS.MergedBits.grpRDRS\r
+\r
+\r
+/*** PERS - Port S Pull Device Enable Register; 0x0000024C ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PERS0 :1; /* Pull Device Enable Port S Bit 0 */\r
+ byte PERS1 :1; /* Pull Device Enable Port S Bit 1 */\r
+ byte PERS2 :1; /* Pull Device Enable Port S Bit 2 */\r
+ byte PERS3 :1; /* Pull Device Enable Port S Bit 3 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpPERS :4;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} PERSSTR;\r
+extern volatile PERSSTR _PERS @(REG_BASE + 0x0000024C);\r
+#define PERS _PERS.Byte\r
+#define PERS_PERS0 _PERS.Bits.PERS0\r
+#define PERS_PERS1 _PERS.Bits.PERS1\r
+#define PERS_PERS2 _PERS.Bits.PERS2\r
+#define PERS_PERS3 _PERS.Bits.PERS3\r
+#define PERS_PERS _PERS.MergedBits.grpPERS\r
+\r
+\r
+/*** PPSS - Port S Polarity Select Register; 0x0000024D ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PPSS0 :1; /* Pull Select Port S Bit 0 */\r
+ byte PPSS1 :1; /* Pull Select Port S Bit 1 */\r
+ byte PPSS2 :1; /* Pull Select Port S Bit 2 */\r
+ byte PPSS3 :1; /* Pull Select Port S Bit 3 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpPPSS :4;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} PPSSSTR;\r
+extern volatile PPSSSTR _PPSS @(REG_BASE + 0x0000024D);\r
+#define PPSS _PPSS.Byte\r
+#define PPSS_PPSS0 _PPSS.Bits.PPSS0\r
+#define PPSS_PPSS1 _PPSS.Bits.PPSS1\r
+#define PPSS_PPSS2 _PPSS.Bits.PPSS2\r
+#define PPSS_PPSS3 _PPSS.Bits.PPSS3\r
+#define PPSS_PPSS _PPSS.MergedBits.grpPPSS\r
+\r
+\r
+/*** WOMS - Port S Wired-Or Mode Register; 0x0000024E ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte WOMS0 :1; /* Wired-Or Mode Port S Bit 0 */\r
+ byte WOMS1 :1; /* Wired-Or Mode Port S Bit 1 */\r
+ byte WOMS2 :1; /* Wired-Or Mode Port S Bit 2 */\r
+ byte WOMS3 :1; /* Wired-Or Mode Port S Bit 3 */\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpWOMS :4;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} WOMSSTR;\r
+extern volatile WOMSSTR _WOMS @(REG_BASE + 0x0000024E);\r
+#define WOMS _WOMS.Byte\r
+#define WOMS_WOMS0 _WOMS.Bits.WOMS0\r
+#define WOMS_WOMS1 _WOMS.Bits.WOMS1\r
+#define WOMS_WOMS2 _WOMS.Bits.WOMS2\r
+#define WOMS_WOMS3 _WOMS.Bits.WOMS3\r
+#define WOMS_WOMS _WOMS.MergedBits.grpWOMS\r
+\r
+\r
+/*** PTM - Port M I/O Register; 0x00000250 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PTM0 :1; /* Port T Bit 0 */\r
+ byte PTM1 :1; /* Port T Bit 1 */\r
+ byte PTM2 :1; /* Port T Bit 2 */\r
+ byte PTM3 :1; /* Port T Bit 3 */\r
+ byte PTM4 :1; /* Port T Bit 4 */\r
+ byte PTM5 :1; /* Port T Bit 5 */\r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpPTM :6;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} PTMSTR;\r
+extern volatile PTMSTR _PTM @(REG_BASE + 0x00000250);\r
+#define PTM _PTM.Byte\r
+#define PTM_PTM0 _PTM.Bits.PTM0\r
+#define PTM_PTM1 _PTM.Bits.PTM1\r
+#define PTM_PTM2 _PTM.Bits.PTM2\r
+#define PTM_PTM3 _PTM.Bits.PTM3\r
+#define PTM_PTM4 _PTM.Bits.PTM4\r
+#define PTM_PTM5 _PTM.Bits.PTM5\r
+#define PTM_PTM _PTM.MergedBits.grpPTM\r
+\r
+\r
+/*** PTIM - Port M Input; 0x00000251 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PTIM0 :1; /* Port M Bit 0 */\r
+ byte PTIM1 :1; /* Port M Bit 1 */\r
+ byte PTIM2 :1; /* Port M Bit 2 */\r
+ byte PTIM3 :1; /* Port M Bit 3 */\r
+ byte PTIM4 :1; /* Port M Bit 4 */\r
+ byte PTIM5 :1; /* Port M Bit 5 */\r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpPTIM :6;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} PTIMSTR;\r
+extern volatile PTIMSTR _PTIM @(REG_BASE + 0x00000251);\r
+#define PTIM _PTIM.Byte\r
+#define PTIM_PTIM0 _PTIM.Bits.PTIM0\r
+#define PTIM_PTIM1 _PTIM.Bits.PTIM1\r
+#define PTIM_PTIM2 _PTIM.Bits.PTIM2\r
+#define PTIM_PTIM3 _PTIM.Bits.PTIM3\r
+#define PTIM_PTIM4 _PTIM.Bits.PTIM4\r
+#define PTIM_PTIM5 _PTIM.Bits.PTIM5\r
+#define PTIM_PTIM _PTIM.MergedBits.grpPTIM\r
+\r
+\r
+/*** DDRM - Port M Data Direction Register; 0x00000252 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DDRM0 :1; /* Data Direction Port M Bit 0 */\r
+ byte DDRM1 :1; /* Data Direction Port M Bit 1 */\r
+ byte DDRM2 :1; /* Data Direction Port M Bit 2 */\r
+ byte DDRM3 :1; /* Data Direction Port M Bit 3 */\r
+ byte DDRM4 :1; /* Data Direction Port M Bit 4 */\r
+ byte DDRM5 :1; /* Data Direction Port M Bit 5 */\r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpDDRM :6;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} DDRMSTR;\r
+extern volatile DDRMSTR _DDRM @(REG_BASE + 0x00000252);\r
+#define DDRM _DDRM.Byte\r
+#define DDRM_DDRM0 _DDRM.Bits.DDRM0\r
+#define DDRM_DDRM1 _DDRM.Bits.DDRM1\r
+#define DDRM_DDRM2 _DDRM.Bits.DDRM2\r
+#define DDRM_DDRM3 _DDRM.Bits.DDRM3\r
+#define DDRM_DDRM4 _DDRM.Bits.DDRM4\r
+#define DDRM_DDRM5 _DDRM.Bits.DDRM5\r
+#define DDRM_DDRM _DDRM.MergedBits.grpDDRM\r
+\r
+\r
+/*** RDRM - Port M Reduced Drive Register; 0x00000253 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte RDRM0 :1; /* Reduced Drive Port M Bit 0 */\r
+ byte RDRM1 :1; /* Reduced Drive Port M Bit 1 */\r
+ byte RDRM2 :1; /* Reduced Drive Port M Bit 2 */\r
+ byte RDRM3 :1; /* Reduced Drive Port M Bit 3 */\r
+ byte RDRM4 :1; /* Reduced Drive Port M Bit 4 */\r
+ byte RDRM5 :1; /* Reduced Drive Port M Bit 5 */\r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpRDRM :6;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} RDRMSTR;\r
+extern volatile RDRMSTR _RDRM @(REG_BASE + 0x00000253);\r
+#define RDRM _RDRM.Byte\r
+#define RDRM_RDRM0 _RDRM.Bits.RDRM0\r
+#define RDRM_RDRM1 _RDRM.Bits.RDRM1\r
+#define RDRM_RDRM2 _RDRM.Bits.RDRM2\r
+#define RDRM_RDRM3 _RDRM.Bits.RDRM3\r
+#define RDRM_RDRM4 _RDRM.Bits.RDRM4\r
+#define RDRM_RDRM5 _RDRM.Bits.RDRM5\r
+#define RDRM_RDRM _RDRM.MergedBits.grpRDRM\r
+\r
+\r
+/*** PERM - Port M Pull Device Enable Register; 0x00000254 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PERM0 :1; /* Pull Device Enable Port M Bit 0 */\r
+ byte PERM1 :1; /* Pull Device Enable Port M Bit 1 */\r
+ byte PERM2 :1; /* Pull Device Enable Port M Bit 2 */\r
+ byte PERM3 :1; /* Pull Device Enable Port M Bit 3 */\r
+ byte PERM4 :1; /* Pull Device Enable Port M Bit 4 */\r
+ byte PERM5 :1; /* Pull Device Enable Port M Bit 5 */\r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpPERM :6;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} PERMSTR;\r
+extern volatile PERMSTR _PERM @(REG_BASE + 0x00000254);\r
+#define PERM _PERM.Byte\r
+#define PERM_PERM0 _PERM.Bits.PERM0\r
+#define PERM_PERM1 _PERM.Bits.PERM1\r
+#define PERM_PERM2 _PERM.Bits.PERM2\r
+#define PERM_PERM3 _PERM.Bits.PERM3\r
+#define PERM_PERM4 _PERM.Bits.PERM4\r
+#define PERM_PERM5 _PERM.Bits.PERM5\r
+#define PERM_PERM _PERM.MergedBits.grpPERM\r
+\r
+\r
+/*** PPSM - Port M Polarity Select Register; 0x00000255 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PPSM0 :1; /* Pull Select Port M Bit 0 */\r
+ byte PPSM1 :1; /* Pull Select Port M Bit 1 */\r
+ byte PPSM2 :1; /* Pull Select Port M Bit 2 */\r
+ byte PPSM3 :1; /* Pull Select Port M Bit 3 */\r
+ byte PPSM4 :1; /* Pull Select Port M Bit 4 */\r
+ byte PPSM5 :1; /* Pull Select Port M Bit 5 */\r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpPPSM :6;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} PPSMSTR;\r
+extern volatile PPSMSTR _PPSM @(REG_BASE + 0x00000255);\r
+#define PPSM _PPSM.Byte\r
+#define PPSM_PPSM0 _PPSM.Bits.PPSM0\r
+#define PPSM_PPSM1 _PPSM.Bits.PPSM1\r
+#define PPSM_PPSM2 _PPSM.Bits.PPSM2\r
+#define PPSM_PPSM3 _PPSM.Bits.PPSM3\r
+#define PPSM_PPSM4 _PPSM.Bits.PPSM4\r
+#define PPSM_PPSM5 _PPSM.Bits.PPSM5\r
+#define PPSM_PPSM _PPSM.MergedBits.grpPPSM\r
+\r
+\r
+/*** WOMM - Port M Wired-Or Mode Register; 0x00000256 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte WOMM0 :1; /* Wired-Or Mode Port M Bit 0 */\r
+ byte WOMM1 :1; /* Wired-Or Mode Port M Bit 1 */\r
+ byte WOMM2 :1; /* Wired-Or Mode Port M Bit 2 */\r
+ byte WOMM3 :1; /* Wired-Or Mode Port M Bit 3 */\r
+ byte WOMM4 :1; /* Wired-Or Mode Port M Bit 4 */\r
+ byte WOMM5 :1; /* Wired-Or Mode Port M Bit 5 */\r
+ byte :1; \r
+ byte :1; \r
+ } Bits;\r
+ struct {\r
+ byte grpWOMM :6;\r
+ byte :1;\r
+ byte :1;\r
+ } MergedBits;\r
+} WOMMSTR;\r
+extern volatile WOMMSTR _WOMM @(REG_BASE + 0x00000256);\r
+#define WOMM _WOMM.Byte\r
+#define WOMM_WOMM0 _WOMM.Bits.WOMM0\r
+#define WOMM_WOMM1 _WOMM.Bits.WOMM1\r
+#define WOMM_WOMM2 _WOMM.Bits.WOMM2\r
+#define WOMM_WOMM3 _WOMM.Bits.WOMM3\r
+#define WOMM_WOMM4 _WOMM.Bits.WOMM4\r
+#define WOMM_WOMM5 _WOMM.Bits.WOMM5\r
+#define WOMM_WOMM _WOMM.MergedBits.grpWOMM\r
+\r
+\r
+/*** PTP - Port P I/O Register; 0x00000258 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PTP0 :1; /* Port P Bit 0 */\r
+ byte PTP1 :1; /* Port P Bit 1 */\r
+ byte PTP2 :1; /* Port P Bit 2 */\r
+ byte PTP3 :1; /* Port P Bit 3 */\r
+ byte PTP4 :1; /* Port P Bit 4 */\r
+ byte PTP5 :1; /* Port P Bit 5 */\r
+ byte PTP6 :1; /* Port P Bit 6 */\r
+ byte PTP7 :1; /* Port P Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpPTP :8;\r
+ } MergedBits;\r
+} PTPSTR;\r
+extern volatile PTPSTR _PTP @(REG_BASE + 0x00000258);\r
+#define PTP _PTP.Byte\r
+#define PTP_PTP0 _PTP.Bits.PTP0\r
+#define PTP_PTP1 _PTP.Bits.PTP1\r
+#define PTP_PTP2 _PTP.Bits.PTP2\r
+#define PTP_PTP3 _PTP.Bits.PTP3\r
+#define PTP_PTP4 _PTP.Bits.PTP4\r
+#define PTP_PTP5 _PTP.Bits.PTP5\r
+#define PTP_PTP6 _PTP.Bits.PTP6\r
+#define PTP_PTP7 _PTP.Bits.PTP7\r
+#define PTP_PTP _PTP.MergedBits.grpPTP\r
+\r
+\r
+/*** PTIP - Port P Input; 0x00000259 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PTIP0 :1; /* Port P Bit 0 */\r
+ byte PTIP1 :1; /* Port P Bit 1 */\r
+ byte PTIP2 :1; /* Port P Bit 2 */\r
+ byte PTIP3 :1; /* Port P Bit 3 */\r
+ byte PTIP4 :1; /* Port P Bit 4 */\r
+ byte PTIP5 :1; /* Port P Bit 5 */\r
+ byte PTIP6 :1; /* Port P Bit 6 */\r
+ byte PTIP7 :1; /* Port P Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpPTIP :8;\r
+ } MergedBits;\r
+} PTIPSTR;\r
+extern volatile PTIPSTR _PTIP @(REG_BASE + 0x00000259);\r
+#define PTIP _PTIP.Byte\r
+#define PTIP_PTIP0 _PTIP.Bits.PTIP0\r
+#define PTIP_PTIP1 _PTIP.Bits.PTIP1\r
+#define PTIP_PTIP2 _PTIP.Bits.PTIP2\r
+#define PTIP_PTIP3 _PTIP.Bits.PTIP3\r
+#define PTIP_PTIP4 _PTIP.Bits.PTIP4\r
+#define PTIP_PTIP5 _PTIP.Bits.PTIP5\r
+#define PTIP_PTIP6 _PTIP.Bits.PTIP6\r
+#define PTIP_PTIP7 _PTIP.Bits.PTIP7\r
+#define PTIP_PTIP _PTIP.MergedBits.grpPTIP\r
+\r
+\r
+/*** DDRP - Port P Data Direction Register; 0x0000025A ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DDRP0 :1; /* Data Direction Port P Bit 0 */\r
+ byte DDRP1 :1; /* Data Direction Port P Bit 1 */\r
+ byte DDRP2 :1; /* Data Direction Port P Bit 2 */\r
+ byte DDRP3 :1; /* Data Direction Port P Bit 3 */\r
+ byte DDRP4 :1; /* Data Direction Port P Bit 4 */\r
+ byte DDRP5 :1; /* Data Direction Port P Bit 5 */\r
+ byte DDRP6 :1; /* Data Direction Port P Bit 6 */\r
+ byte DDRP7 :1; /* Data Direction Port P Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDDRP :8;\r
+ } MergedBits;\r
+} DDRPSTR;\r
+extern volatile DDRPSTR _DDRP @(REG_BASE + 0x0000025A);\r
+#define DDRP _DDRP.Byte\r
+#define DDRP_DDRP0 _DDRP.Bits.DDRP0\r
+#define DDRP_DDRP1 _DDRP.Bits.DDRP1\r
+#define DDRP_DDRP2 _DDRP.Bits.DDRP2\r
+#define DDRP_DDRP3 _DDRP.Bits.DDRP3\r
+#define DDRP_DDRP4 _DDRP.Bits.DDRP4\r
+#define DDRP_DDRP5 _DDRP.Bits.DDRP5\r
+#define DDRP_DDRP6 _DDRP.Bits.DDRP6\r
+#define DDRP_DDRP7 _DDRP.Bits.DDRP7\r
+#define DDRP_DDRP _DDRP.MergedBits.grpDDRP\r
+\r
+\r
+/*** RDRP - Port P Reduced Drive Register; 0x0000025B ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte RDRP0 :1; /* Reduced Drive Port P Bit 0 */\r
+ byte RDRP1 :1; /* Reduced Drive Port P Bit 1 */\r
+ byte RDRP2 :1; /* Reduced Drive Port P Bit 2 */\r
+ byte RDRP3 :1; /* Reduced Drive Port P Bit 3 */\r
+ byte RDRP4 :1; /* Reduced Drive Port P Bit 4 */\r
+ byte RDRP5 :1; /* Reduced Drive Port P Bit 5 */\r
+ byte RDRP6 :1; /* Reduced Drive Port P Bit 6 */\r
+ byte RDRP7 :1; /* Reduced Drive Port P Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpRDRP :8;\r
+ } MergedBits;\r
+} RDRPSTR;\r
+extern volatile RDRPSTR _RDRP @(REG_BASE + 0x0000025B);\r
+#define RDRP _RDRP.Byte\r
+#define RDRP_RDRP0 _RDRP.Bits.RDRP0\r
+#define RDRP_RDRP1 _RDRP.Bits.RDRP1\r
+#define RDRP_RDRP2 _RDRP.Bits.RDRP2\r
+#define RDRP_RDRP3 _RDRP.Bits.RDRP3\r
+#define RDRP_RDRP4 _RDRP.Bits.RDRP4\r
+#define RDRP_RDRP5 _RDRP.Bits.RDRP5\r
+#define RDRP_RDRP6 _RDRP.Bits.RDRP6\r
+#define RDRP_RDRP7 _RDRP.Bits.RDRP7\r
+#define RDRP_RDRP _RDRP.MergedBits.grpRDRP\r
+\r
+\r
+/*** PERP - Port P Pull Device Enable Register; 0x0000025C ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PERP0 :1; /* Pull Device Enable Port P Bit 0 */\r
+ byte PERP1 :1; /* Pull Device Enable Port P Bit 1 */\r
+ byte PERP2 :1; /* Pull Device Enable Port P Bit 2 */\r
+ byte PERP3 :1; /* Pull Device Enable Port P Bit 3 */\r
+ byte PERP4 :1; /* Pull Device Enable Port P Bit 4 */\r
+ byte PERP5 :1; /* Pull Device Enable Port P Bit 5 */\r
+ byte PERP6 :1; /* Pull Device Enable Port P Bit 6 */\r
+ byte PERP7 :1; /* Pull Device Enable Port P Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpPERP :8;\r
+ } MergedBits;\r
+} PERPSTR;\r
+extern volatile PERPSTR _PERP @(REG_BASE + 0x0000025C);\r
+#define PERP _PERP.Byte\r
+#define PERP_PERP0 _PERP.Bits.PERP0\r
+#define PERP_PERP1 _PERP.Bits.PERP1\r
+#define PERP_PERP2 _PERP.Bits.PERP2\r
+#define PERP_PERP3 _PERP.Bits.PERP3\r
+#define PERP_PERP4 _PERP.Bits.PERP4\r
+#define PERP_PERP5 _PERP.Bits.PERP5\r
+#define PERP_PERP6 _PERP.Bits.PERP6\r
+#define PERP_PERP7 _PERP.Bits.PERP7\r
+#define PERP_PERP _PERP.MergedBits.grpPERP\r
+\r
+\r
+/*** PPSP - Port P Polarity Select Register; 0x0000025D ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PPSP0 :1; /* Pull Select Port P Bit 0 */\r
+ byte PPSP1 :1; /* Pull Select Port P Bit 1 */\r
+ byte PPSP2 :1; /* Pull Select Port P Bit 2 */\r
+ byte PPSP3 :1; /* Pull Select Port P Bit 3 */\r
+ byte PPSP4 :1; /* Pull Select Port P Bit 4 */\r
+ byte PPSP5 :1; /* Pull Select Port P Bit 5 */\r
+ byte PPSP6 :1; /* Pull Select Port P Bit 6 */\r
+ byte PPSP7 :1; /* Pull Select Port P Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpPPSP :8;\r
+ } MergedBits;\r
+} PPSPSTR;\r
+extern volatile PPSPSTR _PPSP @(REG_BASE + 0x0000025D);\r
+#define PPSP _PPSP.Byte\r
+#define PPSP_PPSP0 _PPSP.Bits.PPSP0\r
+#define PPSP_PPSP1 _PPSP.Bits.PPSP1\r
+#define PPSP_PPSP2 _PPSP.Bits.PPSP2\r
+#define PPSP_PPSP3 _PPSP.Bits.PPSP3\r
+#define PPSP_PPSP4 _PPSP.Bits.PPSP4\r
+#define PPSP_PPSP5 _PPSP.Bits.PPSP5\r
+#define PPSP_PPSP6 _PPSP.Bits.PPSP6\r
+#define PPSP_PPSP7 _PPSP.Bits.PPSP7\r
+#define PPSP_PPSP _PPSP.MergedBits.grpPPSP\r
+\r
+\r
+/*** PIEP - Port P Interrupt Enable Register; 0x0000025E ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PIEP0 :1; /* Interrupt Enable Port P Bit 0 */\r
+ byte PIEP1 :1; /* Interrupt Enable Port P Bit 1 */\r
+ byte PIEP2 :1; /* Interrupt Enable Port P Bit 2 */\r
+ byte PIEP3 :1; /* Interrupt Enable Port P Bit 3 */\r
+ byte PIEP4 :1; /* Interrupt Enable Port P Bit 4 */\r
+ byte PIEP5 :1; /* Interrupt Enable Port P Bit 5 */\r
+ byte PIEP6 :1; /* Interrupt Enable Port P Bit 6 */\r
+ byte PIEP7 :1; /* Interrupt Enable Port P Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpPIEP :8;\r
+ } MergedBits;\r
+} PIEPSTR;\r
+extern volatile PIEPSTR _PIEP @(REG_BASE + 0x0000025E);\r
+#define PIEP _PIEP.Byte\r
+#define PIEP_PIEP0 _PIEP.Bits.PIEP0\r
+#define PIEP_PIEP1 _PIEP.Bits.PIEP1\r
+#define PIEP_PIEP2 _PIEP.Bits.PIEP2\r
+#define PIEP_PIEP3 _PIEP.Bits.PIEP3\r
+#define PIEP_PIEP4 _PIEP.Bits.PIEP4\r
+#define PIEP_PIEP5 _PIEP.Bits.PIEP5\r
+#define PIEP_PIEP6 _PIEP.Bits.PIEP6\r
+#define PIEP_PIEP7 _PIEP.Bits.PIEP7\r
+#define PIEP_PIEP _PIEP.MergedBits.grpPIEP\r
+\r
+\r
+/*** PIFP - Port P Interrupt Flag Register; 0x0000025F ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PIFP0 :1; /* Interrupt Flags Port P Bit 0 */\r
+ byte PIFP1 :1; /* Interrupt Flags Port P Bit 1 */\r
+ byte PIFP2 :1; /* Interrupt Flags Port P Bit 2 */\r
+ byte PIFP3 :1; /* Interrupt Flags Port P Bit 3 */\r
+ byte PIFP4 :1; /* Interrupt Flags Port P Bit 4 */\r
+ byte PIFP5 :1; /* Interrupt Flags Port P Bit 5 */\r
+ byte PIFP6 :1; /* Interrupt Flags Port P Bit 6 */\r
+ byte PIFP7 :1; /* Interrupt Flags Port P Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpPIFP :8;\r
+ } MergedBits;\r
+} PIFPSTR;\r
+extern volatile PIFPSTR _PIFP @(REG_BASE + 0x0000025F);\r
+#define PIFP _PIFP.Byte\r
+#define PIFP_PIFP0 _PIFP.Bits.PIFP0\r
+#define PIFP_PIFP1 _PIFP.Bits.PIFP1\r
+#define PIFP_PIFP2 _PIFP.Bits.PIFP2\r
+#define PIFP_PIFP3 _PIFP.Bits.PIFP3\r
+#define PIFP_PIFP4 _PIFP.Bits.PIFP4\r
+#define PIFP_PIFP5 _PIFP.Bits.PIFP5\r
+#define PIFP_PIFP6 _PIFP.Bits.PIFP6\r
+#define PIFP_PIFP7 _PIFP.Bits.PIFP7\r
+#define PIFP_PIFP _PIFP.MergedBits.grpPIFP\r
+\r
+\r
+/*** PTJ - Port J I/O Register; 0x00000268 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte PTJ6 :1; /* Port J Bit 6 */\r
+ byte PTJ7 :1; /* Port J Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpPTJ_6 :2;\r
+ } MergedBits;\r
+} PTJSTR;\r
+extern volatile PTJSTR _PTJ @(REG_BASE + 0x00000268);\r
+#define PTJ _PTJ.Byte\r
+#define PTJ_PTJ6 _PTJ.Bits.PTJ6\r
+#define PTJ_PTJ7 _PTJ.Bits.PTJ7\r
+#define PTJ_PTJ_6 _PTJ.MergedBits.grpPTJ_6\r
+\r
+\r
+/*** PTIJ - Port J Input Register; 0x00000269 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte PTIJ6 :1; /* Port J Bit 6 */\r
+ byte PTIJ7 :1; /* Port J Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpPTIJ_6 :2;\r
+ } MergedBits;\r
+} PTIJSTR;\r
+extern volatile PTIJSTR _PTIJ @(REG_BASE + 0x00000269);\r
+#define PTIJ _PTIJ.Byte\r
+#define PTIJ_PTIJ6 _PTIJ.Bits.PTIJ6\r
+#define PTIJ_PTIJ7 _PTIJ.Bits.PTIJ7\r
+#define PTIJ_PTIJ_6 _PTIJ.MergedBits.grpPTIJ_6\r
+\r
+\r
+/*** DDRJ - Port J Data Direction Register; 0x0000026A ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte DDRJ6 :1; /* Data Direction Port J Bit 6 */\r
+ byte DDRJ7 :1; /* Data Direction Port J Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpDDRJ_6 :2;\r
+ } MergedBits;\r
+} DDRJSTR;\r
+extern volatile DDRJSTR _DDRJ @(REG_BASE + 0x0000026A);\r
+#define DDRJ _DDRJ.Byte\r
+#define DDRJ_DDRJ6 _DDRJ.Bits.DDRJ6\r
+#define DDRJ_DDRJ7 _DDRJ.Bits.DDRJ7\r
+#define DDRJ_DDRJ_6 _DDRJ.MergedBits.grpDDRJ_6\r
+\r
+\r
+/*** RDRJ - Port J Reduced Drive Register; 0x0000026B ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte RDRJ6 :1; /* Reduced Drive Port J Bit 6 */\r
+ byte RDRJ7 :1; /* Reduced Drive Port J Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpRDRJ_6 :2;\r
+ } MergedBits;\r
+} RDRJSTR;\r
+extern volatile RDRJSTR _RDRJ @(REG_BASE + 0x0000026B);\r
+#define RDRJ _RDRJ.Byte\r
+#define RDRJ_RDRJ6 _RDRJ.Bits.RDRJ6\r
+#define RDRJ_RDRJ7 _RDRJ.Bits.RDRJ7\r
+#define RDRJ_RDRJ_6 _RDRJ.MergedBits.grpRDRJ_6\r
+\r
+\r
+/*** PERJ - Port J Pull Device Enable Register; 0x0000026C ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte PERJ6 :1; /* Pull Device Enable Port J Bit 6 */\r
+ byte PERJ7 :1; /* Pull Device Enable Port J Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpPERJ_6 :2;\r
+ } MergedBits;\r
+} PERJSTR;\r
+extern volatile PERJSTR _PERJ @(REG_BASE + 0x0000026C);\r
+#define PERJ _PERJ.Byte\r
+#define PERJ_PERJ6 _PERJ.Bits.PERJ6\r
+#define PERJ_PERJ7 _PERJ.Bits.PERJ7\r
+#define PERJ_PERJ_6 _PERJ.MergedBits.grpPERJ_6\r
+\r
+\r
+/*** PPSJ - PortJP Polarity Select Register; 0x0000026D ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte PPSJ6 :1; /* Pull Select Port J Bit 6 */\r
+ byte PPSJ7 :1; /* Pull Select Port J Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpPPSJ_6 :2;\r
+ } MergedBits;\r
+} PPSJSTR;\r
+extern volatile PPSJSTR _PPSJ @(REG_BASE + 0x0000026D);\r
+#define PPSJ _PPSJ.Byte\r
+#define PPSJ_PPSJ6 _PPSJ.Bits.PPSJ6\r
+#define PPSJ_PPSJ7 _PPSJ.Bits.PPSJ7\r
+#define PPSJ_PPSJ_6 _PPSJ.MergedBits.grpPPSJ_6\r
+\r
+\r
+/*** PIEJ - Port J Interrupt Enable Register; 0x0000026E ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte PIEJ6 :1; /* Interrupt Enable Port J Bit 6 */\r
+ byte PIEJ7 :1; /* Interrupt Enable Port J Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpPIEJ_6 :2;\r
+ } MergedBits;\r
+} PIEJSTR;\r
+extern volatile PIEJSTR _PIEJ @(REG_BASE + 0x0000026E);\r
+#define PIEJ _PIEJ.Byte\r
+#define PIEJ_PIEJ6 _PIEJ.Bits.PIEJ6\r
+#define PIEJ_PIEJ7 _PIEJ.Bits.PIEJ7\r
+#define PIEJ_PIEJ_6 _PIEJ.MergedBits.grpPIEJ_6\r
+\r
+\r
+/*** PIFJ - Port J Interrupt Flag Register; 0x0000026F ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte PIFJ6 :1; /* Interrupt Flags Port J Bit 6 */\r
+ byte PIFJ7 :1; /* Interrupt Flags Port J Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpPIFJ_6 :2;\r
+ } MergedBits;\r
+} PIFJSTR;\r
+extern volatile PIFJSTR _PIFJ @(REG_BASE + 0x0000026F);\r
+#define PIFJ _PIFJ.Byte\r
+#define PIFJ_PIFJ6 _PIFJ.Bits.PIFJ6\r
+#define PIFJ_PIFJ7 _PIFJ.Bits.PIFJ7\r
+#define PIFJ_PIFJ_6 _PIFJ.MergedBits.grpPIFJ_6\r
+\r
+\r
+/*** PTAD - Port AD I/O Register; 0x00000270 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PTAD0 :1; /* Port AD Bit 0 */\r
+ byte PTAD1 :1; /* Port AD Bit 1 */\r
+ byte PTAD2 :1; /* Port AD Bit 2 */\r
+ byte PTAD3 :1; /* Port AD Bit 3 */\r
+ byte PTAD4 :1; /* Port AD Bit 4 */\r
+ byte PTAD5 :1; /* Port AD Bit 5 */\r
+ byte PTAD6 :1; /* Port AD Bit 6 */\r
+ byte PTAD7 :1; /* Port AD Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpPTAD :8;\r
+ } MergedBits;\r
+} PTADSTR;\r
+extern volatile PTADSTR _PTAD @(REG_BASE + 0x00000270);\r
+#define PTAD _PTAD.Byte\r
+#define PTAD_PTAD0 _PTAD.Bits.PTAD0\r
+#define PTAD_PTAD1 _PTAD.Bits.PTAD1\r
+#define PTAD_PTAD2 _PTAD.Bits.PTAD2\r
+#define PTAD_PTAD3 _PTAD.Bits.PTAD3\r
+#define PTAD_PTAD4 _PTAD.Bits.PTAD4\r
+#define PTAD_PTAD5 _PTAD.Bits.PTAD5\r
+#define PTAD_PTAD6 _PTAD.Bits.PTAD6\r
+#define PTAD_PTAD7 _PTAD.Bits.PTAD7\r
+#define PTAD_PTAD _PTAD.MergedBits.grpPTAD\r
+\r
+\r
+/*** PTIAD - Port AD Input Register; 0x00000271 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PTIAD0 :1; /* Port AD Bit 0 */\r
+ byte PTIAD1 :1; /* Port AD Bit 1 */\r
+ byte PTIAD2 :1; /* Port AD Bit 2 */\r
+ byte PTIAD3 :1; /* Port AD Bit 3 */\r
+ byte PTIAD4 :1; /* Port AD Bit 4 */\r
+ byte PTIAD5 :1; /* Port AD Bit 5 */\r
+ byte PTIAD6 :1; /* Port AD Bit 6 */\r
+ byte PTIAD7 :1; /* Port AD Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpPTIAD :8;\r
+ } MergedBits;\r
+} PTIADSTR;\r
+extern volatile PTIADSTR _PTIAD @(REG_BASE + 0x00000271);\r
+#define PTIAD _PTIAD.Byte\r
+#define PTIAD_PTIAD0 _PTIAD.Bits.PTIAD0\r
+#define PTIAD_PTIAD1 _PTIAD.Bits.PTIAD1\r
+#define PTIAD_PTIAD2 _PTIAD.Bits.PTIAD2\r
+#define PTIAD_PTIAD3 _PTIAD.Bits.PTIAD3\r
+#define PTIAD_PTIAD4 _PTIAD.Bits.PTIAD4\r
+#define PTIAD_PTIAD5 _PTIAD.Bits.PTIAD5\r
+#define PTIAD_PTIAD6 _PTIAD.Bits.PTIAD6\r
+#define PTIAD_PTIAD7 _PTIAD.Bits.PTIAD7\r
+#define PTIAD_PTIAD _PTIAD.MergedBits.grpPTIAD\r
+\r
+\r
+/*** DDRAD - Port AD Data Direction Register; 0x00000272 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte DDRAD0 :1; /* Port AD Data Direction Bit 0 */\r
+ byte DDRAD1 :1; /* Port AD Data Direction Bit 1 */\r
+ byte DDRAD2 :1; /* Port AD Data Direction Bit 2 */\r
+ byte DDRAD3 :1; /* Port AD Data Direction Bit 3 */\r
+ byte DDRAD4 :1; /* Port AD Data Direction Bit 4 */\r
+ byte DDRAD5 :1; /* Port AD Data Direction Bit 5 */\r
+ byte DDRAD6 :1; /* Port AD Data Direction Bit 6 */\r
+ byte DDRAD7 :1; /* Port AD Data Direction Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpDDRAD :8;\r
+ } MergedBits;\r
+} DDRADSTR;\r
+extern volatile DDRADSTR _DDRAD @(REG_BASE + 0x00000272);\r
+#define DDRAD _DDRAD.Byte\r
+#define DDRAD_DDRAD0 _DDRAD.Bits.DDRAD0\r
+#define DDRAD_DDRAD1 _DDRAD.Bits.DDRAD1\r
+#define DDRAD_DDRAD2 _DDRAD.Bits.DDRAD2\r
+#define DDRAD_DDRAD3 _DDRAD.Bits.DDRAD3\r
+#define DDRAD_DDRAD4 _DDRAD.Bits.DDRAD4\r
+#define DDRAD_DDRAD5 _DDRAD.Bits.DDRAD5\r
+#define DDRAD_DDRAD6 _DDRAD.Bits.DDRAD6\r
+#define DDRAD_DDRAD7 _DDRAD.Bits.DDRAD7\r
+#define DDRAD_DDRAD _DDRAD.MergedBits.grpDDRAD\r
+\r
+\r
+/*** RDRAD - Port AD Reduced Drive Register; 0x00000273 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte RDRAD0 :1; /* Port AD Reduced Drive Bit 0 */\r
+ byte RDRAD1 :1; /* Port AD Reduced Drive Bit 1 */\r
+ byte RDRAD2 :1; /* Port AD Reduced Drive Bit 2 */\r
+ byte RDRAD3 :1; /* Port AD Reduced Drive Bit 3 */\r
+ byte RDRAD4 :1; /* Port AD Reduced Drive Bit 4 */\r
+ byte RDRAD5 :1; /* Port AD Reduced Drive Bit 5 */\r
+ byte RDRAD6 :1; /* Port AD Reduced Drive Bit 6 */\r
+ byte RDRAD7 :1; /* Port AD Reduced Drive Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpRDRAD :8;\r
+ } MergedBits;\r
+} RDRADSTR;\r
+extern volatile RDRADSTR _RDRAD @(REG_BASE + 0x00000273);\r
+#define RDRAD _RDRAD.Byte\r
+#define RDRAD_RDRAD0 _RDRAD.Bits.RDRAD0\r
+#define RDRAD_RDRAD1 _RDRAD.Bits.RDRAD1\r
+#define RDRAD_RDRAD2 _RDRAD.Bits.RDRAD2\r
+#define RDRAD_RDRAD3 _RDRAD.Bits.RDRAD3\r
+#define RDRAD_RDRAD4 _RDRAD.Bits.RDRAD4\r
+#define RDRAD_RDRAD5 _RDRAD.Bits.RDRAD5\r
+#define RDRAD_RDRAD6 _RDRAD.Bits.RDRAD6\r
+#define RDRAD_RDRAD7 _RDRAD.Bits.RDRAD7\r
+#define RDRAD_RDRAD _RDRAD.MergedBits.grpRDRAD\r
+\r
+\r
+/*** PERAD - Port AD Pull Device Enable Register; 0x00000274 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PERAD0 :1; /* Port AD Pull Device Enable Bit 0 */\r
+ byte PERAD1 :1; /* Port AD Pull Device Enable Bit 1 */\r
+ byte PERAD2 :1; /* Port AD Pull Device Enable Bit 2 */\r
+ byte PERAD3 :1; /* Port AD Pull Device Enable Bit 3 */\r
+ byte PERAD4 :1; /* Port AD Pull Device Enable Bit 4 */\r
+ byte PERAD5 :1; /* Port AD Pull Device Enable Bit 5 */\r
+ byte PERAD6 :1; /* Port AD Pull Device Enable Bit 6 */\r
+ byte PERAD7 :1; /* Port AD Pull Device Enable Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpPERAD :8;\r
+ } MergedBits;\r
+} PERADSTR;\r
+extern volatile PERADSTR _PERAD @(REG_BASE + 0x00000274);\r
+#define PERAD _PERAD.Byte\r
+#define PERAD_PERAD0 _PERAD.Bits.PERAD0\r
+#define PERAD_PERAD1 _PERAD.Bits.PERAD1\r
+#define PERAD_PERAD2 _PERAD.Bits.PERAD2\r
+#define PERAD_PERAD3 _PERAD.Bits.PERAD3\r
+#define PERAD_PERAD4 _PERAD.Bits.PERAD4\r
+#define PERAD_PERAD5 _PERAD.Bits.PERAD5\r
+#define PERAD_PERAD6 _PERAD.Bits.PERAD6\r
+#define PERAD_PERAD7 _PERAD.Bits.PERAD7\r
+#define PERAD_PERAD _PERAD.MergedBits.grpPERAD\r
+\r
+\r
+/*** PPSAD - Port AD Polarity Select Register; 0x00000275 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte PPSAD0 :1; /* Port AD Polarity Select Bit 0 */\r
+ byte PPSAD1 :1; /* Port AD Polarity Select Bit 1 */\r
+ byte PPSAD2 :1; /* Port AD Polarity Select Bit 2 */\r
+ byte PPSAD3 :1; /* Port AD Polarity Select Bit 3 */\r
+ byte PPSAD4 :1; /* Port AD Polarity Select Bit 4 */\r
+ byte PPSAD5 :1; /* Port AD Polarity Select Bit 5 */\r
+ byte PPSAD6 :1; /* Port AD Polarity Select Bit 6 */\r
+ byte PPSAD7 :1; /* Port AD Polarity Select Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpPPSAD :8;\r
+ } MergedBits;\r
+} PPSADSTR;\r
+extern volatile PPSADSTR _PPSAD @(REG_BASE + 0x00000275);\r
+#define PPSAD _PPSAD.Byte\r
+#define PPSAD_PPSAD0 _PPSAD.Bits.PPSAD0\r
+#define PPSAD_PPSAD1 _PPSAD.Bits.PPSAD1\r
+#define PPSAD_PPSAD2 _PPSAD.Bits.PPSAD2\r
+#define PPSAD_PPSAD3 _PPSAD.Bits.PPSAD3\r
+#define PPSAD_PPSAD4 _PPSAD.Bits.PPSAD4\r
+#define PPSAD_PPSAD5 _PPSAD.Bits.PPSAD5\r
+#define PPSAD_PPSAD6 _PPSAD.Bits.PPSAD6\r
+#define PPSAD_PPSAD7 _PPSAD.Bits.PPSAD7\r
+#define PPSAD_PPSAD _PPSAD.MergedBits.grpPPSAD\r
+\r
+\r
+/*** BDMSTS - BDM Status Register; 0x0000FF01 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte UNSEC :1; /* Unsecure */\r
+ byte CLKSW :1; /* Clock switch */\r
+ byte TRACE :1; /* TRACE1 BDM firmware command is being executed */\r
+ byte SDV :1; /* Shift data valid */\r
+ byte ENTAG :1; /* Tagging enable */\r
+ byte BDMACT :1; /* BDM active status */\r
+ byte ENBDM :1; /* Enable BDM */\r
+ } Bits;\r
+} BDMSTSSTR;\r
+extern volatile BDMSTSSTR _BDMSTS @(0x0000FF01);\r
+#define BDMSTS _BDMSTS.Byte\r
+#define BDMSTS_UNSEC _BDMSTS.Bits.UNSEC\r
+#define BDMSTS_CLKSW _BDMSTS.Bits.CLKSW\r
+#define BDMSTS_TRACE _BDMSTS.Bits.TRACE\r
+#define BDMSTS_SDV _BDMSTS.Bits.SDV\r
+#define BDMSTS_ENTAG _BDMSTS.Bits.ENTAG\r
+#define BDMSTS_BDMACT _BDMSTS.Bits.BDMACT\r
+#define BDMSTS_ENBDM _BDMSTS.Bits.ENBDM\r
+\r
+\r
+/*** BDMCCR - BDM CCR Holding Register; 0x0000FF06 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte CCR0 :1; /* BDM CCR Holding Bit 0 */\r
+ byte CCR1 :1; /* BDM CCR Holding Bit 1 */\r
+ byte CCR2 :1; /* BDM CCR Holding Bit 2 */\r
+ byte CCR3 :1; /* BDM CCR Holding Bit 3 */\r
+ byte CCR4 :1; /* BDM CCR Holding Bit 4 */\r
+ byte CCR5 :1; /* BDM CCR Holding Bit 5 */\r
+ byte CCR6 :1; /* BDM CCR Holding Bit 6 */\r
+ byte CCR7 :1; /* BDM CCR Holding Bit 7 */\r
+ } Bits;\r
+ struct {\r
+ byte grpCCR :8;\r
+ } MergedBits;\r
+} BDMCCRSTR;\r
+extern volatile BDMCCRSTR _BDMCCR @(0x0000FF06);\r
+#define BDMCCR _BDMCCR.Byte\r
+#define BDMCCR_CCR0 _BDMCCR.Bits.CCR0\r
+#define BDMCCR_CCR1 _BDMCCR.Bits.CCR1\r
+#define BDMCCR_CCR2 _BDMCCR.Bits.CCR2\r
+#define BDMCCR_CCR3 _BDMCCR.Bits.CCR3\r
+#define BDMCCR_CCR4 _BDMCCR.Bits.CCR4\r
+#define BDMCCR_CCR5 _BDMCCR.Bits.CCR5\r
+#define BDMCCR_CCR6 _BDMCCR.Bits.CCR6\r
+#define BDMCCR_CCR7 _BDMCCR.Bits.CCR7\r
+#define BDMCCR_CCR _BDMCCR.MergedBits.grpCCR\r
+\r
+\r
+/*** BDMINR - BDM Internal Register Position Register; 0x0000FF07 ***/\r
+typedef union {\r
+ byte Byte;\r
+ struct {\r
+ byte :1; \r
+ byte :1; \r
+ byte :1; \r
+ byte REG11 :1; /* Internal register map position */\r
+ byte REG12 :1; /* Internal register map position */\r
+ byte REG13 :1; /* Internal register map position */\r
+ byte REG14 :1; /* Internal register map position */\r
+ byte REG15 :1; /* Internal register map position */\r
+ } Bits;\r
+ struct {\r
+ byte :1;\r
+ byte :1;\r
+ byte :1;\r
+ byte grpREG_11 :5;\r
+ } MergedBits;\r
+} BDMINRSTR;\r
+extern volatile BDMINRSTR _BDMINR @(0x0000FF07);\r
+#define BDMINR _BDMINR.Byte\r
+#define BDMINR_REG11 _BDMINR.Bits.REG11\r
+#define BDMINR_REG12 _BDMINR.Bits.REG12\r
+#define BDMINR_REG13 _BDMINR.Bits.REG13\r
+#define BDMINR_REG14 _BDMINR.Bits.REG14\r
+#define BDMINR_REG15 _BDMINR.Bits.REG15\r
+#define BDMINR_REG_11 _BDMINR.MergedBits.grpREG_11\r
+#define BDMINR_REG BDMINR_REG_11\r
+\r
+\r
+ /* Watchdog reset macro */\r
+#ifdef _lint\r
+ #define __RESET_WATCHDOG() /* empty */\r
+#else\r
+ #define __RESET_WATCHDOG() {asm sta COPCTL;} /* Just write a byte to feed the dog */\r
+#endif\r
+\r
+#endif\r
+\r
+/*\r
+** ###################################################################\r
+**\r
+** This file was created by UNIS Processor Expert 03.33 for \r
+** the Motorola HCS12 series of microcontrollers.\r
+**\r
+** ###################################################################\r
+*/\r
+\r
--- /dev/null
+/* ================================================================================================================================= **\r
+** ================================================================================================================================= **\r
+** CONFIGURATION FILE FOR PESL LIBRARY **\r
+** ================================================================================================================================= **\r
+** ================================================================================================================================= */\r
+\r
+#define _MC9S12A128_112 1\r
+#define _MC9S12A128_80 2\r
+#define _MC9S12A256_112 3\r
+#define _MC9S12A256_80 4\r
+#define _MC9S12A64_112 5\r
+#define _MC9S12A64_80 6\r
+#define _MC9S12C32_48 7\r
+#define _MC9S12C32_52 8\r
+#define _MC9S12C32_80 9\r
+#define _MC9S12D64_112 10\r
+#define _MC9S12D64_80 11\r
+#define _MC9S12DB128_112 12\r
+#define _MC9S12DG128_112 13\r
+#define _MC9S12DG128_80 14\r
+#define _MC9S12DG256_112 15\r
+#define _MC9S12DJ128_112 16\r
+#define _MC9S12DJ128_80 17\r
+#define _MC9S12DJ256_112 18\r
+#define _MC9S12DJ256_80 19\r
+#define _MC9S12DJ64_112 20\r
+#define _MC9S12DJ64_80 21\r
+#define _MC9S12DP256_112 22\r
+#define _MC9S12DT128_112 23\r
+#define _MC9S12DT256_112 24\r
+#define _MC9S12A32_80 25\r
+#define _MC9S12D32_80 26\r
+#define _MC9S12DP512_112 27\r
+#define _MC9S12A512_112 28\r
+#define _MC9S12E128_112 29\r
+#define _MC9S12E128_80 30\r
+#define _MC9S12E64_112 31\r
+\r
+\r
+/* Selected target MCU */\r
+\r
+#define CPUtype _MC9S12C32_80\r
+\r
+\r
+/* PESL library */\r
+\r
+#pragma MESSAGE DISABLE C4000 /* WARNING C4000: Condition is always TRUE */\r
+#pragma MESSAGE DISABLE C4001 /* WARNING C4001: Condition is always FALSE */\r
+\r
+#include "PESLlib.h"\r
+\r
+\r
--- /dev/null
+/** ###################################################################\r
+** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.\r
+** Filename : PE_Const.H\r
+** Project : RTOSDemo\r
+** Processor : MC9S12C32CFU\r
+** Beantype : PE_Const\r
+** Version : Driver 01.00\r
+** Compiler : Metrowerks HC12 C Compiler\r
+** Date/Time : 10/05/2005, 11:11\r
+** Abstract :\r
+** This bean "PE_Const" contains internal definitions\r
+** of the constants.\r
+** Settings :\r
+** Contents :\r
+** No public methods\r
+**\r
+** (c) Copyright UNIS, spol. s r.o. 1997-2002\r
+** UNIS, spol. s r.o.\r
+** Jundrovska 33\r
+** 624 00 Brno\r
+** Czech Republic\r
+** http : www.processorexpert.com\r
+** mail : info@processorexpert.com\r
+** ###################################################################*/\r
+\r
+#ifndef __PE_Const_H\r
+#define __PE_Const_H\r
+\r
+/* Constants for detecting running mode */\r
+#define HIGH_SPEED 0 /* High speed */\r
+#define LOW_SPEED 1 /* Low speed */\r
+#define SLOW_SPEED 2 /* Slow speed */\r
+\r
+/* Reset cause constants */\r
+#define RSTSRC_POR 1 /* Power-on reset */\r
+#define RSTSRC_PIN 8 /* External reset bit */\r
+#define RSTSRC_COP 4 /* COP reset */\r
+#define RSTSRC_ILOP 2 /* Illegal opcode reset */\r
+#define RSTSRC_ILAD 16 /* Illegal address reset */\r
+#define RSTSRC_LVI 32 /* Low voltage inhibit reset */\r
+\r
+#endif /* _PE_Const_H */\r
+/*\r
+** ###################################################################\r
+**\r
+** This file was created by UNIS Processor Expert 03.33 for \r
+** the Motorola HCS12 series of microcontrollers.\r
+**\r
+** ###################################################################\r
+*/\r
--- /dev/null
+/** ###################################################################\r
+** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.\r
+** Filename : PE_Error.H\r
+** Project : RTOSDemo\r
+** Processor : MC9S12C32CFU\r
+** Beantype : PE_Error\r
+** Version : Driver 01.00\r
+** Compiler : Metrowerks HC12 C Compiler\r
+** Date/Time : 10/05/2005, 11:11\r
+** Abstract :\r
+** This bean "PE_Error" contains internal definitions\r
+** of the error constants.\r
+** Settings :\r
+** Contents :\r
+** No public methods\r
+**\r
+** (c) Copyright UNIS, spol. s r.o. 1997-2002\r
+** UNIS, spol. s r.o.\r
+** Jundrovska 33\r
+** 624 00 Brno\r
+** Czech Republic\r
+** http : www.processorexpert.com\r
+** mail : info@processorexpert.com\r
+** ###################################################################*/\r
+\r
+#ifndef __PE_Error_H\r
+#define __PE_Error_H\r
+\r
+#define ERR_OK 0 /* OK */\r
+#define ERR_SPEED 1 /* This device does not work in the active speed mode. */\r
+#define ERR_RANGE 2 /* Parameter out of range. */\r
+#define ERR_VALUE 3 /* Parameter of incorrect value. */\r
+#define ERR_OVERFLOW 4 /* Timer overflow. */\r
+#define ERR_MATH 5 /* Overflow during evaluation. */\r
+#define ERR_ENABLED 6 /* Device is enabled. */\r
+#define ERR_DISABLED 7 /* Device is disabled. */\r
+#define ERR_BUSY 8 /* Device is busy. */\r
+#define ERR_NOTAVAIL 9 /* Requested value or method not available. */\r
+#define ERR_RXEMPTY 10 /* No data in receiver. */\r
+#define ERR_TXFULL 11 /* Transmitter is full. */\r
+#define ERR_BUSOFF 12 /* Bus not available. */\r
+#define ERR_OVERRUN 13 /* Overrun error is detected. */\r
+#define ERR_FRAMING 14 /* Framing error is detected. */\r
+#define ERR_PARITY 15 /* Parity error is detected. */\r
+#define ERR_NOISE 16 /* Noise error is detected. */\r
+#define ERR_IDLE 17 /* Idle error is detectes. */\r
+#define ERR_FAULT 18 /* Fault error is detected. */\r
+#define ERR_BREAK 19 /* Break char is received during communication. */\r
+#define ERR_CRC 20 /* CRC error is detected. */\r
+#define ERR_ARBITR 21 /* A node losts arbitration. This error occurs if two nodes start transmission at the same time. */\r
+#define ERR_PROTECT 22 /* Protection error is detected. */\r
+\r
+#endif __PE_Error_H\r
--- /dev/null
+/** ###################################################################\r
+** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.\r
+** Filename : PE_Timer.C\r
+** Project : RTOSDemo\r
+** Processor : MC9S12C32CFU\r
+** Beantype : PE_Timer\r
+** Version : Driver 01.00\r
+** Compiler : Metrowerks HC12 C Compiler\r
+** Date/Time : 17/05/2005, 08:44\r
+** Abstract :\r
+** This bean "PE_Timer" implements internal methods and definitions\r
+** used by beans working with timers.\r
+** Settings :\r
+** Contents :\r
+** No public methods\r
+**\r
+** (c) Copyright UNIS, spol. s r.o. 1997-2002\r
+** UNIS, spol. s r.o.\r
+** Jundrovska 33\r
+** 624 00 Brno\r
+** Czech Republic\r
+** http : www.processorexpert.com\r
+** mail : info@processorexpert.com\r
+** ###################################################################*/\r
+\r
+\r
+/* MODULE PE_Timer. */\r
+\r
+#include "PE_Timer.h"\r
+\r
+\r
+/*\r
+** ===================================================================\r
+** Method : PE_Timer_LngHi1 (bean PE_Timer)\r
+**\r
+** Description :\r
+** This method is internal. It is used by Processor Expert\r
+** only.\r
+** ===================================================================\r
+*/\r
+bool PE_Timer_LngHi1(dword High, dword Low, word *Out) \r
+{\r
+ if ((High == 0) && ((Low >> 24) == 0)) \r
+ if ((Low & 0x80) != 0) {\r
+ if ((Low >> 8) < 0xFFFF) {\r
+ *Out = ((unsigned int)(Low >> 8))+1;\r
+ return FALSE;\r
+ } \r
+ } \r
+ else {\r
+ *Out = (unsigned int)(Low >> 8);\r
+ return FALSE;\r
+ } \r
+ *Out = (unsigned int)(Low >> 8);\r
+ return TRUE;\r
+}\r
+\r
+\r
+\r
+/* END PE_Timer. */\r
+\r
+/*\r
+** ###################################################################\r
+**\r
+** This file was created by UNIS Processor Expert 03.33 for \r
+** the Motorola HCS12 series of microcontrollers.\r
+**\r
+** ###################################################################\r
+*/\r
--- /dev/null
+/** ###################################################################\r
+** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.\r
+** Filename : PE_Timer.H\r
+** Project : RTOSDemo\r
+** Processor : MC9S12C32CFU\r
+** Beantype : PE_Timer\r
+** Version : Driver 01.00\r
+** Compiler : Metrowerks HC12 C Compiler\r
+** Date/Time : 17/05/2005, 08:44\r
+** Abstract :\r
+** This bean "PE_Timer" implements internal methods and definitions\r
+** used by beans working with timers.\r
+** Settings :\r
+** Contents :\r
+** No public methods\r
+**\r
+** (c) Copyright UNIS, spol. s r.o. 1997-2002\r
+** UNIS, spol. s r.o.\r
+** Jundrovska 33\r
+** 624 00 Brno\r
+** Czech Republic\r
+** http : www.processorexpert.com\r
+** mail : info@processorexpert.com\r
+** ###################################################################*/\r
+#ifndef __PE_Timer\r
+#define __PE_Timer\r
+/*Include shared modules, which are used for whole project*/\r
+#include "PE_types.h"\r
+#include "PE_const.h"\r
+\r
+/* MODULE PE_Timer. */\r
+\r
+bool PE_Timer_LngHi1(dword Low, dword High, word *Out);\r
+/*\r
+** ===================================================================\r
+** Method : PE_Timer_LngHi1 (bean PE_Timer)\r
+**\r
+** Description :\r
+** This method is internal. It is used by Processor Expert\r
+** only.\r
+** ===================================================================\r
+*/\r
+\r
+\r
+#endif /* END PE_Timer. */\r
+/*\r
+** ###################################################################\r
+**\r
+** This file was created by UNIS Processor Expert 03.33 for \r
+** the Motorola HCS12 series of microcontrollers.\r
+**\r
+** ###################################################################\r
+*/\r
--- /dev/null
+/** ###################################################################\r
+** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.\r
+** Filename : PE_Types.H\r
+** Project : RTOSDemo\r
+** Processor : MC9S12C32CFU\r
+** Beantype : PE_Types\r
+** Version : Driver 01.04\r
+** Compiler : Metrowerks HC12 C Compiler\r
+** Date/Time : 10/05/2005, 11:11\r
+** Abstract :\r
+** This bean "PE_Types" contains internal definitions\r
+** of the types.\r
+** Settings :\r
+** Contents :\r
+** No public methods\r
+**\r
+** (c) Copyright UNIS, spol. s r.o. 1997-2002\r
+** UNIS, spol. s r.o.\r
+** Jundrovska 33\r
+** 624 00 Brno\r
+** Czech Republic\r
+** http : www.processorexpert.com\r
+** mail : info@processorexpert.com\r
+** ###################################################################*/\r
+\r
+#ifndef __PE_Types_H\r
+#define __PE_Types_H\r
+\r
+#define FALSE 0\r
+#define TRUE 1\r
+\r
+/*Types definition*/\r
+typedef unsigned char bool;\r
+typedef unsigned char byte;\r
+typedef unsigned int word;\r
+typedef unsigned long dword;\r
+typedef unsigned long dlong[2];\r
+typedef void (*tIntFunc)(void);\r
+\r
+/* Motorola types */\r
+typedef unsigned char VUINT8;\r
+typedef signed char VINT8;\r
+typedef unsigned short int VUINT16;\r
+typedef signed short int VINT16;\r
+typedef unsigned long int VUINT32;\r
+\r
+#define in16(var,l,h) var = ((word)(l)) | (((word)(h)) << 8)\r
+#define out16(l,h,val) { l = (byte)val; h = (byte)(val >> 8); }\r
+\r
+#define output(P, V) P = (V)\r
+#define input(P) (P)\r
+\r
+#define __DI() { asm sei; } /* Disable global interrupts */\r
+#define __EI() { asm cli; } /* Enable global interrupts */\r
+#define EnterCritical() { __asm pshc; __asm sei; __asm movb 1,SP+,CCR_reg; } /* This macro is used by Processor Expert. It saves CCR register and disable global interrupts. */\r
+#define ExitCritical() { __asm movb CCR_reg, 1,-SP; __asm pulc; } /* This macro is used by Processor Expert. It restores CCR register saved in SaveStatusReg(). */\r
+/* obsolete definition for backward compatibility */\r
+#define SaveStatusReg() EnterCritical()\r
+#define RestoreStatusReg() ExitCritical()\r
+\r
+\r
+typedef struct { /* Black&White Image */\r
+ word width; /* Image width */\r
+ word height; /* Image height */\r
+ byte *pixmap; /* Image pixel bitmap */\r
+ word size; /* Image size */\r
+ char *name; /* Image name */\r
+} TIMAGE;\r
+typedef TIMAGE* PIMAGE ; /* Pointer to image */\r
+\r
+/* 16-bit register (Motorola format - big endian) */\r
+typedef union {\r
+ word w;\r
+ struct {\r
+ byte high,low;\r
+ } b;\r
+} TWREG;\r
+\r
+#endif /* __PE_Types_H */\r
+/*\r
+** ###################################################################\r
+**\r
+** This file was created by UNIS Processor Expert 03.33 for \r
+** the Motorola HCS12 series of microcontrollers.\r
+**\r
+** ###################################################################\r
+*/\r
--- /dev/null
+/** ###################################################################\r
+** Filename : RTOSDemo.C\r
+** Project : RTOSDemo\r
+** Processor : MC9S12C32CFU\r
+** Version : Driver 01.05\r
+** Compiler : Metrowerks HC12 C Compiler\r
+** Date/Time : 10/05/2005, 11:11\r
+** Abstract :\r
+** Main module. \r
+** Here is to be placed user's code.\r
+** Settings :\r
+** Contents :\r
+** No public methods\r
+**\r
+** (c) Copyright UNIS, spol. s r.o. 1997-2002\r
+** UNIS, spol. s r.o.\r
+** Jundrovska 33\r
+** 624 00 Brno\r
+** Czech Republic\r
+** http : www.processorexpert.com\r
+** mail : info@processorexpert.com\r
+** ###################################################################*/\r
+/* MODULE RTOSDemo */\r
+\r
+/* Including used modules for compilling procedure */\r
+#include "Cpu.h"\r
+#include "Events.h"\r
+#include "Byte1.h"\r
+#include "TickTimer.h"\r
+#include "ButtonInterrupt.h"\r
+/* Include shared modules, which are used for whole project */\r
+#include "PE_Types.h"\r
+#include "PE_Error.h"\r
+#include "PE_Const.h"\r
+#include "IO_Map.h"\r
+\r
+extern void vMain( void );\r
+\r
+void main(void)\r
+{\r
+ /*** Processor Expert internal initialization. DON'T REMOVE THIS CODE!!! ***/\r
+ PE_low_level_init();\r
+ /*** End of Processor Expert internal initialization. ***/\r
+\r
+ /*Write your code here*/\r
+ \r
+ /* Just jump to the real main(). */\r
+ __asm\r
+ {\r
+ jmp vMain\r
+ }\r
+ \r
+ /*** Processor Expert end of main routine. DON'T MODIFY THIS CODE!!! ***/\r
+ for(;;);\r
+ /*** Processor Expert end of main routine. DON'T WRITE CODE BELOW!!! ***/\r
+} /*** End of main routine. DO NOT MODIFY THIS TEXT!!! ***/\r
+\r
+/* END RTOSDemo */\r
+/*\r
+** ###################################################################\r
+**\r
+** This file was created by UNIS Processor Expert 03.33 for \r
+** the Motorola HCS12 series of microcontrollers.\r
+**\r
+** ###################################################################\r
+*/\r
--- /dev/null
+/*\r
+** ###################################################################\r
+** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.\r
+** Filename : RTOSDemo.PRM\r
+** Project : RTOSDemo\r
+** Processor : MC9S12C32CFU\r
+** Compiler : Metrowerks HC12 C Compiler\r
+** Date/Time : 18/06/2005, 18:00\r
+** Abstract :\r
+** This file is used by the linker. It describes files to be linked,\r
+** memory ranges, stack size, etc. For detailed description of the PRM file\r
+** see CodeWarrior documentation. This file is generated by default.\r
+** You can switch off generation by setting the property\r
+** "Generate PRM file = no" on the "Build options" tab in CPU bean and then modify\r
+** this file if needed.\r
+**\r
+** (c) Copyright UNIS, spol. s r.o. 1997-2002\r
+** UNIS, spol. s r.o.\r
+** Jundrovska 33\r
+** 624 00 Brno\r
+** Czech Republic\r
+** http : www.processorexpert.com\r
+** mail : info@processorexpert.com\r
+** ###################################################################\r
+*/\r
+\r
+NAMES\r
+\r
+END\r
+\r
+SECTIONS\r
+ /* List of all sections specified on the "Build options" tab */\r
+ RAM = READ_WRITE 0x00000800 TO 0x00000FFF;\r
+ ROM_C000 = READ_ONLY 0x0000C000 TO 0x0000FF7F;\r
+ ROM_4000 = READ_ONLY 0x00004000 TO 0x00007FFF;\r
+END\r
+\r
+PLACEMENT\r
+ DEFAULT_RAM INTO RAM;\r
+ _PRESTART, STARTUP,\r
+ ROM_VAR, STRINGS,\r
+ NON_BANKED, DEFAULT_ROM, COPY INTO ROM_C000, ROM_4000;\r
+END\r
+\r
+INIT _EntryPoint /* The entry point of the application. This function is generated into the CPU module. */\r
+\r
+STACKSIZE 0x0030 /* Size of the system stack. Value can be changed on the "Build options" tab */\r
+\r
--- /dev/null
+/** ###################################################################\r
+** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.\r
+** Filename : TickTimer.C\r
+** Project : RTOSDemo\r
+** Processor : MC9S12C32CFU\r
+** Beantype : TimerInt\r
+** Version : Bean 02.063, Driver 01.05, CPU db: 2.87.276\r
+** Compiler : Metrowerks HC12 C Compiler\r
+** Date/Time : 18/06/2005, 17:53\r
+** Abstract :\r
+** This bean "TimerInt" implements a periodic interrupt.\r
+** When the bean and its events are enabled, the "OnInterrupt"\r
+** event is called periodically with the period that you specify.\r
+** TimerInt supports also changing the period in runtime.\r
+** The source of periodic interrupt can be timer compare or reload \r
+** register or timer-overflow interrupt (of free running counter).\r
+** Settings :\r
+** Timer name : TIM (16-bit)\r
+** Compare name : TC0\r
+** Counter shared : No\r
+**\r
+** High-speed CPU mode\r
+** Prescaler : divide-by-4\r
+** Clock : 5999000 Hz\r
+** Initial period/frequency\r
+** Xtal ticks : 16000\r
+** microseconds : 1000\r
+** milliseconds : 1\r
+** seconds (real) : 0.0010000\r
+** Hz : 1000\r
+** kHz : 1\r
+**\r
+** Runtime setting : period/frequency interval (continual setting)\r
+** ticks : 16000 to 160000 ticks\r
+** microseconds : 1000 to 10000 microseconds\r
+** milliseconds : 1 to 10 milliseconds\r
+** seconds (real) : 0.0010000 to 0.0100000 seconds\r
+** Hz : 100 to 1000 Hz\r
+**\r
+** Initialization:\r
+** Timer : Disabled\r
+** Events : Enabled\r
+**\r
+** Timer registers\r
+** Counter : TCNT [68]\r
+** Mode : TIOS [64]\r
+** Run : TSCR1 [70]\r
+** Prescaler : TSCR2 [77]\r
+**\r
+** Compare registers\r
+** Compare : TC0 [80]\r
+**\r
+** Flip-flop registers\r
+** Mode : TCTL2 [73]\r
+** Contents :\r
+** Enable - byte TickTimer_Enable(void);\r
+** SetFreqHz - byte TickTimer_SetFreqHz(word Freq);\r
+**\r
+** (c) Copyright UNIS, spol. s r.o. 1997-2002\r
+** UNIS, spol. s r.o.\r
+** Jundrovska 33\r
+** 624 00 Brno\r
+** Czech Republic\r
+** http : www.processorexpert.com\r
+** mail : info@processorexpert.com\r
+** ###################################################################*/\r
+\r
+\r
+/* MODULE TickTimer. */\r
+\r
+#include "Events.h"\r
+#include "TickTimer.h"\r
+\r
+/* Definition of DATA and CODE segments for this bean. User can specify where\r
+ these segments will be located on "Build options" tab of the selected CPU bean. */\r
+#pragma DATA_SEG TickTimer_DATA /* Data section for this module. */\r
+#pragma CODE_SEG TickTimer_CODE /* Code section for this module. */\r
+\r
+static bool EnUser; /* Enable/Disable device by user */\r
+static word CmpHighVal; /* Compare register value for high speed CPU mode */\r
+\r
+\r
+/*\r
+** ===================================================================\r
+** Method : SetCV (bean TimerInt)\r
+**\r
+** Description :\r
+** This method is internal. It is used by Processor Expert\r
+** only.\r
+** ===================================================================\r
+*/\r
+static void SetCV(word Val)\r
+{\r
+ if (Val == 0) /* If the given value is zero */\r
+ Val = 65535; /* then change it to the maximal one */\r
+ TC0 = Val; /* Store given value to the compare register */\r
+ TC7 = Val; /* Store given value to the modulo register */\r
+}\r
+\r
+/*\r
+** ===================================================================\r
+** Method : SetPV (bean TimerInt)\r
+**\r
+** Description :\r
+** This method is internal. It is used by Processor Expert\r
+** only.\r
+** ===================================================================\r
+*/\r
+static void SetPV(byte Val)\r
+{\r
+ TSCR2_PR = Val; /* Store given value to the prescaler */\r
+}\r
+\r
+/*\r
+** ===================================================================\r
+** Method : HWEnDi (bean TimerInt)\r
+**\r
+** Description :\r
+** This method is internal. It is used by Processor Expert\r
+** only.\r
+** ===================================================================\r
+*/\r
+static void HWEnDi(void)\r
+{\r
+ if (EnUser) { /* Enable device? */\r
+ TFLG1 = 1; /* Reset interrupt request flag */\r
+ TIE_C0I = 1; /* Enable interrupt */\r
+ }\r
+ else { /* Disable device? */\r
+ TIE_C0I = 0; /* Disable interrupt */\r
+ }\r
+}\r
+\r
+/*\r
+** ===================================================================\r
+** Method : TickTimer_Enable (bean TimerInt)\r
+**\r
+** Description :\r
+** Enable the bean - it starts the timer. Events may be\r
+** generated ("DisableEvent"/"EnableEvent").\r
+** Parameters : None\r
+** Returns :\r
+** --- - Error code, possible codes:\r
+** ERR_OK - OK\r
+** ERR_SPEED - This device does not work in\r
+** the active speed mode\r
+** ===================================================================\r
+*/\r
+byte TickTimer_Enable(void)\r
+{\r
+ if (!EnUser) { /* Is the device disabled by user? */\r
+ EnUser = TRUE; /* If yes then set the flag "device enabled" */\r
+ HWEnDi(); /* Enable the device */\r
+ }\r
+ return ERR_OK; /* OK */\r
+}\r
+\r
+/*\r
+** ===================================================================\r
+** Method : TickTimer_SetFreqHz (bean TimerInt)\r
+**\r
+** Description :\r
+** This method sets the new frequency of the generated\r
+** events. The frequency is expressed in Hz as a 16-bit\r
+** unsigned integer number.\r
+** This method is available only if runtime setting type\r
+** 'from interval' is selected in the Timing dialog box in\r
+** Runtime setting area.\r
+** Parameters :\r
+** NAME - DESCRIPTION\r
+** Freq - Frequency to set [in Hz]\r
+** (100 to 1000 Hz)\r
+** Returns :\r
+** --- - Error code, possible codes:\r
+** ERR_OK - OK\r
+** ERR_SPEED - This device does not work in\r
+** the active speed mode\r
+** ERR_MATH - Overflow during evaluation\r
+** ERR_RANGE - Parameter out of range\r
+** ===================================================================\r
+*/\r
+byte TickTimer_SetFreqHz(word Freq)\r
+{\r
+ dlong rtval; /* Result of two 32-bit numbers division */\r
+ word rtword; /* Result of 64-bit number division */\r
+\r
+ if ((Freq > 1000) || (Freq < 100)) /* Is the given value out of range? */\r
+ return ERR_RANGE; /* If yes then error */\r
+ rtval[1] = 1535744000 / (dword)Freq; /* Divide high speed CPU mode coefficient by the given value */\r
+ rtval[0] = 0; /* Convert result to the type dlong */\r
+ if (PE_Timer_LngHi1(rtval[0],rtval[1],&rtword)) /* Is the result greater or equal than 65536 ? */\r
+ rtword = 65535; /* If yes then use maximal possible value */\r
+ CmpHighVal = rtword; /* Store result (compare register value for high speed CPU mode) to the variable CmpHighVal */\r
+ SetCV(CmpHighVal); /* Store appropriate value to the compare register according to the selected high speed CPU mode */\r
+ return ERR_OK; /* OK */\r
+}\r
+\r
+/*\r
+** ===================================================================\r
+** Method : TickTimer_Init (bean TimerInt)\r
+**\r
+** Description :\r
+** This method is internal. It is used by Processor Expert\r
+** only.\r
+** ===================================================================\r
+*/\r
+void TickTimer_Init(void)\r
+{\r
+ CmpHighVal = 5999; /* Compare register value for high speed CPU mode */\r
+ EnUser = FALSE; /* Disable device */\r
+ SetCV(CmpHighVal); /* Store appropriate value to the compare register according to the selected high speed CPU mode */\r
+ SetPV(2); /* Set prescaler register according to the selected high speed CPU mode */\r
+ HWEnDi(); /* Enable/disable device according to status flags */\r
+}\r
+\r
+/*\r
+** ===================================================================\r
+** Method : TickTimer_Interrupt (bean TimerInt)\r
+**\r
+** Description :\r
+** This method is internal. It is used by Processor Expert\r
+** only.\r
+** ===================================================================\r
+*/\r
+#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */\r
+__interrupt void TickTimer_Interrupt(void)\r
+{\r
+ TFLG1 = 1; /* Reset interrupt request flag */\r
+ vTaskTickInterrupt(); /* Invoke user event */\r
+}\r
+\r
+#pragma CODE_SEG TickTimer_CODE /* Code section for this module. */\r
+\r
+/* END TickTimer. */\r
+\r
+/*\r
+** ###################################################################\r
+**\r
+** This file was created by UNIS Processor Expert 03.33 for \r
+** the Motorola HCS12 series of microcontrollers.\r
+**\r
+** ###################################################################\r
+*/\r
--- /dev/null
+/** ###################################################################\r
+** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.\r
+** Filename : TickTimer.H\r
+** Project : RTOSDemo\r
+** Processor : MC9S12C32CFU\r
+** Beantype : TimerInt\r
+** Version : Bean 02.063, Driver 01.05, CPU db: 2.87.276\r
+** Compiler : Metrowerks HC12 C Compiler\r
+** Date/Time : 18/06/2005, 17:53\r
+** Abstract :\r
+** This bean "TimerInt" implements a periodic interrupt.\r
+** When the bean and its events are enabled, the "OnInterrupt"\r
+** event is called periodically with the period that you specify.\r
+** TimerInt supports also changing the period in runtime.\r
+** The source of periodic interrupt can be timer compare or reload \r
+** register or timer-overflow interrupt (of free running counter).\r
+** Settings :\r
+** Timer name : TIM (16-bit)\r
+** Compare name : TC0\r
+** Counter shared : No\r
+**\r
+** High-speed CPU mode\r
+** Prescaler : divide-by-4\r
+** Clock : 5999000 Hz\r
+** Initial period/frequency\r
+** Xtal ticks : 16000\r
+** microseconds : 1000\r
+** milliseconds : 1\r
+** seconds (real) : 0.0010000\r
+** Hz : 1000\r
+** kHz : 1\r
+**\r
+** Runtime setting : period/frequency interval (continual setting)\r
+** ticks : 16000 to 160000 ticks\r
+** microseconds : 1000 to 10000 microseconds\r
+** milliseconds : 1 to 10 milliseconds\r
+** seconds (real) : 0.0010000 to 0.0100000 seconds\r
+** Hz : 100 to 1000 Hz\r
+**\r
+** Initialization:\r
+** Timer : Disabled\r
+** Events : Enabled\r
+**\r
+** Timer registers\r
+** Counter : TCNT [68]\r
+** Mode : TIOS [64]\r
+** Run : TSCR1 [70]\r
+** Prescaler : TSCR2 [77]\r
+**\r
+** Compare registers\r
+** Compare : TC0 [80]\r
+**\r
+** Flip-flop registers\r
+** Mode : TCTL2 [73]\r
+** Contents :\r
+** Enable - byte TickTimer_Enable(void);\r
+** SetFreqHz - byte TickTimer_SetFreqHz(word Freq);\r
+**\r
+** (c) Copyright UNIS, spol. s r.o. 1997-2002\r
+** UNIS, spol. s r.o.\r
+** Jundrovska 33\r
+** 624 00 Brno\r
+** Czech Republic\r
+** http : www.processorexpert.com\r
+** mail : info@processorexpert.com\r
+** ###################################################################*/\r
+\r
+#ifndef __TickTimer\r
+#define __TickTimer\r
+\r
+/* MODULE TickTimer. */\r
+\r
+#include "Cpu.h"\r
+\r
+#pragma CODE_SEG TickTimer_CODE /* Code section for this module. */\r
+\r
+#define TickTimer_SFHzMin 100 /* Lower bound of interval for method SetFreqHz */\r
+#define TickTimer_SFHzMax 1000 /* Upper bound of interval for method SetFreqHz */\r
+\r
+\r
+byte TickTimer_Enable(void);\r
+/*\r
+** ===================================================================\r
+** Method : TickTimer_Enable (bean TimerInt)\r
+**\r
+** Description :\r
+** Enable the bean - it starts the timer. Events may be\r
+** generated ("DisableEvent"/"EnableEvent").\r
+** Parameters : None\r
+** Returns :\r
+** --- - Error code, possible codes:\r
+** ERR_OK - OK\r
+** ERR_SPEED - This device does not work in\r
+** the active speed mode\r
+** ===================================================================\r
+*/\r
+\r
+byte TickTimer_SetFreqHz(word Freq);\r
+/*\r
+** ===================================================================\r
+** Method : TickTimer_SetFreqHz (bean TimerInt)\r
+**\r
+** Description :\r
+** This method sets the new frequency of the generated\r
+** events. The frequency is expressed in Hz as a 16-bit\r
+** unsigned integer number.\r
+** This method is available only if runtime setting type\r
+** 'from interval' is selected in the Timing dialog box in\r
+** Runtime setting area.\r
+** Parameters :\r
+** NAME - DESCRIPTION\r
+** Freq - Frequency to set [in Hz]\r
+** (100 to 1000 Hz)\r
+** Returns :\r
+** --- - Error code, possible codes:\r
+** ERR_OK - OK\r
+** ERR_SPEED - This device does not work in\r
+** the active speed mode\r
+** ERR_MATH - Overflow during evaluation\r
+** ERR_RANGE - Parameter out of range\r
+** ===================================================================\r
+*/\r
+\r
+#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */\r
+__interrupt void TickTimer_Interrupt(void);\r
+#pragma CODE_SEG TickTimer_CODE /* Code section for this module. */\r
+/*\r
+** ===================================================================\r
+** Method : TickTimer_Interrupt (bean TimerInt)\r
+**\r
+** Description :\r
+** This method is internal. It is used by Processor Expert\r
+** only.\r
+** ===================================================================\r
+*/\r
+\r
+void TickTimer_Init(void);\r
+/*\r
+** ===================================================================\r
+** Method : TickTimer_Init (bean TimerInt)\r
+**\r
+** Description :\r
+** This method is internal. It is used by Processor Expert\r
+** only.\r
+** ===================================================================\r
+*/\r
+\r
+#pragma CODE_SEG DEFAULT /* Change code section to DEFAULT. */\r
+\r
+/* END TickTimer. */\r
+\r
+#endif /* ifndef __TickTimer */\r
+/*\r
+** ###################################################################\r
+**\r
+** This file was created by UNIS Processor Expert 03.33 for \r
+** the Motorola HCS12 series of microcontrollers.\r
+**\r
+** ###################################################################\r
+*/\r
--- /dev/null
+/** ###################################################################\r
+** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.\r
+** Filename : Cpu.C\r
+** Project : RTOSDemo\r
+** Processor : MC9S12C32CFU\r
+** Beantype : MC9S12C32_80\r
+** Version : Bean 01.002, Driver 01.09, CPU db: 2.87.276\r
+** Compiler : Metrowerks HC12 C Compiler\r
+** Date/Time : 17/05/2005, 18:22\r
+** Abstract :\r
+** This bean "MC9S12C32_80" implements properties, methods,\r
+** and events of the CPU.\r
+** Settings :\r
+**\r
+** Contents :\r
+** EnableInt - void Cpu_EnableInt(void);\r
+** DisableInt - void Cpu_DisableInt(void);\r
+** SetWaitMode - void Cpu_SetWaitMode(void);\r
+** SetStopMode - void Cpu_SetStopMode(void);\r
+**\r
+** (c) Copyright UNIS, spol. s r.o. 1997-2002\r
+** UNIS, spol. s r.o.\r
+** Jundrovska 33\r
+** 624 00 Brno\r
+** Czech Republic\r
+** http : www.processorexpert.com\r
+** mail : info@processorexpert.com\r
+** ###################################################################*/\r
+\r
+\r
+#include "Cpu.h"\r
+#include "Byte1.h"\r
+#include "TickTimer.h"\r
+#include "ButtonInterrupt.h"\r
+\r
+extern void near _EntryPoint(void); /* Startup routine */\r
+extern void near vPortTickInterrupt( void );\r
+extern void near vPortYield( void );\r
+extern void near vButtonPush( void );\r
+\r
+typedef void (*near tIsrFunc)(void);\r
+const tIsrFunc _vect[] @0xFF80 = { /* Interrupt table */\r
+ Cpu_Interrupt, /* 0 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 1 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 2 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 3 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 4 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 5 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 6 Default (unused) interrupt */\r
+ vButtonPush, /* 7 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 8 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 9 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 10 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 11 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 12 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 13 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 14 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 15 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 16 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 17 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 18 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 19 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 20 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 21 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 22 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 23 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 24 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 25 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 26 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 27 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 28 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 29 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 30 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 31 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 32 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 33 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 34 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 35 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 36 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 37 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 38 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 39 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 40 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 41 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 42 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 43 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 44 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 45 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 46 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 47 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 48 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 49 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 50 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 51 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 52 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 53 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 54 Default (unused) interrupt */\r
+ vPortTickInterrupt,\r
+ Cpu_Interrupt, /* 56 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 57 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 58 Default (unused) interrupt */\r
+ vPortYield, /* 59 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 60 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 61 Default (unused) interrupt */\r
+ Cpu_Interrupt, /* 62 Default (unused) interrupt */\r
+ _EntryPoint /* Reset vector */\r
+ };\r
+/*\r
+** ###################################################################\r
+**\r
+** This file was created by UNIS Processor Expert 03.33 for \r
+** the Motorola HCS12 series of microcontrollers.\r
+**\r
+** ###################################################################\r
+*/
\ No newline at end of file
--- /dev/null
+OPEN source 0 0 60 39\r
+Source < attributes MARKS off\r
+OPEN assembly 60 0 40 31\r
+Assembly < attributes ADR on,CODE off,ABSADR on,SYMB off,TOPPC 0xF88C\r
+OPEN procedure 0 39 60 17\r
+Procedure < attributes VALUES on,TYPES off\r
+OPEN register 60 31 40 25\r
+Register < attributes FORMAT AUTO,COMPLEMENT None\r
+OPEN memory 60 56 40 22\r
+Memory < attributes FORMAT hex,COMPLEMENT None,WORD 1,ASC on,ADR on,ADDRESS 0x80\r
+OPEN data 0 56 60 22\r
+Data:1 < attributes SCOPE global,COMPLEMENT None,FORMAT Symb,MODE automatic,UPDATERATE 10,NAMEWIDTH 16\r
+OPEN data 0 78 60 22\r
+Data:2 < attributes SCOPE local,COMPLEMENT None,FORMAT Symb,MODE automatic,UPDATERATE 10,NAMEWIDTH 16\r
+OPEN command 60 78 40 22\r
+Command < attributes CACHESIZE 1000\r
+bckcolor 50331647\r
+font 'Courier New' 9 BLACK\r
+AUTOSIZE on\r
+ACTIVATE Data:2 Command Procedure Data:1 Source Register Assembly Memory\r
--- /dev/null
+=================================================================\r
+This file was generated from Processor Expert 03.33\r
+ project "RTOSDemo", 18/06/2005, 18:00\r
+-----------------------------------------------------------------\r
+There is no signal defined in this project.\r
+ Hint: Signals may be defined in the Bean Inspector (advanced or expert view)\r
+=================================================================\r
+\r
+=================================================================\r
+ SIGNAL LIST\r
+-----------------------------------------------------------------\r
+ SIGNAL NAME => PIN NAME\r
+-----------------------------------------------------------------\r
+=================================================================\r
+\r
+\r
+=================================================================\r
+ PIN LIST\r
+-----------------------------------------------------------------\r
+ PIN NAME => SIGNAL NAME\r
+-----------------------------------------------------------------\r
+=================================================================\r
+\r
--- /dev/null
+=============================================================================\r
+List of methods in project: RTOSDemo\r
+\r
+THIS TEXT DESCRIPTION IS GENERATED BY THE TOOL. DO NOT MODIFY IT.\r
+=============================================================================\r
+\r
+Module "Byte1" (bean ByteIO)\r
+ Byte1_PutBit -Put the specified value to the specified bit/pin of the Input/Output bean. If direction is [input] saves the \r
+ value to a memory or a register, this value will be written to the pin after switching to the output mode - \r
+ using [SetDir(TRUE)]. If direction is [output] writes the value to the pin.\r
+ Byte1_NegBit -Negate (invert) the specified bit of the Input/Output bean. It is the same as [PutBit(Bit,!GetBit(Bit))].\r
+\r
+Module "TickTimer" (bean TimerInt)\r
+ TickTimer_Enable -Enable the bean - it starts the timer. Events may be generated ("DisableEvent"/"EnableEvent").\r
+ TickTimer_SetFreqHz -This method sets the new frequency of the generated events. The frequency is expressed in [Hz] as a \r
+ 16-bit unsigned integer number. This method is available only if runtime setting type 'from interval' is \r
+ selected in the <Timing dialog box> in Runtime setting area.\r
+\r
+Module "ButtonInterrupt" (bean ExtInt)\r
+ ButtonInterrupt_Enable -Enable the bean - the external events are accepted.\r
+\r
+Module "Cpu" (bean MC9S12C32_80)\r
+ Cpu_EnableInt -Enable maskable interrupts\r
+ Cpu_DisableInt -Disable maskable interrupts\r
+ Cpu_SetWaitMode -Set low power mode - Wait mode.\r
+For more information about the wait mode see documentation of this CPU.\r
+ \r
+Release from Wait mode: Reset or interrupt\r
+ Cpu_SetStopMode -Set low power mode - Stop mode.\r
+For more information about the stop mode see documentation of this CPU.\r
+\r
+=============================================================================\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+#include <hidef.h> /* common defines and macros */\r
+#include "TickTimer.h"\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. \r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 1\r
+#define configUSE_TICK_HOOK 0\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 4 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 70 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 2048 - 256 ) )\r
+#define configMAX_TASK_NAME_LEN ( 1 )\r
+#define configUSE_TRACE_FACILITY 0\r
+#define configUSE_16_BIT_TICKS 1\r
+#define configIDLE_SHOULD_YIELD 1\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* This parameter is normally required in order to set the RTOS tick timer.\r
+This port is a bit different in that hardware setup uses the code generated by \r
+the Processor Expert, making this definition obsolete.\r
+\r
+#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 24000000 )\r
+*/\r
+\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 0\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+\r
+\r
+\r
+\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "portable.h"\r
+\r
+/* Processor Expert created headers. */\r
+#include "byte1.h"\r
+\r
+/* Demo application include files. */\r
+#include "partest.h"\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple parallel port IO routines.\r
+ *-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )\r
+{\r
+ /* This function is required as it is called from the standard demo \r
+ application files. All it does however is call the Processor Expert\r
+ created function. */\r
+ portENTER_CRITICAL();\r
+ Byte1_PutBit( uxLED, !xValue );\r
+ portEXIT_CRITICAL();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+ /* This function is required as it is called from the standard demo\r
+ application files. All it does however is call the processor Expert\r
+ created function. */\r
+ portENTER_CRITICAL();\r
+ Byte1_NegBit( uxLED );\r
+ portEXIT_CRITICAL();\r
+}\r
+\r
+\r
+\r
--- /dev/null
+;Please do not modify this file!\r
+;The file contains internal information about the Processor Expert project generation\r
+[Options]\r
+ProjectName=RTOSDemo\r
+ProjectDirectory=E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior_small\\r
+DestEventsDirectory=CODE\\r
+DestDriversSubDirectory=\r
+DestDocumentationDirectory=DOC\\r
+DestCompiledFilesSubDirectory=\r
+DestFpgaSubDirectory=\r
+DestTemporaryDirectory=\r
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+Line=E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior_small\CODE\Vectors.c\r
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+DestinationCompiler=MetrowerksHC12CC\r
+ProjectModificationStamp=23\r
+\r
+[18]\r
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+BeforeNewSpeed_Name=TickTimer_BeforeNewSpeed\r
+BeforeNewSpeed_Priority=interrupts disabled\r
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+OnInterrupt_Name=vTaskTickInterrupt\r
+OnInterrupt_Priority=same as interrupt\r
+GenSmartUserChangesDetected_Header=No\r
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+\r
+[_end_]\r
--- /dev/null
+[Version]\r
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+\r
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+\r
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+\r
+[CpuExpert]\r
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+[_end_]\r
--- /dev/null
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+[Childs]\r
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+[EndOfChilds]\r
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+RuntimeSetting=1\r
+InitValue=1000 Hz\r
+Precision=5\r
+PrecInProc=Yes\r
+LowLimit=100 Hz\r
+HighLimit=1000 Hz\r
+List=0\r
+UnitText=Hz\r
+[ItemState]\r
+ItemSymbol=SameValuesInAllModes\r
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+ItemSymbol=SetPeriodReal\r
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+\r
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+\r
+[EndOfChilds]\r
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+[ExtInt:ButtonInterrupt]\r
+CompNumb=26\r
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+IconName=EXTINT\r
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+Template=\r
+\r
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+ItemSymbol=InitEdge\r
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+[ItemState]\r
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+\r
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+\r
+[Childs]\r
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+\r
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+ItemSymbol=GetVal\r
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+[ItemState]\r
+ItemSymbol=SetEdge\r
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+[Childs]\r
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+LastUserSel=no\r
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+\r
+[EndOfChilds]\r
+\r
+[Events]\r
+List=Event\r
+[ItemState]\r
+ItemSymbol=EventModule\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=ADVANCED\r
+Value=Events\r
+[ItemState]\r
+ItemSymbol=OnInterrupt\r
+ReadOnly=Yes\r
+UserReadOnly=No\r
+BasAdvHid=BASIC\r
+Value=Yes\r
+\r
+[Childs]\r
+List=GrupItem\r
+[ItemState]\r
+ItemSymbol=Name\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=BASIC\r
+Value=ButtonInterrupt_OnInterrupt\r
+[ItemState]\r
+ItemSymbol=Priority\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=ADVANCED\r
+Value=same as interrupt\r
+\r
+[EndOfChilds]\r
+LastSelection=No\r
+LastUserSel=always\r
+[ItemState]\r
+ItemSymbol=CPUCondJBJG\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=BASIC\r
+\r
+[Childs]\r
+List=GrupItem\r
+[ItemState]\r
+ItemSymbol=OnTriggerInterrupt\r
+ReadOnly=Yes\r
+UserReadOnly=No\r
+BasAdvHid=BASIC\r
+Value=No\r
+\r
+[Childs]\r
+List=GrupItem\r
+[ItemState]\r
+ItemSymbol=Name\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=BASIC\r
+Value=ButtonInterrupt_OnTriggerInterrupt\r
+[ItemState]\r
+ItemSymbol=Priority\r
+ReadOnly=No\r
+UserReadOnly=No\r
+BasAdvHid=BASIC\r
+Value=interrupts disabled\r
+\r
+[EndOfChilds]\r
+LastSelection=No\r
+LastUserSel=never\r
+\r
+[EndOfChilds]\r
+\r
+[Program]\r
+ProgType=event\r
+ProgNumb=2\r
+List=Property\r
+EventModule=Events\r
+\r
+[_end_]\r
--- /dev/null
+[Environment Variables]\r
+GENPATH={Compiler}lib\HC12c\src;{Compiler}lib\HC12c\include;{Compiler}lib\HC12c\lib\r
+LIBPATH={Compiler}lib\HC12c\include\r
+OBJPATH={Project}bin\r
+TEXTPATH={Project}bin\r
+ABSPATH={Project}bin\r
+\r
+[HI-WAVE]\r
+Target=sim\r
+Layout=C_layout.hwl\r
+LoadDialogOptions=\r
+CPU=HC12\r
+MainFrame=2,3,-1,-1,-1,-1,243,243,1443,1097\r
+TOOLBAR=57600 57601 32795 0 57635 57634 57637 0 57671 57669 0 32777 32776 32782 32780 32781 32778 0 32806\r
+\r
+[Simulator]\r
+CMDFILE0=CMDFILE STARTUP ON ".\cmd\simulator_startup.cmd"\r
+\r
+[Simulator HC12]\r
+CMDFILE0=CMDFILE RESET ON ".\cmd\simulator_reset.cmd"\r
+CMDFILE1=CMDFILE PRELOAD ON ".\cmd\simulator_preload.cmd"\r
+CMDFILE2=CMDFILE POSTLOAD ON ".\cmd\simulator_postload.cmd"\r
+CMDFILE3=CMDFILE SETCPU ON ".\cmd\simulator_setcpu.cmd"\r
+HCS12_SUPPORT=1\r
+FCS=MC9S12C32\r
+\r
+[Recent Applications File List]\r
+File1=E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior\bin\Simulator.abs\r
+File2=\r
+File3=\r
+File4=\r
+LoadFlags1=4099\r
+LoadFlags2=0\r
+LoadFlags3=0\r
+LoadFlags4=0\r
+\r
+[Recent Layout File List]\r
+File1=C_layout.hwl\r
+File2=\r
+File3=\r
+File4=\r
--- /dev/null
+[Environment Variables]\r
+GENPATH={Compiler}lib\HC12c\src;{Compiler}lib\HC12c\include;{Compiler}lib\HC12c\lib\r
+LIBPATH={Compiler}lib\HC12c\include\r
+OBJPATH={Project}bin\r
+TEXTPATH={Project}bin\r
+ABSPATH={Project}bin\r
+\r
+[HI-WAVE]\r
+Target=gdi\r
+Layout=C_layout.hwl\r
+LoadDialogOptions=AUTOERASEANDFLASH\r
+CPU=HC12\r
+MainFrame=2,3,-1,-1,-1,-1,216,216,1416,1070\r
+TOOLBAR=57600 57601 32795 0 57635 57634 57637 0 57671 57669 0 32777 32776 32782 32780 32781 32778 0 32806\r
+\r
+[GDI]\r
+COMSETTINGS=SETCOMM DRIVER NOPROTOCOL NOPERIODICAL "SofTec_BDM12.dll"\r
+\r
+[SofTec_Microsystems_GdiHCS12]\r
+Hardware=PK-HCS12C32\r
+DeviceName=MC9S12C32\r
+Settings=-\r
+\r
+[inDART-HCS12_GDI_SETTINGS]\r
+CMDFILE0=CMDFILE STARTUP ON ".\cmd\SofTec_startup.cmd"\r
+CMDFILE1=CMDFILE RESET ON ".\cmd\SofTec_reset.cmd"\r
+CMDFILE2=CMDFILE PRELOAD ON ".\cmd\SofTec_preload.cmd"\r
+CMDFILE3=CMDFILE POSTLOAD ON ".\cmd\SofTec_postload.cmd"\r
+BNKA_MCUID03E1_BANKWINDOW0=BANKWINDOW PPAGE ON 0x8000..0xBFFF 0x30 2 0x3E\r
+BNKA_MCUID03E1_BANKWINDOW1=BANKWINDOW DPAGE OFF 0x7000..0x7FFF 0x34 256 0x0\r
+BNKA_MCUID03E1_BANKWINDOW2=BANKWINDOW EPAGE OFF 0x400..0x7FF 0x36 256 0x0\r
+DBG_S12_0=DBG GENERAL DISARM_ON PROTECT_OFF ANALYZE_ON STEPATRUN_ON\r
+DBG_S12_1=DBG USER12 0x0 0x0 0x0 0x0\r
+DBG_S12_2=DBG PREDEFINED SELECT 0 END STOP 0x0 DATAMATCH_HIGH NORMAL\r
+\r
+[Recent Applications File List]\r
+File1=E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior\bin\SofTec.abs\r
+File2=\r
+File3=\r
+File4=\r
+LoadFlags1=4099\r
+LoadFlags2=0\r
+LoadFlags3=0\r
+LoadFlags4=0\r
+\r
+[Recent Layout File List]\r
+File1=C_layout.hwl\r
+File2=\r
+File3=\r
+File4=\r
--- /dev/null
+/*****************************************************\r
+ start12.c - standard startup code\r
+ The startup code may be optimized to special user requests\r
+ ----------------------------------------------------\r
+ Copyright (c) Metrowerks, Basel, Switzerland\r
+ All rights reserved\r
+ Do not modify!\r
+\r
+Note: ROM libraries are not implemented in this startup code\r
+Note: C++ destructors of global objects are NOT yet supported in the HIWARE Object File Format.\r
+ To use this feature, please build your application with the ELF object file format.\r
+ *****************************************************/\r
+\r
+#include "hidef.h"\r
+#include "start12.h"\r
+\r
+/* Macros to control how the startup code handles the COP: */\r
+/* #define _DO_FEED_COP_ : do feed the COP */\r
+/* #define _DO_ENABLE_COP_: do enable the COP */\r
+/* #define _DO_DISABLE_COP_: disable the COP */\r
+/* Without defining any of these, the startup code does NOT handle the COP */\r
+\r
+#pragma DATA_SEG __NEAR_SEG STARTUP_DATA /* _startupData can be accessed using 16 bit accesses. This is needed because it contains the stack top, and without stack, far data cannot be accessed */\r
+struct _tagStartup _startupData; /* read-only: */\r
+ /* _startupData is allocated in ROM and */\r
+ /* initialized by the linker */\r
+#pragma DATA_SEG DEFAULT\r
+#if defined(FAR_DATA)\r
+#include "non_bank.sgm"\r
+/* the init function must be in non banked memory if banked variables are used */\r
+/* because _SET_PAGE is called, which may change any page register. */\r
+\r
+#ifdef __cplusplus\r
+ extern "C"\r
+#endif\r
+void _SET_PAGE(void); /* the inline assembler needs a prototype */\r
+ /* this is a runtime routine with a special */\r
+ /* calling convention, dont use it in c code! */\r
+static void Init(void);\r
+static void Fini(void);\r
+#else\r
+#include "default.sgm"\r
+#if defined( __BANKED__) || defined(__LARGE__)\r
+static void __far Init(void);\r
+static void __far Fini(void);\r
+#endif /* defined( __BANKED__) || defined(__LARGE__) */\r
+#endif /* FAR_DATA */\r
+\r
+\r
+/* define value and bits for Windef Register */\r
+#ifdef HC812A4\r
+#define WINDEF (*(volatile unsigned char*) 0x37)\r
+#if defined( __BANKED__) || defined(__LARGE__) || defined(__PPAGE__)\r
+#define __ENABLE_PPAGE__ 0x40\r
+#else\r
+#define __ENABLE_PPAGE__ 0x0\r
+#endif\r
+#if defined(__DPAGE__)\r
+#define __ENABLE_DPAGE__ 0x80\r
+#else\r
+#define __ENABLE_DPAGE__ 0x0\r
+#endif\r
+#if defined(__EPAGE__)\r
+#define __ENABLE_EPAGE__ 0x20\r
+#else\r
+#define __ENABLE_EPAGE__ 0x0\r
+#endif\r
+#endif /* HC812A4 */\r
+\r
+#ifdef _HCS12_SERIALMON\r
+ /* for Monitor based software remap the RAM & EEPROM to adhere\r
+ to EB386. Edit RAM and EEPROM sections in PRM file to match these. */\r
+#define ___INITRM (*(volatile unsigned char *) 0x0010)\r
+#define ___INITRG (*(volatile unsigned char *) 0x0011)\r
+#define ___INITEE (*(volatile unsigned char *) 0x0012)\r
+#endif\r
+\r
+#if defined(_DO_FEED_COP_)\r
+#define __FEED_COP_IN_HLI() } __asm movb #0x55, _COP_RST_ADR; __asm movb #0xAA, _COP_RST_ADR; __asm {\r
+#else\r
+#define __FEED_COP_IN_HLI() /* do nothing */\r
+#endif\r
+\r
+#if !defined(FAR_DATA) && (defined( __BANKED__) || defined(__LARGE__))\r
+static void __far Init(void)\r
+#else\r
+static void Init(void)\r
+#endif\r
+ {\r
+/* purpose: 1) zero out RAM-areas where data is allocated */\r
+/* 2) copy initialization data from ROM to RAM */\r
+/* 3) call global constructors in C++ */\r
+/* called from: _Startup, LibInits */\r
+ __asm {\r
+ZeroOut:\r
+#if defined(__HIWARE_OBJECT_FILE_FORMAT__) && defined(__LARGE__)\r
+ LDX _startupData.pZeroOut:1 ; in the large memory model in the HIWARE format, pZeroOut is a 24 bit pointer\r
+#else\r
+ LDX _startupData.pZeroOut ; *pZeroOut\r
+#endif\r
+ LDY _startupData.nofZeroOuts ; nofZeroOuts\r
+ BEQ CopyDown ; if nothing to zero out\r
+\r
+NextZeroOut: PSHY ; save nofZeroOuts\r
+#ifdef FAR_DATA\r
+ LDAB 1,X+ ; load page of destination address\r
+ LDY 2,X+ ; load offset of destination address\r
+ __PIC_JSR(_SET_PAGE) ; sets the page in the correct page register\r
+#else /* FAR_DATA */\r
+ LDY 2,X+ ; start address and advance *pZeroOut (X = X+4)\r
+#endif /* FAR_DATA */\r
+ LDD 2,X+ ; byte count\r
+#ifdef __OPTIMIZE_FOR_SIZE__ /* -os, default */\r
+NextWord: CLR 1,Y+ ; clear memory byte\r
+ __FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */\r
+ DBNE D, NextWord ; dec byte count\r
+#else\r
+ LSRD ; /2 and save bit 0 in the carry\r
+ PSHX\r
+ LDX #0\r
+LoopClrW: STX 2,Y+ ; Word-Clear\r
+ __FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */\r
+ DBNE D, LoopClrW\r
+ PULX\r
+ BCC LastClr ; handle last byte\r
+ CLR 1,Y+\r
+LastClr:\r
+#endif\r
+ PULY ; restore nofZeroOuts\r
+ DEY ; dec nofZeroOuts\r
+ BNE NextZeroOut\r
+CopyDown:\r
+#ifdef __ELF_OBJECT_FILE_FORMAT__\r
+ LDX _startupData.toCopyDownBeg ; load address of copy down desc.\r
+#else\r
+ LDX _startupData.toCopyDownBeg:2 ; load address of copy down desc.\r
+#endif\r
+NextBlock:\r
+ LDD 2,X+ ; size of init-data -> D\r
+ BEQ funcInits ; end of copy down desc.\r
+#ifdef FAR_DATA\r
+ PSHD ; save counter\r
+ LDAB 1,X+ ; load destination page\r
+ LDY 2,X+ ; destination address\r
+ __PIC_JSR(_SET_PAGE) ; sets the destinations page register\r
+ PULD ; restore counter\r
+#else /* FAR_DATA */\r
+ LDY 2,X+ ; load destination address\r
+#endif /* FAR_DATA */\r
+\r
+#ifdef __OPTIMIZE_FOR_SIZE__ /* -os, default */\r
+Copy: MOVB 1,X+,1,Y+ ; move a byte from ROM to the data area\r
+ __FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */\r
+ DBNE D,Copy ; copy-byte loop\r
+#else\r
+ LSRD ; /2 and save bit 0 in the carry\r
+Copy: MOVW 2,X+,2,Y+ ; move a word from ROM to the data area\r
+ __FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */\r
+ DBNE D,Copy ; copy-word loop\r
+ BCC NextBlock ; handle last byte?\r
+ MOVB 1,X+,1,Y+ ; copy the last byte\r
+#endif\r
+ BRA NextBlock\r
+funcInits: ; call of global construtors is only in c++ necessary\r
+#if defined(__cplusplus)\r
+#if defined(__ELF_OBJECT_FILE_FORMAT__)\r
+#if defined( __BANKED__) || defined(__LARGE__)\r
+ LDY _startupData.nofInitBodies; load number of cpp.\r
+ BEQ done ; if cppcount == 0, goto done\r
+ LDX _startupData.initBodies ; load address of first module to initialize\r
+nextInit:\r
+ LEAX 3,X ; increment to next init\r
+ PSHX ; save address of next function to initialize\r
+ PSHY ; save cpp counter\r
+ CALL [-3,X] ; use double indirect call to load the page register also\r
+ PULY ; restore cpp counter\r
+ PULX ; restore actual address\r
+ DEY ; decrement cpp counter\r
+ BNE nextInit\r
+#else /* defined( __BANKED__) || defined(__LARGE__) */\r
+\r
+ LDD _startupData.nofInitBodies; load number of cpp.\r
+ BEQ done ; if cppcount == 0, goto done\r
+ LDX _startupData.initBodies ; load address of first module to initialize\r
+nextInit:\r
+ LDY 2,X+ ; load address of first module to initialize\r
+ PSHD\r
+ PSHX ; save actual address\r
+ JSR 0,Y ; call initialization function\r
+ PULX ; restore actual address\r
+ PULD ; restore cpp counter\r
+ DBNE D, nextInit\r
+#endif /* defined( __BANKED__) || defined(__LARGE__) */\r
+#else /* __ELF_OBJECT_FILE_FORMAT__ */\r
+ LDX _startupData.mInits ; load address of first module to initialize\r
+#if defined( __BANKED__) || defined(__LARGE__)\r
+nextInit: LDY 3,X+ ; load address of initialization function\r
+ BEQ done ; stop when address == 0\r
+ ; in common environments the offset of a function is never 0, so this test could be avoided\r
+#ifdef __InitFunctionsMayHaveOffset0__\r
+ BRCLR -1,X, done, 0xff ; stop when address == 0\r
+#endif /* __InitFunctionsMayHaveOffset0__ */\r
+ PSHX ; save address of next function to initialize\r
+ CALL [-3,X] ; use double indirect call to load the page register also\r
+#else /* defined( __BANKED__) || defined(__LARGE__) */\r
+nextInit:\r
+ LDY 2,X+ ; load address of first module to initialize\r
+ BEQ done ; stop when address of function == 0\r
+ PSHX ; save actual address\r
+ JSR 0,Y ; call initialization function\r
+#endif /* defined( __BANKED__) || defined(__LARGE__) */\r
+ PULX ; restore actual address\r
+ BRA nextInit\r
+#endif /* __ELF_OBJECT_FILE_FORMAT__ */\r
+done:\r
+#endif /* __cplusplus */\r
+ }\r
+}\r
+\r
+#if defined( __ELF_OBJECT_FILE_FORMAT__) && defined(__cplusplus )\r
+\r
+#if !defined(FAR_DATA) && (defined( __BANKED__) || defined(__LARGE__))\r
+static void __far Fini(void)\r
+#else\r
+static void Fini(void)\r
+#endif\r
+{\r
+/* purpose: 1) call global destructors in C++ */\r
+ __asm {\r
+#if defined( __BANKED__) || defined(__LARGE__)\r
+\r
+ LDY _startupData.nofFiniBodies; load number of cpp.\r
+ BEQ done ; if cppcount == 0, goto done\r
+ LDX _startupData.finiBodies ; load address of first module to finalize\r
+nextInit2:\r
+ LEAX 3,X ; increment to next init\r
+ PSHX ; save address of next function to finalize\r
+ PSHY ; save cpp counter\r
+ CALL [-3,X] ; use double indirect call to load the page register also\r
+ PULY ; restore cpp counter\r
+ PULX ; restore actual address\r
+ DEY ; decrement cpp counter\r
+ BNE nextInit2\r
+#else /* defined( __BANKED__) || defined(__LARGE__) */\r
+\r
+ LDD _startupData.nofFiniBodies; load number of cpp.\r
+ BEQ done ; if cppcount == 0, goto done\r
+ LDX _startupData.finiBodies ; load address of first module to finalize\r
+nextInit2:\r
+ LDY 2,X+ ; load address of first module to finalize\r
+ PSHD\r
+ PSHX ; save actual address\r
+ JSR 0,Y ; call finalize function\r
+ PULX ; restore actual address\r
+ PULD ; restore cpp counter\r
+ DBNE D, nextInit2\r
+#endif /* defined( __BANKED__) || defined(__LARGE__) */\r
+done:;\r
+ }\r
+}\r
+#endif\r
+\r
+\r
+#include "non_bank.sgm"\r
+\r
+#pragma MESSAGE DISABLE C12053 /* Stack-pointer change not in debugging-information */\r
+#pragma NO_FRAME\r
+#pragma NO_ENTRY\r
+#pragma NO_EXIT\r
+\r
+#ifdef __cplusplus\r
+ extern "C"\r
+#endif\r
+\r
+/* The function _Startup must be called in order to initialize global variables and to call main */\r
+/* You can adapt this function or call it from your startup code to implement a different startup */\r
+/* functionality. */\r
+\r
+/* You should also setup the needed IO registers as WINDEF (HC12A4 only) or the COP registers to run */\r
+/* on hardware */\r
+\r
+/* to set the reset vector several ways are possible : */\r
+/* 1. define the function with "interrupt 0" as done below in the first case */\r
+/* 2. add the following line to your prm file : VECTOR ADDRESS 0xfffe _Startup */\r
+/* of course, even more posibilities exists */\r
+/* the reset vector must be set so that the application has a defined entry point */\r
+\r
+#define STARTUP_FLAGS_NOT_INIT_SP (1<<1)\r
+\r
+#if defined(__SET_RESET_VECTOR__)\r
+void __interrupt 0 _Startup(void) {\r
+#else\r
+void _Startup(void) {\r
+#endif\r
+/* purpose: 1) initialize the stack\r
+ 2) initialize the RAM, copy down init data etc (Init)\r
+ 3) call main;\r
+ parameters: NONE\r
+ called from: _PRESTART-code generated by the Linker \r
+ or directly referenced by the reset vector */\r
+ for(;;) { /* forever: initialize the program; call the root-procedure */\r
+ if (!(_startupData.flags&STARTUP_FLAGS_NOT_INIT_SP)) {\r
+ /* initialize the stack pointer */\r
+ INIT_SP_FROM_STARTUP_DESC(); /*lint !e522 asm code */ /* HLI macro definition in hidef.h */\r
+ }\r
+\r
+#ifdef _HCS12_SERIALMON\r
+ /* for Monitor based software remap the RAM & EEPROM to adhere\r
+ to EB386. Edit RAM and EEPROM sections in PRM file to match these. */\r
+ ___INITRG = 0x00; /* lock registers block to 0x0000 */\r
+ ___INITRM = 0x39; /* lock Ram to end at 0x3FFF */\r
+ ___INITEE = 0x09; /* lock EEPROM block to end at 0x0fff */\r
+#endif\r
+ \r
+ /* Here user defined code could be inserted, the stack could be used */\r
+#if defined(_DO_DISABLE_COP_)\r
+ _DISABLE_COP();\r
+#endif \r
+\r
+ /* Example : Set up WinDef Register to allow Paging */\r
+#ifdef HC812A4 /* HC12 A4 derivative needs WINDEF to configure which pages are available */\r
+#if (__ENABLE_EPAGE__ != 0 || __ENABLE_DPAGE__ != 0 || __ENABLE_PPAGE__ != 0)\r
+ WINDEF= __ENABLE_EPAGE__ | __ENABLE_DPAGE__ | __ENABLE_PPAGE__;\r
+#endif\r
+#endif\r
+ Init(); /* zero out, copy down, call constructors */\r
+ /* Here user defined code could be inserted, all global variables are initilized */\r
+#if defined(_DO_ENABLE_COP_)\r
+ _ENABLE_COP(1);\r
+#endif\r
+\r
+ /* call main() */\r
+ (*_startupData.main)();\r
+\r
+ /* call destructors. Only done when this file is compiled as C++ and for the ELF object file format */\r
+ /* the HIWARE object file format does not support this */\r
+#if defined( __ELF_OBJECT_FILE_FORMAT__) && defined(__cplusplus )\r
+ Fini();\r
+#endif\r
+\r
+ } /* end loop forever */\r
+}\r
--- /dev/null
+/******************************************************************************\r
+ FILE : datapage.c\r
+ PURPOSE : paged data access runtime routines\r
+ MACHINE : Motorola 68HC12 (Target)\r
+ LANGUAGE : ANSI-C\r
+ HISTORY : 21.7.96 first version created\r
+******************************************************************************/\r
+\r
+/*\r
+ According to the -Cp option of the compiler the\r
+ __DPAGE__, __PPAGE__ and __EPAGE__ macros are defined.\r
+ If none of them is given as argument, then no page accesses should occur and\r
+ this runtime routine should not be used !\r
+ To be on the save side, the runtime routines are created anyway.\r
+ If some of the -Cp options are given an adapted versions which only covers the\r
+ needed cases is produced.\r
+*/\r
+\r
+/* if no compiler option -Cp is given, it is assumed that all possible are given : */\r
+\r
+/* Compile with option -DHCS12 to activate this code */\r
+#if defined(HCS12) || defined(_HCS12) /* HCS12 family has PPAGE register only at 0x30 */\r
+#define PPAGE_ADDR (0x30+REGISTER_BASE)\r
+#ifndef __PPAGE__ /* may be set already by option -CPPPAGE */\r
+#define __PPAGE__\r
+#endif\r
+/* Compile with option -DDG128 to activate this code */\r
+#elif defined DG128 /* HC912DG128 derivative has PPAGE register only at 0xFF */\r
+#define PPAGE_ADDR (0xFF+REGISTER_BASE)\r
+#ifndef __PPAGE__ /* may be set already by option -CPPPAGE */\r
+#define __PPAGE__\r
+#endif\r
+#elif defined(HC812A4)\r
+/* all setting default to A4 already */\r
+#endif\r
+\r
+\r
+#if !defined(__EPAGE__) && !defined(__PPAGE__) && !defined(__DPAGE__)\r
+/* as default use all page registers */\r
+#define __DPAGE__\r
+#define __EPAGE__\r
+#define __PPAGE__\r
+#endif\r
+\r
+/* modify the following defines to your memory configuration */\r
+\r
+#define EPAGE_LOW_BOUND 0x400u\r
+#define EPAGE_HIGH_BOUND 0x7ffu\r
+\r
+#define DPAGE_LOW_BOUND 0x7000u\r
+#define DPAGE_HIGH_BOUND 0x7fffu\r
+\r
+#define PPAGE_LOW_BOUND (DPAGE_HIGH_BOUND+1)\r
+#define PPAGE_HIGH_BOUND 0xBFFFu\r
+\r
+#define REGISTER_BASE 0x0u\r
+#ifndef DPAGE_ADDR\r
+#define DPAGE_ADDR (0x34u+REGISTER_BASE)\r
+#endif\r
+#ifndef EPAGE_ADDR\r
+#define EPAGE_ADDR (0x36u+REGISTER_BASE)\r
+#endif\r
+#ifndef PPAGE_ADDR\r
+#define PPAGE_ADDR (0x35u+REGISTER_BASE)\r
+#endif\r
+\r
+/*\r
+ The following parts about the defines are assumed in the code of _GET_PAGE_REG :\r
+ - the memory region controlled by DPAGE is above the area controlled by the EPAGE and\r
+ below the area controlled by the PPAGE.\r
+ - the lower bound of the PPAGE area is equal to be the higher bound of the DPAGE area + 1\r
+*/\r
+#if EPAGE_LOW_BOUND >= EPAGE_HIGH_BOUND || EPAGE_HIGH_BOUND >= DPAGE_LOW_BOUND || DPAGE_LOW_BOUND >= DPAGE_HIGH_BOUND || DPAGE_HIGH_BOUND >= PPAGE_LOW_BOUND || PPAGE_LOW_BOUND >= PPAGE_HIGH_BOUND\r
+#error /* please adapt _GET_PAGE_REG for this non default page configuration */\r
+#endif\r
+\r
+#if DPAGE_HIGH_BOUND+1 != PPAGE_LOW_BOUND\r
+#error /* please adapt _GET_PAGE_REG for this non default page configuration */\r
+#endif\r
+\r
+#include "hidef.h"\r
+#include "non_bank.sgm"\r
+#include "runtime.sgm"\r
+\r
+/* this module does either control if any access is in the bounds of the specified page or */\r
+/* ,if only one page is specified, just use this page. */\r
+/* This behavior is controlled by the define USE_SEVERAL_PAGES. */\r
+/* If !USE_SEVERAL_PAGES does increase the performance significantly */\r
+/* NOTE : When !USE_SEVERAL_PAGES, the page is also set for accesses outside of the area controlled */\r
+/* by this single page. But this is usually no problem because the page is set again before any other access */\r
+\r
+#if !defined(__DPAGE__) && !defined(__EPAGE__) && !defined(__PPAGE__)\r
+/* no page at all is specified */\r
+/* only specifing the right pages will speed up these functions a lot */\r
+#define USE_SEVERAL_PAGES 1\r
+#elif defined(__DPAGE__) && defined(__EPAGE__) || defined(__DPAGE__) && defined(__PPAGE__) || defined(__EPAGE__) && defined(__PPAGE__)\r
+/* more than one page register is used */\r
+#define USE_SEVERAL_PAGES 1\r
+#else\r
+\r
+#define USE_SEVERAL_PAGES 0\r
+\r
+#if defined(__DPAGE__) /* check which pages are used */\r
+#define PAGE_ADDR PPAGE_ADDR\r
+#elif defined(__EPAGE__)\r
+#define PAGE_ADDR EPAGE_ADDR\r
+#elif defined(__PPAGE__)\r
+#define PAGE_ADDR PPAGE_ADDR\r
+#else /* we dont know which page, decide it at runtime */\r
+#error /* must not happen */\r
+#endif\r
+\r
+#endif\r
+\r
+\r
+#if USE_SEVERAL_PAGES /* only needed for several pages support */\r
+/*--------------------------- _GET_PAGE_REG --------------------------------\r
+ Runtime routine to detect the right register depending on the 16 bit offset part\r
+ of an address.\r
+ This function is only used by the functions below.\r
+\r
+ Depending on the compiler options -Cp different versions of _GET_PAGE_REG are produced.\r
+\r
+ Arguments :\r
+ - Y : offset part of an address\r
+\r
+ Result :\r
+ if address Y is controlled by a page register :\r
+ - X : address of page register if Y is controlled by an page register\r
+ - Zero flag cleared\r
+ - all other registers remain unchanged\r
+\r
+ if address Y is not controlled by a page register :\r
+ - Zero flag is set\r
+ - all registers remain unchanged\r
+\r
+ --------------------------- _GET_PAGE_REG ----------------------------------*/\r
+\r
+#if defined(__DPAGE__)\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+#endif\r
+#pragma NO_ENTRY\r
+#pragma NO_EXIT\r
+#pragma NO_FRAME\r
+\r
+static void NEAR _GET_PAGE_REG(void) { /*lint -esym(528, _GET_PAGE_REG) used in asm code */\r
+ asm {\r
+L_DPAGE:\r
+ CPY #DPAGE_LOW_BOUND ; test of lower bound of DPAGE\r
+#if defined(__EPAGE__)\r
+ BLO L_EPAGE ; EPAGE accesses are possible\r
+#else\r
+ BLO L_NOPAGE ; no paged memory below accesses\r
+#endif\r
+ CPY #DPAGE_HIGH_BOUND ; test of higher bound DPAGE/lower bound PPAGE\r
+#if defined(__PPAGE__)\r
+ BHI L_PPAGE ; EPAGE accesses are possible\r
+#else\r
+ BHI L_NOPAGE ; no paged memory above accesses\r
+#endif\r
+FOUND_DPAGE:\r
+ LDX #DPAGE_ADDR ; load page register address and clear zero flag\r
+ RTS\r
+\r
+#if defined(__PPAGE__)\r
+L_PPAGE:\r
+ CPY #PPAGE_HIGH_BOUND ; test of higher bound of PPAGE\r
+ BHI L_NOPAGE\r
+FOUND_PPAGE:\r
+ LDX #PPAGE_ADDR ; load page register address and clear zero flag\r
+ RTS\r
+#endif\r
+\r
+#if defined(__EPAGE__)\r
+L_EPAGE:\r
+ CPY #EPAGE_LOW_BOUND ; test of lower bound of EPAGE\r
+ BLO L_NOPAGE\r
+ CPY #EPAGE_HIGH_BOUND ; test of higher bound of EPAGE\r
+ BHI L_NOPAGE\r
+\r
+FOUND_EPAGE:\r
+ LDX #EPAGE_ADDR ; load page register address and clear zero flag\r
+ RTS\r
+#endif\r
+\r
+L_NOPAGE:\r
+ ORCC #0x04 ; sets zero flag\r
+ RTS\r
+ }\r
+}\r
+\r
+#else /* !defined(__DPAGE__) */\r
+\r
+#if defined( __PPAGE__ )\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+#endif\r
+#pragma NO_ENTRY\r
+#pragma NO_EXIT\r
+#pragma NO_FRAME\r
+\r
+static void NEAR _GET_PAGE_REG(void) { /*lint -esym(528, _GET_PAGE_REG) used in asm code */\r
+ asm {\r
+L_PPAGE:\r
+ CPY #PPAGE_LOW_BOUND ; test of lower bound of PPAGE\r
+#if defined( __EPAGE__ )\r
+ BLO L_EPAGE\r
+#else\r
+ BLO L_NOPAGE ; no paged memory below\r
+#endif\r
+ CPY #PPAGE_HIGH_BOUND ; test of higher bound PPAGE\r
+ BHI L_NOPAGE\r
+FOUND_PPAGE:\r
+ LDX #PPAGE_ADDR ; load page register address and clear zero flag\r
+ RTS\r
+#if defined( __EPAGE__ )\r
+L_EPAGE:\r
+ CPY #EPAGE_LOW_BOUND ; test of lower bound of EPAGE\r
+ BLO L_NOPAGE\r
+ CPY #EPAGE_HIGH_BOUND ; test of higher bound of EPAGE\r
+ BHI L_NOPAGE\r
+FOUND_EPAGE:\r
+ LDX #EPAGE_ADDR ; load page register address and clear zero flag\r
+ RTS\r
+#endif\r
+\r
+L_NOPAGE: ; not in any allowed page area\r
+ ; its a far access to a non paged variable\r
+ ORCC #0x04 ; sets zero flag\r
+ RTS\r
+ }\r
+}\r
+\r
+#else /* !defined(__DPAGE__ ) && !defined( __PPAGE__) */\r
+#if defined(__EPAGE__)\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+#endif\r
+#pragma NO_ENTRY\r
+#pragma NO_EXIT\r
+#pragma NO_FRAME\r
+\r
+static void NEAR _GET_PAGE_REG(void) { /*lint -esym(528, _GET_PAGE_REG) used in asm code */\r
+ asm {\r
+L_EPAGE:\r
+ CPY #EPAGE_LOW_BOUND ; test of lower bound of EPAGE\r
+ BLO L_NOPAGE\r
+ CPY #EPAGE_HIGH_BOUND ; test of higher bound of EPAGE\r
+ BHI L_NOPAGE\r
+FOUND_EPAGE:\r
+ LDX #EPAGE_ADDR ; load page register address and clear zero flag\r
+ RTS\r
+\r
+L_NOPAGE: ; not in any allowed page area\r
+ ; its a far access to a non paged variable\r
+ ORCC #0x04 ; sets zero flag\r
+ RTS\r
+ }\r
+}\r
+\r
+#endif /* defined(__EPAGE__) */\r
+#endif /* defined(__PPAGE__) */\r
+#endif /* defined(__DPAGE__) */\r
+\r
+#endif /* USE_SEVERAL_PAGES */\r
+\r
+/*--------------------------- _SET_PAGE --------------------------------\r
+ Runtime routine to set the right page register. This routine is used if the compiler\r
+ does not know the right page register, i.e. if the option -Cp is used for more than\r
+ one pageregister or if the runtime option is used for one of the -Cp options.\r
+\r
+ Arguments :\r
+ - offset part of an address in the Y register\r
+ - page part of an address in the B register\r
+\r
+ Result :\r
+ - page part written into the correct page register.\r
+ - the old page register content is destroyed\r
+ - all processor registers remains unchanged\r
+ --------------------------- _SET_PAGE ----------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+#endif\r
+#pragma NO_ENTRY\r
+#pragma NO_EXIT\r
+#pragma NO_FRAME\r
+\r
+void NEAR _SET_PAGE(void) {\r
+#if USE_SEVERAL_PAGES\r
+ asm {\r
+ PSHX ; save X register\r
+ __PIC_JSR(_GET_PAGE_REG)\r
+ BEQ L_NOPAGE\r
+ STAB 0,X ; set page register\r
+L_NOPAGE:\r
+ PULX ; restore X register\r
+ RTS\r
+ }\r
+#else /* USE_SEVERAL_PAGES */\r
+ asm {\r
+ STAB PAGE_ADDR ; set page register\r
+ RTS\r
+ }\r
+#endif /* USE_SEVERAL_PAGES */\r
+}\r
+\r
+/*--------------------------- _LOAD_FAR_8 --------------------------------\r
+ This runtime routine is used to access paged memory via a runtime function.\r
+ It may also be used if the compiler option -Cp is not used with the runtime argument.\r
+\r
+ Arguments :\r
+ - offset part of an address in the Y register\r
+ - page part of an address in the B register\r
+\r
+ Result :\r
+ - value to be read in the B register\r
+ - all other registers remains unchanged\r
+ - all page register still contain the same value\r
+ --------------------------- _LOAD_FAR_8 ----------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+#endif\r
+#pragma NO_ENTRY\r
+#pragma NO_EXIT\r
+#pragma NO_FRAME\r
+\r
+void NEAR _LOAD_FAR_8(void) {\r
+#if USE_SEVERAL_PAGES\r
+ asm {\r
+ PSHX ; save X register\r
+ __PIC_JSR(_GET_PAGE_REG)\r
+ BEQ L_NOPAGE\r
+ PSHA ; save A register\r
+ LDAA 0,X ; save page register\r
+ STAB 0,X ; set page register\r
+ LDAB 0,Y ; actual load, overwrites page\r
+ STAA 0,X ; restore page register\r
+ PULA ; restore A register\r
+ PULX ; restore X register\r
+ RTS\r
+L_NOPAGE:\r
+ LDAB 0,Y ; actual load, overwrites page\r
+ PULX ; restore X register\r
+ RTS\r
+ }\r
+#else /* USE_SEVERAL_PAGES */\r
+ asm {\r
+ PSHA ; save A register\r
+ LDAA PAGE_ADDR ; save page register\r
+ STAB PAGE_ADDR ; set page register\r
+ LDAB 0,Y ; actual load, overwrites page\r
+ STAA PAGE_ADDR ; restore page register\r
+ PULA ; restore A register\r
+ RTS\r
+ }\r
+#endif /* USE_SEVERAL_PAGES */\r
+}\r
+\r
+/*--------------------------- _LOAD_FAR_16 --------------------------------\r
+ This runtime routine is used to access paged memory via a runtime function.\r
+ It may also be used if the compiler option -Cp is not used with the runtime argument.\r
+\r
+ Arguments :\r
+ - offset part of an address in the Y register\r
+ - page part of an address in the B register\r
+\r
+ Result :\r
+ - value to be read in the Y register\r
+ - all other registers remains unchanged\r
+ - all page register still contain the same value\r
+ --------------------------- _LOAD_FAR_16 ----------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+#endif\r
+#pragma NO_ENTRY\r
+#pragma NO_EXIT\r
+#pragma NO_FRAME\r
+\r
+void NEAR _LOAD_FAR_16(void) {\r
+#if USE_SEVERAL_PAGES\r
+ asm {\r
+ PSHX ; save X register\r
+ __PIC_JSR(_GET_PAGE_REG)\r
+ BEQ L_NOPAGE\r
+ PSHA ; save A register\r
+ LDAA 0,X ; save page register\r
+ STAB 0,X ; set page register\r
+ LDY 0,Y ; actual load, overwrites address\r
+ STAA 0,X ; restore page register\r
+ PULA ; restore A register\r
+ PULX ; restore X register\r
+ RTS\r
+L_NOPAGE:\r
+ LDY 0,Y ; actual load, overwrites address\r
+ PULX ; restore X register\r
+ RTS\r
+ }\r
+#else /* USE_SEVERAL_PAGES */\r
+ asm {\r
+ PSHA ; save A register\r
+ LDAA PAGE_ADDR ; save page register\r
+ STAB PAGE_ADDR ; set page register\r
+ LDY 0,Y ; actual load, overwrites address\r
+ STAA PAGE_ADDR ; restore page register\r
+ PULA ; restore A register\r
+ RTS\r
+ }\r
+#endif /* USE_SEVERAL_PAGES */\r
+}\r
+/*--------------------------- _LOAD_FAR_24 --------------------------------\r
+ This runtime routine is used to access paged memory via a runtime function.\r
+ It may also be used if the compiler option -Cp is not used with the runtime argument.\r
+\r
+ Arguments :\r
+ - offset part of an address in the Y register\r
+ - page part of an address in the B register\r
+\r
+ Result :\r
+ - value to be read in the Y:B registers\r
+ - all other registers remains unchanged\r
+ - all page register still contain the same value\r
+ --------------------------- _LOAD_FAR_24 ----------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+#endif\r
+#pragma NO_ENTRY\r
+#pragma NO_EXIT\r
+#pragma NO_FRAME\r
+\r
+void NEAR _LOAD_FAR_24(void) {\r
+#if USE_SEVERAL_PAGES\r
+ asm {\r
+ PSHX ; save X register\r
+ __PIC_JSR(_GET_PAGE_REG)\r
+ BEQ L_NOPAGE\r
+ PSHA ; save A register\r
+ LDAA 0,X ; save page register\r
+ STAB 0,X ; set page register\r
+ LDAB 0,Y ; actual load, overwrites page of address\r
+ LDY 1,Y ; actual load, overwrites offset of address\r
+ STAA 0,X ; restore page register\r
+ PULA ; restore A register\r
+ PULX ; restore X register\r
+ RTS\r
+L_NOPAGE:\r
+ LDAB 0,Y ; actual load, overwrites page of address\r
+ LDY 1,Y ; actual load, overwrites offset of address\r
+ PULX ; restore X register\r
+ RTS\r
+ }\r
+#else /* USE_SEVERAL_PAGES */\r
+ asm {\r
+ PSHA ; save A register\r
+ LDAA PAGE_ADDR ; save page register\r
+ STAB PAGE_ADDR ; set page register\r
+ LDAB 0,Y ; actual load, overwrites page of address\r
+ LDY 1,Y ; actual load, overwrites offset of address\r
+ STAA PAGE_ADDR ; restore page register\r
+ PULA ; restore A register\r
+ RTS\r
+ }\r
+#endif /* USE_SEVERAL_PAGES */\r
+\r
+}\r
+\r
+/*--------------------------- _LOAD_FAR_32 --------------------------------\r
+ This runtime routine is used to access paged memory via a runtime function.\r
+ It may also be used if the compiler option -Cp is not used with the runtime argument.\r
+\r
+ Arguments :\r
+ - offset part of an address in the Y register\r
+ - page part of an address in the B register\r
+\r
+ Result :\r
+ - low 16 bit of value to be read in the D registers\r
+ - high 16 bit of value to be read in the Y registers\r
+ - all other registers remains unchanged\r
+ - all page register still contain the same value\r
+ --------------------------- _LOAD_FAR_32 ----------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+#endif\r
+#pragma NO_ENTRY\r
+#pragma NO_EXIT\r
+#pragma NO_FRAME\r
+\r
+void NEAR _LOAD_FAR_32(void) {\r
+#if USE_SEVERAL_PAGES\r
+ asm {\r
+ PSHX ; save X register\r
+ __PIC_JSR(_GET_PAGE_REG)\r
+ BEQ L_NOPAGE\r
+ LDAA 0,X ; save page register\r
+ PSHA ; put it onto the stack\r
+ STAB 0,X ; set page register\r
+ LDD 2,Y ; actual load, low word\r
+ LDY 0,Y ; actual load, high word\r
+ MOVB 1,SP+,0,X ; restore page register\r
+ PULX ; restore X register\r
+ RTS\r
+L_NOPAGE:\r
+ LDD 2,Y ; actual load, low word\r
+ LDY 0,Y ; actual load, high word\r
+ PULX ; restore X register\r
+ RTS\r
+ }\r
+#else /* USE_SEVERAL_PAGES */\r
+ asm {\r
+ LDAA PAGE_ADDR ; save page register\r
+ PSHA ; put it onto the stack\r
+ STAB PAGE_ADDR ; set page register\r
+ LDD 2,Y ; actual load, low word\r
+ LDY 0,Y ; actual load, high word\r
+ MOVB 1,SP+,PAGE_ADDR; restore page register\r
+ RTS\r
+ }\r
+#endif /* USE_SEVERAL_PAGES */\r
+}\r
+\r
+/*--------------------------- _STORE_FAR_8 --------------------------------\r
+ This runtime routine is used to access paged memory via a runtime function.\r
+ It may also be used if the compiler option -Cp is not used with the runtime argument.\r
+\r
+ Arguments :\r
+ - offset part of an address in the Y register\r
+ - page part of an address in the B register\r
+ - value to be stored in the B register\r
+\r
+ Result :\r
+ - value stored at the address\r
+ - all registers remains unchanged\r
+ - all page register still contain the same value\r
+ --------------------------- _STORE_FAR_8 ----------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+#endif\r
+#pragma NO_ENTRY\r
+#pragma NO_EXIT\r
+#pragma NO_FRAME\r
+\r
+void NEAR _STORE_FAR_8(void) {\r
+#if USE_SEVERAL_PAGES\r
+ asm {\r
+ PSHX ; save X register\r
+ __PIC_JSR(_GET_PAGE_REG)\r
+ BEQ L_NOPAGE\r
+ PSHB ; save B register\r
+ LDAB 0,X ; save page register\r
+ MOVB 0,SP, 0,X ; set page register\r
+ STAA 0,Y ; store the value passed in A\r
+ STAB 0,X ; restore page register\r
+ PULB ; restore B register\r
+ PULX ; restore X register\r
+ RTS\r
+L_NOPAGE:\r
+ STAA 0,Y ; store the value passed in A\r
+ PULX ; restore X register\r
+ RTS\r
+ }\r
+#else /* USE_SEVERAL_PAGES */\r
+ asm {\r
+ PSHB ; save A register\r
+ LDAB PAGE_ADDR ; save page register\r
+ MOVB 0,SP,PAGE_ADDR ; set page register\r
+ STAA 0,Y ; store the value passed in A\r
+ STAB PAGE_ADDR ; restore page register\r
+ PULB ; restore B register\r
+ RTS\r
+ }\r
+#endif /* USE_SEVERAL_PAGES */\r
+}\r
+\r
+/*--------------------------- _STORE_FAR_16 --------------------------------\r
+ This runtime routine is used to access paged memory via a runtime function.\r
+ It may also be used if the compiler option -Cp is not used with the runtime argument.\r
+\r
+ Arguments :\r
+ - offset part of an address in the Y register\r
+ - page part of an address in the B register\r
+ - value to be stored in the X register\r
+\r
+ Result :\r
+ - value stored at the address\r
+ - all registers remains unchanged\r
+ - all page register still contain the same value\r
+ --------------------------- _STORE_FAR_16 ----------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+#endif\r
+#pragma NO_ENTRY\r
+#pragma NO_EXIT\r
+#pragma NO_FRAME\r
+\r
+void NEAR _STORE_FAR_16(void) {\r
+#if USE_SEVERAL_PAGES\r
+ asm {\r
+ PSHX ; save X register\r
+ __PIC_JSR(_GET_PAGE_REG)\r
+ BEQ L_NOPAGE\r
+\r
+ PSHA\r
+ LDAA 0,X ; save page register\r
+ STAB 0,X ; set page register\r
+ MOVW 1,SP, 0,Y ; store the value passed in X\r
+ STAA 0,X ; restore page register\r
+ PULA ; restore A register\r
+ PULX ; restore X register\r
+ RTS\r
+\r
+L_NOPAGE:\r
+ STX 0,Y ; store the value passed in X\r
+ PULX ; restore X register\r
+ RTS\r
+ }\r
+#else /* USE_SEVERAL_PAGES */\r
+ asm {\r
+ PSHA ; save A register\r
+ LDAA PAGE_ADDR ; save page register\r
+ STAB PAGE_ADDR ; set page register\r
+ STX 0,Y ; store the value passed in X\r
+ STAA PAGE_ADDR ; restore page register\r
+ PULA ; restore A register\r
+ RTS\r
+ }\r
+#endif /* USE_SEVERAL_PAGES */\r
+}\r
+/*--------------------------- _STORE_FAR_24 --------------------------------\r
+ This runtime routine is used to access paged memory via a runtime function.\r
+ It may also be used if the compiler option -Cp is not used with the runtime argument.\r
+\r
+ Arguments :\r
+ - offset part of an address in the Y register\r
+ - page part of an address in the B register\r
+ - value to be stored in the X:A registers (X : low 16 bit, A : high 8 bit)\r
+\r
+ Result :\r
+ - value stored at the address\r
+ - all registers remains unchanged\r
+ - all page register still contain the same value\r
+ --------------------------- _STORE_FAR_24 ----------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+#endif\r
+#pragma NO_ENTRY\r
+#pragma NO_EXIT\r
+#pragma NO_FRAME\r
+\r
+void NEAR _STORE_FAR_24(void) {\r
+#if USE_SEVERAL_PAGES\r
+ asm {\r
+ PSHX ; save X register\r
+ __PIC_JSR(_GET_PAGE_REG)\r
+ BEQ L_NOPAGE\r
+\r
+ PSHA\r
+ LDAA 0,X ; save page register\r
+ STAB 0,X ; set page register\r
+ MOVW 1,SP, 1,Y ; store the value passed in X\r
+ MOVB 0,SP, 0,Y ; store the value passed in A\r
+ STAA 0,X ; restore page register\r
+ PULA ; restore A register\r
+ PULX ; restore X register\r
+ RTS\r
+\r
+L_NOPAGE:\r
+ STX 1,Y ; store the value passed in X\r
+ STAA 0,Y ; store the value passed in X\r
+ PULX ; restore X register\r
+ RTS\r
+ }\r
+#else /* USE_SEVERAL_PAGES */\r
+ asm {\r
+ PSHA ; save A register\r
+ LDAA PAGE_ADDR ; save page register\r
+ STAB PAGE_ADDR ; set page register\r
+ MOVB 0,SP, 0,Y ; store the value passed in A\r
+ STX 1,Y ; store the value passed in X\r
+ STAA PAGE_ADDR ; restore page register\r
+ PULA ; restore A register\r
+ RTS\r
+ }\r
+#endif /* USE_SEVERAL_PAGES */\r
+}\r
+/*--------------------------- _STORE_FAR_32 --------------------------------\r
+ This runtime routine is used to access paged memory via a runtime function.\r
+ It may also be used if the compiler option -Cp is not used with the runtime argument.\r
+\r
+ Arguments :\r
+ - offset part of an address in the Y register\r
+ - page part of an address is on the stack at 3,SP (just below the return address)\r
+ - value to be stored in the X:D registers (D : low 16 bit, X : high 16 bit)\r
+\r
+ Result :\r
+ - value stored at the address\r
+ - all registers remains unchanged\r
+ - the page part is removed from the stack\r
+ - all page register still contain the same value\r
+ --------------------------- _STORE_FAR_32 ----------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+#endif\r
+#pragma NO_ENTRY\r
+#pragma NO_EXIT\r
+#pragma NO_FRAME\r
+\r
+void NEAR _STORE_FAR_32(void) {\r
+#if USE_SEVERAL_PAGES\r
+ asm {\r
+ PSHX ; save X register\r
+ __PIC_JSR(_GET_PAGE_REG)\r
+ BEQ L_NOPAGE\r
+\r
+ PSHD\r
+ LDAA 0,X ; save page register\r
+ MOVB 6,SP, 0,X ; set page register\r
+ MOVW 2,SP, 0,Y ; store the value passed in X (high word)\r
+ MOVW 0,SP, 2,Y ; store the value passed in D (low word)\r
+ STAA 0,X ; restore page register\r
+ PULD ; restore A register\r
+ BRA done\r
+\r
+L_NOPAGE:\r
+ MOVW 0,SP, 0,Y ; store the value passed in X (high word)\r
+ STD 2,Y ; store the value passed in D (low word)\r
+done:\r
+ PULX ; restore X register\r
+ MOVW 0,SP, 1,+SP ; move return address\r
+ RTS\r
+ }\r
+#else /* USE_SEVERAL_PAGES */\r
+ asm {\r
+ PSHD ; save D register\r
+ LDAA PAGE_ADDR ; save page register\r
+ LDAB 4,SP ; load page part of address\r
+ STAB PAGE_ADDR ; set page register\r
+ STX 0,Y ; store the value passed in X\r
+ MOVW 0,SP, 2,Y ; store the value passed in D (low word)\r
+ STAA PAGE_ADDR ; restore page register\r
+ PULD ; restore D register\r
+ MOVW 0,SP, 1,+SP ; move return address\r
+ RTS\r
+ }\r
+#endif /* USE_SEVERAL_PAGES */\r
+}\r
+\r
+/*--------------------------- _FAR_COPY --------------------------------\r
+ This runtime routine is used to access paged memory via a runtime function.\r
+ It may also be used if the compiler option -Cp is not used with the runtime argument.\r
+\r
+ Arguments :\r
+ - offset part of the source int the X register\r
+ - page part of the source in the A register\r
+ - offset part of the dest int the Y register\r
+ - page part of the dest in the B register\r
+ - number of bytes to be copied at 2,SP. The number of bytes is always > 0\r
+\r
+ Result :\r
+ - memory area copied\r
+ - no registers are saved, i.e. all registers may be destroied\r
+ - all page register still contain the same value\r
+\r
+\r
+ stack-structure at the loop-label:\r
+ 0,SP : destination offset\r
+ 2,SP : source page\r
+ 3,SP : destination page\r
+ 4,SP : source offset\r
+ 6,SP : return address\r
+ 8,SP : counter, > 0\r
+ --------------------------- _FAR_COPY ----------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+#endif\r
+#pragma NO_ENTRY\r
+#pragma NO_EXIT\r
+#pragma NO_FRAME\r
+\r
+void NEAR _FAR_COPY(void) {\r
+#if USE_SEVERAL_PAGES\r
+ asm {\r
+ DEX ; source addr-=1, because loop counter ends at 1\r
+ PSHX ; save source offset\r
+ PSHD ; save both pages\r
+ DEY ; destination addr-=1, because loop counter ends at 1\r
+ PSHY ; save destination offset\r
+ LDX 8,SP ; load counter, assuming counter > 0\r
+\r
+loop:\r
+ LDD 4,SP ; load source offset\r
+ LEAY D,X ; calcutate actual source address\r
+ LDAB 2,SP ; load source page\r
+ __PIC_JSR (_LOAD_FAR_8); load 1 source byte\r
+ PSHB ; save value\r
+ LDD 0+1,SP ; load destination offset\r
+ LEAY D,X ; calcutate acual destination address\r
+ PULA ; restore value\r
+ LDAB 3,SP ; load destination page\r
+ __PIC_JSR (_STORE_FAR_8); store one byte\r
+ DEX\r
+ BNE loop\r
+ LDX 6,SP ; load return address\r
+ LEAS 10,SP ; release stack\r
+ JMP 0,X ; return\r
+ }\r
+#else\r
+ asm {\r
+ PSHD ; store page registers\r
+ TFR X,D\r
+ ADDD 4,SP ; calculate source end address\r
+ STD 4,SP\r
+ PULB ; reload source page\r
+ LDAA PAGE_ADDR ; save page register\r
+ PSHA\r
+loop:\r
+ STAB PAGE_ADDR ; set source page\r
+ LDAA 1,X+ ; load value\r
+ MOVB 1,SP, PAGE_ADDR ; set destination page\r
+ STAA 1,Y+\r
+ CPX 4,SP\r
+ BNE loop\r
+\r
+ LDAA 2,SP+ ; restore old page value and release stack\r
+ STAA PAGE_ADDR ; store it into page register\r
+ LDX 4,SP+ ; release stack and load return address\r
+ JMP 0,X ; return\r
+ }\r
+#endif\r
+}\r
+\r
--- /dev/null
+\r
+PROGRAM "E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior_small\bin\Simulator.abs"\r
+\r
+*********************************************************************************************\r
+TARGET SECTION\r
+---------------------------------------------------------------------------------------------\r
+Processor : Motorola HC12\r
+Memory Model: SMALL\r
+File Format : ELF\Dwarf 2.0\r
+Linker : SmartLinker V-5.0.22 Build 4047, Feb 17 2004\r
+\r
+*********************************************************************************************\r
+FILE SECTION\r
+---------------------------------------------------------------------------------------------\r
+Start12.c.o Model: SMALL, Lang: ANSI-C\r
+STRING.C.o (ansisi.lib) Model: SMALL, Lang: ANSI-C\r
+rtshc12.c.o (ansisi.lib) Model: SMALL, Lang: ANSI-C\r
+Cpu.C.o Model: SMALL, Lang: ANSI-C\r
+Byte1.C.o Model: SMALL, Lang: ANSI-C\r
+IO_Map.C.o Model: SMALL, Lang: ANSI-C\r
+Vectors.c.o Model: SMALL, Lang: ANSI-C\r
+RTOSDemo.C.o Model: SMALL, Lang: ANSI-C\r
+tasks.c.o Model: SMALL, Lang: ANSI-C\r
+queue.c.o Model: SMALL, Lang: ANSI-C\r
+list.c.o Model: SMALL, Lang: ANSI-C\r
+port.c.o Model: SMALL, Lang: ANSI-C\r
+flash.c.o Model: SMALL, Lang: ANSI-C\r
+main.c.o Model: SMALL, Lang: ANSI-C\r
+heap_1.c.o Model: SMALL, Lang: ANSI-C\r
+TickTimer.C.o Model: SMALL, Lang: ANSI-C\r
+PE_Timer.C.o Model: SMALL, Lang: ANSI-C\r
+ParTest.c.o Model: SMALL, Lang: ANSI-C\r
+PollQ.c.o Model: SMALL, Lang: ANSI-C\r
+dynamic.c.o Model: SMALL, Lang: ANSI-C\r
+ButtonInterrupt.C.o Model: SMALL, Lang: ANSI-C\r
+\r
+*********************************************************************************************\r
+STARTUP SECTION\r
+---------------------------------------------------------------------------------------------\r
+Entry point: 0xC000 (_EntryPoint)\r
+_startupData is allocated at 0xC076 and uses 23 Bytes\r
+extern struct _tagStartup {\r
+ unsigned flags 0\r
+ _PFunc main 0xC1FD (main)\r
+ long stackOffset 0xFED\r
+ unsigned nofZeroOut 1\r
+ _Range pZeroOut 0x800 1982\r
+ _Copy *toCopyDownBeg 0xD3CF\r
+ int nofLibInits 0\r
+ _LibInit *libInits 0xC091\r
+ int nofInitBodies 0\r
+ _Cpp *initBodies 0xC093\r
+ int nofFiniBodies 0\r
+ _Cpp *finiBodies 0xC093\r
+} _startupData;\r
+\r
+*********************************************************************************************\r
+SECTION-ALLOCATION SECTION\r
+Section Name Size Type From To Segment\r
+---------------------------------------------------------------------------------------------\r
+.data 1 R/W 0x800 0x800 RAM\r
+.init 118 R 0xC000 0xC075 ROM_C000\r
+.startData 29 R 0xC076 0xC092 ROM_C000\r
+.rodata1 78 R 0xC093 0xC0E0 ROM_C000\r
+NON_BANKED 114 R 0xC0E1 0xC152 ROM_C000\r
+.text 4164 R 0xC153 0xD196 ROM_C000\r
+.copy 19 R 0xD3CF 0xD3E1 ROM_C000\r
+.abs_section_3f 1 N/I 0x3F 0x3F .absSeg0\r
+.abs_section_8d 1 N/I 0x8D 0x8D .absSeg1\r
+.abs_section_86 1 N/I 0x86 0x86 .absSeg2\r
+.abs_section_8b 1 N/I 0x8B 0x8B .absSeg3\r
+.abs_section_ff06 1 N/I 0xFF06 0xFF06 .absSeg4\r
+.abs_section_ff07 1 N/I 0xFF07 0xFF07 .absSeg5\r
+.abs_section_ff01 1 N/I 0xFF01 0xFF01 .absSeg6\r
+.abs_section_2b 1 N/I 0x2B 0x2B .absSeg7\r
+.abs_section_2c 1 N/I 0x2C 0x2C .absSeg8\r
+.abs_section_2a 1 N/I 0x2A 0x2A .absSeg9\r
+.abs_section_2e 1 N/I 0x2E 0x2E .absSeg10\r
+.abs_section_2f 1 N/I 0x2F 0x2F .absSeg11\r
+.abs_section_2d 1 N/I 0x2D 0x2D .absSeg12\r
+.abs_section_28 1 N/I 0x28 0x28 .absSeg13\r
+.abs_section_29 1 N/I 0x29 0x29 .absSeg14\r
+.abs_section_142 1 N/I 0x142 0x142 .absSeg15\r
+.abs_section_143 1 N/I 0x143 0x143 .absSeg16\r
+.abs_section_140 1 N/I 0x140 0x140 .absSeg17\r
+.abs_section_141 1 N/I 0x141 0x141 .absSeg18\r
+.abs_section_14b 1 N/I 0x14B 0x14B .absSeg19\r
+.abs_section_150 1 N/I 0x150 0x150 .absSeg20\r
+.abs_section_151 1 N/I 0x151 0x151 .absSeg21\r
+.abs_section_152 1 N/I 0x152 0x152 .absSeg22\r
+.abs_section_153 1 N/I 0x153 0x153 .absSeg23\r
+.abs_section_158 1 N/I 0x158 0x158 .absSeg24\r
+.abs_section_159 1 N/I 0x159 0x159 .absSeg25\r
+.abs_section_15a 1 N/I 0x15A 0x15A .absSeg26\r
+.abs_section_15b 1 N/I 0x15B 0x15B .absSeg27\r
+.abs_section_154 1 N/I 0x154 0x154 .absSeg28\r
+.abs_section_155 1 N/I 0x155 0x155 .absSeg29\r
+.abs_section_156 1 N/I 0x156 0x156 .absSeg30\r
+.abs_section_157 1 N/I 0x157 0x157 .absSeg31\r
+.abs_section_15c 1 N/I 0x15C 0x15C .absSeg32\r
+.abs_section_15d 1 N/I 0x15D 0x15D .absSeg33\r
+.abs_section_15e 1 N/I 0x15E 0x15E .absSeg34\r
+.abs_section_15f 1 N/I 0x15F 0x15F .absSeg35\r
+.abs_section_144 1 N/I 0x144 0x144 .absSeg36\r
+.abs_section_145 1 N/I 0x145 0x145 .absSeg37\r
+.abs_section_16c 1 N/I 0x16C 0x16C .absSeg38\r
+.abs_section_164 1 N/I 0x164 0x164 .absSeg39\r
+.abs_section_165 1 N/I 0x165 0x165 .absSeg40\r
+.abs_section_166 1 N/I 0x166 0x166 .absSeg41\r
+.abs_section_167 1 N/I 0x167 0x167 .absSeg42\r
+.abs_section_168 1 N/I 0x168 0x168 .absSeg43\r
+.abs_section_169 1 N/I 0x169 0x169 .absSeg44\r
+.abs_section_16a 1 N/I 0x16A 0x16A .absSeg45\r
+.abs_section_16b 1 N/I 0x16B 0x16B .absSeg46\r
+.abs_section_14e 1 N/I 0x14E 0x14E .absSeg47\r
+.abs_section_160 1 N/I 0x160 0x160 .absSeg48\r
+.abs_section_161 1 N/I 0x161 0x161 .absSeg49\r
+.abs_section_162 1 N/I 0x162 0x162 .absSeg50\r
+.abs_section_163 1 N/I 0x163 0x163 .absSeg51\r
+.abs_section_149 1 N/I 0x149 0x149 .absSeg52\r
+.abs_section_148 1 N/I 0x148 0x148 .absSeg53\r
+.abs_section_14a 1 N/I 0x14A 0x14A .absSeg54\r
+.abs_section_146 1 N/I 0x146 0x146 .absSeg55\r
+.abs_section_147 1 N/I 0x147 0x147 .absSeg56\r
+.abs_section_17c 1 N/I 0x17C 0x17C .absSeg57\r
+.abs_section_174 1 N/I 0x174 0x174 .absSeg58\r
+.abs_section_175 1 N/I 0x175 0x175 .absSeg59\r
+.abs_section_176 1 N/I 0x176 0x176 .absSeg60\r
+.abs_section_177 1 N/I 0x177 0x177 .absSeg61\r
+.abs_section_178 1 N/I 0x178 0x178 .absSeg62\r
+.abs_section_179 1 N/I 0x179 0x179 .absSeg63\r
+.abs_section_17a 1 N/I 0x17A 0x17A .absSeg64\r
+.abs_section_17b 1 N/I 0x17B 0x17B .absSeg65\r
+.abs_section_14f 1 N/I 0x14F 0x14F .absSeg66\r
+.abs_section_170 1 N/I 0x170 0x170 .absSeg67\r
+.abs_section_171 1 N/I 0x171 0x171 .absSeg68\r
+.abs_section_172 1 N/I 0x172 0x172 .absSeg69\r
+.abs_section_173 1 N/I 0x173 0x173 .absSeg70\r
+.abs_section_17f 1 N/I 0x17F 0x17F .absSeg71\r
+.abs_section_41 1 N/I 0x41 0x41 .absSeg72\r
+.abs_section_39 1 N/I 0x39 0x39 .absSeg73\r
+.abs_section_3c 1 N/I 0x3C 0x3C .absSeg74\r
+.abs_section_37 1 N/I 0x37 0x37 .absSeg75\r
+.abs_section_38 1 N/I 0x38 0x38 .absSeg76\r
+.abs_section_3e 1 N/I 0x3E 0x3E .absSeg77\r
+.abs_section_36 1 N/I 0x36 0x36 .absSeg78\r
+.abs_section_272 1 N/I 0x272 0x272 .absSeg79\r
+.abs_section_9 1 N/I 0x9 0x9 .absSeg80\r
+.abs_section_26a 1 N/I 0x26A 0x26A .absSeg81\r
+.abs_section_33 1 N/I 0x33 0x33 .absSeg82\r
+.abs_section_252 1 N/I 0x252 0x252 .absSeg83\r
+.abs_section_25a 1 N/I 0x25A 0x25A .absSeg84\r
+.abs_section_24a 1 N/I 0x24A 0x24A .absSeg85\r
+.abs_section_242 1 N/I 0x242 0x242 .absSeg86\r
+.abs_section_e 1 N/I 0xE 0xE .absSeg87\r
+.abs_section_100 1 N/I 0x100 0x100 .absSeg88\r
+.abs_section_106 1 N/I 0x106 0x106 .absSeg89\r
+.abs_section_103 1 N/I 0x103 0x103 .absSeg90\r
+.abs_section_104 1 N/I 0x104 0x104 .absSeg91\r
+.abs_section_101 1 N/I 0x101 0x101 .absSeg92\r
+.abs_section_105 1 N/I 0x105 0x105 .absSeg93\r
+.abs_section_1f 1 N/I 0x1F 0x1F .absSeg94\r
+.abs_section_12 1 N/I 0x12 0x12 .absSeg95\r
+.abs_section_11 1 N/I 0x11 0x11 .absSeg96\r
+.abs_section_10 1 N/I 0x10 0x10 .absSeg97\r
+.abs_section_1e 1 N/I 0x1E 0x1E .absSeg98\r
+.abs_section_15 1 N/I 0x15 0x15 .absSeg99\r
+.abs_section_16 1 N/I 0x16 0x16 .absSeg100\r
+.abs_section_1c 1 N/I 0x1C 0x1C .absSeg101\r
+.abs_section_1d 1 N/I 0x1D 0x1D .absSeg102\r
+.abs_section_13 1 N/I 0x13 0x13 .absSeg103\r
+.abs_section_b 1 N/I 0xB 0xB .absSeg104\r
+.abs_section_247 1 N/I 0x247 0x247 .absSeg105\r
+.abs_section_14 1 N/I 0x14 0x14 .absSeg106\r
+.abs_section_17 1 N/I 0x17 0x17 .absSeg107\r
+.abs_section_43 1 N/I 0x43 0x43 .absSeg108\r
+.abs_section_42 1 N/I 0x42 0x42 .absSeg109\r
+.abs_section_60 1 N/I 0x60 0x60 .absSeg110\r
+.abs_section_61 1 N/I 0x61 0x61 .absSeg111\r
+.abs_section_1a 1 N/I 0x1A 0x1A .absSeg112\r
+.abs_section_1b 1 N/I 0x1B 0x1B .absSeg113\r
+.abs_section_a 1 N/I 0xA 0xA .absSeg114\r
+.abs_section_274 1 N/I 0x274 0x274 .absSeg115\r
+.abs_section_26c 1 N/I 0x26C 0x26C .absSeg116\r
+.abs_section_254 1 N/I 0x254 0x254 .absSeg117\r
+.abs_section_25c 1 N/I 0x25C 0x25C .absSeg118\r
+.abs_section_24c 1 N/I 0x24C 0x24C .absSeg119\r
+.abs_section_244 1 N/I 0x244 0x244 .absSeg120\r
+.abs_section_26e 1 N/I 0x26E 0x26E .absSeg121\r
+.abs_section_25e 1 N/I 0x25E 0x25E .absSeg122\r
+.abs_section_26f 1 N/I 0x26F 0x26F .absSeg123\r
+.abs_section_25f 1 N/I 0x25F 0x25F .absSeg124\r
+.abs_section_3a 1 N/I 0x3A 0x3A .absSeg125\r
+.abs_section_8f 1 N/I 0x8F 0x8F .absSeg126\r
+.abs_section_8 1 N/I 0x8 0x8 .absSeg127\r
+.abs_section_32 1 N/I 0x32 0x32 .absSeg128\r
+.abs_section_30 1 N/I 0x30 0x30 .absSeg129\r
+.abs_section_275 1 N/I 0x275 0x275 .absSeg130\r
+.abs_section_26d 1 N/I 0x26D 0x26D .absSeg131\r
+.abs_section_255 1 N/I 0x255 0x255 .absSeg132\r
+.abs_section_25d 1 N/I 0x25D 0x25D .absSeg133\r
+.abs_section_24d 1 N/I 0x24D 0x24D .absSeg134\r
+.abs_section_245 1 N/I 0x245 0x245 .absSeg135\r
+.abs_section_270 1 N/I 0x270 0x270 .absSeg136\r
+.abs_section_271 1 N/I 0x271 0x271 .absSeg137\r
+.abs_section_269 1 N/I 0x269 0x269 .absSeg138\r
+.abs_section_251 1 N/I 0x251 0x251 .absSeg139\r
+.abs_section_259 1 N/I 0x259 0x259 .absSeg140\r
+.abs_section_249 1 N/I 0x249 0x249 .absSeg141\r
+.abs_section_241 1 N/I 0x241 0x241 .absSeg142\r
+.abs_section_268 1 N/I 0x268 0x268 .absSeg143\r
+.abs_section_250 1 N/I 0x250 0x250 .absSeg144\r
+.abs_section_258 1 N/I 0x258 0x258 .absSeg145\r
+.abs_section_248 1 N/I 0x248 0x248 .absSeg146\r
+.abs_section_240 1 N/I 0x240 0x240 .absSeg147\r
+.abs_section_c 1 N/I 0xC 0xC .absSeg148\r
+.abs_section_e4 1 N/I 0xE4 0xE4 .absSeg149\r
+.abs_section_e2 1 N/I 0xE2 0xE2 .absSeg150\r
+.abs_section_e5 1 N/I 0xE5 0xE5 .absSeg151\r
+.abs_section_e0 1 N/I 0xE0 0xE0 .absSeg152\r
+.abs_section_e1 1 N/I 0xE1 0xE1 .absSeg153\r
+.abs_section_e3 1 N/I 0xE3 0xE3 .absSeg154\r
+.abs_section_e8 1 N/I 0xE8 0xE8 .absSeg155\r
+.abs_section_e9 1 N/I 0xE9 0xE9 .absSeg156\r
+.abs_section_fe 1 N/I 0xFE 0xFE .absSeg157\r
+.abs_section_273 1 N/I 0x273 0x273 .absSeg158\r
+.abs_section_d 1 N/I 0xD 0xD .absSeg159\r
+.abs_section_26b 1 N/I 0x26B 0x26B .absSeg160\r
+.abs_section_253 1 N/I 0x253 0x253 .absSeg161\r
+.abs_section_25b 1 N/I 0x25B 0x25B .absSeg162\r
+.abs_section_24b 1 N/I 0x24B 0x24B .absSeg163\r
+.abs_section_243 1 N/I 0x243 0x243 .absSeg164\r
+.abs_section_35 1 N/I 0x35 0x35 .absSeg165\r
+.abs_section_3b 1 N/I 0x3B 0x3B .absSeg166\r
+.abs_section_ca 1 N/I 0xCA 0xCA .absSeg167\r
+.abs_section_cb 1 N/I 0xCB 0xCB .absSeg168\r
+.abs_section_ce 1 N/I 0xCE 0xCE .absSeg169\r
+.abs_section_cf 1 N/I 0xCF 0xCF .absSeg170\r
+.abs_section_cc 1 N/I 0xCC 0xCC .absSeg171\r
+.abs_section_cd 1 N/I 0xCD 0xCD .absSeg172\r
+.abs_section_da 1 N/I 0xDA 0xDA .absSeg173\r
+.abs_section_d8 1 N/I 0xD8 0xD8 .absSeg174\r
+.abs_section_d9 1 N/I 0xD9 0xD9 .absSeg175\r
+.abs_section_dd 1 N/I 0xDD 0xDD .absSeg176\r
+.abs_section_db 1 N/I 0xDB 0xDB .absSeg177\r
+.abs_section_34 1 N/I 0x34 0x34 .absSeg178\r
+.abs_section_48 1 N/I 0x48 0x48 .absSeg179\r
+.abs_section_49 1 N/I 0x49 0x49 .absSeg180\r
+.abs_section_4a 1 N/I 0x4A 0x4A .absSeg181\r
+.abs_section_4b 1 N/I 0x4B 0x4B .absSeg182\r
+.abs_section_4e 1 N/I 0x4E 0x4E .absSeg183\r
+.abs_section_4f 1 N/I 0x4F 0x4F .absSeg184\r
+.abs_section_4c 1 N/I 0x4C 0x4C .absSeg185\r
+.abs_section_40 1 N/I 0x40 0x40 .absSeg186\r
+.abs_section_46 1 N/I 0x46 0x46 .absSeg187\r
+.abs_section_4d 1 N/I 0x4D 0x4D .absSeg188\r
+.abs_section_47 1 N/I 0x47 0x47 .absSeg189\r
+.abs_section_256 1 N/I 0x256 0x256 .absSeg190\r
+.abs_section_24e 1 N/I 0x24E 0x24E .absSeg191\r
+.abs_section_82 2 N/I 0x82 0x83 .absSeg192\r
+.abs_section_84 2 N/I 0x84 0x85 .absSeg193\r
+.abs_section_90 2 N/I 0x90 0x91 .absSeg194\r
+.abs_section_92 2 N/I 0x92 0x93 .absSeg195\r
+.abs_section_94 2 N/I 0x94 0x95 .absSeg196\r
+.abs_section_96 2 N/I 0x96 0x97 .absSeg197\r
+.abs_section_98 2 N/I 0x98 0x99 .absSeg198\r
+.abs_section_9a 2 N/I 0x9A 0x9B .absSeg199\r
+.abs_section_9c 2 N/I 0x9C 0x9D .absSeg200\r
+.abs_section_9e 2 N/I 0x9E 0x9F .absSeg201\r
+.abs_section_2 2 N/I 0x2 0x3 .absSeg202\r
+.abs_section_62 2 N/I 0x62 0x63 .absSeg203\r
+.abs_section_0 2 N/I 0x0 0x1 .absSeg204\r
+.abs_section_ec 2 N/I 0xEC 0xED .absSeg205\r
+.abs_section_ee 2 N/I 0xEE 0xEF .absSeg206\r
+.abs_section_f0 2 N/I 0xF0 0xF1 .absSeg207\r
+.abs_section_f8 2 N/I 0xF8 0xF9 .absSeg208\r
+.abs_section_fa 2 N/I 0xFA 0xFB .absSeg209\r
+.abs_section_fc 2 N/I 0xFC 0xFD .absSeg210\r
+.abs_section_f2 2 N/I 0xF2 0xF3 .absSeg211\r
+.abs_section_f4 2 N/I 0xF4 0xF5 .absSeg212\r
+.abs_section_f6 2 N/I 0xF6 0xF7 .absSeg213\r
+.abs_section_c8 2 N/I 0xC8 0xC9 .absSeg214\r
+.abs_section_50 2 N/I 0x50 0x51 .absSeg215\r
+.abs_section_52 2 N/I 0x52 0x53 .absSeg216\r
+.abs_section_54 2 N/I 0x54 0x55 .absSeg217\r
+.abs_section_56 2 N/I 0x56 0x57 .absSeg218\r
+.abs_section_58 2 N/I 0x58 0x59 .absSeg219\r
+.abs_section_5a 2 N/I 0x5A 0x5B .absSeg220\r
+.abs_section_5c 2 N/I 0x5C 0x5D .absSeg221\r
+.abs_section_5e 2 N/I 0x5E 0x5F .absSeg222\r
+.abs_section_44 2 N/I 0x44 0x45 .absSeg223\r
+.abs_section_ff80 128 R 0xFF80 0xFFFF .absSeg224\r
+.bss 1968 R/W 0x801 0xFB0 RAM\r
+RUNTIME 373 R 0xD197 0xD30B ROM_C000\r
+.common 2 R/W 0xFB1 0xFB2 RAM\r
+Byte1_CODE 28 R 0xD30C 0xD327 ROM_C000\r
+TickTimer_CODE 157 R 0xD328 0xD3C4 ROM_C000\r
+ButtonInterrupt_CODE 10 R 0xD3C5 0xD3CE ROM_C000\r
+Byte1_DATA 8 R/W 0xFB3 0xFBA RAM\r
+TickTimer_DATA 3 R/W 0xFBB 0xFBD RAM\r
+.stack 48 R/W 0xFBE 0xFED RAM\r
+\r
+Summary of section sizes per section type:\r
+READ_ONLY (R): 1462 (dec: 5218)\r
+READ_WRITE (R/W): 7EE (dec: 2030)\r
+NO_INIT (N/I): 100 (dec: 256)\r
+\r
+*********************************************************************************************\r
+VECTOR-ALLOCATION SECTION\r
+ Address InitValue InitFunction\r
+---------------------------------------------------------------------------------------------\r
+\r
+*********************************************************************************************\r
+OBJECT-ALLOCATION SECTION\r
+ Name Module Addr hSize dSize Ref Section RLIB\r
+---------------------------------------------------------------------------------------------\r
+MODULE: -- Start12.c.o --\r
+- PROCEDURES:\r
+ Init C153 29 41 1 .text \r
+ _Startup C17C 10 16 1 .text \r
+- VARIABLES:\r
+ _startupData C076 17 23 6 .startData \r
+MODULE: -- STRING.C.o (ansisi.lib) --\r
+- PROCEDURES:\r
+ memcpy C18C 26 38 3 .text \r
+ memset C1B2 1E 30 1 .text \r
+ strncpy C1D0 2D 45 1 .text \r
+- VARIABLES:\r
+MODULE: -- rtshc12.c.o (ansisi.lib) --\r
+- PROCEDURES:\r
+ _LCMP D197 19 25 2 RUNTIME \r
+ _LCMP_P D1B0 15 21 2 RUNTIME \r
+ _LNEG D1C5 D 13 1 RUNTIME \r
+ _LINC D1D2 5 5 4 RUNTIME \r
+ _lDivMod D1D7 E3 227 3 RUNTIME \r
+ _LDIVU D2BA E 14 1 RUNTIME \r
+ _NEG_P D2C8 F 15 4 RUNTIME \r
+ _LDIVS D2D7 35 53 1 RUNTIME \r
+- VARIABLES:\r
+MODULE: -- Cpu.C.o --\r
+- PROCEDURES:\r
+ _EntryPoint C000 2E 46 1 .init \r
+ PE_low_level_init C02E 48 72 1 .init \r
+ Cpu_Interrupt C0E1 1 1 60 NON_BANKED \r
+- VARIABLES:\r
+MODULE: -- Byte1.C.o --\r
+- PROCEDURES:\r
+ Byte1_GetMsk D30C D 13 1 Byte1_CODE \r
+ Byte1_NegBit D319 F 15 1 Byte1_CODE \r
+- VARIABLES:\r
+ Byte1_Table FB3 8 8 1 Byte1_DATA \r
+MODULE: -- IO_Map.C.o --\r
+- PROCEDURES:\r
+- VARIABLES:\r
+ _ARMCOP 3F 1 1 0 .abs_section_3f\r
+ _ATDDIEN 8D 1 1 0 .abs_section_8d\r
+ _ATDSTAT0 86 1 1 0 .abs_section_86\r
+ _ATDSTAT1 8B 1 1 0 .abs_section_8b\r
+ _BDMCCR FF06 1 1 0 .abs_section_ff06\r
+ _BDMINR FF07 1 1 0 .abs_section_ff07\r
+ _BDMSTS FF01 1 1 0 .abs_section_ff01\r
+ _BKP0H 2B 1 1 0 .abs_section_2b\r
+ _BKP0L 2C 1 1 0 .abs_section_2c\r
+ _BKP0X 2A 1 1 0 .abs_section_2a\r
+ _BKP1H 2E 1 1 0 .abs_section_2e\r
+ _BKP1L 2F 1 1 0 .abs_section_2f\r
+ _BKP1X 2D 1 1 0 .abs_section_2d\r
+ _BKPCT0 28 1 1 0 .abs_section_28\r
+ _BKPCT1 29 1 1 0 .abs_section_29\r
+ _CANBTR0 142 1 1 0 .abs_section_142\r
+ _CANBTR1 143 1 1 0 .abs_section_143\r
+ _CANCTL0 140 1 1 0 .abs_section_140\r
+ _CANCTL1 141 1 1 0 .abs_section_141\r
+ _CANIDAC 14B 1 1 0 .abs_section_14b\r
+ _CANIDAR0 150 1 1 0 .abs_section_150\r
+ _CANIDAR1 151 1 1 0 .abs_section_151\r
+ _CANIDAR2 152 1 1 0 .abs_section_152\r
+ _CANIDAR3 153 1 1 0 .abs_section_153\r
+ _CANIDAR4 158 1 1 0 .abs_section_158\r
+ _CANIDAR5 159 1 1 0 .abs_section_159\r
+ _CANIDAR6 15A 1 1 0 .abs_section_15a\r
+ _CANIDAR7 15B 1 1 0 .abs_section_15b\r
+ _CANIDMR0 154 1 1 0 .abs_section_154\r
+ _CANIDMR1 155 1 1 0 .abs_section_155\r
+ _CANIDMR2 156 1 1 0 .abs_section_156\r
+ _CANIDMR3 157 1 1 0 .abs_section_157\r
+ _CANIDMR4 15C 1 1 0 .abs_section_15c\r
+ _CANIDMR5 15D 1 1 0 .abs_section_15d\r
+ _CANIDMR6 15E 1 1 0 .abs_section_15e\r
+ _CANIDMR7 15F 1 1 0 .abs_section_15f\r
+ _CANRFLG 144 1 1 0 .abs_section_144\r
+ _CANRIER 145 1 1 0 .abs_section_145\r
+ _CANRXDLR 16C 1 1 0 .abs_section_16c\r
+ _CANRXDSR0 164 1 1 0 .abs_section_164\r
+ _CANRXDSR1 165 1 1 0 .abs_section_165\r
+ _CANRXDSR2 166 1 1 0 .abs_section_166\r
+ _CANRXDSR3 167 1 1 0 .abs_section_167\r
+ _CANRXDSR4 168 1 1 0 .abs_section_168\r
+ _CANRXDSR5 169 1 1 0 .abs_section_169\r
+ _CANRXDSR6 16A 1 1 0 .abs_section_16a\r
+ _CANRXDSR7 16B 1 1 0 .abs_section_16b\r
+ _CANRXERR 14E 1 1 0 .abs_section_14e\r
+ _CANRXIDR0 160 1 1 0 .abs_section_160\r
+ _CANRXIDR1 161 1 1 0 .abs_section_161\r
+ _CANRXIDR2 162 1 1 0 .abs_section_162\r
+ _CANRXIDR3 163 1 1 0 .abs_section_163\r
+ _CANTAAK 149 1 1 0 .abs_section_149\r
+ _CANTARQ 148 1 1 0 .abs_section_148\r
+ _CANTBSEL 14A 1 1 0 .abs_section_14a\r
+ _CANTFLG 146 1 1 0 .abs_section_146\r
+ _CANTIER 147 1 1 0 .abs_section_147\r
+ _CANTXDLR 17C 1 1 0 .abs_section_17c\r
+ _CANTXDSR0 174 1 1 0 .abs_section_174\r
+ _CANTXDSR1 175 1 1 0 .abs_section_175\r
+ _CANTXDSR2 176 1 1 0 .abs_section_176\r
+ _CANTXDSR3 177 1 1 0 .abs_section_177\r
+ _CANTXDSR4 178 1 1 0 .abs_section_178\r
+ _CANTXDSR5 179 1 1 0 .abs_section_179\r
+ _CANTXDSR6 17A 1 1 0 .abs_section_17a\r
+ _CANTXDSR7 17B 1 1 0 .abs_section_17b\r
+ _CANTXERR 14F 1 1 0 .abs_section_14f\r
+ _CANTXIDR0 170 1 1 0 .abs_section_170\r
+ _CANTXIDR1 171 1 1 0 .abs_section_171\r
+ _CANTXIDR2 172 1 1 0 .abs_section_172\r
+ _CANTXIDR3 173 1 1 0 .abs_section_173\r
+ _CANTXTBPR 17F 1 1 0 .abs_section_17f\r
+ _CFORC 41 1 1 0 .abs_section_41\r
+ _CLKSEL 39 1 1 3 .abs_section_39\r
+ _COPCTL 3C 1 1 0 .abs_section_3c\r
+ _CRGFLG 37 1 1 1 .abs_section_37\r
+ _CRGINT 38 1 1 0 .abs_section_38\r
+ _CTCTL 3E 1 1 0 .abs_section_3e\r
+ _CTFLG 36 1 1 0 .abs_section_36\r
+ _DDRAD 272 1 1 0 .abs_section_272\r
+ _DDRE 9 1 1 0 .abs_section_9\r
+ _DDRJ 26A 1 1 0 .abs_section_26a\r
+ _DDRK 33 1 1 0 .abs_section_33\r
+ _DDRM 252 1 1 0 .abs_section_252\r
+ _DDRP 25A 1 1 1 .abs_section_25a\r
+ _DDRS 24A 1 1 0 .abs_section_24a\r
+ _DDRT 242 1 1 0 .abs_section_242\r
+ _EBICTL E 1 1 0 .abs_section_e\r
+ _FCLKDIV 100 1 1 0 .abs_section_100\r
+ _FCMD 106 1 1 0 .abs_section_106\r
+ _FCNFG 103 1 1 0 .abs_section_103\r
+ _FPROT 104 1 1 0 .abs_section_104\r
+ _FSEC 101 1 1 0 .abs_section_101\r
+ _FSTAT 105 1 1 0 .abs_section_105\r
+ _HPRIO 1F 1 1 0 .abs_section_1f\r
+ _INITEE 12 1 1 0 .abs_section_12\r
+ _INITRG 11 1 1 0 .abs_section_11\r
+ _INITRM 10 1 1 1 .abs_section_10\r
+ _INTCR 1E 1 1 1 .abs_section_1e\r
+ _ITCR 15 1 1 0 .abs_section_15\r
+ _ITEST 16 1 1 0 .abs_section_16\r
+ _MEMSIZ0 1C 1 1 0 .abs_section_1c\r
+ _MEMSIZ1 1D 1 1 0 .abs_section_1d\r
+ _MISC 13 1 1 1 .abs_section_13\r
+ _MODE B 1 1 0 .abs_section_b\r
+ _MODRR 247 1 1 0 .abs_section_247\r
+ _MTST0 14 1 1 0 .abs_section_14\r
+ _MTST1 17 1 1 0 .abs_section_17\r
+ _OC7D 43 1 1 0 .abs_section_43\r
+ _OC7M 42 1 1 0 .abs_section_42\r
+ _PACTL 60 1 1 0 .abs_section_60\r
+ _PAFLG 61 1 1 0 .abs_section_61\r
+ _PARTIDH 1A 1 1 0 .abs_section_1a\r
+ _PARTIDL 1B 1 1 0 .abs_section_1b\r
+ _PEAR A 1 1 0 .abs_section_a\r
+ _PERAD 274 1 1 0 .abs_section_274\r
+ _PERJ 26C 1 1 0 .abs_section_26c\r
+ _PERM 254 1 1 0 .abs_section_254\r
+ _PERP 25C 1 1 1 .abs_section_25c\r
+ _PERS 24C 1 1 0 .abs_section_24c\r
+ _PERT 244 1 1 0 .abs_section_244\r
+ _PIEJ 26E 1 1 0 .abs_section_26e\r
+ _PIEP 25E 1 1 2 .abs_section_25e\r
+ _PIFJ 26F 1 1 0 .abs_section_26f\r
+ _PIFP 25F 1 1 2 .abs_section_25f\r
+ _PLLCTL 3A 1 1 3 .abs_section_3a\r
+ _PORTAD0 8F 1 1 0 .abs_section_8f\r
+ _PORTE 8 1 1 0 .abs_section_8\r
+ _PORTK 32 1 1 0 .abs_section_32\r
+ _PPAGE 30 1 1 0 .abs_section_30\r
+ _PPSAD 275 1 1 0 .abs_section_275\r
+ _PPSJ 26D 1 1 0 .abs_section_26d\r
+ _PPSM 255 1 1 0 .abs_section_255\r
+ _PPSP 25D 1 1 1 .abs_section_25d\r
+ _PPSS 24D 1 1 0 .abs_section_24d\r
+ _PPST 245 1 1 0 .abs_section_245\r
+ _PTAD 270 1 1 0 .abs_section_270\r
+ _PTIAD 271 1 1 0 .abs_section_271\r
+ _PTIJ 269 1 1 0 .abs_section_269\r
+ _PTIM 251 1 1 0 .abs_section_251\r
+ _PTIP 259 1 1 0 .abs_section_259\r
+ _PTIS 249 1 1 0 .abs_section_249\r
+ _PTIT 241 1 1 0 .abs_section_241\r
+ _PTJ 268 1 1 0 .abs_section_268\r
+ _PTM 250 1 1 0 .abs_section_250\r
+ _PTP 258 1 1 0 .abs_section_258\r
+ _PTS 248 1 1 0 .abs_section_248\r
+ _PTT 240 1 1 0 .abs_section_240\r
+ _PUCR C 1 1 0 .abs_section_c\r
+ _PWMCAE E4 1 1 0 .abs_section_e4\r
+ _PWMCLK E2 1 1 0 .abs_section_e2\r
+ _PWMCTL E5 1 1 1 .abs_section_e5\r
+ _PWME E0 1 1 0 .abs_section_e0\r
+ _PWMPOL E1 1 1 0 .abs_section_e1\r
+ _PWMPRCLK E3 1 1 0 .abs_section_e3\r
+ _PWMSCLA E8 1 1 0 .abs_section_e8\r
+ _PWMSCLB E9 1 1 0 .abs_section_e9\r
+ _PWMSDN FE 1 1 1 .abs_section_fe\r
+ _RDRAD 273 1 1 0 .abs_section_273\r
+ _RDRIV D 1 1 0 .abs_section_d\r
+ _RDRJ 26B 1 1 0 .abs_section_26b\r
+ _RDRM 253 1 1 0 .abs_section_253\r
+ _RDRP 25B 1 1 0 .abs_section_25b\r
+ _RDRS 24B 1 1 0 .abs_section_24b\r
+ _RDRT 243 1 1 0 .abs_section_243\r
+ _REFDV 35 1 1 1 .abs_section_35\r
+ _RTICTL 3B 1 1 0 .abs_section_3b\r
+ _SCICR1 CA 1 1 0 .abs_section_ca\r
+ _SCICR2 CB 1 1 0 .abs_section_cb\r
+ _SCIDRH CE 1 1 0 .abs_section_ce\r
+ _SCIDRL CF 1 1 0 .abs_section_cf\r
+ _SCISR1 CC 1 1 0 .abs_section_cc\r
+ _SCISR2 CD 1 1 0 .abs_section_cd\r
+ _SPIBR DA 1 1 0 .abs_section_da\r
+ _SPICR1 D8 1 1 0 .abs_section_d8\r
+ _SPICR2 D9 1 1 0 .abs_section_d9\r
+ _SPIDR DD 1 1 0 .abs_section_dd\r
+ _SPISR DB 1 1 0 .abs_section_db\r
+ _SYNR 34 1 1 1 .abs_section_34\r
+ _TCTL1 48 1 1 1 .abs_section_48\r
+ _TCTL2 49 1 1 1 .abs_section_49\r
+ _TCTL3 4A 1 1 0 .abs_section_4a\r
+ _TCTL4 4B 1 1 0 .abs_section_4b\r
+ _TFLG1 4E 1 1 2 .abs_section_4e\r
+ _TFLG2 4F 1 1 0 .abs_section_4f\r
+ _TIE 4C 1 1 3 .abs_section_4c\r
+ _TIOS 40 1 1 1 .abs_section_40\r
+ _TSCR1 46 1 1 3 .abs_section_46\r
+ _TSCR2 4D 1 1 5 .abs_section_4d\r
+ _TTOV 47 1 1 1 .abs_section_47\r
+ _WOMM 256 1 1 0 .abs_section_256\r
+ _WOMS 24E 1 1 0 .abs_section_24e\r
+ _ATDCTL23 82 2 2 0 .abs_section_82\r
+ _ATDCTL45 84 2 2 0 .abs_section_84\r
+ _ATDDR0 90 2 2 0 .abs_section_90\r
+ _ATDDR1 92 2 2 0 .abs_section_92\r
+ _ATDDR2 94 2 2 0 .abs_section_94\r
+ _ATDDR3 96 2 2 0 .abs_section_96\r
+ _ATDDR4 98 2 2 0 .abs_section_98\r
+ _ATDDR5 9A 2 2 0 .abs_section_9a\r
+ _ATDDR6 9C 2 2 0 .abs_section_9c\r
+ _ATDDR7 9E 2 2 0 .abs_section_9e\r
+ _DDRAB 2 2 2 1 .abs_section_2\r
+ _PACNT 62 2 2 0 .abs_section_62\r
+ _PORTAB 0 2 2 3 .abs_section_0\r
+ _PWMCNT01 EC 2 2 0 .abs_section_ec\r
+ _PWMCNT23 EE 2 2 0 .abs_section_ee\r
+ _PWMCNT45 F0 2 2 0 .abs_section_f0\r
+ _PWMDTY01 F8 2 2 0 .abs_section_f8\r
+ _PWMDTY23 FA 2 2 0 .abs_section_fa\r
+ _PWMDTY45 FC 2 2 0 .abs_section_fc\r
+ _PWMPER01 F2 2 2 0 .abs_section_f2\r
+ _PWMPER23 F4 2 2 0 .abs_section_f4\r
+ _PWMPER45 F6 2 2 0 .abs_section_f6\r
+ _SCIBD C8 2 2 0 .abs_section_c8\r
+ _TC0 50 2 2 1 .abs_section_50\r
+ _TC1 52 2 2 0 .abs_section_52\r
+ _TC2 54 2 2 0 .abs_section_54\r
+ _TC3 56 2 2 0 .abs_section_56\r
+ _TC4 58 2 2 0 .abs_section_58\r
+ _TC5 5A 2 2 0 .abs_section_5a\r
+ _TC6 5C 2 2 0 .abs_section_5c\r
+ _TC7 5E 2 2 1 .abs_section_5e\r
+ _TCNT 44 2 2 0 .abs_section_44\r
+MODULE: -- Vectors.c.o --\r
+- PROCEDURES:\r
+- VARIABLES:\r
+ _vect FF80 80 128 0 .abs_section_ff80\r
+MODULE: -- RTOSDemo.C.o --\r
+- PROCEDURES:\r
+ main C1FD 8 8 0 .text \r
+- VARIABLES:\r
+MODULE: -- tasks.c.o --\r
+- PROCEDURES:\r
+ xTaskCreate C205 CE 206 11 .text \r
+ vTaskDelayUntil C2D3 74 116 3 .text \r
+ vTaskDelay C347 46 70 4 .text \r
+ uxTaskPriorityGet C38D 26 38 1 .text \r
+ vTaskPrioritySet C3B3 69 105 2 .text \r
+ vTaskSuspend C41C 44 68 3 .text \r
+ vTaskResume C460 59 89 3 .text \r
+ vTaskStartScheduler C4B9 30 48 1 .text \r
+ vTaskSuspendAll C4E9 13 19 11 .text \r
+ xTaskResumeAll C4FC 9F 159 13 .text \r
+ xTaskGetTickCount C59B 17 23 2 .text \r
+ vTaskIncrementTick C5B2 81 129 2 .text \r
+ vTaskSwitchContext C633 5B 91 3 .text \r
+ vTaskPlaceOnEventList C68E 41 65 2 .text \r
+ xTaskRemoveFromEventList C6CF 6C 108 3 .text \r
+ prvIdleTask C73B 10 16 1 .text \r
+ prvInitialiseTCBVariables C74B 4C 76 1 .text \r
+ prvInitialiseTaskLists C797 3C 60 1 .text \r
+ prvCheckTasksWaitingTermination C7D3 1 1 1 .text \r
+ prvAllocateTCBAndStack C7D4 33 51 1 .text \r
+- VARIABLES:\r
+ STRING.IDLE.2 C093 5 5 1 .rodata1 \r
+ pxCurrentTCB 801 2 2 29 .bss \r
+ uxCurrentNumberOfTasks 803 1 1 3 .bss \r
+ xTickCount 804 2 2 14 .bss \r
+ uxTopUsedPriority 806 1 1 2 .bss \r
+ uxTopReadyPriority 807 1 1 15 .bss \r
+ xSchedulerRunning 808 1 1 3 .bss \r
+ uxSchedulerSuspended 809 1 1 6 .bss \r
+ uxMissedTicks 80A 1 1 4 .bss \r
+ uxTaskNumber.1 80B 1 1 2 .bss \r
+ pxReadyTasksLists 80C 3C 60 11 .bss \r
+ xDelayedTaskList1 848 F 15 2 .bss \r
+ xDelayedTaskList2 857 F 15 2 .bss \r
+ pxDelayedTaskList 866 2 2 8 .bss \r
+ pxOverflowDelayedTaskList 868 2 2 6 .bss \r
+ xPendingReadyList 86A F 15 4 .bss \r
+ xSuspendedTaskList 879 F 15 2 .bss \r
+MODULE: -- queue.c.o --\r
+- PROCEDURES:\r
+ xQueueCreate C807 77 119 3 .text \r
+ xQueueSend C87E CA 202 3 .text \r
+ xQueueSendFromISR C948 54 84 1 .text \r
+ xQueueReceive C99C C4 196 4 .text \r
+ uxQueueMessagesWaiting CA60 1B 27 1 .text \r
+ prvUnlockQueue CA7B 6F 111 4 .text \r
+ prvIsQueueEmpty CAEA 21 33 1 .text \r
+ prvIsQueueFull CB0B 24 36 1 .text \r
+- VARIABLES:\r
+MODULE: -- list.c.o --\r
+- PROCEDURES:\r
+ vListInitialise CB2F 1F 31 7 .text \r
+ vListInitialiseItem CB4E 7 7 3 .text \r
+ vListInsertEnd CB55 27 39 7 .text \r
+ vListInsert CB7C 5A 90 4 .text \r
+ vListRemove CBD6 23 35 13 .text \r
+- VARIABLES:\r
+MODULE: -- port.c.o --\r
+- PROCEDURES:\r
+ pxPortInitialiseStack CBF9 2B 43 1 .text \r
+ prvSetupTimerInterrupt CC24 9 9 1 .text \r
+ xPortStartScheduler CC2D 4 4 1 .text \r
+ xBankedStartScheduler C0E2 F 15 1 NON_BANKED \r
+ vPortYield C0F1 16 22 1 NON_BANKED \r
+ vPortTickInterrupt C107 1D 29 1 NON_BANKED \r
+- VARIABLES:\r
+ uxCriticalNesting 800 1 1 91 .data \r
+MODULE: -- flash.c.o --\r
+- PROCEDURES:\r
+ vStartLEDFlashTasks CC31 26 38 1 .text \r
+ vLEDFlashTask CC57 52 82 1 .text \r
+- VARIABLES:\r
+ STRING.LEDx.1 C098 5 5 1 .rodata1 \r
+ uxFlashTaskNumber 888 1 1 2 .bss \r
+MODULE: -- main.c.o --\r
+- PROCEDURES:\r
+ vMain CCA9 42 66 1 .text \r
+ vErrorChecks CCEB 2F 47 1 .text \r
+ prvCheckOtherTasksAreStillRunning CD1A 23 35 1 .text \r
+ vApplicationIdleHook CD3D 73 115 1 .text \r
+ vButtonTask CDB0 4F 79 1 .text \r
+ vButtonPush C124 2F 47 1 NON_BANKED \r
+- VARIABLES:\r
+ STRING.Check.1 C09D 6 6 1 .rodata1 \r
+ STRING.Button.2 C0A3 7 7 1 .rodata1 \r
+ xLocalError 889 1 1 3 .bss \r
+ uxValToSend.3 88A 1 1 2 .bss \r
+ xButtonQueue 88B 2 2 3 .bss \r
+MODULE: -- heap_1.c.o --\r
+- PROCEDURES:\r
+ pvPortMalloc CDFF 30 48 4 .text \r
+ vPortFree CE2F 1 1 2 .text \r
+- VARIABLES:\r
+ xNextFreeByte 88D 2 2 5 .bss \r
+ xHeap 88F 704 1796 1 .bss \r
+MODULE: -- TickTimer.C.o --\r
+- PROCEDURES:\r
+ SetCV D328 F 15 2 TickTimer_CODE\r
+ SetPV D337 C 12 1 TickTimer_CODE\r
+ HWEnDi D343 11 17 2 TickTimer_CODE\r
+ TickTimer_Enable D354 E 14 1 TickTimer_CODE\r
+ TickTimer_SetFreqHz D362 4F 79 1 TickTimer_CODE\r
+ TickTimer_Init D3B1 14 20 1 TickTimer_CODE\r
+- VARIABLES:\r
+ EnUser FBB 1 1 4 TickTimer_DATA\r
+ CmpHighVal FBC 2 2 2 TickTimer_DATA\r
+MODULE: -- PE_Timer.C.o --\r
+- PROCEDURES:\r
+ PE_Timer_LngHi1 CE30 43 67 1 .text \r
+- VARIABLES:\r
+MODULE: -- ParTest.c.o --\r
+- PROCEDURES:\r
+ vParTestToggleLED CE73 13 19 4 .text \r
+- VARIABLES:\r
+MODULE: -- PollQ.c.o --\r
+- PROCEDURES:\r
+ vStartPolledQueueTasks CE86 40 64 1 .text \r
+ vPolledQueueProducer CEC6 4D 77 1 .text \r
+ vPolledQueueConsumer CF13 59 89 1 .text \r
+ xArePollingQueuesStillRunning CF6C 1D 29 1 .text \r
+- VARIABLES:\r
+ STRING.QConsNB.2 C0AA 8 8 1 .rodata1 \r
+ STRING.QProdNB.3 C0B2 8 8 1 .rodata1 \r
+ xPollingConsumerCount F93 1 1 3 .bss \r
+ xPollingProducerCount F94 1 1 3 .bss \r
+ xPolledQueue.1 F95 2 2 3 .bss \r
+MODULE: -- dynamic.c.o --\r
+- PROCEDURES:\r
+ vStartDynamicPriorityTasks CF89 7C 124 1 .text \r
+ vLimitedIncrementTask D005 21 33 1 .text \r
+ vContinuousIncrementTask D026 30 48 1 .text \r
+ vCounterControlTask D056 98 152 3 .text \r
+ vQueueSendWhenSuspendedTask D0EE 34 52 1 .text \r
+ vQueueReceiveWhenSuspendedTask D122 4E 78 1 .text \r
+ xAreDynamicPriorityTasksStillRunning D170 27 39 1 .text \r
+- VARIABLES:\r
+ STRING.CNT_INC.1 C0BA 8 8 1 .rodata1 \r
+ STRING.LIM_INC.2 C0C2 8 8 1 .rodata1 \r
+ STRING.C_CTRL.3 C0CA 7 7 1 .rodata1 \r
+ STRING.SUSP_TX.4 C0D1 8 8 1 .rodata1 \r
+ STRING.SUSP_RX.5 C0D9 8 8 1 .rodata1 \r
+ usCheckVariable F97 2 2 4 .bss \r
+ xSuspendedQueueSendError F99 1 1 2 .bss \r
+ xSuspendedQueueReceiveError F9A 1 1 3 .bss \r
+ ulValueToSend.6 F9B 4 4 5 .bss \r
+ ulExpectedValue.7 F9F 4 4 6 .bss \r
+ usLastTaskCheck.9 FA3 2 2 2 .bss \r
+ xContinousIncrementHandle FA5 2 2 5 .bss \r
+ xLimitedIncrementHandle FA7 2 2 2 .bss \r
+ ulCounter FA9 4 4 10 .bss \r
+ ulReceivedValue.8 FAD 4 4 3 .bss \r
+ xSuspendedTestQueue FB1 2 2 3 .common \r
+MODULE: -- ButtonInterrupt.C.o --\r
+- PROCEDURES:\r
+ ButtonInterrupt_Enable D3C5 A 10 1 ButtonInterrupt_CODE\r
+- VARIABLES:\r
+\r
+*********************************************************************************************\r
+MODULE STATISTIC\r
+ Name Data Code Const\r
+---------------------------------------------------------------------------------------------\r
+ Start12.c.o 0 57 0\r
+ STRING.C.o (ansisi.lib) 0 113 0\r
+ rtshc12.c.o (ansisi.lib) 0 373 0\r
+ Cpu.C.o 0 119 0\r
+ Byte1.C.o 8 28 0\r
+ IO_Map.C.o 256 0 0\r
+ Vectors.c.o 0 0 128\r
+ RTOSDemo.C.o 0 8 0\r
+ tasks.c.o 135 1538 5\r
+ queue.c.o 0 808 0\r
+ list.c.o 0 202 0\r
+ port.c.o 1 122 0\r
+ flash.c.o 1 120 5\r
+ main.c.o 4 389 13\r
+ heap_1.c.o 1798 49 0\r
+ TickTimer.C.o 3 157 0\r
+ PE_Timer.C.o 0 67 0\r
+ ParTest.c.o 0 19 0\r
+ PollQ.c.o 4 259 16\r
+ dynamic.c.o 28 526 39\r
+ ButtonInterrupt.C.o 0 10 0\r
+ other 48 29 19\r
+\r
+*********************************************************************************************\r
+SECTION USE IN OBJECT-ALLOCATION SECTION\r
+---------------------------------------------------------------------------------------------\r
+SECTION: ".text"\r
+ Init _Startup memcpy memset strncpy main xTaskCreate vTaskDelayUntil \r
+ vTaskDelay uxTaskPriorityGet vTaskPrioritySet vTaskSuspend vTaskResume \r
+ vTaskStartScheduler vTaskSuspendAll xTaskResumeAll xTaskGetTickCount \r
+ vTaskIncrementTick vTaskSwitchContext vTaskPlaceOnEventList \r
+ xTaskRemoveFromEventList prvIdleTask prvInitialiseTCBVariables \r
+ prvInitialiseTaskLists prvCheckTasksWaitingTermination prvAllocateTCBAndStack \r
+ xQueueCreate xQueueSend xQueueSendFromISR xQueueReceive \r
+ uxQueueMessagesWaiting prvUnlockQueue prvIsQueueEmpty prvIsQueueFull \r
+ vListInitialise vListInitialiseItem vListInsertEnd vListInsert vListRemove \r
+ pxPortInitialiseStack prvSetupTimerInterrupt xPortStartScheduler \r
+ vStartLEDFlashTasks vLEDFlashTask vMain vErrorChecks \r
+ prvCheckOtherTasksAreStillRunning vApplicationIdleHook vButtonTask \r
+ pvPortMalloc vPortFree PE_Timer_LngHi1 vParTestToggleLED \r
+ vStartPolledQueueTasks vPolledQueueProducer vPolledQueueConsumer \r
+ xArePollingQueuesStillRunning vStartDynamicPriorityTasks \r
+ vLimitedIncrementTask vContinuousIncrementTask vCounterControlTask \r
+ vQueueSendWhenSuspendedTask vQueueReceiveWhenSuspendedTask \r
+ xAreDynamicPriorityTasksStillRunning \r
+SECTION: ".data"\r
+ uxCriticalNesting \r
+SECTION: ".bss"\r
+ pxCurrentTCB uxCurrentNumberOfTasks xTickCount uxTopUsedPriority \r
+ uxTopReadyPriority xSchedulerRunning uxSchedulerSuspended uxMissedTicks \r
+ uxTaskNumber.1 pxReadyTasksLists xDelayedTaskList1 xDelayedTaskList2 \r
+ pxDelayedTaskList pxOverflowDelayedTaskList xPendingReadyList \r
+ xSuspendedTaskList uxFlashTaskNumber xLocalError uxValToSend.3 xButtonQueue \r
+ xNextFreeByte xHeap xPollingConsumerCount xPollingProducerCount \r
+ xPolledQueue.1 usCheckVariable xSuspendedQueueSendError \r
+ xSuspendedQueueReceiveError ulValueToSend.6 ulExpectedValue.7 \r
+ usLastTaskCheck.9 xContinousIncrementHandle xLimitedIncrementHandle ulCounter \r
+ ulReceivedValue.8 \r
+SECTION: ".init"\r
+ _EntryPoint PE_low_level_init \r
+SECTION: ".rodata1"\r
+ STRING.IDLE.2 STRING.LEDx.1 STRING.Check.1 STRING.Button.2 STRING.QConsNB.2 \r
+ STRING.QProdNB.3 STRING.CNT_INC.1 STRING.LIM_INC.2 STRING.C_CTRL.3 \r
+ STRING.SUSP_TX.4 STRING.SUSP_RX.5 \r
+SECTION: "NON_BANKED"\r
+ Cpu_Interrupt xBankedStartScheduler vPortYield vPortTickInterrupt \r
+ vButtonPush \r
+SECTION: "RUNTIME"\r
+ _LCMP _LCMP_P _LNEG _LINC _lDivMod _LDIVU _NEG_P _LDIVS \r
+SECTION: ".common"\r
+ xSuspendedTestQueue \r
+SECTION: "Byte1_CODE"\r
+ Byte1_GetMsk Byte1_NegBit \r
+SECTION: "TickTimer_CODE"\r
+ SetCV SetPV HWEnDi TickTimer_Enable TickTimer_SetFreqHz TickTimer_Init \r
+SECTION: "ButtonInterrupt_CODE"\r
+ ButtonInterrupt_Enable \r
+SECTION: "Byte1_DATA"\r
+ Byte1_Table \r
+SECTION: ".abs_section_3f"\r
+ _ARMCOP \r
+SECTION: ".abs_section_8d"\r
+ _ATDDIEN \r
+SECTION: ".abs_section_86"\r
+ _ATDSTAT0 \r
+SECTION: ".abs_section_8b"\r
+ _ATDSTAT1 \r
+SECTION: ".abs_section_ff06"\r
+ _BDMCCR \r
+SECTION: ".abs_section_ff07"\r
+ _BDMINR \r
+SECTION: ".abs_section_ff01"\r
+ _BDMSTS \r
+SECTION: ".abs_section_2b"\r
+ _BKP0H \r
+SECTION: ".abs_section_2c"\r
+ _BKP0L \r
+SECTION: ".abs_section_2a"\r
+ _BKP0X \r
+SECTION: ".abs_section_2e"\r
+ _BKP1H \r
+SECTION: ".abs_section_2f"\r
+ _BKP1L \r
+SECTION: ".abs_section_2d"\r
+ _BKP1X \r
+SECTION: ".abs_section_28"\r
+ _BKPCT0 \r
+SECTION: ".abs_section_29"\r
+ _BKPCT1 \r
+SECTION: ".abs_section_142"\r
+ _CANBTR0 \r
+SECTION: ".abs_section_143"\r
+ _CANBTR1 \r
+SECTION: ".abs_section_140"\r
+ _CANCTL0 \r
+SECTION: ".abs_section_141"\r
+ _CANCTL1 \r
+SECTION: ".abs_section_14b"\r
+ _CANIDAC \r
+SECTION: ".abs_section_150"\r
+ _CANIDAR0 \r
+SECTION: ".abs_section_151"\r
+ _CANIDAR1 \r
+SECTION: ".abs_section_152"\r
+ _CANIDAR2 \r
+SECTION: ".abs_section_153"\r
+ _CANIDAR3 \r
+SECTION: ".abs_section_158"\r
+ _CANIDAR4 \r
+SECTION: ".abs_section_159"\r
+ _CANIDAR5 \r
+SECTION: ".abs_section_15a"\r
+ _CANIDAR6 \r
+SECTION: ".abs_section_15b"\r
+ _CANIDAR7 \r
+SECTION: ".abs_section_154"\r
+ _CANIDMR0 \r
+SECTION: ".abs_section_155"\r
+ _CANIDMR1 \r
+SECTION: ".abs_section_156"\r
+ _CANIDMR2 \r
+SECTION: ".abs_section_157"\r
+ _CANIDMR3 \r
+SECTION: ".abs_section_15c"\r
+ _CANIDMR4 \r
+SECTION: ".abs_section_15d"\r
+ _CANIDMR5 \r
+SECTION: ".abs_section_15e"\r
+ _CANIDMR6 \r
+SECTION: ".abs_section_15f"\r
+ _CANIDMR7 \r
+SECTION: ".abs_section_144"\r
+ _CANRFLG \r
+SECTION: ".abs_section_145"\r
+ _CANRIER \r
+SECTION: ".abs_section_16c"\r
+ _CANRXDLR \r
+SECTION: ".abs_section_164"\r
+ _CANRXDSR0 \r
+SECTION: ".abs_section_165"\r
+ _CANRXDSR1 \r
+SECTION: ".abs_section_166"\r
+ _CANRXDSR2 \r
+SECTION: ".abs_section_167"\r
+ _CANRXDSR3 \r
+SECTION: ".abs_section_168"\r
+ _CANRXDSR4 \r
+SECTION: ".abs_section_169"\r
+ _CANRXDSR5 \r
+SECTION: ".abs_section_16a"\r
+ _CANRXDSR6 \r
+SECTION: ".abs_section_16b"\r
+ _CANRXDSR7 \r
+SECTION: ".abs_section_14e"\r
+ _CANRXERR \r
+SECTION: ".abs_section_160"\r
+ _CANRXIDR0 \r
+SECTION: ".abs_section_161"\r
+ _CANRXIDR1 \r
+SECTION: ".abs_section_162"\r
+ _CANRXIDR2 \r
+SECTION: ".abs_section_163"\r
+ _CANRXIDR3 \r
+SECTION: ".abs_section_149"\r
+ _CANTAAK \r
+SECTION: ".abs_section_148"\r
+ _CANTARQ \r
+SECTION: ".abs_section_14a"\r
+ _CANTBSEL \r
+SECTION: ".abs_section_146"\r
+ _CANTFLG \r
+SECTION: ".abs_section_147"\r
+ _CANTIER \r
+SECTION: ".abs_section_17c"\r
+ _CANTXDLR \r
+SECTION: ".abs_section_174"\r
+ _CANTXDSR0 \r
+SECTION: ".abs_section_175"\r
+ _CANTXDSR1 \r
+SECTION: ".abs_section_176"\r
+ _CANTXDSR2 \r
+SECTION: ".abs_section_177"\r
+ _CANTXDSR3 \r
+SECTION: ".abs_section_178"\r
+ _CANTXDSR4 \r
+SECTION: ".abs_section_179"\r
+ _CANTXDSR5 \r
+SECTION: ".abs_section_17a"\r
+ _CANTXDSR6 \r
+SECTION: ".abs_section_17b"\r
+ _CANTXDSR7 \r
+SECTION: ".abs_section_14f"\r
+ _CANTXERR \r
+SECTION: ".abs_section_170"\r
+ _CANTXIDR0 \r
+SECTION: ".abs_section_171"\r
+ _CANTXIDR1 \r
+SECTION: ".abs_section_172"\r
+ _CANTXIDR2 \r
+SECTION: ".abs_section_173"\r
+ _CANTXIDR3 \r
+SECTION: ".abs_section_17f"\r
+ _CANTXTBPR \r
+SECTION: ".abs_section_41"\r
+ _CFORC \r
+SECTION: ".abs_section_39"\r
+ _CLKSEL \r
+SECTION: ".abs_section_3c"\r
+ _COPCTL \r
+SECTION: ".abs_section_37"\r
+ _CRGFLG \r
+SECTION: ".abs_section_38"\r
+ _CRGINT \r
+SECTION: ".abs_section_3e"\r
+ _CTCTL \r
+SECTION: ".abs_section_36"\r
+ _CTFLG \r
+SECTION: ".abs_section_272"\r
+ _DDRAD \r
+SECTION: ".abs_section_9"\r
+ _DDRE \r
+SECTION: ".abs_section_26a"\r
+ _DDRJ \r
+SECTION: ".abs_section_33"\r
+ _DDRK \r
+SECTION: ".abs_section_252"\r
+ _DDRM \r
+SECTION: ".abs_section_25a"\r
+ _DDRP \r
+SECTION: ".abs_section_24a"\r
+ _DDRS \r
+SECTION: ".abs_section_242"\r
+ _DDRT \r
+SECTION: ".abs_section_e"\r
+ _EBICTL \r
+SECTION: ".abs_section_100"\r
+ _FCLKDIV \r
+SECTION: ".abs_section_106"\r
+ _FCMD \r
+SECTION: ".abs_section_103"\r
+ _FCNFG \r
+SECTION: ".abs_section_104"\r
+ _FPROT \r
+SECTION: ".abs_section_101"\r
+ _FSEC \r
+SECTION: ".abs_section_105"\r
+ _FSTAT \r
+SECTION: ".abs_section_1f"\r
+ _HPRIO \r
+SECTION: ".abs_section_12"\r
+ _INITEE \r
+SECTION: ".abs_section_11"\r
+ _INITRG \r
+SECTION: ".abs_section_10"\r
+ _INITRM \r
+SECTION: ".abs_section_1e"\r
+ _INTCR \r
+SECTION: ".abs_section_15"\r
+ _ITCR \r
+SECTION: ".abs_section_16"\r
+ _ITEST \r
+SECTION: ".abs_section_1c"\r
+ _MEMSIZ0 \r
+SECTION: ".abs_section_1d"\r
+ _MEMSIZ1 \r
+SECTION: ".abs_section_13"\r
+ _MISC \r
+SECTION: ".abs_section_b"\r
+ _MODE \r
+SECTION: ".abs_section_247"\r
+ _MODRR \r
+SECTION: ".abs_section_14"\r
+ _MTST0 \r
+SECTION: ".abs_section_17"\r
+ _MTST1 \r
+SECTION: ".abs_section_43"\r
+ _OC7D \r
+SECTION: ".abs_section_42"\r
+ _OC7M \r
+SECTION: ".abs_section_60"\r
+ _PACTL \r
+SECTION: ".abs_section_61"\r
+ _PAFLG \r
+SECTION: ".abs_section_1a"\r
+ _PARTIDH \r
+SECTION: ".abs_section_1b"\r
+ _PARTIDL \r
+SECTION: ".abs_section_a"\r
+ _PEAR \r
+SECTION: ".abs_section_274"\r
+ _PERAD \r
+SECTION: ".abs_section_26c"\r
+ _PERJ \r
+SECTION: ".abs_section_254"\r
+ _PERM \r
+SECTION: ".abs_section_25c"\r
+ _PERP \r
+SECTION: ".abs_section_24c"\r
+ _PERS \r
+SECTION: ".abs_section_244"\r
+ _PERT \r
+SECTION: ".abs_section_26e"\r
+ _PIEJ \r
+SECTION: ".abs_section_25e"\r
+ _PIEP \r
+SECTION: ".abs_section_26f"\r
+ _PIFJ \r
+SECTION: ".abs_section_25f"\r
+ _PIFP \r
+SECTION: ".abs_section_3a"\r
+ _PLLCTL \r
+SECTION: ".abs_section_8f"\r
+ _PORTAD0 \r
+SECTION: ".abs_section_8"\r
+ _PORTE \r
+SECTION: ".abs_section_32"\r
+ _PORTK \r
+SECTION: ".abs_section_30"\r
+ _PPAGE \r
+SECTION: ".abs_section_275"\r
+ _PPSAD \r
+SECTION: ".abs_section_26d"\r
+ _PPSJ \r
+SECTION: ".abs_section_255"\r
+ _PPSM \r
+SECTION: ".abs_section_25d"\r
+ _PPSP \r
+SECTION: ".abs_section_24d"\r
+ _PPSS \r
+SECTION: ".abs_section_245"\r
+ _PPST \r
+SECTION: ".abs_section_270"\r
+ _PTAD \r
+SECTION: ".abs_section_271"\r
+ _PTIAD \r
+SECTION: ".abs_section_269"\r
+ _PTIJ \r
+SECTION: ".abs_section_251"\r
+ _PTIM \r
+SECTION: ".abs_section_259"\r
+ _PTIP \r
+SECTION: ".abs_section_249"\r
+ _PTIS \r
+SECTION: ".abs_section_241"\r
+ _PTIT \r
+SECTION: ".abs_section_268"\r
+ _PTJ \r
+SECTION: ".abs_section_250"\r
+ _PTM \r
+SECTION: ".abs_section_258"\r
+ _PTP \r
+SECTION: ".abs_section_248"\r
+ _PTS \r
+SECTION: ".abs_section_240"\r
+ _PTT \r
+SECTION: ".abs_section_c"\r
+ _PUCR \r
+SECTION: ".abs_section_e4"\r
+ _PWMCAE \r
+SECTION: ".abs_section_e2"\r
+ _PWMCLK \r
+SECTION: ".abs_section_e5"\r
+ _PWMCTL \r
+SECTION: ".abs_section_e0"\r
+ _PWME \r
+SECTION: ".abs_section_e1"\r
+ _PWMPOL \r
+SECTION: ".abs_section_e3"\r
+ _PWMPRCLK \r
+SECTION: ".abs_section_e8"\r
+ _PWMSCLA \r
+SECTION: ".abs_section_e9"\r
+ _PWMSCLB \r
+SECTION: ".abs_section_fe"\r
+ _PWMSDN \r
+SECTION: ".abs_section_273"\r
+ _RDRAD \r
+SECTION: ".abs_section_d"\r
+ _RDRIV \r
+SECTION: ".abs_section_26b"\r
+ _RDRJ \r
+SECTION: ".abs_section_253"\r
+ _RDRM \r
+SECTION: ".abs_section_25b"\r
+ _RDRP \r
+SECTION: ".abs_section_24b"\r
+ _RDRS \r
+SECTION: ".abs_section_243"\r
+ _RDRT \r
+SECTION: ".abs_section_35"\r
+ _REFDV \r
+SECTION: ".abs_section_3b"\r
+ _RTICTL \r
+SECTION: ".abs_section_ca"\r
+ _SCICR1 \r
+SECTION: ".abs_section_cb"\r
+ _SCICR2 \r
+SECTION: ".abs_section_ce"\r
+ _SCIDRH \r
+SECTION: ".abs_section_cf"\r
+ _SCIDRL \r
+SECTION: ".abs_section_cc"\r
+ _SCISR1 \r
+SECTION: ".abs_section_cd"\r
+ _SCISR2 \r
+SECTION: ".abs_section_da"\r
+ _SPIBR \r
+SECTION: ".abs_section_d8"\r
+ _SPICR1 \r
+SECTION: ".abs_section_d9"\r
+ _SPICR2 \r
+SECTION: ".abs_section_dd"\r
+ _SPIDR \r
+SECTION: ".abs_section_db"\r
+ _SPISR \r
+SECTION: ".abs_section_34"\r
+ _SYNR \r
+SECTION: ".abs_section_48"\r
+ _TCTL1 \r
+SECTION: ".abs_section_49"\r
+ _TCTL2 \r
+SECTION: ".abs_section_4a"\r
+ _TCTL3 \r
+SECTION: ".abs_section_4b"\r
+ _TCTL4 \r
+SECTION: ".abs_section_4e"\r
+ _TFLG1 \r
+SECTION: ".abs_section_4f"\r
+ _TFLG2 \r
+SECTION: ".abs_section_4c"\r
+ _TIE \r
+SECTION: ".abs_section_40"\r
+ _TIOS \r
+SECTION: ".abs_section_46"\r
+ _TSCR1 \r
+SECTION: ".abs_section_4d"\r
+ _TSCR2 \r
+SECTION: ".abs_section_47"\r
+ _TTOV \r
+SECTION: ".abs_section_256"\r
+ _WOMM \r
+SECTION: ".abs_section_24e"\r
+ _WOMS \r
+SECTION: ".abs_section_82"\r
+ _ATDCTL23 \r
+SECTION: ".abs_section_84"\r
+ _ATDCTL45 \r
+SECTION: ".abs_section_90"\r
+ _ATDDR0 \r
+SECTION: ".abs_section_92"\r
+ _ATDDR1 \r
+SECTION: ".abs_section_94"\r
+ _ATDDR2 \r
+SECTION: ".abs_section_96"\r
+ _ATDDR3 \r
+SECTION: ".abs_section_98"\r
+ _ATDDR4 \r
+SECTION: ".abs_section_9a"\r
+ _ATDDR5 \r
+SECTION: ".abs_section_9c"\r
+ _ATDDR6 \r
+SECTION: ".abs_section_9e"\r
+ _ATDDR7 \r
+SECTION: ".abs_section_2"\r
+ _DDRAB \r
+SECTION: ".abs_section_62"\r
+ _PACNT \r
+SECTION: ".abs_section_0"\r
+ _PORTAB \r
+SECTION: ".abs_section_ec"\r
+ _PWMCNT01 \r
+SECTION: ".abs_section_ee"\r
+ _PWMCNT23 \r
+SECTION: ".abs_section_f0"\r
+ _PWMCNT45 \r
+SECTION: ".abs_section_f8"\r
+ _PWMDTY01 \r
+SECTION: ".abs_section_fa"\r
+ _PWMDTY23 \r
+SECTION: ".abs_section_fc"\r
+ _PWMDTY45 \r
+SECTION: ".abs_section_f2"\r
+ _PWMPER01 \r
+SECTION: ".abs_section_f4"\r
+ _PWMPER23 \r
+SECTION: ".abs_section_f6"\r
+ _PWMPER45 \r
+SECTION: ".abs_section_c8"\r
+ _SCIBD \r
+SECTION: ".abs_section_50"\r
+ _TC0 \r
+SECTION: ".abs_section_52"\r
+ _TC1 \r
+SECTION: ".abs_section_54"\r
+ _TC2 \r
+SECTION: ".abs_section_56"\r
+ _TC3 \r
+SECTION: ".abs_section_58"\r
+ _TC4 \r
+SECTION: ".abs_section_5a"\r
+ _TC5 \r
+SECTION: ".abs_section_5c"\r
+ _TC6 \r
+SECTION: ".abs_section_5e"\r
+ _TC7 \r
+SECTION: ".abs_section_44"\r
+ _TCNT \r
+SECTION: ".abs_section_ff80"\r
+ _vect \r
+SECTION: "TickTimer_DATA"\r
+ EnUser CmpHighVal \r
+\r
+*********************************************************************************************\r
+OBJECT LIST SORTED BY ADDRESS\r
+ Name Addr hSize dSize Ref Section RLIB\r
+---------------------------------------------------------------------------------------------\r
+ _PORTAB 0 2 2 3 .abs_section_0\r
+ _DDRAB 2 2 2 1 .abs_section_2\r
+ _PORTE 8 1 1 0 .abs_section_8\r
+ _DDRE 9 1 1 0 .abs_section_9\r
+ _PEAR A 1 1 0 .abs_section_a\r
+ _MODE B 1 1 0 .abs_section_b\r
+ _PUCR C 1 1 0 .abs_section_c\r
+ _RDRIV D 1 1 0 .abs_section_d\r
+ _EBICTL E 1 1 0 .abs_section_e\r
+ _INITRM 10 1 1 1 .abs_section_10\r
+ _INITRG 11 1 1 0 .abs_section_11\r
+ _INITEE 12 1 1 0 .abs_section_12\r
+ _MISC 13 1 1 1 .abs_section_13\r
+ _MTST0 14 1 1 0 .abs_section_14\r
+ _ITCR 15 1 1 0 .abs_section_15\r
+ _ITEST 16 1 1 0 .abs_section_16\r
+ _MTST1 17 1 1 0 .abs_section_17\r
+ _PARTIDH 1A 1 1 0 .abs_section_1a\r
+ _PARTIDL 1B 1 1 0 .abs_section_1b\r
+ _MEMSIZ0 1C 1 1 0 .abs_section_1c\r
+ _MEMSIZ1 1D 1 1 0 .abs_section_1d\r
+ _INTCR 1E 1 1 1 .abs_section_1e\r
+ _HPRIO 1F 1 1 0 .abs_section_1f\r
+ _BKPCT0 28 1 1 0 .abs_section_28\r
+ _BKPCT1 29 1 1 0 .abs_section_29\r
+ _BKP0X 2A 1 1 0 .abs_section_2a\r
+ _BKP0H 2B 1 1 0 .abs_section_2b\r
+ _BKP0L 2C 1 1 0 .abs_section_2c\r
+ _BKP1X 2D 1 1 0 .abs_section_2d\r
+ _BKP1H 2E 1 1 0 .abs_section_2e\r
+ _BKP1L 2F 1 1 0 .abs_section_2f\r
+ _PPAGE 30 1 1 0 .abs_section_30\r
+ _PORTK 32 1 1 0 .abs_section_32\r
+ _DDRK 33 1 1 0 .abs_section_33\r
+ _SYNR 34 1 1 1 .abs_section_34\r
+ _REFDV 35 1 1 1 .abs_section_35\r
+ _CTFLG 36 1 1 0 .abs_section_36\r
+ _CRGFLG 37 1 1 1 .abs_section_37\r
+ _CRGINT 38 1 1 0 .abs_section_38\r
+ _CLKSEL 39 1 1 3 .abs_section_39\r
+ _PLLCTL 3A 1 1 3 .abs_section_3a\r
+ _RTICTL 3B 1 1 0 .abs_section_3b\r
+ _COPCTL 3C 1 1 0 .abs_section_3c\r
+ _CTCTL 3E 1 1 0 .abs_section_3e\r
+ _ARMCOP 3F 1 1 0 .abs_section_3f\r
+ _TIOS 40 1 1 1 .abs_section_40\r
+ _CFORC 41 1 1 0 .abs_section_41\r
+ _OC7M 42 1 1 0 .abs_section_42\r
+ _OC7D 43 1 1 0 .abs_section_43\r
+ _TCNT 44 2 2 0 .abs_section_44\r
+ _TSCR1 46 1 1 3 .abs_section_46\r
+ _TTOV 47 1 1 1 .abs_section_47\r
+ _TCTL1 48 1 1 1 .abs_section_48\r
+ _TCTL2 49 1 1 1 .abs_section_49\r
+ _TCTL3 4A 1 1 0 .abs_section_4a\r
+ _TCTL4 4B 1 1 0 .abs_section_4b\r
+ _TIE 4C 1 1 3 .abs_section_4c\r
+ _TSCR2 4D 1 1 5 .abs_section_4d\r
+ _TFLG1 4E 1 1 2 .abs_section_4e\r
+ _TFLG2 4F 1 1 0 .abs_section_4f\r
+ _TC0 50 2 2 1 .abs_section_50\r
+ _TC1 52 2 2 0 .abs_section_52\r
+ _TC2 54 2 2 0 .abs_section_54\r
+ _TC3 56 2 2 0 .abs_section_56\r
+ _TC4 58 2 2 0 .abs_section_58\r
+ _TC5 5A 2 2 0 .abs_section_5a\r
+ _TC6 5C 2 2 0 .abs_section_5c\r
+ _TC7 5E 2 2 1 .abs_section_5e\r
+ _PACTL 60 1 1 0 .abs_section_60\r
+ _PAFLG 61 1 1 0 .abs_section_61\r
+ _PACNT 62 2 2 0 .abs_section_62\r
+ _ATDCTL23 82 2 2 0 .abs_section_82\r
+ _ATDCTL45 84 2 2 0 .abs_section_84\r
+ _ATDSTAT0 86 1 1 0 .abs_section_86\r
+ _ATDSTAT1 8B 1 1 0 .abs_section_8b\r
+ _ATDDIEN 8D 1 1 0 .abs_section_8d\r
+ _PORTAD0 8F 1 1 0 .abs_section_8f\r
+ _ATDDR0 90 2 2 0 .abs_section_90\r
+ _ATDDR1 92 2 2 0 .abs_section_92\r
+ _ATDDR2 94 2 2 0 .abs_section_94\r
+ _ATDDR3 96 2 2 0 .abs_section_96\r
+ _ATDDR4 98 2 2 0 .abs_section_98\r
+ _ATDDR5 9A 2 2 0 .abs_section_9a\r
+ _ATDDR6 9C 2 2 0 .abs_section_9c\r
+ _ATDDR7 9E 2 2 0 .abs_section_9e\r
+ _SCIBD C8 2 2 0 .abs_section_c8\r
+ _SCICR1 CA 1 1 0 .abs_section_ca\r
+ _SCICR2 CB 1 1 0 .abs_section_cb\r
+ _SCISR1 CC 1 1 0 .abs_section_cc\r
+ _SCISR2 CD 1 1 0 .abs_section_cd\r
+ _SCIDRH CE 1 1 0 .abs_section_ce\r
+ _SCIDRL CF 1 1 0 .abs_section_cf\r
+ _SPICR1 D8 1 1 0 .abs_section_d8\r
+ _SPICR2 D9 1 1 0 .abs_section_d9\r
+ _SPIBR DA 1 1 0 .abs_section_da\r
+ _SPISR DB 1 1 0 .abs_section_db\r
+ _SPIDR DD 1 1 0 .abs_section_dd\r
+ _PWME E0 1 1 0 .abs_section_e0\r
+ _PWMPOL E1 1 1 0 .abs_section_e1\r
+ _PWMCLK E2 1 1 0 .abs_section_e2\r
+ _PWMPRCLK E3 1 1 0 .abs_section_e3\r
+ _PWMCAE E4 1 1 0 .abs_section_e4\r
+ _PWMCTL E5 1 1 1 .abs_section_e5\r
+ _PWMSCLA E8 1 1 0 .abs_section_e8\r
+ _PWMSCLB E9 1 1 0 .abs_section_e9\r
+ _PWMCNT01 EC 2 2 0 .abs_section_ec\r
+ _PWMCNT23 EE 2 2 0 .abs_section_ee\r
+ _PWMCNT45 F0 2 2 0 .abs_section_f0\r
+ _PWMPER01 F2 2 2 0 .abs_section_f2\r
+ _PWMPER23 F4 2 2 0 .abs_section_f4\r
+ _PWMPER45 F6 2 2 0 .abs_section_f6\r
+ _PWMDTY01 F8 2 2 0 .abs_section_f8\r
+ _PWMDTY23 FA 2 2 0 .abs_section_fa\r
+ _PWMDTY45 FC 2 2 0 .abs_section_fc\r
+ _PWMSDN FE 1 1 1 .abs_section_fe\r
+ _FCLKDIV 100 1 1 0 .abs_section_100\r
+ _FSEC 101 1 1 0 .abs_section_101\r
+ _FCNFG 103 1 1 0 .abs_section_103\r
+ _FPROT 104 1 1 0 .abs_section_104\r
+ _FSTAT 105 1 1 0 .abs_section_105\r
+ _FCMD 106 1 1 0 .abs_section_106\r
+ _CANCTL0 140 1 1 0 .abs_section_140\r
+ _CANCTL1 141 1 1 0 .abs_section_141\r
+ _CANBTR0 142 1 1 0 .abs_section_142\r
+ _CANBTR1 143 1 1 0 .abs_section_143\r
+ _CANRFLG 144 1 1 0 .abs_section_144\r
+ _CANRIER 145 1 1 0 .abs_section_145\r
+ _CANTFLG 146 1 1 0 .abs_section_146\r
+ _CANTIER 147 1 1 0 .abs_section_147\r
+ _CANTARQ 148 1 1 0 .abs_section_148\r
+ _CANTAAK 149 1 1 0 .abs_section_149\r
+ _CANTBSEL 14A 1 1 0 .abs_section_14a\r
+ _CANIDAC 14B 1 1 0 .abs_section_14b\r
+ _CANRXERR 14E 1 1 0 .abs_section_14e\r
+ _CANTXERR 14F 1 1 0 .abs_section_14f\r
+ _CANIDAR0 150 1 1 0 .abs_section_150\r
+ _CANIDAR1 151 1 1 0 .abs_section_151\r
+ _CANIDAR2 152 1 1 0 .abs_section_152\r
+ _CANIDAR3 153 1 1 0 .abs_section_153\r
+ _CANIDMR0 154 1 1 0 .abs_section_154\r
+ _CANIDMR1 155 1 1 0 .abs_section_155\r
+ _CANIDMR2 156 1 1 0 .abs_section_156\r
+ _CANIDMR3 157 1 1 0 .abs_section_157\r
+ _CANIDAR4 158 1 1 0 .abs_section_158\r
+ _CANIDAR5 159 1 1 0 .abs_section_159\r
+ _CANIDAR6 15A 1 1 0 .abs_section_15a\r
+ _CANIDAR7 15B 1 1 0 .abs_section_15b\r
+ _CANIDMR4 15C 1 1 0 .abs_section_15c\r
+ _CANIDMR5 15D 1 1 0 .abs_section_15d\r
+ _CANIDMR6 15E 1 1 0 .abs_section_15e\r
+ _CANIDMR7 15F 1 1 0 .abs_section_15f\r
+ _CANRXIDR0 160 1 1 0 .abs_section_160\r
+ _CANRXIDR1 161 1 1 0 .abs_section_161\r
+ _CANRXIDR2 162 1 1 0 .abs_section_162\r
+ _CANRXIDR3 163 1 1 0 .abs_section_163\r
+ _CANRXDSR0 164 1 1 0 .abs_section_164\r
+ _CANRXDSR1 165 1 1 0 .abs_section_165\r
+ _CANRXDSR2 166 1 1 0 .abs_section_166\r
+ _CANRXDSR3 167 1 1 0 .abs_section_167\r
+ _CANRXDSR4 168 1 1 0 .abs_section_168\r
+ _CANRXDSR5 169 1 1 0 .abs_section_169\r
+ _CANRXDSR6 16A 1 1 0 .abs_section_16a\r
+ _CANRXDSR7 16B 1 1 0 .abs_section_16b\r
+ _CANRXDLR 16C 1 1 0 .abs_section_16c\r
+ _CANTXIDR0 170 1 1 0 .abs_section_170\r
+ _CANTXIDR1 171 1 1 0 .abs_section_171\r
+ _CANTXIDR2 172 1 1 0 .abs_section_172\r
+ _CANTXIDR3 173 1 1 0 .abs_section_173\r
+ _CANTXDSR0 174 1 1 0 .abs_section_174\r
+ _CANTXDSR1 175 1 1 0 .abs_section_175\r
+ _CANTXDSR2 176 1 1 0 .abs_section_176\r
+ _CANTXDSR3 177 1 1 0 .abs_section_177\r
+ _CANTXDSR4 178 1 1 0 .abs_section_178\r
+ _CANTXDSR5 179 1 1 0 .abs_section_179\r
+ _CANTXDSR6 17A 1 1 0 .abs_section_17a\r
+ _CANTXDSR7 17B 1 1 0 .abs_section_17b\r
+ _CANTXDLR 17C 1 1 0 .abs_section_17c\r
+ _CANTXTBPR 17F 1 1 0 .abs_section_17f\r
+ _PTT 240 1 1 0 .abs_section_240\r
+ _PTIT 241 1 1 0 .abs_section_241\r
+ _DDRT 242 1 1 0 .abs_section_242\r
+ _RDRT 243 1 1 0 .abs_section_243\r
+ _PERT 244 1 1 0 .abs_section_244\r
+ _PPST 245 1 1 0 .abs_section_245\r
+ _MODRR 247 1 1 0 .abs_section_247\r
+ _PTS 248 1 1 0 .abs_section_248\r
+ _PTIS 249 1 1 0 .abs_section_249\r
+ _DDRS 24A 1 1 0 .abs_section_24a\r
+ _RDRS 24B 1 1 0 .abs_section_24b\r
+ _PERS 24C 1 1 0 .abs_section_24c\r
+ _PPSS 24D 1 1 0 .abs_section_24d\r
+ _WOMS 24E 1 1 0 .abs_section_24e\r
+ _PTM 250 1 1 0 .abs_section_250\r
+ _PTIM 251 1 1 0 .abs_section_251\r
+ _DDRM 252 1 1 0 .abs_section_252\r
+ _RDRM 253 1 1 0 .abs_section_253\r
+ _PERM 254 1 1 0 .abs_section_254\r
+ _PPSM 255 1 1 0 .abs_section_255\r
+ _WOMM 256 1 1 0 .abs_section_256\r
+ _PTP 258 1 1 0 .abs_section_258\r
+ _PTIP 259 1 1 0 .abs_section_259\r
+ _DDRP 25A 1 1 1 .abs_section_25a\r
+ _RDRP 25B 1 1 0 .abs_section_25b\r
+ _PERP 25C 1 1 1 .abs_section_25c\r
+ _PPSP 25D 1 1 1 .abs_section_25d\r
+ _PIEP 25E 1 1 2 .abs_section_25e\r
+ _PIFP 25F 1 1 2 .abs_section_25f\r
+ _PTJ 268 1 1 0 .abs_section_268\r
+ _PTIJ 269 1 1 0 .abs_section_269\r
+ _DDRJ 26A 1 1 0 .abs_section_26a\r
+ _RDRJ 26B 1 1 0 .abs_section_26b\r
+ _PERJ 26C 1 1 0 .abs_section_26c\r
+ _PPSJ 26D 1 1 0 .abs_section_26d\r
+ _PIEJ 26E 1 1 0 .abs_section_26e\r
+ _PIFJ 26F 1 1 0 .abs_section_26f\r
+ _PTAD 270 1 1 0 .abs_section_270\r
+ _PTIAD 271 1 1 0 .abs_section_271\r
+ _DDRAD 272 1 1 0 .abs_section_272\r
+ _RDRAD 273 1 1 0 .abs_section_273\r
+ _PERAD 274 1 1 0 .abs_section_274\r
+ _PPSAD 275 1 1 0 .abs_section_275\r
+ uxCriticalNesting 800 1 1 91 .data \r
+ pxCurrentTCB 801 2 2 29 .bss \r
+ uxCurrentNumberOfTasks 803 1 1 3 .bss \r
+ xTickCount 804 2 2 14 .bss \r
+ uxTopUsedPriority 806 1 1 2 .bss \r
+ uxTopReadyPriority 807 1 1 15 .bss \r
+ xSchedulerRunning 808 1 1 3 .bss \r
+ uxSchedulerSuspended 809 1 1 6 .bss \r
+ uxMissedTicks 80A 1 1 4 .bss \r
+ uxTaskNumber.1 80B 1 1 2 .bss \r
+ pxReadyTasksLists 80C 3C 60 11 .bss \r
+ xDelayedTaskList1 848 F 15 2 .bss \r
+ xDelayedTaskList2 857 F 15 2 .bss \r
+ pxDelayedTaskList 866 2 2 8 .bss \r
+ pxOverflowDelayedTaskList 868 2 2 6 .bss \r
+ xPendingReadyList 86A F 15 4 .bss \r
+ xSuspendedTaskList 879 F 15 2 .bss \r
+ uxFlashTaskNumber 888 1 1 2 .bss \r
+ xLocalError 889 1 1 3 .bss \r
+ uxValToSend.3 88A 1 1 2 .bss \r
+ xButtonQueue 88B 2 2 3 .bss \r
+ xNextFreeByte 88D 2 2 5 .bss \r
+ xHeap 88F 704 1796 1 .bss \r
+ xPollingConsumerCount F93 1 1 3 .bss \r
+ xPollingProducerCount F94 1 1 3 .bss \r
+ xPolledQueue.1 F95 2 2 3 .bss \r
+ usCheckVariable F97 2 2 4 .bss \r
+ xSuspendedQueueSendError F99 1 1 2 .bss \r
+ xSuspendedQueueReceiveError F9A 1 1 3 .bss \r
+ ulValueToSend.6 F9B 4 4 5 .bss \r
+ ulExpectedValue.7 F9F 4 4 6 .bss \r
+ usLastTaskCheck.9 FA3 2 2 2 .bss \r
+ xContinousIncrementHandle FA5 2 2 5 .bss \r
+ xLimitedIncrementHandle FA7 2 2 2 .bss \r
+ ulCounter FA9 4 4 10 .bss \r
+ ulReceivedValue.8 FAD 4 4 3 .bss \r
+ xSuspendedTestQueue FB1 2 2 3 .common \r
+ Byte1_Table FB3 8 8 1 Byte1_DATA \r
+ EnUser FBB 1 1 4 TickTimer_DATA\r
+ CmpHighVal FBC 2 2 2 TickTimer_DATA\r
+ _EntryPoint C000 2E 46 1 .init \r
+ PE_low_level_init C02E 48 72 1 .init \r
+ STRING.IDLE.2 C093 5 5 1 .rodata1 \r
+ STRING.LEDx.1 C098 5 5 1 .rodata1 \r
+ STRING.Check.1 C09D 6 6 1 .rodata1 \r
+ STRING.Button.2 C0A3 7 7 1 .rodata1 \r
+ STRING.QConsNB.2 C0AA 8 8 1 .rodata1 \r
+ STRING.QProdNB.3 C0B2 8 8 1 .rodata1 \r
+ STRING.CNT_INC.1 C0BA 8 8 1 .rodata1 \r
+ STRING.LIM_INC.2 C0C2 8 8 1 .rodata1 \r
+ STRING.C_CTRL.3 C0CA 7 7 1 .rodata1 \r
+ STRING.SUSP_TX.4 C0D1 8 8 1 .rodata1 \r
+ STRING.SUSP_RX.5 C0D9 8 8 1 .rodata1 \r
+ Cpu_Interrupt C0E1 1 1 60 NON_BANKED \r
+ xBankedStartScheduler C0E2 F 15 1 NON_BANKED \r
+ vPortYield C0F1 16 22 1 NON_BANKED \r
+ vPortTickInterrupt C107 1D 29 1 NON_BANKED \r
+ vButtonPush C124 2F 47 1 NON_BANKED \r
+ Init C153 29 41 1 .text \r
+ _Startup C17C 10 16 1 .text \r
+ memcpy C18C 26 38 3 .text \r
+ memset C1B2 1E 30 1 .text \r
+ strncpy C1D0 2D 45 1 .text \r
+ main C1FD 8 8 0 .text \r
+ xTaskCreate C205 CE 206 11 .text \r
+ vTaskDelayUntil C2D3 74 116 3 .text \r
+ vTaskDelay C347 46 70 4 .text \r
+ uxTaskPriorityGet C38D 26 38 1 .text \r
+ vTaskPrioritySet C3B3 69 105 2 .text \r
+ vTaskSuspend C41C 44 68 3 .text \r
+ vTaskResume C460 59 89 3 .text \r
+ vTaskStartScheduler C4B9 30 48 1 .text \r
+ vTaskSuspendAll C4E9 13 19 11 .text \r
+ xTaskResumeAll C4FC 9F 159 13 .text \r
+ xTaskGetTickCount C59B 17 23 2 .text \r
+ vTaskIncrementTick C5B2 81 129 2 .text \r
+ vTaskSwitchContext C633 5B 91 3 .text \r
+ vTaskPlaceOnEventList C68E 41 65 2 .text \r
+ xTaskRemoveFromEventList C6CF 6C 108 3 .text \r
+ prvIdleTask C73B 10 16 1 .text \r
+ prvInitialiseTCBVariables C74B 4C 76 1 .text \r
+ prvInitialiseTaskLists C797 3C 60 1 .text \r
+ prvCheckTasksWaitingTermination C7D3 1 1 1 .text \r
+ prvAllocateTCBAndStack C7D4 33 51 1 .text \r
+ xQueueCreate C807 77 119 3 .text \r
+ xQueueSend C87E CA 202 3 .text \r
+ xQueueSendFromISR C948 54 84 1 .text \r
+ xQueueReceive C99C C4 196 4 .text \r
+ uxQueueMessagesWaiting CA60 1B 27 1 .text \r
+ prvUnlockQueue CA7B 6F 111 4 .text \r
+ prvIsQueueEmpty CAEA 21 33 1 .text \r
+ prvIsQueueFull CB0B 24 36 1 .text \r
+ vListInitialise CB2F 1F 31 7 .text \r
+ vListInitialiseItem CB4E 7 7 3 .text \r
+ vListInsertEnd CB55 27 39 7 .text \r
+ vListInsert CB7C 5A 90 4 .text \r
+ vListRemove CBD6 23 35 13 .text \r
+ pxPortInitialiseStack CBF9 2B 43 1 .text \r
+ prvSetupTimerInterrupt CC24 9 9 1 .text \r
+ xPortStartScheduler CC2D 4 4 1 .text \r
+ vStartLEDFlashTasks CC31 26 38 1 .text \r
+ vLEDFlashTask CC57 52 82 1 .text \r
+ vMain CCA9 42 66 1 .text \r
+ vErrorChecks CCEB 2F 47 1 .text \r
+ prvCheckOtherTasksAreStillRunning CD1A 23 35 1 .text \r
+ vApplicationIdleHook CD3D 73 115 1 .text \r
+ vButtonTask CDB0 4F 79 1 .text \r
+ pvPortMalloc CDFF 30 48 4 .text \r
+ vPortFree CE2F 1 1 2 .text \r
+ PE_Timer_LngHi1 CE30 43 67 1 .text \r
+ vParTestToggleLED CE73 13 19 4 .text \r
+ vStartPolledQueueTasks CE86 40 64 1 .text \r
+ vPolledQueueProducer CEC6 4D 77 1 .text \r
+ vPolledQueueConsumer CF13 59 89 1 .text \r
+ xArePollingQueuesStillRunning CF6C 1D 29 1 .text \r
+ vStartDynamicPriorityTasks CF89 7C 124 1 .text \r
+ vLimitedIncrementTask D005 21 33 1 .text \r
+ vContinuousIncrementTask D026 30 48 1 .text \r
+ vCounterControlTask D056 98 152 3 .text \r
+ vQueueSendWhenSuspendedTask D0EE 34 52 1 .text \r
+ vQueueReceiveWhenSuspendedTask D122 4E 78 1 .text \r
+ xAreDynamicPriorityTasksStillRunning D170 27 39 1 .text \r
+ _LCMP D197 19 25 2 RUNTIME \r
+ _LCMP_P D1B0 15 21 2 RUNTIME \r
+ _LNEG D1C5 D 13 1 RUNTIME \r
+ _LINC D1D2 5 5 4 RUNTIME \r
+ _lDivMod D1D7 E3 227 3 RUNTIME \r
+ _LDIVU D2BA E 14 1 RUNTIME \r
+ _NEG_P D2C8 F 15 4 RUNTIME \r
+ _LDIVS D2D7 35 53 1 RUNTIME \r
+ Byte1_GetMsk D30C D 13 1 Byte1_CODE \r
+ Byte1_NegBit D319 F 15 1 Byte1_CODE \r
+ SetCV D328 F 15 2 TickTimer_CODE\r
+ SetPV D337 C 12 1 TickTimer_CODE\r
+ HWEnDi D343 11 17 2 TickTimer_CODE\r
+ TickTimer_Enable D354 E 14 1 TickTimer_CODE\r
+ TickTimer_SetFreqHz D362 4F 79 1 TickTimer_CODE\r
+ TickTimer_Init D3B1 14 20 1 TickTimer_CODE\r
+ ButtonInterrupt_Enable D3C5 A 10 1 ButtonInterrupt_CODE\r
+ _BDMSTS FF01 1 1 0 .abs_section_ff01\r
+ _BDMCCR FF06 1 1 0 .abs_section_ff06\r
+ _BDMINR FF07 1 1 0 .abs_section_ff07\r
+ _vect FF80 80 128 0 .abs_section_ff80\r
+\r
+*********************************************************************************************\r
+UNUSED-OBJECTS SECTION\r
+---------------------------------------------------------------------------------------------\r
+NOT USED PROCEDURES\r
+STRING.C.o (ansisi.lib):\r
+ strerror memchr memcmp memcpy2 _memcpy_8bitCount memmove \r
+ _memset_clear_8bitCount strlen strset strcat strncat strcpy strcmp strncmp \r
+ strchr strrchr strspn strcspn strpbrk strstr strtok strcoll strxfrm \r
+rtshc12.c.o (ansisi.lib):\r
+ _BSHL _BSHRS _BSHRU _BDIVMODU _BDIVMODS _ISHL _ISHRU _ISHRS _LSHL _LSHRU \r
+ _LSHRS _LADD _LSUB _LAND _LOR _LXOR _LCMP_PP _LABS _LCOM _LDEC _LMUL _LMODU \r
+ _LMODS _ILSEXT _LTEST _COPY _CASE_DIRECT _CASE_DIRECT_BYTE _CASE_CHECKED \r
+ _CASE_CHECKED_BYTE _CASE_SEARCH _CASE_SEARCH_BYTE _CASE_SEARCH_8 \r
+ _CASE_SEARCH_8_BYTE _FCALL _FPCMP \r
+Byte1.C.o:\r
+ Byte1_PutBit \r
+tasks.c.o:\r
+ vTaskEndScheduler uxTaskGetNumberOfTasks \r
+queue.c.o:\r
+ xQueueReceiveFromISR vQueueDelete \r
+port.c.o:\r
+ vPortEndScheduler \r
+heap_1.c.o:\r
+ vPortInitialiseBlocks \r
+TickTimer.C.o:\r
+ TickTimer_Interrupt \r
+ParTest.c.o:\r
+ vParTestSetLED \r
+ButtonInterrupt.C.o:\r
+ ButtonInterrupt_Interrupt \r
+NOT USED VARIABLES\r
+STRING.C.o (ansisi.lib):\r
+ STRING..1 next.2 \r
+rtshc12.c.o (ansisi.lib):\r
+ _PowOfTwo_8 _PowOfTwo_16 _PowOfTwo_32 \r
+Cpu.C.o:\r
+ CpuMode CCR_reg \r
+\r
+*********************************************************************************************\r
+COPYDOWN SECTION\r
+---------------------------------------------------------------------------------------------\r
+------- ROM-ADDRESS: 0xD3CF ---- SIZE 4 ---\r
+Filling bytes inserted\r
+ 00010800\r
+------- ROM-ADDRESS: 0xD3D3 ---- RAM-ADDRESS: 0x800 ---- SIZE 1 ---\r
+Name of initialized Object : uxCriticalNesting\r
+ FF\r
+------- ROM-ADDRESS: 0xD3D4 ---- SIZE 4 ---\r
+Filling bytes inserted\r
+ 00080FB3\r
+------- ROM-ADDRESS: 0xD3D8 ---- RAM-ADDRESS: 0xFB3 ---- SIZE 8 ---\r
+Name of initialized Object : Byte1_Table\r
+ 0102040810 204080\r
+------- ROM-ADDRESS: 0xD3E0 ---- SIZE 2 ---\r
+Filling bytes inserted\r
+ 0000\r
+\r
+*********************************************************************************************\r
+OBJECT-DEPENDENCIES SECTION\r
+---------------------------------------------------------------------------------------------\r
+_EntryPoint USES _INITRM _MISC _CLKSEL _PLLCTL _SYNR _REFDV \r
+ _CRGFLG _Startup \r
+PE_low_level_init USES _TSCR1 _TCTL2 _TCTL1 _TIE _TTOV _TSCR2 _TIOS \r
+ _PPSP _PERP _DDRP _PWMCTL _PWMSDN _PORTAB _DDRAB \r
+ TickTimer_Init _PIEP _INTCR \r
+xBankedStartScheduler USES prvSetupTimerInterrupt pxCurrentTCB \r
+ uxCriticalNesting \r
+vPortYield USES uxCriticalNesting pxCurrentTCB \r
+ vTaskSwitchContext \r
+vPortTickInterrupt USES uxCriticalNesting pxCurrentTCB \r
+ vTaskIncrementTick vTaskSwitchContext _TFLG1 \r
+vButtonPush USES uxValToSend.3 _PIFP xButtonQueue \r
+ xQueueSendFromISR uxCriticalNesting pxCurrentTCB \r
+ vTaskSwitchContext \r
+Init USES _startupData \r
+_Startup USES _startupData Init \r
+main USES PE_low_level_init vMain \r
+xTaskCreate USES prvAllocateTCBAndStack \r
+ prvInitialiseTCBVariables pxPortInitialiseStack uxCriticalNesting \r
+ uxCurrentNumberOfTasks pxCurrentTCB prvInitialiseTaskLists \r
+ xSchedulerRunning uxTopUsedPriority uxTaskNumber.1 \r
+ uxTopReadyPriority pxReadyTasksLists vListInsertEnd \r
+vTaskDelayUntil USES vTaskSuspendAll xTickCount pxCurrentTCB \r
+ vListRemove pxOverflowDelayedTaskList pxDelayedTaskList \r
+ vListInsert xTaskResumeAll \r
+vTaskDelay USES vTaskSuspendAll xTickCount pxCurrentTCB \r
+ vListRemove pxOverflowDelayedTaskList pxDelayedTaskList \r
+ vListInsert xTaskResumeAll \r
+uxTaskPriorityGet USES uxCriticalNesting pxCurrentTCB \r
+vTaskPrioritySet USES uxCriticalNesting pxCurrentTCB \r
+ pxReadyTasksLists vListRemove uxTopReadyPriority vListInsertEnd \r
+vTaskSuspend USES uxCriticalNesting pxCurrentTCB vListRemove \r
+ xSuspendedTaskList vListInsertEnd \r
+vTaskResume USES uxCriticalNesting pxCurrentTCB vListRemove \r
+ uxTopReadyPriority pxReadyTasksLists vListInsertEnd \r
+vTaskStartScheduler USES pxCurrentTCB prvIdleTask STRING.IDLE.2 \r
+ xTaskCreate xSchedulerRunning xTickCount \r
+ xPortStartScheduler \r
+vTaskSuspendAll USES uxCriticalNesting uxSchedulerSuspended \r
+xTaskResumeAll USES uxCriticalNesting uxSchedulerSuspended \r
+ uxCurrentNumberOfTasks vListRemove uxTopReadyPriority \r
+ pxReadyTasksLists vListInsertEnd pxCurrentTCB xPendingReadyList \r
+ uxMissedTicks vTaskIncrementTick \r
+xTaskGetTickCount USES uxCriticalNesting xTickCount \r
+vTaskIncrementTick USES uxSchedulerSuspended xTickCount \r
+ pxDelayedTaskList pxOverflowDelayedTaskList vListRemove \r
+ uxTopReadyPriority pxReadyTasksLists vListInsertEnd uxMissedTicks \r
+vTaskSwitchContext USES uxSchedulerSuspended uxTopReadyPriority \r
+ pxCurrentTCB pxReadyTasksLists \r
+vTaskPlaceOnEventList USES pxCurrentTCB vListInsert xTickCount vListRemove \r
+ pxOverflowDelayedTaskList pxDelayedTaskList \r
+xTaskRemoveFromEventList USES vListRemove uxSchedulerSuspended \r
+ uxTopReadyPriority pxReadyTasksLists xPendingReadyList \r
+ vListInsertEnd pxCurrentTCB \r
+prvIdleTask USES prvCheckTasksWaitingTermination \r
+ pxReadyTasksLists vApplicationIdleHook \r
+prvInitialiseTCBVariables USES strncpy vListInitialiseItem \r
+prvInitialiseTaskLists USES pxReadyTasksLists vListInitialise \r
+ xDelayedTaskList1 xDelayedTaskList2 xPendingReadyList \r
+ xSuspendedTaskList pxDelayedTaskList pxOverflowDelayedTaskList \r
+prvAllocateTCBAndStack USES pvPortMalloc vPortFree memset \r
+xQueueCreate USES pvPortMalloc vListInitialise vPortFree \r
+xQueueSend USES vTaskSuspendAll uxCriticalNesting xQueueSend \r
+ prvIsQueueFull vTaskPlaceOnEventList prvUnlockQueue \r
+ xTaskResumeAll memcpy \r
+xQueueSendFromISR USES memcpy xTaskRemoveFromEventList \r
+xQueueReceive USES vTaskSuspendAll uxCriticalNesting xQueueReceive \r
+ prvIsQueueEmpty vTaskPlaceOnEventList prvUnlockQueue \r
+ xTaskResumeAll memcpy \r
+uxQueueMessagesWaiting USES uxCriticalNesting \r
+prvUnlockQueue USES uxCriticalNesting xTaskRemoveFromEventList \r
+prvIsQueueEmpty USES uxCriticalNesting \r
+prvIsQueueFull USES uxCriticalNesting \r
+vListInitialise USES vListInitialiseItem \r
+prvSetupTimerInterrupt USES TickTimer_SetFreqHz TickTimer_Enable \r
+xPortStartScheduler USES xBankedStartScheduler \r
+vStartLEDFlashTasks USES vLEDFlashTask STRING.LEDx.1 xTaskCreate \r
+vLEDFlashTask USES uxCriticalNesting uxFlashTaskNumber \r
+ xTaskGetTickCount vTaskDelayUntil vParTestToggleLED \r
+vMain USES vStartLEDFlashTasks vStartPolledQueueTasks \r
+ vStartDynamicPriorityTasks vErrorChecks STRING.Check.1 xTaskCreate \r
+ vButtonTask STRING.Button.2 vTaskStartScheduler \r
+vErrorChecks USES xTaskGetTickCount vTaskDelayUntil \r
+ prvCheckOtherTasksAreStillRunning _LCMP vParTestToggleLED \r
+prvCheckOtherTasksAreStillRunning USES xArePollingQueuesStillRunning \r
+ xAreDynamicPriorityTasksStillRunning xLocalError \r
+vApplicationIdleHook USES _LNEG _LDIVS _LCMP_P uxCriticalNesting \r
+ xLocalError \r
+vButtonTask USES xQueueCreate xButtonQueue \r
+ ButtonInterrupt_Enable xQueueReceive uxCriticalNesting xLocalError \r
+ vParTestToggleLED \r
+pvPortMalloc USES vTaskSuspendAll xNextFreeByte xHeap \r
+ xTaskResumeAll \r
+PE_Timer_LngHi1 USES _LCMP \r
+vParTestToggleLED USES uxCriticalNesting Byte1_NegBit \r
+vStartPolledQueueTasks USES xQueueCreate xPolledQueue.1 \r
+ vPolledQueueConsumer STRING.QConsNB.2 xTaskCreate \r
+ vPolledQueueProducer STRING.QProdNB.3 \r
+vPolledQueueProducer USES xQueueSend uxCriticalNesting \r
+ xPollingProducerCount vTaskDelay \r
+vPolledQueueConsumer USES xQueueReceive uxCriticalNesting \r
+ xPollingConsumerCount uxQueueMessagesWaiting vTaskDelay \r
+xArePollingQueuesStillRunning USES xPollingConsumerCount xPollingProducerCount \r
+vStartDynamicPriorityTasks USES xQueueCreate xSuspendedTestQueue \r
+ vContinuousIncrementTask STRING.CNT_INC.1 ulCounter \r
+ xContinousIncrementHandle xTaskCreate vLimitedIncrementTask \r
+ STRING.LIM_INC.2 xLimitedIncrementHandle vCounterControlTask \r
+ STRING.C_CTRL.3 vQueueSendWhenSuspendedTask STRING.SUSP_TX.4 \r
+ vQueueReceiveWhenSuspendedTask STRING.SUSP_RX.5 \r
+vLimitedIncrementTask USES _LINC _LCMP_P vTaskSuspend \r
+vContinuousIncrementTask USES uxTaskPriorityGet vTaskPrioritySet _LINC \r
+vCounterControlTask USES vCounterControlTask xContinousIncrementHandle \r
+ vTaskSuspend ulCounter vTaskResume vTaskDelay \r
+ vTaskSuspendAll xTaskResumeAll xLimitedIncrementHandle \r
+ uxCriticalNesting usCheckVariable \r
+vQueueSendWhenSuspendedTask USES vTaskSuspendAll xSuspendedTestQueue \r
+ ulValueToSend.6 xQueueSend xSuspendedQueueSendError \r
+ xTaskResumeAll vTaskDelay _LINC \r
+vQueueReceiveWhenSuspendedTask USES vTaskSuspendAll xSuspendedTestQueue \r
+ ulReceivedValue.8 xQueueReceive xTaskResumeAll \r
+ xSuspendedQueueReceiveError ulExpectedValue.7 _LINC \r
+xAreDynamicPriorityTasksStillRunning USES usCheckVariable usLastTaskCheck.9 \r
+ xSuspendedQueueSendError xSuspendedQueueReceiveError \r
+_LDIVU USES _lDivMod \r
+_LDIVS USES _NEG_P _lDivMod \r
+Byte1_GetMsk USES Byte1_Table \r
+Byte1_NegBit USES Byte1_GetMsk _PORTAB \r
+SetCV USES _TC0 _TC7 \r
+SetPV USES _TSCR2 \r
+HWEnDi USES EnUser _TFLG1 _TIE \r
+TickTimer_Enable USES EnUser HWEnDi \r
+TickTimer_SetFreqHz USES _LDIVU PE_Timer_LngHi1 CmpHighVal SetCV \r
+TickTimer_Init USES CmpHighVal EnUser SetCV SetPV HWEnDi \r
+ButtonInterrupt_Enable USES _PIFP _PIEP \r
+_vect USES Cpu_Interrupt vButtonPush vPortTickInterrupt \r
+ vPortYield _EntryPoint \r
+\r
+*********************************************************************************************\r
+DEPENDENCY TREE\r
+*********************************************************************************************\r
+ main and _Startup Group\r
+ | \r
+ +- main \r
+ | | \r
+ | +- PE_low_level_init \r
+ | | | \r
+ | | +- TickTimer_Init \r
+ | | | \r
+ | | +- SetCV \r
+ | | | \r
+ | | +- SetPV \r
+ | | | \r
+ | | +- HWEnDi \r
+ | | \r
+ | +- vMain \r
+ | | \r
+ | +- vStartLEDFlashTasks \r
+ | | | \r
+ | | +- vLEDFlashTask \r
+ | | | | \r
+ | | | +- xTaskGetTickCount \r
+ | | | | \r
+ | | | +- vTaskDelayUntil \r
+ | | | | | \r
+ | | | | +- vTaskSuspendAll \r
+ | | | | | \r
+ | | | | +- vListRemove \r
+ | | | | | \r
+ | | | | +- vListInsert \r
+ | | | | | \r
+ | | | | +- xTaskResumeAll \r
+ | | | | | \r
+ | | | | +- vListRemove (see above)\r
+ | | | | | \r
+ | | | | +- vListInsertEnd \r
+ | | | | | \r
+ | | | | +- vTaskIncrementTick \r
+ | | | | | \r
+ | | | | +- vListRemove (see above)\r
+ | | | | | \r
+ | | | | +- vListInsertEnd (see above)\r
+ | | | | \r
+ | | | +- vParTestToggleLED \r
+ | | | | \r
+ | | | +- Byte1_NegBit \r
+ | | | | \r
+ | | | +- Byte1_GetMsk \r
+ | | | \r
+ | | +- xTaskCreate \r
+ | | | \r
+ | | +- prvAllocateTCBAndStack\r
+ | | | | \r
+ | | | +- pvPortMalloc \r
+ | | | | | \r
+ | | | | +- vTaskSuspendAll (see above)\r
+ | | | | | \r
+ | | | | +- xTaskResumeAll (see above)\r
+ | | | | \r
+ | | | +- vPortFree \r
+ | | | | \r
+ | | | +- memset \r
+ | | | \r
+ | | +- prvInitialiseTCBVariables\r
+ | | | | \r
+ | | | +- strncpy \r
+ | | | | \r
+ | | | +- vListInitialiseItem \r
+ | | | \r
+ | | +- pxPortInitialiseStack\r
+ | | | \r
+ | | +- prvInitialiseTaskLists\r
+ | | | | \r
+ | | | +- vListInitialise \r
+ | | | | \r
+ | | | +- vListInitialiseItem (see above)\r
+ | | | \r
+ | | +- vListInsertEnd (see above)\r
+ | | \r
+ | +- vStartPolledQueueTasks\r
+ | | | \r
+ | | +- xQueueCreate \r
+ | | | | \r
+ | | | +- pvPortMalloc (see above)\r
+ | | | | \r
+ | | | +- vListInitialise (see above)\r
+ | | | | \r
+ | | | +- vPortFree (see above)\r
+ | | | \r
+ | | +- vPolledQueueConsumer\r
+ | | | | \r
+ | | | +- xQueueReceive \r
+ | | | | | \r
+ | | | | +- vTaskSuspendAll (see above)\r
+ | | | | | \r
+ | | | | +- prvIsQueueEmpty \r
+ | | | | | \r
+ | | | | +- vTaskPlaceOnEventList\r
+ | | | | | | \r
+ | | | | | +- vListInsert (see above)\r
+ | | | | | | \r
+ | | | | | +- vListRemove (see above)\r
+ | | | | | \r
+ | | | | +- prvUnlockQueue \r
+ | | | | | | \r
+ | | | | | +- xTaskRemoveFromEventList\r
+ | | | | | | \r
+ | | | | | +- vListRemove (see above)\r
+ | | | | | | \r
+ | | | | | +- vListInsertEnd (see above)\r
+ | | | | | \r
+ | | | | +- xTaskResumeAll (see above)\r
+ | | | | | \r
+ | | | | +- memcpy \r
+ | | | | \r
+ | | | +- uxQueueMessagesWaiting\r
+ | | | | \r
+ | | | +- vTaskDelay \r
+ | | | | \r
+ | | | +- vTaskSuspendAll (see above)\r
+ | | | | \r
+ | | | +- vListRemove (see above)\r
+ | | | | \r
+ | | | +- vListInsert (see above)\r
+ | | | | \r
+ | | | +- xTaskResumeAll (see above)\r
+ | | | \r
+ | | +- xTaskCreate (see above)\r
+ | | | \r
+ | | +- vPolledQueueProducer\r
+ | | | \r
+ | | +- xQueueSend \r
+ | | | | \r
+ | | | +- vTaskSuspendAll (see above)\r
+ | | | | \r
+ | | | +- prvIsQueueFull \r
+ | | | | \r
+ | | | +- vTaskPlaceOnEventList (see above)\r
+ | | | | \r
+ | | | +- prvUnlockQueue (see above)\r
+ | | | | \r
+ | | | +- xTaskResumeAll (see above)\r
+ | | | | \r
+ | | | +- memcpy (see above)\r
+ | | | \r
+ | | +- vTaskDelay (see above)\r
+ | | \r
+ | +- vStartDynamicPriorityTasks\r
+ | | | \r
+ | | +- xQueueCreate (see above)\r
+ | | | \r
+ | | +- vContinuousIncrementTask\r
+ | | | | \r
+ | | | +- uxTaskPriorityGet \r
+ | | | | \r
+ | | | +- vTaskPrioritySet \r
+ | | | | | \r
+ | | | | +- vListRemove (see above)\r
+ | | | | | \r
+ | | | | +- vListInsertEnd (see above)\r
+ | | | | \r
+ | | | +- _LINC \r
+ | | | \r
+ | | +- xTaskCreate (see above)\r
+ | | | \r
+ | | +- vLimitedIncrementTask\r
+ | | | | \r
+ | | | +- _LINC (see above)\r
+ | | | | \r
+ | | | +- _LCMP_P \r
+ | | | | \r
+ | | | +- vTaskSuspend \r
+ | | | | \r
+ | | | +- vListRemove (see above)\r
+ | | | | \r
+ | | | +- vListInsertEnd (see above)\r
+ | | | \r
+ | | +- vCounterControlTask \r
+ | | | | \r
+ | | | +- vTaskSuspend (see above)\r
+ | | | | \r
+ | | | +- vTaskResume \r
+ | | | | | \r
+ | | | | +- vListRemove (see above)\r
+ | | | | | \r
+ | | | | +- vListInsertEnd (see above)\r
+ | | | | \r
+ | | | +- vTaskDelay (see above)\r
+ | | | | \r
+ | | | +- vTaskSuspendAll (see above)\r
+ | | | | \r
+ | | | +- xTaskResumeAll (see above)\r
+ | | | \r
+ | | +- vQueueSendWhenSuspendedTask\r
+ | | | | \r
+ | | | +- vTaskSuspendAll (see above)\r
+ | | | | \r
+ | | | +- xQueueSend (see above)\r
+ | | | | \r
+ | | | +- xTaskResumeAll (see above)\r
+ | | | | \r
+ | | | +- vTaskDelay (see above)\r
+ | | | | \r
+ | | | +- _LINC (see above)\r
+ | | | \r
+ | | +- vQueueReceiveWhenSuspendedTask\r
+ | | | \r
+ | | +- vTaskSuspendAll (see above)\r
+ | | | \r
+ | | +- xQueueReceive (see above)\r
+ | | | \r
+ | | +- xTaskResumeAll (see above)\r
+ | | | \r
+ | | +- _LINC (see above)\r
+ | | \r
+ | +- vErrorChecks \r
+ | | | \r
+ | | +- xTaskGetTickCount (see above)\r
+ | | | \r
+ | | +- vTaskDelayUntil (see above)\r
+ | | | \r
+ | | +- prvCheckOtherTasksAreStillRunning\r
+ | | | | \r
+ | | | +- xArePollingQueuesStillRunning\r
+ | | | | \r
+ | | | +- xAreDynamicPriorityTasksStillRunning\r
+ | | | \r
+ | | +- _LCMP \r
+ | | | \r
+ | | +- vParTestToggleLED (see above)\r
+ | | \r
+ | +- xTaskCreate (see above)\r
+ | | \r
+ | +- vButtonTask \r
+ | | | \r
+ | | +- xQueueCreate (see above)\r
+ | | | \r
+ | | +- ButtonInterrupt_Enable\r
+ | | | \r
+ | | +- xQueueReceive (see above)\r
+ | | | \r
+ | | +- vParTestToggleLED (see above)\r
+ | | \r
+ | +- vTaskStartScheduler \r
+ | | \r
+ | +- prvIdleTask \r
+ | | | \r
+ | | +- prvCheckTasksWaitingTermination\r
+ | | | \r
+ | | +- vApplicationIdleHook\r
+ | | | \r
+ | | +- _LNEG \r
+ | | | \r
+ | | +- _LDIVS \r
+ | | | | \r
+ | | | +- _NEG_P \r
+ | | | | \r
+ | | | +- _lDivMod \r
+ | | | \r
+ | | +- _LCMP_P (see above)\r
+ | | \r
+ | +- xTaskCreate (see above)\r
+ | | \r
+ | +- xPortStartScheduler \r
+ | | \r
+ | +- xBankedStartScheduler\r
+ | | \r
+ | +- prvSetupTimerInterrupt\r
+ | | \r
+ | +- TickTimer_SetFreqHz \r
+ | | | \r
+ | | +- _LDIVU \r
+ | | | | \r
+ | | | +- _lDivMod (see above)\r
+ | | | \r
+ | | +- PE_Timer_LngHi1 \r
+ | | | | \r
+ | | | +- _LCMP (see above)\r
+ | | | \r
+ | | +- SetCV (see above)\r
+ | | \r
+ | +- TickTimer_Enable \r
+ | | \r
+ | +- HWEnDi (see above)\r
+ | \r
+ +- _EntryPoint \r
+ | \r
+ +- _Startup \r
+ | \r
+ +- Init \r
+ \r
+ _vect \r
+ | \r
+ +- Cpu_Interrupt \r
+ | \r
+ +- vButtonPush \r
+ | | \r
+ | +- xQueueSendFromISR \r
+ | | | \r
+ | | +- memcpy (see above)\r
+ | | | \r
+ | | +- xTaskRemoveFromEventList (see above)\r
+ | | \r
+ | +- vTaskSwitchContext \r
+ | \r
+ +- vPortTickInterrupt \r
+ | | \r
+ | +- vTaskIncrementTick (see above)\r
+ | | \r
+ | +- vTaskSwitchContext (see above)\r
+ | \r
+ +- vPortYield \r
+ | | \r
+ | +- vTaskSwitchContext (see above)\r
+ | \r
+ +- _EntryPoint (see above)\r
+ \r
+*********************************************************************************************\r
+STATISTIC SECTION\r
+---------------------------------------------------------------------------------------------\r
+\r
+ExeFile:\r
+--------\r
+Number of blocks to be downloaded: 9\r
+Total size of all blocks to be downloaded: 5218\r
+\r
--- /dev/null
+\r
+PROGRAM "E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior_small\bin\SofTec.abs"\r
+\r
+*********************************************************************************************\r
+TARGET SECTION\r
+---------------------------------------------------------------------------------------------\r
+Processor : Motorola HC12\r
+Memory Model: SMALL\r
+File Format : ELF\Dwarf 2.0\r
+Linker : SmartLinker V-5.0.22 Build 4047, Feb 17 2004\r
+\r
+*********************************************************************************************\r
+FILE SECTION\r
+---------------------------------------------------------------------------------------------\r
+Start12.c.o Model: SMALL, Lang: ANSI-C\r
+STRING.C.o (ansisi.lib) Model: SMALL, Lang: ANSI-C\r
+rtshc12.c.o (ansisi.lib) Model: SMALL, Lang: ANSI-C\r
+tasks.c.o Model: SMALL, Lang: ANSI-C\r
+queue.c.o Model: SMALL, Lang: ANSI-C\r
+list.c.o Model: SMALL, Lang: ANSI-C\r
+port.c.o Model: SMALL, Lang: ANSI-C\r
+flash.c.o Model: SMALL, Lang: ANSI-C\r
+main.c.o Model: SMALL, Lang: ANSI-C\r
+heap_1.c.o Model: SMALL, Lang: ANSI-C\r
+ParTest.c.o Model: SMALL, Lang: ANSI-C\r
+Cpu.C.o Model: SMALL, Lang: ANSI-C\r
+Byte1.C.o Model: SMALL, Lang: ANSI-C\r
+TickTimer.C.o Model: SMALL, Lang: ANSI-C\r
+IO_Map.C.o Model: SMALL, Lang: ANSI-C\r
+PE_Timer.C.o Model: SMALL, Lang: ANSI-C\r
+Vectors.c.o Model: SMALL, Lang: ANSI-C\r
+RTOSDemo.C.o Model: SMALL, Lang: ANSI-C\r
+PollQ.c.o Model: SMALL, Lang: ANSI-C\r
+dynamic.c.o Model: SMALL, Lang: ANSI-C\r
+ButtonInterrupt.C.o Model: SMALL, Lang: ANSI-C\r
+\r
+*********************************************************************************************\r
+STARTUP SECTION\r
+---------------------------------------------------------------------------------------------\r
+Entry point: 0xC000 (_EntryPoint)\r
+_startupData is allocated at 0xC076 and uses 23 Bytes\r
+extern struct _tagStartup {\r
+ unsigned flags 0\r
+ _PFunc main 0xCE77 (main)\r
+ long stackOffset 0xFED\r
+ unsigned nofZeroOut 1\r
+ _Range pZeroOut 0x800 1982\r
+ _Copy *toCopyDownBeg 0xD3C4\r
+ int nofLibInits 0\r
+ _LibInit *libInits 0xC091\r
+ int nofInitBodies 0\r
+ _Cpp *initBodies 0xC093\r
+ int nofFiniBodies 0\r
+ _Cpp *finiBodies 0xC093\r
+} _startupData;\r
+\r
+*********************************************************************************************\r
+SECTION-ALLOCATION SECTION\r
+Section Name Size Type From To Segment\r
+---------------------------------------------------------------------------------------------\r
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+.abs_section_240 1 N/I 0x240 0x240 .absSeg147\r
+.abs_section_c 1 N/I 0xC 0xC .absSeg148\r
+.abs_section_e4 1 N/I 0xE4 0xE4 .absSeg149\r
+.abs_section_e2 1 N/I 0xE2 0xE2 .absSeg150\r
+.abs_section_e5 1 N/I 0xE5 0xE5 .absSeg151\r
+.abs_section_e0 1 N/I 0xE0 0xE0 .absSeg152\r
+.abs_section_e1 1 N/I 0xE1 0xE1 .absSeg153\r
+.abs_section_e3 1 N/I 0xE3 0xE3 .absSeg154\r
+.abs_section_e8 1 N/I 0xE8 0xE8 .absSeg155\r
+.abs_section_e9 1 N/I 0xE9 0xE9 .absSeg156\r
+.abs_section_fe 1 N/I 0xFE 0xFE .absSeg157\r
+.abs_section_273 1 N/I 0x273 0x273 .absSeg158\r
+.abs_section_d 1 N/I 0xD 0xD .absSeg159\r
+.abs_section_26b 1 N/I 0x26B 0x26B .absSeg160\r
+.abs_section_253 1 N/I 0x253 0x253 .absSeg161\r
+.abs_section_25b 1 N/I 0x25B 0x25B .absSeg162\r
+.abs_section_24b 1 N/I 0x24B 0x24B .absSeg163\r
+.abs_section_243 1 N/I 0x243 0x243 .absSeg164\r
+.abs_section_35 1 N/I 0x35 0x35 .absSeg165\r
+.abs_section_3b 1 N/I 0x3B 0x3B .absSeg166\r
+.abs_section_ca 1 N/I 0xCA 0xCA .absSeg167\r
+.abs_section_cb 1 N/I 0xCB 0xCB .absSeg168\r
+.abs_section_ce 1 N/I 0xCE 0xCE .absSeg169\r
+.abs_section_cf 1 N/I 0xCF 0xCF .absSeg170\r
+.abs_section_cc 1 N/I 0xCC 0xCC .absSeg171\r
+.abs_section_cd 1 N/I 0xCD 0xCD .absSeg172\r
+.abs_section_da 1 N/I 0xDA 0xDA .absSeg173\r
+.abs_section_d8 1 N/I 0xD8 0xD8 .absSeg174\r
+.abs_section_d9 1 N/I 0xD9 0xD9 .absSeg175\r
+.abs_section_dd 1 N/I 0xDD 0xDD .absSeg176\r
+.abs_section_db 1 N/I 0xDB 0xDB .absSeg177\r
+.abs_section_34 1 N/I 0x34 0x34 .absSeg178\r
+.abs_section_48 1 N/I 0x48 0x48 .absSeg179\r
+.abs_section_49 1 N/I 0x49 0x49 .absSeg180\r
+.abs_section_4a 1 N/I 0x4A 0x4A .absSeg181\r
+.abs_section_4b 1 N/I 0x4B 0x4B .absSeg182\r
+.abs_section_4e 1 N/I 0x4E 0x4E .absSeg183\r
+.abs_section_4f 1 N/I 0x4F 0x4F .absSeg184\r
+.abs_section_4c 1 N/I 0x4C 0x4C .absSeg185\r
+.abs_section_40 1 N/I 0x40 0x40 .absSeg186\r
+.abs_section_46 1 N/I 0x46 0x46 .absSeg187\r
+.abs_section_4d 1 N/I 0x4D 0x4D .absSeg188\r
+.abs_section_47 1 N/I 0x47 0x47 .absSeg189\r
+.abs_section_256 1 N/I 0x256 0x256 .absSeg190\r
+.abs_section_24e 1 N/I 0x24E 0x24E .absSeg191\r
+.abs_section_82 2 N/I 0x82 0x83 .absSeg192\r
+.abs_section_84 2 N/I 0x84 0x85 .absSeg193\r
+.abs_section_90 2 N/I 0x90 0x91 .absSeg194\r
+.abs_section_92 2 N/I 0x92 0x93 .absSeg195\r
+.abs_section_94 2 N/I 0x94 0x95 .absSeg196\r
+.abs_section_96 2 N/I 0x96 0x97 .absSeg197\r
+.abs_section_98 2 N/I 0x98 0x99 .absSeg198\r
+.abs_section_9a 2 N/I 0x9A 0x9B .absSeg199\r
+.abs_section_9c 2 N/I 0x9C 0x9D .absSeg200\r
+.abs_section_9e 2 N/I 0x9E 0x9F .absSeg201\r
+.abs_section_2 2 N/I 0x2 0x3 .absSeg202\r
+.abs_section_62 2 N/I 0x62 0x63 .absSeg203\r
+.abs_section_0 2 N/I 0x0 0x1 .absSeg204\r
+.abs_section_ec 2 N/I 0xEC 0xED .absSeg205\r
+.abs_section_ee 2 N/I 0xEE 0xEF .absSeg206\r
+.abs_section_f0 2 N/I 0xF0 0xF1 .absSeg207\r
+.abs_section_f8 2 N/I 0xF8 0xF9 .absSeg208\r
+.abs_section_fa 2 N/I 0xFA 0xFB .absSeg209\r
+.abs_section_fc 2 N/I 0xFC 0xFD .absSeg210\r
+.abs_section_f2 2 N/I 0xF2 0xF3 .absSeg211\r
+.abs_section_f4 2 N/I 0xF4 0xF5 .absSeg212\r
+.abs_section_f6 2 N/I 0xF6 0xF7 .absSeg213\r
+.abs_section_c8 2 N/I 0xC8 0xC9 .absSeg214\r
+.abs_section_50 2 N/I 0x50 0x51 .absSeg215\r
+.abs_section_52 2 N/I 0x52 0x53 .absSeg216\r
+.abs_section_54 2 N/I 0x54 0x55 .absSeg217\r
+.abs_section_56 2 N/I 0x56 0x57 .absSeg218\r
+.abs_section_58 2 N/I 0x58 0x59 .absSeg219\r
+.abs_section_5a 2 N/I 0x5A 0x5B .absSeg220\r
+.abs_section_5c 2 N/I 0x5C 0x5D .absSeg221\r
+.abs_section_5e 2 N/I 0x5E 0x5F .absSeg222\r
+.abs_section_44 2 N/I 0x44 0x45 .absSeg223\r
+.abs_section_ff80 128 R 0xFF80 0xFFFF .absSeg224\r
+.bss 1968 R/W 0x801 0xFB0 RAM\r
+RUNTIME 373 R 0xD199 0xD30D ROM_C000\r
+.common 2 R/W 0xFB1 0xFB2 RAM\r
+TickTimer_CODE 149 R 0xD30E 0xD3A2 ROM_C000\r
+ButtonInterrupt_CODE 10 R 0xD3A3 0xD3AC ROM_C000\r
+Byte1_CODE 23 R 0xD3AD 0xD3C3 ROM_C000\r
+Byte1_DATA 8 R/W 0xFB3 0xFBA RAM\r
+TickTimer_DATA 3 R/W 0xFBB 0xFBD RAM\r
+.stack 48 R/W 0xFBE 0xFED RAM\r
+\r
+Summary of section sizes per section type:\r
+READ_ONLY (R): 1457 (dec: 5207)\r
+READ_WRITE (R/W): 7EE (dec: 2030)\r
+NO_INIT (N/I): 100 (dec: 256)\r
+\r
+*********************************************************************************************\r
+VECTOR-ALLOCATION SECTION\r
+ Address InitValue InitFunction\r
+---------------------------------------------------------------------------------------------\r
+\r
+*********************************************************************************************\r
+OBJECT-ALLOCATION SECTION\r
+ Name Module Addr hSize dSize Ref Section RLIB\r
+---------------------------------------------------------------------------------------------\r
+MODULE: -- Start12.c.o --\r
+- PROCEDURES:\r
+ Init C153 29 41 1 .text \r
+ _Startup C17C 10 16 1 .text \r
+- VARIABLES:\r
+ _startupData C076 17 23 6 .startData \r
+MODULE: -- STRING.C.o (ansisi.lib) --\r
+- PROCEDURES:\r
+ _memcpy_8bitCount C18C 1C 28 3 .text \r
+ memset C1A8 1E 30 1 .text \r
+ strncpy C1C6 2D 45 1 .text \r
+- VARIABLES:\r
+MODULE: -- rtshc12.c.o (ansisi.lib) --\r
+- PROCEDURES:\r
+ _LCMP D199 19 25 2 RUNTIME \r
+ _LCMP_P D1B2 15 21 2 RUNTIME \r
+ _LNEG D1C7 D 13 1 RUNTIME \r
+ _LINC D1D4 5 5 4 RUNTIME \r
+ _lDivMod D1D9 E3 227 3 RUNTIME \r
+ _LDIVU D2BC E 14 1 RUNTIME \r
+ _NEG_P D2CA F 15 4 RUNTIME \r
+ _LDIVS D2D9 35 53 1 RUNTIME \r
+- VARIABLES:\r
+MODULE: -- tasks.c.o --\r
+- PROCEDURES:\r
+ xTaskCreate C1F3 CE 206 11 .text \r
+ vTaskDelayUntil C2C1 74 116 3 .text \r
+ vTaskDelay C335 46 70 4 .text \r
+ uxTaskPriorityGet C37B 26 38 1 .text \r
+ vTaskPrioritySet C3A1 69 105 2 .text \r
+ vTaskSuspend C40A 44 68 3 .text \r
+ vTaskResume C44E 59 89 3 .text \r
+ vTaskStartScheduler C4A7 30 48 1 .text \r
+ vTaskSuspendAll C4D7 13 19 11 .text \r
+ xTaskResumeAll C4EA 9F 159 13 .text \r
+ xTaskGetTickCount C589 17 23 2 .text \r
+ vTaskIncrementTick C5A0 81 129 2 .text \r
+ vTaskSwitchContext C621 5B 91 3 .text \r
+ vTaskPlaceOnEventList C67C 3E 62 2 .text \r
+ xTaskRemoveFromEventList C6BA 65 101 3 .text \r
+ prvIdleTask C71F 10 16 1 .text \r
+ prvInitialiseTCBVariables C72F 4A 74 1 .text \r
+ prvInitialiseTaskLists C779 37 55 1 .text \r
+ prvCheckTasksWaitingTermination C7B0 1 1 1 .text \r
+ prvAllocateTCBAndStack C7B1 39 57 1 .text \r
+- VARIABLES:\r
+ STRING.IDLE.2 C093 5 5 1 .rodata1 \r
+ pxCurrentTCB 801 2 2 29 .bss \r
+ uxCurrentNumberOfTasks 803 1 1 3 .bss \r
+ xTickCount 804 2 2 14 .bss \r
+ uxTopUsedPriority 806 1 1 2 .bss \r
+ uxTopReadyPriority 807 1 1 15 .bss \r
+ xSchedulerRunning 808 1 1 3 .bss \r
+ uxSchedulerSuspended 809 1 1 6 .bss \r
+ uxMissedTicks 80A 1 1 4 .bss \r
+ uxTaskNumber.1 80B 1 1 2 .bss \r
+ pxReadyTasksLists 80C 3C 60 11 .bss \r
+ xDelayedTaskList1 848 F 15 2 .bss \r
+ xDelayedTaskList2 857 F 15 2 .bss \r
+ pxDelayedTaskList 866 2 2 8 .bss \r
+ pxOverflowDelayedTaskList 868 2 2 6 .bss \r
+ xPendingReadyList 86A F 15 4 .bss \r
+ xSuspendedTaskList 879 F 15 2 .bss \r
+MODULE: -- queue.c.o --\r
+- PROCEDURES:\r
+ xQueueCreate C7EA 76 118 3 .text \r
+ xQueueSend C860 C9 201 3 .text \r
+ xQueueSendFromISR C929 58 88 1 .text \r
+ xQueueReceive C981 C3 195 4 .text \r
+ uxQueueMessagesWaiting CA44 1B 27 1 .text \r
+ prvUnlockQueue CA5F 6F 111 4 .text \r
+ prvIsQueueEmpty CACE 21 33 1 .text \r
+ prvIsQueueFull CAEF 24 36 1 .text \r
+- VARIABLES:\r
+MODULE: -- list.c.o --\r
+- PROCEDURES:\r
+ vListInitialise CB13 1F 31 7 .text \r
+ vListInitialiseItem CB32 7 7 3 .text \r
+ vListInsertEnd CB39 25 37 7 .text \r
+ vListInsert CB5E 54 84 4 .text \r
+ vListRemove CBB2 23 35 13 .text \r
+- VARIABLES:\r
+MODULE: -- port.c.o --\r
+- PROCEDURES:\r
+ pxPortInitialiseStack CBD5 2B 43 1 .text \r
+ prvSetupTimerInterrupt CC00 9 9 1 .text \r
+ xPortStartScheduler CC09 4 4 1 .text \r
+ xBankedStartScheduler C0E1 F 15 1 NON_BANKED \r
+ vPortYield C0F0 16 22 1 NON_BANKED \r
+ vPortTickInterrupt C106 1D 29 1 NON_BANKED \r
+- VARIABLES:\r
+ uxCriticalNesting 800 1 1 91 .data \r
+MODULE: -- flash.c.o --\r
+- PROCEDURES:\r
+ vStartLEDFlashTasks CC0D 2E 46 1 .text \r
+ vLEDFlashTask CC3B 52 82 1 .text \r
+- VARIABLES:\r
+ STRING.LEDx.1 C098 5 5 1 .rodata1 \r
+ uxFlashTaskNumber 888 1 1 2 .bss \r
+MODULE: -- main.c.o --\r
+- PROCEDURES:\r
+ vMain CC8D 42 66 1 .text \r
+ vErrorChecks CCCF 35 53 1 .text \r
+ prvCheckOtherTasksAreStillRunning CD04 26 38 1 .text \r
+ vApplicationIdleHook CD2A 73 115 1 .text \r
+ vButtonTask CD9D 4F 79 1 .text \r
+ vButtonPush C123 2F 47 1 NON_BANKED \r
+- VARIABLES:\r
+ STRING.Check.1 C09D 6 6 1 .rodata1 \r
+ STRING.Button.2 C0A3 7 7 1 .rodata1 \r
+ xLocalError 889 1 1 3 .bss \r
+ uxValToSend.3 88A 1 1 2 .bss \r
+ xButtonQueue 88B 2 2 3 .bss \r
+MODULE: -- heap_1.c.o --\r
+- PROCEDURES:\r
+ pvPortMalloc CDEC 2D 45 4 .text \r
+ vPortFree CE19 1 1 2 .text \r
+- VARIABLES:\r
+ xNextFreeByte 88D 2 2 4 .bss \r
+ xHeap 88F 704 1796 1 .bss \r
+MODULE: -- ParTest.c.o --\r
+- PROCEDURES:\r
+ vParTestToggleLED CE1A 13 19 4 .text \r
+- VARIABLES:\r
+MODULE: -- Cpu.C.o --\r
+- PROCEDURES:\r
+ _EntryPoint C000 2E 46 1 .init \r
+ PE_low_level_init C02E 48 72 1 .init \r
+ Cpu_Interrupt C152 1 1 60 NON_BANKED \r
+- VARIABLES:\r
+MODULE: -- Byte1.C.o --\r
+- PROCEDURES:\r
+ Byte1_GetMsk D3AD D 13 1 Byte1_CODE \r
+ Byte1_NegBit D3BA A 10 1 Byte1_CODE \r
+- VARIABLES:\r
+ Byte1_Table FB3 8 8 1 Byte1_DATA \r
+MODULE: -- TickTimer.C.o --\r
+- PROCEDURES:\r
+ SetCV D30E B 11 2 TickTimer_CODE\r
+ SetPV D319 9 9 1 TickTimer_CODE\r
+ HWEnDi D322 11 17 2 TickTimer_CODE\r
+ TickTimer_Enable D333 E 14 1 TickTimer_CODE\r
+ TickTimer_SetFreqHz D341 4E 78 1 TickTimer_CODE\r
+ TickTimer_Init D38F 14 20 1 TickTimer_CODE\r
+- VARIABLES:\r
+ EnUser FBB 1 1 4 TickTimer_DATA\r
+ CmpHighVal FBC 2 2 2 TickTimer_DATA\r
+MODULE: -- IO_Map.C.o --\r
+- PROCEDURES:\r
+- VARIABLES:\r
+ _ARMCOP 3F 1 1 0 .abs_section_3f\r
+ _ATDDIEN 8D 1 1 0 .abs_section_8d\r
+ _ATDSTAT0 86 1 1 0 .abs_section_86\r
+ _ATDSTAT1 8B 1 1 0 .abs_section_8b\r
+ _BDMCCR FF06 1 1 0 .abs_section_ff06\r
+ _BDMINR FF07 1 1 0 .abs_section_ff07\r
+ _BDMSTS FF01 1 1 0 .abs_section_ff01\r
+ _BKP0H 2B 1 1 0 .abs_section_2b\r
+ _BKP0L 2C 1 1 0 .abs_section_2c\r
+ _BKP0X 2A 1 1 0 .abs_section_2a\r
+ _BKP1H 2E 1 1 0 .abs_section_2e\r
+ _BKP1L 2F 1 1 0 .abs_section_2f\r
+ _BKP1X 2D 1 1 0 .abs_section_2d\r
+ _BKPCT0 28 1 1 0 .abs_section_28\r
+ _BKPCT1 29 1 1 0 .abs_section_29\r
+ _CANBTR0 142 1 1 0 .abs_section_142\r
+ _CANBTR1 143 1 1 0 .abs_section_143\r
+ _CANCTL0 140 1 1 0 .abs_section_140\r
+ _CANCTL1 141 1 1 0 .abs_section_141\r
+ _CANIDAC 14B 1 1 0 .abs_section_14b\r
+ _CANIDAR0 150 1 1 0 .abs_section_150\r
+ _CANIDAR1 151 1 1 0 .abs_section_151\r
+ _CANIDAR2 152 1 1 0 .abs_section_152\r
+ _CANIDAR3 153 1 1 0 .abs_section_153\r
+ _CANIDAR4 158 1 1 0 .abs_section_158\r
+ _CANIDAR5 159 1 1 0 .abs_section_159\r
+ _CANIDAR6 15A 1 1 0 .abs_section_15a\r
+ _CANIDAR7 15B 1 1 0 .abs_section_15b\r
+ _CANIDMR0 154 1 1 0 .abs_section_154\r
+ _CANIDMR1 155 1 1 0 .abs_section_155\r
+ _CANIDMR2 156 1 1 0 .abs_section_156\r
+ _CANIDMR3 157 1 1 0 .abs_section_157\r
+ _CANIDMR4 15C 1 1 0 .abs_section_15c\r
+ _CANIDMR5 15D 1 1 0 .abs_section_15d\r
+ _CANIDMR6 15E 1 1 0 .abs_section_15e\r
+ _CANIDMR7 15F 1 1 0 .abs_section_15f\r
+ _CANRFLG 144 1 1 0 .abs_section_144\r
+ _CANRIER 145 1 1 0 .abs_section_145\r
+ _CANRXDLR 16C 1 1 0 .abs_section_16c\r
+ _CANRXDSR0 164 1 1 0 .abs_section_164\r
+ _CANRXDSR1 165 1 1 0 .abs_section_165\r
+ _CANRXDSR2 166 1 1 0 .abs_section_166\r
+ _CANRXDSR3 167 1 1 0 .abs_section_167\r
+ _CANRXDSR4 168 1 1 0 .abs_section_168\r
+ _CANRXDSR5 169 1 1 0 .abs_section_169\r
+ _CANRXDSR6 16A 1 1 0 .abs_section_16a\r
+ _CANRXDSR7 16B 1 1 0 .abs_section_16b\r
+ _CANRXERR 14E 1 1 0 .abs_section_14e\r
+ _CANRXIDR0 160 1 1 0 .abs_section_160\r
+ _CANRXIDR1 161 1 1 0 .abs_section_161\r
+ _CANRXIDR2 162 1 1 0 .abs_section_162\r
+ _CANRXIDR3 163 1 1 0 .abs_section_163\r
+ _CANTAAK 149 1 1 0 .abs_section_149\r
+ _CANTARQ 148 1 1 0 .abs_section_148\r
+ _CANTBSEL 14A 1 1 0 .abs_section_14a\r
+ _CANTFLG 146 1 1 0 .abs_section_146\r
+ _CANTIER 147 1 1 0 .abs_section_147\r
+ _CANTXDLR 17C 1 1 0 .abs_section_17c\r
+ _CANTXDSR0 174 1 1 0 .abs_section_174\r
+ _CANTXDSR1 175 1 1 0 .abs_section_175\r
+ _CANTXDSR2 176 1 1 0 .abs_section_176\r
+ _CANTXDSR3 177 1 1 0 .abs_section_177\r
+ _CANTXDSR4 178 1 1 0 .abs_section_178\r
+ _CANTXDSR5 179 1 1 0 .abs_section_179\r
+ _CANTXDSR6 17A 1 1 0 .abs_section_17a\r
+ _CANTXDSR7 17B 1 1 0 .abs_section_17b\r
+ _CANTXERR 14F 1 1 0 .abs_section_14f\r
+ _CANTXIDR0 170 1 1 0 .abs_section_170\r
+ _CANTXIDR1 171 1 1 0 .abs_section_171\r
+ _CANTXIDR2 172 1 1 0 .abs_section_172\r
+ _CANTXIDR3 173 1 1 0 .abs_section_173\r
+ _CANTXTBPR 17F 1 1 0 .abs_section_17f\r
+ _CFORC 41 1 1 0 .abs_section_41\r
+ _CLKSEL 39 1 1 3 .abs_section_39\r
+ _COPCTL 3C 1 1 0 .abs_section_3c\r
+ _CRGFLG 37 1 1 1 .abs_section_37\r
+ _CRGINT 38 1 1 0 .abs_section_38\r
+ _CTCTL 3E 1 1 0 .abs_section_3e\r
+ _CTFLG 36 1 1 0 .abs_section_36\r
+ _DDRAD 272 1 1 0 .abs_section_272\r
+ _DDRE 9 1 1 0 .abs_section_9\r
+ _DDRJ 26A 1 1 0 .abs_section_26a\r
+ _DDRK 33 1 1 0 .abs_section_33\r
+ _DDRM 252 1 1 0 .abs_section_252\r
+ _DDRP 25A 1 1 1 .abs_section_25a\r
+ _DDRS 24A 1 1 0 .abs_section_24a\r
+ _DDRT 242 1 1 0 .abs_section_242\r
+ _EBICTL E 1 1 0 .abs_section_e\r
+ _FCLKDIV 100 1 1 0 .abs_section_100\r
+ _FCMD 106 1 1 0 .abs_section_106\r
+ _FCNFG 103 1 1 0 .abs_section_103\r
+ _FPROT 104 1 1 0 .abs_section_104\r
+ _FSEC 101 1 1 0 .abs_section_101\r
+ _FSTAT 105 1 1 0 .abs_section_105\r
+ _HPRIO 1F 1 1 0 .abs_section_1f\r
+ _INITEE 12 1 1 0 .abs_section_12\r
+ _INITRG 11 1 1 0 .abs_section_11\r
+ _INITRM 10 1 1 1 .abs_section_10\r
+ _INTCR 1E 1 1 1 .abs_section_1e\r
+ _ITCR 15 1 1 0 .abs_section_15\r
+ _ITEST 16 1 1 0 .abs_section_16\r
+ _MEMSIZ0 1C 1 1 0 .abs_section_1c\r
+ _MEMSIZ1 1D 1 1 0 .abs_section_1d\r
+ _MISC 13 1 1 1 .abs_section_13\r
+ _MODE B 1 1 0 .abs_section_b\r
+ _MODRR 247 1 1 0 .abs_section_247\r
+ _MTST0 14 1 1 0 .abs_section_14\r
+ _MTST1 17 1 1 0 .abs_section_17\r
+ _OC7D 43 1 1 0 .abs_section_43\r
+ _OC7M 42 1 1 0 .abs_section_42\r
+ _PACTL 60 1 1 0 .abs_section_60\r
+ _PAFLG 61 1 1 0 .abs_section_61\r
+ _PARTIDH 1A 1 1 0 .abs_section_1a\r
+ _PARTIDL 1B 1 1 0 .abs_section_1b\r
+ _PEAR A 1 1 0 .abs_section_a\r
+ _PERAD 274 1 1 0 .abs_section_274\r
+ _PERJ 26C 1 1 0 .abs_section_26c\r
+ _PERM 254 1 1 0 .abs_section_254\r
+ _PERP 25C 1 1 1 .abs_section_25c\r
+ _PERS 24C 1 1 0 .abs_section_24c\r
+ _PERT 244 1 1 0 .abs_section_244\r
+ _PIEJ 26E 1 1 0 .abs_section_26e\r
+ _PIEP 25E 1 1 2 .abs_section_25e\r
+ _PIFJ 26F 1 1 0 .abs_section_26f\r
+ _PIFP 25F 1 1 2 .abs_section_25f\r
+ _PLLCTL 3A 1 1 3 .abs_section_3a\r
+ _PORTAD0 8F 1 1 0 .abs_section_8f\r
+ _PORTE 8 1 1 0 .abs_section_8\r
+ _PORTK 32 1 1 0 .abs_section_32\r
+ _PPAGE 30 1 1 0 .abs_section_30\r
+ _PPSAD 275 1 1 0 .abs_section_275\r
+ _PPSJ 26D 1 1 0 .abs_section_26d\r
+ _PPSM 255 1 1 0 .abs_section_255\r
+ _PPSP 25D 1 1 1 .abs_section_25d\r
+ _PPSS 24D 1 1 0 .abs_section_24d\r
+ _PPST 245 1 1 0 .abs_section_245\r
+ _PTAD 270 1 1 0 .abs_section_270\r
+ _PTIAD 271 1 1 0 .abs_section_271\r
+ _PTIJ 269 1 1 0 .abs_section_269\r
+ _PTIM 251 1 1 0 .abs_section_251\r
+ _PTIP 259 1 1 0 .abs_section_259\r
+ _PTIS 249 1 1 0 .abs_section_249\r
+ _PTIT 241 1 1 0 .abs_section_241\r
+ _PTJ 268 1 1 0 .abs_section_268\r
+ _PTM 250 1 1 0 .abs_section_250\r
+ _PTP 258 1 1 0 .abs_section_258\r
+ _PTS 248 1 1 0 .abs_section_248\r
+ _PTT 240 1 1 0 .abs_section_240\r
+ _PUCR C 1 1 0 .abs_section_c\r
+ _PWMCAE E4 1 1 0 .abs_section_e4\r
+ _PWMCLK E2 1 1 0 .abs_section_e2\r
+ _PWMCTL E5 1 1 1 .abs_section_e5\r
+ _PWME E0 1 1 0 .abs_section_e0\r
+ _PWMPOL E1 1 1 0 .abs_section_e1\r
+ _PWMPRCLK E3 1 1 0 .abs_section_e3\r
+ _PWMSCLA E8 1 1 0 .abs_section_e8\r
+ _PWMSCLB E9 1 1 0 .abs_section_e9\r
+ _PWMSDN FE 1 1 1 .abs_section_fe\r
+ _RDRAD 273 1 1 0 .abs_section_273\r
+ _RDRIV D 1 1 0 .abs_section_d\r
+ _RDRJ 26B 1 1 0 .abs_section_26b\r
+ _RDRM 253 1 1 0 .abs_section_253\r
+ _RDRP 25B 1 1 0 .abs_section_25b\r
+ _RDRS 24B 1 1 0 .abs_section_24b\r
+ _RDRT 243 1 1 0 .abs_section_243\r
+ _REFDV 35 1 1 1 .abs_section_35\r
+ _RTICTL 3B 1 1 0 .abs_section_3b\r
+ _SCICR1 CA 1 1 0 .abs_section_ca\r
+ _SCICR2 CB 1 1 0 .abs_section_cb\r
+ _SCIDRH CE 1 1 0 .abs_section_ce\r
+ _SCIDRL CF 1 1 0 .abs_section_cf\r
+ _SCISR1 CC 1 1 0 .abs_section_cc\r
+ _SCISR2 CD 1 1 0 .abs_section_cd\r
+ _SPIBR DA 1 1 0 .abs_section_da\r
+ _SPICR1 D8 1 1 0 .abs_section_d8\r
+ _SPICR2 D9 1 1 0 .abs_section_d9\r
+ _SPIDR DD 1 1 0 .abs_section_dd\r
+ _SPISR DB 1 1 0 .abs_section_db\r
+ _SYNR 34 1 1 1 .abs_section_34\r
+ _TCTL1 48 1 1 1 .abs_section_48\r
+ _TCTL2 49 1 1 1 .abs_section_49\r
+ _TCTL3 4A 1 1 0 .abs_section_4a\r
+ _TCTL4 4B 1 1 0 .abs_section_4b\r
+ _TFLG1 4E 1 1 2 .abs_section_4e\r
+ _TFLG2 4F 1 1 0 .abs_section_4f\r
+ _TIE 4C 1 1 3 .abs_section_4c\r
+ _TIOS 40 1 1 1 .abs_section_40\r
+ _TSCR1 46 1 1 3 .abs_section_46\r
+ _TSCR2 4D 1 1 5 .abs_section_4d\r
+ _TTOV 47 1 1 1 .abs_section_47\r
+ _WOMM 256 1 1 0 .abs_section_256\r
+ _WOMS 24E 1 1 0 .abs_section_24e\r
+ _ATDCTL23 82 2 2 0 .abs_section_82\r
+ _ATDCTL45 84 2 2 0 .abs_section_84\r
+ _ATDDR0 90 2 2 0 .abs_section_90\r
+ _ATDDR1 92 2 2 0 .abs_section_92\r
+ _ATDDR2 94 2 2 0 .abs_section_94\r
+ _ATDDR3 96 2 2 0 .abs_section_96\r
+ _ATDDR4 98 2 2 0 .abs_section_98\r
+ _ATDDR5 9A 2 2 0 .abs_section_9a\r
+ _ATDDR6 9C 2 2 0 .abs_section_9c\r
+ _ATDDR7 9E 2 2 0 .abs_section_9e\r
+ _DDRAB 2 2 2 1 .abs_section_2\r
+ _PACNT 62 2 2 0 .abs_section_62\r
+ _PORTAB 0 2 2 3 .abs_section_0\r
+ _PWMCNT01 EC 2 2 0 .abs_section_ec\r
+ _PWMCNT23 EE 2 2 0 .abs_section_ee\r
+ _PWMCNT45 F0 2 2 0 .abs_section_f0\r
+ _PWMDTY01 F8 2 2 0 .abs_section_f8\r
+ _PWMDTY23 FA 2 2 0 .abs_section_fa\r
+ _PWMDTY45 FC 2 2 0 .abs_section_fc\r
+ _PWMPER01 F2 2 2 0 .abs_section_f2\r
+ _PWMPER23 F4 2 2 0 .abs_section_f4\r
+ _PWMPER45 F6 2 2 0 .abs_section_f6\r
+ _SCIBD C8 2 2 0 .abs_section_c8\r
+ _TC0 50 2 2 1 .abs_section_50\r
+ _TC1 52 2 2 0 .abs_section_52\r
+ _TC2 54 2 2 0 .abs_section_54\r
+ _TC3 56 2 2 0 .abs_section_56\r
+ _TC4 58 2 2 0 .abs_section_58\r
+ _TC5 5A 2 2 0 .abs_section_5a\r
+ _TC6 5C 2 2 0 .abs_section_5c\r
+ _TC7 5E 2 2 1 .abs_section_5e\r
+ _TCNT 44 2 2 0 .abs_section_44\r
+MODULE: -- PE_Timer.C.o --\r
+- PROCEDURES:\r
+ PE_Timer_LngHi1 CE2D 4A 74 1 .text \r
+- VARIABLES:\r
+MODULE: -- Vectors.c.o --\r
+- PROCEDURES:\r
+- VARIABLES:\r
+ _vect FF80 80 128 0 .abs_section_ff80\r
+MODULE: -- RTOSDemo.C.o --\r
+- PROCEDURES:\r
+ main CE77 8 8 0 .text \r
+- VARIABLES:\r
+MODULE: -- PollQ.c.o --\r
+- PROCEDURES:\r
+ vStartPolledQueueTasks CE7F 42 66 1 .text \r
+ vPolledQueueProducer CEC1 4D 77 1 .text \r
+ vPolledQueueConsumer CF0E 59 89 1 .text \r
+ xArePollingQueuesStillRunning CF67 15 21 1 .text \r
+- VARIABLES:\r
+ STRING.QConsNB.2 C0AA 8 8 1 .rodata1 \r
+ STRING.QProdNB.3 C0B2 8 8 1 .rodata1 \r
+ xPollingConsumerCount F93 1 1 3 .bss \r
+ xPollingProducerCount F94 1 1 3 .bss \r
+ xPolledQueue.1 F95 2 2 3 .bss \r
+MODULE: -- dynamic.c.o --\r
+- PROCEDURES:\r
+ vStartDynamicPriorityTasks CF7C 7C 124 1 .text \r
+ vLimitedIncrementTask CFF8 26 38 1 .text \r
+ vContinuousIncrementTask D01E 35 53 1 .text \r
+ vCounterControlTask D053 98 152 3 .text \r
+ vQueueSendWhenSuspendedTask D0EB 34 52 1 .text \r
+ vQueueReceiveWhenSuspendedTask D11F 4F 79 1 .text \r
+ xAreDynamicPriorityTasksStillRunning D16E 2B 43 1 .text \r
+- VARIABLES:\r
+ STRING.CNT_INC.1 C0BA 8 8 1 .rodata1 \r
+ STRING.LIM_INC.2 C0C2 8 8 1 .rodata1 \r
+ STRING.C_CTRL.3 C0CA 7 7 1 .rodata1 \r
+ STRING.SUSP_TX.4 C0D1 8 8 1 .rodata1 \r
+ STRING.SUSP_RX.5 C0D9 8 8 1 .rodata1 \r
+ usCheckVariable F97 2 2 3 .bss \r
+ xSuspendedQueueSendError F99 1 1 2 .bss \r
+ xSuspendedQueueReceiveError F9A 1 1 3 .bss \r
+ ulValueToSend.6 F9B 4 4 5 .bss \r
+ ulExpectedValue.7 F9F 4 4 6 .bss \r
+ usLastTaskCheck.9 FA3 2 2 2 .bss \r
+ xContinousIncrementHandle FA5 2 2 5 .bss \r
+ xLimitedIncrementHandle FA7 2 2 2 .bss \r
+ ulCounter FA9 4 4 10 .bss \r
+ ulReceivedValue.8 FAD 4 4 3 .bss \r
+ xSuspendedTestQueue FB1 2 2 3 .common \r
+MODULE: -- ButtonInterrupt.C.o --\r
+- PROCEDURES:\r
+ ButtonInterrupt_Enable D3A3 A 10 1 ButtonInterrupt_CODE\r
+- VARIABLES:\r
+\r
+*********************************************************************************************\r
+MODULE STATISTIC\r
+ Name Data Code Const\r
+---------------------------------------------------------------------------------------------\r
+ Start12.c.o 0 57 0\r
+ STRING.C.o (ansisi.lib) 0 103 0\r
+ rtshc12.c.o (ansisi.lib) 0 373 0\r
+ tasks.c.o 135 1527 5\r
+ queue.c.o 0 809 0\r
+ list.c.o 0 194 0\r
+ port.c.o 1 122 0\r
+ flash.c.o 1 128 5\r
+ main.c.o 4 398 13\r
+ heap_1.c.o 1798 46 0\r
+ ParTest.c.o 0 19 0\r
+ Cpu.C.o 0 119 0\r
+ Byte1.C.o 8 23 0\r
+ TickTimer.C.o 3 149 0\r
+ IO_Map.C.o 256 0 0\r
+ PE_Timer.C.o 0 74 0\r
+ Vectors.c.o 0 0 128\r
+ RTOSDemo.C.o 0 8 0\r
+ PollQ.c.o 4 253 16\r
+ dynamic.c.o 28 541 39\r
+ ButtonInterrupt.C.o 0 10 0\r
+ other 48 29 19\r
+\r
+*********************************************************************************************\r
+SECTION USE IN OBJECT-ALLOCATION SECTION\r
+---------------------------------------------------------------------------------------------\r
+SECTION: ".text"\r
+ Init _Startup _memcpy_8bitCount memset strncpy xTaskCreate vTaskDelayUntil \r
+ vTaskDelay uxTaskPriorityGet vTaskPrioritySet vTaskSuspend vTaskResume \r
+ vTaskStartScheduler vTaskSuspendAll xTaskResumeAll xTaskGetTickCount \r
+ vTaskIncrementTick vTaskSwitchContext vTaskPlaceOnEventList \r
+ xTaskRemoveFromEventList prvIdleTask prvInitialiseTCBVariables \r
+ prvInitialiseTaskLists prvCheckTasksWaitingTermination prvAllocateTCBAndStack \r
+ xQueueCreate xQueueSend xQueueSendFromISR xQueueReceive \r
+ uxQueueMessagesWaiting prvUnlockQueue prvIsQueueEmpty prvIsQueueFull \r
+ vListInitialise vListInitialiseItem vListInsertEnd vListInsert vListRemove \r
+ pxPortInitialiseStack prvSetupTimerInterrupt xPortStartScheduler \r
+ vStartLEDFlashTasks vLEDFlashTask vMain vErrorChecks \r
+ prvCheckOtherTasksAreStillRunning vApplicationIdleHook vButtonTask \r
+ pvPortMalloc vPortFree vParTestToggleLED PE_Timer_LngHi1 main \r
+ vStartPolledQueueTasks vPolledQueueProducer vPolledQueueConsumer \r
+ xArePollingQueuesStillRunning vStartDynamicPriorityTasks \r
+ vLimitedIncrementTask vContinuousIncrementTask vCounterControlTask \r
+ vQueueSendWhenSuspendedTask vQueueReceiveWhenSuspendedTask \r
+ xAreDynamicPriorityTasksStillRunning \r
+SECTION: ".data"\r
+ uxCriticalNesting \r
+SECTION: ".bss"\r
+ pxCurrentTCB uxCurrentNumberOfTasks xTickCount uxTopUsedPriority \r
+ uxTopReadyPriority xSchedulerRunning uxSchedulerSuspended uxMissedTicks \r
+ uxTaskNumber.1 pxReadyTasksLists xDelayedTaskList1 xDelayedTaskList2 \r
+ pxDelayedTaskList pxOverflowDelayedTaskList xPendingReadyList \r
+ xSuspendedTaskList uxFlashTaskNumber xLocalError uxValToSend.3 xButtonQueue \r
+ xNextFreeByte xHeap xPollingConsumerCount xPollingProducerCount \r
+ xPolledQueue.1 usCheckVariable xSuspendedQueueSendError \r
+ xSuspendedQueueReceiveError ulValueToSend.6 ulExpectedValue.7 \r
+ usLastTaskCheck.9 xContinousIncrementHandle xLimitedIncrementHandle ulCounter \r
+ ulReceivedValue.8 \r
+SECTION: ".init"\r
+ _EntryPoint PE_low_level_init \r
+SECTION: ".rodata1"\r
+ STRING.IDLE.2 STRING.LEDx.1 STRING.Check.1 STRING.Button.2 STRING.QConsNB.2 \r
+ STRING.QProdNB.3 STRING.CNT_INC.1 STRING.LIM_INC.2 STRING.C_CTRL.3 \r
+ STRING.SUSP_TX.4 STRING.SUSP_RX.5 \r
+SECTION: "NON_BANKED"\r
+ xBankedStartScheduler vPortYield vPortTickInterrupt vButtonPush \r
+ Cpu_Interrupt \r
+SECTION: "RUNTIME"\r
+ _LCMP _LCMP_P _LNEG _LINC _lDivMod _LDIVU _NEG_P _LDIVS \r
+SECTION: ".common"\r
+ xSuspendedTestQueue \r
+SECTION: "TickTimer_CODE"\r
+ SetCV SetPV HWEnDi TickTimer_Enable TickTimer_SetFreqHz TickTimer_Init \r
+SECTION: "ButtonInterrupt_CODE"\r
+ ButtonInterrupt_Enable \r
+SECTION: "Byte1_CODE"\r
+ Byte1_GetMsk Byte1_NegBit \r
+SECTION: "Byte1_DATA"\r
+ Byte1_Table \r
+SECTION: "TickTimer_DATA"\r
+ EnUser CmpHighVal \r
+SECTION: ".abs_section_3f"\r
+ _ARMCOP \r
+SECTION: ".abs_section_8d"\r
+ _ATDDIEN \r
+SECTION: ".abs_section_86"\r
+ _ATDSTAT0 \r
+SECTION: ".abs_section_8b"\r
+ _ATDSTAT1 \r
+SECTION: ".abs_section_ff06"\r
+ _BDMCCR \r
+SECTION: ".abs_section_ff07"\r
+ _BDMINR \r
+SECTION: ".abs_section_ff01"\r
+ _BDMSTS \r
+SECTION: ".abs_section_2b"\r
+ _BKP0H \r
+SECTION: ".abs_section_2c"\r
+ _BKP0L \r
+SECTION: ".abs_section_2a"\r
+ _BKP0X \r
+SECTION: ".abs_section_2e"\r
+ _BKP1H \r
+SECTION: ".abs_section_2f"\r
+ _BKP1L \r
+SECTION: ".abs_section_2d"\r
+ _BKP1X \r
+SECTION: ".abs_section_28"\r
+ _BKPCT0 \r
+SECTION: ".abs_section_29"\r
+ _BKPCT1 \r
+SECTION: ".abs_section_142"\r
+ _CANBTR0 \r
+SECTION: ".abs_section_143"\r
+ _CANBTR1 \r
+SECTION: ".abs_section_140"\r
+ _CANCTL0 \r
+SECTION: ".abs_section_141"\r
+ _CANCTL1 \r
+SECTION: ".abs_section_14b"\r
+ _CANIDAC \r
+SECTION: ".abs_section_150"\r
+ _CANIDAR0 \r
+SECTION: ".abs_section_151"\r
+ _CANIDAR1 \r
+SECTION: ".abs_section_152"\r
+ _CANIDAR2 \r
+SECTION: ".abs_section_153"\r
+ _CANIDAR3 \r
+SECTION: ".abs_section_158"\r
+ _CANIDAR4 \r
+SECTION: ".abs_section_159"\r
+ _CANIDAR5 \r
+SECTION: ".abs_section_15a"\r
+ _CANIDAR6 \r
+SECTION: ".abs_section_15b"\r
+ _CANIDAR7 \r
+SECTION: ".abs_section_154"\r
+ _CANIDMR0 \r
+SECTION: ".abs_section_155"\r
+ _CANIDMR1 \r
+SECTION: ".abs_section_156"\r
+ _CANIDMR2 \r
+SECTION: ".abs_section_157"\r
+ _CANIDMR3 \r
+SECTION: ".abs_section_15c"\r
+ _CANIDMR4 \r
+SECTION: ".abs_section_15d"\r
+ _CANIDMR5 \r
+SECTION: ".abs_section_15e"\r
+ _CANIDMR6 \r
+SECTION: ".abs_section_15f"\r
+ _CANIDMR7 \r
+SECTION: ".abs_section_144"\r
+ _CANRFLG \r
+SECTION: ".abs_section_145"\r
+ _CANRIER \r
+SECTION: ".abs_section_16c"\r
+ _CANRXDLR \r
+SECTION: ".abs_section_164"\r
+ _CANRXDSR0 \r
+SECTION: ".abs_section_165"\r
+ _CANRXDSR1 \r
+SECTION: ".abs_section_166"\r
+ _CANRXDSR2 \r
+SECTION: ".abs_section_167"\r
+ _CANRXDSR3 \r
+SECTION: ".abs_section_168"\r
+ _CANRXDSR4 \r
+SECTION: ".abs_section_169"\r
+ _CANRXDSR5 \r
+SECTION: ".abs_section_16a"\r
+ _CANRXDSR6 \r
+SECTION: ".abs_section_16b"\r
+ _CANRXDSR7 \r
+SECTION: ".abs_section_14e"\r
+ _CANRXERR \r
+SECTION: ".abs_section_160"\r
+ _CANRXIDR0 \r
+SECTION: ".abs_section_161"\r
+ _CANRXIDR1 \r
+SECTION: ".abs_section_162"\r
+ _CANRXIDR2 \r
+SECTION: ".abs_section_163"\r
+ _CANRXIDR3 \r
+SECTION: ".abs_section_149"\r
+ _CANTAAK \r
+SECTION: ".abs_section_148"\r
+ _CANTARQ \r
+SECTION: ".abs_section_14a"\r
+ _CANTBSEL \r
+SECTION: ".abs_section_146"\r
+ _CANTFLG \r
+SECTION: ".abs_section_147"\r
+ _CANTIER \r
+SECTION: ".abs_section_17c"\r
+ _CANTXDLR \r
+SECTION: ".abs_section_174"\r
+ _CANTXDSR0 \r
+SECTION: ".abs_section_175"\r
+ _CANTXDSR1 \r
+SECTION: ".abs_section_176"\r
+ _CANTXDSR2 \r
+SECTION: ".abs_section_177"\r
+ _CANTXDSR3 \r
+SECTION: ".abs_section_178"\r
+ _CANTXDSR4 \r
+SECTION: ".abs_section_179"\r
+ _CANTXDSR5 \r
+SECTION: ".abs_section_17a"\r
+ _CANTXDSR6 \r
+SECTION: ".abs_section_17b"\r
+ _CANTXDSR7 \r
+SECTION: ".abs_section_14f"\r
+ _CANTXERR \r
+SECTION: ".abs_section_170"\r
+ _CANTXIDR0 \r
+SECTION: ".abs_section_171"\r
+ _CANTXIDR1 \r
+SECTION: ".abs_section_172"\r
+ _CANTXIDR2 \r
+SECTION: ".abs_section_173"\r
+ _CANTXIDR3 \r
+SECTION: ".abs_section_17f"\r
+ _CANTXTBPR \r
+SECTION: ".abs_section_41"\r
+ _CFORC \r
+SECTION: ".abs_section_39"\r
+ _CLKSEL \r
+SECTION: ".abs_section_3c"\r
+ _COPCTL \r
+SECTION: ".abs_section_37"\r
+ _CRGFLG \r
+SECTION: ".abs_section_38"\r
+ _CRGINT \r
+SECTION: ".abs_section_3e"\r
+ _CTCTL \r
+SECTION: ".abs_section_36"\r
+ _CTFLG \r
+SECTION: ".abs_section_272"\r
+ _DDRAD \r
+SECTION: ".abs_section_9"\r
+ _DDRE \r
+SECTION: ".abs_section_26a"\r
+ _DDRJ \r
+SECTION: ".abs_section_33"\r
+ _DDRK \r
+SECTION: ".abs_section_252"\r
+ _DDRM \r
+SECTION: ".abs_section_25a"\r
+ _DDRP \r
+SECTION: ".abs_section_24a"\r
+ _DDRS \r
+SECTION: ".abs_section_242"\r
+ _DDRT \r
+SECTION: ".abs_section_e"\r
+ _EBICTL \r
+SECTION: ".abs_section_100"\r
+ _FCLKDIV \r
+SECTION: ".abs_section_106"\r
+ _FCMD \r
+SECTION: ".abs_section_103"\r
+ _FCNFG \r
+SECTION: ".abs_section_104"\r
+ _FPROT \r
+SECTION: ".abs_section_101"\r
+ _FSEC \r
+SECTION: ".abs_section_105"\r
+ _FSTAT \r
+SECTION: ".abs_section_1f"\r
+ _HPRIO \r
+SECTION: ".abs_section_12"\r
+ _INITEE \r
+SECTION: ".abs_section_11"\r
+ _INITRG \r
+SECTION: ".abs_section_10"\r
+ _INITRM \r
+SECTION: ".abs_section_1e"\r
+ _INTCR \r
+SECTION: ".abs_section_15"\r
+ _ITCR \r
+SECTION: ".abs_section_16"\r
+ _ITEST \r
+SECTION: ".abs_section_1c"\r
+ _MEMSIZ0 \r
+SECTION: ".abs_section_1d"\r
+ _MEMSIZ1 \r
+SECTION: ".abs_section_13"\r
+ _MISC \r
+SECTION: ".abs_section_b"\r
+ _MODE \r
+SECTION: ".abs_section_247"\r
+ _MODRR \r
+SECTION: ".abs_section_14"\r
+ _MTST0 \r
+SECTION: ".abs_section_17"\r
+ _MTST1 \r
+SECTION: ".abs_section_43"\r
+ _OC7D \r
+SECTION: ".abs_section_42"\r
+ _OC7M \r
+SECTION: ".abs_section_60"\r
+ _PACTL \r
+SECTION: ".abs_section_61"\r
+ _PAFLG \r
+SECTION: ".abs_section_1a"\r
+ _PARTIDH \r
+SECTION: ".abs_section_1b"\r
+ _PARTIDL \r
+SECTION: ".abs_section_a"\r
+ _PEAR \r
+SECTION: ".abs_section_274"\r
+ _PERAD \r
+SECTION: ".abs_section_26c"\r
+ _PERJ \r
+SECTION: ".abs_section_254"\r
+ _PERM \r
+SECTION: ".abs_section_25c"\r
+ _PERP \r
+SECTION: ".abs_section_24c"\r
+ _PERS \r
+SECTION: ".abs_section_244"\r
+ _PERT \r
+SECTION: ".abs_section_26e"\r
+ _PIEJ \r
+SECTION: ".abs_section_25e"\r
+ _PIEP \r
+SECTION: ".abs_section_26f"\r
+ _PIFJ \r
+SECTION: ".abs_section_25f"\r
+ _PIFP \r
+SECTION: ".abs_section_3a"\r
+ _PLLCTL \r
+SECTION: ".abs_section_8f"\r
+ _PORTAD0 \r
+SECTION: ".abs_section_8"\r
+ _PORTE \r
+SECTION: ".abs_section_32"\r
+ _PORTK \r
+SECTION: ".abs_section_30"\r
+ _PPAGE \r
+SECTION: ".abs_section_275"\r
+ _PPSAD \r
+SECTION: ".abs_section_26d"\r
+ _PPSJ \r
+SECTION: ".abs_section_255"\r
+ _PPSM \r
+SECTION: ".abs_section_25d"\r
+ _PPSP \r
+SECTION: ".abs_section_24d"\r
+ _PPSS \r
+SECTION: ".abs_section_245"\r
+ _PPST \r
+SECTION: ".abs_section_270"\r
+ _PTAD \r
+SECTION: ".abs_section_271"\r
+ _PTIAD \r
+SECTION: ".abs_section_269"\r
+ _PTIJ \r
+SECTION: ".abs_section_251"\r
+ _PTIM \r
+SECTION: ".abs_section_259"\r
+ _PTIP \r
+SECTION: ".abs_section_249"\r
+ _PTIS \r
+SECTION: ".abs_section_241"\r
+ _PTIT \r
+SECTION: ".abs_section_268"\r
+ _PTJ \r
+SECTION: ".abs_section_250"\r
+ _PTM \r
+SECTION: ".abs_section_258"\r
+ _PTP \r
+SECTION: ".abs_section_248"\r
+ _PTS \r
+SECTION: ".abs_section_240"\r
+ _PTT \r
+SECTION: ".abs_section_c"\r
+ _PUCR \r
+SECTION: ".abs_section_e4"\r
+ _PWMCAE \r
+SECTION: ".abs_section_e2"\r
+ _PWMCLK \r
+SECTION: ".abs_section_e5"\r
+ _PWMCTL \r
+SECTION: ".abs_section_e0"\r
+ _PWME \r
+SECTION: ".abs_section_e1"\r
+ _PWMPOL \r
+SECTION: ".abs_section_e3"\r
+ _PWMPRCLK \r
+SECTION: ".abs_section_e8"\r
+ _PWMSCLA \r
+SECTION: ".abs_section_e9"\r
+ _PWMSCLB \r
+SECTION: ".abs_section_fe"\r
+ _PWMSDN \r
+SECTION: ".abs_section_273"\r
+ _RDRAD \r
+SECTION: ".abs_section_d"\r
+ _RDRIV \r
+SECTION: ".abs_section_26b"\r
+ _RDRJ \r
+SECTION: ".abs_section_253"\r
+ _RDRM \r
+SECTION: ".abs_section_25b"\r
+ _RDRP \r
+SECTION: ".abs_section_24b"\r
+ _RDRS \r
+SECTION: ".abs_section_243"\r
+ _RDRT \r
+SECTION: ".abs_section_35"\r
+ _REFDV \r
+SECTION: ".abs_section_3b"\r
+ _RTICTL \r
+SECTION: ".abs_section_ca"\r
+ _SCICR1 \r
+SECTION: ".abs_section_cb"\r
+ _SCICR2 \r
+SECTION: ".abs_section_ce"\r
+ _SCIDRH \r
+SECTION: ".abs_section_cf"\r
+ _SCIDRL \r
+SECTION: ".abs_section_cc"\r
+ _SCISR1 \r
+SECTION: ".abs_section_cd"\r
+ _SCISR2 \r
+SECTION: ".abs_section_da"\r
+ _SPIBR \r
+SECTION: ".abs_section_d8"\r
+ _SPICR1 \r
+SECTION: ".abs_section_d9"\r
+ _SPICR2 \r
+SECTION: ".abs_section_dd"\r
+ _SPIDR \r
+SECTION: ".abs_section_db"\r
+ _SPISR \r
+SECTION: ".abs_section_34"\r
+ _SYNR \r
+SECTION: ".abs_section_48"\r
+ _TCTL1 \r
+SECTION: ".abs_section_49"\r
+ _TCTL2 \r
+SECTION: ".abs_section_4a"\r
+ _TCTL3 \r
+SECTION: ".abs_section_4b"\r
+ _TCTL4 \r
+SECTION: ".abs_section_4e"\r
+ _TFLG1 \r
+SECTION: ".abs_section_4f"\r
+ _TFLG2 \r
+SECTION: ".abs_section_4c"\r
+ _TIE \r
+SECTION: ".abs_section_40"\r
+ _TIOS \r
+SECTION: ".abs_section_46"\r
+ _TSCR1 \r
+SECTION: ".abs_section_4d"\r
+ _TSCR2 \r
+SECTION: ".abs_section_47"\r
+ _TTOV \r
+SECTION: ".abs_section_256"\r
+ _WOMM \r
+SECTION: ".abs_section_24e"\r
+ _WOMS \r
+SECTION: ".abs_section_82"\r
+ _ATDCTL23 \r
+SECTION: ".abs_section_84"\r
+ _ATDCTL45 \r
+SECTION: ".abs_section_90"\r
+ _ATDDR0 \r
+SECTION: ".abs_section_92"\r
+ _ATDDR1 \r
+SECTION: ".abs_section_94"\r
+ _ATDDR2 \r
+SECTION: ".abs_section_96"\r
+ _ATDDR3 \r
+SECTION: ".abs_section_98"\r
+ _ATDDR4 \r
+SECTION: ".abs_section_9a"\r
+ _ATDDR5 \r
+SECTION: ".abs_section_9c"\r
+ _ATDDR6 \r
+SECTION: ".abs_section_9e"\r
+ _ATDDR7 \r
+SECTION: ".abs_section_2"\r
+ _DDRAB \r
+SECTION: ".abs_section_62"\r
+ _PACNT \r
+SECTION: ".abs_section_0"\r
+ _PORTAB \r
+SECTION: ".abs_section_ec"\r
+ _PWMCNT01 \r
+SECTION: ".abs_section_ee"\r
+ _PWMCNT23 \r
+SECTION: ".abs_section_f0"\r
+ _PWMCNT45 \r
+SECTION: ".abs_section_f8"\r
+ _PWMDTY01 \r
+SECTION: ".abs_section_fa"\r
+ _PWMDTY23 \r
+SECTION: ".abs_section_fc"\r
+ _PWMDTY45 \r
+SECTION: ".abs_section_f2"\r
+ _PWMPER01 \r
+SECTION: ".abs_section_f4"\r
+ _PWMPER23 \r
+SECTION: ".abs_section_f6"\r
+ _PWMPER45 \r
+SECTION: ".abs_section_c8"\r
+ _SCIBD \r
+SECTION: ".abs_section_50"\r
+ _TC0 \r
+SECTION: ".abs_section_52"\r
+ _TC1 \r
+SECTION: ".abs_section_54"\r
+ _TC2 \r
+SECTION: ".abs_section_56"\r
+ _TC3 \r
+SECTION: ".abs_section_58"\r
+ _TC4 \r
+SECTION: ".abs_section_5a"\r
+ _TC5 \r
+SECTION: ".abs_section_5c"\r
+ _TC6 \r
+SECTION: ".abs_section_5e"\r
+ _TC7 \r
+SECTION: ".abs_section_44"\r
+ _TCNT \r
+SECTION: ".abs_section_ff80"\r
+ _vect \r
+\r
+*********************************************************************************************\r
+OBJECT LIST SORTED BY ADDRESS\r
+ Name Addr hSize dSize Ref Section RLIB\r
+---------------------------------------------------------------------------------------------\r
+ _PORTAB 0 2 2 3 .abs_section_0\r
+ _DDRAB 2 2 2 1 .abs_section_2\r
+ _PORTE 8 1 1 0 .abs_section_8\r
+ _DDRE 9 1 1 0 .abs_section_9\r
+ _PEAR A 1 1 0 .abs_section_a\r
+ _MODE B 1 1 0 .abs_section_b\r
+ _PUCR C 1 1 0 .abs_section_c\r
+ _RDRIV D 1 1 0 .abs_section_d\r
+ _EBICTL E 1 1 0 .abs_section_e\r
+ _INITRM 10 1 1 1 .abs_section_10\r
+ _INITRG 11 1 1 0 .abs_section_11\r
+ _INITEE 12 1 1 0 .abs_section_12\r
+ _MISC 13 1 1 1 .abs_section_13\r
+ _MTST0 14 1 1 0 .abs_section_14\r
+ _ITCR 15 1 1 0 .abs_section_15\r
+ _ITEST 16 1 1 0 .abs_section_16\r
+ _MTST1 17 1 1 0 .abs_section_17\r
+ _PARTIDH 1A 1 1 0 .abs_section_1a\r
+ _PARTIDL 1B 1 1 0 .abs_section_1b\r
+ _MEMSIZ0 1C 1 1 0 .abs_section_1c\r
+ _MEMSIZ1 1D 1 1 0 .abs_section_1d\r
+ _INTCR 1E 1 1 1 .abs_section_1e\r
+ _HPRIO 1F 1 1 0 .abs_section_1f\r
+ _BKPCT0 28 1 1 0 .abs_section_28\r
+ _BKPCT1 29 1 1 0 .abs_section_29\r
+ _BKP0X 2A 1 1 0 .abs_section_2a\r
+ _BKP0H 2B 1 1 0 .abs_section_2b\r
+ _BKP0L 2C 1 1 0 .abs_section_2c\r
+ _BKP1X 2D 1 1 0 .abs_section_2d\r
+ _BKP1H 2E 1 1 0 .abs_section_2e\r
+ _BKP1L 2F 1 1 0 .abs_section_2f\r
+ _PPAGE 30 1 1 0 .abs_section_30\r
+ _PORTK 32 1 1 0 .abs_section_32\r
+ _DDRK 33 1 1 0 .abs_section_33\r
+ _SYNR 34 1 1 1 .abs_section_34\r
+ _REFDV 35 1 1 1 .abs_section_35\r
+ _CTFLG 36 1 1 0 .abs_section_36\r
+ _CRGFLG 37 1 1 1 .abs_section_37\r
+ _CRGINT 38 1 1 0 .abs_section_38\r
+ _CLKSEL 39 1 1 3 .abs_section_39\r
+ _PLLCTL 3A 1 1 3 .abs_section_3a\r
+ _RTICTL 3B 1 1 0 .abs_section_3b\r
+ _COPCTL 3C 1 1 0 .abs_section_3c\r
+ _CTCTL 3E 1 1 0 .abs_section_3e\r
+ _ARMCOP 3F 1 1 0 .abs_section_3f\r
+ _TIOS 40 1 1 1 .abs_section_40\r
+ _CFORC 41 1 1 0 .abs_section_41\r
+ _OC7M 42 1 1 0 .abs_section_42\r
+ _OC7D 43 1 1 0 .abs_section_43\r
+ _TCNT 44 2 2 0 .abs_section_44\r
+ _TSCR1 46 1 1 3 .abs_section_46\r
+ _TTOV 47 1 1 1 .abs_section_47\r
+ _TCTL1 48 1 1 1 .abs_section_48\r
+ _TCTL2 49 1 1 1 .abs_section_49\r
+ _TCTL3 4A 1 1 0 .abs_section_4a\r
+ _TCTL4 4B 1 1 0 .abs_section_4b\r
+ _TIE 4C 1 1 3 .abs_section_4c\r
+ _TSCR2 4D 1 1 5 .abs_section_4d\r
+ _TFLG1 4E 1 1 2 .abs_section_4e\r
+ _TFLG2 4F 1 1 0 .abs_section_4f\r
+ _TC0 50 2 2 1 .abs_section_50\r
+ _TC1 52 2 2 0 .abs_section_52\r
+ _TC2 54 2 2 0 .abs_section_54\r
+ _TC3 56 2 2 0 .abs_section_56\r
+ _TC4 58 2 2 0 .abs_section_58\r
+ _TC5 5A 2 2 0 .abs_section_5a\r
+ _TC6 5C 2 2 0 .abs_section_5c\r
+ _TC7 5E 2 2 1 .abs_section_5e\r
+ _PACTL 60 1 1 0 .abs_section_60\r
+ _PAFLG 61 1 1 0 .abs_section_61\r
+ _PACNT 62 2 2 0 .abs_section_62\r
+ _ATDCTL23 82 2 2 0 .abs_section_82\r
+ _ATDCTL45 84 2 2 0 .abs_section_84\r
+ _ATDSTAT0 86 1 1 0 .abs_section_86\r
+ _ATDSTAT1 8B 1 1 0 .abs_section_8b\r
+ _ATDDIEN 8D 1 1 0 .abs_section_8d\r
+ _PORTAD0 8F 1 1 0 .abs_section_8f\r
+ _ATDDR0 90 2 2 0 .abs_section_90\r
+ _ATDDR1 92 2 2 0 .abs_section_92\r
+ _ATDDR2 94 2 2 0 .abs_section_94\r
+ _ATDDR3 96 2 2 0 .abs_section_96\r
+ _ATDDR4 98 2 2 0 .abs_section_98\r
+ _ATDDR5 9A 2 2 0 .abs_section_9a\r
+ _ATDDR6 9C 2 2 0 .abs_section_9c\r
+ _ATDDR7 9E 2 2 0 .abs_section_9e\r
+ _SCIBD C8 2 2 0 .abs_section_c8\r
+ _SCICR1 CA 1 1 0 .abs_section_ca\r
+ _SCICR2 CB 1 1 0 .abs_section_cb\r
+ _SCISR1 CC 1 1 0 .abs_section_cc\r
+ _SCISR2 CD 1 1 0 .abs_section_cd\r
+ _SCIDRH CE 1 1 0 .abs_section_ce\r
+ _SCIDRL CF 1 1 0 .abs_section_cf\r
+ _SPICR1 D8 1 1 0 .abs_section_d8\r
+ _SPICR2 D9 1 1 0 .abs_section_d9\r
+ _SPIBR DA 1 1 0 .abs_section_da\r
+ _SPISR DB 1 1 0 .abs_section_db\r
+ _SPIDR DD 1 1 0 .abs_section_dd\r
+ _PWME E0 1 1 0 .abs_section_e0\r
+ _PWMPOL E1 1 1 0 .abs_section_e1\r
+ _PWMCLK E2 1 1 0 .abs_section_e2\r
+ _PWMPRCLK E3 1 1 0 .abs_section_e3\r
+ _PWMCAE E4 1 1 0 .abs_section_e4\r
+ _PWMCTL E5 1 1 1 .abs_section_e5\r
+ _PWMSCLA E8 1 1 0 .abs_section_e8\r
+ _PWMSCLB E9 1 1 0 .abs_section_e9\r
+ _PWMCNT01 EC 2 2 0 .abs_section_ec\r
+ _PWMCNT23 EE 2 2 0 .abs_section_ee\r
+ _PWMCNT45 F0 2 2 0 .abs_section_f0\r
+ _PWMPER01 F2 2 2 0 .abs_section_f2\r
+ _PWMPER23 F4 2 2 0 .abs_section_f4\r
+ _PWMPER45 F6 2 2 0 .abs_section_f6\r
+ _PWMDTY01 F8 2 2 0 .abs_section_f8\r
+ _PWMDTY23 FA 2 2 0 .abs_section_fa\r
+ _PWMDTY45 FC 2 2 0 .abs_section_fc\r
+ _PWMSDN FE 1 1 1 .abs_section_fe\r
+ _FCLKDIV 100 1 1 0 .abs_section_100\r
+ _FSEC 101 1 1 0 .abs_section_101\r
+ _FCNFG 103 1 1 0 .abs_section_103\r
+ _FPROT 104 1 1 0 .abs_section_104\r
+ _FSTAT 105 1 1 0 .abs_section_105\r
+ _FCMD 106 1 1 0 .abs_section_106\r
+ _CANCTL0 140 1 1 0 .abs_section_140\r
+ _CANCTL1 141 1 1 0 .abs_section_141\r
+ _CANBTR0 142 1 1 0 .abs_section_142\r
+ _CANBTR1 143 1 1 0 .abs_section_143\r
+ _CANRFLG 144 1 1 0 .abs_section_144\r
+ _CANRIER 145 1 1 0 .abs_section_145\r
+ _CANTFLG 146 1 1 0 .abs_section_146\r
+ _CANTIER 147 1 1 0 .abs_section_147\r
+ _CANTARQ 148 1 1 0 .abs_section_148\r
+ _CANTAAK 149 1 1 0 .abs_section_149\r
+ _CANTBSEL 14A 1 1 0 .abs_section_14a\r
+ _CANIDAC 14B 1 1 0 .abs_section_14b\r
+ _CANRXERR 14E 1 1 0 .abs_section_14e\r
+ _CANTXERR 14F 1 1 0 .abs_section_14f\r
+ _CANIDAR0 150 1 1 0 .abs_section_150\r
+ _CANIDAR1 151 1 1 0 .abs_section_151\r
+ _CANIDAR2 152 1 1 0 .abs_section_152\r
+ _CANIDAR3 153 1 1 0 .abs_section_153\r
+ _CANIDMR0 154 1 1 0 .abs_section_154\r
+ _CANIDMR1 155 1 1 0 .abs_section_155\r
+ _CANIDMR2 156 1 1 0 .abs_section_156\r
+ _CANIDMR3 157 1 1 0 .abs_section_157\r
+ _CANIDAR4 158 1 1 0 .abs_section_158\r
+ _CANIDAR5 159 1 1 0 .abs_section_159\r
+ _CANIDAR6 15A 1 1 0 .abs_section_15a\r
+ _CANIDAR7 15B 1 1 0 .abs_section_15b\r
+ _CANIDMR4 15C 1 1 0 .abs_section_15c\r
+ _CANIDMR5 15D 1 1 0 .abs_section_15d\r
+ _CANIDMR6 15E 1 1 0 .abs_section_15e\r
+ _CANIDMR7 15F 1 1 0 .abs_section_15f\r
+ _CANRXIDR0 160 1 1 0 .abs_section_160\r
+ _CANRXIDR1 161 1 1 0 .abs_section_161\r
+ _CANRXIDR2 162 1 1 0 .abs_section_162\r
+ _CANRXIDR3 163 1 1 0 .abs_section_163\r
+ _CANRXDSR0 164 1 1 0 .abs_section_164\r
+ _CANRXDSR1 165 1 1 0 .abs_section_165\r
+ _CANRXDSR2 166 1 1 0 .abs_section_166\r
+ _CANRXDSR3 167 1 1 0 .abs_section_167\r
+ _CANRXDSR4 168 1 1 0 .abs_section_168\r
+ _CANRXDSR5 169 1 1 0 .abs_section_169\r
+ _CANRXDSR6 16A 1 1 0 .abs_section_16a\r
+ _CANRXDSR7 16B 1 1 0 .abs_section_16b\r
+ _CANRXDLR 16C 1 1 0 .abs_section_16c\r
+ _CANTXIDR0 170 1 1 0 .abs_section_170\r
+ _CANTXIDR1 171 1 1 0 .abs_section_171\r
+ _CANTXIDR2 172 1 1 0 .abs_section_172\r
+ _CANTXIDR3 173 1 1 0 .abs_section_173\r
+ _CANTXDSR0 174 1 1 0 .abs_section_174\r
+ _CANTXDSR1 175 1 1 0 .abs_section_175\r
+ _CANTXDSR2 176 1 1 0 .abs_section_176\r
+ _CANTXDSR3 177 1 1 0 .abs_section_177\r
+ _CANTXDSR4 178 1 1 0 .abs_section_178\r
+ _CANTXDSR5 179 1 1 0 .abs_section_179\r
+ _CANTXDSR6 17A 1 1 0 .abs_section_17a\r
+ _CANTXDSR7 17B 1 1 0 .abs_section_17b\r
+ _CANTXDLR 17C 1 1 0 .abs_section_17c\r
+ _CANTXTBPR 17F 1 1 0 .abs_section_17f\r
+ _PTT 240 1 1 0 .abs_section_240\r
+ _PTIT 241 1 1 0 .abs_section_241\r
+ _DDRT 242 1 1 0 .abs_section_242\r
+ _RDRT 243 1 1 0 .abs_section_243\r
+ _PERT 244 1 1 0 .abs_section_244\r
+ _PPST 245 1 1 0 .abs_section_245\r
+ _MODRR 247 1 1 0 .abs_section_247\r
+ _PTS 248 1 1 0 .abs_section_248\r
+ _PTIS 249 1 1 0 .abs_section_249\r
+ _DDRS 24A 1 1 0 .abs_section_24a\r
+ _RDRS 24B 1 1 0 .abs_section_24b\r
+ _PERS 24C 1 1 0 .abs_section_24c\r
+ _PPSS 24D 1 1 0 .abs_section_24d\r
+ _WOMS 24E 1 1 0 .abs_section_24e\r
+ _PTM 250 1 1 0 .abs_section_250\r
+ _PTIM 251 1 1 0 .abs_section_251\r
+ _DDRM 252 1 1 0 .abs_section_252\r
+ _RDRM 253 1 1 0 .abs_section_253\r
+ _PERM 254 1 1 0 .abs_section_254\r
+ _PPSM 255 1 1 0 .abs_section_255\r
+ _WOMM 256 1 1 0 .abs_section_256\r
+ _PTP 258 1 1 0 .abs_section_258\r
+ _PTIP 259 1 1 0 .abs_section_259\r
+ _DDRP 25A 1 1 1 .abs_section_25a\r
+ _RDRP 25B 1 1 0 .abs_section_25b\r
+ _PERP 25C 1 1 1 .abs_section_25c\r
+ _PPSP 25D 1 1 1 .abs_section_25d\r
+ _PIEP 25E 1 1 2 .abs_section_25e\r
+ _PIFP 25F 1 1 2 .abs_section_25f\r
+ _PTJ 268 1 1 0 .abs_section_268\r
+ _PTIJ 269 1 1 0 .abs_section_269\r
+ _DDRJ 26A 1 1 0 .abs_section_26a\r
+ _RDRJ 26B 1 1 0 .abs_section_26b\r
+ _PERJ 26C 1 1 0 .abs_section_26c\r
+ _PPSJ 26D 1 1 0 .abs_section_26d\r
+ _PIEJ 26E 1 1 0 .abs_section_26e\r
+ _PIFJ 26F 1 1 0 .abs_section_26f\r
+ _PTAD 270 1 1 0 .abs_section_270\r
+ _PTIAD 271 1 1 0 .abs_section_271\r
+ _DDRAD 272 1 1 0 .abs_section_272\r
+ _RDRAD 273 1 1 0 .abs_section_273\r
+ _PERAD 274 1 1 0 .abs_section_274\r
+ _PPSAD 275 1 1 0 .abs_section_275\r
+ uxCriticalNesting 800 1 1 91 .data \r
+ pxCurrentTCB 801 2 2 29 .bss \r
+ uxCurrentNumberOfTasks 803 1 1 3 .bss \r
+ xTickCount 804 2 2 14 .bss \r
+ uxTopUsedPriority 806 1 1 2 .bss \r
+ uxTopReadyPriority 807 1 1 15 .bss \r
+ xSchedulerRunning 808 1 1 3 .bss \r
+ uxSchedulerSuspended 809 1 1 6 .bss \r
+ uxMissedTicks 80A 1 1 4 .bss \r
+ uxTaskNumber.1 80B 1 1 2 .bss \r
+ pxReadyTasksLists 80C 3C 60 11 .bss \r
+ xDelayedTaskList1 848 F 15 2 .bss \r
+ xDelayedTaskList2 857 F 15 2 .bss \r
+ pxDelayedTaskList 866 2 2 8 .bss \r
+ pxOverflowDelayedTaskList 868 2 2 6 .bss \r
+ xPendingReadyList 86A F 15 4 .bss \r
+ xSuspendedTaskList 879 F 15 2 .bss \r
+ uxFlashTaskNumber 888 1 1 2 .bss \r
+ xLocalError 889 1 1 3 .bss \r
+ uxValToSend.3 88A 1 1 2 .bss \r
+ xButtonQueue 88B 2 2 3 .bss \r
+ xNextFreeByte 88D 2 2 4 .bss \r
+ xHeap 88F 704 1796 1 .bss \r
+ xPollingConsumerCount F93 1 1 3 .bss \r
+ xPollingProducerCount F94 1 1 3 .bss \r
+ xPolledQueue.1 F95 2 2 3 .bss \r
+ usCheckVariable F97 2 2 3 .bss \r
+ xSuspendedQueueSendError F99 1 1 2 .bss \r
+ xSuspendedQueueReceiveError F9A 1 1 3 .bss \r
+ ulValueToSend.6 F9B 4 4 5 .bss \r
+ ulExpectedValue.7 F9F 4 4 6 .bss \r
+ usLastTaskCheck.9 FA3 2 2 2 .bss \r
+ xContinousIncrementHandle FA5 2 2 5 .bss \r
+ xLimitedIncrementHandle FA7 2 2 2 .bss \r
+ ulCounter FA9 4 4 10 .bss \r
+ ulReceivedValue.8 FAD 4 4 3 .bss \r
+ xSuspendedTestQueue FB1 2 2 3 .common \r
+ Byte1_Table FB3 8 8 1 Byte1_DATA \r
+ EnUser FBB 1 1 4 TickTimer_DATA\r
+ CmpHighVal FBC 2 2 2 TickTimer_DATA\r
+ _EntryPoint C000 2E 46 1 .init \r
+ PE_low_level_init C02E 48 72 1 .init \r
+ STRING.IDLE.2 C093 5 5 1 .rodata1 \r
+ STRING.LEDx.1 C098 5 5 1 .rodata1 \r
+ STRING.Check.1 C09D 6 6 1 .rodata1 \r
+ STRING.Button.2 C0A3 7 7 1 .rodata1 \r
+ STRING.QConsNB.2 C0AA 8 8 1 .rodata1 \r
+ STRING.QProdNB.3 C0B2 8 8 1 .rodata1 \r
+ STRING.CNT_INC.1 C0BA 8 8 1 .rodata1 \r
+ STRING.LIM_INC.2 C0C2 8 8 1 .rodata1 \r
+ STRING.C_CTRL.3 C0CA 7 7 1 .rodata1 \r
+ STRING.SUSP_TX.4 C0D1 8 8 1 .rodata1 \r
+ STRING.SUSP_RX.5 C0D9 8 8 1 .rodata1 \r
+ xBankedStartScheduler C0E1 F 15 1 NON_BANKED \r
+ vPortYield C0F0 16 22 1 NON_BANKED \r
+ vPortTickInterrupt C106 1D 29 1 NON_BANKED \r
+ vButtonPush C123 2F 47 1 NON_BANKED \r
+ Cpu_Interrupt C152 1 1 60 NON_BANKED \r
+ Init C153 29 41 1 .text \r
+ _Startup C17C 10 16 1 .text \r
+ _memcpy_8bitCount C18C 1C 28 3 .text \r
+ memset C1A8 1E 30 1 .text \r
+ strncpy C1C6 2D 45 1 .text \r
+ xTaskCreate C1F3 CE 206 11 .text \r
+ vTaskDelayUntil C2C1 74 116 3 .text \r
+ vTaskDelay C335 46 70 4 .text \r
+ uxTaskPriorityGet C37B 26 38 1 .text \r
+ vTaskPrioritySet C3A1 69 105 2 .text \r
+ vTaskSuspend C40A 44 68 3 .text \r
+ vTaskResume C44E 59 89 3 .text \r
+ vTaskStartScheduler C4A7 30 48 1 .text \r
+ vTaskSuspendAll C4D7 13 19 11 .text \r
+ xTaskResumeAll C4EA 9F 159 13 .text \r
+ xTaskGetTickCount C589 17 23 2 .text \r
+ vTaskIncrementTick C5A0 81 129 2 .text \r
+ vTaskSwitchContext C621 5B 91 3 .text \r
+ vTaskPlaceOnEventList C67C 3E 62 2 .text \r
+ xTaskRemoveFromEventList C6BA 65 101 3 .text \r
+ prvIdleTask C71F 10 16 1 .text \r
+ prvInitialiseTCBVariables C72F 4A 74 1 .text \r
+ prvInitialiseTaskLists C779 37 55 1 .text \r
+ prvCheckTasksWaitingTermination C7B0 1 1 1 .text \r
+ prvAllocateTCBAndStack C7B1 39 57 1 .text \r
+ xQueueCreate C7EA 76 118 3 .text \r
+ xQueueSend C860 C9 201 3 .text \r
+ xQueueSendFromISR C929 58 88 1 .text \r
+ xQueueReceive C981 C3 195 4 .text \r
+ uxQueueMessagesWaiting CA44 1B 27 1 .text \r
+ prvUnlockQueue CA5F 6F 111 4 .text \r
+ prvIsQueueEmpty CACE 21 33 1 .text \r
+ prvIsQueueFull CAEF 24 36 1 .text \r
+ vListInitialise CB13 1F 31 7 .text \r
+ vListInitialiseItem CB32 7 7 3 .text \r
+ vListInsertEnd CB39 25 37 7 .text \r
+ vListInsert CB5E 54 84 4 .text \r
+ vListRemove CBB2 23 35 13 .text \r
+ pxPortInitialiseStack CBD5 2B 43 1 .text \r
+ prvSetupTimerInterrupt CC00 9 9 1 .text \r
+ xPortStartScheduler CC09 4 4 1 .text \r
+ vStartLEDFlashTasks CC0D 2E 46 1 .text \r
+ vLEDFlashTask CC3B 52 82 1 .text \r
+ vMain CC8D 42 66 1 .text \r
+ vErrorChecks CCCF 35 53 1 .text \r
+ prvCheckOtherTasksAreStillRunning CD04 26 38 1 .text \r
+ vApplicationIdleHook CD2A 73 115 1 .text \r
+ vButtonTask CD9D 4F 79 1 .text \r
+ pvPortMalloc CDEC 2D 45 4 .text \r
+ vPortFree CE19 1 1 2 .text \r
+ vParTestToggleLED CE1A 13 19 4 .text \r
+ PE_Timer_LngHi1 CE2D 4A 74 1 .text \r
+ main CE77 8 8 0 .text \r
+ vStartPolledQueueTasks CE7F 42 66 1 .text \r
+ vPolledQueueProducer CEC1 4D 77 1 .text \r
+ vPolledQueueConsumer CF0E 59 89 1 .text \r
+ xArePollingQueuesStillRunning CF67 15 21 1 .text \r
+ vStartDynamicPriorityTasks CF7C 7C 124 1 .text \r
+ vLimitedIncrementTask CFF8 26 38 1 .text \r
+ vContinuousIncrementTask D01E 35 53 1 .text \r
+ vCounterControlTask D053 98 152 3 .text \r
+ vQueueSendWhenSuspendedTask D0EB 34 52 1 .text \r
+ vQueueReceiveWhenSuspendedTask D11F 4F 79 1 .text \r
+ xAreDynamicPriorityTasksStillRunning D16E 2B 43 1 .text \r
+ _LCMP D199 19 25 2 RUNTIME \r
+ _LCMP_P D1B2 15 21 2 RUNTIME \r
+ _LNEG D1C7 D 13 1 RUNTIME \r
+ _LINC D1D4 5 5 4 RUNTIME \r
+ _lDivMod D1D9 E3 227 3 RUNTIME \r
+ _LDIVU D2BC E 14 1 RUNTIME \r
+ _NEG_P D2CA F 15 4 RUNTIME \r
+ _LDIVS D2D9 35 53 1 RUNTIME \r
+ SetCV D30E B 11 2 TickTimer_CODE\r
+ SetPV D319 9 9 1 TickTimer_CODE\r
+ HWEnDi D322 11 17 2 TickTimer_CODE\r
+ TickTimer_Enable D333 E 14 1 TickTimer_CODE\r
+ TickTimer_SetFreqHz D341 4E 78 1 TickTimer_CODE\r
+ TickTimer_Init D38F 14 20 1 TickTimer_CODE\r
+ ButtonInterrupt_Enable D3A3 A 10 1 ButtonInterrupt_CODE\r
+ Byte1_GetMsk D3AD D 13 1 Byte1_CODE \r
+ Byte1_NegBit D3BA A 10 1 Byte1_CODE \r
+ _BDMSTS FF01 1 1 0 .abs_section_ff01\r
+ _BDMCCR FF06 1 1 0 .abs_section_ff06\r
+ _BDMINR FF07 1 1 0 .abs_section_ff07\r
+ _vect FF80 80 128 0 .abs_section_ff80\r
+\r
+*********************************************************************************************\r
+UNUSED-OBJECTS SECTION\r
+---------------------------------------------------------------------------------------------\r
+NOT USED PROCEDURES\r
+STRING.C.o (ansisi.lib):\r
+ strerror memchr memcmp memcpy2 memcpy memmove _memset_clear_8bitCount strlen \r
+ strset strcat strncat strcpy strcmp strncmp strchr strrchr strspn strcspn \r
+ strpbrk strstr strtok strcoll strxfrm \r
+rtshc12.c.o (ansisi.lib):\r
+ _BSHL _BSHRS _BSHRU _BDIVMODU _BDIVMODS _ISHL _ISHRU _ISHRS _LSHL _LSHRU \r
+ _LSHRS _LADD _LSUB _LAND _LOR _LXOR _LCMP_PP _LABS _LCOM _LDEC _LMUL _LMODU \r
+ _LMODS _ILSEXT _LTEST _COPY _CASE_DIRECT _CASE_DIRECT_BYTE _CASE_CHECKED \r
+ _CASE_CHECKED_BYTE _CASE_SEARCH _CASE_SEARCH_BYTE _CASE_SEARCH_8 \r
+ _CASE_SEARCH_8_BYTE _FCALL _FPCMP \r
+tasks.c.o:\r
+ vTaskEndScheduler uxTaskGetNumberOfTasks \r
+queue.c.o:\r
+ xQueueReceiveFromISR vQueueDelete \r
+port.c.o:\r
+ vPortEndScheduler \r
+heap_1.c.o:\r
+ vPortInitialiseBlocks \r
+ParTest.c.o:\r
+ vParTestSetLED \r
+Byte1.C.o:\r
+ Byte1_PutBit \r
+TickTimer.C.o:\r
+ TickTimer_Interrupt \r
+ButtonInterrupt.C.o:\r
+ ButtonInterrupt_Interrupt \r
+NOT USED VARIABLES\r
+STRING.C.o (ansisi.lib):\r
+ STRING..1 next.2 \r
+rtshc12.c.o (ansisi.lib):\r
+ _PowOfTwo_8 _PowOfTwo_16 _PowOfTwo_32 \r
+Cpu.C.o:\r
+ CpuMode CCR_reg \r
+\r
+*********************************************************************************************\r
+COPYDOWN SECTION\r
+---------------------------------------------------------------------------------------------\r
+------- ROM-ADDRESS: 0xD3C4 ---- SIZE 4 ---\r
+Filling bytes inserted\r
+ 00010800\r
+------- ROM-ADDRESS: 0xD3C8 ---- RAM-ADDRESS: 0x800 ---- SIZE 1 ---\r
+Name of initialized Object : uxCriticalNesting\r
+ FF\r
+------- ROM-ADDRESS: 0xD3C9 ---- SIZE 4 ---\r
+Filling bytes inserted\r
+ 00080FB3\r
+------- ROM-ADDRESS: 0xD3CD ---- RAM-ADDRESS: 0xFB3 ---- SIZE 8 ---\r
+Name of initialized Object : Byte1_Table\r
+ 0102040810 204080\r
+------- ROM-ADDRESS: 0xD3D5 ---- SIZE 2 ---\r
+Filling bytes inserted\r
+ 0000\r
+\r
+*********************************************************************************************\r
+OBJECT-DEPENDENCIES SECTION\r
+---------------------------------------------------------------------------------------------\r
+_EntryPoint USES _INITRM _MISC _CLKSEL _PLLCTL _SYNR _REFDV \r
+ _CRGFLG _Startup \r
+PE_low_level_init USES _TSCR1 _TCTL2 _TCTL1 _TIE _TTOV _TSCR2 _TIOS \r
+ _PPSP _PERP _DDRP _PWMCTL _PWMSDN _PORTAB _DDRAB \r
+ TickTimer_Init _PIEP _INTCR \r
+xBankedStartScheduler USES prvSetupTimerInterrupt pxCurrentTCB \r
+ uxCriticalNesting \r
+vPortYield USES uxCriticalNesting pxCurrentTCB \r
+ vTaskSwitchContext \r
+vPortTickInterrupt USES uxCriticalNesting pxCurrentTCB \r
+ vTaskIncrementTick vTaskSwitchContext _TFLG1 \r
+vButtonPush USES uxValToSend.3 _PIFP xButtonQueue \r
+ xQueueSendFromISR uxCriticalNesting pxCurrentTCB \r
+ vTaskSwitchContext \r
+Init USES _startupData \r
+_Startup USES _startupData Init \r
+xTaskCreate USES prvAllocateTCBAndStack \r
+ prvInitialiseTCBVariables pxPortInitialiseStack uxCriticalNesting \r
+ uxCurrentNumberOfTasks pxCurrentTCB prvInitialiseTaskLists \r
+ xSchedulerRunning uxTopUsedPriority uxTaskNumber.1 \r
+ uxTopReadyPriority pxReadyTasksLists vListInsertEnd \r
+vTaskDelayUntil USES vTaskSuspendAll xTickCount pxCurrentTCB \r
+ vListRemove pxOverflowDelayedTaskList pxDelayedTaskList \r
+ vListInsert xTaskResumeAll \r
+vTaskDelay USES vTaskSuspendAll xTickCount pxCurrentTCB \r
+ vListRemove pxOverflowDelayedTaskList pxDelayedTaskList \r
+ vListInsert xTaskResumeAll \r
+uxTaskPriorityGet USES uxCriticalNesting pxCurrentTCB \r
+vTaskPrioritySet USES uxCriticalNesting pxCurrentTCB \r
+ pxReadyTasksLists vListRemove uxTopReadyPriority vListInsertEnd \r
+vTaskSuspend USES uxCriticalNesting pxCurrentTCB vListRemove \r
+ xSuspendedTaskList vListInsertEnd \r
+vTaskResume USES uxCriticalNesting pxCurrentTCB vListRemove \r
+ uxTopReadyPriority pxReadyTasksLists vListInsertEnd \r
+vTaskStartScheduler USES pxCurrentTCB prvIdleTask STRING.IDLE.2 \r
+ xTaskCreate xSchedulerRunning xTickCount \r
+ xPortStartScheduler \r
+vTaskSuspendAll USES uxCriticalNesting uxSchedulerSuspended \r
+xTaskResumeAll USES uxCriticalNesting uxSchedulerSuspended \r
+ uxCurrentNumberOfTasks vListRemove uxTopReadyPriority \r
+ pxReadyTasksLists vListInsertEnd pxCurrentTCB xPendingReadyList \r
+ uxMissedTicks vTaskIncrementTick \r
+xTaskGetTickCount USES uxCriticalNesting xTickCount \r
+vTaskIncrementTick USES uxSchedulerSuspended xTickCount \r
+ pxDelayedTaskList pxOverflowDelayedTaskList vListRemove \r
+ uxTopReadyPriority pxReadyTasksLists vListInsertEnd uxMissedTicks \r
+vTaskSwitchContext USES uxSchedulerSuspended uxTopReadyPriority \r
+ pxCurrentTCB pxReadyTasksLists \r
+vTaskPlaceOnEventList USES pxCurrentTCB vListInsert xTickCount vListRemove \r
+ pxOverflowDelayedTaskList pxDelayedTaskList \r
+xTaskRemoveFromEventList USES vListRemove uxSchedulerSuspended \r
+ uxTopReadyPriority pxReadyTasksLists xPendingReadyList \r
+ vListInsertEnd pxCurrentTCB \r
+prvIdleTask USES prvCheckTasksWaitingTermination \r
+ pxReadyTasksLists vApplicationIdleHook \r
+prvInitialiseTCBVariables USES strncpy vListInitialiseItem \r
+prvInitialiseTaskLists USES pxReadyTasksLists vListInitialise \r
+ xDelayedTaskList1 xDelayedTaskList2 xPendingReadyList \r
+ xSuspendedTaskList pxDelayedTaskList pxOverflowDelayedTaskList \r
+prvAllocateTCBAndStack USES pvPortMalloc vPortFree memset \r
+xQueueCreate USES pvPortMalloc vListInitialise vPortFree \r
+xQueueSend USES vTaskSuspendAll uxCriticalNesting xQueueSend \r
+ prvIsQueueFull vTaskPlaceOnEventList prvUnlockQueue \r
+ xTaskResumeAll _memcpy_8bitCount \r
+xQueueSendFromISR USES _memcpy_8bitCount xTaskRemoveFromEventList \r
+xQueueReceive USES vTaskSuspendAll uxCriticalNesting xQueueReceive \r
+ prvIsQueueEmpty vTaskPlaceOnEventList prvUnlockQueue \r
+ xTaskResumeAll _memcpy_8bitCount \r
+uxQueueMessagesWaiting USES uxCriticalNesting \r
+prvUnlockQueue USES uxCriticalNesting xTaskRemoveFromEventList \r
+prvIsQueueEmpty USES uxCriticalNesting \r
+prvIsQueueFull USES uxCriticalNesting \r
+vListInitialise USES vListInitialiseItem \r
+prvSetupTimerInterrupt USES TickTimer_SetFreqHz TickTimer_Enable \r
+xPortStartScheduler USES xBankedStartScheduler \r
+vStartLEDFlashTasks USES vLEDFlashTask STRING.LEDx.1 xTaskCreate \r
+vLEDFlashTask USES uxCriticalNesting uxFlashTaskNumber \r
+ xTaskGetTickCount vTaskDelayUntil vParTestToggleLED \r
+vMain USES vStartLEDFlashTasks vStartPolledQueueTasks \r
+ vStartDynamicPriorityTasks vErrorChecks STRING.Check.1 xTaskCreate \r
+ vButtonTask STRING.Button.2 vTaskStartScheduler \r
+vErrorChecks USES xTaskGetTickCount vTaskDelayUntil \r
+ prvCheckOtherTasksAreStillRunning _LCMP vParTestToggleLED \r
+prvCheckOtherTasksAreStillRunning USES xArePollingQueuesStillRunning \r
+ xAreDynamicPriorityTasksStillRunning xLocalError \r
+vApplicationIdleHook USES _LNEG _LDIVS _LCMP_P uxCriticalNesting \r
+ xLocalError \r
+vButtonTask USES xQueueCreate xButtonQueue \r
+ ButtonInterrupt_Enable xQueueReceive uxCriticalNesting xLocalError \r
+ vParTestToggleLED \r
+pvPortMalloc USES vTaskSuspendAll xNextFreeByte xHeap \r
+ xTaskResumeAll \r
+vParTestToggleLED USES uxCriticalNesting Byte1_NegBit \r
+PE_Timer_LngHi1 USES _LCMP \r
+main USES PE_low_level_init vMain \r
+vStartPolledQueueTasks USES xQueueCreate xPolledQueue.1 \r
+ vPolledQueueConsumer STRING.QConsNB.2 xTaskCreate \r
+ vPolledQueueProducer STRING.QProdNB.3 \r
+vPolledQueueProducer USES xQueueSend uxCriticalNesting \r
+ xPollingProducerCount vTaskDelay \r
+vPolledQueueConsumer USES xQueueReceive uxCriticalNesting \r
+ xPollingConsumerCount uxQueueMessagesWaiting vTaskDelay \r
+xArePollingQueuesStillRunning USES xPollingConsumerCount xPollingProducerCount \r
+vStartDynamicPriorityTasks USES xQueueCreate xSuspendedTestQueue \r
+ vContinuousIncrementTask STRING.CNT_INC.1 ulCounter \r
+ xContinousIncrementHandle xTaskCreate vLimitedIncrementTask \r
+ STRING.LIM_INC.2 xLimitedIncrementHandle vCounterControlTask \r
+ STRING.C_CTRL.3 vQueueSendWhenSuspendedTask STRING.SUSP_TX.4 \r
+ vQueueReceiveWhenSuspendedTask STRING.SUSP_RX.5 \r
+vLimitedIncrementTask USES _LINC _LCMP_P vTaskSuspend \r
+vContinuousIncrementTask USES uxTaskPriorityGet vTaskPrioritySet _LINC \r
+vCounterControlTask USES vCounterControlTask xContinousIncrementHandle \r
+ vTaskSuspend ulCounter vTaskResume vTaskDelay \r
+ vTaskSuspendAll xTaskResumeAll xLimitedIncrementHandle \r
+ uxCriticalNesting usCheckVariable \r
+vQueueSendWhenSuspendedTask USES vTaskSuspendAll xSuspendedTestQueue \r
+ ulValueToSend.6 xQueueSend xSuspendedQueueSendError \r
+ xTaskResumeAll vTaskDelay _LINC \r
+vQueueReceiveWhenSuspendedTask USES vTaskSuspendAll xSuspendedTestQueue \r
+ ulReceivedValue.8 xQueueReceive xTaskResumeAll \r
+ xSuspendedQueueReceiveError ulExpectedValue.7 _LINC \r
+xAreDynamicPriorityTasksStillRunning USES usCheckVariable usLastTaskCheck.9 \r
+ xSuspendedQueueSendError xSuspendedQueueReceiveError \r
+_LDIVU USES _lDivMod \r
+_LDIVS USES _NEG_P _lDivMod \r
+SetCV USES _TC0 _TC7 \r
+SetPV USES _TSCR2 \r
+HWEnDi USES EnUser _TFLG1 _TIE \r
+TickTimer_Enable USES EnUser HWEnDi \r
+TickTimer_SetFreqHz USES _LDIVU PE_Timer_LngHi1 CmpHighVal SetCV \r
+TickTimer_Init USES CmpHighVal EnUser SetCV SetPV HWEnDi \r
+ButtonInterrupt_Enable USES _PIFP _PIEP \r
+Byte1_GetMsk USES Byte1_Table \r
+Byte1_NegBit USES Byte1_GetMsk _PORTAB \r
+_vect USES Cpu_Interrupt vButtonPush vPortTickInterrupt \r
+ vPortYield _EntryPoint \r
+\r
+*********************************************************************************************\r
+DEPENDENCY TREE\r
+*********************************************************************************************\r
+ main and _Startup Group\r
+ | \r
+ +- main \r
+ | | \r
+ | +- PE_low_level_init \r
+ | | | \r
+ | | +- TickTimer_Init \r
+ | | | \r
+ | | +- SetCV \r
+ | | | \r
+ | | +- SetPV \r
+ | | | \r
+ | | +- HWEnDi \r
+ | | \r
+ | +- vMain \r
+ | | \r
+ | +- vStartLEDFlashTasks \r
+ | | | \r
+ | | +- vLEDFlashTask \r
+ | | | | \r
+ | | | +- xTaskGetTickCount \r
+ | | | | \r
+ | | | +- vTaskDelayUntil \r
+ | | | | | \r
+ | | | | +- vTaskSuspendAll \r
+ | | | | | \r
+ | | | | +- vListRemove \r
+ | | | | | \r
+ | | | | +- vListInsert \r
+ | | | | | \r
+ | | | | +- xTaskResumeAll \r
+ | | | | | \r
+ | | | | +- vListRemove (see above)\r
+ | | | | | \r
+ | | | | +- vListInsertEnd \r
+ | | | | | \r
+ | | | | +- vTaskIncrementTick \r
+ | | | | | \r
+ | | | | +- vListRemove (see above)\r
+ | | | | | \r
+ | | | | +- vListInsertEnd (see above)\r
+ | | | | \r
+ | | | +- vParTestToggleLED \r
+ | | | | \r
+ | | | +- Byte1_NegBit \r
+ | | | | \r
+ | | | +- Byte1_GetMsk \r
+ | | | \r
+ | | +- xTaskCreate \r
+ | | | \r
+ | | +- prvAllocateTCBAndStack\r
+ | | | | \r
+ | | | +- pvPortMalloc \r
+ | | | | | \r
+ | | | | +- vTaskSuspendAll (see above)\r
+ | | | | | \r
+ | | | | +- xTaskResumeAll (see above)\r
+ | | | | \r
+ | | | +- vPortFree \r
+ | | | | \r
+ | | | +- memset \r
+ | | | \r
+ | | +- prvInitialiseTCBVariables\r
+ | | | | \r
+ | | | +- strncpy \r
+ | | | | \r
+ | | | +- vListInitialiseItem \r
+ | | | \r
+ | | +- pxPortInitialiseStack\r
+ | | | \r
+ | | +- prvInitialiseTaskLists\r
+ | | | | \r
+ | | | +- vListInitialise \r
+ | | | | \r
+ | | | +- vListInitialiseItem (see above)\r
+ | | | \r
+ | | +- vListInsertEnd (see above)\r
+ | | \r
+ | +- vStartPolledQueueTasks\r
+ | | | \r
+ | | +- xQueueCreate \r
+ | | | | \r
+ | | | +- pvPortMalloc (see above)\r
+ | | | | \r
+ | | | +- vListInitialise (see above)\r
+ | | | | \r
+ | | | +- vPortFree (see above)\r
+ | | | \r
+ | | +- vPolledQueueConsumer\r
+ | | | | \r
+ | | | +- xQueueReceive \r
+ | | | | | \r
+ | | | | +- vTaskSuspendAll (see above)\r
+ | | | | | \r
+ | | | | +- prvIsQueueEmpty \r
+ | | | | | \r
+ | | | | +- vTaskPlaceOnEventList\r
+ | | | | | | \r
+ | | | | | +- vListInsert (see above)\r
+ | | | | | | \r
+ | | | | | +- vListRemove (see above)\r
+ | | | | | \r
+ | | | | +- prvUnlockQueue \r
+ | | | | | | \r
+ | | | | | +- xTaskRemoveFromEventList\r
+ | | | | | | \r
+ | | | | | +- vListRemove (see above)\r
+ | | | | | | \r
+ | | | | | +- vListInsertEnd (see above)\r
+ | | | | | \r
+ | | | | +- xTaskResumeAll (see above)\r
+ | | | | | \r
+ | | | | +- _memcpy_8bitCount \r
+ | | | | \r
+ | | | +- uxQueueMessagesWaiting\r
+ | | | | \r
+ | | | +- vTaskDelay \r
+ | | | | \r
+ | | | +- vTaskSuspendAll (see above)\r
+ | | | | \r
+ | | | +- vListRemove (see above)\r
+ | | | | \r
+ | | | +- vListInsert (see above)\r
+ | | | | \r
+ | | | +- xTaskResumeAll (see above)\r
+ | | | \r
+ | | +- xTaskCreate (see above)\r
+ | | | \r
+ | | +- vPolledQueueProducer\r
+ | | | \r
+ | | +- xQueueSend \r
+ | | | | \r
+ | | | +- vTaskSuspendAll (see above)\r
+ | | | | \r
+ | | | +- prvIsQueueFull \r
+ | | | | \r
+ | | | +- vTaskPlaceOnEventList (see above)\r
+ | | | | \r
+ | | | +- prvUnlockQueue (see above)\r
+ | | | | \r
+ | | | +- xTaskResumeAll (see above)\r
+ | | | | \r
+ | | | +- _memcpy_8bitCount (see above)\r
+ | | | \r
+ | | +- vTaskDelay (see above)\r
+ | | \r
+ | +- vStartDynamicPriorityTasks\r
+ | | | \r
+ | | +- xQueueCreate (see above)\r
+ | | | \r
+ | | +- vContinuousIncrementTask\r
+ | | | | \r
+ | | | +- uxTaskPriorityGet \r
+ | | | | \r
+ | | | +- vTaskPrioritySet \r
+ | | | | | \r
+ | | | | +- vListRemove (see above)\r
+ | | | | | \r
+ | | | | +- vListInsertEnd (see above)\r
+ | | | | \r
+ | | | +- _LINC \r
+ | | | \r
+ | | +- xTaskCreate (see above)\r
+ | | | \r
+ | | +- vLimitedIncrementTask\r
+ | | | | \r
+ | | | +- _LINC (see above)\r
+ | | | | \r
+ | | | +- _LCMP_P \r
+ | | | | \r
+ | | | +- vTaskSuspend \r
+ | | | | \r
+ | | | +- vListRemove (see above)\r
+ | | | | \r
+ | | | +- vListInsertEnd (see above)\r
+ | | | \r
+ | | +- vCounterControlTask \r
+ | | | | \r
+ | | | +- vTaskSuspend (see above)\r
+ | | | | \r
+ | | | +- vTaskResume \r
+ | | | | | \r
+ | | | | +- vListRemove (see above)\r
+ | | | | | \r
+ | | | | +- vListInsertEnd (see above)\r
+ | | | | \r
+ | | | +- vTaskDelay (see above)\r
+ | | | | \r
+ | | | +- vTaskSuspendAll (see above)\r
+ | | | | \r
+ | | | +- xTaskResumeAll (see above)\r
+ | | | \r
+ | | +- vQueueSendWhenSuspendedTask\r
+ | | | | \r
+ | | | +- vTaskSuspendAll (see above)\r
+ | | | | \r
+ | | | +- xQueueSend (see above)\r
+ | | | | \r
+ | | | +- xTaskResumeAll (see above)\r
+ | | | | \r
+ | | | +- vTaskDelay (see above)\r
+ | | | | \r
+ | | | +- _LINC (see above)\r
+ | | | \r
+ | | +- vQueueReceiveWhenSuspendedTask\r
+ | | | \r
+ | | +- vTaskSuspendAll (see above)\r
+ | | | \r
+ | | +- xQueueReceive (see above)\r
+ | | | \r
+ | | +- xTaskResumeAll (see above)\r
+ | | | \r
+ | | +- _LINC (see above)\r
+ | | \r
+ | +- vErrorChecks \r
+ | | | \r
+ | | +- xTaskGetTickCount (see above)\r
+ | | | \r
+ | | +- vTaskDelayUntil (see above)\r
+ | | | \r
+ | | +- prvCheckOtherTasksAreStillRunning\r
+ | | | | \r
+ | | | +- xArePollingQueuesStillRunning\r
+ | | | | \r
+ | | | +- xAreDynamicPriorityTasksStillRunning\r
+ | | | \r
+ | | +- _LCMP \r
+ | | | \r
+ | | +- vParTestToggleLED (see above)\r
+ | | \r
+ | +- xTaskCreate (see above)\r
+ | | \r
+ | +- vButtonTask \r
+ | | | \r
+ | | +- xQueueCreate (see above)\r
+ | | | \r
+ | | +- ButtonInterrupt_Enable\r
+ | | | \r
+ | | +- xQueueReceive (see above)\r
+ | | | \r
+ | | +- vParTestToggleLED (see above)\r
+ | | \r
+ | +- vTaskStartScheduler \r
+ | | \r
+ | +- prvIdleTask \r
+ | | | \r
+ | | +- prvCheckTasksWaitingTermination\r
+ | | | \r
+ | | +- vApplicationIdleHook\r
+ | | | \r
+ | | +- _LNEG \r
+ | | | \r
+ | | +- _LDIVS \r
+ | | | | \r
+ | | | +- _NEG_P \r
+ | | | | \r
+ | | | +- _lDivMod \r
+ | | | \r
+ | | +- _LCMP_P (see above)\r
+ | | \r
+ | +- xTaskCreate (see above)\r
+ | | \r
+ | +- xPortStartScheduler \r
+ | | \r
+ | +- xBankedStartScheduler\r
+ | | \r
+ | +- prvSetupTimerInterrupt\r
+ | | \r
+ | +- TickTimer_SetFreqHz \r
+ | | | \r
+ | | +- _LDIVU \r
+ | | | | \r
+ | | | +- _lDivMod (see above)\r
+ | | | \r
+ | | +- PE_Timer_LngHi1 \r
+ | | | | \r
+ | | | +- _LCMP (see above)\r
+ | | | \r
+ | | +- SetCV (see above)\r
+ | | \r
+ | +- TickTimer_Enable \r
+ | | \r
+ | +- HWEnDi (see above)\r
+ | \r
+ +- _EntryPoint \r
+ | \r
+ +- _Startup \r
+ | \r
+ +- Init \r
+ \r
+ _vect \r
+ | \r
+ +- Cpu_Interrupt \r
+ | \r
+ +- vButtonPush \r
+ | | \r
+ | +- xQueueSendFromISR \r
+ | | | \r
+ | | +- _memcpy_8bitCount (see above)\r
+ | | | \r
+ | | +- xTaskRemoveFromEventList (see above)\r
+ | | \r
+ | +- vTaskSwitchContext \r
+ | \r
+ +- vPortTickInterrupt \r
+ | | \r
+ | +- vTaskIncrementTick (see above)\r
+ | | \r
+ | +- vTaskSwitchContext (see above)\r
+ | \r
+ +- vPortYield \r
+ | | \r
+ | +- vTaskSwitchContext (see above)\r
+ | \r
+ +- _EntryPoint (see above)\r
+ \r
+*********************************************************************************************\r
+STATISTIC SECTION\r
+---------------------------------------------------------------------------------------------\r
+\r
+ExeFile:\r
+--------\r
+Number of blocks to be downloaded: 11\r
+Total size of all blocks to be downloaded: 5207\r
+\r
--- /dev/null
+// After load the commands written below will be executed\r
+// Show main function at startup\r
+FindProc main\r
--- /dev/null
+// Before load the commands written below will be executed\r
--- /dev/null
+// After reset the commands written below will be executed\r
--- /dev/null
+// At startup the commands written below will be executed\r
--- /dev/null
+// At startup the commands written below will be executed\r
--- /dev/null
+// After load the commands written below will be executed\r
+// Show main function at startup\r
+FindProc main\r
--- /dev/null
+// Before load the commands written below will be executed\r
--- /dev/null
+// After reset the commands written below will be executed\r
--- /dev/null
+// At startup the commands written below will be executed\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+\r
+/*\r
+ *\r
+ * vMain() is effectively the demo application entry point. It is called by\r
+ * the main() function generated by the Processor Expert application. \r
+ *\r
+ * vMain() creates all the demo application tasks, then starts the scheduler.\r
+ * The WEB documentation provides more details of the demo application tasks.\r
+ *\r
+ * Main.c also creates a task called "Check". This only executes every three \r
+ * seconds but has the highest priority so is guaranteed to get processor time. \r
+ * Its main function is to check that all the other tasks are still operational.\r
+ * Each task (other than the "flash" tasks) maintains a unique count that is \r
+ * incremented each time the task successfully completes its function. Should \r
+ * any error occur within such a task the count is permanently halted. The \r
+ * check task inspects the count of each task to ensure it has changed since\r
+ * the last time the check task executed. If all the count variables have \r
+ * changed all the tasks are still executing error free, and the check task\r
+ * toggles the onboard LED. Should any task contain an error at any time \r
+ * the LED toggle rate will change from 3 seconds to 500ms.\r
+ *\r
+ * This file also includes the functionality normally implemented within the \r
+ * standard demo application file integer.c. Due to the limited memory \r
+ * available on the microcontroller the functionality has been included within\r
+ * the idle task hook [vApplicationIdleHook()] - instead of within the usual\r
+ * separate task. See the documentation within integer.c for the rationale \r
+ * of the integer task functionality.\r
+ *\r
+ *\r
+ * \r
+ * The demo applications included with other FreeRTOS ports make use of the\r
+ * standard ComTest tasks. These use a loopback connector to transmit and\r
+ * receive RS232 characters between two tasks. The test is important for two\r
+ * reasons:\r
+ *\r
+ * 1) It tests the mechanism of context switching from within an application\r
+ * ISR.\r
+ *\r
+ * 2) It generates some randomised timing.\r
+ *\r
+ * The demo board used to develop this port does not include an RS232 interface\r
+ * so the ComTest tasks could not easily be included. Instead these two tests\r
+ * are created using a 'Button Push' task. \r
+ * \r
+ * The 'Button Push' task blocks on a queue, waiting for data to arrive. A\r
+ * simple interrupt routine connected to the PP0 input on the demo board places\r
+ * data in the queue each time the PP0 button is pushed (this button is built \r
+ * onto the demo board). As the 'Button Push' task is created with a \r
+ * relatively high priority it will unblock and want to execute as soon as data\r
+ * arrives in the queue - resulting in a context switch within the PP0 input\r
+ * ISR. If the data retrieved from the queue is that expected the 'Button Push'\r
+ * task toggles LED 5. Therefore correct operation is indicated by the LED\r
+ * toggling each time the PP0 button is pressed.\r
+ *\r
+ * This test is not as satisfactory as the ComTest method - but the simple \r
+ * nature of the port makes is just about adequate.\r
+ * \r
+ */\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+\r
+/* Demo application includes. */\r
+#include "flash.h"\r
+#include "PollQ.h"\r
+#include "dynamic.h"\r
+#include "partest.h"\r
+\r
+/* Processor expert includes. */\r
+#include "ButtonInterrupt.h"\r
+\r
+/*-----------------------------------------------------------\r
+ Definitions.\r
+-----------------------------------------------------------*/\r
+\r
+/* Priorities assigned to demo application tasks. */\r
+#define mainFLASH_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+#define mainBUTTON_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+\r
+/* LED that is toggled by the check task. The check task periodically checks\r
+that all the other tasks are operating without error. If no errors are found\r
+the LED is toggled with mainCHECK_PERIOD frequency. If an error is found \r
+then the toggle rate increases to mainERROR_CHECK_PERIOD. */\r
+#define mainCHECK_TASK_LED ( 7 )\r
+#define mainCHECK_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS )\r
+#define mainERROR_CHECK_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS )\r
+\r
+/* LED that is toggled by the button push interrupt. */\r
+#define mainBUTTON_PUSH_LED ( 5 )\r
+\r
+/* The constants used in the idle task calculation. */\r
+#define intgCONST1 ( ( portLONG ) 123 )\r
+#define intgCONST2 ( ( portLONG ) 234567 )\r
+#define intgCONST3 ( ( portLONG ) -3 )\r
+#define intgCONST4 ( ( portLONG ) 7 )\r
+#define intgEXPECTED_ANSWER ( ( ( intgCONST1 + intgCONST2 ) * intgCONST3 ) / intgCONST4 )\r
+\r
+/* The length of the queue between is button push ISR and the Button Push task\r
+is greater than 1 to account for switch bounces generating multiple inputs. */\r
+#define mainBUTTON_QUEUE_SIZE 6\r
+\r
+/*-----------------------------------------------------------\r
+ Local functions prototypes.\r
+-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The 'Check' task function. See the explanation at the top of the file.\r
+ */\r
+static void vErrorChecks( void* pvParameters );\r
+\r
+/*\r
+ * The 'Button Push' task. See the explanation at the top of the file.\r
+ */\r
+static void vButtonTask( void *pvParameters );\r
+\r
+/*\r
+ * The idle task hook - in which the integer task is implemented. See the\r
+ * explanation at the top of the file.\r
+ */\r
+void vApplicationIdleHook( void );\r
+\r
+/*\r
+ * Checks the unique counts of other tasks to ensure they are still operational.\r
+ */\r
+static portLONG prvCheckOtherTasksAreStillRunning( void );\r
+\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ Local variables.\r
+-----------------------------------------------------------*/\r
+\r
+/* A few tasks are defined within this file. This flag is used to indicate\r
+their status. If an error is detected in one of the locally defined tasks then\r
+this flag is set to pdTRUE. */\r
+portBASE_TYPE xLocalError = pdFALSE;\r
+\r
+/* The queue used to send data from the button push ISR to the Button Push \r
+task. */\r
+static xQueueHandle xButtonQueue;\r
+\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* \r
+ * This is called from the main() function generated by the Processor Expert.\r
+ */\r
+void vMain( void )\r
+{\r
+ /* Start some of the standard demo tasks. */\r
+ vStartLEDFlashTasks( mainFLASH_PRIORITY );\r
+ vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
+ vStartDynamicPriorityTasks();\r
+ \r
+ /* Start the locally defined tasks. There is also a task implemented as\r
+ the idle hook. */\r
+ xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
+ xTaskCreate( vButtonTask, "Button", configMINIMAL_STACK_SIZE, NULL, mainBUTTON_TASK_PRIORITY, NULL );\r
+ \r
+ /* All the tasks have been created - start the scheduler. */\r
+ vTaskStartScheduler();\r
+ \r
+ /* Should not reach here! */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vErrorChecks( void *pvParameters )\r
+{\r
+portTickType xDelayPeriod = mainCHECK_PERIOD;\r
+portTickType xLastWakeTime;\r
+\r
+ /* Initialise xLastWakeTime to ensure the first call to vTaskDelayUntil()\r
+ functions correctly. */\r
+ xLastWakeTime = xTaskGetTickCount();\r
+\r
+ for( ;; )\r
+ {\r
+ /* Delay until it is time to execute again. The delay period is \r
+ shorter following an error. */\r
+ vTaskDelayUntil( &xLastWakeTime, xDelayPeriod );\r
+\r
+ /* Check all the demo application tasks are executing without \r
+ error. If an error is found the delay period is shortened - this\r
+ has the effect of increasing the flash rate of the 'check' task\r
+ LED. */\r
+ if( prvCheckOtherTasksAreStillRunning() == pdFAIL )\r
+ {\r
+ /* An error has been detected in one of the tasks - flash faster. */\r
+ xDelayPeriod = mainERROR_CHECK_PERIOD;\r
+ }\r
+\r
+ /* Toggle the LED each cycle round. */\r
+ vParTestToggleLED( mainCHECK_TASK_LED );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portLONG prvCheckOtherTasksAreStillRunning( void )\r
+{\r
+portBASE_TYPE xAllTasksPassed = pdPASS;\r
+\r
+ if( xArePollingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ xAllTasksPassed = pdFAIL;\r
+ }\r
+\r
+ if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )\r
+ {\r
+ xAllTasksPassed = pdFAIL;\r
+ }\r
+\r
+ /* Also check the status flag for the tasks defined within this function. */\r
+ if( xLocalError != pdFALSE )\r
+ {\r
+ xAllTasksPassed = pdFAIL;\r
+ }\r
+\r
+ return xAllTasksPassed;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationIdleHook( void )\r
+{\r
+/* This variable is effectively set to a constant so it is made volatile to\r
+ensure the compiler does not just get rid of it. */\r
+volatile portLONG lValue;\r
+\r
+ /* Keep performing a calculation and checking the result against a constant. */\r
+ for( ;; )\r
+ {\r
+ /* Perform the calculation. This will store partial value in\r
+ registers, resulting in a good test of the context switch mechanism. */\r
+ lValue = intgCONST1;\r
+ lValue += intgCONST2;\r
+ lValue *= intgCONST3;\r
+ lValue /= intgCONST4;\r
+\r
+ /* Did we perform the calculation correctly with no corruption? */\r
+ if( lValue != intgEXPECTED_ANSWER )\r
+ {\r
+ /* Error! */\r
+ portENTER_CRITICAL();\r
+ xLocalError = pdTRUE;\r
+ portEXIT_CRITICAL();\r
+ }\r
+\r
+ /* Yield in case cooperative scheduling is being used. */\r
+ #if configUSE_PREEMPTION == 0\r
+ {\r
+ taskYIELD();\r
+ }\r
+ #endif \r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vButtonTask( void *pvParameters )\r
+{\r
+unsigned portBASE_TYPE uxExpected = 1, uxReceived;\r
+\r
+ /* Create the queue used by the producer and consumer. */\r
+ xButtonQueue = xQueueCreate( mainBUTTON_QUEUE_SIZE, ( unsigned portBASE_TYPE ) sizeof( unsigned portBASE_TYPE ) );\r
+\r
+ if( xButtonQueue )\r
+ {\r
+ /* Now the queue is created it is safe to enable the button interrupt. */\r
+ ButtonInterrupt_Enable();\r
+ \r
+ for( ;; )\r
+ {\r
+ /* Simply wait for data to arrive from the button push interrupt. */\r
+ if( xQueueReceive( xButtonQueue, &uxReceived, portMAX_DELAY ) == pdPASS ) \r
+ {\r
+ /* Was the data we received that expected? */\r
+ if( uxReceived != uxExpected )\r
+ {\r
+ /* Error! */\r
+ portENTER_CRITICAL();\r
+ xLocalError = pdTRUE;\r
+ portEXIT_CRITICAL(); \r
+ }\r
+ else\r
+ {\r
+ /* Toggle the LED for every successful push. */\r
+ vParTestToggleLED( mainBUTTON_PUSH_LED ); \r
+ }\r
+ \r
+ uxExpected++;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Will only get here if the queue could not be created. */\r
+ for( ;; ); \r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#pragma CODE_SEG __NEAR_SEG NON_BANKED\r
+\r
+ /* Button push ISR. */\r
+ void interrupt vButtonPush( void )\r
+ {\r
+ static unsigned portBASE_TYPE uxValToSend = 0;\r
+ \r
+ /* Send an incrementing value to the button push task each run. */\r
+ uxValToSend++; \r
+\r
+ /* Clear the interrupt flag. */\r
+ PIFP = 1;\r
+\r
+ /* Send the incremented value down the queue. The button push task is\r
+ blocked waiting for the data. As the button push task is high priority\r
+ it will wake and a context switch should be performed before leaving\r
+ the ISR. */\r
+ if( xQueueSendFromISR( xButtonQueue, &uxValToSend, pdFALSE ) )\r
+ {\r
+ /* NOTE: This macro can only be used if there are no local\r
+ variables defined. This function uses a static variable so it's\r
+ use is permitted. If the variable were not static portYIELD() \r
+ would have to be used in it's place. */\r
+ portTASK_SWITCH_FROM_ISR();\r
+ } \r
+ }\r
+\r
+#pragma CODE_SEG DEFAULT\r
+\r
+\r
--- /dev/null
+/* logical s-record file */\r
+OPENFILE "%ABS_FILE%.s19"\r
+format=motorola\r
+busWidth=1\r
+origin=0\r
+len=0x1000000\r
+destination=0\r
+SRECORD=Sx\r
+SENDBYTE 1 "%ABS_FILE%"\r
+CLOSE\r
+\r
+/* physical s-record file */\r
+OPENFILE "%ABS_FILE%.phy"\r
+format = motorola\r
+busWidth = 1\r
+len = 0x4000\r
+\r
+origin = 0x008000\r
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+\r
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+SENDBYTE 1 "%ABS_FILE%"\r
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+SENDBYTE 1 "%ABS_FILE%"\r
+\r
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+SENDBYTE 1 "%ABS_FILE%"\r
+origin = 0x00C000\r
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+SENDBYTE 1 "%ABS_FILE%"\r
+\r
+CLOSE\r
+\r
--- /dev/null
+//------------------------------------------------------------------------\r
+// Readme.txt\r
+//------------------------------------------------------------------------\r
+This project stationery is designed to get you up and running\r
+quickly with CodeWarrior for MC9S12C32.\r
+It is set up for the selected CPU and target connection,\r
+but can be easily modified.\r
+\r
+Sample code for the following language(s) is at your disposal:\r
+- C\r
+\r
+The wizard has prepared CodeWarrior target(s) with the connection methods of\r
+your choice:\r
+- Simulator:\r
+ This interface/target is prepared to use the FCS (Full Chip Simulation).\r
+\r
+- SofTec:\r
+ This target interface connects to any of the USB-based SofTec Microsystems tools for HC(S)12.\r
+ \r
+\r
+Additional connections can be chosen in the simulator/debugger,\r
+use the menu Component > Set Target.\r
+\r
+//------------------------------------------------------------------------\r
+// Processor Expert\r
+//------------------------------------------------------------------------\r
+This project is prepared to be designed with Processor Expert.\r
+The project has an additional 'tab' named 'Processor Expert' where you\r
+can configure the CPU and its beans.\r
+The CPU selected is inserted into the Processor Expert project panel, in\r
+the Debug and Release configurations.\r
+Change of the configuration is possible by the mouse double-click on it.\r
+All the installed Embedded Beans are accessible in the Bean Selector\r
+window, grouped into folders according to their function. The mouse\r
+double-click on selected Embedded Bean in the Bean Selector window adds\r
+the Bean to the project. The mouse double-click on the Bean icon in the\r
+Project panel opens the Bean Inspector window, which is used to set the\r
+Bean properties. Source code is generated after selecting the\r
+(Code Design 'Project_name.mcp') menu command from the CodeWarrior main\r
+window (Processor Expert > Code design 'Project_name.mcp').\r
+Use the bean methods and events to write your code in the main module\r
+'Project_name'.c and the event module Events.c.\r
+\r
+For more help please read Processor Expert help:\r
+ (Processor Expert > Help > 'Topic').\r
+\r
+The following folders are used in CodeWarrior project window for\r
+ProcessorExpert:\r
+- User modules: contains your sources. The main module 'Project_name'.c\r
+ and event module Events.c are located here after the Processor Expert\r
+ code generation.\r
+- Prm: Linker parameter file used for linking. Note that the file used\r
+ for the linker is specified in the Linker Preference Panel. To open\r
+ the Preference Panel, please press <ALT-F7> or open the\r
+ (Edit > 'Current Build Target Name' Settings...) menu item in the\r
+ CodeWarrior main window menu, while the project window is opened).\r
+ After Processor Expert code generation 'Project_name'.prm file\r
+ will be placed here. You can switch off the .prm file generation in\r
+ Processor Expert if you want (in the CPU bean, Build Options)\r
+- Generated code: this folder appears after the Processor Expert code\r
+ generation and contains generated code from Processor Expert.\r
+- Doc: other files generated from the Processor Expert (documentation)\r
+\r
+//------------------------------------------------------------------------\r
+// Getting Started\r
+//------------------------------------------------------------------------\r
+To build/debug your project, use the menu Project > Debug or press F5.\r
+This will open the simulator/debugger.\r
+Press again F5 in the debugger (or menu Run > Start/Continue) to start\r
+the application. The menu Run > Halt or F6 stops the application.\r
+In the debugger menu Component > Open you can load additional components.\r
+\r
+//------------------------------------------------------------------------\r
+// Project structure\r
+//------------------------------------------------------------------------\r
+The project generated contains various files/folders:\r
+- readme.txt: this file\r
+- Sources: folder with the application source code\r
+- Startup Code: C/C++ startup code\r
+- Prm:\r
+ - burner.bbl file to generate S-Records\r
+- Linker Map: the .map file generated by the linker\r
+- Libraries: needed library files (ANSI, derivative header/implementation files)\r
+- Debugger Project File: contains a .ini file for the debugger for each\r
+ connection\r
+- Debugger Cmd Files: contains sub-folders for each connection with command\r
+ files\r
+\r
+//------------------------------------------------------------------------\r
+// Adding your own code\r
+//------------------------------------------------------------------------\r
+Once everything is working as expected, you can begin adding your own code\r
+to the project. Keep in mind that we provide this as an example of how to\r
+get up and running quickly with CodeWarrior. There are certainly other\r
+ways to handle interrupts and set up your linker command file. Feel free\r
+to modify any of the source files provided.\r
+\r
+//------------------------------------------------------------------------\r
+// Simulator/Debugger: Additional components\r
+//------------------------------------------------------------------------\r
+In the simulator/debugger, you can load additional components. Try the menu\r
+Component > Open.\r
+\r
+//------------------------------------------------------------------------\r
+// Additional documentation\r
+//------------------------------------------------------------------------\r
+Check out the online documentation provided. Use in CodeWarrior IDE the\r
+menu Help > Online Manuals.\r
+\r
+//------------------------------------------------------------------------\r
+// Contacting Metrowerks\r
+//------------------------------------------------------------------------\r
+For bug reports, technical questions, and suggestions, please use the\r
+forms installed in the Release_Notes folder and send them to:\r
+USA: support@metrowerks.com\r
+EUROPE: support_europe@metrowerks.com\r
+ASIA/PACIFIC: j-emb-sup@metrowerks.com
\ No newline at end of file
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+\r
+/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER for port 1.\r
+\r
+Note that this driver is written to test the RTOS port and is not intended\r
+to represent an optimised solution. */\r
+\r
+/* Standard include files. */\r
+#include <stdlib.h>\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "queue.h"\r
+#include "task.h"\r
+\r
+/* Demo application include files. */\r
+#include "serial.h"\r
+\r
+\r
+/*\r
+ * Initialise port 1 for interrupt driven communications.\r
+ */\r
+xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )\r
+{\r
+ return NULL;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )\r
+{\r
+ return pdFALSE;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )\r
+{\r
+signed portBASE_TYPE xReturn = pdPASS;\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSerialClose( xComPortHandle xPort )\r
+{ \r
+ /* Not supported. */\r
+ ( void ) xPort;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+#include "xparameters.h"\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. \r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 100000000 )\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 4 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 120 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 18 * 1024 ) )\r
+#define configMAX_TASK_NAME_LEN ( 5 )\r
+#define configUSE_TRACE_FACILITY 0\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 0\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 0\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple parallel port IO routines.\r
+ *-----------------------------------------------------------*/\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+\r
+/* Demo application includes. */\r
+#include "partest.h"\r
+\r
+/* Library includes. */\r
+#include "xgpio_l.h"\r
+\r
+/* Misc hardware specific definitions. */\r
+#define partstALL_AS_OUTPUT 0x00\r
+#define partstCHANNEL_1 0x01\r
+#define partstMAX_4BIT_LED 0x03\r
+\r
+/* The outputs are split into two IO sections, these variables maintain the \r
+current value of either section. */\r
+static unsigned portBASE_TYPE uxCurrentOutput4Bit, uxCurrentOutput5Bit;\r
+\r
+/*-----------------------------------------------------------*/\r
+/*\r
+ * Setup the IO for the LED outputs.\r
+ */\r
+void vParTestInitialise( void )\r
+{\r
+ /* Set both sets of LED's on the demo board to outputs. */\r
+ XGpio_mSetDataDirection( XPAR_LEDS_4BIT_BASEADDR, partstCHANNEL_1, partstALL_AS_OUTPUT );\r
+ XGpio_mSetDataDirection( XPAR_LEDS_POSITIONS_BASEADDR, partstCHANNEL_1, partstALL_AS_OUTPUT );\r
+\r
+ /* Start with all outputs off. */\r
+ uxCurrentOutput4Bit = 0;\r
+ XGpio_mSetDataReg( XPAR_LEDS_4BIT_BASEADDR, partstCHANNEL_1, 0x00 );\r
+ uxCurrentOutput5Bit = 0;\r
+ XGpio_mSetDataReg( XPAR_LEDS_POSITIONS_BASEADDR, partstCHANNEL_1, 0x00 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )\r
+{\r
+unsigned portBASE_TYPE uxBaseAddress, *puxCurrentValue;\r
+\r
+ portENTER_CRITICAL();\r
+ {\r
+ /* Which IO section does the LED being set/cleared belong to? The\r
+ 4 bit or 5 bit outputs? */\r
+ if( uxLED <= partstMAX_4BIT_LED )\r
+ {\r
+ uxBaseAddress = XPAR_LEDS_4BIT_BASEADDR;\r
+ puxCurrentValue = &uxCurrentOutput4Bit;\r
+ } \r
+ else\r
+ {\r
+ uxBaseAddress = XPAR_LEDS_POSITIONS_BASEADDR;\r
+ puxCurrentValue = &uxCurrentOutput5Bit;\r
+ uxLED -= partstMAX_4BIT_LED;\r
+ }\r
+\r
+ /* Setup the bit mask accordingly. */\r
+ uxLED = 0x01 << uxLED;\r
+\r
+ /* Maintain the current output value. */\r
+ if( xValue )\r
+ {\r
+ *puxCurrentValue |= uxLED;\r
+ }\r
+ else\r
+ {\r
+ *puxCurrentValue &= ~uxLED;\r
+ }\r
+\r
+ /* Write the value to the port. */\r
+ XGpio_mSetDataReg( uxBaseAddress, partstCHANNEL_1, *puxCurrentValue );\r
+ }\r
+ portEXIT_CRITICAL();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+unsigned portBASE_TYPE uxBaseAddress, *puxCurrentValue;\r
+\r
+ portENTER_CRITICAL();\r
+ {\r
+ /* Which IO section does the LED being toggled belong to? The\r
+ 4 bit or 5 bit outputs? */\r
+ if( uxLED <= partstMAX_4BIT_LED )\r
+ {\r
+ uxBaseAddress = XPAR_LEDS_4BIT_BASEADDR;\r
+ puxCurrentValue = &uxCurrentOutput4Bit;\r
+ } \r
+ else\r
+ {\r
+ uxBaseAddress = XPAR_LEDS_POSITIONS_BASEADDR;\r
+ puxCurrentValue = &uxCurrentOutput5Bit;\r
+ uxLED -= partstMAX_4BIT_LED;\r
+ }\r
+\r
+ /* Setup the bit mask accordingly. */\r
+ uxLED = 0x01 << uxLED;\r
+\r
+ /* Maintain the current output value. */\r
+ if( *puxCurrentValue & uxLED )\r
+ {\r
+ *puxCurrentValue &= ~uxLED;\r
+ }\r
+ else\r
+ {\r
+ *puxCurrentValue |= uxLED;\r
+ }\r
+\r
+ /* Write the value to the port. */\r
+ XGpio_mSetDataReg(uxBaseAddress, partstCHANNEL_1, *puxCurrentValue );\r
+ }\r
+ portEXIT_CRITICAL();\r
+}\r
+\r
+\r
--- /dev/null
+ -pe microblaze_0 RTOSDemo/executable.elf\r
--- /dev/null
+ -p virtex4\r
--- /dev/null
+ -p virtex4 -lang vhdl -st xst\r
--- /dev/null
+microblaze_0\r
+RTOSDEMO_SOURCES = main.c ParTest/ParTest.c ../../Source/tasks.c ../../Source/queue.c ../../Source/list.c ../../Source/portable/MemMang/heap_1.c ../../Source/portable/GCC/MicroBlaze/port.c ../../Source/portable/GCC/MicroBlaze/portasm.s ../Common/Minimal/flash.c serial/serial.c ../Common/Minimal/comtest.c ../Common/Minimal/integer.c ../Common/Minimal/semtest.c ../Common/Minimal/dynamic.c ../Common/Minimal/PollQ.c ../Common/Minimal/BlockQ.c \r
+RTOSDEMO_HEADERS = FreeRTOSConfig.h \r
+RTOSDEMO_CC = mb-gcc\r
+RTOSDEMO_CC_SIZE = mb-size\r
+RTOSDEMO_CC_OPT = -Os\r
+RTOSDEMO_CFLAGS = -D MICROBLAZE_GCC -Wall\r
+RTOSDEMO_CC_SEARCH = # -B\r
+RTOSDEMO_LIBPATH = -L./microblaze_0/lib/ # -L\r
+RTOSDEMO_INCLUDES = -I./microblaze_0/include/ -IDev/FreeRTOS/Demo/MicroBlaze/ -I. -I../Common/include -I../../Source/include -I../../Source/portable/GCC/MicroBlaze \r
+RTOSDEMO_LFLAGS = # -l\r
+RTOSDEMO_CC_PREPROC_FLAG = # -Wp,\r
+RTOSDEMO_CC_ASM_FLAG = # -Wa,\r
+RTOSDEMO_CC_LINKER_FLAG = -Wl,-Map=rtosdemo.map \r
+RTOSDEMO_LINKER_SCRIPT = \r
+RTOSDEMO_CC_DEBUG_FLAG = -g \r
+RTOSDEMO_CC_GLOBPTR_FLAG= # -mxl-gp-opt\r
+RTOSDEMO_MODE = executable\r
+RTOSDEMO_LIBG_OPT = -$(RTOSDEMO_MODE) microblaze_0\r
+RTOSDEMO_CC_SOFTMUL_FLAG= -mno-xl-soft-mul \r
+RTOSDEMO_CC_START_ADDR_FLAG= # -Wl,-defsym -Wl,_TEXT_START_ADDR=\r
+RTOSDEMO_CC_STACK_SIZE_FLAG= # -Wl,-defsym -Wl,_STACK_SIZE=\r
+ $(RTOSDEMO_CC_SOFTMUL_FLAG) \\r
--- /dev/null
+ -p virtex4 -lang vhdl -pe microblaze_0 RTOSDemo/executable.elf -s mti\r
--- /dev/null
+microblaze_0\r
+TESTAPP_PERIPHERAL_SOURCES = TestApp_Peripheral/src/TestApp_Peripheral.c TestApp_Peripheral/src/xuartlite_selftest_example.c \r
+TESTAPP_PERIPHERAL_HEADERS = \r
+TESTAPP_PERIPHERAL_CC = mb-gcc\r
+TESTAPP_PERIPHERAL_CC_SIZE = mb-size\r
+TESTAPP_PERIPHERAL_CC_OPT = -O2\r
+TESTAPP_PERIPHERAL_CFLAGS = \r
+TESTAPP_PERIPHERAL_CC_SEARCH = # -B\r
+TESTAPP_PERIPHERAL_LIBPATH = -L./microblaze_0/lib/ # -L\r
+TESTAPP_PERIPHERAL_INCLUDES = -I./microblaze_0/include/ # -I\r
+TESTAPP_PERIPHERAL_LFLAGS = # -l\r
+TESTAPP_PERIPHERAL_CC_PREPROC_FLAG = # -Wp,\r
+TESTAPP_PERIPHERAL_CC_ASM_FLAG = # -Wa,\r
+TESTAPP_PERIPHERAL_CC_LINKER_FLAG = # -Wl,\r
+TESTAPP_PERIPHERAL_LINKER_SCRIPT = TestApp_Peripheral/src/TestApp_Peripheral_LinkScr\r
+TESTAPP_PERIPHERAL_CC_DEBUG_FLAG = -g \r
+TESTAPP_PERIPHERAL_CC_GLOBPTR_FLAG= # -mxl-gp-opt\r
+TESTAPP_PERIPHERAL_MODE = executable\r
+TESTAPP_PERIPHERAL_LIBG_OPT = -$(TESTAPP_PERIPHERAL_MODE) microblaze_0\r
+TESTAPP_PERIPHERAL_CC_SOFTMUL_FLAG= -mno-xl-soft-mul \r
+TESTAPP_PERIPHERAL_CC_START_ADDR_FLAG= # -Wl,-defsym -Wl,_TEXT_START_ADDR=\r
+TESTAPP_PERIPHERAL_CC_STACK_SIZE_FLAG= # -Wl,-defsym -Wl,_STACK_SIZE=\r
+ $(TESTAPP_PERIPHERAL_CC_SOFTMUL_FLAG) \\r
--- /dev/null
+ -p xc4vfx12ff668-10\r
--- /dev/null
+-device xc4vfx12ff668-10\r
--- /dev/null
+setMode -bs\r
+setCable -port auto\r
+identify\r
+identifyMPM\r
+setAttribute -position 3 -attr configFileName -value "implementation/download.bit"\r
+program -p 3 \r
+quit\r
--- /dev/null
+###################################-*-asm*-
+#
+# Copyright (c) 2001 Xilinx, Inc. All rights reserved.
+#
+# Xilinx, Inc. CONFIDENTIAL
+#
+# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
+# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
+# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
+# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
+# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
+# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
+# AND FITNESS FOR A PARTICULAR PURPOSE.
+#
+# crt0.s
+#
+# C RunTime:
+# Used for initialization of small data
+# anchors and stack for programs compiled using
+# Xilinx Gnu Tools. This routine also intializes the
+# exception and interrupt handlers
+#
+# $Id: crt0.s,v 1.1.4.2 2005/05/26 21:50:39 vasanth Exp $
+#
+#######################################
+
+/* Vector map (Interrupts, Exceptions, Breakpoints) */
+# # 0x00 # Jump to Start
+# # 0x04 # nop
+# # 0x08 # Imm instr for soft exception address [Hi halfword]
+# # 0x0c # Jump to sof Exception handler [Lo halfword]
+# # 0x10 # Imm instr for interrupt address [Hi halfword]
+# # 0x14 # Jump to interrupt handler [Lo halfword]
+# # 0x18 # nop - Reserved for breakpoint vector
+# # 0x1C # nop - Reserved for breakpoint vector
+# # 0x20 # Imm instr for hw exception address [Hi halfword]
+# # 0x24 # Jump instr to hw exception handler [Lo halfword]
+
+ .globl _start
+
+/* Set the exception and interrupt address vectors */
+/* to jump to the appropriate handlers */
+
+ .align 2
+ .ent _start
+ _start:
+ bri _start1 # 0x00
+ nop # 0x04
+ nop # 0x08 # Reserve space for software exception vector
+ nop # 0x0c
+ nop # 0x10 # Reserve space for interrupt vector
+ nop # 0x14
+ nop # 0x18 # Reserve space for breakpoint vector
+ nop # 0x1c
+ nop # 0x18 # Reserve space for hw exception vector
+ nop # 0x1c
+
+ _start1:
+/* Set the Small Data Anchors and the Stack pointer */
+ la r13, r0, _SDA_BASE_
+ la r2, r0, _SDA2_BASE_
+ la r1, r0, _stack-16 # 16 bytes (4 words are needed by
+ # crt for args and link reg )
+
+/* Set the opcodes brai and imm for handlers */
+ la r6,r0,0xb8080000 # [opcode for brai ]
+ swi r6,r0,0x4 # [brai opcode for reset]
+ swi r6,r0,0xc # [brai opcode for exception]
+ swi r6,r0,0x14 # [brai opcode for interrupt]
+ swi r6,r0,0x24 # [brai opcode for hw exceptions]
+
+ la r6,r0,0xb0000000 # [opcode for imm ]
+ swi r6,r0,0x0 # [imm opcode for reset]
+ swi r6,r0,0x8 # [imm opcode for exception]
+ swi r6,r0,0x10 # [imm opocde for interrupt]
+ swi r6,r0,0x20 # [imm opocde for hw exceptions]
+
+/* Set Reset vector */
+ la r6,r0,_start1
+ sw r6,r1,r0
+ lhu r7,r1,r0
+ shi r7,r0, 0x2 # [imm for reset]
+ shi r6,r0, 0x6 # [lower half for reset]
+
+/* Set Software Exception Handler */
+ la r6,r0,_exception_handler
+ sw r6,r1,r0
+ lhu r7,r1,r0
+ shi r7,r0, 0xa # [imm for exception]
+ shi r6,r0, 0xe # [lower half for exception ]
+
+/* Set Interrupt Handler */
+ la r6,r0,_interrupt_handler
+ sw r6,r1,r0
+ lhu r7,r1,r0
+ shi r7,r0, 0x12 # [imm for exception]
+ shi r6,r0, 0x16 # [lower half for intterupt ]
+
+/* Set HW Exception Handler */
+ la r6,r0,_hw_exception_handler
+ sw r6,r1,r0
+ lhu r7,r1,r0
+ shi r7,r0, 0x22 # [imm for exception]
+ shi r6,r0, 0x26 # [lower half for hw exception]
+
+/* initialize bss sections */
+ brlid r15,_crtinit
+ nop
+
+/* Adjust the stack pointer */
+ addi r1,r1,16
+
+/* Fall through to exit */
+ .end _start
+
+/* Use this exit function */
+ .globl exit # exit library call
+ .ent exit
+exit:
+ bri exit
+ .end exit
+
--- /dev/null
+############################################################################\r
+## This system.ucf file is generated by Base System Builder based on the\r
+## settings in the selected Xilinx Board Definition file. Please add other\r
+## user constraints to this file based on customer design specifications.\r
+############################################################################\r
+\r
+Net sys_clk_pin LOC=AE14;\r
+Net sys_clk_pin IOSTANDARD = LVCMOS33;\r
+Net sys_rst_pin LOC=D6;\r
+Net sys_rst_pin PULLUP;\r
+## System level constraints\r
+Net sys_clk_pin TNM_NET = sys_clk_pin;\r
+TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 10000 ps;\r
+Net sys_rst_pin TIG;\r
+\r
+## FPGA pin constraints\r
+Net fpga_0_RS232_Uart_RX_pin LOC=W2;\r
+Net fpga_0_RS232_Uart_RX_pin IOSTANDARD = LVCMOS33;\r
+Net fpga_0_RS232_Uart_TX_pin LOC=W1;\r
+Net fpga_0_RS232_Uart_TX_pin IOSTANDARD = LVCMOS33;\r
+Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> LOC=G5;\r
+Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25;\r
+Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> PULLUP;\r
+Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> SLEW = SLOW;\r
+Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> DRIVE = 2;\r
+Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> TIG;\r
+Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> LOC=G6;\r
+Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> IOSTANDARD = LVCMOS25;\r
+Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> PULLUP;\r
+Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> SLEW = SLOW;\r
+Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> DRIVE = 2;\r
+Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> TIG;\r
+Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> LOC=A11;\r
+Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> IOSTANDARD = LVCMOS25;\r
+Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> PULLUP;\r
+Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> SLEW = SLOW;\r
+Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> DRIVE = 2;\r
+Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> TIG;\r
+Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> LOC=A12;\r
+Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25;\r
+Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> PULLUP;\r
+Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> SLEW = SLOW;\r
+Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> DRIVE = 2;\r
+Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> TIG;\r
+Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> LOC=C6;\r
+Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25;\r
+Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> PULLUP;\r
+Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> SLEW = SLOW;\r
+Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> DRIVE = 2;\r
+Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> TIG;\r
+Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> LOC=F9;\r
+Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> IOSTANDARD = LVCMOS25;\r
+Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> PULLUP;\r
+Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> SLEW = SLOW;\r
+Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> DRIVE = 2;\r
+Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> TIG;\r
+Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> LOC=A5;\r
+Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> IOSTANDARD = LVCMOS25;\r
+Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> PULLUP;\r
+Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> SLEW = SLOW;\r
+Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> DRIVE = 2;\r
+Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> TIG;\r
+Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> LOC=E10;\r
+Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25;\r
+Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> PULLUP;\r
+Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> SLEW = SLOW;\r
+Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> DRIVE = 2;\r
+Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> TIG;\r
+Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> LOC=E2;\r
+Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> IOSTANDARD = LVCMOS25;\r
+Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> PULLUP;\r
+Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> SLEW = SLOW;\r
+Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> DRIVE = 2;\r
+Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> TIG;\r
--- /dev/null
+-g ConfigRate:4
+-g CclkPin:PULLUP
+-g TdoPin:PULLNONE
+-g M1Pin:PULLDOWN
+-g DonePin:PULLUP
+-g DriveDone:No
+-g StartUpClk:JTAGCLK
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g M0Pin:PULLUP
+-g M2Pin:PULLUP
+-g ProgPin:PULLUP
+-g TckPin:PULLUP
+-g TdiPin:PULLUP
+-g TmsPin:PULLUP
+-g DonePipe:No
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Security:NONE
+-m
+-g Persist:No
--- /dev/null
+-g CclkPin:PULLUP
+-g TdoPin:PULLNONE
+-g M1Pin:PULLDOWN
+-g DonePin:PULLUP
+-g StartUpClk:JTAGCLK
+-g M0Pin:PULLUP
+-g M2Pin:PULLUP
+-g ProgPin:PULLUP
+-g TckPin:PULLUP
+-g TdiPin:PULLUP
+-g TmsPin:PULLUP
+-g LCK_cycle:NoWait
+-g Security:NONE
+-m
+-g Persist:No
--- /dev/null
+setMode -bscan\r
+setCable -p auto\r
+identify\r
+assignfile -p 3 -file implementation/download.bit\r
+program -p 3\r
+quit\r
--- /dev/null
+FLOWTYPE = FPGA;
+###############################################################
+## Filename: fast_runtime.opt
+##
+## Option File For Xilinx FPGA Implementation Flow for Fast
+## Runtime.
+##
+## Version: 4.1.1
+###############################################################
+#
+# Options for Translator
+#
+# Type "ngdbuild -h" for a detailed list of ngdbuild command line options
+#
+Program ngdbuild
+-p <partname>; # Partname to use - picked from xflow commandline
+-nt timestamp; # NGO File generation. Regenerate only when
+ # source netlist is newer than existing
+ # NGO file (default)
+-bm <design>.bmm # Block RAM memory map file
+<userdesign>; # User design - pick from xflow command line
+-uc <design>.ucf; # ucf constraints
+<design>.ngd; # Name of NGD file. Filebase same as design filebase
+End Program ngdbuild
+
+#
+# Options for Mapper
+#
+# Type "map -h <arch>" for a detailed list of map command line options
+#
+Program map
+-o <design>_map.ncd; # Output Mapped ncd file
+-pr b; # Pack internal FF/latches into IOBs
+#-fp <design>.mfp; # Floorplan file
+<inputdir><design>.ngd; # Input NGD file
+<inputdir><design>.pcf; # Physical constraints file
+END Program map
+
+#
+# Options for Post Map Trace
+#
+# Type "trce -h" for a detailed list of trce command line options
+#
+Program post_map_trce
+-e 3; # Produce error report limited to 3 items per constraint
+#-o <design>_map.twr; # Output trace report file
+-xml <design>_map.twx; # Output XML version of the timing report
+#-tsi <design>_map.tsi; # Produce Timing Specification Interaction report
+<inputdir><design>_map.ncd; # Input mapped ncd
+<inputdir><design>.pcf; # Physical constraints file
+END Program post_map_trce
+
+#
+# Options for Place and Route
+#
+# Type "par -h" for a detailed list of par command line options
+#
+Program par
+-w; # Overwrite existing placed and routed ncd
+-ol high; # Overall effort level
+<inputdir><design>_map.ncd; # Input mapped NCD file
+<design>.ncd; # Output placed and routed NCD
+<inputdir><design>.pcf; # Input physical constraints file
+END Program par
+
+#
+# Options for Post Par Trace
+#
+# Type "trce -h" for a detailed list of trce command line options
+#
+Program post_par_trce
+-e 3; # Produce error report limited to 3 items per constraint
+#-o <design>.twr; # Output trace report file
+-xml <design>.twx; # Output XML version of the timing report
+#-tsi <design>.tsi; # Produce Timing Specification Interaction report
+<inputdir><design>.ncd; # Input placed and routed ncd
+<inputdir><design>.pcf; # Physical constraints file
+END Program post_par_trce
+
+
--- /dev/null
+connect mb mdm -cable type xilinx_parallel port LPT1 frequency 5000000 -debugdevice cpunr 1\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+ * Creates all the demo application tasks, then starts the scheduler. The WEB\r
+ * documentation provides more details of the standard demo application tasks.\r
+ *\r
+ * In addition to the standard tasks, main() creates two "Register Check" \r
+ * tasks. These tasks write known values into every general purpose register,\r
+ * then check each register to ensure it still contains the expected (written)\r
+ * value. The register check tasks operate at the idle priority so will get\r
+ * repeatedly preempted. A register being found to contain an incorrect value\r
+ * following such a preemption would be indicative of an error in the context\r
+ * switch mechanism.\r
+ * \r
+ * Main.c also creates a task called "Check". This only executes every three \r
+ * seconds but has the highest priority so is guaranteed to get processor time. \r
+ * Its main function is to check that all the other tasks are still operational.\r
+ * Each task (other than the "flash" tasks) maintains a unique count that is \r
+ * incremented each time the task successfully completes its function. Should \r
+ * any error occur within such a task the count is permanently halted. The \r
+ * check task inspects the count of each task to ensure it has changed since\r
+ * the last time the check task executed. If all the count variables have \r
+ * changed all the tasks are still executing error free, and the check task\r
+ * toggles the onboard LED. Should any task contain an error at any time \r
+ * the LED toggle rate will change from 3 seconds to 500ms.\r
+ *\r
+ */\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo application includes. */
+#include "ParTest.h"\r
+#include "flash.h"\r
+#include "comtest2.h"\r
+#include "integer.h"\r
+#include "semtest.h"\r
+#include "BlockQ.h"\r
+#include "dynamic.h"\r
+#include "PollQ.h"\r
+\r
+/* Hardware library includes. */\r
+#include <xintc.h>\r
+\r
+/* The rate at which the 'check' LED will flash when no errors have been\r
+detected. */\r
+#define mainNO_ERROR_CHECK_PERIOD 3000\r
+\r
+/* The rate at which the 'check' LED will flash when an error has been\r
+detected in one of the demo tasks. */\r
+#define mainERROR_CHECK_PERIOD 500\r
+\r
+/* Demo application task priorities. */\r
+#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+\r
+/* Software cannot influence the BAUD rate used by the simple UART \r
+implementation. */\r
+#define mainBAUD_RATE 0\r
+\r
+/* The LED flashed by the 'check' task to indicate the system status. */\r
+#define mainCHECK_TASK_LED 3\r
+\r
+/* The first LED flashed by the COM port test tasks. LED mainCOM_TEST_LED + 1\r
+will also be used. */\r
+#define mainCOM_TEST_LED 4\r
+\r
+/* The register test task does not make any function calls so does not require\r
+much stack at all. */\r
+#define mainTINY_STACK 70\r
+\r
+/*\r
+ * The task that executes at the highest priority and calls \r
+ * prvCheckOtherTasksAreStillRunning(). See the description at the top\r
+ * of the file.\r
+ */\r
+static void vErrorChecks( void *pvParameters );\r
+\r
+/*\r
+ * Checks that all the demo application tasks are still executing without error\r
+ * - as described at the top of the file.\r
+ */\r
+static portBASE_TYPE prvCheckOtherTasksAreStillRunning( void );\r
+\r
+/*\r
+ * The register test task as described at the top of this file.\r
+ */\r
+static void vRegisterTest( void *pvParameters );\r
+\r
+/*\r
+ * Perform any necessary hardware configuration.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/* Set to pdFAIL should an error be discovered in the register test tasks. */\r
+static unsigned portLONG ulRegisterTestStatus = pdPASS;\r
+const unsigned portLONG *pulStatusAddr = &ulRegisterTestStatus;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Create all the demo tasks - then start the scheduler.\r
+ */\r
+int main (void) \r
+{\r
+ /* When re-starting a debug session (rather than cold booting) we want\r
+ to ensure the installed interrupt handlers do not execute until after the\r
+ scheduler has been started. */\r
+ portDISABLE_INTERRUPTS();\r
+\r
+ prvSetupHardware();\r
+\r
+ /* Start the standard demo application tasks. */\r
+ vStartLEDFlashTasks( mainLED_TASK_PRIORITY );\r
+ vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainBAUD_RATE, mainCOM_TEST_LED );\r
+ vStartIntegerMathTasks( tskIDLE_PRIORITY );\r
+ vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
+ vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
+ vStartDynamicPriorityTasks();\r
+ vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
+ \r
+ /* Create two register check tasks - using a different parameter for each.\r
+ The parameter is used to generate the known values written to the registers. */\r
+ #if configUSE_PREEMPTION == 1\r
+ xTaskCreate( vRegisterTest, "Reg1", mainTINY_STACK, ( void * ) 10, tskIDLE_PRIORITY, NULL );\r
+ xTaskCreate( vRegisterTest, "Reg2", mainTINY_STACK, ( void * ) 20, tskIDLE_PRIORITY, NULL );\r
+ #endif\r
+\r
+ /* Create the 'check' task that is defined in this file. */\r
+ xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
+\r
+ /* Finally start the scheduler. */\r
+ vTaskStartScheduler();\r
+\r
+ /* Should not get here as the processor is now under control of the \r
+ scheduler! */\r
+\r
+ return 0;
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vErrorChecks( void *pvParameters )\r
+{\r
+portTickType xDelayPeriod = mainNO_ERROR_CHECK_PERIOD;\r
+\r
+ /* The parameters are not used. */\r
+ ( void ) pvParameters;\r
+\r
+ /* Cycle for ever, delaying then checking all the other tasks are still\r
+ operating without error. The delay period used will depend on whether\r
+ or not an error has been discovered in one of the demo tasks. */\r
+ for( ;; )\r
+ {\r
+ vTaskDelay( xDelayPeriod );\r
+ if( !prvCheckOtherTasksAreStillRunning() )\r
+ {\r
+ /* An error has been found. Shorten the delay period to make\r
+ the LED flash faster. */\r
+ xDelayPeriod = mainERROR_CHECK_PERIOD;\r
+ }\r
+\r
+ vParTestToggleLED( mainCHECK_TASK_LED );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portBASE_TYPE prvCheckOtherTasksAreStillRunning( void )\r
+{\r
+static portBASE_TYPE xAllTestsPass = pdTRUE;\r
+\r
+ /* Return pdFALSE if any demo application task set has encountered\r
+ an error. */\r
+\r
+ if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ xAllTestsPass = pdFALSE;\r
+ }\r
+\r
+ if( xAreComTestTasksStillRunning() != pdTRUE )\r
+ {\r
+ xAllTestsPass = pdFALSE;\r
+ }\r
+\r
+ if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ xAllTestsPass = pdFALSE;\r
+ }\r
+\r
+ if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ xAllTestsPass = pdFAIL;\r
+ }\r
+\r
+ if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )\r
+ {\r
+ xAllTestsPass = ( portLONG ) pdFAIL;\r
+ }\r
+\r
+ if( xArePollingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ xAllTestsPass = ( portLONG ) pdFAIL;\r
+ }\r
+\r
+ /* Mutual exclusion on this variable is not necessary as we only read it. */\r
+ if( ulRegisterTestStatus != pdPASS )\r
+ {\r
+ xAllTestsPass = pdFALSE;\r
+ }\r
+\r
+ return xAllTestsPass;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+ /* Ensure the interrupt controller is enabled in order that subsequent \r
+ code can successfully configure the peripherals. */\r
+ XIntc_mMasterEnable( XPAR_OPB_INTC_0_BASEADDR );\r
+\r
+ /* Initialise the GPIO used for the LED's. */\r
+ vParTestInitialise();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vRegisterTest( void *pvParameters )\r
+{\r
+ for( ;; )\r
+ {\r
+ /* Fill the registers with their register number plus the offset \r
+ (added) value. The added value is passed in as a parameter so\r
+ is contained in r5. */\r
+ asm volatile ( "addi r3, r5, 3 \n\t" \\r
+ "addi r4, r5, 4 \n\t" \\r
+ "addi r6, r5, 6 \n\t" \\r
+ "addi r7, r5, 7 \n\t" \\r
+ "addi r8, r5, 8 \n\t" \\r
+ "addi r9, r5, 9 \n\t" \\r
+ "addi r10, r5, 10 \n\t" \\r
+ "addi r11, r5, 11 \n\t" \\r
+ "addi r12, r5, 12 \n\t" \\r
+ "addi r16, r5, 16 \n\t" \\r
+ "addi r17, r5, 17 \n\t" \\r
+ "addi r18, r5, 18 \n\t" \\r
+ "addi r19, r5, 19 \n\t" \\r
+ "addi r20, r5, 20 \n\t" \\r
+ "addi r21, r5, 21 \n\t" \\r
+ "addi r22, r5, 22 \n\t" \\r
+ "addi r23, r5, 23 \n\t" \\r
+ "addi r24, r5, 24 \n\t" \\r
+ "addi r25, r5, 25 \n\t" \\r
+ "addi r26, r5, 26 \n\t" \\r
+ "addi r27, r5, 27 \n\t" \\r
+ "addi r28, r5, 28 \n\t" \\r
+ "addi r29, r5, 29 \n\t" \\r
+ "addi r30, r5, 30 \n\t" \\r
+ "addi r31, r5, 31 \n\t"\r
+ );\r
+\r
+ /* Now read back the register values to ensure they are as we expect. \r
+ This task will get preempted frequently so other tasks are likely to\r
+ have executed since the register values were written. */\r
+\r
+ /* r3 should contain r5 + 3. Subtract 3 to leave r3 equal to r5. */\r
+ asm volatile ( "addi r3, r3, -3 " );\r
+\r
+ /* Compare r3 and r5. If they are not equal then either r3 or r5\r
+ contains the wrong value and *pulStatusAddr is to pdFAIL. */\r
+ asm volatile ( "cmp r3, r3, r5 \n\t" \\r
+ "beqi r3, 12 \n\t" \\r
+ "lwi r3, r0, pulStatusAddr \n\t" \\r
+ "sw r0, r0, r3 \n\t" \r
+ );\r
+\r
+ /* Repeat for all the other registers. */\r
+ asm volatile ( "addi r4, r4, -4 \n\t" \\r
+ "cmp r4, r4, r5 \n\t" \\r
+ "beqi r4, 12 \n\t" \\r
+ "lwi r3, r0, pulStatusAddr \n\t" \\r
+ "sw r0, r0, r3 \n\t" \\r
+ "addi r6, r6, -6 \n\t" \\r
+ "cmp r6, r6, r5 \n\t" \\r
+ "beqi r6, 12 \n\t" \\r
+ "lwi r3, r0, pulStatusAddr \n\t" \\r
+ "sw r0, r0, r3 \n\t" \\r
+ "addi r7, r7, -7 \n\t" \\r
+ "cmp r7, r7, r5 \n\t" \\r
+ "beqi r7, 12 \n\t" \\r
+ "lwi r3, r0, pulStatusAddr \n\t" \\r
+ "sw r0, r0, r3 \n\t" \\r
+ "addi r8, r8, -8 \n\t" \\r
+ "cmp r8, r8, r5 \n\t" \\r
+ "beqi r8, 12 \n\t" \\r
+ "lwi r3, r0, pulStatusAddr \n\t" \\r
+ "sw r0, r0, r3 \n\t" \\r
+ "addi r9, r9, -9 \n\t" \\r
+ "cmp r9, r9, r5 \n\t" \\r
+ "beqi r9, 12 \n\t" \\r
+ "lwi r3, r0, pulStatusAddr \n\t" \\r
+ "sw r0, r0, r3 \n\t" \\r
+ "addi r10, r10, -10 \n\t" \\r
+ "cmp r10, r10, r5 \n\t" \\r
+ "beqi r10, 12 \n\t" \\r
+ "lwi r3, r0, pulStatusAddr \n\t" \\r
+ "sw r0, r0, r3 \n\t" \\r
+ "addi r11, r11, -11 \n\t" \\r
+ "cmp r11, r11, r5 \n\t" \\r
+ "beqi r11, 12 \n\t" \\r
+ "lwi r3, r0, pulStatusAddr \n\t" \\r
+ "sw r0, r0, r3 \n\t" \\r
+ "addi r12, r12, -12 \n\t" \\r
+ "cmp r12, r12, r5 \n\t" \\r
+ "beqi r12, 12 \n\t" \\r
+ "lwi r3, r0, pulStatusAddr \n\t" \\r
+ "sw r0, r0, r3 \n\t" \\r
+ "sw r0, r0, r3 \n\t" \\r
+ "addi r16, r16, -16 \n\t" \\r
+ "cmp r16, r16, r5 \n\t" \\r
+ "beqi r16, 12 \n\t" \\r
+ "lwi r3, r0, pulStatusAddr \n\t" \\r
+ "sw r0, r0, r3 \n\t" \\r
+ "addi r17, r17, -17 \n\t" \\r
+ "cmp r17, r17, r5 \n\t" \\r
+ "beqi r17, 12 \n\t" \\r
+ "lwi r3, r0, pulStatusAddr \n\t" \\r
+ "sw r0, r0, r3 \n\t" \\r
+ "addi r18, r18, -18 \n\t" \\r
+ "cmp r18, r18, r5 \n\t" \\r
+ "beqi r18, 12 \n\t" \\r
+ "lwi r3, r0, pulStatusAddr \n\t" \\r
+ "sw r0, r0, r3 \n\t" \\r
+ "addi r19, r19, -19 \n\t" \\r
+ "cmp r19, r19, r5 \n\t" \\r
+ "beqi r19, 12 \n\t" \\r
+ "lwi r3, r0, pulStatusAddr \n\t" \\r
+ "sw r0, r0, r3 \n\t" \\r
+ "addi r20, r20, -20 \n\t" \\r
+ "cmp r20, r20, r5 \n\t" \\r
+ "beqi r20, 12 \n\t" \\r
+ "lwi r3, r0, pulStatusAddr \n\t" \\r
+ "sw r0, r0, r3 \n\t" \\r
+ "addi r21, r21, -21 \n\t" \\r
+ "cmp r21, r21, r5 \n\t" \\r
+ "beqi r21, 12 \n\t" \\r
+ "lwi r3, r0, pulStatusAddr \n\t" \\r
+ "sw r0, r0, r3 \n\t" \\r
+ "addi r22, r22, -22 \n\t" \\r
+ "cmp r22, r22, r5 \n\t" \\r
+ "beqi r22, 12 \n\t" \\r
+ "lwi r3, r0, pulStatusAddr \n\t" \\r
+ "sw r0, r0, r3 \n\t" \\r
+ "addi r23, r23, -23 \n\t" \\r
+ "cmp r23, r23, r5 \n\t" \\r
+ "beqi r23, 12 \n\t" \\r
+ "lwi r3, r0, pulStatusAddr \n\t" \\r
+ "sw r0, r0, r3 \n\t" \\r
+ "addi r24, r24, -24 \n\t" \\r
+ "cmp r24, r24, r5 \n\t" \\r
+ "beqi r24, 12 \n\t" \\r
+ "lwi r3, r0, pulStatusAddr \n\t" \\r
+ "sw r0, r0, r3 \n\t" \\r
+ "addi r25, r25, -25 \n\t" \\r
+ "cmp r25, r25, r5 \n\t" \\r
+ "beqi r25, 12 \n\t" \\r
+ "lwi r3, r0, pulStatusAddr \n\t" \\r
+ "sw r0, r0, r3 \n\t" \\r
+ "addi r26, r26, -26 \n\t" \\r
+ "cmp r26, r26, r5 \n\t" \\r
+ "beqi r26, 12 \n\t" \\r
+ "lwi r3, r0, pulStatusAddr \n\t" \\r
+ "sw r0, r0, r3 \n\t" \\r
+ "addi r27, r27, -27 \n\t" \\r
+ "cmp r27, r27, r5 \n\t" \\r
+ "beqi r27, 12 \n\t" \\r
+ "lwi r3, r0, pulStatusAddr \n\t" \\r
+ "sw r0, r0, r3 \n\t" \\r
+ "addi r28, r28, -28 \n\t" \\r
+ "cmp r28, r28, r5 \n\t" \\r
+ "beqi r28, 12 \n\t" \\r
+ "lwi r3, r0, pulStatusAddr \n\t" \\r
+ "sw r0, r0, r3 \n\t" \\r
+ "addi r29, r29, -29 \n\t" \\r
+ "cmp r29, r29, r5 \n\t" \\r
+ "beqi r29, 12 \n\t" \\r
+ "lwi r3, r0, pulStatusAddr \n\t" \\r
+ "sw r0, r0, r3 \n\t" \\r
+ "addi r30, r30, -30 \n\t" \\r
+ "cmp r30, r30, r5 \n\t" \\r
+ "beqi r30, 12 \n\t" \\r
+ "lwi r3, r0, pulStatusAddr \n\t" \\r
+ "sw r0, r0, r3 \n\t" \\r
+ "addi r31, r31, -31 \n\t" \\r
+ "cmp r31, r31, r5 \n\t" \\r
+ "beqi r31, 12 \n\t" \\r
+ "lwi r3, r0, pulStatusAddr \n\t" \\r
+ "sw r0, r0, r3 \n\t"\r
+ );\r
+ }\r
+}\r
+\r
+\r
+\r
--- /dev/null
+-p\r
+xc4vfx12ff668-10\r
+-lang\r
+vhdl\r
+-st\r
+xst\r
+system.mhs\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+\r
+/* \r
+ BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART\r
+*/\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "queue.h"\r
+#include "task.h"\r
+\r
+/* Demo application includes. */\r
+#include "serial.h"\r
+\r
+/* Microblaze driver includes. */\r
+#include "xuartlite_l.h"\r
+#include "xintc_l.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Queues used to hold received characters, and characters waiting to be\r
+transmitted. */\r
+static xQueueHandle xRxedChars; \r
+static xQueueHandle xCharsForTx; \r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )\r
+{\r
+unsigned portLONG ulControlReg, ulMask;\r
+\r
+ /* NOTE: The baud rate used by this driver is determined by the hardware\r
+ parameterization of the UART Lite peripheral, and the baud value passed to\r
+ this function has no effect. */\r
+\r
+ /* Create the queues used to hold Rx and Tx characters. */\r
+ xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );\r
+ xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );\r
+\r
+ if( ( xRxedChars ) && ( xCharsForTx ) )\r
+ {\r
+ /* Disable the interrupt. */\r
+ XUartLite_mDisableIntr( XPAR_RS232_UART_BASEADDR );\r
+ \r
+ /* Flush the fifos. */\r
+ ulControlReg = XIo_In32( XPAR_RS232_UART_BASEADDR + XUL_STATUS_REG_OFFSET );\r
+ XIo_Out32( XPAR_RS232_UART_BASEADDR + XUL_CONTROL_REG_OFFSET, ulControlReg | XUL_CR_FIFO_TX_RESET | XUL_CR_FIFO_RX_RESET );\r
+\r
+ /* Enable the interrupt again. The interrupt controller has not yet been \r
+ initialised so there is no chance of receiving an interrupt until the \r
+ scheduler has been started. */\r
+ XUartLite_mEnableIntr( XPAR_RS232_UART_BASEADDR );\r
+\r
+ /* Enable the interrupt in the interrupt controller while maintaining \r
+ all the other bit settings. */\r
+ ulMask = XIntc_In32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ) );\r
+ ulMask |= XPAR_RS232_UART_INTERRUPT_MASK;\r
+ XIntc_Out32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ), ( ulMask ) );\r
+ XIntc_mAckIntr( XPAR_INTC_SINGLE_BASEADDR, 2 );\r
+ }\r
+ \r
+ return ( xComPortHandle ) 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )\r
+{\r
+ /* The port handle is not required as this driver only supports one UART. */\r
+ ( void ) pxPort;\r
+\r
+ /* Get the next character from the buffer. Return false if no characters\r
+ are available, or arrive before xBlockTime expires. */\r
+ if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )\r
+ {\r
+ return pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ return pdFALSE;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )\r
+{\r
+portBASE_TYPE xReturn = pdTRUE;\r
+\r
+ portENTER_CRITICAL();\r
+ {\r
+ /* If the UART FIFO is full we can block posting the new data on the\r
+ Tx queue. */\r
+ if( XUartLite_mIsTransmitFull( XPAR_RS232_UART_BASEADDR ) )\r
+ {\r
+ if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )\r
+ {\r
+ xReturn = pdFAIL;\r
+ }\r
+ }\r
+ /* Otherwise, if there is data already in the queue we should add the\r
+ new data to the back of the queue to ensure the sequencing is \r
+ maintained. */\r
+ else if( uxQueueMessagesWaiting( xCharsForTx ) )\r
+ {\r
+ if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )\r
+ {\r
+ xReturn = pdFAIL;\r
+ } \r
+ }\r
+ /* If the UART FIFO is not full and there is no data already in the\r
+ queue we can write directly to the FIFO without disrupting the \r
+ sequence. */\r
+ else\r
+ {\r
+ XIo_Out32( XPAR_RS232_UART_BASEADDR + XUL_TX_FIFO_OFFSET, cOutChar );\r
+ }\r
+ }\r
+ portEXIT_CRITICAL();\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSerialClose( xComPortHandle xPort )\r
+{\r
+ /* Not supported as not required by the demo application. */\r
+ ( void ) xPort;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSerialISR( void *pvBaseAddress )\r
+{\r
+unsigned portLONG ulISRStatus;\r
+portBASE_TYPE xTaskWokenByTx = pdFALSE, xTaskWokenByRx = pdFALSE;\r
+portCHAR cChar;\r
+\r
+ /* Determine the cause of the interrupt. */\r
+ ulISRStatus = XIo_In32( XPAR_RS232_UART_BASEADDR + XUL_STATUS_REG_OFFSET );\r
+\r
+ if( ( ulISRStatus & ( XUL_SR_RX_FIFO_FULL | XUL_SR_RX_FIFO_VALID_DATA ) ) != 0 )\r
+ {\r
+ /* A character is available - place it in the queue of received\r
+ characters. This might wake a task that was blocked waiting for \r
+ data. */\r
+ cChar = ( portCHAR )XIo_In32( XPAR_RS232_UART_BASEADDR + XUL_RX_FIFO_OFFSET );\r
+ xTaskWokenByRx = xQueueSendFromISR( xRxedChars, &cChar, xTaskWokenByRx );\r
+ }\r
+\r
+ if( ( ulISRStatus & XUL_SR_TX_FIFO_EMPTY ) != 0 )\r
+ {\r
+ /* There is space in the FIFO - if there are any characters queue for\r
+ transmission they can be send to the UART now. This might unblock a\r
+ task that was waiting for space to become available on the Tx queue. */\r
+ if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWokenByTx ) == pdTRUE )\r
+ {\r
+ XIo_Out32( XPAR_RS232_UART_BASEADDR + XUL_TX_FIFO_OFFSET, cChar );\r
+ }\r
+ }\r
+\r
+ /* If we woke any tasks we may require a context switch. */\r
+ if( xTaskWokenByTx || xTaskWokenByRx )\r
+ {\r
+ portYIELD_FROM_ISR();\r
+ }\r
+}\r
--- /dev/null
+\e\84æÄ®Òôtt¦Êè¬ÊäæÒÞÜ@Dn\b\dDvC\84æÄ®Òôtt¦Êè\84ÞÂäÈ@D°ÒØÒÜðD@D¬ÒäèÊð@h@\9a\98h`f@\8aìÂØêÂèÒÞÜ@ ØÂèÌÞäÚD@DbDv,\84æÄ®ÒôttªàÈÂèÊ\8c \8e\82@D\82¤\86\90\92¨\8a\86¨ª¤\8aD@DìÒäèÊðhDv,\84æÄ®ÒôttªàÈÂèÊ\8c \8e\82@D\88\8a¬\92\86\8a¾¦\92´\8aD@DðÆhìÌðbdDv%\84æÄ®ÒôttªàÈÂèÊ\8c \8e\82@D \82\86\96\82\8e\8aD@DÌÌllpDv&\84æÄ®ÒôttªàÈÂèÊ\8c \8e\82@D¦ \8a\8a\88\8e¤\82\88\8aD@DZb`Dv"\84æÄ®Òôtt\82ÈÈ äÞÆÊææÞä@DÚÒÆäÞÄØÂôÊDv=\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@DÚÒÆäÞÄØÂôÊD@D\84ª¦¾\8c¤\8a¢D@Db``\``````Dv8\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@DÚÒÆäÞÄØÂôÊD@D\86\82\86\90\8aD@D\9c\9e@\86\82\86\90\8aDvN\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@DÚÒÆäÞÄØÂôÊD@D\86\82\86\90\8a\98\92\9c\96@\86\9e\9a \9e\9c\8a\9c¨D@D\88\88¤¾¦\88¤\82\9a¾lh\9aðfdDv=\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@DÚÒÆäÞÄØÂôÊD@D\86\98\96¾\8c¤\8a¢D@Db``\``````DvJ\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@DÚÒÆäÞÄØÂôÊD@D\88\8a\84ª\8e¾\92\8cD@D\9eÜZ\86ÐÒà@\90®@\88ÊÄêÎ@\9aÞÈêØÊDv<\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@DÚÒÆäÞÄØÂôÊD@D\98\9a\84\84¤\82\9a@¦\92´\8aD@DljjflDv>\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@DÚÒÆäÞÄØÂôÊD@D ¤\9e\86¾\8c¤\8a¢D@Db``\``````Dv8\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@DÚÒÆäÞÄØÂôÊD@D¤¦¨¾ \9e\98\82¤\92¨²D@D`Dv2\84æÄ®Òôtt\82ÈÈ ÊäÒàÐÊäÂØ@D¤¦dfd¾ªÂäèD@DÞàľêÂäèØÒèÊDv9\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@D¤¦dfd¾ªÂäèD@D\86¾\84\82ª\88¤\82¨\8aD@Drl``Dv7\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@D¤¦dfd¾ªÂäèD@D\86¾\88\82¨\82¾\84\92¨¦D@DpDv8\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@D¤¦dfd¾ªÂäèD@D\86¾\9e\88\88¾ \82¤\92¨²D@D`Dv8\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@D¤¦dfd¾ªÂäèD@D\86¾ª¦\8a¾ \82¤\92¨²D@D`Dv<\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@D¤¦dfd¾ªÂäèD@D\92\9e¨² \8aD@D°\92\98¾ª\82¤¨¾¬bDv<\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@D¤¦dfd¾ªÂäèD@Dª¦\8a¾\92\9c¨\8a¤¤ª ¨D@D¨¤ª\8aDv-\84æÄ®Òôtt\82ÈÈ ÊäÒàÐÊäÂØ@D\98\8a\88æ¾h\84ÒèD@DÞàľÎàÒÞDv;\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@D\98\8a\88æ¾h\84ÒèD@D\92\9e¨² \8aD@D°\92\98¾\8e \92\9e¾¬bDv2\84æÄ®Òôtt\82ÈÈ ÊäÒàÐÊäÂØ@D\98\8a\88æ¾ ÞæÒèÒÞÜæD@DÞàľÎàÒÞDv@\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@D\98\8a\88æ¾ ÞæÒèÒÞÜæD@D\92\9e¨² \8aD@D°\92\98¾\8e \92\9e¾¬bDv0\84æÄ®Òôtt\82ÈÈ ÊäÒàÐÊäÂØ@DÞàľèÒÚÊä¾bD@DÞàľèÒÚÊäDv;\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@DÞàľèÒÚÊä¾bD@D\86¾\86\9eª\9c¨¾®\92\88¨\90D@DfdDv=\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@DÞàľèÒÚÊä¾bD@D\86¾\9e\9c\8a¾¨\92\9a\8a¤¾\9e\9c\98²D@DbDv=\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@DÞàľèÒÚÊä¾bD@Dª¦\8a¾\92\9c¨\8a¤¤ª ¨D@D¨¤ª\8aDv/\84æÄ®ÒôttªàÈÂèʦ®@D¦®¾\8e\8a\9c\8a¤\82¨\8a¾\9a\8a\9a¨\8a¦¨D@D\8c\82\98¦\8aDv1\84æÄ®ÒôttªàÈÂèʦ®@D¦®¾\8e\8a\9c\8a¤\82¨\8a¾ \8a¤\92 \90¨\8a¦¨D@D¨¤ª\8aDv#\84æÄ®ÒôttªàÈÂèʦ®@D¦®¾¦¨\88\92\9cD@D\9cÞÜÊDv$\84æÄ®ÒôttªàÈÂèʦ®@D¦®¾¦¨\88\9eª¨D@D\9cÞÜÊDvA\84æÄ®ÒôttªàÈÂèʦ®@D¦®¾\88\82¨\82¾\92\9c¦D@DÈØÚľÆÜèØäD@D¨Êæè\82àྠÊäÒàÐÊäÂØDvA\84æÄ®ÒôttªàÈÂèʦ®@D¦®¾\88\82¨\82¾ \82¤D@D\86¾\84\82¦\8a\82\88\88¤D@D¨Êæè\82àྠÊäÒàÐÊäÂØDvD\84æÄ®ÒôttªàÈÂèʦ®@D¦®¾ ¤\9e\8e¤\82\9a¾\92\9c¦D@DÒØÚľÆÜèØäD@D¨Êæè\82àྠÊäÒàÐÊäÂØDvD\84æÄ®ÒôttªàÈÂèʦ®@D¦®¾ ¤\9e\8e¤\82\9a¾ \82¤D@D\86¾\84\82¦\8a\82\88\88¤D@D¨Êæè\82àྠÊäÒàÐÊäÂØDvB\84æÄ®ÒôttªàÈÂèʦ®@D¦®¾¦¨\82\86\96¾\92\9c¦D@DÈØÚľÆÜèØäD@D¨Êæè\82àྠÊäÒàÐÊäÂØDvB\84æÄ®ÒôttªàÈÂèʦ®@D¦®¾¦¨\82\86\96¾ \82¤D@D\86¾\84\82¦\8a\82\88\88¤D@D¨Êæè\82àྠÊäÒàÐÊäÂØDv
\ No newline at end of file
--- /dev/null
+#################################################################\r
+# Makefile generated by Xilinx Platform Studio \r
+# Project:E:\Dev\FreeRTOS\Demo\MicroBlaze\system.xmp\r
+#################################################################\r
+\r
+# Name of the Microprocessor system\r
+# The hardware specification of the system is in file :\r
+# E:\Dev\FreeRTOS\Demo\MicroBlaze\system.mhs\r
+# The software specification of the system is in file :\r
+# E:\Dev\FreeRTOS\Demo\MicroBlaze\system.mss\r
+\r
+include system_incl.make\r
+\r
+\r
+#################################################################\r
+# EXTERNAL TARGETS\r
+#################################################################\r
+all:\r
+ @echo "Makefile to build a Microprocessor system :"\r
+ @echo "Run make with any of the following targets"\r
+ @echo " "\r
+ @echo " netlist : Generates the netlist for the given MHS "\r
+ @echo " bits : Runs Implementation tools to generate the bitstream"\r
+ @echo " exporttopn:Export to ProjNav"\r
+ @echo " "\r
+ @echo " libs : Configures the sw libraries for this system"\r
+ @echo " program : Compiles the program sources for all the processor instances"\r
+ @echo " "\r
+ @echo " init_bram: Initializes bitstream with BRAM data"\r
+ @echo " ace : Generate ace file from bitstream and elf"\r
+ @echo " download : Downloads the bitstream onto the board"\r
+ @echo " "\r
+ @echo " sim : Generates HDL simulation models and runs simulator for chosen simulation mode"\r
+ @echo " simmodel : Generates HDL simulation models for chosen simulation mode"\r
+ @echo " behavioral_model:Generates behavioral HDL models with BRAM initialization"\r
+ @echo " structural_model:Generates structural simulation HDL models with BRAM initialization"\r
+ @echo " timing_model : Generates timing simulation HDL models with BRAM initialization"\r
+ @echo " vp : Generates virtual platform model"\r
+ @echo " "\r
+ @echo " netlistclean: Deletes netlist"\r
+ @echo " bitsclean: Deletes bit, ncd, bmm files"\r
+ @echo " hwclean : Deletes implementation dir"\r
+ @echo " libsclean: Deletes sw libraries"\r
+ @echo " programclean: Deletes compiled ELF files"\r
+ @echo " swclean : Deletes sw libraries and ELF files"\r
+ @echo " simclean : Deletes simulation dir"\r
+ @echo " vpclean : Deletes virtualplatform dir"\r
+ @echo " clean : Deletes all generated files/directories"\r
+ @echo " "\r
+ @echo " make <target> : (Default)"\r
+ @echo " Creates a Microprocessor system using default initializations"\r
+ @echo " specified for each processor in MSS file"\r
+\r
+\r
+bits: $(SYSTEM_BIT)\r
+\r
+ace: $(SYSTEM_ACE)\r
+\r
+netlist: $(POSTSYN_NETLIST)\r
+\r
+libs: $(LIBRARIES)\r
+\r
+program: $(ALL_USER_ELF_FILES)\r
+\r
+download: $(DOWNLOAD_BIT) dummy\r
+ @echo "*********************************************"\r
+ @echo "Downloading Bitstream onto the target board"\r
+ @echo "*********************************************"\r
+ impact -batch etc/download.cmd\r
+\r
+init_bram: $(DOWNLOAD_BIT)\r
+\r
+sim: $(DEFAULT_SIM_SCRIPT)\r
+ cd simulation/behavioral; \\r
+ $(SIM_CMD) &\r
+\r
+simmodel: $(DEFAULT_SIM_SCRIPT)\r
+\r
+behavioral_model: $(BEHAVIORAL_SIM_SCRIPT)\r
+\r
+structural_model: $(STRUCTURAL_SIM_SCRIPT)\r
+\r
+timing_model: $(TIMING_SIM_SCRIPT)\r
+\r
+vp: $(VPEXEC)\r
+\r
+clean: hwclean libsclean programclean simclean vpclean\r
+ rm -f _impact.cmd\r
+\r
+hwclean: netlistclean bitsclean\r
+ rm -rf implementation synthesis xst hdl\r
+ rm -rf xst.srp $(SYSTEM).srp\r
+\r
+netlistclean:\r
+ rm -f $(POSTSYN_NETLIST)\r
+ rm -f $(BMM_FILE)\r
+\r
+bitsclean:\r
+ rm -f $(SYSTEM_BIT)\r
+ rm -f implementation/$(SYSTEM).ncd\r
+ rm -f implementation/$(SYSTEM)_bd.bmm \r
+\r
+bitsclean:\r
+\r
+simclean: \r
+ rm -rf simulation/behavioral\r
+\r
+swclean: libsclean programclean\r
+ @echo ""\r
+\r
+libsclean: $(LIBSCLEAN_TARGETS)\r
+\r
+programclean: $(PROGRAMCLEAN_TARGETS)\r
+\r
+vpclean:\r
+ rm -rf virtualplatform\r
+\r
+#################################################################\r
+# SOFTWARE PLATFORM FLOW\r
+#################################################################\r
+\r
+\r
+$(LIBRARIES): $(MHSFILE) $(MSSFILE) __xps/libgen.opt\r
+ @echo "*********************************************"\r
+ @echo "Creating software libraries..."\r
+ @echo "*********************************************"\r
+ libgen $(LIBGEN_OPTIONS) $(MSSFILE)\r
+\r
+\r
+microblaze_0_libsclean:\r
+ rm -rf microblaze_0/lib/\r
+\r
+$(MICROBLAZE_0_XMDSTUB): $(LIBRARIES)\r
+\r
+#################################################################\r
+# SOFTWARE APPLICATION RTOSDEMO\r
+#################################################################\r
+\r
+RTOSDemo_program: $(RTOSDEMO_OUTPUT) \r
+\r
+$(RTOSDEMO_OUTPUT) : $(RTOSDEMO_SOURCES) $(RTOSDEMO_HEADERS) $(RTOSDEMO_LINKER_SCRIPT) \\r
+ $(LIBRARIES) __xps/rtosdemo_compiler.opt\r
+ @mkdir -p $(RTOSDEMO_OUTPUT_DIR) \r
+ $(RTOSDEMO_CC) $(RTOSDEMO_CC_OPT) $(RTOSDEMO_SOURCES) -o $(RTOSDEMO_OUTPUT) \\r
+ $(RTOSDEMO_OTHER_CC_FLAGS) $(RTOSDEMO_INCLUDES) $(RTOSDEMO_LIBPATH) \\r
+ -xl-mode-$(RTOSDEMO_MODE) \\r
+ $(RTOSDEMO_CFLAGS) $(RTOSDEMO_LFLAGS) \r
+ $(RTOSDEMO_CC_SIZE) $(RTOSDEMO_OUTPUT) \r
+\r
+RTOSDemo_programclean:\r
+ rm -f $(RTOSDEMO_OUTPUT) \r
+\r
+#################################################################\r
+# BOOTLOOP ELF FILES\r
+#################################################################\r
+\r
+\r
+\r
+$(MICROBLAZE_0_BOOTLOOP): $(MICROBLAZE_BOOTLOOP)\r
+ @mkdir -p $(BOOTLOOP_DIR)\r
+ cp -f $(MICROBLAZE_BOOTLOOP) $(MICROBLAZE_0_BOOTLOOP)\r
+\r
+#################################################################\r
+# HARDWARE IMPLEMENTATION FLOW\r
+#################################################################\r
+\r
+\r
+$(BMM_FILE) \\r
+$(WRAPPER_NGC_FILES): $(MHSFILE) __xps/platgen.opt \\r
+ $(CORE_STATE_DEVELOPMENT_FILES)\r
+ @echo "****************************************************"\r
+ @echo "Creating system netlist for hardware specification.."\r
+ @echo "****************************************************"\r
+ platgen $(PLATGEN_OPTIONS) -st xst $(MHSFILE)\r
+\r
+$(POSTSYN_NETLIST): $(WRAPPER_NGC_FILES)\r
+ @echo "Running synthesis..."\r
+ bash -c "cd synthesis; ./synthesis.sh; cd .."\r
+\r
+$(SYSTEM_BIT): $(BMM_FILE) $(POSTSYN_NETLIST) __xps/xpsxflow.opt \\r
+ $(UCF_FILE) $(BITGEN_UT_FILE) $(FASTRUNTIME_OPT_FILE)\r
+ @echo "Copying Xilinx Implementation tool scripts.."\r
+ @cp -f $(BITGEN_UT_FILE) implementation/bitgen.ut\r
+ @cp -f $(FASTRUNTIME_OPT_FILE) implementation/fast_runtime.opt\r
+ @cp -f $(UCF_FILE) implementation/$(SYSTEM).ucf\r
+ @echo "*********************************************"\r
+ @echo "Running Xilinx Implementation tools.."\r
+ @echo "*********************************************"\r
+ xflow -wd implementation -p $(DEVICE) -implement fast_runtime.opt $(SYSTEM).ngc\r
+ cd implementation; bitgen -w -f bitgen.ut $(SYSTEM)\r
+\r
+exporttopn: \r
+ @echo "You have chosen XPS for implementation tool flow."\r
+ @echo "Please select ProjNav as your implementation flow in Project Options."\r
+ @echo "In batch mode, use commad xset pnproj <isefile>."\r
+\r
+$(DOWNLOAD_BIT): $(SYSTEM_BIT) $(BRAMINIT_ELF_FILES) __xps/bitinit.opt\r
+ @cp -f implementation/$(SYSTEM)_bd.bmm .\r
+ @echo "*********************************************"\r
+ @echo "Initializing BRAM contents of the bitstream"\r
+ @echo "*********************************************"\r
+ bitinit $(MHSFILE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_FILE_ARGS) \\r
+ -bt $(SYSTEM_BIT) -o $(DOWNLOAD_BIT)\r
+ @rm -f $(SYSTEM)_bd.bmm\r
+\r
+$(SYSTEM_ACE): $(DOWNLOAD_BIT) $(RTOSDEMO_OUTPUT) \r
+ @echo "*********************************************"\r
+ @echo "Creating system ace file"\r
+ @echo "*********************************************"\r
+ xmd -tcl genace.tcl -jprog -hw $(DOWNLOAD_BIT) -elf $(RTOSDEMO_OUTPUT) -ace $(SYSTEM_ACE)\r
+\r
+#################################################################\r
+# SIMULATION FLOW\r
+#################################################################\r
+\r
+\r
+################## BEHAVIORAL SIMULATION ##################\r
+\r
+$(BEHAVIORAL_SIM_SCRIPT): $(MHSFILE) __xps/simgen.opt \\r
+ $(BRAMINIT_ELF_FILES)\r
+ @echo "*********************************************"\r
+ @echo "Creating behavioral simulation models..."\r
+ @echo "*********************************************"\r
+ simgen $(SIMGEN_OPTIONS) -m behavioral $(MHSFILE)\r
+\r
+################## STRUCTURAL SIMULATION ##################\r
+\r
+$(STRUCTURAL_SIM_SCRIPT): $(WRAPPER_NGC_FILES) __xps/simgen.opt \\r
+ $(BRAMINIT_ELF_FILES)\r
+ @echo "*********************************************"\r
+ @echo "Creating structural simulation models..."\r
+ @echo "*********************************************"\r
+ simgen $(SIMGEN_OPTIONS) -sd implementation -m structural $(MHSFILE)\r
+\r
+\r
+################## TIMING SIMULATION ##################\r
+\r
+$(TIMING_SIM_SCRIPT): $(SYSTEM_BIT) __xps/simgen.opt \\r
+ $(BRAMINIT_ELF_FILES)\r
+ @echo "*********************************************"\r
+ @echo "Creating timing simulation models..."\r
+ @echo "*********************************************"\r
+ simgen $(SIMGEN_OPTIONS) -sd implementation -m timing $(MHSFILE)\r
+\r
+#################################################################\r
+# VIRTUAL PLATFORM FLOW\r
+#################################################################\r
+\r
+\r
+$(VPEXEC): $(MHSFILE) __xps/vpgen.opt\r
+ @echo "****************************************************"\r
+ @echo "Creating virtual platform for hardware specification.."\r
+ @echo "****************************************************"\r
+ vpgen $(VPGEN_OPTIONS) $(MHSFILE)\r
+\r
+dummy:\r
+ @echo ""\r
+\r
--- /dev/null
+# ##############################################################################\r
+# Created by Base System Builder Wizard for Xilinx EDK 7.1.2 Build EDK_H.12.5.1\r
+# Sun Nov 13 16:46:19 2005\r
+# Target Board: Xilinx Virtex 4 ML403 Evaluation Platform Rev 1\r
+# Family: virtex4\r
+# Device: xc4vfx12\r
+# Package: ff668\r
+# Speed Grade: -10\r
+# Processor: Microblaze\r
+# System clock frequency: 100.000000 MHz\r
+# Debug interface: On-Chip HW Debug Module\r
+# On Chip Memory : 64 KB\r
+# ##############################################################################\r
+\r
+\r
+ PARAMETER VERSION = 2.1.0\r
+\r
+\r
+ PORT fpga_0_RS232_Uart_RX_pin = fpga_0_RS232_Uart_RX, DIR = INPUT\r
+ PORT fpga_0_RS232_Uart_TX_pin = fpga_0_RS232_Uart_TX, DIR = OUTPUT\r
+ PORT fpga_0_LEDs_4Bit_GPIO_IO_pin = fpga_0_LEDs_4Bit_GPIO_IO, DIR = INOUT, VEC = [0:3]\r
+ PORT fpga_0_LEDs_Positions_GPIO_IO_pin = fpga_0_LEDs_Positions_GPIO_IO, DIR = INOUT, VEC = [0:4]\r
+ PORT sys_clk_pin = dcm_clk_s, DIR = INPUT, SIGIS = DCMCLK\r
+ PORT sys_rst_pin = sys_rst_s, DIR = INPUT\r
+\r
+\r
+BEGIN microblaze\r
+ PARAMETER INSTANCE = microblaze_0\r
+ PARAMETER HW_VER = 4.00.a\r
+ PARAMETER C_DEBUG_ENABLED = 1\r
+ PARAMETER C_NUMBER_OF_PC_BRK = 2\r
+ PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1\r
+ PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1\r
+ BUS_INTERFACE DLMB = dlmb\r
+ BUS_INTERFACE ILMB = ilmb\r
+ BUS_INTERFACE DOPB = mb_opb\r
+ BUS_INTERFACE IOPB = mb_opb\r
+ PORT CLK = sys_clk_s\r
+ PORT DBG_CAPTURE = DBG_CAPTURE_s\r
+ PORT DBG_CLK = DBG_CLK_s\r
+ PORT DBG_REG_EN = DBG_REG_EN_s\r
+ PORT DBG_TDI = DBG_TDI_s\r
+ PORT DBG_TDO = DBG_TDO_s\r
+ PORT DBG_UPDATE = DBG_UPDATE_s\r
+ PORT Interrupt = Interrupt\r
+END\r
+\r
+BEGIN opb_v20\r
+ PARAMETER INSTANCE = mb_opb\r
+ PARAMETER HW_VER = 1.10.c\r
+ PARAMETER C_EXT_RESET_HIGH = 0\r
+ PORT SYS_Rst = sys_rst_s\r
+ PORT OPB_Clk = sys_clk_s\r
+END\r
+\r
+BEGIN opb_mdm\r
+ PARAMETER INSTANCE = debug_module\r
+ PARAMETER HW_VER = 2.00.a\r
+ PARAMETER C_MB_DBG_PORTS = 1\r
+ PARAMETER C_USE_UART = 1\r
+ PARAMETER C_UART_WIDTH = 8\r
+ PARAMETER C_BASEADDR = 0x41400000\r
+ PARAMETER C_HIGHADDR = 0x4140ffff\r
+ BUS_INTERFACE SOPB = mb_opb\r
+ PORT OPB_Clk = sys_clk_s\r
+ PORT DBG_CAPTURE_0 = DBG_CAPTURE_s\r
+ PORT DBG_CLK_0 = DBG_CLK_s\r
+ PORT DBG_REG_EN_0 = DBG_REG_EN_s\r
+ PORT DBG_TDI_0 = DBG_TDI_s\r
+ PORT DBG_TDO_0 = DBG_TDO_s\r
+ PORT DBG_UPDATE_0 = DBG_UPDATE_s\r
+END\r
+\r
+BEGIN lmb_v10\r
+ PARAMETER INSTANCE = ilmb\r
+ PARAMETER HW_VER = 1.00.a\r
+ PARAMETER C_EXT_RESET_HIGH = 0\r
+ PORT SYS_Rst = sys_rst_s\r
+ PORT LMB_Clk = sys_clk_s\r
+END\r
+\r
+BEGIN lmb_v10\r
+ PARAMETER INSTANCE = dlmb\r
+ PARAMETER HW_VER = 1.00.a\r
+ PARAMETER C_EXT_RESET_HIGH = 0\r
+ PORT SYS_Rst = sys_rst_s\r
+ PORT LMB_Clk = sys_clk_s\r
+END\r
+\r
+BEGIN lmb_bram_if_cntlr\r
+ PARAMETER INSTANCE = dlmb_cntlr\r
+ PARAMETER HW_VER = 1.00.b\r
+ PARAMETER C_BASEADDR = 0x00000000\r
+ PARAMETER C_HIGHADDR = 0x0000ffff\r
+ BUS_INTERFACE SLMB = dlmb\r
+ BUS_INTERFACE BRAM_PORT = dlmb_port\r
+END\r
+\r
+BEGIN lmb_bram_if_cntlr\r
+ PARAMETER INSTANCE = ilmb_cntlr\r
+ PARAMETER HW_VER = 1.00.b\r
+ PARAMETER C_BASEADDR = 0x00000000\r
+ PARAMETER C_HIGHADDR = 0x0000ffff\r
+ BUS_INTERFACE SLMB = ilmb\r
+ BUS_INTERFACE BRAM_PORT = ilmb_port\r
+END\r
+\r
+BEGIN bram_block\r
+ PARAMETER INSTANCE = lmb_bram\r
+ PARAMETER HW_VER = 1.00.a\r
+ BUS_INTERFACE PORTA = ilmb_port\r
+ BUS_INTERFACE PORTB = dlmb_port\r
+END\r
+\r
+BEGIN opb_uartlite\r
+ PARAMETER INSTANCE = RS232_Uart\r
+ PARAMETER HW_VER = 1.00.b\r
+ PARAMETER C_BAUDRATE = 9600\r
+ PARAMETER C_DATA_BITS = 8\r
+ PARAMETER C_ODD_PARITY = 0\r
+ PARAMETER C_USE_PARITY = 0\r
+ PARAMETER C_CLK_FREQ = 100000000\r
+ PARAMETER C_BASEADDR = 0x40600000\r
+ PARAMETER C_HIGHADDR = 0x4060ffff\r
+ BUS_INTERFACE SOPB = mb_opb\r
+ PORT OPB_Clk = sys_clk_s\r
+ PORT Interrupt = RS232_Uart_Interrupt\r
+ PORT RX = fpga_0_RS232_Uart_RX\r
+ PORT TX = fpga_0_RS232_Uart_TX\r
+END\r
+\r
+BEGIN opb_gpio\r
+ PARAMETER INSTANCE = LEDs_4Bit\r
+ PARAMETER HW_VER = 3.01.b\r
+ PARAMETER C_GPIO_WIDTH = 4\r
+ PARAMETER C_IS_DUAL = 0\r
+ PARAMETER C_IS_BIDIR = 1\r
+ PARAMETER C_ALL_INPUTS = 0\r
+ PARAMETER C_BASEADDR = 0x40020000\r
+ PARAMETER C_HIGHADDR = 0x4002ffff\r
+ BUS_INTERFACE SOPB = mb_opb\r
+ PORT OPB_Clk = sys_clk_s\r
+ PORT GPIO_IO = fpga_0_LEDs_4Bit_GPIO_IO\r
+END\r
+\r
+BEGIN opb_gpio\r
+ PARAMETER INSTANCE = LEDs_Positions\r
+ PARAMETER HW_VER = 3.01.b\r
+ PARAMETER C_GPIO_WIDTH = 5\r
+ PARAMETER C_IS_DUAL = 0\r
+ PARAMETER C_IS_BIDIR = 1\r
+ PARAMETER C_ALL_INPUTS = 0\r
+ PARAMETER C_BASEADDR = 0x40000000\r
+ PARAMETER C_HIGHADDR = 0x4000ffff\r
+ BUS_INTERFACE SOPB = mb_opb\r
+ PORT OPB_Clk = sys_clk_s\r
+ PORT GPIO_IO = fpga_0_LEDs_Positions_GPIO_IO\r
+END\r
+\r
+BEGIN opb_timer\r
+ PARAMETER INSTANCE = opb_timer_1\r
+ PARAMETER HW_VER = 1.00.b\r
+ PARAMETER C_COUNT_WIDTH = 32\r
+ PARAMETER C_ONE_TIMER_ONLY = 1\r
+ PARAMETER C_BASEADDR = 0x41c00000\r
+ PARAMETER C_HIGHADDR = 0x41c0ffff\r
+ BUS_INTERFACE SOPB = mb_opb\r
+ PORT OPB_Clk = sys_clk_s\r
+ PORT Interrupt = opb_timer_1_Interrupt\r
+END\r
+\r
+BEGIN opb_intc\r
+ PARAMETER INSTANCE = opb_intc_0\r
+ PARAMETER HW_VER = 1.00.c\r
+ PARAMETER C_BASEADDR = 0x41200000\r
+ PARAMETER C_HIGHADDR = 0x4120ffff\r
+ PARAMETER C_HAS_IPR = 0\r
+ BUS_INTERFACE SOPB = mb_opb\r
+ PORT Irq = Interrupt\r
+ PORT Intr = RS232_Uart_Interrupt & opb_timer_1_Interrupt\r
+END\r
+\r
+BEGIN dcm_module\r
+ PARAMETER INSTANCE = dcm_0\r
+ PARAMETER HW_VER = 1.00.a\r
+ PARAMETER C_CLK0_BUF = TRUE\r
+ PARAMETER C_CLKIN_PERIOD = 10.000000\r
+ PARAMETER C_CLK_FEEDBACK = 1X\r
+ PARAMETER C_EXT_RESET_HIGH = 1\r
+ PORT CLKIN = dcm_clk_s\r
+ PORT CLK0 = sys_clk_s\r
+ PORT CLKFB = sys_clk_s\r
+ PORT RST = net_gnd\r
+ PORT LOCKED = dcm_0_lock\r
+END\r
+\r
--- /dev/null
+\r
+ PARAMETER VERSION = 2.2.0\r
+\r
+\r
+BEGIN OS\r
+ PARAMETER OS_NAME = standalone\r
+ PARAMETER OS_VER = 1.00.a\r
+ PARAMETER PROC_INSTANCE = microblaze_0\r
+END\r
+\r
+\r
+BEGIN PROCESSOR\r
+ PARAMETER DRIVER_NAME = cpu\r
+ PARAMETER DRIVER_VER = 1.00.a\r
+ PARAMETER HW_INSTANCE = microblaze_0\r
+ PARAMETER COMPILER = mb-gcc\r
+ PARAMETER ARCHIVER = mb-ar\r
+ PARAMETER XMDSTUB_PERIPHERAL = debug_module\r
+END\r
+\r
+\r
+BEGIN DRIVER\r
+ PARAMETER DRIVER_NAME = opbarb\r
+ PARAMETER DRIVER_VER = 1.02.a\r
+ PARAMETER HW_INSTANCE = mb_opb\r
+END\r
+\r
+BEGIN DRIVER\r
+ PARAMETER DRIVER_NAME = uartlite\r
+ PARAMETER DRIVER_VER = 1.00.b\r
+ PARAMETER HW_INSTANCE = debug_module\r
+END\r
+\r
+BEGIN DRIVER\r
+ PARAMETER DRIVER_NAME = bram\r
+ PARAMETER DRIVER_VER = 1.00.a\r
+ PARAMETER HW_INSTANCE = dlmb_cntlr\r
+END\r
+\r
+BEGIN DRIVER\r
+ PARAMETER DRIVER_NAME = bram\r
+ PARAMETER DRIVER_VER = 1.00.a\r
+ PARAMETER HW_INSTANCE = ilmb_cntlr\r
+END\r
+\r
+BEGIN DRIVER\r
+ PARAMETER DRIVER_NAME = uartlite\r
+ PARAMETER DRIVER_VER = 1.00.b\r
+ PARAMETER HW_INSTANCE = RS232_Uart\r
+ PARAMETER int_handler = vSerialISR, int_port = Interrupt\r
+END\r
+\r
+BEGIN DRIVER\r
+ PARAMETER DRIVER_NAME = gpio\r
+ PARAMETER DRIVER_VER = 2.00.a\r
+ PARAMETER HW_INSTANCE = LEDs_4Bit\r
+END\r
+\r
+BEGIN DRIVER\r
+ PARAMETER DRIVER_NAME = gpio\r
+ PARAMETER DRIVER_VER = 2.00.a\r
+ PARAMETER HW_INSTANCE = LEDs_Positions\r
+END\r
+\r
+BEGIN DRIVER\r
+ PARAMETER DRIVER_NAME = tmrctr\r
+ PARAMETER DRIVER_VER = 1.00.b\r
+ PARAMETER HW_INSTANCE = opb_timer_1\r
+ PARAMETER int_handler = vTickISR, int_port = Interrupt\r
+END\r
+\r
+BEGIN DRIVER\r
+ PARAMETER DRIVER_NAME = intc\r
+ PARAMETER DRIVER_VER = 1.00.c\r
+ PARAMETER HW_INSTANCE = opb_intc_0\r
+END\r
+\r
+BEGIN DRIVER\r
+ PARAMETER DRIVER_NAME = generic\r
+ PARAMETER DRIVER_VER = 1.00.a\r
+ PARAMETER HW_INSTANCE = dcm_0\r
+END\r
+\r
+\r
--- /dev/null
+#Please do not modify this file by hand\r
+XmpVersion: 7.1\r
+IntStyle: default\r
+MHS File: system.mhs\r
+MSS File: system.mss\r
+NPL File: projnav/system.ise\r
+Architecture: virtex4\r
+Device: xc4vfx12\r
+Package: ff668\r
+SpeedGrade: -10\r
+UseProjNav: 0\r
+AddToNPL: 0\r
+PNImportBitFile: \r
+PNImportBmmFile: \r
+UserCmd1: \r
+UserCmd1Type: 0\r
+UserCmd2: \r
+UserCmd2Type: 0\r
+SynProj: xst\r
+ReloadPbde: 0\r
+MainMhsEditor: 0\r
+InsertNoPads: 0\r
+HdlLang: VHDL\r
+Simulator: mti\r
+SimModel: BEHAVIORAL\r
+SimXLib: \r
+SimEdkLib: \r
+MixLangSim: 1\r
+UcfFile: data/system.ucf\r
+Processor: microblaze_0\r
+BootLoop: 0\r
+XmdStub: 0\r
+SwProj: RTOSDemo\r
+Processor: microblaze_0\r
+Executable: RTOSDemo/executable.elf\r
+Source: main.c\r
+Source: ParTest/ParTest.c\r
+Source: ../../Source/tasks.c\r
+Source: ../../Source/queue.c\r
+Source: ../../Source/list.c\r
+Source: ../../Source/portable/MemMang/heap_1.c\r
+Source: ../../Source/portable/GCC/MicroBlaze/port.c\r
+Source: ../../Source/portable/GCC/MicroBlaze/portasm.s\r
+Source: ../Common/Minimal/flash.c\r
+Source: serial/serial.c\r
+Source: ../Common/Minimal/comtest.c\r
+Source: ../Common/Minimal/integer.c\r
+Source: ../Common/Minimal/semtest.c\r
+Source: ../Common/Minimal/dynamic.c\r
+Source: ../Common/Minimal/PollQ.c\r
+Source: ../Common/Minimal/BlockQ.c\r
+Header: FreeRTOSConfig.h\r
+DefaultInit: EXECUTABLE\r
+InitBram: 1\r
+Active: 1\r
+CompilerOptLevel: 4\r
+GlobPtrOpt: 0\r
+DebugSym: 1\r
+SearchIncl: . ../Common/include ../../Source/include ../../Source/portable/GCC/MicroBlaze\r
+AsmOpt: \r
+LinkOpt: -Map=rtosdemo.map\r
+ProgStart: \r
+StackSize: \r
+HeapSize: \r
+LinkerScript: \r
+ProgCCFlags: -D MICROBLAZE_GCC -Wall\r
--- /dev/null
+#################################################################\r
+# Makefile generated by Xilinx Platform Studio \r
+# Project:E:\Dev\FreeRTOS\Demo\MicroBlaze\system.xmp\r
+#################################################################\r
+\r
+XILINX_EDK_DIR = C:/devtools/xilinx/EDK\r
+\r
+SYSTEM = system\r
+\r
+MHSFILE = system.mhs\r
+\r
+MSSFILE = system.mss\r
+\r
+FPGA_ARCH = virtex4\r
+\r
+DEVICE = xc4vfx12ff668-10\r
+\r
+LANGUAGE = vhdl\r
+\r
+SEARCHPATHOPT = \r
+\r
+SUBMODULE_OPT = \r
+\r
+PLATGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(SUBMODULE_OPT)\r
+\r
+LIBGEN_OPTIONS = -mhs $(MHSFILE) -p $(DEVICE) $(SEARCHPATHOPT) \\r
+ $(MICROBLAZE_0_LIBG_OPT)\r
+\r
+VPGEN_OPTIONS = -p $(DEVICE) $(SEARCHPATHOPT)\r
+\r
+RTOSDEMO_OUTPUT_DIR = RTOSDemo\r
+RTOSDEMO_OUTPUT = $(RTOSDEMO_OUTPUT_DIR)/executable.elf\r
+\r
+MICROBLAZE_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/microblaze/mb_bootloop.elf\r
+PPC405_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/ppc405/ppc_bootloop.elf\r
+BOOTLOOP_DIR = bootloops\r
+\r
+MICROBLAZE_0_BOOTLOOP = $(BOOTLOOP_DIR)/microblaze_0.elf\r
+MICROBLAZE_0_XMDSTUB = microblaze_0/code/xmdstub.elf\r
+\r
+BRAMINIT_ELF_FILES = $(RTOSDEMO_OUTPUT) \r
+BRAMINIT_ELF_FILE_ARGS = -pe microblaze_0 $(RTOSDEMO_OUTPUT) \r
+\r
+ALL_USER_ELF_FILES = $(RTOSDEMO_OUTPUT) \r
+\r
+SIM_CMD = vsim\r
+\r
+BEHAVIORAL_SIM_SCRIPT = simulation/behavioral/$(SYSTEM).do\r
+\r
+STRUCTURAL_SIM_SCRIPT = simulation/structural/$(SYSTEM).do\r
+\r
+TIMING_SIM_SCRIPT = simulation/timing/$(SYSTEM).do\r
+\r
+DEFAULT_SIM_SCRIPT = $(BEHAVIORAL_SIM_SCRIPT)\r
+\r
+MIX_LANG_SIM_OPT = -mixed yes\r
+\r
+SIMGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(SUBMODULE_OPT) $(BRAMINIT_ELF_FILE_ARGS) $(MIX_LANG_SIM_OPT) -s mti\r
+\r
+MICROBLAZE_0_XMDSTUB = microblaze_0/code/xmdstub.elf\r
+\r
+LIBRARIES = \\r
+ microblaze_0/lib/libxil.a \r
+VPEXEC = virtualplatform/vpexec.exe\r
+\r
+LIBSCLEAN_TARGETS = microblaze_0_libsclean \r
+\r
+PROGRAMCLEAN_TARGETS = RTOSDemo_programclean \r
+\r
+CORE_STATE_DEVELOPMENT_FILES = \r
+\r
+WRAPPER_NGC_FILES = implementation/microblaze_0_wrapper.ngc \
+implementation/mb_opb_wrapper.ngc \
+implementation/debug_module_wrapper.ngc \
+implementation/ilmb_wrapper.ngc \
+implementation/dlmb_wrapper.ngc \
+implementation/dlmb_cntlr_wrapper.ngc \
+implementation/ilmb_cntlr_wrapper.ngc \
+implementation/lmb_bram_wrapper.ngc \
+implementation/rs232_uart_wrapper.ngc \
+implementation/leds_4bit_wrapper.ngc \
+implementation/leds_positions_wrapper.ngc \
+implementation/opb_timer_1_wrapper.ngc \
+implementation/opb_intc_0_wrapper.ngc \
+implementation/dcm_0_wrapper.ngc\r
+\r
+POSTSYN_NETLIST = implementation/$(SYSTEM).ngc\r
+\r
+SYSTEM_BIT = implementation/$(SYSTEM).bit\r
+\r
+DOWNLOAD_BIT = implementation/download.bit\r
+\r
+SYSTEM_ACE = implementation/$(SYSTEM).ace\r
+\r
+UCF_FILE = data/system.ucf\r
+\r
+BMM_FILE = implementation/$(SYSTEM).bmm\r
+\r
+FASTRUNTIME_OPT_FILE = etc/fast_runtime.opt\r
+BITGEN_UT_FILE = etc/bitgen.ut\r
+\r
+#################################################################\r
+# SOFTWARE APPLICATION RTOSDEMO\r
+#################################################################\r
+\r
+RTOSDEMO_SOURCES = main.c ParTest/ParTest.c ../../Source/tasks.c ../../Source/queue.c ../../Source/list.c ../../Source/portable/MemMang/heap_1.c ../../Source/portable/GCC/MicroBlaze/port.c ../../Source/portable/GCC/MicroBlaze/portasm.s ../Common/Minimal/flash.c serial/serial.c ../Common/Minimal/comtest.c ../Common/Minimal/integer.c ../Common/Minimal/semtest.c ../Common/Minimal/dynamic.c ../Common/Minimal/PollQ.c ../Common/Minimal/BlockQ.c \r
+\r
+RTOSDEMO_HEADERS = FreeRTOSConfig.h \r
+\r
+RTOSDEMO_CC = mb-gcc\r
+RTOSDEMO_CC_SIZE = mb-size\r
+RTOSDEMO_CC_OPT = -Os\r
+RTOSDEMO_CFLAGS = -D MICROBLAZE_GCC -Wall\r
+RTOSDEMO_CC_SEARCH = # -B\r
+RTOSDEMO_LIBPATH = -L./microblaze_0/lib/ # -L\r
+RTOSDEMO_INCLUDES = -I./microblaze_0/include/ -IDev/FreeRTOS/Demo/MicroBlaze/ -I. -I../Common/include -I../../Source/include -I../../Source/portable/GCC/MicroBlaze \r
+RTOSDEMO_LFLAGS = # -l\r
+RTOSDEMO_CC_PREPROC_FLAG = # -Wp,\r
+RTOSDEMO_CC_ASM_FLAG = # -Wa,\r
+RTOSDEMO_CC_LINKER_FLAG = -Wl,-Map=rtosdemo.map \r
+RTOSDEMO_LINKER_SCRIPT = \r
+RTOSDEMO_LINKER_SCRIPT_FLAG = #-Wl,-T -Wl,$(RTOSDEMO_LINKER_SCRIPT) \r
+RTOSDEMO_CC_DEBUG_FLAG = -g \r
+RTOSDEMO_CC_GLOBPTR_FLAG= # -mxl-gp-opt\r
+RTOSDEMO_MODE = executable\r
+RTOSDEMO_LIBG_OPT = -$(RTOSDEMO_MODE) microblaze_0\r
+RTOSDEMO_CC_SOFTMUL_FLAG= -mno-xl-soft-mul \r
+RTOSDEMO_CC_START_ADDR_FLAG= # -Wl,-defsym -Wl,_TEXT_START_ADDR=\r
+RTOSDEMO_CC_STACK_SIZE_FLAG= # -Wl,-defsym -Wl,_STACK_SIZE=\r
+RTOSDEMO_OTHER_CC_FLAGS= $(RTOSDEMO_CC_GLOBPTR_FLAG) \\r
+ $(RTOSDEMO_CC_START_ADDR_FLAG) $(RTOSDEMO_CC_STACK_SIZE_FLAG) \\r
+ $(RTOSDEMO_CC_SOFTMUL_FLAG) \\r
+ $(RTOSDEMO_CC_PREPROC_FLAG) $(RTOSDEMO_CC_ASM_FLAG) $(RTOSDEMO_CC_LINKER_FLAG) \\r
+ $(RTOSDEMO_LINKER_SCRIPT_FLAG) $(RTOSDEMO_CC_DEBUG_FLAG) \r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+#include <conio.h>\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions for the x86 port.\r
+ *----------------------------------------------------------*/\r
+\r
+/* These are the only definitions that can be modified!. */\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 1\r
+#define configUSE_TICK_HOOK 1\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 128 ) /* This can be made smaller if required. */\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 32 * 1024 ) ) \r
+#define configMAX_TASK_NAME_LEN ( 16 )\r
+#define configUSE_TRACE_FACILITY 0\r
+#define configUSE_16_BIT_TICKS 1\r
+#define configIDLE_SHOULD_YIELD 1\r
+#define configUSE_CO_ROUTINES 1\r
+\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 10 )\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+\r
+/* The maximum number of characters a task name can take, \r
+including the null terminator. */\r
+#define configMAX_TASK_NAME_LEN ( 16 )\r
+\r
+/* Set the following definitions to 1 to include the component, or zero\r
+to exclude the component. */\r
+\r
+/* Include/exclude the stated API function. */\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 1\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+\r
+\r
+/* \r
+ * The tick count (and times defined in tick count units) can be either a 16bit\r
+ * or a 32 bit value. See documentation on http://www.FreeRTOS.org to decide\r
+ * which to use.\r
+ */\r
+#define configUSE_16_BIT_TICKS 1\r
+\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#include <stdio.h>\r
+#include <string.h>\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo program include files. */\r
+#include "fileio.h"\r
+\r
+void vDisplayMessage( const portCHAR * const pcMessageToPrint )\r
+{\r
+ taskENTER_CRITICAL();\r
+ printf( "%s", pcMessageToPrint );\r
+ fflush( stdout );\r
+ taskEXIT_CRITICAL();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vWriteMessageToDisk( const portCHAR * const pcMessage )\r
+{\r
+const portCHAR * const pcFileName = "a:\\RTOSlog.txt";\r
+const portCHAR * const pcSeparator = "\r\n-----------------------\r\n";\r
+FILE *pf;\r
+\r
+ taskENTER_CRITICAL();\r
+ { \r
+ pf = fopen( pcFileName, "a" );\r
+ if( pf != NULL )\r
+ {\r
+ fwrite( pcMessage, strlen( pcMessage ), ( unsigned portSHORT ) 1, pf );\r
+ fwrite( pcSeparator, strlen( pcSeparator ), ( unsigned portSHORT ) 1, pf );\r
+ fclose( pf );\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vWriteBufferToDisk( const portCHAR * const pcBuffer, unsigned portLONG ulBufferLength )\r
+{\r
+const portCHAR * const pcFileName = "a:\\trace.bin";\r
+FILE *pf;\r
+\r
+ taskENTER_CRITICAL();\r
+ {\r
+ pf = fopen( pcFileName, "wb" );\r
+ if( pf )\r
+ {\r
+ fwrite( pcBuffer, ( size_t ) ulBufferLength, ( unsigned portSHORT ) 1, pf );\r
+ fclose( pf );\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+}\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+#include <i86.h>\r
+#include <conio.h>\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. \r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 1\r
+#define configUSE_TICK_HOOK 1\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 128 ) /* This can be made smaller if required. */\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 32 * 1024 ) ) \r
+#define configMAX_TASK_NAME_LEN ( 16 )\r
+#define configUSE_TRACE_FACILITY 1\r
+#define configUSE_16_BIT_TICKS 1\r
+#define configIDLE_SHOULD_YIELD 1\r
+#define configUSE_CO_ROUTINES 1\r
+\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 10 )\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 1\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+\r
+\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+Changes from V1.01:\r
+\r
+ + Types used updated.\r
+ + Add vParTestToggleLED();\r
+\r
+\r
+Changes from V2.0.0\r
+\r
+ + Use scheduler suspends in place of critical sections.\r
+*/\r
+\r
+#include "FreeRTOS.h"\r
+#include "partest.h"\r
+#include "task.h"\r
+\r
+#define partstALL_OUTPUTS_OFF ( ( unsigned portCHAR ) 0x00 )\r
+#define partstMAX_OUTPUT_LED ( ( unsigned portCHAR ) 7 )\r
+\r
+/*lint -e956 File scope parameters okay here. */\r
+static unsigned portSHORT usPortAddress = partstDEFAULT_PORT_ADDRESS;\r
+static volatile unsigned portCHAR ucCurrentOutputValue = partstALL_OUTPUTS_OFF;\r
+/*lint +e956 */\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple parallel port IO routines\r
+ *-----------------------------------------------------------*/\r
+\r
+void vParTestInitialise( void )\r
+{\r
+ ucCurrentOutputValue = partstALL_OUTPUTS_OFF;\r
+\r
+ portOUTPUT_BYTE( usPortAddress, ( unsigned ) partstALL_OUTPUTS_OFF );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, portBASE_TYPE xValue )\r
+{\r
+unsigned portCHAR ucBit = ( unsigned portCHAR ) 1;\r
+\r
+ if( uxLED <= partstMAX_OUTPUT_LED )\r
+ {\r
+ ucBit <<= uxLED;\r
+ } \r
+\r
+ vTaskSuspendAll();\r
+ {\r
+ if( xValue == pdTRUE )\r
+ {\r
+ ucBit ^= ( unsigned portCHAR ) 0xff;\r
+ ucCurrentOutputValue &= ucBit;\r
+ }\r
+ else\r
+ {\r
+ ucCurrentOutputValue |= ucBit;\r
+ }\r
+\r
+ portOUTPUT_BYTE( usPortAddress, ( unsigned ) ucCurrentOutputValue );\r
+ }\r
+ xTaskResumeAll();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+unsigned portCHAR ucBit;\r
+\r
+ if( uxLED <= partstMAX_OUTPUT_LED )\r
+ {\r
+ ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED;\r
+\r
+ vTaskSuspendAll();\r
+ {\r
+ if( ucCurrentOutputValue & ucBit )\r
+ {\r
+ ucCurrentOutputValue &= ~ucBit;\r
+ }\r
+ else\r
+ {\r
+ ucCurrentOutputValue |= ucBit;\r
+ }\r
+\r
+ portOUTPUT_BYTE( usPortAddress, ( unsigned ) ucCurrentOutputValue );\r
+ }\r
+ xTaskResumeAll(); \r
+ }\r
+}\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/**\r
+ * Creates all the demo application tasks and co-routines, then starts the \r
+ * scheduler.\r
+ *\r
+ * Main. c also creates a task called "Print". This only executes every \r
+ * five seconds but has the highest priority so is guaranteed to get \r
+ * processor time. Its main function is to check that all the other tasks \r
+ * are still operational. Nearly all the tasks in the demo application \r
+ * maintain a unique count that is incremented each time the task successfully \r
+ * completes its function. Should any error occur within the task the count is \r
+ * permanently halted. The print task checks the count of each task to ensure \r
+ * it has changed since the last time the print task executed. If any count is \r
+ * found not to have changed the print task displays an appropriate message. \r
+ * If all the tasks are still incrementing their unique counts the print task \r
+ * displays an "OK" message.\r
+ *\r
+ * The LED flash tasks do not maintain a count as they already provide visual \r
+ * feedback of their status.\r
+ *\r
+ * The print task blocks on the queue into which messages that require \r
+ * displaying are posted. It will therefore only block for the full 5 seconds\r
+ * if no messages are posted onto the queue.\r
+ *\r
+ * Main. c also provides a demonstration of how the trace visualisation utility\r
+ * can be used, and how the scheduler can be stopped.\r
+ *\r
+ * \page MainC main.c\r
+ * \ingroup DemoFiles\r
+ * <HR>\r
+ */\r
+\r
+/*\r
+Changes from V1.00:\r
+\r
+ + Prevent the call to kbhit() for debug builds as the debugger seems to\r
+ have problems stepping over the call.\r
+\r
+Changes from V1.2.3\r
+\r
+ + The integer and comtest tasks are now used when the cooperative scheduler \r
+ is being used. Previously they were only used with the preemptive\r
+ scheduler.\r
+\r
+Changes from V1.2.6\r
+\r
+ + Create new tasks as defined by the new demo application file dynamic.c.\r
+\r
+Changes from V2.0.0\r
+\r
+ + Delay periods are now specified using variables and constants of\r
+ portTickType rather than unsigned portLONG.\r
+\r
+Changes from V3.1.1\r
+\r
+ + The tasks defined in the new file "events.c" are now created and \r
+ monitored for errors. \r
+\r
+Changes from V3.2.4\r
+\r
+ + Now includes the flash co-routine demo rather than the flash task demo.\r
+ This is to demonstrate the co-routine functionality.\r
+*/\r
+\r
+#include <stdlib.h>\r
+#include <conio.h>\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "croutine.h"\r
+#include "partest.h"\r
+#include "serial.h"\r
+\r
+/* Demo file headers. */\r
+#include "BlockQ.h"\r
+#include "PollQ.h"\r
+#include "death.h"\r
+#include "crflash.h"\r
+#include "flop.h"\r
+#include "print.h"\r
+#include "comtest.h"\r
+#include "fileio.h"\r
+#include "semtest.h"\r
+#include "integer.h"\r
+#include "dynamic.h"\r
+#include "mevents.h"\r
+#include "crhook.h"\r
+\r
+/* Priority definitions for the tasks in the demo application. */\r
+#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+#define mainPRINT_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 )\r
+#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainQUEUE_BLOCK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainSEMAPHORE_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+\r
+#define mainPRINT_STACK_SIZE ( ( unsigned portSHORT ) 512 )\r
+#define mainDEBUG_LOG_BUFFER_SIZE ( ( unsigned portSHORT ) 20480 )\r
+\r
+/* The number of flash co-routines to create. */\r
+#define mainNUM_FLASH_CO_ROUTINES ( 8 )\r
+\r
+/* Task function for the "Print" task as described at the top of the file. */\r
+static void vErrorChecks( void *pvParameters );\r
+\r
+/* Function that checks the unique count of all the other tasks as described at\r
+the top of the file. */\r
+static void prvCheckOtherTasksAreStillRunning( void );\r
+\r
+/* Key presses can be used to start/stop the trace visualisation utility or stop\r
+the scheduler. */\r
+static void prvCheckForKeyPresses( void );\r
+\r
+/* Buffer used by the trace visualisation utility so only needed if the trace\r
+being used. */\r
+#if configUSE_TRACE_FACILITY == 1\r
+ static portCHAR pcWriteBuffer[ mainDEBUG_LOG_BUFFER_SIZE ];\r
+#endif\r
+\r
+/* Constant definition used to turn on/off the pre-emptive scheduler. */\r
+static const portSHORT sUsingPreemption = pdTRUE;\r
+\r
+/* Start the math tasks appropriate to the build. The Borland port does\r
+not yet support floating point so uses the integer equivalent. */\r
+static void prvStartMathTasks( void );\r
+\r
+/* Check which ever tasks are relevant to this build. */\r
+static portBASE_TYPE prvCheckMathTasksAreStillRunning( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+portSHORT main( void )\r
+{\r
+ /* Initialise hardware and utilities. */\r
+ vParTestInitialise();\r
+ vPrintInitialise();\r
+ \r
+ /* CREATE ALL THE DEMO APPLICATION TASKS. */\r
+ prvStartMathTasks();\r
+ vStartComTestTasks( mainCOM_TEST_PRIORITY, serCOM1, ser115200 );\r
+ vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
+ vStartBlockingQueueTasks( mainQUEUE_BLOCK_PRIORITY );\r
+ \r
+ vStartSemaphoreTasks( mainSEMAPHORE_TASK_PRIORITY );\r
+ vStartDynamicPriorityTasks();\r
+ vStartMultiEventTasks();\r
+\r
+ /* Create the "Print" task as described at the top of the file. */\r
+ xTaskCreate( vErrorChecks, "Print", mainPRINT_STACK_SIZE, NULL, mainPRINT_TASK_PRIORITY, NULL );\r
+\r
+ /* This task has to be created last as it keeps account of the number of tasks\r
+ it expects to see running. */\r
+ vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );\r
+\r
+ /* Create the co-routines that flash the LED's. */\r
+ vStartFlashCoRoutines( mainNUM_FLASH_CO_ROUTINES );\r
+\r
+ /* Create the co-routines that communicate with the tick hook. */\r
+ vStartHookCoRoutines();\r
+\r
+ /* Set the scheduler running. This function will not return unless a task\r
+ calls vTaskEndScheduler(). */\r
+ vTaskStartScheduler();\r
+\r
+ return 1;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vErrorChecks( void *pvParameters )\r
+{\r
+portTickType xExpectedWakeTime;\r
+const portTickType xPrintRate = ( portTickType ) 5000 / portTICK_RATE_MS;\r
+const portLONG lMaxAllowableTimeDifference = ( portLONG ) 0;\r
+portTickType xWakeTime;\r
+portLONG lTimeDifference;\r
+const portCHAR *pcReceivedMessage;\r
+const portCHAR * const pcTaskBlockedTooLongMsg = "Print task blocked too long!\r\n";\r
+\r
+ ( void ) pvParameters;\r
+\r
+ /* Loop continuously, blocking, then checking all the other tasks are still\r
+ running, before blocking once again. This task blocks on the queue of\r
+ messages that require displaying so will wake either by its time out expiring,\r
+ or a message becoming available. */\r
+ for( ;; )\r
+ {\r
+ /* Calculate the time we will unblock if no messages are received\r
+ on the queue. This is used to check that we have not blocked for too long. */\r
+ xExpectedWakeTime = xTaskGetTickCount();\r
+ xExpectedWakeTime += xPrintRate;\r
+\r
+ /* Block waiting for either a time out or a message to be posted that\r
+ required displaying. */\r
+ pcReceivedMessage = pcPrintGetNextMessage( xPrintRate );\r
+\r
+ /* Was a message received? */\r
+ if( pcReceivedMessage == NULL )\r
+ {\r
+ /* A message was not received so we timed out, did we unblock at the\r
+ expected time? */\r
+ xWakeTime = xTaskGetTickCount();\r
+\r
+ /* Calculate the difference between the time we unblocked and the\r
+ time we should have unblocked. */\r
+ if( xWakeTime > xExpectedWakeTime )\r
+ {\r
+ lTimeDifference = ( portLONG ) ( xWakeTime - xExpectedWakeTime );\r
+ }\r
+ else\r
+ {\r
+ lTimeDifference = ( portLONG ) ( xExpectedWakeTime - xWakeTime );\r
+ }\r
+\r
+ if( lTimeDifference > lMaxAllowableTimeDifference )\r
+ {\r
+ /* We blocked too long - create a message that will get\r
+ printed out the next time around. If we are not using\r
+ preemption then we won't expect the timing to be so\r
+ accurate. */\r
+ if( sUsingPreemption == pdTRUE )\r
+ {\r
+ vPrintDisplayMessage( &pcTaskBlockedTooLongMsg );\r
+ }\r
+ }\r
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+ /* Key presses can be used to start/stop the trace utility, or end the \r
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+ switch( sIn )\r
+ {\r
+ /* Only define keys for turning on and off the trace if the trace\r
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+ break; \r
+ case 's' : vTaskStartTrace( pcWriteBuffer, mainDEBUG_LOG_BUFFER_SIZE );\r
+ break;\r
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+ case 'e' : {\r
+ unsigned portLONG ulBufferLength;\r
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+ }\r
+ break;\r
+ #endif\r
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+ default : vTaskEndScheduler();\r
+ break;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCheckOtherTasksAreStillRunning( void )\r
+{\r
+static portSHORT sErrorHasOccurred = pdFALSE;\r
+\r
+ if( prvCheckMathTasksAreStillRunning() != pdTRUE )\r
+ {\r
+ vDisplayMessage( "Maths task count unchanged!\r\n" );\r
+ sErrorHasOccurred = pdTRUE;\r
+ }\r
+\r
+ if( xAreComTestTasksStillRunning() != pdTRUE )\r
+ {\r
+ vDisplayMessage( "Com test count unchanged!\r\n" );\r
+ sErrorHasOccurred = pdTRUE;\r
+ }\r
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+ if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
+ {\r
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+ sErrorHasOccurred = pdTRUE;\r
+ }\r
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+ if( xArePollingQueuesStillRunning() != pdTRUE )\r
+ {\r
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+ sErrorHasOccurred = pdTRUE;\r
+ }\r
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+ if( xIsCreateTaskStillRunning() != pdTRUE )\r
+ {\r
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+ sErrorHasOccurred = pdTRUE;\r
+ }\r
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+ if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ vDisplayMessage( "Semaphore take count unchanged!\r\n" );\r
+ sErrorHasOccurred = pdTRUE;\r
+ }\r
+\r
+ if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )\r
+ {\r
+ vDisplayMessage( "Dynamic priority count unchanged!\r\n" );\r
+ sErrorHasOccurred = pdTRUE;\r
+ }\r
+ \r
+ if( xAreMultiEventTasksStillRunning() != pdTRUE )\r
+ {\r
+ vDisplayMessage( "Error in multi events tasks!\r\n" );\r
+ sErrorHasOccurred = pdTRUE;\r
+ }\r
+\r
+ if( xAreFlashCoRoutinesStillRunning() != pdTRUE )\r
+ {\r
+ vDisplayMessage( "Error in co-routine flash tasks!\r\n" );\r
+ sErrorHasOccurred = pdTRUE;\r
+ }\r
+\r
+ if( xAreHookCoRoutinesStillRunning() != pdTRUE )\r
+ {\r
+ vDisplayMessage( "Error in tick hook to co-routine communications!\r\n" );\r
+ sErrorHasOccurred = pdTRUE;\r
+ }\r
+\r
+ if( sErrorHasOccurred == pdFALSE )\r
+ {\r
+ vDisplayMessage( "OK " );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvStartMathTasks( void )\r
+{\r
+ #ifdef BCC_INDUSTRIAL_PC_PORT\r
+ /* The Borland project does not yet support floating point. */\r
+ vStartIntegerMathTasks( tskIDLE_PRIORITY );\r
+ #else\r
+ vStartMathTasks( tskIDLE_PRIORITY );\r
+ #endif\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portBASE_TYPE prvCheckMathTasksAreStillRunning( void )\r
+{\r
+ #ifdef BCC_INDUSTRIAL_PC_PORT\r
+ /* The Borland project does not yet support floating point. */\r
+ return xAreIntegerMathsTaskStillRunning();\r
+ #else\r
+ return xAreMathsTaskStillRunning();\r
+ #endif\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationIdleHook( void )\r
+{\r
+ /* The co-routines are executed in the idle task using the idle task \r
+ hook. */\r
+ vCoRoutineSchedule();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
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--- /dev/null
+/*\r
+ This serial port driver is borrowed heavily from DZComm. I have\r
+ simplified it by removing a lot of the functionality (hardware \r
+ flow control, etc.). For more details and the full version see\r
+ http://dzcomm.sourceforge.net\r
+\r
+\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+Changes from V1.00:\r
+ \r
+ + Call to the more efficient portSWITCH_CONTEXT() replaces the call to \r
+ taskYIELD() in the ISR.\r
+\r
+Changes from V1.2.0:\r
+\r
+ + Added vSerialPutString().\r
+\r
+Changes from V1.2.3\r
+\r
+ + The function xPortInitMinimal() has been renamed to \r
+ xSerialPortInitMinimal() and the function xPortInit() has been renamed\r
+ to xSerialPortInit().\r
+\r
+Changes From V2.0.0\r
+\r
+ + Use portTickType in place of unsigned pdLONG for delay periods.\r
+ + cQueueReieveFromISR() used in place of xQueueReceive() in ISR.\r
+*/\r
+\r
+\r
+#include <stdlib.h>\r
+#include <dos.h>\r
+#include "FreeRTOS.h"\r
+#include "queue.h"\r
+#include "task.h"\r
+#include "semphr.h"\r
+#include "portasm.h"\r
+\r
+#define serMAX_IRQs ( 16 )\r
+#define serTRANSMIT_HOLD_EMPTY_INT ( 0x02 )\r
+#define serCOM1_STANDARD_IRQ ( ( unsigned portCHAR ) 4 )\r
+#define serCOM2_STANDARD_IRQ ( ( unsigned portCHAR ) 3 )\r
+\r
+\r
+#define serIMR_8259_0 ( ( unsigned portCHAR ) 0x21 )\r
+#define serIMR_8259_1 ( ( unsigned portCHAR ) 0xa1 )\r
+#define serISR_8259_0 ( ( unsigned portCHAR ) 0x20 )\r
+#define serISR_8259_1 ( ( unsigned portCHAR ) 0xa0 )\r
+#define serALL_COMS_INTERRUPTS ( ( unsigned portCHAR ) 0x0f )\r
+#define serALL_MODEM_CTRL_INTERRUPTS ( ( unsigned portCHAR ) 0x0f )\r
+\r
+#define serTRANSMIT_HOLD_OFFSET ( 0 )\r
+#define serRECEIVE_DATA_OFFSET ( 0 )\r
+#define serBAUD_RATE_DIVISOR_LOW_OFFSET ( 0 )\r
+#define serBAUD_RATE_DIVISOR_HIGH_OFFSET ( 1 )\r
+#define serINTERRUPT_ENABLE_OFFSET ( 1 )\r
+#define serINTERRUPT_ID_OFFSET ( 2 )\r
+#define serFIFO_CTRL_OFFSET ( 2 )\r
+#define serLINE_CTRL_OFFSET ( 3 )\r
+#define serMODEM_CTRL_OFFSET ( 4 )\r
+#define serLINE_STATUS_OFFSET ( 5 )\r
+#define serMODEM_STATUS_OFFSET ( 6 )\r
+#define serSCR_OFFSET ( 7 )\r
+\r
+#define serMAX_BAUD ( ( unsigned portLONG ) 115200UL )\r
+\r
+#define serNO_INTERRUPTS ( 0x00 )\r
+\r
+#define vInterruptOn( pxPort, ucInterrupt ) \\r
+{ \\r
+ unsigned portCHAR ucIn = portINPUT_BYTE( pxPort->usInterruptEnableReg ); \\r
+ if( !( ucIn & ucInterrupt ) ) \\r
+ { \\r
+ portOUTPUT_BYTE( pxPort->usInterruptEnableReg, ucIn | ucInterrupt ); \\r
+ } \\r
+} \r
+/*-----------------------------------------------------------*/\r
+\r
+#define vInterruptOff( pxPort, ucInterrupt ) \\r
+{ \\r
+ unsigned portCHAR ucIn = portINPUT_BYTE( pxPort->usInterruptEnableReg ); \\r
+ if( ucIn & ucInterrupt ) \\r
+ { \\r
+ portOUTPUT_BYTE( pxPort->usInterruptEnableReg, ucIn & ~ucInterrupt); \\r
+ } \\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+typedef enum\r
+{ \r
+ serCOM1, \r
+ serCOM2, \r
+ serCOM3, \r
+ serCOM4, \r
+ serCOM5, \r
+ serCOM6, \r
+ serCOM7, \r
+ serCOM8 \r
+} eCOMPort;\r
+\r
+typedef enum \r
+{ \r
+ serNO_PARITY, \r
+ serODD_PARITY, \r
+ serEVEN_PARITY, \r
+ serMARK_PARITY, \r
+ serSPACE_PARITY \r
+} eParity;\r
+\r
+typedef enum \r
+{ \r
+ serSTOP_1, \r
+ serSTOP_2 \r
+} eStopBits;\r
+\r
+typedef enum \r
+{ \r
+ serBITS_5, \r
+ serBITS_6, \r
+ serBITS_7, \r
+ serBITS_8 \r
+} eDataBits;\r
+\r
+typedef enum \r
+{ \r
+ ser50, \r
+ ser75, \r
+ ser110, \r
+ ser134, \r
+ ser150, \r
+ ser200,\r
+ ser300, \r
+ ser600, \r
+ ser1200, \r
+ ser1800, \r
+ ser2400, \r
+ ser4800,\r
+ ser9600, \r
+ ser19200, \r
+ ser38400, \r
+ ser57600, \r
+ ser115200\r
+} eBaud;\r
+\r
+/* This *MUST* match the order in the eBaud definition. */\r
+unsigned portLONG ulBaudFromEnum[] = \r
+{ \r
+ ( unsigned portLONG ) 50, \r
+ ( unsigned portLONG ) 75, \r
+ ( unsigned portLONG ) 110, \r
+ ( unsigned portLONG ) 134, \r
+ ( unsigned portLONG ) 150, \r
+ ( unsigned portLONG ) 200, \r
+ ( unsigned portLONG ) 300, \r
+ ( unsigned portLONG ) 600, \r
+ ( unsigned portLONG ) 1200, \r
+ ( unsigned portLONG ) 1800, \r
+ ( unsigned portLONG ) 2400, \r
+ ( unsigned portLONG ) 4800, \r
+ ( unsigned portLONG ) 9600, \r
+ ( unsigned portLONG ) 19200, \r
+ ( unsigned portLONG ) 38400UL,\r
+ ( unsigned portLONG ) 57600UL,\r
+ ( unsigned portLONG ) 115200UL\r
+};\r
+\r
+typedef struct xCOM_PORT\r
+{ \r
+ unsigned portSHORT sPort; /* comm port address eg. 0x3f8 */\r
+ unsigned portCHAR ucIRQ; /* comm IRQ eg. 3 */\r
+\r
+ /* Next two fields used for setting up the IRQ routine and\r
+ * (un)masking the interrupt in certain circumstances.\r
+ */\r
+ unsigned portSHORT usIRQVector;\r
+ unsigned portCHAR ucInterruptEnableMast;\r
+\r
+ /* Read/Write buffers. */\r
+ xQueueHandle xRxedChars; \r
+ xQueueHandle xCharsForTx;\r
+\r
+ /* This lot are set up to minimise CPU time where accessing the comm\r
+ * port's registers.\r
+ */\r
+ unsigned portSHORT usTransmitHoldReg; \r
+ unsigned portSHORT usReceiveDataRegister;\r
+ unsigned portSHORT usBaudRateDivisorLow; \r
+ unsigned portSHORT usBaudRateDivisorHigh;\r
+ unsigned portSHORT usInterruptEnableReg;\r
+ unsigned portSHORT usInterruptIDReg;\r
+ unsigned portSHORT usFIFOCtrlReg;\r
+ unsigned portSHORT usLineCtrlReg;\r
+ unsigned portSHORT usModemCtrlReg;\r
+ unsigned portSHORT usLineStatusReg;\r
+ unsigned portSHORT usModemStatusReg;\r
+ unsigned portSHORT usSCRReg;\r
+ unsigned portSHORT us8259InterruptServiceReg;\r
+ unsigned portSHORT us8259InterruptMaskReg;\r
+\r
+ /* This semaphore does nothing useful except test a feature of the\r
+ scheduler. */\r
+ xSemaphoreHandle xTestSem;\r
+\r
+} xComPort;\r
+\r
+typedef xComPort *xComPortHandle;\r
+\r
+/* A xComPort structure can be associated with each IRQ. Initially none\r
+are create/installed. */\r
+xComPort *xPortStatus[ serMAX_IRQs ] = { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL };\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* These prototypes are repeated here so we don't have to include the serial header. This allows\r
+the xComPortHandle structure details to be private to this file. */\r
+xComPortHandle xSerialPortInit( eCOMPort ePort, eBaud eWantedBaud, eParity eWantedParity, eDataBits eWantedDataBits, eStopBits eWantedStopBits, unsigned portBASE_TYPE uxBufferLength );\r
+portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, portCHAR *pcRxedChar, portTickType xBlockTime );\r
+portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, portCHAR cOutChar, portTickType xBlockTime );\r
+portBASE_TYPE xSerialWaitForSemaphore( xComPortHandle xPort );\r
+\r
+static void prvSetupPortHardware( xComPort *pxPort, eCOMPort ePort, eBaud eWantedBaud, eParity eWantedParity, eDataBits eWantedDataBits, eStopBits eWantedStopBits );\r
+static portSHORT sComPortISR( const xComPort * const pxPort );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Define an interrupt handler for each slot in the xPortStatus array. */\r
+\r
+#define COM_IRQ_WRAPPER(N) \\r
+ static void __interrupt COM_IRQ##N##_WRAPPER( void ) \\r
+ { \\r
+ portDISABLE_INTERRUPTS(); \\r
+ if( sComPortISR( xPortStatus[##N##] ) ) \\r
+ { \\r
+ portSWITCH_CONTEXT(); \\r
+ } \\r
+ } \r
+\r
+COM_IRQ_WRAPPER( 0 )\r
+COM_IRQ_WRAPPER( 1 )\r
+COM_IRQ_WRAPPER( 2 )\r
+COM_IRQ_WRAPPER( 3 )\r
+COM_IRQ_WRAPPER( 4 )\r
+COM_IRQ_WRAPPER( 5 )\r
+COM_IRQ_WRAPPER( 6 )\r
+COM_IRQ_WRAPPER( 7 )\r
+COM_IRQ_WRAPPER( 8 )\r
+COM_IRQ_WRAPPER( 9 )\r
+COM_IRQ_WRAPPER( 10 )\r
+COM_IRQ_WRAPPER( 11 )\r
+COM_IRQ_WRAPPER( 12 )\r
+COM_IRQ_WRAPPER( 13 )\r
+COM_IRQ_WRAPPER( 14 )\r
+COM_IRQ_WRAPPER( 15 )\r
+\r
+static pxISR xISRs[ serMAX_IRQs ] = \r
+{\r
+ COM_IRQ0_WRAPPER, \r
+ COM_IRQ1_WRAPPER, \r
+ COM_IRQ2_WRAPPER, \r
+ COM_IRQ3_WRAPPER, \r
+ COM_IRQ4_WRAPPER, \r
+ COM_IRQ5_WRAPPER, \r
+ COM_IRQ6_WRAPPER, \r
+ COM_IRQ7_WRAPPER, \r
+ COM_IRQ8_WRAPPER, \r
+ COM_IRQ9_WRAPPER, \r
+ COM_IRQ10_WRAPPER, \r
+ COM_IRQ11_WRAPPER, \r
+ COM_IRQ12_WRAPPER, \r
+ COM_IRQ13_WRAPPER, \r
+ COM_IRQ14_WRAPPER,\r
+ COM_IRQ15_WRAPPER\r
+};\r
+\r
+static pxISR xOldISRs[ serMAX_IRQs ] = { NULL };\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+xComPortHandle xSerialPortInit( eCOMPort ePort, eBaud eWantedBaud, eParity eWantedParity, eDataBits eWantedDataBits, eStopBits eWantedStopBits, unsigned portBASE_TYPE uxBufferLength )\r
+{\r
+xComPort *pxPort;\r
+\r
+ /* Create a structure to handle this port. */\r
+ pxPort = ( xComPort * ) pvPortMalloc( sizeof( xComPort ) );\r
+ \r
+ if( pxPort != NULL )\r
+ {\r
+ /* Create the queues used by the comtest task. */\r
+ pxPort->xRxedChars = xQueueCreate( uxBufferLength, ( unsigned portBASE_TYPE ) sizeof( portCHAR ) );\r
+ pxPort->xCharsForTx = xQueueCreate( uxBufferLength, ( unsigned portBASE_TYPE ) sizeof( portCHAR ) );\r
+\r
+ /* Create the test semaphore. This does nothing useful except test a feature of the scheduler. */\r
+ vSemaphoreCreateBinary( pxPort->xTestSem );\r
+\r
+ prvSetupPortHardware( pxPort, ePort, eWantedBaud, eWantedParity, eWantedDataBits, eWantedStopBits );\r
+\r
+ return pxPort;\r
+ }\r
+\r
+ return NULL;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupPortHardware( xComPort *pxPort, eCOMPort ePort, eBaud eWantedBaud, eParity eWantedParity, eDataBits eWantedDataBits, eStopBits eWantedStopBits )\r
+{\r
+portSHORT sIn;\r
+unsigned portLONG ulDivisor;\r
+unsigned portCHAR ucDivisorLow;\r
+unsigned portCHAR ucDivisorHigh;\r
+unsigned portCHAR ucCommParam;\r
+\r
+ /* IRQ numbers - standard */\r
+ if( ( ePort == serCOM1 ) || ( ePort == serCOM3 ) || ( ePort == serCOM5 ) || ( ePort == serCOM7 ) )\r
+ {\r
+ pxPort->ucIRQ = serCOM1_STANDARD_IRQ;\r
+ pxPort->sPort = 0x3f8;\r
+ }\r
+ else\r
+ {\r
+ pxPort->ucIRQ = serCOM2_STANDARD_IRQ;\r
+ pxPort->sPort = 0x2f8;\r
+ }\r
+\r
+ /* Set up variables in port making it easy to see which sIn/o address is which */\r
+ pxPort->usTransmitHoldReg = pxPort->sPort + serTRANSMIT_HOLD_OFFSET;\r
+ pxPort->usReceiveDataRegister = pxPort->sPort + serRECEIVE_DATA_OFFSET;\r
+ pxPort->usBaudRateDivisorLow = pxPort->sPort + serBAUD_RATE_DIVISOR_LOW_OFFSET;\r
+ pxPort->usBaudRateDivisorHigh = pxPort->sPort + serBAUD_RATE_DIVISOR_HIGH_OFFSET;\r
+ pxPort->usInterruptEnableReg = pxPort->sPort + serINTERRUPT_ENABLE_OFFSET;\r
+ pxPort->usInterruptIDReg = pxPort->sPort + serINTERRUPT_ID_OFFSET;\r
+ pxPort->usFIFOCtrlReg = pxPort->sPort + serFIFO_CTRL_OFFSET;\r
+ pxPort->usLineCtrlReg = pxPort->sPort + serLINE_CTRL_OFFSET;\r
+ pxPort->usModemCtrlReg = pxPort->sPort + serMODEM_CTRL_OFFSET;\r
+ pxPort->usLineStatusReg = pxPort->sPort + serLINE_STATUS_OFFSET;\r
+ pxPort->usModemStatusReg = pxPort->sPort + serMODEM_STATUS_OFFSET;\r
+ pxPort->usSCRReg = pxPort->sPort + serSCR_OFFSET;\r
+\r
+ /* Set communication parameters. */\r
+ ulDivisor = serMAX_BAUD / ulBaudFromEnum[ eWantedBaud ];\r
+ ucDivisorLow = ( unsigned portCHAR ) ulDivisor & ( unsigned portCHAR ) 0xff;\r
+ ucDivisorHigh = ( unsigned portCHAR ) ( ( ( unsigned portSHORT ) ulDivisor >> 8 ) & 0xff );\r
+ \r
+ switch( eWantedParity )\r
+ { \r
+ case serNO_PARITY: ucCommParam = 0x00;\r
+ break;\r
+ case serODD_PARITY: ucCommParam = 0x08;\r
+ break;\r
+ case serEVEN_PARITY: ucCommParam = 0x18;\r
+ break;\r
+ case serMARK_PARITY: ucCommParam = 0x28;\r
+ break;\r
+ case serSPACE_PARITY: ucCommParam = 0x38;\r
+ break;\r
+ default: ucCommParam = 0x00;\r
+ break;\r
+ }\r
+\r
+ switch ( eWantedDataBits )\r
+ {\r
+ case serBITS_5: ucCommParam |= 0x00;\r
+ break;\r
+ case serBITS_6: ucCommParam |= 0x01;\r
+ break;\r
+ case serBITS_7: ucCommParam |= 0x02;\r
+ break;\r
+ case serBITS_8: ucCommParam |= 0x03;\r
+ break;\r
+ default: ucCommParam |= 0x03;\r
+ break;\r
+ }\r
+\r
+ if( eWantedStopBits == serSTOP_2 ) \r
+ {\r
+ ucCommParam |= 0x04;\r
+ }\r
+\r
+ /* Reset UART into known state - Thanks to Bradley Town */\r
+ portOUTPUT_BYTE( pxPort->usLineCtrlReg, 0x00 ); /* Access usTransmitHoldReg/RBR/usInterruptEnableReg */\r
+ portOUTPUT_BYTE( pxPort->usInterruptEnableReg, 0x00 ); /* Disable interrupts from UART */\r
+ portOUTPUT_BYTE( pxPort->usModemCtrlReg, 0x04 ); /* Enable some multi-port cards */\r
+\r
+ /* Code based on stuff from SVAsync lib. Clear UART Status and data registers\r
+ setting up FIFO if possible */\r
+ sIn = portINPUT_BYTE( pxPort->usSCRReg );\r
+ portOUTPUT_BYTE( pxPort->usSCRReg, 0x55 );\r
+\r
+ if( portINPUT_BYTE( pxPort->usSCRReg ) == 0x55 )\r
+ {\r
+ /* The chip is better than an 8250 */\r
+ portOUTPUT_BYTE( pxPort->usSCRReg, sIn ); /* Set usSCRReg back to what it was before */\r
+ portINPUT_BYTE( pxPort->usSCRReg); /* Give slow motherboards a chance */\r
+\r
+ /* Try and start the FIFO. It appears that some chips need a two call \r
+ protocol, but those that don't seem to work even if you do start it twice. \r
+ The first call is simply to start it, the second starts it and sets an 8 \r
+ byte FIFO trigger level. */\r
+ portOUTPUT_BYTE( pxPort->usFIFOCtrlReg, 0x01 );\r
+ portINPUT_BYTE( pxPort->usFIFOCtrlReg ); /* Give slow motherboards a chance to catch up */\r
+ portOUTPUT_BYTE( pxPort->usFIFOCtrlReg, 0x87 );\r
+\r
+ /* Check that the FIFO initialised */\r
+ if( ( portINPUT_BYTE( pxPort->usInterruptIDReg ) & 0xc0 ) != 0xc0 )\r
+ {\r
+ /* It didn't so we assume it isn't there but disable it to be on the \r
+ safe side. */\r
+ portOUTPUT_BYTE( pxPort->usInterruptIDReg, 0xfe );\r
+ }\r
+ }\r
+\r
+ /* End of (modified) SVAsync code. \r
+ Set interrupt parameters calculating mask for 8259 controller's \r
+ IMR and number of interrupt handler for given irq level */\r
+ if (pxPort->ucIRQ <= 7)\r
+ { \r
+ /* if 0<=irq<=7 first IMR address used */\r
+ pxPort->ucInterruptEnableMast = ~(0x01 << pxPort->ucIRQ);\r
+ pxPort->usIRQVector = pxPort->ucIRQ + 8;\r
+ pxPort->us8259InterruptMaskReg = serIMR_8259_0;\r
+ pxPort->us8259InterruptServiceReg = serISR_8259_0;\r
+ }\r
+ else\r
+ {\r
+ pxPort->ucInterruptEnableMast = ~( 0x01 << ( pxPort->ucIRQ % 8 ) );\r
+ pxPort->usIRQVector = 0x70 + ( pxPort->ucIRQ - 8) ;\r
+ pxPort->us8259InterruptMaskReg = serIMR_8259_1;\r
+ pxPort->us8259InterruptServiceReg = serISR_8259_1;\r
+ }\r
+\r
+ /* Set Port Toggle to usBaudRateDivisorLow/usBaudRateDivisorHigh registers \r
+ to set baud rate */\r
+ portOUTPUT_BYTE( pxPort->usLineCtrlReg, ucCommParam | 0x80 );\r
+ portOUTPUT_BYTE( pxPort->usBaudRateDivisorLow, ucDivisorLow );\r
+ portOUTPUT_BYTE( pxPort->usBaudRateDivisorHigh, ucDivisorHigh );\r
+\r
+ /* reset usLineCtrlReg and Port Toggleout */\r
+ portOUTPUT_BYTE( pxPort->usLineCtrlReg, ucCommParam & 0x7F );\r
+\r
+ portENTER_CRITICAL();\r
+\r
+ if( xPortStatus[ pxPort->ucIRQ ] == NULL )\r
+ { \r
+ xPortStatus[ pxPort->ucIRQ ] = pxPort;\r
+ }\r
+ \r
+ xOldISRs[ pxPort->ucIRQ ] = _dos_getvect( pxPort->usIRQVector );\r
+ _dos_setvect( pxPort->usIRQVector, xISRs[ pxPort->ucIRQ ] );\r
+\r
+ /* enable interrupt pxPort->ucIRQ level */\r
+ portOUTPUT_BYTE( pxPort->us8259InterruptMaskReg, portINPUT_BYTE( pxPort->us8259InterruptMaskReg ) & pxPort->ucInterruptEnableMast );\r
+\r
+ /* And allow interrupts again now the hairy bit's done */\r
+ portEXIT_CRITICAL(); \r
+\r
+ /* This version does not allow flow control. */\r
+ portOUTPUT_BYTE( pxPort->usModemCtrlReg, serALL_MODEM_CTRL_INTERRUPTS );\r
+\r
+ /* enable all communication's interrupts */\r
+ portOUTPUT_BYTE( pxPort->usInterruptEnableReg, serALL_COMS_INTERRUPTS );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portSHORT sComPortISR( const xComPort * const pxPort )\r
+{\r
+portSHORT sInterruptID;\r
+portCHAR cIn, cOut;\r
+portBASE_TYPE xTaskWokenByPost = pdFALSE, xAnotherTaskWokenByPost = pdFALSE, xTaskWokenByTx = pdFALSE;\r
+\r
+ portOUTPUT_BYTE( pxPort->us8259InterruptMaskReg, ( portINPUT_BYTE( pxPort->us8259InterruptMaskReg) | ~pxPort->ucInterruptEnableMast ) );\r
+\r
+ /* Decide which UART has issued the interrupt */\r
+ sInterruptID = portINPUT_BYTE( pxPort->usInterruptIDReg );\r
+\r
+ /* service whatever requests the calling UART may have. The top 4 bits are\r
+ either unused or indicate the presence of a functioning FIFO, which we don't\r
+ need to know. So trim them off to simplify the switch statement below. */\r
+ sInterruptID &= 0x0f;\r
+ do\r
+ {\r
+ switch( sInterruptID )\r
+ {\r
+ case 0x0c: /* Timeout\r
+ Called when FIFO not up to trigger level but no activity for \r
+ a while. Handled exactly as RDAINT, see below for \r
+ description. */\r
+ do\r
+ {\r
+ cIn = ( portCHAR ) portINPUT_BYTE( pxPort->usReceiveDataRegister ); \r
+ xTaskWokenByPost = xQueueSendFromISR( pxPort->xRxedChars, &cIn, xTaskWokenByPost );\r
+\r
+ /* Also release the semaphore - this does nothing interesting and is just a test. */\r
+ xAnotherTaskWokenByPost = xSemaphoreGiveFromISR( pxPort->xTestSem, xAnotherTaskWokenByPost );\r
+\r
+ } while( portINPUT_BYTE( pxPort->usLineStatusReg ) & 0x01 );\r
+ break;\r
+\r
+ case 0x06: /* LSINT */\r
+ portINPUT_BYTE( pxPort->usLineStatusReg );\r
+ break;\r
+\r
+ case 0x04: /* RDAINT */\r
+ /* The usInterruptIDReg flag tested above stops when the \r
+ FIFO is below the trigger level rather than empty, whereas \r
+ this flag allows one to empty it: (do loop because there \r
+ must be at least one to read by virtue of having got here.) */\r
+ do\r
+ {\r
+ cIn = ( portCHAR ) portINPUT_BYTE( pxPort->usReceiveDataRegister ); \r
+ xTaskWokenByPost = xQueueSendFromISR( pxPort->xRxedChars, &cIn, xTaskWokenByPost );\r
+\r
+ /* Also release the semaphore - this does nothing interesting and is just a test. */\r
+ xAnotherTaskWokenByPost = xSemaphoreGiveFromISR( pxPort->xTestSem, xAnotherTaskWokenByPost );\r
+\r
+ } while( portINPUT_BYTE( pxPort->usLineStatusReg ) & 0x01 );\r
+ break;\r
+\r
+ case 0x02: /* serTRANSMIT_HOLD_EMPTY_INT */\r
+ if( xQueueReceiveFromISR( pxPort->xCharsForTx, &cOut, &xTaskWokenByTx ) != pdTRUE ) \r
+ { \r
+ /* Queue empty, nothing to send */ \r
+ vInterruptOff( pxPort, serTRANSMIT_HOLD_EMPTY_INT); \r
+ } \r
+ else \r
+ { \r
+ portOUTPUT_BYTE( pxPort->usTransmitHoldReg, ( portSHORT ) cOut ); \r
+ }\r
+ break;\r
+\r
+ case 0x00: /* MSINT */\r
+ portINPUT_BYTE( pxPort->usModemStatusReg );\r
+ break;\r
+ } \r
+\r
+ /* Get the next instruction, trimming as above */\r
+ sInterruptID = portINPUT_BYTE( pxPort->usInterruptIDReg ) & 0x0f;\r
+\r
+ } while( !( sInterruptID & 0x01 ) );\r
+\r
+ if( pxPort->ucIRQ > 7 )\r
+ {\r
+ portOUTPUT_BYTE( 0xA0, 0x60 + ( pxPort->ucIRQ & 0x07 ) );\r
+ portOUTPUT_BYTE( 0x20, 0x62);\r
+ }\r
+ else\r
+ {\r
+ portOUTPUT_BYTE( 0x20, 0x60 + pxPort->ucIRQ );\r
+ }\r
+\r
+ portOUTPUT_BYTE( pxPort->us8259InterruptMaskReg, portINPUT_BYTE( pxPort->us8259InterruptMaskReg ) & pxPort->ucInterruptEnableMast );\r
+\r
+ /* If posting any of the characters to a queue woke a task that was blocked on\r
+ the queue we may want to return to the task just woken (depending on its \r
+ priority relative to the task this ISR interrupted. */\r
+ if( xTaskWokenByPost || xAnotherTaskWokenByPost || xTaskWokenByTx )\r
+ {\r
+ return pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ return pdFALSE;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, portCHAR *pcRxedChar, portTickType xBlockTime )\r
+{\r
+ /* Get the next character from the buffer, note that this routine is only \r
+ called having checked that the is (at least) one to get */\r
+ if( xQueueReceive( pxPort->xRxedChars, pcRxedChar, xBlockTime ) )\r
+ {\r
+ return pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ return pdFALSE;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, portCHAR cOutChar, portTickType xBlockTime )\r
+{\r
+ if( xQueueSend( pxPort->xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )\r
+ {\r
+ return pdFAIL;\r
+ }\r
+\r
+ vInterruptOn( pxPort, serTRANSMIT_HOLD_EMPTY_INT );\r
+\r
+ return pdPASS;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSerialPutString( xComPortHandle pxPort, const portCHAR * const pcString, unsigned portSHORT usStringLength )\r
+{\r
+portCHAR * pcNextChar;\r
+const portTickType xNoBlock = ( portTickType ) 0;\r
+\r
+ /* Stop warnings. */\r
+ ( void ) usStringLength;\r
+\r
+ pcNextChar = ( portCHAR * ) pcString;\r
+ while( *pcNextChar )\r
+ {\r
+ xSerialPutChar( pxPort, *pcNextChar, xNoBlock );\r
+ pcNextChar++;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portBASE_TYPE xSerialWaitForSemaphore( xComPortHandle xPort )\r
+{\r
+const portTickType xBlockTime = ( portTickType ) 0xffff;\r
+\r
+ /* This function does nothing interesting, but test the \r
+ semaphore from ISR mechanism. */\r
+ return xSemaphoreTake( xPort->xTestSem, xBlockTime ); \r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSerialClose( xComPortHandle xPort )\r
+{\r
+ portENTER_CRITICAL();\r
+\r
+ /* Turn off the interrupts. */\r
+ portOUTPUT_BYTE( xPort->usModemCtrlReg, serNO_INTERRUPTS );\r
+ portOUTPUT_BYTE( xPort->usInterruptEnableReg, serNO_INTERRUPTS );\r
+\r
+ /* Put back the original ISR. */\r
+ _dos_setvect( xPort->usIRQVector, xOldISRs[ xPort->ucIRQ ] );\r
+\r
+ /* Remove the reference in the array of xComPort structures. */\r
+ xPortStatus[ xPort->ucIRQ ] = NULL;\r
+\r
+ /* Delete the queues. */\r
+ vQueueDelete( xPort->xRxedChars );\r
+ vQueueDelete( xPort->xCharsForTx );\r
+\r
+ vPortFree( ( void * ) xPort );\r
+\r
+ portEXIT_CRITICAL();\r
+}\r
+\r
--- /dev/null
+// $Id: 18f452.lkr,v 1.4 2003/03/13 05:02:23 sealep Exp $\r
+// File: 18f452.lkr\r
+// Sample linker script for the PIC18F452 processor\r
+\r
+LIBPATH .\r
+\r
+FILES c018i.o\r
+FILES clib.lib\r
+FILES p18f452.lib\r
+\r
+CODEPAGE NAME=vectors START=0x0 END=0x39 PROTECTED\r
+CODEPAGE NAME=page START=0x3A END=0x7FFF\r
+CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED\r
+CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED\r
+CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED\r
+CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED\r
+\r
+ACCESSBANK NAME=accessram START=0x0 END=0x7F\r
+DATABANK NAME=BIG_BLOCK START=0x80 END=0x5FF\r
+ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED\r
+\r
+SECTION NAME=CONFIG ROM=config\r
+\r
+STACK SIZE=0x60 RAM=BIG_BLOCK\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+#include <p18cxxx.h>\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. \r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 20000000 )\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 4 )\r
+#define configMINIMAL_STACK_SIZE ( 105 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) 1024 )\r
+#define configMAX_TASK_NAME_LEN ( 4 )\r
+#define configUSE_TRACE_FACILITY 0\r
+#define configUSE_16_BIT_TICKS 1\r
+#define configIDLE_SHOULD_YIELD 1\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet 0\r
+#define INCLUDE_uxTaskPriorityGet 0\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 0\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* \r
+Changes from V2.0.0\r
+\r
+ + Use scheduler suspends in place of critical sections.\r
+*/\r
+\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "partest.h"\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple parallel port IO routines for the FED 40pin demo board.\r
+ * The four LED's are connected to D4 to D7.\r
+ *-----------------------------------------------------------*/\r
+\r
+#define partstBIT_AS_OUTPUT ( ( unsigned portSHORT ) 0 )\r
+#define partstSET_OUTPUT ( ( unsigned portSHORT ) 1 )\r
+#define partstCLEAR_OUTPUT ( ( unsigned portSHORT ) 0 )\r
+\r
+#define partstENABLE_GENERAL_IO ( ( unsigned portCHAR ) 7 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestInitialise( void )\r
+{\r
+ /* Set the top four bits of port D to output. */\r
+ TRISDbits.TRISD7 = partstBIT_AS_OUTPUT;\r
+ TRISDbits.TRISD6 = partstBIT_AS_OUTPUT;\r
+ TRISDbits.TRISD5 = partstBIT_AS_OUTPUT;\r
+ TRISDbits.TRISD4 = partstBIT_AS_OUTPUT;\r
+\r
+ /* Start with all bits off. */\r
+ PORTDbits.RD7 = partstCLEAR_OUTPUT;\r
+ PORTDbits.RD6 = partstCLEAR_OUTPUT;\r
+ PORTDbits.RD5 = partstCLEAR_OUTPUT;\r
+ PORTDbits.RD4 = partstCLEAR_OUTPUT;\r
+\r
+ /* Enable the driver. */\r
+ ADCON1 = partstENABLE_GENERAL_IO;\r
+ TRISEbits.TRISE2 = partstBIT_AS_OUTPUT;\r
+ PORTEbits.RE2 = partstSET_OUTPUT; \r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, portBASE_TYPE xValue )\r
+{\r
+ /* We are only using the top nibble, so LED 0 corresponds to bit 4. */ \r
+ vTaskSuspendAll();\r
+ {\r
+ switch( uxLED )\r
+ {\r
+ case 3 : PORTDbits.RD7 = ( portSHORT ) xValue;\r
+ break;\r
+ case 2 : PORTDbits.RD6 = ( portSHORT ) xValue;\r
+ break;\r
+ case 1 : PORTDbits.RD5 = ( portSHORT ) xValue;\r
+ break;\r
+ case 0 : PORTDbits.RD4 = ( portSHORT ) xValue;\r
+ break;\r
+ default : /* There are only 4 LED's. */\r
+ break;\r
+ }\r
+ }\r
+ xTaskResumeAll();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+ /* We are only using the top nibble, so LED 0 corresponds to bit 4. */ \r
+ vTaskSuspendAll();\r
+ {\r
+ switch( uxLED )\r
+ {\r
+ case 3 : PORTDbits.RD7 = !( PORTDbits.RD7 );\r
+ break;\r
+ case 2 : PORTDbits.RD6 = !( PORTDbits.RD6 );\r
+ break;\r
+ case 1 : PORTDbits.RD5 = !( PORTDbits.RD5 );\r
+ break;\r
+ case 0 : PORTDbits.RD4 = !( PORTDbits.RD4 );\r
+ break;\r
+ default : /* There are only 4 LED's. */\r
+ break;\r
+ }\r
+ }\r
+ xTaskResumeAll();\r
+}\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+ * Instead of the normal single demo application, the PIC18F demo is split \r
+ * into several smaller programs of which this is the first. This enables the \r
+ * demo's to be executed on the RAM limited 40 pin devices. The 64 and 80 pin \r
+ * devices require a more costly development platform and are not so readily \r
+ * available.\r
+ *\r
+ * The RTOSDemo1 project is configured for a PIC18F452 device. Main1.c starts 5 \r
+ * tasks (including the idle task).\r
+ *\r
+ * The first task runs at the idle priority. It repeatedly performs a 32bit \r
+ * calculation and checks it's result against the expected value. This checks \r
+ * that the temporary storage utilised by the compiler to hold intermediate \r
+ * results does not get corrupted when the task gets switched in and out. See \r
+ * demo/common/minimal/integer.c for more information.\r
+ *\r
+ * The second and third tasks pass an incrementing value between each other on \r
+ * a message queue. See demo/common/minimal/PollQ.c for more information.\r
+ *\r
+ * Main1.c also creates a check task. This periodically checks that all the \r
+ * other tasks are still running and have not experienced any unexpected \r
+ * results. If all the other tasks are executing correctly an LED is flashed \r
+ * once every mainCHECK_PERIOD milliseconds. If any of the tasks have not \r
+ * executed, or report and error, the frequency of the LED flash will increase \r
+ * to mainERROR_FLASH_RATE.\r
+ *\r
+ * On entry to main an 'X' is transmitted. Monitoring the serial port using a\r
+ * dumb terminal allows for verification that the device is not continuously \r
+ * being reset (no more than one 'X' should be transmitted).\r
+ *\r
+ * http://www.FreeRTOS.org contains important information on the use of the \r
+ * PIC18F port.\r
+ */\r
+\r
+/*\r
+Changes from V2.0.0\r
+\r
+ + Delay periods are now specified using variables and constants of\r
+ portTickType rather than unsigned portLONG.\r
+*/\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo app include files. */\r
+#include "pollq.h"\r
+#include "integer.h"\r
+#include "partest.h"\r
+#include "serial.h"\r
+\r
+/* The period between executions of the check task before and after an error\r
+has been discovered. If an error has been discovered the check task runs\r
+more frequently - increasing the LED flash rate. */\r
+#define mainNO_ERROR_CHECK_PERIOD ( ( portTickType ) 1000 / portTICK_RATE_MS )\r
+#define mainERROR_CHECK_PERIOD ( ( portTickType ) 100 / portTICK_RATE_MS )\r
+\r
+/* Priority definitions for some of the tasks. Other tasks just use the idle\r
+priority. */\r
+#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+\r
+/* The LED that is flashed by the check task. */\r
+#define mainCHECK_TASK_LED ( 0 )\r
+\r
+/* Constants required for the communications. Only one character is ever \r
+transmitted. */\r
+#define mainCOMMS_QUEUE_LENGTH ( 5 )\r
+#define mainNO_BLOCK ( ( portTickType ) 0 )\r
+#define mainBAUD_RATE ( ( unsigned portLONG ) 9600 )\r
+\r
+/*\r
+ * The task function for the "Check" task.\r
+ */\r
+static void vErrorChecks( void *pvParameters );\r
+\r
+/*\r
+ * Checks the unique counts of other tasks to ensure they are still operational.\r
+ * Returns pdTRUE if an error is detected, otherwise pdFALSE.\r
+ */\r
+static portBASE_TYPE prvCheckOtherTasksAreStillRunning( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Creates the tasks, then starts the scheduler. */\r
+void main( void )\r
+{\r
+ /* Initialise the required hardware. */\r
+ vParTestInitialise();\r
+ vPortInitialiseBlocks();\r
+\r
+ /* Send a character so we have some visible feedback of a reset. */\r
+ xSerialPortInitMinimal( mainBAUD_RATE, mainCOMMS_QUEUE_LENGTH );\r
+ xSerialPutChar( NULL, 'X', mainNO_BLOCK );\r
+\r
+ /* Start the standard demo tasks found in the demo\common directory. */\r
+ vStartIntegerMathTasks( tskIDLE_PRIORITY );\r
+ vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
+\r
+ /* Start the check task defined in this file. */\r
+ xTaskCreate( vErrorChecks, ( const portCHAR * const ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
+\r
+ /* Start the scheduler. Will never return here. */\r
+ vTaskStartScheduler();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vErrorChecks( void *pvParameters )\r
+{\r
+portTickType xDelayTime = mainNO_ERROR_CHECK_PERIOD;\r
+portBASE_TYPE xErrorOccurred;\r
+\r
+ /* Cycle for ever, delaying then checking all the other tasks are still\r
+ operating without error. */\r
+ for( ;; )\r
+ {\r
+ /* Wait until it is time to check the other tasks. */\r
+ vTaskDelay( xDelayTime );\r
+\r
+ /* Check all the other tasks are running, and running without ever\r
+ having an error. */\r
+ xErrorOccurred = prvCheckOtherTasksAreStillRunning();\r
+\r
+ /* If an error was detected increase the frequency of the LED flash. */\r
+ if( xErrorOccurred == pdTRUE )\r
+ {\r
+ xDelayTime = mainERROR_CHECK_PERIOD;\r
+ }\r
+\r
+ /* Flash the LED for visual feedback. */\r
+ vParTestToggleLED( mainCHECK_TASK_LED );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portBASE_TYPE prvCheckOtherTasksAreStillRunning( void )\r
+{\r
+portBASE_TYPE xErrorHasOccurred = pdFALSE;\r
+\r
+ if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ xErrorHasOccurred = pdTRUE;\r
+ }\r
+\r
+ if( xArePollingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ xErrorHasOccurred = pdTRUE;\r
+ }\r
+\r
+ return xErrorHasOccurred;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+ * Instead of the normal single demo application, the PIC18F demo is split \r
+ * into several smaller programs of which this is the second. This enables the \r
+ * demo's to be executed on the RAM limited 40 pin devices. The 64 and 80 pin \r
+ * devices require a more costly development platform and are not so readily \r
+ * available.\r
+ *\r
+ * The RTOSDemo2 project is configured for a PIC18F452 device. Main2.c starts \r
+ * 5 tasks (including the idle task).\r
+ * \r
+ * The first, second and third tasks do nothing but flash an LED. This gives\r
+ * visual feedback that everything is executing as expected. One task flashes\r
+ * an LED every 333ms (i.e. on and off every 333/2 ms), then next every 666ms\r
+ * and the last every 999ms.\r
+ *\r
+ * The last task runs at the idle priority. It repeatedly performs a 32bit \r
+ * calculation and checks it's result against the expected value. This checks \r
+ * that the temporary storage utilised by the compiler to hold intermediate \r
+ * results does not get corrupted when the task gets switched in and out.\r
+ * should the calculation ever provide an incorrect result the final LED is\r
+ * turned on.\r
+ *\r
+ * On entry to main() an 'X' is transmitted. Monitoring the serial port using a\r
+ * dumb terminal allows for verification that the device is not continuously \r
+ * being reset (no more than one 'X' should be transmitted).\r
+ *\r
+ * http://www.FreeRTOS.org contains important information on the use of the \r
+ * PIC18F port.\r
+ */\r
+\r
+/*\r
+Changes from V2.0.0\r
+\r
+ + Delay periods are now specified using variables and constants of\r
+ portTickType rather than unsigned portLONG.\r
+*/\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo app include files. */\r
+#include "flash.h"\r
+#include "partest.h"\r
+#include "serial.h"\r
+\r
+/* Priority definitions for the LED tasks. Other tasks just use the idle\r
+priority. */\r
+#define mainLED_FLASH_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portBASE_TYPE ) 1 )\r
+\r
+/* The LED that is lit when should the calculation fail. */\r
+#define mainCHECK_TASK_LED ( ( unsigned portBASE_TYPE ) 3 )\r
+\r
+/* Constants required for the communications. Only one character is ever \r
+transmitted. */\r
+#define mainCOMMS_QUEUE_LENGTH ( ( unsigned portBASE_TYPE ) 5 )\r
+#define mainNO_BLOCK ( ( portTickType ) 0 )\r
+#define mainBAUD_RATE ( ( unsigned portLONG ) 9600 )\r
+\r
+/*\r
+ * The task that performs the 32 bit calculation at the idle priority.\r
+ */\r
+static void vCalculationTask( void *pvParameters );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Creates the tasks, then starts the scheduler. */\r
+void main( void )\r
+{\r
+ /* Initialise the required hardware. */\r
+ vParTestInitialise();\r
+ vPortInitialiseBlocks();\r
+\r
+ /* Send a character so we have some visible feedback of a reset. */\r
+ xSerialPortInitMinimal( mainBAUD_RATE, mainCOMMS_QUEUE_LENGTH );\r
+ xSerialPutChar( NULL, 'X', mainNO_BLOCK );\r
+\r
+ /* Start the standard LED flash tasks as defined in demo/common/minimal. */\r
+ vStartLEDFlashTasks( mainLED_FLASH_PRIORITY );\r
+\r
+ /* Start the check task defined in this file. */\r
+ xTaskCreate( vCalculationTask, ( const portCHAR * const ) "Check", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );\r
+\r
+ /* Start the scheduler. */\r
+ vTaskStartScheduler();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vCalculationTask( void *pvParameters )\r
+{\r
+volatile unsigned long ulCalculatedValue; /* Volatile to ensure optimisation is minimal. */\r
+\r
+ /* Continuously perform a calculation. If the calculation result is ever\r
+ incorrect turn the LED on. */\r
+ for( ;; )\r
+ {\r
+ /* A good optimising compiler would just remove all this! */\r
+ ulCalculatedValue = 1234UL;\r
+ ulCalculatedValue *= 99UL;\r
+\r
+ if( ulCalculatedValue != 122166UL )\r
+ {\r
+ vParTestSetLED( mainCHECK_TASK_LED, pdTRUE );\r
+ }\r
+\r
+ ulCalculatedValue *= 9876UL;\r
+\r
+ if( ulCalculatedValue != 1206511416UL )\r
+ {\r
+ vParTestSetLED( mainCHECK_TASK_LED, pdTRUE );\r
+ }\r
+\r
+ ulCalculatedValue /= 15UL;\r
+\r
+ if( ulCalculatedValue != 80434094UL )\r
+ {\r
+ vParTestSetLED( mainCHECK_TASK_LED, pdTRUE );\r
+ }\r
+\r
+ ulCalculatedValue += 918273UL;\r
+\r
+ if( ulCalculatedValue != 81352367UL )\r
+ {\r
+ vParTestSetLED( mainCHECK_TASK_LED, pdTRUE );\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+ * THIS DEMO APPLICATION REQUIRES A LOOPBACK CONNECTOR TO BE FITTED TO THE PIC\r
+ * USART PORT - connect pin 2 to pin 3 on J2.\r
+ *\r
+ * Instead of the normal single demo application, the PIC18F demo is split \r
+ * into several smaller programs of which this is the third. This enables the \r
+ * demo's to be executed on the RAM limited 40 pin devices. The 64 and 80 pin \r
+ * devices require a more costly development platform and are not so readily \r
+ * available.\r
+ *\r
+ * The RTOSDemo3 project is configured for a PIC18F452 device. Main3.c starts\r
+ * 5 tasks (including the idle task).\r
+ * \r
+ * The first task repeatedly transmits a string of characters on the PIC USART\r
+ * port. The second task receives the characters, checking that the correct\r
+ * sequence is maintained (i.e. what is transmitted is identical to that \r
+ * received). Each transmitted and each received character causes an LED to \r
+ * flash. See demo/common/minimal/comtest. c for more information.\r
+ *\r
+ * The third task continuously performs a 32 bit calculation. This is a good\r
+ * test of the context switch mechanism as the 8 bit architecture requires \r
+ * the use of several file registers to perform the 32 bit operations. See\r
+ * demo/common/minimal/integer. c for more information.\r
+ *\r
+ * The third task is the check task. This periodically checks that the other\r
+ * tasks are still running and have not experienced any errors. If no errors\r
+ * have been reported by either the comms or integer tasks an LED is flashed\r
+ * with a frequency mainNO_ERROR_CHECK_PERIOD. If an error is discovered the \r
+ * frequency is increased to mainERROR_FLASH_RATE.\r
+ *\r
+ * The check task also provides a visual indication of a system reset by\r
+ * flashing the one remaining LED (mainRESET_LED) when it starts. After \r
+ * this initial flash mainRESET_LED should remain off.\r
+ *\r
+ * http://www.FreeRTOS.org contains important information on the use of the \r
+ * PIC18F port.\r
+ */\r
+\r
+/*\r
+Changes from V2.0.0\r
+\r
+ + Delay periods are now specified using variables and constants of\r
+ portTickType rather than unsigned portLONG.\r
+*/\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo app include files. */\r
+#include "partest.h"\r
+#include "serial.h"\r
+#include "comtest.h"\r
+#include "integer.h"\r
+\r
+/* Priority definitions for the LED tasks. Other tasks just use the idle\r
+priority. */\r
+#define mainCOMM_TEST_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portBASE_TYPE ) 2 )\r
+#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portBASE_TYPE ) 3 )\r
+\r
+/* The period between executions of the check task before and after an error\r
+has been discovered. If an error has been discovered the check task runs\r
+more frequently - increasing the LED flash rate. */\r
+#define mainNO_ERROR_CHECK_PERIOD ( ( portTickType ) 1000 / portTICK_RATE_MS )\r
+#define mainERROR_CHECK_PERIOD ( ( portTickType ) 100 / portTICK_RATE_MS )\r
+\r
+/* The period for which mainRESET_LED remain on every reset. */\r
+#define mainRESET_LED_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS )\r
+\r
+/* The LED that is toggled whenever a character is transmitted.\r
+mainCOMM_TX_RX_LED + 1 will be toggled every time a character is received. */\r
+#define mainCOMM_TX_RX_LED ( ( unsigned portBASE_TYPE ) 2 )\r
+\r
+/* The LED that is flashed by the check task at a rate that indicates the \r
+error status. */\r
+#define mainCHECK_TASK_LED ( ( unsigned portBASE_TYPE ) 1 )\r
+\r
+/* The LED that is flashed once upon every reset. */\r
+#define mainRESET_LED ( ( unsigned portBASE_TYPE ) 0 )\r
+\r
+/* Constants required for the communications. */\r
+#define mainCOMMS_QUEUE_LENGTH ( ( unsigned portBASE_TYPE ) 5 )\r
+#define mainBAUD_RATE ( ( unsigned portLONG ) 57600 )\r
+/*-----------------------------------------------------------*/\r
+\r
+/* \r
+ * Task function which periodically checks the other tasks for errors. Flashes\r
+ * an LED at a rate that indicates whether an error has ever been detected. \r
+ */\r
+static void vErrorChecks( void *pvParameters );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Creates the tasks, then starts the scheduler. */\r
+void main( void )\r
+{\r
+ /* Initialise the required hardware. */\r
+ vParTestInitialise();\r
+\r
+ /* Initialise the block memory allocator. */\r
+ vPortInitialiseBlocks();\r
+\r
+ /* Start the standard comtest tasks as defined in demo/common/minimal. */\r
+ vAltStartComTestTasks( mainCOMM_TEST_PRIORITY, mainBAUD_RATE, mainCOMM_TX_RX_LED );\r
+\r
+ /* Start the standard 32bit calculation task as defined in\r
+ demo/common/minimal. */\r
+ vStartIntegerMathTasks( tskIDLE_PRIORITY );\r
+\r
+ /* Start the check task defined in this file. */\r
+ xTaskCreate( vErrorChecks, ( const portCHAR * const ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
+\r
+ /* Start the scheduler. This will never return. */\r
+ vTaskStartScheduler();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vErrorChecks( void *pvParameters )\r
+{\r
+portTickType xDelayTime = mainNO_ERROR_CHECK_PERIOD;\r
+volatile unsigned portLONG ulDummy = 3UL;\r
+\r
+ /* Toggle the LED so we can see when a reset occurs. */\r
+ vParTestSetLED( mainRESET_LED, pdTRUE );\r
+ vTaskDelay( mainRESET_LED_PERIOD );\r
+ vParTestSetLED( mainRESET_LED, pdFALSE );\r
+\r
+ /* Cycle for ever, delaying then checking all the other tasks are still\r
+ operating without error. */\r
+ for( ;; )\r
+ {\r
+ /* Wait until it is time to check the other tasks. */\r
+ vTaskDelay( xDelayTime );\r
+\r
+ /* Perform an integer calculation - just to ensure the registers\r
+ get used. The result is not important. */\r
+ ulDummy *= 3UL;\r
+\r
+ /* Check all the other tasks are running, and running without ever\r
+ having an error. The delay period is lowered if an error is reported,\r
+ causing the LED to flash at a higher rate. */\r
+ if( xAreIntegerMathsTaskStillRunning() == pdFALSE )\r
+ {\r
+ xDelayTime = mainERROR_CHECK_PERIOD;\r
+ }\r
+\r
+ if( xAreComTestTasksStillRunning() == pdFALSE )\r
+ {\r
+ xDelayTime = mainERROR_CHECK_PERIOD;\r
+ }\r
+\r
+ /* Flash the LED for visual feedback. The rate of the flash will \r
+ indicate the health of the system. */\r
+ vParTestToggleLED( mainCHECK_TASK_LED );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+del rtosdemo.hex\r
+copy rtosdemo1.hex rtosdemo.hex\r
+hex2bin rtosdemo.hex\r
--- /dev/null
+del rtosdemo.hex\r
+copy rtosdemo2.hex rtosdemo.hex\r
+hex2bin rtosdemo.hex\r
--- /dev/null
+del rtosdemo.hex\r
+copy rtosdemo3.hex rtosdemo.hex\r
+hex2bin rtosdemo.hex\r
--- /dev/null
+Unfortunately the project files:\r
+\r
+RTOSDemo1.mcp\r
+RTOSDemo2.mcp\r
+and RTOSDemo3.mcp\r
+\r
+contain absolute paths. I don't know how to get around this, so if somebody knows, let me know!\r
+\r
+Edit the paths in a text editor before use.\r
+\r
+See the PIC port section of www.FreeRTOS.org for more information.\r
+\r
--- /dev/null
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--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+Changes from V1.2.5\r
+\r
+ + Clear overrun errors in the Rx ISR. Overrun errors prevent any further\r
+ characters being received.\r
+\r
+Changes from V2.0.0\r
+\r
+ + Use portTickType in place of unsigned pdLONG for delay periods.\r
+ + cQueueReieveFromISR() used in place of xQueueReceive() in ISR.\r
+*/\r
+\r
+/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER. */\r
+\r
+/* Scheduler header files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "serial.h"\r
+#include "queue.h"\r
+\r
+/*\r
+ * Prototypes for ISR's. The PIC architecture means that these functions\r
+ * have to be called from port.c. The prototypes are not however included\r
+ * in the header as the header is common to all ports.\r
+ */\r
+void vSerialTxISR( void );\r
+void vSerialRxISR( void );\r
+\r
+/* Hardware pin definitions. */\r
+#define serTX_PIN TRISCbits.TRISC6\r
+#define serRX_PIN TRISCbits.TRISC7\r
+\r
+/* Bit/register definitions. */\r
+#define serINPUT ( 1 )\r
+#define serOUTPUT ( 0 )\r
+#define serTX_ENABLE ( ( unsigned portSHORT ) 1 )\r
+#define serRX_ENABLE ( ( unsigned portSHORT ) 1 )\r
+#define serHIGH_SPEED ( ( unsigned portSHORT ) 1 )\r
+#define serCONTINUOUS_RX ( ( unsigned portSHORT ) 1 )\r
+#define serCLEAR_OVERRUN ( ( unsigned portSHORT ) 0 )\r
+#define serINTERRUPT_ENABLED ( ( unsigned portSHORT ) 1 )\r
+#define serINTERRUPT_DISABLED ( ( unsigned portSHORT ) 0 )\r
+\r
+/* All ISR's use the PIC18 low priority interrupt. */\r
+#define serLOW_PRIORITY ( 0 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Queues to interface between comms API and interrupt routines. */\r
+static xQueueHandle xRxedChars; \r
+static xQueueHandle xCharsForTx;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )\r
+{\r
+unsigned portLONG ulBaud;\r
+\r
+ /* Calculate the baud rate generator constant.\r
+ SPBRG = ( (FOSC / Desired Baud Rate) / 16 ) - 1 */\r
+ ulBaud = configCPU_CLOCK_HZ / ulWantedBaud;\r
+ ulBaud /= ( unsigned portLONG ) 16;\r
+ ulBaud -= ( unsigned portLONG ) 1;\r
+\r
+ /* Create the queues used by the ISR's to interface to tasks. */\r
+ xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( portCHAR ) );\r
+ xCharsForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( portCHAR ) );\r
+\r
+ portENTER_CRITICAL();\r
+ {\r
+ /* Start with config registers cleared, so we can just set the wanted\r
+ bits. */\r
+ TXSTA = ( unsigned portSHORT ) 0;\r
+ RCSTA = ( unsigned portSHORT ) 0;\r
+\r
+ /* Set the baud rate generator using the above calculated constant. */\r
+ SPBRG = ( unsigned portCHAR ) ulBaud;\r
+\r
+ /* Setup the IO pins to enable the USART IO. */\r
+ serTX_PIN = serOUTPUT;\r
+ serRX_PIN = serINPUT;\r
+\r
+ /* Set the serial interrupts to use the same priority as the tick. */\r
+ IPR1bits.TXIP = serLOW_PRIORITY;\r
+ IPR1bits.RCIP = serLOW_PRIORITY;\r
+\r
+ /* Setup Tx configuration. */\r
+ TXSTAbits.BRGH = serHIGH_SPEED;\r
+ TXSTAbits.TXEN = serTX_ENABLE;\r
+\r
+ /* Setup Rx configuration. */\r
+ RCSTAbits.SPEN = serRX_ENABLE;\r
+ RCSTAbits.CREN = serCONTINUOUS_RX;\r
+\r
+ /* Enable the Rx interrupt now, the Tx interrupt will get enabled when\r
+ we have data to send. */\r
+ PIE1bits.RCIE = serINTERRUPT_ENABLED;\r
+ }\r
+ portEXIT_CRITICAL();\r
+\r
+ /* Unlike other ports, this serial code does not allow for more than one\r
+ com port. We therefore don't return a pointer to a port structure and \r
+ can instead just return NULL. */\r
+ return NULL;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+xComPortHandle xSerialPortInit( eCOMPort ePort, eBaud eWantedBaud, eParity eWantedParity, eDataBits eWantedDataBits, eStopBits eWantedStopBits, unsigned portBASE_TYPE uxBufferLength )\r
+{\r
+ /* This is not implemented in this port.\r
+ Use xSerialPortInitMinimal() instead. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )\r
+{\r
+ /* Get the next character from the buffer. Return false if no characters\r
+ are available, or arrive before xBlockTime expires. */\r
+ if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )\r
+ {\r
+ return pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ return pdFALSE;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )\r
+{\r
+ /* Return false if after the block time there is no room on the Tx queue. */\r
+ if( xQueueSend( xCharsForTx, ( const void * ) &cOutChar, xBlockTime ) != pdPASS )\r
+ {\r
+ return pdFAIL;\r
+ }\r
+\r
+ /* Turn interrupt on - ensure the compiler only generates a single \r
+ instruction for this. */\r
+ PIE1bits.TXIE = serINTERRUPT_ENABLED;\r
+\r
+ return pdPASS;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSerialClose( xComPortHandle xPort )\r
+{\r
+ /* Not implemented for this port.\r
+ To implement, turn off the interrupts and delete the memory\r
+ allocated to the queues. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#pragma interruptlow vSerialRxISR save=PRODH, PRODL, TABLAT, section(".tmpdata")\r
+void vSerialRxISR( void )\r
+{\r
+portCHAR cChar;\r
+\r
+ /* Get the character and post it on the queue of Rxed characters.\r
+ If the post causes a task to wake force a context switch as the woken task\r
+ may have a higher priority than the task we have interrupted. */\r
+ cChar = RCREG;\r
+\r
+ /* Clear any overrun errors. */\r
+ if( RCSTAbits.OERR )\r
+ {\r
+ RCSTAbits.CREN = serCLEAR_OVERRUN;\r
+ RCSTAbits.CREN = serCONTINUOUS_RX; \r
+ }\r
+\r
+ if( xQueueSendFromISR( xRxedChars, ( const void * ) &cChar, pdFALSE ) )\r
+ {\r
+ taskYIELD();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#pragma interruptlow vSerialTxISR save=PRODH, PRODL, TABLAT, section(".tmpdata")\r
+void vSerialTxISR( void )\r
+{\r
+portCHAR cChar, cTaskWoken;\r
+\r
+ if( xQueueReceiveFromISR( xCharsForTx, &cChar, &cTaskWoken ) == pdTRUE )\r
+ {\r
+ /* Send the next character queued for Tx. */\r
+ TXREG = cChar;\r
+ }\r
+ else\r
+ {\r
+ /* Queue empty, nothing to send. */\r
+ PIE1bits.TXIE = serINTERRUPT_DISABLED;\r
+ }\r
+}\r
+\r
+\r
+\r
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+Files3=C:\Documents and Settings\marcel\My Documents\pic\FreeRTOS\FreeRTOS\Demo\PIC18_WizC\Demo1\Demo1.rep\r
+Files4=C:\Documents and Settings\marcel\My Documents\pic\FreeRTOS\FreeRTOS\Demo\PIC18_WizC\Demo1\interrupt.c\r
+MRU3=C:\PROGRAM FILES\FED\PIXIE\Libs\LibsUser\LIBFREERTOS\Modules\Tasks.c\r
+MRU4=C:\Documents and Settings\marcel\My Documents\pic\FreeRTOS\FreeRTOS\Demo\PIC18_WizC\Demo1\interrupt.c\r
+Files5=C:\PROGRAM FILES\FED\PIXIE\Libs\LibsUser\LIBFREERTOS\Modules\Tasks.c\r
+Files6=C:\Documents and Settings\marcel\My Documents\pic\FreeRTOS\FreeRTOS\Demo\PIC18_WizC\Demo1\fuses.c\r
+MRU5=C:\Program Files\FED\PIXIE\Libs\LibCore\Bit16.asm\r
+MRU6=C:\Documents and Settings\marcel\My Documents\pic\FreeRTOS\FreeRTOS\Demo\PIC18_WizC\Demo1\fuses.c\r
+MRU7=C:\Program Files\FED\PIXIE\Libs\LibsUser\libFreeRTOS\Include\portmacro.h\r
+MRU8=C:\Documents and Settings\marcel\My Documents\pic\FreeRTOS\FreeRTOS\Demo\PIC18_WizC\Demo1\FreeRTOSConfig.h\r
+[PinConnections]\r
+nPins=0\r
+[AssCode]\r
+ProcType=18F4620\r
+[Information]\r
+Column0=-1\r
+Column1=8\r
+Column2=4\r
+Column3=16\r
+Column4=-1\r
+Column5=50\r
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+Width=339\r
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+[F16904974]\r
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+y=0\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+Changes from V3.0.0\r
+ + TickRate reduced to 250Hz.\r
+\r
+ + configIDLE_SHOULD_YIELD added.\r
+\r
+Changes from V3.0.1\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. \r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION ( 1 )\r
+#define configUSE_IDLE_HOOK ( 0 )\r
+#define configUSE_TICK_HOOK ( 0 )\r
+#define configTICK_RATE_HZ ( 250 )\r
+#define configMAX_PRIORITIES ( 1 )\r
+#define configMINIMAL_STACK_SIZE portMINIMAL_STACK_SIZE\r
+#define configMAX_TASK_NAME_LEN ( 3 )\r
+#define configUSE_TRACE_FACILITY ( 0 )\r
+#define configUSE_16_BIT_TICKS ( 1 )\r
+#define configIDLE_SHOULD_YIELD ( 1 )\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Set the following definitions to 1 to include the component, or zero\r
+to exclude the component. */\r
+\r
+/* Include/exclude the stated API function. */\r
+#define INCLUDE_vTaskPrioritySet ( 0 )\r
+#define INCLUDE_uxTaskPriorityGet ( 0 )\r
+#define INCLUDE_vTaskDelete ( 0 )\r
+#define INCLUDE_vTaskCleanUpResources ( 0 )\r
+#define INCLUDE_vTaskSuspend ( 0 )\r
+#define INCLUDE_vTaskDelayUntil ( 1 )\r
+#define INCLUDE_vTaskDelay ( 0 )\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+#ifndef _MALLOC_SETTINGS_H\r
+#define _MALLOC_SETTINGS_H\r
+/*********************************************************************\r
+** Title: Dynamic memory (de-)allocation library for wizC.\r
+**\r
+** Author: Marcel van Lieshout\r
+**\r
+** Copyright: (c) 2005, HMCS, Marcel van Lieshout\r
+**\r
+** License: This software is released to the public domain and comes\r
+** without warranty and/or guarantees of any kind. You have\r
+** the right to use, copy, modify and/or (re-)distribute the\r
+** software as long as the reference to the author is\r
+** maintained in the software and a reference to the author\r
+** is included in any documentation of each product in which\r
+** this library (in it's original or in a modified form)\r
+** is used.\r
+*********************************************************************/\r
+\r
+/*********************************************************************\r
+** The model to use\r
+*********************************************************************/\r
+//#define MALLOC_SMALL\r
+#define MALLOC_LARGE\r
+\r
+/*********************************************************************\r
+** The size of the heap\r
+*********************************************************************/\r
+#define MALLOC_HEAP_SIZE (3200)\r
+\r
+/*********************************************************************\r
+** Should released memory be scribbled with 0x55 before releasing it?\r
+*********************************************************************/\r
+//#define MALLOC_SCRIBBLE\r
+\r
+/********************************************************************\r
+** Enable Debug-mode?\r
+*********************************************************************/\r
+//#define MALLOC_DEBUG\r
+\r
+#endif /* _MALLOC_SETTINGS_H */\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+Changes from V3.0.0\r
+ + Several modules predefined to avoid linker problems\r
+\r
+Changes from V3.0.1\r
+*/\r
+\r
+#ifndef _memcpy\r
+ #define _memcpy 1\r
+#endif\r
+\r
+#ifndef _memset\r
+ #define _memset 1\r
+#endif\r
+\r
+#ifndef _strncpy\r
+ #define _strncpy 1\r
+#endif\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+Changes from V3.0.0\r
+\r
+Changes from V3.0.1\r
+*/\r
+\r
+/*\r
+** Here are the configuration words set. See the PIC datasheet\r
+** and the wizC manual for an explanation\r
+*/\r
+#include <pic.h>\r
+\r
+/*\r
+** These fuses are for PIC18F4620\r
+*/\r
+#pragma __config _CONFIG1H,_IESO_OFF_1H & _FCMEN_OFF_1H & _OSC_HSPLL_1H\r
+#pragma __config _CONFIG2L,_BORV_21_2L & _BOREN_SBORDIS_2L & _PWRT_ON_2L\r
+#pragma __config _CONFIG2H,_WDTPS_32768_2H & _WDT_OFF_2H\r
+#pragma __config _CONFIG3H,_MCLRE_ON_3H & _LPT1OSC_OFF_3H & _PBADEN_OFF_3H & _CCP2MX_PORTC_3H\r
+#pragma __config _CONFIG4L,_DEBUG_OFF_4L & _XINST_OFF_4L & _LVP_OFF_4L & _STVREN_OFF_4L\r
+#pragma __config _CONFIG5L,_CP3_OFF_5L & _CP2_OFF_5L & _CP1_OFF_5L & _CP0_OFF_5L\r
+#pragma __config _CONFIG5H,_CPD_OFF_5H & _CPB_OFF_5H\r
+#pragma __config _CONFIG6L,_WRT3_OFF_6L & _WRT2_OFF_6L & _WRT1_OFF_6L & _WRT0_OFF_6L\r
+#pragma __config _CONFIG6H,_WRTD_OFF_6H & _WRTB_OFF_6H & _WRTC_OFF_6H\r
+#pragma __config _CONFIG7L,_EBTR3_OFF_7L & _EBTR2_OFF_7L & _EBTR1_OFF_7L & _EBTR0_OFF_7L\r
+#pragma __config _CONFIG7H,_EBTRB_OFF_7H\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* \r
+Changes from V3.0.0\r
+ + Added functionality to only call vTaskSwitchContext() once\r
+ when handling multiple interruptsources in a single interruptcall.\r
+\r
+ + Included Filenames changed to a .c extension to allow stepping through\r
+ code using F7.\r
+\r
+Changes from V3.0.1\r
+*/\r
+\r
+#include <pic.h>\r
+\r
+/* Scheduler include files. */\r
+#include <FreeRTOS.h>\r
+#include <task.h>\r
+#include <queue.h>\r
+\r
+static bit uxSwitchRequested;\r
+\r
+/*\r
+ * Vector for the ISR.\r
+ */\r
+void pointed Interrupt()\r
+{\r
+ /*\r
+ * Save the context of the current task.\r
+ */\r
+ portSAVE_CONTEXT( portINTERRUPTS_FORCED );\r
+\r
+ /*\r
+ * No contextswitch requested yet\r
+ */\r
+ uxSwitchRequested = pdFALSE;\r
+ \r
+ /*\r
+ * Was the interrupt the FreeRTOS SystemTick?\r
+ */\r
+ #include <libFreeRTOS/Drivers/Tick/isrTick.c>\r
+\r
+/*******************************************************************************\r
+** DO NOT MODIFY ANYTHING ABOVE THIS LINE\r
+********************************************************************************\r
+** Enter the includes for the ISR-code of the FreeRTOS drivers below.\r
+**\r
+** You cannot use local variables. Alternatives are:\r
+** - Use static variables (Global RAM usage increases)\r
+** - Call a function (Additional cycles are needed)\r
+** - Use unused SFR's (preferred, no additional overhead)\r
+** See "../Serial/isrSerialTx.c" for an example of this last option\r
+*******************************************************************************/\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+/*******************************************************************************\r
+** DO NOT MODIFY ANYTHING BELOW THIS LINE\r
+*******************************************************************************/\r
+ /*\r
+ * Was a contextswitch requested by one of the\r
+ * interrupthandlers?\r
+ */\r
+ if ( uxSwitchRequested )\r
+ {\r
+ vTaskSwitchContext();\r
+ }\r
+ \r
+ /*\r
+ * Restore the context of the (possibly other) task.\r
+ */\r
+ portRESTORE_CONTEXT();\r
+\r
+ #pragma asmline retfie 0\r
+}\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+Changes from V3.0.0\r
+\r
+Changes from V3.0.1\r
+*/\r
+\r
+/*\r
+ * Instead of the normal single demo application, the PIC18F demo is split \r
+ * into several smaller programs of which this is the first. This enables the \r
+ * demo's to be executed on the RAM limited PIC-devices.\r
+ *\r
+ * The Demo1 project is configured for a PIC18F4620 device. Main.c starts 9 \r
+ * tasks (including the idle task).\r
+\r
+ * This first demo is included to do a quick check on the FreeRTOS\r
+ * installation. It is also included to demonstrate a minimal project-setup\r
+ * to use FreeRTOS in a wizC environment.\r
+ *\r
+ * Eight independant tasks are created. All tasks share the same taskcode.\r
+ * Each task blinks a different led on portB. The blinkrate for each task\r
+ * is different, but chosen in such a way that portB will show a binary\r
+ * counter pattern. All blinkrates are derived from a single master-rate.\r
+ * By default, this masterrate is set to 100 milliseconds. Although such\r
+ * a low value will make it almost impossible to see some of the leds\r
+ * actually blink, it is a good value when using the wizC-simulator.\r
+ * When testing on a real chip, changing the value to eg. 500 milliseconds\r
+ * would be appropiate.\r
+ */\r
+ \r
+/* Scheduler include files. */\r
+#include <FreeRTOS.h>\r
+#include <task.h>\r
+\r
+#define mainBLINK_LED_INTERVAL ( ( portTickType ) 100 / ( portTICK_RATE_MS ) )\r
+\r
+/* The LED that is flashed by the B0 task. */\r
+#define mainBLINK_LED0_PORT LATD\r
+#define mainBLINK_LED0_TRIS TRISD\r
+#define mainBLINK_LED0_PIN 0\r
+#define mainBLINK_LED0_INTERVAL ((mainBLINK_LED_INTERVAL) << (mainBLINK_LED0_PIN))\r
+\r
+/* The LED that is flashed by the B1 task. */\r
+#define mainBLINK_LED1_PORT LATD\r
+#define mainBLINK_LED1_TRIS TRISD\r
+#define mainBLINK_LED1_PIN 1\r
+#define mainBLINK_LED1_INTERVAL ((mainBLINK_LED_INTERVAL) << (mainBLINK_LED1_PIN))\r
+\r
+/* The LED that is flashed by the B2 task. */\r
+#define mainBLINK_LED2_PORT LATD\r
+#define mainBLINK_LED2_TRIS TRISD\r
+#define mainBLINK_LED2_PIN 2\r
+#define mainBLINK_LED2_INTERVAL ((mainBLINK_LED_INTERVAL) << (mainBLINK_LED2_PIN))\r
+\r
+/* The LED that is flashed by the B3 task. */\r
+#define mainBLINK_LED3_PORT LATD\r
+#define mainBLINK_LED3_TRIS TRISD\r
+#define mainBLINK_LED3_PIN 3\r
+#define mainBLINK_LED3_INTERVAL ((mainBLINK_LED_INTERVAL) << (mainBLINK_LED3_PIN))\r
+\r
+/* The LED that is flashed by the B4 task. */\r
+#define mainBLINK_LED4_PORT LATD\r
+#define mainBLINK_LED4_TRIS TRISD\r
+#define mainBLINK_LED4_PIN 4\r
+#define mainBLINK_LED4_INTERVAL ((mainBLINK_LED_INTERVAL) << (mainBLINK_LED4_PIN))\r
+\r
+/* The LED that is flashed by the B5 task. */\r
+#define mainBLINK_LED5_PORT LATD\r
+#define mainBLINK_LED5_TRIS TRISD\r
+#define mainBLINK_LED5_PIN 5\r
+#define mainBLINK_LED5_INTERVAL ((mainBLINK_LED_INTERVAL) << (mainBLINK_LED5_PIN))\r
+\r
+/* The LED that is flashed by the B6 task. */\r
+#define mainBLINK_LED6_PORT LATD\r
+#define mainBLINK_LED6_TRIS TRISD\r
+#define mainBLINK_LED6_PIN 6\r
+#define mainBLINK_LED6_INTERVAL ((mainBLINK_LED_INTERVAL) << (mainBLINK_LED6_PIN))\r
+\r
+/* The LED that is flashed by the B7 task. */\r
+#define mainBLINK_LED7_PORT LATD\r
+#define mainBLINK_LED7_TRIS TRISD\r
+#define mainBLINK_LED7_PIN 7\r
+#define mainBLINK_LED7_INTERVAL ((mainBLINK_LED_INTERVAL) << (mainBLINK_LED7_PIN))\r
+\r
+typedef struct {\r
+ unsigned char *port;\r
+ unsigned char *tris;\r
+ unsigned char pin;\r
+ portTickType interval;\r
+} SBLINK;\r
+\r
+const SBLINK sled0 = {&mainBLINK_LED0_PORT, &mainBLINK_LED0_TRIS, mainBLINK_LED0_PIN, mainBLINK_LED0_INTERVAL};\r
+const SBLINK sled1 = {&mainBLINK_LED1_PORT, &mainBLINK_LED1_TRIS, mainBLINK_LED1_PIN, mainBLINK_LED1_INTERVAL};\r
+const SBLINK sled2 = {&mainBLINK_LED2_PORT, &mainBLINK_LED2_TRIS, mainBLINK_LED2_PIN, mainBLINK_LED2_INTERVAL};\r
+const SBLINK sled3 = {&mainBLINK_LED3_PORT, &mainBLINK_LED3_TRIS, mainBLINK_LED3_PIN, mainBLINK_LED3_INTERVAL};\r
+const SBLINK sled4 = {&mainBLINK_LED4_PORT, &mainBLINK_LED4_TRIS, mainBLINK_LED4_PIN, mainBLINK_LED4_INTERVAL};\r
+const SBLINK sled5 = {&mainBLINK_LED5_PORT, &mainBLINK_LED5_TRIS, mainBLINK_LED5_PIN, mainBLINK_LED5_INTERVAL};\r
+const SBLINK sled6 = {&mainBLINK_LED6_PORT, &mainBLINK_LED6_TRIS, mainBLINK_LED6_PIN, mainBLINK_LED6_INTERVAL};\r
+const SBLINK sled7 = {&mainBLINK_LED7_PORT, &mainBLINK_LED7_TRIS, mainBLINK_LED7_PIN, mainBLINK_LED7_INTERVAL};\r
+\r
+/*\r
+ * The task code for the "vBlink" task.\r
+ */\r
+static portTASK_FUNCTION_PROTO(vBlink, pvParameters);\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Creates the tasks, then starts the scheduler.\r
+ */\r
+void main( void )\r
+{\r
+ /*\r
+ * Start the blink tasks defined in this file.\r
+ */\r
+ xTaskCreate( vBlink, "B0", configMINIMAL_STACK_SIZE, &sled0, tskIDLE_PRIORITY, NULL );\r
+ xTaskCreate( vBlink, "B1", configMINIMAL_STACK_SIZE, &sled1, tskIDLE_PRIORITY, NULL );\r
+ xTaskCreate( vBlink, "B2", configMINIMAL_STACK_SIZE, &sled2, tskIDLE_PRIORITY, NULL );\r
+ xTaskCreate( vBlink, "B3", configMINIMAL_STACK_SIZE, &sled3, tskIDLE_PRIORITY, NULL );\r
+ xTaskCreate( vBlink, "B4", configMINIMAL_STACK_SIZE, &sled4, tskIDLE_PRIORITY, NULL );\r
+ xTaskCreate( vBlink, "B5", configMINIMAL_STACK_SIZE, &sled5, tskIDLE_PRIORITY, NULL );\r
+ xTaskCreate( vBlink, "B6", configMINIMAL_STACK_SIZE, &sled6, tskIDLE_PRIORITY, NULL );\r
+ xTaskCreate( vBlink, "B7", configMINIMAL_STACK_SIZE, &sled7, tskIDLE_PRIORITY, NULL );\r
+\r
+ /*\r
+ * Start the scheduler.\r
+ */\r
+ vTaskStartScheduler( );\r
+ \r
+ while(1) /* This point should never be reached. */\r
+ {\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portTASK_FUNCTION(vBlink, pvParameters)\r
+{\r
+ unsigned char *Port = ((SBLINK *)pvParameters)->port;\r
+ unsigned char *Tris = ((SBLINK *)pvParameters)->tris;\r
+ unsigned char Pin = ((SBLINK *)pvParameters)->pin;\r
+ portTickType Interval = ((SBLINK *)pvParameters)->interval;\r
+ \r
+ portTickType xLastWakeTime;\r
+\r
+ /*\r
+ * Initialize the hardware\r
+ */\r
+ *Tris &= ~(1<<Pin); // Set the pin that is used by this task to ouput\r
+ *Port &= ~(1<<Pin); // Drive the pin low\r
+ \r
+ /*\r
+ * Initialise the xLastWakeTime variable with the current time.\r
+ */\r
+ xLastWakeTime = xTaskGetTickCount();\r
+\r
+ /*\r
+ * Cycle for ever, delaying then toggle the LED.\r
+ */\r
+ for( ;; )\r
+ {\r
+ /*\r
+ * Wait until it is time to toggle\r
+ */\r
+ vTaskDelayUntil( &xLastWakeTime, Interval );\r
+\r
+ /*\r
+ * Toggle the LED for visual feedback.\r
+ */\r
+ *Port ^= 1<<Pin;\r
+ }\r
+}\r
--- /dev/null
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--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*\r
+Changes from V3.0.0\r
+ + TickRate reduced to 250Hz.\r
+\r
+ + configIDLE_SHOULD_YIELD added.\r
+\r
+Changes from V3.0.1\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. \r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION ( 1 )\r
+#define configUSE_IDLE_HOOK ( 0 )\r
+#define configUSE_TICK_HOOK ( 0 )\r
+#define configTICK_RATE_HZ ( 250 )\r
+#define configMAX_PRIORITIES ( 4 )\r
+#define configMINIMAL_STACK_SIZE portMINIMAL_STACK_SIZE\r
+#define configMAX_TASK_NAME_LEN ( 3 )\r
+#define configUSE_TRACE_FACILITY ( 0 )\r
+#define configUSE_16_BIT_TICKS ( 1 )\r
+#define configIDLE_SHOULD_YIELD ( 1 )\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Set the following definitions to 1 to include the component, or zero\r
+to exclude the component. */\r
+\r
+/* Include/exclude the stated API function. */\r
+#define INCLUDE_vTaskPrioritySet ( 0 )\r
+#define INCLUDE_uxTaskPriorityGet ( 0 )\r
+#define INCLUDE_vTaskDelete ( 0 )\r
+#define INCLUDE_vTaskCleanUpResources ( 0 )\r
+#define INCLUDE_vTaskSuspend ( 0 )\r
+#define INCLUDE_vTaskDelayUntil ( 1 )\r
+#define INCLUDE_vTaskDelay ( 1 )\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+#ifndef _MALLOC_SETTINGS_H\r
+#define _MALLOC_SETTINGS_H\r
+/*********************************************************************\r
+** Title: Dynamic memory (de-)allocation library for wizC.\r
+**\r
+** Author: Marcel van Lieshout\r
+**\r
+** Copyright: (c) 2005, HMCS, Marcel van Lieshout\r
+**\r
+** License: This software is released to the public domain and comes\r
+** without warranty and/or guarantees of any kind. You have\r
+** the right to use, copy, modify and/or (re-)distribute the\r
+** software as long as the reference to the author is\r
+** maintained in the software and a reference to the author\r
+** is included in any documentation of each product in which\r
+** this library (in it's original or in a modified form)\r
+** is used.\r
+*********************************************************************/\r
+\r
+/*********************************************************************\r
+** The model to use\r
+*********************************************************************/\r
+//#define MALLOC_SMALL\r
+#define MALLOC_LARGE\r
+\r
+/*********************************************************************\r
+** The size of the heap\r
+*********************************************************************/\r
+#define MALLOC_HEAP_SIZE (3200)\r
+\r
+/*********************************************************************\r
+** Should released memory be scribbled with 0x55 before releasing it?\r
+*********************************************************************/\r
+//#define MALLOC_SCRIBBLE\r
+\r
+/********************************************************************\r
+** Enable Debug-mode?\r
+*********************************************************************/\r
+//#define MALLOC_DEBUG\r
+\r
+#endif /* _MALLOC_SETTINGS_H */\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+Changes from V3.0.0\r
+ + Several modules predefined to avoid linker problems\r
+\r
+Changes from V3.0.1\r
+*/\r
+\r
+#ifndef _memcpy\r
+ #define _memcpy 1\r
+#endif\r
+\r
+#ifndef _memset\r
+ #define _memset 1\r
+#endif\r
+\r
+#ifndef _strncpy\r
+ #define _strncpy 1\r
+#endif\r
+\r
+\r
+#pragma wizcpp searchpath <../../Common/Include/>\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+Changes from V3.0.0\r
+\r
+Changes from V3.0.1\r
+*/\r
+\r
+/*\r
+** Here are the configuration words set. See the PIC datasheet\r
+** and the wizC manual for an explanation\r
+*/\r
+#include <pic.h>\r
+\r
+/*\r
+** These fuses are for PIC18F4620\r
+*/\r
+#pragma __config _CONFIG1H,_IESO_OFF_1H & _FCMEN_OFF_1H & _OSC_HSPLL_1H\r
+#pragma __config _CONFIG2L,_BORV_21_2L & _BOREN_SBORDIS_2L & _PWRT_ON_2L\r
+#pragma __config _CONFIG2H,_WDTPS_32768_2H & _WDT_OFF_2H\r
+#pragma __config _CONFIG3H,_MCLRE_ON_3H & _LPT1OSC_OFF_3H & _PBADEN_OFF_3H & _CCP2MX_PORTC_3H\r
+#pragma __config _CONFIG4L,_DEBUG_OFF_4L & _XINST_OFF_4L & _LVP_OFF_4L & _STVREN_OFF_4L\r
+#pragma __config _CONFIG5L,_CP3_OFF_5L & _CP2_OFF_5L & _CP1_OFF_5L & _CP0_OFF_5L\r
+#pragma __config _CONFIG5H,_CPD_OFF_5H & _CPB_OFF_5H\r
+#pragma __config _CONFIG6L,_WRT3_OFF_6L & _WRT2_OFF_6L & _WRT1_OFF_6L & _WRT0_OFF_6L\r
+#pragma __config _CONFIG6H,_WRTD_OFF_6H & _WRTB_OFF_6H & _WRTC_OFF_6H\r
+#pragma __config _CONFIG7L,_EBTR3_OFF_7L & _EBTR2_OFF_7L & _EBTR1_OFF_7L & _EBTR0_OFF_7L\r
+#pragma __config _CONFIG7H,_EBTRB_OFF_7H\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* \r
+Changes from V3.0.0\r
+ + Added functionality to only call vTaskSwitchContext() once\r
+ when handling multiple interruptsources in a single interruptcall.\r
+\r
+ + Included Filenames changed to a .c extension to allow stepping through\r
+ code using F7.\r
+\r
+Changes from V3.0.1\r
+*/\r
+\r
+#include <pic.h>\r
+\r
+/* Scheduler include files. */\r
+#include <FreeRTOS.h>\r
+#include <task.h>\r
+#include <queue.h>\r
+\r
+static bit uxSwitchRequested;\r
+\r
+/*\r
+ * Vector for the ISR.\r
+ */\r
+void pointed Interrupt()\r
+{\r
+ /*\r
+ * Save the context of the current task.\r
+ */\r
+ portSAVE_CONTEXT( portINTERRUPTS_FORCED );\r
+\r
+ /*\r
+ * No contextswitch requested yet\r
+ */\r
+ uxSwitchRequested = pdFALSE;\r
+ \r
+ /*\r
+ * Was the interrupt the FreeRTOS SystemTick?\r
+ */\r
+ #include <libFreeRTOS/Drivers/Tick/isrTick.c>\r
+\r
+/*******************************************************************************\r
+** DO NOT MODIFY ANYTHING ABOVE THIS LINE\r
+********************************************************************************\r
+** Enter the includes for the ISR-code of the FreeRTOS drivers below.\r
+**\r
+** You cannot use local variables. Alternatives are:\r
+** - Use static variables (Global RAM usage increases)\r
+** - Call a function (Additional cycles are needed)\r
+** - Use unused SFR's (preferred, no additional overhead)\r
+** See "../Serial/isrSerialTx.c" for an example of this last option\r
+*******************************************************************************/\r
+\r
+\r
+\r
+ /*\r
+ * Was the interrupt a byte being received?\r
+ */\r
+ #include "../Serial/isrSerialRx.c"\r
+\r
+\r
+ /*\r
+ * Was the interrupt the Tx register becoming empty?\r
+ */\r
+ #include "../Serial/isrSerialTx.c"\r
+\r
+\r
+\r
+/*******************************************************************************\r
+** DO NOT MODIFY ANYTHING BELOW THIS LINE\r
+*******************************************************************************/\r
+ /*\r
+ * Was a contextswitch requested by one of the\r
+ * interrupthandlers?\r
+ */\r
+ if ( uxSwitchRequested )\r
+ {\r
+ vTaskSwitchContext();\r
+ }\r
+ \r
+ /*\r
+ * Restore the context of the (possibly other) task.\r
+ */\r
+ portRESTORE_CONTEXT();\r
+\r
+ #pragma asmline retfie 0\r
+}\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+Changes from V3.0.0\r
+\r
+Changes from V3.0.1\r
+*/\r
+\r
+/*\r
+ * Instead of the normal single demo application, the PIC18F demo is split \r
+ * into several smaller programs of which this is the second. This enables the \r
+ * demo's to be executed on the RAM limited PIC-devices.\r
+ *\r
+ * The Demo2 project is configured for a PIC18F4620 device. Main.c starts 12 \r
+ * tasks (including the idle task). See the indicated files in the demo/common\r
+ * directory for more information.\r
+ *\r
+ * demo/common/minimal/integer.c: Creates 1 task\r
+ * demo/common/minimal/PollQ.c: Creates 2 tasks\r
+ * demo/common/minimal/semtest.c: Creates 4 tasks\r
+ * demo/common/minimal/flash.c: Creates 3 tasks\r
+ *\r
+ * Main.c also creates a check task. This periodically checks that all the \r
+ * other tasks are still running and have not experienced any unexpected \r
+ * results. If all the other tasks are executing correctly an LED is flashed \r
+ * once every mainCHECK_PERIOD milliseconds. If any of the tasks have not \r
+ * executed, or report an error, the frequency of the LED flash will increase \r
+ * to mainERROR_FLASH_RATE.\r
+ *\r
+ * On entry to main an 'X' is transmitted. Monitoring the serial port using a\r
+ * dumb terminal allows for verification that the device is not continuously \r
+ * being reset (no more than one 'X' should be transmitted).\r
+ *\r
+ * http://www.FreeRTOS.org contains important information on the use of the \r
+ * wizC PIC18F port.\r
+ */\r
+\r
+/* Scheduler include files. */\r
+#include <FreeRTOS.h>\r
+#include <task.h>\r
+\r
+/* Demo app include files. */\r
+#include "integer.h"\r
+#include "pollq.h"\r
+#include "semtest.h"\r
+#include "flash.h"\r
+#include "partest.h"\r
+#include "serial.h"\r
+\r
+/* The period between executions of the check task before and after an error\r
+has been discovered. If an error has been discovered the check task runs\r
+more frequently - increasing the LED flash rate. */\r
+#define mainNO_ERROR_CHECK_PERIOD ( ( portTickType ) 10000 / portTICK_RATE_MS )\r
+#define mainERROR_CHECK_PERIOD ( ( portTickType ) 1000 / portTICK_RATE_MS )\r
+#define mainCHECK_TASK_LED ( ( unsigned portCHAR ) 3 )\r
+\r
+/* Priority definitions for some of the tasks. Other tasks just use the idle\r
+priority. */\r
+#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 3 )\r
+#define mainLED_FLASH_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 2 )\r
+#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 1 )\r
+#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 1 )\r
+#define mainINTEGER_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 0 )\r
+\r
+/* Constants required for the communications. Only one character is ever \r
+transmitted. */\r
+#define mainCOMMS_QUEUE_LENGTH ( ( unsigned portCHAR ) 5 )\r
+#define mainNO_BLOCK ( ( portTickType ) 0 )\r
+#define mainBAUD_RATE ( ( unsigned portLONG ) 57600 )\r
+\r
+/*\r
+ * The task function for the "Check" task.\r
+ */\r
+static portTASK_FUNCTION_PROTO( vErrorChecks, pvParameters );\r
+\r
+/*\r
+ * Checks the unique counts of other tasks to ensure they are still operational.\r
+ * Returns pdTRUE if an error is detected, otherwise pdFALSE.\r
+ */\r
+static portCHAR prvCheckOtherTasksAreStillRunning( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Creates the tasks, then starts the scheduler. */\r
+void main( void )\r
+{\r
+ /* Initialise the required hardware. */\r
+ vParTestInitialise();\r
+\r
+ /* Send a character so we have some visible feedback of a reset. */\r
+ xSerialPortInitMinimal( mainBAUD_RATE, mainCOMMS_QUEUE_LENGTH );\r
+ xSerialPutChar( NULL, 'X', mainNO_BLOCK );\r
+\r
+ /* Start a few of the standard demo tasks found in the demo\common directory. */\r
+ vStartIntegerMathTasks( mainINTEGER_PRIORITY);\r
+ vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
+ vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
+ vStartLEDFlashTasks( mainLED_FLASH_PRIORITY );\r
+\r
+ /* Start the check task defined in this file. */\r
+ xTaskCreate( vErrorChecks, ( const portCHAR * const ) "Check", portMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
+\r
+ /* Start the scheduler. Will never return here. */\r
+ vTaskStartScheduler();\r
+\r
+ while(1) /* This point should never be reached. */\r
+ {\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portTASK_FUNCTION( vErrorChecks, pvParameters )\r
+{\r
+portTickType xLastCheckTime;\r
+portTickType xDelayTime = mainNO_ERROR_CHECK_PERIOD;\r
+portCHAR cErrorOccurred;\r
+\r
+ /* We need to initialise xLastCheckTime prior to the first call to \r
+ vTaskDelayUntil(). */\r
+ xLastCheckTime = xTaskGetTickCount();\r
+ \r
+ /* Cycle for ever, delaying then checking all the other tasks are still\r
+ operating without error. */\r
+ for( ;; )\r
+ {\r
+ /* Wait until it is time to check the other tasks again. */\r
+ vTaskDelayUntil( &xLastCheckTime, xDelayTime );\r
+ \r
+ /* Check all the other tasks are running, and running without ever\r
+ having an error. */\r
+ cErrorOccurred = prvCheckOtherTasksAreStillRunning();\r
+\r
+ /* If an error was detected increase the frequency of the LED flash. */\r
+ if( cErrorOccurred == pdTRUE )\r
+ {\r
+ xDelayTime = mainERROR_CHECK_PERIOD;\r
+ }\r
+\r
+ /* Flash the LED for visual feedback. */\r
+ vParTestToggleLED( mainCHECK_TASK_LED );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portCHAR prvCheckOtherTasksAreStillRunning( void )\r
+{\r
+ portCHAR cErrorHasOccurred = ( portCHAR ) pdFALSE;\r
+\r
+ if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ cErrorHasOccurred = ( portCHAR ) pdTRUE;\r
+ }\r
+\r
+ if( xArePollingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ cErrorHasOccurred = ( portCHAR ) pdTRUE;\r
+ }\r
+\r
+ if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ cErrorHasOccurred = ( portCHAR ) pdTRUE;\r
+ }\r
+\r
+ return cErrorHasOccurred;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
--- /dev/null
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+aHeight=191\r
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+[Window2]\r
+aHeight=1000\r
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+Width=177\r
+isMinimised=1\r
+isVisible=1\r
+ShowBorder=1\r
+ShowCaption=1\r
+Sizeable=1\r
+x=462\r
+y=0\r
+Left=152\r
+Top=81\r
+Group=0\r
+Page=4\r
+[Window1]\r
+aHeight=389\r
+aWidth=998\r
+Height=201\r
+Width=329\r
+isMinimised=1\r
+isVisible=1\r
+ShowBorder=1\r
+ShowCaption=1\r
+Sizeable=1\r
+x=0\r
+y=608\r
+Left=0\r
+Top=395\r
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+Page=1\r
+[Window11]\r
+aHeight=335\r
+aWidth=560\r
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+isMinimised=1\r
+isVisible=1\r
+ShowBorder=1\r
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+Sizeable=1\r
+x=436\r
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+[Window0]\r
+aHeight=472\r
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+Sizeable=1\r
+x=438\r
+y=42\r
+Left=219\r
+Top=102\r
+Group=0\r
+Page=1\r
+[APPWIZ]\r
+AProcFreq=4000000\r
+nUserTemp=0\r
+Proc=16F84\r
+Left=-48\r
+Top=-2560\r
+Width=750\r
+Heigth=600\r
+nElem=0\r
+[GLOBAL]\r
+LoadCheck=2\r
+SimulateAll=1\r
+[MainWindow]\r
+WindowState=2\r
+Top=-4\r
+Left=-4\r
+Width=1032\r
+Height=748\r
+Update=25000\r
+StopOnError=1\r
+[FindRep]\r
+nTextFind=0\r
+nTextReplace=0\r
+[EditWindow]\r
+Tab=0\r
+nFiles=1\r
+nMRU=9\r
+MarginOn=1\r
+MarginType=2\r
+WindowState=0\r
+Top=0\r
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+Height=418\r
+Files0=C:\Documents and Settings\marcel\My Documents\pic\FreeRTOS\FreeRTOS\Demo\PIC18_WizC\Demo3\main.c\r
+MRU0=C:\DOCUMENTS AND SETTINGS\marcel\MY DOCUMENTS\pic\FreeRTOS\FreeRTOS\Demo\PIC18_WIZC\Demo3\main.c\r
+Files1=C:\PROGRA~1\FED\PIXIE\Libs\LibCore\Bit16.asm\r
+Files2=C:\Documents and Settings\marcel\My Documents\pic\FreeRTOS\FreeRTOS\Demo\PIC18_WizC\Demo3\Demo3.rep\r
+MRU1=C:\PROGRA~1\FED\PIXIE\Libs\LibCore\Bit16.asm\r
+MRU2=C:\Documents and Settings\marcel\My Documents\pic\FreeRTOS\FreeRTOS\Demo\PIC18_WizC\Demo3\Demo3.rep\r
+Files3=C:\PROGRAM FILES\FED\PIXIE\Libs\LibsUser\LIBFREERTOS\Modules\List.c\r
+Files4=C:\PROGRAM FILES\FED\PIXIE\Libs\LibsUser\LIBFREERTOS\Modules\Queue.c\r
+Files5=C:\DOCUMENTS AND SETTINGS\marcel\MY DOCUMENTS\pic\FreeRTOS\FREERTOS 2005-06-04 01\Demo\PIC18_WIZC\Demo3\main.c\r
+MRU3=C:\PROGRAM FILES\FED\PIXIE\Libs\LibsUser\LIBFREERTOS\Modules\Queue.c\r
+MRU4=C:\DOCUMENTS AND SETTINGS\marcel\MY DOCUMENTS\pic\FreeRTOS\FREERTOS 2005-06-04 01\Demo\PIC18_WIZC\Demo3\INTERRUPT.C\r
+MRU5=C:\Documents and Settings\marcel\My Documents\pic\FreeRTOS\FreeRTOS 2005-06-04 01\Demo\PIC18_WizC\serial\serial.c\r
+MRU6=C:\DOCUMENTS AND SETTINGS\marcel\MY DOCUMENTS\pic\FreeRTOS\FREERTOS 2005-06-04 01\Demo\PIC18_WIZC\Demo3\main.c\r
+MRU7=C:\Documents and Settings\marcel\My Documents\pic\FreeRTOS\FreeRTOS 2005-06-04 01\Demo\PIC18_WizC\Demo3\Demo3.rep\r
+MRU8=C:\DOCUMENTS AND SETTINGS\marcel\MY DOCUMENTS\pic\FreeRTOS\FreeRTOS\Demo\PIC18_WIZC\Demo3\INTERRUPT.C\r
+Files6=C:\DOCUMENTS AND SETTINGS\marcel\MY DOCUMENTS\pic\FreeRTOS\FREERTOS 2005-06-04 01\Demo\PIC18_WIZC\Demo3\INTERRUPT.C\r
+Files7=C:\Documents and Settings\marcel\My Documents\pic\FreeRTOS\FreeRTOS 2005-06-04 01\Demo\PIC18_WizC\serial\serial.c\r
+[PinConnections]\r
+nPins=0\r
+[AssCode]\r
+ProcType=18F4620\r
+[Information]\r
+Column0=-1\r
+Column1=8\r
+Column2=4\r
+Column3=16\r
+Column4=-1\r
+Column5=50\r
+MemoHeight=154\r
+WindowState=0\r
+Top=418\r
+Left=339\r
+Width=339\r
+Height=209\r
+[F29012037]\r
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+[F30163486]\r
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+[F29565310]\r
+x=0\r
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+[F30089258]\r
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+[F29012293]\r
+x=0\r
+y=114\r
+[F28446561]\r
+x=0\r
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+[F30243165]\r
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+y=4852\r
+[F27125515]\r
+x=0\r
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+[F15568046]\r
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+[F20528681]\r
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+[F30163742]\r
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+[F33200396]\r
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+[F32375968]\r
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+[F28917072]\r
+x=0\r
+y=114\r
+[F31779807]\r
+x=0\r
+y=0\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+Changes from V3.0.0\r
+ + TickRate reduced to 250Hz.\r
+\r
+ + configIDLE_SHOULD_YIELD added.\r
+\r
+Changes from V3.0.1\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. \r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION ( 1 )\r
+#define configUSE_IDLE_HOOK ( 0 )\r
+#define configUSE_TICK_HOOK ( 0 )\r
+#define configTICK_RATE_HZ ( 250 )\r
+#define configMAX_PRIORITIES ( 4 )\r
+#define configMINIMAL_STACK_SIZE portMINIMAL_STACK_SIZE\r
+#define configMAX_TASK_NAME_LEN ( 3 )\r
+#define configUSE_TRACE_FACILITY ( 0 )\r
+#define configUSE_16_BIT_TICKS ( 1 )\r
+#define configIDLE_SHOULD_YIELD ( 1 )\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Set the following definitions to 1 to include the component, or zero\r
+to exclude the component. */\r
+\r
+/* Include/exclude the stated API function. */\r
+#define INCLUDE_vTaskPrioritySet ( 0 )\r
+#define INCLUDE_uxTaskPriorityGet ( 0 )\r
+#define INCLUDE_vTaskDelete ( 0 )\r
+#define INCLUDE_vTaskCleanUpResources ( 0 )\r
+#define INCLUDE_vTaskSuspend ( 0 )\r
+#define INCLUDE_vTaskDelayUntil ( 1 )\r
+#define INCLUDE_vTaskDelay ( 0 )\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+#ifndef _MALLOC_SETTINGS_H\r
+#define _MALLOC_SETTINGS_H\r
+/*********************************************************************\r
+** Title: Dynamic memory (de-)allocation library for wizC.\r
+**\r
+** Author: Marcel van Lieshout\r
+**\r
+** Copyright: (c) 2005, HMCS, Marcel van Lieshout\r
+**\r
+** License: This software is released to the public domain and comes\r
+** without warranty and/or guarantees of any kind. You have\r
+** the right to use, copy, modify and/or (re-)distribute the\r
+** software as long as the reference to the author is\r
+** maintained in the software and a reference to the author\r
+** is included in any documentation of each product in which\r
+** this library (in it's original or in a modified form)\r
+** is used.\r
+*********************************************************************/\r
+\r
+/*********************************************************************\r
+** The model to use\r
+*********************************************************************/\r
+//#define MALLOC_SMALL\r
+#define MALLOC_LARGE\r
+\r
+/*********************************************************************\r
+** The size of the heap\r
+*********************************************************************/\r
+#define MALLOC_HEAP_SIZE (3200)\r
+\r
+/*********************************************************************\r
+** Should released memory be scribbled with 0x55 before releasing it?\r
+*********************************************************************/\r
+//#define MALLOC_SCRIBBLE\r
+\r
+/********************************************************************\r
+** Enable Debug-mode?\r
+*********************************************************************/\r
+//#define MALLOC_DEBUG\r
+\r
+#endif /* _MALLOC_SETTINGS_H */\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+Changes from V3.0.0\r
+ + Several modules predefined to avoid linker problems\r
+\r
+Changes from V3.0.1\r
+*/\r
+\r
+#ifndef _memcpy\r
+ #define _memcpy 1\r
+#endif\r
+\r
+#ifndef _memset\r
+ #define _memset 1\r
+#endif\r
+\r
+#ifndef _strncpy\r
+ #define _strncpy 1\r
+#endif\r
+\r
+\r
+#pragma wizcpp searchpath <../../Common/Include/>\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+Changes from V3.0.0\r
+\r
+Changes from V3.0.1\r
+*/\r
+\r
+/*\r
+** Here are the configuration words set. See the PIC datasheet\r
+** and the wizC manual for an explanation\r
+*/\r
+#include <pic.h>\r
+\r
+/*\r
+** These fuses are for PIC18F4620\r
+*/\r
+#pragma __config _CONFIG1H,_IESO_OFF_1H & _FCMEN_OFF_1H & _OSC_HSPLL_1H\r
+#pragma __config _CONFIG2L,_BORV_21_2L & _BOREN_SBORDIS_2L & _PWRT_ON_2L\r
+#pragma __config _CONFIG2H,_WDTPS_32768_2H & _WDT_OFF_2H\r
+#pragma __config _CONFIG3H,_MCLRE_ON_3H & _LPT1OSC_OFF_3H & _PBADEN_OFF_3H & _CCP2MX_PORTC_3H\r
+#pragma __config _CONFIG4L,_DEBUG_OFF_4L & _XINST_OFF_4L & _LVP_OFF_4L & _STVREN_OFF_4L\r
+#pragma __config _CONFIG5L,_CP3_OFF_5L & _CP2_OFF_5L & _CP1_OFF_5L & _CP0_OFF_5L\r
+#pragma __config _CONFIG5H,_CPD_OFF_5H & _CPB_OFF_5H\r
+#pragma __config _CONFIG6L,_WRT3_OFF_6L & _WRT2_OFF_6L & _WRT1_OFF_6L & _WRT0_OFF_6L\r
+#pragma __config _CONFIG6H,_WRTD_OFF_6H & _WRTB_OFF_6H & _WRTC_OFF_6H\r
+#pragma __config _CONFIG7L,_EBTR3_OFF_7L & _EBTR2_OFF_7L & _EBTR1_OFF_7L & _EBTR0_OFF_7L\r
+#pragma __config _CONFIG7H,_EBTRB_OFF_7H\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* \r
+Changes from V3.0.0\r
+ + Added functionality to only call vTaskSwitchContext() once\r
+ when handling multiple interruptsources in a single interruptcall.\r
+\r
+ + Included Filenames changed to a .c extension to allow stepping through\r
+ code using F7.\r
+\r
+Changes from V3.0.1\r
+*/\r
+\r
+#include <pic.h>\r
+\r
+/* Scheduler include files. */\r
+#include <FreeRTOS.h>\r
+#include <task.h>\r
+#include <queue.h>\r
+\r
+static bit uxSwitchRequested;\r
+\r
+/*\r
+ * Vector for the ISR.\r
+ */\r
+void pointed Interrupt()\r
+{\r
+ /*\r
+ * Save the context of the current task.\r
+ */\r
+ portSAVE_CONTEXT( portINTERRUPTS_FORCED );\r
+\r
+ /*\r
+ * No contextswitch requested yet\r
+ */\r
+ uxSwitchRequested = pdFALSE;\r
+ \r
+ /*\r
+ * Was the interrupt the FreeRTOS SystemTick?\r
+ */\r
+ #include <libFreeRTOS/Drivers/Tick/isrTick.c>\r
+\r
+/*******************************************************************************\r
+** DO NOT MODIFY ANYTHING ABOVE THIS LINE\r
+********************************************************************************\r
+** Enter the includes for the ISR-code of the FreeRTOS drivers below.\r
+**\r
+** You cannot use local variables. Alternatives are:\r
+** - Use static variables (Global RAM usage increases)\r
+** - Call a function (Additional cycles are needed)\r
+** - Use unused SFR's (preferred, no additional overhead)\r
+** See "../Serial/isrSerialTx.c" for an example of this last option\r
+*******************************************************************************/\r
+\r
+\r
+\r
+ /*\r
+ * Was the interrupt a byte being received?\r
+ */\r
+ #include "../Serial/isrSerialRx.c"\r
+\r
+\r
+ /*\r
+ * Was the interrupt the Tx register becoming empty?\r
+ */\r
+ #include "../Serial/isrSerialTx.c"\r
+\r
+\r
+\r
+/*******************************************************************************\r
+** DO NOT MODIFY ANYTHING BELOW THIS LINE\r
+*******************************************************************************/\r
+ /*\r
+ * Was a contextswitch requested by one of the\r
+ * interrupthandlers?\r
+ */\r
+ if ( uxSwitchRequested )\r
+ {\r
+ vTaskSwitchContext();\r
+ }\r
+ \r
+ /*\r
+ * Restore the context of the (possibly other) task.\r
+ */\r
+ portRESTORE_CONTEXT();\r
+\r
+ #pragma asmline retfie 0\r
+}\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+Changes from V3.0.0\r
+\r
+Changes from V3.0.1\r
+*/\r
+\r
+/*\r
+ * Instead of the normal single demo application, the PIC18F demo is split \r
+ * into several smaller programs of which this is the third. This enables the \r
+ * demo's to be executed on the RAM limited PIC-devices.\r
+ *\r
+ * The Demo3 project is configured for a PIC18F4620 device. Main.c starts 12 \r
+ * tasks (including the idle task). See the indicated files in the demo/common\r
+ * directory for more information.\r
+ *\r
+ * demo/common/minimal/integer.c: Creates 1 task\r
+ * demo/common/minimal/BlockQ.c: Creates 6 tasks\r
+ * demo/common/minimal/flash.c: Creates 3 tasks\r
+ *\r
+ * Main.c also creates a check task. This periodically checks that all the \r
+ * other tasks are still running and have not experienced any unexpected \r
+ * results. If all the other tasks are executing correctly an LED is flashed \r
+ * once every mainCHECK_PERIOD milliseconds. If any of the tasks have not \r
+ * executed, or report an error, the frequency of the LED flash will increase \r
+ * to mainERROR_FLASH_RATE.\r
+ *\r
+ * On entry to main an 'X' is transmitted. Monitoring the serial port using a\r
+ * dumb terminal allows for verification that the device is not continuously \r
+ * being reset (no more than one 'X' should be transmitted).\r
+ *\r
+ * http://www.FreeRTOS.org contains important information on the use of the \r
+ * wizC PIC18F port.\r
+ */\r
+\r
+/* Scheduler include files. */\r
+#include <FreeRTOS.h>\r
+#include <task.h>\r
+\r
+/* Demo app include files. */\r
+#include "integer.h"\r
+#include "BlockQ.h"\r
+#include "flash.h"\r
+#include "partest.h"\r
+#include "serial.h"\r
+\r
+/* The period between executions of the check task before and after an error\r
+has been discovered. If an error has been discovered the check task runs\r
+more frequently - increasing the LED flash rate. */\r
+#define mainNO_ERROR_CHECK_PERIOD ( ( portTickType ) 10000 / portTICK_RATE_MS )\r
+#define mainERROR_CHECK_PERIOD ( ( portTickType ) 1000 / portTICK_RATE_MS )\r
+#define mainCHECK_TASK_LED ( ( unsigned portCHAR ) 3 )\r
+\r
+/* Priority definitions for some of the tasks. Other tasks just use the idle\r
+priority. */\r
+#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 3 )\r
+#define mainLED_FLASH_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 2 )\r
+#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 1 )\r
+#define mainINTEGER_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 0 )\r
+\r
+/* Constants required for the communications. Only one character is ever \r
+transmitted. */\r
+#define mainCOMMS_QUEUE_LENGTH ( ( unsigned portCHAR ) 5 )\r
+#define mainNO_BLOCK ( ( portTickType ) 0 )\r
+#define mainBAUD_RATE ( ( unsigned portLONG ) 57600 )\r
+\r
+/*\r
+ * The task function for the "Check" task.\r
+ */\r
+static portTASK_FUNCTION_PROTO( vErrorChecks, pvParameters );\r
+\r
+/*\r
+ * Checks the unique counts of other tasks to ensure they are still operational.\r
+ * Returns pdTRUE if an error is detected, otherwise pdFALSE.\r
+ */\r
+static portCHAR prvCheckOtherTasksAreStillRunning( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Creates the tasks, then starts the scheduler. */\r
+void main( void )\r
+{\r
+ /* Initialise the required hardware. */\r
+ vParTestInitialise();\r
+\r
+ /* Send a character so we have some visible feedback of a reset. */\r
+ xSerialPortInitMinimal( mainBAUD_RATE, mainCOMMS_QUEUE_LENGTH );\r
+ xSerialPutChar( NULL, 'X', mainNO_BLOCK );\r
+\r
+ /* Start the standard demo tasks found in the demo\common directory. */\r
+ vStartIntegerMathTasks( mainINTEGER_PRIORITY);\r
+ vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
+ vStartLEDFlashTasks( mainLED_FLASH_PRIORITY );\r
+\r
+ /* Start the check task defined in this file. */\r
+ xTaskCreate( vErrorChecks, ( const portCHAR * const ) "Check", portMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
+\r
+ /* Start the scheduler. Will never return here. */\r
+ vTaskStartScheduler( );\r
+\r
+ while(1) /* This point should never be reached. */\r
+ {\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portTASK_FUNCTION( vErrorChecks, pvParameters )\r
+{\r
+ portTickType xLastCheckTime;\r
+ portTickType xDelayTime = mainNO_ERROR_CHECK_PERIOD;\r
+ portCHAR cErrorOccurred;\r
+\r
+ /* We need to initialise xLastCheckTime prior to the first call to \r
+ vTaskDelayUntil(). */\r
+ xLastCheckTime = xTaskGetTickCount();\r
+ \r
+ /* Cycle for ever, delaying then checking all the other tasks are still\r
+ operating without error. */\r
+ for( ;; )\r
+ {\r
+ /* Wait until it is time to check the other tasks again. */\r
+ vTaskDelayUntil( &xLastCheckTime, xDelayTime );\r
+\r
+ /* Check all the other tasks are running, and running without ever\r
+ having an error. */\r
+ cErrorOccurred = prvCheckOtherTasksAreStillRunning();\r
+\r
+ /* If an error was detected increase the frequency of the LED flash. */\r
+ if( cErrorOccurred == pdTRUE )\r
+ {\r
+ xDelayTime = mainERROR_CHECK_PERIOD;\r
+ }\r
+\r
+ /* Flash the LED for visual feedback. */\r
+ vParTestToggleLED( mainCHECK_TASK_LED );\r
+ }\r
+}\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+static portCHAR prvCheckOtherTasksAreStillRunning( void )\r
+{\r
+ portCHAR cErrorHasOccurred = ( portCHAR ) pdFALSE;\r
+\r
+ if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ cErrorHasOccurred = ( portCHAR ) pdTRUE;\r
+ }\r
+\r
+ if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ cErrorHasOccurred = ( portCHAR ) pdTRUE;\r
+ }\r
+\r
+ return cErrorHasOccurred;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
--- /dev/null
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--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+Changes from V3.0.0\r
+ + TickRate reduced to 250Hz.\r
+\r
+ + configIDLE_SHOULD_YIELD added.\r
+\r
+Changes from V3.0.1\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. \r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION ( 1 )\r
+#define configUSE_IDLE_HOOK ( 0 )\r
+#define configUSE_TICK_HOOK ( 0 )\r
+#define configTICK_RATE_HZ ( 250 )\r
+#define configMAX_PRIORITIES ( 4 )\r
+#define configMINIMAL_STACK_SIZE portMINIMAL_STACK_SIZE\r
+#define configMAX_TASK_NAME_LEN ( 3 )\r
+#define configUSE_TRACE_FACILITY ( 0 )\r
+#define configUSE_16_BIT_TICKS ( 1 )\r
+#define configIDLE_SHOULD_YIELD ( 1 )\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Set the following definitions to 1 to include the component, or zero\r
+to exclude the component. */\r
+\r
+/* Include/exclude the stated API function. */\r
+#define INCLUDE_vTaskPrioritySet ( 1 )\r
+#define INCLUDE_uxTaskPriorityGet ( 1 )\r
+#define INCLUDE_vTaskDelete ( 0 )\r
+#define INCLUDE_vTaskCleanUpResources ( 0 )\r
+#define INCLUDE_vTaskSuspend ( 1 )\r
+#define INCLUDE_vTaskDelayUntil ( 1 )\r
+#define INCLUDE_vTaskDelay ( 1 )\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+#ifndef _MALLOC_SETTINGS_H\r
+#define _MALLOC_SETTINGS_H\r
+/*********************************************************************\r
+** Title: Dynamic memory (de-)allocation library for wizC.\r
+**\r
+** Author: Marcel van Lieshout\r
+**\r
+** Copyright: (c) 2005, HMCS, Marcel van Lieshout\r
+**\r
+** License: This software is released to the public domain and comes\r
+** without warranty and/or guarantees of any kind. You have\r
+** the right to use, copy, modify and/or (re-)distribute the\r
+** software as long as the reference to the author is\r
+** maintained in the software and a reference to the author\r
+** is included in any documentation of each product in which\r
+** this library (in it's original or in a modified form)\r
+** is used.\r
+*********************************************************************/\r
+\r
+/*********************************************************************\r
+** The model to use\r
+*********************************************************************/\r
+//#define MALLOC_SMALL\r
+#define MALLOC_LARGE\r
+\r
+/*********************************************************************\r
+** The size of the heap\r
+*********************************************************************/\r
+#define MALLOC_HEAP_SIZE (3200)\r
+\r
+/*********************************************************************\r
+** Should released memory be scribbled with 0x55 before releasing it?\r
+*********************************************************************/\r
+//#define MALLOC_SCRIBBLE\r
+\r
+/********************************************************************\r
+** Enable Debug-mode?\r
+*********************************************************************/\r
+//#define MALLOC_DEBUG\r
+\r
+#endif /* _MALLOC_SETTINGS_H */\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+Changes from V3.0.0\r
+ + Several modules predefined to avoid linker problems\r
+\r
+Changes from V3.0.1\r
+*/\r
+\r
+#ifndef _memcpy\r
+ #define _memcpy 1\r
+#endif\r
+\r
+#ifndef _memset\r
+ #define _memset 1\r
+#endif\r
+\r
+#ifndef _strncpy\r
+ #define _strncpy 1\r
+#endif\r
+\r
+\r
+#pragma wizcpp searchpath <../../Common/Include/>\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+Changes from V3.0.0\r
+\r
+Changes from V3.0.1\r
+*/\r
+\r
+/*\r
+** Here are the configuration words set. See the PIC datasheet\r
+** and the wizC manual for an explanation\r
+*/\r
+#include <pic.h>\r
+\r
+/*\r
+** These fuses are for PIC18F4620\r
+*/\r
+#pragma __config _CONFIG1H,_IESO_OFF_1H & _FCMEN_OFF_1H & _OSC_HSPLL_1H\r
+#pragma __config _CONFIG2L,_BORV_21_2L & _BOREN_SBORDIS_2L & _PWRT_ON_2L\r
+#pragma __config _CONFIG2H,_WDTPS_32768_2H & _WDT_OFF_2H\r
+#pragma __config _CONFIG3H,_MCLRE_ON_3H & _LPT1OSC_OFF_3H & _PBADEN_OFF_3H & _CCP2MX_PORTC_3H\r
+#pragma __config _CONFIG4L,_DEBUG_OFF_4L & _XINST_OFF_4L & _LVP_OFF_4L & _STVREN_OFF_4L\r
+#pragma __config _CONFIG5L,_CP3_OFF_5L & _CP2_OFF_5L & _CP1_OFF_5L & _CP0_OFF_5L\r
+#pragma __config _CONFIG5H,_CPD_OFF_5H & _CPB_OFF_5H\r
+#pragma __config _CONFIG6L,_WRT3_OFF_6L & _WRT2_OFF_6L & _WRT1_OFF_6L & _WRT0_OFF_6L\r
+#pragma __config _CONFIG6H,_WRTD_OFF_6H & _WRTB_OFF_6H & _WRTC_OFF_6H\r
+#pragma __config _CONFIG7L,_EBTR3_OFF_7L & _EBTR2_OFF_7L & _EBTR1_OFF_7L & _EBTR0_OFF_7L\r
+#pragma __config _CONFIG7H,_EBTRB_OFF_7H\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* \r
+Changes from V3.0.0\r
+ + Added functionality to only call vTaskSwitchContext() once\r
+ when handling multiple interruptsources in a single interruptcall.\r
+\r
+ + Included Filenames changed to a .c extension to allow stepping through\r
+ code using F7.\r
+\r
+Changes from V3.0.1\r
+*/\r
+\r
+#include <pic.h>\r
+\r
+/* Scheduler include files. */\r
+#include <FreeRTOS.h>\r
+#include <task.h>\r
+#include <queue.h>\r
+\r
+static bit uxSwitchRequested;\r
+\r
+/*\r
+ * Vector for the ISR.\r
+ */\r
+void pointed Interrupt()\r
+{\r
+ /*\r
+ * Save the context of the current task.\r
+ */\r
+ portSAVE_CONTEXT( portINTERRUPTS_FORCED );\r
+\r
+ /*\r
+ * No contextswitch requested yet\r
+ */\r
+ uxSwitchRequested = pdFALSE;\r
+ \r
+ /*\r
+ * Was the interrupt the FreeRTOS SystemTick?\r
+ */\r
+ #include <libFreeRTOS/Drivers/Tick/isrTick.c>\r
+\r
+/*******************************************************************************\r
+** DO NOT MODIFY ANYTHING ABOVE THIS LINE\r
+********************************************************************************\r
+** Enter the includes for the ISR-code of the FreeRTOS drivers below.\r
+**\r
+** You cannot use local variables. Alternatives are:\r
+** - Use static variables (Global RAM usage increases)\r
+** - Call a function (Additional cycles are needed)\r
+** - Use unused SFR's (preferred, no additional overhead)\r
+** See "../Serial/isrSerialTx.c" for an example of this last option\r
+*******************************************************************************/\r
+\r
+\r
+\r
+ /*\r
+ * Was the interrupt a byte being received?\r
+ */\r
+ #include "../Serial/isrSerialRx.c"\r
+\r
+\r
+ /*\r
+ * Was the interrupt the Tx register becoming empty?\r
+ */\r
+ #include "../Serial/isrSerialTx.c"\r
+\r
+\r
+\r
+/*******************************************************************************\r
+** DO NOT MODIFY ANYTHING BELOW THIS LINE\r
+*******************************************************************************/\r
+ /*\r
+ * Was a contextswitch requested by one of the\r
+ * interrupthandlers?\r
+ */\r
+ if ( uxSwitchRequested )\r
+ {\r
+ vTaskSwitchContext();\r
+ }\r
+ \r
+ /*\r
+ * Restore the context of the (possibly other) task.\r
+ */\r
+ portRESTORE_CONTEXT();\r
+\r
+ #pragma asmline retfie 0\r
+}\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+Changes from V3.0.0\r
+\r
+Changes from V3.0.1\r
+*/\r
+\r
+/*\r
+ * Instead of the normal single demo application, the PIC18F demo is split \r
+ * into several smaller programs of which this is the fourth. This enables the \r
+ * demo's to be executed on the RAM limited PIC-devices.\r
+ *\r
+ * The Demo4 project is configured for a PIC18F4620 device. Main.c starts 11 \r
+ * tasks (including the idle task). See the indicated files in the demo/common\r
+ * directory for more information.\r
+ *\r
+ * demo/common/minimal/integer.c: Creates 1 task\r
+ * demo/common/minimal/dynamic.c: Creates 5 tasks\r
+ * demo/common/minimal/flash.c: Creates 3 tasks\r
+ *\r
+ * Main.c also creates a check task. This periodically checks that all the \r
+ * other tasks are still running and have not experienced any unexpected \r
+ * results. If all the other tasks are executing correctly an LED is flashed \r
+ * once every mainCHECK_PERIOD milliseconds. If any of the tasks have not \r
+ * executed, or report an error, the frequency of the LED flash will increase \r
+ * to mainERROR_FLASH_RATE.\r
+ *\r
+ * On entry to main an 'X' is transmitted. Monitoring the serial port using a\r
+ * dumb terminal allows for verification that the device is not continuously \r
+ * being reset (no more than one 'X' should be transmitted).\r
+ *\r
+ * http://www.FreeRTOS.org contains important information on the use of the \r
+ * wizC PIC18F port.\r
+ */\r
+\r
+/* Scheduler include files. */\r
+#include <FreeRTOS.h>\r
+#include <task.h>\r
+\r
+/* Demo app include files. */\r
+#include "integer.h"\r
+#include "dynamic.h"\r
+#include "flash.h"\r
+#include "partest.h"\r
+#include "serial.h"\r
+\r
+/* The period between executions of the check task before and after an error\r
+has been discovered. If an error has been discovered the check task runs\r
+more frequently - increasing the LED flash rate. */\r
+#define mainNO_ERROR_CHECK_PERIOD ( ( portTickType ) 10000 / portTICK_RATE_MS )\r
+#define mainERROR_CHECK_PERIOD ( ( portTickType ) 1000 / portTICK_RATE_MS )\r
+#define mainCHECK_TASK_LED ( ( unsigned portCHAR ) 3 )\r
+\r
+/* Priority definitions for some of the tasks. Other tasks just use the idle\r
+priority. */\r
+#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 3 )\r
+#define mainLED_FLASH_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 2 )\r
+#define mainINTEGER_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 0 )\r
+\r
+/* Constants required for the communications. Only one character is ever \r
+transmitted. */\r
+#define mainCOMMS_QUEUE_LENGTH ( ( unsigned portCHAR ) 5 )\r
+#define mainNO_BLOCK ( ( portTickType ) 0 )\r
+#define mainBAUD_RATE ( ( unsigned portLONG ) 57600 )\r
+\r
+/*\r
+ * The task function for the "Check" task.\r
+ */\r
+static portTASK_FUNCTION_PROTO( vErrorChecks, pvParameters );\r
+\r
+/*\r
+ * Checks the unique counts of other tasks to ensure they are still operational.\r
+ * Returns pdTRUE if an error is detected, otherwise pdFALSE.\r
+ */\r
+static portCHAR prvCheckOtherTasksAreStillRunning( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Creates the tasks, then starts the scheduler. */\r
+void main( void )\r
+{\r
+ /* Initialise the required hardware. */\r
+ vParTestInitialise();\r
+\r
+ /* Send a character so we have some visible feedback of a reset. */\r
+ xSerialPortInitMinimal( mainBAUD_RATE, mainCOMMS_QUEUE_LENGTH );\r
+ xSerialPutChar( NULL, 'X', mainNO_BLOCK );\r
+\r
+ /* Start the standard demo tasks found in the demo\common directory. */\r
+ vStartIntegerMathTasks( mainINTEGER_PRIORITY);\r
+ vStartDynamicPriorityTasks();\r
+ vStartLEDFlashTasks( mainLED_FLASH_PRIORITY );\r
+\r
+ /* Start the check task defined in this file. */\r
+ xTaskCreate( vErrorChecks, ( const portCHAR * const ) "Check", portMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
+\r
+ /* Start the scheduler. Will never return here. */\r
+ vTaskStartScheduler( );\r
+\r
+ while(1) /* This point should never be reached. */\r
+ {\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portTASK_FUNCTION( vErrorChecks, pvParameters )\r
+{\r
+ portTickType xLastCheckTime;\r
+ portTickType xDelayTime = mainNO_ERROR_CHECK_PERIOD;\r
+ portCHAR cErrorOccurred;\r
+\r
+ /* We need to initialise xLastCheckTime prior to the first call to \r
+ vTaskDelayUntil(). */\r
+ xLastCheckTime = xTaskGetTickCount();\r
+ \r
+ /* Cycle for ever, delaying then checking all the other tasks are still\r
+ operating without error. */\r
+ for( ;; )\r
+ {\r
+ /* Wait until it is time to check the other tasks again. */\r
+ vTaskDelayUntil( &xLastCheckTime, xDelayTime );\r
+\r
+ /* Check all the other tasks are running, and running without ever\r
+ having an error. */\r
+ cErrorOccurred = prvCheckOtherTasksAreStillRunning();\r
+\r
+ /* If an error was detected increase the frequency of the LED flash. */\r
+ if( cErrorOccurred == pdTRUE )\r
+ {\r
+ xDelayTime = mainERROR_CHECK_PERIOD;\r
+ }\r
+\r
+ /* Flash the LED for visual feedback. */\r
+ vParTestToggleLED( mainCHECK_TASK_LED );\r
+ }\r
+}\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+static portCHAR prvCheckOtherTasksAreStillRunning( void )\r
+{\r
+ portCHAR cErrorHasOccurred = ( portCHAR ) pdFALSE;\r
+\r
+ if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ cErrorHasOccurred = ( portCHAR ) pdTRUE;\r
+ }\r
+\r
+ if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )\r
+ {\r
+ cErrorHasOccurred = ( portCHAR ) pdTRUE;\r
+ }\r
+\r
+ return cErrorHasOccurred;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
--- /dev/null
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+[GLOBAL]\r
+LoadCheck=2\r
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--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+Changes from V3.0.0\r
+ + TickRate reduced to 250Hz.\r
+\r
+ + configIDLE_SHOULD_YIELD added.\r
+\r
+Changes from V3.0.1\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. \r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION ( 1 )\r
+#define configUSE_IDLE_HOOK ( 0 )\r
+#define configUSE_TICK_HOOK ( 0 )\r
+#define configTICK_RATE_HZ ( 250 )\r
+#define configMAX_PRIORITIES ( 3 )\r
+#define configMINIMAL_STACK_SIZE portMINIMAL_STACK_SIZE\r
+#define configMAX_TASK_NAME_LEN ( 3 )\r
+#define configUSE_TRACE_FACILITY ( 0 )\r
+#define configUSE_16_BIT_TICKS ( 1 )\r
+#define configIDLE_SHOULD_YIELD ( 1 )\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Set the following definitions to 1 to include the component, or zero\r
+to exclude the component. */\r
+\r
+/* Include/exclude the stated API function. */\r
+#define INCLUDE_vTaskPrioritySet ( 0 )\r
+#define INCLUDE_uxTaskPriorityGet ( 0 )\r
+#define INCLUDE_vTaskDelete ( 0 )\r
+#define INCLUDE_vTaskCleanUpResources ( 0 )\r
+#define INCLUDE_vTaskSuspend ( 0 )\r
+#define INCLUDE_vTaskDelayUntil ( 1 )\r
+#define INCLUDE_vTaskDelay ( 0 )\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+#ifndef _MALLOC_SETTINGS_H\r
+#define _MALLOC_SETTINGS_H\r
+/*********************************************************************\r
+** Title: Dynamic memory (de-)allocation library for wizC.\r
+**\r
+** Author: Marcel van Lieshout\r
+**\r
+** Copyright: (c) 2005, HMCS, Marcel van Lieshout\r
+**\r
+** License: This software is released to the public domain and comes\r
+** without warranty and/or guarantees of any kind. You have\r
+** the right to use, copy, modify and/or (re-)distribute the\r
+** software as long as the reference to the author is\r
+** maintained in the software and a reference to the author\r
+** is included in any documentation of each product in which\r
+** this library (in it's original or in a modified form)\r
+** is used.\r
+*********************************************************************/\r
+\r
+/*********************************************************************\r
+** The model to use\r
+*********************************************************************/\r
+//#define MALLOC_SMALL\r
+#define MALLOC_LARGE\r
+\r
+/*********************************************************************\r
+** The size of the heap\r
+*********************************************************************/\r
+#define MALLOC_HEAP_SIZE (3200)\r
+\r
+/*********************************************************************\r
+** Should released memory be scribbled with 0x55 before releasing it?\r
+*********************************************************************/\r
+//#define MALLOC_SCRIBBLE\r
+\r
+/********************************************************************\r
+** Enable Debug-mode?\r
+*********************************************************************/\r
+//#define MALLOC_DEBUG\r
+\r
+#endif /* _MALLOC_SETTINGS_H */\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+Changes from V3.0.0\r
+ + Several modules predefined to avoid linker problems\r
+\r
+Changes from V3.0.1\r
+*/\r
+\r
+#ifndef _memcpy\r
+ #define _memcpy 1\r
+#endif\r
+\r
+#ifndef _memset\r
+ #define _memset 1\r
+#endif\r
+\r
+#ifndef _strncpy\r
+ #define _strncpy 1\r
+#endif\r
+\r
+\r
+#pragma wizcpp searchpath <../../Common/Include/>\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+Changes from V3.0.0\r
+\r
+Changes from V3.0.1\r
+*/\r
+\r
+/*\r
+** Here are the configuration words set. See the PIC datasheet\r
+** and the wizC manual for an explanation\r
+*/\r
+#include <pic.h>\r
+\r
+/*\r
+** These fuses are for PIC18F4620\r
+*/\r
+#pragma __config _CONFIG1H,_IESO_OFF_1H & _FCMEN_OFF_1H & _OSC_HSPLL_1H\r
+#pragma __config _CONFIG2L,_BORV_21_2L & _BOREN_SBORDIS_2L & _PWRT_ON_2L\r
+#pragma __config _CONFIG2H,_WDTPS_32768_2H & _WDT_OFF_2H\r
+#pragma __config _CONFIG3H,_MCLRE_ON_3H & _LPT1OSC_OFF_3H & _PBADEN_OFF_3H & _CCP2MX_PORTC_3H\r
+#pragma __config _CONFIG4L,_DEBUG_OFF_4L & _XINST_OFF_4L & _LVP_OFF_4L & _STVREN_OFF_4L\r
+#pragma __config _CONFIG5L,_CP3_OFF_5L & _CP2_OFF_5L & _CP1_OFF_5L & _CP0_OFF_5L\r
+#pragma __config _CONFIG5H,_CPD_OFF_5H & _CPB_OFF_5H\r
+#pragma __config _CONFIG6L,_WRT3_OFF_6L & _WRT2_OFF_6L & _WRT1_OFF_6L & _WRT0_OFF_6L\r
+#pragma __config _CONFIG6H,_WRTD_OFF_6H & _WRTB_OFF_6H & _WRTC_OFF_6H\r
+#pragma __config _CONFIG7L,_EBTR3_OFF_7L & _EBTR2_OFF_7L & _EBTR1_OFF_7L & _EBTR0_OFF_7L\r
+#pragma __config _CONFIG7H,_EBTRB_OFF_7H\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* \r
+Changes from V3.0.0\r
+ + Added functionality to only call vTaskSwitchContext() once\r
+ when handling multiple interruptsources in a single interruptcall.\r
+\r
+ + Included Filenames changed to a .c extension to allow stepping through\r
+ code using F7.\r
+\r
+Changes from V3.0.1\r
+*/\r
+\r
+#include <pic.h>\r
+\r
+/* Scheduler include files. */\r
+#include <FreeRTOS.h>\r
+#include <task.h>\r
+#include <queue.h>\r
+\r
+static bit uxSwitchRequested;\r
+\r
+/*\r
+ * Vector for the ISR.\r
+ */\r
+void pointed Interrupt()\r
+{\r
+ /*\r
+ * Save the context of the current task.\r
+ */\r
+ portSAVE_CONTEXT( portINTERRUPTS_FORCED );\r
+\r
+ /*\r
+ * No contextswitch requested yet\r
+ */\r
+ uxSwitchRequested = pdFALSE;\r
+ \r
+ /*\r
+ * Was the interrupt the FreeRTOS SystemTick?\r
+ */\r
+ #include <libFreeRTOS/Drivers/Tick/isrTick.c>\r
+\r
+/*******************************************************************************\r
+** DO NOT MODIFY ANYTHING ABOVE THIS LINE\r
+********************************************************************************\r
+** Enter the includes for the ISR-code of the FreeRTOS drivers below.\r
+**\r
+** You cannot use local variables. Alternatives are:\r
+** - Use static variables (Global RAM usage increases)\r
+** - Call a function (Additional cycles are needed)\r
+** - Use unused SFR's (preferred, no additional overhead)\r
+** See "../Serial/isrSerialTx.c" for an example of this last option\r
+*******************************************************************************/\r
+\r
+\r
+\r
+ /*\r
+ * Was the interrupt a byte being received?\r
+ */\r
+ #include "../Serial/isrSerialRx.c"\r
+\r
+\r
+ /*\r
+ * Was the interrupt the Tx register becoming empty?\r
+ */\r
+ #include "../Serial/isrSerialTx.c"\r
+\r
+\r
+\r
+/*******************************************************************************\r
+** DO NOT MODIFY ANYTHING BELOW THIS LINE\r
+*******************************************************************************/\r
+ /*\r
+ * Was a contextswitch requested by one of the\r
+ * interrupthandlers?\r
+ */\r
+ if ( uxSwitchRequested )\r
+ {\r
+ vTaskSwitchContext();\r
+ }\r
+ \r
+ /*\r
+ * Restore the context of the (possibly other) task.\r
+ */\r
+ portRESTORE_CONTEXT();\r
+\r
+ #pragma asmline retfie 0\r
+}\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+Changes from V3.0.0\r
+\r
+Changes from V3.0.1\r
+*/\r
+\r
+/*\r
+ * Instead of the normal single demo application, the PIC18F demo is split \r
+ * into several smaller programs of which this is the fifth. This enables the \r
+ * demo's to be executed on the RAM limited PIC-devices.\r
+ *\r
+ * The Demo5 project is configured for a PIC18F4620 device. Main.c starts 13 \r
+ * tasks (including the idle task). See the indicated files in the demo/common\r
+ * directory for more information.\r
+ *\r
+ * demo/common/minimal/flop.c: Creates 8 tasks\r
+ * demo/common/minimal/flash.c: Creates 3 tasks\r
+ *\r
+ * Main.c also creates a check task. This periodically checks that all the \r
+ * other tasks are still running and have not experienced any unexpected \r
+ * results. If all the other tasks are executing correctly an LED is flashed \r
+ * once every mainCHECK_PERIOD milliseconds. If any of the tasks have not \r
+ * executed, or report an error, the frequency of the LED flash will increase \r
+ * to mainERROR_FLASH_RATE.\r
+ *\r
+ * On entry to main an 'X' is transmitted. Monitoring the serial port using a\r
+ * dumb terminal allows for verification that the device is not continuously \r
+ * being reset (no more than one 'X' should be transmitted).\r
+ *\r
+ * http://www.FreeRTOS.org contains important information on the use of the \r
+ * wizC PIC18F port.\r
+ */\r
+\r
+/* Scheduler include files. */\r
+#include <FreeRTOS.h>\r
+#include <task.h>\r
+\r
+/* Demo app include files. */\r
+#include "flop.h"\r
+#include "flash.h"\r
+#include "partest.h"\r
+#include "serial.h"\r
+\r
+/* The period between executions of the check task before and after an error\r
+has been discovered. If an error has been discovered the check task runs\r
+more frequently - increasing the LED flash rate. */\r
+#define mainNO_ERROR_CHECK_PERIOD ( ( portTickType ) 10000 / portTICK_RATE_MS )\r
+#define mainERROR_CHECK_PERIOD ( ( portTickType ) 1000 / portTICK_RATE_MS )\r
+#define mainCHECK_TASK_LED ( ( unsigned portCHAR ) 3 )\r
+\r
+/* Priority definitions for some of the tasks. Other tasks just use the idle\r
+priority. */\r
+#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 2 )\r
+#define mainLED_FLASH_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 1 )\r
+\r
+/* Constants required for the communications. Only one character is ever \r
+transmitted. */\r
+#define mainCOMMS_QUEUE_LENGTH ( ( unsigned portCHAR ) 5 )\r
+#define mainNO_BLOCK ( ( portTickType ) 0 )\r
+#define mainBAUD_RATE ( ( unsigned portLONG ) 57600 )\r
+\r
+/*\r
+ * The task function for the "Check" task.\r
+ */\r
+static portTASK_FUNCTION_PROTO( vErrorChecks, pvParameters );\r
+\r
+/*\r
+ * Checks the unique counts of other tasks to ensure they are still operational.\r
+ * Returns pdTRUE if an error is detected, otherwise pdFALSE.\r
+ */\r
+static portCHAR prvCheckOtherTasksAreStillRunning( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Creates the tasks, then starts the scheduler. */\r
+void main( void )\r
+{\r
+ /* Initialise the required hardware. */\r
+ vParTestInitialise();\r
+\r
+ /* Send a character so we have some visible feedback of a reset. */\r
+ xSerialPortInitMinimal( mainBAUD_RATE, mainCOMMS_QUEUE_LENGTH );\r
+ xSerialPutChar( NULL, 'X', mainNO_BLOCK );\r
+\r
+ /* Start a few of the standard demo tasks found in the demo\common directory. */\r
+ vStartMathTasks( tskIDLE_PRIORITY );\r
+ vStartLEDFlashTasks( mainLED_FLASH_PRIORITY );\r
+\r
+ /* Start the check task defined in this file. */\r
+ xTaskCreate( vErrorChecks, ( const portCHAR * const ) "Check", portMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
+\r
+ /* Start the scheduler. Will never return here. */\r
+ vTaskStartScheduler();\r
+\r
+ while(1) /* This point should never be reached. */\r
+ {\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portTASK_FUNCTION( vErrorChecks, pvParameters )\r
+{\r
+portTickType xLastCheckTime;\r
+portTickType xDelayTime = mainNO_ERROR_CHECK_PERIOD;\r
+portCHAR cErrorOccurred;\r
+\r
+ /* We need to initialise xLastCheckTime prior to the first call to \r
+ vTaskDelayUntil(). */\r
+ xLastCheckTime = xTaskGetTickCount();\r
+ \r
+ /* Cycle for ever, delaying then checking all the other tasks are still\r
+ operating without error. */\r
+ for( ;; )\r
+ {\r
+ /* Wait until it is time to check the other tasks again. */\r
+ vTaskDelayUntil( &xLastCheckTime, xDelayTime );\r
+ \r
+ /* Check all the other tasks are running, and running without ever\r
+ having an error. */\r
+ cErrorOccurred = prvCheckOtherTasksAreStillRunning();\r
+\r
+ /* If an error was detected increase the frequency of the LED flash. */\r
+ if( cErrorOccurred == pdTRUE )\r
+ {\r
+ xDelayTime = mainERROR_CHECK_PERIOD;\r
+ }\r
+\r
+ /* Flash the LED for visual feedback. */\r
+ vParTestToggleLED( mainCHECK_TASK_LED );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portCHAR prvCheckOtherTasksAreStillRunning( void )\r
+{\r
+ portCHAR cErrorHasOccurred = ( portCHAR ) pdFALSE;\r
+\r
+ if( xAreMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ cErrorHasOccurred = ( portCHAR ) pdTRUE;\r
+ }\r
+ return cErrorHasOccurred;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
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+[F24752775]\r
+x=40\r
+y=52\r
+[F24752903]\r
+x=40\r
+y=52\r
+[F29013061]\r
+x=0\r
+y=113\r
+[F27123467]\r
+x=55\r
+y=67\r
+[F28496481]\r
+x=8\r
+y=29\r
+[F20528681]\r
+x=18\r
+y=94\r
+[F28479879]\r
+x=49\r
+y=2522\r
+[F28931976]\r
+x=0\r
+y=0\r
+[F29801213]\r
+x=24\r
+y=36\r
+[F29801181]\r
+x=24\r
+y=36\r
+[F24754146]\r
+x=0\r
+y=0\r
+[F20122654]\r
+x=0\r
+y=44\r
+[F20558577]\r
+x=6\r
+y=5403\r
+[F29471871]\r
+x=13\r
+y=4972\r
+[F15787712]\r
+x=0\r
+y=47\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+Changes from V3.0.0\r
+ + TickRate reduced to 250Hz.\r
+\r
+ + configIDLE_SHOULD_YIELD added.\r
+\r
+Changes from V3.0.1\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. \r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION ( 1 )\r
+#define configUSE_IDLE_HOOK ( 0 )\r
+#define configUSE_TICK_HOOK ( 0 )\r
+#define configTICK_RATE_HZ ( 250 )\r
+#define configMAX_PRIORITIES ( 3 )\r
+#define configMINIMAL_STACK_SIZE portMINIMAL_STACK_SIZE\r
+#define configMAX_TASK_NAME_LEN ( 3 )\r
+#define configUSE_TRACE_FACILITY ( 0 )\r
+#define configUSE_16_BIT_TICKS ( 1 )\r
+#define configIDLE_SHOULD_YIELD ( 1 )\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Set the following definitions to 1 to include the component, or zero\r
+to exclude the component. */\r
+\r
+/* Include/exclude the stated API function. */\r
+#define INCLUDE_vTaskPrioritySet ( 0 )\r
+#define INCLUDE_uxTaskPriorityGet ( 0 )\r
+#define INCLUDE_vTaskDelete ( 0 )\r
+#define INCLUDE_vTaskCleanUpResources ( 0 )\r
+#define INCLUDE_vTaskSuspend ( 0 )\r
+#define INCLUDE_vTaskDelayUntil ( 1 )\r
+#define INCLUDE_vTaskDelay ( 1 )\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+#ifndef _MALLOC_SETTINGS_H\r
+#define _MALLOC_SETTINGS_H\r
+/*********************************************************************\r
+** Title: Dynamic memory (de-)allocation library for wizC.\r
+**\r
+** Author: Marcel van Lieshout\r
+**\r
+** Copyright: (c) 2005, HMCS, Marcel van Lieshout\r
+**\r
+** License: This software is released to the public domain and comes\r
+** without warranty and/or guarantees of any kind. You have\r
+** the right to use, copy, modify and/or (re-)distribute the\r
+** software as long as the reference to the author is\r
+** maintained in the software and a reference to the author\r
+** is included in any documentation of each product in which\r
+** this library (in it's original or in a modified form)\r
+** is used.\r
+*********************************************************************/\r
+\r
+/*********************************************************************\r
+** The model to use\r
+*********************************************************************/\r
+//#define MALLOC_SMALL\r
+#define MALLOC_LARGE\r
+\r
+/*********************************************************************\r
+** The size of the heap\r
+*********************************************************************/\r
+#define MALLOC_HEAP_SIZE (3200)\r
+\r
+/*********************************************************************\r
+** Should released memory be scribbled with 0x55 before releasing it?\r
+*********************************************************************/\r
+//#define MALLOC_SCRIBBLE\r
+\r
+/********************************************************************\r
+** Enable Debug-mode?\r
+*********************************************************************/\r
+//#define MALLOC_DEBUG\r
+\r
+#endif /* _MALLOC_SETTINGS_H */\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+Changes from V3.0.0\r
+ + Several modules predefined to avoid linker problems\r
+\r
+Changes from V3.0.1\r
+*/\r
+\r
+#ifndef _memcpy\r
+ #define _memcpy 1\r
+#endif\r
+\r
+#ifndef _memset\r
+ #define _memset 1\r
+#endif\r
+\r
+#ifndef _strncpy\r
+ #define _strncpy 1\r
+#endif\r
+\r
+\r
+#pragma wizcpp searchpath <../../Common/Include/>\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+Changes from V3.0.0\r
+\r
+Changes from V3.0.1\r
+*/\r
+\r
+/*\r
+** Here are the configuration words set. See the PIC datasheet\r
+** and the wizC manual for an explanation\r
+*/\r
+#include <pic.h>\r
+\r
+/*\r
+** These fuses are for PIC18F4620\r
+*/\r
+#pragma __config _CONFIG1H,_IESO_OFF_1H & _FCMEN_OFF_1H & _OSC_HSPLL_1H\r
+#pragma __config _CONFIG2L,_BORV_21_2L & _BOREN_SBORDIS_2L & _PWRT_ON_2L\r
+#pragma __config _CONFIG2H,_WDTPS_32768_2H & _WDT_OFF_2H\r
+#pragma __config _CONFIG3H,_MCLRE_ON_3H & _LPT1OSC_OFF_3H & _PBADEN_OFF_3H & _CCP2MX_PORTC_3H\r
+#pragma __config _CONFIG4L,_DEBUG_OFF_4L & _XINST_OFF_4L & _LVP_OFF_4L & _STVREN_OFF_4L\r
+#pragma __config _CONFIG5L,_CP3_OFF_5L & _CP2_OFF_5L & _CP1_OFF_5L & _CP0_OFF_5L\r
+#pragma __config _CONFIG5H,_CPD_OFF_5H & _CPB_OFF_5H\r
+#pragma __config _CONFIG6L,_WRT3_OFF_6L & _WRT2_OFF_6L & _WRT1_OFF_6L & _WRT0_OFF_6L\r
+#pragma __config _CONFIG6H,_WRTD_OFF_6H & _WRTB_OFF_6H & _WRTC_OFF_6H\r
+#pragma __config _CONFIG7L,_EBTR3_OFF_7L & _EBTR2_OFF_7L & _EBTR1_OFF_7L & _EBTR0_OFF_7L\r
+#pragma __config _CONFIG7H,_EBTRB_OFF_7H\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* \r
+Changes from V3.0.0\r
+ + Added functionality to only call vTaskSwitchContext() once\r
+ when handling multiple interruptsources in a single interruptcall.\r
+\r
+ + Included Filenames changed to a .c extension to allow stepping through\r
+ code using F7.\r
+\r
+Changes from V3.0.1\r
+*/\r
+\r
+#include <pic.h>\r
+\r
+/* Scheduler include files. */\r
+#include <FreeRTOS.h>\r
+#include <task.h>\r
+#include <queue.h>\r
+\r
+static bit uxSwitchRequested;\r
+\r
+/*\r
+ * Vector for the ISR.\r
+ */\r
+void pointed Interrupt()\r
+{\r
+ /*\r
+ * Save the context of the current task.\r
+ */\r
+ portSAVE_CONTEXT( portINTERRUPTS_FORCED );\r
+\r
+ /*\r
+ * No contextswitch requested yet\r
+ */\r
+ uxSwitchRequested = pdFALSE;\r
+ \r
+ /*\r
+ * Was the interrupt the FreeRTOS SystemTick?\r
+ */\r
+ #include <libFreeRTOS/Drivers/Tick/isrTick.c>\r
+\r
+/*******************************************************************************\r
+** DO NOT MODIFY ANYTHING ABOVE THIS LINE\r
+********************************************************************************\r
+** Enter the includes for the ISR-code of the FreeRTOS drivers below.\r
+**\r
+** You cannot use local variables. Alternatives are:\r
+** - Use static variables (Global RAM usage increases)\r
+** - Call a function (Additional cycles are needed)\r
+** - Use unused SFR's (preferred, no additional overhead)\r
+** See "../Serial/isrSerialTx.c" for an example of this last option\r
+*******************************************************************************/\r
+\r
+\r
+\r
+ /*\r
+ * Was the interrupt a byte being received?\r
+ */\r
+ #include "../Serial/isrSerialRx.c"\r
+\r
+\r
+ /*\r
+ * Was the interrupt the Tx register becoming empty?\r
+ */\r
+ #include "../Serial/isrSerialTx.c"\r
+\r
+\r
+\r
+/*******************************************************************************\r
+** DO NOT MODIFY ANYTHING BELOW THIS LINE\r
+*******************************************************************************/\r
+ /*\r
+ * Was a contextswitch requested by one of the\r
+ * interrupthandlers?\r
+ */\r
+ if ( uxSwitchRequested )\r
+ {\r
+ vTaskSwitchContext();\r
+ }\r
+ \r
+ /*\r
+ * Restore the context of the (possibly other) task.\r
+ */\r
+ portRESTORE_CONTEXT();\r
+\r
+ #pragma asmline retfie 0\r
+}\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+Changes from V3.0.0\r
+\r
+Changes from V3.0.1\r
+*/\r
+\r
+/*\r
+ * Instead of the normal single demo application, the PIC18F demo is split \r
+ * into several smaller programs of which this is the sixth. This enables the \r
+ * demo's to be executed on the RAM limited PIC-devices.\r
+ *\r
+ * The Demo6 project is configured for a PIC18F4620 device. Main.c starts 4 \r
+ * tasks (including the idle task). See the indicated files in the demo/common\r
+ * directory for more information.\r
+ *\r
+ * demo/common/minimal/comtest.c: Creates 2 tasks\r
+ * ATTENTION: Comtest needs a loopback-connector on the serial port.\r
+ *\r
+ * Main.c also creates a check task. This periodically checks that all the \r
+ * other tasks are still running and have not experienced any unexpected \r
+ * results. If all the other tasks are executing correctly an LED is flashed \r
+ * once every mainCHECK_PERIOD milliseconds. If any of the tasks have not \r
+ * executed, or report an error, the frequency of the LED flash will increase \r
+ * to mainERROR_FLASH_RATE.\r
+ *\r
+ * http://www.FreeRTOS.org contains important information on the use of the \r
+ * wizC PIC18F port.\r
+ */\r
+\r
+/* Scheduler include files. */\r
+#include <FreeRTOS.h>\r
+#include <task.h>\r
+\r
+/* Demo app include files. */\r
+#include "partest.h"\r
+#include "serial.h"\r
+#include "comtest.h"\r
+\r
+/* The period between executions of the check task before and after an error\r
+has been discovered. If an error has been discovered the check task runs\r
+more frequently - increasing the LED flash rate. */\r
+#define mainNO_ERROR_CHECK_PERIOD ( ( portTickType ) 10000 / portTICK_RATE_MS )\r
+#define mainERROR_CHECK_PERIOD ( ( portTickType ) 1000 / portTICK_RATE_MS )\r
+#define mainCHECK_TASK_LED ( ( unsigned portCHAR ) 3 )\r
+\r
+/* Priority definitions for some of the tasks. Other tasks just use the idle\r
+priority. */\r
+#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 2 )\r
+#define mainCOMM_TEST_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 1 )\r
+\r
+/* The LED that is toggled whenever a character is transmitted.\r
+mainCOMM_TX_RX_LED + 1 will be toggled every time a character is received. */\r
+#define mainCOMM_TX_RX_LED ( ( unsigned portCHAR ) 0 )\r
+\r
+/* Constants required for the communications. */\r
+#define mainBAUD_RATE ( ( unsigned portLONG ) 57600 )\r
+\r
+/*\r
+ * The task function for the "Check" task.\r
+ */\r
+static portTASK_FUNCTION_PROTO( vErrorChecks, pvParameters );\r
+\r
+/*\r
+ * Checks the unique counts of other tasks to ensure they are still operational.\r
+ * Returns pdTRUE if an error is detected, otherwise pdFALSE.\r
+ */\r
+static portCHAR prvCheckOtherTasksAreStillRunning( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Creates the tasks, then starts the scheduler. */\r
+void main( void )\r
+{\r
+ /* Initialise the required hardware. */\r
+ vParTestInitialise();\r
+\r
+ /* Start a few of the standard demo tasks found in the demo\common directory. */\r
+ vAltStartComTestTasks( mainCOMM_TEST_PRIORITY, mainBAUD_RATE, mainCOMM_TX_RX_LED );\r
+\r
+ /* Start the check task defined in this file. */\r
+ xTaskCreate( vErrorChecks, ( const portCHAR * const ) "Check", portMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
+\r
+ /* Start the scheduler. Will never return here. */\r
+ vTaskStartScheduler();\r
+\r
+ while(1) /* This point should never be reached. */\r
+ {\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portTASK_FUNCTION( vErrorChecks, pvParameters )\r
+{\r
+portTickType xLastCheckTime;\r
+portTickType xDelayTime = mainNO_ERROR_CHECK_PERIOD;\r
+portCHAR cErrorOccurred;\r
+\r
+ /* We need to initialise xLastCheckTime prior to the first call to \r
+ vTaskDelayUntil(). */\r
+ xLastCheckTime = xTaskGetTickCount();\r
+ \r
+ /* Cycle for ever, delaying then checking all the other tasks are still\r
+ operating without error. */\r
+ for( ;; )\r
+ {\r
+ /* Wait until it is time to check the other tasks again. */\r
+ vTaskDelayUntil( &xLastCheckTime, xDelayTime );\r
+ \r
+ /* Check all the other tasks are running, and running without ever\r
+ having an error. */\r
+ cErrorOccurred = prvCheckOtherTasksAreStillRunning();\r
+\r
+ /* If an error was detected increase the frequency of the LED flash. */\r
+ if( cErrorOccurred == pdTRUE )\r
+ {\r
+ xDelayTime = mainERROR_CHECK_PERIOD;\r
+ }\r
+\r
+ /* Flash the LED for visual feedback. */\r
+ vParTestToggleLED( mainCHECK_TASK_LED );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portCHAR prvCheckOtherTasksAreStillRunning( void )\r
+{\r
+ portCHAR cErrorHasOccurred = ( portCHAR ) pdFALSE;\r
+\r
+ if( xAreComTestTasksStillRunning() != pdTRUE )\r
+ {\r
+ cErrorHasOccurred = ( portCHAR ) pdTRUE;\r
+ }\r
+\r
+ return cErrorHasOccurred;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
--- /dev/null
+[F29012549]\r
+x=0\r
+y=111\r
+[F15207742]\r
+x=0\r
+y=48\r
+[F26101515]\r
+x=0\r
+y=269\r
+[F28463201]\r
+x=0\r
+y=0\r
+[F20539803]\r
+x=0\r
+y=233\r
+[ProjectGroup]\r
+nFiles=1\r
+FileName0=Demo7.PC\r
+[Project]\r
+nFiles=7\r
+UseAD=0\r
+CompatOpts=0\r
+AutoHead=\r
+IdentifierPrint=0\r
+TreePrint=0\r
+StatementResultPrint=0\r
+SourcePrint=0\r
+spoPrint=0\r
+AsmPrint=0\r
+CaseSens=1\r
+Optimise=45\r
+AProcFreq=40000000\r
+LOptBytes=16\r
+LOptBytesReg=6\r
+TopROM=32767\r
+StackPointer=3839\r
+HeapPointer=3584\r
+HasDoneOptionDialog=1\r
+ASMProcessor=18F4620\r
+UseLinker=0\r
+DEBUGADV=1\r
+Column0=-1\r
+Column1=-1\r
+Column2=259\r
+TabIndex=0\r
+ShowIcons=0\r
+WindowState=0\r
+Top=418\r
+Left=0\r
+Width=339\r
+Height=209\r
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+FileType0_FileType=0\r
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+FileType5_FileType=0\r
+FileType5_DoLast=0\r
+FileType6_Name=..\ParTest\ParTest.c\r
+FileType6_FileType=0\r
+FileType6_DoLast=0\r
+[Debug]\r
+WindowState=0\r
+Top=0\r
+Left=679\r
+Width=338\r
+Height=626\r
+WinNumberIsIndex0=4097\r
+WinNumberIsIndex1=4096\r
+WinNumberIsIndex2=12\r
+WinNumberIsIndex3=9\r
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+WinNumberIsIndex10=1\r
+WinNumberIsIndex11=11\r
+WinNumberIsIndex12=0\r
+nWin=13\r
+HType=0\r
+HFreq=1\r
+ScenixTurbo=1\r
+Watchdog=0\r
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+DBPort=3970\r
+DBBit=3\r
+UseICD=0\r
+AutoSet=1\r
+DBVars=3824\r
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+UsePICKey=2\r
+nTabs=4\r
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+[MainWindow]\r
+WindowState=2\r
+Top=-4\r
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+Width=1032\r
+Height=748\r
+Update=25000\r
+StopOnError=1\r
+[FindRep]\r
+nTextFind=2\r
+nTextReplace=0\r
+TextFind0=vTaskStartScheduler\r
+TextFind1=switch\r
+[EditWindow]\r
+Tab=0\r
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+MarginOn=1\r
+MarginType=2\r
+WindowState=0\r
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--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+Changes from V3.0.0\r
+ + TickRate reduced to 250Hz.\r
+\r
+ + configIDLE_SHOULD_YIELD added.\r
+\r
+Changes from V3.0.1\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. \r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION ( 1 )\r
+#define configUSE_IDLE_HOOK ( 0 )\r
+#define configUSE_TICK_HOOK ( 0 )\r
+#define configTICK_RATE_HZ ( 250 )\r
+#define configMAX_PRIORITIES ( 4 )\r
+#define configMINIMAL_STACK_SIZE portMINIMAL_STACK_SIZE\r
+#define configMAX_TASK_NAME_LEN ( 3 )\r
+#define configUSE_TRACE_FACILITY ( 0 )\r
+#define configUSE_16_BIT_TICKS ( 1 )\r
+#define configIDLE_SHOULD_YIELD ( 1 )\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Set the following definitions to 1 to include the component, or zero\r
+to exclude the component. */\r
+\r
+/* Include/exclude the stated API function. */\r
+#define INCLUDE_vTaskPrioritySet ( 0 )\r
+#define INCLUDE_uxTaskPriorityGet ( 0 )\r
+#define INCLUDE_vTaskDelete ( 1 )\r
+#define INCLUDE_vTaskCleanUpResources ( 0 )\r
+#define INCLUDE_vTaskSuspend ( 0 )\r
+#define INCLUDE_vTaskDelayUntil ( 1 )\r
+#define INCLUDE_vTaskDelay ( 1 )\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+#ifndef _MALLOC_SETTINGS_H\r
+#define _MALLOC_SETTINGS_H\r
+/*********************************************************************\r
+** Title: Dynamic memory (de-)allocation library for wizC.\r
+**\r
+** Author: Marcel van Lieshout\r
+**\r
+** Copyright: (c) 2005, HMCS, Marcel van Lieshout\r
+**\r
+** License: This software is released to the public domain and comes\r
+** without warranty and/or guarantees of any kind. You have\r
+** the right to use, copy, modify and/or (re-)distribute the\r
+** software as long as the reference to the author is\r
+** maintained in the software and a reference to the author\r
+** is included in any documentation of each product in which\r
+** this library (in it's original or in a modified form)\r
+** is used.\r
+*********************************************************************/\r
+\r
+/*********************************************************************\r
+** The model to use\r
+*********************************************************************/\r
+//#define MALLOC_SMALL\r
+#define MALLOC_LARGE\r
+\r
+/*********************************************************************\r
+** The size of the heap\r
+*********************************************************************/\r
+#define MALLOC_HEAP_SIZE (3200)\r
+\r
+/*********************************************************************\r
+** Should released memory be scribbled with 0x55 before releasing it?\r
+*********************************************************************/\r
+//#define MALLOC_SCRIBBLE\r
+\r
+/********************************************************************\r
+** Enable Debug-mode?\r
+*********************************************************************/\r
+//#define MALLOC_DEBUG\r
+\r
+#endif /* _MALLOC_SETTINGS_H */\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+Changes from V3.0.0\r
+ + Several modules predefined to avoid linker problems\r
+\r
+Changes from V3.0.1\r
+*/\r
+\r
+#ifndef _memcpy\r
+ #define _memcpy 1\r
+#endif\r
+\r
+#ifndef _memset\r
+ #define _memset 1\r
+#endif\r
+\r
+#ifndef _strncpy\r
+ #define _strncpy 1\r
+#endif\r
+\r
+\r
+#pragma wizcpp searchpath <../../Common/Include/>\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+Changes from V3.0.0\r
+\r
+Changes from V3.0.1\r
+*/\r
+\r
+/*\r
+** Here are the configuration words set. See the PIC datasheet\r
+** and the wizC manual for an explanation\r
+*/\r
+#include <pic.h>\r
+\r
+/*\r
+** These fuses are for PIC18F4620\r
+*/\r
+#pragma __config _CONFIG1H,_IESO_OFF_1H & _FCMEN_OFF_1H & _OSC_HSPLL_1H\r
+#pragma __config _CONFIG2L,_BORV_21_2L & _BOREN_SBORDIS_2L & _PWRT_ON_2L\r
+#pragma __config _CONFIG2H,_WDTPS_32768_2H & _WDT_OFF_2H\r
+#pragma __config _CONFIG3H,_MCLRE_ON_3H & _LPT1OSC_OFF_3H & _PBADEN_OFF_3H & _CCP2MX_PORTC_3H\r
+#pragma __config _CONFIG4L,_DEBUG_OFF_4L & _XINST_OFF_4L & _LVP_OFF_4L & _STVREN_OFF_4L\r
+#pragma __config _CONFIG5L,_CP3_OFF_5L & _CP2_OFF_5L & _CP1_OFF_5L & _CP0_OFF_5L\r
+#pragma __config _CONFIG5H,_CPD_OFF_5H & _CPB_OFF_5H\r
+#pragma __config _CONFIG6L,_WRT3_OFF_6L & _WRT2_OFF_6L & _WRT1_OFF_6L & _WRT0_OFF_6L\r
+#pragma __config _CONFIG6H,_WRTD_OFF_6H & _WRTB_OFF_6H & _WRTC_OFF_6H\r
+#pragma __config _CONFIG7L,_EBTR3_OFF_7L & _EBTR2_OFF_7L & _EBTR1_OFF_7L & _EBTR0_OFF_7L\r
+#pragma __config _CONFIG7H,_EBTRB_OFF_7H\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* \r
+Changes from V3.0.0\r
+ + Added functionality to only call vTaskSwitchContext() once\r
+ when handling multiple interruptsources in a single interruptcall.\r
+\r
+ + Included Filenames changed to a .c extension to allow stepping through\r
+ code using F7.\r
+\r
+Changes from V3.0.1\r
+*/\r
+\r
+#include <pic.h>\r
+\r
+/* Scheduler include files. */\r
+#include <FreeRTOS.h>\r
+#include <task.h>\r
+#include <queue.h>\r
+\r
+static bit uxSwitchRequested;\r
+\r
+/*\r
+ * Vector for the ISR.\r
+ */\r
+void pointed Interrupt()\r
+{\r
+ /*\r
+ * Save the context of the current task.\r
+ */\r
+ portSAVE_CONTEXT( portINTERRUPTS_FORCED );\r
+\r
+ /*\r
+ * No contextswitch requested yet\r
+ */\r
+ uxSwitchRequested = pdFALSE;\r
+ \r
+ /*\r
+ * Was the interrupt the FreeRTOS SystemTick?\r
+ */\r
+ #include <libFreeRTOS/Drivers/Tick/isrTick.c>\r
+\r
+/*******************************************************************************\r
+** DO NOT MODIFY ANYTHING ABOVE THIS LINE\r
+********************************************************************************\r
+** Enter the includes for the ISR-code of the FreeRTOS drivers below.\r
+**\r
+** You cannot use local variables. Alternatives are:\r
+** - Use static variables (Global RAM usage increases)\r
+** - Call a function (Additional cycles are needed)\r
+** - Use unused SFR's (preferred, no additional overhead)\r
+** See "../Serial/isrSerialTx.c" for an example of this last option\r
+*******************************************************************************/\r
+\r
+\r
+\r
+ /*\r
+ * Was the interrupt a byte being received?\r
+ */\r
+ #include "../Serial/isrSerialRx.c"\r
+\r
+\r
+ /*\r
+ * Was the interrupt the Tx register becoming empty?\r
+ */\r
+ #include "../Serial/isrSerialTx.c"\r
+\r
+\r
+\r
+/*******************************************************************************\r
+** DO NOT MODIFY ANYTHING BELOW THIS LINE\r
+*******************************************************************************/\r
+ /*\r
+ * Was a contextswitch requested by one of the\r
+ * interrupthandlers?\r
+ */\r
+ if ( uxSwitchRequested )\r
+ {\r
+ vTaskSwitchContext();\r
+ }\r
+ \r
+ /*\r
+ * Restore the context of the (possibly other) task.\r
+ */\r
+ portRESTORE_CONTEXT();\r
+\r
+ #pragma asmline retfie 0\r
+}\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+Changes from V3.0.0\r
+\r
+Changes from V3.0.1\r
+*/\r
+\r
+/*\r
+ * Instead of the normal single demo application, the PIC18F demo is split \r
+ * into several smaller programs of which this is the seventh. This enables the \r
+ * demo's to be executed on the RAM limited PIC-devices.\r
+ *\r
+ * The Demo7 project is configured for a PIC18F4620 device. Main.c starts 10 \r
+ * tasks (including the idle task). See the indicated files in the demo/common\r
+ * directory for more information.\r
+ *\r
+ * demo/common/minimal/flash.c: Creates 3 tasks\r
+ * demo/common/minimal/death.c: Creates 1 controltask and\r
+ * creates/deletes 4 suicidaltasks\r
+ *\r
+ * Main.c also creates a check task. This periodically checks that all the \r
+ * other tasks are still running and have not experienced any unexpected \r
+ * results. If all the other tasks are executing correctly an LED is flashed \r
+ * once every mainCHECK_PERIOD milliseconds. If any of the tasks have not \r
+ * executed, or report an error, the frequency of the LED flash will increase \r
+ * to mainERROR_FLASH_RATE.\r
+ *\r
+ * On entry to main an 'X' is transmitted. Monitoring the serial port using a\r
+ * dumb terminal allows for verification that the device is not continuously \r
+ * being reset (no more than one 'X' should be transmitted).\r
+ *\r
+ * http://www.FreeRTOS.org contains important information on the use of the \r
+ * wizC PIC18F port.\r
+ */\r
+\r
+/* Scheduler include files. */\r
+#include <FreeRTOS.h>\r
+#include <task.h>\r
+\r
+/* Demo app include files. */\r
+#include "death.h"\r
+#include "flash.h"\r
+#include "partest.h"\r
+#include "serial.h"\r
+\r
+/* The period between executions of the check task before and after an error\r
+has been discovered. If an error has been discovered the check task runs\r
+more frequently - increasing the LED flash rate. */\r
+#define mainNO_ERROR_CHECK_PERIOD ( ( portTickType ) 10000 / portTICK_RATE_MS )\r
+#define mainERROR_CHECK_PERIOD ( ( portTickType ) 1000 / portTICK_RATE_MS )\r
+#define mainCHECK_TASK_LED ( ( unsigned portCHAR ) 3 )\r
+\r
+/* Priority definitions for some of the tasks. Other tasks just use the idle\r
+priority. */\r
+#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 2 )\r
+#define mainLED_FLASH_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 2 )\r
+#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 1 )\r
+\r
+/* Constants required for the communications. Only one character is ever \r
+transmitted. */\r
+#define mainCOMMS_QUEUE_LENGTH ( ( unsigned portCHAR ) 5 )\r
+#define mainNO_BLOCK ( ( portTickType ) 0 )\r
+#define mainBAUD_RATE ( ( unsigned portLONG ) 57600 )\r
+\r
+/*\r
+ * The task function for the "Check" task.\r
+ */\r
+static portTASK_FUNCTION_PROTO( vErrorChecks, pvParameters );\r
+\r
+/*\r
+ * Checks the unique counts of other tasks to ensure they are still operational.\r
+ * Returns pdTRUE if an error is detected, otherwise pdFALSE.\r
+ */\r
+static portCHAR prvCheckOtherTasksAreStillRunning( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Creates the tasks, then starts the scheduler. */\r
+void main( void )\r
+{\r
+ /* Initialise the required hardware. */\r
+ vParTestInitialise();\r
+\r
+ /* Send a character so we have some visible feedback of a reset. */\r
+ xSerialPortInitMinimal( mainBAUD_RATE, mainCOMMS_QUEUE_LENGTH );\r
+ xSerialPutChar( NULL, 'X', mainNO_BLOCK );\r
+\r
+ /* Start a few of the standard demo tasks found in the demo\common directory. */\r
+ vStartLEDFlashTasks( mainLED_FLASH_PRIORITY );\r
+\r
+ /* Start the check task defined in this file. */\r
+ xTaskCreate( vErrorChecks, ( const portCHAR * const ) "Check", portMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
+\r
+ /* This task has to be created last as it keeps account of the number of tasks\r
+ it expects to see running. */\r
+ vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );\r
+\r
+ /* Start the scheduler. Will never return here. */\r
+ vTaskStartScheduler();\r
+\r
+ while(1) /* This point should never be reached. */\r
+ {\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portTASK_FUNCTION( vErrorChecks, pvParameters )\r
+{\r
+portTickType xLastCheckTime;\r
+portTickType xDelayTime = mainNO_ERROR_CHECK_PERIOD;\r
+portCHAR cErrorOccurred;\r
+\r
+ /* We need to initialise xLastCheckTime prior to the first call to \r
+ vTaskDelayUntil(). */\r
+ xLastCheckTime = xTaskGetTickCount();\r
+ \r
+ /* Cycle for ever, delaying then checking all the other tasks are still\r
+ operating without error. */\r
+ for( ;; )\r
+ {\r
+ /* Wait until it is time to check the other tasks again. */\r
+ vTaskDelayUntil( &xLastCheckTime, xDelayTime );\r
+ \r
+ /* Check all the other tasks are running, and running without ever\r
+ having an error. */\r
+ cErrorOccurred = prvCheckOtherTasksAreStillRunning();\r
+\r
+ /* If an error was detected increase the frequency of the LED flash. */\r
+ if( cErrorOccurred == pdTRUE )\r
+ {\r
+ xDelayTime = mainERROR_CHECK_PERIOD;\r
+ }\r
+\r
+ /* Flash the LED for visual feedback. */\r
+ vParTestToggleLED( mainCHECK_TASK_LED );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portCHAR prvCheckOtherTasksAreStillRunning( void )\r
+{\r
+ portCHAR cErrorHasOccurred = ( portCHAR ) pdFALSE;\r
+\r
+ if( xIsCreateTaskStillRunning() != pdTRUE )\r
+ {\r
+ cErrorHasOccurred = ( portCHAR ) pdTRUE;\r
+ }\r
+\r
+ return cErrorHasOccurred;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* \r
+Changes from V3.0.0\r
+\r
+Changes from V3.0.1\r
+*/\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include <task.h>\r
+\r
+#include "partest.h"\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple parallel port IO routines for the FED 40pin demo board.\r
+ * The four LED's are connected to D4 to D7.\r
+ *-----------------------------------------------------------*/\r
+\r
+#define partstBIT_AS_OUTPUT ( ( unsigned portSHORT ) 0 )\r
+#define partstSET_OUTPUT ( ( unsigned portSHORT ) 1 )\r
+#define partstCLEAR_OUTPUT ( ( unsigned portSHORT ) 0 )\r
+\r
+#define partstENABLE_GENERAL_IO ( ( unsigned portCHAR ) 7 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestInitialise( void )\r
+{\r
+ /* Set the top four bits of port D to output. */\r
+ bTRD7 = partstBIT_AS_OUTPUT;\r
+ bTRD6 = partstBIT_AS_OUTPUT;\r
+ bTRD5 = partstBIT_AS_OUTPUT;\r
+ bTRD4 = partstBIT_AS_OUTPUT;\r
+\r
+ /* Start with all bits off. */\r
+ bRD7 = partstCLEAR_OUTPUT;\r
+ bRD6 = partstCLEAR_OUTPUT;\r
+ bRD5 = partstCLEAR_OUTPUT;\r
+ bRD4 = partstCLEAR_OUTPUT;\r
+\r
+ /* Enable the driver. */\r
+ ADCON1 = partstENABLE_GENERAL_IO;\r
+ bTRE2 = partstBIT_AS_OUTPUT;\r
+ bRE2 = partstSET_OUTPUT; \r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned portCHAR ucLED, portCHAR cValue )\r
+{\r
+ /* We are only using the top nibble, so LED 0 corresponds to bit 4. */ \r
+ vTaskSuspendAll();\r
+ {\r
+ switch( ucLED )\r
+ {\r
+ case 3 : bRD7 = ( portSHORT ) cValue;\r
+ break;\r
+ case 2 : bRD6 = ( portSHORT ) cValue;\r
+ break;\r
+ case 1 : bRD5 = ( portSHORT ) cValue;\r
+ break;\r
+ case 0 : bRD4 = ( portSHORT ) cValue;\r
+ break;\r
+ default : /* There are only 4 LED's. */\r
+ break;\r
+ }\r
+ }\r
+ xTaskResumeAll();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned portCHAR ucLED )\r
+{\r
+ /* We are only using the top nibble, so LED 0 corresponds to bit 4. */ \r
+ vTaskSuspendAll();\r
+ {\r
+ switch( ucLED )\r
+ {\r
+ case 3 : bRD7 = !bRD7;\r
+ break;\r
+ case 2 : bRD6 = !bRD6;\r
+ break;\r
+ case 1 : bRD5 = !bRD5;\r
+ break;\r
+ case 0 : bRD4 = !bRD4 );\r
+ break;\r
+ default : /* There are only 4 LED's. */\r
+ break;\r
+ }\r
+ }\r
+ xTaskResumeAll();\r
+}\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+Changes from V3.0.0\r
+ + ISRcode pulled inline to reduce stack-usage.\r
+\r
+ + Added functionality to only call vTaskSwitchContext() once\r
+ when handling multiple interruptsources in a single interruptcall.\r
+\r
+ + Filename changed to a .c extension to allow stepping through code\r
+ using F7.\r
+\r
+Changes from V3.0.1\r
+*/\r
+\r
+#ifndef _FREERTOS_SERIAL_ISRSERIALRX_C\r
+#define _FREERTOS_SERIAL_ISRSERIALRX_C\r
+\r
+#define serCONTINUOUS_RX ( 1 )\r
+#define serCLEAR_OVERRUN ( 0 )\r
+\r
+{\r
+ /*\r
+ * Was the interrupt a byte being received?\r
+ */\r
+ if( bRCIF && bRCIE)\r
+ {\r
+ /*\r
+ * Queue to interface between comms API and interrupt routine.\r
+ */\r
+ extern xQueueHandle xRxedChars;\r
+ \r
+ /*\r
+ * Because we are not allowed to use local variables here,\r
+ * PRODL is (ab)used as temporary storage. This is allowed\r
+ * because this SFR will be restored before exiting the ISR.\r
+ */\r
+ extern portCHAR cChar;\r
+ #pragma locate cChar &PRODL\r
+\r
+ /*\r
+ * If there was a framing error, just get and ignore\r
+ * the character\r
+ */\r
+ if( bFERR )\r
+ {\r
+ cChar = RCREG;\r
+ }\r
+ else\r
+ {\r
+ /*\r
+ * Get the character and post it on the queue of Rxed\r
+ * characters. If the post causes a task to wake ask\r
+ * for a context switch as the woken task may have a\r
+ * higher priority than the task we have interrupted.\r
+ */\r
+ cChar = RCREG;\r
+\r
+ /*\r
+ * Clear any overrun errors.\r
+ */\r
+ if( bOERR )\r
+ {\r
+ bCREN = serCLEAR_OVERRUN;\r
+ bCREN = serCONTINUOUS_RX; \r
+ }\r
+\r
+ if( xQueueSendFromISR( xRxedChars, ( const void * ) &cChar, pdFALSE ) )\r
+ {\r
+ uxSwitchRequested = pdTRUE;\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+#endif /* _FREERTOS_SERIAL_ISRSERIALRX_C */\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+Changes from V3.0.0\r
+ + ISRcode pulled inline to reduce stack-usage.\r
+\r
+ + Added functionality to only call vTaskSwitchContext() once\r
+ when handling multiple interruptsources in a single interruptcall.\r
+\r
+ + Filename changed to a .c extension to allow stepping through code\r
+ using F7.\r
+\r
+Changes from V3.0.1\r
+*/\r
+\r
+#ifndef _FREERTOS_SERIAL_ISRSERIALTX_C\r
+#define _FREERTOS_SERIAL_ISRSERIALTX_C\r
+\r
+#define serINTERRUPT_DISABLED ( 0 )\r
+\r
+\r
+{\r
+ /*\r
+ * Was the interrupt the Tx register becoming empty?\r
+ */\r
+ if( bTXIF && bTXIE)\r
+ {\r
+ /*\r
+ * Queue to interface between comms API and interrupt routine.\r
+ */\r
+ extern xQueueHandle xCharsForTx;\r
+\r
+ /*\r
+ * Because we are not allowed to use local variables here,\r
+ * PRODL and PRODH are (ab)used as temporary storage. This\r
+ * is allowed because these SFR's will be restored before\r
+ * exiting the ISR.\r
+ */\r
+ extern portCHAR cChar;\r
+ #pragma locate cChar &PRODL\r
+ extern portBASE_TYPE pxTaskWoken;\r
+ #pragma locate pxTaskWoken &PRODH\r
+\r
+ if( xQueueReceiveFromISR( xCharsForTx, &cChar, &pxTaskWoken ) == pdTRUE )\r
+ {\r
+ /*\r
+ * Send the next character queued for Tx.\r
+ */\r
+ TXREG = cChar;\r
+ }\r
+ else\r
+ {\r
+ /*\r
+ * Queue empty, nothing to send.\r
+ */\r
+ bTXIE = serINTERRUPT_DISABLED;\r
+ }\r
+\r
+ /*\r
+ * If we woke another task, ask for a contextswitch\r
+ */\r
+ if( pxTaskWoken == pdTRUE )\r
+ {\r
+ uxSwitchRequested = pdTRUE;\r
+ }\r
+ }\r
+}\r
+\r
+#endif /* _FREERTOS_SERIAL_ISRSERIALTX_C */\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+Changes from V3.0.0\r
+ + ISRcode removed. Is now pulled inline to reduce stack-usage.\r
+\r
+Changes from V3.0.1\r
+*/\r
+\r
+/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER. */\r
+\r
+/* Scheduler header files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+\r
+#include "serial.h"\r
+\r
+/* Hardware pin definitions. */\r
+#define serTX_PIN bTRC6\r
+#define serRX_PIN bTRC7\r
+\r
+/* Bit/register definitions. */\r
+#define serINPUT ( 1 )\r
+#define serOUTPUT ( 0 )\r
+#define serINTERRUPT_ENABLED ( 1 )\r
+\r
+/* All ISR's use the PIC18 low priority interrupt. */\r
+#define serLOW_PRIORITY ( 0 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Queues to interface between comms API and interrupt routines. */\r
+xQueueHandle xRxedChars; \r
+xQueueHandle xCharsForTx;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portCHAR ucQueueLength )\r
+{\r
+ unsigned portSHORT usSPBRG;\r
+ \r
+ /* Create the queues used by the ISR's to interface to tasks. */\r
+ xRxedChars = xQueueCreate( ucQueueLength, ( unsigned portBASE_TYPE ) sizeof( portCHAR ) );\r
+ xCharsForTx = xQueueCreate( ucQueueLength, ( unsigned portBASE_TYPE ) sizeof( portCHAR ) );\r
+\r
+ portENTER_CRITICAL();\r
+\r
+ /* Setup the IO pins to enable the USART IO. */\r
+ serTX_PIN = serINPUT; // YES really! See datasheet\r
+ serRX_PIN = serINPUT;\r
+\r
+ /* Set the TX config register. */\r
+ TXSTA = 0b00100000;\r
+ // ||||||||--bit0: TX9D = n/a\r
+ // |||||||---bit1: TRMT = ReadOnly\r
+ // ||||||----bit2: BRGH = High speed\r
+ // |||||-----bit3: SENDB = n/a\r
+ // ||||------bit4: SYNC = Asynchronous mode\r
+ // |||-------bit5: TXEN = Transmit enable\r
+ // ||--------bit6: TX9 = 8-bit transmission\r
+ // |---------bit7: CSRC = n/a\r
+\r
+ /* Set the Receive config register. */\r
+ RCSTA = 0b10010000;\r
+ // ||||||||--bit0: RX9D = ReadOnly\r
+ // |||||||---bit1: OERR = ReadOnly\r
+ // ||||||----bit2: FERR = ReadOnly\r
+ // |||||-----bit3: ADDEN = n/a\r
+ // ||||------bit4: CREN = Enable receiver\r
+ // |||-------bit5: SREN = n/a\r
+ // ||--------bit6: RX9 = 8-bit reception\r
+ // |---------bit7: SPEN = Serial port enabled\r
+\r
+ /* Calculate the baud rate generator value.\r
+ We use low-speed (BRGH=0), the formula is\r
+ SPBRG = ( ( FOSC / Desired Baud Rate ) / 64 ) - 1 */\r
+ usSPBRG = ( ( APROCFREQ / ulWantedBaud ) / 64 ) - 1;\r
+ if( usSPBRG > 255 )\r
+ {\r
+ SPBRG = 255;\r
+ }\r
+ else\r
+ {\r
+ SPBRG = usSPBRG;\r
+ }\r
+\r
+ /* Set the serial interrupts to use the same priority as the tick. */\r
+ bTXIP = serLOW_PRIORITY;\r
+ bRCIP = serLOW_PRIORITY;\r
+\r
+ /* Enable the Rx interrupt now, the Tx interrupt will get enabled when\r
+ we have data to send. */\r
+ bRCIE = serINTERRUPT_ENABLED;\r
+ \r
+ portEXIT_CRITICAL();\r
+\r
+ /* Unlike other ports, this serial code does not allow for more than one\r
+ com port. We therefore don't return a pointer to a port structure and \r
+ can instead just return NULL. */\r
+ return NULL;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+xComPortHandle xSerialPortInit( eCOMPort ePort, eBaud eWantedBaud, eParity eWantedParity, eDataBits eWantedDataBits, eStopBits eWantedStopBits, unsigned portCHAR ucBufferLength )\r
+{\r
+ /* This is not implemented in this port.\r
+ Use xSerialPortInitMinimal() instead. */\r
+ return NULL;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, portCHAR *pcRxedChar, portTickType xBlockTime )\r
+{\r
+ /* Get the next character from the buffer. Return false if no characters\r
+ are available, or arrive before xBlockTime expires. */\r
+ if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )\r
+ {\r
+ return ( portCHAR ) pdTRUE;\r
+ }\r
+\r
+ return ( portCHAR ) pdFALSE;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, portCHAR cOutChar, portTickType xBlockTime )\r
+{\r
+ /* Return false if after the block time there is no room on the Tx queue. */\r
+ if( xQueueSend( xCharsForTx, ( const void * ) &cOutChar, xBlockTime ) != ( portCHAR ) pdPASS )\r
+ {\r
+ return pdFAIL;\r
+ }\r
+\r
+ /* Turn interrupt on - ensure the compiler only generates a single \r
+ instruction for this. */\r
+ bTXIE = serINTERRUPT_ENABLED;\r
+\r
+ return pdPASS;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSerialClose( xComPortHandle xPort )\r
+{\r
+ /* Not implemented for this port.\r
+ To implement, turn off the interrupts and delete the memory\r
+ allocated to the queues. */\r
+}\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+#include <lpc210x.h>\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. \r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 58982400 ) /* =14.7456MHz xtal multiplied by 4 using the PLL. */\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 128 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 23 * 1024 ) )\r
+#define configMAX_TASK_NAME_LEN ( 16 )\r
+#define configUSE_TRACE_FACILITY 0\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 1\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+\r
+\r
+\r
+\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+\r
+/* Standard includes. */\r
+#include <stdlib.h>\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Application includes. */\r
+#include "tcp.h"\r
+\r
+/* Misc constants. */\r
+#define tcpPOLL_DELAY ( ( portTickType ) 12 / portTICK_RATE_MS )\r
+#define tcpCONNECTION_DELAY ( ( portTickType ) 8 / portTICK_RATE_MS )\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * This task initialises the hardware then processes one TCP connection at a\r
+ * time. When an HTTP client connects we just simply send a single page then\r
+ * disconnect - reset the socket data and wait for the next connection.\r
+ */\r
+void vHTTPServerTask( void *pvParameters )\r
+{\r
+ /* Reset the network hardware. */\r
+ vTCPHardReset();\r
+\r
+ /* Loop, processing connections are they arrive. */\r
+ for( ;; )\r
+ {\r
+ /* Initialise the TCP interface.\r
+\r
+ The current minimal implementation does not check for buffer overflows\r
+ in the WIZnet hardware, so simply resets all the buffers for each\r
+ connection - and only processes one connection at a time. */\r
+ if( lTCPSoftReset() )\r
+ { \r
+ /* Create the socket that is going to accept incoming connections. */\r
+ if( lTCPCreateSocket() )\r
+ {\r
+ /* Wait for a connection. */\r
+ vTCPListen();\r
+\r
+ /* Process connections as they arrive. This function will only\r
+ return once the connection has been closed. */\r
+ lProcessConnection();\r
+ }\r
+ }\r
+\r
+ /* If we get here then the connection completed or failed. Wait a \r
+ while then try or start again. */\r
+ vTaskDelay( tcpCONNECTION_DELAY ); \r
+ }\r
+}\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef HTTP_H\r
+#define HTTP_H\r
+\r
+void vHTTPServerTask( void *pvParameters );\r
+\r
+#endif\r
--- /dev/null
+# FreeRTOS V4.0.1 - copyright (C) 2003-2006 Richard Barry.\r
+#\r
+# This file is part of the FreeRTOS distribution.\r
+#\r
+# FreeRTOS is free software; you can redistribute it and/or modify\r
+# it under the terms of the GNU General Public License as published by\r
+# the Free Software Foundation; either version 2 of the License, or\r
+# (at your option) any later version.\r
+#\r
+# FreeRTOS is distributed in the hope that it will be useful,\r
+# but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+# GNU General Public License for more details.\r
+#\r
+# You should have received a copy of the GNU General Public License\r
+# along with FreeRTOS; if not, write to the Free Software\r
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+#\r
+# A special exception to the GPL can be applied should you wish to distribute\r
+# a combined work that includes FreeRTOS, without being obliged to provide\r
+# the source code for any proprietary components. See the licensing section \r
+# of http://www.FreeRTOS.org for full details of how and when the exception\r
+# can be applied.\r
+#\r
+# ***************************************************************************\r
+# See http://www.FreeRTOS.org for documentation, latest information, license \r
+# and contact details. Please ensure to read the configuration and relevant \r
+# port sections of the online documentation.\r
+# ***************************************************************************\r
+\r
+\r
+CC=arm-elf-gcc\r
+OBJCOPY=arm-elf-objcopy\r
+ARCH=arm-elf-ar\r
+CRT0=boot.s\r
+USE_THUMB_MODE=YES\r
+DEBUG=-g\r
+OPTIM=-Os\r
+RUN_MODE=RUN_FROM_ROM\r
+LDSCRIPT=lpc2106-rom.ld\r
+\r
+\r
+#\r
+# CFLAGS common to both the THUMB and ARM mode builds\r
+#\r
+CFLAGS=-Wall -D $(RUN_MODE) -D GCC_ARM7 -I. -I../../Source/include \\r
+ -I../Common/include $(DEBUG) -mcpu=arm7tdmi -T$(LDSCRIPT) \\r
+ -Wcast-align $(OPTIM)\r
+\r
+ifeq ($(USE_THUMB_MODE),YES)\r
+ CFLAGS += -mthumb-interwork -D THUMB_INTERWORK\r
+ THUMB_FLAGS=-mthumb\r
+endif\r
+\r
+\r
+LINKER_FLAGS=-Xlinker -oWebServeDemo.elf -Xlinker -M -Xlinker -Map=WebServeDemo.map\r
+\r
+#\r
+# Source files that can be built to THUMB mode.\r
+#\r
+THUMB_SRC = \\r
+../../Source/tasks.c \\r
+../../Source/queue.c \\r
+../../Source/list.c \\r
+../../Source/portable/MemMang/heap_2.c \\r
+../../Source/portable/GCC/ARM7_LPC2000/port.c \\r
+../Common/Minimal/flash.c \\r
+../Common/Minimal/dynamic.c \\r
+../Common/Minimal/semtest.c \\r
+../Common/Minimal/PollQ.c \\r
+../Common/Minimal/BlockQ.c \\r
+../Common/Minimal/integer.c \\r
+../ARM7_LPC2106_GCC/ParTest/ParTest.c \\r
+main.c \\r
+TCP.c \\r
+HTTP_Serv.c \\r
+i2c.c\r
+\r
+#\r
+# Source files that must be built to ARM mode.\r
+#\r
+ARM_SRC = \\r
+../../Source/portable/GCC/ARM7_LPC2000/portISR.c \\r
+i2cISR.c \\r
+TCPISR.c\r
+\r
+#\r
+# Define all object files.\r
+#\r
+ARM_OBJ = $(ARM_SRC:.c=.o)\r
+THUMB_OBJ = $(THUMB_SRC:.c=.o)\r
+\r
+WebServeDemo.hex : WebServeDemo.elf\r
+ $(OBJCOPY) WebServeDemo.elf -O ihex WebServeDemo.hex\r
+\r
+WebServeDemo.elf : $(ARM_OBJ) $(THUMB_OBJ) $(CRT0) Makefile\r
+ $(CC) $(CFLAGS) $(ARM_OBJ) $(THUMB_OBJ) -nostartfiles $(CRT0) $(LINKER_FLAGS)\r
+\r
+$(THUMB_OBJ) : %.o : %.c $(LDSCRIPT) Makefile\r
+ $(CC) -c $(THUMB_FLAGS) $(CFLAGS) $< -o $@\r
+\r
+$(ARM_OBJ) : %.o : %.c $(LDSCRIPT) Makefile\r
+ $(CC) -c $(CFLAGS) $< -o $@\r
+\r
+clean :\r
+ touch makefile\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+ \r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+ Changes from V3.2.3\r
+ \r
+ + Modified char* types to compile without warning when using GCC V4.0.1.\r
+ + Corrected the address to which the MAC address is written. Thanks to\r
+ Bill Knight for this correction.\r
+\r
+ Changes from V3.2.4\r
+\r
+ + Changed the default MAC address to something more realistic.\r
+\r
+*/\r
+\r
+/* Standard includes. */\r
+#include <stdlib.h>\r
+#include <string.h>\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "semphr.h"\r
+#include "tcp.h"\r
+#include "serial.h"\r
+\r
+/* Application includes. */\r
+#include "i2c.h"\r
+#include "html_pages.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Hardwired i2c address of the WIZNet device. */\r
+#define tcpDEVICE_ADDRESS ( ( unsigned portCHAR ) 0x00 )\r
+\r
+/* Constants used to configure the Tx and Rx buffer sizes within the WIZnet\r
+device. */\r
+#define tcp8K_RX ( ( unsigned portCHAR ) 0x03 )\r
+#define tcp8K_TX ( ( unsigned portCHAR ) 0x03 )\r
+\r
+/* Constants used to generate the WIZnet internal buffer addresses. */\r
+#define tcpSINGLE_SOCKET_ADDR_MASK ( ( unsigned portLONG ) 0x1fff )\r
+#define tcpSINGLE_SOCKET_ADDR_OFFSET ( ( unsigned portLONG ) 0x4000 )\r
+\r
+/* Bit definitions of the commands that can be sent to the command register. */\r
+#define tcpRESET_CMD ( ( unsigned portCHAR ) 0x80 )\r
+#define tcpSYS_INIT_CMD ( ( unsigned portCHAR ) 0x01 )\r
+#define tcpSOCK_STREAM ( ( unsigned portCHAR ) 0x01 )\r
+#define tcpSOCK_INIT ( ( unsigned portCHAR ) 0x02 )\r
+#define tcpLISTEN_CMD ( ( unsigned portCHAR ) 0x08 )\r
+#define tcpRECEIVE_CMD ( ( unsigned portCHAR ) 0x40 )\r
+#define tcpDISCONNECT_CMD ( ( unsigned portCHAR ) 0x10 )\r
+#define tcpSEND_CMD ( ( unsigned portCHAR ) 0x20 )\r
+\r
+/* Constants required to handle the interrupts. */\r
+#define tcpCLEAR_EINT0 ( 1 )\r
+#define i2cCLEAR_ALL_INTERRUPTS ( ( unsigned portCHAR ) 0xff )\r
+#define i2cCHANNEL_0_ISR_ENABLE ( ( unsigned portCHAR ) 0x01 )\r
+#define i2cCHANNEL_0_ISR_DISABLE ( ( unsigned portCHAR ) 0x00 )\r
+#define tcpWAKE_ON_EINT0 ( 1 )\r
+#define tcpENABLE_EINT0_FUNCTION ( ( unsigned portLONG ) 0x01 )\r
+#define tcpEINT0_VIC_CHANNEL_BIT ( ( unsigned portLONG ) 0x4000 )\r
+#define tcpEINT0_VIC_CHANNEL ( ( unsigned portLONG ) 14 )\r
+#define tcpEINT0_VIC_ENABLE ( ( unsigned portLONG ) 0x0020 )\r
+\r
+/* Various delays used in the driver. */\r
+#define tcpRESET_DELAY ( ( portTickType ) 16 / portTICK_RATE_MS )\r
+#define tcpINIT_DELAY ( ( portTickType ) 500 / portTICK_RATE_MS )\r
+#define tcpLONG_DELAY ( ( portTickType ) 500 / portTICK_RATE_MS )\r
+#define tcpSHORT_DELAY ( ( portTickType ) 5 / portTICK_RATE_MS )\r
+#define tcpCONNECTION_WAIT_DELAY ( ( portTickType ) 100 / portTICK_RATE_MS )\r
+#define tcpNO_DELAY ( ( portTickType ) 0 )\r
+\r
+/* Length of the data to read for various register reads. */\r
+#define tcpSTATUS_READ_LEN ( ( unsigned portLONG ) 1 )\r
+#define tcpSHADOW_READ_LEN ( ( unsigned portLONG ) 1 )\r
+ \r
+/* Register addresses within the WIZnet device. */\r
+#define tcpCOMMAND_REG ( ( unsigned portSHORT ) 0x0000 )\r
+#define tcpGATEWAY_ADDR_REG ( ( unsigned portSHORT ) 0x0080 )\r
+#define tcpSUBNET_MASK_REG ( ( unsigned portSHORT ) 0x0084 )\r
+#define tcpSOURCE_HA_REG ( ( unsigned portSHORT ) 0x0088 )\r
+#define tpcSOURCE_IP_REG ( ( unsigned portSHORT ) 0x008E )\r
+#define tpcSOCKET_OPT_REG ( ( unsigned portSHORT ) 0x00A1 )\r
+#define tcpSOURCE_PORT_REG ( ( unsigned portSHORT ) 0x00AE )\r
+#define tcpTX_WRITE_POINTER_REG ( ( unsigned portSHORT ) 0x0040 )\r
+#define tcpTX_READ_POINTER_REG ( ( unsigned portSHORT ) 0x0044 )\r
+#define tcpTX_ACK_POINTER_REG ( ( unsigned portSHORT ) 0x0018 )\r
+#define tcpTX_MEM_SIZE_REG ( ( unsigned portSHORT ) 0x0096 )\r
+#define tcpRX_MEM_SIZE_REG ( ( unsigned portSHORT ) 0x0095 )\r
+#define tcpINTERRUPT_STATUS_REG ( ( unsigned portSHORT ) 0x0004 )\r
+#define tcpTX_WRITE_SHADOW_REG ( ( unsigned portSHORT ) 0x01F0 )\r
+#define tcpTX_ACK_SHADOW_REG ( ( unsigned portSHORT ) 0x01E2 )\r
+#define tcpISR_MASK_REG ( ( unsigned portSHORT ) 0x0009 )\r
+#define tcpINTERRUPT_REG ( ( unsigned portSHORT ) 0x0008 )\r
+#define tcpSOCKET_STATE_REG ( ( unsigned portSHORT ) 0x00a0 )\r
+\r
+/* Constants required for hardware setup. */\r
+#define tcpRESET_ACTIVE_LOW ( ( unsigned portLONG ) 0x20 )\r
+#define tcpRESET_ACTIVE_HIGH ( ( unsigned portLONG ) 0x10 )\r
+\r
+/* Constants defining the source of the WIZnet ISR. */\r
+#define tcpISR_SYS_INIT ( ( unsigned portCHAR ) 0x01 )\r
+#define tcpISR_SOCKET_INIT ( ( unsigned portCHAR ) 0x02 )\r
+#define tcpISR_ESTABLISHED ( ( unsigned portCHAR ) 0x04 )\r
+#define tcpISR_CLOSED ( ( unsigned portCHAR ) 0x08 )\r
+#define tcpISR_TIMEOUT ( ( unsigned portCHAR ) 0x10 )\r
+#define tcpISR_TX_COMPLETE ( ( unsigned portCHAR ) 0x20 )\r
+#define tcpISR_RX_COMPLETE ( ( unsigned portCHAR ) 0x40 )\r
+\r
+/* Constants defining the socket status bits. */\r
+#define tcpSTATUS_ESTABLISHED ( ( unsigned portCHAR ) 0x06 )\r
+#define tcpSTATUS_LISTEN ( ( unsigned portCHAR ) 0x02 )\r
+\r
+/* Misc constants. */\r
+#define tcpNO_STATUS_BITS ( ( unsigned portCHAR ) 0x00 )\r
+#define i2cNO_ADDR_REQUIRED ( ( unsigned portSHORT ) 0x0000 )\r
+#define i2cNO_DATA_REQUIRED ( 0x0000 )\r
+#define tcpISR_QUEUE_LENGTH ( ( unsigned portBASE_TYPE ) 10 )\r
+#define tcpISR_QUEUE_ITEM_SIZE ( ( unsigned portBASE_TYPE ) 0 )\r
+#define tcpBUFFER_LEN ( 4 * 1024 )\r
+#define tcpMAX_REGISTER_LEN ( 4 )\r
+#define tcpMAX_ATTEMPTS_TO_CHECK_BUFFER ( 6 )\r
+#define tcpMAX_NON_LISTEN_STAUS_READS ( 5 )\r
+\r
+/* Message definitions. The IP address, MAC address, gateway address, etc.\r
+is set here! */\r
+const unsigned portCHAR const ucDataGAR[] = { 172, 25, 218, 3 }; /* Gateway address. */\r
+const unsigned portCHAR const ucDataMSR[] = { 255, 255, 255, 0 }; /* Subnet mask. */\r
+const unsigned portCHAR const ucDataSIPR[] = { 172, 25, 218, 201 };/* IP address. */\r
+const unsigned portCHAR const ucDataSHAR[] = { 00, 23, 30, 41, 15, 26 }; /* MAC address - DO NOT USE THIS ON A PUBLIC NETWORK! */\r
+\r
+/* Other fixed messages. */\r
+const unsigned portCHAR const ucDataReset[] = { tcpRESET_CMD }; \r
+const unsigned portCHAR const ucDataInit[] = { tcpSYS_INIT_CMD }; \r
+const unsigned portCHAR const ucDataProtocol[] = { tcpSOCK_STREAM };\r
+const unsigned portCHAR const ucDataPort[] = { 0xBA, 0xCC };\r
+const unsigned portCHAR const ucDataSockInit[] = { tcpSOCK_INIT };\r
+const unsigned portCHAR const ucDataTxWritePointer[] = { 0x11, 0x22, 0x00, 0x00 };\r
+const unsigned portCHAR const ucDataTxAckPointer[] = { 0x11, 0x22, 0x00, 0x00 };\r
+const unsigned portCHAR const ucDataTxReadPointer[] = { 0x11, 0x22, 0x00, 0x00 };\r
+const unsigned portCHAR const ucDataListen[] = { tcpLISTEN_CMD };\r
+const unsigned portCHAR const ucDataReceiveCmd[] = { tcpRECEIVE_CMD };\r
+const unsigned portCHAR const ucDataSetTxBufSize[] = { tcp8K_TX };\r
+const unsigned portCHAR const ucDataSetRxBufSize[] = { tcp8K_RX };\r
+const unsigned portCHAR const ucDataSend[] = { tcpSEND_CMD };\r
+const unsigned portCHAR const ucDataDisconnect[] = { tcpDISCONNECT_CMD };\r
+const unsigned portCHAR const ucDataEnableISR[] = { i2cCHANNEL_0_ISR_ENABLE };\r
+const unsigned portCHAR const ucDataDisableISR[] = { i2cCHANNEL_0_ISR_DISABLE };\r
+const unsigned portCHAR const ucDataClearInterrupt[] = { i2cCLEAR_ALL_INTERRUPTS };\r
+\r
+static xSemaphoreHandle xMessageComplete = NULL;\r
+xQueueHandle xTCPISRQueue = NULL;\r
+\r
+/* Dynamically generate and send an html page. */\r
+static void prvSendSamplePage( void );\r
+\r
+/* Read a register from the WIZnet device via the i2c interface. */\r
+static void prvReadRegister( unsigned portCHAR *pucDestination, unsigned portSHORT usAddress, unsigned portLONG ulLength );\r
+\r
+/* Send the entire Tx buffer (the Tx buffer within the WIZnet device). */\r
+static void prvFlushBuffer( unsigned portLONG ulTxAddress );\r
+\r
+/* Write a string to the WIZnet Tx buffer. */\r
+static void prvWriteString( const portCHAR * const pucTxBuffer, portLONG lTxLen, unsigned portLONG *pulTxAddress );\r
+\r
+/* Convert a number to a string. */\r
+void ultoa( unsigned portLONG ulVal, portCHAR *pcBuffer, portLONG lIgnore );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void ultoa( unsigned portLONG ulVal, portCHAR *pcBuffer, portLONG lIgnore )\r
+{\r
+unsigned portLONG lNibble;\r
+portLONG lIndex;\r
+\r
+ /* Simple routine to convert an unsigned long value into a string in hex \r
+ format. */\r
+\r
+ /* For each nibble in the number we are converting. */\r
+ for( lIndex = 0; lIndex < ( sizeof( ulVal ) * 2 ); lIndex++ )\r
+ {\r
+ /* Take the top four bits of the number. */\r
+ lNibble = ( ulVal >> 28 );\r
+\r
+ /* We are converting it to a hex string, so is the number in the range\r
+ 0-10 or A-F? */\r
+ if( lNibble < 10 )\r
+ {\r
+ pcBuffer[ lIndex ] = '0' + lNibble;\r
+ }\r
+ else\r
+ {\r
+ lNibble -= 10;\r
+ pcBuffer[ lIndex ] = 'A' + lNibble;\r
+ }\r
+\r
+ /* Shift off the top nibble so we use the next nibble next time around. */\r
+ ulVal <<= 4;\r
+ } \r
+\r
+ /* Mark the end of the string with a null terminator. */\r
+ pcBuffer[ lIndex ] = 0x00;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvReadRegister( unsigned portCHAR *pucDestination, unsigned portSHORT usAddress, unsigned portLONG ulLength )\r
+{\r
+unsigned portCHAR ucRxBuffer[ tcpMAX_REGISTER_LEN ];\r
+\r
+ /* Read a register value from the WIZnet device. */\r
+\r
+ /* First write out the address of the register we want to read. */\r
+ i2cMessage( ucRxBuffer, i2cNO_DATA_REQUIRED, tcpDEVICE_ADDRESS, usAddress, i2cWRITE, NULL, portMAX_DELAY );\r
+ \r
+ /* Then read back from that address. */\r
+ i2cMessage( ( unsigned portCHAR * ) pucDestination, ulLength, tcpDEVICE_ADDRESS, i2cNO_ADDR_REQUIRED, i2cREAD, xMessageComplete, portMAX_DELAY );\r
+\r
+ /* I2C messages are queued so use the semaphore to wait for the read to \r
+ complete - otherwise we will leave this function before the I2C \r
+ transactions have completed. */\r
+ xSemaphoreTake( xMessageComplete, tcpLONG_DELAY );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vTCPHardReset( void )\r
+{\r
+ /* Physical reset of the WIZnet device by using the GPIO lines to hold the \r
+ WIZnet reset lines active for a few milliseconds. */\r
+\r
+ /* Make sure the interrupt from the WIZnet is disabled. */\r
+ VICIntEnClear |= tcpEINT0_VIC_CHANNEL_BIT;\r
+\r
+ /* If xMessageComplete is NULL then this is the first time that this \r
+ function has been called and the queue and semaphore used in this file\r
+ have not yet been created. */\r
+ if( xMessageComplete == NULL )\r
+ {\r
+ /* Create and obtain the semaphore used when we want to wait for an i2c\r
+ message to be completed. */\r
+ vSemaphoreCreateBinary( xMessageComplete );\r
+ xSemaphoreTake( xMessageComplete, tcpNO_DELAY );\r
+\r
+ /* Create the queue used to communicate between the WIZnet and TCP tasks. */\r
+ xTCPISRQueue = xQueueCreate( tcpISR_QUEUE_LENGTH, tcpISR_QUEUE_ITEM_SIZE );\r
+ }\r
+\r
+ /* Use the GPIO to reset the network hardware. */\r
+ GPIO_IOCLR = tcpRESET_ACTIVE_LOW;\r
+ GPIO_IOSET = tcpRESET_ACTIVE_HIGH;\r
+\r
+ /* Delay with the network hardware in reset for a short while. */\r
+ vTaskDelay( tcpRESET_DELAY );\r
+\r
+ GPIO_IOCLR = tcpRESET_ACTIVE_HIGH;\r
+ GPIO_IOSET = tcpRESET_ACTIVE_LOW;\r
+\r
+ vTaskDelay( tcpINIT_DELAY );\r
+\r
+ /* Setup the EINT0 to interrupt on required events from the WIZnet device.\r
+ First enable the EINT0 function of the pin. */\r
+ PCB_PINSEL1 |= tcpENABLE_EINT0_FUNCTION;\r
+ \r
+ /* We want the TCP comms to wake us from power save. */\r
+ SCB_EXTWAKE = tcpWAKE_ON_EINT0;\r
+\r
+ /* Install the ISR into the VIC - but don't enable it yet! */\r
+ portENTER_CRITICAL();\r
+ {\r
+ extern void ( vEINT0_ISR )( void );\r
+\r
+ VICIntSelect &= ~( tcpEINT0_VIC_CHANNEL_BIT );\r
+ VICVectAddr3 = ( portLONG ) vEINT0_ISR;\r
+\r
+ VICVectCntl3 = tcpEINT0_VIC_CHANNEL | tcpEINT0_VIC_ENABLE;\r
+ }\r
+ portEXIT_CRITICAL();\r
+\r
+ /* Enable interrupts in the WIZnet itself. */\r
+ i2cMessage( ucDataEnableISR, sizeof( ucDataEnableISR ), tcpDEVICE_ADDRESS, tcpISR_MASK_REG, i2cWRITE, NULL, portMAX_DELAY );\r
+\r
+ vTaskDelay( tcpLONG_DELAY );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portLONG lTCPSoftReset( void )\r
+{\r
+unsigned portCHAR ucStatus;\r
+extern volatile portLONG lTransactionCompleted;\r
+\r
+ /* Send a message to the WIZnet device to tell it set all it's registers\r
+ back to their default states. Then setup the WIZnet device as required. */\r
+\r
+ /* Reset the internal WIZnet registers. */\r
+ i2cMessage( ucDataReset, sizeof( ucDataReset ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );\r
+\r
+ /* Now we can configure the protocol. Here the MAC address, gateway \r
+ address, subnet mask and IP address are configured. */\r
+ i2cMessage( ucDataSHAR, sizeof( ucDataSHAR ), tcpDEVICE_ADDRESS, tcpSOURCE_HA_REG, i2cWRITE, NULL, portMAX_DELAY );\r
+ i2cMessage( ucDataGAR, sizeof( ucDataGAR ), tcpDEVICE_ADDRESS, tcpGATEWAY_ADDR_REG, i2cWRITE, NULL, portMAX_DELAY );\r
+ i2cMessage( ucDataMSR, sizeof( ucDataMSR ), tcpDEVICE_ADDRESS, tcpSUBNET_MASK_REG, i2cWRITE, NULL, portMAX_DELAY );\r
+ i2cMessage( ucDataSIPR, sizeof( ucDataSIPR ), tcpDEVICE_ADDRESS, tpcSOURCE_IP_REG, i2cWRITE, NULL, portMAX_DELAY );\r
+ \r
+ /* Next the memory buffers are configured to give all the WIZnet internal\r
+ memory over to a single socket. This gives the socket the maximum internal\r
+ Tx and Rx buffer space. */\r
+ i2cMessage( ucDataSetTxBufSize, sizeof( ucDataSetTxBufSize ), tcpDEVICE_ADDRESS, tcpTX_MEM_SIZE_REG, i2cWRITE, NULL, portMAX_DELAY );\r
+ i2cMessage( ucDataSetRxBufSize, sizeof( ucDataSetRxBufSize ), tcpDEVICE_ADDRESS, tcpRX_MEM_SIZE_REG, i2cWRITE, NULL, portMAX_DELAY );\r
+\r
+ /* Send the sys init command so the above parameters take effect. */\r
+ i2cMessage( ucDataInit, sizeof( ucDataInit ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );\r
+\r
+ /* Seems to like a little wait here. */\r
+ vTaskDelay( tcpINIT_DELAY );\r
+\r
+ /* Read back the status to ensure the system initialised ok. */\r
+ prvReadRegister( &ucStatus, tcpINTERRUPT_STATUS_REG, tcpSTATUS_READ_LEN );\r
+\r
+ /* We should find that the sys init was successful. */\r
+ if( ucStatus != tcpISR_SYS_INIT )\r
+ {\r
+ return ( portLONG ) pdFAIL;\r
+ }\r
+\r
+ /* No i2c errors yet. */\r
+ portENTER_CRITICAL();\r
+ lTransactionCompleted = pdTRUE;\r
+ portEXIT_CRITICAL();\r
+\r
+ return ( portLONG ) pdPASS;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portLONG lTCPCreateSocket( void )\r
+{\r
+unsigned portCHAR ucStatus;\r
+\r
+ /* Create and configure a socket. */\r
+\r
+ /* Setup and init the socket. Here the port number is set and the socket\r
+ is initialised. */\r
+ i2cMessage( ucDataProtocol, sizeof( ucDataProtocol),tcpDEVICE_ADDRESS, tpcSOCKET_OPT_REG, i2cWRITE, NULL, portMAX_DELAY );\r
+ i2cMessage( ucDataPort, sizeof( ucDataPort), tcpDEVICE_ADDRESS, tcpSOURCE_PORT_REG, i2cWRITE, NULL, portMAX_DELAY );\r
+ i2cMessage( ucDataSockInit, sizeof( ucDataSockInit),tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, xMessageComplete, portMAX_DELAY );\r
+\r
+ /* Wait for the Init command to be sent. */\r
+ if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) )\r
+ {\r
+ /* For some reason the message was not transmitted within our block\r
+ period. */\r
+ return ( portLONG ) pdFAIL;\r
+ }\r
+\r
+ /* Allow the socket to initialise. */\r
+ vTaskDelay( tcpINIT_DELAY );\r
+\r
+ /* Read back the status to ensure the socket initialised ok. */\r
+ prvReadRegister( &ucStatus, tcpINTERRUPT_STATUS_REG, tcpSTATUS_READ_LEN );\r
+ \r
+ /* We should find that the socket init was successful. */\r
+ if( ucStatus != tcpISR_SOCKET_INIT )\r
+ {\r
+ return ( portLONG ) pdFAIL;\r
+ }\r
+\r
+\r
+ /* Setup the Tx pointer registers to indicate that the Tx buffer is empty. */\r
+ i2cMessage( ucDataTxReadPointer, sizeof( ucDataTxReadPointer ), tcpDEVICE_ADDRESS, tcpTX_READ_POINTER_REG, i2cWRITE, NULL, portMAX_DELAY );\r
+ vTaskDelay( tcpSHORT_DELAY );\r
+ i2cMessage( ucDataTxWritePointer, sizeof( ucDataTxWritePointer ), tcpDEVICE_ADDRESS, tcpTX_WRITE_POINTER_REG, i2cWRITE, NULL, portMAX_DELAY );\r
+ vTaskDelay( tcpSHORT_DELAY );\r
+ i2cMessage( ucDataTxAckPointer, sizeof( ucDataTxAckPointer ), tcpDEVICE_ADDRESS, tcpTX_ACK_POINTER_REG, i2cWRITE, NULL, portMAX_DELAY );\r
+ vTaskDelay( tcpSHORT_DELAY );\r
+\r
+ return ( portLONG ) pdPASS;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vTCPListen( void )\r
+{\r
+unsigned portCHAR ucISR;\r
+\r
+ /* Start a passive listen on the socket. */\r
+\r
+ /* Enable interrupts in the WizNet device after ensuring none are \r
+ currently pending. */\r
+ while( SCB_EXTINT & tcpCLEAR_EINT0 )\r
+ {\r
+ /* The WIZnet device is still asserting and interrupt so tell it to \r
+ clear. */\r
+ i2cMessage( ucDataClearInterrupt, sizeof( ucDataClearInterrupt ), tcpDEVICE_ADDRESS, tcpINTERRUPT_REG, i2cWRITE, xMessageComplete, portMAX_DELAY );\r
+ xSemaphoreTake( xMessageComplete, tcpLONG_DELAY );\r
+\r
+ vTaskDelay( 1 );\r
+ SCB_EXTINT = tcpCLEAR_EINT0;\r
+ }\r
+\r
+ while( xQueueReceive( xTCPISRQueue, &ucISR, tcpNO_DELAY ) )\r
+ {\r
+ /* Just clearing the queue used by the ISR routine to tell this task\r
+ that the WIZnet device needs attention. */\r
+ }\r
+\r
+ /* Now all the pending interrupts have been cleared we can enable the \r
+ processor interrupts. */\r
+ VICIntEnable |= tcpEINT0_VIC_CHANNEL_BIT;\r
+\r
+ /* Then start listening for incoming connections. */\r
+ i2cMessage( ucDataListen, sizeof( ucDataListen ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portLONG lProcessConnection( void )\r
+{\r
+unsigned portCHAR ucISR, ucState, ucLastState = 2, ucShadow;\r
+extern volatile portLONG lTransactionCompleted;\r
+portLONG lSameStateCount = 0, lDataSent = pdFALSE;\r
+unsigned portLONG ulWritePointer, ulAckPointer;\r
+\r
+ /* No I2C errors can yet have occurred. */\r
+ portENTER_CRITICAL();\r
+ lTransactionCompleted = pdTRUE;\r
+ portEXIT_CRITICAL();\r
+\r
+ /* Keep looping - processing interrupts, until we have completed a \r
+ transaction. This uses the WIZnet in it's simplest form. The socket\r
+ accepts a connection - we process the connection - then close the socket.\r
+ We then go back to reinitialise everything and start again. */\r
+ while( lTransactionCompleted == pdTRUE )\r
+ {\r
+ /* Wait for a message on the queue from the WIZnet ISR. When the \r
+ WIZnet device asserts an interrupt the ISR simply posts a message\r
+ onto this queue to wake this task. */\r
+ if( xQueueReceive( xTCPISRQueue, &ucISR, tcpCONNECTION_WAIT_DELAY ) )\r
+ {\r
+ /* The ISR posted a message on this queue to tell us that the\r
+ WIZnet device asserted an interrupt. The ISR cannot process\r
+ an I2C message so cannot tell us what caused the interrupt so\r
+ we have to query the device here. This task is the highest\r
+ priority in the system so will run immediately following the ISR. */\r
+ prvReadRegister( &ucISR, tcpINTERRUPT_STATUS_REG, tcpSTATUS_READ_LEN );\r
+\r
+ /* Once we have read what caused the ISR we can clear the interrupt\r
+ in the WIZnet. */\r
+ i2cMessage( ucDataClearInterrupt, sizeof( ucDataClearInterrupt ), tcpDEVICE_ADDRESS, tcpINTERRUPT_REG, i2cWRITE, NULL, portMAX_DELAY );\r
+\r
+ /* Now we can clear the processor interrupt and re-enable ready for\r
+ the next. */\r
+ SCB_EXTINT = tcpCLEAR_EINT0;\r
+ VICIntEnable |= tcpEINT0_VIC_CHANNEL_BIT;\r
+ \r
+ /* Process the interrupt ... */\r
+\r
+ if( ucISR & tcpISR_ESTABLISHED )\r
+ {\r
+ /* A connection has been established - respond by sending\r
+ a receive command. */\r
+ i2cMessage( ucDataReceiveCmd, sizeof( ucDataReceiveCmd ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );\r
+ }\r
+ \r
+ if( ucISR & tcpISR_RX_COMPLETE )\r
+ {\r
+ /* We message has been received. This will be an HTTP get \r
+ command. We only have one page to send so just send it without\r
+ regard to what the actual requested page was. */\r
+ prvSendSamplePage();\r
+ }\r
+ \r
+ if( ucISR & tcpISR_TX_COMPLETE )\r
+ {\r
+ /* We have a TX complete interrupt - which oddly does not \r
+ indicate that the message being sent is complete so we cannot\r
+ yet close the socket. Instead we read the position of the Tx\r
+ pointer within the WIZnet device so we know how much data it\r
+ has to send. Later we will read the ack pointer and compare \r
+ this to the Tx pointer to ascertain whether the transmission \r
+ has completed. */\r
+\r
+ /* First read the shadow register. */\r
+ prvReadRegister( &ucShadow, tcpTX_WRITE_SHADOW_REG, tcpSHADOW_READ_LEN );\r
+ \r
+ /* Now a short delay is required. */\r
+ vTaskDelay( tcpSHORT_DELAY );\r
+\r
+ /* Then we can read the real register. */\r
+ prvReadRegister( ( unsigned portCHAR * ) &ulWritePointer, tcpTX_WRITE_POINTER_REG, sizeof( ulWritePointer ) );\r
+\r
+ /* We cannot do anything more here but need to remember that \r
+ this interrupt has occurred. */\r
+ lDataSent = pdTRUE;\r
+ }\r
+ \r
+ if( ucISR & tcpISR_CLOSED )\r
+ {\r
+ /* The socket has been closed so we can leave this function. */\r
+ lTransactionCompleted = pdFALSE;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* We have not received an interrupt from the WIZnet device for a \r
+ while. Read the socket status and check that everything is as\r
+ expected. */\r
+ prvReadRegister( &ucState, tcpSOCKET_STATE_REG, tcpSTATUS_READ_LEN );\r
+ \r
+ if( ( ucState == tcpSTATUS_ESTABLISHED ) && ( lDataSent > 0 ) ) \r
+ {\r
+ /* The socket is established and we have already received a Tx\r
+ end interrupt. We must therefore be waiting for the Tx buffer\r
+ inside the WIZnet device to be empty before we can close the\r
+ socket. \r
+\r
+ Read the Ack pointer register to see if it has caught up with\r
+ the Tx pointer register. First we have to read the shadow \r
+ register. */\r
+ prvReadRegister( &ucShadow, tcpTX_ACK_SHADOW_REG, tcpSHADOW_READ_LEN );\r
+ vTaskDelay( tcpSHORT_DELAY );\r
+ prvReadRegister( ( unsigned portCHAR * ) &ulAckPointer, tcpTX_ACK_POINTER_REG, sizeof( ulWritePointer ) );\r
+\r
+ if( ulAckPointer == ulWritePointer )\r
+ {\r
+ /* The Ack and write pointer are now equal and we can \r
+ safely close the socket. */\r
+ i2cMessage( ucDataDisconnect, sizeof( ucDataDisconnect ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );\r
+ }\r
+ else\r
+ {\r
+ /* Keep a count of how many times we encounter the Tx\r
+ buffer still containing data. */\r
+ lDataSent++;\r
+ if( lDataSent > tcpMAX_ATTEMPTS_TO_CHECK_BUFFER )\r
+ {\r
+ /* Assume we cannot complete sending the data and \r
+ therefore cannot safely close the socket. Start over. */\r
+ vTCPHardReset();\r
+ lTransactionCompleted = pdFALSE;\r
+ }\r
+ }\r
+ }\r
+ else if( ucState != tcpSTATUS_LISTEN )\r
+ {\r
+ /* If we have not yet received a Tx end interrupt we would only \r
+ ever expect to find the socket still listening for any \r
+ sustained period. */\r
+ if( ucState == ucLastState )\r
+ {\r
+ lSameStateCount++;\r
+ if( lSameStateCount > tcpMAX_NON_LISTEN_STAUS_READS )\r
+ { \r
+ /* We are persistently in an unexpected state. Assume\r
+ we cannot safely close the socket and start over. */\r
+ vTCPHardReset();\r
+ lTransactionCompleted = pdFALSE;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* We are in the listen state so are happy that everything\r
+ is as expected. */\r
+ lSameStateCount = 0;\r
+ }\r
+\r
+ /* Remember what state we are in this time around so we can check\r
+ for a persistence on an unexpected state. */\r
+ ucLastState = ucState;\r
+ }\r
+ }\r
+\r
+ /* We are going to reinitialise the WIZnet device so do not want our \r
+ interrupts from the WIZnet to be processed. */\r
+ VICIntEnClear |= tcpEINT0_VIC_CHANNEL_BIT;\r
+ return lTransactionCompleted;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvWriteString( const portCHAR * const pucTxBuffer, portLONG lTxLen, unsigned portLONG *pulTxAddress )\r
+{\r
+unsigned portLONG ulSendAddress;\r
+\r
+ /* Send a string to the Tx buffer internal to the WIZnet device. */\r
+\r
+ /* Calculate the address to which we are going to write in the buffer. */\r
+ ulSendAddress = ( *pulTxAddress & tcpSINGLE_SOCKET_ADDR_MASK ) + tcpSINGLE_SOCKET_ADDR_OFFSET;\r
+\r
+ /* Send the buffer to the calculated address. Use the semaphore so we\r
+ can wait until the entire message has been transferred. */\r
+ i2cMessage( ( unsigned portCHAR * ) pucTxBuffer, lTxLen, tcpDEVICE_ADDRESS, ( unsigned portSHORT ) ulSendAddress, i2cWRITE, xMessageComplete, portMAX_DELAY );\r
+\r
+ /* Wait until the semaphore indicates that the message has been transferred. */\r
+ if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) )\r
+ {\r
+ return;\r
+ }\r
+\r
+ /* Return the new address of the end of the buffer (within the WIZnet \r
+ device). */\r
+ *pulTxAddress += ( unsigned portLONG ) lTxLen;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvFlushBuffer( unsigned portLONG ulTxAddress )\r
+{\r
+unsigned portCHAR ucTxBuffer[ tcpMAX_REGISTER_LEN ];\r
+\r
+ /* We have written some data to the Tx buffer internal to the WIZnet\r
+ device. Now we update the Tx pointer inside the WIZnet then send a\r
+ Send command - which causes the data up to the new Tx pointer to be \r
+ transmitted. */\r
+\r
+ /* Make sure endieness is correct for transmission. */\r
+ ulTxAddress = htonl( ulTxAddress );\r
+\r
+ /* Place the new Tx pointer in the string to be transmitted. */\r
+ ucTxBuffer[ 0 ] = ( unsigned portCHAR ) ( ulTxAddress & 0xff );\r
+ ulTxAddress >>= 8;\r
+ ucTxBuffer[ 1 ] = ( unsigned portCHAR ) ( ulTxAddress & 0xff );\r
+ ulTxAddress >>= 8;\r
+ ucTxBuffer[ 2 ] = ( unsigned portCHAR ) ( ulTxAddress & 0xff );\r
+ ulTxAddress >>= 8;\r
+ ucTxBuffer[ 3 ] = ( unsigned portCHAR ) ( ulTxAddress & 0xff );\r
+ ulTxAddress >>= 8;\r
+\r
+ /* And send it to the WIZnet device. */\r
+ i2cMessage( ucTxBuffer, sizeof( ulTxAddress ), tcpDEVICE_ADDRESS, tcpTX_WRITE_POINTER_REG, i2cWRITE, xMessageComplete, portMAX_DELAY );\r
+\r
+ if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) )\r
+ {\r
+ return;\r
+ }\r
+\r
+ vTaskDelay( tcpSHORT_DELAY );\r
+\r
+ /* Transmit! */\r
+ i2cMessage( ucDataSend, sizeof( ucDataSend ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, xMessageComplete, portMAX_DELAY );\r
+\r
+ if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) )\r
+ {\r
+ return;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSendSamplePage( void )\r
+{\r
+extern portLONG lErrorInTask;\r
+unsigned portLONG ulTxAddress;\r
+unsigned portCHAR ucShadow;\r
+portLONG lIndex;\r
+static unsigned portLONG ulRefreshCount = 0x00;\r
+static portCHAR cPageBuffer[ tcpBUFFER_LEN ];\r
+\r
+\r
+ /* This function just generates a sample page of HTML which gets\r
+ sent each time a client attaches to the socket. The page is created\r
+ from two fixed strings (cSamplePageFirstPart and cSamplePageSecondPart)\r
+ with a bit of dynamically generated data in the middle. */\r
+\r
+ /* We need to know the address to which the html string should be sent\r
+ in the WIZnet Tx buffer. First read the shadow register. */\r
+ prvReadRegister( &ucShadow, tcpTX_WRITE_SHADOW_REG, tcpSHADOW_READ_LEN );\r
+\r
+ /* Now a short delay is required. */\r
+ vTaskDelay( tcpSHORT_DELAY );\r
+\r
+ /* Now we can read the real pointer value. */\r
+ prvReadRegister( ( unsigned portCHAR * ) &ulTxAddress, tcpTX_WRITE_POINTER_REG, sizeof( ulTxAddress ) );\r
+\r
+ /* Make sure endieness is correct. */\r
+ ulTxAddress = htonl( ulTxAddress );\r
+\r
+ /* Send the start of the page. */\r
+ prvWriteString( cSamplePageFirstPart, strlen( cSamplePageFirstPart ), &ulTxAddress );\r
+\r
+ /* Generate a bit of dynamic data and place it in the buffer ready to be\r
+ transmitted. */\r
+ strcpy( cPageBuffer, "<BR>Number of ticks since boot = 0x" );\r
+ lIndex = strlen( cPageBuffer );\r
+ ultoa( xTaskGetTickCount(), &( cPageBuffer[ lIndex ] ), 0 );\r
+ strcat( cPageBuffer, "<br>Number of tasks executing = ");\r
+ lIndex = strlen( cPageBuffer );\r
+ ultoa( ( unsigned portLONG ) uxTaskGetNumberOfTasks(), &( cPageBuffer[ lIndex ] ), 0 );\r
+ strcat( cPageBuffer, "<br>IO port 0 state (used by flash tasks) = 0x" );\r
+ lIndex = strlen( cPageBuffer );\r
+ ultoa( ( unsigned portLONG ) GPIO0_IOPIN, &( cPageBuffer[ lIndex ] ), 0 );\r
+ strcat( cPageBuffer, "<br>Refresh = 0x" );\r
+ lIndex = strlen( cPageBuffer );\r
+ ultoa( ( unsigned portLONG ) ulRefreshCount, &( cPageBuffer[ lIndex ] ), 0 );\r
+ \r
+ if( lErrorInTask )\r
+ {\r
+ strcat( cPageBuffer, "<p>An error has occurred in at least one task." );\r
+ }\r
+ else\r
+ {\r
+ strcat( cPageBuffer, "<p>All tasks executing without error." ); \r
+ }\r
+\r
+ ulRefreshCount++;\r
+\r
+ /* Send the dynamically generated string. */\r
+ prvWriteString( cPageBuffer, strlen( cPageBuffer ), &ulTxAddress );\r
+\r
+ /* Finish the page. */\r
+ prvWriteString( cSamplePageSecondPart, strlen( cSamplePageSecondPart ), &ulTxAddress );\r
+\r
+ /* Tell the WIZnet to send the data we have just written to its Tx buffer. */\r
+ prvFlushBuffer( ulTxAddress );\r
+}\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef TCP_H\r
+#define TCP_H\r
+\r
+#define htonl(A) ((((A) & 0xff000000) >> 24) | (((A) & 0x00ff0000) >> 8) | (((A) & 0x0000ff00) << 8) | (((A) & 0x000000ff) << 24))\r
+\r
+void vTCPHardReset( void );\r
+portLONG lTCPSoftReset( void );\r
+portLONG lTCPCreateSocket( void );\r
+portLONG lTCPListen( void );\r
+portLONG lProcessConnection( void );\r
+void vTCPListen( void );\r
+\r
+#endif\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+\r
+/* Constants required for interrupt management. */\r
+#define tcpCLEAR_VIC_INTERRUPT ( 0 )\r
+#define tcpEINT0_VIC_CHANNEL_BIT ( ( unsigned portLONG ) 0x4000 )\r
+\r
+/* EINT0 interrupt handler. This processes interrupts from the WIZnet device. */\r
+void vEINT0_ISR( void ) __attribute__((naked));\r
+\r
+/* Variable is required for its address, but does not otherwise get used. */\r
+static portLONG lDummyVariable;\r
+\r
+/*\r
+ * When the WIZnet device asserts an interrupt we send an (empty) message to\r
+ * the TCP task. This wakes the task so the interrupt can be processed. The\r
+ * source of the interrupt has to be ascertained by the TCP task as this \r
+ * requires an I2C transaction which cannot be performed from this ISR.\r
+ */\r
+void vEINT0_ISR( void )\r
+{\r
+ portENTER_SWITCHING_ISR();\r
+\r
+ extern xQueueHandle xTCPISRQueue;\r
+ portBASE_TYPE xTaskWoken = pdFALSE;\r
+\r
+ /* Just wake the TCP task so it knows an ISR has occurred. */\r
+ xQueueSendFromISR( xTCPISRQueue, ( void * ) &lDummyVariable, xTaskWoken ); \r
+\r
+ /* We cannot carry on processing interrupts until the TCP task has \r
+ processed this one - so for now interrupts are disabled. The TCP task will\r
+ re-enable it. */\r
+ VICIntEnClear |= tcpEINT0_VIC_CHANNEL_BIT;\r
+\r
+ /* Clear the interrupt bit. */ \r
+ VICVectAddr = tcpCLEAR_VIC_INTERRUPT;\r
+\r
+ /* Switch to the TCP task immediately so the cause of the interrupt can\r
+ be ascertained. It is the responsibility of the TCP task to clear the\r
+ interrupts. */\r
+ portEXIT_SWITCHING_ISR( ( xTaskWoken ) );\r
+}\r
+\r
+\r
--- /dev/null
+ /* Sample initialization file */\r
+\r
+ .extern main\r
+ .extern exit\r
+\r
+ .text\r
+ .code 32\r
+\r
+\r
+ .align 0\r
+\r
+ .extern __bss_beg__\r
+ .extern __bss_end__\r
+ .extern __stack_end__\r
+ .extern __data_beg__\r
+ .extern __data_end__\r
+ .extern __data+beg_src__\r
+\r
+ .global start\r
+ .global endless_loop\r
+\r
+ /* Stack Sizes */\r
+ .set UND_STACK_SIZE, 0x00000004\r
+ .set ABT_STACK_SIZE, 0x00000004\r
+ .set FIQ_STACK_SIZE, 0x00000004\r
+ .set IRQ_STACK_SIZE, 0X00000400\r
+ .set SVC_STACK_SIZE, 0x00000400\r
+\r
+ /* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */\r
+ .set MODE_USR, 0x10 /* User Mode */\r
+ .set MODE_FIQ, 0x11 /* FIQ Mode */\r
+ .set MODE_IRQ, 0x12 /* IRQ Mode */\r
+ .set MODE_SVC, 0x13 /* Supervisor Mode */\r
+ .set MODE_ABT, 0x17 /* Abort Mode */\r
+ .set MODE_UND, 0x1B /* Undefined Mode */\r
+ .set MODE_SYS, 0x1F /* System Mode */\r
+\r
+ .equ I_BIT, 0x80 /* when I bit is set, IRQ is disabled */\r
+ .equ F_BIT, 0x40 /* when F bit is set, FIQ is disabled */\r
+\r
+\r
+start:\r
+_start:\r
+_mainCRTStartup:\r
+\r
+ /* Setup a stack for each mode - note that this only sets up a usable stack\r
+ for system/user, SWI and IRQ modes. Also each mode is setup with\r
+ interrupts initially disabled. */\r
+ ldr r0, .LC6\r
+ msr CPSR_c, #MODE_UND|I_BIT|F_BIT /* Undefined Instruction Mode\r
+ mov sp, r0\r
+ sub r0, r0, #UND_STACK_SIZE\r
+ msr CPSR_c, #MODE_ABT|I_BIT|F_BIT /* Abort Mode */\r
+ mov sp, r0\r
+ sub r0, r0, #ABT_STACK_SIZE\r
+ msr CPSR_c, #MODE_FIQ|I_BIT|F_BIT /* FIQ Mode */\r
+ mov sp, r0\r
+ sub r0, r0, #FIQ_STACK_SIZE\r
+ msr CPSR_c, #MODE_IRQ|I_BIT|F_BIT /* IRQ Mode */\r
+ mov sp, r0\r
+ sub r0, r0, #IRQ_STACK_SIZE\r
+ msr CPSR_c, #MODE_SVC|I_BIT|F_BIT /* Supervisor Mode */\r
+ mov sp, r0\r
+ sub r0, r0, #SVC_STACK_SIZE\r
+ msr CPSR_c, #MODE_SYS|I_BIT|F_BIT /* System Mode */\r
+ mov sp, r0\r
+\r
+ /* We want to start in supervisor mode. Operation will switch to system\r
+ mode when the first task starts. */\r
+ msr CPSR_c, #MODE_SVC|I_BIT|F_BIT\r
+\r
+ /* Clear BSS. */\r
+\r
+ mov a2, #0 /* Fill value */\r
+ mov fp, a2 /* Null frame pointer */\r
+ mov r7, a2 /* Null frame pointer for Thumb */\r
+\r
+ ldr r1, .LC1 /* Start of memory block */\r
+ ldr r3, .LC2 /* End of memory block */\r
+ subs r3, r3, r1 /* Length of block */\r
+ beq .end_clear_loop\r
+ mov r2, #0\r
+\r
+.clear_loop:\r
+ strb r2, [r1], #1\r
+ subs r3, r3, #1\r
+ bgt .clear_loop\r
+\r
+.end_clear_loop:\r
+\r
+ /* Initialise data. */\r
+\r
+ ldr r1, .LC3 /* Start of memory block */\r
+ ldr r2, .LC4 /* End of memory block */\r
+ ldr r3, .LC5\r
+ subs r3, r3, r1 /* Length of block */\r
+ beq .end_set_loop\r
+\r
+.set_loop:\r
+ ldrb r4, [r2], #1\r
+ strb r4, [r1], #1\r
+ subs r3, r3, #1\r
+ bgt .set_loop\r
+\r
+.end_set_loop:\r
+\r
+ mov r0, #0 /* no arguments */\r
+ mov r1, #0 /* no argv either */\r
+\r
+ bl main\r
+\r
+endless_loop:\r
+ b endless_loop\r
+\r
+\r
+ .align 0\r
+\r
+ .LC1:\r
+ .word __bss_beg__\r
+ .LC2:\r
+ .word __bss_end__\r
+ .LC3:\r
+ .word __data_beg__\r
+ .LC4:\r
+ .word __data_beg_src__\r
+ .LC5:\r
+ .word __data_end__\r
+ .LC6:\r
+ .word __stack_end__\r
+\r
+\r
+ /* Setup vector table. Note that undf, pabt, dabt, fiq just execute\r
+ a null loop. */\r
+\r
+.section .startup,"ax"\r
+ .code 32\r
+ .align 0\r
+\r
+ b _start /* reset - _start */\r
+ ldr pc, _undf /* undefined - _undf */\r
+ ldr pc, _swi /* SWI - _swi */\r
+ ldr pc, _pabt /* program abort - _pabt */\r
+ ldr pc, _dabt /* data abort - _dabt */\r
+ nop /* reserved */\r
+ ldr pc, [pc,#-0xFF0] /* IRQ - read the VIC */\r
+ ldr pc, _fiq /* FIQ - _fiq */\r
+\r
+_undf: .word __undf /* undefined */\r
+_swi: .word vPortYieldProcessor /* SWI */\r
+_pabt: .word __pabt /* program abort */\r
+_dabt: .word __dabt /* data abort */\r
+_fiq: .word __fiq /* FIQ */\r
+\r
+__undf: b . /* undefined */\r
+__pabt: b . /* program abort */\r
+__dabt: b . /* data abort */\r
+__fiq: b . /* FIQ */\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef HTML_PAGES_H\r
+#define HTML_PAGES_H\r
+\r
+/* Simply defines some strings that get sent as HTML pages. */\r
+\r
+const portCHAR * const cSamplePageFirstPart =\r
+"HTTP/1.0 200 OK\r\n"\r
+"Content-type: text/html\r\n"\r
+"\r\n" \r
+"<!DOCTYPE HTML PUBLIC \"-//W3C//DTD HTML 4.0 Transitional//EN\">\r\n"\r
+"<html>\r\n"\r
+"<head>\r\n"\r
+"<title>FreeRTOS - Live embedded WEB server demo</title>\r\n"\r
+"</head>\r\n"\r
+"<body BGCOLOR=\"#CCCCFF\">\r\n"\r
+"<font face=\"arial\">\r\n"\r
+"<small><b><a href=\"http://www.freertos.org\" target=\"_top\">FreeRTOS Homepage</a></b></small><p>"\r
+"<H1>Embedded WEB Server<br><small>On the FreeRTOS real time kernel</small></h1>\r\n"\r
+"<p>\r\n"\r
+"<b>This demo is now using FreeRTOS V4.x.x!</b><p>"\r
+"This page is being served by the FreeRTOS embedded WEB server running on an ARM7 microcontroller.\r\n<pre>";\r
+\r
+const portCHAR * const cSamplePageSecondPart =\r
+"</pre>"\r
+"If all is well you should see that 18 tasks are executing - 15 standard demo tasks, the embedded WEB server"\r
+" task, the error check task and the idle task.<p>"\r
+"</font>\r\n"\r
+"</body>\r\n"\r
+"</html>\r\n";\r
+\r
+\r
+\r
+#endif\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+\r
+/* Standard includes. */\r
+#include <stdlib.h>\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "queue.h"\r
+#include "semphr.h"\r
+\r
+/* Application includes. */\r
+#include "i2c.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Constants to setup the microcontroller IO. */\r
+#define mainSDA_ENABLE ( ( unsigned portLONG ) 0x0040 )\r
+#define mainSCL_ENABLE ( ( unsigned portLONG ) 0x0010 )\r
+\r
+/* Bit definitions within the I2CONCLR register. */\r
+#define i2cSTA_BIT ( ( unsigned portCHAR ) 0x20 )\r
+#define i2cSI_BIT ( ( unsigned portCHAR ) 0x08 )\r
+#define i2cSTO_BIT ( ( unsigned portCHAR ) 0x10 )\r
+\r
+/* Constants required to setup the VIC. */\r
+#define i2cI2C_VIC_CHANNEL ( ( unsigned portLONG ) 0x0009 )\r
+#define i2cI2C_VIC_CHANNEL_BIT ( ( unsigned portLONG ) 0x0200 )\r
+#define i2cI2C_VIC_ENABLE ( ( unsigned portLONG ) 0x0020 )\r
+\r
+/* Misc constants. */\r
+#define i2cNO_BLOCK ( ( portTickType ) 0 )\r
+#define i2cQUEUE_LENGTH ( ( unsigned portCHAR ) 5 )\r
+#define i2cEXTRA_MESSAGES ( ( unsigned portCHAR ) 2 )\r
+#define i2cREAD_TX_LEN ( ( unsigned portLONG ) 2 )\r
+#define i2cACTIVE_MASTER_MODE ( ( unsigned portCHAR ) 0x40 )\r
+#define i2cTIMERL ( 200 )\r
+#define i2cTIMERH ( 200 )\r
+\r
+/* Array of message definitions. See the header file for more information\r
+on the structure members. There are two more places in the queue than as\r
+defined by i2cQUEUE_LENGTH. This is to ensure that there is always a free\r
+message available - one can be in the process of being transmitted and one\r
+can be left free. */\r
+static xI2CMessage xTxMessages[ i2cQUEUE_LENGTH + i2cEXTRA_MESSAGES ];\r
+\r
+/* Function in the ARM part of the code used to create the queues. */\r
+extern void vI2CISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxTxMessages, unsigned portLONG **ppulBusFree );\r
+\r
+/* Index to the next free message in the xTxMessages array. */\r
+unsigned portLONG ulNextFreeMessage = ( unsigned portLONG ) 0;\r
+\r
+/* Queue of messages that are waiting transmission. */\r
+static xQueueHandle xMessagesForTx;\r
+\r
+/* Flag to indicate the state of the I2C ISR state machine. */\r
+static unsigned portLONG *pulBusFree;\r
+\r
+/*-----------------------------------------------------------*/\r
+void i2cMessage( const unsigned portCHAR * const pucMessage, portLONG lMessageLength, unsigned portCHAR ucSlaveAddress, unsigned portSHORT usBufferAddress, unsigned portLONG ulDirection, xSemaphoreHandle xMessageCompleteSemaphore, portTickType xBlockTime )\r
+{\r
+extern volatile xI2CMessage *pxCurrentMessage;\r
+xI2CMessage *pxNextFreeMessage;\r
+signed portBASE_TYPE xReturn;\r
+\r
+ portENTER_CRITICAL();\r
+ {\r
+ /* This message is guaranteed to be free as there are two more messages\r
+ than spaces in the queue allowing for one message to be in process of\r
+ being transmitted and one to be left free. */\r
+ pxNextFreeMessage = &( xTxMessages[ ulNextFreeMessage ] );\r
+\r
+ /* Fill the message with the data to be sent. */\r
+\r
+ /* Pointer to the actual data. Only a pointer is stored (i.e. the \r
+ actual data is not copied, so the data being pointed to must still\r
+ be valid when the message eventually gets sent (it may be queued for\r
+ a while. */\r
+ pxNextFreeMessage->pucBuffer = ( unsigned portCHAR * ) pucMessage; \r
+\r
+ /* This is the address of the I2C device we are going to transmit this\r
+ message to. */\r
+ pxNextFreeMessage->ucSlaveAddress = ucSlaveAddress | ( unsigned portCHAR ) ulDirection;\r
+\r
+ /* A semaphore can be used to allow the I2C ISR to indicate that the\r
+ message has been sent. This can be NULL if you don't want to wait for\r
+ the message transmission to complete. */\r
+ pxNextFreeMessage->xMessageCompleteSemaphore = xMessageCompleteSemaphore;\r
+\r
+ /* How many bytes are to be sent? */\r
+ pxNextFreeMessage->lMessageLength = lMessageLength;\r
+\r
+ /* The address within the WIZnet device to which the data will be \r
+ written. This could be the address of a register, or alternatively\r
+ a location within the WIZnet Tx buffer. */\r
+ pxNextFreeMessage->ucBufferAddressLowByte = ( unsigned portCHAR ) ( usBufferAddress & 0xff );\r
+\r
+ /* Second byte of the address. */\r
+ usBufferAddress >>= 8;\r
+ pxNextFreeMessage->ucBufferAddressHighByte = ( unsigned portCHAR ) ( usBufferAddress & 0xff );\r
+\r
+ /* Increment to the next message in the array - with a wrap around check. */\r
+ ulNextFreeMessage++;\r
+ if( ulNextFreeMessage >= ( i2cQUEUE_LENGTH + i2cEXTRA_MESSAGES ) )\r
+ {\r
+ ulNextFreeMessage = ( unsigned portLONG ) 0;\r
+ }\r
+\r
+ /* Is the I2C interrupt in the middle of transmitting a message? */\r
+ if( *pulBusFree == ( unsigned portLONG ) pdTRUE )\r
+ {\r
+ /* No message is currently being sent or queued to be sent. We\r
+ can start the ISR sending this message immediately. */\r
+ pxCurrentMessage = pxNextFreeMessage;\r
+\r
+ I2C_I2CONCLR = i2cSI_BIT; \r
+ I2C_I2CONSET = i2cSTA_BIT;\r
+ \r
+ *pulBusFree = ( unsigned portLONG ) pdFALSE;\r
+ }\r
+ else\r
+ {\r
+ /* The I2C interrupt routine is mid sending a message. Queue\r
+ this message ready to be sent. */\r
+ xReturn = xQueueSend( xMessagesForTx, &pxNextFreeMessage, xBlockTime );\r
+\r
+ /* We may have blocked while trying to queue the message. If this\r
+ was the case then the interrupt would have been enabled and we may\r
+ now find that the I2C interrupt routine is no longer sending a\r
+ message. */\r
+ if( ( *pulBusFree == ( unsigned portLONG ) pdTRUE ) && ( xReturn == pdPASS ) )\r
+ {\r
+ /* Get the next message in the queue (this should be the \r
+ message we just posted) and start off the transmission\r
+ again. */\r
+ xQueueReceive( xMessagesForTx, &pxNextFreeMessage, i2cNO_BLOCK );\r
+ pxCurrentMessage = pxNextFreeMessage;\r
+\r
+ I2C_I2CONCLR = i2cSI_BIT; \r
+ I2C_I2CONSET = i2cSTA_BIT;\r
+ \r
+ *pulBusFree = ( unsigned portLONG ) pdFALSE;\r
+ }\r
+ }\r
+ }\r
+ portEXIT_CRITICAL();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void i2cInit( void )\r
+{\r
+extern void ( vI2C_ISR )( void );\r
+\r
+ /* Create the queue used to send messages to the ISR. */\r
+ vI2CISRCreateQueues( i2cQUEUE_LENGTH, &xMessagesForTx, &pulBusFree );\r
+\r
+ /* Configure the I2C hardware. */\r
+\r
+ I2C_I2CONCLR = 0xff; \r
+\r
+ PCB_PINSEL0 |= mainSDA_ENABLE;\r
+ PCB_PINSEL0 |= mainSCL_ENABLE;\r
+\r
+ I2C_I2SCLL = i2cTIMERL;\r
+ I2C_I2SCLH = i2cTIMERH;\r
+ I2C_I2CONSET = i2cACTIVE_MASTER_MODE;\r
+\r
+ portENTER_CRITICAL();\r
+ {\r
+ /* Setup the VIC for the i2c interrupt. */\r
+ VICIntSelect &= ~( i2cI2C_VIC_CHANNEL_BIT );\r
+ VICIntEnable |= i2cI2C_VIC_CHANNEL_BIT;\r
+ VICVectAddr2 = ( portLONG ) vI2C_ISR;\r
+\r
+ VICVectCntl2 = i2cI2C_VIC_CHANNEL | i2cI2C_VIC_ENABLE;\r
+ }\r
+ portEXIT_CRITICAL();\r
+}\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef I2C_H\r
+#define I2C_H\r
+\r
+/* Structure used to capture the I2C message details. The structure is then\r
+ * queued for processing by the I2C ISR. \r
+ */\r
+typedef struct AN_I2C_MESSAGE\r
+{\r
+ portLONG lMessageLength; /*< How many bytes of data to send or received - excluding the buffer address. */\r
+ unsigned portCHAR ucSlaveAddress; /*< The slave address of the WIZnet on the I2C bus. */\r
+ unsigned portCHAR ucBufferAddressLowByte; /*< The address within the WIZnet device to which data should be read from / written to. */\r
+ unsigned portCHAR ucBufferAddressHighByte; /*< As above, high byte. */\r
+ xSemaphoreHandle xMessageCompleteSemaphore; /*< Contains a reference to a semaphore if the application tasks wants notifying when the message has been transacted. */\r
+ unsigned portCHAR *pucBuffer; /*< Pointer to the buffer from where data will be read for transmission, or into which received data will be placed. */\r
+} xI2CMessage;\r
+\r
+/* Constants to use as the ulDirection parameter of i2cMessage(). */\r
+#define i2cWRITE ( ( unsigned portLONG ) 0 )\r
+#define i2cREAD ( ( unsigned portLONG ) 1 )\r
+\r
+/**\r
+ * Must be called once before any calls to i2cMessage.\r
+ */\r
+void i2cInit( void );\r
+\r
+/**\r
+ * Send or receive a message over the I2C bus.\r
+ *\r
+ * @param pucMessage The data to be transmitted or the buffer into which\r
+ * received data will be placed. \r
+ *\r
+ * @param lMessageLength The number of bytes to either transmit or receive.\r
+ *\r
+ * @param ucSlaveAddress The slave address of the WIZNet device on the I2C bus.\r
+ *\r
+ * @param usBufferAddress The address within the WIZNet device to which data is\r
+ * either written to or read from. The WIZnet has it's\r
+ * own Rx and Tx buffers.\r
+ *\r
+ * @param ulDirection Must be either i2cWRITE or i2cREAD as #defined above.\r
+ *\r
+ * @param xMessageCompleteSemaphore\r
+ * Can be used to pass a semaphore reference if the \r
+ * calling task want notification of when the message has\r
+ * completed. Otherwise NULL can be passed.\r
+ * \r
+ * @param xBlockTime The time to wait for a space in the message queue to \r
+ * become available should one not be available \r
+ * immediately.\r
+ */\r
+void i2cMessage( const unsigned portCHAR * const pucMessage, portLONG lMessageLength, unsigned portCHAR ucSlaveAddress, unsigned portSHORT usBufferAddress, unsigned portLONG ulDirection, xSemaphoreHandle xMessageCompleteSemaphore, portTickType xBlockTime );\r
+\r
+#endif\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+\r
+/* Standard includes. */\r
+#include <stdlib.h>\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+#include "semphr.h"\r
+\r
+/* Application includes. */\r
+#include "i2c.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Bit definitions within the I2CONCLR register. */\r
+#define i2cSTA_BIT ( ( unsigned portCHAR ) 0x20 )\r
+#define i2cSI_BIT ( ( unsigned portCHAR ) 0x08 )\r
+#define i2cSTO_BIT ( ( unsigned portCHAR ) 0x10 )\r
+#define i2cAA_BIT ( ( unsigned portCHAR ) 0x04 )\r
+\r
+/* Status codes for the I2STAT register. */\r
+#define i2cSTATUS_START_TXED ( 0x08 )\r
+#define i2cSTATUS_REP_START_TXED ( 0x10 )\r
+#define i2cSTATUS_TX_ADDR_ACKED ( 0x18 )\r
+#define i2cSTATUS_DATA_TXED ( 0x28 )\r
+#define i2cSTATUS_RX_ADDR_ACKED ( 0x40 )\r
+#define i2cSTATUS_DATA_RXED ( 0x50 )\r
+#define i2cSTATUS_LAST_BYTE_RXED ( 0x58 )\r
+\r
+/* Constants for operation of the VIC. */\r
+#define i2cCLEAR_VIC_INTERRUPT ( 0 )\r
+\r
+/* Misc constants. */\r
+#define i2cJUST_ONE_BYTE_TO_RX ( 1 )\r
+#define i2cBUFFER_ADDRESS_BYTES ( 2 )\r
+\r
+/* End the current transmission and free the bus. */\r
+#define i2cEND_TRANSMISSION( lStatus ) \\r
+{ \\r
+ I2C_I2CONCLR = i2cAA_BIT; \\r
+ I2C_I2CONSET = i2cSTO_BIT; \\r
+ eCurrentState = eSentStart; \\r
+ lTransactionCompleted = lStatus; \\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Valid i2c communication states. */\r
+typedef enum\r
+{\r
+ eSentStart, /*<< Last action was the transmission of a start bit. */\r
+ eSentAddressForWrite, /*<< Last action was the transmission of the slave address we are to write to. */\r
+ eSentAddressForRead, /*<< Last action was the transmission of the slave address we are to read from. */\r
+ eSentData, /*<< Last action was the transmission of a data byte. */\r
+ eReceiveData /*<< We expected data to be received. */\r
+} I2C_STATE;\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Points to the message currently being sent. */\r
+volatile xI2CMessage *pxCurrentMessage = NULL; \r
+\r
+/* The queue of messages waiting to be transmitted. */\r
+static xQueueHandle xMessagesForTx;\r
+\r
+/* Flag used to indicate whether or not the ISR is amid sending a message. */\r
+unsigned portLONG ulBusFree = ( unsigned portLONG ) pdTRUE;\r
+\r
+/* Setting this to true will cause the TCP task to think a message is \r
+complete and thus restart. It can therefore be used under error states\r
+to force a restart. */\r
+volatile portLONG lTransactionCompleted = pdTRUE;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vI2CISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxTxMessages, unsigned portLONG **ppulBusFree )\r
+{\r
+ /* Create the queues used to hold Rx and Tx characters. */\r
+ xMessagesForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( xI2CMessage * ) );\r
+\r
+ /* Pass back a reference to the queue and bus free flag so the I2C API file \r
+ can post messages. */\r
+ *pxTxMessages = xMessagesForTx;\r
+ *ppulBusFree = &ulBusFree;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vI2C_ISR( void ) __attribute__ (( naked ));\r
+void vI2C_ISR( void )\r
+{\r
+ portENTER_SWITCHING_ISR();\r
+\r
+ /* Holds the current transmission state. */ \r
+ static I2C_STATE eCurrentState = eSentStart;\r
+ static portLONG lMessageIndex = -i2cBUFFER_ADDRESS_BYTES; /* There are two address bytes to send prior to the data. */\r
+ portBASE_TYPE xTaskWokenByTx = pdFALSE;\r
+ portLONG lBytesLeft;\r
+\r
+ /* The action taken for this interrupt depends on our current state. */\r
+ switch( eCurrentState )\r
+ {\r
+ case eSentStart : \r
+\r
+ /* We sent a start bit, if it was successful we can\r
+ go on to send the slave address. */\r
+ if( ( I2C_I2STAT == i2cSTATUS_START_TXED ) || ( I2C_I2STAT == i2cSTATUS_REP_START_TXED ) )\r
+ {\r
+ /* Send the slave address. */\r
+ I2C_I2DAT = pxCurrentMessage->ucSlaveAddress;\r
+\r
+ if( pxCurrentMessage->ucSlaveAddress & i2cREAD )\r
+ {\r
+ /* We are then going to read bytes back from the \r
+ slave. */\r
+ eCurrentState = eSentAddressForRead;\r
+ \r
+ /* Initialise the buffer index so the first byte goes\r
+ into the first buffer position. */\r
+ lMessageIndex = 0;\r
+ }\r
+ else\r
+ {\r
+ /* We are then going to write some data to the slave. */\r
+ eCurrentState = eSentAddressForWrite;\r
+\r
+ /* When writing bytes we first have to send the two\r
+ byte buffer address so lMessageIndex is set negative,\r
+ when it reaches 0 it is time to send the actual data. */\r
+ lMessageIndex = -i2cBUFFER_ADDRESS_BYTES;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Could not send the start bit so give up. */\r
+ i2cEND_TRANSMISSION( pdFAIL ); \r
+ }\r
+\r
+ I2C_I2CONCLR = i2cSTA_BIT; \r
+\r
+ break;\r
+\r
+ case eSentAddressForWrite :\r
+\r
+ /* We sent the address of the slave we are going to write to.\r
+ If this was acknowledged we can go on to send the data. */\r
+ if( I2C_I2STAT == i2cSTATUS_TX_ADDR_ACKED )\r
+ {\r
+ /* Start the first byte transmitting which is the \r
+ first byte of the buffer address to which the data will \r
+ be sent. */\r
+ I2C_I2DAT = pxCurrentMessage->ucBufferAddressHighByte;\r
+ eCurrentState = eSentData;\r
+ }\r
+ else\r
+ {\r
+ /* Address was not acknowledged so give up. */\r
+ i2cEND_TRANSMISSION( pdFAIL ); \r
+ } \r
+ break;\r
+\r
+ case eSentAddressForRead :\r
+\r
+ /* We sent the address of the slave we are going to read from.\r
+ If this was acknowledged we can go on to read the data. */\r
+ if( I2C_I2STAT == i2cSTATUS_RX_ADDR_ACKED )\r
+ {\r
+ eCurrentState = eReceiveData;\r
+ if( pxCurrentMessage->lMessageLength > i2cJUST_ONE_BYTE_TO_RX )\r
+ {\r
+ /* Don't ack the last byte of the message. */\r
+ I2C_I2CONSET = i2cAA_BIT;\r
+ } \r
+ }\r
+ else\r
+ {\r
+ /* Something unexpected happened - give up. */\r
+ i2cEND_TRANSMISSION( pdFAIL ); \r
+ }\r
+ break;\r
+\r
+ case eReceiveData :\r
+ \r
+ /* We have just received a byte from the slave. */\r
+ if( ( I2C_I2STAT == i2cSTATUS_DATA_RXED ) || ( I2C_I2STAT == i2cSTATUS_LAST_BYTE_RXED ) )\r
+ {\r
+ /* Buffer the byte just received then increment the index \r
+ so it points to the next free space. */\r
+ pxCurrentMessage->pucBuffer[ lMessageIndex ] = I2C_I2DAT;\r
+ lMessageIndex++;\r
+\r
+ /* How many more bytes are we expecting to receive? */\r
+ lBytesLeft = pxCurrentMessage->lMessageLength - lMessageIndex;\r
+ if( lBytesLeft == ( unsigned portLONG ) 0 )\r
+ {\r
+ /* This was the last byte in the message. */\r
+ i2cEND_TRANSMISSION( pdPASS );\r
+\r
+ /* If xMessageCompleteSemaphore is not null then there\r
+ is a task waiting for this message to complete and we\r
+ must 'give' the semaphore so the task is woken.*/\r
+ if( pxCurrentMessage->xMessageCompleteSemaphore )\r
+ {\r
+ xTaskWokenByTx = xSemaphoreGiveFromISR( pxCurrentMessage->xMessageCompleteSemaphore, xTaskWokenByTx );\r
+ }\r
+\r
+ /* Are there any other messages to transact? */\r
+ if( xQueueReceiveFromISR( xMessagesForTx, &pxCurrentMessage, &xTaskWokenByTx ) == pdTRUE )\r
+ {\r
+ /* Start the next message - which was\r
+ retrieved from the queue. */\r
+ I2C_I2CONSET = i2cSTA_BIT;\r
+ }\r
+ else\r
+ {\r
+ /* No more messages were found to be waiting for\r
+ transaction so the bus is free. */\r
+ ulBusFree = ( unsigned portLONG ) pdTRUE; \r
+ } \r
+ }\r
+ else\r
+ {\r
+ /* There are more bytes to receive but don't ack the \r
+ last byte. */\r
+ if( lBytesLeft <= i2cJUST_ONE_BYTE_TO_RX )\r
+ {\r
+ I2C_I2CONCLR = i2cAA_BIT;\r
+ } \r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Something unexpected happened - give up. */\r
+ i2cEND_TRANSMISSION( pdFAIL ); \r
+ }\r
+\r
+ break;\r
+ \r
+ case eSentData : \r
+\r
+ /* We sent a data byte, if successful send the next byte in \r
+ the message. */\r
+ if( I2C_I2STAT == i2cSTATUS_DATA_TXED )\r
+ {\r
+ /* Index to the next byte to send. */\r
+ lMessageIndex++;\r
+ if( lMessageIndex < 0 )\r
+ {\r
+ /* lMessage index is still negative so we have so far \r
+ only sent the first byte of the buffer address. Send \r
+ the second byte now, then initialise the buffer index\r
+ to zero so the next byte sent comes from the actual \r
+ data buffer. */\r
+ I2C_I2DAT = pxCurrentMessage->ucBufferAddressLowByte;\r
+ }\r
+ else if( lMessageIndex < pxCurrentMessage->lMessageLength )\r
+ {\r
+ /* Simply send the next byte in the tx buffer. */\r
+ I2C_I2DAT = pxCurrentMessage->pucBuffer[ lMessageIndex ]; \r
+ }\r
+ else\r
+ {\r
+ /* No more bytes in this message to be send. Finished \r
+ sending message - send a stop bit. */\r
+ i2cEND_TRANSMISSION( pdPASS );\r
+\r
+ /* If xMessageCompleteSemaphore is not null then there\r
+ is a task waiting for this message to be sent and the\r
+ semaphore must be 'given' to wake the task. */\r
+ if( pxCurrentMessage->xMessageCompleteSemaphore )\r
+ {\r
+ xTaskWokenByTx = xSemaphoreGiveFromISR( pxCurrentMessage->xMessageCompleteSemaphore, xTaskWokenByTx );\r
+ }\r
+\r
+ /* Are there any other messages to transact? */\r
+ if( xQueueReceiveFromISR( xMessagesForTx, &pxCurrentMessage, &xTaskWokenByTx ) == pdTRUE )\r
+ {\r
+ /* Start the next message from the Tx queue. */\r
+ I2C_I2CONSET = i2cSTA_BIT;\r
+ }\r
+ else\r
+ {\r
+ /* No more message were queues for transaction so \r
+ the bus is free. */\r
+ ulBusFree = ( unsigned portLONG ) pdTRUE; \r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Something unexpected happened, give up. */\r
+ i2cEND_TRANSMISSION( pdFAIL ); \r
+ }\r
+ break;\r
+\r
+ default : \r
+ \r
+ /* Should never get here. */\r
+ eCurrentState = eSentStart;\r
+ break;\r
+ } \r
+\r
+ /* Clear the interrupt. */\r
+ I2C_I2CONCLR = i2cSI_BIT;\r
+ VICVectAddr = i2cCLEAR_VIC_INTERRUPT;\r
+\r
+ portEXIT_SWITCHING_ISR( ( xTaskWokenByTx ) );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+MEMORY \r
+{\r
+ flash : ORIGIN = 0, LENGTH = 120K\r
+ ram : ORIGIN = 0x40000000, LENGTH = 64K\r
+}\r
+\r
+__stack_end__ = 0x40000000 + 64K - 4;\r
+\r
+SECTIONS \r
+{\r
+ . = 0;\r
+ startup : { *(.startup)} >flash\r
+\r
+ prog : \r
+ {\r
+ *(.text)\r
+ *(.rodata)\r
+ *(.rodata*)\r
+ *(.glue_7)\r
+ *(.glue_7t)\r
+ } >flash\r
+\r
+ __end_of_text__ = .;\r
+\r
+ .data : \r
+ {\r
+ __data_beg__ = .;\r
+ __data_beg_src__ = __end_of_text__;\r
+ *(.data)\r
+ __data_end__ = .;\r
+ } >ram AT>flash\r
+\r
+ .bss : \r
+ {\r
+ __bss_beg__ = .;\r
+ *(.bss)\r
+ } >ram\r
+\r
+ /* Align here to ensure that the .bss section occupies space up to\r
+ _end. Align after .bss to ensure correct alignment even if the\r
+ .bss section disappears because there are no input sections. */\r
+ . = ALIGN(32 / 8);\r
+}\r
+ . = ALIGN(32 / 8);\r
+ _end = .;\r
+ _bss_end__ = . ; __bss_end__ = . ; __end__ = . ;\r
+ PROVIDE (end = .);\r
+\r
+\r
--- /dev/null
+#ifndef lpc210x_h\r
+#define lpc210x_h\r
+/*******************************************************************************\r
+lpc210x.h - Register defs for Philips LPC210X: LPC2104, LPC2105 and LPC2106\r
+\r
+ \r
+THE SOFTWARE IS DELIVERED "AS IS" WITHOUT WARRANTY OR CONDITION OF ANY KIND, \r
+EITHER EXPRESS, IMPLIED OR STATUTORY. THIS INCLUDES WITHOUT LIMITATION ANY \r
+WARRANTY OR CONDITION WITH RESPECT TO MERCHANTABILITY OR FITNESS FOR ANY \r
+PARTICULAR PURPOSE, OR AGAINST THE INFRINGEMENTS OF INTELLECTUAL PROPERTY RIGHTS \r
+OF OTHERS.\r
+ \r
+This file may be freely used for commercial and non-commercial applications, \r
+including being redistributed with any tools.\r
+\r
+If you find a problem with the file, please report it so that it can be fixed.\r
+\r
+Created by Sten Larsson (sten_larsson at yahoo com)\r
+\r
+Edited by Richard Barry.\r
+*******************************************************************************/\r
+\r
+#define REG8 (volatile unsigned char*)\r
+#define REG16 (volatile unsigned short*)\r
+#define REG32 (volatile unsigned int*)\r
+\r
+\r
+/*##############################################################################\r
+## MISC\r
+##############################################################################*/\r
+\r
+ /* Constants for data to put in IRQ/FIQ Exception Vectors */\r
+#define VECTDATA_IRQ 0xE51FFFF0 /* LDR PC,[PC,#-0xFF0] */\r
+#define VECTDATA_FIQ /* __TODO */\r
+\r
+\r
+/*##############################################################################\r
+## VECTORED INTERRUPT CONTROLLER\r
+##############################################################################*/\r
+\r
+#define VICIRQStatus (*(REG32 (0xFFFFF000)))\r
+#define VICFIQStatus (*(REG32 (0xFFFFF004)))\r
+#define VICRawIntr (*(REG32 (0xFFFFF008)))\r
+#define VICIntSelect (*(REG32 (0xFFFFF00C)))\r
+#define VICIntEnable (*(REG32 (0xFFFFF010)))\r
+#define VICIntEnClear (*(REG32 (0xFFFFF014)))\r
+#define VICSoftInt (*(REG32 (0xFFFFF018)))\r
+#define VICSoftIntClear (*(REG32 (0xFFFFF01C)))\r
+#define VICProtection (*(REG32 (0xFFFFF020)))\r
+#define VICVectAddr (*(REG32 (0xFFFFF030)))\r
+#define VICDefVectAddr (*(REG32 (0xFFFFF034)))\r
+\r
+#define VICVectAddr0 (*(REG32 (0xFFFFF100)))\r
+#define VICVectAddr1 (*(REG32 (0xFFFFF104)))\r
+#define VICVectAddr2 (*(REG32 (0xFFFFF108)))\r
+#define VICVectAddr3 (*(REG32 (0xFFFFF10C)))\r
+#define VICVectAddr4 (*(REG32 (0xFFFFF110)))\r
+#define VICVectAddr5 (*(REG32 (0xFFFFF114)))\r
+#define VICVectAddr6 (*(REG32 (0xFFFFF118)))\r
+#define VICVectAddr7 (*(REG32 (0xFFFFF11C)))\r
+#define VICVectAddr8 (*(REG32 (0xFFFFF120)))\r
+#define VICVectAddr9 (*(REG32 (0xFFFFF124)))\r
+#define VICVectAddr10 (*(REG32 (0xFFFFF128)))\r
+#define VICVectAddr11 (*(REG32 (0xFFFFF12C)))\r
+#define VICVectAddr12 (*(REG32 (0xFFFFF130)))\r
+#define VICVectAddr13 (*(REG32 (0xFFFFF134)))\r
+#define VICVectAddr14 (*(REG32 (0xFFFFF138)))\r
+#define VICVectAddr15 (*(REG32 (0xFFFFF13C)))\r
+\r
+#define VICVectCntl0 (*(REG32 (0xFFFFF200)))\r
+#define VICVectCntl1 (*(REG32 (0xFFFFF204)))\r
+#define VICVectCntl2 (*(REG32 (0xFFFFF208)))\r
+#define VICVectCntl3 (*(REG32 (0xFFFFF20C)))\r
+#define VICVectCntl4 (*(REG32 (0xFFFFF210)))\r
+#define VICVectCntl5 (*(REG32 (0xFFFFF214)))\r
+#define VICVectCntl6 (*(REG32 (0xFFFFF218)))\r
+#define VICVectCntl7 (*(REG32 (0xFFFFF21C)))\r
+#define VICVectCntl8 (*(REG32 (0xFFFFF220)))\r
+#define VICVectCntl9 (*(REG32 (0xFFFFF224)))\r
+#define VICVectCntl10 (*(REG32 (0xFFFFF228)))\r
+#define VICVectCntl11 (*(REG32 (0xFFFFF22C)))\r
+#define VICVectCntl12 (*(REG32 (0xFFFFF230)))\r
+#define VICVectCntl13 (*(REG32 (0xFFFFF234)))\r
+#define VICVectCntl14 (*(REG32 (0xFFFFF238)))\r
+#define VICVectCntl15 (*(REG32 (0xFFFFF23C)))\r
+\r
+#define VICITCR (*(REG32 (0xFFFFF300)))\r
+#define VICITIP1 (*(REG32 (0xFFFFF304)))\r
+#define VICITIP2 (*(REG32 (0xFFFFF308)))\r
+#define VICITOP1 (*(REG32 (0xFFFFF30C)))\r
+#define VICITOP2 (*(REG32 (0xFFFFF310)))\r
+#define VICPeriphID0 (*(REG32 (0xFFFFFFE0)))\r
+#define VICPeriphID1 (*(REG32 (0xFFFFFFE4)))\r
+#define VICPeriphID2 (*(REG32 (0xFFFFFFE8)))\r
+#define VICPeriphID3 (*(REG32 (0xFFFFFFEC)))\r
+\r
+#define VICIntEnClr VICIntEnClear\r
+#define VICSoftIntClr VICSoftIntClear\r
+\r
+\r
+/*##############################################################################\r
+## PCB - Pin Connect Block\r
+##############################################################################*/\r
+\r
+#define PCB_PINSEL0 (*(REG32 (0xE002C000)))\r
+#define PCB_PINSEL1 (*(REG32 (0xE002C004)))\r
+\r
+\r
+/*##############################################################################\r
+## GPIO - General Purpose I/O\r
+##############################################################################*/\r
+\r
+#define GPIO_IOPIN (*(REG32 (0xE0028000))) /* ALTERNATE NAME GPIO = GPIO0 */\r
+#define GPIO_IOSET (*(REG32 (0xE0028004)))\r
+#define GPIO_IODIR (*(REG32 (0xE0028008)))\r
+#define GPIO_IOCLR (*(REG32 (0xE002800C)))\r
+\r
+#define GPIO0_IOPIN (*(REG32 (0xE0028000))) /* ALTERNATE NAME GPIO = GPIO0 */\r
+#define GPIO0_IOSET (*(REG32 (0xE0028004)))\r
+#define GPIO0_IODIR (*(REG32 (0xE0028008)))\r
+#define GPIO0_IOCLR (*(REG32 (0xE002800C)))\r
+\r
+\r
+/*##############################################################################\r
+## UART0 / UART1\r
+##############################################################################*/\r
+\r
+/* ---- UART 0 --------------------------------------------- */\r
+#define UART0_RBR (*(REG32 (0xE000C000)))\r
+#define UART0_THR (*(REG32 (0xE000C000)))\r
+#define UART0_IER (*(REG32 (0xE000C004)))\r
+#define UART0_IIR (*(REG32 (0xE000C008)))\r
+#define UART0_FCR (*(REG32 (0xE000C008)))\r
+#define UART0_LCR (*(REG32 (0xE000C00C)))\r
+#define UART0_LSR (*(REG32 (0xE000C014)))\r
+#define UART0_SCR (*(REG32 (0xE000C01C)))\r
+#define UART0_DLL (*(REG32 (0xE000C000)))\r
+#define UART0_DLM (*(REG32 (0xE000C004)))\r
+\r
+/* ---- UART 1 --------------------------------------------- */\r
+#define UART1_RBR (*(REG32 (0xE0010000)))\r
+#define UART1_THR (*(REG32 (0xE0010000)))\r
+#define UART1_IER (*(REG32 (0xE0010004)))\r
+#define UART1_IIR (*(REG32 (0xE0010008)))\r
+#define UART1_FCR (*(REG32 (0xE0010008)))\r
+#define UART1_LCR (*(REG32 (0xE001000C)))\r
+#define UART1_LSR (*(REG32 (0xE0010014)))\r
+#define UART1_SCR (*(REG32 (0xE001001C)))\r
+#define UART1_DLL (*(REG32 (0xE0010000)))\r
+#define UART1_DLM (*(REG32 (0xE0010004)))\r
+#define UART1_MCR (*(REG32 (0xE0010010)))\r
+#define UART1_MSR (*(REG32 (0xE0010018)))\r
+\r
+\r
+/*##############################################################################\r
+## I2C\r
+##############################################################################*/\r
+\r
+#define I2C_I2CONSET (*(REG32 (0xE001C000)))\r
+#define I2C_I2STAT (*(REG32 (0xE001C004)))\r
+#define I2C_I2DAT (*(REG32 (0xE001C008)))\r
+#define I2C_I2ADR (*(REG32 (0xE001C00C)))\r
+#define I2C_I2SCLH (*(REG32 (0xE001C010)))\r
+#define I2C_I2SCLL (*(REG32 (0xE001C014)))\r
+#define I2C_I2CONCLR (*(REG32 (0xE001C018)))\r
+\r
+\r
+/*##############################################################################\r
+## SPI - Serial Peripheral Interface\r
+##############################################################################*/\r
+\r
+#define SPI_SPCR (*(REG32 (0xE0020000)))\r
+#define SPI_SPSR (*(REG32 (0xE0020004)))\r
+#define SPI_SPDR (*(REG32 (0xE0020008)))\r
+#define SPI_SPCCR (*(REG32 (0xE002000C)))\r
+#define SPI_SPTCR (*(REG32 (0xE0020010)))\r
+#define SPI_SPTSR (*(REG32 (0xE0020014)))\r
+#define SPI_SPTOR (*(REG32 (0xE0020018)))\r
+#define SPI_SPINT (*(REG32 (0xE002001C)))\r
+\r
+\r
+/*##############################################################################\r
+## Timer 0 and Timer 1\r
+##############################################################################*/\r
+\r
+/* ---- Timer 0 -------------------------------------------- */\r
+#define T0_IR (*(REG32 (0xE0004000)))\r
+#define T0_TCR (*(REG32 (0xE0004004)))\r
+#define T0_TC (*(REG32 (0xE0004008)))\r
+#define T0_PR (*(REG32 (0xE000400C)))\r
+#define T0_PC (*(REG32 (0xE0004010)))\r
+#define T0_MCR (*(REG32 (0xE0004014)))\r
+#define T0_MR0 (*(REG32 (0xE0004018)))\r
+#define T0_MR1 (*(REG32 (0xE000401C)))\r
+#define T0_MR2 (*(REG32 (0xE0004020)))\r
+#define T0_MR3 (*(REG32 (0xE0004024)))\r
+#define T0_CCR (*(REG32 (0xE0004028)))\r
+#define T0_CR0 (*(REG32 (0xE000402C)))\r
+#define T0_CR1 (*(REG32 (0xE0004030)))\r
+#define T0_CR2 (*(REG32 (0xE0004034)))\r
+#define T0_CR3 (*(REG32 (0xE0004038)))\r
+#define T0_EMR (*(REG32 (0xE000403C)))\r
+\r
+/* ---- Timer 1 -------------------------------------------- */\r
+#define T1_IR (*(REG32 (0xE0008000)))\r
+#define T1_TCR (*(REG32 (0xE0008004)))\r
+#define T1_TC (*(REG32 (0xE0008008)))\r
+#define T1_PR (*(REG32 (0xE000800C)))\r
+#define T1_PC (*(REG32 (0xE0008010)))\r
+#define T1_MCR (*(REG32 (0xE0008014)))\r
+#define T1_MR0 (*(REG32 (0xE0008018)))\r
+#define T1_MR1 (*(REG32 (0xE000801C)))\r
+#define T1_MR2 (*(REG32 (0xE0008020)))\r
+#define T1_MR3 (*(REG32 (0xE0008024)))\r
+#define T1_CCR (*(REG32 (0xE0008028)))\r
+#define T1_CR0 (*(REG32 (0xE000802C)))\r
+#define T1_CR1 (*(REG32 (0xE0008030)))\r
+#define T1_CR2 (*(REG32 (0xE0008034)))\r
+#define T1_CR3 (*(REG32 (0xE0008038)))\r
+#define T1_EMR (*(REG32 (0xE000803C)))\r
+\r
+\r
+/*##############################################################################\r
+## PWM\r
+##############################################################################*/\r
+\r
+#define PWM_IR (*(REG32 (0xE0014000)))\r
+#define PWM_TCR (*(REG32 (0xE0014004)))\r
+#define PWM_TC (*(REG32 (0xE0014008)))\r
+#define PWM_PR (*(REG32 (0xE001400C)))\r
+#define PWM_PC (*(REG32 (0xE0014010)))\r
+#define PWM_MCR (*(REG32 (0xE0014014)))\r
+#define PWM_MR0 (*(REG32 (0xE0014018)))\r
+#define PWM_MR1 (*(REG32 (0xE001401C)))\r
+#define PWM_MR2 (*(REG32 (0xE0014020)))\r
+#define PWM_MR3 (*(REG32 (0xE0014024)))\r
+#define PWM_MR4 (*(REG32 (0xE0014040)))\r
+#define PWM_MR5 (*(REG32 (0xE0014044)))\r
+#define PWM_MR6 (*(REG32 (0xE0014048)))\r
+#define PWM_EMR (*(REG32 (0xE001403C)))\r
+#define PWM_PCR (*(REG32 (0xE001404C)))\r
+#define PWM_LER (*(REG32 (0xE0014050)))\r
+#define PWM_CCR (*(REG32 (0xE0014028)))\r
+#define PWM_CR0 (*(REG32 (0xE001402C)))\r
+#define PWM_CR1 (*(REG32 (0xE0014030)))\r
+#define PWM_CR2 (*(REG32 (0xE0014034)))\r
+#define PWM_CR3 (*(REG32 (0xE0014038)))\r
+\r
+/*##############################################################################\r
+## RTC\r
+##############################################################################*/\r
+\r
+/* ---- RTC: Miscellaneous Register Group ------------------ */\r
+#define RTC_ILR (*(REG32 (0xE0024000)))\r
+#define RTC_CTC (*(REG32 (0xE0024004)))\r
+#define RTC_CCR (*(REG32 (0xE0024008))) \r
+#define RTC_CIIR (*(REG32 (0xE002400C)))\r
+#define RTC_AMR (*(REG32 (0xE0024010)))\r
+#define RTC_CTIME0 (*(REG32 (0xE0024014)))\r
+#define RTC_CTIME1 (*(REG32 (0xE0024018)))\r
+#define RTC_CTIME2 (*(REG32 (0xE002401C)))\r
+\r
+/* ---- RTC: Timer Control Group --------------------------- */\r
+#define RTC_SEC (*(REG32 (0xE0024020)))\r
+#define RTC_MIN (*(REG32 (0xE0024024)))\r
+#define RTC_HOUR (*(REG32 (0xE0024028)))\r
+#define RTC_DOM (*(REG32 (0xE002402C)))\r
+#define RTC_DOW (*(REG32 (0xE0024030)))\r
+#define RTC_DOY (*(REG32 (0xE0024034)))\r
+#define RTC_MONTH (*(REG32 (0xE0024038)))\r
+#define RTC_YEAR (*(REG32 (0xE002403C)))\r
+\r
+/* ---- RTC: Alarm Control Group --------------------------- */\r
+#define RTC_ALSEC (*(REG32 (0xE0024060)))\r
+#define RTC_ALMIN (*(REG32 (0xE0024064)))\r
+#define RTC_ALHOUR (*(REG32 (0xE0024068)))\r
+#define RTC_ALDOM (*(REG32 (0xE002406C)))\r
+#define RTC_ALDOW (*(REG32 (0xE0024070)))\r
+#define RTC_ALDOY (*(REG32 (0xE0024074)))\r
+#define RTC_ALMON (*(REG32 (0xE0024078)))\r
+#define RTC_ALYEAR (*(REG32 (0xE002407C)))\r
+\r
+/* ---- RTC: Reference Clock Divider Group ----------------- */\r
+#define RTC_PREINT (*(REG32 (0xE0024080)))\r
+#define RTC_PREFRAC (*(REG32 (0xE0024084)))\r
+\r
+\r
+/*##############################################################################\r
+## WD - Watchdog\r
+##############################################################################*/\r
+\r
+#define WD_WDMOD (*(REG32 (0xE0000000)))\r
+#define WD_WDTC (*(REG32 (0xE0000004)))\r
+#define WD_WDFEED (*(REG32 (0xE0000008)))\r
+#define WD_WDTV (*(REG32 (0xE000000C)))\r
+\r
+\r
+/*##############################################################################\r
+## System Control Block\r
+##############################################################################*/\r
+\r
+#define SCB_EXTINT (*(REG32 (0xE01FC140)))\r
+#define SCB_EXTWAKE (*(REG32 (0xE01FC144)))\r
+#define SCB_MEMMAP (*(REG32 (0xE01FC040)))\r
+#define SCB_PLLCON (*(REG32 (0xE01FC080)))\r
+#define SCB_PLLCFG (*(REG32 (0xE01FC084)))\r
+#define SCB_PLLSTAT (*(REG32 (0xE01FC088)))\r
+#define SCB_PLLFEED (*(REG32 (0xE01FC08C)))\r
+#define SCB_PCON (*(REG32 (0xE01FC0C0)))\r
+#define SCB_PCONP (*(REG32 (0xE01FC0C4)))\r
+#define SCB_VPBDIV (*(REG32 (0xE01FC100)))\r
+\r
+/*##############################################################################\r
+## Memory Accelerator Module (MAM)\r
+##############################################################################*/\r
+\r
+#define MAM_TIM (*(REG32 (0xE01FC004)))\r
+#define MAM_CR (*(REG32 (0xE01FC000)))\r
+\r
+#endif /* lpc210x_h */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* \r
+ NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.\r
+ The processor MUST be in supervisor mode when vTaskStartScheduler is \r
+ called. The demo applications included in the FreeRTOS.org download switch\r
+ to supervisor mode prior to main being called. If you are not using one of\r
+ these demo application projects then ensure Supervisor mode is used.\r
+*/\r
+\r
+\r
+/*\r
+ * Program entry point.\r
+ * \r
+ * main() is responsible for setting up the microcontroller peripherals, then\r
+ * starting the demo application tasks. Once the tasks have been created the\r
+ * scheduler is started and main() should never complete.\r
+ *\r
+ * The demo creates the three standard 'flash' tasks to provide some visual\r
+ * feedback that the system and scheduler are still operating correctly.\r
+ *\r
+ * The HTTP server task operates at the highest priority so will always preempt\r
+ * the flash or idle task on TCP/IP events.\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdlib.h>\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "semphr.h"\r
+#include "task.h"\r
+\r
+/* Application includes. */\r
+#include "i2c.h"\r
+#include "HTTP_Serv.h"\r
+#include "flash.h"\r
+#include "partest.h"\r
+#include "dynamic.h"\r
+#include "semtest.h"\r
+#include "PollQ.h"\r
+#include "BlockQ.h"\r
+#include "integer.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Constants to setup the PLL. */\r
+#define mainPLL_MUL_4 ( ( unsigned portCHAR ) 0x0003 )\r
+#define mainPLL_DIV_1 ( ( unsigned portCHAR ) 0x0000 )\r
+#define mainPLL_ENABLE ( ( unsigned portCHAR ) 0x0001 )\r
+#define mainPLL_CONNECT ( ( unsigned portCHAR ) 0x0003 )\r
+#define mainPLL_FEED_BYTE1 ( ( unsigned portCHAR ) 0xaa )\r
+#define mainPLL_FEED_BYTE2 ( ( unsigned portCHAR ) 0x55 )\r
+#define mainPLL_LOCK ( ( unsigned portLONG ) 0x0400 )\r
+\r
+/* Constants to setup the MAM. */\r
+#define mainMAM_TIM_3 ( ( unsigned portCHAR ) 0x03 )\r
+#define mainMAM_MODE_FULL ( ( unsigned portCHAR ) 0x02 )\r
+\r
+/* Constants to setup the peripheral bus. */\r
+#define mainBUS_CLK_FULL ( ( unsigned portCHAR ) 0x01 )\r
+\r
+/* Constants to setup I/O and processor. */\r
+#define mainBUS_CLK_FULL ( ( unsigned portCHAR ) 0x01 )\r
+#define mainLED_TO_OUTPUT ( ( unsigned portLONG ) 0xff0000 )\r
+#define mainJTAG_PORT ( ( unsigned portLONG ) 0x3E0000UL )\r
+\r
+/* Priorities for the demo application tasks. */\r
+#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define mainHTTP_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainERROR_CHECK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+\r
+/* Flash rates of the on board LED to indicate the health of the system. */\r
+#define mainNO_ERROR_DELAY ( 3000 )\r
+#define mainERROR_DELAY ( 500 )\r
+#define mainON_BOARD_LED_BIT ( ( unsigned portLONG ) 0x80 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The Olimex demo board has a single built in LED. This function simply\r
+ * toggles its state. \r
+ */\r
+void prvToggleOnBoardLED( void );\r
+\r
+/*\r
+ * Configure the processor for use with the Olimex demo board.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*\r
+ * Simply check for errors and toggle the onboard LED.\r
+ */\r
+static void prvErrorChecks( void *pvParameters );\r
+\r
+/*\r
+ * Return true if the demo tasks are executing without error - otherwise \r
+ * return false.\r
+ */\r
+static void prvMainCheckOtherTasksAreStillRunning( void );\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Flag set by prvMainCheckOtherTasksAreStillExecuting(). */\r
+portLONG lErrorInTask = pdFALSE;\r
+\r
+/*\r
+ * Application entry point:\r
+ * Starts all the other tasks, then starts the scheduler. \r
+ */\r
+int main( void )\r
+{\r
+ /* Setup the hardware for use with the Olimex demo board. */\r
+ prvSetupHardware();\r
+\r
+ /* Start the standard flash tasks so the WEB server is not the only thing \r
+ running. */\r
+ vStartLEDFlashTasks( mainLED_TASK_PRIORITY );\r
+ vStartSemaphoreTasks( tskIDLE_PRIORITY );\r
+ vStartDynamicPriorityTasks();\r
+ vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
+ vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
+ vStartIntegerMathTasks( tskIDLE_PRIORITY );\r
+\r
+ /* Start the WEB server task and the error check task. */\r
+ xTaskCreate( vHTTPServerTask, ( signed portCHAR * ) "HTTP", configMINIMAL_STACK_SIZE, NULL, mainHTTP_TASK_PRIORITY, NULL );\r
+ xTaskCreate( prvErrorChecks, ( signed portCHAR * ) "Check", configMINIMAL_STACK_SIZE, NULL, mainERROR_CHECK_PRIORITY, NULL );\r
+ \r
+ /* Now all the tasks have been started - start the scheduler.\r
+\r
+ NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.\r
+ The processor MUST be in supervisor mode when vTaskStartScheduler is \r
+ called. The demo applications included in the FreeRTOS.org download switch\r
+ to supervisor mode prior to main being called. If you are not using one of\r
+ these demo application projects then ensure Supervisor mode is used. */\r
+ vTaskStartScheduler();\r
+\r
+ /* Should never reach here! */\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+ #ifdef RUN_FROM_RAM\r
+ /* Remap the interrupt vectors to RAM if we are are running from RAM. */\r
+ SCB_MEMMAP = 2;\r
+ #endif\r
+\r
+ /* Set all GPIO to output other than the P0.14 (BSL), and the JTAG pins. \r
+ The JTAG pins are left as input as I'm not sure what will happen if the \r
+ Wiggler is connected after powerup - not that it would be a good idea to\r
+ do that anyway. */\r
+ GPIO_IODIR = ~( mainJTAG_PORT );\r
+\r
+ /* Setup the PLL to multiply the XTAL input by 4. */\r
+ SCB_PLLCFG = ( mainPLL_MUL_4 | mainPLL_DIV_1 );\r
+\r
+ /* Activate the PLL by turning it on then feeding the correct sequence of\r
+ bytes. */\r
+ SCB_PLLCON = mainPLL_ENABLE;\r
+ SCB_PLLFEED = mainPLL_FEED_BYTE1;\r
+ SCB_PLLFEED = mainPLL_FEED_BYTE2;\r
+\r
+ /* Wait for the PLL to lock... */\r
+ while( !( SCB_PLLSTAT & mainPLL_LOCK ) );\r
+\r
+ /* ...before connecting it using the feed sequence again. */\r
+ SCB_PLLCON = mainPLL_CONNECT;\r
+ SCB_PLLFEED = mainPLL_FEED_BYTE1;\r
+ SCB_PLLFEED = mainPLL_FEED_BYTE2;\r
+\r
+ /* Setup and turn on the MAM. Three cycle access is used due to the fast\r
+ PLL used. It is possible faster overall performance could be obtained by\r
+ tuning the MAM and PLL settings. */\r
+ MAM_TIM = mainMAM_TIM_3;\r
+ MAM_CR = mainMAM_MODE_FULL;\r
+\r
+ /* Setup the peripheral bus to be the same as the PLL output. */\r
+ SCB_VPBDIV = mainBUS_CLK_FULL;\r
+\r
+ /* Initialise the i2c peripheral. */\r
+ i2cInit();\r
+\r
+ /* Initialise the LED's used by the flash tasks. */\r
+ vParTestInitialise();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvMainCheckOtherTasksAreStillRunning( void )\r
+{\r
+ /* Check all the demo tasks (other than the flash tasks) to ensure\r
+ that they are all still running, and that none of them have detected\r
+ an error. */\r
+\r
+ /* This function is called from more than one task. */\r
+ if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ lErrorInTask = pdTRUE;\r
+ }\r
+\r
+ if( xArePollingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ lErrorInTask = pdTRUE;\r
+ }\r
+\r
+ if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ lErrorInTask = pdTRUE;\r
+ }\r
+\r
+ if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )\r
+ {\r
+ lErrorInTask = pdTRUE;\r
+ }\r
+\r
+ if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ lErrorInTask = pdTRUE;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void prvToggleOnBoardLED( void )\r
+{\r
+unsigned portLONG ulState;\r
+\r
+ ulState = GPIO0_IOPIN;\r
+ if( ulState & mainON_BOARD_LED_BIT )\r
+ {\r
+ GPIO_IOCLR = mainON_BOARD_LED_BIT;\r
+ }\r
+ else\r
+ {\r
+ GPIO_IOSET = mainON_BOARD_LED_BIT;\r
+ } \r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvErrorChecks( void *pvParameters )\r
+{\r
+portTickType xDelay = mainNO_ERROR_DELAY;\r
+\r
+ /* The parameters are not used. */\r
+ ( void ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ /* How long we delay depends on whether an error has been detected\r
+ or not. Therefore the flash rate of the on board LED indicates \r
+ whether or not an error has occurred. */\r
+ vTaskDelay( xDelay );\r
+\r
+ /* Update the lErrorInTask flag. */\r
+ prvMainCheckOtherTasksAreStillRunning();\r
+\r
+ if( lErrorInTask )\r
+ {\r
+ /* An error has been found so reduce the delay period and in so\r
+ doing speed up the flash rate of the on board LED. */\r
+ xDelay = mainERROR_DELAY;\r
+ }\r
+\r
+ prvToggleOnBoardLED();\r
+ }\r
+}\r
+\r
--- /dev/null
+<!DOCTYPE Board_Memory_Definition_File>
+<Root name="AT91SAM7S256" >
+ <MemorySegment size="0x00040000" access="ReadOnly" start="0x00100000" name="FLASH" />
+ <MemorySegment size="0x00010000" access="Read/Write" start="0x00200000" name="SRAM" />
+ <MemorySegment size="0xc8" start="0xF0000000" name="User Peripherals" >
+ <RegisterGroup start="0xFFFA0000" name="TC012" >
+ <Register size="4" access="WriteOnly" start="0xFFFA0000" name="TC0_CCR" >
+ <BitField size="1" start="0" name="CLKEN" />
+ <BitField size="1" start="1" name="CLKDIS" />
+ <BitField size="1" start="2" name="SWTRG" />
+ </Register>
+ <Register size="4" start="0xFFFA0004" name="TC0_CMR" >
+ <BitField size="3" start="0" name="TCCLKS" />
+ <BitField size="1" start="3" name="CLKI" />
+ <BitField size="2" start="4" name="BURST" />
+ <BitField size="1" start="6" name="LDBSTOP" />
+ <BitField size="1" start="7" name="LDBDIS" />
+ <BitField size="2" start="8" name="ETRGEDG" />
+ <BitField size="1" start="10" name="ABETRG" />
+ <BitField size="1" start="14" name="CPCTRG" />
+ <BitField size="1" start="15" name="WAVE" />
+ <BitField size="2" start="16" name="LDRA" />
+ <BitField size="2" start="18" name="LDRB" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFA0010" name="TC0_CV" />
+ <Register size="4" start="0xFFFA0014" name="TC0_RA" />
+ <Register size="4" start="0xFFFA0018" name="TC0_RB" />
+ <Register size="4" start="0xFFFA001C" name="TC0_RC" />
+ <Register size="4" access="ReadOnly" start="0xFFFA0020" name="TC0_SR" >
+ <BitField size="1" start="0" name="COVFS" />
+ <BitField size="1" start="1" name="LOVRS" />
+ <BitField size="1" start="2" name="CPAS" />
+ <BitField size="1" start="3" name="CPBS" />
+ <BitField size="1" start="4" name="CPCS" />
+ <BitField size="1" start="5" name="LDRAS" />
+ <BitField size="1" start="6" name="LDRBS" />
+ <BitField size="1" start="7" name="ETRGS" />
+ <BitField size="1" start="16" name="CLKSTA" />
+ <BitField size="1" start="17" name="MTIOA" />
+ <BitField size="1" start="18" name="MTIOB" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFA0024" name="TC0_IER" >
+ <BitField size="1" start="0" name="COVFS" />
+ <BitField size="1" start="1" name="LOVRS" />
+ <BitField size="1" start="2" name="CPAS" />
+ <BitField size="1" start="3" name="CPBS" />
+ <BitField size="1" start="4" name="CPCS" />
+ <BitField size="1" start="5" name="LDRAS" />
+ <BitField size="1" start="6" name="LDRBS" />
+ <BitField size="1" start="7" name="ETRGS" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFA0028" name="TC0_IDR" >
+ <BitField size="1" start="0" name="COVFS" />
+ <BitField size="1" start="1" name="LOVRS" />
+ <BitField size="1" start="2" name="CPAS" />
+ <BitField size="1" start="3" name="CPBS" />
+ <BitField size="1" start="4" name="CPCS" />
+ <BitField size="1" start="5" name="LDRAS" />
+ <BitField size="1" start="6" name="LDRBS" />
+ <BitField size="1" start="7" name="ETRGS" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFA002C" name="TC0_IMR" >
+ <BitField size="1" start="0" name="COVFS" />
+ <BitField size="1" start="1" name="LOVRS" />
+ <BitField size="1" start="2" name="CPAS" />
+ <BitField size="1" start="3" name="CPBS" />
+ <BitField size="1" start="4" name="CPCS" />
+ <BitField size="1" start="5" name="LDRAS" />
+ <BitField size="1" start="6" name="LDRBS" />
+ <BitField size="1" start="7" name="ETRGS" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFA0040" name="TC1_CCR" >
+ <BitField size="1" start="0" name="CLKEN" />
+ <BitField size="1" start="1" name="CLKDIS" />
+ <BitField size="1" start="2" name="SWTRG" />
+ </Register>
+ <Register size="4" start="0xFFFA0044" name="TC1_CMR" >
+ <BitField size="3" start="0" name="TCCLKS" />
+ <BitField size="1" start="3" name="CLKI" />
+ <BitField size="2" start="4" name="BURST" />
+ <BitField size="1" start="6" name="LDBSTOP" />
+ <BitField size="1" start="7" name="LDBDIS" />
+ <BitField size="2" start="8" name="ETRGEDG" />
+ <BitField size="1" start="10" name="ABETRG" />
+ <BitField size="1" start="14" name="CPCTRG" />
+ <BitField size="1" start="15" name="WAVE" />
+ <BitField size="2" start="16" name="LDRA" />
+ <BitField size="2" start="18" name="LDRB" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFA0050" name="TC1_CV" />
+ <Register size="4" start="0xFFFA0054" name="TC1_RA" />
+ <Register size="4" start="0xFFFA0058" name="TC1_RB" />
+ <Register size="4" start="0xFFFA005C" name="TC1_RC" />
+ <Register size="4" access="ReadOnly" start="0xFFFA0060" name="TC1_SR" >
+ <BitField size="1" start="0" name="COVFS" />
+ <BitField size="1" start="1" name="LOVRS" />
+ <BitField size="1" start="2" name="CPAS" />
+ <BitField size="1" start="3" name="CPBS" />
+ <BitField size="1" start="4" name="CPCS" />
+ <BitField size="1" start="5" name="LDRAS" />
+ <BitField size="1" start="6" name="LDRBS" />
+ <BitField size="1" start="7" name="ETRGS" />
+ <BitField size="1" start="16" name="CLKSTA" />
+ <BitField size="1" start="17" name="MTIOA" />
+ <BitField size="1" start="18" name="MTIOB" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFA0064" name="TC1_IER" >
+ <BitField size="1" start="0" name="COVFS" />
+ <BitField size="1" start="1" name="LOVRS" />
+ <BitField size="1" start="2" name="CPAS" />
+ <BitField size="1" start="3" name="CPBS" />
+ <BitField size="1" start="4" name="CPCS" />
+ <BitField size="1" start="5" name="LDRAS" />
+ <BitField size="1" start="6" name="LDRBS" />
+ <BitField size="1" start="7" name="ETRGS" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFA0068" name="TC1_IDR" >
+ <BitField size="1" start="0" name="COVFS" />
+ <BitField size="1" start="1" name="LOVRS" />
+ <BitField size="1" start="2" name="CPAS" />
+ <BitField size="1" start="3" name="CPBS" />
+ <BitField size="1" start="4" name="CPCS" />
+ <BitField size="1" start="5" name="LDRAS" />
+ <BitField size="1" start="6" name="LDRBS" />
+ <BitField size="1" start="7" name="ETRGS" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFA006C" name="TC1_IMR" >
+ <BitField size="1" start="0" name="COVFS" />
+ <BitField size="1" start="1" name="LOVRS" />
+ <BitField size="1" start="2" name="CPAS" />
+ <BitField size="1" start="3" name="CPBS" />
+ <BitField size="1" start="4" name="CPCS" />
+ <BitField size="1" start="5" name="LDRAS" />
+ <BitField size="1" start="6" name="LDRBS" />
+ <BitField size="1" start="7" name="ETRGS" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFA0080" name="TC2_CCR" >
+ <BitField size="1" start="0" name="CLKEN" />
+ <BitField size="1" start="1" name="CLKDIS" />
+ <BitField size="1" start="2" name="SWTRG" />
+ </Register>
+ <Register size="4" start="0xFFFA0084" name="TC2_CMR" >
+ <BitField size="3" start="0" name="TCCLKS" />
+ <BitField size="1" start="3" name="CLKI" />
+ <BitField size="2" start="4" name="BURST" />
+ <BitField size="1" start="6" name="LDBSTOP" />
+ <BitField size="1" start="7" name="LDBDIS" />
+ <BitField size="2" start="8" name="ETRGEDG" />
+ <BitField size="1" start="10" name="ABETRG" />
+ <BitField size="1" start="14" name="CPCTRG" />
+ <BitField size="1" start="15" name="WAVE" />
+ <BitField size="2" start="16" name="LDRA" />
+ <BitField size="2" start="18" name="LDRB" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFA0090" name="TC2_CV" />
+ <Register size="4" start="0xFFFA0094" name="TC2_RA" />
+ <Register size="4" start="0xFFFA0098" name="TC2_RB" />
+ <Register size="4" start="0xFFFA009C" name="TC2_RC" />
+ <Register size="4" access="ReadOnly" start="0xFFFA00A0" name="TC2_SR" >
+ <BitField size="1" start="0" name="COVFS" />
+ <BitField size="1" start="1" name="LOVRS" />
+ <BitField size="1" start="2" name="CPAS" />
+ <BitField size="1" start="3" name="CPBS" />
+ <BitField size="1" start="4" name="CPCS" />
+ <BitField size="1" start="5" name="LDRAS" />
+ <BitField size="1" start="6" name="LDRBS" />
+ <BitField size="1" start="7" name="ETRGS" />
+ <BitField size="1" start="16" name="CLKSTA" />
+ <BitField size="1" start="17" name="MTIOA" />
+ <BitField size="1" start="18" name="MTIOB" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFA00A4" name="TC2_IER" >
+ <BitField size="1" start="0" name="COVFS" />
+ <BitField size="1" start="1" name="LOVRS" />
+ <BitField size="1" start="2" name="CPAS" />
+ <BitField size="1" start="3" name="CPBS" />
+ <BitField size="1" start="4" name="CPCS" />
+ <BitField size="1" start="5" name="LDRAS" />
+ <BitField size="1" start="6" name="LDRBS" />
+ <BitField size="1" start="7" name="ETRGS" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFA00A8" name="TC2_IDR" >
+ <BitField size="1" start="0" name="COVFS" />
+ <BitField size="1" start="1" name="LOVRS" />
+ <BitField size="1" start="2" name="CPAS" />
+ <BitField size="1" start="3" name="CPBS" />
+ <BitField size="1" start="4" name="CPCS" />
+ <BitField size="1" start="5" name="LDRAS" />
+ <BitField size="1" start="6" name="LDRBS" />
+ <BitField size="1" start="7" name="ETRGS" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFA00AC" name="TC2_IMR" >
+ <BitField size="1" start="0" name="COVFS" />
+ <BitField size="1" start="1" name="LOVRS" />
+ <BitField size="1" start="2" name="CPAS" />
+ <BitField size="1" start="3" name="CPBS" />
+ <BitField size="1" start="4" name="CPCS" />
+ <BitField size="1" start="5" name="LDRAS" />
+ <BitField size="1" start="6" name="LDRBS" />
+ <BitField size="1" start="7" name="ETRGS" />
+ </Register>
+ <Register size="4" start="0xFFFA00C0" name="TC012_BCR" />
+ <Register size="4" start="0xFFFA00C4" name="TC012_BMR" >
+ <BitField size="2" start="0" name="TC0XC0S" />
+ <BitField size="2" start="2" name="TC1XC1S" />
+ <BitField size="2" start="4" name="TC2XC2S" />
+ </Register>
+ </RegisterGroup>
+ <RegisterGroup start="0xFFFB0000" name="UDP" >
+ <Register size="4" access="ReadOnly" start="0xFFFB0000" name="USB_FRM_NUM" >
+ <BitField size="11" start="0" name="FRM_NUM" />
+ <BitField size="1" start="16" name="FRM_ERR" />
+ <BitField size="1" start="17" name="FRM_OK" />
+ </Register>
+ <Register size="4" start="0xFFFB0004" name="USB_GLB_STAT" >
+ <BitField size="1" start="0" name="FADDEN" />
+ <BitField size="1" start="1" name="CONFG" />
+ <BitField size="1" start="2" name="ESR" />
+ <BitField size="1" start="3" name="RSMINPR" />
+ <BitField size="1" start="4" name="RMWUPE" />
+ </Register>
+ <Register size="4" start="0xFFFB0008" name="USB_FADDR" >
+ <BitField size="7" start="0" name="FADD" />
+ <BitField size="1" start="8" name="FEN" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFB0010" name="USB_IER" >
+ <BitField size="1" start="0" name="EP0INT" />
+ <BitField size="1" start="1" name="EP1INT" />
+ <BitField size="1" start="2" name="EP2INT" />
+ <BitField size="1" start="3" name="EP3INT" />
+ <BitField size="1" start="8" name="RXSUSP" />
+ <BitField size="1" start="9" name="RXRSM" />
+ <BitField size="1" start="10" name="EXTRSM" />
+ <BitField size="1" start="11" name="SOFINT" />
+ <BitField size="1" start="13" name="WAKEUP" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFB0014" name="USB_IDR" >
+ <BitField size="1" start="0" name="EP0INT" />
+ <BitField size="1" start="1" name="EP1INT" />
+ <BitField size="1" start="2" name="EP2INT" />
+ <BitField size="1" start="3" name="EP3INT" />
+ <BitField size="1" start="8" name="RXSUSP" />
+ <BitField size="1" start="9" name="RXRSM" />
+ <BitField size="1" start="10" name="EXTRSM" />
+ <BitField size="1" start="11" name="SOFINT" />
+ <BitField size="1" start="13" name="WAKEUP" />
+ </Register>
+ <Register size="4" start="0xFFFB0018" name="USB_IMR" >
+ <BitField size="1" start="0" name="EP0INT" />
+ <BitField size="1" start="1" name="EP1INT" />
+ <BitField size="1" start="2" name="EP2INT" />
+ <BitField size="1" start="3" name="EP3INT" />
+ <BitField size="1" start="8" name="RXSUSP" />
+ <BitField size="1" start="9" name="RXRSM" />
+ <BitField size="1" start="10" name="EXTRSM" />
+ <BitField size="1" start="11" name="SOFINT" />
+ <BitField size="1" start="13" name="WAKEUP" />
+ </Register>
+ <Register size="4" start="0xFFFB001C" name="USB_ISR" >
+ <BitField size="1" start="0" name="EP0INT" />
+ <BitField size="1" start="1" name="EP1INT" />
+ <BitField size="1" start="2" name="EP2INT" />
+ <BitField size="1" start="3" name="EP3INT" />
+ <BitField size="1" start="8" name="RXSUSP" />
+ <BitField size="1" start="9" name="RXRSM" />
+ <BitField size="1" start="10" name="EXTRSM" />
+ <BitField size="1" start="11" name="SOFINT" />
+ <BitField size="1" start="12" name="ENDBUSRES" />
+ <BitField size="1" start="13" name="WAKEUP" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFB0020" name="USB_ICR" >
+ <BitField size="1" start="8" name="RXSUSP" />
+ <BitField size="1" start="9" name="RXRSM" />
+ <BitField size="1" start="10" name="EXTRSM" />
+ <BitField size="1" start="11" name="SOFINT" />
+ <BitField size="1" start="12" name="ENDBUSRES" />
+ <BitField size="1" start="13" name="WAKEUP" />
+ </Register>
+ <Register size="4" start="0xFFFB0028" name="USB_RST_EP" >
+ <BitField size="1" start="0" name="EP0" />
+ <BitField size="1" start="1" name="EP1" />
+ <BitField size="1" start="2" name="EP2" />
+ <BitField size="1" start="3" name="EP3" />
+ </Register>
+ <Register size="4" start="0xFFFB0030" name="USB_CSR0" >
+ <BitField size="1" start="0" name="TXCOMP" />
+ <BitField size="1" start="1" name="RX_DATA_BK0" />
+ <BitField size="1" start="2" name="RXSETUP" />
+ <BitField size="1" start="3" name="STALLSENT_ISOERROR" />
+ <BitField size="1" start="4" name="TXPKTRDY" />
+ <BitField size="1" start="5" name="FORCE_STALL" />
+ <BitField size="1" start="6" name="RX_DATA_BK1" />
+ <BitField size="1" start="7" name="DIR" />
+ <BitField size="3" start="8" name="EPTYPE" />
+ <BitField size="1" start="11" name="DTGLE" />
+ <BitField size="1" start="15" name="EPEDS" />
+ <BitField size="11" start="16" name="RXBYTECNT" />
+ </Register>
+ <Register size="4" start="0xFFFB0034" name="USB_CSR1" >
+ <BitField size="1" start="0" name="TXCOMP" />
+ <BitField size="1" start="1" name="RX_DATA_BK0" />
+ <BitField size="1" start="2" name="RXSETUP" />
+ <BitField size="1" start="3" name="STALLSENT_ISOERROR" />
+ <BitField size="1" start="4" name="TXPKTRDY" />
+ <BitField size="1" start="5" name="FORCE_STALL" />
+ <BitField size="1" start="6" name="RX_DATA_BK1" />
+ <BitField size="1" start="7" name="DIR" />
+ <BitField size="3" start="8" name="EPTYPE" />
+ <BitField size="1" start="11" name="DTGLE" />
+ <BitField size="1" start="15" name="EPEDS" />
+ <BitField size="11" start="16" name="RXBYTECNT" />
+ </Register>
+ <Register size="4" start="0xFFFB0038" name="USB_CSR2" >
+ <BitField size="1" start="0" name="TXCOMP" />
+ <BitField size="1" start="1" name="RX_DATA_BK0" />
+ <BitField size="1" start="2" name="RXSETUP" />
+ <BitField size="1" start="3" name="STALLSENT_ISOERROR" />
+ <BitField size="1" start="4" name="TXPKTRDY" />
+ <BitField size="1" start="5" name="FORCE_STALL" />
+ <BitField size="1" start="6" name="RX_DATA_BK1" />
+ <BitField size="1" start="7" name="DIR" />
+ <BitField size="3" start="8" name="EPTYPE" />
+ <BitField size="1" start="11" name="DTGLE" />
+ <BitField size="1" start="15" name="EPEDS" />
+ <BitField size="11" start="16" name="RXBYTECNT" />
+ </Register>
+ <Register size="4" start="0xFFFB003C" name="USB_CSR3" >
+ <BitField size="1" start="0" name="TXCOMP" />
+ <BitField size="1" start="1" name="RX_DATA_BK0" />
+ <BitField size="1" start="2" name="RXSETUP" />
+ <BitField size="1" start="3" name="STALLSENT_ISOERROR" />
+ <BitField size="1" start="4" name="TXPKTRDY" />
+ <BitField size="1" start="5" name="FORCE_STALL" />
+ <BitField size="1" start="6" name="RX_DATA_BK1" />
+ <BitField size="1" start="7" name="DIR" />
+ <BitField size="3" start="8" name="EPTYPE" />
+ <BitField size="1" start="11" name="DTGLE" />
+ <BitField size="1" start="15" name="EPEDS" />
+ <BitField size="11" start="16" name="RXBYTECNT" />
+ </Register>
+ <Register size="4" start="0xFFFB0050" name="USB_FDR0" />
+ <Register size="4" start="0xFFFB0054" name="USB_FDR1" />
+ <Register size="4" start="0xFFFB0058" name="USB_FDR2" />
+ <Register size="4" start="0xFFFB005C" name="USB_FDR3" />
+ <Register size="4" start="0xFFFB0074" name="USB_TXVC" >
+ <BitField size="1" start="8" name="TXVDIS" />
+ </Register>
+ </RegisterGroup>
+ <RegisterGroup start="0xFFFB8000" name="TWI" >
+ <Register size="4" access="WriteOnly" start="0xFFFB8000" name="TWI_CR" >
+ <BitField size="1" start="0" name="START" />
+ <BitField size="1" start="1" name="STOP" />
+ <BitField size="1" start="2" name="MSEN" />
+ <BitField size="1" start="3" name="MSDIS" />
+ <BitField size="1" start="7" name="SWRST" />
+ </Register>
+ <Register size="4" start="0xFFFB8004" name="TWI_MMR" >
+ <BitField size="2" start="8" name="IADRSZ" />
+ <BitField size="12" start="12" name="MREAD" />
+ <BitField size="7" start="16" name="DADR" />
+ </Register>
+ <Register size="4" start="0xFFFB800C" name="TWI_IADR" />
+ <Register size="4" start="0xFFFB8010" name="TWI_CWGR" >
+ <BitField size="8" start="8" name="CHDIV" />
+ <BitField size="8" start="8" name="CLDIV" />
+ <BitField size="3" start="16" name="CKDIV" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFB8020" name="TWI_SR" >
+ <BitField size="1" start="0" name="TXCOMP" />
+ <BitField size="1" start="1" name="RXRDY" />
+ <BitField size="1" start="2" name="TXRDY" />
+ <BitField size="1" start="6" name="OVRE" />
+ <BitField size="1" start="7" name="UNRE" />
+ <BitField size="1" start="8" name="NACK" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFB8024" name="TWI_IER" >
+ <BitField size="1" start="0" name="TXCOMP" />
+ <BitField size="1" start="1" name="RXRDY" />
+ <BitField size="1" start="2" name="TXRDY" />
+ <BitField size="1" start="6" name="OVRE" />
+ <BitField size="1" start="7" name="UNRE" />
+ <BitField size="1" start="8" name="NACK" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFB8028" name="TWI_IDR" >
+ <BitField size="1" start="0" name="TXCOMP" />
+ <BitField size="1" start="1" name="RXRDY" />
+ <BitField size="1" start="2" name="TXRDY" />
+ <BitField size="1" start="6" name="OVRE" />
+ <BitField size="1" start="7" name="UNRE" />
+ <BitField size="1" start="8" name="NACK" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFB802C" name="TWI_IMR" >
+ <BitField size="1" start="0" name="TXCOMP" />
+ <BitField size="1" start="1" name="RXRDY" />
+ <BitField size="1" start="2" name="TXRDY" />
+ <BitField size="1" start="6" name="OVRE" />
+ <BitField size="1" start="7" name="UNRE" />
+ <BitField size="1" start="8" name="NACK" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFB8030" name="TWI_RHR" />
+ <Register size="4" start="0xFFFB8034" name="TWI_THR" />
+ </RegisterGroup>
+ <RegisterGroup start="0xFFFC0000" name="USART0" >
+ <Register size="4" access="WriteOnly" start="0xFFFC0000" name="US0_CR" >
+ <BitField size="1" start="2" name="RSTRX" />
+ <BitField size="1" start="3" name="RSTTX" />
+ <BitField size="1" start="4" name="RXEN" />
+ <BitField size="1" start="5" name="RXDIS" />
+ <BitField size="1" start="6" name="TXEN" />
+ <BitField size="1" start="7" name="TXDIS" />
+ <BitField size="1" start="8" name="RSTSTA" />
+ <BitField size="1" start="9" name="STTBRK" />
+ <BitField size="1" start="10" name="STPBRK" />
+ <BitField size="1" start="11" name="STTTO" />
+ <BitField size="1" start="12" name="SENDA" />
+ <BitField size="1" start="13" name="RSTIT" />
+ <BitField size="1" start="14" name="RSTNACK" />
+ <BitField size="1" start="15" name="RETTO" />
+ <BitField size="1" start="16" name="DTREN" />
+ <BitField size="1" start="17" name="DTRDIS" />
+ <BitField size="1" start="18" name="RTSEN" />
+ <BitField size="1" start="19" name="RTSDIS" />
+ </Register>
+ <Register size="4" start="0xFFFC0004" name="US0_MR" >
+ <BitField size="4" start="0" name="USART_MODE" />
+ <BitField size="2" start="4" name="USCLKS" />
+ <BitField size="2" start="6" name="CHRL" />
+ <BitField size="1" start="8" name="SYNC" />
+ <BitField size="3" start="9" name="PAR" />
+ <BitField size="2" start="12" name="NBSTOP" />
+ <BitField size="2" start="14" name="CHMODE" />
+ <BitField size="1" start="16" name="MSBF" />
+ <BitField size="1" start="17" name="MODE9" />
+ <BitField size="1" start="18" name="CLKO" />
+ <BitField size="1" start="19" name="OVER" />
+ <BitField size="1" start="20" name="INACK" />
+ <BitField size="1" start="21" name="DSNACK" />
+ <BitField size="3" start="24" name="MAX_ITERATION" />
+ <BitField size="1" start="28" name="FILTER" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFC0008" name="US0_IER" >
+ <BitField size="1" start="0" name="RXRDY" />
+ <BitField size="1" start="1" name="TXRDY" />
+ <BitField size="1" start="2" name="RXBRK" />
+ <BitField size="1" start="3" name="ENDRX" />
+ <BitField size="1" start="4" name="ENDTX" />
+ <BitField size="1" start="5" name="OVRE" />
+ <BitField size="1" start="6" name="FRAME" />
+ <BitField size="1" start="7" name="PARE" />
+ <BitField size="1" start="8" name="TIMEOUT" />
+ <BitField size="1" start="9" name="TXEMPTY" />
+ <BitField size="1" start="10" name="ITERATION" />
+ <BitField size="1" start="11" name="TXBUFE" />
+ <BitField size="1" start="12" name="RXBUFF" />
+ <BitField size="1" start="13" name="NACK" />
+ <BitField size="1" start="16" name="RIIC" />
+ <BitField size="1" start="17" name="DSRIC" />
+ <BitField size="1" start="18" name="DCDIC" />
+ <BitField size="1" start="19" name="CTSIC" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFC000C" name="US0_IDR" >
+ <BitField size="1" start="0" name="RXRDY" />
+ <BitField size="1" start="1" name="TXRDY" />
+ <BitField size="1" start="2" name="RXBRK" />
+ <BitField size="1" start="3" name="ENDRX" />
+ <BitField size="1" start="4" name="ENDTX" />
+ <BitField size="1" start="5" name="OVRE" />
+ <BitField size="1" start="6" name="FRAME" />
+ <BitField size="1" start="7" name="PARE" />
+ <BitField size="1" start="8" name="TIMEOUT" />
+ <BitField size="1" start="9" name="TXEMPTY" />
+ <BitField size="1" start="10" name="ITERATION" />
+ <BitField size="1" start="11" name="TXBUFE" />
+ <BitField size="1" start="12" name="RXBUFF" />
+ <BitField size="1" start="13" name="NACK" />
+ <BitField size="1" start="16" name="RIIC" />
+ <BitField size="1" start="17" name="DSRIC" />
+ <BitField size="1" start="18" name="DCDIC" />
+ <BitField size="1" start="19" name="CTSIC" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFC0010" name="US0_IMR" >
+ <BitField size="1" start="0" name="RXRDY" />
+ <BitField size="1" start="1" name="TXRDY" />
+ <BitField size="1" start="2" name="RXBRK" />
+ <BitField size="1" start="3" name="ENDRX" />
+ <BitField size="1" start="4" name="ENDTX" />
+ <BitField size="1" start="5" name="OVRE" />
+ <BitField size="1" start="6" name="FRAME" />
+ <BitField size="1" start="7" name="PARE" />
+ <BitField size="1" start="8" name="TIMEOUT" />
+ <BitField size="1" start="9" name="TXEMPTY" />
+ <BitField size="1" start="10" name="ITERATION" />
+ <BitField size="1" start="11" name="TXBUFE" />
+ <BitField size="1" start="12" name="RXBUFF" />
+ <BitField size="1" start="13" name="NACK" />
+ <BitField size="1" start="16" name="RIIC" />
+ <BitField size="1" start="17" name="DSRIC" />
+ <BitField size="1" start="18" name="DCDIC" />
+ <BitField size="1" start="19" name="CTSIC" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFC0014" name="US0_CSR" >
+ <BitField size="1" start="0" name="RXRDY" />
+ <BitField size="1" start="1" name="TXRDY" />
+ <BitField size="1" start="2" name="RXBRK" />
+ <BitField size="1" start="3" name="ENDRX" />
+ <BitField size="1" start="4" name="ENDTX" />
+ <BitField size="1" start="5" name="OVRE" />
+ <BitField size="1" start="6" name="FRAME" />
+ <BitField size="1" start="7" name="PARE" />
+ <BitField size="1" start="8" name="TIMEOUT" />
+ <BitField size="1" start="9" name="TXEMPTY" />
+ <BitField size="1" start="10" name="ITERATION" />
+ <BitField size="1" start="11" name="TXBUFE" />
+ <BitField size="1" start="12" name="RXBUFF" />
+ <BitField size="1" start="13" name="NACK" />
+ <BitField size="1" start="16" name="RIIC" />
+ <BitField size="1" start="17" name="DSRIC" />
+ <BitField size="1" start="18" name="DCDIC" />
+ <BitField size="1" start="19" name="CTSIC" />
+ <BitField size="1" start="20" name="RI" />
+ <BitField size="1" start="21" name="DSR" />
+ <BitField size="1" start="22" name="DCD" />
+ <BitField size="1" start="23" name="CTS" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFC0018" name="US0_RHR" />
+ <Register size="4" start="0xFFFC001C" name="US0_THR" />
+ <Register size="4" start="0xFFFC0020" name="US0_BRGR" />
+ <Register size="4" start="0xFFFC0024" name="US0_RTOR" />
+ <Register size="4" start="0xFFFC0028" name="US0_TTGR" />
+ <Register size="4" start="0xFFFC0040" name="US0_FIDI" />
+ <Register size="4" access="ReadOnly" start="0xFFFC0044" name="US0_NER" />
+ <Register size="4" start="0xFFFC004C" name="US0_IF" />
+ <Register size="4" start="0xFFFC0100" name="US0_RPR" />
+ <Register size="4" start="0xFFFC0104" name="US0_RCR" />
+ <Register size="4" start="0xFFFC0108" name="US0_TPR" />
+ <Register size="4" start="0xFFFC010C" name="US0_TCR" />
+ <Register size="4" start="0xFFFC0110" name="US0_RNPR" />
+ <Register size="4" start="0xFFFC0114" name="US0_RNCR" />
+ <Register size="4" start="0xFFFC0118" name="US0_TNPR" />
+ <Register size="4" start="0xFFFC011C" name="US0_TNCR" />
+ <Register size="4" access="WriteOnly" start="0xFFFC0120" name="US0_PTCR" >
+ <BitField size="1" start="0" name="RXTEN" />
+ <BitField size="1" start="1" name="RXTDIS" />
+ <BitField size="1" start="8" name="TXTEN" />
+ <BitField size="4" start="9" name="TXTDIS" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFC0124" name="US0_PTSR" >
+ <BitField size="1" start="0" name="RXTEN" />
+ <BitField size="4" start="9" name="TXTEN" />
+ </Register>
+ </RegisterGroup>
+ <RegisterGroup start="0xFFFC4000" name="USART1" >
+ <Register size="4" access="WriteOnly" start="0xFFFC4000" name="US1_CR" >
+ <BitField size="1" start="2" name="RSTRX" />
+ <BitField size="1" start="3" name="RSTTX" />
+ <BitField size="1" start="4" name="RXEN" />
+ <BitField size="1" start="5" name="RXDIS" />
+ <BitField size="1" start="6" name="TXEN" />
+ <BitField size="1" start="7" name="TXDIS" />
+ <BitField size="1" start="8" name="RSTSTA" />
+ <BitField size="1" start="9" name="STTBRK" />
+ <BitField size="1" start="10" name="STPBRK" />
+ <BitField size="1" start="11" name="STTTO" />
+ <BitField size="1" start="12" name="SENDA" />
+ <BitField size="1" start="13" name="RSTIT" />
+ <BitField size="1" start="14" name="RSTNACK" />
+ <BitField size="1" start="15" name="RETTO" />
+ <BitField size="1" start="16" name="DTREN" />
+ <BitField size="1" start="17" name="DTRDIS" />
+ <BitField size="1" start="18" name="RTSEN" />
+ <BitField size="1" start="19" name="RTSDIS" />
+ </Register>
+ <Register size="4" start="0xFFFC4004" name="US1_MR" >
+ <BitField size="4" start="0" name="USART_MODE" />
+ <BitField size="2" start="4" name="USCLKS" />
+ <BitField size="2" start="6" name="CHRL" />
+ <BitField size="1" start="8" name="SYNC" />
+ <BitField size="3" start="9" name="PAR" />
+ <BitField size="2" start="12" name="NBSTOP" />
+ <BitField size="2" start="14" name="CHMODE" />
+ <BitField size="1" start="16" name="MSBF" />
+ <BitField size="1" start="17" name="MODE9" />
+ <BitField size="1" start="18" name="CLKO" />
+ <BitField size="1" start="19" name="OVER" />
+ <BitField size="1" start="20" name="INACK" />
+ <BitField size="1" start="21" name="DSNACK" />
+ <BitField size="3" start="24" name="MAX_ITERATION" />
+ <BitField size="1" start="28" name="FILTER" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFC4008" name="US1_IER" >
+ <BitField size="1" start="0" name="RXRDY" />
+ <BitField size="1" start="1" name="TXRDY" />
+ <BitField size="1" start="2" name="RXBRK" />
+ <BitField size="1" start="3" name="ENDRX" />
+ <BitField size="1" start="4" name="ENDTX" />
+ <BitField size="1" start="5" name="OVRE" />
+ <BitField size="1" start="6" name="FRAME" />
+ <BitField size="1" start="7" name="PARE" />
+ <BitField size="1" start="8" name="TIMEOUT" />
+ <BitField size="1" start="9" name="TXEMPTY" />
+ <BitField size="1" start="10" name="ITERATION" />
+ <BitField size="1" start="11" name="TXBUFE" />
+ <BitField size="1" start="12" name="RXBUFF" />
+ <BitField size="1" start="13" name="NACK" />
+ <BitField size="1" start="16" name="RIIC" />
+ <BitField size="1" start="17" name="DSRIC" />
+ <BitField size="1" start="18" name="DCDIC" />
+ <BitField size="1" start="19" name="CTSIC" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFC400C" name="US1_IDR" >
+ <BitField size="1" start="0" name="RXRDY" />
+ <BitField size="1" start="1" name="TXRDY" />
+ <BitField size="1" start="2" name="RXBRK" />
+ <BitField size="1" start="3" name="ENDRX" />
+ <BitField size="1" start="4" name="ENDTX" />
+ <BitField size="1" start="5" name="OVRE" />
+ <BitField size="1" start="6" name="FRAME" />
+ <BitField size="1" start="7" name="PARE" />
+ <BitField size="1" start="8" name="TIMEOUT" />
+ <BitField size="1" start="9" name="TXEMPTY" />
+ <BitField size="1" start="10" name="ITERATION" />
+ <BitField size="1" start="11" name="TXBUFE" />
+ <BitField size="1" start="12" name="RXBUFF" />
+ <BitField size="1" start="13" name="NACK" />
+ <BitField size="1" start="16" name="RIIC" />
+ <BitField size="1" start="17" name="DSRIC" />
+ <BitField size="1" start="18" name="DCDIC" />
+ <BitField size="1" start="19" name="CTSIC" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFC4010" name="US1_IMR" >
+ <BitField size="1" start="0" name="RXRDY" />
+ <BitField size="1" start="1" name="TXRDY" />
+ <BitField size="1" start="2" name="RXBRK" />
+ <BitField size="1" start="3" name="ENDRX" />
+ <BitField size="1" start="4" name="ENDTX" />
+ <BitField size="1" start="5" name="OVRE" />
+ <BitField size="1" start="6" name="FRAME" />
+ <BitField size="1" start="7" name="PARE" />
+ <BitField size="1" start="8" name="TIMEOUT" />
+ <BitField size="1" start="9" name="TXEMPTY" />
+ <BitField size="1" start="10" name="ITERATION" />
+ <BitField size="1" start="11" name="TXBUFE" />
+ <BitField size="1" start="12" name="RXBUFF" />
+ <BitField size="1" start="13" name="NACK" />
+ <BitField size="1" start="16" name="RIIC" />
+ <BitField size="1" start="17" name="DSRIC" />
+ <BitField size="1" start="18" name="DCDIC" />
+ <BitField size="1" start="19" name="CTSIC" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFC4014" name="US1_CSR" >
+ <BitField size="1" start="0" name="RXRDY" />
+ <BitField size="1" start="1" name="TXRDY" />
+ <BitField size="1" start="2" name="RXBRK" />
+ <BitField size="1" start="3" name="ENDRX" />
+ <BitField size="1" start="4" name="ENDTX" />
+ <BitField size="1" start="5" name="OVRE" />
+ <BitField size="1" start="6" name="FRAME" />
+ <BitField size="1" start="7" name="PARE" />
+ <BitField size="1" start="8" name="TIMEOUT" />
+ <BitField size="1" start="9" name="TXEMPTY" />
+ <BitField size="1" start="10" name="ITERATION" />
+ <BitField size="1" start="11" name="TXBUFE" />
+ <BitField size="1" start="12" name="RXBUFF" />
+ <BitField size="1" start="13" name="NACK" />
+ <BitField size="1" start="16" name="RIIC" />
+ <BitField size="1" start="17" name="DSRIC" />
+ <BitField size="1" start="18" name="DCDIC" />
+ <BitField size="1" start="19" name="CTSIC" />
+ <BitField size="1" start="20" name="RI" />
+ <BitField size="1" start="21" name="DSR" />
+ <BitField size="1" start="22" name="DCD" />
+ <BitField size="1" start="23" name="CTS" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFC4018" name="US1_RHR" />
+ <Register size="4" access="WriteOnly" start="0xFFFC401C" name="US1_THR" />
+ <Register size="4" start="0xFFFC4020" name="US1_BRGR" />
+ <Register size="4" start="0xFFFC4024" name="US1_RTOR" />
+ <Register size="4" start="0xFFFC4028" name="US1_TTGR" />
+ <Register size="4" start="0xFFFC4040" name="US1_FIDI" />
+ <Register size="4" access="ReadOnly" start="0xFFFC4044" name="US1_NER" />
+ <Register size="4" start="0xFFFC404C" name="US1_IF" />
+ <Register size="4" start="0xFFFC4100" name="US1_RPR" />
+ <Register size="4" start="0xFFFC4104" name="US1_RCR" />
+ <Register size="4" start="0xFFFC4108" name="US1_TPR" />
+ <Register size="4" start="0xFFFC410C" name="US1_TCR" />
+ <Register size="4" start="0xFFFC4110" name="US1_RNPR" />
+ <Register size="4" start="0xFFFC4114" name="US1_RNCR" />
+ <Register size="4" start="0xFFFC4118" name="US1_TNPR" />
+ <Register size="4" start="0xFFFC411C" name="US1_TNCR" />
+ <Register size="4" access="WriteOnly" start="0xFFFC4120" name="US1_PTCR" >
+ <BitField size="1" start="0" name="RXTEN" />
+ <BitField size="1" start="1" name="RXTDIS" />
+ <BitField size="1" start="8" name="TXTEN" />
+ <BitField size="4" start="9" name="TXTDIS" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFC4124" name="US1_PTSR" >
+ <BitField size="1" start="0" name="RXTEN" />
+ <BitField size="4" start="9" name="TXTEN" />
+ </Register>
+ </RegisterGroup>
+ <RegisterGroup start="0xFFFCC000" name="PWM" >
+ <Register size="4" start="0xFFFCC000" name="PWM_MR" >
+ <BitField size="8" start="0" name="DIVA" />
+ <BitField size="4" start="8" name="PREA" />
+ <BitField size="8" start="16" name="DIVB" />
+ <BitField size="4" start="24" name="PREB" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFCC004" name="PWM_ENA" >
+ <BitField size="1" start="0" name="CHID0" />
+ <BitField size="1" start="1" name="CHID1" />
+ <BitField size="1" start="2" name="CHID2" />
+ <BitField size="1" start="3" name="CHID3" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFCC008" name="PWM_DIS" >
+ <BitField size="1" start="0" name="CHID0" />
+ <BitField size="1" start="1" name="CHID1" />
+ <BitField size="1" start="2" name="CHID2" />
+ <BitField size="1" start="3" name="CHID3" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFCC00C" name="PWM_SR" >
+ <BitField size="1" start="0" name="CHID0" />
+ <BitField size="1" start="1" name="CHID1" />
+ <BitField size="1" start="2" name="CHID2" />
+ <BitField size="1" start="3" name="CHID3" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFCC010" name="PWM_IER" >
+ <BitField size="1" start="0" name="CHID0" />
+ <BitField size="1" start="1" name="CHID1" />
+ <BitField size="1" start="2" name="CHID2" />
+ <BitField size="1" start="3" name="CHID3" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFCC014" name="PWM_IDR" >
+ <BitField size="1" start="0" name="CHID0" />
+ <BitField size="1" start="1" name="CHID1" />
+ <BitField size="1" start="2" name="CHID2" />
+ <BitField size="1" start="3" name="CHID3" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFCC018" name="PWM_IMR" >
+ <BitField size="1" start="0" name="CHID0" />
+ <BitField size="1" start="1" name="CHID1" />
+ <BitField size="1" start="2" name="CHID2" />
+ <BitField size="1" start="3" name="CHID3" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFCC01C" name="PWM_ISR" >
+ <BitField size="1" start="0" name="CHID0" />
+ <BitField size="1" start="1" name="CHID1" />
+ <BitField size="1" start="2" name="CHID2" />
+ <BitField size="1" start="3" name="CHID3" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFCC0FC" name="PWM_VERSION" >
+ <BitField size="12" start="0" name="VERSION" />
+ <BitField size="3" start="16" name="MFN" />
+ </Register>
+ <Register size="4" start="0xFFFCC200" name="PWM_CMR0" >
+ <BitField size="4" start="0" name="CPRE" />
+ <BitField size="1" start="8" name="CALG" />
+ <BitField size="1" start="9" name="CPOL" />
+ <BitField size="1" start="10" name="CPD" />
+ </Register>
+ <Register size="4" start="0xFFFCC204" name="PWM_CDTY0" />
+ <Register size="4" start="0xFFFCC208" name="PWM_CPRD0" />
+ <Register size="4" access="ReadOnly" start="0xFFFCC20C" name="PWM_CCNT0" />
+ <Register size="4" access="WriteOnly" start="0xFFFCC210" name="PWM_CUPD0" />
+ <Register size="4" start="0xFFFCC220" name="PWM_CMR1" />
+ <Register size="4" start="0xFFFCC224" name="PWM_CDTY1" />
+ <Register size="4" start="0xFFFCC228" name="PWM_CPRD1" />
+ <Register size="4" access="ReadOnly" start="0xFFFCC22C" name="PWM_CCNT1" />
+ <Register size="4" access="WriteOnly" start="0xFFFCC230" name="PWM_CUPD1" />
+ </RegisterGroup>
+ <RegisterGroup start="0xFFFD4000" name="SSC" >
+ <Register size="4" access="WriteOnly" start="0xFFFD4000" name="SSC_CR" >
+ <BitField size="1" start="0" name="RXEN" />
+ <BitField size="1" start="1" name="RXDIS" />
+ <BitField size="1" start="8" name="TXEN" />
+ <BitField size="1" start="9" name="TXDIS" />
+ <BitField size="1" start="15" name="SWRST" />
+ </Register>
+ <Register size="4" start="0xFFFD4004" name="SSC_CMR" />
+ <Register size="4" start="0xFFFD4010" name="SSC_RCMR" >
+ <BitField size="2" start="0" name="CKS" />
+ <BitField size="3" start="2" name="CKO" />
+ <BitField size="1" start="5" name="CKI" />
+ <BitField size="4" start="8" name="START" />
+ <BitField size="8" start="16" name="STTDLY" />
+ <BitField size="8" start="24" name="PERIOD" />
+ </Register>
+ <Register size="4" start="0xFFFD4014" name="SSC_RFMR" >
+ <BitField size="5" start="0" name="DATLEN" />
+ <BitField size="1" start="5" name="LOOP" />
+ <BitField size="1" start="7" name="MSBF" />
+ <BitField size="4" start="8" name="DATNB" />
+ <BitField size="4" start="16" name="FSLEN" />
+ <BitField size="4" start="20" name="FSOS" />
+ <BitField size="1" start="24" name="FSEDGE" />
+ </Register>
+ <Register size="4" start="0xFFFD4018" name="SSC_TCMR" >
+ <BitField size="2" start="0" name="CKS" />
+ <BitField size="3" start="2" name="CKO" />
+ <BitField size="1" start="5" name="CKI" />
+ <BitField size="4" start="8" name="START" />
+ <BitField size="8" start="16" name="STTDLY" />
+ <BitField size="8" start="24" name="PERIOD" />
+ </Register>
+ <Register size="4" start="0xFFFD401C" name="SSC_TFMR" >
+ <BitField size="5" start="0" name="DATLEN" />
+ <BitField size="1" start="5" name="DATDEF" />
+ <BitField size="1" start="7" name="MSBF" />
+ <BitField size="4" start="8" name="DATNB" />
+ <BitField size="4" start="16" name="FSLEN" />
+ <BitField size="3" start="20" name="FSOS" />
+ <BitField size="1" start="24" name="FSDEN" />
+ <BitField size="1" start="24" name="FSEDGE" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFD4020" name="SSC_RHR" />
+ <Register size="4" access="WriteOnly" start="0xFFFD4024" name="SSC_THR" />
+ <Register size="4" access="ReadOnly" start="0xFFFD4030" name="SSC_RSHR" />
+ <Register size="4" start="0xFFFD4034" name="SSC_TSHR" />
+ <Register size="4" access="ReadOnly" start="0xFFFD4040" name="SSC_SR" >
+ <BitField size="1" start="0" name="TXRDY" />
+ <BitField size="1" start="1" name="TXEMPTY" />
+ <BitField size="1" start="2" name="ENDTX" />
+ <BitField size="1" start="3" name="TXBUFE" />
+ <BitField size="1" start="4" name="RXRDY" />
+ <BitField size="1" start="5" name="OVRUN" />
+ <BitField size="1" start="6" name="ENDRX" />
+ <BitField size="1" start="7" name="RXBUFF" />
+ <BitField size="1" start="10" name="TXSYN" />
+ <BitField size="1" start="11" name="RXSYN" />
+ <BitField size="1" start="16" name="TXEN" />
+ <BitField size="1" start="17" name="RXEN" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFD4044" name="SSC_IER" >
+ <BitField size="1" start="0" name="TXRDY" />
+ <BitField size="1" start="1" name="TXEMPTY" />
+ <BitField size="1" start="2" name="ENDTX" />
+ <BitField size="1" start="3" name="TXBUFE" />
+ <BitField size="1" start="4" name="RXRDY" />
+ <BitField size="1" start="5" name="OVRUN" />
+ <BitField size="1" start="6" name="ENDRX" />
+ <BitField size="1" start="7" name="RXBUFF" />
+ <BitField size="1" start="10" name="TXSYN" />
+ <BitField size="1" start="11" name="RXSYN" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFD4048" name="SSC_IDR" >
+ <BitField size="1" start="0" name="TXRDY" />
+ <BitField size="1" start="1" name="TXEMPTY" />
+ <BitField size="1" start="2" name="ENDTX" />
+ <BitField size="1" start="3" name="TXBUFE" />
+ <BitField size="1" start="4" name="RXRDY" />
+ <BitField size="1" start="5" name="OVRUN" />
+ <BitField size="1" start="6" name="ENDRX" />
+ <BitField size="1" start="7" name="RXBUFF" />
+ <BitField size="1" start="10" name="TXSYN" />
+ <BitField size="1" start="11" name="RXSYN" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFD404C" name="SSC_IMR" >
+ <BitField size="1" start="0" name="TXRDY" />
+ <BitField size="1" start="1" name="TXEMPTY" />
+ <BitField size="1" start="2" name="ENDTX" />
+ <BitField size="1" start="3" name="TXBUFE" />
+ <BitField size="1" start="4" name="RXRDY" />
+ <BitField size="1" start="5" name="OVRUN" />
+ <BitField size="1" start="6" name="ENDRX" />
+ <BitField size="1" start="7" name="RXBUFF" />
+ <BitField size="1" start="10" name="TXSYN" />
+ <BitField size="1" start="11" name="RXSYN" />
+ </Register>
+ <Register size="4" start="0xFFFD4100" name="SSC_RPR" />
+ <Register size="4" start="0xFFFD4104" name="SSC_RCR" />
+ <Register size="4" start="0xFFFD4108" name="SSC_TPR" />
+ <Register size="4" start="0xFFFD410C" name="SSC_TCR" />
+ <Register size="4" start="0xFFFD4110" name="SSC_RNPR" />
+ <Register size="4" start="0xFFFD4114" name="SSC_RNCR" />
+ <Register size="4" start="0xFFFD4118" name="SSC_TNPR" />
+ <Register size="4" start="0xFFFD411C" name="SSC_TNCR" />
+ <Register size="4" access="WriteOnly" start="0xFFFD4120" name="SSC_PTCR" >
+ <BitField size="1" start="0" name="RXTEN" />
+ <BitField size="1" start="1" name="RXTDIS" />
+ <BitField size="1" start="8" name="TXTEN" />
+ <BitField size="4" start="9" name="TXTDIS" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFD4124" name="SSC_PTSR" >
+ <BitField size="1" start="0" name="RXTEN" />
+ <BitField size="4" start="9" name="TXTEN" />
+ </Register>
+ </RegisterGroup>
+ <RegisterGroup start="0xFFFD8000" name="ADC" >
+ <Register size="4" access="WriteOnly" start="0xFFFD8000" name="ADC_CR" >
+ <BitField size="1" start="0" name="SWRST" />
+ <BitField size="1" start="1" name="START" />
+ </Register>
+ <Register size="4" start="0xFFFD8004" name="ADC_MR" >
+ <BitField size="1" start="0" name="TRGEN" />
+ <BitField size="3" start="1" name="TRGSEL" />
+ <BitField size="1" start="4" name="LOWRES" />
+ <BitField size="1" start="5" name="SLEEP" />
+ <BitField size="6" start="8" name="PRESCAL" />
+ <BitField size="5" start="16" name="STARTUP" />
+ <BitField size="4" start="24" name="SHTIM" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFD8010" name="ADC_CHER" >
+ <BitField size="1" start="0" name="CH0" />
+ <BitField size="1" start="1" name="CH1" />
+ <BitField size="1" start="2" name="CH2" />
+ <BitField size="1" start="3" name="CH3" />
+ <BitField size="1" start="4" name="CH4" />
+ <BitField size="1" start="5" name="CH5" />
+ <BitField size="1" start="6" name="CH6" />
+ <BitField size="1" start="7" name="CH7" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFD8014" name="ADC_CHDR" >
+ <BitField size="1" start="0" name="CH0" />
+ <BitField size="1" start="1" name="CH1" />
+ <BitField size="1" start="2" name="CH2" />
+ <BitField size="1" start="3" name="CH3" />
+ <BitField size="1" start="4" name="CH4" />
+ <BitField size="1" start="5" name="CH5" />
+ <BitField size="1" start="6" name="CH6" />
+ <BitField size="1" start="7" name="CH7" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFD8018" name="ADC_CHSR" >
+ <BitField size="1" start="0" name="CH0" />
+ <BitField size="1" start="1" name="CH1" />
+ <BitField size="1" start="2" name="CH2" />
+ <BitField size="1" start="3" name="CH3" />
+ <BitField size="1" start="4" name="CH4" />
+ <BitField size="1" start="5" name="CH5" />
+ <BitField size="1" start="6" name="CH6" />
+ <BitField size="1" start="7" name="CH7" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFD801C" name="ADC_SR" >
+ <BitField size="1" start="0" name="EOC0" />
+ <BitField size="1" start="1" name="EOC1" />
+ <BitField size="1" start="2" name="EOC2" />
+ <BitField size="1" start="3" name="EOC3" />
+ <BitField size="1" start="4" name="EOC4" />
+ <BitField size="1" start="5" name="EOC5" />
+ <BitField size="1" start="6" name="EOC6" />
+ <BitField size="1" start="7" name="EOC7" />
+ <BitField size="1" start="8" name="OVRE0" />
+ <BitField size="1" start="9" name="OVRE1" />
+ <BitField size="1" start="10" name="OVRE2" />
+ <BitField size="1" start="11" name="OVRE3" />
+ <BitField size="1" start="12" name="OVRE4" />
+ <BitField size="1" start="13" name="OVRE5" />
+ <BitField size="1" start="14" name="OVRE6" />
+ <BitField size="1" start="15" name="OVRE7" />
+ <BitField size="1" start="16" name="DRDY" />
+ <BitField size="1" start="17" name="GOVRE" />
+ <BitField size="1" start="18" name="ENDRX" />
+ <BitField size="1" start="19" name="RXBUFF" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFD8020" name="ADC_LCDR" />
+ <Register size="4" access="WriteOnly" start="0xFFFD8024" name="ADC_IER" >
+ <BitField size="1" start="0" name="EOC0" />
+ <BitField size="1" start="1" name="EOC1" />
+ <BitField size="1" start="2" name="EOC2" />
+ <BitField size="1" start="3" name="EOC3" />
+ <BitField size="1" start="4" name="EOC4" />
+ <BitField size="1" start="5" name="EOC5" />
+ <BitField size="1" start="6" name="EOC6" />
+ <BitField size="1" start="7" name="EOC7" />
+ <BitField size="1" start="8" name="OVRE0" />
+ <BitField size="1" start="9" name="OVRE1" />
+ <BitField size="1" start="10" name="OVRE2" />
+ <BitField size="1" start="11" name="OVRE3" />
+ <BitField size="1" start="12" name="OVRE4" />
+ <BitField size="1" start="13" name="OVRE5" />
+ <BitField size="1" start="14" name="OVRE6" />
+ <BitField size="1" start="15" name="OVRE7" />
+ <BitField size="1" start="16" name="DRDY" />
+ <BitField size="1" start="17" name="GOVRE" />
+ <BitField size="1" start="18" name="ENDRX" />
+ <BitField size="1" start="19" name="RXBUFF" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFD8028" name="ADC_IDR" >
+ <BitField size="1" start="0" name="EOC0" />
+ <BitField size="1" start="1" name="EOC1" />
+ <BitField size="1" start="2" name="EOC2" />
+ <BitField size="1" start="3" name="EOC3" />
+ <BitField size="1" start="4" name="EOC4" />
+ <BitField size="1" start="5" name="EOC5" />
+ <BitField size="1" start="6" name="EOC6" />
+ <BitField size="1" start="7" name="EOC7" />
+ <BitField size="1" start="8" name="OVRE0" />
+ <BitField size="1" start="9" name="OVRE1" />
+ <BitField size="1" start="10" name="OVRE2" />
+ <BitField size="1" start="11" name="OVRE3" />
+ <BitField size="1" start="12" name="OVRE4" />
+ <BitField size="1" start="13" name="OVRE5" />
+ <BitField size="1" start="14" name="OVRE6" />
+ <BitField size="1" start="15" name="OVRE7" />
+ <BitField size="1" start="16" name="DRDY" />
+ <BitField size="1" start="17" name="GOVRE" />
+ <BitField size="1" start="18" name="ENDRX" />
+ <BitField size="1" start="19" name="RXBUFF" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFD802C" name="ADC_IMR" />
+ <Register size="4" access="ReadOnly" start="0xFFFD8030" name="ADC_CDR0" />
+ <Register size="4" access="ReadOnly" start="0xFFFD8034" name="ADC_CDR1" />
+ <Register size="4" access="ReadOnly" start="0xFFFD8038" name="ADC_CDR2" />
+ <Register size="4" access="ReadOnly" start="0xFFFD803C" name="ADC_CDR3" />
+ <Register size="4" access="ReadOnly" start="0xFFFD8040" name="ADC_CDR4" />
+ <Register size="4" access="ReadOnly" start="0xFFFD8044" name="ADC_CDR5" />
+ <Register size="4" access="ReadOnly" start="0xFFFD8048" name="ADC_CDR6" />
+ <Register size="4" access="ReadOnly" start="0xFFFD804C" name="ADC_CDR7" />
+ <Register size="4" start="0xFFFD8100" name="ADC_RPR" />
+ <Register size="4" start="0xFFFD8104" name="ADC_RCR" />
+ <Register size="4" start="0xFFFD8108" name="ADC_TPR" />
+ <Register size="4" start="0xFFFD810C" name="ADC_TCR" />
+ <Register size="4" start="0xFFFD8110" name="ADC_RNPR" />
+ <Register size="4" start="0xFFFD8114" name="ADC_RNCR" />
+ <Register size="4" start="0xFFFD8118" name="ADC_TNPR" />
+ <Register size="4" start="0xFFFD811C" name="ADC_TNCR" />
+ <Register size="4" access="WriteOnly" start="0xFFFD8120" name="ADC_PTCR" >
+ <BitField size="1" start="0" name="RXTEN" />
+ <BitField size="1" start="1" name="RXTDIS" />
+ <BitField size="1" start="8" name="TXTEN" />
+ <BitField size="4" start="9" name="TXTDIS" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFD8124" name="ADC_PTSR" >
+ <BitField size="1" start="0" name="RXTEN" />
+ <BitField size="4" start="9" name="TXTEN" />
+ </Register>
+ </RegisterGroup>
+ <RegisterGroup start="0xFFFE0000" name="SPI" >
+ <Register size="4" access="WriteOnly" start="0xFFFE0000" name="SPI_CR" >
+ <BitField size="1" start="0" name="SPIEN" />
+ <BitField size="1" start="1" name="SPIDIS" />
+ <BitField size="1" start="7" name="SWRST" />
+ <BitField size="1" start="24" name="LASTXFER" />
+ </Register>
+ <Register size="4" start="0xFFFE0004" name="SPI_MR" >
+ <BitField size="1" start="0" name="MSTR" />
+ <BitField size="1" start="1" name="PS" />
+ <BitField size="1" start="2" name="PCSDEC" />
+ <BitField size="1" start="3" name="FDIV" />
+ <BitField size="1" start="4" name="MODFDIS" />
+ <BitField size="1" start="7" name="LLB" />
+ <BitField size="4" start="16" name="PCS" />
+ <BitField size="8" start="24" name="DLYBCS" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFE0008" name="SPI_RDR" >
+ <BitField size="16" start="0" name="RD" />
+ <BitField size="4" start="16" name="PCS" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFE000C" name="SPI_TDR" >
+ <BitField size="16" start="0" name="TD" />
+ <BitField size="4" start="16" name="PCS" />
+ <BitField size="1" start="24" name="LASTXFER" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFE0010" name="SPI_SR" >
+ <BitField size="1" start="0" name="RDRF" />
+ <BitField size="1" start="1" name="TDRE" />
+ <BitField size="1" start="2" name="MODF" />
+ <BitField size="1" start="3" name="OVRES" />
+ <BitField size="1" start="4" name="ENDRX" />
+ <BitField size="1" start="5" name="ENDTX" />
+ <BitField size="1" start="6" name="RXBUFF" />
+ <BitField size="1" start="7" name="TXBUFE" />
+ <BitField size="1" start="8" name="NSSR" />
+ <BitField size="1" start="9" name="TXEMPTY" />
+ <BitField size="1" start="16" name="SPIENS" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFE0014" name="SPI_IER" >
+ <BitField size="1" start="0" name="RDRF" />
+ <BitField size="1" start="1" name="TDRE" />
+ <BitField size="1" start="2" name="MODF" />
+ <BitField size="1" start="3" name="OVRES" />
+ <BitField size="1" start="4" name="ENDRX" />
+ <BitField size="1" start="5" name="ENDTX" />
+ <BitField size="1" start="6" name="RXBUFF" />
+ <BitField size="1" start="7" name="TXBUFE" />
+ <BitField size="1" start="8" name="NSSR" />
+ <BitField size="1" start="9" name="TXEMPTY" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFE0018" name="SPI_IDR" >
+ <BitField size="1" start="0" name="RDRF" />
+ <BitField size="1" start="1" name="TDRE" />
+ <BitField size="1" start="2" name="MODF" />
+ <BitField size="1" start="3" name="OVRES" />
+ <BitField size="1" start="4" name="ENDRX" />
+ <BitField size="1" start="5" name="ENDTX" />
+ <BitField size="1" start="6" name="RXBUFF" />
+ <BitField size="1" start="7" name="TXBUFE" />
+ <BitField size="1" start="8" name="NSSR" />
+ <BitField size="1" start="9" name="TXEMPTY" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFE001C" name="SPI_IMR" >
+ <BitField size="1" start="0" name="RDRF" />
+ <BitField size="1" start="1" name="TDRE" />
+ <BitField size="1" start="2" name="MODF" />
+ <BitField size="1" start="3" name="OVRES" />
+ <BitField size="1" start="4" name="ENDRX" />
+ <BitField size="1" start="5" name="ENDTX" />
+ <BitField size="1" start="6" name="RXBUFF" />
+ <BitField size="1" start="7" name="TXBUFE" />
+ <BitField size="1" start="8" name="NSSR" />
+ <BitField size="1" start="9" name="TXEMPTY" />
+ </Register>
+ <Register size="4" start="0xFFFE0030" name="SPI_CSR0" >
+ <BitField size="1" start="0" name="CPOL" />
+ <BitField size="1" start="1" name="NCPHA" />
+ <BitField size="1" start="3" name="CSAAT" />
+ <BitField size="4" start="4" name="BITS" />
+ <BitField size="8" start="8" name="SCBR" />
+ <BitField size="8" start="16" name="DLYBS" />
+ <BitField size="8" start="24" name="DLYBCT" />
+ </Register>
+ <Register size="4" start="0xFFFE0034" name="SPI_CSR1" >
+ <BitField size="1" start="0" name="CPOL" />
+ <BitField size="1" start="1" name="NCPHA" />
+ <BitField size="1" start="3" name="CSAAT" />
+ <BitField size="4" start="4" name="BITS" />
+ <BitField size="8" start="8" name="SCBR" />
+ <BitField size="8" start="16" name="DLYBS" />
+ <BitField size="8" start="24" name="DLYBCT" />
+ </Register>
+ <Register size="4" start="0xFFFE0038" name="SPI_CSR2" >
+ <BitField size="1" start="0" name="CPOL" />
+ <BitField size="1" start="1" name="NCPHA" />
+ <BitField size="1" start="3" name="CSAAT" />
+ <BitField size="4" start="4" name="BITS" />
+ <BitField size="8" start="8" name="SCBR" />
+ <BitField size="8" start="16" name="DLYBS" />
+ <BitField size="8" start="24" name="DLYBCT" />
+ </Register>
+ <Register size="4" start="0xFFFE003C" name="SPI_CSR3" >
+ <BitField size="1" start="0" name="CPOL" />
+ <BitField size="1" start="1" name="NCPHA" />
+ <BitField size="1" start="3" name="CSAAT" />
+ <BitField size="4" start="4" name="BITS" />
+ <BitField size="8" start="8" name="SCBR" />
+ <BitField size="8" start="16" name="DLYBS" />
+ <BitField size="8" start="24" name="DLYBCT" />
+ </Register>
+ <Register size="4" start="0xFFFE0100" name="SPI_RPR" />
+ <Register size="4" start="0xFFFE0104" name="SPI_RCR" />
+ <Register size="4" start="0xFFFE0108" name="SPI_TPR" />
+ <Register size="4" start="0xFFFE010C" name="SPI_TCR" />
+ <Register size="4" start="0xFFFE0110" name="SPI_RNPR" />
+ <Register size="4" start="0xFFFE0114" name="SPI_RNCR" />
+ <Register size="4" start="0xFFFE0118" name="SPI_TNPR" />
+ <Register size="4" start="0xFFFE011C" name="SPI_TNCR" />
+ <Register size="4" access="WriteOnly" start="0xFFFE0120" name="SPI_PTCR" >
+ <BitField size="1" start="0" name="RXTEN" />
+ <BitField size="1" start="1" name="RXTDIS" />
+ <BitField size="1" start="8" name="TXTEN" />
+ <BitField size="4" start="9" name="TXTDIS" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFE0124" name="SPI_PTSR" >
+ <BitField size="1" start="0" name="RXTEN" />
+ <BitField size="4" start="9" name="TXTEN" />
+ </Register>
+ </RegisterGroup>
+ </MemorySegment>
+ <MemorySegment start="0xFFFFF000" name="System Controller" >
+ <RegisterGroup start="0xFFFFF000" name="AIC" >
+ <Register size="4" start="0xFFFFF000" name="AIC_SMR0" >
+ <BitField size="3" start="0" name="PRIOR" />
+ <BitField size="2" start="5" name="SRCTYPE" />
+ </Register>
+ <Register size="4" start="0xFFFFF004" name="AIC_SMR1" >
+ <BitField size="3" start="0" name="PRIOR" />
+ <BitField size="2" start="5" name="SRCTYPE" />
+ </Register>
+ <Register size="4" start="0xFFFFF008" name="AIC_SMR2" >
+ <BitField size="3" start="0" name="PRIOR" />
+ <BitField size="2" start="5" name="SRCTYPE" />
+ </Register>
+ <Register size="4" start="0xFFFFF00C" name="AIC_SMR3" >
+ <BitField size="3" start="0" name="PRIOR" />
+ <BitField size="2" start="5" name="SRCTYPE" />
+ </Register>
+ <Register size="4" start="0xFFFFF010" name="AIC_SMR4" >
+ <BitField size="3" start="0" name="PRIOR" />
+ <BitField size="2" start="5" name="SRCTYPE" />
+ </Register>
+ <Register size="4" start="0xFFFFF014" name="AIC_SMR5" >
+ <BitField size="3" start="0" name="PRIOR" />
+ <BitField size="2" start="5" name="SRCTYPE" />
+ </Register>
+ <Register size="4" start="0xFFFFF018" name="AIC_SMR6" >
+ <BitField size="3" start="0" name="PRIOR" />
+ <BitField size="2" start="5" name="SRCTYPE" />
+ </Register>
+ <Register size="4" start="0xFFFFF01C" name="AIC_SMR7" >
+ <BitField size="3" start="0" name="PRIOR" />
+ <BitField size="2" start="5" name="SRCTYPE" />
+ </Register>
+ <Register size="4" start="0xFFFFF020" name="AIC_SMR8" >
+ <BitField size="3" start="0" name="PRIOR" />
+ <BitField size="2" start="5" name="SRCTYPE" />
+ </Register>
+ <Register size="4" start="0xFFFFF024" name="AIC_SMR9" >
+ <BitField size="3" start="0" name="PRIOR" />
+ <BitField size="2" start="5" name="SRCTYPE" />
+ </Register>
+ <Register size="4" start="0xFFFFF028" name="AIC_SMR10" >
+ <BitField size="3" start="0" name="PRIOR" />
+ <BitField size="2" start="5" name="SRCTYPE" />
+ </Register>
+ <Register size="4" start="0xFFFFF02C" name="AIC_SMR11" >
+ <BitField size="3" start="0" name="PRIOR" />
+ <BitField size="2" start="5" name="SRCTYPE" />
+ </Register>
+ <Register size="4" start="0xFFFFF030" name="AIC_SMR12" >
+ <BitField size="3" start="0" name="PRIOR" />
+ <BitField size="2" start="5" name="SRCTYPE" />
+ </Register>
+ <Register size="4" start="0xFFFFF034" name="AIC_SMR13" >
+ <BitField size="3" start="0" name="PRIOR" />
+ <BitField size="2" start="5" name="SRCTYPE" />
+ </Register>
+ <Register size="4" start="0xFFFFF038" name="AIC_SMR14" >
+ <BitField size="3" start="0" name="PRIOR" />
+ <BitField size="2" start="5" name="SRCTYPE" />
+ </Register>
+ <Register size="4" start="0xFFFFF03C" name="AIC_SMR15" >
+ <BitField size="3" start="0" name="PRIOR" />
+ <BitField size="2" start="5" name="SRCTYPE" />
+ </Register>
+ <Register size="4" start="0xFFFFF040" name="AIC_SMR16" >
+ <BitField size="3" start="0" name="PRIOR" />
+ <BitField size="2" start="5" name="SRCTYPE" />
+ </Register>
+ <Register size="4" start="0xFFFFF044" name="AIC_SMR17" >
+ <BitField size="3" start="0" name="PRIOR" />
+ <BitField size="2" start="5" name="SRCTYPE" />
+ </Register>
+ <Register size="4" start="0xFFFFF048" name="AIC_SMR18" >
+ <BitField size="3" start="0" name="PRIOR" />
+ <BitField size="2" start="5" name="SRCTYPE" />
+ </Register>
+ <Register size="4" start="0xFFFFF04C" name="AIC_SMR19" >
+ <BitField size="3" start="0" name="PRIOR" />
+ <BitField size="2" start="5" name="SRCTYPE" />
+ </Register>
+ <Register size="4" start="0xFFFFF050" name="AIC_SMR20" >
+ <BitField size="3" start="0" name="PRIOR" />
+ <BitField size="2" start="5" name="SRCTYPE" />
+ </Register>
+ <Register size="4" start="0xFFFFF054" name="AIC_SMR21" >
+ <BitField size="3" start="0" name="PRIOR" />
+ <BitField size="2" start="5" name="SRCTYPE" />
+ </Register>
+ <Register size="4" start="0xFFFFF058" name="AIC_SMR22" >
+ <BitField size="3" start="0" name="PRIOR" />
+ <BitField size="2" start="5" name="SRCTYPE" />
+ </Register>
+ <Register size="4" start="0xFFFFF05C" name="AIC_SMR23" >
+ <BitField size="3" start="0" name="PRIOR" />
+ <BitField size="2" start="5" name="SRCTYPE" />
+ </Register>
+ <Register size="4" start="0xFFFFF060" name="AIC_SMR24" >
+ <BitField size="3" start="0" name="PRIOR" />
+ <BitField size="2" start="5" name="SRCTYPE" />
+ </Register>
+ <Register size="4" start="0xFFFFF064" name="AIC_SMR25" >
+ <BitField size="3" start="0" name="PRIOR" />
+ <BitField size="2" start="5" name="SRCTYPE" />
+ </Register>
+ <Register size="4" start="0xFFFFF068" name="AIC_SMR26" >
+ <BitField size="3" start="0" name="PRIOR" />
+ <BitField size="2" start="5" name="SRCTYPE" />
+ </Register>
+ <Register size="4" start="0xFFFFF06C" name="AIC_SMR27" >
+ <BitField size="3" start="0" name="PRIOR" />
+ <BitField size="2" start="5" name="SRCTYPE" />
+ </Register>
+ <Register size="4" start="0xFFFFF070" name="AIC_SMR28" >
+ <BitField size="3" start="0" name="PRIOR" />
+ <BitField size="2" start="5" name="SRCTYPE" />
+ </Register>
+ <Register size="4" start="0xFFFFF074" name="AIC_SMR29" >
+ <BitField size="3" start="0" name="PRIOR" />
+ <BitField size="2" start="5" name="SRCTYPE" />
+ </Register>
+ <Register size="4" start="0xFFFFF078" name="AIC_SMR30" >
+ <BitField size="3" start="0" name="PRIOR" />
+ <BitField size="2" start="5" name="SRCTYPE" />
+ </Register>
+ <Register size="4" start="0xFFFFF07C" name="AIC_SMR31" >
+ <BitField size="3" start="0" name="PRIOR" />
+ <BitField size="2" start="5" name="SRCTYPE" />
+ </Register>
+ <Register size="4" start="0xFFFFF080" name="AIC_SVR0" />
+ <Register size="4" start="0xFFFFF084" name="AIC_SVR1" />
+ <Register size="4" start="0xFFFFF088" name="AIC_SVR2" />
+ <Register size="4" start="0xFFFFF08C" name="AIC_SVR3" />
+ <Register size="4" start="0xFFFFF090" name="AIC_SVR4" />
+ <Register size="4" start="0xFFFFF094" name="AIC_SVR5" />
+ <Register size="4" start="0xFFFFF098" name="AIC_SVR6" />
+ <Register size="4" start="0xFFFFF09C" name="AIC_SVR7" />
+ <Register size="4" start="0xFFFFF0A0" name="AIC_SVR8" />
+ <Register size="4" start="0xFFFFF0A4" name="AIC_SVR9" />
+ <Register size="4" start="0xFFFFF0A8" name="AIC_SVR10" />
+ <Register size="4" start="0xFFFFF0AC" name="AIC_SVR11" />
+ <Register size="4" start="0xFFFFF0B0" name="AIC_SVR12" />
+ <Register size="4" start="0xFFFFF0B4" name="AIC_SVR13" />
+ <Register size="4" start="0xFFFFF0B8" name="AIC_SVR14" />
+ <Register size="4" start="0xFFFFF0BC" name="AIC_SVR15" />
+ <Register size="4" start="0xFFFFF0C0" name="AIC_SVR16" />
+ <Register size="4" start="0xFFFFF0C4" name="AIC_SVR17" />
+ <Register size="4" start="0xFFFFF0C8" name="AIC_SVR18" />
+ <Register size="4" start="0xFFFFF0CC" name="AIC_SVR19" />
+ <Register size="4" start="0xFFFFF0D0" name="AIC_SVR20" />
+ <Register size="4" start="0xFFFFF0D4" name="AIC_SVR21" />
+ <Register size="4" start="0xFFFFF0D8" name="AIC_SVR22" />
+ <Register size="4" start="0xFFFFF0DC" name="AIC_SVR23" />
+ <Register size="4" start="0xFFFFF0E0" name="AIC_SVR24" />
+ <Register size="4" start="0xFFFFF0E4" name="AIC_SVR25" />
+ <Register size="4" start="0xFFFFF0E8" name="AIC_SVR26" />
+ <Register size="4" start="0xFFFFF0EC" name="AIC_SVR27" />
+ <Register size="4" start="0xFFFFF0F0" name="AIC_SVR28" />
+ <Register size="4" start="0xFFFFF0F4" name="AIC_SVR29" />
+ <Register size="4" start="0xFFFFF0F8" name="AIC_SVR30" />
+ <Register size="4" start="0xFFFFF0FC" name="AIC_SVR31" />
+ <Register size="4" access="ReadOnly" start="0xFFFFF100" name="AIC_IVR" />
+ <Register size="4" access="ReadOnly" start="0xFFFFF104" name="AIC_FVR" />
+ <Register size="4" access="ReadOnly" start="0xFFFFF108" name="AIC_ISR" />
+ <Register size="4" access="ReadOnly" start="0xFFFFF10C" name="AIC_IPR" >
+ <BitField size="1" start="0" name="FIQ" />
+ <BitField size="1" start="1" name="SYS" />
+ <BitField size="1" start="2" name="PID2" />
+ <BitField size="1" start="3" name="PID3" />
+ <BitField size="1" start="4" name="PID4" />
+ <BitField size="1" start="5" name="PID5" />
+ <BitField size="1" start="6" name="PID6" />
+ <BitField size="1" start="7" name="PID7" />
+ <BitField size="1" start="8" name="PID8" />
+ <BitField size="1" start="9" name="PID9" />
+ <BitField size="1" start="10" name="PID10" />
+ <BitField size="1" start="11" name="PID11" />
+ <BitField size="1" start="12" name="PID12" />
+ <BitField size="1" start="13" name="PID13" />
+ <BitField size="1" start="14" name="PID14" />
+ <BitField size="1" start="15" name="PID15" />
+ <BitField size="1" start="16" name="PID16" />
+ <BitField size="1" start="17" name="PID17" />
+ <BitField size="1" start="18" name="PID18" />
+ <BitField size="1" start="19" name="PID19" />
+ <BitField size="1" start="20" name="PID20" />
+ <BitField size="1" start="21" name="PID21" />
+ <BitField size="1" start="22" name="PID22" />
+ <BitField size="1" start="23" name="PID23" />
+ <BitField size="1" start="24" name="PID24" />
+ <BitField size="1" start="25" name="PID25" />
+ <BitField size="1" start="26" name="PID26" />
+ <BitField size="1" start="27" name="PID27" />
+ <BitField size="1" start="28" name="PID28" />
+ <BitField size="1" start="29" name="PID29" />
+ <BitField size="1" start="30" name="PID30" />
+ <BitField size="1" start="31" name="PID31" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFFF110" name="AIC_IMR" >
+ <BitField size="1" start="0" name="FIQ" />
+ <BitField size="1" start="1" name="SYS" />
+ <BitField size="1" start="2" name="PID2" />
+ <BitField size="1" start="3" name="PID3" />
+ <BitField size="1" start="4" name="PID4" />
+ <BitField size="1" start="5" name="PID5" />
+ <BitField size="1" start="6" name="PID6" />
+ <BitField size="1" start="7" name="PID7" />
+ <BitField size="1" start="8" name="PID8" />
+ <BitField size="1" start="9" name="PID9" />
+ <BitField size="1" start="10" name="PID10" />
+ <BitField size="1" start="11" name="PID11" />
+ <BitField size="1" start="12" name="PID12" />
+ <BitField size="1" start="13" name="PID13" />
+ <BitField size="1" start="14" name="PID14" />
+ <BitField size="1" start="15" name="PID15" />
+ <BitField size="1" start="16" name="PID16" />
+ <BitField size="1" start="17" name="PID17" />
+ <BitField size="1" start="18" name="PID18" />
+ <BitField size="1" start="19" name="PID19" />
+ <BitField size="1" start="20" name="PID20" />
+ <BitField size="1" start="21" name="PID21" />
+ <BitField size="1" start="22" name="PID22" />
+ <BitField size="1" start="23" name="PID23" />
+ <BitField size="1" start="24" name="PID24" />
+ <BitField size="1" start="25" name="PID25" />
+ <BitField size="1" start="26" name="PID26" />
+ <BitField size="1" start="27" name="PID27" />
+ <BitField size="1" start="28" name="PID28" />
+ <BitField size="1" start="29" name="PID29" />
+ <BitField size="1" start="30" name="PID30" />
+ <BitField size="1" start="31" name="PID31" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFFF114" name="AIC_CISR" >
+ <BitField size="1" start="0" name="NFIQ" />
+ <BitField size="1" start="1" name="NIRQ" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFFF120" name="AIC_IECR" >
+ <BitField size="1" start="0" name="FIQ" />
+ <BitField size="1" start="1" name="SYS" />
+ <BitField size="1" start="2" name="PID2" />
+ <BitField size="1" start="3" name="PID3" />
+ <BitField size="1" start="4" name="PID4" />
+ <BitField size="1" start="5" name="PID5" />
+ <BitField size="1" start="6" name="PID6" />
+ <BitField size="1" start="7" name="PID7" />
+ <BitField size="1" start="8" name="PID8" />
+ <BitField size="1" start="9" name="PID9" />
+ <BitField size="1" start="10" name="PID10" />
+ <BitField size="1" start="11" name="PID11" />
+ <BitField size="1" start="12" name="PID12" />
+ <BitField size="1" start="13" name="PID13" />
+ <BitField size="1" start="14" name="PID14" />
+ <BitField size="1" start="15" name="PID15" />
+ <BitField size="1" start="16" name="PID16" />
+ <BitField size="1" start="17" name="PID17" />
+ <BitField size="1" start="18" name="PID18" />
+ <BitField size="1" start="19" name="PID19" />
+ <BitField size="1" start="20" name="PID20" />
+ <BitField size="1" start="21" name="PID21" />
+ <BitField size="1" start="22" name="PID22" />
+ <BitField size="1" start="23" name="PID23" />
+ <BitField size="1" start="24" name="PID24" />
+ <BitField size="1" start="25" name="PID25" />
+ <BitField size="1" start="26" name="PID26" />
+ <BitField size="1" start="27" name="PID27" />
+ <BitField size="1" start="28" name="PID28" />
+ <BitField size="1" start="29" name="PID29" />
+ <BitField size="1" start="30" name="PID30" />
+ <BitField size="1" start="31" name="PID31" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFFF124" name="AIC_IDCR" >
+ <BitField size="1" start="0" name="FIQ" />
+ <BitField size="1" start="1" name="SYS" />
+ <BitField size="1" start="2" name="PID2" />
+ <BitField size="1" start="3" name="PID3" />
+ <BitField size="1" start="4" name="PID4" />
+ <BitField size="1" start="5" name="PID5" />
+ <BitField size="1" start="6" name="PID6" />
+ <BitField size="1" start="7" name="PID7" />
+ <BitField size="1" start="8" name="PID8" />
+ <BitField size="1" start="9" name="PID9" />
+ <BitField size="1" start="10" name="PID10" />
+ <BitField size="1" start="11" name="PID11" />
+ <BitField size="1" start="12" name="PID12" />
+ <BitField size="1" start="13" name="PID13" />
+ <BitField size="1" start="14" name="PID14" />
+ <BitField size="1" start="15" name="PID15" />
+ <BitField size="1" start="16" name="PID16" />
+ <BitField size="1" start="17" name="PID17" />
+ <BitField size="1" start="18" name="PID18" />
+ <BitField size="1" start="19" name="PID19" />
+ <BitField size="1" start="20" name="PID20" />
+ <BitField size="1" start="21" name="PID21" />
+ <BitField size="1" start="22" name="PID22" />
+ <BitField size="1" start="23" name="PID23" />
+ <BitField size="1" start="24" name="PID24" />
+ <BitField size="1" start="25" name="PID25" />
+ <BitField size="1" start="26" name="PID26" />
+ <BitField size="1" start="27" name="PID27" />
+ <BitField size="1" start="28" name="PID28" />
+ <BitField size="1" start="29" name="PID29" />
+ <BitField size="1" start="30" name="PID30" />
+ <BitField size="1" start="31" name="PID31" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFFF128" name="AIC_ICCR" >
+ <BitField size="1" start="0" name="FIQ" />
+ <BitField size="1" start="1" name="SYS" />
+ <BitField size="1" start="2" name="PID2" />
+ <BitField size="1" start="3" name="PID3" />
+ <BitField size="1" start="4" name="PID4" />
+ <BitField size="1" start="5" name="PID5" />
+ <BitField size="1" start="6" name="PID6" />
+ <BitField size="1" start="7" name="PID7" />
+ <BitField size="1" start="8" name="PID8" />
+ <BitField size="1" start="9" name="PID9" />
+ <BitField size="1" start="10" name="PID10" />
+ <BitField size="1" start="11" name="PID11" />
+ <BitField size="1" start="12" name="PID12" />
+ <BitField size="1" start="13" name="PID13" />
+ <BitField size="1" start="14" name="PID14" />
+ <BitField size="1" start="15" name="PID15" />
+ <BitField size="1" start="16" name="PID16" />
+ <BitField size="1" start="17" name="PID17" />
+ <BitField size="1" start="18" name="PID18" />
+ <BitField size="1" start="19" name="PID19" />
+ <BitField size="1" start="20" name="PID20" />
+ <BitField size="1" start="21" name="PID21" />
+ <BitField size="1" start="22" name="PID22" />
+ <BitField size="1" start="23" name="PID23" />
+ <BitField size="1" start="24" name="PID24" />
+ <BitField size="1" start="25" name="PID25" />
+ <BitField size="1" start="26" name="PID26" />
+ <BitField size="1" start="27" name="PID27" />
+ <BitField size="1" start="28" name="PID28" />
+ <BitField size="1" start="29" name="PID29" />
+ <BitField size="1" start="30" name="PID30" />
+ <BitField size="1" start="31" name="PID31" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFFF12C" name="AIC_ISCR" >
+ <BitField size="1" start="0" name="FIQ" />
+ <BitField size="1" start="1" name="SYS" />
+ <BitField size="1" start="2" name="PID2" />
+ <BitField size="1" start="3" name="PID3" />
+ <BitField size="1" start="4" name="PID4" />
+ <BitField size="1" start="5" name="PID5" />
+ <BitField size="1" start="6" name="PID6" />
+ <BitField size="1" start="7" name="PID7" />
+ <BitField size="1" start="8" name="PID8" />
+ <BitField size="1" start="9" name="PID9" />
+ <BitField size="1" start="10" name="PID10" />
+ <BitField size="1" start="11" name="PID11" />
+ <BitField size="1" start="12" name="PID12" />
+ <BitField size="1" start="13" name="PID13" />
+ <BitField size="1" start="14" name="PID14" />
+ <BitField size="1" start="15" name="PID15" />
+ <BitField size="1" start="16" name="PID16" />
+ <BitField size="1" start="17" name="PID17" />
+ <BitField size="1" start="18" name="PID18" />
+ <BitField size="1" start="19" name="PID19" />
+ <BitField size="1" start="20" name="PID20" />
+ <BitField size="1" start="21" name="PID21" />
+ <BitField size="1" start="22" name="PID22" />
+ <BitField size="1" start="23" name="PID23" />
+ <BitField size="1" start="24" name="PID24" />
+ <BitField size="1" start="25" name="PID25" />
+ <BitField size="1" start="26" name="PID26" />
+ <BitField size="1" start="27" name="PID27" />
+ <BitField size="1" start="28" name="PID28" />
+ <BitField size="1" start="29" name="PID29" />
+ <BitField size="1" start="30" name="PID30" />
+ <BitField size="1" start="31" name="PID31" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFFF130" name="AIC_EOICR" />
+ <Register size="4" start="0xFFFFF134" name="AIC_SPU" />
+ <Register size="4" start="0xFFFFF138" name="AIC_DEBUG" >
+ <BitField size="1" start="0" name="PROT" />
+ <BitField size="1" start="1" name="GMSK" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFFF140" name="AIC_FFER" >
+ <BitField size="1" start="1" name="SYS" />
+ <BitField size="1" start="2" name="PID2" />
+ <BitField size="1" start="3" name="PID3" />
+ <BitField size="1" start="4" name="PID4" />
+ <BitField size="1" start="5" name="PID5" />
+ <BitField size="1" start="6" name="PID6" />
+ <BitField size="1" start="7" name="PID7" />
+ <BitField size="1" start="8" name="PID8" />
+ <BitField size="1" start="9" name="PID9" />
+ <BitField size="1" start="10" name="PID10" />
+ <BitField size="1" start="11" name="PID11" />
+ <BitField size="1" start="12" name="PID12" />
+ <BitField size="1" start="13" name="PID13" />
+ <BitField size="1" start="14" name="PID14" />
+ <BitField size="1" start="15" name="PID15" />
+ <BitField size="1" start="16" name="PID16" />
+ <BitField size="1" start="17" name="PID17" />
+ <BitField size="1" start="18" name="PID18" />
+ <BitField size="1" start="19" name="PID19" />
+ <BitField size="1" start="20" name="PID20" />
+ <BitField size="1" start="21" name="PID21" />
+ <BitField size="1" start="22" name="PID22" />
+ <BitField size="1" start="23" name="PID23" />
+ <BitField size="1" start="24" name="PID24" />
+ <BitField size="1" start="25" name="PID25" />
+ <BitField size="1" start="26" name="PID26" />
+ <BitField size="1" start="27" name="PID27" />
+ <BitField size="1" start="28" name="PID28" />
+ <BitField size="1" start="29" name="PID29" />
+ <BitField size="1" start="30" name="PID30" />
+ <BitField size="1" start="31" name="PID31" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFFF144" name="AIC_FFDR" >
+ <BitField size="1" start="1" name="SYS" />
+ <BitField size="1" start="2" name="PID2" />
+ <BitField size="1" start="3" name="PID3" />
+ <BitField size="1" start="4" name="PID4" />
+ <BitField size="1" start="5" name="PID5" />
+ <BitField size="1" start="6" name="PID6" />
+ <BitField size="1" start="7" name="PID7" />
+ <BitField size="1" start="8" name="PID8" />
+ <BitField size="1" start="9" name="PID9" />
+ <BitField size="1" start="10" name="PID10" />
+ <BitField size="1" start="11" name="PID11" />
+ <BitField size="1" start="12" name="PID12" />
+ <BitField size="1" start="13" name="PID13" />
+ <BitField size="1" start="14" name="PID14" />
+ <BitField size="1" start="15" name="PID15" />
+ <BitField size="1" start="16" name="PID16" />
+ <BitField size="1" start="17" name="PID17" />
+ <BitField size="1" start="18" name="PID18" />
+ <BitField size="1" start="19" name="PID19" />
+ <BitField size="1" start="20" name="PID20" />
+ <BitField size="1" start="21" name="PID21" />
+ <BitField size="1" start="22" name="PID22" />
+ <BitField size="1" start="23" name="PID23" />
+ <BitField size="1" start="24" name="PID24" />
+ <BitField size="1" start="25" name="PID25" />
+ <BitField size="1" start="26" name="PID26" />
+ <BitField size="1" start="27" name="PID27" />
+ <BitField size="1" start="28" name="PID28" />
+ <BitField size="1" start="29" name="PID29" />
+ <BitField size="1" start="30" name="PID30" />
+ <BitField size="1" start="31" name="PID31" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFFF148" name="AIC_FFSR" >
+ <BitField size="1" start="1" name="SYS" />
+ <BitField size="1" start="2" name="PID2" />
+ <BitField size="1" start="3" name="PID3" />
+ <BitField size="1" start="4" name="PID4" />
+ <BitField size="1" start="5" name="PID5" />
+ <BitField size="1" start="6" name="PID6" />
+ <BitField size="1" start="7" name="PID7" />
+ <BitField size="1" start="8" name="PID8" />
+ <BitField size="1" start="9" name="PID9" />
+ <BitField size="1" start="10" name="PID10" />
+ <BitField size="1" start="11" name="PID11" />
+ <BitField size="1" start="12" name="PID12" />
+ <BitField size="1" start="13" name="PID13" />
+ <BitField size="1" start="14" name="PID14" />
+ <BitField size="1" start="15" name="PID15" />
+ <BitField size="1" start="16" name="PID16" />
+ <BitField size="1" start="17" name="PID17" />
+ <BitField size="1" start="18" name="PID18" />
+ <BitField size="1" start="19" name="PID19" />
+ <BitField size="1" start="20" name="PID20" />
+ <BitField size="1" start="21" name="PID21" />
+ <BitField size="1" start="22" name="PID22" />
+ <BitField size="1" start="23" name="PID23" />
+ <BitField size="1" start="24" name="PID24" />
+ <BitField size="1" start="25" name="PID25" />
+ <BitField size="1" start="26" name="PID26" />
+ <BitField size="1" start="27" name="PID27" />
+ <BitField size="1" start="28" name="PID28" />
+ <BitField size="1" start="29" name="PID29" />
+ <BitField size="1" start="30" name="PID30" />
+ <BitField size="1" start="31" name="PID31" />
+ </Register>
+ </RegisterGroup>
+ <RegisterGroup start="0xFFFFF200" name="DBGU" >
+ <Register size="4" access="WriteOnly" start="0xFFFFF200" name="DBGU_CR" >
+ <BitField size="1" start="2" name="RSTRX" />
+ <BitField size="1" start="3" name="RSTTX" />
+ <BitField size="1" start="4" name="RXEN" />
+ <BitField size="1" start="5" name="RXDIS" />
+ <BitField size="1" start="6" name="TXEN" />
+ <BitField size="1" start="7" name="TXDIS" />
+ <BitField size="1" start="8" name="RSTSTA" />
+ </Register>
+ <Register size="4" start="0xFFFFF204" name="DBGU_MR" >
+ <BitField size="3" start="9" name="PAR" />
+ <BitField size="2" start="14" name="CHMODE" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFFF208" name="DBGU_IER" >
+ <BitField size="1" start="0" name="RXRDY" />
+ <BitField size="1" start="1" name="TXRDY" />
+ <BitField size="1" start="3" name="ENDRX" />
+ <BitField size="1" start="4" name="ENDTX" />
+ <BitField size="1" start="5" name="OVRE" />
+ <BitField size="1" start="6" name="FRAME" />
+ <BitField size="1" start="7" name="PARE" />
+ <BitField size="1" start="9" name="TXEMPTY" />
+ <BitField size="1" start="11" name="TXBUFE" />
+ <BitField size="1" start="12" name="RXBUFF" />
+ <BitField size="1" start="30" name="COMMTX" />
+ <BitField size="1" start="31" name="COMMRX" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFFF20C" name="DBGU_IDR" >
+ <BitField size="1" start="0" name="RXRDY" />
+ <BitField size="1" start="1" name="TXRDY" />
+ <BitField size="1" start="3" name="ENDRX" />
+ <BitField size="1" start="4" name="ENDTX" />
+ <BitField size="1" start="5" name="OVRE" />
+ <BitField size="1" start="6" name="FRAME" />
+ <BitField size="1" start="7" name="PARE" />
+ <BitField size="1" start="9" name="TXEMPTY" />
+ <BitField size="1" start="11" name="TXBUFE" />
+ <BitField size="1" start="12" name="RXBUFF" />
+ <BitField size="1" start="30" name="COMMTX" />
+ <BitField size="1" start="31" name="COMMRX" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFFF210" name="DBGU_IMR" >
+ <BitField size="1" start="0" name="RXRDY" />
+ <BitField size="1" start="1" name="TXRDY" />
+ <BitField size="1" start="3" name="ENDRX" />
+ <BitField size="1" start="4" name="ENDTX" />
+ <BitField size="1" start="5" name="OVRE" />
+ <BitField size="1" start="6" name="FRAME" />
+ <BitField size="1" start="7" name="PARE" />
+ <BitField size="1" start="9" name="TXEMPTY" />
+ <BitField size="1" start="11" name="TXBUFE" />
+ <BitField size="1" start="12" name="RXBUFF" />
+ <BitField size="1" start="30" name="COMMTX" />
+ <BitField size="1" start="31" name="COMMRX" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFFF214" name="DBGU_SR" >
+ <BitField size="1" start="0" name="RXRDY" />
+ <BitField size="1" start="1" name="TXRDY" />
+ <BitField size="1" start="3" name="ENDRX" />
+ <BitField size="1" start="4" name="ENDTX" />
+ <BitField size="1" start="5" name="OVRE" />
+ <BitField size="1" start="6" name="FRAME" />
+ <BitField size="1" start="7" name="PARE" />
+ <BitField size="1" start="9" name="TXEMPTY" />
+ <BitField size="1" start="11" name="TXBUFE" />
+ <BitField size="1" start="12" name="RXBUFF" />
+ <BitField size="1" start="30" name="COMMTX" />
+ <BitField size="1" start="31" name="COMMRX" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFFF218" name="DBGU_RHR" />
+ <Register size="4" access="WriteOnly" start="0xFFFFF21C" name="DBGU_THR" />
+ <Register size="4" start="0xFFFFF220" name="DBGU_BRGR" />
+ <Register size="4" access="ReadOnly" start="0xFFFFF240" name="DBGU_CIDR" >
+ <BitField size="5" start="0" name="VERSION" />
+ <BitField size="3" start="5" name="EPROC" />
+ <BitField size="4" start="8" name="NVPSIZ" />
+ <BitField size="4" start="12" name="NVPSIZ2" />
+ <BitField size="4" start="16" name="SRAMSIZ" />
+ <BitField size="8" start="20" name="ARCH" />
+ <BitField size="3" start="28" name="NVPTYP" />
+ <BitField size="1" start="31" name="EXT" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFFF244" name="DBGU_EXID" />
+ <Register size="4" start="0xFFFFF248" name="DBGU_FNR" />
+ <Register size="4" start="0xFFFFF300" name="DBGU_RPR" />
+ <Register size="4" start="0xFFFFF304" name="DBGU_RCR" />
+ <Register size="4" start="0xFFFFF308" name="DBGU_TPR" />
+ <Register size="4" start="0xFFFFF30C" name="DBGU_TCR" />
+ <Register size="4" start="0xFFFFF310" name="DBGU_RNPR" />
+ <Register size="4" start="0xFFFFF314" name="DBGU_RNCR" />
+ <Register size="4" start="0xFFFFF318" name="DBGU_TNPR" />
+ <Register size="4" start="0xFFFFF31C" name="DBGU_TNCR" />
+ <Register size="4" access="WriteOnly" start="0xFFFFF320" name="DBGU_PTCR" >
+ <BitField size="1" start="0" name="RXTEN" />
+ <BitField size="1" start="1" name="RXTDIS" />
+ <BitField size="1" start="8" name="TXTEN" />
+ <BitField size="4" start="9" name="TXTDIS" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFFF324" name="DBGU_PTSR" >
+ <BitField size="1" start="0" name="RXTEN" />
+ <BitField size="4" start="9" name="TXTEN" />
+ </Register>
+ </RegisterGroup>
+ <RegisterGroup start="0xFFFFF400" name="PIOA" >
+ <Register size="4" access="WriteOnly" start="0xFFFFF400" name="PIOA_PER" >
+ <BitField size="1" start="0" name="P0" />
+ <BitField size="1" start="1" name="P1" />
+ <BitField size="1" start="2" name="P2" />
+ <BitField size="1" start="3" name="P3" />
+ <BitField size="1" start="4" name="P4" />
+ <BitField size="1" start="5" name="P5" />
+ <BitField size="1" start="6" name="P6" />
+ <BitField size="1" start="7" name="P7" />
+ <BitField size="1" start="8" name="P8" />
+ <BitField size="1" start="9" name="P9" />
+ <BitField size="1" start="10" name="P10" />
+ <BitField size="1" start="11" name="P11" />
+ <BitField size="1" start="12" name="P12" />
+ <BitField size="1" start="13" name="P13" />
+ <BitField size="1" start="14" name="P14" />
+ <BitField size="1" start="15" name="P15" />
+ <BitField size="1" start="16" name="P16" />
+ <BitField size="1" start="17" name="P17" />
+ <BitField size="1" start="18" name="P18" />
+ <BitField size="1" start="19" name="P19" />
+ <BitField size="1" start="20" name="P20" />
+ <BitField size="1" start="21" name="P21" />
+ <BitField size="1" start="22" name="P22" />
+ <BitField size="1" start="23" name="P23" />
+ <BitField size="1" start="24" name="P24" />
+ <BitField size="1" start="25" name="P25" />
+ <BitField size="1" start="26" name="P26" />
+ <BitField size="1" start="27" name="P27" />
+ <BitField size="1" start="28" name="P28" />
+ <BitField size="1" start="29" name="P29" />
+ <BitField size="1" start="30" name="P30" />
+ <BitField size="1" start="31" name="P31" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFFF404" name="PIOA_PDR" >
+ <BitField size="1" start="0" name="P0" />
+ <BitField size="1" start="1" name="P1" />
+ <BitField size="1" start="2" name="P2" />
+ <BitField size="1" start="3" name="P3" />
+ <BitField size="1" start="4" name="P4" />
+ <BitField size="1" start="5" name="P5" />
+ <BitField size="1" start="6" name="P6" />
+ <BitField size="1" start="7" name="P7" />
+ <BitField size="1" start="8" name="P8" />
+ <BitField size="1" start="9" name="P9" />
+ <BitField size="1" start="10" name="P10" />
+ <BitField size="1" start="11" name="P11" />
+ <BitField size="1" start="12" name="P12" />
+ <BitField size="1" start="13" name="P13" />
+ <BitField size="1" start="14" name="P14" />
+ <BitField size="1" start="15" name="P15" />
+ <BitField size="1" start="16" name="P16" />
+ <BitField size="1" start="17" name="P17" />
+ <BitField size="1" start="18" name="P18" />
+ <BitField size="1" start="19" name="P19" />
+ <BitField size="1" start="20" name="P20" />
+ <BitField size="1" start="21" name="P21" />
+ <BitField size="1" start="22" name="P22" />
+ <BitField size="1" start="23" name="P23" />
+ <BitField size="1" start="24" name="P24" />
+ <BitField size="1" start="25" name="P25" />
+ <BitField size="1" start="26" name="P26" />
+ <BitField size="1" start="27" name="P27" />
+ <BitField size="1" start="28" name="P28" />
+ <BitField size="1" start="29" name="P29" />
+ <BitField size="1" start="30" name="P30" />
+ <BitField size="1" start="31" name="P31" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFFF408" name="PIOA_PSR" >
+ <BitField size="1" start="0" name="P0" />
+ <BitField size="1" start="1" name="P1" />
+ <BitField size="1" start="2" name="P2" />
+ <BitField size="1" start="3" name="P3" />
+ <BitField size="1" start="4" name="P4" />
+ <BitField size="1" start="5" name="P5" />
+ <BitField size="1" start="6" name="P6" />
+ <BitField size="1" start="7" name="P7" />
+ <BitField size="1" start="8" name="P8" />
+ <BitField size="1" start="9" name="P9" />
+ <BitField size="1" start="10" name="P10" />
+ <BitField size="1" start="11" name="P11" />
+ <BitField size="1" start="12" name="P12" />
+ <BitField size="1" start="13" name="P13" />
+ <BitField size="1" start="14" name="P14" />
+ <BitField size="1" start="15" name="P15" />
+ <BitField size="1" start="16" name="P16" />
+ <BitField size="1" start="17" name="P17" />
+ <BitField size="1" start="18" name="P18" />
+ <BitField size="1" start="19" name="P19" />
+ <BitField size="1" start="20" name="P20" />
+ <BitField size="1" start="21" name="P21" />
+ <BitField size="1" start="22" name="P22" />
+ <BitField size="1" start="23" name="P23" />
+ <BitField size="1" start="24" name="P24" />
+ <BitField size="1" start="25" name="P25" />
+ <BitField size="1" start="26" name="P26" />
+ <BitField size="1" start="27" name="P27" />
+ <BitField size="1" start="28" name="P28" />
+ <BitField size="1" start="29" name="P29" />
+ <BitField size="1" start="30" name="P30" />
+ <BitField size="1" start="31" name="P31" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFFF410" name="PIOA_OER" >
+ <BitField size="1" start="0" name="P0" />
+ <BitField size="1" start="1" name="P1" />
+ <BitField size="1" start="2" name="P2" />
+ <BitField size="1" start="3" name="P3" />
+ <BitField size="1" start="4" name="P4" />
+ <BitField size="1" start="5" name="P5" />
+ <BitField size="1" start="6" name="P6" />
+ <BitField size="1" start="7" name="P7" />
+ <BitField size="1" start="8" name="P8" />
+ <BitField size="1" start="9" name="P9" />
+ <BitField size="1" start="10" name="P10" />
+ <BitField size="1" start="11" name="P11" />
+ <BitField size="1" start="12" name="P12" />
+ <BitField size="1" start="13" name="P13" />
+ <BitField size="1" start="14" name="P14" />
+ <BitField size="1" start="15" name="P15" />
+ <BitField size="1" start="16" name="P16" />
+ <BitField size="1" start="17" name="P17" />
+ <BitField size="1" start="18" name="P18" />
+ <BitField size="1" start="19" name="P19" />
+ <BitField size="1" start="20" name="P20" />
+ <BitField size="1" start="21" name="P21" />
+ <BitField size="1" start="22" name="P22" />
+ <BitField size="1" start="23" name="P23" />
+ <BitField size="1" start="24" name="P24" />
+ <BitField size="1" start="25" name="P25" />
+ <BitField size="1" start="26" name="P26" />
+ <BitField size="1" start="27" name="P27" />
+ <BitField size="1" start="28" name="P28" />
+ <BitField size="1" start="29" name="P29" />
+ <BitField size="1" start="30" name="P30" />
+ <BitField size="1" start="31" name="P31" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFFF414" name="PIOA_ODR" >
+ <BitField size="1" start="0" name="P0" />
+ <BitField size="1" start="1" name="P1" />
+ <BitField size="1" start="2" name="P2" />
+ <BitField size="1" start="3" name="P3" />
+ <BitField size="1" start="4" name="P4" />
+ <BitField size="1" start="5" name="P5" />
+ <BitField size="1" start="6" name="P6" />
+ <BitField size="1" start="7" name="P7" />
+ <BitField size="1" start="8" name="P8" />
+ <BitField size="1" start="9" name="P9" />
+ <BitField size="1" start="10" name="P10" />
+ <BitField size="1" start="11" name="P11" />
+ <BitField size="1" start="12" name="P12" />
+ <BitField size="1" start="13" name="P13" />
+ <BitField size="1" start="14" name="P14" />
+ <BitField size="1" start="15" name="P15" />
+ <BitField size="1" start="16" name="P16" />
+ <BitField size="1" start="17" name="P17" />
+ <BitField size="1" start="18" name="P18" />
+ <BitField size="1" start="19" name="P19" />
+ <BitField size="1" start="20" name="P20" />
+ <BitField size="1" start="21" name="P21" />
+ <BitField size="1" start="22" name="P22" />
+ <BitField size="1" start="23" name="P23" />
+ <BitField size="1" start="24" name="P24" />
+ <BitField size="1" start="25" name="P25" />
+ <BitField size="1" start="26" name="P26" />
+ <BitField size="1" start="27" name="P27" />
+ <BitField size="1" start="28" name="P28" />
+ <BitField size="1" start="29" name="P29" />
+ <BitField size="1" start="30" name="P30" />
+ <BitField size="1" start="31" name="P31" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFFF418" name="PIOA_OSR" >
+ <BitField size="1" start="0" name="P0" />
+ <BitField size="1" start="1" name="P1" />
+ <BitField size="1" start="2" name="P2" />
+ <BitField size="1" start="3" name="P3" />
+ <BitField size="1" start="4" name="P4" />
+ <BitField size="1" start="5" name="P5" />
+ <BitField size="1" start="6" name="P6" />
+ <BitField size="1" start="7" name="P7" />
+ <BitField size="1" start="8" name="P8" />
+ <BitField size="1" start="9" name="P9" />
+ <BitField size="1" start="10" name="P10" />
+ <BitField size="1" start="11" name="P11" />
+ <BitField size="1" start="12" name="P12" />
+ <BitField size="1" start="13" name="P13" />
+ <BitField size="1" start="14" name="P14" />
+ <BitField size="1" start="15" name="P15" />
+ <BitField size="1" start="16" name="P16" />
+ <BitField size="1" start="17" name="P17" />
+ <BitField size="1" start="18" name="P18" />
+ <BitField size="1" start="19" name="P19" />
+ <BitField size="1" start="20" name="P20" />
+ <BitField size="1" start="21" name="P21" />
+ <BitField size="1" start="22" name="P22" />
+ <BitField size="1" start="23" name="P23" />
+ <BitField size="1" start="24" name="P24" />
+ <BitField size="1" start="25" name="P25" />
+ <BitField size="1" start="26" name="P26" />
+ <BitField size="1" start="27" name="P27" />
+ <BitField size="1" start="28" name="P28" />
+ <BitField size="1" start="29" name="P29" />
+ <BitField size="1" start="30" name="P30" />
+ <BitField size="1" start="31" name="P31" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFFF420" name="PIOA_IFER" >
+ <BitField size="1" start="0" name="P0" />
+ <BitField size="1" start="1" name="P1" />
+ <BitField size="1" start="2" name="P2" />
+ <BitField size="1" start="3" name="P3" />
+ <BitField size="1" start="4" name="P4" />
+ <BitField size="1" start="5" name="P5" />
+ <BitField size="1" start="6" name="P6" />
+ <BitField size="1" start="7" name="P7" />
+ <BitField size="1" start="8" name="P8" />
+ <BitField size="1" start="9" name="P9" />
+ <BitField size="1" start="10" name="P10" />
+ <BitField size="1" start="11" name="P11" />
+ <BitField size="1" start="12" name="P12" />
+ <BitField size="1" start="13" name="P13" />
+ <BitField size="1" start="14" name="P14" />
+ <BitField size="1" start="15" name="P15" />
+ <BitField size="1" start="16" name="P16" />
+ <BitField size="1" start="17" name="P17" />
+ <BitField size="1" start="18" name="P18" />
+ <BitField size="1" start="19" name="P19" />
+ <BitField size="1" start="20" name="P20" />
+ <BitField size="1" start="21" name="P21" />
+ <BitField size="1" start="22" name="P22" />
+ <BitField size="1" start="23" name="P23" />
+ <BitField size="1" start="24" name="P24" />
+ <BitField size="1" start="25" name="P25" />
+ <BitField size="1" start="26" name="P26" />
+ <BitField size="1" start="27" name="P27" />
+ <BitField size="1" start="28" name="P28" />
+ <BitField size="1" start="29" name="P29" />
+ <BitField size="1" start="30" name="P30" />
+ <BitField size="1" start="31" name="P31" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFFF424" name="PIOA_IFDR" >
+ <BitField size="1" start="0" name="P0" />
+ <BitField size="1" start="1" name="P1" />
+ <BitField size="1" start="2" name="P2" />
+ <BitField size="1" start="3" name="P3" />
+ <BitField size="1" start="4" name="P4" />
+ <BitField size="1" start="5" name="P5" />
+ <BitField size="1" start="6" name="P6" />
+ <BitField size="1" start="7" name="P7" />
+ <BitField size="1" start="8" name="P8" />
+ <BitField size="1" start="9" name="P9" />
+ <BitField size="1" start="10" name="P10" />
+ <BitField size="1" start="11" name="P11" />
+ <BitField size="1" start="12" name="P12" />
+ <BitField size="1" start="13" name="P13" />
+ <BitField size="1" start="14" name="P14" />
+ <BitField size="1" start="15" name="P15" />
+ <BitField size="1" start="16" name="P16" />
+ <BitField size="1" start="17" name="P17" />
+ <BitField size="1" start="18" name="P18" />
+ <BitField size="1" start="19" name="P19" />
+ <BitField size="1" start="20" name="P20" />
+ <BitField size="1" start="21" name="P21" />
+ <BitField size="1" start="22" name="P22" />
+ <BitField size="1" start="23" name="P23" />
+ <BitField size="1" start="24" name="P24" />
+ <BitField size="1" start="25" name="P25" />
+ <BitField size="1" start="26" name="P26" />
+ <BitField size="1" start="27" name="P27" />
+ <BitField size="1" start="28" name="P28" />
+ <BitField size="1" start="29" name="P29" />
+ <BitField size="1" start="30" name="P30" />
+ <BitField size="1" start="31" name="P31" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFFF428" name="PIOA_IFSR" >
+ <BitField size="1" start="0" name="P0" />
+ <BitField size="1" start="1" name="P1" />
+ <BitField size="1" start="2" name="P2" />
+ <BitField size="1" start="3" name="P3" />
+ <BitField size="1" start="4" name="P4" />
+ <BitField size="1" start="5" name="P5" />
+ <BitField size="1" start="6" name="P6" />
+ <BitField size="1" start="7" name="P7" />
+ <BitField size="1" start="8" name="P8" />
+ <BitField size="1" start="9" name="P9" />
+ <BitField size="1" start="10" name="P10" />
+ <BitField size="1" start="11" name="P11" />
+ <BitField size="1" start="12" name="P12" />
+ <BitField size="1" start="13" name="P13" />
+ <BitField size="1" start="14" name="P14" />
+ <BitField size="1" start="15" name="P15" />
+ <BitField size="1" start="16" name="P16" />
+ <BitField size="1" start="17" name="P17" />
+ <BitField size="1" start="18" name="P18" />
+ <BitField size="1" start="19" name="P19" />
+ <BitField size="1" start="20" name="P20" />
+ <BitField size="1" start="21" name="P21" />
+ <BitField size="1" start="22" name="P22" />
+ <BitField size="1" start="23" name="P23" />
+ <BitField size="1" start="24" name="P24" />
+ <BitField size="1" start="25" name="P25" />
+ <BitField size="1" start="26" name="P26" />
+ <BitField size="1" start="27" name="P27" />
+ <BitField size="1" start="28" name="P28" />
+ <BitField size="1" start="29" name="P29" />
+ <BitField size="1" start="30" name="P30" />
+ <BitField size="1" start="31" name="P31" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFFF430" name="PIOA_SODR" >
+ <BitField size="1" start="0" name="P0" />
+ <BitField size="1" start="1" name="P1" />
+ <BitField size="1" start="2" name="P2" />
+ <BitField size="1" start="3" name="P3" />
+ <BitField size="1" start="4" name="P4" />
+ <BitField size="1" start="5" name="P5" />
+ <BitField size="1" start="6" name="P6" />
+ <BitField size="1" start="7" name="P7" />
+ <BitField size="1" start="8" name="P8" />
+ <BitField size="1" start="9" name="P9" />
+ <BitField size="1" start="10" name="P10" />
+ <BitField size="1" start="11" name="P11" />
+ <BitField size="1" start="12" name="P12" />
+ <BitField size="1" start="13" name="P13" />
+ <BitField size="1" start="14" name="P14" />
+ <BitField size="1" start="15" name="P15" />
+ <BitField size="1" start="16" name="P16" />
+ <BitField size="1" start="17" name="P17" />
+ <BitField size="1" start="18" name="P18" />
+ <BitField size="1" start="19" name="P19" />
+ <BitField size="1" start="20" name="P20" />
+ <BitField size="1" start="21" name="P21" />
+ <BitField size="1" start="22" name="P22" />
+ <BitField size="1" start="23" name="P23" />
+ <BitField size="1" start="24" name="P24" />
+ <BitField size="1" start="25" name="P25" />
+ <BitField size="1" start="26" name="P26" />
+ <BitField size="1" start="27" name="P27" />
+ <BitField size="1" start="28" name="P28" />
+ <BitField size="1" start="29" name="P29" />
+ <BitField size="1" start="30" name="P30" />
+ <BitField size="1" start="31" name="P31" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFFF434" name="PIOA_CODR" >
+ <BitField size="1" start="0" name="P0" />
+ <BitField size="1" start="1" name="P1" />
+ <BitField size="1" start="2" name="P2" />
+ <BitField size="1" start="3" name="P3" />
+ <BitField size="1" start="4" name="P4" />
+ <BitField size="1" start="5" name="P5" />
+ <BitField size="1" start="6" name="P6" />
+ <BitField size="1" start="7" name="P7" />
+ <BitField size="1" start="8" name="P8" />
+ <BitField size="1" start="9" name="P9" />
+ <BitField size="1" start="10" name="P10" />
+ <BitField size="1" start="11" name="P11" />
+ <BitField size="1" start="12" name="P12" />
+ <BitField size="1" start="13" name="P13" />
+ <BitField size="1" start="14" name="P14" />
+ <BitField size="1" start="15" name="P15" />
+ <BitField size="1" start="16" name="P16" />
+ <BitField size="1" start="17" name="P17" />
+ <BitField size="1" start="18" name="P18" />
+ <BitField size="1" start="19" name="P19" />
+ <BitField size="1" start="20" name="P20" />
+ <BitField size="1" start="21" name="P21" />
+ <BitField size="1" start="22" name="P22" />
+ <BitField size="1" start="23" name="P23" />
+ <BitField size="1" start="24" name="P24" />
+ <BitField size="1" start="25" name="P25" />
+ <BitField size="1" start="26" name="P26" />
+ <BitField size="1" start="27" name="P27" />
+ <BitField size="1" start="28" name="P28" />
+ <BitField size="1" start="29" name="P29" />
+ <BitField size="1" start="30" name="P30" />
+ <BitField size="1" start="31" name="P31" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFFF438" name="PIOA_ODSR" >
+ <BitField size="1" start="0" name="P0" />
+ <BitField size="1" start="1" name="P1" />
+ <BitField size="1" start="2" name="P2" />
+ <BitField size="1" start="3" name="P3" />
+ <BitField size="1" start="4" name="P4" />
+ <BitField size="1" start="5" name="P5" />
+ <BitField size="1" start="6" name="P6" />
+ <BitField size="1" start="7" name="P7" />
+ <BitField size="1" start="8" name="P8" />
+ <BitField size="1" start="9" name="P9" />
+ <BitField size="1" start="10" name="P10" />
+ <BitField size="1" start="11" name="P11" />
+ <BitField size="1" start="12" name="P12" />
+ <BitField size="1" start="13" name="P13" />
+ <BitField size="1" start="14" name="P14" />
+ <BitField size="1" start="15" name="P15" />
+ <BitField size="1" start="16" name="P16" />
+ <BitField size="1" start="17" name="P17" />
+ <BitField size="1" start="18" name="P18" />
+ <BitField size="1" start="19" name="P19" />
+ <BitField size="1" start="20" name="P20" />
+ <BitField size="1" start="21" name="P21" />
+ <BitField size="1" start="22" name="P22" />
+ <BitField size="1" start="23" name="P23" />
+ <BitField size="1" start="24" name="P24" />
+ <BitField size="1" start="25" name="P25" />
+ <BitField size="1" start="26" name="P26" />
+ <BitField size="1" start="27" name="P27" />
+ <BitField size="1" start="28" name="P28" />
+ <BitField size="1" start="29" name="P29" />
+ <BitField size="1" start="30" name="P30" />
+ <BitField size="1" start="31" name="P31" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFFF43C" name="PIOA_PDSR" >
+ <BitField size="1" start="0" name="P0" />
+ <BitField size="1" start="1" name="P1" />
+ <BitField size="1" start="2" name="P2" />
+ <BitField size="1" start="3" name="P3" />
+ <BitField size="1" start="4" name="P4" />
+ <BitField size="1" start="5" name="P5" />
+ <BitField size="1" start="6" name="P6" />
+ <BitField size="1" start="7" name="P7" />
+ <BitField size="1" start="8" name="P8" />
+ <BitField size="1" start="9" name="P9" />
+ <BitField size="1" start="10" name="P10" />
+ <BitField size="1" start="11" name="P11" />
+ <BitField size="1" start="12" name="P12" />
+ <BitField size="1" start="13" name="P13" />
+ <BitField size="1" start="14" name="P14" />
+ <BitField size="1" start="15" name="P15" />
+ <BitField size="1" start="16" name="P16" />
+ <BitField size="1" start="17" name="P17" />
+ <BitField size="1" start="18" name="P18" />
+ <BitField size="1" start="19" name="P19" />
+ <BitField size="1" start="20" name="P20" />
+ <BitField size="1" start="21" name="P21" />
+ <BitField size="1" start="22" name="P22" />
+ <BitField size="1" start="23" name="P23" />
+ <BitField size="1" start="24" name="P24" />
+ <BitField size="1" start="25" name="P25" />
+ <BitField size="1" start="26" name="P26" />
+ <BitField size="1" start="27" name="P27" />
+ <BitField size="1" start="28" name="P28" />
+ <BitField size="1" start="29" name="P29" />
+ <BitField size="1" start="30" name="P30" />
+ <BitField size="1" start="31" name="P31" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFFF440" name="PIOA_IER" >
+ <BitField size="1" start="0" name="P0" />
+ <BitField size="1" start="1" name="P1" />
+ <BitField size="1" start="2" name="P2" />
+ <BitField size="1" start="3" name="P3" />
+ <BitField size="1" start="4" name="P4" />
+ <BitField size="1" start="5" name="P5" />
+ <BitField size="1" start="6" name="P6" />
+ <BitField size="1" start="7" name="P7" />
+ <BitField size="1" start="8" name="P8" />
+ <BitField size="1" start="9" name="P9" />
+ <BitField size="1" start="10" name="P10" />
+ <BitField size="1" start="11" name="P11" />
+ <BitField size="1" start="12" name="P12" />
+ <BitField size="1" start="13" name="P13" />
+ <BitField size="1" start="14" name="P14" />
+ <BitField size="1" start="15" name="P15" />
+ <BitField size="1" start="16" name="P16" />
+ <BitField size="1" start="17" name="P17" />
+ <BitField size="1" start="18" name="P18" />
+ <BitField size="1" start="19" name="P19" />
+ <BitField size="1" start="20" name="P20" />
+ <BitField size="1" start="21" name="P21" />
+ <BitField size="1" start="22" name="P22" />
+ <BitField size="1" start="23" name="P23" />
+ <BitField size="1" start="24" name="P24" />
+ <BitField size="1" start="25" name="P25" />
+ <BitField size="1" start="26" name="P26" />
+ <BitField size="1" start="27" name="P27" />
+ <BitField size="1" start="28" name="P28" />
+ <BitField size="1" start="29" name="P29" />
+ <BitField size="1" start="30" name="P30" />
+ <BitField size="1" start="31" name="P31" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFFF444" name="PIOA_IDR" >
+ <BitField size="1" start="0" name="P0" />
+ <BitField size="1" start="1" name="P1" />
+ <BitField size="1" start="2" name="P2" />
+ <BitField size="1" start="3" name="P3" />
+ <BitField size="1" start="4" name="P4" />
+ <BitField size="1" start="5" name="P5" />
+ <BitField size="1" start="6" name="P6" />
+ <BitField size="1" start="7" name="P7" />
+ <BitField size="1" start="8" name="P8" />
+ <BitField size="1" start="9" name="P9" />
+ <BitField size="1" start="10" name="P10" />
+ <BitField size="1" start="11" name="P11" />
+ <BitField size="1" start="12" name="P12" />
+ <BitField size="1" start="13" name="P13" />
+ <BitField size="1" start="14" name="P14" />
+ <BitField size="1" start="15" name="P15" />
+ <BitField size="1" start="16" name="P16" />
+ <BitField size="1" start="17" name="P17" />
+ <BitField size="1" start="18" name="P18" />
+ <BitField size="1" start="19" name="P19" />
+ <BitField size="1" start="20" name="P20" />
+ <BitField size="1" start="21" name="P21" />
+ <BitField size="1" start="22" name="P22" />
+ <BitField size="1" start="23" name="P23" />
+ <BitField size="1" start="24" name="P24" />
+ <BitField size="1" start="25" name="P25" />
+ <BitField size="1" start="26" name="P26" />
+ <BitField size="1" start="27" name="P27" />
+ <BitField size="1" start="28" name="P28" />
+ <BitField size="1" start="29" name="P29" />
+ <BitField size="1" start="30" name="P30" />
+ <BitField size="1" start="31" name="P31" />
+ </Register>
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+ <BitField size="1" start="0" name="P0" />
+ <BitField size="1" start="1" name="P1" />
+ <BitField size="1" start="2" name="P2" />
+ <BitField size="1" start="3" name="P3" />
+ <BitField size="1" start="4" name="P4" />
+ <BitField size="1" start="5" name="P5" />
+ <BitField size="1" start="6" name="P6" />
+ <BitField size="1" start="7" name="P7" />
+ <BitField size="1" start="8" name="P8" />
+ <BitField size="1" start="9" name="P9" />
+ <BitField size="1" start="10" name="P10" />
+ <BitField size="1" start="11" name="P11" />
+ <BitField size="1" start="12" name="P12" />
+ <BitField size="1" start="13" name="P13" />
+ <BitField size="1" start="14" name="P14" />
+ <BitField size="1" start="15" name="P15" />
+ <BitField size="1" start="16" name="P16" />
+ <BitField size="1" start="17" name="P17" />
+ <BitField size="1" start="18" name="P18" />
+ <BitField size="1" start="19" name="P19" />
+ <BitField size="1" start="20" name="P20" />
+ <BitField size="1" start="21" name="P21" />
+ <BitField size="1" start="22" name="P22" />
+ <BitField size="1" start="23" name="P23" />
+ <BitField size="1" start="24" name="P24" />
+ <BitField size="1" start="25" name="P25" />
+ <BitField size="1" start="26" name="P26" />
+ <BitField size="1" start="27" name="P27" />
+ <BitField size="1" start="28" name="P28" />
+ <BitField size="1" start="29" name="P29" />
+ <BitField size="1" start="30" name="P30" />
+ <BitField size="1" start="31" name="P31" />
+ </Register>
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+ <BitField size="1" start="1" name="P1" />
+ <BitField size="1" start="2" name="P2" />
+ <BitField size="1" start="3" name="P3" />
+ <BitField size="1" start="4" name="P4" />
+ <BitField size="1" start="5" name="P5" />
+ <BitField size="1" start="6" name="P6" />
+ <BitField size="1" start="7" name="P7" />
+ <BitField size="1" start="8" name="P8" />
+ <BitField size="1" start="9" name="P9" />
+ <BitField size="1" start="10" name="P10" />
+ <BitField size="1" start="11" name="P11" />
+ <BitField size="1" start="12" name="P12" />
+ <BitField size="1" start="13" name="P13" />
+ <BitField size="1" start="14" name="P14" />
+ <BitField size="1" start="15" name="P15" />
+ <BitField size="1" start="16" name="P16" />
+ <BitField size="1" start="17" name="P17" />
+ <BitField size="1" start="18" name="P18" />
+ <BitField size="1" start="19" name="P19" />
+ <BitField size="1" start="20" name="P20" />
+ <BitField size="1" start="21" name="P21" />
+ <BitField size="1" start="22" name="P22" />
+ <BitField size="1" start="23" name="P23" />
+ <BitField size="1" start="24" name="P24" />
+ <BitField size="1" start="25" name="P25" />
+ <BitField size="1" start="26" name="P26" />
+ <BitField size="1" start="27" name="P27" />
+ <BitField size="1" start="28" name="P28" />
+ <BitField size="1" start="29" name="P29" />
+ <BitField size="1" start="30" name="P30" />
+ <BitField size="1" start="31" name="P31" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFFF450" name="PIOA_MDER" >
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+ <BitField size="1" start="1" name="P1" />
+ <BitField size="1" start="2" name="P2" />
+ <BitField size="1" start="3" name="P3" />
+ <BitField size="1" start="4" name="P4" />
+ <BitField size="1" start="5" name="P5" />
+ <BitField size="1" start="6" name="P6" />
+ <BitField size="1" start="7" name="P7" />
+ <BitField size="1" start="8" name="P8" />
+ <BitField size="1" start="9" name="P9" />
+ <BitField size="1" start="10" name="P10" />
+ <BitField size="1" start="11" name="P11" />
+ <BitField size="1" start="12" name="P12" />
+ <BitField size="1" start="13" name="P13" />
+ <BitField size="1" start="14" name="P14" />
+ <BitField size="1" start="15" name="P15" />
+ <BitField size="1" start="16" name="P16" />
+ <BitField size="1" start="17" name="P17" />
+ <BitField size="1" start="18" name="P18" />
+ <BitField size="1" start="19" name="P19" />
+ <BitField size="1" start="20" name="P20" />
+ <BitField size="1" start="21" name="P21" />
+ <BitField size="1" start="22" name="P22" />
+ <BitField size="1" start="23" name="P23" />
+ <BitField size="1" start="24" name="P24" />
+ <BitField size="1" start="25" name="P25" />
+ <BitField size="1" start="26" name="P26" />
+ <BitField size="1" start="27" name="P27" />
+ <BitField size="1" start="28" name="P28" />
+ <BitField size="1" start="29" name="P29" />
+ <BitField size="1" start="30" name="P30" />
+ <BitField size="1" start="31" name="P31" />
+ </Register>
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+ <BitField size="1" start="0" name="P0" />
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+ <BitField size="1" start="2" name="P2" />
+ <BitField size="1" start="3" name="P3" />
+ <BitField size="1" start="4" name="P4" />
+ <BitField size="1" start="5" name="P5" />
+ <BitField size="1" start="6" name="P6" />
+ <BitField size="1" start="7" name="P7" />
+ <BitField size="1" start="8" name="P8" />
+ <BitField size="1" start="9" name="P9" />
+ <BitField size="1" start="10" name="P10" />
+ <BitField size="1" start="11" name="P11" />
+ <BitField size="1" start="12" name="P12" />
+ <BitField size="1" start="13" name="P13" />
+ <BitField size="1" start="14" name="P14" />
+ <BitField size="1" start="15" name="P15" />
+ <BitField size="1" start="16" name="P16" />
+ <BitField size="1" start="17" name="P17" />
+ <BitField size="1" start="18" name="P18" />
+ <BitField size="1" start="19" name="P19" />
+ <BitField size="1" start="20" name="P20" />
+ <BitField size="1" start="21" name="P21" />
+ <BitField size="1" start="22" name="P22" />
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+ <BitField size="1" start="24" name="P24" />
+ <BitField size="1" start="25" name="P25" />
+ <BitField size="1" start="26" name="P26" />
+ <BitField size="1" start="27" name="P27" />
+ <BitField size="1" start="28" name="P28" />
+ <BitField size="1" start="29" name="P29" />
+ <BitField size="1" start="30" name="P30" />
+ <BitField size="1" start="31" name="P31" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFFF458" name="PIOA_MDSR" >
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+ <BitField size="1" start="3" name="P3" />
+ <BitField size="1" start="4" name="P4" />
+ <BitField size="1" start="5" name="P5" />
+ <BitField size="1" start="6" name="P6" />
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+ <BitField size="1" start="8" name="P8" />
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+ <BitField size="1" start="10" name="P10" />
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+ <BitField size="1" start="13" name="P13" />
+ <BitField size="1" start="14" name="P14" />
+ <BitField size="1" start="15" name="P15" />
+ <BitField size="1" start="16" name="P16" />
+ <BitField size="1" start="17" name="P17" />
+ <BitField size="1" start="18" name="P18" />
+ <BitField size="1" start="19" name="P19" />
+ <BitField size="1" start="20" name="P20" />
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+ <BitField size="1" start="24" name="P24" />
+ <BitField size="1" start="25" name="P25" />
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+ <BitField size="1" start="29" name="P29" />
+ <BitField size="1" start="30" name="P30" />
+ <BitField size="1" start="31" name="P31" />
+ </Register>
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+ <BitField size="1" start="5" name="P5" />
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+ <BitField size="1" start="8" name="P8" />
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+ <BitField size="1" start="10" name="P10" />
+ <BitField size="1" start="11" name="P11" />
+ <BitField size="1" start="12" name="P12" />
+ <BitField size="1" start="13" name="P13" />
+ <BitField size="1" start="14" name="P14" />
+ <BitField size="1" start="15" name="P15" />
+ <BitField size="1" start="16" name="P16" />
+ <BitField size="1" start="17" name="P17" />
+ <BitField size="1" start="18" name="P18" />
+ <BitField size="1" start="19" name="P19" />
+ <BitField size="1" start="20" name="P20" />
+ <BitField size="1" start="21" name="P21" />
+ <BitField size="1" start="22" name="P22" />
+ <BitField size="1" start="23" name="P23" />
+ <BitField size="1" start="24" name="P24" />
+ <BitField size="1" start="25" name="P25" />
+ <BitField size="1" start="26" name="P26" />
+ <BitField size="1" start="27" name="P27" />
+ <BitField size="1" start="28" name="P28" />
+ <BitField size="1" start="29" name="P29" />
+ <BitField size="1" start="30" name="P30" />
+ <BitField size="1" start="31" name="P31" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFFF464" name="PIOA_PUER" >
+ <BitField size="1" start="0" name="P0" />
+ <BitField size="1" start="1" name="P1" />
+ <BitField size="1" start="2" name="P2" />
+ <BitField size="1" start="3" name="P3" />
+ <BitField size="1" start="4" name="P4" />
+ <BitField size="1" start="5" name="P5" />
+ <BitField size="1" start="6" name="P6" />
+ <BitField size="1" start="7" name="P7" />
+ <BitField size="1" start="8" name="P8" />
+ <BitField size="1" start="9" name="P9" />
+ <BitField size="1" start="10" name="P10" />
+ <BitField size="1" start="11" name="P11" />
+ <BitField size="1" start="12" name="P12" />
+ <BitField size="1" start="13" name="P13" />
+ <BitField size="1" start="14" name="P14" />
+ <BitField size="1" start="15" name="P15" />
+ <BitField size="1" start="16" name="P16" />
+ <BitField size="1" start="17" name="P17" />
+ <BitField size="1" start="18" name="P18" />
+ <BitField size="1" start="19" name="P19" />
+ <BitField size="1" start="20" name="P20" />
+ <BitField size="1" start="21" name="P21" />
+ <BitField size="1" start="22" name="P22" />
+ <BitField size="1" start="23" name="P23" />
+ <BitField size="1" start="24" name="P24" />
+ <BitField size="1" start="25" name="P25" />
+ <BitField size="1" start="26" name="P26" />
+ <BitField size="1" start="27" name="P27" />
+ <BitField size="1" start="28" name="P28" />
+ <BitField size="1" start="29" name="P29" />
+ <BitField size="1" start="30" name="P30" />
+ <BitField size="1" start="31" name="P31" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFFF468" name="PIOA_PUSR" >
+ <BitField size="1" start="0" name="P0" />
+ <BitField size="1" start="1" name="P1" />
+ <BitField size="1" start="2" name="P2" />
+ <BitField size="1" start="3" name="P3" />
+ <BitField size="1" start="4" name="P4" />
+ <BitField size="1" start="5" name="P5" />
+ <BitField size="1" start="6" name="P6" />
+ <BitField size="1" start="7" name="P7" />
+ <BitField size="1" start="8" name="P8" />
+ <BitField size="1" start="9" name="P9" />
+ <BitField size="1" start="10" name="P10" />
+ <BitField size="1" start="11" name="P11" />
+ <BitField size="1" start="12" name="P12" />
+ <BitField size="1" start="13" name="P13" />
+ <BitField size="1" start="14" name="P14" />
+ <BitField size="1" start="15" name="P15" />
+ <BitField size="1" start="16" name="P16" />
+ <BitField size="1" start="17" name="P17" />
+ <BitField size="1" start="18" name="P18" />
+ <BitField size="1" start="19" name="P19" />
+ <BitField size="1" start="20" name="P20" />
+ <BitField size="1" start="21" name="P21" />
+ <BitField size="1" start="22" name="P22" />
+ <BitField size="1" start="23" name="P23" />
+ <BitField size="1" start="24" name="P24" />
+ <BitField size="1" start="25" name="P25" />
+ <BitField size="1" start="26" name="P26" />
+ <BitField size="1" start="27" name="P27" />
+ <BitField size="1" start="28" name="P28" />
+ <BitField size="1" start="29" name="P29" />
+ <BitField size="1" start="30" name="P30" />
+ <BitField size="1" start="31" name="P31" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFFF470" name="PIOA_ASR" >
+ <BitField size="1" start="0" name="P0" />
+ <BitField size="1" start="1" name="P1" />
+ <BitField size="1" start="2" name="P2" />
+ <BitField size="1" start="3" name="P3" />
+ <BitField size="1" start="4" name="P4" />
+ <BitField size="1" start="5" name="P5" />
+ <BitField size="1" start="6" name="P6" />
+ <BitField size="1" start="7" name="P7" />
+ <BitField size="1" start="8" name="P8" />
+ <BitField size="1" start="9" name="P9" />
+ <BitField size="1" start="10" name="P10" />
+ <BitField size="1" start="11" name="P11" />
+ <BitField size="1" start="12" name="P12" />
+ <BitField size="1" start="13" name="P13" />
+ <BitField size="1" start="14" name="P14" />
+ <BitField size="1" start="15" name="P15" />
+ <BitField size="1" start="16" name="P16" />
+ <BitField size="1" start="17" name="P17" />
+ <BitField size="1" start="18" name="P18" />
+ <BitField size="1" start="19" name="P19" />
+ <BitField size="1" start="20" name="P20" />
+ <BitField size="1" start="21" name="P21" />
+ <BitField size="1" start="22" name="P22" />
+ <BitField size="1" start="23" name="P23" />
+ <BitField size="1" start="24" name="P24" />
+ <BitField size="1" start="25" name="P25" />
+ <BitField size="1" start="26" name="P26" />
+ <BitField size="1" start="27" name="P27" />
+ <BitField size="1" start="28" name="P28" />
+ <BitField size="1" start="29" name="P29" />
+ <BitField size="1" start="30" name="P30" />
+ <BitField size="1" start="31" name="P31" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFFF474" name="PIOA_BSR" >
+ <BitField size="1" start="0" name="P0" />
+ <BitField size="1" start="1" name="P1" />
+ <BitField size="1" start="2" name="P2" />
+ <BitField size="1" start="3" name="P3" />
+ <BitField size="1" start="4" name="P4" />
+ <BitField size="1" start="5" name="P5" />
+ <BitField size="1" start="6" name="P6" />
+ <BitField size="1" start="7" name="P7" />
+ <BitField size="1" start="8" name="P8" />
+ <BitField size="1" start="9" name="P9" />
+ <BitField size="1" start="10" name="P10" />
+ <BitField size="1" start="11" name="P11" />
+ <BitField size="1" start="12" name="P12" />
+ <BitField size="1" start="13" name="P13" />
+ <BitField size="1" start="14" name="P14" />
+ <BitField size="1" start="15" name="P15" />
+ <BitField size="1" start="16" name="P16" />
+ <BitField size="1" start="17" name="P17" />
+ <BitField size="1" start="18" name="P18" />
+ <BitField size="1" start="19" name="P19" />
+ <BitField size="1" start="20" name="P20" />
+ <BitField size="1" start="21" name="P21" />
+ <BitField size="1" start="22" name="P22" />
+ <BitField size="1" start="23" name="P23" />
+ <BitField size="1" start="24" name="P24" />
+ <BitField size="1" start="25" name="P25" />
+ <BitField size="1" start="26" name="P26" />
+ <BitField size="1" start="27" name="P27" />
+ <BitField size="1" start="28" name="P28" />
+ <BitField size="1" start="29" name="P29" />
+ <BitField size="1" start="30" name="P30" />
+ <BitField size="1" start="31" name="P31" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFFF478" name="PIOA_ABSR" >
+ <BitField size="1" start="0" name="P0" />
+ <BitField size="1" start="1" name="P1" />
+ <BitField size="1" start="2" name="P2" />
+ <BitField size="1" start="3" name="P3" />
+ <BitField size="1" start="4" name="P4" />
+ <BitField size="1" start="5" name="P5" />
+ <BitField size="1" start="6" name="P6" />
+ <BitField size="1" start="7" name="P7" />
+ <BitField size="1" start="8" name="P8" />
+ <BitField size="1" start="9" name="P9" />
+ <BitField size="1" start="10" name="P10" />
+ <BitField size="1" start="11" name="P11" />
+ <BitField size="1" start="12" name="P12" />
+ <BitField size="1" start="13" name="P13" />
+ <BitField size="1" start="14" name="P14" />
+ <BitField size="1" start="15" name="P15" />
+ <BitField size="1" start="16" name="P16" />
+ <BitField size="1" start="17" name="P17" />
+ <BitField size="1" start="18" name="P18" />
+ <BitField size="1" start="19" name="P19" />
+ <BitField size="1" start="20" name="P20" />
+ <BitField size="1" start="21" name="P21" />
+ <BitField size="1" start="22" name="P22" />
+ <BitField size="1" start="23" name="P23" />
+ <BitField size="1" start="24" name="P24" />
+ <BitField size="1" start="25" name="P25" />
+ <BitField size="1" start="26" name="P26" />
+ <BitField size="1" start="27" name="P27" />
+ <BitField size="1" start="28" name="P28" />
+ <BitField size="1" start="29" name="P29" />
+ <BitField size="1" start="30" name="P30" />
+ <BitField size="1" start="31" name="P31" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFFF4A0" name="PIOA_OWER" >
+ <BitField size="1" start="0" name="P0" />
+ <BitField size="1" start="1" name="P1" />
+ <BitField size="1" start="2" name="P2" />
+ <BitField size="1" start="3" name="P3" />
+ <BitField size="1" start="4" name="P4" />
+ <BitField size="1" start="5" name="P5" />
+ <BitField size="1" start="6" name="P6" />
+ <BitField size="1" start="7" name="P7" />
+ <BitField size="1" start="8" name="P8" />
+ <BitField size="1" start="9" name="P9" />
+ <BitField size="1" start="10" name="P10" />
+ <BitField size="1" start="11" name="P11" />
+ <BitField size="1" start="12" name="P12" />
+ <BitField size="1" start="13" name="P13" />
+ <BitField size="1" start="14" name="P14" />
+ <BitField size="1" start="15" name="P15" />
+ <BitField size="1" start="16" name="P16" />
+ <BitField size="1" start="17" name="P17" />
+ <BitField size="1" start="18" name="P18" />
+ <BitField size="1" start="19" name="P19" />
+ <BitField size="1" start="20" name="P20" />
+ <BitField size="1" start="21" name="P21" />
+ <BitField size="1" start="22" name="P22" />
+ <BitField size="1" start="23" name="P23" />
+ <BitField size="1" start="24" name="P24" />
+ <BitField size="1" start="25" name="P25" />
+ <BitField size="1" start="26" name="P26" />
+ <BitField size="1" start="27" name="P27" />
+ <BitField size="1" start="28" name="P28" />
+ <BitField size="1" start="29" name="P29" />
+ <BitField size="1" start="30" name="P30" />
+ <BitField size="1" start="31" name="P31" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFFF4A4" name="PIOA_OWDR" >
+ <BitField size="1" start="0" name="P0" />
+ <BitField size="1" start="1" name="P1" />
+ <BitField size="1" start="2" name="P2" />
+ <BitField size="1" start="3" name="P3" />
+ <BitField size="1" start="4" name="P4" />
+ <BitField size="1" start="5" name="P5" />
+ <BitField size="1" start="6" name="P6" />
+ <BitField size="1" start="7" name="P7" />
+ <BitField size="1" start="8" name="P8" />
+ <BitField size="1" start="9" name="P9" />
+ <BitField size="1" start="10" name="P10" />
+ <BitField size="1" start="11" name="P11" />
+ <BitField size="1" start="12" name="P12" />
+ <BitField size="1" start="13" name="P13" />
+ <BitField size="1" start="14" name="P14" />
+ <BitField size="1" start="15" name="P15" />
+ <BitField size="1" start="16" name="P16" />
+ <BitField size="1" start="17" name="P17" />
+ <BitField size="1" start="18" name="P18" />
+ <BitField size="1" start="19" name="P19" />
+ <BitField size="1" start="20" name="P20" />
+ <BitField size="1" start="21" name="P21" />
+ <BitField size="1" start="22" name="P22" />
+ <BitField size="1" start="23" name="P23" />
+ <BitField size="1" start="24" name="P24" />
+ <BitField size="1" start="25" name="P25" />
+ <BitField size="1" start="26" name="P26" />
+ <BitField size="1" start="27" name="P27" />
+ <BitField size="1" start="28" name="P28" />
+ <BitField size="1" start="29" name="P29" />
+ <BitField size="1" start="30" name="P30" />
+ <BitField size="1" start="31" name="P31" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFFF4A8" name="PIOA_OWSR" >
+ <BitField size="1" start="0" name="P0" />
+ <BitField size="1" start="1" name="P1" />
+ <BitField size="1" start="2" name="P2" />
+ <BitField size="1" start="3" name="P3" />
+ <BitField size="1" start="4" name="P4" />
+ <BitField size="1" start="5" name="P5" />
+ <BitField size="1" start="6" name="P6" />
+ <BitField size="1" start="7" name="P7" />
+ <BitField size="1" start="8" name="P8" />
+ <BitField size="1" start="9" name="P9" />
+ <BitField size="1" start="10" name="P10" />
+ <BitField size="1" start="11" name="P11" />
+ <BitField size="1" start="12" name="P12" />
+ <BitField size="1" start="13" name="P13" />
+ <BitField size="1" start="14" name="P14" />
+ <BitField size="1" start="15" name="P15" />
+ <BitField size="1" start="16" name="P16" />
+ <BitField size="1" start="17" name="P17" />
+ <BitField size="1" start="18" name="P18" />
+ <BitField size="1" start="19" name="P19" />
+ <BitField size="1" start="20" name="P20" />
+ <BitField size="1" start="21" name="P21" />
+ <BitField size="1" start="22" name="P22" />
+ <BitField size="1" start="23" name="P23" />
+ <BitField size="1" start="24" name="P24" />
+ <BitField size="1" start="25" name="P25" />
+ <BitField size="1" start="26" name="P26" />
+ <BitField size="1" start="27" name="P27" />
+ <BitField size="1" start="28" name="P28" />
+ <BitField size="1" start="29" name="P29" />
+ <BitField size="1" start="30" name="P30" />
+ <BitField size="1" start="31" name="P31" />
+ </Register>
+ </RegisterGroup>
+ <RegisterGroup start="0xFFFFFC00" name="PMC" >
+ <Register size="4" access="WriteOnly" start="0xFFFFFC00" name="PMC_SCER" >
+ <BitField size="1" start="0" name="PCK" />
+ <BitField size="1" start="7" name="UDP" />
+ <BitField size="1" start="8" name="PCK0" />
+ <BitField size="1" start="9" name="PCK1" />
+ <BitField size="1" start="10" name="PCK2" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFFFC04" name="PMC_SCDR" >
+ <BitField size="1" start="0" name="PCK" />
+ <BitField size="1" start="7" name="UDP" />
+ <BitField size="1" start="8" name="PCK0" />
+ <BitField size="1" start="9" name="PCK1" />
+ <BitField size="1" start="10" name="PCK2" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFFFC08" name="PMC_SCSR" >
+ <BitField size="1" start="0" name="PCK" />
+ <BitField size="1" start="7" name="UDP" />
+ <BitField size="1" start="8" name="PCK0" />
+ <BitField size="1" start="9" name="PCK1" />
+ <BitField size="1" start="10" name="PCK2" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFFFC10" name="PMC_PCER" >
+ <BitField size="1" start="2" name="PID2" />
+ <BitField size="1" start="3" name="PID3" />
+ <BitField size="1" start="4" name="PID4" />
+ <BitField size="1" start="5" name="PID5" />
+ <BitField size="1" start="6" name="PID6" />
+ <BitField size="1" start="7" name="PID7" />
+ <BitField size="1" start="8" name="PID8" />
+ <BitField size="1" start="9" name="PID9" />
+ <BitField size="1" start="10" name="PID10" />
+ <BitField size="1" start="11" name="PID11" />
+ <BitField size="1" start="12" name="PID12" />
+ <BitField size="1" start="13" name="PID13" />
+ <BitField size="1" start="14" name="PID14" />
+ <BitField size="1" start="15" name="PID15" />
+ <BitField size="1" start="16" name="PID16" />
+ <BitField size="1" start="17" name="PID17" />
+ <BitField size="1" start="18" name="PID18" />
+ <BitField size="1" start="19" name="PID19" />
+ <BitField size="1" start="20" name="PID20" />
+ <BitField size="1" start="21" name="PID21" />
+ <BitField size="1" start="22" name="PID22" />
+ <BitField size="1" start="23" name="PID23" />
+ <BitField size="1" start="24" name="PID24" />
+ <BitField size="1" start="25" name="PID25" />
+ <BitField size="1" start="26" name="PID26" />
+ <BitField size="1" start="27" name="PID27" />
+ <BitField size="1" start="28" name="PID28" />
+ <BitField size="1" start="29" name="PID29" />
+ <BitField size="1" start="30" name="PID30" />
+ <BitField size="1" start="31" name="PID31" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFFFC14" name="PMC_PCDR" >
+ <BitField size="1" start="2" name="PID2" />
+ <BitField size="1" start="3" name="PID3" />
+ <BitField size="1" start="4" name="PID4" />
+ <BitField size="1" start="5" name="PID5" />
+ <BitField size="1" start="6" name="PID6" />
+ <BitField size="1" start="7" name="PID7" />
+ <BitField size="1" start="8" name="PID8" />
+ <BitField size="1" start="9" name="PID9" />
+ <BitField size="1" start="10" name="PID10" />
+ <BitField size="1" start="11" name="PID11" />
+ <BitField size="1" start="12" name="PID12" />
+ <BitField size="1" start="13" name="PID13" />
+ <BitField size="1" start="14" name="PID14" />
+ <BitField size="1" start="15" name="PID15" />
+ <BitField size="1" start="16" name="PID16" />
+ <BitField size="1" start="17" name="PID17" />
+ <BitField size="1" start="18" name="PID18" />
+ <BitField size="1" start="19" name="PID19" />
+ <BitField size="1" start="20" name="PID20" />
+ <BitField size="1" start="21" name="PID21" />
+ <BitField size="1" start="22" name="PID22" />
+ <BitField size="1" start="23" name="PID23" />
+ <BitField size="1" start="24" name="PID24" />
+ <BitField size="1" start="25" name="PID25" />
+ <BitField size="1" start="26" name="PID26" />
+ <BitField size="1" start="27" name="PID27" />
+ <BitField size="1" start="28" name="PID28" />
+ <BitField size="1" start="29" name="PID29" />
+ <BitField size="1" start="30" name="PID30" />
+ <BitField size="1" start="31" name="PID31" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFFFC18" name="PMC_PCSR" >
+ <BitField size="1" start="2" name="PID2" />
+ <BitField size="1" start="3" name="PID3" />
+ <BitField size="1" start="4" name="PID4" />
+ <BitField size="1" start="5" name="PID5" />
+ <BitField size="1" start="6" name="PID6" />
+ <BitField size="1" start="7" name="PID7" />
+ <BitField size="1" start="8" name="PID8" />
+ <BitField size="1" start="9" name="PID9" />
+ <BitField size="1" start="10" name="PID10" />
+ <BitField size="1" start="11" name="PID11" />
+ <BitField size="1" start="12" name="PID12" />
+ <BitField size="1" start="13" name="PID13" />
+ <BitField size="1" start="14" name="PID14" />
+ <BitField size="1" start="15" name="PID15" />
+ <BitField size="1" start="16" name="PID16" />
+ <BitField size="1" start="17" name="PID17" />
+ <BitField size="1" start="18" name="PID18" />
+ <BitField size="1" start="19" name="PID19" />
+ <BitField size="1" start="20" name="PID20" />
+ <BitField size="1" start="21" name="PID21" />
+ <BitField size="1" start="22" name="PID22" />
+ <BitField size="1" start="23" name="PID23" />
+ <BitField size="1" start="24" name="PID24" />
+ <BitField size="1" start="25" name="PID25" />
+ <BitField size="1" start="26" name="PID26" />
+ <BitField size="1" start="27" name="PID27" />
+ <BitField size="1" start="28" name="PID28" />
+ <BitField size="1" start="29" name="PID29" />
+ <BitField size="1" start="30" name="PID30" />
+ <BitField size="1" start="31" name="PID31" />
+ </Register>
+ <Register size="4" start="0xFFFFFC20" name="CKGR_MOR" >
+ <BitField size="1" start="0" name="MOSCEN" />
+ <BitField size="1" start="1" name="OSCBYPASS" />
+ <BitField size="8" start="8" name="OSCOUNT" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFFFC24" name="CKGR_MCFR" >
+ <BitField size="16" start="0" name="MAINF" />
+ <BitField size="1" start="16" name="MAINRDY" />
+ </Register>
+ <Register size="4" start="0xFFFFFC2C" name="CKGR_PLLR" >
+ <BitField size="8" start="0" name="DIV" />
+ <BitField size="6" start="8" name="PLLCOUNT" />
+ <BitField size="2" start="14" name="OUT" />
+ <BitField size="11" start="16" name="MUL" />
+ <BitField size="2" start="28" name="USBDIV" />
+ </Register>
+ <Register size="4" start="0xFFFFFC30" name="PMC_MCKR" >
+ <BitField size="2" start="0" name="CSS" />
+ <BitField size="3" start="2" name="PRES" />
+ </Register>
+ <Register size="4" start="0xFFFFFC40" name="PMC_PCK0" >
+ <BitField size="2" start="0" name="CSS" />
+ <BitField size="3" start="2" name="PRES" />
+ </Register>
+ <Register size="4" start="0xFFFFFC44" name="PMC_PCK1" >
+ <BitField size="2" start="0" name="CSS" />
+ <BitField size="3" start="2" name="PRES" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFFFC60" name="PMC_IER" >
+ <BitField size="1" start="0" name="MOSCS" />
+ <BitField size="1" start="2" name="LOCK" />
+ <BitField size="1" start="3" name="MCKRDY" />
+ <BitField size="1" start="8" name="PCKRDY0" />
+ <BitField size="1" start="9" name="PCKRDY1" />
+ <BitField size="1" start="10" name="PCKRDY2" />
+ <BitField size="1" start="11" name="PCKRDY3" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFFFC64" name="PMC_IDR" >
+ <BitField size="1" start="0" name="MOSCS" />
+ <BitField size="1" start="2" name="LOCK" />
+ <BitField size="1" start="3" name="MCKRDY" />
+ <BitField size="1" start="8" name="PCKRDY0" />
+ <BitField size="1" start="9" name="PCKRDY1" />
+ <BitField size="1" start="10" name="PCKRDY2" />
+ <BitField size="1" start="11" name="PCKRDY3" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFFFC68" name="PMC_SR" >
+ <BitField size="1" start="0" name="MOSCS" />
+ <BitField size="1" start="2" name="LOCK" />
+ <BitField size="1" start="3" name="MCKRDY" />
+ <BitField size="1" start="8" name="PCKRDY0" />
+ <BitField size="1" start="9" name="PCKRDY1" />
+ <BitField size="1" start="10" name="PCKRDY2" />
+ <BitField size="1" start="11" name="PCKRDY3" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFFFC6C" name="PMC_IMR" >
+ <BitField size="1" start="0" name="MOSCS" />
+ <BitField size="1" start="2" name="LOCK" />
+ <BitField size="1" start="3" name="MCKRDY" />
+ <BitField size="1" start="8" name="PCKRDY0" />
+ <BitField size="1" start="9" name="PCKRDY1" />
+ <BitField size="1" start="10" name="PCKRDY2" />
+ <BitField size="1" start="11" name="PCKRDY3" />
+ </Register>
+ </RegisterGroup>
+ <RegisterGroup start="0xFFFFFD00" name="RSTC" >
+ <Register size="4" access="WriteOnly" start="0xFFFFFD00" name="RSTC_CR" >
+ <BitField size="1" start="0" name="PROCRST" />
+ <BitField size="1" start="2" name="PERRST" />
+ <BitField size="1" start="3" name="EXTRST" />
+ <BitField size="8" start="24" name="KEY" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFFFD04" name="RSTC_SR" >
+ <BitField size="1" start="0" name="URSTS" />
+ <BitField size="1" start="1" name="BODSTS" />
+ <BitField size="3" start="8" name="RSTTYP" />
+ <BitField size="1" start="16" name="NRSTL" />
+ <BitField size="1" start="17" name="SRCMP" />
+ </Register>
+ <Register size="4" start="0xFFFFFD08" name="RSTC_MR" >
+ <BitField size="1" start="0" name="URSTEN" />
+ <BitField size="1" start="4" name="URSTIEN" />
+ <BitField size="4" start="8" name="ERSTL" />
+ <BitField size="1" start="16" name="BODIEN" />
+ <BitField size="8" start="24" name="KEY" />
+ </Register>
+ </RegisterGroup>
+ <RegisterGroup start="0xFFFFFD20" name="RTT" >
+ <Register size="4" start="0xFFFFFD20" name="RTT_MR" >
+ <BitField size="16" start="0" name="RTPRES" />
+ <BitField size="1" start="16" name="ALMIEN" />
+ <BitField size="1" start="17" name="RTTINCIEN" />
+ <BitField size="1" start="18" name="RTTRST" />
+ </Register>
+ <Register size="4" start="0xFFFFFD24" name="RTT_AR" />
+ <Register size="4" access="ReadOnly" start="0xFFFFFD28" name="RTT_VR" />
+ <Register size="4" access="ReadOnly" start="0xFFFFFD2C" name="RTT_SR" >
+ <BitField size="1" start="0" name="ALMS" />
+ <BitField size="1" start="1" name="RTTINC" />
+ </Register>
+ </RegisterGroup>
+ <RegisterGroup start="0xFFFFFD30" name="PIT" >
+ <Register size="4" start="0xFFFFFD30" name="PIT_MR" >
+ <BitField size="24" start="0" name="PIV" />
+ <BitField size="1" start="24" name="PITEN" />
+ <BitField size="1" start="25" name="PITIEN" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFFFD34" name="PIT_SR" />
+ <Register size="4" access="ReadOnly" start="0xFFFFFD38" name="PIT_PIVR" >
+ <BitField size="20" start="0" name="CPIV" />
+ <BitField size="12" start="20" name="PICNT" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFFFD3C" name="PIT_PIIR" >
+ <BitField size="20" start="0" name="CPIV" />
+ <BitField size="12" start="20" name="PICNT" />
+ </Register>
+ </RegisterGroup>
+ <RegisterGroup start="0xFFFFFD40" name="WDT" >
+ <Register size="4" access="WriteOnly" start="0xFFFFFD40" name="WDT_CR" >
+ <BitField size="1" start="0" name="WDRSTT" />
+ <BitField size="8" start="24" name="KEY" />
+ </Register>
+ <Register size="4" start="0xFFFFFD44" name="WDT_MR" >
+ <BitField size="12" start="0" name="WDV" />
+ <BitField size="1" start="12" name="WDFIEN" />
+ <BitField size="1" start="13" name="WDRSTEN" />
+ <BitField size="1" start="14" name="WDRPROC" />
+ <BitField size="1" start="15" name="WDDIS" />
+ <BitField size="12" start="16" name="WDD" />
+ <BitField size="1" start="28" name="WDDBGHLT" />
+ <BitField size="1" start="29" name="WDIDLEHLT" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFFFD48" name="WDT_SR" >
+ <BitField size="1" start="0" name="WDUNF" />
+ <BitField size="1" start="1" name="WDERR" />
+ </Register>
+ </RegisterGroup>
+ <RegisterGroup start="0xFFFFFD60" name="VREG" >
+ <Register size="4" start="0xFFFFFD60" name="WREG_MR" />
+ </RegisterGroup>
+ <RegisterGroup start="0xFFFFFF00" name="MC" >
+ <Register size="4" access="WriteOnly" start="0xFFFFFF00" name="MC_RCR" />
+ <Register size="4" access="ReadOnly" start="0xFFFFFF04" name="MC_ASR" >
+ <BitField size="1" start="0" name="UNDADD" />
+ <BitField size="1" start="1" name="MISADD" />
+ <BitField size="2" start="8" name="ABTSZ" />
+ <BitField size="2" start="10" name="ABTTYP" />
+ <BitField size="1" start="16" name="MST0" />
+ <BitField size="1" start="17" name="MST1" />
+ <BitField size="1" start="24" name="SVMST0" />
+ <BitField size="1" start="25" name="SVMST1" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFFFF08" name="MC_AASR" />
+ <Register size="4" start="0xFFFFFF60" name="MC_FMR" >
+ <BitField size="1" start="0" name="FRDY" />
+ <BitField size="1" start="2" name="LOCKE" />
+ <BitField size="1" start="3" name="PROGE" />
+ <BitField size="1" start="7" name="NEBP" />
+ <BitField size="2" start="8" name="FWS" />
+ <BitField size="16" start="16" name="FMCN" />
+ </Register>
+ <Register size="4" access="WriteOnly" start="0xFFFFFF64" name="MC_FCR" >
+ <BitField size="4" start="0" name="FCMD" />
+ <BitField size="10" start="8" name="PAGEN" />
+ <BitField size="8" start="24" name="KEY" />
+ </Register>
+ <Register size="4" access="ReadOnly" start="0xFFFFFF68" name="MC_FSR" >
+ <BitField size="1" start="0" name="FRDY" />
+ <BitField size="1" start="2" name="LOCKE" />
+ <BitField size="1" start="3" name="PROGE" />
+ <BitField size="1" start="4" name="SECURITY" />
+ <BitField size="1" start="8" name="GPNVM0" />
+ <BitField size="1" start="9" name="GPNVM1" />
+ <BitField size="1" start="16" name="LOCKS0" />
+ <BitField size="1" start="17" name="LOCKS1" />
+ <BitField size="1" start="18" name="LOCKS2" />
+ <BitField size="1" start="19" name="LOCKS3" />
+ <BitField size="1" start="20" name="LOCKS4" />
+ <BitField size="1" start="21" name="LOCKS5" />
+ <BitField size="1" start="22" name="LOCKS6" />
+ <BitField size="1" start="23" name="LOCKS7" />
+ <BitField size="1" start="24" name="LOCKS8" />
+ <BitField size="1" start="25" name="LOCKS9" />
+ <BitField size="1" start="26" name="LOCKS10" />
+ <BitField size="1" start="27" name="LOCKS11" />
+ <BitField size="1" start="28" name="LOCKS12" />
+ <BitField size="1" start="29" name="LOCKS13" />
+ <BitField size="1" start="30" name="LOCKS14" />
+ <BitField size="1" start="31" name="LOCKS15" />
+ </Register>
+ </RegisterGroup>
+ </MemorySegment>
+</Root>
--- /dev/null
+/*****************************************************************************\r
+ Exception handlers and startup code for ATMEL AT91SAM7.\r
+\r
+ Copyright (c) 2004 Rowley Associates Limited.\r
+\r
+ This file may be distributed under the terms of the License Agreement\r
+ provided with this software. \r
+ \r
+ THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE\r
+ WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\r
+ *****************************************************************************/\r
+\r
+#define REG_BASE 0xFFFFF000\r
+#define CKGR_MOR_OFFSET 0xC20\r
+#define CKGR_PLLR_OFFSET 0xC2C\r
+#define PMC_MCKR_OFFSET 0xC30\r
+#define PMC_SR_OFFSET 0xC68\r
+#define WDT_MR_OFFSET 0xD44\r
+#define MC_RCR_OFFSET 0xF00\r
+#define MC_FMR_OFFSET 0xF60\r
+\r
+#define CKGR_MOR_MOSCEN (1 << 0)\r
+#define CKGR_MOR_OSCBYPASS (1 << 1)\r
+#define CKGR_MOR_OSCOUNT_BIT_OFFSET (8)\r
+\r
+#define CKGR_PLLR_DIV_BIT_OFFSET (0)\r
+#define CKGR_PLLR_PLLCOUNT_BIT_OFFSET (8)\r
+#define CKGR_PLLR_OUT_BIT_OFFSET (14)\r
+#define CKGR_PLLR_MUL_BIT_OFFSET (16)\r
+#define CKGR_PLLR_USBDIV_BIT_OFFSET (28)\r
+\r
+#define PMC_MCKR_CSS_MAIN_CLOCK (0x1)\r
+#define PMC_MCKR_CSS_PLL_CLOCK (0x3)\r
+#define PMC_MCKR_PRES_CLK (0)\r
+#define PMC_MCKR_PRES_CLK_2 (1 << 2)\r
+#define PMC_MCKR_PRES_CLK_4 (2 << 2)\r
+#define PMC_MCKR_PRES_CLK_8 (3 << 2)\r
+#define PMC_MCKR_PRES_CLK_16 (4 << 2)\r
+#define PMC_MCKR_PRES_CLK_32 (5 << 2)\r
+#define PMC_MCKR_PRES_CLK_64 (6 << 2)\r
+\r
+#define PMC_SR_MOSCS (1 << 0)\r
+#define PMC_SR_LOCK (1 << 2)\r
+#define PMC_SR_MCKRDY (1 << 3)\r
+#define PMC_SR_PCKRDY0 (1 << 8)\r
+#define PMC_SR_PCKRDY1 (1 << 9)\r
+#define PMC_SR_PCKRDY2 (1 << 10)\r
+\r
+#define MC_RCR_RCB (1 << 0)\r
+\r
+#define MC_FMR_FWS_0FWS (0)\r
+#define MC_FMR_FWS_1FWS (1 << 8)\r
+#define MC_FMR_FWS_2FWS (2 << 8)\r
+#define MC_FMR_FWS_3FWS (3 << 8)\r
+#define MC_FMR_FMCN_BIT_OFFSET 16\r
+\r
+#define WDT_MR_WDDIS (1 << 15)\r
+\r
+ .section .vectors, "ax"\r
+ .code 32\r
+ .align 0\r
+ \r
+/*****************************************************************************\r
+ Exception Vectors\r
+ *****************************************************************************/\r
+_vectors:\r
+ ldr pc, [pc, #reset_handler_address - . - 8] /* reset */\r
+ ldr pc, [pc, #undef_handler_address - . - 8] /* undefined instruction */\r
+ ldr pc, [pc, #swi_handler_address - . - 8] /* swi handler */\r
+ ldr pc, [pc, #pabort_handler_address - . - 8] /* abort prefetch */\r
+ ldr pc, [pc, #dabort_handler_address - . - 8] /* abort data */\r
+ nop\r
+ ldr pc, [PC, #-0xF20] /* irq */\r
+ ldr pc, [pc, #fiq_handler_address - . - 8] /* fiq */\r
+\r
+reset_handler_address:\r
+ .word reset_handler\r
+undef_handler_address:\r
+ .word undef_handler\r
+swi_handler_address:\r
+ .word swi_handler\r
+pabort_handler_address:\r
+ .word pabort_handler\r
+dabort_handler_address:\r
+ .word dabort_handler\r
+irq_handler_address:\r
+ .word irq_handler\r
+fiq_handler_address:\r
+ .word fiq_handler\r
+\r
+ .section .init, "ax"\r
+ .code 32\r
+ .align 0\r
+\r
+/******************************************************************************\r
+ Reset handler\r
+ ******************************************************************************/\r
+reset_handler:\r
+\r
+\r
+ ldr r10, =REG_BASE\r
+\r
+ /* Set up FLASH wait state */\r
+ ldr r0, =(50 << MC_FMR_FMCN_BIT_OFFSET) | MC_FMR_FWS_1FWS\r
+ str r0, [r10, #MC_FMR_OFFSET]\r
+\r
+ /* Disable Watchdog */\r
+ ldr r0, =WDT_MR_WDDIS\r
+ str r0, [r10, #WDT_MR_OFFSET]\r
+\r
+ /* Enable the main oscillator */\r
+ ldr r0, =(6 << CKGR_MOR_OSCOUNT_BIT_OFFSET) | CKGR_MOR_MOSCEN\r
+ str r0, [r10, #CKGR_MOR_OFFSET]\r
+ \r
+1:/* Wait for main oscillator to stabilize */\r
+ ldr r0, [r10, #PMC_SR_OFFSET]\r
+ tst r0, #PMC_SR_MOSCS\r
+ beq 1b\r
+\r
+ /* Set up the PLL */\r
+ ldr r0, =(5 << CKGR_PLLR_DIV_BIT_OFFSET) | (28 << CKGR_PLLR_PLLCOUNT_BIT_OFFSET) | (25 << CKGR_PLLR_MUL_BIT_OFFSET)\r
+ str r0, [r10, #CKGR_PLLR_OFFSET]\r
+ \r
+1:/* Wait for PLL to lock */\r
+ ldr r0, [r10, #PMC_SR_OFFSET]\r
+ tst r0, #PMC_SR_LOCK\r
+ beq 1b\r
+\r
+ /* Select PLL as clock source */\r
+ ldr r0, =(PMC_MCKR_CSS_PLL_CLOCK | PMC_MCKR_PRES_CLK_2)\r
+ str r0, [r10, #PMC_MCKR_OFFSET]\r
+ \r
+#ifdef __FLASH_BUILD\r
+ /* Copy exception vectors into Internal SRAM */\r
+ mov r8, #0x00200000\r
+ ldr r9, =_vectors\r
+ ldmia r9!, {r0-r7}\r
+ stmia r8!, {r0-r7}\r
+ ldmia r9!, {r0-r6}\r
+ stmia r8!, {r0-r6}\r
+\r
+ /* Remap Internal SRAM to 0x00000000 */\r
+ ldr r0, =MC_RCR_RCB\r
+ strb r0, [r10, #MC_RCR_OFFSET]\r
+#endif\r
+\r
+\r
+ /* Jump to the default C runtime startup code. */\r
+ b _start\r
+\r
+/******************************************************************************\r
+ Default exception handlers\r
+ (These are declared weak symbols so they can be redefined in user code)\r
+ ******************************************************************************/\r
+undef_handler:\r
+ b undef_handler\r
+ \r
+swi_handler:\r
+ b swi_handler\r
+ \r
+pabort_handler:\r
+ b pabort_handler\r
+ \r
+dabort_handler:\r
+ b dabort_handler\r
+ \r
+irq_handler:\r
+ b irq_handler\r
+ \r
+fiq_handler:\r
+ b fiq_handler\r
+\r
+ .weak undef_handler, swi_handler, pabort_handler, dabort_handler, irq_handler, fiq_handler\r
--- /dev/null
+/******************************************************************************\r
+ Target Script for ATMEL AT91SAM7.\r
+\r
+ Copyright (c) 2004 Rowley Associates Limited.\r
+\r
+ This file may be distributed under the terms of the License Agreement\r
+ provided with this software.\r
+\r
+ THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE\r
+ WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\r
+ ******************************************************************************/\r
+\r
+function Reset()\r
+{\r
+ /* Reset and stop target */\r
+ TargetInterface.pokeWord(0xFFFFFD00, 0xA500000D); // RSTC_CR\r
+ TargetInterface.waitForDebugState(1000);\r
+ /* Configure Clock */\r
+ TargetInterface.pokeWord(0xFFFFFC20, 0x00000601); // CKGR_MOR\r
+ TargetInterface.delay(10);\r
+ TargetInterface.pokeWord(0xFFFFFC2C, 0x00191C05); // CKGR_PLLR\r
+ TargetInterface.delay(10);\r
+ TargetInterface.pokeWord(0xFFFFFC30, 0x00000007); // CKGR_MCKR\r
+ TargetInterface.delay(10);\r
+}\r
+\r
+function RAMReset()\r
+{\r
+ Reset();\r
+ /* Remap SRAM to 0x00000000 */\r
+ TargetInterface.pokeWord(0xFFFFFF00, 1); // MC_RCR \r
+}\r
+\r
+function FLASHReset()\r
+{\r
+ Reset();\r
+\r
+// Mask All interrupt pAic->AIC_IDCR = 0xFFFFFFFF;\r
+ \r
+ TargetInterface.pokeWord(0xffffffff,0xFFFFF124);\r
+ TargetInterface.pokeWord(0xffffffff,0xFFFFF128);\r
+// disable peripheral clock Peripheral Clock Disable Register\r
+ TargetInterface.pokeWord(0xffffffff,0xFFFFFC14);\r
+\r
+// #define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register\r
+// #define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register\r
+// #define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register\r
+ TargetInterface.peekWord(0xFFFA0020);\r
+ TargetInterface.peekWord(0xFFFA0060);\r
+ TargetInterface.peekWord(0xFFFA00A0);\r
+\r
+// for (__mac_i=0;__mac_i < 8; __mac_i++)\r
+// {\r
+ // AT91C_BASE_AIC->AIC_EOICR\r
+// __mac_pt = TargetInterface.peekWord(0xFFFFF130);\r
+ \r
+// }\r
+// __message "------------------------------- AIC 2 INIT ---------------------------------------------"; \r
+\r
+}\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+ Implements a simplistic WEB server. Every time a connection is made and\r
+ data is received a dynamic page that shows the current TCP/IP statistics\r
+ is generated and returned. The connection is then closed.\r
+\r
+ This file was adapted from a FreeRTOS lwIP slip demo supplied by a third\r
+ party.\r
+*/\r
+\r
+/*\r
+ Changes from V3.2.2\r
+\r
+ + Changed the page returned by the lwIP WEB server demo to display the \r
+ task status table rather than the TCP/IP statistics.\r
+*/\r
+\r
+\r
+/* Standard includes. */\r
+#include <stdio.h>\r
+#include <string.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "semphr.h"\r
+\r
+/* Demo includes. */\r
+#include "BasicWEB.h"\r
+#include "SAM7_EMAC.h"\r
+\r
+/* lwIP includes. */\r
+#include "lwip/api.h" \r
+#include "lwip/tcpip.h"\r
+#include "lwip/memp.h" \r
+#include "lwip/stats.h"\r
+#include "netif/loopif.h"\r
+\r
+/* The size of the buffer in which the dynamic WEB page is created. */\r
+#define webMAX_PAGE_SIZE 2048\r
+\r
+/* Standard GET response. */\r
+#define webHTTP_OK "HTTP/1.0 200 OK\r\nContent-type: text/html\r\n\r\n"\r
+\r
+/* The port on which we listen. */\r
+#define webHTTP_PORT ( 80 )\r
+\r
+/* Delay on close error. */\r
+#define webSHORT_DELAY ( 10 )\r
+\r
+/* Format of the dynamic page that is returned on each connection. */\r
+#define webHTML_START \\r
+"<html>\\r
+<head>\\r
+</head>\\r
+<BODY onLoad=\"window.setTimeout("location.href='index.html'",1000)\"bgcolor=\"#CCCCff\">\\r
+\r\nPage Hits = "\r
+\r
+#define webHTML_END \\r
+"\r\n</pre>\\r
+\r\n</BODY>\\r
+</html>"\r
+\r
+/*------------------------------------------------------------*/\r
+\r
+/* \r
+ * Process an incoming connection on port 80.\r
+ *\r
+ * This simply checks to see if the incoming data contains a GET request, and\r
+ * if so sends back a single dynamically created page. The connection is then\r
+ * closed. A more complete implementation could create a task for each \r
+ * connection. \r
+ */\r
+static void vProcessConnection( struct netconn *pxNetCon );\r
+\r
+/*------------------------------------------------------------*/\r
+\r
+static void vProcessConnection( struct netconn *pxNetCon )\r
+{\r
+static portCHAR cDynamicPage[ webMAX_PAGE_SIZE ], cPageHits[ 11 ];\r
+struct netbuf *pxRxBuffer;\r
+portCHAR *pcRxString;\r
+unsigned portSHORT usLength;\r
+static unsigned portLONG ulPageHits = 0;\r
+\r
+ /* We expect to immediately get data. */\r
+ pxRxBuffer = netconn_recv( pxNetCon );\r
+\r
+ if( pxRxBuffer != NULL )\r
+ {\r
+ /* Where is the data? */\r
+ netbuf_data( pxRxBuffer, ( void * ) &pcRxString, &usLength ); \r
+ \r
+ /* Is this a GET? We don't handle anything else. */\r
+ if( !strncmp( pcRxString, "GET", 3 ) )\r
+ {\r
+ pcRxString = cDynamicPage;\r
+\r
+ /* Update the hit count. */\r
+ ulPageHits++;\r
+ sprintf( cPageHits, "%lu", ulPageHits );\r
+\r
+ /* Write out the HTTP OK header. */\r
+ netconn_write(pxNetCon, webHTTP_OK, (u16_t)strlen( webHTTP_OK ), NETCONN_COPY );\r
+\r
+ /* Generate the dynamic page...\r
+\r
+ ... First the page header. */\r
+ strcpy( cDynamicPage, webHTML_START );\r
+ /* ... Then the hit count... */\r
+ strcat( cDynamicPage, cPageHits );\r
+ strcat( cDynamicPage, "<p><pre>Task State Priority Stack #<br>************************************************<br>" );\r
+ /* ... Then the list of tasks and their status... */\r
+ vTaskList( ( signed portCHAR * ) cDynamicPage + strlen( cDynamicPage ) ); \r
+ /* ... Finally the page footer. */\r
+ strcat( cDynamicPage, webHTML_END );\r
+\r
+ /* Write out the dynamically generated page. */\r
+ netconn_write(pxNetCon, cDynamicPage, (u16_t)strlen( cDynamicPage ), NETCONN_COPY );\r
+ }\r
+ \r
+ netbuf_delete( pxRxBuffer );\r
+ }\r
+\r
+ netconn_close( pxNetCon );\r
+}\r
+/*------------------------------------------------------------*/\r
+\r
+void vlwIPInit( void )\r
+{\r
+ /* Initialize lwIP and its interface layer. */\r
+ sys_init();\r
+ mem_init(); \r
+ memp_init();\r
+ pbuf_init(); \r
+ netif_init();\r
+ ip_init();\r
+ tcpip_init( NULL, NULL );\r
+}\r
+/*------------------------------------------------------------*/\r
+\r
+void vBasicWEBServer( void *pvParameters )\r
+{\r
+struct netconn *pxHTTPListener, *pxNewConnection;\r
+struct ip_addr xIpAddr, xNetMast, xGateway;\r
+extern err_t ethernetif_init( struct netif *netif );\r
+static struct netif EMAC_if;\r
+\r
+ /* Parameters are not used - suppress compiler error. */\r
+ ( void ) pvParameters;\r
+\r
+\r
+ /* Create and configure the EMAC interface. */\r
+ IP4_ADDR(&xIpAddr,emacIPADDR0,emacIPADDR1,emacIPADDR2,emacIPADDR3);\r
+ IP4_ADDR(&xNetMast,emacNET_MASK0,emacNET_MASK1,emacNET_MASK2,emacNET_MASK3);\r
+ IP4_ADDR(&xGateway,emacGATEWAY_ADDR0,emacGATEWAY_ADDR1,emacGATEWAY_ADDR2,emacGATEWAY_ADDR3);\r
+ netif_add(&EMAC_if, &xIpAddr, &xNetMast, &xGateway, NULL, ethernetif_init, tcpip_input);\r
+\r
+ /* make it the default interface */\r
+ netif_set_default(&EMAC_if);\r
+\r
+ /* bring it up */\r
+ netif_set_up(&EMAC_if);\r
+ \r
+ /* Create a new tcp connection handle */\r
+\r
+ pxHTTPListener = netconn_new( NETCONN_TCP );\r
+ netconn_bind(pxHTTPListener, NULL, webHTTP_PORT );\r
+ netconn_listen( pxHTTPListener );\r
+\r
+ /* Loop forever */\r
+ for( ;; )\r
+ {\r
+ /* Wait for connection. */\r
+ pxNewConnection = netconn_accept(pxHTTPListener);\r
+\r
+ if(pxNewConnection != NULL)\r
+ {\r
+ /* Service connection. */\r
+ vProcessConnection( pxNewConnection );\r
+ while( netconn_delete( pxNewConnection ) != ERR_OK )\r
+ {\r
+ vTaskDelay( webSHORT_DELAY );\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef BASIC_WEB_SERVER_H\r
+#define BASIC_WEB_SERVER_H\r
+\r
+/* The function that implements the WEB server task. */\r
+void vBasicWEBServer( void *pvParameters );\r
+\r
+/* Initialisation required by lwIP. */\r
+void vlwIPInit( void );\r
+\r
+#endif\r
+\r
--- /dev/null
+/*----------------------------------------------------------------------------\r
+* ATMEL Microcontroller Software Support - ROUSSET -\r
+*----------------------------------------------------------------------------\r
+* The software is delivered "AS IS" without warranty or condition of any\r
+* kind, either express, implied or statutory. This includes without\r
+* limitation any warranty or condition with respect to merchantability or\r
+* fitness for any particular purpose, or against the infringements of\r
+* intellectual property rights of others.\r
+*----------------------------------------------------------------------------\r
+* File Name : Board.h\r
+* Object : AT91SAM7X Evaluation Board Features Definition File.\r
+*\r
+* Creation : JG 20/Jun/2005\r
+*----------------------------------------------------------------------------\r
+*/\r
+#ifndef Board_h\r
+#define Board_h\r
+\r
+#include "AT91SAM7X256.h"\r
+#include "ioat91sam7x256.h"\r
+\r
+#define true -1\r
+#define false 0\r
+\r
+/*-------------------------------*/\r
+/* SAM7Board Memories Definition */\r
+/*-------------------------------*/\r
+// The AT91SAM7X128 embeds a 32-Kbyte SRAM bank, and 128K-Byte Flash\r
+\r
+#define FLASH_PAGE_NB 256\r
+#define FLASH_PAGE_SIZE 128\r
+\r
+/*-----------------*/\r
+/* Leds Definition */\r
+/*-----------------*/\r
+#define LED1 (1<<19) // PB19\r
+#define LED2 (1<<20) // PB20\r
+#define LED3 (1<<21) // PB21\r
+#define LED4 (1<<22) // PB22\r
+#define NB_LED 4\r
+\r
+#define LED_MASK (LED1|LED2|LED3|LED4)\r
+\r
+/*-------------------------*/\r
+/* Push Buttons Definition */\r
+/*-------------------------*/\r
+\r
+#define SW1_MASK (1<<21) // PA21\r
+#define SW2_MASK (1<<22) // PA22\r
+#define SW3_MASK (1<<23) // PA23\r
+#define SW4_MASK (1<<24) // PA24\r
+#define SW_MASK (SW1_MASK|SW2_MASK|SW3_MASK|SW4_MASK)\r
+\r
+\r
+#define SW1 (1<<21) // PA21\r
+#define SW2 (1<<22) // PA22\r
+#define SW3 (1<<23) // PA23\r
+#define SW4 (1<<24) // PA24\r
+\r
+/*--------------*/\r
+/* Master Clock */\r
+/*--------------*/\r
+\r
+#define EXT_OC 18432000 // Exetrnal ocilator MAINCK\r
+#define MCK 47923200 // MCK (PLLRC div by 2)\r
+#define MCKKHz (MCK/1000) //\r
+\r
+#endif /* Board_h */\r
--- /dev/null
+//*----------------------------------------------------------------------------\r
+//* ATMEL Microcontroller Software Support - ROUSSET -\r
+//*----------------------------------------------------------------------------\r
+//* The software is delivered "AS IS" without warranty or condition of any\r
+//* kind, either express, implied or statutory. This includes without\r
+//* limitation any warranty or condition with respect to merchantability or\r
+//* fitness for any particular purpose, or against the infringements of\r
+//* intellectual property rights of others.\r
+//*----------------------------------------------------------------------------\r
+//* File Name : Cstartup_SAM7.c\r
+//* Object : Low level initializations written in C for IAR\r
+//* tools\r
+//* 1.0 08/Sep/04 JPP : Creation\r
+//* 1.10 10/Sep/04 JPP : Update AT91C_CKGR_PLLCOUNT filed\r
+//*----------------------------------------------------------------------------\r
+\r
+\r
+// Include the board file description\r
+#include "Board.h"\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_LowLevelInit\r
+//* \brief This function performs very low level HW initialization\r
+//* this function can be use a Stack, depending the compilation\r
+//* optimization mode\r
+//*----------------------------------------------------------------------------\r
+void AT91F_LowLevelInit( void);\r
+void AT91F_LowLevelInit( void )\r
+{\r
+ AT91PS_PMC pPMC = AT91C_BASE_PMC;\r
+\r
+ //* Set Flash Waite sate\r
+ // Single Cycle Access at Up to 30 MHz, or 40\r
+ // if MCK = 47923200 I have 50 Cycle for 1 useconde ( flied MC_FMR->FMCN\r
+ AT91C_BASE_MC->MC_FMR = ((AT91C_MC_FMCN)&(75 <<16)) | AT91C_MC_FWS_1FWS ;\r
+\r
+ //* Watchdog Disable\r
+ AT91C_BASE_WDTC->WDTC_WDMR= AT91C_WDTC_WDDIS;\r
+\r
+ //* Set MCK at 47 923 200\r
+ // 1 Enabling the Main Oscillator:\r
+ // SCK = 1/32768 = 30.51 uSeconde\r
+ // Start up time = 8 * 6 / SCK = 56 * 30.51 = 1,46484375 ms\r
+ pPMC->PMC_MOR = ((( AT91C_CKGR_OSCOUNT & (0x06 <<8)) | AT91C_CKGR_MOSCEN ));\r
+ // Wait the startup time\r
+ while(!(pPMC->PMC_SR & AT91C_PMC_MOSCS));\r
+ // 2 Checking the Main Oscillator Frequency (Optional)\r
+ // 3 Setting PLL and divider:\r
+ // - div by 5 Fin = 3,6864 =(18,432 / 5)\r
+ // - Mul 25+1: Fout = 95,8464 =(3,6864 *26)\r
+ // for 96 MHz the erroe is 0.16%\r
+ //eld out NOT USED = 0 Fi\r
+ pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 5) |\r
+ (AT91C_CKGR_PLLCOUNT & (28<<8)) |\r
+ (AT91C_CKGR_MUL & (25<<16)));\r
+\r
+ // Wait the startup time\r
+ while(!(pPMC->PMC_SR & AT91C_PMC_LOCK));\r
+ // 4. Selection of Master Clock and Processor Clock\r
+ // select the PLL clock divided by 2\r
+ pPMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2 ;\r
+ while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));\r
+\r
+ pPMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK ;\r
+ while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));\r
+}\r
+\r
+\r
+\r
--- /dev/null
+//*----------------------------------------------------------------------------\r
+//* ATMEL Microcontroller Software Support - ROUSSET -\r
+//*----------------------------------------------------------------------------\r
+//* The software is delivered "AS IS" without warranty or condition of any\r
+//* kind, either express, implied or statutory. This includes without\r
+//* limitation any warranty or condition with respect to merchantability or\r
+//* fitness for any particular purpose, or against the infringements of\r
+//* intellectual property rights of others.\r
+//*----------------------------------------------------------------------------\r
+//* File Name : Emac.h\r
+//* Object : Emac header file\r
+//* Creation : Hi 11/18/2002\r
+//*\r
+//*----------------------------------------------------------------------------\r
+#ifndef AT91C_EMAC_H\r
+#define AT91C_EMAC_H\r
+\r
+#include "lwipopts.h"\r
+\r
+\r
+/* Number of receive buffers */\r
+#define NB_RX_BUFFERS 50 \r
+\r
+/* Size of each receive buffer - DO NOT CHANGE. */\r
+#define ETH_RX_BUFFER_SIZE 128 \r
+\r
+/* Number of Transmit buffers */\r
+#define NB_TX_BUFFERS ( MEMP_NUM_PBUF / 2 ) \r
+\r
+/* Size of each Transmit buffer. */\r
+#define ETH_TX_BUFFER_SIZE ( PBUF_POOL_BUFSIZE ) \r
+\r
+/* Receive Transfer descriptor structure */\r
+typedef struct _AT91S_RxTdDescriptor {\r
+ unsigned int addr;\r
+ union\r
+ {\r
+ unsigned int status;\r
+ struct {\r
+ unsigned int Length:11;\r
+ unsigned int Res0:1;\r
+ unsigned int Rxbuf_off:2;\r
+ unsigned int StartOfFrame:1;\r
+ unsigned int EndOfFrame:1;\r
+ unsigned int Cfi:1;\r
+ unsigned int VlanPriority:3;\r
+ unsigned int PriorityTag:1;\r
+ unsigned int VlanTag:1;\r
+ unsigned int TypeID:1;\r
+ unsigned int Sa4Match:1;\r
+ unsigned int Sa3Match:1;\r
+ unsigned int Sa2Match:1;\r
+ unsigned int Sa1Match:1;\r
+ unsigned int Res1:1;\r
+ unsigned int ExternalAdd:1;\r
+ unsigned int UniCast:1;\r
+ unsigned int MultiCast:1;\r
+ unsigned int BroadCast:1;\r
+ }S_Status; \r
+ }U_Status;\r
+}AT91S_RxTdDescriptor, *AT91PS_RxTdDescriptor;\r
+\r
+\r
+/* Transmit Transfer descriptor structure */\r
+typedef struct _AT91S_TxTdDescriptor {\r
+ unsigned int addr;\r
+ union\r
+ {\r
+ unsigned int status;\r
+ struct {\r
+ unsigned int Length:11;\r
+ unsigned int Res0:4;\r
+ unsigned int LastBuff:1;\r
+ unsigned int NoCrc:1;\r
+ unsigned int Res1:10;\r
+ unsigned int BufExhausted:1;\r
+ unsigned int TransmitUnderrun:1;\r
+ unsigned int TransmitError:1;\r
+ unsigned int Wrap:1;\r
+ unsigned int BuffUsed:1;\r
+ }S_Status; \r
+ }U_Status;\r
+}AT91S_TxTdDescriptor, *AT91PS_TxTdDescriptor;\r
+\r
+#define AT91C_OWNERSHIP_BIT 0x00000001\r
+\r
+/* Receive status defintion */\r
+#define AT91C_BROADCAST_ADDR ((unsigned int) (1 << 31)) //* Broadcat address detected\r
+#define AT91C_MULTICAST_HASH ((unsigned int) (1 << 30)) //* MultiCast hash match\r
+#define AT91C_UNICAST_HASH ((unsigned int) (1 << 29)) //* UniCast hash match\r
+#define AT91C_EXTERNAL_ADDR ((unsigned int) (1 << 28)) //* External Address match\r
+#define AT91C_SA1_ADDR ((unsigned int) (1 << 26)) //* Specific address 1 match\r
+#define AT91C_SA2_ADDR ((unsigned int) (1 << 25)) //* Specific address 2 match\r
+#define AT91C_SA3_ADDR ((unsigned int) (1 << 24)) //* Specific address 3 match\r
+#define AT91C_SA4_ADDR ((unsigned int) (1 << 23)) //* Specific address 4 match\r
+#define AT91C_TYPE_ID ((unsigned int) (1 << 22)) //* Type ID match\r
+#define AT91C_VLAN_TAG ((unsigned int) (1 << 21)) //* VLAN tag detected\r
+#define AT91C_PRIORITY_TAG ((unsigned int) (1 << 20)) //* PRIORITY tag detected\r
+#define AT91C_VLAN_PRIORITY ((unsigned int) (7 << 17)) //* PRIORITY Mask\r
+#define AT91C_CFI_IND ((unsigned int) (1 << 16)) //* CFI indicator\r
+#define AT91C_EOF ((unsigned int) (1 << 15)) //* EOF\r
+#define AT91C_SOF ((unsigned int) (1 << 14)) //* SOF\r
+#define AT91C_RBF_OFFSET ((unsigned int) (3 << 12)) //* Receive Buffer Offset Mask\r
+#define AT91C_LENGTH_FRAME ((unsigned int) 0x07FF) //* Length of frame\r
+\r
+/* Transmit Status definition */\r
+#define AT91C_TRANSMIT_OK ((unsigned int) (1 << 31)) //*\r
+#define AT91C_TRANSMIT_WRAP ((unsigned int) (1 << 30)) //* Wrap bit: mark the last descriptor\r
+#define AT91C_TRANSMIT_ERR ((unsigned int) (1 << 29)) //* RLE:transmit error\r
+#define AT91C_TRANSMIT_UND ((unsigned int) (1 << 28)) //* Transmit Underrun\r
+#define AT91C_BUF_EX ((unsigned int) (1 << 27)) //* Buffers exhausted in mid frame\r
+#define AT91C_TRANSMIT_NO_CRC ((unsigned int) (1 << 16)) //* No CRC will be appended to the current frame\r
+#define AT91C_LAST_BUFFER ((unsigned int) (1 << 15)) //*\r
+\r
+#define AT91C_EMAC_CLKEN 0x2\r
+\r
+#endif //* AT91C_EMAC_H\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+ * Interrupt driven driver for the EMAC peripheral. This driver is not\r
+ * reentrant, re-entrancy is handled by a semaphore at the network interface\r
+ * level. \r
+ */\r
+\r
+\r
+/*\r
+Changes from V3.2.2\r
+\r
+ + Corrected the byte order when writing the MAC address to the MAC.\r
+ + Support added for MII interfaces. Previously only RMII was supported.\r
+\r
+Changes from V3.2.3\r
+\r
+ + The MII interface is now the default.\r
+ + Modified the initialisation sequence slightly to allow auto init more\r
+ time to complete.\r
+*/\r
+\r
+\r
+/* Standard includes. */\r
+#include <string.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "semphr.h"\r
+#include "task.h"\r
+\r
+/* Demo app includes. */\r
+#include "SAM7_EMAC.h"\r
+\r
+/* Hardware specific includes. */\r
+#include "Emac.h"\r
+#include "mii.h"\r
+#include "AT91SAM7X256.h"\r
+\r
+\r
+/* USE_RMII_INTERFACE must be defined as 1 to use an RMII interface, or 0\r
+to use an MII interface. */\r
+#define USE_RMII_INTERFACE 0\r
+\r
+\r
+/* The buffer addresses written into the descriptors must be aligned so the\r
+last few bits are zero. These bits have special meaning for the EMAC\r
+peripheral and cannot be used as part of the address. */\r
+#define emacADDRESS_MASK ( ( unsigned portLONG ) 0xFFFFFFFC )\r
+\r
+/* Bit used within the address stored in the descriptor to mark the last\r
+descriptor in the array. */\r
+#define emacRX_WRAP_BIT ( ( unsigned portLONG ) 0x02 )\r
+\r
+/* Bit used within the Tx descriptor status to indicate whether the\r
+descriptor is under the control of the EMAC or the software. */\r
+#define emacTX_BUF_USED ( ( unsigned portLONG ) 0x80000000 )\r
+\r
+/* A short delay is used to wait for a buffer to become available, should\r
+one not be immediately available when trying to transmit a frame. */\r
+#define emacBUFFER_WAIT_DELAY ( 2 )\r
+#define emacMAX_WAIT_CYCLES ( ( portBASE_TYPE ) ( configTICK_RATE_HZ / 40 ) )\r
+\r
+/* The time to block waiting for input. */\r
+#define emacBLOCK_TIME_WAITING_FOR_INPUT ( ( portTickType ) 100 )\r
+\r
+/* Peripheral setup for the EMAC. */\r
+#define emacPERIPHERAL_A_SETUP ( ( unsigned portLONG ) AT91C_PB2_ETX0 ) | \\r
+ ( ( unsigned portLONG ) AT91C_PB12_ETXER ) | \\r
+ ( ( unsigned portLONG ) AT91C_PB16_ECOL ) | \\r
+ ( ( unsigned portLONG ) AT91C_PB11_ETX3 ) | \\r
+ ( ( unsigned portLONG ) AT91C_PB6_ERX1 ) | \\r
+ ( ( unsigned portLONG ) AT91C_PB15_ERXDV ) | \\r
+ ( ( unsigned portLONG ) AT91C_PB13_ERX2 ) | \\r
+ ( ( unsigned portLONG ) AT91C_PB3_ETX1 ) | \\r
+ ( ( unsigned portLONG ) AT91C_PB8_EMDC ) | \\r
+ ( ( unsigned portLONG ) AT91C_PB5_ERX0 ) | \\r
+ ( ( unsigned portLONG ) AT91C_PB14_ERX3 ) | \\r
+ ( ( unsigned portLONG ) AT91C_PB4_ECRS_ECRSDV ) | \\r
+ ( ( unsigned portLONG ) AT91C_PB1_ETXEN ) | \\r
+ ( ( unsigned portLONG ) AT91C_PB10_ETX2 ) | \\r
+ ( ( unsigned portLONG ) AT91C_PB0_ETXCK_EREFCK ) | \\r
+ ( ( unsigned portLONG ) AT91C_PB9_EMDIO ) | \\r
+ ( ( unsigned portLONG ) AT91C_PB7_ERXER ) | \\r
+ ( ( unsigned portLONG ) AT91C_PB17_ERXCK );\r
+\r
+/* Misc defines. */\r
+#define emacINTERRUPT_LEVEL ( 5 )\r
+#define emacNO_DELAY ( 0 )\r
+#define emacTOTAL_FRAME_HEADER_SIZE ( 54 )\r
+#define emacPHY_INIT_DELAY ( 5000 / portTICK_RATE_MS )\r
+#define emacRESET_KEY ( ( unsigned portLONG ) 0xA5000000 )\r
+#define emacRESET_LENGTH ( ( unsigned portLONG ) ( 0x01 << 8 ) )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Buffer written to by the EMAC DMA. Must be aligned as described by the\r
+comment above the emacADDRESS_MASK definition. */\r
+static volatile portCHAR pcRxBuffer[ NB_RX_BUFFERS * ETH_RX_BUFFER_SIZE ] __attribute__ ((aligned (8)));\r
+\r
+/* Buffer read by the EMAC DMA. Must be aligned as described by the comment\r
+above the emacADDRESS_MASK definition. */\r
+static portCHAR pcTxBuffer[ NB_TX_BUFFERS * ETH_TX_BUFFER_SIZE ] __attribute__ ((aligned (8)));\r
+\r
+/* Descriptors used to communicate between the program and the EMAC peripheral.\r
+These descriptors hold the locations and state of the Rx and Tx buffers. */\r
+static volatile AT91S_TxTdDescriptor xTxDescriptors[ NB_TX_BUFFERS ];\r
+static volatile AT91S_RxTdDescriptor xRxDescriptors[ NB_RX_BUFFERS ];\r
+\r
+/* The IP and Ethernet addresses are read from the header files. */\r
+const portCHAR cMACAddress[ 6 ] = { emacETHADDR0, emacETHADDR1, emacETHADDR2, emacETHADDR3, emacETHADDR4, emacETHADDR5 };\r
+const unsigned char ucIPAddress[ 4 ] = { emacIPADDR0, emacIPADDR1, emacIPADDR2, emacIPADDR3 };\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* See the header file for descriptions of public functions. */\r
+\r
+/*\r
+ * Prototype for the EMAC interrupt function - called by the asm wrapper.\r
+ */\r
+void vEMACISR( void ) __attribute__ ((naked));\r
+\r
+/*\r
+ * Initialise both the Tx and Rx descriptors used by the EMAC.\r
+ */\r
+static void prvSetupDescriptors(void);\r
+\r
+/*\r
+ * Write our MAC address into the EMAC. \r
+ */\r
+static void prvSetupMACAddress( void );\r
+\r
+/*\r
+ * Configure the EMAC and AIC for EMAC interrupts.\r
+ */\r
+static void prvSetupEMACInterrupt( void );\r
+\r
+/*\r
+ * Some initialisation functions taken from the Atmel EMAC sample code.\r
+ */\r
+static void vReadPHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG *pulValue );\r
+static portBASE_TYPE xGetLinkSpeed( void );\r
+static portBASE_TYPE prvProbePHY( void );\r
+#if USE_RMII_INTERFACE != 1\r
+ static void vWritePHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG ulValue);\r
+#endif\r
+\r
+\r
+/* The semaphore used by the EMAC ISR to wake the EMAC task. */\r
+static xSemaphoreHandle xSemaphore = NULL;\r
+\r
+/* Holds the index to the next buffer from which data will be read. */\r
+static volatile unsigned portLONG ulNextRxBuffer = 0;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* See the header file for descriptions of public functions. */\r
+portLONG lEMACSend( portCHAR *pcFrom, unsigned portLONG ulLength, portLONG lEndOfFrame )\r
+{\r
+static unsigned portBASE_TYPE uxTxBufferIndex = 0;\r
+portBASE_TYPE xWaitCycles = 0;\r
+portLONG lReturn = pdPASS;\r
+portCHAR *pcBuffer;\r
+unsigned portLONG ulLastBuffer, ulDataBuffered = 0, ulDataRemainingToSend, ulLengthToSend;\r
+\r
+ /* If the length of data to be transmitted is greater than each individual\r
+ transmit buffer then the data will be split into more than one buffer.\r
+ Loop until the entire length has been buffered. */\r
+ while( ulDataBuffered < ulLength )\r
+ {\r
+ /* Is a buffer available? */\r
+ while( !( xTxDescriptors[ uxTxBufferIndex ].U_Status.status & AT91C_TRANSMIT_OK ) )\r
+ {\r
+ /* There is no room to write the Tx data to the Tx buffer. Wait a\r
+ short while, then try again. */\r
+ xWaitCycles++;\r
+ if( xWaitCycles > emacMAX_WAIT_CYCLES )\r
+ {\r
+ /* Give up. */\r
+ lReturn = pdFAIL;\r
+ break;\r
+ }\r
+ else\r
+ {\r
+ vTaskDelay( emacBUFFER_WAIT_DELAY );\r
+ }\r
+ }\r
+ \r
+ /* lReturn will only be pdPASS if a buffer is available. */\r
+ if( lReturn == pdPASS )\r
+ {\r
+ portENTER_CRITICAL();\r
+ {\r
+ /* Get the address of the buffer from the descriptor, then copy \r
+ the data into the buffer. */\r
+ pcBuffer = ( portCHAR * ) xTxDescriptors[ uxTxBufferIndex ].addr;\r
+\r
+ /* How much can we write to the buffer? */\r
+ ulDataRemainingToSend = ulLength - ulDataBuffered;\r
+ if( ulDataRemainingToSend <= ETH_TX_BUFFER_SIZE )\r
+ {\r
+ /* We can write all the remaining bytes. */\r
+ ulLengthToSend = ulDataRemainingToSend;\r
+ }\r
+ else\r
+ {\r
+ /* We can not write more than ETH_TX_BUFFER_SIZE in one go. */\r
+ ulLengthToSend = ETH_TX_BUFFER_SIZE;\r
+ }\r
+\r
+ /* Copy the data into the buffer. */\r
+ memcpy( ( void * ) pcBuffer, ( void * ) &( pcFrom[ ulDataBuffered ] ), ulLengthToSend );\r
+ ulDataBuffered += ulLengthToSend;\r
+\r
+ /* Is this the last data for the frame? */\r
+ if( lEndOfFrame && ( ulDataBuffered >= ulLength ) )\r
+ {\r
+ /* No more data remains for this frame so we can start the \r
+ transmission. */\r
+ ulLastBuffer = AT91C_LAST_BUFFER;\r
+ }\r
+ else\r
+ {\r
+ /* More data to come for this frame. */\r
+ ulLastBuffer = 0;\r
+ }\r
+ \r
+ /* Fill out the necessary in the descriptor to get the data sent, \r
+ then move to the next descriptor, wrapping if necessary. */\r
+ if( uxTxBufferIndex >= ( NB_TX_BUFFERS - 1 ) )\r
+ { \r
+ xTxDescriptors[ uxTxBufferIndex ].U_Status.status = ( ulLengthToSend & ( unsigned portLONG ) AT91C_LENGTH_FRAME )\r
+ | ulLastBuffer\r
+ | AT91C_TRANSMIT_WRAP;\r
+ uxTxBufferIndex = 0;\r
+ }\r
+ else\r
+ {\r
+ xTxDescriptors[ uxTxBufferIndex ].U_Status.status = ( ulLengthToSend & ( unsigned portLONG ) AT91C_LENGTH_FRAME )\r
+ | ulLastBuffer;\r
+ uxTxBufferIndex++;\r
+ }\r
+ \r
+ /* If this is the last buffer to be sent for this frame we can\r
+ start the transmission. */\r
+ if( ulLastBuffer )\r
+ {\r
+ AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TSTART;\r
+ }\r
+ }\r
+ portEXIT_CRITICAL();\r
+ }\r
+ else\r
+ {\r
+ break;\r
+ }\r
+ }\r
+\r
+ return lReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* See the header file for descriptions of public functions. */\r
+unsigned portLONG ulEMACInputLength( void )\r
+{\r
+register unsigned portLONG ulIndex, ulLength = 0;\r
+\r
+ /* Skip any fragments. We are looking for the first buffer that contains\r
+ data and has the SOF (start of frame) bit set. */\r
+ while( ( xRxDescriptors[ ulNextRxBuffer ].addr & AT91C_OWNERSHIP_BIT ) && !( xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AT91C_SOF ) )\r
+ {\r
+ /* Ignoring this buffer. Mark it as free again. */\r
+ xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT ); \r
+ ulNextRxBuffer++;\r
+ if( ulNextRxBuffer >= NB_RX_BUFFERS )\r
+ {\r
+ ulNextRxBuffer = 0;\r
+ }\r
+ }\r
+\r
+ /* We are going to walk through the descriptors that make up this frame, \r
+ but don't want to alter ulNextRxBuffer as this would prevent vEMACRead()\r
+ from finding the data. Therefore use a copy of ulNextRxBuffer instead. */\r
+ ulIndex = ulNextRxBuffer;\r
+\r
+ /* Walk through the descriptors until we find the last buffer for this \r
+ frame. The last buffer will give us the length of the entire frame. */\r
+ while( ( xRxDescriptors[ ulIndex ].addr & AT91C_OWNERSHIP_BIT ) && !ulLength )\r
+ {\r
+ ulLength = xRxDescriptors[ ulIndex ].U_Status.status & AT91C_LENGTH_FRAME;\r
+\r
+ /* Increment to the next buffer, wrapping if necessary. */\r
+ ulIndex++;\r
+ if( ulIndex >= NB_RX_BUFFERS )\r
+ {\r
+ ulIndex = 0;\r
+ }\r
+ }\r
+\r
+ return ulLength;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* See the header file for descriptions of public functions. */\r
+void vEMACRead( portCHAR *pcTo, unsigned portLONG ulSectionLength, unsigned portLONG ulTotalFrameLength )\r
+{\r
+static unsigned portLONG ulSectionBytesReadSoFar = 0, ulBufferPosition = 0, ulFameBytesReadSoFar = 0;\r
+static portCHAR *pcSource;\r
+register unsigned portLONG ulBytesRemainingInBuffer, ulRemainingSectionBytes;\r
+\r
+ /* Read ulSectionLength bytes from the Rx buffers. This is not necessarily any\r
+ correspondence between the length of our Rx buffers, and the length of the\r
+ data we are returning or the length of the data being requested. Therefore, \r
+ between calls we have to remember not only which buffer we are currently \r
+ processing, but our position within that buffer. This would be greatly\r
+ simplified if PBUF_POOL_BUFSIZE could be guaranteed to be greater than\r
+ the size of each Rx buffer, and that memory fragmentation did not occur.\r
+ \r
+ This function should only be called after a call to ulEMACInputLength().\r
+ This will ensure ulNextRxBuffer is set to the correct buffer. */\r
+\r
+\r
+\r
+ /* vEMACRead is called with pcTo set to NULL to indicate that we are about\r
+ to read a new frame. Any fragments remaining in the frame we were \r
+ processing during the last call should be dropped. */\r
+ if( pcTo == NULL )\r
+ {\r
+ /* How many bytes are indicated as being in this buffer? If none then\r
+ the buffer is completely full and the frame is contained within more\r
+ than one buffer. */\r
+\r
+ /* Reset our state variables ready for the next read from this buffer. */\r
+ pcSource = ( portCHAR * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK );\r
+ ulFameBytesReadSoFar = ( unsigned portLONG ) 0;\r
+ ulBufferPosition = ( unsigned portLONG ) 0;\r
+ }\r
+ else\r
+ {\r
+ /* Loop until we have obtained the required amount of data. */\r
+ ulSectionBytesReadSoFar = 0;\r
+ while( ulSectionBytesReadSoFar < ulSectionLength )\r
+ {\r
+ /* We may have already read some data from this buffer. How much\r
+ data remains in the buffer? */\r
+ ulBytesRemainingInBuffer = ( ETH_RX_BUFFER_SIZE - ulBufferPosition );\r
+\r
+ /* How many more bytes do we need to read before we have the \r
+ required amount of data? */\r
+ ulRemainingSectionBytes = ulSectionLength - ulSectionBytesReadSoFar;\r
+\r
+ /* Do we want more data than remains in the buffer? */\r
+ if( ulRemainingSectionBytes > ulBytesRemainingInBuffer )\r
+ {\r
+ /* We want more data than remains in the buffer so we can \r
+ write the remains of the buffer to the destination, then move\r
+ onto the next buffer to get the rest. */\r
+ memcpy( &( pcTo[ ulSectionBytesReadSoFar ] ), &( pcSource[ ulBufferPosition ] ), ulBytesRemainingInBuffer );\r
+ ulSectionBytesReadSoFar += ulBytesRemainingInBuffer;\r
+ ulFameBytesReadSoFar += ulBytesRemainingInBuffer;\r
+\r
+ /* Mark the buffer as free again. */\r
+ xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );\r
+\r
+ /* Move onto the next buffer. */\r
+ ulNextRxBuffer++;\r
+ if( ulNextRxBuffer >= NB_RX_BUFFERS )\r
+ {\r
+ ulNextRxBuffer = ( unsigned portLONG ) 0;\r
+ }\r
+\r
+ /* Reset the variables for the new buffer. */\r
+ pcSource = ( portCHAR * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK );\r
+ ulBufferPosition = ( unsigned portLONG ) 0;\r
+ }\r
+ else\r
+ {\r
+ /* We have enough data in this buffer to send back. Read out\r
+ enough data and remember how far we read up to. */\r
+ memcpy( &( pcTo[ ulSectionBytesReadSoFar ] ), &( pcSource[ ulBufferPosition ] ), ulRemainingSectionBytes );\r
+\r
+ /* There may be more data in this buffer yet. Increment our \r
+ position in this buffer past the data we have just read. */\r
+ ulBufferPosition += ulRemainingSectionBytes;\r
+ ulSectionBytesReadSoFar += ulRemainingSectionBytes;\r
+ ulFameBytesReadSoFar += ulRemainingSectionBytes;\r
+\r
+ /* Have we now finished with this buffer? */\r
+ if( ( ulBufferPosition >= ETH_RX_BUFFER_SIZE ) || ( ulFameBytesReadSoFar >= ulTotalFrameLength ) )\r
+ {\r
+ /* Mark the buffer as free again. */\r
+ xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );\r
+\r
+ /* Move onto the next buffer. */\r
+ ulNextRxBuffer++;\r
+ if( ulNextRxBuffer >= NB_RX_BUFFERS )\r
+ {\r
+ ulNextRxBuffer = 0;\r
+ }\r
+ \r
+ pcSource = ( portCHAR * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK );\r
+ ulBufferPosition = 0;\r
+ }\r
+ }\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* See the header file for descriptions of public functions. */\r
+xSemaphoreHandle xEMACInit( void )\r
+{\r
+ /* Code supplied by Atmel -------------------------------*/\r
+\r
+ /* Disable pull up on RXDV => PHY normal mode (not in test mode),\r
+ PHY has internal pull down. */\r
+ AT91C_BASE_PIOB->PIO_PPUDR = 1 << 15;\r
+\r
+ #if USE_RMII_INTERFACE != 1\r
+ /* PHY has internal pull down : set MII mode. */\r
+ AT91C_BASE_PIOB->PIO_PPUDR = 1 << 16;\r
+ #endif\r
+\r
+ /* Clear PB18 <=> PHY powerdown. */\r
+ AT91C_BASE_PIOB->PIO_PER = 1 << 18;\r
+ AT91C_BASE_PIOB->PIO_OER = 1 << 18;\r
+ AT91C_BASE_PIOB->PIO_CODR = 1 << 18;\r
+\r
+ /* After PHY power up, hardware reset. */\r
+ AT91C_BASE_RSTC->RSTC_RMR = emacRESET_KEY | emacRESET_LENGTH;\r
+ AT91C_BASE_RSTC->RSTC_RCR = emacRESET_KEY | AT91C_RSTC_EXTRST;\r
+\r
+ /* Wait for hardware reset end. */\r
+ while( !( AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL ) )\r
+ {\r
+ __asm volatile ( "NOP" );\r
+ }\r
+ __asm volatile ( "NOP" );\r
+\r
+ /* Setup the pins. */\r
+ AT91C_BASE_PIOB->PIO_ASR = emacPERIPHERAL_A_SETUP;\r
+ AT91C_BASE_PIOB->PIO_PDR = emacPERIPHERAL_A_SETUP;\r
+\r
+ /* Enable com between EMAC PHY.\r
+\r
+ Enable management port. */\r
+ AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE; \r
+\r
+ /* MDC = MCK/32. */\r
+ AT91C_BASE_EMAC->EMAC_NCFGR |= ( 2 ) << 10; \r
+\r
+ /* Wait for PHY auto init end (rather crude delay!). */\r
+ vTaskDelay( emacPHY_INIT_DELAY );\r
+\r
+ /* PHY configuration. */\r
+ #if USE_RMII_INTERFACE != 1\r
+ {\r
+ unsigned portLONG ulControl;\r
+\r
+ /* PHY has internal pull down : disable MII isolate. */\r
+ vReadPHY( AT91C_PHY_ADDR, MII_BMCR, &ulControl );\r
+ vReadPHY( AT91C_PHY_ADDR, MII_BMCR, &ulControl );\r
+ ulControl &= ~BMCR_ISOLATE;\r
+ vWritePHY( AT91C_PHY_ADDR, MII_BMCR, ulControl );\r
+ }\r
+ #endif\r
+\r
+ /* Disable management port again. */\r
+ AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;\r
+\r
+ #if USE_RMII_INTERFACE != 1\r
+ /* Enable EMAC in MII mode, enable clock ERXCK and ETXCK. */\r
+ AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_CLKEN ;\r
+ #else\r
+ /* Enable EMAC in RMII mode, enable RMII clock (50MHz from oscillator\r
+ on ERFCK). */\r
+ AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_RMII | AT91C_EMAC_CLKEN ;\r
+ #endif\r
+\r
+ /* End of code supplied by Atmel ------------------------*/\r
+\r
+ /* Setup the buffers and descriptors. */\r
+ prvSetupDescriptors();\r
+ \r
+ /* Load our MAC address into the EMAC. */\r
+ prvSetupMACAddress();\r
+\r
+ /* Are we connected? */\r
+ if( prvProbePHY() )\r
+ {\r
+ /* Enable the interrupt! */\r
+ portENTER_CRITICAL();\r
+ {\r
+ prvSetupEMACInterrupt();\r
+ vPassEMACSemaphore( xSemaphore );\r
+ }\r
+ portEXIT_CRITICAL();\r
+ }\r
+\r
+ return xSemaphore;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* See the header file for descriptions of public functions. */\r
+void vClearEMACTxBuffer( void )\r
+{\r
+static unsigned portBASE_TYPE uxNextBufferToClear = 0;\r
+\r
+ /* Called on Tx interrupt events to reset the AT91C_TRANSMIT_OK bit in each \r
+ Tx buffer within the frame just transmitted. This marks all the buffers\r
+ as available again.\r
+\r
+ The first buffer in the frame should have the bit set automatically. */\r
+ if( xTxDescriptors[ uxNextBufferToClear ].U_Status.status & AT91C_TRANSMIT_OK )\r
+ {\r
+ /* Loop through the other buffers in the frame. */\r
+ while( !( xTxDescriptors[ uxNextBufferToClear ].U_Status.status & AT91C_LAST_BUFFER ) )\r
+ {\r
+ uxNextBufferToClear++;\r
+\r
+ if( uxNextBufferToClear >= NB_TX_BUFFERS )\r
+ {\r
+ uxNextBufferToClear = 0;\r
+ }\r
+\r
+ xTxDescriptors[ uxNextBufferToClear ].U_Status.status |= AT91C_TRANSMIT_OK;\r
+ }\r
+ }\r
+\r
+ /* Start with the next buffer the next time a Tx interrupt is called. */\r
+ uxNextBufferToClear++;\r
+\r
+ /* Do we need to wrap back to the first buffer? */\r
+ if( uxNextBufferToClear >= NB_TX_BUFFERS )\r
+ {\r
+ uxNextBufferToClear = 0;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupDescriptors(void)\r
+{\r
+unsigned portBASE_TYPE xIndex;\r
+unsigned portLONG ulAddress;\r
+\r
+ /* Initialise xRxDescriptors descriptor. */\r
+ for( xIndex = 0; xIndex < NB_RX_BUFFERS; ++xIndex )\r
+ {\r
+ /* Calculate the address of the nth buffer within the array. */\r
+ ulAddress = ( unsigned portLONG )( pcRxBuffer + ( xIndex * ETH_RX_BUFFER_SIZE ) );\r
+\r
+ /* Write the buffer address into the descriptor. The DMA will place\r
+ the data at this address when this descriptor is being used. Mask off\r
+ the bottom bits of the address as these have special meaning. */\r
+ xRxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK;\r
+ } \r
+\r
+ /* The last buffer has the wrap bit set so the EMAC knows to wrap back\r
+ to the first buffer. */\r
+ xRxDescriptors[ NB_RX_BUFFERS - 1 ].addr |= emacRX_WRAP_BIT;\r
+\r
+ /* Initialise xTxDescriptors. */\r
+ for( xIndex = 0; xIndex < NB_TX_BUFFERS; ++xIndex )\r
+ {\r
+ /* Calculate the address of the nth buffer within the array. */\r
+ ulAddress = ( unsigned portLONG )( pcTxBuffer + ( xIndex * ETH_TX_BUFFER_SIZE ) );\r
+\r
+ /* Write the buffer address into the descriptor. The DMA will read\r
+ data from here when the descriptor is being used. */\r
+ xTxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK;\r
+ xTxDescriptors[ xIndex ].U_Status.status = AT91C_TRANSMIT_OK;\r
+ } \r
+\r
+ /* The last buffer has the wrap bit set so the EMAC knows to wrap back\r
+ to the first buffer. */\r
+ xTxDescriptors[ NB_TX_BUFFERS - 1 ].U_Status.status = AT91C_TRANSMIT_WRAP | AT91C_TRANSMIT_OK;\r
+\r
+ /* Tell the EMAC where to find the descriptors. */\r
+ AT91C_BASE_EMAC->EMAC_RBQP = ( unsigned portLONG ) xRxDescriptors;\r
+ AT91C_BASE_EMAC->EMAC_TBQP = ( unsigned portLONG ) xTxDescriptors;\r
+ \r
+ /* Clear all the bits in the receive status register. */\r
+ AT91C_BASE_EMAC->EMAC_RSR = ( AT91C_EMAC_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA );\r
+\r
+ /* Enable the copy of data into the buffers, ignore broadcasts, \r
+ and don't copy FCS. */\r
+ AT91C_BASE_EMAC->EMAC_NCFGR |= ( AT91C_EMAC_CAF | AT91C_EMAC_NBC | AT91C_EMAC_DRFCS);\r
+\r
+ /* Enable Rx and Tx, plus the stats register. */\r
+ AT91C_BASE_EMAC->EMAC_NCR |= ( AT91C_EMAC_TE | AT91C_EMAC_RE | AT91C_EMAC_WESTAT );\r
+} \r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupMACAddress( void )\r
+{\r
+ /* Must be written SA1L then SA1H. */\r
+ AT91C_BASE_EMAC->EMAC_SA1L = ( ( unsigned portLONG ) cMACAddress[ 3 ] << 24 ) |\r
+ ( ( unsigned portLONG ) cMACAddress[ 2 ] << 16 ) |\r
+ ( ( unsigned portLONG ) cMACAddress[ 1 ] << 8 ) |\r
+ cMACAddress[ 0 ];\r
+\r
+ AT91C_BASE_EMAC->EMAC_SA1H = ( ( unsigned portLONG ) cMACAddress[ 5 ] << 8 ) |\r
+ cMACAddress[ 4 ];\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupEMACInterrupt( void )\r
+{\r
+ /* Create the semaphore used to trigger the EMAC task. */\r
+ vSemaphoreCreateBinary( xSemaphore );\r
+ if( xSemaphore )\r
+ {\r
+ /* We start by 'taking' the semaphore so the ISR can 'give' it when the\r
+ first interrupt occurs. */\r
+ xSemaphoreTake( xSemaphore, emacNO_DELAY );\r
+ portENTER_CRITICAL();\r
+ {\r
+ /* We want to interrupt on Rx and Tx events. */\r
+ AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_RCOMP | AT91C_EMAC_TCOMP;\r
+\r
+ /* Enable the interrupts in the AIC. */\r
+ AT91F_AIC_ConfigureIt( AT91C_ID_EMAC, emacINTERRUPT_LEVEL, AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, ( void (*)( void ) ) vEMACISR );\r
+ AT91C_BASE_AIC->AIC_IECR = 0x1 << AT91C_ID_EMAC;\r
+ }\r
+ portEXIT_CRITICAL();\r
+ }\r
+}\r
+\r
+\r
+\r
+\r
+\r
+/*\r
+ * The following functions are initialisation functions taken from the Atmel\r
+ * EMAC sample code.\r
+ */\r
+\r
+\r
+static portBASE_TYPE prvProbePHY( void )\r
+{\r
+unsigned portLONG ulPHYId1, ulPHYId2, ulStatus;\r
+portBASE_TYPE xReturn = pdPASS;\r
+ \r
+ /* Code supplied by Atmel (reformatted) -----------------*/\r
+\r
+ /* Enable management port */\r
+ AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE; \r
+ AT91C_BASE_EMAC->EMAC_NCFGR |= ( 2 ) << 10;\r
+\r
+ /* Read the PHY ID. */\r
+ vReadPHY( AT91C_PHY_ADDR, MII_PHYSID1, &ulPHYId1 );\r
+ vReadPHY(AT91C_PHY_ADDR, MII_PHYSID2, &ulPHYId2 );\r
+\r
+ /* AMD AM79C875:\r
+ PHY_ID1 = 0x0022\r
+ PHY_ID2 = 0x5541\r
+ Bits 3:0 Revision Number Four bit manufacturer?s revision number.\r
+ 0001 stands for Rev. A, etc.\r
+ */\r
+ if( ( ( ulPHYId1 << 16 ) | ( ulPHYId2 & 0xfff0 ) ) != MII_DM9161_ID )\r
+ {\r
+ /* Did not expect this ID. */\r
+ xReturn = pdFAIL;\r
+ }\r
+ else\r
+ {\r
+ ulStatus = xGetLinkSpeed();\r
+\r
+ if( ulStatus != pdPASS )\r
+ {\r
+ xReturn = pdFAIL;\r
+ }\r
+ }\r
+\r
+ /* Disable management port */\r
+ AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE; \r
+\r
+ /* End of code supplied by Atmel ------------------------*/\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vReadPHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG *pulValue )\r
+{\r
+ /* Code supplied by Atmel (reformatted) ----------------------*/\r
+\r
+ AT91C_BASE_EMAC->EMAC_MAN = (AT91C_EMAC_SOF & (0x01<<30))\r
+ | (2 << 16) | (2 << 28)\r
+ | ((ucPHYAddress & 0x1f) << 23)\r
+ | (ucAddress << 18);\r
+\r
+ /* Wait until IDLE bit in Network Status register is cleared. */\r
+ while( !( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE ) )\r
+ {\r
+ __asm( "NOP" );\r
+ }\r
+\r
+ *pulValue = ( AT91C_BASE_EMAC->EMAC_MAN & 0x0000ffff ); \r
+\r
+ /* End of code supplied by Atmel ------------------------*/\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if USE_RMII_INTERFACE != 1\r
+static void vWritePHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG ulValue )\r
+{\r
+ /* Code supplied by Atmel (reformatted) ----------------------*/\r
+\r
+ AT91C_BASE_EMAC->EMAC_MAN = (( AT91C_EMAC_SOF & (0x01<<30))\r
+ | (2 << 16) | (1 << 28)\r
+ | ((ucPHYAddress & 0x1f) << 23)\r
+ | (ucAddress << 18))\r
+ | (ulValue & 0xffff);\r
+\r
+ /* Wait until IDLE bit in Network Status register is cleared */\r
+ while( !( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE ) )\r
+ {\r
+ __asm( "NOP" );\r
+ };\r
+\r
+ /* End of code supplied by Atmel ------------------------*/\r
+}\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+static portBASE_TYPE xGetLinkSpeed( void )\r
+{\r
+ unsigned portLONG ulBMSR, ulBMCR, ulLPA, ulMACCfg, ulSpeed, ulDuplex;\r
+\r
+ /* Code supplied by Atmel (reformatted) -----------------*/\r
+\r
+ /* Link status is latched, so read twice to get current value */\r
+ vReadPHY(AT91C_PHY_ADDR, MII_BMSR, &ulBMSR);\r
+ vReadPHY(AT91C_PHY_ADDR, MII_BMSR, &ulBMSR);\r
+\r
+ if( !( ulBMSR & BMSR_LSTATUS ) )\r
+ { \r
+ /* No Link. */\r
+ return pdFAIL;\r
+ }\r
+\r
+ vReadPHY(AT91C_PHY_ADDR, MII_BMCR, &ulBMCR);\r
+ if (ulBMCR & BMCR_ANENABLE)\r
+ { \r
+ /* AutoNegotiation is enabled. */\r
+ if (!(ulBMSR & BMSR_ANEGCOMPLETE))\r
+ {\r
+ /* Auto-negotitation in progress. */\r
+ return pdFAIL; \r
+ } \r
+\r
+ vReadPHY(AT91C_PHY_ADDR, MII_LPA, &ulLPA);\r
+ if( ( ulLPA & LPA_100FULL ) || ( ulLPA & LPA_100HALF ) )\r
+ {\r
+ ulSpeed = SPEED_100;\r
+ }\r
+ else\r
+ {\r
+ ulSpeed = SPEED_10;\r
+ }\r
+\r
+ if( ( ulLPA & LPA_100FULL ) || ( ulLPA & LPA_10FULL ) )\r
+ {\r
+ ulDuplex = DUPLEX_FULL;\r
+ }\r
+ else\r
+ {\r
+ ulDuplex = DUPLEX_HALF;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ ulSpeed = ( ulBMCR & BMCR_SPEED100 ) ? SPEED_100 : SPEED_10;\r
+ ulDuplex = ( ulBMCR & BMCR_FULLDPLX ) ? DUPLEX_FULL : DUPLEX_HALF;\r
+ }\r
+\r
+ /* Update the MAC */\r
+ ulMACCfg = AT91C_BASE_EMAC->EMAC_NCFGR & ~( AT91C_EMAC_SPD | AT91C_EMAC_FD );\r
+ if( ulSpeed == SPEED_100 )\r
+ {\r
+ if( ulDuplex == DUPLEX_FULL )\r
+ {\r
+ /* 100 Full Duplex */\r
+ AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_SPD | AT91C_EMAC_FD;\r
+ }\r
+ else\r
+ { \r
+ /* 100 Half Duplex */\r
+ AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_SPD;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if (ulDuplex == DUPLEX_FULL)\r
+ {\r
+ /* 10 Full Duplex */\r
+ AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_FD;\r
+ }\r
+ else\r
+ { /* 10 Half Duplex */\r
+ AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg;\r
+ }\r
+ }\r
+\r
+ /* End of code supplied by Atmel ------------------------*/\r
+\r
+ return pdPASS;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vEMACWaitForInput( void )\r
+{\r
+ /* Just wait until we are signled from an ISR that data is available, or\r
+ we simply time out. */\r
+ xSemaphoreTake( xSemaphore, emacBLOCK_TIME_WAITING_FOR_INPUT );\r
+}\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+Changes from V3.2.4\r
+\r
+ + Modified the default MAC address as the one used previously was not liked\r
+ by some routers.\r
+\r
+*/\r
+\r
+#ifndef SAM_7_EMAC_H\r
+#define SAM_7_EMAC_H\r
+\r
+/* MAC address definition. The MAC address must be unique on the network. */\r
+#define emacETHADDR0 0\r
+#define emacETHADDR1 0xbd\r
+#define emacETHADDR2 0x33\r
+#define emacETHADDR3 0x06\r
+#define emacETHADDR4 0x68\r
+#define emacETHADDR5 0x22\r
+\r
+/* The IP address being used. */\r
+#define emacIPADDR0 172\r
+#define emacIPADDR1 25\r
+#define emacIPADDR2 218\r
+#define emacIPADDR3 205\r
+\r
+/* The gateway address being used. */\r
+#define emacGATEWAY_ADDR0 172\r
+#define emacGATEWAY_ADDR1 25\r
+#define emacGATEWAY_ADDR2 218\r
+#define emacGATEWAY_ADDR3 3\r
+\r
+/* The network mask being used. */\r
+#define emacNET_MASK0 255\r
+#define emacNET_MASK1 255\r
+#define emacNET_MASK2 0\r
+#define emacNET_MASK3 0\r
+\r
+/*\r
+ * Initialise the EMAC driver. If successful a semaphore is returned that\r
+ * is used by the EMAC ISR to indicate that Rx packets have been received.\r
+ * If the initialisation fails then NULL is returned.\r
+ */\r
+xSemaphoreHandle xEMACInit( void );\r
+\r
+/*\r
+ * Send ulLength bytes from pcFrom. This copies the buffer to one of the\r
+ * EMAC Tx buffers, then indicates to the EMAC that the buffer is ready.\r
+ * If lEndOfFrame is true then the data being copied is the end of the frame\r
+ * and the frame can be transmitted. \r
+ */\r
+portLONG lEMACSend( portCHAR *pcFrom, unsigned portLONG ulLength, portLONG lEndOfFrame );\r
+\r
+/*\r
+ * Frames can be read from the EMAC in multiple sections.\r
+ * Read ulSectionLength bytes from the EMAC receive buffers to pcTo. \r
+ * ulTotalFrameLength is the size of the entire frame. Generally vEMACRead\r
+ * will be repetedly called until the sum of all the ulSectionLenths totals\r
+ * the value of ulTotalFrameLength.\r
+ */\r
+void vEMACRead( portCHAR *pcTo, unsigned portLONG ulSectionLength, unsigned portLONG ulTotalFrameLength );\r
+\r
+/*\r
+ * The EMAC driver and interrupt service routines are defined in different \r
+ * files as the driver is compiled to THUMB, and the ISR to ARM. This function\r
+ * simply passes the semaphore used to communicate between the two.\r
+ */\r
+void vPassEMACSemaphore( xSemaphoreHandle xCreatedSemaphore );\r
+\r
+/* \r
+ * Called by the Tx interrupt, this function traverses the buffers used to\r
+ * hold the frame that has just completed transmission and marks each as\r
+ * free again.\r
+ */\r
+void vClearEMACTxBuffer( void );\r
+\r
+/*\r
+ * Suspend on a semaphore waiting either for the semaphore to be obtained \r
+ * or a timeout. The semaphore is used by the EMAC ISR to indicate that\r
+ * data has been received and is ready for processing.\r
+ */\r
+void vEMACWaitForInput( void );\r
+\r
+/*\r
+ * Return the length of the next frame in the receive buffers.\r
+ */\r
+unsigned portLONG ulEMACInputLength( void );\r
+\r
+#endif\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* \r
+Changes from V3.2.4\r
+\r
+ + Also read the EMAC_RSR register in the EMAC ISR as a work around the \r
+ the EMAC bug that can reset the RX bit in EMAC_ISR register before the\r
+ bit has been read.\r
+*/\r
+\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "semphr.h"\r
+#include "SAM7_EMAC.h"\r
+#include "AT91SAM7X256.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The semaphore used to signal the arrival of new data to the interface\r
+task. */\r
+static xSemaphoreHandle xSemaphore = NULL;\r
+\r
+void vEMACISR( void ) __attribute__((naked));\r
+\r
+/*-----------------------------------------------------------*/\r
+/*\r
+ * The EMAC ISR. Handles both Tx and Rx complete interrupts.\r
+ */\r
+void vEMACISR( void )\r
+{\r
+ /* This ISR can cause a context switch, so the first statement must be a\r
+ call to the portENTER_SWITCHING_ISR() macro. This must be BEFORE any\r
+ variable declarations. */\r
+ portENTER_SWITCHING_ISR();\r
+\r
+ /* Variable definitions can be made now. */\r
+ volatile unsigned portLONG ulIntStatus, ulEventStatus;\r
+ portBASE_TYPE xSwitchRequired = pdFALSE;\r
+ extern void vClearEMACTxBuffer( void );\r
+\r
+ /* Find the cause of the interrupt. */\r
+ ulIntStatus = AT91C_BASE_EMAC->EMAC_ISR;\r
+ ulEventStatus = AT91C_BASE_EMAC->EMAC_RSR;\r
+\r
+ if( ( ulIntStatus & AT91C_EMAC_RCOMP ) || ( ulEventStatus & AT91C_EMAC_REC ) )\r
+ {\r
+ /* A frame has been received, signal the lwIP task so it can process\r
+ the Rx descriptors. */\r
+ xSwitchRequired = xSemaphoreGiveFromISR( xSemaphore, pdFALSE );\r
+ AT91C_BASE_EMAC->EMAC_RSR = AT91C_EMAC_REC;\r
+ }\r
+\r
+ ulEventStatus = AT91C_BASE_EMAC->EMAC_TSR;\r
+ if( ( ulIntStatus & AT91C_EMAC_TCOMP ) || ( ulEventStatus & AT91C_EMAC_COMP ) )\r
+ {\r
+ /* A frame has been transmitted. Mark all the buffers used by the\r
+ frame just transmitted as free again. */\r
+ vClearEMACTxBuffer();\r
+ AT91C_BASE_EMAC->EMAC_TSR = AT91C_EMAC_COMP;\r
+ }\r
+\r
+ /* Clear the interrupt. */\r
+ AT91C_BASE_AIC->AIC_EOICR = 0;\r
+\r
+ /* If a task was woken by either a frame being received then we may need to \r
+ switch to another task. */\r
+ portEXIT_SWITCHING_ISR( xSwitchRequired );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPassEMACSemaphore( xSemaphoreHandle xCreatedSemaphore )\r
+{\r
+ /* Simply store the semaphore that should be used by the ISR. */\r
+ xSemaphore = xCreatedSemaphore;\r
+}\r
+\r
--- /dev/null
+/* Generic MII registers. */\r
+\r
+#define MII_BMCR 0x00 /* Basic mode control register */\r
+#define MII_BMSR 0x01 /* Basic mode status register */\r
+#define MII_PHYSID1 0x02 /* PHYS ID 1 */\r
+#define MII_PHYSID2 0x03 /* PHYS ID 2 */\r
+#define MII_ADVERTISE 0x04 /* Advertisement control reg */\r
+#define MII_LPA 0x05 /* Link partner ability reg */\r
+#define MII_EXPANSION 0x06 /* Expansion register */\r
+#define MII_DCOUNTER 0x12 /* Disconnect counter */\r
+#define MII_FCSCOUNTER 0x13 /* False carrier counter */\r
+#define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */\r
+#define MII_RERRCOUNTER 0x15 /* Receive error counter */\r
+#define MII_SREVISION 0x16 /* Silicon revision */\r
+#define MII_RESV1 0x17 /* Reserved... */\r
+#define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */\r
+#define MII_PHYADDR 0x19 /* PHY address */\r
+#define MII_RESV2 0x1a /* Reserved... */\r
+#define MII_TPISTATUS 0x1b /* TPI status for 10mbps */\r
+#define MII_NCONFIG 0x1c /* Network interface config */\r
+\r
+/* Basic mode control register. */\r
+#define BMCR_RESV 0x007f /* Unused... */\r
+#define BMCR_CTST 0x0080 /* Collision test */\r
+#define BMCR_FULLDPLX 0x0100 /* Full duplex */\r
+#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */\r
+#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */\r
+#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */\r
+#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */\r
+#define BMCR_SPEED100 0x2000 /* Select 100Mbps */\r
+#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */\r
+#define BMCR_RESET 0x8000 /* Reset the DP83840 */\r
+\r
+/* Basic mode status register. */\r
+#define BMSR_ERCAP 0x0001 /* Ext-reg capability */\r
+#define BMSR_JCD 0x0002 /* Jabber detected */\r
+#define BMSR_LSTATUS 0x0004 /* Link status */\r
+#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */\r
+#define BMSR_RFAULT 0x0010 /* Remote fault detected */\r
+#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */\r
+#define BMSR_RESV 0x07c0 /* Unused... */\r
+#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */\r
+#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */\r
+#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */\r
+#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */\r
+#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */\r
+\r
+/* Advertisement control register. */\r
+#define ADVERTISE_SLCT 0x001f /* Selector bits */\r
+#define ADVERTISE_CSMA 0x0001 /* Only selector supported */\r
+#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */\r
+#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */\r
+#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */\r
+#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */\r
+#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */\r
+#define ADVERTISE_RESV 0x1c00 /* Unused... */\r
+#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */\r
+#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */\r
+#define ADVERTISE_NPAGE 0x8000 /* Next page bit */\r
+\r
+#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \\r
+ ADVERTISE_CSMA)\r
+#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \\r
+ ADVERTISE_100HALF | ADVERTISE_100FULL)\r
+\r
+/* Link partner ability register. */\r
+#define LPA_SLCT 0x001f /* Same as advertise selector */\r
+#define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */\r
+#define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */\r
+#define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */\r
+#define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */\r
+#define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */\r
+#define LPA_RESV 0x1c00 /* Unused... */\r
+#define LPA_RFAULT 0x2000 /* Link partner faulted */\r
+#define LPA_LPACK 0x4000 /* Link partner acked us */\r
+#define LPA_NPAGE 0x8000 /* Next page bit */\r
+\r
+#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL)\r
+#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)\r
+\r
+/* Expansion register for auto-negotiation. */\r
+#define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */\r
+#define EXPANSION_LCWP 0x0002 /* Got new RX page code word */\r
+#define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */\r
+#define EXPANSION_NPCAPABLE 0x0008 /* Link partner supports npage */\r
+#define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */\r
+#define EXPANSION_RESV 0xffe0 /* Unused... */\r
+\r
+/* N-way test register. */\r
+#define NWAYTEST_RESV1 0x00ff /* Unused... */\r
+#define NWAYTEST_LOOPBACK 0x0100 /* Enable loopback for N-way */\r
+#define NWAYTEST_RESV2 0xfe00 /* Unused... */\r
+\r
+#define SPEED_10 10\r
+#define SPEED_100 100\r
+\r
+/* Duplex, half or full. */\r
+#define DUPLEX_HALF 0x00\r
+#define DUPLEX_FULL 0x01\r
+\r
+/* PHY ID */\r
+#define MII_DM9161_ID 0x0181b8a0\r
+#define MII_AM79C875_ID 0x00225540 /* 0x00225541 */\r
+\r
+#define AT91C_PHY_ADDR 31\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *----------------------------------------------------------*/\r
+\r
+/* The SWI is used by the scheduler. */\r
+#define vPortYieldProcessor swi_handler\r
+\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 1\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 47923200 )\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 110 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) 24000 )\r
+#define configMAX_TASK_NAME_LEN ( 16 )\r
+#define configUSE_TRACE_FACILITY 1\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 1\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+#define INCLUDE_xTaskGetCurrentTaskHandle 1\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+\r
+/* Demo application includes. */\r
+#include "partest.h"\r
+\r
+/* Hardware specific includes. */\r
+#include "Board.h"\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple parallel port IO routines for the LED's. LED's can be set, cleared\r
+ * or toggled.\r
+ *-----------------------------------------------------------*/\r
+const unsigned portLONG ulLED_MASK[ NB_LED ]= { LED1, LED2, LED3, LED4 };\r
+\r
+void vParTestInitialise( void )\r
+{ \r
+ /* Start with all LED's off. */\r
+ AT91C_BASE_PIOB->PIO_SODR = LED_MASK;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )\r
+{\r
+ if( uxLED < ( portBASE_TYPE ) NB_LED )\r
+ {\r
+ if( xValue )\r
+ {\r
+ AT91C_BASE_PIOB->PIO_SODR = ulLED_MASK[ uxLED ];\r
+ }\r
+ else\r
+ {\r
+ AT91C_BASE_PIOB->PIO_CODR = ulLED_MASK[ uxLED ];\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+ if( uxLED < ( portBASE_TYPE ) NB_LED )\r
+ {\r
+ if( AT91C_BASE_PIOB->PIO_PDSR & ulLED_MASK[ uxLED ] )\r
+ {\r
+ AT91C_BASE_PIOB->PIO_CODR = ulLED_MASK[ uxLED ];\r
+ }\r
+ else\r
+ {\r
+ AT91C_BASE_PIOB->PIO_SODR = ulLED_MASK[ uxLED ];\r
+ }\r
+ }\r
+}\r
+\r
--- /dev/null
+[Version]\r
+Signature="$Windows NT$"\r
+Class=Ports\r
+ClassGuid={4D36E978-E325-11CE-BFC1-08002BE10318}\r
+Provider=%ATMEL%\r
+LayoutFile=layout.inf\r
+DriverVer=10/15/1999,5.0.2153.1\r
+\r
+[MANUFACTURER]\r
+%FreeRTOS%=FreeRTOS\r
+\r
+[FreeRTOS]\r
+%FreeRTOS_CDC%=Reader,USB\VID_EB03&PID_0920\r
+\r
+[Reader_Install.NTx86]\r
+;Windows2000\r
+\r
+[DestinationDirs]\r
+DefaultDestDir=12\r
+Reader.NT.Copy=12\r
+\r
+[Reader.NT]\r
+CopyFiles=Reader.NT.Copy\r
+AddReg=Reader.NT.AddReg\r
+\r
+[Reader.NT.Copy]\r
+usbser.sys\r
+\r
+[Reader.NT.AddReg]\r
+HKR,,NTMPDriver,,*ntkern\r
+HKR,,NTMPDriver,,usbser.sys\r
+HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider"\r
+[Reader.NT.Services]\r
+AddService = usbser, 0x00000002,Service_Inst\r
+\r
+[Service_Inst]\r
+DisplayName = %Serial.SvcDesc%\r
+ServiceType = 1 ; SERVICE_KERNEL_DRIVER\r
+StartType = 3 ; SERVICE_DEMAND_START\r
+ErrorControl = 1 ;SERVICE_ERROR_NORMAL\r
+ServiceBinary = %12%\usbser.sys\r
+LoadOrderGroup = Base\r
+\r
+[Strings]\r
+FreeRTOS = "FreeRTOS"\r
+FreeRTOS_CDC = "FreeRTOS CDC Demo"\r
+Serial.SvcDesc = "USB Serial emulation driver"\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+ USB Communications Device Class driver.\r
+ Implements task vUSBCDCTask and provides an Abstract Control Model serial \r
+ interface. Control is through endpoint 0, device-to-host notification is \r
+ provided by interrupt-in endpoint 3, and raw data is transferred through \r
+ bulk endpoints 1 and 2.\r
+\r
+ - developed from original FreeRTOS HID example by Scott Miller\r
+ - modified to support 3.2 GCC by najay\r
+*/\r
+\r
+/* Standard includes. */\r
+#include <string.h>\r
+#include <stdio.h>\r
+\r
+/* Demo board includes. */\r
+#include "Board.h"\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+\r
+/* Demo app includes. */\r
+#include "USB-CDC.h"\r
+#include "descriptors.h"\r
+\r
+#define usbNO_BLOCK ( ( portTickType ) 0 )\r
+\r
+/* Reset all endpoints */\r
+static void prvResetEndPoints( void );\r
+\r
+/* Clear pull up resistor to detach device from host */\r
+static void vDetachUSBInterface( void );\r
+\r
+/* Set up interface and initialize variables */\r
+static void vInitUSBInterface( void );\r
+\r
+/* Handle control endpoint events. */\r
+static void prvProcessEndPoint0Interrupt( xISRStatus *pxMessage );\r
+\r
+/* Handle standard device requests. */\r
+static void prvHandleStandardDeviceRequest( xUSB_REQUEST *pxRequest );\r
+\r
+/* Handle standard interface requests. */\r
+static void prvHandleStandardInterfaceRequest( xUSB_REQUEST *pxRequest );\r
+\r
+/* Handle endpoint requests. */\r
+static void prvHandleStandardEndPointRequest( xUSB_REQUEST *pxRequest );\r
+\r
+/* Handle class interface requests. */\r
+static void prvHandleClassInterfaceRequest( xUSB_REQUEST *pxRequest );\r
+\r
+/* Prepare control data transfer. prvSendNextSegment starts transfer. */\r
+static void prvSendControlData( unsigned portCHAR *pucData, unsigned portSHORT usRequestedLength, unsigned portLONG ulLengthLeftToSend, portLONG lSendingDescriptor );\r
+\r
+/* Send next segment of data for the control transfer */\r
+static void prvSendNextSegment( void );\r
+\r
+/* Send stall - used to respond to unsupported requests */\r
+static void prvSendStall( void );\r
+\r
+/* Send a zero-length (null) packet */\r
+static void prvSendZLP( void );\r
+\r
+/* Handle requests for standard interface descriptors */\r
+static void prvGetStandardInterfaceDescriptor( xUSB_REQUEST *pxRequest );\r
+\r
+/*------------------------------------------------------------*/\r
+\r
+/* File scope static variables */\r
+static unsigned portCHAR ucUSBConfig = ( unsigned portCHAR ) 0;\r
+static unsigned portLONG ulReceivedAddress = ( unsigned portLONG ) 0;\r
+static eDRIVER_STATE eDriverState = eNOTHING;\r
+\r
+/* Incoming and outgoing control data structures */\r
+static xCONTROL_MESSAGE pxControlTx;\r
+static xCONTROL_MESSAGE pxControlRx;\r
+\r
+/* Queue holding pointers to pending messages */\r
+xQueueHandle xUSBInterruptQueue; \r
+\r
+/* Queues used to hold received characters, and characters waiting to be\r
+transmitted. Rx queue must be larger than FIFO size. */\r
+static xQueueHandle xRxCDC; \r
+static xQueueHandle xTxCDC; \r
+\r
+/* Line coding - 115,200 baud, N-8-1 */\r
+static const unsigned portCHAR pxLineCoding[] = { 0x00, 0xC2, 0x01, 0x00, 0x00, 0x00, 0x08 };\r
+\r
+/* Status variables. */\r
+static unsigned portCHAR ucControlState;\r
+static unsigned int uiCurrentBank;\r
+\r
+\r
+/*------------------------------------------------------------*/\r
+\r
+\r
+void vUSBCDCTask( void *pvParameters )\r
+{\r
+xISRStatus *pxMessage;\r
+unsigned portLONG ulStatus;\r
+unsigned portLONG ulRxBytes;\r
+unsigned portCHAR ucByte;\r
+portBASE_TYPE xByte;\r
+\r
+ ( void ) pvParameters;\r
+\r
+ /* Disconnect USB device from hub. For debugging - causes host to register reset */\r
+ portENTER_CRITICAL();\r
+ vDetachUSBInterface();\r
+ portEXIT_CRITICAL();\r
+ \r
+ vTaskDelay( portTICK_RATE_MS * 60 );\r
+\r
+ /* Init USB interface */\r
+ portENTER_CRITICAL();\r
+ vInitUSBInterface();\r
+ portEXIT_CRITICAL();\r
+ \r
+ /* Main task loop. Process incoming endpoint 0 interrupts, handle data transfers. */\r
+ \r
+ for( ;; )\r
+ {\r
+ /* Look for data coming from the ISR. */\r
+ if( xQueueReceive( xUSBInterruptQueue, &pxMessage, usbSHORTEST_DELAY ) )\r
+ {\r
+ if( pxMessage->ulISR & AT91C_UDP_EPINT0 )\r
+ {\r
+ /* All endpoint 0 interrupts are handled here. */\r
+ prvProcessEndPoint0Interrupt( pxMessage );\r
+ }\r
+\r
+ if( pxMessage->ulISR & AT91C_UDP_ENDBUSRES )\r
+ {\r
+ /* End of bus reset - reset the endpoints and de-configure. */\r
+ prvResetEndPoints(); \r
+ }\r
+ }\r
+ \r
+ /* See if we're ready to send and receive data. */\r
+ if( eDriverState == eREADY_TO_SEND && ucControlState ) \r
+ {\r
+ if( ( !(AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_2 ] & AT91C_UDP_TXPKTRDY) ) && uxQueueMessagesWaiting( xTxCDC ) )\r
+ {\r
+ for( xByte = 0; xByte < 64; xByte++ )\r
+ { \r
+ if( !xQueueReceive( xTxCDC, &ucByte, 0 ) ) \r
+ {\r
+ /* No data buffered to transmit. */\r
+ break;\r
+ }\r
+\r
+ /* Got a byte to transmit. */\r
+ AT91C_BASE_UDP->UDP_FDR[ usbEND_POINT_2 ] = ucByte;\r
+ } \r
+ AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_2 ] |= AT91C_UDP_TXPKTRDY;\r
+ }\r
+\r
+ /* Check for incoming data (host-to-device) on endpoint 1. */\r
+ while( AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ] & (AT91C_UDP_RX_DATA_BK0 | AT91C_UDP_RX_DATA_BK1) )\r
+ {\r
+ ulRxBytes = (AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ] >> 16) & usbRX_COUNT_MASK;\r
+\r
+ /* Only process FIFO if there's room to store it in the queue */\r
+ if( ulRxBytes < ( USB_CDC_QUEUE_SIZE - uxQueueMessagesWaiting( xRxCDC ) ) )\r
+ {\r
+ while( ulRxBytes-- )\r
+ {\r
+ ucByte = AT91C_BASE_UDP->UDP_FDR[ usbEND_POINT_1 ];\r
+ xQueueSend( xRxCDC, &ucByte, 0 );\r
+ }\r
+\r
+ /* Release the FIFO */\r
+ portENTER_CRITICAL();\r
+ {\r
+ ulStatus = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ];\r
+ usbCSR_CLEAR_BIT( &ulStatus, uiCurrentBank );\r
+ AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ] = ulStatus;\r
+ }\r
+ portEXIT_CRITICAL();\r
+\r
+ /* Re-enable endpoint 1's interrupts */\r
+ AT91C_BASE_UDP->UDP_IER = AT91C_UDP_EPINT1;\r
+ \r
+ /* Update the current bank in use */\r
+ if( uiCurrentBank == AT91C_UDP_RX_DATA_BK0 ) \r
+ {\r
+ uiCurrentBank = AT91C_UDP_RX_DATA_BK1;\r
+ }\r
+ else \r
+ {\r
+ uiCurrentBank = AT91C_UDP_RX_DATA_BK0;\r
+ }\r
+\r
+ }\r
+ else \r
+ {\r
+ break;\r
+ }\r
+ }\r
+ }\r
+ }\r
+}\r
+/*------------------------------------------------------------*/\r
+\r
+void vUSBSendByte( portCHAR cByte )\r
+{\r
+ /* Queue the byte to be sent. The USB task will send it. */\r
+ xQueueSend( xTxCDC, &cByte, usbNO_BLOCK );\r
+}\r
+/*------------------------------------------------------------*/\r
+\r
+static void prvSendZLP( void )\r
+{\r
+unsigned portLONG ulStatus;\r
+\r
+ /* Wait until the FIFO is free - even though we are not going to use it.\r
+ THERE IS NO TIMEOUT HERE! */\r
+ while( AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] & AT91C_UDP_TXPKTRDY )\r
+ {\r
+ vTaskDelay( usbSHORTEST_DELAY );\r
+ }\r
+\r
+ portENTER_CRITICAL();\r
+ {\r
+ /* Cancel any further pending data */\r
+ pxControlTx.ulTotalDataLength = pxControlTx.ulNextCharIndex;\r
+\r
+ /* Set the TXPKTRDY bit to cause a transmission with no data. */\r
+ ulStatus = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ];\r
+ usbCSR_SET_BIT( &ulStatus, AT91C_UDP_TXPKTRDY );\r
+ AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] = ulStatus;\r
+ }\r
+ portEXIT_CRITICAL();\r
+}\r
+/*------------------------------------------------------------*/\r
+\r
+static void prvSendStall( void )\r
+{\r
+ unsigned portLONG ulStatus;\r
+\r
+ portENTER_CRITICAL();\r
+ {\r
+ /* Force a stall by simply setting the FORCESTALL bit in the CSR. */\r
+ ulStatus = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ];\r
+ usbCSR_SET_BIT( &ulStatus, AT91C_UDP_FORCESTALL );\r
+ AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] = ulStatus;\r
+ }\r
+ portEXIT_CRITICAL();\r
+}\r
+/*------------------------------------------------------------*/\r
+\r
+static void prvResetEndPoints( void )\r
+{\r
+unsigned portLONG ulTemp;\r
+\r
+ eDriverState = eJUST_RESET;\r
+ ucControlState = 0;\r
+\r
+ /* Reset all the end points. */\r
+ AT91C_BASE_UDP->UDP_RSTEP = usbEND_POINT_RESET_MASK;\r
+ AT91C_BASE_UDP->UDP_RSTEP = ( unsigned portLONG ) 0x00;\r
+\r
+ /* Enable data to be sent and received. */\r
+ AT91C_BASE_UDP->UDP_FADDR = AT91C_UDP_FEN;\r
+\r
+ /* Repair the configuration end point. */\r
+ portENTER_CRITICAL();\r
+ {\r
+ ulTemp = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ];\r
+ usbCSR_SET_BIT( &ulTemp, ( ( unsigned portLONG ) ( AT91C_UDP_EPEDS | AT91C_UDP_EPTYPE_CTRL ) ) );\r
+ AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] = ulTemp;\r
+ AT91C_BASE_UDP->UDP_IER = AT91C_UDP_EPINT0;\r
+ }\r
+ portEXIT_CRITICAL();\r
+ uiCurrentBank = AT91C_UDP_RX_DATA_BK0;\r
+}\r
+/*------------------------------------------------------------*/\r
+\r
+static void prvProcessEndPoint0Interrupt( xISRStatus *pxMessage )\r
+{\r
+static xUSB_REQUEST xRequest;\r
+unsigned portLONG ulRxBytes;\r
+\r
+ /* Get number of bytes received, if any */\r
+ ulRxBytes = pxMessage->ulCSR0 >> 16;\r
+ ulRxBytes &= usbRX_COUNT_MASK;\r
+\r
+ if( pxMessage->ulCSR0 & AT91C_UDP_TXCOMP )\r
+ {\r
+ /* We received a TX complete interrupt. What we do depends on\r
+ what we sent to get this interrupt. */\r
+\r
+ if( eDriverState == eJUST_GOT_CONFIG )\r
+ {\r
+ /* We sent an acknowledgement of a SET_CONFIG request. We\r
+ are now at the end of the enumeration.\r
+ \r
+ TODO: Config 0 sets unconfigured state, should enter Address state.\r
+ Request for unsupported config should stall. */\r
+ AT91C_BASE_UDP->UDP_GLBSTATE = AT91C_UDP_CONFG;\r
+ \r
+ /* Set up endpoints */\r
+ portENTER_CRITICAL();\r
+ {\r
+ unsigned portLONG ulTemp;\r
+\r
+ /* Set endpoint 1 to bulk-out */\r
+ ulTemp = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ]; \r
+ usbCSR_SET_BIT( &ulTemp, AT91C_UDP_EPEDS | AT91C_UDP_EPTYPE_BULK_OUT );\r
+ AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ] = ulTemp; \r
+ AT91C_BASE_UDP->UDP_IER = AT91C_UDP_EPINT1;\r
+ /* Set endpoint 2 to bulk-in */\r
+ ulTemp = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_2 ]; \r
+ usbCSR_SET_BIT( &ulTemp, AT91C_UDP_EPEDS | AT91C_UDP_EPTYPE_BULK_IN );\r
+ AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_2 ] = ulTemp; \r
+ AT91C_BASE_UDP->UDP_IER = AT91C_UDP_EPINT2;\r
+ /* Set endpoint 3 to interrupt-in, enable it, and enable interrupts */\r
+ ulTemp = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_3 ]; \r
+ usbCSR_SET_BIT( &ulTemp, AT91C_UDP_EPEDS | AT91C_UDP_EPTYPE_INT_IN );\r
+ AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_3 ] = ulTemp; \r
+ /*AT91F_UDP_EnableIt( AT91C_BASE_UDP, AT91C_UDP_EPINT3 ); */\r
+ }\r
+ portEXIT_CRITICAL();\r
+\r
+ eDriverState = eREADY_TO_SEND;\r
+ } \r
+ else if( eDriverState == eJUST_GOT_ADDRESS )\r
+ {\r
+ /* We sent an acknowledgement of a SET_ADDRESS request. Move\r
+ to the addressed state. */\r
+ if( ulReceivedAddress != ( unsigned portLONG ) 0 )\r
+ { \r
+ AT91C_BASE_UDP->UDP_GLBSTATE = AT91C_UDP_FADDEN;\r
+ }\r
+ else\r
+ {\r
+ AT91C_BASE_UDP->UDP_GLBSTATE = 0;\r
+ } \r
+\r
+ AT91C_BASE_UDP->UDP_FADDR = ( AT91C_UDP_FEN | ulReceivedAddress ); \r
+ eDriverState = eNOTHING;\r
+ }\r
+ else\r
+ { \r
+ /* The TXCOMP was not for any special type of transmission. See\r
+ if there is any more data to send. */\r
+ prvSendNextSegment();\r
+ }\r
+ }\r
+\r
+ if( pxMessage->ulCSR0 & AT91C_UDP_RX_DATA_BK0 )\r
+ {\r
+ /* Received a control data packet. May be a 0-length ACK or a data stage. */\r
+ unsigned portCHAR ucBytesToGet;\r
+ \r
+ /* Got data. Cancel any outgoing data. */\r
+ pxControlTx.ulNextCharIndex = pxControlTx.ulTotalDataLength;\r
+ \r
+ /* Determine how many bytes we need to receive. */\r
+ ucBytesToGet = pxControlRx.ulTotalDataLength - pxControlRx.ulNextCharIndex;\r
+ if( ucBytesToGet > ulRxBytes ) \r
+ { \r
+ ucBytesToGet = ulRxBytes;\r
+ }\r
+\r
+ /* If we're not expecting any data, it's an ack - just quit now. */\r
+ if( !ucBytesToGet )\r
+ {\r
+ return;\r
+ }\r
+\r
+ /* Get the required data and update the index. */\r
+ memcpy( pxControlRx.ucBuffer, pxMessage->ucFifoData, ucBytesToGet );\r
+ pxControlRx.ulNextCharIndex += ucBytesToGet; \r
+ }\r
+\r
+ if( pxMessage->ulCSR0 & AT91C_UDP_RXSETUP )\r
+ {\r
+ /* Received a SETUP packet. May be followed by data packets. */\r
+\r
+ if( ulRxBytes >= usbEXPECTED_NUMBER_OF_BYTES )\r
+ { \r
+ /* Create an xUSB_REQUEST variable from the raw bytes array. */\r
+\r
+ xRequest.ucReqType = pxMessage->ucFifoData[ usbREQUEST_TYPE_INDEX ];\r
+ xRequest.ucRequest = pxMessage->ucFifoData[ usbREQUEST_INDEX ];\r
+\r
+ xRequest.usValue = pxMessage->ucFifoData[ usbVALUE_HIGH_BYTE ];\r
+ xRequest.usValue <<= 8;\r
+ xRequest.usValue |= pxMessage->ucFifoData[ usbVALUE_LOW_BYTE ];\r
+ \r
+ xRequest.usIndex = pxMessage->ucFifoData[ usbINDEX_HIGH_BYTE ];\r
+ xRequest.usIndex <<= 8;\r
+ xRequest.usIndex |= pxMessage->ucFifoData[ usbINDEX_LOW_BYTE ];\r
+ \r
+ xRequest.usLength = pxMessage->ucFifoData[ usbLENGTH_HIGH_BYTE ];\r
+ xRequest.usLength <<= 8;\r
+ xRequest.usLength |= pxMessage->ucFifoData[ usbLENGTH_LOW_BYTE ];\r
+\r
+ pxControlRx.ulNextCharIndex = 0;\r
+ if( ! (xRequest.ucReqType & 0x80) ) /* Host-to-Device transfer, may need to get data first */\r
+ {\r
+ if( xRequest.usLength > usbMAX_CONTROL_MESSAGE_SIZE )\r
+ { \r
+ /* Too big! No space for control data, stall and abort. */\r
+ prvSendStall();\r
+ return;\r
+ }\r
+\r
+ pxControlRx.ulTotalDataLength = xRequest.usLength;\r
+ }\r
+ else\r
+ {\r
+ /* We're sending the data, don't wait for any. */\r
+ pxControlRx.ulTotalDataLength = 0; \r
+ }\r
+ }\r
+ }\r
+\r
+ /* See if we've got a pending request and all its associated data ready */\r
+ if( ( pxMessage->ulCSR0 & ( AT91C_UDP_RX_DATA_BK0 | AT91C_UDP_RXSETUP ) ) \r
+ && ( pxControlRx.ulNextCharIndex >= pxControlRx.ulTotalDataLength ) )\r
+ {\r
+ unsigned portCHAR ucRequest;\r
+\r
+ /* Manipulate the ucRequestType and the ucRequest parameters to \r
+ generate a zero based request selection. This is just done to \r
+ break up the requests into subsections for clarity. The \r
+ alternative would be to have more huge switch statement that would\r
+ be difficult to optimise. */\r
+ ucRequest = ( ( xRequest.ucReqType & 0x60 ) >> 3 );\r
+ ucRequest |= ( xRequest.ucReqType & 0x03 );\r
+ \r
+ switch( ucRequest )\r
+ {\r
+ case usbSTANDARD_DEVICE_REQUEST: \r
+ /* Standard Device request */\r
+ prvHandleStandardDeviceRequest( &xRequest );\r
+ break;\r
+\r
+ case usbSTANDARD_INTERFACE_REQUEST: \r
+ /* Standard Interface request */\r
+ prvHandleStandardInterfaceRequest( &xRequest );\r
+ break;\r
+\r
+ case usbSTANDARD_END_POINT_REQUEST: \r
+ /* Standard Endpoint request */\r
+ prvHandleStandardEndPointRequest( &xRequest );\r
+ break;\r
+\r
+ case usbCLASS_INTERFACE_REQUEST: \r
+ /* Class Interface request */\r
+ prvHandleClassInterfaceRequest( &xRequest );\r
+ break;\r
+\r
+ default: /* This is not something we want to respond to. */\r
+ prvSendStall(); \r
+ }\r
+ }\r
+}\r
+/*------------------------------------------------------------*/\r
+\r
+static void prvGetStandardDeviceDescriptor( xUSB_REQUEST *pxRequest )\r
+{\r
+ /* The type is in the high byte. Return whatever has been requested. */\r
+ switch( ( pxRequest->usValue & 0xff00 ) >> 8 )\r
+ {\r
+ case usbDESCRIPTOR_TYPE_DEVICE:\r
+ prvSendControlData( ( unsigned portCHAR * ) &pxDeviceDescriptor, pxRequest->usLength, sizeof( pxDeviceDescriptor ), pdTRUE );\r
+ break;\r
+\r
+ case usbDESCRIPTOR_TYPE_CONFIGURATION:\r
+ prvSendControlData( ( unsigned portCHAR * ) &( pxConfigDescriptor ), pxRequest->usLength, sizeof( pxConfigDescriptor ), pdTRUE );\r
+ break;\r
+\r
+ case usbDESCRIPTOR_TYPE_STRING:\r
+\r
+ /* The index to the string descriptor is the lower byte. */\r
+ switch( pxRequest->usValue & 0xff )\r
+ { \r
+ case usbLANGUAGE_STRING:\r
+ prvSendControlData( ( unsigned portCHAR * ) &pxLanguageStringDescriptor, pxRequest->usLength, sizeof(pxLanguageStringDescriptor), pdTRUE );\r
+ break;\r
+\r
+ case usbMANUFACTURER_STRING:\r
+ prvSendControlData( ( unsigned portCHAR * ) &pxManufacturerStringDescriptor, pxRequest->usLength, sizeof( pxManufacturerStringDescriptor ), pdTRUE );\r
+ break;\r
+\r
+ case usbPRODUCT_STRING:\r
+ prvSendControlData( ( unsigned portCHAR * ) &pxProductStringDescriptor, pxRequest->usLength, sizeof( pxProductStringDescriptor ), pdTRUE );\r
+ break;\r
+\r
+ case usbCONFIGURATION_STRING:\r
+ prvSendControlData( ( unsigned portCHAR * ) &pxConfigurationStringDescriptor, pxRequest->usLength, sizeof( pxConfigurationStringDescriptor ), pdTRUE );\r
+ break;\r
+\r
+ case usbINTERFACE_STRING:\r
+ prvSendControlData( ( unsigned portCHAR * ) &pxInterfaceStringDescriptor, pxRequest->usLength, sizeof( pxInterfaceStringDescriptor ), pdTRUE );\r
+ break;\r
+\r
+ default:\r
+ prvSendStall();\r
+ break;\r
+ }\r
+ break;\r
+\r
+ default:\r
+ prvSendStall();\r
+ break;\r
+ }\r
+}\r
+/*------------------------------------------------------------*/\r
+\r
+static void prvHandleStandardDeviceRequest( xUSB_REQUEST *pxRequest )\r
+{\r
+unsigned portSHORT usStatus = 0;\r
+\r
+ switch( pxRequest->ucRequest )\r
+ {\r
+ case usbGET_STATUS_REQUEST:\r
+ /* Just send two byte dummy status. */\r
+ prvSendControlData( ( unsigned portCHAR * ) &usStatus, sizeof( usStatus ), sizeof( usStatus ), pdFALSE );\r
+ break;\r
+\r
+ case usbGET_DESCRIPTOR_REQUEST:\r
+ /* Send device descriptor */\r
+ prvGetStandardDeviceDescriptor( pxRequest );\r
+ break;\r
+\r
+ case usbGET_CONFIGURATION_REQUEST:\r
+ /* Send selected device configuration */\r
+ prvSendControlData( ( unsigned portCHAR * ) &ucUSBConfig, sizeof( ucUSBConfig ), sizeof( ucUSBConfig ), pdFALSE );\r
+ break;\r
+\r
+ case usbSET_FEATURE_REQUEST:\r
+ prvSendZLP();\r
+ break;\r
+\r
+ case usbSET_ADDRESS_REQUEST: \r
+ /* Get assigned address and send ack, but don't implement new address until we get a TXCOMP */\r
+ prvSendZLP(); \r
+ eDriverState = eJUST_GOT_ADDRESS; \r
+ ulReceivedAddress = ( unsigned portLONG ) pxRequest->usValue;\r
+ break;\r
+\r
+ case usbSET_CONFIGURATION_REQUEST:\r
+ /* Ack SET_CONFIGURATION request, but don't implement until TXCOMP */\r
+ ucUSBConfig = ( unsigned portCHAR ) ( pxRequest->usValue & 0xff );\r
+ eDriverState = eJUST_GOT_CONFIG;\r
+ prvSendZLP();\r
+ break;\r
+\r
+ default:\r
+ /* Any unsupported request results in a STALL response. */\r
+ prvSendStall();\r
+ break;\r
+ }\r
+}\r
+/*------------------------------------------------------------*/\r
+\r
+static void prvHandleClassInterfaceRequest( xUSB_REQUEST *pxRequest )\r
+{\r
+ switch( pxRequest->ucRequest )\r
+ {\r
+ case usbSEND_ENCAPSULATED_COMMAND:\r
+ prvSendStall();\r
+ break;\r
+\r
+ case usbGET_ENCAPSULATED_RESPONSE:\r
+ prvSendStall();\r
+ break;\r
+\r
+ case usbSET_LINE_CODING:\r
+ /* Set line coding - baud rate, data bits, parity, stop bits */\r
+ prvSendZLP();\r
+ memcpy( ( void * ) pxLineCoding, pxControlRx.ucBuffer, sizeof( pxLineCoding ) );\r
+ break;\r
+\r
+ case usbGET_LINE_CODING:\r
+ /* Get line coding */\r
+ prvSendControlData( (unsigned portCHAR *) &pxLineCoding, pxRequest->usLength, sizeof( pxLineCoding ), pdFALSE );\r
+ break;\r
+\r
+ case usbSET_CONTROL_LINE_STATE:\r
+ /* D0: 1=DTR, 0=No DTR, D1: 1=Activate Carrier, 0=Deactivate carrier (RTS, half-duplex) */\r
+ prvSendZLP();\r
+ ucControlState = pxRequest->usValue;\r
+ break;\r
+\r
+ default:\r
+ prvSendStall();\r
+ break;\r
+ }\r
+}\r
+/*------------------------------------------------------------*/\r
+\r
+static void prvGetStandardInterfaceDescriptor( xUSB_REQUEST *pxRequest )\r
+{\r
+ switch( ( pxRequest->usValue & ( unsigned portSHORT ) 0xff00 ) >> 8 )\r
+ {\r
+ default:\r
+ prvSendStall();\r
+ break;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvHandleStandardInterfaceRequest( xUSB_REQUEST *pxRequest )\r
+{\r
+unsigned portSHORT usStatus = 0;\r
+\r
+ switch( pxRequest->ucRequest )\r
+ {\r
+ case usbGET_STATUS_REQUEST:\r
+ /* Send dummy 2 bytes. */\r
+ prvSendControlData( ( unsigned portCHAR * ) &usStatus, sizeof( usStatus ), sizeof( usStatus ), pdFALSE );\r
+ break;\r
+\r
+ case usbGET_DESCRIPTOR_REQUEST:\r
+ prvGetStandardInterfaceDescriptor( pxRequest ); \r
+ break;\r
+\r
+ /* This minimal implementation does not respond to these. */\r
+ case usbGET_INTERFACE_REQUEST:\r
+ case usbSET_FEATURE_REQUEST:\r
+ case usbSET_INTERFACE_REQUEST: \r
+\r
+ default:\r
+ prvSendStall();\r
+ break;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvHandleStandardEndPointRequest( xUSB_REQUEST *pxRequest )\r
+{\r
+ switch( pxRequest->ucRequest )\r
+ {\r
+ /* This minimal implementation does not expect to respond to these. */\r
+ case usbGET_STATUS_REQUEST:\r
+ case usbCLEAR_FEATURE_REQUEST: \r
+ case usbSET_FEATURE_REQUEST:\r
+\r
+ default: \r
+ prvSendStall();\r
+ break;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vDetachUSBInterface( void)\r
+{\r
+ /* Setup the PIO for the USB pull up resistor. */\r
+ AT91C_BASE_PIOA->PIO_PER = AT91C_PIO_PA16;\r
+ AT91C_BASE_PIOA->PIO_OER = AT91C_PIO_PA16;\r
+\r
+\r
+ /* Disable pull up */\r
+ AT91C_BASE_PIOA->PIO_SODR = AT91C_PIO_PA16;\r
+} \r
+/*-----------------------------------------------------------*/\r
+\r
+static void vInitUSBInterface( void )\r
+{\r
+extern void ( vUSB_ISR )( void );\r
+\r
+ /* Create the queue used to communicate between the USB ISR and task. */\r
+ xUSBInterruptQueue = xQueueCreate( usbQUEUE_LENGTH + 1, sizeof( xISRStatus * ) );\r
+ \r
+ /* Create the queues used to hold Rx and Tx characters. */\r
+ xRxCDC = xQueueCreate( USB_CDC_QUEUE_SIZE, ( unsigned portCHAR ) sizeof( signed portCHAR ) );\r
+ xTxCDC = xQueueCreate( USB_CDC_QUEUE_SIZE + 1, ( unsigned portCHAR ) sizeof( signed portCHAR ) );\r
+\r
+ if( (!xUSBInterruptQueue) || (!xRxCDC) || (!xTxCDC) )\r
+ { \r
+ /* Not enough RAM to create queues!. */\r
+ return;\r
+ }\r
+ \r
+ /* Initialise a few state variables. */\r
+ pxControlTx.ulNextCharIndex = ( unsigned portLONG ) 0;\r
+ pxControlRx.ulNextCharIndex = ( unsigned portLONG ) 0;\r
+ ucUSBConfig = ( unsigned portCHAR ) 0;\r
+ eDriverState = eNOTHING;\r
+ ucControlState = 0;\r
+ uiCurrentBank = AT91C_UDP_RX_DATA_BK0;\r
+\r
+\r
+ /* HARDWARE SETUP */\r
+\r
+ /* Set the PLL USB Divider */\r
+ AT91C_BASE_CKGR->CKGR_PLLR |= AT91C_CKGR_USBDIV_1;\r
+\r
+ /* Enables the 48MHz USB clock UDPCK and System Peripheral USB Clock. */\r
+ AT91C_BASE_PMC->PMC_SCER = AT91C_PMC_UDP;\r
+ AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_UDP);\r
+\r
+ /* Setup the PIO for the USB pull up resistor. */\r
+ AT91C_BASE_PIOA->PIO_PER = AT91C_PIO_PA16;\r
+ AT91C_BASE_PIOA->PIO_OER = AT91C_PIO_PA16;\r
+\r
+\r
+ /* Start without the pullup - this will get set at the end of this \r
+ function. */\r
+ AT91C_BASE_PIOA->PIO_SODR = AT91C_PIO_PA16;\r
+\r
+\r
+ /* When using the USB debugger the peripheral registers do not always get\r
+ set to the correct default values. To make sure set the relevant registers\r
+ manually here. */\r
+ AT91C_BASE_UDP->UDP_IDR = ( unsigned portLONG ) 0xffffffff;\r
+ AT91C_BASE_UDP->UDP_ICR = ( unsigned portLONG ) 0xffffffff;\r
+ AT91C_BASE_UDP->UDP_CSR[ 0 ] = ( unsigned portLONG ) 0x00;\r
+ AT91C_BASE_UDP->UDP_CSR[ 1 ] = ( unsigned portLONG ) 0x00;\r
+ AT91C_BASE_UDP->UDP_CSR[ 2 ] = ( unsigned portLONG ) 0x00;\r
+ AT91C_BASE_UDP->UDP_CSR[ 3 ] = ( unsigned portLONG ) 0x00;\r
+ AT91C_BASE_UDP->UDP_GLBSTATE = 0;\r
+ AT91C_BASE_UDP->UDP_FADDR = 0;\r
+\r
+ /* Enable the transceiver. */\r
+ AT91C_UDP_TRANSCEIVER_ENABLE = 0;\r
+\r
+ /* Enable the USB interrupts - other interrupts get enabled as the \r
+ enumeration process progresses. */\r
+ AT91F_AIC_ConfigureIt( AT91C_ID_UDP, usbINTERRUPT_PRIORITY, AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, ( void (*)( void ) ) vUSB_ISR );\r
+ AT91C_BASE_AIC->AIC_IECR = 0x1 << AT91C_ID_UDP;\r
+\r
+\r
+ /* Wait a short while before making our presence known. */\r
+ vTaskDelay( usbINIT_DELAY );\r
+ AT91C_BASE_PIOA->PIO_CODR = AT91C_PIO_PA16;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSendControlData( unsigned portCHAR *pucData, unsigned portSHORT usRequestedLength, unsigned portLONG ulLengthToSend, portLONG lSendingDescriptor )\r
+{\r
+ if( ( ( unsigned portLONG ) usRequestedLength < ulLengthToSend ) )\r
+ {\r
+ /* Cap the data length to that requested. */\r
+ ulLengthToSend = ( unsigned portSHORT ) usRequestedLength;\r
+ }\r
+ else if( ( ulLengthToSend < ( unsigned portLONG ) usRequestedLength ) && lSendingDescriptor )\r
+ {\r
+ /* We are sending a descriptor. If the descriptor is an exact \r
+ multiple of the FIFO length then it will have to be terminated\r
+ with a NULL packet. Set the state to indicate this if\r
+ necessary. */\r
+ if( ( ulLengthToSend % usbFIFO_LENGTH ) == 0 )\r
+ {\r
+ eDriverState = eSENDING_EVEN_DESCRIPTOR;\r
+ }\r
+ }\r
+\r
+ /* Here we assume that the previous message has been sent. THERE IS NO\r
+ BUFFER OVERFLOW PROTECTION HERE.\r
+\r
+ Copy the data to send into the buffer as we cannot send it all at once\r
+ (if it is greater than 8 bytes in length). */\r
+ memcpy( pxControlTx.ucBuffer, pucData, ulLengthToSend );\r
+\r
+ /* Reinitialise the buffer index so we start sending from the start of \r
+ the data. */\r
+ pxControlTx.ulTotalDataLength = ulLengthToSend;\r
+ pxControlTx.ulNextCharIndex = ( unsigned portLONG ) 0;\r
+\r
+ /* Send the first 8 bytes now. The rest will get sent in response to \r
+ TXCOMP interrupts. */\r
+ prvSendNextSegment();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSendNextSegment( void )\r
+{\r
+volatile unsigned portLONG ulNextLength, ulStatus, ulLengthLeftToSend;\r
+\r
+ /* Is there any data to send? */\r
+ if( pxControlTx.ulTotalDataLength > pxControlTx.ulNextCharIndex )\r
+ {\r
+ ulLengthLeftToSend = pxControlTx.ulTotalDataLength - pxControlTx.ulNextCharIndex;\r
+ \r
+ /* We can only send 8 bytes to the fifo at a time. */\r
+ if( ulLengthLeftToSend > usbFIFO_LENGTH )\r
+ {\r
+ ulNextLength = usbFIFO_LENGTH;\r
+ }\r
+ else\r
+ {\r
+ ulNextLength = ulLengthLeftToSend;\r
+ }\r
+\r
+ /* Wait until we can place data in the fifo. THERE IS NO TIMEOUT\r
+ HERE! */\r
+ while( AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] & AT91C_UDP_TXPKTRDY )\r
+ {\r
+ vTaskDelay( usbSHORTEST_DELAY );\r
+ }\r
+\r
+ /* Write the data to the FIFO. */\r
+ while( ulNextLength > ( unsigned portLONG ) 0 )\r
+ {\r
+ AT91C_BASE_UDP->UDP_FDR[ usbEND_POINT_0 ] = pxControlTx.ucBuffer[ pxControlTx.ulNextCharIndex ];\r
+ \r
+ ulNextLength--;\r
+ pxControlTx.ulNextCharIndex++;\r
+ }\r
+ \r
+ /* Start the transmission. */\r
+ portENTER_CRITICAL();\r
+ {\r
+ ulStatus = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ];\r
+ usbCSR_SET_BIT( &ulStatus, ( ( unsigned portLONG ) 0x10 ) );\r
+ AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] = ulStatus;\r
+ }\r
+ portEXIT_CRITICAL();\r
+ }\r
+ else\r
+ {\r
+ /* There is no data to send. If we were sending a descriptor and the \r
+ descriptor was an exact multiple of the max packet size then we need\r
+ to send a null to terminate the transmission. */\r
+ if( eDriverState == eSENDING_EVEN_DESCRIPTOR )\r
+ {\r
+ prvSendZLP();\r
+ eDriverState = eNOTHING;\r
+ }\r
+ }\r
+}\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef USB_CDC_H\r
+#define USB_CDC_H\r
+\r
+#include "usb.h"\r
+\r
+#define USB_CDC_QUEUE_SIZE 200\r
+\r
+/* Structure used to take a snapshot of the USB status from within the ISR. */\r
+typedef struct X_ISR_STATUS\r
+{\r
+ unsigned portLONG ulISR;\r
+ unsigned portLONG ulCSR0;\r
+ unsigned portCHAR ucFifoData[ 8 ];\r
+} xISRStatus;\r
+\r
+/* Structure used to hold the received requests. */\r
+typedef struct \r
+{\r
+ unsigned portCHAR ucReqType;\r
+ unsigned portCHAR ucRequest;\r
+ unsigned portSHORT usValue;\r
+ unsigned portSHORT usIndex;\r
+ unsigned portSHORT usLength;\r
+} xUSB_REQUEST;\r
+\r
+typedef enum\r
+{\r
+ eNOTHING,\r
+ eJUST_RESET,\r
+ eJUST_GOT_CONFIG,\r
+ eJUST_GOT_ADDRESS,\r
+ eSENDING_EVEN_DESCRIPTOR,\r
+ eREADY_TO_SEND\r
+} eDRIVER_STATE;\r
+\r
+/* Structure used to control the data being sent to the host. */\r
+typedef struct\r
+{\r
+ unsigned portCHAR ucBuffer[ usbMAX_CONTROL_MESSAGE_SIZE ];\r
+ unsigned portLONG ulNextCharIndex;\r
+ unsigned portLONG ulTotalDataLength;\r
+} xCONTROL_MESSAGE;\r
+\r
+/*-----------------------------------------------------------*/\r
+void vUSBCDCTask( void *pvParameters );\r
+\r
+/* Send cByte down the USB port. Characters are simply buffered and not\r
+sent unless the port is connected. */\r
+void vUSBSendByte( portCHAR cByte );\r
+\r
+\r
+#endif\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+\r
+/* \r
+ BASIC INTERRUPT DRIVEN DRIVER FOR USB. \r
+\r
+ This file contains all the usb components that must be compiled\r
+ to ARM mode. The components that can be compiled to either ARM or THUMB\r
+ mode are contained in USB-CDC.c.\r
+\r
+*/\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+\r
+/* Demo application includes. */\r
+#include "Board.h"\r
+#include "usb.h"\r
+#include "USB-CDC.h"\r
+\r
+#define usbINT_CLEAR_MASK (AT91C_UDP_TXCOMP | AT91C_UDP_STALLSENT | AT91C_UDP_RXSETUP | AT91C_UDP_RX_DATA_BK0 | AT91C_UDP_RX_DATA_BK1 )\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Messages and queue used to communicate between the ISR and the USB task. */\r
+static xISRStatus xISRMessages[ usbQUEUE_LENGTH + 1 ];\r
+extern xQueueHandle xUSBInterruptQueue;\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The ISR can cause a context switch so is declared naked. */\r
+void vUSB_ISR( void ) __attribute__ ((naked));\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+void vUSB_ISR( void )\r
+{\r
+ /* This ISR can cause a context switch. Therefore a call to the \r
+ portENTER_SWITCHING_ISR() macro is made. This must come BEFORE any \r
+ stack variable declarations. */\r
+ portENTER_SWITCHING_ISR();\r
+\r
+ /* Now variables can be declared. */\r
+ portCHAR cTaskWokenByPost = pdFALSE; \r
+ static volatile unsigned portLONG ulNextMessage = 0;\r
+ xISRStatus *pxMessage;\r
+ unsigned portLONG ulRxBytes;\r
+ unsigned portCHAR ucFifoIndex;\r
+\r
+ /* Use the next message from the array. */\r
+ pxMessage = &( xISRMessages[ ( ulNextMessage & usbQUEUE_LENGTH ) ] );\r
+ ulNextMessage++;\r
+\r
+ /* Save UDP ISR state for task-level processing. */\r
+ pxMessage->ulISR = AT91C_BASE_UDP->UDP_ISR;\r
+ pxMessage->ulCSR0 = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ];\r
+\r
+ /* Clear interrupts from ICR. */\r
+ AT91C_BASE_UDP->UDP_ICR = AT91C_BASE_UDP->UDP_IMR | AT91C_UDP_ENDBUSRES;\r
+ \r
+ \r
+ /* Process incoming FIFO data. Must set DIR (if needed) and clear RXSETUP \r
+ before exit. */\r
+\r
+ /* Read CSR and get incoming byte count. */\r
+ ulRxBytes = ( pxMessage->ulCSR0 >> 16 ) & usbRX_COUNT_MASK;\r
+ \r
+ /* Receive control transfers on endpoint 0. */\r
+ if( pxMessage->ulCSR0 & ( AT91C_UDP_RXSETUP | AT91C_UDP_RX_DATA_BK0 ) )\r
+ {\r
+ /* Save FIFO data buffer for either a SETUP or DATA stage */\r
+ for( ucFifoIndex = 0; ucFifoIndex < ulRxBytes; ucFifoIndex++ )\r
+ {\r
+ pxMessage->ucFifoData[ ucFifoIndex ] = AT91C_BASE_UDP->UDP_FDR[ usbEND_POINT_0 ];\r
+ }\r
+\r
+ /* Set direction for data stage. Must be done before RXSETUP is \r
+ cleared. */\r
+ if( ( AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] & AT91C_UDP_RXSETUP ) )\r
+ {\r
+ if( ulRxBytes && ( pxMessage->ucFifoData[ usbREQUEST_TYPE_INDEX ] & 0x80 ) )\r
+ {\r
+ AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] |= AT91C_UDP_DIR;\r
+\r
+ /* Might not be wise in an ISR! */\r
+ while( !(AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] & AT91C_UDP_DIR) );\r
+ }\r
+\r
+ /* Clear RXSETUP */\r
+ AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] &= ~AT91C_UDP_RXSETUP;\r
+\r
+ /* Might not be wise in an ISR! */\r
+ while ( AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] & AT91C_UDP_RXSETUP );\r
+ }\r
+ else\r
+ {\r
+ /* Clear RX_DATA_BK0 */\r
+ AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] &= ~AT91C_UDP_RX_DATA_BK0;\r
+\r
+ /* Might not be wise in an ISR! */\r
+ while ( AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] & AT91C_UDP_RX_DATA_BK0 );\r
+ }\r
+ }\r
+ \r
+ /* If we received data on endpoint 1, disable its interrupts until it is \r
+ processed in the main loop */\r
+ if( AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ] & ( AT91C_UDP_RX_DATA_BK0 | AT91C_UDP_RX_DATA_BK1 ) )\r
+ {\r
+ AT91C_BASE_UDP->UDP_IDR = AT91C_UDP_EPINT1;\r
+ }\r
+ \r
+ AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] &= ~( AT91C_UDP_TXCOMP | AT91C_UDP_STALLSENT );\r
+ \r
+ /* Clear interrupts for the other endpoints, retain data flags for endpoint \r
+ 1. */\r
+ AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ] &= ~( AT91C_UDP_TXCOMP | AT91C_UDP_STALLSENT | AT91C_UDP_RXSETUP );\r
+ AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_2 ] &= ~usbINT_CLEAR_MASK;\r
+ AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_3 ] &= ~usbINT_CLEAR_MASK;\r
+\r
+ /* Post ISR data to queue for task-level processing */\r
+ cTaskWokenByPost = xQueueSendFromISR( xUSBInterruptQueue, &pxMessage, cTaskWokenByPost );\r
+\r
+ /* Clear AIC to complete ISR processing */\r
+ AT91C_BASE_AIC->AIC_EOICR = 0;\r
+\r
+ /* Do a task switch if needed */\r
+ portEXIT_SWITCHING_ISR( cTaskWokenByPost )\r
+}\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+ - DESCRIPTOR DEFINITIONS -\r
+*/\r
+\r
+/* String descriptors used during the enumeration process.\r
+These take the form:\r
+\r
+{\r
+ Length of descriptor,\r
+ Descriptor type,\r
+ Data\r
+}\r
+*/\r
+\r
+const portCHAR pxLanguageStringDescriptor[] =\r
+{\r
+ 4,\r
+ usbDESCRIPTOR_TYPE_STRING,\r
+ 0x09, 0x04\r
+};\r
+\r
+const portCHAR pxManufacturerStringDescriptor[] = \r
+{\r
+ 18,\r
+ usbDESCRIPTOR_TYPE_STRING,\r
+\r
+ 'F', 0x00, 'r', 0x00, 'e', 0x00, 'e', 0x00, 'R', 0x00, 'T', 0x00, 'O', 0x00, 'S', 0x00\r
+};\r
+\r
+const portCHAR pxProductStringDescriptor[] = \r
+{\r
+ 36,\r
+ usbDESCRIPTOR_TYPE_STRING,\r
+\r
+ 'F', 0x00, 'r', 0x00, 'e', 0x00, 'e', 0x00, 'R', 0x00, 'T', 0x00, 'O', 0x00, 'S', 0x00, ' ', 0x00, 'C', 0x00, 'D', 0x00,\r
+ 'C', 0x00, ' ', 0x00, 'D', 0x00, 'E', 0x00, 'M', 0x00, 'O', 0x00\r
+};\r
+\r
+const portCHAR pxConfigurationStringDescriptor[] = \r
+{\r
+ 38,\r
+ usbDESCRIPTOR_TYPE_STRING,\r
+\r
+ 'C', 0x00, 'o', 0x00, 'n', 0x00, 'f', 0x00, 'i', 0x00, 'g', 0x00, 'u', 0x00, 'r', 0x00, 'a', 0x00, 't', 0x00, 'i', 0x00,\r
+ 'o', 0x00, 'n', 0x00, ' ', 0x00, 'N', 0x00, 'a', 0x00, 'm', 0x00, 'e', 0x00\r
+};\r
+\r
+const portCHAR pxInterfaceStringDescriptor[] = \r
+{\r
+ 30,\r
+ usbDESCRIPTOR_TYPE_STRING,\r
+\r
+ 'I', 0x00, 'n', 0x00, 't', 0x00, 'e', 0x00, 'r', 0x00, 'f', 0x00, 'a', 0x00, 'c', 0x00, 'e', 0x00, ' ', 0x00, 'N', 0x00,\r
+ 'a', 0x00, 'm', 0x00, 'e', 0x00\r
+};\r
+\r
+/* Device should properly be 0x134A:0x9001, using 0x05F9:0xFFFF for Linux testing */\r
+const char pxDeviceDescriptor[] = \r
+{\r
+ /* Device descriptor */\r
+ 0x12, /* bLength */\r
+ 0x01, /* bDescriptorType */\r
+ 0x10, 0x01, /* bcdUSBL */\r
+ 0x02, /* bDeviceClass: */\r
+ 0x00, /* bDeviceSubclass: */\r
+ 0x00, /* bDeviceProtocol: */\r
+ 0x08, /* bMaxPacketSize0 */\r
+ 0x03, 0xEB, /* idVendorL */\r
+ 0x20, 0x09, /* idProductL */\r
+ 0x10, 0x01, /* bcdDeviceL */\r
+ usbMANUFACTURER_STRING, /* iManufacturer */\r
+ usbPRODUCT_STRING, /* iProduct */\r
+ 0x00, /* SerialNumber */\r
+ 0x01 /* bNumConfigs */\r
+};\r
+\r
+const char pxConfigDescriptor[] = {\r
+\r
+ /* Configuration 1 descriptor\r
+ Here we define two interfaces (0 and 1) and a total of 3 endpoints.\r
+ Interface 0 is a CDC Abstract Control Model interface with one interrupt-in endpoint.\r
+ Interface 1 is a CDC Data Interface class, with a bulk-in and bulk-out endpoint.\r
+ Endpoint 0 gets used as the CDC management element.\r
+ */\r
+ 0x09, /* CbLength */\r
+ 0x02, /* CbDescriptorType */\r
+ 0x43, 0x00, /* CwTotalLength 2 EP + Control ? */\r
+ 0x02, /* CbNumInterfaces */\r
+ 0x01, /* CbConfigurationValue */\r
+ usbCONFIGURATION_STRING,/* CiConfiguration */\r
+ usbBUS_POWERED, /* CbmAttributes Bus powered + Remote Wakeup*/\r
+ 0x32, /* CMaxPower: 100mA */\r
+\r
+ /* Communication Class Interface Descriptor Requirement */\r
+ 0x09, /* bLength */\r
+ 0x04, /* bDescriptorType */\r
+ 0x00, /* bInterfaceNumber */\r
+ 0x00, /* bAlternateSetting */\r
+ 0x01, /* bNumEndpoints */\r
+ 0x02, /* bInterfaceClass: Comm Interface Class */\r
+ 0x02, /* bInterfaceSubclass: Abstract Control Model*/\r
+ 0x00, /* bInterfaceProtocol */\r
+ usbINTERFACE_STRING,/* iInterface */\r
+\r
+ /* Header Functional Descriptor */\r
+ 0x05, /* bLength */\r
+ 0x24, /* bDescriptor type: CS_INTERFACE */\r
+ 0x00, /* bDescriptor subtype: Header Func Desc*/\r
+ 0x10, 0x01, /* bcdCDC:1.1 */\r
+\r
+ /* ACM Functional Descriptor */\r
+ 0x04, /* bFunctionLength */\r
+ 0x24, /* bDescriptor type: CS_INTERFACE */\r
+ 0x02, /* bDescriptor subtype: ACM Func Desc */\r
+ 0x00, /* bmCapabilities: We don't support squat*/\r
+\r
+ /* Union Functional Descriptor */\r
+ 0x05, /* bFunctionLength */\r
+ 0x24, /* bDescriptor type: CS_INTERFACE */\r
+ 0x06, /* bDescriptor subtype: Union Func Desc */\r
+ 0x00, /* bMasterInterface: CDC Interface */\r
+ 0x01, /* bSlaveInterface0: Data Class Interface*/\r
+\r
+ /* Call Management Functional Descriptor\r
+ 0 in D1 and D0 indicates that device does not handle call management*/\r
+ 0x05, /* bFunctionLength */\r
+ 0x24, /* bDescriptor type: CS_INTERFACE */\r
+ 0x01, /* bDescriptor subtype: Call Management Func*/\r
+ 0x00, /* bmCapabilities: D1 + D0 */\r
+ 0x01, /* bDataInterface: Data Class Interface 1*/\r
+\r
+ /* CDC Control - Endpoint 3 descriptor\r
+ This endpoint serves as a notification element. */\r
+\r
+ 0x07, /* bLength */\r
+ 0x05, /* bDescriptorType */\r
+ 0x83, /* bEndpointAddress, Endpoint 03 - IN */\r
+ 0x03, /* bmAttributes INT */\r
+ 0x08, 0x00, /* wMaxPacketSize: 8 bytes */\r
+ 0xFF, /* bInterval */\r
+\r
+ /* Data Class Interface Descriptor Requirement */\r
+ 0x09, /* bLength */\r
+ 0x04, /* bDescriptorType */\r
+ 0x01, /* bInterfaceNumber */\r
+ 0x00, /* bAlternateSetting */\r
+ 0x02, /* bNumEndPoints */\r
+ 0x0A, /* bInterfaceClass */\r
+ 0x00, /* bInterfaceSubclass */\r
+ 0x00, /* bInterfaceProtocol */\r
+ 0x00, /* iInterface */\r
+\r
+ /* CDC Data - Endpoint 1 descriptor */\r
+ 0x07, /* bLenght */\r
+ 0x05, /* bDescriptorType */\r
+ 0x01, /* bEndPointAddress, Endpoint 01 - OUT */\r
+ 0x02, /* bmAttributes BULK */\r
+ 64, /* wMaxPacketSize */\r
+ 0x00,\r
+ 0x00, /* bInterval */\r
+\r
+ /* CDC Data - Endpoint 2 descriptor */\r
+ 0x07, /* bLength */\r
+ 0x05, /* bDescriptorType */\r
+ 0x82, /* bEndPointAddress, Endpoint 02 - IN */\r
+ 0x02, /* bmAttributes BULK */\r
+ 64, /* wMaxPacketSize */\r
+ 0x00,\r
+ 0x00 /* bInterval */\r
+};\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* Descriptor type definitions. */\r
+#define usbDESCRIPTOR_TYPE_DEVICE ( 0x01 )\r
+#define usbDESCRIPTOR_TYPE_CONFIGURATION ( 0x02 )\r
+#define usbDESCRIPTOR_TYPE_STRING ( 0x03 )\r
+\r
+/* USB request type definitions. */\r
+#define usbGET_REPORT_REQUEST ( 0x01 )\r
+#define usbGET_IDLE_REQUEST ( 0x02 )\r
+#define usbGET_PROTOCOL_REQUEST ( 0x03 )\r
+#define usbSET_REPORT_REQUEST ( 0x09 )\r
+#define usbSET_IDLE_REQUEST ( 0x0A )\r
+#define usbSET_PROTOCOL_REQUEST ( 0x0B )\r
+#define usbGET_CONFIGURATION_REQUEST ( 0x08 )\r
+#define usbGET_STATUS_REQUEST ( 0x00 )\r
+#define usbCLEAR_FEATURE_REQUEST ( 0x01 )\r
+#define usbSET_FEATURE_REQUEST ( 0x03 )\r
+#define usbSET_ADDRESS_REQUEST ( 0x05 )\r
+#define usbGET_DESCRIPTOR_REQUEST ( 0x06 )\r
+#define usbSET_CONFIGURATION_REQUEST ( 0x09 )\r
+#define usbGET_INTERFACE_REQUEST ( 0x0A )\r
+#define usbSET_INTERFACE_REQUEST ( 0x0B )\r
+\r
+/* ACM Requests */\r
+#define usbSEND_ENCAPSULATED_COMMAND ( 0x00 )\r
+#define usbGET_ENCAPSULATED_RESPONSE ( 0x01 )\r
+#define usbSET_LINE_CODING ( 0x20 )\r
+#define usbGET_LINE_CODING ( 0x21 )\r
+#define usbSET_CONTROL_LINE_STATE ( 0x22 )\r
+\r
+/* Misc USB definitions. */\r
+#define usbDEVICE_CLASS_VENDOR_SPECIFIC ( 0xFF )\r
+#define usbBUS_POWERED ( 0x80 )\r
+#define usbHID_REPORT_DESCRIPTOR ( 0x22 )\r
+#define AT91C_UDP_TRANSCEIVER_ENABLE ( *( ( unsigned long * ) 0xfffb0074 ) )\r
+\r
+/* Index to the various string. */\r
+#define usbLANGUAGE_STRING ( 0 )\r
+#define usbMANUFACTURER_STRING ( 1 )\r
+#define usbPRODUCT_STRING ( 2 )\r
+#define usbCONFIGURATION_STRING ( 3 )\r
+#define usbINTERFACE_STRING ( 4 )\r
+\r
+/* Defines fields of standard SETUP request. Now in normal order. */\r
+#define usbREQUEST_TYPE_INDEX ( 0 )\r
+#define usbREQUEST_INDEX ( 1 )\r
+#define usbVALUE_HIGH_BYTE ( 3 )\r
+#define usbVALUE_LOW_BYTE ( 2 )\r
+#define usbINDEX_HIGH_BYTE ( 5 )\r
+#define usbINDEX_LOW_BYTE ( 4 )\r
+#define usbLENGTH_HIGH_BYTE ( 7 )\r
+#define usbLENGTH_LOW_BYTE ( 6 )\r
+\r
+/* Misc application definitions. */\r
+#define usbINTERRUPT_PRIORITY ( 3 )\r
+#define usbQUEUE_LENGTH ( 0x3 ) /* Must have all bits set! */\r
+#define usbFIFO_LENGTH ( ( unsigned portLONG ) 8 )\r
+#define usbEND_POINT_0 ( 0 )\r
+#define usbEND_POINT_1 ( 1 )\r
+#define usbEND_POINT_2 ( 2 )\r
+#define usbEND_POINT_3 ( 3 )\r
+#define usbMAX_CONTROL_MESSAGE_SIZE ( 128 )\r
+#define usbRX_COUNT_MASK ( ( unsigned portLONG ) 0x7ff )\r
+#define AT91C_UDP_STALLSENT AT91C_UDP_ISOERROR\r
+#define usbSHORTEST_DELAY ( ( portTickType ) 1 )\r
+#define usbINIT_DELAY ( ( portTickType ) 1000 / portTICK_RATE_MS )\r
+#define usbSHORT_DELAY ( ( portTickType ) 50 / portTICK_RATE_MS )\r
+#define usbEND_POINT_RESET_MASK ( ( unsigned portLONG ) 0x0f )\r
+#define usbDATA_INC ( ( portCHAR ) 5 )\r
+#define usbEXPECTED_NUMBER_OF_BYTES ( ( unsigned portLONG ) 8 )\r
+\r
+/* Control request types. */\r
+#define usbSTANDARD_DEVICE_REQUEST ( 0 )\r
+#define usbSTANDARD_INTERFACE_REQUEST ( 1 )\r
+#define usbSTANDARD_END_POINT_REQUEST ( 2 )\r
+#define usbCLASS_INTERFACE_REQUEST ( 5 )\r
+\r
+\r
+/* Macros to manipulate the control and status registers. These registers \r
+cannot be accessed using a direct read modify write operation outside of the \r
+ISR as some bits are left unchanged by writing with a 0, and some are left \r
+unchanged by writing with a 1. */\r
+\r
+\r
+#define usbCSR_SET_BIT( pulValueNow, ulBit ) \\r
+{ \\r
+ /* Set TXCOMP, RX_DATA_BK0, RXSETUP, */ \\r
+ /* STALLSENT and RX_DATA_BK1 to 1 so the */ \\r
+ /* write has no effect. */ \\r
+ ( * ( ( unsigned portLONG * ) pulValueNow ) ) |= ( unsigned portLONG ) 0x4f; \\r
+ \\r
+ /* Clear the FORCE_STALL and TXPKTRDY bits */ \\r
+ /* so the write has no effect. */ \\r
+ ( * ( ( unsigned portLONG * ) pulValueNow ) ) &= ( unsigned portLONG ) 0xffffffcf; \\r
+ \\r
+ /* Set whichever bit we want set. */ \\r
+ ( * ( ( unsigned portLONG * ) pulValueNow ) ) |= ( ulBit ); \\r
+}\r
+\r
+#define usbCSR_CLEAR_BIT( pulValueNow, ulBit ) \\r
+{ \\r
+ /* Set TXCOMP, RX_DATA_BK0, RXSETUP, */ \\r
+ /* STALLSENT and RX_DATA_BK1 to 1 so the */ \\r
+ /* write has no effect. */ \\r
+ ( * ( ( unsigned portLONG * ) pulValueNow ) ) |= ( unsigned portLONG ) 0x4f; \\r
+ \\r
+ /* Clear the FORCE_STALL and TXPKTRDY bits */ \\r
+ /* so the write has no effect. */ \\r
+ ( * ( ( unsigned portLONG * ) pulValueNow ) ) &= ( unsigned portLONG ) 0xffffffcf; \\r
+ \\r
+ /* Clear whichever bit we want clear. */ \\r
+ ( * ( ( unsigned portLONG * ) pulValueNow ) ) &= ( ~ulBit ); \\r
+}\r
--- /dev/null
+MEMORY \r
+{\r
+ flash : ORIGIN = 0x00100000, LENGTH = 256K\r
+ ram : ORIGIN = 0x00200000, LENGTH = 64K\r
+}\r
+\r
+__stack_end__ = 0x00200000 + 64K - 4;\r
+\r
+SECTIONS \r
+{\r
+ . = 0;\r
+ startup : { *(.startup)} >flash\r
+\r
+ prog : \r
+ {\r
+ *(.text)\r
+ *(.rodata)\r
+ *(.rodata*)\r
+ *(.glue_7)\r
+ *(.glue_7t)\r
+ } >flash\r
+\r
+ __end_of_text__ = .;\r
+\r
+ .data : \r
+ {\r
+ __data_beg__ = .;\r
+ __data_beg_src__ = __end_of_text__;\r
+ *(.data)\r
+ __data_end__ = .;\r
+ } >ram AT>flash\r
+\r
+ .bss : \r
+ {\r
+ __bss_beg__ = .;\r
+ *(.bss)\r
+ } >ram\r
+\r
+ /* Align here to ensure that the .bss section occupies space up to\r
+ _end. Align after .bss to ensure correct alignment even if the\r
+ .bss section disappears because there are no input sections. */\r
+ . = ALIGN(32 / 8);\r
+}\r
+ . = ALIGN(32 / 8);\r
+ _end = .;\r
+ _bss_end__ = . ; __bss_end__ = . ; __end__ = . ;\r
+ PROVIDE (end = .);\r
+\r
+\r
--- /dev/null
+ /* Sample initialization file */\r
+\r
+ .extern main\r
+ .extern exit\r
+ .extern AT91F_LowLevelInit\r
+\r
+ .text\r
+ .code 32\r
+\r
+\r
+ .align 0\r
+\r
+ .extern __stack_end__\r
+ .extern __bss_beg__\r
+ .extern __bss_end__\r
+ .extern __data_beg__\r
+ .extern __data_end__\r
+ .extern __data+beg_src__\r
+\r
+ .global start\r
+ .global endless_loop\r
+\r
+ /* Stack Sizes */\r
+ .set UND_STACK_SIZE, 0x00000004\r
+ .set ABT_STACK_SIZE, 0x00000004\r
+ .set FIQ_STACK_SIZE, 0x00000004\r
+ .set IRQ_STACK_SIZE, 0X00000400\r
+ .set SVC_STACK_SIZE, 0x00000400\r
+\r
+ /* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */\r
+ .set MODE_USR, 0x10 /* User Mode */\r
+ .set MODE_FIQ, 0x11 /* FIQ Mode */\r
+ .set MODE_IRQ, 0x12 /* IRQ Mode */\r
+ .set MODE_SVC, 0x13 /* Supervisor Mode */\r
+ .set MODE_ABT, 0x17 /* Abort Mode */\r
+ .set MODE_UND, 0x1B /* Undefined Mode */\r
+ .set MODE_SYS, 0x1F /* System Mode */\r
+\r
+ .equ I_BIT, 0x80 /* when I bit is set, IRQ is disabled */\r
+ .equ F_BIT, 0x40 /* when F bit is set, FIQ is disabled */\r
+\r
+\r
+start:\r
+_start:\r
+_mainCRTStartup:\r
+\r
+ /* Setup a stack for each mode - note that this only sets up a usable stack\r
+ for system/user, SWI and IRQ modes. Also each mode is setup with\r
+ interrupts initially disabled. */\r
+ ldr r0, .LC6\r
+ msr CPSR_c, #MODE_UND|I_BIT|F_BIT /* Undefined Instruction Mode */\r
+ mov sp, r0\r
+ sub r0, r0, #UND_STACK_SIZE\r
+ msr CPSR_c, #MODE_ABT|I_BIT|F_BIT /* Abort Mode */\r
+ mov sp, r0\r
+ sub r0, r0, #ABT_STACK_SIZE\r
+ msr CPSR_c, #MODE_FIQ|I_BIT|F_BIT /* FIQ Mode */\r
+ mov sp, r0\r
+ sub r0, r0, #FIQ_STACK_SIZE\r
+ msr CPSR_c, #MODE_IRQ|I_BIT|F_BIT /* IRQ Mode */\r
+ mov sp, r0\r
+ sub r0, r0, #IRQ_STACK_SIZE\r
+ msr CPSR_c, #MODE_SVC|I_BIT|F_BIT /* Supervisor Mode */\r
+ mov sp, r0\r
+ sub r0, r0, #SVC_STACK_SIZE\r
+ msr CPSR_c, #MODE_SYS|I_BIT|F_BIT /* System Mode */\r
+ mov sp, r0\r
+\r
+ /* We want to start in supervisor mode. Operation will switch to system\r
+ mode when the first task starts. */\r
+ msr CPSR_c, #MODE_SVC|I_BIT|F_BIT\r
+\r
+ bl AT91F_LowLevelInit\r
+\r
+ /* Clear BSS. */\r
+\r
+ mov a2, #0 /* Fill value */\r
+ mov fp, a2 /* Null frame pointer */\r
+ mov r7, a2 /* Null frame pointer for Thumb */\r
+\r
+ ldr r1, .LC1 /* Start of memory block */\r
+ ldr r3, .LC2 /* End of memory block */\r
+ subs r3, r3, r1 /* Length of block */\r
+ beq .end_clear_loop\r
+ mov r2, #0\r
+\r
+.clear_loop:\r
+ strb r2, [r1], #1\r
+ subs r3, r3, #1\r
+ bgt .clear_loop\r
+\r
+.end_clear_loop:\r
+\r
+ /* Initialise data. */\r
+\r
+ ldr r1, .LC3 /* Start of memory block */\r
+ ldr r2, .LC4 /* End of memory block */\r
+ ldr r3, .LC5\r
+ subs r3, r3, r1 /* Length of block */\r
+ beq .end_set_loop\r
+\r
+.set_loop:\r
+ ldrb r4, [r2], #1\r
+ strb r4, [r1], #1\r
+ subs r3, r3, #1\r
+ bgt .set_loop\r
+\r
+.end_set_loop:\r
+\r
+ mov r0, #0 /* no arguments */\r
+ mov r1, #0 /* no argv either */\r
+\r
+ ldr lr, =main \r
+ bx lr\r
+\r
+endless_loop:\r
+ b endless_loop\r
+\r
+\r
+ .align 0\r
+\r
+ .LC1:\r
+ .word __bss_beg__\r
+ .LC2:\r
+ .word __bss_end__\r
+ .LC3:\r
+ .word __data_beg__\r
+ .LC4:\r
+ .word __data_beg_src__\r
+ .LC5:\r
+ .word __data_end__\r
+ .LC6:\r
+ .word __stack_end__\r
+\r
+\r
+ /* Setup vector table. Note that undf, pabt, dabt, fiq just execute\r
+ a null loop. */\r
+\r
+.section .startup,"ax"\r
+ .code 32\r
+ .align 0\r
+\r
+ b _start /* reset - _start */\r
+ ldr pc, _undf /* undefined - _undf */\r
+ ldr pc, _swi /* SWI - _swi */\r
+ ldr pc, _pabt /* program abort - _pabt */\r
+ ldr pc, _dabt /* data abort - _dabt */\r
+ nop /* reserved */\r
+ ldr pc, [pc,#-0xF20] /* IRQ - read the AIC */\r
+ ldr pc, _fiq /* FIQ - _fiq */\r
+\r
+_undf: .word __undf /* undefined */\r
+_swi: .word swi_handler /* SWI */\r
+_pabt: .word __pabt /* program abort */\r
+_dabt: .word __dabt /* data abort */\r
+_fiq: .word __fiq /* FIQ */\r
+\r
+__undf: b . /* undefined */\r
+__pabt: b . /* program abort */\r
+__dabt: b . /* data abort */\r
+__fiq: b . /* FIQ */\r
--- /dev/null
+/*****************************************************************************\r
+ * Copyright (c) 2001, 2002 Rowley Associates Limited. *\r
+ * *\r
+ * This file may be distributed under the terms of the License Agreement *\r
+ * provided with this software. *\r
+ * *\r
+ * THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE *\r
+ * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *\r
+ *****************************************************************************/\r
+ .section .init, "ax"\r
+ .code 32\r
+ .align 0\r
+ \r
+ .weak _start\r
+ .global __start\r
+ .global __gccmain\r
+ .extern main\r
+ .extern exit\r
+\r
+/*****************************************************************************\r
+ * Function : _start *\r
+ * Description : Main entry point and startup code for C system. *\r
+ *****************************************************************************/\r
+_start:\r
+__start: \r
+ mrs r0, cpsr\r
+ bic r0, r0, #0x1F\r
+\r
+ /* Setup stacks */ \r
+ orr r1, r0, #0x1B /* Undefined mode */\r
+ msr cpsr_cxsf, r1\r
+ ldr sp, =__stack_und_end__\r
+ \r
+ orr r1, r0, #0x17 /* Abort mode */\r
+ msr cpsr_cxsf, r1\r
+ ldr sp, =__stack_abt_end__\r
+\r
+ orr r1, r0, #0x12 /* IRQ mode */\r
+ msr cpsr_cxsf, r1\r
+ ldr sp, =__stack_irq_end__\r
+\r
+ orr r1, r0, #0x11 /* FIQ mode */\r
+ msr cpsr_cxsf, r1\r
+ ldr sp, =__stack_fiq_end__\r
+\r
+ orr r1, r0, #0x13 /* Supervisor mode */\r
+ msr cpsr_cxsf, r1\r
+ ldr sp, =__stack_svc_end__\r
+#ifdef SUPERVISOR_START\r
+ /* Start application in supervisor mode */\r
+ ldr r1, =__stack_end__ /* Setup user/system mode stack */ \r
+ mov r2, sp\r
+ stmfd r2!, {r1}\r
+ ldmfd r2, {sp}^\r
+#else\r
+ /* Start application in system mode */\r
+ orr r1, r0, #0x1F /* System mode */\r
+ msr cpsr_cxsf, r1\r
+ ldr sp, =__stack_end__\r
+#endif\r
+ \r
+ /* Copy from initialised data section to data section (if necessary). */\r
+ ldr r0, =__data_load_start__\r
+ ldr r1, =__data_start__\r
+ cmp r0, r1\r
+ beq copy_data_end\r
+ \r
+ ldr r2, =__data_end__\r
+ subs r2, r2, r1\r
+ beq copy_data_end\r
+ \r
+copy_data_loop:\r
+ ldrb r3, [r0], #+1\r
+ strb r3, [r1], #+1\r
+ subs r2, r2, #1\r
+ bne copy_data_loop\r
+copy_data_end: \r
+\r
+ /* Copy from initialised text section to text section (if necessary). */\r
+ ldr r0, =__text_load_start__\r
+ ldr r1, =__text_start__\r
+ cmp r0, r1\r
+ beq copy_text_end\r
+ \r
+ ldr r2, =__text_end__\r
+ subs r2, r2, r1\r
+ beq copy_text_end\r
+ \r
+copy_text_loop:\r
+ ldrb r3, [r0], #+1\r
+ strb r3, [r1], #+1\r
+ subs r2, r2, #1\r
+ bne copy_text_loop\r
+copy_text_end: \r
+\r
+ /* Copy from initialised fast_text section to fast_text section (if necessary). */\r
+ ldr r0, =__fast_load_start__\r
+ ldr r1, =__fast_start__\r
+ cmp r0, r1\r
+ beq copy_fast_end\r
+ \r
+ ldr r2, =__fast_end__\r
+ subs r2, r2, r1\r
+ beq copy_fast_end\r
+ \r
+copy_fast_loop:\r
+ ldrb r3, [r0], #+1\r
+ strb r3, [r1], #+1\r
+ subs r2, r2, #1\r
+ bne copy_fast_loop\r
+copy_fast_end: \r
+\r
+ /* Zero the bss. */\r
+ ldr r0, =__bss_start__\r
+ ldr r1, =__bss_end__\r
+ mov r2, #0\r
+zero_bss_loop:\r
+ cmp r0, r1\r
+ beq zero_bss_end\r
+ strb r2, [r0], #+1\r
+ b zero_bss_loop\r
+zero_bss_end: \r
+\r
+#ifdef CHECK \r
+ /* Check data */\r
+ ldr r0, =__data_load_start__\r
+ ldr r1, =__data_start__\r
+ cmp r0, r1\r
+ beq check_data_end\r
+ ldr r2, =__data_end__\r
+ subs r2, r2, r1\r
+ beq check_data_end\r
+ \r
+check_data_loop:\r
+ ldrb r3, [r0], #+1\r
+ ldrb r4, [r1], #+1\r
+ cmp r3, r4\r
+ bne data_error_loop\r
+ subs r2, r2, #1\r
+ bne check_data_loop\r
+check_data_end: \r
+\r
+ /* Check text */\r
+ ldr r0, =__text_load_start__\r
+ ldr r1, =__text_start__\r
+ cmp r0, r1\r
+ beq check_text_end\r
+ ldr r2, =__text_end__\r
+ subs r2, r2, r1\r
+ beq check_text_end\r
+ \r
+check_text_loop:\r
+ ldrb r3, [r0], #+1\r
+ ldrb r4, [r1], #+1\r
+ cmp r3, r4\r
+ bne text_error_loop\r
+ subs r2, r2, #1\r
+ bne check_text_loop\r
+check_text_end: \r
+\r
+ /* Check fast */\r
+ ldr r0, =__fast_load_start__\r
+ ldr r1, =__fast_start__\r
+ cmp r0, r1\r
+ beq check_fast_end\r
+ ldr r2, =__fast_end__\r
+ subs r2, r2, r1\r
+ beq check_fast_end\r
+ \r
+check_fast_loop:\r
+ ldrb r3, [r0], #+1\r
+ ldrb r4, [r1], #+1\r
+ cmp r3, r4\r
+ bne fast_error_loop\r
+ subs r2, r2, #1\r
+ bne check_fast_loop\r
+check_fast_end: \r
+\r
+ /* Check bss */\r
+ ldr r0, =__bss_start__\r
+ ldr r1, =__bss_end__\r
+ mov r2, #0\r
+check_bss_loop:\r
+ cmp r0, r1\r
+ beq check_bss_end\r
+ ldrb r2, [r0], #+1\r
+ cmp r2, #0\r
+ bne bss_error_loop \r
+ b check_bss_loop\r
+check_bss_end: \r
+#endif\r
+\r
+ /* Initialise the heap */\r
+ ldr r0, = __heap_start__\r
+ ldr r1, = __heap_end__\r
+ sub r1, r1, r0 /* r1 = r1-r0 */ \r
+ mov r2, #0\r
+ str r2, [r0], #+4 /* *r0++ = 0 */\r
+ str r1, [r0] /* *r0 = __heap_end__ - __heap_start__ */\r
+\r
+ /* Call constructors */\r
+ ldr r0, =__ctors_start__\r
+ ldr r1, =__ctors_end__\r
+ctor_loop:\r
+ cmp r0, r1\r
+ beq ctor_end\r
+ ldr r2, [r0], #+4\r
+ stmfd sp!, {r0-r1}\r
+ mov lr, pc\r
+ mov pc, r2\r
+ ldmfd sp!, {r0-r1}\r
+ b ctor_loop\r
+ctor_end:\r
+\r
+ /* Setup initial call frame */\r
+ mov lr, #4\r
+ mov r12, sp\r
+ stmfd sp!, {r11-r12, lr-pc}\r
+ sub r11, r12, #0x00000004\r
+\r
+start:\r
+ /* Jump to main entry point */\r
+ mov r0, #0\r
+ mov r1, #0\r
+ ldr r2, =main\r
+ mov lr, pc\r
+#ifdef __ARM_ARCH_3__\r
+ mov pc, r2\r
+#else \r
+ bx r2\r
+#endif\r
+\r
+ /* Call destructors */\r
+ ldr r0, =__dtors_start__\r
+ ldr r1, =__dtors_end__\r
+dtor_loop:\r
+ cmp r0, r1\r
+ beq dtor_end\r
+ ldr r2, [r0], #+4\r
+ stmfd sp!, {r0-r1}\r
+ mov lr, pc\r
+ mov pc, r2\r
+ ldmfd sp!, {r0-r1}\r
+ b dtor_loop\r
+dtor_end:\r
+\r
+ /* Return from main, loop forever. */\r
+exit_loop:\r
+ b exit_loop\r
+\r
+#ifdef CHECK\r
+data_error_loop:\r
+ b data_error_loop\r
+\r
+text_error_loop:\r
+ b text_error_loop\r
+ \r
+fast_error_loop:\r
+ b fast_error_loop\r
+ \r
+bss_error_loop:\r
+ b bss_error_loop \r
+#endif\r
+ \r
+ \r
--- /dev/null
+<!DOCTYPE Linker_Placement_File>
+<Root name="Flash Section Placement" >
+ <MemorySegment name="FLASH" >
+ <ProgramSection load="Yes" inputsections="*(.vectors .vectors.*)" name=".vectors" />
+ <ProgramSection alignment="4" load="Yes" inputsections="*(.init .init.*)" name=".init" />
+ <ProgramSection alignment="4" load="No" name=".text_load" />
+ <ProgramSection alignment="4" load="Yes" inputsections="*(.text .text.* .glue_7t .glue_7 .gnu.linkonce.t.*)" name=".text" />
+ <ProgramSection alignment="4" load="Yes" inputsections="KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors))" name=".dtors" />
+ <ProgramSection alignment="4" load="Yes" inputsections="KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors))" name=".ctors" />
+ <ProgramSection alignment="4" load="Yes" inputsections="*(.rodata .rodata.* .gnu.linkonce.r.*)" name=".rodata" />
+ <ProgramSection alignment="4" load="Yes" runin=".fast_run" inputsections="*(.fast .fast.*)" name=".fast" />
+ <ProgramSection alignment="4" load="Yes" runin=".data_run" inputsections="*(.data .data.* .gnu.linkonce.d.*)" name=".data" />
+ </MemorySegment>
+ <MemorySegment name="External SRAM;SRAM;SDRAM;DRAM" >
+ <ProgramSection alignment="4" load="No" name=".data_run" />
+ <ProgramSection alignment="4" load="No" inputsections="*(.bss .bss.* .gnu.linkonce.b.*) *(COMMON)" name=".bss" />
+ <ProgramSection alignment="4" size="__HEAPSIZE__" load="No" name=".heap" />
+ <ProgramSection alignment="4" size="__STACKSIZE__" load="No" name=".stack" />
+ <ProgramSection alignment="4" size="0x190" load="No" name=".stack_irq" />
+ <ProgramSection alignment="4" size="0x0" load="No" name=".stack_fiq" />
+ <ProgramSection alignment="4" size="0x190" load="No" name=".stack_svc" />
+ <ProgramSection alignment="4" size="0x0" load="No" name=".stack_abt" />
+ <ProgramSection alignment="4" size="0x0" load="No" name=".stack_und" />
+ </MemorySegment>
+ <MemorySegment name="Internal SRAM;SRAM;SDRAM;DRAM" >
+ <ProgramSection size="0x3C" load="No" name=".vectors_ram" />
+ <ProgramSection alignment="4" load="No" name=".fast_run" />
+ </MemorySegment>
+</Root>
--- /dev/null
+FUTURE
+
+ * TODO: The lwIP source code makes some invalid assumptions on processor
+ word-length, storage sizes and alignment. See the mailing lists for
+ problems with exoteric (/DSP) architectures showing these problems.
+ We still have to fix some of these issues neatly.
+
+ * TODO: the ARP layer is not protected against concurrent access. If
+ you run from a multitasking OS, serialize access to ARP (called from
+ your network device driver and from a timeout thread.)
+
+HISTORY
+
+(HEAD)
+
+ 2004-12-28 Leon Woestenberg <leon.woestenberg@gmx.net>
+ * etharp.*: Disabled multiple packets on the ARP queue.
+ This clashes with TCP queueing.
+
+ 2004-11-28 Leon Woestenberg <leon.woestenberg@gmx.net>
+ * etharp.*: Fixed race condition from ARP request to ARP timeout.
+ Halved the ARP period, doubled the period counts.
+ ETHARP_MAX_PENDING now should be at least 2. This prevents
+ the counter from reaching 0 right away (which would allow
+ too little time for ARP responses to be received).
+
+ 2004-11-25 Leon Woestenberg <leon.woestenberg@gmx.net>
+ * dhcp.c: Decline messages were not multicast but unicast.
+ * etharp.c: ETHARP_CREATE is renamed to ETHARP_TRY_HARD.
+ Do not try hard to insert arbitrary packet's source address,
+ etharp_ip_input() now calls etharp_update() without ETHARP_TRY_HARD.
+ etharp_query() now always DOES call ETHARP_TRY_HARD so that users
+ querying an address will see it appear in the cache (DHCP could
+ suffer from this when a server invalidly gave an in-use address.)
+ * ipv4/ip_addr.h: Renamed ip_addr_maskcmp() to _netcmp() as we are
+ comparing network addresses (identifiers), not the network masks
+ themselves.
+ * ipv4/ip_addr.c: ip_addr_isbroadcast() now checks that the given
+ IP address actually belongs to the network of the given interface.
+
+ 2004-11-24 Kieran Mansley <kjm25@cam.ac.uk>
+ * tcp.c: Increment pcb->snd_buf when ACK is received in SYN_SENT state.
+
+(STABLE-1_1_0-RC1)
+
+ 2004-10-16 Kieran Mansley <kjm25@cam.ac.uk>
+ * tcp.c: Add code to tcp_recved() to send an ACK (window update) immediately,
+ even if one is already pending, if the rcv_wnd is above a threshold
+ (currently TCP_WND/2). This avoids waiting for a timer to expire to send a
+ delayed ACK in order to open the window if the stack is only receiving data.
+
+ 2004-09-12 Kieran Mansley <kjm25@cam.ac.uk>
+ * tcp*.*: Retransmit time-out handling improvement by Sam Jansen.
+
+ 2004-08-20 Tony Mountifield <tony@softins.co.uk>
+ * etharp.c: Make sure the first pbuf queued on an ARP entry
+ is properly ref counted.
+
+ 2004-07-27 Tony Mountifield <tony@softins.co.uk>
+ * debug.h: Added (int) cast in LWIP_DEBUGF() to avoid compiler
+ warnings about comparison.
+ * pbuf.c: Stopped compiler complaining of empty if statement
+ when LWIP_DEBUGF() empty. Closed an unclosed comment.
+ * tcp.c: Stopped compiler complaining of empty if statement
+ when LWIP_DEBUGF() empty.
+ * ip.h Corrected IPH_TOS() macro: returns a byte, so doesn't need htons().
+ * inet.c: Added a couple of casts to quiet the compiler.
+ No need to test isascii(c) before isdigit(c) or isxdigit(c).
+
+ 2004-07-22 Tony Mountifield <tony@softins.co.uk>
+ * inet.c: Made data types consistent in inet_ntoa().
+ Added casts for return values of checksum routines, to pacify compiler.
+ * ip_frag.c, tcp_out.c, sockets.c, pbuf.c
+ Small corrections to some debugging statements, to pacify compiler.
+
+ 2004-07-21 Tony Mountifield <tony@softins.co.uk>
+ * etharp.c: Removed spurious semicolon and added missing end-of-comment.
+ * ethernetif.c Updated low_level_output() to match prototype for
+ netif->linkoutput and changed low_level_input() similarly for consistency.
+ * api_msg.c: Changed recv_raw() from int to u8_t, to match prototype
+ of raw_recv() in raw.h and so avoid compiler error.
+ * sockets.c: Added trivial (int) cast to keep compiler happier.
+ * ip.c, netif.c Changed debug statements to use the tidier ip4_addrN() macros.
+
+(STABLE-1_0_0)
+
+ ++ Changes:
+
+ 2004-07-05 Leon Woestenberg <leon.woestenberg@gmx.net>
+ * sockets.*: Restructured LWIP_PRIVATE_TIMEVAL. Make sure
+ your cc.h file defines this either 1 or 0. If non-defined,
+ defaults to 1.
+ * .c: Added <string.h> and <errno.h> includes where used.
+ * etharp.c: Made some array indices unsigned.
+
+ 2004-06-27 Leon Woestenberg <leon.woestenberg@gmx.net>
+ * netif.*: Added netif_set_up()/down().
+ * dhcp.c: Changes to restart program flow.
+
+ 2004-05-07 Leon Woestenberg <leon.woestenberg@gmx.net>
+ * etharp.c: In find_entry(), instead of a list traversal per candidate, do a
+ single-pass lookup for different candidates. Should exploit locality.
+
+ 2004-04-29 Leon Woestenberg <leon.woestenberg@gmx.net>
+ * tcp*.c: Cleaned up source comment documentation for Doxygen processing.
+ * opt.h: ETHARP_ALWAYS_INSERT option removed to comply with ARP RFC.
+ * etharp.c: update_arp_entry() only adds new ARP entries when adviced to by
+ the caller. This deprecates the ETHARP_ALWAYS_INSERT overrule option.
+
+ ++ Bug fixes:
+
+ 2004-04-27 Leon Woestenberg <leon.woestenberg@gmx.net>
+ * etharp.c: Applied patch of bug #8708 by Toni Mountifield with a solution
+ suggested by Timmy Brolin. Fix for 32-bit processors that cannot access
+ non-aligned 32-bit words, such as soms 32-bit TCP/IP header fields. Fix
+ is to prefix the 14-bit Ethernet headers with two padding bytes.
+
+ 2004-04-23 Leon Woestenberg <leon.woestenberg@gmx.net>
+ * ip_addr.c: Fix in the ip_addr_isbroadcast() check.
+ * etharp.c: Fixed the case where the packet that initiates the ARP request
+ is not queued, and gets lost. Fixed the case where the packets destination
+ address is already known; we now always queue the packet and perform an ARP
+ request.
+
+(STABLE-0_7_0)
+
+ ++ Bug fixes:
+
+ * Fixed TCP bug for SYN_SENT to ESTABLISHED state transition.
+ * Fixed TCP bug in dequeueing of FIN from out of order segment queue.
+ * Fixed two possible NULL references in rare cases.
+
+(STABLE-0_6_6)
+
+ ++ Bug fixes:
+
+ * Fixed DHCP which did not include the IP address in DECLINE messages.
+
+ ++ Changes:
+
+ * etharp.c has been hauled over a bit.
+
+(STABLE-0_6_5)
+
+ ++ Bug fixes:
+
+ * Fixed TCP bug induced by bad window resizing with unidirectional TCP traffic.
+ * Packets sent from ARP queue had invalid source hardware address.
+
+ ++ Changes:
+
+ * Pass-by ARP requests do now update the cache.
+
+ ++ New features:
+
+ * No longer dependent on ctype.h.
+ * New socket options.
+ * Raw IP pcb support.
+
+(STABLE-0_6_4)
+
+ ++ Bug fixes:
+
+ * Some debug formatters and casts fixed.
+ * Numereous fixes in PPP.
+
+ ++ Changes:
+
+ * DEBUGF now is LWIP_DEBUGF
+ * pbuf_dechain() has been re-enabled.
+ * Mentioned the changed use of CVS branches in README.
+
+(STABLE-0_6_3)
+
+ ++ Bug fixes:
+
+ * Fixed pool pbuf memory leak in pbuf_alloc().
+ Occured if not enough PBUF_POOL pbufs for a packet pbuf chain.
+ Reported by Savin Zlobec.
+
+ * PBUF_POOL chains had their tot_len field not set for non-first
+ pbufs. Fixed in pbuf_alloc().
+
+ ++ New features:
+
+ * Added PPP stack contributed by Marc Boucher
+
+ ++ Changes:
+
+ * Now drops short packets for ICMP/UDP/TCP protocols. More robust.
+
+ * ARP queueuing now queues the latest packet instead of the first.
+ This is the RFC recommended behaviour, but can be overridden in
+ lwipopts.h.
+
+(0.6.2)
+
+ ++ Bugfixes:
+
+ * TCP has been fixed to deal with the new use of the pbuf->ref
+ counter.
+
+ * DHCP dhcp_inform() crash bug fixed.
+
+ ++ Changes:
+
+ * Removed pbuf_pool_free_cache and pbuf_pool_alloc_cache. Also removed
+ pbuf_refresh(). This has sped up pbuf pool operations considerably.
+ Implemented by David Haas.
+
+(0.6.1)
+
+ ++ New features:
+
+ * The packet buffer implementation has been enhanced to support
+ zero-copy and copy-on-demand for packet buffers which have their
+ payloads in application-managed memory.
+ Implemented by David Haas.
+
+ Use PBUF_REF to make a pbuf refer to RAM. lwIP will use zero-copy
+ if an outgoing packet can be directly sent on the link, or perform
+ a copy-on-demand when necessary.
+
+ The application can safely assume the packet is sent, and the RAM
+ is available to the application directly after calling udp_send()
+ or similar function.
+
+ ++ Bugfixes:
+
+ * ARP_QUEUEING should now correctly work for all cases, including
+ PBUF_REF.
+ Implemented by Leon Woestenberg.
+
+ ++ Changes:
+
+ * IP_ADDR_ANY is no longer a NULL pointer. Instead, it is a pointer
+ to a '0.0.0.0' IP address.
+
+ * The packet buffer implementation is changed. The pbuf->ref counter
+ meaning has changed, and several pbuf functions have been
+ adapted accordingly.
+
+ * netif drivers have to be changed to set the hardware address length field
+ that must be initialized correctly by the driver (hint: 6 for Ethernet MAC).
+ See the contrib/ports/c16x cs8900 driver as a driver example.
+
+ * netif's have a dhcp field that must be initialized to NULL by the driver.
+ See the contrib/ports/c16x cs8900 driver as a driver example.
+
+(0.5.x) This file has been unmaintained up to 0.6.1. All changes are
+ logged in CVS but have not been explained here.
+
+(0.5.3) Changes since version 0.5.2
+
+ ++ Bugfixes:
+
+ * memp_malloc(MEMP_API_MSG) could fail with multiple application
+ threads because it wasn't protected by semaphores.
+
+ ++ Other changes:
+
+ * struct ip_addr now packed.
+
+ * The name of the time variable in arp.c has been changed to ctime
+ to avoid conflicts with the time() function.
+
+(0.5.2) Changes since version 0.5.1
+
+ ++ New features:
+
+ * A new TCP function, tcp_tmr(), now handles both TCP timers.
+
+ ++ Bugfixes:
+
+ * A bug in tcp_parseopt() could cause the stack to hang because of a
+ malformed TCP option.
+
+ * The address of new connections in the accept() function in the BSD
+ socket library was not handled correctly.
+
+ * pbuf_dechain() did not update the ->tot_len field of the tail.
+
+ * Aborted TCP connections were not handled correctly in all
+ situations.
+
+ ++ Other changes:
+
+ * All protocol header structs are now packed.
+
+ * The ->len field in the tcp_seg structure now counts the actual
+ amount of data, and does not add one for SYN and FIN segments.
+
+(0.5.1) Changes since version 0.5.0
+
+ ++ New features:
+
+ * Possible to run as a user process under Linux.
+
+ * Preliminary support for cross platform packed structs.
+
+ * ARP timer now implemented.
+
+ ++ Bugfixes:
+
+ * TCP output queue length was badly initialized when opening
+ connections.
+
+ * TCP delayed ACKs were not sent correctly.
+
+ * Explicit initialization of BSS segment variables.
+
+ * read() in BSD socket library could drop data.
+
+ * Problems with memory alignment.
+
+ * Situations when all TCP buffers were used could lead to
+ starvation.
+
+ * TCP MSS option wasn't parsed correctly.
+
+ * Problems with UDP checksum calculation.
+
+ * IP multicast address tests had endianess problems.
+
+ * ARP requests had wrong destination hardware address.
+
+ ++ Other changes:
+
+ * struct eth_addr changed from u16_t[3] array to u8_t[6].
+
+ * A ->linkoutput() member was added to struct netif.
+
+ * TCP and UDP ->dest_* struct members where changed to ->remote_*.
+
+ * ntoh* macros are now null definitions for big endian CPUs.
+
+(0.5.0) Changes since version 0.4.2
+
+ ++ New features:
+
+ * Redesigned operating system emulation layer to make porting easier.
+
+ * Better control over TCP output buffers.
+
+ * Documenation added.
+
+ ++ Bugfixes:
+
+ * Locking issues in buffer management.
+
+ * Bugfixes in the sequential API.
+
+ * IP forwarding could cause memory leakage. This has been fixed.
+
+ ++ Other changes:
+
+ * Directory structure somewhat changed; the core/ tree has been
+ collapsed.
+
+(0.4.2) Changes since version 0.4.1
+
+ ++ New features:
+
+ * Experimental ARP implementation added.
+
+ * Skeleton Ethernet driver added.
+
+ * Experimental BSD socket API library added.
+
+ ++ Bugfixes:
+
+ * In very intense situations, memory leakage could occur. This has
+ been fixed.
+
+ ++ Other changes:
+
+ * Variables named "data" and "code" have been renamed in order to
+ avoid name conflicts in certain compilers.
+
+ * Variable++ have in appliciable cases been translated to ++variable
+ since some compilers generate better code in the latter case.
+
+(0.4.1) Changes since version 0.4
+
+ ++ New features:
+
+ * TCP: Connection attempts time out earlier than data
+ transmissions. Nagle algorithm implemented. Push flag set on the
+ last segment in a burst.
+
+ * UDP: experimental support for UDP-Lite extensions.
+
+ ++ Bugfixes:
+
+ * TCP: out of order segments were in some cases handled incorrectly,
+ and this has now been fixed. Delayed acknowledgements was broken
+ in 0.4, has now been fixed. Binding to an address that is in use
+ now results in an error. Reset connections sometimes hung an
+ application; this has been fixed.
+
+ * Checksum calculation sometimes failed for chained pbufs with odd
+ lengths. This has been fixed.
+
+ * API: a lot of bug fixes in the API. The UDP API has been improved
+ and tested. Error reporting and handling has been
+ improved. Logical flaws and race conditions for incoming TCP
+ connections has been found and removed.
+
+ * Memory manager: alignment issues. Reallocating memory sometimes
+ failed, this has been fixed.
+
+ * Generic library: bcopy was flawed and has been fixed.
+
+ ++ Other changes:
+
+ * API: all datatypes has been changed from generic ones such as
+ ints, to specified ones such as u16_t. Functions that return
+ errors now have the correct type (err_t).
+
+ * General: A lot of code cleaned up and debugging code removed. Many
+ portability issues have been fixed.
+
+ * The license was changed; the advertising clause was removed.
+
+ * C64 port added.
+
+ * Thanks: Huge thanks go to Dagan Galarneau, Horst Garnetzke, Petri
+ Kosunen, Mikael Caleres, and Frits Wilmink for reporting and
+ fixing bugs!
+
+(0.4) Changes since version 0.3.1
+
+ * Memory management has been radically changed; instead of
+ allocating memory from a shared heap, memory for objects that are
+ rapidly allocated and deallocated is now kept in pools. Allocation
+ and deallocation from those memory pools is very fast. The shared
+ heap is still present but is used less frequently.
+
+ * The memory, memory pool, and packet buffer subsystems now support
+ 4-, 2-, or 1-byte alignment.
+
+ * "Out of memory" situations are handled in a more robust way.
+
+ * Stack usage has been reduced.
+
+ * Easier configuration of lwIP parameters such as memory usage,
+ TTLs, statistics gathering, etc. All configuration parameters are
+ now kept in a single header file "lwipopts.h".
+
+ * The directory structure has been changed slightly so that all
+ architecture specific files are kept under the src/arch
+ hierarchy.
+
+ * Error propagation has been improved, both in the protocol modules
+ and in the API.
+
+ * The code for the RTXC architecture has been implemented, tested
+ and put to use.
+
+ * Bugs have been found and corrected in the TCP, UDP, IP, API, and
+ the Internet checksum modules.
+
+ * Bugs related to porting between a 32-bit and a 16-bit architecture
+ have been found and corrected.
+
+ * The license has been changed slightly to conform more with the
+ original BSD license, including the advertisement clause.
+
+(0.3.1) Changes since version 0.3
+
+ * Fix of a fatal bug in the buffer management. Pbufs with allocated
+ RAM never returned the RAM when the pbuf was deallocated.
+
+ * TCP congestion control, window updates and retransmissions did not
+ work correctly. This has now been fixed.
+
+ * Bugfixes in the API.
+
+(0.3) Changes since version 0.2
+
+ * New and improved directory structure. All include files are now
+ kept in a dedicated include/ directory.
+
+ * The API now has proper error handling. A new function,
+ netconn_err(), now returns an error code for the connection in
+ case of errors.
+
+ * Improvements in the memory management subsystem. The system now
+ keeps a pointer to the lowest free memory block. A new function,
+ mem_malloc2() tries to allocate memory once, and if it fails tries
+ to free some memory and retry the allocation.
+
+ * Much testing has been done with limited memory
+ configurations. lwIP now does a better job when overloaded.
+
+ * Some bugfixes and improvements to the buffer (pbuf) subsystem.
+
+ * Many bugfixes in the TCP code:
+
+ - Fixed a bug in tcp_close().
+
+ - The TCP receive window was incorrectly closed when out of
+ sequence segments was received. This has been fixed.
+
+ - Connections are now timed-out of the FIN-WAIT-2 state.
+
+ - The initial congestion window could in some cases be too
+ large. This has been fixed.
+
+ - The retransmission queue could in some cases be screwed up. This
+ has been fixed.
+
+ - TCP RST flag now handled correctly.
+
+ - Out of sequence data was in some cases never delivered to the
+ application. This has been fixed.
+
+ - Retransmitted segments now contain the correct acknowledgment
+ number and advertised window.
+
+ - TCP retransmission timeout backoffs are not correctly computed
+ (ala BSD). After a number of retransmissions, TCP now gives up
+ the connection.
+
+ * TCP connections now are kept on three lists, one for active
+ connections, one for listening connections, and one for
+ connections that are in TIME-WAIT. This greatly speeds up the fast
+ timeout processing for sending delayed ACKs.
+
+ * TCP now provides proper feedback to the application when a
+ connection has been successfully set up.
+
+ * More comments have been added to the code. The code has also been
+ somewhat cleaned up.
+
+(0.2) Initial public release.
--- /dev/null
+/*
+ * Copyright (c) 2001, 2002 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+
--- /dev/null
+src/ - The source code for the lwIP TCP/IP stack.
+doc/ - The documentation for lwIP.
+
+See also the FILES file in each subdirectory.
--- /dev/null
+INTRODUCTION
+
+lwIP is a small independent implementation of the TCP/IP protocol
+suite that has been developed by Adam Dunkels at the Computer and
+Networks Architectures (CNA) lab at the Swedish Institute of Computer
+Science (SICS).
+
+The focus of the lwIP TCP/IP implementation is to reduce the RAM usage
+while still having a full scale TCP. This making lwIP suitable for use
+in embedded systems with tenths of kilobytes of free RAM and room for
+around 40 kilobytes of code ROM.
+
+FEATURES
+
+ * IP (Internet Protocol) including packet forwarding over multiple
+ network interfaces
+ * ICMP (Internet Control Message Protocol) for network maintenance
+ and debugging
+ * UDP (User Datagram Protocol) including experimental UDP-lite
+ extensions
+ * TCP (Transmission Control Protocol) with congestion control, RTT
+ estimation and fast recovery/fast retransmit
+ * Specialized API for enhanced performance
+ * Optional Berkeley socket API
+
+LICENSE
+
+lwIP is freely available under a BSD license.
+
+DEVELOPMENT
+
+lwIP has grown into an excellent TCP/IP stack for embedded devices,
+and developers using the stack often submit bug fixes, improvements,
+and additions to the stack to further increase its usefulness.
+
+Development of lwIP is hosted on Savannah, a central point for
+software development, maintenance and distribution. Everyone can
+help improve lwIP by use of Savannah's interface, CVS and the
+mailing list. A core team of developers will commit changes to the
+CVS source tree.
+
+The lwIP TCP/IP stack is maintained in the 'lwip' CVS module and
+contributions (such as platform ports) are in the 'contrib' module.
+
+The CVS main trunk is the stable branch, which contains bug fixes and
+tested features. The latest stable branch can be checked out by doing:
+ cvs -d:pserver:anoncvs@subversions.gnu.org:/cvsroot/lwip login
+ cvs -z3 -d:pserver:anoncvs@subversions.gnu.org:/cvsroot/lwip co lwip
+
+The 'STABLE' tag in the stable branch will represent the most stable
+revision (which may be somewhat older to protect us from errors
+introduced by merges). This 'STABLE' tagged version can be checked out
+by doing:
+ cvs -d:pserver:anoncvs@subversions.gnu.org:/cvsroot/lwip login
+ cvs -z3 -d:pserver:anoncvs@subversions.gnu.org:/cvsroot/lwip co -r STABLE lwip
+
+The 'DEVEL' branch is the active development branch, which contains
+bleeding edge changes, and may be instable. It can be checkout by doing:
+ cvs -d:pserver:anoncvs@subversions.gnu.org:/cvsroot/lwip login
+ cvs -z3 -d:pserver:anoncvs@subversions.gnu.org:/cvsroot/lwip co -r DEVEL lwip
+
+The current contrib CVS tree can be checked out by doing:
+ cvs -d:pserver:anoncvs@subversions.gnu.org:/cvsroot/lwip login
+ cvs -z3 -d:pserver:anoncvs@subversions.gnu.org:/cvsroot/lwip co contrib
+
+Last night's CVS tar ball can be downloaded from:
+ http://savannah.gnu.org/cvs.backups/lwip.tar.gz
+
+The current CVS trees are web-browsable:
+ http://savannah.nongnu.org/cgi-bin/viewcvs/lwip/lwip/
+ http://savannah.nongnu.org/cgi-bin/viewcvs/lwip/contrib/
+
+Submit patches and bugs via the lwIP project page:
+ http://savannah.nongnu.org/projects/lwip/
+
+
+DOCUMENTATION
+
+The original out-dated homepage of lwIP and Adam Dunkels' papers on
+lwIP are at the official lwIP home page:
+ http://www.sics.se/~adam/lwip/
+
+Self documentation of the source code is regularly extracted from the
+current CVS sources and is available from this web page:
+ http://www.nongnu.org/lwip/
+
+Reading Adam's papers, the files in docs/, browsing the source code
+documentation and browsing the mailing list archives is a good way to
+become familiar with the design of lwIP.
+
+Adam Dunkels <adam@sics.se>
+Leon Woestenberg <leon.woestenberg@gmx.net>
--- /dev/null
+/*\r
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.\r
+ * All rights reserved. \r
+ * \r
+ * Redistribution and use in source and binary forms, with or without modification, \r
+ * are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. The name of the author may not be used to endorse or promote products\r
+ * derived from this software without specific prior written permission. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED \r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT \r
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, \r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT \r
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS \r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN \r
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING \r
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY \r
+ * OF SUCH DAMAGE.\r
+ *\r
+ * This file is part of the lwIP TCP/IP stack.\r
+ * \r
+ * Author: Adam Dunkels <adam@sics.se>\r
+ *\r
+ */\r
+#ifndef __CC_H__\r
+#define __CC_H__\r
+\r
+#include "cpu.h"\r
+\r
+typedef unsigned char u8_t;\r
+typedef signed char s8_t;\r
+typedef unsigned short u16_t;\r
+typedef signed short s16_t;\r
+typedef unsigned long u32_t;\r
+typedef signed long s32_t;\r
+typedef u32_t mem_ptr_t;\r
+typedef int sys_prot_t;\r
+\r
+\r
+#define PACK_STRUCT_BEGIN\r
+#define PACK_STRUCT_STRUCT __attribute__ ((__packed__))\r
+#define PACK_STRUCT_END\r
+#define PACK_STRUCT_FIELD(x) x\r
+\r
+#endif /* __CC_H__ */\r
--- /dev/null
+/*\r
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.\r
+ * All rights reserved. \r
+ * \r
+ * Redistribution and use in source and binary forms, with or without modification, \r
+ * are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. The name of the author may not be used to endorse or promote products\r
+ * derived from this software without specific prior written permission. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED \r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT \r
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, \r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT \r
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS \r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN \r
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING \r
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY \r
+ * OF SUCH DAMAGE.\r
+ *\r
+ * This file is part of the lwIP TCP/IP stack.\r
+ * \r
+ * Author: Adam Dunkels <adam@sics.se>\r
+ *\r
+ */\r
+#ifndef __CPU_H__\r
+#define __CPU_H__\r
+\r
+#define BYTE_ORDER LITTLE_ENDIAN\r
+\r
+#endif /* __CPU_H__ */\r
--- /dev/null
+/*\r
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.\r
+ * All rights reserved. \r
+ * \r
+ * Redistribution and use in source and binary forms, with or without modification, \r
+ * are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. The name of the author may not be used to endorse or promote products\r
+ * derived from this software without specific prior written permission. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED \r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT \r
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, \r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT \r
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS \r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN \r
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING \r
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY \r
+ * OF SUCH DAMAGE.\r
+ *\r
+ * This file is part of the lwIP TCP/IP stack.\r
+ * \r
+ * Author: Adam Dunkels <adam@sics.se>\r
+ *\r
+ */\r
+#ifndef __ARCH_INIT_H__\r
+#define __ARCH_INIT_H__\r
+\r
+#define TCPIP_INIT_DONE(arg) tcpip_init_done(arg)\r
+\r
+void tcpip_init_done(void *);\r
+int wait_for_tcpip_init(void);\r
+\r
+#endif /* __ARCH_INIT_H__ */\r
+\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.\r
+ * All rights reserved. \r
+ * \r
+ * Redistribution and use in source and binary forms, with or without modification, \r
+ * are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. The name of the author may not be used to endorse or promote products\r
+ * derived from this software without specific prior written permission. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED \r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT \r
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, \r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT \r
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS \r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN \r
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING \r
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY \r
+ * OF SUCH DAMAGE.\r
+ *\r
+ * This file is part of the lwIP TCP/IP stack.\r
+ * \r
+ * Author: Adam Dunkels <adam@sics.se>\r
+ *\r
+ */\r
+#ifndef __LIB_H__\r
+#define __LIB_H__\r
+\r
+#include <string.h>\r
+\r
+\r
+#endif /* __LIB_H__ */\r
--- /dev/null
+/*\r
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.\r
+ * All rights reserved. \r
+ * \r
+ * Redistribution and use in source and binary forms, with or without modification, \r
+ * are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. The name of the author may not be used to endorse or promote products\r
+ * derived from this software without specific prior written permission. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED \r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT \r
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, \r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT \r
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS \r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN \r
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING \r
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY \r
+ * OF SUCH DAMAGE.\r
+ *\r
+ * This file is part of the lwIP TCP/IP stack.\r
+ * \r
+ * Author: Adam Dunkels <adam@sics.se>\r
+ *\r
+ */\r
+#ifndef __PERF_H__\r
+#define __PERF_H__\r
+\r
+#define PERF_START /* null definition */\r
+#define PERF_STOP(x) /* null definition */\r
+\r
+#endif /* __PERF_H__ */\r
--- /dev/null
+/*\r
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.\r
+ * All rights reserved. \r
+ * \r
+ * Redistribution and use in source and binary forms, with or without modification, \r
+ * are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. The name of the author may not be used to endorse or promote products\r
+ * derived from this software without specific prior written permission. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED \r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT \r
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, \r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT \r
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS \r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN \r
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING \r
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY \r
+ * OF SUCH DAMAGE.\r
+ *\r
+ * This file is part of the lwIP TCP/IP stack.\r
+ * \r
+ * Author: Adam Dunkels <adam@sics.se>\r
+ *\r
+ */\r
+#ifndef __SYS_RTXC_H__\r
+#define __SYS_RTXC_H__\r
+\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+#include "semphr.h"\r
+\r
+#define SYS_MBOX_NULL (xQueueHandle)0\r
+#define SYS_SEM_NULL (xSemaphoreHandle)0\r
+\r
+typedef xSemaphoreHandle sys_sem_t;\r
+typedef xQueueHandle sys_mbox_t;\r
+typedef xTaskHandle sys_thread_t;\r
+\r
+#endif /* __SYS_RTXC_H__ */\r
+\r
--- /dev/null
+/*\r
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.\r
+ * All rights reserved. \r
+ * \r
+ * Redistribution and use in source and binary forms, with or without modification, \r
+ * are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. The name of the author may not be used to endorse or promote products\r
+ * derived from this software without specific prior written permission. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED \r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT \r
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, \r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT \r
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS \r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN \r
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING \r
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY \r
+ * OF SUCH DAMAGE.\r
+ *\r
+ * This file is part of the lwIP TCP/IP stack.\r
+ * \r
+ * Author: Adam Dunkels <adam@sics.se>\r
+ *\r
+ */\r
+\r
+/* lwIP includes. */\r
+#include "lwip/debug.h"\r
+#include "lwip/def.h"\r
+#include "lwip/sys.h"\r
+#include "lwip/mem.h"\r
+\r
+/* Message queue constants. */\r
+#define archMESG_QUEUE_LENGTH ( 6 )\r
+#define archPOST_BLOCK_TIME_MS ( ( unsigned portLONG ) 10000 )\r
+\r
+struct timeoutlist \r
+{\r
+ struct sys_timeouts timeouts;\r
+ xTaskHandle pid;\r
+};\r
+\r
+/* This is the number of threads that can be started with sys_thread_new() */\r
+#define SYS_THREAD_MAX 4\r
+\r
+#define lwipTCP_STACK_SIZE 600\r
+#define lwipBASIC_SERVER_STACK_SIZE 250\r
+\r
+static struct timeoutlist timeoutlist[SYS_THREAD_MAX];\r
+static u16_t nextthread = 0;\r
+int intlevel = 0;\r
+\r
+\r
+/*-----------------------------------------------------------------------------------*/\r
+// Creates an empty mailbox.\r
+sys_mbox_t\r
+sys_mbox_new(void)\r
+{\r
+ xQueueHandle mbox;\r
+\r
+ mbox = xQueueCreate( archMESG_QUEUE_LENGTH, sizeof( void * ) );\r
+\r
+ return mbox;\r
+}\r
+\r
+/*-----------------------------------------------------------------------------------*/\r
+/*\r
+ Deallocates a mailbox. If there are messages still present in the\r
+ mailbox when the mailbox is deallocated, it is an indication of a\r
+ programming error in lwIP and the developer should be notified.\r
+*/\r
+void\r
+sys_mbox_free(sys_mbox_t mbox)\r
+{\r
+ if( uxQueueMessagesWaiting( mbox ) )\r
+ {\r
+ /* Line for breakpoint. Should never break here! */\r
+ __asm volatile ( "NOP" );\r
+ }\r
+\r
+ vQueueDelete( mbox ); \r
+}\r
+\r
+/*-----------------------------------------------------------------------------------*/\r
+// Posts the "msg" to the mailbox.\r
+void\r
+sys_mbox_post(sys_mbox_t mbox, void *data)\r
+{ \r
+ xQueueSend( mbox, &data, ( portTickType ) ( archPOST_BLOCK_TIME_MS / portTICK_RATE_MS ) );\r
+}\r
+\r
+\r
+/*-----------------------------------------------------------------------------------*/\r
+/*\r
+ Blocks the thread until a message arrives in the mailbox, but does\r
+ not block the thread longer than "timeout" milliseconds (similar to\r
+ the sys_arch_sem_wait() function). The "msg" argument is a result\r
+ parameter that is set by the function (i.e., by doing "*msg =\r
+ ptr"). The "msg" parameter maybe NULL to indicate that the message\r
+ should be dropped.\r
+\r
+ The return values are the same as for the sys_arch_sem_wait() function:\r
+ Number of milliseconds spent waiting or SYS_ARCH_TIMEOUT if there was a\r
+ timeout.\r
+\r
+ Note that a function with a similar name, sys_mbox_fetch(), is\r
+ implemented by lwIP. \r
+*/\r
+u32_t sys_arch_mbox_fetch(sys_mbox_t mbox, void **msg, u32_t timeout)\r
+{\r
+void *dummyptr;\r
+portTickType StartTime, EndTime, Elapsed;\r
+\r
+ StartTime = xTaskGetTickCount();\r
+\r
+ if( msg == NULL )\r
+ {\r
+ msg = &dummyptr;\r
+ }\r
+ \r
+ if( timeout != 0 )\r
+ {\r
+ if(pdTRUE == xQueueReceive( mbox, &(*msg), timeout ) )\r
+ {\r
+ EndTime = xTaskGetTickCount();\r
+ Elapsed = EndTime - StartTime;\r
+ if( Elapsed == 0 )\r
+ {\r
+ Elapsed = 1;\r
+ }\r
+ return ( Elapsed );\r
+ }\r
+ else // timed out blocking for message\r
+ {\r
+ *msg = NULL;\r
+ return SYS_ARCH_TIMEOUT;\r
+ }\r
+ }\r
+ else // block forever for a message.\r
+ {\r
+ while( pdTRUE != xQueueReceive( mbox, &(*msg), 10000 ) ) // time is arbitrary\r
+ {\r
+ ;\r
+ }\r
+ EndTime = xTaskGetTickCount();\r
+ Elapsed = EndTime - StartTime;\r
+ if( Elapsed == 0 )\r
+ {\r
+ Elapsed = 1;\r
+ }\r
+ return ( Elapsed ); // return time blocked TBD test \r
+ }\r
+}\r
+\r
+/*-----------------------------------------------------------------------------------*/\r
+// Creates and returns a new semaphore. The "count" argument specifies\r
+// the initial state of the semaphore. TBD finish and test\r
+sys_sem_t\r
+sys_sem_new(u8_t count)\r
+{\r
+ xSemaphoreHandle xSemaphore;\r
+\r
+ portENTER_CRITICAL();\r
+ vSemaphoreCreateBinary( xSemaphore );\r
+ if(count == 0) // Means it can't be taken\r
+ {\r
+ xSemaphoreTake(xSemaphore,1);\r
+ }\r
+ portEXIT_CRITICAL();\r
+\r
+ if( xSemaphore == NULL )\r
+ {\r
+ return NULL; // TBD need assert\r
+ }\r
+ else\r
+ {\r
+ return xSemaphore;\r
+ }\r
+}\r
+\r
+/*-----------------------------------------------------------------------------------*/\r
+/*\r
+ Blocks the thread while waiting for the semaphore to be\r
+ signaled. If the "timeout" argument is non-zero, the thread should\r
+ only be blocked for the specified time (measured in\r
+ milliseconds).\r
+\r
+ If the timeout argument is non-zero, the return value is the number of\r
+ milliseconds spent waiting for the semaphore to be signaled. If the\r
+ semaphore wasn't signaled within the specified time, the return value is\r
+ SYS_ARCH_TIMEOUT. If the thread didn't have to wait for the semaphore\r
+ (i.e., it was already signaled), the function may return zero.\r
+\r
+ Notice that lwIP implements a function with a similar name,\r
+ sys_sem_wait(), that uses the sys_arch_sem_wait() function.\r
+*/\r
+u32_t\r
+sys_arch_sem_wait(sys_sem_t sem, u32_t timeout)\r
+{\r
+portTickType StartTime, EndTime, Elapsed;\r
+\r
+ StartTime = xTaskGetTickCount();\r
+\r
+ if( timeout != 0)\r
+ {\r
+ if( xSemaphoreTake( sem, timeout ) == pdTRUE )\r
+ {\r
+ EndTime = xTaskGetTickCount();\r
+ Elapsed = EndTime - StartTime;\r
+ if( Elapsed == 0 )\r
+ {\r
+ Elapsed = 1;\r
+ }\r
+ return (Elapsed); // return time blocked TBD test \r
+ }\r
+ else\r
+ {\r
+ return SYS_ARCH_TIMEOUT;\r
+ }\r
+ }\r
+ else // must block without a timeout\r
+ {\r
+ while( xSemaphoreTake( sem, 10000 ) != pdTRUE )\r
+ {\r
+ ;\r
+ }\r
+ EndTime = xTaskGetTickCount();\r
+ Elapsed = EndTime - StartTime;\r
+ if( Elapsed == 0 )\r
+ {\r
+ Elapsed = 1;\r
+ }\r
+\r
+ return ( Elapsed ); // return time blocked \r
+ \r
+ }\r
+}\r
+\r
+/*-----------------------------------------------------------------------------------*/\r
+// Signals a semaphore\r
+void\r
+sys_sem_signal(sys_sem_t sem)\r
+{\r
+ xSemaphoreGive( sem );\r
+}\r
+\r
+/*-----------------------------------------------------------------------------------*/\r
+// Deallocates a semaphore\r
+void\r
+sys_sem_free(sys_sem_t sem)\r
+{\r
+ vQueueDelete( sem ); \r
+}\r
+\r
+/*-----------------------------------------------------------------------------------*/\r
+// Initialize sys arch\r
+void\r
+sys_init(void)\r
+{\r
+\r
+ int i;\r
+\r
+ // Initialize the the per-thread sys_timeouts structures\r
+ // make sure there are no valid pids in the list\r
+ for(i = 0; i < SYS_THREAD_MAX; i++)\r
+ {\r
+ timeoutlist[i].pid = 0;\r
+ }\r
+\r
+ // keep track of how many threads have been created\r
+ nextthread = 0;\r
+}\r
+\r
+/*-----------------------------------------------------------------------------------*/\r
+/*\r
+ Returns a pointer to the per-thread sys_timeouts structure. In lwIP,\r
+ each thread has a list of timeouts which is represented as a linked\r
+ list of sys_timeout structures. The sys_timeouts structure holds a\r
+ pointer to a linked list of timeouts. This function is called by\r
+ the lwIP timeout scheduler and must not return a NULL value. \r
+\r
+ In a single threaded sys_arch implementation, this function will\r
+ simply return a pointer to a global sys_timeouts variable stored in\r
+ the sys_arch module.\r
+*/\r
+struct sys_timeouts *\r
+sys_arch_timeouts(void)\r
+{\r
+int i;\r
+xTaskHandle pid;\r
+struct timeoutlist *tl; \r
+\r
+ pid = xTaskGetCurrentTaskHandle( ); \r
+\r
+ for(i = 0; i < nextthread; i++) \r
+ {\r
+ tl = &timeoutlist[i];\r
+ if(tl->pid == pid) \r
+ {\r
+ return &(tl->timeouts);\r
+ }\r
+ }\r
+\r
+ // Error\r
+ return NULL;\r
+}\r
+\r
+/*-----------------------------------------------------------------------------------*/\r
+/*-----------------------------------------------------------------------------------*/\r
+// TBD \r
+/*-----------------------------------------------------------------------------------*/\r
+/*\r
+ Starts a new thread with priority "prio" that will begin its execution in the\r
+ function "thread()". The "arg" argument will be passed as an argument to the\r
+ thread() function. The id of the new thread is returned. Both the id and\r
+ the priority are system dependent.\r
+*/\r
+sys_thread_t sys_thread_new(void (* thread)(void *arg), void *arg, int prio)\r
+{\r
+xTaskHandle CreatedTask;\r
+int result;\r
+static int iCall = 0;\r
+\r
+ if( iCall == 0 )\r
+ {\r
+ /* The first time this is called we are creating the lwIP handler. */\r
+ result = xTaskCreate( thread, ( signed portCHAR * ) "lwIP", lwipTCP_STACK_SIZE, arg, prio, &CreatedTask );\r
+ iCall++;\r
+ }\r
+ else\r
+ {\r
+ result = xTaskCreate( thread, ( signed portCHAR * ) "WEBSvr", lwipBASIC_SERVER_STACK_SIZE, arg, prio, &CreatedTask );\r
+ }\r
+\r
+ // For each task created, store the task handle (pid) in the timers array.\r
+ // This scheme doesn't allow for threads to be deleted\r
+ timeoutlist[nextthread++].pid = CreatedTask;\r
+\r
+ if(result == pdPASS)\r
+ {\r
+ return CreatedTask;\r
+ }\r
+ else\r
+ {\r
+ return NULL;\r
+ }\r
+}\r
+\r
+/*\r
+ This optional function does a "fast" critical region protection and returns\r
+ the previous protection level. This function is only called during very short\r
+ critical regions. An embedded system which supports ISR-based drivers might\r
+ want to implement this function by disabling interrupts. Task-based systems\r
+ might want to implement this by using a mutex or disabling tasking. This\r
+ function should support recursive calls from the same task or interrupt. In\r
+ other words, sys_arch_protect() could be called while already protected. In\r
+ that case the return value indicates that it is already protected.\r
+\r
+ sys_arch_protect() is only required if your port is supporting an operating\r
+ system.\r
+*/\r
+sys_prot_t sys_arch_protect(void)\r
+{\r
+ vPortEnterCritical();\r
+ return 1;\r
+}\r
+\r
+/*\r
+ This optional function does a "fast" set of critical region protection to the\r
+ value specified by pval. See the documentation for sys_arch_protect() for\r
+ more information. This function is only required if your port is supporting\r
+ an operating system.\r
+*/\r
+void sys_arch_unprotect(sys_prot_t pval)\r
+{ \r
+ ( void ) pval;\r
+ vPortExitCritical();\r
+}\r
+\r
--- /dev/null
+1 Introduction
+
+This document describes some guidelines for people participating
+in lwIP development.
+
+2 How to contribute to lwIP
+
+Here is a short list of suggestions to anybody working with lwIP and
+trying to contribute bug reports, fixes, enhancements, platform ports etc.
+First of all as you may already know lwIP is a volunteer project so feedback
+to fixes or questions might often come late. Hopefully the bug and patch tracking
+features of Savannah help us not lose users' input.
+
+2.1 Source code style:
+
+1. do not use tabs.
+2. indentation is two spaces per level (i.e. per tab).
+3. end debug messages with a trailing newline (\n).
+4. one space between keyword and opening bracket.
+5. no space between function and opening bracket.
+6. one space and no newline before opening curly braces of a block.
+7. closing curly brace on a single line.
+8. spaces surrounding assignment and comparisons.
+9. use current source code style as further reference.
+
+2.2 Source code documentation style:
+
+1. JavaDoc compliant and Doxygen compatible.
+2. Function documentation above functions in .c files, not .h files.
+ (This forces you to synchronize documentation and implementation.)
+3. Use current documentation style as further reference.
+
+2.3 Bug reports and patches:
+
+1. Make sure you are reporting bugs or send patches against the latest
+ sources. (From the latest release and/or the current CVS sources.)
+2. If you think you found a bug make sure it's not already filed in the
+ bugtracker at Savannah.
+3. If you have a fix put the patch on Savannah. If it is a patch that affects
+ both core and arch specific stuff please separate them so that the core can
+ be applied separately while leaving the other patch 'open'. The prefered way
+ is to NOT touch archs you can't test and let maintainers take care of them.
+ This is a good way to see if they are used at all - the same goes for unix
+ netifs except tapif.
+4. Do not file a bug and post a fix to it to the patch area. Either a bug report
+ or a patch will be enough.
+ If you correct an existing bug then attach the patch to the bug rather than creating a new entry in the patch area.
+5. Trivial patches (compiler warning, indentation and spelling fixes or anything obvious which takes a line or two)
+ can go to the lwip-users list. This is still the fastest way of interaction and the list is not so crowded
+ as to allow for loss of fixes. Putting bugs on Savannah and subsequently closing them is too much an overhead
+ for reporting a compiler warning fix.
+6. Patches should be specific to a single change or to related changes.Do not mix bugfixes with spelling and other
+ trivial fixes unless the bugfix is trivial too.Do not reorganize code and rename identifiers in the same patch you
+ change behaviour if not necessary.A patch is easier to read and understand if it's to the point and short than
+ if it's not to the point and long :) so the chances for it to be applied are greater.
+
+2.4 Platform porters:
+
+1. If you have ported lwIP to a platform (an OS, a uC/processor or a combination of these) and
+ you think it could benefit others[1] you might want discuss this on the mailing list. You
+ can also ask for CVS access to submit and maintain your port in the contrib CVS module.
+
\ No newline at end of file
--- /dev/null
+Raw TCP/IP interface for lwIP
+
+Authors: Adam Dunkels, Leon Woestenberg
+
+lwIP provides two Application Program's Interfaces (APIs) for programs
+to use for communication with the TCP/IP code:
+* low-level "core" / "callback" or "raw" API.
+* higher-level "sequential" API.
+
+The sequential API provides a way for ordinary, sequential, programs
+to use the lwIP stack. It is quite similar to the BSD socket API. The
+model of execution is based on the blocking open-read-write-close
+paradigm. Since the TCP/IP stack is event based by nature, the TCP/IP
+code and the application program must reside in different execution
+contexts (threads).
+
+** The remainder of this document discusses the "raw" API. **
+
+The raw TCP/IP interface allows the application program to integrate
+better with the TCP/IP code. Program execution is event based by
+having callback functions being called from within the TCP/IP
+code. The TCP/IP code and the application program both run in the same
+thread. The sequential API has a much higher overhead and is not very
+well suited for small systems since it forces a multithreaded paradigm
+on the application.
+
+The raw TCP/IP interface is not only faster in terms of code execution
+time but is also less memory intensive. The drawback is that program
+development is somewhat harder and application programs written for
+the raw TCP/IP interface are more difficult to understand. Still, this
+is the preferred way of writing applications that should be small in
+code size and memory usage.
+
+Both APIs can be used simultaneously by different application
+programs. In fact, the sequential API is implemented as an application
+program using the raw TCP/IP interface.
+
+--- Callbacks
+
+Program execution is driven by callbacks. Each callback is an ordinary
+C function that is called from within the TCP/IP code. Every callback
+function is passed the current TCP or UDP connection state as an
+argument. Also, in order to be able to keep program specific state,
+the callback functions are called with a program specified argument
+that is independent of the TCP/IP state.
+
+The function for setting the application connection state is:
+
+- void tcp_arg(struct tcp_pcb *pcb, void *arg)
+
+ Specifies the program specific state that should be passed to all
+ other callback functions. The "pcb" argument is the current TCP
+ connection control block, and the "arg" argument is the argument
+ that will be passed to the callbacks.
+
+
+--- TCP connection setup
+
+The functions used for setting up connections is similar to that of
+the sequential API and of the BSD socket API. A new TCP connection
+identifier (i.e., a protocol control block - PCB) is created with the
+tcp_new() function. This PCB can then be either set to listen for new
+incoming connections or be explicitly connected to another host.
+
+- struct tcp_pcb *tcp_new(void)
+
+ Creates a new connection identifier (PCB). If memory is not
+ available for creating the new pcb, NULL is returned.
+
+- err_t tcp_bind(struct tcp_pcb *pcb, struct ip_addr *ipaddr,
+ u16_t port)
+
+ Binds the pcb to a local IP address and port number. The IP address
+ can be specified as IP_ADDR_ANY in order to bind the connection to
+ all local IP addresses.
+
+ If another connection is bound to the same port, the function will
+ return ERR_USE, otherwise ERR_OK is returned.
+
+- struct tcp_pcb *tcp_listen(struct tcp_pcb *pcb)
+
+ Commands a pcb to start listening for incoming connections. When an
+ incoming connection is accepted, the function specified with the
+ tcp_accept() function will be called. The pcb will have to be bound
+ to a local port with the tcp_bind() function.
+
+ The tcp_listen() function returns a new connection identifier, and
+ the one passed as an argument to the function will be
+ deallocated. The reason for this behavior is that less memory is
+ needed for a connection that is listening, so tcp_listen() will
+ reclaim the memory needed for the original connection and allocate a
+ new smaller memory block for the listening connection.
+
+ tcp_listen() may return NULL if no memory was available for the
+ listening connection. If so, the memory associated with the pcb
+ passed as an argument to tcp_listen() will not be deallocated.
+
+- void tcp_accept(struct tcp_pcb *pcb,
+ err_t (* accept)(void *arg, struct tcp_pcb *newpcb,
+ err_t err))
+
+ Specified the callback function that should be called when a new
+ connection arrives on a listening connection.
+
+- err_t tcp_connect(struct tcp_pcb *pcb, struct ip_addr *ipaddr,
+ u16_t port, err_t (* connected)(void *arg,
+ struct tcp_pcb *tpcb,
+ err_t err));
+
+ Sets up the pcb to connect to the remote host and sends the
+ initial SYN segment which opens the connection.
+
+ The tcp_connect() function returns immediately; it does not wait for
+ the connection to be properly setup. Instead, it will call the
+ function specified as the fourth argument (the "connected" argument)
+ when the connection is established. If the connection could not be
+ properly established, either because the other host refused the
+ connection or because the other host didn't answer, the "connected"
+ function will be called with an the "err" argument set accordingly.
+
+ The tcp_connect() function can return ERR_MEM if no memory is
+ available for enqueueing the SYN segment. If the SYN indeed was
+ enqueued successfully, the tcp_connect() function returns ERR_OK.
+
+
+--- Sending TCP data
+
+TCP data is sent by enqueueing the data with a call to
+tcp_write(). When the data is successfully transmitted to the remote
+host, the application will be notified with a call to a specified
+callback function.
+
+- err_t tcp_write(struct tcp_pcb *pcb, void *dataptr, u16_t len,
+ u8_t copy)
+
+ Enqueues the data pointed to by the argument dataptr. The length of
+ the data is passed as the len parameter. The copy argument is either
+ 0 or 1 and indicates whether the new memory should be allocated for
+ the data to be copied into. If the argument is 0, no new memory
+ should be allocated and the data should only be referenced by
+ pointer.
+
+ The tcp_write() function will fail and return ERR_MEM if the length
+ of the data exceeds the current send buffer size or if the length of
+ the queue of outgoing segment is larger than the upper limit defined
+ in lwipopts.h. The number of bytes available in the output queue can
+ be retrieved with the tcp_sndbuf() function.
+
+ The proper way to use this function is to call the function with at
+ most tcp_sndbuf() bytes of data. If the function returns ERR_MEM,
+ the application should wait until some of the currently enqueued
+ data has been successfully received by the other host and try again.
+
+- void tcp_sent(struct tcp_pcb *pcb,
+ err_t (* sent)(void *arg, struct tcp_pcb *tpcb,
+ u16_t len))
+
+ Specifies the callback function that should be called when data has
+ successfully been received (i.e., acknowledged) by the remote
+ host. The len argument passed to the callback function gives the
+ amount bytes that was acknowledged by the last acknowledgment.
+
+
+--- Receiving TCP data
+
+TCP data reception is callback based - an application specified
+callback function is called when new data arrives. When the
+application has taken the data, it has to call the tcp_recved()
+function to indicate that TCP can advertise increase the receive
+window.
+
+- void tcp_recv(struct tcp_pcb *pcb,
+ err_t (* recv)(void *arg, struct tcp_pcb *tpcb,
+ struct pbuf *p, err_t err))
+
+ Sets the callback function that will be called when new data
+ arrives. The callback function will be passed a NULL pbuf to
+ indicate that the remote host has closed the connection.
+
+- void tcp_recved(struct tcp_pcb *pcb, u16_t len)
+
+ Must be called when the application has received the data. The len
+ argument indicates the length of the received data.
+
+
+--- Application polling
+
+When a connection is idle (i.e., no data is either transmitted or
+received), lwIP will repeatedly poll the application by calling a
+specified callback function. This can be used either as a watchdog
+timer for killing connections that have stayed idle for too long, or
+as a method of waiting for memory to become available. For instance,
+if a call to tcp_write() has failed because memory wasn't available,
+the application may use the polling functionality to call tcp_write()
+again when the connection has been idle for a while.
+
+- void tcp_poll(struct tcp_pcb *pcb, u8_t interval,
+ err_t (* poll)(void *arg, struct tcp_pcb *tpcb))
+
+ Specifies the polling interval and the callback function that should
+ be called to poll the application. The interval is specified in
+ number of TCP coarse grained timer shots, which typically occurs
+ twice a second. An interval of 10 means that the application would
+ be polled every 5 seconds.
+
+
+--- Closing and aborting connections
+
+- err_t tcp_close(struct tcp_pcb *pcb)
+
+ Closes the connection. The function may return ERR_MEM if no memory
+ was available for closing the connection. If so, the application
+ should wait and try again either by using the acknowledgment
+ callback or the polling functionality. If the close succeeds, the
+ function returns ERR_OK.
+
+ The pcb is deallocated by the TCP code after a call to tcp_close().
+
+- void tcp_abort(struct tcp_pcb *pcb)
+
+ Aborts the connection by sending a RST (reset) segment to the remote
+ host. The pcb is deallocated. This function never fails.
+
+If a connection is aborted because of an error, the application is
+alerted of this event by the err callback. Errors that might abort a
+connection are when there is a shortage of memory. The callback
+function to be called is set using the tcp_err() function.
+
+- void tcp_err(struct tcp_pcb *pcb, void (* err)(void *arg,
+ err_t err))
+
+ The error callback function does not get the pcb passed to it as a
+ parameter since the pcb may already have been deallocated.
+
+
+--- Lower layer TCP interface
+
+TCP provides a simple interface to the lower layers of the
+system. During system initialization, the function tcp_init() has
+to be called before any other TCP function is called. When the system
+is running, the two timer functions tcp_fasttmr() and tcp_slowtmr()
+must be called with regular intervals. The tcp_fasttmr() should be
+called every TCP_FAST_INTERVAL milliseconds (defined in tcp.h) and
+tcp_slowtmr() should be called every TCP_SLOW_INTERVAL milliseconds.
+
+
+--- UDP interface
+
+The UDP interface is similar to that of TCP, but due to the lower
+level of complexity of UDP, the interface is significantly simpler.
+
+- struct udp_pcb *udp_new(void)
+
+ Creates a new UDP pcb which can be used for UDP communication. The
+ pcb is not active until it has either been bound to a local address
+ or connected to a remote address.
+
+- void udp_remove(struct udp_pcb *pcb)
+
+ Removes and deallocates the pcb.
+
+- err_t udp_bind(struct udp_pcb *pcb, struct ip_addr *ipaddr,
+ u16_t port)
+
+ Binds the pcb to a local address. The IP-address argument "ipaddr"
+ can be IP_ADDR_ANY to indicate that it should listen to any local IP
+ address. The function currently always return ERR_OK.
+
+- err_t udp_connect(struct udp_pcb *pcb, struct ip_addr *ipaddr,
+ u16_t port)
+
+ Sets the remote end of the pcb. This function does not generate any
+ network traffic, but only set the remote address of the pcb.
+
+- err_t udp_disconnect(struct udp_pcb *pcb)
+
+ Remove the remote end of the pcb. This function does not generate
+ any network traffic, but only removes the remote address of the pcb.
+
+- err_t udp_send(struct udp_pcb *pcb, struct pbuf *p)
+
+ Sends the pbuf p. The pbuf is not deallocated.
+
+- void udp_recv(struct udp_pcb *pcb,
+ void (* recv)(void *arg, struct udp_pcb *upcb,
+ struct pbuf *p,
+ struct ip_addr *addr,
+ u16_t port),
+ void *recv_arg)
+
+ Specifies a callback function that should be called when a UDP
+ datagram is received.
\ No newline at end of file
--- /dev/null
+Daily Use Guide for using Savannah for lwIP
+
+Table of Contents:
+
+1 - Obtaining lwIP from the CVS repository
+2 - Committers/developers CVS access using SSH (to be written)
+3 - Merging from DEVEL branch to main trunk (stable branch)
+4 - How to release lwIP
+
+
+
+1 Obtaining lwIP from the CVS repository
+----------------------------------------
+
+To perform an anonymous CVS checkout of the main trunk (this is where
+bug fixes and incremental enhancements occur), do this:
+
+export CVS_RSH=ssh
+cvs -d:ext:anoncvs@subversions.gnu.org:/cvsroot/lwip checkout lwip
+
+(If SSH asks about authenticity of the host, you can check the key
+ fingerprint against http://savannah.nongnu.org/cvs/?group=lwip)
+
+Or, obtain a stable branch (updated with bug fixes only) as follows:
+cvs -d:ext:anoncvs@subversions.gnu.org:/cvsroot/lwip checkout -r STABLE-0_7 -d lwip-0.7 lwip
+
+Or, obtain a specific (fixed) release as follows:
+cvs -d:ext:anoncvs@subversions.gnu.org:/cvsroot/lwip checkout -r STABLE-0_7_0 -d lwip-0.7.0 lwip
+
+Or, obtain a development branch (considered unstable!) as follows:
+cvs -d:ext:anoncvs@subversions.gnu.org:/cvsroot/lwip checkout -r DEVEL -d lwip-DEVEL lwip
+
+3 Committers/developers CVS access using SSH
+--------------------------------------------
+
+The Savannah server uses SSH (Secure Shell) protocol 2 authentication and encryption.
+As such, CVS commits to the server occur through a SSH tunnel for project members.
+To create a SSH2 key pair in UNIX-like environments, do this:
+
+ssh-keygen -t dsa
+
+Under Windows, a recommended SSH client is "PuTTY", freely available with good
+documentation and a graphic user interface. Use its key generator.
+
+Now paste the id_dsa.pub contents into your Savannah account public key list. Wait
+a while so that Savannah can update its configuration (This can take minutes).
+
+Try to login using SSH:
+
+ssh -v your_login@subversions.gnu.org
+
+If it tells you:
+
+Authenticating with public key "your_key_name"...
+Server refused to allocate pty
+
+then you could login; Savannah refuses to give you a shell - which is OK, as we
+are allowed to use SSH for CVS only. Now, you should be able to do this:
+
+export CVS_RSH=ssh
+cvs -d:ext:your_login@subversions.gnu.org:/cvsroot/lwip checkout lwip
+
+after which you can edit your local files with bug fixes or new features and
+commit them. Make sure you know what you are doing when using CVS to make
+changes on the repository. If in doubt, ask on the lwip-members mailing list.
+
+3 Merging from DEVEL branch to main trunk (stable)
+--------------------------------------------------
+
+Merging is a delicate process in CVS and requires the
+following disciplined steps in order to prevent conflicts
+in the future. Conflicts can be hard to solve!
+
+Merging from branch A to branch B requires that the A branch
+has a tag indicating the previous merger. This tag is called
+'merged_from_A_to_B'. After merging, the tag is moved in the
+A branch to remember this merger for future merge actions.
+
+IMPORTANT: AFTER COMMITTING A SUCCESFUL MERGE IN THE
+REPOSITORY, THE TAG MUST BE SET ON THE SOURCE BRANCH OF THE
+MERGE ACTION (REPLACING EXISTING TAGS WITH THE SAME NAME).
+
+Merge all changes in DEVEL since our last merge to main:
+
+In the working copy of the main trunk:
+cvs update -P -jmerged_from_DEVEL_to_main -jDEVEL
+
+(This will apply the changes between 'merged_from_DEVEL_to_main'
+and 'DEVEL' to your work set of files)
+
+We can now commit the merge result.
+cvs commit -R -m "Merged from DEVEL to main."
+
+If this worked out OK, we now move the tag in the DEVEL branch
+to this merge point, so we can use this point for future merges:
+
+cvs rtag -F -r DEVEL merged_from_DEVEL_to_main lwip
+
+4 How to release lwIP
+---------------------
+
+First, checkout a clean copy of the branch to be released. Tag this set with
+tag name "STABLE-0_6_3". (I use release number 0.6.3 throughout this example).
+
+Login CVS using pserver authentication, then export a clean copy of the
+tagged tree. Export is similar to a checkout, except that the CVS metadata
+is not created locally.
+
+export CVS_RSH=ssh
+cvs -d:ext:anoncvs@subversions.gnu.org:/cvsroot/lwip export -r STABLE-0_6_3 -d lwip-0.6.3 lwip
+
+Archive this directory using tar, gzip'd, bzip2'd and zip'd.
+
+tar czvf lwip-0.6.3.tar.gz lwip-0.6.3
+tar cjvf lwip-0.6.3.tar.bz2 lwip-0.6.3
+zip -r lwip-0.6.3.zip lwip-0.6.3
+
+Now, sign the archives with a detached GPG binary signature as follows:
+
+gpg -b lwip-0.6.3.tar.gz
+gpg -b lwip-0.6.3.tar.bz2
+gpg -b lwip-0.6.3.zip
+
+Upload these files using anonymous FTP:
+ncftp ftp://savannah.gnu.org/incoming/savannah/lwip
+
+ncftp>mput *0.6.3.*
+
+Additionally, you may post a news item on Savannah, like this:
+
+A new 0.6.3 release is now available here:
+http://savannah.nongnu.org/files/?group=lwip&highlight=0.6.3
+
+You will have to submit this via the user News interface, then approve
+this via the Administrator News interface.
\ No newline at end of file
--- /dev/null
+sys_arch interface for lwIP 0.6++
+
+Author: Adam Dunkels
+
+The operating system emulation layer provides a common interface
+between the lwIP code and the underlying operating system kernel. The
+general idea is that porting lwIP to new architectures requires only
+small changes to a few header files and a new sys_arch
+implementation. It is also possible to do a sys_arch implementation
+that does not rely on any underlying operating system.
+
+The sys_arch provides semaphores and mailboxes to lwIP. For the full
+lwIP functionality, multiple threads support can be implemented in the
+sys_arch, but this is not required for the basic lwIP
+functionality. Previous versions of lwIP required the sys_arch to
+implement timer scheduling as well but as of lwIP 0.5 this is
+implemented in a higher layer.
+
+In addition to the source file providing the functionality of sys_arch,
+the OS emulation layer must provide several header files defining
+macros used throughout lwip. The files required and the macros they
+must define are listed below the sys_arch description.
+
+Semaphores can be either counting or binary - lwIP works with both
+kinds. Mailboxes are used for message passing and can be implemented
+either as a queue which allows multiple messages to be posted to a
+mailbox, or as a rendez-vous point where only one message can be
+posted at a time. lwIP works with both kinds, but the former type will
+be more efficient. A message in a mailbox is just a pointer, nothing
+more.
+
+Semaphores are represented by the type "sys_sem_t" which is typedef'd
+in the sys_arch.h file. Mailboxes are equivalently represented by the
+type "sys_mbox_t". lwIP does not place any restrictions on how
+sys_sem_t or sys_mbox_t are represented internally.
+
+The following functions must be implemented by the sys_arch:
+
+- void sys_init(void)
+
+ Is called to initialize the sys_arch layer.
+
+- sys_sem_t sys_sem_new(u8_t count)
+
+ Creates and returns a new semaphore. The "count" argument specifies
+ the initial state of the semaphore.
+
+- void sys_sem_free(sys_sem_t sem)
+
+ Deallocates a semaphore.
+
+- void sys_sem_signal(sys_sem_t sem)
+
+ Signals a semaphore.
+
+- u32_t sys_arch_sem_wait(sys_sem_t sem, u32_t timeout)
+
+ Blocks the thread while waiting for the semaphore to be
+ signaled. If the "timeout" argument is non-zero, the thread should
+ only be blocked for the specified time (measured in
+ milliseconds).
+
+ If the timeout argument is non-zero, the return value is the number of
+ milliseconds spent waiting for the semaphore to be signaled. If the
+ semaphore wasn't signaled within the specified time, the return value is
+ SYS_ARCH_TIMEOUT. If the thread didn't have to wait for the semaphore
+ (i.e., it was already signaled), the function may return zero.
+
+ Notice that lwIP implements a function with a similar name,
+ sys_sem_wait(), that uses the sys_arch_sem_wait() function.
+
+- sys_mbox_t sys_mbox_new(void)
+
+ Creates an empty mailbox.
+
+- void sys_mbox_free(sys_mbox_t mbox)
+
+ Deallocates a mailbox. If there are messages still present in the
+ mailbox when the mailbox is deallocated, it is an indication of a
+ programming error in lwIP and the developer should be notified.
+
+- void sys_mbox_post(sys_mbox_t mbox, void *msg)
+
+ Posts the "msg" to the mailbox.
+
+- u32_t sys_arch_mbox_fetch(sys_mbox_t mbox, void **msg, u32_t timeout)
+
+ Blocks the thread until a message arrives in the mailbox, but does
+ not block the thread longer than "timeout" milliseconds (similar to
+ the sys_arch_sem_wait() function). The "msg" argument is a result
+ parameter that is set by the function (i.e., by doing "*msg =
+ ptr"). The "msg" parameter maybe NULL to indicate that the message
+ should be dropped.
+
+ The return values are the same as for the sys_arch_sem_wait() function:
+ Number of milliseconds spent waiting or SYS_ARCH_TIMEOUT if there was a
+ timeout.
+
+ Note that a function with a similar name, sys_mbox_fetch(), is
+ implemented by lwIP.
+
+- struct sys_timeouts *sys_arch_timeouts(void)
+
+ Returns a pointer to the per-thread sys_timeouts structure. In lwIP,
+ each thread has a list of timeouts which is repressented as a linked
+ list of sys_timeout structures. The sys_timeouts structure holds a
+ pointer to a linked list of timeouts. This function is called by
+ the lwIP timeout scheduler and must not return a NULL value.
+
+ In a single threadd sys_arch implementation, this function will
+ simply return a pointer to a global sys_timeouts variable stored in
+ the sys_arch module.
+
+If threads are supported by the underlying operating system and if
+such functionality is needed in lwIP, the following function will have
+to be implemented as well:
+
+- sys_thread_t sys_thread_new(void (* thread)(void *arg), void *arg, int prio)
+
+ Starts a new thread with priority "prio" that will begin its execution in the
+ function "thread()". The "arg" argument will be passed as an argument to the
+ thread() function. The id of the new thread is returned. Both the id and
+ the priority are system dependent.
+
+- sys_prot_t sys_arch_protect(void)
+
+ This optional function does a "fast" critical region protection and returns
+ the previous protection level. This function is only called during very short
+ critical regions. An embedded system which supports ISR-based drivers might
+ want to implement this function by disabling interrupts. Task-based systems
+ might want to implement this by using a mutex or disabling tasking. This
+ function should support recursive calls from the same task or interrupt. In
+ other words, sys_arch_protect() could be called while already protected. In
+ that case the return value indicates that it is already protected.
+
+ sys_arch_protect() is only required if your port is supporting an operating
+ system.
+
+- void sys_arch_unprotect(sys_prot_t pval)
+
+ This optional function does a "fast" set of critical region protection to the
+ value specified by pval. See the documentation for sys_arch_protect() for
+ more information. This function is only required if your port is supporting
+ an operating system.
+
+-------------------------------------------------------------------------------
+Additional files required for the "OS support" emulation layer:
+-------------------------------------------------------------------------------
+
+cc.h - Architecture environment, some compiler specific, some
+ environment specific (probably should move env stuff
+ to sys_arch.h.)
+
+ Typedefs for the types used by lwip -
+ u8_t, s8_t, u16_t, s16_t, u32_t, s32_t, mem_ptr_t
+
+ Compiler hints for packing lwip's structures -
+ PACK_STRUCT_FIELD(x)
+ PACK_STRUCT_STRUCT
+ PACK_STRUCT_BEGIN
+ PACK_STRUCT_END
+
+ Platform specific diagnostic output -
+ LWIP_PLATFORM_DIAG(x) - non-fatal, print a message.
+ LWIP_PLATFORM_ASSERT(x) - fatal, print message and abandon execution.
+
+ "lightweight" synchronization mechanisms -
+ SYS_ARCH_DECL_PROTECT(x) - declare a protection state variable.
+ SYS_ARCH_PROTECT(x) - enter protection mode.
+ SYS_ARCH_UNPROTECT(x) - leave protection mode.
+
+ If the compiler does not provide memset() this file must include a
+ definition of it, or include a file which defines it.
+
+ This file must either include a system-local <errno.h> which defines
+ the standard *nix error codes, or it should #define LWIP_PROVIDE_ERRNO
+ to make lwip/arch.h define the codes which are used throughout.
+
+
+perf.h - Architecture specific performance measurement.
+ Measurement calls made throughout lwip, these can be defined to nothing.
+ PERF_START - start measuring something.
+ PERF_STOP(x) - stop measuring something, and record the result.
+
+sys_arch.h - Tied to sys_arch.c
+
+ Arch dependent types for the following objects:
+ sys_sem_t, sys_mbox_t, sys_thread_t,
+ And, optionally:
+ sys_prot_t
+
+ Defines to set vars of sys_mbox_t and sys_sem_t to NULL.
+ SYS_MBOX_NULL NULL
+ SYS_SEM_NULL NULL
--- /dev/null
+api/ - The code for the high-level wrapper API. Not needed if
+ you use the lowel-level call-back/raw API.
+
+core/ - The core of the TPC/IP stack; protocol implementations,
+ memory and buffer management, and the low-level raw API.
+
+include/ - lwIP include files.
+
+netif/ - Generic network interface device drivers are kept here,
+ as well as the ARP module.
+
+For more information on the various subdirectories, check the FILES
+file in each directory.
--- /dev/null
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+/* This is the part of the API that is linked with
+ the application */
+
+#include "lwip/opt.h"
+#include "lwip/api.h"
+#include "lwip/api_msg.h"
+#include "lwip/memp.h"
+
+
+struct
+netbuf *netbuf_new(void)
+{
+ struct netbuf *buf;
+
+ buf = memp_malloc(MEMP_NETBUF);
+ if (buf != NULL) {
+ buf->p = NULL;
+ buf->ptr = NULL;
+ return buf;
+ } else {
+ return NULL;
+ }
+}
+
+void
+netbuf_delete(struct netbuf *buf)
+{
+ if (buf != NULL) {
+ if (buf->p != NULL) {
+ pbuf_free(buf->p);
+ buf->p = buf->ptr = NULL;
+ }
+ memp_free(MEMP_NETBUF, buf);
+ }
+}
+
+void *
+netbuf_alloc(struct netbuf *buf, u16_t size)
+{
+ /* Deallocate any previously allocated memory. */
+ if (buf->p != NULL) {
+ pbuf_free(buf->p);
+ }
+ buf->p = pbuf_alloc(PBUF_TRANSPORT, size, PBUF_RAM);
+ if (buf->p == NULL) {
+ return NULL;
+ }
+ buf->ptr = buf->p;
+ return buf->p->payload;
+}
+
+void
+netbuf_free(struct netbuf *buf)
+{
+ if (buf->p != NULL) {
+ pbuf_free(buf->p);
+ }
+ buf->p = buf->ptr = NULL;
+}
+
+void
+netbuf_ref(struct netbuf *buf, void *dataptr, u16_t size)
+{
+ if (buf->p != NULL) {
+ pbuf_free(buf->p);
+ }
+ buf->p = pbuf_alloc(PBUF_TRANSPORT, 0, PBUF_REF);
+ buf->p->payload = dataptr;
+ buf->p->len = buf->p->tot_len = size;
+ buf->ptr = buf->p;
+}
+
+void
+netbuf_chain(struct netbuf *head, struct netbuf *tail)
+{
+ pbuf_chain(head->p, tail->p);
+ head->ptr = head->p;
+ memp_free(MEMP_NETBUF, tail);
+}
+
+u16_t
+netbuf_len(struct netbuf *buf)
+{
+ return buf->p->tot_len;
+}
+
+err_t
+netbuf_data(struct netbuf *buf, void **dataptr, u16_t *len)
+{
+ if (buf->ptr == NULL) {
+ return ERR_BUF;
+ }
+ *dataptr = buf->ptr->payload;
+ *len = buf->ptr->len;
+ return ERR_OK;
+}
+
+s8_t
+netbuf_next(struct netbuf *buf)
+{
+ if (buf->ptr->next == NULL) {
+ return -1;
+ }
+ buf->ptr = buf->ptr->next;
+ if (buf->ptr->next == NULL) {
+ return 1;
+ }
+ return 0;
+}
+
+void
+netbuf_first(struct netbuf *buf)
+{
+ buf->ptr = buf->p;
+}
+
+void
+netbuf_copy_partial(struct netbuf *buf, void *dataptr, u16_t len, u16_t offset)
+{
+ struct pbuf *p;
+ u16_t i, left;
+
+ left = 0;
+
+ if(buf == NULL || dataptr == NULL) {
+ return;
+ }
+
+ /* This implementation is bad. It should use bcopy
+ instead. */
+ for(p = buf->p; left < len && p != NULL; p = p->next) {
+ if (offset != 0 && offset >= p->len) {
+ offset -= p->len;
+ } else {
+ for(i = offset; i < p->len; ++i) {
+ ((char *)dataptr)[left] = ((char *)p->payload)[i];
+ if (++left >= len) {
+ return;
+ }
+ }
+ offset = 0;
+ }
+ }
+}
+
+void
+netbuf_copy(struct netbuf *buf, void *dataptr, u16_t len)
+{
+ netbuf_copy_partial(buf, dataptr, len, 0);
+}
+
+struct ip_addr *
+netbuf_fromaddr(struct netbuf *buf)
+{
+ return buf->fromaddr;
+}
+
+u16_t
+netbuf_fromport(struct netbuf *buf)
+{
+ return buf->fromport;
+}
+
+struct
+netconn *netconn_new_with_proto_and_callback(enum netconn_type t, u16_t proto,
+ void (*callback)(struct netconn *, enum netconn_evt, u16_t len))
+{
+ struct netconn *conn;
+ struct api_msg *msg;
+
+ conn = memp_malloc(MEMP_NETCONN);
+ if (conn == NULL) {
+ return NULL;
+ }
+
+ conn->err = ERR_OK;
+ conn->type = t;
+ conn->pcb.tcp = NULL;
+
+ if ((conn->mbox = sys_mbox_new()) == SYS_MBOX_NULL) {
+ memp_free(MEMP_NETCONN, conn);
+ return NULL;
+ }
+ conn->recvmbox = SYS_MBOX_NULL;
+ conn->acceptmbox = SYS_MBOX_NULL;
+ conn->sem = SYS_SEM_NULL;
+ conn->state = NETCONN_NONE;
+ conn->socket = 0;
+ conn->callback = callback;
+ conn->recv_avail = 0;
+
+ if((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
+ memp_free(MEMP_NETCONN, conn);
+ return NULL;
+ }
+
+ msg->type = API_MSG_NEWCONN;
+ msg->msg.msg.bc.port = proto; /* misusing the port field */
+ msg->msg.conn = conn;
+ api_msg_post(msg);
+ sys_mbox_fetch(conn->mbox, NULL);
+ memp_free(MEMP_API_MSG, msg);
+
+ if ( conn->err != ERR_OK ) {
+ memp_free(MEMP_NETCONN, conn);
+ return NULL;
+ }
+
+ return conn;
+}
+
+
+struct
+netconn *netconn_new(enum netconn_type t)
+{
+ return netconn_new_with_proto_and_callback(t,0,NULL);
+}
+
+struct
+netconn *netconn_new_with_callback(enum netconn_type t,
+ void (*callback)(struct netconn *, enum netconn_evt, u16_t len))
+{
+ return netconn_new_with_proto_and_callback(t,0,callback);
+}
+
+
+err_t
+netconn_delete(struct netconn *conn)
+{
+ struct api_msg *msg;
+ void *mem;
+
+ if (conn == NULL) {
+ return ERR_OK;
+ }
+
+ if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
+ return ERR_MEM;
+ }
+
+ msg->type = API_MSG_DELCONN;
+ msg->msg.conn = conn;
+ api_msg_post(msg);
+ sys_mbox_fetch(conn->mbox, NULL);
+ memp_free(MEMP_API_MSG, msg);
+
+ /* Drain the recvmbox. */
+ if (conn->recvmbox != SYS_MBOX_NULL) {
+ while (sys_arch_mbox_fetch(conn->recvmbox, &mem, 1) != SYS_ARCH_TIMEOUT) {
+ if (conn->type == NETCONN_TCP) {
+ if(mem != NULL)
+ pbuf_free((struct pbuf *)mem);
+ } else {
+ netbuf_delete((struct netbuf *)mem);
+ }
+ }
+ sys_mbox_free(conn->recvmbox);
+ conn->recvmbox = SYS_MBOX_NULL;
+ }
+
+
+ /* Drain the acceptmbox. */
+ if (conn->acceptmbox != SYS_MBOX_NULL) {
+ while (sys_arch_mbox_fetch(conn->acceptmbox, &mem, 1) != SYS_ARCH_TIMEOUT) {
+ netconn_delete((struct netconn *)mem);
+ }
+
+ sys_mbox_free(conn->acceptmbox);
+ conn->acceptmbox = SYS_MBOX_NULL;
+ }
+
+ sys_mbox_free(conn->mbox);
+ conn->mbox = SYS_MBOX_NULL;
+ if (conn->sem != SYS_SEM_NULL) {
+ sys_sem_free(conn->sem);
+ }
+ /* conn->sem = SYS_SEM_NULL;*/
+ memp_free(MEMP_NETCONN, conn);
+ return ERR_OK;
+}
+
+enum netconn_type
+netconn_type(struct netconn *conn)
+{
+ return conn->type;
+}
+
+err_t
+netconn_peer(struct netconn *conn, struct ip_addr *addr,
+ u16_t *port)
+{
+ switch (conn->type) {
+ case NETCONN_RAW:
+ /* return an error as connecting is only a helper for upper layers */
+ return ERR_CONN;
+ case NETCONN_UDPLITE:
+ case NETCONN_UDPNOCHKSUM:
+ case NETCONN_UDP:
+ if (conn->pcb.udp == NULL ||
+ ((conn->pcb.udp->flags & UDP_FLAGS_CONNECTED) == 0))
+ return ERR_CONN;
+ *addr = (conn->pcb.udp->remote_ip);
+ *port = conn->pcb.udp->remote_port;
+ break;
+ case NETCONN_TCP:
+ if (conn->pcb.tcp == NULL)
+ return ERR_CONN;
+ *addr = (conn->pcb.tcp->remote_ip);
+ *port = conn->pcb.tcp->remote_port;
+ break;
+ }
+ return (conn->err = ERR_OK);
+}
+
+err_t
+netconn_addr(struct netconn *conn, struct ip_addr **addr,
+ u16_t *port)
+{
+ switch (conn->type) {
+ case NETCONN_RAW:
+ *addr = &(conn->pcb.raw->local_ip);
+ *port = conn->pcb.raw->protocol;
+ break;
+ case NETCONN_UDPLITE:
+ case NETCONN_UDPNOCHKSUM:
+ case NETCONN_UDP:
+ *addr = &(conn->pcb.udp->local_ip);
+ *port = conn->pcb.udp->local_port;
+ break;
+ case NETCONN_TCP:
+ *addr = &(conn->pcb.tcp->local_ip);
+ *port = conn->pcb.tcp->local_port;
+ break;
+ }
+ return (conn->err = ERR_OK);
+}
+
+err_t
+netconn_bind(struct netconn *conn, struct ip_addr *addr,
+ u16_t port)
+{
+ struct api_msg *msg;
+
+ if (conn == NULL) {
+ return ERR_VAL;
+ }
+
+ if (conn->type != NETCONN_TCP &&
+ conn->recvmbox == SYS_MBOX_NULL) {
+ if ((conn->recvmbox = sys_mbox_new()) == SYS_MBOX_NULL) {
+ return ERR_MEM;
+ }
+ }
+
+ if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
+ return (conn->err = ERR_MEM);
+ }
+ msg->type = API_MSG_BIND;
+ msg->msg.conn = conn;
+ msg->msg.msg.bc.ipaddr = addr;
+ msg->msg.msg.bc.port = port;
+ api_msg_post(msg);
+ sys_mbox_fetch(conn->mbox, NULL);
+ memp_free(MEMP_API_MSG, msg);
+ return conn->err;
+}
+
+
+err_t
+netconn_connect(struct netconn *conn, struct ip_addr *addr,
+ u16_t port)
+{
+ struct api_msg *msg;
+
+ if (conn == NULL) {
+ return ERR_VAL;
+ }
+
+
+ if (conn->recvmbox == SYS_MBOX_NULL) {
+ if ((conn->recvmbox = sys_mbox_new()) == SYS_MBOX_NULL) {
+ return ERR_MEM;
+ }
+ }
+
+ if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
+ return ERR_MEM;
+ }
+ msg->type = API_MSG_CONNECT;
+ msg->msg.conn = conn;
+ msg->msg.msg.bc.ipaddr = addr;
+ msg->msg.msg.bc.port = port;
+ api_msg_post(msg);
+ sys_mbox_fetch(conn->mbox, NULL);
+ memp_free(MEMP_API_MSG, msg);
+ return conn->err;
+}
+
+err_t
+netconn_disconnect(struct netconn *conn)
+{
+ struct api_msg *msg;
+
+ if (conn == NULL) {
+ return ERR_VAL;
+ }
+
+ if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
+ return ERR_MEM;
+ }
+ msg->type = API_MSG_DISCONNECT;
+ msg->msg.conn = conn;
+ api_msg_post(msg);
+ sys_mbox_fetch(conn->mbox, NULL);
+ memp_free(MEMP_API_MSG, msg);
+ return conn->err;
+
+}
+
+err_t
+netconn_listen(struct netconn *conn)
+{
+ struct api_msg *msg;
+
+ if (conn == NULL) {
+ return ERR_VAL;
+ }
+
+ if (conn->acceptmbox == SYS_MBOX_NULL) {
+ conn->acceptmbox = sys_mbox_new();
+ if (conn->acceptmbox == SYS_MBOX_NULL) {
+ return ERR_MEM;
+ }
+ }
+
+ if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
+ return (conn->err = ERR_MEM);
+ }
+ msg->type = API_MSG_LISTEN;
+ msg->msg.conn = conn;
+ api_msg_post(msg);
+ sys_mbox_fetch(conn->mbox, NULL);
+ memp_free(MEMP_API_MSG, msg);
+ return conn->err;
+}
+
+struct netconn *
+netconn_accept(struct netconn *conn)
+{
+ struct netconn *newconn;
+
+ if (conn == NULL) {
+ return NULL;
+ }
+
+ sys_mbox_fetch(conn->acceptmbox, (void **)&newconn);
+ /* Register event with callback */
+ if (conn->callback)
+ (*conn->callback)(conn, NETCONN_EVT_RCVMINUS, 0);
+
+ return newconn;
+}
+
+struct netbuf *
+netconn_recv(struct netconn *conn)
+{
+ struct api_msg *msg;
+ struct netbuf *buf;
+ struct pbuf *p;
+ u16_t len;
+
+ if (conn == NULL) {
+ return NULL;
+ }
+
+ if (conn->recvmbox == SYS_MBOX_NULL) {
+ conn->err = ERR_CONN;
+ return NULL;
+ }
+
+ if (conn->err != ERR_OK) {
+ return NULL;
+ }
+
+ if (conn->type == NETCONN_TCP) {
+ if (conn->pcb.tcp->state == LISTEN) {
+ conn->err = ERR_CONN;
+ return NULL;
+ }
+
+
+ buf = memp_malloc(MEMP_NETBUF);
+
+ if (buf == NULL) {
+ conn->err = ERR_MEM;
+ return NULL;
+ }
+
+ sys_mbox_fetch(conn->recvmbox, (void **)&p);
+
+ if (p != NULL)
+ {
+ len = p->tot_len;
+ conn->recv_avail -= len;
+ }
+ else
+ len = 0;
+
+ /* Register event with callback */
+ if (conn->callback)
+ (*conn->callback)(conn, NETCONN_EVT_RCVMINUS, len);
+
+ /* If we are closed, we indicate that we no longer wish to receive
+ data by setting conn->recvmbox to SYS_MBOX_NULL. */
+ if (p == NULL) {
+ memp_free(MEMP_NETBUF, buf);
+ sys_mbox_free(conn->recvmbox);
+ conn->recvmbox = SYS_MBOX_NULL;
+ return NULL;
+ }
+
+ buf->p = p;
+ buf->ptr = p;
+ buf->fromport = 0;
+ buf->fromaddr = NULL;
+
+ /* Let the stack know that we have taken the data. */
+ if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
+ conn->err = ERR_MEM;
+ return buf;
+ }
+ msg->type = API_MSG_RECV;
+ msg->msg.conn = conn;
+ if (buf != NULL) {
+ msg->msg.msg.len = buf->p->tot_len;
+ } else {
+ msg->msg.msg.len = 1;
+ }
+ api_msg_post(msg);
+
+ sys_mbox_fetch(conn->mbox, NULL);
+ memp_free(MEMP_API_MSG, msg);
+ } else {
+ sys_mbox_fetch(conn->recvmbox, (void **)&buf);
+ conn->recv_avail -= buf->p->tot_len;
+ /* Register event with callback */
+ if (conn->callback)
+ (*conn->callback)(conn, NETCONN_EVT_RCVMINUS, buf->p->tot_len);
+ }
+
+
+
+
+ LWIP_DEBUGF(API_LIB_DEBUG, ("netconn_recv: received %p (err %d)\n", (void *)buf, conn->err));
+
+
+ return buf;
+}
+
+err_t
+netconn_send(struct netconn *conn, struct netbuf *buf)
+{
+ struct api_msg *msg;
+
+ if (conn == NULL) {
+ return ERR_VAL;
+ }
+
+ if (conn->err != ERR_OK) {
+ return conn->err;
+ }
+
+ if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
+ return (conn->err = ERR_MEM);
+ }
+
+ LWIP_DEBUGF(API_LIB_DEBUG, ("netconn_send: sending %d bytes\n", buf->p->tot_len));
+ msg->type = API_MSG_SEND;
+ msg->msg.conn = conn;
+ msg->msg.msg.p = buf->p;
+ api_msg_post(msg);
+
+ sys_mbox_fetch(conn->mbox, NULL);
+ memp_free(MEMP_API_MSG, msg);
+ return conn->err;
+}
+
+err_t
+netconn_write(struct netconn *conn, void *dataptr, u16_t size, u8_t copy)
+{
+ struct api_msg *msg;
+ u16_t len;
+
+ if (conn == NULL) {
+ return ERR_VAL;
+ }
+
+ if (conn->err != ERR_OK) {
+ return conn->err;
+ }
+
+ if (conn->sem == SYS_SEM_NULL) {
+ conn->sem = sys_sem_new(0);
+ if (conn->sem == SYS_SEM_NULL) {
+ return ERR_MEM;
+ }
+ }
+
+ if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
+ return (conn->err = ERR_MEM);
+ }
+ msg->type = API_MSG_WRITE;
+ msg->msg.conn = conn;
+
+
+ conn->state = NETCONN_WRITE;
+ while (conn->err == ERR_OK && size > 0) {
+ msg->msg.msg.w.dataptr = dataptr;
+ msg->msg.msg.w.copy = copy;
+
+ if (conn->type == NETCONN_TCP) {
+ if (tcp_sndbuf(conn->pcb.tcp) == 0) {
+ sys_sem_wait(conn->sem);
+ if (conn->err != ERR_OK) {
+ goto ret;
+ }
+ }
+ if (size > tcp_sndbuf(conn->pcb.tcp)) {
+ /* We cannot send more than one send buffer's worth of data at a
+ time. */
+ len = tcp_sndbuf(conn->pcb.tcp);
+ } else {
+ len = size;
+ }
+ } else {
+ len = size;
+ }
+
+ LWIP_DEBUGF(API_LIB_DEBUG, ("netconn_write: writing %d bytes (%d)\n", len, copy));
+ msg->msg.msg.w.len = len;
+ api_msg_post(msg);
+ sys_mbox_fetch(conn->mbox, NULL);
+ if (conn->err == ERR_OK) {
+ dataptr = (void *)((char *)dataptr + len);
+ size -= len;
+ } else if (conn->err == ERR_MEM) {
+ conn->err = ERR_OK;
+ sys_sem_wait(conn->sem);
+ } else {
+ goto ret;
+ }
+ }
+ ret:
+ memp_free(MEMP_API_MSG, msg);
+ conn->state = NETCONN_NONE;
+ if (conn->sem != SYS_SEM_NULL) {
+ sys_sem_free(conn->sem);
+ conn->sem = SYS_SEM_NULL;
+ }
+
+ return conn->err;
+}
+
+err_t
+netconn_close(struct netconn *conn)
+{
+ struct api_msg *msg;
+
+ if (conn == NULL) {
+ return ERR_VAL;
+ }
+ if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
+ return (conn->err = ERR_MEM);
+ }
+
+ conn->state = NETCONN_CLOSE;
+ again:
+ msg->type = API_MSG_CLOSE;
+ msg->msg.conn = conn;
+ api_msg_post(msg);
+ sys_mbox_fetch(conn->mbox, NULL);
+ if (conn->err == ERR_MEM &&
+ conn->sem != SYS_SEM_NULL) {
+ sys_sem_wait(conn->sem);
+ goto again;
+ }
+ conn->state = NETCONN_NONE;
+ memp_free(MEMP_API_MSG, msg);
+ return conn->err;
+}
+
+err_t
+netconn_err(struct netconn *conn)
+{
+ return conn->err;
+}
+
--- /dev/null
+/*\r
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.\r
+ * All rights reserved. \r
+ * \r
+ * Redistribution and use in source and binary forms, with or without modification, \r
+ * are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. The name of the author may not be used to endorse or promote products\r
+ * derived from this software without specific prior written permission. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED \r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT \r
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, \r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT \r
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS \r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN \r
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING \r
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY \r
+ * OF SUCH DAMAGE.\r
+ *\r
+ * This file is part of the lwIP TCP/IP stack.\r
+ * \r
+ * Author: Adam Dunkels <adam@sics.se>\r
+ *\r
+ */\r
+\r
+#include "lwip/opt.h"\r
+#include "lwip/arch.h"\r
+#include "lwip/api_msg.h"\r
+#include "lwip/memp.h"\r
+#include "lwip/sys.h"\r
+#include "lwip/tcpip.h"\r
+\r
+#if LWIP_RAW\r
+static u8_t\r
+recv_raw(void *arg, struct raw_pcb *pcb, struct pbuf *p,\r
+ struct ip_addr *addr)\r
+{\r
+ struct netbuf *buf;\r
+ struct netconn *conn;\r
+\r
+ conn = arg;\r
+ if (!conn) return 0;\r
+\r
+ if (conn->recvmbox != SYS_MBOX_NULL) {\r
+ if (!(buf = memp_malloc(MEMP_NETBUF))) {\r
+ return 0;\r
+ }\r
+ pbuf_ref(p);\r
+ buf->p = p;\r
+ buf->ptr = p;\r
+ buf->fromaddr = addr;\r
+ buf->fromport = pcb->protocol;\r
+\r
+ conn->recv_avail += p->tot_len;\r
+ /* Register event with callback */\r
+ if (conn->callback)\r
+ (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, p->tot_len);\r
+ sys_mbox_post(conn->recvmbox, buf);\r
+ }\r
+\r
+ return 0; /* do not eat the packet */\r
+}\r
+#endif\r
+#if LWIP_UDP\r
+static void\r
+recv_udp(void *arg, struct udp_pcb *pcb, struct pbuf *p,\r
+ struct ip_addr *addr, u16_t port)\r
+{\r
+ struct netbuf *buf;\r
+ struct netconn *conn;\r
+\r
+ (void)pcb;\r
+\r
+ conn = arg;\r
+ \r
+ if (conn == NULL) {\r
+ pbuf_free(p);\r
+ return;\r
+ }\r
+ if (conn->recvmbox != SYS_MBOX_NULL) {\r
+ buf = memp_malloc(MEMP_NETBUF);\r
+ if (buf == NULL) {\r
+ pbuf_free(p);\r
+ return;\r
+ } else {\r
+ buf->p = p;\r
+ buf->ptr = p;\r
+ buf->fromaddr = addr;\r
+ buf->fromport = port;\r
+ }\r
+\r
+ conn->recv_avail += p->tot_len;\r
+ /* Register event with callback */\r
+ if (conn->callback)\r
+ (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, p->tot_len);\r
+ sys_mbox_post(conn->recvmbox, buf);\r
+ }\r
+}\r
+#endif /* LWIP_UDP */\r
+#if LWIP_TCP\r
+\r
+static err_t\r
+recv_tcp(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err)\r
+{\r
+ struct netconn *conn;\r
+ u16_t len;\r
+\r
+ (void)pcb;\r
+\r
+ conn = arg;\r
+\r
+ if (conn == NULL) {\r
+ pbuf_free(p);\r
+ return ERR_VAL;\r
+ }\r
+\r
+ if (conn->recvmbox != SYS_MBOX_NULL) {\r
+ \r
+ conn->err = err;\r
+ if (p != NULL) {\r
+ len = p->tot_len;\r
+ conn->recv_avail += len;\r
+ }\r
+ else\r
+ len = 0;\r
+ /* Register event with callback */\r
+ if (conn->callback)\r
+ (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, len);\r
+ sys_mbox_post(conn->recvmbox, p);\r
+ } \r
+ return ERR_OK;\r
+}\r
+\r
+\r
+static err_t\r
+poll_tcp(void *arg, struct tcp_pcb *pcb)\r
+{\r
+ struct netconn *conn;\r
+\r
+ (void)pcb;\r
+\r
+ conn = arg;\r
+ if (conn != NULL &&\r
+ (conn->state == NETCONN_WRITE || conn->state == NETCONN_CLOSE) &&\r
+ conn->sem != SYS_SEM_NULL) {\r
+ sys_sem_signal(conn->sem);\r
+ }\r
+ return ERR_OK;\r
+}\r
+\r
+static err_t\r
+sent_tcp(void *arg, struct tcp_pcb *pcb, u16_t len)\r
+{\r
+ struct netconn *conn;\r
+\r
+ (void)pcb;\r
+\r
+ conn = arg;\r
+ if (conn != NULL && conn->sem != SYS_SEM_NULL) {\r
+ sys_sem_signal(conn->sem);\r
+ }\r
+\r
+ if (conn && conn->callback)\r
+ if (tcp_sndbuf(conn->pcb.tcp) > TCP_SNDLOWAT)\r
+ (*conn->callback)(conn, NETCONN_EVT_SENDPLUS, len);\r
+ \r
+ return ERR_OK;\r
+}\r
+\r
+static void\r
+err_tcp(void *arg, err_t err)\r
+{\r
+ struct netconn *conn;\r
+\r
+ conn = arg;\r
+\r
+ conn->pcb.tcp = NULL;\r
+\r
+ \r
+ conn->err = err;\r
+ if (conn->recvmbox != SYS_MBOX_NULL) {\r
+ /* Register event with callback */\r
+ if (conn->callback)\r
+ (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, 0);\r
+ sys_mbox_post(conn->recvmbox, NULL);\r
+ }\r
+ if (conn->mbox != SYS_MBOX_NULL) {\r
+ sys_mbox_post(conn->mbox, NULL);\r
+ }\r
+ if (conn->acceptmbox != SYS_MBOX_NULL) {\r
+ /* Register event with callback */\r
+ if (conn->callback)\r
+ (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, 0);\r
+ sys_mbox_post(conn->acceptmbox, NULL);\r
+ }\r
+ if (conn->sem != SYS_SEM_NULL) {\r
+ sys_sem_signal(conn->sem);\r
+ }\r
+}\r
+\r
+static void\r
+setup_tcp(struct netconn *conn)\r
+{\r
+ struct tcp_pcb *pcb;\r
+ \r
+ pcb = conn->pcb.tcp;\r
+ tcp_arg(pcb, conn);\r
+ tcp_recv(pcb, recv_tcp);\r
+ tcp_sent(pcb, sent_tcp);\r
+ tcp_poll(pcb, poll_tcp, 4);\r
+ tcp_err(pcb, err_tcp);\r
+}\r
+\r
+static err_t\r
+accept_function(void *arg, struct tcp_pcb *newpcb, err_t err)\r
+{\r
+ sys_mbox_t mbox;\r
+ struct netconn *newconn;\r
+ struct netconn *conn;\r
+ \r
+#if API_MSG_DEBUG\r
+#if TCP_DEBUG\r
+ tcp_debug_print_state(newpcb->state);\r
+#endif /* TCP_DEBUG */\r
+#endif /* API_MSG_DEBUG */\r
+ conn = (struct netconn *)arg;\r
+ mbox = conn->acceptmbox;\r
+ newconn = memp_malloc(MEMP_NETCONN);\r
+ if (newconn == NULL) {\r
+ return ERR_MEM;\r
+ }\r
+ newconn->type = NETCONN_TCP;\r
+ newconn->pcb.tcp = newpcb;\r
+ setup_tcp(newconn);\r
+ newconn->recvmbox = sys_mbox_new();\r
+ if (newconn->recvmbox == SYS_MBOX_NULL) {\r
+ memp_free(MEMP_NETCONN, newconn);\r
+ return ERR_MEM;\r
+ }\r
+ newconn->mbox = sys_mbox_new();\r
+ if (newconn->mbox == SYS_MBOX_NULL) {\r
+ sys_mbox_free(newconn->recvmbox);\r
+ memp_free(MEMP_NETCONN, newconn);\r
+ return ERR_MEM;\r
+ }\r
+ newconn->sem = sys_sem_new(0);\r
+ if (newconn->sem == SYS_SEM_NULL) {\r
+ sys_mbox_free(newconn->recvmbox);\r
+ sys_mbox_free(newconn->mbox);\r
+ memp_free(MEMP_NETCONN, newconn);\r
+ return ERR_MEM;\r
+ }\r
+ newconn->acceptmbox = SYS_MBOX_NULL;\r
+ newconn->err = err;\r
+ /* Register event with callback */\r
+ if (conn->callback)\r
+ {\r
+ (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, 0);\r
+ /* We have to set the callback here even though\r
+ * the new socket is unknown. Mark the socket as -1. */\r
+ newconn->callback = conn->callback;\r
+ newconn->socket = -1;\r
+ }\r
+ \r
+ sys_mbox_post(mbox, newconn);\r
+ return ERR_OK;\r
+}\r
+#endif /* LWIP_TCP */\r
+\r
+static void\r
+do_newconn(struct api_msg_msg *msg)\r
+{\r
+ if(msg->conn->pcb.tcp != NULL) {\r
+ /* This "new" connection already has a PCB allocated. */\r
+ /* Is this an error condition? Should it be deleted? \r
+ We currently just are happy and return. */\r
+ sys_mbox_post(msg->conn->mbox, NULL);\r
+ return;\r
+ }\r
+\r
+ msg->conn->err = ERR_OK;\r
+\r
+ /* Allocate a PCB for this connection */\r
+ switch(msg->conn->type) {\r
+#if LWIP_RAW\r
+ case NETCONN_RAW:\r
+ msg->conn->pcb.raw = raw_new(msg->msg.bc.port); /* misusing the port field */\r
+ raw_recv(msg->conn->pcb.raw, recv_raw, msg->conn);\r
+ break;\r
+#endif\r
+#if LWIP_UDP\r
+ case NETCONN_UDPLITE:\r
+ msg->conn->pcb.udp = udp_new();\r
+ if(msg->conn->pcb.udp == NULL) {\r
+ msg->conn->err = ERR_MEM;\r
+ break;\r
+ }\r
+ udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_UDPLITE);\r
+ udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);\r
+ break;\r
+ case NETCONN_UDPNOCHKSUM:\r
+ msg->conn->pcb.udp = udp_new();\r
+ if(msg->conn->pcb.udp == NULL) {\r
+ msg->conn->err = ERR_MEM;\r
+ break;\r
+ }\r
+ udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_NOCHKSUM);\r
+ udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);\r
+ break;\r
+ case NETCONN_UDP:\r
+ msg->conn->pcb.udp = udp_new();\r
+ if(msg->conn->pcb.udp == NULL) {\r
+ msg->conn->err = ERR_MEM;\r
+ break;\r
+ }\r
+ udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);\r
+ break;\r
+#endif /* LWIP_UDP */\r
+#if LWIP_TCP\r
+ case NETCONN_TCP:\r
+ msg->conn->pcb.tcp = tcp_new();\r
+ if(msg->conn->pcb.tcp == NULL) {\r
+ msg->conn->err = ERR_MEM;\r
+ break;\r
+ }\r
+ setup_tcp(msg->conn);\r
+ break;\r
+#endif\r
+ }\r
+ \r
+ \r
+ sys_mbox_post(msg->conn->mbox, NULL);\r
+}\r
+\r
+\r
+static void\r
+do_delconn(struct api_msg_msg *msg)\r
+{\r
+ if (msg->conn->pcb.tcp != NULL) {\r
+ switch (msg->conn->type) {\r
+#if LWIP_RAW\r
+ case NETCONN_RAW:\r
+ raw_remove(msg->conn->pcb.raw);\r
+ break;\r
+#endif\r
+#if LWIP_UDP\r
+ case NETCONN_UDPLITE:\r
+ /* FALLTHROUGH */\r
+ case NETCONN_UDPNOCHKSUM:\r
+ /* FALLTHROUGH */\r
+ case NETCONN_UDP:\r
+ msg->conn->pcb.udp->recv_arg = NULL;\r
+ udp_remove(msg->conn->pcb.udp);\r
+ break;\r
+#endif /* LWIP_UDP */\r
+#if LWIP_TCP \r
+ case NETCONN_TCP:\r
+ if (msg->conn->pcb.tcp->state == LISTEN) {\r
+ tcp_arg(msg->conn->pcb.tcp, NULL);\r
+ tcp_accept(msg->conn->pcb.tcp, NULL); \r
+ tcp_close(msg->conn->pcb.tcp);\r
+ } else {\r
+ tcp_arg(msg->conn->pcb.tcp, NULL);\r
+ tcp_sent(msg->conn->pcb.tcp, NULL);\r
+ tcp_recv(msg->conn->pcb.tcp, NULL); \r
+ tcp_poll(msg->conn->pcb.tcp, NULL, 0);\r
+ tcp_err(msg->conn->pcb.tcp, NULL);\r
+ if (tcp_close(msg->conn->pcb.tcp) != ERR_OK) {\r
+ tcp_abort(msg->conn->pcb.tcp);\r
+ }\r
+ }\r
+#endif\r
+ default: \r
+ break;\r
+ }\r
+ }\r
+ /* Trigger select() in socket layer */\r
+ if (msg->conn->callback)\r
+ {\r
+ (*msg->conn->callback)(msg->conn, NETCONN_EVT_RCVPLUS, 0);\r
+ (*msg->conn->callback)(msg->conn, NETCONN_EVT_SENDPLUS, 0);\r
+ }\r
+ \r
+ if (msg->conn->mbox != SYS_MBOX_NULL) {\r
+ sys_mbox_post(msg->conn->mbox, NULL);\r
+ }\r
+}\r
+\r
+static void\r
+do_bind(struct api_msg_msg *msg)\r
+{\r
+ if (msg->conn->pcb.tcp == NULL) {\r
+ switch (msg->conn->type) {\r
+#if LWIP_RAW\r
+ case NETCONN_RAW:\r
+ msg->conn->pcb.raw = raw_new(msg->msg.bc.port); /* misusing the port field as protocol */\r
+ raw_recv(msg->conn->pcb.raw, recv_raw, msg->conn);\r
+ break;\r
+#endif\r
+#if LWIP_UDP\r
+ case NETCONN_UDPLITE:\r
+ msg->conn->pcb.udp = udp_new();\r
+ udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_UDPLITE);\r
+ udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);\r
+ break;\r
+ case NETCONN_UDPNOCHKSUM:\r
+ msg->conn->pcb.udp = udp_new();\r
+ udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_NOCHKSUM);\r
+ udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);\r
+ break;\r
+ case NETCONN_UDP:\r
+ msg->conn->pcb.udp = udp_new();\r
+ udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);\r
+ break;\r
+#endif /* LWIP_UDP */\r
+#if LWIP_TCP \r
+ case NETCONN_TCP:\r
+ msg->conn->pcb.tcp = tcp_new();\r
+ setup_tcp(msg->conn);\r
+#endif /* LWIP_TCP */\r
+ default: \r
+ break;\r
+ }\r
+ }\r
+ switch (msg->conn->type) {\r
+#if LWIP_RAW\r
+ case NETCONN_RAW:\r
+ msg->conn->err = raw_bind(msg->conn->pcb.raw,msg->msg.bc.ipaddr);\r
+ break;\r
+#endif\r
+#if LWIP_UDP\r
+ case NETCONN_UDPLITE:\r
+ /* FALLTHROUGH */\r
+ case NETCONN_UDPNOCHKSUM:\r
+ /* FALLTHROUGH */\r
+ case NETCONN_UDP:\r
+ msg->conn->err = udp_bind(msg->conn->pcb.udp, msg->msg.bc.ipaddr, msg->msg.bc.port);\r
+ break;\r
+#endif /* LWIP_UDP */\r
+#if LWIP_TCP\r
+ case NETCONN_TCP:\r
+ msg->conn->err = tcp_bind(msg->conn->pcb.tcp,\r
+ msg->msg.bc.ipaddr, msg->msg.bc.port);\r
+#endif /* LWIP_TCP */\r
+ default:\r
+ break;\r
+ }\r
+ sys_mbox_post(msg->conn->mbox, NULL);\r
+}\r
+#if LWIP_TCP\r
+\r
+static err_t\r
+do_connected(void *arg, struct tcp_pcb *pcb, err_t err)\r
+{\r
+ struct netconn *conn;\r
+\r
+ (void)pcb;\r
+\r
+ conn = arg;\r
+\r
+ if (conn == NULL) {\r
+ return ERR_VAL;\r
+ }\r
+ \r
+ conn->err = err;\r
+ if (conn->type == NETCONN_TCP && err == ERR_OK) {\r
+ setup_tcp(conn);\r
+ } \r
+ sys_mbox_post(conn->mbox, NULL);\r
+ return ERR_OK;\r
+}\r
+#endif \r
+\r
+static void\r
+do_connect(struct api_msg_msg *msg)\r
+{\r
+ if (msg->conn->pcb.tcp == NULL) {\r
+ switch (msg->conn->type) {\r
+#if LWIP_RAW\r
+ case NETCONN_RAW:\r
+ msg->conn->pcb.raw = raw_new(msg->msg.bc.port); /* misusing the port field as protocol */\r
+ raw_recv(msg->conn->pcb.raw, recv_raw, msg->conn);\r
+ break;\r
+#endif\r
+#if LWIP_UDP\r
+ case NETCONN_UDPLITE:\r
+ msg->conn->pcb.udp = udp_new();\r
+ if (msg->conn->pcb.udp == NULL) {\r
+ msg->conn->err = ERR_MEM;\r
+ sys_mbox_post(msg->conn->mbox, NULL);\r
+ return;\r
+ }\r
+ udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_UDPLITE);\r
+ udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);\r
+ break;\r
+ case NETCONN_UDPNOCHKSUM:\r
+ msg->conn->pcb.udp = udp_new();\r
+ if (msg->conn->pcb.udp == NULL) {\r
+ msg->conn->err = ERR_MEM;\r
+ sys_mbox_post(msg->conn->mbox, NULL);\r
+ return;\r
+ }\r
+ udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_NOCHKSUM);\r
+ udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);\r
+ break;\r
+ case NETCONN_UDP:\r
+ msg->conn->pcb.udp = udp_new();\r
+ if (msg->conn->pcb.udp == NULL) {\r
+ msg->conn->err = ERR_MEM;\r
+ sys_mbox_post(msg->conn->mbox, NULL);\r
+ return;\r
+ }\r
+ udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);\r
+ break;\r
+#endif /* LWIP_UDP */\r
+#if LWIP_TCP \r
+ case NETCONN_TCP:\r
+ msg->conn->pcb.tcp = tcp_new(); \r
+ if (msg->conn->pcb.tcp == NULL) {\r
+ msg->conn->err = ERR_MEM;\r
+ sys_mbox_post(msg->conn->mbox, NULL);\r
+ return;\r
+ }\r
+#endif\r
+ default:\r
+ break;\r
+ }\r
+ }\r
+ switch (msg->conn->type) {\r
+#if LWIP_RAW\r
+ case NETCONN_RAW:\r
+ raw_connect(msg->conn->pcb.raw, msg->msg.bc.ipaddr);\r
+ sys_mbox_post(msg->conn->mbox, NULL);\r
+ break;\r
+#endif\r
+#if LWIP_UDP\r
+ case NETCONN_UDPLITE:\r
+ /* FALLTHROUGH */\r
+ case NETCONN_UDPNOCHKSUM:\r
+ /* FALLTHROUGH */\r
+ case NETCONN_UDP:\r
+ udp_connect(msg->conn->pcb.udp, msg->msg.bc.ipaddr, msg->msg.bc.port);\r
+ sys_mbox_post(msg->conn->mbox, NULL);\r
+ break;\r
+#endif \r
+#if LWIP_TCP \r
+ case NETCONN_TCP:\r
+ /* tcp_arg(msg->conn->pcb.tcp, msg->conn);*/\r
+ setup_tcp(msg->conn);\r
+ tcp_connect(msg->conn->pcb.tcp, msg->msg.bc.ipaddr, msg->msg.bc.port,\r
+ do_connected);\r
+ /*tcp_output(msg->conn->pcb.tcp);*/\r
+#endif\r
+\r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+static void\r
+do_disconnect(struct api_msg_msg *msg)\r
+{\r
+\r
+ switch (msg->conn->type) {\r
+#if LWIP_RAW\r
+ case NETCONN_RAW:\r
+ /* Do nothing as connecting is only a helper for upper lwip layers */\r
+ break;\r
+#endif\r
+#if LWIP_UDP\r
+ case NETCONN_UDPLITE:\r
+ /* FALLTHROUGH */\r
+ case NETCONN_UDPNOCHKSUM:\r
+ /* FALLTHROUGH */\r
+ case NETCONN_UDP:\r
+ udp_disconnect(msg->conn->pcb.udp);\r
+ break;\r
+#endif \r
+ case NETCONN_TCP:\r
+ break;\r
+ }\r
+ sys_mbox_post(msg->conn->mbox, NULL);\r
+}\r
+\r
+\r
+static void\r
+do_listen(struct api_msg_msg *msg)\r
+{\r
+ if (msg->conn->pcb.tcp != NULL) {\r
+ switch (msg->conn->type) {\r
+#if LWIP_RAW\r
+ case NETCONN_RAW:\r
+ LWIP_DEBUGF(API_MSG_DEBUG, ("api_msg: listen RAW: cannot listen for RAW.\n"));\r
+ break;\r
+#endif\r
+#if LWIP_UDP\r
+ case NETCONN_UDPLITE:\r
+ /* FALLTHROUGH */\r
+ case NETCONN_UDPNOCHKSUM:\r
+ /* FALLTHROUGH */\r
+ case NETCONN_UDP:\r
+ LWIP_DEBUGF(API_MSG_DEBUG, ("api_msg: listen UDP: cannot listen for UDP.\n"));\r
+ break;\r
+#endif /* LWIP_UDP */\r
+#if LWIP_TCP \r
+ case NETCONN_TCP:\r
+ msg->conn->pcb.tcp = tcp_listen(msg->conn->pcb.tcp);\r
+ if (msg->conn->pcb.tcp == NULL) {\r
+ msg->conn->err = ERR_MEM;\r
+ } else {\r
+ if (msg->conn->acceptmbox == SYS_MBOX_NULL) {\r
+ msg->conn->acceptmbox = sys_mbox_new();\r
+ if (msg->conn->acceptmbox == SYS_MBOX_NULL) {\r
+ msg->conn->err = ERR_MEM;\r
+ break;\r
+ }\r
+ }\r
+ tcp_arg(msg->conn->pcb.tcp, msg->conn);\r
+ tcp_accept(msg->conn->pcb.tcp, accept_function);\r
+ }\r
+#endif\r
+ default:\r
+ break;\r
+ }\r
+ }\r
+ sys_mbox_post(msg->conn->mbox, NULL);\r
+}\r
+\r
+static void\r
+do_accept(struct api_msg_msg *msg)\r
+{\r
+ if (msg->conn->pcb.tcp != NULL) {\r
+ switch (msg->conn->type) {\r
+#if LWIP_RAW\r
+ case NETCONN_RAW:\r
+ LWIP_DEBUGF(API_MSG_DEBUG, ("api_msg: accept RAW: cannot accept for RAW.\n"));\r
+ break;\r
+#endif\r
+#if LWIP_UDP\r
+ case NETCONN_UDPLITE:\r
+ /* FALLTHROUGH */\r
+ case NETCONN_UDPNOCHKSUM:\r
+ /* FALLTHROUGH */\r
+ case NETCONN_UDP: \r
+ LWIP_DEBUGF(API_MSG_DEBUG, ("api_msg: accept UDP: cannot accept for UDP.\n"));\r
+ break;\r
+#endif /* LWIP_UDP */\r
+ case NETCONN_TCP:\r
+ break;\r
+ }\r
+ }\r
+}\r
+\r
+static void\r
+do_send(struct api_msg_msg *msg)\r
+{\r
+ if (msg->conn->pcb.tcp != NULL) {\r
+ switch (msg->conn->type) {\r
+#if LWIP_RAW\r
+ case NETCONN_RAW:\r
+ raw_send(msg->conn->pcb.raw, msg->msg.p);\r
+ break;\r
+#endif\r
+#if LWIP_UDP\r
+ case NETCONN_UDPLITE:\r
+ /* FALLTHROUGH */\r
+ case NETCONN_UDPNOCHKSUM:\r
+ /* FALLTHROUGH */\r
+ case NETCONN_UDP:\r
+ udp_send(msg->conn->pcb.udp, msg->msg.p);\r
+ break;\r
+#endif /* LWIP_UDP */\r
+ case NETCONN_TCP:\r
+ break;\r
+ }\r
+ }\r
+ sys_mbox_post(msg->conn->mbox, NULL);\r
+}\r
+\r
+static void\r
+do_recv(struct api_msg_msg *msg)\r
+{\r
+#if LWIP_TCP\r
+ if (msg->conn->pcb.tcp != NULL) {\r
+ if (msg->conn->type == NETCONN_TCP) {\r
+ tcp_recved(msg->conn->pcb.tcp, msg->msg.len);\r
+ }\r
+ }\r
+#endif \r
+ sys_mbox_post(msg->conn->mbox, NULL);\r
+}\r
+\r
+static void\r
+do_write(struct api_msg_msg *msg)\r
+{\r
+#if LWIP_TCP \r
+ err_t err;\r
+#endif \r
+ if (msg->conn->pcb.tcp != NULL) {\r
+ switch (msg->conn->type) {\r
+#if LWIP_RAW\r
+ case NETCONN_RAW:\r
+ msg->conn->err = ERR_VAL;\r
+ break;\r
+#endif\r
+#if LWIP_UDP \r
+ case NETCONN_UDPLITE:\r
+ /* FALLTHROUGH */\r
+ case NETCONN_UDPNOCHKSUM:\r
+ /* FALLTHROUGH */\r
+ case NETCONN_UDP:\r
+ msg->conn->err = ERR_VAL;\r
+ break;\r
+#endif /* LWIP_UDP */\r
+#if LWIP_TCP \r
+ case NETCONN_TCP: \r
+ err = tcp_write(msg->conn->pcb.tcp, msg->msg.w.dataptr,\r
+ msg->msg.w.len, msg->msg.w.copy);\r
+ /* This is the Nagle algorithm: inhibit the sending of new TCP\r
+ segments when new outgoing data arrives from the user if any\r
+ previously transmitted data on the connection remains\r
+ unacknowledged. */\r
+ if(err == ERR_OK && (msg->conn->pcb.tcp->unacked == NULL || (msg->conn->pcb.tcp->flags & TF_NODELAY)) ) {\r
+ tcp_output(msg->conn->pcb.tcp);\r
+ }\r
+ msg->conn->err = err;\r
+ if (msg->conn->callback)\r
+ if (err == ERR_OK)\r
+ {\r
+ if (tcp_sndbuf(msg->conn->pcb.tcp) <= TCP_SNDLOWAT)\r
+ (*msg->conn->callback)(msg->conn, NETCONN_EVT_SENDMINUS, msg->msg.w.len);\r
+ }\r
+#endif\r
+ default:\r
+ break;\r
+ }\r
+ }\r
+ sys_mbox_post(msg->conn->mbox, NULL);\r
+}\r
+\r
+static void\r
+do_close(struct api_msg_msg *msg)\r
+{\r
+ err_t err;\r
+\r
+ err = ERR_OK;\r
+\r
+ if (msg->conn->pcb.tcp != NULL) {\r
+ switch (msg->conn->type) {\r
+#if LWIP_RAW\r
+ case NETCONN_RAW:\r
+ break;\r
+#endif\r
+#if LWIP_UDP\r
+ case NETCONN_UDPLITE:\r
+ /* FALLTHROUGH */\r
+ case NETCONN_UDPNOCHKSUM:\r
+ /* FALLTHROUGH */\r
+ case NETCONN_UDP:\r
+ break;\r
+#endif /* LWIP_UDP */\r
+#if LWIP_TCP\r
+ case NETCONN_TCP:\r
+ if (msg->conn->pcb.tcp->state == LISTEN) {\r
+ err = tcp_close(msg->conn->pcb.tcp);\r
+ }\r
+ msg->conn->err = err; \r
+#endif\r
+ default: \r
+ break;\r
+ }\r
+ }\r
+ sys_mbox_post(msg->conn->mbox, NULL);\r
+}\r
+\r
+typedef void (* api_msg_decode)(struct api_msg_msg *msg);\r
+static api_msg_decode decode[API_MSG_MAX] = {\r
+ do_newconn,\r
+ do_delconn,\r
+ do_bind,\r
+ do_connect,\r
+ do_disconnect,\r
+ do_listen,\r
+ do_accept,\r
+ do_send,\r
+ do_recv,\r
+ do_write,\r
+ do_close\r
+ };\r
+void\r
+api_msg_input(struct api_msg *msg)\r
+{ \r
+ decode[msg->type](&(msg->msg));\r
+}\r
+\r
+void\r
+api_msg_post(struct api_msg *msg)\r
+{\r
+ tcpip_apimsg(msg);\r
+}\r
+\r
+\r
+\r
--- /dev/null
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+#include "lwip/err.h"
+
+#ifdef LWIP_DEBUG
+
+static char *err_strerr[] = {"Ok.",
+ "Out of memory error.",
+ "Buffer error.",
+ "Connection aborted.",
+ "Connection reset.",
+ "Connection closed.",
+ "Not connected.",
+ "Illegal value.",
+ "Illegal argument.",
+ "Routing problem.",
+ "Address in use."
+};
+
+
+char *
+lwip_strerr(err_t err)
+{
+ return err_strerr[-err];
+
+}
+
+
+#endif /* LWIP_DEBUG */
--- /dev/null
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ * Improved by Marc Boucher <marc@mbsi.ca> and David Haas <dhaas@alum.rpi.edu>
+ *
+ */
+
+#include <string.h>
+#include <errno.h>
+
+#include "lwip/opt.h"
+#include "lwip/api.h"
+#include "lwip/arch.h"
+#include "lwip/sys.h"
+
+#include "lwip/sockets.h"
+
+#define NUM_SOCKETS MEMP_NUM_NETCONN
+
+struct lwip_socket {
+ struct netconn *conn;
+ struct netbuf *lastdata;
+ u16_t lastoffset;
+ u16_t rcvevent;
+ u16_t sendevent;
+ u16_t flags;
+ int err;
+};
+
+struct lwip_select_cb
+{
+ struct lwip_select_cb *next;
+ fd_set *readset;
+ fd_set *writeset;
+ fd_set *exceptset;
+ int sem_signalled;
+ sys_sem_t sem;
+};
+
+static struct lwip_socket sockets[NUM_SOCKETS];
+static struct lwip_select_cb *select_cb_list = 0;
+
+static sys_sem_t socksem = 0;
+static sys_sem_t selectsem = 0;
+
+static void
+event_callback(struct netconn *conn, enum netconn_evt evt, u16_t len);
+
+static int err_to_errno_table[11] = {
+ 0, /* ERR_OK 0 No error, everything OK. */
+ ENOMEM, /* ERR_MEM -1 Out of memory error. */
+ ENOBUFS, /* ERR_BUF -2 Buffer error. */
+ ECONNABORTED, /* ERR_ABRT -3 Connection aborted. */
+ ECONNRESET, /* ERR_RST -4 Connection reset. */
+ ESHUTDOWN, /* ERR_CLSD -5 Connection closed. */
+ ENOTCONN, /* ERR_CONN -6 Not connected. */
+ EINVAL, /* ERR_VAL -7 Illegal value. */
+ EIO, /* ERR_ARG -8 Illegal argument. */
+ EHOSTUNREACH, /* ERR_RTE -9 Routing problem. */
+ EADDRINUSE /* ERR_USE -10 Address in use. */
+};
+
+#define err_to_errno(err) \
+ ((err) < (sizeof(err_to_errno_table)/sizeof(int))) ? \
+ err_to_errno_table[-(err)] : EIO
+
+#ifdef ERRNO
+#define set_errno(err) errno = (err)
+#else
+#define set_errno(err)
+#endif
+
+#define sock_set_errno(sk, e) do { \
+ sk->err = (e); \
+ set_errno(sk->err); \
+} while (0)
+
+
+static struct lwip_socket *
+get_socket(int s)
+{
+ struct lwip_socket *sock;
+
+ if ((s < 0) || (s > NUM_SOCKETS)) {
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("get_socket(%d): invalid\n", s));
+ set_errno(EBADF);
+ return NULL;
+ }
+
+ sock = &sockets[s];
+
+ if (!sock->conn) {
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("get_socket(%d): not active\n", s));
+ set_errno(EBADF);
+ return NULL;
+ }
+
+ return sock;
+}
+
+static int
+alloc_socket(struct netconn *newconn)
+{
+ int i;
+
+ if (!socksem)
+ socksem = sys_sem_new(1);
+
+ /* Protect socket array */
+ sys_sem_wait(socksem);
+
+ /* allocate a new socket identifier */
+ for(i = 0; i < NUM_SOCKETS; ++i) {
+ if (!sockets[i].conn) {
+ sockets[i].conn = newconn;
+ sockets[i].lastdata = NULL;
+ sockets[i].lastoffset = 0;
+ sockets[i].rcvevent = 0;
+ sockets[i].sendevent = 1; /* TCP send buf is empty */
+ sockets[i].flags = 0;
+ sockets[i].err = 0;
+ sys_sem_signal(socksem);
+ return i;
+ }
+ }
+ sys_sem_signal(socksem);
+ return -1;
+}
+
+int
+lwip_accept(int s, struct sockaddr *addr, socklen_t *addrlen)
+{
+ struct lwip_socket *sock;
+ struct netconn *newconn;
+ struct ip_addr naddr;
+ u16_t port;
+ int newsock;
+ struct sockaddr_in sin;
+
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d)...\n", s));
+ sock = get_socket(s);
+ if (!sock) {
+ set_errno(EBADF);
+ return -1;
+ }
+
+ newconn = netconn_accept(sock->conn);
+
+ /* get the IP address and port of the remote host */
+ netconn_peer(newconn, &naddr, &port);
+
+ memset(&sin, 0, sizeof(sin));
+ sin.sin_len = sizeof(sin);
+ sin.sin_family = AF_INET;
+ sin.sin_port = htons(port);
+ sin.sin_addr.s_addr = naddr.addr;
+
+ if (*addrlen > sizeof(sin))
+ *addrlen = sizeof(sin);
+
+ memcpy(addr, &sin, *addrlen);
+
+ newsock = alloc_socket(newconn);
+ if (newsock == -1) {
+ netconn_delete(newconn);
+ sock_set_errno(sock, ENOBUFS);
+ return -1;
+ }
+ newconn->callback = event_callback;
+ sock = get_socket(newsock);
+
+ sys_sem_wait(socksem);
+ sock->rcvevent += -1 - newconn->socket;
+ newconn->socket = newsock;
+ sys_sem_signal(socksem);
+
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d) returning new sock=%d addr=", s, newsock));
+ ip_addr_debug_print(SOCKETS_DEBUG, &naddr);
+ LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u\n", port));
+
+ sock_set_errno(sock, 0);
+ return newsock;
+}
+
+int
+lwip_bind(int s, struct sockaddr *name, socklen_t namelen)
+{
+ struct lwip_socket *sock;
+ struct ip_addr local_addr;
+ u16_t local_port;
+ err_t err;
+
+ sock = get_socket(s);
+ if (!sock) {
+ set_errno(EBADF);
+ return -1;
+ }
+
+ local_addr.addr = ((struct sockaddr_in *)name)->sin_addr.s_addr;
+ local_port = ((struct sockaddr_in *)name)->sin_port;
+
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d, addr=", s));
+ ip_addr_debug_print(SOCKETS_DEBUG, &local_addr);
+ LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u)\n", ntohs(local_port)));
+
+ err = netconn_bind(sock->conn, &local_addr, ntohs(local_port));
+
+ if (err != ERR_OK) {
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d) failed, err=%d\n", s, err));
+ sock_set_errno(sock, err_to_errno(err));
+ return -1;
+ }
+
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d) succeeded\n", s));
+ sock_set_errno(sock, 0);
+ return 0;
+}
+
+int
+lwip_close(int s)
+{
+ struct lwip_socket *sock;
+
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_close(%d)\n", s));
+ if (!socksem)
+ socksem = sys_sem_new(1);
+
+ /* We cannot allow multiple closes of the same socket. */
+ sys_sem_wait(socksem);
+
+ sock = get_socket(s);
+ if (!sock) {
+ sys_sem_signal(socksem);
+ set_errno(EBADF);
+ return -1;
+ }
+
+ netconn_delete(sock->conn);
+ if (sock->lastdata) {
+ netbuf_delete(sock->lastdata);
+ }
+ sock->lastdata = NULL;
+ sock->lastoffset = 0;
+ sock->conn = NULL;
+ sys_sem_signal(socksem);
+ sock_set_errno(sock, 0);
+ return 0;
+}
+
+int
+lwip_connect(int s, struct sockaddr *name, socklen_t namelen)
+{
+ struct lwip_socket *sock;
+ err_t err;
+
+ sock = get_socket(s);
+ if (!sock) {
+ set_errno(EBADF);
+ return -1;
+ }
+
+ if (((struct sockaddr_in *)name)->sin_family == AF_UNSPEC) {
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d, AF_UNSPEC)\n", s));
+ err = netconn_disconnect(sock->conn);
+ } else {
+ struct ip_addr remote_addr;
+ u16_t remote_port;
+
+ remote_addr.addr = ((struct sockaddr_in *)name)->sin_addr.s_addr;
+ remote_port = ((struct sockaddr_in *)name)->sin_port;
+
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d, addr=", s));
+ ip_addr_debug_print(SOCKETS_DEBUG, &remote_addr);
+ LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u)\n", ntohs(remote_port)));
+
+ err = netconn_connect(sock->conn, &remote_addr, ntohs(remote_port));
+ }
+
+ if (err != ERR_OK) {
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d) failed, err=%d\n", s, err));
+ sock_set_errno(sock, err_to_errno(err));
+ return -1;
+ }
+
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d) succeeded\n", s));
+ sock_set_errno(sock, 0);
+ return 0;
+}
+
+int
+lwip_listen(int s, int backlog)
+{
+ struct lwip_socket *sock;
+ err_t err;
+
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_listen(%d, backlog=%d)\n", s, backlog));
+ sock = get_socket(s);
+ if (!sock) {
+ set_errno(EBADF);
+ return -1;
+ }
+
+ err = netconn_listen(sock->conn);
+
+ if (err != ERR_OK) {
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_listen(%d) failed, err=%d\n", s, err));
+ sock_set_errno(sock, err_to_errno(err));
+ return -1;
+ }
+
+ sock_set_errno(sock, 0);
+ return 0;
+}
+
+int
+lwip_recvfrom(int s, void *mem, int len, unsigned int flags,
+ struct sockaddr *from, socklen_t *fromlen)
+{
+ struct lwip_socket *sock;
+ struct netbuf *buf;
+ u16_t buflen, copylen;
+ struct ip_addr *addr;
+ u16_t port;
+
+
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d, %p, %d, 0x%x, ..)\n", s, mem, len, flags));
+ sock = get_socket(s);
+ if (!sock) {
+ set_errno(EBADF);
+ return -1;
+ }
+
+ /* Check if there is data left from the last recv operation. */
+ if (sock->lastdata) {
+ buf = sock->lastdata;
+ } else {
+ /* If this is non-blocking call, then check first */
+ if (((flags & MSG_DONTWAIT) || (sock->flags & O_NONBLOCK))
+ && !sock->rcvevent)
+ {
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): returning EWOULDBLOCK\n", s));
+ sock_set_errno(sock, EWOULDBLOCK);
+ return -1;
+ }
+
+ /* No data was left from the previous operation, so we try to get
+ some from the network. */
+ buf = netconn_recv(sock->conn);
+
+ if (!buf) {
+ /* We should really do some error checking here. */
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): buf == NULL!\n", s));
+ sock_set_errno(sock, 0);
+ return 0;
+ }
+ }
+
+ buflen = netbuf_len(buf);
+
+ buflen -= sock->lastoffset;
+
+ if (len > buflen) {
+ copylen = buflen;
+ } else {
+ copylen = len;
+ }
+
+ /* copy the contents of the received buffer into
+ the supplied memory pointer mem */
+ netbuf_copy_partial(buf, mem, copylen, sock->lastoffset);
+
+ /* Check to see from where the data was. */
+ if (from && fromlen) {
+ struct sockaddr_in sin;
+
+ addr = netbuf_fromaddr(buf);
+ port = netbuf_fromport(buf);
+
+ memset(&sin, 0, sizeof(sin));
+ sin.sin_len = sizeof(sin);
+ sin.sin_family = AF_INET;
+ sin.sin_port = htons(port);
+ sin.sin_addr.s_addr = addr->addr;
+
+ if (*fromlen > sizeof(sin))
+ *fromlen = sizeof(sin);
+
+ memcpy(from, &sin, *fromlen);
+
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): addr=", s));
+ ip_addr_debug_print(SOCKETS_DEBUG, addr);
+ LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u len=%u\n", port, copylen));
+ } else {
+#if SOCKETS_DEBUG
+ addr = netbuf_fromaddr(buf);
+ port = netbuf_fromport(buf);
+
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): addr=", s));
+ ip_addr_debug_print(SOCKETS_DEBUG, addr);
+ LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u len=%u\n", port, copylen));
+#endif
+
+ }
+
+ /* If this is a TCP socket, check if there is data left in the
+ buffer. If so, it should be saved in the sock structure for next
+ time around. */
+ if (netconn_type(sock->conn) == NETCONN_TCP && buflen - copylen > 0) {
+ sock->lastdata = buf;
+ sock->lastoffset += copylen;
+ } else {
+ sock->lastdata = NULL;
+ sock->lastoffset = 0;
+ netbuf_delete(buf);
+ }
+
+
+ sock_set_errno(sock, 0);
+ return copylen;
+}
+
+int
+lwip_read(int s, void *mem, int len)
+{
+ return lwip_recvfrom(s, mem, len, 0, NULL, NULL);
+}
+
+int
+lwip_recv(int s, void *mem, int len, unsigned int flags)
+{
+ return lwip_recvfrom(s, mem, len, flags, NULL, NULL);
+}
+
+int
+lwip_send(int s, void *data, int size, unsigned int flags)
+{
+ struct lwip_socket *sock;
+ struct netbuf *buf;
+ err_t err;
+
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d, data=%p, size=%d, flags=0x%x)\n", s, data, size, flags));
+
+ sock = get_socket(s);
+ if (!sock) {
+ set_errno(EBADF);
+ return -1;
+ }
+
+ switch (netconn_type(sock->conn)) {
+ case NETCONN_RAW:
+ case NETCONN_UDP:
+ case NETCONN_UDPLITE:
+ case NETCONN_UDPNOCHKSUM:
+ /* create a buffer */
+ buf = netbuf_new();
+
+ if (!buf) {
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d) ENOBUFS\n", s));
+ sock_set_errno(sock, ENOBUFS);
+ return -1;
+ }
+
+ /* make the buffer point to the data that should
+ be sent */
+ netbuf_ref(buf, data, size);
+
+ /* send the data */
+ err = netconn_send(sock->conn, buf);
+
+ /* deallocated the buffer */
+ netbuf_delete(buf);
+ break;
+ case NETCONN_TCP:
+ err = netconn_write(sock->conn, data, size, NETCONN_COPY);
+ break;
+ default:
+ err = ERR_ARG;
+ break;
+ }
+ if (err != ERR_OK) {
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d) err=%d\n", s, err));
+ sock_set_errno(sock, err_to_errno(err));
+ return -1;
+ }
+
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d) ok size=%d\n", s, size));
+ sock_set_errno(sock, 0);
+ return size;
+}
+
+int
+lwip_sendto(int s, void *data, int size, unsigned int flags,
+ struct sockaddr *to, socklen_t tolen)
+{
+ struct lwip_socket *sock;
+ struct ip_addr remote_addr, addr;
+ u16_t remote_port, port;
+ int ret,connected;
+
+ sock = get_socket(s);
+ if (!sock) {
+ set_errno(EBADF);
+ return -1;
+ }
+
+ /* get the peer if currently connected */
+ connected = (netconn_peer(sock->conn, &addr, &port) == ERR_OK);
+
+ remote_addr.addr = ((struct sockaddr_in *)to)->sin_addr.s_addr;
+ remote_port = ((struct sockaddr_in *)to)->sin_port;
+
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_sendto(%d, data=%p, size=%d, flags=0x%x to=", s, data, size, flags));
+ ip_addr_debug_print(SOCKETS_DEBUG, &remote_addr);
+ LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u\n", ntohs(remote_port)));
+
+ netconn_connect(sock->conn, &remote_addr, ntohs(remote_port));
+
+ ret = lwip_send(s, data, size, flags);
+
+ /* reset the remote address and port number
+ of the connection */
+ if (connected)
+ netconn_connect(sock->conn, &addr, port);
+ else
+ netconn_disconnect(sock->conn);
+ return ret;
+}
+
+int
+lwip_socket(int domain, int type, int protocol)
+{
+ struct netconn *conn;
+ int i;
+
+ /* create a netconn */
+ switch (type) {
+ case SOCK_RAW:
+ conn = netconn_new_with_proto_and_callback(NETCONN_RAW, protocol, event_callback);
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_RAW, %d) = ", domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol));
+ break;
+ case SOCK_DGRAM:
+ conn = netconn_new_with_callback(NETCONN_UDP, event_callback);
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_DGRAM, %d) = ", domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol));
+ break;
+ case SOCK_STREAM:
+ conn = netconn_new_with_callback(NETCONN_TCP, event_callback);
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_STREAM, %d) = ", domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol));
+ break;
+ default:
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%d, %d/UNKNOWN, %d) = -1\n", domain, type, protocol));
+ set_errno(EINVAL);
+ return -1;
+ }
+
+ if (!conn) {
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("-1 / ENOBUFS (could not create netconn)\n"));
+ set_errno(ENOBUFS);
+ return -1;
+ }
+
+ i = alloc_socket(conn);
+
+ if (i == -1) {
+ netconn_delete(conn);
+ set_errno(ENOBUFS);
+ return -1;
+ }
+ conn->socket = i;
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("%d\n", i));
+ set_errno(0);
+ return i;
+}
+
+int
+lwip_write(int s, void *data, int size)
+{
+ return lwip_send(s, data, size, 0);
+}
+
+
+static int
+lwip_selscan(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset)
+{
+ int i, nready = 0;
+ fd_set lreadset, lwriteset, lexceptset;
+ struct lwip_socket *p_sock;
+
+ FD_ZERO(&lreadset);
+ FD_ZERO(&lwriteset);
+ FD_ZERO(&lexceptset);
+
+ /* Go through each socket in each list to count number of sockets which
+ currently match */
+ for(i = 0; i < maxfdp1; i++)
+ {
+ if (FD_ISSET(i, readset))
+ {
+ /* See if netconn of this socket is ready for read */
+ p_sock = get_socket(i);
+ if (p_sock && (p_sock->lastdata || p_sock->rcvevent))
+ {
+ FD_SET(i, &lreadset);
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_selscan: fd=%d ready for reading\n", i));
+ nready++;
+ }
+ }
+ if (FD_ISSET(i, writeset))
+ {
+ /* See if netconn of this socket is ready for write */
+ p_sock = get_socket(i);
+ if (p_sock && p_sock->sendevent)
+ {
+ FD_SET(i, &lwriteset);
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_selscan: fd=%d ready for writing\n", i));
+ nready++;
+ }
+ }
+ }
+ *readset = lreadset;
+ *writeset = lwriteset;
+ FD_ZERO(exceptset);
+
+ return nready;
+}
+
+
+
+int
+lwip_select(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset,
+ struct timeval *timeout)
+{
+ int i;
+ int nready;
+ fd_set lreadset, lwriteset, lexceptset;
+ u32_t msectimeout;
+ struct lwip_select_cb select_cb;
+ struct lwip_select_cb *p_selcb;
+
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select(%d, %p, %p, %p, tvsec=%ld tvusec=%ld)\n", maxfdp1, (void *)readset, (void *) writeset, (void *) exceptset, timeout ? timeout->tv_sec : -1L, timeout ? timeout->tv_usec : -1L));
+
+ select_cb.next = 0;
+ select_cb.readset = readset;
+ select_cb.writeset = writeset;
+ select_cb.exceptset = exceptset;
+ select_cb.sem_signalled = 0;
+
+ /* Protect ourselves searching through the list */
+ if (!selectsem)
+ selectsem = sys_sem_new(1);
+ sys_sem_wait(selectsem);
+
+ if (readset)
+ lreadset = *readset;
+ else
+ FD_ZERO(&lreadset);
+ if (writeset)
+ lwriteset = *writeset;
+ else
+ FD_ZERO(&lwriteset);
+ if (exceptset)
+ lexceptset = *exceptset;
+ else
+ FD_ZERO(&lexceptset);
+
+ /* Go through each socket in each list to count number of sockets which
+ currently match */
+ nready = lwip_selscan(maxfdp1, &lreadset, &lwriteset, &lexceptset);
+
+ /* If we don't have any current events, then suspend if we are supposed to */
+ if (!nready)
+ {
+ if (timeout && timeout->tv_sec == 0 && timeout->tv_usec == 0)
+ {
+ sys_sem_signal(selectsem);
+ if (readset)
+ FD_ZERO(readset);
+ if (writeset)
+ FD_ZERO(writeset);
+ if (exceptset)
+ FD_ZERO(exceptset);
+
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: no timeout, returning 0\n"));
+ set_errno(0);
+
+ return 0;
+ }
+
+ /* add our semaphore to list */
+ /* We don't actually need any dynamic memory. Our entry on the
+ * list is only valid while we are in this function, so it's ok
+ * to use local variables */
+
+ select_cb.sem = sys_sem_new(0);
+ /* Note that we are still protected */
+ /* Put this select_cb on top of list */
+ select_cb.next = select_cb_list;
+ select_cb_list = &select_cb;
+
+ /* Now we can safely unprotect */
+ sys_sem_signal(selectsem);
+
+ /* Now just wait to be woken */
+ if (timeout == 0)
+ /* Wait forever */
+ msectimeout = 0;
+ else
+ msectimeout = ((timeout->tv_sec * 1000) + ((timeout->tv_usec + 500)/1000));
+
+ i = sys_sem_wait_timeout(select_cb.sem, msectimeout);
+
+ /* Take us off the list */
+ sys_sem_wait(selectsem);
+ if (select_cb_list == &select_cb)
+ select_cb_list = select_cb.next;
+ else
+ for (p_selcb = select_cb_list; p_selcb; p_selcb = p_selcb->next)
+ if (p_selcb->next == &select_cb)
+ {
+ p_selcb->next = select_cb.next;
+ break;
+ }
+
+ sys_sem_signal(selectsem);
+
+ sys_sem_free(select_cb.sem);
+ if (i == 0) /* Timeout */
+ {
+ if (readset)
+ FD_ZERO(readset);
+ if (writeset)
+ FD_ZERO(writeset);
+ if (exceptset)
+ FD_ZERO(exceptset);
+
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: timeout expired\n"));
+ set_errno(0);
+
+ return 0;
+ }
+
+ if (readset)
+ lreadset = *readset;
+ else
+ FD_ZERO(&lreadset);
+ if (writeset)
+ lwriteset = *writeset;
+ else
+ FD_ZERO(&lwriteset);
+ if (exceptset)
+ lexceptset = *exceptset;
+ else
+ FD_ZERO(&lexceptset);
+
+ /* See what's set */
+ nready = lwip_selscan(maxfdp1, &lreadset, &lwriteset, &lexceptset);
+ }
+ else
+ sys_sem_signal(selectsem);
+
+ if (readset)
+ *readset = lreadset;
+ if (writeset)
+ *writeset = lwriteset;
+ if (exceptset)
+ *exceptset = lexceptset;
+
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: nready=%d\n", nready));
+ set_errno(0);
+
+ return nready;
+}
+
+
+static void
+event_callback(struct netconn *conn, enum netconn_evt evt, u16_t len)
+{
+ int s;
+ struct lwip_socket *sock;
+ struct lwip_select_cb *scb;
+
+ /* Get socket */
+ if (conn)
+ {
+ s = conn->socket;
+ if (s < 0)
+ {
+ /* Data comes in right away after an accept, even though
+ * the server task might not have created a new socket yet.
+ * Just count down (or up) if that's the case and we
+ * will use the data later. Note that only receive events
+ * can happen before the new socket is set up. */
+ if (evt == NETCONN_EVT_RCVPLUS)
+ conn->socket--;
+ return;
+ }
+
+ sock = get_socket(s);
+ if (!sock)
+ return;
+ }
+ else
+ return;
+
+ if (!selectsem)
+ selectsem = sys_sem_new(1);
+
+ sys_sem_wait(selectsem);
+ /* Set event as required */
+ switch (evt)
+ {
+ case NETCONN_EVT_RCVPLUS:
+ sock->rcvevent++;
+ break;
+ case NETCONN_EVT_RCVMINUS:
+ sock->rcvevent--;
+ break;
+ case NETCONN_EVT_SENDPLUS:
+ sock->sendevent = 1;
+ break;
+ case NETCONN_EVT_SENDMINUS:
+ sock->sendevent = 0;
+ break;
+ }
+ sys_sem_signal(selectsem);
+
+ /* Now decide if anyone is waiting for this socket */
+ /* NOTE: This code is written this way to protect the select link list
+ but to avoid a deadlock situation by releasing socksem before
+ signalling for the select. This means we need to go through the list
+ multiple times ONLY IF a select was actually waiting. We go through
+ the list the number of waiting select calls + 1. This list is
+ expected to be small. */
+ while (1)
+ {
+ sys_sem_wait(selectsem);
+ for (scb = select_cb_list; scb; scb = scb->next)
+ {
+ if (scb->sem_signalled == 0)
+ {
+ /* Test this select call for our socket */
+ if (scb->readset && FD_ISSET(s, scb->readset))
+ if (sock->rcvevent)
+ break;
+ if (scb->writeset && FD_ISSET(s, scb->writeset))
+ if (sock->sendevent)
+ break;
+ }
+ }
+ if (scb)
+ {
+ scb->sem_signalled = 1;
+ sys_sem_signal(selectsem);
+ sys_sem_signal(scb->sem);
+ } else {
+ sys_sem_signal(selectsem);
+ break;
+ }
+ }
+
+}
+
+
+
+
+int lwip_shutdown(int s, int how)
+{
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_shutdown(%d, how=%d)\n", s, how));
+ return lwip_close(s); /* XXX temporary hack until proper implementation */
+}
+
+int lwip_getpeername (int s, struct sockaddr *name, socklen_t *namelen)
+{
+ struct lwip_socket *sock;
+ struct sockaddr_in sin;
+ struct ip_addr naddr;
+
+ sock = get_socket(s);
+ if (!sock) {
+ set_errno(EBADF);
+ return -1;
+ }
+
+ memset(&sin, 0, sizeof(sin));
+ sin.sin_len = sizeof(sin);
+ sin.sin_family = AF_INET;
+
+ /* get the IP address and port of the remote host */
+ netconn_peer(sock->conn, &naddr, &sin.sin_port);
+
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getpeername(%d, addr=", s));
+ ip_addr_debug_print(SOCKETS_DEBUG, &naddr);
+ LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%d)\n", sin.sin_port));
+
+ sin.sin_port = htons(sin.sin_port);
+ sin.sin_addr.s_addr = naddr.addr;
+
+ if (*namelen > sizeof(sin))
+ *namelen = sizeof(sin);
+
+ memcpy(name, &sin, *namelen);
+ sock_set_errno(sock, 0);
+ return 0;
+}
+
+int lwip_getsockname (int s, struct sockaddr *name, socklen_t *namelen)
+{
+ struct lwip_socket *sock;
+ struct sockaddr_in sin;
+ struct ip_addr *naddr;
+
+ sock = get_socket(s);
+ if (!sock) {
+ set_errno(EBADF);
+ return -1;
+ }
+
+ memset(&sin, 0, sizeof(sin));
+ sin.sin_len = sizeof(sin);
+ sin.sin_family = AF_INET;
+
+ /* get the IP address and port of the remote host */
+ netconn_addr(sock->conn, &naddr, &sin.sin_port);
+
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockname(%d, addr=", s));
+ ip_addr_debug_print(SOCKETS_DEBUG, naddr);
+ LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%d)\n", sin.sin_port));
+
+ sin.sin_port = htons(sin.sin_port);
+ sin.sin_addr.s_addr = naddr->addr;
+
+ if (*namelen > sizeof(sin))
+ *namelen = sizeof(sin);
+
+ memcpy(name, &sin, *namelen);
+ sock_set_errno(sock, 0);
+ return 0;
+}
+
+int lwip_getsockopt (int s, int level, int optname, void *optval, socklen_t *optlen)
+{
+ int err = 0;
+ struct lwip_socket *sock = get_socket(s);
+
+ if(!sock) {
+ set_errno(EBADF);
+ return -1;
+ }
+
+ if( NULL == optval || NULL == optlen ) {
+ sock_set_errno( sock, EFAULT );
+ return -1;
+ }
+
+ /* Do length and type checks for the various options first, to keep it readable. */
+ switch( level ) {
+
+/* Level: SOL_SOCKET */
+ case SOL_SOCKET:
+ switch(optname) {
+
+ case SO_ACCEPTCONN:
+ case SO_BROADCAST:
+ /* UNIMPL case SO_DEBUG: */
+ /* UNIMPL case SO_DONTROUTE: */
+ case SO_ERROR:
+ case SO_KEEPALIVE:
+ /* UNIMPL case SO_OOBINLINE: */
+ /* UNIMPL case SO_RCVBUF: */
+ /* UNIMPL case SO_SNDBUF: */
+ /* UNIMPL case SO_RCVLOWAT: */
+ /* UNIMPL case SO_SNDLOWAT: */
+#if SO_REUSE
+ case SO_REUSEADDR:
+ case SO_REUSEPORT:
+#endif /* SO_REUSE */
+ case SO_TYPE:
+ /* UNIMPL case SO_USELOOPBACK: */
+ if( *optlen < sizeof(int) ) {
+ err = EINVAL;
+ }
+ break;
+
+ default:
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, UNIMPL: optname=0x%x, ..)\n", s, optname));
+ err = ENOPROTOOPT;
+ } /* switch */
+ break;
+
+/* Level: IPPROTO_IP */
+ case IPPROTO_IP:
+ switch(optname) {
+ /* UNIMPL case IP_HDRINCL: */
+ /* UNIMPL case IP_RCVDSTADDR: */
+ /* UNIMPL case IP_RCVIF: */
+ case IP_TTL:
+ case IP_TOS:
+ if( *optlen < sizeof(int) ) {
+ err = EINVAL;
+ }
+ break;
+
+ default:
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, UNIMPL: optname=0x%x, ..)\n", s, optname));
+ err = ENOPROTOOPT;
+ } /* switch */
+ break;
+
+/* Level: IPPROTO_TCP */
+ case IPPROTO_TCP:
+ if( *optlen < sizeof(int) ) {
+ err = EINVAL;
+ break;
+ }
+
+ /* If this is no TCP socket, ignore any options. */
+ if ( sock->conn->type != NETCONN_TCP ) return 0;
+
+ switch( optname ) {
+ case TCP_NODELAY:
+ case TCP_KEEPALIVE:
+ break;
+
+ default:
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, UNIMPL: optname=0x%x, ..)\n", s, optname));
+ err = ENOPROTOOPT;
+ } /* switch */
+ break;
+
+/* UNDEFINED LEVEL */
+ default:
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, level=0x%x, UNIMPL: optname=0x%x, ..)\n", s, level, optname));
+ err = ENOPROTOOPT;
+ } /* switch */
+
+
+ if( 0 != err ) {
+ sock_set_errno(sock, err);
+ return -1;
+ }
+
+
+
+ /* Now do the actual option processing */
+
+ switch(level) {
+
+/* Level: SOL_SOCKET */
+ case SOL_SOCKET:
+ switch( optname ) {
+
+ /* The option flags */
+ case SO_ACCEPTCONN:
+ case SO_BROADCAST:
+ /* UNIMPL case SO_DEBUG: */
+ /* UNIMPL case SO_DONTROUTE: */
+ case SO_KEEPALIVE:
+ /* UNIMPL case SO_OOBINCLUDE: */
+#if SO_REUSE
+ case SO_REUSEADDR:
+ case SO_REUSEPORT:
+#endif /* SO_REUSE */
+ /*case SO_USELOOPBACK: UNIMPL */
+ *(int*)optval = sock->conn->pcb.tcp->so_options & optname;
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, optname=0x%x, ..) = %s\n", s, optname, (*(int*)optval?"on":"off")));
+ break;
+
+ case SO_TYPE:
+ switch (sock->conn->type) {
+ case NETCONN_RAW:
+ *(int*)optval = SOCK_RAW;
+ break;
+ case NETCONN_TCP:
+ *(int*)optval = SOCK_STREAM;
+ break;
+ case NETCONN_UDP:
+ case NETCONN_UDPLITE:
+ case NETCONN_UDPNOCHKSUM:
+ *(int*)optval = SOCK_DGRAM;
+ break;
+ default: /* unrecognized socket type */
+ *(int*)optval = sock->conn->type;
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, SO_TYPE): unrecognized socket type %d\n", s, *(int *)optval));
+ } /* switch */
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, SO_TYPE) = %d\n", s, *(int *)optval));
+ break;
+
+ case SO_ERROR:
+ *(int *)optval = sock->err;
+ sock->err = 0;
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, SO_ERROR) = %d\n", s, *(int *)optval));
+ break;
+ } /* switch */
+ break;
+
+/* Level: IPPROTO_IP */
+ case IPPROTO_IP:
+ switch( optname ) {
+ case IP_TTL:
+ *(int*)optval = sock->conn->pcb.tcp->ttl;
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_TTL) = %d\n", s, *(int *)optval));
+ break;
+ case IP_TOS:
+ *(int*)optval = sock->conn->pcb.tcp->tos;
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_TOS) = %d\n", s, *(int *)optval));
+ break;
+ } /* switch */
+ break;
+
+/* Level: IPPROTO_TCP */
+ case IPPROTO_TCP:
+ switch( optname ) {
+ case TCP_NODELAY:
+ *(int*)optval = (sock->conn->pcb.tcp->flags & TF_NODELAY);
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, TCP_NODELAY) = %s\n", s, (*(int*)optval)?"on":"off") );
+ break;
+ case TCP_KEEPALIVE:
+ *(int*)optval = (int)sock->conn->pcb.tcp->keepalive;
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, TCP_KEEPALIVE) = %d\n", s, *(int *)optval));
+ break;
+ } /* switch */
+ break;
+ }
+
+
+ sock_set_errno(sock, err);
+ return err ? -1 : 0;
+}
+
+int lwip_setsockopt (int s, int level, int optname, const void *optval, socklen_t optlen)
+{
+ struct lwip_socket *sock = get_socket(s);
+ int err = 0;
+
+ if(!sock) {
+ set_errno(EBADF);
+ return -1;
+ }
+
+ if( NULL == optval ) {
+ sock_set_errno( sock, EFAULT );
+ return -1;
+ }
+
+
+ /* Do length and type checks for the various options first, to keep it readable. */
+ switch( level ) {
+
+/* Level: SOL_SOCKET */
+ case SOL_SOCKET:
+ switch(optname) {
+
+ case SO_BROADCAST:
+ /* UNIMPL case SO_DEBUG: */
+ /* UNIMPL case SO_DONTROUTE: */
+ case SO_KEEPALIVE:
+ /* UNIMPL case SO_OOBINLINE: */
+ /* UNIMPL case SO_RCVBUF: */
+ /* UNIMPL case SO_SNDBUF: */
+ /* UNIMPL case SO_RCVLOWAT: */
+ /* UNIMPL case SO_SNDLOWAT: */
+#if SO_REUSE
+ case SO_REUSEADDR:
+ case SO_REUSEPORT:
+#endif /* SO_REUSE */
+ /* UNIMPL case SO_USELOOPBACK: */
+ if( optlen < sizeof(int) ) {
+ err = EINVAL;
+ }
+ break;
+ default:
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, SOL_SOCKET, UNIMPL: optname=0x%x, ..)\n", s, optname));
+ err = ENOPROTOOPT;
+ } /* switch */
+ break;
+
+/* Level: IPPROTO_IP */
+ case IPPROTO_IP:
+ switch(optname) {
+ /* UNIMPL case IP_HDRINCL: */
+ /* UNIMPL case IP_RCVDSTADDR: */
+ /* UNIMPL case IP_RCVIF: */
+ case IP_TTL:
+ case IP_TOS:
+ if( optlen < sizeof(int) ) {
+ err = EINVAL;
+ }
+ break;
+ default:
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, UNIMPL: optname=0x%x, ..)\n", s, optname));
+ err = ENOPROTOOPT;
+ } /* switch */
+ break;
+
+/* Level: IPPROTO_TCP */
+ case IPPROTO_TCP:
+ if( optlen < sizeof(int) ) {
+ err = EINVAL;
+ break;
+ }
+
+ /* If this is no TCP socket, ignore any options. */
+ if ( sock->conn->type != NETCONN_TCP ) return 0;
+
+ switch( optname ) {
+ case TCP_NODELAY:
+ case TCP_KEEPALIVE:
+ break;
+
+ default:
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, UNIMPL: optname=0x%x, ..)\n", s, optname));
+ err = ENOPROTOOPT;
+ } /* switch */
+ break;
+
+/* UNDEFINED LEVEL */
+ default:
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, level=0x%x, UNIMPL: optname=0x%x, ..)\n", s, level, optname));
+ err = ENOPROTOOPT;
+ } /* switch */
+
+
+ if( 0 != err ) {
+ sock_set_errno(sock, err);
+ return -1;
+ }
+
+
+
+ /* Now do the actual option processing */
+
+ switch(level) {
+
+/* Level: SOL_SOCKET */
+ case SOL_SOCKET:
+ switch(optname) {
+
+ /* The option flags */
+ case SO_BROADCAST:
+ /* UNIMPL case SO_DEBUG: */
+ /* UNIMPL case SO_DONTROUTE: */
+ case SO_KEEPALIVE:
+ /* UNIMPL case SO_OOBINCLUDE: */
+#if SO_REUSE
+ case SO_REUSEADDR:
+ case SO_REUSEPORT:
+#endif /* SO_REUSE */
+ /* UNIMPL case SO_USELOOPBACK: */
+ if ( *(int*)optval ) {
+ sock->conn->pcb.tcp->so_options |= optname;
+ } else {
+ sock->conn->pcb.tcp->so_options &= ~optname;
+ }
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, SOL_SOCKET, optname=0x%x, ..) -> %s\n", s, optname, (*(int*)optval?"on":"off")));
+ break;
+ } /* switch */
+ break;
+
+/* Level: IPPROTO_IP */
+ case IPPROTO_IP:
+ switch( optname ) {
+ case IP_TTL:
+ sock->conn->pcb.tcp->ttl = (u8_t)(*(int*)optval);
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, IP_TTL, ..) -> %u\n", s, sock->conn->pcb.tcp->ttl));
+ break;
+ case IP_TOS:
+ sock->conn->pcb.tcp->tos = (u8_t)(*(int*)optval);
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, IP_TOS, ..)-> %u\n", s, sock->conn->pcb.tcp->tos));
+ break;
+ } /* switch */
+ break;
+
+/* Level: IPPROTO_TCP */
+ case IPPROTO_TCP:
+ switch( optname ) {
+ case TCP_NODELAY:
+ if ( *(int*)optval ) {
+ sock->conn->pcb.tcp->flags |= TF_NODELAY;
+ } else {
+ sock->conn->pcb.tcp->flags &= ~TF_NODELAY;
+ }
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_NODELAY) -> %s\n", s, (*(int *)optval)?"on":"off") );
+ break;
+ case TCP_KEEPALIVE:
+ sock->conn->pcb.tcp->keepalive = (u32_t)(*(int*)optval);
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_KEEPALIVE) -> %lu\n", s, sock->conn->pcb.tcp->keepalive));
+ break;
+ } /* switch */
+ break;
+ } /* switch */
+
+ sock_set_errno(sock, err);
+ return err ? -1 : 0;
+}
+
+int lwip_ioctl(int s, long cmd, void *argp)
+{
+ struct lwip_socket *sock = get_socket(s);
+
+ if(!sock) {
+ set_errno(EBADF);
+ return -1;
+ }
+
+ switch (cmd) {
+ case FIONREAD:
+ if (!argp) {
+ sock_set_errno(sock, EINVAL);
+ return -1;
+ }
+
+ *((u16_t*)argp) = sock->conn->recv_avail;
+
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, FIONREAD, %p) = %u\n", s, argp, *((u16_t*)argp)));
+ sock_set_errno(sock, 0);
+ return 0;
+
+ case FIONBIO:
+ if (argp && *(u32_t*)argp)
+ sock->flags |= O_NONBLOCK;
+ else
+ sock->flags &= ~O_NONBLOCK;
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, FIONBIO, %d)\n", s, !!(sock->flags & O_NONBLOCK)));
+ sock_set_errno(sock, 0);
+ return 0;
+
+ default:
+ LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, UNIMPL: 0x%lx, %p)\n", s, cmd, argp));
+ sock_set_errno(sock, ENOSYS); /* not yet implemented */
+ return -1;
+ }
+}
+
--- /dev/null
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+#include "lwip/opt.h"
+
+#include "lwip/sys.h"
+
+#include "lwip/memp.h"
+#include "lwip/pbuf.h"
+
+#include "lwip/ip.h"
+#include "lwip/udp.h"
+#include "lwip/tcp.h"
+
+#include "lwip/tcpip.h"
+
+static void (* tcpip_init_done)(void *arg) = NULL;
+static void *tcpip_init_done_arg;
+static sys_mbox_t mbox;
+
+#if LWIP_TCP
+static int tcpip_tcp_timer_active = 0;
+
+static void
+tcpip_tcp_timer(void *arg)
+{
+ (void)arg;
+
+ /* call TCP timer handler */
+ tcp_tmr();
+ /* timer still needed? */
+ if (tcp_active_pcbs || tcp_tw_pcbs) {
+ /* restart timer */
+ sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL);
+ } else {
+ /* disable timer */
+ tcpip_tcp_timer_active = 0;
+ }
+}
+
+#if !NO_SYS
+void
+tcp_timer_needed(void)
+{
+ /* timer is off but needed again? */
+ if (!tcpip_tcp_timer_active && (tcp_active_pcbs || tcp_tw_pcbs)) {
+ /* enable and start timer */
+ tcpip_tcp_timer_active = 1;
+ sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL);
+ }
+}
+#endif /* !NO_SYS */
+#endif /* LWIP_TCP */
+
+static void
+tcpip_thread(void *arg)
+{
+ struct tcpip_msg *msg;
+
+ (void)arg;
+
+ ip_init();
+#if LWIP_UDP
+ udp_init();
+#endif
+#if LWIP_TCP
+ tcp_init();
+#endif
+ if (tcpip_init_done != NULL) {
+ tcpip_init_done(tcpip_init_done_arg);
+ }
+
+ while (1) { /* MAIN Loop */
+ sys_mbox_fetch(mbox, (void *)&msg);
+ switch (msg->type) {
+ case TCPIP_MSG_API:
+ LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: API message %p\n", (void *)msg));
+ api_msg_input(msg->msg.apimsg);
+ break;
+ case TCPIP_MSG_INPUT:
+ LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: IP packet %p\n", (void *)msg));
+ ip_input(msg->msg.inp.p, msg->msg.inp.netif);
+ break;
+ case TCPIP_MSG_CALLBACK:
+ LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: CALLBACK %p\n", (void *)msg));
+ msg->msg.cb.f(msg->msg.cb.ctx);
+ break;
+ default:
+ break;
+ }
+ memp_free(MEMP_TCPIP_MSG, msg);
+ }
+}
+
+err_t
+tcpip_input(struct pbuf *p, struct netif *inp)
+{
+ struct tcpip_msg *msg;
+
+ msg = memp_malloc(MEMP_TCPIP_MSG);
+ if (msg == NULL) {
+ pbuf_free(p);
+ return ERR_MEM;
+ }
+
+ msg->type = TCPIP_MSG_INPUT;
+ msg->msg.inp.p = p;
+ msg->msg.inp.netif = inp;
+ sys_mbox_post(mbox, msg);
+ return ERR_OK;
+}
+
+err_t
+tcpip_callback(void (*f)(void *ctx), void *ctx)
+{
+ struct tcpip_msg *msg;
+
+ msg = memp_malloc(MEMP_TCPIP_MSG);
+ if (msg == NULL) {
+ return ERR_MEM;
+ }
+
+ msg->type = TCPIP_MSG_CALLBACK;
+ msg->msg.cb.f = f;
+ msg->msg.cb.ctx = ctx;
+ sys_mbox_post(mbox, msg);
+ return ERR_OK;
+}
+
+void
+tcpip_apimsg(struct api_msg *apimsg)
+{
+ struct tcpip_msg *msg;
+ msg = memp_malloc(MEMP_TCPIP_MSG);
+ if (msg == NULL) {
+ memp_free(MEMP_API_MSG, apimsg);
+ return;
+ }
+ msg->type = TCPIP_MSG_API;
+ msg->msg.apimsg = apimsg;
+ sys_mbox_post(mbox, msg);
+}
+
+void
+tcpip_init(void (* initfunc)(void *), void *arg)
+{
+ tcpip_init_done = initfunc;
+ tcpip_init_done_arg = arg;
+ mbox = sys_mbox_new();
+ sys_thread_new(tcpip_thread, NULL, TCPIP_THREAD_PRIO);
+}
+
+
+
+
--- /dev/null
+/**
+ * @file
+ *
+ * Dynamic Host Configuration Protocol client
+ */
+
+/*
+ *
+ * Copyright (c) 2001-2004 Leon Woestenberg <leon.woestenberg@gmx.net>
+ * Copyright (c) 2001-2004 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is a contribution to the lwIP TCP/IP stack.
+ * The Swedish Institute of Computer Science and Adam Dunkels
+ * are specifically granted permission to redistribute this
+ * source code.
+ *
+ * Author: Leon Woestenberg <leon.woestenberg@gmx.net>
+ *
+ * This is a DHCP client for the lwIP TCP/IP stack. It aims to conform
+ * with RFC 2131 and RFC 2132.
+ *
+ * TODO:
+ * - Proper parsing of DHCP messages exploiting file/sname field overloading.
+ * - Add JavaDoc style documentation (API, internals).
+ * - Support for interfaces other than Ethernet (SLIP, PPP, ...)
+ *
+ * Please coordinate changes and requests with Leon Woestenberg
+ * <leon.woestenberg@gmx.net>
+ *
+ * Integration with your code:
+ *
+ * In lwip/dhcp.h
+ * #define DHCP_COARSE_TIMER_SECS (recommended 60 which is a minute)
+ * #define DHCP_FINE_TIMER_MSECS (recommended 500 which equals TCP coarse timer)
+ *
+ * Then have your application call dhcp_coarse_tmr() and
+ * dhcp_fine_tmr() on the defined intervals.
+ *
+ * dhcp_start(struct netif *netif);
+ * starts a DHCP client instance which configures the interface by
+ * obtaining an IP address lease and maintaining it.
+ *
+ * Use dhcp_release(netif) to end the lease and use dhcp_stop(netif)
+ * to remove the DHCP client.
+ *
+ */
+
+#include <string.h>
+
+#include "lwip/stats.h"
+#include "lwip/mem.h"
+#include "lwip/udp.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/inet.h"
+#include "netif/etharp.h"
+
+#include "lwip/sys.h"
+#include "lwip/opt.h"
+#include "lwip/dhcp.h"
+
+#if LWIP_DHCP /* don't build if not configured for use in lwipopt.h */
+
+/** global transaction identifier, must be
+ * unique for each DHCP request. We simply increment, starting
+ * with this value (easy to match with a packet analyzer) */
+static u32_t xid = 0xABCD0000;
+
+/** DHCP client state machine functions */
+static void dhcp_handle_ack(struct netif *netif);
+static void dhcp_handle_nak(struct netif *netif);
+static void dhcp_handle_offer(struct netif *netif);
+
+static err_t dhcp_discover(struct netif *netif);
+static err_t dhcp_select(struct netif *netif);
+static void dhcp_check(struct netif *netif);
+static void dhcp_bind(struct netif *netif);
+static err_t dhcp_decline(struct netif *netif);
+static err_t dhcp_rebind(struct netif *netif);
+static void dhcp_set_state(struct dhcp *dhcp, unsigned char new_state);
+
+/** receive, unfold, parse and free incoming messages */
+static void dhcp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *addr, u16_t port);
+static err_t dhcp_unfold_reply(struct dhcp *dhcp);
+static u8_t *dhcp_get_option_ptr(struct dhcp *dhcp, u8_t option_type);
+static u8_t dhcp_get_option_byte(u8_t *ptr);
+static u16_t dhcp_get_option_short(u8_t *ptr);
+static u32_t dhcp_get_option_long(u8_t *ptr);
+static void dhcp_free_reply(struct dhcp *dhcp);
+
+/** set the DHCP timers */
+static void dhcp_timeout(struct netif *netif);
+static void dhcp_t1_timeout(struct netif *netif);
+static void dhcp_t2_timeout(struct netif *netif);
+
+/** build outgoing messages */
+/** create a DHCP request, fill in common headers */
+static err_t dhcp_create_request(struct netif *netif);
+/** free a DHCP request */
+static void dhcp_delete_request(struct netif *netif);
+/** add a DHCP option (type, then length in bytes) */
+static void dhcp_option(struct dhcp *dhcp, u8_t option_type, u8_t option_len);
+/** add option values */
+static void dhcp_option_byte(struct dhcp *dhcp, u8_t value);
+static void dhcp_option_short(struct dhcp *dhcp, u16_t value);
+static void dhcp_option_long(struct dhcp *dhcp, u32_t value);
+/** always add the DHCP options trailer to end and pad */
+static void dhcp_option_trailer(struct dhcp *dhcp);
+
+/**
+ * Back-off the DHCP client (because of a received NAK response).
+ *
+ * Back-off the DHCP client because of a received NAK. Receiving a
+ * NAK means the client asked for something non-sensible, for
+ * example when it tries to renew a lease obtained on another network.
+ *
+ * We back-off and will end up restarting a fresh DHCP negotiation later.
+ *
+ * @param state pointer to DHCP state structure
+ */
+static void dhcp_handle_nak(struct netif *netif) {
+ struct dhcp *dhcp = netif->dhcp;
+ u16_t msecs = 10 * 1000;
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_handle_nak(netif=%p) %c%c%u\n", netif,
+ netif->name[0], netif->name[1], (unsigned int)netif->num));
+ dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_handle_nak(): set request timeout %u msecs\n", msecs));
+ dhcp_set_state(dhcp, DHCP_BACKING_OFF);
+}
+
+/**
+ * Checks if the offered IP address is already in use.
+ *
+ * It does so by sending an ARP request for the offered address and
+ * entering CHECKING state. If no ARP reply is received within a small
+ * interval, the address is assumed to be free for use by us.
+ */
+static void dhcp_check(struct netif *netif)
+{
+ struct dhcp *dhcp = netif->dhcp;
+ err_t result;
+ u16_t msecs;
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_check(netif=%p) %c%c\n", (void *)netif, (unsigned int)netif->name[0],
+ (unsigned int)netif->name[1]));
+ /* create an ARP query for the offered IP address, expecting that no host
+ responds, as the IP address should not be in use. */
+ result = etharp_query(netif, &dhcp->offered_ip_addr, NULL);
+ if (result != ERR_OK) {
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_check: could not perform ARP query\n"));
+ }
+ dhcp->tries++;
+ msecs = 500;
+ dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_check(): set request timeout %u msecs\n", msecs));
+ dhcp_set_state(dhcp, DHCP_CHECKING);
+}
+
+/**
+ * Remember the configuration offered by a DHCP server.
+ *
+ * @param state pointer to DHCP state structure
+ */
+static void dhcp_handle_offer(struct netif *netif)
+{
+ struct dhcp *dhcp = netif->dhcp;
+ /* obtain the server address */
+ u8_t *option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_SERVER_ID);
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_handle_offer(netif=%p) %c%c%u\n", netif,
+ netif->name[0], netif->name[1], netif->num));
+ if (option_ptr != NULL)
+ {
+ dhcp->server_ip_addr.addr = htonl(dhcp_get_option_long(&option_ptr[2]));
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_handle_offer(): server 0x%08lx\n", dhcp->server_ip_addr.addr));
+ /* remember offered address */
+ ip_addr_set(&dhcp->offered_ip_addr, (struct ip_addr *)&dhcp->msg_in->yiaddr);
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_handle_offer(): offer for 0x%08lx\n", dhcp->offered_ip_addr.addr));
+
+ dhcp_select(netif);
+ }
+}
+
+/**
+ * Select a DHCP server offer out of all offers.
+ *
+ * Simply select the first offer received.
+ *
+ * @param netif the netif under DHCP control
+ * @return lwIP specific error (see error.h)
+ */
+static err_t dhcp_select(struct netif *netif)
+{
+ struct dhcp *dhcp = netif->dhcp;
+ err_t result;
+ u32_t msecs;
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_select(netif=%p) %c%c%u\n", netif, netif->name[0], netif->name[1], netif->num));
+
+ /* create and initialize the DHCP message header */
+ result = dhcp_create_request(netif);
+ if (result == ERR_OK)
+ {
+ dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
+ dhcp_option_byte(dhcp, DHCP_REQUEST);
+
+ dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
+ dhcp_option_short(dhcp, 576);
+
+ /* MUST request the offered IP address */
+ dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4);
+ dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr));
+
+ dhcp_option(dhcp, DHCP_OPTION_SERVER_ID, 4);
+ dhcp_option_long(dhcp, ntohl(dhcp->server_ip_addr.addr));
+
+ dhcp_option(dhcp, DHCP_OPTION_PARAMETER_REQUEST_LIST, 4/*num options*/);
+ dhcp_option_byte(dhcp, DHCP_OPTION_SUBNET_MASK);
+ dhcp_option_byte(dhcp, DHCP_OPTION_ROUTER);
+ dhcp_option_byte(dhcp, DHCP_OPTION_BROADCAST);
+ dhcp_option_byte(dhcp, DHCP_OPTION_DNS_SERVER);
+
+ dhcp_option_trailer(dhcp);
+ /* shrink the pbuf to the actual content length */
+ pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+ /* TODO: we really should bind to a specific local interface here
+ but we cannot specify an unconfigured netif as it is addressless */
+ udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
+ /* send broadcast to any DHCP server */
+ udp_connect(dhcp->pcb, IP_ADDR_BROADCAST, DHCP_SERVER_PORT);
+ udp_send(dhcp->pcb, dhcp->p_out);
+ /* reconnect to any (or to server here?!) */
+ udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT);
+ dhcp_delete_request(netif);
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_select: REQUESTING\n"));
+ dhcp_set_state(dhcp, DHCP_REQUESTING);
+ } else {
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_select: could not allocate DHCP request\n"));
+ }
+ dhcp->tries++;
+ msecs = dhcp->tries < 4 ? dhcp->tries * 1000 : 4 * 1000;
+ dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_select(): set request timeout %u msecs\n", msecs));
+ return result;
+}
+
+/**
+ * The DHCP timer that checks for lease renewal/rebind timeouts.
+ *
+ */
+void dhcp_coarse_tmr()
+{
+ struct netif *netif = netif_list;
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_coarse_tmr()\n"));
+ /* iterate through all network interfaces */
+ while (netif != NULL) {
+ /* only act on DHCP configured interfaces */
+ if (netif->dhcp != NULL) {
+ /* timer is active (non zero), and triggers (zeroes) now? */
+ if (netif->dhcp->t2_timeout-- == 1) {
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_coarse_tmr(): t2 timeout\n"));
+ /* this clients' rebind timeout triggered */
+ dhcp_t2_timeout(netif);
+ /* timer is active (non zero), and triggers (zeroes) now */
+ } else if (netif->dhcp->t1_timeout-- == 1) {
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_coarse_tmr(): t1 timeout\n"));
+ /* this clients' renewal timeout triggered */
+ dhcp_t1_timeout(netif);
+ }
+ }
+ /* proceed to next netif */
+ netif = netif->next;
+ }
+}
+
+/**
+ * DHCP transaction timeout handling
+ *
+ * A DHCP server is expected to respond within a short period of time.
+ * This timer checks whether an outstanding DHCP request is timed out.
+ *
+ */
+void dhcp_fine_tmr()
+{
+ struct netif *netif = netif_list;
+ /* loop through netif's */
+ while (netif != NULL) {
+ /* only act on DHCP configured interfaces */
+ if (netif->dhcp != NULL) {
+ /* timer is active (non zero), and is about to trigger now */
+ if (netif->dhcp->request_timeout-- == 1) {
+ /* { netif->dhcp->request_timeout == 0 } */
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_fine_tmr(): request timeout\n"));
+ /* this clients' request timeout triggered */
+ dhcp_timeout(netif);
+ }
+ }
+ /* proceed to next network interface */
+ netif = netif->next;
+ }
+}
+
+/**
+ * A DHCP negotiation transaction, or ARP request, has timed out.
+ *
+ * The timer that was started with the DHCP or ARP request has
+ * timed out, indicating no response was received in time.
+ *
+ * @param netif the netif under DHCP control
+ *
+ */
+static void dhcp_timeout(struct netif *netif)
+{
+ struct dhcp *dhcp = netif->dhcp;
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_timeout()\n"));
+ /* back-off period has passed, or server selection timed out */
+ if ((dhcp->state == DHCP_BACKING_OFF) || (dhcp->state == DHCP_SELECTING)) {
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_timeout(): restarting discovery\n"));
+ dhcp_discover(netif);
+ /* receiving the requested lease timed out */
+ } else if (dhcp->state == DHCP_REQUESTING) {
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): REQUESTING, DHCP request timed out\n"));
+ if (dhcp->tries <= 5) {
+ dhcp_select(netif);
+ } else {
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): REQUESTING, releasing, restarting\n"));
+ dhcp_release(netif);
+ dhcp_discover(netif);
+ }
+ /* received no ARP reply for the offered address (which is good) */
+ } else if (dhcp->state == DHCP_CHECKING) {
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): CHECKING, ARP request timed out\n"));
+ if (dhcp->tries <= 1) {
+ dhcp_check(netif);
+ /* no ARP replies on the offered address,
+ looks like the IP address is indeed free */
+ } else {
+ /* bind the interface to the offered address */
+ dhcp_bind(netif);
+ }
+ }
+ /* did not get response to renew request? */
+ else if (dhcp->state == DHCP_RENEWING) {
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): RENEWING, DHCP request timed out\n"));
+ /* just retry renewal */
+ /* note that the rebind timer will eventually time-out if renew does not work */
+ dhcp_renew(netif);
+ /* did not get response to rebind request? */
+ } else if (dhcp->state == DHCP_REBINDING) {
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): REBINDING, DHCP request timed out\n"));
+ if (dhcp->tries <= 8) {
+ dhcp_rebind(netif);
+ } else {
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): RELEASING, DISCOVERING\n"));
+ dhcp_release(netif);
+ dhcp_discover(netif);
+ }
+ }
+}
+
+/**
+ * The renewal period has timed out.
+ *
+ * @param netif the netif under DHCP control
+ */
+static void dhcp_t1_timeout(struct netif *netif)
+{
+ struct dhcp *dhcp = netif->dhcp;
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_t1_timeout()\n"));
+ if ((dhcp->state == DHCP_REQUESTING) || (dhcp->state == DHCP_BOUND) || (dhcp->state == DHCP_RENEWING)) {
+ /* just retry to renew - note that the rebind timer (t2) will
+ * eventually time-out if renew tries fail. */
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_t1_timeout(): must renew\n"));
+ dhcp_renew(netif);
+ }
+}
+
+/**
+ * The rebind period has timed out.
+ *
+ */
+static void dhcp_t2_timeout(struct netif *netif)
+{
+ struct dhcp *dhcp = netif->dhcp;
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_t2_timeout()\n"));
+ if ((dhcp->state == DHCP_REQUESTING) || (dhcp->state == DHCP_BOUND) || (dhcp->state == DHCP_RENEWING)) {
+ /* just retry to rebind */
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_t2_timeout(): must rebind\n"));
+ dhcp_rebind(netif);
+ }
+}
+
+/**
+ *
+ * @param netif the netif under DHCP control
+ */
+static void dhcp_handle_ack(struct netif *netif)
+{
+ struct dhcp *dhcp = netif->dhcp;
+ u8_t *option_ptr;
+ /* clear options we might not get from the ACK */
+ dhcp->offered_sn_mask.addr = 0;
+ dhcp->offered_gw_addr.addr = 0;
+ dhcp->offered_bc_addr.addr = 0;
+
+ /* lease time given? */
+ option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_LEASE_TIME);
+ if (option_ptr != NULL) {
+ /* remember offered lease time */
+ dhcp->offered_t0_lease = dhcp_get_option_long(option_ptr + 2);
+ }
+ /* renewal period given? */
+ option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_T1);
+ if (option_ptr != NULL) {
+ /* remember given renewal period */
+ dhcp->offered_t1_renew = dhcp_get_option_long(option_ptr + 2);
+ } else {
+ /* calculate safe periods for renewal */
+ dhcp->offered_t1_renew = dhcp->offered_t0_lease / 2;
+ }
+
+ /* renewal period given? */
+ option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_T2);
+ if (option_ptr != NULL) {
+ /* remember given rebind period */
+ dhcp->offered_t2_rebind = dhcp_get_option_long(option_ptr + 2);
+ } else {
+ /* calculate safe periods for rebinding */
+ dhcp->offered_t2_rebind = dhcp->offered_t0_lease;
+ }
+
+ /* (y)our internet address */
+ ip_addr_set(&dhcp->offered_ip_addr, &dhcp->msg_in->yiaddr);
+
+/**
+ * Patch #1308
+ * TODO: we must check if the file field is not overloaded by DHCP options!
+ */
+#if 0
+ /* boot server address */
+ ip_addr_set(&dhcp->offered_si_addr, &dhcp->msg_in->siaddr);
+ /* boot file name */
+ if (dhcp->msg_in->file[0]) {
+ dhcp->boot_file_name = mem_malloc(strlen(dhcp->msg_in->file) + 1);
+ strcpy(dhcp->boot_file_name, dhcp->msg_in->file);
+ }
+#endif
+
+ /* subnet mask */
+ option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_SUBNET_MASK);
+ /* subnet mask given? */
+ if (option_ptr != NULL) {
+ dhcp->offered_sn_mask.addr = htonl(dhcp_get_option_long(&option_ptr[2]));
+ }
+
+ /* gateway router */
+ option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_ROUTER);
+ if (option_ptr != NULL) {
+ dhcp->offered_gw_addr.addr = htonl(dhcp_get_option_long(&option_ptr[2]));
+ }
+
+ /* broadcast address */
+ option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_BROADCAST);
+ if (option_ptr != NULL) {
+ dhcp->offered_bc_addr.addr = htonl(dhcp_get_option_long(&option_ptr[2]));
+ }
+
+ /* DNS servers */
+ option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_DNS_SERVER);
+ if (option_ptr != NULL) {
+ u8_t n;
+ dhcp->dns_count = dhcp_get_option_byte(&option_ptr[1]);
+ /* limit to at most DHCP_MAX_DNS DNS servers */
+ if (dhcp->dns_count > DHCP_MAX_DNS) dhcp->dns_count = DHCP_MAX_DNS;
+ for (n = 0; n < dhcp->dns_count; n++)
+ {
+ dhcp->offered_dns_addr[n].addr = htonl(dhcp_get_option_long(&option_ptr[2+(n<<2)]));
+ }
+ }
+}
+
+/**
+ * Start DHCP negotiation for a network interface.
+ *
+ * If no DHCP client instance was attached to this interface,
+ * a new client is created first. If a DHCP client instance
+ * was already present, it restarts negotiation.
+ *
+ * @param netif The lwIP network interface
+ * @return lwIP error code
+ * - ERR_OK - No error
+ * - ERR_MEM - Out of memory
+ *
+ */
+err_t dhcp_start(struct netif *netif)
+{
+ struct dhcp *dhcp = netif->dhcp;
+ err_t result = ERR_OK;
+
+ LWIP_ASSERT("netif != NULL", netif != NULL);
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_start(netif=%p) %c%c%u\n", netif, netif->name[0], netif->name[1], netif->num));
+ netif->flags &= ~NETIF_FLAG_DHCP;
+
+ /* no DHCP client attached yet? */
+ if (dhcp == NULL) {
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): starting new DHCP client\n"));
+ dhcp = mem_malloc(sizeof(struct dhcp));
+ if (dhcp == NULL) {
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): could not allocate dhcp\n"));
+ return ERR_MEM;
+ }
+ /* store this dhcp client in the netif */
+ netif->dhcp = dhcp;
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): allocated dhcp"));
+ /* already has DHCP client attached */
+ } else {
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE | 3, ("dhcp_start(): restarting DHCP configuration\n"));
+ }
+
+ /* clear data structure */
+ memset(dhcp, 0, sizeof(struct dhcp));
+ /* allocate UDP PCB */
+ dhcp->pcb = udp_new();
+ if (dhcp->pcb == NULL) {
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): could not obtain pcb\n"));
+ mem_free((void *)dhcp);
+ netif->dhcp = dhcp = NULL;
+ return ERR_MEM;
+ }
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): starting DHCP configuration\n"));
+ /* (re)start the DHCP negotiation */
+ result = dhcp_discover(netif);
+ if (result != ERR_OK) {
+ /* free resources allocated above */
+ dhcp_stop(netif);
+ return ERR_MEM;
+ }
+ netif->flags |= NETIF_FLAG_DHCP;
+ return result;
+}
+
+/**
+ * Inform a DHCP server of our manual configuration.
+ *
+ * This informs DHCP servers of our fixed IP address configuration
+ * by sending an INFORM message. It does not involve DHCP address
+ * configuration, it is just here to be nice to the network.
+ *
+ * @param netif The lwIP network interface
+ *
+ */
+void dhcp_inform(struct netif *netif)
+{
+ struct dhcp *dhcp;
+ err_t result = ERR_OK;
+ dhcp = mem_malloc(sizeof(struct dhcp));
+ if (dhcp == NULL) {
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_inform(): could not allocate dhcp\n"));
+ return;
+ }
+ netif->dhcp = dhcp;
+ memset(dhcp, 0, sizeof(struct dhcp));
+
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_inform(): allocated dhcp\n"));
+ dhcp->pcb = udp_new();
+ if (dhcp->pcb == NULL) {
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_inform(): could not obtain pcb"));
+ mem_free((void *)dhcp);
+ return;
+ }
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_inform(): created new udp pcb\n"));
+ /* create and initialize the DHCP message header */
+ result = dhcp_create_request(netif);
+ if (result == ERR_OK) {
+
+ dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
+ dhcp_option_byte(dhcp, DHCP_INFORM);
+
+ dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
+ /* TODO: use netif->mtu ?! */
+ dhcp_option_short(dhcp, 576);
+
+ dhcp_option_trailer(dhcp);
+
+ pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+ udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
+ udp_connect(dhcp->pcb, IP_ADDR_BROADCAST, DHCP_SERVER_PORT);
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_inform: INFORMING\n"));
+ udp_send(dhcp->pcb, dhcp->p_out);
+ udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT);
+ dhcp_delete_request(netif);
+ } else {
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_inform: could not allocate DHCP request\n"));
+ }
+
+ if (dhcp != NULL)
+ {
+ if (dhcp->pcb != NULL) udp_remove(dhcp->pcb);
+ dhcp->pcb = NULL;
+ mem_free((void *)dhcp);
+ netif->dhcp = NULL;
+ }
+}
+
+#if DHCP_DOES_ARP_CHECK
+/**
+ * Match an ARP reply with the offered IP address.
+ *
+ * @param addr The IP address we received a reply from
+ *
+ */
+void dhcp_arp_reply(struct netif *netif, struct ip_addr *addr)
+{
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_arp_reply()\n"));
+ /* is this DHCP client doing an ARP check? */
+ if ((netif->dhcp != NULL) && (netif->dhcp->state == DHCP_CHECKING)) {
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_arp_reply(): CHECKING, arp reply for 0x%08lx\n", addr->addr));
+ /* did a host respond with the address we
+ were offered by the DHCP server? */
+ if (ip_addr_cmp(addr, &netif->dhcp->offered_ip_addr)) {
+ /* we will not accept the offered address */
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE | 1, ("dhcp_arp_reply(): arp reply matched with offered address, declining\n"));
+ dhcp_decline(netif);
+ }
+ }
+}
+
+/**
+ * Decline an offered lease.
+ *
+ * Tell the DHCP server we do not accept the offered address.
+ * One reason to decline the lease is when we find out the address
+ * is already in use by another host (through ARP).
+ */
+static err_t dhcp_decline(struct netif *netif)
+{
+ struct dhcp *dhcp = netif->dhcp;
+ err_t result = ERR_OK;
+ u16_t msecs;
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_decline()\n"));
+ dhcp_set_state(dhcp, DHCP_BACKING_OFF);
+ /* create and initialize the DHCP message header */
+ result = dhcp_create_request(netif);
+ if (result == ERR_OK)
+ {
+ dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
+ dhcp_option_byte(dhcp, DHCP_DECLINE);
+
+ dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
+ dhcp_option_short(dhcp, 576);
+
+ dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4);
+ dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr));
+
+ dhcp_option_trailer(dhcp);
+ /* resize pbuf to reflect true size of options */
+ pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+ udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
+ /* @todo: should we really connect here? we are performing sendto() */
+ udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT);
+ /* per section 4.4.4, broadcast DECLINE messages */
+ udp_sendto(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT);
+ dhcp_delete_request(netif);
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_decline: BACKING OFF\n"));
+ } else {
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_decline: could not allocate DHCP request\n"));
+ }
+ dhcp->tries++;
+ msecs = 10*1000;
+ dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_decline(): set request timeout %u msecs\n", msecs));
+ return result;
+}
+#endif
+
+
+/**
+ * Start the DHCP process, discover a DHCP server.
+ *
+ */
+static err_t dhcp_discover(struct netif *netif)
+{
+ struct dhcp *dhcp = netif->dhcp;
+ err_t result = ERR_OK;
+ u16_t msecs;
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_discover()\n"));
+ ip_addr_set(&dhcp->offered_ip_addr, IP_ADDR_ANY);
+ /* create and initialize the DHCP message header */
+ result = dhcp_create_request(netif);
+ if (result == ERR_OK)
+ {
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_discover: making request\n"));
+ dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
+ dhcp_option_byte(dhcp, DHCP_DISCOVER);
+
+ dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
+ dhcp_option_short(dhcp, 576);
+
+ dhcp_option(dhcp, DHCP_OPTION_PARAMETER_REQUEST_LIST, 4/*num options*/);
+ dhcp_option_byte(dhcp, DHCP_OPTION_SUBNET_MASK);
+ dhcp_option_byte(dhcp, DHCP_OPTION_ROUTER);
+ dhcp_option_byte(dhcp, DHCP_OPTION_BROADCAST);
+ dhcp_option_byte(dhcp, DHCP_OPTION_DNS_SERVER);
+
+ dhcp_option_trailer(dhcp);
+
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_discover: realloc()ing\n"));
+ pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+ /* set receive callback function with netif as user data */
+ udp_recv(dhcp->pcb, dhcp_recv, netif);
+ udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
+ udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT);
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_discover: sendto(DISCOVER, IP_ADDR_BROADCAST, DHCP_SERVER_PORT)\n"));
+ udp_sendto(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT);
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_discover: deleting()ing\n"));
+ dhcp_delete_request(netif);
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_discover: SELECTING\n"));
+ dhcp_set_state(dhcp, DHCP_SELECTING);
+ } else {
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_discover: could not allocate DHCP request\n"));
+ }
+ dhcp->tries++;
+ msecs = dhcp->tries < 4 ? (dhcp->tries + 1) * 1000 : 10 * 1000;
+ dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_discover(): set request timeout %u msecs\n", msecs));
+ return result;
+}
+
+
+/**
+ * Bind the interface to the offered IP address.
+ *
+ * @param netif network interface to bind to the offered address
+ */
+static void dhcp_bind(struct netif *netif)
+{
+ struct dhcp *dhcp = netif->dhcp;
+ struct ip_addr sn_mask, gw_addr;
+ LWIP_ASSERT("dhcp_bind: netif != NULL", netif != NULL);
+ LWIP_ASSERT("dhcp_bind: dhcp != NULL", dhcp != NULL);
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_bind(netif=%p) %c%c%u\n", netif, netif->name[0], netif->name[1], netif->num));
+
+ /* temporary DHCP lease? */
+ if (dhcp->offered_t1_renew != 0xffffffffUL) {
+ /* set renewal period timer */
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_bind(): t1 renewal timer %lu secs\n", dhcp->offered_t1_renew));
+ dhcp->t1_timeout = (dhcp->offered_t1_renew + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS;
+ if (dhcp->t1_timeout == 0) dhcp->t1_timeout = 1;
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_bind(): set request timeout %u msecs\n", dhcp->offered_t1_renew*1000));
+ }
+ /* set renewal period timer */
+ if (dhcp->offered_t2_rebind != 0xffffffffUL) {
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_bind(): t2 rebind timer %lu secs\n", dhcp->offered_t2_rebind));
+ dhcp->t2_timeout = (dhcp->offered_t2_rebind + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS;
+ if (dhcp->t2_timeout == 0) dhcp->t2_timeout = 1;
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_bind(): set request timeout %u msecs\n", dhcp->offered_t2_rebind*1000));
+ }
+ /* copy offered network mask */
+ ip_addr_set(&sn_mask, &dhcp->offered_sn_mask);
+
+ /* subnet mask not given? */
+ /* TODO: this is not a valid check. what if the network mask is 0? */
+ if (sn_mask.addr == 0) {
+ /* choose a safe subnet mask given the network class */
+ u8_t first_octet = ip4_addr1(&sn_mask);
+ if (first_octet <= 127) sn_mask.addr = htonl(0xff000000);
+ else if (first_octet >= 192) sn_mask.addr = htonl(0xffffff00);
+ else sn_mask.addr = htonl(0xffff0000);
+ }
+
+ ip_addr_set(&gw_addr, &dhcp->offered_gw_addr);
+ /* gateway address not given? */
+ if (gw_addr.addr == 0) {
+ /* copy network address */
+ gw_addr.addr = (dhcp->offered_ip_addr.addr & sn_mask.addr);
+ /* use first host address on network as gateway */
+ gw_addr.addr |= htonl(0x00000001);
+ }
+
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_bind(): IP: 0x%08lx\n", dhcp->offered_ip_addr.addr));
+ netif_set_ipaddr(netif, &dhcp->offered_ip_addr);
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_bind(): SN: 0x%08lx\n", sn_mask.addr));
+ netif_set_netmask(netif, &sn_mask);
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_bind(): GW: 0x%08lx\n", gw_addr.addr));
+ netif_set_gw(netif, &gw_addr);
+ /* bring the interface up */
+ netif_set_up(netif);
+ /* netif is now bound to DHCP leased address */
+ dhcp_set_state(dhcp, DHCP_BOUND);
+}
+
+/**
+ * Renew an existing DHCP lease at the involved DHCP server.
+ *
+ * @param netif network interface which must renew its lease
+ */
+err_t dhcp_renew(struct netif *netif)
+{
+ struct dhcp *dhcp = netif->dhcp;
+ err_t result;
+ u16_t msecs;
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_renew()\n"));
+ dhcp_set_state(dhcp, DHCP_RENEWING);
+
+ /* create and initialize the DHCP message header */
+ result = dhcp_create_request(netif);
+ if (result == ERR_OK) {
+
+ dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
+ dhcp_option_byte(dhcp, DHCP_REQUEST);
+
+ dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
+ /* TODO: use netif->mtu in some way */
+ dhcp_option_short(dhcp, 576);
+
+#if 0
+ dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4);
+ dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr));
+#endif
+
+#if 0
+ dhcp_option(dhcp, DHCP_OPTION_SERVER_ID, 4);
+ dhcp_option_long(dhcp, ntohl(dhcp->server_ip_addr.addr));
+#endif
+ /* append DHCP message trailer */
+ dhcp_option_trailer(dhcp);
+
+ pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+ udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
+ udp_connect(dhcp->pcb, &dhcp->server_ip_addr, DHCP_SERVER_PORT);
+ udp_send(dhcp->pcb, dhcp->p_out);
+ dhcp_delete_request(netif);
+
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_renew: RENEWING\n"));
+ } else {
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_renew: could not allocate DHCP request\n"));
+ }
+ dhcp->tries++;
+ /* back-off on retries, but to a maximum of 20 seconds */
+ msecs = dhcp->tries < 10 ? dhcp->tries * 2000 : 20 * 1000;
+ dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_renew(): set request timeout %u msecs\n", msecs));
+ return result;
+}
+
+/**
+ * Rebind with a DHCP server for an existing DHCP lease.
+ *
+ * @param netif network interface which must rebind with a DHCP server
+ */
+static err_t dhcp_rebind(struct netif *netif)
+{
+ struct dhcp *dhcp = netif->dhcp;
+ err_t result;
+ u16_t msecs;
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_rebind()\n"));
+ dhcp_set_state(dhcp, DHCP_REBINDING);
+
+ /* create and initialize the DHCP message header */
+ result = dhcp_create_request(netif);
+ if (result == ERR_OK)
+ {
+
+ dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
+ dhcp_option_byte(dhcp, DHCP_REQUEST);
+
+ dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
+ dhcp_option_short(dhcp, 576);
+
+#if 0
+ dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4);
+ dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr));
+
+ dhcp_option(dhcp, DHCP_OPTION_SERVER_ID, 4);
+ dhcp_option_long(dhcp, ntohl(dhcp->server_ip_addr.addr));
+#endif
+
+ dhcp_option_trailer(dhcp);
+
+ pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+ /* set remote IP association to any DHCP server */
+ udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
+ udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT);
+ /* broadcast to server */
+ udp_sendto(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT);
+ dhcp_delete_request(netif);
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_rebind: REBINDING\n"));
+ } else {
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_rebind: could not allocate DHCP request\n"));
+ }
+ dhcp->tries++;
+ msecs = dhcp->tries < 10 ? dhcp->tries * 1000 : 10 * 1000;
+ dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_rebind(): set request timeout %u msecs\n", msecs));
+ return result;
+}
+
+/**
+ * Release a DHCP lease.
+ *
+ * @param netif network interface which must release its lease
+ */
+err_t dhcp_release(struct netif *netif)
+{
+ struct dhcp *dhcp = netif->dhcp;
+ err_t result;
+ u16_t msecs;
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_release()\n"));
+
+ /* idle DHCP client */
+ dhcp_set_state(dhcp, DHCP_OFF);
+ /* clean old DHCP offer */
+ dhcp->server_ip_addr.addr = 0;
+ dhcp->offered_ip_addr.addr = dhcp->offered_sn_mask.addr = 0;
+ dhcp->offered_gw_addr.addr = dhcp->offered_bc_addr.addr = 0;
+ dhcp->offered_t0_lease = dhcp->offered_t1_renew = dhcp->offered_t2_rebind = 0;
+ dhcp->dns_count = 0;
+
+ /* create and initialize the DHCP message header */
+ result = dhcp_create_request(netif);
+ if (result == ERR_OK) {
+ dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
+ dhcp_option_byte(dhcp, DHCP_RELEASE);
+
+ dhcp_option_trailer(dhcp);
+
+ pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+ udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
+ udp_connect(dhcp->pcb, &dhcp->server_ip_addr, DHCP_SERVER_PORT);
+ udp_send(dhcp->pcb, dhcp->p_out);
+ dhcp_delete_request(netif);
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_release: RELEASED, DHCP_OFF\n"));
+ } else {
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_release: could not allocate DHCP request\n"));
+ }
+ dhcp->tries++;
+ msecs = dhcp->tries < 10 ? dhcp->tries * 1000 : 10 * 1000;
+ dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_release(): set request timeout %u msecs\n", msecs));
+ /* bring the interface down */
+ netif_set_down(netif);
+ /* remove IP address from interface */
+ netif_set_ipaddr(netif, IP_ADDR_ANY);
+ netif_set_gw(netif, IP_ADDR_ANY);
+ netif_set_netmask(netif, IP_ADDR_ANY);
+
+ /* TODO: netif_down(netif); */
+ return result;
+}
+/**
+ * Remove the DHCP client from the interface.
+ *
+ * @param netif The network interface to stop DHCP on
+ */
+void dhcp_stop(struct netif *netif)
+{
+ struct dhcp *dhcp = netif->dhcp;
+ LWIP_ASSERT("dhcp_stop: netif != NULL", netif != NULL);
+
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_stop()\n"));
+ /* netif is DHCP configured? */
+ if (dhcp != NULL)
+ {
+ if (dhcp->pcb != NULL)
+ {
+ udp_remove(dhcp->pcb);
+ dhcp->pcb = NULL;
+ }
+ if (dhcp->p != NULL)
+ {
+ pbuf_free(dhcp->p);
+ dhcp->p = NULL;
+ }
+ /* free unfolded reply */
+ dhcp_free_reply(dhcp);
+ mem_free((void *)dhcp);
+ netif->dhcp = NULL;
+ }
+}
+
+/*
+ * Set the DHCP state of a DHCP client.
+ *
+ * If the state changed, reset the number of tries.
+ *
+ * TODO: we might also want to reset the timeout here?
+ */
+static void dhcp_set_state(struct dhcp *dhcp, unsigned char new_state)
+{
+ if (new_state != dhcp->state)
+ {
+ dhcp->state = new_state;
+ dhcp->tries = 0;
+ }
+}
+
+/*
+ * Concatenate an option type and length field to the outgoing
+ * DHCP message.
+ *
+ */
+static void dhcp_option(struct dhcp *dhcp, u8_t option_type, u8_t option_len)
+{
+ LWIP_ASSERT("dhcp_option_short: dhcp->options_out_len + 2 + option_len <= DHCP_OPTIONS_LEN", dhcp->options_out_len + 2 + option_len <= DHCP_OPTIONS_LEN);
+ dhcp->msg_out->options[dhcp->options_out_len++] = option_type;
+ dhcp->msg_out->options[dhcp->options_out_len++] = option_len;
+}
+/*
+ * Concatenate a single byte to the outgoing DHCP message.
+ *
+ */
+static void dhcp_option_byte(struct dhcp *dhcp, u8_t value)
+{
+ LWIP_ASSERT("dhcp_option_short: dhcp->options_out_len < DHCP_OPTIONS_LEN", dhcp->options_out_len < DHCP_OPTIONS_LEN);
+ dhcp->msg_out->options[dhcp->options_out_len++] = value;
+}
+static void dhcp_option_short(struct dhcp *dhcp, u16_t value)
+{
+ LWIP_ASSERT("dhcp_option_short: dhcp->options_out_len + 2 <= DHCP_OPTIONS_LEN", dhcp->options_out_len + 2 <= DHCP_OPTIONS_LEN);
+ dhcp->msg_out->options[dhcp->options_out_len++] = (value & 0xff00U) >> 8;
+ dhcp->msg_out->options[dhcp->options_out_len++] = value & 0x00ffU;
+}
+static void dhcp_option_long(struct dhcp *dhcp, u32_t value)
+{
+ LWIP_ASSERT("dhcp_option_long: dhcp->options_out_len + 4 <= DHCP_OPTIONS_LEN", dhcp->options_out_len + 4 <= DHCP_OPTIONS_LEN);
+ dhcp->msg_out->options[dhcp->options_out_len++] = (value & 0xff000000UL) >> 24;
+ dhcp->msg_out->options[dhcp->options_out_len++] = (value & 0x00ff0000UL) >> 16;
+ dhcp->msg_out->options[dhcp->options_out_len++] = (value & 0x0000ff00UL) >> 8;
+ dhcp->msg_out->options[dhcp->options_out_len++] = (value & 0x000000ffUL);
+}
+
+/**
+ * Extract the DHCP message and the DHCP options.
+ *
+ * Extract the DHCP message and the DHCP options, each into a contiguous
+ * piece of memory. As a DHCP message is variable sized by its options,
+ * and also allows overriding some fields for options, the easy approach
+ * is to first unfold the options into a conitguous piece of memory, and
+ * use that further on.
+ *
+ */
+static err_t dhcp_unfold_reply(struct dhcp *dhcp)
+{
+ struct pbuf *p = dhcp->p;
+ u8_t *ptr;
+ u16_t i;
+ u16_t j = 0;
+ LWIP_ASSERT("dhcp->p != NULL", dhcp->p != NULL);
+ /* free any left-overs from previous unfolds */
+ dhcp_free_reply(dhcp);
+ /* options present? */
+ if (dhcp->p->tot_len > (sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN))
+ {
+ dhcp->options_in_len = dhcp->p->tot_len - (sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN);
+ dhcp->options_in = mem_malloc(dhcp->options_in_len);
+ if (dhcp->options_in == NULL)
+ {
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_unfold_reply(): could not allocate dhcp->options\n"));
+ return ERR_MEM;
+ }
+ }
+ dhcp->msg_in = mem_malloc(sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN);
+ if (dhcp->msg_in == NULL)
+ {
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_unfold_reply(): could not allocate dhcp->msg_in\n"));
+ mem_free((void *)dhcp->options_in);
+ dhcp->options_in = NULL;
+ return ERR_MEM;
+ }
+
+ ptr = (u8_t *)dhcp->msg_in;
+ /* proceed through struct dhcp_msg */
+ for (i = 0; i < sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN; i++)
+ {
+ *ptr++ = ((u8_t *)p->payload)[j++];
+ /* reached end of pbuf? */
+ if (j == p->len)
+ {
+ /* proceed to next pbuf in chain */
+ p = p->next;
+ j = 0;
+ }
+ }
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_unfold_reply(): copied %u bytes into dhcp->msg_in[]\n", i));
+ if (dhcp->options_in != NULL) {
+ ptr = (u8_t *)dhcp->options_in;
+ /* proceed through options */
+ for (i = 0; i < dhcp->options_in_len; i++) {
+ *ptr++ = ((u8_t *)p->payload)[j++];
+ /* reached end of pbuf? */
+ if (j == p->len) {
+ /* proceed to next pbuf in chain */
+ p = p->next;
+ j = 0;
+ }
+ }
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_unfold_reply(): copied %u bytes to dhcp->options_in[]\n", i));
+ }
+ return ERR_OK;
+}
+
+/**
+ * Free the incoming DHCP message including contiguous copy of
+ * its DHCP options.
+ *
+ */
+static void dhcp_free_reply(struct dhcp *dhcp)
+{
+ if (dhcp->msg_in != NULL) {
+ mem_free((void *)dhcp->msg_in);
+ dhcp->msg_in = NULL;
+ }
+ if (dhcp->options_in) {
+ mem_free((void *)dhcp->options_in);
+ dhcp->options_in = NULL;
+ dhcp->options_in_len = 0;
+ }
+ LWIP_DEBUGF(DHCP_DEBUG, ("dhcp_free_reply(): free'd\n"));
+}
+
+
+/**
+ * If an incoming DHCP message is in response to us, then trigger the state machine
+ */
+static void dhcp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *addr, u16_t port)
+{
+ struct netif *netif = (struct netif *)arg;
+ struct dhcp *dhcp = netif->dhcp;
+ struct dhcp_msg *reply_msg = (struct dhcp_msg *)p->payload;
+ u8_t *options_ptr;
+ u8_t msg_type;
+ u8_t i;
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_recv(pbuf = %p) from DHCP server %u.%u.%u.%u port %u\n", p,
+ (unsigned int)(ntohl(addr->addr) >> 24 & 0xff), (unsigned int)(ntohl(addr->addr) >> 16 & 0xff),
+ (unsigned int)(ntohl(addr->addr) >> 8 & 0xff), (unsigned int)(ntohl(addr->addr) & 0xff), port));
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("pbuf->len = %u\n", p->len));
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("pbuf->tot_len = %u\n", p->tot_len));
+ /* prevent warnings about unused arguments */
+ (void)pcb; (void)addr; (void)port;
+ dhcp->p = p;
+ /* TODO: check packet length before reading them */
+ if (reply_msg->op != DHCP_BOOTREPLY) {
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("not a DHCP reply message, but type %u\n", reply_msg->op));
+ pbuf_free(p);
+ dhcp->p = NULL;
+ return;
+ }
+ /* iterate through hardware address and match against DHCP message */
+ for (i = 0; i < netif->hwaddr_len; i++) {
+ if (netif->hwaddr[i] != reply_msg->chaddr[i]) {
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("netif->hwaddr[%u]==%02x != reply_msg->chaddr[%u]==%02x\n",
+ i, netif->hwaddr[i], i, reply_msg->chaddr[i]));
+ pbuf_free(p);
+ dhcp->p = NULL;
+ return;
+ }
+ }
+ /* match transaction ID against what we expected */
+ if (ntohl(reply_msg->xid) != dhcp->xid) {
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("transaction id mismatch\n"));
+ pbuf_free(p);
+ dhcp->p = NULL;
+ return;
+ }
+ /* option fields could be unfold? */
+ if (dhcp_unfold_reply(dhcp) != ERR_OK) {
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("problem unfolding DHCP message - too short on memory?\n"));
+ pbuf_free(p);
+ dhcp->p = NULL;
+ return;
+ }
+
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("searching DHCP_OPTION_MESSAGE_TYPE\n"));
+ /* obtain pointer to DHCP message type */
+ options_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_MESSAGE_TYPE);
+ if (options_ptr == NULL) {
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("DHCP_OPTION_MESSAGE_TYPE option not found\n"));
+ pbuf_free(p);
+ dhcp->p = NULL;
+ return;
+ }
+
+ /* read DHCP message type */
+ msg_type = dhcp_get_option_byte(options_ptr + 2);
+ /* message type is DHCP ACK? */
+ if (msg_type == DHCP_ACK) {
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("DHCP_ACK received\n"));
+ /* in requesting state? */
+ if (dhcp->state == DHCP_REQUESTING) {
+ dhcp_handle_ack(netif);
+ dhcp->request_timeout = 0;
+#if DHCP_DOES_ARP_CHECK
+ /* check if the acknowledged lease address is already in use */
+ dhcp_check(netif);
+#else
+ /* bind interface to the acknowledged lease address */
+ dhcp_bind(netif);
+#endif
+ }
+ /* already bound to the given lease address? */
+ else if ((dhcp->state == DHCP_REBOOTING) || (dhcp->state == DHCP_REBINDING) || (dhcp->state == DHCP_RENEWING)) {
+ dhcp->request_timeout = 0;
+ dhcp_bind(netif);
+ }
+ }
+ /* received a DHCP_NAK in appropriate state? */
+ else if ((msg_type == DHCP_NAK) &&
+ ((dhcp->state == DHCP_REBOOTING) || (dhcp->state == DHCP_REQUESTING) ||
+ (dhcp->state == DHCP_REBINDING) || (dhcp->state == DHCP_RENEWING ))) {
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("DHCP_NAK received\n"));
+ dhcp->request_timeout = 0;
+ dhcp_handle_nak(netif);
+ }
+ /* received a DHCP_OFFER in DHCP_SELECTING state? */
+ else if ((msg_type == DHCP_OFFER) && (dhcp->state == DHCP_SELECTING)) {
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("DHCP_OFFER received in DHCP_SELECTING state\n"));
+ dhcp->request_timeout = 0;
+ /* remember offered lease */
+ dhcp_handle_offer(netif);
+ }
+ pbuf_free(p);
+ dhcp->p = NULL;
+}
+
+
+static err_t dhcp_create_request(struct netif *netif)
+{
+ struct dhcp *dhcp = netif->dhcp;
+ u16_t i;
+ LWIP_ASSERT("dhcp_create_request: dhcp->p_out == NULL", dhcp->p_out == NULL);
+ LWIP_ASSERT("dhcp_create_request: dhcp->msg_out == NULL", dhcp->msg_out == NULL);
+ dhcp->p_out = pbuf_alloc(PBUF_TRANSPORT, sizeof(struct dhcp_msg), PBUF_RAM);
+ if (dhcp->p_out == NULL) {
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_create_request(): could not allocate pbuf\n"));
+ return ERR_MEM;
+ }
+ /* give unique transaction identifier to this request */
+ dhcp->xid = xid++;
+
+ dhcp->msg_out = (struct dhcp_msg *)dhcp->p_out->payload;
+
+ dhcp->msg_out->op = DHCP_BOOTREQUEST;
+ /* TODO: make link layer independent */
+ dhcp->msg_out->htype = DHCP_HTYPE_ETH;
+ /* TODO: make link layer independent */
+ dhcp->msg_out->hlen = DHCP_HLEN_ETH;
+ dhcp->msg_out->hops = 0;
+ dhcp->msg_out->xid = htonl(dhcp->xid);
+ dhcp->msg_out->secs = 0;
+ dhcp->msg_out->flags = 0;
+ dhcp->msg_out->ciaddr.addr = netif->ip_addr.addr;
+ dhcp->msg_out->yiaddr.addr = 0;
+ dhcp->msg_out->siaddr.addr = 0;
+ dhcp->msg_out->giaddr.addr = 0;
+ for (i = 0; i < DHCP_CHADDR_LEN; i++) {
+ /* copy netif hardware address, pad with zeroes */
+ dhcp->msg_out->chaddr[i] = (i < netif->hwaddr_len) ? netif->hwaddr[i] : 0/* pad byte*/;
+ }
+ for (i = 0; i < DHCP_SNAME_LEN; i++) dhcp->msg_out->sname[i] = 0;
+ for (i = 0; i < DHCP_FILE_LEN; i++) dhcp->msg_out->file[i] = 0;
+ dhcp->msg_out->cookie = htonl(0x63825363UL);
+ dhcp->options_out_len = 0;
+ /* fill options field with an incrementing array (for debugging purposes) */
+ for (i = 0; i < DHCP_OPTIONS_LEN; i++) dhcp->msg_out->options[i] = i;
+ return ERR_OK;
+}
+
+static void dhcp_delete_request(struct netif *netif)
+{
+ struct dhcp *dhcp = netif->dhcp;
+ LWIP_ASSERT("dhcp_free_msg: dhcp->p_out != NULL", dhcp->p_out != NULL);
+ LWIP_ASSERT("dhcp_free_msg: dhcp->msg_out != NULL", dhcp->msg_out != NULL);
+ pbuf_free(dhcp->p_out);
+ dhcp->p_out = NULL;
+ dhcp->msg_out = NULL;
+}
+
+/**
+ * Add a DHCP message trailer
+ *
+ * Adds the END option to the DHCP message, and if
+ * necessary, up to three padding bytes.
+ */
+
+static void dhcp_option_trailer(struct dhcp *dhcp)
+{
+ LWIP_ASSERT("dhcp_option_trailer: dhcp->msg_out != NULL\n", dhcp->msg_out != NULL);
+ LWIP_ASSERT("dhcp_option_trailer: dhcp->options_out_len < DHCP_OPTIONS_LEN\n", dhcp->options_out_len < DHCP_OPTIONS_LEN);
+ dhcp->msg_out->options[dhcp->options_out_len++] = DHCP_OPTION_END;
+ /* packet is too small, or not 4 byte aligned? */
+ while ((dhcp->options_out_len < DHCP_MIN_OPTIONS_LEN) || (dhcp->options_out_len & 3)) {
+ /* LWIP_DEBUGF(DHCP_DEBUG, ("dhcp_option_trailer: dhcp->options_out_len=%u, DHCP_OPTIONS_LEN=%u", dhcp->options_out_len, DHCP_OPTIONS_LEN)); */
+ LWIP_ASSERT("dhcp_option_trailer: dhcp->options_out_len < DHCP_OPTIONS_LEN\n", dhcp->options_out_len < DHCP_OPTIONS_LEN);
+ /* add a fill/padding byte */
+ dhcp->msg_out->options[dhcp->options_out_len++] = 0;
+ }
+}
+
+/**
+ * Find the offset of a DHCP option inside the DHCP message.
+ *
+ * @param client DHCP client
+ * @param option_type
+ *
+ * @return a byte offset into the UDP message where the option was found, or
+ * zero if the given option was not found.
+ */
+static u8_t *dhcp_get_option_ptr(struct dhcp *dhcp, u8_t option_type)
+{
+ u8_t overload = DHCP_OVERLOAD_NONE;
+
+ /* options available? */
+ if ((dhcp->options_in != NULL) && (dhcp->options_in_len > 0)) {
+ /* start with options field */
+ u8_t *options = (u8_t *)dhcp->options_in;
+ u16_t offset = 0;
+ /* at least 1 byte to read and no end marker, then at least 3 bytes to read? */
+ while ((offset < dhcp->options_in_len) && (options[offset] != DHCP_OPTION_END)) {
+ /* LWIP_DEBUGF(DHCP_DEBUG, ("msg_offset=%u, q->len=%u", msg_offset, q->len)); */
+ /* are the sname and/or file field overloaded with options? */
+ if (options[offset] == DHCP_OPTION_OVERLOAD) {
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("overloaded message detected\n"));
+ /* skip option type and length */
+ offset += 2;
+ overload = options[offset++];
+ }
+ /* requested option found */
+ else if (options[offset] == option_type) {
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("option found at offset %u in options\n", offset));
+ return &options[offset];
+ /* skip option */
+ } else {
+ LWIP_DEBUGF(DHCP_DEBUG, ("skipping option %u in options\n", options[offset]));
+ /* skip option type */
+ offset++;
+ /* skip option length, and then length bytes */
+ offset += 1 + options[offset];
+ }
+ }
+ /* is this an overloaded message? */
+ if (overload != DHCP_OVERLOAD_NONE) {
+ u16_t field_len;
+ if (overload == DHCP_OVERLOAD_FILE) {
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("overloaded file field\n"));
+ options = (u8_t *)&dhcp->msg_in->file;
+ field_len = DHCP_FILE_LEN;
+ } else if (overload == DHCP_OVERLOAD_SNAME) {
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("overloaded sname field\n"));
+ options = (u8_t *)&dhcp->msg_in->sname;
+ field_len = DHCP_SNAME_LEN;
+ /* TODO: check if else if () is necessary */
+ } else {
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("overloaded sname and file field\n"));
+ options = (u8_t *)&dhcp->msg_in->sname;
+ field_len = DHCP_FILE_LEN + DHCP_SNAME_LEN;
+ }
+ offset = 0;
+
+ /* at least 1 byte to read and no end marker */
+ while ((offset < field_len) && (options[offset] != DHCP_OPTION_END)) {
+ if (options[offset] == option_type) {
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("option found at offset=%u\n", offset));
+ return &options[offset];
+ /* skip option */
+ } else {
+ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("skipping option %u\n", options[offset]));
+ /* skip option type */
+ offset++;
+ offset += 1 + options[offset];
+ }
+ }
+ }
+ }
+ return 0;
+}
+
+/**
+ * Return the byte of DHCP option data.
+ *
+ * @param client DHCP client.
+ * @param ptr pointer obtained by dhcp_get_option_ptr().
+ *
+ * @return byte value at the given address.
+ */
+static u8_t dhcp_get_option_byte(u8_t *ptr)
+{
+ LWIP_DEBUGF(DHCP_DEBUG, ("option byte value=%u\n", *ptr));
+ return *ptr;
+}
+
+/**
+ * Return the 16-bit value of DHCP option data.
+ *
+ * @param client DHCP client.
+ * @param ptr pointer obtained by dhcp_get_option_ptr().
+ *
+ * @return byte value at the given address.
+ */
+static u16_t dhcp_get_option_short(u8_t *ptr)
+{
+ u16_t value;
+ value = *ptr++ << 8;
+ value |= *ptr;
+ LWIP_DEBUGF(DHCP_DEBUG, ("option short value=%u\n", value));
+ return value;
+}
+
+/**
+ * Return the 32-bit value of DHCP option data.
+ *
+ * @param client DHCP client.
+ * @param ptr pointer obtained by dhcp_get_option_ptr().
+ *
+ * @return byte value at the given address.
+ */
+static u32_t dhcp_get_option_long(u8_t *ptr)
+{
+ u32_t value;
+ value = (u32_t)(*ptr++) << 24;
+ value |= (u32_t)(*ptr++) << 16;
+ value |= (u32_t)(*ptr++) << 8;
+ value |= (u32_t)(*ptr++);
+ LWIP_DEBUGF(DHCP_DEBUG, ("option long value=%lu\n", value));
+ return value;
+}
+
+#endif /* LWIP_DHCP */
--- /dev/null
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+
+/* inet.c
+ *
+ * Functions common to all TCP/IP modules, such as the Internet checksum and the
+ * byte order functions.
+ *
+ */
+
+
+#include "lwip/opt.h"
+
+#include "lwip/arch.h"
+
+#include "lwip/def.h"
+#include "lwip/inet.h"
+
+#include "lwip/sys.h"
+
+/* This is a reference implementation of the checksum algorithm
+
+ - it may not work on all architectures, and all processors, particularly
+ if they have issues with alignment and 16 bit access.
+
+ - in this case you will need to port it to your architecture and
+ #define LWIP_CHKSUM <your_checksum_routine>
+ in your sys_arch.h
+*/
+#ifndef LWIP_CHKSUM
+#define LWIP_CHKSUM lwip_standard_chksum
+static u16_t
+lwip_standard_chksum(void *dataptr, int len)
+{
+ u32_t acc;
+
+ LWIP_DEBUGF(INET_DEBUG, ("lwip_chksum(%p, %d)\n", (void *)dataptr, len));
+ for(acc = 0; len > 1; len -= 2) {
+ /* acc = acc + *((u16_t *)dataptr)++;*/
+ acc += *(u16_t *)dataptr;
+ dataptr = (void *)((u16_t *)dataptr + 1);
+ }
+
+ /* add up any odd byte */
+ if (len == 1) {
+ acc += htons((u16_t)((*(u8_t *)dataptr) & 0xff) << 8);
+ LWIP_DEBUGF(INET_DEBUG, ("inet: chksum: odd byte %d\n", (unsigned int)(*(u8_t *)dataptr)));
+ } else {
+ LWIP_DEBUGF(INET_DEBUG, ("inet: chksum: no odd byte\n"));
+ }
+ acc = (acc >> 16) + (acc & 0xffffUL);
+
+ if ((acc & 0xffff0000) != 0) {
+ acc = (acc >> 16) + (acc & 0xffffUL);
+ }
+
+ return (u16_t)acc;
+}
+#endif
+
+/* inet_chksum_pseudo:
+ *
+ * Calculates the pseudo Internet checksum used by TCP and UDP for a pbuf chain.
+ */
+
+u16_t
+inet_chksum_pseudo(struct pbuf *p,
+ struct ip_addr *src, struct ip_addr *dest,
+ u8_t proto, u16_t proto_len)
+{
+ u32_t acc;
+ struct pbuf *q;
+ u8_t swapped;
+
+ acc = 0;
+ swapped = 0;
+ /* iterate through all pbuf in chain */
+ for(q = p; q != NULL; q = q->next) {
+ LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): checksumming pbuf %p (has next %p) \n",
+ (void *)q, (void *)q->next));
+ acc += LWIP_CHKSUM(q->payload, q->len);
+ /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): unwrapped lwip_chksum()=%lx \n", acc));*/
+ while (acc >> 16) {
+ acc = (acc & 0xffffUL) + (acc >> 16);
+ }
+ if (q->len % 2 != 0) {
+ swapped = 1 - swapped;
+ acc = ((acc & 0xff) << 8) | ((acc & 0xff00UL) >> 8);
+ }
+ /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): wrapped lwip_chksum()=%lx \n", acc));*/
+ }
+
+ if (swapped) {
+ acc = ((acc & 0xff) << 8) | ((acc & 0xff00UL) >> 8);
+ }
+ acc += (src->addr & 0xffffUL);
+ acc += ((src->addr >> 16) & 0xffffUL);
+ acc += (dest->addr & 0xffffUL);
+ acc += ((dest->addr >> 16) & 0xffffUL);
+ acc += (u32_t)htons((u16_t)proto);
+ acc += (u32_t)htons(proto_len);
+
+ while (acc >> 16) {
+ acc = (acc & 0xffffUL) + (acc >> 16);
+ }
+ LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): pbuf chain lwip_chksum()=%lx\n", acc));
+ return (u16_t)~(acc & 0xffffUL);
+}
+
+/* inet_chksum:
+ *
+ * Calculates the Internet checksum over a portion of memory. Used primarely for IP
+ * and ICMP.
+ */
+
+u16_t
+inet_chksum(void *dataptr, u16_t len)
+{
+ u32_t acc;
+
+ acc = LWIP_CHKSUM(dataptr, len);
+ while (acc >> 16) {
+ acc = (acc & 0xffff) + (acc >> 16);
+ }
+ return (u16_t)~(acc & 0xffff);
+}
+
+u16_t
+inet_chksum_pbuf(struct pbuf *p)
+{
+ u32_t acc;
+ struct pbuf *q;
+ u8_t swapped;
+
+ acc = 0;
+ swapped = 0;
+ for(q = p; q != NULL; q = q->next) {
+ acc += LWIP_CHKSUM(q->payload, q->len);
+ while (acc >> 16) {
+ acc = (acc & 0xffffUL) + (acc >> 16);
+ }
+ if (q->len % 2 != 0) {
+ swapped = 1 - swapped;
+ acc = (acc & 0x00ffUL << 8) | (acc & 0xff00UL >> 8);
+ }
+ }
+
+ if (swapped) {
+ acc = ((acc & 0x00ffUL) << 8) | ((acc & 0xff00UL) >> 8);
+ }
+ return (u16_t)~(acc & 0xffffUL);
+}
+
+/* Here for now until needed in other places in lwIP */
+#ifndef isascii
+#define in_range(c, lo, up) ((u8_t)c >= lo && (u8_t)c <= up)
+#define isascii(c) in_range(c, 0x20, 0x7f)
+#define isdigit(c) in_range(c, '0', '9')
+#define isxdigit(c) (isdigit(c) || in_range(c, 'a', 'f') || in_range(c, 'A', 'F'))
+#define islower(c) in_range(c, 'a', 'z')
+#define isspace(c) (c == ' ' || c == '\f' || c == '\n' || c == '\r' || c == '\t' || c == '\v')
+#endif
+
+
+ /*
+ * Ascii internet address interpretation routine.
+ * The value returned is in network order.
+ */
+
+ /* */
+ /* inet_addr */
+ u32_t inet_addr(const char *cp)
+ {
+ struct in_addr val;
+
+ if (inet_aton(cp, &val)) {
+ return (val.s_addr);
+ }
+ return (INADDR_NONE);
+ }
+
+ /*
+ * Check whether "cp" is a valid ascii representation
+ * of an Internet address and convert to a binary address.
+ * Returns 1 if the address is valid, 0 if not.
+ * This replaces inet_addr, the return value from which
+ * cannot distinguish between failure and a local broadcast address.
+ */
+ /* */
+ /* inet_aton */
+ int inet_aton(const char *cp, struct in_addr *addr)
+ {
+ u32_t val;
+ int base, n;
+ char c;
+ u32_t parts[4];
+ u32_t* pp = parts;
+
+ c = *cp;
+ for (;;) {
+ /*
+ * Collect number up to ``.''.
+ * Values are specified as for C:
+ * 0x=hex, 0=octal, isdigit=decimal.
+ */
+ if (!isdigit(c))
+ return (0);
+ val = 0; base = 10;
+ if (c == '0') {
+ c = *++cp;
+ if (c == 'x' || c == 'X')
+ base = 16, c = *++cp;
+ else
+ base = 8;
+ }
+ for (;;) {
+ if (isdigit(c)) {
+ val = (val * base) + (int)(c - '0');
+ c = *++cp;
+ } else if (base == 16 && isxdigit(c)) {
+ val = (val << 4) |
+ (int)(c + 10 - (islower(c) ? 'a' : 'A'));
+ c = *++cp;
+ } else
+ break;
+ }
+ if (c == '.') {
+ /*
+ * Internet format:
+ * a.b.c.d
+ * a.b.c (with c treated as 16 bits)
+ * a.b (with b treated as 24 bits)
+ */
+ if (pp >= parts + 3)
+ return (0);
+ *pp++ = val;
+ c = *++cp;
+ } else
+ break;
+ }
+ /*
+ * Check for trailing characters.
+ */
+ if (c != '\0' && (!isascii(c) || !isspace(c)))
+ return (0);
+ /*
+ * Concoct the address according to
+ * the number of parts specified.
+ */
+ n = pp - parts + 1;
+ switch (n) {
+
+ case 0:
+ return (0); /* initial nondigit */
+
+ case 1: /* a -- 32 bits */
+ break;
+
+ case 2: /* a.b -- 8.24 bits */
+ if (val > 0xffffff)
+ return (0);
+ val |= parts[0] << 24;
+ break;
+
+ case 3: /* a.b.c -- 8.8.16 bits */
+ if (val > 0xffff)
+ return (0);
+ val |= (parts[0] << 24) | (parts[1] << 16);
+ break;
+
+ case 4: /* a.b.c.d -- 8.8.8.8 bits */
+ if (val > 0xff)
+ return (0);
+ val |= (parts[0] << 24) | (parts[1] << 16) | (parts[2] << 8);
+ break;
+ }
+ if (addr)
+ addr->s_addr = htonl(val);
+ return (1);
+ }
+
+/* Convert numeric IP address into decimal dotted ASCII representation.
+ * returns ptr to static buffer; not reentrant!
+ */
+char *inet_ntoa(struct in_addr addr)
+{
+ static char str[16];
+ u32_t s_addr = addr.s_addr;
+ char inv[3];
+ char *rp;
+ u8_t *ap;
+ u8_t rem;
+ u8_t n;
+ u8_t i;
+
+ rp = str;
+ ap = (u8_t *)&s_addr;
+ for(n = 0; n < 4; n++) {
+ i = 0;
+ do {
+ rem = *ap % (u8_t)10;
+ *ap /= (u8_t)10;
+ inv[i++] = '0' + rem;
+ } while(*ap);
+ while(i--)
+ *rp++ = inv[i];
+ *rp++ = '.';
+ ap++;
+ }
+ *--rp = 0;
+ return str;
+}
+
+
+#ifndef BYTE_ORDER
+#error BYTE_ORDER is not defined
+#endif
+#if BYTE_ORDER == LITTLE_ENDIAN
+
+u16_t
+htons(u16_t n)
+{
+ return ((n & 0xff) << 8) | ((n & 0xff00) >> 8);
+}
+
+u16_t
+ntohs(u16_t n)
+{
+ return htons(n);
+}
+
+u32_t
+htonl(u32_t n)
+{
+ return ((n & 0xff) << 24) |
+ ((n & 0xff00) << 8) |
+ ((n & 0xff0000) >> 8) |
+ ((n & 0xff000000) >> 24);
+}
+
+u32_t
+ntohl(u32_t n)
+{
+ return htonl(n);
+}
+
+#endif /* BYTE_ORDER == LITTLE_ENDIAN */
--- /dev/null
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+
+/* inet6.c
+ *
+ * Functions common to all TCP/IP modules, such as the Internet checksum and the
+ * byte order functions.
+ *
+ */
+
+
+#include "lwip/opt.h"
+
+#include "lwip/def.h"
+#include "lwip/inet.h"
+
+
+
+/* chksum:
+ *
+ * Sums up all 16 bit words in a memory portion. Also includes any odd byte.
+ * This function is used by the other checksum functions.
+ *
+ * For now, this is not optimized. Must be optimized for the particular processor
+ * arcitecture on which it is to run. Preferebly coded in assembler.
+ */
+
+static u32_t
+chksum(void *dataptr, u16_t len)
+{
+ u16_t *sdataptr = dataptr;
+ u32_t acc;
+
+
+ for(acc = 0; len > 1; len -= 2) {
+ acc += *sdataptr++;
+ }
+
+ /* add up any odd byte */
+ if (len == 1) {
+ acc += htons((u16_t)(*(u8_t *)dataptr) << 8);
+ }
+
+ return acc;
+
+}
+
+/* inet_chksum_pseudo:
+ *
+ * Calculates the pseudo Internet checksum used by TCP and UDP for a pbuf chain.
+ */
+
+u16_t
+inet_chksum_pseudo(struct pbuf *p,
+ struct ip_addr *src, struct ip_addr *dest,
+ u8_t proto, u32_t proto_len)
+{
+ u32_t acc;
+ struct pbuf *q;
+ u8_t swapped, i;
+
+ acc = 0;
+ swapped = 0;
+ for(q = p; q != NULL; q = q->next) {
+ acc += chksum(q->payload, q->len);
+ while (acc >> 16) {
+ acc = (acc & 0xffff) + (acc >> 16);
+ }
+ if (q->len % 2 != 0) {
+ swapped = 1 - swapped;
+ acc = ((acc & 0xff) << 8) | ((acc & 0xff00) >> 8);
+ }
+ }
+
+ if (swapped) {
+ acc = ((acc & 0xff) << 8) | ((acc & 0xff00) >> 8);
+ }
+
+ for(i = 0; i < 8; i++) {
+ acc += ((u16_t *)src->addr)[i] & 0xffff;
+ acc += ((u16_t *)dest->addr)[i] & 0xffff;
+ while (acc >> 16) {
+ acc = (acc & 0xffff) + (acc >> 16);
+ }
+ }
+ acc += (u16_t)htons((u16_t)proto);
+ acc += ((u16_t *)&proto_len)[0] & 0xffff;
+ acc += ((u16_t *)&proto_len)[1] & 0xffff;
+
+ while (acc >> 16) {
+ acc = (acc & 0xffff) + (acc >> 16);
+ }
+ return ~(acc & 0xffff);
+}
+
+/* inet_chksum:
+ *
+ * Calculates the Internet checksum over a portion of memory. Used primarely for IP
+ * and ICMP.
+ */
+
+u16_t
+inet_chksum(void *dataptr, u16_t len)
+{
+ u32_t acc, sum;
+
+ acc = chksum(dataptr, len);
+ sum = (acc & 0xffff) + (acc >> 16);
+ sum += (sum >> 16);
+ return ~(sum & 0xffff);
+}
+
+u16_t
+inet_chksum_pbuf(struct pbuf *p)
+{
+ u32_t acc;
+ struct pbuf *q;
+ u8_t swapped;
+
+ acc = 0;
+ swapped = 0;
+ for(q = p; q != NULL; q = q->next) {
+ acc += chksum(q->payload, q->len);
+ while (acc >> 16) {
+ acc = (acc & 0xffff) + (acc >> 16);
+ }
+ if (q->len % 2 != 0) {
+ swapped = 1 - swapped;
+ acc = (acc & 0xff << 8) | (acc & 0xff00 >> 8);
+ }
+ }
+
+ if (swapped) {
+ acc = ((acc & 0xff) << 8) | ((acc & 0xff00) >> 8);
+ }
+ return ~(acc & 0xffff);
+}
+
--- /dev/null
+/*\r
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. The name of the author may not be used to endorse or promote products\r
+ * derived from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT\r
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT\r
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING\r
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY\r
+ * OF SUCH DAMAGE.\r
+ *\r
+ * This file is part of the lwIP TCP/IP stack.\r
+ *\r
+ * Author: Adam Dunkels <adam@sics.se>\r
+ *\r
+ */\r
+\r
+/* Some ICMP messages should be passed to the transport protocols. This\r
+ is not implemented. */\r
+\r
+#include "lwip/opt.h"\r
+\r
+#include "lwip/icmp.h"\r
+#include "lwip/inet.h"\r
+#include "lwip/ip.h"\r
+#include "lwip/def.h"\r
+\r
+#include "lwip/stats.h"\r
+\r
+#include "lwip/snmp.h"\r
+\r
+#include <string.h>\r
+\r
+void\r
+icmp_input(struct pbuf *p, struct netif *inp)\r
+{\r
+ unsigned char type;\r
+ unsigned char code;\r
+ struct icmp_echo_hdr *iecho;\r
+ struct ip_hdr *iphdr;\r
+ struct ip_addr tmpaddr;\r
+ u16_t hlen;\r
+\r
+ ICMP_STATS_INC(icmp.recv);\r
+ snmp_inc_icmpinmsgs();\r
+\r
+\r
+ iphdr = p->payload;\r
+ hlen = IPH_HL(iphdr) * 4;\r
+ if (pbuf_header(p, -((s16_t)hlen)) || (p->tot_len < sizeof(u16_t)*2)) {\r
+ LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: short ICMP (%u bytes) received\n", p->tot_len));\r
+ pbuf_free(p);\r
+ ICMP_STATS_INC(icmp.lenerr);\r
+ snmp_inc_icmpinerrors();\r
+ return;\r
+ }\r
+\r
+ type = *((u8_t *)p->payload);\r
+ code = *(((u8_t *)p->payload)+1);\r
+ switch (type) {\r
+ case ICMP_ECHO:\r
+ /* broadcast or multicast destination address? */\r
+ if (ip_addr_isbroadcast(&iphdr->dest, inp) || ip_addr_ismulticast(&iphdr->dest)) {\r
+ LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: Not echoing to multicast or broadcast pings\n"));\r
+ ICMP_STATS_INC(icmp.err);\r
+ pbuf_free(p);\r
+ return;\r
+ }\r
+ LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ping\n"));\r
+ if (p->tot_len < sizeof(struct icmp_echo_hdr)) {\r
+ LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: bad ICMP echo received\n"));\r
+ pbuf_free(p);\r
+ ICMP_STATS_INC(icmp.lenerr);\r
+ snmp_inc_icmpinerrors();\r
+\r
+ return;\r
+ }\r
+ iecho = p->payload;\r
+ if (inet_chksum_pbuf(p) != 0) {\r
+ LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: checksum failed for received ICMP echo\n"));\r
+ pbuf_free(p);\r
+ ICMP_STATS_INC(icmp.chkerr);\r
+ snmp_inc_icmpinerrors();\r
+ return;\r
+ }\r
+ tmpaddr.addr = iphdr->src.addr;\r
+ iphdr->src.addr = iphdr->dest.addr;\r
+ iphdr->dest.addr = tmpaddr.addr;\r
+ ICMPH_TYPE_SET(iecho, ICMP_ER);\r
+ /* adjust the checksum */\r
+ if (iecho->chksum >= htons(0xffff - (ICMP_ECHO << 8))) {\r
+ iecho->chksum += htons(ICMP_ECHO << 8) + 1;\r
+ } else {\r
+ iecho->chksum += htons(ICMP_ECHO << 8);\r
+ }\r
+ ICMP_STATS_INC(icmp.xmit);\r
+ /* increase number of messages attempted to send */\r
+ snmp_inc_icmpoutmsgs();\r
+ /* increase number of echo replies attempted to send */\r
+ snmp_inc_icmpoutechoreps();\r
+\r
+ pbuf_header(p, hlen);\r
+ ip_output_if(p, &(iphdr->src), IP_HDRINCL,\r
+ IPH_TTL(iphdr), 0, IP_PROTO_ICMP, inp);\r
+ break;\r
+ default:\r
+ LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ICMP type %d code %d not supported.\n", (int)type, (int)code));\r
+ ICMP_STATS_INC(icmp.proterr);\r
+ ICMP_STATS_INC(icmp.drop);\r
+ }\r
+ pbuf_free(p);\r
+}\r
+\r
+void\r
+icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t)\r
+{\r
+ struct pbuf *q;\r
+ struct ip_hdr *iphdr;\r
+ struct icmp_dur_hdr *idur;\r
+\r
+ q = pbuf_alloc(PBUF_IP, 8 + IP_HLEN + 8, PBUF_RAM);\r
+ /* ICMP header + IP header + 8 bytes of data */\r
+\r
+ iphdr = p->payload;\r
+\r
+ idur = q->payload;\r
+ ICMPH_TYPE_SET(idur, ICMP_DUR);\r
+ ICMPH_CODE_SET(idur, t);\r
+\r
+ memcpy((char *)q->payload + 8, p->payload, IP_HLEN + 8);\r
+\r
+ /* calculate checksum */\r
+ idur->chksum = 0;\r
+ idur->chksum = inet_chksum(idur, q->len);\r
+ ICMP_STATS_INC(icmp.xmit);\r
+ /* increase number of messages attempted to send */\r
+ snmp_inc_icmpoutmsgs();\r
+ /* increase number of destination unreachable messages attempted to send */\r
+ snmp_inc_icmpoutdestunreachs();\r
+\r
+ ip_output(q, NULL, &(iphdr->src),\r
+ ICMP_TTL, 0, IP_PROTO_ICMP);\r
+ pbuf_free(q);\r
+}\r
+\r
+#if IP_FORWARD\r
+void\r
+icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t)\r
+{\r
+ struct pbuf *q;\r
+ struct ip_hdr *iphdr;\r
+ struct icmp_te_hdr *tehdr;\r
+\r
+ q = pbuf_alloc(PBUF_IP, 8 + IP_HLEN + 8, PBUF_RAM);\r
+\r
+ iphdr = p->payload;\r
+ LWIP_DEBUGF(ICMP_DEBUG, ("icmp_time_exceeded from "));\r
+ ip_addr_debug_print(ICMP_DEBUG, &(iphdr->src));\r
+ LWIP_DEBUGF(ICMP_DEBUG, (" to "));\r
+ ip_addr_debug_print(ICMP_DEBUG, &(iphdr->dest));\r
+ LWIP_DEBUGF(ICMP_DEBUG, ("\n"));\r
+\r
+ tehdr = q->payload;\r
+ ICMPH_TYPE_SET(tehdr, ICMP_TE);\r
+ ICMPH_CODE_SET(tehdr, t);\r
+\r
+ /* copy fields from original packet */\r
+ memcpy((char *)q->payload + 8, (char *)p->payload, IP_HLEN + 8);\r
+\r
+ /* calculate checksum */\r
+ tehdr->chksum = 0;\r
+ tehdr->chksum = inet_chksum(tehdr, q->len);\r
+ ICMP_STATS_INC(icmp.xmit);\r
+ /* increase number of messages attempted to send */\r
+ snmp_inc_icmpoutmsgs();\r
+ /* increase number of destination unreachable messages attempted to send */\r
+ snmp_inc_icmpouttimeexcds();\r
+ ip_output(q, NULL, &(iphdr->src),\r
+ ICMP_TTL, 0, IP_PROTO_ICMP);\r
+ pbuf_free(q);\r
+}\r
+\r
+#endif /* IP_FORWARD */\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/* @file
+ *
+ * This is the IP layer implementation for incoming and outgoing IP traffic.
+ *
+ * @see ip_frag.c
+ *
+ */
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+#include "lwip/opt.h"
+
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/ip.h"
+#include "lwip/ip_frag.h"
+#include "lwip/inet.h"
+#include "lwip/netif.h"
+#include "lwip/icmp.h"
+#include "lwip/raw.h"
+#include "lwip/udp.h"
+#include "lwip/tcp.h"
+
+#include "lwip/stats.h"
+
+#include "arch/perf.h"
+
+#include "lwip/snmp.h"
+#if LWIP_DHCP
+# include "lwip/dhcp.h"
+#endif /* LWIP_DHCP */
+
+
+/**
+ * Initializes the IP layer.
+ */
+
+void
+ip_init(void)
+{
+ /* no initializations as of yet */
+}
+
+/**
+ * Finds the appropriate network interface for a given IP address. It
+ * searches the list of network interfaces linearly. A match is found
+ * if the masked IP address of the network interface equals the masked
+ * IP address given to the function.
+ */
+
+struct netif *
+ip_route(struct ip_addr *dest)
+{
+ struct netif *netif;
+
+ /* iterate through netifs */
+ for(netif = netif_list; netif != NULL; netif = netif->next) {
+ /* network mask matches? */
+ if (ip_addr_netcmp(dest, &(netif->ip_addr), &(netif->netmask))) {
+ /* return netif on which to forward IP packet */
+ return netif;
+ }
+ }
+ /* no matching netif found, use default netif */
+ return netif_default;
+}
+#if IP_FORWARD
+
+/**
+ * Forwards an IP packet. It finds an appropriate route for the
+ * packet, decrements the TTL value of the packet, adjusts the
+ * checksum and outputs the packet on the appropriate interface.
+ */
+
+static struct netif *
+ip_forward(struct pbuf *p, struct ip_hdr *iphdr, struct netif *inp)
+{
+ struct netif *netif;
+
+ PERF_START;
+ /* Find network interface where to forward this IP packet to. */
+ netif = ip_route((struct ip_addr *)&(iphdr->dest));
+ if (netif == NULL) {
+ LWIP_DEBUGF(IP_DEBUG, ("ip_forward: no forwarding route for 0x%lx found\n",
+ iphdr->dest.addr));
+ snmp_inc_ipnoroutes();
+ return (struct netif *)NULL;
+ }
+ /* Do not forward packets onto the same network interface on which
+ * they arrived. */
+ if (netif == inp) {
+ LWIP_DEBUGF(IP_DEBUG, ("ip_forward: not bouncing packets back on incoming interface.\n"));
+ snmp_inc_ipnoroutes();
+ return (struct netif *)NULL;
+ }
+
+ /* decrement TTL */
+ IPH_TTL_SET(iphdr, IPH_TTL(iphdr) - 1);
+ /* send ICMP if TTL == 0 */
+ if (IPH_TTL(iphdr) == 0) {
+ /* Don't send ICMP messages in response to ICMP messages */
+ if (IPH_PROTO(iphdr) != IP_PROTO_ICMP) {
+ icmp_time_exceeded(p, ICMP_TE_TTL);
+ snmp_inc_icmpouttimeexcds();
+ }
+ return (struct netif *)NULL;
+ }
+
+ /* Incrementally update the IP checksum. */
+ if (IPH_CHKSUM(iphdr) >= htons(0xffff - 0x100)) {
+ IPH_CHKSUM_SET(iphdr, IPH_CHKSUM(iphdr) + htons(0x100) + 1);
+ } else {
+ IPH_CHKSUM_SET(iphdr, IPH_CHKSUM(iphdr) + htons(0x100));
+ }
+
+ LWIP_DEBUGF(IP_DEBUG, ("ip_forward: forwarding packet to 0x%lx\n",
+ iphdr->dest.addr));
+
+ IP_STATS_INC(ip.fw);
+ IP_STATS_INC(ip.xmit);
+ snmp_inc_ipforwdatagrams();
+
+ PERF_STOP("ip_forward");
+ /* transmit pbuf on chosen interface */
+ netif->output(netif, p, (struct ip_addr *)&(iphdr->dest));
+ return netif;
+}
+#endif /* IP_FORWARD */
+
+/**
+ * This function is called by the network interface device driver when
+ * an IP packet is received. The function does the basic checks of the
+ * IP header such as packet size being at least larger than the header
+ * size etc. If the packet was not destined for us, the packet is
+ * forwarded (using ip_forward). The IP checksum is always checked.
+ *
+ * Finally, the packet is sent to the upper layer protocol input function.
+ *
+ *
+ *
+ */
+
+err_t
+ip_input(struct pbuf *p, struct netif *inp) {
+ struct ip_hdr *iphdr;
+ struct netif *netif;
+ u16_t iphdrlen;
+
+ IP_STATS_INC(ip.recv);
+ snmp_inc_ipinreceives();
+
+ /* identify the IP header */
+ iphdr = p->payload;
+ if (IPH_V(iphdr) != 4) {
+ LWIP_DEBUGF(IP_DEBUG | 1, ("IP packet dropped due to bad version number %u\n", IPH_V(iphdr)));
+ ip_debug_print(p);
+ pbuf_free(p);
+ IP_STATS_INC(ip.err);
+ IP_STATS_INC(ip.drop);
+ snmp_inc_ipunknownprotos();
+ return ERR_OK;
+ }
+ /* obtain IP header length in number of 32-bit words */
+ iphdrlen = IPH_HL(iphdr);
+ /* calculate IP header length in bytes */
+ iphdrlen *= 4;
+
+ /* header length exceeds first pbuf length? */
+ if (iphdrlen > p->len) {
+ LWIP_DEBUGF(IP_DEBUG | 2, ("IP header (len %u) does not fit in first pbuf (len %u), IP packet droppped.\n",
+ iphdrlen, p->len));
+ /* free (drop) packet pbufs */
+ pbuf_free(p);
+ IP_STATS_INC(ip.lenerr);
+ IP_STATS_INC(ip.drop);
+ snmp_inc_ipindiscards();
+ return ERR_OK;
+ }
+
+ /* verify checksum */
+#if CHECKSUM_CHECK_IP
+ if (inet_chksum(iphdr, iphdrlen) != 0) {
+
+ LWIP_DEBUGF(IP_DEBUG | 2, ("Checksum (0x%x) failed, IP packet dropped.\n", inet_chksum(iphdr, iphdrlen)));
+ ip_debug_print(p);
+ pbuf_free(p);
+ IP_STATS_INC(ip.chkerr);
+ IP_STATS_INC(ip.drop);
+ snmp_inc_ipindiscards();
+ return ERR_OK;
+ }
+#endif
+
+ /* Trim pbuf. This should have been done at the netif layer,
+ * but we'll do it anyway just to be sure that its done. */
+ pbuf_realloc(p, ntohs(IPH_LEN(iphdr)));
+
+ /* match packet against an interface, i.e. is this packet for us? */
+ for (netif = netif_list; netif != NULL; netif = netif->next) {
+
+ LWIP_DEBUGF(IP_DEBUG, ("ip_input: iphdr->dest 0x%lx netif->ip_addr 0x%lx (0x%lx, 0x%lx, 0x%lx)\n",
+ iphdr->dest.addr, netif->ip_addr.addr,
+ iphdr->dest.addr & netif->netmask.addr,
+ netif->ip_addr.addr & netif->netmask.addr,
+ iphdr->dest.addr & ~(netif->netmask.addr)));
+
+ /* interface is up and configured? */
+ if ((netif_is_up(netif)) && (!ip_addr_isany(&(netif->ip_addr))))
+ {
+ /* unicast to this interface address? */
+ if (ip_addr_cmp(&(iphdr->dest), &(netif->ip_addr)) ||
+ /* or broadcast on this interface network address? */
+ ip_addr_isbroadcast(&(iphdr->dest), netif)) {
+ LWIP_DEBUGF(IP_DEBUG, ("ip_input: packet accepted on interface %c%c\n",
+ netif->name[0], netif->name[1]));
+ /* break out of for loop */
+ break;
+ }
+ }
+ }
+#if LWIP_DHCP
+ /* Pass DHCP messages regardless of destination address. DHCP traffic is addressed
+ * using link layer addressing (such as Ethernet MAC) so we must not filter on IP.
+ * According to RFC 1542 section 3.1.1, referred by RFC 2131).
+ */
+ if (netif == NULL) {
+ /* remote port is DHCP server? */
+ if (IPH_PROTO(iphdr) == IP_PROTO_UDP) {
+ LWIP_DEBUGF(IP_DEBUG | DBG_TRACE | 1, ("ip_input: UDP packet to DHCP client port %u\n",
+ ntohs(((struct udp_hdr *)((u8_t *)iphdr + iphdrlen))->dest)));
+ if (ntohs(((struct udp_hdr *)((u8_t *)iphdr + iphdrlen))->dest) == DHCP_CLIENT_PORT) {
+ LWIP_DEBUGF(IP_DEBUG | DBG_TRACE | 1, ("ip_input: DHCP packet accepted.\n"));
+ netif = inp;
+ }
+ }
+ }
+#endif /* LWIP_DHCP */
+ /* packet not for us? */
+ if (netif == NULL) {
+ /* packet not for us, route or discard */
+ LWIP_DEBUGF(IP_DEBUG | DBG_TRACE | 1, ("ip_input: packet not for us.\n"));
+#if IP_FORWARD
+ /* non-broadcast packet? */
+ if (!ip_addr_isbroadcast(&(iphdr->dest), inp)) {
+ /* try to forward IP packet on (other) interfaces */
+ ip_forward(p, iphdr, inp);
+ }
+ else
+#endif /* IP_FORWARD */
+ {
+ snmp_inc_ipindiscards();
+ }
+ pbuf_free(p);
+ return ERR_OK;
+ }
+ /* packet consists of multiple fragments? */
+ if ((IPH_OFFSET(iphdr) & htons(IP_OFFMASK | IP_MF)) != 0) {
+#if IP_REASSEMBLY /* packet fragment reassembly code present? */
+ LWIP_DEBUGF(IP_DEBUG, ("IP packet is a fragment (id=0x%04x tot_len=%u len=%u MF=%u offset=%u), calling ip_reass()\n",
+ ntohs(IPH_ID(iphdr)), p->tot_len, ntohs(IPH_LEN(iphdr)), !!(IPH_OFFSET(iphdr) & htons(IP_MF)), (ntohs(IPH_OFFSET(iphdr)) & IP_OFFMASK)*8));
+ /* reassemble the packet*/
+ p = ip_reass(p);
+ /* packet not fully reassembled yet? */
+ if (p == NULL) {
+ return ERR_OK;
+ }
+ iphdr = p->payload;
+#else /* IP_REASSEMBLY == 0, no packet fragment reassembly code present */
+ pbuf_free(p);
+ LWIP_DEBUGF(IP_DEBUG | 2, ("IP packet dropped since it was fragmented (0x%x) (while IP_REASSEMBLY == 0).\n",
+ ntohs(IPH_OFFSET(iphdr))));
+ IP_STATS_INC(ip.opterr);
+ IP_STATS_INC(ip.drop);
+ snmp_inc_ipunknownprotos();
+ return ERR_OK;
+#endif /* IP_REASSEMBLY */
+ }
+
+#if IP_OPTIONS == 0 /* no support for IP options in the IP header? */
+ if (iphdrlen > IP_HLEN) {
+ LWIP_DEBUGF(IP_DEBUG | 2, ("IP packet dropped since there were IP options (while IP_OPTIONS == 0).\n"));
+ pbuf_free(p);
+ IP_STATS_INC(ip.opterr);
+ IP_STATS_INC(ip.drop);
+ snmp_inc_ipunknownprotos();
+ return ERR_OK;
+ }
+#endif /* IP_OPTIONS == 0 */
+
+ /* send to upper layers */
+ LWIP_DEBUGF(IP_DEBUG, ("ip_input: \n"));
+ ip_debug_print(p);
+ LWIP_DEBUGF(IP_DEBUG, ("ip_input: p->len %d p->tot_len %d\n", p->len, p->tot_len));
+
+#if LWIP_RAW
+ /* raw input did not eat the packet? */
+ if (raw_input(p, inp) == 0) {
+#endif /* LWIP_RAW */
+
+ switch (IPH_PROTO(iphdr)) {
+#if LWIP_UDP
+ case IP_PROTO_UDP:
+ case IP_PROTO_UDPLITE:
+ snmp_inc_ipindelivers();
+ udp_input(p, inp);
+ break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+ case IP_PROTO_TCP:
+ snmp_inc_ipindelivers();
+ tcp_input(p, inp);
+ break;
+#endif /* LWIP_TCP */
+ case IP_PROTO_ICMP:
+ snmp_inc_ipindelivers();
+ icmp_input(p, inp);
+ break;
+ default:
+ /* send ICMP destination protocol unreachable unless is was a broadcast */
+ if (!ip_addr_isbroadcast(&(iphdr->dest), inp) &&
+ !ip_addr_ismulticast(&(iphdr->dest))) {
+ p->payload = iphdr;
+ icmp_dest_unreach(p, ICMP_DUR_PROTO);
+ }
+ pbuf_free(p);
+
+ LWIP_DEBUGF(IP_DEBUG | 2, ("Unsupported transport protocol %d\n", IPH_PROTO(iphdr)));
+
+ IP_STATS_INC(ip.proterr);
+ IP_STATS_INC(ip.drop);
+ snmp_inc_ipunknownprotos();
+ }
+#if LWIP_RAW
+ } /* LWIP_RAW */
+#endif
+ return ERR_OK;
+}
+
+/**
+ * Sends an IP packet on a network interface. This function constructs
+ * the IP header and calculates the IP header checksum. If the source
+ * IP address is NULL, the IP address of the outgoing network
+ * interface is filled in as source address.
+ */
+
+err_t
+ip_output_if(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+ u8_t ttl, u8_t tos,
+ u8_t proto, struct netif *netif)
+{
+ struct ip_hdr *iphdr;
+ u16_t ip_id = 0;
+
+ snmp_inc_ipoutrequests();
+
+ if (dest != IP_HDRINCL) {
+ if (pbuf_header(p, IP_HLEN)) {
+ LWIP_DEBUGF(IP_DEBUG | 2, ("ip_output: not enough room for IP header in pbuf\n"));
+
+ IP_STATS_INC(ip.err);
+ snmp_inc_ipoutdiscards();
+ return ERR_BUF;
+ }
+
+ iphdr = p->payload;
+
+ IPH_TTL_SET(iphdr, ttl);
+ IPH_PROTO_SET(iphdr, proto);
+
+ ip_addr_set(&(iphdr->dest), dest);
+
+ IPH_VHLTOS_SET(iphdr, 4, IP_HLEN / 4, tos);
+ IPH_LEN_SET(iphdr, htons(p->tot_len));
+ IPH_OFFSET_SET(iphdr, htons(IP_DF));
+ IPH_ID_SET(iphdr, htons(ip_id));
+ ++ip_id;
+
+ if (ip_addr_isany(src)) {
+ ip_addr_set(&(iphdr->src), &(netif->ip_addr));
+ } else {
+ ip_addr_set(&(iphdr->src), src);
+ }
+
+ IPH_CHKSUM_SET(iphdr, 0);
+#if CHECKSUM_GEN_IP
+ IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, IP_HLEN));
+#endif
+ } else {
+ iphdr = p->payload;
+ dest = &(iphdr->dest);
+ }
+
+#if IP_FRAG
+ /* don't fragment if interface has mtu set to 0 [loopif] */
+ if (netif->mtu && (p->tot_len > netif->mtu))
+ return ip_frag(p,netif,dest);
+#endif
+
+ IP_STATS_INC(ip.xmit);
+
+ LWIP_DEBUGF(IP_DEBUG, ("ip_output_if: %c%c%u\n", netif->name[0], netif->name[1], netif->num));
+ ip_debug_print(p);
+
+ LWIP_DEBUGF(IP_DEBUG, ("netif->output()"));
+
+ return netif->output(netif, p, dest);
+}
+
+/**
+ * Simple interface to ip_output_if. It finds the outgoing network
+ * interface and calls upon ip_output_if to do the actual work.
+ */
+
+err_t
+ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+ u8_t ttl, u8_t tos, u8_t proto)
+{
+ struct netif *netif;
+
+ if ((netif = ip_route(dest)) == NULL) {
+ LWIP_DEBUGF(IP_DEBUG | 2, ("ip_output: No route to 0x%lx\n", dest->addr));
+
+ IP_STATS_INC(ip.rterr);
+ snmp_inc_ipoutdiscards();
+ return ERR_RTE;
+ }
+
+ return ip_output_if(p, src, dest, ttl, tos, proto, netif);
+}
+
+#if IP_DEBUG
+void
+ip_debug_print(struct pbuf *p)
+{
+ struct ip_hdr *iphdr = p->payload;
+ u8_t *payload;
+
+ payload = (u8_t *)iphdr + IP_HLEN;
+
+ LWIP_DEBUGF(IP_DEBUG, ("IP header:\n"));
+ LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+ LWIP_DEBUGF(IP_DEBUG, ("|%2d |%2d | 0x%02x | %5u | (v, hl, tos, len)\n",
+ IPH_V(iphdr),
+ IPH_HL(iphdr),
+ IPH_TOS(iphdr),
+ ntohs(IPH_LEN(iphdr))));
+ LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+ LWIP_DEBUGF(IP_DEBUG, ("| %5u |%u%u%u| %4u | (id, flags, offset)\n",
+ ntohs(IPH_ID(iphdr)),
+ ntohs(IPH_OFFSET(iphdr)) >> 15 & 1,
+ ntohs(IPH_OFFSET(iphdr)) >> 14 & 1,
+ ntohs(IPH_OFFSET(iphdr)) >> 13 & 1,
+ ntohs(IPH_OFFSET(iphdr)) & IP_OFFMASK));
+ LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+ LWIP_DEBUGF(IP_DEBUG, ("| %3u | %3u | 0x%04x | (ttl, proto, chksum)\n",
+ IPH_TTL(iphdr),
+ IPH_PROTO(iphdr),
+ ntohs(IPH_CHKSUM(iphdr))));
+ LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+ LWIP_DEBUGF(IP_DEBUG, ("| %3u | %3u | %3u | %3u | (src)\n",
+ ip4_addr1(&iphdr->src),
+ ip4_addr2(&iphdr->src),
+ ip4_addr3(&iphdr->src),
+ ip4_addr4(&iphdr->src)));
+ LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+ LWIP_DEBUGF(IP_DEBUG, ("| %3u | %3u | %3u | %3u | (dest)\n",
+ ip4_addr1(&iphdr->dest),
+ ip4_addr2(&iphdr->dest),
+ ip4_addr3(&iphdr->dest),
+ ip4_addr4(&iphdr->dest)));
+ LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+}
+#endif /* IP_DEBUG */
+
+
+
+
+
+
--- /dev/null
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+#include "lwip/ip_addr.h"
+#include "lwip/inet.h"
+#include "lwip/netif.h"
+
+/* used by IP_ADDR_ANY and IP_ADDR_BROADCAST in ip_addr.h */
+const struct ip_addr ip_addr_any = { 0x00000000UL };
+const struct ip_addr ip_addr_broadcast = { 0xffffffffUL };
+
+/* Determine if an address is a broadcast address on a network interface
+ *
+ * @param addr address to be checked
+ * @param netif the network interface against which the address is checked
+ * @return returns non-zero if the address is a broadcast address
+ *
+ */
+
+u8_t ip_addr_isbroadcast(struct ip_addr *addr, struct netif *netif)
+{
+ /* all ones (broadcast) or all zeroes (old skool broadcast) */
+ if ((addr->addr == ip_addr_broadcast.addr) ||
+ (addr->addr == ip_addr_any.addr))
+ return 1;
+ /* no broadcast support on this network interface? */
+ else if ((netif->flags & NETIF_FLAG_BROADCAST) == 0)
+ /* the given address cannot be a broadcast address
+ * nor can we check against any broadcast addresses */
+ return 0;
+ /* address matches network interface address exactly? => no broadcast */
+ else if (addr->addr == netif->ip_addr.addr)
+ return 0;
+ /* on the same (sub) network... */
+ else if (ip_addr_netcmp(addr, &(netif->ip_addr), &(netif->netmask))
+ /* ...and host identifier bits are all ones? =>... */
+ && ((addr->addr & ~netif->netmask.addr) ==
+ (ip_addr_broadcast.addr & ~netif->netmask.addr)))
+ /* => network broadcast address */
+ return 1;
+ else
+ return 0;
+}
--- /dev/null
+/* @file\r
+ * \r
+ * This is the IP packet segmentation and reassembly implementation.\r
+ *\r
+ */\r
+\r
+/*\r
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.\r
+ * All rights reserved. \r
+ * \r
+ * Redistribution and use in source and binary forms, with or without modification, \r
+ * are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. The name of the author may not be used to endorse or promote products\r
+ * derived from this software without specific prior written permission. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED \r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT \r
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, \r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT \r
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS \r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN \r
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING \r
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY \r
+ * OF SUCH DAMAGE.\r
+ *\r
+ * This file is part of the lwIP TCP/IP stack.\r
+ * \r
+ * Author: Jani Monoses <jani@iv.ro> \r
+ * original reassembly code by Adam Dunkels <adam@sics.se>\r
+ * \r
+ */\r
+\r
+#include "lwip/opt.h"\r
+#include "lwip/sys.h"\r
+#include "lwip/ip.h"\r
+#include "lwip/ip_frag.h"\r
+#include "lwip/netif.h"\r
+\r
+#include "lwip/stats.h"\r
+\r
+#include <string.h>\r
+\r
+/*\r
+ * Copy len bytes from offset in pbuf to buffer \r
+ *\r
+ * helper used by both ip_reass and ip_frag\r
+ */\r
+static struct pbuf *\r
+copy_from_pbuf(struct pbuf *p, u16_t * offset,\r
+ u8_t * buffer, u16_t len)\r
+{\r
+ u16_t l;\r
+\r
+ p->payload = (u8_t *)p->payload + *offset;\r
+ p->len -= *offset;\r
+ while (len) {\r
+ l = len < p->len ? len : p->len;\r
+ memcpy(buffer, p->payload, l);\r
+ buffer += l;\r
+ len -= l;\r
+ if (len)\r
+ p = p->next;\r
+ else\r
+ *offset = l;\r
+ }\r
+ return p;\r
+}\r
+\r
+#define IP_REASS_BUFSIZE 5760\r
+#define IP_REASS_MAXAGE 30\r
+#define IP_REASS_TMO 1000\r
+\r
+static u8_t ip_reassbuf[IP_HLEN + IP_REASS_BUFSIZE];\r
+static u8_t ip_reassbitmap[IP_REASS_BUFSIZE / (8 * 8)];\r
+static const u8_t bitmap_bits[8] = { 0xff, 0x7f, 0x3f, 0x1f,\r
+ 0x0f, 0x07, 0x03, 0x01\r
+};\r
+static u16_t ip_reasslen;\r
+static u8_t ip_reassflags;\r
+#define IP_REASS_FLAG_LASTFRAG 0x01\r
+\r
+static u8_t ip_reasstmr;\r
+\r
+/* Reassembly timer */ \r
+static void \r
+ip_reass_timer(void *arg)\r
+{\r
+ (void)arg;\r
+ if (ip_reasstmr > 1) {\r
+ ip_reasstmr--;\r
+ sys_timeout(IP_REASS_TMO, ip_reass_timer, NULL);\r
+ } else if (ip_reasstmr == 1)\r
+ ip_reasstmr = 0;\r
+}\r
+\r
+struct pbuf *\r
+ip_reass(struct pbuf *p)\r
+{\r
+ struct pbuf *q;\r
+ struct ip_hdr *fraghdr, *iphdr;\r
+ u16_t offset, len;\r
+ u16_t i;\r
+\r
+ IPFRAG_STATS_INC(ip_frag.recv);\r
+\r
+ iphdr = (struct ip_hdr *) ip_reassbuf;\r
+ fraghdr = (struct ip_hdr *) p->payload;\r
+ /* If ip_reasstmr is zero, no packet is present in the buffer, so we\r
+ write the IP header of the fragment into the reassembly\r
+ buffer. The timer is updated with the maximum age. */\r
+ if (ip_reasstmr == 0) {\r
+ LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass: new packet\n"));\r
+ memcpy(iphdr, fraghdr, IP_HLEN);\r
+ ip_reasstmr = IP_REASS_MAXAGE;\r
+ sys_timeout(IP_REASS_TMO, ip_reass_timer, NULL);\r
+ ip_reassflags = 0;\r
+ /* Clear the bitmap. */\r
+ memset(ip_reassbitmap, 0, sizeof(ip_reassbitmap));\r
+ }\r
+\r
+ /* Check if the incoming fragment matches the one currently present\r
+ in the reasembly buffer. If so, we proceed with copying the\r
+ fragment into the buffer. */\r
+ if (ip_addr_cmp(&iphdr->src, &fraghdr->src) &&\r
+ ip_addr_cmp(&iphdr->dest, &fraghdr->dest) &&\r
+ IPH_ID(iphdr) == IPH_ID(fraghdr)) {\r
+ LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass: matching old packet\n"));\r
+ IPFRAG_STATS_INC(ip_frag.cachehit);\r
+ /* Find out the offset in the reassembly buffer where we should\r
+ copy the fragment. */\r
+ len = ntohs(IPH_LEN(fraghdr)) - IPH_HL(fraghdr) * 4;\r
+ offset = (ntohs(IPH_OFFSET(fraghdr)) & IP_OFFMASK) * 8;\r
+\r
+ /* If the offset or the offset + fragment length overflows the\r
+ reassembly buffer, we discard the entire packet. */\r
+ if (offset > IP_REASS_BUFSIZE || offset + len > IP_REASS_BUFSIZE) {\r
+ LWIP_DEBUGF(IP_REASS_DEBUG,\r
+ ("ip_reass: fragment outside of buffer (%d:%d/%d).\n", offset,\r
+ offset + len, IP_REASS_BUFSIZE));\r
+ sys_untimeout(ip_reass_timer, NULL);\r
+ ip_reasstmr = 0;\r
+ goto nullreturn;\r
+ }\r
+\r
+ /* Copy the fragment into the reassembly buffer, at the right\r
+ offset. */\r
+ LWIP_DEBUGF(IP_REASS_DEBUG,\r
+ ("ip_reass: copying with offset %d into %d:%d\n", offset,\r
+ IP_HLEN + offset, IP_HLEN + offset + len));\r
+ i = IPH_HL(fraghdr) * 4;\r
+ copy_from_pbuf(p, &i, &ip_reassbuf[IP_HLEN + offset], len);\r
+\r
+ /* Update the bitmap. */\r
+ if (offset / (8 * 8) == (offset + len) / (8 * 8)) {\r
+ LWIP_DEBUGF(IP_REASS_DEBUG,\r
+ ("ip_reass: updating single byte in bitmap.\n"));\r
+ /* If the two endpoints are in the same byte, we only update\r
+ that byte. */\r
+ ip_reassbitmap[offset / (8 * 8)] |=\r
+ bitmap_bits[(offset / 8) & 7] &\r
+ ~bitmap_bits[((offset + len) / 8) & 7];\r
+ } else {\r
+ /* If the two endpoints are in different bytes, we update the\r
+ bytes in the endpoints and fill the stuff inbetween with\r
+ 0xff. */\r
+ ip_reassbitmap[offset / (8 * 8)] |= bitmap_bits[(offset / 8) & 7];\r
+ LWIP_DEBUGF(IP_REASS_DEBUG,\r
+ ("ip_reass: updating many bytes in bitmap (%d:%d).\n",\r
+ 1 + offset / (8 * 8), (offset + len) / (8 * 8)));\r
+ for (i = 1 + offset / (8 * 8); i < (offset + len) / (8 * 8); ++i) {\r
+ ip_reassbitmap[i] = 0xff;\r
+ }\r
+ ip_reassbitmap[(offset + len) / (8 * 8)] |=\r
+ ~bitmap_bits[((offset + len) / 8) & 7];\r
+ }\r
+\r
+ /* If this fragment has the More Fragments flag set to zero, we\r
+ know that this is the last fragment, so we can calculate the\r
+ size of the entire packet. We also set the\r
+ IP_REASS_FLAG_LASTFRAG flag to indicate that we have received\r
+ the final fragment. */\r
+\r
+ if ((ntohs(IPH_OFFSET(fraghdr)) & IP_MF) == 0) {\r
+ ip_reassflags |= IP_REASS_FLAG_LASTFRAG;\r
+ ip_reasslen = offset + len;\r
+ LWIP_DEBUGF(IP_REASS_DEBUG,\r
+ ("ip_reass: last fragment seen, total len %d\n",\r
+ ip_reasslen));\r
+ }\r
+\r
+ /* Finally, we check if we have a full packet in the buffer. We do\r
+ this by checking if we have the last fragment and if all bits\r
+ in the bitmap are set. */\r
+ if (ip_reassflags & IP_REASS_FLAG_LASTFRAG) {\r
+ /* Check all bytes up to and including all but the last byte in\r
+ the bitmap. */\r
+ for (i = 0; i < ip_reasslen / (8 * 8) - 1; ++i) {\r
+ if (ip_reassbitmap[i] != 0xff) {\r
+ LWIP_DEBUGF(IP_REASS_DEBUG,\r
+ ("ip_reass: last fragment seen, bitmap %d/%d failed (%x)\n",\r
+ i, ip_reasslen / (8 * 8) - 1, ip_reassbitmap[i]));\r
+ goto nullreturn;\r
+ }\r
+ }\r
+ /* Check the last byte in the bitmap. It should contain just the\r
+ right amount of bits. */\r
+ if (ip_reassbitmap[ip_reasslen / (8 * 8)] !=\r
+ (u8_t) ~ bitmap_bits[ip_reasslen / 8 & 7]) {\r
+ LWIP_DEBUGF(IP_REASS_DEBUG,\r
+ ("ip_reass: last fragment seen, bitmap %d didn't contain %x (%x)\n",\r
+ ip_reasslen / (8 * 8), ~bitmap_bits[ip_reasslen / 8 & 7],\r
+ ip_reassbitmap[ip_reasslen / (8 * 8)]));\r
+ goto nullreturn;\r
+ }\r
+\r
+ /* Pretend to be a "normal" (i.e., not fragmented) IP packet\r
+ from now on. */\r
+ ip_reasslen += IP_HLEN;\r
+\r
+ IPH_LEN_SET(iphdr, htons(ip_reasslen));\r
+ IPH_OFFSET_SET(iphdr, 0);\r
+ IPH_CHKSUM_SET(iphdr, 0);\r
+ IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, IP_HLEN));\r
+\r
+ /* If we have come this far, we have a full packet in the\r
+ buffer, so we allocate a pbuf and copy the packet into it. We\r
+ also reset the timer. */\r
+ sys_untimeout(ip_reass_timer, NULL);\r
+ ip_reasstmr = 0;\r
+ pbuf_free(p);\r
+ p = pbuf_alloc(PBUF_LINK, ip_reasslen, PBUF_POOL);\r
+ if (p != NULL) {\r
+ i = 0;\r
+ for (q = p; q != NULL; q = q->next) {\r
+ /* Copy enough bytes to fill this pbuf in the chain. The\r
+ available data in the pbuf is given by the q->len\r
+ variable. */\r
+ LWIP_DEBUGF(IP_REASS_DEBUG,\r
+ ("ip_reass: memcpy from %p (%d) to %p, %d bytes\n",\r
+ (void *)&ip_reassbuf[i], i, q->payload,\r
+ q->len > ip_reasslen - i ? ip_reasslen - i : q->len));\r
+ memcpy(q->payload, &ip_reassbuf[i],\r
+ q->len > ip_reasslen - i ? ip_reasslen - i : q->len);\r
+ i += q->len;\r
+ }\r
+ IPFRAG_STATS_INC(ip_frag.fw);\r
+ } else {\r
+ IPFRAG_STATS_INC(ip_frag.memerr);\r
+ }\r
+ LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass: p %p\n", (void*)p));\r
+ return p;\r
+ }\r
+ }\r
+\r
+nullreturn:\r
+ IPFRAG_STATS_INC(ip_frag.drop);\r
+ pbuf_free(p);\r
+ return NULL;\r
+}\r
+\r
+#define MAX_MTU 1500\r
+static u8_t buf[MEM_ALIGN_SIZE(MAX_MTU)];\r
+\r
+/**\r
+ * Fragment an IP packet if too large\r
+ *\r
+ * Chop the packet in mtu sized chunks and send them in order\r
+ * by using a fixed size static memory buffer (PBUF_ROM)\r
+ */\r
+err_t \r
+ip_frag(struct pbuf *p, struct netif *netif, struct ip_addr *dest)\r
+{\r
+ struct pbuf *rambuf;\r
+ struct pbuf *header;\r
+ struct ip_hdr *iphdr;\r
+ u16_t nfb = 0;\r
+ u16_t left, cop;\r
+ u16_t mtu = netif->mtu;\r
+ u16_t ofo, omf;\r
+ u16_t last;\r
+ u16_t poff = IP_HLEN;\r
+ u16_t tmp;\r
+\r
+ /* Get a RAM based MTU sized pbuf */\r
+ rambuf = pbuf_alloc(PBUF_LINK, 0, PBUF_REF);\r
+ rambuf->tot_len = rambuf->len = mtu;\r
+ rambuf->payload = MEM_ALIGN((void *)buf);\r
+\r
+ /* Copy the IP header in it */\r
+ iphdr = rambuf->payload;\r
+ memcpy(iphdr, p->payload, IP_HLEN);\r
+\r
+ /* Save original offset */\r
+ tmp = ntohs(IPH_OFFSET(iphdr));\r
+ ofo = tmp & IP_OFFMASK;\r
+ omf = tmp & IP_MF;\r
+\r
+ left = p->tot_len - IP_HLEN;\r
+\r
+ while (left) {\r
+ last = (left <= mtu - IP_HLEN);\r
+\r
+ /* Set new offset and MF flag */\r
+ ofo += nfb;\r
+ tmp = omf | (IP_OFFMASK & (ofo));\r
+ if (!last)\r
+ tmp = tmp | IP_MF;\r
+ IPH_OFFSET_SET(iphdr, htons(tmp));\r
+\r
+ /* Fill this fragment */\r
+ nfb = (mtu - IP_HLEN) / 8;\r
+ cop = last ? left : nfb * 8;\r
+\r
+ p = copy_from_pbuf(p, &poff, (u8_t *) iphdr + IP_HLEN, cop);\r
+\r
+ /* Correct header */\r
+ IPH_LEN_SET(iphdr, htons(cop + IP_HLEN));\r
+ IPH_CHKSUM_SET(iphdr, 0);\r
+ IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, IP_HLEN));\r
+\r
+ if (last)\r
+ pbuf_realloc(rambuf, left + IP_HLEN);\r
+ /* This part is ugly: we alloc a RAM based pbuf for \r
+ * the link level header for each chunk and then \r
+ * free it.A PBUF_ROM style pbuf for which pbuf_header\r
+ * worked would make things simpler.\r
+ */\r
+ header = pbuf_alloc(PBUF_LINK, 0, PBUF_RAM);\r
+ pbuf_chain(header, rambuf);\r
+ netif->output(netif, header, dest);\r
+ IPFRAG_STATS_INC(ip_frag.xmit);\r
+ pbuf_free(header);\r
+\r
+ left -= cop;\r
+ }\r
+ pbuf_free(rambuf);\r
+ return ERR_OK;\r
+}\r
--- /dev/null
+IPv6 support in lwIP is very experimental.
--- /dev/null
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+/* Some ICMP messages should be passed to the transport protocols. This
+ is not implemented. */
+
+#include "lwip/opt.h"
+
+#include "lwip/icmp.h"
+#include "lwip/inet.h"
+#include "lwip/ip.h"
+#include "lwip/def.h"
+
+#include "lwip/stats.h"
+
+
+void
+icmp_input(struct pbuf *p, struct netif *inp)
+{
+ unsigned char type;
+ struct icmp_echo_hdr *iecho;
+ struct ip_hdr *iphdr;
+ struct ip_addr tmpaddr;
+
+#ifdef ICMP_STATS
+ ++lwip_stats.icmp.recv;
+#endif /* ICMP_STATS */
+
+ /* TODO: check length before accessing payload! */
+
+ type = ((char *)p->payload)[0];
+
+ switch (type) {
+ case ICMP6_ECHO:
+ LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ping\n"));
+
+ if (p->tot_len < sizeof(struct icmp_echo_hdr)) {
+ LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: bad ICMP echo received\n"));
+
+ pbuf_free(p);
+#ifdef ICMP_STATS
+ ++lwip_stats.icmp.lenerr;
+#endif /* ICMP_STATS */
+
+ return;
+ }
+ iecho = p->payload;
+ iphdr = (struct ip_hdr *)((char *)p->payload - IP_HLEN);
+ if (inet_chksum_pbuf(p) != 0) {
+ LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: checksum failed for received ICMP echo (%x)\n", inet_chksum_pseudo(p, &(iphdr->src), &(iphdr->dest), IP_PROTO_ICMP, p->tot_len)));
+
+#ifdef ICMP_STATS
+ ++lwip_stats.icmp.chkerr;
+#endif /* ICMP_STATS */
+ /* return;*/
+ }
+ LWIP_DEBUGF(ICMP_DEBUG, ("icmp: p->len %d p->tot_len %d\n", p->len, p->tot_len));
+ ip_addr_set(&tmpaddr, &(iphdr->src));
+ ip_addr_set(&(iphdr->src), &(iphdr->dest));
+ ip_addr_set(&(iphdr->dest), &tmpaddr);
+ iecho->type = ICMP6_ER;
+ /* adjust the checksum */
+ if (iecho->chksum >= htons(0xffff - (ICMP6_ECHO << 8))) {
+ iecho->chksum += htons(ICMP6_ECHO << 8) + 1;
+ } else {
+ iecho->chksum += htons(ICMP6_ECHO << 8);
+ }
+ LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: checksum failed for received ICMP echo (%x)\n", inet_chksum_pseudo(p, &(iphdr->src), &(iphdr->dest), IP_PROTO_ICMP, p->tot_len)));
+#ifdef ICMP_STATS
+ ++lwip_stats.icmp.xmit;
+#endif /* ICMP_STATS */
+
+ /* LWIP_DEBUGF("icmp: p->len %u p->tot_len %u\n", p->len, p->tot_len);*/
+ ip_output_if (p, &(iphdr->src), IP_HDRINCL,
+ iphdr->hoplim, IP_PROTO_ICMP, inp);
+ break;
+ default:
+ LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ICMP type %d not supported.\n", (int)type));
+#ifdef ICMP_STATS
+ ++lwip_stats.icmp.proterr;
+ ++lwip_stats.icmp.drop;
+#endif /* ICMP_STATS */
+ }
+
+ pbuf_free(p);
+}
+
+void
+icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t)
+{
+ struct pbuf *q;
+ struct ip_hdr *iphdr;
+ struct icmp_dur_hdr *idur;
+
+ q = pbuf_alloc(PBUF_IP, 8 + IP_HLEN + 8, PBUF_RAM);
+ /* ICMP header + IP header + 8 bytes of data */
+
+ iphdr = p->payload;
+
+ idur = q->payload;
+ idur->type = (char)ICMP6_DUR;
+ idur->icode = (char)t;
+
+ memcpy((char *)q->payload + 8, p->payload, IP_HLEN + 8);
+
+ /* calculate checksum */
+ idur->chksum = 0;
+ idur->chksum = inet_chksum(idur, q->len);
+#ifdef ICMP_STATS
+ ++lwip_stats.icmp.xmit;
+#endif /* ICMP_STATS */
+
+ ip_output(q, NULL,
+ (struct ip_addr *)&(iphdr->src), ICMP_TTL, IP_PROTO_ICMP);
+ pbuf_free(q);
+}
+
+void
+icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t)
+{
+ struct pbuf *q;
+ struct ip_hdr *iphdr;
+ struct icmp_te_hdr *tehdr;
+
+ LWIP_DEBUGF(ICMP_DEBUG, ("icmp_time_exceeded\n"));
+
+ q = pbuf_alloc(PBUF_IP, 8 + IP_HLEN + 8, PBUF_RAM);
+
+ iphdr = p->payload;
+
+ tehdr = q->payload;
+ tehdr->type = (char)ICMP6_TE;
+ tehdr->icode = (char)t;
+
+ /* copy fields from original packet */
+ memcpy((char *)q->payload + 8, (char *)p->payload, IP_HLEN + 8);
+
+ /* calculate checksum */
+ tehdr->chksum = 0;
+ tehdr->chksum = inet_chksum(tehdr, q->len);
+#ifdef ICMP_STATS
+ ++lwip_stats.icmp.xmit;
+#endif /* ICMP_STATS */
+ ip_output(q, NULL,
+ (struct ip_addr *)&(iphdr->src), ICMP_TTL, IP_PROTO_ICMP);
+ pbuf_free(q);
+}
+
+
+
+
+
+
+
+
--- /dev/null
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+
+
+/* ip.c
+ *
+ * This is the code for the IP layer for IPv6.
+ *
+ */
+
+
+#include "lwip/opt.h"
+
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/ip.h"
+#include "lwip/inet.h"
+#include "lwip/netif.h"
+#include "lwip/icmp.h"
+#include "lwip/udp.h"
+#include "lwip/tcp.h"
+
+#include "lwip/stats.h"
+
+#include "arch/perf.h"
+
+/* ip_init:
+ *
+ * Initializes the IP layer.
+ */
+
+void
+ip_init(void)
+{
+}
+
+/* ip_route:
+ *
+ * Finds the appropriate network interface for a given IP address. It searches the
+ * list of network interfaces linearly. A match is found if the masked IP address of
+ * the network interface equals the masked IP address given to the function.
+ */
+
+struct netif *
+ip_route(struct ip_addr *dest)
+{
+ struct netif *netif;
+
+ for(netif = netif_list; netif != NULL; netif = netif->next) {
+ if (ip_addr_netcmp(dest, &(netif->ip_addr), &(netif->netmask))) {
+ return netif;
+ }
+ }
+
+ return netif_default;
+}
+
+/* ip_forward:
+ *
+ * Forwards an IP packet. It finds an appropriate route for the packet, decrements
+ * the TTL value of the packet, adjusts the checksum and outputs the packet on the
+ * appropriate interface.
+ */
+
+static void
+ip_forward(struct pbuf *p, struct ip_hdr *iphdr)
+{
+ struct netif *netif;
+
+ PERF_START;
+
+ if ((netif = ip_route((struct ip_addr *)&(iphdr->dest))) == NULL) {
+
+ LWIP_DEBUGF(IP_DEBUG, ("ip_input: no forwarding route found for "));
+#if IP_DEBUG
+ ip_addr_debug_print(IP_DEBUG, &(iphdr->dest));
+#endif /* IP_DEBUG */
+ LWIP_DEBUGF(IP_DEBUG, ("\n"));
+ pbuf_free(p);
+ return;
+ }
+ /* Decrement TTL and send ICMP if ttl == 0. */
+ if (--iphdr->hoplim == 0) {
+ /* Don't send ICMP messages in response to ICMP messages */
+ if (iphdr->nexthdr != IP_PROTO_ICMP) {
+ icmp_time_exceeded(p, ICMP_TE_TTL);
+ }
+ pbuf_free(p);
+ return;
+ }
+
+ /* Incremental update of the IP checksum. */
+ /* if (iphdr->chksum >= htons(0xffff - 0x100)) {
+ iphdr->chksum += htons(0x100) + 1;
+ } else {
+ iphdr->chksum += htons(0x100);
+ }*/
+
+
+ LWIP_DEBUGF(IP_DEBUG, ("ip_forward: forwarding packet to "));
+#if IP_DEBUG
+ ip_addr_debug_print(IP_DEBUG, &(iphdr->dest));
+#endif /* IP_DEBUG */
+ LWIP_DEBUGF(IP_DEBUG, ("\n"));
+
+#ifdef IP_STATS
+ ++lwip_stats.ip.fw;
+ ++lwip_stats.ip.xmit;
+#endif /* IP_STATS */
+
+ PERF_STOP("ip_forward");
+
+ netif->output(netif, p, (struct ip_addr *)&(iphdr->dest));
+}
+
+/* ip_input:
+ *
+ * This function is called by the network interface device driver when an IP packet is
+ * received. The function does the basic checks of the IP header such as packet size
+ * being at least larger than the header size etc. If the packet was not destined for
+ * us, the packet is forwarded (using ip_forward). The IP checksum is always checked.
+ *
+ * Finally, the packet is sent to the upper layer protocol input function.
+ */
+
+void
+ip_input(struct pbuf *p, struct netif *inp) {
+ struct ip_hdr *iphdr;
+ struct netif *netif;
+
+
+ PERF_START;
+
+#if IP_DEBUG
+ ip_debug_print(p);
+#endif /* IP_DEBUG */
+
+
+#ifdef IP_STATS
+ ++lwip_stats.ip.recv;
+#endif /* IP_STATS */
+
+ /* identify the IP header */
+ iphdr = p->payload;
+
+
+ if (iphdr->v != 6) {
+ LWIP_DEBUGF(IP_DEBUG, ("IP packet dropped due to bad version number\n"));
+#if IP_DEBUG
+ ip_debug_print(p);
+#endif /* IP_DEBUG */
+ pbuf_free(p);
+#ifdef IP_STATS
+ ++lwip_stats.ip.err;
+ ++lwip_stats.ip.drop;
+#endif /* IP_STATS */
+ return;
+ }
+
+ /* is this packet for us? */
+ for(netif = netif_list; netif != NULL; netif = netif->next) {
+#if IP_DEBUG
+ LWIP_DEBUGF(IP_DEBUG, ("ip_input: iphdr->dest "));
+ ip_addr_debug_print(IP_DEBUG, &(iphdr->dest));
+ LWIP_DEBUGF(IP_DEBUG, ("netif->ip_addr "));
+ ip_addr_debug_print(IP_DEBUG, &(netif->ip_addr));
+ LWIP_DEBUGF(IP_DEBUG, ("\n"));
+#endif /* IP_DEBUG */
+ if (ip_addr_cmp(&(iphdr->dest), &(netif->ip_addr))) {
+ break;
+ }
+ }
+
+
+ if (netif == NULL) {
+ /* packet not for us, route or discard */
+#ifdef IP_FORWARD
+ ip_forward(p, iphdr);
+#endif
+ pbuf_free(p);
+ return;
+ }
+
+ pbuf_realloc(p, IP_HLEN + ntohs(iphdr->len));
+
+ /* send to upper layers */
+#if IP_DEBUG
+ /* LWIP_DEBUGF("ip_input: \n");
+ ip_debug_print(p);
+ LWIP_DEBUGF("ip_input: p->len %u p->tot_len %u\n", p->len, p->tot_len);*/
+#endif /* IP_DEBUG */
+
+
+ pbuf_header(p, -IP_HLEN);
+
+ switch (iphdr->nexthdr) {
+ case IP_PROTO_UDP:
+ udp_input(p);
+ break;
+ case IP_PROTO_TCP:
+ tcp_input(p);
+ break;
+ case IP_PROTO_ICMP:
+ icmp_input(p, inp);
+ break;
+ default:
+ /* send ICMP destination protocol unreachable */
+ icmp_dest_unreach(p, ICMP_DUR_PROTO);
+ pbuf_free(p);
+ LWIP_DEBUGF(IP_DEBUG, ("Unsupported transport protocol %u\n",
+ iphdr->nexthdr));
+
+#ifdef IP_STATS
+ ++lwip_stats.ip.proterr;
+ ++lwip_stats.ip.drop;
+#endif /* IP_STATS */
+
+ }
+ PERF_STOP("ip_input");
+}
+
+
+/* ip_output_if:
+ *
+ * Sends an IP packet on a network interface. This function constructs the IP header
+ * and calculates the IP header checksum. If the source IP address is NULL,
+ * the IP address of the outgoing network interface is filled in as source address.
+ */
+
+err_t
+ip_output_if (struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+ u8_t ttl,
+ u8_t proto, struct netif *netif)
+{
+ struct ip_hdr *iphdr;
+
+ PERF_START;
+
+ printf("len %u tot_len %u\n", p->len, p->tot_len);
+ if (pbuf_header(p, IP_HLEN)) {
+ LWIP_DEBUGF(IP_DEBUG, ("ip_output: not enough room for IP header in pbuf\n"));
+#ifdef IP_STATS
+ ++lwip_stats.ip.err;
+#endif /* IP_STATS */
+
+ return ERR_BUF;
+ }
+ printf("len %u tot_len %u\n", p->len, p->tot_len);
+
+ iphdr = p->payload;
+
+
+ if (dest != IP_HDRINCL) {
+ printf("!IP_HDRLINCL\n");
+ iphdr->hoplim = ttl;
+ iphdr->nexthdr = proto;
+ iphdr->len = htons(p->tot_len - IP_HLEN);
+ ip_addr_set(&(iphdr->dest), dest);
+
+ iphdr->v = 6;
+
+ if (ip_addr_isany(src)) {
+ ip_addr_set(&(iphdr->src), &(netif->ip_addr));
+ } else {
+ ip_addr_set(&(iphdr->src), src);
+ }
+
+ } else {
+ dest = &(iphdr->dest);
+ }
+
+#ifdef IP_STATS
+ ++lwip_stats.ip.xmit;
+#endif /* IP_STATS */
+
+ LWIP_DEBUGF(IP_DEBUG, ("ip_output_if: %c%c (len %u)\n", netif->name[0], netif->name[1], p->tot_len));
+#if IP_DEBUG
+ ip_debug_print(p);
+#endif /* IP_DEBUG */
+
+ PERF_STOP("ip_output_if");
+ return netif->output(netif, p, dest);
+}
+
+/* ip_output:
+ *
+ * Simple interface to ip_output_if. It finds the outgoing network interface and
+ * calls upon ip_output_if to do the actual work.
+ */
+
+err_t
+ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+ u8_t ttl, u8_t proto)
+{
+ struct netif *netif;
+ if ((netif = ip_route(dest)) == NULL) {
+ LWIP_DEBUGF(IP_DEBUG, ("ip_output: No route to 0x%lx\n", dest->addr));
+#ifdef IP_STATS
+ ++lwip_stats.ip.rterr;
+#endif /* IP_STATS */
+ return ERR_RTE;
+ }
+
+ return ip_output_if (p, src, dest, ttl, proto, netif);
+}
+
+#if IP_DEBUG
+void
+ip_debug_print(struct pbuf *p)
+{
+ struct ip_hdr *iphdr = p->payload;
+ char *payload;
+
+ payload = (char *)iphdr + IP_HLEN;
+
+ LWIP_DEBUGF(IP_DEBUG, ("IP header:\n"));
+ LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+ LWIP_DEBUGF(IP_DEBUG, ("|%2d | %x%x | %x%x | (v, traffic class, flow label)\n",
+ iphdr->v,
+ iphdr->tclass1, iphdr->tclass2,
+ iphdr->flow1, iphdr->flow2));
+ LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+ LWIP_DEBUGF(IP_DEBUG, ("| %5u | %2u | %2u | (len, nexthdr, hoplim)\n",
+ ntohs(iphdr->len),
+ iphdr->nexthdr,
+ iphdr->hoplim));
+ LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+ LWIP_DEBUGF(IP_DEBUG, ("| %4lx | %4lx | (src)\n",
+ ntohl(iphdr->src.addr[0]) >> 16 & 0xffff,
+ ntohl(iphdr->src.addr[0]) & 0xffff));
+ LWIP_DEBUGF(IP_DEBUG, ("| %4lx | %4lx | (src)\n",
+ ntohl(iphdr->src.addr[1]) >> 16 & 0xffff,
+ ntohl(iphdr->src.addr[1]) & 0xffff));
+ LWIP_DEBUGF(IP_DEBUG, ("| %4lx | %4lx | (src)\n",
+ ntohl(iphdr->src.addr[2]) >> 16 & 0xffff,
+ ntohl(iphdr->src.addr[2]) & 0xffff));
+ LWIP_DEBUGF(IP_DEBUG, ("| %4lx | %4lx | (src)\n",
+ ntohl(iphdr->src.addr[3]) >> 16 & 0xffff,
+ ntohl(iphdr->src.addr[3]) & 0xffff));
+ LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+ LWIP_DEBUGF(IP_DEBUG, ("| %4lx | %4lx | (dest)\n",
+ ntohl(iphdr->dest.addr[0]) >> 16 & 0xffff,
+ ntohl(iphdr->dest.addr[0]) & 0xffff));
+ LWIP_DEBUGF(IP_DEBUG, ("| %4lx | %4lx | (dest)\n",
+ ntohl(iphdr->dest.addr[1]) >> 16 & 0xffff,
+ ntohl(iphdr->dest.addr[1]) & 0xffff));
+ LWIP_DEBUGF(IP_DEBUG, ("| %4lx | %4lx | (dest)\n",
+ ntohl(iphdr->dest.addr[2]) >> 16 & 0xffff,
+ ntohl(iphdr->dest.addr[2]) & 0xffff));
+ LWIP_DEBUGF(IP_DEBUG, ("| %4lx | %4lx | (dest)\n",
+ ntohl(iphdr->dest.addr[3]) >> 16 & 0xffff,
+ ntohl(iphdr->dest.addr[3]) & 0xffff));
+ LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+}
+#endif /* IP_DEBUG */
+
--- /dev/null
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+#include "lwip/ip_addr.h"
+#include "lwip/inet.h"
+
+
+int
+ip_addr_netcmp(struct ip_addr *addr1, struct ip_addr *addr2,
+ struct ip_addr *mask)
+{
+ return((addr1->addr[0] & mask->addr[0]) == (addr2->addr[0] & mask->addr[0]) &&
+ (addr1->addr[1] & mask->addr[1]) == (addr2->addr[1] & mask->addr[1]) &&
+ (addr1->addr[2] & mask->addr[2]) == (addr2->addr[2] & mask->addr[2]) &&
+ (addr1->addr[3] & mask->addr[3]) == (addr2->addr[3] & mask->addr[3]));
+
+}
+
+int
+ip_addr_cmp(struct ip_addr *addr1, struct ip_addr *addr2)
+{
+ return(addr1->addr[0] == addr2->addr[0] &&
+ addr1->addr[1] == addr2->addr[1] &&
+ addr1->addr[2] == addr2->addr[2] &&
+ addr1->addr[3] == addr2->addr[3]);
+}
+
+void
+ip_addr_set(struct ip_addr *dest, struct ip_addr *src)
+{
+ memcpy(dest, src, sizeof(struct ip_addr));
+ /* dest->addr[0] = src->addr[0];
+ dest->addr[1] = src->addr[1];
+ dest->addr[2] = src->addr[2];
+ dest->addr[3] = src->addr[3];*/
+}
+
+int
+ip_addr_isany(struct ip_addr *addr)
+{
+ if (addr == NULL) return 1;
+ return((addr->addr[0] | addr->addr[1] | addr->addr[2] | addr->addr[3]) == 0);
+}
+
+
+/*#if IP_DEBUG*/
+void
+ip_addr_debug_print(struct ip_addr *addr)
+{
+ printf("%lx:%lx:%lx:%lx:%lx:%lx:%lx:%lx",
+ ntohl(addr->addr[0]) >> 16 & 0xffff,
+ ntohl(addr->addr[0]) & 0xffff,
+ ntohl(addr->addr[1]) >> 16 & 0xffff,
+ ntohl(addr->addr[1]) & 0xffff,
+ ntohl(addr->addr[2]) >> 16 & 0xffff,
+ ntohl(addr->addr[2]) & 0xffff,
+ ntohl(addr->addr[3]) >> 16 & 0xffff,
+ ntohl(addr->addr[3]) & 0xffff);
+}
+/*#endif*/ /* IP_DEBUG */
+
--- /dev/null
+/** @file
+ *
+ * Dynamic memory manager
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+#include <string.h>
+
+#include "lwip/arch.h"
+#include "lwip/opt.h"
+#include "lwip/def.h"
+#include "lwip/mem.h"
+
+#include "lwip/sys.h"
+
+#include "lwip/stats.h"
+
+struct mem {
+ mem_size_t next, prev;
+#if MEM_ALIGNMENT == 1
+ u8_t used;
+#elif MEM_ALIGNMENT == 2
+ u16_t used;
+#elif MEM_ALIGNMENT == 4
+ u32_t used;
+#elif MEM_ALIGNMENT == 8
+ u64_t used;
+#else
+#error "unhandled MEM_ALIGNMENT size"
+#endif /* MEM_ALIGNMENT */
+};
+
+static struct mem *ram_end;
+static u8_t ram[MEM_SIZE + sizeof(struct mem) + MEM_ALIGNMENT];
+
+#define MIN_SIZE 12
+#if 0 /* this one does not align correctly for some, resulting in crashes */
+#define SIZEOF_STRUCT_MEM (unsigned int)MEM_ALIGN_SIZE(sizeof(struct mem))
+#else
+#define SIZEOF_STRUCT_MEM (sizeof(struct mem) + \
+ (((sizeof(struct mem) % MEM_ALIGNMENT) == 0)? 0 : \
+ (4 - (sizeof(struct mem) % MEM_ALIGNMENT))))
+#endif
+
+static struct mem *lfree; /* pointer to the lowest free block */
+
+static sys_sem_t mem_sem;
+
+static void
+plug_holes(struct mem *mem)
+{
+ struct mem *nmem;
+ struct mem *pmem;
+
+ LWIP_ASSERT("plug_holes: mem >= ram", (u8_t *)mem >= ram);
+ LWIP_ASSERT("plug_holes: mem < ram_end", (u8_t *)mem < (u8_t *)ram_end);
+ LWIP_ASSERT("plug_holes: mem->used == 0", mem->used == 0);
+
+ /* plug hole forward */
+ LWIP_ASSERT("plug_holes: mem->next <= MEM_SIZE", mem->next <= MEM_SIZE);
+
+ nmem = (struct mem *)&ram[mem->next];
+ if (mem != nmem && nmem->used == 0 && (u8_t *)nmem != (u8_t *)ram_end) {
+ if (lfree == nmem) {
+ lfree = mem;
+ }
+ mem->next = nmem->next;
+ ((struct mem *)&ram[nmem->next])->prev = (u8_t *)mem - ram;
+ }
+
+ /* plug hole backward */
+ pmem = (struct mem *)&ram[mem->prev];
+ if (pmem != mem && pmem->used == 0) {
+ if (lfree == mem) {
+ lfree = pmem;
+ }
+ pmem->next = mem->next;
+ ((struct mem *)&ram[mem->next])->prev = (u8_t *)pmem - ram;
+ }
+
+}
+void
+mem_init(void)
+{
+ struct mem *mem;
+
+ memset(ram, 0, MEM_SIZE);
+ mem = (struct mem *)ram;
+ mem->next = MEM_SIZE;
+ mem->prev = 0;
+ mem->used = 0;
+ ram_end = (struct mem *)&ram[MEM_SIZE];
+ ram_end->used = 1;
+ ram_end->next = MEM_SIZE;
+ ram_end->prev = MEM_SIZE;
+
+ mem_sem = sys_sem_new(1);
+
+ lfree = (struct mem *)ram;
+
+#if MEM_STATS
+ lwip_stats.mem.avail = MEM_SIZE;
+#endif /* MEM_STATS */
+}
+void
+mem_free(void *rmem)
+{
+ struct mem *mem;
+
+ if (rmem == NULL) {
+ LWIP_DEBUGF(MEM_DEBUG | DBG_TRACE | 2, ("mem_free(p == NULL) was called.\n"));
+ return;
+ }
+
+ sys_sem_wait(mem_sem);
+
+ LWIP_ASSERT("mem_free: legal memory", (u8_t *)rmem >= (u8_t *)ram &&
+ (u8_t *)rmem < (u8_t *)ram_end);
+
+ if ((u8_t *)rmem < (u8_t *)ram || (u8_t *)rmem >= (u8_t *)ram_end) {
+ LWIP_DEBUGF(MEM_DEBUG | 3, ("mem_free: illegal memory\n"));
+#if MEM_STATS
+ ++lwip_stats.mem.err;
+#endif /* MEM_STATS */
+ sys_sem_signal(mem_sem);
+ return;
+ }
+ mem = (struct mem *)((u8_t *)rmem - SIZEOF_STRUCT_MEM);
+
+ LWIP_ASSERT("mem_free: mem->used", mem->used);
+
+ mem->used = 0;
+
+ if (mem < lfree) {
+ lfree = mem;
+ }
+
+#if MEM_STATS
+ lwip_stats.mem.used -= mem->next - ((u8_t *)mem - ram);
+
+#endif /* MEM_STATS */
+ plug_holes(mem);
+ sys_sem_signal(mem_sem);
+}
+void *
+mem_reallocm(void *rmem, mem_size_t newsize)
+{
+ void *nmem;
+ nmem = mem_malloc(newsize);
+ if (nmem == NULL) {
+ return mem_realloc(rmem, newsize);
+ }
+ memcpy(nmem, rmem, newsize);
+ mem_free(rmem);
+ return nmem;
+}
+
+void *
+mem_realloc(void *rmem, mem_size_t newsize)
+{
+ mem_size_t size;
+ mem_size_t ptr, ptr2;
+ struct mem *mem, *mem2;
+
+ /* Expand the size of the allocated memory region so that we can
+ adjust for alignment. */
+ if ((newsize % MEM_ALIGNMENT) != 0) {
+ newsize += MEM_ALIGNMENT - ((newsize + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT);
+ }
+
+ if (newsize > MEM_SIZE) {
+ return NULL;
+ }
+
+ sys_sem_wait(mem_sem);
+
+ LWIP_ASSERT("mem_realloc: legal memory", (u8_t *)rmem >= (u8_t *)ram &&
+ (u8_t *)rmem < (u8_t *)ram_end);
+
+ if ((u8_t *)rmem < (u8_t *)ram || (u8_t *)rmem >= (u8_t *)ram_end) {
+ LWIP_DEBUGF(MEM_DEBUG | 3, ("mem_realloc: illegal memory\n"));
+ return rmem;
+ }
+ mem = (struct mem *)((u8_t *)rmem - SIZEOF_STRUCT_MEM);
+
+ ptr = (u8_t *)mem - ram;
+
+ size = mem->next - ptr - SIZEOF_STRUCT_MEM;
+#if MEM_STATS
+ lwip_stats.mem.used -= (size - newsize);
+#endif /* MEM_STATS */
+
+ if (newsize + SIZEOF_STRUCT_MEM + MIN_SIZE < size) {
+ ptr2 = ptr + SIZEOF_STRUCT_MEM + newsize;
+ mem2 = (struct mem *)&ram[ptr2];
+ mem2->used = 0;
+ mem2->next = mem->next;
+ mem2->prev = ptr;
+ mem->next = ptr2;
+ if (mem2->next != MEM_SIZE) {
+ ((struct mem *)&ram[mem2->next])->prev = ptr2;
+ }
+
+ plug_holes(mem2);
+ }
+ sys_sem_signal(mem_sem);
+ return rmem;
+}
+void *
+mem_malloc(mem_size_t size)
+{
+ mem_size_t ptr, ptr2;
+ struct mem *mem, *mem2;
+
+ if (size == 0) {
+ return NULL;
+ }
+
+ /* Expand the size of the allocated memory region so that we can
+ adjust for alignment. */
+ if ((size % MEM_ALIGNMENT) != 0) {
+ size += MEM_ALIGNMENT - ((size + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT);
+ }
+
+ if (size > MEM_SIZE) {
+ return NULL;
+ }
+
+ sys_sem_wait(mem_sem);
+
+ for (ptr = (u8_t *)lfree - ram; ptr < MEM_SIZE; ptr = ((struct mem *)&ram[ptr])->next) {
+ mem = (struct mem *)&ram[ptr];
+ if (!mem->used &&
+ mem->next - (ptr + SIZEOF_STRUCT_MEM) >= size + SIZEOF_STRUCT_MEM) {
+ ptr2 = ptr + SIZEOF_STRUCT_MEM + size;
+ mem2 = (struct mem *)&ram[ptr2];
+
+ mem2->prev = ptr;
+ mem2->next = mem->next;
+ mem->next = ptr2;
+ if (mem2->next != MEM_SIZE) {
+ ((struct mem *)&ram[mem2->next])->prev = ptr2;
+ }
+
+ mem2->used = 0;
+ mem->used = 1;
+#if MEM_STATS
+ lwip_stats.mem.used += (size + SIZEOF_STRUCT_MEM);
+ /* if (lwip_stats.mem.max < lwip_stats.mem.used) {
+ lwip_stats.mem.max = lwip_stats.mem.used;
+ } */
+ if (lwip_stats.mem.max < ptr2) {
+ lwip_stats.mem.max = ptr2;
+ }
+#endif /* MEM_STATS */
+
+ if (mem == lfree) {
+ /* Find next free block after mem */
+ while (lfree->used && lfree != ram_end) {
+ lfree = (struct mem *)&ram[lfree->next];
+ }
+ LWIP_ASSERT("mem_malloc: !lfree->used", !lfree->used);
+ }
+ sys_sem_signal(mem_sem);
+ LWIP_ASSERT("mem_malloc: allocated memory not above ram_end.",
+ (mem_ptr_t)mem + SIZEOF_STRUCT_MEM + size <= (mem_ptr_t)ram_end);
+ LWIP_ASSERT("mem_malloc: allocated memory properly aligned.",
+ (unsigned long)((u8_t *)mem + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT == 0);
+ return (u8_t *)mem + SIZEOF_STRUCT_MEM;
+ }
+ }
+ LWIP_DEBUGF(MEM_DEBUG | 2, ("mem_malloc: could not allocate %d bytes\n", (int)size));
+#if MEM_STATS
+ ++lwip_stats.mem.err;
+#endif /* MEM_STATS */
+ sys_sem_signal(mem_sem);
+ return NULL;
+}
--- /dev/null
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+#include "lwip/opt.h"
+
+#include "lwip/memp.h"
+
+#include "lwip/pbuf.h"
+#include "lwip/udp.h"
+#include "lwip/raw.h"
+#include "lwip/tcp.h"
+#include "lwip/api.h"
+#include "lwip/api_msg.h"
+#include "lwip/tcpip.h"
+
+#include "lwip/sys.h"
+#include "lwip/stats.h"
+
+struct memp {
+ struct memp *next;
+};
+
+
+
+static struct memp *memp_tab[MEMP_MAX];
+
+static const u16_t memp_sizes[MEMP_MAX] = {
+ sizeof(struct pbuf),
+ sizeof(struct raw_pcb),
+ sizeof(struct udp_pcb),
+ sizeof(struct tcp_pcb),
+ sizeof(struct tcp_pcb_listen),
+ sizeof(struct tcp_seg),
+ sizeof(struct netbuf),
+ sizeof(struct netconn),
+ sizeof(struct api_msg),
+ sizeof(struct tcpip_msg),
+ sizeof(struct sys_timeout)
+};
+
+static const u16_t memp_num[MEMP_MAX] = {
+ MEMP_NUM_PBUF,
+ MEMP_NUM_RAW_PCB,
+ MEMP_NUM_UDP_PCB,
+ MEMP_NUM_TCP_PCB,
+ MEMP_NUM_TCP_PCB_LISTEN,
+ MEMP_NUM_TCP_SEG,
+ MEMP_NUM_NETBUF,
+ MEMP_NUM_NETCONN,
+ MEMP_NUM_API_MSG,
+ MEMP_NUM_TCPIP_MSG,
+ MEMP_NUM_SYS_TIMEOUT
+};
+
+static u8_t memp_memory[(MEMP_NUM_PBUF *
+ MEM_ALIGN_SIZE(sizeof(struct pbuf) +
+ sizeof(struct memp)) +
+ MEMP_NUM_RAW_PCB *
+ MEM_ALIGN_SIZE(sizeof(struct raw_pcb) +
+ sizeof(struct memp)) +
+ MEMP_NUM_UDP_PCB *
+ MEM_ALIGN_SIZE(sizeof(struct udp_pcb) +
+ sizeof(struct memp)) +
+ MEMP_NUM_TCP_PCB *
+ MEM_ALIGN_SIZE(sizeof(struct tcp_pcb) +
+ sizeof(struct memp)) +
+ MEMP_NUM_TCP_PCB_LISTEN *
+ MEM_ALIGN_SIZE(sizeof(struct tcp_pcb_listen) +
+ sizeof(struct memp)) +
+ MEMP_NUM_TCP_SEG *
+ MEM_ALIGN_SIZE(sizeof(struct tcp_seg) +
+ sizeof(struct memp)) +
+ MEMP_NUM_NETBUF *
+ MEM_ALIGN_SIZE(sizeof(struct netbuf) +
+ sizeof(struct memp)) +
+ MEMP_NUM_NETCONN *
+ MEM_ALIGN_SIZE(sizeof(struct netconn) +
+ sizeof(struct memp)) +
+ MEMP_NUM_API_MSG *
+ MEM_ALIGN_SIZE(sizeof(struct api_msg) +
+ sizeof(struct memp)) +
+ MEMP_NUM_TCPIP_MSG *
+ MEM_ALIGN_SIZE(sizeof(struct tcpip_msg) +
+ sizeof(struct memp)) +
+ MEMP_NUM_SYS_TIMEOUT *
+ MEM_ALIGN_SIZE(sizeof(struct sys_timeout) +
+ sizeof(struct memp)))];
+
+
+#if !SYS_LIGHTWEIGHT_PROT
+static sys_sem_t mutex;
+#endif
+
+#if MEMP_SANITY_CHECK
+static int
+memp_sanity(void)
+{
+ int i, c;
+ struct memp *m, *n;
+
+ for(i = 0; i < MEMP_MAX; i++) {
+ for(m = memp_tab[i]; m != NULL; m = m->next) {
+ c = 1;
+ for(n = memp_tab[i]; n != NULL; n = n->next) {
+ if (n == m) {
+ --c;
+ }
+ if (c < 0) return 0; /* LW was: abort(); */
+ }
+ }
+ }
+ return 1;
+}
+#endif /* MEMP_SANITY_CHECK*/
+
+void
+memp_init(void)
+{
+ struct memp *m, *memp;
+ u16_t i, j;
+ u16_t size;
+
+#if MEMP_STATS
+ for(i = 0; i < MEMP_MAX; ++i) {
+ lwip_stats.memp[i].used = lwip_stats.memp[i].max =
+ lwip_stats.memp[i].err = 0;
+ lwip_stats.memp[i].avail = memp_num[i];
+ }
+#endif /* MEMP_STATS */
+
+ memp = (struct memp *)&memp_memory[0];
+ for(i = 0; i < MEMP_MAX; ++i) {
+ size = MEM_ALIGN_SIZE(memp_sizes[i] + sizeof(struct memp));
+ if (memp_num[i] > 0) {
+ memp_tab[i] = memp;
+ m = memp;
+
+ for(j = 0; j < memp_num[i]; ++j) {
+ m->next = (struct memp *)MEM_ALIGN((u8_t *)m + size);
+ memp = m;
+ m = m->next;
+ }
+ memp->next = NULL;
+ memp = m;
+ } else {
+ memp_tab[i] = NULL;
+ }
+ }
+
+#if !SYS_LIGHTWEIGHT_PROT
+ mutex = sys_sem_new(1);
+#endif
+
+
+}
+
+void *
+memp_malloc(memp_t type)
+{
+ struct memp *memp;
+ void *mem;
+#if SYS_LIGHTWEIGHT_PROT
+ SYS_ARCH_DECL_PROTECT(old_level);
+#endif
+
+ LWIP_ASSERT("memp_malloc: type < MEMP_MAX", type < MEMP_MAX);
+
+#if SYS_LIGHTWEIGHT_PROT
+ SYS_ARCH_PROTECT(old_level);
+#else /* SYS_LIGHTWEIGHT_PROT */
+ sys_sem_wait(mutex);
+#endif /* SYS_LIGHTWEIGHT_PROT */
+
+ memp = memp_tab[type];
+
+ if (memp != NULL) {
+ memp_tab[type] = memp->next;
+ memp->next = NULL;
+#if MEMP_STATS
+ ++lwip_stats.memp[type].used;
+ if (lwip_stats.memp[type].used > lwip_stats.memp[type].max) {
+ lwip_stats.memp[type].max = lwip_stats.memp[type].used;
+ }
+#endif /* MEMP_STATS */
+#if SYS_LIGHTWEIGHT_PROT
+ SYS_ARCH_UNPROTECT(old_level);
+#else /* SYS_LIGHTWEIGHT_PROT */
+ sys_sem_signal(mutex);
+#endif /* SYS_LIGHTWEIGHT_PROT */
+ LWIP_ASSERT("memp_malloc: memp properly aligned",
+ ((mem_ptr_t)MEM_ALIGN((u8_t *)memp + sizeof(struct memp)) % MEM_ALIGNMENT) == 0);
+
+ mem = MEM_ALIGN((u8_t *)memp + sizeof(struct memp));
+ return mem;
+ } else {
+ LWIP_DEBUGF(MEMP_DEBUG | 2, ("memp_malloc: out of memory in pool %d\n", type));
+#if MEMP_STATS
+ ++lwip_stats.memp[type].err;
+#endif /* MEMP_STATS */
+#if SYS_LIGHTWEIGHT_PROT
+ SYS_ARCH_UNPROTECT(old_level);
+#else /* SYS_LIGHTWEIGHT_PROT */
+ sys_sem_signal(mutex);
+#endif /* SYS_LIGHTWEIGHT_PROT */
+ return NULL;
+ }
+}
+
+void
+memp_free(memp_t type, void *mem)
+{
+ struct memp *memp;
+#if SYS_LIGHTWEIGHT_PROT
+ SYS_ARCH_DECL_PROTECT(old_level);
+#endif /* SYS_LIGHTWEIGHT_PROT */
+
+ if (mem == NULL) {
+ return;
+ }
+ memp = (struct memp *)((u8_t *)mem - sizeof(struct memp));
+
+#if SYS_LIGHTWEIGHT_PROT
+ SYS_ARCH_PROTECT(old_level);
+#else /* SYS_LIGHTWEIGHT_PROT */
+ sys_sem_wait(mutex);
+#endif /* SYS_LIGHTWEIGHT_PROT */
+
+#if MEMP_STATS
+ lwip_stats.memp[type].used--;
+#endif /* MEMP_STATS */
+
+ memp->next = memp_tab[type];
+ memp_tab[type] = memp;
+
+#if MEMP_SANITY_CHECK
+ LWIP_ASSERT("memp sanity", memp_sanity());
+#endif
+
+#if SYS_LIGHTWEIGHT_PROT
+ SYS_ARCH_UNPROTECT(old_level);
+#else /* SYS_LIGHTWEIGHT_PROT */
+ sys_sem_signal(mutex);
+#endif /* SYS_LIGHTWEIGHT_PROT */
+}
+
--- /dev/null
+/**
+ * @file
+ *
+ * lwIP network interface abstraction
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+#include "lwip/opt.h"
+
+#include "lwip/def.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/tcp.h"
+
+struct netif *netif_list = NULL;
+struct netif *netif_default = NULL;
+
+/**
+ * Add a network interface to the list of lwIP netifs.
+ *
+ * @param netif a pre-allocated netif structure
+ * @param ipaddr IP address for the new netif
+ * @param netmask network mask for the new netif
+ * @param gw default gateway IP address for the new netif
+ * @param state opaque data passed to the new netif
+ * @param init callback function that initializes the interface
+ * @param input callback function that is called to pass
+ * ingress packets up in the protocol layer stack.
+ *
+ * @return netif, or NULL if failed.
+ */
+struct netif *
+netif_add(struct netif *netif, struct ip_addr *ipaddr, struct ip_addr *netmask,
+ struct ip_addr *gw,
+ void *state,
+ err_t (* init)(struct netif *netif),
+ err_t (* input)(struct pbuf *p, struct netif *netif))
+{
+ static int netifnum = 0;
+
+#if LWIP_DHCP
+ /* netif not under DHCP control by default */
+ netif->dhcp = NULL;
+#endif
+ /* remember netif specific state information data */
+ netif->state = state;
+ netif->num = netifnum++;
+ netif->input = input;
+
+ netif_set_addr(netif, ipaddr, netmask, gw);
+
+ /* call user specified initialization function for netif */
+ if (init(netif) != ERR_OK) {
+ return NULL;
+ }
+
+ /* add this netif to the list */
+ netif->next = netif_list;
+ netif_list = netif;
+ LWIP_DEBUGF(NETIF_DEBUG, ("netif: added interface %c%c IP addr ",
+ netif->name[0], netif->name[1]));
+ ip_addr_debug_print(NETIF_DEBUG, ipaddr);
+ LWIP_DEBUGF(NETIF_DEBUG, (" netmask "));
+ ip_addr_debug_print(NETIF_DEBUG, netmask);
+ LWIP_DEBUGF(NETIF_DEBUG, (" gw "));
+ ip_addr_debug_print(NETIF_DEBUG, gw);
+ LWIP_DEBUGF(NETIF_DEBUG, ("\n"));
+ return netif;
+}
+
+void
+netif_set_addr(struct netif *netif,struct ip_addr *ipaddr, struct ip_addr *netmask,
+ struct ip_addr *gw)
+{
+ netif_set_ipaddr(netif, ipaddr);
+ netif_set_netmask(netif, netmask);
+ netif_set_gw(netif, gw);
+}
+
+void netif_remove(struct netif * netif)
+{
+ if ( netif == NULL ) return;
+
+ /* is it the first netif? */
+ if (netif_list == netif) {
+ netif_list = netif->next;
+ }
+ else {
+ /* look for netif further down the list */
+ struct netif * tmpNetif;
+ for (tmpNetif = netif_list; tmpNetif != NULL; tmpNetif = tmpNetif->next) {
+ if (tmpNetif->next == netif) {
+ tmpNetif->next = netif->next;
+ break;
+ }
+ }
+ if (tmpNetif == NULL)
+ return; /* we didn't find any netif today */
+ }
+ /* this netif is default? */
+ if (netif_default == netif)
+ /* reset default netif */
+ netif_default = NULL;
+ LWIP_DEBUGF( NETIF_DEBUG, ("netif_remove: removed netif\n") );
+}
+
+struct netif *
+netif_find(char *name)
+{
+ struct netif *netif;
+ u8_t num;
+
+ if (name == NULL) {
+ return NULL;
+ }
+
+ num = name[2] - '0';
+
+ for(netif = netif_list; netif != NULL; netif = netif->next) {
+ if (num == netif->num &&
+ name[0] == netif->name[0] &&
+ name[1] == netif->name[1]) {
+ LWIP_DEBUGF(NETIF_DEBUG, ("netif_find: found %c%c\n", name[0], name[1]));
+ return netif;
+ }
+ }
+ LWIP_DEBUGF(NETIF_DEBUG, ("netif_find: didn't find %c%c\n", name[0], name[1]));
+ return NULL;
+}
+
+void
+netif_set_ipaddr(struct netif *netif, struct ip_addr *ipaddr)
+{
+ /* TODO: Handling of obsolete pcbs */
+ /* See: http://mail.gnu.org/archive/html/lwip-users/2003-03/msg00118.html */
+#if LWIP_TCP
+ struct tcp_pcb *pcb;
+ struct tcp_pcb_listen *lpcb;
+
+ /* address is actually being changed? */
+ if ((ip_addr_cmp(ipaddr, &(netif->ip_addr))) == 0)
+ {
+ /* extern struct tcp_pcb *tcp_active_pcbs; defined by tcp.h */
+ LWIP_DEBUGF(NETIF_DEBUG | 1, ("netif_set_ipaddr: netif address being changed\n"));
+ pcb = tcp_active_pcbs;
+ while (pcb != NULL) {
+ /* PCB bound to current local interface address? */
+ if (ip_addr_cmp(&(pcb->local_ip), &(netif->ip_addr))) {
+ /* this connection must be aborted */
+ struct tcp_pcb *next = pcb->next;
+ LWIP_DEBUGF(NETIF_DEBUG | 1, ("netif_set_ipaddr: aborting TCP pcb %p\n", (void *)pcb));
+ tcp_abort(pcb);
+ pcb = next;
+ } else {
+ pcb = pcb->next;
+ }
+ }
+ for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) {
+ /* PCB bound to current local interface address? */
+ if (ip_addr_cmp(&(lpcb->local_ip), &(netif->ip_addr))) {
+ /* The PCB is listening to the old ipaddr and
+ * is set to listen to the new one instead */
+ ip_addr_set(&(lpcb->local_ip), ipaddr);
+ }
+ }
+ }
+#endif
+ ip_addr_set(&(netif->ip_addr), ipaddr);
+#if 0 /* only allowed for Ethernet interfaces TODO: how can we check? */
+ /** For Ethernet network interfaces, we would like to send a
+ * "gratuitous ARP"; this is an ARP packet sent by a node in order
+ * to spontaneously cause other nodes to update an entry in their
+ * ARP cache. From RFC 3220 "IP Mobility Support for IPv4" section 4.6.
+ */
+ etharp_query(netif, ipaddr, NULL);
+#endif
+ LWIP_DEBUGF(NETIF_DEBUG | DBG_TRACE | DBG_STATE | 3, ("netif: IP address of interface %c%c set to %u.%u.%u.%u\n",
+ netif->name[0], netif->name[1],
+ ip4_addr1(&netif->ip_addr),
+ ip4_addr2(&netif->ip_addr),
+ ip4_addr3(&netif->ip_addr),
+ ip4_addr4(&netif->ip_addr)));
+}
+
+void
+netif_set_gw(struct netif *netif, struct ip_addr *gw)
+{
+ ip_addr_set(&(netif->gw), gw);
+ LWIP_DEBUGF(NETIF_DEBUG | DBG_TRACE | DBG_STATE | 3, ("netif: GW address of interface %c%c set to %u.%u.%u.%u\n",
+ netif->name[0], netif->name[1],
+ ip4_addr1(&netif->gw),
+ ip4_addr2(&netif->gw),
+ ip4_addr3(&netif->gw),
+ ip4_addr4(&netif->gw)));
+}
+
+void
+netif_set_netmask(struct netif *netif, struct ip_addr *netmask)
+{
+ ip_addr_set(&(netif->netmask), netmask);
+ LWIP_DEBUGF(NETIF_DEBUG | DBG_TRACE | DBG_STATE | 3, ("netif: netmask of interface %c%c set to %u.%u.%u.%u\n",
+ netif->name[0], netif->name[1],
+ ip4_addr1(&netif->netmask),
+ ip4_addr2(&netif->netmask),
+ ip4_addr3(&netif->netmask),
+ ip4_addr4(&netif->netmask)));
+}
+
+void
+netif_set_default(struct netif *netif)
+{
+ netif_default = netif;
+ LWIP_DEBUGF(NETIF_DEBUG, ("netif: setting default interface %c%c\n",
+ netif ? netif->name[0] : '\'', netif ? netif->name[1] : '\''));
+}
+
+/**
+ * Bring an interface up, available for processing
+ * traffic.
+ *
+ * @note: Enabling DHCP on a down interface will make it come
+ * up once configured.
+ *
+ * @see dhcp_start()
+ */
+void netif_set_up(struct netif *netif)
+{
+ netif->flags |= NETIF_FLAG_UP;
+}
+
+/**
+ * Ask if an interface is up
+ */
+u8_t netif_is_up(struct netif *netif)
+{
+ return (netif->flags & NETIF_FLAG_UP)?1:0;
+}
+
+/**
+ * Bring an interface down, disabling any traffic processing.
+ *
+ * @note: Enabling DHCP on a down interface will make it come
+ * up once configured.
+ *
+ * @see dhcp_start()
+ */
+void netif_set_down(struct netif *netif)
+{
+ netif->flags &= ~NETIF_FLAG_UP;
+}
+
+void
+netif_init(void)
+{
+ netif_list = netif_default = NULL;
+}
+
--- /dev/null
+/**\r
+ * @file\r
+ * Packet buffer management\r
+ *\r
+ * Packets are built from the pbuf data structure. It supports dynamic\r
+ * memory allocation for packet contents or can reference externally\r
+ * managed packet contents both in RAM and ROM. Quick allocation for\r
+ * incoming packets is provided through pools with fixed sized pbufs.\r
+ *\r
+ * A packet may span over multiple pbufs, chained as a singly linked\r
+ * list. This is called a "pbuf chain".\r
+ *\r
+ * Multiple packets may be queued, also using this singly linked list.\r
+ * This is called a "packet queue".\r
+ * \r
+ * So, a packet queue consists of one or more pbuf chains, each of\r
+ * which consist of one or more pbufs. Currently, queues are only\r
+ * supported in a limited section of lwIP, this is the etharp queueing\r
+ * code. Outside of this section no packet queues are supported yet.\r
+ * \r
+ * The differences between a pbuf chain and a packet queue are very\r
+ * precise but subtle. \r
+ *\r
+ * The last pbuf of a packet has a ->tot_len field that equals the\r
+ * ->len field. It can be found by traversing the list. If the last\r
+ * pbuf of a packet has a ->next field other than NULL, more packets\r
+ * are on the queue.\r
+ *\r
+ * Therefore, looping through a pbuf of a single packet, has an\r
+ * loop end condition (tot_len == p->len), NOT (next == NULL).\r
+ */\r
+\r
+/*\r
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. The name of the author may not be used to endorse or promote products\r
+ * derived from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT\r
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT\r
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING\r
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY\r
+ * OF SUCH DAMAGE.\r
+ *\r
+ * This file is part of the lwIP TCP/IP stack.\r
+ *\r
+ * Author: Adam Dunkels <adam@sics.se>\r
+ *\r
+ */\r
+\r
+#include "lwip/opt.h"\r
+\r
+#include "lwip/stats.h"\r
+\r
+#include "lwip/def.h"\r
+#include "lwip/mem.h"\r
+#include "lwip/memp.h"\r
+#include "lwip/pbuf.h"\r
+\r
+#include "lwip/sys.h"\r
+\r
+#include "arch/perf.h"\r
+\r
+#include <string.h>\r
+\r
+static u8_t pbuf_pool_memory[(PBUF_POOL_SIZE * MEM_ALIGN_SIZE(PBUF_POOL_BUFSIZE + sizeof(struct pbuf)))];\r
+\r
+#if !SYS_LIGHTWEIGHT_PROT\r
+static volatile u8_t pbuf_pool_free_lock, pbuf_pool_alloc_lock;\r
+static sys_sem_t pbuf_pool_free_sem;\r
+#endif\r
+\r
+static struct pbuf *pbuf_pool = NULL;\r
+\r
+/**\r
+ * Initializes the pbuf module.\r
+ *\r
+ * A large part of memory is allocated for holding the pool of pbufs.\r
+ * The size of the individual pbufs in the pool is given by the size\r
+ * parameter, and the number of pbufs in the pool by the num parameter.\r
+ *\r
+ * After the memory has been allocated, the pbufs are set up. The\r
+ * ->next pointer in each pbuf is set up to point to the next pbuf in\r
+ * the pool.\r
+ *\r
+ */\r
+void\r
+pbuf_init(void)\r
+{\r
+ struct pbuf *p, *q = NULL;\r
+ u16_t i;\r
+\r
+ pbuf_pool = (struct pbuf *)&pbuf_pool_memory[0];\r
+ LWIP_ASSERT("pbuf_init: pool aligned", (mem_ptr_t)pbuf_pool % MEM_ALIGNMENT == 0);\r
+\r
+#if PBUF_STATS\r
+ lwip_stats.pbuf.avail = PBUF_POOL_SIZE;\r
+#endif /* PBUF_STATS */\r
+\r
+ /* Set up ->next pointers to link the pbufs of the pool together */\r
+ p = pbuf_pool;\r
+\r
+ for(i = 0; i < PBUF_POOL_SIZE; ++i) {\r
+ p->next = (struct pbuf *)((u8_t *)p + PBUF_POOL_BUFSIZE + sizeof(struct pbuf));\r
+ p->len = p->tot_len = PBUF_POOL_BUFSIZE;\r
+ p->payload = MEM_ALIGN((void *)((u8_t *)p + sizeof(struct pbuf)));\r
+ p->flags = PBUF_FLAG_POOL;\r
+ q = p;\r
+ p = p->next;\r
+ }\r
+\r
+ /* The ->next pointer of last pbuf is NULL to indicate that there\r
+ are no more pbufs in the pool */\r
+ q->next = NULL;\r
+\r
+#if !SYS_LIGHTWEIGHT_PROT\r
+ pbuf_pool_alloc_lock = 0;\r
+ pbuf_pool_free_lock = 0;\r
+ pbuf_pool_free_sem = sys_sem_new(1);\r
+#endif\r
+}\r
+\r
+/**\r
+ * @internal only called from pbuf_alloc()\r
+ */\r
+static struct pbuf *\r
+pbuf_pool_alloc(void)\r
+{\r
+ struct pbuf *p = NULL;\r
+\r
+ SYS_ARCH_DECL_PROTECT(old_level);\r
+ SYS_ARCH_PROTECT(old_level);\r
+\r
+#if !SYS_LIGHTWEIGHT_PROT\r
+ /* Next, check the actual pbuf pool, but if the pool is locked, we\r
+ pretend to be out of buffers and return NULL. */\r
+ if (pbuf_pool_free_lock) {\r
+#if PBUF_STATS\r
+ ++lwip_stats.pbuf.alloc_locked;\r
+#endif /* PBUF_STATS */\r
+ return NULL;\r
+ }\r
+ pbuf_pool_alloc_lock = 1;\r
+ if (!pbuf_pool_free_lock) {\r
+#endif /* SYS_LIGHTWEIGHT_PROT */\r
+ p = pbuf_pool;\r
+ if (p) {\r
+ pbuf_pool = p->next;\r
+ }\r
+#if !SYS_LIGHTWEIGHT_PROT\r
+#if PBUF_STATS\r
+ } else {\r
+ ++lwip_stats.pbuf.alloc_locked;\r
+#endif /* PBUF_STATS */\r
+ }\r
+ pbuf_pool_alloc_lock = 0;\r
+#endif /* SYS_LIGHTWEIGHT_PROT */\r
+\r
+#if PBUF_STATS\r
+ if (p != NULL) {\r
+ ++lwip_stats.pbuf.used;\r
+ if (lwip_stats.pbuf.used > lwip_stats.pbuf.max) {\r
+ lwip_stats.pbuf.max = lwip_stats.pbuf.used;\r
+ }\r
+ }\r
+#endif /* PBUF_STATS */\r
+\r
+ SYS_ARCH_UNPROTECT(old_level);\r
+ return p;\r
+}\r
+\r
+\r
+/**\r
+ * Allocates a pbuf of the given type (possibly a chain for PBUF_POOL type).\r
+ *\r
+ * The actual memory allocated for the pbuf is determined by the\r
+ * layer at which the pbuf is allocated and the requested size\r
+ * (from the size parameter).\r
+ *\r
+ * @param flag this parameter decides how and where the pbuf\r
+ * should be allocated as follows:\r
+ *\r
+ * - PBUF_RAM: buffer memory for pbuf is allocated as one large\r
+ * chunk. This includes protocol headers as well.\r
+ * - PBUF_ROM: no buffer memory is allocated for the pbuf, even for\r
+ * protocol headers. Additional headers must be prepended\r
+ * by allocating another pbuf and chain in to the front of\r
+ * the ROM pbuf. It is assumed that the memory used is really\r
+ * similar to ROM in that it is immutable and will not be\r
+ * changed. Memory which is dynamic should generally not\r
+ * be attached to PBUF_ROM pbufs. Use PBUF_REF instead.\r
+ * - PBUF_REF: no buffer memory is allocated for the pbuf, even for\r
+ * protocol headers. It is assumed that the pbuf is only\r
+ * being used in a single thread. If the pbuf gets queued,\r
+ * then pbuf_take should be called to copy the buffer.\r
+ * - PBUF_POOL: the pbuf is allocated as a pbuf chain, with pbufs from\r
+ * the pbuf pool that is allocated during pbuf_init().\r
+ *\r
+ * @return the allocated pbuf. If multiple pbufs where allocated, this\r
+ * is the first pbuf of a pbuf chain.\r
+ */\r
+struct pbuf *\r
+pbuf_alloc(pbuf_layer l, u16_t length, pbuf_flag flag)\r
+{\r
+ struct pbuf *p, *q, *r;\r
+ u16_t offset;\r
+ s32_t rem_len; /* remaining length */\r
+ LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_alloc(length=%u)\n", length));\r
+\r
+ /* determine header offset */\r
+ offset = 0;\r
+ switch (l) {\r
+ case PBUF_TRANSPORT:\r
+ /* add room for transport (often TCP) layer header */\r
+ offset += PBUF_TRANSPORT_HLEN;\r
+ /* FALLTHROUGH */\r
+ case PBUF_IP:\r
+ /* add room for IP layer header */\r
+ offset += PBUF_IP_HLEN;\r
+ /* FALLTHROUGH */\r
+ case PBUF_LINK:\r
+ /* add room for link layer header */\r
+ offset += PBUF_LINK_HLEN;\r
+ break;\r
+ case PBUF_RAW:\r
+ break;\r
+ default:\r
+ LWIP_ASSERT("pbuf_alloc: bad pbuf layer", 0);\r
+ return NULL;\r
+ }\r
+\r
+ switch (flag) {\r
+ case PBUF_POOL:\r
+ /* allocate head of pbuf chain into p */\r
+ p = pbuf_pool_alloc();\r
+ LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_alloc: allocated pbuf %p\n", (void *)p));\r
+ if (p == NULL) {\r
+#if PBUF_STATS\r
+ ++lwip_stats.pbuf.err;\r
+#endif /* PBUF_STATS */\r
+ return NULL;\r
+ }\r
+ p->next = NULL;\r
+\r
+ /* make the payload pointer point 'offset' bytes into pbuf data memory */\r
+ p->payload = MEM_ALIGN((void *)((u8_t *)p + (sizeof(struct pbuf) + offset)));\r
+ LWIP_ASSERT("pbuf_alloc: pbuf p->payload properly aligned",\r
+ ((mem_ptr_t)p->payload % MEM_ALIGNMENT) == 0);\r
+ /* the total length of the pbuf chain is the requested size */\r
+ p->tot_len = length;\r
+ /* set the length of the first pbuf in the chain */\r
+ p->len = length > PBUF_POOL_BUFSIZE - offset? PBUF_POOL_BUFSIZE - offset: length;\r
+ /* set reference count (needed here in case we fail) */\r
+ p->ref = 1;\r
+\r
+ /* now allocate the tail of the pbuf chain */\r
+\r
+ /* remember first pbuf for linkage in next iteration */\r
+ r = p;\r
+ /* remaining length to be allocated */\r
+ rem_len = length - p->len;\r
+ /* any remaining pbufs to be allocated? */\r
+ while (rem_len > 0) {\r
+ q = pbuf_pool_alloc();\r
+ if (q == NULL) {\r
+ LWIP_DEBUGF(PBUF_DEBUG | 2, ("pbuf_alloc: Out of pbufs in pool.\n"));\r
+#if PBUF_STATS\r
+ ++lwip_stats.pbuf.err;\r
+#endif /* PBUF_STATS */\r
+ /* free chain so far allocated */\r
+ pbuf_free(p);\r
+ /* bail out unsuccesfully */\r
+ return NULL;\r
+ }\r
+ q->next = NULL;\r
+ /* make previous pbuf point to this pbuf */\r
+ r->next = q;\r
+ /* set total length of this pbuf and next in chain */\r
+ q->tot_len = rem_len;\r
+ /* this pbuf length is pool size, unless smaller sized tail */\r
+ q->len = rem_len > PBUF_POOL_BUFSIZE? PBUF_POOL_BUFSIZE: rem_len;\r
+ q->payload = (void *)((u8_t *)q + sizeof(struct pbuf));\r
+ LWIP_ASSERT("pbuf_alloc: pbuf q->payload properly aligned",\r
+ ((mem_ptr_t)q->payload % MEM_ALIGNMENT) == 0);\r
+ q->ref = 1;\r
+ /* calculate remaining length to be allocated */\r
+ rem_len -= q->len;\r
+ /* remember this pbuf for linkage in next iteration */\r
+ r = q;\r
+ }\r
+ /* end of chain */\r
+ /*r->next = NULL;*/\r
+\r
+ break;\r
+ case PBUF_RAM:\r
+ /* If pbuf is to be allocated in RAM, allocate memory for it. */\r
+ p = mem_malloc(MEM_ALIGN_SIZE(sizeof(struct pbuf) + offset) + MEM_ALIGN_SIZE(length));\r
+ if (p == NULL) {\r
+ return NULL;\r
+ }\r
+ /* Set up internal structure of the pbuf. */\r
+ p->payload = MEM_ALIGN((void *)((u8_t *)p + sizeof(struct pbuf) + offset));\r
+ p->len = p->tot_len = length;\r
+ p->next = NULL;\r
+ p->flags = PBUF_FLAG_RAM;\r
+\r
+ LWIP_ASSERT("pbuf_alloc: pbuf->payload properly aligned",\r
+ ((mem_ptr_t)p->payload % MEM_ALIGNMENT) == 0);\r
+ break;\r
+ /* pbuf references existing (non-volatile static constant) ROM payload? */\r
+ case PBUF_ROM:\r
+ /* pbuf references existing (externally allocated) RAM payload? */\r
+ case PBUF_REF:\r
+ /* only allocate memory for the pbuf structure */\r
+ p = memp_malloc(MEMP_PBUF);\r
+ if (p == NULL) {\r
+ LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_alloc: Could not allocate MEMP_PBUF for PBUF_%s.\n", flag == PBUF_ROM?"ROM":"REF"));\r
+ return NULL;\r
+ }\r
+ /* caller must set this field properly, afterwards */\r
+ p->payload = NULL;\r
+ p->len = p->tot_len = length;\r
+ p->next = NULL;\r
+ p->flags = (flag == PBUF_ROM? PBUF_FLAG_ROM: PBUF_FLAG_REF);\r
+ break;\r
+ default:\r
+ LWIP_ASSERT("pbuf_alloc: erroneous flag", 0);\r
+ return NULL;\r
+ }\r
+ /* set reference count */\r
+ p->ref = 1;\r
+ LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_alloc(length=%u) == %p\n", length, (void *)p));\r
+ return p;\r
+}\r
+\r
+\r
+#if PBUF_STATS\r
+#define DEC_PBUF_STATS do { --lwip_stats.pbuf.used; } while (0)\r
+#else /* PBUF_STATS */\r
+#define DEC_PBUF_STATS\r
+#endif /* PBUF_STATS */\r
+\r
+#define PBUF_POOL_FAST_FREE(p) do { \\r
+ p->next = pbuf_pool; \\r
+ pbuf_pool = p; \\r
+ DEC_PBUF_STATS; \\r
+ } while (0)\r
+\r
+#if SYS_LIGHTWEIGHT_PROT\r
+#define PBUF_POOL_FREE(p) do { \\r
+ SYS_ARCH_DECL_PROTECT(old_level); \\r
+ SYS_ARCH_PROTECT(old_level); \\r
+ PBUF_POOL_FAST_FREE(p); \\r
+ SYS_ARCH_UNPROTECT(old_level); \\r
+ } while (0)\r
+#else /* SYS_LIGHTWEIGHT_PROT */\r
+#define PBUF_POOL_FREE(p) do { \\r
+ sys_sem_wait(pbuf_pool_free_sem); \\r
+ PBUF_POOL_FAST_FREE(p); \\r
+ sys_sem_signal(pbuf_pool_free_sem); \\r
+ } while (0)\r
+#endif /* SYS_LIGHTWEIGHT_PROT */\r
+\r
+/**\r
+ * Shrink a pbuf chain to a desired length.\r
+ *\r
+ * @param p pbuf to shrink.\r
+ * @param new_len desired new length of pbuf chain\r
+ *\r
+ * Depending on the desired length, the first few pbufs in a chain might\r
+ * be skipped and left unchanged. The new last pbuf in the chain will be\r
+ * resized, and any remaining pbufs will be freed.\r
+ *\r
+ * @note If the pbuf is ROM/REF, only the ->tot_len and ->len fields are adjusted.\r
+ * @note May not be called on a packet queue.\r
+ *\r
+ * @bug Cannot grow the size of a pbuf (chain) (yet).\r
+ */\r
+void\r
+pbuf_realloc(struct pbuf *p, u16_t new_len)\r
+{\r
+ struct pbuf *q;\r
+ u16_t rem_len; /* remaining length */\r
+ s16_t grow;\r
+\r
+ LWIP_ASSERT("pbuf_realloc: sane p->flags", p->flags == PBUF_FLAG_POOL ||\r
+ p->flags == PBUF_FLAG_ROM ||\r
+ p->flags == PBUF_FLAG_RAM ||\r
+ p->flags == PBUF_FLAG_REF);\r
+\r
+ /* desired length larger than current length? */\r
+ if (new_len >= p->tot_len) {\r
+ /* enlarging not yet supported */\r
+ return;\r
+ }\r
+\r
+ /* the pbuf chain grows by (new_len - p->tot_len) bytes\r
+ * (which may be negative in case of shrinking) */\r
+ grow = new_len - p->tot_len;\r
+\r
+ /* first, step over any pbufs that should remain in the chain */\r
+ rem_len = new_len;\r
+ q = p;\r
+ /* should this pbuf be kept? */\r
+ while (rem_len > q->len) {\r
+ /* decrease remaining length by pbuf length */\r
+ rem_len -= q->len;\r
+ /* decrease total length indicator */\r
+ q->tot_len += grow;\r
+ /* proceed to next pbuf in chain */\r
+ q = q->next;\r
+ }\r
+ /* we have now reached the new last pbuf (in q) */\r
+ /* rem_len == desired length for pbuf q */\r
+\r
+ /* shrink allocated memory for PBUF_RAM */\r
+ /* (other types merely adjust their length fields */\r
+ if ((q->flags == PBUF_FLAG_RAM) && (rem_len != q->len)) {\r
+ /* reallocate and adjust the length of the pbuf that will be split */\r
+ mem_realloc(q, (u8_t *)q->payload - (u8_t *)q + rem_len);\r
+ }\r
+ /* adjust length fields for new last pbuf */\r
+ q->len = rem_len;\r
+ q->tot_len = q->len;\r
+\r
+ /* any remaining pbufs in chain? */\r
+ if (q->next != NULL) {\r
+ /* free remaining pbufs in chain */\r
+ pbuf_free(q->next);\r
+ }\r
+ /* q is last packet in chain */\r
+ q->next = NULL;\r
+\r
+}\r
+\r
+/**\r
+ * Adjusts the payload pointer to hide or reveal headers in the payload.\r
+ *\r
+ * Adjusts the ->payload pointer so that space for a header\r
+ * (dis)appears in the pbuf payload.\r
+ *\r
+ * The ->payload, ->tot_len and ->len fields are adjusted.\r
+ *\r
+ * @param hdr_size_inc Number of bytes to increment header size which\r
+ * increases the size of the pbuf. New space is on the front.\r
+ * (Using a negative value decreases the header size.)\r
+ * If hdr_size_inc is 0, this function does nothing and returns succesful.\r
+ *\r
+ * PBUF_ROM and PBUF_REF type buffers cannot have their sizes increased, so\r
+ * the call will fail. A check is made that the increase in header size does\r
+ * not move the payload pointer in front of the start of the buffer.\r
+ * @return non-zero on failure, zero on success.\r
+ *\r
+ */\r
+u8_t\r
+pbuf_header(struct pbuf *p, s16_t header_size_increment)\r
+{\r
+ void *payload;\r
+\r
+ LWIP_ASSERT("p != NULL", p != NULL);\r
+ if ((header_size_increment == 0) || (p == NULL)) return 0;\r
+ \r
+ /* remember current payload pointer */\r
+ payload = p->payload;\r
+\r
+ /* pbuf types containing payloads? */\r
+ if (p->flags == PBUF_FLAG_RAM || p->flags == PBUF_FLAG_POOL) {\r
+ /* set new payload pointer */\r
+ p->payload = (u8_t *)p->payload - header_size_increment;\r
+ /* boundary check fails? */\r
+ if ((u8_t *)p->payload < (u8_t *)p + sizeof(struct pbuf)) {\r
+ LWIP_DEBUGF( PBUF_DEBUG | 2, ("pbuf_header: failed as %p < %p (not enough space for new header size)\n",\r
+ (void *)p->payload,\r
+ (void *)(p + 1)));\\r
+ /* restore old payload pointer */\r
+ p->payload = payload;\r
+ /* bail out unsuccesfully */\r
+ return 1;\r
+ }\r
+ /* pbuf types refering to external payloads? */\r
+ } else if (p->flags == PBUF_FLAG_REF || p->flags == PBUF_FLAG_ROM) {\r
+ /* hide a header in the payload? */\r
+ if ((header_size_increment < 0) && (header_size_increment - p->len <= 0)) {\r
+ /* increase payload pointer */\r
+ p->payload = (u8_t *)p->payload - header_size_increment;\r
+ } else {\r
+ /* cannot expand payload to front (yet!)\r
+ * bail out unsuccesfully */\r
+ return 1;\r
+ }\r
+ }\r
+ /* modify pbuf length fields */\r
+ p->len += header_size_increment;\r
+ p->tot_len += header_size_increment;\r
+\r
+ LWIP_DEBUGF( PBUF_DEBUG, ("pbuf_header: old %p new %p (%d)\n",\r
+ (void *)payload, (void *)p->payload, header_size_increment));\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * Dereference a pbuf chain or queue and deallocate any no-longer-used\r
+ * pbufs at the head of this chain or queue.\r
+ *\r
+ * Decrements the pbuf reference count. If it reaches zero, the pbuf is\r
+ * deallocated.\r
+ *\r
+ * For a pbuf chain, this is repeated for each pbuf in the chain,\r
+ * up to the first pbuf which has a non-zero reference count after\r
+ * decrementing. So, when all reference counts are one, the whole\r
+ * chain is free'd.\r
+ *\r
+ * @param pbuf The pbuf (chain) to be dereferenced.\r
+ *\r
+ * @return the number of pbufs that were de-allocated\r
+ * from the head of the chain.\r
+ *\r
+ * @note MUST NOT be called on a packet queue (Not verified to work yet).\r
+ * @note the reference counter of a pbuf equals the number of pointers\r
+ * that refer to the pbuf (or into the pbuf).\r
+ *\r
+ * @internal examples:\r
+ *\r
+ * Assuming existing chains a->b->c with the following reference\r
+ * counts, calling pbuf_free(a) results in:\r
+ * \r
+ * 1->2->3 becomes ...1->3\r
+ * 3->3->3 becomes 2->3->3\r
+ * 1->1->2 becomes ......1\r
+ * 2->1->1 becomes 1->1->1\r
+ * 1->1->1 becomes .......\r
+ *\r
+ */\r
+u8_t\r
+pbuf_free(struct pbuf *p)\r
+{\r
+ struct pbuf *q;\r
+ u8_t count;\r
+ SYS_ARCH_DECL_PROTECT(old_level);\r
+\r
+ LWIP_ASSERT("p != NULL", p != NULL);\r
+ /* if assertions are disabled, proceed with debug output */\r
+ if (p == NULL) {\r
+ LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_free(p == NULL) was called.\n"));\r
+ return 0;\r
+ }\r
+ LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_free(%p)\n", (void *)p));\r
+\r
+ PERF_START;\r
+\r
+ LWIP_ASSERT("pbuf_free: sane flags",\r
+ p->flags == PBUF_FLAG_RAM || p->flags == PBUF_FLAG_ROM ||\r
+ p->flags == PBUF_FLAG_REF || p->flags == PBUF_FLAG_POOL);\r
+\r
+ count = 0;\r
+ /* Since decrementing ref cannot be guaranteed to be a single machine operation\r
+ * we must protect it. Also, the later test of ref must be protected.\r
+ */\r
+ SYS_ARCH_PROTECT(old_level);\r
+ /* de-allocate all consecutive pbufs from the head of the chain that\r
+ * obtain a zero reference count after decrementing*/\r
+ while (p != NULL) {\r
+ /* all pbufs in a chain are referenced at least once */\r
+ LWIP_ASSERT("pbuf_free: p->ref > 0", p->ref > 0);\r
+ /* decrease reference count (number of pointers to pbuf) */\r
+ p->ref--;\r
+ /* this pbuf is no longer referenced to? */\r
+ if (p->ref == 0) {\r
+ /* remember next pbuf in chain for next iteration */\r
+ q = p->next;\r
+ LWIP_DEBUGF( PBUF_DEBUG | 2, ("pbuf_free: deallocating %p\n", (void *)p));\r
+ /* is this a pbuf from the pool? */\r
+ if (p->flags == PBUF_FLAG_POOL) {\r
+ p->len = p->tot_len = PBUF_POOL_BUFSIZE;\r
+ p->payload = (void *)((u8_t *)p + sizeof(struct pbuf));\r
+ PBUF_POOL_FREE(p);\r
+ /* is this a ROM or RAM referencing pbuf? */\r
+ } else if (p->flags == PBUF_FLAG_ROM || p->flags == PBUF_FLAG_REF) {\r
+ memp_free(MEMP_PBUF, p);\r
+ /* p->flags == PBUF_FLAG_RAM */\r
+ } else {\r
+ mem_free(p);\r
+ }\r
+ count++;\r
+ /* proceed to next pbuf */\r
+ p = q;\r
+ /* p->ref > 0, this pbuf is still referenced to */\r
+ /* (and so the remaining pbufs in chain as well) */\r
+ } else {\r
+ LWIP_DEBUGF( PBUF_DEBUG | 2, ("pbuf_free: %p has ref %u, ending here.\n", (void *)p, (unsigned int)p->ref));\r
+ /* stop walking through the chain */\r
+ p = NULL;\r
+ }\r
+ }\r
+ SYS_ARCH_UNPROTECT(old_level);\r
+ PERF_STOP("pbuf_free");\r
+ /* return number of de-allocated pbufs */\r
+ return count;\r
+}\r
+\r
+/**\r
+ * Count number of pbufs in a chain\r
+ *\r
+ * @param p first pbuf of chain\r
+ * @return the number of pbufs in a chain\r
+ */\r
+\r
+u8_t\r
+pbuf_clen(struct pbuf *p)\r
+{\r
+ u8_t len;\r
+\r
+ len = 0;\r
+ while (p != NULL) {\r
+ ++len;\r
+ p = p->next;\r
+ }\r
+ return len;\r
+}\r
+\r
+/**\r
+ * Increment the reference count of the pbuf.\r
+ *\r
+ * @param p pbuf to increase reference counter of\r
+ *\r
+ */\r
+void\r
+pbuf_ref(struct pbuf *p)\r
+{\r
+ SYS_ARCH_DECL_PROTECT(old_level);\r
+ /* pbuf given? */\r
+ if (p != NULL) {\r
+ SYS_ARCH_PROTECT(old_level);\r
+ ++(p->ref);\r
+ SYS_ARCH_UNPROTECT(old_level);\r
+ }\r
+}\r
+\r
+/**\r
+ * Concatenate two pbufs (each may be a pbuf chain) and take over\r
+ * the caller's reference of the tail pbuf.\r
+ * \r
+ * @note The caller MAY NOT reference the tail pbuf afterwards.\r
+ * Use pbuf_chain() for that purpose.\r
+ * \r
+ * @see pbuf_chain()\r
+ */\r
+\r
+void\r
+pbuf_cat(struct pbuf *h, struct pbuf *t)\r
+{\r
+ struct pbuf *p;\r
+\r
+ LWIP_ASSERT("h != NULL (programmer violates API)", h != NULL);\r
+ LWIP_ASSERT("t != NULL (programmer violates API)", t != NULL);\r
+ if ((h == NULL) || (t == NULL)) return;\r
+\r
+ /* proceed to last pbuf of chain */\r
+ for (p = h; p->next != NULL; p = p->next) {\r
+ /* add total length of second chain to all totals of first chain */\r
+ p->tot_len += t->tot_len;\r
+ }\r
+ /* { p is last pbuf of first h chain, p->next == NULL } */\r
+ LWIP_ASSERT("p->tot_len == p->len (of last pbuf in chain)", p->tot_len == p->len);\r
+ LWIP_ASSERT("p->next == NULL", p->next == NULL);\r
+ /* add total length of second chain to last pbuf total of first chain */\r
+ p->tot_len += t->tot_len;\r
+ /* chain last pbuf of head (p) with first of tail (t) */\r
+ p->next = t;\r
+ /* p->next now references t, but the caller will drop its reference to t,\r
+ * so netto there is no change to the reference count of t.\r
+ */\r
+}\r
+\r
+/**\r
+ * Chain two pbufs (or pbuf chains) together.\r
+ * \r
+ * The caller MUST call pbuf_free(t) once it has stopped\r
+ * using it. Use pbuf_cat() instead if you no longer use t.\r
+ * \r
+ * @param h head pbuf (chain)\r
+ * @param t tail pbuf (chain)\r
+ * @note The pbufs MUST belong to the same packet.\r
+ * @note MAY NOT be called on a packet queue.\r
+ *\r
+ * The ->tot_len fields of all pbufs of the head chain are adjusted.\r
+ * The ->next field of the last pbuf of the head chain is adjusted.\r
+ * The ->ref field of the first pbuf of the tail chain is adjusted.\r
+ *\r
+ */\r
+void\r
+pbuf_chain(struct pbuf *h, struct pbuf *t)\r
+{\r
+ pbuf_cat(h, t);\r
+ /* t is now referenced by h */\r
+ pbuf_ref(t);\r
+ LWIP_DEBUGF(PBUF_DEBUG | DBG_FRESH | 2, ("pbuf_chain: %p references %p\n", (void *)h, (void *)t));\r
+}\r
+\r
+/* For packet queueing. Note that queued packets MUST be dequeued first\r
+ * using pbuf_dequeue() before calling other pbuf_() functions. */\r
+#if ARP_QUEUEING\r
+/**\r
+ * Add a packet to the end of a queue.\r
+ *\r
+ * @param q pointer to first packet on the queue\r
+ * @param n packet to be queued\r
+ *\r
+ * Both packets MUST be given, and must be different.\r
+ */\r
+void\r
+pbuf_queue(struct pbuf *p, struct pbuf *n)\r
+{\r
+#if PBUF_DEBUG /* remember head of queue */\r
+ struct pbuf *q = p;\r
+#endif\r
+ /* programmer stupidity checks */\r
+ LWIP_ASSERT("p == NULL in pbuf_queue: this indicates a programmer error\n", p != NULL);\r
+ LWIP_ASSERT("n == NULL in pbuf_queue: this indicates a programmer error\n", n != NULL);\r
+ LWIP_ASSERT("p == n in pbuf_queue: this indicates a programmer error\n", p != n);\r
+ if ((p == NULL) || (n == NULL) || (p == n)){\r
+ LWIP_DEBUGF(PBUF_DEBUG | DBG_HALT | 3, ("pbuf_queue: programmer argument error\n"))\r
+ return;\r
+ }\r
+\r
+ /* iterate through all packets on queue */\r
+ while (p->next != NULL) {\r
+/* be very picky about pbuf chain correctness */\r
+#if PBUF_DEBUG\r
+ /* iterate through all pbufs in packet */\r
+ while (p->tot_len != p->len) {\r
+ /* make sure invariant condition holds */\r
+ LWIP_ASSERT("p->len < p->tot_len", p->len < p->tot_len);\r
+ /* make sure each packet is complete */\r
+ LWIP_ASSERT("p->next != NULL", p->next != NULL);\r
+ p = p->next;\r
+ /* { p->tot_len == p->len => p is last pbuf of a packet } */\r
+ }\r
+ /* { p is last pbuf of a packet } */\r
+ /* proceed to next packet on queue */\r
+#endif\r
+ /* proceed to next pbuf */\r
+ if (p->next != NULL) p = p->next;\r
+ }\r
+ /* { p->tot_len == p->len and p->next == NULL } ==>\r
+ * { p is last pbuf of last packet on queue } */\r
+ /* chain last pbuf of queue with n */\r
+ p->next = n;\r
+ /* n is now referenced to by the (packet p in the) queue */\r
+ pbuf_ref(n);\r
+#if PBUF_DEBUG\r
+ LWIP_DEBUGF(PBUF_DEBUG | DBG_FRESH | 2,\r
+ ("pbuf_queue: newly queued packet %p sits after packet %p in queue %p\n",\r
+ (void *)n, (void *)p, (void *)q));\r
+#endif\r
+}\r
+\r
+/**\r
+ * Remove a packet from the head of a queue.\r
+ *\r
+ * The caller MUST reference the remainder of the queue (as returned). The\r
+ * caller MUST NOT call pbuf_ref() as it implicitly takes over the reference\r
+ * from p.\r
+ * \r
+ * @param p pointer to first packet on the queue which will be dequeued.\r
+ * @return first packet on the remaining queue (NULL if no further packets).\r
+ *\r
+ */\r
+struct pbuf *\r
+pbuf_dequeue(struct pbuf *p)\r
+{\r
+ struct pbuf *q;\r
+ LWIP_ASSERT("p != NULL", p != NULL);\r
+\r
+ /* iterate through all pbufs in packet p */\r
+ while (p->tot_len != p->len) {\r
+ /* make sure invariant condition holds */\r
+ LWIP_ASSERT("p->len < p->tot_len", p->len < p->tot_len);\r
+ /* make sure each packet is complete */\r
+ LWIP_ASSERT("p->next != NULL", p->next != NULL);\r
+ p = p->next;\r
+ }\r
+ /* { p->tot_len == p->len } => p is the last pbuf of the first packet */\r
+ /* remember next packet on queue in q */\r
+ q = p->next;\r
+ /* dequeue packet p from queue */\r
+ p->next = NULL;\r
+ /* any next packet on queue? */\r
+ if (q != NULL) {\r
+ /* although q is no longer referenced by p, it MUST be referenced by\r
+ * the caller, who is maintaining this packet queue. So, we do not call\r
+ * pbuf_free(q) here, resulting in an implicit pbuf_ref(q) for the caller. */\r
+ LWIP_DEBUGF(PBUF_DEBUG | DBG_FRESH | 2, ("pbuf_dequeue: first remaining packet on queue is %p\n", (void *)q));\r
+ } else {\r
+ LWIP_DEBUGF(PBUF_DEBUG | DBG_FRESH | 2, ("pbuf_dequeue: no further packets on queue\n"));\r
+ }\r
+ return q;\r
+}\r
+#endif\r
+\r
+/**\r
+ *\r
+ * Create PBUF_POOL (or PBUF_RAM) copies of PBUF_REF pbufs.\r
+ *\r
+ * Used to queue packets on behalf of the lwIP stack, such as\r
+ * ARP based queueing.\r
+ *\r
+ * Go through a pbuf chain and replace any PBUF_REF buffers\r
+ * with PBUF_POOL (or PBUF_RAM) pbufs, each taking a copy of\r
+ * the referenced data.\r
+ *\r
+ * @note You MUST explicitly use p = pbuf_take(p);\r
+ * The pbuf you give as argument, may have been replaced\r
+ * by a (differently located) copy through pbuf_take()!\r
+ *\r
+ * @note Any replaced pbufs will be freed through pbuf_free().\r
+ * This may deallocate them if they become no longer referenced.\r
+ *\r
+ * @param p Head of pbuf chain to process\r
+ *\r
+ * @return Pointer to head of pbuf chain\r
+ */\r
+struct pbuf *\r
+pbuf_take(struct pbuf *p)\r
+{\r
+ struct pbuf *q , *prev, *head;\r
+ LWIP_ASSERT("pbuf_take: p != NULL\n", p != NULL);\r
+ LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_take(%p)\n", (void*)p));\r
+\r
+ prev = NULL;\r
+ head = p;\r
+ /* iterate through pbuf chain */\r
+ do\r
+ {\r
+ /* pbuf is of type PBUF_REF? */\r
+ if (p->flags == PBUF_FLAG_REF) {\r
+ LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE, ("pbuf_take: encountered PBUF_REF %p\n", (void *)p));\r
+ /* allocate a pbuf (w/ payload) fully in RAM */\r
+ /* PBUF_POOL buffers are faster if we can use them */\r
+ if (p->len <= PBUF_POOL_BUFSIZE) {\r
+ q = pbuf_alloc(PBUF_RAW, p->len, PBUF_POOL);\r
+ if (q == NULL) {\r
+ LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_take: Could not allocate PBUF_POOL\n"));\r
+ }\r
+ } else {\r
+ /* no replacement pbuf yet */\r
+ q = NULL;\r
+ LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_take: PBUF_POOL too small to replace PBUF_REF\n"));\r
+ }\r
+ /* no (large enough) PBUF_POOL was available? retry with PBUF_RAM */\r
+ if (q == NULL) {\r
+ q = pbuf_alloc(PBUF_RAW, p->len, PBUF_RAM);\r
+ if (q == NULL) {\r
+ LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_take: Could not allocate PBUF_RAM\n"));\r
+ }\r
+ }\r
+ /* replacement pbuf could be allocated? */\r
+ if (q != NULL)\r
+ {\r
+ /* copy p to q */\r
+ /* copy successor */\r
+ q->next = p->next;\r
+ /* remove linkage from original pbuf */\r
+ p->next = NULL;\r
+ /* remove linkage to original pbuf */\r
+ if (prev != NULL) {\r
+ /* prev->next == p at this point */\r
+ LWIP_ASSERT("prev->next == p", prev->next == p);\r
+ /* break chain and insert new pbuf instead */\r
+ prev->next = q;\r
+ /* prev == NULL, so we replaced the head pbuf of the chain */\r
+ } else {\r
+ head = q;\r
+ }\r
+ /* copy pbuf payload */\r
+ memcpy(q->payload, p->payload, p->len);\r
+ q->tot_len = p->tot_len;\r
+ q->len = p->len;\r
+ /* in case p was the first pbuf, it is no longer refered to by\r
+ * our caller, as the caller MUST do p = pbuf_take(p);\r
+ * in case p was not the first pbuf, it is no longer refered to\r
+ * by prev. we can safely free the pbuf here.\r
+ * (note that we have set p->next to NULL already so that\r
+ * we will not free the rest of the chain by accident.)\r
+ */\r
+ pbuf_free(p);\r
+ /* do not copy ref, since someone else might be using the old buffer */\r
+ LWIP_DEBUGF(PBUF_DEBUG, ("pbuf_take: replaced PBUF_REF %p with %p\n", (void *)p, (void *)q));\r
+ p = q;\r
+ } else {\r
+ /* deallocate chain */\r
+ pbuf_free(head);\r
+ LWIP_DEBUGF(PBUF_DEBUG | 2, ("pbuf_take: failed to allocate replacement pbuf for %p\n", (void *)p));\r
+ return NULL;\r
+ }\r
+ /* p->flags != PBUF_FLAG_REF */\r
+ } else {\r
+ LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 1, ("pbuf_take: skipping pbuf not of type PBUF_REF\n"));\r
+ }\r
+ /* remember this pbuf */\r
+ prev = p;\r
+ /* proceed to next pbuf in original chain */\r
+ p = p->next;\r
+ } while (p);\r
+ LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 1, ("pbuf_take: end of chain reached.\n"));\r
+\r
+ return head;\r
+}\r
+\r
+/**\r
+ * Dechains the first pbuf from its succeeding pbufs in the chain.\r
+ *\r
+ * Makes p->tot_len field equal to p->len.\r
+ * @param p pbuf to dechain\r
+ * @return remainder of the pbuf chain, or NULL if it was de-allocated.\r
+ * @note May not be called on a packet queue.\r
+ */\r
+struct pbuf *\r
+pbuf_dechain(struct pbuf *p)\r
+{\r
+ struct pbuf *q;\r
+ u8_t tail_gone = 1;\r
+ /* tail */\r
+ q = p->next;\r
+ /* pbuf has successor in chain? */\r
+ if (q != NULL) {\r
+ /* assert tot_len invariant: (p->tot_len == p->len + (p->next? p->next->tot_len: 0) */\r
+ LWIP_ASSERT("p->tot_len == p->len + q->tot_len", q->tot_len == p->tot_len - p->len);\r
+ /* enforce invariant if assertion is disabled */\r
+ q->tot_len = p->tot_len - p->len;\r
+ /* decouple pbuf from remainder */\r
+ p->next = NULL;\r
+ /* total length of pbuf p is its own length only */\r
+ p->tot_len = p->len;\r
+ /* q is no longer referenced by p, free it */\r
+ LWIP_DEBUGF(PBUF_DEBUG | DBG_STATE, ("pbuf_dechain: unreferencing %p\n", (void *)q));\r
+ tail_gone = pbuf_free(q);\r
+ if (tail_gone > 0) {\r
+ LWIP_DEBUGF(PBUF_DEBUG | DBG_STATE,\r
+ ("pbuf_dechain: deallocated %p (as it is no longer referenced)\n", (void *)q));\r
+ }\r
+ /* return remaining tail or NULL if deallocated */\r
+ }\r
+ /* assert tot_len invariant: (p->tot_len == p->len + (p->next? p->next->tot_len: 0) */\r
+ LWIP_ASSERT("p->tot_len == p->len", p->tot_len == p->len);\r
+ return (tail_gone > 0? NULL: q);\r
+}\r
--- /dev/null
+/**\r
+ * @file\r
+ * \r
+ * Implementation of raw protocol PCBs for low-level handling of\r
+ * different types of protocols besides (or overriding) those\r
+ * already available in lwIP.\r
+ *\r
+ */\r
+/*\r
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. The name of the author may not be used to endorse or promote products\r
+ * derived from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT\r
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT\r
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING\r
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY\r
+ * OF SUCH DAMAGE.\r
+ *\r
+ * This file is part of the lwIP TCP/IP stack.\r
+ *\r
+ * Author: Adam Dunkels <adam@sics.se>\r
+ *\r
+ */\r
+\r
+#include <string.h>\r
+\r
+#include "lwip/opt.h"\r
+\r
+#include "lwip/def.h"\r
+#include "lwip/memp.h"\r
+#include "lwip/inet.h"\r
+#include "lwip/ip_addr.h"\r
+#include "lwip/netif.h"\r
+#include "lwip/raw.h"\r
+\r
+#include "lwip/stats.h"\r
+\r
+#include "arch/perf.h"\r
+#include "lwip/snmp.h"\r
+\r
+#if LWIP_RAW\r
+\r
+/** The list of RAW PCBs */\r
+static struct raw_pcb *raw_pcbs = NULL;\r
+\r
+void\r
+raw_init(void)\r
+{\r
+ raw_pcbs = NULL;\r
+}\r
+\r
+/**\r
+ * Determine if in incoming IP packet is covered by a RAW PCB\r
+ * and if so, pass it to a user-provided receive callback function.\r
+ *\r
+ * Given an incoming IP datagram (as a chain of pbufs) this function\r
+ * finds a corresponding RAW PCB and calls the corresponding receive\r
+ * callback function.\r
+ *\r
+ * @param pbuf pbuf to be demultiplexed to a RAW PCB.\r
+ * @param netif network interface on which the datagram was received.\r
+ * @Return - 1 if the packet has been eaten by a RAW PCB receive\r
+ * callback function. The caller MAY NOT not reference the\r
+ * packet any longer, and MAY NOT call pbuf_free().\r
+ * @return - 0 if packet is not eaten (pbuf is still referenced by the\r
+ * caller).\r
+ *\r
+ */\r
+u8_t\r
+raw_input(struct pbuf *p, struct netif *inp)\r
+{\r
+ struct raw_pcb *pcb;\r
+ struct ip_hdr *iphdr;\r
+ int proto;\r
+ u8_t eaten = 0;\r
+\r
+ ( void ) inp;\r
+\r
+ iphdr = p->payload;\r
+ proto = IPH_PROTO(iphdr);\r
+\r
+ pcb = raw_pcbs;\r
+ /* loop through all raw pcbs until the packet is eaten by one */\r
+ /* this allows multiple pcbs to match against the packet by design */\r
+ while ((eaten == 0) && (pcb != NULL)) {\r
+ if (pcb->protocol == proto) {\r
+ /* receive callback function available? */\r
+ if (pcb->recv != NULL) {\r
+ /* the receive callback function did not eat the packet? */\r
+ if (pcb->recv(pcb->recv_arg, pcb, p, &(iphdr->src)) != 0)\r
+ {\r
+ /* receive function ate the packet */\r
+ p = NULL;\r
+ eaten = 1;\r
+ }\r
+ }\r
+ /* no receive callback function was set for this raw PCB */\r
+ /* drop the packet */\r
+ }\r
+ pcb = pcb->next;\r
+ }\r
+ return eaten;\r
+}\r
+\r
+/**\r
+ * Bind a RAW PCB.\r
+ *\r
+ * @param pcb RAW PCB to be bound with a local address ipaddr.\r
+ * @param ipaddr local IP address to bind with. Use IP_ADDR_ANY to\r
+ * bind to all local interfaces.\r
+ *\r
+ * @return lwIP error code.\r
+ * - ERR_OK. Successful. No error occured.\r
+ * - ERR_USE. The specified IP address is already bound to by\r
+ * another RAW PCB.\r
+ *\r
+ * @see raw_disconnect()\r
+ */\r
+err_t\r
+raw_bind(struct raw_pcb *pcb, struct ip_addr *ipaddr)\r
+{\r
+ ip_addr_set(&pcb->local_ip, ipaddr);\r
+ return ERR_OK;\r
+}\r
+\r
+/**\r
+ * Connect an RAW PCB. This function is required by upper layers\r
+ * of lwip. Using the raw api you could use raw_sendto() instead\r
+ *\r
+ * This will associate the RAW PCB with the remote address.\r
+ *\r
+ * @param pcb RAW PCB to be connected with remote address ipaddr and port.\r
+ * @param ipaddr remote IP address to connect with.\r
+ *\r
+ * @return lwIP error code\r
+ *\r
+ * @see raw_disconnect() and raw_sendto()\r
+ */\r
+err_t\r
+raw_connect(struct raw_pcb *pcb, struct ip_addr *ipaddr)\r
+{\r
+ ip_addr_set(&pcb->remote_ip, ipaddr);\r
+ return ERR_OK;\r
+}\r
+\r
+\r
+/**\r
+ * Set the callback function for received packets that match the\r
+ * raw PCB's protocol and binding. \r
+ * \r
+ * The callback function MUST either\r
+ * - eat the packet by calling pbuf_free() and returning non-zero. The\r
+ * packet will not be passed to other raw PCBs or other protocol layers.\r
+ * - not free the packet, and return zero. The packet will be matched\r
+ * against further PCBs and/or forwarded to another protocol layers.\r
+ * \r
+ * @return non-zero if the packet was free()d, zero if the packet remains\r
+ * available for others.\r
+ */\r
+void\r
+raw_recv(struct raw_pcb *pcb,\r
+ u8_t (* recv)(void *arg, struct raw_pcb *upcb, struct pbuf *p,\r
+ struct ip_addr *addr),\r
+ void *recv_arg)\r
+{\r
+ /* remember recv() callback and user data */\r
+ pcb->recv = recv;\r
+ pcb->recv_arg = recv_arg;\r
+}\r
+\r
+/**\r
+ * Send the raw IP packet to the given address. Note that actually you cannot\r
+ * modify the IP headers (this is inconsistent with the receive callback where\r
+ * you actually get the IP headers), you can only specify the IP payload here.\r
+ * It requires some more changes in lwIP. (there will be a raw_send() function\r
+ * then.)\r
+ *\r
+ * @param pcb the raw pcb which to send\r
+ * @param p the IP payload to send\r
+ * @param ipaddr the destination address of the IP packet\r
+ *\r
+ */\r
+err_t\r
+raw_sendto(struct raw_pcb *pcb, struct pbuf *p, struct ip_addr *ipaddr)\r
+{\r
+ err_t err;\r
+ struct netif *netif;\r
+ struct ip_addr *src_ip;\r
+ struct pbuf *q; /* q will be sent down the stack */\r
+ \r
+ LWIP_DEBUGF(RAW_DEBUG | DBG_TRACE | 3, ("raw_sendto\n"));\r
+ \r
+ /* not enough space to add an IP header to first pbuf in given p chain? */\r
+ if (pbuf_header(p, IP_HLEN)) {\r
+ /* allocate header in new pbuf */\r
+ q = pbuf_alloc(PBUF_IP, 0, PBUF_RAM);\r
+ /* new header pbuf could not be allocated? */\r
+ if (q == NULL) {\r
+ LWIP_DEBUGF(RAW_DEBUG | DBG_TRACE | 2, ("raw_sendto: could not allocate header\n"));\r
+ return ERR_MEM;\r
+ }\r
+ /* chain header q in front of given pbuf p */\r
+ pbuf_chain(q, p);\r
+ /* { first pbuf q points to header pbuf } */\r
+ LWIP_DEBUGF(RAW_DEBUG, ("raw_sendto: added header pbuf %p before given pbuf %p\n", (void *)q, (void *)p));\r
+ } else {\r
+ /* first pbuf q equals given pbuf */\r
+ q = p;\r
+ pbuf_header(q, -IP_HLEN);\r
+ }\r
+ \r
+ if ((netif = ip_route(ipaddr)) == NULL) {\r
+ LWIP_DEBUGF(RAW_DEBUG | 1, ("raw_sendto: No route to 0x%lx\n", ipaddr->addr));\r
+#if RAW_STATS\r
+ /* ++lwip_stats.raw.rterr;*/\r
+#endif /* RAW_STATS */\r
+ /* free any temporary header pbuf allocated by pbuf_header() */\r
+ if (q != p) {\r
+ pbuf_free(q);\r
+ }\r
+ return ERR_RTE;\r
+ }\r
+\r
+ if (ip_addr_isany(&pcb->local_ip)) {\r
+ /* use outgoing network interface IP address as source address */\r
+ src_ip = &(netif->ip_addr);\r
+ } else {\r
+ /* use RAW PCB local IP address as source address */\r
+ src_ip = &(pcb->local_ip);\r
+ }\r
+\r
+ err = ip_output_if (q, src_ip, ipaddr, pcb->ttl, pcb->tos, pcb->protocol, netif);\r
+\r
+ /* did we chain a header earlier? */\r
+ if (q != p) {\r
+ /* free the header */\r
+ pbuf_free(q);\r
+ }\r
+ return err;\r
+}\r
+\r
+/**\r
+ * Send the raw IP packet to the address given by raw_connect()\r
+ *\r
+ * @param pcb the raw pcb which to send\r
+ * @param p the IP payload to send\r
+ * @param ipaddr the destination address of the IP packet\r
+ *\r
+ */\r
+err_t\r
+raw_send(struct raw_pcb *pcb, struct pbuf *p)\r
+{\r
+ return raw_sendto(pcb, p, &pcb->remote_ip);\r
+}\r
+\r
+/**\r
+ * Remove an RAW PCB.\r
+ *\r
+ * @param pcb RAW PCB to be removed. The PCB is removed from the list of\r
+ * RAW PCB's and the data structure is freed from memory.\r
+ *\r
+ * @see raw_new()\r
+ */\r
+void\r
+raw_remove(struct raw_pcb *pcb)\r
+{\r
+ struct raw_pcb *pcb2;\r
+ /* pcb to be removed is first in list? */\r
+ if (raw_pcbs == pcb) {\r
+ /* make list start at 2nd pcb */\r
+ raw_pcbs = raw_pcbs->next;\r
+ /* pcb not 1st in list */\r
+ } else for(pcb2 = raw_pcbs; pcb2 != NULL; pcb2 = pcb2->next) {\r
+ /* find pcb in raw_pcbs list */\r
+ if (pcb2->next != NULL && pcb2->next == pcb) {\r
+ /* remove pcb from list */\r
+ pcb2->next = pcb->next;\r
+ }\r
+ }\r
+ memp_free(MEMP_RAW_PCB, pcb);\r
+}\r
+\r
+/**\r
+ * Create a RAW PCB.\r
+ *\r
+ * @return The RAW PCB which was created. NULL if the PCB data structure\r
+ * could not be allocated.\r
+ *\r
+ * @param proto the protocol number of the IPs payload (e.g. IP_PROTO_ICMP)\r
+ *\r
+ * @see raw_remove()\r
+ */\r
+struct raw_pcb *\r
+raw_new(u16_t proto) {\r
+ struct raw_pcb *pcb;\r
+\r
+ LWIP_DEBUGF(RAW_DEBUG | DBG_TRACE | 3, ("raw_new\n"));\r
+\r
+ pcb = memp_malloc(MEMP_RAW_PCB);\r
+ /* could allocate RAW PCB? */\r
+ if (pcb != NULL) {\r
+ /* initialize PCB to all zeroes */\r
+ memset(pcb, 0, sizeof(struct raw_pcb));\r
+ pcb->protocol = proto;\r
+ pcb->ttl = RAW_TTL;\r
+ pcb->next = raw_pcbs;\r
+ raw_pcbs = pcb;\r
+ }\r
+ return pcb;\r
+}\r
+\r
+#endif /* LWIP_RAW */\r
--- /dev/null
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+#include <string.h>
+
+#include "lwip/opt.h"
+
+#include "lwip/def.h"
+
+#include "lwip/stats.h"
+#include "lwip/mem.h"
+
+
+#if LWIP_STATS
+struct stats_ lwip_stats;
+
+void
+stats_init(void)
+{
+ memset(&lwip_stats, 0, sizeof(struct stats_));
+}
+#if LWIP_STATS_DISPLAY
+void
+stats_display_proto(struct stats_proto *proto, char *name)
+{
+ LWIP_PLATFORM_DIAG(("\n%s\n\t", name));
+ LWIP_PLATFORM_DIAG(("xmit: %d\n\t", proto->xmit));
+ LWIP_PLATFORM_DIAG(("rexmit: %d\n\t", proto->rexmit));
+ LWIP_PLATFORM_DIAG(("recv: %d\n\t", proto->recv));
+ LWIP_PLATFORM_DIAG(("fw: %d\n\t", proto->fw));
+ LWIP_PLATFORM_DIAG(("drop: %d\n\t", proto->drop));
+ LWIP_PLATFORM_DIAG(("chkerr: %d\n\t", proto->chkerr));
+ LWIP_PLATFORM_DIAG(("lenerr: %d\n\t", proto->lenerr));
+ LWIP_PLATFORM_DIAG(("memerr: %d\n\t", proto->memerr));
+ LWIP_PLATFORM_DIAG(("rterr: %d\n\t", proto->rterr));
+ LWIP_PLATFORM_DIAG(("proterr: %d\n\t", proto->proterr));
+ LWIP_PLATFORM_DIAG(("opterr: %d\n\t", proto->opterr));
+ LWIP_PLATFORM_DIAG(("err: %d\n\t", proto->err));
+ LWIP_PLATFORM_DIAG(("cachehit: %d\n", proto->cachehit));
+}
+
+void
+stats_display_pbuf(struct stats_pbuf *pbuf)
+{
+ LWIP_PLATFORM_DIAG(("\nPBUF\n\t"));
+ LWIP_PLATFORM_DIAG(("avail: %d\n\t", pbuf->avail));
+ LWIP_PLATFORM_DIAG(("used: %d\n\t", pbuf->used));
+ LWIP_PLATFORM_DIAG(("max: %d\n\t", pbuf->max));
+ LWIP_PLATFORM_DIAG(("err: %d\n\t", pbuf->err));
+ LWIP_PLATFORM_DIAG(("alloc_locked: %d\n\t", pbuf->alloc_locked));
+ LWIP_PLATFORM_DIAG(("refresh_locked: %d\n", pbuf->refresh_locked));
+}
+
+void
+stats_display_mem(struct stats_mem *mem, char *name)
+{
+ LWIP_PLATFORM_DIAG(("\n MEM %s\n\t", name));
+ LWIP_PLATFORM_DIAG(("avail: %d\n\t", mem->avail));
+ LWIP_PLATFORM_DIAG(("used: %d\n\t", mem->used));
+ LWIP_PLATFORM_DIAG(("max: %d\n\t", mem->max));
+ LWIP_PLATFORM_DIAG(("err: %d\n", mem->err));
+
+}
+
+void
+stats_display(void)
+{
+ int i;
+ char * memp_names[] = {"PBUF", "RAW_PCB", "UDP_PCB", "TCP_PCB", "TCP_PCB_LISTEN",
+ "TCP_SEG", "NETBUF", "NETCONN", "API_MSG", "TCP_MSG", "TIMEOUT"};
+ stats_display_proto(&lwip_stats.link, "LINK");
+ stats_display_proto(&lwip_stats.ip_frag, "IP_FRAG");
+ stats_display_proto(&lwip_stats.ip, "IP");
+ stats_display_proto(&lwip_stats.icmp, "ICMP");
+ stats_display_proto(&lwip_stats.udp, "UDP");
+ stats_display_proto(&lwip_stats.tcp, "TCP");
+ stats_display_pbuf(&lwip_stats.pbuf);
+ stats_display_mem(&lwip_stats.mem, "HEAP");
+ for (i = 0; i < MEMP_MAX; i++) {
+ stats_display_mem(&lwip_stats.memp[i], memp_names[i]);
+ }
+
+}
+#endif /* LWIP_STATS_DISPLAY */
+#endif /* LWIP_STATS */
+
--- /dev/null
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+#include "lwip/sys.h"
+#include "lwip/opt.h"
+#include "lwip/def.h"
+#include "lwip/memp.h"
+
+#if (NO_SYS == 0)
+
+struct sswt_cb
+{
+ int timeflag;
+ sys_sem_t *psem;
+};
+
+
+
+void
+sys_mbox_fetch(sys_mbox_t mbox, void **msg)
+{
+ u32_t time;
+ struct sys_timeouts *timeouts;
+ struct sys_timeout *tmptimeout;
+ sys_timeout_handler h;
+ void *arg;
+
+
+ again:
+ timeouts = sys_arch_timeouts();
+
+ if (!timeouts || !timeouts->next) {
+ sys_arch_mbox_fetch(mbox, msg, 0);
+ } else {
+ if (timeouts->next->time > 0) {
+ time = sys_arch_mbox_fetch(mbox, msg, timeouts->next->time);
+ } else {
+ time = SYS_ARCH_TIMEOUT;
+ }
+
+ if (time == SYS_ARCH_TIMEOUT) {
+ /* If time == SYS_ARCH_TIMEOUT, a timeout occured before a message
+ could be fetched. We should now call the timeout handler and
+ deallocate the memory allocated for the timeout. */
+ tmptimeout = timeouts->next;
+ timeouts->next = tmptimeout->next;
+ h = tmptimeout->h;
+ arg = tmptimeout->arg;
+ memp_free(MEMP_SYS_TIMEOUT, tmptimeout);
+ if (h != NULL) {
+ LWIP_DEBUGF(SYS_DEBUG, ("smf calling h=%p(%p)\n", (void *)h, (void *)arg));
+ h(arg);
+ }
+
+ /* We try again to fetch a message from the mbox. */
+ goto again;
+ } else {
+ /* If time != SYS_ARCH_TIMEOUT, a message was received before the timeout
+ occured. The time variable is set to the number of
+ milliseconds we waited for the message. */
+ if (time <= timeouts->next->time) {
+ timeouts->next->time -= time;
+ } else {
+ timeouts->next->time = 0;
+ }
+ }
+
+ }
+}
+
+void
+sys_sem_wait(sys_sem_t sem)
+{
+ u32_t time;
+ struct sys_timeouts *timeouts;
+ struct sys_timeout *tmptimeout;
+ sys_timeout_handler h;
+ void *arg;
+
+ /* while (sys_arch_sem_wait(sem, 1000) == 0);
+ return;*/
+
+ again:
+
+ timeouts = sys_arch_timeouts();
+
+ if (!timeouts || !timeouts->next) {
+ sys_arch_sem_wait(sem, 0);
+ } else {
+ if (timeouts->next->time > 0) {
+ time = sys_arch_sem_wait(sem, timeouts->next->time);
+ } else {
+ time = SYS_ARCH_TIMEOUT;
+ }
+
+ if (time == SYS_ARCH_TIMEOUT) {
+ /* If time == SYS_ARCH_TIMEOUT, a timeout occured before a message
+ could be fetched. We should now call the timeout handler and
+ deallocate the memory allocated for the timeout. */
+ tmptimeout = timeouts->next;
+ timeouts->next = tmptimeout->next;
+ h = tmptimeout->h;
+ arg = tmptimeout->arg;
+ memp_free(MEMP_SYS_TIMEOUT, tmptimeout);
+ if (h != NULL) {
+ LWIP_DEBUGF(SYS_DEBUG, ("ssw h=%p(%p)\n", (void *)h, (void *)arg));
+ h(arg);
+ }
+
+
+ /* We try again to fetch a message from the mbox. */
+ goto again;
+ } else {
+ /* If time != SYS_ARCH_TIMEOUT, a message was received before the timeout
+ occured. The time variable is set to the number of
+ milliseconds we waited for the message. */
+ if (time <= timeouts->next->time) {
+ timeouts->next->time -= time;
+ } else {
+ timeouts->next->time = 0;
+ }
+ }
+
+ }
+}
+
+void
+sys_timeout(u32_t msecs, sys_timeout_handler h, void *arg)
+{
+ struct sys_timeouts *timeouts;
+ struct sys_timeout *timeout, *t;
+
+ timeout = memp_malloc(MEMP_SYS_TIMEOUT);
+ if (timeout == NULL) {
+ return;
+ }
+ timeout->next = NULL;
+ timeout->h = h;
+ timeout->arg = arg;
+ timeout->time = msecs;
+
+ timeouts = sys_arch_timeouts();
+
+ LWIP_DEBUGF(SYS_DEBUG, ("sys_timeout: %p msecs=%lu h=%p arg=%p\n",
+ (void *)timeout, msecs, (void *)h, (void *)arg));
+
+ LWIP_ASSERT("sys_timeout: timeouts != NULL", timeouts != NULL);
+
+ if (timeouts->next == NULL) {
+ timeouts->next = timeout;
+ return;
+ }
+
+ if (timeouts->next->time > msecs) {
+ timeouts->next->time -= msecs;
+ timeout->next = timeouts->next;
+ timeouts->next = timeout;
+ } else {
+ for(t = timeouts->next; t != NULL; t = t->next) {
+ timeout->time -= t->time;
+ if (t->next == NULL || t->next->time > timeout->time) {
+ if (t->next != NULL) {
+ t->next->time -= timeout->time;
+ }
+ timeout->next = t->next;
+ t->next = timeout;
+ break;
+ }
+ }
+ }
+
+}
+
+/* Go through timeout list (for this task only) and remove the first matching entry,
+ even though the timeout has not triggered yet.
+*/
+
+void
+sys_untimeout(sys_timeout_handler h, void *arg)
+{
+ struct sys_timeouts *timeouts;
+ struct sys_timeout *prev_t, *t;
+
+ timeouts = sys_arch_timeouts();
+
+ if (timeouts->next == NULL)
+ return;
+
+ for (t = timeouts->next, prev_t = NULL; t != NULL; prev_t = t, t = t->next)
+ {
+ if ((t->h == h) && (t->arg == arg))
+ {
+ /* We have a match */
+ /* Unlink from previous in list */
+ if (prev_t == NULL)
+ timeouts->next = t->next;
+ else
+ prev_t->next = t->next;
+ /* If not the last one, add time of this one back to next */
+ if (t->next != NULL)
+ t->next->time += t->time;
+ memp_free(MEMP_SYS_TIMEOUT, t);
+ return;
+ }
+ }
+ return;
+}
+
+
+
+
+
+static void
+sswt_handler(void *arg)
+{
+ struct sswt_cb *sswt_cb = (struct sswt_cb *) arg;
+
+ /* Timeout. Set flag to TRUE and signal semaphore */
+ sswt_cb->timeflag = 1;
+ sys_sem_signal(*(sswt_cb->psem));
+}
+
+/* Wait for a semaphore with timeout (specified in ms) */
+/* timeout = 0: wait forever */
+/* Returns 0 on timeout. 1 otherwise */
+
+int
+sys_sem_wait_timeout(sys_sem_t sem, u32_t timeout)
+{
+ struct sswt_cb sswt_cb;
+
+ sswt_cb.psem = &sem;
+ sswt_cb.timeflag = 0;
+
+ /* If timeout is zero, then just wait forever */
+ if (timeout > 0)
+ /* Create a timer and pass it the address of our flag */
+ sys_timeout(timeout, sswt_handler, &sswt_cb);
+ sys_sem_wait(sem);
+ /* Was it a timeout? */
+ if (sswt_cb.timeflag)
+ {
+ /* timeout */
+ return 0;
+ } else {
+ /* Not a timeout. Remove timeout entry */
+ sys_untimeout(sswt_handler, &sswt_cb);
+ return 1;
+ }
+
+}
+
+
+void
+sys_msleep(u32_t ms)
+{
+ sys_sem_t delaysem = sys_sem_new(0);
+
+ sys_sem_wait_timeout(delaysem, ms);
+
+ sys_sem_free(delaysem);
+}
+
+
+#endif /* NO_SYS */
--- /dev/null
+/**\r
+ * @file\r
+ *\r
+ * Transmission Control Protocol for IP\r
+ *\r
+ * This file contains common functions for the TCP implementation, such as functinos\r
+ * for manipulating the data structures and the TCP timer functions. TCP functions\r
+ * related to input and output is found in tcp_in.c and tcp_out.c respectively.\r
+ *\r
+ */\r
+\r
+/*\r
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.\r
+ * All rights reserved. \r
+ * \r
+ * Redistribution and use in source and binary forms, with or without modification, \r
+ * are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. The name of the author may not be used to endorse or promote products\r
+ * derived from this software without specific prior written permission. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED \r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT \r
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, \r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT \r
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS \r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN \r
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING \r
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY \r
+ * OF SUCH DAMAGE.\r
+ *\r
+ * This file is part of the lwIP TCP/IP stack.\r
+ * \r
+ * Author: Adam Dunkels <adam@sics.se>\r
+ *\r
+ */\r
+\r
+#include <string.h>\r
+\r
+#include "lwip/opt.h"\r
+#include "lwip/def.h"\r
+#include "lwip/mem.h"\r
+#include "lwip/memp.h"\r
+\r
+#include "lwip/tcp.h"\r
+#if LWIP_TCP\r
+\r
+/* Incremented every coarse grained timer shot\r
+ (typically every 500 ms, determined by TCP_COARSE_TIMEOUT). */\r
+u32_t tcp_ticks;\r
+const u8_t tcp_backoff[13] =\r
+ { 1, 2, 3, 4, 5, 6, 7, 7, 7, 7, 7, 7, 7};\r
+\r
+/* The TCP PCB lists. */\r
+\r
+/** List of all TCP PCBs in LISTEN state */\r
+union tcp_listen_pcbs_t tcp_listen_pcbs;\r
+/** List of all TCP PCBs that are in a state in which\r
+ * they accept or send data. */\r
+struct tcp_pcb *tcp_active_pcbs; \r
+/** List of all TCP PCBs in TIME-WAIT state */\r
+struct tcp_pcb *tcp_tw_pcbs;\r
+\r
+struct tcp_pcb *tcp_tmp_pcb;\r
+\r
+static u8_t tcp_timer;\r
+static u16_t tcp_new_port(void);\r
+\r
+/**\r
+ * Initializes the TCP layer.\r
+ */\r
+void\r
+tcp_init(void)\r
+{\r
+ /* Clear globals. */\r
+ tcp_listen_pcbs.listen_pcbs = NULL;\r
+ tcp_active_pcbs = NULL;\r
+ tcp_tw_pcbs = NULL;\r
+ tcp_tmp_pcb = NULL;\r
+ \r
+ /* initialize timer */\r
+ tcp_ticks = 0;\r
+ tcp_timer = 0;\r
+ \r
+}\r
+\r
+/**\r
+ * Called periodically to dispatch TCP timers.\r
+ *\r
+ */\r
+void\r
+tcp_tmr(void)\r
+{\r
+ /* Call tcp_fasttmr() every 250 ms */\r
+ tcp_fasttmr();\r
+\r
+ if (++tcp_timer & 1) {\r
+ /* Call tcp_tmr() every 500 ms, i.e., every other timer\r
+ tcp_tmr() is called. */\r
+ tcp_slowtmr();\r
+ }\r
+}\r
+\r
+/**\r
+ * Closes the connection held by the PCB.\r
+ *\r
+ */\r
+err_t\r
+tcp_close(struct tcp_pcb *pcb)\r
+{\r
+ err_t err;\r
+\r
+#if TCP_DEBUG\r
+ LWIP_DEBUGF(TCP_DEBUG, ("tcp_close: closing in state "));\r
+ tcp_debug_print_state(pcb->state);\r
+ LWIP_DEBUGF(TCP_DEBUG, ("\n"));\r
+#endif /* TCP_DEBUG */\r
+ switch (pcb->state) {\r
+ case CLOSED:\r
+ /* Closing a pcb in the CLOSED state might seem erroneous,\r
+ * however, it is in this state once allocated and as yet unused\r
+ * and the user needs some way to free it should the need arise.\r
+ * Calling tcp_close() with a pcb that has already been closed, (i.e. twice)\r
+ * or for a pcb that has been used and then entered the CLOSED state \r
+ * is erroneous, but this should never happen as the pcb has in those cases\r
+ * been freed, and so any remaining handles are bogus. */\r
+ err = ERR_OK;\r
+ memp_free(MEMP_TCP_PCB, pcb);\r
+ pcb = NULL;\r
+ break;\r
+ case LISTEN:\r
+ err = ERR_OK;\r
+ tcp_pcb_remove((struct tcp_pcb **)&tcp_listen_pcbs.pcbs, pcb);\r
+ memp_free(MEMP_TCP_PCB_LISTEN, pcb);\r
+ pcb = NULL;\r
+ break;\r
+ case SYN_SENT:\r
+ err = ERR_OK;\r
+ tcp_pcb_remove(&tcp_active_pcbs, pcb);\r
+ memp_free(MEMP_TCP_PCB, pcb);\r
+ pcb = NULL;\r
+ break;\r
+ case SYN_RCVD:\r
+ case ESTABLISHED:\r
+ err = tcp_send_ctrl(pcb, TCP_FIN);\r
+ if (err == ERR_OK) {\r
+ pcb->state = FIN_WAIT_1;\r
+ }\r
+ break;\r
+ case CLOSE_WAIT:\r
+ err = tcp_send_ctrl(pcb, TCP_FIN);\r
+ if (err == ERR_OK) {\r
+ pcb->state = LAST_ACK;\r
+ }\r
+ break;\r
+ default:\r
+ /* Has already been closed, do nothing. */\r
+ err = ERR_OK;\r
+ pcb = NULL;\r
+ break;\r
+ }\r
+\r
+ if (pcb != NULL && err == ERR_OK) {\r
+ err = tcp_output(pcb);\r
+ }\r
+ return err;\r
+}\r
+\r
+/**\r
+ * Aborts a connection by sending a RST to the remote host and deletes\r
+ * the local protocol control block. This is done when a connection is\r
+ * killed because of shortage of memory.\r
+ *\r
+ */\r
+void\r
+tcp_abort(struct tcp_pcb *pcb)\r
+{\r
+ u32_t seqno, ackno;\r
+ u16_t remote_port, local_port;\r
+ struct ip_addr remote_ip, local_ip;\r
+#if LWIP_CALLBACK_API \r
+ void (* errf)(void *arg, err_t err);\r
+#endif /* LWIP_CALLBACK_API */\r
+ void *errf_arg;\r
+\r
+ \r
+ /* Figure out on which TCP PCB list we are, and remove us. If we\r
+ are in an active state, call the receive function associated with\r
+ the PCB with a NULL argument, and send an RST to the remote end. */\r
+ if (pcb->state == TIME_WAIT) {\r
+ tcp_pcb_remove(&tcp_tw_pcbs, pcb);\r
+ memp_free(MEMP_TCP_PCB, pcb);\r
+ } else {\r
+ seqno = pcb->snd_nxt;\r
+ ackno = pcb->rcv_nxt;\r
+ ip_addr_set(&local_ip, &(pcb->local_ip));\r
+ ip_addr_set(&remote_ip, &(pcb->remote_ip));\r
+ local_port = pcb->local_port;\r
+ remote_port = pcb->remote_port;\r
+#if LWIP_CALLBACK_API\r
+ errf = pcb->errf;\r
+#endif /* LWIP_CALLBACK_API */\r
+ errf_arg = pcb->callback_arg;\r
+ tcp_pcb_remove(&tcp_active_pcbs, pcb);\r
+ if (pcb->unacked != NULL) {\r
+ tcp_segs_free(pcb->unacked);\r
+ }\r
+ if (pcb->unsent != NULL) {\r
+ tcp_segs_free(pcb->unsent);\r
+ }\r
+#if TCP_QUEUE_OOSEQ \r
+ if (pcb->ooseq != NULL) {\r
+ tcp_segs_free(pcb->ooseq);\r
+ }\r
+#endif /* TCP_QUEUE_OOSEQ */\r
+ memp_free(MEMP_TCP_PCB, pcb);\r
+ TCP_EVENT_ERR(errf, errf_arg, ERR_ABRT);\r
+ LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_abort: sending RST\n"));\r
+ tcp_rst(seqno, ackno, &local_ip, &remote_ip, local_port, remote_port);\r
+ }\r
+}\r
+\r
+/**\r
+ * Binds the connection to a local portnumber and IP address. If the\r
+ * IP address is not given (i.e., ipaddr == NULL), the IP address of\r
+ * the outgoing network interface is used instead.\r
+ *\r
+ */\r
+\r
+err_t\r
+tcp_bind(struct tcp_pcb *pcb, struct ip_addr *ipaddr, u16_t port)\r
+{\r
+ struct tcp_pcb *cpcb;\r
+#if SO_REUSE\r
+ int reuse_port_all_set = 1;\r
+#endif /* SO_REUSE */\r
+\r
+ if (port == 0) {\r
+ port = tcp_new_port();\r
+ }\r
+#if SO_REUSE == 0\r
+ /* Check if the address already is in use. */\r
+ for(cpcb = (struct tcp_pcb *)tcp_listen_pcbs.pcbs;\r
+ cpcb != NULL; cpcb = cpcb->next) {\r
+ if (cpcb->local_port == port) {\r
+ if (ip_addr_isany(&(cpcb->local_ip)) ||\r
+ ip_addr_isany(ipaddr) ||\r
+ ip_addr_cmp(&(cpcb->local_ip), ipaddr)) {\r
+ return ERR_USE;\r
+ }\r
+ }\r
+ }\r
+ for(cpcb = tcp_active_pcbs;\r
+ cpcb != NULL; cpcb = cpcb->next) {\r
+ if (cpcb->local_port == port) {\r
+ if (ip_addr_isany(&(cpcb->local_ip)) ||\r
+ ip_addr_isany(ipaddr) ||\r
+ ip_addr_cmp(&(cpcb->local_ip), ipaddr)) {\r
+ return ERR_USE;\r
+ }\r
+ }\r
+ }\r
+#else /* SO_REUSE */\r
+ /* Search through list of PCB's in LISTEN state. \r
+ \r
+ If there is a PCB bound to specified port and IP_ADDR_ANY another PCB can be bound to the interface IP\r
+ or to the loopback address on the same port if SOF_REUSEADDR is set. Any combination of PCB's bound to \r
+ the same local port, but to one address out of {IP_ADDR_ANY, 127.0.0.1, interface IP} at a time is valid.\r
+ But no two PCB's bound to same local port and same local address is valid.\r
+ \r
+ If SOF_REUSEPORT is set several PCB's can be bound to same local port and same local address also. But then \r
+ all PCB's must have the SOF_REUSEPORT option set.\r
+ \r
+ When the two options aren't set and specified port is already bound, ERR_USE is returned saying that \r
+ address is already in use. */\r
+ for(cpcb = (struct tcp_pcb *)tcp_listen_pcbs.pcbs; cpcb != NULL; cpcb = cpcb->next) {\r
+ if(cpcb->local_port == port) {\r
+ if(ip_addr_cmp(&(cpcb->local_ip), ipaddr)) {\r
+ if(pcb->so_options & SOF_REUSEPORT) {\r
+ LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: in listening PCB's: SO_REUSEPORT set and same address.\n"));\r
+ reuse_port_all_set = (reuse_port_all_set && (cpcb->so_options & SOF_REUSEPORT));\r
+ }\r
+ else {\r
+ LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: in listening PCB's: SO_REUSEPORT not set and same address.\n"));\r
+ return ERR_USE;\r
+ }\r
+ }\r
+ else if((ip_addr_isany(ipaddr) && !ip_addr_isany(&(cpcb->local_ip))) ||\r
+ (!ip_addr_isany(ipaddr) && ip_addr_isany(&(cpcb->local_ip)))) {\r
+ if(!(pcb->so_options & SOF_REUSEADDR) && !(pcb->so_options & SOF_REUSEPORT)) {\r
+ LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: in listening PCB's SO_REUSEPORT or SO_REUSEADDR not set and not the same address.\n"));\r
+ return ERR_USE;\r
+ } \r
+ else {\r
+ LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: in listening PCB's SO_REUSEPORT or SO_REUSEADDR set and not the same address.\n"));\r
+ } \r
+ }\r
+ }\r
+ }\r
+\r
+ /* Search through list of PCB's in a state in which they can accept or send data. Same decription as for \r
+ PCB's in state LISTEN applies to this PCB's regarding the options SOF_REUSEADDR and SOF_REUSEPORT. */\r
+ for(cpcb = tcp_active_pcbs; cpcb != NULL; cpcb = cpcb->next) {\r
+ if(cpcb->local_port == port) {\r
+ if(ip_addr_cmp(&(cpcb->local_ip), ipaddr)) {\r
+ if(pcb->so_options & SOF_REUSEPORT) {\r
+ LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: in active PCB's SO_REUSEPORT set and same address.\n"));\r
+ reuse_port_all_set = (reuse_port_all_set && (cpcb->so_options & SOF_REUSEPORT));\r
+ }\r
+ else {\r
+ LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: in active PCB's SO_REUSEPORT not set and same address.\n"));\r
+ return ERR_USE;\r
+ }\r
+ }\r
+ else if((ip_addr_isany(ipaddr) && !ip_addr_isany(&(cpcb->local_ip))) ||\r
+ (!ip_addr_isany(ipaddr) && ip_addr_isany(&(cpcb->local_ip)))) {\r
+ if(!(pcb->so_options & SOF_REUSEADDR) && !(pcb->so_options & SOF_REUSEPORT)) {\r
+ LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: in active PCB's SO_REUSEPORT or SO_REUSEADDR not set and not the same address.\n"));\r
+ return ERR_USE;\r
+ } \r
+ else {\r
+ LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: in active PCB's SO_REUSEPORT or SO_REUSEADDR set and not the same address.\n"));\r
+ } \r
+ }\r
+ }\r
+ }\r
+\r
+ /* Search through list of PCB's in TIME_WAIT state. If SO_REUSEADDR is set a bound combination [IP, port} \r
+ can be rebound. The same applies when SOF_REUSEPORT is set. \r
+ \r
+ If SOF_REUSEPORT is set several PCB's can be bound to same local port and same local address also. But then \r
+ all PCB's must have the SOF_REUSEPORT option set.\r
+ \r
+ When the two options aren't set and specified port is already bound, ERR_USE is returned saying that \r
+ address is already in use. */\r
+ for(cpcb = tcp_tw_pcbs; cpcb != NULL; cpcb = cpcb->next) {\r
+ if(cpcb->local_port == port) {\r
+ if(ip_addr_cmp(&(cpcb->local_ip), ipaddr)) {\r
+ if(!(pcb->so_options & SOF_REUSEADDR) && !(pcb->so_options & SOF_REUSEPORT)) {\r
+ LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: in TIME_WAIT PCB's SO_REUSEPORT or SO_REUSEADDR not set and same address.\n"));\r
+ return ERR_USE;\r
+ }\r
+ else if(pcb->so_options & SOF_REUSEPORT) {\r
+ LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: in TIME_WAIT PCB's SO_REUSEPORT set and same address.\n"));\r
+ reuse_port_all_set = (reuse_port_all_set && (cpcb->so_options & SOF_REUSEPORT));\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ /* If SOF_REUSEPORT isn't set in all PCB's bound to specified port and local address specified then \r
+ {IP, port} can't be reused. */\r
+ if(!reuse_port_all_set) {\r
+ LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: not all sockets have SO_REUSEPORT set.\n"));\r
+ return ERR_USE;\r
+ }\r
+#endif /* SO_REUSE */\r
+\r
+ if (!ip_addr_isany(ipaddr)) {\r
+ pcb->local_ip = *ipaddr;\r
+ }\r
+ pcb->local_port = port;\r
+ LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: bind to port %u\n", port));\r
+ return ERR_OK;\r
+}\r
+#if LWIP_CALLBACK_API\r
+static err_t\r
+tcp_accept_null(void *arg, struct tcp_pcb *pcb, err_t err)\r
+{\r
+ (void)arg;\r
+ (void)pcb;\r
+ (void)err;\r
+\r
+ return ERR_ABRT;\r
+}\r
+#endif /* LWIP_CALLBACK_API */\r
+\r
+/**\r
+ * Set the state of the connection to be LISTEN, which means that it\r
+ * is able to accept incoming connections. The protocol control block\r
+ * is reallocated in order to consume less memory. Setting the\r
+ * connection to LISTEN is an irreversible process.\r
+ *\r
+ */\r
+struct tcp_pcb *\r
+tcp_listen(struct tcp_pcb *pcb)\r
+{\r
+ struct tcp_pcb_listen *lpcb;\r
+\r
+ /* already listening? */\r
+ if (pcb->state == LISTEN) {\r
+ return pcb;\r
+ }\r
+ lpcb = memp_malloc(MEMP_TCP_PCB_LISTEN);\r
+ if (lpcb == NULL) {\r
+ return NULL;\r
+ }\r
+ lpcb->callback_arg = pcb->callback_arg;\r
+ lpcb->local_port = pcb->local_port;\r
+ lpcb->state = LISTEN;\r
+ lpcb->so_options = pcb->so_options;\r
+ lpcb->so_options |= SOF_ACCEPTCONN;\r
+ lpcb->ttl = pcb->ttl;\r
+ lpcb->tos = pcb->tos;\r
+ ip_addr_set(&lpcb->local_ip, &pcb->local_ip);\r
+ memp_free(MEMP_TCP_PCB, pcb);\r
+#if LWIP_CALLBACK_API\r
+ lpcb->accept = tcp_accept_null;\r
+#endif /* LWIP_CALLBACK_API */\r
+ TCP_REG(&tcp_listen_pcbs.listen_pcbs, lpcb);\r
+ return (struct tcp_pcb *)lpcb;\r
+}\r
+\r
+/**\r
+ * This function should be called by the application when it has\r
+ * processed the data. The purpose is to advertise a larger window\r
+ * when the data has been processed.\r
+ *\r
+ */\r
+void\r
+tcp_recved(struct tcp_pcb *pcb, u16_t len)\r
+{\r
+ if ((u32_t)pcb->rcv_wnd + len > TCP_WND) {\r
+ pcb->rcv_wnd = TCP_WND;\r
+ } else {\r
+ pcb->rcv_wnd += len;\r
+ }\r
+ if (!(pcb->flags & TF_ACK_DELAY) &&\r
+ !(pcb->flags & TF_ACK_NOW)) {\r
+ /*\r
+ * We send an ACK here (if one is not already pending, hence\r
+ * the above tests) as tcp_recved() implies that the application\r
+ * has processed some data, and so we can open the receiver's\r
+ * window to allow more to be transmitted. This could result in\r
+ * two ACKs being sent for each received packet in some limited cases\r
+ * (where the application is only receiving data, and is slow to\r
+ * process it) but it is necessary to guarantee that the sender can\r
+ * continue to transmit.\r
+ */\r
+ tcp_ack(pcb);\r
+ } \r
+ else if (pcb->flags & TF_ACK_DELAY && pcb->rcv_wnd >= TCP_WND/2) {\r
+ /* If we can send a window update such that there is a full\r
+ * segment available in the window, do so now. This is sort of\r
+ * nagle-like in its goals, and tries to hit a compromise between\r
+ * sending acks each time the window is updated, and only sending\r
+ * window updates when a timer expires. The "threshold" used\r
+ * above (currently TCP_WND/2) can be tuned to be more or less\r
+ * aggressive */\r
+ tcp_ack_now(pcb);\r
+ }\r
+\r
+ LWIP_DEBUGF(TCP_DEBUG, ("tcp_recved: recveived %u bytes, wnd %u (%u).\n",\r
+ len, pcb->rcv_wnd, TCP_WND - pcb->rcv_wnd));\r
+}\r
+\r
+/**\r
+ * A nastly hack featuring 'goto' statements that allocates a\r
+ * new TCP local port.\r
+ */\r
+static u16_t\r
+tcp_new_port(void)\r
+{\r
+ struct tcp_pcb *pcb;\r
+#ifndef TCP_LOCAL_PORT_RANGE_START\r
+#define TCP_LOCAL_PORT_RANGE_START 4096\r
+#define TCP_LOCAL_PORT_RANGE_END 0x7fff\r
+#endif\r
+ static u16_t port = TCP_LOCAL_PORT_RANGE_START;\r
+ \r
+ again:\r
+ if (++port > TCP_LOCAL_PORT_RANGE_END) {\r
+ port = TCP_LOCAL_PORT_RANGE_START;\r
+ }\r
+ \r
+ for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {\r
+ if (pcb->local_port == port) {\r
+ goto again;\r
+ }\r
+ }\r
+ for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {\r
+ if (pcb->local_port == port) {\r
+ goto again;\r
+ }\r
+ }\r
+ for(pcb = (struct tcp_pcb *)tcp_listen_pcbs.pcbs; pcb != NULL; pcb = pcb->next) {\r
+ if (pcb->local_port == port) {\r
+ goto again;\r
+ }\r
+ }\r
+ return port;\r
+}\r
+\r
+/**\r
+ * Connects to another host. The function given as the "connected"\r
+ * argument will be called when the connection has been established.\r
+ *\r
+ */\r
+err_t\r
+tcp_connect(struct tcp_pcb *pcb, struct ip_addr *ipaddr, u16_t port,\r
+ err_t (* connected)(void *arg, struct tcp_pcb *tpcb, err_t err))\r
+{\r
+ u32_t optdata;\r
+ err_t ret;\r
+ u32_t iss;\r
+\r
+ LWIP_DEBUGF(TCP_DEBUG, ("tcp_connect to port %u\n", port));\r
+ if (ipaddr != NULL) {\r
+ pcb->remote_ip = *ipaddr;\r
+ } else {\r
+ return ERR_VAL;\r
+ }\r
+ pcb->remote_port = port;\r
+ if (pcb->local_port == 0) {\r
+ pcb->local_port = tcp_new_port();\r
+ }\r
+ iss = tcp_next_iss();\r
+ pcb->rcv_nxt = 0;\r
+ pcb->snd_nxt = iss;\r
+ pcb->lastack = iss - 1;\r
+ pcb->snd_lbb = iss - 1;\r
+ pcb->rcv_wnd = TCP_WND;\r
+ pcb->snd_wnd = TCP_WND;\r
+ pcb->mss = TCP_MSS;\r
+ pcb->cwnd = 1;\r
+ pcb->ssthresh = pcb->mss * 10;\r
+ pcb->state = SYN_SENT;\r
+#if LWIP_CALLBACK_API \r
+ pcb->connected = connected;\r
+#endif /* LWIP_CALLBACK_API */ \r
+ TCP_REG(&tcp_active_pcbs, pcb);\r
+ \r
+ /* Build an MSS option */\r
+ optdata = htonl(((u32_t)2 << 24) | \r
+ ((u32_t)4 << 16) | \r
+ (((u32_t)pcb->mss / 256) << 8) |\r
+ (pcb->mss & 255));\r
+\r
+ ret = tcp_enqueue(pcb, NULL, 0, TCP_SYN, 0, (u8_t *)&optdata, 4);\r
+ if (ret == ERR_OK) { \r
+ tcp_output(pcb);\r
+ }\r
+ return ret;\r
+} \r
+\r
+/**\r
+ * Called every 500 ms and implements the retransmission timer and the timer that\r
+ * removes PCBs that have been in TIME-WAIT for enough time. It also increments\r
+ * various timers such as the inactivity timer in each PCB.\r
+ */\r
+void\r
+tcp_slowtmr(void)\r
+{\r
+ struct tcp_pcb *pcb, *pcb2, *prev;\r
+ u32_t eff_wnd;\r
+ u8_t pcb_remove; /* flag if a PCB should be removed */\r
+ err_t err;\r
+\r
+ err = ERR_OK;\r
+\r
+ ++tcp_ticks;\r
+\r
+ /* Steps through all of the active PCBs. */\r
+ prev = NULL;\r
+ pcb = tcp_active_pcbs;\r
+ if (pcb == NULL) {\r
+ LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: no active pcbs\n"));\r
+ }\r
+ while (pcb != NULL) {\r
+ LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: processing active pcb\n"));\r
+ LWIP_ASSERT("tcp_slowtmr: active pcb->state != CLOSED\n", pcb->state != CLOSED);\r
+ LWIP_ASSERT("tcp_slowtmr: active pcb->state != LISTEN\n", pcb->state != LISTEN);\r
+ LWIP_ASSERT("tcp_slowtmr: active pcb->state != TIME-WAIT\n", pcb->state != TIME_WAIT);\r
+\r
+ pcb_remove = 0;\r
+\r
+ if (pcb->state == SYN_SENT && pcb->nrtx == TCP_SYNMAXRTX) {\r
+ ++pcb_remove;\r
+ LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max SYN retries reached\n"));\r
+ }\r
+ else if (pcb->nrtx == TCP_MAXRTX) {\r
+ ++pcb_remove;\r
+ LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max DATA retries reached\n"));\r
+ } else {\r
+ ++pcb->rtime;\r
+ if (pcb->unacked != NULL && pcb->rtime >= pcb->rto) {\r
+\r
+ /* Time for a retransmission. */\r
+ LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_slowtmr: rtime %u pcb->rto %u\n",\r
+ pcb->rtime, pcb->rto));\r
+\r
+ /* Double retransmission time-out unless we are trying to\r
+ * connect to somebody (i.e., we are in SYN_SENT). */\r
+ if (pcb->state != SYN_SENT) {\r
+ pcb->rto = ((pcb->sa >> 3) + pcb->sv) << tcp_backoff[pcb->nrtx];\r
+ }\r
+ /* Reduce congestion window and ssthresh. */\r
+ eff_wnd = LWIP_MIN(pcb->cwnd, pcb->snd_wnd);\r
+ pcb->ssthresh = eff_wnd >> 1;\r
+ if (pcb->ssthresh < pcb->mss) {\r
+ pcb->ssthresh = pcb->mss * 2;\r
+ }\r
+ pcb->cwnd = pcb->mss;\r
+ LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: cwnd %u ssthresh %u\n",\r
+ pcb->cwnd, pcb->ssthresh));\r
+ \r
+ /* The following needs to be called AFTER cwnd is set to one mss - STJ */\r
+ tcp_rexmit_rto(pcb);\r
+ }\r
+ }\r
+ /* Check if this PCB has stayed too long in FIN-WAIT-2 */\r
+ if (pcb->state == FIN_WAIT_2) {\r
+ if ((u32_t)(tcp_ticks - pcb->tmr) >\r
+ TCP_FIN_WAIT_TIMEOUT / TCP_SLOW_INTERVAL) {\r
+ ++pcb_remove;\r
+ LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in FIN-WAIT-2\n"));\r
+ }\r
+ }\r
+\r
+ /* Check if KEEPALIVE should be sent */\r
+ if((pcb->so_options & SOF_KEEPALIVE) && ((pcb->state == ESTABLISHED) || (pcb->state == CLOSE_WAIT))) {\r
+ if((u32_t)(tcp_ticks - pcb->tmr) > (pcb->keepalive + TCP_MAXIDLE) / TCP_SLOW_INTERVAL) {\r
+ LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: KEEPALIVE timeout. Aborting connection to %u.%u.%u.%u.\n",\r
+ ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip),\r
+ ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip)));\r
+\r
+ tcp_abort(pcb);\r
+ }\r
+ else if((u32_t)(tcp_ticks - pcb->tmr) > (pcb->keepalive + pcb->keep_cnt * TCP_KEEPINTVL) / TCP_SLOW_INTERVAL) {\r
+ tcp_keepalive(pcb);\r
+ pcb->keep_cnt++;\r
+ }\r
+ }\r
+\r
+ /* If this PCB has queued out of sequence data, but has been\r
+ inactive for too long, will drop the data (it will eventually\r
+ be retransmitted). */\r
+#if TCP_QUEUE_OOSEQ \r
+ if (pcb->ooseq != NULL &&\r
+ (u32_t)tcp_ticks - pcb->tmr >=\r
+ pcb->rto * (u32_t)TCP_OOSEQ_TIMEOUT) {\r
+ tcp_segs_free(pcb->ooseq);\r
+ pcb->ooseq = NULL;\r
+ LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: dropping OOSEQ queued data\n"));\r
+ }\r
+#endif /* TCP_QUEUE_OOSEQ */\r
+\r
+ /* Check if this PCB has stayed too long in SYN-RCVD */\r
+ if (pcb->state == SYN_RCVD) {\r
+ if ((u32_t)(tcp_ticks - pcb->tmr) >\r
+ TCP_SYN_RCVD_TIMEOUT / TCP_SLOW_INTERVAL) {\r
+ ++pcb_remove;\r
+ LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in SYN-RCVD\n"));\r
+ }\r
+ }\r
+\r
+\r
+ /* If the PCB should be removed, do it. */\r
+ if (pcb_remove) {\r
+ tcp_pcb_purge(pcb); \r
+ /* Remove PCB from tcp_active_pcbs list. */\r
+ if (prev != NULL) {\r
+ LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_active_pcbs", pcb != tcp_active_pcbs);\r
+ prev->next = pcb->next;\r
+ } else {\r
+ /* This PCB was the first. */\r
+ LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_active_pcbs", tcp_active_pcbs == pcb);\r
+ tcp_active_pcbs = pcb->next;\r
+ }\r
+\r
+ TCP_EVENT_ERR(pcb->errf, pcb->callback_arg, ERR_ABRT);\r
+\r
+ pcb2 = pcb->next;\r
+ memp_free(MEMP_TCP_PCB, pcb);\r
+ pcb = pcb2;\r
+ } else {\r
+\r
+ /* We check if we should poll the connection. */\r
+ ++pcb->polltmr;\r
+ if (pcb->polltmr >= pcb->pollinterval) {\r
+ pcb->polltmr = 0;\r
+ LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: polling application\n"));\r
+ TCP_EVENT_POLL(pcb, err);\r
+ if (err == ERR_OK) {\r
+ tcp_output(pcb);\r
+ }\r
+ }\r
+ \r
+ prev = pcb;\r
+ pcb = pcb->next;\r
+ }\r
+ }\r
+\r
+ \r
+ /* Steps through all of the TIME-WAIT PCBs. */\r
+ prev = NULL; \r
+ pcb = tcp_tw_pcbs;\r
+ while (pcb != NULL) {\r
+ LWIP_ASSERT("tcp_slowtmr: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT);\r
+ pcb_remove = 0;\r
+\r
+ /* Check if this PCB has stayed long enough in TIME-WAIT */\r
+ if ((u32_t)(tcp_ticks - pcb->tmr) > 2 * TCP_MSL / TCP_SLOW_INTERVAL) {\r
+ ++pcb_remove;\r
+ }\r
+ \r
+\r
+\r
+ /* If the PCB should be removed, do it. */\r
+ if (pcb_remove) {\r
+ tcp_pcb_purge(pcb); \r
+ /* Remove PCB from tcp_tw_pcbs list. */\r
+ if (prev != NULL) {\r
+ LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_tw_pcbs", pcb != tcp_tw_pcbs);\r
+ prev->next = pcb->next;\r
+ } else {\r
+ /* This PCB was the first. */\r
+ LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_tw_pcbs", tcp_tw_pcbs == pcb);\r
+ tcp_tw_pcbs = pcb->next;\r
+ }\r
+ pcb2 = pcb->next;\r
+ memp_free(MEMP_TCP_PCB, pcb);\r
+ pcb = pcb2;\r
+ } else {\r
+ prev = pcb;\r
+ pcb = pcb->next;\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * Is called every TCP_FAST_INTERVAL (250 ms) and sends delayed ACKs.\r
+ */\r
+void\r
+tcp_fasttmr(void)\r
+{\r
+ struct tcp_pcb *pcb;\r
+\r
+ /* send delayed ACKs */ \r
+ for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {\r
+ if (pcb->flags & TF_ACK_DELAY) {\r
+ LWIP_DEBUGF(TCP_DEBUG, ("tcp_fasttmr: delayed ACK\n"));\r
+ tcp_ack_now(pcb);\r
+ pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * Deallocates a list of TCP segments (tcp_seg structures).\r
+ *\r
+ */\r
+u8_t\r
+tcp_segs_free(struct tcp_seg *seg)\r
+{\r
+ u8_t count = 0;\r
+ struct tcp_seg *next;\r
+ while (seg != NULL) {\r
+ next = seg->next;\r
+ count += tcp_seg_free(seg);\r
+ seg = next;\r
+ }\r
+ return count;\r
+}\r
+\r
+/**\r
+ * Frees a TCP segment.\r
+ *\r
+ */\r
+u8_t\r
+tcp_seg_free(struct tcp_seg *seg)\r
+{\r
+ u8_t count = 0;\r
+ \r
+ if (seg != NULL) {\r
+ if (seg->p != NULL) {\r
+ count = pbuf_free(seg->p);\r
+#if TCP_DEBUG\r
+ seg->p = NULL;\r
+#endif /* TCP_DEBUG */\r
+ }\r
+ memp_free(MEMP_TCP_SEG, seg);\r
+ }\r
+ return count;\r
+}\r
+\r
+/**\r
+ * Sets the priority of a connection.\r
+ *\r
+ */\r
+void\r
+tcp_setprio(struct tcp_pcb *pcb, u8_t prio)\r
+{\r
+ pcb->prio = prio;\r
+}\r
+#if TCP_QUEUE_OOSEQ\r
+\r
+/**\r
+ * Returns a copy of the given TCP segment.\r
+ *\r
+ */ \r
+struct tcp_seg *\r
+tcp_seg_copy(struct tcp_seg *seg)\r
+{\r
+ struct tcp_seg *cseg;\r
+\r
+ cseg = memp_malloc(MEMP_TCP_SEG);\r
+ if (cseg == NULL) {\r
+ return NULL;\r
+ }\r
+ memcpy((char *)cseg, (const char *)seg, sizeof(struct tcp_seg)); \r
+ pbuf_ref(cseg->p);\r
+ return cseg;\r
+}\r
+#endif\r
+\r
+#if LWIP_CALLBACK_API\r
+static err_t\r
+tcp_recv_null(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err)\r
+{\r
+ arg = arg;\r
+ if (p != NULL) {\r
+ pbuf_free(p);\r
+ } else if (err == ERR_OK) {\r
+ return tcp_close(pcb);\r
+ }\r
+ return ERR_OK;\r
+}\r
+#endif /* LWIP_CALLBACK_API */\r
+\r
+static void\r
+tcp_kill_prio(u8_t prio)\r
+{\r
+ struct tcp_pcb *pcb, *inactive;\r
+ u32_t inactivity;\r
+ u8_t mprio;\r
+\r
+\r
+ mprio = TCP_PRIO_MAX;\r
+ \r
+ /* We kill the oldest active connection that has lower priority than\r
+ prio. */\r
+ inactivity = 0;\r
+ inactive = NULL;\r
+ for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {\r
+ if (pcb->prio <= prio &&\r
+ pcb->prio <= mprio &&\r
+ (u32_t)(tcp_ticks - pcb->tmr) >= inactivity) {\r
+ inactivity = tcp_ticks - pcb->tmr;\r
+ inactive = pcb;\r
+ mprio = pcb->prio;\r
+ }\r
+ }\r
+ if (inactive != NULL) {\r
+ LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_prio: killing oldest PCB %p (%ld)\n",\r
+ (void *)inactive, inactivity));\r
+ tcp_abort(inactive);\r
+ } \r
+}\r
+\r
+\r
+static void\r
+tcp_kill_timewait(void)\r
+{\r
+ struct tcp_pcb *pcb, *inactive;\r
+ u32_t inactivity;\r
+\r
+ inactivity = 0;\r
+ inactive = NULL;\r
+ for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {\r
+ if ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity) {\r
+ inactivity = tcp_ticks - pcb->tmr;\r
+ inactive = pcb;\r
+ }\r
+ }\r
+ if (inactive != NULL) {\r
+ LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_timewait: killing oldest TIME-WAIT PCB %p (%ld)\n",\r
+ (void *)inactive, inactivity));\r
+ tcp_abort(inactive);\r
+ } \r
+}\r
+\r
+\r
+\r
+struct tcp_pcb *\r
+tcp_alloc(u8_t prio)\r
+{\r
+ struct tcp_pcb *pcb;\r
+ u32_t iss;\r
+ \r
+ pcb = memp_malloc(MEMP_TCP_PCB);\r
+ if (pcb == NULL) {\r
+ /* Try killing oldest connection in TIME-WAIT. */\r
+ LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing off oldest TIME-WAIT connection\n"));\r
+ tcp_kill_timewait();\r
+ pcb = memp_malloc(MEMP_TCP_PCB);\r
+ if (pcb == NULL) {\r
+ tcp_kill_prio(prio); \r
+ pcb = memp_malloc(MEMP_TCP_PCB);\r
+ }\r
+ }\r
+ if (pcb != NULL) {\r
+ memset(pcb, 0, sizeof(struct tcp_pcb));\r
+ pcb->prio = TCP_PRIO_NORMAL;\r
+ pcb->snd_buf = TCP_SND_BUF;\r
+ pcb->snd_queuelen = 0;\r
+ pcb->rcv_wnd = TCP_WND;\r
+ pcb->tos = 0;\r
+ pcb->ttl = TCP_TTL;\r
+ pcb->mss = TCP_MSS;\r
+ pcb->rto = 3000 / TCP_SLOW_INTERVAL;\r
+ pcb->sa = 0;\r
+ pcb->sv = 3000 / TCP_SLOW_INTERVAL;\r
+ pcb->rtime = 0;\r
+ pcb->cwnd = 1;\r
+ iss = tcp_next_iss();\r
+ pcb->snd_wl2 = iss;\r
+ pcb->snd_nxt = iss;\r
+ pcb->snd_max = iss;\r
+ pcb->lastack = iss;\r
+ pcb->snd_lbb = iss; \r
+ pcb->tmr = tcp_ticks;\r
+\r
+ pcb->polltmr = 0;\r
+\r
+#if LWIP_CALLBACK_API\r
+ pcb->recv = tcp_recv_null;\r
+#endif /* LWIP_CALLBACK_API */ \r
+ \r
+ /* Init KEEPALIVE timer */\r
+ pcb->keepalive = TCP_KEEPDEFAULT;\r
+ pcb->keep_cnt = 0;\r
+ }\r
+ return pcb;\r
+}\r
+\r
+/**\r
+ * Creates a new TCP protocol control block but doesn't place it on\r
+ * any of the TCP PCB lists.\r
+ *\r
+ * @internal: Maybe there should be a idle TCP PCB list where these\r
+ * PCBs are put on. We can then implement port reservation using\r
+ * tcp_bind(). Currently, we lack this (BSD socket type of) feature.\r
+ */\r
+\r
+struct tcp_pcb *\r
+tcp_new(void)\r
+{\r
+ return tcp_alloc(TCP_PRIO_NORMAL);\r
+}\r
+\r
+/*\r
+ * tcp_arg():\r
+ *\r
+ * Used to specify the argument that should be passed callback\r
+ * functions.\r
+ *\r
+ */ \r
+\r
+void\r
+tcp_arg(struct tcp_pcb *pcb, void *arg)\r
+{ \r
+ pcb->callback_arg = arg;\r
+}\r
+#if LWIP_CALLBACK_API\r
+\r
+/**\r
+ * Used to specify the function that should be called when a TCP\r
+ * connection receives data.\r
+ *\r
+ */ \r
+void\r
+tcp_recv(struct tcp_pcb *pcb,\r
+ err_t (* recv)(void *arg, struct tcp_pcb *tpcb, struct pbuf *p, err_t err))\r
+{\r
+ pcb->recv = recv;\r
+}\r
+\r
+/**\r
+ * Used to specify the function that should be called when TCP data\r
+ * has been successfully delivered to the remote host.\r
+ *\r
+ */ \r
+\r
+void\r
+tcp_sent(struct tcp_pcb *pcb,\r
+ err_t (* sent)(void *arg, struct tcp_pcb *tpcb, u16_t len))\r
+{\r
+ pcb->sent = sent;\r
+}\r
+\r
+/**\r
+ * Used to specify the function that should be called when a fatal error\r
+ * has occured on the connection.\r
+ *\r
+ */ \r
+void\r
+tcp_err(struct tcp_pcb *pcb,\r
+ void (* errf)(void *arg, err_t err))\r
+{\r
+ pcb->errf = errf;\r
+}\r
+\r
+/**\r
+ * Used for specifying the function that should be called when a\r
+ * LISTENing connection has been connected to another host.\r
+ *\r
+ */ \r
+void\r
+tcp_accept(struct tcp_pcb *pcb,\r
+ err_t (* accept)(void *arg, struct tcp_pcb *newpcb, err_t err))\r
+{\r
+ ((struct tcp_pcb_listen *)pcb)->accept = accept;\r
+}\r
+#endif /* LWIP_CALLBACK_API */\r
+\r
+\r
+/**\r
+ * Used to specify the function that should be called periodically\r
+ * from TCP. The interval is specified in terms of the TCP coarse\r
+ * timer interval, which is called twice a second.\r
+ *\r
+ */ \r
+void\r
+tcp_poll(struct tcp_pcb *pcb,\r
+ err_t (* poll)(void *arg, struct tcp_pcb *tpcb), u8_t interval)\r
+{\r
+#if LWIP_CALLBACK_API\r
+ pcb->poll = poll;\r
+#endif /* LWIP_CALLBACK_API */ \r
+ pcb->pollinterval = interval;\r
+}\r
+\r
+/**\r
+ * Purges a TCP PCB. Removes any buffered data and frees the buffer memory.\r
+ *\r
+ */\r
+void\r
+tcp_pcb_purge(struct tcp_pcb *pcb)\r
+{\r
+ if (pcb->state != CLOSED &&\r
+ pcb->state != TIME_WAIT &&\r
+ pcb->state != LISTEN) {\r
+\r
+ LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge\n"));\r
+ \r
+ if (pcb->unsent != NULL) { \r
+ LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: not all data sent\n"));\r
+ }\r
+ if (pcb->unacked != NULL) { \r
+ LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->unacked\n"));\r
+ }\r
+#if TCP_QUEUE_OOSEQ /* LW */\r
+ if (pcb->ooseq != NULL) { \r
+ LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->ooseq\n"));\r
+ }\r
+ \r
+ tcp_segs_free(pcb->ooseq);\r
+ pcb->ooseq = NULL;\r
+#endif /* TCP_QUEUE_OOSEQ */\r
+ tcp_segs_free(pcb->unsent);\r
+ tcp_segs_free(pcb->unacked);\r
+ pcb->unacked = pcb->unsent = NULL;\r
+ }\r
+}\r
+\r
+/**\r
+ * Purges the PCB and removes it from a PCB list. Any delayed ACKs are sent first.\r
+ *\r
+ */\r
+void\r
+tcp_pcb_remove(struct tcp_pcb **pcblist, struct tcp_pcb *pcb)\r
+{\r
+ TCP_RMV(pcblist, pcb);\r
+\r
+ tcp_pcb_purge(pcb);\r
+ \r
+ /* if there is an outstanding delayed ACKs, send it */\r
+ if (pcb->state != TIME_WAIT &&\r
+ pcb->state != LISTEN &&\r
+ pcb->flags & TF_ACK_DELAY) {\r
+ pcb->flags |= TF_ACK_NOW;\r
+ tcp_output(pcb);\r
+ } \r
+ pcb->state = CLOSED;\r
+\r
+ LWIP_ASSERT("tcp_pcb_remove: tcp_pcbs_sane()", tcp_pcbs_sane());\r
+}\r
+\r
+/**\r
+ * Calculates a new initial sequence number for new connections.\r
+ *\r
+ */\r
+u32_t\r
+tcp_next_iss(void)\r
+{\r
+ static u32_t iss = 6510;\r
+ \r
+ iss += tcp_ticks; /* XXX */\r
+ return iss;\r
+}\r
+\r
+#if TCP_DEBUG || TCP_INPUT_DEBUG || TCP_OUTPUT_DEBUG\r
+void\r
+tcp_debug_print(struct tcp_hdr *tcphdr)\r
+{\r
+ LWIP_DEBUGF(TCP_DEBUG, ("TCP header:\n"));\r
+ LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));\r
+ LWIP_DEBUGF(TCP_DEBUG, ("| %5u | %5u | (src port, dest port)\n",\r
+ ntohs(tcphdr->src), ntohs(tcphdr->dest)));\r
+ LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));\r
+ LWIP_DEBUGF(TCP_DEBUG, ("| %010lu | (seq no)\n",\r
+ ntohl(tcphdr->seqno)));\r
+ LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));\r
+ LWIP_DEBUGF(TCP_DEBUG, ("| %010lu | (ack no)\n",\r
+ ntohl(tcphdr->ackno)));\r
+ LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));\r
+ LWIP_DEBUGF(TCP_DEBUG, ("| %2u | |%u%u%u%u%u%u| %5u | (hdrlen, flags (",\r
+ TCPH_HDRLEN(tcphdr),\r
+ TCPH_FLAGS(tcphdr) >> 5 & 1,\r
+ TCPH_FLAGS(tcphdr) >> 4 & 1,\r
+ TCPH_FLAGS(tcphdr) >> 3 & 1,\r
+ TCPH_FLAGS(tcphdr) >> 2 & 1,\r
+ TCPH_FLAGS(tcphdr) >> 1 & 1,\r
+ TCPH_FLAGS(tcphdr) & 1,\r
+ ntohs(tcphdr->wnd)));\r
+ tcp_debug_print_flags(TCPH_FLAGS(tcphdr));\r
+ LWIP_DEBUGF(TCP_DEBUG, ("), win)\n"));\r
+ LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));\r
+ LWIP_DEBUGF(TCP_DEBUG, ("| 0x%04x | %5u | (chksum, urgp)\n",\r
+ ntohs(tcphdr->chksum), ntohs(tcphdr->urgp)));\r
+ LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));\r
+}\r
+\r
+void\r
+tcp_debug_print_state(enum tcp_state s)\r
+{\r
+ LWIP_DEBUGF(TCP_DEBUG, ("State: "));\r
+ switch (s) {\r
+ case CLOSED:\r
+ LWIP_DEBUGF(TCP_DEBUG, ("CLOSED\n"));\r
+ break;\r
+ case LISTEN:\r
+ LWIP_DEBUGF(TCP_DEBUG, ("LISTEN\n"));\r
+ break;\r
+ case SYN_SENT:\r
+ LWIP_DEBUGF(TCP_DEBUG, ("SYN_SENT\n"));\r
+ break;\r
+ case SYN_RCVD:\r
+ LWIP_DEBUGF(TCP_DEBUG, ("SYN_RCVD\n"));\r
+ break;\r
+ case ESTABLISHED:\r
+ LWIP_DEBUGF(TCP_DEBUG, ("ESTABLISHED\n"));\r
+ break;\r
+ case FIN_WAIT_1:\r
+ LWIP_DEBUGF(TCP_DEBUG, ("FIN_WAIT_1\n"));\r
+ break;\r
+ case FIN_WAIT_2:\r
+ LWIP_DEBUGF(TCP_DEBUG, ("FIN_WAIT_2\n"));\r
+ break;\r
+ case CLOSE_WAIT:\r
+ LWIP_DEBUGF(TCP_DEBUG, ("CLOSE_WAIT\n"));\r
+ break;\r
+ case CLOSING:\r
+ LWIP_DEBUGF(TCP_DEBUG, ("CLOSING\n"));\r
+ break;\r
+ case LAST_ACK:\r
+ LWIP_DEBUGF(TCP_DEBUG, ("LAST_ACK\n"));\r
+ break;\r
+ case TIME_WAIT:\r
+ LWIP_DEBUGF(TCP_DEBUG, ("TIME_WAIT\n"));\r
+ break;\r
+ }\r
+}\r
+\r
+void\r
+tcp_debug_print_flags(u8_t flags)\r
+{\r
+ if (flags & TCP_FIN) {\r
+ LWIP_DEBUGF(TCP_DEBUG, ("FIN "));\r
+ }\r
+ if (flags & TCP_SYN) {\r
+ LWIP_DEBUGF(TCP_DEBUG, ("SYN "));\r
+ }\r
+ if (flags & TCP_RST) {\r
+ LWIP_DEBUGF(TCP_DEBUG, ("RST "));\r
+ }\r
+ if (flags & TCP_PSH) {\r
+ LWIP_DEBUGF(TCP_DEBUG, ("PSH "));\r
+ }\r
+ if (flags & TCP_ACK) {\r
+ LWIP_DEBUGF(TCP_DEBUG, ("ACK "));\r
+ }\r
+ if (flags & TCP_URG) {\r
+ LWIP_DEBUGF(TCP_DEBUG, ("URG "));\r
+ }\r
+ if (flags & TCP_ECE) {\r
+ LWIP_DEBUGF(TCP_DEBUG, ("ECE "));\r
+ }\r
+ if (flags & TCP_CWR) {\r
+ LWIP_DEBUGF(TCP_DEBUG, ("CWR "));\r
+ }\r
+}\r
+\r
+void\r
+tcp_debug_print_pcbs(void)\r
+{\r
+ struct tcp_pcb *pcb;\r
+ LWIP_DEBUGF(TCP_DEBUG, ("Active PCB states:\n"));\r
+ for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {\r
+ LWIP_DEBUGF(TCP_DEBUG, ("Local port %u, foreign port %u snd_nxt %lu rcv_nxt %lu ",\r
+ pcb->local_port, pcb->remote_port,\r
+ pcb->snd_nxt, pcb->rcv_nxt));\r
+ tcp_debug_print_state(pcb->state);\r
+ } \r
+ LWIP_DEBUGF(TCP_DEBUG, ("Listen PCB states:\n"));\r
+ for(pcb = (struct tcp_pcb *)tcp_listen_pcbs.pcbs; pcb != NULL; pcb = pcb->next) {\r
+ LWIP_DEBUGF(TCP_DEBUG, ("Local port %u, foreign port %u snd_nxt %lu rcv_nxt %lu ",\r
+ pcb->local_port, pcb->remote_port,\r
+ pcb->snd_nxt, pcb->rcv_nxt));\r
+ tcp_debug_print_state(pcb->state);\r
+ } \r
+ LWIP_DEBUGF(TCP_DEBUG, ("TIME-WAIT PCB states:\n"));\r
+ for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {\r
+ LWIP_DEBUGF(TCP_DEBUG, ("Local port %u, foreign port %u snd_nxt %lu rcv_nxt %lu ",\r
+ pcb->local_port, pcb->remote_port,\r
+ pcb->snd_nxt, pcb->rcv_nxt));\r
+ tcp_debug_print_state(pcb->state);\r
+ } \r
+}\r
+\r
+int\r
+tcp_pcbs_sane(void)\r
+{\r
+ struct tcp_pcb *pcb;\r
+ for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {\r
+ LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != CLOSED", pcb->state != CLOSED);\r
+ LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != LISTEN", pcb->state != LISTEN);\r
+ LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != TIME-WAIT", pcb->state != TIME_WAIT);\r
+ }\r
+ for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {\r
+ LWIP_ASSERT("tcp_pcbs_sane: tw pcb->state == TIME-WAIT", pcb->state == TIME_WAIT);\r
+ }\r
+ return 1;\r
+}\r
+#endif /* TCP_DEBUG */\r
+#endif /* LWIP_TCP */\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/**
+ * @file
+ *
+ * Transmission Control Protocol, incoming traffic
+ *
+ * The input processing functions of TCP.
+ *
+ * These functions are generally called in the order (ip_input() ->) tcp_input() ->
+ * tcp_process() -> tcp_receive() (-> application).
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+#include "lwip/def.h"
+#include "lwip/opt.h"
+
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/mem.h"
+#include "lwip/memp.h"
+
+#include "lwip/inet.h"
+#include "lwip/tcp.h"
+
+#include "lwip/stats.h"
+
+#include "arch/perf.h"
+#if LWIP_TCP
+/* These variables are global to all functions involved in the input
+ processing of TCP segments. They are set by the tcp_input()
+ function. */
+static struct tcp_seg inseg;
+static struct tcp_hdr *tcphdr;
+static struct ip_hdr *iphdr;
+static u32_t seqno, ackno;
+static u8_t flags;
+static u16_t tcplen;
+
+static u8_t recv_flags;
+static struct pbuf *recv_data;
+
+struct tcp_pcb *tcp_input_pcb;
+
+/* Forward declarations. */
+static err_t tcp_process(struct tcp_pcb *pcb);
+static void tcp_receive(struct tcp_pcb *pcb);
+static void tcp_parseopt(struct tcp_pcb *pcb);
+
+static err_t tcp_listen_input(struct tcp_pcb_listen *pcb);
+static err_t tcp_timewait_input(struct tcp_pcb *pcb);
+
+
+/* tcp_input:
+ *
+ * The initial input processing of TCP. It verifies the TCP header, demultiplexes
+ * the segment between the PCBs and passes it on to tcp_process(), which implements
+ * the TCP finite state machine. This function is called by the IP layer (in
+ * ip_input()).
+ */
+
+void
+tcp_input(struct pbuf *p, struct netif *inp)
+{
+ struct tcp_pcb *pcb, *prev;
+ struct tcp_pcb_listen *lpcb;
+ u8_t hdrlen;
+ err_t err;
+
+#if SO_REUSE
+ struct tcp_pcb *pcb_temp;
+ int reuse = 0;
+ int reuse_port = 0;
+#endif /* SO_REUSE */
+
+ PERF_START;
+
+ TCP_STATS_INC(tcp.recv);
+
+ iphdr = p->payload;
+ tcphdr = (struct tcp_hdr *)((u8_t *)p->payload + IPH_HL(iphdr) * 4);
+
+#if TCP_INPUT_DEBUG
+ tcp_debug_print(tcphdr);
+#endif
+
+ /* remove header from payload */
+ if (pbuf_header(p, -((s16_t)(IPH_HL(iphdr) * 4))) || (p->tot_len < sizeof(struct tcp_hdr))) {
+ /* drop short packets */
+ LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: short packet (%u bytes) discarded\n", p->tot_len));
+ TCP_STATS_INC(tcp.lenerr);
+ TCP_STATS_INC(tcp.drop);
+ pbuf_free(p);
+ return;
+ }
+
+ /* Don't even process incoming broadcasts/multicasts. */
+ if (ip_addr_isbroadcast(&(iphdr->dest), inp) ||
+ ip_addr_ismulticast(&(iphdr->dest))) {
+ pbuf_free(p);
+ return;
+ }
+
+#if CHECKSUM_CHECK_TCP
+ /* Verify TCP checksum. */
+ if (inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src),
+ (struct ip_addr *)&(iphdr->dest),
+ IP_PROTO_TCP, p->tot_len) != 0) {
+ LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packet discarded due to failing checksum 0x%04x\n",
+ inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src), (struct ip_addr *)&(iphdr->dest),
+ IP_PROTO_TCP, p->tot_len)));
+#if TCP_DEBUG
+ tcp_debug_print(tcphdr);
+#endif /* TCP_DEBUG */
+ TCP_STATS_INC(tcp.chkerr);
+ TCP_STATS_INC(tcp.drop);
+
+ pbuf_free(p);
+ return;
+ }
+#endif
+
+ /* Move the payload pointer in the pbuf so that it points to the
+ TCP data instead of the TCP header. */
+ hdrlen = TCPH_HDRLEN(tcphdr);
+ pbuf_header(p, -(hdrlen * 4));
+
+ /* Convert fields in TCP header to host byte order. */
+ tcphdr->src = ntohs(tcphdr->src);
+ tcphdr->dest = ntohs(tcphdr->dest);
+ seqno = tcphdr->seqno = ntohl(tcphdr->seqno);
+ ackno = tcphdr->ackno = ntohl(tcphdr->ackno);
+ tcphdr->wnd = ntohs(tcphdr->wnd);
+
+ flags = TCPH_FLAGS(tcphdr) & TCP_FLAGS;
+ tcplen = p->tot_len + ((flags & TCP_FIN || flags & TCP_SYN)? 1: 0);
+
+ /* Demultiplex an incoming segment. First, we check if it is destined
+ for an active connection. */
+ prev = NULL;
+
+#if SO_REUSE
+ pcb_temp = tcp_active_pcbs;
+
+ again_1:
+
+ /* Iterate through the TCP pcb list for a fully matching pcb */
+ for(pcb = pcb_temp; pcb != NULL; pcb = pcb->next) {
+#else /* SO_REUSE */
+ for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
+#endif /* SO_REUSE */
+ LWIP_ASSERT("tcp_input: active pcb->state != CLOSED", pcb->state != CLOSED);
+ LWIP_ASSERT("tcp_input: active pcb->state != TIME-WAIT", pcb->state != TIME_WAIT);
+ LWIP_ASSERT("tcp_input: active pcb->state != LISTEN", pcb->state != LISTEN);
+ if (pcb->remote_port == tcphdr->src &&
+ pcb->local_port == tcphdr->dest &&
+ ip_addr_cmp(&(pcb->remote_ip), &(iphdr->src)) &&
+ ip_addr_cmp(&(pcb->local_ip), &(iphdr->dest))) {
+
+#if SO_REUSE
+ if(pcb->so_options & SOF_REUSEPORT) {
+ if(reuse) {
+ /* We processed one PCB already */
+ LWIP_DEBUGF(TCP_INPUT_DEBUG,("tcp_input: second or later PCB and SOF_REUSEPORT set.\n"));
+ } else {
+ /* First PCB with this address */
+ LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: first PCB and SOF_REUSEPORT set.\n"));
+ reuse = 1;
+ }
+
+ reuse_port = 1;
+ p->ref++;
+
+ /* We want to search on next socket after receiving */
+ pcb_temp = pcb->next;
+
+ LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: reference counter on PBUF set to %i\n", p->ref));
+ } else {
+ if(reuse) {
+ /* We processed one PCB already */
+ LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: second or later PCB but SOF_REUSEPORT not set !\n"));
+ }
+ }
+#endif /* SO_REUSE */
+
+ /* Move this PCB to the front of the list so that subsequent
+ lookups will be faster (we exploit locality in TCP segment
+ arrivals). */
+ LWIP_ASSERT("tcp_input: pcb->next != pcb (before cache)", pcb->next != pcb);
+ if (prev != NULL) {
+ prev->next = pcb->next;
+ pcb->next = tcp_active_pcbs;
+ tcp_active_pcbs = pcb;
+ }
+ LWIP_ASSERT("tcp_input: pcb->next != pcb (after cache)", pcb->next != pcb);
+ break;
+ }
+ prev = pcb;
+ }
+
+ if (pcb == NULL) {
+ /* If it did not go to an active connection, we check the connections
+ in the TIME-WAIT state. */
+
+ for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
+ LWIP_ASSERT("tcp_input: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT);
+ if (pcb->remote_port == tcphdr->src &&
+ pcb->local_port == tcphdr->dest &&
+ ip_addr_cmp(&(pcb->remote_ip), &(iphdr->src)) &&
+ ip_addr_cmp(&(pcb->local_ip), &(iphdr->dest))) {
+ /* We don't really care enough to move this PCB to the front
+ of the list since we are not very likely to receive that
+ many segments for connections in TIME-WAIT. */
+ LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packed for TIME_WAITing connection.\n"));
+ tcp_timewait_input(pcb);
+ pbuf_free(p);
+ return;
+ }
+ }
+
+ /* Finally, if we still did not get a match, we check all PCBs that
+ are LISTENing for incoming connections. */
+ prev = NULL;
+ for(lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) {
+ if ((ip_addr_isany(&(lpcb->local_ip)) ||
+ ip_addr_cmp(&(lpcb->local_ip), &(iphdr->dest))) &&
+ lpcb->local_port == tcphdr->dest) {
+ /* Move this PCB to the front of the list so that subsequent
+ lookups will be faster (we exploit locality in TCP segment
+ arrivals). */
+ if (prev != NULL) {
+ ((struct tcp_pcb_listen *)prev)->next = lpcb->next;
+ /* our successor is the remainder of the listening list */
+ lpcb->next = tcp_listen_pcbs.listen_pcbs;
+ /* put this listening pcb at the head of the listening list */
+ tcp_listen_pcbs.listen_pcbs = lpcb;
+ }
+
+ LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packed for LISTENing connection.\n"));
+ tcp_listen_input(lpcb);
+ pbuf_free(p);
+ return;
+ }
+ prev = (struct tcp_pcb *)lpcb;
+ }
+ }
+
+#if TCP_INPUT_DEBUG
+ LWIP_DEBUGF(TCP_INPUT_DEBUG, ("+-+-+-+-+-+-+-+-+-+-+-+-+-+- tcp_input: flags "));
+ tcp_debug_print_flags(TCPH_FLAGS(tcphdr));
+ LWIP_DEBUGF(TCP_INPUT_DEBUG, ("-+-+-+-+-+-+-+-+-+-+-+-+-+-+\n"));
+#endif /* TCP_INPUT_DEBUG */
+
+
+ if (pcb != NULL) {
+ /* The incoming segment belongs to a connection. */
+#if TCP_INPUT_DEBUG
+#if TCP_DEBUG
+ tcp_debug_print_state(pcb->state);
+#endif /* TCP_DEBUG */
+#endif /* TCP_INPUT_DEBUG */
+
+ /* Set up a tcp_seg structure. */
+ inseg.next = NULL;
+ inseg.len = p->tot_len;
+ inseg.dataptr = p->payload;
+ inseg.p = p;
+ inseg.tcphdr = tcphdr;
+
+ recv_data = NULL;
+ recv_flags = 0;
+
+ tcp_input_pcb = pcb;
+ err = tcp_process(pcb);
+ tcp_input_pcb = NULL;
+ /* A return value of ERR_ABRT means that tcp_abort() was called
+ and that the pcb has been freed. If so, we don't do anything. */
+ if (err != ERR_ABRT) {
+ if (recv_flags & TF_RESET) {
+ /* TF_RESET means that the connection was reset by the other
+ end. We then call the error callback to inform the
+ application that the connection is dead before we
+ deallocate the PCB. */
+ TCP_EVENT_ERR(pcb->errf, pcb->callback_arg, ERR_RST);
+ tcp_pcb_remove(&tcp_active_pcbs, pcb);
+ memp_free(MEMP_TCP_PCB, pcb);
+ } else if (recv_flags & TF_CLOSED) {
+ /* The connection has been closed and we will deallocate the
+ PCB. */
+ tcp_pcb_remove(&tcp_active_pcbs, pcb);
+ memp_free(MEMP_TCP_PCB, pcb);
+ } else {
+ err = ERR_OK;
+ /* If the application has registered a "sent" function to be
+ called when new send buffer space is available, we call it
+ now. */
+ if (pcb->acked > 0) {
+ TCP_EVENT_SENT(pcb, pcb->acked, err);
+ }
+
+ if (recv_data != NULL) {
+ /* Notify application that data has been received. */
+ TCP_EVENT_RECV(pcb, recv_data, ERR_OK, err);
+ }
+
+ /* If a FIN segment was received, we call the callback
+ function with a NULL buffer to indicate EOF. */
+ if (recv_flags & TF_GOT_FIN) {
+ TCP_EVENT_RECV(pcb, NULL, ERR_OK, err);
+ }
+ /* If there were no errors, we try to send something out. */
+ if (err == ERR_OK) {
+ tcp_output(pcb);
+ }
+ }
+ }
+
+
+ /* We deallocate the incoming pbuf. If it was buffered by the
+ application, the application should have called pbuf_ref() to
+ increase the reference counter in the pbuf. If so, the buffer
+ isn't actually deallocated by the call to pbuf_free(), only the
+ reference count is decreased. */
+ if (inseg.p != NULL) pbuf_free(inseg.p);
+#if TCP_INPUT_DEBUG
+#if TCP_DEBUG
+ tcp_debug_print_state(pcb->state);
+#endif /* TCP_DEBUG */
+#endif /* TCP_INPUT_DEBUG */
+#if SO_REUSE
+ /* First socket should receive now */
+ if(reuse_port) {
+ LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: searching next PCB.\n"));
+ reuse_port = 0;
+
+ /* We are searching connected sockets */
+ goto again_1;
+ }
+#endif /* SO_REUSE */
+
+ } else {
+#if SO_REUSE
+ if(reuse) {
+ LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: freeing PBUF with reference counter set to %i\n", p->ref));
+ pbuf_free(p);
+ goto end;
+ }
+#endif /* SO_REUSE */
+ /* If no matching PCB was found, send a TCP RST (reset) to the
+ sender. */
+ LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_input: no PCB match found, resetting.\n"));
+ if (!(TCPH_FLAGS(tcphdr) & TCP_RST)) {
+ TCP_STATS_INC(tcp.proterr);
+ TCP_STATS_INC(tcp.drop);
+ tcp_rst(ackno, seqno + tcplen,
+ &(iphdr->dest), &(iphdr->src),
+ tcphdr->dest, tcphdr->src);
+ }
+ pbuf_free(p);
+ }
+#if SO_REUSE
+ end:
+#endif /* SO_REUSE */
+ LWIP_ASSERT("tcp_input: tcp_pcbs_sane()", tcp_pcbs_sane());
+ PERF_STOP("tcp_input");
+}
+
+/* tcp_listen_input():
+ *
+ * Called by tcp_input() when a segment arrives for a listening
+ * connection.
+ */
+
+static err_t
+tcp_listen_input(struct tcp_pcb_listen *pcb)
+{
+ struct tcp_pcb *npcb;
+ u32_t optdata;
+
+ /* In the LISTEN state, we check for incoming SYN segments,
+ creates a new PCB, and responds with a SYN|ACK. */
+ if (flags & TCP_ACK) {
+ /* For incoming segments with the ACK flag set, respond with a
+ RST. */
+ LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_listen_input: ACK in LISTEN, sending reset\n"));
+ tcp_rst(ackno + 1, seqno + tcplen,
+ &(iphdr->dest), &(iphdr->src),
+ tcphdr->dest, tcphdr->src);
+ } else if (flags & TCP_SYN) {
+ LWIP_DEBUGF(TCP_DEBUG, ("TCP connection request %u -> %u.\n", tcphdr->src, tcphdr->dest));
+ npcb = tcp_alloc(pcb->prio);
+ /* If a new PCB could not be created (probably due to lack of memory),
+ we don't do anything, but rely on the sender will retransmit the
+ SYN at a time when we have more memory available. */
+ if (npcb == NULL) {
+ LWIP_DEBUGF(TCP_DEBUG, ("tcp_listen_input: could not allocate PCB\n"));
+ TCP_STATS_INC(tcp.memerr);
+ return ERR_MEM;
+ }
+ /* Set up the new PCB. */
+ ip_addr_set(&(npcb->local_ip), &(iphdr->dest));
+ npcb->local_port = pcb->local_port;
+ ip_addr_set(&(npcb->remote_ip), &(iphdr->src));
+ npcb->remote_port = tcphdr->src;
+ npcb->state = SYN_RCVD;
+ npcb->rcv_nxt = seqno + 1;
+ npcb->snd_wnd = tcphdr->wnd;
+ npcb->ssthresh = npcb->snd_wnd;
+ npcb->snd_wl1 = seqno - 1;/* initialise to seqno-1 to force window update */
+ npcb->callback_arg = pcb->callback_arg;
+#if LWIP_CALLBACK_API
+ npcb->accept = pcb->accept;
+#endif /* LWIP_CALLBACK_API */
+ /* inherit socket options */
+ npcb->so_options = pcb->so_options & (SOF_DEBUG|SOF_DONTROUTE|SOF_KEEPALIVE|SOF_OOBINLINE|SOF_LINGER);
+ /* Register the new PCB so that we can begin receiving segments
+ for it. */
+ TCP_REG(&tcp_active_pcbs, npcb);
+
+ /* Parse any options in the SYN. */
+ tcp_parseopt(npcb);
+
+ /* Build an MSS option. */
+ optdata = htonl(((u32_t)2 << 24) |
+ ((u32_t)4 << 16) |
+ (((u32_t)npcb->mss / 256) << 8) |
+ (npcb->mss & 255));
+ /* Send a SYN|ACK together with the MSS option. */
+ tcp_enqueue(npcb, NULL, 0, TCP_SYN | TCP_ACK, 0, (u8_t *)&optdata, 4);
+ return tcp_output(npcb);
+ }
+ return ERR_OK;
+}
+
+/* tcp_timewait_input():
+ *
+ * Called by tcp_input() when a segment arrives for a connection in
+ * TIME_WAIT.
+ */
+
+static err_t
+tcp_timewait_input(struct tcp_pcb *pcb)
+{
+ if (TCP_SEQ_GT(seqno + tcplen, pcb->rcv_nxt)) {
+ pcb->rcv_nxt = seqno + tcplen;
+ }
+ if (tcplen > 0) {
+ tcp_ack_now(pcb);
+ }
+ return tcp_output(pcb);
+}
+
+/* tcp_process
+ *
+ * Implements the TCP state machine. Called by tcp_input. In some
+ * states tcp_receive() is called to receive data. The tcp_seg
+ * argument will be freed by the caller (tcp_input()) unless the
+ * recv_data pointer in the pcb is set.
+ */
+
+static err_t
+tcp_process(struct tcp_pcb *pcb)
+{
+ struct tcp_seg *rseg;
+ u8_t acceptable = 0;
+ err_t err;
+
+
+ err = ERR_OK;
+
+ /* Process incoming RST segments. */
+ if (flags & TCP_RST) {
+ /* First, determine if the reset is acceptable. */
+ if (pcb->state == SYN_SENT) {
+ if (ackno == pcb->snd_nxt) {
+ acceptable = 1;
+ }
+ } else {
+ /*if (TCP_SEQ_GEQ(seqno, pcb->rcv_nxt) &&
+ TCP_SEQ_LEQ(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) {
+ */
+ if(TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt+pcb->rcv_wnd)){
+ acceptable = 1;
+ }
+ }
+
+ if (acceptable) {
+ LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: Connection RESET\n"));
+ LWIP_ASSERT("tcp_input: pcb->state != CLOSED", pcb->state != CLOSED);
+ recv_flags = TF_RESET;
+ pcb->flags &= ~TF_ACK_DELAY;
+ return ERR_RST;
+ } else {
+ LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: unacceptable reset seqno %lu rcv_nxt %lu\n",
+ seqno, pcb->rcv_nxt));
+ LWIP_DEBUGF(TCP_DEBUG, ("tcp_process: unacceptable reset seqno %lu rcv_nxt %lu\n",
+ seqno, pcb->rcv_nxt));
+ return ERR_OK;
+ }
+ }
+
+ /* Update the PCB (in)activity timer. */
+ pcb->tmr = tcp_ticks;
+ pcb->keep_cnt = 0;
+
+ /* Do different things depending on the TCP state. */
+ switch (pcb->state) {
+ case SYN_SENT:
+ LWIP_DEBUGF(TCP_INPUT_DEBUG, ("SYN-SENT: ackno %lu pcb->snd_nxt %lu unacked %lu\n", ackno,
+ pcb->snd_nxt, ntohl(pcb->unacked->tcphdr->seqno)));
+ if ((flags & TCP_ACK) && (flags & TCP_SYN)
+ && ackno == ntohl(pcb->unacked->tcphdr->seqno) + 1) {
+ pcb->snd_buf ++;
+ pcb->rcv_nxt = seqno + 1;
+ pcb->lastack = ackno;
+ pcb->snd_wnd = tcphdr->wnd;
+ pcb->snd_wl1 = seqno - 1; /* initialise to seqno - 1 to force window update */
+ pcb->state = ESTABLISHED;
+ pcb->cwnd = pcb->mss;
+ --pcb->snd_queuelen;
+ LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_process: SYN-SENT --queuelen %u\n", (unsigned int)pcb->snd_queuelen));
+ rseg = pcb->unacked;
+ pcb->unacked = rseg->next;
+ tcp_seg_free(rseg);
+
+ /* Parse any options in the SYNACK. */
+ tcp_parseopt(pcb);
+
+ /* Call the user specified function to call when sucessfully
+ * connected. */
+ TCP_EVENT_CONNECTED(pcb, ERR_OK, err);
+ tcp_ack(pcb);
+ }
+ break;
+ case SYN_RCVD:
+ if (flags & TCP_ACK &&
+ !(flags & TCP_RST)) {
+ /*if (TCP_SEQ_LT(pcb->lastack, ackno) &&
+ TCP_SEQ_LEQ(ackno, pcb->snd_nxt)) { */
+ if(TCP_SEQ_BETWEEN(ackno, pcb->lastack+1, pcb->snd_nxt)){
+ pcb->state = ESTABLISHED;
+ LWIP_DEBUGF(TCP_DEBUG, ("TCP connection established %u -> %u.\n", inseg.tcphdr->src, inseg.tcphdr->dest));
+#if LWIP_CALLBACK_API
+ LWIP_ASSERT("pcb->accept != NULL", pcb->accept != NULL);
+#endif
+ /* Call the accept function. */
+ TCP_EVENT_ACCEPT(pcb, ERR_OK, err);
+ if (err != ERR_OK) {
+ /* If the accept function returns with an error, we abort
+ * the connection. */
+ tcp_abort(pcb);
+ return ERR_ABRT;
+ }
+ /* If there was any data contained within this ACK,
+ * we'd better pass it on to the application as well. */
+ tcp_receive(pcb);
+ pcb->cwnd = pcb->mss;
+ }
+ }
+ break;
+ case CLOSE_WAIT:
+ /* FALLTHROUGH */
+ case ESTABLISHED:
+ tcp_receive(pcb);
+ if (flags & TCP_FIN) {
+ tcp_ack_now(pcb);
+ pcb->state = CLOSE_WAIT;
+ }
+ break;
+ case FIN_WAIT_1:
+ tcp_receive(pcb);
+ if (flags & TCP_FIN) {
+ if (flags & TCP_ACK && ackno == pcb->snd_nxt) {
+ LWIP_DEBUGF(TCP_DEBUG,
+ ("TCP connection closed %d -> %d.\n", inseg.tcphdr->src, inseg.tcphdr->dest));
+ tcp_ack_now(pcb);
+ tcp_pcb_purge(pcb);
+ TCP_RMV(&tcp_active_pcbs, pcb);
+ pcb->state = TIME_WAIT;
+ TCP_REG(&tcp_tw_pcbs, pcb);
+ } else {
+ tcp_ack_now(pcb);
+ pcb->state = CLOSING;
+ }
+ } else if (flags & TCP_ACK && ackno == pcb->snd_nxt) {
+ pcb->state = FIN_WAIT_2;
+ }
+ break;
+ case FIN_WAIT_2:
+ tcp_receive(pcb);
+ if (flags & TCP_FIN) {
+ LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed %u -> %u.\n", inseg.tcphdr->src, inseg.tcphdr->dest));
+ tcp_ack_now(pcb);
+ tcp_pcb_purge(pcb);
+ TCP_RMV(&tcp_active_pcbs, pcb);
+ pcb->state = TIME_WAIT;
+ TCP_REG(&tcp_tw_pcbs, pcb);
+ }
+ break;
+ case CLOSING:
+ tcp_receive(pcb);
+ if (flags & TCP_ACK && ackno == pcb->snd_nxt) {
+ LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed %u -> %u.\n", inseg.tcphdr->src, inseg.tcphdr->dest));
+ tcp_ack_now(pcb);
+ tcp_pcb_purge(pcb);
+ TCP_RMV(&tcp_active_pcbs, pcb);
+ pcb->state = TIME_WAIT;
+ TCP_REG(&tcp_tw_pcbs, pcb);
+ }
+ break;
+ case LAST_ACK:
+ tcp_receive(pcb);
+ if (flags & TCP_ACK && ackno == pcb->snd_nxt) {
+ LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed %u -> %u.\n", inseg.tcphdr->src, inseg.tcphdr->dest));
+ pcb->state = CLOSED;
+ recv_flags = TF_CLOSED;
+ }
+ break;
+ default:
+ break;
+ }
+
+ return ERR_OK;
+}
+
+/* tcp_receive:
+ *
+ * Called by tcp_process. Checks if the given segment is an ACK for outstanding
+ * data, and if so frees the memory of the buffered data. Next, is places the
+ * segment on any of the receive queues (pcb->recved or pcb->ooseq). If the segment
+ * is buffered, the pbuf is referenced by pbuf_ref so that it will not be freed until
+ * i it has been removed from the buffer.
+ *
+ * If the incoming segment constitutes an ACK for a segment that was used for RTT
+ * estimation, the RTT is estimated here as well.
+ */
+
+static void
+tcp_receive(struct tcp_pcb *pcb)
+{
+ struct tcp_seg *next;
+#if TCP_QUEUE_OOSEQ
+ struct tcp_seg *prev, *cseg;
+#endif
+ struct pbuf *p;
+ s32_t off;
+ int m;
+ u32_t right_wnd_edge;
+ u16_t new_tot_len;
+
+
+ if (flags & TCP_ACK) {
+ right_wnd_edge = pcb->snd_wnd + pcb->snd_wl1;
+
+ /* Update window. */
+ if (TCP_SEQ_LT(pcb->snd_wl1, seqno) ||
+ (pcb->snd_wl1 == seqno && TCP_SEQ_LT(pcb->snd_wl2, ackno)) ||
+ (pcb->snd_wl2 == ackno && tcphdr->wnd > pcb->snd_wnd)) {
+ pcb->snd_wnd = tcphdr->wnd;
+ pcb->snd_wl1 = seqno;
+ pcb->snd_wl2 = ackno;
+ LWIP_DEBUGF(TCP_WND_DEBUG, ("tcp_receive: window update %lu\n", pcb->snd_wnd));
+#if TCP_WND_DEBUG
+ } else {
+ if (pcb->snd_wnd != tcphdr->wnd) {
+ LWIP_DEBUGF(TCP_WND_DEBUG, ("tcp_receive: no window update lastack %lu snd_max %lu ackno %lu wl1 %lu seqno %lu wl2 %lu\n",
+ pcb->lastack, pcb->snd_max, ackno, pcb->snd_wl1, seqno, pcb->snd_wl2));
+ }
+#endif /* TCP_WND_DEBUG */
+ }
+
+
+ if (pcb->lastack == ackno) {
+ pcb->acked = 0;
+
+ if (pcb->snd_wl1 + pcb->snd_wnd == right_wnd_edge){
+ ++pcb->dupacks;
+ if (pcb->dupacks >= 3 && pcb->unacked != NULL) {
+ if (!(pcb->flags & TF_INFR)) {
+ /* This is fast retransmit. Retransmit the first unacked segment. */
+ LWIP_DEBUGF(TCP_FR_DEBUG, ("tcp_receive: dupacks %u (%lu), fast retransmit %lu\n",
+ (unsigned int)pcb->dupacks, pcb->lastack,
+ ntohl(pcb->unacked->tcphdr->seqno)));
+ tcp_rexmit(pcb);
+ /* Set ssthresh to max (FlightSize / 2, 2*SMSS) */
+ /*pcb->ssthresh = LWIP_MAX((pcb->snd_max -
+ pcb->lastack) / 2,
+ 2 * pcb->mss);*/
+ /* Set ssthresh to half of the minimum of the currenct cwnd and the advertised window */
+ if(pcb->cwnd > pcb->snd_wnd)
+ pcb->ssthresh = pcb->snd_wnd / 2;
+ else
+ pcb->ssthresh = pcb->cwnd / 2;
+
+ pcb->cwnd = pcb->ssthresh + 3 * pcb->mss;
+ pcb->flags |= TF_INFR;
+ } else {
+ /* Inflate the congestion window, but not if it means that
+ the value overflows. */
+ if ((u16_t)(pcb->cwnd + pcb->mss) > pcb->cwnd) {
+ pcb->cwnd += pcb->mss;
+ }
+ }
+ }
+ } else {
+ LWIP_DEBUGF(TCP_FR_DEBUG, ("tcp_receive: dupack averted %lu %lu\n",
+ pcb->snd_wl1 + pcb->snd_wnd, right_wnd_edge));
+ }
+ } else
+ /*if (TCP_SEQ_LT(pcb->lastack, ackno) &&
+ TCP_SEQ_LEQ(ackno, pcb->snd_max)) { */
+ if(TCP_SEQ_BETWEEN(ackno, pcb->lastack+1, pcb->snd_max)){
+ /* We come here when the ACK acknowledges new data. */
+
+ /* Reset the "IN Fast Retransmit" flag, since we are no longer
+ in fast retransmit. Also reset the congestion window to the
+ slow start threshold. */
+ if (pcb->flags & TF_INFR) {
+ pcb->flags &= ~TF_INFR;
+ pcb->cwnd = pcb->ssthresh;
+ }
+
+ /* Reset the number of retransmissions. */
+ pcb->nrtx = 0;
+
+ /* Reset the retransmission time-out. */
+ pcb->rto = (pcb->sa >> 3) + pcb->sv;
+
+ /* Update the send buffer space. */
+ pcb->acked = ackno - pcb->lastack;
+ pcb->snd_buf += pcb->acked;
+
+ /* Reset the fast retransmit variables. */
+ pcb->dupacks = 0;
+ pcb->lastack = ackno;
+
+ /* Update the congestion control variables (cwnd and
+ ssthresh). */
+ if (pcb->state >= ESTABLISHED) {
+ if (pcb->cwnd < pcb->ssthresh) {
+ if ((u16_t)(pcb->cwnd + pcb->mss) > pcb->cwnd) {
+ pcb->cwnd += pcb->mss;
+ }
+ LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_receive: slow start cwnd %u\n", pcb->cwnd));
+ } else {
+ u16_t new_cwnd = (pcb->cwnd + pcb->mss * pcb->mss / pcb->cwnd);
+ if (new_cwnd > pcb->cwnd) {
+ pcb->cwnd = new_cwnd;
+ }
+ LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_receive: congestion avoidance cwnd %u\n", pcb->cwnd));
+ }
+ }
+ LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: ACK for %lu, unacked->seqno %lu:%lu\n",
+ ackno,
+ pcb->unacked != NULL?
+ ntohl(pcb->unacked->tcphdr->seqno): 0,
+ pcb->unacked != NULL?
+ ntohl(pcb->unacked->tcphdr->seqno) + TCP_TCPLEN(pcb->unacked): 0));
+
+ /* Remove segment from the unacknowledged list if the incoming
+ ACK acknowlegdes them. */
+ while (pcb->unacked != NULL &&
+ TCP_SEQ_LEQ(ntohl(pcb->unacked->tcphdr->seqno) +
+ TCP_TCPLEN(pcb->unacked), ackno)) {
+ LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: removing %lu:%lu from pcb->unacked\n",
+ ntohl(pcb->unacked->tcphdr->seqno),
+ ntohl(pcb->unacked->tcphdr->seqno) +
+ TCP_TCPLEN(pcb->unacked)));
+
+ next = pcb->unacked;
+ pcb->unacked = pcb->unacked->next;
+
+ LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_receive: queuelen %u ... ", (unsigned int)pcb->snd_queuelen));
+ pcb->snd_queuelen -= pbuf_clen(next->p);
+ tcp_seg_free(next);
+
+ LWIP_DEBUGF(TCP_QLEN_DEBUG, ("%u (after freeing unacked)\n", (unsigned int)pcb->snd_queuelen));
+ if (pcb->snd_queuelen != 0) {
+ LWIP_ASSERT("tcp_receive: valid queue length", pcb->unacked != NULL ||
+ pcb->unsent != NULL);
+ }
+ }
+ pcb->polltmr = 0;
+ }
+
+ /* We go through the ->unsent list to see if any of the segments
+ on the list are acknowledged by the ACK. This may seem
+ strange since an "unsent" segment shouldn't be acked. The
+ rationale is that lwIP puts all outstanding segments on the
+ ->unsent list after a retransmission, so these segments may
+ in fact have been sent once. */
+ while (pcb->unsent != NULL &&
+ /*TCP_SEQ_LEQ(ntohl(pcb->unsent->tcphdr->seqno) + TCP_TCPLEN(pcb->unsent), ackno) &&
+ TCP_SEQ_LEQ(ackno, pcb->snd_max)*/
+ TCP_SEQ_BETWEEN(ackno, ntohl(pcb->unsent->tcphdr->seqno) + TCP_TCPLEN(pcb->unsent), pcb->snd_max)
+ ) {
+ LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: removing %lu:%lu from pcb->unsent\n",
+ ntohl(pcb->unsent->tcphdr->seqno), ntohl(pcb->unsent->tcphdr->seqno) +
+ TCP_TCPLEN(pcb->unsent)));
+
+ next = pcb->unsent;
+ pcb->unsent = pcb->unsent->next;
+ LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_receive: queuelen %u ... ", (unsigned int)pcb->snd_queuelen));
+ pcb->snd_queuelen -= pbuf_clen(next->p);
+ tcp_seg_free(next);
+ LWIP_DEBUGF(TCP_QLEN_DEBUG, ("%u (after freeing unsent)\n", (unsigned int)pcb->snd_queuelen));
+ if (pcb->snd_queuelen != 0) {
+ LWIP_ASSERT("tcp_receive: valid queue length",
+ pcb->unacked != NULL || pcb->unsent != NULL);
+ }
+
+ if (pcb->unsent != NULL) {
+ pcb->snd_nxt = htonl(pcb->unsent->tcphdr->seqno);
+ }
+ }
+ /* End of ACK for new data processing. */
+
+ LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: pcb->rttest %u rtseq %lu ackno %lu\n",
+ pcb->rttest, pcb->rtseq, ackno));
+
+ /* RTT estimation calculations. This is done by checking if the
+ incoming segment acknowledges the segment we use to take a
+ round-trip time measurement. */
+ if (pcb->rttest && TCP_SEQ_LT(pcb->rtseq, ackno)) {
+ m = tcp_ticks - pcb->rttest;
+
+ LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: experienced rtt %u ticks (%u msec).\n",
+ m, m * TCP_SLOW_INTERVAL));
+
+ /* This is taken directly from VJs original code in his paper */
+ m = m - (pcb->sa >> 3);
+ pcb->sa += m;
+ if (m < 0) {
+ m = -m;
+ }
+ m = m - (pcb->sv >> 2);
+ pcb->sv += m;
+ pcb->rto = (pcb->sa >> 3) + pcb->sv;
+
+ LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: RTO %u (%u miliseconds)\n",
+ pcb->rto, pcb->rto * TCP_SLOW_INTERVAL));
+
+ pcb->rttest = 0;
+ }
+ }
+
+ /* If the incoming segment contains data, we must process it
+ further. */
+ if (tcplen > 0) {
+ /* This code basically does three things:
+
+ +) If the incoming segment contains data that is the next
+ in-sequence data, this data is passed to the application. This
+ might involve trimming the first edge of the data. The rcv_nxt
+ variable and the advertised window are adjusted.
+
+ +) If the incoming segment has data that is above the next
+ sequence number expected (->rcv_nxt), the segment is placed on
+ the ->ooseq queue. This is done by finding the appropriate
+ place in the ->ooseq queue (which is ordered by sequence
+ number) and trim the segment in both ends if needed. An
+ immediate ACK is sent to indicate that we received an
+ out-of-sequence segment.
+
+ +) Finally, we check if the first segment on the ->ooseq queue
+ now is in sequence (i.e., if rcv_nxt >= ooseq->seqno). If
+ rcv_nxt > ooseq->seqno, we must trim the first edge of the
+ segment on ->ooseq before we adjust rcv_nxt. The data in the
+ segments that are now on sequence are chained onto the
+ incoming segment so that we only need to call the application
+ once.
+ */
+
+ /* First, we check if we must trim the first edge. We have to do
+ this if the sequence number of the incoming segment is less
+ than rcv_nxt, and the sequence number plus the length of the
+ segment is larger than rcv_nxt. */
+ /* if (TCP_SEQ_LT(seqno, pcb->rcv_nxt)){
+ if (TCP_SEQ_LT(pcb->rcv_nxt, seqno + tcplen)) {*/
+ if(TCP_SEQ_BETWEEN(pcb->rcv_nxt, seqno+1, seqno+tcplen-1)){
+ /* Trimming the first edge is done by pushing the payload
+ pointer in the pbuf downwards. This is somewhat tricky since
+ we do not want to discard the full contents of the pbuf up to
+ the new starting point of the data since we have to keep the
+ TCP header which is present in the first pbuf in the chain.
+
+ What is done is really quite a nasty hack: the first pbuf in
+ the pbuf chain is pointed to by inseg.p. Since we need to be
+ able to deallocate the whole pbuf, we cannot change this
+ inseg.p pointer to point to any of the later pbufs in the
+ chain. Instead, we point the ->payload pointer in the first
+ pbuf to data in one of the later pbufs. We also set the
+ inseg.data pointer to point to the right place. This way, the
+ ->p pointer will still point to the first pbuf, but the
+ ->p->payload pointer will point to data in another pbuf.
+
+ After we are done with adjusting the pbuf pointers we must
+ adjust the ->data pointer in the seg and the segment
+ length.*/
+
+ off = pcb->rcv_nxt - seqno;
+ p = inseg.p;
+ if (inseg.p->len < off) {
+ new_tot_len = inseg.p->tot_len - off;
+ while (p->len < off) {
+ off -= p->len;
+ /* KJM following line changed (with addition of new_tot_len var)
+ to fix bug #9076
+ inseg.p->tot_len -= p->len; */
+ p->tot_len = new_tot_len;
+ p->len = 0;
+ p = p->next;
+ }
+ pbuf_header(p, -off);
+ } else {
+ pbuf_header(inseg.p, -off);
+ }
+ /* KJM following line changed to use p->payload rather than inseg->p->payload
+ to fix bug #9076 */
+ inseg.dataptr = p->payload;
+ inseg.len -= pcb->rcv_nxt - seqno;
+ inseg.tcphdr->seqno = seqno = pcb->rcv_nxt;
+ }
+ else{
+ if(TCP_SEQ_LT(seqno, pcb->rcv_nxt)){
+ /* the whole segment is < rcv_nxt */
+ /* must be a duplicate of a packet that has already been correctly handled */
+
+ LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: duplicate seqno %lu\n", seqno));
+ tcp_ack_now(pcb);
+ }
+ }
+
+ /* The sequence number must be within the window (above rcv_nxt
+ and below rcv_nxt + rcv_wnd) in order to be further
+ processed. */
+ /*if (TCP_SEQ_GEQ(seqno, pcb->rcv_nxt) &&
+ TCP_SEQ_LT(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) {*/
+ if(TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd - 1)){
+ if (pcb->rcv_nxt == seqno) {
+ /* The incoming segment is the next in sequence. We check if
+ we have to trim the end of the segment and update rcv_nxt
+ and pass the data to the application. */
+#if TCP_QUEUE_OOSEQ
+ if (pcb->ooseq != NULL &&
+ TCP_SEQ_LEQ(pcb->ooseq->tcphdr->seqno, seqno + inseg.len)) {
+ /* We have to trim the second edge of the incoming
+ segment. */
+ inseg.len = pcb->ooseq->tcphdr->seqno - seqno;
+ pbuf_realloc(inseg.p, inseg.len);
+ }
+#endif /* TCP_QUEUE_OOSEQ */
+
+ tcplen = TCP_TCPLEN(&inseg);
+
+ pcb->rcv_nxt += tcplen;
+
+ /* Update the receiver's (our) window. */
+ if (pcb->rcv_wnd < tcplen) {
+ pcb->rcv_wnd = 0;
+ } else {
+ pcb->rcv_wnd -= tcplen;
+ }
+
+ /* If there is data in the segment, we make preparations to
+ pass this up to the application. The ->recv_data variable
+ is used for holding the pbuf that goes to the
+ application. The code for reassembling out-of-sequence data
+ chains its data on this pbuf as well.
+
+ If the segment was a FIN, we set the TF_GOT_FIN flag that will
+ be used to indicate to the application that the remote side has
+ closed its end of the connection. */
+ if (inseg.p->tot_len > 0) {
+ recv_data = inseg.p;
+ /* Since this pbuf now is the responsibility of the
+ application, we delete our reference to it so that we won't
+ (mistakingly) deallocate it. */
+ inseg.p = NULL;
+ }
+ if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) {
+ LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: received FIN.\n"));
+ recv_flags = TF_GOT_FIN;
+ }
+
+#if TCP_QUEUE_OOSEQ
+ /* We now check if we have segments on the ->ooseq queue that
+ is now in sequence. */
+ while (pcb->ooseq != NULL &&
+ pcb->ooseq->tcphdr->seqno == pcb->rcv_nxt) {
+
+ cseg = pcb->ooseq;
+ seqno = pcb->ooseq->tcphdr->seqno;
+
+ pcb->rcv_nxt += TCP_TCPLEN(cseg);
+ if (pcb->rcv_wnd < TCP_TCPLEN(cseg)) {
+ pcb->rcv_wnd = 0;
+ } else {
+ pcb->rcv_wnd -= TCP_TCPLEN(cseg);
+ }
+ if (cseg->p->tot_len > 0) {
+ /* Chain this pbuf onto the pbuf that we will pass to
+ the application. */
+ if (recv_data) {
+ pbuf_cat(recv_data, cseg->p);
+ } else {
+ recv_data = cseg->p;
+ }
+ cseg->p = NULL;
+ }
+ if (TCPH_FLAGS(cseg->tcphdr) & TCP_FIN) {
+ LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: dequeued FIN.\n"));
+ recv_flags = TF_GOT_FIN;
+ }
+
+
+ pcb->ooseq = cseg->next;
+ tcp_seg_free(cseg);
+ }
+#endif /* TCP_QUEUE_OOSEQ */
+
+
+ /* Acknowledge the segment(s). */
+ tcp_ack(pcb);
+
+ } else {
+ /* We get here if the incoming segment is out-of-sequence. */
+ tcp_ack_now(pcb);
+#if TCP_QUEUE_OOSEQ
+ /* We queue the segment on the ->ooseq queue. */
+ if (pcb->ooseq == NULL) {
+ pcb->ooseq = tcp_seg_copy(&inseg);
+ } else {
+ /* If the queue is not empty, we walk through the queue and
+ try to find a place where the sequence number of the
+ incoming segment is between the sequence numbers of the
+ previous and the next segment on the ->ooseq queue. That is
+ the place where we put the incoming segment. If needed, we
+ trim the second edges of the previous and the incoming
+ segment so that it will fit into the sequence.
+
+ If the incoming segment has the same sequence number as a
+ segment on the ->ooseq queue, we discard the segment that
+ contains less data. */
+
+ prev = NULL;
+ for(next = pcb->ooseq; next != NULL; next = next->next) {
+ if (seqno == next->tcphdr->seqno) {
+ /* The sequence number of the incoming segment is the
+ same as the sequence number of the segment on
+ ->ooseq. We check the lengths to see which one to
+ discard. */
+ if (inseg.len > next->len) {
+ /* The incoming segment is larger than the old
+ segment. We replace the old segment with the new
+ one. */
+ cseg = tcp_seg_copy(&inseg);
+ if (cseg != NULL) {
+ cseg->next = next->next;
+ if (prev != NULL) {
+ prev->next = cseg;
+ } else {
+ pcb->ooseq = cseg;
+ }
+ }
+ break;
+ } else {
+ /* Either the lenghts are the same or the incoming
+ segment was smaller than the old one; in either
+ case, we ditch the incoming segment. */
+ break;
+ }
+ } else {
+ if (prev == NULL) {
+ if (TCP_SEQ_LT(seqno, next->tcphdr->seqno)) {
+ /* The sequence number of the incoming segment is lower
+ than the sequence number of the first segment on the
+ queue. We put the incoming segment first on the
+ queue. */
+
+ if (TCP_SEQ_GT(seqno + inseg.len, next->tcphdr->seqno)) {
+ /* We need to trim the incoming segment. */
+ inseg.len = next->tcphdr->seqno - seqno;
+ pbuf_realloc(inseg.p, inseg.len);
+ }
+ cseg = tcp_seg_copy(&inseg);
+ if (cseg != NULL) {
+ cseg->next = next;
+ pcb->ooseq = cseg;
+ }
+ break;
+ }
+ } else
+ /*if (TCP_SEQ_LT(prev->tcphdr->seqno, seqno) &&
+ TCP_SEQ_LT(seqno, next->tcphdr->seqno)) {*/
+ if(TCP_SEQ_BETWEEN(seqno, prev->tcphdr->seqno+1, next->tcphdr->seqno-1)){
+ /* The sequence number of the incoming segment is in
+ between the sequence numbers of the previous and
+ the next segment on ->ooseq. We trim and insert the
+ incoming segment and trim the previous segment, if
+ needed. */
+ if (TCP_SEQ_GT(seqno + inseg.len, next->tcphdr->seqno)) {
+ /* We need to trim the incoming segment. */
+ inseg.len = next->tcphdr->seqno - seqno;
+ pbuf_realloc(inseg.p, inseg.len);
+ }
+
+ cseg = tcp_seg_copy(&inseg);
+ if (cseg != NULL) {
+ cseg->next = next;
+ prev->next = cseg;
+ if (TCP_SEQ_GT(prev->tcphdr->seqno + prev->len, seqno)) {
+ /* We need to trim the prev segment. */
+ prev->len = seqno - prev->tcphdr->seqno;
+ pbuf_realloc(prev->p, prev->len);
+ }
+ }
+ break;
+ }
+ /* If the "next" segment is the last segment on the
+ ooseq queue, we add the incoming segment to the end
+ of the list. */
+ if (next->next == NULL &&
+ TCP_SEQ_GT(seqno, next->tcphdr->seqno)) {
+ next->next = tcp_seg_copy(&inseg);
+ if (next->next != NULL) {
+ if (TCP_SEQ_GT(next->tcphdr->seqno + next->len, seqno)) {
+ /* We need to trim the last segment. */
+ next->len = seqno - next->tcphdr->seqno;
+ pbuf_realloc(next->p, next->len);
+ }
+ }
+ break;
+ }
+ }
+ prev = next;
+ }
+ }
+#endif /* TCP_QUEUE_OOSEQ */
+
+ }
+ } else {
+ /*if (TCP_SEQ_GT(pcb->rcv_nxt, seqno) ||
+ TCP_SEQ_GEQ(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) {*/
+ if(!TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd-1)){
+ tcp_ack_now(pcb);
+ }
+ }
+ } else {
+ /* Segments with length 0 is taken care of here. Segments that
+ fall out of the window are ACKed. */
+ /*if (TCP_SEQ_GT(pcb->rcv_nxt, seqno) ||
+ TCP_SEQ_GEQ(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) {*/
+ if(!TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd-1)){
+ tcp_ack_now(pcb);
+ }
+ }
+}
+
+/*
+ * tcp_parseopt:
+ *
+ * Parses the options contained in the incoming segment. (Code taken
+ * from uIP with only small changes.)
+ *
+ */
+
+static void
+tcp_parseopt(struct tcp_pcb *pcb)
+{
+ u8_t c;
+ u8_t *opts, opt;
+ u16_t mss;
+
+ opts = (u8_t *)tcphdr + TCP_HLEN;
+
+ /* Parse the TCP MSS option, if present. */
+ if(TCPH_HDRLEN(tcphdr) > 0x5) {
+ for(c = 0; c < (TCPH_HDRLEN(tcphdr) - 5) << 2 ;) {
+ opt = opts[c];
+ if (opt == 0x00) {
+ /* End of options. */
+ break;
+ } else if (opt == 0x01) {
+ ++c;
+ /* NOP option. */
+ } else if (opt == 0x02 &&
+ opts[c + 1] == 0x04) {
+ /* An MSS option with the right option length. */
+ mss = (opts[c + 2] << 8) | opts[c + 3];
+ pcb->mss = mss > TCP_MSS? TCP_MSS: mss;
+
+ /* And we are done processing options. */
+ break;
+ } else {
+ if (opts[c + 1] == 0) {
+ /* If the length field is zero, the options are malformed
+ and we don't process them further. */
+ break;
+ }
+ /* All other options have a length field, so that we easily
+ can skip past them. */
+ c += opts[c + 1];
+ }
+ }
+ }
+}
+#endif /* LWIP_TCP */
+
+
--- /dev/null
+/**\r
+ * @file\r
+ *\r
+ * Transmission Control Protocol, outgoing traffic\r
+ *\r
+ * The output functions of TCP.\r
+ *\r
+ */\r
+\r
+/*\r
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. The name of the author may not be used to endorse or promote products\r
+ * derived from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT\r
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT\r
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING\r
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY\r
+ * OF SUCH DAMAGE.\r
+ *\r
+ * This file is part of the lwIP TCP/IP stack.\r
+ *\r
+ * Author: Adam Dunkels <adam@sics.se>\r
+ *\r
+ */\r
+\r
+#include "lwip/def.h"\r
+#include "lwip/opt.h"\r
+\r
+#include "lwip/mem.h"\r
+#include "lwip/memp.h"\r
+#include "lwip/sys.h"\r
+\r
+#include "lwip/ip_addr.h"\r
+#include "lwip/netif.h"\r
+\r
+#include "lwip/inet.h"\r
+#include "lwip/tcp.h"\r
+\r
+#include "lwip/stats.h"\r
+\r
+#include <string.h>\r
+\r
+#if LWIP_TCP\r
+\r
+/* Forward declarations.*/\r
+static void tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb);\r
+\r
+err_t\r
+tcp_send_ctrl(struct tcp_pcb *pcb, u8_t flags)\r
+{\r
+ /* no data, no length, flags, copy=1, no optdata, no optdatalen */\r
+ return tcp_enqueue(pcb, NULL, 0, flags, 1, NULL, 0);\r
+}\r
+\r
+/**\r
+ * Write data for sending (but does not send it immediately).\r
+ *\r
+ * It waits in the expectation of more data being sent soon (as\r
+ * it can send them more efficiently by combining them together).\r
+ * To prompt the system to send data now, call tcp_output() after\r
+ * calling tcp_write().\r
+ * \r
+ * @arg pcb Protocol control block of the TCP connection to enqueue data for. \r
+ * \r
+ * @see tcp_write()\r
+ */\r
+\r
+err_t\r
+tcp_write(struct tcp_pcb *pcb, const void *arg, u16_t len, u8_t copy)\r
+{\r
+ LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_write(pcb=%p, arg=%p, len=%u, copy=%d)\n", (void *)pcb,\r
+ arg, len, (unsigned int)copy));\r
+ /* connection is in valid state for data transmission? */\r
+ if (pcb->state == ESTABLISHED ||\r
+ pcb->state == CLOSE_WAIT ||\r
+ pcb->state == SYN_SENT ||\r
+ pcb->state == SYN_RCVD) {\r
+ if (len > 0) {\r
+ return tcp_enqueue(pcb, (void *)arg, len, 0, copy, NULL, 0);\r
+ }\r
+ return ERR_OK;\r
+ } else {\r
+ LWIP_DEBUGF(TCP_OUTPUT_DEBUG | DBG_STATE | 3, ("tcp_write() called in invalid state\n"));\r
+ return ERR_CONN;\r
+ }\r
+}\r
+\r
+/**\r
+ * Enqueue either data or TCP options (but not both) for tranmission\r
+ * \r
+ * \r
+ * \r
+ * @arg pcb Protocol control block for the TCP connection to enqueue data for.\r
+ * @arg arg Pointer to the data to be enqueued for sending.\r
+ * @arg len Data length in bytes\r
+ * @arg flags\r
+ * @arg copy 1 if data must be copied, 0 if data is non-volatile and can be\r
+ * referenced.\r
+ * @arg optdata\r
+ * @arg optlen\r
+ */\r
+err_t\r
+tcp_enqueue(struct tcp_pcb *pcb, void *arg, u16_t len,\r
+ u8_t flags, u8_t copy,\r
+ u8_t *optdata, u8_t optlen)\r
+{\r
+ struct pbuf *p;\r
+ struct tcp_seg *seg, *useg, *queue=NULL;\r
+ u32_t left, seqno;\r
+ u16_t seglen;\r
+ void *ptr;\r
+ u8_t queuelen;\r
+\r
+ LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_enqueue(pcb=%p, arg=%p, len=%u, flags=%x, copy=%u)\n",\r
+ (void *)pcb, arg, len, (unsigned int)flags, (unsigned int)copy));\r
+ LWIP_ASSERT("tcp_enqueue: len == 0 || optlen == 0 (programmer violates API)",\r
+ len == 0 || optlen == 0);\r
+ LWIP_ASSERT("tcp_enqueue: arg == NULL || optdata == NULL (programmer violates API)",\r
+ arg == NULL || optdata == NULL);\r
+ /* fail on too much data */\r
+ if (len > pcb->snd_buf) {\r
+ LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 3, ("tcp_enqueue: too much data (len=%u > snd_buf=%u)\n", len, pcb->snd_buf));\r
+ return ERR_MEM;\r
+ }\r
+ left = len;\r
+ ptr = arg;\r
+\r
+ /* seqno will be the sequence number of the first segment enqueued\r
+ * by the call to this function. */\r
+ seqno = pcb->snd_lbb;\r
+\r
+ LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue: queuelen: %u\n", (unsigned int)pcb->snd_queuelen));\r
+\r
+ /* If total number of pbufs on the unsent/unacked queues exceeds the\r
+ * configured maximum, return an error */\r
+ queuelen = pcb->snd_queuelen;\r
+ if (queuelen >= TCP_SND_QUEUELEN) {\r
+ LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 3, ("tcp_enqueue: too long queue %u (max %u)\n", queuelen, TCP_SND_QUEUELEN));\r
+ goto memerr;\r
+ }\r
+ if (queuelen != 0) {\r
+ LWIP_ASSERT("tcp_enqueue: pbufs on queue => at least one queue non-empty",\r
+ pcb->unacked != NULL || pcb->unsent != NULL);\r
+ } else {\r
+ LWIP_ASSERT("tcp_enqueue: no pbufs on queue => both queues empty",\r
+ pcb->unacked == NULL && pcb->unsent == NULL);\r
+ }\r
+\r
+ /* First, break up the data into segments and tuck them together in\r
+ * the local "queue" variable. */\r
+ useg = NULL;\r
+ queue = NULL;\r
+ seg = NULL;\r
+ seglen = 0;\r
+ while (queue == NULL || left > 0) {\r
+\r
+ /* The segment length should be the MSS if the data to be enqueued\r
+ * is larger than the MSS. */\r
+ seglen = left > pcb->mss? pcb->mss: left;\r
+\r
+ /* Allocate memory for tcp_seg, and fill in fields. */\r
+ seg = memp_malloc(MEMP_TCP_SEG);\r
+ if (seg == NULL) {\r
+ LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: could not allocate memory for tcp_seg\n"));\r
+ goto memerr;\r
+ }\r
+ seg->next = NULL;\r
+ seg->p = NULL;\r
+\r
+ /* first segment of to-be-queued data? */\r
+ if (queue == NULL) {\r
+ queue = seg;\r
+ }\r
+ /* subsequent segments of to-be-queued data */\r
+ else {\r
+ /* Attach the segment to the end of the queued segments */\r
+ LWIP_ASSERT("useg != NULL", useg != NULL);\r
+ useg->next = seg;\r
+ }\r
+ /* remember last segment of to-be-queued data for next iteration */\r
+ useg = seg;\r
+\r
+ /* If copy is set, memory should be allocated\r
+ * and data copied into pbuf, otherwise data comes from\r
+ * ROM or other static memory, and need not be copied. If\r
+ * optdata is != NULL, we have options instead of data. */\r
+ \r
+ /* options? */\r
+ if (optdata != NULL) {\r
+ if ((seg->p = pbuf_alloc(PBUF_TRANSPORT, optlen, PBUF_RAM)) == NULL) {\r
+ goto memerr;\r
+ }\r
+ ++queuelen;\r
+ seg->dataptr = seg->p->payload;\r
+ }\r
+ /* copy from volatile memory? */\r
+ else if (copy) {\r
+ if ((seg->p = pbuf_alloc(PBUF_TRANSPORT, seglen, PBUF_RAM)) == NULL) {\r
+ LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue : could not allocate memory for pbuf copy size %u\n", seglen));\r
+ goto memerr;\r
+ }\r
+ ++queuelen;\r
+ if (arg != NULL) {\r
+ memcpy(seg->p->payload, ptr, seglen);\r
+ }\r
+ seg->dataptr = seg->p->payload;\r
+ }\r
+ /* do not copy data */\r
+ else {\r
+ /* First, allocate a pbuf for holding the data.\r
+ * since the referenced data is available at least until it is sent out on the\r
+ * link (as it has to be ACKed by the remote party) we can safely use PBUF_ROM\r
+ * instead of PBUF_REF here.\r
+ */\r
+ if ((p = pbuf_alloc(PBUF_TRANSPORT, seglen, PBUF_ROM)) == NULL) {\r
+ LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: could not allocate memory for zero-copy pbuf\n"));\r
+ goto memerr;\r
+ }\r
+ ++queuelen;\r
+ /* reference the non-volatile payload data */\r
+ p->payload = ptr;\r
+ seg->dataptr = ptr;\r
+\r
+ /* Second, allocate a pbuf for the headers. */\r
+ if ((seg->p = pbuf_alloc(PBUF_TRANSPORT, 0, PBUF_RAM)) == NULL) {\r
+ /* If allocation fails, we have to deallocate the data pbuf as\r
+ * well. */\r
+ pbuf_free(p);\r
+ LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: could not allocate memory for header pbuf\n"));\r
+ goto memerr;\r
+ }\r
+ ++queuelen;\r
+\r
+ /* Concatenate the headers and data pbufs together. */\r
+ pbuf_cat(seg->p/*header*/, p/*data*/);\r
+ p = NULL;\r
+ }\r
+\r
+ /* Now that there are more segments queued, we check again if the\r
+ length of the queue exceeds the configured maximum. */\r
+ if (queuelen > TCP_SND_QUEUELEN) {\r
+ LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: queue too long %u (%u)\n", queuelen, TCP_SND_QUEUELEN));\r
+ goto memerr;\r
+ }\r
+\r
+ seg->len = seglen;\r
+\r
+ /* build TCP header */\r
+ if (pbuf_header(seg->p, TCP_HLEN)) {\r
+ LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: no room for TCP header in pbuf.\n"));\r
+ TCP_STATS_INC(tcp.err);\r
+ goto memerr;\r
+ }\r
+ seg->tcphdr = seg->p->payload;\r
+ seg->tcphdr->src = htons(pcb->local_port);\r
+ seg->tcphdr->dest = htons(pcb->remote_port);\r
+ seg->tcphdr->seqno = htonl(seqno);\r
+ seg->tcphdr->urgp = 0;\r
+ TCPH_FLAGS_SET(seg->tcphdr, flags);\r
+ /* don't fill in tcphdr->ackno and tcphdr->wnd until later */\r
+\r
+ /* Copy the options into the header, if they are present. */\r
+ if (optdata == NULL) {\r
+ TCPH_HDRLEN_SET(seg->tcphdr, 5);\r
+ }\r
+ else {\r
+ TCPH_HDRLEN_SET(seg->tcphdr, (5 + optlen / 4));\r
+ /* Copy options into data portion of segment.\r
+ Options can thus only be sent in non data carrying\r
+ segments such as SYN|ACK. */\r
+ memcpy(seg->dataptr, optdata, optlen);\r
+ }\r
+ LWIP_DEBUGF(TCP_OUTPUT_DEBUG | DBG_TRACE, ("tcp_enqueue: queueing %lu:%lu (0x%x)\n",\r
+ ntohl(seg->tcphdr->seqno),\r
+ ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg),\r
+ flags));\r
+\r
+ left -= seglen;\r
+ seqno += seglen;\r
+ ptr = (void *)((char *)ptr + seglen);\r
+ }\r
+\r
+ /* Now that the data to be enqueued has been broken up into TCP\r
+ segments in the queue variable, we add them to the end of the\r
+ pcb->unsent queue. */\r
+ if (pcb->unsent == NULL) {\r
+ useg = NULL;\r
+ }\r
+ else {\r
+ for (useg = pcb->unsent; useg->next != NULL; useg = useg->next);\r
+ }\r
+ /* { useg is last segment on the unsent queue, NULL if list is empty } */\r
+\r
+ /* If there is room in the last pbuf on the unsent queue,\r
+ chain the first pbuf on the queue together with that. */\r
+ if (useg != NULL &&\r
+ TCP_TCPLEN(useg) != 0 &&\r
+ !(TCPH_FLAGS(useg->tcphdr) & (TCP_SYN | TCP_FIN)) &&\r
+ !(flags & (TCP_SYN | TCP_FIN)) &&\r
+ /* fit within max seg size */\r
+ useg->len + queue->len <= pcb->mss) {\r
+ /* Remove TCP header from first segment of our to-be-queued list */\r
+ pbuf_header(queue->p, -TCP_HLEN);\r
+ pbuf_cat(useg->p, queue->p);\r
+ useg->len += queue->len;\r
+ useg->next = queue->next;\r
+\r
+ LWIP_DEBUGF(TCP_OUTPUT_DEBUG | DBG_TRACE | DBG_STATE, ("tcp_enqueue: chaining segments, new len %u\n", useg->len));\r
+ if (seg == queue) {\r
+ seg = NULL;\r
+ }\r
+ memp_free(MEMP_TCP_SEG, queue);\r
+ }\r
+ else {\r
+ /* empty list */\r
+ if (useg == NULL) {\r
+ /* initialize list with this segment */\r
+ pcb->unsent = queue;\r
+ }\r
+ /* enqueue segment */\r
+ else {\r
+ useg->next = queue;\r
+ }\r
+ }\r
+ if ((flags & TCP_SYN) || (flags & TCP_FIN)) {\r
+ ++len;\r
+ }\r
+ pcb->snd_lbb += len;\r
+ pcb->snd_buf -= len;\r
+ /* update number of segments on the queues */\r
+ pcb->snd_queuelen = queuelen;\r
+ LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue: %d (after enqueued)\n", pcb->snd_queuelen));\r
+ if (pcb->snd_queuelen != 0) {\r
+ LWIP_ASSERT("tcp_enqueue: valid queue length",\r
+ pcb->unacked != NULL || pcb->unsent != NULL);\r
+ }\r
+\r
+ /* Set the PSH flag in the last segment that we enqueued, but only\r
+ if the segment has data (indicated by seglen > 0). */\r
+ if (seg != NULL && seglen > 0 && seg->tcphdr != NULL) {\r
+ TCPH_SET_FLAG(seg->tcphdr, TCP_PSH);\r
+ }\r
+\r
+ return ERR_OK;\r
+ memerr:\r
+ TCP_STATS_INC(tcp.memerr);\r
+\r
+ if (queue != NULL) {\r
+ tcp_segs_free(queue);\r
+ }\r
+ if (pcb->snd_queuelen != 0) {\r
+ LWIP_ASSERT("tcp_enqueue: valid queue length", pcb->unacked != NULL ||\r
+ pcb->unsent != NULL);\r
+ }\r
+ LWIP_DEBUGF(TCP_QLEN_DEBUG | DBG_STATE, ("tcp_enqueue: %d (with mem err)\n", pcb->snd_queuelen));\r
+ return ERR_MEM;\r
+}\r
+\r
+/* find out what we can send and send it */\r
+err_t\r
+tcp_output(struct tcp_pcb *pcb)\r
+{\r
+ struct pbuf *p;\r
+ struct tcp_hdr *tcphdr;\r
+ struct tcp_seg *seg, *useg;\r
+ u32_t wnd;\r
+#if TCP_CWND_DEBUG\r
+ int i = 0;\r
+#endif /* TCP_CWND_DEBUG */\r
+\r
+ /* First, check if we are invoked by the TCP input processing\r
+ code. If so, we do not output anything. Instead, we rely on the\r
+ input processing code to call us when input processing is done\r
+ with. */\r
+ if (tcp_input_pcb == pcb) {\r
+ return ERR_OK;\r
+ }\r
+\r
+ wnd = LWIP_MIN(pcb->snd_wnd, pcb->cwnd);\r
+\r
+ seg = pcb->unsent;\r
+\r
+ /* useg should point to last segment on unacked queue */\r
+ useg = pcb->unacked;\r
+ if (useg != NULL) {\r
+ for (; useg->next != NULL; useg = useg->next);\r
+ } \r
+ \r
+ /* If the TF_ACK_NOW flag is set and no data will be sent (either\r
+ * because the ->unsent queue is empty or because the window does\r
+ * not allow it), construct an empty ACK segment and send it.\r
+ *\r
+ * If data is to be sent, we will just piggyback the ACK (see below).\r
+ */\r
+ if (pcb->flags & TF_ACK_NOW &&\r
+ (seg == NULL ||\r
+ ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len > wnd)) {\r
+ p = pbuf_alloc(PBUF_IP, TCP_HLEN, PBUF_RAM);\r
+ if (p == NULL) {\r
+ LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: (ACK) could not allocate pbuf\n"));\r
+ return ERR_BUF;\r
+ }\r
+ LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: sending ACK for %lu\n", pcb->rcv_nxt));\r
+ /* remove ACK flags from the PCB, as we send an empty ACK now */\r
+ pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW);\r
+\r
+ tcphdr = p->payload;\r
+ tcphdr->src = htons(pcb->local_port);\r
+ tcphdr->dest = htons(pcb->remote_port);\r
+ tcphdr->seqno = htonl(pcb->snd_nxt);\r
+ tcphdr->ackno = htonl(pcb->rcv_nxt);\r
+ TCPH_FLAGS_SET(tcphdr, TCP_ACK);\r
+ tcphdr->wnd = htons(pcb->rcv_wnd);\r
+ tcphdr->urgp = 0;\r
+ TCPH_HDRLEN_SET(tcphdr, 5);\r
+\r
+ tcphdr->chksum = 0;\r
+#if CHECKSUM_GEN_TCP\r
+ tcphdr->chksum = inet_chksum_pseudo(p, &(pcb->local_ip), &(pcb->remote_ip),\r
+ IP_PROTO_TCP, p->tot_len);\r
+#endif\r
+ ip_output(p, &(pcb->local_ip), &(pcb->remote_ip), pcb->ttl, pcb->tos,\r
+ IP_PROTO_TCP);\r
+ pbuf_free(p);\r
+\r
+ return ERR_OK;\r
+ }\r
+\r
+#if TCP_OUTPUT_DEBUG\r
+ if (seg == NULL) {\r
+ LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: nothing to send (%p)\n", pcb->unsent));\r
+ }\r
+#endif /* TCP_OUTPUT_DEBUG */\r
+#if TCP_CWND_DEBUG\r
+ if (seg == NULL) {\r
+ LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %lu, cwnd %lu, wnd %lu, seg == NULL, ack %lu\n",\r
+ pcb->snd_wnd, pcb->cwnd, wnd,\r
+ pcb->lastack));\r
+ } else {\r
+ LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %lu, cwnd %lu, wnd %lu, effwnd %lu, seq %lu, ack %lu\n",\r
+ pcb->snd_wnd, pcb->cwnd, wnd,\r
+ ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len,\r
+ ntohl(seg->tcphdr->seqno), pcb->lastack));\r
+ }\r
+#endif /* TCP_CWND_DEBUG */\r
+ /* data available and window allows it to be sent? */\r
+ while (seg != NULL &&\r
+ ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len <= wnd) {\r
+#if TCP_CWND_DEBUG\r
+ LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %lu, cwnd %lu, wnd %lu, effwnd %lu, seq %lu, ack %lu, i%d\n",\r
+ pcb->snd_wnd, pcb->cwnd, wnd,\r
+ ntohl(seg->tcphdr->seqno) + seg->len -\r
+ pcb->lastack,\r
+ ntohl(seg->tcphdr->seqno), pcb->lastack, i));\r
+ ++i;\r
+#endif /* TCP_CWND_DEBUG */\r
+\r
+ pcb->unsent = seg->next;\r
+\r
+ if (pcb->state != SYN_SENT) {\r
+ TCPH_SET_FLAG(seg->tcphdr, TCP_ACK);\r
+ pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW);\r
+ }\r
+\r
+ tcp_output_segment(seg, pcb);\r
+ pcb->snd_nxt = ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg);\r
+ if (TCP_SEQ_LT(pcb->snd_max, pcb->snd_nxt)) {\r
+ pcb->snd_max = pcb->snd_nxt;\r
+ }\r
+ /* put segment on unacknowledged list if length > 0 */\r
+ if (TCP_TCPLEN(seg) > 0) {\r
+ seg->next = NULL;\r
+ /* unacked list is empty? */\r
+ if (pcb->unacked == NULL) {\r
+ pcb->unacked = seg;\r
+ useg = seg;\r
+ /* unacked list is not empty? */\r
+ } else {\r
+ /* In the case of fast retransmit, the packet should not go to the tail\r
+ * of the unacked queue, but rather at the head. We need to check for\r
+ * this case. -STJ Jul 27, 2004 */\r
+ if (TCP_SEQ_LT(ntohl(seg->tcphdr->seqno), ntohl(useg->tcphdr->seqno))){\r
+ /* add segment to head of unacked list */\r
+ seg->next = pcb->unacked;\r
+ pcb->unacked = seg;\r
+ } else {\r
+ /* add segment to tail of unacked list */\r
+ useg->next = seg;\r
+ useg = useg->next;\r
+ }\r
+ }\r
+ /* do not queue empty segments on the unacked list */\r
+ } else {\r
+ tcp_seg_free(seg);\r
+ }\r
+ seg = pcb->unsent;\r
+ }\r
+ return ERR_OK;\r
+}\r
+\r
+/**\r
+ * Actually send a TCP segment over IP\r
+ */\r
+static void\r
+tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb)\r
+{\r
+ u16_t len;\r
+ struct netif *netif;\r
+\r
+ /* The TCP header has already been constructed, but the ackno and\r
+ wnd fields remain. */\r
+ seg->tcphdr->ackno = htonl(pcb->rcv_nxt);\r
+\r
+ /* silly window avoidance */\r
+ if (pcb->rcv_wnd < pcb->mss) {\r
+ seg->tcphdr->wnd = 0;\r
+ } else {\r
+ /* advertise our receive window size in this TCP segment */\r
+ seg->tcphdr->wnd = htons(pcb->rcv_wnd);\r
+ }\r
+\r
+ /* If we don't have a local IP address, we get one by\r
+ calling ip_route(). */\r
+ if (ip_addr_isany(&(pcb->local_ip))) {\r
+ netif = ip_route(&(pcb->remote_ip));\r
+ if (netif == NULL) {\r
+ return;\r
+ }\r
+ ip_addr_set(&(pcb->local_ip), &(netif->ip_addr));\r
+ }\r
+\r
+ pcb->rtime = 0;\r
+\r
+ if (pcb->rttest == 0) {\r
+ pcb->rttest = tcp_ticks;\r
+ pcb->rtseq = ntohl(seg->tcphdr->seqno);\r
+\r
+ LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_output_segment: rtseq %lu\n", pcb->rtseq));\r
+ }\r
+ LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output_segment: %lu:%lu\n",\r
+ htonl(seg->tcphdr->seqno), htonl(seg->tcphdr->seqno) +\r
+ seg->len));\r
+\r
+ len = (u16_t)((u8_t *)seg->tcphdr - (u8_t *)seg->p->payload);\r
+\r
+ seg->p->len -= len;\r
+ seg->p->tot_len -= len;\r
+\r
+ seg->p->payload = seg->tcphdr;\r
+\r
+ seg->tcphdr->chksum = 0;\r
+#if CHECKSUM_GEN_TCP\r
+ seg->tcphdr->chksum = inet_chksum_pseudo(seg->p,\r
+ &(pcb->local_ip),\r
+ &(pcb->remote_ip),\r
+ IP_PROTO_TCP, seg->p->tot_len);\r
+#endif\r
+ TCP_STATS_INC(tcp.xmit);\r
+\r
+ ip_output(seg->p, &(pcb->local_ip), &(pcb->remote_ip), pcb->ttl, pcb->tos,\r
+ IP_PROTO_TCP);\r
+}\r
+\r
+void\r
+tcp_rst(u32_t seqno, u32_t ackno,\r
+ struct ip_addr *local_ip, struct ip_addr *remote_ip,\r
+ u16_t local_port, u16_t remote_port)\r
+{\r
+ struct pbuf *p;\r
+ struct tcp_hdr *tcphdr;\r
+ p = pbuf_alloc(PBUF_IP, TCP_HLEN, PBUF_RAM);\r
+ if (p == NULL) {\r
+ LWIP_DEBUGF(TCP_DEBUG, ("tcp_rst: could not allocate memory for pbuf\n"));\r
+ return;\r
+ }\r
+\r
+ tcphdr = p->payload;\r
+ tcphdr->src = htons(local_port);\r
+ tcphdr->dest = htons(remote_port);\r
+ tcphdr->seqno = htonl(seqno);\r
+ tcphdr->ackno = htonl(ackno);\r
+ TCPH_FLAGS_SET(tcphdr, TCP_RST | TCP_ACK);\r
+ tcphdr->wnd = htons(TCP_WND);\r
+ tcphdr->urgp = 0;\r
+ TCPH_HDRLEN_SET(tcphdr, 5);\r
+\r
+ tcphdr->chksum = 0;\r
+#if CHECKSUM_GEN_TCP\r
+ tcphdr->chksum = inet_chksum_pseudo(p, local_ip, remote_ip,\r
+ IP_PROTO_TCP, p->tot_len);\r
+#endif\r
+ TCP_STATS_INC(tcp.xmit);\r
+ /* Send output with hardcoded TTL since we have no access to the pcb */\r
+ ip_output(p, local_ip, remote_ip, TCP_TTL, 0, IP_PROTO_TCP);\r
+ pbuf_free(p);\r
+ LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_rst: seqno %lu ackno %lu.\n", seqno, ackno));\r
+}\r
+\r
+/* requeue all unacked segments for retransmission */\r
+void\r
+tcp_rexmit_rto(struct tcp_pcb *pcb)\r
+{\r
+ struct tcp_seg *seg;\r
+\r
+ if (pcb->unacked == NULL) {\r
+ return;\r
+ }\r
+\r
+ /* Move all unacked segments to the head of the unsent queue */\r
+ for (seg = pcb->unacked; seg->next != NULL; seg = seg->next);\r
+ /* concatenate unsent queue after unacked queue */\r
+ seg->next = pcb->unsent;\r
+ /* unsent queue is the concatenated queue (of unacked, unsent) */\r
+ pcb->unsent = pcb->unacked;\r
+ /* unacked queue is now empty */\r
+ pcb->unacked = NULL;\r
+\r
+ pcb->snd_nxt = ntohl(pcb->unsent->tcphdr->seqno);\r
+ /* increment number of retransmissions */\r
+ ++pcb->nrtx;\r
+\r
+ /* Don't take any RTT measurements after retransmitting. */\r
+ pcb->rttest = 0;\r
+\r
+ /* Do the actual retransmission */\r
+ tcp_output(pcb);\r
+}\r
+\r
+void\r
+tcp_rexmit(struct tcp_pcb *pcb)\r
+{\r
+ struct tcp_seg *seg;\r
+\r
+ if (pcb->unacked == NULL) {\r
+ return;\r
+ }\r
+\r
+ /* Move the first unacked segment to the unsent queue */\r
+ seg = pcb->unacked->next;\r
+ pcb->unacked->next = pcb->unsent;\r
+ pcb->unsent = pcb->unacked;\r
+ pcb->unacked = seg;\r
+\r
+ pcb->snd_nxt = ntohl(pcb->unsent->tcphdr->seqno);\r
+\r
+ ++pcb->nrtx;\r
+\r
+ /* Don't take any rtt measurements after retransmitting. */\r
+ pcb->rttest = 0;\r
+\r
+ /* Do the actual retransmission. */\r
+ tcp_output(pcb);\r
+\r
+}\r
+\r
+\r
+void\r
+tcp_keepalive(struct tcp_pcb *pcb)\r
+{\r
+ struct pbuf *p;\r
+ struct tcp_hdr *tcphdr;\r
+\r
+ LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: sending KEEPALIVE probe to %u.%u.%u.%u\n",\r
+ ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip),\r
+ ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip)));\r
+\r
+ LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: tcp_ticks %lu pcb->tmr %lu pcb->keep_cnt %u\n", tcp_ticks, pcb->tmr, pcb->keep_cnt));\r
+ \r
+ p = pbuf_alloc(PBUF_IP, TCP_HLEN, PBUF_RAM);\r
+\r
+ if(p == NULL) {\r
+ LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: could not allocate memory for pbuf\n"));\r
+ return;\r
+ }\r
+\r
+ tcphdr = p->payload;\r
+ tcphdr->src = htons(pcb->local_port);\r
+ tcphdr->dest = htons(pcb->remote_port);\r
+ tcphdr->seqno = htonl(pcb->snd_nxt - 1);\r
+ tcphdr->ackno = htonl(pcb->rcv_nxt);\r
+ tcphdr->wnd = htons(pcb->rcv_wnd);\r
+ tcphdr->urgp = 0;\r
+ TCPH_HDRLEN_SET(tcphdr, 5);\r
+ \r
+ tcphdr->chksum = 0;\r
+#if CHECKSUM_GEN_TCP\r
+ tcphdr->chksum = inet_chksum_pseudo(p, &pcb->local_ip, &pcb->remote_ip, IP_PROTO_TCP, p->tot_len);\r
+#endif\r
+ TCP_STATS_INC(tcp.xmit);\r
+\r
+ /* Send output to IP */\r
+ ip_output(p, &pcb->local_ip, &pcb->remote_ip, pcb->ttl, 0, IP_PROTO_TCP);\r
+\r
+ pbuf_free(p);\r
+\r
+ LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_keepalive: seqno %lu ackno %lu.\n", pcb->snd_nxt - 1, pcb->rcv_nxt));\r
+}\r
+\r
+#endif /* LWIP_TCP */\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/**
+ * @file
+ * User Datagram Protocol module
+ *
+ */
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+
+/* udp.c
+ *
+ * The code for the User Datagram Protocol UDP.
+ *
+ */
+
+#include <string.h>
+
+#include "lwip/opt.h"
+
+#include "lwip/def.h"
+#include "lwip/memp.h"
+#include "lwip/inet.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/udp.h"
+#include "lwip/icmp.h"
+
+#include "lwip/stats.h"
+
+#include "arch/perf.h"
+#include "lwip/snmp.h"
+
+/* The list of UDP PCBs */
+#if LWIP_UDP
+/* was static, but we may want to access this from a socket layer */
+struct udp_pcb *udp_pcbs = NULL;
+
+static struct udp_pcb *pcb_cache = NULL;
+
+
+void
+udp_init(void)
+{
+ udp_pcbs = pcb_cache = NULL;
+}
+
+/**
+ * Process an incoming UDP datagram.
+ *
+ * Given an incoming UDP datagram (as a chain of pbufs) this function
+ * finds a corresponding UDP PCB and
+ *
+ * @param pbuf pbuf to be demultiplexed to a UDP PCB.
+ * @param netif network interface on which the datagram was received.
+ *
+ */
+void
+udp_input(struct pbuf *p, struct netif *inp)
+{
+ struct udp_hdr *udphdr;
+ struct udp_pcb *pcb;
+ struct ip_hdr *iphdr;
+ u16_t src, dest;
+
+#if SO_REUSE
+ struct udp_pcb *pcb_temp;
+ int reuse = 0;
+ int reuse_port_1 = 0;
+ int reuse_port_2 = 0;
+#endif /* SO_REUSE */
+
+ PERF_START;
+
+ UDP_STATS_INC(udp.recv);
+
+ iphdr = p->payload;
+
+ if (pbuf_header(p, -((s16_t)(UDP_HLEN + IPH_HL(iphdr) * 4)))) {
+ /* drop short packets */
+ LWIP_DEBUGF(UDP_DEBUG, ("udp_input: short UDP datagram (%u bytes) discarded\n", p->tot_len));
+ UDP_STATS_INC(udp.lenerr);
+ UDP_STATS_INC(udp.drop);
+ snmp_inc_udpinerrors();
+ pbuf_free(p);
+ goto end;
+ }
+
+ udphdr = (struct udp_hdr *)((u8_t *)p->payload - UDP_HLEN);
+
+ LWIP_DEBUGF(UDP_DEBUG, ("udp_input: received datagram of length %u\n", p->tot_len));
+
+ src = ntohs(udphdr->src);
+ dest = ntohs(udphdr->dest);
+
+ udp_debug_print(udphdr);
+
+ /* print the UDP source and destination */
+ LWIP_DEBUGF(UDP_DEBUG, ("udp (%u.%u.%u.%u, %u) <-- (%u.%u.%u.%u, %u)\n",
+ ip4_addr1(&iphdr->dest), ip4_addr2(&iphdr->dest),
+ ip4_addr3(&iphdr->dest), ip4_addr4(&iphdr->dest), ntohs(udphdr->dest),
+ ip4_addr1(&iphdr->src), ip4_addr2(&iphdr->src),
+ ip4_addr3(&iphdr->src), ip4_addr4(&iphdr->src), ntohs(udphdr->src)));
+
+#if SO_REUSE
+ pcb_temp = udp_pcbs;
+
+ again_1:
+
+ /* Iterate through the UDP pcb list for a fully matching pcb */
+ for (pcb = pcb_temp; pcb != NULL; pcb = pcb->next) {
+#else /* SO_REUSE */
+ /* Iterate through the UDP pcb list for a fully matching pcb */
+ for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) {
+#endif /* SO_REUSE */
+ /* print the PCB local and remote address */
+ LWIP_DEBUGF(UDP_DEBUG, ("pcb (%u.%u.%u.%u, %u) --- (%u.%u.%u.%u, %u)\n",
+ ip4_addr1(&pcb->local_ip), ip4_addr2(&pcb->local_ip),
+ ip4_addr3(&pcb->local_ip), ip4_addr4(&pcb->local_ip), pcb->local_port,
+ ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip),
+ ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip), pcb->remote_port));
+
+ /* PCB remote port matches UDP source port? */
+ if ((pcb->remote_port == src) &&
+ /* PCB local port matches UDP destination port? */
+ (pcb->local_port == dest) &&
+ /* accepting from any remote (source) IP address? or... */
+ (ip_addr_isany(&pcb->remote_ip) ||
+ /* PCB remote IP address matches UDP source IP address? */
+ ip_addr_cmp(&(pcb->remote_ip), &(iphdr->src))) &&
+ /* accepting on any local (netif) IP address? or... */
+ (ip_addr_isany(&pcb->local_ip) ||
+ /* PCB local IP address matches UDP destination IP address? */
+ ip_addr_cmp(&(pcb->local_ip), &(iphdr->dest)))) {
+#if SO_REUSE
+ if (pcb->so_options & SOF_REUSEPORT) {
+ if(reuse) {
+ /* We processed one PCB already */
+ LWIP_DEBUGF(UDP_DEBUG, ("udp_input: second or later PCB and SOF_REUSEPORT set.\n"));
+ } else {
+ /* First PCB with this address */
+ LWIP_DEBUGF(UDP_DEBUG, ("udp_input: first PCB and SOF_REUSEPORT set.\n"));
+ reuse = 1;
+ }
+
+ reuse_port_1 = 1;
+ p->ref++;
+ LWIP_DEBUGF(UDP_DEBUG, ("udp_input: reference counter on PBUF set to %i\n", p->ref));
+ } else {
+ if (reuse) {
+ /* We processed one PCB already */
+ LWIP_DEBUGF(UDP_DEBUG, ("udp_input: second or later PCB but SOF_REUSEPORT not set !\n"));
+ }
+ }
+#endif /* SO_REUSE */
+ break;
+ }
+ }
+ /* no fully matching pcb found? then look for an unconnected pcb */
+ if (pcb == NULL) {
+ /* Iterate through the UDP PCB list for a pcb that matches
+ the local address. */
+
+#if SO_REUSE
+ pcb_temp = udp_pcbs;
+
+ again_2:
+
+ for (pcb = pcb_temp; pcb != NULL; pcb = pcb->next) {
+#else /* SO_REUSE */
+ for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) {
+#endif /* SO_REUSE */
+ LWIP_DEBUGF(UDP_DEBUG, ("pcb (%u.%u.%u.%u, %u) --- (%u.%u.%u.%u, %u)\n",
+ ip4_addr1(&pcb->local_ip), ip4_addr2(&pcb->local_ip),
+ ip4_addr3(&pcb->local_ip), ip4_addr4(&pcb->local_ip), pcb->local_port,
+ ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip),
+ ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip), pcb->remote_port));
+ /* unconnected? */
+ if (((pcb->flags & UDP_FLAGS_CONNECTED) == 0) &&
+ /* destination port matches? */
+ (pcb->local_port == dest) &&
+ /* not bound to a specific (local) interface address? or... */
+ (ip_addr_isany(&pcb->local_ip) ||
+ /* ...matching interface address? */
+ ip_addr_cmp(&(pcb->local_ip), &(iphdr->dest)))) {
+#if SO_REUSE
+ if (pcb->so_options & SOF_REUSEPORT) {
+ if (reuse) {
+ /* We processed one PCB already */
+ LWIP_DEBUGF(UDP_DEBUG, ("udp_input: second or later PCB and SOF_REUSEPORT set.\n"));
+ } else {
+ /* First PCB with this address */
+ LWIP_DEBUGF(UDP_DEBUG, ("udp_input: first PCB and SOF_REUSEPORT set.\n"));
+ reuse = 1;
+ }
+
+ reuse_port_2 = 1;
+ p->ref++;
+ LWIP_DEBUGF(UDP_DEBUG, ("udp_input: reference counter on PBUF set to %i\n", p->ref));
+ } else {
+ if (reuse) {
+ /* We processed one PCB already */
+ LWIP_DEBUGF(UDP_DEBUG, ("udp_input: second or later PCB but SOF_REUSEPORT not set !\n"));
+ }
+ }
+#endif /* SO_REUSE */
+ break;
+ }
+ }
+ }
+
+ /* Check checksum if this is a match or if it was directed at us. */
+ if (pcb != NULL || ip_addr_cmp(&inp->ip_addr, &iphdr->dest))
+ {
+ LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE, ("udp_input: calculating checksum\n"));
+ pbuf_header(p, UDP_HLEN);
+#ifdef IPv6
+ if (iphdr->nexthdr == IP_PROTO_UDPLITE) {
+#else
+ if (IPH_PROTO(iphdr) == IP_PROTO_UDPLITE) {
+#endif /* IPv4 */
+ /* Do the UDP Lite checksum */
+#if CHECKSUM_CHECK_UDP
+ if (inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src),
+ (struct ip_addr *)&(iphdr->dest),
+ IP_PROTO_UDPLITE, ntohs(udphdr->len)) != 0) {
+ LWIP_DEBUGF(UDP_DEBUG | 2, ("udp_input: UDP Lite datagram discarded due to failing checksum\n"));
+ UDP_STATS_INC(udp.chkerr);
+ UDP_STATS_INC(udp.drop);
+ snmp_inc_udpinerrors();
+ pbuf_free(p);
+ goto end;
+ }
+#endif
+ } else {
+#if CHECKSUM_CHECK_UDP
+ if (udphdr->chksum != 0) {
+ if (inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src),
+ (struct ip_addr *)&(iphdr->dest),
+ IP_PROTO_UDP, p->tot_len) != 0) {
+ LWIP_DEBUGF(UDP_DEBUG | 2, ("udp_input: UDP datagram discarded due to failing checksum\n"));
+
+ UDP_STATS_INC(udp.chkerr);
+ UDP_STATS_INC(udp.drop);
+ snmp_inc_udpinerrors();
+ pbuf_free(p);
+ goto end;
+ }
+ }
+#endif
+ }
+ pbuf_header(p, -UDP_HLEN);
+ if (pcb != NULL) {
+ snmp_inc_udpindatagrams();
+ pcb->recv(pcb->recv_arg, pcb, p, &(iphdr->src), src);
+#if SO_REUSE
+ /* First socket should receive now */
+ if(reuse_port_1 || reuse_port_2) {
+ /* We want to search on next socket after receiving */
+ pcb_temp = pcb->next;
+
+ if(reuse_port_1) {
+ /* We are searching connected sockets */
+ reuse_port_1 = 0;
+ reuse_port_2 = 0;
+ goto again_1;
+ } else {
+ /* We are searching unconnected sockets */
+ reuse_port_1 = 0;
+ reuse_port_2 = 0;
+ goto again_2;
+ }
+ }
+#endif /* SO_REUSE */
+ } else {
+#if SO_REUSE
+ if(reuse) {
+ LWIP_DEBUGF(UDP_DEBUG, ("udp_input: freeing PBUF with reference counter set to %i\n", p->ref));
+ pbuf_free(p);
+ goto end;
+ }
+#endif /* SO_REUSE */
+ LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE, ("udp_input: not for us.\n"));
+
+ /* No match was found, send ICMP destination port unreachable unless
+ destination address was broadcast/multicast. */
+
+ if (!ip_addr_isbroadcast(&iphdr->dest, inp) &&
+ !ip_addr_ismulticast(&iphdr->dest)) {
+
+ /* adjust pbuf pointer */
+ p->payload = iphdr;
+ icmp_dest_unreach(p, ICMP_DUR_PORT);
+ }
+ UDP_STATS_INC(udp.proterr);
+ UDP_STATS_INC(udp.drop);
+ snmp_inc_udpnoports();
+ pbuf_free(p);
+ }
+ } else {
+ pbuf_free(p);
+ }
+ end:
+
+ PERF_STOP("udp_input");
+}
+
+/**
+ * Send data to a specified address using UDP.
+ *
+ * @param pcb UDP PCB used to send the data.
+ * @param pbuf chain of pbuf's to be sent.
+ * @param dst_ip Destination IP address.
+ * @param dst_port Destination UDP port.
+ *
+ * If the PCB already has a remote address association, it will
+ * be restored after the data is sent.
+ *
+ * @return lwIP error code.
+ * - ERR_OK. Successful. No error occured.
+ * - ERR_MEM. Out of memory.
+ * - ERR_RTE. Could not find route to destination address.
+ *
+ * @see udp_disconnect() udp_send()
+ */
+err_t
+udp_sendto(struct udp_pcb *pcb, struct pbuf *p,
+ struct ip_addr *dst_ip, u16_t dst_port)
+{
+ err_t err;
+ /* temporary space for current PCB remote address */
+ struct ip_addr pcb_remote_ip;
+ u16_t pcb_remote_port;
+ /* remember current remote peer address of PCB */
+ pcb_remote_ip.addr = pcb->remote_ip.addr;
+ pcb_remote_port = pcb->remote_port;
+ /* copy packet destination address to PCB remote peer address */
+ pcb->remote_ip.addr = dst_ip->addr;
+ pcb->remote_port = dst_port;
+ /* send to the packet destination address */
+ err = udp_send(pcb, p);
+ /* restore PCB remote peer address */
+ pcb->remote_ip.addr = pcb_remote_ip.addr;
+ pcb->remote_port = pcb_remote_port;
+ return err;
+}
+
+/**
+ * Send data using UDP.
+ *
+ * @param pcb UDP PCB used to send the data.
+ * @param pbuf chain of pbuf's to be sent.
+ *
+ * @return lwIP error code.
+ * - ERR_OK. Successful. No error occured.
+ * - ERR_MEM. Out of memory.
+ * - ERR_RTE. Could not find route to destination address.
+ *
+ * @see udp_disconnect() udp_sendto()
+ */
+err_t
+udp_send(struct udp_pcb *pcb, struct pbuf *p)
+{
+ struct udp_hdr *udphdr;
+ struct netif *netif;
+ struct ip_addr *src_ip;
+ err_t err;
+ struct pbuf *q; /* q will be sent down the stack */
+
+ LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 3, ("udp_send\n"));
+
+ /* if the PCB is not yet bound to a port, bind it here */
+ if (pcb->local_port == 0) {
+ LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 2, ("udp_send: not yet bound to a port, binding now\n"));
+ err = udp_bind(pcb, &pcb->local_ip, pcb->local_port);
+ if (err != ERR_OK) {
+ LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 2, ("udp_send: forced port bind failed\n"));
+ return err;
+ }
+ }
+
+ /* not enough space to add an UDP header to first pbuf in given p chain? */
+ if (pbuf_header(p, UDP_HLEN)) {
+ /* allocate header in a seperate new pbuf */
+ q = pbuf_alloc(PBUF_IP, UDP_HLEN, PBUF_RAM);
+ /* new header pbuf could not be allocated? */
+ if (q == NULL) {
+ LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 2, ("udp_send: could not allocate header\n"));
+ return ERR_MEM;
+ }
+ /* chain header q in front of given pbuf p */
+ pbuf_chain(q, p);
+ /* { first pbuf q points to header pbuf } */
+ LWIP_DEBUGF(UDP_DEBUG, ("udp_send: added header pbuf %p before given pbuf %p\n", (void *)q, (void *)p));
+ /* adding a header within p succeeded */
+ } else {
+ /* first pbuf q equals given pbuf */
+ q = p;
+ LWIP_DEBUGF(UDP_DEBUG, ("udp_send: added header in given pbuf %p\n", (void *)p));
+ }
+ /* { q now represents the packet to be sent } */
+ udphdr = q->payload;
+ udphdr->src = htons(pcb->local_port);
+ udphdr->dest = htons(pcb->remote_port);
+ /* in UDP, 0 checksum means 'no checksum' */
+ udphdr->chksum = 0x0000;
+
+ /* find the outgoing network interface for this packet */
+ netif = ip_route(&(pcb->remote_ip));
+ /* no outgoing network interface could be found? */
+ if (netif == NULL) {
+ LWIP_DEBUGF(UDP_DEBUG | 1, ("udp_send: No route to 0x%lx\n", pcb->remote_ip.addr));
+ UDP_STATS_INC(udp.rterr);
+ return ERR_RTE;
+ }
+ /* PCB local address is IP_ANY_ADDR? */
+ if (ip_addr_isany(&pcb->local_ip)) {
+ /* use outgoing network interface IP address as source address */
+ src_ip = &(netif->ip_addr);
+ } else {
+ /* use UDP PCB local IP address as source address */
+ src_ip = &(pcb->local_ip);
+ }
+
+ LWIP_DEBUGF(UDP_DEBUG, ("udp_send: sending datagram of length %u\n", q->tot_len));
+
+ /* UDP Lite protocol? */
+ if (pcb->flags & UDP_FLAGS_UDPLITE) {
+ LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP LITE packet length %u\n", q->tot_len));
+ /* set UDP message length in UDP header */
+ udphdr->len = htons(pcb->chksum_len);
+ /* calculate checksum */
+#if CHECKSUM_GEN_UDP
+ udphdr->chksum = inet_chksum_pseudo(q, src_ip, &(pcb->remote_ip),
+ IP_PROTO_UDP, pcb->chksum_len);
+ /* chksum zero must become 0xffff, as zero means 'no checksum' */
+ if (udphdr->chksum == 0x0000) udphdr->chksum = 0xffff;
+#else
+ udphdr->chksum = 0x0000;
+#endif
+ /* output to IP */
+ LWIP_DEBUGF(UDP_DEBUG, ("udp_send: ip_output_if (,,,,IP_PROTO_UDPLITE,)\n"));
+ err = ip_output_if (q, src_ip, &pcb->remote_ip, pcb->ttl, pcb->tos, IP_PROTO_UDPLITE, netif);
+ /* UDP */
+ } else {
+ LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP packet length %u\n", q->tot_len));
+ udphdr->len = htons(q->tot_len);
+ /* calculate checksum */
+#if CHECKSUM_GEN_UDP
+ if ((pcb->flags & UDP_FLAGS_NOCHKSUM) == 0) {
+ udphdr->chksum = inet_chksum_pseudo(q, src_ip, &pcb->remote_ip, IP_PROTO_UDP, q->tot_len);
+ /* chksum zero must become 0xffff, as zero means 'no checksum' */
+ if (udphdr->chksum == 0x0000) udphdr->chksum = 0xffff;
+ }
+#else
+ udphdr->chksum = 0x0000;
+#endif
+ LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP checksum 0x%04x\n", udphdr->chksum));
+ LWIP_DEBUGF(UDP_DEBUG, ("udp_send: ip_output_if (,,,,IP_PROTO_UDP,)\n"));
+ /* output to IP */
+ err = ip_output_if(q, src_ip, &pcb->remote_ip, pcb->ttl, pcb->tos, IP_PROTO_UDP, netif);
+ }
+ /* TODO: must this be increased even if error occured? */
+ snmp_inc_udpoutdatagrams();
+
+ /* did we chain a seperate header pbuf earlier? */
+ if (q != p) {
+ /* free the header pbuf */
+ pbuf_free(q); q = NULL;
+ /* { p is still referenced by the caller, and will live on } */
+ }
+
+ UDP_STATS_INC(udp.xmit);
+ return err;
+}
+
+/**
+ * Bind an UDP PCB.
+ *
+ * @param pcb UDP PCB to be bound with a local address ipaddr and port.
+ * @param ipaddr local IP address to bind with. Use IP_ADDR_ANY to
+ * bind to all local interfaces.
+ * @param port local UDP port to bind with.
+ *
+ * @return lwIP error code.
+ * - ERR_OK. Successful. No error occured.
+ * - ERR_USE. The specified ipaddr and port are already bound to by
+ * another UDP PCB.
+ *
+ * @see udp_disconnect()
+ */
+err_t
+udp_bind(struct udp_pcb *pcb, struct ip_addr *ipaddr, u16_t port)
+{
+ struct udp_pcb *ipcb;
+ u8_t rebind;
+#if SO_REUSE
+ int reuse_port_all_set = 1;
+#endif /* SO_REUSE */
+ LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 3, ("udp_bind(ipaddr = "));
+ ip_addr_debug_print(UDP_DEBUG, ipaddr);
+ LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 3, (", port = %u)\n", port));
+
+ rebind = 0;
+ /* Check for double bind and rebind of the same pcb */
+ for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) {
+ /* is this UDP PCB already on active list? */
+ if (pcb == ipcb) {
+ /* pcb may occur at most once in active list */
+ LWIP_ASSERT("rebind == 0", rebind == 0);
+ /* pcb already in list, just rebind */
+ rebind = 1;
+ }
+
+#if SO_REUSE == 0
+/* this code does not allow upper layer to share a UDP port for
+ listening to broadcast or multicast traffic (See SO_REUSE_ADDR and
+ SO_REUSE_PORT under *BSD). TODO: See where it fits instead, OR
+ combine with implementation of UDP PCB flags. Leon Woestenberg. */
+#ifdef LWIP_UDP_TODO
+ /* port matches that of PCB in list? */
+ else if ((ipcb->local_port == port) &&
+ /* IP address matches, or one is IP_ADDR_ANY? */
+ (ip_addr_isany(&(ipcb->local_ip)) ||
+ ip_addr_isany(ipaddr) ||
+ ip_addr_cmp(&(ipcb->local_ip), ipaddr))) {
+ /* other PCB already binds to this local IP and port */
+ LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: local port %u already bound by another pcb\n", port));
+ return ERR_USE;
+ }
+#endif
+
+#else /* SO_REUSE */
+ /* Search through list of PCB's.
+
+ If there is a PCB bound to specified port and IP_ADDR_ANY another PCB can be bound to the interface IP
+ or to the loopback address on the same port if SOF_REUSEADDR is set. Any combination of PCB's bound to
+ the same local port, but to one address out of {IP_ADDR_ANY, 127.0.0.1, interface IP} at a time is valid.
+ But no two PCB's bound to same local port and same local address is valid.
+
+ If SOF_REUSEPORT is set several PCB's can be bound to same local port and same local address also. But then
+ all PCB's must have the SOF_REUSEPORT option set.
+
+ When the two options aren't set and specified port is already bound, ERR_USE is returned saying that
+ address is already in use. */
+ else if (ipcb->local_port == port) {
+ if(ip_addr_cmp(&(ipcb->local_ip), ipaddr)) {
+ if(pcb->so_options & SOF_REUSEPORT) {
+ LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: in UDP PCB's SO_REUSEPORT set and same address.\n"));
+ reuse_port_all_set = (reuse_port_all_set && (ipcb->so_options & SOF_REUSEPORT));
+ }
+ else {
+ LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: in UDP PCB's SO_REUSEPORT not set and same address.\n"));
+ return ERR_USE;
+ }
+ }
+ else if((ip_addr_isany(ipaddr) && !ip_addr_isany(&(ipcb->local_ip))) ||
+ (!ip_addr_isany(ipaddr) && ip_addr_isany(&(ipcb->local_ip)))) {
+ if(!(pcb->so_options & SOF_REUSEADDR) && !(pcb->so_options & SOF_REUSEPORT)) {
+ LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: in UDP PCB's SO_REUSEPORT or SO_REUSEADDR not set and not the same address.\n"));
+ return ERR_USE;
+ }
+ }
+ }
+#endif /* SO_REUSE */
+
+ }
+
+#if SO_REUSE
+ /* If SOF_REUSEPORT isn't set in all PCB's bound to specified port and local address specified then
+ {IP, port} can't be reused. */
+ if(!reuse_port_all_set) {
+ LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: not all sockets have SO_REUSEPORT set.\n"));
+ return ERR_USE;
+ }
+#endif /* SO_REUSE */
+
+ ip_addr_set(&pcb->local_ip, ipaddr);
+ /* no port specified? */
+ if (port == 0) {
+#ifndef UDP_LOCAL_PORT_RANGE_START
+#define UDP_LOCAL_PORT_RANGE_START 4096
+#define UDP_LOCAL_PORT_RANGE_END 0x7fff
+#endif
+ port = UDP_LOCAL_PORT_RANGE_START;
+ ipcb = udp_pcbs;
+ while ((ipcb != NULL) && (port != UDP_LOCAL_PORT_RANGE_END)) {
+ if (ipcb->local_port == port) {
+ port++;
+ ipcb = udp_pcbs;
+ } else
+ ipcb = ipcb->next;
+ }
+ if (ipcb != NULL) {
+ /* no more ports available in local range */
+ LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: out of free UDP ports\n"));
+ return ERR_USE;
+ }
+ }
+ pcb->local_port = port;
+ /* pcb not active yet? */
+ if (rebind == 0) {
+ /* place the PCB on the active list if not already there */
+ pcb->next = udp_pcbs;
+ udp_pcbs = pcb;
+ }
+ LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | DBG_STATE, ("udp_bind: bound to %u.%u.%u.%u, port %u\n",
+ (unsigned int)(ntohl(pcb->local_ip.addr) >> 24 & 0xff),
+ (unsigned int)(ntohl(pcb->local_ip.addr) >> 16 & 0xff),
+ (unsigned int)(ntohl(pcb->local_ip.addr) >> 8 & 0xff),
+ (unsigned int)(ntohl(pcb->local_ip.addr) & 0xff), pcb->local_port));
+ return ERR_OK;
+}
+/**
+ * Connect an UDP PCB.
+ *
+ * This will associate the UDP PCB with the remote address.
+ *
+ * @param pcb UDP PCB to be connected with remote address ipaddr and port.
+ * @param ipaddr remote IP address to connect with.
+ * @param port remote UDP port to connect with.
+ *
+ * @return lwIP error code
+ *
+ * @see udp_disconnect()
+ */
+err_t
+udp_connect(struct udp_pcb *pcb, struct ip_addr *ipaddr, u16_t port)
+{
+ struct udp_pcb *ipcb;
+
+ if (pcb->local_port == 0) {
+ err_t err = udp_bind(pcb, &pcb->local_ip, pcb->local_port);
+ if (err != ERR_OK)
+ return err;
+ }
+
+ ip_addr_set(&pcb->remote_ip, ipaddr);
+ pcb->remote_port = port;
+ pcb->flags |= UDP_FLAGS_CONNECTED;
+/** TODO: this functionality belongs in upper layers */
+#ifdef LWIP_UDP_TODO
+ /* Nail down local IP for netconn_addr()/getsockname() */
+ if (ip_addr_isany(&pcb->local_ip) && !ip_addr_isany(&pcb->remote_ip)) {
+ struct netif *netif;
+
+ if ((netif = ip_route(&(pcb->remote_ip))) == NULL) {
+ LWIP_DEBUGF(UDP_DEBUG, ("udp_connect: No route to 0x%lx\n", pcb->remote_ip.addr));
+ UDP_STATS_INC(udp.rterr);
+ return ERR_RTE;
+ }
+ /** TODO: this will bind the udp pcb locally, to the interface which
+ is used to route output packets to the remote address. However, we
+ might want to accept incoming packets on any interface! */
+ pcb->local_ip = netif->ip_addr;
+ } else if (ip_addr_isany(&pcb->remote_ip)) {
+ pcb->local_ip.addr = 0;
+ }
+#endif
+ LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | DBG_STATE, ("udp_connect: connected to %u.%u.%u.%u, port %u\n",
+ (unsigned int)(ntohl(pcb->remote_ip.addr) >> 24 & 0xff),
+ (unsigned int)(ntohl(pcb->remote_ip.addr) >> 16 & 0xff),
+ (unsigned int)(ntohl(pcb->remote_ip.addr) >> 8 & 0xff),
+ (unsigned int)(ntohl(pcb->remote_ip.addr) & 0xff), pcb->remote_port));
+
+ /* Insert UDP PCB into the list of active UDP PCBs. */
+ for(ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) {
+ if (pcb == ipcb) {
+ /* already on the list, just return */
+ return ERR_OK;
+ }
+ }
+ /* PCB not yet on the list, add PCB now */
+ pcb->next = udp_pcbs;
+ udp_pcbs = pcb;
+ return ERR_OK;
+}
+
+void
+udp_disconnect(struct udp_pcb *pcb)
+{
+ /* reset remote address association */
+ ip_addr_set(&pcb->remote_ip, IP_ADDR_ANY);
+ pcb->remote_port = 0;
+ /* mark PCB as unconnected */
+ pcb->flags &= ~UDP_FLAGS_CONNECTED;
+}
+
+void
+udp_recv(struct udp_pcb *pcb,
+ void (* recv)(void *arg, struct udp_pcb *upcb, struct pbuf *p,
+ struct ip_addr *addr, u16_t port),
+ void *recv_arg)
+{
+ /* remember recv() callback and user data */
+ pcb->recv = recv;
+ pcb->recv_arg = recv_arg;
+}
+/**
+ * Remove an UDP PCB.
+ *
+ * @param pcb UDP PCB to be removed. The PCB is removed from the list of
+ * UDP PCB's and the data structure is freed from memory.
+ *
+ * @see udp_new()
+ */
+void
+udp_remove(struct udp_pcb *pcb)
+{
+ struct udp_pcb *pcb2;
+ /* pcb to be removed is first in list? */
+ if (udp_pcbs == pcb) {
+ /* make list start at 2nd pcb */
+ udp_pcbs = udp_pcbs->next;
+ /* pcb not 1st in list */
+ } else for(pcb2 = udp_pcbs; pcb2 != NULL; pcb2 = pcb2->next) {
+ /* find pcb in udp_pcbs list */
+ if (pcb2->next != NULL && pcb2->next == pcb) {
+ /* remove pcb from list */
+ pcb2->next = pcb->next;
+ }
+ }
+ memp_free(MEMP_UDP_PCB, pcb);
+}
+/**
+ * Create a UDP PCB.
+ *
+ * @return The UDP PCB which was created. NULL if the PCB data structure
+ * could not be allocated.
+ *
+ * @see udp_remove()
+ */
+struct udp_pcb *
+udp_new(void) {
+ struct udp_pcb *pcb;
+ pcb = memp_malloc(MEMP_UDP_PCB);
+ /* could allocate UDP PCB? */
+ if (pcb != NULL) {
+ /* initialize PCB to all zeroes */
+ memset(pcb, 0, sizeof(struct udp_pcb));
+ pcb->ttl = UDP_TTL;
+ }
+
+
+ return pcb;
+}
+
+#if UDP_DEBUG
+int
+udp_debug_print(struct udp_hdr *udphdr)
+{
+ LWIP_DEBUGF(UDP_DEBUG, ("UDP header:\n"));
+ LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n"));
+ LWIP_DEBUGF(UDP_DEBUG, ("| %5u | %5u | (src port, dest port)\n",
+ ntohs(udphdr->src), ntohs(udphdr->dest)));
+ LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n"));
+ LWIP_DEBUGF(UDP_DEBUG, ("| %5u | 0x%04x | (len, chksum)\n",
+ ntohs(udphdr->len), ntohs(udphdr->chksum)));
+ LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n"));
+ return 0;
+}
+#endif /* UDP_DEBUG */
+
+#endif /* LWIP_UDP */
+
+
+
+
+
+
+
+
+
--- /dev/null
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef __LWIP_ICMP_H__
+#define __LWIP_ICMP_H__
+
+#include "lwip/arch.h"
+
+#include "lwip/opt.h"
+#include "lwip/pbuf.h"
+
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+
+#define ICMP_ER 0 /* echo reply */
+#define ICMP_DUR 3 /* destination unreachable */
+#define ICMP_SQ 4 /* source quench */
+#define ICMP_RD 5 /* redirect */
+#define ICMP_ECHO 8 /* echo */
+#define ICMP_TE 11 /* time exceeded */
+#define ICMP_PP 12 /* parameter problem */
+#define ICMP_TS 13 /* timestamp */
+#define ICMP_TSR 14 /* timestamp reply */
+#define ICMP_IRQ 15 /* information request */
+#define ICMP_IR 16 /* information reply */
+
+enum icmp_dur_type {
+ ICMP_DUR_NET = 0, /* net unreachable */
+ ICMP_DUR_HOST = 1, /* host unreachable */
+ ICMP_DUR_PROTO = 2, /* protocol unreachable */
+ ICMP_DUR_PORT = 3, /* port unreachable */
+ ICMP_DUR_FRAG = 4, /* fragmentation needed and DF set */
+ ICMP_DUR_SR = 5 /* source route failed */
+};
+
+enum icmp_te_type {
+ ICMP_TE_TTL = 0, /* time to live exceeded in transit */
+ ICMP_TE_FRAG = 1 /* fragment reassembly time exceeded */
+};
+
+void icmp_input(struct pbuf *p, struct netif *inp);
+
+void icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t);
+void icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t);
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct icmp_echo_hdr {
+ PACK_STRUCT_FIELD(u16_t _type_code);
+ PACK_STRUCT_FIELD(u16_t chksum);
+ PACK_STRUCT_FIELD(u16_t id);
+ PACK_STRUCT_FIELD(u16_t seqno);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+
+PACK_STRUCT_BEGIN
+struct icmp_dur_hdr {
+ PACK_STRUCT_FIELD(u16_t _type_code);
+ PACK_STRUCT_FIELD(u16_t chksum);
+ PACK_STRUCT_FIELD(u32_t unused);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+
+PACK_STRUCT_BEGIN
+struct icmp_te_hdr {
+ PACK_STRUCT_FIELD(u16_t _type_code);
+ PACK_STRUCT_FIELD(u16_t chksum);
+ PACK_STRUCT_FIELD(u32_t unused);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/epstruct.h"
+#endif
+
+#define ICMPH_TYPE(hdr) (ntohs((hdr)->_type_code) >> 8)
+#define ICMPH_CODE(hdr) (ntohs((hdr)->_type_code) & 0xff)
+
+#define ICMPH_TYPE_SET(hdr, type) ((hdr)->_type_code = htons(ICMPH_CODE(hdr) | ((type) << 8)))
+#define ICMPH_CODE_SET(hdr, code) ((hdr)->_type_code = htons((code) | (ICMPH_TYPE(hdr) << 8)))
+
+#endif /* __LWIP_ICMP_H__ */
+
--- /dev/null
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef __LWIP_INET_H__
+#define __LWIP_INET_H__
+
+#include "lwip/arch.h"
+
+#include "lwip/opt.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+
+u16_t inet_chksum(void *dataptr, u16_t len);
+u16_t inet_chksum_pbuf(struct pbuf *p);
+u16_t inet_chksum_pseudo(struct pbuf *p,
+ struct ip_addr *src, struct ip_addr *dest,
+ u8_t proto, u16_t proto_len);
+
+u32_t inet_addr(const char *cp);
+int inet_aton(const char *cp, struct in_addr *addr);
+char *inet_ntoa(struct in_addr addr); /* returns ptr to static buffer; not reentrant! */
+
+#ifdef htons
+#undef htons
+#endif /* htons */
+#ifdef htonl
+#undef htonl
+#endif /* htonl */
+#ifdef ntohs
+#undef ntohs
+#endif /* ntohs */
+#ifdef ntohl
+#undef ntohl
+#endif /* ntohl */
+
+#if BYTE_ORDER == BIG_ENDIAN
+#define htons(x) (x)
+#define ntohs(x) (x)
+#define htonl(x) (x)
+#define ntohl(x) (x)
+#else
+#ifdef LWIP_PREFIX_BYTEORDER_FUNCS
+/* workaround for naming collisions on some platforms */
+#define htons lwip_htons
+#define ntohs lwip_ntohs
+#define htonl lwip_htonl
+#define ntohl lwip_ntohl
+#endif
+u16_t htons(u16_t x);
+u16_t ntohs(u16_t x);
+u32_t htonl(u32_t x);
+u32_t ntohl(u32_t x);
+#endif
+
+#endif /* __LWIP_INET_H__ */
+
--- /dev/null
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef __LWIP_IP_H__
+#define __LWIP_IP_H__
+
+#include "lwip/arch.h"
+
+#include "lwip/def.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+
+#include "lwip/err.h"
+
+
+void ip_init(void);
+struct netif *ip_route(struct ip_addr *dest);
+err_t ip_input(struct pbuf *p, struct netif *inp);
+err_t ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+ u8_t ttl, u8_t tos, u8_t proto);
+err_t ip_output_if(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+ u8_t ttl, u8_t tos, u8_t proto,
+ struct netif *netif);
+
+#define IP_HLEN 20
+
+#define IP_PROTO_ICMP 1
+#define IP_PROTO_UDP 17
+#define IP_PROTO_UDPLITE 170
+#define IP_PROTO_TCP 6
+
+/* This is passed as the destination address to ip_output_if (not
+ to ip_output), meaning that an IP header already is constructed
+ in the pbuf. This is used when TCP retransmits. */
+#ifdef IP_HDRINCL
+#undef IP_HDRINCL
+#endif /* IP_HDRINCL */
+#define IP_HDRINCL NULL
+
+
+/* This is the common part of all PCB types. It needs to be at the
+ beginning of a PCB type definition. It is located here so that
+ changes to this common part are made in one location instead of
+ having to change all PCB structs. */
+#define IP_PCB struct ip_addr local_ip; \
+ struct ip_addr remote_ip; \
+ /* Socket options */ \
+ u16_t so_options; \
+ /* Type Of Service */ \
+ u8_t tos; \
+ /* Time To Live */ \
+ u8_t ttl
+
+/*
+ * Option flags per-socket. These are the same like SO_XXX.
+ */
+#define SOF_DEBUG (u16_t)0x0001U /* turn on debugging info recording */
+#define SOF_ACCEPTCONN (u16_t)0x0002U /* socket has had listen() */
+#define SOF_REUSEADDR (u16_t)0x0004U /* allow local address reuse */
+#define SOF_KEEPALIVE (u16_t)0x0008U /* keep connections alive */
+#define SOF_DONTROUTE (u16_t)0x0010U /* just use interface addresses */
+#define SOF_BROADCAST (u16_t)0x0020U /* permit sending of broadcast msgs */
+#define SOF_USELOOPBACK (u16_t)0x0040U /* bypass hardware when possible */
+#define SOF_LINGER (u16_t)0x0080U /* linger on close if data present */
+#define SOF_OOBINLINE (u16_t)0x0100U /* leave received OOB data in line */
+#define SOF_REUSEPORT (u16_t)0x0200U /* allow local address & port reuse */
+
+
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ip_hdr {
+ /* version / header length / type of service */
+ PACK_STRUCT_FIELD(u16_t _v_hl_tos);
+ /* total length */
+ PACK_STRUCT_FIELD(u16_t _len);
+ /* identification */
+ PACK_STRUCT_FIELD(u16_t _id);
+ /* fragment offset field */
+ PACK_STRUCT_FIELD(u16_t _offset);
+#define IP_RF 0x8000 /* reserved fragment flag */
+#define IP_DF 0x4000 /* dont fragment flag */
+#define IP_MF 0x2000 /* more fragments flag */
+#define IP_OFFMASK 0x1fff /* mask for fragmenting bits */
+ /* time to live / protocol*/
+ PACK_STRUCT_FIELD(u16_t _ttl_proto);
+ /* checksum */
+ PACK_STRUCT_FIELD(u16_t _chksum);
+ /* source and destination IP addresses */
+ PACK_STRUCT_FIELD(struct ip_addr src);
+ PACK_STRUCT_FIELD(struct ip_addr dest);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/epstruct.h"
+#endif
+
+#define IPH_V(hdr) (ntohs((hdr)->_v_hl_tos) >> 12)
+#define IPH_HL(hdr) ((ntohs((hdr)->_v_hl_tos) >> 8) & 0x0f)
+#define IPH_TOS(hdr) (ntohs((hdr)->_v_hl_tos) & 0xff)
+#define IPH_LEN(hdr) ((hdr)->_len)
+#define IPH_ID(hdr) ((hdr)->_id)
+#define IPH_OFFSET(hdr) ((hdr)->_offset)
+#define IPH_TTL(hdr) (ntohs((hdr)->_ttl_proto) >> 8)
+#define IPH_PROTO(hdr) (ntohs((hdr)->_ttl_proto) & 0xff)
+#define IPH_CHKSUM(hdr) ((hdr)->_chksum)
+
+#define IPH_VHLTOS_SET(hdr, v, hl, tos) (hdr)->_v_hl_tos = (htons(((v) << 12) | ((hl) << 8) | (tos)))
+#define IPH_LEN_SET(hdr, len) (hdr)->_len = (len)
+#define IPH_ID_SET(hdr, id) (hdr)->_id = (id)
+#define IPH_OFFSET_SET(hdr, off) (hdr)->_offset = (off)
+#define IPH_TTL_SET(hdr, ttl) (hdr)->_ttl_proto = (htons(IPH_PROTO(hdr) | ((ttl) << 8)))
+#define IPH_PROTO_SET(hdr, proto) (hdr)->_ttl_proto = (htons((proto) | (IPH_TTL(hdr) << 8)))
+#define IPH_CHKSUM_SET(hdr, chksum) (hdr)->_chksum = (chksum)
+
+#if IP_DEBUG
+void ip_debug_print(struct pbuf *p);
+#else
+#define ip_debug_print(p)
+#endif /* IP_DEBUG */
+
+#endif /* __LWIP_IP_H__ */
+
+
--- /dev/null
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef __LWIP_IP_ADDR_H__
+#define __LWIP_IP_ADDR_H__
+
+#include "lwip/arch.h"
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ip_addr {
+ PACK_STRUCT_FIELD(u32_t addr);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/epstruct.h"
+#endif
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ip_addr2 {
+ PACK_STRUCT_FIELD(u16_t addrw[2]);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/epstruct.h"
+#endif
+
+/* For compatibility with BSD code */
+struct in_addr {
+ u32_t s_addr;
+};
+
+struct netif;
+
+extern const struct ip_addr ip_addr_any;
+extern const struct ip_addr ip_addr_broadcast;
+
+/** IP_ADDR_ can be used as a fixed IP address
+ * for the wildcard and the broadcast address
+ */
+#define IP_ADDR_ANY ((struct ip_addr *)&ip_addr_any)
+#define IP_ADDR_BROADCAST ((struct ip_addr *)&ip_addr_broadcast)
+
+#define INADDR_NONE ((u32_t) 0xffffffff) /* 255.255.255.255 */
+#define INADDR_LOOPBACK ((u32_t) 0x7f000001) /* 127.0.0.1 */
+
+/* Definitions of the bits in an Internet address integer.
+
+ On subnets, host and network parts are found according to
+ the subnet mask, not these masks. */
+
+#define IN_CLASSA(a) ((((u32_t)(a)) & 0x80000000) == 0)
+#define IN_CLASSA_NET 0xff000000
+#define IN_CLASSA_NSHIFT 24
+#define IN_CLASSA_HOST (0xffffffff & ~IN_CLASSA_NET)
+#define IN_CLASSA_MAX 128
+
+#define IN_CLASSB(a) ((((u32_t)(a)) & 0xc0000000) == 0x80000000)
+#define IN_CLASSB_NET 0xffff0000
+#define IN_CLASSB_NSHIFT 16
+#define IN_CLASSB_HOST (0xffffffff & ~IN_CLASSB_NET)
+#define IN_CLASSB_MAX 65536
+
+#define IN_CLASSC(a) ((((u32_t)(a)) & 0xe0000000) == 0xc0000000)
+#define IN_CLASSC_NET 0xffffff00
+#define IN_CLASSC_NSHIFT 8
+#define IN_CLASSC_HOST (0xffffffff & ~IN_CLASSC_NET)
+
+#define IN_CLASSD(a) (((u32_t)(a) & 0xf0000000) == 0xe0000000)
+#define IN_CLASSD_NET 0xf0000000 /* These ones aren't really */
+#define IN_CLASSD_NSHIFT 28 /* net and host fields, but */
+#define IN_CLASSD_HOST 0x0fffffff /* routing needn't know. */
+#define IN_MULTICAST(a) IN_CLASSD(a)
+
+#define IN_EXPERIMENTAL(a) (((u32_t)(a) & 0xf0000000) == 0xf0000000)
+#define IN_BADCLASS(a) (((u32_t)(a) & 0xf0000000) == 0xf0000000)
+
+#define IN_LOOPBACKNET 127 /* official! */
+
+
+#define IP4_ADDR(ipaddr, a,b,c,d) (ipaddr)->addr = htonl(((u32_t)(a & 0xff) << 24) | ((u32_t)(b & 0xff) << 16) | \
+ ((u32_t)(c & 0xff) << 8) | (u32_t)(d & 0xff))
+
+#define ip_addr_set(dest, src) (dest)->addr = \
+ ((src) == NULL? 0:\
+ (src)->addr)
+/**
+ * Determine if two address are on the same network.
+ *
+ * @arg addr1 IP address 1
+ * @arg addr2 IP address 2
+ * @arg mask network identifier mask
+ * @return !0 if the network identifiers of both address match
+ */
+#define ip_addr_netcmp(addr1, addr2, mask) (((addr1)->addr & \
+ (mask)->addr) == \
+ ((addr2)->addr & \
+ (mask)->addr))
+#define ip_addr_cmp(addr1, addr2) ((addr1)->addr == (addr2)->addr)
+
+#define ip_addr_isany(addr1) ((addr1) == NULL || (addr1)->addr == 0)
+
+u8_t ip_addr_isbroadcast(struct ip_addr *, struct netif *);
+
+#define ip_addr_ismulticast(addr1) (((addr1)->addr & ntohl(0xf0000000)) == ntohl(0xe0000000))
+
+
+#define ip_addr_debug_print(debug, ipaddr) LWIP_DEBUGF(debug, ("%u.%u.%u.%u", \
+ ipaddr?(unsigned int)(ntohl((ipaddr)->addr) >> 24) & 0xff:0, \
+ ipaddr?(unsigned int)(ntohl((ipaddr)->addr) >> 16) & 0xff:0, \
+ ipaddr?(unsigned int)(ntohl((ipaddr)->addr) >> 8) & 0xff:0, \
+ ipaddr?(unsigned int)ntohl((ipaddr)->addr) & 0xff:0U))
+
+/* cast to unsigned int, as it is used as argument to printf functions
+ * which expect integer arguments */
+#define ip4_addr1(ipaddr) ((unsigned int)(ntohl((ipaddr)->addr) >> 24) & 0xff)
+#define ip4_addr2(ipaddr) ((unsigned int)(ntohl((ipaddr)->addr) >> 16) & 0xff)
+#define ip4_addr3(ipaddr) ((unsigned int)(ntohl((ipaddr)->addr) >> 8) & 0xff)
+#define ip4_addr4(ipaddr) ((unsigned int)(ntohl((ipaddr)->addr)) & 0xff)
+#endif /* __LWIP_IP_ADDR_H__ */
+
+
+
+
+
+
--- /dev/null
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Jani Monoses <jani@iv.ro>
+ *
+ */
+
+#ifndef __LWIP_IP_FRAG_H__
+#define __LWIP_IP_FRAG_H__
+
+#include "lwip/err.h"
+#include "lwip/pbuf.h"
+#include "lwip/netif.h"
+#include "lwip/ip_addr.h"
+
+struct pbuf * ip_reass(struct pbuf *);
+err_t ip_frag(struct pbuf *, struct netif *, struct ip_addr *);
+
+#endif /* __LWIP_IP_FRAG_H__ */
+
+
--- /dev/null
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef __LWIP_ICMP_H__
+#define __LWIP_ICMP_H__
+
+#include "lwip/arch.h"
+
+#include "lwip/opt.h"
+#include "lwip/pbuf.h"
+
+#include "lwip/netif.h"
+
+#define ICMP6_DUR 1
+#define ICMP6_TE 3
+#define ICMP6_ECHO 128 /* echo */
+#define ICMP6_ER 129 /* echo reply */
+
+
+enum icmp_dur_type {
+ ICMP_DUR_NET = 0, /* net unreachable */
+ ICMP_DUR_HOST = 1, /* host unreachable */
+ ICMP_DUR_PROTO = 2, /* protocol unreachable */
+ ICMP_DUR_PORT = 3, /* port unreachable */
+ ICMP_DUR_FRAG = 4, /* fragmentation needed and DF set */
+ ICMP_DUR_SR = 5 /* source route failed */
+};
+
+enum icmp_te_type {
+ ICMP_TE_TTL = 0, /* time to live exceeded in transit */
+ ICMP_TE_FRAG = 1 /* fragment reassembly time exceeded */
+};
+
+void icmp_input(struct pbuf *p, struct netif *inp);
+
+void icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t);
+void icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t);
+
+struct icmp_echo_hdr {
+ u8_t type;
+ u8_t icode;
+ u16_t chksum;
+ u16_t id;
+ u16_t seqno;
+};
+
+struct icmp_dur_hdr {
+ u8_t type;
+ u8_t icode;
+ u16_t chksum;
+ u32_t unused;
+};
+
+struct icmp_te_hdr {
+ u8_t type;
+ u8_t icode;
+ u16_t chksum;
+ u32_t unused;
+};
+
+#endif /* __LWIP_ICMP_H__ */
+
--- /dev/null
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef __LWIP_INET_H__
+#define __LWIP_INET_H__
+
+#include "lwip/arch.h"
+
+#include "lwip/opt.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+
+u16_t inet_chksum(void *data, u16_t len);
+u16_t inet_chksum_pbuf(struct pbuf *p);
+u16_t inet_chksum_pseudo(struct pbuf *p,
+ struct ip_addr *src, struct ip_addr *dest,
+ u8_t proto, u32_t proto_len);
+
+u32_t inet_addr(const char *cp);
+int inet_aton(const char *cp, struct in_addr *addr);
+
+#ifndef _MACHINE_ENDIAN_H_
+#ifndef _NETINET_IN_H
+#ifndef _LINUX_BYTEORDER_GENERIC_H
+u16_t htons(u16_t n);
+u16_t ntohs(u16_t n);
+u32_t htonl(u32_t n);
+u32_t ntohl(u32_t n);
+#endif /* _LINUX_BYTEORDER_GENERIC_H */
+#endif /* _NETINET_IN_H */
+#endif /* _MACHINE_ENDIAN_H_ */
+
+#endif /* __LWIP_INET_H__ */
+
--- /dev/null
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef __LWIP_IP_H__
+#define __LWIP_IP_H__
+
+#include "lwip/opt.h"
+#include "lwip/def.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+
+#include "lwip/err.h"
+
+#define IP_HLEN 40
+
+#define IP_PROTO_ICMP 58
+#define IP_PROTO_UDP 17
+#define IP_PROTO_UDPLITE 170
+#define IP_PROTO_TCP 6
+
+/* This is passed as the destination address to ip_output_if (not
+ to ip_output), meaning that an IP header already is constructed
+ in the pbuf. This is used when TCP retransmits. */
+#ifdef IP_HDRINCL
+#undef IP_HDRINCL
+#endif /* IP_HDRINCL */
+#define IP_HDRINCL NULL
+
+
+/* The IPv6 header. */
+struct ip_hdr {
+#if BYTE_ORDER == LITTLE_ENDIAN
+ u8_t tclass1:4, v:4;
+ u8_t flow1:4, tclass2:4;
+#else
+ u8_t v:4, tclass1:4;
+ u8_t tclass2:8, flow1:4;
+#endif
+ u16_t flow2;
+ u16_t len; /* payload length */
+ u8_t nexthdr; /* next header */
+ u8_t hoplim; /* hop limit (TTL) */
+ struct ip_addr src, dest; /* source and destination IP addresses */
+};
+
+void ip_init(void);
+
+#include "lwip/netif.h"
+
+struct netif *ip_route(struct ip_addr *dest);
+
+void ip_input(struct pbuf *p, struct netif *inp);
+
+/* source and destination addresses in network byte order, please */
+err_t ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+ unsigned char ttl, unsigned char proto);
+
+err_t ip_output_if(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+ unsigned char ttl, unsigned char proto,
+ struct netif *netif);
+
+#if IP_DEBUG
+void ip_debug_print(struct pbuf *p);
+#endif /* IP_DEBUG */
+
+#endif /* __LWIP_IP_H__ */
+
+
--- /dev/null
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef __LWIP_IP_ADDR_H__
+#define __LWIP_IP_ADDR_H__
+
+#include "lwip/arch.h"
+
+#define IP_ADDR_ANY 0
+
+struct ip_addr {
+ u32_t addr[4];
+};
+
+#define IP6_ADDR(ipaddr, a,b,c,d,e,f,g,h) do { (ipaddr)->addr[0] = htonl((u32_t)((a & 0xffff) << 16) | (b & 0xffff)); \
+ (ipaddr)->addr[1] = htonl(((c & 0xffff) << 16) | (d & 0xffff)); \
+ (ipaddr)->addr[2] = htonl(((e & 0xffff) << 16) | (f & 0xffff)); \
+ (ipaddr)->addr[3] = htonl(((g & 0xffff) << 16) | (h & 0xffff)); } while(0)
+
+int ip_addr_netcmp(struct ip_addr *addr1, struct ip_addr *addr2,
+ struct ip_addr *mask);
+int ip_addr_cmp(struct ip_addr *addr1, struct ip_addr *addr2);
+void ip_addr_set(struct ip_addr *dest, struct ip_addr *src);
+int ip_addr_isany(struct ip_addr *addr);
+
+
+#if IP_DEBUG
+void ip_addr_debug_print(struct ip_addr *addr);
+#endif /* IP_DEBUG */
+
+#endif /* __LWIP_IP_ADDR_H__ */
--- /dev/null
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef __LWIP_API_H__
+#define __LWIP_API_H__
+
+#include "lwip/opt.h"
+#include "lwip/pbuf.h"
+#include "lwip/sys.h"
+
+#include "lwip/ip.h"
+
+#include "lwip/raw.h"
+#include "lwip/udp.h"
+#include "lwip/tcp.h"
+
+#include "lwip/err.h"
+
+#define NETCONN_NOCOPY 0x00
+#define NETCONN_COPY 0x01
+
+enum netconn_type {
+ NETCONN_TCP,
+ NETCONN_UDP,
+ NETCONN_UDPLITE,
+ NETCONN_UDPNOCHKSUM,
+ NETCONN_RAW
+};
+
+enum netconn_state {
+ NETCONN_NONE,
+ NETCONN_WRITE,
+ NETCONN_ACCEPT,
+ NETCONN_RECV,
+ NETCONN_CONNECT,
+ NETCONN_CLOSE
+};
+
+enum netconn_evt {
+ NETCONN_EVT_RCVPLUS,
+ NETCONN_EVT_RCVMINUS,
+ NETCONN_EVT_SENDPLUS,
+ NETCONN_EVT_SENDMINUS
+};
+
+struct netbuf {
+ struct pbuf *p, *ptr;
+ struct ip_addr *fromaddr;
+ u16_t fromport;
+ err_t err;
+};
+
+struct netconn {
+ enum netconn_type type;
+ enum netconn_state state;
+ union {
+ struct tcp_pcb *tcp;
+ struct udp_pcb *udp;
+ struct raw_pcb *raw;
+ } pcb;
+ err_t err;
+ sys_mbox_t mbox;
+ sys_mbox_t recvmbox;
+ sys_mbox_t acceptmbox;
+ sys_sem_t sem;
+ int socket;
+ u16_t recv_avail;
+ void (* callback)(struct netconn *, enum netconn_evt, u16_t len);
+};
+
+/* Network buffer functions: */
+struct netbuf * netbuf_new (void);
+void netbuf_delete (struct netbuf *buf);
+void * netbuf_alloc (struct netbuf *buf, u16_t size);
+void netbuf_free (struct netbuf *buf);
+void netbuf_ref (struct netbuf *buf,
+ void *dataptr, u16_t size);
+void netbuf_chain (struct netbuf *head,
+ struct netbuf *tail);
+
+u16_t netbuf_len (struct netbuf *buf);
+err_t netbuf_data (struct netbuf *buf,
+ void **dataptr, u16_t *len);
+s8_t netbuf_next (struct netbuf *buf);
+void netbuf_first (struct netbuf *buf);
+
+void netbuf_copy (struct netbuf *buf,
+ void *dataptr, u16_t len);
+void netbuf_copy_partial(struct netbuf *buf, void *dataptr,
+ u16_t len, u16_t offset);
+struct ip_addr * netbuf_fromaddr (struct netbuf *buf);
+u16_t netbuf_fromport (struct netbuf *buf);
+
+/* Network connection functions: */
+struct netconn * netconn_new (enum netconn_type type);
+struct
+netconn *netconn_new_with_callback(enum netconn_type t,
+ void (*callback)(struct netconn *, enum netconn_evt, u16_t len));
+struct
+netconn *netconn_new_with_proto_and_callback(enum netconn_type t, u16_t proto,
+ void (*callback)(struct netconn *, enum netconn_evt, u16_t len));
+err_t netconn_delete (struct netconn *conn);
+enum netconn_type netconn_type (struct netconn *conn);
+err_t netconn_peer (struct netconn *conn,
+ struct ip_addr *addr,
+ u16_t *port);
+err_t netconn_addr (struct netconn *conn,
+ struct ip_addr **addr,
+ u16_t *port);
+err_t netconn_bind (struct netconn *conn,
+ struct ip_addr *addr,
+ u16_t port);
+err_t netconn_connect (struct netconn *conn,
+ struct ip_addr *addr,
+ u16_t port);
+err_t netconn_disconnect (struct netconn *conn);
+err_t netconn_listen (struct netconn *conn);
+struct netconn * netconn_accept (struct netconn *conn);
+struct netbuf * netconn_recv (struct netconn *conn);
+err_t netconn_send (struct netconn *conn,
+ struct netbuf *buf);
+err_t netconn_write (struct netconn *conn,
+ void *dataptr, u16_t size,
+ u8_t copy);
+err_t netconn_close (struct netconn *conn);
+
+err_t netconn_err (struct netconn *conn);
+
+#endif /* __LWIP_API_H__ */
+
+
--- /dev/null
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef __LWIP_API_MSG_H__
+#define __LWIP_API_MSG_H__
+
+#include "lwip/opt.h"
+#include "lwip/pbuf.h"
+#include "lwip/sys.h"
+
+#include "lwip/ip.h"
+
+#include "lwip/udp.h"
+#include "lwip/tcp.h"
+
+#include "lwip/api.h"
+
+enum api_msg_type {
+ API_MSG_NEWCONN,
+ API_MSG_DELCONN,
+
+ API_MSG_BIND,
+ API_MSG_CONNECT,
+ API_MSG_DISCONNECT,
+
+ API_MSG_LISTEN,
+ API_MSG_ACCEPT,
+
+ API_MSG_SEND,
+ API_MSG_RECV,
+ API_MSG_WRITE,
+
+ API_MSG_CLOSE,
+
+ API_MSG_MAX
+};
+
+struct api_msg_msg {
+ struct netconn *conn;
+ enum netconn_type conntype;
+ union {
+ struct pbuf *p;
+ struct {
+ struct ip_addr *ipaddr;
+ u16_t port;
+ } bc;
+ struct {
+ void *dataptr;
+ u16_t len;
+ unsigned char copy;
+ } w;
+ sys_mbox_t mbox;
+ u16_t len;
+ } msg;
+};
+
+struct api_msg {
+ enum api_msg_type type;
+ struct api_msg_msg msg;
+};
+
+void api_msg_input(struct api_msg *msg);
+void api_msg_post(struct api_msg *msg);
+
+#endif /* __LWIP_API_MSG_H__ */
+
--- /dev/null
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef __LWIP_ARCH_H__
+#define __LWIP_ARCH_H__
+
+#ifndef LITTLE_ENDIAN
+#define LITTLE_ENDIAN 1234
+#endif
+
+#ifndef BIG_ENDIAN
+#define BIG_ENDIAN 4321
+#endif
+
+#include "arch/cc.h"
+
+#ifndef PACK_STRUCT_BEGIN
+#define PACK_STRUCT_BEGIN
+#endif /* PACK_STRUCT_BEGIN */
+
+#ifndef PACK_STRUCT_END
+#define PACK_STRUCT_END
+#endif /* PACK_STRUCT_END */
+
+#ifndef PACK_STRUCT_FIELD
+#define PACK_STRUCT_FIELD(x) x
+#endif /* PACK_STRUCT_FIELD */
+
+
+
+#ifdef LWIP_PROVIDE_ERRNO
+
+#define EPERM 1 /* Operation not permitted */
+#define ENOENT 2 /* No such file or directory */
+#define ESRCH 3 /* No such process */
+#define EINTR 4 /* Interrupted system call */
+#define EIO 5 /* I/O error */
+#define ENXIO 6 /* No such device or address */
+#define E2BIG 7 /* Arg list too long */
+#define ENOEXEC 8 /* Exec format error */
+#define EBADF 9 /* Bad file number */
+#define ECHILD 10 /* No child processes */
+#define EAGAIN 11 /* Try again */
+#define ENOMEM 12 /* Out of memory */
+#define EACCES 13 /* Permission denied */
+#define EFAULT 14 /* Bad address */
+#define ENOTBLK 15 /* Block device required */
+#define EBUSY 16 /* Device or resource busy */
+#define EEXIST 17 /* File exists */
+#define EXDEV 18 /* Cross-device link */
+#define ENODEV 19 /* No such device */
+#define ENOTDIR 20 /* Not a directory */
+#define EISDIR 21 /* Is a directory */
+#define EINVAL 22 /* Invalid argument */
+#define ENFILE 23 /* File table overflow */
+#define EMFILE 24 /* Too many open files */
+#define ENOTTY 25 /* Not a typewriter */
+#define ETXTBSY 26 /* Text file busy */
+#define EFBIG 27 /* File too large */
+#define ENOSPC 28 /* No space left on device */
+#define ESPIPE 29 /* Illegal seek */
+#define EROFS 30 /* Read-only file system */
+#define EMLINK 31 /* Too many links */
+#define EPIPE 32 /* Broken pipe */
+#define EDOM 33 /* Math argument out of domain of func */
+#define ERANGE 34 /* Math result not representable */
+#define EDEADLK 35 /* Resource deadlock would occur */
+#define ENAMETOOLONG 36 /* File name too long */
+#define ENOLCK 37 /* No record locks available */
+#define ENOSYS 38 /* Function not implemented */
+#define ENOTEMPTY 39 /* Directory not empty */
+#define ELOOP 40 /* Too many symbolic links encountered */
+#define EWOULDBLOCK EAGAIN /* Operation would block */
+#define ENOMSG 42 /* No message of desired type */
+#define EIDRM 43 /* Identifier removed */
+#define ECHRNG 44 /* Channel number out of range */
+#define EL2NSYNC 45 /* Level 2 not synchronized */
+#define EL3HLT 46 /* Level 3 halted */
+#define EL3RST 47 /* Level 3 reset */
+#define ELNRNG 48 /* Link number out of range */
+#define EUNATCH 49 /* Protocol driver not attached */
+#define ENOCSI 50 /* No CSI structure available */
+#define EL2HLT 51 /* Level 2 halted */
+#define EBADE 52 /* Invalid exchange */
+#define EBADR 53 /* Invalid request descriptor */
+#define EXFULL 54 /* Exchange full */
+#define ENOANO 55 /* No anode */
+#define EBADRQC 56 /* Invalid request code */
+#define EBADSLT 57 /* Invalid slot */
+
+#define EDEADLOCK EDEADLK
+
+#define EBFONT 59 /* Bad font file format */
+#define ENOSTR 60 /* Device not a stream */
+#define ENODATA 61 /* No data available */
+#define ETIME 62 /* Timer expired */
+#define ENOSR 63 /* Out of streams resources */
+#define ENONET 64 /* Machine is not on the network */
+#define ENOPKG 65 /* Package not installed */
+#define EREMOTE 66 /* Object is remote */
+#define ENOLINK 67 /* Link has been severed */
+#define EADV 68 /* Advertise error */
+#define ESRMNT 69 /* Srmount error */
+#define ECOMM 70 /* Communication error on send */
+#define EPROTO 71 /* Protocol error */
+#define EMULTIHOP 72 /* Multihop attempted */
+#define EDOTDOT 73 /* RFS specific error */
+#define EBADMSG 74 /* Not a data message */
+#define EOVERFLOW 75 /* Value too large for defined data type */
+#define ENOTUNIQ 76 /* Name not unique on network */
+#define EBADFD 77 /* File descriptor in bad state */
+#define EREMCHG 78 /* Remote address changed */
+#define ELIBACC 79 /* Can not access a needed shared library */
+#define ELIBBAD 80 /* Accessing a corrupted shared library */
+#define ELIBSCN 81 /* .lib section in a.out corrupted */
+#define ELIBMAX 82 /* Attempting to link in too many shared libraries */
+#define ELIBEXEC 83 /* Cannot exec a shared library directly */
+#define EILSEQ 84 /* Illegal byte sequence */
+#define ERESTART 85 /* Interrupted system call should be restarted */
+#define ESTRPIPE 86 /* Streams pipe error */
+#define EUSERS 87 /* Too many users */
+#define ENOTSOCK 88 /* Socket operation on non-socket */
+#define EDESTADDRREQ 89 /* Destination address required */
+#define EMSGSIZE 90 /* Message too long */
+#define EPROTOTYPE 91 /* Protocol wrong type for socket */
+#define ENOPROTOOPT 92 /* Protocol not available */
+#define EPROTONOSUPPORT 93 /* Protocol not supported */
+#define ESOCKTNOSUPPORT 94 /* Socket type not supported */
+#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */
+#define EPFNOSUPPORT 96 /* Protocol family not supported */
+#define EAFNOSUPPORT 97 /* Address family not supported by protocol */
+#define EADDRINUSE 98 /* Address already in use */
+#define EADDRNOTAVAIL 99 /* Cannot assign requested address */
+#define ENETDOWN 100 /* Network is down */
+#define ENETUNREACH 101 /* Network is unreachable */
+#define ENETRESET 102 /* Network dropped connection because of reset */
+#define ECONNABORTED 103 /* Software caused connection abort */
+#define ECONNRESET 104 /* Connection reset by peer */
+#define ENOBUFS 105 /* No buffer space available */
+#define EISCONN 106 /* Transport endpoint is already connected */
+#define ENOTCONN 107 /* Transport endpoint is not connected */
+#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */
+#define ETOOMANYREFS 109 /* Too many references: cannot splice */
+#define ETIMEDOUT 110 /* Connection timed out */
+#define ECONNREFUSED 111 /* Connection refused */
+#define EHOSTDOWN 112 /* Host is down */
+#define EHOSTUNREACH 113 /* No route to host */
+#define EALREADY 114 /* Operation already in progress */
+#define EINPROGRESS 115 /* Operation now in progress */
+#define ESTALE 116 /* Stale NFS file handle */
+#define EUCLEAN 117 /* Structure needs cleaning */
+#define ENOTNAM 118 /* Not a XENIX named type file */
+#define ENAVAIL 119 /* No XENIX semaphores available */
+#define EISNAM 120 /* Is a named type file */
+#define EREMOTEIO 121 /* Remote I/O error */
+#define EDQUOT 122 /* Quota exceeded */
+
+#define ENOMEDIUM 123 /* No medium found */
+#define EMEDIUMTYPE 124 /* Wrong medium type */
+
+
+#define ENSROK 0 /* DNS server returned answer with no data */
+#define ENSRNODATA 160 /* DNS server returned answer with no data */
+#define ENSRFORMERR 161 /* DNS server claims query was misformatted */
+#define ENSRSERVFAIL 162 /* DNS server returned general failure */
+#define ENSRNOTFOUND 163 /* Domain name not found */
+#define ENSRNOTIMP 164 /* DNS server does not implement requested operation */
+#define ENSRREFUSED 165 /* DNS server refused query */
+#define ENSRBADQUERY 166 /* Misformatted DNS query */
+#define ENSRBADNAME 167 /* Misformatted domain name */
+#define ENSRBADFAMILY 168 /* Unsupported address family */
+#define ENSRBADRESP 169 /* Misformatted DNS reply */
+#define ENSRCONNREFUSED 170 /* Could not contact DNS servers */
+#define ENSRTIMEOUT 171 /* Timeout while contacting DNS servers */
+#define ENSROF 172 /* End of file */
+#define ENSRFILE 173 /* Error reading file */
+#define ENSRNOMEM 174 /* Out of memory */
+#define ENSRDESTRUCTION 175 /* Application terminated lookup */
+#define ENSRQUERYDOMAINTOOLONG 176 /* Domain name is too long */
+#define ENSRCNAMELOOP 177 /* Domain name is too long */
+
+#ifndef errno
+extern int errno;
+#endif
+
+#endif /* LWIP_PROVIDE_ERRNO */
+
+#endif /* __LWIP_ARCH_H__ */
--- /dev/null
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef __LWIP_DEBUG_H__
+#define __LWIP_DEBUG_H__
+
+#include "arch/cc.h"
+
+/** lower two bits indicate debug level
+ * - 0 off
+ * - 1 warning
+ * - 2 serious
+ * - 3 severe
+ */
+
+#define DBG_LEVEL_OFF 0
+#define DBG_LEVEL_WARNING 1 /* bad checksums, dropped packets, ... */
+#define DBG_LEVEL_SERIOUS 2 /* memory allocation failures, ... */
+#define DBG_LEVEL_SEVERE 3 /* */
+#define DBG_MASK_LEVEL 3
+
+/** flag for LWIP_DEBUGF to enable that debug message */
+#define DBG_ON 0x80U
+/** flag for LWIP_DEBUGF to disable that debug message */
+#define DBG_OFF 0x00U
+
+/** flag for LWIP_DEBUGF indicating a tracing message (to follow program flow) */
+#define DBG_TRACE 0x40U
+/** flag for LWIP_DEBUGF indicating a state debug message (to follow module states) */
+#define DBG_STATE 0x20U
+/** flag for LWIP_DEBUGF indicating newly added code, not thoroughly tested yet */
+#define DBG_FRESH 0x10U
+/** flag for LWIP_DEBUGF to halt after printing this debug message */
+#define DBG_HALT 0x08U
+
+#ifndef LWIP_NOASSERT
+# define LWIP_ASSERT(x,y) do { if(!(y)) LWIP_PLATFORM_ASSERT(x); } while(0)
+#else
+# define LWIP_ASSERT(x,y)
+#endif
+
+#ifdef LWIP_DEBUG
+/** print debug message only if debug message type is enabled...
+ * AND is of correct type AND is at least DBG_LEVEL
+ */
+# define LWIP_DEBUGF(debug,x) do { if (((debug) & DBG_ON) && ((debug) & DBG_TYPES_ON) && ((int)((debug) & DBG_MASK_LEVEL) >= DBG_MIN_LEVEL)) { LWIP_PLATFORM_DIAG(x); if ((debug) & DBG_HALT) while(1); } } while(0)
+# define LWIP_ERROR(x) do { LWIP_PLATFORM_DIAG(x); } while(0)
+#else /* LWIP_DEBUG */
+# define LWIP_DEBUGF(debug,x)
+# define LWIP_ERROR(x)
+#endif /* LWIP_DEBUG */
+
+#endif /* __LWIP_DEBUG_H__ */
+
+
+
+
+
+
--- /dev/null
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef __LWIP_DEF_H__
+#define __LWIP_DEF_H__
+
+/* this might define NULL already */
+#include "arch/cc.h"
+
+#define LWIP_MAX(x , y) (x) > (y) ? (x) : (y)
+#define LWIP_MIN(x , y) (x) < (y) ? (x) : (y)
+
+#ifndef NULL
+#define NULL ((void *)0)
+#endif
+
+
+#endif /* __LWIP_DEF_H__ */
+
--- /dev/null
+/** @file
+ */
+
+#ifndef __LWIP_DHCP_H__
+#define __LWIP_DHCP_H__
+
+#include "lwip/opt.h"
+#include "lwip/netif.h"
+#include "lwip/udp.h"
+
+/** period (in seconds) of the application calling dhcp_coarse_tmr() */
+#define DHCP_COARSE_TIMER_SECS 60
+/** period (in milliseconds) of the application calling dhcp_fine_tmr() */
+#define DHCP_FINE_TIMER_MSECS 500
+
+struct dhcp
+{
+ /** current DHCP state machine state */
+ u8_t state;
+ /** retries of current request */
+ u8_t tries;
+ /** transaction identifier of last sent request */
+ u32_t xid;
+ /** our connection to the DHCP server */
+ struct udp_pcb *pcb;
+ /** (first) pbuf of incoming msg */
+ struct pbuf *p;
+ /** incoming msg */
+ struct dhcp_msg *msg_in;
+ /** incoming msg options */
+ struct dhcp_msg *options_in;
+ /** ingoing msg options length */
+ u16_t options_in_len;
+
+ struct pbuf *p_out; /* pbuf of outcoming msg */
+ struct dhcp_msg *msg_out; /* outgoing msg */
+ u16_t options_out_len; /* outgoing msg options length */
+ u16_t request_timeout; /* #ticks with period DHCP_FINE_TIMER_SECS for request timeout */
+ u16_t t1_timeout; /* #ticks with period DHCP_COARSE_TIMER_SECS for renewal time */
+ u16_t t2_timeout; /* #ticks with period DHCP_COARSE_TIMER_SECS for rebind time */
+ struct ip_addr server_ip_addr; /* dhcp server address that offered this lease */
+ struct ip_addr offered_ip_addr;
+ struct ip_addr offered_sn_mask;
+ struct ip_addr offered_gw_addr;
+ struct ip_addr offered_bc_addr;
+#define DHCP_MAX_DNS 2
+ u32_t dns_count; /* actual number of DNS servers obtained */
+ struct ip_addr offered_dns_addr[DHCP_MAX_DNS]; /* DNS server addresses */
+
+ u32_t offered_t0_lease; /* lease period (in seconds) */
+ u32_t offered_t1_renew; /* recommended renew time (usually 50% of lease period) */
+ u32_t offered_t2_rebind; /* recommended rebind time (usually 66% of lease period) */
+/** Patch #1308
+ * TODO: See dhcp.c "TODO"s
+ */
+#if 0
+ struct ip_addr offered_si_addr;
+ u8_t *boot_file_name;
+#endif
+};
+
+/* MUST be compiled with "pack structs" or equivalent! */
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+/** minimum set of fields of any DHCP message */
+struct dhcp_msg
+{
+ PACK_STRUCT_FIELD(u8_t op);
+ PACK_STRUCT_FIELD(u8_t htype);
+ PACK_STRUCT_FIELD(u8_t hlen);
+ PACK_STRUCT_FIELD(u8_t hops);
+ PACK_STRUCT_FIELD(u32_t xid);
+ PACK_STRUCT_FIELD(u16_t secs);
+ PACK_STRUCT_FIELD(u16_t flags);
+ PACK_STRUCT_FIELD(struct ip_addr ciaddr);
+ PACK_STRUCT_FIELD(struct ip_addr yiaddr);
+ PACK_STRUCT_FIELD(struct ip_addr siaddr);
+ PACK_STRUCT_FIELD(struct ip_addr giaddr);
+#define DHCP_CHADDR_LEN 16U
+ PACK_STRUCT_FIELD(u8_t chaddr[DHCP_CHADDR_LEN]);
+#define DHCP_SNAME_LEN 64U
+ PACK_STRUCT_FIELD(u8_t sname[DHCP_SNAME_LEN]);
+#define DHCP_FILE_LEN 128U
+ PACK_STRUCT_FIELD(u8_t file[DHCP_FILE_LEN]);
+ PACK_STRUCT_FIELD(u32_t cookie);
+#define DHCP_MIN_OPTIONS_LEN 68U
+/** make sure user does not configure this too small */
+#if ((defined(DHCP_OPTIONS_LEN)) && (DHCP_OPTIONS_LEN < DHCP_MIN_OPTIONS_LEN))
+# undef DHCP_OPTIONS_LEN
+#endif
+/** allow this to be configured in lwipopts.h, but not too small */
+#if (!defined(DHCP_OPTIONS_LEN))
+/** set this to be sufficient for your options in outgoing DHCP msgs */
+# define DHCP_OPTIONS_LEN DHCP_MIN_OPTIONS_LEN
+#endif
+ PACK_STRUCT_FIELD(u8_t options[DHCP_OPTIONS_LEN]);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/epstruct.h"
+#endif
+
+/** start DHCP configuration */
+err_t dhcp_start(struct netif *netif);
+/** enforce early lease renewal (not needed normally)*/
+err_t dhcp_renew(struct netif *netif);
+/** release the DHCP lease, usually called before dhcp_stop()*/
+err_t dhcp_release(struct netif *netif);
+/** stop DHCP configuration */
+void dhcp_stop(struct netif *netif);
+/** inform server of our manual IP address */
+void dhcp_inform(struct netif *netif);
+
+/** if enabled, check whether the offered IP address is not in use, using ARP */
+#if DHCP_DOES_ARP_CHECK
+void dhcp_arp_reply(struct netif *netif, struct ip_addr *addr);
+#endif
+
+/** to be called every minute */
+void dhcp_coarse_tmr(void);
+/** to be called every half second */
+void dhcp_fine_tmr(void);
+
+/** DHCP message item offsets and length */
+#define DHCP_MSG_OFS (UDP_DATA_OFS)
+ #define DHCP_OP_OFS (DHCP_MSG_OFS + 0)
+ #define DHCP_HTYPE_OFS (DHCP_MSG_OFS + 1)
+ #define DHCP_HLEN_OFS (DHCP_MSG_OFS + 2)
+ #define DHCP_HOPS_OFS (DHCP_MSG_OFS + 3)
+ #define DHCP_XID_OFS (DHCP_MSG_OFS + 4)
+ #define DHCP_SECS_OFS (DHCP_MSG_OFS + 8)
+ #define DHCP_FLAGS_OFS (DHCP_MSG_OFS + 10)
+ #define DHCP_CIADDR_OFS (DHCP_MSG_OFS + 12)
+ #define DHCP_YIADDR_OFS (DHCP_MSG_OFS + 16)
+ #define DHCP_SIADDR_OFS (DHCP_MSG_OFS + 20)
+ #define DHCP_GIADDR_OFS (DHCP_MSG_OFS + 24)
+ #define DHCP_CHADDR_OFS (DHCP_MSG_OFS + 28)
+ #define DHCP_SNAME_OFS (DHCP_MSG_OFS + 44)
+ #define DHCP_FILE_OFS (DHCP_MSG_OFS + 108)
+#define DHCP_MSG_LEN 236
+
+#define DHCP_COOKIE_OFS (DHCP_MSG_OFS + DHCP_MSG_LEN)
+#define DHCP_OPTIONS_OFS (DHCP_MSG_OFS + DHCP_MSG_LEN + 4)
+
+#define DHCP_CLIENT_PORT 68
+#define DHCP_SERVER_PORT 67
+
+/** DHCP client states */
+#define DHCP_REQUESTING 1
+#define DHCP_INIT 2
+#define DHCP_REBOOTING 3
+#define DHCP_REBINDING 4
+#define DHCP_RENEWING 5
+#define DHCP_SELECTING 6
+#define DHCP_INFORMING 7
+#define DHCP_CHECKING 8
+#define DHCP_PERMANENT 9
+#define DHCP_BOUND 10
+/** not yet implemented #define DHCP_RELEASING 11 */
+#define DHCP_BACKING_OFF 12
+#define DHCP_OFF 13
+
+#define DHCP_BOOTREQUEST 1
+#define DHCP_BOOTREPLY 2
+
+#define DHCP_DISCOVER 1
+#define DHCP_OFFER 2
+#define DHCP_REQUEST 3
+#define DHCP_DECLINE 4
+#define DHCP_ACK 5
+#define DHCP_NAK 6
+#define DHCP_RELEASE 7
+#define DHCP_INFORM 8
+
+#define DHCP_HTYPE_ETH 1
+
+#define DHCP_HLEN_ETH 6
+
+#define DHCP_BROADCAST_FLAG 15
+#define DHCP_BROADCAST_MASK (1 << DHCP_FLAG_BROADCAST)
+
+/** BootP options */
+#define DHCP_OPTION_PAD 0
+#define DHCP_OPTION_SUBNET_MASK 1 /* RFC 2132 3.3 */
+#define DHCP_OPTION_ROUTER 3
+#define DHCP_OPTION_DNS_SERVER 6
+#define DHCP_OPTION_HOSTNAME 12
+#define DHCP_OPTION_IP_TTL 23
+#define DHCP_OPTION_MTU 26
+#define DHCP_OPTION_BROADCAST 28
+#define DHCP_OPTION_TCP_TTL 37
+#define DHCP_OPTION_END 255
+
+/** DHCP options */
+#define DHCP_OPTION_REQUESTED_IP 50 /* RFC 2132 9.1, requested IP address */
+#define DHCP_OPTION_LEASE_TIME 51 /* RFC 2132 9.2, time in seconds, in 4 bytes */
+#define DHCP_OPTION_OVERLOAD 52 /* RFC2132 9.3, use file and/or sname field for options */
+
+#define DHCP_OPTION_MESSAGE_TYPE 53 /* RFC 2132 9.6, important for DHCP */
+#define DHCP_OPTION_MESSAGE_TYPE_LEN 1
+
+
+#define DHCP_OPTION_SERVER_ID 54 /* RFC 2132 9.7, server IP address */
+#define DHCP_OPTION_PARAMETER_REQUEST_LIST 55 /* RFC 2132 9.8, requested option types */
+
+#define DHCP_OPTION_MAX_MSG_SIZE 57 /* RFC 2132 9.10, message size accepted >= 576 */
+#define DHCP_OPTION_MAX_MSG_SIZE_LEN 2
+
+#define DHCP_OPTION_T1 58 /* T1 renewal time */
+#define DHCP_OPTION_T2 59 /* T2 rebinding time */
+#define DHCP_OPTION_CLIENT_ID 61
+#define DHCP_OPTION_TFTP_SERVERNAME 66
+#define DHCP_OPTION_BOOTFILE 67
+
+/** possible combinations of overloading the file and sname fields with options */
+#define DHCP_OVERLOAD_NONE 0
+#define DHCP_OVERLOAD_FILE 1
+#define DHCP_OVERLOAD_SNAME 2
+#define DHCP_OVERLOAD_SNAME_FILE 3
+
+#endif /*__LWIP_DHCP_H__*/
--- /dev/null
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef __LWIP_ERR_H__
+#define __LWIP_ERR_H__
+
+#include "lwip/opt.h"
+
+#include "arch/cc.h"
+
+typedef s8_t err_t;
+
+/* Definitions for error constants. */
+
+#define ERR_OK 0 /* No error, everything OK. */
+#define ERR_MEM -1 /* Out of memory error. */
+#define ERR_BUF -2 /* Buffer error. */
+
+
+#define ERR_ABRT -3 /* Connection aborted. */
+#define ERR_RST -4 /* Connection reset. */
+#define ERR_CLSD -5 /* Connection closed. */
+#define ERR_CONN -6 /* Not connected. */
+
+#define ERR_VAL -7 /* Illegal value. */
+
+#define ERR_ARG -8 /* Illegal argument. */
+
+#define ERR_RTE -9 /* Routing problem. */
+
+#define ERR_USE -10 /* Address in use. */
+
+#define ERR_IF -11 /* Low-level netif error */
+#define ERR_ISCONN -12 /* Already connected. */
+
+
+#ifdef LWIP_DEBUG
+extern char *lwip_strerr(err_t err);
+#else
+#define lwip_strerr(x) ""
+#endif /* LWIP_DEBUG */
+#endif /* __LWIP_ERR_H__ */
--- /dev/null
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef __LWIP_MEM_H__
+#define __LWIP_MEM_H__
+
+#include "lwip/opt.h"
+#include "lwip/arch.h"
+
+#if MEM_SIZE > 64000l
+typedef u32_t mem_size_t;
+#else
+typedef u16_t mem_size_t;
+#endif /* MEM_SIZE > 64000 */
+
+
+void mem_init(void);
+
+void *mem_malloc(mem_size_t size);
+void mem_free(void *mem);
+void *mem_realloc(void *mem, mem_size_t size);
+void *mem_reallocm(void *mem, mem_size_t size);
+
+#ifndef MEM_ALIGN_SIZE
+#define MEM_ALIGN_SIZE(size) (((size) + MEM_ALIGNMENT - 1) & ~(MEM_ALIGNMENT-1))
+#endif
+
+#ifndef MEM_ALIGN
+#define MEM_ALIGN(addr) ((void *)(((mem_ptr_t)(addr) + MEM_ALIGNMENT - 1) & ~(mem_ptr_t)(MEM_ALIGNMENT-1)))
+#endif
+
+#endif /* __LWIP_MEM_H__ */
+
--- /dev/null
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+#ifndef __LWIP_MEMP_H__
+#define __LWIP_MEMP_H__
+
+#include "lwip/opt.h"
+
+typedef enum {
+ MEMP_PBUF,
+ MEMP_RAW_PCB,
+ MEMP_UDP_PCB,
+ MEMP_TCP_PCB,
+ MEMP_TCP_PCB_LISTEN,
+ MEMP_TCP_SEG,
+
+ MEMP_NETBUF,
+ MEMP_NETCONN,
+ MEMP_API_MSG,
+ MEMP_TCPIP_MSG,
+
+ MEMP_SYS_TIMEOUT,
+
+ MEMP_MAX
+} memp_t;
+
+void memp_init(void);
+
+void *memp_malloc(memp_t type);
+void *memp_realloc(memp_t fromtype, memp_t totype, void *mem);
+void memp_free(memp_t type, void *mem);
+
+#endif /* __LWIP_MEMP_H__ */
+
--- /dev/null
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef __LWIP_NETIF_H__
+#define __LWIP_NETIF_H__
+
+#include "lwip/opt.h"
+
+#include "lwip/err.h"
+
+#include "lwip/ip_addr.h"
+
+#include "lwip/inet.h"
+#include "lwip/pbuf.h"
+#if LWIP_DHCP
+# include "lwip/dhcp.h"
+#endif
+
+/** must be the maximum of all used hardware address lengths
+ across all types of interfaces in use */
+#define NETIF_MAX_HWADDR_LEN 6U
+
+/** TODO: define the use (where, when, whom) of netif flags */
+
+/** whether the network interface is 'up'. this is
+ * a software flag used to control whether this network
+ * interface is enabled and processes traffic.
+ */
+#define NETIF_FLAG_UP 0x1U
+/** if set, the netif has broadcast capability */
+#define NETIF_FLAG_BROADCAST 0x2U
+/** if set, the netif is one end of a point-to-point connection */
+#define NETIF_FLAG_POINTTOPOINT 0x4U
+/** if set, the interface is configured using DHCP */
+#define NETIF_FLAG_DHCP 0x08U
+/** if set, the interface has an active link
+ * (set by the network interface driver) */
+#define NETIF_FLAG_LINK_UP 0x10U
+
+/** Generic data structure used for all lwIP network interfaces.
+ * The following fields should be filled in by the initialization
+ * function for the device driver: hwaddr_len, hwaddr[], mtu, flags */
+
+struct netif {
+ /** pointer to next in linked list */
+ struct netif *next;
+
+ /** IP address configuration in network byte order */
+ struct ip_addr ip_addr;
+ struct ip_addr netmask;
+ struct ip_addr gw;
+
+ /** This function is called by the network device driver
+ * to pass a packet up the TCP/IP stack. */
+ err_t (* input)(struct pbuf *p, struct netif *inp);
+ /** This function is called by the IP module when it wants
+ * to send a packet on the interface. This function typically
+ * first resolves the hardware address, then sends the packet. */
+ err_t (* output)(struct netif *netif, struct pbuf *p,
+ struct ip_addr *ipaddr);
+ /** This function is called by the ARP module when it wants
+ * to send a packet on the interface. This function outputs
+ * the pbuf as-is on the link medium. */
+ err_t (* linkoutput)(struct netif *netif, struct pbuf *p);
+ /** This field can be set by the device driver and could point
+ * to state information for the device. */
+ void *state;
+#if LWIP_DHCP
+ /** the DHCP client state information for this netif */
+ struct dhcp *dhcp;
+#endif
+ /** number of bytes used in hwaddr */
+ unsigned char hwaddr_len;
+ /** link level hardware address of this interface */
+ unsigned char hwaddr[NETIF_MAX_HWADDR_LEN];
+ /** maximum transfer unit (in bytes) */
+ u16_t mtu;
+ /** flags (see NETIF_FLAG_ above) */
+ u8_t flags;
+ /** link type */
+ u8_t link_type;
+ /** descriptive abbreviation */
+ char name[2];
+ /** number of this interface */
+ u8_t num;
+};
+
+/** The list of network interfaces. */
+extern struct netif *netif_list;
+/** The default network interface. */
+extern struct netif *netif_default;
+
+/* netif_init() must be called first. */
+void netif_init(void);
+
+struct netif *netif_add(struct netif *netif, struct ip_addr *ipaddr, struct ip_addr *netmask,
+ struct ip_addr *gw,
+ void *state,
+ err_t (* init)(struct netif *netif),
+ err_t (* input)(struct pbuf *p, struct netif *netif));
+
+void
+netif_set_addr(struct netif *netif,struct ip_addr *ipaddr, struct ip_addr *netmask,
+ struct ip_addr *gw);
+void netif_remove(struct netif * netif);
+
+/* Returns a network interface given its name. The name is of the form
+ "et0", where the first two letters are the "name" field in the
+ netif structure, and the digit is in the num field in the same
+ structure. */
+struct netif *netif_find(char *name);
+
+void netif_set_default(struct netif *netif);
+
+void netif_set_ipaddr(struct netif *netif, struct ip_addr *ipaddr);
+void netif_set_netmask(struct netif *netif, struct ip_addr *netmast);
+void netif_set_gw(struct netif *netif, struct ip_addr *gw);
+void netif_set_up(struct netif *netif);
+void netif_set_down(struct netif *netif);
+u8_t netif_is_up(struct netif *netif);
+
+#endif /* __LWIP_NETIF_H__ */
--- /dev/null
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef __LWIP_OPT_H__
+#define __LWIP_OPT_H__
+
+/* Include user defined options first */
+#include "lwipopts.h"
+#include "lwip/debug.h"
+
+/* Define default values for unconfigured parameters. */
+
+/* Platform specific locking */
+
+/*
+ * enable SYS_LIGHTWEIGHT_PROT in lwipopts.h if you want inter-task protection
+ * for certain critical regions during buffer allocation, deallocation and memory
+ * allocation and deallocation.
+ */
+#ifndef SYS_LIGHTWEIGHT_PROT
+#define SYS_LIGHTWEIGHT_PROT 0
+#endif
+
+#ifndef NO_SYS
+#define NO_SYS 0
+#endif
+/* ---------- Memory options ---------- */
+/* MEM_ALIGNMENT: should be set to the alignment of the CPU for which
+ lwIP is compiled. 4 byte alignment -> define MEM_ALIGNMENT to 4, 2
+ byte alignment -> define MEM_ALIGNMENT to 2. */
+
+#ifndef MEM_ALIGNMENT
+#define MEM_ALIGNMENT 1
+#endif
+
+/* MEM_SIZE: the size of the heap memory. If the application will send
+a lot of data that needs to be copied, this should be set high. */
+#ifndef MEM_SIZE
+#define MEM_SIZE 1600
+#endif
+
+#ifndef MEMP_SANITY_CHECK
+#define MEMP_SANITY_CHECK 0
+#endif
+
+/* MEMP_NUM_PBUF: the number of memp struct pbufs. If the application
+ sends a lot of data out of ROM (or other static memory), this
+ should be set high. */
+#ifndef MEMP_NUM_PBUF
+#define MEMP_NUM_PBUF 16
+#endif
+
+/* Number of raw connection PCBs */
+#ifndef MEMP_NUM_RAW_PCB
+#define MEMP_NUM_RAW_PCB 4
+#endif
+
+/* MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One
+ per active UDP "connection". */
+#ifndef MEMP_NUM_UDP_PCB
+#define MEMP_NUM_UDP_PCB 4
+#endif
+/* MEMP_NUM_TCP_PCB: the number of simulatenously active TCP
+ connections. */
+#ifndef MEMP_NUM_TCP_PCB
+#define MEMP_NUM_TCP_PCB 5
+#endif
+/* MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP
+ connections. */
+#ifndef MEMP_NUM_TCP_PCB_LISTEN
+#define MEMP_NUM_TCP_PCB_LISTEN 8
+#endif
+/* MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP
+ segments. */
+#ifndef MEMP_NUM_TCP_SEG
+#define MEMP_NUM_TCP_SEG 16
+#endif
+/* MEMP_NUM_SYS_TIMEOUT: the number of simulateously active
+ timeouts. */
+#ifndef MEMP_NUM_SYS_TIMEOUT
+#define MEMP_NUM_SYS_TIMEOUT 3
+#endif
+
+/* The following four are used only with the sequential API and can be
+ set to 0 if the application only will use the raw API. */
+/* MEMP_NUM_NETBUF: the number of struct netbufs. */
+#ifndef MEMP_NUM_NETBUF
+#define MEMP_NUM_NETBUF 2
+#endif
+/* MEMP_NUM_NETCONN: the number of struct netconns. */
+#ifndef MEMP_NUM_NETCONN
+#define MEMP_NUM_NETCONN 4
+#endif
+/* MEMP_NUM_APIMSG: the number of struct api_msg, used for
+ communication between the TCP/IP stack and the sequential
+ programs. */
+#ifndef MEMP_NUM_API_MSG
+#define MEMP_NUM_API_MSG 8
+#endif
+/* MEMP_NUM_TCPIPMSG: the number of struct tcpip_msg, which is used
+ for sequential API communication and incoming packets. Used in
+ src/api/tcpip.c. */
+#ifndef MEMP_NUM_TCPIP_MSG
+#define MEMP_NUM_TCPIP_MSG 8
+#endif
+
+/* ---------- Pbuf options ---------- */
+/* PBUF_POOL_SIZE: the number of buffers in the pbuf pool. */
+
+#ifndef PBUF_POOL_SIZE
+#define PBUF_POOL_SIZE 16
+#endif
+
+/* PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. */
+
+#ifndef PBUF_POOL_BUFSIZE
+#define PBUF_POOL_BUFSIZE 128
+#endif
+
+/* PBUF_LINK_HLEN: the number of bytes that should be allocated for a
+ link level header. Defaults to 14 for Ethernet. */
+
+#ifndef PBUF_LINK_HLEN
+#define PBUF_LINK_HLEN 14
+#endif
+
+
+
+/* ---------- ARP options ---------- */
+
+/** Number of active hardware address, IP address pairs cached */
+#ifndef ARP_TABLE_SIZE
+#define ARP_TABLE_SIZE 10
+#endif
+
+/**
+ * If enabled, outgoing packets are queued during hardware address
+ * resolution.
+ *
+ * This feature has not stabilized yet. Single-packet queueing is
+ * believed to be stable, multi-packet queueing is believed to
+ * clash with the TCP segment queueing.
+ *
+ * As multi-packet-queueing is currently disabled, enabling this
+ * _should_ work, but we need your testing feedback on lwip-users.
+ *
+ */
+#ifndef ARP_QUEUEING
+#define ARP_QUEUEING 1
+#endif
+
+/* This option is deprecated */
+#ifdef ETHARP_QUEUE_FIRST
+#error ETHARP_QUEUE_FIRST option is deprecated. Remove it from your lwipopts.h.
+#endif
+
+/* This option is removed to comply with the ARP standard */
+#ifdef ETHARP_ALWAYS_INSERT
+#error ETHARP_ALWAYS_INSERT option is deprecated. Remove it from your lwipopts.h.
+#endif
+
+/* ---------- IP options ---------- */
+/* Define IP_FORWARD to 1 if you wish to have the ability to forward
+ IP packets across network interfaces. If you are going to run lwIP
+ on a device with only one network interface, define this to 0. */
+#ifndef IP_FORWARD
+#define IP_FORWARD 0
+#endif
+
+/* If defined to 1, IP options are allowed (but not parsed). If
+ defined to 0, all packets with IP options are dropped. */
+#ifndef IP_OPTIONS
+#define IP_OPTIONS 1
+#endif
+
+/** IP reassembly and segmentation. Even if they both deal with IP
+ * fragments, note that these are orthogonal, one dealing with incoming
+ * packets, the other with outgoing packets
+ */
+
+/** Reassemble incoming fragmented IP packets */
+#ifndef IP_REASSEMBLY
+#define IP_REASSEMBLY 1
+#endif
+
+/** Fragment outgoing IP packets if their size exceeds MTU */
+#ifndef IP_FRAG
+#define IP_FRAG 1
+#endif
+
+/* ---------- ICMP options ---------- */
+
+#ifndef ICMP_TTL
+#define ICMP_TTL 255
+#endif
+
+/* ---------- RAW options ---------- */
+
+#ifndef LWIP_RAW
+#define LWIP_RAW 1
+#endif
+
+#ifndef RAW_TTL
+#define RAW_TTL 255
+#endif
+
+/* ---------- DHCP options ---------- */
+
+#ifndef LWIP_DHCP
+#define LWIP_DHCP 0
+#endif
+
+/* 1 if you want to do an ARP check on the offered address
+ (recommended). */
+#ifndef DHCP_DOES_ARP_CHECK
+#define DHCP_DOES_ARP_CHECK 1
+#endif
+
+/* ---------- UDP options ---------- */
+#ifndef LWIP_UDP
+#define LWIP_UDP 1
+#endif
+
+#ifndef UDP_TTL
+#define UDP_TTL 255
+#endif
+
+/* ---------- TCP options ---------- */
+#ifndef LWIP_TCP
+#define LWIP_TCP 1
+#endif
+
+#ifndef TCP_TTL
+#define TCP_TTL 255
+#endif
+
+#ifndef TCP_WND
+#define TCP_WND 2048
+#endif
+
+#ifndef TCP_MAXRTX
+#define TCP_MAXRTX 12
+#endif
+
+#ifndef TCP_SYNMAXRTX
+#define TCP_SYNMAXRTX 6
+#endif
+
+
+/* Controls if TCP should queue segments that arrive out of
+ order. Define to 0 if your device is low on memory. */
+#ifndef TCP_QUEUE_OOSEQ
+#define TCP_QUEUE_OOSEQ 1
+#endif
+
+/* TCP Maximum segment size. */
+#ifndef TCP_MSS
+#define TCP_MSS 128 /* A *very* conservative default. */
+#endif
+
+/* TCP sender buffer space (bytes). */
+#ifndef TCP_SND_BUF
+#define TCP_SND_BUF 256
+#endif
+
+/* TCP sender buffer space (pbufs). This must be at least = 2 *
+ TCP_SND_BUF/TCP_MSS for things to work. */
+#ifndef TCP_SND_QUEUELEN
+#define TCP_SND_QUEUELEN 4 * TCP_SND_BUF/TCP_MSS
+#endif
+
+
+/* Maximum number of retransmissions of data segments. */
+
+/* Maximum number of retransmissions of SYN segments. */
+
+/* TCP writable space (bytes). This must be less than or equal
+ to TCP_SND_BUF. It is the amount of space which must be
+ available in the tcp snd_buf for select to return writable */
+#ifndef TCP_SNDLOWAT
+#define TCP_SNDLOWAT TCP_SND_BUF/2
+#endif
+
+/* Support loop interface (127.0.0.1) */
+#ifndef LWIP_HAVE_LOOPIF
+#define LWIP_HAVE_LOOPIF 1
+#endif
+
+#ifndef LWIP_EVENT_API
+#define LWIP_EVENT_API 0
+#define LWIP_CALLBACK_API 1
+#else
+#define LWIP_EVENT_API 1
+#define LWIP_CALLBACK_API 0
+#endif
+
+#ifndef LWIP_COMPAT_SOCKETS
+#define LWIP_COMPAT_SOCKETS 1
+#endif
+
+
+#ifndef TCPIP_THREAD_PRIO
+#define TCPIP_THREAD_PRIO 1
+#endif
+
+#ifndef SLIPIF_THREAD_PRIO
+#define SLIPIF_THREAD_PRIO 1
+#endif
+
+#ifndef PPP_THREAD_PRIO
+#define PPP_THREAD_PRIO 1
+#endif
+
+#ifndef DEFAULT_THREAD_PRIO
+#define DEFAULT_THREAD_PRIO 1
+#endif
+
+
+/* ---------- Socket Options ---------- */
+/* Enable SO_REUSEADDR and SO_REUSEPORT options */
+#ifndef SO_REUSE
+# define SO_REUSE 0
+#endif
+
+
+/* ---------- Statistics options ---------- */
+#ifndef LWIP_STATS
+#define LWIP_STATS 1
+#endif
+
+#if LWIP_STATS
+
+#ifndef LWIP_STATS_DISPLAY
+#define LWIP_STATS_DISPLAY 0
+#endif
+
+#ifndef LINK_STATS
+#define LINK_STATS 1
+#endif
+
+#ifndef IP_STATS
+#define IP_STATS 1
+#endif
+
+#ifndef IPFRAG_STATS
+#define IPFRAG_STATS 1
+#endif
+
+#ifndef ICMP_STATS
+#define ICMP_STATS 1
+#endif
+
+#ifndef UDP_STATS
+#define UDP_STATS 1
+#endif
+
+#ifndef TCP_STATS
+#define TCP_STATS 1
+#endif
+
+#ifndef MEM_STATS
+#define MEM_STATS 1
+#endif
+
+#ifndef MEMP_STATS
+#define MEMP_STATS 1
+#endif
+
+#ifndef PBUF_STATS
+#define PBUF_STATS 1
+#endif
+
+#ifndef SYS_STATS
+#define SYS_STATS 1
+#endif
+
+#ifndef RAW_STATS
+#define RAW_STATS 0
+#endif
+
+#else
+
+#define LINK_STATS 0
+#define IP_STATS 0
+#define IPFRAG_STATS 0
+#define ICMP_STATS 0
+#define UDP_STATS 0
+#define TCP_STATS 0
+#define MEM_STATS 0
+#define MEMP_STATS 0
+#define PBUF_STATS 0
+#define SYS_STATS 0
+#define RAW_STATS 0
+#define LWIP_STATS_DISPLAY 0
+
+#endif /* LWIP_STATS */
+
+/* ---------- PPP options ---------- */
+
+#ifndef PPP_SUPPORT
+#define PPP_SUPPORT 0 /* Set for PPP */
+#endif
+
+#if PPP_SUPPORT
+
+#define NUM_PPP 1 /* Max PPP sessions. */
+
+
+
+#ifndef PAP_SUPPORT
+#define PAP_SUPPORT 0 /* Set for PAP. */
+#endif
+
+#ifndef CHAP_SUPPORT
+#define CHAP_SUPPORT 0 /* Set for CHAP. */
+#endif
+
+#define MSCHAP_SUPPORT 0 /* Set for MSCHAP (NOT FUNCTIONAL!) */
+#define CBCP_SUPPORT 0 /* Set for CBCP (NOT FUNCTIONAL!) */
+#define CCP_SUPPORT 0 /* Set for CCP (NOT FUNCTIONAL!) */
+
+#ifndef VJ_SUPPORT
+#define VJ_SUPPORT 0 /* Set for VJ header compression. */
+#endif
+
+#ifndef MD5_SUPPORT
+#define MD5_SUPPORT 0 /* Set for MD5 (see also CHAP) */
+#endif
+
+
+/*
+ * Timeouts.
+ */
+#define FSM_DEFTIMEOUT 6 /* Timeout time in seconds */
+#define FSM_DEFMAXTERMREQS 2 /* Maximum Terminate-Request transmissions */
+#define FSM_DEFMAXCONFREQS 10 /* Maximum Configure-Request transmissions */
+#define FSM_DEFMAXNAKLOOPS 5 /* Maximum number of nak loops */
+
+#define UPAP_DEFTIMEOUT 6 /* Timeout (seconds) for retransmitting req */
+#define UPAP_DEFREQTIME 30 /* Time to wait for auth-req from peer */
+
+#define CHAP_DEFTIMEOUT 6 /* Timeout time in seconds */
+#define CHAP_DEFTRANSMITS 10 /* max # times to send challenge */
+
+
+/* Interval in seconds between keepalive echo requests, 0 to disable. */
+#if 1
+#define LCP_ECHOINTERVAL 0
+#else
+#define LCP_ECHOINTERVAL 10
+#endif
+
+/* Number of unanswered echo requests before failure. */
+#define LCP_MAXECHOFAILS 3
+
+/* Max Xmit idle time (in jiffies) before resend flag char. */
+#define PPP_MAXIDLEFLAG 100
+
+/*
+ * Packet sizes
+ *
+ * Note - lcp shouldn't be allowed to negotiate stuff outside these
+ * limits. See lcp.h in the pppd directory.
+ * (XXX - these constants should simply be shared by lcp.c instead
+ * of living in lcp.h)
+ */
+#define PPP_MTU 1500 /* Default MTU (size of Info field) */
+#if 0
+#define PPP_MAXMTU 65535 - (PPP_HDRLEN + PPP_FCSLEN)
+#else
+#define PPP_MAXMTU 1500 /* Largest MTU we allow */
+#endif
+#define PPP_MINMTU 64
+#define PPP_MRU 1500 /* default MRU = max length of info field */
+#define PPP_MAXMRU 1500 /* Largest MRU we allow */
+#define PPP_DEFMRU 296 /* Try for this */
+#define PPP_MINMRU 128 /* No MRUs below this */
+
+
+#define MAXNAMELEN 256 /* max length of hostname or name for auth */
+#define MAXSECRETLEN 256 /* max length of password or secret */
+
+#endif /* PPP_SUPPORT */
+
+/* checksum options - set to zero for hardware checksum support */
+
+#ifndef CHECKSUM_GEN_IP
+#define CHECKSUM_GEN_IP 1
+#endif
+
+#ifndef CHECKSUM_GEN_UDP
+#define CHECKSUM_GEN_UDP 1
+#endif
+
+#ifndef CHECKSUM_GEN_TCP
+#define CHECKSUM_GEN_TCP 1
+#endif
+
+#ifndef CHECKSUM_CHECK_IP
+#define CHECKSUM_CHECK_IP 1
+#endif
+
+#ifndef CHECKSUM_CHECK_UDP
+#define CHECKSUM_CHECK_UDP 1
+#endif
+
+#ifndef CHECKSUM_CHECK_TCP
+#define CHECKSUM_CHECK_TCP 1
+#endif
+
+/* Debugging options all default to off */
+
+#ifndef DBG_TYPES_ON
+#define DBG_TYPES_ON 0
+#endif
+
+#ifndef ETHARP_DEBUG
+#define ETHARP_DEBUG DBG_OFF
+#endif
+
+#ifndef NETIF_DEBUG
+#define NETIF_DEBUG DBG_OFF
+#endif
+
+#ifndef PBUF_DEBUG
+#define PBUF_DEBUG DBG_OFF
+#endif
+
+#ifndef API_LIB_DEBUG
+#define API_LIB_DEBUG DBG_OFF
+#endif
+
+#ifndef API_MSG_DEBUG
+#define API_MSG_DEBUG DBG_OFF
+#endif
+
+#ifndef SOCKETS_DEBUG
+#define SOCKETS_DEBUG DBG_OFF
+#endif
+
+#ifndef ICMP_DEBUG
+#define ICMP_DEBUG DBG_OFF
+#endif
+
+#ifndef INET_DEBUG
+#define INET_DEBUG DBG_OFF
+#endif
+
+#ifndef IP_DEBUG
+#define IP_DEBUG DBG_OFF
+#endif
+
+#ifndef IP_REASS_DEBUG
+#define IP_REASS_DEBUG DBG_OFF
+#endif
+
+#ifndef RAW_DEBUG
+#define RAW_DEBUG DBG_OFF
+#endif
+
+#ifndef MEM_DEBUG
+#define MEM_DEBUG DBG_OFF
+#endif
+
+#ifndef MEMP_DEBUG
+#define MEMP_DEBUG DBG_OFF
+#endif
+
+#ifndef SYS_DEBUG
+#define SYS_DEBUG DBG_OFF
+#endif
+
+#ifndef TCP_DEBUG
+#define TCP_DEBUG DBG_OFF
+#endif
+
+#ifndef TCP_INPUT_DEBUG
+#define TCP_INPUT_DEBUG DBG_OFF
+#endif
+
+#ifndef TCP_FR_DEBUG
+#define TCP_FR_DEBUG DBG_OFF
+#endif
+
+#ifndef TCP_RTO_DEBUG
+#define TCP_RTO_DEBUG DBG_OFF
+#endif
+
+#ifndef TCP_REXMIT_DEBUG
+#define TCP_REXMIT_DEBUG DBG_OFF
+#endif
+
+#ifndef TCP_CWND_DEBUG
+#define TCP_CWND_DEBUG DBG_OFF
+#endif
+
+#ifndef TCP_WND_DEBUG
+#define TCP_WND_DEBUG DBG_OFF
+#endif
+
+#ifndef TCP_OUTPUT_DEBUG
+#define TCP_OUTPUT_DEBUG DBG_OFF
+#endif
+
+#ifndef TCP_RST_DEBUG
+#define TCP_RST_DEBUG DBG_OFF
+#endif
+
+#ifndef TCP_QLEN_DEBUG
+#define TCP_QLEN_DEBUG DBG_OFF
+#endif
+
+#ifndef UDP_DEBUG
+#define UDP_DEBUG DBG_OFF
+#endif
+
+#ifndef TCPIP_DEBUG
+#define TCPIP_DEBUG DBG_OFF
+#endif
+
+#ifndef PPP_DEBUG
+#define PPP_DEBUG DBG_OFF
+#endif
+
+#ifndef SLIP_DEBUG
+#define SLIP_DEBUG DBG_OFF
+#endif
+
+#ifndef DHCP_DEBUG
+#define DHCP_DEBUG DBG_OFF
+#endif
+
+
+#ifndef DBG_MIN_LEVEL
+#define DBG_MIN_LEVEL DBG_LEVEL_OFF
+#endif
+
+#endif /* __LWIP_OPT_H__ */
+
+
+
--- /dev/null
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+#ifndef __LWIP_PBUF_H__
+#define __LWIP_PBUF_H__
+
+#include "arch/cc.h"
+
+
+#define PBUF_TRANSPORT_HLEN 20
+#define PBUF_IP_HLEN 20
+
+typedef enum {
+ PBUF_TRANSPORT,
+ PBUF_IP,
+ PBUF_LINK,
+ PBUF_RAW
+} pbuf_layer;
+
+typedef enum {
+ PBUF_RAM,
+ PBUF_ROM,
+ PBUF_REF,
+ PBUF_POOL
+} pbuf_flag;
+
+/* Definitions for the pbuf flag field. These are NOT the flags that
+ * are passed to pbuf_alloc(). */
+#define PBUF_FLAG_RAM 0x00U /* Flags that pbuf data is stored in RAM */
+#define PBUF_FLAG_ROM 0x01U /* Flags that pbuf data is stored in ROM */
+#define PBUF_FLAG_POOL 0x02U /* Flags that the pbuf comes from the pbuf pool */
+#define PBUF_FLAG_REF 0x04U /* Flags thet the pbuf payload refers to RAM */
+
+/** indicates this packet was broadcast on the link */
+#define PBUF_FLAG_LINK_BROADCAST 0x80U
+
+struct pbuf {
+ /** next pbuf in singly linked pbuf chain */
+ struct pbuf *next;
+
+ /** pointer to the actual data in the buffer */
+ void *payload;
+
+ /**
+ * total length of this buffer and all next buffers in chain
+ * belonging to the same packet.
+ *
+ * For non-queue packet chains this is the invariant:
+ * p->tot_len == p->len + (p->next? p->next->tot_len: 0)
+ */
+ u16_t tot_len;
+
+ /** length of this buffer */
+ u16_t len;
+
+ /** flags telling the type of pbuf, see PBUF_FLAG_ */
+ u16_t flags;
+
+ /**
+ * the reference count always equals the number of pointers
+ * that refer to this pbuf. This can be pointers from an application,
+ * the stack itself, or pbuf->next pointers from a chain.
+ */
+ u16_t ref;
+
+};
+
+void pbuf_init(void);
+
+struct pbuf *pbuf_alloc(pbuf_layer l, u16_t size, pbuf_flag flag);
+void pbuf_realloc(struct pbuf *p, u16_t size);
+u8_t pbuf_header(struct pbuf *p, s16_t header_size);
+void pbuf_ref(struct pbuf *p);
+void pbuf_ref_chain(struct pbuf *p);
+u8_t pbuf_free(struct pbuf *p);
+u8_t pbuf_clen(struct pbuf *p);
+void pbuf_cat(struct pbuf *h, struct pbuf *t);
+void pbuf_chain(struct pbuf *h, struct pbuf *t);
+struct pbuf *pbuf_take(struct pbuf *f);
+struct pbuf *pbuf_dechain(struct pbuf *p);
+void pbuf_queue(struct pbuf *p, struct pbuf *n);
+struct pbuf * pbuf_dequeue(struct pbuf *p);
+
+#endif /* __LWIP_PBUF_H__ */
--- /dev/null
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef __LWIP_RAW_H__
+#define __LWIP_RAW_H__
+
+#include "lwip/arch.h"
+
+#include "lwip/pbuf.h"
+#include "lwip/inet.h"
+#include "lwip/ip.h"
+
+struct raw_pcb {
+/* Common members of all PCB types */
+ IP_PCB;
+
+ struct raw_pcb *next;
+
+ u16_t protocol;
+
+ u8_t (* recv)(void *arg, struct raw_pcb *pcb, struct pbuf *p,
+ struct ip_addr *addr);
+ void *recv_arg;
+};
+
+/* The following functions is the application layer interface to the
+ RAW code. */
+struct raw_pcb * raw_new (u16_t proto);
+void raw_remove (struct raw_pcb *pcb);
+err_t raw_bind (struct raw_pcb *pcb, struct ip_addr *ipaddr);
+err_t raw_connect (struct raw_pcb *pcb, struct ip_addr *ipaddr);
+
+void raw_recv (struct raw_pcb *pcb,
+ u8_t (* recv)(void *arg, struct raw_pcb *pcb,
+ struct pbuf *p,
+ struct ip_addr *addr),
+ void *recv_arg);
+err_t raw_sendto (struct raw_pcb *pcb, struct pbuf *p, struct ip_addr *ipaddr);
+err_t raw_send (struct raw_pcb *pcb, struct pbuf *p);
+
+/* The following functions are the lower layer interface to RAW. */
+u8_t raw_input (struct pbuf *p, struct netif *inp);
+void raw_init (void);
+
+
+#endif /* __LWIP_RAW_H__ */
--- /dev/null
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ */
+
+/*
+ * This is the interface to the platform specific serial IO module
+ * It needs to be implemented by those platforms which need SLIP or PPP
+ */
+
+#include "arch/cc.h"
+
+#ifndef __sio_fd_t_defined
+typedef void * sio_fd_t;
+#endif
+
+#ifndef sio_open
+sio_fd_t sio_open(u8_t);
+#endif
+
+#ifndef sio_send
+void sio_send(u8_t, sio_fd_t);
+#endif
+
+#ifndef sio_recv
+u8_t sio_recv(sio_fd_t);
+#endif
+
+#ifndef sio_read
+u32_t sio_read(sio_fd_t, u8_t *, u32_t);
+#endif
+
+#ifndef sio_write
+u32_t sio_write(sio_fd_t, u8_t *, u32_t);
+#endif
+
+#ifndef sio_read_abort
+void sio_read_abort(sio_fd_t);
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2001, 2002 Leon Woestenberg <leon.woestenberg@axon.tv>
+ * Copyright (c) 2001, 2002 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Leon Woestenberg <leon.woestenberg@axon.tv>
+ *
+ */
+#ifndef __LWIP_SNMP_H__
+#define __LWIP_SNMP_H__
+
+#include "lwip/opt.h"
+
+/* SNMP support available? */
+#if defined(LWIP_SNMP) && (LWIP_SNMP > 0)
+
+/* network interface */
+void snmp_add_ifinoctets(unsigned long value);
+void snmp_inc_ifinucastpkts(void);
+void snmp_inc_ifinnucastpkts(void);
+void snmp_inc_ifindiscards(void);
+void snmp_add_ifoutoctets(unsigned long value);
+void snmp_inc_ifoutucastpkts(void);
+void snmp_inc_ifoutnucastpkts(void);
+void snmp_inc_ifoutdiscards(void);
+
+/* IP */
+void snmp_inc_ipinreceives(void);
+void snmp_inc_ipindelivers(void);
+void snmp_inc_ipindiscards(void);
+void snmp_inc_ipoutdiscards(void);
+void snmp_inc_ipoutrequests(void);
+void snmp_inc_ipunknownprotos(void);
+void snmp_inc_ipnoroutes(void);
+void snmp_inc_ipforwdatagrams(void);
+
+/* ICMP */
+void snmp_inc_icmpinmsgs(void);
+void snmp_inc_icmpinerrors(void);
+void snmp_inc_icmpindestunreachs(void);
+void snmp_inc_icmpintimeexcds(void);
+void snmp_inc_icmpinparmprobs(void);
+void snmp_inc_icmpinsrcquenchs(void);
+void snmp_inc_icmpinredirects(void);
+void snmp_inc_icmpinechos(void);
+void snmp_inc_icmpinechoreps(void);
+void snmp_inc_icmpintimestamps(void);
+void snmp_inc_icmpintimestampreps(void);
+void snmp_inc_icmpinaddrmasks(void);
+void snmp_inc_icmpinaddrmaskreps(void);
+void snmp_inc_icmpoutmsgs(void);
+void snmp_inc_icmpouterrors(void);
+void snmp_inc_icmpoutdestunreachs(void);
+void snmp_inc_icmpouttimeexcds(void);
+void snmp_inc_icmpoutparmprobs(void);
+void snmp_inc_icmpoutsrcquenchs(void);
+void snmp_inc_icmpoutredirects(void);
+void snmp_inc_icmpoutechos(void);
+void snmp_inc_icmpoutechoreps(void);
+void snmp_inc_icmpouttimestamps(void);
+void snmp_inc_icmpouttimestampreps(void);
+void snmp_inc_icmpoutaddrmasks(void);
+void snmp_inc_icmpoutaddrmaskreps(void);
+
+/* TCP */
+void snmp_inc_tcpactiveopens(void);
+void snmp_inc_tcppassiveopens(void);
+void snmp_inc_tcpattemptfails(void);
+void snmp_inc_tcpestabresets(void);
+void snmp_inc_tcpcurrestab(void);
+void snmp_inc_tcpinsegs(void);
+void snmp_inc_tcpoutsegs(void);
+void snmp_inc_tcpretranssegs(void);
+void snmp_inc_tcpinerrs(void);
+void snmp_inc_tcpoutrsts(void);
+
+/* UDP */
+void snmp_inc_udpindatagrams(void);
+void snmp_inc_udpnoports(void);
+void snmp_inc_udpinerrors(void);
+void snmp_inc_udpoutdatagrams(void);
+
+/* LWIP_SNMP support not available */
+/* define everything to be empty */
+#else
+
+/* network interface */
+#define snmp_add_ifinoctets(value)
+#define snmp_inc_ifinucastpkts()
+#define snmp_inc_ifinnucastpkts()
+#define snmp_inc_ifindiscards()
+#define snmp_add_ifoutoctets(value)
+#define snmp_inc_ifoutucastpkts()
+#define snmp_inc_ifoutnucastpkts()
+#define snmp_inc_ifoutdiscards()
+
+/* IP */
+#define snmp_inc_ipinreceives()
+#define snmp_inc_ipindelivers()
+#define snmp_inc_ipindiscards()
+#define snmp_inc_ipoutdiscards()
+#define snmp_inc_ipoutrequests()
+#define snmp_inc_ipunknownprotos()
+#define snmp_inc_ipnoroutes()
+#define snmp_inc_ipforwdatagrams()
+
+/* ICMP */
+#define snmp_inc_icmpinmsgs()
+#define snmp_inc_icmpinerrors()
+#define snmp_inc_icmpindestunreachs()
+#define snmp_inc_icmpintimeexcds()
+#define snmp_inc_icmpinparmprobs()
+#define snmp_inc_icmpinsrcquenchs()
+#define snmp_inc_icmpinredirects()
+#define snmp_inc_icmpinechos()
+#define snmp_inc_icmpinechoreps()
+#define snmp_inc_icmpintimestamps()
+#define snmp_inc_icmpintimestampreps()
+#define snmp_inc_icmpinaddrmasks()
+#define snmp_inc_icmpinaddrmaskreps()
+#define snmp_inc_icmpoutmsgs()
+#define snmp_inc_icmpouterrors()
+#define snmp_inc_icmpoutdestunreachs()
+#define snmp_inc_icmpouttimeexcds()
+#define snmp_inc_icmpoutparmprobs()
+#define snmp_inc_icmpoutsrcquenchs()
+#define snmp_inc_icmpoutredirects()
+#define snmp_inc_icmpoutechos()
+#define snmp_inc_icmpoutechoreps()
+#define snmp_inc_icmpouttimestamps()
+#define snmp_inc_icmpouttimestampreps()
+#define snmp_inc_icmpoutaddrmasks()
+#define snmp_inc_icmpoutaddrmaskreps()
+/* TCP */
+#define snmp_inc_tcpactiveopens()
+#define snmp_inc_tcppassiveopens()
+#define snmp_inc_tcpattemptfails()
+#define snmp_inc_tcpestabresets()
+#define snmp_inc_tcpcurrestab()
+#define snmp_inc_tcpinsegs()
+#define snmp_inc_tcpoutsegs()
+#define snmp_inc_tcpretranssegs()
+#define snmp_inc_tcpinerrs()
+#define snmp_inc_tcpoutrsts()
+
+/* UDP */
+#define snmp_inc_udpindatagrams()
+#define snmp_inc_udpnoports()
+#define snmp_inc_udpinerrors()
+#define snmp_inc_udpoutdatagrams()
+
+#endif
+
+#endif /* __LWIP_SNMP_H__ */
--- /dev/null
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+
+#ifndef __LWIP_SOCKETS_H__
+#define __LWIP_SOCKETS_H__
+#include "lwip/ip_addr.h"
+
+struct sockaddr_in {
+ u8_t sin_len;
+ u8_t sin_family;
+ u16_t sin_port;
+ struct in_addr sin_addr;
+ char sin_zero[8];
+};
+
+struct sockaddr {
+ u8_t sa_len;
+ u8_t sa_family;
+ char sa_data[14];
+};
+
+#ifndef socklen_t
+# define socklen_t int
+#endif
+
+
+#define SOCK_STREAM 1
+#define SOCK_DGRAM 2
+#define SOCK_RAW 3
+
+/*
+ * Option flags per-socket.
+ */
+#define SO_DEBUG 0x0001 /* turn on debugging info recording */
+#define SO_ACCEPTCONN 0x0002 /* socket has had listen() */
+#define SO_REUSEADDR 0x0004 /* allow local address reuse */
+#define SO_KEEPALIVE 0x0008 /* keep connections alive */
+#define SO_DONTROUTE 0x0010 /* just use interface addresses */
+#define SO_BROADCAST 0x0020 /* permit sending of broadcast msgs */
+#define SO_USELOOPBACK 0x0040 /* bypass hardware when possible */
+#define SO_LINGER 0x0080 /* linger on close if data present */
+#define SO_OOBINLINE 0x0100 /* leave received OOB data in line */
+#define SO_REUSEPORT 0x0200 /* allow local address & port reuse */
+
+#define SO_DONTLINGER (int)(~SO_LINGER)
+
+/*
+ * Additional options, not kept in so_options.
+ */
+#define SO_SNDBUF 0x1001 /* send buffer size */
+#define SO_RCVBUF 0x1002 /* receive buffer size */
+#define SO_SNDLOWAT 0x1003 /* send low-water mark */
+#define SO_RCVLOWAT 0x1004 /* receive low-water mark */
+#define SO_SNDTIMEO 0x1005 /* send timeout */
+#define SO_RCVTIMEO 0x1006 /* receive timeout */
+#define SO_ERROR 0x1007 /* get error status and clear */
+#define SO_TYPE 0x1008 /* get socket type */
+
+
+
+/*
+ * Structure used for manipulating linger option.
+ */
+struct linger {
+ int l_onoff; /* option on/off */
+ int l_linger; /* linger time */
+};
+
+/*
+ * Level number for (get/set)sockopt() to apply to socket itself.
+ */
+#define SOL_SOCKET 0xfff /* options for socket level */
+
+
+#define AF_UNSPEC 0
+#define AF_INET 2
+#define PF_INET AF_INET
+#define PF_UNSPEC AF_UNSPEC
+
+#define IPPROTO_IP 0
+#define IPPROTO_TCP 6
+#define IPPROTO_UDP 17
+
+#define INADDR_ANY 0
+#define INADDR_BROADCAST 0xffffffff
+
+/* Flags we can use with send and recv. */
+#define MSG_DONTWAIT 0x40 /* Nonblocking i/o for this operation only */
+
+
+/*
+ * Options for level IPPROTO_IP
+ */
+#define IP_TOS 1
+#define IP_TTL 2
+
+
+#define IPTOS_TOS_MASK 0x1E
+#define IPTOS_TOS(tos) ((tos) & IPTOS_TOS_MASK)
+#define IPTOS_LOWDELAY 0x10
+#define IPTOS_THROUGHPUT 0x08
+#define IPTOS_RELIABILITY 0x04
+#define IPTOS_LOWCOST 0x02
+#define IPTOS_MINCOST IPTOS_LOWCOST
+
+/*
+ * Definitions for IP precedence (also in ip_tos) (hopefully unused)
+ */
+#define IPTOS_PREC_MASK 0xe0
+#define IPTOS_PREC(tos) ((tos) & IPTOS_PREC_MASK)
+#define IPTOS_PREC_NETCONTROL 0xe0
+#define IPTOS_PREC_INTERNETCONTROL 0xc0
+#define IPTOS_PREC_CRITIC_ECP 0xa0
+#define IPTOS_PREC_FLASHOVERRIDE 0x80
+#define IPTOS_PREC_FLASH 0x60
+#define IPTOS_PREC_IMMEDIATE 0x40
+#define IPTOS_PREC_PRIORITY 0x20
+#define IPTOS_PREC_ROUTINE 0x00
+
+
+/*
+ * Commands for ioctlsocket(), taken from the BSD file fcntl.h.
+ *
+ *
+ * Ioctl's have the command encoded in the lower word,
+ * and the size of any in or out parameters in the upper
+ * word. The high 2 bits of the upper word are used
+ * to encode the in/out status of the parameter; for now
+ * we restrict parameters to at most 128 bytes.
+ */
+#if !defined(FIONREAD) || !defined(FIONBIO)
+#define IOCPARM_MASK 0x7f /* parameters must be < 128 bytes */
+#define IOC_VOID 0x20000000 /* no parameters */
+#define IOC_OUT 0x40000000 /* copy out parameters */
+#define IOC_IN 0x80000000 /* copy in parameters */
+#define IOC_INOUT (IOC_IN|IOC_OUT)
+ /* 0x20000000 distinguishes new &
+ old ioctl's */
+#define _IO(x,y) (IOC_VOID|((x)<<8)|(y))
+
+#define _IOR(x,y,t) (IOC_OUT|(((long)sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y))
+
+#define _IOW(x,y,t) (IOC_IN|(((long)sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y))
+#endif
+
+#ifndef FIONREAD
+#define FIONREAD _IOR('f', 127, unsigned long) /* get # bytes to read */
+#endif
+#ifndef FIONBIO
+#define FIONBIO _IOW('f', 126, unsigned long) /* set/clear non-blocking i/o */
+#endif
+
+/* Socket I/O Controls */
+#ifndef SIOCSHIWAT
+#define SIOCSHIWAT _IOW('s', 0, unsigned long) /* set high watermark */
+#define SIOCGHIWAT _IOR('s', 1, unsigned long) /* get high watermark */
+#define SIOCSLOWAT _IOW('s', 2, unsigned long) /* set low watermark */
+#define SIOCGLOWAT _IOR('s', 3, unsigned long) /* get low watermark */
+#define SIOCATMARK _IOR('s', 7, unsigned long) /* at oob mark? */
+#endif
+
+#ifndef O_NONBLOCK
+#define O_NONBLOCK 04000U
+#endif
+
+#ifndef FD_SET
+ #undef FD_SETSIZE
+ #define FD_SETSIZE 16
+ #define FD_SET(n, p) ((p)->fd_bits[(n)/8] |= (1 << ((n) & 7)))
+ #define FD_CLR(n, p) ((p)->fd_bits[(n)/8] &= ~(1 << ((n) & 7)))
+ #define FD_ISSET(n,p) ((p)->fd_bits[(n)/8] & (1 << ((n) & 7)))
+ #define FD_ZERO(p) memset((void*)(p),0,sizeof(*(p)))
+
+ typedef struct fd_set {
+ unsigned char fd_bits [(FD_SETSIZE+7)/8];
+ } fd_set;
+
+/*
+ * only define this in sockets.c so it does not interfere
+ * with other projects namespaces where timeval is present
+ */
+#ifndef LWIP_TIMEVAL_PRIVATE
+#define LWIP_TIMEVAL_PRIVATE 1
+#endif
+
+#if LWIP_TIMEVAL_PRIVATE
+ struct timeval {
+ long tv_sec; /* seconds */
+ long tv_usec; /* and microseconds */
+ };
+#endif
+
+#endif
+
+int lwip_accept(int s, struct sockaddr *addr, socklen_t *addrlen);
+int lwip_bind(int s, struct sockaddr *name, socklen_t namelen);
+int lwip_shutdown(int s, int how);
+int lwip_getpeername (int s, struct sockaddr *name, socklen_t *namelen);
+int lwip_getsockname (int s, struct sockaddr *name, socklen_t *namelen);
+int lwip_getsockopt (int s, int level, int optname, void *optval, socklen_t *optlen);
+int lwip_setsockopt (int s, int level, int optname, const void *optval, socklen_t optlen);
+int lwip_close(int s);
+int lwip_connect(int s, struct sockaddr *name, socklen_t namelen);
+int lwip_listen(int s, int backlog);
+int lwip_recv(int s, void *mem, int len, unsigned int flags);
+int lwip_read(int s, void *mem, int len);
+int lwip_recvfrom(int s, void *mem, int len, unsigned int flags,
+ struct sockaddr *from, socklen_t *fromlen);
+int lwip_send(int s, void *dataptr, int size, unsigned int flags);
+int lwip_sendto(int s, void *dataptr, int size, unsigned int flags,
+ struct sockaddr *to, socklen_t tolen);
+int lwip_socket(int domain, int type, int protocol);
+int lwip_write(int s, void *dataptr, int size);
+int lwip_select(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset,
+ struct timeval *timeout);
+int lwip_ioctl(int s, long cmd, void *argp);
+
+#if LWIP_COMPAT_SOCKETS
+#define accept(a,b,c) lwip_accept(a,b,c)
+#define bind(a,b,c) lwip_bind(a,b,c)
+#define shutdown(a,b) lwip_shutdown(a,b)
+#define close(s) lwip_close(s)
+#define connect(a,b,c) lwip_connect(a,b,c)
+#define getsockname(a,b,c) lwip_getsockname(a,b,c)
+#define getpeername(a,b,c) lwip_getpeername(a,b,c)
+#define setsockopt(a,b,c,d,e) lwip_setsockopt(a,b,c,d,e)
+#define getsockopt(a,b,c,d,e) lwip_getsockopt(a,b,c,d,e)
+#define listen(a,b) lwip_listen(a,b)
+#define recv(a,b,c,d) lwip_recv(a,b,c,d)
+#define read(a,b,c) lwip_read(a,b,c)
+#define recvfrom(a,b,c,d,e,f) lwip_recvfrom(a,b,c,d,e,f)
+#define send(a,b,c,d) lwip_send(a,b,c,d)
+#define sendto(a,b,c,d,e,f) lwip_sendto(a,b,c,d,e,f)
+#define socket(a,b,c) lwip_socket(a,b,c)
+#define write(a,b,c) lwip_write(a,b,c)
+#define select(a,b,c,d,e) lwip_select(a,b,c,d,e)
+#define ioctlsocket(a,b,c) lwip_ioctl(a,b,c)
+#endif /* LWIP_COMPAT_SOCKETS */
+
+#endif /* __LWIP_SOCKETS_H__ */
+
--- /dev/null
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef __LWIP_STATS_H__
+#define __LWIP_STATS_H__
+
+#include "lwip/opt.h"
+#include "arch/cc.h"
+
+#include "lwip/mem.h"
+#include "lwip/memp.h"
+
+#if LWIP_STATS
+
+struct stats_proto {
+ u16_t xmit; /* Transmitted packets. */
+ u16_t rexmit; /* Retransmitted packets. */
+ u16_t recv; /* Received packets. */
+ u16_t fw; /* Forwarded packets. */
+ u16_t drop; /* Dropped packets. */
+ u16_t chkerr; /* Checksum error. */
+ u16_t lenerr; /* Invalid length error. */
+ u16_t memerr; /* Out of memory error. */
+ u16_t rterr; /* Routing error. */
+ u16_t proterr; /* Protocol error. */
+ u16_t opterr; /* Error in options. */
+ u16_t err; /* Misc error. */
+ u16_t cachehit;
+};
+
+struct stats_mem {
+ mem_size_t avail;
+ mem_size_t used;
+ mem_size_t max;
+ mem_size_t err;
+};
+
+struct stats_pbuf {
+ u16_t avail;
+ u16_t used;
+ u16_t max;
+ u16_t err;
+
+ u16_t alloc_locked;
+ u16_t refresh_locked;
+};
+
+struct stats_syselem {
+ u16_t used;
+ u16_t max;
+ u16_t err;
+};
+
+struct stats_sys {
+ struct stats_syselem sem;
+ struct stats_syselem mbox;
+};
+
+struct stats_ {
+ struct stats_proto link;
+ struct stats_proto ip_frag;
+ struct stats_proto ip;
+ struct stats_proto icmp;
+ struct stats_proto udp;
+ struct stats_proto tcp;
+ struct stats_pbuf pbuf;
+ struct stats_mem mem;
+ struct stats_mem memp[MEMP_MAX];
+ struct stats_sys sys;
+};
+
+extern struct stats_ lwip_stats;
+
+
+void stats_init(void);
+
+#define STATS_INC(x) ++lwip_stats.x
+#else
+#define stats_init()
+#define STATS_INC(x)
+#endif /* LWIP_STATS */
+
+#if TCP_STATS
+#define TCP_STATS_INC(x) STATS_INC(x)
+#else
+#define TCP_STATS_INC(x)
+#endif
+
+#if UDP_STATS
+#define UDP_STATS_INC(x) STATS_INC(x)
+#else
+#define UDP_STATS_INC(x)
+#endif
+
+#if ICMP_STATS
+#define ICMP_STATS_INC(x) STATS_INC(x)
+#else
+#define ICMP_STATS_INC(x)
+#endif
+
+#if IP_STATS
+#define IP_STATS_INC(x) STATS_INC(x)
+#else
+#define IP_STATS_INC(x)
+#endif
+
+#if IPFRAG_STATS
+#define IPFRAG_STATS_INC(x) STATS_INC(x)
+#else
+#define IPFRAG_STATS_INC(x)
+#endif
+
+#if LINK_STATS
+#define LINK_STATS_INC(x) STATS_INC(x)
+#else
+#define LINK_STATS_INC(x)
+#endif
+
+/* Display of statistics */
+#if LWIP_STATS_DISPLAY
+void stats_display(void);
+#else
+#define stats_display()
+#endif
+
+#endif /* __LWIP_STATS_H__ */
+
+
+
+
--- /dev/null
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef __LWIP_SYS_H__
+#define __LWIP_SYS_H__
+
+#include "arch/cc.h"
+
+#include "lwip/opt.h"
+
+
+#if NO_SYS
+
+/* For a totally minimal and standalone system, we provide null
+ definitions of the sys_ functions. */
+typedef u8_t sys_sem_t;
+typedef u8_t sys_mbox_t;
+struct sys_timeout {u8_t dummy;};
+
+#define sys_init()
+#define sys_timeout(m,h,a)
+#define sys_untimeout(m,a)
+#define sys_sem_new(c) c
+#define sys_sem_signal(s)
+#define sys_sem_wait(s)
+#define sys_sem_free(s)
+#define sys_mbox_new() 0
+#define sys_mbox_fetch(m,d)
+#define sys_mbox_post(m,d)
+#define sys_mbox_free(m)
+
+#define sys_thread_new(t,a,p)
+
+#else /* NO_SYS */
+
+#include "arch/sys_arch.h"
+
+/** Return code for timeouts from sys_arch_mbox_fetch and sys_arch_sem_wait */
+#define SYS_ARCH_TIMEOUT 0xffffffff
+
+typedef void (* sys_timeout_handler)(void *arg);
+
+struct sys_timeout {
+ struct sys_timeout *next;
+ u32_t time;
+ sys_timeout_handler h;
+ void *arg;
+};
+
+struct sys_timeouts {
+ struct sys_timeout *next;
+};
+
+/* sys_init() must be called before anthing else. */
+void sys_init(void);
+
+/*
+ * sys_timeout():
+ *
+ * Schedule a timeout a specified amount of milliseconds in the
+ * future. When the timeout occurs, the specified timeout handler will
+ * be called. The handler will be passed the "arg" argument when
+ * called.
+ *
+ */
+void sys_timeout(u32_t msecs, sys_timeout_handler h, void *arg);
+void sys_untimeout(sys_timeout_handler h, void *arg);
+struct sys_timeouts *sys_arch_timeouts(void);
+
+/* Semaphore functions. */
+sys_sem_t sys_sem_new(u8_t count);
+void sys_sem_signal(sys_sem_t sem);
+u32_t sys_arch_sem_wait(sys_sem_t sem, u32_t timeout);
+void sys_sem_free(sys_sem_t sem);
+void sys_sem_wait(sys_sem_t sem);
+int sys_sem_wait_timeout(sys_sem_t sem, u32_t timeout);
+
+/* Time functions. */
+#ifndef sys_msleep
+void sys_msleep(u32_t ms); /* only has a (close to) 1 jiffy resolution. */
+#endif
+#ifndef sys_jiffies
+u32_t sys_jiffies(void); /* since power up. */
+#endif
+
+/* Mailbox functions. */
+sys_mbox_t sys_mbox_new(void);
+void sys_mbox_post(sys_mbox_t mbox, void *msg);
+u32_t sys_arch_mbox_fetch(sys_mbox_t mbox, void **msg, u32_t timeout);
+void sys_mbox_free(sys_mbox_t mbox);
+void sys_mbox_fetch(sys_mbox_t mbox, void **msg);
+
+
+/* Thread functions. */
+sys_thread_t sys_thread_new(void (* thread)(void *arg), void *arg, int prio);
+
+/* The following functions are used only in Unix code, and
+ can be omitted when porting the stack. */
+/* Returns the current time in microseconds. */
+unsigned long sys_now(void);
+
+#endif /* NO_SYS */
+
+/* Critical Region Protection */
+/* These functions must be implemented in the sys_arch.c file.
+ In some implementations they can provide a more light-weight protection
+ mechanism than using semaphores. Otherwise semaphores can be used for
+ implementation */
+#ifndef SYS_ARCH_PROTECT
+/** SYS_LIGHTWEIGHT_PROT
+ * define SYS_LIGHTWEIGHT_PROT in lwipopts.h if you want inter-task protection
+ * for certain critical regions during buffer allocation, deallocation and memory
+ * allocation and deallocation.
+ */
+#if SYS_LIGHTWEIGHT_PROT
+
+/** SYS_ARCH_DECL_PROTECT
+ * declare a protection variable. This macro will default to defining a variable of
+ * type sys_prot_t. If a particular port needs a different implementation, then
+ * this macro may be defined in sys_arch.h.
+ */
+#define SYS_ARCH_DECL_PROTECT(lev) sys_prot_t lev
+/** SYS_ARCH_PROTECT
+ * Perform a "fast" protect. This could be implemented by
+ * disabling interrupts for an embedded system or by using a semaphore or
+ * mutex. The implementation should allow calling SYS_ARCH_PROTECT when
+ * already protected. The old protection level is returned in the variable
+ * "lev". This macro will default to calling the sys_arch_protect() function
+ * which should be implemented in sys_arch.c. If a particular port needs a
+ * different implementation, then this macro may be defined in sys_arch.h
+ */
+#define SYS_ARCH_PROTECT(lev) lev = sys_arch_protect()
+/** SYS_ARCH_UNPROTECT
+ * Perform a "fast" set of the protection level to "lev". This could be
+ * implemented by setting the interrupt level to "lev" within the MACRO or by
+ * using a semaphore or mutex. This macro will default to calling the
+ * sys_arch_unprotect() function which should be implemented in
+ * sys_arch.c. If a particular port needs a different implementation, then
+ * this macro may be defined in sys_arch.h
+ */
+#define SYS_ARCH_UNPROTECT(lev) sys_arch_unprotect(lev)
+sys_prot_t sys_arch_protect(void);
+void sys_arch_unprotect(sys_prot_t pval);
+
+#else
+
+#define SYS_ARCH_DECL_PROTECT(lev)
+#define SYS_ARCH_PROTECT(lev)
+#define SYS_ARCH_UNPROTECT(lev)
+
+#endif /* SYS_LIGHTWEIGHT_PROT */
+
+#endif /* SYS_ARCH_PROTECT */
+
+#endif /* __LWIP_SYS_H__ */
--- /dev/null
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef __LWIP_TCP_H__
+#define __LWIP_TCP_H__
+
+#include "lwip/sys.h"
+#include "lwip/mem.h"
+
+#include "lwip/pbuf.h"
+#include "lwip/opt.h"
+#include "lwip/ip.h"
+#include "lwip/icmp.h"
+
+#include "lwip/err.h"
+
+struct tcp_pcb;
+
+/* Functions for interfacing with TCP: */
+
+/* Lower layer interface to TCP: */
+void tcp_init (void); /* Must be called first to
+ initialize TCP. */
+void tcp_tmr (void); /* Must be called every
+ TCP_TMR_INTERVAL
+ ms. (Typically 250 ms). */
+/* Application program's interface: */
+struct tcp_pcb * tcp_new (void);
+struct tcp_pcb * tcp_alloc (u8_t prio);
+
+void tcp_arg (struct tcp_pcb *pcb, void *arg);
+void tcp_accept (struct tcp_pcb *pcb,
+ err_t (* accept)(void *arg, struct tcp_pcb *newpcb,
+ err_t err));
+void tcp_recv (struct tcp_pcb *pcb,
+ err_t (* recv)(void *arg, struct tcp_pcb *tpcb,
+ struct pbuf *p, err_t err));
+void tcp_sent (struct tcp_pcb *pcb,
+ err_t (* sent)(void *arg, struct tcp_pcb *tpcb,
+ u16_t len));
+void tcp_poll (struct tcp_pcb *pcb,
+ err_t (* poll)(void *arg, struct tcp_pcb *tpcb),
+ u8_t interval);
+void tcp_err (struct tcp_pcb *pcb,
+ void (* err)(void *arg, err_t err));
+
+#define tcp_mss(pcb) ((pcb)->mss)
+#define tcp_sndbuf(pcb) ((pcb)->snd_buf)
+
+void tcp_recved (struct tcp_pcb *pcb, u16_t len);
+err_t tcp_bind (struct tcp_pcb *pcb, struct ip_addr *ipaddr,
+ u16_t port);
+err_t tcp_connect (struct tcp_pcb *pcb, struct ip_addr *ipaddr,
+ u16_t port, err_t (* connected)(void *arg,
+ struct tcp_pcb *tpcb,
+ err_t err));
+struct tcp_pcb * tcp_listen (struct tcp_pcb *pcb);
+void tcp_abort (struct tcp_pcb *pcb);
+err_t tcp_close (struct tcp_pcb *pcb);
+err_t tcp_write (struct tcp_pcb *pcb, const void *dataptr, u16_t len,
+ u8_t copy);
+
+void tcp_setprio (struct tcp_pcb *pcb, u8_t prio);
+
+#define TCP_PRIO_MIN 1
+#define TCP_PRIO_NORMAL 64
+#define TCP_PRIO_MAX 127
+
+/* It is also possible to call these two functions at the right
+ intervals (instead of calling tcp_tmr()). */
+void tcp_slowtmr (void);
+void tcp_fasttmr (void);
+
+
+/* Only used by IP to pass a TCP segment to TCP: */
+void tcp_input (struct pbuf *p, struct netif *inp);
+/* Used within the TCP code only: */
+err_t tcp_output (struct tcp_pcb *pcb);
+void tcp_rexmit (struct tcp_pcb *pcb);
+void tcp_rexmit_rto (struct tcp_pcb *pcb);
+
+
+
+#define TCP_SEQ_LT(a,b) ((s32_t)((a)-(b)) < 0)
+#define TCP_SEQ_LEQ(a,b) ((s32_t)((a)-(b)) <= 0)
+#define TCP_SEQ_GT(a,b) ((s32_t)((a)-(b)) > 0)
+#define TCP_SEQ_GEQ(a,b) ((s32_t)((a)-(b)) >= 0)
+/* is b<=a<=c? */
+#if 0 /* see bug #10548 */
+#define TCP_SEQ_BETWEEN(a,b,c) ((c)-(b) >= (a)-(b))
+#endif
+#define TCP_SEQ_BETWEEN(a,b,c) (TCP_SEQ_GEQ(a,b) && TCP_SEQ_LEQ(a,c))
+#define TCP_FIN 0x01U
+#define TCP_SYN 0x02U
+#define TCP_RST 0x04U
+#define TCP_PSH 0x08U
+#define TCP_ACK 0x10U
+#define TCP_URG 0x20U
+#define TCP_ECE 0x40U
+#define TCP_CWR 0x80U
+
+#define TCP_FLAGS 0x3fU
+
+/* Length of the TCP header, excluding options. */
+#define TCP_HLEN 20
+
+#ifndef TCP_TMR_INTERVAL
+#define TCP_TMR_INTERVAL 250 /* The TCP timer interval in
+ milliseconds. */
+#endif /* TCP_TMR_INTERVAL */
+
+#ifndef TCP_FAST_INTERVAL
+#define TCP_FAST_INTERVAL TCP_TMR_INTERVAL /* the fine grained timeout in
+ milliseconds */
+#endif /* TCP_FAST_INTERVAL */
+
+#ifndef TCP_SLOW_INTERVAL
+#define TCP_SLOW_INTERVAL (2*TCP_TMR_INTERVAL) /* the coarse grained timeout in
+ milliseconds */
+#endif /* TCP_SLOW_INTERVAL */
+
+#define TCP_FIN_WAIT_TIMEOUT 20000 /* milliseconds */
+#define TCP_SYN_RCVD_TIMEOUT 20000 /* milliseconds */
+
+#define TCP_OOSEQ_TIMEOUT 6 /* x RTO */
+
+#define TCP_MSL 60000 /* The maximum segment lifetime in microseconds */
+
+/*
+ * User-settable options (used with setsockopt).
+ */
+#define TCP_NODELAY 0x01 /* don't delay send to coalesce packets */
+#define TCP_KEEPALIVE 0x02 /* send KEEPALIVE probes when idle for pcb->keepalive miliseconds */
+
+/* Keepalive values */
+#define TCP_KEEPDEFAULT 7200000 /* KEEPALIVE timer in miliseconds */
+#define TCP_KEEPINTVL 75000 /* Time between KEEPALIVE probes in miliseconds */
+#define TCP_KEEPCNT 9 /* Counter for KEEPALIVE probes */
+#define TCP_MAXIDLE TCP_KEEPCNT * TCP_KEEPINTVL /* Maximum KEEPALIVE probe time */
+
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct tcp_hdr {
+ PACK_STRUCT_FIELD(u16_t src);
+ PACK_STRUCT_FIELD(u16_t dest);
+ PACK_STRUCT_FIELD(u32_t seqno);
+ PACK_STRUCT_FIELD(u32_t ackno);
+ PACK_STRUCT_FIELD(u16_t _hdrlen_rsvd_flags);
+ PACK_STRUCT_FIELD(u16_t wnd);
+ PACK_STRUCT_FIELD(u16_t chksum);
+ PACK_STRUCT_FIELD(u16_t urgp);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/epstruct.h"
+#endif
+
+#define TCPH_OFFSET(phdr) (ntohs((phdr)->_hdrlen_rsvd_flags) >> 8)
+#define TCPH_HDRLEN(phdr) (ntohs((phdr)->_hdrlen_rsvd_flags) >> 12)
+#define TCPH_FLAGS(phdr) (ntohs((phdr)->_hdrlen_rsvd_flags) & TCP_FLAGS)
+
+#define TCPH_OFFSET_SET(phdr, offset) (phdr)->_hdrlen_rsvd_flags = htons(((offset) << 8) | TCPH_FLAGS(phdr))
+#define TCPH_HDRLEN_SET(phdr, len) (phdr)->_hdrlen_rsvd_flags = htons(((len) << 12) | TCPH_FLAGS(phdr))
+#define TCPH_FLAGS_SET(phdr, flags) (phdr)->_hdrlen_rsvd_flags = htons((ntohs((phdr)->_hdrlen_rsvd_flags) & ~TCP_FLAGS) | (flags))
+#define TCPH_SET_FLAG(phdr, flags ) (phdr)->_hdrlen_rsvd_flags = htons(ntohs((phdr)->_hdrlen_rsvd_flags) | (flags))
+#define TCPH_UNSET_FLAG(phdr, flags) (phdr)->_hdrlen_rsvd_flags = htons(ntohs((phdr)->_hdrlen_rsvd_flags) | (TCPH_FLAGS(phdr) & ~(flags)) )
+
+#define TCP_TCPLEN(seg) ((seg)->len + ((TCPH_FLAGS((seg)->tcphdr) & TCP_FIN || \
+ TCPH_FLAGS((seg)->tcphdr) & TCP_SYN)? 1: 0))
+
+enum tcp_state {
+ CLOSED = 0,
+ LISTEN = 1,
+ SYN_SENT = 2,
+ SYN_RCVD = 3,
+ ESTABLISHED = 4,
+ FIN_WAIT_1 = 5,
+ FIN_WAIT_2 = 6,
+ CLOSE_WAIT = 7,
+ CLOSING = 8,
+ LAST_ACK = 9,
+ TIME_WAIT = 10
+};
+
+/* the TCP protocol control block */
+struct tcp_pcb {
+/** common PCB members */
+ IP_PCB;
+/** protocol specific PCB members */
+ struct tcp_pcb *next; /* for the linked list */
+ enum tcp_state state; /* TCP state */
+ u8_t prio;
+ void *callback_arg;
+
+ u16_t local_port;
+ u16_t remote_port;
+
+ u8_t flags;
+#define TF_ACK_DELAY (u8_t)0x01U /* Delayed ACK. */
+#define TF_ACK_NOW (u8_t)0x02U /* Immediate ACK. */
+#define TF_INFR (u8_t)0x04U /* In fast recovery. */
+#define TF_RESET (u8_t)0x08U /* Connection was reset. */
+#define TF_CLOSED (u8_t)0x10U /* Connection was sucessfully closed. */
+#define TF_GOT_FIN (u8_t)0x20U /* Connection was closed by the remote end. */
+#define TF_NODELAY (u8_t)0x40U /* Disable Nagle algorithm */
+
+ /* receiver variables */
+ u32_t rcv_nxt; /* next seqno expected */
+ u16_t rcv_wnd; /* receiver window */
+
+ /* Timers */
+ u32_t tmr;
+ u8_t polltmr, pollinterval;
+
+ /* Retransmission timer. */
+ u16_t rtime;
+
+ u16_t mss; /* maximum segment size */
+
+ /* RTT (round trip time) estimation variables */
+ u32_t rttest; /* RTT estimate in 500ms ticks */
+ u32_t rtseq; /* sequence number being timed */
+ s16_t sa, sv; /* @todo document this */
+
+ u16_t rto; /* retransmission time-out */
+ u8_t nrtx; /* number of retransmissions */
+
+ /* fast retransmit/recovery */
+ u32_t lastack; /* Highest acknowledged seqno. */
+ u8_t dupacks;
+
+ /* congestion avoidance/control variables */
+ u16_t cwnd;
+ u16_t ssthresh;
+
+ /* sender variables */
+ u32_t snd_nxt, /* next seqno to be sent */
+ snd_max, /* Highest seqno sent. */
+ snd_wnd, /* sender window */
+ snd_wl1, snd_wl2, /* Sequence and acknowledgement numbers of last
+ window update. */
+ snd_lbb; /* Sequence number of next byte to be buffered. */
+
+ u16_t acked;
+
+ u16_t snd_buf; /* Available buffer space for sending (in bytes). */
+ u8_t snd_queuelen; /* Available buffer space for sending (in tcp_segs). */
+
+
+ /* These are ordered by sequence number: */
+ struct tcp_seg *unsent; /* Unsent (queued) segments. */
+ struct tcp_seg *unacked; /* Sent but unacknowledged segments. */
+#if TCP_QUEUE_OOSEQ
+ struct tcp_seg *ooseq; /* Received out of sequence segments. */
+#endif /* TCP_QUEUE_OOSEQ */
+
+#if LWIP_CALLBACK_API
+ /* Function to be called when more send buffer space is available. */
+ err_t (* sent)(void *arg, struct tcp_pcb *pcb, u16_t space);
+
+ /* Function to be called when (in-sequence) data has arrived. */
+ err_t (* recv)(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err);
+
+ /* Function to be called when a connection has been set up. */
+ err_t (* connected)(void *arg, struct tcp_pcb *pcb, err_t err);
+
+ /* Function to call when a listener has been connected. */
+ err_t (* accept)(void *arg, struct tcp_pcb *newpcb, err_t err);
+
+ /* Function which is called periodically. */
+ err_t (* poll)(void *arg, struct tcp_pcb *pcb);
+
+ /* Function to be called whenever a fatal error occurs. */
+ void (* errf)(void *arg, err_t err);
+#endif /* LWIP_CALLBACK_API */
+
+ /* idle time before KEEPALIVE is sent */
+ u32_t keepalive;
+
+ /* KEEPALIVE counter */
+ u8_t keep_cnt;
+};
+
+struct tcp_pcb_listen {
+/* Common members of all PCB types */
+ IP_PCB;
+
+/* Protocol specific PCB members */
+ struct tcp_pcb_listen *next; /* for the linked list */
+
+ /* Even if state is obviously LISTEN this is here for
+ * field compatibility with tpc_pcb to which it is cast sometimes
+ * Until a cleaner solution emerges this is here.FIXME
+ */
+ enum tcp_state state; /* TCP state */
+
+ u8_t prio;
+ void *callback_arg;
+
+ u16_t local_port;
+
+#if LWIP_CALLBACK_API
+ /* Function to call when a listener has been connected. */
+ err_t (* accept)(void *arg, struct tcp_pcb *newpcb, err_t err);
+#endif /* LWIP_CALLBACK_API */
+};
+
+#if LWIP_EVENT_API
+
+enum lwip_event {
+ LWIP_EVENT_ACCEPT,
+ LWIP_EVENT_SENT,
+ LWIP_EVENT_RECV,
+ LWIP_EVENT_CONNECTED,
+ LWIP_EVENT_POLL,
+ LWIP_EVENT_ERR
+};
+
+err_t lwip_tcp_event(void *arg, struct tcp_pcb *pcb,
+ enum lwip_event,
+ struct pbuf *p,
+ u16_t size,
+ err_t err);
+
+#define TCP_EVENT_ACCEPT(pcb,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
+ LWIP_EVENT_ACCEPT, NULL, 0, err)
+#define TCP_EVENT_SENT(pcb,space,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
+ LWIP_EVENT_SENT, NULL, space, ERR_OK)
+#define TCP_EVENT_RECV(pcb,p,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
+ LWIP_EVENT_RECV, (p), 0, (err))
+#define TCP_EVENT_CONNECTED(pcb,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
+ LWIP_EVENT_CONNECTED, NULL, 0, (err))
+#define TCP_EVENT_POLL(pcb,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
+ LWIP_EVENT_POLL, NULL, 0, ERR_OK)
+#define TCP_EVENT_ERR(errf,arg,err) lwip_tcp_event((arg), NULL, \
+ LWIP_EVENT_ERR, NULL, 0, (err))
+#else /* LWIP_EVENT_API */
+#define TCP_EVENT_ACCEPT(pcb,err,ret) \
+ if((pcb)->accept != NULL) \
+ (ret = (pcb)->accept((pcb)->callback_arg,(pcb),(err)))
+#define TCP_EVENT_SENT(pcb,space,ret) \
+ if((pcb)->sent != NULL) \
+ (ret = (pcb)->sent((pcb)->callback_arg,(pcb),(space)))
+#define TCP_EVENT_RECV(pcb,p,err,ret) \
+ if((pcb)->recv != NULL) \
+ { ret = (pcb)->recv((pcb)->callback_arg,(pcb),(p),(err)); } else { \
+ if (p) pbuf_free(p); }
+#define TCP_EVENT_CONNECTED(pcb,err,ret) \
+ if((pcb)->connected != NULL) \
+ (ret = (pcb)->connected((pcb)->callback_arg,(pcb),(err)))
+#define TCP_EVENT_POLL(pcb,ret) \
+ if((pcb)->poll != NULL) \
+ (ret = (pcb)->poll((pcb)->callback_arg,(pcb)))
+#define TCP_EVENT_ERR(errf,arg,err) \
+ if((errf) != NULL) \
+ (errf)((arg),(err))
+#endif /* LWIP_EVENT_API */
+
+/* This structure represents a TCP segment on the unsent and unacked queues */
+struct tcp_seg {
+ struct tcp_seg *next; /* used when putting segements on a queue */
+ struct pbuf *p; /* buffer containing data + TCP header */
+ void *dataptr; /* pointer to the TCP data in the pbuf */
+ u16_t len; /* the TCP length of this segment */
+ struct tcp_hdr *tcphdr; /* the TCP header */
+};
+
+/* Internal functions and global variables: */
+struct tcp_pcb *tcp_pcb_copy(struct tcp_pcb *pcb);
+void tcp_pcb_purge(struct tcp_pcb *pcb);
+void tcp_pcb_remove(struct tcp_pcb **pcblist, struct tcp_pcb *pcb);
+
+u8_t tcp_segs_free(struct tcp_seg *seg);
+u8_t tcp_seg_free(struct tcp_seg *seg);
+struct tcp_seg *tcp_seg_copy(struct tcp_seg *seg);
+
+#define tcp_ack(pcb) if((pcb)->flags & TF_ACK_DELAY) { \
+ (pcb)->flags &= ~TF_ACK_DELAY; \
+ (pcb)->flags |= TF_ACK_NOW; \
+ tcp_output(pcb); \
+ } else { \
+ (pcb)->flags |= TF_ACK_DELAY; \
+ }
+
+#define tcp_ack_now(pcb) (pcb)->flags |= TF_ACK_NOW; \
+ tcp_output(pcb)
+
+err_t tcp_send_ctrl(struct tcp_pcb *pcb, u8_t flags);
+err_t tcp_enqueue(struct tcp_pcb *pcb, void *dataptr, u16_t len,
+ u8_t flags, u8_t copy,
+ u8_t *optdata, u8_t optlen);
+
+void tcp_rexmit_seg(struct tcp_pcb *pcb, struct tcp_seg *seg);
+
+void tcp_rst(u32_t seqno, u32_t ackno,
+ struct ip_addr *local_ip, struct ip_addr *remote_ip,
+ u16_t local_port, u16_t remote_port);
+
+u32_t tcp_next_iss(void);
+
+void tcp_keepalive(struct tcp_pcb *pcb);
+
+extern struct tcp_pcb *tcp_input_pcb;
+extern u32_t tcp_ticks;
+
+#if TCP_DEBUG || TCP_INPUT_DEBUG || TCP_OUTPUT_DEBUG
+void tcp_debug_print(struct tcp_hdr *tcphdr);
+void tcp_debug_print_flags(u8_t flags);
+void tcp_debug_print_state(enum tcp_state s);
+void tcp_debug_print_pcbs(void);
+int tcp_pcbs_sane(void);
+#else
+# define tcp_debug_print(tcphdr)
+# define tcp_debug_print_flags(flags)
+# define tcp_debug_print_state(s)
+# define tcp_debug_print_pcbs()
+# define tcp_pcbs_sane() 1
+#endif /* TCP_DEBUG */
+
+#if NO_SYS
+#define tcp_timer_needed()
+#else
+void tcp_timer_needed(void);
+#endif
+
+/* The TCP PCB lists. */
+union tcp_listen_pcbs_t { /* List of all TCP PCBs in LISTEN state. */
+ struct tcp_pcb_listen *listen_pcbs;
+ struct tcp_pcb *pcbs;
+};
+extern union tcp_listen_pcbs_t tcp_listen_pcbs;
+extern struct tcp_pcb *tcp_active_pcbs; /* List of all TCP PCBs that are in a
+ state in which they accept or send
+ data. */
+extern struct tcp_pcb *tcp_tw_pcbs; /* List of all TCP PCBs in TIME-WAIT. */
+
+extern struct tcp_pcb *tcp_tmp_pcb; /* Only used for temporary storage. */
+
+/* Axioms about the above lists:
+ 1) Every TCP PCB that is not CLOSED is in one of the lists.
+ 2) A PCB is only in one of the lists.
+ 3) All PCBs in the tcp_listen_pcbs list is in LISTEN state.
+ 4) All PCBs in the tcp_tw_pcbs list is in TIME-WAIT state.
+*/
+
+/* Define two macros, TCP_REG and TCP_RMV that registers a TCP PCB
+ with a PCB list or removes a PCB from a list, respectively. */
+#if 0
+#define TCP_REG(pcbs, npcb) do {\
+ LWIP_DEBUGF(TCP_DEBUG, ("TCP_REG %p local port %d\n", npcb, npcb->local_port)); \
+ for(tcp_tmp_pcb = *pcbs; \
+ tcp_tmp_pcb != NULL; \
+ tcp_tmp_pcb = tcp_tmp_pcb->next) { \
+ LWIP_ASSERT("TCP_REG: already registered\n", tcp_tmp_pcb != npcb); \
+ } \
+ LWIP_ASSERT("TCP_REG: pcb->state != CLOSED", npcb->state != CLOSED); \
+ npcb->next = *pcbs; \
+ LWIP_ASSERT("TCP_REG: npcb->next != npcb", npcb->next != npcb); \
+ *(pcbs) = npcb; \
+ LWIP_ASSERT("TCP_RMV: tcp_pcbs sane", tcp_pcbs_sane()); \
+ tcp_timer_needed(); \
+ } while(0)
+#define TCP_RMV(pcbs, npcb) do { \
+ LWIP_ASSERT("TCP_RMV: pcbs != NULL", *pcbs != NULL); \
+ LWIP_DEBUGF(TCP_DEBUG, ("TCP_RMV: removing %p from %p\n", npcb, *pcbs)); \
+ if(*pcbs == npcb) { \
+ *pcbs = (*pcbs)->next; \
+ } else for(tcp_tmp_pcb = *pcbs; tcp_tmp_pcb != NULL; tcp_tmp_pcb = tcp_tmp_pcb->next) { \
+ if(tcp_tmp_pcb->next != NULL && tcp_tmp_pcb->next == npcb) { \
+ tcp_tmp_pcb->next = npcb->next; \
+ break; \
+ } \
+ } \
+ npcb->next = NULL; \
+ LWIP_ASSERT("TCP_RMV: tcp_pcbs sane", tcp_pcbs_sane()); \
+ LWIP_DEBUGF(TCP_DEBUG, ("TCP_RMV: removed %p from %p\n", npcb, *pcbs)); \
+ } while(0)
+
+#else /* LWIP_DEBUG */
+#define TCP_REG(pcbs, npcb) do { \
+ npcb->next = *pcbs; \
+ *(pcbs) = npcb; \
+ tcp_timer_needed(); \
+ } while(0)
+#define TCP_RMV(pcbs, npcb) do { \
+ if(*(pcbs) == npcb) { \
+ (*(pcbs)) = (*pcbs)->next; \
+ } else for(tcp_tmp_pcb = *pcbs; tcp_tmp_pcb != NULL; tcp_tmp_pcb = tcp_tmp_pcb->next) { \
+ if(tcp_tmp_pcb->next != NULL && tcp_tmp_pcb->next == npcb) { \
+ tcp_tmp_pcb->next = npcb->next; \
+ break; \
+ } \
+ } \
+ npcb->next = NULL; \
+ } while(0)
+#endif /* LWIP_DEBUG */
+#endif /* __LWIP_TCP_H__ */
+
+
+
--- /dev/null
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef __LWIP_TCPIP_H__
+#define __LWIP_TCPIP_H__
+
+#include "lwip/api_msg.h"
+#include "lwip/pbuf.h"
+
+void tcpip_init(void (* tcpip_init_done)(void *), void *arg);
+void tcpip_apimsg(struct api_msg *apimsg);
+err_t tcpip_input(struct pbuf *p, struct netif *inp);
+err_t tcpip_callback(void (*f)(void *ctx), void *ctx);
+
+void tcpip_tcp_timer_needed(void);
+
+enum tcpip_msg_type {
+ TCPIP_MSG_API,
+ TCPIP_MSG_INPUT,
+ TCPIP_MSG_CALLBACK
+};
+
+struct tcpip_msg {
+ enum tcpip_msg_type type;
+ sys_sem_t *sem;
+ union {
+ struct api_msg *apimsg;
+ struct {
+ struct pbuf *p;
+ struct netif *netif;
+ } inp;
+ struct {
+ void (*f)(void *ctx);
+ void *ctx;
+ } cb;
+ } msg;
+};
+
+
+#endif /* __LWIP_TCPIP_H__ */
--- /dev/null
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef __LWIP_UDP_H__
+#define __LWIP_UDP_H__
+
+#include "lwip/arch.h"
+
+#include "lwip/pbuf.h"
+#include "lwip/inet.h"
+#include "lwip/ip.h"
+
+#define UDP_HLEN 8
+
+struct udp_hdr {
+ PACK_STRUCT_FIELD(u16_t src);
+ PACK_STRUCT_FIELD(u16_t dest); /* src/dest UDP ports */
+ PACK_STRUCT_FIELD(u16_t len);
+ PACK_STRUCT_FIELD(u16_t chksum);
+} PACK_STRUCT_STRUCT;
+
+#define UDP_FLAGS_NOCHKSUM 0x01U
+#define UDP_FLAGS_UDPLITE 0x02U
+#define UDP_FLAGS_CONNECTED 0x04U
+
+struct udp_pcb {
+/* Common members of all PCB types */
+ IP_PCB;
+
+/* Protocol specific PCB members */
+
+ struct udp_pcb *next;
+
+ u8_t flags;
+ u16_t local_port, remote_port;
+
+ u16_t chksum_len;
+
+ void (* recv)(void *arg, struct udp_pcb *pcb, struct pbuf *p,
+ struct ip_addr *addr, u16_t port);
+ void *recv_arg;
+};
+
+/* The following functions is the application layer interface to the
+ UDP code. */
+struct udp_pcb * udp_new (void);
+void udp_remove (struct udp_pcb *pcb);
+err_t udp_bind (struct udp_pcb *pcb, struct ip_addr *ipaddr,
+ u16_t port);
+err_t udp_connect (struct udp_pcb *pcb, struct ip_addr *ipaddr,
+ u16_t port);
+void udp_disconnect (struct udp_pcb *pcb);
+void udp_recv (struct udp_pcb *pcb,
+ void (* recv)(void *arg, struct udp_pcb *upcb,
+ struct pbuf *p,
+ struct ip_addr *addr,
+ u16_t port),
+ void *recv_arg);
+err_t udp_sendto (struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *dst_ip, u16_t dst_port);
+err_t udp_send (struct udp_pcb *pcb, struct pbuf *p);
+
+#define udp_flags(pcb) ((pcb)->flags)
+#define udp_setflags(pcb, f) ((pcb)->flags = (f))
+
+/* The following functions are the lower layer interface to UDP. */
+void udp_input (struct pbuf *p, struct netif *inp);
+void udp_init (void);
+
+#if UDP_DEBUG
+int udp_debug_print(struct udp_hdr *udphdr);
+#else
+#define udp_debug_print(udphdr)
+#endif
+#endif /* __LWIP_UDP_H__ */
+
+
--- /dev/null
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * Copyright (c) 2003-2004 Leon Woestenberg <leon.woestenberg@axon.tv>
+ * Copyright (c) 2003-2004 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+#ifndef __NETIF_ETHARP_H__
+#define __NETIF_ETHARP_H__
+
+#ifndef ETH_PAD_SIZE
+#define ETH_PAD_SIZE 0
+#endif
+
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/ip.h"
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct eth_addr {
+ PACK_STRUCT_FIELD(u8_t addr[6]);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/epstruct.h"
+#endif
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct eth_hdr {
+#if ETH_PAD_SIZE
+ PACK_STRUCT_FIELD(u8_t padding[ETH_PAD_SIZE]);
+#endif
+ PACK_STRUCT_FIELD(struct eth_addr dest);
+ PACK_STRUCT_FIELD(struct eth_addr src);
+ PACK_STRUCT_FIELD(u16_t type);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/epstruct.h"
+#endif
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+/** the ARP message */
+struct etharp_hdr {
+ PACK_STRUCT_FIELD(struct eth_hdr ethhdr);
+ PACK_STRUCT_FIELD(u16_t hwtype);
+ PACK_STRUCT_FIELD(u16_t proto);
+ PACK_STRUCT_FIELD(u16_t _hwlen_protolen);
+ PACK_STRUCT_FIELD(u16_t opcode);
+ PACK_STRUCT_FIELD(struct eth_addr shwaddr);
+ PACK_STRUCT_FIELD(struct ip_addr2 sipaddr);
+ PACK_STRUCT_FIELD(struct eth_addr dhwaddr);
+ PACK_STRUCT_FIELD(struct ip_addr2 dipaddr);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/epstruct.h"
+#endif
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ethip_hdr {
+ PACK_STRUCT_FIELD(struct eth_hdr eth);
+ PACK_STRUCT_FIELD(struct ip_hdr ip);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/epstruct.h"
+#endif
+
+/** 5 seconds period */
+#define ARP_TMR_INTERVAL 5000
+
+#define ETHTYPE_ARP 0x0806
+#define ETHTYPE_IP 0x0800
+
+void etharp_init(void);
+void etharp_tmr(void);
+void etharp_ip_input(struct netif *netif, struct pbuf *p);
+void etharp_arp_input(struct netif *netif, struct eth_addr *ethaddr,
+ struct pbuf *p);
+err_t etharp_output(struct netif *netif, struct ip_addr *ipaddr,
+ struct pbuf *q);
+err_t etharp_query(struct netif *netif, struct ip_addr *ipaddr, struct pbuf *q);
+err_t etharp_request(struct netif *netif, struct ip_addr *ipaddr);
+
+#endif /* __NETIF_ARP_H__ */
--- /dev/null
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef __NETIF_LOOPIF_H__
+#define __NETIF_LOOPIF_H__
+
+#include "lwip/netif.h"
+
+err_t loopif_init(struct netif *netif);
+
+#endif /* __NETIF_LOOPIF_H__ */
--- /dev/null
+/*
+ * Copyright (c) 2001, Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef __NETIF_SLIPIF_H__
+#define __NETIF_SLIPIF_H__
+
+#include "lwip/netif.h"
+
+err_t slipif_init(struct netif * netif);
+
+#endif
+
--- /dev/null
+This directory contains generic network interface device drivers that
+do not contain any hardware or architecture specific code. The files
+are:
+
+etharp.c
+ Implements the ARP (Address Resolution Protocol) over
+ Ethernet. The code in this file should be used together with
+ Ethernet device drivers. Note that this module has been
+ largely made Ethernet independent so you should be able to
+ adapt this for other link layers (such as Firewire).
+
+ethernetif.c
+ An example of how an Ethernet device driver could look. This
+ file can be used as a "skeleton" for developing new Ethernet
+ network device drivers. It uses the etharp.c ARP code.
+
+loopif.c
+ An example network interface that shows how a "loopback"
+ interface would work. This is not really intended for actual
+ use, but as a very basic example of how initialization and
+ output functions work.
+
+slipif.c
+ A generic implementation of the SLIP (Serial Line IP)
+ protocol. It requires a sio (serial I/O) module to work.
+
+ppp/ Point-to-Point Protocol stack
--- /dev/null
+/**\r
+ * @file\r
+ * Address Resolution Protocol module for IP over Ethernet\r
+ *\r
+ * Functionally, ARP is divided into two parts. The first maps an IP address\r
+ * to a physical address when sending a packet, and the second part answers\r
+ * requests from other machines for our physical address.\r
+ *\r
+ * This implementation complies with RFC 826 (Ethernet ARP). It supports\r
+ * Gratuitious ARP from RFC3220 (IP Mobility Support for IPv4) section 4.6\r
+ * if an interface calls etharp_query(our_netif, its_ip_addr, NULL) upon\r
+ * address change.\r
+ */\r
+\r
+/*\r
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.\r
+ * Copyright (c) 2003-2004 Leon Woestenberg <leon.woestenberg@axon.tv>\r
+ * Copyright (c) 2003-2004 Axon Digital Design B.V., The Netherlands.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. The name of the author may not be used to endorse or promote products\r
+ * derived from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT\r
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT\r
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING\r
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY\r
+ * OF SUCH DAMAGE.\r
+ *\r
+ * This file is part of the lwIP TCP/IP stack.\r
+ *\r
+ */\r
+\r
+#include "lwip/opt.h"\r
+#include "lwip/inet.h"\r
+#include "netif/etharp.h"\r
+#include "lwip/ip.h"\r
+#include "lwip/stats.h"\r
+\r
+/* ARP needs to inform DHCP of any ARP replies? */\r
+#if (LWIP_DHCP && DHCP_DOES_ARP_CHECK)\r
+# include "lwip/dhcp.h"\r
+#endif\r
+\r
+/** the time an ARP entry stays valid after its last update,\r
+ * (240 * 5) seconds = 20 minutes.\r
+ */\r
+#define ARP_MAXAGE 240\r
+/** the time an ARP entry stays pending after first request,\r
+ * (2 * 5) seconds = 10 seconds.\r
+ * \r
+ * @internal Keep this number at least 2, otherwise it might\r
+ * run out instantly if the timeout occurs directly after a request.\r
+ */\r
+#define ARP_MAXPENDING 2\r
+\r
+#define HWTYPE_ETHERNET 1\r
+\r
+/** ARP message types */\r
+#define ARP_REQUEST 1\r
+#define ARP_REPLY 2\r
+\r
+#define ARPH_HWLEN(hdr) (ntohs((hdr)->_hwlen_protolen) >> 8)\r
+#define ARPH_PROTOLEN(hdr) (ntohs((hdr)->_hwlen_protolen) & 0xff)\r
+\r
+#define ARPH_HWLEN_SET(hdr, len) (hdr)->_hwlen_protolen = htons(ARPH_PROTOLEN(hdr) | ((len) << 8))\r
+#define ARPH_PROTOLEN_SET(hdr, len) (hdr)->_hwlen_protolen = htons((len) | (ARPH_HWLEN(hdr) << 8))\r
+\r
+enum etharp_state {\r
+ ETHARP_STATE_EMPTY,\r
+ ETHARP_STATE_PENDING,\r
+ ETHARP_STATE_STABLE,\r
+ /** @internal transitional state used in etharp_tmr() for convenience*/\r
+ ETHARP_STATE_EXPIRED\r
+};\r
+\r
+struct etharp_entry {\r
+#if ARP_QUEUEING\r
+ /** \r
+ * Pointer to queue of pending outgoing packets on this ARP entry.\r
+ */\r
+ struct pbuf *p;\r
+#endif\r
+ struct ip_addr ipaddr;\r
+ struct eth_addr ethaddr;\r
+ enum etharp_state state;\r
+ u8_t ctime;\r
+};\r
+\r
+static const struct eth_addr ethbroadcast = {{0xff,0xff,0xff,0xff,0xff,0xff}};\r
+static struct etharp_entry arp_table[ARP_TABLE_SIZE];\r
+\r
+/**\r
+ * Try hard to create a new entry - we want the IP address to appear in\r
+ * the cache (even if this means removing an active entry or so). */\r
+#define ETHARP_TRY_HARD 1\r
+\r
+static s8_t find_entry(struct ip_addr *ipaddr, u8_t flags);\r
+static err_t update_arp_entry(struct netif *netif, struct ip_addr *ipaddr, struct eth_addr *ethaddr, u8_t flags);\r
+/**\r
+ * Initializes ARP module.\r
+ */\r
+void\r
+etharp_init(void)\r
+{\r
+ u8_t i;\r
+ /* clear ARP entries */\r
+ for(i = 0; i < ARP_TABLE_SIZE; ++i) {\r
+ arp_table[i].state = ETHARP_STATE_EMPTY;\r
+#if ARP_QUEUEING\r
+ arp_table[i].p = NULL;\r
+#endif\r
+ arp_table[i].ctime = 0;\r
+ }\r
+}\r
+\r
+/**\r
+ * Clears expired entries in the ARP table.\r
+ *\r
+ * This function should be called every ETHARP_TMR_INTERVAL microseconds (5 seconds),\r
+ * in order to expire entries in the ARP table.\r
+ */\r
+void\r
+etharp_tmr(void)\r
+{\r
+ u8_t i;\r
+\r
+ LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer\n"));\r
+ /* remove expired entries from the ARP table */\r
+ for (i = 0; i < ARP_TABLE_SIZE; ++i) {\r
+ arp_table[i].ctime++;\r
+ /* stable entry? */\r
+ if ((arp_table[i].state == ETHARP_STATE_STABLE) &&\r
+ /* entry has become old? */\r
+ (arp_table[i].ctime >= ARP_MAXAGE)) {\r
+ LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: expired stable entry %u.\n", i));\r
+ arp_table[i].state = ETHARP_STATE_EXPIRED;\r
+ /* pending entry? */\r
+ } else if (arp_table[i].state == ETHARP_STATE_PENDING) {\r
+ /* entry unresolved/pending for too long? */\r
+ if (arp_table[i].ctime >= ARP_MAXPENDING) {\r
+ LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: expired pending entry %u.\n", i));\r
+ arp_table[i].state = ETHARP_STATE_EXPIRED;\r
+#if ARP_QUEUEING\r
+ } else if (arp_table[i].p != NULL) {\r
+ /* resend an ARP query here */\r
+#endif\r
+ }\r
+ }\r
+ /* clean up entries that have just been expired */\r
+ if (arp_table[i].state == ETHARP_STATE_EXPIRED) {\r
+#if ARP_QUEUEING\r
+ /* and empty packet queue */\r
+ if (arp_table[i].p != NULL) {\r
+ /* remove all queued packets */\r
+ LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: freeing entry %u, packet queue %p.\n", i, (void *)(arp_table[i].p)));\r
+ pbuf_free(arp_table[i].p);\r
+ arp_table[i].p = NULL;\r
+ }\r
+#endif\r
+ /* recycle entry for re-use */ \r
+ arp_table[i].state = ETHARP_STATE_EMPTY;\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * Search the ARP table for a matching or new entry.\r
+ * \r
+ * If an IP address is given, return a pending or stable ARP entry that matches\r
+ * the address. If no match is found, create a new entry with this address set,\r
+ * but in state ETHARP_EMPTY. The caller must check and possibly change the\r
+ * state of the returned entry.\r
+ * \r
+ * If ipaddr is NULL, return a initialized new entry in state ETHARP_EMPTY.\r
+ * \r
+ * In all cases, attempt to create new entries from an empty entry. If no\r
+ * empty entries are available and ETHARP_TRY_HARD flag is set, recycle\r
+ * old entries. Heuristic choose the least important entry for recycling.\r
+ *\r
+ * @param ipaddr IP address to find in ARP cache, or to add if not found.\r
+ * @param flags\r
+ * - ETHARP_TRY_HARD: Try hard to create a entry by allowing recycling of\r
+ * active (stable or pending) entries.\r
+ * \r
+ * @return The ARP entry index that matched or is created, ERR_MEM if no\r
+ * entry is found or could be recycled.\r
+ */\r
+static s8_t find_entry(struct ip_addr *ipaddr, u8_t flags)\r
+{\r
+ s8_t old_pending = ARP_TABLE_SIZE, old_stable = ARP_TABLE_SIZE;\r
+ s8_t empty = ARP_TABLE_SIZE;\r
+ u8_t i = 0, age_pending = 0, age_stable = 0;\r
+#if ARP_QUEUEING\r
+ /* oldest entry with packets on queue */\r
+ s8_t old_queue = ARP_TABLE_SIZE;\r
+ /* its age */\r
+ u8_t age_queue = 0;\r
+#endif\r
+\r
+ /**\r
+ * a) do a search through the cache, remember candidates\r
+ * b) select candidate entry\r
+ * c) create new entry\r
+ */\r
+\r
+ /* a) in a single search sweep, do all of this\r
+ * 1) remember the first empty entry (if any)\r
+ * 2) remember the oldest stable entry (if any)\r
+ * 3) remember the oldest pending entry without queued packets (if any)\r
+ * 4) remember the oldest pending entry with queued packets (if any)\r
+ * 5) search for a matching IP entry, either pending or stable\r
+ * until 5 matches, or all entries are searched for.\r
+ */\r
+\r
+ for (i = 0; i < ARP_TABLE_SIZE; ++i) {\r
+ /* no empty entry found yet and now we do find one? */\r
+ if ((empty == ARP_TABLE_SIZE) && (arp_table[i].state == ETHARP_STATE_EMPTY)) {\r
+ LWIP_DEBUGF(ETHARP_DEBUG, ("find_entry: found empty entry %d\n", i));\r
+ /* remember first empty entry */\r
+ empty = i;\r
+ }\r
+ /* pending entry? */\r
+ else if (arp_table[i].state == ETHARP_STATE_PENDING) {\r
+ /* if given, does IP address match IP address in ARP entry? */\r
+ if (ipaddr && ip_addr_cmp(ipaddr, &arp_table[i].ipaddr)) {\r
+ LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: found matching pending entry %d\n", i));\r
+ /* found exact IP address match, simply bail out */\r
+ return i;\r
+#if ARP_QUEUEING\r
+ /* pending with queued packets? */\r
+ } else if (arp_table[i].p != NULL) {\r
+ if (arp_table[i].ctime >= age_queue) {\r
+ old_queue = i;\r
+ age_queue = arp_table[i].ctime;\r
+ }\r
+#endif\r
+ /* pending without queued packets? */\r
+ } else {\r
+ if (arp_table[i].ctime >= age_pending) {\r
+ old_pending = i;\r
+ age_pending = arp_table[i].ctime;\r
+ }\r
+ } \r
+ }\r
+ /* stable entry? */\r
+ else if (arp_table[i].state == ETHARP_STATE_STABLE) {\r
+ /* if given, does IP address match IP address in ARP entry? */\r
+ if (ipaddr && ip_addr_cmp(ipaddr, &arp_table[i].ipaddr)) {\r
+ LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: found matching stable entry %d\n", i));\r
+ /* found exact IP address match, simply bail out */\r
+ return i;\r
+ /* remember entry with oldest stable entry in oldest, its age in maxtime */\r
+ } else if (arp_table[i].ctime >= age_stable) {\r
+ old_stable = i;\r
+ age_stable = arp_table[i].ctime;\r
+ }\r
+ }\r
+ }\r
+ /* { we have no match } => try to create a new entry */\r
+ \r
+ /* no empty entry found and not allowed to recycle? */\r
+ if ((empty == ARP_TABLE_SIZE) && ((flags & ETHARP_TRY_HARD) == 0))\r
+ {\r
+ return (s8_t)ERR_MEM;\r
+ }\r
+ \r
+ /* b) choose the least destructive entry to recycle:\r
+ * 1) empty entry\r
+ * 2) oldest stable entry\r
+ * 3) oldest pending entry without queued packets\r
+ * 4) oldest pending entry without queued packets\r
+ * \r
+ * { ETHARP_TRY_HARD is set at this point }\r
+ */ \r
+\r
+ /* 1) empty entry available? */\r
+ if (empty < ARP_TABLE_SIZE) {\r
+ i = empty;\r
+ LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: selecting empty entry %d\n", i));\r
+ }\r
+ /* 2) found recyclable stable entry? */\r
+ else if (old_stable < ARP_TABLE_SIZE) {\r
+ /* recycle oldest stable*/\r
+ i = old_stable;\r
+ LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: selecting oldest stable entry %d\n", i));\r
+#if ARP_QUEUEING\r
+ /* no queued packets should exist on stable entries */\r
+ LWIP_ASSERT("arp_table[i].p == NULL", arp_table[i].p == NULL);\r
+#endif\r
+ /* 3) found recyclable pending entry without queued packets? */\r
+ } else if (old_pending < ARP_TABLE_SIZE) {\r
+ /* recycle oldest pending */\r
+ i = old_pending;\r
+ LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: selecting oldest pending entry %d (without queue)\n", i));\r
+#if ARP_QUEUEING\r
+ /* 4) found recyclable pending entry with queued packets? */\r
+ } else if (old_queue < ARP_TABLE_SIZE) {\r
+ /* recycle oldest pending */\r
+ i = old_queue;\r
+ LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: selecting oldest pending entry %d, freeing packet queue %p\n", i, (void *)(arp_table[i].p)));\r
+ pbuf_free(arp_table[i].p);\r
+ arp_table[i].p = NULL;\r
+#endif\r
+ /* no empty or recyclable entries found */\r
+ } else {\r
+ return (s8_t)ERR_MEM;\r
+ }\r
+\r
+ /* { empty or recyclable entry found } */\r
+ LWIP_ASSERT("i < ARP_TABLE_SIZE", i < ARP_TABLE_SIZE);\r
+\r
+ /* recycle entry (no-op for an already empty entry) */\r
+ arp_table[i].state = ETHARP_STATE_EMPTY;\r
+\r
+ /* IP address given? */\r
+ if (ipaddr != NULL) {\r
+ /* set IP address */\r
+ ip_addr_set(&arp_table[i].ipaddr, ipaddr);\r
+ }\r
+ arp_table[i].ctime = 0;\r
+ return (err_t)i;\r
+}\r
+\r
+/**\r
+ * Update (or insert) a IP/MAC address pair in the ARP cache.\r
+ *\r
+ * If a pending entry is resolved, any queued packets will be sent\r
+ * at this point.\r
+ * \r
+ * @param ipaddr IP address of the inserted ARP entry.\r
+ * @param ethaddr Ethernet address of the inserted ARP entry.\r
+ * @param flags Defines behaviour:\r
+ * - ETHARP_TRY_HARD Allows ARP to insert this as a new item. If not specified,\r
+ * only existing ARP entries will be updated.\r
+ *\r
+ * @return\r
+ * - ERR_OK Succesfully updated ARP cache.\r
+ * - ERR_MEM If we could not add a new ARP entry when ETHARP_TRY_HARD was set.\r
+ * - ERR_ARG Non-unicast address given, those will not appear in ARP cache.\r
+ *\r
+ * @see pbuf_free()\r
+ */\r
+static err_t\r
+update_arp_entry(struct netif *netif, struct ip_addr *ipaddr, struct eth_addr *ethaddr, u8_t flags)\r
+{\r
+ s8_t i, k;\r
+ LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE | 3, ("update_arp_entry()\n"));\r
+ LWIP_ASSERT("netif->hwaddr_len != 0", netif->hwaddr_len != 0);\r
+ LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: %u.%u.%u.%u - %02x:%02x:%02x:%02x:%02x:%02x\n",\r
+ ip4_addr1(ipaddr), ip4_addr2(ipaddr), ip4_addr3(ipaddr), ip4_addr4(ipaddr), \r
+ ethaddr->addr[0], ethaddr->addr[1], ethaddr->addr[2],\r
+ ethaddr->addr[3], ethaddr->addr[4], ethaddr->addr[5]));\r
+ /* non-unicast address? */\r
+ if (ip_addr_isany(ipaddr) ||\r
+ ip_addr_isbroadcast(ipaddr, netif) ||\r
+ ip_addr_ismulticast(ipaddr)) {\r
+ LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: will not add non-unicast IP address to ARP cache\n"));\r
+ return ERR_ARG;\r
+ }\r
+ /* find or create ARP entry */\r
+ i = find_entry(ipaddr, flags);\r
+ /* bail out if no entry could be found */\r
+ if (i < 0) return (err_t)i;\r
+ \r
+ /* mark it stable */\r
+ arp_table[i].state = ETHARP_STATE_STABLE;\r
+\r
+ LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: updating stable entry %u\n", i));\r
+ /* update address */\r
+ for (k = 0; k < netif->hwaddr_len; ++k) {\r
+ arp_table[i].ethaddr.addr[k] = ethaddr->addr[k];\r
+ }\r
+ /* reset time stamp */\r
+ arp_table[i].ctime = 0;\r
+/* this is where we will send out queued packets! */\r
+#if ARP_QUEUEING\r
+ while (arp_table[i].p != NULL) {\r
+ /* get the first packet on the queue */\r
+ struct pbuf *p = arp_table[i].p;\r
+ /* Ethernet header */\r
+ struct eth_hdr *ethhdr = p->payload;\r
+ /* remember (and reference) remainder of queue */\r
+ /* note: this will also terminate the p pbuf chain */\r
+ arp_table[i].p = pbuf_dequeue(p);\r
+ /* fill-in Ethernet header */\r
+ for (k = 0; k < netif->hwaddr_len; ++k) {\r
+ ethhdr->dest.addr[k] = ethaddr->addr[k];\r
+ ethhdr->src.addr[k] = netif->hwaddr[k];\r
+ }\r
+ ethhdr->type = htons(ETHTYPE_IP);\r
+ LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: sending queued IP packet %p.\n", (void *)p));\r
+ /* send the queued IP packet */\r
+ netif->linkoutput(netif, p);\r
+ /* free the queued IP packet */\r
+ pbuf_free(p);\r
+ }\r
+#endif\r
+ return ERR_OK;\r
+}\r
+\r
+/**\r
+ * Updates the ARP table using the given IP packet.\r
+ *\r
+ * Uses the incoming IP packet's source address to update the\r
+ * ARP cache for the local network. The function does not alter\r
+ * or free the packet. This function must be called before the\r
+ * packet p is passed to the IP layer.\r
+ *\r
+ * @param netif The lwIP network interface on which the IP packet pbuf arrived.\r
+ * @param pbuf The IP packet that arrived on netif.\r
+ *\r
+ * @return NULL\r
+ *\r
+ * @see pbuf_free()\r
+ */\r
+void\r
+etharp_ip_input(struct netif *netif, struct pbuf *p)\r
+{\r
+ struct ethip_hdr *hdr;\r
+\r
+ /* Only insert an entry if the source IP address of the\r
+ incoming IP packet comes from a host on the local network. */\r
+ hdr = p->payload;\r
+ /* source is not on the local network? */\r
+ if (!ip_addr_netcmp(&(hdr->ip.src), &(netif->ip_addr), &(netif->netmask))) {\r
+ /* do nothing */\r
+ return;\r
+ }\r
+\r
+ LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_ip_input: updating ETHARP table.\n"));\r
+ /* update ARP table */\r
+ /* @todo We could use ETHARP_TRY_HARD if we think we are going to talk\r
+ * back soon (for example, if the destination IP address is ours. */\r
+ update_arp_entry(netif, &(hdr->ip.src), &(hdr->eth.src), 0);\r
+}\r
+\r
+\r
+/**\r
+ * Responds to ARP requests to us. Upon ARP replies to us, add entry to cache \r
+ * send out queued IP packets. Updates cache with snooped address pairs.\r
+ *\r
+ * Should be called for incoming ARP packets. The pbuf in the argument\r
+ * is freed by this function.\r
+ *\r
+ * @param netif The lwIP network interface on which the ARP packet pbuf arrived.\r
+ * @param pbuf The ARP packet that arrived on netif. Is freed by this function.\r
+ * @param ethaddr Ethernet address of netif.\r
+ *\r
+ * @return NULL\r
+ *\r
+ * @see pbuf_free()\r
+ */\r
+void\r
+etharp_arp_input(struct netif *netif, struct eth_addr *ethaddr, struct pbuf *p)\r
+{\r
+ struct etharp_hdr *hdr;\r
+ /* these are aligned properly, whereas the ARP header fields might not be */\r
+ struct ip_addr sipaddr, dipaddr;\r
+ u8_t i;\r
+ u8_t for_us;\r
+\r
+ /* drop short ARP packets */\r
+ if (p->tot_len < sizeof(struct etharp_hdr)) {\r
+ LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE | 1, ("etharp_arp_input: packet dropped, too short (%d/%d)\n", p->tot_len, sizeof(struct etharp_hdr)));\r
+ pbuf_free(p);\r
+ return;\r
+ }\r
+\r
+ hdr = p->payload;\r
+ \r
+ /* get aligned copies of addresses */\r
+ *(struct ip_addr2 *)&sipaddr = hdr->sipaddr;\r
+ *(struct ip_addr2 *)&dipaddr = hdr->dipaddr;\r
+\r
+ /* this interface is not configured? */\r
+ if (netif->ip_addr.addr == 0) {\r
+ for_us = 0;\r
+ } else {\r
+ /* ARP packet directed to us? */\r
+ for_us = ip_addr_cmp(&dipaddr, &(netif->ip_addr));\r
+ }\r
+\r
+ /* ARP message directed to us? */\r
+ if (for_us) {\r
+ /* add IP address in ARP cache; assume requester wants to talk to us.\r
+ * can result in directly sending the queued packets for this host. */\r
+ update_arp_entry(netif, &sipaddr, &(hdr->shwaddr), ETHARP_TRY_HARD);\r
+ /* ARP message not directed to us? */\r
+ } else {\r
+ /* update the source IP address in the cache, if present */\r
+ update_arp_entry(netif, &sipaddr, &(hdr->shwaddr), 0);\r
+ }\r
+\r
+ /* now act on the message itself */\r
+ switch (htons(hdr->opcode)) {\r
+ /* ARP request? */\r
+ case ARP_REQUEST:\r
+ /* ARP request. If it asked for our address, we send out a\r
+ * reply. In any case, we time-stamp any existing ARP entry,\r
+ * and possiby send out an IP packet that was queued on it. */\r
+\r
+ LWIP_DEBUGF (ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: incoming ARP request\n"));\r
+ /* ARP request for our address? */\r
+ if (for_us) {\r
+\r
+ LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: replying to ARP request for our IP address\n"));\r
+ /* re-use pbuf to send ARP reply */\r
+ hdr->opcode = htons(ARP_REPLY);\r
+\r
+ hdr->dipaddr = hdr->sipaddr;\r
+ hdr->sipaddr = *(struct ip_addr2 *)&netif->ip_addr;\r
+\r
+ for(i = 0; i < netif->hwaddr_len; ++i) {\r
+ hdr->dhwaddr.addr[i] = hdr->shwaddr.addr[i];\r
+ hdr->shwaddr.addr[i] = ethaddr->addr[i];\r
+ hdr->ethhdr.dest.addr[i] = hdr->dhwaddr.addr[i];\r
+ hdr->ethhdr.src.addr[i] = ethaddr->addr[i];\r
+ }\r
+\r
+ hdr->hwtype = htons(HWTYPE_ETHERNET);\r
+ ARPH_HWLEN_SET(hdr, netif->hwaddr_len);\r
+\r
+ hdr->proto = htons(ETHTYPE_IP);\r
+ ARPH_PROTOLEN_SET(hdr, sizeof(struct ip_addr));\r
+\r
+ hdr->ethhdr.type = htons(ETHTYPE_ARP);\r
+ /* return ARP reply */\r
+ netif->linkoutput(netif, p);\r
+ /* we are not configured? */\r
+ } else if (netif->ip_addr.addr == 0) {\r
+ /* { for_us == 0 and netif->ip_addr.addr == 0 } */\r
+ LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: we are unconfigured, ARP request ignored.\n"));\r
+ /* request was not directed to us */\r
+ } else {\r
+ /* { for_us == 0 and netif->ip_addr.addr != 0 } */\r
+ LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: ARP request was not for us.\n"));\r
+ }\r
+ break;\r
+ case ARP_REPLY:\r
+ /* ARP reply. We already updated the ARP cache earlier. */\r
+ LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: incoming ARP reply\n"));\r
+#if (LWIP_DHCP && DHCP_DOES_ARP_CHECK)\r
+ /* When unconfigured, DHCP wants to know about ARP replies from the\r
+ * address offered to us, as that means someone else uses it already! */\r
+ if (netif->ip_addr.addr == 0) dhcp_arp_reply(netif, &sipaddr);\r
+#endif\r
+ break;\r
+ default:\r
+ LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: ARP unknown opcode type %d\n", htons(hdr->opcode)));\r
+ break;\r
+ }\r
+ /* free ARP packet */\r
+ pbuf_free(p);\r
+}\r
+\r
+/**\r
+ * Resolve and fill-in Ethernet address header for outgoing packet.\r
+ *\r
+ * For IP multicast and broadcast, corresponding Ethernet addresses\r
+ * are selected and the packet is transmitted on the link.\r
+ *\r
+ * For unicast addresses, the packet is submitted to etharp_query(). In\r
+ * case the IP address is outside the local network, the IP address of\r
+ * the gateway is used.\r
+ *\r
+ * @param netif The lwIP network interface which the IP packet will be sent on.\r
+ * @param ipaddr The IP address of the packet destination.\r
+ * @param pbuf The pbuf(s) containing the IP packet to be sent.\r
+ *\r
+ * @return\r
+ * - ERR_RTE No route to destination (no gateway to external networks),\r
+ * or the return type of either etharp_query() or netif->linkoutput().\r
+ */\r
+err_t\r
+etharp_output(struct netif *netif, struct ip_addr *ipaddr, struct pbuf *q)\r
+{\r
+ struct eth_addr *dest, *srcaddr, mcastaddr;\r
+ struct eth_hdr *ethhdr;\r
+ u8_t i;\r
+\r
+ /* make room for Ethernet header - should not fail */\r
+ if (pbuf_header(q, sizeof(struct eth_hdr)) != 0) {\r
+ /* bail out */\r
+ LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE | 2, ("etharp_output: could not allocate room for header.\n"));\r
+ LINK_STATS_INC(link.lenerr);\r
+ return ERR_BUF;\r
+ }\r
+\r
+ /* assume unresolved Ethernet address */\r
+ dest = NULL;\r
+ /* Determine on destination hardware address. Broadcasts and multicasts\r
+ * are special, other IP addresses are looked up in the ARP table. */\r
+\r
+ /* broadcast destination IP address? */\r
+ if (ip_addr_isbroadcast(ipaddr, netif)) {\r
+ /* broadcast on Ethernet also */\r
+ dest = (struct eth_addr *)ðbroadcast;\r
+ /* multicast destination IP address? */\r
+ } else if (ip_addr_ismulticast(ipaddr)) {\r
+ /* Hash IP multicast address to MAC address.*/\r
+ mcastaddr.addr[0] = 0x01;\r
+ mcastaddr.addr[1] = 0x00;\r
+ mcastaddr.addr[2] = 0x5e;\r
+ mcastaddr.addr[3] = ip4_addr2(ipaddr) & 0x7f;\r
+ mcastaddr.addr[4] = ip4_addr3(ipaddr);\r
+ mcastaddr.addr[5] = ip4_addr4(ipaddr);\r
+ /* destination Ethernet address is multicast */\r
+ dest = &mcastaddr;\r
+ /* unicast destination IP address? */\r
+ } else {\r
+ /* outside local network? */\r
+ if (!ip_addr_netcmp(ipaddr, &(netif->ip_addr), &(netif->netmask))) {\r
+ /* interface has default gateway? */\r
+ if (netif->gw.addr != 0) {\r
+ /* send to hardware address of default gateway IP address */\r
+ ipaddr = &(netif->gw);\r
+ /* no default gateway available */\r
+ } else {\r
+ /* no route to destination error (default gateway missing) */\r
+ return ERR_RTE;\r
+ }\r
+ }\r
+ /* queue on destination Ethernet address belonging to ipaddr */\r
+ return etharp_query(netif, ipaddr, q);\r
+ }\r
+\r
+ /* continuation for multicast/broadcast destinations */\r
+ /* obtain source Ethernet address of the given interface */\r
+ srcaddr = (struct eth_addr *)netif->hwaddr;\r
+ ethhdr = q->payload;\r
+ for (i = 0; i < netif->hwaddr_len; i++) {\r
+ ethhdr->dest.addr[i] = dest->addr[i];\r
+ ethhdr->src.addr[i] = srcaddr->addr[i];\r
+ }\r
+ ethhdr->type = htons(ETHTYPE_IP);\r
+ /* send packet directly on the link */\r
+ return netif->linkoutput(netif, q);\r
+}\r
+\r
+/**\r
+ * Send an ARP request for the given IP address and/or queue a packet.\r
+ *\r
+ * If the IP address was not yet in the cache, a pending ARP cache entry\r
+ * is added and an ARP request is sent for the given address. The packet\r
+ * is queued on this entry.\r
+ *\r
+ * If the IP address was already pending in the cache, a new ARP request\r
+ * is sent for the given address. The packet is queued on this entry.\r
+ *\r
+ * If the IP address was already stable in the cache, and a packet is\r
+ * given, it is directly sent and no ARP request is sent out. \r
+ * \r
+ * If the IP address was already stable in the cache, and no packet is\r
+ * given, an ARP request is sent out.\r
+ * \r
+ * @param netif The lwIP network interface on which ipaddr\r
+ * must be queried for.\r
+ * @param ipaddr The IP address to be resolved.\r
+ * @param q If non-NULL, a pbuf that must be delivered to the IP address.\r
+ * q is not freed by this function.\r
+ *\r
+ * @return\r
+ * - ERR_BUF Could not make room for Ethernet header.\r
+ * - ERR_MEM Hardware address unknown, and no more ARP entries available\r
+ * to query for address or queue the packet.\r
+ * - ERR_MEM Could not queue packet due to memory shortage.\r
+ * - ERR_RTE No route to destination (no gateway to external networks).\r
+ * - ERR_ARG Non-unicast address given, those will not appear in ARP cache.\r
+ *\r
+ */\r
+err_t etharp_query(struct netif *netif, struct ip_addr *ipaddr, struct pbuf *q)\r
+{\r
+ struct pbuf *p;\r
+ struct eth_addr * srcaddr = (struct eth_addr *)netif->hwaddr;\r
+ err_t result = ERR_MEM;\r
+ s8_t i; /* ARP entry index */\r
+ u8_t k; /* Ethernet address octet index */\r
+\r
+ /* non-unicast address? */\r
+ if (ip_addr_isbroadcast(ipaddr, netif) ||\r
+ ip_addr_ismulticast(ipaddr) ||\r
+ ip_addr_isany(ipaddr)) {\r
+ LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: will not add non-unicast IP address to ARP cache\n"));\r
+ return ERR_ARG;\r
+ }\r
+\r
+ /* find entry in ARP cache, ask to create entry if queueing packet */\r
+ i = find_entry(ipaddr, ETHARP_TRY_HARD);\r
+\r
+ /* could not find or create entry? */\r
+ if (i < 0)\r
+ {\r
+ LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: could not create ARP entry\n"));\r
+ #ifdef LWIP_DEBUG\r
+ if (q) LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: packet dropped\n"));\r
+ #endif\r
+ return (err_t)i;\r
+ }\r
+\r
+ /* mark a fresh entry as pending (we just sent a request) */\r
+ if (arp_table[i].state == ETHARP_STATE_EMPTY) {\r
+ arp_table[i].state = ETHARP_STATE_PENDING;\r
+ }\r
+\r
+ /* { i is either a STABLE or (new or existing) PENDING entry } */\r
+ LWIP_ASSERT("arp_table[i].state == PENDING or STABLE",\r
+ ((arp_table[i].state == ETHARP_STATE_PENDING) ||\r
+ (arp_table[i].state == ETHARP_STATE_STABLE)));\r
+\r
+ /* do we have a pending entry? or an implicit query request? */\r
+ if ((arp_table[i].state == ETHARP_STATE_PENDING) || (q == NULL)) {\r
+ /* try to resolve it; send out ARP request */\r
+ result = etharp_request(netif, ipaddr);\r
+ }\r
+ \r
+ /* packet given? */\r
+ if (q != NULL) {\r
+ /* stable entry? */\r
+ if (arp_table[i].state == ETHARP_STATE_STABLE) {\r
+ /* we have a valid IP->Ethernet address mapping,\r
+ * fill in the Ethernet header for the outgoing packet */\r
+ struct eth_hdr *ethhdr = q->payload;\r
+ for(k = 0; k < netif->hwaddr_len; k++) {\r
+ ethhdr->dest.addr[k] = arp_table[i].ethaddr.addr[k];\r
+ ethhdr->src.addr[k] = srcaddr->addr[k];\r
+ }\r
+ ethhdr->type = htons(ETHTYPE_IP);\r
+ LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: sending packet %p\n", (void *)q));\r
+ /* send the packet */\r
+ result = netif->linkoutput(netif, q);\r
+ /* pending entry? (either just created or already pending */\r
+ } else if (arp_table[i].state == ETHARP_STATE_PENDING) {\r
+#if ARP_QUEUEING /* queue the given q packet */\r
+ /* copy any PBUF_REF referenced payloads into PBUF_RAM */\r
+ /* (the caller of lwIP assumes the referenced payload can be\r
+ * freed after it returns from the lwIP call that brought us here) */\r
+ p = pbuf_take(q);\r
+ /* packet could be taken over? */\r
+ if (p != NULL) {\r
+ /* queue packet ... */\r
+ if (arp_table[i].p == NULL) {\r
+ /* ... in the empty queue */\r
+ pbuf_ref(p);\r
+ arp_table[i].p = p;\r
+#if 0 /* multi-packet-queueing disabled, see bug #11400 */\r
+ } else {\r
+ /* ... at tail of non-empty queue */\r
+ pbuf_queue(arp_table[i].p, p);\r
+#endif\r
+ }\r
+ LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: queued packet %p on ARP entry %d\n", (void *)q, i));\r
+ result = ERR_OK;\r
+ } else {\r
+ LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: could not queue a copy of PBUF_REF packet %p (out of memory)\n", (void *)q));\r
+ /* { result == ERR_MEM } through initialization */\r
+ }\r
+#else /* ARP_QUEUEING == 0 */\r
+ /* q && state == PENDING && ARP_QUEUEING == 0 => result = ERR_MEM */\r
+ /* { result == ERR_MEM } through initialization */\r
+ LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: Ethernet destination address unknown, queueing disabled, packet %p dropped\n", (void *)q));\r
+#endif\r
+ }\r
+ }\r
+ return result;\r
+}\r
+\r
+err_t etharp_request(struct netif *netif, struct ip_addr *ipaddr)\r
+{\r
+ struct pbuf *p;\r
+ struct eth_addr * srcaddr = (struct eth_addr *)netif->hwaddr;\r
+ err_t result = ERR_OK;\r
+ u8_t k; /* ARP entry index */\r
+\r
+ /* allocate a pbuf for the outgoing ARP request packet */\r
+ p = pbuf_alloc(PBUF_LINK, sizeof(struct etharp_hdr), PBUF_RAM);\r
+ /* could allocate a pbuf for an ARP request? */\r
+ if (p != NULL) {\r
+ struct etharp_hdr *hdr = p->payload;\r
+ LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_request: sending ARP request.\n"));\r
+ hdr->opcode = htons(ARP_REQUEST);\r
+ for (k = 0; k < netif->hwaddr_len; k++)\r
+ {\r
+ hdr->shwaddr.addr[k] = srcaddr->addr[k];\r
+ /* the hardware address is what we ask for, in\r
+ * a request it is a don't-care value, we use zeroes */\r
+ hdr->dhwaddr.addr[k] = 0x00;\r
+ }\r
+ hdr->dipaddr = *(struct ip_addr2 *)ipaddr;\r
+ hdr->sipaddr = *(struct ip_addr2 *)&netif->ip_addr;\r
+\r
+ hdr->hwtype = htons(HWTYPE_ETHERNET);\r
+ ARPH_HWLEN_SET(hdr, netif->hwaddr_len);\r
+\r
+ hdr->proto = htons(ETHTYPE_IP);\r
+ ARPH_PROTOLEN_SET(hdr, sizeof(struct ip_addr));\r
+ for (k = 0; k < netif->hwaddr_len; ++k)\r
+ {\r
+ /* broadcast to all network interfaces on the local network */\r
+ hdr->ethhdr.dest.addr[k] = 0xff;\r
+ hdr->ethhdr.src.addr[k] = srcaddr->addr[k];\r
+ }\r
+ hdr->ethhdr.type = htons(ETHTYPE_ARP);\r
+ /* send ARP query */\r
+ result = netif->linkoutput(netif, p);\r
+ /* free ARP query packet */\r
+ pbuf_free(p);\r
+ p = NULL;\r
+ /* could not allocate pbuf for ARP request */\r
+ } else {\r
+ result = ERR_MEM;\r
+ LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE | 2, ("etharp_request: could not allocate pbuf for ARP request.\n"));\r
+ }\r
+ return result;\r
+}\r
--- /dev/null
+/*\r
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. The name of the author may not be used to endorse or promote products\r
+ * derived from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT\r
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT\r
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING\r
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY\r
+ * OF SUCH DAMAGE.\r
+ *\r
+ * This file is part of the lwIP TCP/IP stack.\r
+ *\r
+ * Author: Adam Dunkels <adam@sics.se>\r
+ *\r
+ */\r
+\r
+/* lwIP includes. */\r
+#include <string.h>\r
+#include "lwip/opt.h"\r
+#include "lwip/def.h"\r
+#include "lwip/mem.h"\r
+#include "lwip/pbuf.h"\r
+#include "lwip/sys.h"\r
+#include <lwip/stats.h>\r
+#include "netif/etharp.h"\r
+\r
+/* FreeRTOS includes. */\r
+#include "FreeRTOS.h"\r
+#include "SAM7_EMAC.h"\r
+#include "Emac.h"\r
+\r
+#define netifMTU ( 1500 )\r
+#define netifINTERFACE_TASK_STACK_SIZE ( 350 )\r
+#define netifINTERFACE_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )\r
+#define netifGUARD_BLOCK_TIME ( 250 )\r
+#define IFNAME0 'e'\r
+#define IFNAME1 'm'\r
+\r
+/* lwIP definitions. */\r
+struct ethernetif\r
+{\r
+ struct eth_addr *ethaddr;\r
+};\r
+static const struct eth_addr ethbroadcast = { { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff } };\r
+static struct netif *xNetIf = NULL;\r
+\r
+/* Forward declarations. */\r
+static void ethernetif_input( void * );\r
+static err_t ethernetif_output( struct netif *netif, struct pbuf *p, struct ip_addr *ipaddr );\r
+err_t ethernetif_init( struct netif *netif );\r
+\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+static void low_level_init( struct netif *netif )\r
+{\r
+unsigned portBASE_TYPE uxPriority;\r
+\r
+ /* set MAC hardware address length */\r
+ netif->hwaddr_len = 6;\r
+\r
+ /* set MAC hardware address */\r
+ netif->hwaddr[0] = emacETHADDR0;\r
+ netif->hwaddr[1] = emacETHADDR1;\r
+ netif->hwaddr[2] = emacETHADDR2;\r
+ netif->hwaddr[3] = emacETHADDR3;\r
+ netif->hwaddr[4] = emacETHADDR4;\r
+ netif->hwaddr[5] = emacETHADDR5;\r
+\r
+ /* maximum transfer unit */\r
+ netif->mtu = netifMTU;\r
+\r
+ /* broadcast capability */\r
+ netif->flags = NETIF_FLAG_BROADCAST;\r
+\r
+ xNetIf = netif;\r
+\r
+ /* Initialise the EMAC. This routine contains code that polls status bits. \r
+ If the Ethernet cable is not plugged in then this can take a considerable \r
+ time. To prevent this starving lower priority tasks of processing time we\r
+ lower our priority prior to the call, then raise it back again once the\r
+ initialisation is complete. */\r
+ uxPriority = uxTaskPriorityGet( NULL );\r
+ vTaskPrioritySet( NULL, tskIDLE_PRIORITY );\r
+ while( xEMACInit() == NULL )\r
+ {\r
+ __asm( "NOP" );\r
+ }\r
+ vTaskPrioritySet( NULL, uxPriority );\r
+\r
+ /* Create the task that handles the EMAC. */\r
+ xTaskCreate( ethernetif_input, ( signed portCHAR * ) "ETH_INT", netifINTERFACE_TASK_STACK_SIZE, NULL, netifINTERFACE_TASK_PRIORITY, NULL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * low_level_output(): Should do the actual transmission of the packet. The \r
+ * packet is contained in the pbuf that is passed to the function. This pbuf \r
+ * might be chained.\r
+ */\r
+static err_t low_level_output( struct netif *netif, struct pbuf *p )\r
+{\r
+struct pbuf *q;\r
+static xSemaphoreHandle xTxSemaphore = NULL;\r
+err_t xReturn = ERR_OK;\r
+\r
+ /* Parameter not used. */\r
+ ( void ) netif;\r
+\r
+ if( xTxSemaphore == NULL )\r
+ {\r
+ vSemaphoreCreateBinary( xTxSemaphore );\r
+ }\r
+\r
+ #if ETH_PAD_SIZE\r
+ pbuf_header( p, -ETH_PAD_SIZE ); /* drop the padding word */\r
+ #endif\r
+\r
+ /* Access to the EMAC is guarded using a semaphore. */\r
+ if( xSemaphoreTake( xTxSemaphore, netifGUARD_BLOCK_TIME ) )\r
+ {\r
+ for( q = p; q != NULL; q = q->next )\r
+ {\r
+ /* Send the data from the pbuf to the interface, one pbuf at a \r
+ time. The size of the data in each pbuf is kept in the ->len \r
+ variable. if q->next == NULL then this is the last pbuf in the\r
+ chain. */\r
+ if( !lEMACSend( q->payload, q->len, ( q->next == NULL ) ) )\r
+ {\r
+ xReturn = ~ERR_OK;\r
+ }\r
+ }\r
+\r
+ xSemaphoreGive( xTxSemaphore );\r
+ }\r
+ \r
+\r
+ #if ETH_PAD_SIZE\r
+ pbuf_header( p, ETH_PAD_SIZE ); /* reclaim the padding word */\r
+ #endif\r
+\r
+ #if LINK_STATS\r
+ lwip_stats.link.xmit++;\r
+ #endif /* LINK_STATS */\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * low_level_input(): Should allocate a pbuf and transfer the bytes of the \r
+ * incoming packet from the interface into the pbuf. \r
+ */\r
+static struct pbuf *low_level_input( struct netif *netif )\r
+{\r
+struct pbuf *p = NULL, *q;\r
+u16_t len = 0;\r
+static xSemaphoreHandle xRxSemaphore = NULL;\r
+\r
+ /* Parameter not used. */\r
+ ( void ) netif;\r
+\r
+ if( xRxSemaphore == NULL )\r
+ {\r
+ vSemaphoreCreateBinary( xRxSemaphore );\r
+ }\r
+\r
+ /* Access to the emac is guarded using a semaphore. */\r
+ if( xSemaphoreTake( xRxSemaphore, netifGUARD_BLOCK_TIME ) )\r
+ {\r
+ /* Obtain the size of the packet. */\r
+ len = ulEMACInputLength();\r
+ \r
+ if( len )\r
+ {\r
+ #if ETH_PAD_SIZE\r
+ len += ETH_PAD_SIZE; /* allow room for Ethernet padding */\r
+ #endif\r
+ \r
+ /* We allocate a pbuf chain of pbufs from the pool. */\r
+ p = pbuf_alloc( PBUF_RAW, len, PBUF_POOL );\r
+ \r
+ if( p != NULL )\r
+ {\r
+ #if ETH_PAD_SIZE\r
+ pbuf_header( p, -ETH_PAD_SIZE ); /* drop the padding word */\r
+ #endif\r
+ \r
+ /* Let the driver know we are going to read a new packet. */\r
+ vEMACRead( NULL, 0, len );\r
+ \r
+ /* We iterate over the pbuf chain until we have read the entire\r
+ packet into the pbuf. */ \r
+ for( q = p; q != NULL; q = q->next )\r
+ {\r
+ /* Read enough bytes to fill this pbuf in the chain. The \r
+ available data in the pbuf is given by the q->len variable. */\r
+ vEMACRead( q->payload, q->len, len );\r
+ }\r
+ \r
+ #if ETH_PAD_SIZE\r
+ pbuf_header( p, ETH_PAD_SIZE ); /* reclaim the padding word */\r
+ #endif\r
+ #if LINK_STATS\r
+ lwip_stats.link.recv++;\r
+ #endif /* LINK_STATS */\r
+ }\r
+ else\r
+ {\r
+ #if LINK_STATS\r
+ lwip_stats.link.memerr++;\r
+ lwip_stats.link.drop++;\r
+ #endif /* LINK_STATS */\r
+ }\r
+ }\r
+\r
+ xSemaphoreGive( xRxSemaphore );\r
+ }\r
+\r
+ return p;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * ethernetif_output(): This function is called by the TCP/IP stack when an \r
+ * IP packet should be sent. It calls the function called low_level_output() \r
+ * to do the actual transmission of the packet.\r
+ */\r
+static err_t ethernetif_output( struct netif *netif, struct pbuf *p, struct ip_addr *ipaddr )\r
+{\r
+ /* resolve hardware address, then send (or queue) packet */\r
+ return etharp_output( netif, ipaddr, p );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * ethernetif_input(): This function should be called when a packet is ready to \r
+ * be read from the interface. It uses the function low_level_input() that \r
+ * should handle the actual reception of bytes from the network interface.\r
+ */\r
+static void ethernetif_input( void * pvParameters )\r
+{\r
+struct ethernetif *ethernetif;\r
+struct eth_hdr *ethhdr;\r
+struct pbuf *p;\r
+\r
+ ( void ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ do\r
+ {\r
+ ethernetif = xNetIf->state;\r
+\r
+ /* move received packet into a new pbuf */\r
+ p = low_level_input( xNetIf );\r
+\r
+ if( p == NULL )\r
+ {\r
+ /* No packet could be read. Wait a for an interrupt to tell us \r
+ there is more data available. */\r
+ vEMACWaitForInput();\r
+ }\r
+\r
+ } while( p == NULL );\r
+ \r
+ /* points to packet payload, which starts with an Ethernet header */\r
+ ethhdr = p->payload;\r
+ \r
+ #if LINK_STATS\r
+ lwip_stats.link.recv++;\r
+ #endif /* LINK_STATS */\r
+ \r
+ ethhdr = p->payload;\r
+ \r
+ switch( htons( ethhdr->type ) )\r
+ {\r
+ /* IP packet? */\r
+ case ETHTYPE_IP:\r
+ /* update ARP table */\r
+ etharp_ip_input( xNetIf, p );\r
+ \r
+ /* skip Ethernet header */\r
+ pbuf_header( p, (s16_t)-sizeof(struct eth_hdr) );\r
+ \r
+ /* pass to network layer */\r
+ xNetIf->input( p, xNetIf );\r
+ break;\r
+ \r
+ case ETHTYPE_ARP:\r
+ /* pass p to ARP module */\r
+ etharp_arp_input( xNetIf, ethernetif->ethaddr, p );\r
+ break;\r
+ \r
+ default:\r
+ pbuf_free( p );\r
+ p = NULL;\r
+ break;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void arp_timer( void *arg )\r
+{\r
+ ( void ) arg;\r
+\r
+ etharp_tmr();\r
+ sys_timeout( ARP_TMR_INTERVAL, arp_timer, NULL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+err_t ethernetif_init( struct netif *netif )\r
+{\r
+struct ethernetif *ethernetif;\r
+\r
+ ethernetif = mem_malloc( sizeof(struct ethernetif) );\r
+\r
+ if( ethernetif == NULL )\r
+ {\r
+ LWIP_DEBUGF( NETIF_DEBUG, ("ethernetif_init: out of memory\n") );\r
+ return ERR_MEM;\r
+ }\r
+\r
+ netif->state = ethernetif;\r
+ netif->name[0] = IFNAME0;\r
+ netif->name[1] = IFNAME1;\r
+ netif->output = ethernetif_output;\r
+ netif->linkoutput = low_level_output;\r
+\r
+ ethernetif->ethaddr = ( struct eth_addr * ) &( netif->hwaddr[0] );\r
+\r
+ low_level_init( netif );\r
+ etharp_init();\r
+ sys_timeout( ARP_TMR_INTERVAL, arp_timer, NULL );\r
+\r
+ return ERR_OK;\r
+}\r
--- /dev/null
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#include "lwip/opt.h"
+
+#if LWIP_HAVE_LOOPIF
+
+#include "netif/loopif.h"
+#include "lwip/mem.h"
+
+#if defined(LWIP_DEBUG) && defined(LWIP_TCPDUMP)
+#include "netif/tcpdump.h"
+#endif /* LWIP_DEBUG && LWIP_TCPDUMP */
+
+#include "lwip/tcp.h"
+#include "lwip/ip.h"
+
+static void
+loopif_input( void * arg )
+{
+ struct netif *netif = (struct netif *)( ((void **)arg)[ 0 ] );
+ struct pbuf *r = (struct pbuf *)( ((void **)arg)[ 1 ] );
+
+ mem_free( arg );
+ netif -> input( r, netif );
+}
+
+static err_t
+loopif_output(struct netif *netif, struct pbuf *p,
+ struct ip_addr *ipaddr)
+{
+ struct pbuf *q, *r;
+ char *ptr;
+ void **arg;
+
+#if defined(LWIP_DEBUG) && defined(LWIP_TCPDUMP)
+ tcpdump(p);
+#endif /* LWIP_DEBUG && LWIP_TCPDUMP */
+
+ r = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_RAM);
+ if (r != NULL) {
+ ptr = r->payload;
+
+ for(q = p; q != NULL; q = q->next) {
+ memcpy(ptr, q->payload, q->len);
+ ptr += q->len;
+ }
+
+ arg = mem_malloc( sizeof( void *[2]));
+ if( NULL == arg ) {
+ return ERR_MEM;
+ }
+
+ arg[0] = netif;
+ arg[1] = r;
+ /**
+ * workaround (patch #1779) to try to prevent bug #2595:
+ * When connecting to "localhost" with the loopif interface,
+ * tcp_output doesn't get the opportunity to finnish sending the
+ * segment before tcp_process gets it, resulting in tcp_process
+ * referencing pcb->unacked-> which still is NULL.
+ *
+ * TODO: Is there still a race condition here? Leon
+ */
+ sys_timeout( 1, loopif_input, arg );
+
+ return ERR_OK;
+ }
+ return ERR_MEM;
+}
+
+err_t
+loopif_init(struct netif *netif)
+{
+ netif->name[0] = 'l';
+ netif->name[1] = 'o';
+#if 0 /** TODO: I think this should be enabled, or not? Leon */
+ netif->input = loopif_input;
+#endif
+ netif->output = loopif_output;
+ return ERR_OK;
+}
+
+#endif /* LWIP_HAVE_LOOPIF */
+
+
+
+
+
+
+
--- /dev/null
+/*****************************************************************************
+* auth.c - Network Authentication and Phase Control program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* Copyright (c) 1997 by Global Election Systems Inc. All rights reserved.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher <marc@mbsi.ca>
+* Ported to lwIP.
+* 97-12-08 Guy Lancaster <lancasterg@acm.org>, Global Election Systems Inc.
+* Ported from public pppd code.
+*****************************************************************************/
+/*
+ * auth.c - PPP authentication and phase control.
+ *
+ * Copyright (c) 1993 The Australian National University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by the Australian National University. The name of the University
+ * may not be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University. The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include "ppp.h"
+#if PPP_SUPPORT > 0
+#include "fsm.h"
+#include "lcp.h"
+#include "pap.h"
+#include "chap.h"
+#include "auth.h"
+#include "ipcp.h"
+
+#if CBCP_SUPPORT > 0
+#include "cbcp.h"
+#endif
+
+#include "pppdebug.h"
+
+
+/*************************/
+/*** LOCAL DEFINITIONS ***/
+/*************************/
+
+/* Bits in auth_pending[] */
+#define PAP_WITHPEER 1
+#define PAP_PEER 2
+#define CHAP_WITHPEER 4
+#define CHAP_PEER 8
+
+
+
+/************************/
+/*** LOCAL DATA TYPES ***/
+/************************/
+/* Used for storing a sequence of words. Usually malloced. */
+struct wordlist {
+ struct wordlist *next;
+ char word[1];
+};
+
+
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+extern char *crypt (const char *, const char *);
+
+/* Prototypes for procedures local to this file. */
+
+static void network_phase (int);
+static void check_idle (void *);
+static void connect_time_expired (void *);
+#if 0
+static int login (char *, char *, char **, int *);
+#endif
+static void logout (void);
+static int null_login (int);
+static int get_pap_passwd (int, char *, char *);
+static int have_pap_secret (void);
+static int have_chap_secret (char *, char *, u32_t);
+static int ip_addr_check (u32_t, struct wordlist *);
+#if 0 /* PAP_SUPPORT > 0 || CHAP_SUPPORT > 0 */
+static void set_allowed_addrs(int unit, struct wordlist *addrs);
+static void free_wordlist (struct wordlist *);
+#endif
+#if CBCP_SUPPORT > 0
+static void callback_phase (int);
+#endif
+
+
+/******************************/
+/*** PUBLIC DATA STRUCTURES ***/
+/******************************/
+
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+#if PAP_SUPPORT > 0 || CHAP_SUPPORT > 0
+/* The name by which the peer authenticated itself to us. */
+static char peer_authname[MAXNAMELEN];
+#endif
+
+/* Records which authentication operations haven't completed yet. */
+static int auth_pending[NUM_PPP];
+
+/* Set if we have successfully called login() */
+static int logged_in;
+
+/* Set if we have run the /etc/ppp/auth-up script. */
+static int did_authup;
+
+/* List of addresses which the peer may use. */
+static struct wordlist *addresses[NUM_PPP];
+
+/* Number of network protocols which we have opened. */
+static int num_np_open;
+
+/* Number of network protocols which have come up. */
+static int num_np_up;
+
+#if PAP_SUPPORT > 0 || CHAP_SUPPORT > 0
+/* Set if we got the contents of passwd[] from the pap-secrets file. */
+static int passwd_from_file;
+#endif
+
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/*
+ * An Open on LCP has requested a change from Dead to Establish phase.
+ * Do what's necessary to bring the physical layer up.
+ */
+void link_required(int unit)
+{
+ AUTHDEBUG((LOG_INFO, "link_required: %d\n", unit));
+}
+
+/*
+ * LCP has terminated the link; go to the Dead phase and take the
+ * physical layer down.
+ */
+void link_terminated(int unit)
+{
+ AUTHDEBUG((LOG_INFO, "link_terminated: %d\n", unit));
+
+ if (lcp_phase[unit] == PHASE_DEAD)
+ return;
+ if (logged_in)
+ logout();
+ lcp_phase[unit] = PHASE_DEAD;
+ AUTHDEBUG((LOG_NOTICE, "Connection terminated.\n"));
+ pppMainWakeup(unit);
+}
+
+/*
+ * LCP has gone down; it will either die or try to re-establish.
+ */
+void link_down(int unit)
+{
+ int i;
+ struct protent *protp;
+
+ AUTHDEBUG((LOG_INFO, "link_down: %d\n", unit));
+ if (did_authup) {
+ /* XXX Do link down processing. */
+ did_authup = 0;
+ }
+ for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) {
+ if (!protp->enabled_flag)
+ continue;
+ if (protp->protocol != PPP_LCP && protp->lowerdown != NULL)
+ (*protp->lowerdown)(unit);
+ if (protp->protocol < 0xC000 && protp->close != NULL)
+ (*protp->close)(unit, "LCP down");
+ }
+ num_np_open = 0;
+ num_np_up = 0;
+ if (lcp_phase[unit] != PHASE_DEAD)
+ lcp_phase[unit] = PHASE_TERMINATE;
+ pppMainWakeup(unit);
+}
+
+/*
+ * The link is established.
+ * Proceed to the Dead, Authenticate or Network phase as appropriate.
+ */
+void link_established(int unit)
+{
+ int auth;
+ int i;
+ struct protent *protp;
+ lcp_options *wo = &lcp_wantoptions[unit];
+ lcp_options *go = &lcp_gotoptions[unit];
+#if PAP_SUPPORT > 0 || CHAP_SUPPORT > 0
+ lcp_options *ho = &lcp_hisoptions[unit];
+#endif
+
+ AUTHDEBUG((LOG_INFO, "link_established: %d\n", unit));
+ /*
+ * Tell higher-level protocols that LCP is up.
+ */
+ for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i)
+ if (protp->protocol != PPP_LCP && protp->enabled_flag
+ && protp->lowerup != NULL)
+ (*protp->lowerup)(unit);
+
+ if (ppp_settings.auth_required && !(go->neg_chap || go->neg_upap)) {
+ /*
+ * We wanted the peer to authenticate itself, and it refused:
+ * treat it as though it authenticated with PAP using a username
+ * of "" and a password of "". If that's not OK, boot it out.
+ */
+ if (!wo->neg_upap || !null_login(unit)) {
+ AUTHDEBUG((LOG_WARNING, "peer refused to authenticate\n"));
+ lcp_close(unit, "peer refused to authenticate");
+ return;
+ }
+ }
+
+ lcp_phase[unit] = PHASE_AUTHENTICATE;
+ auth = 0;
+#if CHAP_SUPPORT > 0
+ if (go->neg_chap) {
+ ChapAuthPeer(unit, ppp_settings.our_name, go->chap_mdtype);
+ auth |= CHAP_PEER;
+ }
+#endif
+#if PAP_SUPPORT > 0 && CHAP_SUPPORT > 0
+ else
+#endif
+#if PAP_SUPPORT > 0
+ if (go->neg_upap) {
+ upap_authpeer(unit);
+ auth |= PAP_PEER;
+ }
+#endif
+#if CHAP_SUPPORT > 0
+ if (ho->neg_chap) {
+ ChapAuthWithPeer(unit, ppp_settings.user, ho->chap_mdtype);
+ auth |= CHAP_WITHPEER;
+ }
+#endif
+#if PAP_SUPPORT > 0 && CHAP_SUPPORT > 0
+ else
+#endif
+#if PAP_SUPPORT > 0
+ if (ho->neg_upap) {
+ if (ppp_settings.passwd[0] == 0) {
+ passwd_from_file = 1;
+ if (!get_pap_passwd(unit, ppp_settings.user, ppp_settings.passwd))
+ AUTHDEBUG((LOG_ERR, "No secret found for PAP login\n"));
+ }
+ upap_authwithpeer(unit, ppp_settings.user, ppp_settings.passwd);
+ auth |= PAP_WITHPEER;
+ }
+#endif
+ auth_pending[unit] = auth;
+
+ if (!auth)
+ network_phase(unit);
+}
+
+
+/*
+ * The peer has failed to authenticate himself using `protocol'.
+ */
+void auth_peer_fail(int unit, u16_t protocol)
+{
+ AUTHDEBUG((LOG_INFO, "auth_peer_fail: %d proto=%X\n", unit, protocol));
+ /*
+ * Authentication failure: take the link down
+ */
+ lcp_close(unit, "Authentication failed");
+}
+
+
+#if PAP_SUPPORT > 0 || CHAP_SUPPORT > 0
+/*
+ * The peer has been successfully authenticated using `protocol'.
+ */
+void auth_peer_success(int unit, u16_t protocol, char *name, int namelen)
+{
+ int pbit;
+
+ AUTHDEBUG((LOG_INFO, "auth_peer_success: %d proto=%X\n", unit, protocol));
+ switch (protocol) {
+ case PPP_CHAP:
+ pbit = CHAP_PEER;
+ break;
+ case PPP_PAP:
+ pbit = PAP_PEER;
+ break;
+ default:
+ AUTHDEBUG((LOG_WARNING, "auth_peer_success: unknown protocol %x\n",
+ protocol));
+ return;
+ }
+
+ /*
+ * Save the authenticated name of the peer for later.
+ */
+ if (namelen > sizeof(peer_authname) - 1)
+ namelen = sizeof(peer_authname) - 1;
+ BCOPY(name, peer_authname, namelen);
+ peer_authname[namelen] = 0;
+
+ /*
+ * If there is no more authentication still to be done,
+ * proceed to the network (or callback) phase.
+ */
+ if ((auth_pending[unit] &= ~pbit) == 0)
+ network_phase(unit);
+}
+
+/*
+ * We have failed to authenticate ourselves to the peer using `protocol'.
+ */
+void auth_withpeer_fail(int unit, u16_t protocol)
+{
+ int errCode = PPPERR_AUTHFAIL;
+
+ AUTHDEBUG((LOG_INFO, "auth_withpeer_fail: %d proto=%X\n", unit, protocol));
+ if (passwd_from_file)
+ BZERO(ppp_settings.passwd, MAXSECRETLEN);
+ /*
+ * XXX Warning: the unit number indicates the interface which is
+ * not necessarily the PPP connection. It works here as long
+ * as we are only supporting PPP interfaces.
+ */
+ pppIOCtl(unit, PPPCTLS_ERRCODE, &errCode);
+
+ /*
+ * We've failed to authenticate ourselves to our peer.
+ * He'll probably take the link down, and there's not much
+ * we can do except wait for that.
+ */
+}
+
+/*
+ * We have successfully authenticated ourselves with the peer using `protocol'.
+ */
+void auth_withpeer_success(int unit, u16_t protocol)
+{
+ int pbit;
+
+ AUTHDEBUG((LOG_INFO, "auth_withpeer_success: %d proto=%X\n", unit, protocol));
+ switch (protocol) {
+ case PPP_CHAP:
+ pbit = CHAP_WITHPEER;
+ break;
+ case PPP_PAP:
+ if (passwd_from_file)
+ BZERO(ppp_settings.passwd, MAXSECRETLEN);
+ pbit = PAP_WITHPEER;
+ break;
+ default:
+ AUTHDEBUG((LOG_WARNING, "auth_peer_success: unknown protocol %x\n",
+ protocol));
+ pbit = 0;
+ }
+
+ /*
+ * If there is no more authentication still being done,
+ * proceed to the network (or callback) phase.
+ */
+ if ((auth_pending[unit] &= ~pbit) == 0)
+ network_phase(unit);
+}
+#endif
+
+
+/*
+ * np_up - a network protocol has come up.
+ */
+void np_up(int unit, u16_t proto)
+{
+ AUTHDEBUG((LOG_INFO, "np_up: %d proto=%X\n", unit, proto));
+ if (num_np_up == 0) {
+ AUTHDEBUG((LOG_INFO, "np_up: maxconnect=%d idle_time_limit=%d\n",ppp_settings.maxconnect,ppp_settings.idle_time_limit));
+ /*
+ * At this point we consider that the link has come up successfully.
+ */
+ if (ppp_settings.idle_time_limit > 0)
+ TIMEOUT(check_idle, NULL, ppp_settings.idle_time_limit);
+
+ /*
+ * Set a timeout to close the connection once the maximum
+ * connect time has expired.
+ */
+ if (ppp_settings.maxconnect > 0)
+ TIMEOUT(connect_time_expired, 0, ppp_settings.maxconnect);
+ }
+ ++num_np_up;
+}
+
+/*
+ * np_down - a network protocol has gone down.
+ */
+void np_down(int unit, u16_t proto)
+{
+ AUTHDEBUG((LOG_INFO, "np_down: %d proto=%X\n", unit, proto));
+ if (--num_np_up == 0 && ppp_settings.idle_time_limit > 0) {
+ UNTIMEOUT(check_idle, NULL);
+ }
+}
+
+/*
+ * np_finished - a network protocol has finished using the link.
+ */
+void np_finished(int unit, u16_t proto)
+{
+ AUTHDEBUG((LOG_INFO, "np_finished: %d proto=%X\n", unit, proto));
+ if (--num_np_open <= 0) {
+ /* no further use for the link: shut up shop. */
+ lcp_close(0, "No network protocols running");
+ }
+}
+
+/*
+ * auth_reset - called when LCP is starting negotiations to recheck
+ * authentication options, i.e. whether we have appropriate secrets
+ * to use for authenticating ourselves and/or the peer.
+ */
+void auth_reset(int unit)
+{
+ lcp_options *go = &lcp_gotoptions[unit];
+ lcp_options *ao = &lcp_allowoptions[0];
+ ipcp_options *ipwo = &ipcp_wantoptions[0];
+ u32_t remote;
+
+ AUTHDEBUG((LOG_INFO, "auth_reset: %d\n", unit));
+ ao->neg_upap = !ppp_settings.refuse_pap && (ppp_settings.passwd[0] != 0 || get_pap_passwd(unit, NULL, NULL));
+ ao->neg_chap = !ppp_settings.refuse_chap && ppp_settings.passwd[0] != 0 /*have_chap_secret(ppp_settings.user, ppp_settings.remote_name, (u32_t)0)*/;
+
+ if (go->neg_upap && !have_pap_secret())
+ go->neg_upap = 0;
+ if (go->neg_chap) {
+ remote = ipwo->accept_remote? 0: ipwo->hisaddr;
+ if (!have_chap_secret(ppp_settings.remote_name, ppp_settings.our_name, remote))
+ go->neg_chap = 0;
+ }
+}
+
+
+#if PAP_SUPPORT > 0
+/*
+ * check_passwd - Check the user name and passwd against the PAP secrets
+ * file. If requested, also check against the system password database,
+ * and login the user if OK.
+ *
+ * returns:
+ * UPAP_AUTHNAK: Authentication failed.
+ * UPAP_AUTHACK: Authentication succeeded.
+ * In either case, msg points to an appropriate message.
+ */
+int check_passwd(
+ int unit,
+ char *auser,
+ int userlen,
+ char *apasswd,
+ int passwdlen,
+ char **msg,
+ int *msglen
+)
+{
+#if 1
+ *msg = (char *) 0;
+ return UPAP_AUTHACK; /* XXX Assume all entries OK. */
+#else
+ int ret = 0;
+ struct wordlist *addrs = NULL;
+ char passwd[256], user[256];
+ char secret[MAXWORDLEN];
+ static u_short attempts = 0;
+
+ /*
+ * Make copies of apasswd and auser, then null-terminate them.
+ */
+ BCOPY(apasswd, passwd, passwdlen);
+ passwd[passwdlen] = '\0';
+ BCOPY(auser, user, userlen);
+ user[userlen] = '\0';
+ *msg = (char *) 0;
+
+ /* XXX Validate user name and password. */
+ ret = UPAP_AUTHACK; /* XXX Assume all entries OK. */
+
+ if (ret == UPAP_AUTHNAK) {
+ if (*msg == (char *) 0)
+ *msg = "Login incorrect";
+ *msglen = strlen(*msg);
+ /*
+ * Frustrate passwd stealer programs.
+ * Allow 10 tries, but start backing off after 3 (stolen from login).
+ * On 10'th, drop the connection.
+ */
+ if (attempts++ >= 10) {
+ AUTHDEBUG((LOG_WARNING, "%d LOGIN FAILURES BY %s\n", attempts, user));
+ /*ppp_panic("Excess Bad Logins");*/
+ }
+ if (attempts > 3) {
+ sys_msleep((attempts - 3) * 5);
+ }
+ if (addrs != NULL) {
+ free_wordlist(addrs);
+ }
+ } else {
+ attempts = 0; /* Reset count */
+ if (*msg == (char *) 0)
+ *msg = "Login ok";
+ *msglen = strlen(*msg);
+ set_allowed_addrs(unit, addrs);
+ }
+
+ BZERO(passwd, sizeof(passwd));
+ BZERO(secret, sizeof(secret));
+
+ return ret;
+#endif
+}
+#endif
+
+
+/*
+ * auth_ip_addr - check whether the peer is authorized to use
+ * a given IP address. Returns 1 if authorized, 0 otherwise.
+ */
+int auth_ip_addr(int unit, u32_t addr)
+{
+ return ip_addr_check(addr, addresses[unit]);
+}
+
+/*
+ * bad_ip_adrs - return 1 if the IP address is one we don't want
+ * to use, such as an address in the loopback net or a multicast address.
+ * addr is in network byte order.
+ */
+int bad_ip_adrs(u32_t addr)
+{
+ addr = ntohl(addr);
+ return (addr >> IN_CLASSA_NSHIFT) == IN_LOOPBACKNET
+ || IN_MULTICAST(addr) || IN_BADCLASS(addr);
+}
+
+
+#if CHAP_SUPPORT > 0
+/*
+ * get_secret - open the CHAP secret file and return the secret
+ * for authenticating the given client on the given server.
+ * (We could be either client or server).
+ */
+int get_secret(
+ int unit,
+ char *client,
+ char *server,
+ char *secret,
+ int *secret_len,
+ int save_addrs
+)
+{
+#if 1
+ int len;
+ struct wordlist *addrs;
+
+ addrs = NULL;
+
+ if(!client || !client[0] || strcmp(client, ppp_settings.user)) {
+ return 0;
+ }
+
+ len = strlen(ppp_settings.passwd);
+ if (len > MAXSECRETLEN) {
+ AUTHDEBUG((LOG_ERR, "Secret for %s on %s is too long\n", client, server));
+ len = MAXSECRETLEN;
+ }
+ BCOPY(ppp_settings.passwd, secret, len);
+ *secret_len = len;
+
+ return 1;
+#else
+ int ret = 0, len;
+ struct wordlist *addrs;
+ char secbuf[MAXWORDLEN];
+
+ addrs = NULL;
+ secbuf[0] = 0;
+
+ /* XXX Find secret. */
+ if (ret < 0)
+ return 0;
+
+ if (save_addrs)
+ set_allowed_addrs(unit, addrs);
+
+ len = strlen(secbuf);
+ if (len > MAXSECRETLEN) {
+ AUTHDEBUG((LOG_ERR, "Secret for %s on %s is too long\n", client, server));
+ len = MAXSECRETLEN;
+ }
+ BCOPY(secbuf, secret, len);
+ BZERO(secbuf, sizeof(secbuf));
+ *secret_len = len;
+
+ return 1;
+#endif
+}
+#endif
+
+
+#if 0 /* UNUSED */
+/*
+ * auth_check_options - called to check authentication options.
+ */
+void auth_check_options(void)
+{
+ lcp_options *wo = &lcp_wantoptions[0];
+ int can_auth;
+ ipcp_options *ipwo = &ipcp_wantoptions[0];
+ u32_t remote;
+
+ /* Default our_name to hostname, and user to our_name */
+ if (ppp_settings.our_name[0] == 0 || ppp_settings.usehostname)
+ strcpy(ppp_settings.our_name, ppp_settings.hostname);
+ if (ppp_settings.user[0] == 0)
+ strcpy(ppp_settings.user, ppp_settings.our_name);
+
+ /* If authentication is required, ask peer for CHAP or PAP. */
+ if (ppp_settings.auth_required && !wo->neg_chap && !wo->neg_upap) {
+ wo->neg_chap = 1;
+ wo->neg_upap = 1;
+ }
+
+ /*
+ * Check whether we have appropriate secrets to use
+ * to authenticate the peer.
+ */
+ can_auth = wo->neg_upap && have_pap_secret();
+ if (!can_auth && wo->neg_chap) {
+ remote = ipwo->accept_remote? 0: ipwo->hisaddr;
+ can_auth = have_chap_secret(ppp_settings.remote_name, ppp_settings.our_name, remote);
+ }
+
+ if (ppp_settings.auth_required && !can_auth) {
+ ppp_panic("No auth secret");
+ }
+}
+#endif
+
+
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+/*
+ * Proceed to the network phase.
+ */
+static void network_phase(int unit)
+{
+ int i;
+ struct protent *protp;
+ lcp_options *go = &lcp_gotoptions[unit];
+
+ /*
+ * If the peer had to authenticate, run the auth-up script now.
+ */
+ if ((go->neg_chap || go->neg_upap) && !did_authup) {
+ /* XXX Do setup for peer authentication. */
+ did_authup = 1;
+ }
+
+#if CBCP_SUPPORT > 0
+ /*
+ * If we negotiated callback, do it now.
+ */
+ if (go->neg_cbcp) {
+ lcp_phase[unit] = PHASE_CALLBACK;
+ (*cbcp_protent.open)(unit);
+ return;
+ }
+#endif
+
+ lcp_phase[unit] = PHASE_NETWORK;
+ for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i)
+ if (protp->protocol < 0xC000 && protp->enabled_flag
+ && protp->open != NULL) {
+ (*protp->open)(unit);
+ if (protp->protocol != PPP_CCP)
+ ++num_np_open;
+ }
+
+ if (num_np_open == 0)
+ /* nothing to do */
+ lcp_close(0, "No network protocols running");
+}
+
+/*
+ * check_idle - check whether the link has been idle for long
+ * enough that we can shut it down.
+ */
+static void check_idle(void *arg)
+{
+ struct ppp_idle idle;
+ u_short itime;
+
+ (void)arg;
+ if (!get_idle_time(0, &idle))
+ return;
+ itime = LWIP_MIN(idle.xmit_idle, idle.recv_idle);
+ if (itime >= ppp_settings.idle_time_limit) {
+ /* link is idle: shut it down. */
+ AUTHDEBUG((LOG_INFO, "Terminating connection due to lack of activity.\n"));
+ lcp_close(0, "Link inactive");
+ } else {
+ TIMEOUT(check_idle, NULL, ppp_settings.idle_time_limit - itime);
+ }
+}
+
+/*
+ * connect_time_expired - log a message and close the connection.
+ */
+static void connect_time_expired(void *arg)
+{
+ (void)arg;
+
+ AUTHDEBUG((LOG_INFO, "Connect time expired\n"));
+ lcp_close(0, "Connect time expired"); /* Close connection */
+}
+
+#if 0
+/*
+ * login - Check the user name and password against the system
+ * password database, and login the user if OK.
+ *
+ * returns:
+ * UPAP_AUTHNAK: Login failed.
+ * UPAP_AUTHACK: Login succeeded.
+ * In either case, msg points to an appropriate message.
+ */
+static int login(char *user, char *passwd, char **msg, int *msglen)
+{
+ /* XXX Fail until we decide that we want to support logins. */
+ return (UPAP_AUTHNAK);
+}
+#endif
+
+/*
+ * logout - Logout the user.
+ */
+static void logout(void)
+{
+ logged_in = 0;
+}
+
+
+/*
+ * null_login - Check if a username of "" and a password of "" are
+ * acceptable, and iff so, set the list of acceptable IP addresses
+ * and return 1.
+ */
+static int null_login(int unit)
+{
+ (void)unit;
+ /* XXX Fail until we decide that we want to support logins. */
+ return 0;
+}
+
+
+/*
+ * get_pap_passwd - get a password for authenticating ourselves with
+ * our peer using PAP. Returns 1 on success, 0 if no suitable password
+ * could be found.
+ */
+static int get_pap_passwd(int unit, char *user, char *passwd)
+{
+/* normally we would reject PAP if no password is provided,
+ but this causes problems with some providers (like CHT in Taiwan)
+ who incorrectly request PAP and expect a bogus/empty password, so
+ always provide a default user/passwd of "none"/"none"
+*/
+ if(user)
+ strcpy(user, "none");
+ if(passwd)
+ strcpy(passwd, "none");
+
+ return 1;
+}
+
+
+/*
+ * have_pap_secret - check whether we have a PAP file with any
+ * secrets that we could possibly use for authenticating the peer.
+ */
+static int have_pap_secret(void)
+{
+ /* XXX Fail until we set up our passwords. */
+ return 0;
+}
+
+
+/*
+ * have_chap_secret - check whether we have a CHAP file with a
+ * secret that we could possibly use for authenticating `client'
+ * on `server'. Either can be the null string, meaning we don't
+ * know the identity yet.
+ */
+static int have_chap_secret(char *client, char *server, u32_t remote)
+{
+ (void)client;
+ (void)server;
+ (void)remote;
+ /* XXX Fail until we set up our passwords. */
+ return 0;
+}
+
+
+#if 0 /* PAP_SUPPORT > 0 || CHAP_SUPPORT > 0 */
+/*
+ * set_allowed_addrs() - set the list of allowed addresses.
+ */
+static void set_allowed_addrs(int unit, struct wordlist *addrs)
+{
+ if (addresses[unit] != NULL)
+ free_wordlist(addresses[unit]);
+ addresses[unit] = addrs;
+
+#if 0
+ /*
+ * If there's only one authorized address we might as well
+ * ask our peer for that one right away
+ */
+ if (addrs != NULL && addrs->next == NULL) {
+ char *p = addrs->word;
+ struct ipcp_options *wo = &ipcp_wantoptions[unit];
+ u32_t a;
+ struct hostent *hp;
+
+ if (wo->hisaddr == 0 && *p != '!' && *p != '-'
+ && strchr(p, '/') == NULL) {
+ hp = gethostbyname(p);
+ if (hp != NULL && hp->h_addrtype == AF_INET)
+ a = *(u32_t *)hp->h_addr;
+ else
+ a = inet_addr(p);
+ if (a != (u32_t) -1)
+ wo->hisaddr = a;
+ }
+ }
+#endif
+}
+#endif
+
+static int ip_addr_check(u32_t addr, struct wordlist *addrs)
+{
+
+ /* don't allow loopback or multicast address */
+ if (bad_ip_adrs(addr))
+ return 0;
+
+ if (addrs == NULL)
+ return !ppp_settings.auth_required; /* no addresses authorized */
+
+ /* XXX All other addresses allowed. */
+ return 1;
+}
+
+#if 0 /* PAP_SUPPORT > 0 || CHAP_SUPPORT */
+/*
+ * free_wordlist - release memory allocated for a wordlist.
+ */
+static void free_wordlist(struct wordlist *wp)
+{
+ struct wordlist *next;
+
+ while (wp != NULL) {
+ next = wp->next;
+ free(wp);
+ wp = next;
+ }
+}
+#endif
+
+#endif /* PPP_SUPPORT */
--- /dev/null
+/*****************************************************************************
+* auth.h - PPP Authentication and phase control header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1998 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher <marc@mbsi.ca>
+* Ported to lwIP.
+* 97-12-04 Guy Lancaster <lancasterg@acm.org>, Global Election Systems Inc.
+* Original derived from BSD pppd.h.
+*****************************************************************************/
+/*
+ * pppd.h - PPP daemon global declarations.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University. The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ */
+
+#ifndef AUTH_H
+#define AUTH_H
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+void link_required (int); /* we are starting to use the link */
+void link_terminated (int); /* we are finished with the link */
+void link_down (int); /* the LCP layer has left the Opened state */
+void link_established (int); /* the link is up; authenticate now */
+void np_up (int, u16_t); /* a network protocol has come up */
+void np_down (int, u16_t); /* a network protocol has gone down */
+void np_finished (int, u16_t); /* a network protocol no longer needs link */
+void auth_peer_fail (int, u16_t);/* peer failed to authenticate itself */
+
+/* peer successfully authenticated itself */
+void auth_peer_success (int, u16_t, char *, int);
+
+/* we failed to authenticate ourselves */
+void auth_withpeer_fail (int, u16_t);
+
+/* we successfully authenticated ourselves */
+void auth_withpeer_success (int, u16_t);
+
+/* check authentication options supplied */
+void auth_check_options (void);
+void auth_reset (int); /* check what secrets we have */
+
+/* Check peer-supplied username/password */
+int check_passwd (int, char *, int, char *, int, char **, int *);
+
+/* get "secret" for chap */
+int get_secret (int, char *, char *, char *, int *, int);
+
+/* check if IP address is authorized */
+int auth_ip_addr (int, u32_t);
+
+/* check if IP address is unreasonable */
+int bad_ip_adrs (u32_t);
+
+
+#endif /* AUTH_H */
--- /dev/null
+/*** WARNING - THIS HAS NEVER BEEN FINISHED ***/
+/*****************************************************************************
+* chap.c - Network Challenge Handshake Authentication Protocol program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher <marc@mbsi.ca>
+* Ported to lwIP.
+* 97-12-04 Guy Lancaster <lancasterg@acm.org>, Global Election Systems Inc.
+* Original based on BSD chap.c.
+*****************************************************************************/
+/*
+ * chap.c - Challenge Handshake Authentication Protocol.
+ *
+ * Copyright (c) 1993 The Australian National University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by the Australian National University. The name of the University
+ * may not be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Copyright (c) 1991 Gregory M. Christy.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Gregory M. Christy. The name of the author may not be used to
+ * endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include "ppp.h"
+#if PPP_SUPPORT > 0
+#include "magic.h"
+
+#if CHAP_SUPPORT > 0
+
+#include "randm.h"
+#include "auth.h"
+#include "md5.h"
+#include "chap.h"
+#include "chpms.h"
+#include "pppdebug.h"
+
+
+/*************************/
+/*** LOCAL DEFINITIONS ***/
+/*************************/
+
+
+/************************/
+/*** LOCAL DATA TYPES ***/
+/************************/
+
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+/*
+ * Protocol entry points.
+ */
+static void ChapInit (int);
+static void ChapLowerUp (int);
+static void ChapLowerDown (int);
+static void ChapInput (int, u_char *, int);
+static void ChapProtocolReject (int);
+static int ChapPrintPkt (u_char *, int,
+ void (*) (void *, char *, ...), void *);
+
+static void ChapChallengeTimeout (void *);
+static void ChapResponseTimeout (void *);
+static void ChapReceiveChallenge (chap_state *, u_char *, int, int);
+static void ChapRechallenge (void *);
+static void ChapReceiveResponse (chap_state *, u_char *, int, int);
+static void ChapReceiveSuccess(chap_state *cstate, u_char *inp, u_char id, int len);
+static void ChapReceiveFailure(chap_state *cstate, u_char *inp, u_char id, int len);
+static void ChapSendStatus (chap_state *, int);
+static void ChapSendChallenge (chap_state *);
+static void ChapSendResponse (chap_state *);
+static void ChapGenChallenge (chap_state *);
+
+
+/******************************/
+/*** PUBLIC DATA STRUCTURES ***/
+/******************************/
+chap_state chap[NUM_PPP]; /* CHAP state; one for each unit */
+
+struct protent chap_protent = {
+ PPP_CHAP,
+ ChapInit,
+ ChapInput,
+ ChapProtocolReject,
+ ChapLowerUp,
+ ChapLowerDown,
+ NULL,
+ NULL,
+#if 0
+ ChapPrintPkt,
+ NULL,
+#endif
+ 1,
+ "CHAP",
+#if 0
+ NULL,
+ NULL,
+ NULL
+#endif
+};
+
+
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+static char *ChapCodenames[] = {
+ "Challenge", "Response", "Success", "Failure"
+};
+
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/*
+ * ChapAuthWithPeer - Authenticate us with our peer (start client).
+ *
+ */
+void ChapAuthWithPeer(int unit, char *our_name, int digest)
+{
+ chap_state *cstate = &chap[unit];
+
+ cstate->resp_name = our_name;
+ cstate->resp_type = digest;
+
+ if (cstate->clientstate == CHAPCS_INITIAL ||
+ cstate->clientstate == CHAPCS_PENDING) {
+ /* lower layer isn't up - wait until later */
+ cstate->clientstate = CHAPCS_PENDING;
+ return;
+ }
+
+ /*
+ * We get here as a result of LCP coming up.
+ * So even if CHAP was open before, we will
+ * have to re-authenticate ourselves.
+ */
+ cstate->clientstate = CHAPCS_LISTEN;
+}
+
+
+/*
+ * ChapAuthPeer - Authenticate our peer (start server).
+ */
+void ChapAuthPeer(int unit, char *our_name, int digest)
+{
+ chap_state *cstate = &chap[unit];
+
+ cstate->chal_name = our_name;
+ cstate->chal_type = digest;
+
+ if (cstate->serverstate == CHAPSS_INITIAL ||
+ cstate->serverstate == CHAPSS_PENDING) {
+ /* lower layer isn't up - wait until later */
+ cstate->serverstate = CHAPSS_PENDING;
+ return;
+ }
+
+ ChapGenChallenge(cstate);
+ ChapSendChallenge(cstate); /* crank it up dude! */
+ cstate->serverstate = CHAPSS_INITIAL_CHAL;
+}
+
+
+
+
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+/*
+ * ChapInit - Initialize a CHAP unit.
+ */
+static void ChapInit(int unit)
+{
+ chap_state *cstate = &chap[unit];
+
+ BZERO(cstate, sizeof(*cstate));
+ cstate->unit = unit;
+ cstate->clientstate = CHAPCS_INITIAL;
+ cstate->serverstate = CHAPSS_INITIAL;
+ cstate->timeouttime = CHAP_DEFTIMEOUT;
+ cstate->max_transmits = CHAP_DEFTRANSMITS;
+ /* random number generator is initialized in magic_init */
+}
+
+
+/*
+ * ChapChallengeTimeout - Timeout expired on sending challenge.
+ */
+static void ChapChallengeTimeout(void *arg)
+{
+ chap_state *cstate = (chap_state *) arg;
+
+ /* if we aren't sending challenges, don't worry. then again we */
+ /* probably shouldn't be here either */
+ if (cstate->serverstate != CHAPSS_INITIAL_CHAL &&
+ cstate->serverstate != CHAPSS_RECHALLENGE)
+ return;
+
+ if (cstate->chal_transmits >= cstate->max_transmits) {
+ /* give up on peer */
+ CHAPDEBUG((LOG_ERR, "Peer failed to respond to CHAP challenge\n"));
+ cstate->serverstate = CHAPSS_BADAUTH;
+ auth_peer_fail(cstate->unit, PPP_CHAP);
+ return;
+ }
+
+ ChapSendChallenge(cstate); /* Re-send challenge */
+}
+
+
+/*
+ * ChapResponseTimeout - Timeout expired on sending response.
+ */
+static void ChapResponseTimeout(void *arg)
+{
+ chap_state *cstate = (chap_state *) arg;
+
+ /* if we aren't sending a response, don't worry. */
+ if (cstate->clientstate != CHAPCS_RESPONSE)
+ return;
+
+ ChapSendResponse(cstate); /* re-send response */
+}
+
+
+/*
+ * ChapRechallenge - Time to challenge the peer again.
+ */
+static void ChapRechallenge(void *arg)
+{
+ chap_state *cstate = (chap_state *) arg;
+
+ /* if we aren't sending a response, don't worry. */
+ if (cstate->serverstate != CHAPSS_OPEN)
+ return;
+
+ ChapGenChallenge(cstate);
+ ChapSendChallenge(cstate);
+ cstate->serverstate = CHAPSS_RECHALLENGE;
+}
+
+
+/*
+ * ChapLowerUp - The lower layer is up.
+ *
+ * Start up if we have pending requests.
+ */
+static void ChapLowerUp(int unit)
+{
+ chap_state *cstate = &chap[unit];
+
+ if (cstate->clientstate == CHAPCS_INITIAL)
+ cstate->clientstate = CHAPCS_CLOSED;
+ else if (cstate->clientstate == CHAPCS_PENDING)
+ cstate->clientstate = CHAPCS_LISTEN;
+
+ if (cstate->serverstate == CHAPSS_INITIAL)
+ cstate->serverstate = CHAPSS_CLOSED;
+ else if (cstate->serverstate == CHAPSS_PENDING) {
+ ChapGenChallenge(cstate);
+ ChapSendChallenge(cstate);
+ cstate->serverstate = CHAPSS_INITIAL_CHAL;
+ }
+}
+
+
+/*
+ * ChapLowerDown - The lower layer is down.
+ *
+ * Cancel all timeouts.
+ */
+static void ChapLowerDown(int unit)
+{
+ chap_state *cstate = &chap[unit];
+
+ /* Timeout(s) pending? Cancel if so. */
+ if (cstate->serverstate == CHAPSS_INITIAL_CHAL ||
+ cstate->serverstate == CHAPSS_RECHALLENGE)
+ UNTIMEOUT(ChapChallengeTimeout, cstate);
+ else if (cstate->serverstate == CHAPSS_OPEN
+ && cstate->chal_interval != 0)
+ UNTIMEOUT(ChapRechallenge, cstate);
+ if (cstate->clientstate == CHAPCS_RESPONSE)
+ UNTIMEOUT(ChapResponseTimeout, cstate);
+
+ cstate->clientstate = CHAPCS_INITIAL;
+ cstate->serverstate = CHAPSS_INITIAL;
+}
+
+
+/*
+ * ChapProtocolReject - Peer doesn't grok CHAP.
+ */
+static void ChapProtocolReject(int unit)
+{
+ chap_state *cstate = &chap[unit];
+
+ if (cstate->serverstate != CHAPSS_INITIAL &&
+ cstate->serverstate != CHAPSS_CLOSED)
+ auth_peer_fail(unit, PPP_CHAP);
+ if (cstate->clientstate != CHAPCS_INITIAL &&
+ cstate->clientstate != CHAPCS_CLOSED)
+ auth_withpeer_fail(unit, PPP_CHAP);
+ ChapLowerDown(unit); /* shutdown chap */
+}
+
+
+/*
+ * ChapInput - Input CHAP packet.
+ */
+static void ChapInput(int unit, u_char *inpacket, int packet_len)
+{
+ chap_state *cstate = &chap[unit];
+ u_char *inp;
+ u_char code, id;
+ int len;
+
+ /*
+ * Parse header (code, id and length).
+ * If packet too short, drop it.
+ */
+ inp = inpacket;
+ if (packet_len < CHAP_HEADERLEN) {
+ CHAPDEBUG((LOG_INFO, "ChapInput: rcvd short header.\n"));
+ return;
+ }
+ GETCHAR(code, inp);
+ GETCHAR(id, inp);
+ GETSHORT(len, inp);
+ if (len < CHAP_HEADERLEN) {
+ CHAPDEBUG((LOG_INFO, "ChapInput: rcvd illegal length.\n"));
+ return;
+ }
+ if (len > packet_len) {
+ CHAPDEBUG((LOG_INFO, "ChapInput: rcvd short packet.\n"));
+ return;
+ }
+ len -= CHAP_HEADERLEN;
+
+ /*
+ * Action depends on code (as in fact it usually does :-).
+ */
+ switch (code) {
+ case CHAP_CHALLENGE:
+ ChapReceiveChallenge(cstate, inp, id, len);
+ break;
+
+ case CHAP_RESPONSE:
+ ChapReceiveResponse(cstate, inp, id, len);
+ break;
+
+ case CHAP_FAILURE:
+ ChapReceiveFailure(cstate, inp, id, len);
+ break;
+
+ case CHAP_SUCCESS:
+ ChapReceiveSuccess(cstate, inp, id, len);
+ break;
+
+ default: /* Need code reject? */
+ CHAPDEBUG((LOG_WARNING, "Unknown CHAP code (%d) received.\n", code));
+ break;
+ }
+}
+
+
+/*
+ * ChapReceiveChallenge - Receive Challenge and send Response.
+ */
+static void ChapReceiveChallenge(chap_state *cstate, u_char *inp, int id, int len)
+{
+ int rchallenge_len;
+ u_char *rchallenge;
+ int secret_len;
+ char secret[MAXSECRETLEN];
+ char rhostname[256];
+ MD5_CTX mdContext;
+ u_char hash[MD5_SIGNATURE_SIZE];
+
+ CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: Rcvd id %d.\n", id));
+ if (cstate->clientstate == CHAPCS_CLOSED ||
+ cstate->clientstate == CHAPCS_PENDING) {
+ CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: in state %d\n",
+ cstate->clientstate));
+ return;
+ }
+
+ if (len < 2) {
+ CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: rcvd short packet.\n"));
+ return;
+ }
+
+ GETCHAR(rchallenge_len, inp);
+ len -= sizeof (u_char) + rchallenge_len; /* now name field length */
+ if (len < 0) {
+ CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: rcvd short packet.\n"));
+ return;
+ }
+ rchallenge = inp;
+ INCPTR(rchallenge_len, inp);
+
+ if (len >= sizeof(rhostname))
+ len = sizeof(rhostname) - 1;
+ BCOPY(inp, rhostname, len);
+ rhostname[len] = '\000';
+
+ CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: received name field '%s'\n",
+ rhostname));
+
+ /* Microsoft doesn't send their name back in the PPP packet */
+ if (ppp_settings.remote_name[0] != 0 && (ppp_settings.explicit_remote || rhostname[0] == 0)) {
+ strncpy(rhostname, ppp_settings.remote_name, sizeof(rhostname));
+ rhostname[sizeof(rhostname) - 1] = 0;
+ CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: using '%s' as remote name\n",
+ rhostname));
+ }
+
+ /* get secret for authenticating ourselves with the specified host */
+ if (!get_secret(cstate->unit, cstate->resp_name, rhostname,
+ secret, &secret_len, 0)) {
+ secret_len = 0; /* assume null secret if can't find one */
+ CHAPDEBUG((LOG_WARNING, "No CHAP secret found for authenticating us to %s\n", rhostname));
+ }
+
+ /* cancel response send timeout if necessary */
+ if (cstate->clientstate == CHAPCS_RESPONSE)
+ UNTIMEOUT(ChapResponseTimeout, cstate);
+
+ cstate->resp_id = id;
+ cstate->resp_transmits = 0;
+
+ /* generate MD based on negotiated type */
+ switch (cstate->resp_type) {
+
+ case CHAP_DIGEST_MD5:
+ MD5Init(&mdContext);
+ MD5Update(&mdContext, &cstate->resp_id, 1);
+ MD5Update(&mdContext, (u_char*)secret, secret_len);
+ MD5Update(&mdContext, rchallenge, rchallenge_len);
+ MD5Final(hash, &mdContext);
+ BCOPY(hash, cstate->response, MD5_SIGNATURE_SIZE);
+ cstate->resp_length = MD5_SIGNATURE_SIZE;
+ break;
+
+#ifdef CHAPMS
+ case CHAP_MICROSOFT:
+ ChapMS(cstate, rchallenge, rchallenge_len, secret, secret_len);
+ break;
+#endif
+
+ default:
+ CHAPDEBUG((LOG_INFO, "unknown digest type %d\n", cstate->resp_type));
+ return;
+ }
+
+ BZERO(secret, sizeof(secret));
+ ChapSendResponse(cstate);
+}
+
+
+/*
+ * ChapReceiveResponse - Receive and process response.
+ */
+static void ChapReceiveResponse(chap_state *cstate, u_char *inp, int id, int len)
+{
+ u_char *remmd, remmd_len;
+ int secret_len, old_state;
+ int code;
+ char rhostname[256];
+ MD5_CTX mdContext;
+ char secret[MAXSECRETLEN];
+ u_char hash[MD5_SIGNATURE_SIZE];
+
+ CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: Rcvd id %d.\n", id));
+
+ if (cstate->serverstate == CHAPSS_CLOSED ||
+ cstate->serverstate == CHAPSS_PENDING) {
+ CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: in state %d\n",
+ cstate->serverstate));
+ return;
+ }
+
+ if (id != cstate->chal_id)
+ return; /* doesn't match ID of last challenge */
+
+ /*
+ * If we have received a duplicate or bogus Response,
+ * we have to send the same answer (Success/Failure)
+ * as we did for the first Response we saw.
+ */
+ if (cstate->serverstate == CHAPSS_OPEN) {
+ ChapSendStatus(cstate, CHAP_SUCCESS);
+ return;
+ }
+ if (cstate->serverstate == CHAPSS_BADAUTH) {
+ ChapSendStatus(cstate, CHAP_FAILURE);
+ return;
+ }
+
+ if (len < 2) {
+ CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: rcvd short packet.\n"));
+ return;
+ }
+ GETCHAR(remmd_len, inp); /* get length of MD */
+ remmd = inp; /* get pointer to MD */
+ INCPTR(remmd_len, inp);
+
+ len -= sizeof (u_char) + remmd_len;
+ if (len < 0) {
+ CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: rcvd short packet.\n"));
+ return;
+ }
+
+ UNTIMEOUT(ChapChallengeTimeout, cstate);
+
+ if (len >= sizeof(rhostname))
+ len = sizeof(rhostname) - 1;
+ BCOPY(inp, rhostname, len);
+ rhostname[len] = '\000';
+
+ CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: received name field: %s\n",
+ rhostname));
+
+ /*
+ * Get secret for authenticating them with us,
+ * do the hash ourselves, and compare the result.
+ */
+ code = CHAP_FAILURE;
+ if (!get_secret(cstate->unit, rhostname, cstate->chal_name,
+ secret, &secret_len, 1)) {
+/* CHAPDEBUG((LOG_WARNING, TL_CHAP, "No CHAP secret found for authenticating %s\n", rhostname)); */
+ CHAPDEBUG((LOG_WARNING, "No CHAP secret found for authenticating %s\n",
+ rhostname));
+ } else {
+
+ /* generate MD based on negotiated type */
+ switch (cstate->chal_type) {
+
+ case CHAP_DIGEST_MD5: /* only MD5 is defined for now */
+ if (remmd_len != MD5_SIGNATURE_SIZE)
+ break; /* it's not even the right length */
+ MD5Init(&mdContext);
+ MD5Update(&mdContext, &cstate->chal_id, 1);
+ MD5Update(&mdContext, (u_char*)secret, secret_len);
+ MD5Update(&mdContext, cstate->challenge, cstate->chal_len);
+ MD5Final(hash, &mdContext);
+
+ /* compare local and remote MDs and send the appropriate status */
+ if (memcmp (hash, remmd, MD5_SIGNATURE_SIZE) == 0)
+ code = CHAP_SUCCESS; /* they are the same! */
+ break;
+
+ default:
+ CHAPDEBUG((LOG_INFO, "unknown digest type %d\n", cstate->chal_type));
+ }
+ }
+
+ BZERO(secret, sizeof(secret));
+ ChapSendStatus(cstate, code);
+
+ if (code == CHAP_SUCCESS) {
+ old_state = cstate->serverstate;
+ cstate->serverstate = CHAPSS_OPEN;
+ if (old_state == CHAPSS_INITIAL_CHAL) {
+ auth_peer_success(cstate->unit, PPP_CHAP, rhostname, len);
+ }
+ if (cstate->chal_interval != 0)
+ TIMEOUT(ChapRechallenge, cstate, cstate->chal_interval);
+ } else {
+ CHAPDEBUG((LOG_ERR, "CHAP peer authentication failed\n"));
+ cstate->serverstate = CHAPSS_BADAUTH;
+ auth_peer_fail(cstate->unit, PPP_CHAP);
+ }
+}
+
+/*
+ * ChapReceiveSuccess - Receive Success
+ */
+static void ChapReceiveSuccess(chap_state *cstate, u_char *inp, u_char id, int len)
+{
+
+ CHAPDEBUG((LOG_INFO, "ChapReceiveSuccess: Rcvd id %d.\n", id));
+
+ if (cstate->clientstate == CHAPCS_OPEN)
+ /* presumably an answer to a duplicate response */
+ return;
+
+ if (cstate->clientstate != CHAPCS_RESPONSE) {
+ /* don't know what this is */
+ CHAPDEBUG((LOG_INFO, "ChapReceiveSuccess: in state %d\n",
+ cstate->clientstate));
+ return;
+ }
+
+ UNTIMEOUT(ChapResponseTimeout, cstate);
+
+ /*
+ * Print message.
+ */
+ if (len > 0)
+ PRINTMSG(inp, len);
+
+ cstate->clientstate = CHAPCS_OPEN;
+
+ auth_withpeer_success(cstate->unit, PPP_CHAP);
+}
+
+
+/*
+ * ChapReceiveFailure - Receive failure.
+ */
+static void ChapReceiveFailure(chap_state *cstate, u_char *inp, u_char id, int len)
+{
+ CHAPDEBUG((LOG_INFO, "ChapReceiveFailure: Rcvd id %d.\n", id));
+
+ if (cstate->clientstate != CHAPCS_RESPONSE) {
+ /* don't know what this is */
+ CHAPDEBUG((LOG_INFO, "ChapReceiveFailure: in state %d\n",
+ cstate->clientstate));
+ return;
+ }
+
+ UNTIMEOUT(ChapResponseTimeout, cstate);
+
+ /*
+ * Print message.
+ */
+ if (len > 0)
+ PRINTMSG(inp, len);
+
+ CHAPDEBUG((LOG_ERR, "CHAP authentication failed\n"));
+ auth_withpeer_fail(cstate->unit, PPP_CHAP);
+}
+
+
+/*
+ * ChapSendChallenge - Send an Authenticate challenge.
+ */
+static void ChapSendChallenge(chap_state *cstate)
+{
+ u_char *outp;
+ int chal_len, name_len;
+ int outlen;
+
+ chal_len = cstate->chal_len;
+ name_len = strlen(cstate->chal_name);
+ outlen = CHAP_HEADERLEN + sizeof (u_char) + chal_len + name_len;
+ outp = outpacket_buf[cstate->unit];
+
+ MAKEHEADER(outp, PPP_CHAP); /* paste in a CHAP header */
+
+ PUTCHAR(CHAP_CHALLENGE, outp);
+ PUTCHAR(cstate->chal_id, outp);
+ PUTSHORT(outlen, outp);
+
+ PUTCHAR(chal_len, outp); /* put length of challenge */
+ BCOPY(cstate->challenge, outp, chal_len);
+ INCPTR(chal_len, outp);
+
+ BCOPY(cstate->chal_name, outp, name_len); /* append hostname */
+
+ pppWrite(cstate->unit, outpacket_buf[cstate->unit], outlen + PPP_HDRLEN);
+
+ CHAPDEBUG((LOG_INFO, "ChapSendChallenge: Sent id %d.\n", cstate->chal_id));
+
+ TIMEOUT(ChapChallengeTimeout, cstate, cstate->timeouttime);
+ ++cstate->chal_transmits;
+}
+
+
+/*
+ * ChapSendStatus - Send a status response (ack or nak).
+ */
+static void ChapSendStatus(chap_state *cstate, int code)
+{
+ u_char *outp;
+ int outlen, msglen;
+ char msg[256];
+
+ if (code == CHAP_SUCCESS)
+ strcpy(msg, "Welcome!");
+ else
+ strcpy(msg, "I don't like you. Go 'way.");
+ msglen = strlen(msg);
+
+ outlen = CHAP_HEADERLEN + msglen;
+ outp = outpacket_buf[cstate->unit];
+
+ MAKEHEADER(outp, PPP_CHAP); /* paste in a header */
+
+ PUTCHAR(code, outp);
+ PUTCHAR(cstate->chal_id, outp);
+ PUTSHORT(outlen, outp);
+ BCOPY(msg, outp, msglen);
+ pppWrite(cstate->unit, outpacket_buf[cstate->unit], outlen + PPP_HDRLEN);
+
+ CHAPDEBUG((LOG_INFO, "ChapSendStatus: Sent code %d, id %d.\n", code,
+ cstate->chal_id));
+}
+
+/*
+ * ChapGenChallenge is used to generate a pseudo-random challenge string of
+ * a pseudo-random length between min_len and max_len. The challenge
+ * string and its length are stored in *cstate, and various other fields of
+ * *cstate are initialized.
+ */
+
+static void ChapGenChallenge(chap_state *cstate)
+{
+ int chal_len;
+ u_char *ptr = cstate->challenge;
+ int i;
+
+ /* pick a random challenge length between MIN_CHALLENGE_LENGTH and
+ MAX_CHALLENGE_LENGTH */
+ chal_len = (unsigned)
+ ((((magic() >> 16) *
+ (MAX_CHALLENGE_LENGTH - MIN_CHALLENGE_LENGTH)) >> 16)
+ + MIN_CHALLENGE_LENGTH);
+ cstate->chal_len = chal_len;
+ cstate->chal_id = ++cstate->id;
+ cstate->chal_transmits = 0;
+
+ /* generate a random string */
+ for (i = 0; i < chal_len; i++ )
+ *ptr++ = (char) (magic() & 0xff);
+}
+
+/*
+ * ChapSendResponse - send a response packet with values as specified
+ * in *cstate.
+ */
+/* ARGSUSED */
+static void ChapSendResponse(chap_state *cstate)
+{
+ u_char *outp;
+ int outlen, md_len, name_len;
+
+ md_len = cstate->resp_length;
+ name_len = strlen(cstate->resp_name);
+ outlen = CHAP_HEADERLEN + sizeof (u_char) + md_len + name_len;
+ outp = outpacket_buf[cstate->unit];
+
+ MAKEHEADER(outp, PPP_CHAP);
+
+ PUTCHAR(CHAP_RESPONSE, outp); /* we are a response */
+ PUTCHAR(cstate->resp_id, outp); /* copy id from challenge packet */
+ PUTSHORT(outlen, outp); /* packet length */
+
+ PUTCHAR(md_len, outp); /* length of MD */
+ BCOPY(cstate->response, outp, md_len); /* copy MD to buffer */
+ INCPTR(md_len, outp);
+
+ BCOPY(cstate->resp_name, outp, name_len); /* append our name */
+
+ /* send the packet */
+ pppWrite(cstate->unit, outpacket_buf[cstate->unit], outlen + PPP_HDRLEN);
+
+ cstate->clientstate = CHAPCS_RESPONSE;
+ TIMEOUT(ChapResponseTimeout, cstate, cstate->timeouttime);
+ ++cstate->resp_transmits;
+}
+
+/*
+ * ChapPrintPkt - print the contents of a CHAP packet.
+ */
+static int ChapPrintPkt(
+ u_char *p,
+ int plen,
+ void (*printer) (void *, char *, ...),
+ void *arg
+)
+{
+ int code, id, len;
+ int clen, nlen;
+ u_char x;
+
+ if (plen < CHAP_HEADERLEN)
+ return 0;
+ GETCHAR(code, p);
+ GETCHAR(id, p);
+ GETSHORT(len, p);
+ if (len < CHAP_HEADERLEN || len > plen)
+ return 0;
+
+ if (code >= 1 && code <= sizeof(ChapCodenames) / sizeof(char *))
+ printer(arg, " %s", ChapCodenames[code-1]);
+ else
+ printer(arg, " code=0x%x", code);
+ printer(arg, " id=0x%x", id);
+ len -= CHAP_HEADERLEN;
+ switch (code) {
+ case CHAP_CHALLENGE:
+ case CHAP_RESPONSE:
+ if (len < 1)
+ break;
+ clen = p[0];
+ if (len < clen + 1)
+ break;
+ ++p;
+ nlen = len - clen - 1;
+ printer(arg, " <");
+ for (; clen > 0; --clen) {
+ GETCHAR(x, p);
+ printer(arg, "%.2x", x);
+ }
+ printer(arg, ">, name = %.*Z", nlen, p);
+ break;
+ case CHAP_FAILURE:
+ case CHAP_SUCCESS:
+ printer(arg, " %.*Z", len, p);
+ break;
+ default:
+ for (clen = len; clen > 0; --clen) {
+ GETCHAR(x, p);
+ printer(arg, " %.2x", x);
+ }
+ }
+
+ return len + CHAP_HEADERLEN;
+}
+
+#endif
+
+#endif /* PPP_SUPPORT */
--- /dev/null
+/*****************************************************************************
+* chap.h - Network Challenge Handshake Authentication Protocol header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1998 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher <marc@mbsi.ca>
+* Ported to lwIP.
+* 97-12-03 Guy Lancaster <lancasterg@acm.org>, Global Election Systems Inc.
+* Original built from BSD network code.
+******************************************************************************/
+/*
+ * chap.h - Challenge Handshake Authentication Protocol definitions.
+ *
+ * Copyright (c) 1993 The Australian National University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by the Australian National University. The name of the University
+ * may not be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Copyright (c) 1991 Gregory M. Christy
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by the author.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * $Id: chap.h,v 1.1 2003/05/27 14:37:56 jani Exp $
+ */
+
+#ifndef CHAP_H
+#define CHAP_H
+
+/*************************
+*** PUBLIC DEFINITIONS ***
+*************************/
+
+/* Code + ID + length */
+#define CHAP_HEADERLEN 4
+
+/*
+ * CHAP codes.
+ */
+
+#define CHAP_DIGEST_MD5 5 /* use MD5 algorithm */
+#define MD5_SIGNATURE_SIZE 16 /* 16 bytes in a MD5 message digest */
+#define CHAP_MICROSOFT 0x80 /* use Microsoft-compatible alg. */
+#define MS_CHAP_RESPONSE_LEN 49 /* Response length for MS-CHAP */
+
+#define CHAP_CHALLENGE 1
+#define CHAP_RESPONSE 2
+#define CHAP_SUCCESS 3
+#define CHAP_FAILURE 4
+
+/*
+ * Challenge lengths (for challenges we send) and other limits.
+ */
+#define MIN_CHALLENGE_LENGTH 32
+#define MAX_CHALLENGE_LENGTH 64
+#define MAX_RESPONSE_LENGTH 64 /* sufficient for MD5 or MS-CHAP */
+
+/*
+ * Client (peer) states.
+ */
+#define CHAPCS_INITIAL 0 /* Lower layer down, not opened */
+#define CHAPCS_CLOSED 1 /* Lower layer up, not opened */
+#define CHAPCS_PENDING 2 /* Auth us to peer when lower up */
+#define CHAPCS_LISTEN 3 /* Listening for a challenge */
+#define CHAPCS_RESPONSE 4 /* Sent response, waiting for status */
+#define CHAPCS_OPEN 5 /* We've received Success */
+
+/*
+ * Server (authenticator) states.
+ */
+#define CHAPSS_INITIAL 0 /* Lower layer down, not opened */
+#define CHAPSS_CLOSED 1 /* Lower layer up, not opened */
+#define CHAPSS_PENDING 2 /* Auth peer when lower up */
+#define CHAPSS_INITIAL_CHAL 3 /* We've sent the first challenge */
+#define CHAPSS_OPEN 4 /* We've sent a Success msg */
+#define CHAPSS_RECHALLENGE 5 /* We've sent another challenge */
+#define CHAPSS_BADAUTH 6 /* We've sent a Failure msg */
+
+/************************
+*** PUBLIC DATA TYPES ***
+************************/
+
+/*
+ * Each interface is described by a chap structure.
+ */
+
+typedef struct chap_state {
+ int unit; /* Interface unit number */
+ int clientstate; /* Client state */
+ int serverstate; /* Server state */
+ u_char challenge[MAX_CHALLENGE_LENGTH]; /* last challenge string sent */
+ u_char chal_len; /* challenge length */
+ u_char chal_id; /* ID of last challenge */
+ u_char chal_type; /* hash algorithm for challenges */
+ u_char id; /* Current id */
+ char *chal_name; /* Our name to use with challenge */
+ int chal_interval; /* Time until we challenge peer again */
+ int timeouttime; /* Timeout time in seconds */
+ int max_transmits; /* Maximum # of challenge transmissions */
+ int chal_transmits; /* Number of transmissions of challenge */
+ int resp_transmits; /* Number of transmissions of response */
+ u_char response[MAX_RESPONSE_LENGTH]; /* Response to send */
+ u_char resp_length; /* length of response */
+ u_char resp_id; /* ID for response messages */
+ u_char resp_type; /* hash algorithm for responses */
+ char *resp_name; /* Our name to send with response */
+} chap_state;
+
+
+/******************
+*** PUBLIC DATA ***
+******************/
+extern chap_state chap[];
+
+extern struct protent chap_protent;
+
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+
+void ChapAuthWithPeer (int, char *, int);
+void ChapAuthPeer (int, char *, int);
+
+#endif /* CHAP_H */
+
--- /dev/null
+/*** WARNING - THIS CODE HAS NOT BEEN FINISHED! ***/
+/*****************************************************************************
+* chpms.c - Network MicroSoft Challenge Handshake Authentication Protocol program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* Copyright (c) 1997 by Global Election Systems Inc. All rights reserved.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher <marc@mbsi.ca>
+* Ported to lwIP.
+* 97-12-08 Guy Lancaster <lancasterg@acm.org>, Global Election Systems Inc.
+* Original based on BSD chap_ms.c.
+*****************************************************************************/
+/*
+ * chap_ms.c - Microsoft MS-CHAP compatible implementation.
+ *
+ * Copyright (c) 1995 Eric Rosenquist, Strata Software Limited.
+ * http://www.strataware.com/
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Eric Rosenquist. The name of the author may not be used to
+ * endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+/*
+ * Modifications by Lauri Pesonen / lpesonen@clinet.fi, april 1997
+ *
+ * Implemented LANManager type password response to MS-CHAP challenges.
+ * Now pppd provides both NT style and LANMan style blocks, and the
+ * prefered is set by option "ms-lanman". Default is to use NT.
+ * The hash text (StdText) was taken from Win95 RASAPI32.DLL.
+ *
+ * You should also use DOMAIN\\USERNAME as described in README.MSCHAP80
+ */
+
+#define USE_CRYPT
+
+
+#include "ppp.h"
+
+#if MSCHAP_SUPPORT > 0
+
+#include "md4.h"
+#ifndef USE_CRYPT
+#include "des.h"
+#endif
+#include "chap.h"
+#include "chpms.h"
+#include "pppdebug.h"
+
+
+/*************************/
+/*** LOCAL DEFINITIONS ***/
+/*************************/
+
+
+/************************/
+/*** LOCAL DATA TYPES ***/
+/************************/
+typedef struct {
+ u_char LANManResp[24];
+ u_char NTResp[24];
+ u_char UseNT; /* If 1, ignore the LANMan response field */
+} MS_ChapResponse;
+/* We use MS_CHAP_RESPONSE_LEN, rather than sizeof(MS_ChapResponse),
+ in case this struct gets padded. */
+
+
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+
+/* XXX Don't know what to do with these. */
+extern void setkey(const char *);
+extern void encrypt(char *, int);
+
+static void DesEncrypt (u_char *, u_char *, u_char *);
+static void MakeKey (u_char *, u_char *);
+
+#ifdef USE_CRYPT
+static void Expand (u_char *, u_char *);
+static void Collapse (u_char *, u_char *);
+#endif
+
+static void ChallengeResponse(
+ u_char *challenge, /* IN 8 octets */
+ u_char *pwHash, /* IN 16 octets */
+ u_char *response /* OUT 24 octets */
+);
+static void ChapMS_NT(
+ char *rchallenge,
+ int rchallenge_len,
+ char *secret,
+ int secret_len,
+ MS_ChapResponse *response
+);
+static u_char Get7Bits(
+ u_char *input,
+ int startBit
+);
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+void ChapMS(
+ chap_state *cstate,
+ char *rchallenge,
+ int rchallenge_len,
+ char *secret,
+ int secret_len
+)
+{
+ MS_ChapResponse response;
+#ifdef MSLANMAN
+ extern int ms_lanman;
+#endif
+
+#if 0
+ CHAPDEBUG((LOG_INFO, "ChapMS: secret is '%.*s'\n", secret_len, secret));
+#endif
+ BZERO(&response, sizeof(response));
+
+ /* Calculate both always */
+ ChapMS_NT(rchallenge, rchallenge_len, secret, secret_len, &response);
+
+#ifdef MSLANMAN
+ ChapMS_LANMan(rchallenge, rchallenge_len, secret, secret_len, &response);
+
+ /* prefered method is set by option */
+ response.UseNT = !ms_lanman;
+#else
+ response.UseNT = 1;
+#endif
+
+ BCOPY(&response, cstate->response, MS_CHAP_RESPONSE_LEN);
+ cstate->resp_length = MS_CHAP_RESPONSE_LEN;
+}
+
+
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+static void ChallengeResponse(
+ u_char *challenge, /* IN 8 octets */
+ u_char *pwHash, /* IN 16 octets */
+ u_char *response /* OUT 24 octets */
+)
+{
+ char ZPasswordHash[21];
+
+ BZERO(ZPasswordHash, sizeof(ZPasswordHash));
+ BCOPY(pwHash, ZPasswordHash, 16);
+
+#if 0
+ log_packet(ZPasswordHash, sizeof(ZPasswordHash), "ChallengeResponse - ZPasswordHash", LOG_DEBUG);
+#endif
+
+ DesEncrypt(challenge, ZPasswordHash + 0, response + 0);
+ DesEncrypt(challenge, ZPasswordHash + 7, response + 8);
+ DesEncrypt(challenge, ZPasswordHash + 14, response + 16);
+
+#if 0
+ log_packet(response, 24, "ChallengeResponse - response", LOG_DEBUG);
+#endif
+}
+
+
+#ifdef USE_CRYPT
+static void DesEncrypt(
+ u_char *clear, /* IN 8 octets */
+ u_char *key, /* IN 7 octets */
+ u_char *cipher /* OUT 8 octets */
+)
+{
+ u_char des_key[8];
+ u_char crypt_key[66];
+ u_char des_input[66];
+
+ MakeKey(key, des_key);
+
+ Expand(des_key, crypt_key);
+ setkey(crypt_key);
+
+#if 0
+ CHAPDEBUG((LOG_INFO, "DesEncrypt: 8 octet input : %02X%02X%02X%02X%02X%02X%02X%02X\n",
+ clear[0], clear[1], clear[2], clear[3], clear[4], clear[5], clear[6], clear[7]));
+#endif
+
+ Expand(clear, des_input);
+ encrypt(des_input, 0);
+ Collapse(des_input, cipher);
+
+#if 0
+ CHAPDEBUG((LOG_INFO, "DesEncrypt: 8 octet output: %02X%02X%02X%02X%02X%02X%02X%02X\n",
+ cipher[0], cipher[1], cipher[2], cipher[3], cipher[4], cipher[5], cipher[6], cipher[7]));
+#endif
+}
+
+#else /* USE_CRYPT */
+
+static void DesEncrypt(
+ u_char *clear, /* IN 8 octets */
+ u_char *key, /* IN 7 octets */
+ u_char *cipher /* OUT 8 octets */
+)
+{
+ des_cblock des_key;
+ des_key_schedule key_schedule;
+
+ MakeKey(key, des_key);
+
+ des_set_key(&des_key, key_schedule);
+
+#if 0
+ CHAPDEBUG((LOG_INFO, "DesEncrypt: 8 octet input : %02X%02X%02X%02X%02X%02X%02X%02X\n",
+ clear[0], clear[1], clear[2], clear[3], clear[4], clear[5], clear[6], clear[7]));
+#endif
+
+ des_ecb_encrypt((des_cblock *)clear, (des_cblock *)cipher, key_schedule, 1);
+
+#if 0
+ CHAPDEBUG((LOG_INFO, "DesEncrypt: 8 octet output: %02X%02X%02X%02X%02X%02X%02X%02X\n",
+ cipher[0], cipher[1], cipher[2], cipher[3], cipher[4], cipher[5], cipher[6], cipher[7]));
+#endif
+}
+
+#endif /* USE_CRYPT */
+
+
+static u_char Get7Bits(
+ u_char *input,
+ int startBit
+)
+{
+ register unsigned int word;
+
+ word = (unsigned)input[startBit / 8] << 8;
+ word |= (unsigned)input[startBit / 8 + 1];
+
+ word >>= 15 - (startBit % 8 + 7);
+
+ return word & 0xFE;
+}
+
+#ifdef USE_CRYPT
+
+/* in == 8-byte string (expanded version of the 56-bit key)
+ * out == 64-byte string where each byte is either 1 or 0
+ * Note that the low-order "bit" is always ignored by by setkey()
+ */
+static void Expand(u_char *in, u_char *out)
+{
+ int j, c;
+ int i;
+
+ for(i = 0; i < 64; in++){
+ c = *in;
+ for(j = 7; j >= 0; j--)
+ *out++ = (c >> j) & 01;
+ i += 8;
+ }
+}
+
+/* The inverse of Expand
+ */
+static void Collapse(u_char *in, u_char *out)
+{
+ int j;
+ int i;
+ unsigned int c;
+
+ for (i = 0; i < 64; i += 8, out++) {
+ c = 0;
+ for (j = 7; j >= 0; j--, in++)
+ c |= *in << j;
+ *out = c & 0xff;
+ }
+}
+#endif
+
+static void MakeKey(
+ u_char *key, /* IN 56 bit DES key missing parity bits */
+ u_char *des_key /* OUT 64 bit DES key with parity bits added */
+)
+{
+ des_key[0] = Get7Bits(key, 0);
+ des_key[1] = Get7Bits(key, 7);
+ des_key[2] = Get7Bits(key, 14);
+ des_key[3] = Get7Bits(key, 21);
+ des_key[4] = Get7Bits(key, 28);
+ des_key[5] = Get7Bits(key, 35);
+ des_key[6] = Get7Bits(key, 42);
+ des_key[7] = Get7Bits(key, 49);
+
+#ifndef USE_CRYPT
+ des_set_odd_parity((des_cblock *)des_key);
+#endif
+
+#if 0
+ CHAPDEBUG((LOG_INFO, "MakeKey: 56-bit input : %02X%02X%02X%02X%02X%02X%02X\n",
+ key[0], key[1], key[2], key[3], key[4], key[5], key[6]));
+ CHAPDEBUG((LOG_INFO, "MakeKey: 64-bit output: %02X%02X%02X%02X%02X%02X%02X%02X\n",
+ des_key[0], des_key[1], des_key[2], des_key[3], des_key[4], des_key[5], des_key[6], des_key[7]));
+#endif
+}
+
+static void ChapMS_NT(
+ char *rchallenge,
+ int rchallenge_len,
+ char *secret,
+ int secret_len,
+ MS_ChapResponse *response
+)
+{
+ int i;
+ MDstruct md4Context;
+ u_char unicodePassword[MAX_NT_PASSWORD * 2];
+ static int low_byte_first = -1;
+
+ /* Initialize the Unicode version of the secret (== password). */
+ /* This implicitly supports 8-bit ISO8859/1 characters. */
+ BZERO(unicodePassword, sizeof(unicodePassword));
+ for (i = 0; i < secret_len; i++)
+ unicodePassword[i * 2] = (u_char)secret[i];
+
+ MDbegin(&md4Context);
+ MDupdate(&md4Context, unicodePassword, secret_len * 2 * 8); /* Unicode is 2 bytes/char, *8 for bit count */
+
+ if (low_byte_first == -1)
+ low_byte_first = (htons((unsigned short int)1) != 1);
+ if (low_byte_first == 0)
+ MDreverse((u_long *)&md4Context); /* sfb 961105 */
+
+ MDupdate(&md4Context, NULL, 0); /* Tell MD4 we're done */
+
+ ChallengeResponse(rchallenge, (char *)md4Context.buffer, response->NTResp);
+}
+
+#ifdef MSLANMAN
+static u_char *StdText = (u_char *)"KGS!@#$%"; /* key from rasapi32.dll */
+
+static ChapMS_LANMan(
+ char *rchallenge,
+ int rchallenge_len,
+ char *secret,
+ int secret_len,
+ MS_ChapResponse *response
+)
+{
+ int i;
+ u_char UcasePassword[MAX_NT_PASSWORD]; /* max is actually 14 */
+ u_char PasswordHash[16];
+
+ /* LANMan password is case insensitive */
+ BZERO(UcasePassword, sizeof(UcasePassword));
+ for (i = 0; i < secret_len; i++)
+ UcasePassword[i] = (u_char)toupper(secret[i]);
+ DesEncrypt( StdText, UcasePassword + 0, PasswordHash + 0 );
+ DesEncrypt( StdText, UcasePassword + 7, PasswordHash + 8 );
+ ChallengeResponse(rchallenge, PasswordHash, response->LANManResp);
+}
+#endif
+
+#endif /* MSCHAP_SUPPORT */
+
--- /dev/null
+/*****************************************************************************
+* chpms.h - Network Microsoft Challenge Handshake Protocol header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1998 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher <marc@mbsi.ca>
+* Ported to lwIP.
+* 98-01-30 Guy Lancaster <lancasterg@acm.org>, Global Election Systems Inc.
+* Original built from BSD network code.
+******************************************************************************/
+/*
+ * chap.h - Challenge Handshake Authentication Protocol definitions.
+ *
+ * Copyright (c) 1995 Eric Rosenquist, Strata Software Limited.
+ * http://www.strataware.com/
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Eric Rosenquist. The name of the author may not be used to
+ * endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * $Id: chpms.h,v 1.3 2004/02/07 00:30:03 likewise Exp $
+ */
+
+#ifndef CHPMS_H
+#define CHPMS_H
+
+#define MAX_NT_PASSWORD 256 /* Maximum number of (Unicode) chars in an NT password */
+
+void ChapMS (chap_state *, char *, int, char *, int);
+
+#endif /* CHPMS_H */
--- /dev/null
+/*****************************************************************************
+* fsm.c - Network Control Protocol Finite State Machine program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher <marc@mbsi.ca>
+* Ported to lwIP.
+* 97-12-01 Guy Lancaster <lancasterg@acm.org>, Global Election Systems Inc.
+* Original based on BSD fsm.c.
+*****************************************************************************/
+/*
+ * fsm.c - {Link, IP} Control Protocol Finite State Machine.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University. The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+
+/*
+ * TODO:
+ * Randomize fsm id on link/init.
+ * Deal with variable outgoing MTU.
+ */
+
+#include "ppp.h"
+#if PPP_SUPPORT > 0
+#include "fsm.h"
+#include "pppdebug.h"
+
+
+/*************************/
+/*** LOCAL DEFINITIONS ***/
+/*************************/
+
+
+/************************/
+/*** LOCAL DATA TYPES ***/
+/************************/
+
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+static void fsm_timeout (void *);
+static void fsm_rconfreq (fsm *, u_char, u_char *, int);
+static void fsm_rconfack (fsm *, int, u_char *, int);
+static void fsm_rconfnakrej (fsm *, int, int, u_char *, int);
+static void fsm_rtermreq (fsm *, int, u_char *, int);
+static void fsm_rtermack (fsm *);
+static void fsm_rcoderej (fsm *, u_char *, int);
+static void fsm_sconfreq (fsm *, int);
+
+#define PROTO_NAME(f) ((f)->callbacks->proto_name)
+
+
+/******************************/
+/*** PUBLIC DATA STRUCTURES ***/
+/******************************/
+
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+int peer_mru[NUM_PPP];
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+
+/*
+ * fsm_init - Initialize fsm.
+ *
+ * Initialize fsm state.
+ */
+void fsm_init(fsm *f)
+{
+ f->state = INITIAL;
+ f->flags = 0;
+ f->id = 0; /* XXX Start with random id? */
+ f->timeouttime = FSM_DEFTIMEOUT;
+ f->maxconfreqtransmits = FSM_DEFMAXCONFREQS;
+ f->maxtermtransmits = FSM_DEFMAXTERMREQS;
+ f->maxnakloops = FSM_DEFMAXNAKLOOPS;
+ f->term_reason_len = 0;
+}
+
+
+/*
+ * fsm_lowerup - The lower layer is up.
+ */
+void fsm_lowerup(fsm *f)
+{
+ int oldState = f->state;
+
+ switch( f->state ){
+ case INITIAL:
+ f->state = CLOSED;
+ break;
+
+ case STARTING:
+ if( f->flags & OPT_SILENT )
+ f->state = STOPPED;
+ else {
+ /* Send an initial configure-request */
+ fsm_sconfreq(f, 0);
+ f->state = REQSENT;
+ }
+ break;
+
+ default:
+ FSMDEBUG((LOG_INFO, "%s: Up event in state %d!\n",
+ PROTO_NAME(f), f->state));
+ }
+
+ FSMDEBUG((LOG_INFO, "%s: lowerup state %d -> %d\n",
+ PROTO_NAME(f), oldState, f->state));
+}
+
+
+/*
+ * fsm_lowerdown - The lower layer is down.
+ *
+ * Cancel all timeouts and inform upper layers.
+ */
+void fsm_lowerdown(fsm *f)
+{
+ int oldState = f->state;
+
+ switch( f->state ){
+ case CLOSED:
+ f->state = INITIAL;
+ break;
+
+ case STOPPED:
+ f->state = STARTING;
+ if( f->callbacks->starting )
+ (*f->callbacks->starting)(f);
+ break;
+
+ case CLOSING:
+ f->state = INITIAL;
+ UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */
+ break;
+
+ case STOPPING:
+ case REQSENT:
+ case ACKRCVD:
+ case ACKSENT:
+ f->state = STARTING;
+ UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */
+ break;
+
+ case OPENED:
+ if( f->callbacks->down )
+ (*f->callbacks->down)(f);
+ f->state = STARTING;
+ break;
+
+ default:
+ FSMDEBUG((LOG_INFO, "%s: Down event in state %d!\n",
+ PROTO_NAME(f), f->state));
+ }
+
+ FSMDEBUG((LOG_INFO, "%s: lowerdown state %d -> %d\n",
+ PROTO_NAME(f), oldState, f->state));
+}
+
+
+/*
+ * fsm_open - Link is allowed to come up.
+ */
+void fsm_open(fsm *f)
+{
+ int oldState = f->state;
+
+ switch( f->state ){
+ case INITIAL:
+ f->state = STARTING;
+ if( f->callbacks->starting )
+ (*f->callbacks->starting)(f);
+ break;
+
+ case CLOSED:
+ if( f->flags & OPT_SILENT )
+ f->state = STOPPED;
+ else {
+ /* Send an initial configure-request */
+ fsm_sconfreq(f, 0);
+ f->state = REQSENT;
+ }
+ break;
+
+ case CLOSING:
+ f->state = STOPPING;
+ /* fall through */
+ case STOPPED:
+ case OPENED:
+ if( f->flags & OPT_RESTART ){
+ fsm_lowerdown(f);
+ fsm_lowerup(f);
+ }
+ break;
+ }
+
+ FSMDEBUG((LOG_INFO, "%s: open state %d -> %d\n",
+ PROTO_NAME(f), oldState, f->state));
+}
+
+
+/*
+ * fsm_close - Start closing connection.
+ *
+ * Cancel timeouts and either initiate close or possibly go directly to
+ * the CLOSED state.
+ */
+void fsm_close(fsm *f, char *reason)
+{
+ int oldState = f->state;
+
+ f->term_reason = reason;
+ f->term_reason_len = (reason == NULL? 0: strlen(reason));
+ switch( f->state ){
+ case STARTING:
+ f->state = INITIAL;
+ break;
+ case STOPPED:
+ f->state = CLOSED;
+ break;
+ case STOPPING:
+ f->state = CLOSING;
+ break;
+
+ case REQSENT:
+ case ACKRCVD:
+ case ACKSENT:
+ case OPENED:
+ if( f->state != OPENED )
+ UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */
+ else if( f->callbacks->down )
+ (*f->callbacks->down)(f); /* Inform upper layers we're down */
+
+ /* Init restart counter, send Terminate-Request */
+ f->retransmits = f->maxtermtransmits;
+ fsm_sdata(f, TERMREQ, f->reqid = ++f->id,
+ (u_char *) f->term_reason, f->term_reason_len);
+ TIMEOUT(fsm_timeout, f, f->timeouttime);
+ --f->retransmits;
+
+ f->state = CLOSING;
+ break;
+ }
+
+ FSMDEBUG((LOG_INFO, "%s: close reason=%s state %d -> %d\n",
+ PROTO_NAME(f), reason, oldState, f->state));
+}
+
+
+/*
+ * fsm_sdata - Send some data.
+ *
+ * Used for all packets sent to our peer by this module.
+ */
+void fsm_sdata(
+ fsm *f,
+ u_char code,
+ u_char id,
+ u_char *data,
+ int datalen
+)
+{
+ u_char *outp;
+ int outlen;
+
+ /* Adjust length to be smaller than MTU */
+ outp = outpacket_buf[f->unit];
+ if (datalen > peer_mru[f->unit] - (int)HEADERLEN)
+ datalen = peer_mru[f->unit] - HEADERLEN;
+ if (datalen && data != outp + PPP_HDRLEN + HEADERLEN)
+ BCOPY(data, outp + PPP_HDRLEN + HEADERLEN, datalen);
+ outlen = datalen + HEADERLEN;
+ MAKEHEADER(outp, f->protocol);
+ PUTCHAR(code, outp);
+ PUTCHAR(id, outp);
+ PUTSHORT(outlen, outp);
+ pppWrite(f->unit, outpacket_buf[f->unit], outlen + PPP_HDRLEN);
+ FSMDEBUG((LOG_INFO, "fsm_sdata(%s): Sent code %d,%d,%d.\n",
+ PROTO_NAME(f), code, id, outlen));
+}
+
+
+/*
+ * fsm_input - Input packet.
+ */
+void fsm_input(fsm *f, u_char *inpacket, int l)
+{
+ u_char *inp = inpacket;
+ u_char code, id;
+ int len;
+
+ /*
+ * Parse header (code, id and length).
+ * If packet too short, drop it.
+ */
+ if (l < HEADERLEN) {
+ FSMDEBUG((LOG_WARNING, "fsm_input(%x): Rcvd short header.\n",
+ f->protocol));
+ return;
+ }
+ GETCHAR(code, inp);
+ GETCHAR(id, inp);
+ GETSHORT(len, inp);
+ if (len < HEADERLEN) {
+ FSMDEBUG((LOG_INFO, "fsm_input(%x): Rcvd illegal length.\n",
+ f->protocol));
+ return;
+ }
+ if (len > l) {
+ FSMDEBUG((LOG_INFO, "fsm_input(%x): Rcvd short packet.\n",
+ f->protocol));
+ return;
+ }
+ len -= HEADERLEN; /* subtract header length */
+
+ if( f->state == INITIAL || f->state == STARTING ){
+ FSMDEBUG((LOG_INFO, "fsm_input(%x): Rcvd packet in state %d.\n",
+ f->protocol, f->state));
+ return;
+ }
+ FSMDEBUG((LOG_INFO, "fsm_input(%s):%d,%d,%d\n", PROTO_NAME(f), code, id, l));
+ /*
+ * Action depends on code.
+ */
+ switch (code) {
+ case CONFREQ:
+ fsm_rconfreq(f, id, inp, len);
+ break;
+
+ case CONFACK:
+ fsm_rconfack(f, id, inp, len);
+ break;
+
+ case CONFNAK:
+ case CONFREJ:
+ fsm_rconfnakrej(f, code, id, inp, len);
+ break;
+
+ case TERMREQ:
+ fsm_rtermreq(f, id, inp, len);
+ break;
+
+ case TERMACK:
+ fsm_rtermack(f);
+ break;
+
+ case CODEREJ:
+ fsm_rcoderej(f, inp, len);
+ break;
+
+ default:
+ if( !f->callbacks->extcode
+ || !(*f->callbacks->extcode)(f, code, id, inp, len) )
+ fsm_sdata(f, CODEREJ, ++f->id, inpacket, len + HEADERLEN);
+ break;
+ }
+}
+
+
+/*
+ * fsm_protreject - Peer doesn't speak this protocol.
+ *
+ * Treat this as a catastrophic error (RXJ-).
+ */
+void fsm_protreject(fsm *f)
+{
+ switch( f->state ){
+ case CLOSING:
+ UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */
+ /* fall through */
+ case CLOSED:
+ f->state = CLOSED;
+ if( f->callbacks->finished )
+ (*f->callbacks->finished)(f);
+ break;
+
+ case STOPPING:
+ case REQSENT:
+ case ACKRCVD:
+ case ACKSENT:
+ UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */
+ /* fall through */
+ case STOPPED:
+ f->state = STOPPED;
+ if( f->callbacks->finished )
+ (*f->callbacks->finished)(f);
+ break;
+
+ case OPENED:
+ if( f->callbacks->down )
+ (*f->callbacks->down)(f);
+
+ /* Init restart counter, send Terminate-Request */
+ f->retransmits = f->maxtermtransmits;
+ fsm_sdata(f, TERMREQ, f->reqid = ++f->id,
+ (u_char *) f->term_reason, f->term_reason_len);
+ TIMEOUT(fsm_timeout, f, f->timeouttime);
+ --f->retransmits;
+
+ f->state = STOPPING;
+ break;
+
+ default:
+ FSMDEBUG((LOG_INFO, "%s: Protocol-reject event in state %d!\n",
+ PROTO_NAME(f), f->state));
+ }
+}
+
+
+
+
+
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+
+/*
+ * fsm_timeout - Timeout expired.
+ */
+static void fsm_timeout(void *arg)
+{
+ fsm *f = (fsm *) arg;
+
+ switch (f->state) {
+ case CLOSING:
+ case STOPPING:
+ if( f->retransmits <= 0 ){
+ FSMDEBUG((LOG_WARNING, "%s: timeout sending Terminate-Request state=%d\n",
+ PROTO_NAME(f), f->state));
+ /*
+ * We've waited for an ack long enough. Peer probably heard us.
+ */
+ f->state = (f->state == CLOSING)? CLOSED: STOPPED;
+ if( f->callbacks->finished )
+ (*f->callbacks->finished)(f);
+ } else {
+ FSMDEBUG((LOG_WARNING, "%s: timeout resending Terminate-Requests state=%d\n",
+ PROTO_NAME(f), f->state));
+ /* Send Terminate-Request */
+ fsm_sdata(f, TERMREQ, f->reqid = ++f->id,
+ (u_char *) f->term_reason, f->term_reason_len);
+ TIMEOUT(fsm_timeout, f, f->timeouttime);
+ --f->retransmits;
+ }
+ break;
+
+ case REQSENT:
+ case ACKRCVD:
+ case ACKSENT:
+ if (f->retransmits <= 0) {
+ FSMDEBUG((LOG_WARNING, "%s: timeout sending Config-Requests state=%d\n",
+ PROTO_NAME(f), f->state));
+ f->state = STOPPED;
+ if( (f->flags & OPT_PASSIVE) == 0 && f->callbacks->finished )
+ (*f->callbacks->finished)(f);
+
+ } else {
+ FSMDEBUG((LOG_WARNING, "%s: timeout resending Config-Request state=%d\n",
+ PROTO_NAME(f), f->state));
+ /* Retransmit the configure-request */
+ if (f->callbacks->retransmit)
+ (*f->callbacks->retransmit)(f);
+ fsm_sconfreq(f, 1); /* Re-send Configure-Request */
+ if( f->state == ACKRCVD )
+ f->state = REQSENT;
+ }
+ break;
+
+ default:
+ FSMDEBUG((LOG_INFO, "%s: Timeout event in state %d!\n",
+ PROTO_NAME(f), f->state));
+ }
+}
+
+
+/*
+ * fsm_rconfreq - Receive Configure-Request.
+ */
+static void fsm_rconfreq(fsm *f, u_char id, u_char *inp, int len)
+{
+ int code, reject_if_disagree;
+
+ FSMDEBUG((LOG_INFO, "fsm_rconfreq(%s): Rcvd id %d state=%d\n",
+ PROTO_NAME(f), id, f->state));
+ switch( f->state ){
+ case CLOSED:
+ /* Go away, we're closed */
+ fsm_sdata(f, TERMACK, id, NULL, 0);
+ return;
+ case CLOSING:
+ case STOPPING:
+ return;
+
+ case OPENED:
+ /* Go down and restart negotiation */
+ if( f->callbacks->down )
+ (*f->callbacks->down)(f); /* Inform upper layers */
+ fsm_sconfreq(f, 0); /* Send initial Configure-Request */
+ break;
+
+ case STOPPED:
+ /* Negotiation started by our peer */
+ fsm_sconfreq(f, 0); /* Send initial Configure-Request */
+ f->state = REQSENT;
+ break;
+ }
+
+ /*
+ * Pass the requested configuration options
+ * to protocol-specific code for checking.
+ */
+ if (f->callbacks->reqci){ /* Check CI */
+ reject_if_disagree = (f->nakloops >= f->maxnakloops);
+ code = (*f->callbacks->reqci)(f, inp, &len, reject_if_disagree);
+ }
+ else if (len)
+ code = CONFREJ; /* Reject all CI */
+ else
+ code = CONFACK;
+
+ /* send the Ack, Nak or Rej to the peer */
+ fsm_sdata(f, (u_char)code, id, inp, len);
+
+ if (code == CONFACK) {
+ if (f->state == ACKRCVD) {
+ UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */
+ f->state = OPENED;
+ if (f->callbacks->up)
+ (*f->callbacks->up)(f); /* Inform upper layers */
+ }
+ else
+ f->state = ACKSENT;
+ f->nakloops = 0;
+ }
+ else {
+ /* we sent CONFACK or CONFREJ */
+ if (f->state != ACKRCVD)
+ f->state = REQSENT;
+ if( code == CONFNAK )
+ ++f->nakloops;
+ }
+}
+
+
+/*
+ * fsm_rconfack - Receive Configure-Ack.
+ */
+static void fsm_rconfack(fsm *f, int id, u_char *inp, int len)
+{
+ FSMDEBUG((LOG_INFO, "fsm_rconfack(%s): Rcvd id %d state=%d\n",
+ PROTO_NAME(f), id, f->state));
+
+ if (id != f->reqid || f->seen_ack) /* Expected id? */
+ return; /* Nope, toss... */
+ if( !(f->callbacks->ackci? (*f->callbacks->ackci)(f, inp, len):
+ (len == 0)) ){
+ /* Ack is bad - ignore it */
+ FSMDEBUG((LOG_INFO, "%s: received bad Ack (length %d)\n",
+ PROTO_NAME(f), len));
+ return;
+ }
+ f->seen_ack = 1;
+
+ switch (f->state) {
+ case CLOSED:
+ case STOPPED:
+ fsm_sdata(f, TERMACK, (u_char)id, NULL, 0);
+ break;
+
+ case REQSENT:
+ f->state = ACKRCVD;
+ f->retransmits = f->maxconfreqtransmits;
+ break;
+
+ case ACKRCVD:
+ /* Huh? an extra valid Ack? oh well... */
+ UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */
+ fsm_sconfreq(f, 0);
+ f->state = REQSENT;
+ break;
+
+ case ACKSENT:
+ UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */
+ f->state = OPENED;
+ f->retransmits = f->maxconfreqtransmits;
+ if (f->callbacks->up)
+ (*f->callbacks->up)(f); /* Inform upper layers */
+ break;
+
+ case OPENED:
+ /* Go down and restart negotiation */
+ if (f->callbacks->down)
+ (*f->callbacks->down)(f); /* Inform upper layers */
+ fsm_sconfreq(f, 0); /* Send initial Configure-Request */
+ f->state = REQSENT;
+ break;
+ }
+}
+
+
+/*
+ * fsm_rconfnakrej - Receive Configure-Nak or Configure-Reject.
+ */
+static void fsm_rconfnakrej(fsm *f, int code, int id, u_char *inp, int len)
+{
+ int (*proc) (fsm *, u_char *, int);
+ int ret;
+
+ FSMDEBUG((LOG_INFO, "fsm_rconfnakrej(%s): Rcvd id %d state=%d\n",
+ PROTO_NAME(f), id, f->state));
+
+ if (id != f->reqid || f->seen_ack) /* Expected id? */
+ return; /* Nope, toss... */
+ proc = (code == CONFNAK)? f->callbacks->nakci: f->callbacks->rejci;
+ if (!proc || !(ret = proc(f, inp, len))) {
+ /* Nak/reject is bad - ignore it */
+ FSMDEBUG((LOG_INFO, "%s: received bad %s (length %d)\n",
+ PROTO_NAME(f), (code==CONFNAK? "Nak": "reject"), len));
+ return;
+ }
+ f->seen_ack = 1;
+
+ switch (f->state) {
+ case CLOSED:
+ case STOPPED:
+ fsm_sdata(f, TERMACK, (u_char)id, NULL, 0);
+ break;
+
+ case REQSENT:
+ case ACKSENT:
+ /* They didn't agree to what we wanted - try another request */
+ UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */
+ if (ret < 0)
+ f->state = STOPPED; /* kludge for stopping CCP */
+ else
+ fsm_sconfreq(f, 0); /* Send Configure-Request */
+ break;
+
+ case ACKRCVD:
+ /* Got a Nak/reject when we had already had an Ack?? oh well... */
+ UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */
+ fsm_sconfreq(f, 0);
+ f->state = REQSENT;
+ break;
+
+ case OPENED:
+ /* Go down and restart negotiation */
+ if (f->callbacks->down)
+ (*f->callbacks->down)(f); /* Inform upper layers */
+ fsm_sconfreq(f, 0); /* Send initial Configure-Request */
+ f->state = REQSENT;
+ break;
+ }
+}
+
+
+/*
+ * fsm_rtermreq - Receive Terminate-Req.
+ */
+static void fsm_rtermreq(fsm *f, int id, u_char *p, int len)
+{
+ FSMDEBUG((LOG_INFO, "fsm_rtermreq(%s): Rcvd id %d state=%d\n",
+ PROTO_NAME(f), id, f->state));
+
+ switch (f->state) {
+ case ACKRCVD:
+ case ACKSENT:
+ f->state = REQSENT; /* Start over but keep trying */
+ break;
+
+ case OPENED:
+ if (len > 0) {
+ FSMDEBUG((LOG_INFO, "%s terminated by peer (%x)\n", PROTO_NAME(f), p));
+ } else {
+ FSMDEBUG((LOG_INFO, "%s terminated by peer\n", PROTO_NAME(f)));
+ }
+ if (f->callbacks->down)
+ (*f->callbacks->down)(f); /* Inform upper layers */
+ f->retransmits = 0;
+ f->state = STOPPING;
+ TIMEOUT(fsm_timeout, f, f->timeouttime);
+ break;
+ }
+
+ fsm_sdata(f, TERMACK, (u_char)id, NULL, 0);
+}
+
+
+/*
+ * fsm_rtermack - Receive Terminate-Ack.
+ */
+static void fsm_rtermack(fsm *f)
+{
+ FSMDEBUG((LOG_INFO, "fsm_rtermack(%s): state=%d\n",
+ PROTO_NAME(f), f->state));
+
+ switch (f->state) {
+ case CLOSING:
+ UNTIMEOUT(fsm_timeout, f);
+ f->state = CLOSED;
+ if( f->callbacks->finished )
+ (*f->callbacks->finished)(f);
+ break;
+ case STOPPING:
+ UNTIMEOUT(fsm_timeout, f);
+ f->state = STOPPED;
+ if( f->callbacks->finished )
+ (*f->callbacks->finished)(f);
+ break;
+
+ case ACKRCVD:
+ f->state = REQSENT;
+ break;
+
+ case OPENED:
+ if (f->callbacks->down)
+ (*f->callbacks->down)(f); /* Inform upper layers */
+ fsm_sconfreq(f, 0);
+ break;
+ }
+}
+
+
+/*
+ * fsm_rcoderej - Receive an Code-Reject.
+ */
+static void fsm_rcoderej(fsm *f, u_char *inp, int len)
+{
+ u_char code, id;
+
+ FSMDEBUG((LOG_INFO, "fsm_rcoderej(%s): state=%d\n",
+ PROTO_NAME(f), f->state));
+
+ if (len < HEADERLEN) {
+ FSMDEBUG((LOG_INFO, "fsm_rcoderej: Rcvd short Code-Reject packet!\n"));
+ return;
+ }
+ GETCHAR(code, inp);
+ GETCHAR(id, inp);
+ FSMDEBUG((LOG_WARNING, "%s: Rcvd Code-Reject for code %d, id %d\n",
+ PROTO_NAME(f), code, id));
+
+ if( f->state == ACKRCVD )
+ f->state = REQSENT;
+}
+
+
+/*
+ * fsm_sconfreq - Send a Configure-Request.
+ */
+static void fsm_sconfreq(fsm *f, int retransmit)
+{
+ u_char *outp;
+ int cilen;
+
+ if( f->state != REQSENT && f->state != ACKRCVD && f->state != ACKSENT ){
+ /* Not currently negotiating - reset options */
+ if( f->callbacks->resetci )
+ (*f->callbacks->resetci)(f);
+ f->nakloops = 0;
+ }
+
+ if( !retransmit ){
+ /* New request - reset retransmission counter, use new ID */
+ f->retransmits = f->maxconfreqtransmits;
+ f->reqid = ++f->id;
+ }
+
+ f->seen_ack = 0;
+
+ /*
+ * Make up the request packet
+ */
+ outp = outpacket_buf[f->unit] + PPP_HDRLEN + HEADERLEN;
+ if( f->callbacks->cilen && f->callbacks->addci ){
+ cilen = (*f->callbacks->cilen)(f);
+ if( cilen > peer_mru[f->unit] - (int)HEADERLEN )
+ cilen = peer_mru[f->unit] - HEADERLEN;
+ if (f->callbacks->addci)
+ (*f->callbacks->addci)(f, outp, &cilen);
+ } else
+ cilen = 0;
+
+ /* send the request to our peer */
+ fsm_sdata(f, CONFREQ, f->reqid, outp, cilen);
+
+ /* start the retransmit timer */
+ --f->retransmits;
+ TIMEOUT(fsm_timeout, f, f->timeouttime);
+
+ FSMDEBUG((LOG_INFO, "%s: sending Configure-Request, id %d\n",
+ PROTO_NAME(f), f->reqid));
+}
+
+#endif /* PPP_SUPPORT */
--- /dev/null
+/*****************************************************************************
+* fsm.h - Network Control Protocol Finite State Machine header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* Copyright (c) 1997 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher <marc@mbsi.ca>
+* Ported to lwIP.
+* 97-11-05 Guy Lancaster <glanca@gesn.com>, Global Election Systems Inc.
+* Original based on BSD code.
+*****************************************************************************/
+/*
+ * fsm.h - {Link, IP} Control Protocol Finite State Machine definitions.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University. The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * $Id: fsm.h,v 1.1 2003/05/27 14:37:56 jani Exp $
+ */
+
+#ifndef FSM_H
+#define FSM_H
+
+
+/*****************************************************************************
+************************* PUBLIC DEFINITIONS *********************************
+*****************************************************************************/
+/*
+ * LCP Packet header = Code, id, length.
+ */
+#define HEADERLEN (sizeof (u_char) + sizeof (u_char) + sizeof (u_short))
+
+
+/*
+ * CP (LCP, IPCP, etc.) codes.
+ */
+#define CONFREQ 1 /* Configuration Request */
+#define CONFACK 2 /* Configuration Ack */
+#define CONFNAK 3 /* Configuration Nak */
+#define CONFREJ 4 /* Configuration Reject */
+#define TERMREQ 5 /* Termination Request */
+#define TERMACK 6 /* Termination Ack */
+#define CODEREJ 7 /* Code Reject */
+
+/*
+ * Link states.
+ */
+#define INITIAL 0 /* Down, hasn't been opened */
+#define STARTING 1 /* Down, been opened */
+#define CLOSED 2 /* Up, hasn't been opened */
+#define STOPPED 3 /* Open, waiting for down event */
+#define CLOSING 4 /* Terminating the connection, not open */
+#define STOPPING 5 /* Terminating, but open */
+#define REQSENT 6 /* We've sent a Config Request */
+#define ACKRCVD 7 /* We've received a Config Ack */
+#define ACKSENT 8 /* We've sent a Config Ack */
+#define OPENED 9 /* Connection available */
+
+
+/*
+ * Flags - indicate options controlling FSM operation
+ */
+#define OPT_PASSIVE 1 /* Don't die if we don't get a response */
+#define OPT_RESTART 2 /* Treat 2nd OPEN as DOWN, UP */
+#define OPT_SILENT 4 /* Wait for peer to speak first */
+
+
+/*****************************************************************************
+************************* PUBLIC DATA TYPES **********************************
+*****************************************************************************/
+/*
+ * Each FSM is described by an fsm structure and fsm callbacks.
+ */
+typedef struct fsm {
+ int unit; /* Interface unit number */
+ u_short protocol; /* Data Link Layer Protocol field value */
+ int state; /* State */
+ int flags; /* Contains option bits */
+ u_char id; /* Current id */
+ u_char reqid; /* Current request id */
+ u_char seen_ack; /* Have received valid Ack/Nak/Rej to Req */
+ int timeouttime; /* Timeout time in milliseconds */
+ int maxconfreqtransmits;/* Maximum Configure-Request transmissions */
+ int retransmits; /* Number of retransmissions left */
+ int maxtermtransmits; /* Maximum Terminate-Request transmissions */
+ int nakloops; /* Number of nak loops since last ack */
+ int maxnakloops; /* Maximum number of nak loops tolerated */
+ struct fsm_callbacks* callbacks;/* Callback routines */
+ char* term_reason; /* Reason for closing protocol */
+ int term_reason_len; /* Length of term_reason */
+} fsm;
+
+
+typedef struct fsm_callbacks {
+ void (*resetci) /* Reset our Configuration Information */
+ (fsm*);
+ int (*cilen) /* Length of our Configuration Information */
+ (fsm*);
+ void (*addci) /* Add our Configuration Information */
+ (fsm*, u_char*, int*);
+ int (*ackci) /* ACK our Configuration Information */
+ (fsm*, u_char*, int);
+ int (*nakci) /* NAK our Configuration Information */
+ (fsm*, u_char*, int);
+ int (*rejci) /* Reject our Configuration Information */
+ (fsm*, u_char*, int);
+ int (*reqci) /* Request peer's Configuration Information */
+ (fsm*, u_char*, int*, int);
+ void (*up) /* Called when fsm reaches OPENED state */
+ (fsm*);
+ void (*down) /* Called when fsm leaves OPENED state */
+ (fsm*);
+ void (*starting) /* Called when we want the lower layer */
+ (fsm*);
+ void (*finished) /* Called when we don't want the lower layer */
+ (fsm*);
+ void (*protreject) /* Called when Protocol-Reject received */
+ (int);
+ void (*retransmit) /* Retransmission is necessary */
+ (fsm*);
+ int (*extcode) /* Called when unknown code received */
+ (fsm*, int, u_char, u_char*, int);
+ char *proto_name; /* String name for protocol (for messages) */
+} fsm_callbacks;
+
+
+/*****************************************************************************
+*********************** PUBLIC DATA STRUCTURES *******************************
+*****************************************************************************/
+/*
+ * Variables
+ */
+extern int peer_mru[]; /* currently negotiated peer MRU (per unit) */
+
+
+/*****************************************************************************
+************************** PUBLIC FUNCTIONS **********************************
+*****************************************************************************/
+
+/*
+ * Prototypes
+ */
+void fsm_init (fsm*);
+void fsm_lowerup (fsm*);
+void fsm_lowerdown (fsm*);
+void fsm_open (fsm*);
+void fsm_close (fsm*, char*);
+void fsm_input (fsm*, u_char*, int);
+void fsm_protreject (fsm*);
+void fsm_sdata (fsm*, u_char, u_char, u_char*, int);
+
+
+#endif /* FSM_H */
+
--- /dev/null
+/*****************************************************************************
+* ipcp.c - Network PPP IP Control Protocol program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher <marc@mbsi.ca>
+* Ported to lwIP.
+* 97-12-08 Guy Lancaster <lancasterg@acm.org>, Global Election Systems Inc.
+* Original.
+*****************************************************************************/
+/*
+ * ipcp.c - PPP IP Control Protocol.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University. The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include <string.h>
+
+#include "ppp.h"
+#if PPP_SUPPORT > 0
+#include "auth.h"
+#include "fsm.h"
+#include "vj.h"
+#include "ipcp.h"
+#include "pppdebug.h"
+
+
+/*************************/
+/*** LOCAL DEFINITIONS ***/
+/*************************/
+/* #define OLD_CI_ADDRS 1 */ /* Support deprecated address negotiation. */
+
+/*
+ * Lengths of configuration options.
+ */
+#define CILEN_VOID 2
+#define CILEN_COMPRESS 4 /* min length for compression protocol opt. */
+#define CILEN_VJ 6 /* length for RFC1332 Van-Jacobson opt. */
+#define CILEN_ADDR 6 /* new-style single address option */
+#define CILEN_ADDRS 10 /* old-style dual address option */
+
+
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+/*
+ * Callbacks for fsm code. (CI = Configuration Information)
+ */
+static void ipcp_resetci (fsm *); /* Reset our CI */
+static int ipcp_cilen (fsm *); /* Return length of our CI */
+static void ipcp_addci (fsm *, u_char *, int *); /* Add our CI */
+static int ipcp_ackci (fsm *, u_char *, int); /* Peer ack'd our CI */
+static int ipcp_nakci (fsm *, u_char *, int); /* Peer nak'd our CI */
+static int ipcp_rejci (fsm *, u_char *, int); /* Peer rej'd our CI */
+static int ipcp_reqci (fsm *, u_char *, int *, int); /* Rcv CI */
+static void ipcp_up (fsm *); /* We're UP */
+static void ipcp_down (fsm *); /* We're DOWN */
+#if 0
+static void ipcp_script (fsm *, char *); /* Run an up/down script */
+#endif
+static void ipcp_finished (fsm *); /* Don't need lower layer */
+
+/*
+ * Protocol entry points from main code.
+ */
+static void ipcp_init (int);
+static void ipcp_open (int);
+static void ipcp_close (int, char *);
+static void ipcp_lowerup (int);
+static void ipcp_lowerdown (int);
+static void ipcp_input (int, u_char *, int);
+static void ipcp_protrej (int);
+
+static void ipcp_clear_addrs (int);
+
+#define CODENAME(x) ((x) == CONFACK ? "ACK" : \
+ (x) == CONFNAK ? "NAK" : "REJ")
+
+
+
+/******************************/
+/*** PUBLIC DATA STRUCTURES ***/
+/******************************/
+/* global vars */
+ipcp_options ipcp_wantoptions[NUM_PPP]; /* Options that we want to request */
+ipcp_options ipcp_gotoptions[NUM_PPP]; /* Options that peer ack'd */
+ipcp_options ipcp_allowoptions[NUM_PPP]; /* Options we allow peer to request */
+ipcp_options ipcp_hisoptions[NUM_PPP]; /* Options that we ack'd */
+
+fsm ipcp_fsm[NUM_PPP]; /* IPCP fsm structure */
+
+struct protent ipcp_protent = {
+ PPP_IPCP,
+ ipcp_init,
+ ipcp_input,
+ ipcp_protrej,
+ ipcp_lowerup,
+ ipcp_lowerdown,
+ ipcp_open,
+ ipcp_close,
+#if 0
+ ipcp_printpkt,
+ NULL,
+#endif
+ 1,
+ "IPCP",
+#if 0
+ ip_check_options,
+ NULL,
+ ip_active_pkt
+#endif
+};
+
+
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+/* local vars */
+static int cis_received[NUM_PPP]; /* # Conf-Reqs received */
+static int default_route_set[NUM_PPP]; /* Have set up a default route */
+
+static fsm_callbacks ipcp_callbacks = { /* IPCP callback routines */
+ ipcp_resetci, /* Reset our Configuration Information */
+ ipcp_cilen, /* Length of our Configuration Information */
+ ipcp_addci, /* Add our Configuration Information */
+ ipcp_ackci, /* ACK our Configuration Information */
+ ipcp_nakci, /* NAK our Configuration Information */
+ ipcp_rejci, /* Reject our Configuration Information */
+ ipcp_reqci, /* Request peer's Configuration Information */
+ ipcp_up, /* Called when fsm reaches OPENED state */
+ ipcp_down, /* Called when fsm leaves OPENED state */
+ NULL, /* Called when we want the lower layer up */
+ ipcp_finished, /* Called when we want the lower layer down */
+ NULL, /* Called when Protocol-Reject received */
+ NULL, /* Retransmission is necessary */
+ NULL, /* Called to handle protocol-specific codes */
+ "IPCP" /* String name of protocol */
+};
+
+
+
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+
+/*
+ * Non-standard inet_ntoa left here for compat with original ppp
+ * sources. Assumes u32_t instead of struct in_addr.
+ */
+
+char * _inet_ntoa(u32_t n)
+{
+ struct in_addr ia;
+ ia.s_addr = n;
+ return inet_ntoa(ia);
+}
+
+#define inet_ntoa _inet_ntoa
+
+/*
+ * ipcp_init - Initialize IPCP.
+ */
+static void ipcp_init(int unit)
+{
+ fsm *f = &ipcp_fsm[unit];
+ ipcp_options *wo = &ipcp_wantoptions[unit];
+ ipcp_options *ao = &ipcp_allowoptions[unit];
+
+ f->unit = unit;
+ f->protocol = PPP_IPCP;
+ f->callbacks = &ipcp_callbacks;
+ fsm_init(&ipcp_fsm[unit]);
+
+ memset(wo, 0, sizeof(*wo));
+ memset(ao, 0, sizeof(*ao));
+
+ wo->neg_addr = 1;
+ wo->ouraddr = 0;
+#if VJ_SUPPORT > 0
+ wo->neg_vj = 1;
+#else
+ wo->neg_vj = 0;
+#endif
+ wo->vj_protocol = IPCP_VJ_COMP;
+ wo->maxslotindex = MAX_SLOTS - 1;
+ wo->cflag = 0;
+
+ wo->default_route = 1;
+
+ ao->neg_addr = 1;
+#if VJ_SUPPORT > 0
+ ao->neg_vj = 1;
+#else
+ ao->neg_vj = 0;
+#endif
+ ao->maxslotindex = MAX_SLOTS - 1;
+ ao->cflag = 1;
+
+ ao->default_route = 1;
+}
+
+
+/*
+ * ipcp_open - IPCP is allowed to come up.
+ */
+static void ipcp_open(int unit)
+{
+ fsm_open(&ipcp_fsm[unit]);
+}
+
+
+/*
+ * ipcp_close - Take IPCP down.
+ */
+static void ipcp_close(int unit, char *reason)
+{
+ fsm_close(&ipcp_fsm[unit], reason);
+}
+
+
+/*
+ * ipcp_lowerup - The lower layer is up.
+ */
+static void ipcp_lowerup(int unit)
+{
+ fsm_lowerup(&ipcp_fsm[unit]);
+}
+
+
+/*
+ * ipcp_lowerdown - The lower layer is down.
+ */
+static void ipcp_lowerdown(int unit)
+{
+ fsm_lowerdown(&ipcp_fsm[unit]);
+}
+
+
+/*
+ * ipcp_input - Input IPCP packet.
+ */
+static void ipcp_input(int unit, u_char *p, int len)
+{
+ fsm_input(&ipcp_fsm[unit], p, len);
+}
+
+
+/*
+ * ipcp_protrej - A Protocol-Reject was received for IPCP.
+ *
+ * Pretend the lower layer went down, so we shut up.
+ */
+static void ipcp_protrej(int unit)
+{
+ fsm_lowerdown(&ipcp_fsm[unit]);
+}
+
+
+/*
+ * ipcp_resetci - Reset our CI.
+ */
+static void ipcp_resetci(fsm *f)
+{
+ ipcp_options *wo = &ipcp_wantoptions[f->unit];
+
+ wo->req_addr = wo->neg_addr && ipcp_allowoptions[f->unit].neg_addr;
+ if (wo->ouraddr == 0)
+ wo->accept_local = 1;
+ if (wo->hisaddr == 0)
+ wo->accept_remote = 1;
+ /* Request DNS addresses from the peer */
+ wo->req_dns1 = ppp_settings.usepeerdns;
+ wo->req_dns2 = ppp_settings.usepeerdns;
+ ipcp_gotoptions[f->unit] = *wo;
+ cis_received[f->unit] = 0;
+}
+
+
+/*
+ * ipcp_cilen - Return length of our CI.
+ */
+static int ipcp_cilen(fsm *f)
+{
+ ipcp_options *go = &ipcp_gotoptions[f->unit];
+ ipcp_options *wo = &ipcp_wantoptions[f->unit];
+ ipcp_options *ho = &ipcp_hisoptions[f->unit];
+
+#define LENCIVJ(neg, old) (neg ? (old? CILEN_COMPRESS : CILEN_VJ) : 0)
+#define LENCIADDR(neg, old) (neg ? (old? CILEN_ADDRS : CILEN_ADDR) : 0)
+#define LENCIDNS(neg) (neg ? (CILEN_ADDR) : 0)
+
+ /*
+ * First see if we want to change our options to the old
+ * forms because we have received old forms from the peer.
+ */
+ if (wo->neg_addr && !go->neg_addr && !go->old_addrs) {
+ /* use the old style of address negotiation */
+ go->neg_addr = 1;
+ go->old_addrs = 1;
+ }
+ if (wo->neg_vj && !go->neg_vj && !go->old_vj) {
+ /* try an older style of VJ negotiation */
+ if (cis_received[f->unit] == 0) {
+ /* keep trying the new style until we see some CI from the peer */
+ go->neg_vj = 1;
+ } else {
+ /* use the old style only if the peer did */
+ if (ho->neg_vj && ho->old_vj) {
+ go->neg_vj = 1;
+ go->old_vj = 1;
+ go->vj_protocol = ho->vj_protocol;
+ }
+ }
+ }
+
+ return (LENCIADDR(go->neg_addr, go->old_addrs)
+ + LENCIVJ(go->neg_vj, go->old_vj) +
+ LENCIDNS(go->req_dns1) +
+ LENCIDNS(go->req_dns2));
+}
+
+
+/*
+ * ipcp_addci - Add our desired CIs to a packet.
+ */
+static void ipcp_addci(fsm *f, u_char *ucp, int *lenp)
+{
+ ipcp_options *go = &ipcp_gotoptions[f->unit];
+ int len = *lenp;
+
+#define ADDCIVJ(opt, neg, val, old, maxslotindex, cflag) \
+ if (neg) { \
+ int vjlen = old? CILEN_COMPRESS : CILEN_VJ; \
+ if (len >= vjlen) { \
+ PUTCHAR(opt, ucp); \
+ PUTCHAR(vjlen, ucp); \
+ PUTSHORT(val, ucp); \
+ if (!old) { \
+ PUTCHAR(maxslotindex, ucp); \
+ PUTCHAR(cflag, ucp); \
+ } \
+ len -= vjlen; \
+ } else \
+ neg = 0; \
+ }
+
+#define ADDCIADDR(opt, neg, old, val1, val2) \
+ if (neg) { \
+ int addrlen = (old? CILEN_ADDRS: CILEN_ADDR); \
+ if (len >= addrlen) { \
+ u32_t l; \
+ PUTCHAR(opt, ucp); \
+ PUTCHAR(addrlen, ucp); \
+ l = ntohl(val1); \
+ PUTLONG(l, ucp); \
+ if (old) { \
+ l = ntohl(val2); \
+ PUTLONG(l, ucp); \
+ } \
+ len -= addrlen; \
+ } else \
+ neg = 0; \
+ }
+
+#define ADDCIDNS(opt, neg, addr) \
+ if (neg) { \
+ if (len >= CILEN_ADDR) { \
+ u32_t l; \
+ PUTCHAR(opt, ucp); \
+ PUTCHAR(CILEN_ADDR, ucp); \
+ l = ntohl(addr); \
+ PUTLONG(l, ucp); \
+ len -= CILEN_ADDR; \
+ } else \
+ neg = 0; \
+ }
+
+ ADDCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), go->neg_addr,
+ go->old_addrs, go->ouraddr, go->hisaddr);
+
+ ADDCIVJ(CI_COMPRESSTYPE, go->neg_vj, go->vj_protocol, go->old_vj,
+ go->maxslotindex, go->cflag);
+
+ ADDCIDNS(CI_MS_DNS1, go->req_dns1, go->dnsaddr[0]);
+
+ ADDCIDNS(CI_MS_DNS2, go->req_dns2, go->dnsaddr[1]);
+
+ *lenp -= len;
+}
+
+
+/*
+ * ipcp_ackci - Ack our CIs.
+ *
+ * Returns:
+ * 0 - Ack was bad.
+ * 1 - Ack was good.
+ */
+static int ipcp_ackci(fsm *f, u_char *p, int len)
+{
+ ipcp_options *go = &ipcp_gotoptions[f->unit];
+ u_short cilen, citype, cishort;
+ u32_t cilong;
+ u_char cimaxslotindex, cicflag;
+
+ /*
+ * CIs must be in exactly the same order that we sent...
+ * Check packet length and CI length at each step.
+ * If we find any deviations, then this packet is bad.
+ */
+
+#define ACKCIVJ(opt, neg, val, old, maxslotindex, cflag) \
+ if (neg) { \
+ int vjlen = old? CILEN_COMPRESS : CILEN_VJ; \
+ if ((len -= vjlen) < 0) \
+ goto bad; \
+ GETCHAR(citype, p); \
+ GETCHAR(cilen, p); \
+ if (cilen != vjlen || \
+ citype != opt) \
+ goto bad; \
+ GETSHORT(cishort, p); \
+ if (cishort != val) \
+ goto bad; \
+ if (!old) { \
+ GETCHAR(cimaxslotindex, p); \
+ if (cimaxslotindex != maxslotindex) \
+ goto bad; \
+ GETCHAR(cicflag, p); \
+ if (cicflag != cflag) \
+ goto bad; \
+ } \
+ }
+
+#define ACKCIADDR(opt, neg, old, val1, val2) \
+ if (neg) { \
+ int addrlen = (old? CILEN_ADDRS: CILEN_ADDR); \
+ u32_t l; \
+ if ((len -= addrlen) < 0) \
+ goto bad; \
+ GETCHAR(citype, p); \
+ GETCHAR(cilen, p); \
+ if (cilen != addrlen || \
+ citype != opt) \
+ goto bad; \
+ GETLONG(l, p); \
+ cilong = htonl(l); \
+ if (val1 != cilong) \
+ goto bad; \
+ if (old) { \
+ GETLONG(l, p); \
+ cilong = htonl(l); \
+ if (val2 != cilong) \
+ goto bad; \
+ } \
+ }
+
+#define ACKCIDNS(opt, neg, addr) \
+ if (neg) { \
+ u32_t l; \
+ if ((len -= CILEN_ADDR) < 0) \
+ goto bad; \
+ GETCHAR(citype, p); \
+ GETCHAR(cilen, p); \
+ if (cilen != CILEN_ADDR || \
+ citype != opt) \
+ goto bad; \
+ GETLONG(l, p); \
+ cilong = htonl(l); \
+ if (addr != cilong) \
+ goto bad; \
+ }
+
+ ACKCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), go->neg_addr,
+ go->old_addrs, go->ouraddr, go->hisaddr);
+
+ ACKCIVJ(CI_COMPRESSTYPE, go->neg_vj, go->vj_protocol, go->old_vj,
+ go->maxslotindex, go->cflag);
+
+ ACKCIDNS(CI_MS_DNS1, go->req_dns1, go->dnsaddr[0]);
+
+ ACKCIDNS(CI_MS_DNS2, go->req_dns2, go->dnsaddr[1]);
+
+ /*
+ * If there are any remaining CIs, then this packet is bad.
+ */
+ if (len != 0)
+ goto bad;
+ return (1);
+
+bad:
+ IPCPDEBUG((LOG_INFO, "ipcp_ackci: received bad Ack!\n"));
+ return (0);
+}
+
+/*
+ * ipcp_nakci - Peer has sent a NAK for some of our CIs.
+ * This should not modify any state if the Nak is bad
+ * or if IPCP is in the OPENED state.
+ *
+ * Returns:
+ * 0 - Nak was bad.
+ * 1 - Nak was good.
+ */
+static int ipcp_nakci(fsm *f, u_char *p, int len)
+{
+ ipcp_options *go = &ipcp_gotoptions[f->unit];
+ u_char cimaxslotindex, cicflag;
+ u_char citype, cilen, *next;
+ u_short cishort;
+ u32_t ciaddr1, ciaddr2, l, cidnsaddr;
+ ipcp_options no; /* options we've seen Naks for */
+ ipcp_options try; /* options to request next time */
+
+ BZERO(&no, sizeof(no));
+ try = *go;
+
+ /*
+ * Any Nak'd CIs must be in exactly the same order that we sent.
+ * Check packet length and CI length at each step.
+ * If we find any deviations, then this packet is bad.
+ */
+#define NAKCIADDR(opt, neg, old, code) \
+ if (go->neg && \
+ len >= (cilen = (old? CILEN_ADDRS: CILEN_ADDR)) && \
+ p[1] == cilen && \
+ p[0] == opt) { \
+ len -= cilen; \
+ INCPTR(2, p); \
+ GETLONG(l, p); \
+ ciaddr1 = htonl(l); \
+ if (old) { \
+ GETLONG(l, p); \
+ ciaddr2 = htonl(l); \
+ no.old_addrs = 1; \
+ } else \
+ ciaddr2 = 0; \
+ no.neg = 1; \
+ code \
+ }
+
+#define NAKCIVJ(opt, neg, code) \
+ if (go->neg && \
+ ((cilen = p[1]) == CILEN_COMPRESS || cilen == CILEN_VJ) && \
+ len >= cilen && \
+ p[0] == opt) { \
+ len -= cilen; \
+ INCPTR(2, p); \
+ GETSHORT(cishort, p); \
+ no.neg = 1; \
+ code \
+ }
+
+#define NAKCIDNS(opt, neg, code) \
+ if (go->neg && \
+ ((cilen = p[1]) == CILEN_ADDR) && \
+ len >= cilen && \
+ p[0] == opt) { \
+ len -= cilen; \
+ INCPTR(2, p); \
+ GETLONG(l, p); \
+ cidnsaddr = htonl(l); \
+ no.neg = 1; \
+ code \
+ }
+
+ /*
+ * Accept the peer's idea of {our,his} address, if different
+ * from our idea, only if the accept_{local,remote} flag is set.
+ */
+ NAKCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), neg_addr, go->old_addrs,
+ if (go->accept_local && ciaddr1) { /* Do we know our address? */
+ try.ouraddr = ciaddr1;
+ IPCPDEBUG((LOG_INFO, "local IP address %s\n",
+ inet_ntoa(ciaddr1)));
+ }
+ if (go->accept_remote && ciaddr2) { /* Does he know his? */
+ try.hisaddr = ciaddr2;
+ IPCPDEBUG((LOG_INFO, "remote IP address %s\n",
+ inet_ntoa(ciaddr2)));
+ }
+ );
+
+ /*
+ * Accept the peer's value of maxslotindex provided that it
+ * is less than what we asked for. Turn off slot-ID compression
+ * if the peer wants. Send old-style compress-type option if
+ * the peer wants.
+ */
+ NAKCIVJ(CI_COMPRESSTYPE, neg_vj,
+ if (cilen == CILEN_VJ) {
+ GETCHAR(cimaxslotindex, p);
+ GETCHAR(cicflag, p);
+ if (cishort == IPCP_VJ_COMP) {
+ try.old_vj = 0;
+ if (cimaxslotindex < go->maxslotindex)
+ try.maxslotindex = cimaxslotindex;
+ if (!cicflag)
+ try.cflag = 0;
+ } else {
+ try.neg_vj = 0;
+ }
+ } else {
+ if (cishort == IPCP_VJ_COMP || cishort == IPCP_VJ_COMP_OLD) {
+ try.old_vj = 1;
+ try.vj_protocol = cishort;
+ } else {
+ try.neg_vj = 0;
+ }
+ }
+ );
+
+ NAKCIDNS(CI_MS_DNS1, req_dns1,
+ try.dnsaddr[0] = cidnsaddr;
+ IPCPDEBUG((LOG_INFO, "primary DNS address %s\n", inet_ntoa(cidnsaddr)));
+ );
+
+ NAKCIDNS(CI_MS_DNS2, req_dns2,
+ try.dnsaddr[1] = cidnsaddr;
+ IPCPDEBUG((LOG_INFO, "secondary DNS address %s\n", inet_ntoa(cidnsaddr)));
+ );
+
+ /*
+ * There may be remaining CIs, if the peer is requesting negotiation
+ * on an option that we didn't include in our request packet.
+ * If they want to negotiate about IP addresses, we comply.
+ * If they want us to ask for compression, we refuse.
+ */
+ while (len > CILEN_VOID) {
+ GETCHAR(citype, p);
+ GETCHAR(cilen, p);
+ if( (len -= cilen) < 0 )
+ goto bad;
+ next = p + cilen - 2;
+
+ switch (citype) {
+ case CI_COMPRESSTYPE:
+ if (go->neg_vj || no.neg_vj ||
+ (cilen != CILEN_VJ && cilen != CILEN_COMPRESS))
+ goto bad;
+ no.neg_vj = 1;
+ break;
+ case CI_ADDRS:
+ if ((go->neg_addr && go->old_addrs) || no.old_addrs
+ || cilen != CILEN_ADDRS)
+ goto bad;
+ try.neg_addr = 1;
+ try.old_addrs = 1;
+ GETLONG(l, p);
+ ciaddr1 = htonl(l);
+ if (ciaddr1 && go->accept_local)
+ try.ouraddr = ciaddr1;
+ GETLONG(l, p);
+ ciaddr2 = htonl(l);
+ if (ciaddr2 && go->accept_remote)
+ try.hisaddr = ciaddr2;
+ no.old_addrs = 1;
+ break;
+ case CI_ADDR:
+ if (go->neg_addr || no.neg_addr || cilen != CILEN_ADDR)
+ goto bad;
+ try.old_addrs = 0;
+ GETLONG(l, p);
+ ciaddr1 = htonl(l);
+ if (ciaddr1 && go->accept_local)
+ try.ouraddr = ciaddr1;
+ if (try.ouraddr != 0)
+ try.neg_addr = 1;
+ no.neg_addr = 1;
+ break;
+ }
+ p = next;
+ }
+
+ /* If there is still anything left, this packet is bad. */
+ if (len != 0)
+ goto bad;
+
+ /*
+ * OK, the Nak is good. Now we can update state.
+ */
+ if (f->state != OPENED)
+ *go = try;
+
+ return 1;
+
+bad:
+ IPCPDEBUG((LOG_INFO, "ipcp_nakci: received bad Nak!\n"));
+ return 0;
+}
+
+
+/*
+ * ipcp_rejci - Reject some of our CIs.
+ */
+static int ipcp_rejci(fsm *f, u_char *p, int len)
+{
+ ipcp_options *go = &ipcp_gotoptions[f->unit];
+ u_char cimaxslotindex, ciflag, cilen;
+ u_short cishort;
+ u32_t cilong;
+ ipcp_options try; /* options to request next time */
+
+ try = *go;
+ /*
+ * Any Rejected CIs must be in exactly the same order that we sent.
+ * Check packet length and CI length at each step.
+ * If we find any deviations, then this packet is bad.
+ */
+#define REJCIADDR(opt, neg, old, val1, val2) \
+ if (go->neg && \
+ len >= (cilen = old? CILEN_ADDRS: CILEN_ADDR) && \
+ p[1] == cilen && \
+ p[0] == opt) { \
+ u32_t l; \
+ len -= cilen; \
+ INCPTR(2, p); \
+ GETLONG(l, p); \
+ cilong = htonl(l); \
+ /* Check rejected value. */ \
+ if (cilong != val1) \
+ goto bad; \
+ if (old) { \
+ GETLONG(l, p); \
+ cilong = htonl(l); \
+ /* Check rejected value. */ \
+ if (cilong != val2) \
+ goto bad; \
+ } \
+ try.neg = 0; \
+ }
+
+#define REJCIVJ(opt, neg, val, old, maxslot, cflag) \
+ if (go->neg && \
+ p[1] == (old? CILEN_COMPRESS : CILEN_VJ) && \
+ len >= p[1] && \
+ p[0] == opt) { \
+ len -= p[1]; \
+ INCPTR(2, p); \
+ GETSHORT(cishort, p); \
+ /* Check rejected value. */ \
+ if (cishort != val) \
+ goto bad; \
+ if (!old) { \
+ GETCHAR(cimaxslotindex, p); \
+ if (cimaxslotindex != maxslot) \
+ goto bad; \
+ GETCHAR(ciflag, p); \
+ if (ciflag != cflag) \
+ goto bad; \
+ } \
+ try.neg = 0; \
+ }
+
+#define REJCIDNS(opt, neg, dnsaddr) \
+ if (go->neg && \
+ ((cilen = p[1]) == CILEN_ADDR) && \
+ len >= cilen && \
+ p[0] == opt) { \
+ u32_t l; \
+ len -= cilen; \
+ INCPTR(2, p); \
+ GETLONG(l, p); \
+ cilong = htonl(l); \
+ /* Check rejected value. */ \
+ if (cilong != dnsaddr) \
+ goto bad; \
+ try.neg = 0; \
+ }
+
+ REJCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), neg_addr,
+ go->old_addrs, go->ouraddr, go->hisaddr);
+
+ REJCIVJ(CI_COMPRESSTYPE, neg_vj, go->vj_protocol, go->old_vj,
+ go->maxslotindex, go->cflag);
+
+ REJCIDNS(CI_MS_DNS1, req_dns1, go->dnsaddr[0]);
+
+ REJCIDNS(CI_MS_DNS2, req_dns2, go->dnsaddr[1]);
+
+ /*
+ * If there are any remaining CIs, then this packet is bad.
+ */
+ if (len != 0)
+ goto bad;
+ /*
+ * Now we can update state.
+ */
+ if (f->state != OPENED)
+ *go = try;
+ return 1;
+
+bad:
+ IPCPDEBUG((LOG_INFO, "ipcp_rejci: received bad Reject!\n"));
+ return 0;
+}
+
+
+/*
+ * ipcp_reqci - Check the peer's requested CIs and send appropriate response.
+ *
+ * Returns: CONFACK, CONFNAK or CONFREJ and input packet modified
+ * appropriately. If reject_if_disagree is non-zero, doesn't return
+ * CONFNAK; returns CONFREJ if it can't return CONFACK.
+ */
+static int ipcp_reqci(
+ fsm *f,
+ u_char *inp, /* Requested CIs */
+ int *len, /* Length of requested CIs */
+ int reject_if_disagree
+)
+{
+ ipcp_options *wo = &ipcp_wantoptions[f->unit];
+ ipcp_options *ho = &ipcp_hisoptions[f->unit];
+ ipcp_options *ao = &ipcp_allowoptions[f->unit];
+#ifdef OLD_CI_ADDRS
+ ipcp_options *go = &ipcp_gotoptions[f->unit];
+#endif
+ u_char *cip, *next; /* Pointer to current and next CIs */
+ u_short cilen, citype; /* Parsed len, type */
+ u_short cishort; /* Parsed short value */
+ u32_t tl, ciaddr1; /* Parsed address values */
+#ifdef OLD_CI_ADDRS
+ u32_t ciaddr2; /* Parsed address values */
+#endif
+ int rc = CONFACK; /* Final packet return code */
+ int orc; /* Individual option return code */
+ u_char *p; /* Pointer to next char to parse */
+ u_char *ucp = inp; /* Pointer to current output char */
+ int l = *len; /* Length left */
+ u_char maxslotindex, cflag;
+ int d;
+
+ cis_received[f->unit] = 1;
+
+ /*
+ * Reset all his options.
+ */
+ BZERO(ho, sizeof(*ho));
+
+ /*
+ * Process all his options.
+ */
+ next = inp;
+ while (l) {
+ orc = CONFACK; /* Assume success */
+ cip = p = next; /* Remember begining of CI */
+ if (l < 2 || /* Not enough data for CI header or */
+ p[1] < 2 || /* CI length too small or */
+ p[1] > l) { /* CI length too big? */
+ IPCPDEBUG((LOG_INFO, "ipcp_reqci: bad CI length!\n"));
+ orc = CONFREJ; /* Reject bad CI */
+ cilen = l; /* Reject till end of packet */
+ l = 0; /* Don't loop again */
+ goto endswitch;
+ }
+ GETCHAR(citype, p); /* Parse CI type */
+ GETCHAR(cilen, p); /* Parse CI length */
+ l -= cilen; /* Adjust remaining length */
+ next += cilen; /* Step to next CI */
+
+ switch (citype) { /* Check CI type */
+#ifdef OLD_CI_ADDRS /* Need to save space... */
+ case CI_ADDRS:
+ IPCPDEBUG((LOG_INFO, "ipcp_reqci: received ADDRS\n"));
+ if (!ao->neg_addr ||
+ cilen != CILEN_ADDRS) { /* Check CI length */
+ orc = CONFREJ; /* Reject CI */
+ break;
+ }
+
+ /*
+ * If he has no address, or if we both have his address but
+ * disagree about it, then NAK it with our idea.
+ * In particular, if we don't know his address, but he does,
+ * then accept it.
+ */
+ GETLONG(tl, p); /* Parse source address (his) */
+ ciaddr1 = htonl(tl);
+ IPCPDEBUG((LOG_INFO, "his addr %s\n", inet_ntoa(ciaddr1)));
+ if (ciaddr1 != wo->hisaddr
+ && (ciaddr1 == 0 || !wo->accept_remote)) {
+ orc = CONFNAK;
+ if (!reject_if_disagree) {
+ DECPTR(sizeof(u32_t), p);
+ tl = ntohl(wo->hisaddr);
+ PUTLONG(tl, p);
+ }
+ } else if (ciaddr1 == 0 && wo->hisaddr == 0) {
+ /*
+ * If neither we nor he knows his address, reject the option.
+ */
+ orc = CONFREJ;
+ wo->req_addr = 0; /* don't NAK with 0.0.0.0 later */
+ break;
+ }
+
+ /*
+ * If he doesn't know our address, or if we both have our address
+ * but disagree about it, then NAK it with our idea.
+ */
+ GETLONG(tl, p); /* Parse desination address (ours) */
+ ciaddr2 = htonl(tl);
+ IPCPDEBUG((LOG_INFO, "our addr %s\n", inet_ntoa(ciaddr2)));
+ if (ciaddr2 != wo->ouraddr) {
+ if (ciaddr2 == 0 || !wo->accept_local) {
+ orc = CONFNAK;
+ if (!reject_if_disagree) {
+ DECPTR(sizeof(u32_t), p);
+ tl = ntohl(wo->ouraddr);
+ PUTLONG(tl, p);
+ }
+ } else {
+ go->ouraddr = ciaddr2; /* accept peer's idea */
+ }
+ }
+
+ ho->neg_addr = 1;
+ ho->old_addrs = 1;
+ ho->hisaddr = ciaddr1;
+ ho->ouraddr = ciaddr2;
+ break;
+#endif
+
+ case CI_ADDR:
+ if (!ao->neg_addr) {
+ IPCPDEBUG((LOG_INFO, "ipcp_reqci: Reject ADDR not allowed\n"));
+ orc = CONFREJ; /* Reject CI */
+ break;
+ } else if (cilen != CILEN_ADDR) { /* Check CI length */
+ IPCPDEBUG((LOG_INFO, "ipcp_reqci: Reject ADDR bad len\n"));
+ orc = CONFREJ; /* Reject CI */
+ break;
+ }
+
+ /*
+ * If he has no address, or if we both have his address but
+ * disagree about it, then NAK it with our idea.
+ * In particular, if we don't know his address, but he does,
+ * then accept it.
+ */
+ GETLONG(tl, p); /* Parse source address (his) */
+ ciaddr1 = htonl(tl);
+ if (ciaddr1 != wo->hisaddr
+ && (ciaddr1 == 0 || !wo->accept_remote)) {
+ orc = CONFNAK;
+ if (!reject_if_disagree) {
+ DECPTR(sizeof(u32_t), p);
+ tl = ntohl(wo->hisaddr);
+ PUTLONG(tl, p);
+ }
+ IPCPDEBUG((LOG_INFO, "ipcp_reqci: Nak ADDR %s\n", inet_ntoa(ciaddr1)));
+ } else if (ciaddr1 == 0 && wo->hisaddr == 0) {
+ /*
+ * Don't ACK an address of 0.0.0.0 - reject it instead.
+ */
+ IPCPDEBUG((LOG_INFO, "ipcp_reqci: Reject ADDR %s\n", inet_ntoa(ciaddr1)));
+ orc = CONFREJ;
+ wo->req_addr = 0; /* don't NAK with 0.0.0.0 later */
+ break;
+ }
+
+ ho->neg_addr = 1;
+ ho->hisaddr = ciaddr1;
+ IPCPDEBUG((LOG_INFO, "ipcp_reqci: ADDR %s\n", inet_ntoa(ciaddr1)));
+ break;
+
+ case CI_MS_DNS1:
+ case CI_MS_DNS2:
+ /* Microsoft primary or secondary DNS request */
+ d = citype == CI_MS_DNS2;
+
+ /* If we do not have a DNS address then we cannot send it */
+ if (ao->dnsaddr[d] == 0 ||
+ cilen != CILEN_ADDR) { /* Check CI length */
+ IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting DNS%d Request\n", d+1));
+ orc = CONFREJ; /* Reject CI */
+ break;
+ }
+ GETLONG(tl, p);
+ if (htonl(tl) != ao->dnsaddr[d]) {
+ IPCPDEBUG((LOG_INFO, "ipcp_reqci: Naking DNS%d Request %d\n",
+ d+1, inet_ntoa(tl)));
+ DECPTR(sizeof(u32_t), p);
+ tl = ntohl(ao->dnsaddr[d]);
+ PUTLONG(tl, p);
+ orc = CONFNAK;
+ }
+ IPCPDEBUG((LOG_INFO, "ipcp_reqci: received DNS%d Request\n", d+1));
+ break;
+
+ case CI_MS_WINS1:
+ case CI_MS_WINS2:
+ /* Microsoft primary or secondary WINS request */
+ d = citype == CI_MS_WINS2;
+ IPCPDEBUG((LOG_INFO, "ipcp_reqci: received WINS%d Request\n", d+1));
+
+ /* If we do not have a DNS address then we cannot send it */
+ if (ao->winsaddr[d] == 0 ||
+ cilen != CILEN_ADDR) { /* Check CI length */
+ orc = CONFREJ; /* Reject CI */
+ break;
+ }
+ GETLONG(tl, p);
+ if (htonl(tl) != ao->winsaddr[d]) {
+ DECPTR(sizeof(u32_t), p);
+ tl = ntohl(ao->winsaddr[d]);
+ PUTLONG(tl, p);
+ orc = CONFNAK;
+ }
+ break;
+
+ case CI_COMPRESSTYPE:
+ if (!ao->neg_vj) {
+ IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting COMPRESSTYPE not allowed\n"));
+ orc = CONFREJ;
+ break;
+ } else if (cilen != CILEN_VJ && cilen != CILEN_COMPRESS) {
+ IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting COMPRESSTYPE len=%d\n", cilen));
+ orc = CONFREJ;
+ break;
+ }
+ GETSHORT(cishort, p);
+
+ if (!(cishort == IPCP_VJ_COMP ||
+ (cishort == IPCP_VJ_COMP_OLD && cilen == CILEN_COMPRESS))) {
+ IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting COMPRESSTYPE %d\n", cishort));
+ orc = CONFREJ;
+ break;
+ }
+
+ ho->neg_vj = 1;
+ ho->vj_protocol = cishort;
+ if (cilen == CILEN_VJ) {
+ GETCHAR(maxslotindex, p);
+ if (maxslotindex > ao->maxslotindex) {
+ IPCPDEBUG((LOG_INFO, "ipcp_reqci: Naking VJ max slot %d\n", maxslotindex));
+ orc = CONFNAK;
+ if (!reject_if_disagree){
+ DECPTR(1, p);
+ PUTCHAR(ao->maxslotindex, p);
+ }
+ }
+ GETCHAR(cflag, p);
+ if (cflag && !ao->cflag) {
+ IPCPDEBUG((LOG_INFO, "ipcp_reqci: Naking VJ cflag %d\n", cflag));
+ orc = CONFNAK;
+ if (!reject_if_disagree){
+ DECPTR(1, p);
+ PUTCHAR(wo->cflag, p);
+ }
+ }
+ ho->maxslotindex = maxslotindex;
+ ho->cflag = cflag;
+ } else {
+ ho->old_vj = 1;
+ ho->maxslotindex = MAX_SLOTS - 1;
+ ho->cflag = 1;
+ }
+ IPCPDEBUG((LOG_INFO,
+ "ipcp_reqci: received COMPRESSTYPE p=%d old=%d maxslot=%d cflag=%d\n",
+ ho->vj_protocol, ho->old_vj, ho->maxslotindex, ho->cflag));
+ break;
+
+ default:
+ IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting unknown CI type %d\n", citype));
+ orc = CONFREJ;
+ break;
+ }
+
+endswitch:
+ if (orc == CONFACK && /* Good CI */
+ rc != CONFACK) /* but prior CI wasnt? */
+ continue; /* Don't send this one */
+
+ if (orc == CONFNAK) { /* Nak this CI? */
+ if (reject_if_disagree) { /* Getting fed up with sending NAKs? */
+ IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting too many naks\n"));
+ orc = CONFREJ; /* Get tough if so */
+ } else {
+ if (rc == CONFREJ) /* Rejecting prior CI? */
+ continue; /* Don't send this one */
+ if (rc == CONFACK) { /* Ack'd all prior CIs? */
+ rc = CONFNAK; /* Not anymore... */
+ ucp = inp; /* Backup */
+ }
+ }
+ }
+
+ if (orc == CONFREJ && /* Reject this CI */
+ rc != CONFREJ) { /* but no prior ones? */
+ rc = CONFREJ;
+ ucp = inp; /* Backup */
+ }
+
+ /* Need to move CI? */
+ if (ucp != cip)
+ BCOPY(cip, ucp, cilen); /* Move it */
+
+ /* Update output pointer */
+ INCPTR(cilen, ucp);
+ }
+
+ /*
+ * If we aren't rejecting this packet, and we want to negotiate
+ * their address, and they didn't send their address, then we
+ * send a NAK with a CI_ADDR option appended. We assume the
+ * input buffer is long enough that we can append the extra
+ * option safely.
+ */
+ if (rc != CONFREJ && !ho->neg_addr &&
+ wo->req_addr && !reject_if_disagree) {
+ IPCPDEBUG((LOG_INFO, "ipcp_reqci: Requesting peer address\n"));
+ if (rc == CONFACK) {
+ rc = CONFNAK;
+ ucp = inp; /* reset pointer */
+ wo->req_addr = 0; /* don't ask again */
+ }
+ PUTCHAR(CI_ADDR, ucp);
+ PUTCHAR(CILEN_ADDR, ucp);
+ tl = ntohl(wo->hisaddr);
+ PUTLONG(tl, ucp);
+ }
+
+ *len = (int)(ucp - inp); /* Compute output length */
+ IPCPDEBUG((LOG_INFO, "ipcp_reqci: returning Configure-%s\n", CODENAME(rc)));
+ return (rc); /* Return final code */
+}
+
+
+#if 0
+/*
+ * ip_check_options - check that any IP-related options are OK,
+ * and assign appropriate defaults.
+ */
+static void ip_check_options(u_long localAddr)
+{
+ ipcp_options *wo = &ipcp_wantoptions[0];
+
+ /*
+ * Load our default IP address but allow the remote host to give us
+ * a new address.
+ */
+ if (wo->ouraddr == 0 && !ppp_settings.disable_defaultip) {
+ wo->accept_local = 1; /* don't insist on this default value */
+ wo->ouraddr = htonl(localAddr);
+ }
+}
+#endif
+
+
+/*
+ * ipcp_up - IPCP has come UP.
+ *
+ * Configure the IP network interface appropriately and bring it up.
+ */
+static void ipcp_up(fsm *f)
+{
+ u32_t mask;
+ ipcp_options *ho = &ipcp_hisoptions[f->unit];
+ ipcp_options *go = &ipcp_gotoptions[f->unit];
+ ipcp_options *wo = &ipcp_wantoptions[f->unit];
+
+ np_up(f->unit, PPP_IP);
+ IPCPDEBUG((LOG_INFO, "ipcp: up\n"));
+
+ /*
+ * We must have a non-zero IP address for both ends of the link.
+ */
+ if (!ho->neg_addr)
+ ho->hisaddr = wo->hisaddr;
+
+ if (ho->hisaddr == 0) {
+ IPCPDEBUG((LOG_ERR, "Could not determine remote IP address\n"));
+ ipcp_close(f->unit, "Could not determine remote IP address");
+ return;
+ }
+ if (go->ouraddr == 0) {
+ IPCPDEBUG((LOG_ERR, "Could not determine local IP address\n"));
+ ipcp_close(f->unit, "Could not determine local IP address");
+ return;
+ }
+
+ if (ppp_settings.usepeerdns && (go->dnsaddr[0] || go->dnsaddr[1])) {
+ /*pppGotDNSAddrs(go->dnsaddr[0], go->dnsaddr[1]);*/
+ }
+
+ /*
+ * Check that the peer is allowed to use the IP address it wants.
+ */
+ if (!auth_ip_addr(f->unit, ho->hisaddr)) {
+ IPCPDEBUG((LOG_ERR, "Peer is not authorized to use remote address %s\n",
+ inet_ntoa(ho->hisaddr)));
+ ipcp_close(f->unit, "Unauthorized remote IP address");
+ return;
+ }
+
+ /* set tcp compression */
+ sifvjcomp(f->unit, ho->neg_vj, ho->cflag, ho->maxslotindex);
+
+ /*
+ * Set IP addresses and (if specified) netmask.
+ */
+ mask = GetMask(go->ouraddr);
+
+ if (!sifaddr(f->unit, go->ouraddr, ho->hisaddr, mask, go->dnsaddr[0], go->dnsaddr[1])) {
+ IPCPDEBUG((LOG_WARNING, "sifaddr failed\n"));
+ ipcp_close(f->unit, "Interface configuration failed");
+ return;
+ }
+
+ /* bring the interface up for IP */
+ if (!sifup(f->unit)) {
+ IPCPDEBUG((LOG_WARNING, "sifup failed\n"));
+ ipcp_close(f->unit, "Interface configuration failed");
+ return;
+ }
+
+ sifnpmode(f->unit, PPP_IP, NPMODE_PASS);
+
+ /* assign a default route through the interface if required */
+ if (ipcp_wantoptions[f->unit].default_route)
+ if (sifdefaultroute(f->unit, go->ouraddr, ho->hisaddr))
+ default_route_set[f->unit] = 1;
+
+ IPCPDEBUG((LOG_NOTICE, "local IP address %s\n", inet_ntoa(go->ouraddr)));
+ IPCPDEBUG((LOG_NOTICE, "remote IP address %s\n", inet_ntoa(ho->hisaddr)));
+ if (go->dnsaddr[0]) {
+ IPCPDEBUG((LOG_NOTICE, "primary DNS address %s\n", inet_ntoa(go->dnsaddr[0])));
+ }
+ if (go->dnsaddr[1]) {
+ IPCPDEBUG((LOG_NOTICE, "secondary DNS address %s\n", inet_ntoa(go->dnsaddr[1])));
+ }
+}
+
+
+/*
+ * ipcp_down - IPCP has gone DOWN.
+ *
+ * Take the IP network interface down, clear its addresses
+ * and delete routes through it.
+ */
+static void ipcp_down(fsm *f)
+{
+ IPCPDEBUG((LOG_INFO, "ipcp: down\n"));
+ np_down(f->unit, PPP_IP);
+ sifvjcomp(f->unit, 0, 0, 0);
+
+ sifdown(f->unit);
+ ipcp_clear_addrs(f->unit);
+}
+
+
+/*
+ * ipcp_clear_addrs() - clear the interface addresses, routes, etc.
+ */
+static void ipcp_clear_addrs(int unit)
+{
+ u32_t ouraddr, hisaddr;
+
+ ouraddr = ipcp_gotoptions[unit].ouraddr;
+ hisaddr = ipcp_hisoptions[unit].hisaddr;
+ if (default_route_set[unit]) {
+ cifdefaultroute(unit, ouraddr, hisaddr);
+ default_route_set[unit] = 0;
+ }
+ cifaddr(unit, ouraddr, hisaddr);
+}
+
+
+/*
+ * ipcp_finished - possibly shut down the lower layers.
+ */
+static void ipcp_finished(fsm *f)
+{
+ np_finished(f->unit, PPP_IP);
+}
+
+#if 0
+static int ipcp_printpkt(
+ u_char *p,
+ int plen,
+ void (*printer) (void *, char *, ...),
+ void *arg
+)
+{
+ (void)p;
+ (void)plen;
+ (void)printer;
+ (void)arg;
+ return 0;
+}
+
+/*
+ * ip_active_pkt - see if this IP packet is worth bringing the link up for.
+ * We don't bring the link up for IP fragments or for TCP FIN packets
+ * with no data.
+ */
+#define IP_HDRLEN 20 /* bytes */
+#define IP_OFFMASK 0x1fff
+#define IPPROTO_TCP 6
+#define TCP_HDRLEN 20
+#define TH_FIN 0x01
+
+/*
+ * We use these macros because the IP header may be at an odd address,
+ * and some compilers might use word loads to get th_off or ip_hl.
+ */
+
+#define net_short(x) (((x)[0] << 8) + (x)[1])
+#define get_iphl(x) (((unsigned char *)(x))[0] & 0xF)
+#define get_ipoff(x) net_short((unsigned char *)(x) + 6)
+#define get_ipproto(x) (((unsigned char *)(x))[9])
+#define get_tcpoff(x) (((unsigned char *)(x))[12] >> 4)
+#define get_tcpflags(x) (((unsigned char *)(x))[13])
+
+static int ip_active_pkt(u_char *pkt, int len)
+{
+ u_char *tcp;
+ int hlen;
+
+ len -= PPP_HDRLEN;
+ pkt += PPP_HDRLEN;
+ if (len < IP_HDRLEN)
+ return 0;
+ if ((get_ipoff(pkt) & IP_OFFMASK) != 0)
+ return 0;
+ if (get_ipproto(pkt) != IPPROTO_TCP)
+ return 1;
+ hlen = get_iphl(pkt) * 4;
+ if (len < hlen + TCP_HDRLEN)
+ return 0;
+ tcp = pkt + hlen;
+ if ((get_tcpflags(tcp) & TH_FIN) != 0 && len == hlen + get_tcpoff(tcp) * 4)
+ return 0;
+ return 1;
+}
+#endif
+
+#endif /* PPP_SUPPORT */
--- /dev/null
+/*****************************************************************************
+* ipcp.h - PPP IP NCP: Internet Protocol Network Control Protocol header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher <marc@mbsi.ca>
+* Ported to lwIP.
+* 97-12-04 Guy Lancaster <glanca@gesn.com>, Global Election Systems Inc.
+* Original derived from BSD codes.
+*****************************************************************************/
+/*
+ * ipcp.h - IP Control Protocol definitions.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University. The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * $Id: ipcp.h,v 1.1 2003/05/27 14:37:56 jani Exp $
+ */
+
+#ifndef IPCP_H
+#define IPCP_H
+
+/*************************
+*** PUBLIC DEFINITIONS ***
+*************************/
+/*
+ * Options.
+ */
+#define CI_ADDRS 1 /* IP Addresses */
+#define CI_COMPRESSTYPE 2 /* Compression Type */
+#define CI_ADDR 3
+
+#define CI_MS_WINS1 128 /* Primary WINS value */
+#define CI_MS_DNS1 129 /* Primary DNS value */
+#define CI_MS_WINS2 130 /* Secondary WINS value */
+#define CI_MS_DNS2 131 /* Secondary DNS value */
+
+#define IPCP_VJMODE_OLD 1 /* "old" mode (option # = 0x0037) */
+#define IPCP_VJMODE_RFC1172 2 /* "old-rfc"mode (option # = 0x002d) */
+#define IPCP_VJMODE_RFC1332 3 /* "new-rfc"mode (option # = 0x002d, */
+ /* maxslot and slot number compression) */
+
+#define IPCP_VJ_COMP 0x002d /* current value for VJ compression option*/
+#define IPCP_VJ_COMP_OLD 0x0037 /* "old" (i.e, broken) value for VJ */
+ /* compression option*/
+
+
+/************************
+*** PUBLIC DATA TYPES ***
+************************/
+
+typedef struct ipcp_options {
+ u_int neg_addr : 1; /* Negotiate IP Address? */
+ u_int old_addrs : 1; /* Use old (IP-Addresses) option? */
+ u_int req_addr : 1; /* Ask peer to send IP address? */
+ u_int default_route : 1; /* Assign default route through interface? */
+ u_int proxy_arp : 1; /* Make proxy ARP entry for peer? */
+ u_int neg_vj : 1; /* Van Jacobson Compression? */
+ u_int old_vj : 1; /* use old (short) form of VJ option? */
+ u_int accept_local : 1; /* accept peer's value for ouraddr */
+ u_int accept_remote : 1; /* accept peer's value for hisaddr */
+ u_int req_dns1 : 1; /* Ask peer to send primary DNS address? */
+ u_int req_dns2 : 1; /* Ask peer to send secondary DNS address? */
+ u_short vj_protocol; /* protocol value to use in VJ option */
+ u_char maxslotindex; /* VJ slots - 1. */
+ u_char cflag; /* VJ slot compression flag. */
+ u32_t ouraddr, hisaddr; /* Addresses in NETWORK BYTE ORDER */
+ u32_t dnsaddr[2]; /* Primary and secondary MS DNS entries */
+ u32_t winsaddr[2]; /* Primary and secondary MS WINS entries */
+} ipcp_options;
+
+
+/*****************************
+*** PUBLIC DATA STRUCTURES ***
+*****************************/
+
+extern fsm ipcp_fsm[];
+extern ipcp_options ipcp_wantoptions[];
+extern ipcp_options ipcp_gotoptions[];
+extern ipcp_options ipcp_allowoptions[];
+extern ipcp_options ipcp_hisoptions[];
+
+extern struct protent ipcp_protent;
+
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+
+
+#endif /* IPCP_H */
+
--- /dev/null
+/*****************************************************************************
+* lcp.c - Network Link Control Protocol program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher <marc@mbsi.ca>
+* Ported to lwIP.
+* 97-12-01 Guy Lancaster <lancasterg@acm.org>, Global Election Systems Inc.
+* Original.
+*****************************************************************************/
+
+/*
+ * lcp.c - PPP Link Control Protocol.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University. The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include <string.h>
+
+#include "ppp.h"
+#if PPP_SUPPORT > 0
+#include "fsm.h"
+#include "chap.h"
+#include "magic.h"
+#include "auth.h"
+#include "lcp.h"
+#include "pppdebug.h"
+
+
+/*************************/
+/*** LOCAL DEFINITIONS ***/
+/*************************/
+/*
+ * Length of each type of configuration option (in octets)
+ */
+#define CILEN_VOID 2
+#define CILEN_CHAR 3
+#define CILEN_SHORT 4 /* CILEN_VOID + sizeof(short) */
+#define CILEN_CHAP 5 /* CILEN_VOID + sizeof(short) + 1 */
+#define CILEN_LONG 6 /* CILEN_VOID + sizeof(long) */
+#define CILEN_LQR 8 /* CILEN_VOID + sizeof(short) + sizeof(long) */
+#define CILEN_CBCP 3
+
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+/*
+ * Callbacks for fsm code. (CI = Configuration Information)
+ */
+static void lcp_resetci (fsm*); /* Reset our CI */
+static int lcp_cilen (fsm*); /* Return length of our CI */
+static void lcp_addci (fsm*, u_char*, int*); /* Add our CI to pkt */
+static int lcp_ackci (fsm*, u_char*, int);/* Peer ack'd our CI */
+static int lcp_nakci (fsm*, u_char*, int);/* Peer nak'd our CI */
+static int lcp_rejci (fsm*, u_char*, int);/* Peer rej'd our CI */
+static int lcp_reqci (fsm*, u_char*, int*, int); /* Rcv peer CI */
+static void lcp_up (fsm*); /* We're UP */
+static void lcp_down (fsm*); /* We're DOWN */
+static void lcp_starting (fsm*); /* We need lower layer up */
+static void lcp_finished (fsm*); /* We need lower layer down */
+static int lcp_extcode (fsm*, int, u_char, u_char*, int);
+
+static void lcp_rprotrej (fsm*, u_char*, int);
+
+/*
+ * routines to send LCP echos to peer
+ */
+static void lcp_echo_lowerup (int);
+static void lcp_echo_lowerdown (int);
+static void LcpEchoTimeout (void*);
+static void lcp_received_echo_reply (fsm*, int, u_char*, int);
+static void LcpSendEchoRequest (fsm*);
+static void LcpLinkFailure (fsm*);
+static void LcpEchoCheck (fsm*);
+
+/*
+ * Protocol entry points.
+ * Some of these are called directly.
+ */
+static void lcp_input (int, u_char *, int);
+static void lcp_protrej (int);
+
+#define CODENAME(x) ((x) == CONFACK ? "ACK" : \
+ (x) == CONFNAK ? "NAK" : "REJ")
+
+
+/******************************/
+/*** PUBLIC DATA STRUCTURES ***/
+/******************************/
+/* global vars */
+LinkPhase lcp_phase[NUM_PPP]; /* Phase of link session (RFC 1661) */
+lcp_options lcp_wantoptions[NUM_PPP]; /* Options that we want to request */
+lcp_options lcp_gotoptions[NUM_PPP]; /* Options that peer ack'd */
+lcp_options lcp_allowoptions[NUM_PPP]; /* Options we allow peer to request */
+lcp_options lcp_hisoptions[NUM_PPP]; /* Options that we ack'd */
+ext_accm xmit_accm[NUM_PPP]; /* extended transmit ACCM */
+
+
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+static fsm lcp_fsm[NUM_PPP]; /* LCP fsm structure (global)*/
+static u_int lcp_echo_interval = LCP_ECHOINTERVAL; /* Interval between LCP echo-requests */
+static u_int lcp_echo_fails = LCP_MAXECHOFAILS; /* Tolerance to unanswered echo-requests */
+static u32_t lcp_echos_pending = 0; /* Number of outstanding echo msgs */
+static u32_t lcp_echo_number = 0; /* ID number of next echo frame */
+static u32_t lcp_echo_timer_running = 0; /* TRUE if a timer is running */
+
+static u_char nak_buffer[PPP_MRU]; /* where we construct a nak packet */
+
+static fsm_callbacks lcp_callbacks = { /* LCP callback routines */
+ lcp_resetci, /* Reset our Configuration Information */
+ lcp_cilen, /* Length of our Configuration Information */
+ lcp_addci, /* Add our Configuration Information */
+ lcp_ackci, /* ACK our Configuration Information */
+ lcp_nakci, /* NAK our Configuration Information */
+ lcp_rejci, /* Reject our Configuration Information */
+ lcp_reqci, /* Request peer's Configuration Information */
+ lcp_up, /* Called when fsm reaches OPENED state */
+ lcp_down, /* Called when fsm leaves OPENED state */
+ lcp_starting, /* Called when we want the lower layer up */
+ lcp_finished, /* Called when we want the lower layer down */
+ NULL, /* Called when Protocol-Reject received */
+ NULL, /* Retransmission is necessary */
+ lcp_extcode, /* Called to handle LCP-specific codes */
+ "LCP" /* String name of protocol */
+};
+
+struct protent lcp_protent = {
+ PPP_LCP,
+ lcp_init,
+ lcp_input,
+ lcp_protrej,
+ lcp_lowerup,
+ lcp_lowerdown,
+ lcp_open,
+ lcp_close,
+#if 0
+ lcp_printpkt,
+ NULL,
+#endif
+ 1,
+ "LCP",
+#if 0
+ NULL,
+ NULL,
+ NULL
+#endif
+};
+
+int lcp_loopbackfail = DEFLOOPBACKFAIL;
+
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/*
+ * lcp_init - Initialize LCP.
+ */
+void lcp_init(int unit)
+{
+ fsm *f = &lcp_fsm[unit];
+ lcp_options *wo = &lcp_wantoptions[unit];
+ lcp_options *ao = &lcp_allowoptions[unit];
+
+ f->unit = unit;
+ f->protocol = PPP_LCP;
+ f->callbacks = &lcp_callbacks;
+
+ fsm_init(f);
+
+ wo->passive = 0;
+ wo->silent = 0;
+ wo->restart = 0; /* Set to 1 in kernels or multi-line
+ * implementations */
+ wo->neg_mru = 1;
+ wo->mru = PPP_DEFMRU;
+ wo->neg_asyncmap = 1;
+ wo->asyncmap = 0x00000000l; /* Assume don't need to escape any ctl chars. */
+ wo->neg_chap = 0; /* Set to 1 on server */
+ wo->neg_upap = 0; /* Set to 1 on server */
+ wo->chap_mdtype = CHAP_DIGEST_MD5;
+ wo->neg_magicnumber = 1;
+ wo->neg_pcompression = 1;
+ wo->neg_accompression = 1;
+ wo->neg_lqr = 0; /* no LQR implementation yet */
+ wo->neg_cbcp = 0;
+
+ ao->neg_mru = 1;
+ ao->mru = PPP_MAXMRU;
+ ao->neg_asyncmap = 1;
+ ao->asyncmap = 0x00000000l; /* Assume don't need to escape any ctl chars. */
+ ao->neg_chap = (CHAP_SUPPORT != 0);
+ ao->chap_mdtype = CHAP_DIGEST_MD5;
+ ao->neg_upap = (PAP_SUPPORT != 0);
+ ao->neg_magicnumber = 1;
+ ao->neg_pcompression = 1;
+ ao->neg_accompression = 1;
+ ao->neg_lqr = 0; /* no LQR implementation yet */
+ ao->neg_cbcp = (CBCP_SUPPORT != 0);
+
+ /*
+ * Set transmit escape for the flag and escape characters plus anything
+ * set for the allowable options.
+ */
+ memset(xmit_accm[unit], 0, sizeof(xmit_accm[0]));
+ xmit_accm[unit][15] = 0x60;
+ xmit_accm[unit][0] = (u_char)(ao->asyncmap & 0xFF);
+ xmit_accm[unit][1] = (u_char)((ao->asyncmap >> 8) & 0xFF);
+ xmit_accm[unit][2] = (u_char)((ao->asyncmap >> 16) & 0xFF);
+ xmit_accm[unit][3] = (u_char)((ao->asyncmap >> 24) & 0xFF);
+ LCPDEBUG((LOG_INFO, "lcp_init: xmit_accm=%X %X %X %X\n",
+ xmit_accm[unit][0],
+ xmit_accm[unit][1],
+ xmit_accm[unit][2],
+ xmit_accm[unit][3]));
+
+ lcp_phase[unit] = PHASE_INITIALIZE;
+}
+
+
+/*
+ * lcp_open - LCP is allowed to come up.
+ */
+void lcp_open(int unit)
+{
+ fsm *f = &lcp_fsm[unit];
+ lcp_options *wo = &lcp_wantoptions[unit];
+
+ f->flags = 0;
+ if (wo->passive)
+ f->flags |= OPT_PASSIVE;
+ if (wo->silent)
+ f->flags |= OPT_SILENT;
+ fsm_open(f);
+
+ lcp_phase[unit] = PHASE_ESTABLISH;
+}
+
+
+/*
+ * lcp_close - Take LCP down.
+ */
+void lcp_close(int unit, char *reason)
+{
+ fsm *f = &lcp_fsm[unit];
+
+ if (lcp_phase[unit] != PHASE_DEAD)
+ lcp_phase[unit] = PHASE_TERMINATE;
+ if (f->state == STOPPED && f->flags & (OPT_PASSIVE|OPT_SILENT)) {
+ /*
+ * This action is not strictly according to the FSM in RFC1548,
+ * but it does mean that the program terminates if you do an
+ * lcp_close() in passive/silent mode when a connection hasn't
+ * been established.
+ */
+ f->state = CLOSED;
+ lcp_finished(f);
+ }
+ else
+ fsm_close(&lcp_fsm[unit], reason);
+}
+
+
+/*
+ * lcp_lowerup - The lower layer is up.
+ */
+void lcp_lowerup(int unit)
+{
+ lcp_options *wo = &lcp_wantoptions[unit];
+
+ /*
+ * Don't use A/C or protocol compression on transmission,
+ * but accept A/C and protocol compressed packets
+ * if we are going to ask for A/C and protocol compression.
+ */
+ ppp_set_xaccm(unit, &xmit_accm[unit]);
+ ppp_send_config(unit, PPP_MRU, 0xffffffffl, 0, 0);
+ ppp_recv_config(unit, PPP_MRU, 0x00000000l,
+ wo->neg_pcompression, wo->neg_accompression);
+ peer_mru[unit] = PPP_MRU;
+ lcp_allowoptions[unit].asyncmap
+ = (u_long)xmit_accm[unit][0]
+ | ((u_long)xmit_accm[unit][1] << 8)
+ | ((u_long)xmit_accm[unit][2] << 16)
+ | ((u_long)xmit_accm[unit][3] << 24);
+ LCPDEBUG((LOG_INFO, "lcp_lowerup: asyncmap=%X %X %X %X\n",
+ xmit_accm[unit][3],
+ xmit_accm[unit][2],
+ xmit_accm[unit][1],
+ xmit_accm[unit][0]));
+
+ fsm_lowerup(&lcp_fsm[unit]);
+}
+
+
+/*
+ * lcp_lowerdown - The lower layer is down.
+ */
+void lcp_lowerdown(int unit)
+{
+ fsm_lowerdown(&lcp_fsm[unit]);
+}
+
+/*
+ * lcp_sprotrej - Send a Protocol-Reject for some protocol.
+ */
+void lcp_sprotrej(int unit, u_char *p, int len)
+{
+ /*
+ * Send back the protocol and the information field of the
+ * rejected packet. We only get here if LCP is in the OPENED state.
+ */
+
+ fsm_sdata(&lcp_fsm[unit], PROTREJ, ++lcp_fsm[unit].id,
+ p, len);
+}
+
+
+
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+/*
+ * lcp_input - Input LCP packet.
+ */
+static void lcp_input(int unit, u_char *p, int len)
+{
+ fsm *f = &lcp_fsm[unit];
+
+ fsm_input(f, p, len);
+}
+
+
+/*
+ * lcp_extcode - Handle a LCP-specific code.
+ */
+static int lcp_extcode(fsm *f, int code, u_char id, u_char *inp, int len)
+{
+ u_char *magp;
+
+ switch( code ){
+ case PROTREJ:
+ lcp_rprotrej(f, inp, len);
+ break;
+
+ case ECHOREQ:
+ if (f->state != OPENED)
+ break;
+ LCPDEBUG((LOG_INFO, "lcp: Echo-Request, Rcvd id %d\n", id));
+ magp = inp;
+ PUTLONG(lcp_gotoptions[f->unit].magicnumber, magp);
+ fsm_sdata(f, ECHOREP, id, inp, len);
+ break;
+
+ case ECHOREP:
+ lcp_received_echo_reply(f, id, inp, len);
+ break;
+
+ case DISCREQ:
+ break;
+
+ default:
+ return 0;
+ }
+ return 1;
+}
+
+
+/*
+ * lcp_rprotrej - Receive an Protocol-Reject.
+ *
+ * Figure out which protocol is rejected and inform it.
+ */
+static void lcp_rprotrej(fsm *f, u_char *inp, int len)
+{
+ int i;
+ struct protent *protp;
+ u_short prot;
+
+ if (len < sizeof (u_short)) {
+ LCPDEBUG((LOG_INFO,
+ "lcp_rprotrej: Rcvd short Protocol-Reject packet!\n"));
+ return;
+ }
+
+ GETSHORT(prot, inp);
+
+ LCPDEBUG((LOG_INFO,
+ "lcp_rprotrej: Rcvd Protocol-Reject packet for %x!\n",
+ prot));
+
+ /*
+ * Protocol-Reject packets received in any state other than the LCP
+ * OPENED state SHOULD be silently discarded.
+ */
+ if( f->state != OPENED ){
+ LCPDEBUG((LOG_INFO, "Protocol-Reject discarded: LCP in state %d\n",
+ f->state));
+ return;
+ }
+
+ /*
+ * Upcall the proper Protocol-Reject routine.
+ */
+ for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i)
+ if (protp->protocol == prot && protp->enabled_flag) {
+ (*protp->protrej)(f->unit);
+ return;
+ }
+
+ LCPDEBUG((LOG_WARNING, "Protocol-Reject for unsupported protocol 0x%x\n",
+ prot));
+}
+
+
+/*
+ * lcp_protrej - A Protocol-Reject was received.
+ */
+static void lcp_protrej(int unit)
+{
+ (void)unit;
+ /*
+ * Can't reject LCP!
+ */
+ LCPDEBUG((LOG_WARNING,
+ "lcp_protrej: Received Protocol-Reject for LCP!\n"));
+ fsm_protreject(&lcp_fsm[unit]);
+}
+
+
+/*
+ * lcp_resetci - Reset our CI.
+ */
+static void lcp_resetci(fsm *f)
+{
+ lcp_wantoptions[f->unit].magicnumber = magic();
+ lcp_wantoptions[f->unit].numloops = 0;
+ lcp_gotoptions[f->unit] = lcp_wantoptions[f->unit];
+ peer_mru[f->unit] = PPP_MRU;
+ auth_reset(f->unit);
+}
+
+
+/*
+ * lcp_cilen - Return length of our CI.
+ */
+static int lcp_cilen(fsm *f)
+{
+ lcp_options *go = &lcp_gotoptions[f->unit];
+
+#define LENCIVOID(neg) ((neg) ? CILEN_VOID : 0)
+#define LENCICHAP(neg) ((neg) ? CILEN_CHAP : 0)
+#define LENCISHORT(neg) ((neg) ? CILEN_SHORT : 0)
+#define LENCILONG(neg) ((neg) ? CILEN_LONG : 0)
+#define LENCILQR(neg) ((neg) ? CILEN_LQR: 0)
+#define LENCICBCP(neg) ((neg) ? CILEN_CBCP: 0)
+ /*
+ * NB: we only ask for one of CHAP and UPAP, even if we will
+ * accept either.
+ */
+ return (LENCISHORT(go->neg_mru && go->mru != PPP_DEFMRU) +
+ LENCILONG(go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl) +
+ LENCICHAP(go->neg_chap) +
+ LENCISHORT(!go->neg_chap && go->neg_upap) +
+ LENCILQR(go->neg_lqr) +
+ LENCICBCP(go->neg_cbcp) +
+ LENCILONG(go->neg_magicnumber) +
+ LENCIVOID(go->neg_pcompression) +
+ LENCIVOID(go->neg_accompression));
+}
+
+
+/*
+ * lcp_addci - Add our desired CIs to a packet.
+ */
+static void lcp_addci(fsm *f, u_char *ucp, int *lenp)
+{
+ lcp_options *go = &lcp_gotoptions[f->unit];
+ u_char *start_ucp = ucp;
+
+#define ADDCIVOID(opt, neg) \
+ if (neg) { \
+ LCPDEBUG((LOG_INFO, "lcp_addci: opt=%d\n", opt)); \
+ PUTCHAR(opt, ucp); \
+ PUTCHAR(CILEN_VOID, ucp); \
+ }
+#define ADDCISHORT(opt, neg, val) \
+ if (neg) { \
+ LCPDEBUG((LOG_INFO, "lcp_addci: INT opt=%d %X\n", opt, val)); \
+ PUTCHAR(opt, ucp); \
+ PUTCHAR(CILEN_SHORT, ucp); \
+ PUTSHORT(val, ucp); \
+ }
+#define ADDCICHAP(opt, neg, val, digest) \
+ if (neg) { \
+ LCPDEBUG((LOG_INFO, "lcp_addci: CHAP opt=%d %X\n", opt, val)); \
+ PUTCHAR(opt, ucp); \
+ PUTCHAR(CILEN_CHAP, ucp); \
+ PUTSHORT(val, ucp); \
+ PUTCHAR(digest, ucp); \
+ }
+#define ADDCILONG(opt, neg, val) \
+ if (neg) { \
+ LCPDEBUG((LOG_INFO, "lcp_addci: L opt=%d %lX\n", opt, val)); \
+ PUTCHAR(opt, ucp); \
+ PUTCHAR(CILEN_LONG, ucp); \
+ PUTLONG(val, ucp); \
+ }
+#define ADDCILQR(opt, neg, val) \
+ if (neg) { \
+ LCPDEBUG((LOG_INFO, "lcp_addci: LQR opt=%d %lX\n", opt, val)); \
+ PUTCHAR(opt, ucp); \
+ PUTCHAR(CILEN_LQR, ucp); \
+ PUTSHORT(PPP_LQR, ucp); \
+ PUTLONG(val, ucp); \
+ }
+#define ADDCICHAR(opt, neg, val) \
+ if (neg) { \
+ LCPDEBUG((LOG_INFO, "lcp_addci: CHAR opt=%d %X '%z'\n", opt, val, val)); \
+ PUTCHAR(opt, ucp); \
+ PUTCHAR(CILEN_CHAR, ucp); \
+ PUTCHAR(val, ucp); \
+ }
+
+ ADDCISHORT(CI_MRU, go->neg_mru && go->mru != PPP_DEFMRU, go->mru);
+ ADDCILONG(CI_ASYNCMAP, go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl,
+ go->asyncmap);
+ ADDCICHAP(CI_AUTHTYPE, go->neg_chap, PPP_CHAP, go->chap_mdtype);
+ ADDCISHORT(CI_AUTHTYPE, !go->neg_chap && go->neg_upap, PPP_PAP);
+ ADDCILQR(CI_QUALITY, go->neg_lqr, go->lqr_period);
+ ADDCICHAR(CI_CALLBACK, go->neg_cbcp, CBCP_OPT);
+ ADDCILONG(CI_MAGICNUMBER, go->neg_magicnumber, go->magicnumber);
+ ADDCIVOID(CI_PCOMPRESSION, go->neg_pcompression);
+ ADDCIVOID(CI_ACCOMPRESSION, go->neg_accompression);
+
+ if (ucp - start_ucp != *lenp) {
+ /* this should never happen, because peer_mtu should be 1500 */
+ LCPDEBUG((LOG_ERR, "Bug in lcp_addci: wrong length\n"));
+ }
+}
+
+
+/*
+ * lcp_ackci - Ack our CIs.
+ * This should not modify any state if the Ack is bad.
+ *
+ * Returns:
+ * 0 - Ack was bad.
+ * 1 - Ack was good.
+ */
+static int lcp_ackci(fsm *f, u_char *p, int len)
+{
+ lcp_options *go = &lcp_gotoptions[f->unit];
+ u_char cilen, citype, cichar;
+ u_short cishort;
+ u32_t cilong;
+
+ /*
+ * CIs must be in exactly the same order that we sent.
+ * Check packet length and CI length at each step.
+ * If we find any deviations, then this packet is bad.
+ */
+#define ACKCIVOID(opt, neg) \
+ if (neg) { \
+ if ((len -= CILEN_VOID) < 0) \
+ goto bad; \
+ GETCHAR(citype, p); \
+ GETCHAR(cilen, p); \
+ if (cilen != CILEN_VOID || \
+ citype != opt) \
+ goto bad; \
+ }
+#define ACKCISHORT(opt, neg, val) \
+ if (neg) { \
+ if ((len -= CILEN_SHORT) < 0) \
+ goto bad; \
+ GETCHAR(citype, p); \
+ GETCHAR(cilen, p); \
+ if (cilen != CILEN_SHORT || \
+ citype != opt) \
+ goto bad; \
+ GETSHORT(cishort, p); \
+ if (cishort != val) \
+ goto bad; \
+ }
+#define ACKCICHAR(opt, neg, val) \
+ if (neg) { \
+ if ((len -= CILEN_CHAR) < 0) \
+ goto bad; \
+ GETCHAR(citype, p); \
+ GETCHAR(cilen, p); \
+ if (cilen != CILEN_CHAR || \
+ citype != opt) \
+ goto bad; \
+ GETCHAR(cichar, p); \
+ if (cichar != val) \
+ goto bad; \
+ }
+#define ACKCICHAP(opt, neg, val, digest) \
+ if (neg) { \
+ if ((len -= CILEN_CHAP) < 0) \
+ goto bad; \
+ GETCHAR(citype, p); \
+ GETCHAR(cilen, p); \
+ if (cilen != CILEN_CHAP || \
+ citype != opt) \
+ goto bad; \
+ GETSHORT(cishort, p); \
+ if (cishort != val) \
+ goto bad; \
+ GETCHAR(cichar, p); \
+ if (cichar != digest) \
+ goto bad; \
+ }
+#define ACKCILONG(opt, neg, val) \
+ if (neg) { \
+ if ((len -= CILEN_LONG) < 0) \
+ goto bad; \
+ GETCHAR(citype, p); \
+ GETCHAR(cilen, p); \
+ if (cilen != CILEN_LONG || \
+ citype != opt) \
+ goto bad; \
+ GETLONG(cilong, p); \
+ if (cilong != val) \
+ goto bad; \
+ }
+#define ACKCILQR(opt, neg, val) \
+ if (neg) { \
+ if ((len -= CILEN_LQR) < 0) \
+ goto bad; \
+ GETCHAR(citype, p); \
+ GETCHAR(cilen, p); \
+ if (cilen != CILEN_LQR || \
+ citype != opt) \
+ goto bad; \
+ GETSHORT(cishort, p); \
+ if (cishort != PPP_LQR) \
+ goto bad; \
+ GETLONG(cilong, p); \
+ if (cilong != val) \
+ goto bad; \
+ }
+
+ ACKCISHORT(CI_MRU, go->neg_mru && go->mru != PPP_DEFMRU, go->mru);
+ ACKCILONG(CI_ASYNCMAP, go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl,
+ go->asyncmap);
+ ACKCICHAP(CI_AUTHTYPE, go->neg_chap, PPP_CHAP, go->chap_mdtype);
+ ACKCISHORT(CI_AUTHTYPE, !go->neg_chap && go->neg_upap, PPP_PAP);
+ ACKCILQR(CI_QUALITY, go->neg_lqr, go->lqr_period);
+ ACKCICHAR(CI_CALLBACK, go->neg_cbcp, CBCP_OPT);
+ ACKCILONG(CI_MAGICNUMBER, go->neg_magicnumber, go->magicnumber);
+ ACKCIVOID(CI_PCOMPRESSION, go->neg_pcompression);
+ ACKCIVOID(CI_ACCOMPRESSION, go->neg_accompression);
+
+ /*
+ * If there are any remaining CIs, then this packet is bad.
+ */
+ if (len != 0)
+ goto bad;
+ LCPDEBUG((LOG_INFO, "lcp_acki: Ack\n"));
+ return (1);
+bad:
+ LCPDEBUG((LOG_WARNING, "lcp_acki: received bad Ack!\n"));
+ return (0);
+}
+
+
+/*
+ * lcp_nakci - Peer has sent a NAK for some of our CIs.
+ * This should not modify any state if the Nak is bad
+ * or if LCP is in the OPENED state.
+ *
+ * Returns:
+ * 0 - Nak was bad.
+ * 1 - Nak was good.
+ */
+static int lcp_nakci(fsm *f, u_char *p, int len)
+{
+ lcp_options *go = &lcp_gotoptions[f->unit];
+ lcp_options *wo = &lcp_wantoptions[f->unit];
+ u_char citype, cichar, *next;
+ u_short cishort;
+ u32_t cilong;
+ lcp_options no; /* options we've seen Naks for */
+ lcp_options try; /* options to request next time */
+ int looped_back = 0;
+ int cilen;
+
+ BZERO(&no, sizeof(no));
+ try = *go;
+
+ /*
+ * Any Nak'd CIs must be in exactly the same order that we sent.
+ * Check packet length and CI length at each step.
+ * If we find any deviations, then this packet is bad.
+ */
+#define NAKCIVOID(opt, neg, code) \
+ if (go->neg && \
+ len >= CILEN_VOID && \
+ p[1] == CILEN_VOID && \
+ p[0] == opt) { \
+ len -= CILEN_VOID; \
+ INCPTR(CILEN_VOID, p); \
+ no.neg = 1; \
+ code \
+ }
+#define NAKCICHAP(opt, neg, code) \
+ if (go->neg && \
+ len >= CILEN_CHAP && \
+ p[1] == CILEN_CHAP && \
+ p[0] == opt) { \
+ len -= CILEN_CHAP; \
+ INCPTR(2, p); \
+ GETSHORT(cishort, p); \
+ GETCHAR(cichar, p); \
+ no.neg = 1; \
+ code \
+ }
+#define NAKCICHAR(opt, neg, code) \
+ if (go->neg && \
+ len >= CILEN_CHAR && \
+ p[1] == CILEN_CHAR && \
+ p[0] == opt) { \
+ len -= CILEN_CHAR; \
+ INCPTR(2, p); \
+ GETCHAR(cichar, p); \
+ no.neg = 1; \
+ code \
+ }
+#define NAKCISHORT(opt, neg, code) \
+ if (go->neg && \
+ len >= CILEN_SHORT && \
+ p[1] == CILEN_SHORT && \
+ p[0] == opt) { \
+ len -= CILEN_SHORT; \
+ INCPTR(2, p); \
+ GETSHORT(cishort, p); \
+ no.neg = 1; \
+ code \
+ }
+#define NAKCILONG(opt, neg, code) \
+ if (go->neg && \
+ len >= CILEN_LONG && \
+ p[1] == CILEN_LONG && \
+ p[0] == opt) { \
+ len -= CILEN_LONG; \
+ INCPTR(2, p); \
+ GETLONG(cilong, p); \
+ no.neg = 1; \
+ code \
+ }
+#define NAKCILQR(opt, neg, code) \
+ if (go->neg && \
+ len >= CILEN_LQR && \
+ p[1] == CILEN_LQR && \
+ p[0] == opt) { \
+ len -= CILEN_LQR; \
+ INCPTR(2, p); \
+ GETSHORT(cishort, p); \
+ GETLONG(cilong, p); \
+ no.neg = 1; \
+ code \
+ }
+
+ /*
+ * We don't care if they want to send us smaller packets than
+ * we want. Therefore, accept any MRU less than what we asked for,
+ * but then ignore the new value when setting the MRU in the kernel.
+ * If they send us a bigger MRU than what we asked, accept it, up to
+ * the limit of the default MRU we'd get if we didn't negotiate.
+ */
+ if (go->neg_mru && go->mru != PPP_DEFMRU) {
+ NAKCISHORT(CI_MRU, neg_mru,
+ if (cishort <= wo->mru || cishort < PPP_DEFMRU)
+ try.mru = cishort;
+ );
+ }
+
+ /*
+ * Add any characters they want to our (receive-side) asyncmap.
+ */
+ if (go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl) {
+ NAKCILONG(CI_ASYNCMAP, neg_asyncmap,
+ try.asyncmap = go->asyncmap | cilong;
+ );
+ }
+
+ /*
+ * If they've nak'd our authentication-protocol, check whether
+ * they are proposing a different protocol, or a different
+ * hash algorithm for CHAP.
+ */
+ if ((go->neg_chap || go->neg_upap)
+ && len >= CILEN_SHORT
+ && p[0] == CI_AUTHTYPE && p[1] >= CILEN_SHORT && p[1] <= len) {
+ cilen = p[1];
+ len -= cilen;
+ no.neg_chap = go->neg_chap;
+ no.neg_upap = go->neg_upap;
+ INCPTR(2, p);
+ GETSHORT(cishort, p);
+ if (cishort == PPP_PAP && cilen == CILEN_SHORT) {
+ /*
+ * If we were asking for CHAP, they obviously don't want to do it.
+ * If we weren't asking for CHAP, then we were asking for PAP,
+ * in which case this Nak is bad.
+ */
+ if (!go->neg_chap)
+ goto bad;
+ try.neg_chap = 0;
+
+ } else if (cishort == PPP_CHAP && cilen == CILEN_CHAP) {
+ GETCHAR(cichar, p);
+ if (go->neg_chap) {
+ /*
+ * We were asking for CHAP/MD5; they must want a different
+ * algorithm. If they can't do MD5, we'll have to stop
+ * asking for CHAP.
+ */
+ if (cichar != go->chap_mdtype)
+ try.neg_chap = 0;
+ } else {
+ /*
+ * Stop asking for PAP if we were asking for it.
+ */
+ try.neg_upap = 0;
+ }
+
+ } else {
+ /*
+ * We don't recognize what they're suggesting.
+ * Stop asking for what we were asking for.
+ */
+ if (go->neg_chap)
+ try.neg_chap = 0;
+ else
+ try.neg_upap = 0;
+ p += cilen - CILEN_SHORT;
+ }
+ }
+
+ /*
+ * If they can't cope with our link quality protocol, we'll have
+ * to stop asking for LQR. We haven't got any other protocol.
+ * If they Nak the reporting period, take their value XXX ?
+ */
+ NAKCILQR(CI_QUALITY, neg_lqr,
+ if (cishort != PPP_LQR)
+ try.neg_lqr = 0;
+ else
+ try.lqr_period = cilong;
+ );
+
+ /*
+ * Only implementing CBCP...not the rest of the callback options
+ */
+ NAKCICHAR(CI_CALLBACK, neg_cbcp,
+ try.neg_cbcp = 0;
+ );
+
+ /*
+ * Check for a looped-back line.
+ */
+ NAKCILONG(CI_MAGICNUMBER, neg_magicnumber,
+ try.magicnumber = magic();
+ looped_back = 1;
+ );
+
+ /*
+ * Peer shouldn't send Nak for protocol compression or
+ * address/control compression requests; they should send
+ * a Reject instead. If they send a Nak, treat it as a Reject.
+ */
+ NAKCIVOID(CI_PCOMPRESSION, neg_pcompression,
+ try.neg_pcompression = 0;
+ );
+ NAKCIVOID(CI_ACCOMPRESSION, neg_accompression,
+ try.neg_accompression = 0;
+ );
+
+ /*
+ * There may be remaining CIs, if the peer is requesting negotiation
+ * on an option that we didn't include in our request packet.
+ * If we see an option that we requested, or one we've already seen
+ * in this packet, then this packet is bad.
+ * If we wanted to respond by starting to negotiate on the requested
+ * option(s), we could, but we don't, because except for the
+ * authentication type and quality protocol, if we are not negotiating
+ * an option, it is because we were told not to.
+ * For the authentication type, the Nak from the peer means
+ * `let me authenticate myself with you' which is a bit pointless.
+ * For the quality protocol, the Nak means `ask me to send you quality
+ * reports', but if we didn't ask for them, we don't want them.
+ * An option we don't recognize represents the peer asking to
+ * negotiate some option we don't support, so ignore it.
+ */
+ while (len > CILEN_VOID) {
+ GETCHAR(citype, p);
+ GETCHAR(cilen, p);
+ if (cilen < CILEN_VOID || (len -= cilen) < 0)
+ goto bad;
+ next = p + cilen - 2;
+
+ switch (citype) {
+ case CI_MRU:
+ if ((go->neg_mru && go->mru != PPP_DEFMRU)
+ || no.neg_mru || cilen != CILEN_SHORT)
+ goto bad;
+ GETSHORT(cishort, p);
+ if (cishort < PPP_DEFMRU)
+ try.mru = cishort;
+ break;
+ case CI_ASYNCMAP:
+ if ((go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl)
+ || no.neg_asyncmap || cilen != CILEN_LONG)
+ goto bad;
+ break;
+ case CI_AUTHTYPE:
+ if (go->neg_chap || no.neg_chap || go->neg_upap || no.neg_upap)
+ goto bad;
+ break;
+ case CI_MAGICNUMBER:
+ if (go->neg_magicnumber || no.neg_magicnumber ||
+ cilen != CILEN_LONG)
+ goto bad;
+ break;
+ case CI_PCOMPRESSION:
+ if (go->neg_pcompression || no.neg_pcompression
+ || cilen != CILEN_VOID)
+ goto bad;
+ break;
+ case CI_ACCOMPRESSION:
+ if (go->neg_accompression || no.neg_accompression
+ || cilen != CILEN_VOID)
+ goto bad;
+ break;
+ case CI_QUALITY:
+ if (go->neg_lqr || no.neg_lqr || cilen != CILEN_LQR)
+ goto bad;
+ break;
+ }
+ p = next;
+ }
+
+ /* If there is still anything left, this packet is bad. */
+ if (len != 0)
+ goto bad;
+
+ /*
+ * OK, the Nak is good. Now we can update state.
+ */
+ if (f->state != OPENED) {
+ if (looped_back) {
+ if (++try.numloops >= lcp_loopbackfail) {
+ LCPDEBUG((LOG_NOTICE, "Serial line is looped back.\n"));
+ lcp_close(f->unit, "Loopback detected");
+ }
+ }
+ else
+ try.numloops = 0;
+ *go = try;
+ }
+
+ return 1;
+
+bad:
+ LCPDEBUG((LOG_WARNING, "lcp_nakci: received bad Nak!\n"));
+ return 0;
+}
+
+
+/*
+ * lcp_rejci - Peer has Rejected some of our CIs.
+ * This should not modify any state if the Reject is bad
+ * or if LCP is in the OPENED state.
+ *
+ * Returns:
+ * 0 - Reject was bad.
+ * 1 - Reject was good.
+ */
+static int lcp_rejci(fsm *f, u_char *p, int len)
+{
+ lcp_options *go = &lcp_gotoptions[f->unit];
+ u_char cichar;
+ u_short cishort;
+ u32_t cilong;
+ lcp_options try; /* options to request next time */
+
+ try = *go;
+
+ /*
+ * Any Rejected CIs must be in exactly the same order that we sent.
+ * Check packet length and CI length at each step.
+ * If we find any deviations, then this packet is bad.
+ */
+#define REJCIVOID(opt, neg) \
+ if (go->neg && \
+ len >= CILEN_VOID && \
+ p[1] == CILEN_VOID && \
+ p[0] == opt) { \
+ len -= CILEN_VOID; \
+ INCPTR(CILEN_VOID, p); \
+ try.neg = 0; \
+ LCPDEBUG((LOG_INFO, "lcp_rejci: void opt %d rejected\n", opt)); \
+ }
+#define REJCISHORT(opt, neg, val) \
+ if (go->neg && \
+ len >= CILEN_SHORT && \
+ p[1] == CILEN_SHORT && \
+ p[0] == opt) { \
+ len -= CILEN_SHORT; \
+ INCPTR(2, p); \
+ GETSHORT(cishort, p); \
+ /* Check rejected value. */ \
+ if (cishort != val) \
+ goto bad; \
+ try.neg = 0; \
+ LCPDEBUG((LOG_INFO,"lcp_rejci: short opt %d rejected\n", opt)); \
+ }
+#define REJCICHAP(opt, neg, val, digest) \
+ if (go->neg && \
+ len >= CILEN_CHAP && \
+ p[1] == CILEN_CHAP && \
+ p[0] == opt) { \
+ len -= CILEN_CHAP; \
+ INCPTR(2, p); \
+ GETSHORT(cishort, p); \
+ GETCHAR(cichar, p); \
+ /* Check rejected value. */ \
+ if (cishort != val || cichar != digest) \
+ goto bad; \
+ try.neg = 0; \
+ try.neg_upap = 0; \
+ LCPDEBUG((LOG_INFO,"lcp_rejci: chap opt %d rejected\n", opt)); \
+ }
+#define REJCILONG(opt, neg, val) \
+ if (go->neg && \
+ len >= CILEN_LONG && \
+ p[1] == CILEN_LONG && \
+ p[0] == opt) { \
+ len -= CILEN_LONG; \
+ INCPTR(2, p); \
+ GETLONG(cilong, p); \
+ /* Check rejected value. */ \
+ if (cilong != val) \
+ goto bad; \
+ try.neg = 0; \
+ LCPDEBUG((LOG_INFO,"lcp_rejci: long opt %d rejected\n", opt)); \
+ }
+#define REJCILQR(opt, neg, val) \
+ if (go->neg && \
+ len >= CILEN_LQR && \
+ p[1] == CILEN_LQR && \
+ p[0] == opt) { \
+ len -= CILEN_LQR; \
+ INCPTR(2, p); \
+ GETSHORT(cishort, p); \
+ GETLONG(cilong, p); \
+ /* Check rejected value. */ \
+ if (cishort != PPP_LQR || cilong != val) \
+ goto bad; \
+ try.neg = 0; \
+ LCPDEBUG((LOG_INFO,"lcp_rejci: LQR opt %d rejected\n", opt)); \
+ }
+#define REJCICBCP(opt, neg, val) \
+ if (go->neg && \
+ len >= CILEN_CBCP && \
+ p[1] == CILEN_CBCP && \
+ p[0] == opt) { \
+ len -= CILEN_CBCP; \
+ INCPTR(2, p); \
+ GETCHAR(cichar, p); \
+ /* Check rejected value. */ \
+ if (cichar != val) \
+ goto bad; \
+ try.neg = 0; \
+ LCPDEBUG((LOG_INFO,"lcp_rejci: Callback opt %d rejected\n", opt)); \
+ }
+
+ REJCISHORT(CI_MRU, neg_mru, go->mru);
+ REJCILONG(CI_ASYNCMAP, neg_asyncmap, go->asyncmap);
+ REJCICHAP(CI_AUTHTYPE, neg_chap, PPP_CHAP, go->chap_mdtype);
+ if (!go->neg_chap) {
+ REJCISHORT(CI_AUTHTYPE, neg_upap, PPP_PAP);
+ }
+ REJCILQR(CI_QUALITY, neg_lqr, go->lqr_period);
+ REJCICBCP(CI_CALLBACK, neg_cbcp, CBCP_OPT);
+ REJCILONG(CI_MAGICNUMBER, neg_magicnumber, go->magicnumber);
+ REJCIVOID(CI_PCOMPRESSION, neg_pcompression);
+ REJCIVOID(CI_ACCOMPRESSION, neg_accompression);
+
+ /*
+ * If there are any remaining CIs, then this packet is bad.
+ */
+ if (len != 0)
+ goto bad;
+ /*
+ * Now we can update state.
+ */
+ if (f->state != OPENED)
+ *go = try;
+ return 1;
+
+bad:
+ LCPDEBUG((LOG_WARNING, "lcp_rejci: received bad Reject!\n"));
+ return 0;
+}
+
+
+/*
+ * lcp_reqci - Check the peer's requested CIs and send appropriate response.
+ *
+ * Returns: CONFACK, CONFNAK or CONFREJ and input packet modified
+ * appropriately. If reject_if_disagree is non-zero, doesn't return
+ * CONFNAK; returns CONFREJ if it can't return CONFACK.
+ */
+static int lcp_reqci(fsm *f,
+ u_char *inp, /* Requested CIs */
+ int *lenp, /* Length of requested CIs */
+ int reject_if_disagree)
+{
+ lcp_options *go = &lcp_gotoptions[f->unit];
+ lcp_options *ho = &lcp_hisoptions[f->unit];
+ lcp_options *ao = &lcp_allowoptions[f->unit];
+ u_char *cip, *next; /* Pointer to current and next CIs */
+ int cilen, citype, cichar; /* Parsed len, type, char value */
+ u_short cishort; /* Parsed short value */
+ u32_t cilong; /* Parse long value */
+ int rc = CONFACK; /* Final packet return code */
+ int orc; /* Individual option return code */
+ u_char *p; /* Pointer to next char to parse */
+ u_char *rejp; /* Pointer to next char in reject frame */
+ u_char *nakp; /* Pointer to next char in Nak frame */
+ int l = *lenp; /* Length left */
+#if TRACELCP > 0
+ char traceBuf[80];
+ int traceNdx = 0;
+#endif
+
+ /*
+ * Reset all his options.
+ */
+ BZERO(ho, sizeof(*ho));
+
+ /*
+ * Process all his options.
+ */
+ next = inp;
+ nakp = nak_buffer;
+ rejp = inp;
+ while (l) {
+ orc = CONFACK; /* Assume success */
+ cip = p = next; /* Remember begining of CI */
+ if (l < 2 || /* Not enough data for CI header or */
+ p[1] < 2 || /* CI length too small or */
+ p[1] > l) { /* CI length too big? */
+ LCPDEBUG((LOG_WARNING, "lcp_reqci: bad CI length!\n"));
+ orc = CONFREJ; /* Reject bad CI */
+ cilen = l; /* Reject till end of packet */
+ l = 0; /* Don't loop again */
+ citype = 0;
+ goto endswitch;
+ }
+ GETCHAR(citype, p); /* Parse CI type */
+ GETCHAR(cilen, p); /* Parse CI length */
+ l -= cilen; /* Adjust remaining length */
+ next += cilen; /* Step to next CI */
+
+ switch (citype) { /* Check CI type */
+ case CI_MRU:
+ if (!ao->neg_mru) { /* Allow option? */
+ LCPDEBUG((LOG_INFO, "lcp_reqci: Reject MRU - not allowed\n"));
+ orc = CONFREJ; /* Reject CI */
+ break;
+ } else if (cilen != CILEN_SHORT) { /* Check CI length */
+ LCPDEBUG((LOG_INFO, "lcp_reqci: Reject MRU - bad length\n"));
+ orc = CONFREJ; /* Reject CI */
+ break;
+ }
+ GETSHORT(cishort, p); /* Parse MRU */
+
+ /*
+ * He must be able to receive at least our minimum.
+ * No need to check a maximum. If he sends a large number,
+ * we'll just ignore it.
+ */
+ if (cishort < PPP_MINMRU) {
+ LCPDEBUG((LOG_INFO, "lcp_reqci: Nak - MRU too small\n"));
+ orc = CONFNAK; /* Nak CI */
+ PUTCHAR(CI_MRU, nakp);
+ PUTCHAR(CILEN_SHORT, nakp);
+ PUTSHORT(PPP_MINMRU, nakp); /* Give him a hint */
+ break;
+ }
+ ho->neg_mru = 1; /* Remember he sent MRU */
+ ho->mru = cishort; /* And remember value */
+#if TRACELCP > 0
+ sprintf(&traceBuf[traceNdx], " MRU %d", cishort);
+ traceNdx = strlen(traceBuf);
+#endif
+ break;
+
+ case CI_ASYNCMAP:
+ if (!ao->neg_asyncmap) {
+ LCPDEBUG((LOG_INFO, "lcp_reqci: Reject ASYNCMAP not allowed\n"));
+ orc = CONFREJ;
+ break;
+ } else if (cilen != CILEN_LONG) {
+ LCPDEBUG((LOG_INFO, "lcp_reqci: Reject ASYNCMAP bad length\n"));
+ orc = CONFREJ;
+ break;
+ }
+ GETLONG(cilong, p);
+
+ /*
+ * Asyncmap must have set at least the bits
+ * which are set in lcp_allowoptions[unit].asyncmap.
+ */
+ if ((ao->asyncmap & ~cilong) != 0) {
+ LCPDEBUG((LOG_INFO, "lcp_reqci: Nak ASYNCMAP %lX missing %lX\n",
+ cilong, ao->asyncmap));
+ orc = CONFNAK;
+ PUTCHAR(CI_ASYNCMAP, nakp);
+ PUTCHAR(CILEN_LONG, nakp);
+ PUTLONG(ao->asyncmap | cilong, nakp);
+ break;
+ }
+ ho->neg_asyncmap = 1;
+ ho->asyncmap = cilong;
+#if TRACELCP > 0
+ sprintf(&traceBuf[traceNdx], " ASYNCMAP=%lX", cilong);
+ traceNdx = strlen(traceBuf);
+#endif
+ break;
+
+ case CI_AUTHTYPE:
+ if (cilen < CILEN_SHORT) {
+ LCPDEBUG((LOG_INFO, "lcp_reqci: Reject AUTHTYPE missing arg\n"));
+ orc = CONFREJ;
+ break;
+ } else if (!(ao->neg_upap || ao->neg_chap)) {
+ /*
+ * Reject the option if we're not willing to authenticate.
+ */
+ LCPDEBUG((LOG_INFO, "lcp_reqci: Reject AUTHTYPE not allowed\n"));
+ orc = CONFREJ;
+ break;
+ }
+ GETSHORT(cishort, p);
+
+ /*
+ * Authtype must be UPAP or CHAP.
+ *
+ * Note: if both ao->neg_upap and ao->neg_chap are set,
+ * and the peer sends a Configure-Request with two
+ * authenticate-protocol requests, one for CHAP and one
+ * for UPAP, then we will reject the second request.
+ * Whether we end up doing CHAP or UPAP depends then on
+ * the ordering of the CIs in the peer's Configure-Request.
+ */
+
+ if (cishort == PPP_PAP) {
+ if (ho->neg_chap) { /* we've already accepted CHAP */
+ LCPDEBUG((LOG_WARNING, "lcp_reqci: Reject AUTHTYPE PAP already accepted\n"));
+ orc = CONFREJ;
+ break;
+ } else if (cilen != CILEN_SHORT) {
+ LCPDEBUG((LOG_WARNING, "lcp_reqci: Reject AUTHTYPE PAP bad len\n"));
+ orc = CONFREJ;
+ break;
+ }
+ if (!ao->neg_upap) { /* we don't want to do PAP */
+ LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE PAP not allowed\n"));
+ orc = CONFNAK; /* NAK it and suggest CHAP */
+ PUTCHAR(CI_AUTHTYPE, nakp);
+ PUTCHAR(CILEN_CHAP, nakp);
+ PUTSHORT(PPP_CHAP, nakp);
+ PUTCHAR(ao->chap_mdtype, nakp);
+ break;
+ }
+ ho->neg_upap = 1;
+#if TRACELCP > 0
+ sprintf(&traceBuf[traceNdx], " PAP (%X)", cishort);
+ traceNdx = strlen(traceBuf);
+#endif
+ break;
+ }
+ if (cishort == PPP_CHAP) {
+ if (ho->neg_upap) { /* we've already accepted PAP */
+ LCPDEBUG((LOG_WARNING, "lcp_reqci: Reject AUTHTYPE CHAP accepted PAP\n"));
+ orc = CONFREJ;
+ break;
+ } else if (cilen != CILEN_CHAP) {
+ LCPDEBUG((LOG_WARNING, "lcp_reqci: Reject AUTHTYPE CHAP bad len\n"));
+ orc = CONFREJ;
+ break;
+ }
+ if (!ao->neg_chap) { /* we don't want to do CHAP */
+ LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE CHAP not allowed\n"));
+ orc = CONFNAK; /* NAK it and suggest PAP */
+ PUTCHAR(CI_AUTHTYPE, nakp);
+ PUTCHAR(CILEN_SHORT, nakp);
+ PUTSHORT(PPP_PAP, nakp);
+ break;
+ }
+ GETCHAR(cichar, p); /* get digest type*/
+ if (cichar != CHAP_DIGEST_MD5
+#ifdef CHAPMS
+ && cichar != CHAP_MICROSOFT
+#endif
+ ) {
+ LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE CHAP digest=%d\n", cichar));
+ orc = CONFNAK;
+ PUTCHAR(CI_AUTHTYPE, nakp);
+ PUTCHAR(CILEN_CHAP, nakp);
+ PUTSHORT(PPP_CHAP, nakp);
+ PUTCHAR(ao->chap_mdtype, nakp);
+ break;
+ }
+#if TRACELCP > 0
+ sprintf(&traceBuf[traceNdx], " CHAP %X,%d", cishort, cichar);
+ traceNdx = strlen(traceBuf);
+#endif
+ ho->chap_mdtype = cichar; /* save md type */
+ ho->neg_chap = 1;
+ break;
+ }
+
+ /*
+ * We don't recognize the protocol they're asking for.
+ * Nak it with something we're willing to do.
+ * (At this point we know ao->neg_upap || ao->neg_chap.)
+ */
+ orc = CONFNAK;
+ PUTCHAR(CI_AUTHTYPE, nakp);
+ if (ao->neg_chap) {
+ LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE %d req CHAP\n", cishort));
+ PUTCHAR(CILEN_CHAP, nakp);
+ PUTSHORT(PPP_CHAP, nakp);
+ PUTCHAR(ao->chap_mdtype, nakp);
+ }
+ else {
+ LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE %d req PAP\n", cishort));
+ PUTCHAR(CILEN_SHORT, nakp);
+ PUTSHORT(PPP_PAP, nakp);
+ }
+ break;
+
+ case CI_QUALITY:
+ GETSHORT(cishort, p);
+ GETLONG(cilong, p);
+#if TRACELCP > 0
+ sprintf(&traceBuf[traceNdx], " QUALITY (%x %x)", cishort, (unsigned int) cilong);
+ traceNdx = strlen(traceBuf);
+#endif
+
+ if (!ao->neg_lqr ||
+ cilen != CILEN_LQR) {
+ orc = CONFREJ;
+ break;
+ }
+
+ /*
+ * Check the protocol and the reporting period.
+ * XXX When should we Nak this, and what with?
+ */
+ if (cishort != PPP_LQR) {
+ orc = CONFNAK;
+ PUTCHAR(CI_QUALITY, nakp);
+ PUTCHAR(CILEN_LQR, nakp);
+ PUTSHORT(PPP_LQR, nakp);
+ PUTLONG(ao->lqr_period, nakp);
+ break;
+ }
+ break;
+
+ case CI_MAGICNUMBER:
+ if (!(ao->neg_magicnumber || go->neg_magicnumber) ||
+ cilen != CILEN_LONG) {
+ orc = CONFREJ;
+ break;
+ }
+ GETLONG(cilong, p);
+#if TRACELCP > 0
+ sprintf(&traceBuf[traceNdx], " MAGICNUMBER (%lX)", cilong);
+ traceNdx = strlen(traceBuf);
+#endif
+
+ /*
+ * He must have a different magic number.
+ */
+ if (go->neg_magicnumber &&
+ cilong == go->magicnumber) {
+ cilong = magic(); /* Don't put magic() inside macro! */
+ orc = CONFNAK;
+ PUTCHAR(CI_MAGICNUMBER, nakp);
+ PUTCHAR(CILEN_LONG, nakp);
+ PUTLONG(cilong, nakp);
+ break;
+ }
+ ho->neg_magicnumber = 1;
+ ho->magicnumber = cilong;
+ break;
+
+
+ case CI_PCOMPRESSION:
+#if TRACELCP > 0
+ sprintf(&traceBuf[traceNdx], " PCOMPRESSION");
+ traceNdx = strlen(traceBuf);
+#endif
+ if (!ao->neg_pcompression ||
+ cilen != CILEN_VOID) {
+ orc = CONFREJ;
+ break;
+ }
+ ho->neg_pcompression = 1;
+ break;
+
+ case CI_ACCOMPRESSION:
+#if TRACELCP > 0
+ sprintf(&traceBuf[traceNdx], " ACCOMPRESSION");
+ traceNdx = strlen(traceBuf);
+#endif
+ if (!ao->neg_accompression ||
+ cilen != CILEN_VOID) {
+ orc = CONFREJ;
+ break;
+ }
+ ho->neg_accompression = 1;
+ break;
+
+ case CI_MRRU:
+#if TRACELCP > 0
+ sprintf(&traceBuf[traceNdx], " CI_MRRU");
+ traceNdx = strlen(traceBuf);
+#endif
+ orc = CONFREJ;
+ break;
+
+ case CI_SSNHF:
+#if TRACELCP > 0
+ sprintf(&traceBuf[traceNdx], " CI_SSNHF");
+ traceNdx = strlen(traceBuf);
+#endif
+ orc = CONFREJ;
+ break;
+
+ case CI_EPDISC:
+#if TRACELCP > 0
+ sprintf(&traceBuf[traceNdx], " CI_EPDISC");
+ traceNdx = strlen(traceBuf);
+#endif
+ orc = CONFREJ;
+ break;
+
+ default:
+#if TRACELCP
+ sprintf(&traceBuf[traceNdx], " unknown %d", citype);
+ traceNdx = strlen(traceBuf);
+#endif
+ orc = CONFREJ;
+ break;
+ }
+
+ endswitch:
+#if TRACELCP
+ if (traceNdx >= 80 - 32) {
+ LCPDEBUG((LOG_INFO, "lcp_reqci: rcvd%s\n", traceBuf));
+ traceNdx = 0;
+ }
+#endif
+ if (orc == CONFACK && /* Good CI */
+ rc != CONFACK) /* but prior CI wasnt? */
+ continue; /* Don't send this one */
+
+ if (orc == CONFNAK) { /* Nak this CI? */
+ if (reject_if_disagree /* Getting fed up with sending NAKs? */
+ && citype != CI_MAGICNUMBER) {
+ orc = CONFREJ; /* Get tough if so */
+ }
+ else {
+ if (rc == CONFREJ) /* Rejecting prior CI? */
+ continue; /* Don't send this one */
+ rc = CONFNAK;
+ }
+ }
+ if (orc == CONFREJ) { /* Reject this CI */
+ rc = CONFREJ;
+ if (cip != rejp) /* Need to move rejected CI? */
+ BCOPY(cip, rejp, cilen); /* Move it */
+ INCPTR(cilen, rejp); /* Update output pointer */
+ }
+ }
+
+ /*
+ * If we wanted to send additional NAKs (for unsent CIs), the
+ * code would go here. The extra NAKs would go at *nakp.
+ * At present there are no cases where we want to ask the
+ * peer to negotiate an option.
+ */
+
+ switch (rc) {
+ case CONFACK:
+ *lenp = (int)(next - inp);
+ break;
+ case CONFNAK:
+ /*
+ * Copy the Nak'd options from the nak_buffer to the caller's buffer.
+ */
+ *lenp = (int)(nakp - nak_buffer);
+ BCOPY(nak_buffer, inp, *lenp);
+ break;
+ case CONFREJ:
+ *lenp = (int)(rejp - inp);
+ break;
+ }
+
+#if TRACELCP > 0
+ if (traceNdx > 0) {
+ LCPDEBUG((LOG_INFO, "lcp_reqci: %s\n", traceBuf));
+ }
+#endif
+ LCPDEBUG((LOG_INFO, "lcp_reqci: returning CONF%s.\n", CODENAME(rc)));
+ return (rc); /* Return final code */
+}
+
+
+/*
+ * lcp_up - LCP has come UP.
+ */
+static void lcp_up(fsm *f)
+{
+ lcp_options *wo = &lcp_wantoptions[f->unit];
+ lcp_options *ho = &lcp_hisoptions[f->unit];
+ lcp_options *go = &lcp_gotoptions[f->unit];
+ lcp_options *ao = &lcp_allowoptions[f->unit];
+
+ if (!go->neg_magicnumber)
+ go->magicnumber = 0;
+ if (!ho->neg_magicnumber)
+ ho->magicnumber = 0;
+
+ /*
+ * Set our MTU to the smaller of the MTU we wanted and
+ * the MRU our peer wanted. If we negotiated an MRU,
+ * set our MRU to the larger of value we wanted and
+ * the value we got in the negotiation.
+ */
+ ppp_send_config(f->unit, LWIP_MIN(ao->mru, (ho->neg_mru? ho->mru: PPP_MRU)),
+ (ho->neg_asyncmap? ho->asyncmap: 0xffffffffl),
+ ho->neg_pcompression, ho->neg_accompression);
+ /*
+ * If the asyncmap hasn't been negotiated, we really should
+ * set the receive asyncmap to ffffffff, but we set it to 0
+ * for backwards contemptibility.
+ */
+ ppp_recv_config(f->unit, (go->neg_mru? LWIP_MAX(wo->mru, go->mru): PPP_MRU),
+ (go->neg_asyncmap? go->asyncmap: 0x00000000),
+ go->neg_pcompression, go->neg_accompression);
+
+ if (ho->neg_mru)
+ peer_mru[f->unit] = ho->mru;
+
+ lcp_echo_lowerup(f->unit); /* Enable echo messages */
+
+ link_established(f->unit);
+}
+
+
+/*
+ * lcp_down - LCP has gone DOWN.
+ *
+ * Alert other protocols.
+ */
+static void lcp_down(fsm *f)
+{
+ lcp_options *go = &lcp_gotoptions[f->unit];
+
+ lcp_echo_lowerdown(f->unit);
+
+ link_down(f->unit);
+
+ ppp_send_config(f->unit, PPP_MRU, 0xffffffffl, 0, 0);
+ ppp_recv_config(f->unit, PPP_MRU,
+ (go->neg_asyncmap? go->asyncmap: 0x00000000),
+ go->neg_pcompression, go->neg_accompression);
+ peer_mru[f->unit] = PPP_MRU;
+}
+
+
+/*
+ * lcp_starting - LCP needs the lower layer up.
+ */
+static void lcp_starting(fsm *f)
+{
+ link_required(f->unit);
+}
+
+
+/*
+ * lcp_finished - LCP has finished with the lower layer.
+ */
+static void lcp_finished(fsm *f)
+{
+ link_terminated(f->unit);
+}
+
+
+#if 0
+/*
+ * print_string - print a readable representation of a string using
+ * printer.
+ */
+static void print_string(
+ char *p,
+ int len,
+ void (*printer) (void *, char *, ...),
+ void *arg
+)
+{
+ int c;
+
+ printer(arg, "\"");
+ for (; len > 0; --len) {
+ c = *p++;
+ if (' ' <= c && c <= '~') {
+ if (c == '\\' || c == '"')
+ printer(arg, "\\");
+ printer(arg, "%c", c);
+ } else {
+ switch (c) {
+ case '\n':
+ printer(arg, "\\n");
+ break;
+ case '\r':
+ printer(arg, "\\r");
+ break;
+ case '\t':
+ printer(arg, "\\t");
+ break;
+ default:
+ printer(arg, "\\%.3o", c);
+ }
+ }
+ }
+ printer(arg, "\"");
+}
+
+
+/*
+ * lcp_printpkt - print the contents of an LCP packet.
+ */
+static char *lcp_codenames[] = {
+ "ConfReq", "ConfAck", "ConfNak", "ConfRej",
+ "TermReq", "TermAck", "CodeRej", "ProtRej",
+ "EchoReq", "EchoRep", "DiscReq"
+};
+
+static int lcp_printpkt(
+ u_char *p,
+ int plen,
+ void (*printer) (void *, char *, ...),
+ void *arg
+)
+{
+ int code, id, len, olen;
+ u_char *pstart, *optend;
+ u_short cishort;
+ u32_t cilong;
+
+ if (plen < HEADERLEN)
+ return 0;
+ pstart = p;
+ GETCHAR(code, p);
+ GETCHAR(id, p);
+ GETSHORT(len, p);
+ if (len < HEADERLEN || len > plen)
+ return 0;
+
+ if (code >= 1 && code <= sizeof(lcp_codenames) / sizeof(char *))
+ printer(arg, " %s", lcp_codenames[code-1]);
+ else
+ printer(arg, " code=0x%x", code);
+ printer(arg, " id=0x%x", id);
+ len -= HEADERLEN;
+ switch (code) {
+ case CONFREQ:
+ case CONFACK:
+ case CONFNAK:
+ case CONFREJ:
+ /* print option list */
+ while (len >= 2) {
+ GETCHAR(code, p);
+ GETCHAR(olen, p);
+ p -= 2;
+ if (olen < 2 || olen > len) {
+ break;
+ }
+ printer(arg, " <");
+ len -= olen;
+ optend = p + olen;
+ switch (code) {
+ case CI_MRU:
+ if (olen == CILEN_SHORT) {
+ p += 2;
+ GETSHORT(cishort, p);
+ printer(arg, "mru %d", cishort);
+ }
+ break;
+ case CI_ASYNCMAP:
+ if (olen == CILEN_LONG) {
+ p += 2;
+ GETLONG(cilong, p);
+ printer(arg, "asyncmap 0x%lx", cilong);
+ }
+ break;
+ case CI_AUTHTYPE:
+ if (olen >= CILEN_SHORT) {
+ p += 2;
+ printer(arg, "auth ");
+ GETSHORT(cishort, p);
+ switch (cishort) {
+ case PPP_PAP:
+ printer(arg, "pap");
+ break;
+ case PPP_CHAP:
+ printer(arg, "chap");
+ break;
+ default:
+ printer(arg, "0x%x", cishort);
+ }
+ }
+ break;
+ case CI_QUALITY:
+ if (olen >= CILEN_SHORT) {
+ p += 2;
+ printer(arg, "quality ");
+ GETSHORT(cishort, p);
+ switch (cishort) {
+ case PPP_LQR:
+ printer(arg, "lqr");
+ break;
+ default:
+ printer(arg, "0x%x", cishort);
+ }
+ }
+ break;
+ case CI_CALLBACK:
+ if (olen >= CILEN_CHAR) {
+ p += 2;
+ printer(arg, "callback ");
+ GETSHORT(cishort, p);
+ switch (cishort) {
+ case CBCP_OPT:
+ printer(arg, "CBCP");
+ break;
+ default:
+ printer(arg, "0x%x", cishort);
+ }
+ }
+ break;
+ case CI_MAGICNUMBER:
+ if (olen == CILEN_LONG) {
+ p += 2;
+ GETLONG(cilong, p);
+ printer(arg, "magic 0x%x", cilong);
+ }
+ break;
+ case CI_PCOMPRESSION:
+ if (olen == CILEN_VOID) {
+ p += 2;
+ printer(arg, "pcomp");
+ }
+ break;
+ case CI_ACCOMPRESSION:
+ if (olen == CILEN_VOID) {
+ p += 2;
+ printer(arg, "accomp");
+ }
+ break;
+ }
+ while (p < optend) {
+ GETCHAR(code, p);
+ printer(arg, " %.2x", code);
+ }
+ printer(arg, ">");
+ }
+ break;
+
+ case TERMACK:
+ case TERMREQ:
+ if (len > 0 && *p >= ' ' && *p < 0x7f) {
+ printer(arg, " ");
+ print_string((char*)p, len, printer, arg);
+ p += len;
+ len = 0;
+ }
+ break;
+
+ case ECHOREQ:
+ case ECHOREP:
+ case DISCREQ:
+ if (len >= 4) {
+ GETLONG(cilong, p);
+ printer(arg, " magic=0x%x", cilong);
+ p += 4;
+ len -= 4;
+ }
+ break;
+ }
+
+ /* print the rest of the bytes in the packet */
+ for (; len > 0; --len) {
+ GETCHAR(code, p);
+ printer(arg, " %.2x", code);
+ }
+
+ return (int)(p - pstart);
+}
+#endif
+
+/*
+ * Time to shut down the link because there is nothing out there.
+ */
+
+static void LcpLinkFailure (fsm *f)
+{
+ if (f->state == OPENED) {
+ LCPDEBUG((LOG_INFO, "No response to %d echo-requests\n", lcp_echos_pending));
+ LCPDEBUG((LOG_NOTICE, "Serial link appears to be disconnected.\n"));
+ lcp_close(f->unit, "Peer not responding");
+ }
+}
+
+/*
+ * Timer expired for the LCP echo requests from this process.
+ */
+
+static void LcpEchoCheck (fsm *f)
+{
+ LcpSendEchoRequest (f);
+
+ /*
+ * Start the timer for the next interval.
+ */
+ LWIP_ASSERT("lcp_echo_timer_running == 0", lcp_echo_timer_running == 0);
+
+ TIMEOUT (LcpEchoTimeout, f, lcp_echo_interval);
+ lcp_echo_timer_running = 1;
+}
+
+/*
+ * LcpEchoTimeout - Timer expired on the LCP echo
+ */
+
+static void LcpEchoTimeout (void *arg)
+{
+ if (lcp_echo_timer_running != 0) {
+ lcp_echo_timer_running = 0;
+ LcpEchoCheck ((fsm *) arg);
+ }
+}
+
+/*
+ * LcpEchoReply - LCP has received a reply to the echo
+ */
+static void lcp_received_echo_reply (fsm *f, int id, u_char *inp, int len)
+{
+ u32_t magic;
+
+ (void)id;
+
+ /* Check the magic number - don't count replies from ourselves. */
+ if (len < 4) {
+ LCPDEBUG((LOG_WARNING, "lcp: received short Echo-Reply, length %d\n", len));
+ return;
+ }
+ GETLONG(magic, inp);
+ if (lcp_gotoptions[f->unit].neg_magicnumber
+ && magic == lcp_gotoptions[f->unit].magicnumber) {
+ LCPDEBUG((LOG_WARNING, "appear to have received our own echo-reply!\n"));
+ return;
+ }
+
+ /* Reset the number of outstanding echo frames */
+ lcp_echos_pending = 0;
+}
+
+/*
+ * LcpSendEchoRequest - Send an echo request frame to the peer
+ */
+
+static void LcpSendEchoRequest (fsm *f)
+{
+ u32_t lcp_magic;
+ u_char pkt[4], *pktp;
+
+ /*
+ * Detect the failure of the peer at this point.
+ */
+ if (lcp_echo_fails != 0) {
+ if (lcp_echos_pending++ >= lcp_echo_fails) {
+ LcpLinkFailure(f);
+ lcp_echos_pending = 0;
+ }
+ }
+
+ /*
+ * Make and send the echo request frame.
+ */
+ if (f->state == OPENED) {
+ lcp_magic = lcp_gotoptions[f->unit].magicnumber;
+ pktp = pkt;
+ PUTLONG(lcp_magic, pktp);
+ fsm_sdata(f, ECHOREQ, (u_char)(lcp_echo_number++ & 0xFF), pkt, (int)(pktp - pkt));
+ }
+}
+
+/*
+ * lcp_echo_lowerup - Start the timer for the LCP frame
+ */
+
+static void lcp_echo_lowerup (int unit)
+{
+ fsm *f = &lcp_fsm[unit];
+
+ /* Clear the parameters for generating echo frames */
+ lcp_echos_pending = 0;
+ lcp_echo_number = 0;
+ lcp_echo_timer_running = 0;
+
+ /* If a timeout interval is specified then start the timer */
+ if (lcp_echo_interval != 0)
+ LcpEchoCheck (f);
+}
+
+/*
+ * lcp_echo_lowerdown - Stop the timer for the LCP frame
+ */
+
+static void lcp_echo_lowerdown (int unit)
+{
+ fsm *f = &lcp_fsm[unit];
+
+ if (lcp_echo_timer_running != 0) {
+ UNTIMEOUT (LcpEchoTimeout, f);
+ lcp_echo_timer_running = 0;
+ }
+}
+
+#endif /* PPP_SUPPORT */
--- /dev/null
+/*****************************************************************************
+* lcp.h - Network Link Control Protocol header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher <marc@mbsi.ca>
+* Ported to lwIP.
+* 97-11-05 Guy Lancaster <glanca@gesn.com>, Global Election Systems Inc.
+* Original derived from BSD codes.
+*****************************************************************************/
+/*
+ * lcp.h - Link Control Protocol definitions.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University. The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * $Id: lcp.h,v 1.1 2003/05/27 14:37:56 jani Exp $
+ */
+
+#ifndef LCP_H
+#define LCP_H
+
+
+/*************************
+*** PUBLIC DEFINITIONS ***
+*************************/
+/*
+ * Options.
+ */
+#define CI_MRU 1 /* Maximum Receive Unit */
+#define CI_ASYNCMAP 2 /* Async Control Character Map */
+#define CI_AUTHTYPE 3 /* Authentication Type */
+#define CI_QUALITY 4 /* Quality Protocol */
+#define CI_MAGICNUMBER 5 /* Magic Number */
+#define CI_PCOMPRESSION 7 /* Protocol Field Compression */
+#define CI_ACCOMPRESSION 8 /* Address/Control Field Compression */
+#define CI_CALLBACK 13 /* callback */
+#define CI_MRRU 17 /* max reconstructed receive unit; multilink */
+#define CI_SSNHF 18 /* short sequence numbers for multilink */
+#define CI_EPDISC 19 /* endpoint discriminator */
+
+/*
+ * LCP-specific packet types.
+ */
+#define PROTREJ 8 /* Protocol Reject */
+#define ECHOREQ 9 /* Echo Request */
+#define ECHOREP 10 /* Echo Reply */
+#define DISCREQ 11 /* Discard Request */
+#define CBCP_OPT 6 /* Use callback control protocol */
+
+
+/************************
+*** PUBLIC DATA TYPES ***
+************************/
+
+/*
+ * The state of options is described by an lcp_options structure.
+ */
+typedef struct lcp_options {
+ u_int passive : 1; /* Don't die if we don't get a response */
+ u_int silent : 1; /* Wait for the other end to start first */
+ u_int restart : 1; /* Restart vs. exit after close */
+ u_int neg_mru : 1; /* Negotiate the MRU? */
+ u_int neg_asyncmap : 1; /* Negotiate the async map? */
+ u_int neg_upap : 1; /* Ask for UPAP authentication? */
+ u_int neg_chap : 1; /* Ask for CHAP authentication? */
+ u_int neg_magicnumber : 1; /* Ask for magic number? */
+ u_int neg_pcompression : 1; /* HDLC Protocol Field Compression? */
+ u_int neg_accompression : 1; /* HDLC Address/Control Field Compression? */
+ u_int neg_lqr : 1; /* Negotiate use of Link Quality Reports */
+ u_int neg_cbcp : 1; /* Negotiate use of CBCP */
+#ifdef PPP_MULTILINK
+ u_int neg_mrru : 1; /* Negotiate multilink MRRU */
+ u_int neg_ssnhf : 1; /* Negotiate short sequence numbers */
+ u_int neg_endpoint : 1; /* Negotiate endpoint discriminator */
+#endif
+ u_short mru; /* Value of MRU */
+#ifdef PPP_MULTILINK
+ u_short mrru; /* Value of MRRU, and multilink enable */
+#endif
+ u_char chap_mdtype; /* which MD type (hashing algorithm) */
+ u32_t asyncmap; /* Value of async map */
+ u32_t magicnumber;
+ int numloops; /* Number of loops during magic number neg. */
+ u32_t lqr_period; /* Reporting period for LQR 1/100ths second */
+#ifdef PPP_MULTILINK
+ struct epdisc endpoint; /* endpoint discriminator */
+#endif
+} lcp_options;
+
+/*
+ * Values for phase from BSD pppd.h based on RFC 1661.
+ */
+typedef enum {
+ PHASE_DEAD = 0,
+ PHASE_INITIALIZE,
+ PHASE_ESTABLISH,
+ PHASE_AUTHENTICATE,
+ PHASE_CALLBACK,
+ PHASE_NETWORK,
+ PHASE_TERMINATE
+} LinkPhase;
+
+
+/*****************************
+*** PUBLIC DATA STRUCTURES ***
+*****************************/
+
+extern LinkPhase lcp_phase[NUM_PPP]; /* Phase of link session (RFC 1661) */
+extern lcp_options lcp_wantoptions[];
+extern lcp_options lcp_gotoptions[];
+extern lcp_options lcp_allowoptions[];
+extern lcp_options lcp_hisoptions[];
+extern ext_accm xmit_accm[];
+
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+
+void lcp_init (int);
+void lcp_open (int);
+void lcp_close (int, char *);
+void lcp_lowerup (int);
+void lcp_lowerdown (int);
+void lcp_sprotrej (int, u_char *, int); /* send protocol reject */
+
+extern struct protent lcp_protent;
+
+/* Default number of times we receive our magic number from the peer
+ before deciding the link is looped-back. */
+#define DEFLOOPBACKFAIL 10
+
+#endif /* LCP_H */
+
--- /dev/null
+/*****************************************************************************
+* magic.c - Network Random Number Generator program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher <marc@mbsi.ca>
+* Ported to lwIP.
+* 97-12-04 Guy Lancaster <lancasterg@acm.org>, Global Election Systems Inc.
+* Original based on BSD magic.c.
+*****************************************************************************/
+/*
+ * magic.c - PPP Magic Number routines.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University. The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include "ppp.h"
+#include "randm.h"
+#include "magic.h"
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/*
+ * magicInit - Initialize the magic number generator.
+ *
+ * Since we use another random number generator that has its own
+ * initialization, we do nothing here.
+ */
+void magicInit()
+{
+ return;
+}
+
+/*
+ * magic - Returns the next magic number.
+ */
+u32_t magic()
+{
+ return avRandom();
+}
+
+
--- /dev/null
+/*****************************************************************************
+* magic.h - Network Random Number Generator header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher <marc@mbsi.ca>
+* Ported to lwIP.
+* 97-12-04 Guy Lancaster <glanca@gesn.com>, Global Election Systems Inc.
+* Original derived from BSD codes.
+*****************************************************************************/
+/*
+ * magic.h - PPP Magic Number definitions.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University. The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * $Id: magic.h,v 1.1 2003/05/27 14:37:56 jani Exp $
+ */
+
+#ifndef MAGIC_H
+#define MAGIC_H
+
+/*****************************************************************************
+************************** PUBLIC FUNCTIONS **********************************
+*****************************************************************************/
+
+void magicInit(void); /* Initialize the magic number generator */
+u32_t magic(void); /* Returns the next magic number */
+
+#endif /* MAGIC_H */
--- /dev/null
+/*
+ ***********************************************************************
+ ** md5.c -- the source code for MD5 routines **
+ ** RSA Data Security, Inc. MD5 Message-Digest Algorithm **
+ ** Created: 2/17/90 RLR **
+ ** Revised: 1/91 SRD,AJ,BSK,JT Reference C ver., 7/10 constant corr. **
+ ***********************************************************************
+ */
+
+/*
+ ***********************************************************************
+ ** Copyright (C) 1990, RSA Data Security, Inc. All rights reserved. **
+ ** **
+ ** License to copy and use this software is granted provided that **
+ ** it is identified as the "RSA Data Security, Inc. MD5 Message- **
+ ** Digest Algorithm" in all material mentioning or referencing this **
+ ** software or this function. **
+ ** **
+ ** License is also granted to make and use derivative works **
+ ** provided that such works are identified as "derived from the RSA **
+ ** Data Security, Inc. MD5 Message-Digest Algorithm" in all **
+ ** material mentioning or referencing the derived work. **
+ ** **
+ ** RSA Data Security, Inc. makes no representations concerning **
+ ** either the merchantability of this software or the suitability **
+ ** of this software for any particular purpose. It is provided "as **
+ ** is" without express or implied warranty of any kind. **
+ ** **
+ ** These notices must be retained in any copies of any part of this **
+ ** documentation and/or software. **
+ ***********************************************************************
+ */
+
+#include "ppp.h"
+#include "md5.h"
+#include "pppdebug.h"
+
+#if CHAP_SUPPORT > 0 || MD5_SUPPORT > 0
+
+/*
+ ***********************************************************************
+ ** Message-digest routines: **
+ ** To form the message digest for a message M **
+ ** (1) Initialize a context buffer mdContext using MD5Init **
+ ** (2) Call MD5Update on mdContext and M **
+ ** (3) Call MD5Final on mdContext **
+ ** The message digest is now in mdContext->digest[0...15] **
+ ***********************************************************************
+ */
+
+/* forward declaration */
+static void Transform (u32_t *buf, u32_t *in);
+
+static unsigned char PADDING[64] = {
+ 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+
+/* F, G, H and I are basic MD5 functions */
+#define F(x, y, z) (((x) & (y)) | ((~x) & (z)))
+#define G(x, y, z) (((x) & (z)) | ((y) & (~z)))
+#define H(x, y, z) ((x) ^ (y) ^ (z))
+#define I(x, y, z) ((y) ^ ((x) | (~z)))
+
+/* ROTATE_LEFT rotates x left n bits */
+#define ROTATE_LEFT(x, n) (((x) << (n)) | ((x) >> (32-(n))))
+
+/* FF, GG, HH, and II transformations for rounds 1, 2, 3, and 4 */
+/* Rotation is separate from addition to prevent recomputation */
+#define FF(a, b, c, d, x, s, ac) \
+ {(a) += F ((b), (c), (d)) + (x) + (u32_t)(ac); \
+ (a) = ROTATE_LEFT ((a), (s)); \
+ (a) += (b); \
+ }
+#define GG(a, b, c, d, x, s, ac) \
+ {(a) += G ((b), (c), (d)) + (x) + (u32_t)(ac); \
+ (a) = ROTATE_LEFT ((a), (s)); \
+ (a) += (b); \
+ }
+#define HH(a, b, c, d, x, s, ac) \
+ {(a) += H ((b), (c), (d)) + (x) + (u32_t)(ac); \
+ (a) = ROTATE_LEFT ((a), (s)); \
+ (a) += (b); \
+ }
+#define II(a, b, c, d, x, s, ac) \
+ {(a) += I ((b), (c), (d)) + (x) + (u32_t)(ac); \
+ (a) = ROTATE_LEFT ((a), (s)); \
+ (a) += (b); \
+ }
+
+#ifdef __STDC__
+#define UL(x) x##UL
+#else
+#ifdef WIN32
+#define UL(x) x##UL
+#else
+#define UL(x) x
+#endif
+#endif
+
+/* The routine MD5Init initializes the message-digest context
+ mdContext. All fields are set to zero.
+ */
+void MD5Init (MD5_CTX *mdContext)
+{
+ mdContext->i[0] = mdContext->i[1] = (u32_t)0;
+
+ /* Load magic initialization constants.
+ */
+ mdContext->buf[0] = (u32_t)0x67452301UL;
+ mdContext->buf[1] = (u32_t)0xefcdab89UL;
+ mdContext->buf[2] = (u32_t)0x98badcfeUL;
+ mdContext->buf[3] = (u32_t)0x10325476UL;
+}
+
+/* The routine MD5Update updates the message-digest context to
+ account for the presence of each of the characters inBuf[0..inLen-1]
+ in the message whose digest is being computed.
+ */
+void MD5Update(MD5_CTX *mdContext, unsigned char *inBuf, unsigned int inLen)
+{
+ u32_t in[16];
+ int mdi;
+ unsigned int i, ii;
+
+#if 0
+ ppp_trace(LOG_INFO, "MD5Update: %u:%.*H\n", inLen, MIN(inLen, 20) * 2, inBuf);
+ ppp_trace(LOG_INFO, "MD5Update: %u:%s\n", inLen, inBuf);
+#endif
+
+ /* compute number of bytes mod 64 */
+ mdi = (int)((mdContext->i[0] >> 3) & 0x3F);
+
+ /* update number of bits */
+ if ((mdContext->i[0] + ((u32_t)inLen << 3)) < mdContext->i[0])
+ mdContext->i[1]++;
+ mdContext->i[0] += ((u32_t)inLen << 3);
+ mdContext->i[1] += ((u32_t)inLen >> 29);
+
+ while (inLen--) {
+ /* add new character to buffer, increment mdi */
+ mdContext->in[mdi++] = *inBuf++;
+
+ /* transform if necessary */
+ if (mdi == 0x40) {
+ for (i = 0, ii = 0; i < 16; i++, ii += 4)
+ in[i] = (((u32_t)mdContext->in[ii+3]) << 24) |
+ (((u32_t)mdContext->in[ii+2]) << 16) |
+ (((u32_t)mdContext->in[ii+1]) << 8) |
+ ((u32_t)mdContext->in[ii]);
+ Transform (mdContext->buf, in);
+ mdi = 0;
+ }
+ }
+}
+
+/* The routine MD5Final terminates the message-digest computation and
+ ends with the desired message digest in mdContext->digest[0...15].
+ */
+void MD5Final (unsigned char hash[], MD5_CTX *mdContext)
+{
+ u32_t in[16];
+ int mdi;
+ unsigned int i, ii;
+ unsigned int padLen;
+
+ /* save number of bits */
+ in[14] = mdContext->i[0];
+ in[15] = mdContext->i[1];
+
+ /* compute number of bytes mod 64 */
+ mdi = (int)((mdContext->i[0] >> 3) & 0x3F);
+
+ /* pad out to 56 mod 64 */
+ padLen = (mdi < 56) ? (56 - mdi) : (120 - mdi);
+ MD5Update (mdContext, PADDING, padLen);
+
+ /* append length in bits and transform */
+ for (i = 0, ii = 0; i < 14; i++, ii += 4)
+ in[i] = (((u32_t)mdContext->in[ii+3]) << 24) |
+ (((u32_t)mdContext->in[ii+2]) << 16) |
+ (((u32_t)mdContext->in[ii+1]) << 8) |
+ ((u32_t)mdContext->in[ii]);
+ Transform (mdContext->buf, in);
+
+ /* store buffer in digest */
+ for (i = 0, ii = 0; i < 4; i++, ii += 4) {
+ mdContext->digest[ii] = (unsigned char)(mdContext->buf[i] & 0xFF);
+ mdContext->digest[ii+1] =
+ (unsigned char)((mdContext->buf[i] >> 8) & 0xFF);
+ mdContext->digest[ii+2] =
+ (unsigned char)((mdContext->buf[i] >> 16) & 0xFF);
+ mdContext->digest[ii+3] =
+ (unsigned char)((mdContext->buf[i] >> 24) & 0xFF);
+ }
+ memcpy(hash, mdContext->digest, 16);
+}
+
+/* Basic MD5 step. Transforms buf based on in.
+ */
+static void Transform (u32_t *buf, u32_t *in)
+{
+ u32_t a = buf[0], b = buf[1], c = buf[2], d = buf[3];
+
+ /* Round 1 */
+#define S11 7
+#define S12 12
+#define S13 17
+#define S14 22
+ FF ( a, b, c, d, in[ 0], S11, UL(3614090360)); /* 1 */
+ FF ( d, a, b, c, in[ 1], S12, UL(3905402710)); /* 2 */
+ FF ( c, d, a, b, in[ 2], S13, UL( 606105819)); /* 3 */
+ FF ( b, c, d, a, in[ 3], S14, UL(3250441966)); /* 4 */
+ FF ( a, b, c, d, in[ 4], S11, UL(4118548399)); /* 5 */
+ FF ( d, a, b, c, in[ 5], S12, UL(1200080426)); /* 6 */
+ FF ( c, d, a, b, in[ 6], S13, UL(2821735955)); /* 7 */
+ FF ( b, c, d, a, in[ 7], S14, UL(4249261313)); /* 8 */
+ FF ( a, b, c, d, in[ 8], S11, UL(1770035416)); /* 9 */
+ FF ( d, a, b, c, in[ 9], S12, UL(2336552879)); /* 10 */
+ FF ( c, d, a, b, in[10], S13, UL(4294925233)); /* 11 */
+ FF ( b, c, d, a, in[11], S14, UL(2304563134)); /* 12 */
+ FF ( a, b, c, d, in[12], S11, UL(1804603682)); /* 13 */
+ FF ( d, a, b, c, in[13], S12, UL(4254626195)); /* 14 */
+ FF ( c, d, a, b, in[14], S13, UL(2792965006)); /* 15 */
+ FF ( b, c, d, a, in[15], S14, UL(1236535329)); /* 16 */
+
+ /* Round 2 */
+#define S21 5
+#define S22 9
+#define S23 14
+#define S24 20
+ GG ( a, b, c, d, in[ 1], S21, UL(4129170786)); /* 17 */
+ GG ( d, a, b, c, in[ 6], S22, UL(3225465664)); /* 18 */
+ GG ( c, d, a, b, in[11], S23, UL( 643717713)); /* 19 */
+ GG ( b, c, d, a, in[ 0], S24, UL(3921069994)); /* 20 */
+ GG ( a, b, c, d, in[ 5], S21, UL(3593408605)); /* 21 */
+ GG ( d, a, b, c, in[10], S22, UL( 38016083)); /* 22 */
+ GG ( c, d, a, b, in[15], S23, UL(3634488961)); /* 23 */
+ GG ( b, c, d, a, in[ 4], S24, UL(3889429448)); /* 24 */
+ GG ( a, b, c, d, in[ 9], S21, UL( 568446438)); /* 25 */
+ GG ( d, a, b, c, in[14], S22, UL(3275163606)); /* 26 */
+ GG ( c, d, a, b, in[ 3], S23, UL(4107603335)); /* 27 */
+ GG ( b, c, d, a, in[ 8], S24, UL(1163531501)); /* 28 */
+ GG ( a, b, c, d, in[13], S21, UL(2850285829)); /* 29 */
+ GG ( d, a, b, c, in[ 2], S22, UL(4243563512)); /* 30 */
+ GG ( c, d, a, b, in[ 7], S23, UL(1735328473)); /* 31 */
+ GG ( b, c, d, a, in[12], S24, UL(2368359562)); /* 32 */
+
+ /* Round 3 */
+#define S31 4
+#define S32 11
+#define S33 16
+#define S34 23
+ HH ( a, b, c, d, in[ 5], S31, UL(4294588738)); /* 33 */
+ HH ( d, a, b, c, in[ 8], S32, UL(2272392833)); /* 34 */
+ HH ( c, d, a, b, in[11], S33, UL(1839030562)); /* 35 */
+ HH ( b, c, d, a, in[14], S34, UL(4259657740)); /* 36 */
+ HH ( a, b, c, d, in[ 1], S31, UL(2763975236)); /* 37 */
+ HH ( d, a, b, c, in[ 4], S32, UL(1272893353)); /* 38 */
+ HH ( c, d, a, b, in[ 7], S33, UL(4139469664)); /* 39 */
+ HH ( b, c, d, a, in[10], S34, UL(3200236656)); /* 40 */
+ HH ( a, b, c, d, in[13], S31, UL( 681279174)); /* 41 */
+ HH ( d, a, b, c, in[ 0], S32, UL(3936430074)); /* 42 */
+ HH ( c, d, a, b, in[ 3], S33, UL(3572445317)); /* 43 */
+ HH ( b, c, d, a, in[ 6], S34, UL( 76029189)); /* 44 */
+ HH ( a, b, c, d, in[ 9], S31, UL(3654602809)); /* 45 */
+ HH ( d, a, b, c, in[12], S32, UL(3873151461)); /* 46 */
+ HH ( c, d, a, b, in[15], S33, UL( 530742520)); /* 47 */
+ HH ( b, c, d, a, in[ 2], S34, UL(3299628645)); /* 48 */
+
+ /* Round 4 */
+#define S41 6
+#define S42 10
+#define S43 15
+#define S44 21
+ II ( a, b, c, d, in[ 0], S41, UL(4096336452)); /* 49 */
+ II ( d, a, b, c, in[ 7], S42, UL(1126891415)); /* 50 */
+ II ( c, d, a, b, in[14], S43, UL(2878612391)); /* 51 */
+ II ( b, c, d, a, in[ 5], S44, UL(4237533241)); /* 52 */
+ II ( a, b, c, d, in[12], S41, UL(1700485571)); /* 53 */
+ II ( d, a, b, c, in[ 3], S42, UL(2399980690)); /* 54 */
+ II ( c, d, a, b, in[10], S43, UL(4293915773)); /* 55 */
+ II ( b, c, d, a, in[ 1], S44, UL(2240044497)); /* 56 */
+ II ( a, b, c, d, in[ 8], S41, UL(1873313359)); /* 57 */
+ II ( d, a, b, c, in[15], S42, UL(4264355552)); /* 58 */
+ II ( c, d, a, b, in[ 6], S43, UL(2734768916)); /* 59 */
+ II ( b, c, d, a, in[13], S44, UL(1309151649)); /* 60 */
+ II ( a, b, c, d, in[ 4], S41, UL(4149444226)); /* 61 */
+ II ( d, a, b, c, in[11], S42, UL(3174756917)); /* 62 */
+ II ( c, d, a, b, in[ 2], S43, UL( 718787259)); /* 63 */
+ II ( b, c, d, a, in[ 9], S44, UL(3951481745)); /* 64 */
+
+ buf[0] += a;
+ buf[1] += b;
+ buf[2] += c;
+ buf[3] += d;
+}
+
+#endif
+
--- /dev/null
+/*
+ ***********************************************************************
+ ** md5.h -- header file for implementation of MD5 **
+ ** RSA Data Security, Inc. MD5 Message-Digest Algorithm **
+ ** Created: 2/17/90 RLR **
+ ** Revised: 12/27/90 SRD,AJ,BSK,JT Reference C version **
+ ** Revised (for MD5): RLR 4/27/91 **
+ ** -- G modified to have y&~z instead of y&z **
+ ** -- FF, GG, HH modified to add in last register done **
+ ** -- Access pattern: round 2 works mod 5, round 3 works mod 3 **
+ ** -- distinct additive constant for each step **
+ ** -- round 4 added, working mod 7 **
+ ***********************************************************************
+ */
+
+/*
+ ***********************************************************************
+ ** Copyright (C) 1990, RSA Data Security, Inc. All rights reserved. **
+ ** **
+ ** License to copy and use this software is granted provided that **
+ ** it is identified as the "RSA Data Security, Inc. MD5 Message- **
+ ** Digest Algorithm" in all material mentioning or referencing this **
+ ** software or this function. **
+ ** **
+ ** License is also granted to make and use derivative works **
+ ** provided that such works are identified as "derived from the RSA **
+ ** Data Security, Inc. MD5 Message-Digest Algorithm" in all **
+ ** material mentioning or referencing the derived work. **
+ ** **
+ ** RSA Data Security, Inc. makes no representations concerning **
+ ** either the merchantability of this software or the suitability **
+ ** of this software for any particular purpose. It is provided "as **
+ ** is" without express or implied warranty of any kind. **
+ ** **
+ ** These notices must be retained in any copies of any part of this **
+ ** documentation and/or software. **
+ ***********************************************************************
+ */
+
+#ifndef MD5_H
+#define MD5_H
+
+/* Data structure for MD5 (Message-Digest) computation */
+typedef struct {
+ u32_t i[2]; /* number of _bits_ handled mod 2^64 */
+ u32_t buf[4]; /* scratch buffer */
+ unsigned char in[64]; /* input buffer */
+ unsigned char digest[16]; /* actual digest after MD5Final call */
+} MD5_CTX;
+
+void MD5Init (MD5_CTX *mdContext);
+void MD5Update (MD5_CTX *mdContext, unsigned char *inBuf, unsigned int inLen);
+void MD5Final (unsigned char hash[], MD5_CTX *mdContext);
+
+#endif /* MD5_H */
--- /dev/null
+/*****************************************************************************
+* pap.c - Network Password Authentication Protocol program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher <marc@mbsi.ca>
+* Ported to lwIP.
+* 97-12-12 Guy Lancaster <lancasterg@acm.org>, Global Election Systems Inc.
+* Original.
+*****************************************************************************/
+/*
+ * upap.c - User/Password Authentication Protocol.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University. The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include "ppp.h"
+#include "auth.h"
+#include "pap.h"
+#include "pppdebug.h"
+
+
+#if PAP_SUPPORT > 0
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+/*
+ * Protocol entry points.
+ */
+static void upap_init (int);
+static void upap_lowerup (int);
+static void upap_lowerdown (int);
+static void upap_input (int, u_char *, int);
+static void upap_protrej (int);
+
+static void upap_timeout (void *);
+static void upap_reqtimeout (void *);
+static void upap_rauthreq (upap_state *, u_char *, int, int);
+static void upap_rauthack (upap_state *, u_char *, int, int);
+static void upap_rauthnak (upap_state *, u_char *, int, int);
+static void upap_sauthreq (upap_state *);
+static void upap_sresp (upap_state *, u_char, u_char, char *, int);
+
+
+
+
+/******************************/
+/*** PUBLIC DATA STRUCTURES ***/
+/******************************/
+struct protent pap_protent = {
+ PPP_PAP,
+ upap_init,
+ upap_input,
+ upap_protrej,
+ upap_lowerup,
+ upap_lowerdown,
+ NULL,
+ NULL,
+#if 0
+ upap_printpkt,
+ NULL,
+#endif
+ 1,
+ "PAP",
+#if 0
+ NULL,
+ NULL,
+ NULL
+#endif
+};
+
+upap_state upap[NUM_PPP]; /* UPAP state; one for each unit */
+
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/*
+ * Set the default login name and password for the pap sessions
+ */
+void upap_setloginpasswd(int unit, const char *luser, const char *lpassword)
+{
+ upap_state *u = &upap[unit];
+
+ /* Save the username and password we're given */
+ u->us_user = luser;
+ u->us_userlen = strlen(luser);
+ u->us_passwd = lpassword;
+ u->us_passwdlen = strlen(lpassword);
+}
+
+
+/*
+ * upap_authwithpeer - Authenticate us with our peer (start client).
+ *
+ * Set new state and send authenticate's.
+ */
+void upap_authwithpeer(int unit, char *user, char *password)
+{
+ upap_state *u = &upap[unit];
+
+ UPAPDEBUG((LOG_INFO, "upap_authwithpeer: %d user=%s password=%s s=%d\n",
+ unit, user, password, u->us_clientstate));
+
+ upap_setloginpasswd(unit, user, password);
+
+ u->us_transmits = 0;
+
+ /* Lower layer up yet? */
+ if (u->us_clientstate == UPAPCS_INITIAL ||
+ u->us_clientstate == UPAPCS_PENDING) {
+ u->us_clientstate = UPAPCS_PENDING;
+ return;
+ }
+
+ upap_sauthreq(u); /* Start protocol */
+}
+
+
+/*
+ * upap_authpeer - Authenticate our peer (start server).
+ *
+ * Set new state.
+ */
+void upap_authpeer(int unit)
+{
+ upap_state *u = &upap[unit];
+
+ /* Lower layer up yet? */
+ if (u->us_serverstate == UPAPSS_INITIAL ||
+ u->us_serverstate == UPAPSS_PENDING) {
+ u->us_serverstate = UPAPSS_PENDING;
+ return;
+ }
+
+ u->us_serverstate = UPAPSS_LISTEN;
+ if (u->us_reqtimeout > 0)
+ TIMEOUT(upap_reqtimeout, u, u->us_reqtimeout);
+}
+
+
+
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+/*
+ * upap_init - Initialize a UPAP unit.
+ */
+static void upap_init(int unit)
+{
+ upap_state *u = &upap[unit];
+
+ UPAPDEBUG((LOG_INFO, "upap_init: %d\n", unit));
+ u->us_unit = unit;
+ u->us_user = NULL;
+ u->us_userlen = 0;
+ u->us_passwd = NULL;
+ u->us_passwdlen = 0;
+ u->us_clientstate = UPAPCS_INITIAL;
+ u->us_serverstate = UPAPSS_INITIAL;
+ u->us_id = 0;
+ u->us_timeouttime = UPAP_DEFTIMEOUT;
+ u->us_maxtransmits = 10;
+ u->us_reqtimeout = UPAP_DEFREQTIME;
+}
+
+/*
+ * upap_timeout - Retransmission timer for sending auth-reqs expired.
+ */
+static void upap_timeout(void *arg)
+{
+ upap_state *u = (upap_state *) arg;
+
+ UPAPDEBUG((LOG_INFO, "upap_timeout: %d timeout %d expired s=%d\n",
+ u->us_unit, u->us_timeouttime, u->us_clientstate));
+
+ if (u->us_clientstate != UPAPCS_AUTHREQ)
+ return;
+
+ if (u->us_transmits >= u->us_maxtransmits) {
+ /* give up in disgust */
+ UPAPDEBUG((LOG_ERR, "No response to PAP authenticate-requests\n"));
+ u->us_clientstate = UPAPCS_BADAUTH;
+ auth_withpeer_fail(u->us_unit, PPP_PAP);
+ return;
+ }
+
+ upap_sauthreq(u); /* Send Authenticate-Request */
+}
+
+
+/*
+ * upap_reqtimeout - Give up waiting for the peer to send an auth-req.
+ */
+static void upap_reqtimeout(void *arg)
+{
+ upap_state *u = (upap_state *) arg;
+
+ if (u->us_serverstate != UPAPSS_LISTEN)
+ return; /* huh?? */
+
+ auth_peer_fail(u->us_unit, PPP_PAP);
+ u->us_serverstate = UPAPSS_BADAUTH;
+}
+
+
+/*
+ * upap_lowerup - The lower layer is up.
+ *
+ * Start authenticating if pending.
+ */
+static void upap_lowerup(int unit)
+{
+ upap_state *u = &upap[unit];
+
+ UPAPDEBUG((LOG_INFO, "upap_lowerup: %d s=%d\n", unit, u->us_clientstate));
+
+ if (u->us_clientstate == UPAPCS_INITIAL)
+ u->us_clientstate = UPAPCS_CLOSED;
+ else if (u->us_clientstate == UPAPCS_PENDING) {
+ upap_sauthreq(u); /* send an auth-request */
+ }
+
+ if (u->us_serverstate == UPAPSS_INITIAL)
+ u->us_serverstate = UPAPSS_CLOSED;
+ else if (u->us_serverstate == UPAPSS_PENDING) {
+ u->us_serverstate = UPAPSS_LISTEN;
+ if (u->us_reqtimeout > 0)
+ TIMEOUT(upap_reqtimeout, u, u->us_reqtimeout);
+ }
+}
+
+
+/*
+ * upap_lowerdown - The lower layer is down.
+ *
+ * Cancel all timeouts.
+ */
+static void upap_lowerdown(int unit)
+{
+ upap_state *u = &upap[unit];
+
+ UPAPDEBUG((LOG_INFO, "upap_lowerdown: %d s=%d\n", unit, u->us_clientstate));
+
+ if (u->us_clientstate == UPAPCS_AUTHREQ) /* Timeout pending? */
+ UNTIMEOUT(upap_timeout, u); /* Cancel timeout */
+ if (u->us_serverstate == UPAPSS_LISTEN && u->us_reqtimeout > 0)
+ UNTIMEOUT(upap_reqtimeout, u);
+
+ u->us_clientstate = UPAPCS_INITIAL;
+ u->us_serverstate = UPAPSS_INITIAL;
+}
+
+
+/*
+ * upap_protrej - Peer doesn't speak this protocol.
+ *
+ * This shouldn't happen. In any case, pretend lower layer went down.
+ */
+static void upap_protrej(int unit)
+{
+ upap_state *u = &upap[unit];
+
+ if (u->us_clientstate == UPAPCS_AUTHREQ) {
+ UPAPDEBUG((LOG_ERR, "PAP authentication failed due to protocol-reject\n"));
+ auth_withpeer_fail(unit, PPP_PAP);
+ }
+ if (u->us_serverstate == UPAPSS_LISTEN) {
+ UPAPDEBUG((LOG_ERR, "PAP authentication of peer failed (protocol-reject)\n"));
+ auth_peer_fail(unit, PPP_PAP);
+ }
+ upap_lowerdown(unit);
+}
+
+
+/*
+ * upap_input - Input UPAP packet.
+ */
+static void upap_input(int unit, u_char *inpacket, int l)
+{
+ upap_state *u = &upap[unit];
+ u_char *inp;
+ u_char code, id;
+ int len;
+
+ /*
+ * Parse header (code, id and length).
+ * If packet too short, drop it.
+ */
+ inp = inpacket;
+ if (l < UPAP_HEADERLEN) {
+ UPAPDEBUG((LOG_INFO, "pap_input: rcvd short header.\n"));
+ return;
+ }
+ GETCHAR(code, inp);
+ GETCHAR(id, inp);
+ GETSHORT(len, inp);
+ if (len < UPAP_HEADERLEN) {
+ UPAPDEBUG((LOG_INFO, "pap_input: rcvd illegal length.\n"));
+ return;
+ }
+ if (len > l) {
+ UPAPDEBUG((LOG_INFO, "pap_input: rcvd short packet.\n"));
+ return;
+ }
+ len -= UPAP_HEADERLEN;
+
+ /*
+ * Action depends on code.
+ */
+ switch (code) {
+ case UPAP_AUTHREQ:
+ upap_rauthreq(u, inp, id, len);
+ break;
+
+ case UPAP_AUTHACK:
+ upap_rauthack(u, inp, id, len);
+ break;
+
+ case UPAP_AUTHNAK:
+ upap_rauthnak(u, inp, id, len);
+ break;
+
+ default: /* XXX Need code reject */
+ break;
+ }
+}
+
+
+/*
+ * upap_rauth - Receive Authenticate.
+ */
+static void upap_rauthreq(
+ upap_state *u,
+ u_char *inp,
+ int id,
+ int len
+)
+{
+ u_char ruserlen, rpasswdlen;
+ char *ruser, *rpasswd;
+ int retcode;
+ char *msg;
+ int msglen;
+
+ UPAPDEBUG((LOG_INFO, "pap_rauth: Rcvd id %d.\n", id));
+
+ if (u->us_serverstate < UPAPSS_LISTEN)
+ return;
+
+ /*
+ * If we receive a duplicate authenticate-request, we are
+ * supposed to return the same status as for the first request.
+ */
+ if (u->us_serverstate == UPAPSS_OPEN) {
+ upap_sresp(u, UPAP_AUTHACK, id, "", 0); /* return auth-ack */
+ return;
+ }
+ if (u->us_serverstate == UPAPSS_BADAUTH) {
+ upap_sresp(u, UPAP_AUTHNAK, id, "", 0); /* return auth-nak */
+ return;
+ }
+
+ /*
+ * Parse user/passwd.
+ */
+ if (len < sizeof (u_char)) {
+ UPAPDEBUG((LOG_INFO, "pap_rauth: rcvd short packet.\n"));
+ return;
+ }
+ GETCHAR(ruserlen, inp);
+ len -= sizeof (u_char) + ruserlen + sizeof (u_char);
+ if (len < 0) {
+ UPAPDEBUG((LOG_INFO, "pap_rauth: rcvd short packet.\n"));
+ return;
+ }
+ ruser = (char *) inp;
+ INCPTR(ruserlen, inp);
+ GETCHAR(rpasswdlen, inp);
+ if (len < rpasswdlen) {
+ UPAPDEBUG((LOG_INFO, "pap_rauth: rcvd short packet.\n"));
+ return;
+ }
+ rpasswd = (char *) inp;
+
+ /*
+ * Check the username and password given.
+ */
+ retcode = check_passwd(u->us_unit, ruser, ruserlen, rpasswd,
+ rpasswdlen, &msg, &msglen);
+ BZERO(rpasswd, rpasswdlen);
+
+ upap_sresp(u, retcode, id, msg, msglen);
+
+ if (retcode == UPAP_AUTHACK) {
+ u->us_serverstate = UPAPSS_OPEN;
+ auth_peer_success(u->us_unit, PPP_PAP, ruser, ruserlen);
+ } else {
+ u->us_serverstate = UPAPSS_BADAUTH;
+ auth_peer_fail(u->us_unit, PPP_PAP);
+ }
+
+ if (u->us_reqtimeout > 0)
+ UNTIMEOUT(upap_reqtimeout, u);
+}
+
+
+/*
+ * upap_rauthack - Receive Authenticate-Ack.
+ */
+static void upap_rauthack(
+ upap_state *u,
+ u_char *inp,
+ int id,
+ int len
+)
+{
+ u_char msglen;
+ char *msg;
+
+ UPAPDEBUG((LOG_INFO, "pap_rauthack: Rcvd id %d s=%d\n", id, u->us_clientstate));
+
+ if (u->us_clientstate != UPAPCS_AUTHREQ) /* XXX */
+ return;
+
+ /*
+ * Parse message.
+ */
+ if (len < sizeof (u_char)) {
+ UPAPDEBUG((LOG_INFO, "pap_rauthack: rcvd short packet.\n"));
+ return;
+ }
+ GETCHAR(msglen, inp);
+ len -= sizeof (u_char);
+ if (len < msglen) {
+ UPAPDEBUG((LOG_INFO, "pap_rauthack: rcvd short packet.\n"));
+ return;
+ }
+ msg = (char *) inp;
+ PRINTMSG(msg, msglen);
+
+ u->us_clientstate = UPAPCS_OPEN;
+
+ auth_withpeer_success(u->us_unit, PPP_PAP);
+}
+
+
+/*
+ * upap_rauthnak - Receive Authenticate-Nakk.
+ */
+static void upap_rauthnak(
+ upap_state *u,
+ u_char *inp,
+ int id,
+ int len
+)
+{
+ u_char msglen;
+ char *msg;
+
+ UPAPDEBUG((LOG_INFO, "pap_rauthnak: Rcvd id %d s=%d\n", id, u->us_clientstate));
+
+ if (u->us_clientstate != UPAPCS_AUTHREQ) /* XXX */
+ return;
+
+ /*
+ * Parse message.
+ */
+ if (len < sizeof (u_char)) {
+ UPAPDEBUG((LOG_INFO, "pap_rauthnak: rcvd short packet.\n"));
+ return;
+ }
+ GETCHAR(msglen, inp);
+ len -= sizeof (u_char);
+ if (len < msglen) {
+ UPAPDEBUG((LOG_INFO, "pap_rauthnak: rcvd short packet.\n"));
+ return;
+ }
+ msg = (char *) inp;
+ PRINTMSG(msg, msglen);
+
+ u->us_clientstate = UPAPCS_BADAUTH;
+
+ UPAPDEBUG((LOG_ERR, "PAP authentication failed\n"));
+ auth_withpeer_fail(u->us_unit, PPP_PAP);
+}
+
+
+/*
+ * upap_sauthreq - Send an Authenticate-Request.
+ */
+static void upap_sauthreq(upap_state *u)
+{
+ u_char *outp;
+ int outlen;
+
+ outlen = UPAP_HEADERLEN + 2 * sizeof (u_char)
+ + u->us_userlen + u->us_passwdlen;
+ outp = outpacket_buf[u->us_unit];
+
+ MAKEHEADER(outp, PPP_PAP);
+
+ PUTCHAR(UPAP_AUTHREQ, outp);
+ PUTCHAR(++u->us_id, outp);
+ PUTSHORT(outlen, outp);
+ PUTCHAR(u->us_userlen, outp);
+ BCOPY(u->us_user, outp, u->us_userlen);
+ INCPTR(u->us_userlen, outp);
+ PUTCHAR(u->us_passwdlen, outp);
+ BCOPY(u->us_passwd, outp, u->us_passwdlen);
+
+ pppWrite(u->us_unit, outpacket_buf[u->us_unit], outlen + PPP_HDRLEN);
+
+ UPAPDEBUG((LOG_INFO, "pap_sauth: Sent id %d\n", u->us_id));
+
+ TIMEOUT(upap_timeout, u, u->us_timeouttime);
+ ++u->us_transmits;
+ u->us_clientstate = UPAPCS_AUTHREQ;
+}
+
+
+/*
+ * upap_sresp - Send a response (ack or nak).
+ */
+static void upap_sresp(
+ upap_state *u,
+ u_char code,
+ u_char id,
+ char *msg,
+ int msglen
+)
+{
+ u_char *outp;
+ int outlen;
+
+ outlen = UPAP_HEADERLEN + sizeof (u_char) + msglen;
+ outp = outpacket_buf[u->us_unit];
+ MAKEHEADER(outp, PPP_PAP);
+
+ PUTCHAR(code, outp);
+ PUTCHAR(id, outp);
+ PUTSHORT(outlen, outp);
+ PUTCHAR(msglen, outp);
+ BCOPY(msg, outp, msglen);
+ pppWrite(u->us_unit, outpacket_buf[u->us_unit], outlen + PPP_HDRLEN);
+
+ UPAPDEBUG((LOG_INFO, "pap_sresp: Sent code %d, id %d s=%d\n",
+ code, id, u->us_clientstate));
+}
+
+#if 0
+/*
+ * upap_printpkt - print the contents of a PAP packet.
+ */
+static int upap_printpkt(
+ u_char *p,
+ int plen,
+ void (*printer) (void *, char *, ...),
+ void *arg
+)
+{
+ (void)p;
+ (void)plen;
+ (void)printer;
+ (void)arg;
+ return 0;
+}
+#endif
+
+#endif /* PAP_SUPPORT */
+
--- /dev/null
+/*****************************************************************************
+* pap.h - PPP Password Authentication Protocol header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher <marc@mbsi.ca>
+* Ported to lwIP.
+* 97-12-04 Guy Lancaster <glanca@gesn.com>, Global Election Systems Inc.
+* Original derived from BSD codes.
+*****************************************************************************/
+/*
+ * upap.h - User/Password Authentication Protocol definitions.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University. The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+
+#ifndef PAP_H
+#define PAP_H
+
+/*************************
+*** PUBLIC DEFINITIONS ***
+*************************/
+/*
+ * Packet header = Code, id, length.
+ */
+#define UPAP_HEADERLEN (sizeof (u_char) + sizeof (u_char) + sizeof (u_short))
+
+
+/*
+ * UPAP codes.
+ */
+#define UPAP_AUTHREQ 1 /* Authenticate-Request */
+#define UPAP_AUTHACK 2 /* Authenticate-Ack */
+#define UPAP_AUTHNAK 3 /* Authenticate-Nak */
+
+/*
+ * Client states.
+ */
+#define UPAPCS_INITIAL 0 /* Connection down */
+#define UPAPCS_CLOSED 1 /* Connection up, haven't requested auth */
+#define UPAPCS_PENDING 2 /* Connection down, have requested auth */
+#define UPAPCS_AUTHREQ 3 /* We've sent an Authenticate-Request */
+#define UPAPCS_OPEN 4 /* We've received an Ack */
+#define UPAPCS_BADAUTH 5 /* We've received a Nak */
+
+/*
+ * Server states.
+ */
+#define UPAPSS_INITIAL 0 /* Connection down */
+#define UPAPSS_CLOSED 1 /* Connection up, haven't requested auth */
+#define UPAPSS_PENDING 2 /* Connection down, have requested auth */
+#define UPAPSS_LISTEN 3 /* Listening for an Authenticate */
+#define UPAPSS_OPEN 4 /* We've sent an Ack */
+#define UPAPSS_BADAUTH 5 /* We've sent a Nak */
+
+
+/************************
+*** PUBLIC DATA TYPES ***
+************************/
+
+/*
+ * Each interface is described by upap structure.
+ */
+typedef struct upap_state {
+ int us_unit; /* Interface unit number */
+ const char *us_user; /* User */
+ int us_userlen; /* User length */
+ const char *us_passwd; /* Password */
+ int us_passwdlen; /* Password length */
+ int us_clientstate; /* Client state */
+ int us_serverstate; /* Server state */
+ u_char us_id; /* Current id */
+ int us_timeouttime; /* Timeout (seconds) for auth-req retrans. */
+ int us_transmits; /* Number of auth-reqs sent */
+ int us_maxtransmits; /* Maximum number of auth-reqs to send */
+ int us_reqtimeout; /* Time to wait for auth-req from peer */
+} upap_state;
+
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+
+extern upap_state upap[];
+
+void upap_setloginpasswd(int unit, const char *luser, const char *lpassword);
+void upap_authwithpeer (int, char *, char *);
+void upap_authpeer (int);
+
+extern struct protent pap_protent;
+
+#endif /* PAP_H */
+
--- /dev/null
+/*****************************************************************************
+* ppp.c - Network Point to Point Protocol program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher <marc@mbsi.ca>
+* Ported to lwIP.
+* 97-11-05 Guy Lancaster <lancasterg@acm.org>, Global Election Systems Inc.
+* Original.
+*****************************************************************************/
+
+/*
+ * ppp_defs.h - PPP definitions.
+ *
+ * if_pppvar.h - private structures and declarations for PPP.
+ *
+ * Copyright (c) 1994 The Australian National University.
+ * All rights reserved.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, provided that the above copyright
+ * notice appears in all copies. This software is provided without any
+ * warranty, express or implied. The Australian National University
+ * makes no representations about the suitability of this software for
+ * any purpose.
+ *
+ * IN NO EVENT SHALL THE AUSTRALIAN NATIONAL UNIVERSITY BE LIABLE TO ANY
+ * PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES
+ * ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF
+ * THE AUSTRALIAN NATIONAL UNIVERSITY HAVE BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * THE AUSTRALIAN NATIONAL UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS
+ * ON AN "AS IS" BASIS, AND THE AUSTRALIAN NATIONAL UNIVERSITY HAS NO
+ * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS,
+ * OR MODIFICATIONS.
+ */
+
+/*
+ * if_ppp.h - Point-to-Point Protocol definitions.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University. The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include <string.h>
+
+#include "ppp.h"
+#if PPP_SUPPORT > 0
+#include "randm.h"
+#include "fsm.h"
+#if PAP_SUPPORT > 0
+#include "pap.h"
+#endif
+#if CHAP_SUPPORT > 0
+#include "chap.h"
+#endif
+#include "ipcp.h"
+#include "lcp.h"
+#include "magic.h"
+#include "auth.h"
+#if VJ_SUPPORT > 0
+#include "vj.h"
+#endif
+
+#include "pppdebug.h"
+
+/*************************/
+/*** LOCAL DEFINITIONS ***/
+/*************************/
+
+/*
+ * The basic PPP frame.
+ */
+#define PPP_ADDRESS(p) (((u_char *)(p))[0])
+#define PPP_CONTROL(p) (((u_char *)(p))[1])
+#define PPP_PROTOCOL(p) ((((u_char *)(p))[2] << 8) + ((u_char *)(p))[3])
+
+/* PPP packet parser states. Current state indicates operation yet to be
+ * completed. */
+typedef enum {
+ PDIDLE = 0, /* Idle state - waiting. */
+ PDSTART, /* Process start flag. */
+ PDADDRESS, /* Process address field. */
+ PDCONTROL, /* Process control field. */
+ PDPROTOCOL1, /* Process protocol field 1. */
+ PDPROTOCOL2, /* Process protocol field 2. */
+ PDDATA /* Process data byte. */
+} PPPDevStates;
+
+#define ESCAPE_P(accm, c) ((accm)[(c) >> 3] & pppACCMMask[c & 0x07])
+
+/************************/
+/*** LOCAL DATA TYPES ***/
+/************************/
+/*
+ * PPP interface control block.
+ */
+typedef struct PPPControl_s {
+ char openFlag; /* True when in use. */
+ char oldFrame; /* Old framing character for fd. */
+ sio_fd_t fd; /* File device ID of port. */
+ int kill_link; /* Shut the link down. */
+ int sig_hup; /* Carrier lost. */
+ int if_up; /* True when the interface is up. */
+ int errCode; /* Code indicating why interface is down. */
+ struct pbuf *inHead, *inTail; /* The input packet. */
+ PPPDevStates inState; /* The input process state. */
+ char inEscaped; /* Escape next character. */
+ u16_t inProtocol; /* The input protocol code. */
+ u16_t inFCS; /* Input Frame Check Sequence value. */
+ int mtu; /* Peer's mru */
+ int pcomp; /* Does peer accept protocol compression? */
+ int accomp; /* Does peer accept addr/ctl compression? */
+ u_long lastXMit; /* Time of last transmission. */
+ ext_accm inACCM; /* Async-Ctl-Char-Map for input. */
+ ext_accm outACCM; /* Async-Ctl-Char-Map for output. */
+#if VJ_SUPPORT > 0
+ int vjEnabled; /* Flag indicating VJ compression enabled. */
+ struct vjcompress vjComp; /* Van Jabobsen compression header. */
+#endif
+
+ struct netif netif;
+
+ struct ppp_addrs addrs;
+
+ void (*linkStatusCB)(void *ctx, int errCode, void *arg);
+ void *linkStatusCtx;
+
+} PPPControl;
+
+
+/*
+ * Ioctl definitions.
+ */
+
+struct npioctl {
+ int protocol; /* PPP procotol, e.g. PPP_IP */
+ enum NPmode mode;
+};
+
+
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+static void pppMain(void *pd);
+static void pppDrop(PPPControl *pc);
+static void pppInProc(int pd, u_char *s, int l);
+
+
+/******************************/
+/*** PUBLIC DATA STRUCTURES ***/
+/******************************/
+u_long subnetMask;
+
+static PPPControl pppControl[NUM_PPP]; /* The PPP interface control blocks. */
+
+/*
+ * PPP Data Link Layer "protocol" table.
+ * One entry per supported protocol.
+ * The last entry must be NULL.
+ */
+struct protent *ppp_protocols[] = {
+ &lcp_protent,
+#if PAP_SUPPORT > 0
+ &pap_protent,
+#endif
+#if CHAP_SUPPORT > 0
+ &chap_protent,
+#endif
+#if CBCP_SUPPORT > 0
+ &cbcp_protent,
+#endif
+ &ipcp_protent,
+#if CCP_SUPPORT > 0
+ &ccp_protent,
+#endif
+ NULL
+};
+
+
+/*
+ * Buffers for outgoing packets. This must be accessed only from the appropriate
+ * PPP task so that it doesn't need to be protected to avoid collisions.
+ */
+u_char outpacket_buf[NUM_PPP][PPP_MRU+PPP_HDRLEN];
+
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+
+/*
+ * FCS lookup table as calculated by genfcstab.
+ */
+static const u_short fcstab[256] = {
+ 0x0000, 0x1189, 0x2312, 0x329b, 0x4624, 0x57ad, 0x6536, 0x74bf,
+ 0x8c48, 0x9dc1, 0xaf5a, 0xbed3, 0xca6c, 0xdbe5, 0xe97e, 0xf8f7,
+ 0x1081, 0x0108, 0x3393, 0x221a, 0x56a5, 0x472c, 0x75b7, 0x643e,
+ 0x9cc9, 0x8d40, 0xbfdb, 0xae52, 0xdaed, 0xcb64, 0xf9ff, 0xe876,
+ 0x2102, 0x308b, 0x0210, 0x1399, 0x6726, 0x76af, 0x4434, 0x55bd,
+ 0xad4a, 0xbcc3, 0x8e58, 0x9fd1, 0xeb6e, 0xfae7, 0xc87c, 0xd9f5,
+ 0x3183, 0x200a, 0x1291, 0x0318, 0x77a7, 0x662e, 0x54b5, 0x453c,
+ 0xbdcb, 0xac42, 0x9ed9, 0x8f50, 0xfbef, 0xea66, 0xd8fd, 0xc974,
+ 0x4204, 0x538d, 0x6116, 0x709f, 0x0420, 0x15a9, 0x2732, 0x36bb,
+ 0xce4c, 0xdfc5, 0xed5e, 0xfcd7, 0x8868, 0x99e1, 0xab7a, 0xbaf3,
+ 0x5285, 0x430c, 0x7197, 0x601e, 0x14a1, 0x0528, 0x37b3, 0x263a,
+ 0xdecd, 0xcf44, 0xfddf, 0xec56, 0x98e9, 0x8960, 0xbbfb, 0xaa72,
+ 0x6306, 0x728f, 0x4014, 0x519d, 0x2522, 0x34ab, 0x0630, 0x17b9,
+ 0xef4e, 0xfec7, 0xcc5c, 0xddd5, 0xa96a, 0xb8e3, 0x8a78, 0x9bf1,
+ 0x7387, 0x620e, 0x5095, 0x411c, 0x35a3, 0x242a, 0x16b1, 0x0738,
+ 0xffcf, 0xee46, 0xdcdd, 0xcd54, 0xb9eb, 0xa862, 0x9af9, 0x8b70,
+ 0x8408, 0x9581, 0xa71a, 0xb693, 0xc22c, 0xd3a5, 0xe13e, 0xf0b7,
+ 0x0840, 0x19c9, 0x2b52, 0x3adb, 0x4e64, 0x5fed, 0x6d76, 0x7cff,
+ 0x9489, 0x8500, 0xb79b, 0xa612, 0xd2ad, 0xc324, 0xf1bf, 0xe036,
+ 0x18c1, 0x0948, 0x3bd3, 0x2a5a, 0x5ee5, 0x4f6c, 0x7df7, 0x6c7e,
+ 0xa50a, 0xb483, 0x8618, 0x9791, 0xe32e, 0xf2a7, 0xc03c, 0xd1b5,
+ 0x2942, 0x38cb, 0x0a50, 0x1bd9, 0x6f66, 0x7eef, 0x4c74, 0x5dfd,
+ 0xb58b, 0xa402, 0x9699, 0x8710, 0xf3af, 0xe226, 0xd0bd, 0xc134,
+ 0x39c3, 0x284a, 0x1ad1, 0x0b58, 0x7fe7, 0x6e6e, 0x5cf5, 0x4d7c,
+ 0xc60c, 0xd785, 0xe51e, 0xf497, 0x8028, 0x91a1, 0xa33a, 0xb2b3,
+ 0x4a44, 0x5bcd, 0x6956, 0x78df, 0x0c60, 0x1de9, 0x2f72, 0x3efb,
+ 0xd68d, 0xc704, 0xf59f, 0xe416, 0x90a9, 0x8120, 0xb3bb, 0xa232,
+ 0x5ac5, 0x4b4c, 0x79d7, 0x685e, 0x1ce1, 0x0d68, 0x3ff3, 0x2e7a,
+ 0xe70e, 0xf687, 0xc41c, 0xd595, 0xa12a, 0xb0a3, 0x8238, 0x93b1,
+ 0x6b46, 0x7acf, 0x4854, 0x59dd, 0x2d62, 0x3ceb, 0x0e70, 0x1ff9,
+ 0xf78f, 0xe606, 0xd49d, 0xc514, 0xb1ab, 0xa022, 0x92b9, 0x8330,
+ 0x7bc7, 0x6a4e, 0x58d5, 0x495c, 0x3de3, 0x2c6a, 0x1ef1, 0x0f78
+};
+
+/* PPP's Asynchronous-Control-Character-Map. The mask array is used
+ * to select the specific bit for a character. */
+static u_char pppACCMMask[] = {
+ 0x01,
+ 0x02,
+ 0x04,
+ 0x08,
+ 0x10,
+ 0x20,
+ 0x40,
+ 0x80
+};
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/* Initialize the PPP subsystem. */
+
+struct ppp_settings ppp_settings;
+
+void pppInit(void)
+{
+ struct protent *protp;
+ int i, j;
+
+ memset(&ppp_settings, 0, sizeof(ppp_settings));
+ ppp_settings.usepeerdns = 1;
+ pppSetAuth(PPPAUTHTYPE_NONE, NULL, NULL);
+
+ magicInit();
+
+ for (i = 0; i < NUM_PPP; i++) {
+ pppControl[i].openFlag = 0;
+
+ subnetMask = htonl(0xffffff00);
+
+ /*
+ * Initialize to the standard option set.
+ */
+ for (j = 0; (protp = ppp_protocols[j]) != NULL; ++j)
+ (*protp->init)(i);
+ }
+
+#if LINK_STATS
+ /* Clear the statistics. */
+ memset(&lwip_stats.link, 0, sizeof(lwip_stats.link));
+#endif
+}
+
+void pppSetAuth(enum pppAuthType authType, const char *user, const char *passwd)
+{
+ switch(authType) {
+ case PPPAUTHTYPE_NONE:
+ default:
+#ifdef LWIP_PPP_STRICT_PAP_REJECT
+ ppp_settings.refuse_pap = 1;
+#else
+ /* some providers request pap and accept an empty login/pw */
+ ppp_settings.refuse_pap = 0;
+#endif
+ ppp_settings.refuse_chap = 1;
+ break;
+ case PPPAUTHTYPE_ANY:
+/* Warning: Using PPPAUTHTYPE_ANY might have security consequences.
+ * RFC 1994 says:
+ *
+ * In practice, within or associated with each PPP server, there is a
+ * database which associates "user" names with authentication
+ * information ("secrets"). It is not anticipated that a particular
+ * named user would be authenticated by multiple methods. This would
+ * make the user vulnerable to attacks which negotiate the least secure
+ * method from among a set (such as PAP rather than CHAP). If the same
+ * secret was used, PAP would reveal the secret to be used later with
+ * CHAP.
+ *
+ * Instead, for each user name there should be an indication of exactly
+ * one method used to authenticate that user name. If a user needs to
+ * make use of different authentication methods under different
+ * circumstances, then distinct user names SHOULD be employed, each of
+ * which identifies exactly one authentication method.
+ *
+ */
+ ppp_settings.refuse_pap = 0;
+ ppp_settings.refuse_chap = 0;
+ break;
+ case PPPAUTHTYPE_PAP:
+ ppp_settings.refuse_pap = 0;
+ ppp_settings.refuse_chap = 1;
+ break;
+ case PPPAUTHTYPE_CHAP:
+ ppp_settings.refuse_pap = 1;
+ ppp_settings.refuse_chap = 0;
+ break;
+ }
+
+ if(user) {
+ strncpy(ppp_settings.user, user, sizeof(ppp_settings.user)-1);
+ ppp_settings.user[sizeof(ppp_settings.user)-1] = '\0';
+ } else
+ ppp_settings.user[0] = '\0';
+
+ if(passwd) {
+ strncpy(ppp_settings.passwd, passwd, sizeof(ppp_settings.passwd)-1);
+ ppp_settings.passwd[sizeof(ppp_settings.passwd)-1] = '\0';
+ } else
+ ppp_settings.passwd[0] = '\0';
+}
+
+/* Open a new PPP connection using the given I/O device.
+ * This initializes the PPP control block but does not
+ * attempt to negotiate the LCP session. If this port
+ * connects to a modem, the modem connection must be
+ * established before calling this.
+ * Return a new PPP connection descriptor on success or
+ * an error code (negative) on failure. */
+int pppOpen(sio_fd_t fd, void (*linkStatusCB)(void *ctx, int errCode, void *arg), void *linkStatusCtx)
+{
+ PPPControl *pc;
+ int pd;
+
+ /* Find a free PPP session descriptor. Critical region? */
+ for (pd = 0; pd < NUM_PPP && pppControl[pd].openFlag != 0; pd++);
+ if (pd >= NUM_PPP)
+ pd = PPPERR_OPEN;
+ else
+ pppControl[pd].openFlag = !0;
+
+ /* Launch a deamon thread. */
+ if (pd >= 0) {
+
+ pppControl[pd].openFlag = 1;
+
+ lcp_init(pd);
+ pc = &pppControl[pd];
+ pc->fd = fd;
+ pc->kill_link = 0;
+ pc->sig_hup = 0;
+ pc->if_up = 0;
+ pc->errCode = 0;
+ pc->inState = PDIDLE;
+ pc->inHead = NULL;
+ pc->inTail = NULL;
+ pc->inEscaped = 0;
+ pc->lastXMit = 0;
+
+#if VJ_SUPPORT > 0
+ pc->vjEnabled = 0;
+ vj_compress_init(&pc->vjComp);
+#endif
+
+ /*
+ * Default the in and out accm so that escape and flag characters
+ * are always escaped.
+ */
+ memset(pc->inACCM, 0, sizeof(ext_accm));
+ pc->inACCM[15] = 0x60;
+ memset(pc->outACCM, 0, sizeof(ext_accm));
+ pc->outACCM[15] = 0x60;
+
+ pc->linkStatusCB = linkStatusCB;
+ pc->linkStatusCtx = linkStatusCtx;
+
+ sys_thread_new(pppMain, (void*)pd, PPP_THREAD_PRIO);
+ if(!linkStatusCB) {
+ while(pd >= 0 && !pc->if_up) {
+ sys_msleep(500);
+ if (lcp_phase[pd] == PHASE_DEAD) {
+ pppClose(pd);
+ if (pc->errCode)
+ pd = pc->errCode;
+ else
+ pd = PPPERR_CONNECT;
+ }
+ }
+ }
+ }
+ return pd;
+}
+
+/* Close a PPP connection and release the descriptor.
+ * Any outstanding packets in the queues are dropped.
+ * Return 0 on success, an error code on failure. */
+int pppClose(int pd)
+{
+ PPPControl *pc = &pppControl[pd];
+ int st = 0;
+
+ /* Disconnect */
+ pc->kill_link = !0;
+ pppMainWakeup(pd);
+
+ if(!pc->linkStatusCB) {
+ while(st >= 0 && lcp_phase[pd] != PHASE_DEAD) {
+ sys_msleep(500);
+ break;
+ }
+ }
+ return st;
+}
+
+/* This function is called when carrier is lost on the PPP channel. */
+void pppSigHUP(int pd)
+{
+ PPPControl *pc = &pppControl[pd];
+
+ pc->sig_hup = 1;
+ pppMainWakeup(pd);
+}
+
+static void nPut(PPPControl *pc, struct pbuf *nb)
+{
+ struct pbuf *b;
+ int c;
+
+ for(b = nb; b != NULL; b = b->next) {
+ if((c = sio_write(pc->fd, b->payload, b->len)) != b->len) {
+ PPPDEBUG((LOG_WARNING,
+ "PPP nPut: incomplete sio_write(%d,, %u) = %d\n", pc->fd, b->len, c));
+#if LINK_STATS
+ lwip_stats.link.err++;
+#endif /* LINK_STATS */
+ pc->lastXMit = 0; /* prepend PPP_FLAG to next packet */
+ break;
+ }
+ }
+ pbuf_free(nb);
+
+#if LINK_STATS
+ lwip_stats.link.xmit++;
+#endif /* LINK_STATS */
+}
+
+/*
+ * pppAppend - append given character to end of given pbuf. If outACCM
+ * is not NULL and the character needs to be escaped, do so.
+ * If pbuf is full, append another.
+ * Return the current pbuf.
+ */
+static struct pbuf *pppAppend(u_char c, struct pbuf *nb, ext_accm *outACCM)
+{
+ struct pbuf *tb = nb;
+
+ /* Make sure there is room for the character and an escape code.
+ * Sure we don't quite fill the buffer if the character doesn't
+ * get escaped but is one character worth complicating this? */
+ /* Note: We assume no packet header. */
+ if (nb && (PBUF_POOL_BUFSIZE - nb->len) < 2) {
+ tb = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL);
+ if (tb) {
+ nb->next = tb;
+ }
+#if LINK_STATS
+ else {
+ lwip_stats.link.memerr++;
+ }
+#endif /* LINK_STATS */
+ nb = tb;
+ }
+ if (nb) {
+ if (outACCM && ESCAPE_P(*outACCM, c)) {
+ *((u_char*)nb->payload + nb->len++) = PPP_ESCAPE;
+ *((u_char*)nb->payload + nb->len++) = c ^ PPP_TRANS;
+ }
+ else
+ *((u_char*)nb->payload + nb->len++) = c;
+ }
+
+ return tb;
+}
+
+/* Send a packet on the given connection. */
+static err_t pppifOutput(struct netif *netif, struct pbuf *pb, struct ip_addr *ipaddr)
+{
+ int pd = (int)netif->state;
+ u_short protocol = PPP_IP;
+ PPPControl *pc = &pppControl[pd];
+ u_int fcsOut = PPP_INITFCS;
+ struct pbuf *headMB = NULL, *tailMB = NULL, *p;
+ u_char c;
+
+ (void)ipaddr;
+
+ /* Validate parameters. */
+ /* We let any protocol value go through - it can't hurt us
+ * and the peer will just drop it if it's not accepting it. */
+ if (pd < 0 || pd >= NUM_PPP || !pc->openFlag || !pb) {
+ PPPDEBUG((LOG_WARNING, "pppifOutput[%d]: bad parms prot=%d pb=%p\n",
+ pd, protocol, pb));
+#if LINK_STATS
+ lwip_stats.link.opterr++;
+ lwip_stats.link.drop++;
+#endif
+ return ERR_ARG;
+ }
+
+ /* Check that the link is up. */
+ if (lcp_phase[pd] == PHASE_DEAD) {
+ PPPDEBUG((LOG_ERR, "pppifOutput[%d]: link not up\n", pd));
+#if LINK_STATS
+ lwip_stats.link.rterr++;
+ lwip_stats.link.drop++;
+#endif
+ return ERR_RTE;
+ }
+
+ /* Grab an output buffer. */
+ headMB = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL);
+ if (headMB == NULL) {
+ PPPDEBUG((LOG_WARNING, "pppifOutput[%d]: first alloc fail\n", pd));
+#if LINK_STATS
+ lwip_stats.link.memerr++;
+ lwip_stats.link.drop++;
+#endif /* LINK_STATS */
+ return ERR_MEM;
+ }
+
+#if VJ_SUPPORT > 0
+ /*
+ * Attempt Van Jacobson header compression if VJ is configured and
+ * this is an IP packet.
+ */
+ if (protocol == PPP_IP && pc->vjEnabled) {
+ switch (vj_compress_tcp(&pc->vjComp, pb)) {
+ case TYPE_IP:
+ /* No change...
+ protocol = PPP_IP_PROTOCOL;
+ */
+ break;
+ case TYPE_COMPRESSED_TCP:
+ protocol = PPP_VJC_COMP;
+ break;
+ case TYPE_UNCOMPRESSED_TCP:
+ protocol = PPP_VJC_UNCOMP;
+ break;
+ default:
+ PPPDEBUG((LOG_WARNING, "pppifOutput[%d]: bad IP packet\n", pd));
+#if LINK_STATS
+ lwip_stats.link.proterr++;
+ lwip_stats.link.drop++;
+#endif
+ pbuf_free(headMB);
+ return ERR_VAL;
+ }
+ }
+#endif
+
+ tailMB = headMB;
+
+ /* Build the PPP header. */
+ if ((sys_jiffies() - pc->lastXMit) >= PPP_MAXIDLEFLAG)
+ tailMB = pppAppend(PPP_FLAG, tailMB, NULL);
+ pc->lastXMit = sys_jiffies();
+ if (!pc->accomp) {
+ fcsOut = PPP_FCS(fcsOut, PPP_ALLSTATIONS);
+ tailMB = pppAppend(PPP_ALLSTATIONS, tailMB, &pc->outACCM);
+ fcsOut = PPP_FCS(fcsOut, PPP_UI);
+ tailMB = pppAppend(PPP_UI, tailMB, &pc->outACCM);
+ }
+ if (!pc->pcomp || protocol > 0xFF) {
+ c = (protocol >> 8) & 0xFF;
+ fcsOut = PPP_FCS(fcsOut, c);
+ tailMB = pppAppend(c, tailMB, &pc->outACCM);
+ }
+ c = protocol & 0xFF;
+ fcsOut = PPP_FCS(fcsOut, c);
+ tailMB = pppAppend(c, tailMB, &pc->outACCM);
+
+ /* Load packet. */
+ for(p = pb; p; p = p->next) {
+ int n;
+ u_char *sPtr;
+
+ sPtr = (u_char*)p->payload;
+ n = p->len;
+ while (n-- > 0) {
+ c = *sPtr++;
+
+ /* Update FCS before checking for special characters. */
+ fcsOut = PPP_FCS(fcsOut, c);
+
+ /* Copy to output buffer escaping special characters. */
+ tailMB = pppAppend(c, tailMB, &pc->outACCM);
+ }
+ }
+
+ /* Add FCS and trailing flag. */
+ c = ~fcsOut & 0xFF;
+ tailMB = pppAppend(c, tailMB, &pc->outACCM);
+ c = (~fcsOut >> 8) & 0xFF;
+ tailMB = pppAppend(c, tailMB, &pc->outACCM);
+ tailMB = pppAppend(PPP_FLAG, tailMB, NULL);
+
+ /* If we failed to complete the packet, throw it away. */
+ if (!tailMB) {
+ PPPDEBUG((LOG_WARNING,
+ "pppifOutput[%d]: Alloc err - dropping proto=%d\n",
+ pd, protocol));
+ pbuf_free(headMB);
+#if LINK_STATS
+ lwip_stats.link.memerr++;
+ lwip_stats.link.drop++;
+#endif
+ return ERR_MEM;
+ }
+
+ /* Send it. */
+ PPPDEBUG((LOG_INFO, "pppifOutput[%d]: proto=0x%04X\n", pd, protocol));
+
+ nPut(pc, headMB);
+
+ return ERR_OK;
+}
+
+/* Get and set parameters for the given connection.
+ * Return 0 on success, an error code on failure. */
+int pppIOCtl(int pd, int cmd, void *arg)
+{
+ PPPControl *pc = &pppControl[pd];
+ int st = 0;
+
+ if (pd < 0 || pd >= NUM_PPP)
+ st = PPPERR_PARAM;
+ else {
+ switch(cmd) {
+ case PPPCTLG_UPSTATUS: /* Get the PPP up status. */
+ if (arg)
+ *(int *)arg = (int)(pc->if_up);
+ else
+ st = PPPERR_PARAM;
+ break;
+ case PPPCTLS_ERRCODE: /* Set the PPP error code. */
+ if (arg)
+ pc->errCode = *(int *)arg;
+ else
+ st = PPPERR_PARAM;
+ break;
+ case PPPCTLG_ERRCODE: /* Get the PPP error code. */
+ if (arg)
+ *(int *)arg = (int)(pc->errCode);
+ else
+ st = PPPERR_PARAM;
+ break;
+ case PPPCTLG_FD:
+ if (arg)
+ *(sio_fd_t *)arg = pc->fd;
+ else
+ st = PPPERR_PARAM;
+ break;
+ default:
+ st = PPPERR_PARAM;
+ break;
+ }
+ }
+
+ return st;
+}
+
+/*
+ * Return the Maximum Transmission Unit for the given PPP connection.
+ */
+u_int pppMTU(int pd)
+{
+ PPPControl *pc = &pppControl[pd];
+ u_int st;
+
+ /* Validate parameters. */
+ if (pd < 0 || pd >= NUM_PPP || !pc->openFlag)
+ st = 0;
+ else
+ st = pc->mtu;
+
+ return st;
+}
+
+/*
+ * Write n characters to a ppp link.
+ * RETURN: >= 0 Number of characters written
+ * -1 Failed to write to device
+ */
+int pppWrite(int pd, const u_char *s, int n)
+{
+ PPPControl *pc = &pppControl[pd];
+ u_char c;
+ u_int fcsOut = PPP_INITFCS;
+ struct pbuf *headMB = NULL, *tailMB;
+ headMB = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL);
+ if (headMB == NULL) {
+#if LINK_STATS
+ lwip_stats.link.memerr++;
+ lwip_stats.link.proterr++;
+#endif /* LINK_STATS */
+ return PPPERR_ALLOC;
+ }
+
+ tailMB = headMB;
+
+ /* If the link has been idle, we'll send a fresh flag character to
+ * flush any noise. */
+ if ((sys_jiffies() - pc->lastXMit) >= PPP_MAXIDLEFLAG)
+ tailMB = pppAppend(PPP_FLAG, tailMB, NULL);
+ pc->lastXMit = sys_jiffies();
+
+ /* Load output buffer. */
+ while (n-- > 0) {
+ c = *s++;
+
+ /* Update FCS before checking for special characters. */
+ fcsOut = PPP_FCS(fcsOut, c);
+
+ /* Copy to output buffer escaping special characters. */
+ tailMB = pppAppend(c, tailMB, &pc->outACCM);
+ }
+
+ /* Add FCS and trailing flag. */
+ c = ~fcsOut & 0xFF;
+ tailMB = pppAppend(c, tailMB, &pc->outACCM);
+ c = (~fcsOut >> 8) & 0xFF;
+ tailMB = pppAppend(c, tailMB, &pc->outACCM);
+ tailMB = pppAppend(PPP_FLAG, tailMB, NULL);
+
+ /* If we failed to complete the packet, throw it away.
+ * Otherwise send it. */
+ if (!tailMB) {
+ PPPDEBUG((LOG_WARNING,
+ "pppWrite[%d]: Alloc err - dropping pbuf len=%d\n", pd, headMB->len));
+/* "pppWrite[%d]: Alloc err - dropping %d:%.*H", pd, headMB->len, LWIP_MIN(headMB->len * 2, 40), headMB->payload)); */
+ pbuf_free(headMB);
+#if LINK_STATS
+ lwip_stats.link.memerr++;
+ lwip_stats.link.proterr++;
+#endif /* LINK_STATS */
+ return PPPERR_ALLOC;
+ }
+
+ PPPDEBUG((LOG_INFO, "pppWrite[%d]: len=%d\n", pd, headMB->len));
+/* "pppWrite[%d]: %d:%.*H", pd, headMB->len, LWIP_MIN(headMB->len * 2, 40), headMB->payload)); */
+ nPut(pc, headMB);
+
+ return PPPERR_NONE;
+}
+
+/*
+ * ppp_send_config - configure the transmit characteristics of
+ * the ppp interface.
+ */
+void ppp_send_config(
+ int unit,
+ int mtu,
+ u32_t asyncmap,
+ int pcomp,
+ int accomp
+)
+{
+ PPPControl *pc = &pppControl[unit];
+ int i;
+
+ pc->mtu = mtu;
+ pc->pcomp = pcomp;
+ pc->accomp = accomp;
+
+ /* Load the ACCM bits for the 32 control codes. */
+ for (i = 0; i < 32/8; i++)
+ pc->outACCM[i] = (u_char)((asyncmap >> (8 * i)) & 0xFF);
+ PPPDEBUG((LOG_INFO, "ppp_send_config[%d]: outACCM=%X %X %X %X\n",
+ unit,
+ pc->outACCM[0], pc->outACCM[1], pc->outACCM[2], pc->outACCM[3]));
+}
+
+
+/*
+ * ppp_set_xaccm - set the extended transmit ACCM for the interface.
+ */
+void ppp_set_xaccm(int unit, ext_accm *accm)
+{
+ memcpy(pppControl[unit].outACCM, accm, sizeof(ext_accm));
+ PPPDEBUG((LOG_INFO, "ppp_set_xaccm[%d]: outACCM=%X %X %X %X\n",
+ unit,
+ pppControl[unit].outACCM[0],
+ pppControl[unit].outACCM[1],
+ pppControl[unit].outACCM[2],
+ pppControl[unit].outACCM[3]));
+}
+
+
+/*
+ * ppp_recv_config - configure the receive-side characteristics of
+ * the ppp interface.
+ */
+void ppp_recv_config(
+ int unit,
+ int mru,
+ u32_t asyncmap,
+ int pcomp,
+ int accomp
+)
+{
+ PPPControl *pc = &pppControl[unit];
+ int i;
+
+ (void)accomp;
+ (void)pcomp;
+ (void)mru;
+
+ /* Load the ACCM bits for the 32 control codes. */
+ for (i = 0; i < 32 / 8; i++)
+ pc->inACCM[i] = (u_char)(asyncmap >> (i * 8));
+ PPPDEBUG((LOG_INFO, "ppp_recv_config[%d]: inACCM=%X %X %X %X\n",
+ unit,
+ pc->inACCM[0], pc->inACCM[1], pc->inACCM[2], pc->inACCM[3]));
+}
+
+#if 0
+/*
+ * ccp_test - ask kernel whether a given compression method
+ * is acceptable for use. Returns 1 if the method and parameters
+ * are OK, 0 if the method is known but the parameters are not OK
+ * (e.g. code size should be reduced), or -1 if the method is unknown.
+ */
+int ccp_test(
+ int unit,
+ int opt_len,
+ int for_transmit,
+ u_char *opt_ptr
+)
+{
+ return 0; /* XXX Currently no compression. */
+}
+
+/*
+ * ccp_flags_set - inform kernel about the current state of CCP.
+ */
+void ccp_flags_set(int unit, int isopen, int isup)
+{
+ /* XXX */
+}
+
+/*
+ * ccp_fatal_error - returns 1 if decompression was disabled as a
+ * result of an error detected after decompression of a packet,
+ * 0 otherwise. This is necessary because of patent nonsense.
+ */
+int ccp_fatal_error(int unit)
+{
+ /* XXX */
+ return 0;
+}
+#endif
+
+/*
+ * get_idle_time - return how long the link has been idle.
+ */
+int get_idle_time(int u, struct ppp_idle *ip)
+{
+ /* XXX */
+ (void)u;
+ (void)ip;
+
+ return 0;
+}
+
+
+/*
+ * Return user specified netmask, modified by any mask we might determine
+ * for address `addr' (in network byte order).
+ * Here we scan through the system's list of interfaces, looking for
+ * any non-point-to-point interfaces which might appear to be on the same
+ * network as `addr'. If we find any, we OR in their netmask to the
+ * user-specified netmask.
+ */
+u32_t GetMask(u32_t addr)
+{
+ u32_t mask, nmask;
+
+ htonl(addr);
+ if (IN_CLASSA(addr)) /* determine network mask for address class */
+ nmask = IN_CLASSA_NET;
+ else if (IN_CLASSB(addr))
+ nmask = IN_CLASSB_NET;
+ else
+ nmask = IN_CLASSC_NET;
+ /* class D nets are disallowed by bad_ip_adrs */
+ mask = subnetMask | htonl(nmask);
+
+ /* XXX
+ * Scan through the system's network interfaces.
+ * Get each netmask and OR them into our mask.
+ */
+
+ return mask;
+}
+
+/*
+ * sifvjcomp - config tcp header compression
+ */
+int sifvjcomp(
+ int pd,
+ int vjcomp,
+ int cidcomp,
+ int maxcid
+)
+{
+#if VJ_SUPPORT > 0
+ PPPControl *pc = &pppControl[pd];
+
+ pc->vjEnabled = vjcomp;
+ pc->vjComp.compressSlot = cidcomp;
+ pc->vjComp.maxSlotIndex = maxcid;
+ PPPDEBUG((LOG_INFO, "sifvjcomp: VJ compress enable=%d slot=%d max slot=%d\n",
+ vjcomp, cidcomp, maxcid));
+#endif
+
+ return 0;
+}
+
+/*
+ * pppifNetifInit - netif init callback
+ */
+static err_t pppifNetifInit(struct netif *netif)
+{
+ netif->name[0] = 'p';
+ netif->name[1] = 'p';
+ netif->output = pppifOutput;
+ netif->mtu = pppMTU((int)netif->state);
+ return ERR_OK;
+}
+
+
+/*
+ * sifup - Config the interface up and enable IP packets to pass.
+ */
+int sifup(int pd)
+{
+ PPPControl *pc = &pppControl[pd];
+ int st = 1;
+
+ if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
+ st = 0;
+ PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd));
+ } else {
+ netif_remove(&pc->netif);
+ if (netif_add(&pc->netif, &pc->addrs.our_ipaddr, &pc->addrs.netmask, &pc->addrs.his_ipaddr, (void *)pd, pppifNetifInit, ip_input)) {
+ pc->if_up = 1;
+ pc->errCode = PPPERR_NONE;
+
+ PPPDEBUG((LOG_DEBUG, "sifup: unit %d: linkStatusCB=%lx errCode=%d\n", pd, pc->linkStatusCB, pc->errCode));
+ if(pc->linkStatusCB)
+ pc->linkStatusCB(pc->linkStatusCtx, pc->errCode, &pc->addrs);
+ } else {
+ st = 0;
+ PPPDEBUG((LOG_ERR, "sifup[%d]: netif_add failed\n", pd));
+ }
+ }
+
+ return st;
+}
+
+/*
+ * sifnpmode - Set the mode for handling packets for a given NP.
+ */
+int sifnpmode(int u, int proto, enum NPmode mode)
+{
+ (void)u;
+ (void)proto;
+ (void)mode;
+ return 0;
+}
+
+/*
+ * sifdown - Config the interface down and disable IP.
+ */
+int sifdown(int pd)
+{
+ PPPControl *pc = &pppControl[pd];
+ int st = 1;
+
+ if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
+ st = 0;
+ PPPDEBUG((LOG_WARNING, "sifdown[%d]: bad parms\n", pd));
+ } else {
+ pc->if_up = 0;
+ netif_remove(&pc->netif);
+ PPPDEBUG((LOG_DEBUG, "sifdown: unit %d: linkStatusCB=%lx errCode=%d\n", pd, pc->linkStatusCB, pc->errCode));
+ if(pc->linkStatusCB)
+ pc->linkStatusCB(pc->linkStatusCtx, PPPERR_CONNECT, NULL);
+ }
+ return st;
+}
+
+/*
+ * sifaddr - Config the interface IP addresses and netmask.
+ */
+int sifaddr(
+ int pd, /* Interface unit ??? */
+ u32_t o, /* Our IP address ??? */
+ u32_t h, /* His IP address ??? */
+ u32_t m, /* IP subnet mask ??? */
+ u32_t ns1, /* Primary DNS */
+ u32_t ns2 /* Secondary DNS */
+)
+{
+ PPPControl *pc = &pppControl[pd];
+ int st = 1;
+
+ if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
+ st = 0;
+ PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd));
+ } else {
+ memcpy(&pc->addrs.our_ipaddr, &o, sizeof(o));
+ memcpy(&pc->addrs.his_ipaddr, &h, sizeof(h));
+ memcpy(&pc->addrs.netmask, &m, sizeof(m));
+ memcpy(&pc->addrs.dns1, &ns1, sizeof(ns1));
+ memcpy(&pc->addrs.dns2, &ns2, sizeof(ns2));
+ }
+ return st;
+}
+
+/*
+ * cifaddr - Clear the interface IP addresses, and delete routes
+ * through the interface if possible.
+ */
+int cifaddr(
+ int pd, /* Interface unit ??? */
+ u32_t o, /* Our IP address ??? */
+ u32_t h /* IP broadcast address ??? */
+)
+{
+ PPPControl *pc = &pppControl[pd];
+ int st = 1;
+
+ (void)o;
+ (void)h;
+ if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
+ st = 0;
+ PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd));
+ } else {
+ IP4_ADDR(&pc->addrs.our_ipaddr, 0,0,0,0);
+ IP4_ADDR(&pc->addrs.his_ipaddr, 0,0,0,0);
+ IP4_ADDR(&pc->addrs.netmask, 255,255,255,0);
+ IP4_ADDR(&pc->addrs.dns1, 0,0,0,0);
+ IP4_ADDR(&pc->addrs.dns2, 0,0,0,0);
+ }
+ return st;
+}
+
+/*
+ * sifdefaultroute - assign a default route through the address given.
+ */
+int sifdefaultroute(int pd, u32_t l, u32_t g)
+{
+ PPPControl *pc = &pppControl[pd];
+ int st = 1;
+
+ (void)l;
+ (void)g;
+ if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
+ st = 0;
+ PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd));
+ } else {
+ netif_set_default(&pc->netif);
+ }
+
+ /* TODO: check how PPP handled the netMask, previously not set by ipSetDefault */
+
+ return st;
+}
+
+/*
+ * cifdefaultroute - delete a default route through the address given.
+ */
+int cifdefaultroute(int pd, u32_t l, u32_t g)
+{
+ PPPControl *pc = &pppControl[pd];
+ int st = 1;
+
+ (void)l;
+ (void)g;
+ if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
+ st = 0;
+ PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd));
+ } else {
+ netif_set_default(NULL);
+ }
+
+ return st;
+}
+
+void
+pppMainWakeup(int pd)
+{
+ PPPDEBUG((LOG_DEBUG, "pppMainWakeup: unit %d\n", pd));
+ sio_read_abort(pppControl[pd].fd);
+}
+
+/* these callbacks are necessary because lcp_* functions
+ must be called in the same context as pppInput(),
+ namely the tcpip_thread(), essentially because
+ they manipulate timeouts which are thread-private
+*/
+
+static void
+pppStartCB(void *arg)
+{
+ int pd = (int)arg;
+
+ PPPDEBUG((LOG_DEBUG, "pppStartCB: unit %d\n", pd));
+ lcp_lowerup(pd);
+ lcp_open(pd); /* Start protocol */
+}
+
+static void
+pppStopCB(void *arg)
+{
+ int pd = (int)arg;
+
+ PPPDEBUG((LOG_DEBUG, "pppStopCB: unit %d\n", pd));
+ lcp_close(pd, "User request");
+}
+
+static void
+pppHupCB(void *arg)
+{
+ int pd = (int)arg;
+
+ PPPDEBUG((LOG_DEBUG, "pppHupCB: unit %d\n", pd));
+ lcp_lowerdown(pd);
+ link_terminated(pd);
+}
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+/* The main PPP process function. This implements the state machine according
+ * to section 4 of RFC 1661: The Point-To-Point Protocol. */
+static void pppMain(void *arg)
+{
+ int pd = (int)arg;
+ struct pbuf *p;
+ PPPControl* pc;
+
+ pc = &pppControl[pd];
+
+ p = pbuf_alloc(PBUF_RAW, PPP_MRU+PPP_HDRLEN, PBUF_RAM);
+ if(!p) {
+ LWIP_ASSERT("p != NULL", p);
+ pc->errCode = PPPERR_ALLOC;
+ goto out;
+ }
+
+ /*
+ * Start the connection and handle incoming events (packet or timeout).
+ */
+ PPPDEBUG((LOG_INFO, "pppMain: unit %d: Connecting\n", pd));
+ tcpip_callback(pppStartCB, arg);
+ while (lcp_phase[pd] != PHASE_DEAD) {
+ if (pc->kill_link) {
+ PPPDEBUG((LOG_DEBUG, "pppMainWakeup: unit %d kill_link -> pppStopCB\n", pd));
+ pc->errCode = PPPERR_USER;
+ /* This will leave us at PHASE_DEAD. */
+ tcpip_callback(pppStopCB, arg);
+ pc->kill_link = 0;
+ }
+ else if (pc->sig_hup) {
+ PPPDEBUG((LOG_DEBUG, "pppMainWakeup: unit %d sig_hup -> pppHupCB\n", pd));
+ pc->sig_hup = 0;
+ tcpip_callback(pppHupCB, arg);
+ } else {
+ int c = sio_read(pc->fd, p->payload, p->len);
+ if(c > 0) {
+ pppInProc(pd, p->payload, c);
+ } else {
+ PPPDEBUG((LOG_DEBUG, "pppMainWakeup: unit %d sio_read len=%d returned %d\n", pd, p->len, c));
+ sys_msleep(1); /* give other tasks a chance to run */
+ }
+ }
+ }
+ PPPDEBUG((LOG_INFO, "pppMain: unit %d: PHASE_DEAD\n", pd));
+ pbuf_free(p);
+
+out:
+ PPPDEBUG((LOG_DEBUG, "pppMain: unit %d: linkStatusCB=%lx errCode=%d\n", pd, pc->linkStatusCB, pc->errCode));
+ if(pc->linkStatusCB)
+ pc->linkStatusCB(pc->linkStatusCtx, pc->errCode ? pc->errCode : PPPERR_PROTOCOL, NULL);
+
+ pc->openFlag = 0;
+}
+
+static struct pbuf *pppSingleBuf(struct pbuf *p)
+{
+ struct pbuf *q, *b;
+ u_char *pl;
+
+ if(p->tot_len == p->len)
+ return p;
+
+ q = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_RAM);
+ if(!q) {
+ PPPDEBUG((LOG_ERR,
+ "pppSingleBuf: unable to alloc new buf (%d)\n", p->tot_len));
+ return p; /* live dangerously */
+ }
+
+ for(b = p, pl = q->payload; b != NULL; b = b->next) {
+ memcpy(pl, b->payload, b->len);
+ pl += b->len;
+ }
+
+ pbuf_free(p);
+
+ return q;
+}
+
+struct pppInputHeader {
+ int unit;
+ u16_t proto;
+};
+
+/*
+ * Pass the processed input packet to the appropriate handler.
+ * This function and all handlers run in the context of the tcpip_thread
+ */
+static void pppInput(void *arg)
+{
+ struct pbuf *nb = (struct pbuf *)arg;
+ u16_t protocol;
+ int pd;
+
+ pd = ((struct pppInputHeader *)nb->payload)->unit;
+ protocol = ((struct pppInputHeader *)nb->payload)->proto;
+
+ pbuf_header(nb, -(int)sizeof(struct pppInputHeader));
+
+#if LINK_STATS
+ lwip_stats.link.recv++;
+#endif /* LINK_STATS */
+
+ /*
+ * Toss all non-LCP packets unless LCP is OPEN.
+ * Until we get past the authentication phase, toss all packets
+ * except LCP, LQR and authentication packets.
+ */
+ if((lcp_phase[pd] <= PHASE_AUTHENTICATE) && (protocol != PPP_LCP)) {
+ if(!((protocol == PPP_LQR) || (protocol == PPP_PAP) || (protocol == PPP_CHAP)) ||
+ (lcp_phase[pd] != PHASE_AUTHENTICATE)) {
+ PPPDEBUG((LOG_INFO, "pppInput: discarding proto 0x%04X in phase %d\n", protocol, lcp_phase[pd]));
+ goto drop;
+ }
+ }
+
+ switch(protocol) {
+ case PPP_VJC_COMP: /* VJ compressed TCP */
+#if VJ_SUPPORT > 0
+ PPPDEBUG((LOG_INFO, "pppInput[%d]: vj_comp in pbuf len=%d\n", pd, nb->len));
+ /*
+ * Clip off the VJ header and prepend the rebuilt TCP/IP header and
+ * pass the result to IP.
+ */
+ if (vj_uncompress_tcp(&nb, &pppControl[pd].vjComp) >= 0) {
+ pppControl[pd].netif.input(nb, &pppControl[pd].netif);
+ return;
+ }
+ /* Something's wrong so drop it. */
+ PPPDEBUG((LOG_WARNING, "pppInput[%d]: Dropping VJ compressed\n", pd));
+#else
+ /* No handler for this protocol so drop the packet. */
+ PPPDEBUG((LOG_INFO, "pppInput[%d]: drop VJ Comp in %d:%s\n", pd, nb->len, nb->payload));
+#endif /* VJ_SUPPORT > 0 */
+ break;
+ case PPP_VJC_UNCOMP: /* VJ uncompressed TCP */
+#if VJ_SUPPORT > 0
+ PPPDEBUG((LOG_INFO, "pppInput[%d]: vj_un in pbuf len=%d\n", pd, nb->len));
+ /*
+ * Process the TCP/IP header for VJ header compression and then pass
+ * the packet to IP.
+ */
+ if (vj_uncompress_uncomp(nb, &pppControl[pd].vjComp) >= 0) {
+ pppControl[pd].netif.input(nb, &pppControl[pd].netif);
+ return;
+ }
+ /* Something's wrong so drop it. */
+ PPPDEBUG((LOG_WARNING, "pppInput[%d]: Dropping VJ uncompressed\n", pd));
+#else
+ /* No handler for this protocol so drop the packet. */
+ PPPDEBUG((LOG_INFO,
+ "pppInput[%d]: drop VJ UnComp in %d:.*H\n",
+ pd, nb->len, LWIP_MIN(nb->len * 2, 40), nb->payload));
+#endif /* VJ_SUPPORT > 0 */
+ break;
+ case PPP_IP: /* Internet Protocol */
+ PPPDEBUG((LOG_INFO, "pppInput[%d]: ip in pbuf len=%d\n", pd, nb->len));
+ pppControl[pd].netif.input(nb, &pppControl[pd].netif);
+ return;
+ default:
+ {
+ struct protent *protp;
+ int i;
+
+ /*
+ * Upcall the proper protocol input routine.
+ */
+ for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) {
+ if (protp->protocol == protocol && protp->enabled_flag) {
+ PPPDEBUG((LOG_INFO, "pppInput[%d]: %s len=%d\n", pd, protp->name, nb->len));
+ nb = pppSingleBuf(nb);
+ (*protp->input)(pd, nb->payload, nb->len);
+ goto out;
+ }
+ }
+
+ /* No handler for this protocol so reject the packet. */
+ PPPDEBUG((LOG_INFO, "pppInput[%d]: rejecting unsupported proto 0x%04X len=%d\n", pd, protocol, nb->len));
+ pbuf_header(nb, sizeof(protocol));
+#if BYTE_ORDER == LITTLE_ENDIAN
+ protocol = htons(protocol);
+ memcpy(nb->payload, &protocol, sizeof(protocol));
+#endif
+ lcp_sprotrej(pd, nb->payload, nb->len);
+ }
+ break;
+ }
+
+drop:
+#if LINK_STATS
+ lwip_stats.link.drop++;
+#endif
+
+out:
+ pbuf_free(nb);
+ return;
+}
+
+
+/*
+ * Drop the input packet.
+ */
+static void pppDrop(PPPControl *pc)
+{
+ if (pc->inHead != NULL) {
+#if 0
+ PPPDEBUG((LOG_INFO, "pppDrop: %d:%.*H\n", pc->inHead->len, min(60, pc->inHead->len * 2), pc->inHead->payload));
+#endif
+ PPPDEBUG((LOG_INFO, "pppDrop: pbuf len=%d\n", pc->inHead->len));
+ if (pc->inTail && (pc->inTail != pc->inHead))
+ pbuf_free(pc->inTail);
+ pbuf_free(pc->inHead);
+ pc->inHead = NULL;
+ pc->inTail = NULL;
+ }
+#if VJ_SUPPORT > 0
+ vj_uncompress_err(&pc->vjComp);
+#endif
+
+#if LINK_STATS
+ lwip_stats.link.drop++;
+#endif /* LINK_STATS */
+}
+
+
+/*
+ * Process a received octet string.
+ */
+static void pppInProc(int pd, u_char *s, int l)
+{
+ PPPControl *pc = &pppControl[pd];
+ struct pbuf *nextNBuf;
+ u_char curChar;
+
+ PPPDEBUG((LOG_DEBUG, "pppInProc[%d]: got %d bytes\n", pd, l));
+ while (l-- > 0) {
+ curChar = *s++;
+
+ /* Handle special characters. */
+ if (ESCAPE_P(pc->inACCM, curChar)) {
+ /* Check for escape sequences. */
+ /* XXX Note that this does not handle an escaped 0x5d character which
+ * would appear as an escape character. Since this is an ASCII ']'
+ * and there is no reason that I know of to escape it, I won't complicate
+ * the code to handle this case. GLL */
+ if (curChar == PPP_ESCAPE)
+ pc->inEscaped = 1;
+ /* Check for the flag character. */
+ else if (curChar == PPP_FLAG) {
+ /* If this is just an extra flag character, ignore it. */
+ if (pc->inState <= PDADDRESS)
+ ;
+ /* If we haven't received the packet header, drop what has come in. */
+ else if (pc->inState < PDDATA) {
+ PPPDEBUG((LOG_WARNING,
+ "pppInProc[%d]: Dropping incomplete packet %d\n",
+ pd, pc->inState));
+#if LINK_STATS
+ lwip_stats.link.lenerr++;
+#endif
+ pppDrop(pc);
+ }
+ /* If the fcs is invalid, drop the packet. */
+ else if (pc->inFCS != PPP_GOODFCS) {
+ PPPDEBUG((LOG_INFO,
+ "pppInProc[%d]: Dropping bad fcs 0x%04X proto=0x%04X\n",
+ pd, pc->inFCS, pc->inProtocol));
+#if LINK_STATS
+ lwip_stats.link.chkerr++;
+#endif
+ pppDrop(pc);
+ }
+ /* Otherwise it's a good packet so pass it on. */
+ else {
+
+ /* Trim off the checksum. */
+ if(pc->inTail->len >= 2) {
+ pc->inTail->len -= 2;
+
+ pc->inTail->tot_len = pc->inTail->len;
+ if (pc->inTail != pc->inHead) {
+ pbuf_cat(pc->inHead, pc->inTail);
+ }
+ } else {
+ pc->inTail->tot_len = pc->inTail->len;
+ if (pc->inTail != pc->inHead) {
+ pbuf_cat(pc->inHead, pc->inTail);
+ }
+
+ pbuf_realloc(pc->inHead, pc->inHead->tot_len - 2);
+ }
+
+ /* Dispatch the packet thereby consuming it. */
+ if(tcpip_callback(pppInput, pc->inHead) != ERR_OK) {
+ PPPDEBUG((LOG_ERR,
+ "pppInProc[%d]: tcpip_callback() failed, dropping packet\n", pd));
+ pbuf_free(pc->inHead);
+#if LINK_STATS
+ lwip_stats.link.drop++;
+#endif
+ }
+ pc->inHead = NULL;
+ pc->inTail = NULL;
+ }
+
+ /* Prepare for a new packet. */
+ pc->inFCS = PPP_INITFCS;
+ pc->inState = PDADDRESS;
+ pc->inEscaped = 0;
+ }
+ /* Other characters are usually control characters that may have
+ * been inserted by the physical layer so here we just drop them. */
+ else {
+ PPPDEBUG((LOG_WARNING,
+ "pppInProc[%d]: Dropping ACCM char <%d>\n", pd, curChar));
+ }
+ }
+ /* Process other characters. */
+ else {
+ /* Unencode escaped characters. */
+ if (pc->inEscaped) {
+ pc->inEscaped = 0;
+ curChar ^= PPP_TRANS;
+ }
+
+ /* Process character relative to current state. */
+ switch(pc->inState) {
+ case PDIDLE: /* Idle state - waiting. */
+ /* Drop the character if it's not 0xff
+ * we would have processed a flag character above. */
+ if (curChar != PPP_ALLSTATIONS) {
+ break;
+ }
+
+ /* Fall through */
+ case PDSTART: /* Process start flag. */
+ /* Prepare for a new packet. */
+ pc->inFCS = PPP_INITFCS;
+
+ /* Fall through */
+ case PDADDRESS: /* Process address field. */
+ if (curChar == PPP_ALLSTATIONS) {
+ pc->inState = PDCONTROL;
+ break;
+ }
+ /* Else assume compressed address and control fields so
+ * fall through to get the protocol... */
+ case PDCONTROL: /* Process control field. */
+ /* If we don't get a valid control code, restart. */
+ if (curChar == PPP_UI) {
+ pc->inState = PDPROTOCOL1;
+ break;
+ }
+#if 0
+ else {
+ PPPDEBUG((LOG_WARNING,
+ "pppInProc[%d]: Invalid control <%d>\n", pd, curChar));
+ pc->inState = PDSTART;
+ }
+#endif
+ case PDPROTOCOL1: /* Process protocol field 1. */
+ /* If the lower bit is set, this is the end of the protocol
+ * field. */
+ if (curChar & 1) {
+ pc->inProtocol = curChar;
+ pc->inState = PDDATA;
+ }
+ else {
+ pc->inProtocol = (u_int)curChar << 8;
+ pc->inState = PDPROTOCOL2;
+ }
+ break;
+ case PDPROTOCOL2: /* Process protocol field 2. */
+ pc->inProtocol |= curChar;
+ pc->inState = PDDATA;
+ break;
+ case PDDATA: /* Process data byte. */
+ /* Make space to receive processed data. */
+ if (pc->inTail == NULL || pc->inTail->len == PBUF_POOL_BUFSIZE) {
+ if(pc->inTail) {
+ pc->inTail->tot_len = pc->inTail->len;
+ if (pc->inTail != pc->inHead) {
+ pbuf_cat(pc->inHead, pc->inTail);
+ }
+ }
+ /* If we haven't started a packet, we need a packet header. */
+ nextNBuf = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL);
+ if (nextNBuf == NULL) {
+ /* No free buffers. Drop the input packet and let the
+ * higher layers deal with it. Continue processing
+ * the received pbuf chain in case a new packet starts. */
+ PPPDEBUG((LOG_ERR, "pppInProc[%d]: NO FREE MBUFS!\n", pd));
+#if LINK_STATS
+ lwip_stats.link.memerr++;
+#endif /* LINK_STATS */
+ pppDrop(pc);
+ pc->inState = PDSTART; /* Wait for flag sequence. */
+ break;
+ }
+ if (pc->inHead == NULL) {
+ struct pppInputHeader *pih = nextNBuf->payload;
+
+ pih->unit = pd;
+ pih->proto = pc->inProtocol;
+
+ nextNBuf->len += sizeof(*pih);
+
+ pc->inHead = nextNBuf;
+ }
+ pc->inTail = nextNBuf;
+ }
+ /* Load character into buffer. */
+ ((u_char*)pc->inTail->payload)[pc->inTail->len++] = curChar;
+ break;
+ }
+
+ /* update the frame check sequence number. */
+ pc->inFCS = PPP_FCS(pc->inFCS, curChar);
+ }
+ }
+ avRandomize();
+}
+
+#endif /* PPP_SUPPORT */
--- /dev/null
+/*****************************************************************************
+* ppp.h - Network Point to Point Protocol header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher <marc@mbsi.ca>
+* Ported to lwIP.
+* 97-11-05 Guy Lancaster <glanca@gesn.com>, Global Election Systems Inc.
+* Original derived from BSD codes.
+*****************************************************************************/
+
+#ifndef PPP_H
+#define PPP_H
+
+#include "lwip/opt.h"
+
+#if PPP_SUPPORT > 0
+#include "lwip/sio.h"
+#include "lwip/api.h"
+#include "lwip/sockets.h"
+#include "lwip/stats.h"
+#include "lwip/mem.h"
+#include "lwip/tcpip.h"
+#include "lwip/netif.h"
+
+/*
+ * pppd.h - PPP daemon global declarations.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University. The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ */
+/*
+ * ppp_defs.h - PPP definitions.
+ *
+ * Copyright (c) 1994 The Australian National University.
+ * All rights reserved.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, provided that the above copyright
+ * notice appears in all copies. This software is provided without any
+ * warranty, express or implied. The Australian National University
+ * makes no representations about the suitability of this software for
+ * any purpose.
+ *
+ * IN NO EVENT SHALL THE AUSTRALIAN NATIONAL UNIVERSITY BE LIABLE TO ANY
+ * PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES
+ * ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF
+ * THE AUSTRALIAN NATIONAL UNIVERSITY HAVE BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * THE AUSTRALIAN NATIONAL UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS
+ * ON AN "AS IS" BASIS, AND THE AUSTRALIAN NATIONAL UNIVERSITY HAS NO
+ * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS,
+ * OR MODIFICATIONS.
+ */
+
+#define TIMEOUT(f, a, t) sys_untimeout((f), (a)), sys_timeout((t)*1000, (f), (a))
+#define UNTIMEOUT(f, a) sys_untimeout((f), (a))
+
+
+# ifndef __u_char_defined
+
+/* Type definitions for BSD code. */
+typedef unsigned long u_long;
+typedef unsigned int u_int;
+typedef unsigned short u_short;
+typedef unsigned char u_char;
+
+#endif
+
+/*
+ * Constants and structures defined by the internet system,
+ * Per RFC 790, September 1981, and numerous additions.
+ */
+
+/*
+ * The basic PPP frame.
+ */
+#define PPP_HDRLEN 4 /* octets for standard ppp header */
+#define PPP_FCSLEN 2 /* octets for FCS */
+
+
+/*
+ * Significant octet values.
+ */
+#define PPP_ALLSTATIONS 0xff /* All-Stations broadcast address */
+#define PPP_UI 0x03 /* Unnumbered Information */
+#define PPP_FLAG 0x7e /* Flag Sequence */
+#define PPP_ESCAPE 0x7d /* Asynchronous Control Escape */
+#define PPP_TRANS 0x20 /* Asynchronous transparency modifier */
+
+/*
+ * Protocol field values.
+ */
+#define PPP_IP 0x21 /* Internet Protocol */
+#define PPP_AT 0x29 /* AppleTalk Protocol */
+#define PPP_VJC_COMP 0x2d /* VJ compressed TCP */
+#define PPP_VJC_UNCOMP 0x2f /* VJ uncompressed TCP */
+#define PPP_COMP 0xfd /* compressed packet */
+#define PPP_IPCP 0x8021 /* IP Control Protocol */
+#define PPP_ATCP 0x8029 /* AppleTalk Control Protocol */
+#define PPP_CCP 0x80fd /* Compression Control Protocol */
+#define PPP_LCP 0xc021 /* Link Control Protocol */
+#define PPP_PAP 0xc023 /* Password Authentication Protocol */
+#define PPP_LQR 0xc025 /* Link Quality Report protocol */
+#define PPP_CHAP 0xc223 /* Cryptographic Handshake Auth. Protocol */
+#define PPP_CBCP 0xc029 /* Callback Control Protocol */
+
+/*
+ * Values for FCS calculations.
+ */
+#define PPP_INITFCS 0xffff /* Initial FCS value */
+#define PPP_GOODFCS 0xf0b8 /* Good final FCS value */
+#define PPP_FCS(fcs, c) (((fcs) >> 8) ^ fcstab[((fcs) ^ (c)) & 0xff])
+
+/*
+ * Extended asyncmap - allows any character to be escaped.
+ */
+typedef u_char ext_accm[32];
+
+/*
+ * What to do with network protocol (NP) packets.
+ */
+enum NPmode {
+ NPMODE_PASS, /* pass the packet through */
+ NPMODE_DROP, /* silently drop the packet */
+ NPMODE_ERROR, /* return an error */
+ NPMODE_QUEUE /* save it up for later. */
+};
+
+/*
+ * Inline versions of get/put char/short/long.
+ * Pointer is advanced; we assume that both arguments
+ * are lvalues and will already be in registers.
+ * cp MUST be u_char *.
+ */
+#define GETCHAR(c, cp) { \
+ (c) = *(cp)++; \
+}
+#define PUTCHAR(c, cp) { \
+ *(cp)++ = (u_char) (c); \
+}
+
+
+#define GETSHORT(s, cp) { \
+ (s) = *(cp)++ << 8; \
+ (s) |= *(cp)++; \
+}
+#define PUTSHORT(s, cp) { \
+ *(cp)++ = (u_char) ((s) >> 8); \
+ *(cp)++ = (u_char) (s); \
+}
+
+#define GETLONG(l, cp) { \
+ (l) = *(cp)++ << 8; \
+ (l) |= *(cp)++; (l) <<= 8; \
+ (l) |= *(cp)++; (l) <<= 8; \
+ (l) |= *(cp)++; \
+}
+#define PUTLONG(l, cp) { \
+ *(cp)++ = (u_char) ((l) >> 24); \
+ *(cp)++ = (u_char) ((l) >> 16); \
+ *(cp)++ = (u_char) ((l) >> 8); \
+ *(cp)++ = (u_char) (l); \
+}
+
+
+#define INCPTR(n, cp) ((cp) += (n))
+#define DECPTR(n, cp) ((cp) -= (n))
+
+#define BCMP(s0, s1, l) memcmp((u_char *)(s0), (u_char *)(s1), (l))
+#define BCOPY(s, d, l) memcpy((d), (s), (l))
+#define BZERO(s, n) memset(s, 0, n)
+#if PPP_DEBUG
+#define PRINTMSG(m, l) { m[l] = '\0'; ppp_trace(LOG_INFO, "Remote message: %s\n", m); }
+#else
+#define PRINTMSG(m, l)
+#endif
+
+/*
+ * MAKEHEADER - Add PPP Header fields to a packet.
+ */
+#define MAKEHEADER(p, t) { \
+ PUTCHAR(PPP_ALLSTATIONS, p); \
+ PUTCHAR(PPP_UI, p); \
+ PUTSHORT(t, p); }
+
+/*************************
+*** PUBLIC DEFINITIONS ***
+*************************/
+
+/* Error codes. */
+#define PPPERR_NONE 0 /* No error. */
+#define PPPERR_PARAM -1 /* Invalid parameter. */
+#define PPPERR_OPEN -2 /* Unable to open PPP session. */
+#define PPPERR_DEVICE -3 /* Invalid I/O device for PPP. */
+#define PPPERR_ALLOC -4 /* Unable to allocate resources. */
+#define PPPERR_USER -5 /* User interrupt. */
+#define PPPERR_CONNECT -6 /* Connection lost. */
+#define PPPERR_AUTHFAIL -7 /* Failed authentication challenge. */
+#define PPPERR_PROTOCOL -8 /* Failed to meet protocol. */
+
+/*
+ * PPP IOCTL commands.
+ */
+/*
+ * Get the up status - 0 for down, non-zero for up. The argument must
+ * point to an int.
+ */
+#define PPPCTLG_UPSTATUS 100 /* Get the up status - 0 down else up */
+#define PPPCTLS_ERRCODE 101 /* Set the error code */
+#define PPPCTLG_ERRCODE 102 /* Get the error code */
+#define PPPCTLG_FD 103 /* Get the fd associated with the ppp */
+
+/************************
+*** PUBLIC DATA TYPES ***
+************************/
+
+/*
+ * The following struct gives the addresses of procedures to call
+ * for a particular protocol.
+ */
+struct protent {
+ u_short protocol; /* PPP protocol number */
+ /* Initialization procedure */
+ void (*init) (int unit);
+ /* Process a received packet */
+ void (*input) (int unit, u_char *pkt, int len);
+ /* Process a received protocol-reject */
+ void (*protrej) (int unit);
+ /* Lower layer has come up */
+ void (*lowerup) (int unit);
+ /* Lower layer has gone down */
+ void (*lowerdown) (int unit);
+ /* Open the protocol */
+ void (*open) (int unit);
+ /* Close the protocol */
+ void (*close) (int unit, char *reason);
+#if 0
+ /* Print a packet in readable form */
+ int (*printpkt) (u_char *pkt, int len,
+ void (*printer) (void *, char *, ...),
+ void *arg);
+ /* Process a received data packet */
+ void (*datainput) (int unit, u_char *pkt, int len);
+#endif
+ int enabled_flag; /* 0 iff protocol is disabled */
+ char *name; /* Text name of protocol */
+#if 0
+ /* Check requested options, assign defaults */
+ void (*check_options) (u_long);
+ /* Configure interface for demand-dial */
+ int (*demand_conf) (int unit);
+ /* Say whether to bring up link for this pkt */
+ int (*active_pkt) (u_char *pkt, int len);
+#endif
+};
+
+/*
+ * The following structure records the time in seconds since
+ * the last NP packet was sent or received.
+ */
+struct ppp_idle {
+ u_short xmit_idle; /* seconds since last NP packet sent */
+ u_short recv_idle; /* seconds since last NP packet received */
+};
+
+struct ppp_settings {
+
+ u_int disable_defaultip : 1; /* Don't use hostname for default IP addrs */
+ u_int auth_required : 1; /* Peer is required to authenticate */
+ u_int explicit_remote : 1; /* remote_name specified with remotename opt */
+ u_int refuse_pap : 1; /* Don't wanna auth. ourselves with PAP */
+ u_int refuse_chap : 1; /* Don't wanna auth. ourselves with CHAP */
+ u_int usehostname : 1; /* Use hostname for our_name */
+ u_int usepeerdns : 1; /* Ask peer for DNS adds */
+
+ u_short idle_time_limit; /* Shut down link if idle for this long */
+ int maxconnect; /* Maximum connect time (seconds) */
+
+ char user[MAXNAMELEN + 1];/* Username for PAP */
+ char passwd[MAXSECRETLEN + 1]; /* Password for PAP, secret for CHAP */
+ char our_name[MAXNAMELEN + 1]; /* Our name for authentication purposes */
+ char remote_name[MAXNAMELEN + 1]; /* Peer's name for authentication */
+};
+
+struct ppp_addrs {
+ struct ip_addr our_ipaddr, his_ipaddr, netmask, dns1, dns2;
+};
+
+/*****************************
+*** PUBLIC DATA STRUCTURES ***
+*****************************/
+/* Buffers for outgoing packets. */
+extern u_char outpacket_buf[NUM_PPP][PPP_MRU+PPP_HDRLEN];
+
+extern struct ppp_settings ppp_settings;
+
+extern struct protent *ppp_protocols[];/* Table of pointers to supported protocols */
+
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+
+/* Initialize the PPP subsystem. */
+void pppInit(void);
+
+/* Warning: Using PPPAUTHTYPE_ANY might have security consequences.
+ * RFC 1994 says:
+ *
+ * In practice, within or associated with each PPP server, there is a
+ * database which associates "user" names with authentication
+ * information ("secrets"). It is not anticipated that a particular
+ * named user would be authenticated by multiple methods. This would
+ * make the user vulnerable to attacks which negotiate the least secure
+ * method from among a set (such as PAP rather than CHAP). If the same
+ * secret was used, PAP would reveal the secret to be used later with
+ * CHAP.
+ *
+ * Instead, for each user name there should be an indication of exactly
+ * one method used to authenticate that user name. If a user needs to
+ * make use of different authentication methods under different
+ * circumstances, then distinct user names SHOULD be employed, each of
+ * which identifies exactly one authentication method.
+ *
+ */
+enum pppAuthType {
+ PPPAUTHTYPE_NONE,
+ PPPAUTHTYPE_ANY,
+ PPPAUTHTYPE_PAP,
+ PPPAUTHTYPE_CHAP
+};
+
+void pppSetAuth(enum pppAuthType authType, const char *user, const char *passwd);
+
+/*
+ * Open a new PPP connection using the given I/O device.
+ * This initializes the PPP control block but does not
+ * attempt to negotiate the LCP session.
+ * Return a new PPP connection descriptor on success or
+ * an error code (negative) on failure.
+ */
+int pppOpen(sio_fd_t fd, void (*linkStatusCB)(void *ctx, int errCode, void *arg), void *linkStatusCtx);
+
+/*
+ * Close a PPP connection and release the descriptor.
+ * Any outstanding packets in the queues are dropped.
+ * Return 0 on success, an error code on failure.
+ */
+int pppClose(int pd);
+
+/*
+ * Indicate to the PPP process that the line has disconnected.
+ */
+void pppSigHUP(int pd);
+
+/*
+ * Get and set parameters for the given connection.
+ * Return 0 on success, an error code on failure.
+ */
+int pppIOCtl(int pd, int cmd, void *arg);
+
+/*
+ * Return the Maximum Transmission Unit for the given PPP connection.
+ */
+u_int pppMTU(int pd);
+
+/*
+ * Write n characters to a ppp link.
+ * RETURN: >= 0 Number of characters written
+ * -1 Failed to write to device
+ */
+int pppWrite(int pd, const u_char *s, int n);
+
+void pppMainWakeup(int pd);
+
+/* Configure i/f transmit parameters */
+void ppp_send_config (int, int, u32_t, int, int);
+/* Set extended transmit ACCM */
+void ppp_set_xaccm (int, ext_accm *);
+/* Configure i/f receive parameters */
+void ppp_recv_config (int, int, u32_t, int, int);
+/* Find out how long link has been idle */
+int get_idle_time (int, struct ppp_idle *);
+
+/* Configure VJ TCP header compression */
+int sifvjcomp (int, int, int, int);
+/* Configure i/f down (for IP) */
+int sifup (int);
+/* Set mode for handling packets for proto */
+int sifnpmode (int u, int proto, enum NPmode mode);
+/* Configure i/f down (for IP) */
+int sifdown (int);
+/* Configure IP addresses for i/f */
+int sifaddr (int, u32_t, u32_t, u32_t, u32_t, u32_t);
+/* Reset i/f IP addresses */
+int cifaddr (int, u32_t, u32_t);
+/* Create default route through i/f */
+int sifdefaultroute (int, u32_t, u32_t);
+/* Delete default route through i/f */
+int cifdefaultroute (int, u32_t, u32_t);
+
+/* Get appropriate netmask for address */
+u32_t GetMask (u32_t);
+
+#endif /* PPP_SUPPORT */
+
+#endif /* PPP_H */
--- /dev/null
+/*****************************************************************************
+* pppdebug.h - System debugging utilities.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1998 Global Election Systems Inc.
+* portions Copyright (c) 2001 by Cognizant Pty Ltd.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY (please don't use tabs!)
+*
+* 03-01-01 Marc Boucher <marc@mbsi.ca>
+* Ported to lwIP.
+* 98-07-29 Guy Lancaster <lancasterg@acm.org>, Global Election Systems Inc.
+* Original.
+*
+*****************************************************************************
+*/
+#ifndef PPPDEBUG_H
+#define PPPDEBUG_H
+
+/************************
+*** PUBLIC DATA TYPES ***
+************************/
+/* Trace levels. */
+typedef enum {
+ LOG_CRITICAL = 0,
+ LOG_ERR = 1,
+ LOG_NOTICE = 2,
+ LOG_WARNING = 3,
+ LOG_INFO = 5,
+ LOG_DETAIL = 6,
+ LOG_DEBUG = 7
+} LogCodes;
+
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+/*
+ * ppp_trace - a form of printf to send tracing information to stderr
+ */
+void ppp_trace(int level, const char *format,...);
+
+#if PPP_DEBUG > 0
+
+#define AUTHDEBUG(a) ppp_trace a
+#define IPCPDEBUG(a) ppp_trace a
+#define UPAPDEBUG(a) ppp_trace a
+#define LCPDEBUG(a) ppp_trace a
+#define FSMDEBUG(a) ppp_trace a
+#define CHAPDEBUG(a) ppp_trace a
+#define PPPDEBUG(a) ppp_trace a
+
+#define TRACELCP 1
+
+#else
+
+#define AUTHDEBUG(a)
+#define IPCPDEBUG(a)
+#define UPAPDEBUG(a)
+#define LCPDEBUG(a)
+#define FSMDEBUG(a)
+#define CHAPDEBUG(a)
+
+#define PPPDEBUG(a)
+
+#define TRACELCP 0
+
+#endif
+
+#endif /* PPPDEBUG_H */
--- /dev/null
+/*****************************************************************************
+* randm.c - Random number generator program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* Copyright (c) 1998 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher <marc@mbsi.ca>
+* Ported to lwIP.
+* 98-06-03 Guy Lancaster <lancasterg@acm.org>, Global Election Systems Inc.
+* Extracted from avos.
+*****************************************************************************/
+
+#include "ppp.h"
+#if PPP_SUPPORT > 0
+#include "md5.h"
+#include "randm.h"
+
+#include "pppdebug.h"
+
+
+#if MD5_SUPPORT>0 /* this module depends on MD5 */
+#define RANDPOOLSZ 16 /* Bytes stored in the pool of randomness. */
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+static char randPool[RANDPOOLSZ]; /* Pool of randomness. */
+static long randCount = 0; /* Pseudo-random incrementer */
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/*
+ * Initialize the random number generator.
+ *
+ * Since this is to be called on power up, we don't have much
+ * system randomess to work with. Here all we use is the
+ * real-time clock. We'll accumulate more randomness as soon
+ * as things start happening.
+ */
+void avRandomInit()
+{
+ avChurnRand(NULL, 0);
+}
+
+/*
+ * Churn the randomness pool on a random event. Call this early and often
+ * on random and semi-random system events to build randomness in time for
+ * usage. For randomly timed events, pass a null pointer and a zero length
+ * and this will use the system timer and other sources to add randomness.
+ * If new random data is available, pass a pointer to that and it will be
+ * included.
+ *
+ * Ref: Applied Cryptography 2nd Ed. by Bruce Schneier p. 427
+ */
+void avChurnRand(char *randData, u32_t randLen)
+{
+ MD5_CTX md5;
+
+/* ppp_trace(LOG_INFO, "churnRand: %u@%P\n", randLen, randData); */
+ MD5Init(&md5);
+ MD5Update(&md5, (u_char *)randPool, sizeof(randPool));
+ if (randData)
+ MD5Update(&md5, (u_char *)randData, randLen);
+ else {
+ struct {
+ /* INCLUDE fields for any system sources of randomness */
+ char foobar;
+ } sysData;
+
+ /* Load sysData fields here. */
+ ;
+ MD5Update(&md5, (u_char *)&sysData, sizeof(sysData));
+ }
+ MD5Final((u_char *)randPool, &md5);
+/* ppp_trace(LOG_INFO, "churnRand: -> 0\n"); */
+}
+
+/*
+ * Use the random pool to generate random data. This degrades to pseudo
+ * random when used faster than randomness is supplied using churnRand().
+ * Note: It's important that there be sufficient randomness in randPool
+ * before this is called for otherwise the range of the result may be
+ * narrow enough to make a search feasible.
+ *
+ * Ref: Applied Cryptography 2nd Ed. by Bruce Schneier p. 427
+ *
+ * XXX Why does he not just call churnRand() for each block? Probably
+ * so that you don't ever publish the seed which could possibly help
+ * predict future values.
+ * XXX Why don't we preserve md5 between blocks and just update it with
+ * randCount each time? Probably there is a weakness but I wish that
+ * it was documented.
+ */
+void avGenRand(char *buf, u32_t bufLen)
+{
+ MD5_CTX md5;
+ u_char tmp[16];
+ u32_t n;
+
+ while (bufLen > 0) {
+ n = LWIP_MIN(bufLen, RANDPOOLSZ);
+ MD5Init(&md5);
+ MD5Update(&md5, (u_char *)randPool, sizeof(randPool));
+ MD5Update(&md5, (u_char *)&randCount, sizeof(randCount));
+ MD5Final(tmp, &md5);
+ randCount++;
+ memcpy(buf, tmp, n);
+ buf += n;
+ bufLen -= n;
+ }
+}
+
+/*
+ * Return a new random number.
+ */
+u32_t avRandom()
+{
+ u32_t newRand;
+
+ avGenRand((char *)&newRand, sizeof(newRand));
+
+ return newRand;
+}
+
+#else /* MD5_SUPPORT */
+
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+static int avRandomized = 0; /* Set when truely randomized. */
+static u32_t avRandomSeed = 0; /* Seed used for random number generation. */
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/*
+ * Initialize the random number generator.
+ *
+ * Here we attempt to compute a random number seed but even if
+ * it isn't random, we'll randomize it later.
+ *
+ * The current method uses the fields from the real time clock,
+ * the idle process counter, the millisecond counter, and the
+ * hardware timer tick counter. When this is invoked
+ * in startup(), then the idle counter and timer values may
+ * repeat after each boot and the real time clock may not be
+ * operational. Thus we call it again on the first random
+ * event.
+ */
+void avRandomInit()
+{
+#if 0
+ /* Get a pointer into the last 4 bytes of clockBuf. */
+ u32_t *lptr1 = (u32_t *)((char *)&clockBuf[3]);
+
+ /*
+ * Initialize our seed using the real-time clock, the idle
+ * counter, the millisecond timer, and the hardware timer
+ * tick counter. The real-time clock and the hardware
+ * tick counter are the best sources of randomness but
+ * since the tick counter is only 16 bit (and truncated
+ * at that), the idle counter and millisecond timer
+ * (which may be small values) are added to help
+ * randomize the lower 16 bits of the seed.
+ */
+ readClk();
+ avRandomSeed += *(u32_t *)clockBuf + *lptr1 + OSIdleCtr
+ + ppp_mtime() + ((u32_t)TM1 << 16) + TM1;
+#else
+ avRandomSeed += sys_jiffies(); /* XXX */
+#endif
+
+ /* Initialize the Borland random number generator. */
+ srand((unsigned)avRandomSeed);
+}
+
+/*
+ * Randomize our random seed value. Here we use the fact that
+ * this function is called at *truely random* times by the polling
+ * and network functions. Here we only get 16 bits of new random
+ * value but we use the previous value to randomize the other 16
+ * bits.
+ */
+void avRandomize(void)
+{
+ static u32_t last_jiffies;
+
+ if (!avRandomized) {
+ avRandomized = !0;
+ avRandomInit();
+ /* The initialization function also updates the seed. */
+ } else {
+/* avRandomSeed += (avRandomSeed << 16) + TM1; */
+ avRandomSeed += (sys_jiffies() - last_jiffies); /* XXX */
+ }
+ last_jiffies = sys_jiffies();
+}
+
+/*
+ * Return a new random number.
+ * Here we use the Borland rand() function to supply a pseudo random
+ * number which we make truely random by combining it with our own
+ * seed which is randomized by truely random events.
+ * Thus the numbers will be truely random unless there have been no
+ * operator or network events in which case it will be pseudo random
+ * seeded by the real time clock.
+ */
+u32_t avRandom()
+{
+ return ((((u32_t)rand() << 16) + rand()) + avRandomSeed);
+}
+
+
+
+#endif /* MD5_SUPPORT */
+#endif /* PPP_SUPPORT */
+
--- /dev/null
+/*****************************************************************************
+* randm.h - Random number generator header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* Copyright (c) 1998 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher <marc@mbsi.ca>
+* Ported to lwIP.
+* 98-05-29 Guy Lancaster <glanca@gesn.com>, Global Election Systems Inc.
+* Extracted from avos.
+*****************************************************************************/
+
+#ifndef RANDM_H
+#define RANDM_H
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+/*
+ * Initialize the random number generator.
+ */
+void avRandomInit(void);
+
+/*
+ * Churn the randomness pool on a random event. Call this early and often
+ * on random and semi-random system events to build randomness in time for
+ * usage. For randomly timed events, pass a null pointer and a zero length
+ * and this will use the system timer and other sources to add randomness.
+ * If new random data is available, pass a pointer to that and it will be
+ * included.
+ */
+void avChurnRand(char *randData, u32_t randLen);
+
+/*
+ * Randomize our random seed value. To be called for truely random events
+ * such as user operations and network traffic.
+ */
+#if MD5_SUPPORT
+#define avRandomize() avChurnRand(NULL, 0)
+#else
+void avRandomize(void);
+#endif
+
+/*
+ * Use the random pool to generate random data. This degrades to pseudo
+ * random when used faster than randomness is supplied using churnRand().
+ * Thus it's important to make sure that the results of this are not
+ * published directly because one could predict the next result to at
+ * least some degree. Also, it's important to get a good seed before
+ * the first use.
+ */
+void avGenRand(char *buf, u32_t bufLen);
+
+/*
+ * Return a new random number.
+ */
+u32_t avRandom(void);
+
+
+#endif /* RANDM_H */
--- /dev/null
+/*
+ * Routines to compress and uncompess tcp packets (for transmission
+ * over low speed serial lines.
+ *
+ * Copyright (c) 1989 Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by the University of California, Berkeley. The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Van Jacobson (van@helios.ee.lbl.gov), Dec 31, 1989:
+ * - Initial distribution.
+ *
+ * Modified June 1993 by Paul Mackerras, paulus@cs.anu.edu.au,
+ * so that the entire packet being decompressed doesn't have
+ * to be in contiguous memory (just the compressed header).
+ *
+ * Modified March 1998 by Guy Lancaster, glanca@gesn.com,
+ * for a 16 bit processor.
+ */
+
+#include <string.h>
+
+#include "ppp.h"
+#include "vj.h"
+#include "pppdebug.h"
+
+#if VJ_SUPPORT > 0
+
+#if LINK_STATS
+#define INCR(counter) ++comp->stats.counter
+#else
+#define INCR(counter)
+#endif
+
+#if defined(NO_CHAR_BITFIELDS)
+#define getip_hl(base) ((base).ip_hl_v&0xf)
+#define getth_off(base) (((base).th_x2_off&0xf0)>>4)
+#else
+#define getip_hl(base) ((base).ip_hl)
+#define getth_off(base) ((base).th_off)
+#endif
+
+void vj_compress_init(struct vjcompress *comp)
+{
+ register u_int i;
+ register struct cstate *tstate = comp->tstate;
+
+#if MAX_SLOTS == 0
+ memset((char *)comp, 0, sizeof(*comp));
+#endif
+ comp->maxSlotIndex = MAX_SLOTS - 1;
+ comp->compressSlot = 0; /* Disable slot ID compression by default. */
+ for (i = MAX_SLOTS - 1; i > 0; --i) {
+ tstate[i].cs_id = i;
+ tstate[i].cs_next = &tstate[i - 1];
+ }
+ tstate[0].cs_next = &tstate[MAX_SLOTS - 1];
+ tstate[0].cs_id = 0;
+ comp->last_cs = &tstate[0];
+ comp->last_recv = 255;
+ comp->last_xmit = 255;
+ comp->flags = VJF_TOSS;
+}
+
+
+/* ENCODE encodes a number that is known to be non-zero. ENCODEZ
+ * checks for zero (since zero has to be encoded in the long, 3 byte
+ * form).
+ */
+#define ENCODE(n) { \
+ if ((u_short)(n) >= 256) { \
+ *cp++ = 0; \
+ cp[1] = (n); \
+ cp[0] = (n) >> 8; \
+ cp += 2; \
+ } else { \
+ *cp++ = (n); \
+ } \
+}
+#define ENCODEZ(n) { \
+ if ((u_short)(n) >= 256 || (u_short)(n) == 0) { \
+ *cp++ = 0; \
+ cp[1] = (n); \
+ cp[0] = (n) >> 8; \
+ cp += 2; \
+ } else { \
+ *cp++ = (n); \
+ } \
+}
+
+#define DECODEL(f) { \
+ if (*cp == 0) {\
+ u32_t tmp = ntohl(f) + ((cp[1] << 8) | cp[2]); \
+ (f) = htonl(tmp); \
+ cp += 3; \
+ } else { \
+ u32_t tmp = ntohl(f) + (u32_t)*cp++; \
+ (f) = htonl(tmp); \
+ } \
+}
+
+#define DECODES(f) { \
+ if (*cp == 0) {\
+ u_short tmp = ntohs(f) + (((u_short)cp[1] << 8) | cp[2]); \
+ (f) = htons(tmp); \
+ cp += 3; \
+ } else { \
+ u_short tmp = ntohs(f) + (u_short)*cp++; \
+ (f) = htons(tmp); \
+ } \
+}
+
+#define DECODEU(f) { \
+ if (*cp == 0) {\
+ (f) = htons(((u_short)cp[1] << 8) | cp[2]); \
+ cp += 3; \
+ } else { \
+ (f) = htons((u_short)*cp++); \
+ } \
+}
+
+/*
+ * vj_compress_tcp - Attempt to do Van Jacobsen header compression on a
+ * packet. This assumes that nb and comp are not null and that the first
+ * buffer of the chain contains a valid IP header.
+ * Return the VJ type code indicating whether or not the packet was
+ * compressed.
+ */
+u_int vj_compress_tcp(
+ struct vjcompress *comp,
+ struct pbuf *pb
+)
+{
+ register struct ip *ip = (struct ip *)pb->payload;
+ register struct cstate *cs = comp->last_cs->cs_next;
+ register u_short hlen = getip_hl(*ip);
+ register struct tcphdr *oth;
+ register struct tcphdr *th;
+ register u_short deltaS, deltaA;
+ register u_long deltaL;
+ register u_int changes = 0;
+ u_char new_seq[16];
+ register u_char *cp = new_seq;
+
+ /*
+ * Check that the packet is IP proto TCP.
+ */
+ if (ip->ip_p != IPPROTO_TCP)
+ return (TYPE_IP);
+
+ /*
+ * Bail if this is an IP fragment or if the TCP packet isn't
+ * `compressible' (i.e., ACK isn't set or some other control bit is
+ * set).
+ */
+ if ((ip->ip_off & htons(0x3fff)) || pb->tot_len < 40)
+ return (TYPE_IP);
+ th = (struct tcphdr *)&((long *)ip)[hlen];
+ if ((th->th_flags & (TCP_SYN|TCP_FIN|TCP_RST|TCP_ACK)) != TCP_ACK)
+ return (TYPE_IP);
+
+ /*
+ * Packet is compressible -- we're going to send either a
+ * COMPRESSED_TCP or UNCOMPRESSED_TCP packet. Either way we need
+ * to locate (or create) the connection state. Special case the
+ * most recently used connection since it's most likely to be used
+ * again & we don't have to do any reordering if it's used.
+ */
+ INCR(vjs_packets);
+ if (ip->ip_src.s_addr != cs->cs_ip.ip_src.s_addr
+ || ip->ip_dst.s_addr != cs->cs_ip.ip_dst.s_addr
+ || *(long *)th != ((long *)&cs->cs_ip)[getip_hl(cs->cs_ip)]) {
+ /*
+ * Wasn't the first -- search for it.
+ *
+ * States are kept in a circularly linked list with
+ * last_cs pointing to the end of the list. The
+ * list is kept in lru order by moving a state to the
+ * head of the list whenever it is referenced. Since
+ * the list is short and, empirically, the connection
+ * we want is almost always near the front, we locate
+ * states via linear search. If we don't find a state
+ * for the datagram, the oldest state is (re-)used.
+ */
+ register struct cstate *lcs;
+ register struct cstate *lastcs = comp->last_cs;
+
+ do {
+ lcs = cs; cs = cs->cs_next;
+ INCR(vjs_searches);
+ if (ip->ip_src.s_addr == cs->cs_ip.ip_src.s_addr
+ && ip->ip_dst.s_addr == cs->cs_ip.ip_dst.s_addr
+ && *(long *)th == ((long *)&cs->cs_ip)[getip_hl(cs->cs_ip)])
+ goto found;
+ } while (cs != lastcs);
+
+ /*
+ * Didn't find it -- re-use oldest cstate. Send an
+ * uncompressed packet that tells the other side what
+ * connection number we're using for this conversation.
+ * Note that since the state list is circular, the oldest
+ * state points to the newest and we only need to set
+ * last_cs to update the lru linkage.
+ */
+ INCR(vjs_misses);
+ comp->last_cs = lcs;
+ hlen += getth_off(*th);
+ hlen <<= 2;
+ /* Check that the IP/TCP headers are contained in the first buffer. */
+ if (hlen > pb->len)
+ return (TYPE_IP);
+ goto uncompressed;
+
+ found:
+ /*
+ * Found it -- move to the front on the connection list.
+ */
+ if (cs == lastcs)
+ comp->last_cs = lcs;
+ else {
+ lcs->cs_next = cs->cs_next;
+ cs->cs_next = lastcs->cs_next;
+ lastcs->cs_next = cs;
+ }
+ }
+
+ oth = (struct tcphdr *)&((long *)&cs->cs_ip)[hlen];
+ deltaS = hlen;
+ hlen += getth_off(*th);
+ hlen <<= 2;
+ /* Check that the IP/TCP headers are contained in the first buffer. */
+ if (hlen > pb->len) {
+ PPPDEBUG((LOG_INFO, "vj_compress_tcp: header len %d spans buffers\n",
+ hlen));
+ return (TYPE_IP);
+ }
+
+ /*
+ * Make sure that only what we expect to change changed. The first
+ * line of the `if' checks the IP protocol version, header length &
+ * type of service. The 2nd line checks the "Don't fragment" bit.
+ * The 3rd line checks the time-to-live and protocol (the protocol
+ * check is unnecessary but costless). The 4th line checks the TCP
+ * header length. The 5th line checks IP options, if any. The 6th
+ * line checks TCP options, if any. If any of these things are
+ * different between the previous & current datagram, we send the
+ * current datagram `uncompressed'.
+ */
+ if (((u_short *)ip)[0] != ((u_short *)&cs->cs_ip)[0]
+ || ((u_short *)ip)[3] != ((u_short *)&cs->cs_ip)[3]
+ || ((u_short *)ip)[4] != ((u_short *)&cs->cs_ip)[4]
+ || getth_off(*th) != getth_off(*oth)
+ || (deltaS > 5 && BCMP(ip + 1, &cs->cs_ip + 1, (deltaS - 5) << 2))
+ || (getth_off(*th) > 5 && BCMP(th + 1, oth + 1, (getth_off(*th) - 5) << 2)))
+ goto uncompressed;
+
+ /*
+ * Figure out which of the changing fields changed. The
+ * receiver expects changes in the order: urgent, window,
+ * ack, seq (the order minimizes the number of temporaries
+ * needed in this section of code).
+ */
+ if (th->th_flags & TCP_URG) {
+ deltaS = ntohs(th->th_urp);
+ ENCODEZ(deltaS);
+ changes |= NEW_U;
+ } else if (th->th_urp != oth->th_urp)
+ /* argh! URG not set but urp changed -- a sensible
+ * implementation should never do this but RFC793
+ * doesn't prohibit the change so we have to deal
+ * with it. */
+ goto uncompressed;
+
+ if ((deltaS = (u_short)(ntohs(th->th_win) - ntohs(oth->th_win))) != 0) {
+ ENCODE(deltaS);
+ changes |= NEW_W;
+ }
+
+ if ((deltaL = ntohl(th->th_ack) - ntohl(oth->th_ack)) != 0) {
+ if (deltaL > 0xffff)
+ goto uncompressed;
+ deltaA = (u_short)deltaL;
+ ENCODE(deltaA);
+ changes |= NEW_A;
+ }
+
+ if ((deltaL = ntohl(th->th_seq) - ntohl(oth->th_seq)) != 0) {
+ if (deltaL > 0xffff)
+ goto uncompressed;
+ deltaS = (u_short)deltaL;
+ ENCODE(deltaS);
+ changes |= NEW_S;
+ }
+
+ switch(changes) {
+
+ case 0:
+ /*
+ * Nothing changed. If this packet contains data and the
+ * last one didn't, this is probably a data packet following
+ * an ack (normal on an interactive connection) and we send
+ * it compressed. Otherwise it's probably a retransmit,
+ * retransmitted ack or window probe. Send it uncompressed
+ * in case the other side missed the compressed version.
+ */
+ if (ip->ip_len != cs->cs_ip.ip_len &&
+ ntohs(cs->cs_ip.ip_len) == hlen)
+ break;
+
+ /* (fall through) */
+
+ case SPECIAL_I:
+ case SPECIAL_D:
+ /*
+ * actual changes match one of our special case encodings --
+ * send packet uncompressed.
+ */
+ goto uncompressed;
+
+ case NEW_S|NEW_A:
+ if (deltaS == deltaA && deltaS == ntohs(cs->cs_ip.ip_len) - hlen) {
+ /* special case for echoed terminal traffic */
+ changes = SPECIAL_I;
+ cp = new_seq;
+ }
+ break;
+
+ case NEW_S:
+ if (deltaS == ntohs(cs->cs_ip.ip_len) - hlen) {
+ /* special case for data xfer */
+ changes = SPECIAL_D;
+ cp = new_seq;
+ }
+ break;
+ }
+
+ deltaS = (u_short)(ntohs(ip->ip_id) - ntohs(cs->cs_ip.ip_id));
+ if (deltaS != 1) {
+ ENCODEZ(deltaS);
+ changes |= NEW_I;
+ }
+ if (th->th_flags & TCP_PSH)
+ changes |= TCP_PUSH_BIT;
+ /*
+ * Grab the cksum before we overwrite it below. Then update our
+ * state with this packet's header.
+ */
+ deltaA = ntohs(th->th_sum);
+ BCOPY(ip, &cs->cs_ip, hlen);
+
+ /*
+ * We want to use the original packet as our compressed packet.
+ * (cp - new_seq) is the number of bytes we need for compressed
+ * sequence numbers. In addition we need one byte for the change
+ * mask, one for the connection id and two for the tcp checksum.
+ * So, (cp - new_seq) + 4 bytes of header are needed. hlen is how
+ * many bytes of the original packet to toss so subtract the two to
+ * get the new packet size.
+ */
+ deltaS = (u_short)(cp - new_seq);
+ if (!comp->compressSlot || comp->last_xmit != cs->cs_id) {
+ comp->last_xmit = cs->cs_id;
+ hlen -= deltaS + 4;
+ pbuf_header(pb, -hlen);
+ cp = (u_char *)pb->payload;
+ *cp++ = changes | NEW_C;
+ *cp++ = cs->cs_id;
+ } else {
+ hlen -= deltaS + 3;
+ pbuf_header(pb, -hlen);
+ cp = (u_char *)pb->payload;
+ *cp++ = changes;
+ }
+ *cp++ = deltaA >> 8;
+ *cp++ = deltaA;
+ BCOPY(new_seq, cp, deltaS);
+ INCR(vjs_compressed);
+ return (TYPE_COMPRESSED_TCP);
+
+ /*
+ * Update connection state cs & send uncompressed packet (that is,
+ * a regular ip/tcp packet but with the 'conversation id' we hope
+ * to use on future compressed packets in the protocol field).
+ */
+uncompressed:
+ BCOPY(ip, &cs->cs_ip, hlen);
+ ip->ip_p = cs->cs_id;
+ comp->last_xmit = cs->cs_id;
+ return (TYPE_UNCOMPRESSED_TCP);
+}
+
+/*
+ * Called when we may have missed a packet.
+ */
+void vj_uncompress_err(struct vjcompress *comp)
+{
+ comp->flags |= VJF_TOSS;
+ INCR(vjs_errorin);
+}
+
+/*
+ * "Uncompress" a packet of type TYPE_UNCOMPRESSED_TCP.
+ * Return 0 on success, -1 on failure.
+ */
+int vj_uncompress_uncomp(
+ struct pbuf *nb,
+ struct vjcompress *comp
+)
+{
+ register u_int hlen;
+ register struct cstate *cs;
+ register struct ip *ip;
+
+ ip = (struct ip *)nb->payload;
+ hlen = getip_hl(*ip) << 2;
+ if (ip->ip_p >= MAX_SLOTS
+ || hlen + sizeof(struct tcphdr) > nb->len
+ || (hlen += getth_off(*((struct tcphdr *)&((char *)ip)[hlen])) << 2)
+ > nb->len
+ || hlen > MAX_HDR) {
+ PPPDEBUG((LOG_INFO, "vj_uncompress_uncomp: bad cid=%d, hlen=%d buflen=%d\n",
+ ip->ip_p, hlen, nb->len));
+ comp->flags |= VJF_TOSS;
+ INCR(vjs_errorin);
+ return -1;
+ }
+ cs = &comp->rstate[comp->last_recv = ip->ip_p];
+ comp->flags &=~ VJF_TOSS;
+ ip->ip_p = IPPROTO_TCP;
+ BCOPY(ip, &cs->cs_ip, hlen);
+ cs->cs_hlen = hlen;
+ INCR(vjs_uncompressedin);
+ return 0;
+}
+
+/*
+ * Uncompress a packet of type TYPE_COMPRESSED_TCP.
+ * The packet is composed of a buffer chain and the first buffer
+ * must contain an accurate chain length.
+ * The first buffer must include the entire compressed TCP/IP header.
+ * This procedure replaces the compressed header with the uncompressed
+ * header and returns the length of the VJ header.
+ */
+int vj_uncompress_tcp(
+ struct pbuf **nb,
+ struct vjcompress *comp
+)
+{
+ u_char *cp;
+ struct tcphdr *th;
+ struct cstate *cs;
+ u_short *bp;
+ struct pbuf *n0 = *nb;
+ u32_t tmp;
+ u_int vjlen, hlen, changes;
+
+ INCR(vjs_compressedin);
+ cp = (u_char *)n0->payload;
+ changes = *cp++;
+ if (changes & NEW_C) {
+ /*
+ * Make sure the state index is in range, then grab the state.
+ * If we have a good state index, clear the 'discard' flag.
+ */
+ if (*cp >= MAX_SLOTS) {
+ PPPDEBUG((LOG_INFO, "vj_uncompress_tcp: bad cid=%d\n", *cp));
+ goto bad;
+ }
+
+ comp->flags &=~ VJF_TOSS;
+ comp->last_recv = *cp++;
+ } else {
+ /*
+ * this packet has an implicit state index. If we've
+ * had a line error since the last time we got an
+ * explicit state index, we have to toss the packet.
+ */
+ if (comp->flags & VJF_TOSS) {
+ PPPDEBUG((LOG_INFO, "vj_uncompress_tcp: tossing\n"));
+ INCR(vjs_tossed);
+ return (-1);
+ }
+ }
+ cs = &comp->rstate[comp->last_recv];
+ hlen = getip_hl(cs->cs_ip) << 2;
+ th = (struct tcphdr *)&((u_char *)&cs->cs_ip)[hlen];
+ th->th_sum = htons((*cp << 8) | cp[1]);
+ cp += 2;
+ if (changes & TCP_PUSH_BIT)
+ th->th_flags |= TCP_PSH;
+ else
+ th->th_flags &=~ TCP_PSH;
+
+ switch (changes & SPECIALS_MASK) {
+ case SPECIAL_I:
+ {
+ register u32_t i = ntohs(cs->cs_ip.ip_len) - cs->cs_hlen;
+ /* some compilers can't nest inline assembler.. */
+ tmp = ntohl(th->th_ack) + i;
+ th->th_ack = htonl(tmp);
+ tmp = ntohl(th->th_seq) + i;
+ th->th_seq = htonl(tmp);
+ }
+ break;
+
+ case SPECIAL_D:
+ /* some compilers can't nest inline assembler.. */
+ tmp = ntohl(th->th_seq) + ntohs(cs->cs_ip.ip_len) - cs->cs_hlen;
+ th->th_seq = htonl(tmp);
+ break;
+
+ default:
+ if (changes & NEW_U) {
+ th->th_flags |= TCP_URG;
+ DECODEU(th->th_urp);
+ } else
+ th->th_flags &=~ TCP_URG;
+ if (changes & NEW_W)
+ DECODES(th->th_win);
+ if (changes & NEW_A)
+ DECODEL(th->th_ack);
+ if (changes & NEW_S)
+ DECODEL(th->th_seq);
+ break;
+ }
+ if (changes & NEW_I) {
+ DECODES(cs->cs_ip.ip_id);
+ } else {
+ cs->cs_ip.ip_id = ntohs(cs->cs_ip.ip_id) + 1;
+ cs->cs_ip.ip_id = htons(cs->cs_ip.ip_id);
+ }
+
+ /*
+ * At this point, cp points to the first byte of data in the
+ * packet. Fill in the IP total length and update the IP
+ * header checksum.
+ */
+ vjlen = (u_short)(cp - (u_char*)n0->payload);
+ if (n0->len < vjlen) {
+ /*
+ * We must have dropped some characters (crc should detect
+ * this but the old slip framing won't)
+ */
+ PPPDEBUG((LOG_INFO, "vj_uncompress_tcp: head buffer %d too short %d\n",
+ n0->len, vjlen));
+ goto bad;
+ }
+
+#if BYTE_ORDER == LITTLE_ENDIAN
+ tmp = n0->tot_len - vjlen + cs->cs_hlen;
+ cs->cs_ip.ip_len = htons(tmp);
+#else
+ cs->cs_ip.ip_len = htons(n0->tot_len - vjlen + cs->cs_hlen);
+#endif
+
+ /* recompute the ip header checksum */
+ bp = (u_short *) &cs->cs_ip;
+ cs->cs_ip.ip_sum = 0;
+ for (tmp = 0; hlen > 0; hlen -= 2)
+ tmp += *bp++;
+ tmp = (tmp & 0xffff) + (tmp >> 16);
+ tmp = (tmp & 0xffff) + (tmp >> 16);
+ cs->cs_ip.ip_sum = (u_short)(~tmp);
+
+ /* Remove the compressed header and prepend the uncompressed header. */
+ pbuf_header(n0, -vjlen);
+
+ if(MEM_ALIGN(n0->payload) != n0->payload) {
+ struct pbuf *np, *q;
+ u8_t *bufptr;
+
+ np = pbuf_alloc(PBUF_RAW, n0->len + cs->cs_hlen, PBUF_POOL);
+ if(!np) {
+ PPPDEBUG((LOG_WARNING, "vj_uncompress_tcp: realign failed\n"));
+ *nb = NULL;
+ goto bad;
+ }
+
+ pbuf_header(np, -cs->cs_hlen);
+
+ bufptr = n0->payload;
+ for(q = np; q != NULL; q = q->next) {
+ memcpy(q->payload, bufptr, q->len);
+ bufptr += q->len;
+ }
+
+ if(n0->next) {
+ pbuf_chain(np, n0->next);
+ pbuf_dechain(n0);
+ }
+ pbuf_free(n0);
+ n0 = np;
+ }
+
+ if(pbuf_header(n0, cs->cs_hlen)) {
+ struct pbuf *np;
+
+ LWIP_ASSERT("vj_uncompress_tcp: cs->cs_hlen <= PBUF_POOL_BUFSIZE", cs->cs_hlen <= PBUF_POOL_BUFSIZE);
+ np = pbuf_alloc(PBUF_RAW, cs->cs_hlen, PBUF_POOL);
+ if(!np) {
+ PPPDEBUG((LOG_WARNING, "vj_uncompress_tcp: prepend failed\n"));
+ *nb = NULL;
+ goto bad;
+ }
+ pbuf_cat(np, n0);
+ n0 = np;
+ }
+ LWIP_ASSERT("n0->len >= cs->cs_hlen", n0->len >= cs->cs_hlen);
+ memcpy(n0->payload, &cs->cs_ip, cs->cs_hlen);
+
+ *nb = n0;
+
+ return vjlen;
+
+bad:
+ comp->flags |= VJF_TOSS;
+ INCR(vjs_errorin);
+ return (-1);
+}
+
+#endif
+
+
--- /dev/null
+/*
+ * Definitions for tcp compression routines.
+ *
+ * $Id: vj.h,v 1.4 2004/02/07 00:30:03 likewise Exp $
+ *
+ * Copyright (c) 1989 Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by the University of California, Berkeley. The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Van Jacobson (van@helios.ee.lbl.gov), Dec 31, 1989:
+ * - Initial distribution.
+ */
+
+#ifndef VJ_H
+#define VJ_H
+
+#include "vjbsdhdr.h"
+
+#define MAX_SLOTS 16 /* must be > 2 and < 256 */
+#define MAX_HDR 128
+
+/*
+ * Compressed packet format:
+ *
+ * The first octet contains the packet type (top 3 bits), TCP
+ * 'push' bit, and flags that indicate which of the 4 TCP sequence
+ * numbers have changed (bottom 5 bits). The next octet is a
+ * conversation number that associates a saved IP/TCP header with
+ * the compressed packet. The next two octets are the TCP checksum
+ * from the original datagram. The next 0 to 15 octets are
+ * sequence number changes, one change per bit set in the header
+ * (there may be no changes and there are two special cases where
+ * the receiver implicitly knows what changed -- see below).
+ *
+ * There are 5 numbers which can change (they are always inserted
+ * in the following order): TCP urgent pointer, window,
+ * acknowlegement, sequence number and IP ID. (The urgent pointer
+ * is different from the others in that its value is sent, not the
+ * change in value.) Since typical use of SLIP links is biased
+ * toward small packets (see comments on MTU/MSS below), changes
+ * use a variable length coding with one octet for numbers in the
+ * range 1 - 255 and 3 octets (0, MSB, LSB) for numbers in the
+ * range 256 - 65535 or 0. (If the change in sequence number or
+ * ack is more than 65535, an uncompressed packet is sent.)
+ */
+
+/*
+ * Packet types (must not conflict with IP protocol version)
+ *
+ * The top nibble of the first octet is the packet type. There are
+ * three possible types: IP (not proto TCP or tcp with one of the
+ * control flags set); uncompressed TCP (a normal IP/TCP packet but
+ * with the 8-bit protocol field replaced by an 8-bit connection id --
+ * this type of packet syncs the sender & receiver); and compressed
+ * TCP (described above).
+ *
+ * LSB of 4-bit field is TCP "PUSH" bit (a worthless anachronism) and
+ * is logically part of the 4-bit "changes" field that follows. Top
+ * three bits are actual packet type. For backward compatibility
+ * and in the interest of conserving bits, numbers are chosen so the
+ * IP protocol version number (4) which normally appears in this nibble
+ * means "IP packet".
+ */
+
+/* packet types */
+#define TYPE_IP 0x40
+#define TYPE_UNCOMPRESSED_TCP 0x70
+#define TYPE_COMPRESSED_TCP 0x80
+#define TYPE_ERROR 0x00
+
+/* Bits in first octet of compressed packet */
+#define NEW_C 0x40 /* flag bits for what changed in a packet */
+#define NEW_I 0x20
+#define NEW_S 0x08
+#define NEW_A 0x04
+#define NEW_W 0x02
+#define NEW_U 0x01
+
+/* reserved, special-case values of above */
+#define SPECIAL_I (NEW_S|NEW_W|NEW_U) /* echoed interactive traffic */
+#define SPECIAL_D (NEW_S|NEW_A|NEW_W|NEW_U) /* unidirectional data */
+#define SPECIALS_MASK (NEW_S|NEW_A|NEW_W|NEW_U)
+
+#define TCP_PUSH_BIT 0x10
+
+
+/*
+ * "state" data for each active tcp conversation on the wire. This is
+ * basically a copy of the entire IP/TCP header from the last packet
+ * we saw from the conversation together with a small identifier
+ * the transmit & receive ends of the line use to locate saved header.
+ */
+struct cstate {
+ struct cstate *cs_next; /* next most recently used state (xmit only) */
+ u_short cs_hlen; /* size of hdr (receive only) */
+ u_char cs_id; /* connection # associated with this state */
+ u_char cs_filler;
+ union {
+ char csu_hdr[MAX_HDR];
+ struct ip csu_ip; /* ip/tcp hdr from most recent packet */
+ } vjcs_u;
+};
+#define cs_ip vjcs_u.csu_ip
+#define cs_hdr vjcs_u.csu_hdr
+
+
+struct vjstat {
+ unsigned long vjs_packets; /* outbound packets */
+ unsigned long vjs_compressed; /* outbound compressed packets */
+ unsigned long vjs_searches; /* searches for connection state */
+ unsigned long vjs_misses; /* times couldn't find conn. state */
+ unsigned long vjs_uncompressedin; /* inbound uncompressed packets */
+ unsigned long vjs_compressedin; /* inbound compressed packets */
+ unsigned long vjs_errorin; /* inbound unknown type packets */
+ unsigned long vjs_tossed; /* inbound packets tossed because of error */
+};
+
+/*
+ * all the state data for one serial line (we need one of these per line).
+ */
+struct vjcompress {
+ struct cstate *last_cs; /* most recently used tstate */
+ u_char last_recv; /* last rcvd conn. id */
+ u_char last_xmit; /* last sent conn. id */
+ u_short flags;
+ u_char maxSlotIndex;
+ u_char compressSlot; /* Flag indicating OK to compress slot ID. */
+#if LINK_STATS
+ struct vjstat stats;
+#endif
+ struct cstate tstate[MAX_SLOTS]; /* xmit connection states */
+ struct cstate rstate[MAX_SLOTS]; /* receive connection states */
+};
+
+/* flag values */
+#define VJF_TOSS 1U /* tossing rcvd frames because of input err */
+
+extern void vj_compress_init (struct vjcompress *comp);
+extern u_int vj_compress_tcp (struct vjcompress *comp, struct pbuf *pb);
+extern void vj_uncompress_err (struct vjcompress *comp);
+extern int vj_uncompress_uncomp(struct pbuf *nb, struct vjcompress *comp);
+extern int vj_uncompress_tcp(struct pbuf **nb, struct vjcompress *comp);
+
+#endif /* VJ_H */
--- /dev/null
+#ifndef VJBSDHDR_H
+#define VJBSDHDR_H
+
+#include "lwip/tcp.h"
+
+
+/*
+ * Structure of an internet header, naked of options.
+ *
+ * We declare ip_len and ip_off to be short, rather than u_short
+ * pragmatically since otherwise unsigned comparisons can result
+ * against negative integers quite easily, and fail in subtle ways.
+ */
+PACK_STRUCT_BEGIN
+struct ip
+{
+#if defined(NO_CHAR_BITFIELDS)
+ u_char ip_hl_v; /* bug in GCC for mips means the bitfield stuff will sometimes break - so we use a char for both and get round it with macro's instead... */
+#else
+#if BYTE_ORDER == LITTLE_ENDIAN
+ unsigned ip_hl:4, /* header length */
+ ip_v:4; /* version */
+#elif BYTE_ORDER == BIG_ENDIAN
+ unsigned ip_v:4, /* version */
+ ip_hl:4; /* header length */
+#else
+ COMPLAIN - NO BYTE ORDER SELECTED!
+#endif
+#endif
+ u_char ip_tos; /* type of service */
+ u_short ip_len; /* total length */
+ u_short ip_id; /* identification */
+ u_short ip_off; /* fragment offset field */
+#define IP_DF 0x4000 /* dont fragment flag */
+#define IP_MF 0x2000 /* more fragments flag */
+#define IP_OFFMASK 0x1fff /* mask for fragmenting bits */
+ u_char ip_ttl; /* time to live */
+ u_char ip_p; /* protocol */
+ u_short ip_sum; /* checksum */
+ struct in_addr ip_src,ip_dst; /* source and dest address */
+};
+PACK_STRUCT_END
+
+typedef u32_t tcp_seq;
+
+/*
+ * TCP header.
+ * Per RFC 793, September, 1981.
+ */
+PACK_STRUCT_BEGIN
+struct tcphdr
+{
+ u_short th_sport; /* source port */
+ u_short th_dport; /* destination port */
+ tcp_seq th_seq; /* sequence number */
+ tcp_seq th_ack; /* acknowledgement number */
+#if defined(NO_CHAR_BITFIELDS)
+ u_char th_x2_off;
+#else
+#if BYTE_ORDER == LITTLE_ENDIAN
+ unsigned th_x2:4, /* (unused) */
+ th_off:4; /* data offset */
+#endif
+#if BYTE_ORDER == BIG_ENDIAN
+ unsigned th_off:4, /* data offset */
+ th_x2:4; /* (unused) */
+#endif
+#endif
+ u_char th_flags;
+ u_short th_win; /* window */
+ u_short th_sum; /* checksum */
+ u_short th_urp; /* urgent pointer */
+};
+PACK_STRUCT_END
+
+#endif /* VJBSDHDR_H */
--- /dev/null
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is built upon the file: src/arch/rtxc/netif/sioslip.c
+ *
+ * Author: Magnus Ivarsson <magnus.ivarsson(at)volvo.com>
+ */
+
+/*
+ * This is an arch independent SLIP netif. The specific serial hooks must be provided
+ * by another file.They are sio_open, sio_recv and sio_send
+ */
+
+#include "netif/slipif.h"
+#include "lwip/opt.h"
+#include "lwip/def.h"
+#include "lwip/pbuf.h"
+#include "lwip/sys.h"
+#include "lwip/stats.h"
+#include "lwip/sio.h"
+
+#define SLIP_END 0300
+#define SLIP_ESC 0333
+#define SLIP_ESC_END 0334
+#define SLIP_ESC_ESC 0335
+
+#define MAX_SIZE 1500
+
+/**
+ * Send a pbuf doing the necessary SLIP encapsulation
+ *
+ * Uses the serial layer's sio_send()
+ */
+err_t
+slipif_output(struct netif *netif, struct pbuf *p, struct ip_addr *ipaddr)
+{
+ struct pbuf *q;
+ int i;
+ u8_t c;
+
+ /* Send pbuf out on the serial I/O device. */
+ sio_send(SLIP_END, netif->state);
+
+ for(q = p; q != NULL; q = q->next) {
+ for(i = 0; i < q->len; i++) {
+ c = ((u8_t *)q->payload)[i];
+ switch (c) {
+ case SLIP_END:
+ sio_send(SLIP_ESC, netif->state);
+ sio_send(SLIP_ESC_END, netif->state);
+ break;
+ case SLIP_ESC:
+ sio_send(SLIP_ESC, netif->state);
+ sio_send(SLIP_ESC_ESC, netif->state);
+ break;
+ default:
+ sio_send(c, netif->state);
+ break;
+ }
+ }
+ }
+ sio_send(SLIP_END, netif->state);
+ return 0;
+}
+
+/**
+ * Handle the incoming SLIP stream character by character
+ *
+ * Poll the serial layer by calling sio_recv()
+ *
+ * @return The IP packet when SLIP_END is received
+ */
+static struct pbuf *
+slipif_input( struct netif * netif )
+{
+ u8_t c;
+ struct pbuf *p, *q;
+ int recved;
+ int i;
+
+ q = p = NULL;
+ recved = i = 0;
+ c = 0;
+
+ while (1) {
+ c = sio_recv(netif->state);
+ switch (c) {
+ case SLIP_END:
+ if (recved > 0) {
+ /* Received whole packet. */
+ pbuf_realloc(q, recved);
+
+ LINK_STATS_INC(link.recv);
+
+ LWIP_DEBUGF(SLIP_DEBUG, ("slipif: Got packet\n"));
+ return q;
+ }
+ break;
+
+ case SLIP_ESC:
+ c = sio_recv(netif->state);
+ switch (c) {
+ case SLIP_ESC_END:
+ c = SLIP_END;
+ break;
+ case SLIP_ESC_ESC:
+ c = SLIP_ESC;
+ break;
+ }
+ /* FALLTHROUGH */
+
+ default:
+ if (p == NULL) {
+ LWIP_DEBUGF(SLIP_DEBUG, ("slipif_input: alloc\n"));
+ p = pbuf_alloc(PBUF_LINK, PBUF_POOL_BUFSIZE, PBUF_POOL);
+
+ if (p == NULL) {
+ LINK_STATS_INC(link.drop);
+ LWIP_DEBUGF(SLIP_DEBUG, ("slipif_input: no new pbuf! (DROP)\n"));
+ }
+
+ if (q != NULL) {
+ pbuf_cat(q, p);
+ } else {
+ q = p;
+ }
+ }
+ if (p != NULL && recved < MAX_SIZE) {
+ ((u8_t *)p->payload)[i] = c;
+ recved++;
+ i++;
+ if (i >= p->len) {
+ i = 0;
+ p = NULL;
+ }
+ }
+ break;
+ }
+
+ }
+ return NULL;
+}
+
+/**
+ * The SLIP input thread
+ *
+ * Feed the IP layer with incoming packets
+ */
+static void
+slipif_loop(void *nf)
+{
+ struct pbuf *p;
+ struct netif *netif = (struct netif *)nf;
+
+ while (1) {
+ p = slipif_input(netif);
+ netif->input(p, netif);
+ }
+}
+
+/**
+ * SLIP netif initialization
+ *
+ * Call the arch specific sio_open and remember
+ * the opened device in the state field of the netif.
+ */
+err_t
+slipif_init(struct netif *netif)
+{
+
+ LWIP_DEBUGF(SLIP_DEBUG, ("slipif_init: netif->num=%x\n", (int)netif->num));
+
+ netif->name[0] = 's';
+ netif->name[1] = 'l';
+ netif->output = slipif_output;
+ netif->mtu = 1500;
+ netif->flags = NETIF_FLAG_POINTTOPOINT;
+
+ netif->state = sio_open(netif->num);
+ if (!netif->state)
+ return ERR_IF;
+
+ sys_thread_new(slipif_loop, netif, SLIPIF_THREAD_PRIO);
+ return ERR_OK;
+}
--- /dev/null
+/*\r
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.\r
+ * All rights reserved. \r
+ * \r
+ * Redistribution and use in source and binary forms, with or without modification, \r
+ * are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. The name of the author may not be used to endorse or promote products\r
+ * derived from this software without specific prior written permission. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED \r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT \r
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, \r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT \r
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS \r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN \r
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING \r
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY \r
+ * OF SUCH DAMAGE.\r
+ *\r
+ * This file is part of the lwIP TCP/IP stack.\r
+ * \r
+ * Author: Adam Dunkels <adam@sics.se>\r
+ *\r
+ */\r
+#ifndef __LWIPOPTS_H__\r
+#define __LWIPOPTS_H__\r
+\r
+#define LWIP_NOASSERT 1 // To suppress some errors for now (no debug output)\r
+#define SYS_LIGHTWEIGHT_PROT 1\r
+\r
+#define TCPIP_THREAD_PRIO 3\r
+\r
+/* ---------- Memory options ---------- */\r
+/* MEM_ALIGNMENT: should be set to the alignment of the CPU for which\r
+ lwIP is compiled. 4 byte alignment -> define MEM_ALIGNMENT to 4, 2\r
+ byte alignment -> define MEM_ALIGNMENT to 2. */\r
+#define MEM_ALIGNMENT 4\r
+\r
+/* MEM_SIZE: the size of the heap memory. If the application will send\r
+a lot of data that needs to be copied, this should be set high. */\r
+#define MEM_SIZE 2000\r
+\r
+/* MEMP_NUM_PBUF: the number of memp struct pbufs. If the application\r
+ sends a lot of data out of ROM (or other static memory), this\r
+ should be set high. */\r
+#define MEMP_NUM_PBUF 20\r
+/* MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One\r
+ per active UDP "connection". */\r
+#define MEMP_NUM_UDP_PCB 4\r
+/* MEMP_NUM_TCP_PCB: the number of simulatenously active TCP\r
+ connections. */\r
+#define MEMP_NUM_TCP_PCB 10\r
+/* MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP\r
+ connections. */\r
+#define MEMP_NUM_TCP_PCB_LISTEN 8\r
+/* MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP\r
+ segments. */\r
+#define MEMP_NUM_TCP_SEG 8\r
+/* MEMP_NUM_SYS_TIMEOUT: the number of simulateously active\r
+ timeouts. */\r
+#define MEMP_NUM_SYS_TIMEOUT 3\r
+\r
+\r
+/* The following four are used only with the sequential API and can be\r
+ set to 0 if the application only will use the raw API. */\r
+/* MEMP_NUM_NETBUF: the number of struct netbufs. */\r
+#define MEMP_NUM_NETBUF 4\r
+/* MEMP_NUM_NETCONN: the number of struct netconns. */\r
+#define MEMP_NUM_NETCONN 4\r
+/* MEMP_NUM_APIMSG: the number of struct api_msg, used for\r
+ communication between the TCP/IP stack and the sequential\r
+ programs. */\r
+#define MEMP_NUM_API_MSG 8\r
+/* MEMP_NUM_TCPIPMSG: the number of struct tcpip_msg, which is used\r
+ for sequential API communication and incoming packets. Used in\r
+ src/api/tcpip.c. */\r
+#define MEMP_NUM_TCPIP_MSG 8\r
+\r
+/* These two control is reclaimer functions should be compiled\r
+ in. Should always be turned on (1). */\r
+#define MEM_RECLAIM 1\r
+#define MEMP_RECLAIM 1\r
+\r
+/* ---------- Pbuf options ---------- */\r
+/* PBUF_POOL_SIZE: the number of buffers in the pbuf pool. */\r
+#define PBUF_POOL_SIZE 16\r
+\r
+/* PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. */\r
+#define PBUF_POOL_BUFSIZE 512\r
+\r
+/* PBUF_LINK_HLEN: the number of bytes that should be allocated for a\r
+ link level header. */\r
+#define PBUF_LINK_HLEN 16\r
+\r
+/* ---------- TCP options ---------- */\r
+#define LWIP_TCP 1\r
+#define TCP_TTL 255\r
+\r
+/* Controls if TCP should queue segments that arrive out of\r
+ order. Define to 0 if your device is low on memory. */\r
+#define TCP_QUEUE_OOSEQ 1\r
+\r
+/* TCP Maximum segment size. */\r
+#define TCP_MSS 512\r
+\r
+/* TCP sender buffer space (bytes). */\r
+#define TCP_SND_BUF 512\r
+\r
+/* TCP sender buffer space (pbufs). This must be at least = 2 *\r
+ TCP_SND_BUF/TCP_MSS for things to work. */\r
+#define TCP_SND_QUEUELEN 6 * TCP_SND_BUF/TCP_MSS\r
+\r
+/* TCP receive window. */\r
+#define TCP_WND 512\r
+\r
+/* Maximum number of retransmissions of data segments. */\r
+#define TCP_MAXRTX 12\r
+\r
+/* Maximum number of retransmissions of SYN segments. */\r
+#define TCP_SYNMAXRTX 4\r
+\r
+/* ---------- ARP options ---------- */\r
+#define ARP_TABLE_SIZE 10\r
+#define ARP_QUEUEING 1\r
+\r
+/* ---------- IP options ---------- */\r
+/* Define IP_FORWARD to 1 if you wish to have the ability to forward\r
+ IP packets across network interfaces. If you are going to run lwIP\r
+ on a device with only one network interface, define this to 0. */\r
+#define IP_FORWARD 1\r
+\r
+/* If defined to 1, IP options are allowed (but not parsed). If\r
+ defined to 0, all packets with IP options are dropped. */\r
+#define IP_OPTIONS 1\r
+\r
+/* ---------- ICMP options ---------- */\r
+#define ICMP_TTL 255\r
+\r
+\r
+/* ---------- DHCP options ---------- */\r
+/* Define LWIP_DHCP to 1 if you want DHCP configuration of\r
+ interfaces. DHCP is not implemented in lwIP 0.5.1, however, so\r
+ turning this on does currently not work. */\r
+#define LWIP_DHCP 0\r
+\r
+/* 1 if you want to do an ARP check on the offered address\r
+ (recommended). */\r
+#define DHCP_DOES_ARP_CHECK 1\r
+\r
+/* ---------- UDP options ---------- */\r
+#define LWIP_UDP 1\r
+#define UDP_TTL 255\r
+\r
+\r
+/* ---------- Statistics options ---------- */\r
+#define STATS\r
+\r
+#ifdef STATS\r
+#define LINK_STATS 1\r
+#define IP_STATS 1\r
+#define ICMP_STATS 1\r
+#define UDP_STATS 1\r
+#define TCP_STATS 1\r
+#define MEM_STATS 1\r
+#define MEMP_STATS 1\r
+#define PBUF_STATS 1\r
+#define SYS_STATS 1\r
+#endif /* STATS */\r
+\r
+#define LWIP_PROVIDE_ERRNO 1\r
+\r
+#endif /* __LWIPOPTS_H__ */\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* \r
+ NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.\r
+ The processor MUST be in supervisor mode when vTaskStartScheduler is \r
+ called. The demo applications included in the FreeRTOS.org download switch\r
+ to supervisor mode prior to main being called. If you are not using one of\r
+ these demo application projects then ensure Supervisor mode is used.\r
+*/\r
+\r
+\r
+/*\r
+ * Creates all the application tasks, then starts the scheduler.\r
+ *\r
+ * A task defined by the function vBasicWEBServer is created. This executes \r
+ * the lwIP stack and basic WEB server sample. A task defined by the function\r
+ * vUSBCDCTask. This executes the USB to serial CDC example. All the other \r
+ * tasks are from the set of standard demo tasks. The WEB documentation \r
+ * provides more details of the standard demo application tasks.\r
+ *\r
+ * Main.c also creates a task called "Check". This only executes every three\r
+ * seconds but has the highest priority so is guaranteed to get processor time.\r
+ * Its main function is to check the status of all the other demo application\r
+ * tasks. LED mainCHECK_LED is toggled every three seconds by the check task\r
+ * should no error conditions be detected in any of the standard demo tasks.\r
+ * The toggle rate increasing to 500ms indicates that at least one error has\r
+ * been detected.\r
+ *\r
+ * Main.c includes an idle hook function that simply periodically sends data\r
+ * to the USB task for transmission.\r
+ */\r
+\r
+/*\r
+ Changes from V3.2.2\r
+\r
+ + Modified the stack sizes used by some tasks to permit use of the \r
+ command line GCC tools.\r
+*/\r
+\r
+/* Library includes. */\r
+#include <string.h>\r
+#include <stdio.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo application includes. */\r
+#include "partest.h"\r
+#include "PollQ.h"\r
+#include "semtest.h"\r
+#include "flash.h"\r
+#include "integer.h"\r
+#include "BlockQ.h"\r
+#include "BasicWEB.h"\r
+#include "USB-CDC.h"\r
+\r
+/* lwIP includes. */\r
+#include "lwip/api.h" \r
+\r
+/* Hardware specific headers. */\r
+#include "Board.h"\r
+#include "AT91SAM7X256.h"\r
+\r
+/* Priorities/stacks for the various tasks within the demo application. */\r
+#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define mainFLASH_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define mainWEBSERVER_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainUSB_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define mainUSB_TASK_STACK ( 200 )\r
+\r
+/* The rate at which the on board LED will toggle when there is/is not an\r
+error. */\r
+#define mainNO_ERROR_FLASH_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS )\r
+#define mainERROR_FLASH_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS )\r
+\r
+/* The rate at which the idle hook sends data to the USB port. */\r
+#define mainUSB_TX_FREQUENCY ( 100 / portTICK_RATE_MS )\r
+\r
+/* The string that is transmitted down the USB port. */\r
+#define mainFIRST_TX_CHAR 'a'\r
+#define mainLAST_TX_CHAR 'z'\r
+\r
+/* The LED used by the check task to indicate the system status. */\r
+#define mainCHECK_LED ( 3 )\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Checks that all the demo application tasks are still executing without error\r
+ * - as described at the top of the file.\r
+ */\r
+static portLONG prvCheckOtherTasksAreStillRunning( void );\r
+\r
+/*\r
+ * The task that executes at the highest priority and calls\r
+ * prvCheckOtherTasksAreStillRunning(). See the description at the top\r
+ * of the file.\r
+ */\r
+static void vErrorChecks( void *pvParameters );\r
+\r
+/*\r
+ * Configure the processor for use with the Atmel demo board. This is very\r
+ * minimal as most of the setup is performed in the startup code.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*\r
+ * The idle hook is just used to stream data to the USB port.\r
+ */\r
+void vApplicationIdleHook( void );\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Setup hardware then start all the demo application tasks.\r
+ */\r
+int main( void )\r
+{\r
+ /* Setup the ports. */\r
+ prvSetupHardware();\r
+\r
+ /* Setup the IO required for the LED's. */\r
+ vParTestInitialise();\r
+\r
+ /* Setup lwIP. */\r
+ vlwIPInit();\r
+\r
+ /* Create the lwIP task. This uses the lwIP RTOS abstraction layer.*/\r
+ sys_thread_new( vBasicWEBServer, ( void * ) NULL, mainWEBSERVER_PRIORITY );\r
+\r
+ /* Create the demo USB CDC task. */\r
+ xTaskCreate( vUSBCDCTask, ( signed portCHAR * ) "USB", mainUSB_TASK_STACK, NULL, mainUSB_PRIORITY, NULL );\r
+\r
+ /* Create the standard demo application tasks. */\r
+ vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
+ vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
+ vStartLEDFlashTasks( mainFLASH_PRIORITY );\r
+ vStartIntegerMathTasks( tskIDLE_PRIORITY );\r
+ vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
+\r
+ /* Start the check task - which is defined in this file. */ \r
+ xTaskCreate( vErrorChecks, ( signed portCHAR * ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
+\r
+ /* Finally, start the scheduler. \r
+\r
+ NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.\r
+ The processor MUST be in supervisor mode when vTaskStartScheduler is \r
+ called. The demo applications included in the FreeRTOS.org download switch\r
+ to supervisor mode prior to main being called. If you are not using one of\r
+ these demo application projects then ensure Supervisor mode is used here. */\r
+ vTaskStartScheduler();\r
+\r
+ /* Should never get here! */\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+ /* When using the JTAG debugger the hardware is not always initialised to\r
+ the correct default state. This line just ensures that this does not\r
+ cause all interrupts to be masked at the start. */\r
+ AT91C_BASE_AIC->AIC_EOICR = 0;\r
+ \r
+ /* Most setup is performed by the low level init function called from the\r
+ startup asm file.\r
+\r
+ Configure the PIO Lines corresponding to LED1 to LED4 to be outputs as\r
+ well as the UART Tx line. */\r
+ AT91C_BASE_PIOB->PIO_PER = LED_MASK; // Set in PIO mode\r
+ AT91C_BASE_PIOB->PIO_OER = LED_MASK; // Configure in Output\r
+\r
+\r
+ /* Enable the peripheral clock. */\r
+ AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOA;\r
+ AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOB;\r
+ AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_EMAC;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vErrorChecks( void *pvParameters )\r
+{\r
+portTickType xDelayPeriod = mainNO_ERROR_FLASH_PERIOD;\r
+portTickType xLastWakeTime;\r
+\r
+ /* The parameters are not used. */\r
+ ( void ) pvParameters;\r
+\r
+ /* Initialise xLastWakeTime to ensure the first call to vTaskDelayUntil()\r
+ functions correctly. */\r
+ xLastWakeTime = xTaskGetTickCount();\r
+\r
+ /* Cycle for ever, delaying then checking all the other tasks are still\r
+ operating without error. If an error is detected then the delay period\r
+ is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so\r
+ the Check LED flash rate will increase. */\r
+ for( ;; )\r
+ {\r
+ /* Delay until it is time to execute again. The delay period is\r
+ shorter following an error. */\r
+ vTaskDelayUntil( &xLastWakeTime, xDelayPeriod );\r
+ \r
+ /* Check all the standard demo application tasks are executing without\r
+ error. */\r
+ if( prvCheckOtherTasksAreStillRunning() != pdPASS )\r
+ {\r
+ /* An error has been detected in one of the tasks - flash faster. */\r
+ xDelayPeriod = mainERROR_FLASH_PERIOD;\r
+ }\r
+\r
+ vParTestToggleLED( mainCHECK_LED );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portLONG prvCheckOtherTasksAreStillRunning( void )\r
+{\r
+portLONG lReturn = ( portLONG ) pdPASS;\r
+\r
+ /* Check all the demo tasks (other than the flash tasks) to ensure\r
+ that they are all still running, and that none of them have detected\r
+ an error. */\r
+\r
+ if( xArePollingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ lReturn = ( portLONG ) pdFAIL;\r
+ }\r
+\r
+ if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ lReturn = ( portLONG ) pdFAIL;\r
+ }\r
+\r
+ if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ lReturn = ( portLONG ) pdFAIL;\r
+ }\r
+\r
+ if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ lReturn = ( portLONG ) pdFAIL;\r
+ }\r
+\r
+ return lReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationIdleHook( void )\r
+{\r
+static portTickType xLastTx = 0;\r
+portCHAR cTxByte;\r
+\r
+ /* The idle hook simply sends a string of characters to the USB port.\r
+ The characters will be buffered and sent once the port is connected. */\r
+ if( ( xTaskGetTickCount() - xLastTx ) > mainUSB_TX_FREQUENCY )\r
+ {\r
+ xLastTx = xTaskGetTickCount();\r
+ for( cTxByte = mainFIRST_TX_CHAR; cTxByte <= mainLAST_TX_CHAR; cTxByte++ )\r
+ {\r
+ vUSBSendByte( cTxByte );\r
+ } \r
+ }\r
+}\r
+\r
+\r
--- /dev/null
+# FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+#\r
+# This file is part of the FreeRTOS distribution.\r
+#\r
+# FreeRTOS is free software; you can redistribute it and/or modify\r
+# it under the terms of the GNU General Public License as published by\r
+# the Free Software Foundation; either version 2 of the License, or\r
+# (at your option) any later version.\r
+#\r
+# FreeRTOS is distributed in the hope that it will be useful,\r
+# but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+# GNU General Public License for more details.\r
+#\r
+# You should have received a copy of the GNU General Public License\r
+# along with FreeRTOS; if not, write to the Free Software\r
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+#\r
+# A special exception to the GPL can be applied should you wish to distribute\r
+# a combined work that includes FreeRTOS, without being obliged to provide\r
+# the source code for any proprietary components. See the licensing section \r
+# of http://www.FreeRTOS.org for full details of how and when the exception\r
+# can be applied.\r
+#\r
+# ***************************************************************************\r
+# See http://www.FreeRTOS.org for documentation, latest information, license \r
+# and contact details. Please ensure to read the configuration and relevant \r
+# port sections of the online documentation.\r
+# ***************************************************************************\r
+\r
+CC=arm-elf-gcc\r
+OBJCOPY=arm-elf-objcopy\r
+ARCH=arm-elf-ar\r
+CRT0=boot.s\r
+DEBUG=\r
+OPTIM=-Os\r
+LDSCRIPT=atmel-rom.ld\r
+\r
+#\r
+# CFLAGS common to both the THUMB and ARM mode builds\r
+#\r
+\r
+CFLAGS= \\r
+-I. \\r
+-I./EMAC \\r
+-I../Common/include \\r
+-I./USB \\r
+-I./lwip-1.1.0/src/include \\r
+-I./lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X \\r
+-I../../Source/include \\r
+-I../../Source/portable/GCC/ARM7_AT91SAM7S \\r
+-I./lwip-1.1.0/src/include/ipv4 \\r
+-Wall \\r
+-Wextra \\r
+-Wstrict-prototypes \\r
+-Wmissing-prototypes \\r
+-Wmissing-declarations \\r
+-Wno-strict-aliasing \\r
+-D SAM7_GCC \\r
+-D THUMB_INTERWORK \\r
+-mthumb-interwork \\r
+-mcpu=arm7tdmi \\r
+-T$(LDSCRIPT) \\r
+$(DEBUG) \\r
+$(OPTIM)\r
+\r
+THUMB_FLAGS=-mthumb\r
+LINKER_FLAGS=-Xlinker -ortosdemo.elf -Xlinker -M -Xlinker -Map=rtosdemo.map\r
+\r
+#\r
+# Source files that can be built to THUMB mode.\r
+#\r
+FREERTOS_THUMB_SRC= \\r
+ ../../Source/tasks.c \\r
+ ../../Source/queue.c \\r
+ ../../Source/list.c \\r
+ ../../Source/portable/GCC/ARM7_AT91SAM7S/port.c\r
+\r
+DEMO_APP_THMUB_SRC= \\r
+ ../../Source/portable/MemMang/heap_2.c \\r
+ ParTest/ParTest.c \\r
+ main.c \\r
+ ../Common/Minimal/flash.c \\r
+ ../Common/Minimal/BlockQ.c \\r
+ ../Common/Minimal/integer.c \\r
+ ../Common/Minimal/PollQ.c \\r
+ ../Common/Minimal/semtest.c \\r
+ BasicWEB.c \\r
+ USB/USB-CDC.c \r
+\r
+LWIP_THUMB_SRC= \\r
+ lwip-1.1.0/src/core/tcp_out.c \\r
+ lwip-1.1.0/src/core/inet.c \\r
+ lwip-1.1.0/src/core/mem.c \\r
+ lwip-1.1.0/src/core/memp.c \\r
+ lwip-1.1.0/src/core/netif.c \\r
+ lwip-1.1.0/src/core/pbuf.c \\r
+ lwip-1.1.0/src/core/raw.c \\r
+ lwip-1.1.0/src/core/stats.c \\r
+ lwip-1.1.0/src/core/sys.c \\r
+ lwip-1.1.0/src/core/tcp.c \\r
+ lwip-1.1.0/src/core/tcp_in.c \\r
+ lwip-1.1.0/src/core/ipv4/ip.c \\r
+ lwip-1.1.0/src/core/ipv4/ip_addr.c \\r
+ lwip-1.1.0/src/core/ipv4/icmp.c \\r
+ lwip-1.1.0/src/api/tcpip.c \\r
+ lwip-1.1.0/src/api/api_msg.c \\r
+ lwip-1.1.0/src/api/err.c \\r
+ lwip-1.1.0/src/api/api_lib.c \\r
+ lwip-1.1.0/src/netif/etharp.c \\r
+ lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/sys_arch.c \\r
+ lwip-1.1.0/src/netif/ethernetif.c \\r
+ EMAC/SAM7_EMAC.c \\r
+ lwip-1.1.0/src/core/udp.c \\r
+ lwip-1.1.0/src/core/ipv4/ip_frag.c\r
+\r
+#\r
+# Source files that must be built to ARM mode.\r
+#\r
+ARM_SRC= \\r
+ ../../Source/portable/GCC/ARM7_AT91SAM7S/portISR.c \\r
+ EMAC/SAM7_EMAC_ISR.c \\r
+ USB/USBIsr.c \\r
+ Cstartup_SAM7.c \r
+\r
+\r
+#\r
+# Define all object files.\r
+#\r
+ARM_OBJ = $(ARM_SRC:.c=.o)\r
+FREERTOS_THUMB_OBJ = $(FREERTOS_THUMB_SRC:.c=.o)\r
+DEMO_APP_THMUB_OBJ = $(DEMO_APP_THMUB_SRC:.c=.o)\r
+LWIP_THUMB_OBJ = $(LWIP_THUMB_SRC:.c=.o)\r
+\r
+rtosdemo.bin : rtosdemo.elf\r
+ $(OBJCOPY) rtosdemo.elf -O binary rtosdemo.bin\r
+\r
+rtosdemo.hex : rtosdemo.elf\r
+ $(OBJCOPY) rtosdemo.elf -O ihex rtosdemo.hex\r
+\r
+rtosdemo.elf : $(ARM_OBJ) $(DEMO_APP_THMUB_OBJ) $(LWIP_THUMB_OBJ) $(FREERTOS_THUMB_OBJ) $(CRT0) Makefile FreeRTOSConfig.h\r
+ $(CC) $(CFLAGS) $(ARM_OBJ) $(DEMO_APP_THMUB_OBJ) $(LWIP_THUMB_OBJ) $(FREERTOS_THUMB_OBJ) -nostartfiles $(CRT0) $(LINKER_FLAGS)\r
+\r
+$(DEMO_APP_THMUB_OBJ) : %.o : %.c $(LDSCRIPT) Makefile FreeRTOSConfig.h\r
+ $(CC) -c $(THUMB_FLAGS) $(CFLAGS) $< -o $@\r
+\r
+$(LWIP_THUMB_OBJ) : %.o : %.c $(LDSCRIPT) Makefile FreeRTOSConfig.h\r
+ $(CC) -c $(THUMB_FLAGS) $(CFLAGS) $< -o $@\r
+\r
+$(FREERTOS_THUMB_OBJ) : %.o : %.c $(LDSCRIPT) Makefile FreeRTOSConfig.h\r
+ $(CC) -c $(THUMB_FLAGS) $(CFLAGS) $< -o $@\r
+\r
+$(ARM_OBJ) : %.o : %.c $(LDSCRIPT) Makefile FreeRTOSConfig.h\r
+ $(CC) -c $(CFLAGS) $< -o $@\r
+\r
+clean :\r
+ touch Makefile\r
+\r
--- /dev/null
+<!DOCTYPE CrossStudio_Project_File>
+<solution version="1" Name="rtosdemo" >
+ <project file_name="" Name="rtosdemo" >
+ <configuration Target="AT91SAM7S256" property_groups_file_path="$(StudioDir)/targets/ATMEL_AT91SAM7/propertyGroups.xml" linker_memory_map_file="$(StudioDir)/targets/ATMEL_AT91SAM7/AT91SAM7S256_MemoryMap.xml" project_directory="" link_include_startup_code="No" project_type="Executable" linker_printf_width_precision_supported="Yes" Name="Common" linker_output_format="bin" />
+ <configuration target_reset_script="RAMReset()" Name="RAM" />
+ <configuration arm_target_flash_loader_file_path="$(StudioDir)/targets/ATMEL_AT91SAM7/Release/Loader.exe" target_reset_script="FLASHReset()" Name="Flash" />
+ <folder Name="Source Files" >
+ <configuration filter="c;cpp;cxx;cc;h;s;asm;inc" Name="Common" />
+ <folder Name="FreeRTOS kernel" >
+ <file file_name="../../Source/tasks.c" Name="tasks.c" />
+ <file file_name="../../Source/queue.c" Name="queue.c" />
+ <file file_name="../../Source/list.c" Name="list.c" />
+ <file file_name="../../Source/portable/GCC/ARM7_AT91SAM7S/portISR.c" Name="portISR.c" >
+ <configuration arm_instruction_set="ARM" Name="Common" />
+ </file>
+ <file file_name="../../Source/portable/GCC/ARM7_AT91SAM7S/port.c" Name="port.c" />
+ </folder>
+ <folder Name="Demo App" >
+ <file file_name="../../Source/portable/MemMang/heap_2.c" Name="heap_2.c" />
+ <file file_name="ParTest/ParTest.c" Name="ParTest.c" />
+ <file file_name="main.c" Name="main.c" />
+ <file file_name="../Common/Minimal/flash.c" Name="flash.c" />
+ <file file_name="../Common/Minimal/BlockQ.c" Name="BlockQ.c" />
+ <file file_name="../Common/Minimal/integer.c" Name="integer.c" />
+ <file file_name="../Common/Minimal/PollQ.c" Name="PollQ.c" />
+ <file file_name="../Common/Minimal/semtest.c" Name="semtest.c" />
+ <file file_name="BasicWEB.c" Name="BasicWEB.c" />
+ <file file_name="USB/USBIsr.c" Name="USBIsr.c" >
+ <configuration arm_instruction_set="ARM" Name="THUMB Flash Release" />
+ <configuration arm_instruction_set="ARM" Name="Common" />
+ </file>
+ <file file_name="USB/USB-CDC.c" Name="USB-CDC.c" />
+ </folder>
+ <folder Name="lwIP" >
+ <file file_name="lwip-1.1.0/src/core/tcp_out.c" Name="tcp_out.c" />
+ <file file_name="lwip-1.1.0/src/core/inet.c" Name="inet.c" />
+ <file file_name="lwip-1.1.0/src/core/mem.c" Name="mem.c" />
+ <file file_name="lwip-1.1.0/src/core/memp.c" Name="memp.c" />
+ <file file_name="lwip-1.1.0/src/core/netif.c" Name="netif.c" />
+ <file file_name="lwip-1.1.0/src/core/pbuf.c" Name="pbuf.c" />
+ <file file_name="lwip-1.1.0/src/core/raw.c" Name="raw.c" />
+ <file file_name="lwip-1.1.0/src/core/stats.c" Name="stats.c" />
+ <file file_name="lwip-1.1.0/src/core/sys.c" Name="sys.c" />
+ <file file_name="lwip-1.1.0/src/core/tcp.c" Name="tcp.c" />
+ <file file_name="lwip-1.1.0/src/core/tcp_in.c" Name="tcp_in.c" />
+ <file file_name="lwip-1.1.0/src/core/ipv4/ip.c" Name="ip.c" />
+ <file file_name="lwip-1.1.0/src/core/ipv4/ip_addr.c" Name="ip_addr.c" />
+ <file file_name="lwip-1.1.0/src/core/ipv4/icmp.c" Name="icmp.c" />
+ <file file_name="lwip-1.1.0/src/api/tcpip.c" Name="tcpip.c" />
+ <file file_name="lwip-1.1.0/src/api/api_msg.c" Name="api_msg.c" />
+ <file file_name="lwip-1.1.0/src/api/err.c" Name="err.c" />
+ <file file_name="lwip-1.1.0/src/api/api_lib.c" Name="api_lib.c" />
+ <file file_name="lwip-1.1.0/src/netif/etharp.c" Name="etharp.c" />
+ <file file_name="lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/sys_arch.c" Name="sys_arch.c" />
+ <file file_name="lwip-1.1.0/src/netif/ethernetif.c" Name="ethernetif.c" />
+ <file file_name="EMAC/SAM7_EMAC.c" Name="SAM7_EMAC.c" />
+ <file file_name="EMAC/SAM7_EMAC_ISR.c" Name="SAM7_EMAC_ISR.c" >
+ <configuration arm_instruction_set="ARM" Name="Common" />
+ </file>
+ <file file_name="lwip-1.1.0/src/core/udp.c" Name="udp.c" />
+ <file file_name="lwip-1.1.0/src/core/ipv4/ip_frag.c" Name="ip_frag.c" />
+ </folder>
+ </folder>
+ <folder Name="System Files" >
+ <file file_name="flash_placement.xml" Name="flash_placement.xml" />
+ <file file_name="crt0.s" Name="crt0.s" />
+ <file file_name="AT91SAM7_Startup.s" Name="AT91SAM7_Startup.s" >
+ <configuration asm_additional_options="" arm_instruction_set="ARM" Name="Common" />
+ </file>
+ <file file_name="AT91SAM7S256_MemoryMap.xml" Name="AT91SAM7S256_MemoryMap.xml" />
+ <file file_name="AT91SAM7_Target.js" Name="AT91SAM7_Target.js" >
+ <configuration Name="Common" file_type="Reset Script" />
+ </file>
+ </folder>
+ <configuration arm_target_loader_reset_after_download="Yes" target_reset_script="FLASHReset()" arm_target_flash_loader_type="Comms Channel Loader" Name="THUMB Flash Debug" />
+ </project>
+ <configuration build_quietly="Yes" inherited_configurations="THUMB;Flash;Debug" Name="THUMB Flash Debug" />
+ <configuration arm_library_instruction_set="THUMB" c_preprocessor_definitions="__THUMB" arm_instruction_set="THUMB" hidden="Yes" Name="THUMB" />
+ <configuration c_preprocessor_definitions="__FLASH_BUILD" hidden="Yes" Name="Flash" />
+ <configuration c_preprocessor_definitions="DEBUG" link_include_startup_code="No" gcc_optimization_level="None" build_debug_information="Yes" Name="Debug" />
+ <configuration inherited_configurations="THUMB;Flash;Release" gcc_optimization_level="Level 2" Name="THUMB Flash Release" />
+ <configuration c_preprocessor_definitions="NDEBUG" link_include_startup_code="No" gcc_optimization_level="Level 1" build_debug_information="No" Name="Release" />
+ <configuration arm_library_instruction_set="THUMB" gcc_entry_point="0x100000" build_quietly="Yes" c_preprocessor_definitions="SAM7_GCC;THUMB_INTERWORK;SUPERVISOR_START" c_user_include_directories=".;$(ProjectDir)/EMAC;$(ProjectDir)/../common/include;$(ProjectDir)/USB" link_include_startup_code="Yes" arm_instruction_set="THUMB" c_preprocessor_undefinitions="" c_additional_options="-Wall ;-Wextra;-Wstrict-prototypes ;-Wmissing-prototypes ;-Wmissing-declarations;-Wno-strict-aliasing" arm_linker_stack_size="0" Name="Common" c_system_include_directories="$(StudioDir)/include;$(ProjectDir)/lwip-1.1.0/src/include;$(ProjectDir)/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X;$(ProjectDir);$(ProjectDir)/../../source/include;$(ProjectDir)/../../source/portable/GCC/ARM7_AT91SAM7S;$(ProjectDir)/lwip-1.1.0\\src\\include\\ipv4" arm_linker_heap_size="0" />
+</solution>
--- /dev/null
+<!DOCTYPE CrossStudio_for_ARM_Session_File>
+<session>
+ <Breakpoints/>
+ <ExecutionCountWindow/>
+ <Memory1>
+ <MemoryWindow autoEvaluate="0" addressText="0x102248" numColumns="8" sizeText="128" dataSize="1" radix="16" addressSpace="" />
+ </Memory1>
+ <Memory2>
+ <MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" addressSpace="" />
+ </Memory2>
+ <Memory3>
+ <MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" addressSpace="" />
+ </Memory3>
+ <Memory4>
+ <MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" addressSpace="" />
+ </Memory4>
+ <Project>
+ <ProjectSessionItem path="rtosdemo" name="unnamed" />
+ <ProjectSessionItem path="rtosdemo;rtosdemo" name="unnamed" />
+ <ProjectSessionItem path="rtosdemo;rtosdemo;Source Files" name="unnamed" />
+ <ProjectSessionItem path="rtosdemo;rtosdemo;Source Files;Demo App" name="unnamed" />
+ <ProjectSessionItem path="rtosdemo;rtosdemo;Source Files;FreeRTOS kernel" name="unnamed" />
+ <ProjectSessionItem path="rtosdemo;rtosdemo;Source Files;lwIP" name="unnamed" />
+ </Project>
+ <Register1>
+ <RegisterWindow unsignedDisplays="" asciiDisplays="" octalDisplays="" visibleGroups="CPU - Current Mode" decimalDisplays="" binaryDisplays="" />
+ </Register1>
+ <Register2>
+ <RegisterWindow unsignedDisplays="" asciiDisplays="" octalDisplays="" visibleGroups="" decimalDisplays="" binaryDisplays="" />
+ </Register2>
+ <Register3>
+ <RegisterWindow unsignedDisplays="" asciiDisplays="" octalDisplays="" visibleGroups="" decimalDisplays="" binaryDisplays="" />
+ </Register3>
+ <Register4>
+ <RegisterWindow unsignedDisplays="" asciiDisplays="" octalDisplays="" visibleGroups="" decimalDisplays="" binaryDisplays="" />
+ </Register4>
+ <SourceNavigatorWindow/>
+ <TraceWindow>
+ <Trace wrap="Yes" type="1" enabled="Yes" />
+ </TraceWindow>
+ <Watch1>
+ <Watches active="1" >
+ <Watchpoint linenumber="0" radix="1" name="(char)pcString" expression="(char)pcString" filename="" />
+ <Watchpoint evalMode="3" linenumber="220" evalType="1" radix="16" name="pcString" expression="pcString" filename="E:\Dev\FreeRTOS\Demo\lwIP_Demo_Rowley_ARM7\USB\USB-CDC.c" />
+ <Watchpoint linenumber="0" radix="-1" name="*((char*)pvItemToQueue)" expression="*((char*)pvItemToQueue)" filename="" />
+ <Watchpoint linenumber="0" radix="-1" name="pcString[i]" expression="pcString[i]" filename="" />
+ </Watches>
+ </Watch1>
+ <Watch2>
+ <Watches active="0" />
+ </Watch2>
+ <Watch3>
+ <Watches active="0" />
+ </Watch3>
+ <Watch4>
+ <Watches active="0" />
+ </Watch4>
+ <Files/>
+ <ARMCrossStudioWindow activeProject="rtosdemo" ignoreExceptions="IRQ;FIQ;SWI" autoConnectTarget="" debugSearchFileMap="" fileDialogInitialDirectory="E:\Dev\FreeRTOS\Demo\Common\Minimal" fileDialogDefaultFilter="*.cpp;*.cxx;*.cc;*.c;*.h" debugSearchPath="" buildConfiguration="THUMB Flash Release" />
+</session>
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+#include <msp430x44x.h>\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. \r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 1\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 7995392 ) /* Clock setup from main.c in the demo application. */\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 4 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 50 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1800 ) )\r
+#define configMAX_TASK_NAME_LEN ( 8 )\r
+#define configUSE_TRACE_FACILITY 0\r
+#define configUSE_16_BIT_TICKS 1\r
+#define configIDLE_SHOULD_YIELD 1\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet 0\r
+#define INCLUDE_uxTaskPriorityGet 0\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 0\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Characters on the LCD are used to simulate LED's. In this case the 'ParTest'\r
+ * is really operating on the LCD display.\r
+ *-----------------------------------------------------------*/\r
+\r
+/*\r
+ * This demo is configured to execute on the ES449 prototyping board from\r
+ * SoftBaugh. The ES449 has a built in LCD display and a single built in user\r
+ * LED. Therefore, in place of flashing an LED, the 'flash' and 'check' tasks\r
+ * toggle '*' characters on the LCD. The left most '*' represents LED 0, the\r
+ * next LED 1, etc.\r
+ *\r
+ * There is a single genuine on board LED referenced as LED 10.\r
+ */\r
+\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo application includes. */\r
+#include "partest.h"\r
+\r
+/* Constants required to setup the LCD. */\r
+#define LCD_DIV_64 5\r
+\r
+/* Constants required to access the "LED's". The LED segments are turned on\r
+and off to generate '*' characters. */\r
+#define partstNUM_LEDS ( ( unsigned portCHAR ) 6 )\r
+#define partstSEGMENTS_ON ( ( unsigned portCHAR ) 0x0f )\r
+#define partstSEGMENTS_OFF ( ( unsigned portCHAR ) 0x00 )\r
+\r
+/* The LED number of the real on board LED, rather than a simulated LED. */\r
+#define partstON_BOARD_LED ( ( unsigned portBASE_TYPE ) 10 )\r
+#define mainON_BOARD_LED_BIT ( ( unsigned portCHAR ) 0x01 )\r
+\r
+/* The LCD segments used to generate the '*' characters for LED's 0 to 5. */\r
+unsigned portCHAR * const ucRHSSegments[ partstNUM_LEDS ] = { ( unsigned portCHAR * )0xa4, \r
+ ( unsigned portCHAR * )0xa2, \r
+ ( unsigned portCHAR * )0xa0, \r
+ ( unsigned portCHAR * )0x9e,\r
+ ( unsigned portCHAR * )0x9c,\r
+ ( unsigned portCHAR * )0x9a };\r
+\r
+unsigned portCHAR * const ucLHSSegments[ partstNUM_LEDS ] = { ( unsigned portCHAR * )0xa3, \r
+ ( unsigned portCHAR * )0xa1, \r
+ ( unsigned portCHAR * )0x9f, \r
+ ( unsigned portCHAR * )0x9d,\r
+ ( unsigned portCHAR * )0x9b,\r
+ ( unsigned portCHAR * )0x99 };\r
+\r
+/*\r
+ * Toggle the single genuine built in LED.\r
+ */\r
+static void prvToggleOnBoardLED( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestInitialise( void )\r
+{\r
+ /* Initialise the LCD hardware. */\r
+\r
+ /* Used for the onboard LED. */\r
+ P1DIR = 0x01;\r
+\r
+ // Setup Basic Timer for LCD operation\r
+ BTCTL = (LCD_DIV_64+0x23);\r
+\r
+ // Setup port functions\r
+ P1SEL = 0x32;\r
+ P2SEL = 0x00;\r
+ P3SEL = 0x00;\r
+ P4SEL = 0xFC;\r
+ P5SEL = 0xFF;\r
+ \r
+ /* Initialise all segments to off. */\r
+ LCDM1 = partstSEGMENTS_OFF; \r
+ LCDM2 = partstSEGMENTS_OFF; \r
+ LCDM3 = partstSEGMENTS_OFF; \r
+ LCDM4 = partstSEGMENTS_OFF; \r
+ LCDM5 = partstSEGMENTS_OFF; \r
+ LCDM6 = partstSEGMENTS_OFF; \r
+ LCDM7 = partstSEGMENTS_OFF; \r
+ LCDM8 = partstSEGMENTS_OFF; \r
+ LCDM9 = partstSEGMENTS_OFF; \r
+ LCDM10 = partstSEGMENTS_OFF; \r
+ LCDM11 = partstSEGMENTS_OFF; \r
+ LCDM12 = partstSEGMENTS_OFF; \r
+ LCDM13 = partstSEGMENTS_OFF; \r
+ LCDM14 = partstSEGMENTS_OFF; \r
+ LCDM15 = partstSEGMENTS_OFF; \r
+ LCDM16 = partstSEGMENTS_OFF; \r
+ LCDM17 = partstSEGMENTS_OFF; \r
+ LCDM18 = partstSEGMENTS_OFF; \r
+ LCDM19 = partstSEGMENTS_OFF; \r
+ LCDM20 = partstSEGMENTS_OFF; \r
+\r
+ /* Setup LCD control. */\r
+ LCDCTL = (LCDSG0_7|LCD4MUX|LCDON);\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )\r
+{\r
+ /* Set or clear the output [in this case show or hide the '*' character. */\r
+ if( uxLED < ( portBASE_TYPE ) partstNUM_LEDS )\r
+ {\r
+ vTaskSuspendAll();\r
+ {\r
+ if( xValue )\r
+ {\r
+ /* Turn on the segments required to show the '*'. */\r
+ *( ucRHSSegments[ uxLED ] ) = partstSEGMENTS_ON;\r
+ *( ucLHSSegments[ uxLED ] ) = partstSEGMENTS_ON;\r
+ }\r
+ else\r
+ {\r
+ /* Turn off all the segments. */\r
+ *( ucRHSSegments[ uxLED ] ) = partstSEGMENTS_OFF;\r
+ *( ucLHSSegments[ uxLED ] ) = partstSEGMENTS_OFF;\r
+ }\r
+ }\r
+ xTaskResumeAll();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+ if( uxLED < ( portBASE_TYPE ) partstNUM_LEDS )\r
+ {\r
+ vTaskSuspendAll();\r
+ {\r
+ /* If the '*' is already showing - hide it. If it is not already\r
+ showing then show it. */\r
+ if( *( ucRHSSegments[ uxLED ] ) )\r
+ {\r
+ *( ucRHSSegments[ uxLED ] ) = partstSEGMENTS_OFF;\r
+ *( ucLHSSegments[ uxLED ] ) = partstSEGMENTS_OFF;\r
+ }\r
+ else\r
+ {\r
+ *( ucRHSSegments[ uxLED ] ) = partstSEGMENTS_ON;\r
+ *( ucLHSSegments[ uxLED ] ) = partstSEGMENTS_ON;\r
+ }\r
+ }\r
+ xTaskResumeAll();\r
+ }\r
+ else\r
+ {\r
+ if( uxLED == partstON_BOARD_LED )\r
+ {\r
+ /* The request related to the genuine on board LED. */\r
+ prvToggleOnBoardLED();\r
+ }\r
+ } \r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvToggleOnBoardLED( void )\r
+{\r
+static unsigned portSHORT sState = pdFALSE;\r
+\r
+ /* Toggle the state of the single genuine on board LED. */\r
+ if( sState ) \r
+ {\r
+ P1OUT |= mainON_BOARD_LED_BIT;\r
+ }\r
+ else\r
+ {\r
+ P1OUT &= ~mainON_BOARD_LED_BIT;\r
+ }\r
+\r
+ sState = !sState;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
--- /dev/null
+<!DOCTYPE CrossStudio_Project_File>
+<solution version="1" Name="RTOSDemo" >
+ <project Name="RTOSDemo" >
+ <configuration Target="MSP430F449" linker_memory_map_file="$(StudioDir)/targets/MSP430F449.xml" project_directory="" link_include_startup_code="No" project_type="Executable" Name="Common" build_use_hardware_multiplier="Yes" />
+ <folder Name="Scheduler Source" >
+ <configuration filter="c;h;s;asm;inc;s43" Name="Common" />
+ <file file_name="../../Source/tasks.c" Name="tasks.c" >
+ <configuration c_preprocessor_definitions="" c_user_include_directories="" Name="Common" c_system_include_directories="" />
+ </file>
+ <file file_name="../../Source/queue.c" Name="queue.c" />
+ <file file_name="../../Source/list.c" Name="list.c" />
+ <file file_name="../../Source/portable/Rowley/MSP430F449/portext.asm" Name="portext.asm" />
+ <file file_name="../../Source/portable/Rowley/MSP430F449/port.c" Name="port.c" />
+ <file file_name="../../Source/portable/MemMang/heap_1.c" Name="heap_1.c" />
+ </folder>
+ <folder Name="Startup Code" >
+ <configuration filter="" Name="Common" />
+ <file file_name="$(StudioDir)/targets/section_placement.xml" Name="section_placement.xml" />
+ <file file_name="$(StudioDir)/src/crt0.asm" Name="crt0.asm" />
+ </folder>
+ <folder Name="Demo Source" >
+ <file file_name="main.c" Name="main.c" />
+ <file file_name="../Common/Minimal/flash.c" Name="flash.c" />
+ <file file_name="../Common/Minimal/comtest.c" Name="comtest.c" />
+ <file file_name="../Common/Minimal/PollQ.c" Name="PollQ.c" />
+ <file file_name="ParTest/ParTest.c" Name="ParTest.c" />
+ <file file_name="serial/serial.c" Name="serial.c" />
+ <file file_name="../Common/Minimal/integer.c" Name="integer.c" />
+ </folder>
+ </project>
+ <configuration compiler_optimization_strategy="Minimize size" optimize_code_motion="No" optimize_block_locality="No" optimize_register_allocation="Locals Only" Name="Debug" />
+ <configuration c_preprocessor_definitions="NDEBUG" build_debug_information="No" Name="Release" build_optimize_output="Yes" />
+ <configuration c_preprocessor_definitions="ROWLEY_MSP430" c_user_include_directories="$(ProjectDir);$(ProjectDir)/../common/include" linker_printf_width_precision_supported="No" Name="Common" c_system_include_directories="$(StudioDir)/include;$(ProjectDir)/../../source/include;$(ProjectDir)/../../source/portable/Rowley/msp430F449" />
+</solution>
--- /dev/null
+<!DOCTYPE CrossStudio_for_MSP430_Session_File>
+<session>
+ <Breakpoints/>
+ <ExecutionCountWindow/>
+ <Memory1>
+ <MemoryWindow autoEvaluate="0" addressText="0x200" numColumns="8" sizeText="2048" dataSize="1" radix="16" addressSpace="" />
+ </Memory1>
+ <Memory2>
+ <MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" addressSpace="" />
+ </Memory2>
+ <Memory3>
+ <MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" addressSpace="" />
+ </Memory3>
+ <Memory4>
+ <MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" addressSpace="" />
+ </Memory4>
+ <Project>
+ <ProjectSessionItem path="RTOSDemo" name="unnamed" />
+ <ProjectSessionItem path="RTOSDemo;RTOSDemo" name="unnamed" />
+ <ProjectSessionItem path="RTOSDemo;RTOSDemo;Demo Source" name="unnamed" />
+ <ProjectSessionItem path="RTOSDemo;RTOSDemo;Scheduler Source" name="unnamed" />
+ <ProjectSessionItem path="RTOSDemo;RTOSDemo;Startup Code" name="unnamed" />
+ </Project>
+ <Register1>
+ <RegisterWindow unsignedDisplays="" asciiDisplays="" octalDisplays="" visibleGroups="CPU Registers" decimalDisplays="" binaryDisplays="" />
+ </Register1>
+ <Register2>
+ <RegisterWindow unsignedDisplays="" asciiDisplays="" octalDisplays="" visibleGroups="" decimalDisplays="" binaryDisplays="" />
+ </Register2>
+ <Register3>
+ <RegisterWindow unsignedDisplays="" asciiDisplays="" octalDisplays="" visibleGroups="" decimalDisplays="" binaryDisplays="" />
+ </Register3>
+ <Register4>
+ <RegisterWindow unsignedDisplays="" asciiDisplays="" octalDisplays="" visibleGroups="" decimalDisplays="" binaryDisplays="" />
+ </Register4>
+ <SourceNavigatorWindow/>
+ <TraceWindow>
+ <Trace wrap="Yes" type="1" enabled="Yes" />
+ </TraceWindow>
+ <Watch1>
+ <Watches active="1" />
+ </Watch1>
+ <Watch2>
+ <Watches active="0" />
+ </Watch2>
+ <Watch3>
+ <Watches active="0" />
+ </Watch3>
+ <Watch4>
+ <Watches active="0" />
+ </Watch4>
+ <Files>
+ <SessionOpenFile useTextEdit="1" useBinaryEdit="0" x="0" debugPath="E:\Dev\FreeRTOS\Demo\msp430_CrossStudio\serial\serial.c" y="205" useHTMLEdit="0" path="E:\Dev\FreeRTOS\Demo\msp430_CrossStudio\serial\serial.c" left="0" selected="0" name="unnamed" top="186" />
+ <SessionOpenFile useTextEdit="1" useBinaryEdit="0" x="0" debugPath="E:\Dev\FreeRTOS\Demo\msp430_CrossStudio\main.c" y="134" useHTMLEdit="0" path="E:\Dev\FreeRTOS\Demo\msp430_CrossStudio\main.c" left="0" selected="0" name="unnamed" top="131" />
+ </Files>
+ <MSP430CrossStudioWindow activeProject="RTOSDemo" ignoreExceptions="" autoConnectTarget="/MSP430 Flash Emulation Tool (MSP-FET430PIF)" debugSearchFileMap="" fileDialogInitialDirectory="E:\Dev\FreeRTOS\Demo\Common\Minimal" fileDialogDefaultFilter="*" debugSearchPath="" buildConfiguration="Debug" />
+</session>
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+ * Creates all the demo application tasks, then starts the scheduler. The WEB\r
+ * documentation provides more details of the demo application tasks.\r
+ * \r
+ * This demo is configured to execute on the ES449 prototyping board from\r
+ * SoftBaugh. The ES449 has a built in LCD display and a single built in user\r
+ * LED. Therefore, in place of flashing an LED, the 'flash' and 'check' tasks\r
+ * toggle '*' characters on the LCD. The left most '*' represents LED 0, the\r
+ * next LED 1, etc.\r
+ *\r
+ * Main. c also creates a task called 'Check'. This only executes every three \r
+ * seconds but has the highest priority so is guaranteed to get processor time. \r
+ * Its main function is to check that all the other tasks are still operational. \r
+ * Each task that does not flash an LED maintains a unique count that is \r
+ * incremented each time the task successfully completes its function. Should \r
+ * any error occur within such a task the count is permanently halted. The \r
+ * 'check' task inspects the count of each task to ensure it has changed since\r
+ * the last time the check task executed. If all the count variables have \r
+ * changed all the tasks are still executing error free, and the check task\r
+ * toggles an LED with a three second period. Should any task contain an error \r
+ * at any time the LED toggle rate will increase to 500ms.\r
+ *\r
+ * Please read the documentation for the MSP430 port available on\r
+ * http://www.FreeRTOS.org.\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdlib.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo application includes. */\r
+#include "partest.h"\r
+#include "flash.h"\r
+#include "integer.h"\r
+#include "comtest2.h"\r
+#include "PollQ.h"\r
+\r
+/* Constants required for hardware setup. */\r
+#define mainALL_BITS_OUTPUT ( ( unsigned portCHAR ) 0xff )\r
+#define mainMAX_FREQUENCY ( ( unsigned portCHAR ) 121 )\r
+\r
+/* Constants that define the LED's used by the various tasks. [in this case\r
+the '*' characters on the LCD represent LED's] */\r
+#define mainCHECK_LED ( 4 )\r
+#define mainCOM_TEST_LED ( 10 )\r
+\r
+/* Demo task priorities. */\r
+#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+\r
+/* Baud rate used by the COM test tasks. */\r
+#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 19200 )\r
+\r
+/* The frequency at which the 'Check' tasks executes. See the comments at the \r
+top of the page. When the system is operating error free the 'Check' task\r
+toggles an LED every three seconds. If an error is discovered in any task the\r
+rate is increased to 500 milliseconds. [in this case the '*' characters on the \r
+LCD represent LED's]*/\r
+#define mainNO_ERROR_CHECK_DELAY ( ( portTickType ) 3000 / portTICK_RATE_MS )\r
+#define mainERROR_CHECK_DELAY ( ( portTickType ) 500 / portTICK_RATE_MS )\r
+\r
+/* The constants used in the calculation. */\r
+#define intgCONST1 ( ( portLONG ) 123 )\r
+#define intgCONST2 ( ( portLONG ) 234567 )\r
+#define intgCONST3 ( ( portLONG ) -3 )\r
+#define intgCONST4 ( ( portLONG ) 7 )\r
+#define intgEXPECTED_ANSWER ( ( ( intgCONST1 + intgCONST2 ) * intgCONST3 ) / intgCONST4 )\r
+\r
+/* \r
+ * The function that implements the Check task. See the comments at the head\r
+ * of the page for implementation details.\r
+ */ \r
+static void vErrorChecks( void *pvParameters );\r
+\r
+/*\r
+ * Called by the Check task. Returns pdPASS if all the other tasks are found\r
+ * to be operating without error - otherwise returns pdFAIL.\r
+ */\r
+static portSHORT prvCheckOtherTasksAreStillRunning( void );\r
+\r
+/* \r
+ * Perform the hardware setup required by the ES449 in order to run the demo\r
+ * application.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+\r
+portBASE_TYPE xLocalError = pdFALSE;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Start the demo application tasks - then start the real time scheduler.\r
+ */\r
+int main( void )\r
+{\r
+ /* Setup the hardware ready for the demo. */\r
+ prvSetupHardware();\r
+ vParTestInitialise();\r
+\r
+ /* Start the standard demo application tasks. */\r
+ vStartLEDFlashTasks( mainLED_TASK_PRIORITY );\r
+ vStartIntegerMathTasks( tskIDLE_PRIORITY );\r
+ vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED - 1 );\r
+ vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
+\r
+ /* Start the 'Check' task which is defined in this file. */\r
+ xTaskCreate( vErrorChecks, ( const signed portCHAR * const ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); \r
+\r
+ /* Start the scheduler. */\r
+ vTaskStartScheduler();\r
+\r
+ /* As the scheduler has been started the demo applications tasks will be\r
+ executing and we should never get here! */\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portTASK_FUNCTION( vErrorChecks, pvParameters )\r
+{\r
+portTickType xDelayPeriod = mainNO_ERROR_CHECK_DELAY;\r
+\r
+ /* Cycle for ever, delaying then checking all the other tasks are still\r
+ operating without error. */\r
+ for( ;; )\r
+ {\r
+ /* Wait until it is time to check again. The time we wait here depends\r
+ on whether an error has been detected or not. When an error is \r
+ detected the time is shortened resulting in a faster LED flash rate. */\r
+ vTaskDelay( xDelayPeriod );\r
+\r
+ /* See if the other tasks are all ok. */\r
+ if( prvCheckOtherTasksAreStillRunning() != pdPASS )\r
+ {\r
+ /* An error occurred in one of the tasks so shorten the delay \r
+ period - which has the effect of increasing the frequency of the\r
+ LED toggle. */\r
+ xDelayPeriod = mainERROR_CHECK_DELAY;\r
+ }\r
+\r
+ /* Flash! */\r
+ vParTestToggleLED( mainCHECK_LED );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portSHORT prvCheckOtherTasksAreStillRunning( void )\r
+{\r
+static portSHORT sNoErrorFound = pdTRUE;\r
+\r
+ /* The demo tasks maintain a count that increments every cycle of the task\r
+ provided that the task has never encountered an error. This function \r
+ checks the counts maintained by the tasks to ensure they are still being\r
+ incremented. A count remaining at the same value between calls therefore\r
+ indicates that an error has been detected. Only tasks that do not flash\r
+ an LED are checked. */\r
+\r
+ if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ sNoErrorFound = pdFALSE;\r
+ }\r
+\r
+ if( xAreComTestTasksStillRunning() != pdTRUE )\r
+ {\r
+ sNoErrorFound = pdFALSE;\r
+ }\r
+\r
+ if( xArePollingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ sNoErrorFound = pdFALSE;\r
+ }\r
+\r
+ if( xLocalError == pdTRUE )\r
+ {\r
+ sNoErrorFound = pdFALSE;\r
+ }\r
+ \r
+ return sNoErrorFound;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+ /* Stop the watchdog. */\r
+ WDTCTL = WDTPW + WDTHOLD;\r
+\r
+ /* Setup DCO+ for ( xtal * D * (N + 1) ) operation. */\r
+ FLL_CTL0 |= DCOPLUS + XCAP18PF; \r
+\r
+ /* X2 DCO frequency, 8MHz nominal DCO */\r
+ SCFI0 |= FN_4; \r
+\r
+ /* (121+1) x 32768 x 2 = 7.99 Mhz */\r
+ SCFQCTL = mainMAX_FREQUENCY;\r
+\r
+ /* Setup the IO. This is just copied from the demo supplied by SoftBaugh\r
+ for the ES449 demo board. */\r
+ P1SEL = 0x32;\r
+ P2SEL = 0x00;\r
+ P3SEL = 0x00;\r
+ P4SEL = 0xFC;\r
+ P5SEL = 0xFF;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The idle hook is just a copy of the standard integer maths tasks. See\r
+Demo/Common/integer.c for rationale. */\r
+\r
+void vApplicationIdleHook( void ) __toplevel\r
+{\r
+/* These variables are all effectively set to constants so they are volatile to\r
+ensure the compiler does not just get rid of them. */\r
+volatile portLONG lValue;\r
+volatile signed portBASE_TYPE *pxTaskHasExecuted;\r
+\r
+ /* Keep performing a calculation and checking the result against a constant. */\r
+ for( ;; )\r
+ {\r
+ /* Perform the calculation. This will store partial value in\r
+ registers, resulting in a good test of the context switch mechanism. */\r
+ lValue = intgCONST1;\r
+ lValue += intgCONST2;\r
+\r
+ /* Yield in case cooperative scheduling is being used. */\r
+ #if configUSE_PREEMPTION == 0\r
+ {\r
+ taskYIELD();\r
+ }\r
+ #endif\r
+\r
+ /* Finish off the calculation. */\r
+ lValue *= intgCONST3;\r
+ lValue /= intgCONST4;\r
+\r
+ /* If the calculation is found to be incorrect we stop setting the \r
+ TaskHasExecuted variable so the check task can see an error has \r
+ occurred. */\r
+ if( lValue != intgEXPECTED_ANSWER ) /*lint !e774 volatile used to prevent this being optimised out. */\r
+ {\r
+ /* Don't bother with mutual exclusion - it is only read from the\r
+ check task and never written. */\r
+ xLocalError = pdTRUE;\r
+ }\r
+ /* Yield in case cooperative scheduling is being used. */\r
+ #if configUSE_PREEMPTION == 0\r
+ {\r
+ taskYIELD();\r
+ }\r
+ #endif\r
+ }\r
+}\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+\r
+/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER. \r
+ * \r
+ * This file only supports UART 1\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdlib.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "queue.h"\r
+#include "task.h"\r
+\r
+/* Demo application includes. */\r
+#include "serial.h"\r
+\r
+/* Constants required to setup the hardware. */\r
+#define serTX_AND_RX ( ( unsigned portCHAR ) 0x03 )\r
+\r
+/* Misc. constants. */\r
+#define serNO_BLOCK ( ( portTickType ) 0 )\r
+\r
+/* Enable the UART Tx interrupt. */\r
+#define vInterruptOn() IFG2 |= UTXIFG1\r
+\r
+/* The queue used to hold received characters. */\r
+static xQueueHandle xRxedChars; \r
+\r
+/* The queue used to hold characters waiting transmission. */\r
+static xQueueHandle xCharsForTx; \r
+\r
+static volatile portSHORT sTHREEmpty;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )\r
+{\r
+unsigned portLONG ulBaudRateCount;\r
+\r
+ /* Initialise the hardware. */\r
+\r
+ /* Generate the baud rate constants for the wanted baud rate. */\r
+ ulBaudRateCount = configCPU_CLOCK_HZ / ulWantedBaud;\r
+\r
+ portENTER_CRITICAL();\r
+ {\r
+ /* Create the queues used by the com test task. */\r
+ xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );\r
+ xCharsForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );\r
+\r
+ /* Reset UART. */\r
+ UCTL1 |= SWRST;\r
+\r
+ /* Set pin function. */\r
+ P4SEL |= serTX_AND_RX;\r
+\r
+ /* All other bits remain at zero for n, 8, 1 interrupt driven operation. \r
+ LOOPBACK MODE!*/\r
+ U1CTL |= CHAR + LISTEN;\r
+ U1TCTL |= SSEL1;\r
+\r
+ /* Setup baud rate low byte. */\r
+ U1BR0 = ( unsigned portCHAR ) ( ulBaudRateCount & ( unsigned portLONG ) 0xff );\r
+\r
+ /* Setup baud rate high byte. */\r
+ ulBaudRateCount >>= 8UL;\r
+ U1BR1 = ( unsigned portCHAR ) ( ulBaudRateCount & ( unsigned portLONG ) 0xff );\r
+\r
+ /* Enable ports. */\r
+ ME2 |= UTXE1 + URXE1;\r
+\r
+ /* Set. */\r
+ UCTL1 &= ~SWRST;\r
+\r
+ /* Nothing in the buffer yet. */\r
+ sTHREEmpty = pdTRUE;\r
+\r
+ /* Enable interrupts. */\r
+ IE2 |= URXIE1 + UTXIE1;\r
+ }\r
+ portEXIT_CRITICAL();\r
+ \r
+ /* Unlike other ports, this serial code does not allow for more than one\r
+ com port. We therefore don't return a pointer to a port structure and can\r
+ instead just return NULL. */\r
+ return NULL;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )\r
+{\r
+ /* Get the next character from the buffer. Return false if no characters\r
+ are available, or arrive before xBlockTime expires. */\r
+ if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )\r
+ {\r
+ return pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ return pdFALSE;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )\r
+{\r
+signed portBASE_TYPE xReturn;\r
+\r
+ /* Transmit a character. */\r
+\r
+ portENTER_CRITICAL();\r
+ {\r
+ if( sTHREEmpty == pdTRUE )\r
+ {\r
+ /* If sTHREEmpty is true then the UART Tx ISR has indicated that \r
+ there are no characters queued to be transmitted - so we can\r
+ write the character directly to the shift Tx register. */\r
+ sTHREEmpty = pdFALSE;\r
+ U1TXBUF = cOutChar;\r
+ xReturn = pdPASS;\r
+ }\r
+ else\r
+ {\r
+ /* sTHREEmpty is false, so there are still characters waiting to be\r
+ transmitted. We have to queue this character so it gets \r
+ transmitted in turn. */\r
+\r
+ /* Return false if after the block time there is no room on the Tx \r
+ queue. It is ok to block inside a critical section as each task\r
+ maintains it's own critical section status. */\r
+ xReturn = xQueueSend( xCharsForTx, &cOutChar, xBlockTime );\r
+\r
+ /* Depending on queue sizing and task prioritisation: While we \r
+ were blocked waiting to post on the queue interrupts were not \r
+ disabled. It is possible that the serial ISR has emptied the \r
+ Tx queue, in which case we need to start the Tx off again\r
+ writing directly to the Tx register. */\r
+ if( ( sTHREEmpty == pdTRUE ) && ( xReturn == pdPASS ) )\r
+ {\r
+ /* Get back the character we just posted. */\r
+ xQueueReceive( xCharsForTx, &cOutChar, serNO_BLOCK );\r
+ sTHREEmpty = pdFALSE;\r
+ U1TXBUF = cOutChar;\r
+ }\r
+ }\r
+ }\r
+ portEXIT_CRITICAL();\r
+\r
+ return pdPASS;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#ifdef MSP_ROWLEY_RB_PORT\r
+\r
+/* Serial interrupt service routines for the RB port. */\r
+\r
+ /*\r
+ * UART RX interrupt service routine.\r
+ */\r
+ void vRxISR( void ) __interrupt[ UART1RX_VECTOR ]\r
+ {\r
+ signed portCHAR cChar;\r
+ \r
+ /* Get the character from the UART and post it on the queue of Rxed \r
+ characters. */\r
+ cChar = U1RXBUF;\r
+ \r
+ if( xQueueSendFromISR( xRxedChars, &cChar, pdFALSE ) )\r
+ {\r
+ /*If the post causes a task to wake force a context switch \r
+ as the woken task may have a higher priority than the task we have \r
+ interrupted. */\r
+ taskYIELD();\r
+ }\r
+ }\r
+ /*-----------------------------------------------------------*/\r
+ \r
+ /*\r
+ * UART Tx interrupt service routine.\r
+ */\r
+ void vTxISR( void ) __interrupt[ UART1TX_VECTOR ]\r
+ {\r
+ signed portCHAR cChar;\r
+ portBASE_TYPE xTaskWoken;\r
+ \r
+ /* The previous character has been transmitted. See if there are any\r
+ further characters waiting transmission. */\r
+ \r
+ if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWoken ) == pdTRUE )\r
+ {\r
+ /* There was another character queued - transmit it now. */\r
+ U1TXBUF = cChar;\r
+ }\r
+ else\r
+ {\r
+ /* There were no other characters to transmit. */\r
+ sTHREEmpty = pdTRUE;\r
+ }\r
+ }\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#ifdef MSP_ROWLEY_MP_PORT\r
+\r
+/* Serial port interrupts for the alternative port code. */\r
+\r
+ void ISRCom1Rx( void )\r
+ {\r
+ signed portCHAR cChar;\r
+ \r
+ /* Get the character from the UART and post it on the queue of Rxed \r
+ characters. */\r
+ cChar = U1RXBUF;\r
+ \r
+ if( xQueueSendFromISR( xRxedChars, &cChar, pdFALSE ) )\r
+ {\r
+ /*If the post causes a task to wake force a context switch \r
+ as the woken task may have a higher priority than the task we have \r
+ interrupted. */\r
+ portEXIT_SWITCHING_ISR( pdTRUE );\r
+ }\r
+ }\r
+ /*-----------------------------------------------------------*/\r
+ \r
+ void ISRCom1Tx( void )\r
+ {\r
+ signed portCHAR cChar;\r
+ portBASE_TYPE xTaskWoken;\r
+ \r
+ /* The previous character has been transmitted. See if there are any\r
+ further characters waiting transmission. */\r
+ \r
+ if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWoken ) == pdTRUE )\r
+ {\r
+ /* There was another character queued - transmit it now. */\r
+ U1TXBUF = cChar;\r
+ }\r
+ else\r
+ {\r
+ /* There were no other characters to transmit. */\r
+ sTHREEmpty = pdTRUE;\r
+ }\r
+ }\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+#include <msp430x44x.h>\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. \r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 7995392 ) /* Clock setup from main.c in the demo application. */\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 4 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 50 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1800 ) )\r
+#define configMAX_TASK_NAME_LEN ( 8 )\r
+#define configUSE_TRACE_FACILITY 0\r
+#define configUSE_16_BIT_TICKS 1\r
+#define configIDLE_SHOULD_YIELD 1\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet 0\r
+#define INCLUDE_uxTaskPriorityGet 0\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 0\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Characters on the LCD are used to simulate LED's. In this case the 'ParTest'\r
+ * is really operating on the LCD display.\r
+ *-----------------------------------------------------------*/\r
+\r
+/*\r
+ * This demo is configured to execute on the ES449 prototyping board from\r
+ * SoftBaugh. The ES449 has a built in LCD display and a single built in user\r
+ * LED. Therefore, in place of flashing an LED, the 'flash' and 'check' tasks\r
+ * toggle '*' characters on the LCD. The left most '*' represents LED 0, the\r
+ * next LED 1, etc.\r
+ *\r
+ * There is a single genuine on board LED referenced as LED 10.\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <signal.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo application includes. */\r
+#include "partest.h"\r
+\r
+/* Constants required to setup the LCD. */\r
+#define LCD_DIV_64 5\r
+\r
+/* Constants required to access the "LED's". The LED segments are turned on\r
+and off to generate '*' characters. */\r
+#define partstNUM_LEDS ( ( unsigned portCHAR ) 6 )\r
+#define partstSEGMENTS_ON ( ( unsigned portCHAR ) 0x0f )\r
+#define partstSEGMENTS_OFF ( ( unsigned portCHAR ) 0x00 )\r
+\r
+/* The LED number of the real on board LED, rather than a simulated LED. */\r
+#define partstON_BOARD_LED ( ( unsigned portBASE_TYPE ) 10 )\r
+#define mainON_BOARD_LED_BIT ( ( unsigned portCHAR ) 0x01 )\r
+\r
+/* The LCD segments used to generate the '*' characters for LED's 0 to 5. */\r
+unsigned portCHAR * const ucRHSSegments[ partstNUM_LEDS ] = { ( unsigned portCHAR * )0xa4, \r
+ ( unsigned portCHAR * )0xa2, \r
+ ( unsigned portCHAR * )0xa0, \r
+ ( unsigned portCHAR * )0x9e,\r
+ ( unsigned portCHAR * )0x9c,\r
+ ( unsigned portCHAR * )0x9a };\r
+\r
+unsigned portCHAR * const ucLHSSegments[ partstNUM_LEDS ] = { ( unsigned portCHAR * )0xa3, \r
+ ( unsigned portCHAR * )0xa1, \r
+ ( unsigned portCHAR * )0x9f, \r
+ ( unsigned portCHAR * )0x9d,\r
+ ( unsigned portCHAR * )0x9b,\r
+ ( unsigned portCHAR * )0x99 };\r
+\r
+/*\r
+ * Toggle the single genuine built in LED.\r
+ */\r
+static void prvToggleOnBoardLED( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestInitialise( void )\r
+{\r
+ /* Initialise the LCD hardware. */\r
+\r
+ /* Used for the onboard LED. */\r
+ P1DIR = 0x01;\r
+\r
+ // Setup Basic Timer for LCD operation\r
+ BTCTL = (LCD_DIV_64+0x23);\r
+\r
+ // Setup port functions\r
+ P1SEL = 0x32;\r
+ P2SEL = 0x00;\r
+ P3SEL = 0x00;\r
+ P4SEL = 0xFC;\r
+ P5SEL = 0xFF;\r
+ \r
+ /* Initialise all segments to off. */\r
+ LCDM1 = partstSEGMENTS_OFF; \r
+ LCDM2 = partstSEGMENTS_OFF; \r
+ LCDM3 = partstSEGMENTS_OFF; \r
+ LCDM4 = partstSEGMENTS_OFF; \r
+ LCDM5 = partstSEGMENTS_OFF; \r
+ LCDM6 = partstSEGMENTS_OFF; \r
+ LCDM7 = partstSEGMENTS_OFF; \r
+ LCDM8 = partstSEGMENTS_OFF; \r
+ LCDM9 = partstSEGMENTS_OFF; \r
+ LCDM10 = partstSEGMENTS_OFF; \r
+ LCDM11 = partstSEGMENTS_OFF; \r
+ LCDM12 = partstSEGMENTS_OFF; \r
+ LCDM13 = partstSEGMENTS_OFF; \r
+ LCDM14 = partstSEGMENTS_OFF; \r
+ LCDM15 = partstSEGMENTS_OFF; \r
+ LCDM16 = partstSEGMENTS_OFF; \r
+ LCDM17 = partstSEGMENTS_OFF; \r
+ LCDM18 = partstSEGMENTS_OFF; \r
+ LCDM19 = partstSEGMENTS_OFF; \r
+ LCDM20 = partstSEGMENTS_OFF; \r
+\r
+ /* Setup LCD control. */\r
+ LCDCTL = (LCDSG0_7|LCD4MUX|LCDON);\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )\r
+{\r
+ /* Set or clear the output [in this case show or hide the '*' character. */\r
+ if( uxLED < ( portBASE_TYPE ) partstNUM_LEDS )\r
+ {\r
+ vTaskSuspendAll();\r
+ {\r
+ if( xValue )\r
+ {\r
+ /* Turn on the segments required to show the '*'. */\r
+ *( ucRHSSegments[ uxLED ] ) = partstSEGMENTS_ON;\r
+ *( ucLHSSegments[ uxLED ] ) = partstSEGMENTS_ON;\r
+ }\r
+ else\r
+ {\r
+ /* Turn off all the segments. */\r
+ *( ucRHSSegments[ uxLED ] ) = partstSEGMENTS_OFF;\r
+ *( ucLHSSegments[ uxLED ] ) = partstSEGMENTS_OFF;\r
+ }\r
+ }\r
+ xTaskResumeAll();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+ if( uxLED < ( portBASE_TYPE ) partstNUM_LEDS )\r
+ {\r
+ vTaskSuspendAll();\r
+ {\r
+ /* If the '*' is already showing - hide it. If it is not already\r
+ showing then show it. */\r
+ if( *( ucRHSSegments[ uxLED ] ) )\r
+ {\r
+ *( ucRHSSegments[ uxLED ] ) = partstSEGMENTS_OFF;\r
+ *( ucLHSSegments[ uxLED ] ) = partstSEGMENTS_OFF;\r
+ }\r
+ else\r
+ {\r
+ *( ucRHSSegments[ uxLED ] ) = partstSEGMENTS_ON;\r
+ *( ucLHSSegments[ uxLED ] ) = partstSEGMENTS_ON;\r
+ }\r
+ }\r
+ xTaskResumeAll();\r
+ }\r
+ else\r
+ {\r
+ if( uxLED == partstON_BOARD_LED )\r
+ {\r
+ /* The request related to the genuine on board LED. */\r
+ prvToggleOnBoardLED();\r
+ }\r
+ } \r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvToggleOnBoardLED( void )\r
+{\r
+static unsigned portSHORT sState = pdFALSE;\r
+\r
+ /* Toggle the state of the single genuine on board LED. */\r
+ if( sState ) \r
+ {\r
+ P1OUT |= mainON_BOARD_LED_BIT;\r
+ }\r
+ else\r
+ {\r
+ P1OUT &= ~mainON_BOARD_LED_BIT;\r
+ }\r
+\r
+ sState = !sState;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
--- /dev/null
+target remote localhost:3333\r
+kill\r
+target remote localhost:3333\r
+b main\r
+c\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+ * Creates all the demo application tasks, then starts the scheduler. The WEB\r
+ * documentation provides more details of the demo application tasks.\r
+ * \r
+ * This demo is configured to execute on the ES449 prototyping board from\r
+ * SoftBaugh. The ES449 has a built in LCD display and a single built in user\r
+ * LED. Therefore, in place of flashing an LED, the 'flash' and 'check' tasks\r
+ * toggle '*' characters on the LCD. The left most '*' represents LED 0, the\r
+ * next LED 1, etc.\r
+ *\r
+ * Main. c also creates a task called 'Check'. This only executes every three \r
+ * seconds but has the highest priority so is guaranteed to get processor time. \r
+ * Its main function is to check that all the other tasks are still operational. \r
+ * Each task that does not flash an LED maintains a unique count that is \r
+ * incremented each time the task successfully completes its function. Should \r
+ * any error occur within such a task the count is permanently halted. The \r
+ * 'check' task inspects the count of each task to ensure it has changed since\r
+ * the last time the check task executed. If all the count variables have \r
+ * changed all the tasks are still executing error free, and the check task\r
+ * toggles an LED with a three second period. Should any task contain an error \r
+ * at any time the LED toggle rate will increase to 500ms.\r
+ *\r
+ * Please read the documentation for the MSP430 port available on\r
+ * http://www.FreeRTOS.org.\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdlib.h>\r
+#include <signal.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo application includes. */\r
+#include "partest.h"\r
+#include "flash.h"\r
+#include "integer.h"\r
+#include "comtest2.h"\r
+#include "PollQ.h"\r
+\r
+/* Constants required for hardware setup. */\r
+#define mainALL_BITS_OUTPUT ( ( unsigned portCHAR ) 0xff )\r
+#define mainMAX_FREQUENCY ( ( unsigned portCHAR ) 121 )\r
+\r
+/* Constants that define the LED's used by the various tasks. [in this case\r
+the '*' characters on the LCD represent LED's] */\r
+#define mainCHECK_LED ( 4 )\r
+#define mainCOM_TEST_LED ( 10 )\r
+\r
+/* Demo task priorities. */\r
+#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+\r
+/* Baud rate used by the COM test tasks. */\r
+#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 19200 )\r
+\r
+/* The frequency at which the 'Check' tasks executes. See the comments at the \r
+top of the page. When the system is operating error free the 'Check' task\r
+toggles an LED every three seconds. If an error is discovered in any task the\r
+rate is increased to 500 milliseconds. [in this case the '*' characters on the \r
+LCD represent LED's]*/\r
+#define mainNO_ERROR_CHECK_DELAY ( ( portTickType ) 3000 / portTICK_RATE_MS )\r
+#define mainERROR_CHECK_DELAY ( ( portTickType ) 500 / portTICK_RATE_MS )\r
+\r
+/* \r
+ * The function that implements the Check task. See the comments at the head\r
+ * of the page for implementation details.\r
+ */ \r
+static void vErrorChecks( void *pvParameters );\r
+\r
+/*\r
+ * Called by the Check task. Returns pdPASS if all the other tasks are found\r
+ * to be operating without error - otherwise returns pdFAIL.\r
+ */\r
+static portSHORT prvCheckOtherTasksAreStillRunning( void );\r
+\r
+/* \r
+ * Perform the hardware setup required by the ES449 in order to run the demo\r
+ * application.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Start the demo application tasks - then start the real time scheduler.\r
+ */\r
+int main( void )\r
+{\r
+ /* Setup the hardware ready for the demo. */\r
+ prvSetupHardware();\r
+ vParTestInitialise();\r
+\r
+ /* Start the standard demo application tasks. */\r
+ vStartLEDFlashTasks( mainLED_TASK_PRIORITY );\r
+ vStartIntegerMathTasks( tskIDLE_PRIORITY );\r
+ vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED - 1 );\r
+ vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
+\r
+ /* Start the 'Check' task which is defined in this file. */\r
+ xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); \r
+\r
+ /* Start the scheduler. */\r
+ vTaskStartScheduler();\r
+\r
+ /* As the scheduler has been started the demo applications tasks will be\r
+ executing and we should never get here! */\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vErrorChecks( void *pvParameters )\r
+{\r
+static volatile unsigned portLONG ulDummyVariable = 3UL;\r
+portTickType xDelayPeriod = mainNO_ERROR_CHECK_DELAY;\r
+\r
+ /* Cycle for ever, delaying then checking all the other tasks are still\r
+ operating without error. */\r
+ for( ;; )\r
+ {\r
+ /* Wait until it is time to check again. The time we wait here depends\r
+ on whether an error has been detected or not. When an error is \r
+ detected the time is shortened resulting in a faster LED flash rate. */\r
+ vTaskDelay( xDelayPeriod );\r
+\r
+ /* Perform a bit of 32bit maths to ensure the registers used by the \r
+ integer tasks get some exercise outside of the integer tasks \r
+ themselves. The result here is not important we are just deliberately\r
+ changing registers used by other tasks to ensure that their context\r
+ switch is operating as required. - see the demo application \r
+ documentation for more info. */\r
+ ulDummyVariable *= 3UL;\r
+ \r
+ /* See if the other tasks are all ok. */\r
+ if( prvCheckOtherTasksAreStillRunning() != pdPASS )\r
+ {\r
+ /* An error occurred in one of the tasks so shorten the delay \r
+ period - which has the effect of increasing the frequency of the\r
+ LED toggle. */\r
+ xDelayPeriod = mainERROR_CHECK_DELAY;\r
+ }\r
+\r
+ /* Flash! */\r
+ vParTestToggleLED( mainCHECK_LED );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portSHORT prvCheckOtherTasksAreStillRunning( void )\r
+{\r
+static portSHORT sNoErrorFound = pdTRUE;\r
+\r
+ /* The demo tasks maintain a count that increments every cycle of the task\r
+ provided that the task has never encountered an error. This function \r
+ checks the counts maintained by the tasks to ensure they are still being\r
+ incremented. A count remaining at the same value between calls therefore\r
+ indicates that an error has been detected. Only tasks that do not flash\r
+ an LED are checked. */\r
+\r
+ if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ sNoErrorFound = pdFALSE;\r
+ }\r
+\r
+ if( xAreComTestTasksStillRunning() != pdTRUE )\r
+ {\r
+ sNoErrorFound = pdFALSE;\r
+ }\r
+ \r
+ if( xArePollingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ sNoErrorFound = pdFALSE;\r
+ }\r
+ \r
+ return sNoErrorFound;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+ /* Stop the watchdog. */\r
+ WDTCTL = WDTPW + WDTHOLD;\r
+\r
+ /* Setup DCO+ for ( xtal * D * (N + 1) ) operation. */\r
+ FLL_CTL0 |= DCOPLUS + XCAP18PF; \r
+\r
+ /* X2 DCO frequency, 8MHz nominal DCO */\r
+ SCFI0 |= FN_4; \r
+\r
+ /* (121+1) x 32768 x 2 = 7.99 Mhz */\r
+ SCFQCTL = mainMAX_FREQUENCY;\r
+\r
+ /* Setup the IO as per the SoftBaugh demo for the same target hardware. */\r
+ P1SEL = 0x32;\r
+ P2SEL = 0x00;\r
+ P3SEL = 0x00;\r
+ P4SEL = 0xFC;\r
+ P5SEL = 0xFF;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+# FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+#\r
+# This file is part of the FreeRTOS distribution.\r
+#\r
+# FreeRTOS is free software; you can redistribute it and/or modify\r
+# it under the terms of the GNU General Public License as published by\r
+# the Free Software Foundation; either version 2 of the License, or\r
+# (at your option) any later version.\r
+#\r
+# FreeRTOS is distributed in the hope that it will be useful,\r
+# but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+# GNU General Public License for more details.\r
+#\r
+# You should have received a copy of the GNU General Public License\r
+# along with FreeRTOS; if not, write to the Free Software\r
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+#\r
+# A special exception to the GPL can be applied should you wish to distribute\r
+# a combined work that includes FreeRTOS, without being obliged to provide\r
+# the source code for any proprietary components. See the licensing section \r
+# of http://www.FreeRTOS.org for full details of how and when the exception\r
+# can be applied.\r
+#\r
+# ***************************************************************************\r
+# See http://www.FreeRTOS.org for documentation, latest information, license \r
+# and contact details. Please ensure to read the configuration and relevant \r
+# port sections of the online documentation.\r
+# ***************************************************************************\r
+\r
+\r
+CC=msp430-gcc\r
+OBJCOPY=msp430-objcopy\r
+DEBUG=-g\r
+OPT=-Os\r
+WARNINGS=-Wall -Wshadow -Wpointer-arith -Wbad-function-cast -Wcast-align -Wsign-compare \\r
+ -Waggregate-return -Wstrict-prototypes -Wmissing-prototypes -Wmissing-declarations -Wunused\r
+\r
+CFLAGS=-mmcu=msp430x449 $(OPT) $(DEBUG) -I. -I../../Source/include -I../Common/include -DGCC_MSP430 $(WARNINGS)\r
+\r
+# Setup paths to source code\r
+SOURCE_PATH = ../../Source\r
+PORT_PATH = ../../Source/portable/GCC/MSP430F449\r
+DEMO_PATH = ../Common/Minimal\r
+\r
+#\r
+# Source files that can be built to THUMB mode.\r
+#\r
+SRC = \\r
+main.c \\r
+ParTest/ParTest.c \\r
+serial/serial.c \\r
+$(SOURCE_PATH)/tasks.c \\r
+$(SOURCE_PATH)/list.c \\r
+$(SOURCE_PATH)/queue.c \\r
+$(SOURCE_PATH)/portable/MemMang/heap_1.c \\r
+$(PORT_PATH)/port.c \\r
+$(DEMO_PATH)/flash.c \\r
+$(DEMO_PATH)/integer.c \\r
+$(DEMO_PATH)/comtest.c \\r
+$(DEMO_PATH)/PollQ.c\r
+\r
+#\r
+# Define all object files.\r
+#\r
+OBJ = $(SRC:.c=.o)\r
+\r
+a.out : $(OBJ) makefile\r
+ $(CC) $(OBJ) $(CFLAGS)\r
+\r
+$(OBJ) : %.o : %.c makefile\r
+ $(CC) -c $(CFLAGS) $< -o $@ \r
+ \r
+clean :\r
+ touch makefile\r
+ \r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+ \r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+\r
+/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER. \r
+ * \r
+ * This file only supports UART 1\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdlib.h>\r
+#include <signal.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "queue.h"\r
+#include "task.h"\r
+\r
+/* Demo application includes. */\r
+#include "serial.h"\r
+\r
+/* Constants required to setup the hardware. */\r
+#define serTX_AND_RX ( ( unsigned portCHAR ) 0x03 )\r
+\r
+/* Misc. constants. */\r
+#define serNO_BLOCK ( ( portTickType ) 0 )\r
+\r
+/* Enable the UART Tx interrupt. */\r
+#define vInterruptOn() IFG2 |= UTXIFG1\r
+\r
+/* The queue used to hold received characters. */\r
+static xQueueHandle xRxedChars; \r
+\r
+/* The queue used to hold characters waiting transmission. */\r
+static xQueueHandle xCharsForTx; \r
+\r
+static volatile portSHORT sTHREEmpty;\r
+\r
+/* Interrupt service routines. */\r
+interrupt (UART1RX_VECTOR) vRxISR( void );\r
+interrupt (UART1TX_VECTOR) vTxISR( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )\r
+{\r
+unsigned portLONG ulBaudRateCount;\r
+\r
+ /* Initialise the hardware. */\r
+\r
+ /* Generate the baud rate constants for the wanted baud rate. */\r
+ ulBaudRateCount = configCPU_CLOCK_HZ / ulWantedBaud;\r
+\r
+ portENTER_CRITICAL();\r
+ {\r
+ /* Create the queues used by the com test task. */\r
+ xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );\r
+ xCharsForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );\r
+\r
+ /* Reset UART. */\r
+ UCTL1 |= SWRST;\r
+\r
+ /* Set pin function. */\r
+ P4SEL |= serTX_AND_RX;\r
+\r
+ /* All other bits remain at zero for n, 8, 1 interrupt driven operation. \r
+ LOOPBACK MODE!*/\r
+ U1CTL |= CHAR + LISTEN;\r
+ U1TCTL |= SSEL1;\r
+\r
+ /* Setup baud rate low byte. */\r
+ U1BR0 = ( unsigned portCHAR ) ( ulBaudRateCount & ( unsigned portLONG ) 0xff );\r
+\r
+ /* Setup baud rate high byte. */\r
+ ulBaudRateCount >>= 8UL;\r
+ U1BR1 = ( unsigned portCHAR ) ( ulBaudRateCount & ( unsigned portLONG ) 0xff );\r
+\r
+ /* Enable ports. */\r
+ ME2 |= UTXE1 + URXE1;\r
+\r
+ /* Set. */\r
+ UCTL1 &= ~SWRST;\r
+\r
+ /* Nothing in the buffer yet. */\r
+ sTHREEmpty = pdTRUE;\r
+\r
+ /* Enable interrupts. */\r
+ IE2 |= URXIE1 + UTXIE1;\r
+ }\r
+ portEXIT_CRITICAL();\r
+ \r
+ /* Unlike other ports, this serial code does not allow for more than one\r
+ com port. We therefore don't return a pointer to a port structure and can\r
+ instead just return NULL. */\r
+ return NULL;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )\r
+{\r
+ /* Get the next character from the buffer. Return false if no characters\r
+ are available, or arrive before xBlockTime expires. */\r
+ if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )\r
+ {\r
+ return pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ return pdFALSE;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )\r
+{\r
+signed portBASE_TYPE xReturn;\r
+\r
+ /* Transmit a character. */\r
+\r
+ portENTER_CRITICAL();\r
+ {\r
+ if( sTHREEmpty == pdTRUE )\r
+ {\r
+ /* If sTHREEmpty is true then the UART Tx ISR has indicated that \r
+ there are no characters queued to be transmitted - so we can\r
+ write the character directly to the shift Tx register. */\r
+ sTHREEmpty = pdFALSE;\r
+ U1TXBUF = cOutChar;\r
+ xReturn = pdPASS;\r
+ }\r
+ else\r
+ {\r
+ /* sTHREEmpty is false, so there are still characters waiting to be\r
+ transmitted. We have to queue this character so it gets \r
+ transmitted in turn. */\r
+\r
+ /* Return false if after the block time there is no room on the Tx \r
+ queue. It is ok to block inside a critical section as each task\r
+ maintains it's own critical section status. */\r
+ xReturn = xQueueSend( xCharsForTx, &cOutChar, xBlockTime );\r
+\r
+ /* Depending on queue sizing and task prioritisation: While we \r
+ were blocked waiting to post on the queue interrupts were not \r
+ disabled. It is possible that the serial ISR has emptied the \r
+ Tx queue, in which case we need to start the Tx off again\r
+ writing directly to the Tx register. */\r
+ if( ( sTHREEmpty == pdTRUE ) && ( xReturn == pdPASS ) )\r
+ {\r
+ /* Get back the character we just posted. */\r
+ xQueueReceive( xCharsForTx, &cOutChar, serNO_BLOCK );\r
+ sTHREEmpty = pdFALSE;\r
+ U1TXBUF = cOutChar;\r
+ }\r
+ }\r
+ }\r
+ portEXIT_CRITICAL();\r
+\r
+ return pdPASS;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * UART RX interrupt service routine.\r
+ */\r
+interrupt (UART1RX_VECTOR) vRxISR( void )\r
+{\r
+signed portCHAR cChar;\r
+\r
+ /* Get the character from the UART and post it on the queue of Rxed \r
+ characters. */\r
+ cChar = U1RXBUF;\r
+\r
+ if( xQueueSendFromISR( xRxedChars, &cChar, pdFALSE ) )\r
+ {\r
+ /*If the post causes a task to wake force a context switch \r
+ as the woken task may have a higher priority than the task we have \r
+ interrupted. */\r
+ taskYIELD();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * UART Tx interrupt service routine.\r
+ */\r
+interrupt (UART1TX_VECTOR) vTxISR( void )\r
+{\r
+signed portCHAR cChar;\r
+portBASE_TYPE xTaskWoken;\r
+\r
+ /* The previous character has been transmitted. See if there are any\r
+ further characters waiting transmission. */\r
+\r
+ if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWoken ) == pdTRUE )\r
+ {\r
+ /* There was another character queued - transmit it now. */\r
+ U1TXBUF = cChar;\r
+ }\r
+ else\r
+ {\r
+ /* There were no other characters to transmit. */\r
+ sTHREEmpty = pdTRUE;\r
+ }\r
+}\r
+\r
--- /dev/null
+Each RTOS port has a demo application to demonstrate it's use.\r
+\r
++ The Demo/Common directory contains the demo application files as described on \r
+the http://www.FreeRTOS.org WEB site. Each file creates one or more tasks.\r
+The files in the Demo/Common directory are used by every demo application for\r
+every port.\r
+\r
++ All the other directories contain a project or makefile for the demo\r
+application targeted at a particular microcontroller. \r
+\r
+\r
+For example, if you are interested in the ATMega323 demo application for\r
+the WinAVR tools then the AVR_ATMega323_WinAVR directory contains the \r
+relevant makefile. The makefile includes files from the Demo/ATMega323 \r
+and the Demo/Common directories. If this is the only port you are \r
+interested in then all the other directories can be ignored.\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+ RSEG ICODE:CODE\r
+ CODE32\r
+\r
+ EXTERN vEMACISR\r
+ PUBLIC vEMACISREntry\r
+\r
+; Wrapper for the EMAC interrupt service routine. This can cause a\r
+; context switch so requires an assembly wrapper.\r
+\r
+; Defines the portSAVE_CONTEXT and portRESTORE_CONTEXT macros.\r
+#include "ISR_Support.h"\r
+\r
+vEMACISREntry:\r
+\r
+ portSAVE_CONTEXT ; Save the context of the current task.\r
+\r
+ bl vEMACISR ; Call the ISR routine.\r
+\r
+ portRESTORE_CONTEXT ; Restore the context of the current task -\r
+ ; which may be different to the task that\r
+ ; was interrupted.\r
+\r
+ END\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+ * Basic interrupt driven driver for the EMAC peripheral. This driver is not\r
+ * reentrant as with uIP the buffers are only ever accessed from a single task.\r
+ *\r
+ * The simple buffer management used within uIP allows the EMAC driver to also\r
+ * be simplistic. The driver contained within the lwIP demo is more\r
+ * comprehensive.\r
+ */\r
+\r
+\r
+/*\r
+Changes from V3.2.2\r
+\r
+ + Corrected the byte order when writing the MAC address to the MAC.\r
+ + Support added for MII interfaces. Previously only RMII was supported.\r
+\r
+Changes from V3.2.3\r
+\r
+ + The MII interface is now the default.\r
+ + Modified the initialisation sequence slightly to allow auto init more\r
+ time to complete.\r
+\r
+Changes from V3.2.4\r
+\r
+ + Also read the EMAC_RSR register in the EMAC ISR as a work around the \r
+ the EMAC bug that can reset the RX bit in EMAC_ISR register before the\r
+ bit has been read.\r
+*/\r
+\r
+/* Standard includes. */\r
+#include <string.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "semphr.h"\r
+#include "task.h"\r
+\r
+/* uIP includes. */\r
+#include "uip.h"\r
+\r
+/* Hardware specific includes. */\r
+#include "emac.h"\r
+#include "mii.h"\r
+\r
+\r
+/* USE_RMII_INTERFACE must be defined as 1 to use an RMII interface, or 0\r
+to use an MII interface. */\r
+#define USE_RMII_INTERFACE 0\r
+\r
+/* The buffer addresses written into the descriptors must be aligned so the\r
+last few bits are zero. These bits have special meaning for the EMAC\r
+peripheral and cannot be used as part of the address. */\r
+#define emacADDRESS_MASK ( ( unsigned portLONG ) 0xFFFFFFFC )\r
+\r
+/* Bit used within the address stored in the descriptor to mark the last\r
+descriptor in the array. */\r
+#define emacRX_WRAP_BIT ( ( unsigned portLONG ) 0x02 )\r
+\r
+/* Bit used within the Tx descriptor status to indicate whether the\r
+descriptor is under the control of the EMAC or the software. */\r
+#define emacTX_BUF_USED ( ( unsigned portLONG ) 0x80000000 )\r
+\r
+/* A short delay is used to wait for a buffer to become available, should\r
+one not be immediately available when trying to transmit a frame. */\r
+#define emacBUFFER_WAIT_DELAY ( 2 )\r
+#define emacMAX_WAIT_CYCLES ( configTICK_RATE_HZ / 40 )\r
+\r
+/* Misc defines. */\r
+#define emacINTERRUPT_LEVEL ( 5 )\r
+#define emacNO_DELAY ( 0 )\r
+#define emacTOTAL_FRAME_HEADER_SIZE ( 54 )\r
+#define emacPHY_INIT_DELAY ( 5000 / portTICK_RATE_MS )\r
+#define emacRESET_KEY ( ( unsigned portLONG ) 0xA5000000 )\r
+#define emacRESET_LENGTH ( ( unsigned portLONG ) ( 0x01 << 8 ) )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Prototype for the EMAC interrupt asm wrapper.\r
+ */\r
+extern void vEMACISREntry( void );\r
+\r
+/*\r
+ * Prototype for the EMAC interrupt function - called by the asm wrapper.\r
+ */\r
+__arm void vEMACISR( void );\r
+\r
+/*\r
+ * Initialise both the Tx and Rx descriptors used by the EMAC.\r
+ */\r
+static void prvSetupDescriptors(void);\r
+\r
+/*\r
+ * Write our MAC address into the EMAC. The MAC address is set as one of the\r
+ * uip options.\r
+ */\r
+static void prvSetupMACAddress( void );\r
+\r
+/*\r
+ * Configure the EMAC and AIC for EMAC interrupts.\r
+ */\r
+static void prvSetupEMACInterrupt( void );\r
+\r
+/*\r
+ * Some initialisation functions taken from the Atmel EMAC sample code.\r
+ */\r
+static void vReadPHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG *pulValue );\r
+#if USE_RMII_INTERFACE != 1\r
+ static void vWritePHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG ulValue);\r
+#endif\r
+static portBASE_TYPE xGetLinkSpeed( void );\r
+static portBASE_TYPE prvProbePHY( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Buffer written to by the EMAC DMA. Must be aligned as described by the\r
+comment above the emacADDRESS_MASK definition. */\r
+#pragma data_alignment=8\r
+static volatile portCHAR pcRxBuffer[ NB_RX_BUFFERS * ETH_RX_BUFFER_SIZE ];\r
+\r
+/* Buffer read by the EMAC DMA. Must be aligned as described by he comment\r
+above the emacADDRESS_MASK definition. */\r
+#pragma data_alignment=8\r
+static portCHAR pcTxBuffer[ NB_TX_BUFFERS * ETH_TX_BUFFER_SIZE ];\r
+\r
+/* Descriptors used to communicate between the program and the EMAC peripheral.\r
+These descriptors hold the locations and state of the Rx and Tx buffers. */\r
+static volatile AT91S_TxTdDescriptor xTxDescriptors[ NB_TX_BUFFERS ];\r
+static volatile AT91S_RxTdDescriptor xRxDescriptors[ NB_RX_BUFFERS ];\r
+\r
+/* The IP and Ethernet addresses are read from the uIP setup. */\r
+const portCHAR cMACAddress[ 6 ] = { UIP_ETHADDR0, UIP_ETHADDR1, UIP_ETHADDR2, UIP_ETHADDR3, UIP_ETHADDR4, UIP_ETHADDR5 };\r
+const unsigned char ucIPAddress[ 4 ] = { UIP_IPADDR0, UIP_IPADDR1, UIP_IPADDR2, UIP_IPADDR3 };\r
+\r
+/* The semaphore used by the EMAC ISR to wake the EMAC task. */\r
+static xSemaphoreHandle xSemaphore = NULL;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+xSemaphoreHandle xEMACInit( void )\r
+{\r
+ /* Code supplied by Atmel (modified) --------------------*/\r
+\r
+ /* disable pull up on RXDV => PHY normal mode (not in test mode),\r
+ PHY has internal pull down. */\r
+ AT91C_BASE_PIOB->PIO_PPUDR = 1 << 15;\r
+\r
+ #if USE_RMII_INTERFACE != 1\r
+ /* PHY has internal pull down : set MII mode. */\r
+ AT91C_BASE_PIOB->PIO_PPUDR= 1 << 16;\r
+ #endif\r
+\r
+ /* clear PB18 <=> PHY powerdown. */\r
+ AT91F_PIO_CfgOutput( AT91C_BASE_PIOB, 1 << 18 ) ;\r
+ AT91F_PIO_ClearOutput( AT91C_BASE_PIOB, 1 << 18) ;\r
+\r
+ /* After PHY power up, hardware reset. */\r
+ AT91C_BASE_RSTC->RSTC_RMR = emacRESET_KEY | emacRESET_LENGTH;\r
+ AT91C_BASE_RSTC->RSTC_RCR = emacRESET_KEY | AT91C_RSTC_EXTRST;\r
+ \r
+ /* Wait for hardware reset end. */\r
+ while( !( AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL ) )\r
+ {\r
+ __asm( "NOP" );\r
+ }\r
+ __asm( "NOP" );\r
+ \r
+ /* EMAC IO init for EMAC-PHY com. Remove EF100 config. */\r
+ AT91F_EMAC_CfgPIO();\r
+\r
+ /* Enable com between EMAC PHY.\r
+\r
+ Enable management port. */\r
+ AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE; \r
+\r
+ /* MDC = MCK/32. */\r
+ AT91C_BASE_EMAC->EMAC_NCFGR |= ( 2 ) << 10; \r
+\r
+ /* Wait for PHY auto init end (rather crude delay!). */\r
+ vTaskDelay( emacPHY_INIT_DELAY );\r
+\r
+ /* PHY configuration. */\r
+ #if USE_RMII_INTERFACE != 1\r
+ {\r
+ unsigned portLONG ulControl;\r
+\r
+ /* PHY has internal pull down : disable MII isolate. */\r
+ vReadPHY( AT91C_PHY_ADDR, MII_BMCR, &ulControl );\r
+ vReadPHY( AT91C_PHY_ADDR, MII_BMCR, &ulControl );\r
+ ulControl &= ~BMCR_ISOLATE;\r
+ vWritePHY( AT91C_PHY_ADDR, MII_BMCR, ulControl );\r
+ }\r
+ #endif\r
+\r
+ /* Disable management port again. */\r
+ AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;\r
+\r
+ #if USE_RMII_INTERFACE != 1\r
+ /* Enable EMAC in MII mode, enable clock ERXCK and ETXCK. */\r
+ AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_CLKEN ;\r
+ #else\r
+ /* Enable EMAC in RMII mode, enable RMII clock (50MHz from oscillator\r
+ on ERFCK). */\r
+ AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_RMII | AT91C_EMAC_CLKEN ;\r
+ #endif\r
+\r
+ /* End of code supplied by Atmel ------------------------*/\r
+\r
+ /* Setup the buffers and descriptors. */\r
+ prvSetupDescriptors();\r
+ \r
+ /* Load our MAC address into the EMAC. */\r
+ prvSetupMACAddress();\r
+\r
+ /* Try to connect. */\r
+ if( prvProbePHY() )\r
+ {\r
+ /* Enable the interrupt! */\r
+ prvSetupEMACInterrupt();\r
+ }\r
+\r
+ return xSemaphore;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portLONG lEMACSend( void )\r
+{\r
+static unsigned portBASE_TYPE uxTxBufferIndex = 0;\r
+portBASE_TYPE xWaitCycles = 0;\r
+portLONG lReturn = pdPASS;\r
+portCHAR *pcBuffer;\r
+\r
+ /* Is a buffer available? */\r
+ while( !( xTxDescriptors[ uxTxBufferIndex ].U_Status.status & AT91C_TRANSMIT_OK ) )\r
+ {\r
+ /* There is no room to write the Tx data to the Tx buffer. Wait a\r
+ short while, then try again. */\r
+ xWaitCycles++;\r
+ if( xWaitCycles > emacMAX_WAIT_CYCLES )\r
+ {\r
+ /* Give up. */\r
+ lReturn = pdFAIL;\r
+ break;\r
+ }\r
+ else\r
+ {\r
+ vTaskDelay( emacBUFFER_WAIT_DELAY );\r
+ }\r
+ }\r
+\r
+ /* lReturn will only be pdPASS if a buffer is available. */\r
+ if( lReturn == pdPASS )\r
+ {\r
+ /* Copy the headers into the Tx buffer. These will be in the uIP buffer. */\r
+ pcBuffer = ( portCHAR * ) xTxDescriptors[ uxTxBufferIndex ].addr;\r
+ memcpy( ( void * ) pcBuffer, ( void * ) uip_buf, emacTOTAL_FRAME_HEADER_SIZE );\r
+\r
+ /* If there is room, also copy in the application data if any. */\r
+ if( ( uip_len > emacTOTAL_FRAME_HEADER_SIZE ) && ( uip_len <= ( ETH_TX_BUFFER_SIZE - emacTOTAL_FRAME_HEADER_SIZE ) ) )\r
+ {\r
+ memcpy( ( void * ) &( pcBuffer[ emacTOTAL_FRAME_HEADER_SIZE ] ), ( void * ) uip_appdata, ( uip_len - emacTOTAL_FRAME_HEADER_SIZE ) );\r
+ }\r
+\r
+ /* Send. */ \r
+ portENTER_CRITICAL();\r
+ {\r
+ if( uxTxBufferIndex >= ( NB_TX_BUFFERS - 1 ) )\r
+ {\r
+ /* Fill out the necessary in the descriptor to get the data sent. */\r
+ xTxDescriptors[ uxTxBufferIndex ].U_Status.status = ( uip_len & ( unsigned portLONG ) AT91C_LENGTH_FRAME )\r
+ | AT91C_LAST_BUFFER\r
+ | AT91C_TRANSMIT_WRAP;\r
+ uxTxBufferIndex = 0;\r
+ }\r
+ else\r
+ {\r
+ /* Fill out the necessary in the descriptor to get the data sent. */\r
+ xTxDescriptors[ uxTxBufferIndex ].U_Status.status = ( uip_len & ( unsigned portLONG ) AT91C_LENGTH_FRAME )\r
+ | AT91C_LAST_BUFFER;\r
+ uxTxBufferIndex++;\r
+ }\r
+ \r
+ AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TSTART;\r
+ }\r
+ portEXIT_CRITICAL();\r
+ }\r
+\r
+ return lReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+unsigned portLONG ulEMACPoll( void )\r
+{\r
+static unsigned portBASE_TYPE ulNextRxBuffer = 0;\r
+unsigned portLONG ulSectionLength = 0, ulLengthSoFar = 0, ulEOF = pdFALSE;\r
+portCHAR *pcSource;\r
+\r
+ /* Skip any fragments. */\r
+ while( ( xRxDescriptors[ ulNextRxBuffer ].addr & AT91C_OWNERSHIP_BIT ) && !( xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AT91C_SOF ) )\r
+ {\r
+ /* Mark the buffer as free again. */\r
+ xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT ); \r
+ ulNextRxBuffer++;\r
+ if( ulNextRxBuffer >= NB_RX_BUFFERS )\r
+ {\r
+ ulNextRxBuffer = 0;\r
+ }\r
+ }\r
+\r
+ /* Is there a packet ready? */\r
+\r
+ while( ( xRxDescriptors[ ulNextRxBuffer ].addr & AT91C_OWNERSHIP_BIT ) && !ulSectionLength )\r
+ {\r
+ pcSource = ( portCHAR * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK );\r
+ ulSectionLength = xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AT91C_LENGTH_FRAME;\r
+\r
+ if( ulSectionLength == 0 )\r
+ {\r
+ /* The frame is longer than the buffer pointed to by this\r
+ descriptor so copy the entire buffer to uIP - then move onto\r
+ the next descriptor to get the rest of the frame. */\r
+ if( ( ulLengthSoFar + ETH_RX_BUFFER_SIZE ) <= UIP_BUFSIZE )\r
+ {\r
+ memcpy( &( uip_buf[ ulLengthSoFar ] ), pcSource, ETH_RX_BUFFER_SIZE );\r
+ ulLengthSoFar += ETH_RX_BUFFER_SIZE;\r
+ } \r
+ }\r
+ else\r
+ {\r
+ /* This is the last section of the frame. Copy the section to\r
+ uIP. */\r
+ if( ulSectionLength < UIP_BUFSIZE )\r
+ {\r
+ /* The section length holds the length of the entire frame.\r
+ ulLengthSoFar holds the length of the frame sections already\r
+ copied to uIP, so the length of the final section is\r
+ ulSectionLength - ulLengthSoFar; */\r
+ if( ulSectionLength > ulLengthSoFar )\r
+ {\r
+ memcpy( &( uip_buf[ ulLengthSoFar ] ), pcSource, ( ulSectionLength - ulLengthSoFar ) );\r
+ }\r
+ } \r
+\r
+ /* Is this the last buffer for the frame? If not why? */\r
+ ulEOF = xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AT91C_EOF;\r
+ }\r
+\r
+ /* Mark the buffer as free again. */\r
+ xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );\r
+\r
+ /* Increment to the next buffer, wrapping if necessary. */\r
+ ulNextRxBuffer++;\r
+ if( ulNextRxBuffer >= NB_RX_BUFFERS )\r
+ {\r
+ ulNextRxBuffer = 0;\r
+ }\r
+ }\r
+\r
+ /* If we obtained data but for some reason did not find the end of the\r
+ frame then discard the data as it must contain an error. */\r
+ if( !ulEOF )\r
+ {\r
+ ulSectionLength = 0;\r
+ }\r
+\r
+ return ulSectionLength;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupDescriptors(void)\r
+{\r
+unsigned portBASE_TYPE xIndex;\r
+unsigned portLONG ulAddress;\r
+\r
+ /* Initialise xRxDescriptors descriptor. */\r
+ for( xIndex = 0; xIndex < NB_RX_BUFFERS; ++xIndex )\r
+ {\r
+ /* Calculate the address of the nth buffer within the array. */\r
+ ulAddress = ( unsigned portLONG )( pcRxBuffer + ( xIndex * ETH_RX_BUFFER_SIZE ) );\r
+\r
+ /* Write the buffer address into the descriptor. The DMA will place\r
+ the data at this address when this descriptor is being used. Mask off\r
+ the bottom bits of the address as these have special meaning. */\r
+ xRxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK;\r
+ } \r
+\r
+ /* The last buffer has the wrap bit set so the EMAC knows to wrap back\r
+ to the first buffer. */\r
+ xRxDescriptors[ NB_RX_BUFFERS - 1 ].addr |= emacRX_WRAP_BIT;\r
+\r
+ /* Initialise xTxDescriptors. */\r
+ for( xIndex = 0; xIndex < NB_TX_BUFFERS; ++xIndex )\r
+ {\r
+ /* Calculate the address of the nth buffer within the array. */\r
+ ulAddress = ( unsigned portLONG )( pcTxBuffer + ( xIndex * ETH_TX_BUFFER_SIZE ) );\r
+\r
+ /* Write the buffer address into the descriptor. The DMA will read\r
+ data from here when the descriptor is being used. */\r
+ xTxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK;\r
+ xTxDescriptors[ xIndex ].U_Status.status = AT91C_TRANSMIT_OK;\r
+ } \r
+\r
+ /* The last buffer has the wrap bit set so the EMAC knows to wrap back\r
+ to the first buffer. */\r
+ xTxDescriptors[ NB_TX_BUFFERS - 1 ].U_Status.status = AT91C_TRANSMIT_WRAP | AT91C_TRANSMIT_OK;\r
+\r
+ /* Tell the EMAC where to find the descriptors. */\r
+ AT91C_BASE_EMAC->EMAC_RBQP = ( unsigned portLONG ) xRxDescriptors;\r
+ AT91C_BASE_EMAC->EMAC_TBQP = ( unsigned portLONG ) xTxDescriptors;\r
+ \r
+ /* Clear all the bits in the receive status register. */\r
+ AT91C_BASE_EMAC->EMAC_RSR = ( AT91C_EMAC_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA );\r
+\r
+ /* Enable the copy of data into the buffers, ignore broadcasts,\r
+ and don't copy FCS. */\r
+ AT91C_BASE_EMAC->EMAC_NCFGR |= ( AT91C_EMAC_CAF | AT91C_EMAC_NBC | AT91C_EMAC_DRFCS);\r
+\r
+ /* Enable Rx and Tx, plus the stats register. */\r
+ AT91C_BASE_EMAC->EMAC_NCR |= ( AT91C_EMAC_TE | AT91C_EMAC_RE | AT91C_EMAC_WESTAT );\r
+} \r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupMACAddress( void )\r
+{\r
+ /* Must be written SA1L then SA1H. */\r
+ AT91C_BASE_EMAC->EMAC_SA1L = ( ( unsigned portLONG ) cMACAddress[ 3 ] << 24 ) |\r
+ ( ( unsigned portLONG ) cMACAddress[ 2 ] << 16 ) |\r
+ ( ( unsigned portLONG ) cMACAddress[ 1 ] << 8 ) |\r
+ cMACAddress[ 0 ];\r
+\r
+ AT91C_BASE_EMAC->EMAC_SA1H = ( ( unsigned portLONG ) cMACAddress[ 5 ] << 8 ) |\r
+ cMACAddress[ 4 ];\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupEMACInterrupt( void )\r
+{\r
+ /* Create the semaphore used to trigger the EMAC task. */\r
+ vSemaphoreCreateBinary( xSemaphore );\r
+ if( xSemaphore )\r
+ {\r
+ /* We start by 'taking' the semaphore so the ISR can 'give' it when the\r
+ first interrupt occurs. */\r
+ xSemaphoreTake( xSemaphore, emacNO_DELAY );\r
+ portENTER_CRITICAL();\r
+ {\r
+ /* We want to interrupt on Rx events. */\r
+ AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_RCOMP;\r
+\r
+ /* Enable the interrupts in the AIC. */\r
+ AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_EMAC, emacINTERRUPT_LEVEL, AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, ( void (*)( void ) ) vEMACISREntry );\r
+ AT91F_AIC_EnableIt( AT91C_BASE_AIC, AT91C_ID_EMAC );\r
+ }\r
+ portEXIT_CRITICAL();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+__arm void vEMACISR( void )\r
+{\r
+volatile unsigned portLONG ulIntStatus, ulRxStatus;\r
+portBASE_TYPE xSwitchRequired = pdFALSE;\r
+\r
+ ulIntStatus = AT91C_BASE_EMAC->EMAC_ISR;\r
+ ulRxStatus = AT91C_BASE_EMAC->EMAC_RSR;\r
+\r
+ if( ( ulIntStatus & AT91C_EMAC_RCOMP ) || ( ulRxStatus & AT91C_EMAC_REC ) )\r
+ {\r
+ /* A frame has been received, signal the uIP task so it can process\r
+ the Rx descriptors. */\r
+ xSwitchRequired = xSemaphoreGiveFromISR( xSemaphore, pdFALSE );\r
+ AT91C_BASE_EMAC->EMAC_RSR = AT91C_EMAC_REC;\r
+ }\r
+\r
+ /* If a task was woken by either a character being received or a character\r
+ being transmitted then we may need to switch to another task. */\r
+ portEND_SWITCHING_ISR( xSwitchRequired );\r
+\r
+ /* Clear the interrupt. */\r
+ AT91C_BASE_AIC->AIC_EOICR = 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+\r
+/*\r
+ * The following functions are initialisation functions taken from the Atmel\r
+ * EMAC sample code.\r
+ */\r
+\r
+static portBASE_TYPE prvProbePHY( void )\r
+{\r
+unsigned portLONG ulPHYId1, ulPHYId2, ulStatus;\r
+portBASE_TYPE xReturn = pdPASS;\r
+ \r
+ /* Code supplied by Atmel (reformatted) -----------------*/\r
+\r
+ /* Enable management port */\r
+ AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE; \r
+ AT91C_BASE_EMAC->EMAC_NCFGR |= ( 2 ) << 10;\r
+\r
+ /* Read the PHY ID. */\r
+ vReadPHY( AT91C_PHY_ADDR, MII_PHYSID1, &ulPHYId1 );\r
+ vReadPHY( AT91C_PHY_ADDR, MII_PHYSID2, &ulPHYId2 );\r
+\r
+ /* AMD AM79C875:\r
+ PHY_ID1 = 0x0022\r
+ PHY_ID2 = 0x5541\r
+ Bits 3:0 Revision Number Four bit manufacturer\92s revision number.\r
+ 0001 stands for Rev. A, etc.\r
+ */\r
+ if( ( ( ulPHYId1 << 16 ) | ( ulPHYId2 & 0xfff0 ) ) != MII_DM9161_ID )\r
+ {\r
+ /* Did not expect this ID. */\r
+ xReturn = pdFAIL;\r
+ }\r
+ else\r
+ {\r
+ ulStatus = xGetLinkSpeed();\r
+\r
+ if( ulStatus != pdPASS )\r
+ {\r
+ xReturn = pdFAIL;\r
+ }\r
+ }\r
+\r
+ /* Disable management port */\r
+ AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE; \r
+\r
+ /* End of code supplied by Atmel ------------------------*/\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vReadPHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG *pulValue )\r
+{\r
+ /* Code supplied by Atmel (reformatted) ----------------------*/\r
+\r
+ AT91C_BASE_EMAC->EMAC_MAN = (AT91C_EMAC_SOF & (0x01<<30))\r
+ | (2 << 16) | (2 << 28)\r
+ | ((ucPHYAddress & 0x1f) << 23)\r
+ | (ucAddress << 18);\r
+\r
+ /* Wait until IDLE bit in Network Status register is cleared. */\r
+ while( !( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE ) )\r
+ {\r
+ __asm( "NOP" );\r
+ }\r
+\r
+ *pulValue = ( AT91C_BASE_EMAC->EMAC_MAN & 0x0000ffff ); \r
+\r
+ /* End of code supplied by Atmel ------------------------*/\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if USE_RMII_INTERFACE != 1\r
+static void vWritePHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG ulValue )\r
+{\r
+ /* Code supplied by Atmel (reformatted) ----------------------*/\r
+\r
+ AT91C_BASE_EMAC->EMAC_MAN = (( AT91C_EMAC_SOF & (0x01<<30))\r
+ | (2 << 16) | (1 << 28)\r
+ | ((ucPHYAddress & 0x1f) << 23)\r
+ | (ucAddress << 18))\r
+ | (ulValue & 0xffff);\r
+\r
+ /* Wait until IDLE bit in Network Status register is cleared */\r
+ while( !( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE ) )\r
+ {\r
+ __asm( "NOP" );\r
+ };\r
+\r
+ /* End of code supplied by Atmel ------------------------*/\r
+}\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+static portBASE_TYPE xGetLinkSpeed( void )\r
+{\r
+ unsigned portLONG ulBMSR, ulBMCR, ulLPA, ulMACCfg, ulSpeed, ulDuplex;\r
+\r
+ /* Code supplied by Atmel (reformatted) -----------------*/\r
+\r
+ /* Link status is latched, so read twice to get current value */\r
+ vReadPHY(AT91C_PHY_ADDR, MII_BMSR, &ulBMSR);\r
+ vReadPHY(AT91C_PHY_ADDR, MII_BMSR, &ulBMSR);\r
+\r
+ if( !( ulBMSR & BMSR_LSTATUS ) )\r
+ { \r
+ /* No Link. */\r
+ return pdFAIL;\r
+ }\r
+\r
+ vReadPHY(AT91C_PHY_ADDR, MII_BMCR, &ulBMCR);\r
+ if (ulBMCR & BMCR_ANENABLE)\r
+ { \r
+ /* AutoNegotiation is enabled. */\r
+ if (!(ulBMSR & BMSR_ANEGCOMPLETE))\r
+ {\r
+ /* Auto-negotiation in progress. */\r
+ return pdFAIL; \r
+ } \r
+\r
+ vReadPHY(AT91C_PHY_ADDR, MII_LPA, &ulLPA);\r
+ if( ( ulLPA & LPA_100FULL ) || ( ulLPA & LPA_100HALF ) )\r
+ {\r
+ ulSpeed = SPEED_100;\r
+ }\r
+ else\r
+ {\r
+ ulSpeed = SPEED_10;\r
+ }\r
+\r
+ if( ( ulLPA & LPA_100FULL ) || ( ulLPA & LPA_10FULL ) )\r
+ {\r
+ ulDuplex = DUPLEX_FULL;\r
+ }\r
+ else\r
+ {\r
+ ulDuplex = DUPLEX_HALF;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ ulSpeed = ( ulBMCR & BMCR_SPEED100 ) ? SPEED_100 : SPEED_10;\r
+ ulDuplex = ( ulBMCR & BMCR_FULLDPLX ) ? DUPLEX_FULL : DUPLEX_HALF;\r
+ }\r
+\r
+ /* Update the MAC */\r
+ ulMACCfg = AT91C_BASE_EMAC->EMAC_NCFGR & ~( AT91C_EMAC_SPD | AT91C_EMAC_FD );\r
+ if( ulSpeed == SPEED_100 )\r
+ {\r
+ if( ulDuplex == DUPLEX_FULL )\r
+ {\r
+ /* 100 Full Duplex */\r
+ AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_SPD | AT91C_EMAC_FD;\r
+ }\r
+ else\r
+ { \r
+ /* 100 Half Duplex */\r
+ AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_SPD;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if (ulDuplex == DUPLEX_FULL)\r
+ {\r
+ /* 10 Full Duplex */\r
+ AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_FD;\r
+ }\r
+ else\r
+ {\r
+ /* 10 Half Duplex */\r
+ AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg;\r
+ }\r
+ }\r
+\r
+ /* End of code supplied by Atmel ------------------------*/\r
+\r
+ return pdPASS;\r
+}\r
--- /dev/null
+#ifndef SAM_7_EMAC_H\r
+#define SAM_7_EMAC_H\r
+\r
+\r
+/*\r
+ * Initialise the EMAC driver. If successful a semaphore is returned that\r
+ * is used by the EMAC ISR to indicate that Rx packets have been received.\r
+ * If the initialisation fails then NULL is returned.\r
+ */\r
+xSemaphoreHandle xEMACInit( void );\r
+\r
+/*\r
+ * Send the current uIP buffer. This copies the uIP buffer to one of the\r
+ * EMAC Tx buffers, then indicates to the EMAC that the buffer is ready.\r
+ */\r
+portLONG lEMACSend( void );\r
+\r
+/*\r
+ * Called in response to an EMAC Rx interrupt. Copies the received frame\r
+ * into the uIP buffer.\r
+ */\r
+unsigned portLONG ulEMACPoll( void );\r
+\r
+#endif\r
--- /dev/null
+This is an internal working file generated by the Source Browser.\r
+09:28 06s\r
+C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\BlockQ.pbi\r
+C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\Cstartup_SAM7.pbi\r
+C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\ParTest.pbi\r
+C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\PollQ.pbi\r
+C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\SAM7_EMAC.pbi\r
+C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\cgi.pbi\r
+C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\death.pbi\r
+C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\dynamic.pbi\r
+C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\flash.pbi\r
+C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\flop.pbi\r
+C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\fs.pbi\r
+C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\heap_2.pbi\r
+C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\httpd.pbi\r
+C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\integer.pbi\r
+C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\list.pbi\r
+C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\main.pbi\r
+C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\port.pbi\r
+C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\queue.pbi\r
+C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\semtest.pbi\r
+C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\tasks.pbi\r
+C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\uIP_Task.pbi\r
+C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\uip.pbi\r
+C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\uip_arch.pbi\r
+C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\uip_arp.pbi\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+#include <intrinsic.h>\r
+#include "board.h"\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 47923200 )\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 100 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) 22000 )\r
+#define configMAX_TASK_NAME_LEN ( 16 )\r
+#define configUSE_TRACE_FACILITY 1\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 0\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#include "FreeRTOS.h"\r
+#include "partest.h"\r
+#include "board.h"\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple parallel port IO routines for the LED's. LED's can be set, cleared\r
+ * or toggled.\r
+ *-----------------------------------------------------------*/\r
+const unsigned portLONG ulLED_MASK[ NB_LED ]= { LED1, LED2, LED3, LED4 };\r
+\r
+void vParTestInitialise( void )\r
+{ \r
+ /* Start with all LED's off. */\r
+ AT91F_PIO_SetOutput( AT91C_BASE_PIOB, LED_MASK ); \r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )\r
+{\r
+ if( uxLED < ( portBASE_TYPE ) NB_LED )\r
+ {\r
+ if( xValue )\r
+ {\r
+ AT91F_PIO_SetOutput( AT91C_BASE_PIOB, ulLED_MASK[ uxLED ] );\r
+ }\r
+ else\r
+ {\r
+ AT91F_PIO_ClearOutput( AT91C_BASE_PIOB, ulLED_MASK[ uxLED ]);\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+ if( uxLED < ( portBASE_TYPE ) NB_LED )\r
+ {\r
+ if( AT91F_PIO_GetInput( AT91C_BASE_PIOB ) & ulLED_MASK[ uxLED ] )\r
+ {\r
+ AT91F_PIO_ClearOutput( AT91C_BASE_PIOB, ulLED_MASK[ uxLED ]);\r
+ }\r
+ else\r
+ {\r
+ AT91F_PIO_SetOutput( AT91C_BASE_PIOB, ulLED_MASK[ uxLED ] ); \r
+ }\r
+ }\r
+}\r
+\r
+\r
--- /dev/null
+/*----------------------------------------------------------------------------\r
+* ATMEL Microcontroller Software Support - ROUSSET -\r
+*----------------------------------------------------------------------------\r
+* The software is delivered "AS IS" without warranty or condition of any\r
+* kind, either express, implied or statutory. This includes without\r
+* limitation any warranty or condition with respect to merchantability or\r
+* fitness for any particular purpose, or against the infringements of\r
+* intellectual property rights of others.\r
+*----------------------------------------------------------------------------\r
+* File Name : Board.h\r
+* Object : AT91SAM7X Evaluation Board Features Definition File.\r
+*\r
+* Creation : JG 20/Jun/2005\r
+*----------------------------------------------------------------------------\r
+*/\r
+#ifndef Board_h\r
+#define Board_h\r
+\r
+#include <AT91SAM7X256.h>\r
+#define __inline inline\r
+#include <lib_AT91SAM7X256.h>\r
+\r
+#define true -1\r
+#define false 0\r
+\r
+/*-------------------------------*/\r
+/* SAM7Board Memories Definition */\r
+/*-------------------------------*/\r
+// The AT91SAM7X128 embeds a 32-Kbyte SRAM bank, and 128K-Byte Flash\r
+\r
+#define FLASH_PAGE_NB 256\r
+#define FLASH_PAGE_SIZE 128\r
+\r
+/*-----------------*/\r
+/* Leds Definition */\r
+/*-----------------*/\r
+#define LED1 (1<<19) // PB19\r
+#define LED2 (1<<20) // PB20\r
+#define LED3 (1<<21) // PB21\r
+#define LED4 (1<<22) // PB22\r
+#define NB_LED 4\r
+\r
+#define LED_MASK (LED1|LED2|LED3|LED4)\r
+\r
+/*-------------------------*/\r
+/* Push Buttons Definition */\r
+/*-------------------------*/\r
+\r
+#define SW1_MASK (1<<21) // PA21\r
+#define SW2_MASK (1<<22) // PA22\r
+#define SW3_MASK (1<<23) // PA23\r
+#define SW4_MASK (1<<24) // PA24\r
+#define SW_MASK (SW1_MASK|SW2_MASK|SW3_MASK|SW4_MASK)\r
+\r
+\r
+#define SW1 (1<<21) // PA21\r
+#define SW2 (1<<22) // PA22\r
+#define SW3 (1<<23) // PA23\r
+#define SW4 (1<<24) // PA24\r
+\r
+/*--------------*/\r
+/* Master Clock */\r
+/*--------------*/\r
+\r
+#define EXT_OC 18432000 // Exetrnal ocilator MAINCK\r
+#define MCK 47923200 // MCK (PLLRC div by 2)\r
+#define MCKKHz (MCK/1000) //\r
+\r
+#endif /* Board_h */\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;- ATMEL Microcontroller Software Support - ROUSSET -\r
+;------------------------------------------------------------------------------\r
+; The software is delivered "AS IS" without warranty or condition of any\r
+; kind, either express, implied or statutory. This includes without\r
+; limitation any warranty or condition with respect to merchantability or\r
+; fitness for any particular purpose, or against the infringements of\r
+; intellectual property rights of others.\r
+;-----------------------------------------------------------------------------\r
+;- File source : Cstartup.s79\r
+;- Object : Generic CStartup for IAR No Use REMAP\r
+;- Compilation flag : None\r
+;-\r
+;- 1.0 15/Jun/04 JPP : Creation\r
+;------------------------------------------------------------------------------\r
+\r
+#include "AT91SAM7X256_inc.h"\r
+\r
+;------------------------------------------------------------------------------\r
+;- Area Definition\r
+;------------------------------------------------------------------------------\r
+\r
+;---------------------------------------------------------------\r
+; ?RESET\r
+; Reset Vector.\r
+; Normally, segment INTVEC is linked at address 0.\r
+; For debugging purposes, INTVEC may be placed at other\r
+; addresses.\r
+; A debugger that honors the entry point will start the\r
+; program in a normal way even if INTVEC is not at address 0.\r
+;-------------------------------------------------------------\r
+\r
+ PROGRAM ?RESET\r
+ RSEG INTRAMSTART_REMAP\r
+ RSEG INTRAMEND_REMAP\r
+\r
+ EXTERN vPortYieldProcessor\r
+\r
+ RSEG ICODE:CODE:ROOT(2)\r
+ CODE32 ; Always ARM mode after reset \r
+ org 0 \r
+reset \r
+;------------------------------------------------------------------------------\r
+;- Exception vectors\r
+;--------------------\r
+;- These vectors can be read at address 0 or at RAM address\r
+;- They ABSOLUTELY requires to be in relative addresssing mode in order to\r
+;- guarantee a valid jump. For the moment, all are just looping.\r
+;- If an exception occurs before remap, this would result in an infinite loop.\r
+;- To ensure if a exeption occurs before start application to infinite loop.\r
+;------------------------------------------------------------------------------\r
+\r
+ B InitReset ; 0x00 Reset handler\r
+undefvec:\r
+ B undefvec ; 0x04 Undefined Instruction\r
+swivec:\r
+ B vPortYieldProcessor ; 0x08 Software Interrupt\r
+pabtvec:\r
+ B pabtvec ; 0x0C Prefetch Abort\r
+dabtvec:\r
+ B dabtvec ; 0x10 Data Abort\r
+rsvdvec:\r
+ B rsvdvec ; 0x14 reserved\r
+irqvec:\r
+ LDR PC, [PC, #-0xF20] ; Jump directly to the address given by the AIC\r
+\r
+fiqvec: ; 0x1c FIQ\r
+\r
+;------------------------------------------------------------------------------\r
+;- Function : FIQ_Handler_Entry\r
+;- Treatments : FIQ Controller Interrupt Handler.\r
+;- Called Functions : AIC_FVR[interrupt]\r
+;------------------------------------------------------------------------------\r
+\r
+FIQ_Handler_Entry:\r
+\r
+;- Switch in SVC/User Mode to allow User Stack access for C code\r
+; because the FIQ is not yet acknowledged\r
+\r
+;- Save and r0 in FIQ_Register\r
+ mov r9,r0\r
+ ldr r0 , [r8, #AIC_FVR]\r
+ msr CPSR_c,#I_BIT | F_BIT | ARM_MODE_SVC\r
+\r
+;- Save scratch/used registers and LR in User Stack\r
+ stmfd sp!, { r1-r3, r12, lr}\r
+\r
+;- Branch to the routine pointed by the AIC_FVR\r
+ mov r14, pc\r
+ bx r0\r
+\r
+;- Restore scratch/used registers and LR from User Stack\r
+ ldmia sp!, { r1-r3, r12, lr}\r
+\r
+;- Leave Interrupts disabled \ 4and switch back in FIQ mode\r
+ msr CPSR_c, #I_BIT | F_BIT | ARM_MODE_FIQ\r
+\r
+;- Restore the R0 ARM_MODE_SVC register\r
+ mov r0,r9\r
+\r
+;- Restore the Program Counter using the LR_fiq directly in the PC\r
+ subs pc,lr,#4\r
+\r
+InitReset:\r
+;------------------------------------------------------------------------------\r
+;- Low level Init (PMC, AIC, ? ....) by C function AT91F_LowLevelInit\r
+;------------------------------------------------------------------------------\r
+ EXTERN AT91F_LowLevelInit\r
+\r
+#define __iramend SFB(INTRAMEND_REMAP)\r
+\r
+;- minumum C initialization\r
+;- call AT91F_LowLevelInit( void)\r
+\r
+ ldr r13,=__iramend ; temporary stack in internal RAM\r
+;--Call Low level init function in ABSOLUTE through the Interworking\r
+ ldr r0,=AT91F_LowLevelInit\r
+ mov lr, pc\r
+ bx r0\r
+;------------------------------------------------------------------------------\r
+;- Stack Sizes Definition\r
+;------------------------\r
+;- Interrupt Stack requires 2 words x 8 priority level x 4 bytes when using\r
+;- the vectoring. This assume that the IRQ management.\r
+;- The Interrupt Stack must be adjusted depending on the interrupt handlers.\r
+;- Fast Interrupt not requires stack If in your application it required you must\r
+;- be definehere.\r
+;- The System stack size is not defined and is limited by the free internal\r
+;- SRAM.\r
+;------------------------------------------------------------------------------\r
+\r
+;------------------------------------------------------------------------------\r
+;- Top of Stack Definition\r
+;-------------------------\r
+;- Interrupt and Supervisor Stack are located at the top of internal memory in\r
+;- order to speed the exception handling context saving and restoring.\r
+;- ARM_MODE_SVC (Application, C) Stack is located at the top of the external memory.\r
+;------------------------------------------------------------------------------\r
+\r
+IRQ_STACK_SIZE EQU 300\r
+\r
+ARM_MODE_FIQ EQU 0x11\r
+ARM_MODE_IRQ EQU 0x12\r
+ARM_MODE_SVC EQU 0x13\r
+\r
+I_BIT EQU 0x80\r
+F_BIT EQU 0x40\r
+\r
+;------------------------------------------------------------------------------\r
+;- Setup the stack for each mode\r
+;-------------------------------\r
+ ldr r0, =__iramend\r
+\r
+;- Set up Fast Interrupt Mode and set FIQ Mode Stack\r
+ msr CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT\r
+;- Init the FIQ register\r
+ ldr r8, =AT91C_BASE_AIC\r
+\r
+;- Set up Interrupt Mode and set IRQ Mode Stack\r
+ msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT\r
+ mov r13, r0 ; Init stack IRQ\r
+ sub r0, r0, #IRQ_STACK_SIZE\r
+\r
+;- Enable interrupt & Set up Supervisor Mode and set Supervisor Mode Stack\r
+ msr CPSR_c, #ARM_MODE_SVC\r
+ mov r13, r0\r
+\r
+\r
+;---------------------------------------------------------------\r
+; ?CSTARTUP\r
+;---------------------------------------------------------------\r
+ EXTERN __segment_init\r
+ EXTERN main\r
+; Initialize segments.\r
+; __segment_init is assumed to use\r
+; instruction set and to be reachable by BL from the ICODE segment\r
+; (it is safest to link them in segment ICODE).\r
+ ldr r0,=__segment_init\r
+ mov lr, pc\r
+ bx r0\r
+\r
+ PUBLIC __main\r
+?jump_to_main:\r
+ ldr lr,=?call_exit\r
+ ldr r0,=main\r
+__main:\r
+ bx r0\r
+\r
+;------------------------------------------------------------------------------\r
+;- Loop for ever\r
+;---------------\r
+;- End of application. Normally, never occur.\r
+;- Could jump on Software Reset ( B 0x0 ).\r
+;------------------------------------------------------------------------------\r
+?call_exit:\r
+End\r
+ b End\r
+\r
+\r
+\r
+;---------------------------------------------------------------\r
+; ?EXEPTION_VECTOR\r
+; This module is only linked if needed for closing files.\r
+;---------------------------------------------------------------\r
+ PUBLIC AT91F_Default_FIQ_handler\r
+ PUBLIC AT91F_Default_IRQ_handler\r
+ PUBLIC AT91F_Spurious_handler\r
+\r
+ CODE32 ; Always ARM mode after exeption \r
+\r
+AT91F_Default_FIQ_handler\r
+ b AT91F_Default_FIQ_handler\r
+\r
+AT91F_Default_IRQ_handler\r
+ b AT91F_Default_IRQ_handler\r
+\r
+AT91F_Spurious_handler\r
+ b AT91F_Spurious_handler\r
+\r
+ ENDMOD\r
+\r
+ END\r
+\r
--- /dev/null
+//*----------------------------------------------------------------------------\r
+//* ATMEL Microcontroller Software Support - ROUSSET -\r
+//*----------------------------------------------------------------------------\r
+//* The software is delivered "AS IS" without warranty or condition of any\r
+//* kind, either express, implied or statutory. This includes without\r
+//* limitation any warranty or condition with respect to merchantability or\r
+//* fitness for any particular purpose, or against the infringements of\r
+//* intellectual property rights of others.\r
+//*----------------------------------------------------------------------------\r
+//* File Name : Cstartup_SAM7.c\r
+//* Object : Low level initializations written in C for IAR\r
+//* tools\r
+//* 1.0 08/Sep/04 JPP : Creation\r
+//* 1.10 10/Sep/04 JPP : Update AT91C_CKGR_PLLCOUNT filed\r
+//*----------------------------------------------------------------------------\r
+\r
+\r
+// Include the board file description\r
+#include "Board.h"\r
+//#include "init.h"\r
+#include <string.h>\r
+\r
+// The following functions must be write in ARM mode this function called directly\r
+// by exception vector\r
+extern void AT91F_Spurious_handler(void);\r
+extern void AT91F_Default_IRQ_handler(void);\r
+extern void AT91F_Default_FIQ_handler(void);\r
+\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_LowLevelInit\r
+//* \brief This function performs very low level HW initialization\r
+//* this function can be use a Stack, depending the compilation\r
+//* optimization mode\r
+//*----------------------------------------------------------------------------\r
+void AT91F_LowLevelInit( void);\r
+void AT91F_LowLevelInit( void ) @ "ICODE"\r
+{\r
+ int i;\r
+ AT91PS_PMC pPMC = AT91C_BASE_PMC;\r
+\r
+ //* Set Flash Waite sate\r
+ // Single Cycle Access at Up to 30 MHz, or 40\r
+ // if MCK = 47923200 I have 50 Cycle for 1 useconde ( flied MC_FMR->FMCN\r
+ AT91C_BASE_MC->MC_FMR = ((AT91C_MC_FMCN)&(75 <<16)) | AT91C_MC_FWS_1FWS ;\r
+\r
+ //* Watchdog Disable\r
+ AT91C_BASE_WDTC->WDTC_WDMR= AT91C_WDTC_WDDIS;\r
+\r
+ \r
+ // If we are running off a j-link then the PLL will have already been setup.\r
+ if( !( pPMC->PMC_MCKR & AT91C_PMC_CSS_PLL_CLK ) )\r
+ {\r
+ //* Set MCK at 47 923 200\r
+ // 1 Enabling the Main Oscillator:\r
+ // SCK = 1/32768 = 30.51 uSeconde\r
+ // Start up time = 8 * 6 / SCK = 56 * 30.51 = 1,46484375 ms\r
+ pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) | AT91C_CKGR_MOSCEN ));\r
+ // Wait the startup time\r
+ while(!(pPMC->PMC_SR & AT91C_PMC_MOSCS));\r
+ // 2 Checking the Main Oscillator Frequency (Optional)\r
+ // 3 Setting PLL and divider:\r
+ // - div by 5 Fin = 3,6864 =(18,432 / 5)\r
+ // - Mul 25+1: Fout = 95,8464 =(3,6864 *26)\r
+ // for 96 MHz the erroe is 0.16%\r
+ //eld out NOT USED = 0 Fi\r
+ pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 5) |\r
+ (AT91C_CKGR_PLLCOUNT & (28<<8)) |\r
+ (AT91C_CKGR_MUL & (25<<16)));\r
+\r
+ // Wait the startup time\r
+ while(!(pPMC->PMC_SR & AT91C_PMC_LOCK));\r
+ // 4. Selection of Master Clock and Processor Clock\r
+ // select the PLL clock divided by 2\r
+\r
+ pPMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2 ;\r
+ while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));\r
+\r
+ \r
+ pPMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK ;\r
+ while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));\r
+ } \r
+ \r
+ // Set up the default interrupts handler vectors\r
+ AT91C_BASE_AIC->AIC_SVR[0] = (int) AT91F_Default_FIQ_handler ;\r
+ for (i=1;i < 31; i++)\r
+ {\r
+ AT91C_BASE_AIC->AIC_SVR[i] = (int) AT91F_Default_IRQ_handler ;\r
+ }\r
+ AT91C_BASE_AIC->AIC_SPU = (int) AT91F_Spurious_handler ;\r
+}\r
+\r
+\r
+\r
--- /dev/null
+//*----------------------------------------------------------------------------\r
+//* ATMEL Microcontroller Software Support - ROUSSET -\r
+//*----------------------------------------------------------------------------\r
+//* The software is delivered "AS IS" without warranty or condition of any\r
+//* kind, either express, implied or statutory. This includes without\r
+//* limitation any warranty or condition with respect to merchantability or\r
+//* fitness for any particular purpose, or against the infringements of\r
+//* intellectual property rights of others.\r
+//*----------------------------------------------------------------------------\r
+//* File Name : Emac.h\r
+//* Object : Emac header file\r
+//* Creation : Hi 11/18/2002\r
+//*\r
+//*----------------------------------------------------------------------------\r
+#ifndef AT91C_EMAC_H\r
+#define AT91C_EMAC_H\r
+\r
+\r
+//* Allows to display all IP header in the main.c\r
+//* If not defined, only ICMP packets are displayed\r
+#define AT91C_DISPLAY_ALL_IPHEADER 0\r
+\r
+#define NB_RX_BUFFERS 25 //* Number of receive buffers\r
+#define ETH_RX_BUFFER_SIZE 128 //*\r
+\r
+#define NB_TX_BUFFERS 2 //* Number of Transmit buffers\r
+#define ETH_TX_BUFFER_SIZE UIP_BUFSIZE //*\r
+\r
+#define AT91C_NO_IPPACKET 0\r
+#define AT91C_IPPACKET 1\r
+\r
+#define ARP_REQUEST 0x0001\r
+#define ARP_REPLY 0x0002\r
+#define PROT_ARP 0x0806\r
+#define PROT_IP 0x0800\r
+#define PROT_ICMP 0x01\r
+#define ICMP_ECHO_REQUEST 0x08\r
+#define ICMP_ECHO_REPLY 0x00\r
+\r
+#define AT91C_EMAC_CLKEN 0x2\r
+#define SWAP16(x) (((x & 0xff) << 8) | (x >> 8))\r
+\r
+#if 0\r
+//* Transfer descriptor structure\r
+typedef struct _AT91S_TdDescriptor {\r
+ unsigned int addr;\r
+ unsigned int status;\r
+}AT91S_TdDescriptor, *AT91PS_TdDescriptor;\r
+#endif\r
+\r
+//* Receive Transfer descriptor structure\r
+typedef struct _AT91S_RxTdDescriptor {\r
+ unsigned int addr;\r
+ union\r
+ {\r
+ unsigned int status;\r
+ struct {\r
+ unsigned int Length:11;\r
+ unsigned int Res0:1;\r
+ unsigned int Rxbuf_off:2;\r
+ unsigned int StartOfFrame:1;\r
+ unsigned int EndOfFrame:1;\r
+ unsigned int Cfi:1;\r
+ unsigned int VlanPriority:3;\r
+ unsigned int PriorityTag:1;\r
+ unsigned int VlanTag:1;\r
+ unsigned int TypeID:1;\r
+ unsigned int Sa4Match:1;\r
+ unsigned int Sa3Match:1;\r
+ unsigned int Sa2Match:1;\r
+ unsigned int Sa1Match:1;\r
+ unsigned int Res1:1;\r
+ unsigned int ExternalAdd:1;\r
+ unsigned int UniCast:1;\r
+ unsigned int MultiCast:1;\r
+ unsigned int BroadCast:1;\r
+ }S_Status; \r
+ }U_Status;\r
+}AT91S_RxTdDescriptor, *AT91PS_RxTdDescriptor;\r
+\r
+\r
+//* Transmit Transfer descriptor structure\r
+typedef struct _AT91S_TxTdDescriptor {\r
+ unsigned int addr;\r
+ union\r
+ {\r
+ unsigned int status;\r
+ struct {\r
+ unsigned int Length:11;\r
+ unsigned int Res0:4;\r
+ unsigned int LastBuff:1;\r
+ unsigned int NoCrc:1;\r
+ unsigned int Res1:10;\r
+ unsigned int BufExhausted:1;\r
+ unsigned int TransmitUnderrun:1;\r
+ unsigned int TransmitError:1;\r
+ unsigned int Wrap:1;\r
+ unsigned int BuffUsed:1;\r
+ }S_Status; \r
+ }U_Status;\r
+}AT91S_TxTdDescriptor, *AT91PS_TxTdDescriptor;\r
+\r
+#define AT91C_OWNERSHIP_BIT 0x00000001\r
+\r
+/* Receive status defintion */\r
+#define AT91C_BROADCAST_ADDR ((unsigned int) (1 << 31)) //* Broadcat address detected\r
+#define AT91C_MULTICAST_HASH ((unsigned int) (1 << 30)) //* MultiCast hash match\r
+#define AT91C_UNICAST_HASH ((unsigned int) (1 << 29)) //* UniCast hash match\r
+#define AT91C_EXTERNAL_ADDR ((unsigned int) (1 << 28)) //* External Address match\r
+#define AT91C_SA1_ADDR ((unsigned int) (1 << 26)) //* Specific address 1 match\r
+#define AT91C_SA2_ADDR ((unsigned int) (1 << 25)) //* Specific address 2 match\r
+#define AT91C_SA3_ADDR ((unsigned int) (1 << 24)) //* Specific address 3 match\r
+#define AT91C_SA4_ADDR ((unsigned int) (1 << 23)) //* Specific address 4 match\r
+#define AT91C_TYPE_ID ((unsigned int) (1 << 22)) //* Type ID match\r
+#define AT91C_VLAN_TAG ((unsigned int) (1 << 21)) //* VLAN tag detected\r
+#define AT91C_PRIORITY_TAG ((unsigned int) (1 << 20)) //* PRIORITY tag detected\r
+#define AT91C_VLAN_PRIORITY ((unsigned int) (7 << 17)) //* PRIORITY Mask\r
+#define AT91C_CFI_IND ((unsigned int) (1 << 16)) //* CFI indicator\r
+#define AT91C_EOF ((unsigned int) (1 << 15)) //* EOF\r
+#define AT91C_SOF ((unsigned int) (1 << 14)) //* SOF\r
+#define AT91C_RBF_OFFSET ((unsigned int) (3 << 12)) //* Receive Buffer Offset Mask\r
+#define AT91C_LENGTH_FRAME ((unsigned int) 0x07FF) //* Length of frame\r
+\r
+/* Transmit Status definition */\r
+#define AT91C_TRANSMIT_OK ((unsigned int) (1 << 31)) //*\r
+#define AT91C_TRANSMIT_WRAP ((unsigned int) (1 << 30)) //* Wrap bit: mark the last descriptor\r
+#define AT91C_TRANSMIT_ERR ((unsigned int) (1 << 29)) //* RLE:transmit error\r
+#define AT91C_TRANSMIT_UND ((unsigned int) (1 << 28)) //* Transmit Underrun\r
+#define AT91C_BUF_EX ((unsigned int) (1 << 27)) //* Buffers exhausted in mid frame\r
+#define AT91C_TRANSMIT_NO_CRC ((unsigned int) (1 << 16)) //* No CRC will be appended to the current frame\r
+#define AT91C_LAST_BUFFER ((unsigned int) (1 << 15)) //*\r
+\r
+#define ARP_ETHER 1 /* Ethernet hardware address */\r
+#define ARPOP_REQUEST 1 /* Request to resolve address */\r
+#define ARPOP_REPLY 2 /* Response to previous request */\r
+#define RARPOP_REQUEST 3 /* Request to resolve address */\r
+#define RARPOP_REPLY 4 /* Response to previous request */\r
+\r
+\r
+typedef struct _AT91S_EthHdr\r
+{\r
+ unsigned char et_dest[6]; /* Destination node */\r
+ unsigned char et_src[6]; /* Source node */\r
+ unsigned short et_protlen; /* Protocol or length */\r
+} AT91S_EthHdr, *AT91PS_EthHdr;\r
+\r
+typedef struct _AT91S_ArpHdr\r
+{\r
+ unsigned short ar_hrd; /* Format of hardware address */\r
+ unsigned short ar_pro; /* Format of protocol address */\r
+ unsigned char ar_hln; /* Length of hardware address */\r
+ unsigned char ar_pln; /* Length of protocol address */\r
+ unsigned short ar_op; /* Operation */\r
+ unsigned char ar_sha[6]; /* Sender hardware address */\r
+ unsigned char ar_spa[4]; /* Sender protocol address */\r
+ unsigned char ar_tha[6]; /* Target hardware address */\r
+ unsigned char ar_tpa[4]; /* Target protocol address */\r
+} AT91S_ArpHdr, *AT91PS_ArpHdr;\r
+\r
+//* IP Header structure\r
+typedef struct _AT91S_IPheader {\r
+ unsigned char ip_hl_v; /* header length and version */\r
+ unsigned char ip_tos; /* type of service */\r
+ unsigned short ip_len; /* total length */\r
+ unsigned short ip_id; /* identification */\r
+ unsigned short ip_off; /* fragment offset field */\r
+ unsigned char ip_ttl; /* time to live */\r
+ unsigned char ip_p; /* protocol */\r
+ unsigned short ip_sum; /* checksum */\r
+ unsigned char ip_src[4]; /* Source IP address */\r
+ unsigned char ip_dst[4]; /* Destination IP address */\r
+ unsigned short udp_src; /* UDP source port */\r
+ unsigned short udp_dst; /* UDP destination port */\r
+ unsigned short udp_len; /* Length of UDP packet */\r
+ unsigned short udp_xsum; /* Checksum */\r
+} AT91S_IPheader, *AT91PS_IPheader;\r
+\r
+//* ICMP echo header structure\r
+typedef struct _AT91S_IcmpEchoHdr {\r
+ unsigned char type; /* type of message */\r
+ unsigned char code; /* type subcode */\r
+ unsigned short cksum; /* ones complement cksum of struct */\r
+ unsigned short id; /* identifier */\r
+ unsigned short seq; /* sequence number */\r
+}AT91S_IcmpEchoHdr, *AT91PS_IcmpEchoHdr;\r
+\r
+\r
+typedef struct _AT91S_EthPack\r
+{\r
+ AT91S_EthHdr EthHdr;\r
+ AT91S_ArpHdr ArpHdr;\r
+} AT91S_EthPack, *AT91PS_EthPack;\r
+\r
+\r
+#endif //* AT91C_EMAC_H\r
--- /dev/null
+//*----------------------------------------------------------------------------\r
+//* ATMEL Microcontroller Software Support - ROUSSET -\r
+//*----------------------------------------------------------------------------\r
+//* The software is delivered "AS IS" without warranty or condition of any\r
+//* kind, either express, implied or statutory. This includes without\r
+//* limitation any warranty or condition with respect to merchantability or\r
+//* fitness for any particular purpose, or against the infringements of\r
+//* intellectual property rights of others.\r
+//*----------------------------------------------------------------------------\r
+//* File Name : dbgu.c\r
+//* Object : DBGU routines written in C\r
+//* Creation : JG 16/Aug/2004\r
+//*----------------------------------------------------------------------------\r
+\r
+// Include Standard files\r
+#include "Board.h"\r
+\r
+//*--------------------------1--------------------------------------------------\r
+//* \fn AT91F_DBGU_Printk\r
+//* \brief This function is used to send a string through the DBGU channel (Very low level debugging)\r
+//*----------------------------------------------------------------------------\r
+void AT91F_DBGU_Printk( char *buffer)\r
+{\r
+ AT91PS_DBGU pDbgu = AT91C_BASE_DBGU ; \r
+ unsigned int temp;\r
+ \r
+ while(*buffer != '\0') \r
+ {\r
+ temp=0;\r
+ \r
+ while (temp==0)\r
+ {\r
+ if ( (pDbgu->DBGU_CSR & 0x0200) == 0)\r
+ temp=0;\r
+ else\r
+ temp=1;\r
+ }\r
+\r
+ pDbgu->DBGU_THR = *buffer;\r
+ buffer++;\r
+ }\r
+}\r
+\r
+\r
+void Init_DBGU_CLK(void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(AT91C_BASE_PMC, ((unsigned int) 1 << AT91C_ID_SYS));\r
+}\r
+\r
+void Init_DBGU_BGR(unsigned short baud)\r
+{\r
+ AT91PS_DBGU pDbgu = AT91C_BASE_DBGU ; \r
+ \r
+ pDbgu->DBGU_BRGR = (unsigned short)baud;\r
+}\r
+\r
+void DBGU_TX_Enable(void)\r
+{\r
+ AT91PS_DBGU pDbgu = AT91C_BASE_DBGU ; \r
+ \r
+ pDbgu->DBGU_CR = 0x00000040;\r
+}\r
+\r
+void DBGU_RX_Enable(void)\r
+{\r
+ AT91PS_DBGU pDbgu = AT91C_BASE_DBGU ; \r
+ \r
+ pDbgu->DBGU_CR = 0x00000010;\r
+}\r
+\r
+void DBGU_RX_TX_RST_DIS(void)\r
+{\r
+ AT91PS_DBGU pDbgu = AT91C_BASE_DBGU ; \r
+ pDbgu->DBGU_CR = 0x000000AC;\r
+}\r
+\r
+void DBGU_Parity_Cfg(unsigned int par)\r
+{\r
+ AT91PS_DBGU pDbgu = AT91C_BASE_DBGU ; \r
+ \r
+ pDbgu->DBGU_MR = par << 9;\r
+}\r
+\r
+\r
+void Init_DBGU(void)\r
+{ \r
+ AT91F_DBGU_CfgPIO();\r
+ DBGU_RX_TX_RST_DIS();\r
+ Init_DBGU_BGR(26); //26 <=> 115kBd\r
+ DBGU_Parity_Cfg(4);\r
+ DBGU_TX_Enable(); \r
+ DBGU_RX_Enable();\r
+}\r
+\r
+\r
--- /dev/null
+//*----------------------------------------------------------------------------\r
+//* ATMEL Microcontroller Software Support - ROUSSET -\r
+//*----------------------------------------------------------------------------\r
+//* The software is delivered "AS IS" without warranty or condition of any\r
+//* kind, either express, implied or statutory. This includes without\r
+//* limitation any warranty or condition with respect to merchantability or\r
+//* fitness for any particular purpose, or against the infringements of\r
+//* intellectual property rights of others.\r
+//*----------------------------------------------------------------------------\r
+//* File Name : dbgu.c\r
+//* Object : DBGU routines written in C\r
+//* Creation : JG 16/Aug/2004\r
+//*----------------------------------------------------------------------------\r
+\r
+// Include Standard files\r
+extern void APPLI_DBGU(void); \r
+extern void D1_TEST_REGISTER_RESET_VALUES(void);\r
+extern void D2_CHIP_ID_VALUES(void);\r
+\r
+\r
+\r
+\r
--- /dev/null
+//*----------------------------------------------------------------------------\r
+//* ATMEL Microcontroller Software Support - ROUSSET -\r
+//*----------------------------------------------------------------------------\r
+//* The software is delivered "AS IS" without warranty or condition of any\r
+//* kind, either express, implied or statutory. This includes without\r
+//* limitation any warranty or condition with respect to merchantability or\r
+//* fitness for any particular purpose, or against the infringements of\r
+//* intellectual property rights of others.\r
+//*----------------------------------------------------------------------------\r
+//* File Name : init.c\r
+//* Object : Low level initialisations written in C\r
+//* Creation : ODi 06/26/2002\r
+//*\r
+//*----------------------------------------------------------------------------\r
+#include "board.h"\r
+//#include "init.h"\r
+#include <string.h>\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_DBGU_Printk\r
+//* \brief This function is used to send a string through the DBGU channel (Very low level debugging)\r
+//*----------------------------------------------------------------------------\r
+void AT91F_DBGU_Printk(\r
+ char *buffer) // \arg pointer to a string ending by \0\r
+{\r
+ while(*buffer != '\0') {\r
+ while (!AT91F_US_TxReady((AT91PS_USART)AT91C_BASE_DBGU));\r
+ AT91F_US_PutChar((AT91PS_USART)AT91C_BASE_DBGU, *buffer++);\r
+ }\r
+}\r
+\r
--- /dev/null
+// - ----------------------------------------------------------------------------\r
+// - ATMEL Microcontroller Software Support - ROUSSET -\r
+// - ----------------------------------------------------------------------------\r
+// - DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+// - IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+// - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+// - DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+// - INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+// - LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+// - OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+// - LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+// - NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+// - EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+// - ----------------------------------------------------------------------------\r
+// - File Name : AT91SAM7X128.h\r
+// - Object : AT91SAM7X128 definitions\r
+// - Generated : AT91 SW Application Group 05/20/2005 (16:22:23)\r
+// - \r
+// - CVS Reference : /AT91SAM7X128.pl/1.14/Tue May 10 12:12:05 2005//\r
+// - CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005//\r
+// - CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//\r
+// - CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005//\r
+// - CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005//\r
+// - CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//\r
+// - CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//\r
+// - CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//\r
+// - CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005//\r
+// - CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004//\r
+// - CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004//\r
+// - CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004//\r
+// - CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005//\r
+// - CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005//\r
+// - CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//\r
+// - CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//\r
+// - CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//\r
+// - CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//\r
+// - CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//\r
+// - CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//\r
+// - CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005//\r
+// - CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005//\r
+// - CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//\r
+// - CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005//\r
+// - CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005//\r
+// - ----------------------------------------------------------------------------\r
+\r
+#ifndef AT91SAM7X128_H\r
+#define AT91SAM7X128_H\r
+\r
+#ifdef __IAR_SYSTEMS_ICC__\r
+\r
+typedef volatile unsigned int AT91_REG;// Hardware register definition\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR System Peripherals\r
+// *****************************************************************************\r
+typedef struct _AT91S_SYS {\r
+ AT91_REG AIC_SMR[32]; // Source Mode Register\r
+ AT91_REG AIC_SVR[32]; // Source Vector Register\r
+ AT91_REG AIC_IVR; // IRQ Vector Register\r
+ AT91_REG AIC_FVR; // FIQ Vector Register\r
+ AT91_REG AIC_ISR; // Interrupt Status Register\r
+ AT91_REG AIC_IPR; // Interrupt Pending Register\r
+ AT91_REG AIC_IMR; // Interrupt Mask Register\r
+ AT91_REG AIC_CISR; // Core Interrupt Status Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG AIC_IECR; // Interrupt Enable Command Register\r
+ AT91_REG AIC_IDCR; // Interrupt Disable Command Register\r
+ AT91_REG AIC_ICCR; // Interrupt Clear Command Register\r
+ AT91_REG AIC_ISCR; // Interrupt Set Command Register\r
+ AT91_REG AIC_EOICR; // End of Interrupt Command Register\r
+ AT91_REG AIC_SPU; // Spurious Vector Register\r
+ AT91_REG AIC_DCR; // Debug Control Register (Protect)\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG AIC_FFER; // Fast Forcing Enable Register\r
+ AT91_REG AIC_FFDR; // Fast Forcing Disable Register\r
+ AT91_REG AIC_FFSR; // Fast Forcing Status Register\r
+ AT91_REG Reserved2[45]; // \r
+ AT91_REG DBGU_CR; // Control Register\r
+ AT91_REG DBGU_MR; // Mode Register\r
+ AT91_REG DBGU_IER; // Interrupt Enable Register\r
+ AT91_REG DBGU_IDR; // Interrupt Disable Register\r
+ AT91_REG DBGU_IMR; // Interrupt Mask Register\r
+ AT91_REG DBGU_CSR; // Channel Status Register\r
+ AT91_REG DBGU_RHR; // Receiver Holding Register\r
+ AT91_REG DBGU_THR; // Transmitter Holding Register\r
+ AT91_REG DBGU_BRGR; // Baud Rate Generator Register\r
+ AT91_REG Reserved3[7]; // \r
+ AT91_REG DBGU_CIDR; // Chip ID Register\r
+ AT91_REG DBGU_EXID; // Chip ID Extension Register\r
+ AT91_REG DBGU_FNTR; // Force NTRST Register\r
+ AT91_REG Reserved4[45]; // \r
+ AT91_REG DBGU_RPR; // Receive Pointer Register\r
+ AT91_REG DBGU_RCR; // Receive Counter Register\r
+ AT91_REG DBGU_TPR; // Transmit Pointer Register\r
+ AT91_REG DBGU_TCR; // Transmit Counter Register\r
+ AT91_REG DBGU_RNPR; // Receive Next Pointer Register\r
+ AT91_REG DBGU_RNCR; // Receive Next Counter Register\r
+ AT91_REG DBGU_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG DBGU_TNCR; // Transmit Next Counter Register\r
+ AT91_REG DBGU_PTCR; // PDC Transfer Control Register\r
+ AT91_REG DBGU_PTSR; // PDC Transfer Status Register\r
+ AT91_REG Reserved5[54]; // \r
+ AT91_REG PIOA_PER; // PIO Enable Register\r
+ AT91_REG PIOA_PDR; // PIO Disable Register\r
+ AT91_REG PIOA_PSR; // PIO Status Register\r
+ AT91_REG Reserved6[1]; // \r
+ AT91_REG PIOA_OER; // Output Enable Register\r
+ AT91_REG PIOA_ODR; // Output Disable Registerr\r
+ AT91_REG PIOA_OSR; // Output Status Register\r
+ AT91_REG Reserved7[1]; // \r
+ AT91_REG PIOA_IFER; // Input Filter Enable Register\r
+ AT91_REG PIOA_IFDR; // Input Filter Disable Register\r
+ AT91_REG PIOA_IFSR; // Input Filter Status Register\r
+ AT91_REG Reserved8[1]; // \r
+ AT91_REG PIOA_SODR; // Set Output Data Register\r
+ AT91_REG PIOA_CODR; // Clear Output Data Register\r
+ AT91_REG PIOA_ODSR; // Output Data Status Register\r
+ AT91_REG PIOA_PDSR; // Pin Data Status Register\r
+ AT91_REG PIOA_IER; // Interrupt Enable Register\r
+ AT91_REG PIOA_IDR; // Interrupt Disable Register\r
+ AT91_REG PIOA_IMR; // Interrupt Mask Register\r
+ AT91_REG PIOA_ISR; // Interrupt Status Register\r
+ AT91_REG PIOA_MDER; // Multi-driver Enable Register\r
+ AT91_REG PIOA_MDDR; // Multi-driver Disable Register\r
+ AT91_REG PIOA_MDSR; // Multi-driver Status Register\r
+ AT91_REG Reserved9[1]; // \r
+ AT91_REG PIOA_PPUDR; // Pull-up Disable Register\r
+ AT91_REG PIOA_PPUER; // Pull-up Enable Register\r
+ AT91_REG PIOA_PPUSR; // Pull-up Status Register\r
+ AT91_REG Reserved10[1]; // \r
+ AT91_REG PIOA_ASR; // Select A Register\r
+ AT91_REG PIOA_BSR; // Select B Register\r
+ AT91_REG PIOA_ABSR; // AB Select Status Register\r
+ AT91_REG Reserved11[9]; // \r
+ AT91_REG PIOA_OWER; // Output Write Enable Register\r
+ AT91_REG PIOA_OWDR; // Output Write Disable Register\r
+ AT91_REG PIOA_OWSR; // Output Write Status Register\r
+ AT91_REG Reserved12[85]; // \r
+ AT91_REG PIOB_PER; // PIO Enable Register\r
+ AT91_REG PIOB_PDR; // PIO Disable Register\r
+ AT91_REG PIOB_PSR; // PIO Status Register\r
+ AT91_REG Reserved13[1]; // \r
+ AT91_REG PIOB_OER; // Output Enable Register\r
+ AT91_REG PIOB_ODR; // Output Disable Registerr\r
+ AT91_REG PIOB_OSR; // Output Status Register\r
+ AT91_REG Reserved14[1]; // \r
+ AT91_REG PIOB_IFER; // Input Filter Enable Register\r
+ AT91_REG PIOB_IFDR; // Input Filter Disable Register\r
+ AT91_REG PIOB_IFSR; // Input Filter Status Register\r
+ AT91_REG Reserved15[1]; // \r
+ AT91_REG PIOB_SODR; // Set Output Data Register\r
+ AT91_REG PIOB_CODR; // Clear Output Data Register\r
+ AT91_REG PIOB_ODSR; // Output Data Status Register\r
+ AT91_REG PIOB_PDSR; // Pin Data Status Register\r
+ AT91_REG PIOB_IER; // Interrupt Enable Register\r
+ AT91_REG PIOB_IDR; // Interrupt Disable Register\r
+ AT91_REG PIOB_IMR; // Interrupt Mask Register\r
+ AT91_REG PIOB_ISR; // Interrupt Status Register\r
+ AT91_REG PIOB_MDER; // Multi-driver Enable Register\r
+ AT91_REG PIOB_MDDR; // Multi-driver Disable Register\r
+ AT91_REG PIOB_MDSR; // Multi-driver Status Register\r
+ AT91_REG Reserved16[1]; // \r
+ AT91_REG PIOB_PPUDR; // Pull-up Disable Register\r
+ AT91_REG PIOB_PPUER; // Pull-up Enable Register\r
+ AT91_REG PIOB_PPUSR; // Pull-up Status Register\r
+ AT91_REG Reserved17[1]; // \r
+ AT91_REG PIOB_ASR; // Select A Register\r
+ AT91_REG PIOB_BSR; // Select B Register\r
+ AT91_REG PIOB_ABSR; // AB Select Status Register\r
+ AT91_REG Reserved18[9]; // \r
+ AT91_REG PIOB_OWER; // Output Write Enable Register\r
+ AT91_REG PIOB_OWDR; // Output Write Disable Register\r
+ AT91_REG PIOB_OWSR; // Output Write Status Register\r
+ AT91_REG Reserved19[341]; // \r
+ AT91_REG PMC_SCER; // System Clock Enable Register\r
+ AT91_REG PMC_SCDR; // System Clock Disable Register\r
+ AT91_REG PMC_SCSR; // System Clock Status Register\r
+ AT91_REG Reserved20[1]; // \r
+ AT91_REG PMC_PCER; // Peripheral Clock Enable Register\r
+ AT91_REG PMC_PCDR; // Peripheral Clock Disable Register\r
+ AT91_REG PMC_PCSR; // Peripheral Clock Status Register\r
+ AT91_REG Reserved21[1]; // \r
+ AT91_REG PMC_MOR; // Main Oscillator Register\r
+ AT91_REG PMC_MCFR; // Main Clock Frequency Register\r
+ AT91_REG Reserved22[1]; // \r
+ AT91_REG PMC_PLLR; // PLL Register\r
+ AT91_REG PMC_MCKR; // Master Clock Register\r
+ AT91_REG Reserved23[3]; // \r
+ AT91_REG PMC_PCKR[4]; // Programmable Clock Register\r
+ AT91_REG Reserved24[4]; // \r
+ AT91_REG PMC_IER; // Interrupt Enable Register\r
+ AT91_REG PMC_IDR; // Interrupt Disable Register\r
+ AT91_REG PMC_SR; // Status Register\r
+ AT91_REG PMC_IMR; // Interrupt Mask Register\r
+ AT91_REG Reserved25[36]; // \r
+ AT91_REG RSTC_RCR; // Reset Control Register\r
+ AT91_REG RSTC_RSR; // Reset Status Register\r
+ AT91_REG RSTC_RMR; // Reset Mode Register\r
+ AT91_REG Reserved26[5]; // \r
+ AT91_REG RTTC_RTMR; // Real-time Mode Register\r
+ AT91_REG RTTC_RTAR; // Real-time Alarm Register\r
+ AT91_REG RTTC_RTVR; // Real-time Value Register\r
+ AT91_REG RTTC_RTSR; // Real-time Status Register\r
+ AT91_REG PITC_PIMR; // Period Interval Mode Register\r
+ AT91_REG PITC_PISR; // Period Interval Status Register\r
+ AT91_REG PITC_PIVR; // Period Interval Value Register\r
+ AT91_REG PITC_PIIR; // Period Interval Image Register\r
+ AT91_REG WDTC_WDCR; // Watchdog Control Register\r
+ AT91_REG WDTC_WDMR; // Watchdog Mode Register\r
+ AT91_REG WDTC_WDSR; // Watchdog Status Register\r
+ AT91_REG Reserved27[5]; // \r
+ AT91_REG VREG_MR; // Voltage Regulator Mode Register\r
+} AT91S_SYS, *AT91PS_SYS;\r
+\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller\r
+// *****************************************************************************\r
+typedef struct _AT91S_AIC {\r
+ AT91_REG AIC_SMR[32]; // Source Mode Register\r
+ AT91_REG AIC_SVR[32]; // Source Vector Register\r
+ AT91_REG AIC_IVR; // IRQ Vector Register\r
+ AT91_REG AIC_FVR; // FIQ Vector Register\r
+ AT91_REG AIC_ISR; // Interrupt Status Register\r
+ AT91_REG AIC_IPR; // Interrupt Pending Register\r
+ AT91_REG AIC_IMR; // Interrupt Mask Register\r
+ AT91_REG AIC_CISR; // Core Interrupt Status Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG AIC_IECR; // Interrupt Enable Command Register\r
+ AT91_REG AIC_IDCR; // Interrupt Disable Command Register\r
+ AT91_REG AIC_ICCR; // Interrupt Clear Command Register\r
+ AT91_REG AIC_ISCR; // Interrupt Set Command Register\r
+ AT91_REG AIC_EOICR; // End of Interrupt Command Register\r
+ AT91_REG AIC_SPU; // Spurious Vector Register\r
+ AT91_REG AIC_DCR; // Debug Control Register (Protect)\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG AIC_FFER; // Fast Forcing Enable Register\r
+ AT91_REG AIC_FFDR; // Fast Forcing Disable Register\r
+ AT91_REG AIC_FFSR; // Fast Forcing Status Register\r
+} AT91S_AIC, *AT91PS_AIC;\r
+\r
+// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- \r
+#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level\r
+#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level\r
+#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level\r
+#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type\r
+#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive\r
+#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ((unsigned int) 0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive\r
+#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered\r
+#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered\r
+#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive\r
+#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered\r
+// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- \r
+#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status\r
+#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status\r
+// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- \r
+#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode\r
+#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Peripheral DMA Controller\r
+// *****************************************************************************\r
+typedef struct _AT91S_PDC {\r
+ AT91_REG PDC_RPR; // Receive Pointer Register\r
+ AT91_REG PDC_RCR; // Receive Counter Register\r
+ AT91_REG PDC_TPR; // Transmit Pointer Register\r
+ AT91_REG PDC_TCR; // Transmit Counter Register\r
+ AT91_REG PDC_RNPR; // Receive Next Pointer Register\r
+ AT91_REG PDC_RNCR; // Receive Next Counter Register\r
+ AT91_REG PDC_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG PDC_TNCR; // Transmit Next Counter Register\r
+ AT91_REG PDC_PTCR; // PDC Transfer Control Register\r
+ AT91_REG PDC_PTSR; // PDC Transfer Status Register\r
+} AT91S_PDC, *AT91PS_PDC;\r
+\r
+// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- \r
+#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable\r
+#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable\r
+#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable\r
+#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable\r
+// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Debug Unit\r
+// *****************************************************************************\r
+typedef struct _AT91S_DBGU {\r
+ AT91_REG DBGU_CR; // Control Register\r
+ AT91_REG DBGU_MR; // Mode Register\r
+ AT91_REG DBGU_IER; // Interrupt Enable Register\r
+ AT91_REG DBGU_IDR; // Interrupt Disable Register\r
+ AT91_REG DBGU_IMR; // Interrupt Mask Register\r
+ AT91_REG DBGU_CSR; // Channel Status Register\r
+ AT91_REG DBGU_RHR; // Receiver Holding Register\r
+ AT91_REG DBGU_THR; // Transmitter Holding Register\r
+ AT91_REG DBGU_BRGR; // Baud Rate Generator Register\r
+ AT91_REG Reserved0[7]; // \r
+ AT91_REG DBGU_CIDR; // Chip ID Register\r
+ AT91_REG DBGU_EXID; // Chip ID Extension Register\r
+ AT91_REG DBGU_FNTR; // Force NTRST Register\r
+ AT91_REG Reserved1[45]; // \r
+ AT91_REG DBGU_RPR; // Receive Pointer Register\r
+ AT91_REG DBGU_RCR; // Receive Counter Register\r
+ AT91_REG DBGU_TPR; // Transmit Pointer Register\r
+ AT91_REG DBGU_TCR; // Transmit Counter Register\r
+ AT91_REG DBGU_RNPR; // Receive Next Pointer Register\r
+ AT91_REG DBGU_RNCR; // Receive Next Counter Register\r
+ AT91_REG DBGU_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG DBGU_TNCR; // Transmit Next Counter Register\r
+ AT91_REG DBGU_PTCR; // PDC Transfer Control Register\r
+ AT91_REG DBGU_PTSR; // PDC Transfer Status Register\r
+} AT91S_DBGU, *AT91PS_DBGU;\r
+\r
+// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- \r
+#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver\r
+#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter\r
+#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable\r
+#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable\r
+#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable\r
+#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable\r
+#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits\r
+// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- \r
+#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type\r
+#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity\r
+#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity\r
+#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space)\r
+#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark)\r
+#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity\r
+#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode\r
+#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode\r
+#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.\r
+#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.\r
+#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.\r
+#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.\r
+// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- \r
+#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt\r
+#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt\r
+#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt\r
+#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt\r
+#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt\r
+#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt\r
+#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt\r
+#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt\r
+#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt\r
+#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt\r
+#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt\r
+#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt\r
+// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- \r
+// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- \r
+// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- \r
+// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- \r
+#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Parallel Input Output Controler\r
+// *****************************************************************************\r
+typedef struct _AT91S_PIO {\r
+ AT91_REG PIO_PER; // PIO Enable Register\r
+ AT91_REG PIO_PDR; // PIO Disable Register\r
+ AT91_REG PIO_PSR; // PIO Status Register\r
+ AT91_REG Reserved0[1]; // \r
+ AT91_REG PIO_OER; // Output Enable Register\r
+ AT91_REG PIO_ODR; // Output Disable Registerr\r
+ AT91_REG PIO_OSR; // Output Status Register\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG PIO_IFER; // Input Filter Enable Register\r
+ AT91_REG PIO_IFDR; // Input Filter Disable Register\r
+ AT91_REG PIO_IFSR; // Input Filter Status Register\r
+ AT91_REG Reserved2[1]; // \r
+ AT91_REG PIO_SODR; // Set Output Data Register\r
+ AT91_REG PIO_CODR; // Clear Output Data Register\r
+ AT91_REG PIO_ODSR; // Output Data Status Register\r
+ AT91_REG PIO_PDSR; // Pin Data Status Register\r
+ AT91_REG PIO_IER; // Interrupt Enable Register\r
+ AT91_REG PIO_IDR; // Interrupt Disable Register\r
+ AT91_REG PIO_IMR; // Interrupt Mask Register\r
+ AT91_REG PIO_ISR; // Interrupt Status Register\r
+ AT91_REG PIO_MDER; // Multi-driver Enable Register\r
+ AT91_REG PIO_MDDR; // Multi-driver Disable Register\r
+ AT91_REG PIO_MDSR; // Multi-driver Status Register\r
+ AT91_REG Reserved3[1]; // \r
+ AT91_REG PIO_PPUDR; // Pull-up Disable Register\r
+ AT91_REG PIO_PPUER; // Pull-up Enable Register\r
+ AT91_REG PIO_PPUSR; // Pull-up Status Register\r
+ AT91_REG Reserved4[1]; // \r
+ AT91_REG PIO_ASR; // Select A Register\r
+ AT91_REG PIO_BSR; // Select B Register\r
+ AT91_REG PIO_ABSR; // AB Select Status Register\r
+ AT91_REG Reserved5[9]; // \r
+ AT91_REG PIO_OWER; // Output Write Enable Register\r
+ AT91_REG PIO_OWDR; // Output Write Disable Register\r
+ AT91_REG PIO_OWSR; // Output Write Status Register\r
+} AT91S_PIO, *AT91PS_PIO;\r
+\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Clock Generator Controler\r
+// *****************************************************************************\r
+typedef struct _AT91S_CKGR {\r
+ AT91_REG CKGR_MOR; // Main Oscillator Register\r
+ AT91_REG CKGR_MCFR; // Main Clock Frequency Register\r
+ AT91_REG Reserved0[1]; // \r
+ AT91_REG CKGR_PLLR; // PLL Register\r
+} AT91S_CKGR, *AT91PS_CKGR;\r
+\r
+// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- \r
+#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable\r
+#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass\r
+#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time\r
+// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- \r
+#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency\r
+#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready\r
+// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- \r
+#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected\r
+#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0\r
+#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed\r
+#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter\r
+#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range\r
+#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet\r
+#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet\r
+#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet\r
+#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet\r
+#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier\r
+#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks\r
+#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output\r
+#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2\r
+#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Power Management Controler\r
+// *****************************************************************************\r
+typedef struct _AT91S_PMC {\r
+ AT91_REG PMC_SCER; // System Clock Enable Register\r
+ AT91_REG PMC_SCDR; // System Clock Disable Register\r
+ AT91_REG PMC_SCSR; // System Clock Status Register\r
+ AT91_REG Reserved0[1]; // \r
+ AT91_REG PMC_PCER; // Peripheral Clock Enable Register\r
+ AT91_REG PMC_PCDR; // Peripheral Clock Disable Register\r
+ AT91_REG PMC_PCSR; // Peripheral Clock Status Register\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG PMC_MOR; // Main Oscillator Register\r
+ AT91_REG PMC_MCFR; // Main Clock Frequency Register\r
+ AT91_REG Reserved2[1]; // \r
+ AT91_REG PMC_PLLR; // PLL Register\r
+ AT91_REG PMC_MCKR; // Master Clock Register\r
+ AT91_REG Reserved3[3]; // \r
+ AT91_REG PMC_PCKR[4]; // Programmable Clock Register\r
+ AT91_REG Reserved4[4]; // \r
+ AT91_REG PMC_IER; // Interrupt Enable Register\r
+ AT91_REG PMC_IDR; // Interrupt Disable Register\r
+ AT91_REG PMC_SR; // Status Register\r
+ AT91_REG PMC_IMR; // Interrupt Mask Register\r
+} AT91S_PMC, *AT91PS_PMC;\r
+\r
+// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- \r
+#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock\r
+#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock\r
+#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output\r
+#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output\r
+#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output\r
+#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output\r
+// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- \r
+// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- \r
+// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- \r
+// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- \r
+// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- \r
+// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- \r
+#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection\r
+#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected\r
+#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected\r
+#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected\r
+#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler\r
+#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock\r
+#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2\r
+#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4\r
+#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8\r
+#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16\r
+#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32\r
+#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64\r
+// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- \r
+// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- \r
+#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask\r
+#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask\r
+#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask\r
+// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- \r
+// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- \r
+// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Reset Controller Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_RSTC {\r
+ AT91_REG RSTC_RCR; // Reset Control Register\r
+ AT91_REG RSTC_RSR; // Reset Status Register\r
+ AT91_REG RSTC_RMR; // Reset Mode Register\r
+} AT91S_RSTC, *AT91PS_RSTC;\r
+\r
+// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- \r
+#define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset\r
+#define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset\r
+#define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset\r
+#define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password\r
+// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- \r
+#define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status\r
+#define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status\r
+#define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type\r
+#define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising.\r
+#define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising.\r
+#define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.\r
+#define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.\r
+#define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low.\r
+#define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured.\r
+#define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level\r
+#define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress.\r
+// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- \r
+#define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable\r
+#define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable\r
+#define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable\r
+#define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_RTTC {\r
+ AT91_REG RTTC_RTMR; // Real-time Mode Register\r
+ AT91_REG RTTC_RTAR; // Real-time Alarm Register\r
+ AT91_REG RTTC_RTVR; // Real-time Value Register\r
+ AT91_REG RTTC_RTSR; // Real-time Status Register\r
+} AT91S_RTTC, *AT91PS_RTTC;\r
+\r
+// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- \r
+#define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value\r
+#define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable\r
+#define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable\r
+#define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart\r
+// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- \r
+#define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value\r
+// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- \r
+#define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value\r
+// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- \r
+#define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status\r
+#define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_PITC {\r
+ AT91_REG PITC_PIMR; // Period Interval Mode Register\r
+ AT91_REG PITC_PISR; // Period Interval Status Register\r
+ AT91_REG PITC_PIVR; // Period Interval Value Register\r
+ AT91_REG PITC_PIIR; // Period Interval Image Register\r
+} AT91S_PITC, *AT91PS_PITC;\r
+\r
+// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- \r
+#define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value\r
+#define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled\r
+#define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable\r
+// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- \r
+#define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status\r
+// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- \r
+#define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value\r
+#define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter\r
+// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_WDTC {\r
+ AT91_REG WDTC_WDCR; // Watchdog Control Register\r
+ AT91_REG WDTC_WDMR; // Watchdog Mode Register\r
+ AT91_REG WDTC_WDSR; // Watchdog Status Register\r
+} AT91S_WDTC, *AT91PS_WDTC;\r
+\r
+// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- \r
+#define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart\r
+#define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password\r
+// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- \r
+#define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart\r
+#define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable\r
+#define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable\r
+#define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart\r
+#define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable\r
+#define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value\r
+#define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt\r
+#define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt\r
+// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- \r
+#define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow\r
+#define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_VREG {\r
+ AT91_REG VREG_MR; // Voltage Regulator Mode Register\r
+} AT91S_VREG, *AT91PS_VREG;\r
+\r
+// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- \r
+#define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Memory Controller Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_MC {\r
+ AT91_REG MC_RCR; // MC Remap Control Register\r
+ AT91_REG MC_ASR; // MC Abort Status Register\r
+ AT91_REG MC_AASR; // MC Abort Address Status Register\r
+ AT91_REG Reserved0[21]; // \r
+ AT91_REG MC_FMR; // MC Flash Mode Register\r
+ AT91_REG MC_FCR; // MC Flash Command Register\r
+ AT91_REG MC_FSR; // MC Flash Status Register\r
+} AT91S_MC, *AT91PS_MC;\r
+\r
+// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- \r
+#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit\r
+// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- \r
+#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status\r
+#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status\r
+#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status\r
+#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte\r
+#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word\r
+#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word\r
+#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status\r
+#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read\r
+#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write\r
+#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch\r
+#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source\r
+#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source\r
+#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source\r
+#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source\r
+// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- \r
+#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready\r
+#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error\r
+#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error\r
+#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming\r
+#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State\r
+#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations\r
+#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations\r
+#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations\r
+#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations\r
+#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number\r
+// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- \r
+#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command\r
+#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN.\r
+#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.\r
+#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.\r
+#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.\r
+#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.\r
+#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits.\r
+#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits.\r
+#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit.\r
+#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number\r
+#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key\r
+// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- \r
+#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status\r
+#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status\r
+#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status\r
+#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status\r
+#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status\r
+#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status\r
+#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status\r
+#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status\r
+#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status\r
+#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status\r
+#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status\r
+#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status\r
+#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status\r
+#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status\r
+#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status\r
+#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status\r
+#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status\r
+#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status\r
+#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status\r
+#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status\r
+#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status\r
+#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status\r
+#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status\r
+#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status\r
+#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Serial Parallel Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_SPI {\r
+ AT91_REG SPI_CR; // Control Register\r
+ AT91_REG SPI_MR; // Mode Register\r
+ AT91_REG SPI_RDR; // Receive Data Register\r
+ AT91_REG SPI_TDR; // Transmit Data Register\r
+ AT91_REG SPI_SR; // Status Register\r
+ AT91_REG SPI_IER; // Interrupt Enable Register\r
+ AT91_REG SPI_IDR; // Interrupt Disable Register\r
+ AT91_REG SPI_IMR; // Interrupt Mask Register\r
+ AT91_REG Reserved0[4]; // \r
+ AT91_REG SPI_CSR[4]; // Chip Select Register\r
+ AT91_REG Reserved1[48]; // \r
+ AT91_REG SPI_RPR; // Receive Pointer Register\r
+ AT91_REG SPI_RCR; // Receive Counter Register\r
+ AT91_REG SPI_TPR; // Transmit Pointer Register\r
+ AT91_REG SPI_TCR; // Transmit Counter Register\r
+ AT91_REG SPI_RNPR; // Receive Next Pointer Register\r
+ AT91_REG SPI_RNCR; // Receive Next Counter Register\r
+ AT91_REG SPI_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG SPI_TNCR; // Transmit Next Counter Register\r
+ AT91_REG SPI_PTCR; // PDC Transfer Control Register\r
+ AT91_REG SPI_PTSR; // PDC Transfer Status Register\r
+} AT91S_SPI, *AT91PS_SPI;\r
+\r
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- \r
+#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable\r
+#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable\r
+#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset\r
+#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer\r
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- \r
+#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode\r
+#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select\r
+#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select\r
+#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select\r
+#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode\r
+#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection\r
+#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection\r
+#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection\r
+#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select\r
+#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects\r
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- \r
+#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data\r
+#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status\r
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- \r
+#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data\r
+#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status\r
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- \r
+#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full\r
+#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty\r
+#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error\r
+#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status\r
+#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer\r
+#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer\r
+#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt\r
+#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt\r
+#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt\r
+#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt\r
+#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status\r
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- \r
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- \r
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- \r
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- \r
+#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity\r
+#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase\r
+#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer\r
+#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer\r
+#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer\r
+#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer\r
+#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer\r
+#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer\r
+#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer\r
+#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer\r
+#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer\r
+#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer\r
+#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer\r
+#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate\r
+#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK\r
+#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Usart\r
+// *****************************************************************************\r
+typedef struct _AT91S_USART {\r
+ AT91_REG US_CR; // Control Register\r
+ AT91_REG US_MR; // Mode Register\r
+ AT91_REG US_IER; // Interrupt Enable Register\r
+ AT91_REG US_IDR; // Interrupt Disable Register\r
+ AT91_REG US_IMR; // Interrupt Mask Register\r
+ AT91_REG US_CSR; // Channel Status Register\r
+ AT91_REG US_RHR; // Receiver Holding Register\r
+ AT91_REG US_THR; // Transmitter Holding Register\r
+ AT91_REG US_BRGR; // Baud Rate Generator Register\r
+ AT91_REG US_RTOR; // Receiver Time-out Register\r
+ AT91_REG US_TTGR; // Transmitter Time-guard Register\r
+ AT91_REG Reserved0[5]; // \r
+ AT91_REG US_FIDI; // FI_DI_Ratio Register\r
+ AT91_REG US_NER; // Nb Errors Register\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG US_IF; // IRDA_FILTER Register\r
+ AT91_REG Reserved2[44]; // \r
+ AT91_REG US_RPR; // Receive Pointer Register\r
+ AT91_REG US_RCR; // Receive Counter Register\r
+ AT91_REG US_TPR; // Transmit Pointer Register\r
+ AT91_REG US_TCR; // Transmit Counter Register\r
+ AT91_REG US_RNPR; // Receive Next Pointer Register\r
+ AT91_REG US_RNCR; // Receive Next Counter Register\r
+ AT91_REG US_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG US_TNCR; // Transmit Next Counter Register\r
+ AT91_REG US_PTCR; // PDC Transfer Control Register\r
+ AT91_REG US_PTSR; // PDC Transfer Status Register\r
+} AT91S_USART, *AT91PS_USART;\r
+\r
+// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- \r
+#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break\r
+#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break\r
+#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out\r
+#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address\r
+#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations\r
+#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge\r
+#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out\r
+#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable\r
+#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable\r
+#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable\r
+#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable\r
+// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- \r
+#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode\r
+#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal\r
+#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485\r
+#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking\r
+#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem\r
+#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0\r
+#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1\r
+#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA\r
+#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking\r
+#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock\r
+#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock\r
+#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1\r
+#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM)\r
+#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK)\r
+#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock\r
+#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits\r
+#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits\r
+#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits\r
+#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits\r
+#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select\r
+#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits\r
+#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit\r
+#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits\r
+#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits\r
+#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order\r
+#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length\r
+#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select\r
+#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode\r
+#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge\r
+#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK\r
+#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions\r
+#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter\r
+// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- \r
+#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break\r
+#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out\r
+#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached\r
+#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge\r
+#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag\r
+#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag\r
+#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag\r
+#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag\r
+// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- \r
+// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- \r
+// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- \r
+#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input\r
+#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input\r
+#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input\r
+#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_SSC {\r
+ AT91_REG SSC_CR; // Control Register\r
+ AT91_REG SSC_CMR; // Clock Mode Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG SSC_RCMR; // Receive Clock ModeRegister\r
+ AT91_REG SSC_RFMR; // Receive Frame Mode Register\r
+ AT91_REG SSC_TCMR; // Transmit Clock Mode Register\r
+ AT91_REG SSC_TFMR; // Transmit Frame Mode Register\r
+ AT91_REG SSC_RHR; // Receive Holding Register\r
+ AT91_REG SSC_THR; // Transmit Holding Register\r
+ AT91_REG Reserved1[2]; // \r
+ AT91_REG SSC_RSHR; // Receive Sync Holding Register\r
+ AT91_REG SSC_TSHR; // Transmit Sync Holding Register\r
+ AT91_REG Reserved2[2]; // \r
+ AT91_REG SSC_SR; // Status Register\r
+ AT91_REG SSC_IER; // Interrupt Enable Register\r
+ AT91_REG SSC_IDR; // Interrupt Disable Register\r
+ AT91_REG SSC_IMR; // Interrupt Mask Register\r
+ AT91_REG Reserved3[44]; // \r
+ AT91_REG SSC_RPR; // Receive Pointer Register\r
+ AT91_REG SSC_RCR; // Receive Counter Register\r
+ AT91_REG SSC_TPR; // Transmit Pointer Register\r
+ AT91_REG SSC_TCR; // Transmit Counter Register\r
+ AT91_REG SSC_RNPR; // Receive Next Pointer Register\r
+ AT91_REG SSC_RNCR; // Receive Next Counter Register\r
+ AT91_REG SSC_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG SSC_TNCR; // Transmit Next Counter Register\r
+ AT91_REG SSC_PTCR; // PDC Transfer Control Register\r
+ AT91_REG SSC_PTSR; // PDC Transfer Status Register\r
+} AT91S_SSC, *AT91PS_SSC;\r
+\r
+// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- \r
+#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable\r
+#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable\r
+#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable\r
+#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable\r
+#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset\r
+// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- \r
+#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection\r
+#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock\r
+#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal\r
+#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin\r
+#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection\r
+#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only\r
+#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output\r
+#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output\r
+#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion\r
+#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection\r
+#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.\r
+#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start\r
+#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input\r
+#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input\r
+#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input\r
+#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input\r
+#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input\r
+#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input\r
+#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0\r
+#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay\r
+#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection\r
+// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- \r
+#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length\r
+#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode\r
+#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First\r
+#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame\r
+#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length\r
+#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection\r
+#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only\r
+#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse\r
+#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse\r
+#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer\r
+#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer\r
+#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer\r
+#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection\r
+// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- \r
+// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- \r
+#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value\r
+#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable\r
+// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- \r
+#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready\r
+#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty\r
+#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission\r
+#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty\r
+#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready\r
+#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun\r
+#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception\r
+#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full\r
+#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync\r
+#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync\r
+#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable\r
+#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable\r
+// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- \r
+// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- \r
+// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Two-wire Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_TWI {\r
+ AT91_REG TWI_CR; // Control Register\r
+ AT91_REG TWI_MMR; // Master Mode Register\r
+ AT91_REG Reserved0[1]; // \r
+ AT91_REG TWI_IADR; // Internal Address Register\r
+ AT91_REG TWI_CWGR; // Clock Waveform Generator Register\r
+ AT91_REG Reserved1[3]; // \r
+ AT91_REG TWI_SR; // Status Register\r
+ AT91_REG TWI_IER; // Interrupt Enable Register\r
+ AT91_REG TWI_IDR; // Interrupt Disable Register\r
+ AT91_REG TWI_IMR; // Interrupt Mask Register\r
+ AT91_REG TWI_RHR; // Receive Holding Register\r
+ AT91_REG TWI_THR; // Transmit Holding Register\r
+} AT91S_TWI, *AT91PS_TWI;\r
+\r
+// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- \r
+#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition\r
+#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition\r
+#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled\r
+#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled\r
+#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset\r
+// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- \r
+#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size\r
+#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address\r
+#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address\r
+#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address\r
+#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address\r
+#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction\r
+#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address\r
+// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- \r
+#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider\r
+#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider\r
+#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider\r
+// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- \r
+#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed\r
+#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY\r
+#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY\r
+#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error\r
+#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error\r
+#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged\r
+// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- \r
+// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- \r
+// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR PWMC Channel Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_PWMC_CH {\r
+ AT91_REG PWMC_CMR; // Channel Mode Register\r
+ AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register\r
+ AT91_REG PWMC_CPRDR; // Channel Period Register\r
+ AT91_REG PWMC_CCNTR; // Channel Counter Register\r
+ AT91_REG PWMC_CUPDR; // Channel Update Register\r
+ AT91_REG PWMC_Reserved[3]; // Reserved\r
+} AT91S_PWMC_CH, *AT91PS_PWMC_CH;\r
+\r
+// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- \r
+#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx\r
+#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH) \r
+#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH) \r
+#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH) \r
+#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment\r
+#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity\r
+#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period\r
+// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- \r
+#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle\r
+// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- \r
+#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period\r
+// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- \r
+#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter\r
+// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- \r
+#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_PWMC {\r
+ AT91_REG PWMC_MR; // PWMC Mode Register\r
+ AT91_REG PWMC_ENA; // PWMC Enable Register\r
+ AT91_REG PWMC_DIS; // PWMC Disable Register\r
+ AT91_REG PWMC_SR; // PWMC Status Register\r
+ AT91_REG PWMC_IER; // PWMC Interrupt Enable Register\r
+ AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register\r
+ AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register\r
+ AT91_REG PWMC_ISR; // PWMC Interrupt Status Register\r
+ AT91_REG Reserved0[55]; // \r
+ AT91_REG PWMC_VR; // PWMC Version Register\r
+ AT91_REG Reserved1[64]; // \r
+ AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel\r
+} AT91S_PWMC, *AT91PS_PWMC;\r
+\r
+// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- \r
+#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor.\r
+#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A\r
+#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC) \r
+#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor.\r
+#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B\r
+#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC) \r
+// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- \r
+#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0\r
+#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1\r
+#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2\r
+#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3\r
+// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- \r
+// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- \r
+// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- \r
+// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- \r
+// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- \r
+// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR USB Device Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_UDP {\r
+ AT91_REG UDP_NUM; // Frame Number Register\r
+ AT91_REG UDP_GLBSTATE; // Global State Register\r
+ AT91_REG UDP_FADDR; // Function Address Register\r
+ AT91_REG Reserved0[1]; // \r
+ AT91_REG UDP_IER; // Interrupt Enable Register\r
+ AT91_REG UDP_IDR; // Interrupt Disable Register\r
+ AT91_REG UDP_IMR; // Interrupt Mask Register\r
+ AT91_REG UDP_ISR; // Interrupt Status Register\r
+ AT91_REG UDP_ICR; // Interrupt Clear Register\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG UDP_RSTEP; // Reset Endpoint Register\r
+ AT91_REG Reserved2[1]; // \r
+ AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register\r
+ AT91_REG Reserved3[2]; // \r
+ AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register\r
+ AT91_REG Reserved4[3]; // \r
+ AT91_REG UDP_TXVC; // Transceiver Control Register\r
+} AT91S_UDP, *AT91PS_UDP;\r
+\r
+// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- \r
+#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats\r
+#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error\r
+#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK\r
+// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- \r
+#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable\r
+#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured\r
+#define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume\r
+#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host\r
+#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable\r
+// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- \r
+#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value\r
+#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable\r
+// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- \r
+#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt\r
+#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt\r
+#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt\r
+#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt\r
+#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt\r
+#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt\r
+#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt\r
+#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt\r
+#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt\r
+#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt\r
+#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt\r
+// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- \r
+// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- \r
+// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- \r
+#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt\r
+// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- \r
+// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- \r
+#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0\r
+#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1\r
+#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2\r
+#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3\r
+#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4\r
+#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5\r
+// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- \r
+#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR\r
+#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0\r
+#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)\r
+#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)\r
+#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready\r
+#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).\r
+#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).\r
+#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction\r
+#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type\r
+#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control\r
+#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT\r
+#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT\r
+#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT\r
+#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN\r
+#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN\r
+#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN\r
+#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle\r
+#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable\r
+#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO\r
+// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- \r
+#define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP) \r
+#define AT91C_UDP_PUON ((unsigned int) 0x1 << 9) // (UDP) Pull-up ON\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_TC {\r
+ AT91_REG TC_CCR; // Channel Control Register\r
+ AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode)\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG TC_CV; // Counter Value\r
+ AT91_REG TC_RA; // Register A\r
+ AT91_REG TC_RB; // Register B\r
+ AT91_REG TC_RC; // Register C\r
+ AT91_REG TC_SR; // Status Register\r
+ AT91_REG TC_IER; // Interrupt Enable Register\r
+ AT91_REG TC_IDR; // Interrupt Disable Register\r
+ AT91_REG TC_IMR; // Interrupt Mask Register\r
+} AT91S_TC, *AT91PS_TC;\r
+\r
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- \r
+#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command\r
+#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command\r
+#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command\r
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- \r
+#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection\r
+#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK\r
+#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK\r
+#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK\r
+#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK\r
+#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK\r
+#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0\r
+#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1\r
+#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2\r
+#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert\r
+#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection\r
+#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal\r
+#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock\r
+#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock\r
+#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock\r
+#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare\r
+#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading\r
+#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare\r
+#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading\r
+#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection\r
+#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None\r
+#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge\r
+#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge\r
+#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge\r
+#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection\r
+#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None\r
+#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge\r
+#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge\r
+#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge\r
+#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection\r
+#define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input\r
+#define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output\r
+#define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output\r
+#define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output\r
+#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection\r
+#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable\r
+#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection\r
+#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare\r
+#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare\r
+#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare\r
+#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare\r
+#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable\r
+#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) \r
+#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA\r
+#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none\r
+#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set\r
+#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear\r
+#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle\r
+#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection\r
+#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None\r
+#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA\r
+#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA\r
+#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA\r
+#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA\r
+#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none\r
+#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set\r
+#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear\r
+#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle\r
+#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection\r
+#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None\r
+#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA\r
+#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA\r
+#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA\r
+#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA\r
+#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none\r
+#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set\r
+#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear\r
+#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle\r
+#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA\r
+#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none\r
+#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set\r
+#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear\r
+#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle\r
+#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB\r
+#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none\r
+#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set\r
+#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear\r
+#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle\r
+#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB\r
+#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none\r
+#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set\r
+#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear\r
+#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle\r
+#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB\r
+#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none\r
+#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set\r
+#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear\r
+#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle\r
+#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB\r
+#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none\r
+#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set\r
+#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear\r
+#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle\r
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- \r
+#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow\r
+#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun\r
+#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare\r
+#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare\r
+#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare\r
+#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading\r
+#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading\r
+#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger\r
+#define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling\r
+#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror\r
+#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror\r
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- \r
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- \r
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Timer Counter Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_TCB {\r
+ AT91S_TC TCB_TC0; // TC Channel 0\r
+ AT91_REG Reserved0[4]; // \r
+ AT91S_TC TCB_TC1; // TC Channel 1\r
+ AT91_REG Reserved1[4]; // \r
+ AT91S_TC TCB_TC2; // TC Channel 2\r
+ AT91_REG Reserved2[4]; // \r
+ AT91_REG TCB_BCR; // TC Block Control Register\r
+ AT91_REG TCB_BMR; // TC Block Mode Register\r
+} AT91S_TCB, *AT91PS_TCB;\r
+\r
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- \r
+#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command\r
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- \r
+#define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection\r
+#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0\r
+#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0\r
+#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0\r
+#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0\r
+#define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection\r
+#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1\r
+#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1\r
+#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1\r
+#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1\r
+#define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection\r
+#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2\r
+#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2\r
+#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2\r
+#define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_CAN_MB {\r
+ AT91_REG CAN_MB_MMR; // MailBox Mode Register\r
+ AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register\r
+ AT91_REG CAN_MB_MID; // MailBox ID Register\r
+ AT91_REG CAN_MB_MFID; // MailBox Family ID Register\r
+ AT91_REG CAN_MB_MSR; // MailBox Status Register\r
+ AT91_REG CAN_MB_MDL; // MailBox Data Low Register\r
+ AT91_REG CAN_MB_MDH; // MailBox Data High Register\r
+ AT91_REG CAN_MB_MCR; // MailBox Control Register\r
+} AT91S_CAN_MB, *AT91PS_CAN_MB;\r
+\r
+// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- \r
+#define AT91C_CAN_MTIMEMARK ((unsigned int) 0xFFFF << 0) // (CAN_MB) Mailbox Timemark\r
+#define AT91C_CAN_PRIOR ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority\r
+#define AT91C_CAN_MOT ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type\r
+#define AT91C_CAN_MOT_DIS ((unsigned int) 0x0 << 24) // (CAN_MB) \r
+#define AT91C_CAN_MOT_RX ((unsigned int) 0x1 << 24) // (CAN_MB) \r
+#define AT91C_CAN_MOT_RXOVERWRITE ((unsigned int) 0x2 << 24) // (CAN_MB) \r
+#define AT91C_CAN_MOT_TX ((unsigned int) 0x3 << 24) // (CAN_MB) \r
+#define AT91C_CAN_MOT_CONSUMER ((unsigned int) 0x4 << 24) // (CAN_MB) \r
+#define AT91C_CAN_MOT_PRODUCER ((unsigned int) 0x5 << 24) // (CAN_MB) \r
+// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- \r
+#define AT91C_CAN_MIDvB ((unsigned int) 0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode\r
+#define AT91C_CAN_MIDvA ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode\r
+#define AT91C_CAN_MIDE ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version\r
+// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- \r
+// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- \r
+// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- \r
+#define AT91C_CAN_MTIMESTAMP ((unsigned int) 0xFFFF << 0) // (CAN_MB) Timer Value\r
+#define AT91C_CAN_MDLC ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code\r
+#define AT91C_CAN_MRTR ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request\r
+#define AT91C_CAN_MABT ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort\r
+#define AT91C_CAN_MRDY ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready\r
+#define AT91C_CAN_MMI ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored\r
+// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- \r
+// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- \r
+// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- \r
+#define AT91C_CAN_MACR ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox\r
+#define AT91C_CAN_MTCR ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Control Area Network Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_CAN {\r
+ AT91_REG CAN_MR; // Mode Register\r
+ AT91_REG CAN_IER; // Interrupt Enable Register\r
+ AT91_REG CAN_IDR; // Interrupt Disable Register\r
+ AT91_REG CAN_IMR; // Interrupt Mask Register\r
+ AT91_REG CAN_SR; // Status Register\r
+ AT91_REG CAN_BR; // Baudrate Register\r
+ AT91_REG CAN_TIM; // Timer Register\r
+ AT91_REG CAN_TIMESTP; // Time Stamp Register\r
+ AT91_REG CAN_ECR; // Error Counter Register\r
+ AT91_REG CAN_TCR; // Transfer Command Register\r
+ AT91_REG CAN_ACR; // Abort Command Register\r
+ AT91_REG Reserved0[52]; // \r
+ AT91_REG CAN_VR; // Version Register\r
+ AT91_REG Reserved1[64]; // \r
+ AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0\r
+ AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1\r
+ AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2\r
+ AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3\r
+ AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4\r
+ AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5\r
+ AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6\r
+ AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7\r
+ AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8\r
+ AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9\r
+ AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10\r
+ AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11\r
+ AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12\r
+ AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13\r
+ AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14\r
+ AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15\r
+} AT91S_CAN, *AT91PS_CAN;\r
+\r
+// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- \r
+#define AT91C_CAN_CANEN ((unsigned int) 0x1 << 0) // (CAN) CAN Controller Enable\r
+#define AT91C_CAN_LPM ((unsigned int) 0x1 << 1) // (CAN) Disable/Enable Low Power Mode\r
+#define AT91C_CAN_ABM ((unsigned int) 0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode\r
+#define AT91C_CAN_OVL ((unsigned int) 0x1 << 3) // (CAN) Disable/Enable Overload Frame\r
+#define AT91C_CAN_TEOF ((unsigned int) 0x1 << 4) // (CAN) Time Stamp messages at each end of Frame\r
+#define AT91C_CAN_TTM ((unsigned int) 0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode\r
+#define AT91C_CAN_TIMFRZ ((unsigned int) 0x1 << 6) // (CAN) Enable Timer Freeze\r
+#define AT91C_CAN_DRPT ((unsigned int) 0x1 << 7) // (CAN) Disable Repeat\r
+// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- \r
+#define AT91C_CAN_MB0 ((unsigned int) 0x1 << 0) // (CAN) Mailbox 0 Flag\r
+#define AT91C_CAN_MB1 ((unsigned int) 0x1 << 1) // (CAN) Mailbox 1 Flag\r
+#define AT91C_CAN_MB2 ((unsigned int) 0x1 << 2) // (CAN) Mailbox 2 Flag\r
+#define AT91C_CAN_MB3 ((unsigned int) 0x1 << 3) // (CAN) Mailbox 3 Flag\r
+#define AT91C_CAN_MB4 ((unsigned int) 0x1 << 4) // (CAN) Mailbox 4 Flag\r
+#define AT91C_CAN_MB5 ((unsigned int) 0x1 << 5) // (CAN) Mailbox 5 Flag\r
+#define AT91C_CAN_MB6 ((unsigned int) 0x1 << 6) // (CAN) Mailbox 6 Flag\r
+#define AT91C_CAN_MB7 ((unsigned int) 0x1 << 7) // (CAN) Mailbox 7 Flag\r
+#define AT91C_CAN_MB8 ((unsigned int) 0x1 << 8) // (CAN) Mailbox 8 Flag\r
+#define AT91C_CAN_MB9 ((unsigned int) 0x1 << 9) // (CAN) Mailbox 9 Flag\r
+#define AT91C_CAN_MB10 ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag\r
+#define AT91C_CAN_MB11 ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag\r
+#define AT91C_CAN_MB12 ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag\r
+#define AT91C_CAN_MB13 ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag\r
+#define AT91C_CAN_MB14 ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag\r
+#define AT91C_CAN_MB15 ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag\r
+#define AT91C_CAN_ERRA ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag\r
+#define AT91C_CAN_WARN ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag\r
+#define AT91C_CAN_ERRP ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag\r
+#define AT91C_CAN_BOFF ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag\r
+#define AT91C_CAN_SLEEP ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag\r
+#define AT91C_CAN_WAKEUP ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag\r
+#define AT91C_CAN_TOVF ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag\r
+#define AT91C_CAN_TSTP ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag\r
+#define AT91C_CAN_CERR ((unsigned int) 0x1 << 24) // (CAN) CRC Error\r
+#define AT91C_CAN_SERR ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error\r
+#define AT91C_CAN_AERR ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error\r
+#define AT91C_CAN_FERR ((unsigned int) 0x1 << 27) // (CAN) Form Error\r
+#define AT91C_CAN_BERR ((unsigned int) 0x1 << 28) // (CAN) Bit Error\r
+// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- \r
+// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- \r
+// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- \r
+#define AT91C_CAN_RBSY ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy\r
+#define AT91C_CAN_TBSY ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy\r
+#define AT91C_CAN_OVLY ((unsigned int) 0x1 << 31) // (CAN) Overload Busy\r
+// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- \r
+#define AT91C_CAN_PHASE2 ((unsigned int) 0x7 << 0) // (CAN) Phase 2 segment\r
+#define AT91C_CAN_PHASE1 ((unsigned int) 0x7 << 4) // (CAN) Phase 1 segment\r
+#define AT91C_CAN_PROPAG ((unsigned int) 0x7 << 8) // (CAN) Programmation time segment\r
+#define AT91C_CAN_SYNC ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment\r
+#define AT91C_CAN_BRP ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler\r
+#define AT91C_CAN_SMP ((unsigned int) 0x1 << 24) // (CAN) Sampling mode\r
+// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- \r
+#define AT91C_CAN_TIMER ((unsigned int) 0xFFFF << 0) // (CAN) Timer field\r
+// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- \r
+// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- \r
+#define AT91C_CAN_REC ((unsigned int) 0xFF << 0) // (CAN) Receive Error Counter\r
+#define AT91C_CAN_TEC ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter\r
+// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- \r
+#define AT91C_CAN_TIMRST ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field\r
+// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100\r
+// *****************************************************************************\r
+typedef struct _AT91S_EMAC {\r
+ AT91_REG EMAC_NCR; // Network Control Register\r
+ AT91_REG EMAC_NCFGR; // Network Configuration Register\r
+ AT91_REG EMAC_NSR; // Network Status Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG EMAC_TSR; // Transmit Status Register\r
+ AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer\r
+ AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer\r
+ AT91_REG EMAC_RSR; // Receive Status Register\r
+ AT91_REG EMAC_ISR; // Interrupt Status Register\r
+ AT91_REG EMAC_IER; // Interrupt Enable Register\r
+ AT91_REG EMAC_IDR; // Interrupt Disable Register\r
+ AT91_REG EMAC_IMR; // Interrupt Mask Register\r
+ AT91_REG EMAC_MAN; // PHY Maintenance Register\r
+ AT91_REG EMAC_PTR; // Pause Time Register\r
+ AT91_REG EMAC_PFR; // Pause Frames received Register\r
+ AT91_REG EMAC_FTO; // Frames Transmitted OK Register\r
+ AT91_REG EMAC_SCF; // Single Collision Frame Register\r
+ AT91_REG EMAC_MCF; // Multiple Collision Frame Register\r
+ AT91_REG EMAC_FRO; // Frames Received OK Register\r
+ AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register\r
+ AT91_REG EMAC_ALE; // Alignment Error Register\r
+ AT91_REG EMAC_DTF; // Deferred Transmission Frame Register\r
+ AT91_REG EMAC_LCOL; // Late Collision Register\r
+ AT91_REG EMAC_ECOL; // Excessive Collision Register\r
+ AT91_REG EMAC_TUND; // Transmit Underrun Error Register\r
+ AT91_REG EMAC_CSE; // Carrier Sense Error Register\r
+ AT91_REG EMAC_RRE; // Receive Ressource Error Register\r
+ AT91_REG EMAC_ROV; // Receive Overrun Errors Register\r
+ AT91_REG EMAC_RSE; // Receive Symbol Errors Register\r
+ AT91_REG EMAC_ELE; // Excessive Length Errors Register\r
+ AT91_REG EMAC_RJA; // Receive Jabbers Register\r
+ AT91_REG EMAC_USF; // Undersize Frames Register\r
+ AT91_REG EMAC_STE; // SQE Test Error Register\r
+ AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register\r
+ AT91_REG EMAC_TPF; // Transmitted Pause Frames Register\r
+ AT91_REG EMAC_HRB; // Hash Address Bottom[31:0]\r
+ AT91_REG EMAC_HRT; // Hash Address Top[63:32]\r
+ AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes\r
+ AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes\r
+ AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes\r
+ AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes\r
+ AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes\r
+ AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes\r
+ AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes\r
+ AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes\r
+ AT91_REG EMAC_TID; // Type ID Checking Register\r
+ AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register\r
+ AT91_REG EMAC_USRIO; // USER Input/Output Register\r
+ AT91_REG EMAC_WOL; // Wake On LAN Register\r
+ AT91_REG Reserved1[13]; // \r
+ AT91_REG EMAC_REV; // Revision Register\r
+} AT91S_EMAC, *AT91PS_EMAC;\r
+\r
+// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- \r
+#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.\r
+#define AT91C_EMAC_LLB ((unsigned int) 0x1 << 1) // (EMAC) Loopback local. \r
+#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) // (EMAC) Receive enable. \r
+#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) // (EMAC) Transmit enable. \r
+#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) // (EMAC) Management port enable. \r
+#define AT91C_EMAC_CLRSTAT ((unsigned int) 0x1 << 5) // (EMAC) Clear statistics registers. \r
+#define AT91C_EMAC_INCSTAT ((unsigned int) 0x1 << 6) // (EMAC) Increment statistics registers. \r
+#define AT91C_EMAC_WESTAT ((unsigned int) 0x1 << 7) // (EMAC) Write enable for statistics registers. \r
+#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) // (EMAC) Back pressure. \r
+#define AT91C_EMAC_TSTART ((unsigned int) 0x1 << 9) // (EMAC) Start Transmission. \r
+#define AT91C_EMAC_THALT ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt. \r
+#define AT91C_EMAC_TPFR ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame \r
+#define AT91C_EMAC_TZQ ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame\r
+// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- \r
+#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) // (EMAC) Speed. \r
+#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) // (EMAC) Full duplex. \r
+#define AT91C_EMAC_JFRAME ((unsigned int) 0x1 << 3) // (EMAC) Jumbo Frames. \r
+#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) // (EMAC) Copy all frames. \r
+#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) // (EMAC) No broadcast. \r
+#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) // (EMAC) Multicast hash event enable\r
+#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) // (EMAC) Unicast hash enable. \r
+#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) // (EMAC) Receive 1522 bytes. \r
+#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) // (EMAC) External address match enable. \r
+#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) // (EMAC) \r
+#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8\r
+#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16\r
+#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32\r
+#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64\r
+#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) // (EMAC) \r
+#define AT91C_EMAC_PAE ((unsigned int) 0x1 << 13) // (EMAC) \r
+#define AT91C_EMAC_RBOF ((unsigned int) 0x3 << 14) // (EMAC) \r
+#define AT91C_EMAC_RBOF_OFFSET_0 ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer\r
+#define AT91C_EMAC_RBOF_OFFSET_1 ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer\r
+#define AT91C_EMAC_RBOF_OFFSET_2 ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer\r
+#define AT91C_EMAC_RBOF_OFFSET_3 ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer\r
+#define AT91C_EMAC_RLCE ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable\r
+#define AT91C_EMAC_DRFCS ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS\r
+#define AT91C_EMAC_EFRHD ((unsigned int) 0x1 << 18) // (EMAC) \r
+#define AT91C_EMAC_IRXFCS ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS\r
+// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- \r
+#define AT91C_EMAC_LINKR ((unsigned int) 0x1 << 0) // (EMAC) \r
+#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) // (EMAC) \r
+#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) // (EMAC) \r
+// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- \r
+#define AT91C_EMAC_UBR ((unsigned int) 0x1 << 0) // (EMAC) \r
+#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) // (EMAC) \r
+#define AT91C_EMAC_RLES ((unsigned int) 0x1 << 2) // (EMAC) \r
+#define AT91C_EMAC_TGO ((unsigned int) 0x1 << 3) // (EMAC) Transmit Go\r
+#define AT91C_EMAC_BEX ((unsigned int) 0x1 << 4) // (EMAC) Buffers exhausted mid frame\r
+#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) // (EMAC) \r
+#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) // (EMAC) \r
+// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- \r
+#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) // (EMAC) \r
+#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) // (EMAC) \r
+#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 2) // (EMAC) \r
+// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- \r
+#define AT91C_EMAC_MFD ((unsigned int) 0x1 << 0) // (EMAC) \r
+#define AT91C_EMAC_RCOMP ((unsigned int) 0x1 << 1) // (EMAC) \r
+#define AT91C_EMAC_RXUBR ((unsigned int) 0x1 << 2) // (EMAC) \r
+#define AT91C_EMAC_TXUBR ((unsigned int) 0x1 << 3) // (EMAC) \r
+#define AT91C_EMAC_TUNDR ((unsigned int) 0x1 << 4) // (EMAC) \r
+#define AT91C_EMAC_RLEX ((unsigned int) 0x1 << 5) // (EMAC) \r
+#define AT91C_EMAC_TXERR ((unsigned int) 0x1 << 6) // (EMAC) \r
+#define AT91C_EMAC_TCOMP ((unsigned int) 0x1 << 7) // (EMAC) \r
+#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) // (EMAC) \r
+#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) // (EMAC) \r
+#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) // (EMAC) \r
+#define AT91C_EMAC_PFRE ((unsigned int) 0x1 << 12) // (EMAC) \r
+#define AT91C_EMAC_PTZ ((unsigned int) 0x1 << 13) // (EMAC) \r
+// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- \r
+// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- \r
+// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- \r
+// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- \r
+#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) // (EMAC) \r
+#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) // (EMAC) \r
+#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) // (EMAC) \r
+#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) // (EMAC) \r
+#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) // (EMAC) \r
+#define AT91C_EMAC_SOF ((unsigned int) 0x3 << 30) // (EMAC) \r
+// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- \r
+#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 0) // (EMAC) Reduce MII\r
+// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- \r
+#define AT91C_EMAC_IP ((unsigned int) 0xFFFF << 0) // (EMAC) ARP request IP address\r
+#define AT91C_EMAC_MAG ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable\r
+#define AT91C_EMAC_ARP ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable\r
+#define AT91C_EMAC_SA1 ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable\r
+// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- \r
+#define AT91C_EMAC_REVREF ((unsigned int) 0xFFFF << 0) // (EMAC) \r
+#define AT91C_EMAC_PARTREF ((unsigned int) 0xFFFF << 16) // (EMAC) \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Analog to Digital Convertor\r
+// *****************************************************************************\r
+typedef struct _AT91S_ADC {\r
+ AT91_REG ADC_CR; // ADC Control Register\r
+ AT91_REG ADC_MR; // ADC Mode Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG ADC_CHER; // ADC Channel Enable Register\r
+ AT91_REG ADC_CHDR; // ADC Channel Disable Register\r
+ AT91_REG ADC_CHSR; // ADC Channel Status Register\r
+ AT91_REG ADC_SR; // ADC Status Register\r
+ AT91_REG ADC_LCDR; // ADC Last Converted Data Register\r
+ AT91_REG ADC_IER; // ADC Interrupt Enable Register\r
+ AT91_REG ADC_IDR; // ADC Interrupt Disable Register\r
+ AT91_REG ADC_IMR; // ADC Interrupt Mask Register\r
+ AT91_REG ADC_CDR0; // ADC Channel Data Register 0\r
+ AT91_REG ADC_CDR1; // ADC Channel Data Register 1\r
+ AT91_REG ADC_CDR2; // ADC Channel Data Register 2\r
+ AT91_REG ADC_CDR3; // ADC Channel Data Register 3\r
+ AT91_REG ADC_CDR4; // ADC Channel Data Register 4\r
+ AT91_REG ADC_CDR5; // ADC Channel Data Register 5\r
+ AT91_REG ADC_CDR6; // ADC Channel Data Register 6\r
+ AT91_REG ADC_CDR7; // ADC Channel Data Register 7\r
+ AT91_REG Reserved1[44]; // \r
+ AT91_REG ADC_RPR; // Receive Pointer Register\r
+ AT91_REG ADC_RCR; // Receive Counter Register\r
+ AT91_REG ADC_TPR; // Transmit Pointer Register\r
+ AT91_REG ADC_TCR; // Transmit Counter Register\r
+ AT91_REG ADC_RNPR; // Receive Next Pointer Register\r
+ AT91_REG ADC_RNCR; // Receive Next Counter Register\r
+ AT91_REG ADC_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG ADC_TNCR; // Transmit Next Counter Register\r
+ AT91_REG ADC_PTCR; // PDC Transfer Control Register\r
+ AT91_REG ADC_PTSR; // PDC Transfer Status Register\r
+} AT91S_ADC, *AT91PS_ADC;\r
+\r
+// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- \r
+#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset\r
+#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion\r
+// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- \r
+#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable\r
+#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software\r
+#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.\r
+#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection\r
+#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0\r
+#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1\r
+#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2\r
+#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3\r
+#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4\r
+#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5\r
+#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger\r
+#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution.\r
+#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution\r
+#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution\r
+#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode\r
+#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode\r
+#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode\r
+#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection\r
+#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time\r
+#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time\r
+// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- \r
+#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0\r
+#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1\r
+#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2\r
+#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3\r
+#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4\r
+#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5\r
+#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6\r
+#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7\r
+// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- \r
+// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- \r
+// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- \r
+#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion\r
+#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error\r
+#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready\r
+#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun\r
+#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer\r
+#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt\r
+// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- \r
+#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted\r
+// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- \r
+// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- \r
+// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- \r
+// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- \r
+#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data\r
+// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- \r
+// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- \r
+// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- \r
+// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- \r
+// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- \r
+// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- \r
+// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Advanced Encryption Standard\r
+// *****************************************************************************\r
+typedef struct _AT91S_AES {\r
+ AT91_REG AES_CR; // Control Register\r
+ AT91_REG AES_MR; // Mode Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG AES_IER; // Interrupt Enable Register\r
+ AT91_REG AES_IDR; // Interrupt Disable Register\r
+ AT91_REG AES_IMR; // Interrupt Mask Register\r
+ AT91_REG AES_ISR; // Interrupt Status Register\r
+ AT91_REG AES_KEYWxR[4]; // Key Word x Register\r
+ AT91_REG Reserved1[4]; // \r
+ AT91_REG AES_IDATAxR[4]; // Input Data x Register\r
+ AT91_REG AES_ODATAxR[4]; // Output Data x Register\r
+ AT91_REG AES_IVxR[4]; // Initialization Vector x Register\r
+ AT91_REG Reserved2[35]; // \r
+ AT91_REG AES_VR; // AES Version Register\r
+ AT91_REG AES_RPR; // Receive Pointer Register\r
+ AT91_REG AES_RCR; // Receive Counter Register\r
+ AT91_REG AES_TPR; // Transmit Pointer Register\r
+ AT91_REG AES_TCR; // Transmit Counter Register\r
+ AT91_REG AES_RNPR; // Receive Next Pointer Register\r
+ AT91_REG AES_RNCR; // Receive Next Counter Register\r
+ AT91_REG AES_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG AES_TNCR; // Transmit Next Counter Register\r
+ AT91_REG AES_PTCR; // PDC Transfer Control Register\r
+ AT91_REG AES_PTSR; // PDC Transfer Status Register\r
+} AT91S_AES, *AT91PS_AES;\r
+\r
+// -------- AES_CR : (AES Offset: 0x0) Control Register -------- \r
+#define AT91C_AES_START ((unsigned int) 0x1 << 0) // (AES) Starts Processing\r
+#define AT91C_AES_SWRST ((unsigned int) 0x1 << 8) // (AES) Software Reset\r
+#define AT91C_AES_LOADSEED ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading\r
+// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- \r
+#define AT91C_AES_CIPHER ((unsigned int) 0x1 << 0) // (AES) Processing Mode\r
+#define AT91C_AES_PROCDLY ((unsigned int) 0xF << 4) // (AES) Processing Delay\r
+#define AT91C_AES_SMOD ((unsigned int) 0x3 << 8) // (AES) Start Mode\r
+#define AT91C_AES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.\r
+#define AT91C_AES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).\r
+#define AT91C_AES_SMOD_PDC ((unsigned int) 0x2 << 8) // (AES) PDC Mode (cf datasheet).\r
+#define AT91C_AES_OPMOD ((unsigned int) 0x7 << 12) // (AES) Operation Mode\r
+#define AT91C_AES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode.\r
+#define AT91C_AES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode.\r
+#define AT91C_AES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode.\r
+#define AT91C_AES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode.\r
+#define AT91C_AES_OPMOD_CTR ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode.\r
+#define AT91C_AES_LOD ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode\r
+#define AT91C_AES_CFBS ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size\r
+#define AT91C_AES_CFBS_128_BIT ((unsigned int) 0x0 << 16) // (AES) 128-bit.\r
+#define AT91C_AES_CFBS_64_BIT ((unsigned int) 0x1 << 16) // (AES) 64-bit.\r
+#define AT91C_AES_CFBS_32_BIT ((unsigned int) 0x2 << 16) // (AES) 32-bit.\r
+#define AT91C_AES_CFBS_16_BIT ((unsigned int) 0x3 << 16) // (AES) 16-bit.\r
+#define AT91C_AES_CFBS_8_BIT ((unsigned int) 0x4 << 16) // (AES) 8-bit.\r
+#define AT91C_AES_CKEY ((unsigned int) 0xF << 20) // (AES) Countermeasure Key\r
+#define AT91C_AES_CTYPE ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type\r
+#define AT91C_AES_CTYPE_TYPE1_EN ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled.\r
+#define AT91C_AES_CTYPE_TYPE2_EN ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled.\r
+#define AT91C_AES_CTYPE_TYPE3_EN ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled.\r
+#define AT91C_AES_CTYPE_TYPE4_EN ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled.\r
+#define AT91C_AES_CTYPE_TYPE5_EN ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled.\r
+// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- \r
+#define AT91C_AES_DATRDY ((unsigned int) 0x1 << 0) // (AES) DATRDY\r
+#define AT91C_AES_ENDRX ((unsigned int) 0x1 << 1) // (AES) PDC Read Buffer End\r
+#define AT91C_AES_ENDTX ((unsigned int) 0x1 << 2) // (AES) PDC Write Buffer End\r
+#define AT91C_AES_RXBUFF ((unsigned int) 0x1 << 3) // (AES) PDC Read Buffer Full\r
+#define AT91C_AES_TXBUFE ((unsigned int) 0x1 << 4) // (AES) PDC Write Buffer Empty\r
+#define AT91C_AES_URAD ((unsigned int) 0x1 << 8) // (AES) Unspecified Register Access Detection\r
+// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- \r
+// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- \r
+// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- \r
+#define AT91C_AES_URAT ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status\r
+#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode.\r
+#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing.\r
+#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing.\r
+#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation.\r
+#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation.\r
+#define AT91C_AES_URAT_WO_REG_READ ((unsigned int) 0x5 << 12) // (AES) Write-only register read access.\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard\r
+// *****************************************************************************\r
+typedef struct _AT91S_TDES {\r
+ AT91_REG TDES_CR; // Control Register\r
+ AT91_REG TDES_MR; // Mode Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG TDES_IER; // Interrupt Enable Register\r
+ AT91_REG TDES_IDR; // Interrupt Disable Register\r
+ AT91_REG TDES_IMR; // Interrupt Mask Register\r
+ AT91_REG TDES_ISR; // Interrupt Status Register\r
+ AT91_REG TDES_KEY1WxR[2]; // Key 1 Word x Register\r
+ AT91_REG TDES_KEY2WxR[2]; // Key 2 Word x Register\r
+ AT91_REG TDES_KEY3WxR[2]; // Key 3 Word x Register\r
+ AT91_REG Reserved1[2]; // \r
+ AT91_REG TDES_IDATAxR[2]; // Input Data x Register\r
+ AT91_REG Reserved2[2]; // \r
+ AT91_REG TDES_ODATAxR[2]; // Output Data x Register\r
+ AT91_REG Reserved3[2]; // \r
+ AT91_REG TDES_IVxR[2]; // Initialization Vector x Register\r
+ AT91_REG Reserved4[37]; // \r
+ AT91_REG TDES_VR; // TDES Version Register\r
+ AT91_REG TDES_RPR; // Receive Pointer Register\r
+ AT91_REG TDES_RCR; // Receive Counter Register\r
+ AT91_REG TDES_TPR; // Transmit Pointer Register\r
+ AT91_REG TDES_TCR; // Transmit Counter Register\r
+ AT91_REG TDES_RNPR; // Receive Next Pointer Register\r
+ AT91_REG TDES_RNCR; // Receive Next Counter Register\r
+ AT91_REG TDES_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG TDES_TNCR; // Transmit Next Counter Register\r
+ AT91_REG TDES_PTCR; // PDC Transfer Control Register\r
+ AT91_REG TDES_PTSR; // PDC Transfer Status Register\r
+} AT91S_TDES, *AT91PS_TDES;\r
+\r
+// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- \r
+#define AT91C_TDES_START ((unsigned int) 0x1 << 0) // (TDES) Starts Processing\r
+#define AT91C_TDES_SWRST ((unsigned int) 0x1 << 8) // (TDES) Software Reset\r
+// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- \r
+#define AT91C_TDES_CIPHER ((unsigned int) 0x1 << 0) // (TDES) Processing Mode\r
+#define AT91C_TDES_TDESMOD ((unsigned int) 0x1 << 1) // (TDES) Single or Triple DES Mode\r
+#define AT91C_TDES_KEYMOD ((unsigned int) 0x1 << 4) // (TDES) Key Mode\r
+#define AT91C_TDES_SMOD ((unsigned int) 0x3 << 8) // (TDES) Start Mode\r
+#define AT91C_TDES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.\r
+#define AT91C_TDES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).\r
+#define AT91C_TDES_SMOD_PDC ((unsigned int) 0x2 << 8) // (TDES) PDC Mode (cf datasheet).\r
+#define AT91C_TDES_OPMOD ((unsigned int) 0x3 << 12) // (TDES) Operation Mode\r
+#define AT91C_TDES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode.\r
+#define AT91C_TDES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode.\r
+#define AT91C_TDES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode.\r
+#define AT91C_TDES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode.\r
+#define AT91C_TDES_LOD ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode\r
+#define AT91C_TDES_CFBS ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size\r
+#define AT91C_TDES_CFBS_64_BIT ((unsigned int) 0x0 << 16) // (TDES) 64-bit.\r
+#define AT91C_TDES_CFBS_32_BIT ((unsigned int) 0x1 << 16) // (TDES) 32-bit.\r
+#define AT91C_TDES_CFBS_16_BIT ((unsigned int) 0x2 << 16) // (TDES) 16-bit.\r
+#define AT91C_TDES_CFBS_8_BIT ((unsigned int) 0x3 << 16) // (TDES) 8-bit.\r
+// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- \r
+#define AT91C_TDES_DATRDY ((unsigned int) 0x1 << 0) // (TDES) DATRDY\r
+#define AT91C_TDES_ENDRX ((unsigned int) 0x1 << 1) // (TDES) PDC Read Buffer End\r
+#define AT91C_TDES_ENDTX ((unsigned int) 0x1 << 2) // (TDES) PDC Write Buffer End\r
+#define AT91C_TDES_RXBUFF ((unsigned int) 0x1 << 3) // (TDES) PDC Read Buffer Full\r
+#define AT91C_TDES_TXBUFE ((unsigned int) 0x1 << 4) // (TDES) PDC Write Buffer Empty\r
+#define AT91C_TDES_URAD ((unsigned int) 0x1 << 8) // (TDES) Unspecified Register Access Detection\r
+// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- \r
+// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- \r
+// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- \r
+#define AT91C_TDES_URAT ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status\r
+#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode.\r
+#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing.\r
+#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing.\r
+#define AT91C_TDES_URAT_WO_REG_READ ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access.\r
+\r
+// *****************************************************************************\r
+// REGISTER ADDRESS DEFINITION FOR AT91SAM7X128\r
+// *****************************************************************************\r
+// ========== Register definition for SYS peripheral ========== \r
+// ========== Register definition for AIC peripheral ========== \r
+#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register\r
+#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register\r
+#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register\r
+#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect)\r
+#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register\r
+#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register\r
+#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register\r
+#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register\r
+#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register\r
+#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register\r
+#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register\r
+#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register\r
+#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register\r
+#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register\r
+#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register\r
+#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register\r
+#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register\r
+#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register\r
+// ========== Register definition for PDC_DBGU peripheral ========== \r
+#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register\r
+#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register\r
+#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register\r
+#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register\r
+#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register\r
+#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register\r
+#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register\r
+#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register\r
+#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register\r
+#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register\r
+// ========== Register definition for DBGU peripheral ========== \r
+#define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register\r
+#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register\r
+#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register\r
+#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register\r
+#define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register\r
+#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register\r
+#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register\r
+#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register\r
+#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register\r
+#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register\r
+#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register\r
+#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register\r
+// ========== Register definition for PIOA peripheral ========== \r
+#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr\r
+#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register\r
+#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register\r
+#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register\r
+#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register\r
+#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register\r
+#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register\r
+#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register\r
+#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register\r
+#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register\r
+#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register\r
+#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register\r
+#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register\r
+#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register\r
+#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register\r
+#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register\r
+#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register\r
+#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register\r
+#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register\r
+#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register\r
+#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register\r
+#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register\r
+#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register\r
+#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register\r
+#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register\r
+#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register\r
+#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register\r
+#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register\r
+#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register\r
+// ========== Register definition for PIOB peripheral ========== \r
+#define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register\r
+#define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register\r
+#define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register\r
+#define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register\r
+#define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register\r
+#define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register\r
+#define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register\r
+#define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register\r
+#define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register\r
+#define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register\r
+#define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register\r
+#define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register\r
+#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register\r
+#define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register\r
+#define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register\r
+#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register\r
+#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr\r
+#define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register\r
+#define AT91C_PIOB_PPUER ((AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register\r
+#define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register\r
+#define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register\r
+#define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register\r
+#define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register\r
+#define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register\r
+#define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register\r
+#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register\r
+#define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register\r
+#define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register\r
+#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register\r
+// ========== Register definition for CKGR peripheral ========== \r
+#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register\r
+#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register\r
+#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register\r
+// ========== Register definition for PMC peripheral ========== \r
+#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register\r
+#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register\r
+#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register\r
+#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register\r
+#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register\r
+#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register\r
+#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register\r
+#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register\r
+#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register\r
+#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register\r
+#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register\r
+#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register\r
+#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register\r
+#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register\r
+#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register\r
+// ========== Register definition for RSTC peripheral ========== \r
+#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register\r
+#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register\r
+#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register\r
+// ========== Register definition for RTTC peripheral ========== \r
+#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register\r
+#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register\r
+#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register\r
+#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register\r
+// ========== Register definition for PITC peripheral ========== \r
+#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register\r
+#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register\r
+#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register\r
+#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register\r
+// ========== Register definition for WDTC peripheral ========== \r
+#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register\r
+#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register\r
+#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register\r
+// ========== Register definition for VREG peripheral ========== \r
+#define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register\r
+// ========== Register definition for MC peripheral ========== \r
+#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register\r
+#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register\r
+#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register\r
+#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register\r
+#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register\r
+#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register\r
+// ========== Register definition for PDC_SPI1 peripheral ========== \r
+#define AT91C_SPI1_PTCR ((AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register\r
+#define AT91C_SPI1_RPR ((AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register\r
+#define AT91C_SPI1_TNCR ((AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register\r
+#define AT91C_SPI1_TPR ((AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register\r
+#define AT91C_SPI1_TNPR ((AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register\r
+#define AT91C_SPI1_TCR ((AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register\r
+#define AT91C_SPI1_RCR ((AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register\r
+#define AT91C_SPI1_RNPR ((AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register\r
+#define AT91C_SPI1_RNCR ((AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register\r
+#define AT91C_SPI1_PTSR ((AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register\r
+// ========== Register definition for SPI1 peripheral ========== \r
+#define AT91C_SPI1_IMR ((AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register\r
+#define AT91C_SPI1_IER ((AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register\r
+#define AT91C_SPI1_MR ((AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register\r
+#define AT91C_SPI1_RDR ((AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register\r
+#define AT91C_SPI1_IDR ((AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register\r
+#define AT91C_SPI1_SR ((AT91_REG *) 0xFFFE4010) // (SPI1) Status Register\r
+#define AT91C_SPI1_TDR ((AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register\r
+#define AT91C_SPI1_CR ((AT91_REG *) 0xFFFE4000) // (SPI1) Control Register\r
+#define AT91C_SPI1_CSR ((AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register\r
+// ========== Register definition for PDC_SPI0 peripheral ========== \r
+#define AT91C_SPI0_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register\r
+#define AT91C_SPI0_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register\r
+#define AT91C_SPI0_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register\r
+#define AT91C_SPI0_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register\r
+#define AT91C_SPI0_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register\r
+#define AT91C_SPI0_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register\r
+#define AT91C_SPI0_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register\r
+#define AT91C_SPI0_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register\r
+#define AT91C_SPI0_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register\r
+#define AT91C_SPI0_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register\r
+// ========== Register definition for SPI0 peripheral ========== \r
+#define AT91C_SPI0_IER ((AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register\r
+#define AT91C_SPI0_SR ((AT91_REG *) 0xFFFE0010) // (SPI0) Status Register\r
+#define AT91C_SPI0_IDR ((AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register\r
+#define AT91C_SPI0_CR ((AT91_REG *) 0xFFFE0000) // (SPI0) Control Register\r
+#define AT91C_SPI0_MR ((AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register\r
+#define AT91C_SPI0_IMR ((AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register\r
+#define AT91C_SPI0_TDR ((AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register\r
+#define AT91C_SPI0_RDR ((AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register\r
+#define AT91C_SPI0_CSR ((AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register\r
+// ========== Register definition for PDC_US1 peripheral ========== \r
+#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register\r
+#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register\r
+#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register\r
+#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register\r
+#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register\r
+#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register\r
+#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register\r
+#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register\r
+#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register\r
+#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register\r
+// ========== Register definition for US1 peripheral ========== \r
+#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register\r
+#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register\r
+#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register\r
+#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register\r
+#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register\r
+#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register\r
+#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register\r
+#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register\r
+#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register\r
+#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register\r
+#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register\r
+#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register\r
+#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register\r
+#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register\r
+// ========== Register definition for PDC_US0 peripheral ========== \r
+#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register\r
+#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register\r
+#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register\r
+#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register\r
+#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register\r
+#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register\r
+#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register\r
+#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register\r
+#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register\r
+#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register\r
+// ========== Register definition for US0 peripheral ========== \r
+#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register\r
+#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register\r
+#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register\r
+#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register\r
+#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register\r
+#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register\r
+#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register\r
+#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register\r
+#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register\r
+#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register\r
+#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register\r
+#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register\r
+#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register\r
+#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register\r
+// ========== Register definition for PDC_SSC peripheral ========== \r
+#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register\r
+#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register\r
+#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register\r
+#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register\r
+#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register\r
+#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register\r
+#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register\r
+#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register\r
+#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register\r
+#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register\r
+// ========== Register definition for SSC peripheral ========== \r
+#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register\r
+#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register\r
+#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register\r
+#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register\r
+#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register\r
+#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister\r
+#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register\r
+#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register\r
+#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register\r
+#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register\r
+#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register\r
+#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register\r
+#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register\r
+#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register\r
+// ========== Register definition for TWI peripheral ========== \r
+#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register\r
+#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register\r
+#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register\r
+#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register\r
+#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register\r
+#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register\r
+#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register\r
+#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register\r
+#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register\r
+#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register\r
+// ========== Register definition for PWMC_CH3 peripheral ========== \r
+#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register\r
+#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved\r
+#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register\r
+#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register\r
+#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register\r
+#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register\r
+// ========== Register definition for PWMC_CH2 peripheral ========== \r
+#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved\r
+#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register\r
+#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register\r
+#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register\r
+#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register\r
+#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register\r
+// ========== Register definition for PWMC_CH1 peripheral ========== \r
+#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved\r
+#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register\r
+#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register\r
+#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register\r
+#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register\r
+#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register\r
+// ========== Register definition for PWMC_CH0 peripheral ========== \r
+#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved\r
+#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register\r
+#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register\r
+#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register\r
+#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register\r
+#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register\r
+// ========== Register definition for PWMC peripheral ========== \r
+#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register\r
+#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register\r
+#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register\r
+#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register\r
+#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register\r
+#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register\r
+#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register\r
+#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register\r
+#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register\r
+// ========== Register definition for UDP peripheral ========== \r
+#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register\r
+#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register\r
+#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register\r
+#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register\r
+#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register\r
+#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register\r
+#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register\r
+#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register\r
+#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register\r
+#define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register\r
+#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register\r
+#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register\r
+// ========== Register definition for TC0 peripheral ========== \r
+#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register\r
+#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C\r
+#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B\r
+#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register\r
+#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register\r
+#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A\r
+#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register\r
+#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value\r
+#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register\r
+// ========== Register definition for TC1 peripheral ========== \r
+#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B\r
+#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register\r
+#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register\r
+#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register\r
+#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register\r
+#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A\r
+#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C\r
+#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register\r
+#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value\r
+// ========== Register definition for TC2 peripheral ========== \r
+#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register\r
+#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value\r
+#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A\r
+#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B\r
+#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register\r
+#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register\r
+#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C\r
+#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register\r
+#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register\r
+// ========== Register definition for TCB peripheral ========== \r
+#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register\r
+#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register\r
+// ========== Register definition for CAN_MB0 peripheral ========== \r
+#define AT91C_CAN_MB0_MDL ((AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register\r
+#define AT91C_CAN_MB0_MAM ((AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register\r
+#define AT91C_CAN_MB0_MCR ((AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register\r
+#define AT91C_CAN_MB0_MID ((AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register\r
+#define AT91C_CAN_MB0_MSR ((AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register\r
+#define AT91C_CAN_MB0_MFID ((AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register\r
+#define AT91C_CAN_MB0_MDH ((AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register\r
+#define AT91C_CAN_MB0_MMR ((AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register\r
+// ========== Register definition for CAN_MB1 peripheral ========== \r
+#define AT91C_CAN_MB1_MDL ((AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register\r
+#define AT91C_CAN_MB1_MID ((AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register\r
+#define AT91C_CAN_MB1_MMR ((AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register\r
+#define AT91C_CAN_MB1_MSR ((AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register\r
+#define AT91C_CAN_MB1_MAM ((AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register\r
+#define AT91C_CAN_MB1_MDH ((AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register\r
+#define AT91C_CAN_MB1_MCR ((AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register\r
+#define AT91C_CAN_MB1_MFID ((AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register\r
+// ========== Register definition for CAN_MB2 peripheral ========== \r
+#define AT91C_CAN_MB2_MCR ((AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register\r
+#define AT91C_CAN_MB2_MDH ((AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register\r
+#define AT91C_CAN_MB2_MID ((AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register\r
+#define AT91C_CAN_MB2_MDL ((AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register\r
+#define AT91C_CAN_MB2_MMR ((AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register\r
+#define AT91C_CAN_MB2_MAM ((AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register\r
+#define AT91C_CAN_MB2_MFID ((AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register\r
+#define AT91C_CAN_MB2_MSR ((AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register\r
+// ========== Register definition for CAN_MB3 peripheral ========== \r
+#define AT91C_CAN_MB3_MFID ((AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register\r
+#define AT91C_CAN_MB3_MAM ((AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register\r
+#define AT91C_CAN_MB3_MID ((AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register\r
+#define AT91C_CAN_MB3_MCR ((AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register\r
+#define AT91C_CAN_MB3_MMR ((AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register\r
+#define AT91C_CAN_MB3_MSR ((AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register\r
+#define AT91C_CAN_MB3_MDL ((AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register\r
+#define AT91C_CAN_MB3_MDH ((AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register\r
+// ========== Register definition for CAN_MB4 peripheral ========== \r
+#define AT91C_CAN_MB4_MID ((AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register\r
+#define AT91C_CAN_MB4_MMR ((AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register\r
+#define AT91C_CAN_MB4_MDH ((AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register\r
+#define AT91C_CAN_MB4_MFID ((AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register\r
+#define AT91C_CAN_MB4_MSR ((AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register\r
+#define AT91C_CAN_MB4_MCR ((AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register\r
+#define AT91C_CAN_MB4_MDL ((AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register\r
+#define AT91C_CAN_MB4_MAM ((AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register\r
+// ========== Register definition for CAN_MB5 peripheral ========== \r
+#define AT91C_CAN_MB5_MSR ((AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register\r
+#define AT91C_CAN_MB5_MCR ((AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register\r
+#define AT91C_CAN_MB5_MFID ((AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register\r
+#define AT91C_CAN_MB5_MDH ((AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register\r
+#define AT91C_CAN_MB5_MID ((AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register\r
+#define AT91C_CAN_MB5_MMR ((AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register\r
+#define AT91C_CAN_MB5_MDL ((AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register\r
+#define AT91C_CAN_MB5_MAM ((AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register\r
+// ========== Register definition for CAN_MB6 peripheral ========== \r
+#define AT91C_CAN_MB6_MFID ((AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register\r
+#define AT91C_CAN_MB6_MID ((AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register\r
+#define AT91C_CAN_MB6_MAM ((AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register\r
+#define AT91C_CAN_MB6_MSR ((AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register\r
+#define AT91C_CAN_MB6_MDL ((AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register\r
+#define AT91C_CAN_MB6_MCR ((AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register\r
+#define AT91C_CAN_MB6_MDH ((AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register\r
+#define AT91C_CAN_MB6_MMR ((AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register\r
+// ========== Register definition for CAN_MB7 peripheral ========== \r
+#define AT91C_CAN_MB7_MCR ((AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register\r
+#define AT91C_CAN_MB7_MDH ((AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register\r
+#define AT91C_CAN_MB7_MFID ((AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register\r
+#define AT91C_CAN_MB7_MDL ((AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register\r
+#define AT91C_CAN_MB7_MID ((AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register\r
+#define AT91C_CAN_MB7_MMR ((AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register\r
+#define AT91C_CAN_MB7_MAM ((AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register\r
+#define AT91C_CAN_MB7_MSR ((AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register\r
+// ========== Register definition for CAN peripheral ========== \r
+#define AT91C_CAN_TCR ((AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register\r
+#define AT91C_CAN_IMR ((AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register\r
+#define AT91C_CAN_IER ((AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register\r
+#define AT91C_CAN_ECR ((AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register\r
+#define AT91C_CAN_TIMESTP ((AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register\r
+#define AT91C_CAN_MR ((AT91_REG *) 0xFFFD0000) // (CAN) Mode Register\r
+#define AT91C_CAN_IDR ((AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register\r
+#define AT91C_CAN_ACR ((AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register\r
+#define AT91C_CAN_TIM ((AT91_REG *) 0xFFFD0018) // (CAN) Timer Register\r
+#define AT91C_CAN_SR ((AT91_REG *) 0xFFFD0010) // (CAN) Status Register\r
+#define AT91C_CAN_BR ((AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register\r
+#define AT91C_CAN_VR ((AT91_REG *) 0xFFFD00FC) // (CAN) Version Register\r
+// ========== Register definition for EMAC peripheral ========== \r
+#define AT91C_EMAC_ISR ((AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register\r
+#define AT91C_EMAC_SA4H ((AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes\r
+#define AT91C_EMAC_SA1L ((AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes\r
+#define AT91C_EMAC_ELE ((AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register\r
+#define AT91C_EMAC_LCOL ((AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register\r
+#define AT91C_EMAC_RLE ((AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register\r
+#define AT91C_EMAC_WOL ((AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register\r
+#define AT91C_EMAC_DTF ((AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register\r
+#define AT91C_EMAC_TUND ((AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register\r
+#define AT91C_EMAC_NCR ((AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register\r
+#define AT91C_EMAC_SA4L ((AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes\r
+#define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register\r
+#define AT91C_EMAC_SA3L ((AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes\r
+#define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register\r
+#define AT91C_EMAC_IDR ((AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register\r
+#define AT91C_EMAC_RSE ((AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register\r
+#define AT91C_EMAC_ECOL ((AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register\r
+#define AT91C_EMAC_TID ((AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register\r
+#define AT91C_EMAC_HRB ((AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]\r
+#define AT91C_EMAC_TBQP ((AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer\r
+#define AT91C_EMAC_USRIO ((AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register\r
+#define AT91C_EMAC_PTR ((AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register\r
+#define AT91C_EMAC_SA2H ((AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes\r
+#define AT91C_EMAC_ROV ((AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register\r
+#define AT91C_EMAC_ALE ((AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register\r
+#define AT91C_EMAC_RJA ((AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register\r
+#define AT91C_EMAC_RBQP ((AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer\r
+#define AT91C_EMAC_TPF ((AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register\r
+#define AT91C_EMAC_NCFGR ((AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register\r
+#define AT91C_EMAC_HRT ((AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32]\r
+#define AT91C_EMAC_USF ((AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register\r
+#define AT91C_EMAC_FCSE ((AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register\r
+#define AT91C_EMAC_TPQ ((AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register\r
+#define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register\r
+#define AT91C_EMAC_FTO ((AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register\r
+#define AT91C_EMAC_REV ((AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register\r
+#define AT91C_EMAC_IMR ((AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register\r
+#define AT91C_EMAC_SCF ((AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register\r
+#define AT91C_EMAC_PFR ((AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register\r
+#define AT91C_EMAC_MCF ((AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register\r
+#define AT91C_EMAC_NSR ((AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register\r
+#define AT91C_EMAC_SA2L ((AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes\r
+#define AT91C_EMAC_FRO ((AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register\r
+#define AT91C_EMAC_IER ((AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register\r
+#define AT91C_EMAC_SA1H ((AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes\r
+#define AT91C_EMAC_CSE ((AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register\r
+#define AT91C_EMAC_SA3H ((AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes\r
+#define AT91C_EMAC_RRE ((AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register\r
+#define AT91C_EMAC_STE ((AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register\r
+// ========== Register definition for PDC_ADC peripheral ========== \r
+#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register\r
+#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register\r
+#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register\r
+#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register\r
+#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register\r
+#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register\r
+#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register\r
+#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register\r
+#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register\r
+#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register\r
+// ========== Register definition for ADC peripheral ========== \r
+#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2\r
+#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3\r
+#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0\r
+#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5\r
+#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register\r
+#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register\r
+#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4\r
+#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1\r
+#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register\r
+#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register\r
+#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register\r
+#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7\r
+#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6\r
+#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register\r
+#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register\r
+#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register\r
+#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register\r
+#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register\r
+// ========== Register definition for PDC_AES peripheral ========== \r
+#define AT91C_AES_TPR ((AT91_REG *) 0xFFFA4108) // (PDC_AES) Transmit Pointer Register\r
+#define AT91C_AES_PTCR ((AT91_REG *) 0xFFFA4120) // (PDC_AES) PDC Transfer Control Register\r
+#define AT91C_AES_RNPR ((AT91_REG *) 0xFFFA4110) // (PDC_AES) Receive Next Pointer Register\r
+#define AT91C_AES_TNCR ((AT91_REG *) 0xFFFA411C) // (PDC_AES) Transmit Next Counter Register\r
+#define AT91C_AES_TCR ((AT91_REG *) 0xFFFA410C) // (PDC_AES) Transmit Counter Register\r
+#define AT91C_AES_RCR ((AT91_REG *) 0xFFFA4104) // (PDC_AES) Receive Counter Register\r
+#define AT91C_AES_RNCR ((AT91_REG *) 0xFFFA4114) // (PDC_AES) Receive Next Counter Register\r
+#define AT91C_AES_TNPR ((AT91_REG *) 0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register\r
+#define AT91C_AES_RPR ((AT91_REG *) 0xFFFA4100) // (PDC_AES) Receive Pointer Register\r
+#define AT91C_AES_PTSR ((AT91_REG *) 0xFFFA4124) // (PDC_AES) PDC Transfer Status Register\r
+// ========== Register definition for AES peripheral ========== \r
+#define AT91C_AES_IVxR ((AT91_REG *) 0xFFFA4060) // (AES) Initialization Vector x Register\r
+#define AT91C_AES_MR ((AT91_REG *) 0xFFFA4004) // (AES) Mode Register\r
+#define AT91C_AES_VR ((AT91_REG *) 0xFFFA40FC) // (AES) AES Version Register\r
+#define AT91C_AES_ODATAxR ((AT91_REG *) 0xFFFA4050) // (AES) Output Data x Register\r
+#define AT91C_AES_IDATAxR ((AT91_REG *) 0xFFFA4040) // (AES) Input Data x Register\r
+#define AT91C_AES_CR ((AT91_REG *) 0xFFFA4000) // (AES) Control Register\r
+#define AT91C_AES_IDR ((AT91_REG *) 0xFFFA4014) // (AES) Interrupt Disable Register\r
+#define AT91C_AES_IMR ((AT91_REG *) 0xFFFA4018) // (AES) Interrupt Mask Register\r
+#define AT91C_AES_IER ((AT91_REG *) 0xFFFA4010) // (AES) Interrupt Enable Register\r
+#define AT91C_AES_KEYWxR ((AT91_REG *) 0xFFFA4020) // (AES) Key Word x Register\r
+#define AT91C_AES_ISR ((AT91_REG *) 0xFFFA401C) // (AES) Interrupt Status Register\r
+// ========== Register definition for PDC_TDES peripheral ========== \r
+#define AT91C_TDES_RNCR ((AT91_REG *) 0xFFFA8114) // (PDC_TDES) Receive Next Counter Register\r
+#define AT91C_TDES_TCR ((AT91_REG *) 0xFFFA810C) // (PDC_TDES) Transmit Counter Register\r
+#define AT91C_TDES_RCR ((AT91_REG *) 0xFFFA8104) // (PDC_TDES) Receive Counter Register\r
+#define AT91C_TDES_TNPR ((AT91_REG *) 0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register\r
+#define AT91C_TDES_RNPR ((AT91_REG *) 0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register\r
+#define AT91C_TDES_RPR ((AT91_REG *) 0xFFFA8100) // (PDC_TDES) Receive Pointer Register\r
+#define AT91C_TDES_TNCR ((AT91_REG *) 0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register\r
+#define AT91C_TDES_TPR ((AT91_REG *) 0xFFFA8108) // (PDC_TDES) Transmit Pointer Register\r
+#define AT91C_TDES_PTSR ((AT91_REG *) 0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register\r
+#define AT91C_TDES_PTCR ((AT91_REG *) 0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register\r
+// ========== Register definition for TDES peripheral ========== \r
+#define AT91C_TDES_KEY2WxR ((AT91_REG *) 0xFFFA8028) // (TDES) Key 2 Word x Register\r
+#define AT91C_TDES_KEY3WxR ((AT91_REG *) 0xFFFA8030) // (TDES) Key 3 Word x Register\r
+#define AT91C_TDES_IDR ((AT91_REG *) 0xFFFA8014) // (TDES) Interrupt Disable Register\r
+#define AT91C_TDES_VR ((AT91_REG *) 0xFFFA80FC) // (TDES) TDES Version Register\r
+#define AT91C_TDES_IVxR ((AT91_REG *) 0xFFFA8060) // (TDES) Initialization Vector x Register\r
+#define AT91C_TDES_ODATAxR ((AT91_REG *) 0xFFFA8050) // (TDES) Output Data x Register\r
+#define AT91C_TDES_IMR ((AT91_REG *) 0xFFFA8018) // (TDES) Interrupt Mask Register\r
+#define AT91C_TDES_MR ((AT91_REG *) 0xFFFA8004) // (TDES) Mode Register\r
+#define AT91C_TDES_CR ((AT91_REG *) 0xFFFA8000) // (TDES) Control Register\r
+#define AT91C_TDES_IER ((AT91_REG *) 0xFFFA8010) // (TDES) Interrupt Enable Register\r
+#define AT91C_TDES_ISR ((AT91_REG *) 0xFFFA801C) // (TDES) Interrupt Status Register\r
+#define AT91C_TDES_IDATAxR ((AT91_REG *) 0xFFFA8040) // (TDES) Input Data x Register\r
+#define AT91C_TDES_KEY1WxR ((AT91_REG *) 0xFFFA8020) // (TDES) Key 1 Word x Register\r
+\r
+// *****************************************************************************\r
+// PIO DEFINITIONS FOR AT91SAM7X128\r
+// *****************************************************************************\r
+#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0\r
+#define AT91C_PA0_RXD0 ((unsigned int) AT91C_PIO_PA0) // USART 0 Receive Data\r
+#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1\r
+#define AT91C_PA1_TXD0 ((unsigned int) AT91C_PIO_PA1) // USART 0 Transmit Data\r
+#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10\r
+#define AT91C_PA10_TWD ((unsigned int) AT91C_PIO_PA10) // TWI Two-wire Serial Data\r
+#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11\r
+#define AT91C_PA11_TWCK ((unsigned int) AT91C_PIO_PA11) // TWI Two-wire Serial Clock\r
+#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12\r
+#define AT91C_PA12_NPCS00 ((unsigned int) AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0\r
+#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13\r
+#define AT91C_PA13_NPCS01 ((unsigned int) AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1\r
+#define AT91C_PA13_PCK1 ((unsigned int) AT91C_PIO_PA13) // PMC Programmable Clock Output 1\r
+#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14\r
+#define AT91C_PA14_NPCS02 ((unsigned int) AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2\r
+#define AT91C_PA14_IRQ1 ((unsigned int) AT91C_PIO_PA14) // External Interrupt 1\r
+#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15\r
+#define AT91C_PA15_NPCS03 ((unsigned int) AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3\r
+#define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input\r
+#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16\r
+#define AT91C_PA16_MISO0 ((unsigned int) AT91C_PIO_PA16) // SPI 0 Master In Slave\r
+#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17\r
+#define AT91C_PA17_MOSI0 ((unsigned int) AT91C_PIO_PA17) // SPI 0 Master Out Slave\r
+#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18\r
+#define AT91C_PA18_SPCK0 ((unsigned int) AT91C_PIO_PA18) // SPI 0 Serial Clock\r
+#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19\r
+#define AT91C_PA19_CANRX ((unsigned int) AT91C_PIO_PA19) // CAN Receive\r
+#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2\r
+#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock\r
+#define AT91C_PA2_NPCS11 ((unsigned int) AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1\r
+#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20\r
+#define AT91C_PA20_CANTX ((unsigned int) AT91C_PIO_PA20) // CAN Transmit\r
+#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21\r
+#define AT91C_PA21_TF ((unsigned int) AT91C_PIO_PA21) // SSC Transmit Frame Sync\r
+#define AT91C_PA21_NPCS10 ((unsigned int) AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0\r
+#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22\r
+#define AT91C_PA22_TK ((unsigned int) AT91C_PIO_PA22) // SSC Transmit Clock\r
+#define AT91C_PA22_SPCK1 ((unsigned int) AT91C_PIO_PA22) // SPI 1 Serial Clock\r
+#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23\r
+#define AT91C_PA23_TD ((unsigned int) AT91C_PIO_PA23) // SSC Transmit data\r
+#define AT91C_PA23_MOSI1 ((unsigned int) AT91C_PIO_PA23) // SPI 1 Master Out Slave\r
+#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24\r
+#define AT91C_PA24_RD ((unsigned int) AT91C_PIO_PA24) // SSC Receive Data\r
+#define AT91C_PA24_MISO1 ((unsigned int) AT91C_PIO_PA24) // SPI 1 Master In Slave\r
+#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25\r
+#define AT91C_PA25_RK ((unsigned int) AT91C_PIO_PA25) // SSC Receive Clock\r
+#define AT91C_PA25_NPCS11 ((unsigned int) AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1\r
+#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26\r
+#define AT91C_PA26_RF ((unsigned int) AT91C_PIO_PA26) // SSC Receive Frame Sync\r
+#define AT91C_PA26_NPCS12 ((unsigned int) AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2\r
+#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27\r
+#define AT91C_PA27_DRXD ((unsigned int) AT91C_PIO_PA27) // DBGU Debug Receive Data\r
+#define AT91C_PA27_PCK3 ((unsigned int) AT91C_PIO_PA27) // PMC Programmable Clock Output 3\r
+#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28\r
+#define AT91C_PA28_DTXD ((unsigned int) AT91C_PIO_PA28) // DBGU Debug Transmit Data\r
+#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29\r
+#define AT91C_PA29_FIQ ((unsigned int) AT91C_PIO_PA29) // AIC Fast Interrupt Input\r
+#define AT91C_PA29_NPCS13 ((unsigned int) AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3\r
+#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3\r
+#define AT91C_PA3_RTS0 ((unsigned int) AT91C_PIO_PA3) // USART 0 Ready To Send\r
+#define AT91C_PA3_NPCS12 ((unsigned int) AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2\r
+#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30\r
+#define AT91C_PA30_IRQ0 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 0\r
+#define AT91C_PA30_PCK2 ((unsigned int) AT91C_PIO_PA30) // PMC Programmable Clock Output 2\r
+#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4\r
+#define AT91C_PA4_CTS0 ((unsigned int) AT91C_PIO_PA4) // USART 0 Clear To Send\r
+#define AT91C_PA4_NPCS13 ((unsigned int) AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3\r
+#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5\r
+#define AT91C_PA5_RXD1 ((unsigned int) AT91C_PIO_PA5) // USART 1 Receive Data\r
+#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6\r
+#define AT91C_PA6_TXD1 ((unsigned int) AT91C_PIO_PA6) // USART 1 Transmit Data\r
+#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7\r
+#define AT91C_PA7_SCK1 ((unsigned int) AT91C_PIO_PA7) // USART 1 Serial Clock\r
+#define AT91C_PA7_NPCS01 ((unsigned int) AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1\r
+#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8\r
+#define AT91C_PA8_RTS1 ((unsigned int) AT91C_PIO_PA8) // USART 1 Ready To Send\r
+#define AT91C_PA8_NPCS02 ((unsigned int) AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2\r
+#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9\r
+#define AT91C_PA9_CTS1 ((unsigned int) AT91C_PIO_PA9) // USART 1 Clear To Send\r
+#define AT91C_PA9_NPCS03 ((unsigned int) AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3\r
+#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0\r
+#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock\r
+#define AT91C_PB0_PCK0 ((unsigned int) AT91C_PIO_PB0) // PMC Programmable Clock Output 0\r
+#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1\r
+#define AT91C_PB1_ETXEN ((unsigned int) AT91C_PIO_PB1) // Ethernet MAC Transmit Enable\r
+#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10\r
+#define AT91C_PB10_ETX2 ((unsigned int) AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2\r
+#define AT91C_PB10_NPCS11 ((unsigned int) AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1\r
+#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11\r
+#define AT91C_PB11_ETX3 ((unsigned int) AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3\r
+#define AT91C_PB11_NPCS12 ((unsigned int) AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2\r
+#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12\r
+#define AT91C_PB12_ETXER ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error\r
+#define AT91C_PB12_TCLK0 ((unsigned int) AT91C_PIO_PB12) // Timer Counter 0 external clock input\r
+#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13\r
+#define AT91C_PB13_ERX2 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Receive Data 2\r
+#define AT91C_PB13_NPCS01 ((unsigned int) AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1\r
+#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14\r
+#define AT91C_PB14_ERX3 ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Receive Data 3\r
+#define AT91C_PB14_NPCS02 ((unsigned int) AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2\r
+#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15\r
+#define AT91C_PB15_ERXDV ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid\r
+#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16\r
+#define AT91C_PB16_ECOL ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Collision Detected\r
+#define AT91C_PB16_NPCS13 ((unsigned int) AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3\r
+#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17\r
+#define AT91C_PB17_ERXCK ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Clock\r
+#define AT91C_PB17_NPCS03 ((unsigned int) AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3\r
+#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18\r
+#define AT91C_PB18_EF100 ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec\r
+#define AT91C_PB18_ADTRG ((unsigned int) AT91C_PIO_PB18) // ADC External Trigger\r
+#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19\r
+#define AT91C_PB19_PWM0 ((unsigned int) AT91C_PIO_PB19) // PWM Channel 0\r
+#define AT91C_PB19_TCLK1 ((unsigned int) AT91C_PIO_PB19) // Timer Counter 1 external clock input\r
+#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2\r
+#define AT91C_PB2_ETX0 ((unsigned int) AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0\r
+#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20\r
+#define AT91C_PB20_PWM1 ((unsigned int) AT91C_PIO_PB20) // PWM Channel 1\r
+#define AT91C_PB20_PCK0 ((unsigned int) AT91C_PIO_PB20) // PMC Programmable Clock Output 0\r
+#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21\r
+#define AT91C_PB21_PWM2 ((unsigned int) AT91C_PIO_PB21) // PWM Channel 2\r
+#define AT91C_PB21_PCK1 ((unsigned int) AT91C_PIO_PB21) // PMC Programmable Clock Output 1\r
+#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22\r
+#define AT91C_PB22_PWM3 ((unsigned int) AT91C_PIO_PB22) // PWM Channel 3\r
+#define AT91C_PB22_PCK2 ((unsigned int) AT91C_PIO_PB22) // PMC Programmable Clock Output 2\r
+#define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23\r
+#define AT91C_PB23_TIOA0 ((unsigned int) AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A\r
+#define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect\r
+#define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24\r
+#define AT91C_PB24_TIOB0 ((unsigned int) AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B\r
+#define AT91C_PB24_DSR1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Data Set ready\r
+#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25\r
+#define AT91C_PB25_TIOA1 ((unsigned int) AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A\r
+#define AT91C_PB25_DTR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Terminal ready\r
+#define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26\r
+#define AT91C_PB26_TIOB1 ((unsigned int) AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B\r
+#define AT91C_PB26_RI1 ((unsigned int) AT91C_PIO_PB26) // USART 1 Ring Indicator\r
+#define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27\r
+#define AT91C_PB27_TIOA2 ((unsigned int) AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A\r
+#define AT91C_PB27_PWM0 ((unsigned int) AT91C_PIO_PB27) // PWM Channel 0\r
+#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28\r
+#define AT91C_PB28_TIOB2 ((unsigned int) AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B\r
+#define AT91C_PB28_PWM1 ((unsigned int) AT91C_PIO_PB28) // PWM Channel 1\r
+#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29\r
+#define AT91C_PB29_PCK1 ((unsigned int) AT91C_PIO_PB29) // PMC Programmable Clock Output 1\r
+#define AT91C_PB29_PWM2 ((unsigned int) AT91C_PIO_PB29) // PWM Channel 2\r
+#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3\r
+#define AT91C_PB3_ETX1 ((unsigned int) AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1\r
+#define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30\r
+#define AT91C_PB30_PCK2 ((unsigned int) AT91C_PIO_PB30) // PMC Programmable Clock Output 2\r
+#define AT91C_PB30_PWM3 ((unsigned int) AT91C_PIO_PB30) // PWM Channel 3\r
+#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4\r
+#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid\r
+#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5\r
+#define AT91C_PB5_ERX0 ((unsigned int) AT91C_PIO_PB5) // Ethernet MAC Receive Data 0\r
+#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6\r
+#define AT91C_PB6_ERX1 ((unsigned int) AT91C_PIO_PB6) // Ethernet MAC Receive Data 1\r
+#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7\r
+#define AT91C_PB7_ERXER ((unsigned int) AT91C_PIO_PB7) // Ethernet MAC Receive Error\r
+#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8\r
+#define AT91C_PB8_EMDC ((unsigned int) AT91C_PIO_PB8) // Ethernet MAC Management Data Clock\r
+#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9\r
+#define AT91C_PB9_EMDIO ((unsigned int) AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output\r
+\r
+// *****************************************************************************\r
+// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X128\r
+// *****************************************************************************\r
+#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ)\r
+#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral\r
+#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller A\r
+#define AT91C_ID_PIOB ((unsigned int) 3) // Parallel IO Controller B\r
+#define AT91C_ID_SPI0 ((unsigned int) 4) // Serial Peripheral Interface 0\r
+#define AT91C_ID_SPI1 ((unsigned int) 5) // Serial Peripheral Interface 1\r
+#define AT91C_ID_US0 ((unsigned int) 6) // USART 0\r
+#define AT91C_ID_US1 ((unsigned int) 7) // USART 1\r
+#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller\r
+#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface\r
+#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller\r
+#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port\r
+#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0\r
+#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1\r
+#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2\r
+#define AT91C_ID_CAN ((unsigned int) 15) // Control Area Network Controller\r
+#define AT91C_ID_EMAC ((unsigned int) 16) // Ethernet MAC\r
+#define AT91C_ID_ADC ((unsigned int) 17) // Analog-to-Digital Converter\r
+#define AT91C_ID_AES ((unsigned int) 18) // Advanced Encryption Standard 128-bit\r
+#define AT91C_ID_TDES ((unsigned int) 19) // Triple Data Encryption Standard\r
+#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved\r
+#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved\r
+#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved\r
+#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved\r
+#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved\r
+#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved\r
+#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved\r
+#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved\r
+#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved\r
+#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved\r
+#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0)\r
+#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1)\r
+\r
+// *****************************************************************************\r
+// BASE ADDRESS DEFINITIONS FOR AT91SAM7X128\r
+// *****************************************************************************\r
+#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address\r
+#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address\r
+#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address\r
+#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address\r
+#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address\r
+#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address\r
+#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address\r
+#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address\r
+#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address\r
+#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address\r
+#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address\r
+#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address\r
+#define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address\r
+#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address\r
+#define AT91C_BASE_PDC_SPI1 ((AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address\r
+#define AT91C_BASE_SPI1 ((AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address\r
+#define AT91C_BASE_PDC_SPI0 ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address\r
+#define AT91C_BASE_SPI0 ((AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address\r
+#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address\r
+#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address\r
+#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address\r
+#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address\r
+#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address\r
+#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address\r
+#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address\r
+#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address\r
+#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address\r
+#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address\r
+#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address\r
+#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address\r
+#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address\r
+#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address\r
+#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address\r
+#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address\r
+#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address\r
+#define AT91C_BASE_CAN_MB0 ((AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address\r
+#define AT91C_BASE_CAN_MB1 ((AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address\r
+#define AT91C_BASE_CAN_MB2 ((AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address\r
+#define AT91C_BASE_CAN_MB3 ((AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address\r
+#define AT91C_BASE_CAN_MB4 ((AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address\r
+#define AT91C_BASE_CAN_MB5 ((AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address\r
+#define AT91C_BASE_CAN_MB6 ((AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address\r
+#define AT91C_BASE_CAN_MB7 ((AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address\r
+#define AT91C_BASE_CAN ((AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address\r
+#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address\r
+#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address\r
+#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address\r
+#define AT91C_BASE_PDC_AES ((AT91PS_PDC) 0xFFFA4100) // (PDC_AES) Base Address\r
+#define AT91C_BASE_AES ((AT91PS_AES) 0xFFFA4000) // (AES) Base Address\r
+#define AT91C_BASE_PDC_TDES ((AT91PS_PDC) 0xFFFA8100) // (PDC_TDES) Base Address\r
+#define AT91C_BASE_TDES ((AT91PS_TDES) 0xFFFA8000) // (TDES) Base Address\r
+\r
+// *****************************************************************************\r
+// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X128\r
+// *****************************************************************************\r
+#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address\r
+#define AT91C_ISRAM_SIZE ((unsigned int) 0x00008000) // Internal SRAM size in byte (32 Kbyte)\r
+#define AT91C_IFLASH ((char *) 0x00100000) // Internal ROM base address\r
+#define AT91C_IFLASH_SIZE ((unsigned int) 0x00020000) // Internal ROM size in byte (128 Kbyte)\r
+#endif /* __IAR_SYSTEMS_ICC__ */\r
+\r
+#ifdef __IAR_SYSTEMS_ASM__\r
+\r
+// - Hardware register definition\r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR System Peripherals\r
+// - *****************************************************************************\r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Advanced Interrupt Controller\r
+// - *****************************************************************************\r
+// - -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- \r
+AT91C_AIC_PRIOR EQU (0x7 << 0) ;- (AIC) Priority Level\r
+AT91C_AIC_PRIOR_LOWEST EQU (0x0) ;- (AIC) Lowest priority level\r
+AT91C_AIC_PRIOR_HIGHEST EQU (0x7) ;- (AIC) Highest priority level\r
+AT91C_AIC_SRCTYPE EQU (0x3 << 5) ;- (AIC) Interrupt Source Type\r
+AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL EQU (0x0 << 5) ;- (AIC) Internal Sources Code Label High-level Sensitive\r
+AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL EQU (0x0 << 5) ;- (AIC) External Sources Code Label Low-level Sensitive\r
+AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE EQU (0x1 << 5) ;- (AIC) Internal Sources Code Label Positive Edge triggered\r
+AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE EQU (0x1 << 5) ;- (AIC) External Sources Code Label Negative Edge triggered\r
+AT91C_AIC_SRCTYPE_HIGH_LEVEL EQU (0x2 << 5) ;- (AIC) Internal Or External Sources Code Label High-level Sensitive\r
+AT91C_AIC_SRCTYPE_POSITIVE_EDGE EQU (0x3 << 5) ;- (AIC) Internal Or External Sources Code Label Positive Edge triggered\r
+// - -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- \r
+AT91C_AIC_NFIQ EQU (0x1 << 0) ;- (AIC) NFIQ Status\r
+AT91C_AIC_NIRQ EQU (0x1 << 1) ;- (AIC) NIRQ Status\r
+// - -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- \r
+AT91C_AIC_DCR_PROT EQU (0x1 << 0) ;- (AIC) Protection Mode\r
+AT91C_AIC_DCR_GMSK EQU (0x1 << 1) ;- (AIC) General Mask\r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Peripheral DMA Controller\r
+// - *****************************************************************************\r
+// - -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- \r
+AT91C_PDC_RXTEN EQU (0x1 << 0) ;- (PDC) Receiver Transfer Enable\r
+AT91C_PDC_RXTDIS EQU (0x1 << 1) ;- (PDC) Receiver Transfer Disable\r
+AT91C_PDC_TXTEN EQU (0x1 << 8) ;- (PDC) Transmitter Transfer Enable\r
+AT91C_PDC_TXTDIS EQU (0x1 << 9) ;- (PDC) Transmitter Transfer Disable\r
+// - -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- \r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Debug Unit\r
+// - *****************************************************************************\r
+// - -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- \r
+AT91C_US_RSTRX EQU (0x1 << 2) ;- (DBGU) Reset Receiver\r
+AT91C_US_RSTTX EQU (0x1 << 3) ;- (DBGU) Reset Transmitter\r
+AT91C_US_RXEN EQU (0x1 << 4) ;- (DBGU) Receiver Enable\r
+AT91C_US_RXDIS EQU (0x1 << 5) ;- (DBGU) Receiver Disable\r
+AT91C_US_TXEN EQU (0x1 << 6) ;- (DBGU) Transmitter Enable\r
+AT91C_US_TXDIS EQU (0x1 << 7) ;- (DBGU) Transmitter Disable\r
+AT91C_US_RSTSTA EQU (0x1 << 8) ;- (DBGU) Reset Status Bits\r
+// - -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- \r
+AT91C_US_PAR EQU (0x7 << 9) ;- (DBGU) Parity type\r
+AT91C_US_PAR_EVEN EQU (0x0 << 9) ;- (DBGU) Even Parity\r
+AT91C_US_PAR_ODD EQU (0x1 << 9) ;- (DBGU) Odd Parity\r
+AT91C_US_PAR_SPACE EQU (0x2 << 9) ;- (DBGU) Parity forced to 0 (Space)\r
+AT91C_US_PAR_MARK EQU (0x3 << 9) ;- (DBGU) Parity forced to 1 (Mark)\r
+AT91C_US_PAR_NONE EQU (0x4 << 9) ;- (DBGU) No Parity\r
+AT91C_US_PAR_MULTI_DROP EQU (0x6 << 9) ;- (DBGU) Multi-drop mode\r
+AT91C_US_CHMODE EQU (0x3 << 14) ;- (DBGU) Channel Mode\r
+AT91C_US_CHMODE_NORMAL EQU (0x0 << 14) ;- (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.\r
+AT91C_US_CHMODE_AUTO EQU (0x1 << 14) ;- (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.\r
+AT91C_US_CHMODE_LOCAL EQU (0x2 << 14) ;- (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.\r
+AT91C_US_CHMODE_REMOTE EQU (0x3 << 14) ;- (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.\r
+// - -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- \r
+AT91C_US_RXRDY EQU (0x1 << 0) ;- (DBGU) RXRDY Interrupt\r
+AT91C_US_TXRDY EQU (0x1 << 1) ;- (DBGU) TXRDY Interrupt\r
+AT91C_US_ENDRX EQU (0x1 << 3) ;- (DBGU) End of Receive Transfer Interrupt\r
+AT91C_US_ENDTX EQU (0x1 << 4) ;- (DBGU) End of Transmit Interrupt\r
+AT91C_US_OVRE EQU (0x1 << 5) ;- (DBGU) Overrun Interrupt\r
+AT91C_US_FRAME EQU (0x1 << 6) ;- (DBGU) Framing Error Interrupt\r
+AT91C_US_PARE EQU (0x1 << 7) ;- (DBGU) Parity Error Interrupt\r
+AT91C_US_TXEMPTY EQU (0x1 << 9) ;- (DBGU) TXEMPTY Interrupt\r
+AT91C_US_TXBUFE EQU (0x1 << 11) ;- (DBGU) TXBUFE Interrupt\r
+AT91C_US_RXBUFF EQU (0x1 << 12) ;- (DBGU) RXBUFF Interrupt\r
+AT91C_US_COMM_TX EQU (0x1 << 30) ;- (DBGU) COMM_TX Interrupt\r
+AT91C_US_COMM_RX EQU (0x1 << 31) ;- (DBGU) COMM_RX Interrupt\r
+// - -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- \r
+// - -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- \r
+// - -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- \r
+// - -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- \r
+AT91C_US_FORCE_NTRST EQU (0x1 << 0) ;- (DBGU) Force NTRST in JTAG\r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Parallel Input Output Controler\r
+// - *****************************************************************************\r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Clock Generator Controler\r
+// - *****************************************************************************\r
+// - -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- \r
+AT91C_CKGR_MOSCEN EQU (0x1 << 0) ;- (CKGR) Main Oscillator Enable\r
+AT91C_CKGR_OSCBYPASS EQU (0x1 << 1) ;- (CKGR) Main Oscillator Bypass\r
+AT91C_CKGR_OSCOUNT EQU (0xFF << 8) ;- (CKGR) Main Oscillator Start-up Time\r
+// - -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- \r
+AT91C_CKGR_MAINF EQU (0xFFFF << 0) ;- (CKGR) Main Clock Frequency\r
+AT91C_CKGR_MAINRDY EQU (0x1 << 16) ;- (CKGR) Main Clock Ready\r
+// - -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- \r
+AT91C_CKGR_DIV EQU (0xFF << 0) ;- (CKGR) Divider Selected\r
+AT91C_CKGR_DIV_0 EQU (0x0) ;- (CKGR) Divider output is 0\r
+AT91C_CKGR_DIV_BYPASS EQU (0x1) ;- (CKGR) Divider is bypassed\r
+AT91C_CKGR_PLLCOUNT EQU (0x3F << 8) ;- (CKGR) PLL Counter\r
+AT91C_CKGR_OUT EQU (0x3 << 14) ;- (CKGR) PLL Output Frequency Range\r
+AT91C_CKGR_OUT_0 EQU (0x0 << 14) ;- (CKGR) Please refer to the PLL datasheet\r
+AT91C_CKGR_OUT_1 EQU (0x1 << 14) ;- (CKGR) Please refer to the PLL datasheet\r
+AT91C_CKGR_OUT_2 EQU (0x2 << 14) ;- (CKGR) Please refer to the PLL datasheet\r
+AT91C_CKGR_OUT_3 EQU (0x3 << 14) ;- (CKGR) Please refer to the PLL datasheet\r
+AT91C_CKGR_MUL EQU (0x7FF << 16) ;- (CKGR) PLL Multiplier\r
+AT91C_CKGR_USBDIV EQU (0x3 << 28) ;- (CKGR) Divider for USB Clocks\r
+AT91C_CKGR_USBDIV_0 EQU (0x0 << 28) ;- (CKGR) Divider output is PLL clock output\r
+AT91C_CKGR_USBDIV_1 EQU (0x1 << 28) ;- (CKGR) Divider output is PLL clock output divided by 2\r
+AT91C_CKGR_USBDIV_2 EQU (0x2 << 28) ;- (CKGR) Divider output is PLL clock output divided by 4\r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Power Management Controler\r
+// - *****************************************************************************\r
+// - -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- \r
+AT91C_PMC_PCK EQU (0x1 << 0) ;- (PMC) Processor Clock\r
+AT91C_PMC_UDP EQU (0x1 << 7) ;- (PMC) USB Device Port Clock\r
+AT91C_PMC_PCK0 EQU (0x1 << 8) ;- (PMC) Programmable Clock Output\r
+AT91C_PMC_PCK1 EQU (0x1 << 9) ;- (PMC) Programmable Clock Output\r
+AT91C_PMC_PCK2 EQU (0x1 << 10) ;- (PMC) Programmable Clock Output\r
+AT91C_PMC_PCK3 EQU (0x1 << 11) ;- (PMC) Programmable Clock Output\r
+// - -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- \r
+// - -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- \r
+// - -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- \r
+// - -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- \r
+// - -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- \r
+// - -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- \r
+AT91C_PMC_CSS EQU (0x3 << 0) ;- (PMC) Programmable Clock Selection\r
+AT91C_PMC_CSS_SLOW_CLK EQU (0x0) ;- (PMC) Slow Clock is selected\r
+AT91C_PMC_CSS_MAIN_CLK EQU (0x1) ;- (PMC) Main Clock is selected\r
+AT91C_PMC_CSS_PLL_CLK EQU (0x3) ;- (PMC) Clock from PLL is selected\r
+AT91C_PMC_PRES EQU (0x7 << 2) ;- (PMC) Programmable Clock Prescaler\r
+AT91C_PMC_PRES_CLK EQU (0x0 << 2) ;- (PMC) Selected clock\r
+AT91C_PMC_PRES_CLK_2 EQU (0x1 << 2) ;- (PMC) Selected clock divided by 2\r
+AT91C_PMC_PRES_CLK_4 EQU (0x2 << 2) ;- (PMC) Selected clock divided by 4\r
+AT91C_PMC_PRES_CLK_8 EQU (0x3 << 2) ;- (PMC) Selected clock divided by 8\r
+AT91C_PMC_PRES_CLK_16 EQU (0x4 << 2) ;- (PMC) Selected clock divided by 16\r
+AT91C_PMC_PRES_CLK_32 EQU (0x5 << 2) ;- (PMC) Selected clock divided by 32\r
+AT91C_PMC_PRES_CLK_64 EQU (0x6 << 2) ;- (PMC) Selected clock divided by 64\r
+// - -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- \r
+// - -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- \r
+AT91C_PMC_MOSCS EQU (0x1 << 0) ;- (PMC) MOSC Status/Enable/Disable/Mask\r
+AT91C_PMC_LOCK EQU (0x1 << 2) ;- (PMC) PLL Status/Enable/Disable/Mask\r
+AT91C_PMC_MCKRDY EQU (0x1 << 3) ;- (PMC) MCK_RDY Status/Enable/Disable/Mask\r
+AT91C_PMC_PCK0RDY EQU (0x1 << 8) ;- (PMC) PCK0_RDY Status/Enable/Disable/Mask\r
+AT91C_PMC_PCK1RDY EQU (0x1 << 9) ;- (PMC) PCK1_RDY Status/Enable/Disable/Mask\r
+AT91C_PMC_PCK2RDY EQU (0x1 << 10) ;- (PMC) PCK2_RDY Status/Enable/Disable/Mask\r
+AT91C_PMC_PCK3RDY EQU (0x1 << 11) ;- (PMC) PCK3_RDY Status/Enable/Disable/Mask\r
+// - -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- \r
+// - -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- \r
+// - -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- \r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Reset Controller Interface\r
+// - *****************************************************************************\r
+// - -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- \r
+AT91C_RSTC_PROCRST EQU (0x1 << 0) ;- (RSTC) Processor Reset\r
+AT91C_RSTC_PERRST EQU (0x1 << 2) ;- (RSTC) Peripheral Reset\r
+AT91C_RSTC_EXTRST EQU (0x1 << 3) ;- (RSTC) External Reset\r
+AT91C_RSTC_KEY EQU (0xFF << 24) ;- (RSTC) Password\r
+// - -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- \r
+AT91C_RSTC_URSTS EQU (0x1 << 0) ;- (RSTC) User Reset Status\r
+AT91C_RSTC_BODSTS EQU (0x1 << 1) ;- (RSTC) Brownout Detection Status\r
+AT91C_RSTC_RSTTYP EQU (0x7 << 8) ;- (RSTC) Reset Type\r
+AT91C_RSTC_RSTTYP_POWERUP EQU (0x0 << 8) ;- (RSTC) Power-up Reset. VDDCORE rising.\r
+AT91C_RSTC_RSTTYP_WAKEUP EQU (0x1 << 8) ;- (RSTC) WakeUp Reset. VDDCORE rising.\r
+AT91C_RSTC_RSTTYP_WATCHDOG EQU (0x2 << 8) ;- (RSTC) Watchdog Reset. Watchdog overflow occured.\r
+AT91C_RSTC_RSTTYP_SOFTWARE EQU (0x3 << 8) ;- (RSTC) Software Reset. Processor reset required by the software.\r
+AT91C_RSTC_RSTTYP_USER EQU (0x4 << 8) ;- (RSTC) User Reset. NRST pin detected low.\r
+AT91C_RSTC_RSTTYP_BROWNOUT EQU (0x5 << 8) ;- (RSTC) Brownout Reset occured.\r
+AT91C_RSTC_NRSTL EQU (0x1 << 16) ;- (RSTC) NRST pin level\r
+AT91C_RSTC_SRCMP EQU (0x1 << 17) ;- (RSTC) Software Reset Command in Progress.\r
+// - -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- \r
+AT91C_RSTC_URSTEN EQU (0x1 << 0) ;- (RSTC) User Reset Enable\r
+AT91C_RSTC_URSTIEN EQU (0x1 << 4) ;- (RSTC) User Reset Interrupt Enable\r
+AT91C_RSTC_ERSTL EQU (0xF << 8) ;- (RSTC) User Reset Enable\r
+AT91C_RSTC_BODIEN EQU (0x1 << 16) ;- (RSTC) Brownout Detection Interrupt Enable\r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface\r
+// - *****************************************************************************\r
+// - -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- \r
+AT91C_RTTC_RTPRES EQU (0xFFFF << 0) ;- (RTTC) Real-time Timer Prescaler Value\r
+AT91C_RTTC_ALMIEN EQU (0x1 << 16) ;- (RTTC) Alarm Interrupt Enable\r
+AT91C_RTTC_RTTINCIEN EQU (0x1 << 17) ;- (RTTC) Real Time Timer Increment Interrupt Enable\r
+AT91C_RTTC_RTTRST EQU (0x1 << 18) ;- (RTTC) Real Time Timer Restart\r
+// - -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- \r
+AT91C_RTTC_ALMV EQU (0x0 << 0) ;- (RTTC) Alarm Value\r
+// - -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- \r
+AT91C_RTTC_CRTV EQU (0x0 << 0) ;- (RTTC) Current Real-time Value\r
+// - -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- \r
+AT91C_RTTC_ALMS EQU (0x1 << 0) ;- (RTTC) Real-time Alarm Status\r
+AT91C_RTTC_RTTINC EQU (0x1 << 1) ;- (RTTC) Real-time Timer Increment\r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface\r
+// - *****************************************************************************\r
+// - -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- \r
+AT91C_PITC_PIV EQU (0xFFFFF << 0) ;- (PITC) Periodic Interval Value\r
+AT91C_PITC_PITEN EQU (0x1 << 24) ;- (PITC) Periodic Interval Timer Enabled\r
+AT91C_PITC_PITIEN EQU (0x1 << 25) ;- (PITC) Periodic Interval Timer Interrupt Enable\r
+// - -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- \r
+AT91C_PITC_PITS EQU (0x1 << 0) ;- (PITC) Periodic Interval Timer Status\r
+// - -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- \r
+AT91C_PITC_CPIV EQU (0xFFFFF << 0) ;- (PITC) Current Periodic Interval Value\r
+AT91C_PITC_PICNT EQU (0xFFF << 20) ;- (PITC) Periodic Interval Counter\r
+// - -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- \r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface\r
+// - *****************************************************************************\r
+// - -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- \r
+AT91C_WDTC_WDRSTT EQU (0x1 << 0) ;- (WDTC) Watchdog Restart\r
+AT91C_WDTC_KEY EQU (0xFF << 24) ;- (WDTC) Watchdog KEY Password\r
+// - -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- \r
+AT91C_WDTC_WDV EQU (0xFFF << 0) ;- (WDTC) Watchdog Timer Restart\r
+AT91C_WDTC_WDFIEN EQU (0x1 << 12) ;- (WDTC) Watchdog Fault Interrupt Enable\r
+AT91C_WDTC_WDRSTEN EQU (0x1 << 13) ;- (WDTC) Watchdog Reset Enable\r
+AT91C_WDTC_WDRPROC EQU (0x1 << 14) ;- (WDTC) Watchdog Timer Restart\r
+AT91C_WDTC_WDDIS EQU (0x1 << 15) ;- (WDTC) Watchdog Disable\r
+AT91C_WDTC_WDD EQU (0xFFF << 16) ;- (WDTC) Watchdog Delta Value\r
+AT91C_WDTC_WDDBGHLT EQU (0x1 << 28) ;- (WDTC) Watchdog Debug Halt\r
+AT91C_WDTC_WDIDLEHLT EQU (0x1 << 29) ;- (WDTC) Watchdog Idle Halt\r
+// - -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- \r
+AT91C_WDTC_WDUNF EQU (0x1 << 0) ;- (WDTC) Watchdog Underflow\r
+AT91C_WDTC_WDERR EQU (0x1 << 1) ;- (WDTC) Watchdog Error\r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface\r
+// - *****************************************************************************\r
+// - -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- \r
+AT91C_VREG_PSTDBY EQU (0x1 << 0) ;- (VREG) Voltage Regulator Power Standby Mode\r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Memory Controller Interface\r
+// - *****************************************************************************\r
+// - -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- \r
+AT91C_MC_RCB EQU (0x1 << 0) ;- (MC) Remap Command Bit\r
+// - -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- \r
+AT91C_MC_UNDADD EQU (0x1 << 0) ;- (MC) Undefined Addess Abort Status\r
+AT91C_MC_MISADD EQU (0x1 << 1) ;- (MC) Misaligned Addess Abort Status\r
+AT91C_MC_ABTSZ EQU (0x3 << 8) ;- (MC) Abort Size Status\r
+AT91C_MC_ABTSZ_BYTE EQU (0x0 << 8) ;- (MC) Byte\r
+AT91C_MC_ABTSZ_HWORD EQU (0x1 << 8) ;- (MC) Half-word\r
+AT91C_MC_ABTSZ_WORD EQU (0x2 << 8) ;- (MC) Word\r
+AT91C_MC_ABTTYP EQU (0x3 << 10) ;- (MC) Abort Type Status\r
+AT91C_MC_ABTTYP_DATAR EQU (0x0 << 10) ;- (MC) Data Read\r
+AT91C_MC_ABTTYP_DATAW EQU (0x1 << 10) ;- (MC) Data Write\r
+AT91C_MC_ABTTYP_FETCH EQU (0x2 << 10) ;- (MC) Code Fetch\r
+AT91C_MC_MST0 EQU (0x1 << 16) ;- (MC) Master 0 Abort Source\r
+AT91C_MC_MST1 EQU (0x1 << 17) ;- (MC) Master 1 Abort Source\r
+AT91C_MC_SVMST0 EQU (0x1 << 24) ;- (MC) Saved Master 0 Abort Source\r
+AT91C_MC_SVMST1 EQU (0x1 << 25) ;- (MC) Saved Master 1 Abort Source\r
+// - -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- \r
+AT91C_MC_FRDY EQU (0x1 << 0) ;- (MC) Flash Ready\r
+AT91C_MC_LOCKE EQU (0x1 << 2) ;- (MC) Lock Error\r
+AT91C_MC_PROGE EQU (0x1 << 3) ;- (MC) Programming Error\r
+AT91C_MC_NEBP EQU (0x1 << 7) ;- (MC) No Erase Before Programming\r
+AT91C_MC_FWS EQU (0x3 << 8) ;- (MC) Flash Wait State\r
+AT91C_MC_FWS_0FWS EQU (0x0 << 8) ;- (MC) 1 cycle for Read, 2 for Write operations\r
+AT91C_MC_FWS_1FWS EQU (0x1 << 8) ;- (MC) 2 cycles for Read, 3 for Write operations\r
+AT91C_MC_FWS_2FWS EQU (0x2 << 8) ;- (MC) 3 cycles for Read, 4 for Write operations\r
+AT91C_MC_FWS_3FWS EQU (0x3 << 8) ;- (MC) 4 cycles for Read, 4 for Write operations\r
+AT91C_MC_FMCN EQU (0xFF << 16) ;- (MC) Flash Microsecond Cycle Number\r
+// - -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- \r
+AT91C_MC_FCMD EQU (0xF << 0) ;- (MC) Flash Command\r
+AT91C_MC_FCMD_START_PROG EQU (0x1) ;- (MC) Starts the programming of th epage specified by PAGEN.\r
+AT91C_MC_FCMD_LOCK EQU (0x2) ;- (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.\r
+AT91C_MC_FCMD_PROG_AND_LOCK EQU (0x3) ;- (MC) The lock sequence automatically happens after the programming sequence is completed.\r
+AT91C_MC_FCMD_UNLOCK EQU (0x4) ;- (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.\r
+AT91C_MC_FCMD_ERASE_ALL EQU (0x8) ;- (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.\r
+AT91C_MC_FCMD_SET_GP_NVM EQU (0xB) ;- (MC) Set General Purpose NVM bits.\r
+AT91C_MC_FCMD_CLR_GP_NVM EQU (0xD) ;- (MC) Clear General Purpose NVM bits.\r
+AT91C_MC_FCMD_SET_SECURITY EQU (0xF) ;- (MC) Set Security Bit.\r
+AT91C_MC_PAGEN EQU (0x3FF << 8) ;- (MC) Page Number\r
+AT91C_MC_KEY EQU (0xFF << 24) ;- (MC) Writing Protect Key\r
+// - -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- \r
+AT91C_MC_SECURITY EQU (0x1 << 4) ;- (MC) Security Bit Status\r
+AT91C_MC_GPNVM0 EQU (0x1 << 8) ;- (MC) Sector 0 Lock Status\r
+AT91C_MC_GPNVM1 EQU (0x1 << 9) ;- (MC) Sector 1 Lock Status\r
+AT91C_MC_GPNVM2 EQU (0x1 << 10) ;- (MC) Sector 2 Lock Status\r
+AT91C_MC_GPNVM3 EQU (0x1 << 11) ;- (MC) Sector 3 Lock Status\r
+AT91C_MC_GPNVM4 EQU (0x1 << 12) ;- (MC) Sector 4 Lock Status\r
+AT91C_MC_GPNVM5 EQU (0x1 << 13) ;- (MC) Sector 5 Lock Status\r
+AT91C_MC_GPNVM6 EQU (0x1 << 14) ;- (MC) Sector 6 Lock Status\r
+AT91C_MC_GPNVM7 EQU (0x1 << 15) ;- (MC) Sector 7 Lock Status\r
+AT91C_MC_LOCKS0 EQU (0x1 << 16) ;- (MC) Sector 0 Lock Status\r
+AT91C_MC_LOCKS1 EQU (0x1 << 17) ;- (MC) Sector 1 Lock Status\r
+AT91C_MC_LOCKS2 EQU (0x1 << 18) ;- (MC) Sector 2 Lock Status\r
+AT91C_MC_LOCKS3 EQU (0x1 << 19) ;- (MC) Sector 3 Lock Status\r
+AT91C_MC_LOCKS4 EQU (0x1 << 20) ;- (MC) Sector 4 Lock Status\r
+AT91C_MC_LOCKS5 EQU (0x1 << 21) ;- (MC) Sector 5 Lock Status\r
+AT91C_MC_LOCKS6 EQU (0x1 << 22) ;- (MC) Sector 6 Lock Status\r
+AT91C_MC_LOCKS7 EQU (0x1 << 23) ;- (MC) Sector 7 Lock Status\r
+AT91C_MC_LOCKS8 EQU (0x1 << 24) ;- (MC) Sector 8 Lock Status\r
+AT91C_MC_LOCKS9 EQU (0x1 << 25) ;- (MC) Sector 9 Lock Status\r
+AT91C_MC_LOCKS10 EQU (0x1 << 26) ;- (MC) Sector 10 Lock Status\r
+AT91C_MC_LOCKS11 EQU (0x1 << 27) ;- (MC) Sector 11 Lock Status\r
+AT91C_MC_LOCKS12 EQU (0x1 << 28) ;- (MC) Sector 12 Lock Status\r
+AT91C_MC_LOCKS13 EQU (0x1 << 29) ;- (MC) Sector 13 Lock Status\r
+AT91C_MC_LOCKS14 EQU (0x1 << 30) ;- (MC) Sector 14 Lock Status\r
+AT91C_MC_LOCKS15 EQU (0x1 << 31) ;- (MC) Sector 15 Lock Status\r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Serial Parallel Interface\r
+// - *****************************************************************************\r
+// - -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- \r
+AT91C_SPI_SPIEN EQU (0x1 << 0) ;- (SPI) SPI Enable\r
+AT91C_SPI_SPIDIS EQU (0x1 << 1) ;- (SPI) SPI Disable\r
+AT91C_SPI_SWRST EQU (0x1 << 7) ;- (SPI) SPI Software reset\r
+AT91C_SPI_LASTXFER EQU (0x1 << 24) ;- (SPI) SPI Last Transfer\r
+// - -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- \r
+AT91C_SPI_MSTR EQU (0x1 << 0) ;- (SPI) Master/Slave Mode\r
+AT91C_SPI_PS EQU (0x1 << 1) ;- (SPI) Peripheral Select\r
+AT91C_SPI_PS_FIXED EQU (0x0 << 1) ;- (SPI) Fixed Peripheral Select\r
+AT91C_SPI_PS_VARIABLE EQU (0x1 << 1) ;- (SPI) Variable Peripheral Select\r
+AT91C_SPI_PCSDEC EQU (0x1 << 2) ;- (SPI) Chip Select Decode\r
+AT91C_SPI_FDIV EQU (0x1 << 3) ;- (SPI) Clock Selection\r
+AT91C_SPI_MODFDIS EQU (0x1 << 4) ;- (SPI) Mode Fault Detection\r
+AT91C_SPI_LLB EQU (0x1 << 7) ;- (SPI) Clock Selection\r
+AT91C_SPI_PCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select\r
+AT91C_SPI_DLYBCS EQU (0xFF << 24) ;- (SPI) Delay Between Chip Selects\r
+// - -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- \r
+AT91C_SPI_RD EQU (0xFFFF << 0) ;- (SPI) Receive Data\r
+AT91C_SPI_RPCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status\r
+// - -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- \r
+AT91C_SPI_TD EQU (0xFFFF << 0) ;- (SPI) Transmit Data\r
+AT91C_SPI_TPCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status\r
+// - -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- \r
+AT91C_SPI_RDRF EQU (0x1 << 0) ;- (SPI) Receive Data Register Full\r
+AT91C_SPI_TDRE EQU (0x1 << 1) ;- (SPI) Transmit Data Register Empty\r
+AT91C_SPI_MODF EQU (0x1 << 2) ;- (SPI) Mode Fault Error\r
+AT91C_SPI_OVRES EQU (0x1 << 3) ;- (SPI) Overrun Error Status\r
+AT91C_SPI_ENDRX EQU (0x1 << 4) ;- (SPI) End of Receiver Transfer\r
+AT91C_SPI_ENDTX EQU (0x1 << 5) ;- (SPI) End of Receiver Transfer\r
+AT91C_SPI_RXBUFF EQU (0x1 << 6) ;- (SPI) RXBUFF Interrupt\r
+AT91C_SPI_TXBUFE EQU (0x1 << 7) ;- (SPI) TXBUFE Interrupt\r
+AT91C_SPI_NSSR EQU (0x1 << 8) ;- (SPI) NSSR Interrupt\r
+AT91C_SPI_TXEMPTY EQU (0x1 << 9) ;- (SPI) TXEMPTY Interrupt\r
+AT91C_SPI_SPIENS EQU (0x1 << 16) ;- (SPI) Enable Status\r
+// - -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- \r
+// - -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- \r
+// - -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- \r
+// - -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- \r
+AT91C_SPI_CPOL EQU (0x1 << 0) ;- (SPI) Clock Polarity\r
+AT91C_SPI_NCPHA EQU (0x1 << 1) ;- (SPI) Clock Phase\r
+AT91C_SPI_CSAAT EQU (0x1 << 3) ;- (SPI) Chip Select Active After Transfer\r
+AT91C_SPI_BITS EQU (0xF << 4) ;- (SPI) Bits Per Transfer\r
+AT91C_SPI_BITS_8 EQU (0x0 << 4) ;- (SPI) 8 Bits Per transfer\r
+AT91C_SPI_BITS_9 EQU (0x1 << 4) ;- (SPI) 9 Bits Per transfer\r
+AT91C_SPI_BITS_10 EQU (0x2 << 4) ;- (SPI) 10 Bits Per transfer\r
+AT91C_SPI_BITS_11 EQU (0x3 << 4) ;- (SPI) 11 Bits Per transfer\r
+AT91C_SPI_BITS_12 EQU (0x4 << 4) ;- (SPI) 12 Bits Per transfer\r
+AT91C_SPI_BITS_13 EQU (0x5 << 4) ;- (SPI) 13 Bits Per transfer\r
+AT91C_SPI_BITS_14 EQU (0x6 << 4) ;- (SPI) 14 Bits Per transfer\r
+AT91C_SPI_BITS_15 EQU (0x7 << 4) ;- (SPI) 15 Bits Per transfer\r
+AT91C_SPI_BITS_16 EQU (0x8 << 4) ;- (SPI) 16 Bits Per transfer\r
+AT91C_SPI_SCBR EQU (0xFF << 8) ;- (SPI) Serial Clock Baud Rate\r
+AT91C_SPI_DLYBS EQU (0xFF << 16) ;- (SPI) Delay Before SPCK\r
+AT91C_SPI_DLYBCT EQU (0xFF << 24) ;- (SPI) Delay Between Consecutive Transfers\r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Usart\r
+// - *****************************************************************************\r
+// - -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- \r
+AT91C_US_STTBRK EQU (0x1 << 9) ;- (USART) Start Break\r
+AT91C_US_STPBRK EQU (0x1 << 10) ;- (USART) Stop Break\r
+AT91C_US_STTTO EQU (0x1 << 11) ;- (USART) Start Time-out\r
+AT91C_US_SENDA EQU (0x1 << 12) ;- (USART) Send Address\r
+AT91C_US_RSTIT EQU (0x1 << 13) ;- (USART) Reset Iterations\r
+AT91C_US_RSTNACK EQU (0x1 << 14) ;- (USART) Reset Non Acknowledge\r
+AT91C_US_RETTO EQU (0x1 << 15) ;- (USART) Rearm Time-out\r
+AT91C_US_DTREN EQU (0x1 << 16) ;- (USART) Data Terminal ready Enable\r
+AT91C_US_DTRDIS EQU (0x1 << 17) ;- (USART) Data Terminal ready Disable\r
+AT91C_US_RTSEN EQU (0x1 << 18) ;- (USART) Request to Send enable\r
+AT91C_US_RTSDIS EQU (0x1 << 19) ;- (USART) Request to Send Disable\r
+// - -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- \r
+AT91C_US_USMODE EQU (0xF << 0) ;- (USART) Usart mode\r
+AT91C_US_USMODE_NORMAL EQU (0x0) ;- (USART) Normal\r
+AT91C_US_USMODE_RS485 EQU (0x1) ;- (USART) RS485\r
+AT91C_US_USMODE_HWHSH EQU (0x2) ;- (USART) Hardware Handshaking\r
+AT91C_US_USMODE_MODEM EQU (0x3) ;- (USART) Modem\r
+AT91C_US_USMODE_ISO7816_0 EQU (0x4) ;- (USART) ISO7816 protocol: T = 0\r
+AT91C_US_USMODE_ISO7816_1 EQU (0x6) ;- (USART) ISO7816 protocol: T = 1\r
+AT91C_US_USMODE_IRDA EQU (0x8) ;- (USART) IrDA\r
+AT91C_US_USMODE_SWHSH EQU (0xC) ;- (USART) Software Handshaking\r
+AT91C_US_CLKS EQU (0x3 << 4) ;- (USART) Clock Selection (Baud Rate generator Input Clock\r
+AT91C_US_CLKS_CLOCK EQU (0x0 << 4) ;- (USART) Clock\r
+AT91C_US_CLKS_FDIV1 EQU (0x1 << 4) ;- (USART) fdiv1\r
+AT91C_US_CLKS_SLOW EQU (0x2 << 4) ;- (USART) slow_clock (ARM)\r
+AT91C_US_CLKS_EXT EQU (0x3 << 4) ;- (USART) External (SCK)\r
+AT91C_US_CHRL EQU (0x3 << 6) ;- (USART) Clock Selection (Baud Rate generator Input Clock\r
+AT91C_US_CHRL_5_BITS EQU (0x0 << 6) ;- (USART) Character Length: 5 bits\r
+AT91C_US_CHRL_6_BITS EQU (0x1 << 6) ;- (USART) Character Length: 6 bits\r
+AT91C_US_CHRL_7_BITS EQU (0x2 << 6) ;- (USART) Character Length: 7 bits\r
+AT91C_US_CHRL_8_BITS EQU (0x3 << 6) ;- (USART) Character Length: 8 bits\r
+AT91C_US_SYNC EQU (0x1 << 8) ;- (USART) Synchronous Mode Select\r
+AT91C_US_NBSTOP EQU (0x3 << 12) ;- (USART) Number of Stop bits\r
+AT91C_US_NBSTOP_1_BIT EQU (0x0 << 12) ;- (USART) 1 stop bit\r
+AT91C_US_NBSTOP_15_BIT EQU (0x1 << 12) ;- (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits\r
+AT91C_US_NBSTOP_2_BIT EQU (0x2 << 12) ;- (USART) 2 stop bits\r
+AT91C_US_MSBF EQU (0x1 << 16) ;- (USART) Bit Order\r
+AT91C_US_MODE9 EQU (0x1 << 17) ;- (USART) 9-bit Character length\r
+AT91C_US_CKLO EQU (0x1 << 18) ;- (USART) Clock Output Select\r
+AT91C_US_OVER EQU (0x1 << 19) ;- (USART) Over Sampling Mode\r
+AT91C_US_INACK EQU (0x1 << 20) ;- (USART) Inhibit Non Acknowledge\r
+AT91C_US_DSNACK EQU (0x1 << 21) ;- (USART) Disable Successive NACK\r
+AT91C_US_MAX_ITER EQU (0x1 << 24) ;- (USART) Number of Repetitions\r
+AT91C_US_FILTER EQU (0x1 << 28) ;- (USART) Receive Line Filter\r
+// - -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- \r
+AT91C_US_RXBRK EQU (0x1 << 2) ;- (USART) Break Received/End of Break\r
+AT91C_US_TIMEOUT EQU (0x1 << 8) ;- (USART) Receiver Time-out\r
+AT91C_US_ITERATION EQU (0x1 << 10) ;- (USART) Max number of Repetitions Reached\r
+AT91C_US_NACK EQU (0x1 << 13) ;- (USART) Non Acknowledge\r
+AT91C_US_RIIC EQU (0x1 << 16) ;- (USART) Ring INdicator Input Change Flag\r
+AT91C_US_DSRIC EQU (0x1 << 17) ;- (USART) Data Set Ready Input Change Flag\r
+AT91C_US_DCDIC EQU (0x1 << 18) ;- (USART) Data Carrier Flag\r
+AT91C_US_CTSIC EQU (0x1 << 19) ;- (USART) Clear To Send Input Change Flag\r
+// - -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- \r
+// - -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- \r
+// - -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- \r
+AT91C_US_RI EQU (0x1 << 20) ;- (USART) Image of RI Input\r
+AT91C_US_DSR EQU (0x1 << 21) ;- (USART) Image of DSR Input\r
+AT91C_US_DCD EQU (0x1 << 22) ;- (USART) Image of DCD Input\r
+AT91C_US_CTS EQU (0x1 << 23) ;- (USART) Image of CTS Input\r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface\r
+// - *****************************************************************************\r
+// - -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- \r
+AT91C_SSC_RXEN EQU (0x1 << 0) ;- (SSC) Receive Enable\r
+AT91C_SSC_RXDIS EQU (0x1 << 1) ;- (SSC) Receive Disable\r
+AT91C_SSC_TXEN EQU (0x1 << 8) ;- (SSC) Transmit Enable\r
+AT91C_SSC_TXDIS EQU (0x1 << 9) ;- (SSC) Transmit Disable\r
+AT91C_SSC_SWRST EQU (0x1 << 15) ;- (SSC) Software Reset\r
+// - -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- \r
+AT91C_SSC_CKS EQU (0x3 << 0) ;- (SSC) Receive/Transmit Clock Selection\r
+AT91C_SSC_CKS_DIV EQU (0x0) ;- (SSC) Divided Clock\r
+AT91C_SSC_CKS_TK EQU (0x1) ;- (SSC) TK Clock signal\r
+AT91C_SSC_CKS_RK EQU (0x2) ;- (SSC) RK pin\r
+AT91C_SSC_CKO EQU (0x7 << 2) ;- (SSC) Receive/Transmit Clock Output Mode Selection\r
+AT91C_SSC_CKO_NONE EQU (0x0 << 2) ;- (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only\r
+AT91C_SSC_CKO_CONTINOUS EQU (0x1 << 2) ;- (SSC) Continuous Receive/Transmit Clock RK pin: Output\r
+AT91C_SSC_CKO_DATA_TX EQU (0x2 << 2) ;- (SSC) Receive/Transmit Clock only during data transfers RK pin: Output\r
+AT91C_SSC_CKI EQU (0x1 << 5) ;- (SSC) Receive/Transmit Clock Inversion\r
+AT91C_SSC_START EQU (0xF << 8) ;- (SSC) Receive/Transmit Start Selection\r
+AT91C_SSC_START_CONTINOUS EQU (0x0 << 8) ;- (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.\r
+AT91C_SSC_START_TX EQU (0x1 << 8) ;- (SSC) Transmit/Receive start\r
+AT91C_SSC_START_LOW_RF EQU (0x2 << 8) ;- (SSC) Detection of a low level on RF input\r
+AT91C_SSC_START_HIGH_RF EQU (0x3 << 8) ;- (SSC) Detection of a high level on RF input\r
+AT91C_SSC_START_FALL_RF EQU (0x4 << 8) ;- (SSC) Detection of a falling edge on RF input\r
+AT91C_SSC_START_RISE_RF EQU (0x5 << 8) ;- (SSC) Detection of a rising edge on RF input\r
+AT91C_SSC_START_LEVEL_RF EQU (0x6 << 8) ;- (SSC) Detection of any level change on RF input\r
+AT91C_SSC_START_EDGE_RF EQU (0x7 << 8) ;- (SSC) Detection of any edge on RF input\r
+AT91C_SSC_START_0 EQU (0x8 << 8) ;- (SSC) Compare 0\r
+AT91C_SSC_STTDLY EQU (0xFF << 16) ;- (SSC) Receive/Transmit Start Delay\r
+AT91C_SSC_PERIOD EQU (0xFF << 24) ;- (SSC) Receive/Transmit Period Divider Selection\r
+// - -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- \r
+AT91C_SSC_DATLEN EQU (0x1F << 0) ;- (SSC) Data Length\r
+AT91C_SSC_LOOP EQU (0x1 << 5) ;- (SSC) Loop Mode\r
+AT91C_SSC_MSBF EQU (0x1 << 7) ;- (SSC) Most Significant Bit First\r
+AT91C_SSC_DATNB EQU (0xF << 8) ;- (SSC) Data Number per Frame\r
+AT91C_SSC_FSLEN EQU (0xF << 16) ;- (SSC) Receive/Transmit Frame Sync length\r
+AT91C_SSC_FSOS EQU (0x7 << 20) ;- (SSC) Receive/Transmit Frame Sync Output Selection\r
+AT91C_SSC_FSOS_NONE EQU (0x0 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only\r
+AT91C_SSC_FSOS_NEGATIVE EQU (0x1 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse\r
+AT91C_SSC_FSOS_POSITIVE EQU (0x2 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse\r
+AT91C_SSC_FSOS_LOW EQU (0x3 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer\r
+AT91C_SSC_FSOS_HIGH EQU (0x4 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer\r
+AT91C_SSC_FSOS_TOGGLE EQU (0x5 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer\r
+AT91C_SSC_FSEDGE EQU (0x1 << 24) ;- (SSC) Frame Sync Edge Detection\r
+// - -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- \r
+// - -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- \r
+AT91C_SSC_DATDEF EQU (0x1 << 5) ;- (SSC) Data Default Value\r
+AT91C_SSC_FSDEN EQU (0x1 << 23) ;- (SSC) Frame Sync Data Enable\r
+// - -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- \r
+AT91C_SSC_TXRDY EQU (0x1 << 0) ;- (SSC) Transmit Ready\r
+AT91C_SSC_TXEMPTY EQU (0x1 << 1) ;- (SSC) Transmit Empty\r
+AT91C_SSC_ENDTX EQU (0x1 << 2) ;- (SSC) End Of Transmission\r
+AT91C_SSC_TXBUFE EQU (0x1 << 3) ;- (SSC) Transmit Buffer Empty\r
+AT91C_SSC_RXRDY EQU (0x1 << 4) ;- (SSC) Receive Ready\r
+AT91C_SSC_OVRUN EQU (0x1 << 5) ;- (SSC) Receive Overrun\r
+AT91C_SSC_ENDRX EQU (0x1 << 6) ;- (SSC) End of Reception\r
+AT91C_SSC_RXBUFF EQU (0x1 << 7) ;- (SSC) Receive Buffer Full\r
+AT91C_SSC_TXSYN EQU (0x1 << 10) ;- (SSC) Transmit Sync\r
+AT91C_SSC_RXSYN EQU (0x1 << 11) ;- (SSC) Receive Sync\r
+AT91C_SSC_TXENA EQU (0x1 << 16) ;- (SSC) Transmit Enable\r
+AT91C_SSC_RXENA EQU (0x1 << 17) ;- (SSC) Receive Enable\r
+// - -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- \r
+// - -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- \r
+// - -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- \r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Two-wire Interface\r
+// - *****************************************************************************\r
+// - -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- \r
+AT91C_TWI_START EQU (0x1 << 0) ;- (TWI) Send a START Condition\r
+AT91C_TWI_STOP EQU (0x1 << 1) ;- (TWI) Send a STOP Condition\r
+AT91C_TWI_MSEN EQU (0x1 << 2) ;- (TWI) TWI Master Transfer Enabled\r
+AT91C_TWI_MSDIS EQU (0x1 << 3) ;- (TWI) TWI Master Transfer Disabled\r
+AT91C_TWI_SWRST EQU (0x1 << 7) ;- (TWI) Software Reset\r
+// - -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- \r
+AT91C_TWI_IADRSZ EQU (0x3 << 8) ;- (TWI) Internal Device Address Size\r
+AT91C_TWI_IADRSZ_NO EQU (0x0 << 8) ;- (TWI) No internal device address\r
+AT91C_TWI_IADRSZ_1_BYTE EQU (0x1 << 8) ;- (TWI) One-byte internal device address\r
+AT91C_TWI_IADRSZ_2_BYTE EQU (0x2 << 8) ;- (TWI) Two-byte internal device address\r
+AT91C_TWI_IADRSZ_3_BYTE EQU (0x3 << 8) ;- (TWI) Three-byte internal device address\r
+AT91C_TWI_MREAD EQU (0x1 << 12) ;- (TWI) Master Read Direction\r
+AT91C_TWI_DADR EQU (0x7F << 16) ;- (TWI) Device Address\r
+// - -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- \r
+AT91C_TWI_CLDIV EQU (0xFF << 0) ;- (TWI) Clock Low Divider\r
+AT91C_TWI_CHDIV EQU (0xFF << 8) ;- (TWI) Clock High Divider\r
+AT91C_TWI_CKDIV EQU (0x7 << 16) ;- (TWI) Clock Divider\r
+// - -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- \r
+AT91C_TWI_TXCOMP EQU (0x1 << 0) ;- (TWI) Transmission Completed\r
+AT91C_TWI_RXRDY EQU (0x1 << 1) ;- (TWI) Receive holding register ReaDY\r
+AT91C_TWI_TXRDY EQU (0x1 << 2) ;- (TWI) Transmit holding register ReaDY\r
+AT91C_TWI_OVRE EQU (0x1 << 6) ;- (TWI) Overrun Error\r
+AT91C_TWI_UNRE EQU (0x1 << 7) ;- (TWI) Underrun Error\r
+AT91C_TWI_NACK EQU (0x1 << 8) ;- (TWI) Not Acknowledged\r
+// - -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- \r
+// - -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- \r
+// - -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- \r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR PWMC Channel Interface\r
+// - *****************************************************************************\r
+// - -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- \r
+AT91C_PWMC_CPRE EQU (0xF << 0) ;- (PWMC_CH) Channel Pre-scaler : PWMC_CLKx\r
+AT91C_PWMC_CPRE_MCK EQU (0x0) ;- (PWMC_CH) \r
+AT91C_PWMC_CPRE_MCKA EQU (0xB) ;- (PWMC_CH) \r
+AT91C_PWMC_CPRE_MCKB EQU (0xC) ;- (PWMC_CH) \r
+AT91C_PWMC_CALG EQU (0x1 << 8) ;- (PWMC_CH) Channel Alignment\r
+AT91C_PWMC_CPOL EQU (0x1 << 9) ;- (PWMC_CH) Channel Polarity\r
+AT91C_PWMC_CPD EQU (0x1 << 10) ;- (PWMC_CH) Channel Update Period\r
+// - -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- \r
+AT91C_PWMC_CDTY EQU (0x0 << 0) ;- (PWMC_CH) Channel Duty Cycle\r
+// - -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- \r
+AT91C_PWMC_CPRD EQU (0x0 << 0) ;- (PWMC_CH) Channel Period\r
+// - -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- \r
+AT91C_PWMC_CCNT EQU (0x0 << 0) ;- (PWMC_CH) Channel Counter\r
+// - -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- \r
+AT91C_PWMC_CUPD EQU (0x0 << 0) ;- (PWMC_CH) Channel Update\r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface\r
+// - *****************************************************************************\r
+// - -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- \r
+AT91C_PWMC_DIVA EQU (0xFF << 0) ;- (PWMC) CLKA divide factor.\r
+AT91C_PWMC_PREA EQU (0xF << 8) ;- (PWMC) Divider Input Clock Prescaler A\r
+AT91C_PWMC_PREA_MCK EQU (0x0 << 8) ;- (PWMC) \r
+AT91C_PWMC_DIVB EQU (0xFF << 16) ;- (PWMC) CLKB divide factor.\r
+AT91C_PWMC_PREB EQU (0xF << 24) ;- (PWMC) Divider Input Clock Prescaler B\r
+AT91C_PWMC_PREB_MCK EQU (0x0 << 24) ;- (PWMC) \r
+// - -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- \r
+AT91C_PWMC_CHID0 EQU (0x1 << 0) ;- (PWMC) Channel ID 0\r
+AT91C_PWMC_CHID1 EQU (0x1 << 1) ;- (PWMC) Channel ID 1\r
+AT91C_PWMC_CHID2 EQU (0x1 << 2) ;- (PWMC) Channel ID 2\r
+AT91C_PWMC_CHID3 EQU (0x1 << 3) ;- (PWMC) Channel ID 3\r
+// - -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- \r
+// - -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- \r
+// - -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- \r
+// - -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- \r
+// - -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- \r
+// - -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- \r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR USB Device Interface\r
+// - *****************************************************************************\r
+// - -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- \r
+AT91C_UDP_FRM_NUM EQU (0x7FF << 0) ;- (UDP) Frame Number as Defined in the Packet Field Formats\r
+AT91C_UDP_FRM_ERR EQU (0x1 << 16) ;- (UDP) Frame Error\r
+AT91C_UDP_FRM_OK EQU (0x1 << 17) ;- (UDP) Frame OK\r
+// - -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- \r
+AT91C_UDP_FADDEN EQU (0x1 << 0) ;- (UDP) Function Address Enable\r
+AT91C_UDP_CONFG EQU (0x1 << 1) ;- (UDP) Configured\r
+AT91C_UDP_ESR EQU (0x1 << 2) ;- (UDP) Enable Send Resume\r
+AT91C_UDP_RSMINPR EQU (0x1 << 3) ;- (UDP) A Resume Has Been Sent to the Host\r
+AT91C_UDP_RMWUPE EQU (0x1 << 4) ;- (UDP) Remote Wake Up Enable\r
+// - -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- \r
+AT91C_UDP_FADD EQU (0xFF << 0) ;- (UDP) Function Address Value\r
+AT91C_UDP_FEN EQU (0x1 << 8) ;- (UDP) Function Enable\r
+// - -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- \r
+AT91C_UDP_EPINT0 EQU (0x1 << 0) ;- (UDP) Endpoint 0 Interrupt\r
+AT91C_UDP_EPINT1 EQU (0x1 << 1) ;- (UDP) Endpoint 0 Interrupt\r
+AT91C_UDP_EPINT2 EQU (0x1 << 2) ;- (UDP) Endpoint 2 Interrupt\r
+AT91C_UDP_EPINT3 EQU (0x1 << 3) ;- (UDP) Endpoint 3 Interrupt\r
+AT91C_UDP_EPINT4 EQU (0x1 << 4) ;- (UDP) Endpoint 4 Interrupt\r
+AT91C_UDP_EPINT5 EQU (0x1 << 5) ;- (UDP) Endpoint 5 Interrupt\r
+AT91C_UDP_RXSUSP EQU (0x1 << 8) ;- (UDP) USB Suspend Interrupt\r
+AT91C_UDP_RXRSM EQU (0x1 << 9) ;- (UDP) USB Resume Interrupt\r
+AT91C_UDP_EXTRSM EQU (0x1 << 10) ;- (UDP) USB External Resume Interrupt\r
+AT91C_UDP_SOFINT EQU (0x1 << 11) ;- (UDP) USB Start Of frame Interrupt\r
+AT91C_UDP_WAKEUP EQU (0x1 << 13) ;- (UDP) USB Resume Interrupt\r
+// - -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- \r
+// - -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- \r
+// - -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- \r
+AT91C_UDP_ENDBUSRES EQU (0x1 << 12) ;- (UDP) USB End Of Bus Reset Interrupt\r
+// - -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- \r
+// - -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- \r
+AT91C_UDP_EP0 EQU (0x1 << 0) ;- (UDP) Reset Endpoint 0\r
+AT91C_UDP_EP1 EQU (0x1 << 1) ;- (UDP) Reset Endpoint 1\r
+AT91C_UDP_EP2 EQU (0x1 << 2) ;- (UDP) Reset Endpoint 2\r
+AT91C_UDP_EP3 EQU (0x1 << 3) ;- (UDP) Reset Endpoint 3\r
+AT91C_UDP_EP4 EQU (0x1 << 4) ;- (UDP) Reset Endpoint 4\r
+AT91C_UDP_EP5 EQU (0x1 << 5) ;- (UDP) Reset Endpoint 5\r
+// - -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- \r
+AT91C_UDP_TXCOMP EQU (0x1 << 0) ;- (UDP) Generates an IN packet with data previously written in the DPR\r
+AT91C_UDP_RX_DATA_BK0 EQU (0x1 << 1) ;- (UDP) Receive Data Bank 0\r
+AT91C_UDP_RXSETUP EQU (0x1 << 2) ;- (UDP) Sends STALL to the Host (Control endpoints)\r
+AT91C_UDP_ISOERROR EQU (0x1 << 3) ;- (UDP) Isochronous error (Isochronous endpoints)\r
+AT91C_UDP_TXPKTRDY EQU (0x1 << 4) ;- (UDP) Transmit Packet Ready\r
+AT91C_UDP_FORCESTALL EQU (0x1 << 5) ;- (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).\r
+AT91C_UDP_RX_DATA_BK1 EQU (0x1 << 6) ;- (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).\r
+AT91C_UDP_DIR EQU (0x1 << 7) ;- (UDP) Transfer Direction\r
+AT91C_UDP_EPTYPE EQU (0x7 << 8) ;- (UDP) Endpoint type\r
+AT91C_UDP_EPTYPE_CTRL EQU (0x0 << 8) ;- (UDP) Control\r
+AT91C_UDP_EPTYPE_ISO_OUT EQU (0x1 << 8) ;- (UDP) Isochronous OUT\r
+AT91C_UDP_EPTYPE_BULK_OUT EQU (0x2 << 8) ;- (UDP) Bulk OUT\r
+AT91C_UDP_EPTYPE_INT_OUT EQU (0x3 << 8) ;- (UDP) Interrupt OUT\r
+AT91C_UDP_EPTYPE_ISO_IN EQU (0x5 << 8) ;- (UDP) Isochronous IN\r
+AT91C_UDP_EPTYPE_BULK_IN EQU (0x6 << 8) ;- (UDP) Bulk IN\r
+AT91C_UDP_EPTYPE_INT_IN EQU (0x7 << 8) ;- (UDP) Interrupt IN\r
+AT91C_UDP_DTGLE EQU (0x1 << 11) ;- (UDP) Data Toggle\r
+AT91C_UDP_EPEDS EQU (0x1 << 15) ;- (UDP) Endpoint Enable Disable\r
+AT91C_UDP_RXBYTECNT EQU (0x7FF << 16) ;- (UDP) Number Of Bytes Available in the FIFO\r
+// - -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- \r
+AT91C_UDP_TXVDIS EQU (0x1 << 8) ;- (UDP) \r
+AT91C_UDP_PUON EQU (0x1 << 9) ;- (UDP) Pull-up ON\r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Timer Counter Channel Interface\r
+// - *****************************************************************************\r
+// - -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- \r
+AT91C_TC_CLKEN EQU (0x1 << 0) ;- (TC) Counter Clock Enable Command\r
+AT91C_TC_CLKDIS EQU (0x1 << 1) ;- (TC) Counter Clock Disable Command\r
+AT91C_TC_SWTRG EQU (0x1 << 2) ;- (TC) Software Trigger Command\r
+// - -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- \r
+AT91C_TC_CLKS EQU (0x7 << 0) ;- (TC) Clock Selection\r
+AT91C_TC_CLKS_TIMER_DIV1_CLOCK EQU (0x0) ;- (TC) Clock selected: TIMER_DIV1_CLOCK\r
+AT91C_TC_CLKS_TIMER_DIV2_CLOCK EQU (0x1) ;- (TC) Clock selected: TIMER_DIV2_CLOCK\r
+AT91C_TC_CLKS_TIMER_DIV3_CLOCK EQU (0x2) ;- (TC) Clock selected: TIMER_DIV3_CLOCK\r
+AT91C_TC_CLKS_TIMER_DIV4_CLOCK EQU (0x3) ;- (TC) Clock selected: TIMER_DIV4_CLOCK\r
+AT91C_TC_CLKS_TIMER_DIV5_CLOCK EQU (0x4) ;- (TC) Clock selected: TIMER_DIV5_CLOCK\r
+AT91C_TC_CLKS_XC0 EQU (0x5) ;- (TC) Clock selected: XC0\r
+AT91C_TC_CLKS_XC1 EQU (0x6) ;- (TC) Clock selected: XC1\r
+AT91C_TC_CLKS_XC2 EQU (0x7) ;- (TC) Clock selected: XC2\r
+AT91C_TC_CLKI EQU (0x1 << 3) ;- (TC) Clock Invert\r
+AT91C_TC_BURST EQU (0x3 << 4) ;- (TC) Burst Signal Selection\r
+AT91C_TC_BURST_NONE EQU (0x0 << 4) ;- (TC) The clock is not gated by an external signal\r
+AT91C_TC_BURST_XC0 EQU (0x1 << 4) ;- (TC) XC0 is ANDed with the selected clock\r
+AT91C_TC_BURST_XC1 EQU (0x2 << 4) ;- (TC) XC1 is ANDed with the selected clock\r
+AT91C_TC_BURST_XC2 EQU (0x3 << 4) ;- (TC) XC2 is ANDed with the selected clock\r
+AT91C_TC_CPCSTOP EQU (0x1 << 6) ;- (TC) Counter Clock Stopped with RC Compare\r
+AT91C_TC_LDBSTOP EQU (0x1 << 6) ;- (TC) Counter Clock Stopped with RB Loading\r
+AT91C_TC_CPCDIS EQU (0x1 << 7) ;- (TC) Counter Clock Disable with RC Compare\r
+AT91C_TC_LDBDIS EQU (0x1 << 7) ;- (TC) Counter Clock Disabled with RB Loading\r
+AT91C_TC_ETRGEDG EQU (0x3 << 8) ;- (TC) External Trigger Edge Selection\r
+AT91C_TC_ETRGEDG_NONE EQU (0x0 << 8) ;- (TC) Edge: None\r
+AT91C_TC_ETRGEDG_RISING EQU (0x1 << 8) ;- (TC) Edge: rising edge\r
+AT91C_TC_ETRGEDG_FALLING EQU (0x2 << 8) ;- (TC) Edge: falling edge\r
+AT91C_TC_ETRGEDG_BOTH EQU (0x3 << 8) ;- (TC) Edge: each edge\r
+AT91C_TC_EEVTEDG EQU (0x3 << 8) ;- (TC) External Event Edge Selection\r
+AT91C_TC_EEVTEDG_NONE EQU (0x0 << 8) ;- (TC) Edge: None\r
+AT91C_TC_EEVTEDG_RISING EQU (0x1 << 8) ;- (TC) Edge: rising edge\r
+AT91C_TC_EEVTEDG_FALLING EQU (0x2 << 8) ;- (TC) Edge: falling edge\r
+AT91C_TC_EEVTEDG_BOTH EQU (0x3 << 8) ;- (TC) Edge: each edge\r
+AT91C_TC_EEVT EQU (0x3 << 10) ;- (TC) External Event Selection\r
+AT91C_TC_EEVT_TIOB EQU (0x0 << 10) ;- (TC) Signal selected as external event: TIOB TIOB direction: input\r
+AT91C_TC_EEVT_XC0 EQU (0x1 << 10) ;- (TC) Signal selected as external event: XC0 TIOB direction: output\r
+AT91C_TC_EEVT_XC1 EQU (0x2 << 10) ;- (TC) Signal selected as external event: XC1 TIOB direction: output\r
+AT91C_TC_EEVT_XC2 EQU (0x3 << 10) ;- (TC) Signal selected as external event: XC2 TIOB direction: output\r
+AT91C_TC_ABETRG EQU (0x1 << 10) ;- (TC) TIOA or TIOB External Trigger Selection\r
+AT91C_TC_ENETRG EQU (0x1 << 12) ;- (TC) External Event Trigger enable\r
+AT91C_TC_WAVESEL EQU (0x3 << 13) ;- (TC) Waveform Selection\r
+AT91C_TC_WAVESEL_UP EQU (0x0 << 13) ;- (TC) UP mode without atomatic trigger on RC Compare\r
+AT91C_TC_WAVESEL_UPDOWN EQU (0x1 << 13) ;- (TC) UPDOWN mode without automatic trigger on RC Compare\r
+AT91C_TC_WAVESEL_UP_AUTO EQU (0x2 << 13) ;- (TC) UP mode with automatic trigger on RC Compare\r
+AT91C_TC_WAVESEL_UPDOWN_AUTO EQU (0x3 << 13) ;- (TC) UPDOWN mode with automatic trigger on RC Compare\r
+AT91C_TC_CPCTRG EQU (0x1 << 14) ;- (TC) RC Compare Trigger Enable\r
+AT91C_TC_WAVE EQU (0x1 << 15) ;- (TC) \r
+AT91C_TC_ACPA EQU (0x3 << 16) ;- (TC) RA Compare Effect on TIOA\r
+AT91C_TC_ACPA_NONE EQU (0x0 << 16) ;- (TC) Effect: none\r
+AT91C_TC_ACPA_SET EQU (0x1 << 16) ;- (TC) Effect: set\r
+AT91C_TC_ACPA_CLEAR EQU (0x2 << 16) ;- (TC) Effect: clear\r
+AT91C_TC_ACPA_TOGGLE EQU (0x3 << 16) ;- (TC) Effect: toggle\r
+AT91C_TC_LDRA EQU (0x3 << 16) ;- (TC) RA Loading Selection\r
+AT91C_TC_LDRA_NONE EQU (0x0 << 16) ;- (TC) Edge: None\r
+AT91C_TC_LDRA_RISING EQU (0x1 << 16) ;- (TC) Edge: rising edge of TIOA\r
+AT91C_TC_LDRA_FALLING EQU (0x2 << 16) ;- (TC) Edge: falling edge of TIOA\r
+AT91C_TC_LDRA_BOTH EQU (0x3 << 16) ;- (TC) Edge: each edge of TIOA\r
+AT91C_TC_ACPC EQU (0x3 << 18) ;- (TC) RC Compare Effect on TIOA\r
+AT91C_TC_ACPC_NONE EQU (0x0 << 18) ;- (TC) Effect: none\r
+AT91C_TC_ACPC_SET EQU (0x1 << 18) ;- (TC) Effect: set\r
+AT91C_TC_ACPC_CLEAR EQU (0x2 << 18) ;- (TC) Effect: clear\r
+AT91C_TC_ACPC_TOGGLE EQU (0x3 << 18) ;- (TC) Effect: toggle\r
+AT91C_TC_LDRB EQU (0x3 << 18) ;- (TC) RB Loading Selection\r
+AT91C_TC_LDRB_NONE EQU (0x0 << 18) ;- (TC) Edge: None\r
+AT91C_TC_LDRB_RISING EQU (0x1 << 18) ;- (TC) Edge: rising edge of TIOA\r
+AT91C_TC_LDRB_FALLING EQU (0x2 << 18) ;- (TC) Edge: falling edge of TIOA\r
+AT91C_TC_LDRB_BOTH EQU (0x3 << 18) ;- (TC) Edge: each edge of TIOA\r
+AT91C_TC_AEEVT EQU (0x3 << 20) ;- (TC) External Event Effect on TIOA\r
+AT91C_TC_AEEVT_NONE EQU (0x0 << 20) ;- (TC) Effect: none\r
+AT91C_TC_AEEVT_SET EQU (0x1 << 20) ;- (TC) Effect: set\r
+AT91C_TC_AEEVT_CLEAR EQU (0x2 << 20) ;- (TC) Effect: clear\r
+AT91C_TC_AEEVT_TOGGLE EQU (0x3 << 20) ;- (TC) Effect: toggle\r
+AT91C_TC_ASWTRG EQU (0x3 << 22) ;- (TC) Software Trigger Effect on TIOA\r
+AT91C_TC_ASWTRG_NONE EQU (0x0 << 22) ;- (TC) Effect: none\r
+AT91C_TC_ASWTRG_SET EQU (0x1 << 22) ;- (TC) Effect: set\r
+AT91C_TC_ASWTRG_CLEAR EQU (0x2 << 22) ;- (TC) Effect: clear\r
+AT91C_TC_ASWTRG_TOGGLE EQU (0x3 << 22) ;- (TC) Effect: toggle\r
+AT91C_TC_BCPB EQU (0x3 << 24) ;- (TC) RB Compare Effect on TIOB\r
+AT91C_TC_BCPB_NONE EQU (0x0 << 24) ;- (TC) Effect: none\r
+AT91C_TC_BCPB_SET EQU (0x1 << 24) ;- (TC) Effect: set\r
+AT91C_TC_BCPB_CLEAR EQU (0x2 << 24) ;- (TC) Effect: clear\r
+AT91C_TC_BCPB_TOGGLE EQU (0x3 << 24) ;- (TC) Effect: toggle\r
+AT91C_TC_BCPC EQU (0x3 << 26) ;- (TC) RC Compare Effect on TIOB\r
+AT91C_TC_BCPC_NONE EQU (0x0 << 26) ;- (TC) Effect: none\r
+AT91C_TC_BCPC_SET EQU (0x1 << 26) ;- (TC) Effect: set\r
+AT91C_TC_BCPC_CLEAR EQU (0x2 << 26) ;- (TC) Effect: clear\r
+AT91C_TC_BCPC_TOGGLE EQU (0x3 << 26) ;- (TC) Effect: toggle\r
+AT91C_TC_BEEVT EQU (0x3 << 28) ;- (TC) External Event Effect on TIOB\r
+AT91C_TC_BEEVT_NONE EQU (0x0 << 28) ;- (TC) Effect: none\r
+AT91C_TC_BEEVT_SET EQU (0x1 << 28) ;- (TC) Effect: set\r
+AT91C_TC_BEEVT_CLEAR EQU (0x2 << 28) ;- (TC) Effect: clear\r
+AT91C_TC_BEEVT_TOGGLE EQU (0x3 << 28) ;- (TC) Effect: toggle\r
+AT91C_TC_BSWTRG EQU (0x3 << 30) ;- (TC) Software Trigger Effect on TIOB\r
+AT91C_TC_BSWTRG_NONE EQU (0x0 << 30) ;- (TC) Effect: none\r
+AT91C_TC_BSWTRG_SET EQU (0x1 << 30) ;- (TC) Effect: set\r
+AT91C_TC_BSWTRG_CLEAR EQU (0x2 << 30) ;- (TC) Effect: clear\r
+AT91C_TC_BSWTRG_TOGGLE EQU (0x3 << 30) ;- (TC) Effect: toggle\r
+// - -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- \r
+AT91C_TC_COVFS EQU (0x1 << 0) ;- (TC) Counter Overflow\r
+AT91C_TC_LOVRS EQU (0x1 << 1) ;- (TC) Load Overrun\r
+AT91C_TC_CPAS EQU (0x1 << 2) ;- (TC) RA Compare\r
+AT91C_TC_CPBS EQU (0x1 << 3) ;- (TC) RB Compare\r
+AT91C_TC_CPCS EQU (0x1 << 4) ;- (TC) RC Compare\r
+AT91C_TC_LDRAS EQU (0x1 << 5) ;- (TC) RA Loading\r
+AT91C_TC_LDRBS EQU (0x1 << 6) ;- (TC) RB Loading\r
+AT91C_TC_ETRGS EQU (0x1 << 7) ;- (TC) External Trigger\r
+AT91C_TC_CLKSTA EQU (0x1 << 16) ;- (TC) Clock Enabling\r
+AT91C_TC_MTIOA EQU (0x1 << 17) ;- (TC) TIOA Mirror\r
+AT91C_TC_MTIOB EQU (0x1 << 18) ;- (TC) TIOA Mirror\r
+// - -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- \r
+// - -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- \r
+// - -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- \r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Timer Counter Interface\r
+// - *****************************************************************************\r
+// - -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- \r
+AT91C_TCB_SYNC EQU (0x1 << 0) ;- (TCB) Synchro Command\r
+// - -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- \r
+AT91C_TCB_TC0XC0S EQU (0x3 << 0) ;- (TCB) External Clock Signal 0 Selection\r
+AT91C_TCB_TC0XC0S_TCLK0 EQU (0x0) ;- (TCB) TCLK0 connected to XC0\r
+AT91C_TCB_TC0XC0S_NONE EQU (0x1) ;- (TCB) None signal connected to XC0\r
+AT91C_TCB_TC0XC0S_TIOA1 EQU (0x2) ;- (TCB) TIOA1 connected to XC0\r
+AT91C_TCB_TC0XC0S_TIOA2 EQU (0x3) ;- (TCB) TIOA2 connected to XC0\r
+AT91C_TCB_TC1XC1S EQU (0x3 << 2) ;- (TCB) External Clock Signal 1 Selection\r
+AT91C_TCB_TC1XC1S_TCLK1 EQU (0x0 << 2) ;- (TCB) TCLK1 connected to XC1\r
+AT91C_TCB_TC1XC1S_NONE EQU (0x1 << 2) ;- (TCB) None signal connected to XC1\r
+AT91C_TCB_TC1XC1S_TIOA0 EQU (0x2 << 2) ;- (TCB) TIOA0 connected to XC1\r
+AT91C_TCB_TC1XC1S_TIOA2 EQU (0x3 << 2) ;- (TCB) TIOA2 connected to XC1\r
+AT91C_TCB_TC2XC2S EQU (0x3 << 4) ;- (TCB) External Clock Signal 2 Selection\r
+AT91C_TCB_TC2XC2S_TCLK2 EQU (0x0 << 4) ;- (TCB) TCLK2 connected to XC2\r
+AT91C_TCB_TC2XC2S_NONE EQU (0x1 << 4) ;- (TCB) None signal connected to XC2\r
+AT91C_TCB_TC2XC2S_TIOA0 EQU (0x2 << 4) ;- (TCB) TIOA0 connected to XC2\r
+AT91C_TCB_TC2XC2S_TIOA1 EQU (0x3 << 4) ;- (TCB) TIOA2 connected to XC2\r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface\r
+// - *****************************************************************************\r
+// - -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- \r
+AT91C_CAN_MTIMEMARK EQU (0xFFFF << 0) ;- (CAN_MB) Mailbox Timemark\r
+AT91C_CAN_PRIOR EQU (0xF << 16) ;- (CAN_MB) Mailbox Priority\r
+AT91C_CAN_MOT EQU (0x7 << 24) ;- (CAN_MB) Mailbox Object Type\r
+AT91C_CAN_MOT_DIS EQU (0x0 << 24) ;- (CAN_MB) \r
+AT91C_CAN_MOT_RX EQU (0x1 << 24) ;- (CAN_MB) \r
+AT91C_CAN_MOT_RXOVERWRITE EQU (0x2 << 24) ;- (CAN_MB) \r
+AT91C_CAN_MOT_TX EQU (0x3 << 24) ;- (CAN_MB) \r
+AT91C_CAN_MOT_CONSUMER EQU (0x4 << 24) ;- (CAN_MB) \r
+AT91C_CAN_MOT_PRODUCER EQU (0x5 << 24) ;- (CAN_MB) \r
+// - -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- \r
+AT91C_CAN_MIDvB EQU (0x3FFFF << 0) ;- (CAN_MB) Complementary bits for identifier in extended mode\r
+AT91C_CAN_MIDvA EQU (0x7FF << 18) ;- (CAN_MB) Identifier for standard frame mode\r
+AT91C_CAN_MIDE EQU (0x1 << 29) ;- (CAN_MB) Identifier Version\r
+// - -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- \r
+// - -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- \r
+// - -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- \r
+AT91C_CAN_MTIMESTAMP EQU (0xFFFF << 0) ;- (CAN_MB) Timer Value\r
+AT91C_CAN_MDLC EQU (0xF << 16) ;- (CAN_MB) Mailbox Data Length Code\r
+AT91C_CAN_MRTR EQU (0x1 << 20) ;- (CAN_MB) Mailbox Remote Transmission Request\r
+AT91C_CAN_MABT EQU (0x1 << 22) ;- (CAN_MB) Mailbox Message Abort\r
+AT91C_CAN_MRDY EQU (0x1 << 23) ;- (CAN_MB) Mailbox Ready\r
+AT91C_CAN_MMI EQU (0x1 << 24) ;- (CAN_MB) Mailbox Message Ignored\r
+// - -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- \r
+// - -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- \r
+// - -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- \r
+AT91C_CAN_MACR EQU (0x1 << 22) ;- (CAN_MB) Abort Request for Mailbox\r
+AT91C_CAN_MTCR EQU (0x1 << 23) ;- (CAN_MB) Mailbox Transfer Command\r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Control Area Network Interface\r
+// - *****************************************************************************\r
+// - -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- \r
+AT91C_CAN_CANEN EQU (0x1 << 0) ;- (CAN) CAN Controller Enable\r
+AT91C_CAN_LPM EQU (0x1 << 1) ;- (CAN) Disable/Enable Low Power Mode\r
+AT91C_CAN_ABM EQU (0x1 << 2) ;- (CAN) Disable/Enable Autobaud/Listen Mode\r
+AT91C_CAN_OVL EQU (0x1 << 3) ;- (CAN) Disable/Enable Overload Frame\r
+AT91C_CAN_TEOF EQU (0x1 << 4) ;- (CAN) Time Stamp messages at each end of Frame\r
+AT91C_CAN_TTM EQU (0x1 << 5) ;- (CAN) Disable/Enable Time Trigger Mode\r
+AT91C_CAN_TIMFRZ EQU (0x1 << 6) ;- (CAN) Enable Timer Freeze\r
+AT91C_CAN_DRPT EQU (0x1 << 7) ;- (CAN) Disable Repeat\r
+// - -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- \r
+AT91C_CAN_MB0 EQU (0x1 << 0) ;- (CAN) Mailbox 0 Flag\r
+AT91C_CAN_MB1 EQU (0x1 << 1) ;- (CAN) Mailbox 1 Flag\r
+AT91C_CAN_MB2 EQU (0x1 << 2) ;- (CAN) Mailbox 2 Flag\r
+AT91C_CAN_MB3 EQU (0x1 << 3) ;- (CAN) Mailbox 3 Flag\r
+AT91C_CAN_MB4 EQU (0x1 << 4) ;- (CAN) Mailbox 4 Flag\r
+AT91C_CAN_MB5 EQU (0x1 << 5) ;- (CAN) Mailbox 5 Flag\r
+AT91C_CAN_MB6 EQU (0x1 << 6) ;- (CAN) Mailbox 6 Flag\r
+AT91C_CAN_MB7 EQU (0x1 << 7) ;- (CAN) Mailbox 7 Flag\r
+AT91C_CAN_MB8 EQU (0x1 << 8) ;- (CAN) Mailbox 8 Flag\r
+AT91C_CAN_MB9 EQU (0x1 << 9) ;- (CAN) Mailbox 9 Flag\r
+AT91C_CAN_MB10 EQU (0x1 << 10) ;- (CAN) Mailbox 10 Flag\r
+AT91C_CAN_MB11 EQU (0x1 << 11) ;- (CAN) Mailbox 11 Flag\r
+AT91C_CAN_MB12 EQU (0x1 << 12) ;- (CAN) Mailbox 12 Flag\r
+AT91C_CAN_MB13 EQU (0x1 << 13) ;- (CAN) Mailbox 13 Flag\r
+AT91C_CAN_MB14 EQU (0x1 << 14) ;- (CAN) Mailbox 14 Flag\r
+AT91C_CAN_MB15 EQU (0x1 << 15) ;- (CAN) Mailbox 15 Flag\r
+AT91C_CAN_ERRA EQU (0x1 << 16) ;- (CAN) Error Active Mode Flag\r
+AT91C_CAN_WARN EQU (0x1 << 17) ;- (CAN) Warning Limit Flag\r
+AT91C_CAN_ERRP EQU (0x1 << 18) ;- (CAN) Error Passive Mode Flag\r
+AT91C_CAN_BOFF EQU (0x1 << 19) ;- (CAN) Bus Off Mode Flag\r
+AT91C_CAN_SLEEP EQU (0x1 << 20) ;- (CAN) Sleep Flag\r
+AT91C_CAN_WAKEUP EQU (0x1 << 21) ;- (CAN) Wakeup Flag\r
+AT91C_CAN_TOVF EQU (0x1 << 22) ;- (CAN) Timer Overflow Flag\r
+AT91C_CAN_TSTP EQU (0x1 << 23) ;- (CAN) Timestamp Flag\r
+AT91C_CAN_CERR EQU (0x1 << 24) ;- (CAN) CRC Error\r
+AT91C_CAN_SERR EQU (0x1 << 25) ;- (CAN) Stuffing Error\r
+AT91C_CAN_AERR EQU (0x1 << 26) ;- (CAN) Acknowledgment Error\r
+AT91C_CAN_FERR EQU (0x1 << 27) ;- (CAN) Form Error\r
+AT91C_CAN_BERR EQU (0x1 << 28) ;- (CAN) Bit Error\r
+// - -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- \r
+// - -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- \r
+// - -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- \r
+AT91C_CAN_RBSY EQU (0x1 << 29) ;- (CAN) Receiver Busy\r
+AT91C_CAN_TBSY EQU (0x1 << 30) ;- (CAN) Transmitter Busy\r
+AT91C_CAN_OVLY EQU (0x1 << 31) ;- (CAN) Overload Busy\r
+// - -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- \r
+AT91C_CAN_PHASE2 EQU (0x7 << 0) ;- (CAN) Phase 2 segment\r
+AT91C_CAN_PHASE1 EQU (0x7 << 4) ;- (CAN) Phase 1 segment\r
+AT91C_CAN_PROPAG EQU (0x7 << 8) ;- (CAN) Programmation time segment\r
+AT91C_CAN_SYNC EQU (0x3 << 12) ;- (CAN) Re-synchronization jump width segment\r
+AT91C_CAN_BRP EQU (0x7F << 16) ;- (CAN) Baudrate Prescaler\r
+AT91C_CAN_SMP EQU (0x1 << 24) ;- (CAN) Sampling mode\r
+// - -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- \r
+AT91C_CAN_TIMER EQU (0xFFFF << 0) ;- (CAN) Timer field\r
+// - -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- \r
+// - -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- \r
+AT91C_CAN_REC EQU (0xFF << 0) ;- (CAN) Receive Error Counter\r
+AT91C_CAN_TEC EQU (0xFF << 16) ;- (CAN) Transmit Error Counter\r
+// - -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- \r
+AT91C_CAN_TIMRST EQU (0x1 << 31) ;- (CAN) Timer Reset Field\r
+// - -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- \r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Ethernet MAC 10/100\r
+// - *****************************************************************************\r
+// - -------- EMAC_NCR : (EMAC Offset: 0x0) -------- \r
+AT91C_EMAC_LB EQU (0x1 << 0) ;- (EMAC) Loopback. Optional. When set, loopback signal is at high level.\r
+AT91C_EMAC_LLB EQU (0x1 << 1) ;- (EMAC) Loopback local. \r
+AT91C_EMAC_RE EQU (0x1 << 2) ;- (EMAC) Receive enable. \r
+AT91C_EMAC_TE EQU (0x1 << 3) ;- (EMAC) Transmit enable. \r
+AT91C_EMAC_MPE EQU (0x1 << 4) ;- (EMAC) Management port enable. \r
+AT91C_EMAC_CLRSTAT EQU (0x1 << 5) ;- (EMAC) Clear statistics registers. \r
+AT91C_EMAC_INCSTAT EQU (0x1 << 6) ;- (EMAC) Increment statistics registers. \r
+AT91C_EMAC_WESTAT EQU (0x1 << 7) ;- (EMAC) Write enable for statistics registers. \r
+AT91C_EMAC_BP EQU (0x1 << 8) ;- (EMAC) Back pressure. \r
+AT91C_EMAC_TSTART EQU (0x1 << 9) ;- (EMAC) Start Transmission. \r
+AT91C_EMAC_THALT EQU (0x1 << 10) ;- (EMAC) Transmission Halt. \r
+AT91C_EMAC_TPFR EQU (0x1 << 11) ;- (EMAC) Transmit pause frame \r
+AT91C_EMAC_TZQ EQU (0x1 << 12) ;- (EMAC) Transmit zero quantum pause frame\r
+// - -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- \r
+AT91C_EMAC_SPD EQU (0x1 << 0) ;- (EMAC) Speed. \r
+AT91C_EMAC_FD EQU (0x1 << 1) ;- (EMAC) Full duplex. \r
+AT91C_EMAC_JFRAME EQU (0x1 << 3) ;- (EMAC) Jumbo Frames. \r
+AT91C_EMAC_CAF EQU (0x1 << 4) ;- (EMAC) Copy all frames. \r
+AT91C_EMAC_NBC EQU (0x1 << 5) ;- (EMAC) No broadcast. \r
+AT91C_EMAC_MTI EQU (0x1 << 6) ;- (EMAC) Multicast hash event enable\r
+AT91C_EMAC_UNI EQU (0x1 << 7) ;- (EMAC) Unicast hash enable. \r
+AT91C_EMAC_BIG EQU (0x1 << 8) ;- (EMAC) Receive 1522 bytes. \r
+AT91C_EMAC_EAE EQU (0x1 << 9) ;- (EMAC) External address match enable. \r
+AT91C_EMAC_CLK EQU (0x3 << 10) ;- (EMAC) \r
+AT91C_EMAC_CLK_HCLK_8 EQU (0x0 << 10) ;- (EMAC) HCLK divided by 8\r
+AT91C_EMAC_CLK_HCLK_16 EQU (0x1 << 10) ;- (EMAC) HCLK divided by 16\r
+AT91C_EMAC_CLK_HCLK_32 EQU (0x2 << 10) ;- (EMAC) HCLK divided by 32\r
+AT91C_EMAC_CLK_HCLK_64 EQU (0x3 << 10) ;- (EMAC) HCLK divided by 64\r
+AT91C_EMAC_RTY EQU (0x1 << 12) ;- (EMAC) \r
+AT91C_EMAC_PAE EQU (0x1 << 13) ;- (EMAC) \r
+AT91C_EMAC_RBOF EQU (0x3 << 14) ;- (EMAC) \r
+AT91C_EMAC_RBOF_OFFSET_0 EQU (0x0 << 14) ;- (EMAC) no offset from start of receive buffer\r
+AT91C_EMAC_RBOF_OFFSET_1 EQU (0x1 << 14) ;- (EMAC) one byte offset from start of receive buffer\r
+AT91C_EMAC_RBOF_OFFSET_2 EQU (0x2 << 14) ;- (EMAC) two bytes offset from start of receive buffer\r
+AT91C_EMAC_RBOF_OFFSET_3 EQU (0x3 << 14) ;- (EMAC) three bytes offset from start of receive buffer\r
+AT91C_EMAC_RLCE EQU (0x1 << 16) ;- (EMAC) Receive Length field Checking Enable\r
+AT91C_EMAC_DRFCS EQU (0x1 << 17) ;- (EMAC) Discard Receive FCS\r
+AT91C_EMAC_EFRHD EQU (0x1 << 18) ;- (EMAC) \r
+AT91C_EMAC_IRXFCS EQU (0x1 << 19) ;- (EMAC) Ignore RX FCS\r
+// - -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- \r
+AT91C_EMAC_LINKR EQU (0x1 << 0) ;- (EMAC) \r
+AT91C_EMAC_MDIO EQU (0x1 << 1) ;- (EMAC) \r
+AT91C_EMAC_IDLE EQU (0x1 << 2) ;- (EMAC) \r
+// - -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- \r
+AT91C_EMAC_UBR EQU (0x1 << 0) ;- (EMAC) \r
+AT91C_EMAC_COL EQU (0x1 << 1) ;- (EMAC) \r
+AT91C_EMAC_RLES EQU (0x1 << 2) ;- (EMAC) \r
+AT91C_EMAC_TGO EQU (0x1 << 3) ;- (EMAC) Transmit Go\r
+AT91C_EMAC_BEX EQU (0x1 << 4) ;- (EMAC) Buffers exhausted mid frame\r
+AT91C_EMAC_COMP EQU (0x1 << 5) ;- (EMAC) \r
+AT91C_EMAC_UND EQU (0x1 << 6) ;- (EMAC) \r
+// - -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- \r
+AT91C_EMAC_BNA EQU (0x1 << 0) ;- (EMAC) \r
+AT91C_EMAC_REC EQU (0x1 << 1) ;- (EMAC) \r
+AT91C_EMAC_OVR EQU (0x1 << 2) ;- (EMAC) \r
+// - -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- \r
+AT91C_EMAC_MFD EQU (0x1 << 0) ;- (EMAC) \r
+AT91C_EMAC_RCOMP EQU (0x1 << 1) ;- (EMAC) \r
+AT91C_EMAC_RXUBR EQU (0x1 << 2) ;- (EMAC) \r
+AT91C_EMAC_TXUBR EQU (0x1 << 3) ;- (EMAC) \r
+AT91C_EMAC_TUNDR EQU (0x1 << 4) ;- (EMAC) \r
+AT91C_EMAC_RLEX EQU (0x1 << 5) ;- (EMAC) \r
+AT91C_EMAC_TXERR EQU (0x1 << 6) ;- (EMAC) \r
+AT91C_EMAC_TCOMP EQU (0x1 << 7) ;- (EMAC) \r
+AT91C_EMAC_LINK EQU (0x1 << 9) ;- (EMAC) \r
+AT91C_EMAC_ROVR EQU (0x1 << 10) ;- (EMAC) \r
+AT91C_EMAC_HRESP EQU (0x1 << 11) ;- (EMAC) \r
+AT91C_EMAC_PFRE EQU (0x1 << 12) ;- (EMAC) \r
+AT91C_EMAC_PTZ EQU (0x1 << 13) ;- (EMAC) \r
+// - -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- \r
+// - -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- \r
+// - -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- \r
+// - -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- \r
+AT91C_EMAC_DATA EQU (0xFFFF << 0) ;- (EMAC) \r
+AT91C_EMAC_CODE EQU (0x3 << 16) ;- (EMAC) \r
+AT91C_EMAC_REGA EQU (0x1F << 18) ;- (EMAC) \r
+AT91C_EMAC_PHYA EQU (0x1F << 23) ;- (EMAC) \r
+AT91C_EMAC_RW EQU (0x3 << 28) ;- (EMAC) \r
+AT91C_EMAC_SOF EQU (0x3 << 30) ;- (EMAC) \r
+// - -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- \r
+AT91C_EMAC_RMII EQU (0x1 << 0) ;- (EMAC) Reduce MII\r
+// - -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- \r
+AT91C_EMAC_IP EQU (0xFFFF << 0) ;- (EMAC) ARP request IP address\r
+AT91C_EMAC_MAG EQU (0x1 << 16) ;- (EMAC) Magic packet event enable\r
+AT91C_EMAC_ARP EQU (0x1 << 17) ;- (EMAC) ARP request event enable\r
+AT91C_EMAC_SA1 EQU (0x1 << 18) ;- (EMAC) Specific address register 1 event enable\r
+// - -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- \r
+AT91C_EMAC_REVREF EQU (0xFFFF << 0) ;- (EMAC) \r
+AT91C_EMAC_PARTREF EQU (0xFFFF << 16) ;- (EMAC) \r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Analog to Digital Convertor\r
+// - *****************************************************************************\r
+// - -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- \r
+AT91C_ADC_SWRST EQU (0x1 << 0) ;- (ADC) Software Reset\r
+AT91C_ADC_START EQU (0x1 << 1) ;- (ADC) Start Conversion\r
+// - -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- \r
+AT91C_ADC_TRGEN EQU (0x1 << 0) ;- (ADC) Trigger Enable\r
+AT91C_ADC_TRGEN_DIS EQU (0x0) ;- (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software\r
+AT91C_ADC_TRGEN_EN EQU (0x1) ;- (ADC) Hardware trigger selected by TRGSEL field is enabled.\r
+AT91C_ADC_TRGSEL EQU (0x7 << 1) ;- (ADC) Trigger Selection\r
+AT91C_ADC_TRGSEL_TIOA0 EQU (0x0 << 1) ;- (ADC) Selected TRGSEL = TIAO0\r
+AT91C_ADC_TRGSEL_TIOA1 EQU (0x1 << 1) ;- (ADC) Selected TRGSEL = TIAO1\r
+AT91C_ADC_TRGSEL_TIOA2 EQU (0x2 << 1) ;- (ADC) Selected TRGSEL = TIAO2\r
+AT91C_ADC_TRGSEL_TIOA3 EQU (0x3 << 1) ;- (ADC) Selected TRGSEL = TIAO3\r
+AT91C_ADC_TRGSEL_TIOA4 EQU (0x4 << 1) ;- (ADC) Selected TRGSEL = TIAO4\r
+AT91C_ADC_TRGSEL_TIOA5 EQU (0x5 << 1) ;- (ADC) Selected TRGSEL = TIAO5\r
+AT91C_ADC_TRGSEL_EXT EQU (0x6 << 1) ;- (ADC) Selected TRGSEL = External Trigger\r
+AT91C_ADC_LOWRES EQU (0x1 << 4) ;- (ADC) Resolution.\r
+AT91C_ADC_LOWRES_10_BIT EQU (0x0 << 4) ;- (ADC) 10-bit resolution\r
+AT91C_ADC_LOWRES_8_BIT EQU (0x1 << 4) ;- (ADC) 8-bit resolution\r
+AT91C_ADC_SLEEP EQU (0x1 << 5) ;- (ADC) Sleep Mode\r
+AT91C_ADC_SLEEP_NORMAL_MODE EQU (0x0 << 5) ;- (ADC) Normal Mode\r
+AT91C_ADC_SLEEP_MODE EQU (0x1 << 5) ;- (ADC) Sleep Mode\r
+AT91C_ADC_PRESCAL EQU (0x3F << 8) ;- (ADC) Prescaler rate selection\r
+AT91C_ADC_STARTUP EQU (0x1F << 16) ;- (ADC) Startup Time\r
+AT91C_ADC_SHTIM EQU (0xF << 24) ;- (ADC) Sample & Hold Time\r
+// - -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- \r
+AT91C_ADC_CH0 EQU (0x1 << 0) ;- (ADC) Channel 0\r
+AT91C_ADC_CH1 EQU (0x1 << 1) ;- (ADC) Channel 1\r
+AT91C_ADC_CH2 EQU (0x1 << 2) ;- (ADC) Channel 2\r
+AT91C_ADC_CH3 EQU (0x1 << 3) ;- (ADC) Channel 3\r
+AT91C_ADC_CH4 EQU (0x1 << 4) ;- (ADC) Channel 4\r
+AT91C_ADC_CH5 EQU (0x1 << 5) ;- (ADC) Channel 5\r
+AT91C_ADC_CH6 EQU (0x1 << 6) ;- (ADC) Channel 6\r
+AT91C_ADC_CH7 EQU (0x1 << 7) ;- (ADC) Channel 7\r
+// - -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- \r
+// - -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- \r
+// - -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- \r
+AT91C_ADC_EOC0 EQU (0x1 << 0) ;- (ADC) End of Conversion\r
+AT91C_ADC_EOC1 EQU (0x1 << 1) ;- (ADC) End of Conversion\r
+AT91C_ADC_EOC2 EQU (0x1 << 2) ;- (ADC) End of Conversion\r
+AT91C_ADC_EOC3 EQU (0x1 << 3) ;- (ADC) End of Conversion\r
+AT91C_ADC_EOC4 EQU (0x1 << 4) ;- (ADC) End of Conversion\r
+AT91C_ADC_EOC5 EQU (0x1 << 5) ;- (ADC) End of Conversion\r
+AT91C_ADC_EOC6 EQU (0x1 << 6) ;- (ADC) End of Conversion\r
+AT91C_ADC_EOC7 EQU (0x1 << 7) ;- (ADC) End of Conversion\r
+AT91C_ADC_OVRE0 EQU (0x1 << 8) ;- (ADC) Overrun Error\r
+AT91C_ADC_OVRE1 EQU (0x1 << 9) ;- (ADC) Overrun Error\r
+AT91C_ADC_OVRE2 EQU (0x1 << 10) ;- (ADC) Overrun Error\r
+AT91C_ADC_OVRE3 EQU (0x1 << 11) ;- (ADC) Overrun Error\r
+AT91C_ADC_OVRE4 EQU (0x1 << 12) ;- (ADC) Overrun Error\r
+AT91C_ADC_OVRE5 EQU (0x1 << 13) ;- (ADC) Overrun Error\r
+AT91C_ADC_OVRE6 EQU (0x1 << 14) ;- (ADC) Overrun Error\r
+AT91C_ADC_OVRE7 EQU (0x1 << 15) ;- (ADC) Overrun Error\r
+AT91C_ADC_DRDY EQU (0x1 << 16) ;- (ADC) Data Ready\r
+AT91C_ADC_GOVRE EQU (0x1 << 17) ;- (ADC) General Overrun\r
+AT91C_ADC_ENDRX EQU (0x1 << 18) ;- (ADC) End of Receiver Transfer\r
+AT91C_ADC_RXBUFF EQU (0x1 << 19) ;- (ADC) RXBUFF Interrupt\r
+// - -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- \r
+AT91C_ADC_LDATA EQU (0x3FF << 0) ;- (ADC) Last Data Converted\r
+// - -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- \r
+// - -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- \r
+// - -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- \r
+// - -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- \r
+AT91C_ADC_DATA EQU (0x3FF << 0) ;- (ADC) Converted Data\r
+// - -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- \r
+// - -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- \r
+// - -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- \r
+// - -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- \r
+// - -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- \r
+// - -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- \r
+// - -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- \r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Advanced Encryption Standard\r
+// - *****************************************************************************\r
+// - -------- AES_CR : (AES Offset: 0x0) Control Register -------- \r
+AT91C_AES_START EQU (0x1 << 0) ;- (AES) Starts Processing\r
+AT91C_AES_SWRST EQU (0x1 << 8) ;- (AES) Software Reset\r
+AT91C_AES_LOADSEED EQU (0x1 << 16) ;- (AES) Random Number Generator Seed Loading\r
+// - -------- AES_MR : (AES Offset: 0x4) Mode Register -------- \r
+AT91C_AES_CIPHER EQU (0x1 << 0) ;- (AES) Processing Mode\r
+AT91C_AES_PROCDLY EQU (0xF << 4) ;- (AES) Processing Delay\r
+AT91C_AES_SMOD EQU (0x3 << 8) ;- (AES) Start Mode\r
+AT91C_AES_SMOD_MANUAL EQU (0x0 << 8) ;- (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.\r
+AT91C_AES_SMOD_AUTO EQU (0x1 << 8) ;- (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).\r
+AT91C_AES_SMOD_PDC EQU (0x2 << 8) ;- (AES) PDC Mode (cf datasheet).\r
+AT91C_AES_OPMOD EQU (0x7 << 12) ;- (AES) Operation Mode\r
+AT91C_AES_OPMOD_ECB EQU (0x0 << 12) ;- (AES) ECB Electronic CodeBook mode.\r
+AT91C_AES_OPMOD_CBC EQU (0x1 << 12) ;- (AES) CBC Cipher Block Chaining mode.\r
+AT91C_AES_OPMOD_OFB EQU (0x2 << 12) ;- (AES) OFB Output Feedback mode.\r
+AT91C_AES_OPMOD_CFB EQU (0x3 << 12) ;- (AES) CFB Cipher Feedback mode.\r
+AT91C_AES_OPMOD_CTR EQU (0x4 << 12) ;- (AES) CTR Counter mode.\r
+AT91C_AES_LOD EQU (0x1 << 15) ;- (AES) Last Output Data Mode\r
+AT91C_AES_CFBS EQU (0x7 << 16) ;- (AES) Cipher Feedback Data Size\r
+AT91C_AES_CFBS_128_BIT EQU (0x0 << 16) ;- (AES) 128-bit.\r
+AT91C_AES_CFBS_64_BIT EQU (0x1 << 16) ;- (AES) 64-bit.\r
+AT91C_AES_CFBS_32_BIT EQU (0x2 << 16) ;- (AES) 32-bit.\r
+AT91C_AES_CFBS_16_BIT EQU (0x3 << 16) ;- (AES) 16-bit.\r
+AT91C_AES_CFBS_8_BIT EQU (0x4 << 16) ;- (AES) 8-bit.\r
+AT91C_AES_CKEY EQU (0xF << 20) ;- (AES) Countermeasure Key\r
+AT91C_AES_CTYPE EQU (0x1F << 24) ;- (AES) Countermeasure Type\r
+AT91C_AES_CTYPE_TYPE1_EN EQU (0x1 << 24) ;- (AES) Countermeasure type 1 is enabled.\r
+AT91C_AES_CTYPE_TYPE2_EN EQU (0x2 << 24) ;- (AES) Countermeasure type 2 is enabled.\r
+AT91C_AES_CTYPE_TYPE3_EN EQU (0x4 << 24) ;- (AES) Countermeasure type 3 is enabled.\r
+AT91C_AES_CTYPE_TYPE4_EN EQU (0x8 << 24) ;- (AES) Countermeasure type 4 is enabled.\r
+AT91C_AES_CTYPE_TYPE5_EN EQU (0x10 << 24) ;- (AES) Countermeasure type 5 is enabled.\r
+// - -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- \r
+AT91C_AES_DATRDY EQU (0x1 << 0) ;- (AES) DATRDY\r
+AT91C_AES_ENDRX EQU (0x1 << 1) ;- (AES) PDC Read Buffer End\r
+AT91C_AES_ENDTX EQU (0x1 << 2) ;- (AES) PDC Write Buffer End\r
+AT91C_AES_RXBUFF EQU (0x1 << 3) ;- (AES) PDC Read Buffer Full\r
+AT91C_AES_TXBUFE EQU (0x1 << 4) ;- (AES) PDC Write Buffer Empty\r
+AT91C_AES_URAD EQU (0x1 << 8) ;- (AES) Unspecified Register Access Detection\r
+// - -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- \r
+// - -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- \r
+// - -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- \r
+AT91C_AES_URAT EQU (0x7 << 12) ;- (AES) Unspecified Register Access Type Status\r
+AT91C_AES_URAT_IN_DAT_WRITE_DATPROC EQU (0x0 << 12) ;- (AES) Input data register written during the data processing in PDC mode.\r
+AT91C_AES_URAT_OUT_DAT_READ_DATPROC EQU (0x1 << 12) ;- (AES) Output data register read during the data processing.\r
+AT91C_AES_URAT_MODEREG_WRITE_DATPROC EQU (0x2 << 12) ;- (AES) Mode register written during the data processing.\r
+AT91C_AES_URAT_OUT_DAT_READ_SUBKEY EQU (0x3 << 12) ;- (AES) Output data register read during the sub-keys generation.\r
+AT91C_AES_URAT_MODEREG_WRITE_SUBKEY EQU (0x4 << 12) ;- (AES) Mode register written during the sub-keys generation.\r
+AT91C_AES_URAT_WO_REG_READ EQU (0x5 << 12) ;- (AES) Write-only register read access.\r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Triple Data Encryption Standard\r
+// - *****************************************************************************\r
+// - -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- \r
+AT91C_TDES_START EQU (0x1 << 0) ;- (TDES) Starts Processing\r
+AT91C_TDES_SWRST EQU (0x1 << 8) ;- (TDES) Software Reset\r
+// - -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- \r
+AT91C_TDES_CIPHER EQU (0x1 << 0) ;- (TDES) Processing Mode\r
+AT91C_TDES_TDESMOD EQU (0x1 << 1) ;- (TDES) Single or Triple DES Mode\r
+AT91C_TDES_KEYMOD EQU (0x1 << 4) ;- (TDES) Key Mode\r
+AT91C_TDES_SMOD EQU (0x3 << 8) ;- (TDES) Start Mode\r
+AT91C_TDES_SMOD_MANUAL EQU (0x0 << 8) ;- (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.\r
+AT91C_TDES_SMOD_AUTO EQU (0x1 << 8) ;- (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).\r
+AT91C_TDES_SMOD_PDC EQU (0x2 << 8) ;- (TDES) PDC Mode (cf datasheet).\r
+AT91C_TDES_OPMOD EQU (0x3 << 12) ;- (TDES) Operation Mode\r
+AT91C_TDES_OPMOD_ECB EQU (0x0 << 12) ;- (TDES) ECB Electronic CodeBook mode.\r
+AT91C_TDES_OPMOD_CBC EQU (0x1 << 12) ;- (TDES) CBC Cipher Block Chaining mode.\r
+AT91C_TDES_OPMOD_OFB EQU (0x2 << 12) ;- (TDES) OFB Output Feedback mode.\r
+AT91C_TDES_OPMOD_CFB EQU (0x3 << 12) ;- (TDES) CFB Cipher Feedback mode.\r
+AT91C_TDES_LOD EQU (0x1 << 15) ;- (TDES) Last Output Data Mode\r
+AT91C_TDES_CFBS EQU (0x3 << 16) ;- (TDES) Cipher Feedback Data Size\r
+AT91C_TDES_CFBS_64_BIT EQU (0x0 << 16) ;- (TDES) 64-bit.\r
+AT91C_TDES_CFBS_32_BIT EQU (0x1 << 16) ;- (TDES) 32-bit.\r
+AT91C_TDES_CFBS_16_BIT EQU (0x2 << 16) ;- (TDES) 16-bit.\r
+AT91C_TDES_CFBS_8_BIT EQU (0x3 << 16) ;- (TDES) 8-bit.\r
+// - -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- \r
+AT91C_TDES_DATRDY EQU (0x1 << 0) ;- (TDES) DATRDY\r
+AT91C_TDES_ENDRX EQU (0x1 << 1) ;- (TDES) PDC Read Buffer End\r
+AT91C_TDES_ENDTX EQU (0x1 << 2) ;- (TDES) PDC Write Buffer End\r
+AT91C_TDES_RXBUFF EQU (0x1 << 3) ;- (TDES) PDC Read Buffer Full\r
+AT91C_TDES_TXBUFE EQU (0x1 << 4) ;- (TDES) PDC Write Buffer Empty\r
+AT91C_TDES_URAD EQU (0x1 << 8) ;- (TDES) Unspecified Register Access Detection\r
+// - -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- \r
+// - -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- \r
+// - -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- \r
+AT91C_TDES_URAT EQU (0x3 << 12) ;- (TDES) Unspecified Register Access Type Status\r
+AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC EQU (0x0 << 12) ;- (TDES) Input data register written during the data processing in PDC mode.\r
+AT91C_TDES_URAT_OUT_DAT_READ_DATPROC EQU (0x1 << 12) ;- (TDES) Output data register read during the data processing.\r
+AT91C_TDES_URAT_MODEREG_WRITE_DATPROC EQU (0x2 << 12) ;- (TDES) Mode register written during the data processing.\r
+AT91C_TDES_URAT_WO_REG_READ EQU (0x3 << 12) ;- (TDES) Write-only register read access.\r
+\r
+// - *****************************************************************************\r
+// - REGISTER ADDRESS DEFINITION FOR AT91SAM7X128\r
+// - *****************************************************************************\r
+// - ========== Register definition for SYS peripheral ========== \r
+// - ========== Register definition for AIC peripheral ========== \r
+AT91C_AIC_IVR EQU (0xFFFFF100) ;- (AIC) IRQ Vector Register\r
+AT91C_AIC_SMR EQU (0xFFFFF000) ;- (AIC) Source Mode Register\r
+AT91C_AIC_FVR EQU (0xFFFFF104) ;- (AIC) FIQ Vector Register\r
+AT91C_AIC_DCR EQU (0xFFFFF138) ;- (AIC) Debug Control Register (Protect)\r
+AT91C_AIC_EOICR EQU (0xFFFFF130) ;- (AIC) End of Interrupt Command Register\r
+AT91C_AIC_SVR EQU (0xFFFFF080) ;- (AIC) Source Vector Register\r
+AT91C_AIC_FFSR EQU (0xFFFFF148) ;- (AIC) Fast Forcing Status Register\r
+AT91C_AIC_ICCR EQU (0xFFFFF128) ;- (AIC) Interrupt Clear Command Register\r
+AT91C_AIC_ISR EQU (0xFFFFF108) ;- (AIC) Interrupt Status Register\r
+AT91C_AIC_IMR EQU (0xFFFFF110) ;- (AIC) Interrupt Mask Register\r
+AT91C_AIC_IPR EQU (0xFFFFF10C) ;- (AIC) Interrupt Pending Register\r
+AT91C_AIC_FFER EQU (0xFFFFF140) ;- (AIC) Fast Forcing Enable Register\r
+AT91C_AIC_IECR EQU (0xFFFFF120) ;- (AIC) Interrupt Enable Command Register\r
+AT91C_AIC_ISCR EQU (0xFFFFF12C) ;- (AIC) Interrupt Set Command Register\r
+AT91C_AIC_FFDR EQU (0xFFFFF144) ;- (AIC) Fast Forcing Disable Register\r
+AT91C_AIC_CISR EQU (0xFFFFF114) ;- (AIC) Core Interrupt Status Register\r
+AT91C_AIC_IDCR EQU (0xFFFFF124) ;- (AIC) Interrupt Disable Command Register\r
+AT91C_AIC_SPU EQU (0xFFFFF134) ;- (AIC) Spurious Vector Register\r
+// - ========== Register definition for PDC_DBGU peripheral ========== \r
+AT91C_DBGU_TCR EQU (0xFFFFF30C) ;- (PDC_DBGU) Transmit Counter Register\r
+AT91C_DBGU_RNPR EQU (0xFFFFF310) ;- (PDC_DBGU) Receive Next Pointer Register\r
+AT91C_DBGU_TNPR EQU (0xFFFFF318) ;- (PDC_DBGU) Transmit Next Pointer Register\r
+AT91C_DBGU_TPR EQU (0xFFFFF308) ;- (PDC_DBGU) Transmit Pointer Register\r
+AT91C_DBGU_RPR EQU (0xFFFFF300) ;- (PDC_DBGU) Receive Pointer Register\r
+AT91C_DBGU_RCR EQU (0xFFFFF304) ;- (PDC_DBGU) Receive Counter Register\r
+AT91C_DBGU_RNCR EQU (0xFFFFF314) ;- (PDC_DBGU) Receive Next Counter Register\r
+AT91C_DBGU_PTCR EQU (0xFFFFF320) ;- (PDC_DBGU) PDC Transfer Control Register\r
+AT91C_DBGU_PTSR EQU (0xFFFFF324) ;- (PDC_DBGU) PDC Transfer Status Register\r
+AT91C_DBGU_TNCR EQU (0xFFFFF31C) ;- (PDC_DBGU) Transmit Next Counter Register\r
+// - ========== Register definition for DBGU peripheral ========== \r
+AT91C_DBGU_EXID EQU (0xFFFFF244) ;- (DBGU) Chip ID Extension Register\r
+AT91C_DBGU_BRGR EQU (0xFFFFF220) ;- (DBGU) Baud Rate Generator Register\r
+AT91C_DBGU_IDR EQU (0xFFFFF20C) ;- (DBGU) Interrupt Disable Register\r
+AT91C_DBGU_CSR EQU (0xFFFFF214) ;- (DBGU) Channel Status Register\r
+AT91C_DBGU_CIDR EQU (0xFFFFF240) ;- (DBGU) Chip ID Register\r
+AT91C_DBGU_MR EQU (0xFFFFF204) ;- (DBGU) Mode Register\r
+AT91C_DBGU_IMR EQU (0xFFFFF210) ;- (DBGU) Interrupt Mask Register\r
+AT91C_DBGU_CR EQU (0xFFFFF200) ;- (DBGU) Control Register\r
+AT91C_DBGU_FNTR EQU (0xFFFFF248) ;- (DBGU) Force NTRST Register\r
+AT91C_DBGU_THR EQU (0xFFFFF21C) ;- (DBGU) Transmitter Holding Register\r
+AT91C_DBGU_RHR EQU (0xFFFFF218) ;- (DBGU) Receiver Holding Register\r
+AT91C_DBGU_IER EQU (0xFFFFF208) ;- (DBGU) Interrupt Enable Register\r
+// - ========== Register definition for PIOA peripheral ========== \r
+AT91C_PIOA_ODR EQU (0xFFFFF414) ;- (PIOA) Output Disable Registerr\r
+AT91C_PIOA_SODR EQU (0xFFFFF430) ;- (PIOA) Set Output Data Register\r
+AT91C_PIOA_ISR EQU (0xFFFFF44C) ;- (PIOA) Interrupt Status Register\r
+AT91C_PIOA_ABSR EQU (0xFFFFF478) ;- (PIOA) AB Select Status Register\r
+AT91C_PIOA_IER EQU (0xFFFFF440) ;- (PIOA) Interrupt Enable Register\r
+AT91C_PIOA_PPUDR EQU (0xFFFFF460) ;- (PIOA) Pull-up Disable Register\r
+AT91C_PIOA_IMR EQU (0xFFFFF448) ;- (PIOA) Interrupt Mask Register\r
+AT91C_PIOA_PER EQU (0xFFFFF400) ;- (PIOA) PIO Enable Register\r
+AT91C_PIOA_IFDR EQU (0xFFFFF424) ;- (PIOA) Input Filter Disable Register\r
+AT91C_PIOA_OWDR EQU (0xFFFFF4A4) ;- (PIOA) Output Write Disable Register\r
+AT91C_PIOA_MDSR EQU (0xFFFFF458) ;- (PIOA) Multi-driver Status Register\r
+AT91C_PIOA_IDR EQU (0xFFFFF444) ;- (PIOA) Interrupt Disable Register\r
+AT91C_PIOA_ODSR EQU (0xFFFFF438) ;- (PIOA) Output Data Status Register\r
+AT91C_PIOA_PPUSR EQU (0xFFFFF468) ;- (PIOA) Pull-up Status Register\r
+AT91C_PIOA_OWSR EQU (0xFFFFF4A8) ;- (PIOA) Output Write Status Register\r
+AT91C_PIOA_BSR EQU (0xFFFFF474) ;- (PIOA) Select B Register\r
+AT91C_PIOA_OWER EQU (0xFFFFF4A0) ;- (PIOA) Output Write Enable Register\r
+AT91C_PIOA_IFER EQU (0xFFFFF420) ;- (PIOA) Input Filter Enable Register\r
+AT91C_PIOA_PDSR EQU (0xFFFFF43C) ;- (PIOA) Pin Data Status Register\r
+AT91C_PIOA_PPUER EQU (0xFFFFF464) ;- (PIOA) Pull-up Enable Register\r
+AT91C_PIOA_OSR EQU (0xFFFFF418) ;- (PIOA) Output Status Register\r
+AT91C_PIOA_ASR EQU (0xFFFFF470) ;- (PIOA) Select A Register\r
+AT91C_PIOA_MDDR EQU (0xFFFFF454) ;- (PIOA) Multi-driver Disable Register\r
+AT91C_PIOA_CODR EQU (0xFFFFF434) ;- (PIOA) Clear Output Data Register\r
+AT91C_PIOA_MDER EQU (0xFFFFF450) ;- (PIOA) Multi-driver Enable Register\r
+AT91C_PIOA_PDR EQU (0xFFFFF404) ;- (PIOA) PIO Disable Register\r
+AT91C_PIOA_IFSR EQU (0xFFFFF428) ;- (PIOA) Input Filter Status Register\r
+AT91C_PIOA_OER EQU (0xFFFFF410) ;- (PIOA) Output Enable Register\r
+AT91C_PIOA_PSR EQU (0xFFFFF408) ;- (PIOA) PIO Status Register\r
+// - ========== Register definition for PIOB peripheral ========== \r
+AT91C_PIOB_OWDR EQU (0xFFFFF6A4) ;- (PIOB) Output Write Disable Register\r
+AT91C_PIOB_MDER EQU (0xFFFFF650) ;- (PIOB) Multi-driver Enable Register\r
+AT91C_PIOB_PPUSR EQU (0xFFFFF668) ;- (PIOB) Pull-up Status Register\r
+AT91C_PIOB_IMR EQU (0xFFFFF648) ;- (PIOB) Interrupt Mask Register\r
+AT91C_PIOB_ASR EQU (0xFFFFF670) ;- (PIOB) Select A Register\r
+AT91C_PIOB_PPUDR EQU (0xFFFFF660) ;- (PIOB) Pull-up Disable Register\r
+AT91C_PIOB_PSR EQU (0xFFFFF608) ;- (PIOB) PIO Status Register\r
+AT91C_PIOB_IER EQU (0xFFFFF640) ;- (PIOB) Interrupt Enable Register\r
+AT91C_PIOB_CODR EQU (0xFFFFF634) ;- (PIOB) Clear Output Data Register\r
+AT91C_PIOB_OWER EQU (0xFFFFF6A0) ;- (PIOB) Output Write Enable Register\r
+AT91C_PIOB_ABSR EQU (0xFFFFF678) ;- (PIOB) AB Select Status Register\r
+AT91C_PIOB_IFDR EQU (0xFFFFF624) ;- (PIOB) Input Filter Disable Register\r
+AT91C_PIOB_PDSR EQU (0xFFFFF63C) ;- (PIOB) Pin Data Status Register\r
+AT91C_PIOB_IDR EQU (0xFFFFF644) ;- (PIOB) Interrupt Disable Register\r
+AT91C_PIOB_OWSR EQU (0xFFFFF6A8) ;- (PIOB) Output Write Status Register\r
+AT91C_PIOB_PDR EQU (0xFFFFF604) ;- (PIOB) PIO Disable Register\r
+AT91C_PIOB_ODR EQU (0xFFFFF614) ;- (PIOB) Output Disable Registerr\r
+AT91C_PIOB_IFSR EQU (0xFFFFF628) ;- (PIOB) Input Filter Status Register\r
+AT91C_PIOB_PPUER EQU (0xFFFFF664) ;- (PIOB) Pull-up Enable Register\r
+AT91C_PIOB_SODR EQU (0xFFFFF630) ;- (PIOB) Set Output Data Register\r
+AT91C_PIOB_ISR EQU (0xFFFFF64C) ;- (PIOB) Interrupt Status Register\r
+AT91C_PIOB_ODSR EQU (0xFFFFF638) ;- (PIOB) Output Data Status Register\r
+AT91C_PIOB_OSR EQU (0xFFFFF618) ;- (PIOB) Output Status Register\r
+AT91C_PIOB_MDSR EQU (0xFFFFF658) ;- (PIOB) Multi-driver Status Register\r
+AT91C_PIOB_IFER EQU (0xFFFFF620) ;- (PIOB) Input Filter Enable Register\r
+AT91C_PIOB_BSR EQU (0xFFFFF674) ;- (PIOB) Select B Register\r
+AT91C_PIOB_MDDR EQU (0xFFFFF654) ;- (PIOB) Multi-driver Disable Register\r
+AT91C_PIOB_OER EQU (0xFFFFF610) ;- (PIOB) Output Enable Register\r
+AT91C_PIOB_PER EQU (0xFFFFF600) ;- (PIOB) PIO Enable Register\r
+// - ========== Register definition for CKGR peripheral ========== \r
+AT91C_CKGR_MOR EQU (0xFFFFFC20) ;- (CKGR) Main Oscillator Register\r
+AT91C_CKGR_PLLR EQU (0xFFFFFC2C) ;- (CKGR) PLL Register\r
+AT91C_CKGR_MCFR EQU (0xFFFFFC24) ;- (CKGR) Main Clock Frequency Register\r
+// - ========== Register definition for PMC peripheral ========== \r
+AT91C_PMC_IDR EQU (0xFFFFFC64) ;- (PMC) Interrupt Disable Register\r
+AT91C_PMC_MOR EQU (0xFFFFFC20) ;- (PMC) Main Oscillator Register\r
+AT91C_PMC_PLLR EQU (0xFFFFFC2C) ;- (PMC) PLL Register\r
+AT91C_PMC_PCER EQU (0xFFFFFC10) ;- (PMC) Peripheral Clock Enable Register\r
+AT91C_PMC_PCKR EQU (0xFFFFFC40) ;- (PMC) Programmable Clock Register\r
+AT91C_PMC_MCKR EQU (0xFFFFFC30) ;- (PMC) Master Clock Register\r
+AT91C_PMC_SCDR EQU (0xFFFFFC04) ;- (PMC) System Clock Disable Register\r
+AT91C_PMC_PCDR EQU (0xFFFFFC14) ;- (PMC) Peripheral Clock Disable Register\r
+AT91C_PMC_SCSR EQU (0xFFFFFC08) ;- (PMC) System Clock Status Register\r
+AT91C_PMC_PCSR EQU (0xFFFFFC18) ;- (PMC) Peripheral Clock Status Register\r
+AT91C_PMC_MCFR EQU (0xFFFFFC24) ;- (PMC) Main Clock Frequency Register\r
+AT91C_PMC_SCER EQU (0xFFFFFC00) ;- (PMC) System Clock Enable Register\r
+AT91C_PMC_IMR EQU (0xFFFFFC6C) ;- (PMC) Interrupt Mask Register\r
+AT91C_PMC_IER EQU (0xFFFFFC60) ;- (PMC) Interrupt Enable Register\r
+AT91C_PMC_SR EQU (0xFFFFFC68) ;- (PMC) Status Register\r
+// - ========== Register definition for RSTC peripheral ========== \r
+AT91C_RSTC_RCR EQU (0xFFFFFD00) ;- (RSTC) Reset Control Register\r
+AT91C_RSTC_RMR EQU (0xFFFFFD08) ;- (RSTC) Reset Mode Register\r
+AT91C_RSTC_RSR EQU (0xFFFFFD04) ;- (RSTC) Reset Status Register\r
+// - ========== Register definition for RTTC peripheral ========== \r
+AT91C_RTTC_RTSR EQU (0xFFFFFD2C) ;- (RTTC) Real-time Status Register\r
+AT91C_RTTC_RTMR EQU (0xFFFFFD20) ;- (RTTC) Real-time Mode Register\r
+AT91C_RTTC_RTVR EQU (0xFFFFFD28) ;- (RTTC) Real-time Value Register\r
+AT91C_RTTC_RTAR EQU (0xFFFFFD24) ;- (RTTC) Real-time Alarm Register\r
+// - ========== Register definition for PITC peripheral ========== \r
+AT91C_PITC_PIVR EQU (0xFFFFFD38) ;- (PITC) Period Interval Value Register\r
+AT91C_PITC_PISR EQU (0xFFFFFD34) ;- (PITC) Period Interval Status Register\r
+AT91C_PITC_PIIR EQU (0xFFFFFD3C) ;- (PITC) Period Interval Image Register\r
+AT91C_PITC_PIMR EQU (0xFFFFFD30) ;- (PITC) Period Interval Mode Register\r
+// - ========== Register definition for WDTC peripheral ========== \r
+AT91C_WDTC_WDCR EQU (0xFFFFFD40) ;- (WDTC) Watchdog Control Register\r
+AT91C_WDTC_WDSR EQU (0xFFFFFD48) ;- (WDTC) Watchdog Status Register\r
+AT91C_WDTC_WDMR EQU (0xFFFFFD44) ;- (WDTC) Watchdog Mode Register\r
+// - ========== Register definition for VREG peripheral ========== \r
+AT91C_VREG_MR EQU (0xFFFFFD60) ;- (VREG) Voltage Regulator Mode Register\r
+// - ========== Register definition for MC peripheral ========== \r
+AT91C_MC_ASR EQU (0xFFFFFF04) ;- (MC) MC Abort Status Register\r
+AT91C_MC_RCR EQU (0xFFFFFF00) ;- (MC) MC Remap Control Register\r
+AT91C_MC_FCR EQU (0xFFFFFF64) ;- (MC) MC Flash Command Register\r
+AT91C_MC_AASR EQU (0xFFFFFF08) ;- (MC) MC Abort Address Status Register\r
+AT91C_MC_FSR EQU (0xFFFFFF68) ;- (MC) MC Flash Status Register\r
+AT91C_MC_FMR EQU (0xFFFFFF60) ;- (MC) MC Flash Mode Register\r
+// - ========== Register definition for PDC_SPI1 peripheral ========== \r
+AT91C_SPI1_PTCR EQU (0xFFFE4120) ;- (PDC_SPI1) PDC Transfer Control Register\r
+AT91C_SPI1_RPR EQU (0xFFFE4100) ;- (PDC_SPI1) Receive Pointer Register\r
+AT91C_SPI1_TNCR EQU (0xFFFE411C) ;- (PDC_SPI1) Transmit Next Counter Register\r
+AT91C_SPI1_TPR EQU (0xFFFE4108) ;- (PDC_SPI1) Transmit Pointer Register\r
+AT91C_SPI1_TNPR EQU (0xFFFE4118) ;- (PDC_SPI1) Transmit Next Pointer Register\r
+AT91C_SPI1_TCR EQU (0xFFFE410C) ;- (PDC_SPI1) Transmit Counter Register\r
+AT91C_SPI1_RCR EQU (0xFFFE4104) ;- (PDC_SPI1) Receive Counter Register\r
+AT91C_SPI1_RNPR EQU (0xFFFE4110) ;- (PDC_SPI1) Receive Next Pointer Register\r
+AT91C_SPI1_RNCR EQU (0xFFFE4114) ;- (PDC_SPI1) Receive Next Counter Register\r
+AT91C_SPI1_PTSR EQU (0xFFFE4124) ;- (PDC_SPI1) PDC Transfer Status Register\r
+// - ========== Register definition for SPI1 peripheral ========== \r
+AT91C_SPI1_IMR EQU (0xFFFE401C) ;- (SPI1) Interrupt Mask Register\r
+AT91C_SPI1_IER EQU (0xFFFE4014) ;- (SPI1) Interrupt Enable Register\r
+AT91C_SPI1_MR EQU (0xFFFE4004) ;- (SPI1) Mode Register\r
+AT91C_SPI1_RDR EQU (0xFFFE4008) ;- (SPI1) Receive Data Register\r
+AT91C_SPI1_IDR EQU (0xFFFE4018) ;- (SPI1) Interrupt Disable Register\r
+AT91C_SPI1_SR EQU (0xFFFE4010) ;- (SPI1) Status Register\r
+AT91C_SPI1_TDR EQU (0xFFFE400C) ;- (SPI1) Transmit Data Register\r
+AT91C_SPI1_CR EQU (0xFFFE4000) ;- (SPI1) Control Register\r
+AT91C_SPI1_CSR EQU (0xFFFE4030) ;- (SPI1) Chip Select Register\r
+// - ========== Register definition for PDC_SPI0 peripheral ========== \r
+AT91C_SPI0_PTCR EQU (0xFFFE0120) ;- (PDC_SPI0) PDC Transfer Control Register\r
+AT91C_SPI0_TPR EQU (0xFFFE0108) ;- (PDC_SPI0) Transmit Pointer Register\r
+AT91C_SPI0_TCR EQU (0xFFFE010C) ;- (PDC_SPI0) Transmit Counter Register\r
+AT91C_SPI0_RCR EQU (0xFFFE0104) ;- (PDC_SPI0) Receive Counter Register\r
+AT91C_SPI0_PTSR EQU (0xFFFE0124) ;- (PDC_SPI0) PDC Transfer Status Register\r
+AT91C_SPI0_RNPR EQU (0xFFFE0110) ;- (PDC_SPI0) Receive Next Pointer Register\r
+AT91C_SPI0_RPR EQU (0xFFFE0100) ;- (PDC_SPI0) Receive Pointer Register\r
+AT91C_SPI0_TNCR EQU (0xFFFE011C) ;- (PDC_SPI0) Transmit Next Counter Register\r
+AT91C_SPI0_RNCR EQU (0xFFFE0114) ;- (PDC_SPI0) Receive Next Counter Register\r
+AT91C_SPI0_TNPR EQU (0xFFFE0118) ;- (PDC_SPI0) Transmit Next Pointer Register\r
+// - ========== Register definition for SPI0 peripheral ========== \r
+AT91C_SPI0_IER EQU (0xFFFE0014) ;- (SPI0) Interrupt Enable Register\r
+AT91C_SPI0_SR EQU (0xFFFE0010) ;- (SPI0) Status Register\r
+AT91C_SPI0_IDR EQU (0xFFFE0018) ;- (SPI0) Interrupt Disable Register\r
+AT91C_SPI0_CR EQU (0xFFFE0000) ;- (SPI0) Control Register\r
+AT91C_SPI0_MR EQU (0xFFFE0004) ;- (SPI0) Mode Register\r
+AT91C_SPI0_IMR EQU (0xFFFE001C) ;- (SPI0) Interrupt Mask Register\r
+AT91C_SPI0_TDR EQU (0xFFFE000C) ;- (SPI0) Transmit Data Register\r
+AT91C_SPI0_RDR EQU (0xFFFE0008) ;- (SPI0) Receive Data Register\r
+AT91C_SPI0_CSR EQU (0xFFFE0030) ;- (SPI0) Chip Select Register\r
+// - ========== Register definition for PDC_US1 peripheral ========== \r
+AT91C_US1_RNCR EQU (0xFFFC4114) ;- (PDC_US1) Receive Next Counter Register\r
+AT91C_US1_PTCR EQU (0xFFFC4120) ;- (PDC_US1) PDC Transfer Control Register\r
+AT91C_US1_TCR EQU (0xFFFC410C) ;- (PDC_US1) Transmit Counter Register\r
+AT91C_US1_PTSR EQU (0xFFFC4124) ;- (PDC_US1) PDC Transfer Status Register\r
+AT91C_US1_TNPR EQU (0xFFFC4118) ;- (PDC_US1) Transmit Next Pointer Register\r
+AT91C_US1_RCR EQU (0xFFFC4104) ;- (PDC_US1) Receive Counter Register\r
+AT91C_US1_RNPR EQU (0xFFFC4110) ;- (PDC_US1) Receive Next Pointer Register\r
+AT91C_US1_RPR EQU (0xFFFC4100) ;- (PDC_US1) Receive Pointer Register\r
+AT91C_US1_TNCR EQU (0xFFFC411C) ;- (PDC_US1) Transmit Next Counter Register\r
+AT91C_US1_TPR EQU (0xFFFC4108) ;- (PDC_US1) Transmit Pointer Register\r
+// - ========== Register definition for US1 peripheral ========== \r
+AT91C_US1_IF EQU (0xFFFC404C) ;- (US1) IRDA_FILTER Register\r
+AT91C_US1_NER EQU (0xFFFC4044) ;- (US1) Nb Errors Register\r
+AT91C_US1_RTOR EQU (0xFFFC4024) ;- (US1) Receiver Time-out Register\r
+AT91C_US1_CSR EQU (0xFFFC4014) ;- (US1) Channel Status Register\r
+AT91C_US1_IDR EQU (0xFFFC400C) ;- (US1) Interrupt Disable Register\r
+AT91C_US1_IER EQU (0xFFFC4008) ;- (US1) Interrupt Enable Register\r
+AT91C_US1_THR EQU (0xFFFC401C) ;- (US1) Transmitter Holding Register\r
+AT91C_US1_TTGR EQU (0xFFFC4028) ;- (US1) Transmitter Time-guard Register\r
+AT91C_US1_RHR EQU (0xFFFC4018) ;- (US1) Receiver Holding Register\r
+AT91C_US1_BRGR EQU (0xFFFC4020) ;- (US1) Baud Rate Generator Register\r
+AT91C_US1_IMR EQU (0xFFFC4010) ;- (US1) Interrupt Mask Register\r
+AT91C_US1_FIDI EQU (0xFFFC4040) ;- (US1) FI_DI_Ratio Register\r
+AT91C_US1_CR EQU (0xFFFC4000) ;- (US1) Control Register\r
+AT91C_US1_MR EQU (0xFFFC4004) ;- (US1) Mode Register\r
+// - ========== Register definition for PDC_US0 peripheral ========== \r
+AT91C_US0_TNPR EQU (0xFFFC0118) ;- (PDC_US0) Transmit Next Pointer Register\r
+AT91C_US0_RNPR EQU (0xFFFC0110) ;- (PDC_US0) Receive Next Pointer Register\r
+AT91C_US0_TCR EQU (0xFFFC010C) ;- (PDC_US0) Transmit Counter Register\r
+AT91C_US0_PTCR EQU (0xFFFC0120) ;- (PDC_US0) PDC Transfer Control Register\r
+AT91C_US0_PTSR EQU (0xFFFC0124) ;- (PDC_US0) PDC Transfer Status Register\r
+AT91C_US0_TNCR EQU (0xFFFC011C) ;- (PDC_US0) Transmit Next Counter Register\r
+AT91C_US0_TPR EQU (0xFFFC0108) ;- (PDC_US0) Transmit Pointer Register\r
+AT91C_US0_RCR EQU (0xFFFC0104) ;- (PDC_US0) Receive Counter Register\r
+AT91C_US0_RPR EQU (0xFFFC0100) ;- (PDC_US0) Receive Pointer Register\r
+AT91C_US0_RNCR EQU (0xFFFC0114) ;- (PDC_US0) Receive Next Counter Register\r
+// - ========== Register definition for US0 peripheral ========== \r
+AT91C_US0_BRGR EQU (0xFFFC0020) ;- (US0) Baud Rate Generator Register\r
+AT91C_US0_NER EQU (0xFFFC0044) ;- (US0) Nb Errors Register\r
+AT91C_US0_CR EQU (0xFFFC0000) ;- (US0) Control Register\r
+AT91C_US0_IMR EQU (0xFFFC0010) ;- (US0) Interrupt Mask Register\r
+AT91C_US0_FIDI EQU (0xFFFC0040) ;- (US0) FI_DI_Ratio Register\r
+AT91C_US0_TTGR EQU (0xFFFC0028) ;- (US0) Transmitter Time-guard Register\r
+AT91C_US0_MR EQU (0xFFFC0004) ;- (US0) Mode Register\r
+AT91C_US0_RTOR EQU (0xFFFC0024) ;- (US0) Receiver Time-out Register\r
+AT91C_US0_CSR EQU (0xFFFC0014) ;- (US0) Channel Status Register\r
+AT91C_US0_RHR EQU (0xFFFC0018) ;- (US0) Receiver Holding Register\r
+AT91C_US0_IDR EQU (0xFFFC000C) ;- (US0) Interrupt Disable Register\r
+AT91C_US0_THR EQU (0xFFFC001C) ;- (US0) Transmitter Holding Register\r
+AT91C_US0_IF EQU (0xFFFC004C) ;- (US0) IRDA_FILTER Register\r
+AT91C_US0_IER EQU (0xFFFC0008) ;- (US0) Interrupt Enable Register\r
+// - ========== Register definition for PDC_SSC peripheral ========== \r
+AT91C_SSC_TNCR EQU (0xFFFD411C) ;- (PDC_SSC) Transmit Next Counter Register\r
+AT91C_SSC_RPR EQU (0xFFFD4100) ;- (PDC_SSC) Receive Pointer Register\r
+AT91C_SSC_RNCR EQU (0xFFFD4114) ;- (PDC_SSC) Receive Next Counter Register\r
+AT91C_SSC_TPR EQU (0xFFFD4108) ;- (PDC_SSC) Transmit Pointer Register\r
+AT91C_SSC_PTCR EQU (0xFFFD4120) ;- (PDC_SSC) PDC Transfer Control Register\r
+AT91C_SSC_TCR EQU (0xFFFD410C) ;- (PDC_SSC) Transmit Counter Register\r
+AT91C_SSC_RCR EQU (0xFFFD4104) ;- (PDC_SSC) Receive Counter Register\r
+AT91C_SSC_RNPR EQU (0xFFFD4110) ;- (PDC_SSC) Receive Next Pointer Register\r
+AT91C_SSC_TNPR EQU (0xFFFD4118) ;- (PDC_SSC) Transmit Next Pointer Register\r
+AT91C_SSC_PTSR EQU (0xFFFD4124) ;- (PDC_SSC) PDC Transfer Status Register\r
+// - ========== Register definition for SSC peripheral ========== \r
+AT91C_SSC_RHR EQU (0xFFFD4020) ;- (SSC) Receive Holding Register\r
+AT91C_SSC_RSHR EQU (0xFFFD4030) ;- (SSC) Receive Sync Holding Register\r
+AT91C_SSC_TFMR EQU (0xFFFD401C) ;- (SSC) Transmit Frame Mode Register\r
+AT91C_SSC_IDR EQU (0xFFFD4048) ;- (SSC) Interrupt Disable Register\r
+AT91C_SSC_THR EQU (0xFFFD4024) ;- (SSC) Transmit Holding Register\r
+AT91C_SSC_RCMR EQU (0xFFFD4010) ;- (SSC) Receive Clock ModeRegister\r
+AT91C_SSC_IER EQU (0xFFFD4044) ;- (SSC) Interrupt Enable Register\r
+AT91C_SSC_TSHR EQU (0xFFFD4034) ;- (SSC) Transmit Sync Holding Register\r
+AT91C_SSC_SR EQU (0xFFFD4040) ;- (SSC) Status Register\r
+AT91C_SSC_CMR EQU (0xFFFD4004) ;- (SSC) Clock Mode Register\r
+AT91C_SSC_TCMR EQU (0xFFFD4018) ;- (SSC) Transmit Clock Mode Register\r
+AT91C_SSC_CR EQU (0xFFFD4000) ;- (SSC) Control Register\r
+AT91C_SSC_IMR EQU (0xFFFD404C) ;- (SSC) Interrupt Mask Register\r
+AT91C_SSC_RFMR EQU (0xFFFD4014) ;- (SSC) Receive Frame Mode Register\r
+// - ========== Register definition for TWI peripheral ========== \r
+AT91C_TWI_IER EQU (0xFFFB8024) ;- (TWI) Interrupt Enable Register\r
+AT91C_TWI_CR EQU (0xFFFB8000) ;- (TWI) Control Register\r
+AT91C_TWI_SR EQU (0xFFFB8020) ;- (TWI) Status Register\r
+AT91C_TWI_IMR EQU (0xFFFB802C) ;- (TWI) Interrupt Mask Register\r
+AT91C_TWI_THR EQU (0xFFFB8034) ;- (TWI) Transmit Holding Register\r
+AT91C_TWI_IDR EQU (0xFFFB8028) ;- (TWI) Interrupt Disable Register\r
+AT91C_TWI_IADR EQU (0xFFFB800C) ;- (TWI) Internal Address Register\r
+AT91C_TWI_MMR EQU (0xFFFB8004) ;- (TWI) Master Mode Register\r
+AT91C_TWI_CWGR EQU (0xFFFB8010) ;- (TWI) Clock Waveform Generator Register\r
+AT91C_TWI_RHR EQU (0xFFFB8030) ;- (TWI) Receive Holding Register\r
+// - ========== Register definition for PWMC_CH3 peripheral ========== \r
+AT91C_PWMC_CH3_CUPDR EQU (0xFFFCC270) ;- (PWMC_CH3) Channel Update Register\r
+AT91C_PWMC_CH3_Reserved EQU (0xFFFCC274) ;- (PWMC_CH3) Reserved\r
+AT91C_PWMC_CH3_CPRDR EQU (0xFFFCC268) ;- (PWMC_CH3) Channel Period Register\r
+AT91C_PWMC_CH3_CDTYR EQU (0xFFFCC264) ;- (PWMC_CH3) Channel Duty Cycle Register\r
+AT91C_PWMC_CH3_CCNTR EQU (0xFFFCC26C) ;- (PWMC_CH3) Channel Counter Register\r
+AT91C_PWMC_CH3_CMR EQU (0xFFFCC260) ;- (PWMC_CH3) Channel Mode Register\r
+// - ========== Register definition for PWMC_CH2 peripheral ========== \r
+AT91C_PWMC_CH2_Reserved EQU (0xFFFCC254) ;- (PWMC_CH2) Reserved\r
+AT91C_PWMC_CH2_CMR EQU (0xFFFCC240) ;- (PWMC_CH2) Channel Mode Register\r
+AT91C_PWMC_CH2_CCNTR EQU (0xFFFCC24C) ;- (PWMC_CH2) Channel Counter Register\r
+AT91C_PWMC_CH2_CPRDR EQU (0xFFFCC248) ;- (PWMC_CH2) Channel Period Register\r
+AT91C_PWMC_CH2_CUPDR EQU (0xFFFCC250) ;- (PWMC_CH2) Channel Update Register\r
+AT91C_PWMC_CH2_CDTYR EQU (0xFFFCC244) ;- (PWMC_CH2) Channel Duty Cycle Register\r
+// - ========== Register definition for PWMC_CH1 peripheral ========== \r
+AT91C_PWMC_CH1_Reserved EQU (0xFFFCC234) ;- (PWMC_CH1) Reserved\r
+AT91C_PWMC_CH1_CUPDR EQU (0xFFFCC230) ;- (PWMC_CH1) Channel Update Register\r
+AT91C_PWMC_CH1_CPRDR EQU (0xFFFCC228) ;- (PWMC_CH1) Channel Period Register\r
+AT91C_PWMC_CH1_CCNTR EQU (0xFFFCC22C) ;- (PWMC_CH1) Channel Counter Register\r
+AT91C_PWMC_CH1_CDTYR EQU (0xFFFCC224) ;- (PWMC_CH1) Channel Duty Cycle Register\r
+AT91C_PWMC_CH1_CMR EQU (0xFFFCC220) ;- (PWMC_CH1) Channel Mode Register\r
+// - ========== Register definition for PWMC_CH0 peripheral ========== \r
+AT91C_PWMC_CH0_Reserved EQU (0xFFFCC214) ;- (PWMC_CH0) Reserved\r
+AT91C_PWMC_CH0_CPRDR EQU (0xFFFCC208) ;- (PWMC_CH0) Channel Period Register\r
+AT91C_PWMC_CH0_CDTYR EQU (0xFFFCC204) ;- (PWMC_CH0) Channel Duty Cycle Register\r
+AT91C_PWMC_CH0_CMR EQU (0xFFFCC200) ;- (PWMC_CH0) Channel Mode Register\r
+AT91C_PWMC_CH0_CUPDR EQU (0xFFFCC210) ;- (PWMC_CH0) Channel Update Register\r
+AT91C_PWMC_CH0_CCNTR EQU (0xFFFCC20C) ;- (PWMC_CH0) Channel Counter Register\r
+// - ========== Register definition for PWMC peripheral ========== \r
+AT91C_PWMC_IDR EQU (0xFFFCC014) ;- (PWMC) PWMC Interrupt Disable Register\r
+AT91C_PWMC_DIS EQU (0xFFFCC008) ;- (PWMC) PWMC Disable Register\r
+AT91C_PWMC_IER EQU (0xFFFCC010) ;- (PWMC) PWMC Interrupt Enable Register\r
+AT91C_PWMC_VR EQU (0xFFFCC0FC) ;- (PWMC) PWMC Version Register\r
+AT91C_PWMC_ISR EQU (0xFFFCC01C) ;- (PWMC) PWMC Interrupt Status Register\r
+AT91C_PWMC_SR EQU (0xFFFCC00C) ;- (PWMC) PWMC Status Register\r
+AT91C_PWMC_IMR EQU (0xFFFCC018) ;- (PWMC) PWMC Interrupt Mask Register\r
+AT91C_PWMC_MR EQU (0xFFFCC000) ;- (PWMC) PWMC Mode Register\r
+AT91C_PWMC_ENA EQU (0xFFFCC004) ;- (PWMC) PWMC Enable Register\r
+// - ========== Register definition for UDP peripheral ========== \r
+AT91C_UDP_IMR EQU (0xFFFB0018) ;- (UDP) Interrupt Mask Register\r
+AT91C_UDP_FADDR EQU (0xFFFB0008) ;- (UDP) Function Address Register\r
+AT91C_UDP_NUM EQU (0xFFFB0000) ;- (UDP) Frame Number Register\r
+AT91C_UDP_FDR EQU (0xFFFB0050) ;- (UDP) Endpoint FIFO Data Register\r
+AT91C_UDP_ISR EQU (0xFFFB001C) ;- (UDP) Interrupt Status Register\r
+AT91C_UDP_CSR EQU (0xFFFB0030) ;- (UDP) Endpoint Control and Status Register\r
+AT91C_UDP_IDR EQU (0xFFFB0014) ;- (UDP) Interrupt Disable Register\r
+AT91C_UDP_ICR EQU (0xFFFB0020) ;- (UDP) Interrupt Clear Register\r
+AT91C_UDP_RSTEP EQU (0xFFFB0028) ;- (UDP) Reset Endpoint Register\r
+AT91C_UDP_TXVC EQU (0xFFFB0074) ;- (UDP) Transceiver Control Register\r
+AT91C_UDP_GLBSTATE EQU (0xFFFB0004) ;- (UDP) Global State Register\r
+AT91C_UDP_IER EQU (0xFFFB0010) ;- (UDP) Interrupt Enable Register\r
+// - ========== Register definition for TC0 peripheral ========== \r
+AT91C_TC0_SR EQU (0xFFFA0020) ;- (TC0) Status Register\r
+AT91C_TC0_RC EQU (0xFFFA001C) ;- (TC0) Register C\r
+AT91C_TC0_RB EQU (0xFFFA0018) ;- (TC0) Register B\r
+AT91C_TC0_CCR EQU (0xFFFA0000) ;- (TC0) Channel Control Register\r
+AT91C_TC0_CMR EQU (0xFFFA0004) ;- (TC0) Channel Mode Register (Capture Mode / Waveform Mode)\r
+AT91C_TC0_IER EQU (0xFFFA0024) ;- (TC0) Interrupt Enable Register\r
+AT91C_TC0_RA EQU (0xFFFA0014) ;- (TC0) Register A\r
+AT91C_TC0_IDR EQU (0xFFFA0028) ;- (TC0) Interrupt Disable Register\r
+AT91C_TC0_CV EQU (0xFFFA0010) ;- (TC0) Counter Value\r
+AT91C_TC0_IMR EQU (0xFFFA002C) ;- (TC0) Interrupt Mask Register\r
+// - ========== Register definition for TC1 peripheral ========== \r
+AT91C_TC1_RB EQU (0xFFFA0058) ;- (TC1) Register B\r
+AT91C_TC1_CCR EQU (0xFFFA0040) ;- (TC1) Channel Control Register\r
+AT91C_TC1_IER EQU (0xFFFA0064) ;- (TC1) Interrupt Enable Register\r
+AT91C_TC1_IDR EQU (0xFFFA0068) ;- (TC1) Interrupt Disable Register\r
+AT91C_TC1_SR EQU (0xFFFA0060) ;- (TC1) Status Register\r
+AT91C_TC1_CMR EQU (0xFFFA0044) ;- (TC1) Channel Mode Register (Capture Mode / Waveform Mode)\r
+AT91C_TC1_RA EQU (0xFFFA0054) ;- (TC1) Register A\r
+AT91C_TC1_RC EQU (0xFFFA005C) ;- (TC1) Register C\r
+AT91C_TC1_IMR EQU (0xFFFA006C) ;- (TC1) Interrupt Mask Register\r
+AT91C_TC1_CV EQU (0xFFFA0050) ;- (TC1) Counter Value\r
+// - ========== Register definition for TC2 peripheral ========== \r
+AT91C_TC2_CMR EQU (0xFFFA0084) ;- (TC2) Channel Mode Register (Capture Mode / Waveform Mode)\r
+AT91C_TC2_CCR EQU (0xFFFA0080) ;- (TC2) Channel Control Register\r
+AT91C_TC2_CV EQU (0xFFFA0090) ;- (TC2) Counter Value\r
+AT91C_TC2_RA EQU (0xFFFA0094) ;- (TC2) Register A\r
+AT91C_TC2_RB EQU (0xFFFA0098) ;- (TC2) Register B\r
+AT91C_TC2_IDR EQU (0xFFFA00A8) ;- (TC2) Interrupt Disable Register\r
+AT91C_TC2_IMR EQU (0xFFFA00AC) ;- (TC2) Interrupt Mask Register\r
+AT91C_TC2_RC EQU (0xFFFA009C) ;- (TC2) Register C\r
+AT91C_TC2_IER EQU (0xFFFA00A4) ;- (TC2) Interrupt Enable Register\r
+AT91C_TC2_SR EQU (0xFFFA00A0) ;- (TC2) Status Register\r
+// - ========== Register definition for TCB peripheral ========== \r
+AT91C_TCB_BMR EQU (0xFFFA00C4) ;- (TCB) TC Block Mode Register\r
+AT91C_TCB_BCR EQU (0xFFFA00C0) ;- (TCB) TC Block Control Register\r
+// - ========== Register definition for CAN_MB0 peripheral ========== \r
+AT91C_CAN_MB0_MDL EQU (0xFFFD0214) ;- (CAN_MB0) MailBox Data Low Register\r
+AT91C_CAN_MB0_MAM EQU (0xFFFD0204) ;- (CAN_MB0) MailBox Acceptance Mask Register\r
+AT91C_CAN_MB0_MCR EQU (0xFFFD021C) ;- (CAN_MB0) MailBox Control Register\r
+AT91C_CAN_MB0_MID EQU (0xFFFD0208) ;- (CAN_MB0) MailBox ID Register\r
+AT91C_CAN_MB0_MSR EQU (0xFFFD0210) ;- (CAN_MB0) MailBox Status Register\r
+AT91C_CAN_MB0_MFID EQU (0xFFFD020C) ;- (CAN_MB0) MailBox Family ID Register\r
+AT91C_CAN_MB0_MDH EQU (0xFFFD0218) ;- (CAN_MB0) MailBox Data High Register\r
+AT91C_CAN_MB0_MMR EQU (0xFFFD0200) ;- (CAN_MB0) MailBox Mode Register\r
+// - ========== Register definition for CAN_MB1 peripheral ========== \r
+AT91C_CAN_MB1_MDL EQU (0xFFFD0234) ;- (CAN_MB1) MailBox Data Low Register\r
+AT91C_CAN_MB1_MID EQU (0xFFFD0228) ;- (CAN_MB1) MailBox ID Register\r
+AT91C_CAN_MB1_MMR EQU (0xFFFD0220) ;- (CAN_MB1) MailBox Mode Register\r
+AT91C_CAN_MB1_MSR EQU (0xFFFD0230) ;- (CAN_MB1) MailBox Status Register\r
+AT91C_CAN_MB1_MAM EQU (0xFFFD0224) ;- (CAN_MB1) MailBox Acceptance Mask Register\r
+AT91C_CAN_MB1_MDH EQU (0xFFFD0238) ;- (CAN_MB1) MailBox Data High Register\r
+AT91C_CAN_MB1_MCR EQU (0xFFFD023C) ;- (CAN_MB1) MailBox Control Register\r
+AT91C_CAN_MB1_MFID EQU (0xFFFD022C) ;- (CAN_MB1) MailBox Family ID Register\r
+// - ========== Register definition for CAN_MB2 peripheral ========== \r
+AT91C_CAN_MB2_MCR EQU (0xFFFD025C) ;- (CAN_MB2) MailBox Control Register\r
+AT91C_CAN_MB2_MDH EQU (0xFFFD0258) ;- (CAN_MB2) MailBox Data High Register\r
+AT91C_CAN_MB2_MID EQU (0xFFFD0248) ;- (CAN_MB2) MailBox ID Register\r
+AT91C_CAN_MB2_MDL EQU (0xFFFD0254) ;- (CAN_MB2) MailBox Data Low Register\r
+AT91C_CAN_MB2_MMR EQU (0xFFFD0240) ;- (CAN_MB2) MailBox Mode Register\r
+AT91C_CAN_MB2_MAM EQU (0xFFFD0244) ;- (CAN_MB2) MailBox Acceptance Mask Register\r
+AT91C_CAN_MB2_MFID EQU (0xFFFD024C) ;- (CAN_MB2) MailBox Family ID Register\r
+AT91C_CAN_MB2_MSR EQU (0xFFFD0250) ;- (CAN_MB2) MailBox Status Register\r
+// - ========== Register definition for CAN_MB3 peripheral ========== \r
+AT91C_CAN_MB3_MFID EQU (0xFFFD026C) ;- (CAN_MB3) MailBox Family ID Register\r
+AT91C_CAN_MB3_MAM EQU (0xFFFD0264) ;- (CAN_MB3) MailBox Acceptance Mask Register\r
+AT91C_CAN_MB3_MID EQU (0xFFFD0268) ;- (CAN_MB3) MailBox ID Register\r
+AT91C_CAN_MB3_MCR EQU (0xFFFD027C) ;- (CAN_MB3) MailBox Control Register\r
+AT91C_CAN_MB3_MMR EQU (0xFFFD0260) ;- (CAN_MB3) MailBox Mode Register\r
+AT91C_CAN_MB3_MSR EQU (0xFFFD0270) ;- (CAN_MB3) MailBox Status Register\r
+AT91C_CAN_MB3_MDL EQU (0xFFFD0274) ;- (CAN_MB3) MailBox Data Low Register\r
+AT91C_CAN_MB3_MDH EQU (0xFFFD0278) ;- (CAN_MB3) MailBox Data High Register\r
+// - ========== Register definition for CAN_MB4 peripheral ========== \r
+AT91C_CAN_MB4_MID EQU (0xFFFD0288) ;- (CAN_MB4) MailBox ID Register\r
+AT91C_CAN_MB4_MMR EQU (0xFFFD0280) ;- (CAN_MB4) MailBox Mode Register\r
+AT91C_CAN_MB4_MDH EQU (0xFFFD0298) ;- (CAN_MB4) MailBox Data High Register\r
+AT91C_CAN_MB4_MFID EQU (0xFFFD028C) ;- (CAN_MB4) MailBox Family ID Register\r
+AT91C_CAN_MB4_MSR EQU (0xFFFD0290) ;- (CAN_MB4) MailBox Status Register\r
+AT91C_CAN_MB4_MCR EQU (0xFFFD029C) ;- (CAN_MB4) MailBox Control Register\r
+AT91C_CAN_MB4_MDL EQU (0xFFFD0294) ;- (CAN_MB4) MailBox Data Low Register\r
+AT91C_CAN_MB4_MAM EQU (0xFFFD0284) ;- (CAN_MB4) MailBox Acceptance Mask Register\r
+// - ========== Register definition for CAN_MB5 peripheral ========== \r
+AT91C_CAN_MB5_MSR EQU (0xFFFD02B0) ;- (CAN_MB5) MailBox Status Register\r
+AT91C_CAN_MB5_MCR EQU (0xFFFD02BC) ;- (CAN_MB5) MailBox Control Register\r
+AT91C_CAN_MB5_MFID EQU (0xFFFD02AC) ;- (CAN_MB5) MailBox Family ID Register\r
+AT91C_CAN_MB5_MDH EQU (0xFFFD02B8) ;- (CAN_MB5) MailBox Data High Register\r
+AT91C_CAN_MB5_MID EQU (0xFFFD02A8) ;- (CAN_MB5) MailBox ID Register\r
+AT91C_CAN_MB5_MMR EQU (0xFFFD02A0) ;- (CAN_MB5) MailBox Mode Register\r
+AT91C_CAN_MB5_MDL EQU (0xFFFD02B4) ;- (CAN_MB5) MailBox Data Low Register\r
+AT91C_CAN_MB5_MAM EQU (0xFFFD02A4) ;- (CAN_MB5) MailBox Acceptance Mask Register\r
+// - ========== Register definition for CAN_MB6 peripheral ========== \r
+AT91C_CAN_MB6_MFID EQU (0xFFFD02CC) ;- (CAN_MB6) MailBox Family ID Register\r
+AT91C_CAN_MB6_MID EQU (0xFFFD02C8) ;- (CAN_MB6) MailBox ID Register\r
+AT91C_CAN_MB6_MAM EQU (0xFFFD02C4) ;- (CAN_MB6) MailBox Acceptance Mask Register\r
+AT91C_CAN_MB6_MSR EQU (0xFFFD02D0) ;- (CAN_MB6) MailBox Status Register\r
+AT91C_CAN_MB6_MDL EQU (0xFFFD02D4) ;- (CAN_MB6) MailBox Data Low Register\r
+AT91C_CAN_MB6_MCR EQU (0xFFFD02DC) ;- (CAN_MB6) MailBox Control Register\r
+AT91C_CAN_MB6_MDH EQU (0xFFFD02D8) ;- (CAN_MB6) MailBox Data High Register\r
+AT91C_CAN_MB6_MMR EQU (0xFFFD02C0) ;- (CAN_MB6) MailBox Mode Register\r
+// - ========== Register definition for CAN_MB7 peripheral ========== \r
+AT91C_CAN_MB7_MCR EQU (0xFFFD02FC) ;- (CAN_MB7) MailBox Control Register\r
+AT91C_CAN_MB7_MDH EQU (0xFFFD02F8) ;- (CAN_MB7) MailBox Data High Register\r
+AT91C_CAN_MB7_MFID EQU (0xFFFD02EC) ;- (CAN_MB7) MailBox Family ID Register\r
+AT91C_CAN_MB7_MDL EQU (0xFFFD02F4) ;- (CAN_MB7) MailBox Data Low Register\r
+AT91C_CAN_MB7_MID EQU (0xFFFD02E8) ;- (CAN_MB7) MailBox ID Register\r
+AT91C_CAN_MB7_MMR EQU (0xFFFD02E0) ;- (CAN_MB7) MailBox Mode Register\r
+AT91C_CAN_MB7_MAM EQU (0xFFFD02E4) ;- (CAN_MB7) MailBox Acceptance Mask Register\r
+AT91C_CAN_MB7_MSR EQU (0xFFFD02F0) ;- (CAN_MB7) MailBox Status Register\r
+// - ========== Register definition for CAN peripheral ========== \r
+AT91C_CAN_TCR EQU (0xFFFD0024) ;- (CAN) Transfer Command Register\r
+AT91C_CAN_IMR EQU (0xFFFD000C) ;- (CAN) Interrupt Mask Register\r
+AT91C_CAN_IER EQU (0xFFFD0004) ;- (CAN) Interrupt Enable Register\r
+AT91C_CAN_ECR EQU (0xFFFD0020) ;- (CAN) Error Counter Register\r
+AT91C_CAN_TIMESTP EQU (0xFFFD001C) ;- (CAN) Time Stamp Register\r
+AT91C_CAN_MR EQU (0xFFFD0000) ;- (CAN) Mode Register\r
+AT91C_CAN_IDR EQU (0xFFFD0008) ;- (CAN) Interrupt Disable Register\r
+AT91C_CAN_ACR EQU (0xFFFD0028) ;- (CAN) Abort Command Register\r
+AT91C_CAN_TIM EQU (0xFFFD0018) ;- (CAN) Timer Register\r
+AT91C_CAN_SR EQU (0xFFFD0010) ;- (CAN) Status Register\r
+AT91C_CAN_BR EQU (0xFFFD0014) ;- (CAN) Baudrate Register\r
+AT91C_CAN_VR EQU (0xFFFD00FC) ;- (CAN) Version Register\r
+// - ========== Register definition for EMAC peripheral ========== \r
+AT91C_EMAC_ISR EQU (0xFFFDC024) ;- (EMAC) Interrupt Status Register\r
+AT91C_EMAC_SA4H EQU (0xFFFDC0B4) ;- (EMAC) Specific Address 4 Top, Last 2 bytes\r
+AT91C_EMAC_SA1L EQU (0xFFFDC098) ;- (EMAC) Specific Address 1 Bottom, First 4 bytes\r
+AT91C_EMAC_ELE EQU (0xFFFDC078) ;- (EMAC) Excessive Length Errors Register\r
+AT91C_EMAC_LCOL EQU (0xFFFDC05C) ;- (EMAC) Late Collision Register\r
+AT91C_EMAC_RLE EQU (0xFFFDC088) ;- (EMAC) Receive Length Field Mismatch Register\r
+AT91C_EMAC_WOL EQU (0xFFFDC0C4) ;- (EMAC) Wake On LAN Register\r
+AT91C_EMAC_DTF EQU (0xFFFDC058) ;- (EMAC) Deferred Transmission Frame Register\r
+AT91C_EMAC_TUND EQU (0xFFFDC064) ;- (EMAC) Transmit Underrun Error Register\r
+AT91C_EMAC_NCR EQU (0xFFFDC000) ;- (EMAC) Network Control Register\r
+AT91C_EMAC_SA4L EQU (0xFFFDC0B0) ;- (EMAC) Specific Address 4 Bottom, First 4 bytes\r
+AT91C_EMAC_RSR EQU (0xFFFDC020) ;- (EMAC) Receive Status Register\r
+AT91C_EMAC_SA3L EQU (0xFFFDC0A8) ;- (EMAC) Specific Address 3 Bottom, First 4 bytes\r
+AT91C_EMAC_TSR EQU (0xFFFDC014) ;- (EMAC) Transmit Status Register\r
+AT91C_EMAC_IDR EQU (0xFFFDC02C) ;- (EMAC) Interrupt Disable Register\r
+AT91C_EMAC_RSE EQU (0xFFFDC074) ;- (EMAC) Receive Symbol Errors Register\r
+AT91C_EMAC_ECOL EQU (0xFFFDC060) ;- (EMAC) Excessive Collision Register\r
+AT91C_EMAC_TID EQU (0xFFFDC0B8) ;- (EMAC) Type ID Checking Register\r
+AT91C_EMAC_HRB EQU (0xFFFDC090) ;- (EMAC) Hash Address Bottom[31:0]\r
+AT91C_EMAC_TBQP EQU (0xFFFDC01C) ;- (EMAC) Transmit Buffer Queue Pointer\r
+AT91C_EMAC_USRIO EQU (0xFFFDC0C0) ;- (EMAC) USER Input/Output Register\r
+AT91C_EMAC_PTR EQU (0xFFFDC038) ;- (EMAC) Pause Time Register\r
+AT91C_EMAC_SA2H EQU (0xFFFDC0A4) ;- (EMAC) Specific Address 2 Top, Last 2 bytes\r
+AT91C_EMAC_ROV EQU (0xFFFDC070) ;- (EMAC) Receive Overrun Errors Register\r
+AT91C_EMAC_ALE EQU (0xFFFDC054) ;- (EMAC) Alignment Error Register\r
+AT91C_EMAC_RJA EQU (0xFFFDC07C) ;- (EMAC) Receive Jabbers Register\r
+AT91C_EMAC_RBQP EQU (0xFFFDC018) ;- (EMAC) Receive Buffer Queue Pointer\r
+AT91C_EMAC_TPF EQU (0xFFFDC08C) ;- (EMAC) Transmitted Pause Frames Register\r
+AT91C_EMAC_NCFGR EQU (0xFFFDC004) ;- (EMAC) Network Configuration Register\r
+AT91C_EMAC_HRT EQU (0xFFFDC094) ;- (EMAC) Hash Address Top[63:32]\r
+AT91C_EMAC_USF EQU (0xFFFDC080) ;- (EMAC) Undersize Frames Register\r
+AT91C_EMAC_FCSE EQU (0xFFFDC050) ;- (EMAC) Frame Check Sequence Error Register\r
+AT91C_EMAC_TPQ EQU (0xFFFDC0BC) ;- (EMAC) Transmit Pause Quantum Register\r
+AT91C_EMAC_MAN EQU (0xFFFDC034) ;- (EMAC) PHY Maintenance Register\r
+AT91C_EMAC_FTO EQU (0xFFFDC040) ;- (EMAC) Frames Transmitted OK Register\r
+AT91C_EMAC_REV EQU (0xFFFDC0FC) ;- (EMAC) Revision Register\r
+AT91C_EMAC_IMR EQU (0xFFFDC030) ;- (EMAC) Interrupt Mask Register\r
+AT91C_EMAC_SCF EQU (0xFFFDC044) ;- (EMAC) Single Collision Frame Register\r
+AT91C_EMAC_PFR EQU (0xFFFDC03C) ;- (EMAC) Pause Frames received Register\r
+AT91C_EMAC_MCF EQU (0xFFFDC048) ;- (EMAC) Multiple Collision Frame Register\r
+AT91C_EMAC_NSR EQU (0xFFFDC008) ;- (EMAC) Network Status Register\r
+AT91C_EMAC_SA2L EQU (0xFFFDC0A0) ;- (EMAC) Specific Address 2 Bottom, First 4 bytes\r
+AT91C_EMAC_FRO EQU (0xFFFDC04C) ;- (EMAC) Frames Received OK Register\r
+AT91C_EMAC_IER EQU (0xFFFDC028) ;- (EMAC) Interrupt Enable Register\r
+AT91C_EMAC_SA1H EQU (0xFFFDC09C) ;- (EMAC) Specific Address 1 Top, Last 2 bytes\r
+AT91C_EMAC_CSE EQU (0xFFFDC068) ;- (EMAC) Carrier Sense Error Register\r
+AT91C_EMAC_SA3H EQU (0xFFFDC0AC) ;- (EMAC) Specific Address 3 Top, Last 2 bytes\r
+AT91C_EMAC_RRE EQU (0xFFFDC06C) ;- (EMAC) Receive Ressource Error Register\r
+AT91C_EMAC_STE EQU (0xFFFDC084) ;- (EMAC) SQE Test Error Register\r
+// - ========== Register definition for PDC_ADC peripheral ========== \r
+AT91C_ADC_PTSR EQU (0xFFFD8124) ;- (PDC_ADC) PDC Transfer Status Register\r
+AT91C_ADC_PTCR EQU (0xFFFD8120) ;- (PDC_ADC) PDC Transfer Control Register\r
+AT91C_ADC_TNPR EQU (0xFFFD8118) ;- (PDC_ADC) Transmit Next Pointer Register\r
+AT91C_ADC_TNCR EQU (0xFFFD811C) ;- (PDC_ADC) Transmit Next Counter Register\r
+AT91C_ADC_RNPR EQU (0xFFFD8110) ;- (PDC_ADC) Receive Next Pointer Register\r
+AT91C_ADC_RNCR EQU (0xFFFD8114) ;- (PDC_ADC) Receive Next Counter Register\r
+AT91C_ADC_RPR EQU (0xFFFD8100) ;- (PDC_ADC) Receive Pointer Register\r
+AT91C_ADC_TCR EQU (0xFFFD810C) ;- (PDC_ADC) Transmit Counter Register\r
+AT91C_ADC_TPR EQU (0xFFFD8108) ;- (PDC_ADC) Transmit Pointer Register\r
+AT91C_ADC_RCR EQU (0xFFFD8104) ;- (PDC_ADC) Receive Counter Register\r
+// - ========== Register definition for ADC peripheral ========== \r
+AT91C_ADC_CDR2 EQU (0xFFFD8038) ;- (ADC) ADC Channel Data Register 2\r
+AT91C_ADC_CDR3 EQU (0xFFFD803C) ;- (ADC) ADC Channel Data Register 3\r
+AT91C_ADC_CDR0 EQU (0xFFFD8030) ;- (ADC) ADC Channel Data Register 0\r
+AT91C_ADC_CDR5 EQU (0xFFFD8044) ;- (ADC) ADC Channel Data Register 5\r
+AT91C_ADC_CHDR EQU (0xFFFD8014) ;- (ADC) ADC Channel Disable Register\r
+AT91C_ADC_SR EQU (0xFFFD801C) ;- (ADC) ADC Status Register\r
+AT91C_ADC_CDR4 EQU (0xFFFD8040) ;- (ADC) ADC Channel Data Register 4\r
+AT91C_ADC_CDR1 EQU (0xFFFD8034) ;- (ADC) ADC Channel Data Register 1\r
+AT91C_ADC_LCDR EQU (0xFFFD8020) ;- (ADC) ADC Last Converted Data Register\r
+AT91C_ADC_IDR EQU (0xFFFD8028) ;- (ADC) ADC Interrupt Disable Register\r
+AT91C_ADC_CR EQU (0xFFFD8000) ;- (ADC) ADC Control Register\r
+AT91C_ADC_CDR7 EQU (0xFFFD804C) ;- (ADC) ADC Channel Data Register 7\r
+AT91C_ADC_CDR6 EQU (0xFFFD8048) ;- (ADC) ADC Channel Data Register 6\r
+AT91C_ADC_IER EQU (0xFFFD8024) ;- (ADC) ADC Interrupt Enable Register\r
+AT91C_ADC_CHER EQU (0xFFFD8010) ;- (ADC) ADC Channel Enable Register\r
+AT91C_ADC_CHSR EQU (0xFFFD8018) ;- (ADC) ADC Channel Status Register\r
+AT91C_ADC_MR EQU (0xFFFD8004) ;- (ADC) ADC Mode Register\r
+AT91C_ADC_IMR EQU (0xFFFD802C) ;- (ADC) ADC Interrupt Mask Register\r
+// - ========== Register definition for PDC_AES peripheral ========== \r
+AT91C_AES_TPR EQU (0xFFFA4108) ;- (PDC_AES) Transmit Pointer Register\r
+AT91C_AES_PTCR EQU (0xFFFA4120) ;- (PDC_AES) PDC Transfer Control Register\r
+AT91C_AES_RNPR EQU (0xFFFA4110) ;- (PDC_AES) Receive Next Pointer Register\r
+AT91C_AES_TNCR EQU (0xFFFA411C) ;- (PDC_AES) Transmit Next Counter Register\r
+AT91C_AES_TCR EQU (0xFFFA410C) ;- (PDC_AES) Transmit Counter Register\r
+AT91C_AES_RCR EQU (0xFFFA4104) ;- (PDC_AES) Receive Counter Register\r
+AT91C_AES_RNCR EQU (0xFFFA4114) ;- (PDC_AES) Receive Next Counter Register\r
+AT91C_AES_TNPR EQU (0xFFFA4118) ;- (PDC_AES) Transmit Next Pointer Register\r
+AT91C_AES_RPR EQU (0xFFFA4100) ;- (PDC_AES) Receive Pointer Register\r
+AT91C_AES_PTSR EQU (0xFFFA4124) ;- (PDC_AES) PDC Transfer Status Register\r
+// - ========== Register definition for AES peripheral ========== \r
+AT91C_AES_IVxR EQU (0xFFFA4060) ;- (AES) Initialization Vector x Register\r
+AT91C_AES_MR EQU (0xFFFA4004) ;- (AES) Mode Register\r
+AT91C_AES_VR EQU (0xFFFA40FC) ;- (AES) AES Version Register\r
+AT91C_AES_ODATAxR EQU (0xFFFA4050) ;- (AES) Output Data x Register\r
+AT91C_AES_IDATAxR EQU (0xFFFA4040) ;- (AES) Input Data x Register\r
+AT91C_AES_CR EQU (0xFFFA4000) ;- (AES) Control Register\r
+AT91C_AES_IDR EQU (0xFFFA4014) ;- (AES) Interrupt Disable Register\r
+AT91C_AES_IMR EQU (0xFFFA4018) ;- (AES) Interrupt Mask Register\r
+AT91C_AES_IER EQU (0xFFFA4010) ;- (AES) Interrupt Enable Register\r
+AT91C_AES_KEYWxR EQU (0xFFFA4020) ;- (AES) Key Word x Register\r
+AT91C_AES_ISR EQU (0xFFFA401C) ;- (AES) Interrupt Status Register\r
+// - ========== Register definition for PDC_TDES peripheral ========== \r
+AT91C_TDES_RNCR EQU (0xFFFA8114) ;- (PDC_TDES) Receive Next Counter Register\r
+AT91C_TDES_TCR EQU (0xFFFA810C) ;- (PDC_TDES) Transmit Counter Register\r
+AT91C_TDES_RCR EQU (0xFFFA8104) ;- (PDC_TDES) Receive Counter Register\r
+AT91C_TDES_TNPR EQU (0xFFFA8118) ;- (PDC_TDES) Transmit Next Pointer Register\r
+AT91C_TDES_RNPR EQU (0xFFFA8110) ;- (PDC_TDES) Receive Next Pointer Register\r
+AT91C_TDES_RPR EQU (0xFFFA8100) ;- (PDC_TDES) Receive Pointer Register\r
+AT91C_TDES_TNCR EQU (0xFFFA811C) ;- (PDC_TDES) Transmit Next Counter Register\r
+AT91C_TDES_TPR EQU (0xFFFA8108) ;- (PDC_TDES) Transmit Pointer Register\r
+AT91C_TDES_PTSR EQU (0xFFFA8124) ;- (PDC_TDES) PDC Transfer Status Register\r
+AT91C_TDES_PTCR EQU (0xFFFA8120) ;- (PDC_TDES) PDC Transfer Control Register\r
+// - ========== Register definition for TDES peripheral ========== \r
+AT91C_TDES_KEY2WxR EQU (0xFFFA8028) ;- (TDES) Key 2 Word x Register\r
+AT91C_TDES_KEY3WxR EQU (0xFFFA8030) ;- (TDES) Key 3 Word x Register\r
+AT91C_TDES_IDR EQU (0xFFFA8014) ;- (TDES) Interrupt Disable Register\r
+AT91C_TDES_VR EQU (0xFFFA80FC) ;- (TDES) TDES Version Register\r
+AT91C_TDES_IVxR EQU (0xFFFA8060) ;- (TDES) Initialization Vector x Register\r
+AT91C_TDES_ODATAxR EQU (0xFFFA8050) ;- (TDES) Output Data x Register\r
+AT91C_TDES_IMR EQU (0xFFFA8018) ;- (TDES) Interrupt Mask Register\r
+AT91C_TDES_MR EQU (0xFFFA8004) ;- (TDES) Mode Register\r
+AT91C_TDES_CR EQU (0xFFFA8000) ;- (TDES) Control Register\r
+AT91C_TDES_IER EQU (0xFFFA8010) ;- (TDES) Interrupt Enable Register\r
+AT91C_TDES_ISR EQU (0xFFFA801C) ;- (TDES) Interrupt Status Register\r
+AT91C_TDES_IDATAxR EQU (0xFFFA8040) ;- (TDES) Input Data x Register\r
+AT91C_TDES_KEY1WxR EQU (0xFFFA8020) ;- (TDES) Key 1 Word x Register\r
+\r
+// - *****************************************************************************\r
+// - PIO DEFINITIONS FOR AT91SAM7X128\r
+// - *****************************************************************************\r
+AT91C_PIO_PA0 EQU (1 << 0) ;- Pin Controlled by PA0\r
+AT91C_PA0_RXD0 EQU (AT91C_PIO_PA0) ;- USART 0 Receive Data\r
+AT91C_PIO_PA1 EQU (1 << 1) ;- Pin Controlled by PA1\r
+AT91C_PA1_TXD0 EQU (AT91C_PIO_PA1) ;- USART 0 Transmit Data\r
+AT91C_PIO_PA10 EQU (1 << 10) ;- Pin Controlled by PA10\r
+AT91C_PA10_TWD EQU (AT91C_PIO_PA10) ;- TWI Two-wire Serial Data\r
+AT91C_PIO_PA11 EQU (1 << 11) ;- Pin Controlled by PA11\r
+AT91C_PA11_TWCK EQU (AT91C_PIO_PA11) ;- TWI Two-wire Serial Clock\r
+AT91C_PIO_PA12 EQU (1 << 12) ;- Pin Controlled by PA12\r
+AT91C_PA12_NPCS00 EQU (AT91C_PIO_PA12) ;- SPI 0 Peripheral Chip Select 0\r
+AT91C_PIO_PA13 EQU (1 << 13) ;- Pin Controlled by PA13\r
+AT91C_PA13_NPCS01 EQU (AT91C_PIO_PA13) ;- SPI 0 Peripheral Chip Select 1\r
+AT91C_PA13_PCK1 EQU (AT91C_PIO_PA13) ;- PMC Programmable Clock Output 1\r
+AT91C_PIO_PA14 EQU (1 << 14) ;- Pin Controlled by PA14\r
+AT91C_PA14_NPCS02 EQU (AT91C_PIO_PA14) ;- SPI 0 Peripheral Chip Select 2\r
+AT91C_PA14_IRQ1 EQU (AT91C_PIO_PA14) ;- External Interrupt 1\r
+AT91C_PIO_PA15 EQU (1 << 15) ;- Pin Controlled by PA15\r
+AT91C_PA15_NPCS03 EQU (AT91C_PIO_PA15) ;- SPI 0 Peripheral Chip Select 3\r
+AT91C_PA15_TCLK2 EQU (AT91C_PIO_PA15) ;- Timer Counter 2 external clock input\r
+AT91C_PIO_PA16 EQU (1 << 16) ;- Pin Controlled by PA16\r
+AT91C_PA16_MISO0 EQU (AT91C_PIO_PA16) ;- SPI 0 Master In Slave\r
+AT91C_PIO_PA17 EQU (1 << 17) ;- Pin Controlled by PA17\r
+AT91C_PA17_MOSI0 EQU (AT91C_PIO_PA17) ;- SPI 0 Master Out Slave\r
+AT91C_PIO_PA18 EQU (1 << 18) ;- Pin Controlled by PA18\r
+AT91C_PA18_SPCK0 EQU (AT91C_PIO_PA18) ;- SPI 0 Serial Clock\r
+AT91C_PIO_PA19 EQU (1 << 19) ;- Pin Controlled by PA19\r
+AT91C_PA19_CANRX EQU (AT91C_PIO_PA19) ;- CAN Receive\r
+AT91C_PIO_PA2 EQU (1 << 2) ;- Pin Controlled by PA2\r
+AT91C_PA2_SCK0 EQU (AT91C_PIO_PA2) ;- USART 0 Serial Clock\r
+AT91C_PA2_NPCS11 EQU (AT91C_PIO_PA2) ;- SPI 1 Peripheral Chip Select 1\r
+AT91C_PIO_PA20 EQU (1 << 20) ;- Pin Controlled by PA20\r
+AT91C_PA20_CANTX EQU (AT91C_PIO_PA20) ;- CAN Transmit\r
+AT91C_PIO_PA21 EQU (1 << 21) ;- Pin Controlled by PA21\r
+AT91C_PA21_TF EQU (AT91C_PIO_PA21) ;- SSC Transmit Frame Sync\r
+AT91C_PA21_NPCS10 EQU (AT91C_PIO_PA21) ;- SPI 1 Peripheral Chip Select 0\r
+AT91C_PIO_PA22 EQU (1 << 22) ;- Pin Controlled by PA22\r
+AT91C_PA22_TK EQU (AT91C_PIO_PA22) ;- SSC Transmit Clock\r
+AT91C_PA22_SPCK1 EQU (AT91C_PIO_PA22) ;- SPI 1 Serial Clock\r
+AT91C_PIO_PA23 EQU (1 << 23) ;- Pin Controlled by PA23\r
+AT91C_PA23_TD EQU (AT91C_PIO_PA23) ;- SSC Transmit data\r
+AT91C_PA23_MOSI1 EQU (AT91C_PIO_PA23) ;- SPI 1 Master Out Slave\r
+AT91C_PIO_PA24 EQU (1 << 24) ;- Pin Controlled by PA24\r
+AT91C_PA24_RD EQU (AT91C_PIO_PA24) ;- SSC Receive Data\r
+AT91C_PA24_MISO1 EQU (AT91C_PIO_PA24) ;- SPI 1 Master In Slave\r
+AT91C_PIO_PA25 EQU (1 << 25) ;- Pin Controlled by PA25\r
+AT91C_PA25_RK EQU (AT91C_PIO_PA25) ;- SSC Receive Clock\r
+AT91C_PA25_NPCS11 EQU (AT91C_PIO_PA25) ;- SPI 1 Peripheral Chip Select 1\r
+AT91C_PIO_PA26 EQU (1 << 26) ;- Pin Controlled by PA26\r
+AT91C_PA26_RF EQU (AT91C_PIO_PA26) ;- SSC Receive Frame Sync\r
+AT91C_PA26_NPCS12 EQU (AT91C_PIO_PA26) ;- SPI 1 Peripheral Chip Select 2\r
+AT91C_PIO_PA27 EQU (1 << 27) ;- Pin Controlled by PA27\r
+AT91C_PA27_DRXD EQU (AT91C_PIO_PA27) ;- DBGU Debug Receive Data\r
+AT91C_PA27_PCK3 EQU (AT91C_PIO_PA27) ;- PMC Programmable Clock Output 3\r
+AT91C_PIO_PA28 EQU (1 << 28) ;- Pin Controlled by PA28\r
+AT91C_PA28_DTXD EQU (AT91C_PIO_PA28) ;- DBGU Debug Transmit Data\r
+AT91C_PIO_PA29 EQU (1 << 29) ;- Pin Controlled by PA29\r
+AT91C_PA29_FIQ EQU (AT91C_PIO_PA29) ;- AIC Fast Interrupt Input\r
+AT91C_PA29_NPCS13 EQU (AT91C_PIO_PA29) ;- SPI 1 Peripheral Chip Select 3\r
+AT91C_PIO_PA3 EQU (1 << 3) ;- Pin Controlled by PA3\r
+AT91C_PA3_RTS0 EQU (AT91C_PIO_PA3) ;- USART 0 Ready To Send\r
+AT91C_PA3_NPCS12 EQU (AT91C_PIO_PA3) ;- SPI 1 Peripheral Chip Select 2\r
+AT91C_PIO_PA30 EQU (1 << 30) ;- Pin Controlled by PA30\r
+AT91C_PA30_IRQ0 EQU (AT91C_PIO_PA30) ;- External Interrupt 0\r
+AT91C_PA30_PCK2 EQU (AT91C_PIO_PA30) ;- PMC Programmable Clock Output 2\r
+AT91C_PIO_PA4 EQU (1 << 4) ;- Pin Controlled by PA4\r
+AT91C_PA4_CTS0 EQU (AT91C_PIO_PA4) ;- USART 0 Clear To Send\r
+AT91C_PA4_NPCS13 EQU (AT91C_PIO_PA4) ;- SPI 1 Peripheral Chip Select 3\r
+AT91C_PIO_PA5 EQU (1 << 5) ;- Pin Controlled by PA5\r
+AT91C_PA5_RXD1 EQU (AT91C_PIO_PA5) ;- USART 1 Receive Data\r
+AT91C_PIO_PA6 EQU (1 << 6) ;- Pin Controlled by PA6\r
+AT91C_PA6_TXD1 EQU (AT91C_PIO_PA6) ;- USART 1 Transmit Data\r
+AT91C_PIO_PA7 EQU (1 << 7) ;- Pin Controlled by PA7\r
+AT91C_PA7_SCK1 EQU (AT91C_PIO_PA7) ;- USART 1 Serial Clock\r
+AT91C_PA7_NPCS01 EQU (AT91C_PIO_PA7) ;- SPI 0 Peripheral Chip Select 1\r
+AT91C_PIO_PA8 EQU (1 << 8) ;- Pin Controlled by PA8\r
+AT91C_PA8_RTS1 EQU (AT91C_PIO_PA8) ;- USART 1 Ready To Send\r
+AT91C_PA8_NPCS02 EQU (AT91C_PIO_PA8) ;- SPI 0 Peripheral Chip Select 2\r
+AT91C_PIO_PA9 EQU (1 << 9) ;- Pin Controlled by PA9\r
+AT91C_PA9_CTS1 EQU (AT91C_PIO_PA9) ;- USART 1 Clear To Send\r
+AT91C_PA9_NPCS03 EQU (AT91C_PIO_PA9) ;- SPI 0 Peripheral Chip Select 3\r
+AT91C_PIO_PB0 EQU (1 << 0) ;- Pin Controlled by PB0\r
+AT91C_PB0_ETXCK_EREFCK EQU (AT91C_PIO_PB0) ;- Ethernet MAC Transmit Clock/Reference Clock\r
+AT91C_PB0_PCK0 EQU (AT91C_PIO_PB0) ;- PMC Programmable Clock Output 0\r
+AT91C_PIO_PB1 EQU (1 << 1) ;- Pin Controlled by PB1\r
+AT91C_PB1_ETXEN EQU (AT91C_PIO_PB1) ;- Ethernet MAC Transmit Enable\r
+AT91C_PIO_PB10 EQU (1 << 10) ;- Pin Controlled by PB10\r
+AT91C_PB10_ETX2 EQU (AT91C_PIO_PB10) ;- Ethernet MAC Transmit Data 2\r
+AT91C_PB10_NPCS11 EQU (AT91C_PIO_PB10) ;- SPI 1 Peripheral Chip Select 1\r
+AT91C_PIO_PB11 EQU (1 << 11) ;- Pin Controlled by PB11\r
+AT91C_PB11_ETX3 EQU (AT91C_PIO_PB11) ;- Ethernet MAC Transmit Data 3\r
+AT91C_PB11_NPCS12 EQU (AT91C_PIO_PB11) ;- SPI 1 Peripheral Chip Select 2\r
+AT91C_PIO_PB12 EQU (1 << 12) ;- Pin Controlled by PB12\r
+AT91C_PB12_ETXER EQU (AT91C_PIO_PB12) ;- Ethernet MAC Transmikt Coding Error\r
+AT91C_PB12_TCLK0 EQU (AT91C_PIO_PB12) ;- Timer Counter 0 external clock input\r
+AT91C_PIO_PB13 EQU (1 << 13) ;- Pin Controlled by PB13\r
+AT91C_PB13_ERX2 EQU (AT91C_PIO_PB13) ;- Ethernet MAC Receive Data 2\r
+AT91C_PB13_NPCS01 EQU (AT91C_PIO_PB13) ;- SPI 0 Peripheral Chip Select 1\r
+AT91C_PIO_PB14 EQU (1 << 14) ;- Pin Controlled by PB14\r
+AT91C_PB14_ERX3 EQU (AT91C_PIO_PB14) ;- Ethernet MAC Receive Data 3\r
+AT91C_PB14_NPCS02 EQU (AT91C_PIO_PB14) ;- SPI 0 Peripheral Chip Select 2\r
+AT91C_PIO_PB15 EQU (1 << 15) ;- Pin Controlled by PB15\r
+AT91C_PB15_ERXDV EQU (AT91C_PIO_PB15) ;- Ethernet MAC Receive Data Valid\r
+AT91C_PIO_PB16 EQU (1 << 16) ;- Pin Controlled by PB16\r
+AT91C_PB16_ECOL EQU (AT91C_PIO_PB16) ;- Ethernet MAC Collision Detected\r
+AT91C_PB16_NPCS13 EQU (AT91C_PIO_PB16) ;- SPI 1 Peripheral Chip Select 3\r
+AT91C_PIO_PB17 EQU (1 << 17) ;- Pin Controlled by PB17\r
+AT91C_PB17_ERXCK EQU (AT91C_PIO_PB17) ;- Ethernet MAC Receive Clock\r
+AT91C_PB17_NPCS03 EQU (AT91C_PIO_PB17) ;- SPI 0 Peripheral Chip Select 3\r
+AT91C_PIO_PB18 EQU (1 << 18) ;- Pin Controlled by PB18\r
+AT91C_PB18_EF100 EQU (AT91C_PIO_PB18) ;- Ethernet MAC Force 100 Mbits/sec\r
+AT91C_PB18_ADTRG EQU (AT91C_PIO_PB18) ;- ADC External Trigger\r
+AT91C_PIO_PB19 EQU (1 << 19) ;- Pin Controlled by PB19\r
+AT91C_PB19_PWM0 EQU (AT91C_PIO_PB19) ;- PWM Channel 0\r
+AT91C_PB19_TCLK1 EQU (AT91C_PIO_PB19) ;- Timer Counter 1 external clock input\r
+AT91C_PIO_PB2 EQU (1 << 2) ;- Pin Controlled by PB2\r
+AT91C_PB2_ETX0 EQU (AT91C_PIO_PB2) ;- Ethernet MAC Transmit Data 0\r
+AT91C_PIO_PB20 EQU (1 << 20) ;- Pin Controlled by PB20\r
+AT91C_PB20_PWM1 EQU (AT91C_PIO_PB20) ;- PWM Channel 1\r
+AT91C_PB20_PCK0 EQU (AT91C_PIO_PB20) ;- PMC Programmable Clock Output 0\r
+AT91C_PIO_PB21 EQU (1 << 21) ;- Pin Controlled by PB21\r
+AT91C_PB21_PWM2 EQU (AT91C_PIO_PB21) ;- PWM Channel 2\r
+AT91C_PB21_PCK1 EQU (AT91C_PIO_PB21) ;- PMC Programmable Clock Output 1\r
+AT91C_PIO_PB22 EQU (1 << 22) ;- Pin Controlled by PB22\r
+AT91C_PB22_PWM3 EQU (AT91C_PIO_PB22) ;- PWM Channel 3\r
+AT91C_PB22_PCK2 EQU (AT91C_PIO_PB22) ;- PMC Programmable Clock Output 2\r
+AT91C_PIO_PB23 EQU (1 << 23) ;- Pin Controlled by PB23\r
+AT91C_PB23_TIOA0 EQU (AT91C_PIO_PB23) ;- Timer Counter 0 Multipurpose Timer I/O Pin A\r
+AT91C_PB23_DCD1 EQU (AT91C_PIO_PB23) ;- USART 1 Data Carrier Detect\r
+AT91C_PIO_PB24 EQU (1 << 24) ;- Pin Controlled by PB24\r
+AT91C_PB24_TIOB0 EQU (AT91C_PIO_PB24) ;- Timer Counter 0 Multipurpose Timer I/O Pin B\r
+AT91C_PB24_DSR1 EQU (AT91C_PIO_PB24) ;- USART 1 Data Set ready\r
+AT91C_PIO_PB25 EQU (1 << 25) ;- Pin Controlled by PB25\r
+AT91C_PB25_TIOA1 EQU (AT91C_PIO_PB25) ;- Timer Counter 1 Multipurpose Timer I/O Pin A\r
+AT91C_PB25_DTR1 EQU (AT91C_PIO_PB25) ;- USART 1 Data Terminal ready\r
+AT91C_PIO_PB26 EQU (1 << 26) ;- Pin Controlled by PB26\r
+AT91C_PB26_TIOB1 EQU (AT91C_PIO_PB26) ;- Timer Counter 1 Multipurpose Timer I/O Pin B\r
+AT91C_PB26_RI1 EQU (AT91C_PIO_PB26) ;- USART 1 Ring Indicator\r
+AT91C_PIO_PB27 EQU (1 << 27) ;- Pin Controlled by PB27\r
+AT91C_PB27_TIOA2 EQU (AT91C_PIO_PB27) ;- Timer Counter 2 Multipurpose Timer I/O Pin A\r
+AT91C_PB27_PWM0 EQU (AT91C_PIO_PB27) ;- PWM Channel 0\r
+AT91C_PIO_PB28 EQU (1 << 28) ;- Pin Controlled by PB28\r
+AT91C_PB28_TIOB2 EQU (AT91C_PIO_PB28) ;- Timer Counter 2 Multipurpose Timer I/O Pin B\r
+AT91C_PB28_PWM1 EQU (AT91C_PIO_PB28) ;- PWM Channel 1\r
+AT91C_PIO_PB29 EQU (1 << 29) ;- Pin Controlled by PB29\r
+AT91C_PB29_PCK1 EQU (AT91C_PIO_PB29) ;- PMC Programmable Clock Output 1\r
+AT91C_PB29_PWM2 EQU (AT91C_PIO_PB29) ;- PWM Channel 2\r
+AT91C_PIO_PB3 EQU (1 << 3) ;- Pin Controlled by PB3\r
+AT91C_PB3_ETX1 EQU (AT91C_PIO_PB3) ;- Ethernet MAC Transmit Data 1\r
+AT91C_PIO_PB30 EQU (1 << 30) ;- Pin Controlled by PB30\r
+AT91C_PB30_PCK2 EQU (AT91C_PIO_PB30) ;- PMC Programmable Clock Output 2\r
+AT91C_PB30_PWM3 EQU (AT91C_PIO_PB30) ;- PWM Channel 3\r
+AT91C_PIO_PB4 EQU (1 << 4) ;- Pin Controlled by PB4\r
+AT91C_PB4_ECRS_ECRSDV EQU (AT91C_PIO_PB4) ;- Ethernet MAC Carrier Sense/Carrier Sense and Data Valid\r
+AT91C_PIO_PB5 EQU (1 << 5) ;- Pin Controlled by PB5\r
+AT91C_PB5_ERX0 EQU (AT91C_PIO_PB5) ;- Ethernet MAC Receive Data 0\r
+AT91C_PIO_PB6 EQU (1 << 6) ;- Pin Controlled by PB6\r
+AT91C_PB6_ERX1 EQU (AT91C_PIO_PB6) ;- Ethernet MAC Receive Data 1\r
+AT91C_PIO_PB7 EQU (1 << 7) ;- Pin Controlled by PB7\r
+AT91C_PB7_ERXER EQU (AT91C_PIO_PB7) ;- Ethernet MAC Receive Error\r
+AT91C_PIO_PB8 EQU (1 << 8) ;- Pin Controlled by PB8\r
+AT91C_PB8_EMDC EQU (AT91C_PIO_PB8) ;- Ethernet MAC Management Data Clock\r
+AT91C_PIO_PB9 EQU (1 << 9) ;- Pin Controlled by PB9\r
+AT91C_PB9_EMDIO EQU (AT91C_PIO_PB9) ;- Ethernet MAC Management Data Input/Output\r
+\r
+// - *****************************************************************************\r
+// - PERIPHERAL ID DEFINITIONS FOR AT91SAM7X128\r
+// - *****************************************************************************\r
+AT91C_ID_FIQ EQU ( 0) ;- Advanced Interrupt Controller (FIQ)\r
+AT91C_ID_SYS EQU ( 1) ;- System Peripheral\r
+AT91C_ID_PIOA EQU ( 2) ;- Parallel IO Controller A\r
+AT91C_ID_PIOB EQU ( 3) ;- Parallel IO Controller B\r
+AT91C_ID_SPI0 EQU ( 4) ;- Serial Peripheral Interface 0\r
+AT91C_ID_SPI1 EQU ( 5) ;- Serial Peripheral Interface 1\r
+AT91C_ID_US0 EQU ( 6) ;- USART 0\r
+AT91C_ID_US1 EQU ( 7) ;- USART 1\r
+AT91C_ID_SSC EQU ( 8) ;- Serial Synchronous Controller\r
+AT91C_ID_TWI EQU ( 9) ;- Two-Wire Interface\r
+AT91C_ID_PWMC EQU (10) ;- PWM Controller\r
+AT91C_ID_UDP EQU (11) ;- USB Device Port\r
+AT91C_ID_TC0 EQU (12) ;- Timer Counter 0\r
+AT91C_ID_TC1 EQU (13) ;- Timer Counter 1\r
+AT91C_ID_TC2 EQU (14) ;- Timer Counter 2\r
+AT91C_ID_CAN EQU (15) ;- Control Area Network Controller\r
+AT91C_ID_EMAC EQU (16) ;- Ethernet MAC\r
+AT91C_ID_ADC EQU (17) ;- Analog-to-Digital Converter\r
+AT91C_ID_AES EQU (18) ;- Advanced Encryption Standard 128-bit\r
+AT91C_ID_TDES EQU (19) ;- Triple Data Encryption Standard\r
+AT91C_ID_20_Reserved EQU (20) ;- Reserved\r
+AT91C_ID_21_Reserved EQU (21) ;- Reserved\r
+AT91C_ID_22_Reserved EQU (22) ;- Reserved\r
+AT91C_ID_23_Reserved EQU (23) ;- Reserved\r
+AT91C_ID_24_Reserved EQU (24) ;- Reserved\r
+AT91C_ID_25_Reserved EQU (25) ;- Reserved\r
+AT91C_ID_26_Reserved EQU (26) ;- Reserved\r
+AT91C_ID_27_Reserved EQU (27) ;- Reserved\r
+AT91C_ID_28_Reserved EQU (28) ;- Reserved\r
+AT91C_ID_29_Reserved EQU (29) ;- Reserved\r
+AT91C_ID_IRQ0 EQU (30) ;- Advanced Interrupt Controller (IRQ0)\r
+AT91C_ID_IRQ1 EQU (31) ;- Advanced Interrupt Controller (IRQ1)\r
+\r
+// - *****************************************************************************\r
+// - BASE ADDRESS DEFINITIONS FOR AT91SAM7X128\r
+// - *****************************************************************************\r
+AT91C_BASE_SYS EQU (0xFFFFF000) ;- (SYS) Base Address\r
+AT91C_BASE_AIC EQU (0xFFFFF000) ;- (AIC) Base Address\r
+AT91C_BASE_PDC_DBGU EQU (0xFFFFF300) ;- (PDC_DBGU) Base Address\r
+AT91C_BASE_DBGU EQU (0xFFFFF200) ;- (DBGU) Base Address\r
+AT91C_BASE_PIOA EQU (0xFFFFF400) ;- (PIOA) Base Address\r
+AT91C_BASE_PIOB EQU (0xFFFFF600) ;- (PIOB) Base Address\r
+AT91C_BASE_CKGR EQU (0xFFFFFC20) ;- (CKGR) Base Address\r
+AT91C_BASE_PMC EQU (0xFFFFFC00) ;- (PMC) Base Address\r
+AT91C_BASE_RSTC EQU (0xFFFFFD00) ;- (RSTC) Base Address\r
+AT91C_BASE_RTTC EQU (0xFFFFFD20) ;- (RTTC) Base Address\r
+AT91C_BASE_PITC EQU (0xFFFFFD30) ;- (PITC) Base Address\r
+AT91C_BASE_WDTC EQU (0xFFFFFD40) ;- (WDTC) Base Address\r
+AT91C_BASE_VREG EQU (0xFFFFFD60) ;- (VREG) Base Address\r
+AT91C_BASE_MC EQU (0xFFFFFF00) ;- (MC) Base Address\r
+AT91C_BASE_PDC_SPI1 EQU (0xFFFE4100) ;- (PDC_SPI1) Base Address\r
+AT91C_BASE_SPI1 EQU (0xFFFE4000) ;- (SPI1) Base Address\r
+AT91C_BASE_PDC_SPI0 EQU (0xFFFE0100) ;- (PDC_SPI0) Base Address\r
+AT91C_BASE_SPI0 EQU (0xFFFE0000) ;- (SPI0) Base Address\r
+AT91C_BASE_PDC_US1 EQU (0xFFFC4100) ;- (PDC_US1) Base Address\r
+AT91C_BASE_US1 EQU (0xFFFC4000) ;- (US1) Base Address\r
+AT91C_BASE_PDC_US0 EQU (0xFFFC0100) ;- (PDC_US0) Base Address\r
+AT91C_BASE_US0 EQU (0xFFFC0000) ;- (US0) Base Address\r
+AT91C_BASE_PDC_SSC EQU (0xFFFD4100) ;- (PDC_SSC) Base Address\r
+AT91C_BASE_SSC EQU (0xFFFD4000) ;- (SSC) Base Address\r
+AT91C_BASE_TWI EQU (0xFFFB8000) ;- (TWI) Base Address\r
+AT91C_BASE_PWMC_CH3 EQU (0xFFFCC260) ;- (PWMC_CH3) Base Address\r
+AT91C_BASE_PWMC_CH2 EQU (0xFFFCC240) ;- (PWMC_CH2) Base Address\r
+AT91C_BASE_PWMC_CH1 EQU (0xFFFCC220) ;- (PWMC_CH1) Base Address\r
+AT91C_BASE_PWMC_CH0 EQU (0xFFFCC200) ;- (PWMC_CH0) Base Address\r
+AT91C_BASE_PWMC EQU (0xFFFCC000) ;- (PWMC) Base Address\r
+AT91C_BASE_UDP EQU (0xFFFB0000) ;- (UDP) Base Address\r
+AT91C_BASE_TC0 EQU (0xFFFA0000) ;- (TC0) Base Address\r
+AT91C_BASE_TC1 EQU (0xFFFA0040) ;- (TC1) Base Address\r
+AT91C_BASE_TC2 EQU (0xFFFA0080) ;- (TC2) Base Address\r
+AT91C_BASE_TCB EQU (0xFFFA0000) ;- (TCB) Base Address\r
+AT91C_BASE_CAN_MB0 EQU (0xFFFD0200) ;- (CAN_MB0) Base Address\r
+AT91C_BASE_CAN_MB1 EQU (0xFFFD0220) ;- (CAN_MB1) Base Address\r
+AT91C_BASE_CAN_MB2 EQU (0xFFFD0240) ;- (CAN_MB2) Base Address\r
+AT91C_BASE_CAN_MB3 EQU (0xFFFD0260) ;- (CAN_MB3) Base Address\r
+AT91C_BASE_CAN_MB4 EQU (0xFFFD0280) ;- (CAN_MB4) Base Address\r
+AT91C_BASE_CAN_MB5 EQU (0xFFFD02A0) ;- (CAN_MB5) Base Address\r
+AT91C_BASE_CAN_MB6 EQU (0xFFFD02C0) ;- (CAN_MB6) Base Address\r
+AT91C_BASE_CAN_MB7 EQU (0xFFFD02E0) ;- (CAN_MB7) Base Address\r
+AT91C_BASE_CAN EQU (0xFFFD0000) ;- (CAN) Base Address\r
+AT91C_BASE_EMAC EQU (0xFFFDC000) ;- (EMAC) Base Address\r
+AT91C_BASE_PDC_ADC EQU (0xFFFD8100) ;- (PDC_ADC) Base Address\r
+AT91C_BASE_ADC EQU (0xFFFD8000) ;- (ADC) Base Address\r
+AT91C_BASE_PDC_AES EQU (0xFFFA4100) ;- (PDC_AES) Base Address\r
+AT91C_BASE_AES EQU (0xFFFA4000) ;- (AES) Base Address\r
+AT91C_BASE_PDC_TDES EQU (0xFFFA8100) ;- (PDC_TDES) Base Address\r
+AT91C_BASE_TDES EQU (0xFFFA8000) ;- (TDES) Base Address\r
+\r
+// - *****************************************************************************\r
+// - MEMORY MAPPING DEFINITIONS FOR AT91SAM7X128\r
+// - *****************************************************************************\r
+AT91C_ISRAM EQU (0x00200000) ;- Internal SRAM base address\r
+AT91C_ISRAM_SIZE EQU (0x00008000) ;- Internal SRAM size in byte (32 Kbyte)\r
+AT91C_IFLASH EQU (0x00100000) ;- Internal ROM base address\r
+AT91C_IFLASH_SIZE EQU (0x00020000) ;- Internal ROM size in byte (128 Kbyte)\r
+#endif /* __IAR_SYSTEMS_ASM__ */\r
+\r
+\r
+#endif /* AT91SAM7X128_H */\r
--- /dev/null
+// - ----------------------------------------------------------------------------\r
+// - ATMEL Microcontroller Software Support - ROUSSET -\r
+// - ----------------------------------------------------------------------------\r
+// - DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+// - IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+// - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+// - DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+// - INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+// - LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+// - OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+// - LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+// - NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+// - EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+// - ----------------------------------------------------------------------------\r
+// - File Name : AT91SAM7X256.h\r
+// - Object : AT91SAM7X256 definitions\r
+// - Generated : AT91 SW Application Group 05/20/2005 (16:22:29)\r
+// - \r
+// - CVS Reference : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005//\r
+// - CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005//\r
+// - CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//\r
+// - CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005//\r
+// - CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005//\r
+// - CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//\r
+// - CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//\r
+// - CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//\r
+// - CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005//\r
+// - CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004//\r
+// - CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004//\r
+// - CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004//\r
+// - CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005//\r
+// - CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005//\r
+// - CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//\r
+// - CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//\r
+// - CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//\r
+// - CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//\r
+// - CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//\r
+// - CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//\r
+// - CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005//\r
+// - CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005//\r
+// - CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//\r
+// - CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005//\r
+// - CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005//\r
+// - ----------------------------------------------------------------------------\r
+\r
+#ifndef AT91SAM7X256_H\r
+#define AT91SAM7X256_H\r
+\r
+#ifdef __IAR_SYSTEMS_ICC__\r
+\r
+typedef volatile unsigned int AT91_REG;// Hardware register definition\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR System Peripherals\r
+// *****************************************************************************\r
+typedef struct _AT91S_SYS {\r
+ AT91_REG AIC_SMR[32]; // Source Mode Register\r
+ AT91_REG AIC_SVR[32]; // Source Vector Register\r
+ AT91_REG AIC_IVR; // IRQ Vector Register\r
+ AT91_REG AIC_FVR; // FIQ Vector Register\r
+ AT91_REG AIC_ISR; // Interrupt Status Register\r
+ AT91_REG AIC_IPR; // Interrupt Pending Register\r
+ AT91_REG AIC_IMR; // Interrupt Mask Register\r
+ AT91_REG AIC_CISR; // Core Interrupt Status Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG AIC_IECR; // Interrupt Enable Command Register\r
+ AT91_REG AIC_IDCR; // Interrupt Disable Command Register\r
+ AT91_REG AIC_ICCR; // Interrupt Clear Command Register\r
+ AT91_REG AIC_ISCR; // Interrupt Set Command Register\r
+ AT91_REG AIC_EOICR; // End of Interrupt Command Register\r
+ AT91_REG AIC_SPU; // Spurious Vector Register\r
+ AT91_REG AIC_DCR; // Debug Control Register (Protect)\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG AIC_FFER; // Fast Forcing Enable Register\r
+ AT91_REG AIC_FFDR; // Fast Forcing Disable Register\r
+ AT91_REG AIC_FFSR; // Fast Forcing Status Register\r
+ AT91_REG Reserved2[45]; // \r
+ AT91_REG DBGU_CR; // Control Register\r
+ AT91_REG DBGU_MR; // Mode Register\r
+ AT91_REG DBGU_IER; // Interrupt Enable Register\r
+ AT91_REG DBGU_IDR; // Interrupt Disable Register\r
+ AT91_REG DBGU_IMR; // Interrupt Mask Register\r
+ AT91_REG DBGU_CSR; // Channel Status Register\r
+ AT91_REG DBGU_RHR; // Receiver Holding Register\r
+ AT91_REG DBGU_THR; // Transmitter Holding Register\r
+ AT91_REG DBGU_BRGR; // Baud Rate Generator Register\r
+ AT91_REG Reserved3[7]; // \r
+ AT91_REG DBGU_CIDR; // Chip ID Register\r
+ AT91_REG DBGU_EXID; // Chip ID Extension Register\r
+ AT91_REG DBGU_FNTR; // Force NTRST Register\r
+ AT91_REG Reserved4[45]; // \r
+ AT91_REG DBGU_RPR; // Receive Pointer Register\r
+ AT91_REG DBGU_RCR; // Receive Counter Register\r
+ AT91_REG DBGU_TPR; // Transmit Pointer Register\r
+ AT91_REG DBGU_TCR; // Transmit Counter Register\r
+ AT91_REG DBGU_RNPR; // Receive Next Pointer Register\r
+ AT91_REG DBGU_RNCR; // Receive Next Counter Register\r
+ AT91_REG DBGU_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG DBGU_TNCR; // Transmit Next Counter Register\r
+ AT91_REG DBGU_PTCR; // PDC Transfer Control Register\r
+ AT91_REG DBGU_PTSR; // PDC Transfer Status Register\r
+ AT91_REG Reserved5[54]; // \r
+ AT91_REG PIOA_PER; // PIO Enable Register\r
+ AT91_REG PIOA_PDR; // PIO Disable Register\r
+ AT91_REG PIOA_PSR; // PIO Status Register\r
+ AT91_REG Reserved6[1]; // \r
+ AT91_REG PIOA_OER; // Output Enable Register\r
+ AT91_REG PIOA_ODR; // Output Disable Registerr\r
+ AT91_REG PIOA_OSR; // Output Status Register\r
+ AT91_REG Reserved7[1]; // \r
+ AT91_REG PIOA_IFER; // Input Filter Enable Register\r
+ AT91_REG PIOA_IFDR; // Input Filter Disable Register\r
+ AT91_REG PIOA_IFSR; // Input Filter Status Register\r
+ AT91_REG Reserved8[1]; // \r
+ AT91_REG PIOA_SODR; // Set Output Data Register\r
+ AT91_REG PIOA_CODR; // Clear Output Data Register\r
+ AT91_REG PIOA_ODSR; // Output Data Status Register\r
+ AT91_REG PIOA_PDSR; // Pin Data Status Register\r
+ AT91_REG PIOA_IER; // Interrupt Enable Register\r
+ AT91_REG PIOA_IDR; // Interrupt Disable Register\r
+ AT91_REG PIOA_IMR; // Interrupt Mask Register\r
+ AT91_REG PIOA_ISR; // Interrupt Status Register\r
+ AT91_REG PIOA_MDER; // Multi-driver Enable Register\r
+ AT91_REG PIOA_MDDR; // Multi-driver Disable Register\r
+ AT91_REG PIOA_MDSR; // Multi-driver Status Register\r
+ AT91_REG Reserved9[1]; // \r
+ AT91_REG PIOA_PPUDR; // Pull-up Disable Register\r
+ AT91_REG PIOA_PPUER; // Pull-up Enable Register\r
+ AT91_REG PIOA_PPUSR; // Pull-up Status Register\r
+ AT91_REG Reserved10[1]; // \r
+ AT91_REG PIOA_ASR; // Select A Register\r
+ AT91_REG PIOA_BSR; // Select B Register\r
+ AT91_REG PIOA_ABSR; // AB Select Status Register\r
+ AT91_REG Reserved11[9]; // \r
+ AT91_REG PIOA_OWER; // Output Write Enable Register\r
+ AT91_REG PIOA_OWDR; // Output Write Disable Register\r
+ AT91_REG PIOA_OWSR; // Output Write Status Register\r
+ AT91_REG Reserved12[85]; // \r
+ AT91_REG PIOB_PER; // PIO Enable Register\r
+ AT91_REG PIOB_PDR; // PIO Disable Register\r
+ AT91_REG PIOB_PSR; // PIO Status Register\r
+ AT91_REG Reserved13[1]; // \r
+ AT91_REG PIOB_OER; // Output Enable Register\r
+ AT91_REG PIOB_ODR; // Output Disable Registerr\r
+ AT91_REG PIOB_OSR; // Output Status Register\r
+ AT91_REG Reserved14[1]; // \r
+ AT91_REG PIOB_IFER; // Input Filter Enable Register\r
+ AT91_REG PIOB_IFDR; // Input Filter Disable Register\r
+ AT91_REG PIOB_IFSR; // Input Filter Status Register\r
+ AT91_REG Reserved15[1]; // \r
+ AT91_REG PIOB_SODR; // Set Output Data Register\r
+ AT91_REG PIOB_CODR; // Clear Output Data Register\r
+ AT91_REG PIOB_ODSR; // Output Data Status Register\r
+ AT91_REG PIOB_PDSR; // Pin Data Status Register\r
+ AT91_REG PIOB_IER; // Interrupt Enable Register\r
+ AT91_REG PIOB_IDR; // Interrupt Disable Register\r
+ AT91_REG PIOB_IMR; // Interrupt Mask Register\r
+ AT91_REG PIOB_ISR; // Interrupt Status Register\r
+ AT91_REG PIOB_MDER; // Multi-driver Enable Register\r
+ AT91_REG PIOB_MDDR; // Multi-driver Disable Register\r
+ AT91_REG PIOB_MDSR; // Multi-driver Status Register\r
+ AT91_REG Reserved16[1]; // \r
+ AT91_REG PIOB_PPUDR; // Pull-up Disable Register\r
+ AT91_REG PIOB_PPUER; // Pull-up Enable Register\r
+ AT91_REG PIOB_PPUSR; // Pull-up Status Register\r
+ AT91_REG Reserved17[1]; // \r
+ AT91_REG PIOB_ASR; // Select A Register\r
+ AT91_REG PIOB_BSR; // Select B Register\r
+ AT91_REG PIOB_ABSR; // AB Select Status Register\r
+ AT91_REG Reserved18[9]; // \r
+ AT91_REG PIOB_OWER; // Output Write Enable Register\r
+ AT91_REG PIOB_OWDR; // Output Write Disable Register\r
+ AT91_REG PIOB_OWSR; // Output Write Status Register\r
+ AT91_REG Reserved19[341]; // \r
+ AT91_REG PMC_SCER; // System Clock Enable Register\r
+ AT91_REG PMC_SCDR; // System Clock Disable Register\r
+ AT91_REG PMC_SCSR; // System Clock Status Register\r
+ AT91_REG Reserved20[1]; // \r
+ AT91_REG PMC_PCER; // Peripheral Clock Enable Register\r
+ AT91_REG PMC_PCDR; // Peripheral Clock Disable Register\r
+ AT91_REG PMC_PCSR; // Peripheral Clock Status Register\r
+ AT91_REG Reserved21[1]; // \r
+ AT91_REG PMC_MOR; // Main Oscillator Register\r
+ AT91_REG PMC_MCFR; // Main Clock Frequency Register\r
+ AT91_REG Reserved22[1]; // \r
+ AT91_REG PMC_PLLR; // PLL Register\r
+ AT91_REG PMC_MCKR; // Master Clock Register\r
+ AT91_REG Reserved23[3]; // \r
+ AT91_REG PMC_PCKR[4]; // Programmable Clock Register\r
+ AT91_REG Reserved24[4]; // \r
+ AT91_REG PMC_IER; // Interrupt Enable Register\r
+ AT91_REG PMC_IDR; // Interrupt Disable Register\r
+ AT91_REG PMC_SR; // Status Register\r
+ AT91_REG PMC_IMR; // Interrupt Mask Register\r
+ AT91_REG Reserved25[36]; // \r
+ AT91_REG RSTC_RCR; // Reset Control Register\r
+ AT91_REG RSTC_RSR; // Reset Status Register\r
+ AT91_REG RSTC_RMR; // Reset Mode Register\r
+ AT91_REG Reserved26[5]; // \r
+ AT91_REG RTTC_RTMR; // Real-time Mode Register\r
+ AT91_REG RTTC_RTAR; // Real-time Alarm Register\r
+ AT91_REG RTTC_RTVR; // Real-time Value Register\r
+ AT91_REG RTTC_RTSR; // Real-time Status Register\r
+ AT91_REG PITC_PIMR; // Period Interval Mode Register\r
+ AT91_REG PITC_PISR; // Period Interval Status Register\r
+ AT91_REG PITC_PIVR; // Period Interval Value Register\r
+ AT91_REG PITC_PIIR; // Period Interval Image Register\r
+ AT91_REG WDTC_WDCR; // Watchdog Control Register\r
+ AT91_REG WDTC_WDMR; // Watchdog Mode Register\r
+ AT91_REG WDTC_WDSR; // Watchdog Status Register\r
+ AT91_REG Reserved27[5]; // \r
+ AT91_REG VREG_MR; // Voltage Regulator Mode Register\r
+} AT91S_SYS, *AT91PS_SYS;\r
+\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller\r
+// *****************************************************************************\r
+typedef struct _AT91S_AIC {\r
+ AT91_REG AIC_SMR[32]; // Source Mode Register\r
+ AT91_REG AIC_SVR[32]; // Source Vector Register\r
+ AT91_REG AIC_IVR; // IRQ Vector Register\r
+ AT91_REG AIC_FVR; // FIQ Vector Register\r
+ AT91_REG AIC_ISR; // Interrupt Status Register\r
+ AT91_REG AIC_IPR; // Interrupt Pending Register\r
+ AT91_REG AIC_IMR; // Interrupt Mask Register\r
+ AT91_REG AIC_CISR; // Core Interrupt Status Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG AIC_IECR; // Interrupt Enable Command Register\r
+ AT91_REG AIC_IDCR; // Interrupt Disable Command Register\r
+ AT91_REG AIC_ICCR; // Interrupt Clear Command Register\r
+ AT91_REG AIC_ISCR; // Interrupt Set Command Register\r
+ AT91_REG AIC_EOICR; // End of Interrupt Command Register\r
+ AT91_REG AIC_SPU; // Spurious Vector Register\r
+ AT91_REG AIC_DCR; // Debug Control Register (Protect)\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG AIC_FFER; // Fast Forcing Enable Register\r
+ AT91_REG AIC_FFDR; // Fast Forcing Disable Register\r
+ AT91_REG AIC_FFSR; // Fast Forcing Status Register\r
+} AT91S_AIC, *AT91PS_AIC;\r
+\r
+// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- \r
+#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level\r
+#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level\r
+#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level\r
+#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type\r
+#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive\r
+#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ((unsigned int) 0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive\r
+#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered\r
+#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered\r
+#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive\r
+#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered\r
+// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- \r
+#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status\r
+#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status\r
+// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- \r
+#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode\r
+#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Peripheral DMA Controller\r
+// *****************************************************************************\r
+typedef struct _AT91S_PDC {\r
+ AT91_REG PDC_RPR; // Receive Pointer Register\r
+ AT91_REG PDC_RCR; // Receive Counter Register\r
+ AT91_REG PDC_TPR; // Transmit Pointer Register\r
+ AT91_REG PDC_TCR; // Transmit Counter Register\r
+ AT91_REG PDC_RNPR; // Receive Next Pointer Register\r
+ AT91_REG PDC_RNCR; // Receive Next Counter Register\r
+ AT91_REG PDC_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG PDC_TNCR; // Transmit Next Counter Register\r
+ AT91_REG PDC_PTCR; // PDC Transfer Control Register\r
+ AT91_REG PDC_PTSR; // PDC Transfer Status Register\r
+} AT91S_PDC, *AT91PS_PDC;\r
+\r
+// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- \r
+#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable\r
+#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable\r
+#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable\r
+#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable\r
+// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Debug Unit\r
+// *****************************************************************************\r
+typedef struct _AT91S_DBGU {\r
+ AT91_REG DBGU_CR; // Control Register\r
+ AT91_REG DBGU_MR; // Mode Register\r
+ AT91_REG DBGU_IER; // Interrupt Enable Register\r
+ AT91_REG DBGU_IDR; // Interrupt Disable Register\r
+ AT91_REG DBGU_IMR; // Interrupt Mask Register\r
+ AT91_REG DBGU_CSR; // Channel Status Register\r
+ AT91_REG DBGU_RHR; // Receiver Holding Register\r
+ AT91_REG DBGU_THR; // Transmitter Holding Register\r
+ AT91_REG DBGU_BRGR; // Baud Rate Generator Register\r
+ AT91_REG Reserved0[7]; // \r
+ AT91_REG DBGU_CIDR; // Chip ID Register\r
+ AT91_REG DBGU_EXID; // Chip ID Extension Register\r
+ AT91_REG DBGU_FNTR; // Force NTRST Register\r
+ AT91_REG Reserved1[45]; // \r
+ AT91_REG DBGU_RPR; // Receive Pointer Register\r
+ AT91_REG DBGU_RCR; // Receive Counter Register\r
+ AT91_REG DBGU_TPR; // Transmit Pointer Register\r
+ AT91_REG DBGU_TCR; // Transmit Counter Register\r
+ AT91_REG DBGU_RNPR; // Receive Next Pointer Register\r
+ AT91_REG DBGU_RNCR; // Receive Next Counter Register\r
+ AT91_REG DBGU_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG DBGU_TNCR; // Transmit Next Counter Register\r
+ AT91_REG DBGU_PTCR; // PDC Transfer Control Register\r
+ AT91_REG DBGU_PTSR; // PDC Transfer Status Register\r
+} AT91S_DBGU, *AT91PS_DBGU;\r
+\r
+// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- \r
+#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver\r
+#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter\r
+#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable\r
+#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable\r
+#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable\r
+#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable\r
+#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits\r
+// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- \r
+#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type\r
+#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity\r
+#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity\r
+#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space)\r
+#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark)\r
+#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity\r
+#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode\r
+#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode\r
+#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.\r
+#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.\r
+#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.\r
+#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.\r
+// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- \r
+#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt\r
+#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt\r
+#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt\r
+#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt\r
+#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt\r
+#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt\r
+#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt\r
+#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt\r
+#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt\r
+#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt\r
+#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt\r
+#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt\r
+// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- \r
+// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- \r
+// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- \r
+// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- \r
+#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Parallel Input Output Controler\r
+// *****************************************************************************\r
+typedef struct _AT91S_PIO {\r
+ AT91_REG PIO_PER; // PIO Enable Register\r
+ AT91_REG PIO_PDR; // PIO Disable Register\r
+ AT91_REG PIO_PSR; // PIO Status Register\r
+ AT91_REG Reserved0[1]; // \r
+ AT91_REG PIO_OER; // Output Enable Register\r
+ AT91_REG PIO_ODR; // Output Disable Registerr\r
+ AT91_REG PIO_OSR; // Output Status Register\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG PIO_IFER; // Input Filter Enable Register\r
+ AT91_REG PIO_IFDR; // Input Filter Disable Register\r
+ AT91_REG PIO_IFSR; // Input Filter Status Register\r
+ AT91_REG Reserved2[1]; // \r
+ AT91_REG PIO_SODR; // Set Output Data Register\r
+ AT91_REG PIO_CODR; // Clear Output Data Register\r
+ AT91_REG PIO_ODSR; // Output Data Status Register\r
+ AT91_REG PIO_PDSR; // Pin Data Status Register\r
+ AT91_REG PIO_IER; // Interrupt Enable Register\r
+ AT91_REG PIO_IDR; // Interrupt Disable Register\r
+ AT91_REG PIO_IMR; // Interrupt Mask Register\r
+ AT91_REG PIO_ISR; // Interrupt Status Register\r
+ AT91_REG PIO_MDER; // Multi-driver Enable Register\r
+ AT91_REG PIO_MDDR; // Multi-driver Disable Register\r
+ AT91_REG PIO_MDSR; // Multi-driver Status Register\r
+ AT91_REG Reserved3[1]; // \r
+ AT91_REG PIO_PPUDR; // Pull-up Disable Register\r
+ AT91_REG PIO_PPUER; // Pull-up Enable Register\r
+ AT91_REG PIO_PPUSR; // Pull-up Status Register\r
+ AT91_REG Reserved4[1]; // \r
+ AT91_REG PIO_ASR; // Select A Register\r
+ AT91_REG PIO_BSR; // Select B Register\r
+ AT91_REG PIO_ABSR; // AB Select Status Register\r
+ AT91_REG Reserved5[9]; // \r
+ AT91_REG PIO_OWER; // Output Write Enable Register\r
+ AT91_REG PIO_OWDR; // Output Write Disable Register\r
+ AT91_REG PIO_OWSR; // Output Write Status Register\r
+} AT91S_PIO, *AT91PS_PIO;\r
+\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Clock Generator Controler\r
+// *****************************************************************************\r
+typedef struct _AT91S_CKGR {\r
+ AT91_REG CKGR_MOR; // Main Oscillator Register\r
+ AT91_REG CKGR_MCFR; // Main Clock Frequency Register\r
+ AT91_REG Reserved0[1]; // \r
+ AT91_REG CKGR_PLLR; // PLL Register\r
+} AT91S_CKGR, *AT91PS_CKGR;\r
+\r
+// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- \r
+#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable\r
+#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass\r
+#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time\r
+// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- \r
+#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency\r
+#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready\r
+// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- \r
+#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected\r
+#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0\r
+#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed\r
+#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter\r
+#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range\r
+#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet\r
+#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet\r
+#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet\r
+#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet\r
+#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier\r
+#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks\r
+#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output\r
+#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2\r
+#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Power Management Controler\r
+// *****************************************************************************\r
+typedef struct _AT91S_PMC {\r
+ AT91_REG PMC_SCER; // System Clock Enable Register\r
+ AT91_REG PMC_SCDR; // System Clock Disable Register\r
+ AT91_REG PMC_SCSR; // System Clock Status Register\r
+ AT91_REG Reserved0[1]; // \r
+ AT91_REG PMC_PCER; // Peripheral Clock Enable Register\r
+ AT91_REG PMC_PCDR; // Peripheral Clock Disable Register\r
+ AT91_REG PMC_PCSR; // Peripheral Clock Status Register\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG PMC_MOR; // Main Oscillator Register\r
+ AT91_REG PMC_MCFR; // Main Clock Frequency Register\r
+ AT91_REG Reserved2[1]; // \r
+ AT91_REG PMC_PLLR; // PLL Register\r
+ AT91_REG PMC_MCKR; // Master Clock Register\r
+ AT91_REG Reserved3[3]; // \r
+ AT91_REG PMC_PCKR[4]; // Programmable Clock Register\r
+ AT91_REG Reserved4[4]; // \r
+ AT91_REG PMC_IER; // Interrupt Enable Register\r
+ AT91_REG PMC_IDR; // Interrupt Disable Register\r
+ AT91_REG PMC_SR; // Status Register\r
+ AT91_REG PMC_IMR; // Interrupt Mask Register\r
+} AT91S_PMC, *AT91PS_PMC;\r
+\r
+// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- \r
+#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock\r
+#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock\r
+#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output\r
+#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output\r
+#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output\r
+#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output\r
+// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- \r
+// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- \r
+// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- \r
+// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- \r
+// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- \r
+// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- \r
+#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection\r
+#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected\r
+#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected\r
+#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected\r
+#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler\r
+#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock\r
+#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2\r
+#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4\r
+#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8\r
+#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16\r
+#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32\r
+#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64\r
+// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- \r
+// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- \r
+#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask\r
+#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask\r
+#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask\r
+// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- \r
+// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- \r
+// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Reset Controller Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_RSTC {\r
+ AT91_REG RSTC_RCR; // Reset Control Register\r
+ AT91_REG RSTC_RSR; // Reset Status Register\r
+ AT91_REG RSTC_RMR; // Reset Mode Register\r
+} AT91S_RSTC, *AT91PS_RSTC;\r
+\r
+// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- \r
+#define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset\r
+#define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset\r
+#define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset\r
+#define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password\r
+// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- \r
+#define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status\r
+#define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status\r
+#define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type\r
+#define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising.\r
+#define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising.\r
+#define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.\r
+#define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.\r
+#define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low.\r
+#define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured.\r
+#define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level\r
+#define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress.\r
+// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- \r
+#define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable\r
+#define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable\r
+#define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable\r
+#define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_RTTC {\r
+ AT91_REG RTTC_RTMR; // Real-time Mode Register\r
+ AT91_REG RTTC_RTAR; // Real-time Alarm Register\r
+ AT91_REG RTTC_RTVR; // Real-time Value Register\r
+ AT91_REG RTTC_RTSR; // Real-time Status Register\r
+} AT91S_RTTC, *AT91PS_RTTC;\r
+\r
+// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- \r
+#define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value\r
+#define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable\r
+#define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable\r
+#define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart\r
+// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- \r
+#define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value\r
+// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- \r
+#define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value\r
+// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- \r
+#define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status\r
+#define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_PITC {\r
+ AT91_REG PITC_PIMR; // Period Interval Mode Register\r
+ AT91_REG PITC_PISR; // Period Interval Status Register\r
+ AT91_REG PITC_PIVR; // Period Interval Value Register\r
+ AT91_REG PITC_PIIR; // Period Interval Image Register\r
+} AT91S_PITC, *AT91PS_PITC;\r
+\r
+// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- \r
+#define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value\r
+#define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled\r
+#define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable\r
+// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- \r
+#define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status\r
+// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- \r
+#define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value\r
+#define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter\r
+// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_WDTC {\r
+ AT91_REG WDTC_WDCR; // Watchdog Control Register\r
+ AT91_REG WDTC_WDMR; // Watchdog Mode Register\r
+ AT91_REG WDTC_WDSR; // Watchdog Status Register\r
+} AT91S_WDTC, *AT91PS_WDTC;\r
+\r
+// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- \r
+#define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart\r
+#define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password\r
+// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- \r
+#define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart\r
+#define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable\r
+#define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable\r
+#define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart\r
+#define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable\r
+#define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value\r
+#define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt\r
+#define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt\r
+// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- \r
+#define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow\r
+#define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_VREG {\r
+ AT91_REG VREG_MR; // Voltage Regulator Mode Register\r
+} AT91S_VREG, *AT91PS_VREG;\r
+\r
+// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- \r
+#define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Memory Controller Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_MC {\r
+ AT91_REG MC_RCR; // MC Remap Control Register\r
+ AT91_REG MC_ASR; // MC Abort Status Register\r
+ AT91_REG MC_AASR; // MC Abort Address Status Register\r
+ AT91_REG Reserved0[21]; // \r
+ AT91_REG MC_FMR; // MC Flash Mode Register\r
+ AT91_REG MC_FCR; // MC Flash Command Register\r
+ AT91_REG MC_FSR; // MC Flash Status Register\r
+} AT91S_MC, *AT91PS_MC;\r
+\r
+// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- \r
+#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit\r
+// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- \r
+#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status\r
+#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status\r
+#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status\r
+#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte\r
+#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word\r
+#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word\r
+#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status\r
+#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read\r
+#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write\r
+#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch\r
+#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source\r
+#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source\r
+#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source\r
+#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source\r
+// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- \r
+#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready\r
+#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error\r
+#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error\r
+#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming\r
+#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State\r
+#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations\r
+#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations\r
+#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations\r
+#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations\r
+#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number\r
+// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- \r
+#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command\r
+#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN.\r
+#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.\r
+#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.\r
+#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.\r
+#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.\r
+#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits.\r
+#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits.\r
+#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit.\r
+#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number\r
+#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key\r
+// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- \r
+#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status\r
+#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status\r
+#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status\r
+#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status\r
+#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status\r
+#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status\r
+#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status\r
+#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status\r
+#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status\r
+#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status\r
+#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status\r
+#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status\r
+#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status\r
+#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status\r
+#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status\r
+#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status\r
+#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status\r
+#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status\r
+#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status\r
+#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status\r
+#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status\r
+#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status\r
+#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status\r
+#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status\r
+#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Serial Parallel Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_SPI {\r
+ AT91_REG SPI_CR; // Control Register\r
+ AT91_REG SPI_MR; // Mode Register\r
+ AT91_REG SPI_RDR; // Receive Data Register\r
+ AT91_REG SPI_TDR; // Transmit Data Register\r
+ AT91_REG SPI_SR; // Status Register\r
+ AT91_REG SPI_IER; // Interrupt Enable Register\r
+ AT91_REG SPI_IDR; // Interrupt Disable Register\r
+ AT91_REG SPI_IMR; // Interrupt Mask Register\r
+ AT91_REG Reserved0[4]; // \r
+ AT91_REG SPI_CSR[4]; // Chip Select Register\r
+ AT91_REG Reserved1[48]; // \r
+ AT91_REG SPI_RPR; // Receive Pointer Register\r
+ AT91_REG SPI_RCR; // Receive Counter Register\r
+ AT91_REG SPI_TPR; // Transmit Pointer Register\r
+ AT91_REG SPI_TCR; // Transmit Counter Register\r
+ AT91_REG SPI_RNPR; // Receive Next Pointer Register\r
+ AT91_REG SPI_RNCR; // Receive Next Counter Register\r
+ AT91_REG SPI_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG SPI_TNCR; // Transmit Next Counter Register\r
+ AT91_REG SPI_PTCR; // PDC Transfer Control Register\r
+ AT91_REG SPI_PTSR; // PDC Transfer Status Register\r
+} AT91S_SPI, *AT91PS_SPI;\r
+\r
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- \r
+#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable\r
+#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable\r
+#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset\r
+#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer\r
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- \r
+#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode\r
+#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select\r
+#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select\r
+#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select\r
+#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode\r
+#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection\r
+#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection\r
+#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection\r
+#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select\r
+#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects\r
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- \r
+#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data\r
+#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status\r
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- \r
+#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data\r
+#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status\r
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- \r
+#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full\r
+#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty\r
+#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error\r
+#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status\r
+#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer\r
+#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer\r
+#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt\r
+#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt\r
+#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt\r
+#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt\r
+#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status\r
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- \r
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- \r
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- \r
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- \r
+#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity\r
+#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase\r
+#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer\r
+#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer\r
+#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer\r
+#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer\r
+#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer\r
+#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer\r
+#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer\r
+#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer\r
+#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer\r
+#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer\r
+#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer\r
+#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate\r
+#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK\r
+#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Usart\r
+// *****************************************************************************\r
+typedef struct _AT91S_USART {\r
+ AT91_REG US_CR; // Control Register\r
+ AT91_REG US_MR; // Mode Register\r
+ AT91_REG US_IER; // Interrupt Enable Register\r
+ AT91_REG US_IDR; // Interrupt Disable Register\r
+ AT91_REG US_IMR; // Interrupt Mask Register\r
+ AT91_REG US_CSR; // Channel Status Register\r
+ AT91_REG US_RHR; // Receiver Holding Register\r
+ AT91_REG US_THR; // Transmitter Holding Register\r
+ AT91_REG US_BRGR; // Baud Rate Generator Register\r
+ AT91_REG US_RTOR; // Receiver Time-out Register\r
+ AT91_REG US_TTGR; // Transmitter Time-guard Register\r
+ AT91_REG Reserved0[5]; // \r
+ AT91_REG US_FIDI; // FI_DI_Ratio Register\r
+ AT91_REG US_NER; // Nb Errors Register\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG US_IF; // IRDA_FILTER Register\r
+ AT91_REG Reserved2[44]; // \r
+ AT91_REG US_RPR; // Receive Pointer Register\r
+ AT91_REG US_RCR; // Receive Counter Register\r
+ AT91_REG US_TPR; // Transmit Pointer Register\r
+ AT91_REG US_TCR; // Transmit Counter Register\r
+ AT91_REG US_RNPR; // Receive Next Pointer Register\r
+ AT91_REG US_RNCR; // Receive Next Counter Register\r
+ AT91_REG US_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG US_TNCR; // Transmit Next Counter Register\r
+ AT91_REG US_PTCR; // PDC Transfer Control Register\r
+ AT91_REG US_PTSR; // PDC Transfer Status Register\r
+} AT91S_USART, *AT91PS_USART;\r
+\r
+// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- \r
+#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break\r
+#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break\r
+#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out\r
+#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address\r
+#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations\r
+#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge\r
+#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out\r
+#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable\r
+#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable\r
+#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable\r
+#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable\r
+// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- \r
+#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode\r
+#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal\r
+#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485\r
+#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking\r
+#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem\r
+#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0\r
+#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1\r
+#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA\r
+#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking\r
+#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock\r
+#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock\r
+#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1\r
+#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM)\r
+#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK)\r
+#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock\r
+#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits\r
+#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits\r
+#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits\r
+#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits\r
+#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select\r
+#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits\r
+#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit\r
+#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits\r
+#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits\r
+#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order\r
+#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length\r
+#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select\r
+#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode\r
+#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge\r
+#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK\r
+#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions\r
+#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter\r
+// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- \r
+#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break\r
+#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out\r
+#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached\r
+#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge\r
+#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag\r
+#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag\r
+#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag\r
+#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag\r
+// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- \r
+// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- \r
+// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- \r
+#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input\r
+#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input\r
+#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input\r
+#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_SSC {\r
+ AT91_REG SSC_CR; // Control Register\r
+ AT91_REG SSC_CMR; // Clock Mode Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG SSC_RCMR; // Receive Clock ModeRegister\r
+ AT91_REG SSC_RFMR; // Receive Frame Mode Register\r
+ AT91_REG SSC_TCMR; // Transmit Clock Mode Register\r
+ AT91_REG SSC_TFMR; // Transmit Frame Mode Register\r
+ AT91_REG SSC_RHR; // Receive Holding Register\r
+ AT91_REG SSC_THR; // Transmit Holding Register\r
+ AT91_REG Reserved1[2]; // \r
+ AT91_REG SSC_RSHR; // Receive Sync Holding Register\r
+ AT91_REG SSC_TSHR; // Transmit Sync Holding Register\r
+ AT91_REG Reserved2[2]; // \r
+ AT91_REG SSC_SR; // Status Register\r
+ AT91_REG SSC_IER; // Interrupt Enable Register\r
+ AT91_REG SSC_IDR; // Interrupt Disable Register\r
+ AT91_REG SSC_IMR; // Interrupt Mask Register\r
+ AT91_REG Reserved3[44]; // \r
+ AT91_REG SSC_RPR; // Receive Pointer Register\r
+ AT91_REG SSC_RCR; // Receive Counter Register\r
+ AT91_REG SSC_TPR; // Transmit Pointer Register\r
+ AT91_REG SSC_TCR; // Transmit Counter Register\r
+ AT91_REG SSC_RNPR; // Receive Next Pointer Register\r
+ AT91_REG SSC_RNCR; // Receive Next Counter Register\r
+ AT91_REG SSC_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG SSC_TNCR; // Transmit Next Counter Register\r
+ AT91_REG SSC_PTCR; // PDC Transfer Control Register\r
+ AT91_REG SSC_PTSR; // PDC Transfer Status Register\r
+} AT91S_SSC, *AT91PS_SSC;\r
+\r
+// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- \r
+#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable\r
+#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable\r
+#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable\r
+#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable\r
+#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset\r
+// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- \r
+#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection\r
+#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock\r
+#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal\r
+#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin\r
+#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection\r
+#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only\r
+#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output\r
+#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output\r
+#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion\r
+#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection\r
+#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.\r
+#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start\r
+#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input\r
+#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input\r
+#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input\r
+#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input\r
+#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input\r
+#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input\r
+#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0\r
+#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay\r
+#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection\r
+// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- \r
+#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length\r
+#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode\r
+#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First\r
+#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame\r
+#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length\r
+#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection\r
+#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only\r
+#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse\r
+#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse\r
+#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer\r
+#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer\r
+#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer\r
+#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection\r
+// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- \r
+// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- \r
+#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value\r
+#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable\r
+// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- \r
+#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready\r
+#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty\r
+#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission\r
+#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty\r
+#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready\r
+#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun\r
+#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception\r
+#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full\r
+#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync\r
+#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync\r
+#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable\r
+#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable\r
+// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- \r
+// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- \r
+// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Two-wire Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_TWI {\r
+ AT91_REG TWI_CR; // Control Register\r
+ AT91_REG TWI_MMR; // Master Mode Register\r
+ AT91_REG Reserved0[1]; // \r
+ AT91_REG TWI_IADR; // Internal Address Register\r
+ AT91_REG TWI_CWGR; // Clock Waveform Generator Register\r
+ AT91_REG Reserved1[3]; // \r
+ AT91_REG TWI_SR; // Status Register\r
+ AT91_REG TWI_IER; // Interrupt Enable Register\r
+ AT91_REG TWI_IDR; // Interrupt Disable Register\r
+ AT91_REG TWI_IMR; // Interrupt Mask Register\r
+ AT91_REG TWI_RHR; // Receive Holding Register\r
+ AT91_REG TWI_THR; // Transmit Holding Register\r
+} AT91S_TWI, *AT91PS_TWI;\r
+\r
+// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- \r
+#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition\r
+#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition\r
+#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled\r
+#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled\r
+#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset\r
+// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- \r
+#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size\r
+#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address\r
+#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address\r
+#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address\r
+#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address\r
+#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction\r
+#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address\r
+// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- \r
+#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider\r
+#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider\r
+#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider\r
+// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- \r
+#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed\r
+#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY\r
+#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY\r
+#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error\r
+#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error\r
+#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged\r
+// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- \r
+// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- \r
+// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR PWMC Channel Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_PWMC_CH {\r
+ AT91_REG PWMC_CMR; // Channel Mode Register\r
+ AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register\r
+ AT91_REG PWMC_CPRDR; // Channel Period Register\r
+ AT91_REG PWMC_CCNTR; // Channel Counter Register\r
+ AT91_REG PWMC_CUPDR; // Channel Update Register\r
+ AT91_REG PWMC_Reserved[3]; // Reserved\r
+} AT91S_PWMC_CH, *AT91PS_PWMC_CH;\r
+\r
+// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- \r
+#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx\r
+#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH) \r
+#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH) \r
+#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH) \r
+#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment\r
+#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity\r
+#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period\r
+// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- \r
+#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle\r
+// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- \r
+#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period\r
+// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- \r
+#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter\r
+// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- \r
+#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_PWMC {\r
+ AT91_REG PWMC_MR; // PWMC Mode Register\r
+ AT91_REG PWMC_ENA; // PWMC Enable Register\r
+ AT91_REG PWMC_DIS; // PWMC Disable Register\r
+ AT91_REG PWMC_SR; // PWMC Status Register\r
+ AT91_REG PWMC_IER; // PWMC Interrupt Enable Register\r
+ AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register\r
+ AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register\r
+ AT91_REG PWMC_ISR; // PWMC Interrupt Status Register\r
+ AT91_REG Reserved0[55]; // \r
+ AT91_REG PWMC_VR; // PWMC Version Register\r
+ AT91_REG Reserved1[64]; // \r
+ AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel\r
+} AT91S_PWMC, *AT91PS_PWMC;\r
+\r
+// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- \r
+#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor.\r
+#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A\r
+#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC) \r
+#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor.\r
+#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B\r
+#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC) \r
+// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- \r
+#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0\r
+#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1\r
+#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2\r
+#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3\r
+// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- \r
+// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- \r
+// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- \r
+// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- \r
+// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- \r
+// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR USB Device Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_UDP {\r
+ AT91_REG UDP_NUM; // Frame Number Register\r
+ AT91_REG UDP_GLBSTATE; // Global State Register\r
+ AT91_REG UDP_FADDR; // Function Address Register\r
+ AT91_REG Reserved0[1]; // \r
+ AT91_REG UDP_IER; // Interrupt Enable Register\r
+ AT91_REG UDP_IDR; // Interrupt Disable Register\r
+ AT91_REG UDP_IMR; // Interrupt Mask Register\r
+ AT91_REG UDP_ISR; // Interrupt Status Register\r
+ AT91_REG UDP_ICR; // Interrupt Clear Register\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG UDP_RSTEP; // Reset Endpoint Register\r
+ AT91_REG Reserved2[1]; // \r
+ AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register\r
+ AT91_REG Reserved3[2]; // \r
+ AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register\r
+ AT91_REG Reserved4[3]; // \r
+ AT91_REG UDP_TXVC; // Transceiver Control Register\r
+} AT91S_UDP, *AT91PS_UDP;\r
+\r
+// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- \r
+#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats\r
+#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error\r
+#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK\r
+// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- \r
+#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable\r
+#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured\r
+#define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume\r
+#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host\r
+#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable\r
+// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- \r
+#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value\r
+#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable\r
+// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- \r
+#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt\r
+#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt\r
+#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt\r
+#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt\r
+#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt\r
+#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt\r
+#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt\r
+#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt\r
+#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt\r
+#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt\r
+#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt\r
+// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- \r
+// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- \r
+// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- \r
+#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt\r
+// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- \r
+// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- \r
+#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0\r
+#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1\r
+#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2\r
+#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3\r
+#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4\r
+#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5\r
+// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- \r
+#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR\r
+#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0\r
+#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)\r
+#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)\r
+#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready\r
+#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).\r
+#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).\r
+#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction\r
+#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type\r
+#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control\r
+#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT\r
+#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT\r
+#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT\r
+#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN\r
+#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN\r
+#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN\r
+#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle\r
+#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable\r
+#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO\r
+// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- \r
+#define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP) \r
+#define AT91C_UDP_PUON ((unsigned int) 0x1 << 9) // (UDP) Pull-up ON\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_TC {\r
+ AT91_REG TC_CCR; // Channel Control Register\r
+ AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode)\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG TC_CV; // Counter Value\r
+ AT91_REG TC_RA; // Register A\r
+ AT91_REG TC_RB; // Register B\r
+ AT91_REG TC_RC; // Register C\r
+ AT91_REG TC_SR; // Status Register\r
+ AT91_REG TC_IER; // Interrupt Enable Register\r
+ AT91_REG TC_IDR; // Interrupt Disable Register\r
+ AT91_REG TC_IMR; // Interrupt Mask Register\r
+} AT91S_TC, *AT91PS_TC;\r
+\r
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- \r
+#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command\r
+#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command\r
+#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command\r
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- \r
+#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection\r
+#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK\r
+#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK\r
+#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK\r
+#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK\r
+#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK\r
+#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0\r
+#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1\r
+#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2\r
+#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert\r
+#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection\r
+#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal\r
+#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock\r
+#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock\r
+#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock\r
+#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare\r
+#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading\r
+#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare\r
+#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading\r
+#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection\r
+#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None\r
+#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge\r
+#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge\r
+#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge\r
+#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection\r
+#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None\r
+#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge\r
+#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge\r
+#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge\r
+#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection\r
+#define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input\r
+#define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output\r
+#define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output\r
+#define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output\r
+#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection\r
+#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable\r
+#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection\r
+#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare\r
+#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare\r
+#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare\r
+#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare\r
+#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable\r
+#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) \r
+#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA\r
+#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none\r
+#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set\r
+#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear\r
+#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle\r
+#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection\r
+#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None\r
+#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA\r
+#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA\r
+#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA\r
+#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA\r
+#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none\r
+#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set\r
+#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear\r
+#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle\r
+#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection\r
+#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None\r
+#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA\r
+#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA\r
+#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA\r
+#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA\r
+#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none\r
+#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set\r
+#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear\r
+#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle\r
+#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA\r
+#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none\r
+#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set\r
+#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear\r
+#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle\r
+#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB\r
+#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none\r
+#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set\r
+#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear\r
+#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle\r
+#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB\r
+#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none\r
+#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set\r
+#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear\r
+#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle\r
+#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB\r
+#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none\r
+#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set\r
+#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear\r
+#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle\r
+#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB\r
+#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none\r
+#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set\r
+#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear\r
+#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle\r
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- \r
+#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow\r
+#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun\r
+#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare\r
+#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare\r
+#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare\r
+#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading\r
+#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading\r
+#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger\r
+#define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling\r
+#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror\r
+#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror\r
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- \r
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- \r
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Timer Counter Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_TCB {\r
+ AT91S_TC TCB_TC0; // TC Channel 0\r
+ AT91_REG Reserved0[4]; // \r
+ AT91S_TC TCB_TC1; // TC Channel 1\r
+ AT91_REG Reserved1[4]; // \r
+ AT91S_TC TCB_TC2; // TC Channel 2\r
+ AT91_REG Reserved2[4]; // \r
+ AT91_REG TCB_BCR; // TC Block Control Register\r
+ AT91_REG TCB_BMR; // TC Block Mode Register\r
+} AT91S_TCB, *AT91PS_TCB;\r
+\r
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- \r
+#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command\r
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- \r
+#define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection\r
+#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0\r
+#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0\r
+#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0\r
+#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0\r
+#define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection\r
+#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1\r
+#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1\r
+#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1\r
+#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1\r
+#define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection\r
+#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2\r
+#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2\r
+#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2\r
+#define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_CAN_MB {\r
+ AT91_REG CAN_MB_MMR; // MailBox Mode Register\r
+ AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register\r
+ AT91_REG CAN_MB_MID; // MailBox ID Register\r
+ AT91_REG CAN_MB_MFID; // MailBox Family ID Register\r
+ AT91_REG CAN_MB_MSR; // MailBox Status Register\r
+ AT91_REG CAN_MB_MDL; // MailBox Data Low Register\r
+ AT91_REG CAN_MB_MDH; // MailBox Data High Register\r
+ AT91_REG CAN_MB_MCR; // MailBox Control Register\r
+} AT91S_CAN_MB, *AT91PS_CAN_MB;\r
+\r
+// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- \r
+#define AT91C_CAN_MTIMEMARK ((unsigned int) 0xFFFF << 0) // (CAN_MB) Mailbox Timemark\r
+#define AT91C_CAN_PRIOR ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority\r
+#define AT91C_CAN_MOT ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type\r
+#define AT91C_CAN_MOT_DIS ((unsigned int) 0x0 << 24) // (CAN_MB) \r
+#define AT91C_CAN_MOT_RX ((unsigned int) 0x1 << 24) // (CAN_MB) \r
+#define AT91C_CAN_MOT_RXOVERWRITE ((unsigned int) 0x2 << 24) // (CAN_MB) \r
+#define AT91C_CAN_MOT_TX ((unsigned int) 0x3 << 24) // (CAN_MB) \r
+#define AT91C_CAN_MOT_CONSUMER ((unsigned int) 0x4 << 24) // (CAN_MB) \r
+#define AT91C_CAN_MOT_PRODUCER ((unsigned int) 0x5 << 24) // (CAN_MB) \r
+// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- \r
+#define AT91C_CAN_MIDvB ((unsigned int) 0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode\r
+#define AT91C_CAN_MIDvA ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode\r
+#define AT91C_CAN_MIDE ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version\r
+// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- \r
+// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- \r
+// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- \r
+#define AT91C_CAN_MTIMESTAMP ((unsigned int) 0xFFFF << 0) // (CAN_MB) Timer Value\r
+#define AT91C_CAN_MDLC ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code\r
+#define AT91C_CAN_MRTR ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request\r
+#define AT91C_CAN_MABT ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort\r
+#define AT91C_CAN_MRDY ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready\r
+#define AT91C_CAN_MMI ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored\r
+// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- \r
+// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- \r
+// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- \r
+#define AT91C_CAN_MACR ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox\r
+#define AT91C_CAN_MTCR ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Control Area Network Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_CAN {\r
+ AT91_REG CAN_MR; // Mode Register\r
+ AT91_REG CAN_IER; // Interrupt Enable Register\r
+ AT91_REG CAN_IDR; // Interrupt Disable Register\r
+ AT91_REG CAN_IMR; // Interrupt Mask Register\r
+ AT91_REG CAN_SR; // Status Register\r
+ AT91_REG CAN_BR; // Baudrate Register\r
+ AT91_REG CAN_TIM; // Timer Register\r
+ AT91_REG CAN_TIMESTP; // Time Stamp Register\r
+ AT91_REG CAN_ECR; // Error Counter Register\r
+ AT91_REG CAN_TCR; // Transfer Command Register\r
+ AT91_REG CAN_ACR; // Abort Command Register\r
+ AT91_REG Reserved0[52]; // \r
+ AT91_REG CAN_VR; // Version Register\r
+ AT91_REG Reserved1[64]; // \r
+ AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0\r
+ AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1\r
+ AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2\r
+ AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3\r
+ AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4\r
+ AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5\r
+ AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6\r
+ AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7\r
+ AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8\r
+ AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9\r
+ AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10\r
+ AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11\r
+ AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12\r
+ AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13\r
+ AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14\r
+ AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15\r
+} AT91S_CAN, *AT91PS_CAN;\r
+\r
+// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- \r
+#define AT91C_CAN_CANEN ((unsigned int) 0x1 << 0) // (CAN) CAN Controller Enable\r
+#define AT91C_CAN_LPM ((unsigned int) 0x1 << 1) // (CAN) Disable/Enable Low Power Mode\r
+#define AT91C_CAN_ABM ((unsigned int) 0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode\r
+#define AT91C_CAN_OVL ((unsigned int) 0x1 << 3) // (CAN) Disable/Enable Overload Frame\r
+#define AT91C_CAN_TEOF ((unsigned int) 0x1 << 4) // (CAN) Time Stamp messages at each end of Frame\r
+#define AT91C_CAN_TTM ((unsigned int) 0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode\r
+#define AT91C_CAN_TIMFRZ ((unsigned int) 0x1 << 6) // (CAN) Enable Timer Freeze\r
+#define AT91C_CAN_DRPT ((unsigned int) 0x1 << 7) // (CAN) Disable Repeat\r
+// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- \r
+#define AT91C_CAN_MB0 ((unsigned int) 0x1 << 0) // (CAN) Mailbox 0 Flag\r
+#define AT91C_CAN_MB1 ((unsigned int) 0x1 << 1) // (CAN) Mailbox 1 Flag\r
+#define AT91C_CAN_MB2 ((unsigned int) 0x1 << 2) // (CAN) Mailbox 2 Flag\r
+#define AT91C_CAN_MB3 ((unsigned int) 0x1 << 3) // (CAN) Mailbox 3 Flag\r
+#define AT91C_CAN_MB4 ((unsigned int) 0x1 << 4) // (CAN) Mailbox 4 Flag\r
+#define AT91C_CAN_MB5 ((unsigned int) 0x1 << 5) // (CAN) Mailbox 5 Flag\r
+#define AT91C_CAN_MB6 ((unsigned int) 0x1 << 6) // (CAN) Mailbox 6 Flag\r
+#define AT91C_CAN_MB7 ((unsigned int) 0x1 << 7) // (CAN) Mailbox 7 Flag\r
+#define AT91C_CAN_MB8 ((unsigned int) 0x1 << 8) // (CAN) Mailbox 8 Flag\r
+#define AT91C_CAN_MB9 ((unsigned int) 0x1 << 9) // (CAN) Mailbox 9 Flag\r
+#define AT91C_CAN_MB10 ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag\r
+#define AT91C_CAN_MB11 ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag\r
+#define AT91C_CAN_MB12 ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag\r
+#define AT91C_CAN_MB13 ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag\r
+#define AT91C_CAN_MB14 ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag\r
+#define AT91C_CAN_MB15 ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag\r
+#define AT91C_CAN_ERRA ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag\r
+#define AT91C_CAN_WARN ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag\r
+#define AT91C_CAN_ERRP ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag\r
+#define AT91C_CAN_BOFF ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag\r
+#define AT91C_CAN_SLEEP ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag\r
+#define AT91C_CAN_WAKEUP ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag\r
+#define AT91C_CAN_TOVF ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag\r
+#define AT91C_CAN_TSTP ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag\r
+#define AT91C_CAN_CERR ((unsigned int) 0x1 << 24) // (CAN) CRC Error\r
+#define AT91C_CAN_SERR ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error\r
+#define AT91C_CAN_AERR ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error\r
+#define AT91C_CAN_FERR ((unsigned int) 0x1 << 27) // (CAN) Form Error\r
+#define AT91C_CAN_BERR ((unsigned int) 0x1 << 28) // (CAN) Bit Error\r
+// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- \r
+// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- \r
+// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- \r
+#define AT91C_CAN_RBSY ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy\r
+#define AT91C_CAN_TBSY ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy\r
+#define AT91C_CAN_OVLY ((unsigned int) 0x1 << 31) // (CAN) Overload Busy\r
+// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- \r
+#define AT91C_CAN_PHASE2 ((unsigned int) 0x7 << 0) // (CAN) Phase 2 segment\r
+#define AT91C_CAN_PHASE1 ((unsigned int) 0x7 << 4) // (CAN) Phase 1 segment\r
+#define AT91C_CAN_PROPAG ((unsigned int) 0x7 << 8) // (CAN) Programmation time segment\r
+#define AT91C_CAN_SYNC ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment\r
+#define AT91C_CAN_BRP ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler\r
+#define AT91C_CAN_SMP ((unsigned int) 0x1 << 24) // (CAN) Sampling mode\r
+// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- \r
+#define AT91C_CAN_TIMER ((unsigned int) 0xFFFF << 0) // (CAN) Timer field\r
+// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- \r
+// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- \r
+#define AT91C_CAN_REC ((unsigned int) 0xFF << 0) // (CAN) Receive Error Counter\r
+#define AT91C_CAN_TEC ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter\r
+// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- \r
+#define AT91C_CAN_TIMRST ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field\r
+// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100\r
+// *****************************************************************************\r
+typedef struct _AT91S_EMAC {\r
+ AT91_REG EMAC_NCR; // Network Control Register\r
+ AT91_REG EMAC_NCFGR; // Network Configuration Register\r
+ AT91_REG EMAC_NSR; // Network Status Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG EMAC_TSR; // Transmit Status Register\r
+ AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer\r
+ AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer\r
+ AT91_REG EMAC_RSR; // Receive Status Register\r
+ AT91_REG EMAC_ISR; // Interrupt Status Register\r
+ AT91_REG EMAC_IER; // Interrupt Enable Register\r
+ AT91_REG EMAC_IDR; // Interrupt Disable Register\r
+ AT91_REG EMAC_IMR; // Interrupt Mask Register\r
+ AT91_REG EMAC_MAN; // PHY Maintenance Register\r
+ AT91_REG EMAC_PTR; // Pause Time Register\r
+ AT91_REG EMAC_PFR; // Pause Frames received Register\r
+ AT91_REG EMAC_FTO; // Frames Transmitted OK Register\r
+ AT91_REG EMAC_SCF; // Single Collision Frame Register\r
+ AT91_REG EMAC_MCF; // Multiple Collision Frame Register\r
+ AT91_REG EMAC_FRO; // Frames Received OK Register\r
+ AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register\r
+ AT91_REG EMAC_ALE; // Alignment Error Register\r
+ AT91_REG EMAC_DTF; // Deferred Transmission Frame Register\r
+ AT91_REG EMAC_LCOL; // Late Collision Register\r
+ AT91_REG EMAC_ECOL; // Excessive Collision Register\r
+ AT91_REG EMAC_TUND; // Transmit Underrun Error Register\r
+ AT91_REG EMAC_CSE; // Carrier Sense Error Register\r
+ AT91_REG EMAC_RRE; // Receive Ressource Error Register\r
+ AT91_REG EMAC_ROV; // Receive Overrun Errors Register\r
+ AT91_REG EMAC_RSE; // Receive Symbol Errors Register\r
+ AT91_REG EMAC_ELE; // Excessive Length Errors Register\r
+ AT91_REG EMAC_RJA; // Receive Jabbers Register\r
+ AT91_REG EMAC_USF; // Undersize Frames Register\r
+ AT91_REG EMAC_STE; // SQE Test Error Register\r
+ AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register\r
+ AT91_REG EMAC_TPF; // Transmitted Pause Frames Register\r
+ AT91_REG EMAC_HRB; // Hash Address Bottom[31:0]\r
+ AT91_REG EMAC_HRT; // Hash Address Top[63:32]\r
+ AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes\r
+ AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes\r
+ AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes\r
+ AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes\r
+ AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes\r
+ AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes\r
+ AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes\r
+ AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes\r
+ AT91_REG EMAC_TID; // Type ID Checking Register\r
+ AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register\r
+ AT91_REG EMAC_USRIO; // USER Input/Output Register\r
+ AT91_REG EMAC_WOL; // Wake On LAN Register\r
+ AT91_REG Reserved1[13]; // \r
+ AT91_REG EMAC_REV; // Revision Register\r
+} AT91S_EMAC, *AT91PS_EMAC;\r
+\r
+// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- \r
+#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.\r
+#define AT91C_EMAC_LLB ((unsigned int) 0x1 << 1) // (EMAC) Loopback local. \r
+#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) // (EMAC) Receive enable. \r
+#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) // (EMAC) Transmit enable. \r
+#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) // (EMAC) Management port enable. \r
+#define AT91C_EMAC_CLRSTAT ((unsigned int) 0x1 << 5) // (EMAC) Clear statistics registers. \r
+#define AT91C_EMAC_INCSTAT ((unsigned int) 0x1 << 6) // (EMAC) Increment statistics registers. \r
+#define AT91C_EMAC_WESTAT ((unsigned int) 0x1 << 7) // (EMAC) Write enable for statistics registers. \r
+#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) // (EMAC) Back pressure. \r
+#define AT91C_EMAC_TSTART ((unsigned int) 0x1 << 9) // (EMAC) Start Transmission. \r
+#define AT91C_EMAC_THALT ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt. \r
+#define AT91C_EMAC_TPFR ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame \r
+#define AT91C_EMAC_TZQ ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame\r
+// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- \r
+#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) // (EMAC) Speed. \r
+#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) // (EMAC) Full duplex. \r
+#define AT91C_EMAC_JFRAME ((unsigned int) 0x1 << 3) // (EMAC) Jumbo Frames. \r
+#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) // (EMAC) Copy all frames. \r
+#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) // (EMAC) No broadcast. \r
+#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) // (EMAC) Multicast hash event enable\r
+#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) // (EMAC) Unicast hash enable. \r
+#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) // (EMAC) Receive 1522 bytes. \r
+#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) // (EMAC) External address match enable. \r
+#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) // (EMAC) \r
+#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8\r
+#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16\r
+#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32\r
+#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64\r
+#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) // (EMAC) \r
+#define AT91C_EMAC_PAE ((unsigned int) 0x1 << 13) // (EMAC) \r
+#define AT91C_EMAC_RBOF ((unsigned int) 0x3 << 14) // (EMAC) \r
+#define AT91C_EMAC_RBOF_OFFSET_0 ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer\r
+#define AT91C_EMAC_RBOF_OFFSET_1 ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer\r
+#define AT91C_EMAC_RBOF_OFFSET_2 ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer\r
+#define AT91C_EMAC_RBOF_OFFSET_3 ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer\r
+#define AT91C_EMAC_RLCE ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable\r
+#define AT91C_EMAC_DRFCS ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS\r
+#define AT91C_EMAC_EFRHD ((unsigned int) 0x1 << 18) // (EMAC) \r
+#define AT91C_EMAC_IRXFCS ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS\r
+// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- \r
+#define AT91C_EMAC_LINKR ((unsigned int) 0x1 << 0) // (EMAC) \r
+#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) // (EMAC) \r
+#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) // (EMAC) \r
+// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- \r
+#define AT91C_EMAC_UBR ((unsigned int) 0x1 << 0) // (EMAC) \r
+#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) // (EMAC) \r
+#define AT91C_EMAC_RLES ((unsigned int) 0x1 << 2) // (EMAC) \r
+#define AT91C_EMAC_TGO ((unsigned int) 0x1 << 3) // (EMAC) Transmit Go\r
+#define AT91C_EMAC_BEX ((unsigned int) 0x1 << 4) // (EMAC) Buffers exhausted mid frame\r
+#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) // (EMAC) \r
+#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) // (EMAC) \r
+// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- \r
+#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) // (EMAC) \r
+#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) // (EMAC) \r
+#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 2) // (EMAC) \r
+// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- \r
+#define AT91C_EMAC_MFD ((unsigned int) 0x1 << 0) // (EMAC) \r
+#define AT91C_EMAC_RCOMP ((unsigned int) 0x1 << 1) // (EMAC) \r
+#define AT91C_EMAC_RXUBR ((unsigned int) 0x1 << 2) // (EMAC) \r
+#define AT91C_EMAC_TXUBR ((unsigned int) 0x1 << 3) // (EMAC) \r
+#define AT91C_EMAC_TUNDR ((unsigned int) 0x1 << 4) // (EMAC) \r
+#define AT91C_EMAC_RLEX ((unsigned int) 0x1 << 5) // (EMAC) \r
+#define AT91C_EMAC_TXERR ((unsigned int) 0x1 << 6) // (EMAC) \r
+#define AT91C_EMAC_TCOMP ((unsigned int) 0x1 << 7) // (EMAC) \r
+#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) // (EMAC) \r
+#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) // (EMAC) \r
+#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) // (EMAC) \r
+#define AT91C_EMAC_PFRE ((unsigned int) 0x1 << 12) // (EMAC) \r
+#define AT91C_EMAC_PTZ ((unsigned int) 0x1 << 13) // (EMAC) \r
+// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- \r
+// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- \r
+// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- \r
+// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- \r
+#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) // (EMAC) \r
+#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) // (EMAC) \r
+#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) // (EMAC) \r
+#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) // (EMAC) \r
+#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) // (EMAC) \r
+#define AT91C_EMAC_SOF ((unsigned int) 0x3 << 30) // (EMAC) \r
+// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- \r
+#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 0) // (EMAC) Reduce MII\r
+// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- \r
+#define AT91C_EMAC_IP ((unsigned int) 0xFFFF << 0) // (EMAC) ARP request IP address\r
+#define AT91C_EMAC_MAG ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable\r
+#define AT91C_EMAC_ARP ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable\r
+#define AT91C_EMAC_SA1 ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable\r
+// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- \r
+#define AT91C_EMAC_REVREF ((unsigned int) 0xFFFF << 0) // (EMAC) \r
+#define AT91C_EMAC_PARTREF ((unsigned int) 0xFFFF << 16) // (EMAC) \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Analog to Digital Convertor\r
+// *****************************************************************************\r
+typedef struct _AT91S_ADC {\r
+ AT91_REG ADC_CR; // ADC Control Register\r
+ AT91_REG ADC_MR; // ADC Mode Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG ADC_CHER; // ADC Channel Enable Register\r
+ AT91_REG ADC_CHDR; // ADC Channel Disable Register\r
+ AT91_REG ADC_CHSR; // ADC Channel Status Register\r
+ AT91_REG ADC_SR; // ADC Status Register\r
+ AT91_REG ADC_LCDR; // ADC Last Converted Data Register\r
+ AT91_REG ADC_IER; // ADC Interrupt Enable Register\r
+ AT91_REG ADC_IDR; // ADC Interrupt Disable Register\r
+ AT91_REG ADC_IMR; // ADC Interrupt Mask Register\r
+ AT91_REG ADC_CDR0; // ADC Channel Data Register 0\r
+ AT91_REG ADC_CDR1; // ADC Channel Data Register 1\r
+ AT91_REG ADC_CDR2; // ADC Channel Data Register 2\r
+ AT91_REG ADC_CDR3; // ADC Channel Data Register 3\r
+ AT91_REG ADC_CDR4; // ADC Channel Data Register 4\r
+ AT91_REG ADC_CDR5; // ADC Channel Data Register 5\r
+ AT91_REG ADC_CDR6; // ADC Channel Data Register 6\r
+ AT91_REG ADC_CDR7; // ADC Channel Data Register 7\r
+ AT91_REG Reserved1[44]; // \r
+ AT91_REG ADC_RPR; // Receive Pointer Register\r
+ AT91_REG ADC_RCR; // Receive Counter Register\r
+ AT91_REG ADC_TPR; // Transmit Pointer Register\r
+ AT91_REG ADC_TCR; // Transmit Counter Register\r
+ AT91_REG ADC_RNPR; // Receive Next Pointer Register\r
+ AT91_REG ADC_RNCR; // Receive Next Counter Register\r
+ AT91_REG ADC_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG ADC_TNCR; // Transmit Next Counter Register\r
+ AT91_REG ADC_PTCR; // PDC Transfer Control Register\r
+ AT91_REG ADC_PTSR; // PDC Transfer Status Register\r
+} AT91S_ADC, *AT91PS_ADC;\r
+\r
+// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- \r
+#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset\r
+#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion\r
+// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- \r
+#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable\r
+#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software\r
+#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.\r
+#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection\r
+#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0\r
+#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1\r
+#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2\r
+#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3\r
+#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4\r
+#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5\r
+#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger\r
+#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution.\r
+#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution\r
+#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution\r
+#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode\r
+#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode\r
+#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode\r
+#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection\r
+#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time\r
+#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time\r
+// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- \r
+#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0\r
+#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1\r
+#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2\r
+#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3\r
+#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4\r
+#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5\r
+#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6\r
+#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7\r
+// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- \r
+// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- \r
+// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- \r
+#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion\r
+#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error\r
+#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready\r
+#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun\r
+#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer\r
+#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt\r
+// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- \r
+#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted\r
+// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- \r
+// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- \r
+// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- \r
+// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- \r
+#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data\r
+// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- \r
+// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- \r
+// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- \r
+// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- \r
+// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- \r
+// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- \r
+// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Advanced Encryption Standard\r
+// *****************************************************************************\r
+typedef struct _AT91S_AES {\r
+ AT91_REG AES_CR; // Control Register\r
+ AT91_REG AES_MR; // Mode Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG AES_IER; // Interrupt Enable Register\r
+ AT91_REG AES_IDR; // Interrupt Disable Register\r
+ AT91_REG AES_IMR; // Interrupt Mask Register\r
+ AT91_REG AES_ISR; // Interrupt Status Register\r
+ AT91_REG AES_KEYWxR[4]; // Key Word x Register\r
+ AT91_REG Reserved1[4]; // \r
+ AT91_REG AES_IDATAxR[4]; // Input Data x Register\r
+ AT91_REG AES_ODATAxR[4]; // Output Data x Register\r
+ AT91_REG AES_IVxR[4]; // Initialization Vector x Register\r
+ AT91_REG Reserved2[35]; // \r
+ AT91_REG AES_VR; // AES Version Register\r
+ AT91_REG AES_RPR; // Receive Pointer Register\r
+ AT91_REG AES_RCR; // Receive Counter Register\r
+ AT91_REG AES_TPR; // Transmit Pointer Register\r
+ AT91_REG AES_TCR; // Transmit Counter Register\r
+ AT91_REG AES_RNPR; // Receive Next Pointer Register\r
+ AT91_REG AES_RNCR; // Receive Next Counter Register\r
+ AT91_REG AES_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG AES_TNCR; // Transmit Next Counter Register\r
+ AT91_REG AES_PTCR; // PDC Transfer Control Register\r
+ AT91_REG AES_PTSR; // PDC Transfer Status Register\r
+} AT91S_AES, *AT91PS_AES;\r
+\r
+// -------- AES_CR : (AES Offset: 0x0) Control Register -------- \r
+#define AT91C_AES_START ((unsigned int) 0x1 << 0) // (AES) Starts Processing\r
+#define AT91C_AES_SWRST ((unsigned int) 0x1 << 8) // (AES) Software Reset\r
+#define AT91C_AES_LOADSEED ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading\r
+// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- \r
+#define AT91C_AES_CIPHER ((unsigned int) 0x1 << 0) // (AES) Processing Mode\r
+#define AT91C_AES_PROCDLY ((unsigned int) 0xF << 4) // (AES) Processing Delay\r
+#define AT91C_AES_SMOD ((unsigned int) 0x3 << 8) // (AES) Start Mode\r
+#define AT91C_AES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.\r
+#define AT91C_AES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).\r
+#define AT91C_AES_SMOD_PDC ((unsigned int) 0x2 << 8) // (AES) PDC Mode (cf datasheet).\r
+#define AT91C_AES_OPMOD ((unsigned int) 0x7 << 12) // (AES) Operation Mode\r
+#define AT91C_AES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode.\r
+#define AT91C_AES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode.\r
+#define AT91C_AES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode.\r
+#define AT91C_AES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode.\r
+#define AT91C_AES_OPMOD_CTR ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode.\r
+#define AT91C_AES_LOD ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode\r
+#define AT91C_AES_CFBS ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size\r
+#define AT91C_AES_CFBS_128_BIT ((unsigned int) 0x0 << 16) // (AES) 128-bit.\r
+#define AT91C_AES_CFBS_64_BIT ((unsigned int) 0x1 << 16) // (AES) 64-bit.\r
+#define AT91C_AES_CFBS_32_BIT ((unsigned int) 0x2 << 16) // (AES) 32-bit.\r
+#define AT91C_AES_CFBS_16_BIT ((unsigned int) 0x3 << 16) // (AES) 16-bit.\r
+#define AT91C_AES_CFBS_8_BIT ((unsigned int) 0x4 << 16) // (AES) 8-bit.\r
+#define AT91C_AES_CKEY ((unsigned int) 0xF << 20) // (AES) Countermeasure Key\r
+#define AT91C_AES_CTYPE ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type\r
+#define AT91C_AES_CTYPE_TYPE1_EN ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled.\r
+#define AT91C_AES_CTYPE_TYPE2_EN ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled.\r
+#define AT91C_AES_CTYPE_TYPE3_EN ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled.\r
+#define AT91C_AES_CTYPE_TYPE4_EN ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled.\r
+#define AT91C_AES_CTYPE_TYPE5_EN ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled.\r
+// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- \r
+#define AT91C_AES_DATRDY ((unsigned int) 0x1 << 0) // (AES) DATRDY\r
+#define AT91C_AES_ENDRX ((unsigned int) 0x1 << 1) // (AES) PDC Read Buffer End\r
+#define AT91C_AES_ENDTX ((unsigned int) 0x1 << 2) // (AES) PDC Write Buffer End\r
+#define AT91C_AES_RXBUFF ((unsigned int) 0x1 << 3) // (AES) PDC Read Buffer Full\r
+#define AT91C_AES_TXBUFE ((unsigned int) 0x1 << 4) // (AES) PDC Write Buffer Empty\r
+#define AT91C_AES_URAD ((unsigned int) 0x1 << 8) // (AES) Unspecified Register Access Detection\r
+// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- \r
+// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- \r
+// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- \r
+#define AT91C_AES_URAT ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status\r
+#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode.\r
+#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing.\r
+#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing.\r
+#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation.\r
+#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation.\r
+#define AT91C_AES_URAT_WO_REG_READ ((unsigned int) 0x5 << 12) // (AES) Write-only register read access.\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard\r
+// *****************************************************************************\r
+typedef struct _AT91S_TDES {\r
+ AT91_REG TDES_CR; // Control Register\r
+ AT91_REG TDES_MR; // Mode Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG TDES_IER; // Interrupt Enable Register\r
+ AT91_REG TDES_IDR; // Interrupt Disable Register\r
+ AT91_REG TDES_IMR; // Interrupt Mask Register\r
+ AT91_REG TDES_ISR; // Interrupt Status Register\r
+ AT91_REG TDES_KEY1WxR[2]; // Key 1 Word x Register\r
+ AT91_REG TDES_KEY2WxR[2]; // Key 2 Word x Register\r
+ AT91_REG TDES_KEY3WxR[2]; // Key 3 Word x Register\r
+ AT91_REG Reserved1[2]; // \r
+ AT91_REG TDES_IDATAxR[2]; // Input Data x Register\r
+ AT91_REG Reserved2[2]; // \r
+ AT91_REG TDES_ODATAxR[2]; // Output Data x Register\r
+ AT91_REG Reserved3[2]; // \r
+ AT91_REG TDES_IVxR[2]; // Initialization Vector x Register\r
+ AT91_REG Reserved4[37]; // \r
+ AT91_REG TDES_VR; // TDES Version Register\r
+ AT91_REG TDES_RPR; // Receive Pointer Register\r
+ AT91_REG TDES_RCR; // Receive Counter Register\r
+ AT91_REG TDES_TPR; // Transmit Pointer Register\r
+ AT91_REG TDES_TCR; // Transmit Counter Register\r
+ AT91_REG TDES_RNPR; // Receive Next Pointer Register\r
+ AT91_REG TDES_RNCR; // Receive Next Counter Register\r
+ AT91_REG TDES_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG TDES_TNCR; // Transmit Next Counter Register\r
+ AT91_REG TDES_PTCR; // PDC Transfer Control Register\r
+ AT91_REG TDES_PTSR; // PDC Transfer Status Register\r
+} AT91S_TDES, *AT91PS_TDES;\r
+\r
+// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- \r
+#define AT91C_TDES_START ((unsigned int) 0x1 << 0) // (TDES) Starts Processing\r
+#define AT91C_TDES_SWRST ((unsigned int) 0x1 << 8) // (TDES) Software Reset\r
+// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- \r
+#define AT91C_TDES_CIPHER ((unsigned int) 0x1 << 0) // (TDES) Processing Mode\r
+#define AT91C_TDES_TDESMOD ((unsigned int) 0x1 << 1) // (TDES) Single or Triple DES Mode\r
+#define AT91C_TDES_KEYMOD ((unsigned int) 0x1 << 4) // (TDES) Key Mode\r
+#define AT91C_TDES_SMOD ((unsigned int) 0x3 << 8) // (TDES) Start Mode\r
+#define AT91C_TDES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.\r
+#define AT91C_TDES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).\r
+#define AT91C_TDES_SMOD_PDC ((unsigned int) 0x2 << 8) // (TDES) PDC Mode (cf datasheet).\r
+#define AT91C_TDES_OPMOD ((unsigned int) 0x3 << 12) // (TDES) Operation Mode\r
+#define AT91C_TDES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode.\r
+#define AT91C_TDES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode.\r
+#define AT91C_TDES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode.\r
+#define AT91C_TDES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode.\r
+#define AT91C_TDES_LOD ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode\r
+#define AT91C_TDES_CFBS ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size\r
+#define AT91C_TDES_CFBS_64_BIT ((unsigned int) 0x0 << 16) // (TDES) 64-bit.\r
+#define AT91C_TDES_CFBS_32_BIT ((unsigned int) 0x1 << 16) // (TDES) 32-bit.\r
+#define AT91C_TDES_CFBS_16_BIT ((unsigned int) 0x2 << 16) // (TDES) 16-bit.\r
+#define AT91C_TDES_CFBS_8_BIT ((unsigned int) 0x3 << 16) // (TDES) 8-bit.\r
+// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- \r
+#define AT91C_TDES_DATRDY ((unsigned int) 0x1 << 0) // (TDES) DATRDY\r
+#define AT91C_TDES_ENDRX ((unsigned int) 0x1 << 1) // (TDES) PDC Read Buffer End\r
+#define AT91C_TDES_ENDTX ((unsigned int) 0x1 << 2) // (TDES) PDC Write Buffer End\r
+#define AT91C_TDES_RXBUFF ((unsigned int) 0x1 << 3) // (TDES) PDC Read Buffer Full\r
+#define AT91C_TDES_TXBUFE ((unsigned int) 0x1 << 4) // (TDES) PDC Write Buffer Empty\r
+#define AT91C_TDES_URAD ((unsigned int) 0x1 << 8) // (TDES) Unspecified Register Access Detection\r
+// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- \r
+// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- \r
+// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- \r
+#define AT91C_TDES_URAT ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status\r
+#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode.\r
+#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing.\r
+#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing.\r
+#define AT91C_TDES_URAT_WO_REG_READ ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access.\r
+\r
+// *****************************************************************************\r
+// REGISTER ADDRESS DEFINITION FOR AT91SAM7X256\r
+// *****************************************************************************\r
+// ========== Register definition for SYS peripheral ========== \r
+// ========== Register definition for AIC peripheral ========== \r
+#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register\r
+#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register\r
+#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register\r
+#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect)\r
+#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register\r
+#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register\r
+#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register\r
+#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register\r
+#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register\r
+#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register\r
+#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register\r
+#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register\r
+#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register\r
+#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register\r
+#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register\r
+#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register\r
+#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register\r
+#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register\r
+// ========== Register definition for PDC_DBGU peripheral ========== \r
+#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register\r
+#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register\r
+#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register\r
+#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register\r
+#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register\r
+#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register\r
+#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register\r
+#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register\r
+#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register\r
+#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register\r
+// ========== Register definition for DBGU peripheral ========== \r
+#define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register\r
+#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register\r
+#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register\r
+#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register\r
+#define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register\r
+#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register\r
+#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register\r
+#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register\r
+#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register\r
+#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register\r
+#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register\r
+#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register\r
+// ========== Register definition for PIOA peripheral ========== \r
+#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr\r
+#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register\r
+#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register\r
+#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register\r
+#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register\r
+#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register\r
+#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register\r
+#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register\r
+#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register\r
+#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register\r
+#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register\r
+#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register\r
+#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register\r
+#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register\r
+#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register\r
+#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register\r
+#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register\r
+#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register\r
+#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register\r
+#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register\r
+#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register\r
+#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register\r
+#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register\r
+#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register\r
+#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register\r
+#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register\r
+#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register\r
+#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register\r
+#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register\r
+// ========== Register definition for PIOB peripheral ========== \r
+#define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register\r
+#define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register\r
+#define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register\r
+#define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register\r
+#define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register\r
+#define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register\r
+#define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register\r
+#define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register\r
+#define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register\r
+#define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register\r
+#define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register\r
+#define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register\r
+#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register\r
+#define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register\r
+#define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register\r
+#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register\r
+#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr\r
+#define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register\r
+#define AT91C_PIOB_PPUER ((AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register\r
+#define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register\r
+#define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register\r
+#define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register\r
+#define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register\r
+#define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register\r
+#define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register\r
+#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register\r
+#define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register\r
+#define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register\r
+#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register\r
+// ========== Register definition for CKGR peripheral ========== \r
+#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register\r
+#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register\r
+#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register\r
+// ========== Register definition for PMC peripheral ========== \r
+#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register\r
+#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register\r
+#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register\r
+#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register\r
+#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register\r
+#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register\r
+#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register\r
+#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register\r
+#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register\r
+#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register\r
+#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register\r
+#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register\r
+#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register\r
+#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register\r
+#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register\r
+// ========== Register definition for RSTC peripheral ========== \r
+#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register\r
+#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register\r
+#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register\r
+// ========== Register definition for RTTC peripheral ========== \r
+#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register\r
+#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register\r
+#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register\r
+#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register\r
+// ========== Register definition for PITC peripheral ========== \r
+#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register\r
+#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register\r
+#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register\r
+#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register\r
+// ========== Register definition for WDTC peripheral ========== \r
+#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register\r
+#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register\r
+#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register\r
+// ========== Register definition for VREG peripheral ========== \r
+#define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register\r
+// ========== Register definition for MC peripheral ========== \r
+#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register\r
+#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register\r
+#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register\r
+#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register\r
+#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register\r
+#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register\r
+// ========== Register definition for PDC_SPI1 peripheral ========== \r
+#define AT91C_SPI1_PTCR ((AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register\r
+#define AT91C_SPI1_RPR ((AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register\r
+#define AT91C_SPI1_TNCR ((AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register\r
+#define AT91C_SPI1_TPR ((AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register\r
+#define AT91C_SPI1_TNPR ((AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register\r
+#define AT91C_SPI1_TCR ((AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register\r
+#define AT91C_SPI1_RCR ((AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register\r
+#define AT91C_SPI1_RNPR ((AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register\r
+#define AT91C_SPI1_RNCR ((AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register\r
+#define AT91C_SPI1_PTSR ((AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register\r
+// ========== Register definition for SPI1 peripheral ========== \r
+#define AT91C_SPI1_IMR ((AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register\r
+#define AT91C_SPI1_IER ((AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register\r
+#define AT91C_SPI1_MR ((AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register\r
+#define AT91C_SPI1_RDR ((AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register\r
+#define AT91C_SPI1_IDR ((AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register\r
+#define AT91C_SPI1_SR ((AT91_REG *) 0xFFFE4010) // (SPI1) Status Register\r
+#define AT91C_SPI1_TDR ((AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register\r
+#define AT91C_SPI1_CR ((AT91_REG *) 0xFFFE4000) // (SPI1) Control Register\r
+#define AT91C_SPI1_CSR ((AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register\r
+// ========== Register definition for PDC_SPI0 peripheral ========== \r
+#define AT91C_SPI0_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register\r
+#define AT91C_SPI0_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register\r
+#define AT91C_SPI0_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register\r
+#define AT91C_SPI0_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register\r
+#define AT91C_SPI0_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register\r
+#define AT91C_SPI0_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register\r
+#define AT91C_SPI0_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register\r
+#define AT91C_SPI0_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register\r
+#define AT91C_SPI0_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register\r
+#define AT91C_SPI0_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register\r
+// ========== Register definition for SPI0 peripheral ========== \r
+#define AT91C_SPI0_IER ((AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register\r
+#define AT91C_SPI0_SR ((AT91_REG *) 0xFFFE0010) // (SPI0) Status Register\r
+#define AT91C_SPI0_IDR ((AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register\r
+#define AT91C_SPI0_CR ((AT91_REG *) 0xFFFE0000) // (SPI0) Control Register\r
+#define AT91C_SPI0_MR ((AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register\r
+#define AT91C_SPI0_IMR ((AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register\r
+#define AT91C_SPI0_TDR ((AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register\r
+#define AT91C_SPI0_RDR ((AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register\r
+#define AT91C_SPI0_CSR ((AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register\r
+// ========== Register definition for PDC_US1 peripheral ========== \r
+#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register\r
+#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register\r
+#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register\r
+#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register\r
+#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register\r
+#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register\r
+#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register\r
+#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register\r
+#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register\r
+#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register\r
+// ========== Register definition for US1 peripheral ========== \r
+#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register\r
+#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register\r
+#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register\r
+#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register\r
+#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register\r
+#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register\r
+#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register\r
+#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register\r
+#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register\r
+#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register\r
+#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register\r
+#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register\r
+#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register\r
+#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register\r
+// ========== Register definition for PDC_US0 peripheral ========== \r
+#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register\r
+#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register\r
+#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register\r
+#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register\r
+#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register\r
+#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register\r
+#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register\r
+#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register\r
+#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register\r
+#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register\r
+// ========== Register definition for US0 peripheral ========== \r
+#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register\r
+#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register\r
+#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register\r
+#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register\r
+#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register\r
+#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register\r
+#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register\r
+#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register\r
+#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register\r
+#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register\r
+#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register\r
+#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register\r
+#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register\r
+#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register\r
+// ========== Register definition for PDC_SSC peripheral ========== \r
+#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register\r
+#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register\r
+#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register\r
+#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register\r
+#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register\r
+#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register\r
+#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register\r
+#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register\r
+#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register\r
+#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register\r
+// ========== Register definition for SSC peripheral ========== \r
+#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register\r
+#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register\r
+#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register\r
+#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register\r
+#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register\r
+#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister\r
+#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register\r
+#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register\r
+#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register\r
+#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register\r
+#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register\r
+#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register\r
+#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register\r
+#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register\r
+// ========== Register definition for TWI peripheral ========== \r
+#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register\r
+#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register\r
+#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register\r
+#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register\r
+#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register\r
+#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register\r
+#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register\r
+#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register\r
+#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register\r
+#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register\r
+// ========== Register definition for PWMC_CH3 peripheral ========== \r
+#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register\r
+#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved\r
+#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register\r
+#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register\r
+#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register\r
+#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register\r
+// ========== Register definition for PWMC_CH2 peripheral ========== \r
+#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved\r
+#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register\r
+#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register\r
+#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register\r
+#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register\r
+#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register\r
+// ========== Register definition for PWMC_CH1 peripheral ========== \r
+#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved\r
+#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register\r
+#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register\r
+#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register\r
+#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register\r
+#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register\r
+// ========== Register definition for PWMC_CH0 peripheral ========== \r
+#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved\r
+#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register\r
+#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register\r
+#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register\r
+#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register\r
+#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register\r
+// ========== Register definition for PWMC peripheral ========== \r
+#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register\r
+#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register\r
+#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register\r
+#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register\r
+#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register\r
+#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register\r
+#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register\r
+#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register\r
+#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register\r
+// ========== Register definition for UDP peripheral ========== \r
+#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register\r
+#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register\r
+#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register\r
+#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register\r
+#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register\r
+#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register\r
+#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register\r
+#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register\r
+#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register\r
+#define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register\r
+#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register\r
+#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register\r
+// ========== Register definition for TC0 peripheral ========== \r
+#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register\r
+#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C\r
+#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B\r
+#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register\r
+#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register\r
+#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A\r
+#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register\r
+#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value\r
+#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register\r
+// ========== Register definition for TC1 peripheral ========== \r
+#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B\r
+#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register\r
+#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register\r
+#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register\r
+#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register\r
+#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A\r
+#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C\r
+#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register\r
+#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value\r
+// ========== Register definition for TC2 peripheral ========== \r
+#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register\r
+#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value\r
+#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A\r
+#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B\r
+#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register\r
+#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register\r
+#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C\r
+#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register\r
+#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register\r
+// ========== Register definition for TCB peripheral ========== \r
+#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register\r
+#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register\r
+// ========== Register definition for CAN_MB0 peripheral ========== \r
+#define AT91C_CAN_MB0_MDL ((AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register\r
+#define AT91C_CAN_MB0_MAM ((AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register\r
+#define AT91C_CAN_MB0_MCR ((AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register\r
+#define AT91C_CAN_MB0_MID ((AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register\r
+#define AT91C_CAN_MB0_MSR ((AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register\r
+#define AT91C_CAN_MB0_MFID ((AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register\r
+#define AT91C_CAN_MB0_MDH ((AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register\r
+#define AT91C_CAN_MB0_MMR ((AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register\r
+// ========== Register definition for CAN_MB1 peripheral ========== \r
+#define AT91C_CAN_MB1_MDL ((AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register\r
+#define AT91C_CAN_MB1_MID ((AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register\r
+#define AT91C_CAN_MB1_MMR ((AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register\r
+#define AT91C_CAN_MB1_MSR ((AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register\r
+#define AT91C_CAN_MB1_MAM ((AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register\r
+#define AT91C_CAN_MB1_MDH ((AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register\r
+#define AT91C_CAN_MB1_MCR ((AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register\r
+#define AT91C_CAN_MB1_MFID ((AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register\r
+// ========== Register definition for CAN_MB2 peripheral ========== \r
+#define AT91C_CAN_MB2_MCR ((AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register\r
+#define AT91C_CAN_MB2_MDH ((AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register\r
+#define AT91C_CAN_MB2_MID ((AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register\r
+#define AT91C_CAN_MB2_MDL ((AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register\r
+#define AT91C_CAN_MB2_MMR ((AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register\r
+#define AT91C_CAN_MB2_MAM ((AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register\r
+#define AT91C_CAN_MB2_MFID ((AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register\r
+#define AT91C_CAN_MB2_MSR ((AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register\r
+// ========== Register definition for CAN_MB3 peripheral ========== \r
+#define AT91C_CAN_MB3_MFID ((AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register\r
+#define AT91C_CAN_MB3_MAM ((AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register\r
+#define AT91C_CAN_MB3_MID ((AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register\r
+#define AT91C_CAN_MB3_MCR ((AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register\r
+#define AT91C_CAN_MB3_MMR ((AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register\r
+#define AT91C_CAN_MB3_MSR ((AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register\r
+#define AT91C_CAN_MB3_MDL ((AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register\r
+#define AT91C_CAN_MB3_MDH ((AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register\r
+// ========== Register definition for CAN_MB4 peripheral ========== \r
+#define AT91C_CAN_MB4_MID ((AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register\r
+#define AT91C_CAN_MB4_MMR ((AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register\r
+#define AT91C_CAN_MB4_MDH ((AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register\r
+#define AT91C_CAN_MB4_MFID ((AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register\r
+#define AT91C_CAN_MB4_MSR ((AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register\r
+#define AT91C_CAN_MB4_MCR ((AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register\r
+#define AT91C_CAN_MB4_MDL ((AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register\r
+#define AT91C_CAN_MB4_MAM ((AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register\r
+// ========== Register definition for CAN_MB5 peripheral ========== \r
+#define AT91C_CAN_MB5_MSR ((AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register\r
+#define AT91C_CAN_MB5_MCR ((AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register\r
+#define AT91C_CAN_MB5_MFID ((AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register\r
+#define AT91C_CAN_MB5_MDH ((AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register\r
+#define AT91C_CAN_MB5_MID ((AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register\r
+#define AT91C_CAN_MB5_MMR ((AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register\r
+#define AT91C_CAN_MB5_MDL ((AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register\r
+#define AT91C_CAN_MB5_MAM ((AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register\r
+// ========== Register definition for CAN_MB6 peripheral ========== \r
+#define AT91C_CAN_MB6_MFID ((AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register\r
+#define AT91C_CAN_MB6_MID ((AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register\r
+#define AT91C_CAN_MB6_MAM ((AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register\r
+#define AT91C_CAN_MB6_MSR ((AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register\r
+#define AT91C_CAN_MB6_MDL ((AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register\r
+#define AT91C_CAN_MB6_MCR ((AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register\r
+#define AT91C_CAN_MB6_MDH ((AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register\r
+#define AT91C_CAN_MB6_MMR ((AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register\r
+// ========== Register definition for CAN_MB7 peripheral ========== \r
+#define AT91C_CAN_MB7_MCR ((AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register\r
+#define AT91C_CAN_MB7_MDH ((AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register\r
+#define AT91C_CAN_MB7_MFID ((AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register\r
+#define AT91C_CAN_MB7_MDL ((AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register\r
+#define AT91C_CAN_MB7_MID ((AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register\r
+#define AT91C_CAN_MB7_MMR ((AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register\r
+#define AT91C_CAN_MB7_MAM ((AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register\r
+#define AT91C_CAN_MB7_MSR ((AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register\r
+// ========== Register definition for CAN peripheral ========== \r
+#define AT91C_CAN_TCR ((AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register\r
+#define AT91C_CAN_IMR ((AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register\r
+#define AT91C_CAN_IER ((AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register\r
+#define AT91C_CAN_ECR ((AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register\r
+#define AT91C_CAN_TIMESTP ((AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register\r
+#define AT91C_CAN_MR ((AT91_REG *) 0xFFFD0000) // (CAN) Mode Register\r
+#define AT91C_CAN_IDR ((AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register\r
+#define AT91C_CAN_ACR ((AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register\r
+#define AT91C_CAN_TIM ((AT91_REG *) 0xFFFD0018) // (CAN) Timer Register\r
+#define AT91C_CAN_SR ((AT91_REG *) 0xFFFD0010) // (CAN) Status Register\r
+#define AT91C_CAN_BR ((AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register\r
+#define AT91C_CAN_VR ((AT91_REG *) 0xFFFD00FC) // (CAN) Version Register\r
+// ========== Register definition for EMAC peripheral ========== \r
+#define AT91C_EMAC_ISR ((AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register\r
+#define AT91C_EMAC_SA4H ((AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes\r
+#define AT91C_EMAC_SA1L ((AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes\r
+#define AT91C_EMAC_ELE ((AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register\r
+#define AT91C_EMAC_LCOL ((AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register\r
+#define AT91C_EMAC_RLE ((AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register\r
+#define AT91C_EMAC_WOL ((AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register\r
+#define AT91C_EMAC_DTF ((AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register\r
+#define AT91C_EMAC_TUND ((AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register\r
+#define AT91C_EMAC_NCR ((AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register\r
+#define AT91C_EMAC_SA4L ((AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes\r
+#define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register\r
+#define AT91C_EMAC_SA3L ((AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes\r
+#define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register\r
+#define AT91C_EMAC_IDR ((AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register\r
+#define AT91C_EMAC_RSE ((AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register\r
+#define AT91C_EMAC_ECOL ((AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register\r
+#define AT91C_EMAC_TID ((AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register\r
+#define AT91C_EMAC_HRB ((AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]\r
+#define AT91C_EMAC_TBQP ((AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer\r
+#define AT91C_EMAC_USRIO ((AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register\r
+#define AT91C_EMAC_PTR ((AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register\r
+#define AT91C_EMAC_SA2H ((AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes\r
+#define AT91C_EMAC_ROV ((AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register\r
+#define AT91C_EMAC_ALE ((AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register\r
+#define AT91C_EMAC_RJA ((AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register\r
+#define AT91C_EMAC_RBQP ((AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer\r
+#define AT91C_EMAC_TPF ((AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register\r
+#define AT91C_EMAC_NCFGR ((AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register\r
+#define AT91C_EMAC_HRT ((AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32]\r
+#define AT91C_EMAC_USF ((AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register\r
+#define AT91C_EMAC_FCSE ((AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register\r
+#define AT91C_EMAC_TPQ ((AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register\r
+#define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register\r
+#define AT91C_EMAC_FTO ((AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register\r
+#define AT91C_EMAC_REV ((AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register\r
+#define AT91C_EMAC_IMR ((AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register\r
+#define AT91C_EMAC_SCF ((AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register\r
+#define AT91C_EMAC_PFR ((AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register\r
+#define AT91C_EMAC_MCF ((AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register\r
+#define AT91C_EMAC_NSR ((AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register\r
+#define AT91C_EMAC_SA2L ((AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes\r
+#define AT91C_EMAC_FRO ((AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register\r
+#define AT91C_EMAC_IER ((AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register\r
+#define AT91C_EMAC_SA1H ((AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes\r
+#define AT91C_EMAC_CSE ((AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register\r
+#define AT91C_EMAC_SA3H ((AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes\r
+#define AT91C_EMAC_RRE ((AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register\r
+#define AT91C_EMAC_STE ((AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register\r
+// ========== Register definition for PDC_ADC peripheral ========== \r
+#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register\r
+#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register\r
+#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register\r
+#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register\r
+#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register\r
+#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register\r
+#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register\r
+#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register\r
+#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register\r
+#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register\r
+// ========== Register definition for ADC peripheral ========== \r
+#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2\r
+#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3\r
+#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0\r
+#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5\r
+#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register\r
+#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register\r
+#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4\r
+#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1\r
+#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register\r
+#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register\r
+#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register\r
+#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7\r
+#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6\r
+#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register\r
+#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register\r
+#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register\r
+#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register\r
+#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register\r
+// ========== Register definition for PDC_AES peripheral ========== \r
+#define AT91C_AES_TPR ((AT91_REG *) 0xFFFA4108) // (PDC_AES) Transmit Pointer Register\r
+#define AT91C_AES_PTCR ((AT91_REG *) 0xFFFA4120) // (PDC_AES) PDC Transfer Control Register\r
+#define AT91C_AES_RNPR ((AT91_REG *) 0xFFFA4110) // (PDC_AES) Receive Next Pointer Register\r
+#define AT91C_AES_TNCR ((AT91_REG *) 0xFFFA411C) // (PDC_AES) Transmit Next Counter Register\r
+#define AT91C_AES_TCR ((AT91_REG *) 0xFFFA410C) // (PDC_AES) Transmit Counter Register\r
+#define AT91C_AES_RCR ((AT91_REG *) 0xFFFA4104) // (PDC_AES) Receive Counter Register\r
+#define AT91C_AES_RNCR ((AT91_REG *) 0xFFFA4114) // (PDC_AES) Receive Next Counter Register\r
+#define AT91C_AES_TNPR ((AT91_REG *) 0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register\r
+#define AT91C_AES_RPR ((AT91_REG *) 0xFFFA4100) // (PDC_AES) Receive Pointer Register\r
+#define AT91C_AES_PTSR ((AT91_REG *) 0xFFFA4124) // (PDC_AES) PDC Transfer Status Register\r
+// ========== Register definition for AES peripheral ========== \r
+#define AT91C_AES_IVxR ((AT91_REG *) 0xFFFA4060) // (AES) Initialization Vector x Register\r
+#define AT91C_AES_MR ((AT91_REG *) 0xFFFA4004) // (AES) Mode Register\r
+#define AT91C_AES_VR ((AT91_REG *) 0xFFFA40FC) // (AES) AES Version Register\r
+#define AT91C_AES_ODATAxR ((AT91_REG *) 0xFFFA4050) // (AES) Output Data x Register\r
+#define AT91C_AES_IDATAxR ((AT91_REG *) 0xFFFA4040) // (AES) Input Data x Register\r
+#define AT91C_AES_CR ((AT91_REG *) 0xFFFA4000) // (AES) Control Register\r
+#define AT91C_AES_IDR ((AT91_REG *) 0xFFFA4014) // (AES) Interrupt Disable Register\r
+#define AT91C_AES_IMR ((AT91_REG *) 0xFFFA4018) // (AES) Interrupt Mask Register\r
+#define AT91C_AES_IER ((AT91_REG *) 0xFFFA4010) // (AES) Interrupt Enable Register\r
+#define AT91C_AES_KEYWxR ((AT91_REG *) 0xFFFA4020) // (AES) Key Word x Register\r
+#define AT91C_AES_ISR ((AT91_REG *) 0xFFFA401C) // (AES) Interrupt Status Register\r
+// ========== Register definition for PDC_TDES peripheral ========== \r
+#define AT91C_TDES_RNCR ((AT91_REG *) 0xFFFA8114) // (PDC_TDES) Receive Next Counter Register\r
+#define AT91C_TDES_TCR ((AT91_REG *) 0xFFFA810C) // (PDC_TDES) Transmit Counter Register\r
+#define AT91C_TDES_RCR ((AT91_REG *) 0xFFFA8104) // (PDC_TDES) Receive Counter Register\r
+#define AT91C_TDES_TNPR ((AT91_REG *) 0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register\r
+#define AT91C_TDES_RNPR ((AT91_REG *) 0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register\r
+#define AT91C_TDES_RPR ((AT91_REG *) 0xFFFA8100) // (PDC_TDES) Receive Pointer Register\r
+#define AT91C_TDES_TNCR ((AT91_REG *) 0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register\r
+#define AT91C_TDES_TPR ((AT91_REG *) 0xFFFA8108) // (PDC_TDES) Transmit Pointer Register\r
+#define AT91C_TDES_PTSR ((AT91_REG *) 0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register\r
+#define AT91C_TDES_PTCR ((AT91_REG *) 0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register\r
+// ========== Register definition for TDES peripheral ========== \r
+#define AT91C_TDES_KEY2WxR ((AT91_REG *) 0xFFFA8028) // (TDES) Key 2 Word x Register\r
+#define AT91C_TDES_KEY3WxR ((AT91_REG *) 0xFFFA8030) // (TDES) Key 3 Word x Register\r
+#define AT91C_TDES_IDR ((AT91_REG *) 0xFFFA8014) // (TDES) Interrupt Disable Register\r
+#define AT91C_TDES_VR ((AT91_REG *) 0xFFFA80FC) // (TDES) TDES Version Register\r
+#define AT91C_TDES_IVxR ((AT91_REG *) 0xFFFA8060) // (TDES) Initialization Vector x Register\r
+#define AT91C_TDES_ODATAxR ((AT91_REG *) 0xFFFA8050) // (TDES) Output Data x Register\r
+#define AT91C_TDES_IMR ((AT91_REG *) 0xFFFA8018) // (TDES) Interrupt Mask Register\r
+#define AT91C_TDES_MR ((AT91_REG *) 0xFFFA8004) // (TDES) Mode Register\r
+#define AT91C_TDES_CR ((AT91_REG *) 0xFFFA8000) // (TDES) Control Register\r
+#define AT91C_TDES_IER ((AT91_REG *) 0xFFFA8010) // (TDES) Interrupt Enable Register\r
+#define AT91C_TDES_ISR ((AT91_REG *) 0xFFFA801C) // (TDES) Interrupt Status Register\r
+#define AT91C_TDES_IDATAxR ((AT91_REG *) 0xFFFA8040) // (TDES) Input Data x Register\r
+#define AT91C_TDES_KEY1WxR ((AT91_REG *) 0xFFFA8020) // (TDES) Key 1 Word x Register\r
+\r
+// *****************************************************************************\r
+// PIO DEFINITIONS FOR AT91SAM7X256\r
+// *****************************************************************************\r
+#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0\r
+#define AT91C_PA0_RXD0 ((unsigned int) AT91C_PIO_PA0) // USART 0 Receive Data\r
+#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1\r
+#define AT91C_PA1_TXD0 ((unsigned int) AT91C_PIO_PA1) // USART 0 Transmit Data\r
+#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10\r
+#define AT91C_PA10_TWD ((unsigned int) AT91C_PIO_PA10) // TWI Two-wire Serial Data\r
+#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11\r
+#define AT91C_PA11_TWCK ((unsigned int) AT91C_PIO_PA11) // TWI Two-wire Serial Clock\r
+#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12\r
+#define AT91C_PA12_NPCS00 ((unsigned int) AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0\r
+#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13\r
+#define AT91C_PA13_NPCS01 ((unsigned int) AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1\r
+#define AT91C_PA13_PCK1 ((unsigned int) AT91C_PIO_PA13) // PMC Programmable Clock Output 1\r
+#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14\r
+#define AT91C_PA14_NPCS02 ((unsigned int) AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2\r
+#define AT91C_PA14_IRQ1 ((unsigned int) AT91C_PIO_PA14) // External Interrupt 1\r
+#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15\r
+#define AT91C_PA15_NPCS03 ((unsigned int) AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3\r
+#define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input\r
+#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16\r
+#define AT91C_PA16_MISO0 ((unsigned int) AT91C_PIO_PA16) // SPI 0 Master In Slave\r
+#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17\r
+#define AT91C_PA17_MOSI0 ((unsigned int) AT91C_PIO_PA17) // SPI 0 Master Out Slave\r
+#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18\r
+#define AT91C_PA18_SPCK0 ((unsigned int) AT91C_PIO_PA18) // SPI 0 Serial Clock\r
+#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19\r
+#define AT91C_PA19_CANRX ((unsigned int) AT91C_PIO_PA19) // CAN Receive\r
+#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2\r
+#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock\r
+#define AT91C_PA2_NPCS11 ((unsigned int) AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1\r
+#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20\r
+#define AT91C_PA20_CANTX ((unsigned int) AT91C_PIO_PA20) // CAN Transmit\r
+#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21\r
+#define AT91C_PA21_TF ((unsigned int) AT91C_PIO_PA21) // SSC Transmit Frame Sync\r
+#define AT91C_PA21_NPCS10 ((unsigned int) AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0\r
+#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22\r
+#define AT91C_PA22_TK ((unsigned int) AT91C_PIO_PA22) // SSC Transmit Clock\r
+#define AT91C_PA22_SPCK1 ((unsigned int) AT91C_PIO_PA22) // SPI 1 Serial Clock\r
+#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23\r
+#define AT91C_PA23_TD ((unsigned int) AT91C_PIO_PA23) // SSC Transmit data\r
+#define AT91C_PA23_MOSI1 ((unsigned int) AT91C_PIO_PA23) // SPI 1 Master Out Slave\r
+#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24\r
+#define AT91C_PA24_RD ((unsigned int) AT91C_PIO_PA24) // SSC Receive Data\r
+#define AT91C_PA24_MISO1 ((unsigned int) AT91C_PIO_PA24) // SPI 1 Master In Slave\r
+#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25\r
+#define AT91C_PA25_RK ((unsigned int) AT91C_PIO_PA25) // SSC Receive Clock\r
+#define AT91C_PA25_NPCS11 ((unsigned int) AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1\r
+#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26\r
+#define AT91C_PA26_RF ((unsigned int) AT91C_PIO_PA26) // SSC Receive Frame Sync\r
+#define AT91C_PA26_NPCS12 ((unsigned int) AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2\r
+#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27\r
+#define AT91C_PA27_DRXD ((unsigned int) AT91C_PIO_PA27) // DBGU Debug Receive Data\r
+#define AT91C_PA27_PCK3 ((unsigned int) AT91C_PIO_PA27) // PMC Programmable Clock Output 3\r
+#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28\r
+#define AT91C_PA28_DTXD ((unsigned int) AT91C_PIO_PA28) // DBGU Debug Transmit Data\r
+#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29\r
+#define AT91C_PA29_FIQ ((unsigned int) AT91C_PIO_PA29) // AIC Fast Interrupt Input\r
+#define AT91C_PA29_NPCS13 ((unsigned int) AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3\r
+#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3\r
+#define AT91C_PA3_RTS0 ((unsigned int) AT91C_PIO_PA3) // USART 0 Ready To Send\r
+#define AT91C_PA3_NPCS12 ((unsigned int) AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2\r
+#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30\r
+#define AT91C_PA30_IRQ0 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 0\r
+#define AT91C_PA30_PCK2 ((unsigned int) AT91C_PIO_PA30) // PMC Programmable Clock Output 2\r
+#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4\r
+#define AT91C_PA4_CTS0 ((unsigned int) AT91C_PIO_PA4) // USART 0 Clear To Send\r
+#define AT91C_PA4_NPCS13 ((unsigned int) AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3\r
+#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5\r
+#define AT91C_PA5_RXD1 ((unsigned int) AT91C_PIO_PA5) // USART 1 Receive Data\r
+#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6\r
+#define AT91C_PA6_TXD1 ((unsigned int) AT91C_PIO_PA6) // USART 1 Transmit Data\r
+#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7\r
+#define AT91C_PA7_SCK1 ((unsigned int) AT91C_PIO_PA7) // USART 1 Serial Clock\r
+#define AT91C_PA7_NPCS01 ((unsigned int) AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1\r
+#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8\r
+#define AT91C_PA8_RTS1 ((unsigned int) AT91C_PIO_PA8) // USART 1 Ready To Send\r
+#define AT91C_PA8_NPCS02 ((unsigned int) AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2\r
+#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9\r
+#define AT91C_PA9_CTS1 ((unsigned int) AT91C_PIO_PA9) // USART 1 Clear To Send\r
+#define AT91C_PA9_NPCS03 ((unsigned int) AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3\r
+#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0\r
+#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock\r
+#define AT91C_PB0_PCK0 ((unsigned int) AT91C_PIO_PB0) // PMC Programmable Clock Output 0\r
+#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1\r
+#define AT91C_PB1_ETXEN ((unsigned int) AT91C_PIO_PB1) // Ethernet MAC Transmit Enable\r
+#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10\r
+#define AT91C_PB10_ETX2 ((unsigned int) AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2\r
+#define AT91C_PB10_NPCS11 ((unsigned int) AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1\r
+#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11\r
+#define AT91C_PB11_ETX3 ((unsigned int) AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3\r
+#define AT91C_PB11_NPCS12 ((unsigned int) AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2\r
+#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12\r
+#define AT91C_PB12_ETXER ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error\r
+#define AT91C_PB12_TCLK0 ((unsigned int) AT91C_PIO_PB12) // Timer Counter 0 external clock input\r
+#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13\r
+#define AT91C_PB13_ERX2 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Receive Data 2\r
+#define AT91C_PB13_NPCS01 ((unsigned int) AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1\r
+#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14\r
+#define AT91C_PB14_ERX3 ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Receive Data 3\r
+#define AT91C_PB14_NPCS02 ((unsigned int) AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2\r
+#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15\r
+#define AT91C_PB15_ERXDV ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid\r
+#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16\r
+#define AT91C_PB16_ECOL ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Collision Detected\r
+#define AT91C_PB16_NPCS13 ((unsigned int) AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3\r
+#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17\r
+#define AT91C_PB17_ERXCK ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Clock\r
+#define AT91C_PB17_NPCS03 ((unsigned int) AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3\r
+#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18\r
+#define AT91C_PB18_EF100 ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec\r
+#define AT91C_PB18_ADTRG ((unsigned int) AT91C_PIO_PB18) // ADC External Trigger\r
+#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19\r
+#define AT91C_PB19_PWM0 ((unsigned int) AT91C_PIO_PB19) // PWM Channel 0\r
+#define AT91C_PB19_TCLK1 ((unsigned int) AT91C_PIO_PB19) // Timer Counter 1 external clock input\r
+#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2\r
+#define AT91C_PB2_ETX0 ((unsigned int) AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0\r
+#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20\r
+#define AT91C_PB20_PWM1 ((unsigned int) AT91C_PIO_PB20) // PWM Channel 1\r
+#define AT91C_PB20_PCK0 ((unsigned int) AT91C_PIO_PB20) // PMC Programmable Clock Output 0\r
+#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21\r
+#define AT91C_PB21_PWM2 ((unsigned int) AT91C_PIO_PB21) // PWM Channel 2\r
+#define AT91C_PB21_PCK1 ((unsigned int) AT91C_PIO_PB21) // PMC Programmable Clock Output 1\r
+#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22\r
+#define AT91C_PB22_PWM3 ((unsigned int) AT91C_PIO_PB22) // PWM Channel 3\r
+#define AT91C_PB22_PCK2 ((unsigned int) AT91C_PIO_PB22) // PMC Programmable Clock Output 2\r
+#define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23\r
+#define AT91C_PB23_TIOA0 ((unsigned int) AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A\r
+#define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect\r
+#define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24\r
+#define AT91C_PB24_TIOB0 ((unsigned int) AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B\r
+#define AT91C_PB24_DSR1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Data Set ready\r
+#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25\r
+#define AT91C_PB25_TIOA1 ((unsigned int) AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A\r
+#define AT91C_PB25_DTR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Terminal ready\r
+#define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26\r
+#define AT91C_PB26_TIOB1 ((unsigned int) AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B\r
+#define AT91C_PB26_RI1 ((unsigned int) AT91C_PIO_PB26) // USART 1 Ring Indicator\r
+#define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27\r
+#define AT91C_PB27_TIOA2 ((unsigned int) AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A\r
+#define AT91C_PB27_PWM0 ((unsigned int) AT91C_PIO_PB27) // PWM Channel 0\r
+#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28\r
+#define AT91C_PB28_TIOB2 ((unsigned int) AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B\r
+#define AT91C_PB28_PWM1 ((unsigned int) AT91C_PIO_PB28) // PWM Channel 1\r
+#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29\r
+#define AT91C_PB29_PCK1 ((unsigned int) AT91C_PIO_PB29) // PMC Programmable Clock Output 1\r
+#define AT91C_PB29_PWM2 ((unsigned int) AT91C_PIO_PB29) // PWM Channel 2\r
+#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3\r
+#define AT91C_PB3_ETX1 ((unsigned int) AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1\r
+#define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30\r
+#define AT91C_PB30_PCK2 ((unsigned int) AT91C_PIO_PB30) // PMC Programmable Clock Output 2\r
+#define AT91C_PB30_PWM3 ((unsigned int) AT91C_PIO_PB30) // PWM Channel 3\r
+#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4\r
+#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid\r
+#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5\r
+#define AT91C_PB5_ERX0 ((unsigned int) AT91C_PIO_PB5) // Ethernet MAC Receive Data 0\r
+#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6\r
+#define AT91C_PB6_ERX1 ((unsigned int) AT91C_PIO_PB6) // Ethernet MAC Receive Data 1\r
+#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7\r
+#define AT91C_PB7_ERXER ((unsigned int) AT91C_PIO_PB7) // Ethernet MAC Receive Error\r
+#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8\r
+#define AT91C_PB8_EMDC ((unsigned int) AT91C_PIO_PB8) // Ethernet MAC Management Data Clock\r
+#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9\r
+#define AT91C_PB9_EMDIO ((unsigned int) AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output\r
+\r
+// *****************************************************************************\r
+// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256\r
+// *****************************************************************************\r
+#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ)\r
+#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral\r
+#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller A\r
+#define AT91C_ID_PIOB ((unsigned int) 3) // Parallel IO Controller B\r
+#define AT91C_ID_SPI0 ((unsigned int) 4) // Serial Peripheral Interface 0\r
+#define AT91C_ID_SPI1 ((unsigned int) 5) // Serial Peripheral Interface 1\r
+#define AT91C_ID_US0 ((unsigned int) 6) // USART 0\r
+#define AT91C_ID_US1 ((unsigned int) 7) // USART 1\r
+#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller\r
+#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface\r
+#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller\r
+#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port\r
+#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0\r
+#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1\r
+#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2\r
+#define AT91C_ID_CAN ((unsigned int) 15) // Control Area Network Controller\r
+#define AT91C_ID_EMAC ((unsigned int) 16) // Ethernet MAC\r
+#define AT91C_ID_ADC ((unsigned int) 17) // Analog-to-Digital Converter\r
+#define AT91C_ID_AES ((unsigned int) 18) // Advanced Encryption Standard 128-bit\r
+#define AT91C_ID_TDES ((unsigned int) 19) // Triple Data Encryption Standard\r
+#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved\r
+#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved\r
+#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved\r
+#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved\r
+#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved\r
+#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved\r
+#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved\r
+#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved\r
+#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved\r
+#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved\r
+#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0)\r
+#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1)\r
+\r
+// *****************************************************************************\r
+// BASE ADDRESS DEFINITIONS FOR AT91SAM7X256\r
+// *****************************************************************************\r
+#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address\r
+#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address\r
+#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address\r
+#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address\r
+#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address\r
+#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address\r
+#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address\r
+#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address\r
+#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address\r
+#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address\r
+#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address\r
+#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address\r
+#define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address\r
+#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address\r
+#define AT91C_BASE_PDC_SPI1 ((AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address\r
+#define AT91C_BASE_SPI1 ((AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address\r
+#define AT91C_BASE_PDC_SPI0 ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address\r
+#define AT91C_BASE_SPI0 ((AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address\r
+#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address\r
+#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address\r
+#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address\r
+#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address\r
+#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address\r
+#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address\r
+#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address\r
+#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address\r
+#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address\r
+#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address\r
+#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address\r
+#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address\r
+#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address\r
+#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address\r
+#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address\r
+#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address\r
+#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address\r
+#define AT91C_BASE_CAN_MB0 ((AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address\r
+#define AT91C_BASE_CAN_MB1 ((AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address\r
+#define AT91C_BASE_CAN_MB2 ((AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address\r
+#define AT91C_BASE_CAN_MB3 ((AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address\r
+#define AT91C_BASE_CAN_MB4 ((AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address\r
+#define AT91C_BASE_CAN_MB5 ((AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address\r
+#define AT91C_BASE_CAN_MB6 ((AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address\r
+#define AT91C_BASE_CAN_MB7 ((AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address\r
+#define AT91C_BASE_CAN ((AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address\r
+#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address\r
+#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address\r
+#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address\r
+#define AT91C_BASE_PDC_AES ((AT91PS_PDC) 0xFFFA4100) // (PDC_AES) Base Address\r
+#define AT91C_BASE_AES ((AT91PS_AES) 0xFFFA4000) // (AES) Base Address\r
+#define AT91C_BASE_PDC_TDES ((AT91PS_PDC) 0xFFFA8100) // (PDC_TDES) Base Address\r
+#define AT91C_BASE_TDES ((AT91PS_TDES) 0xFFFA8000) // (TDES) Base Address\r
+\r
+// *****************************************************************************\r
+// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256\r
+// *****************************************************************************\r
+#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address\r
+#define AT91C_ISRAM_SIZE ((unsigned int) 0x00010000) // Internal SRAM size in byte (64 Kbyte)\r
+#define AT91C_IFLASH ((char *) 0x00100000) // Internal ROM base address\r
+#define AT91C_IFLASH_SIZE ((unsigned int) 0x00040000) // Internal ROM size in byte (256 Kbyte)\r
+#endif /* __IAR_SYSTEMS_ICC__ */\r
+\r
+#ifdef __IAR_SYSTEMS_ASM__\r
+\r
+// - Hardware register definition\r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR System Peripherals\r
+// - *****************************************************************************\r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Advanced Interrupt Controller\r
+// - *****************************************************************************\r
+// - -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- \r
+AT91C_AIC_PRIOR EQU (0x7 << 0) ;- (AIC) Priority Level\r
+AT91C_AIC_PRIOR_LOWEST EQU (0x0) ;- (AIC) Lowest priority level\r
+AT91C_AIC_PRIOR_HIGHEST EQU (0x7) ;- (AIC) Highest priority level\r
+AT91C_AIC_SRCTYPE EQU (0x3 << 5) ;- (AIC) Interrupt Source Type\r
+AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL EQU (0x0 << 5) ;- (AIC) Internal Sources Code Label High-level Sensitive\r
+AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL EQU (0x0 << 5) ;- (AIC) External Sources Code Label Low-level Sensitive\r
+AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE EQU (0x1 << 5) ;- (AIC) Internal Sources Code Label Positive Edge triggered\r
+AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE EQU (0x1 << 5) ;- (AIC) External Sources Code Label Negative Edge triggered\r
+AT91C_AIC_SRCTYPE_HIGH_LEVEL EQU (0x2 << 5) ;- (AIC) Internal Or External Sources Code Label High-level Sensitive\r
+AT91C_AIC_SRCTYPE_POSITIVE_EDGE EQU (0x3 << 5) ;- (AIC) Internal Or External Sources Code Label Positive Edge triggered\r
+// - -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- \r
+AT91C_AIC_NFIQ EQU (0x1 << 0) ;- (AIC) NFIQ Status\r
+AT91C_AIC_NIRQ EQU (0x1 << 1) ;- (AIC) NIRQ Status\r
+// - -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- \r
+AT91C_AIC_DCR_PROT EQU (0x1 << 0) ;- (AIC) Protection Mode\r
+AT91C_AIC_DCR_GMSK EQU (0x1 << 1) ;- (AIC) General Mask\r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Peripheral DMA Controller\r
+// - *****************************************************************************\r
+// - -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- \r
+AT91C_PDC_RXTEN EQU (0x1 << 0) ;- (PDC) Receiver Transfer Enable\r
+AT91C_PDC_RXTDIS EQU (0x1 << 1) ;- (PDC) Receiver Transfer Disable\r
+AT91C_PDC_TXTEN EQU (0x1 << 8) ;- (PDC) Transmitter Transfer Enable\r
+AT91C_PDC_TXTDIS EQU (0x1 << 9) ;- (PDC) Transmitter Transfer Disable\r
+// - -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- \r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Debug Unit\r
+// - *****************************************************************************\r
+// - -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- \r
+AT91C_US_RSTRX EQU (0x1 << 2) ;- (DBGU) Reset Receiver\r
+AT91C_US_RSTTX EQU (0x1 << 3) ;- (DBGU) Reset Transmitter\r
+AT91C_US_RXEN EQU (0x1 << 4) ;- (DBGU) Receiver Enable\r
+AT91C_US_RXDIS EQU (0x1 << 5) ;- (DBGU) Receiver Disable\r
+AT91C_US_TXEN EQU (0x1 << 6) ;- (DBGU) Transmitter Enable\r
+AT91C_US_TXDIS EQU (0x1 << 7) ;- (DBGU) Transmitter Disable\r
+AT91C_US_RSTSTA EQU (0x1 << 8) ;- (DBGU) Reset Status Bits\r
+// - -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- \r
+AT91C_US_PAR EQU (0x7 << 9) ;- (DBGU) Parity type\r
+AT91C_US_PAR_EVEN EQU (0x0 << 9) ;- (DBGU) Even Parity\r
+AT91C_US_PAR_ODD EQU (0x1 << 9) ;- (DBGU) Odd Parity\r
+AT91C_US_PAR_SPACE EQU (0x2 << 9) ;- (DBGU) Parity forced to 0 (Space)\r
+AT91C_US_PAR_MARK EQU (0x3 << 9) ;- (DBGU) Parity forced to 1 (Mark)\r
+AT91C_US_PAR_NONE EQU (0x4 << 9) ;- (DBGU) No Parity\r
+AT91C_US_PAR_MULTI_DROP EQU (0x6 << 9) ;- (DBGU) Multi-drop mode\r
+AT91C_US_CHMODE EQU (0x3 << 14) ;- (DBGU) Channel Mode\r
+AT91C_US_CHMODE_NORMAL EQU (0x0 << 14) ;- (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.\r
+AT91C_US_CHMODE_AUTO EQU (0x1 << 14) ;- (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.\r
+AT91C_US_CHMODE_LOCAL EQU (0x2 << 14) ;- (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.\r
+AT91C_US_CHMODE_REMOTE EQU (0x3 << 14) ;- (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.\r
+// - -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- \r
+AT91C_US_RXRDY EQU (0x1 << 0) ;- (DBGU) RXRDY Interrupt\r
+AT91C_US_TXRDY EQU (0x1 << 1) ;- (DBGU) TXRDY Interrupt\r
+AT91C_US_ENDRX EQU (0x1 << 3) ;- (DBGU) End of Receive Transfer Interrupt\r
+AT91C_US_ENDTX EQU (0x1 << 4) ;- (DBGU) End of Transmit Interrupt\r
+AT91C_US_OVRE EQU (0x1 << 5) ;- (DBGU) Overrun Interrupt\r
+AT91C_US_FRAME EQU (0x1 << 6) ;- (DBGU) Framing Error Interrupt\r
+AT91C_US_PARE EQU (0x1 << 7) ;- (DBGU) Parity Error Interrupt\r
+AT91C_US_TXEMPTY EQU (0x1 << 9) ;- (DBGU) TXEMPTY Interrupt\r
+AT91C_US_TXBUFE EQU (0x1 << 11) ;- (DBGU) TXBUFE Interrupt\r
+AT91C_US_RXBUFF EQU (0x1 << 12) ;- (DBGU) RXBUFF Interrupt\r
+AT91C_US_COMM_TX EQU (0x1 << 30) ;- (DBGU) COMM_TX Interrupt\r
+AT91C_US_COMM_RX EQU (0x1 << 31) ;- (DBGU) COMM_RX Interrupt\r
+// - -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- \r
+// - -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- \r
+// - -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- \r
+// - -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- \r
+AT91C_US_FORCE_NTRST EQU (0x1 << 0) ;- (DBGU) Force NTRST in JTAG\r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Parallel Input Output Controler\r
+// - *****************************************************************************\r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Clock Generator Controler\r
+// - *****************************************************************************\r
+// - -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- \r
+AT91C_CKGR_MOSCEN EQU (0x1 << 0) ;- (CKGR) Main Oscillator Enable\r
+AT91C_CKGR_OSCBYPASS EQU (0x1 << 1) ;- (CKGR) Main Oscillator Bypass\r
+AT91C_CKGR_OSCOUNT EQU (0xFF << 8) ;- (CKGR) Main Oscillator Start-up Time\r
+// - -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- \r
+AT91C_CKGR_MAINF EQU (0xFFFF << 0) ;- (CKGR) Main Clock Frequency\r
+AT91C_CKGR_MAINRDY EQU (0x1 << 16) ;- (CKGR) Main Clock Ready\r
+// - -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- \r
+AT91C_CKGR_DIV EQU (0xFF << 0) ;- (CKGR) Divider Selected\r
+AT91C_CKGR_DIV_0 EQU (0x0) ;- (CKGR) Divider output is 0\r
+AT91C_CKGR_DIV_BYPASS EQU (0x1) ;- (CKGR) Divider is bypassed\r
+AT91C_CKGR_PLLCOUNT EQU (0x3F << 8) ;- (CKGR) PLL Counter\r
+AT91C_CKGR_OUT EQU (0x3 << 14) ;- (CKGR) PLL Output Frequency Range\r
+AT91C_CKGR_OUT_0 EQU (0x0 << 14) ;- (CKGR) Please refer to the PLL datasheet\r
+AT91C_CKGR_OUT_1 EQU (0x1 << 14) ;- (CKGR) Please refer to the PLL datasheet\r
+AT91C_CKGR_OUT_2 EQU (0x2 << 14) ;- (CKGR) Please refer to the PLL datasheet\r
+AT91C_CKGR_OUT_3 EQU (0x3 << 14) ;- (CKGR) Please refer to the PLL datasheet\r
+AT91C_CKGR_MUL EQU (0x7FF << 16) ;- (CKGR) PLL Multiplier\r
+AT91C_CKGR_USBDIV EQU (0x3 << 28) ;- (CKGR) Divider for USB Clocks\r
+AT91C_CKGR_USBDIV_0 EQU (0x0 << 28) ;- (CKGR) Divider output is PLL clock output\r
+AT91C_CKGR_USBDIV_1 EQU (0x1 << 28) ;- (CKGR) Divider output is PLL clock output divided by 2\r
+AT91C_CKGR_USBDIV_2 EQU (0x2 << 28) ;- (CKGR) Divider output is PLL clock output divided by 4\r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Power Management Controler\r
+// - *****************************************************************************\r
+// - -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- \r
+AT91C_PMC_PCK EQU (0x1 << 0) ;- (PMC) Processor Clock\r
+AT91C_PMC_UDP EQU (0x1 << 7) ;- (PMC) USB Device Port Clock\r
+AT91C_PMC_PCK0 EQU (0x1 << 8) ;- (PMC) Programmable Clock Output\r
+AT91C_PMC_PCK1 EQU (0x1 << 9) ;- (PMC) Programmable Clock Output\r
+AT91C_PMC_PCK2 EQU (0x1 << 10) ;- (PMC) Programmable Clock Output\r
+AT91C_PMC_PCK3 EQU (0x1 << 11) ;- (PMC) Programmable Clock Output\r
+// - -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- \r
+// - -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- \r
+// - -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- \r
+// - -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- \r
+// - -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- \r
+// - -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- \r
+AT91C_PMC_CSS EQU (0x3 << 0) ;- (PMC) Programmable Clock Selection\r
+AT91C_PMC_CSS_SLOW_CLK EQU (0x0) ;- (PMC) Slow Clock is selected\r
+AT91C_PMC_CSS_MAIN_CLK EQU (0x1) ;- (PMC) Main Clock is selected\r
+AT91C_PMC_CSS_PLL_CLK EQU (0x3) ;- (PMC) Clock from PLL is selected\r
+AT91C_PMC_PRES EQU (0x7 << 2) ;- (PMC) Programmable Clock Prescaler\r
+AT91C_PMC_PRES_CLK EQU (0x0 << 2) ;- (PMC) Selected clock\r
+AT91C_PMC_PRES_CLK_2 EQU (0x1 << 2) ;- (PMC) Selected clock divided by 2\r
+AT91C_PMC_PRES_CLK_4 EQU (0x2 << 2) ;- (PMC) Selected clock divided by 4\r
+AT91C_PMC_PRES_CLK_8 EQU (0x3 << 2) ;- (PMC) Selected clock divided by 8\r
+AT91C_PMC_PRES_CLK_16 EQU (0x4 << 2) ;- (PMC) Selected clock divided by 16\r
+AT91C_PMC_PRES_CLK_32 EQU (0x5 << 2) ;- (PMC) Selected clock divided by 32\r
+AT91C_PMC_PRES_CLK_64 EQU (0x6 << 2) ;- (PMC) Selected clock divided by 64\r
+// - -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- \r
+// - -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- \r
+AT91C_PMC_MOSCS EQU (0x1 << 0) ;- (PMC) MOSC Status/Enable/Disable/Mask\r
+AT91C_PMC_LOCK EQU (0x1 << 2) ;- (PMC) PLL Status/Enable/Disable/Mask\r
+AT91C_PMC_MCKRDY EQU (0x1 << 3) ;- (PMC) MCK_RDY Status/Enable/Disable/Mask\r
+AT91C_PMC_PCK0RDY EQU (0x1 << 8) ;- (PMC) PCK0_RDY Status/Enable/Disable/Mask\r
+AT91C_PMC_PCK1RDY EQU (0x1 << 9) ;- (PMC) PCK1_RDY Status/Enable/Disable/Mask\r
+AT91C_PMC_PCK2RDY EQU (0x1 << 10) ;- (PMC) PCK2_RDY Status/Enable/Disable/Mask\r
+AT91C_PMC_PCK3RDY EQU (0x1 << 11) ;- (PMC) PCK3_RDY Status/Enable/Disable/Mask\r
+// - -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- \r
+// - -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- \r
+// - -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- \r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Reset Controller Interface\r
+// - *****************************************************************************\r
+// - -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- \r
+AT91C_RSTC_PROCRST EQU (0x1 << 0) ;- (RSTC) Processor Reset\r
+AT91C_RSTC_PERRST EQU (0x1 << 2) ;- (RSTC) Peripheral Reset\r
+AT91C_RSTC_EXTRST EQU (0x1 << 3) ;- (RSTC) External Reset\r
+AT91C_RSTC_KEY EQU (0xFF << 24) ;- (RSTC) Password\r
+// - -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- \r
+AT91C_RSTC_URSTS EQU (0x1 << 0) ;- (RSTC) User Reset Status\r
+AT91C_RSTC_BODSTS EQU (0x1 << 1) ;- (RSTC) Brownout Detection Status\r
+AT91C_RSTC_RSTTYP EQU (0x7 << 8) ;- (RSTC) Reset Type\r
+AT91C_RSTC_RSTTYP_POWERUP EQU (0x0 << 8) ;- (RSTC) Power-up Reset. VDDCORE rising.\r
+AT91C_RSTC_RSTTYP_WAKEUP EQU (0x1 << 8) ;- (RSTC) WakeUp Reset. VDDCORE rising.\r
+AT91C_RSTC_RSTTYP_WATCHDOG EQU (0x2 << 8) ;- (RSTC) Watchdog Reset. Watchdog overflow occured.\r
+AT91C_RSTC_RSTTYP_SOFTWARE EQU (0x3 << 8) ;- (RSTC) Software Reset. Processor reset required by the software.\r
+AT91C_RSTC_RSTTYP_USER EQU (0x4 << 8) ;- (RSTC) User Reset. NRST pin detected low.\r
+AT91C_RSTC_RSTTYP_BROWNOUT EQU (0x5 << 8) ;- (RSTC) Brownout Reset occured.\r
+AT91C_RSTC_NRSTL EQU (0x1 << 16) ;- (RSTC) NRST pin level\r
+AT91C_RSTC_SRCMP EQU (0x1 << 17) ;- (RSTC) Software Reset Command in Progress.\r
+// - -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- \r
+AT91C_RSTC_URSTEN EQU (0x1 << 0) ;- (RSTC) User Reset Enable\r
+AT91C_RSTC_URSTIEN EQU (0x1 << 4) ;- (RSTC) User Reset Interrupt Enable\r
+AT91C_RSTC_ERSTL EQU (0xF << 8) ;- (RSTC) User Reset Enable\r
+AT91C_RSTC_BODIEN EQU (0x1 << 16) ;- (RSTC) Brownout Detection Interrupt Enable\r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface\r
+// - *****************************************************************************\r
+// - -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- \r
+AT91C_RTTC_RTPRES EQU (0xFFFF << 0) ;- (RTTC) Real-time Timer Prescaler Value\r
+AT91C_RTTC_ALMIEN EQU (0x1 << 16) ;- (RTTC) Alarm Interrupt Enable\r
+AT91C_RTTC_RTTINCIEN EQU (0x1 << 17) ;- (RTTC) Real Time Timer Increment Interrupt Enable\r
+AT91C_RTTC_RTTRST EQU (0x1 << 18) ;- (RTTC) Real Time Timer Restart\r
+// - -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- \r
+AT91C_RTTC_ALMV EQU (0x0 << 0) ;- (RTTC) Alarm Value\r
+// - -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- \r
+AT91C_RTTC_CRTV EQU (0x0 << 0) ;- (RTTC) Current Real-time Value\r
+// - -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- \r
+AT91C_RTTC_ALMS EQU (0x1 << 0) ;- (RTTC) Real-time Alarm Status\r
+AT91C_RTTC_RTTINC EQU (0x1 << 1) ;- (RTTC) Real-time Timer Increment\r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface\r
+// - *****************************************************************************\r
+// - -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- \r
+AT91C_PITC_PIV EQU (0xFFFFF << 0) ;- (PITC) Periodic Interval Value\r
+AT91C_PITC_PITEN EQU (0x1 << 24) ;- (PITC) Periodic Interval Timer Enabled\r
+AT91C_PITC_PITIEN EQU (0x1 << 25) ;- (PITC) Periodic Interval Timer Interrupt Enable\r
+// - -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- \r
+AT91C_PITC_PITS EQU (0x1 << 0) ;- (PITC) Periodic Interval Timer Status\r
+// - -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- \r
+AT91C_PITC_CPIV EQU (0xFFFFF << 0) ;- (PITC) Current Periodic Interval Value\r
+AT91C_PITC_PICNT EQU (0xFFF << 20) ;- (PITC) Periodic Interval Counter\r
+// - -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- \r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface\r
+// - *****************************************************************************\r
+// - -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- \r
+AT91C_WDTC_WDRSTT EQU (0x1 << 0) ;- (WDTC) Watchdog Restart\r
+AT91C_WDTC_KEY EQU (0xFF << 24) ;- (WDTC) Watchdog KEY Password\r
+// - -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- \r
+AT91C_WDTC_WDV EQU (0xFFF << 0) ;- (WDTC) Watchdog Timer Restart\r
+AT91C_WDTC_WDFIEN EQU (0x1 << 12) ;- (WDTC) Watchdog Fault Interrupt Enable\r
+AT91C_WDTC_WDRSTEN EQU (0x1 << 13) ;- (WDTC) Watchdog Reset Enable\r
+AT91C_WDTC_WDRPROC EQU (0x1 << 14) ;- (WDTC) Watchdog Timer Restart\r
+AT91C_WDTC_WDDIS EQU (0x1 << 15) ;- (WDTC) Watchdog Disable\r
+AT91C_WDTC_WDD EQU (0xFFF << 16) ;- (WDTC) Watchdog Delta Value\r
+AT91C_WDTC_WDDBGHLT EQU (0x1 << 28) ;- (WDTC) Watchdog Debug Halt\r
+AT91C_WDTC_WDIDLEHLT EQU (0x1 << 29) ;- (WDTC) Watchdog Idle Halt\r
+// - -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- \r
+AT91C_WDTC_WDUNF EQU (0x1 << 0) ;- (WDTC) Watchdog Underflow\r
+AT91C_WDTC_WDERR EQU (0x1 << 1) ;- (WDTC) Watchdog Error\r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface\r
+// - *****************************************************************************\r
+// - -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- \r
+AT91C_VREG_PSTDBY EQU (0x1 << 0) ;- (VREG) Voltage Regulator Power Standby Mode\r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Memory Controller Interface\r
+// - *****************************************************************************\r
+// - -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- \r
+AT91C_MC_RCB EQU (0x1 << 0) ;- (MC) Remap Command Bit\r
+// - -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- \r
+AT91C_MC_UNDADD EQU (0x1 << 0) ;- (MC) Undefined Addess Abort Status\r
+AT91C_MC_MISADD EQU (0x1 << 1) ;- (MC) Misaligned Addess Abort Status\r
+AT91C_MC_ABTSZ EQU (0x3 << 8) ;- (MC) Abort Size Status\r
+AT91C_MC_ABTSZ_BYTE EQU (0x0 << 8) ;- (MC) Byte\r
+AT91C_MC_ABTSZ_HWORD EQU (0x1 << 8) ;- (MC) Half-word\r
+AT91C_MC_ABTSZ_WORD EQU (0x2 << 8) ;- (MC) Word\r
+AT91C_MC_ABTTYP EQU (0x3 << 10) ;- (MC) Abort Type Status\r
+AT91C_MC_ABTTYP_DATAR EQU (0x0 << 10) ;- (MC) Data Read\r
+AT91C_MC_ABTTYP_DATAW EQU (0x1 << 10) ;- (MC) Data Write\r
+AT91C_MC_ABTTYP_FETCH EQU (0x2 << 10) ;- (MC) Code Fetch\r
+AT91C_MC_MST0 EQU (0x1 << 16) ;- (MC) Master 0 Abort Source\r
+AT91C_MC_MST1 EQU (0x1 << 17) ;- (MC) Master 1 Abort Source\r
+AT91C_MC_SVMST0 EQU (0x1 << 24) ;- (MC) Saved Master 0 Abort Source\r
+AT91C_MC_SVMST1 EQU (0x1 << 25) ;- (MC) Saved Master 1 Abort Source\r
+// - -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- \r
+AT91C_MC_FRDY EQU (0x1 << 0) ;- (MC) Flash Ready\r
+AT91C_MC_LOCKE EQU (0x1 << 2) ;- (MC) Lock Error\r
+AT91C_MC_PROGE EQU (0x1 << 3) ;- (MC) Programming Error\r
+AT91C_MC_NEBP EQU (0x1 << 7) ;- (MC) No Erase Before Programming\r
+AT91C_MC_FWS EQU (0x3 << 8) ;- (MC) Flash Wait State\r
+AT91C_MC_FWS_0FWS EQU (0x0 << 8) ;- (MC) 1 cycle for Read, 2 for Write operations\r
+AT91C_MC_FWS_1FWS EQU (0x1 << 8) ;- (MC) 2 cycles for Read, 3 for Write operations\r
+AT91C_MC_FWS_2FWS EQU (0x2 << 8) ;- (MC) 3 cycles for Read, 4 for Write operations\r
+AT91C_MC_FWS_3FWS EQU (0x3 << 8) ;- (MC) 4 cycles for Read, 4 for Write operations\r
+AT91C_MC_FMCN EQU (0xFF << 16) ;- (MC) Flash Microsecond Cycle Number\r
+// - -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- \r
+AT91C_MC_FCMD EQU (0xF << 0) ;- (MC) Flash Command\r
+AT91C_MC_FCMD_START_PROG EQU (0x1) ;- (MC) Starts the programming of th epage specified by PAGEN.\r
+AT91C_MC_FCMD_LOCK EQU (0x2) ;- (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.\r
+AT91C_MC_FCMD_PROG_AND_LOCK EQU (0x3) ;- (MC) The lock sequence automatically happens after the programming sequence is completed.\r
+AT91C_MC_FCMD_UNLOCK EQU (0x4) ;- (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.\r
+AT91C_MC_FCMD_ERASE_ALL EQU (0x8) ;- (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.\r
+AT91C_MC_FCMD_SET_GP_NVM EQU (0xB) ;- (MC) Set General Purpose NVM bits.\r
+AT91C_MC_FCMD_CLR_GP_NVM EQU (0xD) ;- (MC) Clear General Purpose NVM bits.\r
+AT91C_MC_FCMD_SET_SECURITY EQU (0xF) ;- (MC) Set Security Bit.\r
+AT91C_MC_PAGEN EQU (0x3FF << 8) ;- (MC) Page Number\r
+AT91C_MC_KEY EQU (0xFF << 24) ;- (MC) Writing Protect Key\r
+// - -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- \r
+AT91C_MC_SECURITY EQU (0x1 << 4) ;- (MC) Security Bit Status\r
+AT91C_MC_GPNVM0 EQU (0x1 << 8) ;- (MC) Sector 0 Lock Status\r
+AT91C_MC_GPNVM1 EQU (0x1 << 9) ;- (MC) Sector 1 Lock Status\r
+AT91C_MC_GPNVM2 EQU (0x1 << 10) ;- (MC) Sector 2 Lock Status\r
+AT91C_MC_GPNVM3 EQU (0x1 << 11) ;- (MC) Sector 3 Lock Status\r
+AT91C_MC_GPNVM4 EQU (0x1 << 12) ;- (MC) Sector 4 Lock Status\r
+AT91C_MC_GPNVM5 EQU (0x1 << 13) ;- (MC) Sector 5 Lock Status\r
+AT91C_MC_GPNVM6 EQU (0x1 << 14) ;- (MC) Sector 6 Lock Status\r
+AT91C_MC_GPNVM7 EQU (0x1 << 15) ;- (MC) Sector 7 Lock Status\r
+AT91C_MC_LOCKS0 EQU (0x1 << 16) ;- (MC) Sector 0 Lock Status\r
+AT91C_MC_LOCKS1 EQU (0x1 << 17) ;- (MC) Sector 1 Lock Status\r
+AT91C_MC_LOCKS2 EQU (0x1 << 18) ;- (MC) Sector 2 Lock Status\r
+AT91C_MC_LOCKS3 EQU (0x1 << 19) ;- (MC) Sector 3 Lock Status\r
+AT91C_MC_LOCKS4 EQU (0x1 << 20) ;- (MC) Sector 4 Lock Status\r
+AT91C_MC_LOCKS5 EQU (0x1 << 21) ;- (MC) Sector 5 Lock Status\r
+AT91C_MC_LOCKS6 EQU (0x1 << 22) ;- (MC) Sector 6 Lock Status\r
+AT91C_MC_LOCKS7 EQU (0x1 << 23) ;- (MC) Sector 7 Lock Status\r
+AT91C_MC_LOCKS8 EQU (0x1 << 24) ;- (MC) Sector 8 Lock Status\r
+AT91C_MC_LOCKS9 EQU (0x1 << 25) ;- (MC) Sector 9 Lock Status\r
+AT91C_MC_LOCKS10 EQU (0x1 << 26) ;- (MC) Sector 10 Lock Status\r
+AT91C_MC_LOCKS11 EQU (0x1 << 27) ;- (MC) Sector 11 Lock Status\r
+AT91C_MC_LOCKS12 EQU (0x1 << 28) ;- (MC) Sector 12 Lock Status\r
+AT91C_MC_LOCKS13 EQU (0x1 << 29) ;- (MC) Sector 13 Lock Status\r
+AT91C_MC_LOCKS14 EQU (0x1 << 30) ;- (MC) Sector 14 Lock Status\r
+AT91C_MC_LOCKS15 EQU (0x1 << 31) ;- (MC) Sector 15 Lock Status\r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Serial Parallel Interface\r
+// - *****************************************************************************\r
+// - -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- \r
+AT91C_SPI_SPIEN EQU (0x1 << 0) ;- (SPI) SPI Enable\r
+AT91C_SPI_SPIDIS EQU (0x1 << 1) ;- (SPI) SPI Disable\r
+AT91C_SPI_SWRST EQU (0x1 << 7) ;- (SPI) SPI Software reset\r
+AT91C_SPI_LASTXFER EQU (0x1 << 24) ;- (SPI) SPI Last Transfer\r
+// - -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- \r
+AT91C_SPI_MSTR EQU (0x1 << 0) ;- (SPI) Master/Slave Mode\r
+AT91C_SPI_PS EQU (0x1 << 1) ;- (SPI) Peripheral Select\r
+AT91C_SPI_PS_FIXED EQU (0x0 << 1) ;- (SPI) Fixed Peripheral Select\r
+AT91C_SPI_PS_VARIABLE EQU (0x1 << 1) ;- (SPI) Variable Peripheral Select\r
+AT91C_SPI_PCSDEC EQU (0x1 << 2) ;- (SPI) Chip Select Decode\r
+AT91C_SPI_FDIV EQU (0x1 << 3) ;- (SPI) Clock Selection\r
+AT91C_SPI_MODFDIS EQU (0x1 << 4) ;- (SPI) Mode Fault Detection\r
+AT91C_SPI_LLB EQU (0x1 << 7) ;- (SPI) Clock Selection\r
+AT91C_SPI_PCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select\r
+AT91C_SPI_DLYBCS EQU (0xFF << 24) ;- (SPI) Delay Between Chip Selects\r
+// - -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- \r
+AT91C_SPI_RD EQU (0xFFFF << 0) ;- (SPI) Receive Data\r
+AT91C_SPI_RPCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status\r
+// - -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- \r
+AT91C_SPI_TD EQU (0xFFFF << 0) ;- (SPI) Transmit Data\r
+AT91C_SPI_TPCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status\r
+// - -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- \r
+AT91C_SPI_RDRF EQU (0x1 << 0) ;- (SPI) Receive Data Register Full\r
+AT91C_SPI_TDRE EQU (0x1 << 1) ;- (SPI) Transmit Data Register Empty\r
+AT91C_SPI_MODF EQU (0x1 << 2) ;- (SPI) Mode Fault Error\r
+AT91C_SPI_OVRES EQU (0x1 << 3) ;- (SPI) Overrun Error Status\r
+AT91C_SPI_ENDRX EQU (0x1 << 4) ;- (SPI) End of Receiver Transfer\r
+AT91C_SPI_ENDTX EQU (0x1 << 5) ;- (SPI) End of Receiver Transfer\r
+AT91C_SPI_RXBUFF EQU (0x1 << 6) ;- (SPI) RXBUFF Interrupt\r
+AT91C_SPI_TXBUFE EQU (0x1 << 7) ;- (SPI) TXBUFE Interrupt\r
+AT91C_SPI_NSSR EQU (0x1 << 8) ;- (SPI) NSSR Interrupt\r
+AT91C_SPI_TXEMPTY EQU (0x1 << 9) ;- (SPI) TXEMPTY Interrupt\r
+AT91C_SPI_SPIENS EQU (0x1 << 16) ;- (SPI) Enable Status\r
+// - -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- \r
+// - -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- \r
+// - -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- \r
+// - -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- \r
+AT91C_SPI_CPOL EQU (0x1 << 0) ;- (SPI) Clock Polarity\r
+AT91C_SPI_NCPHA EQU (0x1 << 1) ;- (SPI) Clock Phase\r
+AT91C_SPI_CSAAT EQU (0x1 << 3) ;- (SPI) Chip Select Active After Transfer\r
+AT91C_SPI_BITS EQU (0xF << 4) ;- (SPI) Bits Per Transfer\r
+AT91C_SPI_BITS_8 EQU (0x0 << 4) ;- (SPI) 8 Bits Per transfer\r
+AT91C_SPI_BITS_9 EQU (0x1 << 4) ;- (SPI) 9 Bits Per transfer\r
+AT91C_SPI_BITS_10 EQU (0x2 << 4) ;- (SPI) 10 Bits Per transfer\r
+AT91C_SPI_BITS_11 EQU (0x3 << 4) ;- (SPI) 11 Bits Per transfer\r
+AT91C_SPI_BITS_12 EQU (0x4 << 4) ;- (SPI) 12 Bits Per transfer\r
+AT91C_SPI_BITS_13 EQU (0x5 << 4) ;- (SPI) 13 Bits Per transfer\r
+AT91C_SPI_BITS_14 EQU (0x6 << 4) ;- (SPI) 14 Bits Per transfer\r
+AT91C_SPI_BITS_15 EQU (0x7 << 4) ;- (SPI) 15 Bits Per transfer\r
+AT91C_SPI_BITS_16 EQU (0x8 << 4) ;- (SPI) 16 Bits Per transfer\r
+AT91C_SPI_SCBR EQU (0xFF << 8) ;- (SPI) Serial Clock Baud Rate\r
+AT91C_SPI_DLYBS EQU (0xFF << 16) ;- (SPI) Delay Before SPCK\r
+AT91C_SPI_DLYBCT EQU (0xFF << 24) ;- (SPI) Delay Between Consecutive Transfers\r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Usart\r
+// - *****************************************************************************\r
+// - -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- \r
+AT91C_US_STTBRK EQU (0x1 << 9) ;- (USART) Start Break\r
+AT91C_US_STPBRK EQU (0x1 << 10) ;- (USART) Stop Break\r
+AT91C_US_STTTO EQU (0x1 << 11) ;- (USART) Start Time-out\r
+AT91C_US_SENDA EQU (0x1 << 12) ;- (USART) Send Address\r
+AT91C_US_RSTIT EQU (0x1 << 13) ;- (USART) Reset Iterations\r
+AT91C_US_RSTNACK EQU (0x1 << 14) ;- (USART) Reset Non Acknowledge\r
+AT91C_US_RETTO EQU (0x1 << 15) ;- (USART) Rearm Time-out\r
+AT91C_US_DTREN EQU (0x1 << 16) ;- (USART) Data Terminal ready Enable\r
+AT91C_US_DTRDIS EQU (0x1 << 17) ;- (USART) Data Terminal ready Disable\r
+AT91C_US_RTSEN EQU (0x1 << 18) ;- (USART) Request to Send enable\r
+AT91C_US_RTSDIS EQU (0x1 << 19) ;- (USART) Request to Send Disable\r
+// - -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- \r
+AT91C_US_USMODE EQU (0xF << 0) ;- (USART) Usart mode\r
+AT91C_US_USMODE_NORMAL EQU (0x0) ;- (USART) Normal\r
+AT91C_US_USMODE_RS485 EQU (0x1) ;- (USART) RS485\r
+AT91C_US_USMODE_HWHSH EQU (0x2) ;- (USART) Hardware Handshaking\r
+AT91C_US_USMODE_MODEM EQU (0x3) ;- (USART) Modem\r
+AT91C_US_USMODE_ISO7816_0 EQU (0x4) ;- (USART) ISO7816 protocol: T = 0\r
+AT91C_US_USMODE_ISO7816_1 EQU (0x6) ;- (USART) ISO7816 protocol: T = 1\r
+AT91C_US_USMODE_IRDA EQU (0x8) ;- (USART) IrDA\r
+AT91C_US_USMODE_SWHSH EQU (0xC) ;- (USART) Software Handshaking\r
+AT91C_US_CLKS EQU (0x3 << 4) ;- (USART) Clock Selection (Baud Rate generator Input Clock\r
+AT91C_US_CLKS_CLOCK EQU (0x0 << 4) ;- (USART) Clock\r
+AT91C_US_CLKS_FDIV1 EQU (0x1 << 4) ;- (USART) fdiv1\r
+AT91C_US_CLKS_SLOW EQU (0x2 << 4) ;- (USART) slow_clock (ARM)\r
+AT91C_US_CLKS_EXT EQU (0x3 << 4) ;- (USART) External (SCK)\r
+AT91C_US_CHRL EQU (0x3 << 6) ;- (USART) Clock Selection (Baud Rate generator Input Clock\r
+AT91C_US_CHRL_5_BITS EQU (0x0 << 6) ;- (USART) Character Length: 5 bits\r
+AT91C_US_CHRL_6_BITS EQU (0x1 << 6) ;- (USART) Character Length: 6 bits\r
+AT91C_US_CHRL_7_BITS EQU (0x2 << 6) ;- (USART) Character Length: 7 bits\r
+AT91C_US_CHRL_8_BITS EQU (0x3 << 6) ;- (USART) Character Length: 8 bits\r
+AT91C_US_SYNC EQU (0x1 << 8) ;- (USART) Synchronous Mode Select\r
+AT91C_US_NBSTOP EQU (0x3 << 12) ;- (USART) Number of Stop bits\r
+AT91C_US_NBSTOP_1_BIT EQU (0x0 << 12) ;- (USART) 1 stop bit\r
+AT91C_US_NBSTOP_15_BIT EQU (0x1 << 12) ;- (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits\r
+AT91C_US_NBSTOP_2_BIT EQU (0x2 << 12) ;- (USART) 2 stop bits\r
+AT91C_US_MSBF EQU (0x1 << 16) ;- (USART) Bit Order\r
+AT91C_US_MODE9 EQU (0x1 << 17) ;- (USART) 9-bit Character length\r
+AT91C_US_CKLO EQU (0x1 << 18) ;- (USART) Clock Output Select\r
+AT91C_US_OVER EQU (0x1 << 19) ;- (USART) Over Sampling Mode\r
+AT91C_US_INACK EQU (0x1 << 20) ;- (USART) Inhibit Non Acknowledge\r
+AT91C_US_DSNACK EQU (0x1 << 21) ;- (USART) Disable Successive NACK\r
+AT91C_US_MAX_ITER EQU (0x1 << 24) ;- (USART) Number of Repetitions\r
+AT91C_US_FILTER EQU (0x1 << 28) ;- (USART) Receive Line Filter\r
+// - -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- \r
+AT91C_US_RXBRK EQU (0x1 << 2) ;- (USART) Break Received/End of Break\r
+AT91C_US_TIMEOUT EQU (0x1 << 8) ;- (USART) Receiver Time-out\r
+AT91C_US_ITERATION EQU (0x1 << 10) ;- (USART) Max number of Repetitions Reached\r
+AT91C_US_NACK EQU (0x1 << 13) ;- (USART) Non Acknowledge\r
+AT91C_US_RIIC EQU (0x1 << 16) ;- (USART) Ring INdicator Input Change Flag\r
+AT91C_US_DSRIC EQU (0x1 << 17) ;- (USART) Data Set Ready Input Change Flag\r
+AT91C_US_DCDIC EQU (0x1 << 18) ;- (USART) Data Carrier Flag\r
+AT91C_US_CTSIC EQU (0x1 << 19) ;- (USART) Clear To Send Input Change Flag\r
+// - -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- \r
+// - -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- \r
+// - -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- \r
+AT91C_US_RI EQU (0x1 << 20) ;- (USART) Image of RI Input\r
+AT91C_US_DSR EQU (0x1 << 21) ;- (USART) Image of DSR Input\r
+AT91C_US_DCD EQU (0x1 << 22) ;- (USART) Image of DCD Input\r
+AT91C_US_CTS EQU (0x1 << 23) ;- (USART) Image of CTS Input\r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface\r
+// - *****************************************************************************\r
+// - -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- \r
+AT91C_SSC_RXEN EQU (0x1 << 0) ;- (SSC) Receive Enable\r
+AT91C_SSC_RXDIS EQU (0x1 << 1) ;- (SSC) Receive Disable\r
+AT91C_SSC_TXEN EQU (0x1 << 8) ;- (SSC) Transmit Enable\r
+AT91C_SSC_TXDIS EQU (0x1 << 9) ;- (SSC) Transmit Disable\r
+AT91C_SSC_SWRST EQU (0x1 << 15) ;- (SSC) Software Reset\r
+// - -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- \r
+AT91C_SSC_CKS EQU (0x3 << 0) ;- (SSC) Receive/Transmit Clock Selection\r
+AT91C_SSC_CKS_DIV EQU (0x0) ;- (SSC) Divided Clock\r
+AT91C_SSC_CKS_TK EQU (0x1) ;- (SSC) TK Clock signal\r
+AT91C_SSC_CKS_RK EQU (0x2) ;- (SSC) RK pin\r
+AT91C_SSC_CKO EQU (0x7 << 2) ;- (SSC) Receive/Transmit Clock Output Mode Selection\r
+AT91C_SSC_CKO_NONE EQU (0x0 << 2) ;- (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only\r
+AT91C_SSC_CKO_CONTINOUS EQU (0x1 << 2) ;- (SSC) Continuous Receive/Transmit Clock RK pin: Output\r
+AT91C_SSC_CKO_DATA_TX EQU (0x2 << 2) ;- (SSC) Receive/Transmit Clock only during data transfers RK pin: Output\r
+AT91C_SSC_CKI EQU (0x1 << 5) ;- (SSC) Receive/Transmit Clock Inversion\r
+AT91C_SSC_START EQU (0xF << 8) ;- (SSC) Receive/Transmit Start Selection\r
+AT91C_SSC_START_CONTINOUS EQU (0x0 << 8) ;- (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.\r
+AT91C_SSC_START_TX EQU (0x1 << 8) ;- (SSC) Transmit/Receive start\r
+AT91C_SSC_START_LOW_RF EQU (0x2 << 8) ;- (SSC) Detection of a low level on RF input\r
+AT91C_SSC_START_HIGH_RF EQU (0x3 << 8) ;- (SSC) Detection of a high level on RF input\r
+AT91C_SSC_START_FALL_RF EQU (0x4 << 8) ;- (SSC) Detection of a falling edge on RF input\r
+AT91C_SSC_START_RISE_RF EQU (0x5 << 8) ;- (SSC) Detection of a rising edge on RF input\r
+AT91C_SSC_START_LEVEL_RF EQU (0x6 << 8) ;- (SSC) Detection of any level change on RF input\r
+AT91C_SSC_START_EDGE_RF EQU (0x7 << 8) ;- (SSC) Detection of any edge on RF input\r
+AT91C_SSC_START_0 EQU (0x8 << 8) ;- (SSC) Compare 0\r
+AT91C_SSC_STTDLY EQU (0xFF << 16) ;- (SSC) Receive/Transmit Start Delay\r
+AT91C_SSC_PERIOD EQU (0xFF << 24) ;- (SSC) Receive/Transmit Period Divider Selection\r
+// - -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- \r
+AT91C_SSC_DATLEN EQU (0x1F << 0) ;- (SSC) Data Length\r
+AT91C_SSC_LOOP EQU (0x1 << 5) ;- (SSC) Loop Mode\r
+AT91C_SSC_MSBF EQU (0x1 << 7) ;- (SSC) Most Significant Bit First\r
+AT91C_SSC_DATNB EQU (0xF << 8) ;- (SSC) Data Number per Frame\r
+AT91C_SSC_FSLEN EQU (0xF << 16) ;- (SSC) Receive/Transmit Frame Sync length\r
+AT91C_SSC_FSOS EQU (0x7 << 20) ;- (SSC) Receive/Transmit Frame Sync Output Selection\r
+AT91C_SSC_FSOS_NONE EQU (0x0 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only\r
+AT91C_SSC_FSOS_NEGATIVE EQU (0x1 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse\r
+AT91C_SSC_FSOS_POSITIVE EQU (0x2 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse\r
+AT91C_SSC_FSOS_LOW EQU (0x3 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer\r
+AT91C_SSC_FSOS_HIGH EQU (0x4 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer\r
+AT91C_SSC_FSOS_TOGGLE EQU (0x5 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer\r
+AT91C_SSC_FSEDGE EQU (0x1 << 24) ;- (SSC) Frame Sync Edge Detection\r
+// - -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- \r
+// - -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- \r
+AT91C_SSC_DATDEF EQU (0x1 << 5) ;- (SSC) Data Default Value\r
+AT91C_SSC_FSDEN EQU (0x1 << 23) ;- (SSC) Frame Sync Data Enable\r
+// - -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- \r
+AT91C_SSC_TXRDY EQU (0x1 << 0) ;- (SSC) Transmit Ready\r
+AT91C_SSC_TXEMPTY EQU (0x1 << 1) ;- (SSC) Transmit Empty\r
+AT91C_SSC_ENDTX EQU (0x1 << 2) ;- (SSC) End Of Transmission\r
+AT91C_SSC_TXBUFE EQU (0x1 << 3) ;- (SSC) Transmit Buffer Empty\r
+AT91C_SSC_RXRDY EQU (0x1 << 4) ;- (SSC) Receive Ready\r
+AT91C_SSC_OVRUN EQU (0x1 << 5) ;- (SSC) Receive Overrun\r
+AT91C_SSC_ENDRX EQU (0x1 << 6) ;- (SSC) End of Reception\r
+AT91C_SSC_RXBUFF EQU (0x1 << 7) ;- (SSC) Receive Buffer Full\r
+AT91C_SSC_TXSYN EQU (0x1 << 10) ;- (SSC) Transmit Sync\r
+AT91C_SSC_RXSYN EQU (0x1 << 11) ;- (SSC) Receive Sync\r
+AT91C_SSC_TXENA EQU (0x1 << 16) ;- (SSC) Transmit Enable\r
+AT91C_SSC_RXENA EQU (0x1 << 17) ;- (SSC) Receive Enable\r
+// - -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- \r
+// - -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- \r
+// - -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- \r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Two-wire Interface\r
+// - *****************************************************************************\r
+// - -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- \r
+AT91C_TWI_START EQU (0x1 << 0) ;- (TWI) Send a START Condition\r
+AT91C_TWI_STOP EQU (0x1 << 1) ;- (TWI) Send a STOP Condition\r
+AT91C_TWI_MSEN EQU (0x1 << 2) ;- (TWI) TWI Master Transfer Enabled\r
+AT91C_TWI_MSDIS EQU (0x1 << 3) ;- (TWI) TWI Master Transfer Disabled\r
+AT91C_TWI_SWRST EQU (0x1 << 7) ;- (TWI) Software Reset\r
+// - -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- \r
+AT91C_TWI_IADRSZ EQU (0x3 << 8) ;- (TWI) Internal Device Address Size\r
+AT91C_TWI_IADRSZ_NO EQU (0x0 << 8) ;- (TWI) No internal device address\r
+AT91C_TWI_IADRSZ_1_BYTE EQU (0x1 << 8) ;- (TWI) One-byte internal device address\r
+AT91C_TWI_IADRSZ_2_BYTE EQU (0x2 << 8) ;- (TWI) Two-byte internal device address\r
+AT91C_TWI_IADRSZ_3_BYTE EQU (0x3 << 8) ;- (TWI) Three-byte internal device address\r
+AT91C_TWI_MREAD EQU (0x1 << 12) ;- (TWI) Master Read Direction\r
+AT91C_TWI_DADR EQU (0x7F << 16) ;- (TWI) Device Address\r
+// - -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- \r
+AT91C_TWI_CLDIV EQU (0xFF << 0) ;- (TWI) Clock Low Divider\r
+AT91C_TWI_CHDIV EQU (0xFF << 8) ;- (TWI) Clock High Divider\r
+AT91C_TWI_CKDIV EQU (0x7 << 16) ;- (TWI) Clock Divider\r
+// - -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- \r
+AT91C_TWI_TXCOMP EQU (0x1 << 0) ;- (TWI) Transmission Completed\r
+AT91C_TWI_RXRDY EQU (0x1 << 1) ;- (TWI) Receive holding register ReaDY\r
+AT91C_TWI_TXRDY EQU (0x1 << 2) ;- (TWI) Transmit holding register ReaDY\r
+AT91C_TWI_OVRE EQU (0x1 << 6) ;- (TWI) Overrun Error\r
+AT91C_TWI_UNRE EQU (0x1 << 7) ;- (TWI) Underrun Error\r
+AT91C_TWI_NACK EQU (0x1 << 8) ;- (TWI) Not Acknowledged\r
+// - -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- \r
+// - -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- \r
+// - -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- \r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR PWMC Channel Interface\r
+// - *****************************************************************************\r
+// - -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- \r
+AT91C_PWMC_CPRE EQU (0xF << 0) ;- (PWMC_CH) Channel Pre-scaler : PWMC_CLKx\r
+AT91C_PWMC_CPRE_MCK EQU (0x0) ;- (PWMC_CH) \r
+AT91C_PWMC_CPRE_MCKA EQU (0xB) ;- (PWMC_CH) \r
+AT91C_PWMC_CPRE_MCKB EQU (0xC) ;- (PWMC_CH) \r
+AT91C_PWMC_CALG EQU (0x1 << 8) ;- (PWMC_CH) Channel Alignment\r
+AT91C_PWMC_CPOL EQU (0x1 << 9) ;- (PWMC_CH) Channel Polarity\r
+AT91C_PWMC_CPD EQU (0x1 << 10) ;- (PWMC_CH) Channel Update Period\r
+// - -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- \r
+AT91C_PWMC_CDTY EQU (0x0 << 0) ;- (PWMC_CH) Channel Duty Cycle\r
+// - -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- \r
+AT91C_PWMC_CPRD EQU (0x0 << 0) ;- (PWMC_CH) Channel Period\r
+// - -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- \r
+AT91C_PWMC_CCNT EQU (0x0 << 0) ;- (PWMC_CH) Channel Counter\r
+// - -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- \r
+AT91C_PWMC_CUPD EQU (0x0 << 0) ;- (PWMC_CH) Channel Update\r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface\r
+// - *****************************************************************************\r
+// - -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- \r
+AT91C_PWMC_DIVA EQU (0xFF << 0) ;- (PWMC) CLKA divide factor.\r
+AT91C_PWMC_PREA EQU (0xF << 8) ;- (PWMC) Divider Input Clock Prescaler A\r
+AT91C_PWMC_PREA_MCK EQU (0x0 << 8) ;- (PWMC) \r
+AT91C_PWMC_DIVB EQU (0xFF << 16) ;- (PWMC) CLKB divide factor.\r
+AT91C_PWMC_PREB EQU (0xF << 24) ;- (PWMC) Divider Input Clock Prescaler B\r
+AT91C_PWMC_PREB_MCK EQU (0x0 << 24) ;- (PWMC) \r
+// - -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- \r
+AT91C_PWMC_CHID0 EQU (0x1 << 0) ;- (PWMC) Channel ID 0\r
+AT91C_PWMC_CHID1 EQU (0x1 << 1) ;- (PWMC) Channel ID 1\r
+AT91C_PWMC_CHID2 EQU (0x1 << 2) ;- (PWMC) Channel ID 2\r
+AT91C_PWMC_CHID3 EQU (0x1 << 3) ;- (PWMC) Channel ID 3\r
+// - -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- \r
+// - -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- \r
+// - -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- \r
+// - -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- \r
+// - -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- \r
+// - -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- \r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR USB Device Interface\r
+// - *****************************************************************************\r
+// - -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- \r
+AT91C_UDP_FRM_NUM EQU (0x7FF << 0) ;- (UDP) Frame Number as Defined in the Packet Field Formats\r
+AT91C_UDP_FRM_ERR EQU (0x1 << 16) ;- (UDP) Frame Error\r
+AT91C_UDP_FRM_OK EQU (0x1 << 17) ;- (UDP) Frame OK\r
+// - -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- \r
+AT91C_UDP_FADDEN EQU (0x1 << 0) ;- (UDP) Function Address Enable\r
+AT91C_UDP_CONFG EQU (0x1 << 1) ;- (UDP) Configured\r
+AT91C_UDP_ESR EQU (0x1 << 2) ;- (UDP) Enable Send Resume\r
+AT91C_UDP_RSMINPR EQU (0x1 << 3) ;- (UDP) A Resume Has Been Sent to the Host\r
+AT91C_UDP_RMWUPE EQU (0x1 << 4) ;- (UDP) Remote Wake Up Enable\r
+// - -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- \r
+AT91C_UDP_FADD EQU (0xFF << 0) ;- (UDP) Function Address Value\r
+AT91C_UDP_FEN EQU (0x1 << 8) ;- (UDP) Function Enable\r
+// - -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- \r
+AT91C_UDP_EPINT0 EQU (0x1 << 0) ;- (UDP) Endpoint 0 Interrupt\r
+AT91C_UDP_EPINT1 EQU (0x1 << 1) ;- (UDP) Endpoint 0 Interrupt\r
+AT91C_UDP_EPINT2 EQU (0x1 << 2) ;- (UDP) Endpoint 2 Interrupt\r
+AT91C_UDP_EPINT3 EQU (0x1 << 3) ;- (UDP) Endpoint 3 Interrupt\r
+AT91C_UDP_EPINT4 EQU (0x1 << 4) ;- (UDP) Endpoint 4 Interrupt\r
+AT91C_UDP_EPINT5 EQU (0x1 << 5) ;- (UDP) Endpoint 5 Interrupt\r
+AT91C_UDP_RXSUSP EQU (0x1 << 8) ;- (UDP) USB Suspend Interrupt\r
+AT91C_UDP_RXRSM EQU (0x1 << 9) ;- (UDP) USB Resume Interrupt\r
+AT91C_UDP_EXTRSM EQU (0x1 << 10) ;- (UDP) USB External Resume Interrupt\r
+AT91C_UDP_SOFINT EQU (0x1 << 11) ;- (UDP) USB Start Of frame Interrupt\r
+AT91C_UDP_WAKEUP EQU (0x1 << 13) ;- (UDP) USB Resume Interrupt\r
+// - -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- \r
+// - -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- \r
+// - -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- \r
+AT91C_UDP_ENDBUSRES EQU (0x1 << 12) ;- (UDP) USB End Of Bus Reset Interrupt\r
+// - -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- \r
+// - -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- \r
+AT91C_UDP_EP0 EQU (0x1 << 0) ;- (UDP) Reset Endpoint 0\r
+AT91C_UDP_EP1 EQU (0x1 << 1) ;- (UDP) Reset Endpoint 1\r
+AT91C_UDP_EP2 EQU (0x1 << 2) ;- (UDP) Reset Endpoint 2\r
+AT91C_UDP_EP3 EQU (0x1 << 3) ;- (UDP) Reset Endpoint 3\r
+AT91C_UDP_EP4 EQU (0x1 << 4) ;- (UDP) Reset Endpoint 4\r
+AT91C_UDP_EP5 EQU (0x1 << 5) ;- (UDP) Reset Endpoint 5\r
+// - -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- \r
+AT91C_UDP_TXCOMP EQU (0x1 << 0) ;- (UDP) Generates an IN packet with data previously written in the DPR\r
+AT91C_UDP_RX_DATA_BK0 EQU (0x1 << 1) ;- (UDP) Receive Data Bank 0\r
+AT91C_UDP_RXSETUP EQU (0x1 << 2) ;- (UDP) Sends STALL to the Host (Control endpoints)\r
+AT91C_UDP_ISOERROR EQU (0x1 << 3) ;- (UDP) Isochronous error (Isochronous endpoints)\r
+AT91C_UDP_TXPKTRDY EQU (0x1 << 4) ;- (UDP) Transmit Packet Ready\r
+AT91C_UDP_FORCESTALL EQU (0x1 << 5) ;- (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).\r
+AT91C_UDP_RX_DATA_BK1 EQU (0x1 << 6) ;- (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).\r
+AT91C_UDP_DIR EQU (0x1 << 7) ;- (UDP) Transfer Direction\r
+AT91C_UDP_EPTYPE EQU (0x7 << 8) ;- (UDP) Endpoint type\r
+AT91C_UDP_EPTYPE_CTRL EQU (0x0 << 8) ;- (UDP) Control\r
+AT91C_UDP_EPTYPE_ISO_OUT EQU (0x1 << 8) ;- (UDP) Isochronous OUT\r
+AT91C_UDP_EPTYPE_BULK_OUT EQU (0x2 << 8) ;- (UDP) Bulk OUT\r
+AT91C_UDP_EPTYPE_INT_OUT EQU (0x3 << 8) ;- (UDP) Interrupt OUT\r
+AT91C_UDP_EPTYPE_ISO_IN EQU (0x5 << 8) ;- (UDP) Isochronous IN\r
+AT91C_UDP_EPTYPE_BULK_IN EQU (0x6 << 8) ;- (UDP) Bulk IN\r
+AT91C_UDP_EPTYPE_INT_IN EQU (0x7 << 8) ;- (UDP) Interrupt IN\r
+AT91C_UDP_DTGLE EQU (0x1 << 11) ;- (UDP) Data Toggle\r
+AT91C_UDP_EPEDS EQU (0x1 << 15) ;- (UDP) Endpoint Enable Disable\r
+AT91C_UDP_RXBYTECNT EQU (0x7FF << 16) ;- (UDP) Number Of Bytes Available in the FIFO\r
+// - -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- \r
+AT91C_UDP_TXVDIS EQU (0x1 << 8) ;- (UDP) \r
+AT91C_UDP_PUON EQU (0x1 << 9) ;- (UDP) Pull-up ON\r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Timer Counter Channel Interface\r
+// - *****************************************************************************\r
+// - -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- \r
+AT91C_TC_CLKEN EQU (0x1 << 0) ;- (TC) Counter Clock Enable Command\r
+AT91C_TC_CLKDIS EQU (0x1 << 1) ;- (TC) Counter Clock Disable Command\r
+AT91C_TC_SWTRG EQU (0x1 << 2) ;- (TC) Software Trigger Command\r
+// - -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- \r
+AT91C_TC_CLKS EQU (0x7 << 0) ;- (TC) Clock Selection\r
+AT91C_TC_CLKS_TIMER_DIV1_CLOCK EQU (0x0) ;- (TC) Clock selected: TIMER_DIV1_CLOCK\r
+AT91C_TC_CLKS_TIMER_DIV2_CLOCK EQU (0x1) ;- (TC) Clock selected: TIMER_DIV2_CLOCK\r
+AT91C_TC_CLKS_TIMER_DIV3_CLOCK EQU (0x2) ;- (TC) Clock selected: TIMER_DIV3_CLOCK\r
+AT91C_TC_CLKS_TIMER_DIV4_CLOCK EQU (0x3) ;- (TC) Clock selected: TIMER_DIV4_CLOCK\r
+AT91C_TC_CLKS_TIMER_DIV5_CLOCK EQU (0x4) ;- (TC) Clock selected: TIMER_DIV5_CLOCK\r
+AT91C_TC_CLKS_XC0 EQU (0x5) ;- (TC) Clock selected: XC0\r
+AT91C_TC_CLKS_XC1 EQU (0x6) ;- (TC) Clock selected: XC1\r
+AT91C_TC_CLKS_XC2 EQU (0x7) ;- (TC) Clock selected: XC2\r
+AT91C_TC_CLKI EQU (0x1 << 3) ;- (TC) Clock Invert\r
+AT91C_TC_BURST EQU (0x3 << 4) ;- (TC) Burst Signal Selection\r
+AT91C_TC_BURST_NONE EQU (0x0 << 4) ;- (TC) The clock is not gated by an external signal\r
+AT91C_TC_BURST_XC0 EQU (0x1 << 4) ;- (TC) XC0 is ANDed with the selected clock\r
+AT91C_TC_BURST_XC1 EQU (0x2 << 4) ;- (TC) XC1 is ANDed with the selected clock\r
+AT91C_TC_BURST_XC2 EQU (0x3 << 4) ;- (TC) XC2 is ANDed with the selected clock\r
+AT91C_TC_CPCSTOP EQU (0x1 << 6) ;- (TC) Counter Clock Stopped with RC Compare\r
+AT91C_TC_LDBSTOP EQU (0x1 << 6) ;- (TC) Counter Clock Stopped with RB Loading\r
+AT91C_TC_CPCDIS EQU (0x1 << 7) ;- (TC) Counter Clock Disable with RC Compare\r
+AT91C_TC_LDBDIS EQU (0x1 << 7) ;- (TC) Counter Clock Disabled with RB Loading\r
+AT91C_TC_ETRGEDG EQU (0x3 << 8) ;- (TC) External Trigger Edge Selection\r
+AT91C_TC_ETRGEDG_NONE EQU (0x0 << 8) ;- (TC) Edge: None\r
+AT91C_TC_ETRGEDG_RISING EQU (0x1 << 8) ;- (TC) Edge: rising edge\r
+AT91C_TC_ETRGEDG_FALLING EQU (0x2 << 8) ;- (TC) Edge: falling edge\r
+AT91C_TC_ETRGEDG_BOTH EQU (0x3 << 8) ;- (TC) Edge: each edge\r
+AT91C_TC_EEVTEDG EQU (0x3 << 8) ;- (TC) External Event Edge Selection\r
+AT91C_TC_EEVTEDG_NONE EQU (0x0 << 8) ;- (TC) Edge: None\r
+AT91C_TC_EEVTEDG_RISING EQU (0x1 << 8) ;- (TC) Edge: rising edge\r
+AT91C_TC_EEVTEDG_FALLING EQU (0x2 << 8) ;- (TC) Edge: falling edge\r
+AT91C_TC_EEVTEDG_BOTH EQU (0x3 << 8) ;- (TC) Edge: each edge\r
+AT91C_TC_EEVT EQU (0x3 << 10) ;- (TC) External Event Selection\r
+AT91C_TC_EEVT_TIOB EQU (0x0 << 10) ;- (TC) Signal selected as external event: TIOB TIOB direction: input\r
+AT91C_TC_EEVT_XC0 EQU (0x1 << 10) ;- (TC) Signal selected as external event: XC0 TIOB direction: output\r
+AT91C_TC_EEVT_XC1 EQU (0x2 << 10) ;- (TC) Signal selected as external event: XC1 TIOB direction: output\r
+AT91C_TC_EEVT_XC2 EQU (0x3 << 10) ;- (TC) Signal selected as external event: XC2 TIOB direction: output\r
+AT91C_TC_ABETRG EQU (0x1 << 10) ;- (TC) TIOA or TIOB External Trigger Selection\r
+AT91C_TC_ENETRG EQU (0x1 << 12) ;- (TC) External Event Trigger enable\r
+AT91C_TC_WAVESEL EQU (0x3 << 13) ;- (TC) Waveform Selection\r
+AT91C_TC_WAVESEL_UP EQU (0x0 << 13) ;- (TC) UP mode without atomatic trigger on RC Compare\r
+AT91C_TC_WAVESEL_UPDOWN EQU (0x1 << 13) ;- (TC) UPDOWN mode without automatic trigger on RC Compare\r
+AT91C_TC_WAVESEL_UP_AUTO EQU (0x2 << 13) ;- (TC) UP mode with automatic trigger on RC Compare\r
+AT91C_TC_WAVESEL_UPDOWN_AUTO EQU (0x3 << 13) ;- (TC) UPDOWN mode with automatic trigger on RC Compare\r
+AT91C_TC_CPCTRG EQU (0x1 << 14) ;- (TC) RC Compare Trigger Enable\r
+AT91C_TC_WAVE EQU (0x1 << 15) ;- (TC) \r
+AT91C_TC_ACPA EQU (0x3 << 16) ;- (TC) RA Compare Effect on TIOA\r
+AT91C_TC_ACPA_NONE EQU (0x0 << 16) ;- (TC) Effect: none\r
+AT91C_TC_ACPA_SET EQU (0x1 << 16) ;- (TC) Effect: set\r
+AT91C_TC_ACPA_CLEAR EQU (0x2 << 16) ;- (TC) Effect: clear\r
+AT91C_TC_ACPA_TOGGLE EQU (0x3 << 16) ;- (TC) Effect: toggle\r
+AT91C_TC_LDRA EQU (0x3 << 16) ;- (TC) RA Loading Selection\r
+AT91C_TC_LDRA_NONE EQU (0x0 << 16) ;- (TC) Edge: None\r
+AT91C_TC_LDRA_RISING EQU (0x1 << 16) ;- (TC) Edge: rising edge of TIOA\r
+AT91C_TC_LDRA_FALLING EQU (0x2 << 16) ;- (TC) Edge: falling edge of TIOA\r
+AT91C_TC_LDRA_BOTH EQU (0x3 << 16) ;- (TC) Edge: each edge of TIOA\r
+AT91C_TC_ACPC EQU (0x3 << 18) ;- (TC) RC Compare Effect on TIOA\r
+AT91C_TC_ACPC_NONE EQU (0x0 << 18) ;- (TC) Effect: none\r
+AT91C_TC_ACPC_SET EQU (0x1 << 18) ;- (TC) Effect: set\r
+AT91C_TC_ACPC_CLEAR EQU (0x2 << 18) ;- (TC) Effect: clear\r
+AT91C_TC_ACPC_TOGGLE EQU (0x3 << 18) ;- (TC) Effect: toggle\r
+AT91C_TC_LDRB EQU (0x3 << 18) ;- (TC) RB Loading Selection\r
+AT91C_TC_LDRB_NONE EQU (0x0 << 18) ;- (TC) Edge: None\r
+AT91C_TC_LDRB_RISING EQU (0x1 << 18) ;- (TC) Edge: rising edge of TIOA\r
+AT91C_TC_LDRB_FALLING EQU (0x2 << 18) ;- (TC) Edge: falling edge of TIOA\r
+AT91C_TC_LDRB_BOTH EQU (0x3 << 18) ;- (TC) Edge: each edge of TIOA\r
+AT91C_TC_AEEVT EQU (0x3 << 20) ;- (TC) External Event Effect on TIOA\r
+AT91C_TC_AEEVT_NONE EQU (0x0 << 20) ;- (TC) Effect: none\r
+AT91C_TC_AEEVT_SET EQU (0x1 << 20) ;- (TC) Effect: set\r
+AT91C_TC_AEEVT_CLEAR EQU (0x2 << 20) ;- (TC) Effect: clear\r
+AT91C_TC_AEEVT_TOGGLE EQU (0x3 << 20) ;- (TC) Effect: toggle\r
+AT91C_TC_ASWTRG EQU (0x3 << 22) ;- (TC) Software Trigger Effect on TIOA\r
+AT91C_TC_ASWTRG_NONE EQU (0x0 << 22) ;- (TC) Effect: none\r
+AT91C_TC_ASWTRG_SET EQU (0x1 << 22) ;- (TC) Effect: set\r
+AT91C_TC_ASWTRG_CLEAR EQU (0x2 << 22) ;- (TC) Effect: clear\r
+AT91C_TC_ASWTRG_TOGGLE EQU (0x3 << 22) ;- (TC) Effect: toggle\r
+AT91C_TC_BCPB EQU (0x3 << 24) ;- (TC) RB Compare Effect on TIOB\r
+AT91C_TC_BCPB_NONE EQU (0x0 << 24) ;- (TC) Effect: none\r
+AT91C_TC_BCPB_SET EQU (0x1 << 24) ;- (TC) Effect: set\r
+AT91C_TC_BCPB_CLEAR EQU (0x2 << 24) ;- (TC) Effect: clear\r
+AT91C_TC_BCPB_TOGGLE EQU (0x3 << 24) ;- (TC) Effect: toggle\r
+AT91C_TC_BCPC EQU (0x3 << 26) ;- (TC) RC Compare Effect on TIOB\r
+AT91C_TC_BCPC_NONE EQU (0x0 << 26) ;- (TC) Effect: none\r
+AT91C_TC_BCPC_SET EQU (0x1 << 26) ;- (TC) Effect: set\r
+AT91C_TC_BCPC_CLEAR EQU (0x2 << 26) ;- (TC) Effect: clear\r
+AT91C_TC_BCPC_TOGGLE EQU (0x3 << 26) ;- (TC) Effect: toggle\r
+AT91C_TC_BEEVT EQU (0x3 << 28) ;- (TC) External Event Effect on TIOB\r
+AT91C_TC_BEEVT_NONE EQU (0x0 << 28) ;- (TC) Effect: none\r
+AT91C_TC_BEEVT_SET EQU (0x1 << 28) ;- (TC) Effect: set\r
+AT91C_TC_BEEVT_CLEAR EQU (0x2 << 28) ;- (TC) Effect: clear\r
+AT91C_TC_BEEVT_TOGGLE EQU (0x3 << 28) ;- (TC) Effect: toggle\r
+AT91C_TC_BSWTRG EQU (0x3 << 30) ;- (TC) Software Trigger Effect on TIOB\r
+AT91C_TC_BSWTRG_NONE EQU (0x0 << 30) ;- (TC) Effect: none\r
+AT91C_TC_BSWTRG_SET EQU (0x1 << 30) ;- (TC) Effect: set\r
+AT91C_TC_BSWTRG_CLEAR EQU (0x2 << 30) ;- (TC) Effect: clear\r
+AT91C_TC_BSWTRG_TOGGLE EQU (0x3 << 30) ;- (TC) Effect: toggle\r
+// - -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- \r
+AT91C_TC_COVFS EQU (0x1 << 0) ;- (TC) Counter Overflow\r
+AT91C_TC_LOVRS EQU (0x1 << 1) ;- (TC) Load Overrun\r
+AT91C_TC_CPAS EQU (0x1 << 2) ;- (TC) RA Compare\r
+AT91C_TC_CPBS EQU (0x1 << 3) ;- (TC) RB Compare\r
+AT91C_TC_CPCS EQU (0x1 << 4) ;- (TC) RC Compare\r
+AT91C_TC_LDRAS EQU (0x1 << 5) ;- (TC) RA Loading\r
+AT91C_TC_LDRBS EQU (0x1 << 6) ;- (TC) RB Loading\r
+AT91C_TC_ETRGS EQU (0x1 << 7) ;- (TC) External Trigger\r
+AT91C_TC_CLKSTA EQU (0x1 << 16) ;- (TC) Clock Enabling\r
+AT91C_TC_MTIOA EQU (0x1 << 17) ;- (TC) TIOA Mirror\r
+AT91C_TC_MTIOB EQU (0x1 << 18) ;- (TC) TIOA Mirror\r
+// - -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- \r
+// - -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- \r
+// - -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- \r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Timer Counter Interface\r
+// - *****************************************************************************\r
+// - -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- \r
+AT91C_TCB_SYNC EQU (0x1 << 0) ;- (TCB) Synchro Command\r
+// - -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- \r
+AT91C_TCB_TC0XC0S EQU (0x3 << 0) ;- (TCB) External Clock Signal 0 Selection\r
+AT91C_TCB_TC0XC0S_TCLK0 EQU (0x0) ;- (TCB) TCLK0 connected to XC0\r
+AT91C_TCB_TC0XC0S_NONE EQU (0x1) ;- (TCB) None signal connected to XC0\r
+AT91C_TCB_TC0XC0S_TIOA1 EQU (0x2) ;- (TCB) TIOA1 connected to XC0\r
+AT91C_TCB_TC0XC0S_TIOA2 EQU (0x3) ;- (TCB) TIOA2 connected to XC0\r
+AT91C_TCB_TC1XC1S EQU (0x3 << 2) ;- (TCB) External Clock Signal 1 Selection\r
+AT91C_TCB_TC1XC1S_TCLK1 EQU (0x0 << 2) ;- (TCB) TCLK1 connected to XC1\r
+AT91C_TCB_TC1XC1S_NONE EQU (0x1 << 2) ;- (TCB) None signal connected to XC1\r
+AT91C_TCB_TC1XC1S_TIOA0 EQU (0x2 << 2) ;- (TCB) TIOA0 connected to XC1\r
+AT91C_TCB_TC1XC1S_TIOA2 EQU (0x3 << 2) ;- (TCB) TIOA2 connected to XC1\r
+AT91C_TCB_TC2XC2S EQU (0x3 << 4) ;- (TCB) External Clock Signal 2 Selection\r
+AT91C_TCB_TC2XC2S_TCLK2 EQU (0x0 << 4) ;- (TCB) TCLK2 connected to XC2\r
+AT91C_TCB_TC2XC2S_NONE EQU (0x1 << 4) ;- (TCB) None signal connected to XC2\r
+AT91C_TCB_TC2XC2S_TIOA0 EQU (0x2 << 4) ;- (TCB) TIOA0 connected to XC2\r
+AT91C_TCB_TC2XC2S_TIOA1 EQU (0x3 << 4) ;- (TCB) TIOA2 connected to XC2\r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface\r
+// - *****************************************************************************\r
+// - -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- \r
+AT91C_CAN_MTIMEMARK EQU (0xFFFF << 0) ;- (CAN_MB) Mailbox Timemark\r
+AT91C_CAN_PRIOR EQU (0xF << 16) ;- (CAN_MB) Mailbox Priority\r
+AT91C_CAN_MOT EQU (0x7 << 24) ;- (CAN_MB) Mailbox Object Type\r
+AT91C_CAN_MOT_DIS EQU (0x0 << 24) ;- (CAN_MB) \r
+AT91C_CAN_MOT_RX EQU (0x1 << 24) ;- (CAN_MB) \r
+AT91C_CAN_MOT_RXOVERWRITE EQU (0x2 << 24) ;- (CAN_MB) \r
+AT91C_CAN_MOT_TX EQU (0x3 << 24) ;- (CAN_MB) \r
+AT91C_CAN_MOT_CONSUMER EQU (0x4 << 24) ;- (CAN_MB) \r
+AT91C_CAN_MOT_PRODUCER EQU (0x5 << 24) ;- (CAN_MB) \r
+// - -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- \r
+AT91C_CAN_MIDvB EQU (0x3FFFF << 0) ;- (CAN_MB) Complementary bits for identifier in extended mode\r
+AT91C_CAN_MIDvA EQU (0x7FF << 18) ;- (CAN_MB) Identifier for standard frame mode\r
+AT91C_CAN_MIDE EQU (0x1 << 29) ;- (CAN_MB) Identifier Version\r
+// - -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- \r
+// - -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- \r
+// - -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- \r
+AT91C_CAN_MTIMESTAMP EQU (0xFFFF << 0) ;- (CAN_MB) Timer Value\r
+AT91C_CAN_MDLC EQU (0xF << 16) ;- (CAN_MB) Mailbox Data Length Code\r
+AT91C_CAN_MRTR EQU (0x1 << 20) ;- (CAN_MB) Mailbox Remote Transmission Request\r
+AT91C_CAN_MABT EQU (0x1 << 22) ;- (CAN_MB) Mailbox Message Abort\r
+AT91C_CAN_MRDY EQU (0x1 << 23) ;- (CAN_MB) Mailbox Ready\r
+AT91C_CAN_MMI EQU (0x1 << 24) ;- (CAN_MB) Mailbox Message Ignored\r
+// - -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- \r
+// - -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- \r
+// - -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- \r
+AT91C_CAN_MACR EQU (0x1 << 22) ;- (CAN_MB) Abort Request for Mailbox\r
+AT91C_CAN_MTCR EQU (0x1 << 23) ;- (CAN_MB) Mailbox Transfer Command\r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Control Area Network Interface\r
+// - *****************************************************************************\r
+// - -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- \r
+AT91C_CAN_CANEN EQU (0x1 << 0) ;- (CAN) CAN Controller Enable\r
+AT91C_CAN_LPM EQU (0x1 << 1) ;- (CAN) Disable/Enable Low Power Mode\r
+AT91C_CAN_ABM EQU (0x1 << 2) ;- (CAN) Disable/Enable Autobaud/Listen Mode\r
+AT91C_CAN_OVL EQU (0x1 << 3) ;- (CAN) Disable/Enable Overload Frame\r
+AT91C_CAN_TEOF EQU (0x1 << 4) ;- (CAN) Time Stamp messages at each end of Frame\r
+AT91C_CAN_TTM EQU (0x1 << 5) ;- (CAN) Disable/Enable Time Trigger Mode\r
+AT91C_CAN_TIMFRZ EQU (0x1 << 6) ;- (CAN) Enable Timer Freeze\r
+AT91C_CAN_DRPT EQU (0x1 << 7) ;- (CAN) Disable Repeat\r
+// - -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- \r
+AT91C_CAN_MB0 EQU (0x1 << 0) ;- (CAN) Mailbox 0 Flag\r
+AT91C_CAN_MB1 EQU (0x1 << 1) ;- (CAN) Mailbox 1 Flag\r
+AT91C_CAN_MB2 EQU (0x1 << 2) ;- (CAN) Mailbox 2 Flag\r
+AT91C_CAN_MB3 EQU (0x1 << 3) ;- (CAN) Mailbox 3 Flag\r
+AT91C_CAN_MB4 EQU (0x1 << 4) ;- (CAN) Mailbox 4 Flag\r
+AT91C_CAN_MB5 EQU (0x1 << 5) ;- (CAN) Mailbox 5 Flag\r
+AT91C_CAN_MB6 EQU (0x1 << 6) ;- (CAN) Mailbox 6 Flag\r
+AT91C_CAN_MB7 EQU (0x1 << 7) ;- (CAN) Mailbox 7 Flag\r
+AT91C_CAN_MB8 EQU (0x1 << 8) ;- (CAN) Mailbox 8 Flag\r
+AT91C_CAN_MB9 EQU (0x1 << 9) ;- (CAN) Mailbox 9 Flag\r
+AT91C_CAN_MB10 EQU (0x1 << 10) ;- (CAN) Mailbox 10 Flag\r
+AT91C_CAN_MB11 EQU (0x1 << 11) ;- (CAN) Mailbox 11 Flag\r
+AT91C_CAN_MB12 EQU (0x1 << 12) ;- (CAN) Mailbox 12 Flag\r
+AT91C_CAN_MB13 EQU (0x1 << 13) ;- (CAN) Mailbox 13 Flag\r
+AT91C_CAN_MB14 EQU (0x1 << 14) ;- (CAN) Mailbox 14 Flag\r
+AT91C_CAN_MB15 EQU (0x1 << 15) ;- (CAN) Mailbox 15 Flag\r
+AT91C_CAN_ERRA EQU (0x1 << 16) ;- (CAN) Error Active Mode Flag\r
+AT91C_CAN_WARN EQU (0x1 << 17) ;- (CAN) Warning Limit Flag\r
+AT91C_CAN_ERRP EQU (0x1 << 18) ;- (CAN) Error Passive Mode Flag\r
+AT91C_CAN_BOFF EQU (0x1 << 19) ;- (CAN) Bus Off Mode Flag\r
+AT91C_CAN_SLEEP EQU (0x1 << 20) ;- (CAN) Sleep Flag\r
+AT91C_CAN_WAKEUP EQU (0x1 << 21) ;- (CAN) Wakeup Flag\r
+AT91C_CAN_TOVF EQU (0x1 << 22) ;- (CAN) Timer Overflow Flag\r
+AT91C_CAN_TSTP EQU (0x1 << 23) ;- (CAN) Timestamp Flag\r
+AT91C_CAN_CERR EQU (0x1 << 24) ;- (CAN) CRC Error\r
+AT91C_CAN_SERR EQU (0x1 << 25) ;- (CAN) Stuffing Error\r
+AT91C_CAN_AERR EQU (0x1 << 26) ;- (CAN) Acknowledgment Error\r
+AT91C_CAN_FERR EQU (0x1 << 27) ;- (CAN) Form Error\r
+AT91C_CAN_BERR EQU (0x1 << 28) ;- (CAN) Bit Error\r
+// - -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- \r
+// - -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- \r
+// - -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- \r
+AT91C_CAN_RBSY EQU (0x1 << 29) ;- (CAN) Receiver Busy\r
+AT91C_CAN_TBSY EQU (0x1 << 30) ;- (CAN) Transmitter Busy\r
+AT91C_CAN_OVLY EQU (0x1 << 31) ;- (CAN) Overload Busy\r
+// - -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- \r
+AT91C_CAN_PHASE2 EQU (0x7 << 0) ;- (CAN) Phase 2 segment\r
+AT91C_CAN_PHASE1 EQU (0x7 << 4) ;- (CAN) Phase 1 segment\r
+AT91C_CAN_PROPAG EQU (0x7 << 8) ;- (CAN) Programmation time segment\r
+AT91C_CAN_SYNC EQU (0x3 << 12) ;- (CAN) Re-synchronization jump width segment\r
+AT91C_CAN_BRP EQU (0x7F << 16) ;- (CAN) Baudrate Prescaler\r
+AT91C_CAN_SMP EQU (0x1 << 24) ;- (CAN) Sampling mode\r
+// - -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- \r
+AT91C_CAN_TIMER EQU (0xFFFF << 0) ;- (CAN) Timer field\r
+// - -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- \r
+// - -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- \r
+AT91C_CAN_REC EQU (0xFF << 0) ;- (CAN) Receive Error Counter\r
+AT91C_CAN_TEC EQU (0xFF << 16) ;- (CAN) Transmit Error Counter\r
+// - -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- \r
+AT91C_CAN_TIMRST EQU (0x1 << 31) ;- (CAN) Timer Reset Field\r
+// - -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- \r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Ethernet MAC 10/100\r
+// - *****************************************************************************\r
+// - -------- EMAC_NCR : (EMAC Offset: 0x0) -------- \r
+AT91C_EMAC_LB EQU (0x1 << 0) ;- (EMAC) Loopback. Optional. When set, loopback signal is at high level.\r
+AT91C_EMAC_LLB EQU (0x1 << 1) ;- (EMAC) Loopback local. \r
+AT91C_EMAC_RE EQU (0x1 << 2) ;- (EMAC) Receive enable. \r
+AT91C_EMAC_TE EQU (0x1 << 3) ;- (EMAC) Transmit enable. \r
+AT91C_EMAC_MPE EQU (0x1 << 4) ;- (EMAC) Management port enable. \r
+AT91C_EMAC_CLRSTAT EQU (0x1 << 5) ;- (EMAC) Clear statistics registers. \r
+AT91C_EMAC_INCSTAT EQU (0x1 << 6) ;- (EMAC) Increment statistics registers. \r
+AT91C_EMAC_WESTAT EQU (0x1 << 7) ;- (EMAC) Write enable for statistics registers. \r
+AT91C_EMAC_BP EQU (0x1 << 8) ;- (EMAC) Back pressure. \r
+AT91C_EMAC_TSTART EQU (0x1 << 9) ;- (EMAC) Start Transmission. \r
+AT91C_EMAC_THALT EQU (0x1 << 10) ;- (EMAC) Transmission Halt. \r
+AT91C_EMAC_TPFR EQU (0x1 << 11) ;- (EMAC) Transmit pause frame \r
+AT91C_EMAC_TZQ EQU (0x1 << 12) ;- (EMAC) Transmit zero quantum pause frame\r
+// - -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- \r
+AT91C_EMAC_SPD EQU (0x1 << 0) ;- (EMAC) Speed. \r
+AT91C_EMAC_FD EQU (0x1 << 1) ;- (EMAC) Full duplex. \r
+AT91C_EMAC_JFRAME EQU (0x1 << 3) ;- (EMAC) Jumbo Frames. \r
+AT91C_EMAC_CAF EQU (0x1 << 4) ;- (EMAC) Copy all frames. \r
+AT91C_EMAC_NBC EQU (0x1 << 5) ;- (EMAC) No broadcast. \r
+AT91C_EMAC_MTI EQU (0x1 << 6) ;- (EMAC) Multicast hash event enable\r
+AT91C_EMAC_UNI EQU (0x1 << 7) ;- (EMAC) Unicast hash enable. \r
+AT91C_EMAC_BIG EQU (0x1 << 8) ;- (EMAC) Receive 1522 bytes. \r
+AT91C_EMAC_EAE EQU (0x1 << 9) ;- (EMAC) External address match enable. \r
+AT91C_EMAC_CLK EQU (0x3 << 10) ;- (EMAC) \r
+AT91C_EMAC_CLK_HCLK_8 EQU (0x0 << 10) ;- (EMAC) HCLK divided by 8\r
+AT91C_EMAC_CLK_HCLK_16 EQU (0x1 << 10) ;- (EMAC) HCLK divided by 16\r
+AT91C_EMAC_CLK_HCLK_32 EQU (0x2 << 10) ;- (EMAC) HCLK divided by 32\r
+AT91C_EMAC_CLK_HCLK_64 EQU (0x3 << 10) ;- (EMAC) HCLK divided by 64\r
+AT91C_EMAC_RTY EQU (0x1 << 12) ;- (EMAC) \r
+AT91C_EMAC_PAE EQU (0x1 << 13) ;- (EMAC) \r
+AT91C_EMAC_RBOF EQU (0x3 << 14) ;- (EMAC) \r
+AT91C_EMAC_RBOF_OFFSET_0 EQU (0x0 << 14) ;- (EMAC) no offset from start of receive buffer\r
+AT91C_EMAC_RBOF_OFFSET_1 EQU (0x1 << 14) ;- (EMAC) one byte offset from start of receive buffer\r
+AT91C_EMAC_RBOF_OFFSET_2 EQU (0x2 << 14) ;- (EMAC) two bytes offset from start of receive buffer\r
+AT91C_EMAC_RBOF_OFFSET_3 EQU (0x3 << 14) ;- (EMAC) three bytes offset from start of receive buffer\r
+AT91C_EMAC_RLCE EQU (0x1 << 16) ;- (EMAC) Receive Length field Checking Enable\r
+AT91C_EMAC_DRFCS EQU (0x1 << 17) ;- (EMAC) Discard Receive FCS\r
+AT91C_EMAC_EFRHD EQU (0x1 << 18) ;- (EMAC) \r
+AT91C_EMAC_IRXFCS EQU (0x1 << 19) ;- (EMAC) Ignore RX FCS\r
+// - -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- \r
+AT91C_EMAC_LINKR EQU (0x1 << 0) ;- (EMAC) \r
+AT91C_EMAC_MDIO EQU (0x1 << 1) ;- (EMAC) \r
+AT91C_EMAC_IDLE EQU (0x1 << 2) ;- (EMAC) \r
+// - -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- \r
+AT91C_EMAC_UBR EQU (0x1 << 0) ;- (EMAC) \r
+AT91C_EMAC_COL EQU (0x1 << 1) ;- (EMAC) \r
+AT91C_EMAC_RLES EQU (0x1 << 2) ;- (EMAC) \r
+AT91C_EMAC_TGO EQU (0x1 << 3) ;- (EMAC) Transmit Go\r
+AT91C_EMAC_BEX EQU (0x1 << 4) ;- (EMAC) Buffers exhausted mid frame\r
+AT91C_EMAC_COMP EQU (0x1 << 5) ;- (EMAC) \r
+AT91C_EMAC_UND EQU (0x1 << 6) ;- (EMAC) \r
+// - -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- \r
+AT91C_EMAC_BNA EQU (0x1 << 0) ;- (EMAC) \r
+AT91C_EMAC_REC EQU (0x1 << 1) ;- (EMAC) \r
+AT91C_EMAC_OVR EQU (0x1 << 2) ;- (EMAC) \r
+// - -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- \r
+AT91C_EMAC_MFD EQU (0x1 << 0) ;- (EMAC) \r
+AT91C_EMAC_RCOMP EQU (0x1 << 1) ;- (EMAC) \r
+AT91C_EMAC_RXUBR EQU (0x1 << 2) ;- (EMAC) \r
+AT91C_EMAC_TXUBR EQU (0x1 << 3) ;- (EMAC) \r
+AT91C_EMAC_TUNDR EQU (0x1 << 4) ;- (EMAC) \r
+AT91C_EMAC_RLEX EQU (0x1 << 5) ;- (EMAC) \r
+AT91C_EMAC_TXERR EQU (0x1 << 6) ;- (EMAC) \r
+AT91C_EMAC_TCOMP EQU (0x1 << 7) ;- (EMAC) \r
+AT91C_EMAC_LINK EQU (0x1 << 9) ;- (EMAC) \r
+AT91C_EMAC_ROVR EQU (0x1 << 10) ;- (EMAC) \r
+AT91C_EMAC_HRESP EQU (0x1 << 11) ;- (EMAC) \r
+AT91C_EMAC_PFRE EQU (0x1 << 12) ;- (EMAC) \r
+AT91C_EMAC_PTZ EQU (0x1 << 13) ;- (EMAC) \r
+// - -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- \r
+// - -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- \r
+// - -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- \r
+// - -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- \r
+AT91C_EMAC_DATA EQU (0xFFFF << 0) ;- (EMAC) \r
+AT91C_EMAC_CODE EQU (0x3 << 16) ;- (EMAC) \r
+AT91C_EMAC_REGA EQU (0x1F << 18) ;- (EMAC) \r
+AT91C_EMAC_PHYA EQU (0x1F << 23) ;- (EMAC) \r
+AT91C_EMAC_RW EQU (0x3 << 28) ;- (EMAC) \r
+AT91C_EMAC_SOF EQU (0x3 << 30) ;- (EMAC) \r
+// - -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- \r
+AT91C_EMAC_RMII EQU (0x1 << 0) ;- (EMAC) Reduce MII\r
+// - -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- \r
+AT91C_EMAC_IP EQU (0xFFFF << 0) ;- (EMAC) ARP request IP address\r
+AT91C_EMAC_MAG EQU (0x1 << 16) ;- (EMAC) Magic packet event enable\r
+AT91C_EMAC_ARP EQU (0x1 << 17) ;- (EMAC) ARP request event enable\r
+AT91C_EMAC_SA1 EQU (0x1 << 18) ;- (EMAC) Specific address register 1 event enable\r
+// - -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- \r
+AT91C_EMAC_REVREF EQU (0xFFFF << 0) ;- (EMAC) \r
+AT91C_EMAC_PARTREF EQU (0xFFFF << 16) ;- (EMAC) \r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Analog to Digital Convertor\r
+// - *****************************************************************************\r
+// - -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- \r
+AT91C_ADC_SWRST EQU (0x1 << 0) ;- (ADC) Software Reset\r
+AT91C_ADC_START EQU (0x1 << 1) ;- (ADC) Start Conversion\r
+// - -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- \r
+AT91C_ADC_TRGEN EQU (0x1 << 0) ;- (ADC) Trigger Enable\r
+AT91C_ADC_TRGEN_DIS EQU (0x0) ;- (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software\r
+AT91C_ADC_TRGEN_EN EQU (0x1) ;- (ADC) Hardware trigger selected by TRGSEL field is enabled.\r
+AT91C_ADC_TRGSEL EQU (0x7 << 1) ;- (ADC) Trigger Selection\r
+AT91C_ADC_TRGSEL_TIOA0 EQU (0x0 << 1) ;- (ADC) Selected TRGSEL = TIAO0\r
+AT91C_ADC_TRGSEL_TIOA1 EQU (0x1 << 1) ;- (ADC) Selected TRGSEL = TIAO1\r
+AT91C_ADC_TRGSEL_TIOA2 EQU (0x2 << 1) ;- (ADC) Selected TRGSEL = TIAO2\r
+AT91C_ADC_TRGSEL_TIOA3 EQU (0x3 << 1) ;- (ADC) Selected TRGSEL = TIAO3\r
+AT91C_ADC_TRGSEL_TIOA4 EQU (0x4 << 1) ;- (ADC) Selected TRGSEL = TIAO4\r
+AT91C_ADC_TRGSEL_TIOA5 EQU (0x5 << 1) ;- (ADC) Selected TRGSEL = TIAO5\r
+AT91C_ADC_TRGSEL_EXT EQU (0x6 << 1) ;- (ADC) Selected TRGSEL = External Trigger\r
+AT91C_ADC_LOWRES EQU (0x1 << 4) ;- (ADC) Resolution.\r
+AT91C_ADC_LOWRES_10_BIT EQU (0x0 << 4) ;- (ADC) 10-bit resolution\r
+AT91C_ADC_LOWRES_8_BIT EQU (0x1 << 4) ;- (ADC) 8-bit resolution\r
+AT91C_ADC_SLEEP EQU (0x1 << 5) ;- (ADC) Sleep Mode\r
+AT91C_ADC_SLEEP_NORMAL_MODE EQU (0x0 << 5) ;- (ADC) Normal Mode\r
+AT91C_ADC_SLEEP_MODE EQU (0x1 << 5) ;- (ADC) Sleep Mode\r
+AT91C_ADC_PRESCAL EQU (0x3F << 8) ;- (ADC) Prescaler rate selection\r
+AT91C_ADC_STARTUP EQU (0x1F << 16) ;- (ADC) Startup Time\r
+AT91C_ADC_SHTIM EQU (0xF << 24) ;- (ADC) Sample & Hold Time\r
+// - -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- \r
+AT91C_ADC_CH0 EQU (0x1 << 0) ;- (ADC) Channel 0\r
+AT91C_ADC_CH1 EQU (0x1 << 1) ;- (ADC) Channel 1\r
+AT91C_ADC_CH2 EQU (0x1 << 2) ;- (ADC) Channel 2\r
+AT91C_ADC_CH3 EQU (0x1 << 3) ;- (ADC) Channel 3\r
+AT91C_ADC_CH4 EQU (0x1 << 4) ;- (ADC) Channel 4\r
+AT91C_ADC_CH5 EQU (0x1 << 5) ;- (ADC) Channel 5\r
+AT91C_ADC_CH6 EQU (0x1 << 6) ;- (ADC) Channel 6\r
+AT91C_ADC_CH7 EQU (0x1 << 7) ;- (ADC) Channel 7\r
+// - -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- \r
+// - -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- \r
+// - -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- \r
+AT91C_ADC_EOC0 EQU (0x1 << 0) ;- (ADC) End of Conversion\r
+AT91C_ADC_EOC1 EQU (0x1 << 1) ;- (ADC) End of Conversion\r
+AT91C_ADC_EOC2 EQU (0x1 << 2) ;- (ADC) End of Conversion\r
+AT91C_ADC_EOC3 EQU (0x1 << 3) ;- (ADC) End of Conversion\r
+AT91C_ADC_EOC4 EQU (0x1 << 4) ;- (ADC) End of Conversion\r
+AT91C_ADC_EOC5 EQU (0x1 << 5) ;- (ADC) End of Conversion\r
+AT91C_ADC_EOC6 EQU (0x1 << 6) ;- (ADC) End of Conversion\r
+AT91C_ADC_EOC7 EQU (0x1 << 7) ;- (ADC) End of Conversion\r
+AT91C_ADC_OVRE0 EQU (0x1 << 8) ;- (ADC) Overrun Error\r
+AT91C_ADC_OVRE1 EQU (0x1 << 9) ;- (ADC) Overrun Error\r
+AT91C_ADC_OVRE2 EQU (0x1 << 10) ;- (ADC) Overrun Error\r
+AT91C_ADC_OVRE3 EQU (0x1 << 11) ;- (ADC) Overrun Error\r
+AT91C_ADC_OVRE4 EQU (0x1 << 12) ;- (ADC) Overrun Error\r
+AT91C_ADC_OVRE5 EQU (0x1 << 13) ;- (ADC) Overrun Error\r
+AT91C_ADC_OVRE6 EQU (0x1 << 14) ;- (ADC) Overrun Error\r
+AT91C_ADC_OVRE7 EQU (0x1 << 15) ;- (ADC) Overrun Error\r
+AT91C_ADC_DRDY EQU (0x1 << 16) ;- (ADC) Data Ready\r
+AT91C_ADC_GOVRE EQU (0x1 << 17) ;- (ADC) General Overrun\r
+AT91C_ADC_ENDRX EQU (0x1 << 18) ;- (ADC) End of Receiver Transfer\r
+AT91C_ADC_RXBUFF EQU (0x1 << 19) ;- (ADC) RXBUFF Interrupt\r
+// - -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- \r
+AT91C_ADC_LDATA EQU (0x3FF << 0) ;- (ADC) Last Data Converted\r
+// - -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- \r
+// - -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- \r
+// - -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- \r
+// - -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- \r
+AT91C_ADC_DATA EQU (0x3FF << 0) ;- (ADC) Converted Data\r
+// - -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- \r
+// - -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- \r
+// - -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- \r
+// - -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- \r
+// - -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- \r
+// - -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- \r
+// - -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- \r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Advanced Encryption Standard\r
+// - *****************************************************************************\r
+// - -------- AES_CR : (AES Offset: 0x0) Control Register -------- \r
+AT91C_AES_START EQU (0x1 << 0) ;- (AES) Starts Processing\r
+AT91C_AES_SWRST EQU (0x1 << 8) ;- (AES) Software Reset\r
+AT91C_AES_LOADSEED EQU (0x1 << 16) ;- (AES) Random Number Generator Seed Loading\r
+// - -------- AES_MR : (AES Offset: 0x4) Mode Register -------- \r
+AT91C_AES_CIPHER EQU (0x1 << 0) ;- (AES) Processing Mode\r
+AT91C_AES_PROCDLY EQU (0xF << 4) ;- (AES) Processing Delay\r
+AT91C_AES_SMOD EQU (0x3 << 8) ;- (AES) Start Mode\r
+AT91C_AES_SMOD_MANUAL EQU (0x0 << 8) ;- (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.\r
+AT91C_AES_SMOD_AUTO EQU (0x1 << 8) ;- (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).\r
+AT91C_AES_SMOD_PDC EQU (0x2 << 8) ;- (AES) PDC Mode (cf datasheet).\r
+AT91C_AES_OPMOD EQU (0x7 << 12) ;- (AES) Operation Mode\r
+AT91C_AES_OPMOD_ECB EQU (0x0 << 12) ;- (AES) ECB Electronic CodeBook mode.\r
+AT91C_AES_OPMOD_CBC EQU (0x1 << 12) ;- (AES) CBC Cipher Block Chaining mode.\r
+AT91C_AES_OPMOD_OFB EQU (0x2 << 12) ;- (AES) OFB Output Feedback mode.\r
+AT91C_AES_OPMOD_CFB EQU (0x3 << 12) ;- (AES) CFB Cipher Feedback mode.\r
+AT91C_AES_OPMOD_CTR EQU (0x4 << 12) ;- (AES) CTR Counter mode.\r
+AT91C_AES_LOD EQU (0x1 << 15) ;- (AES) Last Output Data Mode\r
+AT91C_AES_CFBS EQU (0x7 << 16) ;- (AES) Cipher Feedback Data Size\r
+AT91C_AES_CFBS_128_BIT EQU (0x0 << 16) ;- (AES) 128-bit.\r
+AT91C_AES_CFBS_64_BIT EQU (0x1 << 16) ;- (AES) 64-bit.\r
+AT91C_AES_CFBS_32_BIT EQU (0x2 << 16) ;- (AES) 32-bit.\r
+AT91C_AES_CFBS_16_BIT EQU (0x3 << 16) ;- (AES) 16-bit.\r
+AT91C_AES_CFBS_8_BIT EQU (0x4 << 16) ;- (AES) 8-bit.\r
+AT91C_AES_CKEY EQU (0xF << 20) ;- (AES) Countermeasure Key\r
+AT91C_AES_CTYPE EQU (0x1F << 24) ;- (AES) Countermeasure Type\r
+AT91C_AES_CTYPE_TYPE1_EN EQU (0x1 << 24) ;- (AES) Countermeasure type 1 is enabled.\r
+AT91C_AES_CTYPE_TYPE2_EN EQU (0x2 << 24) ;- (AES) Countermeasure type 2 is enabled.\r
+AT91C_AES_CTYPE_TYPE3_EN EQU (0x4 << 24) ;- (AES) Countermeasure type 3 is enabled.\r
+AT91C_AES_CTYPE_TYPE4_EN EQU (0x8 << 24) ;- (AES) Countermeasure type 4 is enabled.\r
+AT91C_AES_CTYPE_TYPE5_EN EQU (0x10 << 24) ;- (AES) Countermeasure type 5 is enabled.\r
+// - -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- \r
+AT91C_AES_DATRDY EQU (0x1 << 0) ;- (AES) DATRDY\r
+AT91C_AES_ENDRX EQU (0x1 << 1) ;- (AES) PDC Read Buffer End\r
+AT91C_AES_ENDTX EQU (0x1 << 2) ;- (AES) PDC Write Buffer End\r
+AT91C_AES_RXBUFF EQU (0x1 << 3) ;- (AES) PDC Read Buffer Full\r
+AT91C_AES_TXBUFE EQU (0x1 << 4) ;- (AES) PDC Write Buffer Empty\r
+AT91C_AES_URAD EQU (0x1 << 8) ;- (AES) Unspecified Register Access Detection\r
+// - -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- \r
+// - -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- \r
+// - -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- \r
+AT91C_AES_URAT EQU (0x7 << 12) ;- (AES) Unspecified Register Access Type Status\r
+AT91C_AES_URAT_IN_DAT_WRITE_DATPROC EQU (0x0 << 12) ;- (AES) Input data register written during the data processing in PDC mode.\r
+AT91C_AES_URAT_OUT_DAT_READ_DATPROC EQU (0x1 << 12) ;- (AES) Output data register read during the data processing.\r
+AT91C_AES_URAT_MODEREG_WRITE_DATPROC EQU (0x2 << 12) ;- (AES) Mode register written during the data processing.\r
+AT91C_AES_URAT_OUT_DAT_READ_SUBKEY EQU (0x3 << 12) ;- (AES) Output data register read during the sub-keys generation.\r
+AT91C_AES_URAT_MODEREG_WRITE_SUBKEY EQU (0x4 << 12) ;- (AES) Mode register written during the sub-keys generation.\r
+AT91C_AES_URAT_WO_REG_READ EQU (0x5 << 12) ;- (AES) Write-only register read access.\r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Triple Data Encryption Standard\r
+// - *****************************************************************************\r
+// - -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- \r
+AT91C_TDES_START EQU (0x1 << 0) ;- (TDES) Starts Processing\r
+AT91C_TDES_SWRST EQU (0x1 << 8) ;- (TDES) Software Reset\r
+// - -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- \r
+AT91C_TDES_CIPHER EQU (0x1 << 0) ;- (TDES) Processing Mode\r
+AT91C_TDES_TDESMOD EQU (0x1 << 1) ;- (TDES) Single or Triple DES Mode\r
+AT91C_TDES_KEYMOD EQU (0x1 << 4) ;- (TDES) Key Mode\r
+AT91C_TDES_SMOD EQU (0x3 << 8) ;- (TDES) Start Mode\r
+AT91C_TDES_SMOD_MANUAL EQU (0x0 << 8) ;- (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.\r
+AT91C_TDES_SMOD_AUTO EQU (0x1 << 8) ;- (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).\r
+AT91C_TDES_SMOD_PDC EQU (0x2 << 8) ;- (TDES) PDC Mode (cf datasheet).\r
+AT91C_TDES_OPMOD EQU (0x3 << 12) ;- (TDES) Operation Mode\r
+AT91C_TDES_OPMOD_ECB EQU (0x0 << 12) ;- (TDES) ECB Electronic CodeBook mode.\r
+AT91C_TDES_OPMOD_CBC EQU (0x1 << 12) ;- (TDES) CBC Cipher Block Chaining mode.\r
+AT91C_TDES_OPMOD_OFB EQU (0x2 << 12) ;- (TDES) OFB Output Feedback mode.\r
+AT91C_TDES_OPMOD_CFB EQU (0x3 << 12) ;- (TDES) CFB Cipher Feedback mode.\r
+AT91C_TDES_LOD EQU (0x1 << 15) ;- (TDES) Last Output Data Mode\r
+AT91C_TDES_CFBS EQU (0x3 << 16) ;- (TDES) Cipher Feedback Data Size\r
+AT91C_TDES_CFBS_64_BIT EQU (0x0 << 16) ;- (TDES) 64-bit.\r
+AT91C_TDES_CFBS_32_BIT EQU (0x1 << 16) ;- (TDES) 32-bit.\r
+AT91C_TDES_CFBS_16_BIT EQU (0x2 << 16) ;- (TDES) 16-bit.\r
+AT91C_TDES_CFBS_8_BIT EQU (0x3 << 16) ;- (TDES) 8-bit.\r
+// - -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- \r
+AT91C_TDES_DATRDY EQU (0x1 << 0) ;- (TDES) DATRDY\r
+AT91C_TDES_ENDRX EQU (0x1 << 1) ;- (TDES) PDC Read Buffer End\r
+AT91C_TDES_ENDTX EQU (0x1 << 2) ;- (TDES) PDC Write Buffer End\r
+AT91C_TDES_RXBUFF EQU (0x1 << 3) ;- (TDES) PDC Read Buffer Full\r
+AT91C_TDES_TXBUFE EQU (0x1 << 4) ;- (TDES) PDC Write Buffer Empty\r
+AT91C_TDES_URAD EQU (0x1 << 8) ;- (TDES) Unspecified Register Access Detection\r
+// - -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- \r
+// - -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- \r
+// - -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- \r
+AT91C_TDES_URAT EQU (0x3 << 12) ;- (TDES) Unspecified Register Access Type Status\r
+AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC EQU (0x0 << 12) ;- (TDES) Input data register written during the data processing in PDC mode.\r
+AT91C_TDES_URAT_OUT_DAT_READ_DATPROC EQU (0x1 << 12) ;- (TDES) Output data register read during the data processing.\r
+AT91C_TDES_URAT_MODEREG_WRITE_DATPROC EQU (0x2 << 12) ;- (TDES) Mode register written during the data processing.\r
+AT91C_TDES_URAT_WO_REG_READ EQU (0x3 << 12) ;- (TDES) Write-only register read access.\r
+\r
+// - *****************************************************************************\r
+// - REGISTER ADDRESS DEFINITION FOR AT91SAM7X256\r
+// - *****************************************************************************\r
+// - ========== Register definition for SYS peripheral ========== \r
+// - ========== Register definition for AIC peripheral ========== \r
+AT91C_AIC_IVR EQU (0xFFFFF100) ;- (AIC) IRQ Vector Register\r
+AT91C_AIC_SMR EQU (0xFFFFF000) ;- (AIC) Source Mode Register\r
+AT91C_AIC_FVR EQU (0xFFFFF104) ;- (AIC) FIQ Vector Register\r
+AT91C_AIC_DCR EQU (0xFFFFF138) ;- (AIC) Debug Control Register (Protect)\r
+AT91C_AIC_EOICR EQU (0xFFFFF130) ;- (AIC) End of Interrupt Command Register\r
+AT91C_AIC_SVR EQU (0xFFFFF080) ;- (AIC) Source Vector Register\r
+AT91C_AIC_FFSR EQU (0xFFFFF148) ;- (AIC) Fast Forcing Status Register\r
+AT91C_AIC_ICCR EQU (0xFFFFF128) ;- (AIC) Interrupt Clear Command Register\r
+AT91C_AIC_ISR EQU (0xFFFFF108) ;- (AIC) Interrupt Status Register\r
+AT91C_AIC_IMR EQU (0xFFFFF110) ;- (AIC) Interrupt Mask Register\r
+AT91C_AIC_IPR EQU (0xFFFFF10C) ;- (AIC) Interrupt Pending Register\r
+AT91C_AIC_FFER EQU (0xFFFFF140) ;- (AIC) Fast Forcing Enable Register\r
+AT91C_AIC_IECR EQU (0xFFFFF120) ;- (AIC) Interrupt Enable Command Register\r
+AT91C_AIC_ISCR EQU (0xFFFFF12C) ;- (AIC) Interrupt Set Command Register\r
+AT91C_AIC_FFDR EQU (0xFFFFF144) ;- (AIC) Fast Forcing Disable Register\r
+AT91C_AIC_CISR EQU (0xFFFFF114) ;- (AIC) Core Interrupt Status Register\r
+AT91C_AIC_IDCR EQU (0xFFFFF124) ;- (AIC) Interrupt Disable Command Register\r
+AT91C_AIC_SPU EQU (0xFFFFF134) ;- (AIC) Spurious Vector Register\r
+// - ========== Register definition for PDC_DBGU peripheral ========== \r
+AT91C_DBGU_TCR EQU (0xFFFFF30C) ;- (PDC_DBGU) Transmit Counter Register\r
+AT91C_DBGU_RNPR EQU (0xFFFFF310) ;- (PDC_DBGU) Receive Next Pointer Register\r
+AT91C_DBGU_TNPR EQU (0xFFFFF318) ;- (PDC_DBGU) Transmit Next Pointer Register\r
+AT91C_DBGU_TPR EQU (0xFFFFF308) ;- (PDC_DBGU) Transmit Pointer Register\r
+AT91C_DBGU_RPR EQU (0xFFFFF300) ;- (PDC_DBGU) Receive Pointer Register\r
+AT91C_DBGU_RCR EQU (0xFFFFF304) ;- (PDC_DBGU) Receive Counter Register\r
+AT91C_DBGU_RNCR EQU (0xFFFFF314) ;- (PDC_DBGU) Receive Next Counter Register\r
+AT91C_DBGU_PTCR EQU (0xFFFFF320) ;- (PDC_DBGU) PDC Transfer Control Register\r
+AT91C_DBGU_PTSR EQU (0xFFFFF324) ;- (PDC_DBGU) PDC Transfer Status Register\r
+AT91C_DBGU_TNCR EQU (0xFFFFF31C) ;- (PDC_DBGU) Transmit Next Counter Register\r
+// - ========== Register definition for DBGU peripheral ========== \r
+AT91C_DBGU_EXID EQU (0xFFFFF244) ;- (DBGU) Chip ID Extension Register\r
+AT91C_DBGU_BRGR EQU (0xFFFFF220) ;- (DBGU) Baud Rate Generator Register\r
+AT91C_DBGU_IDR EQU (0xFFFFF20C) ;- (DBGU) Interrupt Disable Register\r
+AT91C_DBGU_CSR EQU (0xFFFFF214) ;- (DBGU) Channel Status Register\r
+AT91C_DBGU_CIDR EQU (0xFFFFF240) ;- (DBGU) Chip ID Register\r
+AT91C_DBGU_MR EQU (0xFFFFF204) ;- (DBGU) Mode Register\r
+AT91C_DBGU_IMR EQU (0xFFFFF210) ;- (DBGU) Interrupt Mask Register\r
+AT91C_DBGU_CR EQU (0xFFFFF200) ;- (DBGU) Control Register\r
+AT91C_DBGU_FNTR EQU (0xFFFFF248) ;- (DBGU) Force NTRST Register\r
+AT91C_DBGU_THR EQU (0xFFFFF21C) ;- (DBGU) Transmitter Holding Register\r
+AT91C_DBGU_RHR EQU (0xFFFFF218) ;- (DBGU) Receiver Holding Register\r
+AT91C_DBGU_IER EQU (0xFFFFF208) ;- (DBGU) Interrupt Enable Register\r
+// - ========== Register definition for PIOA peripheral ========== \r
+AT91C_PIOA_ODR EQU (0xFFFFF414) ;- (PIOA) Output Disable Registerr\r
+AT91C_PIOA_SODR EQU (0xFFFFF430) ;- (PIOA) Set Output Data Register\r
+AT91C_PIOA_ISR EQU (0xFFFFF44C) ;- (PIOA) Interrupt Status Register\r
+AT91C_PIOA_ABSR EQU (0xFFFFF478) ;- (PIOA) AB Select Status Register\r
+AT91C_PIOA_IER EQU (0xFFFFF440) ;- (PIOA) Interrupt Enable Register\r
+AT91C_PIOA_PPUDR EQU (0xFFFFF460) ;- (PIOA) Pull-up Disable Register\r
+AT91C_PIOA_IMR EQU (0xFFFFF448) ;- (PIOA) Interrupt Mask Register\r
+AT91C_PIOA_PER EQU (0xFFFFF400) ;- (PIOA) PIO Enable Register\r
+AT91C_PIOA_IFDR EQU (0xFFFFF424) ;- (PIOA) Input Filter Disable Register\r
+AT91C_PIOA_OWDR EQU (0xFFFFF4A4) ;- (PIOA) Output Write Disable Register\r
+AT91C_PIOA_MDSR EQU (0xFFFFF458) ;- (PIOA) Multi-driver Status Register\r
+AT91C_PIOA_IDR EQU (0xFFFFF444) ;- (PIOA) Interrupt Disable Register\r
+AT91C_PIOA_ODSR EQU (0xFFFFF438) ;- (PIOA) Output Data Status Register\r
+AT91C_PIOA_PPUSR EQU (0xFFFFF468) ;- (PIOA) Pull-up Status Register\r
+AT91C_PIOA_OWSR EQU (0xFFFFF4A8) ;- (PIOA) Output Write Status Register\r
+AT91C_PIOA_BSR EQU (0xFFFFF474) ;- (PIOA) Select B Register\r
+AT91C_PIOA_OWER EQU (0xFFFFF4A0) ;- (PIOA) Output Write Enable Register\r
+AT91C_PIOA_IFER EQU (0xFFFFF420) ;- (PIOA) Input Filter Enable Register\r
+AT91C_PIOA_PDSR EQU (0xFFFFF43C) ;- (PIOA) Pin Data Status Register\r
+AT91C_PIOA_PPUER EQU (0xFFFFF464) ;- (PIOA) Pull-up Enable Register\r
+AT91C_PIOA_OSR EQU (0xFFFFF418) ;- (PIOA) Output Status Register\r
+AT91C_PIOA_ASR EQU (0xFFFFF470) ;- (PIOA) Select A Register\r
+AT91C_PIOA_MDDR EQU (0xFFFFF454) ;- (PIOA) Multi-driver Disable Register\r
+AT91C_PIOA_CODR EQU (0xFFFFF434) ;- (PIOA) Clear Output Data Register\r
+AT91C_PIOA_MDER EQU (0xFFFFF450) ;- (PIOA) Multi-driver Enable Register\r
+AT91C_PIOA_PDR EQU (0xFFFFF404) ;- (PIOA) PIO Disable Register\r
+AT91C_PIOA_IFSR EQU (0xFFFFF428) ;- (PIOA) Input Filter Status Register\r
+AT91C_PIOA_OER EQU (0xFFFFF410) ;- (PIOA) Output Enable Register\r
+AT91C_PIOA_PSR EQU (0xFFFFF408) ;- (PIOA) PIO Status Register\r
+// - ========== Register definition for PIOB peripheral ========== \r
+AT91C_PIOB_OWDR EQU (0xFFFFF6A4) ;- (PIOB) Output Write Disable Register\r
+AT91C_PIOB_MDER EQU (0xFFFFF650) ;- (PIOB) Multi-driver Enable Register\r
+AT91C_PIOB_PPUSR EQU (0xFFFFF668) ;- (PIOB) Pull-up Status Register\r
+AT91C_PIOB_IMR EQU (0xFFFFF648) ;- (PIOB) Interrupt Mask Register\r
+AT91C_PIOB_ASR EQU (0xFFFFF670) ;- (PIOB) Select A Register\r
+AT91C_PIOB_PPUDR EQU (0xFFFFF660) ;- (PIOB) Pull-up Disable Register\r
+AT91C_PIOB_PSR EQU (0xFFFFF608) ;- (PIOB) PIO Status Register\r
+AT91C_PIOB_IER EQU (0xFFFFF640) ;- (PIOB) Interrupt Enable Register\r
+AT91C_PIOB_CODR EQU (0xFFFFF634) ;- (PIOB) Clear Output Data Register\r
+AT91C_PIOB_OWER EQU (0xFFFFF6A0) ;- (PIOB) Output Write Enable Register\r
+AT91C_PIOB_ABSR EQU (0xFFFFF678) ;- (PIOB) AB Select Status Register\r
+AT91C_PIOB_IFDR EQU (0xFFFFF624) ;- (PIOB) Input Filter Disable Register\r
+AT91C_PIOB_PDSR EQU (0xFFFFF63C) ;- (PIOB) Pin Data Status Register\r
+AT91C_PIOB_IDR EQU (0xFFFFF644) ;- (PIOB) Interrupt Disable Register\r
+AT91C_PIOB_OWSR EQU (0xFFFFF6A8) ;- (PIOB) Output Write Status Register\r
+AT91C_PIOB_PDR EQU (0xFFFFF604) ;- (PIOB) PIO Disable Register\r
+AT91C_PIOB_ODR EQU (0xFFFFF614) ;- (PIOB) Output Disable Registerr\r
+AT91C_PIOB_IFSR EQU (0xFFFFF628) ;- (PIOB) Input Filter Status Register\r
+AT91C_PIOB_PPUER EQU (0xFFFFF664) ;- (PIOB) Pull-up Enable Register\r
+AT91C_PIOB_SODR EQU (0xFFFFF630) ;- (PIOB) Set Output Data Register\r
+AT91C_PIOB_ISR EQU (0xFFFFF64C) ;- (PIOB) Interrupt Status Register\r
+AT91C_PIOB_ODSR EQU (0xFFFFF638) ;- (PIOB) Output Data Status Register\r
+AT91C_PIOB_OSR EQU (0xFFFFF618) ;- (PIOB) Output Status Register\r
+AT91C_PIOB_MDSR EQU (0xFFFFF658) ;- (PIOB) Multi-driver Status Register\r
+AT91C_PIOB_IFER EQU (0xFFFFF620) ;- (PIOB) Input Filter Enable Register\r
+AT91C_PIOB_BSR EQU (0xFFFFF674) ;- (PIOB) Select B Register\r
+AT91C_PIOB_MDDR EQU (0xFFFFF654) ;- (PIOB) Multi-driver Disable Register\r
+AT91C_PIOB_OER EQU (0xFFFFF610) ;- (PIOB) Output Enable Register\r
+AT91C_PIOB_PER EQU (0xFFFFF600) ;- (PIOB) PIO Enable Register\r
+// - ========== Register definition for CKGR peripheral ========== \r
+AT91C_CKGR_MOR EQU (0xFFFFFC20) ;- (CKGR) Main Oscillator Register\r
+AT91C_CKGR_PLLR EQU (0xFFFFFC2C) ;- (CKGR) PLL Register\r
+AT91C_CKGR_MCFR EQU (0xFFFFFC24) ;- (CKGR) Main Clock Frequency Register\r
+// - ========== Register definition for PMC peripheral ========== \r
+AT91C_PMC_IDR EQU (0xFFFFFC64) ;- (PMC) Interrupt Disable Register\r
+AT91C_PMC_MOR EQU (0xFFFFFC20) ;- (PMC) Main Oscillator Register\r
+AT91C_PMC_PLLR EQU (0xFFFFFC2C) ;- (PMC) PLL Register\r
+AT91C_PMC_PCER EQU (0xFFFFFC10) ;- (PMC) Peripheral Clock Enable Register\r
+AT91C_PMC_PCKR EQU (0xFFFFFC40) ;- (PMC) Programmable Clock Register\r
+AT91C_PMC_MCKR EQU (0xFFFFFC30) ;- (PMC) Master Clock Register\r
+AT91C_PMC_SCDR EQU (0xFFFFFC04) ;- (PMC) System Clock Disable Register\r
+AT91C_PMC_PCDR EQU (0xFFFFFC14) ;- (PMC) Peripheral Clock Disable Register\r
+AT91C_PMC_SCSR EQU (0xFFFFFC08) ;- (PMC) System Clock Status Register\r
+AT91C_PMC_PCSR EQU (0xFFFFFC18) ;- (PMC) Peripheral Clock Status Register\r
+AT91C_PMC_MCFR EQU (0xFFFFFC24) ;- (PMC) Main Clock Frequency Register\r
+AT91C_PMC_SCER EQU (0xFFFFFC00) ;- (PMC) System Clock Enable Register\r
+AT91C_PMC_IMR EQU (0xFFFFFC6C) ;- (PMC) Interrupt Mask Register\r
+AT91C_PMC_IER EQU (0xFFFFFC60) ;- (PMC) Interrupt Enable Register\r
+AT91C_PMC_SR EQU (0xFFFFFC68) ;- (PMC) Status Register\r
+// - ========== Register definition for RSTC peripheral ========== \r
+AT91C_RSTC_RCR EQU (0xFFFFFD00) ;- (RSTC) Reset Control Register\r
+AT91C_RSTC_RMR EQU (0xFFFFFD08) ;- (RSTC) Reset Mode Register\r
+AT91C_RSTC_RSR EQU (0xFFFFFD04) ;- (RSTC) Reset Status Register\r
+// - ========== Register definition for RTTC peripheral ========== \r
+AT91C_RTTC_RTSR EQU (0xFFFFFD2C) ;- (RTTC) Real-time Status Register\r
+AT91C_RTTC_RTMR EQU (0xFFFFFD20) ;- (RTTC) Real-time Mode Register\r
+AT91C_RTTC_RTVR EQU (0xFFFFFD28) ;- (RTTC) Real-time Value Register\r
+AT91C_RTTC_RTAR EQU (0xFFFFFD24) ;- (RTTC) Real-time Alarm Register\r
+// - ========== Register definition for PITC peripheral ========== \r
+AT91C_PITC_PIVR EQU (0xFFFFFD38) ;- (PITC) Period Interval Value Register\r
+AT91C_PITC_PISR EQU (0xFFFFFD34) ;- (PITC) Period Interval Status Register\r
+AT91C_PITC_PIIR EQU (0xFFFFFD3C) ;- (PITC) Period Interval Image Register\r
+AT91C_PITC_PIMR EQU (0xFFFFFD30) ;- (PITC) Period Interval Mode Register\r
+// - ========== Register definition for WDTC peripheral ========== \r
+AT91C_WDTC_WDCR EQU (0xFFFFFD40) ;- (WDTC) Watchdog Control Register\r
+AT91C_WDTC_WDSR EQU (0xFFFFFD48) ;- (WDTC) Watchdog Status Register\r
+AT91C_WDTC_WDMR EQU (0xFFFFFD44) ;- (WDTC) Watchdog Mode Register\r
+// - ========== Register definition for VREG peripheral ========== \r
+AT91C_VREG_MR EQU (0xFFFFFD60) ;- (VREG) Voltage Regulator Mode Register\r
+// - ========== Register definition for MC peripheral ========== \r
+AT91C_MC_ASR EQU (0xFFFFFF04) ;- (MC) MC Abort Status Register\r
+AT91C_MC_RCR EQU (0xFFFFFF00) ;- (MC) MC Remap Control Register\r
+AT91C_MC_FCR EQU (0xFFFFFF64) ;- (MC) MC Flash Command Register\r
+AT91C_MC_AASR EQU (0xFFFFFF08) ;- (MC) MC Abort Address Status Register\r
+AT91C_MC_FSR EQU (0xFFFFFF68) ;- (MC) MC Flash Status Register\r
+AT91C_MC_FMR EQU (0xFFFFFF60) ;- (MC) MC Flash Mode Register\r
+// - ========== Register definition for PDC_SPI1 peripheral ========== \r
+AT91C_SPI1_PTCR EQU (0xFFFE4120) ;- (PDC_SPI1) PDC Transfer Control Register\r
+AT91C_SPI1_RPR EQU (0xFFFE4100) ;- (PDC_SPI1) Receive Pointer Register\r
+AT91C_SPI1_TNCR EQU (0xFFFE411C) ;- (PDC_SPI1) Transmit Next Counter Register\r
+AT91C_SPI1_TPR EQU (0xFFFE4108) ;- (PDC_SPI1) Transmit Pointer Register\r
+AT91C_SPI1_TNPR EQU (0xFFFE4118) ;- (PDC_SPI1) Transmit Next Pointer Register\r
+AT91C_SPI1_TCR EQU (0xFFFE410C) ;- (PDC_SPI1) Transmit Counter Register\r
+AT91C_SPI1_RCR EQU (0xFFFE4104) ;- (PDC_SPI1) Receive Counter Register\r
+AT91C_SPI1_RNPR EQU (0xFFFE4110) ;- (PDC_SPI1) Receive Next Pointer Register\r
+AT91C_SPI1_RNCR EQU (0xFFFE4114) ;- (PDC_SPI1) Receive Next Counter Register\r
+AT91C_SPI1_PTSR EQU (0xFFFE4124) ;- (PDC_SPI1) PDC Transfer Status Register\r
+// - ========== Register definition for SPI1 peripheral ========== \r
+AT91C_SPI1_IMR EQU (0xFFFE401C) ;- (SPI1) Interrupt Mask Register\r
+AT91C_SPI1_IER EQU (0xFFFE4014) ;- (SPI1) Interrupt Enable Register\r
+AT91C_SPI1_MR EQU (0xFFFE4004) ;- (SPI1) Mode Register\r
+AT91C_SPI1_RDR EQU (0xFFFE4008) ;- (SPI1) Receive Data Register\r
+AT91C_SPI1_IDR EQU (0xFFFE4018) ;- (SPI1) Interrupt Disable Register\r
+AT91C_SPI1_SR EQU (0xFFFE4010) ;- (SPI1) Status Register\r
+AT91C_SPI1_TDR EQU (0xFFFE400C) ;- (SPI1) Transmit Data Register\r
+AT91C_SPI1_CR EQU (0xFFFE4000) ;- (SPI1) Control Register\r
+AT91C_SPI1_CSR EQU (0xFFFE4030) ;- (SPI1) Chip Select Register\r
+// - ========== Register definition for PDC_SPI0 peripheral ========== \r
+AT91C_SPI0_PTCR EQU (0xFFFE0120) ;- (PDC_SPI0) PDC Transfer Control Register\r
+AT91C_SPI0_TPR EQU (0xFFFE0108) ;- (PDC_SPI0) Transmit Pointer Register\r
+AT91C_SPI0_TCR EQU (0xFFFE010C) ;- (PDC_SPI0) Transmit Counter Register\r
+AT91C_SPI0_RCR EQU (0xFFFE0104) ;- (PDC_SPI0) Receive Counter Register\r
+AT91C_SPI0_PTSR EQU (0xFFFE0124) ;- (PDC_SPI0) PDC Transfer Status Register\r
+AT91C_SPI0_RNPR EQU (0xFFFE0110) ;- (PDC_SPI0) Receive Next Pointer Register\r
+AT91C_SPI0_RPR EQU (0xFFFE0100) ;- (PDC_SPI0) Receive Pointer Register\r
+AT91C_SPI0_TNCR EQU (0xFFFE011C) ;- (PDC_SPI0) Transmit Next Counter Register\r
+AT91C_SPI0_RNCR EQU (0xFFFE0114) ;- (PDC_SPI0) Receive Next Counter Register\r
+AT91C_SPI0_TNPR EQU (0xFFFE0118) ;- (PDC_SPI0) Transmit Next Pointer Register\r
+// - ========== Register definition for SPI0 peripheral ========== \r
+AT91C_SPI0_IER EQU (0xFFFE0014) ;- (SPI0) Interrupt Enable Register\r
+AT91C_SPI0_SR EQU (0xFFFE0010) ;- (SPI0) Status Register\r
+AT91C_SPI0_IDR EQU (0xFFFE0018) ;- (SPI0) Interrupt Disable Register\r
+AT91C_SPI0_CR EQU (0xFFFE0000) ;- (SPI0) Control Register\r
+AT91C_SPI0_MR EQU (0xFFFE0004) ;- (SPI0) Mode Register\r
+AT91C_SPI0_IMR EQU (0xFFFE001C) ;- (SPI0) Interrupt Mask Register\r
+AT91C_SPI0_TDR EQU (0xFFFE000C) ;- (SPI0) Transmit Data Register\r
+AT91C_SPI0_RDR EQU (0xFFFE0008) ;- (SPI0) Receive Data Register\r
+AT91C_SPI0_CSR EQU (0xFFFE0030) ;- (SPI0) Chip Select Register\r
+// - ========== Register definition for PDC_US1 peripheral ========== \r
+AT91C_US1_RNCR EQU (0xFFFC4114) ;- (PDC_US1) Receive Next Counter Register\r
+AT91C_US1_PTCR EQU (0xFFFC4120) ;- (PDC_US1) PDC Transfer Control Register\r
+AT91C_US1_TCR EQU (0xFFFC410C) ;- (PDC_US1) Transmit Counter Register\r
+AT91C_US1_PTSR EQU (0xFFFC4124) ;- (PDC_US1) PDC Transfer Status Register\r
+AT91C_US1_TNPR EQU (0xFFFC4118) ;- (PDC_US1) Transmit Next Pointer Register\r
+AT91C_US1_RCR EQU (0xFFFC4104) ;- (PDC_US1) Receive Counter Register\r
+AT91C_US1_RNPR EQU (0xFFFC4110) ;- (PDC_US1) Receive Next Pointer Register\r
+AT91C_US1_RPR EQU (0xFFFC4100) ;- (PDC_US1) Receive Pointer Register\r
+AT91C_US1_TNCR EQU (0xFFFC411C) ;- (PDC_US1) Transmit Next Counter Register\r
+AT91C_US1_TPR EQU (0xFFFC4108) ;- (PDC_US1) Transmit Pointer Register\r
+// - ========== Register definition for US1 peripheral ========== \r
+AT91C_US1_IF EQU (0xFFFC404C) ;- (US1) IRDA_FILTER Register\r
+AT91C_US1_NER EQU (0xFFFC4044) ;- (US1) Nb Errors Register\r
+AT91C_US1_RTOR EQU (0xFFFC4024) ;- (US1) Receiver Time-out Register\r
+AT91C_US1_CSR EQU (0xFFFC4014) ;- (US1) Channel Status Register\r
+AT91C_US1_IDR EQU (0xFFFC400C) ;- (US1) Interrupt Disable Register\r
+AT91C_US1_IER EQU (0xFFFC4008) ;- (US1) Interrupt Enable Register\r
+AT91C_US1_THR EQU (0xFFFC401C) ;- (US1) Transmitter Holding Register\r
+AT91C_US1_TTGR EQU (0xFFFC4028) ;- (US1) Transmitter Time-guard Register\r
+AT91C_US1_RHR EQU (0xFFFC4018) ;- (US1) Receiver Holding Register\r
+AT91C_US1_BRGR EQU (0xFFFC4020) ;- (US1) Baud Rate Generator Register\r
+AT91C_US1_IMR EQU (0xFFFC4010) ;- (US1) Interrupt Mask Register\r
+AT91C_US1_FIDI EQU (0xFFFC4040) ;- (US1) FI_DI_Ratio Register\r
+AT91C_US1_CR EQU (0xFFFC4000) ;- (US1) Control Register\r
+AT91C_US1_MR EQU (0xFFFC4004) ;- (US1) Mode Register\r
+// - ========== Register definition for PDC_US0 peripheral ========== \r
+AT91C_US0_TNPR EQU (0xFFFC0118) ;- (PDC_US0) Transmit Next Pointer Register\r
+AT91C_US0_RNPR EQU (0xFFFC0110) ;- (PDC_US0) Receive Next Pointer Register\r
+AT91C_US0_TCR EQU (0xFFFC010C) ;- (PDC_US0) Transmit Counter Register\r
+AT91C_US0_PTCR EQU (0xFFFC0120) ;- (PDC_US0) PDC Transfer Control Register\r
+AT91C_US0_PTSR EQU (0xFFFC0124) ;- (PDC_US0) PDC Transfer Status Register\r
+AT91C_US0_TNCR EQU (0xFFFC011C) ;- (PDC_US0) Transmit Next Counter Register\r
+AT91C_US0_TPR EQU (0xFFFC0108) ;- (PDC_US0) Transmit Pointer Register\r
+AT91C_US0_RCR EQU (0xFFFC0104) ;- (PDC_US0) Receive Counter Register\r
+AT91C_US0_RPR EQU (0xFFFC0100) ;- (PDC_US0) Receive Pointer Register\r
+AT91C_US0_RNCR EQU (0xFFFC0114) ;- (PDC_US0) Receive Next Counter Register\r
+// - ========== Register definition for US0 peripheral ========== \r
+AT91C_US0_BRGR EQU (0xFFFC0020) ;- (US0) Baud Rate Generator Register\r
+AT91C_US0_NER EQU (0xFFFC0044) ;- (US0) Nb Errors Register\r
+AT91C_US0_CR EQU (0xFFFC0000) ;- (US0) Control Register\r
+AT91C_US0_IMR EQU (0xFFFC0010) ;- (US0) Interrupt Mask Register\r
+AT91C_US0_FIDI EQU (0xFFFC0040) ;- (US0) FI_DI_Ratio Register\r
+AT91C_US0_TTGR EQU (0xFFFC0028) ;- (US0) Transmitter Time-guard Register\r
+AT91C_US0_MR EQU (0xFFFC0004) ;- (US0) Mode Register\r
+AT91C_US0_RTOR EQU (0xFFFC0024) ;- (US0) Receiver Time-out Register\r
+AT91C_US0_CSR EQU (0xFFFC0014) ;- (US0) Channel Status Register\r
+AT91C_US0_RHR EQU (0xFFFC0018) ;- (US0) Receiver Holding Register\r
+AT91C_US0_IDR EQU (0xFFFC000C) ;- (US0) Interrupt Disable Register\r
+AT91C_US0_THR EQU (0xFFFC001C) ;- (US0) Transmitter Holding Register\r
+AT91C_US0_IF EQU (0xFFFC004C) ;- (US0) IRDA_FILTER Register\r
+AT91C_US0_IER EQU (0xFFFC0008) ;- (US0) Interrupt Enable Register\r
+// - ========== Register definition for PDC_SSC peripheral ========== \r
+AT91C_SSC_TNCR EQU (0xFFFD411C) ;- (PDC_SSC) Transmit Next Counter Register\r
+AT91C_SSC_RPR EQU (0xFFFD4100) ;- (PDC_SSC) Receive Pointer Register\r
+AT91C_SSC_RNCR EQU (0xFFFD4114) ;- (PDC_SSC) Receive Next Counter Register\r
+AT91C_SSC_TPR EQU (0xFFFD4108) ;- (PDC_SSC) Transmit Pointer Register\r
+AT91C_SSC_PTCR EQU (0xFFFD4120) ;- (PDC_SSC) PDC Transfer Control Register\r
+AT91C_SSC_TCR EQU (0xFFFD410C) ;- (PDC_SSC) Transmit Counter Register\r
+AT91C_SSC_RCR EQU (0xFFFD4104) ;- (PDC_SSC) Receive Counter Register\r
+AT91C_SSC_RNPR EQU (0xFFFD4110) ;- (PDC_SSC) Receive Next Pointer Register\r
+AT91C_SSC_TNPR EQU (0xFFFD4118) ;- (PDC_SSC) Transmit Next Pointer Register\r
+AT91C_SSC_PTSR EQU (0xFFFD4124) ;- (PDC_SSC) PDC Transfer Status Register\r
+// - ========== Register definition for SSC peripheral ========== \r
+AT91C_SSC_RHR EQU (0xFFFD4020) ;- (SSC) Receive Holding Register\r
+AT91C_SSC_RSHR EQU (0xFFFD4030) ;- (SSC) Receive Sync Holding Register\r
+AT91C_SSC_TFMR EQU (0xFFFD401C) ;- (SSC) Transmit Frame Mode Register\r
+AT91C_SSC_IDR EQU (0xFFFD4048) ;- (SSC) Interrupt Disable Register\r
+AT91C_SSC_THR EQU (0xFFFD4024) ;- (SSC) Transmit Holding Register\r
+AT91C_SSC_RCMR EQU (0xFFFD4010) ;- (SSC) Receive Clock ModeRegister\r
+AT91C_SSC_IER EQU (0xFFFD4044) ;- (SSC) Interrupt Enable Register\r
+AT91C_SSC_TSHR EQU (0xFFFD4034) ;- (SSC) Transmit Sync Holding Register\r
+AT91C_SSC_SR EQU (0xFFFD4040) ;- (SSC) Status Register\r
+AT91C_SSC_CMR EQU (0xFFFD4004) ;- (SSC) Clock Mode Register\r
+AT91C_SSC_TCMR EQU (0xFFFD4018) ;- (SSC) Transmit Clock Mode Register\r
+AT91C_SSC_CR EQU (0xFFFD4000) ;- (SSC) Control Register\r
+AT91C_SSC_IMR EQU (0xFFFD404C) ;- (SSC) Interrupt Mask Register\r
+AT91C_SSC_RFMR EQU (0xFFFD4014) ;- (SSC) Receive Frame Mode Register\r
+// - ========== Register definition for TWI peripheral ========== \r
+AT91C_TWI_IER EQU (0xFFFB8024) ;- (TWI) Interrupt Enable Register\r
+AT91C_TWI_CR EQU (0xFFFB8000) ;- (TWI) Control Register\r
+AT91C_TWI_SR EQU (0xFFFB8020) ;- (TWI) Status Register\r
+AT91C_TWI_IMR EQU (0xFFFB802C) ;- (TWI) Interrupt Mask Register\r
+AT91C_TWI_THR EQU (0xFFFB8034) ;- (TWI) Transmit Holding Register\r
+AT91C_TWI_IDR EQU (0xFFFB8028) ;- (TWI) Interrupt Disable Register\r
+AT91C_TWI_IADR EQU (0xFFFB800C) ;- (TWI) Internal Address Register\r
+AT91C_TWI_MMR EQU (0xFFFB8004) ;- (TWI) Master Mode Register\r
+AT91C_TWI_CWGR EQU (0xFFFB8010) ;- (TWI) Clock Waveform Generator Register\r
+AT91C_TWI_RHR EQU (0xFFFB8030) ;- (TWI) Receive Holding Register\r
+// - ========== Register definition for PWMC_CH3 peripheral ========== \r
+AT91C_PWMC_CH3_CUPDR EQU (0xFFFCC270) ;- (PWMC_CH3) Channel Update Register\r
+AT91C_PWMC_CH3_Reserved EQU (0xFFFCC274) ;- (PWMC_CH3) Reserved\r
+AT91C_PWMC_CH3_CPRDR EQU (0xFFFCC268) ;- (PWMC_CH3) Channel Period Register\r
+AT91C_PWMC_CH3_CDTYR EQU (0xFFFCC264) ;- (PWMC_CH3) Channel Duty Cycle Register\r
+AT91C_PWMC_CH3_CCNTR EQU (0xFFFCC26C) ;- (PWMC_CH3) Channel Counter Register\r
+AT91C_PWMC_CH3_CMR EQU (0xFFFCC260) ;- (PWMC_CH3) Channel Mode Register\r
+// - ========== Register definition for PWMC_CH2 peripheral ========== \r
+AT91C_PWMC_CH2_Reserved EQU (0xFFFCC254) ;- (PWMC_CH2) Reserved\r
+AT91C_PWMC_CH2_CMR EQU (0xFFFCC240) ;- (PWMC_CH2) Channel Mode Register\r
+AT91C_PWMC_CH2_CCNTR EQU (0xFFFCC24C) ;- (PWMC_CH2) Channel Counter Register\r
+AT91C_PWMC_CH2_CPRDR EQU (0xFFFCC248) ;- (PWMC_CH2) Channel Period Register\r
+AT91C_PWMC_CH2_CUPDR EQU (0xFFFCC250) ;- (PWMC_CH2) Channel Update Register\r
+AT91C_PWMC_CH2_CDTYR EQU (0xFFFCC244) ;- (PWMC_CH2) Channel Duty Cycle Register\r
+// - ========== Register definition for PWMC_CH1 peripheral ========== \r
+AT91C_PWMC_CH1_Reserved EQU (0xFFFCC234) ;- (PWMC_CH1) Reserved\r
+AT91C_PWMC_CH1_CUPDR EQU (0xFFFCC230) ;- (PWMC_CH1) Channel Update Register\r
+AT91C_PWMC_CH1_CPRDR EQU (0xFFFCC228) ;- (PWMC_CH1) Channel Period Register\r
+AT91C_PWMC_CH1_CCNTR EQU (0xFFFCC22C) ;- (PWMC_CH1) Channel Counter Register\r
+AT91C_PWMC_CH1_CDTYR EQU (0xFFFCC224) ;- (PWMC_CH1) Channel Duty Cycle Register\r
+AT91C_PWMC_CH1_CMR EQU (0xFFFCC220) ;- (PWMC_CH1) Channel Mode Register\r
+// - ========== Register definition for PWMC_CH0 peripheral ========== \r
+AT91C_PWMC_CH0_Reserved EQU (0xFFFCC214) ;- (PWMC_CH0) Reserved\r
+AT91C_PWMC_CH0_CPRDR EQU (0xFFFCC208) ;- (PWMC_CH0) Channel Period Register\r
+AT91C_PWMC_CH0_CDTYR EQU (0xFFFCC204) ;- (PWMC_CH0) Channel Duty Cycle Register\r
+AT91C_PWMC_CH0_CMR EQU (0xFFFCC200) ;- (PWMC_CH0) Channel Mode Register\r
+AT91C_PWMC_CH0_CUPDR EQU (0xFFFCC210) ;- (PWMC_CH0) Channel Update Register\r
+AT91C_PWMC_CH0_CCNTR EQU (0xFFFCC20C) ;- (PWMC_CH0) Channel Counter Register\r
+// - ========== Register definition for PWMC peripheral ========== \r
+AT91C_PWMC_IDR EQU (0xFFFCC014) ;- (PWMC) PWMC Interrupt Disable Register\r
+AT91C_PWMC_DIS EQU (0xFFFCC008) ;- (PWMC) PWMC Disable Register\r
+AT91C_PWMC_IER EQU (0xFFFCC010) ;- (PWMC) PWMC Interrupt Enable Register\r
+AT91C_PWMC_VR EQU (0xFFFCC0FC) ;- (PWMC) PWMC Version Register\r
+AT91C_PWMC_ISR EQU (0xFFFCC01C) ;- (PWMC) PWMC Interrupt Status Register\r
+AT91C_PWMC_SR EQU (0xFFFCC00C) ;- (PWMC) PWMC Status Register\r
+AT91C_PWMC_IMR EQU (0xFFFCC018) ;- (PWMC) PWMC Interrupt Mask Register\r
+AT91C_PWMC_MR EQU (0xFFFCC000) ;- (PWMC) PWMC Mode Register\r
+AT91C_PWMC_ENA EQU (0xFFFCC004) ;- (PWMC) PWMC Enable Register\r
+// - ========== Register definition for UDP peripheral ========== \r
+AT91C_UDP_IMR EQU (0xFFFB0018) ;- (UDP) Interrupt Mask Register\r
+AT91C_UDP_FADDR EQU (0xFFFB0008) ;- (UDP) Function Address Register\r
+AT91C_UDP_NUM EQU (0xFFFB0000) ;- (UDP) Frame Number Register\r
+AT91C_UDP_FDR EQU (0xFFFB0050) ;- (UDP) Endpoint FIFO Data Register\r
+AT91C_UDP_ISR EQU (0xFFFB001C) ;- (UDP) Interrupt Status Register\r
+AT91C_UDP_CSR EQU (0xFFFB0030) ;- (UDP) Endpoint Control and Status Register\r
+AT91C_UDP_IDR EQU (0xFFFB0014) ;- (UDP) Interrupt Disable Register\r
+AT91C_UDP_ICR EQU (0xFFFB0020) ;- (UDP) Interrupt Clear Register\r
+AT91C_UDP_RSTEP EQU (0xFFFB0028) ;- (UDP) Reset Endpoint Register\r
+AT91C_UDP_TXVC EQU (0xFFFB0074) ;- (UDP) Transceiver Control Register\r
+AT91C_UDP_GLBSTATE EQU (0xFFFB0004) ;- (UDP) Global State Register\r
+AT91C_UDP_IER EQU (0xFFFB0010) ;- (UDP) Interrupt Enable Register\r
+// - ========== Register definition for TC0 peripheral ========== \r
+AT91C_TC0_SR EQU (0xFFFA0020) ;- (TC0) Status Register\r
+AT91C_TC0_RC EQU (0xFFFA001C) ;- (TC0) Register C\r
+AT91C_TC0_RB EQU (0xFFFA0018) ;- (TC0) Register B\r
+AT91C_TC0_CCR EQU (0xFFFA0000) ;- (TC0) Channel Control Register\r
+AT91C_TC0_CMR EQU (0xFFFA0004) ;- (TC0) Channel Mode Register (Capture Mode / Waveform Mode)\r
+AT91C_TC0_IER EQU (0xFFFA0024) ;- (TC0) Interrupt Enable Register\r
+AT91C_TC0_RA EQU (0xFFFA0014) ;- (TC0) Register A\r
+AT91C_TC0_IDR EQU (0xFFFA0028) ;- (TC0) Interrupt Disable Register\r
+AT91C_TC0_CV EQU (0xFFFA0010) ;- (TC0) Counter Value\r
+AT91C_TC0_IMR EQU (0xFFFA002C) ;- (TC0) Interrupt Mask Register\r
+// - ========== Register definition for TC1 peripheral ========== \r
+AT91C_TC1_RB EQU (0xFFFA0058) ;- (TC1) Register B\r
+AT91C_TC1_CCR EQU (0xFFFA0040) ;- (TC1) Channel Control Register\r
+AT91C_TC1_IER EQU (0xFFFA0064) ;- (TC1) Interrupt Enable Register\r
+AT91C_TC1_IDR EQU (0xFFFA0068) ;- (TC1) Interrupt Disable Register\r
+AT91C_TC1_SR EQU (0xFFFA0060) ;- (TC1) Status Register\r
+AT91C_TC1_CMR EQU (0xFFFA0044) ;- (TC1) Channel Mode Register (Capture Mode / Waveform Mode)\r
+AT91C_TC1_RA EQU (0xFFFA0054) ;- (TC1) Register A\r
+AT91C_TC1_RC EQU (0xFFFA005C) ;- (TC1) Register C\r
+AT91C_TC1_IMR EQU (0xFFFA006C) ;- (TC1) Interrupt Mask Register\r
+AT91C_TC1_CV EQU (0xFFFA0050) ;- (TC1) Counter Value\r
+// - ========== Register definition for TC2 peripheral ========== \r
+AT91C_TC2_CMR EQU (0xFFFA0084) ;- (TC2) Channel Mode Register (Capture Mode / Waveform Mode)\r
+AT91C_TC2_CCR EQU (0xFFFA0080) ;- (TC2) Channel Control Register\r
+AT91C_TC2_CV EQU (0xFFFA0090) ;- (TC2) Counter Value\r
+AT91C_TC2_RA EQU (0xFFFA0094) ;- (TC2) Register A\r
+AT91C_TC2_RB EQU (0xFFFA0098) ;- (TC2) Register B\r
+AT91C_TC2_IDR EQU (0xFFFA00A8) ;- (TC2) Interrupt Disable Register\r
+AT91C_TC2_IMR EQU (0xFFFA00AC) ;- (TC2) Interrupt Mask Register\r
+AT91C_TC2_RC EQU (0xFFFA009C) ;- (TC2) Register C\r
+AT91C_TC2_IER EQU (0xFFFA00A4) ;- (TC2) Interrupt Enable Register\r
+AT91C_TC2_SR EQU (0xFFFA00A0) ;- (TC2) Status Register\r
+// - ========== Register definition for TCB peripheral ========== \r
+AT91C_TCB_BMR EQU (0xFFFA00C4) ;- (TCB) TC Block Mode Register\r
+AT91C_TCB_BCR EQU (0xFFFA00C0) ;- (TCB) TC Block Control Register\r
+// - ========== Register definition for CAN_MB0 peripheral ========== \r
+AT91C_CAN_MB0_MDL EQU (0xFFFD0214) ;- (CAN_MB0) MailBox Data Low Register\r
+AT91C_CAN_MB0_MAM EQU (0xFFFD0204) ;- (CAN_MB0) MailBox Acceptance Mask Register\r
+AT91C_CAN_MB0_MCR EQU (0xFFFD021C) ;- (CAN_MB0) MailBox Control Register\r
+AT91C_CAN_MB0_MID EQU (0xFFFD0208) ;- (CAN_MB0) MailBox ID Register\r
+AT91C_CAN_MB0_MSR EQU (0xFFFD0210) ;- (CAN_MB0) MailBox Status Register\r
+AT91C_CAN_MB0_MFID EQU (0xFFFD020C) ;- (CAN_MB0) MailBox Family ID Register\r
+AT91C_CAN_MB0_MDH EQU (0xFFFD0218) ;- (CAN_MB0) MailBox Data High Register\r
+AT91C_CAN_MB0_MMR EQU (0xFFFD0200) ;- (CAN_MB0) MailBox Mode Register\r
+// - ========== Register definition for CAN_MB1 peripheral ========== \r
+AT91C_CAN_MB1_MDL EQU (0xFFFD0234) ;- (CAN_MB1) MailBox Data Low Register\r
+AT91C_CAN_MB1_MID EQU (0xFFFD0228) ;- (CAN_MB1) MailBox ID Register\r
+AT91C_CAN_MB1_MMR EQU (0xFFFD0220) ;- (CAN_MB1) MailBox Mode Register\r
+AT91C_CAN_MB1_MSR EQU (0xFFFD0230) ;- (CAN_MB1) MailBox Status Register\r
+AT91C_CAN_MB1_MAM EQU (0xFFFD0224) ;- (CAN_MB1) MailBox Acceptance Mask Register\r
+AT91C_CAN_MB1_MDH EQU (0xFFFD0238) ;- (CAN_MB1) MailBox Data High Register\r
+AT91C_CAN_MB1_MCR EQU (0xFFFD023C) ;- (CAN_MB1) MailBox Control Register\r
+AT91C_CAN_MB1_MFID EQU (0xFFFD022C) ;- (CAN_MB1) MailBox Family ID Register\r
+// - ========== Register definition for CAN_MB2 peripheral ========== \r
+AT91C_CAN_MB2_MCR EQU (0xFFFD025C) ;- (CAN_MB2) MailBox Control Register\r
+AT91C_CAN_MB2_MDH EQU (0xFFFD0258) ;- (CAN_MB2) MailBox Data High Register\r
+AT91C_CAN_MB2_MID EQU (0xFFFD0248) ;- (CAN_MB2) MailBox ID Register\r
+AT91C_CAN_MB2_MDL EQU (0xFFFD0254) ;- (CAN_MB2) MailBox Data Low Register\r
+AT91C_CAN_MB2_MMR EQU (0xFFFD0240) ;- (CAN_MB2) MailBox Mode Register\r
+AT91C_CAN_MB2_MAM EQU (0xFFFD0244) ;- (CAN_MB2) MailBox Acceptance Mask Register\r
+AT91C_CAN_MB2_MFID EQU (0xFFFD024C) ;- (CAN_MB2) MailBox Family ID Register\r
+AT91C_CAN_MB2_MSR EQU (0xFFFD0250) ;- (CAN_MB2) MailBox Status Register\r
+// - ========== Register definition for CAN_MB3 peripheral ========== \r
+AT91C_CAN_MB3_MFID EQU (0xFFFD026C) ;- (CAN_MB3) MailBox Family ID Register\r
+AT91C_CAN_MB3_MAM EQU (0xFFFD0264) ;- (CAN_MB3) MailBox Acceptance Mask Register\r
+AT91C_CAN_MB3_MID EQU (0xFFFD0268) ;- (CAN_MB3) MailBox ID Register\r
+AT91C_CAN_MB3_MCR EQU (0xFFFD027C) ;- (CAN_MB3) MailBox Control Register\r
+AT91C_CAN_MB3_MMR EQU (0xFFFD0260) ;- (CAN_MB3) MailBox Mode Register\r
+AT91C_CAN_MB3_MSR EQU (0xFFFD0270) ;- (CAN_MB3) MailBox Status Register\r
+AT91C_CAN_MB3_MDL EQU (0xFFFD0274) ;- (CAN_MB3) MailBox Data Low Register\r
+AT91C_CAN_MB3_MDH EQU (0xFFFD0278) ;- (CAN_MB3) MailBox Data High Register\r
+// - ========== Register definition for CAN_MB4 peripheral ========== \r
+AT91C_CAN_MB4_MID EQU (0xFFFD0288) ;- (CAN_MB4) MailBox ID Register\r
+AT91C_CAN_MB4_MMR EQU (0xFFFD0280) ;- (CAN_MB4) MailBox Mode Register\r
+AT91C_CAN_MB4_MDH EQU (0xFFFD0298) ;- (CAN_MB4) MailBox Data High Register\r
+AT91C_CAN_MB4_MFID EQU (0xFFFD028C) ;- (CAN_MB4) MailBox Family ID Register\r
+AT91C_CAN_MB4_MSR EQU (0xFFFD0290) ;- (CAN_MB4) MailBox Status Register\r
+AT91C_CAN_MB4_MCR EQU (0xFFFD029C) ;- (CAN_MB4) MailBox Control Register\r
+AT91C_CAN_MB4_MDL EQU (0xFFFD0294) ;- (CAN_MB4) MailBox Data Low Register\r
+AT91C_CAN_MB4_MAM EQU (0xFFFD0284) ;- (CAN_MB4) MailBox Acceptance Mask Register\r
+// - ========== Register definition for CAN_MB5 peripheral ========== \r
+AT91C_CAN_MB5_MSR EQU (0xFFFD02B0) ;- (CAN_MB5) MailBox Status Register\r
+AT91C_CAN_MB5_MCR EQU (0xFFFD02BC) ;- (CAN_MB5) MailBox Control Register\r
+AT91C_CAN_MB5_MFID EQU (0xFFFD02AC) ;- (CAN_MB5) MailBox Family ID Register\r
+AT91C_CAN_MB5_MDH EQU (0xFFFD02B8) ;- (CAN_MB5) MailBox Data High Register\r
+AT91C_CAN_MB5_MID EQU (0xFFFD02A8) ;- (CAN_MB5) MailBox ID Register\r
+AT91C_CAN_MB5_MMR EQU (0xFFFD02A0) ;- (CAN_MB5) MailBox Mode Register\r
+AT91C_CAN_MB5_MDL EQU (0xFFFD02B4) ;- (CAN_MB5) MailBox Data Low Register\r
+AT91C_CAN_MB5_MAM EQU (0xFFFD02A4) ;- (CAN_MB5) MailBox Acceptance Mask Register\r
+// - ========== Register definition for CAN_MB6 peripheral ========== \r
+AT91C_CAN_MB6_MFID EQU (0xFFFD02CC) ;- (CAN_MB6) MailBox Family ID Register\r
+AT91C_CAN_MB6_MID EQU (0xFFFD02C8) ;- (CAN_MB6) MailBox ID Register\r
+AT91C_CAN_MB6_MAM EQU (0xFFFD02C4) ;- (CAN_MB6) MailBox Acceptance Mask Register\r
+AT91C_CAN_MB6_MSR EQU (0xFFFD02D0) ;- (CAN_MB6) MailBox Status Register\r
+AT91C_CAN_MB6_MDL EQU (0xFFFD02D4) ;- (CAN_MB6) MailBox Data Low Register\r
+AT91C_CAN_MB6_MCR EQU (0xFFFD02DC) ;- (CAN_MB6) MailBox Control Register\r
+AT91C_CAN_MB6_MDH EQU (0xFFFD02D8) ;- (CAN_MB6) MailBox Data High Register\r
+AT91C_CAN_MB6_MMR EQU (0xFFFD02C0) ;- (CAN_MB6) MailBox Mode Register\r
+// - ========== Register definition for CAN_MB7 peripheral ========== \r
+AT91C_CAN_MB7_MCR EQU (0xFFFD02FC) ;- (CAN_MB7) MailBox Control Register\r
+AT91C_CAN_MB7_MDH EQU (0xFFFD02F8) ;- (CAN_MB7) MailBox Data High Register\r
+AT91C_CAN_MB7_MFID EQU (0xFFFD02EC) ;- (CAN_MB7) MailBox Family ID Register\r
+AT91C_CAN_MB7_MDL EQU (0xFFFD02F4) ;- (CAN_MB7) MailBox Data Low Register\r
+AT91C_CAN_MB7_MID EQU (0xFFFD02E8) ;- (CAN_MB7) MailBox ID Register\r
+AT91C_CAN_MB7_MMR EQU (0xFFFD02E0) ;- (CAN_MB7) MailBox Mode Register\r
+AT91C_CAN_MB7_MAM EQU (0xFFFD02E4) ;- (CAN_MB7) MailBox Acceptance Mask Register\r
+AT91C_CAN_MB7_MSR EQU (0xFFFD02F0) ;- (CAN_MB7) MailBox Status Register\r
+// - ========== Register definition for CAN peripheral ========== \r
+AT91C_CAN_TCR EQU (0xFFFD0024) ;- (CAN) Transfer Command Register\r
+AT91C_CAN_IMR EQU (0xFFFD000C) ;- (CAN) Interrupt Mask Register\r
+AT91C_CAN_IER EQU (0xFFFD0004) ;- (CAN) Interrupt Enable Register\r
+AT91C_CAN_ECR EQU (0xFFFD0020) ;- (CAN) Error Counter Register\r
+AT91C_CAN_TIMESTP EQU (0xFFFD001C) ;- (CAN) Time Stamp Register\r
+AT91C_CAN_MR EQU (0xFFFD0000) ;- (CAN) Mode Register\r
+AT91C_CAN_IDR EQU (0xFFFD0008) ;- (CAN) Interrupt Disable Register\r
+AT91C_CAN_ACR EQU (0xFFFD0028) ;- (CAN) Abort Command Register\r
+AT91C_CAN_TIM EQU (0xFFFD0018) ;- (CAN) Timer Register\r
+AT91C_CAN_SR EQU (0xFFFD0010) ;- (CAN) Status Register\r
+AT91C_CAN_BR EQU (0xFFFD0014) ;- (CAN) Baudrate Register\r
+AT91C_CAN_VR EQU (0xFFFD00FC) ;- (CAN) Version Register\r
+// - ========== Register definition for EMAC peripheral ========== \r
+AT91C_EMAC_ISR EQU (0xFFFDC024) ;- (EMAC) Interrupt Status Register\r
+AT91C_EMAC_SA4H EQU (0xFFFDC0B4) ;- (EMAC) Specific Address 4 Top, Last 2 bytes\r
+AT91C_EMAC_SA1L EQU (0xFFFDC098) ;- (EMAC) Specific Address 1 Bottom, First 4 bytes\r
+AT91C_EMAC_ELE EQU (0xFFFDC078) ;- (EMAC) Excessive Length Errors Register\r
+AT91C_EMAC_LCOL EQU (0xFFFDC05C) ;- (EMAC) Late Collision Register\r
+AT91C_EMAC_RLE EQU (0xFFFDC088) ;- (EMAC) Receive Length Field Mismatch Register\r
+AT91C_EMAC_WOL EQU (0xFFFDC0C4) ;- (EMAC) Wake On LAN Register\r
+AT91C_EMAC_DTF EQU (0xFFFDC058) ;- (EMAC) Deferred Transmission Frame Register\r
+AT91C_EMAC_TUND EQU (0xFFFDC064) ;- (EMAC) Transmit Underrun Error Register\r
+AT91C_EMAC_NCR EQU (0xFFFDC000) ;- (EMAC) Network Control Register\r
+AT91C_EMAC_SA4L EQU (0xFFFDC0B0) ;- (EMAC) Specific Address 4 Bottom, First 4 bytes\r
+AT91C_EMAC_RSR EQU (0xFFFDC020) ;- (EMAC) Receive Status Register\r
+AT91C_EMAC_SA3L EQU (0xFFFDC0A8) ;- (EMAC) Specific Address 3 Bottom, First 4 bytes\r
+AT91C_EMAC_TSR EQU (0xFFFDC014) ;- (EMAC) Transmit Status Register\r
+AT91C_EMAC_IDR EQU (0xFFFDC02C) ;- (EMAC) Interrupt Disable Register\r
+AT91C_EMAC_RSE EQU (0xFFFDC074) ;- (EMAC) Receive Symbol Errors Register\r
+AT91C_EMAC_ECOL EQU (0xFFFDC060) ;- (EMAC) Excessive Collision Register\r
+AT91C_EMAC_TID EQU (0xFFFDC0B8) ;- (EMAC) Type ID Checking Register\r
+AT91C_EMAC_HRB EQU (0xFFFDC090) ;- (EMAC) Hash Address Bottom[31:0]\r
+AT91C_EMAC_TBQP EQU (0xFFFDC01C) ;- (EMAC) Transmit Buffer Queue Pointer\r
+AT91C_EMAC_USRIO EQU (0xFFFDC0C0) ;- (EMAC) USER Input/Output Register\r
+AT91C_EMAC_PTR EQU (0xFFFDC038) ;- (EMAC) Pause Time Register\r
+AT91C_EMAC_SA2H EQU (0xFFFDC0A4) ;- (EMAC) Specific Address 2 Top, Last 2 bytes\r
+AT91C_EMAC_ROV EQU (0xFFFDC070) ;- (EMAC) Receive Overrun Errors Register\r
+AT91C_EMAC_ALE EQU (0xFFFDC054) ;- (EMAC) Alignment Error Register\r
+AT91C_EMAC_RJA EQU (0xFFFDC07C) ;- (EMAC) Receive Jabbers Register\r
+AT91C_EMAC_RBQP EQU (0xFFFDC018) ;- (EMAC) Receive Buffer Queue Pointer\r
+AT91C_EMAC_TPF EQU (0xFFFDC08C) ;- (EMAC) Transmitted Pause Frames Register\r
+AT91C_EMAC_NCFGR EQU (0xFFFDC004) ;- (EMAC) Network Configuration Register\r
+AT91C_EMAC_HRT EQU (0xFFFDC094) ;- (EMAC) Hash Address Top[63:32]\r
+AT91C_EMAC_USF EQU (0xFFFDC080) ;- (EMAC) Undersize Frames Register\r
+AT91C_EMAC_FCSE EQU (0xFFFDC050) ;- (EMAC) Frame Check Sequence Error Register\r
+AT91C_EMAC_TPQ EQU (0xFFFDC0BC) ;- (EMAC) Transmit Pause Quantum Register\r
+AT91C_EMAC_MAN EQU (0xFFFDC034) ;- (EMAC) PHY Maintenance Register\r
+AT91C_EMAC_FTO EQU (0xFFFDC040) ;- (EMAC) Frames Transmitted OK Register\r
+AT91C_EMAC_REV EQU (0xFFFDC0FC) ;- (EMAC) Revision Register\r
+AT91C_EMAC_IMR EQU (0xFFFDC030) ;- (EMAC) Interrupt Mask Register\r
+AT91C_EMAC_SCF EQU (0xFFFDC044) ;- (EMAC) Single Collision Frame Register\r
+AT91C_EMAC_PFR EQU (0xFFFDC03C) ;- (EMAC) Pause Frames received Register\r
+AT91C_EMAC_MCF EQU (0xFFFDC048) ;- (EMAC) Multiple Collision Frame Register\r
+AT91C_EMAC_NSR EQU (0xFFFDC008) ;- (EMAC) Network Status Register\r
+AT91C_EMAC_SA2L EQU (0xFFFDC0A0) ;- (EMAC) Specific Address 2 Bottom, First 4 bytes\r
+AT91C_EMAC_FRO EQU (0xFFFDC04C) ;- (EMAC) Frames Received OK Register\r
+AT91C_EMAC_IER EQU (0xFFFDC028) ;- (EMAC) Interrupt Enable Register\r
+AT91C_EMAC_SA1H EQU (0xFFFDC09C) ;- (EMAC) Specific Address 1 Top, Last 2 bytes\r
+AT91C_EMAC_CSE EQU (0xFFFDC068) ;- (EMAC) Carrier Sense Error Register\r
+AT91C_EMAC_SA3H EQU (0xFFFDC0AC) ;- (EMAC) Specific Address 3 Top, Last 2 bytes\r
+AT91C_EMAC_RRE EQU (0xFFFDC06C) ;- (EMAC) Receive Ressource Error Register\r
+AT91C_EMAC_STE EQU (0xFFFDC084) ;- (EMAC) SQE Test Error Register\r
+// - ========== Register definition for PDC_ADC peripheral ========== \r
+AT91C_ADC_PTSR EQU (0xFFFD8124) ;- (PDC_ADC) PDC Transfer Status Register\r
+AT91C_ADC_PTCR EQU (0xFFFD8120) ;- (PDC_ADC) PDC Transfer Control Register\r
+AT91C_ADC_TNPR EQU (0xFFFD8118) ;- (PDC_ADC) Transmit Next Pointer Register\r
+AT91C_ADC_TNCR EQU (0xFFFD811C) ;- (PDC_ADC) Transmit Next Counter Register\r
+AT91C_ADC_RNPR EQU (0xFFFD8110) ;- (PDC_ADC) Receive Next Pointer Register\r
+AT91C_ADC_RNCR EQU (0xFFFD8114) ;- (PDC_ADC) Receive Next Counter Register\r
+AT91C_ADC_RPR EQU (0xFFFD8100) ;- (PDC_ADC) Receive Pointer Register\r
+AT91C_ADC_TCR EQU (0xFFFD810C) ;- (PDC_ADC) Transmit Counter Register\r
+AT91C_ADC_TPR EQU (0xFFFD8108) ;- (PDC_ADC) Transmit Pointer Register\r
+AT91C_ADC_RCR EQU (0xFFFD8104) ;- (PDC_ADC) Receive Counter Register\r
+// - ========== Register definition for ADC peripheral ========== \r
+AT91C_ADC_CDR2 EQU (0xFFFD8038) ;- (ADC) ADC Channel Data Register 2\r
+AT91C_ADC_CDR3 EQU (0xFFFD803C) ;- (ADC) ADC Channel Data Register 3\r
+AT91C_ADC_CDR0 EQU (0xFFFD8030) ;- (ADC) ADC Channel Data Register 0\r
+AT91C_ADC_CDR5 EQU (0xFFFD8044) ;- (ADC) ADC Channel Data Register 5\r
+AT91C_ADC_CHDR EQU (0xFFFD8014) ;- (ADC) ADC Channel Disable Register\r
+AT91C_ADC_SR EQU (0xFFFD801C) ;- (ADC) ADC Status Register\r
+AT91C_ADC_CDR4 EQU (0xFFFD8040) ;- (ADC) ADC Channel Data Register 4\r
+AT91C_ADC_CDR1 EQU (0xFFFD8034) ;- (ADC) ADC Channel Data Register 1\r
+AT91C_ADC_LCDR EQU (0xFFFD8020) ;- (ADC) ADC Last Converted Data Register\r
+AT91C_ADC_IDR EQU (0xFFFD8028) ;- (ADC) ADC Interrupt Disable Register\r
+AT91C_ADC_CR EQU (0xFFFD8000) ;- (ADC) ADC Control Register\r
+AT91C_ADC_CDR7 EQU (0xFFFD804C) ;- (ADC) ADC Channel Data Register 7\r
+AT91C_ADC_CDR6 EQU (0xFFFD8048) ;- (ADC) ADC Channel Data Register 6\r
+AT91C_ADC_IER EQU (0xFFFD8024) ;- (ADC) ADC Interrupt Enable Register\r
+AT91C_ADC_CHER EQU (0xFFFD8010) ;- (ADC) ADC Channel Enable Register\r
+AT91C_ADC_CHSR EQU (0xFFFD8018) ;- (ADC) ADC Channel Status Register\r
+AT91C_ADC_MR EQU (0xFFFD8004) ;- (ADC) ADC Mode Register\r
+AT91C_ADC_IMR EQU (0xFFFD802C) ;- (ADC) ADC Interrupt Mask Register\r
+// - ========== Register definition for PDC_AES peripheral ========== \r
+AT91C_AES_TPR EQU (0xFFFA4108) ;- (PDC_AES) Transmit Pointer Register\r
+AT91C_AES_PTCR EQU (0xFFFA4120) ;- (PDC_AES) PDC Transfer Control Register\r
+AT91C_AES_RNPR EQU (0xFFFA4110) ;- (PDC_AES) Receive Next Pointer Register\r
+AT91C_AES_TNCR EQU (0xFFFA411C) ;- (PDC_AES) Transmit Next Counter Register\r
+AT91C_AES_TCR EQU (0xFFFA410C) ;- (PDC_AES) Transmit Counter Register\r
+AT91C_AES_RCR EQU (0xFFFA4104) ;- (PDC_AES) Receive Counter Register\r
+AT91C_AES_RNCR EQU (0xFFFA4114) ;- (PDC_AES) Receive Next Counter Register\r
+AT91C_AES_TNPR EQU (0xFFFA4118) ;- (PDC_AES) Transmit Next Pointer Register\r
+AT91C_AES_RPR EQU (0xFFFA4100) ;- (PDC_AES) Receive Pointer Register\r
+AT91C_AES_PTSR EQU (0xFFFA4124) ;- (PDC_AES) PDC Transfer Status Register\r
+// - ========== Register definition for AES peripheral ========== \r
+AT91C_AES_IVxR EQU (0xFFFA4060) ;- (AES) Initialization Vector x Register\r
+AT91C_AES_MR EQU (0xFFFA4004) ;- (AES) Mode Register\r
+AT91C_AES_VR EQU (0xFFFA40FC) ;- (AES) AES Version Register\r
+AT91C_AES_ODATAxR EQU (0xFFFA4050) ;- (AES) Output Data x Register\r
+AT91C_AES_IDATAxR EQU (0xFFFA4040) ;- (AES) Input Data x Register\r
+AT91C_AES_CR EQU (0xFFFA4000) ;- (AES) Control Register\r
+AT91C_AES_IDR EQU (0xFFFA4014) ;- (AES) Interrupt Disable Register\r
+AT91C_AES_IMR EQU (0xFFFA4018) ;- (AES) Interrupt Mask Register\r
+AT91C_AES_IER EQU (0xFFFA4010) ;- (AES) Interrupt Enable Register\r
+AT91C_AES_KEYWxR EQU (0xFFFA4020) ;- (AES) Key Word x Register\r
+AT91C_AES_ISR EQU (0xFFFA401C) ;- (AES) Interrupt Status Register\r
+// - ========== Register definition for PDC_TDES peripheral ========== \r
+AT91C_TDES_RNCR EQU (0xFFFA8114) ;- (PDC_TDES) Receive Next Counter Register\r
+AT91C_TDES_TCR EQU (0xFFFA810C) ;- (PDC_TDES) Transmit Counter Register\r
+AT91C_TDES_RCR EQU (0xFFFA8104) ;- (PDC_TDES) Receive Counter Register\r
+AT91C_TDES_TNPR EQU (0xFFFA8118) ;- (PDC_TDES) Transmit Next Pointer Register\r
+AT91C_TDES_RNPR EQU (0xFFFA8110) ;- (PDC_TDES) Receive Next Pointer Register\r
+AT91C_TDES_RPR EQU (0xFFFA8100) ;- (PDC_TDES) Receive Pointer Register\r
+AT91C_TDES_TNCR EQU (0xFFFA811C) ;- (PDC_TDES) Transmit Next Counter Register\r
+AT91C_TDES_TPR EQU (0xFFFA8108) ;- (PDC_TDES) Transmit Pointer Register\r
+AT91C_TDES_PTSR EQU (0xFFFA8124) ;- (PDC_TDES) PDC Transfer Status Register\r
+AT91C_TDES_PTCR EQU (0xFFFA8120) ;- (PDC_TDES) PDC Transfer Control Register\r
+// - ========== Register definition for TDES peripheral ========== \r
+AT91C_TDES_KEY2WxR EQU (0xFFFA8028) ;- (TDES) Key 2 Word x Register\r
+AT91C_TDES_KEY3WxR EQU (0xFFFA8030) ;- (TDES) Key 3 Word x Register\r
+AT91C_TDES_IDR EQU (0xFFFA8014) ;- (TDES) Interrupt Disable Register\r
+AT91C_TDES_VR EQU (0xFFFA80FC) ;- (TDES) TDES Version Register\r
+AT91C_TDES_IVxR EQU (0xFFFA8060) ;- (TDES) Initialization Vector x Register\r
+AT91C_TDES_ODATAxR EQU (0xFFFA8050) ;- (TDES) Output Data x Register\r
+AT91C_TDES_IMR EQU (0xFFFA8018) ;- (TDES) Interrupt Mask Register\r
+AT91C_TDES_MR EQU (0xFFFA8004) ;- (TDES) Mode Register\r
+AT91C_TDES_CR EQU (0xFFFA8000) ;- (TDES) Control Register\r
+AT91C_TDES_IER EQU (0xFFFA8010) ;- (TDES) Interrupt Enable Register\r
+AT91C_TDES_ISR EQU (0xFFFA801C) ;- (TDES) Interrupt Status Register\r
+AT91C_TDES_IDATAxR EQU (0xFFFA8040) ;- (TDES) Input Data x Register\r
+AT91C_TDES_KEY1WxR EQU (0xFFFA8020) ;- (TDES) Key 1 Word x Register\r
+\r
+// - *****************************************************************************\r
+// - PIO DEFINITIONS FOR AT91SAM7X256\r
+// - *****************************************************************************\r
+AT91C_PIO_PA0 EQU (1 << 0) ;- Pin Controlled by PA0\r
+AT91C_PA0_RXD0 EQU (AT91C_PIO_PA0) ;- USART 0 Receive Data\r
+AT91C_PIO_PA1 EQU (1 << 1) ;- Pin Controlled by PA1\r
+AT91C_PA1_TXD0 EQU (AT91C_PIO_PA1) ;- USART 0 Transmit Data\r
+AT91C_PIO_PA10 EQU (1 << 10) ;- Pin Controlled by PA10\r
+AT91C_PA10_TWD EQU (AT91C_PIO_PA10) ;- TWI Two-wire Serial Data\r
+AT91C_PIO_PA11 EQU (1 << 11) ;- Pin Controlled by PA11\r
+AT91C_PA11_TWCK EQU (AT91C_PIO_PA11) ;- TWI Two-wire Serial Clock\r
+AT91C_PIO_PA12 EQU (1 << 12) ;- Pin Controlled by PA12\r
+AT91C_PA12_NPCS00 EQU (AT91C_PIO_PA12) ;- SPI 0 Peripheral Chip Select 0\r
+AT91C_PIO_PA13 EQU (1 << 13) ;- Pin Controlled by PA13\r
+AT91C_PA13_NPCS01 EQU (AT91C_PIO_PA13) ;- SPI 0 Peripheral Chip Select 1\r
+AT91C_PA13_PCK1 EQU (AT91C_PIO_PA13) ;- PMC Programmable Clock Output 1\r
+AT91C_PIO_PA14 EQU (1 << 14) ;- Pin Controlled by PA14\r
+AT91C_PA14_NPCS02 EQU (AT91C_PIO_PA14) ;- SPI 0 Peripheral Chip Select 2\r
+AT91C_PA14_IRQ1 EQU (AT91C_PIO_PA14) ;- External Interrupt 1\r
+AT91C_PIO_PA15 EQU (1 << 15) ;- Pin Controlled by PA15\r
+AT91C_PA15_NPCS03 EQU (AT91C_PIO_PA15) ;- SPI 0 Peripheral Chip Select 3\r
+AT91C_PA15_TCLK2 EQU (AT91C_PIO_PA15) ;- Timer Counter 2 external clock input\r
+AT91C_PIO_PA16 EQU (1 << 16) ;- Pin Controlled by PA16\r
+AT91C_PA16_MISO0 EQU (AT91C_PIO_PA16) ;- SPI 0 Master In Slave\r
+AT91C_PIO_PA17 EQU (1 << 17) ;- Pin Controlled by PA17\r
+AT91C_PA17_MOSI0 EQU (AT91C_PIO_PA17) ;- SPI 0 Master Out Slave\r
+AT91C_PIO_PA18 EQU (1 << 18) ;- Pin Controlled by PA18\r
+AT91C_PA18_SPCK0 EQU (AT91C_PIO_PA18) ;- SPI 0 Serial Clock\r
+AT91C_PIO_PA19 EQU (1 << 19) ;- Pin Controlled by PA19\r
+AT91C_PA19_CANRX EQU (AT91C_PIO_PA19) ;- CAN Receive\r
+AT91C_PIO_PA2 EQU (1 << 2) ;- Pin Controlled by PA2\r
+AT91C_PA2_SCK0 EQU (AT91C_PIO_PA2) ;- USART 0 Serial Clock\r
+AT91C_PA2_NPCS11 EQU (AT91C_PIO_PA2) ;- SPI 1 Peripheral Chip Select 1\r
+AT91C_PIO_PA20 EQU (1 << 20) ;- Pin Controlled by PA20\r
+AT91C_PA20_CANTX EQU (AT91C_PIO_PA20) ;- CAN Transmit\r
+AT91C_PIO_PA21 EQU (1 << 21) ;- Pin Controlled by PA21\r
+AT91C_PA21_TF EQU (AT91C_PIO_PA21) ;- SSC Transmit Frame Sync\r
+AT91C_PA21_NPCS10 EQU (AT91C_PIO_PA21) ;- SPI 1 Peripheral Chip Select 0\r
+AT91C_PIO_PA22 EQU (1 << 22) ;- Pin Controlled by PA22\r
+AT91C_PA22_TK EQU (AT91C_PIO_PA22) ;- SSC Transmit Clock\r
+AT91C_PA22_SPCK1 EQU (AT91C_PIO_PA22) ;- SPI 1 Serial Clock\r
+AT91C_PIO_PA23 EQU (1 << 23) ;- Pin Controlled by PA23\r
+AT91C_PA23_TD EQU (AT91C_PIO_PA23) ;- SSC Transmit data\r
+AT91C_PA23_MOSI1 EQU (AT91C_PIO_PA23) ;- SPI 1 Master Out Slave\r
+AT91C_PIO_PA24 EQU (1 << 24) ;- Pin Controlled by PA24\r
+AT91C_PA24_RD EQU (AT91C_PIO_PA24) ;- SSC Receive Data\r
+AT91C_PA24_MISO1 EQU (AT91C_PIO_PA24) ;- SPI 1 Master In Slave\r
+AT91C_PIO_PA25 EQU (1 << 25) ;- Pin Controlled by PA25\r
+AT91C_PA25_RK EQU (AT91C_PIO_PA25) ;- SSC Receive Clock\r
+AT91C_PA25_NPCS11 EQU (AT91C_PIO_PA25) ;- SPI 1 Peripheral Chip Select 1\r
+AT91C_PIO_PA26 EQU (1 << 26) ;- Pin Controlled by PA26\r
+AT91C_PA26_RF EQU (AT91C_PIO_PA26) ;- SSC Receive Frame Sync\r
+AT91C_PA26_NPCS12 EQU (AT91C_PIO_PA26) ;- SPI 1 Peripheral Chip Select 2\r
+AT91C_PIO_PA27 EQU (1 << 27) ;- Pin Controlled by PA27\r
+AT91C_PA27_DRXD EQU (AT91C_PIO_PA27) ;- DBGU Debug Receive Data\r
+AT91C_PA27_PCK3 EQU (AT91C_PIO_PA27) ;- PMC Programmable Clock Output 3\r
+AT91C_PIO_PA28 EQU (1 << 28) ;- Pin Controlled by PA28\r
+AT91C_PA28_DTXD EQU (AT91C_PIO_PA28) ;- DBGU Debug Transmit Data\r
+AT91C_PIO_PA29 EQU (1 << 29) ;- Pin Controlled by PA29\r
+AT91C_PA29_FIQ EQU (AT91C_PIO_PA29) ;- AIC Fast Interrupt Input\r
+AT91C_PA29_NPCS13 EQU (AT91C_PIO_PA29) ;- SPI 1 Peripheral Chip Select 3\r
+AT91C_PIO_PA3 EQU (1 << 3) ;- Pin Controlled by PA3\r
+AT91C_PA3_RTS0 EQU (AT91C_PIO_PA3) ;- USART 0 Ready To Send\r
+AT91C_PA3_NPCS12 EQU (AT91C_PIO_PA3) ;- SPI 1 Peripheral Chip Select 2\r
+AT91C_PIO_PA30 EQU (1 << 30) ;- Pin Controlled by PA30\r
+AT91C_PA30_IRQ0 EQU (AT91C_PIO_PA30) ;- External Interrupt 0\r
+AT91C_PA30_PCK2 EQU (AT91C_PIO_PA30) ;- PMC Programmable Clock Output 2\r
+AT91C_PIO_PA4 EQU (1 << 4) ;- Pin Controlled by PA4\r
+AT91C_PA4_CTS0 EQU (AT91C_PIO_PA4) ;- USART 0 Clear To Send\r
+AT91C_PA4_NPCS13 EQU (AT91C_PIO_PA4) ;- SPI 1 Peripheral Chip Select 3\r
+AT91C_PIO_PA5 EQU (1 << 5) ;- Pin Controlled by PA5\r
+AT91C_PA5_RXD1 EQU (AT91C_PIO_PA5) ;- USART 1 Receive Data\r
+AT91C_PIO_PA6 EQU (1 << 6) ;- Pin Controlled by PA6\r
+AT91C_PA6_TXD1 EQU (AT91C_PIO_PA6) ;- USART 1 Transmit Data\r
+AT91C_PIO_PA7 EQU (1 << 7) ;- Pin Controlled by PA7\r
+AT91C_PA7_SCK1 EQU (AT91C_PIO_PA7) ;- USART 1 Serial Clock\r
+AT91C_PA7_NPCS01 EQU (AT91C_PIO_PA7) ;- SPI 0 Peripheral Chip Select 1\r
+AT91C_PIO_PA8 EQU (1 << 8) ;- Pin Controlled by PA8\r
+AT91C_PA8_RTS1 EQU (AT91C_PIO_PA8) ;- USART 1 Ready To Send\r
+AT91C_PA8_NPCS02 EQU (AT91C_PIO_PA8) ;- SPI 0 Peripheral Chip Select 2\r
+AT91C_PIO_PA9 EQU (1 << 9) ;- Pin Controlled by PA9\r
+AT91C_PA9_CTS1 EQU (AT91C_PIO_PA9) ;- USART 1 Clear To Send\r
+AT91C_PA9_NPCS03 EQU (AT91C_PIO_PA9) ;- SPI 0 Peripheral Chip Select 3\r
+AT91C_PIO_PB0 EQU (1 << 0) ;- Pin Controlled by PB0\r
+AT91C_PB0_ETXCK_EREFCK EQU (AT91C_PIO_PB0) ;- Ethernet MAC Transmit Clock/Reference Clock\r
+AT91C_PB0_PCK0 EQU (AT91C_PIO_PB0) ;- PMC Programmable Clock Output 0\r
+AT91C_PIO_PB1 EQU (1 << 1) ;- Pin Controlled by PB1\r
+AT91C_PB1_ETXEN EQU (AT91C_PIO_PB1) ;- Ethernet MAC Transmit Enable\r
+AT91C_PIO_PB10 EQU (1 << 10) ;- Pin Controlled by PB10\r
+AT91C_PB10_ETX2 EQU (AT91C_PIO_PB10) ;- Ethernet MAC Transmit Data 2\r
+AT91C_PB10_NPCS11 EQU (AT91C_PIO_PB10) ;- SPI 1 Peripheral Chip Select 1\r
+AT91C_PIO_PB11 EQU (1 << 11) ;- Pin Controlled by PB11\r
+AT91C_PB11_ETX3 EQU (AT91C_PIO_PB11) ;- Ethernet MAC Transmit Data 3\r
+AT91C_PB11_NPCS12 EQU (AT91C_PIO_PB11) ;- SPI 1 Peripheral Chip Select 2\r
+AT91C_PIO_PB12 EQU (1 << 12) ;- Pin Controlled by PB12\r
+AT91C_PB12_ETXER EQU (AT91C_PIO_PB12) ;- Ethernet MAC Transmikt Coding Error\r
+AT91C_PB12_TCLK0 EQU (AT91C_PIO_PB12) ;- Timer Counter 0 external clock input\r
+AT91C_PIO_PB13 EQU (1 << 13) ;- Pin Controlled by PB13\r
+AT91C_PB13_ERX2 EQU (AT91C_PIO_PB13) ;- Ethernet MAC Receive Data 2\r
+AT91C_PB13_NPCS01 EQU (AT91C_PIO_PB13) ;- SPI 0 Peripheral Chip Select 1\r
+AT91C_PIO_PB14 EQU (1 << 14) ;- Pin Controlled by PB14\r
+AT91C_PB14_ERX3 EQU (AT91C_PIO_PB14) ;- Ethernet MAC Receive Data 3\r
+AT91C_PB14_NPCS02 EQU (AT91C_PIO_PB14) ;- SPI 0 Peripheral Chip Select 2\r
+AT91C_PIO_PB15 EQU (1 << 15) ;- Pin Controlled by PB15\r
+AT91C_PB15_ERXDV EQU (AT91C_PIO_PB15) ;- Ethernet MAC Receive Data Valid\r
+AT91C_PIO_PB16 EQU (1 << 16) ;- Pin Controlled by PB16\r
+AT91C_PB16_ECOL EQU (AT91C_PIO_PB16) ;- Ethernet MAC Collision Detected\r
+AT91C_PB16_NPCS13 EQU (AT91C_PIO_PB16) ;- SPI 1 Peripheral Chip Select 3\r
+AT91C_PIO_PB17 EQU (1 << 17) ;- Pin Controlled by PB17\r
+AT91C_PB17_ERXCK EQU (AT91C_PIO_PB17) ;- Ethernet MAC Receive Clock\r
+AT91C_PB17_NPCS03 EQU (AT91C_PIO_PB17) ;- SPI 0 Peripheral Chip Select 3\r
+AT91C_PIO_PB18 EQU (1 << 18) ;- Pin Controlled by PB18\r
+AT91C_PB18_EF100 EQU (AT91C_PIO_PB18) ;- Ethernet MAC Force 100 Mbits/sec\r
+AT91C_PB18_ADTRG EQU (AT91C_PIO_PB18) ;- ADC External Trigger\r
+AT91C_PIO_PB19 EQU (1 << 19) ;- Pin Controlled by PB19\r
+AT91C_PB19_PWM0 EQU (AT91C_PIO_PB19) ;- PWM Channel 0\r
+AT91C_PB19_TCLK1 EQU (AT91C_PIO_PB19) ;- Timer Counter 1 external clock input\r
+AT91C_PIO_PB2 EQU (1 << 2) ;- Pin Controlled by PB2\r
+AT91C_PB2_ETX0 EQU (AT91C_PIO_PB2) ;- Ethernet MAC Transmit Data 0\r
+AT91C_PIO_PB20 EQU (1 << 20) ;- Pin Controlled by PB20\r
+AT91C_PB20_PWM1 EQU (AT91C_PIO_PB20) ;- PWM Channel 1\r
+AT91C_PB20_PCK0 EQU (AT91C_PIO_PB20) ;- PMC Programmable Clock Output 0\r
+AT91C_PIO_PB21 EQU (1 << 21) ;- Pin Controlled by PB21\r
+AT91C_PB21_PWM2 EQU (AT91C_PIO_PB21) ;- PWM Channel 2\r
+AT91C_PB21_PCK1 EQU (AT91C_PIO_PB21) ;- PMC Programmable Clock Output 1\r
+AT91C_PIO_PB22 EQU (1 << 22) ;- Pin Controlled by PB22\r
+AT91C_PB22_PWM3 EQU (AT91C_PIO_PB22) ;- PWM Channel 3\r
+AT91C_PB22_PCK2 EQU (AT91C_PIO_PB22) ;- PMC Programmable Clock Output 2\r
+AT91C_PIO_PB23 EQU (1 << 23) ;- Pin Controlled by PB23\r
+AT91C_PB23_TIOA0 EQU (AT91C_PIO_PB23) ;- Timer Counter 0 Multipurpose Timer I/O Pin A\r
+AT91C_PB23_DCD1 EQU (AT91C_PIO_PB23) ;- USART 1 Data Carrier Detect\r
+AT91C_PIO_PB24 EQU (1 << 24) ;- Pin Controlled by PB24\r
+AT91C_PB24_TIOB0 EQU (AT91C_PIO_PB24) ;- Timer Counter 0 Multipurpose Timer I/O Pin B\r
+AT91C_PB24_DSR1 EQU (AT91C_PIO_PB24) ;- USART 1 Data Set ready\r
+AT91C_PIO_PB25 EQU (1 << 25) ;- Pin Controlled by PB25\r
+AT91C_PB25_TIOA1 EQU (AT91C_PIO_PB25) ;- Timer Counter 1 Multipurpose Timer I/O Pin A\r
+AT91C_PB25_DTR1 EQU (AT91C_PIO_PB25) ;- USART 1 Data Terminal ready\r
+AT91C_PIO_PB26 EQU (1 << 26) ;- Pin Controlled by PB26\r
+AT91C_PB26_TIOB1 EQU (AT91C_PIO_PB26) ;- Timer Counter 1 Multipurpose Timer I/O Pin B\r
+AT91C_PB26_RI1 EQU (AT91C_PIO_PB26) ;- USART 1 Ring Indicator\r
+AT91C_PIO_PB27 EQU (1 << 27) ;- Pin Controlled by PB27\r
+AT91C_PB27_TIOA2 EQU (AT91C_PIO_PB27) ;- Timer Counter 2 Multipurpose Timer I/O Pin A\r
+AT91C_PB27_PWM0 EQU (AT91C_PIO_PB27) ;- PWM Channel 0\r
+AT91C_PIO_PB28 EQU (1 << 28) ;- Pin Controlled by PB28\r
+AT91C_PB28_TIOB2 EQU (AT91C_PIO_PB28) ;- Timer Counter 2 Multipurpose Timer I/O Pin B\r
+AT91C_PB28_PWM1 EQU (AT91C_PIO_PB28) ;- PWM Channel 1\r
+AT91C_PIO_PB29 EQU (1 << 29) ;- Pin Controlled by PB29\r
+AT91C_PB29_PCK1 EQU (AT91C_PIO_PB29) ;- PMC Programmable Clock Output 1\r
+AT91C_PB29_PWM2 EQU (AT91C_PIO_PB29) ;- PWM Channel 2\r
+AT91C_PIO_PB3 EQU (1 << 3) ;- Pin Controlled by PB3\r
+AT91C_PB3_ETX1 EQU (AT91C_PIO_PB3) ;- Ethernet MAC Transmit Data 1\r
+AT91C_PIO_PB30 EQU (1 << 30) ;- Pin Controlled by PB30\r
+AT91C_PB30_PCK2 EQU (AT91C_PIO_PB30) ;- PMC Programmable Clock Output 2\r
+AT91C_PB30_PWM3 EQU (AT91C_PIO_PB30) ;- PWM Channel 3\r
+AT91C_PIO_PB4 EQU (1 << 4) ;- Pin Controlled by PB4\r
+AT91C_PB4_ECRS_ECRSDV EQU (AT91C_PIO_PB4) ;- Ethernet MAC Carrier Sense/Carrier Sense and Data Valid\r
+AT91C_PIO_PB5 EQU (1 << 5) ;- Pin Controlled by PB5\r
+AT91C_PB5_ERX0 EQU (AT91C_PIO_PB5) ;- Ethernet MAC Receive Data 0\r
+AT91C_PIO_PB6 EQU (1 << 6) ;- Pin Controlled by PB6\r
+AT91C_PB6_ERX1 EQU (AT91C_PIO_PB6) ;- Ethernet MAC Receive Data 1\r
+AT91C_PIO_PB7 EQU (1 << 7) ;- Pin Controlled by PB7\r
+AT91C_PB7_ERXER EQU (AT91C_PIO_PB7) ;- Ethernet MAC Receive Error\r
+AT91C_PIO_PB8 EQU (1 << 8) ;- Pin Controlled by PB8\r
+AT91C_PB8_EMDC EQU (AT91C_PIO_PB8) ;- Ethernet MAC Management Data Clock\r
+AT91C_PIO_PB9 EQU (1 << 9) ;- Pin Controlled by PB9\r
+AT91C_PB9_EMDIO EQU (AT91C_PIO_PB9) ;- Ethernet MAC Management Data Input/Output\r
+\r
+// - *****************************************************************************\r
+// - PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256\r
+// - *****************************************************************************\r
+AT91C_ID_FIQ EQU ( 0) ;- Advanced Interrupt Controller (FIQ)\r
+AT91C_ID_SYS EQU ( 1) ;- System Peripheral\r
+AT91C_ID_PIOA EQU ( 2) ;- Parallel IO Controller A\r
+AT91C_ID_PIOB EQU ( 3) ;- Parallel IO Controller B\r
+AT91C_ID_SPI0 EQU ( 4) ;- Serial Peripheral Interface 0\r
+AT91C_ID_SPI1 EQU ( 5) ;- Serial Peripheral Interface 1\r
+AT91C_ID_US0 EQU ( 6) ;- USART 0\r
+AT91C_ID_US1 EQU ( 7) ;- USART 1\r
+AT91C_ID_SSC EQU ( 8) ;- Serial Synchronous Controller\r
+AT91C_ID_TWI EQU ( 9) ;- Two-Wire Interface\r
+AT91C_ID_PWMC EQU (10) ;- PWM Controller\r
+AT91C_ID_UDP EQU (11) ;- USB Device Port\r
+AT91C_ID_TC0 EQU (12) ;- Timer Counter 0\r
+AT91C_ID_TC1 EQU (13) ;- Timer Counter 1\r
+AT91C_ID_TC2 EQU (14) ;- Timer Counter 2\r
+AT91C_ID_CAN EQU (15) ;- Control Area Network Controller\r
+AT91C_ID_EMAC EQU (16) ;- Ethernet MAC\r
+AT91C_ID_ADC EQU (17) ;- Analog-to-Digital Converter\r
+AT91C_ID_AES EQU (18) ;- Advanced Encryption Standard 128-bit\r
+AT91C_ID_TDES EQU (19) ;- Triple Data Encryption Standard\r
+AT91C_ID_20_Reserved EQU (20) ;- Reserved\r
+AT91C_ID_21_Reserved EQU (21) ;- Reserved\r
+AT91C_ID_22_Reserved EQU (22) ;- Reserved\r
+AT91C_ID_23_Reserved EQU (23) ;- Reserved\r
+AT91C_ID_24_Reserved EQU (24) ;- Reserved\r
+AT91C_ID_25_Reserved EQU (25) ;- Reserved\r
+AT91C_ID_26_Reserved EQU (26) ;- Reserved\r
+AT91C_ID_27_Reserved EQU (27) ;- Reserved\r
+AT91C_ID_28_Reserved EQU (28) ;- Reserved\r
+AT91C_ID_29_Reserved EQU (29) ;- Reserved\r
+AT91C_ID_IRQ0 EQU (30) ;- Advanced Interrupt Controller (IRQ0)\r
+AT91C_ID_IRQ1 EQU (31) ;- Advanced Interrupt Controller (IRQ1)\r
+\r
+// - *****************************************************************************\r
+// - BASE ADDRESS DEFINITIONS FOR AT91SAM7X256\r
+// - *****************************************************************************\r
+AT91C_BASE_SYS EQU (0xFFFFF000) ;- (SYS) Base Address\r
+AT91C_BASE_AIC EQU (0xFFFFF000) ;- (AIC) Base Address\r
+AT91C_BASE_PDC_DBGU EQU (0xFFFFF300) ;- (PDC_DBGU) Base Address\r
+AT91C_BASE_DBGU EQU (0xFFFFF200) ;- (DBGU) Base Address\r
+AT91C_BASE_PIOA EQU (0xFFFFF400) ;- (PIOA) Base Address\r
+AT91C_BASE_PIOB EQU (0xFFFFF600) ;- (PIOB) Base Address\r
+AT91C_BASE_CKGR EQU (0xFFFFFC20) ;- (CKGR) Base Address\r
+AT91C_BASE_PMC EQU (0xFFFFFC00) ;- (PMC) Base Address\r
+AT91C_BASE_RSTC EQU (0xFFFFFD00) ;- (RSTC) Base Address\r
+AT91C_BASE_RTTC EQU (0xFFFFFD20) ;- (RTTC) Base Address\r
+AT91C_BASE_PITC EQU (0xFFFFFD30) ;- (PITC) Base Address\r
+AT91C_BASE_WDTC EQU (0xFFFFFD40) ;- (WDTC) Base Address\r
+AT91C_BASE_VREG EQU (0xFFFFFD60) ;- (VREG) Base Address\r
+AT91C_BASE_MC EQU (0xFFFFFF00) ;- (MC) Base Address\r
+AT91C_BASE_PDC_SPI1 EQU (0xFFFE4100) ;- (PDC_SPI1) Base Address\r
+AT91C_BASE_SPI1 EQU (0xFFFE4000) ;- (SPI1) Base Address\r
+AT91C_BASE_PDC_SPI0 EQU (0xFFFE0100) ;- (PDC_SPI0) Base Address\r
+AT91C_BASE_SPI0 EQU (0xFFFE0000) ;- (SPI0) Base Address\r
+AT91C_BASE_PDC_US1 EQU (0xFFFC4100) ;- (PDC_US1) Base Address\r
+AT91C_BASE_US1 EQU (0xFFFC4000) ;- (US1) Base Address\r
+AT91C_BASE_PDC_US0 EQU (0xFFFC0100) ;- (PDC_US0) Base Address\r
+AT91C_BASE_US0 EQU (0xFFFC0000) ;- (US0) Base Address\r
+AT91C_BASE_PDC_SSC EQU (0xFFFD4100) ;- (PDC_SSC) Base Address\r
+AT91C_BASE_SSC EQU (0xFFFD4000) ;- (SSC) Base Address\r
+AT91C_BASE_TWI EQU (0xFFFB8000) ;- (TWI) Base Address\r
+AT91C_BASE_PWMC_CH3 EQU (0xFFFCC260) ;- (PWMC_CH3) Base Address\r
+AT91C_BASE_PWMC_CH2 EQU (0xFFFCC240) ;- (PWMC_CH2) Base Address\r
+AT91C_BASE_PWMC_CH1 EQU (0xFFFCC220) ;- (PWMC_CH1) Base Address\r
+AT91C_BASE_PWMC_CH0 EQU (0xFFFCC200) ;- (PWMC_CH0) Base Address\r
+AT91C_BASE_PWMC EQU (0xFFFCC000) ;- (PWMC) Base Address\r
+AT91C_BASE_UDP EQU (0xFFFB0000) ;- (UDP) Base Address\r
+AT91C_BASE_TC0 EQU (0xFFFA0000) ;- (TC0) Base Address\r
+AT91C_BASE_TC1 EQU (0xFFFA0040) ;- (TC1) Base Address\r
+AT91C_BASE_TC2 EQU (0xFFFA0080) ;- (TC2) Base Address\r
+AT91C_BASE_TCB EQU (0xFFFA0000) ;- (TCB) Base Address\r
+AT91C_BASE_CAN_MB0 EQU (0xFFFD0200) ;- (CAN_MB0) Base Address\r
+AT91C_BASE_CAN_MB1 EQU (0xFFFD0220) ;- (CAN_MB1) Base Address\r
+AT91C_BASE_CAN_MB2 EQU (0xFFFD0240) ;- (CAN_MB2) Base Address\r
+AT91C_BASE_CAN_MB3 EQU (0xFFFD0260) ;- (CAN_MB3) Base Address\r
+AT91C_BASE_CAN_MB4 EQU (0xFFFD0280) ;- (CAN_MB4) Base Address\r
+AT91C_BASE_CAN_MB5 EQU (0xFFFD02A0) ;- (CAN_MB5) Base Address\r
+AT91C_BASE_CAN_MB6 EQU (0xFFFD02C0) ;- (CAN_MB6) Base Address\r
+AT91C_BASE_CAN_MB7 EQU (0xFFFD02E0) ;- (CAN_MB7) Base Address\r
+AT91C_BASE_CAN EQU (0xFFFD0000) ;- (CAN) Base Address\r
+AT91C_BASE_EMAC EQU (0xFFFDC000) ;- (EMAC) Base Address\r
+AT91C_BASE_PDC_ADC EQU (0xFFFD8100) ;- (PDC_ADC) Base Address\r
+AT91C_BASE_ADC EQU (0xFFFD8000) ;- (ADC) Base Address\r
+AT91C_BASE_PDC_AES EQU (0xFFFA4100) ;- (PDC_AES) Base Address\r
+AT91C_BASE_AES EQU (0xFFFA4000) ;- (AES) Base Address\r
+AT91C_BASE_PDC_TDES EQU (0xFFFA8100) ;- (PDC_TDES) Base Address\r
+AT91C_BASE_TDES EQU (0xFFFA8000) ;- (TDES) Base Address\r
+\r
+// - *****************************************************************************\r
+// - MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256\r
+// - *****************************************************************************\r
+AT91C_ISRAM EQU (0x00200000) ;- Internal SRAM base address\r
+AT91C_ISRAM_SIZE EQU (0x00010000) ;- Internal SRAM size in byte (64 Kbyte)\r
+AT91C_IFLASH EQU (0x00100000) ;- Internal ROM base address\r
+AT91C_IFLASH_SIZE EQU (0x00040000) ;- Internal ROM size in byte (256 Kbyte)\r
+#endif /* __IAR_SYSTEMS_ASM__ */\r
+\r
+\r
+#endif /* AT91SAM7X256_H */\r
--- /dev/null
+/* Generic MII registers. */\r
+\r
+#define MII_BMCR 0x00 /* Basic mode control register */\r
+#define MII_BMSR 0x01 /* Basic mode status register */\r
+#define MII_PHYSID1 0x02 /* PHYS ID 1 */\r
+#define MII_PHYSID2 0x03 /* PHYS ID 2 */\r
+#define MII_ADVERTISE 0x04 /* Advertisement control reg */\r
+#define MII_LPA 0x05 /* Link partner ability reg */\r
+#define MII_EXPANSION 0x06 /* Expansion register */\r
+#define MII_DCOUNTER 0x12 /* Disconnect counter */\r
+#define MII_FCSCOUNTER 0x13 /* False carrier counter */\r
+#define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */\r
+#define MII_RERRCOUNTER 0x15 /* Receive error counter */\r
+#define MII_SREVISION 0x16 /* Silicon revision */\r
+#define MII_RESV1 0x17 /* Reserved... */\r
+#define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */\r
+#define MII_PHYADDR 0x19 /* PHY address */\r
+#define MII_RESV2 0x1a /* Reserved... */\r
+#define MII_TPISTATUS 0x1b /* TPI status for 10mbps */\r
+#define MII_NCONFIG 0x1c /* Network interface config */\r
+\r
+/* Basic mode control register. */\r
+#define BMCR_RESV 0x007f /* Unused... */\r
+#define BMCR_CTST 0x0080 /* Collision test */\r
+#define BMCR_FULLDPLX 0x0100 /* Full duplex */\r
+#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */\r
+#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */\r
+#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */\r
+#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */\r
+#define BMCR_SPEED100 0x2000 /* Select 100Mbps */\r
+#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */\r
+#define BMCR_RESET 0x8000 /* Reset the DP83840 */\r
+\r
+/* Basic mode status register. */\r
+#define BMSR_ERCAP 0x0001 /* Ext-reg capability */\r
+#define BMSR_JCD 0x0002 /* Jabber detected */\r
+#define BMSR_LSTATUS 0x0004 /* Link status */\r
+#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */\r
+#define BMSR_RFAULT 0x0010 /* Remote fault detected */\r
+#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */\r
+#define BMSR_RESV 0x07c0 /* Unused... */\r
+#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */\r
+#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */\r
+#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */\r
+#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */\r
+#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */\r
+\r
+/* Advertisement control register. */\r
+#define ADVERTISE_SLCT 0x001f /* Selector bits */\r
+#define ADVERTISE_CSMA 0x0001 /* Only selector supported */\r
+#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */\r
+#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */\r
+#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */\r
+#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */\r
+#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */\r
+#define ADVERTISE_RESV 0x1c00 /* Unused... */\r
+#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */\r
+#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */\r
+#define ADVERTISE_NPAGE 0x8000 /* Next page bit */\r
+\r
+#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \\r
+ ADVERTISE_CSMA)\r
+#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \\r
+ ADVERTISE_100HALF | ADVERTISE_100FULL)\r
+\r
+/* Link partner ability register. */\r
+#define LPA_SLCT 0x001f /* Same as advertise selector */\r
+#define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */\r
+#define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */\r
+#define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */\r
+#define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */\r
+#define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */\r
+#define LPA_RESV 0x1c00 /* Unused... */\r
+#define LPA_RFAULT 0x2000 /* Link partner faulted */\r
+#define LPA_LPACK 0x4000 /* Link partner acked us */\r
+#define LPA_NPAGE 0x8000 /* Next page bit */\r
+\r
+#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL)\r
+#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)\r
+\r
+/* Expansion register for auto-negotiation. */\r
+#define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */\r
+#define EXPANSION_LCWP 0x0002 /* Got new RX page code word */\r
+#define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */\r
+#define EXPANSION_NPCAPABLE 0x0008 /* Link partner supports npage */\r
+#define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */\r
+#define EXPANSION_RESV 0xffe0 /* Unused... */\r
+\r
+/* N-way test register. */\r
+#define NWAYTEST_RESV1 0x00ff /* Unused... */\r
+#define NWAYTEST_LOOPBACK 0x0100 /* Enable loopback for N-way */\r
+#define NWAYTEST_RESV2 0xfe00 /* Unused... */\r
+\r
+#define SPEED_10 10\r
+#define SPEED_100 100\r
+\r
+/* Duplex, half or full. */\r
+#define DUPLEX_HALF 0x00\r
+#define DUPLEX_FULL 0x01\r
+\r
+/* PHY ID */\r
+#define MII_DM9161_ID 0x0181b8a0\r
+#define MII_AM79C875_ID 0x00225540 /* 0x00225541 */\r
+\r
+#define AT91C_PHY_ADDR 31\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+ * Creates all the application tasks, then starts the scheduler.\r
+ *\r
+ * A task is also created called "uIP". This executes the uIP stack and small\r
+ * WEB server sample. All the other tasks are from the set of standard\r
+ * demo tasks. The WEB documentation provides more details of the standard\r
+ * demo application tasks.\r
+ *\r
+ * Main.c also creates a task called "Check". This only executes every three\r
+ * seconds but has the highest priority so is guaranteed to get processor time.\r
+ * Its main function is to check the status of all the other demo application\r
+ * tasks. LED mainCHECK_LED is toggled every three seconds by the check task\r
+ * should no error conditions be detected in any of the standard demo tasks.\r
+ * The toggle rate increasing to 500ms indicates that at least one error has\r
+ * been detected.\r
+ */\r
+\r
+\r
+/* Standard includes. */\r
+#include <stdlib.h>\r
+#include <string.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo application includes. */\r
+#include "partest.h"\r
+#include "PollQ.h"\r
+#include "dynamic.h"\r
+#include "semtest.h"\r
+#include "flash.h"\r
+#include "integer.h"\r
+#include "flop.h"\r
+#include "BlockQ.h"\r
+#include "death.h"\r
+#include "uip_task.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Priorities/stacks for the demo application tasks. */\r
+#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define mainUIP_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+#define mainFLASH_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define mainDEATH_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainUIP_TASK_STACK_SIZE ( 250 )\r
+\r
+/* The rate at which the on board LED will toggle when there is/is not an\r
+error. */\r
+#define mainNO_ERROR_FLASH_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS )\r
+#define mainERROR_FLASH_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS )\r
+\r
+/* The LED used by the check task to indicate the system status. */\r
+#define mainCHECK_LED ( 3 )\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Checks that all the demo application tasks are still executing without error\r
+ * - as described at the top of the file.\r
+ */\r
+static portLONG prvCheckOtherTasksAreStillRunning( void );\r
+\r
+/*\r
+ * The task that executes at the highest priority and calls\r
+ * prvCheckOtherTasksAreStillRunning(). See the description at the top\r
+ * of the file.\r
+ */\r
+static void vErrorChecks( void *pvParameters );\r
+\r
+/*\r
+ * Configure the processor for use with the Atmel demo board. This is very\r
+ * minimal as most of the setup is performed in the startup code.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Starts all the other tasks, then starts the scheduler.\r
+ */\r
+int main( void )\r
+{\r
+ /* Configure the processor. */\r
+ prvSetupHardware();\r
+\r
+ /* Setup the port used to flash the LED's. */\r
+ vParTestInitialise();\r
+\r
+ /* Start the task that handles the TCP/IP and WEB server functionality. */\r
+ xTaskCreate( vuIP_TASK, "uIP", mainUIP_TASK_STACK_SIZE, NULL, mainUIP_PRIORITY, NULL );\r
+ \r
+ /* Start the demo/test application tasks. These are created in addition\r
+ to the TCP/IP task for demonstration and test purposes. */\r
+ vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
+ vStartDynamicPriorityTasks();\r
+ vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
+ vStartLEDFlashTasks( mainFLASH_PRIORITY );\r
+ vStartIntegerMathTasks( tskIDLE_PRIORITY );\r
+ vStartMathTasks( tskIDLE_PRIORITY );\r
+ vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
+\r
+ /* Start the check task - which is defined in this file. */ \r
+ xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
+\r
+ /* Must be last to get created. */\r
+ vCreateSuicidalTasks( mainDEATH_PRIORITY );\r
+\r
+ /* Now all the tasks have been started - start the scheduler. */\r
+ vTaskStartScheduler();\r
+\r
+ /* Should never reach here because the tasks should now be executing! */\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+ /* When using the JTAG debugger the hardware is not always initialised to\r
+ the correct default state. This line just ensures that this does not\r
+ cause all interrupts to be masked at the start. */\r
+ AT91C_BASE_AIC->AIC_EOICR = 0;\r
+ \r
+ /* Most setup is performed by the low level init function called from the\r
+ startup asm file.\r
+\r
+ Configure the PIO Lines corresponding to LED1 to LED4 to be outputs as\r
+ well as the UART Tx line. */\r
+ AT91F_PIO_CfgOutput( AT91C_BASE_PIOB, LED_MASK );\r
+\r
+ /* Enable the peripheral clock. */\r
+ AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, 1 << AT91C_ID_PIOA );\r
+ AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, 1 << AT91C_ID_PIOB ) ;\r
+ AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, 1 << AT91C_ID_EMAC ) ;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vErrorChecks( void *pvParameters )\r
+{\r
+portTickType xDelayPeriod = mainNO_ERROR_FLASH_PERIOD;\r
+portTickType xLastWakeTime;\r
+\r
+ /* Initialise xLastWakeTime to ensure the first call to vTaskDelayUntil()\r
+ functions correctly. */\r
+ xLastWakeTime = xTaskGetTickCount();\r
+\r
+ /* Cycle for ever, delaying then checking all the other tasks are still\r
+ operating without error. If an error is detected then the delay period\r
+ is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so\r
+ the Check LED flash rate will increase. */\r
+ for( ;; )\r
+ {\r
+ /* Delay until it is time to execute again. The delay period is\r
+ shorter following an error. */\r
+ vTaskDelayUntil( &xLastWakeTime, xDelayPeriod );\r
+ \r
+ /* Check all the standard demo application tasks are executing without\r
+ error. */\r
+ if( prvCheckOtherTasksAreStillRunning() != pdPASS )\r
+ {\r
+ /* An error has been detected in one of the tasks - flash faster. */\r
+ xDelayPeriod = mainERROR_FLASH_PERIOD;\r
+ }\r
+\r
+ vParTestToggleLED( mainCHECK_LED );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portLONG prvCheckOtherTasksAreStillRunning( void )\r
+{\r
+portLONG lReturn = ( portLONG ) pdPASS;\r
+\r
+\r
+ /* Check all the demo tasks (other than the flash tasks) to ensure\r
+ that they are all still running, and that none of them have detected\r
+ an error. */\r
+\r
+ if( xArePollingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ lReturn = ( portLONG ) pdFAIL;\r
+ }\r
+\r
+ if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )\r
+ {\r
+ lReturn = ( portLONG ) pdFAIL;\r
+ }\r
+\r
+ if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ lReturn = ( portLONG ) pdFAIL;\r
+ }\r
+\r
+ if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ lReturn = ( portLONG ) pdFAIL;\r
+ }\r
+\r
+ if( xAreMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ lReturn = ( portLONG ) pdFAIL;\r
+ }\r
+\r
+ if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ lReturn = ( portLONG ) pdFAIL;\r
+ }\r
+\r
+ if( xIsCreateTaskStillRunning() != pdTRUE )\r
+ {\r
+ lReturn = ( portLONG ) pdFAIL;\r
+ }\r
+\r
+ return lReturn;\r
+}\r
+\r
+\r
+\r
--- /dev/null
+// ---------------------------------------------------------\r
+// Microcontroller Software Support - ROUSSET -\r
+// ---------------------------------------------------------\r
+// The software is delivered "AS IS" without warranty or \r
+// condition of any kind, either express, implied or \r
+// statutory. This includes without limitation any warranty \r
+// or condition with respect to merchantability or fitness \r
+// for any particular purpose, or against the infringements of\r
+// intellectual property rights of others.\r
+// ---------------------------------------------------------\r
+// File: SAM7.mac\r
+//\r
+// 1.0 08/Mar/04 JPP : Creation\r
+// 1.1 23/Mar/05 JPP : Change Variable name\r
+//\r
+// $Revision: 1.5 $\r
+//\r
+// ---------------------------------------------------------\r
+\r
+__var __mac_i;\r
+__var __mac_pt;\r
+\r
+execUserReset()\r
+{\r
+ AIC();\r
+//* Watchdog Disable\r
+ Watchdog();\r
+}\r
+\r
+execUserPreload()\r
+{\r
+//* Set the RAM memory at 0x0020 0000 for code AT 0 flash area \r
+ CheckRemap();\r
+//* Get the Chip ID (AT91C_DBGU_C1R & AT91C_DBGU_C2R\r
+ __mac_i =__readMemory32(0xFFFFF240,"Memory");\r
+ __message " ---------------------------------------- Chip ID 0x",__mac_i:%X; \r
+ __mac_i =__readMemory32(0xFFFFF244,"Memory");\r
+ __message " ---------------------------------------- Extention 0x",__mac_i:%X; \r
+//* Get the chip status\r
+\r
+//* Init AIC\r
+ AIC();\r
+//* Watchdog Disable\r
+ Watchdog();\r
+\r
+}\r
+\r
+\r
+//-----------------------------------------------------------------------------\r
+// Watchdog\r
+//-------------------------------\r
+// Normally, the Watchdog is enable at the reset for load it's preferable to\r
+// Disable.\r
+//-----------------------------------------------------------------------------\r
+Watchdog()\r
+{\r
+//* Watchdog Disable\r
+// AT91C_BASE_WDTC->WDTC_WDMR= AT91C_WDTC_WDDIS;\r
+ __writeMemory32(0x00008000,0xFFFFFD44,"Memory");\r
+ __message "------------------------------- Watchdog Disable ----------------------------------------"; \r
+}\r
+\r
+\r
+//-----------------------------------------------------------------------------\r
+// Check Remap\r
+//-------------\r
+//-----------------------------------------------------------------------------\r
+CheckRemap()\r
+{\r
+//* Read the value at 0x0\r
+ __mac_i =__readMemory32(0x00000000,"Memory");\r
+ __mac_i =__mac_i+1;\r
+ __writeMemory32(__mac_i,0x00,"Memory");\r
+ __mac_pt =__readMemory32(0x00000000,"Memory");\r
+ \r
+ if (__mac_i == __mac_pt) \r
+ {\r
+ __message "------------------------------- The Remap is done ----------------------------------------"; \r
+//* Toggel RESET The remap\r
+ __writeMemory32(0x00000001,0xFFFFFF00,"Memory");\r
+ \r
+ } else { \r
+ __message "------------------------------- The Remap is NOT -----------------------------------------"; \r
+ }\r
+\r
+}\r
+\r
+\r
+execUserSetup()\r
+{\r
+ ini();\r
+ __message "-------------------------------Set PC ----------------------------------------"; \r
+ __writeMemory32(0x00000000,0xB4,"Register");\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+// Reset the Interrupt Controller\r
+//-------------------------------\r
+// Normally, the code is executed only if a reset has been actually performed.\r
+// So, the AIC initialization resumes at setting up the default vectors.\r
+//-----------------------------------------------------------------------------\r
+AIC()\r
+{\r
+// Mask All interrupt pAic->AIC_IDCR = 0xFFFFFFFF;\r
+ __writeMemory32(0xffffffff,0xFFFFF124,"Memory");\r
+ __writeMemory32(0xffffffff,0xFFFFF128,"Memory");\r
+// disable peripheral clock Peripheral Clock Disable Register\r
+ __writeMemory32(0xffffffff,0xFFFFFC14,"Memory");\r
+\r
+// #define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register\r
+// #define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register\r
+// #define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register\r
+ __readMemory32(0xFFFA0020,"Memory");\r
+ __readMemory32(0xFFFA0060,"Memory");\r
+ __readMemory32(0xFFFA00A0,"Memory");\r
+\r
+ for (__mac_i=0;__mac_i < 8; __mac_i++)\r
+ {\r
+ // AT91C_BASE_AIC->AIC_EOICR\r
+ __mac_pt = __readMemory32(0xFFFFF130,"Memory");\r
+ \r
+ }\r
+ __message "------------------------------- AIC 2 INIT ---------------------------------------------"; \r
+}\r
+\r
+ini()\r
+{\r
+__writeMemory32(0x0,0x00,"Register");\r
+__writeMemory32(0x0,0x04,"Register");\r
+__writeMemory32(0x0,0x08,"Register");\r
+__writeMemory32(0x0,0x0C,"Register");\r
+__writeMemory32(0x0,0x10,"Register");\r
+__writeMemory32(0x0,0x14,"Register");\r
+__writeMemory32(0x0,0x18,"Register");\r
+__writeMemory32(0x0,0x1C,"Register");\r
+__writeMemory32(0x0,0x20,"Register");\r
+__writeMemory32(0x0,0x24,"Register");\r
+__writeMemory32(0x0,0x28,"Register");\r
+__writeMemory32(0x0,0x2C,"Register");\r
+__writeMemory32(0x0,0x30,"Register");\r
+__writeMemory32(0x0,0x34,"Register");\r
+__writeMemory32(0x0,0x38,"Register");\r
+\r
+// Set CPSR\r
+__writeMemory32(0x0D3,0x98,"Register");\r
+\r
+\r
+}\r
+\r
+RG()\r
+{\r
+\r
+__mac_i =__readMemory32(0x00,"Register"); __message "R00 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x04,"Register"); __message "R01 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x08,"Register"); __message "R02 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x0C,"Register"); __message "R03 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x10,"Register"); __message "R04 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x14,"Register"); __message "R05 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x18,"Register"); __message "R06 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x1C,"Register"); __message "R07 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x20,"Register"); __message "R08 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x24,"Register"); __message "R09 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x28,"Register"); __message "R10 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x2C,"Register"); __message "R11 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x30,"Register"); __message "R12 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x34,"Register"); __message "R13 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x38,"Register"); __message "R14 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x3C,"Register"); __message "R13 SVC 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x40,"Register"); __message "R14 SVC 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x44,"Register"); __message "R13 ABT 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x48,"Register"); __message "R14 ABT 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x4C,"Register"); __message "R13 UND 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x50,"Register"); __message "R14 UND 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x54,"Register"); __message "R13 IRQ 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x58,"Register"); __message "R14 IRQ 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x5C,"Register"); __message "R08 FIQ 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x60,"Register"); __message "R09 FIQ 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x64,"Register"); __message "R10 FIQ 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x68,"Register"); __message "R11 FIQ 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x6C,"Register"); __message "R12 FIQ 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x70,"Register"); __message "R13 FIQ 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x74,"Register"); __message "R14 FIQ0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x98,"Register"); __message "CPSR ",__mac_i:%X; \r
+__mac_i =__readMemory32(0x94,"Register"); __message "SPSR ",__mac_i:%X; \r
+__mac_i =__readMemory32(0x9C,"Register"); __message "SPSR ABT ",__mac_i:%X; \r
+__mac_i =__readMemory32(0xA0,"Register"); __message "SPSR ABT ",__mac_i:%X; \r
+__mac_i =__readMemory32(0xA4,"Register"); __message "SPSR UND ",__mac_i:%X; \r
+__mac_i =__readMemory32(0xA8,"Register"); __message "SPSR IRQ ",__mac_i:%X; \r
+__mac_i =__readMemory32(0xAC,"Register"); __message "SPSR FIQ ",__mac_i:%X; \r
+\r
+__mac_i =__readMemory32(0xB4,"Register"); __message "PC 0x",__mac_i:%X; \r
+\r
+}\r
+\r
--- /dev/null
+// ---------------------------------------------------------\r
+// ATMEL Microcontroller Software Support - ROUSSET -\r
+// ---------------------------------------------------------\r
+// The software is delivered "AS IS" without warranty or \r
+// condition of any kind, either express, implied or \r
+// statutory. This includes without limitation any warranty \r
+// or condition with respect to merchantability or fitness \r
+// for any particular purpose, or against the infringements of\r
+// intellectual property rights of others.\r
+// ---------------------------------------------------------\r
+// File: SAM7_RAM.mac\r
+//\r
+// 1.0 08/Mar/05 JPP : Creation\r
+// 1.1 23/Mar/05 JPP : Change Variable name\r
+//\r
+// $Revision: 1.6 $\r
+//\r
+// ---------------------------------------------------------\r
+\r
+__var __mac_i;\r
+__var __mac_pt;\r
+__var __mac_mem;\r
+execUserReset()\r
+{\r
+ CheckNoRemap();\r
+ ini();\r
+ AIC();\r
+ __message "-------------------------------Set PC Reset ----------------------------------"; \r
+ __writeMemory32(0x00000000,0xB4,"Register");\r
+}\r
+\r
+execUserPreload()\r
+{\r
+//* __message "-------------------------------Set CPSR ----------------------------------"; \r
+ __writeMemory32(0xD3,0x98,"Register"); \r
+ __writeMemory32(0xffffffff,0xFFFFFC14,"Memory");\r
+ PllSetting();\r
+ //* Init AIC\r
+ AIC();\r
+\r
+//* Set the RAM memory at 0x0020 0000 for code AT 0 flash area \r
+ CheckNoRemap();\r
+//* Get the Chip ID (AT91C_DBGU_C1R & AT91C_DBGU_C2R\r
+ __mac_i=__readMemory32(0xFFFFF240,"Memory");\r
+ __message " ---------------------------------------- Chip ID 0x",__mac_i:%X; \r
+ __mac_i=__readMemory32(0xFFFFF244,"Memory");\r
+ __message " ---------------------------------------- Extention 0x",__mac_i:%X; \r
+ __mac_i=__readMemory32(0xFFFFFF6C,"Memory");\r
+ __message " ---------------------------------------- Flash Version 0x",__mac_i:%X; \r
+\r
+//* Watchdog Disable\r
+ Watchdog();\r
+//* RG();\r
+}\r
+//-----------------------------------------------------------------------------\r
+// PllSetting\r
+//-------------------------------\r
+// Set PLL\r
+//-----------------------------------------------------------------------------\r
+PllSetting()\r
+{\r
+// -1- Enabling the Main Oscillator:\r
+//*#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register\r
+//*#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register\r
+//*#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register\r
+\r
+//*pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) | //0x0000 0600\r
+// AT91C_CKGR_MOSCEN )); //0x0000 0001 \r
+__writeMemory32(0x00000601,0xFFFFFC20,"Memory");\r
+\r
+// -2- Wait\r
+// -3- Setting PLL and divider:\r
+// - div by 5 Fin = 3,6864 =(18,432 / 5)\r
+// - Mul 25+1: Fout = 95,8464 =(3,6864 *26)\r
+// for 96 MHz the erroe is 0.16%\r
+// Field out NOT USED = 0\r
+// PLLCOUNT pll startup time esrtimate at : 0.844 ms\r
+// PLLCOUNT 28 = 0.000844 /(1/32768)\r
+// pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 0x05) | //0x0000 0005\r
+// (AT91C_CKGR_PLLCOUNT & (28<<8)) //0x0000 1C00\r
+// (AT91C_CKGR_MUL & (25<<16))); //0x0019 0000 \r
+__writeMemory32(0x00191C05,0xFFFFFC2C,"Memory");\r
+// -2- Wait\r
+// -5- Selection of Master Clock and Processor Clock\r
+// select the PLL clock divided by 2\r
+// pPMC->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK | //0x0000 0003\r
+// AT91C_PMC_PRES_CLK_2 ; //0x0000 0004\r
+__writeMemory32(0x00000007,0xFFFFFC30,"Memory"); \r
+ \r
+\r
+ __message "------------------------------- PLL Enable ----------------------------------------"; \r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+// Watchdog\r
+//-------------------------------\r
+// Normally, the Watchdog is enable at the reset for load it's preferable to\r
+// Disable.\r
+//-----------------------------------------------------------------------------\r
+Watchdog()\r
+{\r
+//* Watchdog Disable\r
+// AT91C_BASE_WDTC->WDTC_WDMR= AT91C_WDTC_WDDIS;\r
+ __writeMemory32(0x00008000,0xFFFFFD44,"Memory");\r
+ __message "------------------------------- Watchdog Disable ----------------------------------------"; \r
+}\r
+\r
+CheckNoRemap()\r
+{\r
+//* Read the value at 0x0\r
+ __mac_i =__readMemory32(0x00000000,"Memory");\r
+ __mac_mem = __mac_i;\r
+ __mac_i=__mac_i+1;\r
+ __writeMemory32(__mac_i,0x00,"Memory");\r
+ __mac_pt=__readMemory32(0x00000000,"Memory");\r
+ \r
+ if (__mac_i == __mac_pt) \r
+ {\r
+ __message "------------------------------- The Remap is done ----------------------------------------"; \r
+ __writeMemory32( __mac_mem,0x00000000,"Memory");\r
+ \r
+ } else { \r
+ __message "------------------------------- The Remap is NOT -----------------------------------------"; \r
+//* Toggel RESET The remap\r
+ __writeMemory32(0x00000001,0xFFFFFF00,"Memory");\r
+ }\r
+\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+// Reset the Interrupt Controller\r
+//-------------------------------\r
+// Normally, the code is executed only if a reset has been actually performed.\r
+// So, the AIC initialization resumes at setting up the default vectors.\r
+//-----------------------------------------------------------------------------\r
+AIC()\r
+{\r
+// Mask All interrupt pAic->AIC_IDCR = 0xFFFFFFFF;\r
+ __writeMemory32(0xffffffff,0xFFFFF124,"Memory");\r
+ __writeMemory32(0xffffffff,0xFFFFF128,"Memory");\r
+// disable peripheral clock Peripheral Clock Disable Register\r
+ __writeMemory32(0xffffffff,0xFFFFFC14,"Memory");\r
+\r
+// #define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register\r
+// #define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register\r
+// #define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register\r
+ __readMemory32(0xFFFA0020,"Memory");\r
+ __readMemory32(0xFFFA0060,"Memory");\r
+ __readMemory32(0xFFFA00A0,"Memory");\r
+ for (__mac_i=0;__mac_i < 8; __mac_i++)\r
+ {\r
+ // AT91C_BASE_AIC->AIC_EOICR\r
+ __mac_pt = __readMemory32(0xFFFFF130,"Memory");\r
+ \r
+ }\r
+ __message "------------------------------- AIC 2 INIT ---------------------------------------------"; \r
+}\r
+\r
+ini()\r
+{\r
+__writeMemory32(0x0,0x00,"Register");\r
+__writeMemory32(0x0,0x04,"Register");\r
+__writeMemory32(0x0,0x08,"Register");\r
+__writeMemory32(0x0,0x0C,"Register");\r
+__writeMemory32(0x0,0x10,"Register");\r
+__writeMemory32(0x0,0x14,"Register");\r
+__writeMemory32(0x0,0x18,"Register");\r
+__writeMemory32(0x0,0x1C,"Register");\r
+__writeMemory32(0x0,0x20,"Register");\r
+__writeMemory32(0x0,0x24,"Register");\r
+__writeMemory32(0x0,0x28,"Register");\r
+__writeMemory32(0x0,0x2C,"Register");\r
+__writeMemory32(0x0,0x30,"Register");\r
+__writeMemory32(0x0,0x34,"Register");\r
+__writeMemory32(0x0,0x38,"Register");\r
+\r
+// Set CPSR\r
+__writeMemory32(0x0D3,0x98,"Register");\r
+\r
+\r
+}\r
+\r
+RG()\r
+{\r
+\r
+__mac_i =__readMemory32(0x00,"Register"); __message "R00 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x04,"Register"); __message "R01 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x08,"Register"); __message "R02 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x0C,"Register"); __message "R03 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x10,"Register"); __message "R04 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x14,"Register"); __message "R05 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x18,"Register"); __message "R06 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x1C,"Register"); __message "R07 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x20,"Register"); __message "R08 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x24,"Register"); __message "R09 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x28,"Register"); __message "R10 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x2C,"Register"); __message "R11 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x30,"Register"); __message "R12 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x34,"Register"); __message "R13 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x38,"Register"); __message "R14 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x3C,"Register"); __message "R13 SVC 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x40,"Register"); __message "R14 SVC 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x44,"Register"); __message "R13 ABT 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x48,"Register"); __message "R14 ABT 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x4C,"Register"); __message "R13 UND 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x50,"Register"); __message "R14 UND 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x54,"Register"); __message "R13 IRQ 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x58,"Register"); __message "R14 IRQ 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x5C,"Register"); __message "R08 FIQ 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x60,"Register"); __message "R09 FIQ 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x64,"Register"); __message "R10 FIQ 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x68,"Register"); __message "R11 FIQ 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x6C,"Register"); __message "R12 FIQ 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x70,"Register"); __message "R13 FIQ 0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x74,"Register"); __message "R14 FIQ0x",__mac_i:%X; \r
+__mac_i =__readMemory32(0x98,"Register"); __message "CPSR ",__mac_i:%X; \r
+__mac_i =__readMemory32(0x94,"Register"); __message "SPSR ",__mac_i:%X; \r
+__mac_i =__readMemory32(0x9C,"Register"); __message "SPSR ABT ",__mac_i:%X; \r
+__mac_i =__readMemory32(0xA0,"Register"); __message "SPSR ABT ",__mac_i:%X; \r
+__mac_i =__readMemory32(0xA4,"Register"); __message "SPSR UND ",__mac_i:%X; \r
+__mac_i =__readMemory32(0xA8,"Register"); __message "SPSR IRQ ",__mac_i:%X; \r
+__mac_i =__readMemory32(0xAC,"Register"); __message "SPSR FIQ ",__mac_i:%X; \r
+\r
+__mac_i =__readMemory32(0xB4,"Register"); __message "PC 0x",__mac_i:%X; \r
+\r
+}\r
+\r
--- /dev/null
+// ---------------------------------------------------------\r
+// ATMEL Microcontroller Software Support - ROUSSET -\r
+// ---------------------------------------------------------\r
+// The software is delivered "AS IS" without warranty or \r
+// condition of any kind, either express, implied or \r
+// statutory. This includes without limitation any warranty \r
+// or condition with respect to merchantability or fitness \r
+// for any particular purpose, or against the infringements of\r
+// intellectual property rights of others.\r
+// ---------------------------------------------------------\r
+// File: at91SAM7x256_NoRemap.xlc\r
+//\r
+//\r
+// $Revision: 1.1.1.1 $\r
+//\r
+// ---------------------------------------------------------\r
+\r
+//*************************************************************************\r
+// XLINK command file template for EWARM/ICCARM\r
+//\r
+// Usage: xlink -f lnkarm <your_object_file(s)>\r
+// -s <program start label> <C/C++ runtime library>\r
+//\r
+// $Revision: 1.1.1.1 $\r
+//*************************************************************************\r
+\r
+//************************************************\r
+// Inform the linker about the CPU family used.\r
+// AT91SAM7S64 Memory mapping\r
+// No remap\r
+// ROMSTART\r
+// Start address 0x0000 0000 \r
+// Size 256 Kbo 0x0004 0000 \r
+// RAMSTART\r
+// Start address 0x0020 0000 \r
+// Size 64Kbo 0x0001 0000 \r
+// Remap done\r
+// RAMSTART\r
+// Start address 0x0000 0000 \r
+// Size 64Kbo 0x0001 0000 \r
+// ROMSTART\r
+// Start address 0x0010 0000 \r
+// Size 256Kbo 0x0004 0000 \r
+\r
+//************************************************\r
+-carm\r
+\r
+//*************************************************************************\r
+// Internal Ram segments mapped AFTER REMAP 64K.\r
+//*************************************************************************\r
+// Use these addresses for the .\r
+-Z(CONST)INTRAMSTART_REMAP=00200000\r
+-Z(CONST)INTRAMEND_REMAP=0020FFFF\r
+\r
+//*************************************************************************\r
+// Read-only segments mapped to Flash 256K.\r
+//*************************************************************************\r
+-DROMSTART=00000000\r
+-DROMEND=0003FFFF\r
+//*************************************************************************\r
+// Read/write segments mapped to RAM.\r
+//*************************************************************************\r
+-DRAMSTART=00200000\r
+-DRAMEND=00200FFFF\r
+\r
+//************************************************\r
+// Address range for reset and exception\r
+// vectors (INTVEC).\r
+// The vector area is 32 bytes, \r
+// an additional 32 bytes is allocated for the\r
+// constant table used by ldr PC in cstartup.s79.\r
+//************************************************\r
+-Z(CODE)INTVEC=00-3F\r
+\r
+//************************************************\r
+// Startup code and exception routines (ICODE).\r
+//************************************************\r
+-Z(CODE)ICODE,DIFUNCT=ROMSTART-ROMEND\r
+-Z(CODE)SWITAB=ROMSTART-ROMEND\r
+\r
+//************************************************\r
+// Code segments may be placed anywhere.\r
+//************************************************\r
+-Z(CODE)CODE=ROMSTART-ROMEND\r
+\r
+//************************************************\r
+// Various constants and initializers.\r
+//************************************************\r
+-Z(CONST)INITTAB,DATA_ID,DATA_C=ROMSTART-ROMEND\r
+-Z(CONST)CHECKSUM=ROMSTART-ROMEND\r
+\r
+\r
+//************************************************\r
+// Data segments.\r
+//************************************************\r
+-Z(DATA)DATA_I,DATA_Z,DATA_N=RAMSTART-RAMEND\r
+\r
+//************************************************\r
+// __ramfunc code copied to and executed from RAM.\r
+//************************************************\r
+-Z(DATA)CODE_I=RAMSTART-RAMEND\r
+\r
+//************************************************\r
+// ICCARM produces code for __ramfunc functions in\r
+// CODE_I segments. The -Q XLINK command line\r
+// option redirects XLINK to emit the code in the\r
+// debug information associated with the CODE_I\r
+// segment, where the code will execute.\r
+//************************************************\r
+\r
+//*************************************************************************\r
+// Stack and heap segments.\r
+//*************************************************************************\r
+//-D_CSTACK_SIZE=(400*4)\r
+//-D_IRQ_STACK_SIZE=(2*8*4)\r
+\r
+//-Z(DATA)CSTACK+_CSTACK_SIZE=RAMSTART-RAMEND\r
+//-Z(DATA)IRQ_STACK+_IRQ_STACK_SIZE=RAMSTART-RAMEND\r
+\r
+//*************************************************************************\r
+// ELF/DWARF support.\r
+//\r
+// Uncomment the line "-Felf" below to generate ELF/DWARF output.\r
+// Available format specifiers are:\r
+//\r
+// "-yn": Suppress DWARF debug output\r
+// "-yp": Multiple ELF program sections\r
+// "-yas": Format suitable for debuggers from ARM Ltd (also sets -p flag)\r
+//\r
+// "-Felf" and the format specifiers can also be supplied directly as\r
+// command line options, or selected from the Xlink Output tab in the\r
+// IAR Embedded Workbench.\r
+//*************************************************************************\r
+\r
+// -Felf\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+ <fileVersion>2</fileVersion>\r
+ <configuration>\r
+ <name>Flash Debug</name>\r
+ <outputs>\r
+ <file>$PROJ_DIR$\uip\uipopt.h</file>\r
+ <file>$PROJ_DIR$\uip\fsdata.h</file>\r
+ <file>$TOOLKIT_DIR$\inc\intrinsic.h</file>\r
+ <file>$PROJ_DIR$\Flash_Debug\Obj\uip_arp.r79</file>\r
+ <file>$PROJ_DIR$\Flash_Debug\Obj\queue.r79</file>\r
+ <file>$PROJ_DIR$\Flash_Debug\Obj\ParTest.r79</file>\r
+ <file>$PROJ_DIR$\Flash_Debug\Obj\list.r79</file>\r
+ <file>$PROJ_DIR$\Flash_Debug\Obj\PollQ.r79</file>\r
+ <file>$PROJ_DIR$\..\..\Source\portable\IAR\AtmelSAM7S64\lib_AT91SAM7X256.h</file>\r
+ <file>$PROJ_DIR$\uip\uip.c</file>\r
+ <file>$PROJ_DIR$\..\..\Source\tasks.c</file>\r
+ <file>$PROJ_DIR$\..\..\Source\include\semphr.h</file>\r
+ <file>$PROJ_DIR$\uip\cgi.c</file>\r
+ <file>$PROJ_DIR$\uip\fs.c</file>\r
+ <file>$PROJ_DIR$\uip\httpd.c</file>\r
+ <file>$PROJ_DIR$\Flash_Debug\Obj\death.r79</file>\r
+ <file>$PROJ_DIR$\SrcIAR\Board.h</file>\r
+ <file>$PROJ_DIR$\..\Common\include\BlockQ.h</file>\r
+ <file>$PROJ_DIR$\..\..\Source\include\portable.h</file>\r
+ <file>$PROJ_DIR$\SrcIAR\Cstartup_SAM7.c</file>\r
+ <file>$PROJ_DIR$\SrcIAR\Cstartup.s79</file>\r
+ <file>$PROJ_DIR$\uip\uip_arp.c</file>\r
+ <file>$PROJ_DIR$\uip\uip_arch.c</file>\r
+ <file>$PROJ_DIR$\..\..\Source\portable\IAR\AtmelSAM7S64\ISR_Support.h</file>\r
+ <file>$PROJ_DIR$\Flash_Debug\Obj\BlockQ.r79</file>\r
+ <file>$PROJ_DIR$\Flash_Debug\Obj\heap_2.r79</file>\r
+ <file>$PROJ_DIR$\SrcIAR\Emac.h</file>\r
+ <file>$PROJ_DIR$\Flash_Debug\Obj\httpd.r79</file>\r
+ <file>$PROJ_DIR$\..\..\Source\portable\IAR\AtmelSAM7S64\AT91SAM7X256_inc.h</file>\r
+ <file>$PROJ_DIR$\EMAC\SAM7_EMAC.h</file>\r
+ <file>$PROJ_DIR$\Flash_Debug\Obj\main.pbi</file>\r
+ <file>$PROJ_DIR$\..\..\Source\portable\IAR\AtmelSAM7S64\AT91SAM7X256.h</file>\r
+ <file>$PROJ_DIR$\Flash_Debug\Obj\integer.r79</file>\r
+ <file>$PROJ_DIR$\Flash_Debug\Obj\portasm.r79</file>\r
+ <file>$PROJ_DIR$\uip\httpd.h</file>\r
+ <file>$PROJ_DIR$\Flash_Debug\Obj\SAM7_EMAC.r79</file>\r
+ <file>$PROJ_DIR$\Flash_Debug\Obj\dynamic.r79</file>\r
+ <file>$PROJ_DIR$\resource\at91SAM7X256_NoRemap.xcl</file>\r
+ <file>$PROJ_DIR$\..\Common\Minimal\death.c</file>\r
+ <file>$PROJ_DIR$\Flash_Debug\Obj\BlockQ.pbi</file>\r
+ <file>$TOOLKIT_DIR$\inc\DLib_Threads.h</file>\r
+ <file>$PROJ_DIR$\Flash_Debug\Obj\cgi.r79</file>\r
+ <file>$PROJ_DIR$\Flash_Debug\Obj\integer.pbi</file>\r
+ <file>$PROJ_DIR$\Flash_Debug\Exe\rtosdemo.sim</file>\r
+ <file>$PROJ_DIR$\Flash_Debug\Obj\Cstartup_SAM7.r79</file>\r
+ <file>$PROJ_DIR$\..\Common\include\death.h</file>\r
+ <file>$TOOLKIT_DIR$\inc\stddef.h</file>\r
+ <file>$PROJ_DIR$\Flash_Debug\Obj\main.r79</file>\r
+ <file>$PROJ_DIR$\Flash_Debug\Obj\port.r79</file>\r
+ <file>$PROJ_DIR$\Flash_Debug\Obj\flop.r79</file>\r
+ <file>$PROJ_DIR$\Flash_Debug\Obj\Cstartup.r79</file>\r
+ <file>$PROJ_DIR$\..\..\Source\include\croutine.h</file>\r
+ <file>$PROJ_DIR$\Flash_Debug\Obj\queue.pbi</file>\r
+ <file>$PROJ_DIR$\Flash_Debug\Obj\Cstartup_SAM7.pbi</file>\r
+ <file>$PROJ_DIR$\..\..\Source\portable\IAR\AtmelSAM7S64\AT91SAM7S64_inc.h</file>\r
+ <file>$PROJ_DIR$\Flash_Debug\Obj\flash.r79</file>\r
+ <file>$PROJ_DIR$\..\Common\include\integer.h</file>\r
+ <file>$PROJ_DIR$\Flash_Debug\Obj\semtest.r79</file>\r
+ <file>$TOOLKIT_DIR$\inc\string.h</file>\r
+ <file>$PROJ_DIR$\uip\tapdev.h</file>\r
+ <file>$PROJ_DIR$\Flash_Debug\Obj\list.pbi</file>\r
+ <file>$PROJ_DIR$\..\Common\include\semtest.h</file>\r
+ <file>$PROJ_DIR$\uip\uip_arp.h</file>\r
+ <file>$PROJ_DIR$\uip\fs.h</file>\r
+ <file>$PROJ_DIR$\..\Common\include\partest.h</file>\r
+ <file>$PROJ_DIR$\..\..\Source\include\list.h</file>\r
+ <file>$TOOLKIT_DIR$\inc\stdlib.h</file>\r
+ <file>$PROJ_DIR$\Flash_Debug\Obj\fs.r79</file>\r
+ <file>$PROJ_DIR$\..\..\Source\include\task.h</file>\r
+ <file>$TOOLKIT_DIR$\inc\xencoding_limits.h</file>\r
+ <file>$PROJ_DIR$\..\Common\include\PollQ.h</file>\r
+ <file>$PROJ_DIR$\..\..\Source\portable\IAR\AtmelSAM7S64\portmacro.h</file>\r
+ <file>$PROJ_DIR$\Flash_Debug\Exe\rtosdemo.d79</file>\r
+ <file>$PROJ_DIR$\Flash_Debug\Obj\dynamic.pbi</file>\r
+ <file>$TOOLKIT_DIR$\lib\dl4tptinl8n.h</file>\r
+ <file>$PROJ_DIR$\..\Common\Minimal\semtest.c</file>\r
+ <file>$PROJ_DIR$\uip\fsdata.c</file>\r
+ <file>$PROJ_DIR$\Flash_Debug\Obj\fs.pbi</file>\r
+ <file>$PROJ_DIR$\Flash_Debug\List\rtosdemo.map</file>\r
+ <file>$PROJ_DIR$\Flash_Debug\Obj\uIP_Task.r79</file>\r
+ <file>$PROJ_DIR$\Flash_Debug\Obj\EMAClISR.r79</file>\r
+ <file>$PROJ_DIR$\Flash_Debug\Obj\semtest.pbi</file>\r
+ <file>$PROJ_DIR$\uip\uip.h</file>\r
+ <file>$PROJ_DIR$\ParTest\ParTest.c</file>\r
+ <file>$TOOLKIT_DIR$\inc\stdio.h</file>\r
+ <file>$PROJ_DIR$\Flash_Debug\Obj\death.pbi</file>\r
+ <file>$PROJ_DIR$\uIP_Task.c</file>\r
+ <file>$PROJ_DIR$\..\Common\Minimal\PollQ.c</file>\r
+ <file>$PROJ_DIR$\EMAC\SAM7_EMAC.c</file>\r
+ <file>$PROJ_DIR$\..\Common\include\flop.h</file>\r
+ <file>$PROJ_DIR$\..\Common\include\flash.h</file>\r
+ <file>$PROJ_DIR$\uip\cgi.h</file>\r
+ <file>$PROJ_DIR$\..\..\Source\include\FreeRTOS.h</file>\r
+ <file>$TOOLKIT_DIR$\inc\DLib_Product.h</file>\r
+ <file>$PROJ_DIR$\uIP_Task.h</file>\r
+ <file>$PROJ_DIR$\Flash_Debug\Obj\uip_arch.r79</file>\r
+ <file>$TOOLKIT_DIR$\inc\DLib_Defaults.h</file>\r
+ <file>$PROJ_DIR$\FreeRTOSConfig.h</file>\r
+ <file>$PROJ_DIR$\Flash_Debug\Obj\rtosdemo.pbd</file>\r
+ <file>$PROJ_DIR$\Flash_Debug\Obj\heap_2.pbi</file>\r
+ <file>$PROJ_DIR$\Flash_Debug\Obj\port.pbi</file>\r
+ <file>$PROJ_DIR$\Flash_Debug\Obj\uip.pbi</file>\r
+ <file>$TOOLKIT_DIR$\inc\yvals.h</file>\r
+ <file>$TOOLKIT_DIR$\inc\ysizet.h</file>\r
+ <file>$PROJ_DIR$\Flash_Debug\Obj\uip.r79</file>\r
+ <file>$PROJ_DIR$\uip\uip_arch.h</file>\r
+ <file>$PROJ_DIR$\..\Common\include\dynamic.h</file>\r
+ <file>$PROJ_DIR$\Flash_Debug\Obj\uip_arch.pbi</file>\r
+ <file>$PROJ_DIR$\..\..\Source\portable\IAR\AtmelSAM7S64\port.c</file>\r
+ <file>$PROJ_DIR$\..\Common\Minimal\dynamic.c</file>\r
+ <file>$PROJ_DIR$\EMAC\EMAClISR.s79</file>\r
+ <file>$PROJ_DIR$\..\Common\Minimal\flash.c</file>\r
+ <file>$PROJ_DIR$\..\..\Source\include\projdefs.h</file>\r
+ <file>$PROJ_DIR$\Flash_Debug\Obj\flop.pbi</file>\r
+ <file>$PROJ_DIR$\Flash_Debug\Obj\uIP_Task.pbi</file>\r
+ <file>$PROJ_DIR$\Flash_Debug\Obj\cgi.pbi</file>\r
+ <file>$PROJ_DIR$\Flash_Debug\Obj\tasks.r79</file>\r
+ <file>$PROJ_DIR$\Flash_Debug\Obj\PollQ.pbi</file>\r
+ <file>$PROJ_DIR$\..\..\Source\portable\IAR\AtmelSAM7S64\portasm.s79</file>\r
+ <file>$PROJ_DIR$\Flash_Debug\Obj\httpd.pbi</file>\r
+ <file>$TOOLKIT_DIR$\inc\intrinsics.h</file>\r
+ <file>$PROJ_DIR$\Flash_Debug\Obj\flash.pbi</file>\r
+ <file>$TOOLKIT_DIR$\inc\ymath.h</file>\r
+ <file>$PROJ_DIR$\Flash_Debug\Obj\uip_arp.pbi</file>\r
+ <file>$TOOLKIT_DIR$\lib\dl4tptinl8n.r79</file>\r
+ <file>$PROJ_DIR$\..\..\Source\queue.c</file>\r
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+ <forcedrebuild>\r
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+ <file>$PROJ_DIR$\Flash Release\Obj\heap_2.pbi</file>\r
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+ <file>$PROJ_DIR$\SrcIAR\mii.h</file>\r
+ <file>$PROJ_DIR$\Flash Release\Exe\rtosdemo.sim</file>\r
+ <file>$PROJ_DIR$\Flash Release\Obj\SAM7_EMAC.pbi</file>\r
+ <file>$PROJ_DIR$\Flash Release\Obj\Cstartup_SAM7.pbi</file>\r
+ <file>$PROJ_DIR$\..\..\Source\include\queue.h</file>\r
+ <file>$TOOLKIT_DIR$\inc\math.h</file>\r
+ <file>$PROJ_DIR$\Flash Release\Obj\list.pbi</file>\r
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+ <file>$PROJ_DIR$\Flash Release\Obj\BlockQ.r79</file>\r
+ </outputs>\r
+ <file>\r
+ <name>$PROJ_DIR$\uip\uip.c</name>\r
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+ <tool>\r
+ <name>ICCARM</name>\r
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+ <name>BICOMP</name>\r
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+ <name>ICCARM</name>\r
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+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\tasks.c</name>\r
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+ <tool>\r
+ <name>ICCARM</name>\r
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+ <name>BICOMP</name>\r
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+ <name>ICCARM</name>\r
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+ <file>\r
+ <name>$PROJ_DIR$\uip\cgi.c</name>\r
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+ <tool>\r
+ <name>ICCARM</name>\r
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+ <name>BICOMP</name>\r
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+ <name>ICCARM</name>\r
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+ <file>\r
+ <name>$PROJ_DIR$\uip\fs.c</name>\r
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+ <tool>\r
+ <name>ICCARM</name>\r
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+ <name>BICOMP</name>\r
+ <file> 107</file>\r
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+ <tool>\r
+ <name>ICCARM</name>\r
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+ <file>\r
+ <name>$PROJ_DIR$\uip\httpd.c</name>\r
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+ <file>\r
+ <name>$PROJ_DIR$\SrcIAR\Cstartup_SAM7.c</name>\r
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+ <name>BICOMP</name>\r
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+ <name>AARM</name>\r
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+ <name>AARM</name>\r
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+ <name>ICCARM</name>\r
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+ <name>ICCARM</name>\r
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+ <tool>\r
+ <name>ICCARM</name>\r
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+ <name>BICOMP</name>\r
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+ <name>$PROJ_DIR$\..\..\Source\portable\IAR\AtmelSAM7S64\portasm.s79</name>\r
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+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 51</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 44 75 71 49 68 46 30 76 36 67 32 86 74 5 14 26 6 16 48 45 43</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\flop.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 82</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 2</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 44 75 71 49 68 46 30 76 128 94 67 32 86 74 5 14 26 6 16 48 45 43 64</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 44 75 71 68 46 30 76 128 94 67 32 86 74 5 93 14 26 6 16 48 45 43 64</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\MemMang\heap_2.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 104</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 121</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 44 75 71 49 68 46 30 76 67 32 86 74 5 14 26 6 16 48 45 43</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 44 75 71 68 46 30 76 67 32 86 74 5 93 14 26 6 16 48 45 43</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\integer.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 95</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 117</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 44 75 71 49 68 46 30 76 67 32 86 74 5 14 26 6 16 48 45 43 35</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 44 75 71 68 46 30 76 67 32 86 74 5 93 14 26 6 16 48 45 43 35</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\main.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 89</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 98</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 44 75 71 49 68 46 30 76 36 67 32 86 74 5 14 26 6 16 48 45 43 42 47 79 39 65 35 64 15 31 70</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 44 75 71 68 46 30 76 36 67 32 86 74 5 93 14 26 6 16 48 45 43 42 47 79 39 65 35 64 15 31 70</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>[ROOT_NODE]</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>XLINK</name>\r
+ <file> 91 124 60</file>\r
+ </tool>\r
+ </outputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\list.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 130</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 129</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 44 75 71 49 68 46 30 76 67 32 86 74 5 14 26 6 16 48 43</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\BlockQ.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 135</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 13</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 44 75 71 49 68 46 30 76 67 32 86 74 5 14 26 6 16 48 45 43 127 15</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 44 75 71 68 46 30 76 67 32 86 74 5 93 14 26 6 16 48 45 43 127 15</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ </configuration>\r
+</project>\r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+ <fileVersion>1</fileVersion>\r
+ <configuration>\r
+ <name>Flash Debug</name>\r
+ <toolchain>\r
+ <name>ARM</name>\r
+ </toolchain>\r
+ <debug>1</debug>\r
+ <settings>\r
+ <name>C-SPY</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>12</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CInput</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CEndian</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCVariant</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacOverride</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>MacFile</name>\r
+ <state>$PROJ_DIR$\resource\SAM7.mac</state>\r
+ </option>\r
+ <option>\r
+ <name>MemOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MemFile</name>\r
+ <state>$TOOLKIT_DIR$\CONFIG\ioat91sam7x256.ddf</state>\r
+ </option>\r
+ <option>\r
+ <name>RunToEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RunToName</name>\r
+ <state>main</state>\r
+ </option>\r
+ <option>\r
+ <name>CExtraOptionsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CFpuProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDDFArgumentProducer</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadSuppressDownload</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadVerifyAll</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadFlashDownload</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadFlashOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadFlashLoader</name>\r
+ <state>$TOOLKIT_DIR$\config\flashloader\Atmel\FlashAT91SAM7X256.d79</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadFlashLoaderSlave</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCProductVersion</name>\r
+ <state>4.10B</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDynDriverList</name>\r
+ <state>JLINK_ID</state>\r
+ </option>\r
+ <option>\r
+ <name>OCLastSavedByProductVersion</name>\r
+ <state>4.20A</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadFlashLoaderArgs</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadFlashBaseAddrOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadFlashBaseAddr</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadAttachToProgram</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ARMSIM_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCSimDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ANGEL_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CCAngelHeartbeat</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommunication</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommBaud</name>\r
+ <version>0</version>\r
+ <state>3</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ANGELTCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>DoAngelLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AngelLogFile</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>IARROM_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CRomLogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomLogFileEditB</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomCommunication</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomCommBaud</name>\r
+ <version>0</version>\r
+ <state>7</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>JLINK_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>JLinkSpeed</name>\r
+ <state>30</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkHWReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkTRSTReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDoJlinkMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkLogFile</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkHWResetDelay</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkSpeedRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>JLinkInitialSpeed</name>\r
+ <state>32</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>MACRAIGOR_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>jtag</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuSpeed</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>TCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>DoEmuMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuMultiTarget</name>\r
+ <state>0@ARM7TDMI</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuHWReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CEmuCommBaud</name>\r
+ <version>0</version>\r
+ <state>4</state>\r
+ </option>\r
+ <option>\r
+ <name>CEmuCommPort</name>\r
+ <version>0</version>\r
+ <state>4</state>\r
+ </option>\r
+ <option>\r
+ <name>jtago</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>UnusedAddr</name>\r
+ <state>0x00800000</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMacraigorHWResetDelay</name>\r
+ <state></state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>RDI_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CRDIDriverDll</name>\r
+ <state>Browse to your RDI driver</state>\r
+ </option>\r
+ <option>\r
+ <name>CRDILogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRDILogFileEdit</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDIHWReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchUndef</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchSWI</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchData</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchPrefetch</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchIRQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchFIQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDIUseETM</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>THIRDPARTY_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CThirdPartyDriverDll</name>\r
+ <state>Browse to your third-party driver</state>\r
+ </option>\r
+ <option>\r
+ <name>CThirdPartyLogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CThirdPartyLogFileEditB</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <debuggerPlugins>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Profiling\Profiling.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Trace\Trace.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ </debuggerPlugins>\r
+ </configuration>\r
+ <configuration>\r
+ <name>Flash Release</name>\r
+ <toolchain>\r
+ <name>ARM</name>\r
+ </toolchain>\r
+ <debug>0</debug>\r
+ <settings>\r
+ <name>C-SPY</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>12</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>CInput</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CEndian</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCVariant</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacOverride</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>MacFile</name>\r
+ <state>$PROJ_DIR$\resource\SAM7.mac</state>\r
+ </option>\r
+ <option>\r
+ <name>MemOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MemFile</name>\r
+ <state>$TOOLKIT_DIR$\CONFIG\ioat91sam7x256.ddf</state>\r
+ </option>\r
+ <option>\r
+ <name>RunToEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RunToName</name>\r
+ <state>main</state>\r
+ </option>\r
+ <option>\r
+ <name>CExtraOptionsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CFpuProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDDFArgumentProducer</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadSuppressDownload</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadVerifyAll</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadFlashDownload</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadFlashOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadFlashLoader</name>\r
+ <state>$TOOLKIT_DIR$\config\flashloader\Atmel\FlashAT91SAM7X256.d79</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadFlashLoaderSlave</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCProductVersion</name>\r
+ <state>4.10B</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDynDriverList</name>\r
+ <state>JLINK_ID</state>\r
+ </option>\r
+ <option>\r
+ <name>OCLastSavedByProductVersion</name>\r
+ <state>4.20A</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadFlashLoaderArgs</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadFlashBaseAddrOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadFlashBaseAddr</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadAttachToProgram</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ARMSIM_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>OCSimDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ANGEL_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>CCAngelHeartbeat</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommunication</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommBaud</name>\r
+ <version>0</version>\r
+ <state>3</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ANGELTCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>DoAngelLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AngelLogFile</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>IARROM_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>CRomLogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomLogFileEditB</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomCommunication</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomCommBaud</name>\r
+ <version>0</version>\r
+ <state>7</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>JLINK_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>JLinkSpeed</name>\r
+ <state>30</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkHWReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkTRSTReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDoJlinkMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkLogFile</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkHWResetDelay</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkSpeedRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>JLinkInitialSpeed</name>\r
+ <state>32</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>MACRAIGOR_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>jtag</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuSpeed</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>TCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>DoEmuMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuMultiTarget</name>\r
+ <state>0@ARM7TDMI</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuHWReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CEmuCommBaud</name>\r
+ <version>0</version>\r
+ <state>4</state>\r
+ </option>\r
+ <option>\r
+ <name>CEmuCommPort</name>\r
+ <version>0</version>\r
+ <state>4</state>\r
+ </option>\r
+ <option>\r
+ <name>jtago</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>UnusedAddr</name>\r
+ <state>0x00800000</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMacraigorHWResetDelay</name>\r
+ <state></state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>RDI_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>CRDIDriverDll</name>\r
+ <state>Browse to your RDI driver</state>\r
+ </option>\r
+ <option>\r
+ <name>CRDILogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRDILogFileEdit</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDIHWReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchUndef</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchSWI</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchData</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchPrefetch</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchIRQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchFIQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDIUseETM</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>THIRDPARTY_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>CThirdPartyDriverDll</name>\r
+ <state>Browse to your third-party driver</state>\r
+ </option>\r
+ <option>\r
+ <name>CThirdPartyLogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CThirdPartyLogFileEditB</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <debuggerPlugins>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Profiling\Profiling.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Trace\Trace.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ </debuggerPlugins>\r
+ </configuration>\r
+</project>\r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+ <fileVersion>1</fileVersion>\r
+ <configuration>\r
+ <name>Flash Debug</name>\r
+ <toolchain>\r
+ <name>ARM</name>\r
+ </toolchain>\r
+ <debug>1</debug>\r
+ <settings>\r
+ <name>General</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>9</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>GProcessorMode</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>ExePath</name>\r
+ <state>Flash_Debug\Exe</state>\r
+ </option>\r
+ <option>\r
+ <name>ObjPath</name>\r
+ <state>Flash_Debug\Obj</state>\r
+ </option>\r
+ <option>\r
+ <name>ListPath</name>\r
+ <state>Flash_Debug\List</state>\r
+ </option>\r
+ <option>\r
+ <name>Variant</name>\r
+ <version>3</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GEndianMode</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GInterwork</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GStackAlign</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>Input variant</name>\r
+ <version>1</version>\r
+ <state>3</state>\r
+ </option>\r
+ <option>\r
+ <name>Input description</name>\r
+ <state>No specifier n, no float nor long long, no scan set, no assignment suppressing.</state>\r
+ </option>\r
+ <option>\r
+ <name>Output variant</name>\r
+ <version>0</version>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>Output description</name>\r
+ <state>No specifier a, A, no specifier n, no float nor long long.</state>\r
+ </option>\r
+ <option>\r
+ <name>GOutputBinary</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>FPU</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OGCoreOrChip</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GRuntimeLibSelect</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GRuntimeLibSelectSlave</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RTDescription</name>\r
+ <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\r
+ </option>\r
+ <option>\r
+ <name>RTConfigPath</name>\r
+ <state>$TOOLKIT_DIR$\LIB\dl4tptinl8n.h</state>\r
+ </option>\r
+ <option>\r
+ <name>RTLibraryPath</name>\r
+ <state>$TOOLKIT_DIR$\LIB\dl4tptinl8n.r79</state>\r
+ </option>\r
+ <option>\r
+ <name>OGProductVersion</name>\r
+ <state>4.11A</state>\r
+ </option>\r
+ <option>\r
+ <name>OGLastSavedByProductVersion</name>\r
+ <state>4.31A</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraRules</name>\r
+ <version>0</version>\r
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralEnableMisra</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraVerbose</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OGChipSelectEditMenu</name>\r
+ <state>AT91SAM7X256 Atmel AT91SAM7X256</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ICCARM</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>13</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CCDefines</name>\r
+ <state>SAM7_IAR</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocComments</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCMnemonics</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCMessages</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListAssFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListAssSource</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCEnableRemarks</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagSuppress</name>\r
+ <state>pe815, pe191, pa082, pe167, pa050</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagRemark</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagWarning</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagError</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCObjPrefix</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptSizeSpeed</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptimization</name>\r
+ <version>0</version>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>CCAllowList</name>\r
+ <version>1</version>\r
+ <state>1000000</state>\r
+ </option>\r
+ <option>\r
+ <name>CCObjUseModuleName</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCObjModuleName</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCDebugInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IProcessorMode</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IEndianMode</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IStackAlign</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IInterwork</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IExtraOptionsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCLangConformance</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSignedPlainChar</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRequirePrototypes</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMultibyteSupport</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagWarnAreErr</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCompilerRuntimeInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IFpuProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OutputFile</name>\r
+ <state>$FILE_BNAME$.r79</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLangSelect</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLibConfigHeader</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptSizeSpeedSlave</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptimizationSlave</name>\r
+ <version>0</version>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCodeFunctions</name>\r
+ <state>CODE</state>\r
+ </option>\r
+ <option>\r
+ <name>CCData</name>\r
+ <state>DATA</state>\r
+ </option>\r
+ <option>\r
+ <name>PreInclude</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CompilerMisraRules</name>\r
+ <version>0</version>\r
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>CompilerMisraOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCModuleTypeOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCModuleType</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCModuleTypeCmdlineProducer</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCIncludePath2</name>\r
+ <state>$PROJ_DIR$\..\..\source\portable\iar\AtmelSAM7S64</state>\r
+ <state>$PROJ_DIR$\..\common\include</state>\r
+ <state>$PROJ_DIR$\..\..\source\include</state>\r
+ <state>$PROJ_DIR$\SrcIAR</state>\r
+ <state>$PROJ_DIR$</state>\r
+ <state>$PROJ_DIR$\uip</state>\r
+ <state>$PROJ_DIR$\emac</state>\r
+ </option>\r
+ <option>\r
+ <name>CCStdIncCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCStdIncludePath</name>\r
+ <state>$TOOLKIT_DIR$\INC\</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>AARM</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>6</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>AObjPrefix</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AEndian</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>ACaseSensitivity</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>MacroChars</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnWhat</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnOne</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnRange1</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnRange2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>ADebug</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AltRegisterNames</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ADefines</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>AList</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AListHeader</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AListing</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>Includes</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacDefs</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacExps</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>MacExec</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OnlyAssed</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MultiLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>PageLengthCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>PageLength</name>\r
+ <state>80</state>\r
+ </option>\r
+ <option>\r
+ <name>TabSpacing</name>\r
+ <state>8</state>\r
+ </option>\r
+ <option>\r
+ <name>AXRef</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AXRefDefines</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AXRefInternal</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AXRefDual</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AFpuProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
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--- /dev/null
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--- /dev/null
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--- /dev/null
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--- /dev/null
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--- /dev/null
+/*\r
+ * Modified from an original work that is Copyright (c) 2001-2003, Adam Dunkels.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ * 3. The name of the author may not be used to endorse or promote\r
+ * products derived from this software without specific prior\r
+ * written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * $Id: main.c,v 1.10.2.4 2003/10/21 21:27:51 adam Exp $\r
+ *\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdlib.h>\r
+#include <stdio.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "semphr.h"\r
+#include "task.h"\r
+\r
+/* Demo app includes. */\r
+#include "SAM7_EMAC.h"\r
+\r
+/* uIP includes. */\r
+#undef HTONS\r
+#include "uip.h"\r
+#include "uip_arp.h"\r
+#include "tapdev.h"\r
+#include "httpd.h"\r
+\r
+/* The start of the uIP buffer, which will contain the frame headers. */\r
+#define pucUIP_Buffer ( ( struct uip_eth_hdr * ) &uip_buf[ 0 ] )\r
+\r
+/* uIP update frequencies. */\r
+#define RT_CLOCK_SECOND ( configTICK_RATE_HZ )\r
+#define uipARP_FREQUENCY ( 20 )\r
+#define uipMAX_BLOCK_TIME ( RT_CLOCK_SECOND / 4 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vuIP_TASK( void *pvParameters )\r
+{\r
+/* The semaphore used by the EMAC ISR to indicate that an Rx frame is ready\r
+for processing. */\r
+xSemaphoreHandle xSemaphore = NULL;\r
+portBASE_TYPE xARPTimer;\r
+unsigned portBASE_TYPE uxPriority;\r
+static volatile portTickType xStartTime, xCurrentTime;\r
+\r
+ /* Initialize the uIP TCP/IP stack. */\r
+ uip_init();\r
+ uip_arp_init();\r
+ \r
+ /* Initialize the HTTP server. */\r
+ httpd_init();\r
+\r
+ /* Initialise the local timers. */\r
+ xStartTime = xTaskGetTickCount();\r
+ xARPTimer = 0;\r
+\r
+ /* Initialise the EMAC. A semaphore will be returned when this is\r
+ successful. This routine contains code that polls status bits. If the\r
+ Ethernet cable is not plugged in then this can take a considerable time.\r
+ To prevent this starving lower priority tasks of processing time we\r
+ lower our priority prior to the call, then raise it back again once the\r
+ initialisation is complete. */\r
+ uxPriority = uxTaskPriorityGet( NULL );\r
+ vTaskPrioritySet( NULL, tskIDLE_PRIORITY );\r
+ while( xSemaphore == NULL )\r
+ {\r
+ xSemaphore = xEMACInit();\r
+ }\r
+ vTaskPrioritySet( NULL, uxPriority );\r
+\r
+ for( ;; )\r
+ {\r
+ /* Let the network device driver read an entire IP packet\r
+ into the uip_buf. If it returns > 0, there is a packet in the\r
+ uip_buf buffer. */\r
+ uip_len = ulEMACPoll();\r
+\r
+ /* Was a packet placed in the uIP buffer? */\r
+ if( uip_len > 0 )\r
+ {\r
+ /* A packet is present in the uIP buffer. We call the\r
+ appropriate ARP functions depending on what kind of packet we\r
+ have received. If the packet is an IP packet, we should call\r
+ uip_input() as well. */\r
+ if( pucUIP_Buffer->type == htons( UIP_ETHTYPE_IP ) )\r
+ {\r
+ uip_arp_ipin();\r
+ uip_input();\r
+\r
+ /* If the above function invocation resulted in data that\r
+ should be sent out on the network, the global variable\r
+ uip_len is set to a value > 0. */\r
+ if( uip_len > 0 )\r
+ {\r
+ uip_arp_out();\r
+ lEMACSend();\r
+ }\r
+ }\r
+ else if( pucUIP_Buffer->type == htons( UIP_ETHTYPE_ARP ) )\r
+ {\r
+ uip_arp_arpin();\r
+\r
+ /* If the above function invocation resulted in data that\r
+ should be sent out on the network, the global variable\r
+ uip_len is set to a value > 0. */ \r
+ if( uip_len > 0 )\r
+ { \r
+ lEMACSend();\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* The poll function returned 0, so no packet was\r
+ received. Instead we check if it is time that we do the\r
+ periodic processing. */\r
+ xCurrentTime = xTaskGetTickCount();\r
+\r
+ if( ( xCurrentTime - xStartTime ) >= RT_CLOCK_SECOND )\r
+ {\r
+ portBASE_TYPE i;\r
+\r
+ /* Reset the timer. */\r
+ xStartTime = xCurrentTime;\r
+\r
+ /* Periodic check of all connections. */\r
+ for( i = 0; i < UIP_CONNS; i++ )\r
+ {\r
+ uip_periodic( i );\r
+\r
+ /* If the above function invocation resulted in data that\r
+ should be sent out on the network, the global variable\r
+ uip_len is set to a value > 0. */ \r
+ if( uip_len > 0 )\r
+ {\r
+ uip_arp_out();\r
+ lEMACSend();\r
+ }\r
+ }\r
+\r
+ #if UIP_UDP\r
+ for( i = 0; i < UIP_UDP_CONNS; i++ )\r
+ {\r
+ uip_udp_periodic( i );\r
+\r
+ /* If the above function invocation resulted in data that\r
+ should be sent out on the network, the global variable\r
+ uip_len is set to a value > 0. */\r
+ if( uip_len > 0 )\r
+ {\r
+ uip_arp_out();\r
+ tapdev_send();\r
+ }\r
+ }\r
+ #endif /* UIP_UDP */\r
+\r
+ /* Periodically call the ARP timer function. */\r
+ if( ++xARPTimer == uipARP_FREQUENCY )\r
+ { \r
+ uip_arp_timer();\r
+ xARPTimer = 0;\r
+ }\r
+ }\r
+ else\r
+ { \r
+ /* We did not receive a packet, and there was no periodic\r
+ processing to perform. Block for a fixed period. If a packet\r
+ is received during this period we will be woken by the ISR\r
+ giving us the Semaphore. */\r
+ xSemaphoreTake( xSemaphore, uipMAX_BLOCK_TIME );\r
+ }\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+#ifndef UIP_TASK_H\r
+#define UIP_TASK_H\r
+\r
+/* The task that handles all uIP data. */\r
+void vuIP_TASK( void *pvParameters );\r
+\r
+#endif\r
+\r
--- /dev/null
+# Copyright (c) 2001, Adam Dunkels.\r
+# All rights reserved. \r
+#\r
+# Redistribution and use in source and binary forms, with or without \r
+# modification, are permitted provided that the following conditions \r
+# are met: \r
+# 1. Redistributions of source code must retain the above copyright \r
+# notice, this list of conditions and the following disclaimer. \r
+# 2. Redistributions in binary form must reproduce the above copyright \r
+# notice, this list of conditions and the following disclaimer in the \r
+# documentation and/or other materials provided with the distribution. \r
+# 3. All advertising materials mentioning features or use of this software\r
+# must display the following acknowledgement:\r
+# This product includes software developed by Adam Dunkels.\r
+# 4. The name of the author may not be used to endorse or promote\r
+# products derived from this software without specific prior\r
+# written permission. \r
+#\r
+# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+# OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+# GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \r
+#\r
+# This file is part of the uIP TCP/IP stack.\r
+#\r
+# $Id: Makefile,v 1.8.2.2 2003/10/04 22:54:17 adam Exp $\r
+#\r
+\r
+CC=gcc\r
+CFLAGS=-Wall -g -I../uip -I. -I../apps/httpd -I../apps/resolv -I../apps/webclient -I../apps/smtp -I../apps/telnet -fpack-struct\r
+\r
+%.o:\r
+ $(CC) $(CFLAGS) -c $(<:.o=.c)\r
+\r
+\r
+uip: uip.o uip_arch.o tapdev.o httpd.o main.o fs.o uip_arp.o cgi.o \r
+\r
+tapdev.o: tapdev.c uipopt.h\r
+main.o: main.c ../uip/uip.h uipopt.h ../apps/httpd/httpd.h \\r
+ tapdev.h\r
+uip_arch.o: uip_arch.c ../uip/uip_arch.h ../uip/uip.h uipopt.h \\r
+ ../apps/httpd/httpd.h \r
+uip.o: ../uip/uip.c ../uip/uip.h uipopt.h ../apps/httpd/httpd.h \r
+\r
+uip_arp.o: ../uip/uip_arp.c ../uip/uip_arp.h ../uip/uip.h uipopt.h \\r
+ ../apps/httpd/httpd.h\r
+ $(CC) -o uip_arp.o $(CFLAGS) -fpack-struct -c ../uip/uip_arp.c\r
+\r
+\r
+cgi.o: ../apps/httpd/cgi.c ../uip/uip.h uipopt.h ../apps/smtp/smtp.h \\r
+ ../apps/httpd/cgi.h ../apps/httpd/httpd.h ../apps/httpd/fs.h\r
+fs.o: ../apps/httpd/fs.c ../uip/uip.h uipopt.h ../apps/smtp/smtp.h \\r
+ ../apps/httpd/httpd.h ../apps/httpd/fs.h ../apps/httpd/fsdata.h \\r
+ ../apps/httpd/fsdata.c\r
+fsdata.o: ../apps/httpd/fsdata.c\r
+httpd.o: ../apps/httpd/httpd.c ../uip/uip.h uipopt.h \\r
+ ../apps/smtp/smtp.h ../apps/httpd/httpd.h ../apps/httpd/fs.h \\r
+ ../apps/httpd/fsdata.h ../apps/httpd/cgi.h\r
+\r
+clean:\r
+ rm -f *.o *~ *core uip\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/**\r
+ * \addtogroup httpd\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * HTTP server script language C functions file.\r
+ * \author Adam Dunkels <adam@dunkels.com>\r
+ *\r
+ * This file contains functions that are called by the web server\r
+ * scripts. The functions takes one argument, and the return value is\r
+ * interpreted as follows. A zero means that the function did not\r
+ * complete and should be invoked for the next packet as well. A\r
+ * non-zero value indicates that the function has completed and that\r
+ * the web server should move along to the next script line.\r
+ *\r
+ */\r
+\r
+/*\r
+ * Copyright (c) 2001, Adam Dunkels.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ * 3. The name of the author may not be used to endorse or promote\r
+ * products derived from this software without specific prior\r
+ * written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * $Id: cgi.c,v 1.23.2.4 2003/10/07 13:22:27 adam Exp $\r
+ *\r
+ */\r
+\r
+#include "uip.h"\r
+#include "cgi.h"\r
+#include "httpd.h"\r
+#include "fs.h"\r
+\r
+#include <stdio.h>\r
+#include <string.h>\r
+\r
+static u8_t print_stats(u8_t next);\r
+static u8_t file_stats(u8_t next);\r
+static u8_t tcp_stats(u8_t next);\r
+static u8_t rtos_stats(u8_t next);\r
+\r
+cgifunction cgitab[] = {\r
+ print_stats, /* CGI function "a" */\r
+ file_stats, /* CGI function "b" */\r
+ tcp_stats, /* CGI function "c" */\r
+ rtos_stats /* CGI function "d" */\r
+};\r
+\r
+static const char closed[] = /* "CLOSED",*/\r
+{0x43, 0x4c, 0x4f, 0x53, 0x45, 0x44, 0};\r
+static const char syn_rcvd[] = /* "SYN-RCVD",*/\r
+{0x53, 0x59, 0x4e, 0x2d, 0x52, 0x43, 0x56,\r
+ 0x44, 0};\r
+static const char syn_sent[] = /* "SYN-SENT",*/\r
+{0x53, 0x59, 0x4e, 0x2d, 0x53, 0x45, 0x4e,\r
+ 0x54, 0};\r
+static const char established[] = /* "ESTABLISHED",*/\r
+{0x45, 0x53, 0x54, 0x41, 0x42, 0x4c, 0x49, 0x53, 0x48,\r
+ 0x45, 0x44, 0};\r
+static const char fin_wait_1[] = /* "FIN-WAIT-1",*/\r
+{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49,\r
+ 0x54, 0x2d, 0x31, 0};\r
+static const char fin_wait_2[] = /* "FIN-WAIT-2",*/\r
+{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49,\r
+ 0x54, 0x2d, 0x32, 0};\r
+static const char closing[] = /* "CLOSING",*/\r
+{0x43, 0x4c, 0x4f, 0x53, 0x49,\r
+ 0x4e, 0x47, 0};\r
+static const char time_wait[] = /* "TIME-WAIT,"*/\r
+{0x54, 0x49, 0x4d, 0x45, 0x2d, 0x57, 0x41,\r
+ 0x49, 0x54, 0};\r
+static const char last_ack[] = /* "LAST-ACK"*/\r
+{0x4c, 0x41, 0x53, 0x54, 0x2d, 0x41, 0x43,\r
+ 0x4b, 0};\r
+\r
+static const char *states[] = {\r
+ closed,\r
+ syn_rcvd,\r
+ syn_sent,\r
+ established,\r
+ fin_wait_1,\r
+ fin_wait_2,\r
+ closing,\r
+ time_wait,\r
+ last_ack};\r
+\r
+\r
+/*-----------------------------------------------------------------------------------*/\r
+/* print_stats:\r
+ *\r
+ * Prints out a part of the uIP statistics. The statistics data is\r
+ * written into the uip_appdata buffer. It overwrites any incoming\r
+ * packet.\r
+ */\r
+static u8_t\r
+print_stats(u8_t next)\r
+{\r
+#if UIP_STATISTICS\r
+ u16_t i, j;\r
+ u8_t *buf;\r
+ u16_t *databytes;\r
+\r
+ if(next) {\r
+ /* If our last data has been acknowledged, we move on the next\r
+ chunk of statistics. */\r
+ hs->count = hs->count + 4;\r
+ if(hs->count >= sizeof(struct uip_stats)/sizeof(u16_t)) {\r
+ /* We have printed out all statistics, so we return 1 to\r
+ indicate that we are done. */\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ /* Write part of the statistics into the uip_appdata buffer. */\r
+ databytes = (u16_t *)&uip_stat + hs->count;\r
+ buf = (u8_t *)uip_appdata;\r
+\r
+ j = 4 + 1;\r
+ i = hs->count;\r
+ while (i < sizeof(struct uip_stats)/sizeof(u16_t) && --j > 0) {\r
+ sprintf((char *)buf, "%5u\r\n", *databytes);\r
+ ++databytes;\r
+ buf += 6;\r
+ ++i;\r
+ }\r
+\r
+ /* Send the data. */\r
+ uip_send(uip_appdata, buf - uip_appdata);\r
+\r
+ return 0;\r
+#else\r
+ return 1;\r
+#endif /* UIP_STATISTICS */\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+static u8_t\r
+file_stats(u8_t next)\r
+{\r
+ /* We use sprintf() to print the number of file accesses to a\r
+ particular file (given as an argument to the function in the\r
+ script). We then use uip_send() to actually send the data. */\r
+ if(next) {\r
+ return 1;\r
+ }\r
+ uip_send(uip_appdata, sprintf((char *)uip_appdata, "%5u", fs_count(&hs->script[4])));\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+static u8_t\r
+tcp_stats(u8_t next)\r
+{\r
+ struct uip_conn *conn;\r
+\r
+ if(next) {\r
+ /* If the previously sent data has been acknowledged, we move\r
+ forward one connection. */\r
+ if(++hs->count == UIP_CONNS) {\r
+ /* If all connections has been printed out, we are done and\r
+ return 1. */\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ conn = &uip_conns[hs->count];\r
+ if((conn->tcpstateflags & TS_MASK) == CLOSED) {\r
+ uip_send(uip_appdata, sprintf((char *)uip_appdata,\r
+ "<tr align=\"center\"><td>-</td><td>-</td><td>%u</td><td>%u</td><td>%c %c</td></tr>\r\n",\r
+ conn->nrtx,\r
+ conn->timer,\r
+ (uip_outstanding(conn))? '*':' ',\r
+ (uip_stopped(conn))? '!':' '));\r
+ } else {\r
+ uip_send(uip_appdata, sprintf((char *)uip_appdata,\r
+ "<tr align=\"center\"><td>%u.%u.%u.%u:%u</td><td>%s</td><td>%u</td><td>%u</td><td>%c %c</td></tr>\r\n",\r
+ htons(conn->ripaddr[0]) >> 8,\r
+ htons(conn->ripaddr[0]) & 0xff,\r
+ htons(conn->ripaddr[1]) >> 8,\r
+ htons(conn->ripaddr[1]) & 0xff,\r
+ htons(conn->rport),\r
+ states[conn->tcpstateflags & TS_MASK],\r
+ conn->nrtx,\r
+ conn->timer,\r
+ (uip_outstanding(conn))? '*':' ',\r
+ (uip_stopped(conn))? '!':' '));\r
+ }\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+\r
+static u8_t\r
+rtos_stats(u8_t next)\r
+{\r
+static char cTraceBuffer[ 1024 ];\r
+extern void ( vTaskList )( char * );\r
+\r
+ vTaskList( cTraceBuffer );\r
+ uip_send( ( void * ) cTraceBuffer, strlen( cTraceBuffer ) );\r
+\r
+ return 1;\r
+}\r
--- /dev/null
+/**\r
+ * \addtogroup httpd\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * HTTP script language header file.\r
+ * \author Adam Dunkels <adam@dunkels.com>\r
+ */\r
+\r
+/*\r
+ * Copyright (c) 2001, Adam Dunkels.\r
+ * All rights reserved. \r
+ *\r
+ * Redistribution and use in source and binary forms, with or without \r
+ * modification, are permitted provided that the following conditions \r
+ * are met: \r
+ * 1. Redistributions of source code must retain the above copyright \r
+ * notice, this list of conditions and the following disclaimer. \r
+ * 2. Redistributions in binary form must reproduce the above copyright \r
+ * notice, this list of conditions and the following disclaimer in the \r
+ * documentation and/or other materials provided with the distribution. \r
+ * 3. The name of the author may not be used to endorse or promote\r
+ * products derived from this software without specific prior\r
+ * written permission. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * $Id: cgi.h,v 1.3.2.4 2003/10/07 13:22:27 adam Exp $\r
+ *\r
+ */\r
+\r
+#ifndef __CGI_H__\r
+#define __CGI_H__\r
+\r
+typedef u8_t (* cgifunction)(u8_t next);\r
+\r
+/**\r
+ * A table containing pointers to C functions that can be called from\r
+ * a web server script.\r
+ */\r
+extern cgifunction cgitab[];\r
+\r
+#endif /* __CGI_H__ */\r
--- /dev/null
+// Rowley C Compiler, runtime support.\r
+//\r
+// Copyright (c) 2001, 2002, 2003 Rowley Associates Limited.\r
+//\r
+// This file may be distributed under the terms of the License Agreement\r
+// provided with this software.\r
+//\r
+// THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE\r
+// WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\r
+\r
+; Create sections\r
+ .data\r
+ .bss\r
+\r
+; Go to code section.\r
+ .code\r
+\r
+; Executed upon reset\r
+__reset proc\r
+\r
+; Turn off watchdog. You can enable it in main() if required.\r
+ mov.w #0x5a80, &0x120\r
+\r
+; Set up stack.\r
+ mov.w #RAM_Start_Address+RAM_Size, sp\r
+\r
+; Copy from initialised data section to data section.\r
+ mov.w #SFB(IDATA0), r15\r
+ mov.w #data_init_begin, r14\r
+ mov.w #data_init_end-data_init_begin, r13\r
+ call #_memcpy\r
+\r
+; Zero the bss. Ensure the stack is not allocated in the bss!\r
+ mov.w #SFB(UDATA0), r15\r
+ mov.w #0, r14\r
+ mov.w #SFE(UDATA0)-SFB(UDATA0), r13\r
+ call #_memset\r
+\r
+; Call user entry point void main(void).\r
+ call #_main\r
+\r
+; If main() returns, kick off again.\r
+ jmp __reset\r
+ endproc\r
+\r
+; Heap data structures; removed by the linker if the heap isn't used.\r
+ .break \r
+ .data\r
+ align WORD\r
+___heap_start__::\r
+ DW 0\r
+ DW heap_size\r
+ DS heap_size-4 \r
+\r
+; Reset vector\r
+ .vectors\r
+ .keep\r
+ org 0x1e\r
+ dw __reset\r
+\r
+; Initialise the IDATA0 section by duplicating the contents into the\r
+; CONST section and copying them on startup.\r
+ .const\r
+data_init_begin:\r
+ .init "IDATA0"\r
+data_init_end:\r
--- /dev/null
+/**\r
+ * \addtogroup httpd\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * HTTP server read-only file system code.\r
+ * \author Adam Dunkels <adam@dunkels.com>\r
+ *\r
+ * A simple read-only filesystem.\r
+ */\r
+\r
+/*\r
+ * Copyright (c) 2001, Swedish Institute of Computer Science.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ * 3. Neither the name of the Institute nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND\r
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\r
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\r
+ * SUCH DAMAGE.\r
+ *\r
+ * This file is part of the lwIP TCP/IP stack.\r
+ *\r
+ * Author: Adam Dunkels <adam@sics.se>\r
+ *\r
+ * $Id: fs.c,v 1.7.2.3 2003/10/07 13:22:27 adam Exp $\r
+ */\r
+\r
+#include "uip.h"\r
+#include "httpd.h"\r
+#include "fs.h"\r
+#include "fsdata.h"\r
+\r
+#define NULL (void *)0\r
+#include "fsdata.c"\r
+\r
+#ifdef FS_STATISTICS\r
+#if FS_STATISTICS == 1\r
+static u16_t count[FS_NUMFILES];\r
+#endif /* FS_STATISTICS */\r
+#endif /* FS_STATISTICS */\r
+\r
+/*-----------------------------------------------------------------------------------*/\r
+static u8_t\r
+fs_strcmp(const char *str1, const char *str2)\r
+{\r
+ u8_t i;\r
+ i = 0;\r
+ loop:\r
+\r
+ if(str2[i] == 0 ||\r
+ str1[i] == '\r' ||\r
+ str1[i] == '\n') {\r
+ return 0;\r
+ }\r
+\r
+ if(str1[i] != str2[i]) {\r
+ return 1;\r
+ }\r
+\r
+\r
+ ++i;\r
+ goto loop;\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+int\r
+fs_open(const char *name, struct fs_file *file)\r
+{\r
+#ifdef FS_STATISTICS\r
+#if FS_STATISTICS == 1\r
+ u16_t i = 0;\r
+#endif /* FS_STATISTICS */\r
+#endif /* FS_STATISTICS */\r
+ struct fsdata_file_noconst *f;\r
+\r
+ for(f = (struct fsdata_file_noconst *)FS_ROOT;\r
+ f != NULL;\r
+ f = (struct fsdata_file_noconst *)f->next) {\r
+\r
+ if(fs_strcmp(name, f->name) == 0) {\r
+ file->data = f->data;\r
+ file->len = f->len;\r
+#ifdef FS_STATISTICS\r
+#if FS_STATISTICS == 1\r
+ ++count[i];\r
+#endif /* FS_STATISTICS */\r
+#endif /* FS_STATISTICS */\r
+\r
+ return 1;\r
+ }\r
+#ifdef FS_STATISTICS\r
+#if FS_STATISTICS == 1\r
+ ++i;\r
+#endif /* FS_STATISTICS */\r
+#endif /* FS_STATISTICS */\r
+\r
+ }\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+void\r
+fs_init(void)\r
+{\r
+#ifdef FS_STATISTICS\r
+#if FS_STATISTICS == 1\r
+ u16_t i;\r
+ for(i = 0; i < FS_NUMFILES; i++) {\r
+ count[i] = 0;\r
+ }\r
+#endif /* FS_STATISTICS */\r
+#endif /* FS_STATISTICS */\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+#ifdef FS_STATISTICS\r
+#if FS_STATISTICS == 1\r
+u16_t fs_count\r
+(char *name)\r
+{\r
+ struct fsdata_file_noconst *f;\r
+ u16_t i;\r
+\r
+ i = 0;\r
+ for(f = (struct fsdata_file_noconst *)FS_ROOT;\r
+ f != NULL;\r
+ f = (struct fsdata_file_noconst *)f->next) {\r
+\r
+ if(fs_strcmp(name, f->name) == 0) {\r
+ return count[i];\r
+ }\r
+ ++i;\r
+ }\r
+ return 0;\r
+}\r
+#endif /* FS_STATISTICS */\r
+#endif /* FS_STATISTICS */\r
+/*-----------------------------------------------------------------------------------*/\r
--- /dev/null
+/**\r
+ * \addtogroup httpd\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * HTTP server read-only file system header file.\r
+ * \author Adam Dunkels <adam@dunkels.com>\r
+ */\r
+ \r
+/*\r
+ * Copyright (c) 2001, Swedish Institute of Computer Science.\r
+ * All rights reserved. \r
+ *\r
+ * Redistribution and use in source and binary forms, with or without \r
+ * modification, are permitted provided that the following conditions \r
+ * are met: \r
+ * 1. Redistributions of source code must retain the above copyright \r
+ * notice, this list of conditions and the following disclaimer. \r
+ * 2. Redistributions in binary form must reproduce the above copyright \r
+ * notice, this list of conditions and the following disclaimer in the \r
+ * documentation and/or other materials provided with the distribution. \r
+ * 3. Neither the name of the Institute nor the names of its contributors \r
+ * may be used to endorse or promote products derived from this software \r
+ * without specific prior written permission. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND \r
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE \r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE \r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE \r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL \r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS \r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) \r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT \r
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY \r
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF \r
+ * SUCH DAMAGE. \r
+ *\r
+ * This file is part of the lwIP TCP/IP stack.\r
+ * \r
+ * Author: Adam Dunkels <adam@sics.se>\r
+ *\r
+ * $Id: fs.h,v 1.6.2.3 2003/10/07 13:22:27 adam Exp $\r
+ */\r
+#ifndef __FS_H__\r
+#define __FS_H__\r
+\r
+#include "uip.h"\r
+\r
+/**\r
+ * An open file in the read-only file system.\r
+ */\r
+struct fs_file {\r
+ char *data; /**< The actual file data. */\r
+ int len; /**< The length of the file data. */\r
+};\r
+\r
+/**\r
+ * Open a file in the read-only file system.\r
+ *\r
+ * \param name The name of the file.\r
+ *\r
+ * \param file The file pointer, which must be allocated by caller and\r
+ * will be filled in by the function.\r
+ */\r
+int fs_open(const char *name, struct fs_file *file);\r
+\r
+#ifdef FS_STATISTICS\r
+#if FS_STATISTICS == 1 \r
+u16_t fs_count(char *name);\r
+#endif /* FS_STATISTICS */\r
+#endif /* FS_STATISTICS */\r
+\r
+/**\r
+ * Initialize the read-only file system.\r
+ */\r
+void fs_init(void);\r
+\r
+#endif /* __FS_H__ */\r
--- /dev/null
+<html><body bgcolor="white"><center><h1>404 - file not found</h1></center></body></html>
\ No newline at end of file
--- /dev/null
+# This script shows the access statistics for different files on the\r
+# web server.\r
+#\r
+# First, we include the HTML header.\r
+i /files_header.html\r
+# Print out the name of the file, and call the function that prints\r
+# the access statistics of that file.\r
+t <tr><td><a href="/index.html">/index.html</a></td><td>\r
+c b /index.html\r
+t </td></tr> <tr><td><a href="/control.html">/control.html</a></td><td>\r
+c b /control.html\r
+t </td></tr> <tr><td><a href="/img/logo.png">/img/logo.png</a></td><td>\r
+c b /img/logo.png\r
+t </td></tr> <tr><td><a href="/404.html">/404.html</a></td><td>\r
+c b /404.html\r
+t </td></tr> <tr><td><a href="/cgi/files">/cgi/files</a></td><td>\r
+c b /cgi/files\r
+t </td></tr> <tr><td><a href="/cgi/stats">/cgi/stats</a></td><td>\r
+c b /cgi/stats\r
+t </td></tr> <tr><td><a href="/cgi/tcp">/cgi/tcp</a></td><td>\r
+c b /cgi/tcp\r
+t </td></tr>\r
+# Include the HTML footer.\r
+i /files_footer.plain\r
+# End of script.\r
+.
\ No newline at end of file
--- /dev/null
+t <html><head><title>uIP Open Source Embedded TCP/IP Stack On FreeRTOS Kernel</title></head><body BGCOLOR="#CCCCFF"><font face="arial"><small><b><a href="http://www.freertos.org" target="_top">FreeRTOS Homepage</a></b></small><p><H1>AT91SAM7X Embedded WEB Server Demo<br><small>Using uIP and the FreeRTOS real time kernel</small></h1><p>These pages are being served by an Atmel AT91SAM7X256 microcontroller, using Adam Dunkels open source uIP TCP/IP stack.<p>The uIP stack is executing from a single task under control of the FreeRTOS real time kernel. The table below shows the statistics for all the tasks in the demo applicaiton.<p><pre>Task State Priority Stack #<br>************************************************<br>
+c d
+t </pre></font></body></html>
+.
+
+
--- /dev/null
+i /stats_header.html\r
+c a\r
+i /stats_footer.plain\r
+.\r
--- /dev/null
+i /tcp_header.html\r
+c c\r
+i /tcp_footer.plain\r
+.
\ No newline at end of file
--- /dev/null
+<html>\r
+<head>\r
+<title>AT91SAM7X Embedded WEB Server using uIP and FreeRTOS</title>\r
+</head>\r
+<body bgcolor="#ccccff">\r
+<font face="arial">\r
+<img src="/img/logo.png" align="right">\r
+<a href="/cgi/rtos" target="main">Tasks</a> |\r
+<a href="/cgi/tcp" target="main">Connections</a> |\r
+<a href="/cgi/files" target="main">Files</a> |\r
+<a href="/cgi/stats" target="main">Statistics</a><br>\r
+<br>\r
+</font>\r
+</body>\r
+</html>\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+</td></tr></table>\r
+</body>\r
+</html>\r
--- /dev/null
+<html>\r
+<body bgcolor="#CCCCFF">\r
+<center>\r
+<table width="600" border="0">\r
--- /dev/null
+<html>\r
+<head>\r
+</head>\r
+\r
+<frameset cols="*" rows="120,*" frameborder="no"> \r
+ <frame src="control.html">\r
+ <frame src="/cgi/rtos" name="main">\r
+</frameset>\r
+\r
+<noframes>\r
+<body>\r
+Your browser must support frames\r
+</body>\r
+</noframes>\r
+</html>
\ No newline at end of file
--- /dev/null
+</td></tr></table>\r
+</body>\r
+</html>\r
--- /dev/null
+<html>\r
+<body bgcolor="#ccccff">\r
+<center>\r
+<table width="600" border="0">\r
+<tr><td>\r
+<pre>\r
+IP Packets dropped\r
+ Packets received\r
+ Packets sent\r
+IP errors IP version/header length\r
+ IP length, high byte\r
+ IP length, low byte\r
+ IP fragments\r
+ Header checksum\r
+ Wrong protocol\r
+ICMP Packets dropped\r
+ Packets received\r
+ Packets sent\r
+ Type errors\r
+TCP Packets dropped\r
+ Packets received\r
+ Packets sent\r
+ Checksum errors\r
+ Data packets without ACKs\r
+ Resets\r
+ Retransmissions\r
+ No connection avaliable\r
+ Connection attempts to closed ports\r
+</pre> \r
+</td><td><pre>
\ No newline at end of file
--- /dev/null
+\r
+</td></tr></table>\r
+</center>\r
+</body>\r
+</html>
\ No newline at end of file
--- /dev/null
+<html>\r
+<body bgcolor="#ccccff">\r
+<center>\r
+<table width="600" border="0">\r
+<tr><th>Remote</th><th>State</th><th>Retransmissions</th><th>Timer</th><th>Flags</th></tr>\r
+\r
--- /dev/null
+static const char data_404_html[] = {
+ /* /404.html */
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+
+static const char data_control_html[] = {
+ /* /control.html */
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+
+static const char data_files_footer_plain[] = {
+ /* /files_footer.plain */
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+static const char data_files_header_html[] = {
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+static const char data_tcp_footer_plain[] = {
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+static const char data_tcp_header_html[] = {
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+static const char data_img_logo_png[] = {
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+ 0xba, 0xbc, 0xff, 0xbc, 0xbe, 0xff, 0xbe, 0xc0, 0xc0, 0xc0,
+ 0xc3, 0xc3, 0xc3, 0xc4, 0xc4, 0xc4, 0xc6, 0xc6, 0xc6, 0xc8,
+ 0xc8, 0xc8, 0xca, 0xca, 0xca, 0xcc, 0xcc, 0xcc, 0xcf, 0xcf,
+ 0xcf, 0xd0, 0xd0, 0xd0, 0xd2, 0xd2, 0xd2, 0xd4, 0xd4, 0xd4,
+ 0xd6, 0xd6, 0xd6, 0xd8, 0xd8, 0xd8, 0xda, 0xda, 0xda, 0xdc,
+ 0xdc, 0xdc, 0xdf, 0xdf, 0xdf, 0xc0, 0xff, 0xc0, 0xc2, 0xff,
+ 0xc2, 0xc4, 0xff, 0xc4, 0xc6, 0xff, 0xc6, 0xc8, 0xff, 0xc8,
+ 0xca, 0xff, 0xca, 0xcc, 0xf8, 0xcc, 0xce, 0xf8, 0xce, 0xcc,
+ 0xff, 0xcc, 0xce, 0xff, 0xce, 0xd0, 0xf8, 0xd0, 0xd0, 0xff,
+ 0xd0, 0xd2, 0xff, 0xd2, 0xd6, 0xf9, 0xd6, 0xd4, 0xff, 0xd4,
+ 0xd6, 0xff, 0xd6, 0xd9, 0xf9, 0xd9, 0xd8, 0xff, 0xd8, 0xda,
+ 0xff, 0xda, 0xdc, 0xfa, 0xdc, 0xdc, 0xff, 0xdc, 0xde, 0xff,
+ 0xde, 0xe0, 0xe0, 0xe0, 0xe2, 0xe2, 0xe2, 0xe4, 0xe4, 0xe4,
+ 0xe6, 0xe6, 0xe6, 0xe8, 0xe8, 0xe8, 0xea, 0xea, 0xea, 0xec,
+ 0xec, 0xec, 0xee, 0xee, 0xee, 0xe1, 0xfa, 0xe1, 0xe3, 0xfb,
+ 0xe3, 0xe0, 0xff, 0xe0, 0xe2, 0xff, 0xe2, 0xe5, 0xfb, 0xe5,
+ 0xe4, 0xff, 0xe4, 0xe6, 0xff, 0xe6, 0xe8, 0xfc, 0xe8, 0xe8,
+ 0xff, 0xe8, 0xea, 0xfc, 0xea, 0xea, 0xff, 0xea, 0xec, 0xff,
+ 0xec, 0xee, 0xfd, 0xee, 0xee, 0xff, 0xee, 0xf0, 0xf0, 0xf0,
+ 0xf2, 0xf2, 0xf2, 0xf4, 0xf4, 0xf4, 0xf6, 0xf6, 0xf6, 0xf1,
+ 0xfd, 0xf1, 0xf0, 0xff, 0xf0, 0xf3, 0xfd, 0xf3, 0xf2, 0xff,
+ 0xf2, 0xf5, 0xfd, 0xf5, 0xf4, 0xfe, 0xf4, 0xf6, 0xfe, 0xf6,
+ 0xf8, 0xf8, 0xf8, 0xfa, 0xfa, 0xfa, 0xf8, 0xfe, 0xf8, 0xfa,
+ 0xfe, 0xfa, 0xff, 00, 00, 0xfc, 0xfe, 0xfc, 0xfe, 0xfe,
+ 0xfe, 0xd7, 0xd6, 0xbe, 0x1c, 00, 00, 00, 0xfe, 0x74,
+ 0x52, 0x4e, 0x53, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 00, 0xd8, 0xd9, 0xc,
+ 0x71, 00, 00, 0xc, 0xc6, 0x49, 0x44, 0x41, 0x54, 0x78,
+ 0xda, 0xed, 0x9c, 0xf, 0x50, 0x14, 0xd7, 0x19, 0xc0, 0xdf,
+ 0xc2, 0x21, 0x2c, 0x77, 0x27, 0xa0, 0x1, 0x3d, 0x15, 0x10,
+ 0x4, 0x39, 0x23, 0xe3, 0x14, 0x1, 0xeb, 0x1f, 0xc0, 0x51,
+ 0x87, 0x88, 0x81, 0x91, 0x92, 0xa8, 0x41, 0x32, 0x49, 0xac,
+ 0xb6, 0x8e, 0xa5, 0xa6, 0x8e, 0x1d, 0x3b, 0x6d, 0x9c, 0xce,
+ 0x64, 0x3a, 0xda, 0xd8, 0x4e, 0xda, 0x4e, 0x67, 0x9c, 0x74,
+ 0x92, 0x36, 0xa, 0xb6, 0x62, 0xac, 0xa6, 0x15, 0xdb, 0x10,
+ 0xe8, 0x58, 0xb4, 0xa, 0x6, 0x14, 0x73, 0x54, 0x73, 0x53,
+ 0x8e, 0x62, 0x4c, 0xf8, 0x93, 0x9c, 0x60, 0x10, 0xc9, 0x82,
+ 0x87, 0x1c, 0xb0, 0x7d, 0xbb, 0xcb, 0xdd, 0xbd, 0xb7, 0xfb,
+ 0xde, 0xde, 0xae, 0x98, 0x94, 0x23, 0x99, 0xdf, 0xcc, 0xed,
+ 0xbd, 0xdd, 0xf7, 0xde, 0xed, 0xb7, 0xef, 0xbd, 0xef, 0x7d,
+ 0xdf, 0xf7, 0xde, 0x1e, 0x33, 0xa, 00, 0xb8, 0x76, 0xf0,
+ 0x36, 0xfc, 0x9c, 0xd2, 0xa4, 0x1c, 0x83, 0x1f, 0x50, 0xd8,
+ 0x53, 0x7f, 0xfc, 0x6c, 0x82, 0x35, 0x5, 0x2, 0xec, 0xd6,
+ 0x9d, 0x50, 0xd8, 0x3f, 0xbd, 0x36, 0xe1, 0x8a, 0x2, 0x83,
+ 0xef, 0x3f, 0xc7, 0x8c, 0xe6, 0x72, 0x13, 0xae, 0x26, 0x30,
+ 0x30, 0x9f, 0x33, 0xbc, 0x20, 0xc9, 0x6a, 0x88, 0xc, 0x9e,
+ 0x50, 0x4d, 0x93, 0x92, 0xa0, 0x69, 0xd2, 0x71, 0xb0, 0x4f,
+ 0xd0, 0x4c, 0xdc, 0x29, 0x26, 0x53, 0x48, 0xb1, 0x31, 0xd9,
+ 0x39, 0x33, 0x1e, 0xb2, 0xc6, 0x49, 0x4c, 0x58, 0x8c, 0x74,
+ 0xfc, 0xe0, 0x17, 0x1f, 0xbb, 0xe1, 0x61, 0xba, 0x24, 0x6c,
+ 0xfc, 0x6b, 0xe3, 0xa7, 0xa7, 0x28, 0x1d, 0x3f, 0xf8, 0x54,
+ 0x38, 0x4, 0x9, 0x1f, 0x21, 0xeb, 0xa6, 0xb6, 0xac, 0x20,
+ 0x6e, 0xad, 0x41, 0x38, 0x88, 0xc2, 0x1a, 0xd8, 0x9, 0x54,
+ 0x14, 0x10, 0x44, 0x84, 0x8, 0x9f, 0xa2, 0xb0, 0x5f, 0x15,
+ 0xbe, 0x16, 0x76, 0xaa, 0x22, 0xe, 0x5c, 0x1a, 0xfd, 0x63,
+ 0x7d, 0x1f, 0xa7, 0x47, 0x68, 0xab, 0xe8, 0x91, 0xe2, 0xe2,
+ 0x84, 0x89, 0x11, 0x12, 0x6c, 0xd6, 0xaa, 0x4e, 0xc4, 0x22,
+ 0xfd, 0xc2, 0xcd, 0xd2, 0xcb, 0xd0, 0x85, 0xed, 0x7b, 0xef,
+ 0x82, 0xcb, 0xdd, 0x78, 0xaf, 0x7c, 0xad, 0xef, 0x94, 0xb3,
+ 0x8b, 0x92, 0xd7, 0xc, 0x40, 0xbc, 0xfc, 0x17, 0xa8, 0x99,
+ 0x51, 0x82, 0xe7, 0x29, 0xe6, 0x81, 0x9e, 0xae, 0xd1, 0xa1,
+ 0xee, 0xdb, 0x3, 00, 0xb4, 0xa6, 00, 0x60, 0x9a, 0x61,
+ 0xb2, 0x4, 0x5b, 0x2c, 0xea, 0x95, 0xb8, 0xda, 0xb9, 0xa1,
+ 0xbe, 0xde, 0xde, 0x11, 0xa9, 0x88, 0x61, 0xa6, 0x79, 0x56,
+ 0x18, 0x30, 0x2b, 0xee, 0x7, 0x42, 0x13, 0xd6, 0xfd, 0xaf,
+ 0xd3, 0x67, 0x7a, 0xe1, 0x91, 0x75, 0xf7, 0xd7, 0xd7, 00,
+ 0xb0, 0x1b, 0xd6, 0x2, 0x5c, 0x17, 0x2a, 0x29, 0xb9, 0xcd,
+ 0xc9, 0x20, 0xce, 0x14, 0x15, 0x6d, 0x45, 0xcf, 0x5d, 0xae,
+ 0x1a, 0xa4, 0xe4, 0x46, 0x30, 0x6e, 0xc7, 0x85, 0x75, 0xd9,
+ 0x9d, 0x1d, 0xef, 0x7b, 0xca, 0xd9, 0xc6, 0xf3, 0x2c, 0x89,
+ 0x9d, 0x95, 0x42, 0x9f, 0x1b, 0x6d, 0x5d, 0x3, 0xb5, 0x5e,
+ 0x8b, 0x77, 0xbc, 0x8, 0x60, 0xd2, 0xe2, 0x62, 0x93, 0x14,
+ 0xcf, 0x88, 0x26, 0x6c, 0xed, 0x4e, 0x6f, 0xc3, 0x54, 0xbd,
+ 0xe, 0x40, 0xe8, 0x21, 0x51, 0x77, 0xd3, 0xe0, 0x6c, 0xf0,
+ 0x67, 0xe0, 0xf, 0x58, 0x97, 0xaa, 0xe5, 0xf2, 0x8b, 0xeb,
+ 0xda, 0xcd, 0x4b, 0xca, 0x27, 0x34, 0xd8, 0xd0, 0x60, 0x5c,
+ 0xb2, 0x60, 0x39, 0x51, 0x5c, 0x97, 0xbd, 0xad, 0xc3, 0x23,
+ 0x20, 0xa, 0x6f, 0xb3, 0x19, 0x4b, 0xb5, 0xa, 0x7b, 0xd1,
+ 0x27, 0x6b, 0xc4, 0x74, 0xd6, 0x5, 0xde, 0x2d, 0x4d, 0x24,
+ 0x67, 0x44, 0x80, 0x3f, 0xb0, 0xf4, 0x7a, 0xfe, 0x4, 0xcc,
+ 0x13, 0xdb, 0x75, 0x82, 0xa8, 0x22, 0x83, 0xd, 0x37, 0x3e,
+ 0xcc, 0xc8, 0x50, 0x76, 0x4c, 0x47, 0x43, 0x3d, 0xd5, 0x8d,
+ 0x9, 0x9a, 0xa7, 0x38, 0x45, 0x16, 0xd6, 0xfd, 0x77, 0x64,
+ 0xc0, 0xad, 0x3f, 0xfd, 0x11, 0xe8, 0x6e, 0xf7, 0x2f, 0x2c,
+ 0xc4, 0xc6, 0xf4, 0x3e, 0xeb, 0x67, 0x80, 0xd1, 0xa9, 0x2b,
+ 0x1f, 0xe0, 0xa9, 0x17, 0xa1, 0xb8, 0x37, 0x15, 0xf, 0xb2,
+ 0xa9, 0xb6, 0x99, 0x5e, 0x82, 00, 0x59, 0xd8, 0xf6, 0xa,
+ 0xf8, 0x31, 0xa7, 0x78, 0xec, 0xd, 0x17, 0x3c, 0xc6, 0x42,
+ 0xdf, 0xa1, 0x1f, 0x8e, 0x7e, 0x2d, 0xf0, 0x57, 0x5b, 0xe,
+ 0x3e, 0x9c, 0xb4, 0xae, 0x2a, 0x3f, 0x63, 0x7c, 0xb0, 0xa6,
+ 0xf7, 0x79, 0x5c, 0x5a, 0xdb, 0xef, 0xd4, 0x4a, 0x24, 0x47,
+ 0x2a, 0x4e, 0x91, 0xe7, 0xd9, 0x4f, 0xee, 00, 0x90, 0x50,
+ 0x76, 0x68, 0xbd, 0xf8, 0x28, 0xe2, 0xb3, 0x1, 0x18, 0xa3,
+ 0x55, 0xa9, 0x80, 0xfb, 0xa9, 0xe6, 0xac, 0x28, 0xae, 0x33,
+ 0xa7, 0xfd, 0xe9, 0x33, 0xfe, 0xea, 0x4b, 0x3d, 0x68, 0xda,
+ 0x79, 0x58, 0xbd, 0x84, 0xb2, 0xd7, 0x93, 0x85, 0x1d, 0x83,
+ 0xc2, 0x45, 0xe4, 0x8e, 0xeb, 0xa4, 0xae, 0xf7, 0x28, 0xb5,
+ 0x91, 0xe1, 0xca, 0x74, 0x65, 0x97, 0x70, 0x9d, 0x39, 0xab,
+ 0xa1, 0x43, 0x72, 0x2f, 0x9, 0x3d, 0x6d, 0x9c, 0x9e, 0xfd,
+ 0x1a, 0xb4, 0x3d, 0xe, 0x59, 0x58, 0xe1, 0x87, 0x19, 0x4f,
+ 0x62, 0x78, 0x58, 0x4b, 0x45, 0x3e, 0x2e, 0xe9, 0xcb, 0x2e,
+ 0x62, 0xaf, 0x54, 0xca, 0xea, 0xbd, 0x1, 0x1f, 0x1c, 0x9c,
+ 0x18, 0x3c, 0x10, 0x95, 0x19, 0x52, 0x86, 0x30, 0x40, 0xc9,
+ 0x63, 0x56, 0x28, 0xe3, 0x16, 0xcd, 0x11, 0x48, 0x19, 0xc,
+ 0x3d, 0x1a, 0x94, 0x71, 0xc, 0x63, 0x50, 0x32, 0x30, 0x8c,
+ 0x80, 0xb6, 0xb1, 0xfb, 0xb2, 0xfb, 0xbc, 0xdf, 0x24, 0xfa,
+ 0xc8, 0x7a, 0x70, 0xfe, 0x4a, 0x76, 0xc2, 0x98, 0x62, 00,
+ 0x33, 0x7b, 0xc1, 0x48, 0xab, 0xac, 0xf2, 0xc6, 0x3a, 0x38,
+ 0xa6, 0x44, 0x5c, 0xa7, 0x95, 0x25, 0x80, 0x50, 0x6, 0xc0,
+ 0x7b, 0xa2, 0x68, 0x3a, 0xb2, 0xb0, 0x42, 0x7b, 0x3b, 0xf,
+ 0xee, 0x17, 0xbe, 0xba, 0xcf, 0x9f, 0x85, 0xd6, 0xcc, 0x9c,
+ 0xb9, 0x8a, 0x3c, 0xb9, 0x6b, 00, 0xb0, 0x38, 0x41, 0xbf,
+ 0xfd, 0xf6, 0x50, 0x13, 0x56, 0x37, 0x5f, 0x2f, 0x5, 0x4,
+ 0xd2, 0x85, 0xe8, 0x80, 0xc4, 0x28, 0x9a, 0x83, 0x59, 0xee,
+ 0xfb, 0x1e, 0x69, 0x14, 0xf, 0x7f, 0xc1, 0x6f, 0xce, 0xb8,
+ 0x78, 0x61, 0xae, 0x38, 0xe2, 0x5c, 0xf6, 0x2b, 0x5e, 0x13,
+ 0x43, 0xaa, 0xbb, 0xdc, 0x63, 0x5e, 0xd8, 0xb1, 0x22, 0x4c,
+ 0xe6, 0x42, 0xdf, 0x44, 0xec, 0x6a, 0xb7, 0x77, 0x3e, 0x68,
+ 0x26, 0x84, 0x99, 0xc8, 0xc2, 0xce, 0x85, 0x4f, 0xa8, 0xf7,
+ 0xe8, 0x79, 0xde, 0xd, 0xdc, 0x3f, 0x1a, 0x6e, 0x87, 0x27,
+ 0x36, 0xce, 0x56, 0xe4, 0x31, 0x9, 0x5a, 0xd7, 0x2, 0x2c,
+ 0x56, 0xe0, 0x9c, 0x8f, 0x2b, 0xd2, 0x7, 0xe2, 0x67, 0x26,
+ 0xd2, 0xbe, 0x8e, 0x26, 0xe4, 0x72, 0xda, 0x5e, 0x79, 0x55,
+ 0x8e, 0x3a, 0x2c, 0x69, 0xde, 0x90, 0x33, 0x7e, 0xe3, 0x6c,
+ 0x66, 0x66, 0x5d, 0x39, 0x36, 0x93, 0xe, 0xfc, 0xb3, 0x44,
+ 0xfa, 0x52, 0x8f, 0x9e, 0x65, 0xf2, 0xd0, 0x69, 0x89, 0xb5,
+ 0xc2, 0x7b, 0x4a, 0x8a, 0xc7, 0xea, 0x14, 0x21, 0xb, 0x1b,
+ 0x5d, 0x72, 0x18, 0x80, 0xbe, 0x3e, 0xf8, 0x6d, 0xa4, 0x55,
+ 0x48, 0x9b, 0x9e, 0x50, 0x73, 0x7, 0x2c, 0x9b, 0x66, 0x1d,
+ 0xd5, 0xad, 0x2c, 0x50, 0xaa, 0xb1, 0x56, 0x32, 0x6f, 0xf3,
+ 0x74, 0x55, 0x81, 0xec, 0xb0, 0xd7, 0x51, 0x69, 0xf9, 0x8e,
+ 0x1e, 0x49, 0xac, 0x1b, 0x68, 0x91, 0xb4, 0x3c, 0xf9, 0x14,
+ 0x6c, 0xd9, 0x24, 0x3b, 0x21, 0x40, 0x56, 0x50, 0x11, 0xdf,
+ 0x9a, 0x83, 0xa5, 0x13, 0x1e, 0x27, 0x66, 0xf3, 0x92, 0xbd,
+ 0x18, 0x4d, 0xb5, 0xa9, 0x67, 0x56, 0xe0, 0xc0, 0x6e, 0xdc,
+ 0xb8, 0x1, 0x95, 0x15, 0x80, 0xcc, 0x5d, 0x98, 0xa6, 0x6a,
+ 0x25, 0xe9, 0x3f, 0x83, 0xb6, 0xb9, 0x9d, 0xe2, 0xcf, 0x66,
+ 0x6d, 0x35, 0x21, 0xa9, 0x84, 0xdf, 0xfa, 0xb3, 0x9f, 0xe6,
+ 0x13, 0x54, 0xa7, 0x66, 0x1a, 0xee, 0xa3, 0xa9, 0x94, 0x1c,
+ 0xd9, 0xe5, 0xcc, 0x3c, 0x34, 0x35, 0xd8, 0x29, 0x1d, 0xb1,
+ 0x32, 0x1a, 0xa1, 0x8, 0x1b, 0xb2, 0x7f, 0x67, 0xb4, 0x37,
+ 0xcb, 0x82, 0x3f, 0x40, 0x5d, 0xa4, 0x4e, 0x2a, 0x9a, 0x48,
+ 0xf6, 0x97, 0x5b, 0x46, 0x37, 0xda, 0x8b, 0x99, 0x55, 0xa,
+ 0xeb, 0x3a, 0x1f, 0x7b, 0x92, 0x76, 0x92, 0xe1, 0xaf, 0xd,
+ 0x5a, 0xa4, 0x22, 0xea, 0xd0, 0xa9, 0x5d, 0xd0, 0x4b, 0x85,
+ 0xcc, 0xdc, 0xf7, 0xf, 0xc4, 0xa5, 0xa5, 0x60, 0x47, 0xbe,
+ 0x33, 0x68, 0xa7, 0xd0, 0x80, 0x13, 0xeb, 0xf6, 0x26, 0xbc,
+ 0x13, 0xb, 0xc4, 0x20, 0xea, 0x1b, 0x80, 0x1, 0x87, 0xb2,
+ 0x8a, 0xa6, 0xb7, 0x95, 0xe7, 0x8, 0x50, 0x9d, 0xf7, 0x90,
+ 0xd5, 0x2b, 0x7f, 0x2e, 0x68, 0x28, 0x66, 0x86, 0x96, 0x50,
+ 0x45, 0x27, 0xda, 0x38, 0x2b, 0x35, 0x14, 0x40, 0xb8, 0x8c,
+ 0xd9, 0xa2, 0x69, 0x84, 0x1c, 0xc5, 0xd, 0x48, 0x82, 0x97,
+ 0x94, 0x3d, 0x6, 0x7f, 0x7a, 0xb8, 0x48, 0x43, 0x48, 0x43,
+ 0x25, 0x2c, 0x13, 0x12, 0x15, 0xe5, 0xbf, 0xbc, 0x84, 0x13,
+ 0x6d, 0xd9, 0x70, 0x9d, 0x4e, 0x6d, 0x27, 0xaa, 0xc9, 0x99,
+ 0x2d, 0x84, 0x1c, 0x91, 0xc, 0xfa, 0x2c, 0xef, 0xb9, 0x4,
+ 0xb9, 0x32, 0xaf, 0xa2, 0x39, 0xf8, 0xca, 0x73, 0xf9, 0xab,
+ 0x22, 0xfd, 0xc9, 0x2b, 0x76, 0xe3, 0x11, 0xc4, 0xe4, 0xc4,
+ 0xe9, 0x17, 0x1a, 0xd7, 0x2f, 0xce, 0xa, 0x74, 0x76, 0x48,
+ 0xd7, 0x52, 0x84, 0xa, 0xc9, 0x1f, 0x66, 0xb1, 0x7e, 0x3c,
+ 0x7a, 0x4f, 0xf8, 0x5c, 0x2d, 0xcb, 0x33, 0x78, 0x6a, 0xcf,
+ 0xee, 0x3a, 0x87, 0x93, 0x2a, 0x89, 0x80, 0xd8, 0xb2, 0x6e,
+ 0xd2, 0x2, 0xad, 0xfb, 0xd6, 0x71, 0x37, 0x18, 0x4, 0x7b,
+ 0x92, 0x28, 0x25, 0x87, 0xa5, 0x7a, 0xb9, 0xd1, 0xfe, 0x3b,
+ 0x97, 0x51, 0x9d, 0x61, 0xde, 0x41, 0x29, 0x40, 0x1, 0xbf,
+ 0xbd, 0x70, 0x62, 0x9e, 0xc, 0xb4, 0x1f, 0xb7, 0x74, 0x9,
+ 0x13, 0x4d, 0x2a, 0xd6, 0xda, 0x22, 0xdc, 0x61, 0x60, 0x5e,
+ 0x97, 0x6c, 0x9e, 0x41, 0x8d, 0x1f, 0x50, 0xbb, 0x71, 0xeb,
+ 0x1b, 0x55, 0x5d, 0xf0, 0x3e, 0xd8, 0x82, 0xe8, 0xf7, 0xcf,
+ 0x3, 0xb0, 0x23, 0x41, 0x91, 0xe1, 0xe3, 0x33, 0xe2, 0xe1,
+ 0x41, 0x77, 0x2b, 0x66, 0x50, 0x18, 0x77, 0xe9, 0x5c, 0x5e,
+ 0xf0, 0x4, 0x12, 0x25, 0x96, 0x10, 0xf3, 0x48, 0x46, 0xe5,
+ 0x38, 0x3, 0x4e, 0xe1, 0x93, 0xcd, 0xab, 0x26, 0x55, 0x56,
+ 0x9, 0x8c, 0x39, 0x49, 0xca, 0xe8, 0x93, 0x4, 0x4d, 0xd8,
+ 0xb, 0xbb, 0x3a, 0x87, 0xc6, 0xbf, 0x56, 0x1e, 0x7, 0x80,
+ 0x39, 0xa0, 0xc8, 0x81, 0x8d, 0x19, 0x2f, 0xc6, 0x7c, 0xbd,
+ 0x5e, 0xc0, 0x28, 0x16, 0x17, 0x50, 0x7a, 0xdc, 0x2, 0xd8,
+ 0xcd, 0xf3, 0x92, 0x17, 0x96, 0x4f, 0x89, 0xc8, 0xc, 0x56,
+ 0x33, 0xcb, 0x63, 0x57, 0x11, 0xc5, 0xa5, 0x8, 0x7b, 0xb3,
+ 0xf4, 0x43, 0x8f, 0x8e, 0x8c, 0x98, 0x36, 0xe8, 0x6, 0xdd,
+ 0x7d, 0x9a, 0x94, 0x15, 0xb3, 0x3c, 0x23, 0x43, 0x4b, 0x3e,
+ 0x94, 0x2e, 0x6c, 0xe6, 0xa1, 0xd, 0x1a, 0x25, 0x31, 0x85,
+ 0x15, 0x14, 0x17, 0x98, 0x6f, 0x68, 0xec, 0x5c, 0xb0, 0x91,
+ 0x70, 0x81, 0x32, 0xcf, 0x1e, 0x6b, 0xf7, 0xcd, 0x7, 0xeb,
+ 0x67, 0x1, 0xf0, 0x2e, 0x16, 0x23, 0xa0, 0xc0, 0xac, 0xd8,
+ 0x5d, 0x9c, 0xad, 0x7b, 0x8d, 0xcc, 0x89, 0xcd, 0x3c, 0x58,
+ 0x87, 0x55, 0x27, 0xb7, 0x90, 0x6a, 0xb6, 0xf1, 0xd, 0x15,
+ 0x65, 0x4, 0x55, 0x45, 0x6e, 0xd9, 0x5b, 0x27, 0x60, 0x1f,
+ 0x36, 0x25, 0x7c, 0xb3, 0x42, 0x28, 0x91, 00, 0xef, 0xff,
+ 0xce, 0x27, 0x42, 0xe0, 0x58, 0x9d, 0xa5, 0x4f, 0x28, 0x23,
+ 0xde, 0x5f, 0x24, 0x6c, 0x91, 0xe9, 0x2c, 0x35, 0xb6, 0xc8,
+ 0xd7, 0xc, 0xee, 0x50, 0x3c, 0x77, 0x72, 0xcb, 0x76, 0x42,
+ 0x3, 0x34, 0xba, 0xb4, 0xf2, 0x29, 0xf1, 0x51, 0x44, 0x43,
+ 0x8b, 0xc8, 0x8d, 0x69, 0x11, 0x32, 0xcd, 0x17, 0xef, 0xfa,
+ 0xcf, 0xf4, 0x28, 0x61, 0x37, 0x1e, 0xcc, 0xa1, 0x37, 0x6e,
+ 0x9d, 0xa4, 0x40, 0x51, 0x28, 0x31, 0x28, 0xa8, 0x34, 0x66,
+ 0x1f, 0x48, 0x18, 0xaf, 0x49, 0x63, 0xb8, 0x92, 0x6f, 0xac,
+ 0x44, 0xdd, 0x56, 0xad, 0xcc, 0xc3, 0x6e, 0x41, 0xc3, 0x43,
+ 0x45, 0xb0, 0xec, 0xfe, 0xd9, 0x32, 0x9a, 0xb8, 0x7c, 0x2d,
+ 0xee, 0x25, 0x43, 0xe8, 0x31, 0x28, 0x83, 0x67, 0xd, 0xe0,
+ 0xb6, 0x56, 0x5f, 0x95, 0xb7, 0xd5, 0x12, 0xec, 0x56, 0x7f,
+ 0xcc, 0x5b, 0x84, 0xa6, 0x30, 0x9f, 0x5c, 0x3, 0xd6, 0x7d,
+ 0xe5, 0x5b, 0x8c, 0x46, 0xa2, 0xc0, 0xdc, 0x75, 0xf9, 0x19,
+ 0x7a, 0xc, 0xca, 0xdb, 0x9e, 0xc7, 0xa1, 0xc9, 0xa1, 0x71,
+ 0x65, 0xd3, 0xf6, 0x38, 0xb6, 0xdc, 0xf3, 0x10, 0x90, 0x5b,
+ 0x16, 0x5b, 0x23, 0x33, 0x42, 0x85, 0x89, 0xc0, 0x6e, 0xda,
+ 0xe4, 0xac, 0xe9, 0x26, 0x85, 0x9d, 0x9a, 0xe5, 0xc1, 0x30,
+ 0x95, 0x55, 0x3c, 0xc9, 0xd9, 0xe1, 0x6f, 0xfd, 0xd, 0x9a,
+ 0x8c, 0x51, 0xe3, 0x9b, 0x6c, 0x10, 0xcc, 0x82, 0x5b, 0x37,
+ 0x3a, 0x82, 0xc7, 0xe4, 0xcf, 0x66, 0xea, 0xe, 0x91, 0x4b,
+ 0xbe, 0x95, 0x7, 0xf2, 0x40, 0x10, 0x22, 0x43, 0x5e, 0x82,
+ 0xc2, 0xe4, 0x97, 0x2d, 0xdf, 0x6, 0xce, 0xcb, 0x30, 0xec,
+ 0x24, 0x93, 0x97, 0x6b, 0xd3, 0x24, 0xec, 0x1c, 0x33, 0x7,
+ 0xda, 0x4b, 0xb, 0xdc, 0x23, 0x60, 0xe4, 0xaf, 0x8d, 0xff,
+ 0x81, 0x27, 0x8a, 0x94, 0x96, 0x4d, 0xa1, 0x38, 0x93, 0x39,
+ 0x67, 0x61, 0x73, 0x3b, 0x27, 0x9a, 0x72, 0xba, 0x60, 0xf1,
+ 0xc8, 0x98, 0x68, 0xe5, 0xcb, 0x70, 0x61, 0xc6, 0xd2, 0x22,
+ 0xe5, 0x22, 0xe, 0x10, 0xc2, 0x30, 0x8e, 0xb8, 0x4f, 0xc9,
+ 0x86, 0x8e, 0x17, 0x72, 0xff, 0x9c, 0xfd, 0xc, 0xfc, 0xf8,
+ 0xe8, 0xf0, 0x11, 0x17, 0x70, 0xbf, 0x69, 0x87, 0xf3, 0x60,
+ 0x48, 0xc, 0xcd, 0xa6, 0xb0, 0x14, 0x17, 0x62, 0x4d, 0x53,
+ 0xaf, 0x6a, 0x89, 0x13, 0x89, 0xc4, 0x7d, 0x73, 0x52, 0x16,
+ 0x6c, 0x86, 0x9, 0x23, 0x5b, 0x59, 0xc0, 0x5a, 0x52, 0xb0,
+ 0x1, 0x1f, 0xbc, 0x77, 0x65, 0xd6, 0x1, 0x25, 0x6, 0xf5,
+ 0xf4, 0x74, 0xe1, 0xe0, 0x8d, 0x85, 0xc6, 0x3f, 0x47, 0xcc,
+ 0x26, 0xc0, 0xe6, 0x66, 0xa1, 0xc9, 0x46, 0xd1, 0x25, 0xd1,
+ 0x45, 0x12, 0x6a, 0xfc, 0xf3, 0x24, 0xd, 0x85, 0x3f, 00,
+ 0x23, 0xd5, 0x6e, 0xb1, 0x16, 0x63, 0x11, 0x1c, 0x30, 0x24,
+ 0xd3, 00, 0x14, 0xcd, 0xb3, 0xac, 0x4, 0xbd, 0x10, 0xfd,
+ 0x1b, 0x15, 0x93, 0x82, 0x5d, 0xb1, 0xc, 0x49, 0xf1, 0xfa,
+ 0x67, 0x9f, 0x24, 0xec, 0x1e, 0x6e, 0x10, 0x6c, 0xb5, 0x5a,
+ 0x34, 0xc1, 0xe0, 0x83, 0x1c, 0x83, 0xcd, 0xc3, 0x2c, 0xb0,
+ 0x16, 0xd1, 0x65, 0xf0, 0x41, 0x11, 0x36, 0x6a, 0xdf, 0x76,
+ 0x5f, 0x70, 0x25, 0x7a, 0xbb, 0x32, 0x54, 0x82, 0x60, 0xc5,
+ 0x22, 0x91, 0x67, 0x75, 0xf7, 0x63, 0xb, 0x16, 0xb3, 0xba,
+ 0x5f, 0xa5, 0xc8, 0xe0, 0x68, 0x46, 0x53, 0x69, 0xab, 0x54,
+ 0xea, 0x8a, 0x94, 0x47, 0xeb, 0x30, 0x68, 0x73, 0x4a, 0xe2,
+ 0x2f, 0xf7, 0x24, 0x4a, 0xca, 0x8b, 0xfd, 0xc6, 0xc9, 0x9f,
+ 0xa8, 0x47, 0x66, 0x96, 0xa2, 0xa1, 0x9, 0x4e, 0x7f, 0x3f,
+ 0x8e, 0x43, 0x47, 0x1a, 0x5f, 0xaf, 0x98, 0xab, 0xf1, 0x75,
+ 0xa0, 0x50, 0x35, 0x15, 0xc8, 0xce, 0x44, 0x53, 0x69, 0x32,
+ 0x55, 0x46, 0x9d, 0x7a, 0xa2, 0xe, 0xfc, 0xb0, 0xa7, 0xad,
+ 0x1e, 0xc6, 0xda, 0x63, 0x67, 0xfa, 0xb, 0x42, 0x59, 0xb1,
+ 0x8, 0xdb, 0x49, 0x45, 0xc0, 0xdf, 0x1f, 0x45, 0xe7, 0x50,
+ 0xb3, 0x65, 0xa0, 0x5a, 0xb6, 0xf7, 0xe3, 0x4, 0xd6, 0xb0,
+ 0xc6, 0x5, 0x6a, 0x55, 0xb9, 0x3a, 0xd4, 0xae, 0x92, 0x85,
+ 0xbd, 0xb8, 0x26, 0x24, 0x92, 0x7d, 0xea, 0xe5, 0x94, 0x2,
+ 0xb5, 0xa2, 0x3e, 0xe2, 0x8c, 0xc8, 0xdd, 0x36, 0xe8, 0x16,
+ 0x96, 0x5d, 0x82, 0x5, 0xd4, 0x1a, 0x23, 0x8b, 0x51, 0x69,
+ 0x4f, 0xe0, 0x8b, 0x99, 0x8b, 0x3d, 0xbe, 0x9b, 0xcd, 0x41,
+ 0x88, 0xb1, 0xdd, 0xc3, 0x4c, 0x44, 0x79, 0xcc, 0x82, 0xdc,
+ 0x8d, 0x47, 0x81, 0xfb, 0x4e, 0xc7, 0x3, 0xcd, 0x3b, 0xa0,
+ 0x72, 0xb1, 0x5, 0x1, 0xfd, 0x2a, 0xa, 0x8f, 0xf9, 0xf3,
+ 0x35, 0x47, 0x7c, 0x8a, 0xa5, 0x47, 0x26, 0x2b, 0xb3, 0xd0,
+ 0xf3, 0xad, 0xab, 0x72, 0x5b, 0x99, 0xa3, 0x7, 0xd7, 0x10,
+ 0xce, 0x63, 0x58, 0x8, 0x5a, 0x6e, 0x9, 0xd1, 0xcd, 0x45,
+ 0xc0, 0xbb, 0x55, 0x77, 0xc8, 0x20, 0xe0, 0x76, 0x41, 0xad,
+ 0xee, 0x15, 0x4b, 0xb6, 0x10, 0xdb, 0x73, 0xc4, 0x5f, 0x6a,
+ 0x2e, 0x5c, 0x18, 0x11, 0x6c, 0x6, 0xf7, 0xfa, 0xb9, 0x8b,
+ 0x32, 0x3b, 0x21, 0xd3, 0xeb, 0x94, 0xff, 0x17, 0xf0, 0xd5,
+ 0xd5, 0xc6, 0x9c, 0xd4, 0xe0, 0xf0, 0x8, 0x31, 0xbe, 0x1,
+ 0x83, 0x61, 0x1c, 0xb6, 0x2c, 0x4, 0x4c, 0xf2, 0x75, 0xc,
+ 0x8a, 0x5, 0x5, 0x37, 0xc8, 0x80, 0xb, 0xed, 0x9a, 0xc3,
+ 0x6, 0x19, 0x37, 0x90, 0x7e, 0xdc, 0x4a, 0x32, 0x82, 0xd4,
+ 0x29, 0x92, 0xd9, 0x3e, 0xdc, 0x71, 0x26, 0xcd, 0x30, 0x47,
+ 0x1e, 0xde, 0x82, 0x18, 0x7d, 0x3, 0x4b, 0x8c, 0xe6, 0xc,
+ 0x56, 0x57, 0xc3, 0x2d, 0x49, 0x70, 0x9f, 0x17, 0x18, 0xee,
+ 0x56, 0x98, 0x8b, 0x59, 0xf2, 0x98, 0x2e, 0x59, 0xd8, 0x18,
+ 0xeb, 0xf5, 0x31, 0xf0, 0xe9, 0x91, 0x43, 0xc4, 0x8b, 0x4,
+ 0x32, 0xca, 0x91, 0xc4, 0xfd, 0x2a, 0xd2, 0xa, 0x9a, 0x2a,
+ 0x6c, 0x41, 0x8b, 0xcc, 0xd, 0xe7, 0x89, 0x8b, 0x1c, 0x4c,
+ 0xbe, 0xcf, 0xd1, 0xf0, 0x66, 0x20, 0x67, 0x5, 0x92, 0xf1,
+ 0x8e, 0x41, 0x1e, 0xb3, 0x51, 0x7f, 0x5e, 0x10, 0x4, 0xb8,
+ 0x8a, 0x3d, 0x1f, 0x91, 0xab, 0x51, 0xc0, 0xa2, 0x6e, 0x1a,
+ 0x7f, 0x53, 0x63, 0x29, 0x4, 0x6b, 0xa1, 0xa6, 0x78, 0x4c,
+ 0x9e, 0x8e, 0xc7, 0xc8, 0x64, 0x29, 0x86, 0x13, 0x65, 0x1f,
+ 0xd4, 0xe8, 0xe6, 0xb7, 0x3a, 0x47, 0xba, 0xca, 0xde, 0xf1,
+ 0x5c, 0x5e, 0xf3, 0x63, 0x65, 0x2c, 0x15, 0x65, 0x35, 0xba,
+ 0xb4, 0xde, 0xe6, 0xd0, 0xef, 0xe8, 0xe5, 0x82, 0x33, 0xfe,
+ 0xdd, 0xe6, 0xd, 0xf9, 0x7e, 0xb3, 0x78, 0x61, 0x96, 0xe3,
+ 0xa6, 0xa3, 00, 0x59, 0xd8, 0xae, 0xa2, 0xbe, 0x21, 0x68,
+ 0xff, 0xf, 0xc0, 0xd, 0x6, 0x12, 0x9f, 0x6f, 0x55, 0x17,
+ 0x36, 0x35, 0x1c, 0xb9, 0xd5, 0x81, 0x6, 0xfd, 0xc2, 0xb2,
+ 0xb9, 0x51, 0x58, 0xa8, 0x9d, 00, 0xb3, 0x39, 0x1f, 0x51,
+ 0x6, 0xfe, 0xc, 0xb5, 0xcc, 0x62, 0xa5, 0xf1, 0x21, 0x9,
+ 0x2b, 0x77, 0x99, 0xf9, 0xfe, 0x6e, 0x3f, 0x75, 0xc9, 0x60,
+ 0x53, 0x90, 0x3b, 0xe5, 0x7b, 0xf5, 0xab, 0x28, 0xc0, 0x66,
+ 0x47, 0x1b, 0x54, 0x3d, 0x34, 0xf3, 0x36, 0x6c, 0x3f, 0x1f,
+ 0xe6, 0xe2, 0x2a, 0x59, 0xf1, 0x2c, 0x21, 0xf8, 0xa7, 0xba,
+ 0xdf, 0x58, 0x7, 0xeb, 0xd0, 0x66, 0x69, 0xb1, 0xeb, 0x9e,
+ 0x7d, 0x20, 0xd6, 0x78, 0xd9, 0xde, 0xc, 0x14, 0x26, 0x7b,
+ 0x8b, 0x8e, 0xd0, 0x25, 0xb3, 0x2f, 0x95, 0xf4, 0xb8, 0x1f,
+ 0x95, 0xb0, 0x98, 0x74, 0xdc, 0x95, 0x87, 0x11, 0x56, 0x8,
+ 0xb0, 0x9c, 0x38, 0x27, 0xdf, 0x68, 0x24, 0xc0, 0x84, 0xa7,
+ 0x3f, 0x2d, 0xef, 0x94, 0x36, 0x86, 0x16, 0x8, 0x64, 0xc2,
+ 0x8b, 0xa4, 0xbd, 0x36, 0xa, 0x28, 0xc2, 0xb2, 0x26, 0xdc,
+ 0xd, 0xe, 0x17, 0x77, 0xcb, 0x98, 0x50, 0xef, 0x4a, 0xe6,
+ 0xce, 0x2f, 0x6b, 0x41, 0x53, 0xe3, 0xbb, 0x3c, 0x3c, 0x44,
+ 0xa0, 0xd6, 0x73, 0x28, 0x5e, 0x10, 0xa3, 0xa4, 0xa4, 0xe9,
+ 0x62, 0xb, 0x40, 0xb6, 0x56, 0x31, 0x20, 0x3c, 0x28, 0x39,
+ 0x89, 0xa0, 0x84, 0x4b, 0x8a, 0xec, 0x57, 0xa0, 0xd1, 0xc,
+ 0xb5, 0xa, 0xba, 0xeb, 0x28, 0x3c, 0x8, 0xa4, 0xae, 0xa6,
+ 0x2e, 0x99, 0x4a, 0x2f, 0x31, 0xe5, 0xbf, 0x2c, 0xa5, 0xfa,
+ 0xff, 0xd, 0x47, 0x6f, 0x42, 0x2, 0x70, 0xd7, 0xcb, 0x76,
+ 0xb5, 0x4d, 0xcb, 0x12, 0xac, 0x29, 0x17, 0xea, 0xd1, 0xc8,
+ 0x56, 0x43, 0x7b, 0xb0, 0x71, 0x2f, 0x5f, 0x2a, 0xc5, 0x1c,
+ 0x4b, 0x7f, 0x91, 0x9b, 0x9e, 0xd6, 0xeb, 0x9e, 0x75, 0x26,
+ 0x10, 0x36, 0x3b, 0x71, 0x11, 0x5d, 0x1, 0xb8, 0xb8, 0xd6,
+ 0xce, 0x6e, 0xdf, 0xf, 0x7, 0xc7, 0x26, 0x52, 0xe2, 0xf4,
+ 0xc7, 0x8e, 0xa, 0xa, 0xd, 0x6f, 0xd9, 0xab, 0xa5, 0x9f,
+ 0x3, 0xf0, 0xfc, 0x2b, 0x21, 0x21, 0xe4, 0x4d, 0x14, 0xac,
+ 0x8a, 0xde, 0x51, 0x1f, 0x51, 0xba, 0x22, 0x53, 0x31, 0x31,
+ 0xaa, 0xfe, 0x33, 0x2, 0xcb, 0xea, 0x5a, 0x83, 0xc0, 0x85,
+ 0x1d, 0xbe, 0xb, 0x23, 0x89, 0x43, 0xf7, 0xff, 0x1f, 0xef,
+ 0x40, 0x7c, 0x19, 0x90, 0x2d, 0xa8, 0xbe, 0xbd, 0xe9, 0xe9,
+ 0x2f, 0x5e, 0xd0, 0x55, 0x51, 0x20, 0x40, 0x56, 0x50, 0x7d,
+ 0xa7, 0x9c, 0xe0, 0x96, 0xd9, 0xef, 0x86, 0xa0, 0x40, 0xe3,
+ 0xab, 0xfe, 0xc6, 0x56, 0xf5, 0x97, 0xbc, 0x18, 0xf7, 0xe5,
+ 0x81, 0x77, 0x63, 0x76, 0x3a, 0x54, 0x50, 0x1d, 0x59, 0x2f,
+ 0xf0, 0x70, 0xb3, 0xdc, 0xf0, 0x5d, 0xf8, 0x3e, 0x8f, 0x87,
+ 0x69, 0xd9, 0x70, 0xea, 0x71, 0xdf, 0xd2, 0xea, 0x5, 0x4d,
+ 0x12, 0x82, 0x93, 0x70, 0x8b, 0x1e, 0x17, 0x76, 0xbe, 0xe0,
+ 0x68, 0x8d, 0xc0, 0xad, 0xce, 0xd0, 0x33, 0x76, 0xbd, 0x79,
+ 0xd4, 0x77, 0x21, 0xa6, 0x16, 0x46, 0x8e, 0xbb, 0x7e, 0x8d,
+ 0xba, 0xad, 0x1, 0x80, 0xf9, 0x7b, 0x7, 0xb1, 0x34, 0x2e,
+ 0x6c, 0xe2, 0x5a, 0x87, 0xb0, 0xe8, 0x2f, 0x6d, 0xe9, 0x10,
+ 0x5e, 0x14, 0xf0, 0x30, 0x7a, 0x5b, 0x8, 0x93, 0x5f, 0xd3,
+ 0xf8, 0xe, 0xc8, 0x64, 0x1, 0x95, 0x40, 0x40, 0x36, 0x66,
+ 0x9f, 0xc4, 0x97, 0x3, 0xa7, 0x18, 0x32, 0x61, 0xf3, 0x4a,
+ 0xa2, 0x1f, 0x95, 0x6b, 0x30, 0x9, 0x91, 0x6b, 0xe3, 0x57,
+ 0x8f, 0x2c, 0x4a, 0x8c, 0xa7, 0x2c, 0x93, 0x5, 0x3c, 0x8a,
+ 0x76, 0x2c, 0x28, 0xb8, 0xd5, 0x59, 0x53, 0xd5, 0xce, 0x81,
+ 0xb0, 0xb9, 0xe2, 0x4a, 0x9e, 0x44, 0x56, 0x1c, 0xfc, 0x98,
+ 0x81, 0x6f, 0xfc, 0x9d, 0xfc, 0xac, 0xcc, 0xc5, 0xd3, 0x84,
+ 0x4e, 0x9b, 0x98, 0xb8, 0xfa, 0xbb, 0xd9, 0x1c, 0x8, 0xdd,
+ 0xfc, 0x8a, 0xec, 0x42, 0xc4, 0x1, 0xe5, 0x3e, 0xb7, 0x80,
+ 0xe2, 0xeb, 0xd7, 0xc0, 0x1, 0x13, 0x1, 0xc6, 0x4c, 0x6a,
+ 0x4b, 0x83, 0x81, 0x9, 0x59, 0xd8, 0x84, 0x77, 0xdc, 0x20,
+ 0x4, 0x5b, 0xfd, 0x9b, 0x12, 0x50, 0x26, 0x1a, 0x4d, 0x6f,
+ 0xcb, 0x6, 0x1c, 0x5f, 0x2d, 0xaf, 0x67, 0xa, 0xfe, 0x33,
+ 0x12, 0x81, 0x50, 0xb1, 0x51, 0x83, 0xc4, 0xc9, 0xf4, 0xfd,
+ 0xf, 0x26, 0x50, 0x51, 0x40, 0x20, 0x9, 0x2b, 0xbe, 0x6b,
+ 0xf0, 0xd9, 0xc3, 0xbf, 0x18, 0x14, 0x8, 0xf4, 0x9c, 0x94,
+ 0xde, 0xd8, 0x30, 0x14, 0x9, 0xbb, 0xc7, 0x46, 0xde, 0xe,
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+
+static const char data_cgi_files[] = {
+ /* /cgi/files */
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+
+static const char data_cgi_stats[] = {
+ /* /cgi/stats */
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+
+static const char data_cgi_tcp[] = {
+ /* /cgi/tcp */
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+
+static const char data_cgi_rtos[] = {
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+ 0x73, 0x74, 0x61, 0x74, 0x69, 0x73, 0x74, 0x69, 0x63, 0x73,
+ 0x20, 0x66, 0x6f, 0x72, 0x20, 0x61, 0x6c, 0x6c, 0x20, 0x74,
+ 0x68, 0x65, 0x20, 0x74, 0x61, 0x73, 0x6b, 0x73, 0x20, 0x69,
+ 0x6e, 0x20, 0x74, 0x68, 0x65, 0x20, 0x64, 0x65, 0x6d, 0x6f,
+ 0x20, 0x61, 0x70, 0x70, 0x6c, 0x69, 0x63, 0x61, 0x69, 0x74,
+ 0x6f, 0x6e, 0x2e, 0x3c, 0x70, 0x3e, 0x3c, 0x70, 0x72, 0x65,
+ 0x3e, 0x54, 0x61, 0x73, 0x6b, 0x20, 0x20, 0x20, 0x20, 0x20,
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x53, 0x74, 0x61, 0x74, 0x65,
+ 0x20, 0x20, 0x50, 0x72, 0x69, 0x6f, 0x72, 0x69, 0x74, 0x79,
+ 0x20, 0x20, 0x53, 0x74, 0x61, 0x63, 0x6b, 0x9, 0x23, 0x3c,
+ 0x62, 0x72, 0x3e, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a,
+ 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a,
+ 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a,
+ 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a,
+ 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a,
+ 0x2a, 0x3c, 0x62, 0x72, 0x3e, 0xa, 0x63, 0x20, 0x64, 0xa,
+ 0x74, 0x20, 0x3c, 0x2f, 0x70, 0x72, 0x65, 0x3e, 0x3c, 0x2f,
+ 0x66, 0x6f, 0x6e, 0x74, 0x3e, 0x3c, 0x2f, 0x62, 0x6f, 0x64,
+ 0x79, 0x3e, 0x3c, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0xa,
+ 0x2e, 0xa, 0xa, 0xa, };
+
+static const char data_index_html[] = {
+ /* /index.html */
+ 0x2f, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0,
+ 0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x32,
+ 0x30, 0x30, 0x20, 0x4f, 0x4b, 0xd, 0xa, 0x53, 0x65, 0x72,
+ 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x30,
+ 0x2e, 0x39, 0x20, 0x28, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f,
+ 0x2f, 0x64, 0x75, 0x6e, 0x6b, 0x65, 0x6c, 0x73, 0x2e, 0x63,
+ 0x6f, 0x6d, 0x2f, 0x61, 0x64, 0x61, 0x6d, 0x2f, 0x75, 0x69,
+ 0x70, 0x2f, 0x29, 0xd, 0xa, 0x43, 0x6f, 0x6e, 0x74, 0x65,
+ 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74,
+ 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0xd, 0xa,
+ 0xd, 0xa, 0x3c, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0xd, 0xa,
+ 0x3c, 0x68, 0x65, 0x61, 0x64, 0x3e, 0xd, 0xa, 0x3c, 0x2f,
+ 0x68, 0x65, 0x61, 0x64, 0x3e, 0xd, 0xa, 0xd, 0xa, 0x3c,
+ 0x66, 0x72, 0x61, 0x6d, 0x65, 0x73, 0x65, 0x74, 0x20, 0x63,
+ 0x6f, 0x6c, 0x73, 0x3d, 0x22, 0x2a, 0x22, 0x20, 0x72, 0x6f,
+ 0x77, 0x73, 0x3d, 0x22, 0x31, 0x32, 0x30, 0x2c, 0x2a, 0x22,
+ 0x20, 0x66, 0x72, 0x61, 0x6d, 0x65, 0x62, 0x6f, 0x72, 0x64,
+ 0x65, 0x72, 0x3d, 0x22, 0x6e, 0x6f, 0x22, 0x3e, 0x20, 0xd,
+ 0xa, 0x20, 0x20, 0x3c, 0x66, 0x72, 0x61, 0x6d, 0x65, 0x20,
+ 0x73, 0x72, 0x63, 0x3d, 0x22, 0x63, 0x6f, 0x6e, 0x74, 0x72,
+ 0x6f, 0x6c, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, 0xd,
+ 0xa, 0x20, 0x20, 0x3c, 0x66, 0x72, 0x61, 0x6d, 0x65, 0x20,
+ 0x73, 0x72, 0x63, 0x3d, 0x22, 0x2f, 0x63, 0x67, 0x69, 0x2f,
+ 0x72, 0x74, 0x6f, 0x73, 0x22, 0x20, 0x6e, 0x61, 0x6d, 0x65,
+ 0x3d, 0x22, 0x6d, 0x61, 0x69, 0x6e, 0x22, 0x3e, 0xd, 0xa,
+ 0x3c, 0x2f, 0x66, 0x72, 0x61, 0x6d, 0x65, 0x73, 0x65, 0x74,
+ 0x3e, 0xd, 0xa, 0xd, 0xa, 0x3c, 0x6e, 0x6f, 0x66, 0x72,
+ 0x61, 0x6d, 0x65, 0x73, 0x3e, 0xd, 0xa, 0x3c, 0x62, 0x6f,
+ 0x64, 0x79, 0x3e, 0xd, 0xa, 0x59, 0x6f, 0x75, 0x72, 0x20,
+ 0x62, 0x72, 0x6f, 0x77, 0x73, 0x65, 0x72, 0x20, 0x6d, 0x75,
+ 0x73, 0x74, 0x20, 0x73, 0x75, 0x70, 0x70, 0x6f, 0x72, 0x74,
+ 0x20, 0x66, 0x72, 0x61, 0x6d, 0x65, 0x73, 0xd, 0xa, 0x3c,
+ 0x2f, 0x62, 0x6f, 0x64, 0x79, 0x3e, 0xd, 0xa, 0x3c, 0x2f,
+ 0x6e, 0x6f, 0x66, 0x72, 0x61, 0x6d, 0x65, 0x73, 0x3e, 0xd,
+ 0xa, 0x3c, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x3e, };
+
+const struct fsdata_file file_404_html[] = {{NULL, data_404_html, data_404_html + 10, sizeof(data_404_html) - 10}};
+
+const struct fsdata_file file_control_html[] = {{file_404_html, data_control_html, data_control_html + 14, sizeof(data_control_html) - 14}};
+
+const struct fsdata_file file_files_footer_plain[] = {{file_control_html, data_files_footer_plain, data_files_footer_plain + 20, sizeof(data_files_footer_plain) - 20}};
+
+const struct fsdata_file file_files_header_html[] = {{file_files_footer_plain, data_files_header_html, data_files_header_html + 19, sizeof(data_files_header_html) - 19}};
+
+const struct fsdata_file file_stats_footer_plain[] = {{file_files_header_html, data_stats_footer_plain, data_stats_footer_plain + 20, sizeof(data_stats_footer_plain) - 20}};
+
+const struct fsdata_file file_stats_header_html[] = {{file_stats_footer_plain, data_stats_header_html, data_stats_header_html + 19, sizeof(data_stats_header_html) - 19}};
+
+const struct fsdata_file file_tcp_footer_plain[] = {{file_stats_header_html, data_tcp_footer_plain, data_tcp_footer_plain + 18, sizeof(data_tcp_footer_plain) - 18}};
+
+const struct fsdata_file file_tcp_header_html[] = {{file_tcp_footer_plain, data_tcp_header_html, data_tcp_header_html + 17, sizeof(data_tcp_header_html) - 17}};
+
+const struct fsdata_file file_img_logo_png[] = {{file_tcp_header_html, data_img_logo_png, data_img_logo_png + 14, sizeof(data_img_logo_png) - 14}};
+
+const struct fsdata_file file_cgi_files[] = {{file_img_logo_png, data_cgi_files, data_cgi_files + 11, sizeof(data_cgi_files) - 11}};
+
+const struct fsdata_file file_cgi_stats[] = {{file_cgi_files, data_cgi_stats, data_cgi_stats + 11, sizeof(data_cgi_stats) - 11}};
+
+const struct fsdata_file file_cgi_tcp[] = {{file_cgi_stats, data_cgi_tcp, data_cgi_tcp + 9, sizeof(data_cgi_tcp) - 9}};
+
+const struct fsdata_file file_cgi_rtos[] = {{file_cgi_tcp, data_cgi_rtos, data_cgi_rtos + 10, sizeof(data_cgi_rtos) - 10}};
+
+const struct fsdata_file file_index_html[] = {{file_cgi_rtos, data_index_html, data_index_html + 12, sizeof(data_index_html) - 12}};
+
+#define FS_ROOT file_index_html
+
+#define FS_NUMFILES 14\r
--- /dev/null
+/*\r
+ * Copyright (c) 2001, Swedish Institute of Computer Science.\r
+ * All rights reserved. \r
+ *\r
+ * Redistribution and use in source and binary forms, with or without \r
+ * modification, are permitted provided that the following conditions \r
+ * are met: \r
+ * 1. Redistributions of source code must retain the above copyright \r
+ * notice, this list of conditions and the following disclaimer. \r
+ * 2. Redistributions in binary form must reproduce the above copyright \r
+ * notice, this list of conditions and the following disclaimer in the \r
+ * documentation and/or other materials provided with the distribution. \r
+ * 3. Neither the name of the Institute nor the names of its contributors \r
+ * may be used to endorse or promote products derived from this software \r
+ * without specific prior written permission. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND \r
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE \r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE \r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE \r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL \r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS \r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) \r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT \r
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY \r
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF \r
+ * SUCH DAMAGE. \r
+ *\r
+ * This file is part of the lwIP TCP/IP stack.\r
+ * \r
+ * Author: Adam Dunkels <adam@sics.se>\r
+ *\r
+ * $Id: fsdata.h,v 1.4.2.1 2003/10/04 22:54:06 adam Exp $\r
+ */\r
+#ifndef __FSDATA_H__\r
+#define __FSDATA_H__\r
+\r
+#include "uipopt.h"\r
+\r
+struct fsdata_file {\r
+ const struct fsdata_file *next;\r
+ const char *name;\r
+ const char *data;\r
+ const int len;\r
+#ifdef FS_STATISTICS\r
+#if FS_STATISTICS == 1\r
+ u16_t count;\r
+#endif /* FS_STATISTICS */\r
+#endif /* FS_STATISTICS */\r
+};\r
+\r
+struct fsdata_file_noconst {\r
+ struct fsdata_file *next;\r
+ char *name;\r
+ char *data;\r
+ int len;\r
+#ifdef FS_STATISTICS\r
+#if FS_STATISTICS == 1\r
+ u16_t count;\r
+#endif /* FS_STATISTICS */\r
+#endif /* FS_STATISTICS */\r
+};\r
+\r
+#endif /* __FSDATA_H__ */\r
--- /dev/null
+/**\r
+ * \addtogroup exampleapps\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \defgroup httpd Web server\r
+ * @{\r
+ *\r
+ * The uIP web server is a very simplistic implementation of an HTTP\r
+ * server. It can serve web pages and files from a read-only ROM\r
+ * filesystem, and provides a very small scripting language.\r
+ *\r
+ * The script language is very simple and works as follows. Each\r
+ * script line starts with a command character, either "i", "t", "c",\r
+ * "#" or ".". The "i" command tells the script interpreter to\r
+ * "include" a file from the virtual file system and output it to the\r
+ * web browser. The "t" command should be followed by a line of text\r
+ * that is to be output to the browser. The "c" command is used to\r
+ * call one of the C functions from the httpd-cgi.c file. A line that\r
+ * starts with a "#" is ignored (i.e., the "#" denotes a comment), and\r
+ * the "." denotes the last script line.\r
+ *\r
+ * The script that produces the file statistics page looks somewhat\r
+ * like this:\r
+ *\r
+ \code\r
+i /header.html\r
+t <h1>File statistics</h1><br><table width="100%">\r
+t <tr><td><a href="/index.html">/index.html</a></td><td>\r
+c a /index.html\r
+t </td></tr> <tr><td><a href="/cgi/files">/cgi/files</a></td><td>\r
+c a /cgi/files\r
+t </td></tr> <tr><td><a href="/cgi/tcp">/cgi/tcp</a></td><td>\r
+c a /cgi/tcp\r
+t </td></tr> <tr><td><a href="/404.html">/404.html</a></td><td>\r
+c a /404.html\r
+t </td></tr></table>\r
+i /footer.plain\r
+.\r
+ \endcode\r
+ *\r
+ */\r
+\r
+\r
+/**\r
+ * \file\r
+ * HTTP server.\r
+ * \author Adam Dunkels <adam@dunkels.com>\r
+ */\r
+\r
+/*\r
+ * Copyright (c) 2001, Adam Dunkels.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ * 3. The name of the author may not be used to endorse or promote\r
+ * products derived from this software without specific prior\r
+ * written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * $Id: httpd.c,v 1.28.2.6 2003/10/07 13:22:27 adam Exp $\r
+ *\r
+ */\r
+\r
+\r
+#include "uip.h"\r
+#include "httpd.h"\r
+#include "fs.h"\r
+#include "fsdata.h"\r
+#include "cgi.h"\r
+\r
+#define NULL (void *)0\r
+\r
+/* The HTTP server states: */\r
+#define HTTP_NOGET 0\r
+#define HTTP_FILE 1\r
+#define HTTP_TEXT 2\r
+#define HTTP_FUNC 3\r
+#define HTTP_END 4\r
+\r
+#ifdef DEBUG\r
+#include <stdio.h>\r
+#define PRINT(x)\r
+#define PRINTLN(x)\r
+#else /* DEBUG */\r
+#define PRINT(x)\r
+#define PRINTLN(x)\r
+#endif /* DEBUG */\r
+\r
+struct httpd_state *hs;\r
+\r
+extern const struct fsdata_file file_index_html;\r
+extern const struct fsdata_file file_404_html;\r
+\r
+static void next_scriptline(void);\r
+static void next_scriptstate(void);\r
+\r
+#define ISO_G 0x47\r
+#define ISO_E 0x45\r
+#define ISO_T 0x54\r
+#define ISO_slash 0x2f\r
+#define ISO_c 0x63\r
+#define ISO_g 0x67\r
+#define ISO_i 0x69\r
+#define ISO_space 0x20\r
+#define ISO_nl 0x0a\r
+#define ISO_cr 0x0d\r
+#define ISO_a 0x61\r
+#define ISO_t 0x74\r
+#define ISO_hash 0x23\r
+#define ISO_period 0x2e\r
+\r
+#define httpPORT 80\r
+\r
+/*-----------------------------------------------------------------------------------*/\r
+/**\r
+ * Initialize the web server.\r
+ *\r
+ * Starts to listen for incoming connection requests on TCP port 80.\r
+ */\r
+/*-----------------------------------------------------------------------------------*/\r
+void\r
+httpd_init(void)\r
+{\r
+ fs_init();\r
+\r
+ /* Listen to port 80. */\r
+ uip_listen(HTONS(httpPORT));\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+void\r
+httpd_appcall(void)\r
+{\r
+ struct fs_file fsfile;\r
+\r
+ u8_t i;\r
+\r
+ switch(uip_conn->lport) {\r
+ /* This is the web server: */\r
+ case HTONS(httpPORT):\r
+ /* Pick out the application state from the uip_conn structure. */\r
+ hs = (struct httpd_state *)(uip_conn->appstate);\r
+\r
+ /* We use the uip_ test functions to deduce why we were\r
+ called. If uip_connected() is non-zero, we were called\r
+ because a remote host has connected to us. If\r
+ uip_newdata() is non-zero, we were called because the\r
+ remote host has sent us new data, and if uip_acked() is\r
+ non-zero, the remote host has acknowledged the data we\r
+ previously sent to it. */\r
+ if(uip_connected()) {\r
+ /* Since we have just been connected with the remote host, we\r
+ reset the state for this connection. The ->count variable\r
+ contains the amount of data that is yet to be sent to the\r
+ remote host, and the ->state is set to HTTP_NOGET to signal\r
+ that we haven't received any HTTP GET request for this\r
+ connection yet. */\r
+\r
+ hs->state = HTTP_NOGET;\r
+ hs->count = 0;\r
+ return;\r
+\r
+ } else if(uip_poll()) {\r
+ /* If we are polled ten times, we abort the connection. This is\r
+ because we don't want connections lingering indefinately in\r
+ the system. */\r
+ if(hs->count++ >= 10) {\r
+ uip_abort();\r
+ }\r
+ return;\r
+ } else if(uip_newdata() && hs->state == HTTP_NOGET) {\r
+ /* This is the first data we receive, and it should contain a\r
+ GET. */\r
+\r
+ /* Check for GET. */\r
+ if(uip_appdata[0] != ISO_G ||\r
+ uip_appdata[1] != ISO_E ||\r
+ uip_appdata[2] != ISO_T ||\r
+ uip_appdata[3] != ISO_space) {\r
+ /* If it isn't a GET, we abort the connection. */\r
+ uip_abort();\r
+ return;\r
+ }\r
+ \r
+ /* Find the file we are looking for. */\r
+ for(i = 4; i < 40; ++i) {\r
+ if(uip_appdata[i] == ISO_space ||\r
+ uip_appdata[i] == ISO_cr ||\r
+ uip_appdata[i] == ISO_nl) {\r
+ uip_appdata[i] = 0;\r
+ break;\r
+ }\r
+ }\r
+\r
+ PRINT("request for file ");\r
+ PRINTLN(&uip_appdata[4]);\r
+\r
+ /* Check for a request for "/". */\r
+ if(uip_appdata[4] == ISO_slash &&\r
+ uip_appdata[5] == 0) {\r
+ fs_open(file_index_html.name, &fsfile);\r
+ } else {\r
+ if(!fs_open((const char *)&uip_appdata[4], &fsfile)) {\r
+ PRINTLN("couldn't open file");\r
+ fs_open(file_404_html.name, &fsfile);\r
+ }\r
+ }\r
+\r
+\r
+ if(uip_appdata[4] == ISO_slash &&\r
+ uip_appdata[5] == ISO_c &&\r
+ uip_appdata[6] == ISO_g &&\r
+ uip_appdata[7] == ISO_i &&\r
+ uip_appdata[8] == ISO_slash) {\r
+ /* If the request is for a file that starts with "/cgi/", we\r
+ prepare for invoking a script. */ \r
+ hs->script = fsfile.data;\r
+ next_scriptstate();\r
+ } else {\r
+ hs->script = NULL;\r
+ /* The web server is now no longer in the HTTP_NOGET state, but\r
+ in the HTTP_FILE state since is has now got the GET from\r
+ the client and will start transmitting the file. */\r
+ hs->state = HTTP_FILE;\r
+\r
+ /* Point the file pointers in the connection state to point to\r
+ the first byte of the file. */\r
+ hs->dataptr = fsfile.data;\r
+ hs->count = fsfile.len; \r
+ }\r
+ }\r
+\r
+\r
+ if(hs->state != HTTP_FUNC) {\r
+ /* Check if the client (remote end) has acknowledged any data that\r
+ we've previously sent. If so, we move the file pointer further\r
+ into the file and send back more data. If we are out of data to\r
+ send, we close the connection. */\r
+ if(uip_acked()) {\r
+ if(hs->count >= uip_conn->len) {\r
+ hs->count -= uip_conn->len;\r
+ hs->dataptr += uip_conn->len;\r
+ } else {\r
+ hs->count = 0;\r
+ }\r
+ \r
+ if(hs->count == 0) {\r
+ if(hs->script != NULL) {\r
+ next_scriptline();\r
+ next_scriptstate();\r
+ } else {\r
+ uip_close();\r
+ }\r
+ }\r
+ }\r
+ } else {\r
+ /* Call the CGI function. */\r
+ if(cgitab[hs->script[2] - ISO_a](uip_acked())) {\r
+ /* If the function returns non-zero, we jump to the next line\r
+ in the script. */\r
+ next_scriptline();\r
+ next_scriptstate();\r
+ }\r
+ }\r
+\r
+ if(hs->state != HTTP_FUNC && !uip_poll()) {\r
+ /* Send a piece of data, but not more than the MSS of the\r
+ connection. */\r
+ uip_send(( void * ) hs->dataptr, hs->count);\r
+ }\r
+\r
+ /* Finally, return to uIP. Our outgoing packet will soon be on its\r
+ way... */\r
+ return;\r
+\r
+ default:\r
+ /* Should never happen. */\r
+ uip_abort();\r
+ break;\r
+ }\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+/* next_scriptline():\r
+ *\r
+ * Reads the script until it finds a newline. */\r
+static void\r
+next_scriptline(void)\r
+{\r
+ /* Loop until we find a newline character. */\r
+ do {\r
+ ++(hs->script);\r
+ } while(hs->script[0] != ISO_nl);\r
+\r
+ /* Eat up the newline as well. */\r
+ ++(hs->script);\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+/* next_sciptstate:\r
+ *\r
+ * Reads one line of script and decides what to do next.\r
+ */\r
+static void\r
+next_scriptstate(void)\r
+{\r
+ struct fs_file fsfile;\r
+ long i;\r
+\r
+ again:\r
+ switch(hs->script[0]) {\r
+ case ISO_t:\r
+ /* Send a text string. */\r
+ hs->state = HTTP_TEXT;\r
+ hs->dataptr = &hs->script[2];\r
+\r
+ /* Calculate length of string. */\r
+ for(i = 0; hs->dataptr[i] != ISO_nl; ++i);\r
+ hs->count = i;\r
+ break;\r
+ case ISO_c:\r
+ /* Call a function. */\r
+ hs->state = HTTP_FUNC;\r
+ hs->dataptr = NULL;\r
+ hs->count = 0;\r
+ cgitab[hs->script[2] - ISO_a](0);\r
+ break;\r
+ case ISO_i:\r
+ /* Include a file. */\r
+ hs->state = HTTP_FILE;\r
+ if(!fs_open(&hs->script[2], &fsfile)) {\r
+ uip_abort();\r
+ }\r
+ hs->dataptr = fsfile.data;\r
+ hs->count = fsfile.len;\r
+ break;\r
+ case ISO_hash:\r
+ /* Comment line. */\r
+ next_scriptline();\r
+ goto again;\r
+ case ISO_period:\r
+ /* End of script. */\r
+ hs->state = HTTP_END;\r
+ uip_close();\r
+ break;\r
+ default:\r
+ uip_abort();\r
+ break;\r
+ }\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+/** @} */\r
+/** @} */\r
--- /dev/null
+/*$T httpd.c GC 1.138 07/23/05 13:10:49 */\r
+\r
+/*\r
+ * \addtogroup exampleapps @{ £\r
+ * \defgroup httpd Web server @{ The uIP web server is a very simplistic\r
+ * implementation of an HTTP server. It can serve web pages and files from a\r
+ * read-only ROM filesystem, and provides a very small scripting language. The\r
+ * script language is very simple and works as follows. Each script line starts\r
+ * with a command character, either "i", "t", "c", "#" or ".". The "i" command\r
+ * tells the script interpreter to "include" a file from the virtual file system\r
+ * and output it to the web browser. The "t" command should be followed by a line\r
+ * of text that is to be output to the browser. The "c" command is used to call\r
+ * one of the C functions from the httpd-cgi.c file. A line that starts with a "#"\r
+ * is ignored (i.e., the "#" denotes a comment), and the "." denotes the last\r
+ * script line. The script that produces the file statistics page looks somewhat\r
+ * like this: \code i /header.html t <h1>File statistics</h1><br><table\r
+ * width="100%"> t <tr><td><a href="/index.html">/index.html</a></td><td> c a\r
+ * /index.html t </td></tr> <tr><td><a href="/cgi/files">/cgi/files</a></td><td> c\r
+ * a /cgi/files t </td></tr> <tr><td><a href="/cgi/tcp">/cgi/tcp</a></td><td> c a\r
+ * /cgi/tcp t </td></tr> <tr><td><a href="/404.html">/404.html</a></td><td> c a\r
+ * /404.html t </td></tr></table> i /footer.plain . \endcode £\r
+ * \file HTTP server. \author Adam Dunkels <adam@dunkels.com> £\r
+ * Copyright (c) 2001, Adam Dunkels. All rights reserved. Redistribution and use\r
+ * in source and binary forms, with or without modification, are permitted\r
+ * provided that the following conditions are met: 1. Redistributions of source\r
+ * code must retain the above copyright notice, this list of conditions and the\r
+ * following disclaimer. 2. Redistributions in binary form must reproduce the\r
+ * above copyright notice, this list of conditions and the following disclaimer in\r
+ * the documentation and/or other materials provided with the distribution. 3. The\r
+ * name of the author may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission. THIS SOFTWARE IS\r
+ * PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,\r
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND\r
+ * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR\r
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT\r
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * This file is part of the uIP TCP/IP stack. $Id: httpd.c,v 1.28.2.6 2003/10/07\r
+ * 13:22:27 adam Exp $\r
+ */\r
+#include "uip.h"\r
+#include "httpd.h"\r
+#include "fs.h"\r
+#include "fsdata.h"\r
+#include "cgi.h"\r
+\r
+#define NULL ( void * ) 0\r
+\r
+/* The HTTP server states: */\r
+#define HTTP_NOGET 0\r
+#define HTTP_FILE 1\r
+#define HTTP_TEXT 2\r
+#define HTTP_FUNC 3\r
+#define HTTP_END 4\r
+\r
+#ifdef DEBUG\r
+#include <stdio.h>\r
+#define PRINT( x )\r
+#define PRINTLN( x )\r
+#else /* DEBUG */\r
+#define PRINT( x )\r
+#define PRINTLN( x )\r
+#endif /* DEBUG */\r
+\r
+struct httpd_state *hs;\r
+\r
+extern const struct fsdata_file file_index_html;\r
+extern const struct fsdata_file file_404_html;\r
+\r
+static void next_scriptline( void );\r
+static void next_scriptstate( void );\r
+\r
+#define ISO_G 0x47\r
+#define ISO_E 0x45\r
+#define ISO_T 0x54\r
+#define ISO_slash 0x2f\r
+#define ISO_c 0x63\r
+#define ISO_g 0x67\r
+#define ISO_i 0x69\r
+#define ISO_space 0x20\r
+#define ISO_nl 0x0a\r
+#define ISO_cr 0x0d\r
+#define ISO_a 0x61\r
+#define ISO_t 0x74\r
+#define ISO_hash 0x23\r
+#define ISO_period 0x2e\r
+\r
+#define httpPORT 80\r
+\r
+/*\r
+ =======================================================================================================================\r
+ Initialize the web server. Starts to listen for incoming connection requests on TCP port 80.\r
+ =======================================================================================================================\r
+ */\r
+void httpd_init( void )\r
+{\r
+ fs_init();\r
+\r
+ /* Listen to port 80. */\r
+ uip_listen( HTONS( httpPORT ) );\r
+}\r
+\r
+/*\r
+ =======================================================================================================================\r
+ =======================================================================================================================\r
+ */\r
+void httpd_appcall( void )\r
+{\r
+ /*~~~~~~~~~~~~~~~~~~~*/\r
+ struct fs_file fsfile;\r
+ u8_t i;\r
+ /*~~~~~~~~~~~~~~~~~~~*/\r
+\r
+ switch( uip_conn->lport )\r
+ {\r
+ /* This is the web server: */\r
+ case HTONS( httpPORT ):\r
+ /* Pick out the application state from the uip_conn structure. */\r
+ hs = ( struct httpd_state * ) ( uip_conn->appstate );\r
+\r
+ /*\r
+ * We use the uip_ test functions to deduce why we were called. If uip_connected()\r
+ * is non-zero, we were called because a remote host has connected to us. If\r
+ * uip_newdata() is non-zero, we were called because the remote host has sent us\r
+ * new data, and if uip_acked() is non-zero, the remote host has acknowledged the\r
+ * data we previously sent to it.\r
+ */\r
+ if( uip_connected() )\r
+ {\r
+ /*\r
+ * Since we have just been connected with the remote host, we reset the state for\r
+ * this connection. The ->count variable contains the amount of data that is yet\r
+ * to be sent to the remote host, and the ->state is set to HTTP_NOGET to signal\r
+ * that we haven't received any HTTP GET request for this connection yet.\r
+ */\r
+ hs->state = HTTP_NOGET;\r
+ hs->count = 0;\r
+ return;\r
+ }\r
+ else if( uip_poll() )\r
+ {\r
+ /*\r
+ * If we are polled ten times, we abort the connection. This is because we don't\r
+ * want connections lingering indefinately in the system.\r
+ */\r
+ if( hs->count++ >= 10 )\r
+ {\r
+ uip_abort();\r
+ }\r
+\r
+ return;\r
+ }\r
+ else if( uip_newdata() && hs->state == HTTP_NOGET )\r
+ {\r
+ /*\r
+ * This is the first data we receive, and it should contain a GET. £\r
+ * Check for GET.\r
+ */\r
+ if\r
+ (\r
+ uip_appdata[0] != ISO_G\r
+ || uip_appdata[1] != ISO_E\r
+ || uip_appdata[2] != ISO_T\r
+ || uip_appdata[3] != ISO_space\r
+ )\r
+ {\r
+ /* If it isn't a GET, we abort the connection. */\r
+ uip_abort();\r
+ return;\r
+ }\r
+\r
+ /* Find the file we are looking for. */\r
+ for( i = 4; i < 40; ++i )\r
+ {\r
+ if( uip_appdata[i] == ISO_space || uip_appdata[i] == ISO_cr || uip_appdata[i] == ISO_nl )\r
+ {\r
+ uip_appdata[i] = 0;\r
+ break;\r
+ }\r
+ }\r
+\r
+ PRINT( "request for file " );\r
+ PRINTLN( &uip_appdata[4] );\r
+\r
+ /* Check for a request for "/". */\r
+ if( uip_appdata[4] == ISO_slash && uip_appdata[5] == 0 )\r
+ {\r
+ fs_open( file_index_html.name, &fsfile );\r
+ }\r
+ else\r
+ {\r
+ if( !fs_open( ( const char * ) &uip_appdata[4], &fsfile ) )\r
+ {\r
+ PRINTLN( "couldn't open file" );\r
+ fs_open( file_404_html.name, &fsfile );\r
+ }\r
+ }\r
+\r
+ if\r
+ (\r
+ uip_appdata[4] == ISO_slash\r
+ && uip_appdata[5] == ISO_c\r
+ && uip_appdata[6] == ISO_g\r
+ && uip_appdata[7] == ISO_i\r
+ && uip_appdata[8] == ISO_slash\r
+ )\r
+ {\r
+ /*\r
+ * If the request is for a file that starts with "/cgi/", we prepare for invoking\r
+ * a script.\r
+ */\r
+ hs->script = fsfile.data;\r
+ next_scriptstate();\r
+ }\r
+ else\r
+ {\r
+ hs->script = NULL;\r
+\r
+ /*\r
+ * The web server is now no longer in the HTTP_NOGET state, but in the HTTP_FILE\r
+ * state since is has now got the GET from the client and will start transmitting\r
+ * the file.\r
+ */\r
+ hs->state = HTTP_FILE;\r
+\r
+ /*\r
+ * Point the file pointers in the connection state to point to the first byte of\r
+ * the file.\r
+ */\r
+ hs->dataptr = fsfile.data;\r
+ hs->count = fsfile.len;\r
+ }\r
+ }\r
+\r
+ if( hs->state != HTTP_FUNC )\r
+ {\r
+ /*\r
+ * Check if the client (remote end) has acknowledged any data that we've\r
+ * previously sent. If so, we move the file pointer further into the file and send\r
+ * back more data. If we are out of data to send, we close the connection.\r
+ */\r
+ if( uip_acked() )\r
+ {\r
+ if( hs->count >= uip_conn->len )\r
+ {\r
+ hs->count -= uip_conn->len;\r
+ hs->dataptr += uip_conn->len;\r
+ }\r
+ else\r
+ {\r
+ hs->count = 0;\r
+ }\r
+\r
+ if( hs->count == 0 )\r
+ {\r
+ if( hs->script != NULL )\r
+ {\r
+ next_scriptline();\r
+ next_scriptstate();\r
+ }\r
+ else\r
+ {\r
+ uip_close();\r
+ }\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Call the CGI function. */\r
+ if( cgitab[hs->script[2] - ISO_a](uip_acked()) )\r
+ {\r
+ /* If the function returns non-zero, we jump to the next line in the script. */\r
+ next_scriptline();\r
+ next_scriptstate();\r
+ }\r
+ }\r
+\r
+ if( hs->state != HTTP_FUNC && !uip_poll() )\r
+ {\r
+ /* Send a piece of data, but not more than the MSS of the connection. */\r
+ uip_send( ( void * ) hs->dataptr, hs->count );\r
+ }\r
+\r
+ /* Finally, return to uIP. Our outgoing packet will soon be on its way... */\r
+ return;\r
+\r
+ default:\r
+ /* Should never happen. */\r
+ uip_abort();\r
+ break;\r
+ }\r
+}\r
+\r
+/*\r
+ =======================================================================================================================\r
+ next_scriptline(): Reads the script until it finds a newline.\r
+ =======================================================================================================================\r
+ */\r
+static void next_scriptline( void )\r
+{\r
+ /* Loop until we find a newline character. */\r
+ do\r
+ {\r
+ ++( hs->script );\r
+ } while( hs->script[0] != ISO_nl );\r
+\r
+ /* Eat up the newline as well. */\r
+ ++( hs->script );\r
+}\r
+\r
+/*\r
+ =======================================================================================================================\r
+ next_sciptstate: Reads one line of script and decides what to do next.\r
+ =======================================================================================================================\r
+ */\r
+static void next_scriptstate( void )\r
+{\r
+ /*~~~~~~~~~~~~~~~~~~~*/\r
+ struct fs_file fsfile;\r
+ u8_t i;\r
+ /*~~~~~~~~~~~~~~~~~~~*/\r
+\r
+again:\r
+ switch( hs->script[0] )\r
+ {\r
+ case ISO_t:\r
+ /* Send a text string. */\r
+ hs->state = HTTP_TEXT;\r
+ hs->dataptr = &hs->script[2];\r
+\r
+ /* Calculate length of string. */\r
+ for( i = 0; hs->dataptr[i] != ISO_nl; ++i );\r
+ hs->count = i;\r
+ break;\r
+\r
+ case ISO_c:\r
+ /* Call a function. */\r
+ hs->state = HTTP_FUNC;\r
+ hs->dataptr = NULL;\r
+ hs->count = 0;\r
+ cgitab[hs->script[2] - ISO_a]( 0 );\r
+ break;\r
+\r
+ case ISO_i:\r
+ /* Include a file. */\r
+ hs->state = HTTP_FILE;\r
+ if( !fs_open( &hs->script[2], &fsfile ) )\r
+ {\r
+ uip_abort();\r
+ }\r
+\r
+ hs->dataptr = fsfile.data;\r
+ hs->count = fsfile.len;\r
+ break;\r
+\r
+ case ISO_hash:\r
+ /* Comment line. */\r
+ next_scriptline();\r
+ goto again;\r
+\r
+ case ISO_period:\r
+ /* End of script. */\r
+ hs->state = HTTP_END;\r
+ uip_close();\r
+ break;\r
+\r
+ default:\r
+ uip_abort();\r
+ break;\r
+ }\r
+}\r
+\r
+/*\r
+ * @} £\r
+ * @}\r
+ */\r
--- /dev/null
+/**\r
+ * \addtogroup httpd\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * HTTP server header file.\r
+ * \author Adam Dunkels <adam@dunkels.com>\r
+ */\r
+\r
+/*\r
+ * Copyright (c) 2001, Adam Dunkels.\r
+ * All rights reserved. \r
+ *\r
+ * Redistribution and use in source and binary forms, with or without \r
+ * modification, are permitted provided that the following conditions \r
+ * are met: \r
+ * 1. Redistributions of source code must retain the above copyright \r
+ * notice, this list of conditions and the following disclaimer. \r
+ * 2. Redistributions in binary form must reproduce the above copyright \r
+ * notice, this list of conditions and the following disclaimer in the \r
+ * documentation and/or other materials provided with the distribution. \r
+ * 3. The name of the author may not be used to endorse or promote\r
+ * products derived from this software without specific prior\r
+ * written permission. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * $Id: httpd.h,v 1.4.2.3 2003/10/06 22:56:44 adam Exp $\r
+ *\r
+ */\r
+\r
+#ifndef __HTTPD_H__\r
+#define __HTTPD_H__\r
+\r
+void httpd_init(void);\r
+void httpd_appcall(void);\r
+\r
+/* UIP_APPCALL: the name of the application function. This function\r
+ must return void and take no arguments (i.e., C type "void\r
+ appfunc(void)"). */\r
+#ifndef UIP_APPCALL\r
+#define UIP_APPCALL httpd_appcall\r
+#endif\r
+\r
+struct httpd_state {\r
+ u8_t state; \r
+ u16_t count;\r
+ char *dataptr;\r
+ char *script;\r
+};\r
+\r
+\r
+/* UIP_APPSTATE_SIZE: The size of the application-specific state\r
+ stored in the uip_conn structure. */\r
+#ifndef UIP_APPSTATE_SIZE\r
+#define UIP_APPSTATE_SIZE (sizeof(struct httpd_state))\r
+#endif\r
+\r
+#define FS_STATISTICS 1\r
+\r
+extern struct httpd_state *hs;\r
+\r
+#endif /* __HTTPD_H__ */\r
--- /dev/null
+// Copyright (c) 2001-2004 Rowley Associates Limited.\r
+//\r
+// This file may be distributed under the terms of the License Agreement\r
+// provided with this software.\r
+//\r
+// THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE\r
+// WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\r
+//\r
+////////////////////////////////////////////////////////////////////////////////\r
+//\r
+// Olimex LPC-P1 LED Example\r
+//\r
+// Description\r
+// -----------\r
+// This example demonstrates writing to the programmable peripheral interface.\r
+//\r
+////////////////////////////////////////////////////////////////////////////////\r
+\r
+#include <targets/LPC210x.h>\r
+\r
+#define LED_RED (1<<8)\r
+#define LED_GREEN (1<<10)\r
+#define LED_YELLOW (1<<11)\r
+\r
+#define LED1 LED_YELLOW\r
+\r
+static void\r
+ledInit()\r
+{\r
+ IODIR |= LED1;\r
+ IOSET = LED1;\r
+}\r
+\r
+static void\r
+ledOn(void)\r
+{\r
+ IOCLR = LED1;\r
+}\r
+\r
+static void\r
+ledOff(void)\r
+{\r
+ IOSET = LED1;\r
+}\r
+\r
+void\r
+delay(int d)\r
+{ \r
+ for(; d; --d);\r
+}\r
+ \r
+int\r
+main(void)\r
+{\r
+ MAMCR = 2;\r
+ ledInit();\r
+ while (1)\r
+ {\r
+ ledOn();\r
+ delay(100000);\r
+ ledOff();\r
+ delay(100000);\r
+ }\r
+ return 0;\r
+}\r
+\r
+\r
--- /dev/null
+#!/usr/bin/perl\r
+\r
+open(OUTPUT, "> fsdata.c");\r
+\r
+chdir("fs");\r
+open(FILES, "find . -type f |");\r
+\r
+while($file = <FILES>) {\r
+\r
+ # Do not include files in CVS directories nor backup files.\r
+ if($file =~ /(CVS|~)/) {\r
+ next;\r
+ }\r
+ \r
+ chop($file);\r
+ \r
+ open(HEADER, "> /tmp/header") || die $!;\r
+ if($file =~ /404.html/) {\r
+ print(HEADER "HTTP/1.0 404 File not found\r\n");\r
+ } else {\r
+ print(HEADER "HTTP/1.0 200 OK\r\n");\r
+ }\r
+ print(HEADER "Server: uIP/0.9 (http://dunkels.com/adam/uip/)\r\n");\r
+ if($file =~ /\.html$/) {\r
+ print(HEADER "Content-type: text/html\r\n");\r
+ } elsif($file =~ /\.gif$/) {\r
+ print(HEADER "Content-type: image/gif\r\n");\r
+ } elsif($file =~ /\.png$/) {\r
+ print(HEADER "Content-type: image/png\r\n");\r
+ } elsif($file =~ /\.jpg$/) {\r
+ print(HEADER "Content-type: image/jpeg\r\n");\r
+ } else {\r
+ print(HEADER "Content-type: text/plain\r\n");\r
+ }\r
+ print(HEADER "\r\n");\r
+ close(HEADER);\r
+\r
+ unless($file =~ /\.plain$/ || $file =~ /cgi/) {\r
+ system("cat /tmp/header $file > /tmp/file");\r
+ } else {\r
+ system("cp $file /tmp/file");\r
+ }\r
+ \r
+ open(FILE, "/tmp/file");\r
+ unlink("/tmp/file");\r
+ unlink("/tmp/header");\r
+\r
+ $file =~ s/\.//;\r
+ $fvar = $file;\r
+ $fvar =~ s-/-_-g;\r
+ $fvar =~ s-\.-_-g;\r
+ print(OUTPUT "static const char data".$fvar."[] = {\n");\r
+ print(OUTPUT "\t/* $file */\n\t");\r
+ for($j = 0; $j < length($file); $j++) {\r
+ printf(OUTPUT "%#02x, ", unpack("C", substr($file, $j, 1)));\r
+ }\r
+ printf(OUTPUT "0,\n");\r
+ \r
+ \r
+ $i = 0; \r
+ while(read(FILE, $data, 1)) {\r
+ if($i == 0) {\r
+ print(OUTPUT "\t");\r
+ }\r
+ printf(OUTPUT "%#02x, ", unpack("C", $data));\r
+ $i++;\r
+ if($i == 10) {\r
+ print(OUTPUT "\n");\r
+ $i = 0;\r
+ }\r
+ }\r
+ print(OUTPUT "};\n\n");\r
+ close(FILE);\r
+ push(@fvars, $fvar);\r
+ push(@files, $file);\r
+}\r
+\r
+for($i = 0; $i < @fvars; $i++) {\r
+ $file = $files[$i];\r
+ $fvar = $fvars[$i];\r
+\r
+ if($i == 0) {\r
+ $prevfile = "NULL";\r
+ } else {\r
+ $prevfile = "file" . $fvars[$i - 1];\r
+ }\r
+ print(OUTPUT "const struct fsdata_file file".$fvar."[] = {{$prevfile, data$fvar, ");\r
+ print(OUTPUT "data$fvar + ". (length($file) + 1) .", ");\r
+ print(OUTPUT "sizeof(data$fvar) - ". (length($file) + 1) ."}};\n\n");\r
+}\r
+\r
+print(OUTPUT "#define FS_ROOT file$fvars[$i - 1]\n\n");\r
+print(OUTPUT "#define FS_NUMFILES $i");\r
--- /dev/null
+/**\r
+ * \addtogroup exampleapps\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * Memory block allocation routines.\r
+ * \author Adam Dunkels <adam@sics.se>\r
+ *\r
+ * The memory block allocation routines provide a simple yet powerful\r
+ * set of functions for managing a set of memory blocks of fixed\r
+ * size. A set of memory blocks is statically declared with the\r
+ * MEMB() macro. Memory blocks are allocated from the declared\r
+ * memory by the memb_alloc() function, and are deallocated with the\r
+ * memb_free() function.\r
+ *\r
+ * \note Because of namespace clashes only one MEMB() can be\r
+ * declared per C module, and the name scope of a MEMB() memory\r
+ * block is local to each C module.\r
+ *\r
+ * The following example shows how to declare and use a memory block\r
+ * called "cmem" which has 8 chunks of memory with each memory chunk\r
+ * being 20 bytes large.\r
+ *\r
+ \code\r
+ MEMB(cmem, 20, 8);\r
+\r
+ int main(int argc, char *argv[]) {\r
+ char *ptr;\r
+ \r
+ memb_init(&cmem);\r
+\r
+ ptr = memb_alloc(&cmem);\r
+\r
+ if(ptr != NULL) {\r
+ do_something(ptr);\r
+ } else {\r
+ printf("Could not allocate memory.\n");\r
+ }\r
+\r
+ if(memb_free(ptr) == 0) {\r
+ printf("Deallocation succeeded.\n");\r
+ }\r
+ }\r
+ \endcode\r
+ * \r
+ */\r
+\r
+#include <string.h>\r
+\r
+#include "memb.h"\r
+\r
+/*------------------------------------------------------------------------------*/\r
+/**\r
+ * Initialize a memory block that was declared with MEMB().\r
+ *\r
+ * \param m A memory block previosly declared with MEMB().\r
+ */\r
+/*------------------------------------------------------------------------------*/\r
+void\r
+memb_init(struct memb_blocks *m)\r
+{\r
+ memset(m->mem, (m->size + 1) * m->num, 0);\r
+}\r
+/*------------------------------------------------------------------------------*/\r
+/**\r
+ * Allocate a memory block from a block of memory declared with MEMB().\r
+ *\r
+ * \param m A memory block previosly declared with MEMB().\r
+ */\r
+/*------------------------------------------------------------------------------*/\r
+char *\r
+memb_alloc(struct memb_blocks *m)\r
+{\r
+ int i;\r
+ char *ptr;\r
+\r
+ ptr = m->mem;\r
+ for(i = 0; i < m->num; ++i) {\r
+ if(*ptr == 0) {\r
+ /* If this block was unused, we increase the reference count to\r
+ indicate that it now is used and return a pointer to the\r
+ first byte following the reference counter. */\r
+ ++*ptr;\r
+ return ptr + 1;\r
+ }\r
+ ptr += m->size + 1;\r
+ }\r
+\r
+ /* No free block was found, so we return NULL to indicate failure to\r
+ allocate block. */\r
+ return NULL;\r
+}\r
+/*------------------------------------------------------------------------------*/\r
+/**\r
+ * Deallocate a memory block from a memory block previously declared\r
+ * with MEMB().\r
+ *\r
+ * \param m m A memory block previosly declared with MEMB().\r
+ *\r
+ * \param ptr A pointer to the memory block that is to be deallocated.\r
+ *\r
+ * \return The new reference count for the memory block (should be 0\r
+ * if successfully deallocated) or -1 if the pointer "ptr" did not\r
+ * point to a legal memory block.\r
+ */\r
+/*------------------------------------------------------------------------------*/\r
+char\r
+memb_free(struct memb_blocks *m, char *ptr)\r
+{\r
+ int i;\r
+ char *ptr2;\r
+\r
+ /* Walk through the list of blocks and try to find the block to\r
+ which the pointer "ptr" points to. */\r
+ ptr2 = m->mem;\r
+ for(i = 0; i < m->num; ++i) {\r
+ \r
+ if(ptr2 == ptr - 1) {\r
+ /* We've found to block to which "ptr" points so we decrease the\r
+ reference count and return the new value of it. */ \r
+ return --*ptr2;\r
+ }\r
+ ptr2 += m->size + 1;\r
+ }\r
+ return -1;\r
+}\r
+/*------------------------------------------------------------------------------*/\r
+/**\r
+ * Increase the reference count for a memory chunk.\r
+ *\r
+ * \note No sanity checks are currently made.\r
+ *\r
+ * \param m m A memory block previosly declared with MEMB().\r
+ *\r
+ * \param ptr A pointer to the memory chunk for which the reference\r
+ * count should be increased.\r
+ *\r
+ * \return The new reference count.\r
+ */\r
+/*------------------------------------------------------------------------------*/\r
+char\r
+memb_ref(struct memb_blocks *m, char *ptr)\r
+{\r
+ return ++*(ptr - 1);\r
+}\r
+/*------------------------------------------------------------------------------*/\r
+\r
+\r
+\r
+\r
--- /dev/null
+/**\r
+ * \addtogroup exampleapps\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * Memory block allocation routines.\r
+ * \author Adam Dunkels <adam@sics.se>\r
+ *\r
+ */\r
+\r
+#ifndef __MEMB_H__\r
+#define __MEMB_H__\r
+\r
+/**\r
+ * Declare a memory block.\r
+ *\r
+ * \param name The name of the memory block (later used with\r
+ * memb_init(), memb_alloc() and memb_free()).\r
+ *\r
+ * \param size The size of each memory chunk, in bytes.\r
+ *\r
+ * \param num The total number of memory chunks in the block.\r
+ *\r
+ */\r
+#define MEMB(name, size, num) \\r
+ static char memb_mem[(size + 1) * num]; \\r
+ static struct memb_blocks name = {size, num, memb_mem}\r
+\r
+struct memb_blocks {\r
+ unsigned short size;\r
+ unsigned short num;\r
+ char *mem;\r
+};\r
+\r
+void memb_init(struct memb_blocks *m);\r
+char *memb_alloc(struct memb_blocks *m);\r
+char memb_ref(struct memb_blocks *m, char *ptr);\r
+char memb_free(struct memb_blocks *m, char *ptr);\r
+\r
+\r
+#endif /* __MEMB_H__ */\r
--- /dev/null
+arp -s 172.25.218.210 00-bd-3b-33-05-72\r
--- /dev/null
+/**\r
+ * \addtogroup uip\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \defgroup slip Serial Line IP (SLIP) protocol\r
+ * @{\r
+ *\r
+ * The SLIP protocol is a very simple way to transmit IP packets over\r
+ * a serial line. It does not provide any framing or error control,\r
+ * and is therefore not very widely used today.\r
+ *\r
+ * This SLIP implementation requires two functions for accessing the\r
+ * serial device: slipdev_char_poll() and slipdev_char_put(). These\r
+ * must be implemented specifically for the system on which the SLIP\r
+ * protocol is to be run.\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * SLIP protocol implementation\r
+ * \author Adam Dunkels <adam@dunkels.com>\r
+ */\r
+\r
+/*\r
+ * Copyright (c) 2001, Adam Dunkels.\r
+ * All rights reserved. \r
+ *\r
+ * Redistribution and use in source and binary forms, with or without \r
+ * modification, are permitted provided that the following conditions \r
+ * are met: \r
+ * 1. Redistributions of source code must retain the above copyright \r
+ * notice, this list of conditions and the following disclaimer. \r
+ * 2. Redistributions in binary form must reproduce the above copyright \r
+ * notice, this list of conditions and the following disclaimer in the \r
+ * documentation and/or other materials provided with the distribution. \r
+ * 3. The name of the author may not be used to endorse or promote\r
+ * products derived from this software without specific prior\r
+ * written permission. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * $Id: slipdev.c,v 1.1.2.3 2003/10/07 13:23:01 adam Exp $\r
+ *\r
+ */\r
+\r
+/*\r
+ * This is a generic implementation of the SLIP protocol over an RS232\r
+ * (serial) device. \r
+ *\r
+ * Huge thanks to Ullrich von Bassewitz <uz@cc65.org> of cc65 fame for\r
+ * and endless supply of bugfixes, insightsful comments and\r
+ * suggestions, and improvements to this code!\r
+ */\r
+\r
+#include "uip.h"\r
+\r
+#define SLIP_END 0300\r
+#define SLIP_ESC 0333\r
+#define SLIP_ESC_END 0334\r
+#define SLIP_ESC_ESC 0335\r
+\r
+static u8_t slip_buf[UIP_BUFSIZE];\r
+\r
+static u16_t len, tmplen;\r
+static u8_t lastc;\r
+\r
+/*-----------------------------------------------------------------------------------*/\r
+/**\r
+ * Send the packet in the uip_buf and uip_appdata buffers using the\r
+ * SLIP protocol.\r
+ *\r
+ * The first 40 bytes of the packet (the IP and TCP headers) are read\r
+ * from the uip_buf buffer, and the following bytes (the application\r
+ * data) are read from the uip_appdata buffer.\r
+ *\r
+ */\r
+/*-----------------------------------------------------------------------------------*/\r
+void\r
+slipdev_send(void)\r
+{\r
+ u16_t i;\r
+ u8_t *ptr;\r
+ u8_t c;\r
+\r
+ slipdev_char_put(SLIP_END);\r
+\r
+ ptr = uip_buf;\r
+ for(i = 0; i < uip_len; ++i) {\r
+ if(i == 40) {\r
+ ptr = (u8_t *)uip_appdata;\r
+ }\r
+ c = *ptr++;\r
+ switch(c) {\r
+ case SLIP_END:\r
+ slipdev_char_put(SLIP_ESC);\r
+ slipdev_char_put(SLIP_ESC_END);\r
+ break;\r
+ case SLIP_ESC:\r
+ slipdev_char_put(SLIP_ESC);\r
+ slipdev_char_put(SLIP_ESC_ESC);\r
+ break;\r
+ default:\r
+ slipdev_char_put(c);\r
+ break;\r
+ }\r
+ }\r
+ slipdev_char_put(SLIP_END);\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+/** \r
+ * Poll the SLIP device for an available packet.\r
+ *\r
+ * This function will poll the SLIP device to see if a packet is\r
+ * available. It uses a buffer in which all avaliable bytes from the\r
+ * RS232 interface are read into. When a full packet has been read\r
+ * into the buffer, the packet is copied into the uip_buf buffer and\r
+ * the length of the packet is returned.\r
+ *\r
+ * \return The length of the packet placed in the uip_buf buffer, or\r
+ * zero if no packet is available.\r
+ */\r
+/*-----------------------------------------------------------------------------------*/\r
+u16_t\r
+slipdev_poll(void)\r
+{\r
+ u8_t c;\r
+ \r
+ while(slipdev_char_poll(c)) {\r
+ switch(c) {\r
+ case SLIP_ESC:\r
+ lastc = c;\r
+ break;\r
+ \r
+ case SLIP_END:\r
+ lastc = c;\r
+ /* End marker found, we copy our input buffer to the uip_buf\r
+ buffer and return the size of the packet we copied. */\r
+ memcpy(uip_buf, slip_buf, len);\r
+ tmplen = len;\r
+ len = 0;\r
+ return tmplen;\r
+ \r
+ default: \r
+ if(lastc == SLIP_ESC) {\r
+ lastc = c;\r
+ /* Previous read byte was an escape byte, so this byte will be\r
+ interpreted differently from others. */\r
+ switch(c) {\r
+ case SLIP_ESC_END:\r
+ c = SLIP_END;\r
+ break;\r
+ case SLIP_ESC_ESC:\r
+ c = SLIP_ESC;\r
+ break;\r
+ }\r
+ } else {\r
+ lastc = c;\r
+ }\r
+ \r
+ slip_buf[len] = c;\r
+ ++len;\r
+ \r
+ if(len > UIP_BUFSIZE) {\r
+ len = 0;\r
+ }\r
+ \r
+ break;\r
+ }\r
+ }\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+/**\r
+ * Initialize the SLIP module.\r
+ *\r
+ * This function does not initialize the underlying RS232 device, but\r
+ * only the SLIP part.\r
+ */ \r
+/*-----------------------------------------------------------------------------------*/\r
+void\r
+slipdev_init(void)\r
+{\r
+ lastc = len = 0;\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+\r
+/** @} */\r
+/** @} */\r
--- /dev/null
+/**\r
+ * \addtogroup slip\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * SLIP header file.\r
+ * \author Adam Dunkels <adam@dunkels.com>\r
+ */\r
+\r
+/*\r
+ * Copyright (c) 2001, Adam Dunkels.\r
+ * All rights reserved. \r
+ *\r
+ * Redistribution and use in source and binary forms, with or without \r
+ * modification, are permitted provided that the following conditions \r
+ * are met: \r
+ * 1. Redistributions of source code must retain the above copyright \r
+ * notice, this list of conditions and the following disclaimer. \r
+ * 2. Redistributions in binary form must reproduce the above copyright \r
+ * notice, this list of conditions and the following disclaimer in the \r
+ * documentation and/or other materials provided with the distribution. \r
+ * 3. The name of the author may not be used to endorse or promote\r
+ * products derived from this software without specific prior\r
+ * written permission. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * $Id: slipdev.h,v 1.1.2.3 2003/10/06 22:42:51 adam Exp $\r
+ *\r
+ */\r
+\r
+#ifndef __SLIPDEV_H__\r
+#define __SLIPDEV_H__\r
+\r
+#include "uip.h"\r
+\r
+/**\r
+ * Put a character on the serial device.\r
+ *\r
+ * This function is used by the SLIP implementation to put a character\r
+ * on the serial device. It must be implemented specifically for the\r
+ * system on which the SLIP implementation is to be run.\r
+ *\r
+ * \param c The character to be put on the serial device.\r
+ */\r
+void slipdev_char_put(u8_t c);\r
+\r
+/**\r
+ * Poll the serial device for a character.\r
+ *\r
+ * This function is used by the SLIP implementation to poll the serial\r
+ * device for a character. It must be implemented specifically for the\r
+ * system on which the SLIP implementation is to be run.\r
+ *\r
+ * The function should return immediately regardless if a character is\r
+ * available or not. If a character is available it should be placed\r
+ * at the memory location pointed to by the pointer supplied by the\r
+ * arguement c.\r
+ *\r
+ * \param c A pointer to a byte that is filled in by the function with\r
+ * the received character, if available.\r
+ *\r
+ * \retval 0 If no character is available.\r
+ * \retval Non-zero If a character is available.\r
+ */\r
+u8_t slipdev_char_poll(u8_t *c);\r
+\r
+void slipdev_init(void);\r
+void slipdev_send(void);\r
+u16_t slipdev_poll(void);\r
+\r
+#endif /* __SLIPDEV_H__ */\r
+\r
+/** @} */\r
--- /dev/null
+/*\r
+ * Copyright (c) 2001, Swedish Institute of Computer Science.\r
+ * All rights reserved. \r
+ *\r
+ * Redistribution and use in source and binary forms, with or without \r
+ * modification, are permitted provided that the following conditions \r
+ * are met: \r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright \r
+ * notice, this list of conditions and the following disclaimer. \r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright \r
+ * notice, this list of conditions and the following disclaimer in the \r
+ * documentation and/or other materials provided with the distribution. \r
+ *\r
+ * 3. Neither the name of the Institute nor the names of its contributors \r
+ * may be used to endorse or promote products derived from this software \r
+ * without specific prior written permission. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND \r
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE \r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE \r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE \r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL \r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS \r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) \r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT \r
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY \r
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF \r
+ * SUCH DAMAGE. \r
+ *\r
+ * Author: Adam Dunkels <adam@sics.se>\r
+ *\r
+ * $Id: tapdev.c,v 1.7.2.1 2003/10/07 13:23:19 adam Exp $\r
+ */\r
+\r
+\r
+#include <fcntl.h>\r
+#include <stdlib.h>\r
+#include <stdio.h>\r
+#include <unistd.h>\r
+#include <string.h>\r
+#include <sys/ioctl.h>\r
+#include <sys/socket.h>\r
+#include <sys/types.h>\r
+#include <sys/time.h>\r
+#include <sys/uio.h>\r
+#include <sys/socket.h>\r
+\r
+#ifdef linux\r
+#include <sys/ioctl.h>\r
+#include <linux/if.h>\r
+#include <linux/if_tun.h>\r
+#define DEVTAP "/dev/net/tun"\r
+#else /* linux */\r
+#define DEVTAP "/dev/tap0"\r
+#endif /* linux */\r
+\r
+#include "uip.h"\r
+\r
+static int fd;\r
+\r
+static unsigned long lasttime;\r
+static struct timezone tz;\r
+\r
+/*-----------------------------------------------------------------------------------*/\r
+void\r
+tapdev_init(void)\r
+{\r
+ char buf[1024];\r
+ \r
+ fd = open(DEVTAP, O_RDWR);\r
+ if(fd == -1) {\r
+ perror("tapdev: tapdev_init: open");\r
+ exit(1);\r
+ }\r
+\r
+#ifdef linux\r
+ {\r
+ struct ifreq ifr;\r
+ memset(&ifr, 0, sizeof(ifr));\r
+ ifr.ifr_flags = IFF_TAP|IFF_NO_PI;\r
+ if (ioctl(fd, TUNSETIFF, (void *) &ifr) < 0) {\r
+ perror(buf);\r
+ exit(1);\r
+ }\r
+ }\r
+#endif /* Linux */\r
+\r
+ snprintf(buf, sizeof(buf), "ifconfig tap0 inet %d.%d.%d.%d",\r
+ UIP_DRIPADDR0, UIP_DRIPADDR1, UIP_DRIPADDR2, UIP_DRIPADDR3);\r
+ system(buf);\r
+\r
+ lasttime = 0;\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+unsigned int\r
+tapdev_read(void)\r
+{\r
+ fd_set fdset;\r
+ struct timeval tv, now;\r
+ int ret;\r
+ \r
+ if(lasttime >= 500000) {\r
+ lasttime = 0;\r
+ return 0;\r
+ }\r
+ \r
+ tv.tv_sec = 0;\r
+ tv.tv_usec = 500000 - lasttime;\r
+\r
+\r
+ FD_ZERO(&fdset);\r
+ FD_SET(fd, &fdset);\r
+\r
+ gettimeofday(&now, &tz); \r
+ ret = select(fd + 1, &fdset, NULL, NULL, &tv);\r
+ if(ret == 0) {\r
+ lasttime = 0; \r
+ return 0;\r
+ } \r
+ ret = read(fd, uip_buf, UIP_BUFSIZE); \r
+ if(ret == -1) {\r
+ perror("tap_dev: tapdev_read: read");\r
+ }\r
+ gettimeofday(&tv, &tz);\r
+ lasttime += (tv.tv_sec - now.tv_sec) * 1000000 + (tv.tv_usec - now.tv_usec);\r
+\r
+ return ret;\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+void\r
+tapdev_send(void)\r
+{\r
+ int ret;\r
+ struct iovec iov[2];\r
+ \r
+#ifdef linux\r
+ {\r
+ char tmpbuf[UIP_BUFSIZE];\r
+ int i;\r
+\r
+ for(i = 0; i < 40 + UIP_LLH_LEN; i++) {\r
+ tmpbuf[i] = uip_buf[i];\r
+ }\r
+ \r
+ for(; i < uip_len; i++) {\r
+ tmpbuf[i] = uip_appdata[i - 40 - UIP_LLH_LEN];\r
+ }\r
+ \r
+ ret = write(fd, tmpbuf, uip_len);\r
+ } \r
+#else \r
+\r
+ if(uip_len < 40 + UIP_LLH_LEN) {\r
+ ret = write(fd, uip_buf, uip_len + UIP_LLH_LEN);\r
+ } else {\r
+ iov[0].iov_base = uip_buf;\r
+ iov[0].iov_len = 40 + UIP_LLH_LEN;\r
+ iov[1].iov_base = (char *)uip_appdata;\r
+ iov[1].iov_len = uip_len - (40 + UIP_LLH_LEN); \r
+ \r
+ ret = writev(fd, iov, 2);\r
+ }\r
+#endif\r
+ if(ret == -1) {\r
+ perror("tap_dev: tapdev_send: writev");\r
+ exit(1);\r
+ }\r
+} \r
+/*-----------------------------------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * Copyright (c) 2001, Adam Dunkels.\r
+ * All rights reserved. \r
+ *\r
+ * Redistribution and use in source and binary forms, with or without \r
+ * modification, are permitted provided that the following conditions \r
+ * are met: \r
+ * 1. Redistributions of source code must retain the above copyright \r
+ * notice, this list of conditions and the following disclaimer. \r
+ * 2. Redistributions in binary form must reproduce the above copyright \r
+ * notice, this list of conditions and the following disclaimer in the \r
+ * documentation and/or other materials provided with the distribution. \r
+ * 3. The name of the author may not be used to endorse or promote\r
+ * products derived from this software without specific prior\r
+ * written permission. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * $Id: tapdev.h,v 1.1.2.1 2003/10/04 22:54:17 adam Exp $\r
+ *\r
+ */\r
+\r
+#ifndef __TAPDEV_H__\r
+#define __TAPDEV_H__\r
+\r
+void tapdev_init(void);\r
+unsigned int tapdev_read(void);\r
+void tapdev_send(void);\r
+\r
+#endif /* __TAPDEV_H__ */\r
--- /dev/null
+/**\r
+ * \addtogroup telnetd\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * An example telnet server shell\r
+ * \author Adam Dunkels <adam@dunkels.com>\r
+ */\r
+\r
+/*\r
+ * Copyright (c) 2003, Adam Dunkels.\r
+ * All rights reserved. \r
+ *\r
+ * Redistribution and use in source and binary forms, with or without \r
+ * modification, are permitted provided that the following conditions \r
+ * are met: \r
+ * 1. Redistributions of source code must retain the above copyright \r
+ * notice, this list of conditions and the following disclaimer. \r
+ * 2. Redistributions in binary form must reproduce the above copyright \r
+ * notice, this list of conditions and the following disclaimer in the \r
+ * documentation and/or other materials provided with the distribution. \r
+ * 3. The name of the author may not be used to endorse or promote\r
+ * products derived from this software without specific prior\r
+ * written permission. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \r
+ *\r
+ * This file is part of the Contiki desktop OS.\r
+ *\r
+ * $Id: telnetd-shell.c,v 1.1.2.1 2003/10/06 22:56:22 adam Exp $\r
+ *\r
+ */\r
+\r
+#include "uip.h"\r
+#include "telnetd.h"\r
+#include <string.h>\r
+\r
+struct ptentry {\r
+ char c;\r
+ void (* pfunc)(struct telnetd_state *s, char *str);\r
+};\r
+\r
+/*-----------------------------------------------------------------------------------*/\r
+static void\r
+parse(struct telnetd_state *s, register char *str, struct ptentry *t)\r
+{\r
+ register struct ptentry *p;\r
+ char *sstr;\r
+\r
+ sstr = str;\r
+ \r
+ /* Loop over the parse table entries in t in order to find one that\r
+ matches the first character in str. */\r
+ for(p = t; p->c != 0; ++p) {\r
+ if(*str == p->c) {\r
+ /* Skip rest of the characters up to the first space. */\r
+ while(*str != ' ') {\r
+ ++str;\r
+ }\r
+\r
+ /* Skip all spaces.*/\r
+ while(*str == ' ') {\r
+ ++str;\r
+ }\r
+\r
+ /* Call parse table entry function and return. */\r
+ p->pfunc(s, str);\r
+ return;\r
+ }\r
+ }\r
+\r
+ /* Did not find matching entry in parse table. We just call the\r
+ default handler supplied by the caller and return. */\r
+ p->pfunc(s, str);\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+static void\r
+exitt(struct telnetd_state *s, char *str)\r
+{\r
+ telnetd_close(s);\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+static void\r
+inttostr(register char *str, unsigned int i)\r
+{\r
+ str[0] = '0' + i / 100;\r
+ if(str[0] == '0') {\r
+ str[0] = ' ';\r
+ }\r
+ str[1] = '0' + (i / 10) % 10;\r
+ if(str[1] == '0') {\r
+ str[1] = ' ';\r
+ }\r
+ str[2] = '0' + i % 10;\r
+ str[3] = ' ';\r
+ str[4] = 0;\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+static void\r
+stats(struct telnetd_state *s, char *strr)\r
+{\r
+ char str[10];\r
+\r
+ inttostr(str, uip_stat.ip.recv);\r
+ telnetd_output(s, "IP packets received ", str);\r
+ inttostr(str, uip_stat.ip.sent);\r
+ telnetd_output(s, "IP packets sent ", str);\r
+ inttostr(str, uip_stat.ip.drop);\r
+ telnetd_output(s, "IP packets dropped ", str);\r
+\r
+ inttostr(str, uip_stat.icmp.recv);\r
+ telnetd_output(s, "ICMP packets received ", str);\r
+ inttostr(str, uip_stat.icmp.sent);\r
+ telnetd_output(s, "ICMP packets sent ", str);\r
+ inttostr(str, uip_stat.icmp.drop);\r
+ telnetd_output(s, "ICMP packets dropped ", str);\r
+\r
+ inttostr(str, uip_stat.tcp.recv);\r
+ telnetd_output(s, "TCP packets received ", str);\r
+ inttostr(str, uip_stat.tcp.sent);\r
+ telnetd_output(s, "TCP packets sent ", str);\r
+ inttostr(str, uip_stat.tcp.drop);\r
+ telnetd_output(s, "TCP packets dropped ", str);\r
+ inttostr(str, uip_stat.tcp.rexmit);\r
+ telnetd_output(s, "TCP packets retransmitted ", str);\r
+ inttostr(str, uip_stat.tcp.synrst);\r
+ telnetd_output(s, "TCP connection attempts ", str);\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+static void\r
+help(struct telnetd_state *s, char *str)\r
+{\r
+ telnetd_output(s, "Available commands:", "");\r
+ telnetd_output(s, "stats - show uIP statistics", "");\r
+ telnetd_output(s, "exit - exit shell", ""); \r
+ telnetd_output(s, "? - show this help", ""); \r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+static void\r
+none(struct telnetd_state *s, char *str)\r
+{\r
+ if(strlen(str) > 0) {\r
+ telnetd_output(s, "Unknown command", "");\r
+ }\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+static struct ptentry configparsetab[] =\r
+ {{'s', stats},\r
+ {'e', exitt},\r
+ {'?', help},\r
+\r
+ /* Default action */\r
+ {0, none}};\r
+/*-----------------------------------------------------------------------------------*/\r
+void\r
+telnetd_connected(struct telnetd_state *s)\r
+{\r
+ telnetd_output(s, "uIP command shell", "");\r
+ telnetd_output(s, "Type '?' for help", ""); \r
+ telnetd_prompt(s, "uIP-0.9> "); \r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+void\r
+telnetd_input(struct telnetd_state *s, char *cmd)\r
+{\r
+ parse(s, cmd, configparsetab);\r
+ telnetd_prompt(s, "uIP-0.9> "); \r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
--- /dev/null
+/**\r
+ * \addtogroup exampleapps\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \defgroup telnetd Telnet server\r
+ * @{\r
+ *\r
+ * The uIP telnet server provides a command based interface to uIP. It\r
+ * allows using the "telnet" application to access uIP, and implements\r
+ * the required telnet option negotiation.\r
+ *\r
+ * The code is structured in a way which makes it possible to add\r
+ * commands without having to rewrite the main telnet code. The main\r
+ * telnet code calls two callback functions, telnetd_connected() and\r
+ * telnetd_input(), when a telnet connection has been established and\r
+ * when a line of text arrives on a telnet connection. These two\r
+ * functions can be implemented in a way which suits the particular\r
+ * application or environment in which the uIP system is intended to\r
+ * be run.\r
+ *\r
+ * The uIP distribution contains an example telnet shell\r
+ * implementation that provides a basic set of commands.\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * Implementation of the Telnet server.\r
+ * \author Adam Dunkels <adam@dunkels.com>\r
+ */\r
+\r
+/*\r
+ * Copyright (c) 2003, Adam Dunkels.\r
+ * All rights reserved. \r
+ *\r
+ * Redistribution and use in source and binary forms, with or without \r
+ * modification, are permitted provided that the following conditions \r
+ * are met: \r
+ * 1. Redistributions of source code must retain the above copyright \r
+ * notice, this list of conditions and the following disclaimer. \r
+ * 2. Redistributions in binary form must reproduce the above copyright \r
+ * notice, this list of conditions and the following disclaimer in the \r
+ * documentation and/or other materials provided with the distribution. \r
+ * 3. The name of the author may not be used to endorse or promote\r
+ * products derived from this software without specific prior\r
+ * written permission. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * $Id: telnetd.c,v 1.1.2.2 2003/10/07 13:47:50 adam Exp $\r
+ *\r
+ */\r
+\r
+#include "uip.h"\r
+#include "memb.h"\r
+#include "telnetd.h"\r
+#include <string.h>\r
+\r
+#define ISO_nl 0x0a\r
+#define ISO_cr 0x0d\r
+\r
+MEMB(linemem, TELNETD_LINELEN, TELNETD_NUMLINES);\r
+\r
+static u8_t i;\r
+\r
+#define STATE_NORMAL 0\r
+#define STATE_IAC 1\r
+#define STATE_WILL 2\r
+#define STATE_WONT 3\r
+#define STATE_DO 4 \r
+#define STATE_DONT 5\r
+#define STATE_CLOSE 6\r
+\r
+#define TELNET_IAC 255\r
+#define TELNET_WILL 251\r
+#define TELNET_WONT 252\r
+#define TELNET_DO 253\r
+#define TELNET_DONT 254\r
+/*-----------------------------------------------------------------------------------*/\r
+static char *\r
+alloc_line(void)\r
+{ \r
+ return memb_alloc(&linemem);\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+static void\r
+dealloc_line(char *line)\r
+{\r
+ memb_free(&linemem, line);\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+static void\r
+sendline(struct telnetd_state *s, char *line)\r
+{\r
+ static unsigned int i;\r
+ for(i = 0; i < TELNETD_NUMLINES; ++i) {\r
+ if(s->lines[i] == NULL) {\r
+ s->lines[i] = line;\r
+ break;\r
+ }\r
+ }\r
+ if(i == TELNETD_NUMLINES) {\r
+ dealloc_line(line);\r
+ }\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+/**\r
+ * Close a telnet session.\r
+ *\r
+ * This function can be called from a telnet command in order to close\r
+ * the connection.\r
+ *\r
+ * \param s The connection which is to be closed.\r
+ *\r
+ */\r
+/*-----------------------------------------------------------------------------------*/\r
+void\r
+telnetd_close(struct telnetd_state *s)\r
+{\r
+ s->state = STATE_CLOSE;\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+/**\r
+ * Print a prompt on a telnet connection.\r
+ *\r
+ * This function can be called by the telnet command shell in order to\r
+ * print out a command prompt.\r
+ *\r
+ * \param s A telnet connection.\r
+ *\r
+ * \param str The command prompt.\r
+ *\r
+ */\r
+/*-----------------------------------------------------------------------------------*/\r
+void\r
+telnetd_prompt(struct telnetd_state *s, char *str)\r
+{\r
+ char *line;\r
+ line = alloc_line();\r
+ if(line != NULL) {\r
+ strncpy(line, str, TELNETD_LINELEN);\r
+ sendline(s, line);\r
+ } \r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+/**\r
+ * Print out a string on a telnet connection.\r
+ *\r
+ * This function can be called from a telnet command parser in order\r
+ * to print out a string of text on the connection. The two strings\r
+ * given as arguments to the function will be concatenated, a carrige\r
+ * return and a new line character will be added, and the line is\r
+ * sent.\r
+ *\r
+ * \param s The telnet connection.\r
+ *\r
+ * \param str1 The first string.\r
+ *\r
+ * \param str2 The second string.\r
+ *\r
+ */\r
+/*-----------------------------------------------------------------------------------*/\r
+void\r
+telnetd_output(struct telnetd_state *s, char *str1, char *str2)\r
+{\r
+ static unsigned len;\r
+ char *line;\r
+ \r
+ line = alloc_line();\r
+ if(line != NULL) {\r
+ len = strlen(str1);\r
+ strncpy(line, str1, TELNETD_LINELEN);\r
+ if(len < TELNETD_LINELEN) {\r
+ strncpy(line + len, str2, TELNETD_LINELEN - len);\r
+ }\r
+ len = strlen(line);\r
+ if(len < TELNETD_LINELEN - 2) {\r
+ line[len] = ISO_cr;\r
+ line[len+1] = ISO_nl;\r
+ line[len+2] = 0;\r
+ }\r
+ sendline(s, line);\r
+ }\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+/**\r
+ * Initialize the telnet server.\r
+ *\r
+ * This function will perform the necessary initializations and start\r
+ * listening on TCP port 23.\r
+ */\r
+/*-----------------------------------------------------------------------------------*/\r
+void\r
+telnetd_init(void)\r
+{\r
+ memb_init(&linemem);\r
+ uip_listen(HTONS(23));\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+static void\r
+acked(struct telnetd_state *s) \r
+{\r
+ dealloc_line(s->lines[0]);\r
+ for(i = 1; i < TELNETD_NUMLINES; ++i) {\r
+ s->lines[i - 1] = s->lines[i];\r
+ }\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+static void\r
+senddata(struct telnetd_state *s) \r
+{\r
+ if(s->lines[0] != NULL) {\r
+ uip_send(s->lines[0], strlen(s->lines[0]));\r
+ }\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+static void\r
+getchar(struct telnetd_state *s, u8_t c)\r
+{\r
+ if(c == ISO_cr) {\r
+ return;\r
+ }\r
+ \r
+ s->buf[(int)s->bufptr] = c; \r
+ if(s->buf[(int)s->bufptr] == ISO_nl ||\r
+ s->bufptr == sizeof(s->buf) - 1) { \r
+ if(s->bufptr > 0) {\r
+ s->buf[(int)s->bufptr] = 0;\r
+ }\r
+ telnetd_input(s, s->buf);\r
+ s->bufptr = 0;\r
+ } else {\r
+ ++s->bufptr;\r
+ }\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+static void\r
+sendopt(struct telnetd_state *s, u8_t option, u8_t value)\r
+{\r
+ char *line;\r
+ line = alloc_line();\r
+ if(line != NULL) {\r
+ line[0] = TELNET_IAC;\r
+ line[1] = option;\r
+ line[2] = value;\r
+ line[3] = 0;\r
+ sendline(s, line);\r
+ } \r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+static void\r
+newdata(struct telnetd_state *s)\r
+{\r
+ u16_t len;\r
+ u8_t c;\r
+ \r
+ \r
+ len = uip_datalen();\r
+ \r
+ while(len > 0 && s->bufptr < sizeof(s->buf)) {\r
+ c = *uip_appdata;\r
+ ++uip_appdata;\r
+ --len;\r
+ switch(s->state) {\r
+ case STATE_IAC:\r
+ if(c == TELNET_IAC) {\r
+ getchar(s, c);\r
+ s->state = STATE_NORMAL;\r
+ } else {\r
+ switch(c) {\r
+ case TELNET_WILL:\r
+ s->state = STATE_WILL;\r
+ break;\r
+ case TELNET_WONT:\r
+ s->state = STATE_WONT;\r
+ break;\r
+ case TELNET_DO:\r
+ s->state = STATE_DO;\r
+ break;\r
+ case TELNET_DONT:\r
+ s->state = STATE_DONT;\r
+ break;\r
+ default:\r
+ s->state = STATE_NORMAL;\r
+ break;\r
+ }\r
+ }\r
+ break;\r
+ case STATE_WILL:\r
+ /* Reply with a DONT */\r
+ sendopt(s, TELNET_DONT, c);\r
+ s->state = STATE_NORMAL;\r
+ break;\r
+ \r
+ case STATE_WONT:\r
+ /* Reply with a DONT */\r
+ sendopt(s, TELNET_DONT, c);\r
+ s->state = STATE_NORMAL;\r
+ break;\r
+ case STATE_DO:\r
+ /* Reply with a WONT */\r
+ sendopt(s, TELNET_WONT, c);\r
+ s->state = STATE_NORMAL;\r
+ break;\r
+ case STATE_DONT:\r
+ /* Reply with a WONT */\r
+ sendopt(s, TELNET_WONT, c);\r
+ s->state = STATE_NORMAL;\r
+ break;\r
+ case STATE_NORMAL:\r
+ if(c == TELNET_IAC) {\r
+ s->state = STATE_IAC;\r
+ } else {\r
+ getchar(s, c);\r
+ } \r
+ break;\r
+ } \r
+\r
+ \r
+ } \r
+ \r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+void\r
+telnetd_app(void)\r
+{\r
+ struct telnetd_state *s;\r
+\r
+ s = (struct telnetd_state *)uip_conn->appstate;\r
+ \r
+ if(uip_connected()) {\r
+\r
+ for(i = 0; i < TELNETD_NUMLINES; ++i) {\r
+ s->lines[i] = NULL;\r
+ }\r
+ s->bufptr = 0;\r
+ s->state = STATE_NORMAL;\r
+\r
+ telnetd_connected(s);\r
+ senddata(s);\r
+ return;\r
+ }\r
+\r
+ if(s->state == STATE_CLOSE) {\r
+ s->state = STATE_NORMAL;\r
+ uip_close();\r
+ return;\r
+ }\r
+ \r
+ if(uip_closed()) {\r
+ telnetd_output(s, "Connection closed", "");\r
+ }\r
+\r
+ \r
+ if(uip_aborted()) {\r
+ telnetd_output(s, "Connection reset", "");\r
+ }\r
+ \r
+ if(uip_timedout()) {\r
+ telnetd_output(s, "Connection timed out", "");\r
+ }\r
+ \r
+ if(uip_acked()) {\r
+ acked(s);\r
+ }\r
+ \r
+ if(uip_newdata()) {\r
+ newdata(s);\r
+ }\r
+ \r
+ if(uip_rexmit() ||\r
+ uip_newdata() ||\r
+ uip_acked()) {\r
+ senddata(s);\r
+ } else if(uip_poll()) { \r
+ senddata(s);\r
+ }\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
--- /dev/null
+/**\r
+ * \addtogroup telnetd\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * Header file for the telnet server.\r
+ * \author Adam Dunkels <adam@dunkels.com>\r
+ */\r
+\r
+/*\r
+ * Copyright (c) 2002, Adam Dunkels.\r
+ * All rights reserved. \r
+ *\r
+ * Redistribution and use in source and binary forms, with or without \r
+ * modification, are permitted provided that the following conditions \r
+ * are met: \r
+ * 1. Redistributions of source code must retain the above copyright \r
+ * notice, this list of conditions and the following disclaimer. \r
+ * 2. Redistributions in binary form must reproduce the above copyright \r
+ * notice, this list of conditions and the following disclaimer in the \r
+ * documentation and/or other materials provided with the distribution. \r
+ * 3. The name of the author may not be used to endorse or promote\r
+ * products derived from this software without specific prior\r
+ * written permission. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * $Id: telnetd.h,v 1.1.2.2 2003/10/07 13:22:27 adam Exp $\r
+ *\r
+ */\r
+#ifndef __TELNETD_H__\r
+#define __TELNETD_H__\r
+\r
+#include "uip.h"\r
+\r
+/**\r
+ * The maximum length of a telnet line.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define TELNETD_LINELEN 36\r
+\r
+/**\r
+ * The number of output lines being buffered for all telnet\r
+ * connections.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define TELNETD_NUMLINES 2\r
+\r
+/**\r
+ * A telnet connection structure.\r
+ */\r
+struct telnetd_state {\r
+ char *lines[TELNETD_NUMLINES];\r
+ char buf[TELNETD_LINELEN];\r
+ char bufptr;\r
+ u8_t state;\r
+};\r
+\r
+\r
+/**\r
+ * Callback function that is called when a telnet connection has been\r
+ * established.\r
+ *\r
+ * \param s The telnet connection. \r
+ */\r
+void telnetd_connected(struct telnetd_state *s);\r
+\r
+/**\r
+ * Callback function that is called when a line of text has arrived on\r
+ * a telnet connection.\r
+ *\r
+ * \param s The telnet connection.\r
+ *\r
+ * \param cmd The line of text.\r
+ */\r
+void telnetd_input(struct telnetd_state *s, char *cmd);\r
+\r
+\r
+void telnetd_close(struct telnetd_state *s);\r
+void telnetd_output(struct telnetd_state *s, char *s1, char *s2);\r
+void telnetd_prompt(struct telnetd_state *s, char *str);\r
+\r
+void telnetd_app(void);\r
+\r
+#ifndef UIP_APPCALL\r
+#define UIP_APPCALL telnetd_app\r
+#endif\r
+\r
+#ifndef UIP_APPSTATE_SIZE\r
+#define UIP_APPSTATE_SIZE (sizeof(struct telnetd_state))\r
+#endif\r
+\r
+void telnetd_init(void);\r
+\r
+\r
+#endif /* __TELNET_H__ */\r
+\r
+/** @} */\r
--- /dev/null
+/**\r
+ * \addtogroup uip\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * The uIP TCP/IP stack code.\r
+ * \author Adam Dunkels <adam@dunkels.com>\r
+ */\r
+\r
+/*\r
+ * Copyright (c) 2001-2003, Adam Dunkels.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ * 3. The name of the author may not be used to endorse or promote\r
+ * products derived from this software without specific prior\r
+ * written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * $Id: uip.c,v 1.62.2.10 2003/10/07 13:23:01 adam Exp $\r
+ *\r
+ */\r
+\r
+/*\r
+This is a small implementation of the IP and TCP protocols (as well as\r
+some basic ICMP stuff). The implementation couples the IP, TCP and the\r
+application layers very tightly. To keep the size of the compiled code\r
+down, this code also features heavy usage of the goto statement.\r
+\r
+The principle is that we have a small buffer, called the uip_buf, in\r
+which the device driver puts an incoming packet. The TCP/IP stack\r
+parses the headers in the packet, and calls upon the application. If\r
+the remote host has sent data to the application, this data is present\r
+in the uip_buf and the application read the data from there. It is up\r
+to the application to put this data into a byte stream if needed. The\r
+application will not be fed with data that is out of sequence.\r
+\r
+If the application whishes to send data to the peer, it should put its\r
+data into the uip_buf, 40 bytes from the start of the buffer. The\r
+TCP/IP stack will calculate the checksums, and fill in the necessary\r
+header fields and finally send the packet back to the peer.\r
+*/\r
+\r
+#include "uip.h"\r
+#include "uipopt.h"\r
+#include "uip_arch.h"\r
+\r
+/*-----------------------------------------------------------------------------------*/\r
+/* Variable definitions. */\r
+\r
+\r
+/* The IP address of this host. If it is defined to be fixed (by setting UIP_FIXEDADDR to 1 in uipopt.h), the address is set here. Otherwise, the address */\r
+#if UIP_FIXEDADDR > 0\r
+const u16_t uip_hostaddr[2] =\r
+ {HTONS((UIP_IPADDR0 << 8) | UIP_IPADDR1),\r
+ HTONS((UIP_IPADDR2 << 8) | UIP_IPADDR3)};\r
+const u16_t uip_arp_draddr[2] =\r
+ {HTONS((UIP_DRIPADDR0 << 8) | UIP_DRIPADDR1),\r
+ HTONS((UIP_DRIPADDR2 << 8) | UIP_DRIPADDR3)};\r
+const u16_t uip_arp_netmask[2] =\r
+ {HTONS((UIP_NETMASK0 << 8) | UIP_NETMASK1),\r
+ HTONS((UIP_NETMASK2 << 8) | UIP_NETMASK3)};\r
+#else\r
+u16_t uip_hostaddr[2];\r
+u16_t uip_arp_draddr[2], uip_arp_netmask[2];\r
+#endif /* UIP_FIXEDADDR */\r
+\r
+u8_t uip_buf[UIP_BUFSIZE+2]; /* The packet buffer that contains\r
+ incoming packets. */\r
+volatile u8_t *uip_appdata; /* The uip_appdata pointer points to\r
+ application data. */\r
+volatile u8_t *uip_sappdata; /* The uip_appdata pointer points to the\r
+ application data which is to be sent. */\r
+#if UIP_URGDATA > 0\r
+volatile u8_t *uip_urgdata; /* The uip_urgdata pointer points to\r
+ urgent data (out-of-band data), if\r
+ present. */\r
+volatile u8_t uip_urglen, uip_surglen;\r
+#endif /* UIP_URGDATA > 0 */\r
+\r
+volatile u16_t uip_len, uip_slen;\r
+ /* The uip_len is either 8 or 16 bits,\r
+ depending on the maximum packet\r
+ size. */\r
+\r
+volatile u8_t uip_flags; /* The uip_flags variable is used for\r
+ communication between the TCP/IP stack\r
+ and the application program. */\r
+struct uip_conn *uip_conn; /* uip_conn always points to the current\r
+ connection. */\r
+\r
+struct uip_conn uip_conns[UIP_CONNS];\r
+ /* The uip_conns array holds all TCP\r
+ connections. */\r
+u16_t uip_listenports[UIP_LISTENPORTS];\r
+ /* The uip_listenports list all currently\r
+ listning ports. */\r
+#if UIP_UDP\r
+struct uip_udp_conn *uip_udp_conn;\r
+struct uip_udp_conn uip_udp_conns[UIP_UDP_CONNS];\r
+#endif /* UIP_UDP */\r
+\r
+\r
+static u16_t ipid; /* Ths ipid variable is an increasing\r
+ number that is used for the IP ID\r
+ field. */\r
+\r
+static u8_t iss[4]; /* The iss variable is used for the TCP\r
+ initial sequence number. */\r
+\r
+#if UIP_ACTIVE_OPEN\r
+static u16_t lastport; /* Keeps track of the last port used for\r
+ a new connection. */\r
+#endif /* UIP_ACTIVE_OPEN */\r
+\r
+/* Temporary variables. */\r
+volatile u8_t uip_acc32[4];\r
+static u8_t c, opt;\r
+static u16_t tmp16;\r
+\r
+/* Structures and definitions. */\r
+#define TCP_FIN 0x01\r
+#define TCP_SYN 0x02\r
+#define TCP_RST 0x04\r
+#define TCP_PSH 0x08\r
+#define TCP_ACK 0x10\r
+#define TCP_URG 0x20\r
+#define TCP_CTL 0x3f\r
+\r
+#define ICMP_ECHO_REPLY 0\r
+#define ICMP_ECHO 8\r
+\r
+/* Macros. */\r
+#define BUF ((uip_tcpip_hdr *)&uip_buf[UIP_LLH_LEN])\r
+#define FBUF ((uip_tcpip_hdr *)&uip_reassbuf[0])\r
+#define ICMPBUF ((uip_icmpip_hdr *)&uip_buf[UIP_LLH_LEN])\r
+#define UDPBUF ((uip_udpip_hdr *)&uip_buf[UIP_LLH_LEN])\r
+\r
+#if UIP_STATISTICS == 1\r
+struct uip_stats uip_stat;\r
+#define UIP_STAT(s) s\r
+#else\r
+#define UIP_STAT(s)\r
+#endif /* UIP_STATISTICS == 1 */\r
+\r
+#if UIP_LOGGING == 1\r
+#include <stdio.h>\r
+void uip_log(char *msg);\r
+#define UIP_LOG(m) uip_log(m)\r
+#else\r
+#define UIP_LOG(m)\r
+#endif /* UIP_LOGGING == 1 */\r
+\r
+/*-----------------------------------------------------------------------------------*/\r
+void\r
+uip_init(void)\r
+{\r
+ for(c = 0; c < UIP_LISTENPORTS; ++c) {\r
+ uip_listenports[c] = 0;\r
+ }\r
+ for(c = 0; c < UIP_CONNS; ++c) {\r
+ uip_conns[c].tcpstateflags = CLOSED;\r
+ }\r
+#if UIP_ACTIVE_OPEN\r
+ lastport = 1024;\r
+#endif /* UIP_ACTIVE_OPEN */\r
+\r
+#if UIP_UDP\r
+ for(c = 0; c < UIP_UDP_CONNS; ++c) {\r
+ uip_udp_conns[c].lport = 0;\r
+ }\r
+#endif /* UIP_UDP */\r
+\r
+\r
+ /* IPv4 initialization. */\r
+#if UIP_FIXEDADDR == 0\r
+ uip_hostaddr[0] = uip_hostaddr[1] = 0;\r
+#endif /* UIP_FIXEDADDR */\r
+\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+#if UIP_ACTIVE_OPEN\r
+struct uip_conn *\r
+uip_connect(u16_t *ripaddr, u16_t rport)\r
+{\r
+ register struct uip_conn *conn, *cconn;\r
+\r
+ /* Find an unused local port. */\r
+ again:\r
+ ++lastport;\r
+\r
+ if(lastport >= 32000) {\r
+ lastport = 4096;\r
+ }\r
+\r
+ /* Check if this port is already in use, and if so try to find\r
+ another one. */\r
+ for(c = 0; c < UIP_CONNS; ++c) {\r
+ conn = &uip_conns[c];\r
+ if(conn->tcpstateflags != CLOSED &&\r
+ conn->lport == htons(lastport)) {\r
+ goto again;\r
+ }\r
+ }\r
+\r
+\r
+ conn = 0;\r
+ for(c = 0; c < UIP_CONNS; ++c) {\r
+ cconn = &uip_conns[c];\r
+ if(cconn->tcpstateflags == CLOSED) {\r
+ conn = cconn;\r
+ break;\r
+ }\r
+ if(cconn->tcpstateflags == TIME_WAIT) {\r
+ if(conn == 0 ||\r
+ cconn->timer > uip_conn->timer) {\r
+ conn = cconn;\r
+ }\r
+ }\r
+ }\r
+\r
+ if(conn == 0) {\r
+ return 0;\r
+ }\r
+\r
+ conn->tcpstateflags = SYN_SENT;\r
+\r
+ conn->snd_nxt[0] = iss[0];\r
+ conn->snd_nxt[1] = iss[1];\r
+ conn->snd_nxt[2] = iss[2];\r
+ conn->snd_nxt[3] = iss[3];\r
+\r
+ conn->initialmss = conn->mss = UIP_TCP_MSS;\r
+\r
+ conn->len = 1; /* TCP length of the SYN is one. */\r
+ conn->nrtx = 0;\r
+ conn->timer = 1; /* Send the SYN next time around. */\r
+ conn->rto = UIP_RTO;\r
+ conn->sa = 0;\r
+ conn->sv = 16;\r
+ conn->lport = htons(lastport);\r
+ conn->rport = rport;\r
+ conn->ripaddr[0] = ripaddr[0];\r
+ conn->ripaddr[1] = ripaddr[1];\r
+\r
+ return conn;\r
+}\r
+#endif /* UIP_ACTIVE_OPEN */\r
+/*-----------------------------------------------------------------------------------*/\r
+#if UIP_UDP\r
+struct uip_udp_conn *\r
+uip_udp_new(u16_t *ripaddr, u16_t rport)\r
+{\r
+ register struct uip_udp_conn *conn;\r
+\r
+ /* Find an unused local port. */\r
+ again:\r
+ ++lastport;\r
+\r
+ if(lastport >= 32000) {\r
+ lastport = 4096;\r
+ }\r
+\r
+ for(c = 0; c < UIP_UDP_CONNS; ++c) {\r
+ if(uip_udp_conns[c].lport == lastport) {\r
+ goto again;\r
+ }\r
+ }\r
+\r
+\r
+ conn = 0;\r
+ for(c = 0; c < UIP_UDP_CONNS; ++c) {\r
+ if(uip_udp_conns[c].lport == 0) {\r
+ conn = &uip_udp_conns[c];\r
+ break;\r
+ }\r
+ }\r
+\r
+ if(conn == 0) {\r
+ return 0;\r
+ }\r
+\r
+ conn->lport = HTONS(lastport);\r
+ conn->rport = HTONS(rport);\r
+ conn->ripaddr[0] = ripaddr[0];\r
+ conn->ripaddr[1] = ripaddr[1];\r
+\r
+ return conn;\r
+}\r
+#endif /* UIP_UDP */\r
+/*-----------------------------------------------------------------------------------*/\r
+void\r
+uip_unlisten(u16_t port)\r
+{\r
+ for(c = 0; c < UIP_LISTENPORTS; ++c) {\r
+ if(uip_listenports[c] == port) {\r
+ uip_listenports[c] = 0;\r
+ return;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+void\r
+uip_listen(u16_t port)\r
+{\r
+ for(c = 0; c < UIP_LISTENPORTS; ++c) {\r
+ if(uip_listenports[c] == 0) {\r
+ uip_listenports[c] = port;\r
+ return;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+/* XXX: IP fragment reassembly: not well-tested. */\r
+\r
+#if UIP_REASSEMBLY\r
+#define UIP_REASS_BUFSIZE (UIP_BUFSIZE - UIP_LLH_LEN)\r
+static u8_t uip_reassbuf[UIP_REASS_BUFSIZE];\r
+static u8_t uip_reassbitmap[UIP_REASS_BUFSIZE / (8 * 8)];\r
+static const u8_t bitmap_bits[8] = {0xff, 0x7f, 0x3f, 0x1f,\r
+ 0x0f, 0x07, 0x03, 0x01};\r
+static u16_t uip_reasslen;\r
+static u8_t uip_reassflags;\r
+#define UIP_REASS_FLAG_LASTFRAG 0x01\r
+static u8_t uip_reasstmr;\r
+\r
+#define IP_HLEN 20\r
+#define IP_MF 0x20\r
+\r
+static u8_t\r
+uip_reass(void)\r
+{\r
+ u16_t offset, len;\r
+ u16_t i;\r
+\r
+ /* If ip_reasstmr is zero, no packet is present in the buffer, so we\r
+ write the IP header of the fragment into the reassembly\r
+ buffer. The timer is updated with the maximum age. */\r
+ if(uip_reasstmr == 0) {\r
+ memcpy(uip_reassbuf, &BUF->vhl, IP_HLEN);\r
+ uip_reasstmr = UIP_REASS_MAXAGE;\r
+ uip_reassflags = 0;\r
+ /* Clear the bitmap. */\r
+ memset(uip_reassbitmap, sizeof(uip_reassbitmap), 0);\r
+ }\r
+\r
+ /* Check if the incoming fragment matches the one currently present\r
+ in the reasembly buffer. If so, we proceed with copying the\r
+ fragment into the buffer. */\r
+ if(BUF->srcipaddr[0] == FBUF->srcipaddr[0] &&\r
+ BUF->srcipaddr[1] == FBUF->srcipaddr[1] &&\r
+ BUF->destipaddr[0] == FBUF->destipaddr[0] &&\r
+ BUF->destipaddr[1] == FBUF->destipaddr[1] &&\r
+ BUF->ipid[0] == FBUF->ipid[0] &&\r
+ BUF->ipid[1] == FBUF->ipid[1]) {\r
+\r
+ len = (BUF->len[0] << 8) + BUF->len[1] - (BUF->vhl & 0x0f) * 4;\r
+ offset = (((BUF->ipoffset[0] & 0x3f) << 8) + BUF->ipoffset[1]) * 8;\r
+\r
+ /* If the offset or the offset + fragment length overflows the\r
+ reassembly buffer, we discard the entire packet. */\r
+ if(offset > UIP_REASS_BUFSIZE ||\r
+ offset + len > UIP_REASS_BUFSIZE) {\r
+ uip_reasstmr = 0;\r
+ goto nullreturn;\r
+ }\r
+\r
+ /* Copy the fragment into the reassembly buffer, at the right\r
+ offset. */\r
+ memcpy(&uip_reassbuf[IP_HLEN + offset],\r
+ (char *)BUF + (int)((BUF->vhl & 0x0f) * 4),\r
+ len);\r
+\r
+ /* Update the bitmap. */\r
+ if(offset / (8 * 8) == (offset + len) / (8 * 8)) {\r
+ /* If the two endpoints are in the same byte, we only update\r
+ that byte. */\r
+ \r
+ uip_reassbitmap[offset / (8 * 8)] |=\r
+ bitmap_bits[(offset / 8 ) & 7] &\r
+ ~bitmap_bits[((offset + len) / 8 ) & 7];\r
+ } else {\r
+ /* If the two endpoints are in different bytes, we update the\r
+ bytes in the endpoints and fill the stuff inbetween with\r
+ 0xff. */\r
+ uip_reassbitmap[offset / (8 * 8)] |=\r
+ bitmap_bits[(offset / 8 ) & 7];\r
+ for(i = 1 + offset / (8 * 8); i < (offset + len) / (8 * 8); ++i) {\r
+ uip_reassbitmap[i] = 0xff;\r
+ }\r
+ uip_reassbitmap[(offset + len) / (8 * 8)] |=\r
+ ~bitmap_bits[((offset + len) / 8 ) & 7];\r
+ }\r
+\r
+ /* If this fragment has the More Fragments flag set to zero, we\r
+ know that this is the last fragment, so we can calculate the\r
+ size of the entire packet. We also set the\r
+ IP_REASS_FLAG_LASTFRAG flag to indicate that we have received\r
+ the final fragment. */\r
+\r
+ if((BUF->ipoffset[0] & IP_MF) == 0) {\r
+ uip_reassflags |= UIP_REASS_FLAG_LASTFRAG;\r
+ uip_reasslen = offset + len;\r
+ }\r
+\r
+ /* Finally, we check if we have a full packet in the buffer. We do\r
+ this by checking if we have the last fragment and if all bits\r
+ in the bitmap are set. */\r
+ if(uip_reassflags & UIP_REASS_FLAG_LASTFRAG) {\r
+ /* Check all bytes up to and including all but the last byte in\r
+ the bitmap. */\r
+ for(i = 0; i < uip_reasslen / (8 * 8) - 1; ++i) {\r
+ if(uip_reassbitmap[i] != 0xff) {\r
+ goto nullreturn;\r
+ }\r
+ }\r
+ /* Check the last byte in the bitmap. It should contain just the\r
+ right amount of bits. */\r
+ if(uip_reassbitmap[uip_reasslen / (8 * 8)] !=\r
+ (u8_t)~bitmap_bits[uip_reasslen / 8 & 7]) {\r
+ goto nullreturn;\r
+ }\r
+\r
+ /* If we have come this far, we have a full packet in the\r
+ buffer, so we allocate a pbuf and copy the packet into it. We\r
+ also reset the timer. */\r
+ uip_reasstmr = 0;\r
+ memcpy(BUF, FBUF, uip_reasslen);\r
+\r
+ /* Pretend to be a "normal" (i.e., not fragmented) IP packet\r
+ from now on. */\r
+ BUF->ipoffset[0] = BUF->ipoffset[1] = 0;\r
+ BUF->len[0] = uip_reasslen >> 8;\r
+ BUF->len[1] = uip_reasslen & 0xff;\r
+ BUF->ipchksum = 0;\r
+ BUF->ipchksum = ~(uip_ipchksum());\r
+\r
+ return uip_reasslen;\r
+ }\r
+ }\r
+\r
+ nullreturn:\r
+ return 0;\r
+}\r
+#endif /* UIP_REASSEMBL */\r
+/*-----------------------------------------------------------------------------------*/\r
+static void\r
+uip_add_rcv_nxt(u16_t n)\r
+{\r
+ uip_add32(uip_conn->rcv_nxt, n);\r
+ uip_conn->rcv_nxt[0] = uip_acc32[0];\r
+ uip_conn->rcv_nxt[1] = uip_acc32[1];\r
+ uip_conn->rcv_nxt[2] = uip_acc32[2];\r
+ uip_conn->rcv_nxt[3] = uip_acc32[3];\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+void\r
+uip_process(u8_t flag)\r
+{\r
+ register struct uip_conn *uip_connr = uip_conn;\r
+\r
+ uip_appdata = &uip_buf[40 + UIP_LLH_LEN];\r
+\r
+\r
+ /* Check if we were invoked because of the perodic timer fireing. */\r
+ if(flag == UIP_TIMER) {\r
+#if UIP_REASSEMBLY\r
+ if(uip_reasstmr != 0) {\r
+ --uip_reasstmr;\r
+ }\r
+#endif /* UIP_REASSEMBLY */\r
+ /* Increase the initial sequence number. */\r
+ if(++iss[3] == 0) {\r
+ if(++iss[2] == 0) {\r
+ if(++iss[1] == 0) {\r
+ ++iss[0];\r
+ }\r
+ }\r
+ }\r
+ uip_len = 0;\r
+ if(uip_connr->tcpstateflags == TIME_WAIT ||\r
+ uip_connr->tcpstateflags == FIN_WAIT_2) {\r
+ ++(uip_connr->timer);\r
+ if(uip_connr->timer == UIP_TIME_WAIT_TIMEOUT) {\r
+ uip_connr->tcpstateflags = CLOSED;\r
+ }\r
+ } else if(uip_connr->tcpstateflags != CLOSED) {\r
+ /* If the connection has outstanding data, we increase the\r
+ connection's timer and see if it has reached the RTO value\r
+ in which case we retransmit. */\r
+ if(uip_outstanding(uip_connr)) {\r
+ if(uip_connr->timer-- == 0) {\r
+ if(uip_connr->nrtx == UIP_MAXRTX ||\r
+ ((uip_connr->tcpstateflags == SYN_SENT ||\r
+ uip_connr->tcpstateflags == SYN_RCVD) &&\r
+ uip_connr->nrtx == UIP_MAXSYNRTX)) {\r
+ uip_connr->tcpstateflags = CLOSED;\r
+\r
+ /* We call UIP_APPCALL() with uip_flags set to\r
+ UIP_TIMEDOUT to inform the application that the\r
+ connection has timed out. */\r
+ uip_flags = UIP_TIMEDOUT;\r
+ UIP_APPCALL();\r
+\r
+ /* We also send a reset packet to the remote host. */\r
+ BUF->flags = TCP_RST | TCP_ACK;\r
+ goto tcp_send_nodata;\r
+ }\r
+\r
+ /* Exponential backoff. */\r
+ uip_connr->timer = UIP_RTO << (uip_connr->nrtx > 4?\r
+ 4:\r
+ uip_connr->nrtx);\r
+ ++(uip_connr->nrtx);\r
+ \r
+ /* Ok, so we need to retransmit. We do this differently\r
+ depending on which state we are in. In ESTABLISHED, we\r
+ call upon the application so that it may prepare the\r
+ data for the retransmit. In SYN_RCVD, we resend the\r
+ SYNACK that we sent earlier and in LAST_ACK we have to\r
+ retransmit our FINACK. */\r
+ UIP_STAT(++uip_stat.tcp.rexmit);\r
+ switch(uip_connr->tcpstateflags & TS_MASK) {\r
+ case SYN_RCVD:\r
+ /* In the SYN_RCVD state, we should retransmit our\r
+ SYNACK. */\r
+ goto tcp_send_synack;\r
+ \r
+#if UIP_ACTIVE_OPEN\r
+ case SYN_SENT:\r
+ /* In the SYN_SENT state, we retransmit out SYN. */\r
+ BUF->flags = 0;\r
+ goto tcp_send_syn;\r
+#endif /* UIP_ACTIVE_OPEN */\r
+ \r
+ case ESTABLISHED:\r
+ /* In the ESTABLISHED state, we call upon the application\r
+ to do the actual retransmit after which we jump into\r
+ the code for sending out the packet (the apprexmit\r
+ label). */\r
+ uip_len = 0;\r
+ uip_slen = 0;\r
+ uip_flags = UIP_REXMIT;\r
+ UIP_APPCALL();\r
+ goto apprexmit;\r
+ \r
+ case FIN_WAIT_1:\r
+ case CLOSING:\r
+ case LAST_ACK:\r
+ /* In all these states we should retransmit a FINACK. */\r
+ goto tcp_send_finack;\r
+ \r
+ }\r
+ }\r
+ } else if((uip_connr->tcpstateflags & TS_MASK) == ESTABLISHED) {\r
+ /* If there was no need for a retransmission, we poll the\r
+ application for new data. */\r
+ uip_len = 0;\r
+ uip_slen = 0;\r
+ uip_flags = UIP_POLL;\r
+ UIP_APPCALL();\r
+ goto appsend;\r
+ }\r
+ }\r
+ goto drop;\r
+ }\r
+#if UIP_UDP\r
+ if(flag == UIP_UDP_TIMER) {\r
+ if(uip_udp_conn->lport != 0) {\r
+ uip_appdata = &uip_buf[UIP_LLH_LEN + 28];\r
+ uip_len = uip_slen = 0;\r
+ uip_flags = UIP_POLL;\r
+ UIP_UDP_APPCALL();\r
+ goto udp_send;\r
+ } else {\r
+ goto drop;\r
+ }\r
+ }\r
+#endif\r
+\r
+ /* This is where the input processing starts. */\r
+ UIP_STAT(++uip_stat.ip.recv);\r
+\r
+\r
+ /* Start of IPv4 input header processing code. */\r
+\r
+ /* Check validity of the IP header. */\r
+ if(BUF->vhl != 0x45) { /* IP version and header length. */\r
+ UIP_STAT(++uip_stat.ip.drop);\r
+ UIP_STAT(++uip_stat.ip.vhlerr);\r
+ UIP_LOG("ip: invalid version or header length.");\r
+ goto drop;\r
+ }\r
+\r
+ /* Check the size of the packet. If the size reported to us in\r
+ uip_len doesn't match the size reported in the IP header, there\r
+ has been a transmission error and we drop the packet. */\r
+\r
+ if(BUF->len[0] != (uip_len >> 8)) { /* IP length, high byte. */\r
+ uip_len = (uip_len & 0xff) | (BUF->len[0] << 8);\r
+ }\r
+ if(BUF->len[1] != (uip_len & 0xff)) { /* IP length, low byte. */\r
+ uip_len = (uip_len & 0xff00) | BUF->len[1];\r
+ }\r
+\r
+ /* Check the fragment flag. */\r
+ if((BUF->ipoffset[0] & 0x3f) != 0 ||\r
+ BUF->ipoffset[1] != 0) {\r
+#if UIP_REASSEMBLY\r
+ uip_len = uip_reass();\r
+ if(uip_len == 0) {\r
+ goto drop;\r
+ }\r
+#else\r
+ UIP_STAT(++uip_stat.ip.drop);\r
+ UIP_STAT(++uip_stat.ip.fragerr);\r
+ UIP_LOG("ip: fragment dropped.");\r
+ goto drop;\r
+#endif /* UIP_REASSEMBLY */\r
+ }\r
+\r
+ /* If we are configured to use ping IP address configuration and\r
+ hasn't been assigned an IP address yet, we accept all ICMP\r
+ packets. */\r
+#if UIP_PINGADDRCONF\r
+ if((uip_hostaddr[0] | uip_hostaddr[1]) == 0) {\r
+ if(BUF->proto == UIP_PROTO_ICMP) {\r
+ UIP_LOG("ip: possible ping config packet received.");\r
+ goto icmp_input;\r
+ } else {\r
+ UIP_LOG("ip: packet dropped since no address assigned.");\r
+ goto drop;\r
+ }\r
+ }\r
+#endif /* UIP_PINGADDRCONF */\r
+\r
+ /* Check if the packet is destined for our IP address. */\r
+ if(BUF->destipaddr[0] != uip_hostaddr[0]) {\r
+ UIP_STAT(++uip_stat.ip.drop);\r
+ UIP_LOG("ip: packet not for us.");\r
+ goto drop;\r
+ }\r
+ if(BUF->destipaddr[1] != uip_hostaddr[1]) {\r
+ UIP_STAT(++uip_stat.ip.drop);\r
+ UIP_LOG("ip: packet not for us.");\r
+ goto drop;\r
+ }\r
+\r
+#if 0\r
+ // IP checksum is wrong through Netgear DSL router\r
+ if (uip_ipchksum() != 0xffff) { /* Compute and check the IP header\r
+ checksum. */\r
+ UIP_STAT(++uip_stat.ip.drop);\r
+ UIP_STAT(++uip_stat.ip.chkerr);\r
+ UIP_LOG("ip: bad checksum.");\r
+ goto drop;\r
+ }\r
+#endif\r
+\r
+ if(BUF->proto == UIP_PROTO_TCP) /* Check for TCP packet. If so, jump\r
+ to the tcp_input label. */\r
+ goto tcp_input;\r
+\r
+#if UIP_UDP\r
+ if(BUF->proto == UIP_PROTO_UDP)\r
+ goto udp_input;\r
+#endif /* UIP_UDP */\r
+\r
+ if(BUF->proto != UIP_PROTO_ICMP) { /* We only allow ICMP packets from\r
+ here. */\r
+ UIP_STAT(++uip_stat.ip.drop);\r
+ UIP_STAT(++uip_stat.ip.protoerr);\r
+ UIP_LOG("ip: neither tcp nor icmp.");\r
+ goto drop;\r
+ }\r
+\r
+#if UIP_PINGADDRCONF\r
+ icmp_input:\r
+#endif\r
+ UIP_STAT(++uip_stat.icmp.recv);\r
+\r
+ /* ICMP echo (i.e., ping) processing. This is simple, we only change\r
+ the ICMP type from ECHO to ECHO_REPLY and adjust the ICMP\r
+ checksum before we return the packet. */\r
+ if(ICMPBUF->type != ICMP_ECHO) {\r
+ UIP_STAT(++uip_stat.icmp.drop);\r
+ UIP_STAT(++uip_stat.icmp.typeerr);\r
+ UIP_LOG("icmp: not icmp echo.");\r
+ goto drop;\r
+ }\r
+\r
+ /* If we are configured to use ping IP address assignment, we use\r
+ the destination IP address of this ping packet and assign it to\r
+ ourself. */\r
+#if UIP_PINGADDRCONF\r
+ if((uip_hostaddr[0] | uip_hostaddr[1]) == 0) {\r
+ uip_hostaddr[0] = BUF->destipaddr[0];\r
+ uip_hostaddr[1] = BUF->destipaddr[1];\r
+ }\r
+#endif /* UIP_PINGADDRCONF */\r
+\r
+ ICMPBUF->type = ICMP_ECHO_REPLY;\r
+\r
+ if(ICMPBUF->icmpchksum >= HTONS(0xffff - (ICMP_ECHO << 8))) {\r
+ ICMPBUF->icmpchksum += HTONS(ICMP_ECHO << 8) + 1;\r
+ } else {\r
+ ICMPBUF->icmpchksum += HTONS(ICMP_ECHO << 8);\r
+ }\r
+\r
+ /* Swap IP addresses. */\r
+ tmp16 = BUF->destipaddr[0];\r
+ BUF->destipaddr[0] = BUF->srcipaddr[0];\r
+ BUF->srcipaddr[0] = tmp16;\r
+ tmp16 = BUF->destipaddr[1];\r
+ BUF->destipaddr[1] = BUF->srcipaddr[1];\r
+ BUF->srcipaddr[1] = tmp16;\r
+\r
+ UIP_STAT(++uip_stat.icmp.sent);\r
+ goto send;\r
+\r
+ /* End of IPv4 input header processing code. */\r
+\r
+\r
+#if UIP_UDP\r
+ /* UDP input processing. */\r
+ udp_input:\r
+ /* UDP processing is really just a hack. We don't do anything to the\r
+ UDP/IP headers, but let the UDP application do all the hard\r
+ work. If the application sets uip_slen, it has a packet to\r
+ send. */\r
+#if UIP_UDP_CHECKSUMS\r
+ if(uip_udpchksum() != 0xffff) {\r
+ UIP_STAT(++uip_stat.udp.drop);\r
+ UIP_STAT(++uip_stat.udp.chkerr);\r
+ UIP_LOG("udp: bad checksum.");\r
+ goto drop;\r
+ }\r
+#endif /* UIP_UDP_CHECKSUMS */\r
+\r
+ /* Demultiplex this UDP packet between the UDP "connections". */\r
+ for(uip_udp_conn = &uip_udp_conns[0];\r
+ uip_udp_conn < &uip_udp_conns[UIP_UDP_CONNS];\r
+ ++uip_udp_conn) {\r
+ if(uip_udp_conn->lport != 0 &&\r
+ UDPBUF->destport == uip_udp_conn->lport &&\r
+ (uip_udp_conn->rport == 0 ||\r
+ UDPBUF->srcport == uip_udp_conn->rport) &&\r
+ BUF->srcipaddr[0] == uip_udp_conn->ripaddr[0] &&\r
+ BUF->srcipaddr[1] == uip_udp_conn->ripaddr[1]) {\r
+ goto udp_found;\r
+ }\r
+ }\r
+ goto drop;\r
+\r
+ udp_found:\r
+ uip_len = uip_len - 28;\r
+ uip_appdata = &uip_buf[UIP_LLH_LEN + 28];\r
+ uip_flags = UIP_NEWDATA;\r
+ uip_slen = 0;\r
+ UIP_UDP_APPCALL();\r
+ udp_send:\r
+ if(uip_slen == 0) {\r
+ goto drop;\r
+ }\r
+ uip_len = uip_slen + 28;\r
+\r
+ BUF->len[0] = (uip_len >> 8);\r
+ BUF->len[1] = (uip_len & 0xff);\r
+\r
+ BUF->proto = UIP_PROTO_UDP;\r
+\r
+ UDPBUF->udplen = HTONS(uip_slen + 8);\r
+ UDPBUF->udpchksum = 0;\r
+#if UIP_UDP_CHECKSUMS\r
+ /* Calculate UDP checksum. */\r
+ UDPBUF->udpchksum = ~(uip_udpchksum());\r
+ if(UDPBUF->udpchksum == 0) {\r
+ UDPBUF->udpchksum = 0xffff;\r
+ }\r
+#endif /* UIP_UDP_CHECKSUMS */\r
+\r
+ BUF->srcport = uip_udp_conn->lport;\r
+ BUF->destport = uip_udp_conn->rport;\r
+\r
+ BUF->srcipaddr[0] = uip_hostaddr[0];\r
+ BUF->srcipaddr[1] = uip_hostaddr[1];\r
+ BUF->destipaddr[0] = uip_udp_conn->ripaddr[0];\r
+ BUF->destipaddr[1] = uip_udp_conn->ripaddr[1];\r
+\r
+ uip_appdata = &uip_buf[UIP_LLH_LEN + 40];\r
+ goto ip_send_nolen;\r
+#endif /* UIP_UDP */\r
+\r
+ /* TCP input processing. */\r
+ tcp_input:\r
+ UIP_STAT(++uip_stat.tcp.recv);\r
+\r
+ /* Start of TCP input header processing code. */\r
+\r
+#if 1 // FIXME\r
+ if(uip_tcpchksum() != 0xffff) { /* Compute and check the TCP\r
+ checksum. */\r
+ UIP_STAT(++uip_stat.tcp.drop);\r
+ UIP_STAT(++uip_stat.tcp.chkerr);\r
+ UIP_LOG("tcp: bad checksum.");\r
+ goto drop;\r
+ }\r
+#endif\r
+\r
+ /* Demultiplex this segment. */\r
+ /* First check any active connections. */\r
+ for(uip_connr = &uip_conns[0]; uip_connr < &uip_conns[UIP_CONNS]; ++uip_connr) {\r
+ if(uip_connr->tcpstateflags != CLOSED &&\r
+ BUF->destport == uip_connr->lport &&\r
+ BUF->srcport == uip_connr->rport &&\r
+ BUF->srcipaddr[0] == uip_connr->ripaddr[0] &&\r
+ BUF->srcipaddr[1] == uip_connr->ripaddr[1]) {\r
+ goto found;\r
+ }\r
+ }\r
+\r
+ /* If we didn't find and active connection that expected the packet,\r
+ either this packet is an old duplicate, or this is a SYN packet\r
+ destined for a connection in LISTEN. If the SYN flag isn't set,\r
+ it is an old packet and we send a RST. */\r
+ if((BUF->flags & TCP_CTL) != TCP_SYN)\r
+ goto reset;\r
+\r
+ tmp16 = BUF->destport;\r
+ /* Next, check listening connections. */\r
+ for(c = 0; c < UIP_LISTENPORTS; ++c) {\r
+ if(tmp16 == uip_listenports[c])\r
+ goto found_listen;\r
+ }\r
+\r
+ /* No matching connection found, so we send a RST packet. */\r
+ UIP_STAT(++uip_stat.tcp.synrst);\r
+ reset:\r
+\r
+ /* We do not send resets in response to resets. */\r
+ if(BUF->flags & TCP_RST)\r
+ goto drop;\r
+\r
+ UIP_STAT(++uip_stat.tcp.rst);\r
+\r
+ BUF->flags = TCP_RST | TCP_ACK;\r
+ uip_len = 40;\r
+ BUF->tcpoffset = 5 << 4;\r
+\r
+ /* Flip the seqno and ackno fields in the TCP header. */\r
+ c = BUF->seqno[3];\r
+ BUF->seqno[3] = BUF->ackno[3];\r
+ BUF->ackno[3] = c;\r
+\r
+ c = BUF->seqno[2];\r
+ BUF->seqno[2] = BUF->ackno[2];\r
+ BUF->ackno[2] = c;\r
+\r
+ c = BUF->seqno[1];\r
+ BUF->seqno[1] = BUF->ackno[1];\r
+ BUF->ackno[1] = c;\r
+\r
+ c = BUF->seqno[0];\r
+ BUF->seqno[0] = BUF->ackno[0];\r
+ BUF->ackno[0] = c;\r
+\r
+ /* We also have to increase the sequence number we are\r
+ acknowledging. If the least significant byte overflowed, we need\r
+ to propagate the carry to the other bytes as well. */\r
+ if(++BUF->ackno[3] == 0) {\r
+ if(++BUF->ackno[2] == 0) {\r
+ if(++BUF->ackno[1] == 0) {\r
+ ++BUF->ackno[0];\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Swap port numbers. */\r
+ tmp16 = BUF->srcport;\r
+ BUF->srcport = BUF->destport;\r
+ BUF->destport = tmp16;\r
+\r
+ /* Swap IP addresses. */\r
+ tmp16 = BUF->destipaddr[0];\r
+ BUF->destipaddr[0] = BUF->srcipaddr[0];\r
+ BUF->srcipaddr[0] = tmp16;\r
+ tmp16 = BUF->destipaddr[1];\r
+ BUF->destipaddr[1] = BUF->srcipaddr[1];\r
+ BUF->srcipaddr[1] = tmp16;\r
+\r
+\r
+ /* And send out the RST packet! */\r
+ goto tcp_send_noconn;\r
+\r
+ /* This label will be jumped to if we matched the incoming packet\r
+ with a connection in LISTEN. In that case, we should create a new\r
+ connection and send a SYNACK in return. */\r
+ found_listen:\r
+ /* First we check if there are any connections avaliable. Unused\r
+ connections are kept in the same table as used connections, but\r
+ unused ones have the tcpstate set to CLOSED. Also, connections in\r
+ TIME_WAIT are kept track of and we'll use the oldest one if no\r
+ CLOSED connections are found. Thanks to Eddie C. Dost for a very\r
+ nice algorithm for the TIME_WAIT search. */\r
+ uip_connr = 0;\r
+ for(c = 0; c < UIP_CONNS; ++c) {\r
+ if(uip_conns[c].tcpstateflags == CLOSED) {\r
+ uip_connr = &uip_conns[c];\r
+ break;\r
+ }\r
+ if(uip_conns[c].tcpstateflags == TIME_WAIT) {\r
+ if(uip_connr == 0 ||\r
+ uip_conns[c].timer > uip_connr->timer) {\r
+ uip_connr = &uip_conns[c];\r
+ }\r
+ }\r
+ }\r
+\r
+ if(uip_connr == 0) {\r
+ /* All connections are used already, we drop packet and hope that\r
+ the remote end will retransmit the packet at a time when we\r
+ have more spare connections. */\r
+ UIP_STAT(++uip_stat.tcp.syndrop);\r
+ UIP_LOG("tcp: found no unused connections.");\r
+ goto drop;\r
+ }\r
+ uip_conn = uip_connr;\r
+\r
+ /* Fill in the necessary fields for the new connection. */\r
+ uip_connr->rto = uip_connr->timer = UIP_RTO;\r
+ uip_connr->sa = 0;\r
+ uip_connr->sv = 4;\r
+ uip_connr->nrtx = 0;\r
+ uip_connr->lport = BUF->destport;\r
+ uip_connr->rport = BUF->srcport;\r
+ uip_connr->ripaddr[0] = BUF->srcipaddr[0];\r
+ uip_connr->ripaddr[1] = BUF->srcipaddr[1];\r
+ uip_connr->tcpstateflags = SYN_RCVD;\r
+\r
+ uip_connr->snd_nxt[0] = iss[0];\r
+ uip_connr->snd_nxt[1] = iss[1];\r
+ uip_connr->snd_nxt[2] = iss[2];\r
+ uip_connr->snd_nxt[3] = iss[3];\r
+ uip_connr->len = 1;\r
+\r
+ /* rcv_nxt should be the seqno from the incoming packet + 1. */\r
+ uip_connr->rcv_nxt[3] = BUF->seqno[3];\r
+ uip_connr->rcv_nxt[2] = BUF->seqno[2];\r
+ uip_connr->rcv_nxt[1] = BUF->seqno[1];\r
+ uip_connr->rcv_nxt[0] = BUF->seqno[0];\r
+ uip_add_rcv_nxt(1);\r
+\r
+ /* Parse the TCP MSS option, if present. */\r
+ if((BUF->tcpoffset & 0xf0) > 0x50) {\r
+ for(c = 0; c < ((BUF->tcpoffset >> 4) - 5) << 2 ;) {\r
+ opt = uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + c];\r
+ if(opt == 0x00) {\r
+ /* End of options. */ \r
+ break;\r
+ } else if(opt == 0x01) {\r
+ ++c;\r
+ /* NOP option. */\r
+ } else if(opt == 0x02 &&\r
+ uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0x04) {\r
+ /* An MSS option with the right option length. */ \r
+ tmp16 = ((u16_t)uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 2 + c] << 8) |\r
+ (u16_t)uip_buf[40 + UIP_LLH_LEN + 3 + c];\r
+ uip_connr->initialmss = uip_connr->mss =\r
+ tmp16 > UIP_TCP_MSS? UIP_TCP_MSS: tmp16;\r
+ \r
+ /* And we are done processing options. */\r
+ break;\r
+ } else {\r
+ /* All other options have a length field, so that we easily\r
+ can skip past them. */\r
+ if(uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0) {\r
+ /* If the length field is zero, the options are malformed\r
+ and we don't process them further. */\r
+ break;\r
+ }\r
+ c += uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c];\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Our response will be a SYNACK. */\r
+#if UIP_ACTIVE_OPEN\r
+ tcp_send_synack:\r
+ BUF->flags = TCP_ACK;\r
+\r
+ tcp_send_syn:\r
+ BUF->flags |= TCP_SYN;\r
+#else /* UIP_ACTIVE_OPEN */\r
+ tcp_send_synack:\r
+ BUF->flags = TCP_SYN | TCP_ACK;\r
+#endif /* UIP_ACTIVE_OPEN */\r
+\r
+ /* We send out the TCP Maximum Segment Size option with our\r
+ SYNACK. */\r
+ BUF->optdata[0] = 2;\r
+ BUF->optdata[1] = 4;\r
+ BUF->optdata[2] = (UIP_TCP_MSS) / 256;\r
+ BUF->optdata[3] = (UIP_TCP_MSS) & 255;\r
+ uip_len = 44;\r
+ BUF->tcpoffset = 6 << 4;\r
+ goto tcp_send;\r
+\r
+ /* This label will be jumped to if we found an active connection. */\r
+ found:\r
+ uip_conn = uip_connr;\r
+ uip_flags = 0;\r
+\r
+ /* We do a very naive form of TCP reset processing; we just accept\r
+ any RST and kill our connection. We should in fact check if the\r
+ sequence number of this reset is wihtin our advertised window\r
+ before we accept the reset. */\r
+ if(BUF->flags & TCP_RST) {\r
+ uip_connr->tcpstateflags = CLOSED;\r
+ UIP_LOG("tcp: got reset, aborting connection.");\r
+ uip_flags = UIP_ABORT;\r
+ UIP_APPCALL();\r
+ goto drop;\r
+ }\r
+ /* Calculated the length of the data, if the application has sent\r
+ any data to us. */\r
+ c = (BUF->tcpoffset >> 4) << 2;\r
+ /* uip_len will contain the length of the actual TCP data. This is\r
+ calculated by subtracing the length of the TCP header (in\r
+ c) and the length of the IP header (20 bytes). */\r
+ uip_len = uip_len - c - 20;\r
+\r
+ /* First, check if the sequence number of the incoming packet is\r
+ what we're expecting next. If not, we send out an ACK with the\r
+ correct numbers in. */\r
+ if(uip_len > 0 &&\r
+ (BUF->seqno[0] != uip_connr->rcv_nxt[0] ||\r
+ BUF->seqno[1] != uip_connr->rcv_nxt[1] ||\r
+ BUF->seqno[2] != uip_connr->rcv_nxt[2] ||\r
+ BUF->seqno[3] != uip_connr->rcv_nxt[3])) {\r
+ goto tcp_send_ack;\r
+ }\r
+\r
+ /* Next, check if the incoming segment acknowledges any outstanding\r
+ data. If so, we update the sequence number, reset the length of\r
+ the outstanding data, calculate RTT estimations, and reset the\r
+ retransmission timer. */\r
+ if((BUF->flags & TCP_ACK) && uip_outstanding(uip_connr)) {\r
+ uip_add32(uip_connr->snd_nxt, uip_connr->len);\r
+ if(BUF->ackno[0] == uip_acc32[0] &&\r
+ BUF->ackno[1] == uip_acc32[1] &&\r
+ BUF->ackno[2] == uip_acc32[2] &&\r
+ BUF->ackno[3] == uip_acc32[3]) {\r
+ /* Update sequence number. */\r
+ uip_connr->snd_nxt[0] = uip_acc32[0];\r
+ uip_connr->snd_nxt[1] = uip_acc32[1];\r
+ uip_connr->snd_nxt[2] = uip_acc32[2];\r
+ uip_connr->snd_nxt[3] = uip_acc32[3];\r
+ \r
+\r
+ /* Do RTT estimation, unless we have done retransmissions. */\r
+ if(uip_connr->nrtx == 0) {\r
+ signed char m;\r
+ m = uip_connr->rto - uip_connr->timer;\r
+ /* This is taken directly from VJs original code in his paper */\r
+ m = m - (uip_connr->sa >> 3);\r
+ uip_connr->sa += m;\r
+ if(m < 0) {\r
+ m = -m;\r
+ }\r
+ m = m - (uip_connr->sv >> 2);\r
+ uip_connr->sv += m;\r
+ uip_connr->rto = (uip_connr->sa >> 3) + uip_connr->sv;\r
+\r
+ }\r
+ /* Set the acknowledged flag. */\r
+ uip_flags = UIP_ACKDATA;\r
+ /* Reset the retransmission timer. */\r
+ uip_connr->timer = uip_connr->rto;\r
+ }\r
+\r
+ }\r
+\r
+ /* Do different things depending on in what state the connection is. */\r
+ switch(uip_connr->tcpstateflags & TS_MASK) {\r
+ /* CLOSED and LISTEN are not handled here. CLOSE_WAIT is not\r
+ implemented, since we force the application to close when the\r
+ peer sends a FIN (hence the application goes directly from\r
+ ESTABLISHED to LAST_ACK). */\r
+ case SYN_RCVD:\r
+ /* In SYN_RCVD we have sent out a SYNACK in response to a SYN, and\r
+ we are waiting for an ACK that acknowledges the data we sent\r
+ out the last time. Therefore, we want to have the UIP_ACKDATA\r
+ flag set. If so, we enter the ESTABLISHED state. */\r
+ if(uip_flags & UIP_ACKDATA) {\r
+ uip_connr->tcpstateflags = ESTABLISHED;\r
+ uip_flags = UIP_CONNECTED;\r
+ uip_connr->len = 0;\r
+ if(uip_len > 0) {\r
+ uip_flags |= UIP_NEWDATA;\r
+ uip_add_rcv_nxt(uip_len);\r
+ }\r
+ uip_slen = 0;\r
+ UIP_APPCALL();\r
+ goto appsend;\r
+ }\r
+ goto drop;\r
+#if UIP_ACTIVE_OPEN\r
+ case SYN_SENT:\r
+ /* In SYN_SENT, we wait for a SYNACK that is sent in response to\r
+ our SYN. The rcv_nxt is set to sequence number in the SYNACK\r
+ plus one, and we send an ACK. We move into the ESTABLISHED\r
+ state. */\r
+ if((uip_flags & UIP_ACKDATA) &&\r
+ BUF->flags == (TCP_SYN | TCP_ACK)) {\r
+\r
+ /* Parse the TCP MSS option, if present. */\r
+ if((BUF->tcpoffset & 0xf0) > 0x50) {\r
+ for(c = 0; c < ((BUF->tcpoffset >> 4) - 5) << 2 ;) {\r
+ opt = uip_buf[40 + UIP_LLH_LEN + c];\r
+ if(opt == 0x00) {\r
+ /* End of options. */ \r
+ break;\r
+ } else if(opt == 0x01) {\r
+ ++c;\r
+ /* NOP option. */\r
+ } else if(opt == 0x02 &&\r
+ uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0x04) {\r
+ /* An MSS option with the right option length. */\r
+ tmp16 = (uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 2 + c] << 8) |\r
+ uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 3 + c];\r
+ uip_connr->initialmss =\r
+ uip_connr->mss = tmp16 > UIP_TCP_MSS? UIP_TCP_MSS: tmp16;\r
+\r
+ /* And we are done processing options. */\r
+ break;\r
+ } else {\r
+ /* All other options have a length field, so that we easily\r
+ can skip past them. */\r
+ if(uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0) {\r
+ /* If the length field is zero, the options are malformed\r
+ and we don't process them further. */\r
+ break;\r
+ }\r
+ c += uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c];\r
+ }\r
+ }\r
+ }\r
+ uip_connr->tcpstateflags = ESTABLISHED;\r
+ uip_connr->rcv_nxt[0] = BUF->seqno[0];\r
+ uip_connr->rcv_nxt[1] = BUF->seqno[1];\r
+ uip_connr->rcv_nxt[2] = BUF->seqno[2];\r
+ uip_connr->rcv_nxt[3] = BUF->seqno[3];\r
+ uip_add_rcv_nxt(1);\r
+ uip_flags = UIP_CONNECTED | UIP_NEWDATA;\r
+ uip_connr->len = 0;\r
+ uip_len = 0;\r
+ uip_slen = 0;\r
+ UIP_APPCALL();\r
+ goto appsend;\r
+ }\r
+ goto reset;\r
+#endif /* UIP_ACTIVE_OPEN */\r
+\r
+ case ESTABLISHED:\r
+ /* In the ESTABLISHED state, we call upon the application to feed\r
+ data into the uip_buf. If the UIP_ACKDATA flag is set, the\r
+ application should put new data into the buffer, otherwise we are\r
+ retransmitting an old segment, and the application should put that\r
+ data into the buffer.\r
+\r
+ If the incoming packet is a FIN, we should close the connection on\r
+ this side as well, and we send out a FIN and enter the LAST_ACK\r
+ state. We require that there is no outstanding data; otherwise the\r
+ sequence numbers will be screwed up. */\r
+\r
+ if(BUF->flags & TCP_FIN) {\r
+ if(uip_outstanding(uip_connr)) {\r
+ goto drop;\r
+ }\r
+ uip_add_rcv_nxt(1 + uip_len);\r
+ uip_flags = UIP_CLOSE;\r
+ if(uip_len > 0) {\r
+ uip_flags |= UIP_NEWDATA;\r
+ }\r
+ UIP_APPCALL();\r
+ uip_connr->len = 1;\r
+ uip_connr->tcpstateflags = LAST_ACK;\r
+ uip_connr->nrtx = 0;\r
+ tcp_send_finack:\r
+ BUF->flags = TCP_FIN | TCP_ACK;\r
+ goto tcp_send_nodata;\r
+ }\r
+\r
+ /* Check the URG flag. If this is set, the segment carries urgent\r
+ data that we must pass to the application. */\r
+ if(BUF->flags & TCP_URG) {\r
+#if UIP_URGDATA > 0\r
+ uip_urglen = (BUF->urgp[0] << 8) | BUF->urgp[1];\r
+ if(uip_urglen > uip_len) {\r
+ /* There is more urgent data in the next segment to come. */\r
+ uip_urglen = uip_len;\r
+ }\r
+ uip_add_rcv_nxt(uip_urglen);\r
+ uip_len -= uip_urglen;\r
+ uip_urgdata = uip_appdata;\r
+ uip_appdata += uip_urglen;\r
+ } else {\r
+ uip_urglen = 0;\r
+#endif /* UIP_URGDATA > 0 */\r
+ uip_appdata += (BUF->urgp[0] << 8) | BUF->urgp[1];\r
+ uip_len -= (BUF->urgp[0] << 8) | BUF->urgp[1];\r
+ }\r
+\r
+\r
+ /* If uip_len > 0 we have TCP data in the packet, and we flag this\r
+ by setting the UIP_NEWDATA flag and update the sequence number\r
+ we acknowledge. If the application has stopped the dataflow\r
+ using uip_stop(), we must not accept any data packets from the\r
+ remote host. */\r
+ if(uip_len > 0 && !(uip_connr->tcpstateflags & UIP_STOPPED)) {\r
+ uip_flags |= UIP_NEWDATA;\r
+ uip_add_rcv_nxt(uip_len);\r
+ }\r
+\r
+ /* Check if the available buffer space advertised by the other end\r
+ is smaller than the initial MSS for this connection. If so, we\r
+ set the current MSS to the window size to ensure that the\r
+ application does not send more data than the other end can\r
+ handle.\r
+\r
+ If the remote host advertises a zero window, we set the MSS to\r
+ the initial MSS so that the application will send an entire MSS\r
+ of data. This data will not be acknowledged by the receiver,\r
+ and the application will retransmit it. This is called the\r
+ "persistent timer" and uses the retransmission mechanim.\r
+ */\r
+ tmp16 = ((u16_t)BUF->wnd[0] << 8) + (u16_t)BUF->wnd[1];\r
+ if(tmp16 > uip_connr->initialmss ||\r
+ tmp16 == 0) {\r
+ tmp16 = uip_connr->initialmss;\r
+ }\r
+ uip_connr->mss = tmp16;\r
+\r
+ /* If this packet constitutes an ACK for outstanding data (flagged\r
+ by the UIP_ACKDATA flag, we should call the application since it\r
+ might want to send more data. If the incoming packet had data\r
+ from the peer (as flagged by the UIP_NEWDATA flag), the\r
+ application must also be notified.\r
+\r
+ When the application is called, the global variable uip_len\r
+ contains the length of the incoming data. The application can\r
+ access the incoming data through the global pointer\r
+ uip_appdata, which usually points 40 bytes into the uip_buf\r
+ array.\r
+\r
+ If the application wishes to send any data, this data should be\r
+ put into the uip_appdata and the length of the data should be\r
+ put into uip_len. If the application don't have any data to\r
+ send, uip_len must be set to 0. */\r
+ if(uip_flags & (UIP_NEWDATA | UIP_ACKDATA)) {\r
+ uip_slen = 0;\r
+ UIP_APPCALL();\r
+\r
+ appsend:\r
+\r
+ if(uip_flags & UIP_ABORT) {\r
+ uip_slen = 0;\r
+ uip_connr->tcpstateflags = CLOSED;\r
+ BUF->flags = TCP_RST | TCP_ACK;\r
+ goto tcp_send_nodata;\r
+ }\r
+\r
+ if(uip_flags & UIP_CLOSE) {\r
+ uip_slen = 0;\r
+ uip_connr->len = 1;\r
+ uip_connr->tcpstateflags = FIN_WAIT_1;\r
+ uip_connr->nrtx = 0;\r
+ BUF->flags = TCP_FIN | TCP_ACK;\r
+ goto tcp_send_nodata; \r
+ }\r
+\r
+ /* If uip_slen > 0, the application has data to be sent. */\r
+ if(uip_slen > 0) {\r
+\r
+ /* If the connection has acknowledged data, the contents of\r
+ the ->len variable should be discarded. */\r
+ if((uip_flags & UIP_ACKDATA) != 0) {\r
+ uip_connr->len = 0;\r
+ }\r
+\r
+ /* If the ->len variable is non-zero the connection has\r
+ already data in transit and cannot send anymore right\r
+ now. */\r
+ if(uip_connr->len == 0) {\r
+\r
+ /* The application cannot send more than what is allowed by\r
+ the mss (the minumum of the MSS and the available\r
+ window). */\r
+ if(uip_slen > uip_connr->mss) {\r
+ uip_slen = uip_connr->mss;\r
+ }\r
+\r
+ /* Remember how much data we send out now so that we know\r
+ when everything has been acknowledged. */\r
+ uip_connr->len = uip_slen;\r
+ } else {\r
+\r
+ /* If the application already had unacknowledged data, we\r
+ make sure that the application does not send (i.e.,\r
+ retransmit) out more than it previously sent out. */\r
+ uip_slen = uip_connr->len;\r
+ }\r
+ } else {\r
+ uip_connr->len = 0;\r
+ }\r
+ uip_connr->nrtx = 0;\r
+ apprexmit:\r
+ uip_appdata = uip_sappdata;\r
+\r
+ /* If the application has data to be sent, or if the incoming\r
+ packet had new data in it, we must send out a packet. */\r
+ if(uip_slen > 0 && uip_connr->len > 0) {\r
+ /* Add the length of the IP and TCP headers. */\r
+ uip_len = uip_connr->len + UIP_TCPIP_HLEN;\r
+ /* We always set the ACK flag in response packets. */\r
+ BUF->flags = TCP_ACK | TCP_PSH;\r
+ /* Send the packet. */\r
+ goto tcp_send_noopts;\r
+ }\r
+ /* If there is no data to send, just send out a pure ACK if\r
+ there is newdata. */\r
+ if(uip_flags & UIP_NEWDATA) {\r
+ uip_len = UIP_TCPIP_HLEN;\r
+ BUF->flags = TCP_ACK;\r
+ goto tcp_send_noopts;\r
+ }\r
+ }\r
+ goto drop;\r
+ case LAST_ACK:\r
+ /* We can close this connection if the peer has acknowledged our\r
+ FIN. This is indicated by the UIP_ACKDATA flag. */\r
+ if(uip_flags & UIP_ACKDATA) {\r
+ uip_connr->tcpstateflags = CLOSED;\r
+ uip_flags = UIP_CLOSE;\r
+ UIP_APPCALL();\r
+ }\r
+ break;\r
+\r
+ case FIN_WAIT_1:\r
+ /* The application has closed the connection, but the remote host\r
+ hasn't closed its end yet. Thus we do nothing but wait for a\r
+ FIN from the other side. */\r
+ if(uip_len > 0) {\r
+ uip_add_rcv_nxt(uip_len);\r
+ }\r
+ if(BUF->flags & TCP_FIN) {\r
+ if(uip_flags & UIP_ACKDATA) {\r
+ uip_connr->tcpstateflags = TIME_WAIT;\r
+ uip_connr->timer = 0;\r
+ uip_connr->len = 0;\r
+ } else {\r
+ uip_connr->tcpstateflags = CLOSING;\r
+ }\r
+ uip_add_rcv_nxt(1);\r
+ uip_flags = UIP_CLOSE;\r
+ UIP_APPCALL();\r
+ goto tcp_send_ack;\r
+ } else if(uip_flags & UIP_ACKDATA) {\r
+ uip_connr->tcpstateflags = FIN_WAIT_2;\r
+ uip_connr->len = 0;\r
+ goto drop;\r
+ }\r
+ if(uip_len > 0) {\r
+ goto tcp_send_ack;\r
+ }\r
+ goto drop;\r
+\r
+ case FIN_WAIT_2:\r
+ if(uip_len > 0) {\r
+ uip_add_rcv_nxt(uip_len);\r
+ }\r
+ if(BUF->flags & TCP_FIN) {\r
+ uip_connr->tcpstateflags = TIME_WAIT;\r
+ uip_connr->timer = 0;\r
+ uip_add_rcv_nxt(1);\r
+ uip_flags = UIP_CLOSE;\r
+ UIP_APPCALL();\r
+ goto tcp_send_ack;\r
+ }\r
+ if(uip_len > 0) {\r
+ goto tcp_send_ack;\r
+ }\r
+ goto drop;\r
+\r
+ case TIME_WAIT:\r
+ goto tcp_send_ack;\r
+\r
+ case CLOSING:\r
+ if(uip_flags & UIP_ACKDATA) {\r
+ uip_connr->tcpstateflags = TIME_WAIT;\r
+ uip_connr->timer = 0;\r
+ }\r
+ }\r
+ goto drop;\r
+\r
+\r
+ /* We jump here when we are ready to send the packet, and just want\r
+ to set the appropriate TCP sequence numbers in the TCP header. */\r
+ tcp_send_ack:\r
+ BUF->flags = TCP_ACK;\r
+ tcp_send_nodata:\r
+ uip_len = 40;\r
+ tcp_send_noopts:\r
+ BUF->tcpoffset = 5 << 4;\r
+ tcp_send:\r
+ /* We're done with the input processing. We are now ready to send a\r
+ reply. Our job is to fill in all the fields of the TCP and IP\r
+ headers before calculating the checksum and finally send the\r
+ packet. */\r
+ BUF->ackno[0] = uip_connr->rcv_nxt[0];\r
+ BUF->ackno[1] = uip_connr->rcv_nxt[1];\r
+ BUF->ackno[2] = uip_connr->rcv_nxt[2];\r
+ BUF->ackno[3] = uip_connr->rcv_nxt[3];\r
+\r
+ BUF->seqno[0] = uip_connr->snd_nxt[0];\r
+ BUF->seqno[1] = uip_connr->snd_nxt[1];\r
+ BUF->seqno[2] = uip_connr->snd_nxt[2];\r
+ BUF->seqno[3] = uip_connr->snd_nxt[3];\r
+\r
+ BUF->proto = UIP_PROTO_TCP;\r
+\r
+ BUF->srcport = uip_connr->lport;\r
+ BUF->destport = uip_connr->rport;\r
+\r
+ BUF->srcipaddr[0] = uip_hostaddr[0];\r
+ BUF->srcipaddr[1] = uip_hostaddr[1];\r
+ BUF->destipaddr[0] = uip_connr->ripaddr[0];\r
+ BUF->destipaddr[1] = uip_connr->ripaddr[1];\r
+\r
+\r
+ if(uip_connr->tcpstateflags & UIP_STOPPED) {\r
+ /* If the connection has issued uip_stop(), we advertise a zero\r
+ window so that the remote host will stop sending data. */\r
+ BUF->wnd[0] = BUF->wnd[1] = 0;\r
+ } else {\r
+ BUF->wnd[0] = ((UIP_RECEIVE_WINDOW) >> 8);\r
+ BUF->wnd[1] = ((UIP_RECEIVE_WINDOW) & 0xff);\r
+ }\r
+\r
+ tcp_send_noconn:\r
+\r
+ BUF->len[0] = (uip_len >> 8);\r
+ BUF->len[1] = (uip_len & 0xff);\r
+\r
+ /* Calculate TCP checksum. */\r
+ BUF->tcpchksum = 0;\r
+ BUF->tcpchksum = ~(uip_tcpchksum());\r
+\r
+\r
+#if UIP_UDP\r
+ ip_send_nolen:\r
+#endif\r
+\r
+ BUF->vhl = 0x45;\r
+ BUF->tos = 0;\r
+ BUF->ipoffset[0] = BUF->ipoffset[1] = 0;\r
+ BUF->ttl = UIP_TTL;\r
+ ++ipid;\r
+ BUF->ipid[0] = ipid >> 8;\r
+ BUF->ipid[1] = ipid & 0xff;\r
+\r
+ /* Calculate IP checksum. */\r
+ BUF->ipchksum = 0;\r
+ BUF->ipchksum = ~(uip_ipchksum());\r
+\r
+ UIP_STAT(++uip_stat.tcp.sent);\r
+ send:\r
+ UIP_STAT(++uip_stat.ip.sent);\r
+ /* Return and let the caller do the actual transmission. */\r
+ return;\r
+ drop:\r
+ uip_len = 0;\r
+ return;\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+u16_t\r
+htons(u16_t val)\r
+{\r
+ return HTONS(val);\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+/** @} */\r
--- /dev/null
+/**\r
+ * \addtogroup uip\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * Header file for the uIP TCP/IP stack.\r
+ * \author Adam Dunkels <adam@dunkels.com>\r
+ *\r
+ * The uIP TCP/IP stack header file contains definitions for a number\r
+ * of C macros that are used by uIP programs as well as internal uIP\r
+ * structures, TCP/IP header structures and function declarations.\r
+ *\r
+ */\r
+\r
+\r
+/*\r
+ * Copyright (c) 2001-2003, Adam Dunkels.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ * 3. The name of the author may not be used to endorse or promote\r
+ * products derived from this software without specific prior\r
+ * written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * $Id: uip.h,v 1.36.2.7 2003/10/07 13:47:51 adam Exp $\r
+ *\r
+ */\r
+\r
+#ifndef __UIP_H__\r
+#define __UIP_H__\r
+\r
+#include "uipopt.h"\r
+\r
+/*-----------------------------------------------------------------------------------*/\r
+/* First, the functions that should be called from the\r
+ * system. Initialization, the periodic timer and incoming packets are\r
+ * handled by the following three functions.\r
+ */\r
+\r
+/**\r
+ * \defgroup uipconffunc uIP configuration functions\r
+ * @{\r
+ *\r
+ * The uIP configuration functions are used for setting run-time\r
+ * parameters in uIP such as IP addresses.\r
+ */\r
+\r
+/**\r
+ * Set the IP address of this host.\r
+ *\r
+ * The IP address is represented as a 4-byte array where the first\r
+ * octet of the IP address is put in the first member of the 4-byte\r
+ * array.\r
+ *\r
+ * \param addr A pointer to a 4-byte representation of the IP address.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_sethostaddr(addr) do { uip_hostaddr[0] = addr[0]; \\r
+ uip_hostaddr[1] = addr[1]; } while(0)\r
+\r
+/**\r
+ * Get the IP address of this host.\r
+ *\r
+ * The IP address is represented as a 4-byte array where the first\r
+ * octet of the IP address is put in the first member of the 4-byte\r
+ * array.\r
+ *\r
+ * \param addr A pointer to a 4-byte array that will be filled in with\r
+ * the currently configured IP address.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_gethostaddr(addr) do { addr[0] = uip_hostaddr[0]; \\r
+ addr[1] = uip_hostaddr[1]; } while(0)\r
+\r
+/** @} */\r
+\r
+/**\r
+ * \defgroup uipinit uIP initialization functions\r
+ * @{\r
+ *\r
+ * The uIP initialization functions are used for booting uIP.\r
+ */\r
+\r
+/**\r
+ * uIP initialization function.\r
+ *\r
+ * This function should be called at boot up to initilize the uIP\r
+ * TCP/IP stack.\r
+ */\r
+void uip_init(void);\r
+\r
+/** @} */\r
+\r
+/**\r
+ * \defgroup uipdevfunc uIP device driver functions\r
+ * @{\r
+ *\r
+ * These functions are used by a network device driver for interacting\r
+ * with uIP.\r
+ */\r
+\r
+/**\r
+ * Process an incoming packet.\r
+ *\r
+ * This function should be called when the device driver has received\r
+ * a packet from the network. The packet from the device driver must\r
+ * be present in the uip_buf buffer, and the length of the packet\r
+ * should be placed in the uip_len variable.\r
+ *\r
+ * When the function returns, there may be an outbound packet placed\r
+ * in the uip_buf packet buffer. If so, the uip_len variable is set to\r
+ * the length of the packet. If no packet is to be sent out, the\r
+ * uip_len variable is set to 0.\r
+ *\r
+ * The usual way of calling the function is presented by the source\r
+ * code below.\r
+ \code\r
+ uip_len = devicedriver_poll();\r
+ if(uip_len > 0) {\r
+ uip_input();\r
+ if(uip_len > 0) {\r
+ devicedriver_send();\r
+ }\r
+ }\r
+ \endcode\r
+ *\r
+ * \note If you are writing a uIP device driver that needs ARP\r
+ * (Address Resolution Protocol), e.g., when running uIP over\r
+ * Ethernet, you will need to call the uIP ARP code before calling\r
+ * this function:\r
+ \code\r
+ #define BUF ((struct uip_eth_hdr *)&uip_buf[0])\r
+ uip_len = ethernet_devicedrver_poll();\r
+ if(uip_len > 0) {\r
+ if(BUF->type == HTONS(UIP_ETHTYPE_IP)) {\r
+ uip_arp_ipin();\r
+ uip_input();\r
+ if(uip_len > 0) {\r
+ uip_arp_out();\r
+ ethernet_devicedriver_send();\r
+ }\r
+ } else if(BUF->type == HTONS(UIP_ETHTYPE_ARP)) {\r
+ uip_arp_arpin();\r
+ if(uip_len > 0) {\r
+ ethernet_devicedriver_send();\r
+ }\r
+ }\r
+ \endcode\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_input() uip_process(UIP_DATA)\r
+\r
+/**\r
+ * Periodic processing for a connection identified by its number.\r
+ *\r
+ * This function does the necessary periodic processing (timers,\r
+ * polling) for a uIP TCP conneciton, and should be called when the\r
+ * periodic uIP timer goes off. It should be called for every\r
+ * connection, regardless of whether they are open of closed.\r
+ *\r
+ * When the function returns, it may have an outbound packet waiting\r
+ * for service in the uIP packet buffer, and if so the uip_len\r
+ * variable is set to a value larger than zero. The device driver\r
+ * should be called to send out the packet.\r
+ *\r
+ * The ususal way of calling the function is through a for() loop like\r
+ * this:\r
+ \code\r
+ for(i = 0; i < UIP_CONNS; ++i) {\r
+ uip_periodic(i);\r
+ if(uip_len > 0) {\r
+ devicedriver_send();\r
+ }\r
+ }\r
+ \endcode\r
+ *\r
+ * \note If you are writing a uIP device driver that needs ARP\r
+ * (Address Resolution Protocol), e.g., when running uIP over\r
+ * Ethernet, you will need to call the uip_arp_out() function before\r
+ * calling the device driver:\r
+ \code\r
+ for(i = 0; i < UIP_CONNS; ++i) {\r
+ uip_periodic(i);\r
+ if(uip_len > 0) {\r
+ uip_arp_out();\r
+ ethernet_devicedriver_send();\r
+ }\r
+ }\r
+ \endcode\r
+ *\r
+ * \param conn The number of the connection which is to be periodically polled.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_periodic(conn) do { uip_conn = &uip_conns[conn]; \\r
+ uip_process(UIP_TIMER); } while (0)\r
+\r
+/**\r
+ * Periodic processing for a connection identified by a pointer to its structure.\r
+ *\r
+ * Same as uip_periodic() but takes a pointer to the actual uip_conn\r
+ * struct instead of an integer as its argument. This function can be\r
+ * used to force periodic processing of a specific connection.\r
+ *\r
+ * \param conn A pointer to the uip_conn struct for the connection to\r
+ * be processed.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_periodic_conn(conn) do { uip_conn = conn; \\r
+ uip_process(UIP_TIMER); } while (0)\r
+\r
+#if UIP_UDP\r
+/**\r
+ * Periodic processing for a UDP connection identified by its number.\r
+ *\r
+ * This function is essentially the same as uip_prerioic(), but for\r
+ * UDP connections. It is called in a similar fashion as the\r
+ * uip_periodic() function:\r
+ \code\r
+ for(i = 0; i < UIP_UDP_CONNS; i++) {\r
+ uip_udp_periodic(i);\r
+ if(uip_len > 0) {\r
+ devicedriver_send();\r
+ }\r
+ }\r
+ \endcode\r
+ *\r
+ * \note As for the uip_periodic() function, special care has to be\r
+ * taken when using uIP together with ARP and Ethernet:\r
+ \code\r
+ for(i = 0; i < UIP_UDP_CONNS; i++) {\r
+ uip_udp_periodic(i);\r
+ if(uip_len > 0) {\r
+ uip_arp_out();\r
+ ethernet_devicedriver_send();\r
+ }\r
+ }\r
+ \endcode\r
+ *\r
+ * \param conn The number of the UDP connection to be processed.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_udp_periodic(conn) do { uip_udp_conn = &uip_udp_conns[conn]; \\r
+ uip_process(UIP_UDP_TIMER); } while (0)\r
+\r
+/**\r
+ * Periodic processing for a UDP connection identified by a pointer to\r
+ * its structure.\r
+ *\r
+ * Same as uip_udp_periodic() but takes a pointer to the actual\r
+ * uip_conn struct instead of an integer as its argument. This\r
+ * function can be used to force periodic processing of a specific\r
+ * connection.\r
+ *\r
+ * \param conn A pointer to the uip_udp_conn struct for the connection\r
+ * to be processed.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_udp_periodic_conn(conn) do { uip_udp_conn = conn; \\r
+ uip_process(UIP_UDP_TIMER); } while (0)\r
+\r
+\r
+#endif /* UIP_UDP */\r
+\r
+/**\r
+ * The uIP packet buffer.\r
+ *\r
+ * The uip_buf array is used to hold incoming and outgoing\r
+ * packets. The device driver should place incoming data into this\r
+ * buffer. When sending data, the device driver should read the link\r
+ * level headers and the TCP/IP headers from this buffer. The size of\r
+ * the link level headers is configured by the UIP_LLH_LEN define.\r
+ *\r
+ * \note The application data need not be placed in this buffer, so\r
+ * the device driver must read it from the place pointed to by the\r
+ * uip_appdata pointer as illustrated by the following example:\r
+ \code\r
+ void\r
+ devicedriver_send(void)\r
+ {\r
+ hwsend(&uip_buf[0], UIP_LLH_LEN);\r
+ hwsend(&uip_buf[UIP_LLH_LEN], 40);\r
+ hwsend(uip_appdata, uip_len - 40 - UIP_LLH_LEN);\r
+ }\r
+ \endcode\r
+ */\r
+extern u8_t uip_buf[UIP_BUFSIZE+2]; /*_RB_ __attribute__ ((aligned (4)));*/\r
+\r
+/** @} */\r
+\r
+/*-----------------------------------------------------------------------------------*/\r
+/* Functions that are used by the uIP application program. Opening and\r
+ * closing connections, sending and receiving data, etc. is all\r
+ * handled by the functions below.\r
+*/\r
+/**\r
+ * \defgroup uipappfunc uIP application functions\r
+ * @{\r
+ *\r
+ * Functions used by an application running of top of uIP.\r
+ */\r
+\r
+/**\r
+ * Start listening to the specified port.\r
+ *\r
+ * \note Since this function expects the port number in network byte\r
+ * order, a conversion using HTONS() or htons() is necessary.\r
+ *\r
+ \code\r
+ uip_listen(HTONS(80));\r
+ \endcode\r
+ *\r
+ * \param port A 16-bit port number in network byte order.\r
+ */\r
+void uip_listen(u16_t port);\r
+\r
+/**\r
+ * Stop listening to the specified port.\r
+ *\r
+ * \note Since this function expects the port number in network byte\r
+ * order, a conversion using HTONS() or htons() is necessary.\r
+ *\r
+ \code\r
+ uip_unlisten(HTONS(80));\r
+ \endcode\r
+ *\r
+ * \param port A 16-bit port number in network byte order.\r
+ */\r
+void uip_unlisten(u16_t port);\r
+\r
+/**\r
+ * Connect to a remote host using TCP.\r
+ *\r
+ * This function is used to start a new connection to the specified\r
+ * port on the specied host. It allocates a new connection identifier,\r
+ * sets the connection to the SYN_SENT state and sets the\r
+ * retransmission timer to 0. This will cause a TCP SYN segment to be\r
+ * sent out the next time this connection is periodically processed,\r
+ * which usually is done within 0.5 seconds after the call to\r
+ * uip_connect().\r
+ *\r
+ * \note This function is avaliable only if support for active open\r
+ * has been configured by defining UIP_ACTIVE_OPEN to 1 in uipopt.h.\r
+ *\r
+ * \note Since this function requires the port number to be in network\r
+ * byte order, a convertion using HTONS() or htons() is necessary.\r
+ *\r
+ \code\r
+ u16_t ipaddr[2];\r
+\r
+ uip_ipaddr(ipaddr, 192,168,1,2);\r
+ uip_connect(ipaddr, HTONS(80));\r
+ \endcode\r
+ *\r
+ * \param ripaddr A pointer to a 4-byte array representing the IP\r
+ * address of the remote hot.\r
+ *\r
+ * \param port A 16-bit port number in network byte order.\r
+ *\r
+ * \return A pointer to the uIP connection identifier for the new connection,\r
+ * or NULL if no connection could be allocated.\r
+ *\r
+ */\r
+struct uip_conn *uip_connect(u16_t *ripaddr, u16_t port);\r
+\r
+\r
+\r
+/**\r
+ * \internal\r
+ *\r
+ * Check if a connection has outstanding (i.e., unacknowledged) data.\r
+ *\r
+ * \param conn A pointer to the uip_conn structure for the connection.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_outstanding(conn) ((conn)->len)\r
+\r
+/**\r
+ * Send data on the current connection.\r
+ *\r
+ * This function is used to send out a single segment of TCP\r
+ * data. Only applications that have been invoked by uIP for event\r
+ * processing can send data.\r
+ *\r
+ * The amount of data that actually is sent out after a call to this\r
+ * funcion is determined by the maximum amount of data TCP allows. uIP\r
+ * will automatically crop the data so that only the appropriate\r
+ * amount of data is sent. The function uip_mss() can be used to query\r
+ * uIP for the amount of data that actually will be sent.\r
+ *\r
+ * \note This function does not guarantee that the sent data will\r
+ * arrive at the destination. If the data is lost in the network, the\r
+ * application will be invoked with the uip_rexmit() event being\r
+ * set. The application will then have to resend the data using this\r
+ * function.\r
+ *\r
+ * \param data A pointer to the data which is to be sent.\r
+ *\r
+ * \param len The maximum amount of data bytes to be sent.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_send(data, len) do { uip_sappdata = (data); uip_slen = (len);} while(0)\r
+\r
+/**\r
+ * The length of any incoming data that is currently avaliable (if avaliable)\r
+ * in the uip_appdata buffer.\r
+ *\r
+ * The test function uip_data() must first be used to check if there\r
+ * is any data available at all.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_datalen() uip_len\r
+\r
+/**\r
+ * The length of any out-of-band data (urgent data) that has arrived\r
+ * on the connection.\r
+ *\r
+ * \note The configuration parameter UIP_URGDATA must be set for this\r
+ * function to be enabled.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_urgdatalen() uip_urglen\r
+\r
+/**\r
+ * Close the current connection.\r
+ *\r
+ * This function will close the current connection in a nice way.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_close() (uip_flags = UIP_CLOSE)\r
+\r
+/**\r
+ * Abort the current connection.\r
+ *\r
+ * This function will abort (reset) the current connection, and is\r
+ * usually used when an error has occured that prevents using the\r
+ * uip_close() function.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_abort() (uip_flags = UIP_ABORT)\r
+\r
+/**\r
+ * Tell the sending host to stop sending data.\r
+ *\r
+ * This function will close our receiver's window so that we stop\r
+ * receiving data for the current connection.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_stop() (uip_conn->tcpstateflags |= UIP_STOPPED)\r
+\r
+/**\r
+ * Find out if the current connection has been previously stopped with\r
+ * uip_stop().\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_stopped(conn) ((conn)->tcpstateflags & UIP_STOPPED)\r
+\r
+/**\r
+ * Restart the current connection, if is has previously been stopped\r
+ * with uip_stop().\r
+ *\r
+ * This function will open the receiver's window again so that we\r
+ * start receiving data for the current connection.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_restart() do { uip_flags |= UIP_NEWDATA; \\r
+ uip_conn->tcpstateflags &= ~UIP_STOPPED; \\r
+ } while(0)\r
+\r
+\r
+/* uIP tests that can be made to determine in what state the current\r
+ connection is, and what the application function should do. */\r
+\r
+/**\r
+ * Is new incoming data available?\r
+ *\r
+ * Will reduce to non-zero if there is new data for the application\r
+ * present at the uip_appdata pointer. The size of the data is\r
+ * avaliable through the uip_len variable.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_newdata() (uip_flags & UIP_NEWDATA)\r
+\r
+/**\r
+ * Has previously sent data been acknowledged?\r
+ *\r
+ * Will reduce to non-zero if the previously sent data has been\r
+ * acknowledged by the remote host. This means that the application\r
+ * can send new data.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_acked() (uip_flags & UIP_ACKDATA)\r
+\r
+/**\r
+ * Has the connection just been connected?\r
+ *\r
+ * Reduces to non-zero if the current connection has been connected to\r
+ * a remote host. This will happen both if the connection has been\r
+ * actively opened (with uip_connect()) or passively opened (with\r
+ * uip_listen()).\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_connected() (uip_flags & UIP_CONNECTED)\r
+\r
+/**\r
+ * Has the connection been closed by the other end?\r
+ *\r
+ * Is non-zero if the connection has been closed by the remote\r
+ * host. The application may then do the necessary clean-ups.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_closed() (uip_flags & UIP_CLOSE)\r
+\r
+/**\r
+ * Has the connection been aborted by the other end?\r
+ *\r
+ * Non-zero if the current connection has been aborted (reset) by the\r
+ * remote host.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_aborted() (uip_flags & UIP_ABORT)\r
+\r
+/**\r
+ * Has the connection timed out?\r
+ *\r
+ * Non-zero if the current connection has been aborted due to too many\r
+ * retransmissions.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_timedout() (uip_flags & UIP_TIMEDOUT)\r
+\r
+/**\r
+ * Do we need to retransmit previously data?\r
+ *\r
+ * Reduces to non-zero if the previously sent data has been lost in\r
+ * the network, and the application should retransmit it. The\r
+ * application should send the exact same data as it did the last\r
+ * time, using the uip_send() function.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_rexmit() (uip_flags & UIP_REXMIT)\r
+\r
+/**\r
+ * Is the connection being polled by uIP?\r
+ *\r
+ * Is non-zero if the reason the application is invoked is that the\r
+ * current connection has been idle for a while and should be\r
+ * polled.\r
+ *\r
+ * The polling event can be used for sending data without having to\r
+ * wait for the remote host to send data.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_poll() (uip_flags & UIP_POLL)\r
+\r
+/**\r
+ * Get the initial maxium segment size (MSS) of the current\r
+ * connection.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_initialmss() (uip_conn->initialmss)\r
+\r
+/**\r
+ * Get the current maxium segment size that can be sent on the current\r
+ * connection.\r
+ *\r
+ * The current maxiumum segment size that can be sent on the\r
+ * connection is computed from the receiver's window and the MSS of\r
+ * the connection (which also is available by calling\r
+ * uip_initialmss()).\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_mss() (uip_conn->mss)\r
+\r
+/**\r
+ * Set up a new UDP connection.\r
+ *\r
+ * \param ripaddr A pointer to a 4-byte structure representing the IP\r
+ * address of the remote host.\r
+ *\r
+ * \param rport The remote port number in network byte order.\r
+ *\r
+ * \return The uip_udp_conn structure for the new connection or NULL\r
+ * if no connection could be allocated.\r
+ */\r
+struct uip_udp_conn *uip_udp_new(u16_t *ripaddr, u16_t rport);\r
+\r
+/**\r
+ * Removed a UDP connection.\r
+ *\r
+ * \param conn A pointer to the uip_udp_conn structure for the connection.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_udp_remove(conn) (conn)->lport = 0\r
+\r
+/**\r
+ * Send a UDP datagram of length len on the current connection.\r
+ *\r
+ * This function can only be called in response to a UDP event (poll\r
+ * or newdata). The data must be present in the uip_buf buffer, at the\r
+ * place pointed to by the uip_appdata pointer.\r
+ *\r
+ * \param len The length of the data in the uip_buf buffer.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_udp_send(len) uip_slen = (len)\r
+\r
+/** @} */\r
+\r
+/* uIP convenience and converting functions. */\r
+\r
+/**\r
+ * \defgroup uipconvfunc uIP conversion functions\r
+ * @{\r
+ *\r
+ * These functions can be used for converting between different data\r
+ * formats used by uIP.\r
+ */\r
+\r
+/**\r
+ * Pack an IP address into a 4-byte array which is used by uIP to\r
+ * represent IP addresses.\r
+ *\r
+ * Example:\r
+ \code\r
+ u16_t ipaddr[2];\r
+\r
+ uip_ipaddr(&ipaddr, 192,168,1,2);\r
+ \endcode\r
+ *\r
+ * \param addr A pointer to a 4-byte array that will be filled in with\r
+ * the IP addres.\r
+ * \param addr0 The first octet of the IP address.\r
+ * \param addr1 The second octet of the IP address.\r
+ * \param addr2 The third octet of the IP address.\r
+ * \param addr3 The forth octet of the IP address.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_ipaddr(addr, addr0,addr1,addr2,addr3) do { \\r
+ (addr)[0] = HTONS(((addr0) << 8) | (addr1)); \\r
+ (addr)[1] = HTONS(((addr2) << 8) | (addr3)); \\r
+ } while(0)\r
+\r
+/**\r
+ * Convert 16-bit quantity from host byte order to network byte order.\r
+ *\r
+ * This macro is primarily used for converting constants from host\r
+ * byte order to network byte order. For converting variables to\r
+ * network byte order, use the htons() function instead.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#ifndef HTONS\r
+# if BYTE_ORDER == BIG_ENDIAN\r
+# define HTONS(n) (n)\r
+# else /* BYTE_ORDER == BIG_ENDIAN */\r
+# define HTONS(n) ((((u16_t)((n) & 0xff)) << 8) | (((n) & 0xff00) >> 8))\r
+# endif /* BYTE_ORDER == BIG_ENDIAN */\r
+#endif /* HTONS */\r
+\r
+/**\r
+ * Convert 16-bit quantity from host byte order to network byte order.\r
+ *\r
+ * This function is primarily used for converting variables from host\r
+ * byte order to network byte order. For converting constants to\r
+ * network byte order, use the HTONS() macro instead.\r
+ */\r
+#ifndef htons\r
+u16_t htons(u16_t val);\r
+#endif /* htons */\r
+\r
+/** @} */\r
+\r
+/**\r
+ * Pointer to the application data in the packet buffer.\r
+ *\r
+ * This pointer points to the application data when the application is\r
+ * called. If the application wishes to send data, the application may\r
+ * use this space to write the data into before calling uip_send().\r
+ */\r
+extern volatile u8_t *uip_appdata;\r
+extern volatile u8_t *uip_sappdata;\r
+\r
+#if UIP_URGDATA > 0\r
+/* u8_t *uip_urgdata:\r
+ *\r
+ * This pointer points to any urgent data that has been received. Only\r
+ * present if compiled with support for urgent data (UIP_URGDATA).\r
+ */\r
+extern volatile u8_t *uip_urgdata;\r
+#endif /* UIP_URGDATA > 0 */\r
+\r
+\r
+/* u[8|16]_t uip_len:\r
+ *\r
+ * When the application is called, uip_len contains the length of any\r
+ * new data that has been received from the remote host. The\r
+ * application should set this variable to the size of any data that\r
+ * the application wishes to send. When the network device driver\r
+ * output function is called, uip_len should contain the length of the\r
+ * outgoing packet.\r
+ */\r
+extern volatile u16_t uip_len, uip_slen;\r
+\r
+#if UIP_URGDATA > 0\r
+extern volatile u8_t uip_urglen, uip_surglen;\r
+#endif /* UIP_URGDATA > 0 */\r
+\r
+\r
+/**\r
+ * Representation of a uIP TCP connection.\r
+ *\r
+ * The uip_conn structure is used for identifying a connection. All\r
+ * but one field in the structure are to be considered read-only by an\r
+ * application. The only exception is the appstate field whos purpose\r
+ * is to let the application store application-specific state (e.g.,\r
+ * file pointers) for the connection. The size of this field is\r
+ * configured in the "uipopt.h" header file.\r
+ */\r
+struct uip_conn {\r
+ u16_t ripaddr[2]; /**< The IP address of the remote host. */\r
+\r
+ u16_t lport; /**< The local TCP port, in network byte order. */\r
+ u16_t rport; /**< The local remote TCP port, in network byte\r
+ order. */\r
+\r
+ u8_t rcv_nxt[4]; /**< The sequence number that we expect to\r
+ receive next. */\r
+ u8_t snd_nxt[4]; /**< The sequence number that was last sent by\r
+ us. */\r
+ u16_t len; /**< Length of the data that was previously sent. */\r
+ u16_t mss; /**< Current maximum segment size for the\r
+ connection. */\r
+ u16_t initialmss; /**< Initial maximum segment size for the\r
+ connection. */\r
+ u8_t sa; /**< Retransmission time-out calculation state\r
+ variable. */\r
+ u8_t sv; /**< Retransmission time-out calculation state\r
+ variable. */\r
+ u8_t rto; /**< Retransmission time-out. */\r
+ u8_t tcpstateflags; /**< TCP state and flags. */\r
+ u8_t timer; /**< The retransmission timer. */\r
+ u8_t nrtx; /**< The number of retransmissions for the last\r
+ segment sent. */\r
+\r
+ /** The application state. */\r
+ u8_t appstate[UIP_APPSTATE_SIZE];\r
+};\r
+\r
+\r
+/* Pointer to the current connection. */\r
+extern struct uip_conn *uip_conn;\r
+/* The array containing all uIP connections. */\r
+extern struct uip_conn uip_conns[UIP_CONNS];\r
+/**\r
+ * \addtogroup uiparch\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * 4-byte array used for the 32-bit sequence number calculations.\r
+ */\r
+extern volatile u8_t uip_acc32[4];\r
+\r
+/** @} */\r
+\r
+\r
+#if UIP_UDP\r
+/**\r
+ * Representation of a uIP UDP connection.\r
+ */\r
+struct uip_udp_conn {\r
+ u16_t ripaddr[2]; /**< The IP address of the remote peer. */\r
+ u16_t lport; /**< The local port number in network byte order. */\r
+ u16_t rport; /**< The remote port number in network byte order. */\r
+};\r
+\r
+extern struct uip_udp_conn *uip_udp_conn;\r
+extern struct uip_udp_conn uip_udp_conns[UIP_UDP_CONNS];\r
+#endif /* UIP_UDP */\r
+\r
+/**\r
+ * The structure holding the TCP/IP statistics that are gathered if\r
+ * UIP_STATISTICS is set to 1.\r
+ *\r
+ */\r
+struct uip_stats {\r
+ struct {\r
+ uip_stats_t drop; /**< Number of dropped packets at the IP\r
+ layer. */\r
+ uip_stats_t recv; /**< Number of received packets at the IP\r
+ layer. */\r
+ uip_stats_t sent; /**< Number of sent packets at the IP\r
+ layer. */\r
+ uip_stats_t vhlerr; /**< Number of packets dropped due to wrong\r
+ IP version or header length. */\r
+ uip_stats_t hblenerr; /**< Number of packets dropped due to wrong\r
+ IP length, high byte. */\r
+ uip_stats_t lblenerr; /**< Number of packets dropped due to wrong\r
+ IP length, low byte. */\r
+ uip_stats_t fragerr; /**< Number of packets dropped since they\r
+ were IP fragments. */\r
+ uip_stats_t chkerr; /**< Number of packets dropped due to IP\r
+ checksum errors. */\r
+ uip_stats_t protoerr; /**< Number of packets dropped since they\r
+ were neither ICMP, UDP nor TCP. */\r
+ } ip; /**< IP statistics. */\r
+ struct {\r
+ uip_stats_t drop; /**< Number of dropped ICMP packets. */\r
+ uip_stats_t recv; /**< Number of received ICMP packets. */\r
+ uip_stats_t sent; /**< Number of sent ICMP packets. */\r
+ uip_stats_t typeerr; /**< Number of ICMP packets with a wrong\r
+ type. */\r
+ } icmp; /**< ICMP statistics. */\r
+ struct {\r
+ uip_stats_t drop; /**< Number of dropped TCP segments. */\r
+ uip_stats_t recv; /**< Number of recived TCP segments. */\r
+ uip_stats_t sent; /**< Number of sent TCP segments. */\r
+ uip_stats_t chkerr; /**< Number of TCP segments with a bad\r
+ checksum. */\r
+ uip_stats_t ackerr; /**< Number of TCP segments with a bad ACK\r
+ number. */\r
+ uip_stats_t rst; /**< Number of recevied TCP RST (reset) segments. */\r
+ uip_stats_t rexmit; /**< Number of retransmitted TCP segments. */\r
+ uip_stats_t syndrop; /**< Number of dropped SYNs due to too few\r
+ connections was avaliable. */\r
+ uip_stats_t synrst; /**< Number of SYNs for closed ports,\r
+ triggering a RST. */\r
+ } tcp; /**< TCP statistics. */\r
+};\r
+\r
+/**\r
+ * The uIP TCP/IP statistics.\r
+ *\r
+ * This is the variable in which the uIP TCP/IP statistics are gathered.\r
+ */\r
+extern struct uip_stats uip_stat;\r
+\r
+\r
+/*-----------------------------------------------------------------------------------*/\r
+/* All the stuff below this point is internal to uIP and should not be\r
+ * used directly by an application or by a device driver.\r
+ */\r
+/*-----------------------------------------------------------------------------------*/\r
+/* u8_t uip_flags:\r
+ *\r
+ * When the application is called, uip_flags will contain the flags\r
+ * that are defined in this file. Please read below for more\r
+ * infomation.\r
+ */\r
+extern volatile u8_t uip_flags;\r
+\r
+/* The following flags may be set in the global variable uip_flags\r
+ before calling the application callback. The UIP_ACKDATA and\r
+ UIP_NEWDATA flags may both be set at the same time, whereas the\r
+ others are mutualy exclusive. Note that these flags should *NOT* be\r
+ accessed directly, but through the uIP functions/macros. */\r
+\r
+#define UIP_ACKDATA 1 /* Signifies that the outstanding data was\r
+ acked and the application should send\r
+ out new data instead of retransmitting\r
+ the last data. */\r
+#define UIP_NEWDATA 2 /* Flags the fact that the peer has sent\r
+ us new data. */\r
+#define UIP_REXMIT 4 /* Tells the application to retransmit the\r
+ data that was last sent. */\r
+#define UIP_POLL 8 /* Used for polling the application, to\r
+ check if the application has data that\r
+ it wants to send. */\r
+#define UIP_CLOSE 16 /* The remote host has closed the\r
+ connection, thus the connection has\r
+ gone away. Or the application signals\r
+ that it wants to close the\r
+ connection. */\r
+#define UIP_ABORT 32 /* The remote host has aborted the\r
+ connection, thus the connection has\r
+ gone away. Or the application signals\r
+ that it wants to abort the\r
+ connection. */\r
+#define UIP_CONNECTED 64 /* We have got a connection from a remote\r
+ host and have set up a new connection\r
+ for it, or an active connection has\r
+ been successfully established. */\r
+\r
+#define UIP_TIMEDOUT 128 /* The connection has been aborted due to\r
+ too many retransmissions. */\r
+\r
+\r
+/* uip_process(flag):\r
+ *\r
+ * The actual uIP function which does all the work.\r
+ */\r
+void uip_process(u8_t flag);\r
+\r
+/* The following flags are passed as an argument to the uip_process()\r
+ function. They are used to distinguish between the two cases where\r
+ uip_process() is called. It can be called either because we have\r
+ incoming data that should be processed, or because the periodic\r
+ timer has fired. */\r
+\r
+#define UIP_DATA 1 /* Tells uIP that there is incoming data in\r
+ the uip_buf buffer. The length of the\r
+ data is stored in the global variable\r
+ uip_len. */\r
+#define UIP_TIMER 2 /* Tells uIP that the periodic timer has\r
+ fired. */\r
+#if UIP_UDP\r
+#define UIP_UDP_TIMER 3\r
+#endif /* UIP_UDP */\r
+\r
+/* The TCP states used in the uip_conn->tcpstateflags. */\r
+#define CLOSED 0\r
+#define SYN_RCVD 1\r
+#define SYN_SENT 2\r
+#define ESTABLISHED 3\r
+#define FIN_WAIT_1 4\r
+#define FIN_WAIT_2 5\r
+#define CLOSING 6\r
+#define TIME_WAIT 7\r
+#define LAST_ACK 8\r
+#define TS_MASK 15\r
+\r
+#define UIP_STOPPED 16\r
+\r
+#define UIP_TCPIP_HLEN 40\r
+\r
+/* The TCP and IP headers. */\r
+typedef struct {\r
+ /* IP header. */\r
+ u8_t vhl,\r
+ tos,\r
+ len[2],\r
+ ipid[2],\r
+ ipoffset[2],\r
+ ttl,\r
+ proto;\r
+ u16_t ipchksum;\r
+ u16_t srcipaddr[2],\r
+ destipaddr[2];\r
+\r
+ /* TCP header. */\r
+ u16_t srcport,\r
+ destport;\r
+ u8_t seqno[4],\r
+ ackno[4],\r
+ tcpoffset,\r
+ flags,\r
+ wnd[2];\r
+ u16_t tcpchksum;\r
+ u8_t urgp[2];\r
+ u8_t optdata[4];\r
+} uip_tcpip_hdr;\r
+\r
+/* The ICMP and IP headers. */\r
+typedef struct {\r
+ /* IP header. */\r
+ u8_t vhl,\r
+ tos,\r
+ len[2],\r
+ ipid[2],\r
+ ipoffset[2],\r
+ ttl,\r
+ proto;\r
+ u16_t ipchksum;\r
+ u16_t srcipaddr[2],\r
+ destipaddr[2];\r
+ /* ICMP (echo) header. */\r
+ u8_t type, icode;\r
+ u16_t icmpchksum;\r
+ u16_t id, seqno;\r
+} uip_icmpip_hdr;\r
+\r
+\r
+/* The UDP and IP headers. */\r
+typedef struct {\r
+ /* IP header. */\r
+ u8_t vhl,\r
+ tos,\r
+ len[2],\r
+ ipid[2],\r
+ ipoffset[2],\r
+ ttl,\r
+ proto;\r
+ u16_t ipchksum;\r
+ u16_t srcipaddr[2],\r
+ destipaddr[2];\r
+\r
+ /* UDP header. */\r
+ u16_t srcport,\r
+ destport;\r
+ u16_t udplen;\r
+ u16_t udpchksum;\r
+} uip_udpip_hdr;\r
+\r
+#define UIP_PROTO_ICMP 1\r
+#define UIP_PROTO_TCP 6\r
+#define UIP_PROTO_UDP 17\r
+\r
+#if UIP_FIXEDADDR\r
+extern const u16_t uip_hostaddr[2];\r
+#else /* UIP_FIXEDADDR */\r
+extern u16_t uip_hostaddr[2];\r
+#endif /* UIP_FIXEDADDR */\r
+\r
+#endif /* __UIP_H__ */\r
+\r
+\r
+/** @} */\r
+\r
--- /dev/null
+/*\r
+ * Copyright (c) 2001, Adam Dunkels.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ * 3. The name of the author may not be used to endorse or promote\r
+ * products derived from this software without specific prior\r
+ * written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * $Id: uip_arch.c,v 1.2.2.1 2003/10/04 22:54:17 adam Exp $\r
+ *\r
+ */\r
+\r
+\r
+#include "uip.h"\r
+#include "uip_arch.h"\r
+\r
+#define BUF ((uip_tcpip_hdr *)&uip_buf[UIP_LLH_LEN])\r
+#define IP_PROTO_TCP 6\r
+\r
+/*-----------------------------------------------------------------------------------*/\r
+void\r
+uip_add32(u8_t *op32, u16_t op16)\r
+{\r
+\r
+ uip_acc32[3] = op32[3] + (op16 & 0xff);\r
+ uip_acc32[2] = op32[2] + (op16 >> 8);\r
+ uip_acc32[1] = op32[1];\r
+ uip_acc32[0] = op32[0];\r
+\r
+ if(uip_acc32[2] < (op16 >> 8)) {\r
+ ++uip_acc32[1];\r
+ if(uip_acc32[1] == 0) {\r
+ ++uip_acc32[0];\r
+ }\r
+ }\r
+\r
+\r
+ if(uip_acc32[3] < (op16 & 0xff)) {\r
+ ++uip_acc32[2];\r
+ if(uip_acc32[2] == 0) {\r
+ ++uip_acc32[1];\r
+ if(uip_acc32[1] == 0) {\r
+ ++uip_acc32[0];\r
+ }\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+u16_t\r
+uip_chksum(u16_t *sdata, u16_t len)\r
+{\r
+ u16_t acc;\r
+\r
+ for (acc = 0; len > 1; len -= 2) {\r
+ u16_t u = ((unsigned char *)sdata)[0] + (((unsigned char *)sdata)[1] << 8);\r
+ if ((acc += u) < u) {\r
+ /* Overflow, so we add the carry to acc (i.e., increase by\r
+ one). */\r
+ ++acc;\r
+ }\r
+ ++sdata;\r
+ }\r
+\r
+ /* add up any odd byte */\r
+ if(len == 1) {\r
+ acc += htons(((u16_t)(*(u8_t *)sdata)) << 8);\r
+ if(acc < htons(((u16_t)(*(u8_t *)sdata)) << 8)) {\r
+ ++acc;\r
+ }\r
+ }\r
+\r
+ return acc;\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+u16_t\r
+uip_ipchksum(void)\r
+{\r
+ return uip_chksum((u16_t *)&uip_buf[UIP_LLH_LEN], 20);\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+u16_t\r
+uip_tcpchksum(void)\r
+{\r
+ u16_t hsum, sum;\r
+\r
+\r
+ /* Compute the checksum of the TCP header. */\r
+ hsum = uip_chksum((u16_t *)&uip_buf[20 + UIP_LLH_LEN], 20);\r
+\r
+ /* Compute the checksum of the data in the TCP packet and add it to\r
+ the TCP header checksum. */\r
+ sum = uip_chksum((u16_t *)uip_appdata,\r
+ (u16_t)(((((u16_t)(BUF->len[0]) << 8) + BUF->len[1]) - 40)));\r
+\r
+ if((sum += hsum) < hsum) {\r
+ ++sum;\r
+ }\r
+\r
+ if((sum += BUF->srcipaddr[0]) < BUF->srcipaddr[0]) {\r
+ ++sum;\r
+ }\r
+ if((sum += BUF->srcipaddr[1]) < BUF->srcipaddr[1]) {\r
+ ++sum;\r
+ }\r
+ if((sum += BUF->destipaddr[0]) < BUF->destipaddr[0]) {\r
+ ++sum;\r
+ }\r
+ if((sum += BUF->destipaddr[1]) < BUF->destipaddr[1]) {\r
+ ++sum;\r
+ }\r
+ if((sum += (u16_t)htons((u16_t)IP_PROTO_TCP)) < (u16_t)htons((u16_t)IP_PROTO_TCP)) {\r
+ ++sum;\r
+ }\r
+\r
+ hsum = (u16_t)htons((((u16_t)(BUF->len[0]) << 8) + BUF->len[1]) - 20);\r
+\r
+ if((sum += hsum) < hsum) {\r
+ ++sum;\r
+ }\r
+\r
+ return sum;\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
--- /dev/null
+/**\r
+ * \defgroup uiparch Architecture specific uIP functions\r
+ * @{\r
+ *\r
+ * The functions in the architecture specific module implement the IP\r
+ * check sum and 32-bit additions.\r
+ *\r
+ * The IP checksum calculation is the most computationally expensive\r
+ * operation in the TCP/IP stack and it therefore pays off to\r
+ * implement this in efficient assembler. The purpose of the uip-arch\r
+ * module is to let the checksum functions to be implemented in\r
+ * architecture specific assembler.\r
+ *\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * Declarations of architecture specific functions.\r
+ * \author Adam Dunkels <adam@dunkels.com>\r
+ */\r
+\r
+/*\r
+ * Copyright (c) 2001, Adam Dunkels.\r
+ * All rights reserved. \r
+ *\r
+ * Redistribution and use in source and binary forms, with or without \r
+ * modification, are permitted provided that the following conditions \r
+ * are met: \r
+ * 1. Redistributions of source code must retain the above copyright \r
+ * notice, this list of conditions and the following disclaimer. \r
+ * 2. Redistributions in binary form must reproduce the above copyright \r
+ * notice, this list of conditions and the following disclaimer in the \r
+ * documentation and/or other materials provided with the distribution. \r
+ * 3. The name of the author may not be used to endorse or promote\r
+ * products derived from this software without specific prior\r
+ * written permission. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * $Id: uip_arch.h,v 1.1.2.2 2003/10/06 15:10:22 adam Exp $\r
+ *\r
+ */\r
+\r
+#ifndef __UIP_ARCH_H__\r
+#define __UIP_ARCH_H__\r
+\r
+#include "uip.h"\r
+\r
+/**\r
+ * Carry out a 32-bit addition.\r
+ *\r
+ * Because not all architectures for which uIP is intended has native\r
+ * 32-bit arithmetic, uIP uses an external C function for doing the\r
+ * required 32-bit additions in the TCP protocol processing. This\r
+ * function should add the two arguments and place the result in the\r
+ * global variable uip_acc32.\r
+ *\r
+ * \note The 32-bit integer pointed to by the op32 parameter and the\r
+ * result in the uip_acc32 variable are in network byte order (big\r
+ * endian).\r
+ *\r
+ * \param op32 A pointer to a 4-byte array representing a 32-bit\r
+ * integer in network byte order (big endian).\r
+ *\r
+ * \param op16 A 16-bit integer in host byte order.\r
+ */\r
+void uip_add32(u8_t *op32, u16_t op16);\r
+\r
+/**\r
+ * Calculate the Internet checksum over a buffer.\r
+ *\r
+ * The Internet checksum is the one's complement of the one's\r
+ * complement sum of all 16-bit words in the buffer.\r
+ *\r
+ * See RFC1071.\r
+ *\r
+ * \note This function is not called in the current version of uIP,\r
+ * but future versions might make use of it.\r
+ *\r
+ * \param buf A pointer to the buffer over which the checksum is to be\r
+ * computed.\r
+ *\r
+ * \param len The length of the buffer over which the checksum is to\r
+ * be computed.\r
+ *\r
+ * \return The Internet checksum of the buffer.\r
+ */\r
+u16_t uip_chksum(u16_t *buf, u16_t len);\r
+\r
+/**\r
+ * Calculate the IP header checksum of the packet header in uip_buf.\r
+ *\r
+ * The IP header checksum is the Internet checksum of the 20 bytes of\r
+ * the IP header.\r
+ *\r
+ * \return The IP header checksum of the IP header in the uip_buf\r
+ * buffer.\r
+ */\r
+u16_t uip_ipchksum(void);\r
+\r
+/**\r
+ * Calculate the TCP checksum of the packet in uip_buf and uip_appdata.\r
+ *\r
+ * The TCP checksum is the Internet checksum of data contents of the\r
+ * TCP segment, and a pseudo-header as defined in RFC793.\r
+ *\r
+ * \note The uip_appdata pointer that points to the packet data may\r
+ * point anywhere in memory, so it is not possible to simply calculate\r
+ * the Internet checksum of the contents of the uip_buf buffer.\r
+ *\r
+ * \return The TCP checksum of the TCP segment in uip_buf and pointed\r
+ * to by uip_appdata.\r
+ */\r
+u16_t uip_tcpchksum(void);\r
+\r
+/** @} */\r
+\r
+#endif /* __UIP_ARCH_H__ */\r
--- /dev/null
+/**\r
+ * \addtogroup uip\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \defgroup uiparp uIP Address Resolution Protocol\r
+ * @{\r
+ *\r
+ * The Address Resolution Protocol ARP is used for mapping between IP\r
+ * addresses and link level addresses such as the Ethernet MAC\r
+ * addresses. ARP uses broadcast queries to ask for the link level\r
+ * address of a known IP address and the host which is configured with\r
+ * the IP address for which the query was meant, will respond with its\r
+ * link level address.\r
+ *\r
+ * \note This ARP implementation only supports Ethernet.\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * Implementation of the ARP Address Resolution Protocol.\r
+ * \author Adam Dunkels <adam@dunkels.com>\r
+ *\r
+ */\r
+\r
+/*\r
+ * Copyright (c) 2001-2003, Adam Dunkels.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ * 3. The name of the author may not be used to endorse or promote\r
+ * products derived from this software without specific prior\r
+ * written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * $Id: uip_arp.c,v 1.7.2.3 2003/10/06 22:42:30 adam Exp $\r
+ *\r
+ */\r
+\r
+\r
+#include "uip_arp.h"\r
+\r
+#include <string.h>\r
+\r
+struct arp_hdr {\r
+ struct uip_eth_hdr ethhdr;\r
+ u16_t hwtype;\r
+ u16_t protocol;\r
+ u8_t hwlen;\r
+ u8_t protolen;\r
+ u16_t opcode;\r
+ struct uip_eth_addr shwaddr;\r
+ u16_t sipaddr[2];\r
+ struct uip_eth_addr dhwaddr;\r
+ u16_t dipaddr[2];\r
+};\r
+\r
+struct ethip_hdr {\r
+ struct uip_eth_hdr ethhdr;\r
+ /* IP header. */\r
+ u8_t vhl,\r
+ tos,\r
+ len[2],\r
+ ipid[2],\r
+ ipoffset[2],\r
+ ttl,\r
+ proto;\r
+ u16_t ipchksum;\r
+ u16_t srcipaddr[2],\r
+ destipaddr[2];\r
+};\r
+\r
+#define ARP_REQUEST 1\r
+#define ARP_REPLY 2\r
+\r
+#define ARP_HWTYPE_ETH 1\r
+\r
+struct arp_entry {\r
+ u16_t ipaddr[2];\r
+ struct uip_eth_addr ethaddr;\r
+ u8_t time;\r
+};\r
+\r
+struct uip_eth_addr uip_ethaddr = {{UIP_ETHADDR0,\r
+ UIP_ETHADDR1,\r
+ UIP_ETHADDR2,\r
+ UIP_ETHADDR3,\r
+ UIP_ETHADDR4,\r
+ UIP_ETHADDR5}};\r
+\r
+static struct arp_entry arp_table[UIP_ARPTAB_SIZE];\r
+static u16_t ipaddr[2];\r
+static u8_t i, c;\r
+\r
+static u8_t arptime;\r
+static u8_t tmpage;\r
+\r
+#define BUF ((struct arp_hdr *)&uip_buf[0])\r
+#define IPBUF ((struct ethip_hdr *)&uip_buf[0])\r
+/*-----------------------------------------------------------------------------------*/\r
+/**\r
+ * Initialize the ARP module.\r
+ *\r
+ */\r
+/*-----------------------------------------------------------------------------------*/\r
+void\r
+uip_arp_init(void)\r
+{\r
+ for(i = 0; i < UIP_ARPTAB_SIZE; ++i) {\r
+ memset(arp_table[i].ipaddr, 0, 4);\r
+ }\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+/**\r
+ * Periodic ARP processing function.\r
+ *\r
+ * This function performs periodic timer processing in the ARP module\r
+ * and should be called at regular intervals. The recommended interval\r
+ * is 10 seconds between the calls.\r
+ *\r
+ */\r
+/*-----------------------------------------------------------------------------------*/\r
+void\r
+uip_arp_timer(void)\r
+{\r
+ struct arp_entry *tabptr;\r
+\r
+ ++arptime;\r
+ for(i = 0; i < UIP_ARPTAB_SIZE; ++i) {\r
+ tabptr = &arp_table[i];\r
+ if((tabptr->ipaddr[0] | tabptr->ipaddr[1]) != 0 &&\r
+ arptime - tabptr->time >= UIP_ARP_MAXAGE) {\r
+ memset(tabptr->ipaddr, 0, 4);\r
+ }\r
+ }\r
+\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+static void\r
+uip_arp_update(u16_t *ipaddr, struct uip_eth_addr *ethaddr)\r
+{\r
+ register struct arp_entry *tabptr;\r
+ /* Walk through the ARP mapping table and try to find an entry to\r
+ update. If none is found, the IP -> MAC address mapping is\r
+ inserted in the ARP table. */\r
+ for(i = 0; i < UIP_ARPTAB_SIZE; ++i) {\r
+\r
+ tabptr = &arp_table[i];\r
+ /* Only check those entries that are actually in use. */\r
+ if(tabptr->ipaddr[0] != 0 &&\r
+ tabptr->ipaddr[1] != 0) {\r
+\r
+ /* Check if the source IP address of the incoming packet matches\r
+ the IP address in this ARP table entry. */\r
+ if(ipaddr[0] == tabptr->ipaddr[0] &&\r
+ ipaddr[1] == tabptr->ipaddr[1]) {\r
+ \r
+ /* An old entry found, update this and return. */\r
+ memcpy(tabptr->ethaddr.addr, ethaddr->addr, 6);\r
+ tabptr->time = arptime;\r
+\r
+ return;\r
+ }\r
+ }\r
+ }\r
+\r
+ /* If we get here, no existing ARP table entry was found, so we\r
+ create one. */\r
+\r
+ /* First, we try to find an unused entry in the ARP table. */\r
+ for(i = 0; i < UIP_ARPTAB_SIZE; ++i) {\r
+ tabptr = &arp_table[i];\r
+ if(tabptr->ipaddr[0] == 0 &&\r
+ tabptr->ipaddr[1] == 0) {\r
+ break;\r
+ }\r
+ }\r
+\r
+ /* If no unused entry is found, we try to find the oldest entry and\r
+ throw it away. */\r
+ if(i == UIP_ARPTAB_SIZE) {\r
+ tmpage = 0;\r
+ c = 0;\r
+ for(i = 0; i < UIP_ARPTAB_SIZE; ++i) {\r
+ tabptr = &arp_table[i];\r
+ if(arptime - tabptr->time > tmpage) {\r
+ tmpage = arptime - tabptr->time;\r
+ c = i;\r
+ }\r
+ }\r
+ i = c;\r
+ }\r
+\r
+ /* Now, i is the ARP table entry which we will fill with the new\r
+ information. */\r
+ memcpy(tabptr->ipaddr, ipaddr, 4);\r
+ memcpy(tabptr->ethaddr.addr, ethaddr->addr, 6);\r
+ tabptr->time = arptime;\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+/**\r
+ * ARP processing for incoming IP packets\r
+ *\r
+ * This function should be called by the device driver when an IP\r
+ * packet has been received. The function will check if the address is\r
+ * in the ARP cache, and if so the ARP cache entry will be\r
+ * refreshed. If no ARP cache entry was found, a new one is created.\r
+ *\r
+ * This function expects an IP packet with a prepended Ethernet header\r
+ * in the uip_buf[] buffer, and the length of the packet in the global\r
+ * variable uip_len.\r
+ */\r
+/*-----------------------------------------------------------------------------------*/\r
+void\r
+uip_arp_ipin(void)\r
+{\r
+ uip_len -= sizeof(struct uip_eth_hdr);\r
+ \r
+ /* Only insert/update an entry if the source IP address of the\r
+ incoming IP packet comes from a host on the local network. */\r
+ if((IPBUF->srcipaddr[0] & uip_arp_netmask[0]) !=\r
+ (uip_hostaddr[0] & uip_arp_netmask[0])) {\r
+ return;\r
+ }\r
+ if((IPBUF->srcipaddr[1] & uip_arp_netmask[1]) !=\r
+ (uip_hostaddr[1] & uip_arp_netmask[1])) {\r
+ return;\r
+ }\r
+ uip_arp_update(IPBUF->srcipaddr, &(IPBUF->ethhdr.src));\r
+\r
+ return;\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+/**\r
+ * ARP processing for incoming ARP packets.\r
+ *\r
+ * This function should be called by the device driver when an ARP\r
+ * packet has been received. The function will act differently\r
+ * depending on the ARP packet type: if it is a reply for a request\r
+ * that we previously sent out, the ARP cache will be filled in with\r
+ * the values from the ARP reply. If the incoming ARP packet is an ARP\r
+ * request for our IP address, an ARP reply packet is created and put\r
+ * into the uip_buf[] buffer.\r
+ *\r
+ * When the function returns, the value of the global variable uip_len\r
+ * indicates whether the device driver should send out a packet or\r
+ * not. If uip_len is zero, no packet should be sent. If uip_len is\r
+ * non-zero, it contains the length of the outbound packet that is\r
+ * present in the uip_buf[] buffer.\r
+ *\r
+ * This function expects an ARP packet with a prepended Ethernet\r
+ * header in the uip_buf[] buffer, and the length of the packet in the\r
+ * global variable uip_len.\r
+ */\r
+/*-----------------------------------------------------------------------------------*/\r
+typedef struct arp_hdr aht;\r
+\r
+void\r
+uip_arp_arpin(void)\r
+{\r
+ int ul;\r
+\r
+ if(uip_len < sizeof(struct arp_hdr)) {\r
+ uip_len = 0;\r
+ return;\r
+ }\r
+\r
+ uip_len = 0;\r
+\r
+ switch(BUF->opcode) {\r
+ case HTONS(ARP_REQUEST):\r
+ /* ARP request. If it asked for our address, we send out a\r
+ reply. */\r
+ if(BUF->dipaddr[0] == uip_hostaddr[0] &&\r
+ BUF->dipaddr[1] == uip_hostaddr[1]) {\r
+ /* The reply opcode is 2. */\r
+ BUF->opcode = HTONS(2);\r
+\r
+ memcpy(BUF->dhwaddr.addr, BUF->shwaddr.addr, 6);\r
+ memcpy(BUF->shwaddr.addr, uip_ethaddr.addr, 6);\r
+ memcpy(BUF->ethhdr.src.addr, uip_ethaddr.addr, 6);\r
+ memcpy(BUF->ethhdr.dest.addr, BUF->dhwaddr.addr, 6);\r
+\r
+ BUF->dipaddr[0] = BUF->sipaddr[0];\r
+ BUF->dipaddr[1] = BUF->sipaddr[1];\r
+ BUF->sipaddr[0] = uip_hostaddr[0];\r
+ BUF->sipaddr[1] = uip_hostaddr[1];\r
+\r
+ ul = BUF->hwlen;\r
+ BUF->ethhdr.type = HTONS(UIP_ETHTYPE_ARP);\r
+ uip_len = sizeof(struct arp_hdr);\r
+ }\r
+ break;\r
+ case HTONS(ARP_REPLY):\r
+ /* ARP reply. We insert or update the ARP table if it was meant\r
+ for us. */\r
+ if(BUF->dipaddr[0] == uip_hostaddr[0] &&\r
+ BUF->dipaddr[1] == uip_hostaddr[1]) {\r
+\r
+ uip_arp_update(BUF->sipaddr, &BUF->shwaddr);\r
+ }\r
+ break;\r
+ }\r
+\r
+ ( void ) ul;\r
+\r
+ return;\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+/**\r
+ * Prepend Ethernet header to an outbound IP packet and see if we need\r
+ * to send out an ARP request.\r
+ *\r
+ * This function should be called before sending out an IP packet. The\r
+ * function checks the destination IP address of the IP packet to see\r
+ * what Ethernet MAC address that should be used as a destination MAC\r
+ * address on the Ethernet.\r
+ *\r
+ * If the destination IP address is in the local network (determined\r
+ * by logical ANDing of netmask and our IP address), the function\r
+ * checks the ARP cache to see if an entry for the destination IP\r
+ * address is found. If so, an Ethernet header is prepended and the\r
+ * function returns. If no ARP cache entry is found for the\r
+ * destination IP address, the packet in the uip_buf[] is replaced by\r
+ * an ARP request packet for the IP address. The IP packet is dropped\r
+ * and it is assumed that they higher level protocols (e.g., TCP)\r
+ * eventually will retransmit the dropped packet.\r
+ *\r
+ * If the destination IP address is not on the local network, the IP\r
+ * address of the default router is used instead.\r
+ *\r
+ * When the function returns, a packet is present in the uip_buf[]\r
+ * buffer, and the length of the packet is in the global variable\r
+ * uip_len.\r
+ */\r
+/*-----------------------------------------------------------------------------------*/\r
+void\r
+uip_arp_out(void)\r
+{\r
+ struct arp_entry *tabptr;\r
+ /* Find the destination IP address in the ARP table and construct\r
+ the Ethernet header. If the destination IP addres isn't on the\r
+ local network, we use the default router's IP address instead.\r
+\r
+ If not ARP table entry is found, we overwrite the original IP\r
+ packet with an ARP request for the IP address. */\r
+\r
+ /* Check if the destination address is on the local network. */\r
+ if((IPBUF->destipaddr[0] & uip_arp_netmask[0]) !=\r
+ (uip_hostaddr[0] & uip_arp_netmask[0]) ||\r
+ (IPBUF->destipaddr[1] & uip_arp_netmask[1]) !=\r
+ (uip_hostaddr[1] & uip_arp_netmask[1])) {\r
+ /* Destination address was not on the local network, so we need to\r
+ use the default router's IP address instead of the destination\r
+ address when determining the MAC address. */\r
+ ipaddr[0] = uip_arp_draddr[0];\r
+ ipaddr[1] = uip_arp_draddr[1];\r
+ } else {\r
+ /* Else, we use the destination IP address. */\r
+ ipaddr[0] = IPBUF->destipaddr[0];\r
+ ipaddr[1] = IPBUF->destipaddr[1];\r
+ }\r
+\r
+ for(i = 0; i < UIP_ARPTAB_SIZE; ++i) {\r
+ tabptr = &arp_table[i];\r
+ if(ipaddr[0] == tabptr->ipaddr[0] &&\r
+ ipaddr[1] == tabptr->ipaddr[1])\r
+ break;\r
+ }\r
+\r
+ if(i == UIP_ARPTAB_SIZE) {\r
+ /* The destination address was not in our ARP table, so we\r
+ overwrite the IP packet with an ARP request. */\r
+\r
+ memset(BUF->ethhdr.dest.addr, 0xff, 6);\r
+ memset(BUF->dhwaddr.addr, 0x00, 6);\r
+ memcpy(BUF->ethhdr.src.addr, uip_ethaddr.addr, 6);\r
+ memcpy(BUF->shwaddr.addr, uip_ethaddr.addr, 6);\r
+\r
+ BUF->dipaddr[0] = ipaddr[0];\r
+ BUF->dipaddr[1] = ipaddr[1];\r
+ BUF->sipaddr[0] = uip_hostaddr[0];\r
+ BUF->sipaddr[1] = uip_hostaddr[1];\r
+ BUF->opcode = HTONS(ARP_REQUEST); /* ARP request. */\r
+ BUF->hwtype = HTONS(ARP_HWTYPE_ETH);\r
+ BUF->protocol = HTONS(UIP_ETHTYPE_IP);\r
+ BUF->hwlen = 6;\r
+ BUF->protolen = 4;\r
+ BUF->ethhdr.type = HTONS(UIP_ETHTYPE_ARP);\r
+\r
+ uip_appdata = &uip_buf[40 + UIP_LLH_LEN];\r
+\r
+ uip_len = sizeof(struct arp_hdr);\r
+ return;\r
+ }\r
+\r
+ /* Build an ethernet header. */\r
+ memcpy(IPBUF->ethhdr.dest.addr, tabptr->ethaddr.addr, 6);\r
+ memcpy(IPBUF->ethhdr.src.addr, uip_ethaddr.addr, 6);\r
+\r
+ IPBUF->ethhdr.type = HTONS(UIP_ETHTYPE_IP);\r
+\r
+ uip_len += sizeof(struct uip_eth_hdr);\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+\r
+/** @} */\r
+/** @} */\r
--- /dev/null
+/**\r
+ * \addtogroup uip\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \addtogroup uiparp\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * Macros and definitions for the ARP module.\r
+ * \author Adam Dunkels <adam@dunkels.com>\r
+ */\r
+\r
+\r
+/*\r
+ * Copyright (c) 2001-2003, Adam Dunkels.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ * 3. The name of the author may not be used to endorse or promote\r
+ * products derived from this software without specific prior\r
+ * written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * $Id: uip_arp.h,v 1.3.2.2 2003/10/06 15:10:22 adam Exp $\r
+ *\r
+ */\r
+\r
+#ifndef __UIP_ARP_H__\r
+#define __UIP_ARP_H__\r
+\r
+#include "uip.h"\r
+\r
+\r
+/**\r
+ * Representation of a 48-bit Ethernet address.\r
+ */\r
+struct uip_eth_addr {\r
+ u8_t addr[6];\r
+} /*_RB_ __attribute__ ((packed, aligned (1))) */;\r
+\r
+extern struct uip_eth_addr uip_ethaddr;\r
+\r
+/**\r
+ * The Ethernet header.\r
+ */\r
+struct uip_eth_hdr {\r
+ struct uip_eth_addr dest;\r
+ struct uip_eth_addr src;\r
+ u16_t type;\r
+} /*_RB_ __attribute__ ((packed)) */;\r
+\r
+#define UIP_ETHTYPE_ARP 0x0806\r
+#define UIP_ETHTYPE_IP 0x0800\r
+#define UIP_ETHTYPE_IP6 0x86dd\r
+\r
+\r
+/* The uip_arp_init() function must be called before any of the other\r
+ ARP functions. */\r
+void uip_arp_init(void);\r
+\r
+/* The uip_arp_ipin() function should be called whenever an IP packet\r
+ arrives from the Ethernet. This function refreshes the ARP table or\r
+ inserts a new mapping if none exists. The function assumes that an\r
+ IP packet with an Ethernet header is present in the uip_buf buffer\r
+ and that the length of the packet is in the uip_len variable. */\r
+void uip_arp_ipin(void);\r
+\r
+/* The uip_arp_arpin() should be called when an ARP packet is received\r
+ by the Ethernet driver. This function also assumes that the\r
+ Ethernet frame is present in the uip_buf buffer. When the\r
+ uip_arp_arpin() function returns, the contents of the uip_buf\r
+ buffer should be sent out on the Ethernet if the uip_len variable\r
+ is > 0. */\r
+void uip_arp_arpin(void);\r
+\r
+/* The uip_arp_out() function should be called when an IP packet\r
+ should be sent out on the Ethernet. This function creates an\r
+ Ethernet header before the IP header in the uip_buf buffer. The\r
+ Ethernet header will have the correct Ethernet MAC destination\r
+ address filled in if an ARP table entry for the destination IP\r
+ address (or the IP address of the default router) is present. If no\r
+ such table entry is found, the IP packet is overwritten with an ARP\r
+ request and we rely on TCP to retransmit the packet that was\r
+ overwritten. In any case, the uip_len variable holds the length of\r
+ the Ethernet frame that should be transmitted. */\r
+void uip_arp_out(void);\r
+\r
+/* The uip_arp_timer() function should be called every ten seconds. It\r
+ is responsible for flushing old entries in the ARP table. */\r
+void uip_arp_timer(void);\r
+\r
+/** @} */\r
+\r
+/**\r
+ * \addtogroup uipconffunc\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * Set the default router's IP address.\r
+ *\r
+ * \param addr A pointer to a 4-byte array containing the IP address\r
+ * of the default router.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_setdraddr(addr) do { uip_arp_draddr[0] = addr[0]; \\r
+ uip_arp_draddr[1] = addr[1]; } while(0)\r
+\r
+/**\r
+ * Set the netmask.\r
+ *\r
+ * \param addr A pointer to a 4-byte array containing the IP address\r
+ * of the netmask.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_setnetmask(addr) do { uip_arp_netmask[0] = addr[0]; \\r
+ uip_arp_netmask[1] = addr[1]; } while(0)\r
+\r
+\r
+/**\r
+ * Get the default router's IP address.\r
+ *\r
+ * \param addr A pointer to a 4-byte array that will be filled in with\r
+ * the IP address of the default router.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_getdraddr(addr) do { addr[0] = uip_arp_draddr[0]; \\r
+ addr[1] = uip_arp_draddr[1]; } while(0)\r
+\r
+/**\r
+ * Get the netmask.\r
+ *\r
+ * \param addr A pointer to a 4-byte array that will be filled in with\r
+ * the value of the netmask.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_getnetmask(addr) do { addr[0] = uip_arp_netmask[0]; \\r
+ addr[1] = uip_arp_netmask[1]; } while(0)\r
+\r
+\r
+/**\r
+ * Specifiy the Ethernet MAC address.\r
+ *\r
+ * The ARP code needs to know the MAC address of the Ethernet card in\r
+ * order to be able to respond to ARP queries and to generate working\r
+ * Ethernet headers.\r
+ *\r
+ * \note This macro only specifies the Ethernet MAC address to the ARP\r
+ * code. It cannot be used to change the MAC address of the Ethernet\r
+ * card.\r
+ *\r
+ * \param eaddr A pointer to a struct uip_eth_addr containing the\r
+ * Ethernet MAC address of the Ethernet card.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_setethaddr(eaddr) do {uip_ethaddr.addr[0] = eaddr.addr[0]; \\r
+ uip_ethaddr.addr[1] = eaddr.addr[1];\\r
+ uip_ethaddr.addr[2] = eaddr.addr[2];\\r
+ uip_ethaddr.addr[3] = eaddr.addr[3];\\r
+ uip_ethaddr.addr[4] = eaddr.addr[4];\\r
+ uip_ethaddr.addr[5] = eaddr.addr[5];} while(0)\r
+\r
+/** @} */\r
+\r
+/**\r
+ * \internal Internal variables that are set using the macros\r
+ * uip_setdraddr and uip_setnetmask.\r
+ */\r
+extern u16_t uip_arp_draddr[2], uip_arp_netmask[2];\r
+#endif /* __UIP_ARP_H__ */\r
+\r
+\r
--- /dev/null
+/**\r
+ * \defgroup uipopt Configuration options for uIP\r
+ * @{\r
+ *\r
+ * uIP is configured using the per-project configuration file\r
+ * "uipopt.h". This file contains all compile-time options for uIP and\r
+ * should be tweaked to match each specific project. The uIP\r
+ * distribution contains a documented example "uipopt.h" that can be\r
+ * copied and modified for each project.\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * Configuration options for uIP.\r
+ * \author Adam Dunkels <adam@dunkels.com>\r
+ *\r
+ * This file is used for tweaking various configuration options for\r
+ * uIP. You should make a copy of this file into one of your project's\r
+ * directories instead of editing this example "uipopt.h" file that\r
+ * comes with the uIP distribution.\r
+ */\r
+\r
+/*\r
+ * Copyright (c) 2001-2003, Adam Dunkels.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ * 3. The name of the author may not be used to endorse or promote\r
+ * products derived from this software without specific prior\r
+ * written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * $Id: uipopt.h,v 1.16.2.5 2003/10/07 13:22:51 adam Exp $\r
+ *\r
+ */\r
+\r
+#ifndef __UIPOPT_H__\r
+#define __UIPOPT_H__\r
+\r
+/*------------------------------------------------------------------------------*/\r
+/**\r
+ * \defgroup uipopttypedef uIP type definitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * The 8-bit unsigned data type.\r
+ *\r
+ * This may have to be tweaked for your particular compiler. "unsigned\r
+ * char" works for most compilers.\r
+ */\r
+typedef unsigned char u8_t;\r
+\r
+/**\r
+ * The 16-bit unsigned data type.\r
+ *\r
+ * This may have to be tweaked for your particular compiler. "unsigned\r
+ * short" works for most compilers.\r
+ */\r
+typedef unsigned short u16_t;\r
+\r
+/**\r
+ * The statistics data type.\r
+ *\r
+ * This datatype determines how high the statistics counters are able\r
+ * to count.\r
+ */\r
+typedef unsigned short uip_stats_t;\r
+\r
+/** @} */\r
+\r
+/*------------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \defgroup uipoptstaticconf Static configuration options\r
+ * @{\r
+ *\r
+ * These configuration options can be used for setting the IP address\r
+ * settings statically, but only if UIP_FIXEDADDR is set to 1. The\r
+ * configuration options for a specific node includes IP address,\r
+ * netmask and default router as well as the Ethernet address. The\r
+ * netmask, default router and Ethernet address are appliciable only\r
+ * if uIP should be run over Ethernet.\r
+ *\r
+ * All of these should be changed to suit your project.\r
+*/\r
+\r
+/**\r
+ * Determines if uIP should use a fixed IP address or not.\r
+ *\r
+ * If uIP should use a fixed IP address, the settings are set in the\r
+ * uipopt.h file. If not, the macros uip_sethostaddr(),\r
+ * uip_setdraddr() and uip_setnetmask() should be used instead.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_FIXEDADDR 1\r
+\r
+/**\r
+ * Ping IP address asignment.\r
+ *\r
+ * uIP uses a "ping" packets for setting its own IP address if this\r
+ * option is set. If so, uIP will start with an empty IP address and\r
+ * the destination IP address of the first incoming "ping" (ICMP echo)\r
+ * packet will be used for setting the hosts IP address.\r
+ *\r
+ * \note This works only if UIP_FIXEDADDR is 0.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_PINGADDRCONF 0\r
+\r
+\r
+#define UIP_IPADDR0 172U /**< The first octet of the IP address of\r
+ this uIP node, if UIP_FIXEDADDR is\r
+ 1. \hideinitializer */\r
+#define UIP_IPADDR1 25U /**< The second octet of the IP address of\r
+ this uIP node, if UIP_FIXEDADDR is\r
+ 1. \hideinitializer */\r
+#define UIP_IPADDR2 218U /**< The third octet of the IP address of\r
+ this uIP node, if UIP_FIXEDADDR is\r
+ 1. \hideinitializer */\r
+#define UIP_IPADDR3 204U /**< The fourth octet of the IP address of\r
+ this uIP node, if UIP_FIXEDADDR is\r
+ 1. \hideinitializer */\r
+\r
+#define UIP_NETMASK0 255 /**< The first octet of the netmask of\r
+ this uIP node, if UIP_FIXEDADDR is\r
+ 1. \hideinitializer */\r
+#define UIP_NETMASK1 255 /**< The second octet of the netmask of\r
+ this uIP node, if UIP_FIXEDADDR is\r
+ 1. \hideinitializer */\r
+#define UIP_NETMASK2 0 /**< The third octet of the netmask of\r
+ this uIP node, if UIP_FIXEDADDR is\r
+ 1. \hideinitializer */\r
+#define UIP_NETMASK3 0 /**< The fourth octet of the netmask of\r
+ this uIP node, if UIP_FIXEDADDR is\r
+ 1. \hideinitializer */\r
+\r
+#define UIP_DRIPADDR0 172 /**< The first octet of the IP address of\r
+ the default router, if UIP_FIXEDADDR is\r
+ 1. \hideinitializer */\r
+#define UIP_DRIPADDR1 25 /**< The second octet of the IP address of\r
+ the default router, if UIP_FIXEDADDR is\r
+ 1. \hideinitializer */\r
+#define UIP_DRIPADDR2 218 /**< The third octet of the IP address of\r
+ the default router, if UIP_FIXEDADDR is\r
+ 1. \hideinitializer */\r
+#define UIP_DRIPADDR3 3 /**< The fourth octet of the IP address of\r
+ the default router, if UIP_FIXEDADDR is\r
+ 1. \hideinitializer */\r
+\r
+\r
+\r
+/**\r
+ * Specifies if the uIP ARP module should be compiled with a fixed\r
+ * Ethernet MAC address or not.\r
+ *\r
+ * If this configuration option is 0, the macro uip_setethaddr() can\r
+ * be used to specify the Ethernet address at run-time.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_FIXEDETHADDR 0\r
+\r
+#define UIP_ETHADDR0 0x00 /**< The first octet of the Ethernet\r
+ address if UIP_FIXEDETHADDR is\r
+ 1. \hideinitializer */\r
+#define UIP_ETHADDR1 0xbd /**< The second octet of the Ethernet\r
+ address if UIP_FIXEDETHADDR is\r
+ 1. \hideinitializer */\r
+#define UIP_ETHADDR2 0x3b /**< The third octet of the Ethernet\r
+ address if UIP_FIXEDETHADDR is\r
+ 1. \hideinitializer */\r
+#define UIP_ETHADDR3 0x33 /**< The fourth octet of the Ethernet\r
+ address if UIP_FIXEDETHADDR is\r
+ 1. \hideinitializer */\r
+#define UIP_ETHADDR4 0x06 /**< The fifth octet of the Ethernet\r
+ address if UIP_FIXEDETHADDR is\r
+ 1. \hideinitializer */\r
+#define UIP_ETHADDR5 0x65 /**< The sixth octet of the Ethernet\r
+ address if UIP_FIXEDETHADDR is\r
+ 1. \hideinitializer */\r
+\r
+/** @} */\r
+/*------------------------------------------------------------------------------*/\r
+/**\r
+ * \defgroup uipoptip IP configuration options\r
+ * @{\r
+ *\r
+ */\r
+/**\r
+ * The IP TTL (time to live) of IP packets sent by uIP.\r
+ *\r
+ * This should normally not be changed.\r
+ */\r
+#define UIP_TTL 255\r
+\r
+/**\r
+ * Turn on support for IP packet reassembly.\r
+ *\r
+ * uIP supports reassembly of fragmented IP packets. This features\r
+ * requires an additonal amount of RAM to hold the reassembly buffer\r
+ * and the reassembly code size is approximately 700 bytes. The\r
+ * reassembly buffer is of the same size as the uip_buf buffer\r
+ * (configured by UIP_BUFSIZE).\r
+ *\r
+ * \note IP packet reassembly is not heavily tested.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_REASSEMBLY 0\r
+\r
+/**\r
+ * The maximum time an IP fragment should wait in the reassembly\r
+ * buffer before it is dropped.\r
+ *\r
+ */\r
+#define UIP_REASS_MAXAGE 40\r
+\r
+/** @} */\r
+\r
+/*------------------------------------------------------------------------------*/\r
+/**\r
+ * \defgroup uipoptudp UDP configuration options\r
+ * @{\r
+ *\r
+ * \note The UDP support in uIP is still not entirely complete; there\r
+ * is no support for sending or receiving broadcast or multicast\r
+ * packets, but it works well enough to support a number of vital\r
+ * applications such as DNS queries, though\r
+ */\r
+\r
+/**\r
+ * Toggles wether UDP support should be compiled in or not.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_UDP 0\r
+\r
+/**\r
+ * Toggles if UDP checksums should be used or not.\r
+ *\r
+ * \note Support for UDP checksums is currently not included in uIP,\r
+ * so this option has no function.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_UDP_CHECKSUMS 0\r
+\r
+/**\r
+ * The maximum amount of concurrent UDP connections.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_UDP_CONNS 2\r
+\r
+/**\r
+ * The name of the function that should be called when UDP datagrams arrive.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_UDP_APPCALL udp_appcall\r
+\r
+/** @} */\r
+/*------------------------------------------------------------------------------*/\r
+/**\r
+ * \defgroup uipopttcp TCP configuration options\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * Determines if support for opening connections from uIP should be\r
+ * compiled in.\r
+ *\r
+ * If the applications that are running on top of uIP for this project\r
+ * do not need to open outgoing TCP connections, this configration\r
+ * option can be turned off to reduce the code size of uIP.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_ACTIVE_OPEN 0\r
+\r
+/**\r
+ * The maximum number of simultaneously open TCP connections.\r
+ *\r
+ * Since the TCP connections are statically allocated, turning this\r
+ * configuration knob down results in less RAM used. Each TCP\r
+ * connection requires approximatly 30 bytes of memory.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_CONNS 25\r
+\r
+/**\r
+ * The maximum number of simultaneously listening TCP ports.\r
+ *\r
+ * Each listening TCP port requires 2 bytes of memory.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_LISTENPORTS 10\r
+\r
+/**\r
+ * The size of the advertised receiver's window.\r
+ *\r
+ * Should be set low (i.e., to the size of the uip_buf buffer) is the\r
+ * application is slow to process incoming data, or high (32768 bytes)\r
+ * if the application processes data quickly.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_RECEIVE_WINDOW 32768\r
+\r
+/**\r
+ * Determines if support for TCP urgent data notification should be\r
+ * compiled in.\r
+ *\r
+ * Urgent data (out-of-band data) is a rarely used TCP feature that\r
+ * very seldom would be required.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_URGDATA 1\r
+\r
+/**\r
+ * The initial retransmission timeout counted in timer pulses.\r
+ *\r
+ * This should not be changed.\r
+ */\r
+#define UIP_RTO 3\r
+\r
+/**\r
+ * The maximum number of times a segment should be retransmitted\r
+ * before the connection should be aborted.\r
+ *\r
+ * This should not be changed.\r
+ */\r
+#define UIP_MAXRTX 8\r
+\r
+/**\r
+ * The maximum number of times a SYN segment should be retransmitted\r
+ * before a connection request should be deemed to have been\r
+ * unsuccessful.\r
+ *\r
+ * This should not need to be changed.\r
+ */\r
+#define UIP_MAXSYNRTX 3\r
+\r
+/**\r
+ * The TCP maximum segment size.\r
+ *\r
+ * This is should not be to set to more than UIP_BUFSIZE - UIP_LLH_LEN - 40.\r
+ */\r
+#define UIP_TCP_MSS (UIP_BUFSIZE - UIP_LLH_LEN - 40)\r
+\r
+/**\r
+ * How long a connection should stay in the TIME_WAIT state.\r
+ *\r
+ * This configiration option has no real implication, and it should be\r
+ * left untouched.\r
+ */\r
+#define UIP_TIME_WAIT_TIMEOUT 120\r
+\r
+\r
+/** @} */\r
+/*------------------------------------------------------------------------------*/\r
+/**\r
+ * \defgroup uipoptarp ARP configuration options\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * The size of the ARP table.\r
+ *\r
+ * This option should be set to a larger value if this uIP node will\r
+ * have many connections from the local network.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_ARPTAB_SIZE 8\r
+\r
+/**\r
+ * The maxium age of ARP table entries measured in 10ths of seconds.\r
+ *\r
+ * An UIP_ARP_MAXAGE of 120 corresponds to 20 minutes (BSD\r
+ * default).\r
+ */\r
+#define UIP_ARP_MAXAGE 120\r
+\r
+/** @} */\r
+\r
+/*------------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \defgroup uipoptgeneral General configuration options\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * The size of the uIP packet buffer.\r
+ *\r
+ * The uIP packet buffer should not be smaller than 60 bytes, and does\r
+ * not need to be larger than 1500 bytes. Lower size results in lower\r
+ * TCP throughput, larger size results in higher TCP throughput.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_BUFSIZE 2048\r
+\r
+\r
+/**\r
+ * Determines if statistics support should be compiled in.\r
+ *\r
+ * The statistics is useful for debugging and to show the user.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_STATISTICS 1\r
+\r
+/**\r
+ * Determines if logging of certain events should be compiled in.\r
+ *\r
+ * This is useful mostly for debugging. The function uip_log()\r
+ * must be implemented to suit the architecture of the project, if\r
+ * logging is turned on.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_LOGGING 0\r
+\r
+/**\r
+ * Print out a uIP log message.\r
+ *\r
+ * This function must be implemented by the module that uses uIP, and\r
+ * is called by uIP whenever a log message is generated.\r
+ */\r
+void uip_log(char *msg);\r
+\r
+/**\r
+ * The link level header length.\r
+ *\r
+ * This is the offset into the uip_buf where the IP header can be\r
+ * found. For Ethernet, this should be set to 14. For SLIP, this\r
+ * should be set to 0.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_LLH_LEN 14\r
+\r
+\r
+/** @} */\r
+/*------------------------------------------------------------------------------*/\r
+/**\r
+ * \defgroup uipoptcpu CPU architecture configuration\r
+ * @{\r
+ *\r
+ * The CPU architecture configuration is where the endianess of the\r
+ * CPU on which uIP is to be run is specified. Most CPUs today are\r
+ * little endian, and the most notable exception are the Motorolas\r
+ * which are big endian. The BYTE_ORDER macro should be changed to\r
+ * reflect the CPU architecture on which uIP is to be run.\r
+ */\r
+#ifndef LITTLE_ENDIAN\r
+#define LITTLE_ENDIAN 3412\r
+#endif /* LITTLE_ENDIAN */\r
+#ifndef BIG_ENDIAN\r
+#define BIG_ENDIAN 1234\r
+#endif /* BIGE_ENDIAN */\r
+\r
+/**\r
+ * The byte order of the CPU architecture on which uIP is to be run.\r
+ *\r
+ * This option can be either BIG_ENDIAN (Motorola byte order) or\r
+ * LITTLE_ENDIAN (Intel byte order).\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#ifndef BYTE_ORDER\r
+#define BYTE_ORDER LITTLE_ENDIAN\r
+#endif /* BYTE_ORDER */\r
+\r
+/** @} */\r
+/*------------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \defgroup uipoptapp Appication specific configurations\r
+ * @{\r
+ *\r
+ * An uIP application is implemented using a single application\r
+ * function that is called by uIP whenever a TCP/IP event occurs. The\r
+ * name of this function must be registered with uIP at compile time\r
+ * using the UIP_APPCALL definition.\r
+ *\r
+ * uIP applications can store the application state within the\r
+ * uip_conn structure by specifying the size of the application\r
+ * structure with the UIP_APPSTATE_SIZE macro.\r
+ *\r
+ * The file containing the definitions must be included in the\r
+ * uipopt.h file.\r
+ *\r
+ * The following example illustrates how this can look.\r
+ \code\r
+\r
+void httpd_appcall(void);\r
+#define UIP_APPCALL httpd_appcall\r
+\r
+struct httpd_state {\r
+ u8_t state;\r
+ u16_t count;\r
+ char *dataptr;\r
+ char *script;\r
+};\r
+#define UIP_APPSTATE_SIZE (sizeof(struct httpd_state))\r
+ \endcode\r
+ */\r
+\r
+/**\r
+ * \var #define UIP_APPCALL\r
+ *\r
+ * The name of the application function that uIP should call in\r
+ * response to TCP/IP events.\r
+ *\r
+ */\r
+\r
+/**\r
+ * \var #define UIP_APPSTATE_SIZE\r
+ *\r
+ * The size of the application state that is to be stored in the\r
+ * uip_conn structure.\r
+ */\r
+/** @} */\r
+\r
+/* Include the header file for the application program that should be\r
+ used. If you don't use the example web server, you should change\r
+ this. */\r
+#include "httpd.h"\r
+\r
+\r
+#endif /* __UIPOPT_H__ */\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+#include <lpc210x.h>\r
+#define vPortYieldProcessor swi_handler\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. \r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 58982400 ) /* =14.7456MHz xtal multiplied by 4 using the PLL. */\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 128 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 10 * 1024 ) )\r
+#define configMAX_TASK_NAME_LEN ( 16 )\r
+#define configUSE_TRACE_FACILITY 1\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 1\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+<!DOCTYPE Linker_Placement_File>\r
+<Root name="Flash Section Placement" >\r
+ <MemorySegment name="External SRAM;SRAM;SDRAM;DRAM" >\r
+ <ProgramSection alignment="4" load="No" name=".data_run" />\r
+ <ProgramSection alignment="4" load="No" inputsections="*(.bss .bss.* .gnu.linkonce.b.*) *(COMMON)" name=".bss" />\r
+ <ProgramSection alignment="4" size="0x0" load="No" name=".heap" />\r
+ <ProgramSection alignment="4" size="0x0" load="No" name=".stack" />\r
+ <ProgramSection alignment="4" size="0x200" load="No" name=".stack_irq" />\r
+ <ProgramSection alignment="4" size="0x0" load="No" name=".stack_fiq" />\r
+ <ProgramSection alignment="4" size="0x200" load="No" name=".stack_svc" />\r
+ <ProgramSection alignment="4" size="0x0" load="No" name=".stack_abt" />\r
+ <ProgramSection alignment="4" size="0x0" load="No" name=".stack_und" />\r
+ </MemorySegment>\r
+ <MemorySegment name="Internal SRAM;SRAM;SDRAM;DRAM" >\r
+ <ProgramSection size="0x3C" load="No" name=".vectors_ram" />\r
+ <ProgramSection alignment="4" load="No" name=".fast_run" />\r
+ </MemorySegment>\r
+ <MemorySegment name="FLASH" >\r
+ <ProgramSection load="Yes" inputsections="*(.vectors .vectors.*)" name=".vectors" />\r
+ <ProgramSection alignment="4" load="Yes" inputsections="*(.init .init.*)" name=".init" />\r
+ <ProgramSection alignment="4" load="No" name=".text_load" />\r
+ <ProgramSection alignment="4" load="Yes" inputsections="*(.text .text.* .glue_7t .glue_7 .gnu.linkonce.t.*)" name=".text" />\r
+ <ProgramSection alignment="4" load="Yes" inputsections="KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors))" name=".dtors" />\r
+ <ProgramSection alignment="4" load="Yes" inputsections="KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors))" name=".ctors" />\r
+ <ProgramSection alignment="4" load="Yes" inputsections="*(.rodata .rodata.* .gnu.linkonce.r.*)" name=".rodata" />\r
+ <ProgramSection alignment="4" load="Yes" runin=".fast_run" inputsections="*(.fast .fast.*)" name=".fast" />\r
+ <ProgramSection alignment="4" load="Yes" runin=".data_run" inputsections="*(.data .data.* .gnu.linkonce.d.*)" name=".data" />\r
+ </MemorySegment>\r
+</Root>\r
--- /dev/null
+#ifndef lpc210x_h\r
+#define lpc210x_h\r
+/*******************************************************************************\r
+lpc210x.h - Register defs for Philips LPC210X: LPC2104, LPC2105 and LPC2106\r
+\r
+ \r
+THE SOFTWARE IS DELIVERED "AS IS" WITHOUT WARRANTY OR CONDITION OF ANY KIND, \r
+EITHER EXPRESS, IMPLIED OR STATUTORY. THIS INCLUDES WITHOUT LIMITATION ANY \r
+WARRANTY OR CONDITION WITH RESPECT TO MERCHANTABILITY OR FITNESS FOR ANY \r
+PARTICULAR PURPOSE, OR AGAINST THE INFRINGEMENTS OF INTELLECTUAL PROPERTY RIGHTS \r
+OF OTHERS.\r
+ \r
+This file may be freely used for commercial and non-commercial applications, \r
+including being redistributed with any tools.\r
+\r
+If you find a problem with the file, please report it so that it can be fixed.\r
+\r
+Created by Sten Larsson (sten_larsson at yahoo com)\r
+\r
+Edited by Richard Barry.\r
+*******************************************************************************/\r
+\r
+#define REG8 (volatile unsigned char*)\r
+#define REG16 (volatile unsigned short*)\r
+#define REG32 (volatile unsigned int*)\r
+\r
+\r
+/*##############################################################################\r
+## MISC\r
+##############################################################################*/\r
+\r
+ /* Constants for data to put in IRQ/FIQ Exception Vectors */\r
+#define VECTDATA_IRQ 0xE51FFFF0 /* LDR PC,[PC,#-0xFF0] */\r
+#define VECTDATA_FIQ /* __TODO */\r
+\r
+\r
+/*##############################################################################\r
+## VECTORED INTERRUPT CONTROLLER\r
+##############################################################################*/\r
+\r
+#define VICIRQStatus (*(REG32 (0xFFFFF000)))\r
+#define VICFIQStatus (*(REG32 (0xFFFFF004)))\r
+#define VICRawIntr (*(REG32 (0xFFFFF008)))\r
+#define VICIntSelect (*(REG32 (0xFFFFF00C)))\r
+#define VICIntEnable (*(REG32 (0xFFFFF010)))\r
+#define VICIntEnClear (*(REG32 (0xFFFFF014)))\r
+#define VICSoftInt (*(REG32 (0xFFFFF018)))\r
+#define VICSoftIntClear (*(REG32 (0xFFFFF01C)))\r
+#define VICProtection (*(REG32 (0xFFFFF020)))\r
+#define VICVectAddr (*(REG32 (0xFFFFF030)))\r
+#define VICDefVectAddr (*(REG32 (0xFFFFF034)))\r
+\r
+#define VICVectAddr0 (*(REG32 (0xFFFFF100)))\r
+#define VICVectAddr1 (*(REG32 (0xFFFFF104)))\r
+#define VICVectAddr2 (*(REG32 (0xFFFFF108)))\r
+#define VICVectAddr3 (*(REG32 (0xFFFFF10C)))\r
+#define VICVectAddr4 (*(REG32 (0xFFFFF110)))\r
+#define VICVectAddr5 (*(REG32 (0xFFFFF114)))\r
+#define VICVectAddr6 (*(REG32 (0xFFFFF118)))\r
+#define VICVectAddr7 (*(REG32 (0xFFFFF11C)))\r
+#define VICVectAddr8 (*(REG32 (0xFFFFF120)))\r
+#define VICVectAddr9 (*(REG32 (0xFFFFF124)))\r
+#define VICVectAddr10 (*(REG32 (0xFFFFF128)))\r
+#define VICVectAddr11 (*(REG32 (0xFFFFF12C)))\r
+#define VICVectAddr12 (*(REG32 (0xFFFFF130)))\r
+#define VICVectAddr13 (*(REG32 (0xFFFFF134)))\r
+#define VICVectAddr14 (*(REG32 (0xFFFFF138)))\r
+#define VICVectAddr15 (*(REG32 (0xFFFFF13C)))\r
+\r
+#define VICVectCntl0 (*(REG32 (0xFFFFF200)))\r
+#define VICVectCntl1 (*(REG32 (0xFFFFF204)))\r
+#define VICVectCntl2 (*(REG32 (0xFFFFF208)))\r
+#define VICVectCntl3 (*(REG32 (0xFFFFF20C)))\r
+#define VICVectCntl4 (*(REG32 (0xFFFFF210)))\r
+#define VICVectCntl5 (*(REG32 (0xFFFFF214)))\r
+#define VICVectCntl6 (*(REG32 (0xFFFFF218)))\r
+#define VICVectCntl7 (*(REG32 (0xFFFFF21C)))\r
+#define VICVectCntl8 (*(REG32 (0xFFFFF220)))\r
+#define VICVectCntl9 (*(REG32 (0xFFFFF224)))\r
+#define VICVectCntl10 (*(REG32 (0xFFFFF228)))\r
+#define VICVectCntl11 (*(REG32 (0xFFFFF22C)))\r
+#define VICVectCntl12 (*(REG32 (0xFFFFF230)))\r
+#define VICVectCntl13 (*(REG32 (0xFFFFF234)))\r
+#define VICVectCntl14 (*(REG32 (0xFFFFF238)))\r
+#define VICVectCntl15 (*(REG32 (0xFFFFF23C)))\r
+\r
+#define VICITCR (*(REG32 (0xFFFFF300)))\r
+#define VICITIP1 (*(REG32 (0xFFFFF304)))\r
+#define VICITIP2 (*(REG32 (0xFFFFF308)))\r
+#define VICITOP1 (*(REG32 (0xFFFFF30C)))\r
+#define VICITOP2 (*(REG32 (0xFFFFF310)))\r
+#define VICPeriphID0 (*(REG32 (0xFFFFFFE0)))\r
+#define VICPeriphID1 (*(REG32 (0xFFFFFFE4)))\r
+#define VICPeriphID2 (*(REG32 (0xFFFFFFE8)))\r
+#define VICPeriphID3 (*(REG32 (0xFFFFFFEC)))\r
+\r
+#define VICIntEnClr VICIntEnClear\r
+#define VICSoftIntClr VICSoftIntClear\r
+\r
+\r
+/*##############################################################################\r
+## PCB - Pin Connect Block\r
+##############################################################################*/\r
+\r
+#define PCB_PINSEL0 (*(REG32 (0xE002C000)))\r
+#define PCB_PINSEL1 (*(REG32 (0xE002C004)))\r
+\r
+\r
+/*##############################################################################\r
+## GPIO - General Purpose I/O\r
+##############################################################################*/\r
+\r
+#define GPIO_IOPIN (*(REG32 (0xE0028000))) /* ALTERNATE NAME GPIO = GPIO0 */\r
+#define GPIO_IOSET (*(REG32 (0xE0028004)))\r
+#define GPIO_IODIR (*(REG32 (0xE0028008)))\r
+#define GPIO_IOCLR (*(REG32 (0xE002800C)))\r
+\r
+#define GPIO0_IOPIN (*(REG32 (0xE0028000))) /* ALTERNATE NAME GPIO = GPIO0 */\r
+#define GPIO0_IOSET (*(REG32 (0xE0028004)))\r
+#define GPIO0_IODIR (*(REG32 (0xE0028008)))\r
+#define GPIO0_IOCLR (*(REG32 (0xE002800C)))\r
+\r
+\r
+/*##############################################################################\r
+## UART0 / UART1\r
+##############################################################################*/\r
+\r
+/* ---- UART 0 --------------------------------------------- */\r
+#define UART0_RBR (*(REG32 (0xE000C000)))\r
+#define UART0_THR (*(REG32 (0xE000C000)))\r
+#define UART0_IER (*(REG32 (0xE000C004)))\r
+#define UART0_IIR (*(REG32 (0xE000C008)))\r
+#define UART0_FCR (*(REG32 (0xE000C008)))\r
+#define UART0_LCR (*(REG32 (0xE000C00C)))\r
+#define UART0_LSR (*(REG32 (0xE000C014)))\r
+#define UART0_SCR (*(REG32 (0xE000C01C)))\r
+#define UART0_DLL (*(REG32 (0xE000C000)))\r
+#define UART0_DLM (*(REG32 (0xE000C004)))\r
+\r
+/* ---- UART 1 --------------------------------------------- */\r
+#define UART1_RBR (*(REG32 (0xE0010000)))\r
+#define UART1_THR (*(REG32 (0xE0010000)))\r
+#define UART1_IER (*(REG32 (0xE0010004)))\r
+#define UART1_IIR (*(REG32 (0xE0010008)))\r
+#define UART1_FCR (*(REG32 (0xE0010008)))\r
+#define UART1_LCR (*(REG32 (0xE001000C)))\r
+#define UART1_LSR (*(REG32 (0xE0010014)))\r
+#define UART1_SCR (*(REG32 (0xE001001C)))\r
+#define UART1_DLL (*(REG32 (0xE0010000)))\r
+#define UART1_DLM (*(REG32 (0xE0010004)))\r
+#define UART1_MCR (*(REG32 (0xE0010010)))\r
+#define UART1_MSR (*(REG32 (0xE0010018)))\r
+\r
+\r
+/*##############################################################################\r
+## I2C\r
+##############################################################################*/\r
+\r
+#define I2C_I2CONSET (*(REG32 (0xE001C000)))\r
+#define I2C_I2STAT (*(REG32 (0xE001C004)))\r
+#define I2C_I2DAT (*(REG32 (0xE001C008)))\r
+#define I2C_I2ADR (*(REG32 (0xE001C00C)))\r
+#define I2C_I2SCLH (*(REG32 (0xE001C010)))\r
+#define I2C_I2SCLL (*(REG32 (0xE001C014)))\r
+#define I2C_I2CONCLR (*(REG32 (0xE001C018)))\r
+\r
+\r
+/*##############################################################################\r
+## SPI - Serial Peripheral Interface\r
+##############################################################################*/\r
+\r
+#define SPI_SPCR (*(REG32 (0xE0020000)))\r
+#define SPI_SPSR (*(REG32 (0xE0020004)))\r
+#define SPI_SPDR (*(REG32 (0xE0020008)))\r
+#define SPI_SPCCR (*(REG32 (0xE002000C)))\r
+#define SPI_SPTCR (*(REG32 (0xE0020010)))\r
+#define SPI_SPTSR (*(REG32 (0xE0020014)))\r
+#define SPI_SPTOR (*(REG32 (0xE0020018)))\r
+#define SPI_SPINT (*(REG32 (0xE002001C)))\r
+\r
+\r
+/*##############################################################################\r
+## Timer 0 and Timer 1\r
+##############################################################################*/\r
+\r
+/* ---- Timer 0 -------------------------------------------- */\r
+#define T0_IR (*(REG32 (0xE0004000)))\r
+#define T0_TCR (*(REG32 (0xE0004004)))\r
+#define T0_TC (*(REG32 (0xE0004008)))\r
+#define T0_PR (*(REG32 (0xE000400C)))\r
+#define T0_PC (*(REG32 (0xE0004010)))\r
+#define T0_MCR (*(REG32 (0xE0004014)))\r
+#define T0_MR0 (*(REG32 (0xE0004018)))\r
+#define T0_MR1 (*(REG32 (0xE000401C)))\r
+#define T0_MR2 (*(REG32 (0xE0004020)))\r
+#define T0_MR3 (*(REG32 (0xE0004024)))\r
+#define T0_CCR (*(REG32 (0xE0004028)))\r
+#define T0_CR0 (*(REG32 (0xE000402C)))\r
+#define T0_CR1 (*(REG32 (0xE0004030)))\r
+#define T0_CR2 (*(REG32 (0xE0004034)))\r
+#define T0_CR3 (*(REG32 (0xE0004038)))\r
+#define T0_EMR (*(REG32 (0xE000403C)))\r
+\r
+/* ---- Timer 1 -------------------------------------------- */\r
+#define T1_IR (*(REG32 (0xE0008000)))\r
+#define T1_TCR (*(REG32 (0xE0008004)))\r
+#define T1_TC (*(REG32 (0xE0008008)))\r
+#define T1_PR (*(REG32 (0xE000800C)))\r
+#define T1_PC (*(REG32 (0xE0008010)))\r
+#define T1_MCR (*(REG32 (0xE0008014)))\r
+#define T1_MR0 (*(REG32 (0xE0008018)))\r
+#define T1_MR1 (*(REG32 (0xE000801C)))\r
+#define T1_MR2 (*(REG32 (0xE0008020)))\r
+#define T1_MR3 (*(REG32 (0xE0008024)))\r
+#define T1_CCR (*(REG32 (0xE0008028)))\r
+#define T1_CR0 (*(REG32 (0xE000802C)))\r
+#define T1_CR1 (*(REG32 (0xE0008030)))\r
+#define T1_CR2 (*(REG32 (0xE0008034)))\r
+#define T1_CR3 (*(REG32 (0xE0008038)))\r
+#define T1_EMR (*(REG32 (0xE000803C)))\r
+\r
+\r
+/*##############################################################################\r
+## PWM\r
+##############################################################################*/\r
+\r
+#define PWM_IR (*(REG32 (0xE0014000)))\r
+#define PWM_TCR (*(REG32 (0xE0014004)))\r
+#define PWM_TC (*(REG32 (0xE0014008)))\r
+#define PWM_PR (*(REG32 (0xE001400C)))\r
+#define PWM_PC (*(REG32 (0xE0014010)))\r
+#define PWM_MCR (*(REG32 (0xE0014014)))\r
+#define PWM_MR0 (*(REG32 (0xE0014018)))\r
+#define PWM_MR1 (*(REG32 (0xE001401C)))\r
+#define PWM_MR2 (*(REG32 (0xE0014020)))\r
+#define PWM_MR3 (*(REG32 (0xE0014024)))\r
+#define PWM_MR4 (*(REG32 (0xE0014040)))\r
+#define PWM_MR5 (*(REG32 (0xE0014044)))\r
+#define PWM_MR6 (*(REG32 (0xE0014048)))\r
+#define PWM_EMR (*(REG32 (0xE001403C)))\r
+#define PWM_PCR (*(REG32 (0xE001404C)))\r
+#define PWM_LER (*(REG32 (0xE0014050)))\r
+#define PWM_CCR (*(REG32 (0xE0014028)))\r
+#define PWM_CR0 (*(REG32 (0xE001402C)))\r
+#define PWM_CR1 (*(REG32 (0xE0014030)))\r
+#define PWM_CR2 (*(REG32 (0xE0014034)))\r
+#define PWM_CR3 (*(REG32 (0xE0014038)))\r
+\r
+/*##############################################################################\r
+## RTC\r
+##############################################################################*/\r
+\r
+/* ---- RTC: Miscellaneous Register Group ------------------ */\r
+#define RTC_ILR (*(REG32 (0xE0024000)))\r
+#define RTC_CTC (*(REG32 (0xE0024004)))\r
+#define RTC_CCR (*(REG32 (0xE0024008))) \r
+#define RTC_CIIR (*(REG32 (0xE002400C)))\r
+#define RTC_AMR (*(REG32 (0xE0024010)))\r
+#define RTC_CTIME0 (*(REG32 (0xE0024014)))\r
+#define RTC_CTIME1 (*(REG32 (0xE0024018)))\r
+#define RTC_CTIME2 (*(REG32 (0xE002401C)))\r
+\r
+/* ---- RTC: Timer Control Group --------------------------- */\r
+#define RTC_SEC (*(REG32 (0xE0024020)))\r
+#define RTC_MIN (*(REG32 (0xE0024024)))\r
+#define RTC_HOUR (*(REG32 (0xE0024028)))\r
+#define RTC_DOM (*(REG32 (0xE002402C)))\r
+#define RTC_DOW (*(REG32 (0xE0024030)))\r
+#define RTC_DOY (*(REG32 (0xE0024034)))\r
+#define RTC_MONTH (*(REG32 (0xE0024038)))\r
+#define RTC_YEAR (*(REG32 (0xE002403C)))\r
+\r
+/* ---- RTC: Alarm Control Group --------------------------- */\r
+#define RTC_ALSEC (*(REG32 (0xE0024060)))\r
+#define RTC_ALMIN (*(REG32 (0xE0024064)))\r
+#define RTC_ALHOUR (*(REG32 (0xE0024068)))\r
+#define RTC_ALDOM (*(REG32 (0xE002406C)))\r
+#define RTC_ALDOW (*(REG32 (0xE0024070)))\r
+#define RTC_ALDOY (*(REG32 (0xE0024074)))\r
+#define RTC_ALMON (*(REG32 (0xE0024078)))\r
+#define RTC_ALYEAR (*(REG32 (0xE002407C)))\r
+\r
+/* ---- RTC: Reference Clock Divider Group ----------------- */\r
+#define RTC_PREINT (*(REG32 (0xE0024080)))\r
+#define RTC_PREFRAC (*(REG32 (0xE0024084)))\r
+\r
+\r
+/*##############################################################################\r
+## WD - Watchdog\r
+##############################################################################*/\r
+\r
+#define WD_WDMOD (*(REG32 (0xE0000000)))\r
+#define WD_WDTC (*(REG32 (0xE0000004)))\r
+#define WD_WDFEED (*(REG32 (0xE0000008)))\r
+#define WD_WDTV (*(REG32 (0xE000000C)))\r
+\r
+\r
+/*##############################################################################\r
+## System Control Block\r
+##############################################################################*/\r
+\r
+#define SCB_EXTINT (*(REG32 (0xE01FC140)))\r
+#define SCB_EXTWAKE (*(REG32 (0xE01FC144)))\r
+#define SCB_MEMMAP (*(REG32 (0xE01FC040)))\r
+#define SCB_PLLCON (*(REG32 (0xE01FC080)))\r
+#define SCB_PLLCFG (*(REG32 (0xE01FC084)))\r
+#define SCB_PLLSTAT (*(REG32 (0xE01FC088)))\r
+#define SCB_PLLFEED (*(REG32 (0xE01FC08C)))\r
+#define SCB_PCON (*(REG32 (0xE01FC0C0)))\r
+#define SCB_PCONP (*(REG32 (0xE01FC0C4)))\r
+#define SCB_VPBDIV (*(REG32 (0xE01FC100)))\r
+\r
+/*##############################################################################\r
+## Memory Accelerator Module (MAM)\r
+##############################################################################*/\r
+\r
+#define MAM_TIM (*(REG32 (0xE01FC004)))\r
+#define MAM_CR (*(REG32 (0xE01FC000)))\r
+\r
+#endif /* lpc210x_h */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* \r
+ NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.\r
+ The processor MUST be in supervisor mode when vTaskStartScheduler is \r
+ called. The demo applications included in the FreeRTOS.org download switch\r
+ to supervisor mode prior to main being called. If you are not using one of\r
+ these demo application projects then ensure Supervisor mode is used.\r
+*/\r
+\r
+\r
+/*\r
+ * Creates all the application tasks, then starts the scheduler. \r
+ * \r
+ * A task is created called "uIP". This executes the uIP stack and small\r
+ * WEB server sample. All the other tasks are from the set of standard\r
+ * demo tasks. The WEB documentation provides more details of the standard\r
+ * demo application tasks.\r
+ *\r
+ * Main.c also creates a task called "Check". This only executes every three \r
+ * seconds but has the highest priority so is guaranteed to get processor time. \r
+ * Its main function is to check that all the other tasks are still operational.\r
+ * Each standard demo task maintains a unique count that is incremented each \r
+ * time the task successfully completes its function. Should any error occur \r
+ * within such a task the count is permanently halted. The check task inspects\r
+ * the count of each task to ensure it has changed since the last time the \r
+ * check task executed. If all the count variables have changed all the tasks \r
+ * are still executing error free, and the check task toggles the yellow LED. \r
+ * Should any task contain an error at any time the LED toggle rate will change \r
+ * from 3 seconds to 500ms.\r
+ *\r
+ */\r
+\r
+\r
+/* Standard includes. */\r
+#include <stdlib.h>\r
+#include <string.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo application includes. */\r
+#include "PollQ.h"\r
+#include "dynamic.h"\r
+#include "semtest.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Constants to setup the PLL. */\r
+#define mainPLL_MUL_4 ( ( unsigned portCHAR ) 0x0003 )\r
+#define mainPLL_DIV_1 ( ( unsigned portCHAR ) 0x0000 )\r
+#define mainPLL_ENABLE ( ( unsigned portCHAR ) 0x0001 )\r
+#define mainPLL_CONNECT ( ( unsigned portCHAR ) 0x0003 )\r
+#define mainPLL_FEED_BYTE1 ( ( unsigned portCHAR ) 0xaa )\r
+#define mainPLL_FEED_BYTE2 ( ( unsigned portCHAR ) 0x55 )\r
+#define mainPLL_LOCK ( ( unsigned portLONG ) 0x0400 )\r
+\r
+/* Constants to setup the MAM. */\r
+#define mainMAM_TIM_3 ( ( unsigned portCHAR ) 0x03 )\r
+#define mainMAM_MODE_FULL ( ( unsigned portCHAR ) 0x02 )\r
+\r
+/* Constants to setup the peripheral bus. */\r
+#define mainBUS_CLK_FULL ( ( unsigned portCHAR ) 0x01 )\r
+\r
+/* Priorities/stacks for the demo application tasks. */\r
+#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 )\r
+#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define mainUIP_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+#define mainUIP_TASK_STACK_SIZE ( 150 )\r
+\r
+/* The rate at which the on board LED will toggle when there is/is not an \r
+error. */\r
+#define mainNO_ERROR_FLASH_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS )\r
+#define mainERROR_FLASH_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS )\r
+#define mainON_BOARD_LED_BIT ( ( unsigned portLONG ) 0x80 )\r
+#define mainYELLOW_LED ( 1 << 11 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * This is the uIP task which is defined within the uip.c file. This has not\r
+ * been placed into a header file in order to minimise the changes to the uip\r
+ * code.\r
+ */\r
+extern void ( vuIP_TASK ) ( void *pvParameters );\r
+\r
+/*\r
+ * The Yellow LED is under the control of the Check task. All the other LED's\r
+ * are under the control of the uIP task. \r
+ */\r
+void prvToggleOnBoardLED( void );\r
+\r
+/*\r
+ * Checks that all the demo application tasks are still executing without error\r
+ * - as described at the top of the file.\r
+ */\r
+static portLONG prvCheckOtherTasksAreStillRunning( void );\r
+\r
+/*\r
+ * The task that executes at the highest priority and calls \r
+ * prvCheckOtherTasksAreStillRunning(). See the description at the top\r
+ * of the file.\r
+ */\r
+static void vErrorChecks( void *pvParameters );\r
+\r
+/*\r
+ * Configure the processor for use with the Olimex demo board. This includes\r
+ * setup for the I/O, system clock, and access timings.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Starts all the other tasks, then starts the scheduler. \r
+ */\r
+int main( void )\r
+{\r
+ /* Configure the processor. */\r
+ prvSetupHardware();\r
+\r
+ /* Start the task that handles the TCP/IP functionality. */\r
+ xTaskCreate( vuIP_TASK, "uIP", mainUIP_TASK_STACK_SIZE, NULL, mainUIP_PRIORITY, NULL );\r
+ \r
+ /* Start the demo/test application tasks. These are created in addition \r
+ to the TCP/IP task for demonstration and test purposes. */\r
+ vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
+ vStartDynamicPriorityTasks();\r
+ vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
+\r
+ /* Start the check task - which is defined in this file. */ \r
+ xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
+\r
+ /* Now all the tasks have been started - start the scheduler.\r
+\r
+ NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.\r
+ The processor MUST be in supervisor mode when vTaskStartScheduler is \r
+ called. The demo applications included in the FreeRTOS.org download switch\r
+ to supervisor mode prior to main being called. If you are not using one of\r
+ these demo application projects then ensure Supervisor mode is used here. */\r
+ vTaskStartScheduler();\r
+\r
+ /* Should never reach here! */\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vErrorChecks( void *pvParameters )\r
+{\r
+portTickType xDelayPeriod = mainNO_ERROR_FLASH_PERIOD;\r
+\r
+ /* Cycle for ever, delaying then checking all the other tasks are still\r
+ operating without error. If an error is detected then the delay period\r
+ is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so\r
+ the on board LED flash rate will increase. */\r
+ for( ;; )\r
+ {\r
+ /* Delay until it is time to execute again. */\r
+ vTaskDelay( xDelayPeriod );\r
+ \r
+ /* Check all the standard demo application tasks are executing without \r
+ error. */\r
+ if( prvCheckOtherTasksAreStillRunning() != pdPASS )\r
+ {\r
+ /* An error has been detected in one of the tasks - flash faster. */\r
+ xDelayPeriod = mainERROR_FLASH_PERIOD;\r
+ }\r
+\r
+ prvToggleOnBoardLED();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+ #ifdef RUN_FROM_RAM\r
+ /* Remap the interrupt vectors to RAM if we are are running from RAM. */\r
+ SCB_MEMMAP = 2;\r
+ #endif\r
+\r
+ /* Setup the PLL to multiply the XTAL input by 4. */\r
+ SCB_PLLCFG = ( mainPLL_MUL_4 | mainPLL_DIV_1 );\r
+\r
+ /* Activate the PLL by turning it on then feeding the correct sequence of\r
+ bytes. */\r
+ SCB_PLLCON = mainPLL_ENABLE;\r
+ SCB_PLLFEED = mainPLL_FEED_BYTE1;\r
+ SCB_PLLFEED = mainPLL_FEED_BYTE2;\r
+\r
+ /* Wait for the PLL to lock... */\r
+ while( !( SCB_PLLSTAT & mainPLL_LOCK ) );\r
+\r
+ /* ...before connecting it using the feed sequence again. */\r
+ SCB_PLLCON = mainPLL_CONNECT;\r
+ SCB_PLLFEED = mainPLL_FEED_BYTE1;\r
+ SCB_PLLFEED = mainPLL_FEED_BYTE2;\r
+\r
+ /* Setup and turn on the MAM. Three cycle access is used due to the fast\r
+ PLL used. It is possible faster overall performance could be obtained by\r
+ tuning the MAM and PLL settings. */\r
+ MAM_TIM = mainMAM_TIM_3;\r
+ MAM_CR = mainMAM_MODE_FULL;\r
+\r
+ /* Setup the peripheral bus to be the same as the PLL output. */\r
+ SCB_VPBDIV = mainBUS_CLK_FULL;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void prvToggleOnBoardLED( void )\r
+{\r
+unsigned portLONG ulState;\r
+\r
+ ulState = GPIO0_IOPIN;\r
+ if( ulState & mainYELLOW_LED )\r
+ {\r
+ GPIO_IOCLR = mainYELLOW_LED;\r
+ }\r
+ else\r
+ {\r
+ GPIO_IOSET = mainYELLOW_LED;\r
+ } \r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portLONG prvCheckOtherTasksAreStillRunning( void )\r
+{\r
+portLONG lReturn = ( portLONG ) pdPASS;\r
+\r
+ /* Check all the demo tasks (other than the flash tasks) to ensure\r
+ that they are all still running, and that none of them have detected\r
+ an error. */\r
+\r
+ if( xArePollingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ lReturn = ( portLONG ) pdFAIL;\r
+ }\r
+\r
+ if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )\r
+ {\r
+ lReturn = ( portLONG ) pdFAIL;\r
+ }\r
+\r
+ if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ lReturn = ( portLONG ) pdFAIL;\r
+ }\r
+\r
+ return lReturn;\r
+}\r
+\r
+\r
+\r
--- /dev/null
+<!DOCTYPE CrossStudio_Project_File>
+<solution version="1" Name="rtosdemo" >
+ <project Name="rtosdemo" >
+ <configuration Target="LPC2124" property_groups_file_path="$(StudioDir)/targets/Philips_LPC210X/propertyGroups.xml" linker_memory_map_file="$(StudioDir)/targets/Philips_LPC210X/Philips_LPC2124_MemoryMap.xml" c_preprocessor_definitions="OSCILLATOR_CLOCK_FREQUENCY=14745600;THUMB_INTERWORK;SUPERVISOR_START;VECTORED_IRQ_INTERRUPTS;GCC_ARM7" c_user_include_directories="../../Source/include;../../Demo/uIP_Demo_Rowley_ARM7;../../Demo/Common/Include;uip;." project_directory="" link_include_startup_code="No" project_type="Executable" c_additional_options="" Name="Common" />
+ <configuration target_reset_script="SRAMReset()" Name="RAM" />
+ <configuration arm_target_flash_loader_file_path="$(StudioDir)/targets/Philips_LPC210X/Release/Loader.exe" target_reset_script="FLASHReset()" Name="Flash" />
+ <folder Name="uIP Source" >
+ <configuration filter="c;cpp;cxx;cc;h;s;asm;inc" Name="Common" />
+ <file file_name="uip/cgi.c" Name="cgi.c" />
+ <file file_name="uip/cs8900a.c" Name="cs8900a.c" />
+ <file file_name="uip/fs.c" Name="fs.c" />
+ <file file_name="uip/httpd.c" Name="httpd.c" />
+ <file file_name="uip/uip.c" Name="uip.c" />
+ <file file_name="uip/uip_arch.c" Name="uip_arch.c" />
+ <file file_name="uip/uip_arp.c" Name="uip_arp.c" />
+ <file file_name="uip/uIP_Task.c" Name="uIP_Task.c" >
+ <configuration c_preprocessor_definitions="GCC_ARM7" Name="Common" />
+ </file>
+ </folder>
+ <folder Name="System Files" >
+ <configuration filter="" Name="Common" />
+ <file file_name="$(StudioDir)/source/crt0.s" Name="crt0.s" />
+ <file file_name="$(StudioDir)/targets/Philips_LPC210X/Philips_LPC210X_Startup.s" Name="Philips_LPC210X_Startup.s" />
+ <file file_name="$(StudioDir)/targets/Philips_LPC210X/Philips_LPC210X_Target.js" Name="Philips_LPC210X_Target.js" >
+ <configuration Name="Common" file_type="Reset Script" />
+ </file>
+ <file file_name="flash_placement.xml" Name="flash_placement.xml" />
+ </folder>
+ <folder Name="FreeRTOS Source" >
+ <configuration filter="" Name="Common" />
+ <file file_name="../../Source/tasks.c" Name="tasks.c" />
+ <file file_name="../../Source/queue.c" Name="queue.c" />
+ <file file_name="../../Source/list.c" Name="list.c" />
+ <file file_name="../../Source/portable/MemMang/heap_2.c" Name="heap_2.c" />
+ <file file_name="../../Source/portable/GCC/ARM7_LPC2000/port.c" Name="port.c" />
+ <file file_name="../../Source/portable/GCC/ARM7_LPC2000/portISR.c" Name="portISR.c" >
+ <configuration arm_instruction_set="ARM" Name="THUMB Flash Debug" />
+ </file>
+ </folder>
+ <folder Name="Demo App Source" >
+ <configuration filter="" Name="Common" />
+ <file file_name="../Common/Minimal/dynamic.c" Name="dynamic.c" />
+ <file file_name="../Common/Minimal/semtest.c" Name="semtest.c" />
+ <file file_name="main.c" Name="main.c" />
+ <file file_name="../Common/Minimal/PollQ.c" Name="PollQ.c" />
+ </folder>
+ <configuration c_preprocessor_definitions="" c_user_include_directories="" Name="Debug" />
+ </project>
+ <configuration inherited_configurations="THUMB;Flash;Debug" Name="THUMB Flash Debug" />
+ <configuration arm_library_instruction_set="THUMB" c_preprocessor_definitions="__THUMB" arm_instruction_set="THUMB" hidden="Yes" Name="THUMB" />
+ <configuration c_preprocessor_definitions="__FLASH_BUILD" hidden="Yes" Name="Flash" />
+ <configuration c_preprocessor_definitions="DEBUG" link_include_startup_code="No" gcc_optimization_level="None" build_debug_information="Yes" Name="Debug" />
+ <configuration c_preprocessor_definitions="NDEBUG" link_include_startup_code="No" gcc_optimization_level="Level 1" build_debug_information="No" Name="Release" />
+ <configuration c_preprocessor_definitions="" Name="Common" />
+</solution>
--- /dev/null
+<!DOCTYPE CrossStudio_for_ARM_Session_File>
+<session>
+ <Breakpoints/>
+ <ExecutionCountWindow/>
+ <Memory1>
+ <MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="128" dataSize="1" radix="16" addressSpace="" />
+ </Memory1>
+ <Memory2>
+ <MemoryWindow autoEvaluate="0" addressText="0xE01FC040" numColumns="8" sizeText="4" dataSize="4" radix="16" addressSpace="" />
+ </Memory2>
+ <Memory3>
+ <MemoryWindow autoEvaluate="0" addressText="0xE01FC080" numColumns="8" sizeText="12" dataSize="4" radix="16" addressSpace="" />
+ </Memory3>
+ <Memory4>
+ <MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" addressSpace="" />
+ </Memory4>
+ <Project>
+ <ProjectSessionItem path="rtosdemo" name="unnamed" />
+ <ProjectSessionItem path="rtosdemo;rtosdemo" name="unnamed" />
+ <ProjectSessionItem path="rtosdemo;rtosdemo;FreeRTOS Source" name="unnamed" />
+ <ProjectSessionItem path="rtosdemo;rtosdemo;uIP Source" name="unnamed" />
+ </Project>
+ <Register1>
+ <RegisterWindow unsignedDisplays="" asciiDisplays="" octalDisplays="" openGroups="CPU - Current Mode" visibleGroups="CPU - Current Mode" decimalDisplays="" binaryDisplays="" />
+ </Register1>
+ <Register2>
+ <RegisterWindow unsignedDisplays="" asciiDisplays="" octalDisplays="" openGroups="" visibleGroups="" decimalDisplays="" binaryDisplays="" />
+ </Register2>
+ <Register3>
+ <RegisterWindow unsignedDisplays="" asciiDisplays="" octalDisplays="" openGroups="" visibleGroups="" decimalDisplays="" binaryDisplays="" />
+ </Register3>
+ <Register4>
+ <RegisterWindow unsignedDisplays="" asciiDisplays="" octalDisplays="" openGroups="" visibleGroups="" decimalDisplays="" binaryDisplays="" />
+ </Register4>
+ <SourceNavigatorWindow/>
+ <TraceWindow>
+ <Trace wrap="Yes" type="1" enabled="Yes" />
+ </TraceWindow>
+ <Watch1>
+ <Watches active="1" />
+ </Watch1>
+ <Watch2>
+ <Watches active="0" />
+ </Watch2>
+ <Watch3>
+ <Watches active="0" />
+ </Watch3>
+ <Watch4>
+ <Watches active="0" />
+ </Watch4>
+ <Files>
+ <SessionOpenFile useTextEdit="1" useBinaryEdit="0" x="0" debugPath="E:\Dev\FreeRTOS\Source\portable\GCC\ARM7_LPC2000\port.c" y="0" useHTMLEdit="0" path="E:\Dev\FreeRTOS\Source\portable\GCC\ARM7_LPC2000\port.c" left="0" selected="0" name="unnamed" top="0" />
+ </Files>
+ <ARMCrossStudioWindow activeProject="rtosdemo" ignoreExceptions="IRQ;FIQ;SWI" autoConnectTarget="/ARM Simulators/Simulator, LPC22xx" debugSearchFileMap="" fileDialogInitialDirectory="D:\FreeRTOS\Demo\uIP_Demo_Rowley_ARM7\uip" fileDialogDefaultFilter="*" autoConnectCapabilities="4543" debugSearchPath="" buildConfiguration="Release" />
+</session>
--- /dev/null
+# Copyright (c) 2001, Adam Dunkels.\r
+# All rights reserved. \r
+#\r
+# Redistribution and use in source and binary forms, with or without \r
+# modification, are permitted provided that the following conditions \r
+# are met: \r
+# 1. Redistributions of source code must retain the above copyright \r
+# notice, this list of conditions and the following disclaimer. \r
+# 2. Redistributions in binary form must reproduce the above copyright \r
+# notice, this list of conditions and the following disclaimer in the \r
+# documentation and/or other materials provided with the distribution. \r
+# 3. All advertising materials mentioning features or use of this software\r
+# must display the following acknowledgement:\r
+# This product includes software developed by Adam Dunkels.\r
+# 4. The name of the author may not be used to endorse or promote\r
+# products derived from this software without specific prior\r
+# written permission. \r
+#\r
+# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+# OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+# GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \r
+#\r
+# This file is part of the uIP TCP/IP stack.\r
+#\r
+# $Id: Makefile,v 1.8.2.2 2003/10/04 22:54:17 adam Exp $\r
+#\r
+\r
+CC=gcc\r
+CFLAGS=-Wall -g -I../uip -I. -I../apps/httpd -I../apps/resolv -I../apps/webclient -I../apps/smtp -I../apps/telnet -fpack-struct\r
+\r
+%.o:\r
+ $(CC) $(CFLAGS) -c $(<:.o=.c)\r
+\r
+\r
+uip: uip.o uip_arch.o tapdev.o httpd.o main.o fs.o uip_arp.o cgi.o \r
+\r
+tapdev.o: tapdev.c uipopt.h\r
+main.o: main.c ../uip/uip.h uipopt.h ../apps/httpd/httpd.h \\r
+ tapdev.h\r
+uip_arch.o: uip_arch.c ../uip/uip_arch.h ../uip/uip.h uipopt.h \\r
+ ../apps/httpd/httpd.h \r
+uip.o: ../uip/uip.c ../uip/uip.h uipopt.h ../apps/httpd/httpd.h \r
+\r
+uip_arp.o: ../uip/uip_arp.c ../uip/uip_arp.h ../uip/uip.h uipopt.h \\r
+ ../apps/httpd/httpd.h\r
+ $(CC) -o uip_arp.o $(CFLAGS) -fpack-struct -c ../uip/uip_arp.c\r
+\r
+\r
+cgi.o: ../apps/httpd/cgi.c ../uip/uip.h uipopt.h ../apps/smtp/smtp.h \\r
+ ../apps/httpd/cgi.h ../apps/httpd/httpd.h ../apps/httpd/fs.h\r
+fs.o: ../apps/httpd/fs.c ../uip/uip.h uipopt.h ../apps/smtp/smtp.h \\r
+ ../apps/httpd/httpd.h ../apps/httpd/fs.h ../apps/httpd/fsdata.h \\r
+ ../apps/httpd/fsdata.c\r
+fsdata.o: ../apps/httpd/fsdata.c\r
+httpd.o: ../apps/httpd/httpd.c ../uip/uip.h uipopt.h \\r
+ ../apps/smtp/smtp.h ../apps/httpd/httpd.h ../apps/httpd/fs.h \\r
+ ../apps/httpd/fsdata.h ../apps/httpd/cgi.h\r
+\r
+clean:\r
+ rm -f *.o *~ *core uip\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/**\r
+ * \addtogroup httpd\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * HTTP server script language C functions file.\r
+ * \author Adam Dunkels <adam@dunkels.com>\r
+ *\r
+ * This file contains functions that are called by the web server\r
+ * scripts. The functions takes one argument, and the return value is\r
+ * interpreted as follows. A zero means that the function did not\r
+ * complete and should be invoked for the next packet as well. A\r
+ * non-zero value indicates that the function has completed and that\r
+ * the web server should move along to the next script line.\r
+ *\r
+ */\r
+\r
+/*\r
+ * Copyright (c) 2001, Adam Dunkels.\r
+ * All rights reserved. \r
+ *\r
+ * Redistribution and use in source and binary forms, with or without \r
+ * modification, are permitted provided that the following conditions \r
+ * are met: \r
+ * 1. Redistributions of source code must retain the above copyright \r
+ * notice, this list of conditions and the following disclaimer. \r
+ * 2. Redistributions in binary form must reproduce the above copyright \r
+ * notice, this list of conditions and the following disclaimer in the \r
+ * documentation and/or other materials provided with the distribution. \r
+ * 3. The name of the author may not be used to endorse or promote\r
+ * products derived from this software without specific prior\r
+ * written permission. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * $Id: cgi.c,v 1.23.2.4 2003/10/07 13:22:27 adam Exp $\r
+ *\r
+ */\r
+\r
+#include "uip.h"\r
+#include "cgi.h"\r
+#include "httpd.h"\r
+#include "fs.h"\r
+\r
+#include <stdio.h>\r
+#include <string.h>\r
+\r
+static u8_t print_stats(u8_t next);\r
+static u8_t file_stats(u8_t next);\r
+static u8_t tcp_stats(u8_t next);\r
+\r
+cgifunction cgitab[] = {\r
+ print_stats, /* CGI function "a" */\r
+ file_stats, /* CGI function "b" */\r
+ tcp_stats /* CGI function "c" */\r
+};\r
+\r
+static const char closed[] = /* "CLOSED",*/\r
+{0x43, 0x4c, 0x4f, 0x53, 0x45, 0x44, 0};\r
+static const char syn_rcvd[] = /* "SYN-RCVD",*/\r
+{0x53, 0x59, 0x4e, 0x2d, 0x52, 0x43, 0x56, \r
+ 0x44, 0};\r
+static const char syn_sent[] = /* "SYN-SENT",*/\r
+{0x53, 0x59, 0x4e, 0x2d, 0x53, 0x45, 0x4e, \r
+ 0x54, 0};\r
+static const char established[] = /* "ESTABLISHED",*/\r
+{0x45, 0x53, 0x54, 0x41, 0x42, 0x4c, 0x49, 0x53, 0x48, \r
+ 0x45, 0x44, 0};\r
+static const char fin_wait_1[] = /* "FIN-WAIT-1",*/\r
+{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49, \r
+ 0x54, 0x2d, 0x31, 0};\r
+static const char fin_wait_2[] = /* "FIN-WAIT-2",*/\r
+{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49, \r
+ 0x54, 0x2d, 0x32, 0};\r
+static const char closing[] = /* "CLOSING",*/\r
+{0x43, 0x4c, 0x4f, 0x53, 0x49, \r
+ 0x4e, 0x47, 0};\r
+static const char time_wait[] = /* "TIME-WAIT,"*/\r
+{0x54, 0x49, 0x4d, 0x45, 0x2d, 0x57, 0x41, \r
+ 0x49, 0x54, 0};\r
+static const char last_ack[] = /* "LAST-ACK"*/\r
+{0x4c, 0x41, 0x53, 0x54, 0x2d, 0x41, 0x43, \r
+ 0x4b, 0};\r
+\r
+static const char *states[] = {\r
+ closed,\r
+ syn_rcvd,\r
+ syn_sent,\r
+ established,\r
+ fin_wait_1,\r
+ fin_wait_2,\r
+ closing,\r
+ time_wait,\r
+ last_ack};\r
+ \r
+\r
+/*-----------------------------------------------------------------------------------*/\r
+/* print_stats:\r
+ *\r
+ * Prints out a part of the uIP statistics. The statistics data is\r
+ * written into the uip_appdata buffer. It overwrites any incoming\r
+ * packet.\r
+ */\r
+static u8_t\r
+print_stats(u8_t next)\r
+{\r
+#if UIP_STATISTICS\r
+ u16_t i, j;\r
+ u8_t *buf;\r
+ u16_t *databytes;\r
+ \r
+ if(next) {\r
+ /* If our last data has been acknowledged, we move on the next\r
+ chunk of statistics. */\r
+ hs->count = hs->count + 4;\r
+ if(hs->count >= sizeof(struct uip_stats)/sizeof(u16_t)) {\r
+ /* We have printed out all statistics, so we return 1 to\r
+ indicate that we are done. */\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ /* Write part of the statistics into the uip_appdata buffer. */\r
+ databytes = (u16_t *)&uip_stat + hs->count;\r
+ buf = (u8_t *)uip_appdata;\r
+\r
+ j = 4 + 1;\r
+ i = hs->count;\r
+ while (i < sizeof(struct uip_stats)/sizeof(u16_t) && --j > 0) {\r
+ sprintf((char *)buf, "%5u\r\n", *databytes);\r
+ ++databytes;\r
+ buf += 6;\r
+ ++i;\r
+ }\r
+\r
+ /* Send the data. */\r
+ uip_send(uip_appdata, buf - uip_appdata);\r
+ \r
+ return 0;\r
+#else\r
+ return 1;\r
+#endif /* UIP_STATISTICS */\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+static u8_t\r
+file_stats(u8_t next)\r
+{\r
+ /* We use sprintf() to print the number of file accesses to a\r
+ particular file (given as an argument to the function in the\r
+ script). We then use uip_send() to actually send the data. */\r
+ if(next) {\r
+ return 1;\r
+ }\r
+ uip_send(uip_appdata, sprintf((char *)uip_appdata, "%5u", fs_count(&hs->script[4]))); \r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+static u8_t\r
+tcp_stats(u8_t next)\r
+{\r
+ struct uip_conn *conn; \r
+\r
+ if(next) {\r
+ /* If the previously sent data has been acknowledged, we move\r
+ forward one connection. */\r
+ if(++hs->count == UIP_CONNS) {\r
+ /* If all connections has been printed out, we are done and\r
+ return 1. */\r
+ return 1;\r
+ }\r
+ }\r
+ \r
+ conn = &uip_conns[hs->count];\r
+ if((conn->tcpstateflags & TS_MASK) == CLOSED) {\r
+ uip_send(uip_appdata, sprintf((char *)uip_appdata,\r
+ "<tr align=\"center\"><td>-</td><td>-</td><td>%u</td><td>%u</td><td>%c %c</td></tr>\r\n",\r
+ conn->nrtx,\r
+ conn->timer,\r
+ (uip_outstanding(conn))? '*':' ',\r
+ (uip_stopped(conn))? '!':' '));\r
+ } else {\r
+ uip_send(uip_appdata, sprintf((char *)uip_appdata,\r
+ "<tr align=\"center\"><td>%u.%u.%u.%u:%u</td><td>%s</td><td>%u</td><td>%u</td><td>%c %c</td></tr>\r\n",\r
+ htons(conn->ripaddr[0]) >> 8,\r
+ htons(conn->ripaddr[0]) & 0xff,\r
+ htons(conn->ripaddr[1]) >> 8,\r
+ htons(conn->ripaddr[1]) & 0xff,\r
+ htons(conn->rport),\r
+ states[conn->tcpstateflags & TS_MASK],\r
+ conn->nrtx,\r
+ conn->timer,\r
+ (uip_outstanding(conn))? '*':' ',\r
+ (uip_stopped(conn))? '!':' '));\r
+ }\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
--- /dev/null
+/**\r
+ * \addtogroup httpd\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * HTTP script language header file.\r
+ * \author Adam Dunkels <adam@dunkels.com>\r
+ */\r
+\r
+/*\r
+ * Copyright (c) 2001, Adam Dunkels.\r
+ * All rights reserved. \r
+ *\r
+ * Redistribution and use in source and binary forms, with or without \r
+ * modification, are permitted provided that the following conditions \r
+ * are met: \r
+ * 1. Redistributions of source code must retain the above copyright \r
+ * notice, this list of conditions and the following disclaimer. \r
+ * 2. Redistributions in binary form must reproduce the above copyright \r
+ * notice, this list of conditions and the following disclaimer in the \r
+ * documentation and/or other materials provided with the distribution. \r
+ * 3. The name of the author may not be used to endorse or promote\r
+ * products derived from this software without specific prior\r
+ * written permission. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * $Id: cgi.h,v 1.3.2.4 2003/10/07 13:22:27 adam Exp $\r
+ *\r
+ */\r
+\r
+#ifndef __CGI_H__\r
+#define __CGI_H__\r
+\r
+typedef u8_t (* cgifunction)(u8_t next);\r
+\r
+/**\r
+ * A table containing pointers to C functions that can be called from\r
+ * a web server script.\r
+ */\r
+extern cgifunction cgitab[];\r
+\r
+#endif /* __CGI_H__ */\r
--- /dev/null
+// Rowley C Compiler, runtime support.\r
+//\r
+// Copyright (c) 2001, 2002, 2003 Rowley Associates Limited.\r
+//\r
+// This file may be distributed under the terms of the License Agreement\r
+// provided with this software.\r
+//\r
+// THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE\r
+// WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\r
+\r
+; Create sections\r
+ .data\r
+ .bss\r
+\r
+; Go to code section.\r
+ .code\r
+\r
+; Executed upon reset\r
+__reset proc\r
+\r
+; Turn off watchdog. You can enable it in main() if required.\r
+ mov.w #0x5a80, &0x120\r
+\r
+; Set up stack.\r
+ mov.w #RAM_Start_Address+RAM_Size, sp\r
+\r
+; Copy from initialised data section to data section.\r
+ mov.w #SFB(IDATA0), r15\r
+ mov.w #data_init_begin, r14\r
+ mov.w #data_init_end-data_init_begin, r13\r
+ call #_memcpy\r
+\r
+; Zero the bss. Ensure the stack is not allocated in the bss!\r
+ mov.w #SFB(UDATA0), r15\r
+ mov.w #0, r14\r
+ mov.w #SFE(UDATA0)-SFB(UDATA0), r13\r
+ call #_memset\r
+\r
+; Call user entry point void main(void).\r
+ call #_main\r
+\r
+; If main() returns, kick off again.\r
+ jmp __reset\r
+ endproc\r
+\r
+; Heap data structures; removed by the linker if the heap isn't used.\r
+ .break \r
+ .data\r
+ align WORD\r
+___heap_start__::\r
+ DW 0\r
+ DW heap_size\r
+ DS heap_size-4 \r
+\r
+; Reset vector\r
+ .vectors\r
+ .keep\r
+ org 0x1e\r
+ dw __reset\r
+\r
+; Initialise the IDATA0 section by duplicating the contents into the\r
+; CONST section and copying them on startup.\r
+ .const\r
+data_init_begin:\r
+ .init "IDATA0"\r
+data_init_end:\r
--- /dev/null
+// cs8900a.c: device driver for the CS8900a chip in 8-bit mode.\r
+\r
+#include <targets/LPC210x.h>\r
+\r
+#include "cs8900a.h"\r
+#include "uip.h"\r
+#include "uip_arp.h"\r
+\r
+#define IOR (1<<12) // CS8900's ISA-bus interface pins\r
+#define IOW (1<<13)\r
+\r
+// definitions for Crystal CS8900 ethernet-controller\r
+// based on linux-header by Russel Nelson\r
+\r
+#define PP_ChipID 0x0000 // offset 0h -> Corp-ID\r
+ \r
+ // offset 2h -> Model/Product Number\r
+#define LED_RED (1<<8)\r
+#define LED_GREEN (1<<10)\r
+#define LED_YELLOW (1<<11)\r
+\r
+#define PP_ISAIOB 0x0020 // IO base address\r
+#define PP_CS8900_ISAINT 0x0022 // ISA interrupt select\r
+#define PP_CS8900_ISADMA 0x0024 // ISA Rec DMA channel\r
+#define PP_ISASOF 0x0026 // ISA DMA offset\r
+#define PP_DmaFrameCnt 0x0028 // ISA DMA Frame count\r
+#define PP_DmaByteCnt 0x002A // ISA DMA Byte count\r
+#define PP_CS8900_ISAMemB 0x002C // Memory base\r
+#define PP_ISABootBase 0x0030 // Boot Prom base\r
+#define PP_ISABootMask 0x0034 // Boot Prom Mask\r
+\r
+// EEPROM data and command registers\r
+#define PP_EECMD 0x0040 // NVR Interface Command register\r
+#define PP_EEData 0x0042 // NVR Interface Data Register\r
+\r
+// Configuration and control registers\r
+#define PP_RxCFG 0x0102 // Rx Bus config\r
+#define PP_RxCTL 0x0104 // Receive Control Register\r
+#define PP_TxCFG 0x0106 // Transmit Config Register\r
+#define PP_TxCMD 0x0108 // Transmit Command Register\r
+#define PP_BufCFG 0x010A // Bus configuration Register\r
+#define PP_LineCTL 0x0112 // Line Config Register\r
+#define PP_SelfCTL 0x0114 // Self Command Register\r
+#define PP_BusCTL 0x0116 // ISA bus control Register\r
+#define PP_TestCTL 0x0118 // Test Register\r
+\r
+// Status and Event Registers\r
+#define PP_ISQ 0x0120 // Interrupt Status\r
+#define PP_RxEvent 0x0124 // Rx Event Register\r
+#define PP_TxEvent 0x0128 // Tx Event Register\r
+#define PP_BufEvent 0x012C // Bus Event Register\r
+#define PP_RxMiss 0x0130 // Receive Miss Count\r
+#define PP_TxCol 0x0132 // Transmit Collision Count\r
+#define PP_LineST 0x0134 // Line State Register\r
+#define PP_SelfST 0x0136 // Self State register\r
+#define PP_BusST 0x0138 // Bus Status\r
+#define PP_TDR 0x013C // Time Domain Reflectometry\r
+\r
+// Initiate Transmit Registers\r
+#define PP_TxCommand 0x0144 // Tx Command\r
+#define PP_TxLength 0x0146 // Tx Length\r
+\r
+// Adress Filter Registers\r
+#define PP_LAF 0x0150 // Hash Table\r
+#define PP_IA 0x0158 // Physical Address Register\r
+\r
+// Frame Location\r
+#define PP_RxStatus 0x0400 // Receive start of frame\r
+#define PP_RxLength 0x0402 // Receive Length of frame\r
+#define PP_RxFrame 0x0404 // Receive frame pointer\r
+#define PP_TxFrame 0x0A00 // Transmit frame pointer\r
+\r
+// Primary I/O Base Address. If no I/O base is supplied by the user, then this\r
+// can be used as the default I/O base to access the PacketPage Area.\r
+#define DEFAULTIOBASE 0x0300\r
+\r
+// PP_RxCFG - Receive Configuration and Interrupt Mask bit definition - Read/write\r
+#define SKIP_1 0x0040\r
+#define RX_STREAM_ENBL 0x0080\r
+#define RX_OK_ENBL 0x0100\r
+#define RX_DMA_ONLY 0x0200\r
+#define AUTO_RX_DMA 0x0400\r
+#define BUFFER_CRC 0x0800\r
+#define RX_CRC_ERROR_ENBL 0x1000\r
+#define RX_RUNT_ENBL 0x2000\r
+#define RX_EXTRA_DATA_ENBL 0x4000\r
+\r
+// PP_RxCTL - Receive Control bit definition - Read/write\r
+#define RX_IA_HASH_ACCEPT 0x0040\r
+#define RX_PROM_ACCEPT 0x0080\r
+#define RX_OK_ACCEPT 0x0100\r
+#define RX_MULTCAST_ACCEPT 0x0200\r
+#define RX_IA_ACCEPT 0x0400\r
+#define RX_BROADCAST_ACCEPT 0x0800\r
+#define RX_BAD_CRC_ACCEPT 0x1000\r
+#define RX_RUNT_ACCEPT 0x2000\r
+#define RX_EXTRA_DATA_ACCEPT 0x4000\r
+\r
+// PP_TxCFG - Transmit Configuration Interrupt Mask bit definition - Read/write\r
+#define TX_LOST_CRS_ENBL 0x0040\r
+#define TX_SQE_ERROR_ENBL 0x0080\r
+#define TX_OK_ENBL 0x0100\r
+#define TX_LATE_COL_ENBL 0x0200\r
+#define TX_JBR_ENBL 0x0400\r
+#define TX_ANY_COL_ENBL 0x0800\r
+#define TX_16_COL_ENBL 0x8000\r
+\r
+// PP_TxCMD - Transmit Command bit definition - Read-only and\r
+// PP_TxCommand - Write-only\r
+#define TX_START_5_BYTES 0x0000\r
+#define TX_START_381_BYTES 0x0040\r
+#define TX_START_1021_BYTES 0x0080\r
+#define TX_START_ALL_BYTES 0x00C0\r
+#define TX_FORCE 0x0100\r
+#define TX_ONE_COL 0x0200\r
+#define TX_NO_CRC 0x1000\r
+#define TX_RUNT 0x2000\r
+\r
+// PP_BufCFG - Buffer Configuration Interrupt Mask bit definition - Read/write\r
+#define GENERATE_SW_INTERRUPT 0x0040\r
+#define RX_DMA_ENBL 0x0080\r
+#define READY_FOR_TX_ENBL 0x0100\r
+#define TX_UNDERRUN_ENBL 0x0200\r
+#define RX_MISS_ENBL 0x0400\r
+#define RX_128_BYTE_ENBL 0x0800\r
+#define TX_COL_COUNT_OVRFLOW_ENBL 0x1000\r
+#define RX_MISS_COUNT_OVRFLOW_ENBL 0x2000\r
+#define RX_DEST_MATCH_ENBL 0x8000\r
+\r
+// PP_LineCTL - Line Control bit definition - Read/write\r
+#define SERIAL_RX_ON 0x0040\r
+#define SERIAL_TX_ON 0x0080\r
+#define AUI_ONLY 0x0100\r
+#define AUTO_AUI_10BASET 0x0200\r
+#define MODIFIED_BACKOFF 0x0800\r
+#define NO_AUTO_POLARITY 0x1000\r
+#define TWO_PART_DEFDIS 0x2000\r
+#define LOW_RX_SQUELCH 0x4000\r
+\r
+// PP_SelfCTL - Software Self Control bit definition - Read/write\r
+#define POWER_ON_RESET 0x0040\r
+#define SW_STOP 0x0100\r
+#define SLEEP_ON 0x0200\r
+#define AUTO_WAKEUP 0x0400\r
+#define HCB0_ENBL 0x1000\r
+#define HCB1_ENBL 0x2000\r
+#define HCB0 0x4000\r
+#define HCB1 0x8000\r
+\r
+// PP_BusCTL - ISA Bus Control bit definition - Read/write\r
+#define RESET_RX_DMA 0x0040\r
+#define MEMORY_ON 0x0400\r
+#define DMA_BURST_MODE 0x0800\r
+#define IO_CHANNEL_READY_ON 0x1000\r
+#define RX_DMA_SIZE_64K 0x2000\r
+#define ENABLE_IRQ 0x8000\r
+\r
+// PP_TestCTL - Test Control bit definition - Read/write\r
+#define LINK_OFF 0x0080\r
+#define ENDEC_LOOPBACK 0x0200\r
+#define AUI_LOOPBACK 0x0400\r
+#define BACKOFF_OFF 0x0800\r
+#define FDX_8900 0x4000\r
+\r
+// PP_RxEvent - Receive Event Bit definition - Read-only\r
+#define RX_IA_HASHED 0x0040\r
+#define RX_DRIBBLE 0x0080\r
+#define RX_OK 0x0100\r
+#define RX_HASHED 0x0200\r
+#define RX_IA 0x0400\r
+#define RX_BROADCAST 0x0800\r
+#define RX_CRC_ERROR 0x1000\r
+#define RX_RUNT 0x2000\r
+#define RX_EXTRA_DATA 0x4000\r
+#define HASH_INDEX_MASK 0xFC00 // Hash-Table Index Mask (6 Bit)\r
+\r
+// PP_TxEvent - Transmit Event Bit definition - Read-only\r
+#define TX_LOST_CRS 0x0040\r
+#define TX_SQE_ERROR 0x0080\r
+#define TX_OK 0x0100\r
+#define TX_LATE_COL 0x0200\r
+#define TX_JBR 0x0400\r
+#define TX_16_COL 0x8000\r
+#define TX_COL_COUNT_MASK 0x7800\r
+\r
+// PP_BufEvent - Buffer Event Bit definition - Read-only\r
+#define SW_INTERRUPT 0x0040\r
+#define RX_DMA 0x0080\r
+#define READY_FOR_TX 0x0100\r
+#define TX_UNDERRUN 0x0200\r
+#define RX_MISS 0x0400\r
+#define RX_128_BYTE 0x0800\r
+#define TX_COL_OVRFLW 0x1000\r
+#define RX_MISS_OVRFLW 0x2000\r
+#define RX_DEST_MATCH 0x8000\r
+\r
+// PP_LineST - Ethernet Line Status bit definition - Read-only\r
+#define LINK_OK 0x0080\r
+#define AUI_ON 0x0100\r
+#define TENBASET_ON 0x0200\r
+#define POLARITY_OK 0x1000\r
+#define CRS_OK 0x4000\r
+\r
+// PP_SelfST - Chip Software Status bit definition\r
+#define ACTIVE_33V 0x0040\r
+#define INIT_DONE 0x0080\r
+#define SI_BUSY 0x0100\r
+#define EEPROM_PRESENT 0x0200\r
+#define EEPROM_OK 0x0400\r
+#define EL_PRESENT 0x0800\r
+#define EE_SIZE_64 0x1000\r
+\r
+// PP_BusST - ISA Bus Status bit definition\r
+#define TX_BID_ERROR 0x0080\r
+#define READY_FOR_TX_NOW 0x0100\r
+\r
+// The following block defines the ISQ event types\r
+#define ISQ_RX_EVENT 0x0004\r
+#define ISQ_TX_EVENT 0x0008\r
+#define ISQ_BUFFER_EVENT 0x000C\r
+#define ISQ_RX_MISS_EVENT 0x0010\r
+#define ISQ_TX_COL_EVENT 0x0012\r
+\r
+#define ISQ_EVENT_MASK 0x003F // ISQ mask to find out type of event\r
+\r
+// Ports for I/O-Mode\r
+#define RX_FRAME_PORT 0x0000\r
+#define TX_FRAME_PORT 0x0000\r
+#define TX_CMD_PORT 0x0004\r
+#define TX_LEN_PORT 0x0006\r
+#define ISQ_PORT 0x0008\r
+#define ADD_PORT 0x000A\r
+#define DATA_PORT 0x000C\r
+\r
+#define AUTOINCREMENT 0x8000 // Bit mask to set Bit-15 for autoincrement\r
+\r
+// EEProm Commands\r
+#define EEPROM_WRITE_EN 0x00F0\r
+#define EEPROM_WRITE_DIS 0x0000\r
+#define EEPROM_WRITE_CMD 0x0100\r
+#define EEPROM_READ_CMD 0x0200\r
+\r
+// Receive Header of each packet in receive area of memory for DMA-Mode\r
+#define RBUF_EVENT_LOW 0x0000 // Low byte of RxEvent\r
+#define RBUF_EVENT_HIGH 0x0001 // High byte of RxEvent\r
+#define RBUF_LEN_LOW 0x0002 // Length of received data - low byte\r
+#define RBUF_LEN_HI 0x0003 // Length of received data - high byte\r
+#define RBUF_HEAD_LEN 0x0004 // Length of this header\r
+\r
+// typedefs\r
+typedef struct { // struct to store CS8900's\r
+ unsigned int Addr; // init-sequence\r
+ unsigned int Data;\r
+} TInitSeq;\r
+\r
+unsigned short ticks;\r
+\r
+static void skip_frame(void);\r
+\r
+const TInitSeq InitSeq[] =\r
+{\r
+ PP_IA, UIP_ETHADDR0 + (UIP_ETHADDR1 << 8), // set our MAC as Individual Address\r
+ PP_IA + 2, UIP_ETHADDR2 + (UIP_ETHADDR3 << 8),\r
+ PP_IA + 4, UIP_ETHADDR4 + (UIP_ETHADDR5 << 8),\r
+ PP_LineCTL, SERIAL_RX_ON | SERIAL_TX_ON, // configure the Physical Interface\r
+ PP_RxCTL, RX_OK_ACCEPT | RX_IA_ACCEPT | RX_BROADCAST_ACCEPT\r
+};\r
+\r
+// Writes a word in little-endian byte order to a specified port-address\r
+void\r
+cs8900a_write(unsigned addr, unsigned int data)\r
+{\r
+ IODIR |= 0xff << 16; // Data port to output\r
+\r
+ IOCLR = 0xf << 4; // Put address on bus\r
+ IOSET = addr << 4;\r
+ \r
+ IOCLR = 0xff << 16; // Write low order byte to data bus\r
+ IOSET = data << 16;\r
+\r
+ IOCLR = IOW; // Toggle IOW-signal\r
+ IOSET = IOW;\r
+\r
+ IOCLR = 0xf << 4;\r
+ IOSET = ((addr | 1) << 4); // And put next address on bus\r
+\r
+ IOCLR = 0xff << 16; // Write high order byte to data bus\r
+ IOSET = data >> 8 << 16;\r
+\r
+ IOCLR = IOW; // Toggle IOW-signal\r
+ IOSET = IOW;\r
+}\r
+\r
+// Reads a word in little-endian byte order from a specified port-address\r
+unsigned\r
+cs8900a_read(unsigned addr)\r
+{\r
+ unsigned int value;\r
+\r
+ IODIR &= ~(0xff << 16); // Data port to input\r
+\r
+ IOCLR = 0xf << 4; // Put address on bus\r
+ IOSET = addr << 4;\r
+\r
+ IOCLR = IOR; // IOR-signal low\r
+ value = (IOPIN >> 16) & 0xff; // get low order byte from data bus\r
+ IOSET = IOR;\r
+\r
+ IOSET = 1 << 4; // IOR high and put next address on bus\r
+\r
+ IOCLR = IOR; // IOR-signal low\r
+ value |= ((IOPIN >> 8) & 0xff00); // get high order byte from data bus\r
+ IOSET = IOR; // IOR-signal low\r
+ \r
+ return value;\r
+}\r
+\r
+// Reads a word in little-endian byte order from a specified port-address\r
+unsigned\r
+cs8900a_read_addr_high_first(unsigned addr)\r
+{\r
+ unsigned int value;\r
+\r
+ IODIR &= ~(0xff << 16); // Data port to input\r
+\r
+ IOCLR = 0xf << 4; // Put address on bus\r
+ IOSET = (addr+1) << 4;\r
+\r
+ IOCLR = IOR; // IOR-signal low\r
+ value = ((IOPIN >> 8) & 0xff00); // get high order byte from data bus\r
+ IOSET = IOR; // IOR-signal high\r
+\r
+ IOCLR = 1 << 4; // Put low address on bus\r
+\r
+ IOCLR = IOR; // IOR-signal low\r
+ value |= (IOPIN >> 16) & 0xff; // get low order byte from data bus\r
+ IOSET = IOR;\r
+\r
+ return value;\r
+}\r
+\r
+void\r
+cs8900a_init(void)\r
+{\r
+ int i;\r
+\r
+ // Reset outputs, control lines high\r
+ IOSET = IOR | IOW;\r
+\r
+ // No LEDs on.\r
+ IOSET = LED_RED | LED_YELLOW | LED_GREEN;\r
+\r
+ // Port 3 as output (all pins but RS232)\r
+ IODIR = ~0U; // everything to output.\r
+\r
+ // Reset outputs\r
+ IOCLR = 0xff << 16; // clear data outputs\r
+\r
+ // Reset the CS8900A\r
+ cs8900a_write(ADD_PORT, PP_SelfCTL);\r
+ cs8900a_write(DATA_PORT, POWER_ON_RESET);\r
+\r
+ // Wait until chip-reset is done\r
+ cs8900a_write(ADD_PORT, PP_SelfST);\r
+ while ((cs8900a_read(DATA_PORT) & INIT_DONE) == 0)\r
+ ;\r
+\r
+ // Configure the CS8900A\r
+ for (i = 0; i < sizeof InitSeq / sizeof (TInitSeq); ++i)\r
+ {\r
+ cs8900a_write(ADD_PORT, InitSeq[i].Addr);\r
+ cs8900a_write(DATA_PORT, InitSeq[i].Data);\r
+ }\r
+}\r
+\r
+void\r
+cs8900a_send(void)\r
+{\r
+ unsigned u;\r
+\r
+ IOCLR = LED_RED; // Light RED LED when frame starting\r
+\r
+ // Transmit command\r
+ cs8900a_write(TX_CMD_PORT, TX_START_ALL_BYTES);\r
+ cs8900a_write(TX_LEN_PORT, uip_len);\r
+\r
+ // Maximum number of retries\r
+ u = 8;\r
+ for (;;)\r
+ {\r
+ // Check for avaliable buffer space\r
+ cs8900a_write(ADD_PORT, PP_BusST);\r
+ if (cs8900a_read(DATA_PORT) & READY_FOR_TX_NOW)\r
+ break;\r
+ if (u -- == 0)\r
+ {\r
+ IOSET = LED_RED; // Extinguish RED LED on end of frame\r
+ return;\r
+ }\r
+\r
+ // No space avaliable, skip a received frame and try again\r
+ skip_frame();\r
+ }\r
+\r
+ IODIR |= 0xff << 16; // Data port to output\r
+\r
+ // Send 40+14=54 bytes of header\r
+ for (u = 0; u < 54; u += 2)\r
+ {\r
+ IOCLR = 0xf << 4; // Put address on bus\r
+ IOSET = TX_FRAME_PORT << 4;\r
+\r
+ IOCLR = 0xff << 16; // Write low order byte to data bus\r
+ IOSET = uip_buf[u] << 16; // write low order byte to data bus\r
+\r
+ IOCLR = IOW; // Toggle IOW-signal\r
+ IOSET = IOW;\r
+\r
+ IOCLR = 0xf << 4; // Put address on bus\r
+ IOSET = (TX_FRAME_PORT | 1) << 4; // and put next address on bus\r
+\r
+ IOCLR = 0xff << 16; // Write low order byte to data bus\r
+ IOSET = uip_buf[u+1] << 16; // write low order byte to data bus\r
+\r
+ IOCLR = IOW; // Toggle IOW-signal\r
+ IOSET = IOW;\r
+ }\r
+\r
+ if (uip_len <= 54)\r
+ {\r
+ IOSET = LED_RED; // Extinguish RED LED on end of frame\r
+ return;\r
+ }\r
+\r
+ // Send remainder of packet, the application data\r
+ uip_len -= 54;\r
+ for (u = 0; u < uip_len; u += 2)\r
+ {\r
+\r
+ IOCLR = 0xf << 4; // Put address on bus\r
+ IOSET = TX_FRAME_PORT << 4;\r
+\r
+ IOCLR = 0xff << 16; // Write low order byte to data bus\r
+ IOSET = uip_appdata[u] << 16; // write low order byte to data bus\r
+\r
+ IOCLR = IOW; // Toggle IOW-signal\r
+ IOSET = IOW;\r
+\r
+ IOCLR = 0xf << 4; // Put address on bus\r
+ IOSET = (TX_FRAME_PORT | 1) << 4; // and put next address on bus\r
+\r
+ IOCLR = 0xff << 16; // Write low order byte to data bus\r
+ IOSET = uip_appdata[u+1] << 16; // write low order byte to data bus\r
+\r
+ IOCLR = IOW; // Toggle IOW-signal\r
+ IOSET = IOW;\r
+ }\r
+\r
+ IOSET = LED_RED; // Extinguish RED LED on end of frame\r
+}\r
+\r
+static void\r
+skip_frame(void)\r
+{\r
+ // No space avaliable, skip a received frame and try again\r
+ cs8900a_write(ADD_PORT, PP_RxCFG);\r
+ cs8900a_write(DATA_PORT, cs8900a_read(DATA_PORT) | SKIP_1);\r
+}\r
+\r
+u8_t\r
+cs8900a_poll(void)\r
+{\r
+ u16_t len, u;\r
+\r
+ // Check receiver event register to see if there are any valid frames avaliable\r
+ cs8900a_write(ADD_PORT, PP_RxEvent);\r
+ if ((cs8900a_read(DATA_PORT) & 0xd00) == 0)\r
+ return 0;\r
+\r
+ IOCLR = LED_GREEN; // Light GREED LED when frame coming in.\r
+\r
+ // Read receiver status and discard it.\r
+ cs8900a_read_addr_high_first(RX_FRAME_PORT);\r
+\r
+ // Read frame length\r
+ len = cs8900a_read_addr_high_first(RX_FRAME_PORT);\r
+\r
+ // If the frame is too big to handle, throw it away\r
+ if (len > UIP_BUFSIZE)\r
+ {\r
+ skip_frame();\r
+ return 0;\r
+ }\r
+\r
+ // Data port to input\r
+ IODIR &= ~(0xff << 16);\r
+\r
+ IOCLR = 0xf << 4; // put address on bus\r
+ IOSET = RX_FRAME_PORT << 4; \r
+\r
+ // Read bytes into uip_buf\r
+ u = 0;\r
+ while (u < len)\r
+ {\r
+ IOCLR = 1 << 4; // put address on bus\r
+\r
+ IOCLR = IOR; // IOR-signal low\r
+ uip_buf[u] = IOPIN >> 16; // get high order byte from data bus\r
+ IOSET = IOR; // IOR-signal high\r
+\r
+ IOSET = 1 << 4; // put address on bus\r
+\r
+ IOCLR = IOR; // IOR-signal low\r
+ uip_buf[u+1] = IOPIN >> 16; // get high order byte from data bus\r
+ IOSET = IOR; // IOR-signal high\r
+ u += 2;\r
+ }\r
+\r
+ IOSET = LED_GREEN; // Extinguish GREED LED when frame finished.\r
+ return len;\r
+}\r
+\r
--- /dev/null
+#ifndef __CS8900A_H__\r
+#define __CS8900A_H__\r
+\r
+#include "uip_arch.h"\r
+\r
+void cs8900a_init(void);\r
+void cs8900a_send(void);\r
+u8_t cs8900a_poll(void);\r
+\r
+#endif /* __CS8900A_H__ */\r
--- /dev/null
+/**\r
+ * \addtogroup httpd\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * HTTP server read-only file system code.\r
+ * \author Adam Dunkels <adam@dunkels.com>\r
+ *\r
+ * A simple read-only filesystem. \r
+ */\r
+ \r
+/*\r
+ * Copyright (c) 2001, Swedish Institute of Computer Science.\r
+ * All rights reserved. \r
+ *\r
+ * Redistribution and use in source and binary forms, with or without \r
+ * modification, are permitted provided that the following conditions \r
+ * are met: \r
+ * 1. Redistributions of source code must retain the above copyright \r
+ * notice, this list of conditions and the following disclaimer. \r
+ * 2. Redistributions in binary form must reproduce the above copyright \r
+ * notice, this list of conditions and the following disclaimer in the \r
+ * documentation and/or other materials provided with the distribution. \r
+ * 3. Neither the name of the Institute nor the names of its contributors \r
+ * may be used to endorse or promote products derived from this software \r
+ * without specific prior written permission. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND \r
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE \r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE \r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE \r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL \r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS \r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) \r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT \r
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY \r
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF \r
+ * SUCH DAMAGE. \r
+ *\r
+ * This file is part of the lwIP TCP/IP stack.\r
+ * \r
+ * Author: Adam Dunkels <adam@sics.se>\r
+ *\r
+ * $Id: fs.c,v 1.7.2.3 2003/10/07 13:22:27 adam Exp $\r
+ */\r
+\r
+#include "uip.h"\r
+#include "httpd.h"\r
+#include "fs.h"\r
+#include "fsdata.h"\r
+\r
+#define NULL (void *)0\r
+#include "fsdata.c"\r
+\r
+#ifdef FS_STATISTICS\r
+#if FS_STATISTICS == 1\r
+static u16_t count[FS_NUMFILES];\r
+#endif /* FS_STATISTICS */\r
+#endif /* FS_STATISTICS */\r
+\r
+/*-----------------------------------------------------------------------------------*/\r
+static u8_t\r
+fs_strcmp(const char *str1, const char *str2)\r
+{\r
+ u8_t i;\r
+ i = 0;\r
+ loop:\r
+\r
+ if(str2[i] == 0 ||\r
+ str1[i] == '\r' || \r
+ str1[i] == '\n') {\r
+ return 0;\r
+ }\r
+\r
+ if(str1[i] != str2[i]) {\r
+ return 1;\r
+ }\r
+\r
+\r
+ ++i;\r
+ goto loop;\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+int\r
+fs_open(const char *name, struct fs_file *file)\r
+{\r
+#ifdef FS_STATISTICS\r
+#if FS_STATISTICS == 1\r
+ u16_t i = 0;\r
+#endif /* FS_STATISTICS */\r
+#endif /* FS_STATISTICS */\r
+ struct fsdata_file_noconst *f;\r
+\r
+ for(f = (struct fsdata_file_noconst *)FS_ROOT;\r
+ f != NULL;\r
+ f = (struct fsdata_file_noconst *)f->next) {\r
+\r
+ if(fs_strcmp(name, f->name) == 0) {\r
+ file->data = f->data;\r
+ file->len = f->len;\r
+#ifdef FS_STATISTICS\r
+#if FS_STATISTICS == 1\r
+ ++count[i];\r
+#endif /* FS_STATISTICS */\r
+#endif /* FS_STATISTICS */\r
+ return 1;\r
+ }\r
+#ifdef FS_STATISTICS\r
+#if FS_STATISTICS == 1\r
+ ++i;\r
+#endif /* FS_STATISTICS */\r
+#endif /* FS_STATISTICS */\r
+\r
+ }\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+void\r
+fs_init(void)\r
+{\r
+#ifdef FS_STATISTICS\r
+#if FS_STATISTICS == 1\r
+ u16_t i;\r
+ for(i = 0; i < FS_NUMFILES; i++) {\r
+ count[i] = 0;\r
+ }\r
+#endif /* FS_STATISTICS */\r
+#endif /* FS_STATISTICS */\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+#ifdef FS_STATISTICS\r
+#if FS_STATISTICS == 1 \r
+u16_t fs_count\r
+(char *name)\r
+{\r
+ struct fsdata_file_noconst *f;\r
+ u16_t i;\r
+\r
+ i = 0;\r
+ for(f = (struct fsdata_file_noconst *)FS_ROOT;\r
+ f != NULL;\r
+ f = (struct fsdata_file_noconst *)f->next) {\r
+\r
+ if(fs_strcmp(name, f->name) == 0) {\r
+ return count[i];\r
+ }\r
+ ++i;\r
+ }\r
+ return 0;\r
+}\r
+#endif /* FS_STATISTICS */\r
+#endif /* FS_STATISTICS */\r
+/*-----------------------------------------------------------------------------------*/\r
--- /dev/null
+/**\r
+ * \addtogroup httpd\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * HTTP server read-only file system header file.\r
+ * \author Adam Dunkels <adam@dunkels.com>\r
+ */\r
+ \r
+/*\r
+ * Copyright (c) 2001, Swedish Institute of Computer Science.\r
+ * All rights reserved. \r
+ *\r
+ * Redistribution and use in source and binary forms, with or without \r
+ * modification, are permitted provided that the following conditions \r
+ * are met: \r
+ * 1. Redistributions of source code must retain the above copyright \r
+ * notice, this list of conditions and the following disclaimer. \r
+ * 2. Redistributions in binary form must reproduce the above copyright \r
+ * notice, this list of conditions and the following disclaimer in the \r
+ * documentation and/or other materials provided with the distribution. \r
+ * 3. Neither the name of the Institute nor the names of its contributors \r
+ * may be used to endorse or promote products derived from this software \r
+ * without specific prior written permission. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND \r
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE \r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE \r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE \r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL \r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS \r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) \r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT \r
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY \r
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF \r
+ * SUCH DAMAGE. \r
+ *\r
+ * This file is part of the lwIP TCP/IP stack.\r
+ * \r
+ * Author: Adam Dunkels <adam@sics.se>\r
+ *\r
+ * $Id: fs.h,v 1.6.2.3 2003/10/07 13:22:27 adam Exp $\r
+ */\r
+#ifndef __FS_H__\r
+#define __FS_H__\r
+\r
+#include "uip.h"\r
+\r
+/**\r
+ * An open file in the read-only file system.\r
+ */\r
+struct fs_file {\r
+ char *data; /**< The actual file data. */\r
+ int len; /**< The length of the file data. */\r
+};\r
+\r
+/**\r
+ * Open a file in the read-only file system.\r
+ *\r
+ * \param name The name of the file.\r
+ *\r
+ * \param file The file pointer, which must be allocated by caller and\r
+ * will be filled in by the function.\r
+ */\r
+int fs_open(const char *name, struct fs_file *file);\r
+\r
+#ifdef FS_STATISTICS\r
+#if FS_STATISTICS == 1 \r
+u16_t fs_count(char *name);\r
+#endif /* FS_STATISTICS */\r
+#endif /* FS_STATISTICS */\r
+\r
+/**\r
+ * Initialize the read-only file system.\r
+ */\r
+void fs_init(void);\r
+\r
+#endif /* __FS_H__ */\r
--- /dev/null
+<html><body bgcolor="white"><center><h1>404 - file not found</h1></center></body></html>
\ No newline at end of file
--- /dev/null
+<html>\r
+<body bgcolor="white">\r
+<center>\r
+<table width="600" border="0"><tr><td>\r
+<h2>Welcome</h2>\r
+<p align="justify">\r
+These web pages are served by the small web server running on top of\r
+the <a href="http://dunkels.com/adam/uip/" target="_top">uIP TCP/IP\r
+stack</a>.\r
+</p>\r
+<p align="justify">\r
+Click on the links above to see some status information about the web\r
+server and the TCP/IP stack.\r
+</p>\r
+</td></tr></table>\r
+</center>\r
+</body>\r
+</html>
\ No newline at end of file
--- /dev/null
+# This script shows the access statistics for different files on the\r
+# web server.\r
+#\r
+# First, we include the HTML header.\r
+i /files_header.html\r
+# Print out the name of the file, and call the function that prints\r
+# the access statistics of that file.\r
+t <tr><td><a href="/index.html">/index.html</a></td><td>\r
+c b /index.html\r
+t </td></tr> <tr><td><a href="/about.html">/about.html</a></td><td>\r
+c b /about.html\r
+t </td></tr> <tr><td><a href="/control.html">/control.html</a></td><td>\r
+c b /control.html\r
+t </td></tr> <tr><td><a href="/img/bg.png">/img/bg.png</a></td><td>\r
+c b /img/bg.png\r
+t </td></tr> <tr><td><a href="/404.html">/404.html</a></td><td>\r
+c b /404.html\r
+t </td></tr> <tr><td><a href="/cgi/files">/cgi/files</a></td><td>\r
+c b /cgi/files\r
+t </td></tr> <tr><td><a href="/cgi/stats">/cgi/stats</a></td><td>\r
+c b /cgi/stats\r
+t </td></tr> <tr><td><a href="/cgi/tcp">/cgi/tcp</a></td><td>\r
+c b /cgi/tcp\r
+t </td></tr>\r
+# Include the HTML footer.\r
+i /files_footer.plain\r
+# End of script.\r
+.
\ No newline at end of file
--- /dev/null
+i /stats_header.html\r
+c a\r
+i /stats_footer.plain\r
+.\r
--- /dev/null
+i /tcp_header.html\r
+c c\r
+i /tcp_footer.plain\r
+.
\ No newline at end of file
--- /dev/null
+<html>\r
+<body bgcolor="white">\r
+<center>\r
+<table width="797" height="94" border="0" cellpadding="0"\r
+ cellspacing="0" background="/img/bg.png"><tr><td align="center">\r
+<h1>uIP web server test pages</h1>\r
+[ <a href="about.html" target="main">About</a> |\r
+<a href="/cgi/tcp" target="main">Connections</a> |\r
+<a href="/cgi/files" target="main">Files</a> |\r
+<a href="/cgi/stats" target="main">Statistics</a> ]\r
+</td></tr></table>\r
+</center>\r
+</body>\r
+</html>
\ No newline at end of file
--- /dev/null
+</td></tr></table>\r
+</body>\r
+</html>\r
--- /dev/null
+<html>\r
+<body bgcolor="white">\r
+<center>\r
+<table width="600" border="0">\r
--- /dev/null
+<html>\r
+<head><title>uIP web server test page</title></head>\r
+\r
+<frameset cols="*" rows="120,*" frameborder="no"> \r
+ <frame src="control.html">\r
+ <frame src="about.html" name="main">\r
+</frameset>\r
+\r
+<noframes>\r
+<body>\r
+Your browser must support frames\r
+</body>\r
+</noframes>\r
+</html>
\ No newline at end of file
--- /dev/null
+</td></tr></table>\r
+</body>\r
+</html>\r
--- /dev/null
+<html>\r
+<body bgcolor="white">\r
+<center>\r
+<table width="600" border="0">\r
+<tr><td>\r
+<pre>\r
+IP Packets dropped\r
+ Packets received\r
+ Packets sent\r
+IP errors IP version/header length\r
+ IP length, high byte\r
+ IP length, low byte\r
+ IP fragments\r
+ Header checksum\r
+ Wrong protocol\r
+ICMP Packets dropped\r
+ Packets received\r
+ Packets sent\r
+ Type errors\r
+TCP Packets dropped\r
+ Packets received\r
+ Packets sent\r
+ Checksum errors\r
+ Data packets without ACKs\r
+ Resets\r
+ Retransmissions\r
+ No connection avaliable\r
+ Connection attempts to closed ports\r
+</pre> \r
+</td><td><pre>
\ No newline at end of file
--- /dev/null
+\r
+</td></tr></table>\r
+</center>\r
+</body>\r
+</html>
\ No newline at end of file
--- /dev/null
+<html>\r
+<body bgcolor="white">\r
+<center>\r
+<table width="600" border="0">\r
+<tr><th>Remote</th><th>State</th><th>Retransmissions</th><th>Timer</th><th>Flags</th></tr>\r
+\r
--- /dev/null
+static const char data_cgi_files[] = {\r
+ /* /cgi/files */\r
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+\r
+static const char data_cgi_stats[] = {\r
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+\r
+static const char data_cgi_tcp[] = {\r
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+\r
+static const char data_img_bg_png[] = {\r
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+ 0x74, 0x64, 0x3e, 0x3c, 0x70, 0x72, 0x65, 0x3e, };\r
+\r
+static const char data_tcp_footer_plain[] = {\r
+ /* /tcp_footer.plain */\r
+ 0x2f, 0x74, 0x63, 0x70, 0x5f, 0x66, 0x6f, 0x6f, 0x74, 0x65, 0x72, 0x2e, 0x70, 0x6c, 0x61, 0x69, 0x6e, 0,\r
+ 0xa, 0x3c, 0x2f, 0x74, 0x64, 0x3e, 0x3c, 0x2f, 0x74, 0x72, \r
+ 0x3e, 0x3c, 0x2f, 0x74, 0x61, 0x62, 0x6c, 0x65, 0x3e, 0xa, \r
+ 0x3c, 0x2f, 0x63, 0x65, 0x6e, 0x74, 0x65, 0x72, 0x3e, 0xa, \r
+ 0x3c, 0x2f, 0x62, 0x6f, 0x64, 0x79, 0x3e, 0xa, 0x3c, 0x2f, \r
+ 0x68, 0x74, 0x6d, 0x6c, 0x3e, };\r
+\r
+static const char data_tcp_header_html[] = {\r
+ /* /tcp_header.html */\r
+ 0x2f, 0x74, 0x63, 0x70, 0x5f, 0x68, 0x65, 0x61, 0x64, 0x65, 0x72, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0,\r
+ 0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x32, \r
+ 0x30, 0x30, 0x20, 0x4f, 0x4b, 0xd, 0xa, 0x53, 0x65, 0x72, \r
+ 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x30, \r
+ 0x2e, 0x39, 0x20, 0x28, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, \r
+ 0x2f, 0x64, 0x75, 0x6e, 0x6b, 0x65, 0x6c, 0x73, 0x2e, 0x63, \r
+ 0x6f, 0x6d, 0x2f, 0x61, 0x64, 0x61, 0x6d, 0x2f, 0x75, 0x69, \r
+ 0x70, 0x2f, 0x29, 0xd, 0xa, 0x43, 0x6f, 0x6e, 0x74, 0x65, \r
+ 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, \r
+ 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0xd, 0xa, \r
+ 0xd, 0xa, 0x3c, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0xa, 0x3c, \r
+ 0x62, 0x6f, 0x64, 0x79, 0x20, 0x62, 0x67, 0x63, 0x6f, 0x6c, \r
+ 0x6f, 0x72, 0x3d, 0x22, 0x77, 0x68, 0x69, 0x74, 0x65, 0x22, \r
+ 0x3e, 0xa, 0x3c, 0x63, 0x65, 0x6e, 0x74, 0x65, 0x72, 0x3e, \r
+ 0xa, 0x3c, 0x74, 0x61, 0x62, 0x6c, 0x65, 0x20, 0x77, 0x69, \r
+ 0x64, 0x74, 0x68, 0x3d, 0x22, 0x36, 0x30, 0x30, 0x22, 0x20, \r
+ 0x62, 0x6f, 0x72, 0x64, 0x65, 0x72, 0x3d, 0x22, 0x30, 0x22, \r
+ 0x3e, 0xa, 0x3c, 0x74, 0x72, 0x3e, 0x3c, 0x74, 0x68, 0x3e, \r
+ 0x52, 0x65, 0x6d, 0x6f, 0x74, 0x65, 0x3c, 0x2f, 0x74, 0x68, \r
+ 0x3e, 0x3c, 0x74, 0x68, 0x3e, 0x53, 0x74, 0x61, 0x74, 0x65, \r
+ 0x3c, 0x2f, 0x74, 0x68, 0x3e, 0x3c, 0x74, 0x68, 0x3e, 0x52, \r
+ 0x65, 0x74, 0x72, 0x61, 0x6e, 0x73, 0x6d, 0x69, 0x73, 0x73, \r
+ 0x69, 0x6f, 0x6e, 0x73, 0x3c, 0x2f, 0x74, 0x68, 0x3e, 0x3c, \r
+ 0x74, 0x68, 0x3e, 0x54, 0x69, 0x6d, 0x65, 0x72, 0x3c, 0x2f, \r
+ 0x74, 0x68, 0x3e, 0x3c, 0x74, 0x68, 0x3e, 0x46, 0x6c, 0x61, \r
+ 0x67, 0x73, 0x3c, 0x2f, 0x74, 0x68, 0x3e, 0x3c, 0x2f, 0x74, \r
+ 0x72, 0x3e, 0xa, 0xa, };\r
+\r
+const struct fsdata_file file_cgi_files[] = {{NULL, data_cgi_files, data_cgi_files + 11, sizeof(data_cgi_files) - 11}};\r
+\r
+const struct fsdata_file file_cgi_stats[] = {{file_cgi_files, data_cgi_stats, data_cgi_stats + 11, sizeof(data_cgi_stats) - 11}};\r
+\r
+const struct fsdata_file file_cgi_tcp[] = {{file_cgi_stats, data_cgi_tcp, data_cgi_tcp + 9, sizeof(data_cgi_tcp) - 9}};\r
+\r
+const struct fsdata_file file_img_bg_png[] = {{file_cgi_tcp, data_img_bg_png, data_img_bg_png + 12, sizeof(data_img_bg_png) - 12}};\r
+\r
+const struct fsdata_file file_about_html[] = {{file_img_bg_png, data_about_html, data_about_html + 12, sizeof(data_about_html) - 12}};\r
+\r
+const struct fsdata_file file_control_html[] = {{file_about_html, data_control_html, data_control_html + 14, sizeof(data_control_html) - 14}};\r
+\r
+const struct fsdata_file file_404_html[] = {{file_control_html, data_404_html, data_404_html + 10, sizeof(data_404_html) - 10}};\r
+\r
+const struct fsdata_file file_files_footer_plain[] = {{file_404_html, data_files_footer_plain, data_files_footer_plain + 20, sizeof(data_files_footer_plain) - 20}};\r
+\r
+const struct fsdata_file file_files_header_html[] = {{file_files_footer_plain, data_files_header_html, data_files_header_html + 19, sizeof(data_files_header_html) - 19}};\r
+\r
+const struct fsdata_file file_index_html[] = {{file_files_header_html, data_index_html, data_index_html + 12, sizeof(data_index_html) - 12}};\r
+\r
+const struct fsdata_file file_stats_footer_plain[] = {{file_index_html, data_stats_footer_plain, data_stats_footer_plain + 20, sizeof(data_stats_footer_plain) - 20}};\r
+\r
+const struct fsdata_file file_stats_header_html[] = {{file_stats_footer_plain, data_stats_header_html, data_stats_header_html + 19, sizeof(data_stats_header_html) - 19}};\r
+\r
+const struct fsdata_file file_tcp_footer_plain[] = {{file_stats_header_html, data_tcp_footer_plain, data_tcp_footer_plain + 18, sizeof(data_tcp_footer_plain) - 18}};\r
+\r
+const struct fsdata_file file_tcp_header_html[] = {{file_tcp_footer_plain, data_tcp_header_html, data_tcp_header_html + 17, sizeof(data_tcp_header_html) - 17}};\r
+\r
+#define FS_ROOT file_tcp_header_html\r
+\r
+#define FS_NUMFILES 14\r
--- /dev/null
+/*\r
+ * Copyright (c) 2001, Swedish Institute of Computer Science.\r
+ * All rights reserved. \r
+ *\r
+ * Redistribution and use in source and binary forms, with or without \r
+ * modification, are permitted provided that the following conditions \r
+ * are met: \r
+ * 1. Redistributions of source code must retain the above copyright \r
+ * notice, this list of conditions and the following disclaimer. \r
+ * 2. Redistributions in binary form must reproduce the above copyright \r
+ * notice, this list of conditions and the following disclaimer in the \r
+ * documentation and/or other materials provided with the distribution. \r
+ * 3. Neither the name of the Institute nor the names of its contributors \r
+ * may be used to endorse or promote products derived from this software \r
+ * without specific prior written permission. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND \r
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE \r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE \r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE \r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL \r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS \r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) \r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT \r
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY \r
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF \r
+ * SUCH DAMAGE. \r
+ *\r
+ * This file is part of the lwIP TCP/IP stack.\r
+ * \r
+ * Author: Adam Dunkels <adam@sics.se>\r
+ *\r
+ * $Id: fsdata.h,v 1.4.2.1 2003/10/04 22:54:06 adam Exp $\r
+ */\r
+#ifndef __FSDATA_H__\r
+#define __FSDATA_H__\r
+\r
+#include "uipopt.h"\r
+\r
+struct fsdata_file {\r
+ const struct fsdata_file *next;\r
+ const char *name;\r
+ const char *data;\r
+ const int len;\r
+#ifdef FS_STATISTICS\r
+#if FS_STATISTICS == 1\r
+ u16_t count;\r
+#endif /* FS_STATISTICS */\r
+#endif /* FS_STATISTICS */\r
+};\r
+\r
+struct fsdata_file_noconst {\r
+ struct fsdata_file *next;\r
+ char *name;\r
+ char *data;\r
+ int len;\r
+#ifdef FS_STATISTICS\r
+#if FS_STATISTICS == 1\r
+ u16_t count;\r
+#endif /* FS_STATISTICS */\r
+#endif /* FS_STATISTICS */\r
+};\r
+\r
+#endif /* __FSDATA_H__ */\r
--- /dev/null
+/**\r
+ * \addtogroup exampleapps\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \defgroup httpd Web server\r
+ * @{\r
+ *\r
+ * The uIP web server is a very simplistic implementation of an HTTP\r
+ * server. It can serve web pages and files from a read-only ROM\r
+ * filesystem, and provides a very small scripting language.\r
+ *\r
+ * The script language is very simple and works as follows. Each\r
+ * script line starts with a command character, either "i", "t", "c",\r
+ * "#" or ".". The "i" command tells the script interpreter to\r
+ * "include" a file from the virtual file system and output it to the\r
+ * web browser. The "t" command should be followed by a line of text\r
+ * that is to be output to the browser. The "c" command is used to\r
+ * call one of the C functions from the httpd-cgi.c file. A line that\r
+ * starts with a "#" is ignored (i.e., the "#" denotes a comment), and\r
+ * the "." denotes the last script line.\r
+ *\r
+ * The script that produces the file statistics page looks somewhat\r
+ * like this:\r
+ *\r
+ \code\r
+i /header.html\r
+t <h1>File statistics</h1><br><table width="100%">\r
+t <tr><td><a href="/index.html">/index.html</a></td><td>\r
+c a /index.html\r
+t </td></tr> <tr><td><a href="/cgi/files">/cgi/files</a></td><td>\r
+c a /cgi/files\r
+t </td></tr> <tr><td><a href="/cgi/tcp">/cgi/tcp</a></td><td>\r
+c a /cgi/tcp\r
+t </td></tr> <tr><td><a href="/404.html">/404.html</a></td><td>\r
+c a /404.html\r
+t </td></tr></table>\r
+i /footer.plain\r
+.\r
+ \endcode\r
+ *\r
+ */\r
+\r
+\r
+/**\r
+ * \file\r
+ * HTTP server.\r
+ * \author Adam Dunkels <adam@dunkels.com>\r
+ */\r
+\r
+/*\r
+ * Copyright (c) 2001, Adam Dunkels.\r
+ * All rights reserved. \r
+ *\r
+ * Redistribution and use in source and binary forms, with or without \r
+ * modification, are permitted provided that the following conditions \r
+ * are met: \r
+ * 1. Redistributions of source code must retain the above copyright \r
+ * notice, this list of conditions and the following disclaimer. \r
+ * 2. Redistributions in binary form must reproduce the above copyright \r
+ * notice, this list of conditions and the following disclaimer in the \r
+ * documentation and/or other materials provided with the distribution. \r
+ * 3. The name of the author may not be used to endorse or promote\r
+ * products derived from this software without specific prior\r
+ * written permission. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * $Id: httpd.c,v 1.28.2.6 2003/10/07 13:22:27 adam Exp $\r
+ *\r
+ */\r
+\r
+\r
+#include "uip.h"\r
+#include "httpd.h"\r
+#include "fs.h"\r
+#include "fsdata.h"\r
+#include "cgi.h"\r
+\r
+#define NULL (void *)0\r
+\r
+/* The HTTP server states: */\r
+#define HTTP_NOGET 0\r
+#define HTTP_FILE 1\r
+#define HTTP_TEXT 2\r
+#define HTTP_FUNC 3\r
+#define HTTP_END 4\r
+\r
+#ifdef DEBUG\r
+#include <stdio.h>\r
+#define PRINT(x) \r
+#define PRINTLN(x)\r
+#else /* DEBUG */\r
+#define PRINT(x)\r
+#define PRINTLN(x)\r
+#endif /* DEBUG */\r
+\r
+struct httpd_state *hs;\r
+\r
+extern const struct fsdata_file file_index_html;\r
+extern const struct fsdata_file file_404_html;\r
+\r
+static void next_scriptline(void);\r
+static void next_scriptstate(void);\r
+\r
+#define ISO_G 0x47\r
+#define ISO_E 0x45\r
+#define ISO_T 0x54\r
+#define ISO_slash 0x2f \r
+#define ISO_c 0x63\r
+#define ISO_g 0x67\r
+#define ISO_i 0x69\r
+#define ISO_space 0x20\r
+#define ISO_nl 0x0a\r
+#define ISO_cr 0x0d\r
+#define ISO_a 0x61\r
+#define ISO_t 0x74\r
+#define ISO_hash 0x23\r
+#define ISO_period 0x2e\r
+\r
+#define httpPORT 80\r
+\r
+/*-----------------------------------------------------------------------------------*/\r
+/**\r
+ * Initialize the web server.\r
+ *\r
+ * Starts to listen for incoming connection requests on TCP port 80.\r
+ */\r
+/*-----------------------------------------------------------------------------------*/\r
+void\r
+httpd_init(void)\r
+{\r
+ fs_init();\r
+ \r
+ /* Listen to port 80. */\r
+ uip_listen(HTONS(httpPORT));\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+void\r
+httpd_appcall(void)\r
+{\r
+ struct fs_file fsfile; \r
+\r
+ u8_t i;\r
+\r
+ switch(uip_conn->lport) {\r
+ /* This is the web server: */\r
+ case HTONS(httpPORT):\r
+ /* Pick out the application state from the uip_conn structure. */\r
+ hs = (struct httpd_state *)(uip_conn->appstate);\r
+\r
+ /* We use the uip_ test functions to deduce why we were\r
+ called. If uip_connected() is non-zero, we were called\r
+ because a remote host has connected to us. If\r
+ uip_newdata() is non-zero, we were called because the\r
+ remote host has sent us new data, and if uip_acked() is\r
+ non-zero, the remote host has acknowledged the data we\r
+ previously sent to it. */\r
+ if(uip_connected()) {\r
+ /* Since we have just been connected with the remote host, we\r
+ reset the state for this connection. The ->count variable\r
+ contains the amount of data that is yet to be sent to the\r
+ remote host, and the ->state is set to HTTP_NOGET to signal\r
+ that we haven't received any HTTP GET request for this\r
+ connection yet. */\r
+\r
+ hs->state = HTTP_NOGET;\r
+ hs->count = 0;\r
+ return;\r
+\r
+ } else if(uip_poll()) {\r
+ /* If we are polled ten times, we abort the connection. This is\r
+ because we don't want connections lingering indefinately in\r
+ the system. */\r
+ if(hs->count++ >= 10) {\r
+ uip_abort();\r
+ }\r
+ return;\r
+ } else if(uip_newdata() && hs->state == HTTP_NOGET) {\r
+ /* This is the first data we receive, and it should contain a\r
+ GET. */\r
+\r
+ /* Check for GET. */\r
+ if(uip_appdata[0] != ISO_G ||\r
+ uip_appdata[1] != ISO_E ||\r
+ uip_appdata[2] != ISO_T ||\r
+ uip_appdata[3] != ISO_space) {\r
+ /* If it isn't a GET, we abort the connection. */\r
+ uip_abort();\r
+ return;\r
+ }\r
+ \r
+ /* Find the file we are looking for. */\r
+ for(i = 4; i < 40; ++i) {\r
+ if(uip_appdata[i] == ISO_space ||\r
+ uip_appdata[i] == ISO_cr ||\r
+ uip_appdata[i] == ISO_nl) {\r
+ uip_appdata[i] = 0;\r
+ break;\r
+ }\r
+ }\r
+\r
+ PRINT("request for file ");\r
+ PRINTLN(&uip_appdata[4]);\r
+ \r
+ /* Check for a request for "/". */\r
+ if(uip_appdata[4] == ISO_slash &&\r
+ uip_appdata[5] == 0) {\r
+ fs_open(file_index_html.name, &fsfile); \r
+ } else {\r
+ if(!fs_open((const char *)&uip_appdata[4], &fsfile)) {\r
+ PRINTLN("couldn't open file");\r
+ fs_open(file_404_html.name, &fsfile);\r
+ }\r
+ } \r
+\r
+\r
+ if(uip_appdata[4] == ISO_slash &&\r
+ uip_appdata[5] == ISO_c &&\r
+ uip_appdata[6] == ISO_g &&\r
+ uip_appdata[7] == ISO_i &&\r
+ uip_appdata[8] == ISO_slash) {\r
+ /* If the request is for a file that starts with "/cgi/", we\r
+ prepare for invoking a script. */ \r
+ hs->script = fsfile.data;\r
+ next_scriptstate();\r
+ } else {\r
+ hs->script = NULL;\r
+ /* The web server is now no longer in the HTTP_NOGET state, but\r
+ in the HTTP_FILE state since is has now got the GET from\r
+ the client and will start transmitting the file. */\r
+ hs->state = HTTP_FILE;\r
+\r
+ /* Point the file pointers in the connection state to point to\r
+ the first byte of the file. */\r
+ hs->dataptr = fsfile.data;\r
+ hs->count = fsfile.len; \r
+ } \r
+ }\r
+\r
+ \r
+ if(hs->state != HTTP_FUNC) {\r
+ /* Check if the client (remote end) has acknowledged any data that\r
+ we've previously sent. If so, we move the file pointer further\r
+ into the file and send back more data. If we are out of data to\r
+ send, we close the connection. */\r
+ if(uip_acked()) {\r
+ if(hs->count >= uip_conn->len) {\r
+ hs->count -= uip_conn->len;\r
+ hs->dataptr += uip_conn->len;\r
+ } else {\r
+ hs->count = 0;\r
+ }\r
+ \r
+ if(hs->count == 0) {\r
+ if(hs->script != NULL) {\r
+ next_scriptline();\r
+ next_scriptstate();\r
+ } else {\r
+ uip_close();\r
+ }\r
+ }\r
+ } \r
+ } else {\r
+ /* Call the CGI function. */\r
+ if(cgitab[hs->script[2] - ISO_a](uip_acked())) {\r
+ /* If the function returns non-zero, we jump to the next line\r
+ in the script. */\r
+ next_scriptline();\r
+ next_scriptstate();\r
+ }\r
+ }\r
+\r
+ if(hs->state != HTTP_FUNC && !uip_poll()) {\r
+ /* Send a piece of data, but not more than the MSS of the\r
+ connection. */\r
+ uip_send(hs->dataptr, hs->count);\r
+ }\r
+\r
+ /* Finally, return to uIP. Our outgoing packet will soon be on its\r
+ way... */\r
+ return;\r
+\r
+ default:\r
+ /* Should never happen. */\r
+ uip_abort();\r
+ break;\r
+ } \r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+/* next_scriptline():\r
+ *\r
+ * Reads the script until it finds a newline. */\r
+static void\r
+next_scriptline(void)\r
+{\r
+ /* Loop until we find a newline character. */\r
+ do {\r
+ ++(hs->script);\r
+ } while(hs->script[0] != ISO_nl);\r
+\r
+ /* Eat up the newline as well. */\r
+ ++(hs->script);\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+/* next_sciptstate:\r
+ *\r
+ * Reads one line of script and decides what to do next.\r
+ */\r
+static void\r
+next_scriptstate(void)\r
+{\r
+ struct fs_file fsfile;\r
+ u8_t i;\r
+\r
+ again:\r
+ switch(hs->script[0]) {\r
+ case ISO_t:\r
+ /* Send a text string. */\r
+ hs->state = HTTP_TEXT;\r
+ hs->dataptr = &hs->script[2];\r
+\r
+ /* Calculate length of string. */\r
+ for(i = 0; hs->dataptr[i] != ISO_nl; ++i);\r
+ hs->count = i; \r
+ break;\r
+ case ISO_c:\r
+ /* Call a function. */\r
+ hs->state = HTTP_FUNC;\r
+ hs->dataptr = NULL;\r
+ hs->count = 0;\r
+ cgitab[hs->script[2] - ISO_a](0);\r
+ break;\r
+ case ISO_i: \r
+ /* Include a file. */\r
+ hs->state = HTTP_FILE;\r
+ if(!fs_open(&hs->script[2], &fsfile)) {\r
+ uip_abort();\r
+ }\r
+ hs->dataptr = fsfile.data;\r
+ hs->count = fsfile.len;\r
+ break;\r
+ case ISO_hash:\r
+ /* Comment line. */\r
+ next_scriptline();\r
+ goto again;\r
+ break;\r
+ case ISO_period:\r
+ /* End of script. */\r
+ hs->state = HTTP_END;\r
+ uip_close();\r
+ break;\r
+ default:\r
+ uip_abort();\r
+ break;\r
+ }\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+/** @} */\r
+/** @} */\r
--- /dev/null
+/**\r
+ * \addtogroup httpd\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * HTTP server header file.\r
+ * \author Adam Dunkels <adam@dunkels.com>\r
+ */\r
+\r
+/*\r
+ * Copyright (c) 2001, Adam Dunkels.\r
+ * All rights reserved. \r
+ *\r
+ * Redistribution and use in source and binary forms, with or without \r
+ * modification, are permitted provided that the following conditions \r
+ * are met: \r
+ * 1. Redistributions of source code must retain the above copyright \r
+ * notice, this list of conditions and the following disclaimer. \r
+ * 2. Redistributions in binary form must reproduce the above copyright \r
+ * notice, this list of conditions and the following disclaimer in the \r
+ * documentation and/or other materials provided with the distribution. \r
+ * 3. The name of the author may not be used to endorse or promote\r
+ * products derived from this software without specific prior\r
+ * written permission. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * $Id: httpd.h,v 1.4.2.3 2003/10/06 22:56:44 adam Exp $\r
+ *\r
+ */\r
+\r
+#ifndef __HTTPD_H__\r
+#define __HTTPD_H__\r
+\r
+void httpd_init(void);\r
+void httpd_appcall(void);\r
+\r
+/* UIP_APPCALL: the name of the application function. This function\r
+ must return void and take no arguments (i.e., C type "void\r
+ appfunc(void)"). */\r
+#ifndef UIP_APPCALL\r
+#define UIP_APPCALL httpd_appcall\r
+#endif\r
+\r
+struct httpd_state {\r
+ u8_t state; \r
+ u16_t count;\r
+ char *dataptr;\r
+ char *script;\r
+};\r
+\r
+\r
+/* UIP_APPSTATE_SIZE: The size of the application-specific state\r
+ stored in the uip_conn structure. */\r
+#ifndef UIP_APPSTATE_SIZE\r
+#define UIP_APPSTATE_SIZE (sizeof(struct httpd_state))\r
+#endif\r
+\r
+#define FS_STATISTICS 1\r
+\r
+extern struct httpd_state *hs;\r
+\r
+#endif /* __HTTPD_H__ */\r
--- /dev/null
+// Copyright (c) 2001-2004 Rowley Associates Limited.\r
+//\r
+// This file may be distributed under the terms of the License Agreement\r
+// provided with this software.\r
+//\r
+// THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE\r
+// WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\r
+//\r
+////////////////////////////////////////////////////////////////////////////////\r
+//\r
+// Olimex LPC-P1 LED Example\r
+//\r
+// Description\r
+// -----------\r
+// This example demonstrates writing to the programmable peripheral interface.\r
+//\r
+////////////////////////////////////////////////////////////////////////////////\r
+\r
+#include <targets/LPC210x.h>\r
+\r
+#define LED_RED (1<<8)\r
+#define LED_GREEN (1<<10)\r
+#define LED_YELLOW (1<<11)\r
+\r
+#define LED1 LED_YELLOW\r
+\r
+static void\r
+ledInit()\r
+{\r
+ IODIR |= LED1;\r
+ IOSET = LED1;\r
+}\r
+\r
+static void\r
+ledOn(void)\r
+{\r
+ IOCLR = LED1;\r
+}\r
+\r
+static void\r
+ledOff(void)\r
+{\r
+ IOSET = LED1;\r
+}\r
+\r
+void\r
+delay(int d)\r
+{ \r
+ for(; d; --d);\r
+}\r
+ \r
+int\r
+main(void)\r
+{\r
+ MAMCR = 2;\r
+ ledInit();\r
+ while (1)\r
+ {\r
+ ledOn();\r
+ delay(100000);\r
+ ledOff();\r
+ delay(100000);\r
+ }\r
+ return 0;\r
+}\r
+\r
+\r
--- /dev/null
+#!/usr/bin/perl\r
+\r
+open(OUTPUT, "> fsdata.c");\r
+\r
+chdir("fs");\r
+open(FILES, "find . -type f |");\r
+\r
+while($file = <FILES>) {\r
+\r
+ # Do not include files in CVS directories nor backup files.\r
+ if($file =~ /(CVS|~)/) {\r
+ next;\r
+ }\r
+ \r
+ chop($file);\r
+ \r
+ open(HEADER, "> /tmp/header") || die $!;\r
+ if($file =~ /404.html/) {\r
+ print(HEADER "HTTP/1.0 404 File not found\r\n");\r
+ } else {\r
+ print(HEADER "HTTP/1.0 200 OK\r\n");\r
+ }\r
+ print(HEADER "Server: uIP/0.9 (http://dunkels.com/adam/uip/)\r\n");\r
+ if($file =~ /\.html$/) {\r
+ print(HEADER "Content-type: text/html\r\n");\r
+ } elsif($file =~ /\.gif$/) {\r
+ print(HEADER "Content-type: image/gif\r\n");\r
+ } elsif($file =~ /\.png$/) {\r
+ print(HEADER "Content-type: image/png\r\n");\r
+ } elsif($file =~ /\.jpg$/) {\r
+ print(HEADER "Content-type: image/jpeg\r\n");\r
+ } else {\r
+ print(HEADER "Content-type: text/plain\r\n");\r
+ }\r
+ print(HEADER "\r\n");\r
+ close(HEADER);\r
+\r
+ unless($file =~ /\.plain$/ || $file =~ /cgi/) {\r
+ system("cat /tmp/header $file > /tmp/file");\r
+ } else {\r
+ system("cp $file /tmp/file");\r
+ }\r
+ \r
+ open(FILE, "/tmp/file");\r
+ unlink("/tmp/file");\r
+ unlink("/tmp/header");\r
+\r
+ $file =~ s/\.//;\r
+ $fvar = $file;\r
+ $fvar =~ s-/-_-g;\r
+ $fvar =~ s-\.-_-g;\r
+ print(OUTPUT "static const char data".$fvar."[] = {\n");\r
+ print(OUTPUT "\t/* $file */\n\t");\r
+ for($j = 0; $j < length($file); $j++) {\r
+ printf(OUTPUT "%#02x, ", unpack("C", substr($file, $j, 1)));\r
+ }\r
+ printf(OUTPUT "0,\n");\r
+ \r
+ \r
+ $i = 0; \r
+ while(read(FILE, $data, 1)) {\r
+ if($i == 0) {\r
+ print(OUTPUT "\t");\r
+ }\r
+ printf(OUTPUT "%#02x, ", unpack("C", $data));\r
+ $i++;\r
+ if($i == 10) {\r
+ print(OUTPUT "\n");\r
+ $i = 0;\r
+ }\r
+ }\r
+ print(OUTPUT "};\n\n");\r
+ close(FILE);\r
+ push(@fvars, $fvar);\r
+ push(@files, $file);\r
+}\r
+\r
+for($i = 0; $i < @fvars; $i++) {\r
+ $file = $files[$i];\r
+ $fvar = $fvars[$i];\r
+\r
+ if($i == 0) {\r
+ $prevfile = "NULL";\r
+ } else {\r
+ $prevfile = "file" . $fvars[$i - 1];\r
+ }\r
+ print(OUTPUT "const struct fsdata_file file".$fvar."[] = {{$prevfile, data$fvar, ");\r
+ print(OUTPUT "data$fvar + ". (length($file) + 1) .", ");\r
+ print(OUTPUT "sizeof(data$fvar) - ". (length($file) + 1) ."}};\n\n");\r
+}\r
+\r
+print(OUTPUT "#define FS_ROOT file$fvars[$i - 1]\n\n");\r
+print(OUTPUT "#define FS_NUMFILES $i");\r
--- /dev/null
+/**\r
+ * \addtogroup exampleapps\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * Memory block allocation routines.\r
+ * \author Adam Dunkels <adam@sics.se>\r
+ *\r
+ * The memory block allocation routines provide a simple yet powerful\r
+ * set of functions for managing a set of memory blocks of fixed\r
+ * size. A set of memory blocks is statically declared with the\r
+ * MEMB() macro. Memory blocks are allocated from the declared\r
+ * memory by the memb_alloc() function, and are deallocated with the\r
+ * memb_free() function.\r
+ *\r
+ * \note Because of namespace clashes only one MEMB() can be\r
+ * declared per C module, and the name scope of a MEMB() memory\r
+ * block is local to each C module.\r
+ *\r
+ * The following example shows how to declare and use a memory block\r
+ * called "cmem" which has 8 chunks of memory with each memory chunk\r
+ * being 20 bytes large.\r
+ *\r
+ \code\r
+ MEMB(cmem, 20, 8);\r
+\r
+ int main(int argc, char *argv[]) {\r
+ char *ptr;\r
+ \r
+ memb_init(&cmem);\r
+\r
+ ptr = memb_alloc(&cmem);\r
+\r
+ if(ptr != NULL) {\r
+ do_something(ptr);\r
+ } else {\r
+ printf("Could not allocate memory.\n");\r
+ }\r
+\r
+ if(memb_free(ptr) == 0) {\r
+ printf("Deallocation succeeded.\n");\r
+ }\r
+ }\r
+ \endcode\r
+ * \r
+ */\r
+\r
+#include <string.h>\r
+\r
+#include "memb.h"\r
+\r
+/*------------------------------------------------------------------------------*/\r
+/**\r
+ * Initialize a memory block that was declared with MEMB().\r
+ *\r
+ * \param m A memory block previosly declared with MEMB().\r
+ */\r
+/*------------------------------------------------------------------------------*/\r
+void\r
+memb_init(struct memb_blocks *m)\r
+{\r
+ memset(m->mem, (m->size + 1) * m->num, 0);\r
+}\r
+/*------------------------------------------------------------------------------*/\r
+/**\r
+ * Allocate a memory block from a block of memory declared with MEMB().\r
+ *\r
+ * \param m A memory block previosly declared with MEMB().\r
+ */\r
+/*------------------------------------------------------------------------------*/\r
+char *\r
+memb_alloc(struct memb_blocks *m)\r
+{\r
+ int i;\r
+ char *ptr;\r
+\r
+ ptr = m->mem;\r
+ for(i = 0; i < m->num; ++i) {\r
+ if(*ptr == 0) {\r
+ /* If this block was unused, we increase the reference count to\r
+ indicate that it now is used and return a pointer to the\r
+ first byte following the reference counter. */\r
+ ++*ptr;\r
+ return ptr + 1;\r
+ }\r
+ ptr += m->size + 1;\r
+ }\r
+\r
+ /* No free block was found, so we return NULL to indicate failure to\r
+ allocate block. */\r
+ return NULL;\r
+}\r
+/*------------------------------------------------------------------------------*/\r
+/**\r
+ * Deallocate a memory block from a memory block previously declared\r
+ * with MEMB().\r
+ *\r
+ * \param m m A memory block previosly declared with MEMB().\r
+ *\r
+ * \param ptr A pointer to the memory block that is to be deallocated.\r
+ *\r
+ * \return The new reference count for the memory block (should be 0\r
+ * if successfully deallocated) or -1 if the pointer "ptr" did not\r
+ * point to a legal memory block.\r
+ */\r
+/*------------------------------------------------------------------------------*/\r
+char\r
+memb_free(struct memb_blocks *m, char *ptr)\r
+{\r
+ int i;\r
+ char *ptr2;\r
+\r
+ /* Walk through the list of blocks and try to find the block to\r
+ which the pointer "ptr" points to. */\r
+ ptr2 = m->mem;\r
+ for(i = 0; i < m->num; ++i) {\r
+ \r
+ if(ptr2 == ptr - 1) {\r
+ /* We've found to block to which "ptr" points so we decrease the\r
+ reference count and return the new value of it. */ \r
+ return --*ptr2;\r
+ }\r
+ ptr2 += m->size + 1;\r
+ }\r
+ return -1;\r
+}\r
+/*------------------------------------------------------------------------------*/\r
+/**\r
+ * Increase the reference count for a memory chunk.\r
+ *\r
+ * \note No sanity checks are currently made.\r
+ *\r
+ * \param m m A memory block previosly declared with MEMB().\r
+ *\r
+ * \param ptr A pointer to the memory chunk for which the reference\r
+ * count should be increased.\r
+ *\r
+ * \return The new reference count.\r
+ */\r
+/*------------------------------------------------------------------------------*/\r
+char\r
+memb_ref(struct memb_blocks *m, char *ptr)\r
+{\r
+ return ++*(ptr - 1);\r
+}\r
+/*------------------------------------------------------------------------------*/\r
+\r
+\r
+\r
+\r
--- /dev/null
+/**\r
+ * \addtogroup exampleapps\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * Memory block allocation routines.\r
+ * \author Adam Dunkels <adam@sics.se>\r
+ *\r
+ */\r
+\r
+#ifndef __MEMB_H__\r
+#define __MEMB_H__\r
+\r
+/**\r
+ * Declare a memory block.\r
+ *\r
+ * \param name The name of the memory block (later used with\r
+ * memb_init(), memb_alloc() and memb_free()).\r
+ *\r
+ * \param size The size of each memory chunk, in bytes.\r
+ *\r
+ * \param num The total number of memory chunks in the block.\r
+ *\r
+ */\r
+#define MEMB(name, size, num) \\r
+ static char memb_mem[(size + 1) * num]; \\r
+ static struct memb_blocks name = {size, num, memb_mem}\r
+\r
+struct memb_blocks {\r
+ unsigned short size;\r
+ unsigned short num;\r
+ char *mem;\r
+};\r
+\r
+void memb_init(struct memb_blocks *m);\r
+char *memb_alloc(struct memb_blocks *m);\r
+char memb_ref(struct memb_blocks *m, char *ptr);\r
+char memb_free(struct memb_blocks *m, char *ptr);\r
+\r
+\r
+#endif /* __MEMB_H__ */\r
--- /dev/null
+/**\r
+ * \addtogroup uip\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \defgroup slip Serial Line IP (SLIP) protocol\r
+ * @{\r
+ *\r
+ * The SLIP protocol is a very simple way to transmit IP packets over\r
+ * a serial line. It does not provide any framing or error control,\r
+ * and is therefore not very widely used today.\r
+ *\r
+ * This SLIP implementation requires two functions for accessing the\r
+ * serial device: slipdev_char_poll() and slipdev_char_put(). These\r
+ * must be implemented specifically for the system on which the SLIP\r
+ * protocol is to be run.\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * SLIP protocol implementation\r
+ * \author Adam Dunkels <adam@dunkels.com>\r
+ */\r
+\r
+/*\r
+ * Copyright (c) 2001, Adam Dunkels.\r
+ * All rights reserved. \r
+ *\r
+ * Redistribution and use in source and binary forms, with or without \r
+ * modification, are permitted provided that the following conditions \r
+ * are met: \r
+ * 1. Redistributions of source code must retain the above copyright \r
+ * notice, this list of conditions and the following disclaimer. \r
+ * 2. Redistributions in binary form must reproduce the above copyright \r
+ * notice, this list of conditions and the following disclaimer in the \r
+ * documentation and/or other materials provided with the distribution. \r
+ * 3. The name of the author may not be used to endorse or promote\r
+ * products derived from this software without specific prior\r
+ * written permission. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * $Id: slipdev.c,v 1.1.2.3 2003/10/07 13:23:01 adam Exp $\r
+ *\r
+ */\r
+\r
+/*\r
+ * This is a generic implementation of the SLIP protocol over an RS232\r
+ * (serial) device. \r
+ *\r
+ * Huge thanks to Ullrich von Bassewitz <uz@cc65.org> of cc65 fame for\r
+ * and endless supply of bugfixes, insightsful comments and\r
+ * suggestions, and improvements to this code!\r
+ */\r
+\r
+#include "uip.h"\r
+\r
+#define SLIP_END 0300\r
+#define SLIP_ESC 0333\r
+#define SLIP_ESC_END 0334\r
+#define SLIP_ESC_ESC 0335\r
+\r
+static u8_t slip_buf[UIP_BUFSIZE];\r
+\r
+static u16_t len, tmplen;\r
+static u8_t lastc;\r
+\r
+/*-----------------------------------------------------------------------------------*/\r
+/**\r
+ * Send the packet in the uip_buf and uip_appdata buffers using the\r
+ * SLIP protocol.\r
+ *\r
+ * The first 40 bytes of the packet (the IP and TCP headers) are read\r
+ * from the uip_buf buffer, and the following bytes (the application\r
+ * data) are read from the uip_appdata buffer.\r
+ *\r
+ */\r
+/*-----------------------------------------------------------------------------------*/\r
+void\r
+slipdev_send(void)\r
+{\r
+ u16_t i;\r
+ u8_t *ptr;\r
+ u8_t c;\r
+\r
+ slipdev_char_put(SLIP_END);\r
+\r
+ ptr = uip_buf;\r
+ for(i = 0; i < uip_len; ++i) {\r
+ if(i == 40) {\r
+ ptr = (u8_t *)uip_appdata;\r
+ }\r
+ c = *ptr++;\r
+ switch(c) {\r
+ case SLIP_END:\r
+ slipdev_char_put(SLIP_ESC);\r
+ slipdev_char_put(SLIP_ESC_END);\r
+ break;\r
+ case SLIP_ESC:\r
+ slipdev_char_put(SLIP_ESC);\r
+ slipdev_char_put(SLIP_ESC_ESC);\r
+ break;\r
+ default:\r
+ slipdev_char_put(c);\r
+ break;\r
+ }\r
+ }\r
+ slipdev_char_put(SLIP_END);\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+/** \r
+ * Poll the SLIP device for an available packet.\r
+ *\r
+ * This function will poll the SLIP device to see if a packet is\r
+ * available. It uses a buffer in which all avaliable bytes from the\r
+ * RS232 interface are read into. When a full packet has been read\r
+ * into the buffer, the packet is copied into the uip_buf buffer and\r
+ * the length of the packet is returned.\r
+ *\r
+ * \return The length of the packet placed in the uip_buf buffer, or\r
+ * zero if no packet is available.\r
+ */\r
+/*-----------------------------------------------------------------------------------*/\r
+u16_t\r
+slipdev_poll(void)\r
+{\r
+ u8_t c;\r
+ \r
+ while(slipdev_char_poll(c)) {\r
+ switch(c) {\r
+ case SLIP_ESC:\r
+ lastc = c;\r
+ break;\r
+ \r
+ case SLIP_END:\r
+ lastc = c;\r
+ /* End marker found, we copy our input buffer to the uip_buf\r
+ buffer and return the size of the packet we copied. */\r
+ memcpy(uip_buf, slip_buf, len);\r
+ tmplen = len;\r
+ len = 0;\r
+ return tmplen;\r
+ \r
+ default: \r
+ if(lastc == SLIP_ESC) {\r
+ lastc = c;\r
+ /* Previous read byte was an escape byte, so this byte will be\r
+ interpreted differently from others. */\r
+ switch(c) {\r
+ case SLIP_ESC_END:\r
+ c = SLIP_END;\r
+ break;\r
+ case SLIP_ESC_ESC:\r
+ c = SLIP_ESC;\r
+ break;\r
+ }\r
+ } else {\r
+ lastc = c;\r
+ }\r
+ \r
+ slip_buf[len] = c;\r
+ ++len;\r
+ \r
+ if(len > UIP_BUFSIZE) {\r
+ len = 0;\r
+ }\r
+ \r
+ break;\r
+ }\r
+ }\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+/**\r
+ * Initialize the SLIP module.\r
+ *\r
+ * This function does not initialize the underlying RS232 device, but\r
+ * only the SLIP part.\r
+ */ \r
+/*-----------------------------------------------------------------------------------*/\r
+void\r
+slipdev_init(void)\r
+{\r
+ lastc = len = 0;\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+\r
+/** @} */\r
+/** @} */\r
--- /dev/null
+/**\r
+ * \addtogroup slip\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * SLIP header file.\r
+ * \author Adam Dunkels <adam@dunkels.com>\r
+ */\r
+\r
+/*\r
+ * Copyright (c) 2001, Adam Dunkels.\r
+ * All rights reserved. \r
+ *\r
+ * Redistribution and use in source and binary forms, with or without \r
+ * modification, are permitted provided that the following conditions \r
+ * are met: \r
+ * 1. Redistributions of source code must retain the above copyright \r
+ * notice, this list of conditions and the following disclaimer. \r
+ * 2. Redistributions in binary form must reproduce the above copyright \r
+ * notice, this list of conditions and the following disclaimer in the \r
+ * documentation and/or other materials provided with the distribution. \r
+ * 3. The name of the author may not be used to endorse or promote\r
+ * products derived from this software without specific prior\r
+ * written permission. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * $Id: slipdev.h,v 1.1.2.3 2003/10/06 22:42:51 adam Exp $\r
+ *\r
+ */\r
+\r
+#ifndef __SLIPDEV_H__\r
+#define __SLIPDEV_H__\r
+\r
+#include "uip.h"\r
+\r
+/**\r
+ * Put a character on the serial device.\r
+ *\r
+ * This function is used by the SLIP implementation to put a character\r
+ * on the serial device. It must be implemented specifically for the\r
+ * system on which the SLIP implementation is to be run.\r
+ *\r
+ * \param c The character to be put on the serial device.\r
+ */\r
+void slipdev_char_put(u8_t c);\r
+\r
+/**\r
+ * Poll the serial device for a character.\r
+ *\r
+ * This function is used by the SLIP implementation to poll the serial\r
+ * device for a character. It must be implemented specifically for the\r
+ * system on which the SLIP implementation is to be run.\r
+ *\r
+ * The function should return immediately regardless if a character is\r
+ * available or not. If a character is available it should be placed\r
+ * at the memory location pointed to by the pointer supplied by the\r
+ * arguement c.\r
+ *\r
+ * \param c A pointer to a byte that is filled in by the function with\r
+ * the received character, if available.\r
+ *\r
+ * \retval 0 If no character is available.\r
+ * \retval Non-zero If a character is available.\r
+ */\r
+u8_t slipdev_char_poll(u8_t *c);\r
+\r
+void slipdev_init(void);\r
+void slipdev_send(void);\r
+u16_t slipdev_poll(void);\r
+\r
+#endif /* __SLIPDEV_H__ */\r
+\r
+/** @} */\r
--- /dev/null
+/*\r
+ * Copyright (c) 2001, Swedish Institute of Computer Science.\r
+ * All rights reserved. \r
+ *\r
+ * Redistribution and use in source and binary forms, with or without \r
+ * modification, are permitted provided that the following conditions \r
+ * are met: \r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright \r
+ * notice, this list of conditions and the following disclaimer. \r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright \r
+ * notice, this list of conditions and the following disclaimer in the \r
+ * documentation and/or other materials provided with the distribution. \r
+ *\r
+ * 3. Neither the name of the Institute nor the names of its contributors \r
+ * may be used to endorse or promote products derived from this software \r
+ * without specific prior written permission. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND \r
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE \r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE \r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE \r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL \r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS \r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) \r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT \r
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY \r
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF \r
+ * SUCH DAMAGE. \r
+ *\r
+ * Author: Adam Dunkels <adam@sics.se>\r
+ *\r
+ * $Id: tapdev.c,v 1.7.2.1 2003/10/07 13:23:19 adam Exp $\r
+ */\r
+\r
+\r
+#include <fcntl.h>\r
+#include <stdlib.h>\r
+#include <stdio.h>\r
+#include <unistd.h>\r
+#include <string.h>\r
+#include <sys/ioctl.h>\r
+#include <sys/socket.h>\r
+#include <sys/types.h>\r
+#include <sys/time.h>\r
+#include <sys/uio.h>\r
+#include <sys/socket.h>\r
+\r
+#ifdef linux\r
+#include <sys/ioctl.h>\r
+#include <linux/if.h>\r
+#include <linux/if_tun.h>\r
+#define DEVTAP "/dev/net/tun"\r
+#else /* linux */\r
+#define DEVTAP "/dev/tap0"\r
+#endif /* linux */\r
+\r
+#include "uip.h"\r
+\r
+static int fd;\r
+\r
+static unsigned long lasttime;\r
+static struct timezone tz;\r
+\r
+/*-----------------------------------------------------------------------------------*/\r
+void\r
+tapdev_init(void)\r
+{\r
+ char buf[1024];\r
+ \r
+ fd = open(DEVTAP, O_RDWR);\r
+ if(fd == -1) {\r
+ perror("tapdev: tapdev_init: open");\r
+ exit(1);\r
+ }\r
+\r
+#ifdef linux\r
+ {\r
+ struct ifreq ifr;\r
+ memset(&ifr, 0, sizeof(ifr));\r
+ ifr.ifr_flags = IFF_TAP|IFF_NO_PI;\r
+ if (ioctl(fd, TUNSETIFF, (void *) &ifr) < 0) {\r
+ perror(buf);\r
+ exit(1);\r
+ }\r
+ }\r
+#endif /* Linux */\r
+\r
+ snprintf(buf, sizeof(buf), "ifconfig tap0 inet %d.%d.%d.%d",\r
+ UIP_DRIPADDR0, UIP_DRIPADDR1, UIP_DRIPADDR2, UIP_DRIPADDR3);\r
+ system(buf);\r
+\r
+ lasttime = 0;\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+unsigned int\r
+tapdev_read(void)\r
+{\r
+ fd_set fdset;\r
+ struct timeval tv, now;\r
+ int ret;\r
+ \r
+ if(lasttime >= 500000) {\r
+ lasttime = 0;\r
+ return 0;\r
+ }\r
+ \r
+ tv.tv_sec = 0;\r
+ tv.tv_usec = 500000 - lasttime;\r
+\r
+\r
+ FD_ZERO(&fdset);\r
+ FD_SET(fd, &fdset);\r
+\r
+ gettimeofday(&now, &tz); \r
+ ret = select(fd + 1, &fdset, NULL, NULL, &tv);\r
+ if(ret == 0) {\r
+ lasttime = 0; \r
+ return 0;\r
+ } \r
+ ret = read(fd, uip_buf, UIP_BUFSIZE); \r
+ if(ret == -1) {\r
+ perror("tap_dev: tapdev_read: read");\r
+ }\r
+ gettimeofday(&tv, &tz);\r
+ lasttime += (tv.tv_sec - now.tv_sec) * 1000000 + (tv.tv_usec - now.tv_usec);\r
+\r
+ return ret;\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+void\r
+tapdev_send(void)\r
+{\r
+ int ret;\r
+ struct iovec iov[2];\r
+ \r
+#ifdef linux\r
+ {\r
+ char tmpbuf[UIP_BUFSIZE];\r
+ int i;\r
+\r
+ for(i = 0; i < 40 + UIP_LLH_LEN; i++) {\r
+ tmpbuf[i] = uip_buf[i];\r
+ }\r
+ \r
+ for(; i < uip_len; i++) {\r
+ tmpbuf[i] = uip_appdata[i - 40 - UIP_LLH_LEN];\r
+ }\r
+ \r
+ ret = write(fd, tmpbuf, uip_len);\r
+ } \r
+#else \r
+\r
+ if(uip_len < 40 + UIP_LLH_LEN) {\r
+ ret = write(fd, uip_buf, uip_len + UIP_LLH_LEN);\r
+ } else {\r
+ iov[0].iov_base = uip_buf;\r
+ iov[0].iov_len = 40 + UIP_LLH_LEN;\r
+ iov[1].iov_base = (char *)uip_appdata;\r
+ iov[1].iov_len = uip_len - (40 + UIP_LLH_LEN); \r
+ \r
+ ret = writev(fd, iov, 2);\r
+ }\r
+#endif\r
+ if(ret == -1) {\r
+ perror("tap_dev: tapdev_send: writev");\r
+ exit(1);\r
+ }\r
+} \r
+/*-----------------------------------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * Copyright (c) 2001, Adam Dunkels.\r
+ * All rights reserved. \r
+ *\r
+ * Redistribution and use in source and binary forms, with or without \r
+ * modification, are permitted provided that the following conditions \r
+ * are met: \r
+ * 1. Redistributions of source code must retain the above copyright \r
+ * notice, this list of conditions and the following disclaimer. \r
+ * 2. Redistributions in binary form must reproduce the above copyright \r
+ * notice, this list of conditions and the following disclaimer in the \r
+ * documentation and/or other materials provided with the distribution. \r
+ * 3. The name of the author may not be used to endorse or promote\r
+ * products derived from this software without specific prior\r
+ * written permission. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * $Id: tapdev.h,v 1.1.2.1 2003/10/04 22:54:17 adam Exp $\r
+ *\r
+ */\r
+\r
+#ifndef __TAPDEV_H__\r
+#define __TAPDEV_H__\r
+\r
+void tapdev_init(void);\r
+unsigned int tapdev_read(void);\r
+void tapdev_send(void);\r
+\r
+#endif /* __TAPDEV_H__ */\r
--- /dev/null
+/**\r
+ * \addtogroup telnetd\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * An example telnet server shell\r
+ * \author Adam Dunkels <adam@dunkels.com>\r
+ */\r
+\r
+/*\r
+ * Copyright (c) 2003, Adam Dunkels.\r
+ * All rights reserved. \r
+ *\r
+ * Redistribution and use in source and binary forms, with or without \r
+ * modification, are permitted provided that the following conditions \r
+ * are met: \r
+ * 1. Redistributions of source code must retain the above copyright \r
+ * notice, this list of conditions and the following disclaimer. \r
+ * 2. Redistributions in binary form must reproduce the above copyright \r
+ * notice, this list of conditions and the following disclaimer in the \r
+ * documentation and/or other materials provided with the distribution. \r
+ * 3. The name of the author may not be used to endorse or promote\r
+ * products derived from this software without specific prior\r
+ * written permission. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \r
+ *\r
+ * This file is part of the Contiki desktop OS.\r
+ *\r
+ * $Id: telnetd-shell.c,v 1.1.2.1 2003/10/06 22:56:22 adam Exp $\r
+ *\r
+ */\r
+\r
+#include "uip.h"\r
+#include "telnetd.h"\r
+#include <string.h>\r
+\r
+struct ptentry {\r
+ char c;\r
+ void (* pfunc)(struct telnetd_state *s, char *str);\r
+};\r
+\r
+/*-----------------------------------------------------------------------------------*/\r
+static void\r
+parse(struct telnetd_state *s, register char *str, struct ptentry *t)\r
+{\r
+ register struct ptentry *p;\r
+ char *sstr;\r
+\r
+ sstr = str;\r
+ \r
+ /* Loop over the parse table entries in t in order to find one that\r
+ matches the first character in str. */\r
+ for(p = t; p->c != 0; ++p) {\r
+ if(*str == p->c) {\r
+ /* Skip rest of the characters up to the first space. */\r
+ while(*str != ' ') {\r
+ ++str;\r
+ }\r
+\r
+ /* Skip all spaces.*/\r
+ while(*str == ' ') {\r
+ ++str;\r
+ }\r
+\r
+ /* Call parse table entry function and return. */\r
+ p->pfunc(s, str);\r
+ return;\r
+ }\r
+ }\r
+\r
+ /* Did not find matching entry in parse table. We just call the\r
+ default handler supplied by the caller and return. */\r
+ p->pfunc(s, str);\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+static void\r
+exitt(struct telnetd_state *s, char *str)\r
+{\r
+ telnetd_close(s);\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+static void\r
+inttostr(register char *str, unsigned int i)\r
+{\r
+ str[0] = '0' + i / 100;\r
+ if(str[0] == '0') {\r
+ str[0] = ' ';\r
+ }\r
+ str[1] = '0' + (i / 10) % 10;\r
+ if(str[1] == '0') {\r
+ str[1] = ' ';\r
+ }\r
+ str[2] = '0' + i % 10;\r
+ str[3] = ' ';\r
+ str[4] = 0;\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+static void\r
+stats(struct telnetd_state *s, char *strr)\r
+{\r
+ char str[10];\r
+\r
+ inttostr(str, uip_stat.ip.recv);\r
+ telnetd_output(s, "IP packets received ", str);\r
+ inttostr(str, uip_stat.ip.sent);\r
+ telnetd_output(s, "IP packets sent ", str);\r
+ inttostr(str, uip_stat.ip.drop);\r
+ telnetd_output(s, "IP packets dropped ", str);\r
+\r
+ inttostr(str, uip_stat.icmp.recv);\r
+ telnetd_output(s, "ICMP packets received ", str);\r
+ inttostr(str, uip_stat.icmp.sent);\r
+ telnetd_output(s, "ICMP packets sent ", str);\r
+ inttostr(str, uip_stat.icmp.drop);\r
+ telnetd_output(s, "ICMP packets dropped ", str);\r
+\r
+ inttostr(str, uip_stat.tcp.recv);\r
+ telnetd_output(s, "TCP packets received ", str);\r
+ inttostr(str, uip_stat.tcp.sent);\r
+ telnetd_output(s, "TCP packets sent ", str);\r
+ inttostr(str, uip_stat.tcp.drop);\r
+ telnetd_output(s, "TCP packets dropped ", str);\r
+ inttostr(str, uip_stat.tcp.rexmit);\r
+ telnetd_output(s, "TCP packets retransmitted ", str);\r
+ inttostr(str, uip_stat.tcp.synrst);\r
+ telnetd_output(s, "TCP connection attempts ", str);\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+static void\r
+help(struct telnetd_state *s, char *str)\r
+{\r
+ telnetd_output(s, "Available commands:", "");\r
+ telnetd_output(s, "stats - show uIP statistics", "");\r
+ telnetd_output(s, "exit - exit shell", ""); \r
+ telnetd_output(s, "? - show this help", ""); \r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+static void\r
+none(struct telnetd_state *s, char *str)\r
+{\r
+ if(strlen(str) > 0) {\r
+ telnetd_output(s, "Unknown command", "");\r
+ }\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+static struct ptentry configparsetab[] =\r
+ {{'s', stats},\r
+ {'e', exitt},\r
+ {'?', help},\r
+\r
+ /* Default action */\r
+ {0, none}};\r
+/*-----------------------------------------------------------------------------------*/\r
+void\r
+telnetd_connected(struct telnetd_state *s)\r
+{\r
+ telnetd_output(s, "uIP command shell", "");\r
+ telnetd_output(s, "Type '?' for help", ""); \r
+ telnetd_prompt(s, "uIP-0.9> "); \r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+void\r
+telnetd_input(struct telnetd_state *s, char *cmd)\r
+{\r
+ parse(s, cmd, configparsetab);\r
+ telnetd_prompt(s, "uIP-0.9> "); \r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
--- /dev/null
+/**\r
+ * \addtogroup exampleapps\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \defgroup telnetd Telnet server\r
+ * @{\r
+ *\r
+ * The uIP telnet server provides a command based interface to uIP. It\r
+ * allows using the "telnet" application to access uIP, and implements\r
+ * the required telnet option negotiation.\r
+ *\r
+ * The code is structured in a way which makes it possible to add\r
+ * commands without having to rewrite the main telnet code. The main\r
+ * telnet code calls two callback functions, telnetd_connected() and\r
+ * telnetd_input(), when a telnet connection has been established and\r
+ * when a line of text arrives on a telnet connection. These two\r
+ * functions can be implemented in a way which suits the particular\r
+ * application or environment in which the uIP system is intended to\r
+ * be run.\r
+ *\r
+ * The uIP distribution contains an example telnet shell\r
+ * implementation that provides a basic set of commands.\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * Implementation of the Telnet server.\r
+ * \author Adam Dunkels <adam@dunkels.com>\r
+ */\r
+\r
+/*\r
+ * Copyright (c) 2003, Adam Dunkels.\r
+ * All rights reserved. \r
+ *\r
+ * Redistribution and use in source and binary forms, with or without \r
+ * modification, are permitted provided that the following conditions \r
+ * are met: \r
+ * 1. Redistributions of source code must retain the above copyright \r
+ * notice, this list of conditions and the following disclaimer. \r
+ * 2. Redistributions in binary form must reproduce the above copyright \r
+ * notice, this list of conditions and the following disclaimer in the \r
+ * documentation and/or other materials provided with the distribution. \r
+ * 3. The name of the author may not be used to endorse or promote\r
+ * products derived from this software without specific prior\r
+ * written permission. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * $Id: telnetd.c,v 1.1.2.2 2003/10/07 13:47:50 adam Exp $\r
+ *\r
+ */\r
+\r
+#include "uip.h"\r
+#include "memb.h"\r
+#include "telnetd.h"\r
+#include <string.h>\r
+\r
+#define ISO_nl 0x0a\r
+#define ISO_cr 0x0d\r
+\r
+MEMB(linemem, TELNETD_LINELEN, TELNETD_NUMLINES);\r
+\r
+static u8_t i;\r
+\r
+#define STATE_NORMAL 0\r
+#define STATE_IAC 1\r
+#define STATE_WILL 2\r
+#define STATE_WONT 3\r
+#define STATE_DO 4 \r
+#define STATE_DONT 5\r
+#define STATE_CLOSE 6\r
+\r
+#define TELNET_IAC 255\r
+#define TELNET_WILL 251\r
+#define TELNET_WONT 252\r
+#define TELNET_DO 253\r
+#define TELNET_DONT 254\r
+/*-----------------------------------------------------------------------------------*/\r
+static char *\r
+alloc_line(void)\r
+{ \r
+ return memb_alloc(&linemem);\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+static void\r
+dealloc_line(char *line)\r
+{\r
+ memb_free(&linemem, line);\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+static void\r
+sendline(struct telnetd_state *s, char *line)\r
+{\r
+ static unsigned int i;\r
+ for(i = 0; i < TELNETD_NUMLINES; ++i) {\r
+ if(s->lines[i] == NULL) {\r
+ s->lines[i] = line;\r
+ break;\r
+ }\r
+ }\r
+ if(i == TELNETD_NUMLINES) {\r
+ dealloc_line(line);\r
+ }\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+/**\r
+ * Close a telnet session.\r
+ *\r
+ * This function can be called from a telnet command in order to close\r
+ * the connection.\r
+ *\r
+ * \param s The connection which is to be closed.\r
+ *\r
+ */\r
+/*-----------------------------------------------------------------------------------*/\r
+void\r
+telnetd_close(struct telnetd_state *s)\r
+{\r
+ s->state = STATE_CLOSE;\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+/**\r
+ * Print a prompt on a telnet connection.\r
+ *\r
+ * This function can be called by the telnet command shell in order to\r
+ * print out a command prompt.\r
+ *\r
+ * \param s A telnet connection.\r
+ *\r
+ * \param str The command prompt.\r
+ *\r
+ */\r
+/*-----------------------------------------------------------------------------------*/\r
+void\r
+telnetd_prompt(struct telnetd_state *s, char *str)\r
+{\r
+ char *line;\r
+ line = alloc_line();\r
+ if(line != NULL) {\r
+ strncpy(line, str, TELNETD_LINELEN);\r
+ sendline(s, line);\r
+ } \r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+/**\r
+ * Print out a string on a telnet connection.\r
+ *\r
+ * This function can be called from a telnet command parser in order\r
+ * to print out a string of text on the connection. The two strings\r
+ * given as arguments to the function will be concatenated, a carrige\r
+ * return and a new line character will be added, and the line is\r
+ * sent.\r
+ *\r
+ * \param s The telnet connection.\r
+ *\r
+ * \param str1 The first string.\r
+ *\r
+ * \param str2 The second string.\r
+ *\r
+ */\r
+/*-----------------------------------------------------------------------------------*/\r
+void\r
+telnetd_output(struct telnetd_state *s, char *str1, char *str2)\r
+{\r
+ static unsigned len;\r
+ char *line;\r
+ \r
+ line = alloc_line();\r
+ if(line != NULL) {\r
+ len = strlen(str1);\r
+ strncpy(line, str1, TELNETD_LINELEN);\r
+ if(len < TELNETD_LINELEN) {\r
+ strncpy(line + len, str2, TELNETD_LINELEN - len);\r
+ }\r
+ len = strlen(line);\r
+ if(len < TELNETD_LINELEN - 2) {\r
+ line[len] = ISO_cr;\r
+ line[len+1] = ISO_nl;\r
+ line[len+2] = 0;\r
+ }\r
+ sendline(s, line);\r
+ }\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+/**\r
+ * Initialize the telnet server.\r
+ *\r
+ * This function will perform the necessary initializations and start\r
+ * listening on TCP port 23.\r
+ */\r
+/*-----------------------------------------------------------------------------------*/\r
+void\r
+telnetd_init(void)\r
+{\r
+ memb_init(&linemem);\r
+ uip_listen(HTONS(23));\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+static void\r
+acked(struct telnetd_state *s) \r
+{\r
+ dealloc_line(s->lines[0]);\r
+ for(i = 1; i < TELNETD_NUMLINES; ++i) {\r
+ s->lines[i - 1] = s->lines[i];\r
+ }\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+static void\r
+senddata(struct telnetd_state *s) \r
+{\r
+ if(s->lines[0] != NULL) {\r
+ uip_send(s->lines[0], strlen(s->lines[0]));\r
+ }\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+static void\r
+getchar(struct telnetd_state *s, u8_t c)\r
+{\r
+ if(c == ISO_cr) {\r
+ return;\r
+ }\r
+ \r
+ s->buf[(int)s->bufptr] = c; \r
+ if(s->buf[(int)s->bufptr] == ISO_nl ||\r
+ s->bufptr == sizeof(s->buf) - 1) { \r
+ if(s->bufptr > 0) {\r
+ s->buf[(int)s->bufptr] = 0;\r
+ }\r
+ telnetd_input(s, s->buf);\r
+ s->bufptr = 0;\r
+ } else {\r
+ ++s->bufptr;\r
+ }\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+static void\r
+sendopt(struct telnetd_state *s, u8_t option, u8_t value)\r
+{\r
+ char *line;\r
+ line = alloc_line();\r
+ if(line != NULL) {\r
+ line[0] = TELNET_IAC;\r
+ line[1] = option;\r
+ line[2] = value;\r
+ line[3] = 0;\r
+ sendline(s, line);\r
+ } \r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+static void\r
+newdata(struct telnetd_state *s)\r
+{\r
+ u16_t len;\r
+ u8_t c;\r
+ \r
+ \r
+ len = uip_datalen();\r
+ \r
+ while(len > 0 && s->bufptr < sizeof(s->buf)) {\r
+ c = *uip_appdata;\r
+ ++uip_appdata;\r
+ --len;\r
+ switch(s->state) {\r
+ case STATE_IAC:\r
+ if(c == TELNET_IAC) {\r
+ getchar(s, c);\r
+ s->state = STATE_NORMAL;\r
+ } else {\r
+ switch(c) {\r
+ case TELNET_WILL:\r
+ s->state = STATE_WILL;\r
+ break;\r
+ case TELNET_WONT:\r
+ s->state = STATE_WONT;\r
+ break;\r
+ case TELNET_DO:\r
+ s->state = STATE_DO;\r
+ break;\r
+ case TELNET_DONT:\r
+ s->state = STATE_DONT;\r
+ break;\r
+ default:\r
+ s->state = STATE_NORMAL;\r
+ break;\r
+ }\r
+ }\r
+ break;\r
+ case STATE_WILL:\r
+ /* Reply with a DONT */\r
+ sendopt(s, TELNET_DONT, c);\r
+ s->state = STATE_NORMAL;\r
+ break;\r
+ \r
+ case STATE_WONT:\r
+ /* Reply with a DONT */\r
+ sendopt(s, TELNET_DONT, c);\r
+ s->state = STATE_NORMAL;\r
+ break;\r
+ case STATE_DO:\r
+ /* Reply with a WONT */\r
+ sendopt(s, TELNET_WONT, c);\r
+ s->state = STATE_NORMAL;\r
+ break;\r
+ case STATE_DONT:\r
+ /* Reply with a WONT */\r
+ sendopt(s, TELNET_WONT, c);\r
+ s->state = STATE_NORMAL;\r
+ break;\r
+ case STATE_NORMAL:\r
+ if(c == TELNET_IAC) {\r
+ s->state = STATE_IAC;\r
+ } else {\r
+ getchar(s, c);\r
+ } \r
+ break;\r
+ } \r
+\r
+ \r
+ } \r
+ \r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+void\r
+telnetd_app(void)\r
+{\r
+ struct telnetd_state *s;\r
+\r
+ s = (struct telnetd_state *)uip_conn->appstate;\r
+ \r
+ if(uip_connected()) {\r
+\r
+ for(i = 0; i < TELNETD_NUMLINES; ++i) {\r
+ s->lines[i] = NULL;\r
+ }\r
+ s->bufptr = 0;\r
+ s->state = STATE_NORMAL;\r
+\r
+ telnetd_connected(s);\r
+ senddata(s);\r
+ return;\r
+ }\r
+\r
+ if(s->state == STATE_CLOSE) {\r
+ s->state = STATE_NORMAL;\r
+ uip_close();\r
+ return;\r
+ }\r
+ \r
+ if(uip_closed()) {\r
+ telnetd_output(s, "Connection closed", "");\r
+ }\r
+\r
+ \r
+ if(uip_aborted()) {\r
+ telnetd_output(s, "Connection reset", "");\r
+ }\r
+ \r
+ if(uip_timedout()) {\r
+ telnetd_output(s, "Connection timed out", "");\r
+ }\r
+ \r
+ if(uip_acked()) {\r
+ acked(s);\r
+ }\r
+ \r
+ if(uip_newdata()) {\r
+ newdata(s);\r
+ }\r
+ \r
+ if(uip_rexmit() ||\r
+ uip_newdata() ||\r
+ uip_acked()) {\r
+ senddata(s);\r
+ } else if(uip_poll()) { \r
+ senddata(s);\r
+ }\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
--- /dev/null
+/**\r
+ * \addtogroup telnetd\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * Header file for the telnet server.\r
+ * \author Adam Dunkels <adam@dunkels.com>\r
+ */\r
+\r
+/*\r
+ * Copyright (c) 2002, Adam Dunkels.\r
+ * All rights reserved. \r
+ *\r
+ * Redistribution and use in source and binary forms, with or without \r
+ * modification, are permitted provided that the following conditions \r
+ * are met: \r
+ * 1. Redistributions of source code must retain the above copyright \r
+ * notice, this list of conditions and the following disclaimer. \r
+ * 2. Redistributions in binary form must reproduce the above copyright \r
+ * notice, this list of conditions and the following disclaimer in the \r
+ * documentation and/or other materials provided with the distribution. \r
+ * 3. The name of the author may not be used to endorse or promote\r
+ * products derived from this software without specific prior\r
+ * written permission. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * $Id: telnetd.h,v 1.1.2.2 2003/10/07 13:22:27 adam Exp $\r
+ *\r
+ */\r
+#ifndef __TELNETD_H__\r
+#define __TELNETD_H__\r
+\r
+#include "uip.h"\r
+\r
+/**\r
+ * The maximum length of a telnet line.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define TELNETD_LINELEN 36\r
+\r
+/**\r
+ * The number of output lines being buffered for all telnet\r
+ * connections.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define TELNETD_NUMLINES 2\r
+\r
+/**\r
+ * A telnet connection structure.\r
+ */\r
+struct telnetd_state {\r
+ char *lines[TELNETD_NUMLINES];\r
+ char buf[TELNETD_LINELEN];\r
+ char bufptr;\r
+ u8_t state;\r
+};\r
+\r
+\r
+/**\r
+ * Callback function that is called when a telnet connection has been\r
+ * established.\r
+ *\r
+ * \param s The telnet connection. \r
+ */\r
+void telnetd_connected(struct telnetd_state *s);\r
+\r
+/**\r
+ * Callback function that is called when a line of text has arrived on\r
+ * a telnet connection.\r
+ *\r
+ * \param s The telnet connection.\r
+ *\r
+ * \param cmd The line of text.\r
+ */\r
+void telnetd_input(struct telnetd_state *s, char *cmd);\r
+\r
+\r
+void telnetd_close(struct telnetd_state *s);\r
+void telnetd_output(struct telnetd_state *s, char *s1, char *s2);\r
+void telnetd_prompt(struct telnetd_state *s, char *str);\r
+\r
+void telnetd_app(void);\r
+\r
+#ifndef UIP_APPCALL\r
+#define UIP_APPCALL telnetd_app\r
+#endif\r
+\r
+#ifndef UIP_APPSTATE_SIZE\r
+#define UIP_APPSTATE_SIZE (sizeof(struct telnetd_state))\r
+#endif\r
+\r
+void telnetd_init(void);\r
+\r
+\r
+#endif /* __TELNET_H__ */\r
+\r
+/** @} */\r
--- /dev/null
+/*\r
+ * Copyright (c) 2001-2003, Adam Dunkels.\r
+ * All rights reserved. \r
+ *\r
+ * Redistribution and use in source and binary forms, with or without \r
+ * modification, are permitted provided that the following conditions \r
+ * are met: \r
+ * 1. Redistributions of source code must retain the above copyright \r
+ * notice, this list of conditions and the following disclaimer. \r
+ * 2. Redistributions in binary form must reproduce the above copyright \r
+ * notice, this list of conditions and the following disclaimer in the \r
+ * documentation and/or other materials provided with the distribution. \r
+ * 3. The name of the author may not be used to endorse or promote\r
+ * products derived from this software without specific prior\r
+ * written permission. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * $Id: main.c,v 1.10.2.4 2003/10/21 21:27:51 adam Exp $\r
+ *\r
+ */\r
+\r
+\r
+#include <stdlib.h> /* For system(). */\r
+#include <stdio.h> /* For printf(). */\r
+\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+#undef HTONS\r
+\r
+#include "cs8900a.h"\r
+#include "uip.h"\r
+#include "uip_arp.h"\r
+#include "tapdev.h"\r
+#include "httpd.h"\r
+\r
+static const struct uip_eth_addr ethaddr = {{0x00,0x00,0xe2,0x58,0xb6,0x6b}};\r
+\r
+#define BUF ((struct uip_eth_hdr *)&uip_buf[0])\r
+#define uipSHORT_DELAY ( ( portTickType ) 2 / portTICK_RATE_MS )\r
+\r
+#ifndef NULL\r
+#define NULL (void *)0\r
+#endif /* NULL */\r
+\r
+static volatile portTickType start, current;\r
+\r
+#define RT_CLOCK_SECOND ( configTICK_RATE_HZ / 2 )\r
+\r
+/*-----------------------------------------------------------------------------------*/\r
+/**\r
+ * \internal\r
+ * A real-time clock.\r
+ *\r
+ * This example main() function uses polling of a real-time clock in\r
+ * order to know when the periodic processing should be\r
+ * performed. This is implemented using this function - rt_ticks(). In\r
+ * this example unix implementation, it simply calls the unix function\r
+ * gettimeofday() which returns the current wall clock time.\r
+ *\r
+ * For a micro-controller, a simple way to implement this function is\r
+ * by having a counter that is incremented by a timer interrupt and\r
+ * read by this function.\r
+ * \r
+ * The macro RT_CLOCK_SECOND should be defined as the approximate\r
+ * number of ticks that are elapsed during one second. \r
+ */\r
+#define rt_ticks xTaskGetTickCount\r
+\r
+/*-----------------------------------------------------------------------------------*/\r
+void vuIP_TASK( void *pvParameters )\r
+{\r
+u8_t i, arptimer;\r
+u16_t addr[2];\r
+int z = 3;\r
+\r
+ /* Initialize the uIP TCP/IP stack. */\r
+ uip_init();\r
+ uip_arp_init();\r
+\r
+ /* Initialize the device driver. */ \r
+ cs8900a_init();\r
+\r
+ /* Initialize the HTTP server. */\r
+ httpd_init();\r
+\r
+ start = rt_ticks();\r
+ arptimer = 0;\r
+ \r
+ while(1) \r
+ {\r
+ /* Let the network device driver read an entire IP packet\r
+ into the uip_buf. If it returns > 0, there is a packet in the\r
+ uip_buf buffer. */\r
+ uip_len = cs8900a_poll();\r
+\r
+ if(uip_len > 0) \r
+ {\r
+ /* A packet is present in the packet buffer. We call the\r
+ appropriate ARP functions depending on what kind of packet we\r
+ have received. If the packet is an IP packet, we should call\r
+ uip_input() as well. */\r
+ if(BUF->type == htons(UIP_ETHTYPE_IP)) \r
+ {\r
+ uip_arp_ipin();\r
+ uip_input();\r
+ /* If the above function invocation resulted in data that\r
+ should be sent out on the network, the global variable\r
+ uip_len is set to a value > 0. */\r
+ if(uip_len > 0) \r
+ {\r
+ uip_arp_out();\r
+ cs8900a_send();\r
+ }\r
+ } \r
+ else if(BUF->type == htons(UIP_ETHTYPE_ARP)) \r
+ {\r
+ uip_arp_arpin();\r
+ /* If the above function invocation resulted in data that\r
+ should be sent out on the network, the global variable\r
+ uip_len is set to a value > 0. */ \r
+ if(uip_len > 0) \r
+ { \r
+ cs8900a_send();\r
+ }\r
+ }\r
+ } \r
+ else \r
+ {\r
+ /* The poll function returned 0, so no packet was\r
+ received. Instead we check if there is time that we do the\r
+ periodic processing. */\r
+ current = rt_ticks();\r
+\r
+ if((u16_t)(current - start) >= (u16_t)RT_CLOCK_SECOND / 2) \r
+ {\r
+ start = current;\r
+\r
+ for(i = 0; i < UIP_CONNS; i++) \r
+ {\r
+ uip_periodic(i);\r
+\r
+ /* If the above function invocation resulted in data that\r
+ should be sent out on the network, the global variable\r
+ uip_len is set to a value > 0. */\r
+ \r
+ if(uip_len > 0) \r
+ {\r
+ uip_arp_out();\r
+ cs8900a_send();\r
+ }\r
+ }\r
+\r
+ #if UIP_UDP\r
+ for(i = 0; i < UIP_UDP_CONNS; i++) \r
+ {\r
+ uip_udp_periodic(i);\r
+\r
+ /* If the above function invocation resulted in data that\r
+ should be sent out on the network, the global variable\r
+ uip_len is set to a value > 0. */\r
+\r
+ if(uip_len > 0) \r
+ {\r
+ uip_arp_out();\r
+ tapdev_send();\r
+ }\r
+ }\r
+ #endif /* UIP_UDP */\r
+\r
+ /* Call the ARP timer function every 10 seconds. */\r
+ if(++arptimer == 20) \r
+ { \r
+ uip_arp_timer();\r
+ arptimer = 0;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ vTaskDelay( uipSHORT_DELAY );\r
+ } }\r
+ }\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+\r
+\r
+\r
+\r
--- /dev/null
+/**\r
+ * \addtogroup uip\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * The uIP TCP/IP stack code.\r
+ * \author Adam Dunkels <adam@dunkels.com>\r
+ */\r
+\r
+/*\r
+ * Copyright (c) 2001-2003, Adam Dunkels.\r
+ * All rights reserved. \r
+ *\r
+ * Redistribution and use in source and binary forms, with or without \r
+ * modification, are permitted provided that the following conditions \r
+ * are met: \r
+ * 1. Redistributions of source code must retain the above copyright \r
+ * notice, this list of conditions and the following disclaimer. \r
+ * 2. Redistributions in binary form must reproduce the above copyright \r
+ * notice, this list of conditions and the following disclaimer in the \r
+ * documentation and/or other materials provided with the distribution. \r
+ * 3. The name of the author may not be used to endorse or promote\r
+ * products derived from this software without specific prior\r
+ * written permission. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * $Id: uip.c,v 1.62.2.10 2003/10/07 13:23:01 adam Exp $\r
+ *\r
+ */\r
+\r
+/*\r
+This is a small implementation of the IP and TCP protocols (as well as\r
+some basic ICMP stuff). The implementation couples the IP, TCP and the\r
+application layers very tightly. To keep the size of the compiled code\r
+down, this code also features heavy usage of the goto statement.\r
+\r
+The principle is that we have a small buffer, called the uip_buf, in\r
+which the device driver puts an incoming packet. The TCP/IP stack\r
+parses the headers in the packet, and calls upon the application. If\r
+the remote host has sent data to the application, this data is present\r
+in the uip_buf and the application read the data from there. It is up\r
+to the application to put this data into a byte stream if needed. The\r
+application will not be fed with data that is out of sequence.\r
+\r
+If the application whishes to send data to the peer, it should put its\r
+data into the uip_buf, 40 bytes from the start of the buffer. The\r
+TCP/IP stack will calculate the checksums, and fill in the necessary\r
+header fields and finally send the packet back to the peer.\r
+*/\r
+\r
+#include "uip.h"\r
+#include "uipopt.h"\r
+#include "uip_arch.h"\r
+\r
+/*-----------------------------------------------------------------------------------*/\r
+/* Variable definitions. */\r
+\r
+\r
+/* The IP address of this host. If it is defined to be fixed (by setting UIP_FIXEDADDR to 1 in uipopt.h), the address is set here. Otherwise, the address */\r
+#if UIP_FIXEDADDR > 0\r
+const u16_t uip_hostaddr[2] =\r
+ {HTONS((UIP_IPADDR0 << 8) | UIP_IPADDR1),\r
+ HTONS((UIP_IPADDR2 << 8) | UIP_IPADDR3)};\r
+const u16_t uip_arp_draddr[2] =\r
+ {HTONS((UIP_DRIPADDR0 << 8) | UIP_DRIPADDR1),\r
+ HTONS((UIP_DRIPADDR2 << 8) | UIP_DRIPADDR3)};\r
+const u16_t uip_arp_netmask[2] =\r
+ {HTONS((UIP_NETMASK0 << 8) | UIP_NETMASK1),\r
+ HTONS((UIP_NETMASK2 << 8) | UIP_NETMASK3)};\r
+#else\r
+u16_t uip_hostaddr[2]; \r
+u16_t uip_arp_draddr[2], uip_arp_netmask[2];\r
+#endif /* UIP_FIXEDADDR */\r
+\r
+u8_t uip_buf[UIP_BUFSIZE+2]; /* The packet buffer that contains\r
+ incoming packets. */\r
+volatile u8_t *uip_appdata; /* The uip_appdata pointer points to\r
+ application data. */\r
+volatile u8_t *uip_sappdata; /* The uip_appdata pointer points to the\r
+ application data which is to be sent. */\r
+#if UIP_URGDATA > 0\r
+volatile u8_t *uip_urgdata; /* The uip_urgdata pointer points to\r
+ urgent data (out-of-band data), if\r
+ present. */\r
+volatile u8_t uip_urglen, uip_surglen;\r
+#endif /* UIP_URGDATA > 0 */\r
+\r
+volatile u16_t uip_len, uip_slen;\r
+ /* The uip_len is either 8 or 16 bits,\r
+ depending on the maximum packet\r
+ size. */\r
+\r
+volatile u8_t uip_flags; /* The uip_flags variable is used for\r
+ communication between the TCP/IP stack\r
+ and the application program. */\r
+struct uip_conn *uip_conn; /* uip_conn always points to the current\r
+ connection. */\r
+\r
+struct uip_conn uip_conns[UIP_CONNS];\r
+ /* The uip_conns array holds all TCP\r
+ connections. */\r
+u16_t uip_listenports[UIP_LISTENPORTS];\r
+ /* The uip_listenports list all currently\r
+ listning ports. */\r
+#if UIP_UDP\r
+struct uip_udp_conn *uip_udp_conn;\r
+struct uip_udp_conn uip_udp_conns[UIP_UDP_CONNS];\r
+#endif /* UIP_UDP */\r
+\r
+\r
+static u16_t ipid; /* Ths ipid variable is an increasing\r
+ number that is used for the IP ID\r
+ field. */\r
+\r
+static u8_t iss[4]; /* The iss variable is used for the TCP\r
+ initial sequence number. */\r
+\r
+#if UIP_ACTIVE_OPEN\r
+static u16_t lastport; /* Keeps track of the last port used for\r
+ a new connection. */\r
+#endif /* UIP_ACTIVE_OPEN */\r
+\r
+/* Temporary variables. */\r
+volatile u8_t uip_acc32[4];\r
+static u8_t c, opt;\r
+static u16_t tmp16;\r
+\r
+/* Structures and definitions. */\r
+#define TCP_FIN 0x01\r
+#define TCP_SYN 0x02\r
+#define TCP_RST 0x04\r
+#define TCP_PSH 0x08\r
+#define TCP_ACK 0x10\r
+#define TCP_URG 0x20\r
+#define TCP_CTL 0x3f\r
+\r
+#define ICMP_ECHO_REPLY 0\r
+#define ICMP_ECHO 8 \r
+\r
+/* Macros. */\r
+#define BUF ((uip_tcpip_hdr *)&uip_buf[UIP_LLH_LEN])\r
+#define FBUF ((uip_tcpip_hdr *)&uip_reassbuf[0])\r
+#define ICMPBUF ((uip_icmpip_hdr *)&uip_buf[UIP_LLH_LEN])\r
+#define UDPBUF ((uip_udpip_hdr *)&uip_buf[UIP_LLH_LEN])\r
+\r
+#if UIP_STATISTICS == 1\r
+struct uip_stats uip_stat;\r
+#define UIP_STAT(s) s\r
+#else\r
+#define UIP_STAT(s)\r
+#endif /* UIP_STATISTICS == 1 */\r
+\r
+#if UIP_LOGGING == 1\r
+#include <stdio.h>\r
+void uip_log(char *msg);\r
+#define UIP_LOG(m) uip_log(m)\r
+#else\r
+#define UIP_LOG(m)\r
+#endif /* UIP_LOGGING == 1 */\r
+\r
+/*-----------------------------------------------------------------------------------*/\r
+void\r
+uip_init(void)\r
+{\r
+ for(c = 0; c < UIP_LISTENPORTS; ++c) {\r
+ uip_listenports[c] = 0;\r
+ }\r
+ for(c = 0; c < UIP_CONNS; ++c) {\r
+ uip_conns[c].tcpstateflags = CLOSED;\r
+ }\r
+#if UIP_ACTIVE_OPEN\r
+ lastport = 1024;\r
+#endif /* UIP_ACTIVE_OPEN */\r
+\r
+#if UIP_UDP\r
+ for(c = 0; c < UIP_UDP_CONNS; ++c) {\r
+ uip_udp_conns[c].lport = 0;\r
+ }\r
+#endif /* UIP_UDP */\r
+ \r
+\r
+ /* IPv4 initialization. */\r
+#if UIP_FIXEDADDR == 0\r
+ uip_hostaddr[0] = uip_hostaddr[1] = 0;\r
+#endif /* UIP_FIXEDADDR */\r
+\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+#if UIP_ACTIVE_OPEN\r
+struct uip_conn *\r
+uip_connect(u16_t *ripaddr, u16_t rport)\r
+{\r
+ register struct uip_conn *conn, *cconn;\r
+ \r
+ /* Find an unused local port. */\r
+ again:\r
+ ++lastport;\r
+\r
+ if(lastport >= 32000) {\r
+ lastport = 4096;\r
+ }\r
+\r
+ /* Check if this port is already in use, and if so try to find\r
+ another one. */\r
+ for(c = 0; c < UIP_CONNS; ++c) {\r
+ conn = &uip_conns[c];\r
+ if(conn->tcpstateflags != CLOSED &&\r
+ conn->lport == htons(lastport)) {\r
+ goto again;\r
+ }\r
+ }\r
+\r
+\r
+ conn = 0;\r
+ for(c = 0; c < UIP_CONNS; ++c) {\r
+ cconn = &uip_conns[c]; \r
+ if(cconn->tcpstateflags == CLOSED) {\r
+ conn = cconn;\r
+ break;\r
+ }\r
+ if(cconn->tcpstateflags == TIME_WAIT) {\r
+ if(conn == 0 ||\r
+ cconn->timer > uip_conn->timer) {\r
+ conn = cconn;\r
+ }\r
+ }\r
+ }\r
+\r
+ if(conn == 0) {\r
+ return 0;\r
+ }\r
+ \r
+ conn->tcpstateflags = SYN_SENT;\r
+\r
+ conn->snd_nxt[0] = iss[0];\r
+ conn->snd_nxt[1] = iss[1];\r
+ conn->snd_nxt[2] = iss[2];\r
+ conn->snd_nxt[3] = iss[3];\r
+\r
+ conn->initialmss = conn->mss = UIP_TCP_MSS;\r
+ \r
+ conn->len = 1; /* TCP length of the SYN is one. */\r
+ conn->nrtx = 0;\r
+ conn->timer = 1; /* Send the SYN next time around. */\r
+ conn->rto = UIP_RTO;\r
+ conn->sa = 0;\r
+ conn->sv = 16;\r
+ conn->lport = htons(lastport);\r
+ conn->rport = rport;\r
+ conn->ripaddr[0] = ripaddr[0];\r
+ conn->ripaddr[1] = ripaddr[1];\r
+ \r
+ return conn;\r
+}\r
+#endif /* UIP_ACTIVE_OPEN */\r
+/*-----------------------------------------------------------------------------------*/\r
+#if UIP_UDP\r
+struct uip_udp_conn *\r
+uip_udp_new(u16_t *ripaddr, u16_t rport)\r
+{\r
+ register struct uip_udp_conn *conn;\r
+ \r
+ /* Find an unused local port. */\r
+ again:\r
+ ++lastport;\r
+\r
+ if(lastport >= 32000) {\r
+ lastport = 4096;\r
+ }\r
+ \r
+ for(c = 0; c < UIP_UDP_CONNS; ++c) {\r
+ if(uip_udp_conns[c].lport == lastport) {\r
+ goto again;\r
+ }\r
+ }\r
+\r
+\r
+ conn = 0;\r
+ for(c = 0; c < UIP_UDP_CONNS; ++c) {\r
+ if(uip_udp_conns[c].lport == 0) {\r
+ conn = &uip_udp_conns[c]; \r
+ break;\r
+ }\r
+ }\r
+\r
+ if(conn == 0) {\r
+ return 0;\r
+ }\r
+ \r
+ conn->lport = HTONS(lastport);\r
+ conn->rport = HTONS(rport);\r
+ conn->ripaddr[0] = ripaddr[0];\r
+ conn->ripaddr[1] = ripaddr[1];\r
+ \r
+ return conn;\r
+}\r
+#endif /* UIP_UDP */\r
+/*-----------------------------------------------------------------------------------*/\r
+void\r
+uip_unlisten(u16_t port)\r
+{\r
+ for(c = 0; c < UIP_LISTENPORTS; ++c) {\r
+ if(uip_listenports[c] == port) {\r
+ uip_listenports[c] = 0;\r
+ return;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+void\r
+uip_listen(u16_t port)\r
+{\r
+ for(c = 0; c < UIP_LISTENPORTS; ++c) {\r
+ if(uip_listenports[c] == 0) {\r
+ uip_listenports[c] = port;\r
+ return;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+/* XXX: IP fragment reassembly: not well-tested. */\r
+\r
+#if UIP_REASSEMBLY\r
+#define UIP_REASS_BUFSIZE (UIP_BUFSIZE - UIP_LLH_LEN)\r
+static u8_t uip_reassbuf[UIP_REASS_BUFSIZE];\r
+static u8_t uip_reassbitmap[UIP_REASS_BUFSIZE / (8 * 8)];\r
+static const u8_t bitmap_bits[8] = {0xff, 0x7f, 0x3f, 0x1f,\r
+ 0x0f, 0x07, 0x03, 0x01};\r
+static u16_t uip_reasslen;\r
+static u8_t uip_reassflags;\r
+#define UIP_REASS_FLAG_LASTFRAG 0x01\r
+static u8_t uip_reasstmr;\r
+\r
+#define IP_HLEN 20\r
+#define IP_MF 0x20\r
+\r
+static u8_t\r
+uip_reass(void)\r
+{\r
+ u16_t offset, len;\r
+ u16_t i;\r
+\r
+ /* If ip_reasstmr is zero, no packet is present in the buffer, so we\r
+ write the IP header of the fragment into the reassembly\r
+ buffer. The timer is updated with the maximum age. */\r
+ if(uip_reasstmr == 0) {\r
+ memcpy(uip_reassbuf, &BUF->vhl, IP_HLEN);\r
+ uip_reasstmr = UIP_REASS_MAXAGE;\r
+ uip_reassflags = 0;\r
+ /* Clear the bitmap. */\r
+ memset(uip_reassbitmap, sizeof(uip_reassbitmap), 0);\r
+ }\r
+\r
+ /* Check if the incoming fragment matches the one currently present\r
+ in the reasembly buffer. If so, we proceed with copying the\r
+ fragment into the buffer. */\r
+ if(BUF->srcipaddr[0] == FBUF->srcipaddr[0] &&\r
+ BUF->srcipaddr[1] == FBUF->srcipaddr[1] &&\r
+ BUF->destipaddr[0] == FBUF->destipaddr[0] &&\r
+ BUF->destipaddr[1] == FBUF->destipaddr[1] &&\r
+ BUF->ipid[0] == FBUF->ipid[0] &&\r
+ BUF->ipid[1] == FBUF->ipid[1]) {\r
+\r
+ len = (BUF->len[0] << 8) + BUF->len[1] - (BUF->vhl & 0x0f) * 4;\r
+ offset = (((BUF->ipoffset[0] & 0x3f) << 8) + BUF->ipoffset[1]) * 8;\r
+\r
+ /* If the offset or the offset + fragment length overflows the\r
+ reassembly buffer, we discard the entire packet. */\r
+ if(offset > UIP_REASS_BUFSIZE ||\r
+ offset + len > UIP_REASS_BUFSIZE) {\r
+ uip_reasstmr = 0;\r
+ goto nullreturn;\r
+ }\r
+\r
+ /* Copy the fragment into the reassembly buffer, at the right\r
+ offset. */\r
+ memcpy(&uip_reassbuf[IP_HLEN + offset],\r
+ (char *)BUF + (int)((BUF->vhl & 0x0f) * 4),\r
+ len);\r
+ \r
+ /* Update the bitmap. */\r
+ if(offset / (8 * 8) == (offset + len) / (8 * 8)) {\r
+ /* If the two endpoints are in the same byte, we only update\r
+ that byte. */\r
+ \r
+ uip_reassbitmap[offset / (8 * 8)] |=\r
+ bitmap_bits[(offset / 8 ) & 7] &\r
+ ~bitmap_bits[((offset + len) / 8 ) & 7];\r
+ } else {\r
+ /* If the two endpoints are in different bytes, we update the\r
+ bytes in the endpoints and fill the stuff inbetween with\r
+ 0xff. */\r
+ uip_reassbitmap[offset / (8 * 8)] |=\r
+ bitmap_bits[(offset / 8 ) & 7];\r
+ for(i = 1 + offset / (8 * 8); i < (offset + len) / (8 * 8); ++i) {\r
+ uip_reassbitmap[i] = 0xff;\r
+ } \r
+ uip_reassbitmap[(offset + len) / (8 * 8)] |=\r
+ ~bitmap_bits[((offset + len) / 8 ) & 7];\r
+ }\r
+ \r
+ /* If this fragment has the More Fragments flag set to zero, we\r
+ know that this is the last fragment, so we can calculate the\r
+ size of the entire packet. We also set the\r
+ IP_REASS_FLAG_LASTFRAG flag to indicate that we have received\r
+ the final fragment. */\r
+\r
+ if((BUF->ipoffset[0] & IP_MF) == 0) {\r
+ uip_reassflags |= UIP_REASS_FLAG_LASTFRAG;\r
+ uip_reasslen = offset + len;\r
+ }\r
+ \r
+ /* Finally, we check if we have a full packet in the buffer. We do\r
+ this by checking if we have the last fragment and if all bits\r
+ in the bitmap are set. */\r
+ if(uip_reassflags & UIP_REASS_FLAG_LASTFRAG) {\r
+ /* Check all bytes up to and including all but the last byte in\r
+ the bitmap. */\r
+ for(i = 0; i < uip_reasslen / (8 * 8) - 1; ++i) {\r
+ if(uip_reassbitmap[i] != 0xff) {\r
+ goto nullreturn;\r
+ }\r
+ }\r
+ /* Check the last byte in the bitmap. It should contain just the\r
+ right amount of bits. */\r
+ if(uip_reassbitmap[uip_reasslen / (8 * 8)] !=\r
+ (u8_t)~bitmap_bits[uip_reasslen / 8 & 7]) {\r
+ goto nullreturn;\r
+ }\r
+\r
+ /* If we have come this far, we have a full packet in the\r
+ buffer, so we allocate a pbuf and copy the packet into it. We\r
+ also reset the timer. */\r
+ uip_reasstmr = 0;\r
+ memcpy(BUF, FBUF, uip_reasslen);\r
+\r
+ /* Pretend to be a "normal" (i.e., not fragmented) IP packet\r
+ from now on. */\r
+ BUF->ipoffset[0] = BUF->ipoffset[1] = 0;\r
+ BUF->len[0] = uip_reasslen >> 8;\r
+ BUF->len[1] = uip_reasslen & 0xff;\r
+ BUF->ipchksum = 0;\r
+ BUF->ipchksum = ~(uip_ipchksum());\r
+\r
+ return uip_reasslen;\r
+ }\r
+ }\r
+\r
+ nullreturn:\r
+ return 0;\r
+}\r
+#endif /* UIP_REASSEMBL */\r
+/*-----------------------------------------------------------------------------------*/\r
+static void\r
+uip_add_rcv_nxt(u16_t n)\r
+{\r
+ uip_add32(uip_conn->rcv_nxt, n);\r
+ uip_conn->rcv_nxt[0] = uip_acc32[0];\r
+ uip_conn->rcv_nxt[1] = uip_acc32[1];\r
+ uip_conn->rcv_nxt[2] = uip_acc32[2];\r
+ uip_conn->rcv_nxt[3] = uip_acc32[3];\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+void\r
+uip_process(u8_t flag)\r
+{\r
+ register struct uip_conn *uip_connr = uip_conn;\r
+ \r
+ uip_appdata = &uip_buf[40 + UIP_LLH_LEN];\r
+\r
+ \r
+ /* Check if we were invoked because of the perodic timer fireing. */\r
+ if(flag == UIP_TIMER) {\r
+#if UIP_REASSEMBLY\r
+ if(uip_reasstmr != 0) {\r
+ --uip_reasstmr;\r
+ }\r
+#endif /* UIP_REASSEMBLY */\r
+ /* Increase the initial sequence number. */\r
+ if(++iss[3] == 0) {\r
+ if(++iss[2] == 0) {\r
+ if(++iss[1] == 0) {\r
+ ++iss[0];\r
+ }\r
+ }\r
+ } \r
+ uip_len = 0;\r
+ if(uip_connr->tcpstateflags == TIME_WAIT ||\r
+ uip_connr->tcpstateflags == FIN_WAIT_2) {\r
+ ++(uip_connr->timer);\r
+ if(uip_connr->timer == UIP_TIME_WAIT_TIMEOUT) {\r
+ uip_connr->tcpstateflags = CLOSED;\r
+ }\r
+ } else if(uip_connr->tcpstateflags != CLOSED) {\r
+ /* If the connection has outstanding data, we increase the\r
+ connection's timer and see if it has reached the RTO value\r
+ in which case we retransmit. */\r
+ if(uip_outstanding(uip_connr)) {\r
+ if(uip_connr->timer-- == 0) {\r
+ if(uip_connr->nrtx == UIP_MAXRTX ||\r
+ ((uip_connr->tcpstateflags == SYN_SENT ||\r
+ uip_connr->tcpstateflags == SYN_RCVD) &&\r
+ uip_connr->nrtx == UIP_MAXSYNRTX)) {\r
+ uip_connr->tcpstateflags = CLOSED;\r
+\r
+ /* We call UIP_APPCALL() with uip_flags set to\r
+ UIP_TIMEDOUT to inform the application that the\r
+ connection has timed out. */\r
+ uip_flags = UIP_TIMEDOUT;\r
+ UIP_APPCALL();\r
+\r
+ /* We also send a reset packet to the remote host. */\r
+ BUF->flags = TCP_RST | TCP_ACK;\r
+ goto tcp_send_nodata;\r
+ }\r
+\r
+ /* Exponential backoff. */\r
+ uip_connr->timer = UIP_RTO << (uip_connr->nrtx > 4?\r
+ 4:\r
+ uip_connr->nrtx);\r
+ ++(uip_connr->nrtx);\r
+ \r
+ /* Ok, so we need to retransmit. We do this differently\r
+ depending on which state we are in. In ESTABLISHED, we\r
+ call upon the application so that it may prepare the\r
+ data for the retransmit. In SYN_RCVD, we resend the\r
+ SYNACK that we sent earlier and in LAST_ACK we have to\r
+ retransmit our FINACK. */\r
+ UIP_STAT(++uip_stat.tcp.rexmit);\r
+ switch(uip_connr->tcpstateflags & TS_MASK) {\r
+ case SYN_RCVD:\r
+ /* In the SYN_RCVD state, we should retransmit our\r
+ SYNACK. */\r
+ goto tcp_send_synack;\r
+ \r
+#if UIP_ACTIVE_OPEN\r
+ case SYN_SENT:\r
+ /* In the SYN_SENT state, we retransmit out SYN. */\r
+ BUF->flags = 0;\r
+ goto tcp_send_syn;\r
+#endif /* UIP_ACTIVE_OPEN */\r
+ \r
+ case ESTABLISHED:\r
+ /* In the ESTABLISHED state, we call upon the application\r
+ to do the actual retransmit after which we jump into\r
+ the code for sending out the packet (the apprexmit\r
+ label). */\r
+ uip_len = 0;\r
+ uip_slen = 0;\r
+ uip_flags = UIP_REXMIT;\r
+ UIP_APPCALL();\r
+ goto apprexmit;\r
+ \r
+ case FIN_WAIT_1:\r
+ case CLOSING:\r
+ case LAST_ACK:\r
+ /* In all these states we should retransmit a FINACK. */\r
+ goto tcp_send_finack;\r
+ \r
+ }\r
+ }\r
+ } else if((uip_connr->tcpstateflags & TS_MASK) == ESTABLISHED) {\r
+ /* If there was no need for a retransmission, we poll the\r
+ application for new data. */\r
+ uip_len = 0;\r
+ uip_slen = 0;\r
+ uip_flags = UIP_POLL;\r
+ UIP_APPCALL();\r
+ goto appsend;\r
+ }\r
+ }\r
+ goto drop;\r
+ }\r
+#if UIP_UDP \r
+ if(flag == UIP_UDP_TIMER) {\r
+ if(uip_udp_conn->lport != 0) {\r
+ uip_appdata = &uip_buf[UIP_LLH_LEN + 28];\r
+ uip_len = uip_slen = 0;\r
+ uip_flags = UIP_POLL;\r
+ UIP_UDP_APPCALL();\r
+ goto udp_send;\r
+ } else {\r
+ goto drop;\r
+ }\r
+ }\r
+#endif\r
+\r
+ /* This is where the input processing starts. */\r
+ UIP_STAT(++uip_stat.ip.recv);\r
+\r
+\r
+ /* Start of IPv4 input header processing code. */\r
+ \r
+ /* Check validity of the IP header. */ \r
+ if(BUF->vhl != 0x45) { /* IP version and header length. */\r
+ UIP_STAT(++uip_stat.ip.drop);\r
+ UIP_STAT(++uip_stat.ip.vhlerr);\r
+ UIP_LOG("ip: invalid version or header length.");\r
+ goto drop;\r
+ }\r
+ \r
+ /* Check the size of the packet. If the size reported to us in\r
+ uip_len doesn't match the size reported in the IP header, there\r
+ has been a transmission error and we drop the packet. */\r
+ \r
+ if(BUF->len[0] != (uip_len >> 8)) { /* IP length, high byte. */\r
+ uip_len = (uip_len & 0xff) | (BUF->len[0] << 8);\r
+ }\r
+ if(BUF->len[1] != (uip_len & 0xff)) { /* IP length, low byte. */\r
+ uip_len = (uip_len & 0xff00) | BUF->len[1];\r
+ }\r
+\r
+ /* Check the fragment flag. */\r
+ if((BUF->ipoffset[0] & 0x3f) != 0 ||\r
+ BUF->ipoffset[1] != 0) { \r
+#if UIP_REASSEMBLY\r
+ uip_len = uip_reass();\r
+ if(uip_len == 0) {\r
+ goto drop;\r
+ }\r
+#else\r
+ UIP_STAT(++uip_stat.ip.drop);\r
+ UIP_STAT(++uip_stat.ip.fragerr);\r
+ UIP_LOG("ip: fragment dropped."); \r
+ goto drop;\r
+#endif /* UIP_REASSEMBLY */\r
+ }\r
+\r
+ /* If we are configured to use ping IP address configuration and\r
+ hasn't been assigned an IP address yet, we accept all ICMP\r
+ packets. */\r
+#if UIP_PINGADDRCONF\r
+ if((uip_hostaddr[0] | uip_hostaddr[1]) == 0) {\r
+ if(BUF->proto == UIP_PROTO_ICMP) {\r
+ UIP_LOG("ip: possible ping config packet received.");\r
+ goto icmp_input;\r
+ } else {\r
+ UIP_LOG("ip: packet dropped since no address assigned.");\r
+ goto drop;\r
+ }\r
+ }\r
+#endif /* UIP_PINGADDRCONF */\r
+ \r
+ /* Check if the packet is destined for our IP address. */ \r
+ if(BUF->destipaddr[0] != uip_hostaddr[0]) {\r
+ UIP_STAT(++uip_stat.ip.drop);\r
+ UIP_LOG("ip: packet not for us."); \r
+ goto drop;\r
+ }\r
+ if(BUF->destipaddr[1] != uip_hostaddr[1]) {\r
+ UIP_STAT(++uip_stat.ip.drop);\r
+ UIP_LOG("ip: packet not for us."); \r
+ goto drop;\r
+ }\r
+\r
+#if 0\r
+ // IP checksum is wrong through Netgear DSL router\r
+ if (uip_ipchksum() != 0xffff) { /* Compute and check the IP header\r
+ checksum. */\r
+ UIP_STAT(++uip_stat.ip.drop);\r
+ UIP_STAT(++uip_stat.ip.chkerr);\r
+ UIP_LOG("ip: bad checksum."); \r
+ goto drop;\r
+ }\r
+#endif\r
+\r
+ if(BUF->proto == UIP_PROTO_TCP) /* Check for TCP packet. If so, jump\r
+ to the tcp_input label. */\r
+ goto tcp_input;\r
+\r
+#if UIP_UDP\r
+ if(BUF->proto == UIP_PROTO_UDP)\r
+ goto udp_input;\r
+#endif /* UIP_UDP */\r
+\r
+ if(BUF->proto != UIP_PROTO_ICMP) { /* We only allow ICMP packets from\r
+ here. */\r
+ UIP_STAT(++uip_stat.ip.drop);\r
+ UIP_STAT(++uip_stat.ip.protoerr);\r
+ UIP_LOG("ip: neither tcp nor icmp."); \r
+ goto drop;\r
+ }\r
+ \r
+ icmp_input:\r
+ UIP_STAT(++uip_stat.icmp.recv);\r
+ \r
+ /* ICMP echo (i.e., ping) processing. This is simple, we only change\r
+ the ICMP type from ECHO to ECHO_REPLY and adjust the ICMP\r
+ checksum before we return the packet. */\r
+ if(ICMPBUF->type != ICMP_ECHO) {\r
+ UIP_STAT(++uip_stat.icmp.drop);\r
+ UIP_STAT(++uip_stat.icmp.typeerr);\r
+ UIP_LOG("icmp: not icmp echo.");\r
+ goto drop;\r
+ }\r
+\r
+ /* If we are configured to use ping IP address assignment, we use\r
+ the destination IP address of this ping packet and assign it to\r
+ ourself. */\r
+#if UIP_PINGADDRCONF\r
+ if((uip_hostaddr[0] | uip_hostaddr[1]) == 0) {\r
+ uip_hostaddr[0] = BUF->destipaddr[0];\r
+ uip_hostaddr[1] = BUF->destipaddr[1];\r
+ }\r
+#endif /* UIP_PINGADDRCONF */ \r
+ \r
+ ICMPBUF->type = ICMP_ECHO_REPLY;\r
+ \r
+ if(ICMPBUF->icmpchksum >= HTONS(0xffff - (ICMP_ECHO << 8))) {\r
+ ICMPBUF->icmpchksum += HTONS(ICMP_ECHO << 8) + 1;\r
+ } else {\r
+ ICMPBUF->icmpchksum += HTONS(ICMP_ECHO << 8);\r
+ }\r
+ \r
+ /* Swap IP addresses. */\r
+ tmp16 = BUF->destipaddr[0];\r
+ BUF->destipaddr[0] = BUF->srcipaddr[0];\r
+ BUF->srcipaddr[0] = tmp16;\r
+ tmp16 = BUF->destipaddr[1];\r
+ BUF->destipaddr[1] = BUF->srcipaddr[1];\r
+ BUF->srcipaddr[1] = tmp16;\r
+\r
+ UIP_STAT(++uip_stat.icmp.sent);\r
+ goto send;\r
+\r
+ /* End of IPv4 input header processing code. */\r
+ \r
+\r
+#if UIP_UDP\r
+ /* UDP input processing. */\r
+ udp_input:\r
+ /* UDP processing is really just a hack. We don't do anything to the\r
+ UDP/IP headers, but let the UDP application do all the hard\r
+ work. If the application sets uip_slen, it has a packet to\r
+ send. */\r
+#if UIP_UDP_CHECKSUMS\r
+ if(uip_udpchksum() != 0xffff) { \r
+ UIP_STAT(++uip_stat.udp.drop);\r
+ UIP_STAT(++uip_stat.udp.chkerr);\r
+ UIP_LOG("udp: bad checksum."); \r
+ goto drop;\r
+ } \r
+#endif /* UIP_UDP_CHECKSUMS */\r
+\r
+ /* Demultiplex this UDP packet between the UDP "connections". */\r
+ for(uip_udp_conn = &uip_udp_conns[0];\r
+ uip_udp_conn < &uip_udp_conns[UIP_UDP_CONNS];\r
+ ++uip_udp_conn) {\r
+ if(uip_udp_conn->lport != 0 &&\r
+ UDPBUF->destport == uip_udp_conn->lport &&\r
+ (uip_udp_conn->rport == 0 ||\r
+ UDPBUF->srcport == uip_udp_conn->rport) &&\r
+ BUF->srcipaddr[0] == uip_udp_conn->ripaddr[0] &&\r
+ BUF->srcipaddr[1] == uip_udp_conn->ripaddr[1]) {\r
+ goto udp_found; \r
+ }\r
+ }\r
+ goto drop;\r
+ \r
+ udp_found:\r
+ uip_len = uip_len - 28;\r
+ uip_appdata = &uip_buf[UIP_LLH_LEN + 28];\r
+ uip_flags = UIP_NEWDATA;\r
+ uip_slen = 0;\r
+ UIP_UDP_APPCALL();\r
+ udp_send:\r
+ if(uip_slen == 0) {\r
+ goto drop; \r
+ }\r
+ uip_len = uip_slen + 28;\r
+\r
+ BUF->len[0] = (uip_len >> 8);\r
+ BUF->len[1] = (uip_len & 0xff);\r
+ \r
+ BUF->proto = UIP_PROTO_UDP;\r
+\r
+ UDPBUF->udplen = HTONS(uip_slen + 8);\r
+ UDPBUF->udpchksum = 0;\r
+#if UIP_UDP_CHECKSUMS \r
+ /* Calculate UDP checksum. */\r
+ UDPBUF->udpchksum = ~(uip_udpchksum());\r
+ if(UDPBUF->udpchksum == 0) {\r
+ UDPBUF->udpchksum = 0xffff;\r
+ }\r
+#endif /* UIP_UDP_CHECKSUMS */\r
+\r
+ BUF->srcport = uip_udp_conn->lport;\r
+ BUF->destport = uip_udp_conn->rport;\r
+\r
+ BUF->srcipaddr[0] = uip_hostaddr[0];\r
+ BUF->srcipaddr[1] = uip_hostaddr[1];\r
+ BUF->destipaddr[0] = uip_udp_conn->ripaddr[0];\r
+ BUF->destipaddr[1] = uip_udp_conn->ripaddr[1];\r
+ \r
+ uip_appdata = &uip_buf[UIP_LLH_LEN + 40];\r
+ goto ip_send_nolen;\r
+#endif /* UIP_UDP */\r
+ \r
+ /* TCP input processing. */ \r
+ tcp_input:\r
+ UIP_STAT(++uip_stat.tcp.recv);\r
+\r
+ /* Start of TCP input header processing code. */\r
+ \r
+#if 1 // FIXME\r
+ if(uip_tcpchksum() != 0xffff) { /* Compute and check the TCP\r
+ checksum. */\r
+ UIP_STAT(++uip_stat.tcp.drop);\r
+ UIP_STAT(++uip_stat.tcp.chkerr);\r
+ UIP_LOG("tcp: bad checksum."); \r
+ goto drop;\r
+ }\r
+#endif\r
+ \r
+ /* Demultiplex this segment. */\r
+ /* First check any active connections. */\r
+ for(uip_connr = &uip_conns[0]; uip_connr < &uip_conns[UIP_CONNS]; ++uip_connr) {\r
+ if(uip_connr->tcpstateflags != CLOSED &&\r
+ BUF->destport == uip_connr->lport &&\r
+ BUF->srcport == uip_connr->rport &&\r
+ BUF->srcipaddr[0] == uip_connr->ripaddr[0] &&\r
+ BUF->srcipaddr[1] == uip_connr->ripaddr[1]) {\r
+ goto found; \r
+ }\r
+ }\r
+\r
+ /* If we didn't find and active connection that expected the packet,\r
+ either this packet is an old duplicate, or this is a SYN packet\r
+ destined for a connection in LISTEN. If the SYN flag isn't set,\r
+ it is an old packet and we send a RST. */\r
+ if((BUF->flags & TCP_CTL) != TCP_SYN)\r
+ goto reset;\r
+ \r
+ tmp16 = BUF->destport;\r
+ /* Next, check listening connections. */ \r
+ for(c = 0; c < UIP_LISTENPORTS; ++c) {\r
+ if(tmp16 == uip_listenports[c])\r
+ goto found_listen;\r
+ }\r
+ \r
+ /* No matching connection found, so we send a RST packet. */\r
+ UIP_STAT(++uip_stat.tcp.synrst);\r
+ reset:\r
+\r
+ /* We do not send resets in response to resets. */\r
+ if(BUF->flags & TCP_RST) \r
+ goto drop;\r
+\r
+ UIP_STAT(++uip_stat.tcp.rst);\r
+ \r
+ BUF->flags = TCP_RST | TCP_ACK;\r
+ uip_len = 40;\r
+ BUF->tcpoffset = 5 << 4;\r
+\r
+ /* Flip the seqno and ackno fields in the TCP header. */\r
+ c = BUF->seqno[3];\r
+ BUF->seqno[3] = BUF->ackno[3]; \r
+ BUF->ackno[3] = c;\r
+ \r
+ c = BUF->seqno[2];\r
+ BUF->seqno[2] = BUF->ackno[2]; \r
+ BUF->ackno[2] = c;\r
+ \r
+ c = BUF->seqno[1];\r
+ BUF->seqno[1] = BUF->ackno[1];\r
+ BUF->ackno[1] = c;\r
+ \r
+ c = BUF->seqno[0];\r
+ BUF->seqno[0] = BUF->ackno[0]; \r
+ BUF->ackno[0] = c;\r
+\r
+ /* We also have to increase the sequence number we are\r
+ acknowledging. If the least significant byte overflowed, we need\r
+ to propagate the carry to the other bytes as well. */\r
+ if(++BUF->ackno[3] == 0) {\r
+ if(++BUF->ackno[2] == 0) {\r
+ if(++BUF->ackno[1] == 0) {\r
+ ++BUF->ackno[0];\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Swap port numbers. */\r
+ tmp16 = BUF->srcport;\r
+ BUF->srcport = BUF->destport;\r
+ BUF->destport = tmp16;\r
+ \r
+ /* Swap IP addresses. */\r
+ tmp16 = BUF->destipaddr[0];\r
+ BUF->destipaddr[0] = BUF->srcipaddr[0];\r
+ BUF->srcipaddr[0] = tmp16;\r
+ tmp16 = BUF->destipaddr[1];\r
+ BUF->destipaddr[1] = BUF->srcipaddr[1];\r
+ BUF->srcipaddr[1] = tmp16;\r
+\r
+ \r
+ /* And send out the RST packet! */\r
+ goto tcp_send_noconn;\r
+\r
+ /* This label will be jumped to if we matched the incoming packet\r
+ with a connection in LISTEN. In that case, we should create a new\r
+ connection and send a SYNACK in return. */\r
+ found_listen:\r
+ /* First we check if there are any connections avaliable. Unused\r
+ connections are kept in the same table as used connections, but\r
+ unused ones have the tcpstate set to CLOSED. Also, connections in\r
+ TIME_WAIT are kept track of and we'll use the oldest one if no\r
+ CLOSED connections are found. Thanks to Eddie C. Dost for a very\r
+ nice algorithm for the TIME_WAIT search. */\r
+ uip_connr = 0;\r
+ for(c = 0; c < UIP_CONNS; ++c) {\r
+ if(uip_conns[c].tcpstateflags == CLOSED) {\r
+ uip_connr = &uip_conns[c];\r
+ break;\r
+ }\r
+ if(uip_conns[c].tcpstateflags == TIME_WAIT) {\r
+ if(uip_connr == 0 ||\r
+ uip_conns[c].timer > uip_connr->timer) {\r
+ uip_connr = &uip_conns[c];\r
+ }\r
+ }\r
+ }\r
+\r
+ if(uip_connr == 0) {\r
+ /* All connections are used already, we drop packet and hope that\r
+ the remote end will retransmit the packet at a time when we\r
+ have more spare connections. */\r
+ UIP_STAT(++uip_stat.tcp.syndrop);\r
+ UIP_LOG("tcp: found no unused connections.");\r
+ goto drop;\r
+ }\r
+ uip_conn = uip_connr;\r
+ \r
+ /* Fill in the necessary fields for the new connection. */\r
+ uip_connr->rto = uip_connr->timer = UIP_RTO;\r
+ uip_connr->sa = 0;\r
+ uip_connr->sv = 4; \r
+ uip_connr->nrtx = 0;\r
+ uip_connr->lport = BUF->destport;\r
+ uip_connr->rport = BUF->srcport;\r
+ uip_connr->ripaddr[0] = BUF->srcipaddr[0];\r
+ uip_connr->ripaddr[1] = BUF->srcipaddr[1];\r
+ uip_connr->tcpstateflags = SYN_RCVD;\r
+\r
+ uip_connr->snd_nxt[0] = iss[0];\r
+ uip_connr->snd_nxt[1] = iss[1];\r
+ uip_connr->snd_nxt[2] = iss[2];\r
+ uip_connr->snd_nxt[3] = iss[3];\r
+ uip_connr->len = 1;\r
+\r
+ /* rcv_nxt should be the seqno from the incoming packet + 1. */\r
+ uip_connr->rcv_nxt[3] = BUF->seqno[3];\r
+ uip_connr->rcv_nxt[2] = BUF->seqno[2];\r
+ uip_connr->rcv_nxt[1] = BUF->seqno[1];\r
+ uip_connr->rcv_nxt[0] = BUF->seqno[0];\r
+ uip_add_rcv_nxt(1);\r
+\r
+ /* Parse the TCP MSS option, if present. */\r
+ if((BUF->tcpoffset & 0xf0) > 0x50) {\r
+ for(c = 0; c < ((BUF->tcpoffset >> 4) - 5) << 2 ;) {\r
+ opt = uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + c];\r
+ if(opt == 0x00) {\r
+ /* End of options. */ \r
+ break;\r
+ } else if(opt == 0x01) {\r
+ ++c;\r
+ /* NOP option. */\r
+ } else if(opt == 0x02 &&\r
+ uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0x04) {\r
+ /* An MSS option with the right option length. */ \r
+ tmp16 = ((u16_t)uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 2 + c] << 8) |\r
+ (u16_t)uip_buf[40 + UIP_LLH_LEN + 3 + c];\r
+ uip_connr->initialmss = uip_connr->mss =\r
+ tmp16 > UIP_TCP_MSS? UIP_TCP_MSS: tmp16;\r
+ \r
+ /* And we are done processing options. */\r
+ break;\r
+ } else {\r
+ /* All other options have a length field, so that we easily\r
+ can skip past them. */\r
+ if(uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0) {\r
+ /* If the length field is zero, the options are malformed\r
+ and we don't process them further. */\r
+ break;\r
+ }\r
+ c += uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c];\r
+ } \r
+ }\r
+ }\r
+ \r
+ /* Our response will be a SYNACK. */\r
+#if UIP_ACTIVE_OPEN\r
+ tcp_send_synack:\r
+ BUF->flags = TCP_ACK; \r
+ \r
+ tcp_send_syn:\r
+ BUF->flags |= TCP_SYN; \r
+#else /* UIP_ACTIVE_OPEN */\r
+ tcp_send_synack:\r
+ BUF->flags = TCP_SYN | TCP_ACK; \r
+#endif /* UIP_ACTIVE_OPEN */\r
+ \r
+ /* We send out the TCP Maximum Segment Size option with our\r
+ SYNACK. */\r
+ BUF->optdata[0] = 2;\r
+ BUF->optdata[1] = 4;\r
+ BUF->optdata[2] = (UIP_TCP_MSS) / 256;\r
+ BUF->optdata[3] = (UIP_TCP_MSS) & 255;\r
+ uip_len = 44;\r
+ BUF->tcpoffset = 6 << 4;\r
+ goto tcp_send;\r
+\r
+ /* This label will be jumped to if we found an active connection. */\r
+ found:\r
+ uip_conn = uip_connr;\r
+ uip_flags = 0;\r
+\r
+ /* We do a very naive form of TCP reset processing; we just accept\r
+ any RST and kill our connection. We should in fact check if the\r
+ sequence number of this reset is wihtin our advertised window\r
+ before we accept the reset. */\r
+ if(BUF->flags & TCP_RST) {\r
+ uip_connr->tcpstateflags = CLOSED;\r
+ UIP_LOG("tcp: got reset, aborting connection.");\r
+ uip_flags = UIP_ABORT;\r
+ UIP_APPCALL();\r
+ goto drop;\r
+ } \r
+ /* Calculated the length of the data, if the application has sent\r
+ any data to us. */\r
+ c = (BUF->tcpoffset >> 4) << 2;\r
+ /* uip_len will contain the length of the actual TCP data. This is\r
+ calculated by subtracing the length of the TCP header (in\r
+ c) and the length of the IP header (20 bytes). */\r
+ uip_len = uip_len - c - 20;\r
+\r
+ /* First, check if the sequence number of the incoming packet is\r
+ what we're expecting next. If not, we send out an ACK with the\r
+ correct numbers in. */\r
+ if(uip_len > 0 &&\r
+ (BUF->seqno[0] != uip_connr->rcv_nxt[0] ||\r
+ BUF->seqno[1] != uip_connr->rcv_nxt[1] ||\r
+ BUF->seqno[2] != uip_connr->rcv_nxt[2] ||\r
+ BUF->seqno[3] != uip_connr->rcv_nxt[3])) {\r
+ goto tcp_send_ack;\r
+ }\r
+\r
+ /* Next, check if the incoming segment acknowledges any outstanding\r
+ data. If so, we update the sequence number, reset the length of\r
+ the outstanding data, calculate RTT estimations, and reset the\r
+ retransmission timer. */\r
+ if((BUF->flags & TCP_ACK) && uip_outstanding(uip_connr)) {\r
+ uip_add32(uip_connr->snd_nxt, uip_connr->len);\r
+ if(BUF->ackno[0] == uip_acc32[0] &&\r
+ BUF->ackno[1] == uip_acc32[1] &&\r
+ BUF->ackno[2] == uip_acc32[2] &&\r
+ BUF->ackno[3] == uip_acc32[3]) {\r
+ /* Update sequence number. */\r
+ uip_connr->snd_nxt[0] = uip_acc32[0];\r
+ uip_connr->snd_nxt[1] = uip_acc32[1];\r
+ uip_connr->snd_nxt[2] = uip_acc32[2];\r
+ uip_connr->snd_nxt[3] = uip_acc32[3];\r
+ \r
+\r
+ /* Do RTT estimation, unless we have done retransmissions. */\r
+ if(uip_connr->nrtx == 0) {\r
+ signed char m;\r
+ m = uip_connr->rto - uip_connr->timer;\r
+ /* This is taken directly from VJs original code in his paper */\r
+ m = m - (uip_connr->sa >> 3);\r
+ uip_connr->sa += m;\r
+ if(m < 0) {\r
+ m = -m;\r
+ }\r
+ m = m - (uip_connr->sv >> 2);\r
+ uip_connr->sv += m;\r
+ uip_connr->rto = (uip_connr->sa >> 3) + uip_connr->sv;\r
+\r
+ }\r
+ /* Set the acknowledged flag. */\r
+ uip_flags = UIP_ACKDATA;\r
+ /* Reset the retransmission timer. */\r
+ uip_connr->timer = uip_connr->rto;\r
+ }\r
+ \r
+ }\r
+\r
+ /* Do different things depending on in what state the connection is. */\r
+ switch(uip_connr->tcpstateflags & TS_MASK) {\r
+ /* CLOSED and LISTEN are not handled here. CLOSE_WAIT is not\r
+ implemented, since we force the application to close when the\r
+ peer sends a FIN (hence the application goes directly from\r
+ ESTABLISHED to LAST_ACK). */\r
+ case SYN_RCVD:\r
+ /* In SYN_RCVD we have sent out a SYNACK in response to a SYN, and\r
+ we are waiting for an ACK that acknowledges the data we sent\r
+ out the last time. Therefore, we want to have the UIP_ACKDATA\r
+ flag set. If so, we enter the ESTABLISHED state. */\r
+ if(uip_flags & UIP_ACKDATA) {\r
+ uip_connr->tcpstateflags = ESTABLISHED;\r
+ uip_flags = UIP_CONNECTED;\r
+ uip_connr->len = 0;\r
+ if(uip_len > 0) {\r
+ uip_flags |= UIP_NEWDATA;\r
+ uip_add_rcv_nxt(uip_len);\r
+ }\r
+ uip_slen = 0;\r
+ UIP_APPCALL();\r
+ goto appsend;\r
+ }\r
+ goto drop;\r
+#if UIP_ACTIVE_OPEN\r
+ case SYN_SENT:\r
+ /* In SYN_SENT, we wait for a SYNACK that is sent in response to\r
+ our SYN. The rcv_nxt is set to sequence number in the SYNACK\r
+ plus one, and we send an ACK. We move into the ESTABLISHED\r
+ state. */\r
+ if((uip_flags & UIP_ACKDATA) &&\r
+ BUF->flags == (TCP_SYN | TCP_ACK)) {\r
+\r
+ /* Parse the TCP MSS option, if present. */\r
+ if((BUF->tcpoffset & 0xf0) > 0x50) {\r
+ for(c = 0; c < ((BUF->tcpoffset >> 4) - 5) << 2 ;) {\r
+ opt = uip_buf[40 + UIP_LLH_LEN + c];\r
+ if(opt == 0x00) {\r
+ /* End of options. */ \r
+ break;\r
+ } else if(opt == 0x01) {\r
+ ++c;\r
+ /* NOP option. */\r
+ } else if(opt == 0x02 &&\r
+ uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0x04) {\r
+ /* An MSS option with the right option length. */\r
+ tmp16 = (uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 2 + c] << 8) |\r
+ uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 3 + c];\r
+ uip_connr->initialmss =\r
+ uip_connr->mss = tmp16 > UIP_TCP_MSS? UIP_TCP_MSS: tmp16;\r
+\r
+ /* And we are done processing options. */\r
+ break;\r
+ } else {\r
+ /* All other options have a length field, so that we easily\r
+ can skip past them. */\r
+ if(uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0) {\r
+ /* If the length field is zero, the options are malformed\r
+ and we don't process them further. */\r
+ break;\r
+ }\r
+ c += uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c];\r
+ } \r
+ }\r
+ }\r
+ uip_connr->tcpstateflags = ESTABLISHED; \r
+ uip_connr->rcv_nxt[0] = BUF->seqno[0];\r
+ uip_connr->rcv_nxt[1] = BUF->seqno[1];\r
+ uip_connr->rcv_nxt[2] = BUF->seqno[2];\r
+ uip_connr->rcv_nxt[3] = BUF->seqno[3];\r
+ uip_add_rcv_nxt(1);\r
+ uip_flags = UIP_CONNECTED | UIP_NEWDATA;\r
+ uip_connr->len = 0;\r
+ uip_len = 0;\r
+ uip_slen = 0;\r
+ UIP_APPCALL();\r
+ goto appsend;\r
+ }\r
+ goto reset;\r
+#endif /* UIP_ACTIVE_OPEN */\r
+ \r
+ case ESTABLISHED:\r
+ /* In the ESTABLISHED state, we call upon the application to feed\r
+ data into the uip_buf. If the UIP_ACKDATA flag is set, the\r
+ application should put new data into the buffer, otherwise we are\r
+ retransmitting an old segment, and the application should put that\r
+ data into the buffer.\r
+\r
+ If the incoming packet is a FIN, we should close the connection on\r
+ this side as well, and we send out a FIN and enter the LAST_ACK\r
+ state. We require that there is no outstanding data; otherwise the\r
+ sequence numbers will be screwed up. */\r
+\r
+ if(BUF->flags & TCP_FIN) {\r
+ if(uip_outstanding(uip_connr)) {\r
+ goto drop;\r
+ }\r
+ uip_add_rcv_nxt(1 + uip_len); \r
+ uip_flags = UIP_CLOSE;\r
+ if(uip_len > 0) {\r
+ uip_flags |= UIP_NEWDATA;\r
+ }\r
+ UIP_APPCALL();\r
+ uip_connr->len = 1;\r
+ uip_connr->tcpstateflags = LAST_ACK;\r
+ uip_connr->nrtx = 0;\r
+ tcp_send_finack:\r
+ BUF->flags = TCP_FIN | TCP_ACK; \r
+ goto tcp_send_nodata;\r
+ }\r
+\r
+ /* Check the URG flag. If this is set, the segment carries urgent\r
+ data that we must pass to the application. */\r
+ if(BUF->flags & TCP_URG) {\r
+#if UIP_URGDATA > 0\r
+ uip_urglen = (BUF->urgp[0] << 8) | BUF->urgp[1];\r
+ if(uip_urglen > uip_len) {\r
+ /* There is more urgent data in the next segment to come. */\r
+ uip_urglen = uip_len;\r
+ }\r
+ uip_add_rcv_nxt(uip_urglen);\r
+ uip_len -= uip_urglen;\r
+ uip_urgdata = uip_appdata;\r
+ uip_appdata += uip_urglen;\r
+ } else {\r
+ uip_urglen = 0;\r
+#endif /* UIP_URGDATA > 0 */\r
+ uip_appdata += (BUF->urgp[0] << 8) | BUF->urgp[1];\r
+ uip_len -= (BUF->urgp[0] << 8) | BUF->urgp[1];\r
+ }\r
+ \r
+ \r
+ /* If uip_len > 0 we have TCP data in the packet, and we flag this\r
+ by setting the UIP_NEWDATA flag and update the sequence number\r
+ we acknowledge. If the application has stopped the dataflow\r
+ using uip_stop(), we must not accept any data packets from the\r
+ remote host. */\r
+ if(uip_len > 0 && !(uip_connr->tcpstateflags & UIP_STOPPED)) {\r
+ uip_flags |= UIP_NEWDATA;\r
+ uip_add_rcv_nxt(uip_len);\r
+ }\r
+\r
+ /* Check if the available buffer space advertised by the other end\r
+ is smaller than the initial MSS for this connection. If so, we\r
+ set the current MSS to the window size to ensure that the\r
+ application does not send more data than the other end can\r
+ handle.\r
+\r
+ If the remote host advertises a zero window, we set the MSS to\r
+ the initial MSS so that the application will send an entire MSS\r
+ of data. This data will not be acknowledged by the receiver,\r
+ and the application will retransmit it. This is called the\r
+ "persistent timer" and uses the retransmission mechanim.\r
+ */\r
+ tmp16 = ((u16_t)BUF->wnd[0] << 8) + (u16_t)BUF->wnd[1];\r
+ if(tmp16 > uip_connr->initialmss ||\r
+ tmp16 == 0) {\r
+ tmp16 = uip_connr->initialmss;\r
+ }\r
+ uip_connr->mss = tmp16;\r
+\r
+ /* If this packet constitutes an ACK for outstanding data (flagged\r
+ by the UIP_ACKDATA flag, we should call the application since it\r
+ might want to send more data. If the incoming packet had data\r
+ from the peer (as flagged by the UIP_NEWDATA flag), the\r
+ application must also be notified.\r
+\r
+ When the application is called, the global variable uip_len\r
+ contains the length of the incoming data. The application can\r
+ access the incoming data through the global pointer\r
+ uip_appdata, which usually points 40 bytes into the uip_buf\r
+ array.\r
+\r
+ If the application wishes to send any data, this data should be\r
+ put into the uip_appdata and the length of the data should be\r
+ put into uip_len. If the application don't have any data to\r
+ send, uip_len must be set to 0. */\r
+ if(uip_flags & (UIP_NEWDATA | UIP_ACKDATA)) {\r
+ uip_slen = 0;\r
+ UIP_APPCALL();\r
+\r
+ appsend:\r
+ \r
+ if(uip_flags & UIP_ABORT) {\r
+ uip_slen = 0;\r
+ uip_connr->tcpstateflags = CLOSED;\r
+ BUF->flags = TCP_RST | TCP_ACK;\r
+ goto tcp_send_nodata;\r
+ }\r
+\r
+ if(uip_flags & UIP_CLOSE) {\r
+ uip_slen = 0;\r
+ uip_connr->len = 1;\r
+ uip_connr->tcpstateflags = FIN_WAIT_1;\r
+ uip_connr->nrtx = 0;\r
+ BUF->flags = TCP_FIN | TCP_ACK;\r
+ goto tcp_send_nodata; \r
+ }\r
+\r
+ /* If uip_slen > 0, the application has data to be sent. */\r
+ if(uip_slen > 0) {\r
+\r
+ /* If the connection has acknowledged data, the contents of\r
+ the ->len variable should be discarded. */ \r
+ if((uip_flags & UIP_ACKDATA) != 0) {\r
+ uip_connr->len = 0;\r
+ }\r
+\r
+ /* If the ->len variable is non-zero the connection has\r
+ already data in transit and cannot send anymore right\r
+ now. */\r
+ if(uip_connr->len == 0) {\r
+\r
+ /* The application cannot send more than what is allowed by\r
+ the mss (the minumum of the MSS and the available\r
+ window). */\r
+ if(uip_slen > uip_connr->mss) {\r
+ uip_slen = uip_connr->mss;\r
+ }\r
+\r
+ /* Remember how much data we send out now so that we know\r
+ when everything has been acknowledged. */\r
+ uip_connr->len = uip_slen;\r
+ } else {\r
+\r
+ /* If the application already had unacknowledged data, we\r
+ make sure that the application does not send (i.e.,\r
+ retransmit) out more than it previously sent out. */\r
+ uip_slen = uip_connr->len;\r
+ }\r
+ } else {\r
+ uip_connr->len = 0;\r
+ }\r
+ uip_connr->nrtx = 0;\r
+ apprexmit:\r
+ uip_appdata = uip_sappdata;\r
+ \r
+ /* If the application has data to be sent, or if the incoming\r
+ packet had new data in it, we must send out a packet. */\r
+ if(uip_slen > 0 && uip_connr->len > 0) {\r
+ /* Add the length of the IP and TCP headers. */\r
+ uip_len = uip_connr->len + UIP_TCPIP_HLEN;\r
+ /* We always set the ACK flag in response packets. */\r
+ BUF->flags = TCP_ACK | TCP_PSH;\r
+ /* Send the packet. */\r
+ goto tcp_send_noopts;\r
+ }\r
+ /* If there is no data to send, just send out a pure ACK if\r
+ there is newdata. */\r
+ if(uip_flags & UIP_NEWDATA) {\r
+ uip_len = UIP_TCPIP_HLEN;\r
+ BUF->flags = TCP_ACK;\r
+ goto tcp_send_noopts;\r
+ }\r
+ }\r
+ goto drop;\r
+ case LAST_ACK:\r
+ /* We can close this connection if the peer has acknowledged our\r
+ FIN. This is indicated by the UIP_ACKDATA flag. */ \r
+ if(uip_flags & UIP_ACKDATA) {\r
+ uip_connr->tcpstateflags = CLOSED;\r
+ uip_flags = UIP_CLOSE;\r
+ UIP_APPCALL();\r
+ }\r
+ break;\r
+ \r
+ case FIN_WAIT_1:\r
+ /* The application has closed the connection, but the remote host\r
+ hasn't closed its end yet. Thus we do nothing but wait for a\r
+ FIN from the other side. */\r
+ if(uip_len > 0) {\r
+ uip_add_rcv_nxt(uip_len);\r
+ }\r
+ if(BUF->flags & TCP_FIN) {\r
+ if(uip_flags & UIP_ACKDATA) {\r
+ uip_connr->tcpstateflags = TIME_WAIT;\r
+ uip_connr->timer = 0;\r
+ uip_connr->len = 0;\r
+ } else {\r
+ uip_connr->tcpstateflags = CLOSING;\r
+ }\r
+ uip_add_rcv_nxt(1);\r
+ uip_flags = UIP_CLOSE;\r
+ UIP_APPCALL();\r
+ goto tcp_send_ack;\r
+ } else if(uip_flags & UIP_ACKDATA) {\r
+ uip_connr->tcpstateflags = FIN_WAIT_2;\r
+ uip_connr->len = 0;\r
+ goto drop;\r
+ }\r
+ if(uip_len > 0) {\r
+ goto tcp_send_ack;\r
+ }\r
+ goto drop;\r
+ \r
+ case FIN_WAIT_2:\r
+ if(uip_len > 0) {\r
+ uip_add_rcv_nxt(uip_len);\r
+ }\r
+ if(BUF->flags & TCP_FIN) {\r
+ uip_connr->tcpstateflags = TIME_WAIT;\r
+ uip_connr->timer = 0;\r
+ uip_add_rcv_nxt(1);\r
+ uip_flags = UIP_CLOSE;\r
+ UIP_APPCALL();\r
+ goto tcp_send_ack;\r
+ }\r
+ if(uip_len > 0) {\r
+ goto tcp_send_ack;\r
+ }\r
+ goto drop;\r
+\r
+ case TIME_WAIT:\r
+ goto tcp_send_ack;\r
+ \r
+ case CLOSING:\r
+ if(uip_flags & UIP_ACKDATA) {\r
+ uip_connr->tcpstateflags = TIME_WAIT;\r
+ uip_connr->timer = 0;\r
+ }\r
+ } \r
+ goto drop;\r
+ \r
+\r
+ /* We jump here when we are ready to send the packet, and just want\r
+ to set the appropriate TCP sequence numbers in the TCP header. */\r
+ tcp_send_ack:\r
+ BUF->flags = TCP_ACK;\r
+ tcp_send_nodata:\r
+ uip_len = 40;\r
+ tcp_send_noopts:\r
+ BUF->tcpoffset = 5 << 4;\r
+ tcp_send:\r
+ /* We're done with the input processing. We are now ready to send a\r
+ reply. Our job is to fill in all the fields of the TCP and IP\r
+ headers before calculating the checksum and finally send the\r
+ packet. */\r
+ BUF->ackno[0] = uip_connr->rcv_nxt[0];\r
+ BUF->ackno[1] = uip_connr->rcv_nxt[1];\r
+ BUF->ackno[2] = uip_connr->rcv_nxt[2];\r
+ BUF->ackno[3] = uip_connr->rcv_nxt[3];\r
+ \r
+ BUF->seqno[0] = uip_connr->snd_nxt[0];\r
+ BUF->seqno[1] = uip_connr->snd_nxt[1];\r
+ BUF->seqno[2] = uip_connr->snd_nxt[2];\r
+ BUF->seqno[3] = uip_connr->snd_nxt[3];\r
+\r
+ BUF->proto = UIP_PROTO_TCP;\r
+ \r
+ BUF->srcport = uip_connr->lport;\r
+ BUF->destport = uip_connr->rport;\r
+\r
+ BUF->srcipaddr[0] = uip_hostaddr[0];\r
+ BUF->srcipaddr[1] = uip_hostaddr[1];\r
+ BUF->destipaddr[0] = uip_connr->ripaddr[0];\r
+ BUF->destipaddr[1] = uip_connr->ripaddr[1];\r
+ \r
+\r
+ if(uip_connr->tcpstateflags & UIP_STOPPED) {\r
+ /* If the connection has issued uip_stop(), we advertise a zero\r
+ window so that the remote host will stop sending data. */\r
+ BUF->wnd[0] = BUF->wnd[1] = 0;\r
+ } else {\r
+ BUF->wnd[0] = ((UIP_RECEIVE_WINDOW) >> 8);\r
+ BUF->wnd[1] = ((UIP_RECEIVE_WINDOW) & 0xff); \r
+ }\r
+\r
+ tcp_send_noconn:\r
+\r
+ BUF->len[0] = (uip_len >> 8);\r
+ BUF->len[1] = (uip_len & 0xff);\r
+\r
+ /* Calculate TCP checksum. */\r
+ BUF->tcpchksum = 0;\r
+ BUF->tcpchksum = ~(uip_tcpchksum());\r
+ \r
+ ip_send_nolen:\r
+\r
+ BUF->vhl = 0x45;\r
+ BUF->tos = 0;\r
+ BUF->ipoffset[0] = BUF->ipoffset[1] = 0;\r
+ BUF->ttl = UIP_TTL;\r
+ ++ipid;\r
+ BUF->ipid[0] = ipid >> 8;\r
+ BUF->ipid[1] = ipid & 0xff;\r
+ \r
+ /* Calculate IP checksum. */\r
+ BUF->ipchksum = 0;\r
+ BUF->ipchksum = ~(uip_ipchksum());\r
+\r
+ UIP_STAT(++uip_stat.tcp.sent);\r
+ send:\r
+ UIP_STAT(++uip_stat.ip.sent);\r
+ /* Return and let the caller do the actual transmission. */\r
+ return;\r
+ drop:\r
+ uip_len = 0;\r
+ return;\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+u16_t\r
+htons(u16_t val)\r
+{\r
+ return HTONS(val);\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+/** @} */\r
--- /dev/null
+/**\r
+ * \addtogroup uip\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * Header file for the uIP TCP/IP stack.\r
+ * \author Adam Dunkels <adam@dunkels.com>\r
+ *\r
+ * The uIP TCP/IP stack header file contains definitions for a number\r
+ * of C macros that are used by uIP programs as well as internal uIP\r
+ * structures, TCP/IP header structures and function declarations.\r
+ *\r
+ */\r
+\r
+\r
+/*\r
+ * Copyright (c) 2001-2003, Adam Dunkels.\r
+ * All rights reserved. \r
+ *\r
+ * Redistribution and use in source and binary forms, with or without \r
+ * modification, are permitted provided that the following conditions \r
+ * are met: \r
+ * 1. Redistributions of source code must retain the above copyright \r
+ * notice, this list of conditions and the following disclaimer. \r
+ * 2. Redistributions in binary form must reproduce the above copyright \r
+ * notice, this list of conditions and the following disclaimer in the \r
+ * documentation and/or other materials provided with the distribution. \r
+ * 3. The name of the author may not be used to endorse or promote\r
+ * products derived from this software without specific prior\r
+ * written permission. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * $Id: uip.h,v 1.36.2.7 2003/10/07 13:47:51 adam Exp $\r
+ *\r
+ */\r
+\r
+#ifndef __UIP_H__\r
+#define __UIP_H__\r
+\r
+#include "uipopt.h"\r
+\r
+/*-----------------------------------------------------------------------------------*/\r
+/* First, the functions that should be called from the\r
+ * system. Initialization, the periodic timer and incoming packets are\r
+ * handled by the following three functions.\r
+ */\r
+\r
+/**\r
+ * \defgroup uipconffunc uIP configuration functions\r
+ * @{\r
+ *\r
+ * The uIP configuration functions are used for setting run-time\r
+ * parameters in uIP such as IP addresses. \r
+ */\r
+\r
+/**\r
+ * Set the IP address of this host.\r
+ *\r
+ * The IP address is represented as a 4-byte array where the first\r
+ * octet of the IP address is put in the first member of the 4-byte\r
+ * array.\r
+ *\r
+ * \param addr A pointer to a 4-byte representation of the IP address.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_sethostaddr(addr) do { uip_hostaddr[0] = addr[0]; \\r
+ uip_hostaddr[1] = addr[1]; } while(0)\r
+\r
+/**\r
+ * Get the IP address of this host.\r
+ *\r
+ * The IP address is represented as a 4-byte array where the first\r
+ * octet of the IP address is put in the first member of the 4-byte\r
+ * array.\r
+ *\r
+ * \param addr A pointer to a 4-byte array that will be filled in with\r
+ * the currently configured IP address.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_gethostaddr(addr) do { addr[0] = uip_hostaddr[0]; \\r
+ addr[1] = uip_hostaddr[1]; } while(0)\r
+\r
+/** @} */\r
+\r
+/**\r
+ * \defgroup uipinit uIP initialization functions\r
+ * @{\r
+ *\r
+ * The uIP initialization functions are used for booting uIP.\r
+ */\r
+\r
+/**\r
+ * uIP initialization function.\r
+ *\r
+ * This function should be called at boot up to initilize the uIP\r
+ * TCP/IP stack.\r
+ */\r
+void uip_init(void);\r
+\r
+/** @} */\r
+\r
+/**\r
+ * \defgroup uipdevfunc uIP device driver functions\r
+ * @{\r
+ *\r
+ * These functions are used by a network device driver for interacting\r
+ * with uIP.\r
+ */\r
+\r
+/**\r
+ * Process an incoming packet.\r
+ *\r
+ * This function should be called when the device driver has received\r
+ * a packet from the network. The packet from the device driver must\r
+ * be present in the uip_buf buffer, and the length of the packet\r
+ * should be placed in the uip_len variable.\r
+ *\r
+ * When the function returns, there may be an outbound packet placed\r
+ * in the uip_buf packet buffer. If so, the uip_len variable is set to\r
+ * the length of the packet. If no packet is to be sent out, the\r
+ * uip_len variable is set to 0.\r
+ *\r
+ * The usual way of calling the function is presented by the source\r
+ * code below.\r
+ \code\r
+ uip_len = devicedriver_poll();\r
+ if(uip_len > 0) {\r
+ uip_input();\r
+ if(uip_len > 0) {\r
+ devicedriver_send();\r
+ }\r
+ }\r
+ \endcode\r
+ *\r
+ * \note If you are writing a uIP device driver that needs ARP\r
+ * (Address Resolution Protocol), e.g., when running uIP over\r
+ * Ethernet, you will need to call the uIP ARP code before calling\r
+ * this function:\r
+ \code\r
+ #define BUF ((struct uip_eth_hdr *)&uip_buf[0])\r
+ uip_len = ethernet_devicedrver_poll();\r
+ if(uip_len > 0) {\r
+ if(BUF->type == HTONS(UIP_ETHTYPE_IP)) {\r
+ uip_arp_ipin();\r
+ uip_input();\r
+ if(uip_len > 0) {\r
+ uip_arp_out();\r
+ ethernet_devicedriver_send();\r
+ }\r
+ } else if(BUF->type == HTONS(UIP_ETHTYPE_ARP)) {\r
+ uip_arp_arpin();\r
+ if(uip_len > 0) {\r
+ ethernet_devicedriver_send();\r
+ }\r
+ }\r
+ \endcode\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_input() uip_process(UIP_DATA)\r
+\r
+/**\r
+ * Periodic processing for a connection identified by its number.\r
+ * \r
+ * This function does the necessary periodic processing (timers,\r
+ * polling) for a uIP TCP conneciton, and should be called when the\r
+ * periodic uIP timer goes off. It should be called for every\r
+ * connection, regardless of whether they are open of closed.\r
+ *\r
+ * When the function returns, it may have an outbound packet waiting\r
+ * for service in the uIP packet buffer, and if so the uip_len\r
+ * variable is set to a value larger than zero. The device driver\r
+ * should be called to send out the packet.\r
+ *\r
+ * The ususal way of calling the function is through a for() loop like\r
+ * this:\r
+ \code\r
+ for(i = 0; i < UIP_CONNS; ++i) {\r
+ uip_periodic(i);\r
+ if(uip_len > 0) {\r
+ devicedriver_send();\r
+ }\r
+ }\r
+ \endcode\r
+ *\r
+ * \note If you are writing a uIP device driver that needs ARP\r
+ * (Address Resolution Protocol), e.g., when running uIP over\r
+ * Ethernet, you will need to call the uip_arp_out() function before\r
+ * calling the device driver:\r
+ \code\r
+ for(i = 0; i < UIP_CONNS; ++i) {\r
+ uip_periodic(i);\r
+ if(uip_len > 0) {\r
+ uip_arp_out();\r
+ ethernet_devicedriver_send();\r
+ }\r
+ }\r
+ \endcode \r
+ *\r
+ * \param conn The number of the connection which is to be periodically polled.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_periodic(conn) do { uip_conn = &uip_conns[conn]; \\r
+ uip_process(UIP_TIMER); } while (0)\r
+\r
+/**\r
+ * Periodic processing for a connection identified by a pointer to its structure.\r
+ *\r
+ * Same as uip_periodic() but takes a pointer to the actual uip_conn\r
+ * struct instead of an integer as its argument. This function can be\r
+ * used to force periodic processing of a specific connection.\r
+ *\r
+ * \param conn A pointer to the uip_conn struct for the connection to\r
+ * be processed.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_periodic_conn(conn) do { uip_conn = conn; \\r
+ uip_process(UIP_TIMER); } while (0)\r
+\r
+#if UIP_UDP\r
+/**\r
+ * Periodic processing for a UDP connection identified by its number.\r
+ *\r
+ * This function is essentially the same as uip_prerioic(), but for\r
+ * UDP connections. It is called in a similar fashion as the\r
+ * uip_periodic() function:\r
+ \code\r
+ for(i = 0; i < UIP_UDP_CONNS; i++) {\r
+ uip_udp_periodic(i);\r
+ if(uip_len > 0) {\r
+ devicedriver_send();\r
+ }\r
+ } \r
+ \endcode\r
+ *\r
+ * \note As for the uip_periodic() function, special care has to be\r
+ * taken when using uIP together with ARP and Ethernet:\r
+ \code\r
+ for(i = 0; i < UIP_UDP_CONNS; i++) {\r
+ uip_udp_periodic(i);\r
+ if(uip_len > 0) {\r
+ uip_arp_out();\r
+ ethernet_devicedriver_send();\r
+ }\r
+ } \r
+ \endcode\r
+ *\r
+ * \param conn The number of the UDP connection to be processed.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_udp_periodic(conn) do { uip_udp_conn = &uip_udp_conns[conn]; \\r
+ uip_process(UIP_UDP_TIMER); } while (0)\r
+\r
+/**\r
+ * Periodic processing for a UDP connection identified by a pointer to\r
+ * its structure.\r
+ *\r
+ * Same as uip_udp_periodic() but takes a pointer to the actual\r
+ * uip_conn struct instead of an integer as its argument. This\r
+ * function can be used to force periodic processing of a specific\r
+ * connection.\r
+ *\r
+ * \param conn A pointer to the uip_udp_conn struct for the connection\r
+ * to be processed.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_udp_periodic_conn(conn) do { uip_udp_conn = conn; \\r
+ uip_process(UIP_UDP_TIMER); } while (0)\r
+\r
+\r
+#endif /* UIP_UDP */\r
+\r
+/**\r
+ * The uIP packet buffer.\r
+ *\r
+ * The uip_buf array is used to hold incoming and outgoing\r
+ * packets. The device driver should place incoming data into this\r
+ * buffer. When sending data, the device driver should read the link\r
+ * level headers and the TCP/IP headers from this buffer. The size of\r
+ * the link level headers is configured by the UIP_LLH_LEN define.\r
+ *\r
+ * \note The application data need not be placed in this buffer, so\r
+ * the device driver must read it from the place pointed to by the\r
+ * uip_appdata pointer as illustrated by the following example:\r
+ \code\r
+ void\r
+ devicedriver_send(void)\r
+ {\r
+ hwsend(&uip_buf[0], UIP_LLH_LEN);\r
+ hwsend(&uip_buf[UIP_LLH_LEN], 40);\r
+ hwsend(uip_appdata, uip_len - 40 - UIP_LLH_LEN);\r
+ }\r
+ \endcode\r
+ */\r
+extern u8_t uip_buf[UIP_BUFSIZE+2] __attribute__ ((aligned (4)));\r
+\r
+/** @} */\r
+\r
+/*-----------------------------------------------------------------------------------*/\r
+/* Functions that are used by the uIP application program. Opening and\r
+ * closing connections, sending and receiving data, etc. is all\r
+ * handled by the functions below.\r
+*/\r
+/**\r
+ * \defgroup uipappfunc uIP application functions\r
+ * @{\r
+ *\r
+ * Functions used by an application running of top of uIP.\r
+ */\r
+\r
+/**\r
+ * Start listening to the specified port.\r
+ *\r
+ * \note Since this function expects the port number in network byte\r
+ * order, a conversion using HTONS() or htons() is necessary.\r
+ *\r
+ \code\r
+ uip_listen(HTONS(80)); \r
+ \endcode\r
+ *\r
+ * \param port A 16-bit port number in network byte order.\r
+ */\r
+void uip_listen(u16_t port);\r
+\r
+/**\r
+ * Stop listening to the specified port.\r
+ *\r
+ * \note Since this function expects the port number in network byte\r
+ * order, a conversion using HTONS() or htons() is necessary.\r
+ *\r
+ \code\r
+ uip_unlisten(HTONS(80)); \r
+ \endcode\r
+ *\r
+ * \param port A 16-bit port number in network byte order.\r
+ */\r
+void uip_unlisten(u16_t port);\r
+\r
+/**\r
+ * Connect to a remote host using TCP.\r
+ *\r
+ * This function is used to start a new connection to the specified\r
+ * port on the specied host. It allocates a new connection identifier,\r
+ * sets the connection to the SYN_SENT state and sets the\r
+ * retransmission timer to 0. This will cause a TCP SYN segment to be\r
+ * sent out the next time this connection is periodically processed,\r
+ * which usually is done within 0.5 seconds after the call to\r
+ * uip_connect().\r
+ *\r
+ * \note This function is avaliable only if support for active open\r
+ * has been configured by defining UIP_ACTIVE_OPEN to 1 in uipopt.h.\r
+ *\r
+ * \note Since this function requires the port number to be in network\r
+ * byte order, a convertion using HTONS() or htons() is necessary.\r
+ *\r
+ \code\r
+ u16_t ipaddr[2];\r
+\r
+ uip_ipaddr(ipaddr, 192,168,1,2);\r
+ uip_connect(ipaddr, HTONS(80)); \r
+ \endcode\r
+ * \r
+ * \param ripaddr A pointer to a 4-byte array representing the IP\r
+ * address of the remote hot.\r
+ *\r
+ * \param port A 16-bit port number in network byte order.\r
+ *\r
+ * \return A pointer to the uIP connection identifier for the new connection,\r
+ * or NULL if no connection could be allocated. \r
+ *\r
+ */\r
+struct uip_conn *uip_connect(u16_t *ripaddr, u16_t port);\r
+\r
+\r
+\r
+/**\r
+ * \internal\r
+ *\r
+ * Check if a connection has outstanding (i.e., unacknowledged) data.\r
+ *\r
+ * \param conn A pointer to the uip_conn structure for the connection.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_outstanding(conn) ((conn)->len)\r
+\r
+/**\r
+ * Send data on the current connection.\r
+ *\r
+ * This function is used to send out a single segment of TCP\r
+ * data. Only applications that have been invoked by uIP for event\r
+ * processing can send data. \r
+ *\r
+ * The amount of data that actually is sent out after a call to this\r
+ * funcion is determined by the maximum amount of data TCP allows. uIP\r
+ * will automatically crop the data so that only the appropriate\r
+ * amount of data is sent. The function uip_mss() can be used to query\r
+ * uIP for the amount of data that actually will be sent.\r
+ * \r
+ * \note This function does not guarantee that the sent data will\r
+ * arrive at the destination. If the data is lost in the network, the\r
+ * application will be invoked with the uip_rexmit() event being\r
+ * set. The application will then have to resend the data using this\r
+ * function.\r
+ * \r
+ * \param data A pointer to the data which is to be sent.\r
+ *\r
+ * \param len The maximum amount of data bytes to be sent.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_send(data, len) do { uip_sappdata = (data); uip_slen = (len);} while(0) \r
+\r
+/**\r
+ * The length of any incoming data that is currently avaliable (if avaliable)\r
+ * in the uip_appdata buffer.\r
+ *\r
+ * The test function uip_data() must first be used to check if there\r
+ * is any data available at all.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_datalen() uip_len\r
+\r
+/**\r
+ * The length of any out-of-band data (urgent data) that has arrived\r
+ * on the connection.\r
+ *\r
+ * \note The configuration parameter UIP_URGDATA must be set for this\r
+ * function to be enabled.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_urgdatalen() uip_urglen\r
+\r
+/**\r
+ * Close the current connection.\r
+ *\r
+ * This function will close the current connection in a nice way.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_close() (uip_flags = UIP_CLOSE)\r
+\r
+/**\r
+ * Abort the current connection.\r
+ *\r
+ * This function will abort (reset) the current connection, and is\r
+ * usually used when an error has occured that prevents using the\r
+ * uip_close() function.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_abort() (uip_flags = UIP_ABORT)\r
+\r
+/**\r
+ * Tell the sending host to stop sending data.\r
+ *\r
+ * This function will close our receiver's window so that we stop\r
+ * receiving data for the current connection.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_stop() (uip_conn->tcpstateflags |= UIP_STOPPED)\r
+\r
+/**\r
+ * Find out if the current connection has been previously stopped with\r
+ * uip_stop().\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_stopped(conn) ((conn)->tcpstateflags & UIP_STOPPED)\r
+\r
+/**\r
+ * Restart the current connection, if is has previously been stopped\r
+ * with uip_stop().\r
+ *\r
+ * This function will open the receiver's window again so that we\r
+ * start receiving data for the current connection.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_restart() do { uip_flags |= UIP_NEWDATA; \\r
+ uip_conn->tcpstateflags &= ~UIP_STOPPED; \\r
+ } while(0)\r
+\r
+\r
+/* uIP tests that can be made to determine in what state the current\r
+ connection is, and what the application function should do. */\r
+\r
+/**\r
+ * Is new incoming data available?\r
+ *\r
+ * Will reduce to non-zero if there is new data for the application\r
+ * present at the uip_appdata pointer. The size of the data is\r
+ * avaliable through the uip_len variable.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_newdata() (uip_flags & UIP_NEWDATA)\r
+\r
+/**\r
+ * Has previously sent data been acknowledged?\r
+ *\r
+ * Will reduce to non-zero if the previously sent data has been\r
+ * acknowledged by the remote host. This means that the application\r
+ * can send new data. \r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_acked() (uip_flags & UIP_ACKDATA)\r
+\r
+/**\r
+ * Has the connection just been connected? \r
+ *\r
+ * Reduces to non-zero if the current connection has been connected to\r
+ * a remote host. This will happen both if the connection has been\r
+ * actively opened (with uip_connect()) or passively opened (with\r
+ * uip_listen()).\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_connected() (uip_flags & UIP_CONNECTED)\r
+\r
+/**\r
+ * Has the connection been closed by the other end?\r
+ *\r
+ * Is non-zero if the connection has been closed by the remote\r
+ * host. The application may then do the necessary clean-ups.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_closed() (uip_flags & UIP_CLOSE)\r
+\r
+/**\r
+ * Has the connection been aborted by the other end?\r
+ *\r
+ * Non-zero if the current connection has been aborted (reset) by the\r
+ * remote host.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_aborted() (uip_flags & UIP_ABORT)\r
+\r
+/**\r
+ * Has the connection timed out?\r
+ *\r
+ * Non-zero if the current connection has been aborted due to too many\r
+ * retransmissions.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_timedout() (uip_flags & UIP_TIMEDOUT)\r
+\r
+/**\r
+ * Do we need to retransmit previously data?\r
+ *\r
+ * Reduces to non-zero if the previously sent data has been lost in\r
+ * the network, and the application should retransmit it. The\r
+ * application should send the exact same data as it did the last\r
+ * time, using the uip_send() function.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_rexmit() (uip_flags & UIP_REXMIT)\r
+\r
+/**\r
+ * Is the connection being polled by uIP?\r
+ *\r
+ * Is non-zero if the reason the application is invoked is that the\r
+ * current connection has been idle for a while and should be\r
+ * polled.\r
+ *\r
+ * The polling event can be used for sending data without having to\r
+ * wait for the remote host to send data.\r
+ *\r
+ * \hideinitializer\r
+ */ \r
+#define uip_poll() (uip_flags & UIP_POLL)\r
+\r
+/**\r
+ * Get the initial maxium segment size (MSS) of the current\r
+ * connection.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_initialmss() (uip_conn->initialmss)\r
+\r
+/**\r
+ * Get the current maxium segment size that can be sent on the current\r
+ * connection.\r
+ *\r
+ * The current maxiumum segment size that can be sent on the\r
+ * connection is computed from the receiver's window and the MSS of\r
+ * the connection (which also is available by calling\r
+ * uip_initialmss()).\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_mss() (uip_conn->mss)\r
+\r
+/**\r
+ * Set up a new UDP connection.\r
+ *\r
+ * \param ripaddr A pointer to a 4-byte structure representing the IP\r
+ * address of the remote host.\r
+ *\r
+ * \param rport The remote port number in network byte order.\r
+ *\r
+ * \return The uip_udp_conn structure for the new connection or NULL\r
+ * if no connection could be allocated.\r
+ */\r
+struct uip_udp_conn *uip_udp_new(u16_t *ripaddr, u16_t rport);\r
+\r
+/**\r
+ * Removed a UDP connection.\r
+ *\r
+ * \param conn A pointer to the uip_udp_conn structure for the connection.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_udp_remove(conn) (conn)->lport = 0\r
+\r
+/**\r
+ * Send a UDP datagram of length len on the current connection.\r
+ *\r
+ * This function can only be called in response to a UDP event (poll\r
+ * or newdata). The data must be present in the uip_buf buffer, at the\r
+ * place pointed to by the uip_appdata pointer.\r
+ *\r
+ * \param len The length of the data in the uip_buf buffer.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_udp_send(len) uip_slen = (len)\r
+\r
+/** @} */\r
+\r
+/* uIP convenience and converting functions. */\r
+\r
+/**\r
+ * \defgroup uipconvfunc uIP conversion functions\r
+ * @{\r
+ *\r
+ * These functions can be used for converting between different data\r
+ * formats used by uIP.\r
+ */\r
+ \r
+/**\r
+ * Pack an IP address into a 4-byte array which is used by uIP to\r
+ * represent IP addresses.\r
+ *\r
+ * Example:\r
+ \code\r
+ u16_t ipaddr[2];\r
+\r
+ uip_ipaddr(&ipaddr, 192,168,1,2); \r
+ \endcode\r
+ *\r
+ * \param addr A pointer to a 4-byte array that will be filled in with\r
+ * the IP addres.\r
+ * \param addr0 The first octet of the IP address.\r
+ * \param addr1 The second octet of the IP address.\r
+ * \param addr2 The third octet of the IP address.\r
+ * \param addr3 The forth octet of the IP address. \r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_ipaddr(addr, addr0,addr1,addr2,addr3) do { \\r
+ (addr)[0] = HTONS(((addr0) << 8) | (addr1)); \\r
+ (addr)[1] = HTONS(((addr2) << 8) | (addr3)); \\r
+ } while(0)\r
+\r
+/**\r
+ * Convert 16-bit quantity from host byte order to network byte order.\r
+ *\r
+ * This macro is primarily used for converting constants from host\r
+ * byte order to network byte order. For converting variables to\r
+ * network byte order, use the htons() function instead.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#ifndef HTONS\r
+# if BYTE_ORDER == BIG_ENDIAN\r
+# define HTONS(n) (n)\r
+# else /* BYTE_ORDER == BIG_ENDIAN */\r
+# define HTONS(n) ((((u16_t)((n) & 0xff)) << 8) | (((n) & 0xff00) >> 8))\r
+# endif /* BYTE_ORDER == BIG_ENDIAN */\r
+#endif /* HTONS */\r
+\r
+/**\r
+ * Convert 16-bit quantity from host byte order to network byte order.\r
+ *\r
+ * This function is primarily used for converting variables from host\r
+ * byte order to network byte order. For converting constants to\r
+ * network byte order, use the HTONS() macro instead.\r
+ */\r
+#ifndef htons\r
+u16_t htons(u16_t val);\r
+#endif /* htons */\r
+\r
+/** @} */\r
+\r
+/**\r
+ * Pointer to the application data in the packet buffer.\r
+ *\r
+ * This pointer points to the application data when the application is\r
+ * called. If the application wishes to send data, the application may\r
+ * use this space to write the data into before calling uip_send().\r
+ */\r
+extern volatile u8_t *uip_appdata;\r
+extern volatile u8_t *uip_sappdata; \r
+\r
+#if UIP_URGDATA > 0 \r
+/* u8_t *uip_urgdata:\r
+ *\r
+ * This pointer points to any urgent data that has been received. Only\r
+ * present if compiled with support for urgent data (UIP_URGDATA).\r
+ */\r
+extern volatile u8_t *uip_urgdata; \r
+#endif /* UIP_URGDATA > 0 */\r
+\r
+\r
+/* u[8|16]_t uip_len:\r
+ *\r
+ * When the application is called, uip_len contains the length of any\r
+ * new data that has been received from the remote host. The\r
+ * application should set this variable to the size of any data that\r
+ * the application wishes to send. When the network device driver\r
+ * output function is called, uip_len should contain the length of the\r
+ * outgoing packet.\r
+ */\r
+extern volatile u16_t uip_len, uip_slen;\r
+\r
+#if UIP_URGDATA > 0 \r
+extern volatile u8_t uip_urglen, uip_surglen;\r
+#endif /* UIP_URGDATA > 0 */\r
+\r
+\r
+/**\r
+ * Representation of a uIP TCP connection.\r
+ *\r
+ * The uip_conn structure is used for identifying a connection. All\r
+ * but one field in the structure are to be considered read-only by an\r
+ * application. The only exception is the appstate field whos purpose\r
+ * is to let the application store application-specific state (e.g.,\r
+ * file pointers) for the connection. The size of this field is\r
+ * configured in the "uipopt.h" header file.\r
+ */\r
+struct uip_conn {\r
+ u16_t ripaddr[2]; /**< The IP address of the remote host. */\r
+ \r
+ u16_t lport; /**< The local TCP port, in network byte order. */\r
+ u16_t rport; /**< The local remote TCP port, in network byte\r
+ order. */ \r
+ \r
+ u8_t rcv_nxt[4]; /**< The sequence number that we expect to\r
+ receive next. */\r
+ u8_t snd_nxt[4]; /**< The sequence number that was last sent by\r
+ us. */\r
+ u16_t len; /**< Length of the data that was previously sent. */\r
+ u16_t mss; /**< Current maximum segment size for the\r
+ connection. */\r
+ u16_t initialmss; /**< Initial maximum segment size for the\r
+ connection. */ \r
+ u8_t sa; /**< Retransmission time-out calculation state\r
+ variable. */\r
+ u8_t sv; /**< Retransmission time-out calculation state\r
+ variable. */\r
+ u8_t rto; /**< Retransmission time-out. */\r
+ u8_t tcpstateflags; /**< TCP state and flags. */\r
+ u8_t timer; /**< The retransmission timer. */\r
+ u8_t nrtx; /**< The number of retransmissions for the last\r
+ segment sent. */\r
+\r
+ /** The application state. */\r
+ u8_t appstate[UIP_APPSTATE_SIZE]; \r
+};\r
+\r
+\r
+/* Pointer to the current connection. */\r
+extern struct uip_conn *uip_conn;\r
+/* The array containing all uIP connections. */\r
+extern struct uip_conn uip_conns[UIP_CONNS];\r
+/**\r
+ * \addtogroup uiparch\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * 4-byte array used for the 32-bit sequence number calculations.\r
+ */\r
+extern volatile u8_t uip_acc32[4];\r
+\r
+/** @} */\r
+\r
+\r
+#if UIP_UDP\r
+/**\r
+ * Representation of a uIP UDP connection.\r
+ */\r
+struct uip_udp_conn {\r
+ u16_t ripaddr[2]; /**< The IP address of the remote peer. */\r
+ u16_t lport; /**< The local port number in network byte order. */\r
+ u16_t rport; /**< The remote port number in network byte order. */\r
+};\r
+\r
+extern struct uip_udp_conn *uip_udp_conn;\r
+extern struct uip_udp_conn uip_udp_conns[UIP_UDP_CONNS];\r
+#endif /* UIP_UDP */\r
+\r
+/**\r
+ * The structure holding the TCP/IP statistics that are gathered if\r
+ * UIP_STATISTICS is set to 1.\r
+ *\r
+ */\r
+struct uip_stats {\r
+ struct {\r
+ uip_stats_t drop; /**< Number of dropped packets at the IP\r
+ layer. */\r
+ uip_stats_t recv; /**< Number of received packets at the IP\r
+ layer. */\r
+ uip_stats_t sent; /**< Number of sent packets at the IP\r
+ layer. */\r
+ uip_stats_t vhlerr; /**< Number of packets dropped due to wrong\r
+ IP version or header length. */\r
+ uip_stats_t hblenerr; /**< Number of packets dropped due to wrong\r
+ IP length, high byte. */\r
+ uip_stats_t lblenerr; /**< Number of packets dropped due to wrong\r
+ IP length, low byte. */\r
+ uip_stats_t fragerr; /**< Number of packets dropped since they\r
+ were IP fragments. */\r
+ uip_stats_t chkerr; /**< Number of packets dropped due to IP\r
+ checksum errors. */\r
+ uip_stats_t protoerr; /**< Number of packets dropped since they\r
+ were neither ICMP, UDP nor TCP. */\r
+ } ip; /**< IP statistics. */\r
+ struct {\r
+ uip_stats_t drop; /**< Number of dropped ICMP packets. */\r
+ uip_stats_t recv; /**< Number of received ICMP packets. */\r
+ uip_stats_t sent; /**< Number of sent ICMP packets. */\r
+ uip_stats_t typeerr; /**< Number of ICMP packets with a wrong\r
+ type. */\r
+ } icmp; /**< ICMP statistics. */\r
+ struct {\r
+ uip_stats_t drop; /**< Number of dropped TCP segments. */\r
+ uip_stats_t recv; /**< Number of recived TCP segments. */\r
+ uip_stats_t sent; /**< Number of sent TCP segments. */\r
+ uip_stats_t chkerr; /**< Number of TCP segments with a bad\r
+ checksum. */\r
+ uip_stats_t ackerr; /**< Number of TCP segments with a bad ACK\r
+ number. */\r
+ uip_stats_t rst; /**< Number of recevied TCP RST (reset) segments. */\r
+ uip_stats_t rexmit; /**< Number of retransmitted TCP segments. */\r
+ uip_stats_t syndrop; /**< Number of dropped SYNs due to too few\r
+ connections was avaliable. */\r
+ uip_stats_t synrst; /**< Number of SYNs for closed ports,\r
+ triggering a RST. */\r
+ } tcp; /**< TCP statistics. */\r
+};\r
+\r
+/**\r
+ * The uIP TCP/IP statistics.\r
+ *\r
+ * This is the variable in which the uIP TCP/IP statistics are gathered.\r
+ */\r
+extern struct uip_stats uip_stat;\r
+\r
+\r
+/*-----------------------------------------------------------------------------------*/\r
+/* All the stuff below this point is internal to uIP and should not be\r
+ * used directly by an application or by a device driver.\r
+ */\r
+/*-----------------------------------------------------------------------------------*/\r
+/* u8_t uip_flags:\r
+ *\r
+ * When the application is called, uip_flags will contain the flags\r
+ * that are defined in this file. Please read below for more\r
+ * infomation.\r
+ */\r
+extern volatile u8_t uip_flags;\r
+\r
+/* The following flags may be set in the global variable uip_flags\r
+ before calling the application callback. The UIP_ACKDATA and\r
+ UIP_NEWDATA flags may both be set at the same time, whereas the\r
+ others are mutualy exclusive. Note that these flags should *NOT* be\r
+ accessed directly, but through the uIP functions/macros. */\r
+\r
+#define UIP_ACKDATA 1 /* Signifies that the outstanding data was\r
+ acked and the application should send\r
+ out new data instead of retransmitting\r
+ the last data. */\r
+#define UIP_NEWDATA 2 /* Flags the fact that the peer has sent\r
+ us new data. */\r
+#define UIP_REXMIT 4 /* Tells the application to retransmit the\r
+ data that was last sent. */\r
+#define UIP_POLL 8 /* Used for polling the application, to\r
+ check if the application has data that\r
+ it wants to send. */\r
+#define UIP_CLOSE 16 /* The remote host has closed the\r
+ connection, thus the connection has\r
+ gone away. Or the application signals\r
+ that it wants to close the\r
+ connection. */\r
+#define UIP_ABORT 32 /* The remote host has aborted the\r
+ connection, thus the connection has\r
+ gone away. Or the application signals\r
+ that it wants to abort the\r
+ connection. */\r
+#define UIP_CONNECTED 64 /* We have got a connection from a remote\r
+ host and have set up a new connection\r
+ for it, or an active connection has\r
+ been successfully established. */\r
+\r
+#define UIP_TIMEDOUT 128 /* The connection has been aborted due to\r
+ too many retransmissions. */\r
+\r
+\r
+/* uip_process(flag):\r
+ *\r
+ * The actual uIP function which does all the work.\r
+ */\r
+void uip_process(u8_t flag);\r
+\r
+/* The following flags are passed as an argument to the uip_process()\r
+ function. They are used to distinguish between the two cases where\r
+ uip_process() is called. It can be called either because we have\r
+ incoming data that should be processed, or because the periodic\r
+ timer has fired. */\r
+\r
+#define UIP_DATA 1 /* Tells uIP that there is incoming data in\r
+ the uip_buf buffer. The length of the\r
+ data is stored in the global variable\r
+ uip_len. */\r
+#define UIP_TIMER 2 /* Tells uIP that the periodic timer has\r
+ fired. */\r
+#if UIP_UDP\r
+#define UIP_UDP_TIMER 3\r
+#endif /* UIP_UDP */\r
+\r
+/* The TCP states used in the uip_conn->tcpstateflags. */\r
+#define CLOSED 0\r
+#define SYN_RCVD 1\r
+#define SYN_SENT 2\r
+#define ESTABLISHED 3\r
+#define FIN_WAIT_1 4\r
+#define FIN_WAIT_2 5\r
+#define CLOSING 6\r
+#define TIME_WAIT 7\r
+#define LAST_ACK 8\r
+#define TS_MASK 15\r
+ \r
+#define UIP_STOPPED 16\r
+\r
+#define UIP_TCPIP_HLEN 40\r
+\r
+/* The TCP and IP headers. */\r
+typedef struct {\r
+ /* IP header. */\r
+ u8_t vhl,\r
+ tos, \r
+ len[2], \r
+ ipid[2], \r
+ ipoffset[2], \r
+ ttl, \r
+ proto; \r
+ u16_t ipchksum;\r
+ u16_t srcipaddr[2], \r
+ destipaddr[2];\r
+ \r
+ /* TCP header. */\r
+ u16_t srcport,\r
+ destport;\r
+ u8_t seqno[4], \r
+ ackno[4],\r
+ tcpoffset,\r
+ flags,\r
+ wnd[2]; \r
+ u16_t tcpchksum;\r
+ u8_t urgp[2];\r
+ u8_t optdata[4];\r
+} uip_tcpip_hdr;\r
+\r
+/* The ICMP and IP headers. */\r
+typedef struct {\r
+ /* IP header. */\r
+ u8_t vhl,\r
+ tos, \r
+ len[2], \r
+ ipid[2], \r
+ ipoffset[2], \r
+ ttl, \r
+ proto; \r
+ u16_t ipchksum;\r
+ u16_t srcipaddr[2], \r
+ destipaddr[2];\r
+ /* ICMP (echo) header. */\r
+ u8_t type, icode;\r
+ u16_t icmpchksum;\r
+ u16_t id, seqno; \r
+} uip_icmpip_hdr;\r
+\r
+\r
+/* The UDP and IP headers. */\r
+typedef struct {\r
+ /* IP header. */\r
+ u8_t vhl,\r
+ tos, \r
+ len[2], \r
+ ipid[2], \r
+ ipoffset[2], \r
+ ttl, \r
+ proto; \r
+ u16_t ipchksum;\r
+ u16_t srcipaddr[2], \r
+ destipaddr[2];\r
+ \r
+ /* UDP header. */\r
+ u16_t srcport,\r
+ destport;\r
+ u16_t udplen;\r
+ u16_t udpchksum;\r
+} uip_udpip_hdr;\r
+\r
+#define UIP_PROTO_ICMP 1\r
+#define UIP_PROTO_TCP 6\r
+#define UIP_PROTO_UDP 17\r
+\r
+#if UIP_FIXEDADDR\r
+extern const u16_t uip_hostaddr[2];\r
+#else /* UIP_FIXEDADDR */\r
+extern u16_t uip_hostaddr[2];\r
+#endif /* UIP_FIXEDADDR */\r
+\r
+#endif /* __UIP_H__ */\r
+\r
+\r
+/** @} */\r
+\r
--- /dev/null
+/*\r
+ * Copyright (c) 2001, Adam Dunkels.\r
+ * All rights reserved. \r
+ *\r
+ * Redistribution and use in source and binary forms, with or without \r
+ * modification, are permitted provided that the following conditions \r
+ * are met: \r
+ * 1. Redistributions of source code must retain the above copyright \r
+ * notice, this list of conditions and the following disclaimer. \r
+ * 2. Redistributions in binary form must reproduce the above copyright \r
+ * notice, this list of conditions and the following disclaimer in the \r
+ * documentation and/or other materials provided with the distribution. \r
+ * 3. The name of the author may not be used to endorse or promote\r
+ * products derived from this software without specific prior\r
+ * written permission. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * $Id: uip_arch.c,v 1.2.2.1 2003/10/04 22:54:17 adam Exp $\r
+ *\r
+ */\r
+\r
+\r
+#include "uip.h"\r
+#include "uip_arch.h"\r
+#include <__cross_studio_io.h>\r
+\r
+#define BUF ((uip_tcpip_hdr *)&uip_buf[UIP_LLH_LEN])\r
+#define IP_PROTO_TCP 6\r
+\r
+/*-----------------------------------------------------------------------------------*/\r
+void\r
+uip_add32(u8_t *op32, u16_t op16)\r
+{\r
+ \r
+ uip_acc32[3] = op32[3] + (op16 & 0xff);\r
+ uip_acc32[2] = op32[2] + (op16 >> 8);\r
+ uip_acc32[1] = op32[1];\r
+ uip_acc32[0] = op32[0];\r
+ \r
+ if(uip_acc32[2] < (op16 >> 8)) {\r
+ ++uip_acc32[1]; \r
+ if(uip_acc32[1] == 0) {\r
+ ++uip_acc32[0];\r
+ }\r
+ }\r
+ \r
+ \r
+ if(uip_acc32[3] < (op16 & 0xff)) {\r
+ ++uip_acc32[2]; \r
+ if(uip_acc32[2] == 0) {\r
+ ++uip_acc32[1]; \r
+ if(uip_acc32[1] == 0) {\r
+ ++uip_acc32[0];\r
+ }\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+u16_t\r
+uip_chksum(u16_t *sdata, u16_t len)\r
+{\r
+ u16_t acc;\r
+ \r
+ for (acc = 0; len > 1; len -= 2) {\r
+ u16_t u = ((unsigned char *)sdata)[0] + (((unsigned char *)sdata)[1] << 8);\r
+ if ((acc += u) < u) {\r
+ /* Overflow, so we add the carry to acc (i.e., increase by\r
+ one). */\r
+ ++acc;\r
+ }\r
+ ++sdata;\r
+ }\r
+\r
+ /* add up any odd byte */\r
+ if(len == 1) {\r
+ acc += htons(((u16_t)(*(u8_t *)sdata)) << 8);\r
+ if(acc < htons(((u16_t)(*(u8_t *)sdata)) << 8)) {\r
+ ++acc;\r
+ }\r
+ }\r
+\r
+ return acc;\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+u16_t\r
+uip_ipchksum(void)\r
+{\r
+ return uip_chksum((u16_t *)&uip_buf[UIP_LLH_LEN], 20);\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+u16_t\r
+uip_tcpchksum(void)\r
+{\r
+ u16_t hsum, sum;\r
+\r
+ \r
+ /* Compute the checksum of the TCP header. */\r
+ hsum = uip_chksum((u16_t *)&uip_buf[20 + UIP_LLH_LEN], 20);\r
+\r
+ /* Compute the checksum of the data in the TCP packet and add it to\r
+ the TCP header checksum. */\r
+ sum = uip_chksum((u16_t *)uip_appdata,\r
+ (u16_t)(((((u16_t)(BUF->len[0]) << 8) + BUF->len[1]) - 40)));\r
+\r
+ if((sum += hsum) < hsum) {\r
+ ++sum;\r
+ }\r
+ \r
+ if((sum += BUF->srcipaddr[0]) < BUF->srcipaddr[0]) {\r
+ ++sum;\r
+ }\r
+ if((sum += BUF->srcipaddr[1]) < BUF->srcipaddr[1]) {\r
+ ++sum;\r
+ }\r
+ if((sum += BUF->destipaddr[0]) < BUF->destipaddr[0]) {\r
+ ++sum;\r
+ }\r
+ if((sum += BUF->destipaddr[1]) < BUF->destipaddr[1]) {\r
+ ++sum;\r
+ }\r
+ if((sum += (u16_t)htons((u16_t)IP_PROTO_TCP)) < (u16_t)htons((u16_t)IP_PROTO_TCP)) {\r
+ ++sum;\r
+ }\r
+\r
+ hsum = (u16_t)htons((((u16_t)(BUF->len[0]) << 8) + BUF->len[1]) - 20);\r
+ \r
+ if((sum += hsum) < hsum) {\r
+ ++sum;\r
+ }\r
+\r
+ return sum;\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
--- /dev/null
+/**\r
+ * \defgroup uiparch Architecture specific uIP functions\r
+ * @{\r
+ *\r
+ * The functions in the architecture specific module implement the IP\r
+ * check sum and 32-bit additions.\r
+ *\r
+ * The IP checksum calculation is the most computationally expensive\r
+ * operation in the TCP/IP stack and it therefore pays off to\r
+ * implement this in efficient assembler. The purpose of the uip-arch\r
+ * module is to let the checksum functions to be implemented in\r
+ * architecture specific assembler.\r
+ *\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * Declarations of architecture specific functions.\r
+ * \author Adam Dunkels <adam@dunkels.com>\r
+ */\r
+\r
+/*\r
+ * Copyright (c) 2001, Adam Dunkels.\r
+ * All rights reserved. \r
+ *\r
+ * Redistribution and use in source and binary forms, with or without \r
+ * modification, are permitted provided that the following conditions \r
+ * are met: \r
+ * 1. Redistributions of source code must retain the above copyright \r
+ * notice, this list of conditions and the following disclaimer. \r
+ * 2. Redistributions in binary form must reproduce the above copyright \r
+ * notice, this list of conditions and the following disclaimer in the \r
+ * documentation and/or other materials provided with the distribution. \r
+ * 3. The name of the author may not be used to endorse or promote\r
+ * products derived from this software without specific prior\r
+ * written permission. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * $Id: uip_arch.h,v 1.1.2.2 2003/10/06 15:10:22 adam Exp $\r
+ *\r
+ */\r
+\r
+#ifndef __UIP_ARCH_H__\r
+#define __UIP_ARCH_H__\r
+\r
+#include "uip.h"\r
+\r
+/**\r
+ * Carry out a 32-bit addition.\r
+ *\r
+ * Because not all architectures for which uIP is intended has native\r
+ * 32-bit arithmetic, uIP uses an external C function for doing the\r
+ * required 32-bit additions in the TCP protocol processing. This\r
+ * function should add the two arguments and place the result in the\r
+ * global variable uip_acc32.\r
+ *\r
+ * \note The 32-bit integer pointed to by the op32 parameter and the\r
+ * result in the uip_acc32 variable are in network byte order (big\r
+ * endian).\r
+ *\r
+ * \param op32 A pointer to a 4-byte array representing a 32-bit\r
+ * integer in network byte order (big endian).\r
+ *\r
+ * \param op16 A 16-bit integer in host byte order.\r
+ */\r
+void uip_add32(u8_t *op32, u16_t op16);\r
+\r
+/**\r
+ * Calculate the Internet checksum over a buffer.\r
+ *\r
+ * The Internet checksum is the one's complement of the one's\r
+ * complement sum of all 16-bit words in the buffer.\r
+ *\r
+ * See RFC1071.\r
+ *\r
+ * \note This function is not called in the current version of uIP,\r
+ * but future versions might make use of it.\r
+ *\r
+ * \param buf A pointer to the buffer over which the checksum is to be\r
+ * computed.\r
+ *\r
+ * \param len The length of the buffer over which the checksum is to\r
+ * be computed.\r
+ *\r
+ * \return The Internet checksum of the buffer.\r
+ */\r
+u16_t uip_chksum(u16_t *buf, u16_t len);\r
+\r
+/**\r
+ * Calculate the IP header checksum of the packet header in uip_buf.\r
+ *\r
+ * The IP header checksum is the Internet checksum of the 20 bytes of\r
+ * the IP header.\r
+ *\r
+ * \return The IP header checksum of the IP header in the uip_buf\r
+ * buffer.\r
+ */\r
+u16_t uip_ipchksum(void);\r
+\r
+/**\r
+ * Calculate the TCP checksum of the packet in uip_buf and uip_appdata.\r
+ *\r
+ * The TCP checksum is the Internet checksum of data contents of the\r
+ * TCP segment, and a pseudo-header as defined in RFC793.\r
+ *\r
+ * \note The uip_appdata pointer that points to the packet data may\r
+ * point anywhere in memory, so it is not possible to simply calculate\r
+ * the Internet checksum of the contents of the uip_buf buffer.\r
+ *\r
+ * \return The TCP checksum of the TCP segment in uip_buf and pointed\r
+ * to by uip_appdata.\r
+ */\r
+u16_t uip_tcpchksum(void);\r
+\r
+/** @} */\r
+\r
+#endif /* __UIP_ARCH_H__ */\r
--- /dev/null
+/**\r
+ * \addtogroup uip\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \defgroup uiparp uIP Address Resolution Protocol\r
+ * @{\r
+ * \r
+ * The Address Resolution Protocol ARP is used for mapping between IP\r
+ * addresses and link level addresses such as the Ethernet MAC\r
+ * addresses. ARP uses broadcast queries to ask for the link level\r
+ * address of a known IP address and the host which is configured with\r
+ * the IP address for which the query was meant, will respond with its\r
+ * link level address.\r
+ *\r
+ * \note This ARP implementation only supports Ethernet.\r
+ */\r
+ \r
+/**\r
+ * \file\r
+ * Implementation of the ARP Address Resolution Protocol.\r
+ * \author Adam Dunkels <adam@dunkels.com>\r
+ *\r
+ */\r
+\r
+/*\r
+ * Copyright (c) 2001-2003, Adam Dunkels.\r
+ * All rights reserved. \r
+ *\r
+ * Redistribution and use in source and binary forms, with or without \r
+ * modification, are permitted provided that the following conditions \r
+ * are met: \r
+ * 1. Redistributions of source code must retain the above copyright \r
+ * notice, this list of conditions and the following disclaimer. \r
+ * 2. Redistributions in binary form must reproduce the above copyright \r
+ * notice, this list of conditions and the following disclaimer in the \r
+ * documentation and/or other materials provided with the distribution. \r
+ * 3. The name of the author may not be used to endorse or promote\r
+ * products derived from this software without specific prior\r
+ * written permission. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * $Id: uip_arp.c,v 1.7.2.3 2003/10/06 22:42:30 adam Exp $\r
+ *\r
+ */\r
+\r
+\r
+#include "uip_arp.h"\r
+\r
+#include <string.h>\r
+\r
+struct arp_hdr {\r
+ struct uip_eth_hdr ethhdr;\r
+ u16_t hwtype;\r
+ u16_t protocol;\r
+ u8_t hwlen;\r
+ u8_t protolen;\r
+ u16_t opcode;\r
+ struct uip_eth_addr shwaddr;\r
+ u16_t sipaddr[2];\r
+ struct uip_eth_addr dhwaddr;\r
+ u16_t dipaddr[2]; \r
+};\r
+\r
+struct ethip_hdr {\r
+ struct uip_eth_hdr ethhdr;\r
+ /* IP header. */\r
+ u8_t vhl,\r
+ tos, \r
+ len[2], \r
+ ipid[2], \r
+ ipoffset[2], \r
+ ttl, \r
+ proto; \r
+ u16_t ipchksum;\r
+ u16_t srcipaddr[2], \r
+ destipaddr[2];\r
+};\r
+\r
+#define ARP_REQUEST 1\r
+#define ARP_REPLY 2\r
+\r
+#define ARP_HWTYPE_ETH 1\r
+\r
+struct arp_entry {\r
+ u16_t ipaddr[2];\r
+ struct uip_eth_addr ethaddr;\r
+ u8_t time;\r
+};\r
+\r
+struct uip_eth_addr uip_ethaddr = {{UIP_ETHADDR0,\r
+ UIP_ETHADDR1,\r
+ UIP_ETHADDR2,\r
+ UIP_ETHADDR3,\r
+ UIP_ETHADDR4,\r
+ UIP_ETHADDR5}};\r
+\r
+static struct arp_entry arp_table[UIP_ARPTAB_SIZE];\r
+static u16_t ipaddr[2];\r
+static u8_t i, c;\r
+\r
+static u8_t arptime;\r
+static u8_t tmpage;\r
+\r
+#define BUF ((struct arp_hdr *)&uip_buf[0])\r
+#define IPBUF ((struct ethip_hdr *)&uip_buf[0])\r
+/*-----------------------------------------------------------------------------------*/\r
+/**\r
+ * Initialize the ARP module.\r
+ *\r
+ */\r
+/*-----------------------------------------------------------------------------------*/\r
+void\r
+uip_arp_init(void)\r
+{\r
+ for(i = 0; i < UIP_ARPTAB_SIZE; ++i) {\r
+ memset(arp_table[i].ipaddr, 0, 4);\r
+ }\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+/**\r
+ * Periodic ARP processing function.\r
+ *\r
+ * This function performs periodic timer processing in the ARP module\r
+ * and should be called at regular intervals. The recommended interval\r
+ * is 10 seconds between the calls.\r
+ *\r
+ */\r
+/*-----------------------------------------------------------------------------------*/\r
+void\r
+uip_arp_timer(void)\r
+{\r
+ struct arp_entry *tabptr;\r
+ \r
+ ++arptime;\r
+ for(i = 0; i < UIP_ARPTAB_SIZE; ++i) {\r
+ tabptr = &arp_table[i];\r
+ if((tabptr->ipaddr[0] | tabptr->ipaddr[1]) != 0 &&\r
+ arptime - tabptr->time >= UIP_ARP_MAXAGE) {\r
+ memset(tabptr->ipaddr, 0, 4);\r
+ }\r
+ }\r
+\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+static void\r
+uip_arp_update(u16_t *ipaddr, struct uip_eth_addr *ethaddr)\r
+{\r
+ register struct arp_entry *tabptr;\r
+ /* Walk through the ARP mapping table and try to find an entry to\r
+ update. If none is found, the IP -> MAC address mapping is\r
+ inserted in the ARP table. */\r
+ for(i = 0; i < UIP_ARPTAB_SIZE; ++i) {\r
+\r
+ tabptr = &arp_table[i];\r
+ /* Only check those entries that are actually in use. */\r
+ if(tabptr->ipaddr[0] != 0 &&\r
+ tabptr->ipaddr[1] != 0) {\r
+\r
+ /* Check if the source IP address of the incoming packet matches\r
+ the IP address in this ARP table entry. */\r
+ if(ipaddr[0] == tabptr->ipaddr[0] &&\r
+ ipaddr[1] == tabptr->ipaddr[1]) {\r
+ \r
+ /* An old entry found, update this and return. */\r
+ memcpy(tabptr->ethaddr.addr, ethaddr->addr, 6);\r
+ tabptr->time = arptime;\r
+\r
+ return;\r
+ }\r
+ }\r
+ }\r
+\r
+ /* If we get here, no existing ARP table entry was found, so we\r
+ create one. */\r
+\r
+ /* First, we try to find an unused entry in the ARP table. */\r
+ for(i = 0; i < UIP_ARPTAB_SIZE; ++i) {\r
+ tabptr = &arp_table[i];\r
+ if(tabptr->ipaddr[0] == 0 &&\r
+ tabptr->ipaddr[1] == 0) {\r
+ break;\r
+ }\r
+ }\r
+\r
+ /* If no unused entry is found, we try to find the oldest entry and\r
+ throw it away. */\r
+ if(i == UIP_ARPTAB_SIZE) {\r
+ tmpage = 0;\r
+ c = 0;\r
+ for(i = 0; i < UIP_ARPTAB_SIZE; ++i) {\r
+ tabptr = &arp_table[i];\r
+ if(arptime - tabptr->time > tmpage) {\r
+ tmpage = arptime - tabptr->time;\r
+ c = i;\r
+ }\r
+ }\r
+ i = c;\r
+ }\r
+\r
+ /* Now, i is the ARP table entry which we will fill with the new\r
+ information. */\r
+ memcpy(tabptr->ipaddr, ipaddr, 4);\r
+ memcpy(tabptr->ethaddr.addr, ethaddr->addr, 6);\r
+ tabptr->time = arptime;\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+/**\r
+ * ARP processing for incoming IP packets\r
+ *\r
+ * This function should be called by the device driver when an IP\r
+ * packet has been received. The function will check if the address is\r
+ * in the ARP cache, and if so the ARP cache entry will be\r
+ * refreshed. If no ARP cache entry was found, a new one is created.\r
+ *\r
+ * This function expects an IP packet with a prepended Ethernet header\r
+ * in the uip_buf[] buffer, and the length of the packet in the global\r
+ * variable uip_len.\r
+ */\r
+/*-----------------------------------------------------------------------------------*/\r
+void\r
+uip_arp_ipin(void)\r
+{\r
+ uip_len -= sizeof(struct uip_eth_hdr);\r
+ \r
+ /* Only insert/update an entry if the source IP address of the\r
+ incoming IP packet comes from a host on the local network. */\r
+ if((IPBUF->srcipaddr[0] & uip_arp_netmask[0]) !=\r
+ (uip_hostaddr[0] & uip_arp_netmask[0])) {\r
+ return;\r
+ }\r
+ if((IPBUF->srcipaddr[1] & uip_arp_netmask[1]) !=\r
+ (uip_hostaddr[1] & uip_arp_netmask[1])) {\r
+ return;\r
+ }\r
+ uip_arp_update(IPBUF->srcipaddr, &(IPBUF->ethhdr.src));\r
+ \r
+ return;\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+/**\r
+ * ARP processing for incoming ARP packets.\r
+ *\r
+ * This function should be called by the device driver when an ARP\r
+ * packet has been received. The function will act differently\r
+ * depending on the ARP packet type: if it is a reply for a request\r
+ * that we previously sent out, the ARP cache will be filled in with\r
+ * the values from the ARP reply. If the incoming ARP packet is an ARP\r
+ * request for our IP address, an ARP reply packet is created and put\r
+ * into the uip_buf[] buffer.\r
+ *\r
+ * When the function returns, the value of the global variable uip_len\r
+ * indicates whether the device driver should send out a packet or\r
+ * not. If uip_len is zero, no packet should be sent. If uip_len is\r
+ * non-zero, it contains the length of the outbound packet that is\r
+ * present in the uip_buf[] buffer.\r
+ *\r
+ * This function expects an ARP packet with a prepended Ethernet\r
+ * header in the uip_buf[] buffer, and the length of the packet in the\r
+ * global variable uip_len.\r
+ */\r
+/*-----------------------------------------------------------------------------------*/\r
+typedef struct arp_hdr aht;\r
+\r
+void\r
+uip_arp_arpin(void)\r
+{\r
+ int ul;\r
+\r
+ if(uip_len < sizeof(struct arp_hdr)) {\r
+ uip_len = 0;\r
+ return;\r
+ }\r
+\r
+ uip_len = 0;\r
+ \r
+ switch(BUF->opcode) {\r
+ case HTONS(ARP_REQUEST):\r
+ /* ARP request. If it asked for our address, we send out a\r
+ reply. */\r
+ if(BUF->dipaddr[0] == uip_hostaddr[0] &&\r
+ BUF->dipaddr[1] == uip_hostaddr[1]) {\r
+ /* The reply opcode is 2. */\r
+ BUF->opcode = HTONS(2);\r
+\r
+ memcpy(BUF->dhwaddr.addr, BUF->shwaddr.addr, 6);\r
+ memcpy(BUF->shwaddr.addr, uip_ethaddr.addr, 6);\r
+ memcpy(BUF->ethhdr.src.addr, uip_ethaddr.addr, 6);\r
+ memcpy(BUF->ethhdr.dest.addr, BUF->dhwaddr.addr, 6);\r
+ \r
+ BUF->dipaddr[0] = BUF->sipaddr[0];\r
+ BUF->dipaddr[1] = BUF->sipaddr[1];\r
+ BUF->sipaddr[0] = uip_hostaddr[0];\r
+ BUF->sipaddr[1] = uip_hostaddr[1];\r
+\r
+ ul = BUF->hwlen;\r
+ BUF->ethhdr.type = HTONS(UIP_ETHTYPE_ARP); \r
+ uip_len = sizeof(struct arp_hdr);\r
+ } \r
+ break;\r
+ case HTONS(ARP_REPLY):\r
+ /* ARP reply. We insert or update the ARP table if it was meant\r
+ for us. */\r
+ if(BUF->dipaddr[0] == uip_hostaddr[0] &&\r
+ BUF->dipaddr[1] == uip_hostaddr[1]) {\r
+\r
+ uip_arp_update(BUF->sipaddr, &BUF->shwaddr);\r
+ }\r
+ break;\r
+ }\r
+\r
+ return;\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+/**\r
+ * Prepend Ethernet header to an outbound IP packet and see if we need\r
+ * to send out an ARP request.\r
+ *\r
+ * This function should be called before sending out an IP packet. The\r
+ * function checks the destination IP address of the IP packet to see\r
+ * what Ethernet MAC address that should be used as a destination MAC\r
+ * address on the Ethernet.\r
+ *\r
+ * If the destination IP address is in the local network (determined\r
+ * by logical ANDing of netmask and our IP address), the function\r
+ * checks the ARP cache to see if an entry for the destination IP\r
+ * address is found. If so, an Ethernet header is prepended and the\r
+ * function returns. If no ARP cache entry is found for the\r
+ * destination IP address, the packet in the uip_buf[] is replaced by\r
+ * an ARP request packet for the IP address. The IP packet is dropped\r
+ * and it is assumed that they higher level protocols (e.g., TCP)\r
+ * eventually will retransmit the dropped packet.\r
+ *\r
+ * If the destination IP address is not on the local network, the IP\r
+ * address of the default router is used instead.\r
+ *\r
+ * When the function returns, a packet is present in the uip_buf[]\r
+ * buffer, and the length of the packet is in the global variable\r
+ * uip_len.\r
+ */\r
+/*-----------------------------------------------------------------------------------*/\r
+void\r
+uip_arp_out(void)\r
+{\r
+ struct arp_entry *tabptr;\r
+ /* Find the destination IP address in the ARP table and construct\r
+ the Ethernet header. If the destination IP addres isn't on the\r
+ local network, we use the default router's IP address instead.\r
+\r
+ If not ARP table entry is found, we overwrite the original IP\r
+ packet with an ARP request for the IP address. */\r
+\r
+ /* Check if the destination address is on the local network. */\r
+ if((IPBUF->destipaddr[0] & uip_arp_netmask[0]) !=\r
+ (uip_hostaddr[0] & uip_arp_netmask[0]) ||\r
+ (IPBUF->destipaddr[1] & uip_arp_netmask[1]) !=\r
+ (uip_hostaddr[1] & uip_arp_netmask[1])) {\r
+ /* Destination address was not on the local network, so we need to\r
+ use the default router's IP address instead of the destination\r
+ address when determining the MAC address. */\r
+ ipaddr[0] = uip_arp_draddr[0];\r
+ ipaddr[1] = uip_arp_draddr[1];\r
+ } else {\r
+ /* Else, we use the destination IP address. */\r
+ ipaddr[0] = IPBUF->destipaddr[0];\r
+ ipaddr[1] = IPBUF->destipaddr[1];\r
+ }\r
+ \r
+ for(i = 0; i < UIP_ARPTAB_SIZE; ++i) {\r
+ tabptr = &arp_table[i];\r
+ if(ipaddr[0] == tabptr->ipaddr[0] &&\r
+ ipaddr[1] == tabptr->ipaddr[1])\r
+ break;\r
+ }\r
+\r
+ if(i == UIP_ARPTAB_SIZE) {\r
+ /* The destination address was not in our ARP table, so we\r
+ overwrite the IP packet with an ARP request. */\r
+\r
+ memset(BUF->ethhdr.dest.addr, 0xff, 6);\r
+ memset(BUF->dhwaddr.addr, 0x00, 6);\r
+ memcpy(BUF->ethhdr.src.addr, uip_ethaddr.addr, 6);\r
+ memcpy(BUF->shwaddr.addr, uip_ethaddr.addr, 6);\r
+ \r
+ BUF->dipaddr[0] = ipaddr[0];\r
+ BUF->dipaddr[1] = ipaddr[1];\r
+ BUF->sipaddr[0] = uip_hostaddr[0];\r
+ BUF->sipaddr[1] = uip_hostaddr[1];\r
+ BUF->opcode = HTONS(ARP_REQUEST); /* ARP request. */\r
+ BUF->hwtype = HTONS(ARP_HWTYPE_ETH);\r
+ BUF->protocol = HTONS(UIP_ETHTYPE_IP);\r
+ BUF->hwlen = 6;\r
+ BUF->protolen = 4;\r
+ BUF->ethhdr.type = HTONS(UIP_ETHTYPE_ARP);\r
+\r
+ uip_appdata = &uip_buf[40 + UIP_LLH_LEN];\r
+ \r
+ uip_len = sizeof(struct arp_hdr);\r
+ return;\r
+ }\r
+\r
+ /* Build an ethernet header. */\r
+ memcpy(IPBUF->ethhdr.dest.addr, tabptr->ethaddr.addr, 6);\r
+ memcpy(IPBUF->ethhdr.src.addr, uip_ethaddr.addr, 6);\r
+ \r
+ IPBUF->ethhdr.type = HTONS(UIP_ETHTYPE_IP);\r
+\r
+ uip_len += sizeof(struct uip_eth_hdr);\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+\r
+/** @} */\r
+/** @} */\r
--- /dev/null
+/**\r
+ * \addtogroup uip\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \addtogroup uiparp \r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * \file\r
+ * Macros and definitions for the ARP module.\r
+ * \author Adam Dunkels <adam@dunkels.com>\r
+ */\r
+ \r
+\r
+/*\r
+ * Copyright (c) 2001-2003, Adam Dunkels.\r
+ * All rights reserved. \r
+ *\r
+ * Redistribution and use in source and binary forms, with or without \r
+ * modification, are permitted provided that the following conditions \r
+ * are met: \r
+ * 1. Redistributions of source code must retain the above copyright \r
+ * notice, this list of conditions and the following disclaimer. \r
+ * 2. Redistributions in binary form must reproduce the above copyright \r
+ * notice, this list of conditions and the following disclaimer in the \r
+ * documentation and/or other materials provided with the distribution. \r
+ * 3. The name of the author may not be used to endorse or promote\r
+ * products derived from this software without specific prior\r
+ * written permission. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * $Id: uip_arp.h,v 1.3.2.2 2003/10/06 15:10:22 adam Exp $\r
+ *\r
+ */\r
+\r
+#ifndef __UIP_ARP_H__\r
+#define __UIP_ARP_H__\r
+\r
+#include "uip.h"\r
+\r
+\r
+/**\r
+ * Representation of a 48-bit Ethernet address.\r
+ */\r
+struct uip_eth_addr {\r
+ u8_t addr[6];\r
+} __attribute__ ((packed, aligned (1)));\r
+\r
+extern struct uip_eth_addr uip_ethaddr;\r
+\r
+/**\r
+ * The Ethernet header. \r
+ */\r
+struct uip_eth_hdr {\r
+ struct uip_eth_addr dest;\r
+ struct uip_eth_addr src;\r
+ u16_t type;\r
+} __attribute__ ((packed));\r
+\r
+#define UIP_ETHTYPE_ARP 0x0806\r
+#define UIP_ETHTYPE_IP 0x0800\r
+#define UIP_ETHTYPE_IP6 0x86dd \r
+\r
+\r
+/* The uip_arp_init() function must be called before any of the other\r
+ ARP functions. */\r
+void uip_arp_init(void);\r
+\r
+/* The uip_arp_ipin() function should be called whenever an IP packet\r
+ arrives from the Ethernet. This function refreshes the ARP table or\r
+ inserts a new mapping if none exists. The function assumes that an\r
+ IP packet with an Ethernet header is present in the uip_buf buffer\r
+ and that the length of the packet is in the uip_len variable. */\r
+void uip_arp_ipin(void);\r
+\r
+/* The uip_arp_arpin() should be called when an ARP packet is received\r
+ by the Ethernet driver. This function also assumes that the\r
+ Ethernet frame is present in the uip_buf buffer. When the\r
+ uip_arp_arpin() function returns, the contents of the uip_buf\r
+ buffer should be sent out on the Ethernet if the uip_len variable\r
+ is > 0. */\r
+void uip_arp_arpin(void);\r
+\r
+/* The uip_arp_out() function should be called when an IP packet\r
+ should be sent out on the Ethernet. This function creates an\r
+ Ethernet header before the IP header in the uip_buf buffer. The\r
+ Ethernet header will have the correct Ethernet MAC destination\r
+ address filled in if an ARP table entry for the destination IP\r
+ address (or the IP address of the default router) is present. If no\r
+ such table entry is found, the IP packet is overwritten with an ARP\r
+ request and we rely on TCP to retransmit the packet that was\r
+ overwritten. In any case, the uip_len variable holds the length of\r
+ the Ethernet frame that should be transmitted. */\r
+void uip_arp_out(void);\r
+\r
+/* The uip_arp_timer() function should be called every ten seconds. It\r
+ is responsible for flushing old entries in the ARP table. */\r
+void uip_arp_timer(void);\r
+\r
+/** @} */\r
+\r
+/**\r
+ * \addtogroup uipconffunc\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * Set the default router's IP address.\r
+ *\r
+ * \param addr A pointer to a 4-byte array containing the IP address\r
+ * of the default router.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_setdraddr(addr) do { uip_arp_draddr[0] = addr[0]; \\r
+ uip_arp_draddr[1] = addr[1]; } while(0)\r
+\r
+/**\r
+ * Set the netmask.\r
+ *\r
+ * \param addr A pointer to a 4-byte array containing the IP address\r
+ * of the netmask.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_setnetmask(addr) do { uip_arp_netmask[0] = addr[0]; \\r
+ uip_arp_netmask[1] = addr[1]; } while(0)\r
+\r
+\r
+/**\r
+ * Get the default router's IP address.\r
+ *\r
+ * \param addr A pointer to a 4-byte array that will be filled in with\r
+ * the IP address of the default router.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_getdraddr(addr) do { addr[0] = uip_arp_draddr[0]; \\r
+ addr[1] = uip_arp_draddr[1]; } while(0)\r
+\r
+/**\r
+ * Get the netmask.\r
+ *\r
+ * \param addr A pointer to a 4-byte array that will be filled in with\r
+ * the value of the netmask.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_getnetmask(addr) do { addr[0] = uip_arp_netmask[0]; \\r
+ addr[1] = uip_arp_netmask[1]; } while(0)\r
+\r
+\r
+/**\r
+ * Specifiy the Ethernet MAC address.\r
+ *\r
+ * The ARP code needs to know the MAC address of the Ethernet card in\r
+ * order to be able to respond to ARP queries and to generate working\r
+ * Ethernet headers.\r
+ *\r
+ * \note This macro only specifies the Ethernet MAC address to the ARP\r
+ * code. It cannot be used to change the MAC address of the Ethernet\r
+ * card.\r
+ *\r
+ * \param eaddr A pointer to a struct uip_eth_addr containing the\r
+ * Ethernet MAC address of the Ethernet card.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define uip_setethaddr(eaddr) do {uip_ethaddr.addr[0] = eaddr.addr[0]; \\r
+ uip_ethaddr.addr[1] = eaddr.addr[1];\\r
+ uip_ethaddr.addr[2] = eaddr.addr[2];\\r
+ uip_ethaddr.addr[3] = eaddr.addr[3];\\r
+ uip_ethaddr.addr[4] = eaddr.addr[4];\\r
+ uip_ethaddr.addr[5] = eaddr.addr[5];} while(0)\r
+\r
+/** @} */\r
+\r
+/**\r
+ * \internal Internal variables that are set using the macros\r
+ * uip_setdraddr and uip_setnetmask.\r
+ */\r
+extern u16_t uip_arp_draddr[2], uip_arp_netmask[2];\r
+#endif /* __UIP_ARP_H__ */\r
+\r
+\r
--- /dev/null
+/**\r
+ * \defgroup uipopt Configuration options for uIP\r
+ * @{\r
+ *\r
+ * uIP is configured using the per-project configuration file\r
+ * "uipopt.h". This file contains all compile-time options for uIP and\r
+ * should be tweaked to match each specific project. The uIP\r
+ * distribution contains a documented example "uipopt.h" that can be\r
+ * copied and modified for each project.\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * Configuration options for uIP.\r
+ * \author Adam Dunkels <adam@dunkels.com>\r
+ *\r
+ * This file is used for tweaking various configuration options for\r
+ * uIP. You should make a copy of this file into one of your project's\r
+ * directories instead of editing this example "uipopt.h" file that\r
+ * comes with the uIP distribution.\r
+ */\r
+\r
+/*\r
+ * Copyright (c) 2001-2003, Adam Dunkels.\r
+ * All rights reserved. \r
+ *\r
+ * Redistribution and use in source and binary forms, with or without \r
+ * modification, are permitted provided that the following conditions \r
+ * are met: \r
+ * 1. Redistributions of source code must retain the above copyright \r
+ * notice, this list of conditions and the following disclaimer. \r
+ * 2. Redistributions in binary form must reproduce the above copyright \r
+ * notice, this list of conditions and the following disclaimer in the \r
+ * documentation and/or other materials provided with the distribution. \r
+ * 3. The name of the author may not be used to endorse or promote\r
+ * products derived from this software without specific prior\r
+ * written permission. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * $Id: uipopt.h,v 1.16.2.5 2003/10/07 13:22:51 adam Exp $\r
+ *\r
+ */\r
+\r
+#ifndef __UIPOPT_H__\r
+#define __UIPOPT_H__\r
+\r
+/*------------------------------------------------------------------------------*/\r
+/**\r
+ * \defgroup uipopttypedef uIP type definitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * The 8-bit unsigned data type.\r
+ *\r
+ * This may have to be tweaked for your particular compiler. "unsigned\r
+ * char" works for most compilers.\r
+ */\r
+typedef unsigned char u8_t;\r
+\r
+/**\r
+ * The 16-bit unsigned data type.\r
+ *\r
+ * This may have to be tweaked for your particular compiler. "unsigned\r
+ * short" works for most compilers.\r
+ */\r
+typedef unsigned short u16_t;\r
+\r
+/**\r
+ * The statistics data type.\r
+ *\r
+ * This datatype determines how high the statistics counters are able\r
+ * to count.\r
+ */\r
+typedef unsigned short uip_stats_t;\r
+\r
+/** @} */\r
+\r
+/*------------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \defgroup uipoptstaticconf Static configuration options\r
+ * @{\r
+ *\r
+ * These configuration options can be used for setting the IP address\r
+ * settings statically, but only if UIP_FIXEDADDR is set to 1. The\r
+ * configuration options for a specific node includes IP address,\r
+ * netmask and default router as well as the Ethernet address. The\r
+ * netmask, default router and Ethernet address are appliciable only\r
+ * if uIP should be run over Ethernet.\r
+ *\r
+ * All of these should be changed to suit your project.\r
+*/\r
+\r
+/**\r
+ * Determines if uIP should use a fixed IP address or not.\r
+ *\r
+ * If uIP should use a fixed IP address, the settings are set in the\r
+ * uipopt.h file. If not, the macros uip_sethostaddr(),\r
+ * uip_setdraddr() and uip_setnetmask() should be used instead.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_FIXEDADDR 1\r
+\r
+/**\r
+ * Ping IP address asignment.\r
+ *\r
+ * uIP uses a "ping" packets for setting its own IP address if this\r
+ * option is set. If so, uIP will start with an empty IP address and\r
+ * the destination IP address of the first incoming "ping" (ICMP echo)\r
+ * packet will be used for setting the hosts IP address.\r
+ *\r
+ * \note This works only if UIP_FIXEDADDR is 0.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_PINGADDRCONF 0\r
+\r
+#if 0\r
+#define UIP_IPADDR0 172U /**< The first octet of the IP address of\r
+ this uIP node, if UIP_FIXEDADDR is\r
+ 1. \hideinitializer */\r
+#define UIP_IPADDR1 25U /**< The second octet of the IP address of\r
+ this uIP node, if UIP_FIXEDADDR is\r
+ 1. \hideinitializer */\r
+#define UIP_IPADDR2 218U /**< The third octet of the IP address of\r
+ this uIP node, if UIP_FIXEDADDR is\r
+ 1. \hideinitializer */\r
+#define UIP_IPADDR3 202U /**< The fourth octet of the IP address of\r
+ this uIP node, if UIP_FIXEDADDR is\r
+ 1. \hideinitializer */\r
+\r
+#define UIP_NETMASK0 255 /**< The first octet of the netmask of\r
+ this uIP node, if UIP_FIXEDADDR is\r
+ 1. \hideinitializer */\r
+#define UIP_NETMASK1 255 /**< The second octet of the netmask of\r
+ this uIP node, if UIP_FIXEDADDR is\r
+ 1. \hideinitializer */\r
+#define UIP_NETMASK2 255 /**< The third octet of the netmask of\r
+ this uIP node, if UIP_FIXEDADDR is\r
+ 1. \hideinitializer */\r
+#define UIP_NETMASK3 0 /**< The fourth octet of the netmask of\r
+ this uIP node, if UIP_FIXEDADDR is\r
+ 1. \hideinitializer */\r
+\r
+\r
+#define UIP_DRIPADDR0 192 /**< The first octet of the IP address of\r
+ the default router, if UIP_FIXEDADDR is\r
+ 1. \hideinitializer */\r
+#define UIP_DRIPADDR1 168 /**< The second octet of the IP address of\r
+ the default router, if UIP_FIXEDADDR is\r
+ 1. \hideinitializer */\r
+#define UIP_DRIPADDR2 0 /**< The third octet of the IP address of\r
+ the default router, if UIP_FIXEDADDR is\r
+ 1. \hideinitializer */\r
+#define UIP_DRIPADDR3 1 /**< The fourth octet of the IP address of\r
+ the default router, if UIP_FIXEDADDR is\r
+ 1. \hideinitializer */\r
+\r
+#else\r
+\r
+#define UIP_IPADDR0 172U /**< The first octet of the IP address of\r
+ this uIP node, if UIP_FIXEDADDR is\r
+ 1. \hideinitializer */\r
+#define UIP_IPADDR1 25U /**< The second octet of the IP address of\r
+ this uIP node, if UIP_FIXEDADDR is\r
+ 1. \hideinitializer */\r
+#define UIP_IPADDR2 218U /**< The third octet of the IP address of\r
+ this uIP node, if UIP_FIXEDADDR is\r
+ 1. \hideinitializer */\r
+#define UIP_IPADDR3 202U /**< The fourth octet of the IP address of\r
+ this uIP node, if UIP_FIXEDADDR is\r
+ 1. \hideinitializer */\r
+\r
+#define UIP_NETMASK0 255 /**< The first octet of the netmask of\r
+ this uIP node, if UIP_FIXEDADDR is\r
+ 1. \hideinitializer */\r
+#define UIP_NETMASK1 255 /**< The second octet of the netmask of\r
+ this uIP node, if UIP_FIXEDADDR is\r
+ 1. \hideinitializer */\r
+#define UIP_NETMASK2 255 /**< The third octet of the netmask of\r
+ this uIP node, if UIP_FIXEDADDR is\r
+ 1. \hideinitializer */\r
+#define UIP_NETMASK3 0 /**< The fourth octet of the netmask of\r
+ this uIP node, if UIP_FIXEDADDR is\r
+ 1. \hideinitializer */\r
+\r
+#define UIP_DRIPADDR0 172 /**< The first octet of the IP address of\r
+ the default router, if UIP_FIXEDADDR is\r
+ 1. \hideinitializer */\r
+#define UIP_DRIPADDR1 25 /**< The second octet of the IP address of\r
+ the default router, if UIP_FIXEDADDR is\r
+ 1. \hideinitializer */\r
+#define UIP_DRIPADDR2 218 /**< The third octet of the IP address of\r
+ the default router, if UIP_FIXEDADDR is\r
+ 1. \hideinitializer */\r
+#define UIP_DRIPADDR3 3 /**< The fourth octet of the IP address of\r
+ the default router, if UIP_FIXEDADDR is\r
+ 1. \hideinitializer */\r
+\r
+#endif\r
+\r
+/**\r
+ * Specifies if the uIP ARP module should be compiled with a fixed\r
+ * Ethernet MAC address or not.\r
+ *\r
+ * If this configuration option is 0, the macro uip_setethaddr() can\r
+ * be used to specify the Ethernet address at run-time.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_FIXEDETHADDR 0\r
+\r
+#define UIP_ETHADDR0 0x00 /**< The first octet of the Ethernet\r
+ address if UIP_FIXEDETHADDR is\r
+ 1. \hideinitializer */\r
+#define UIP_ETHADDR1 0xbd /**< The second octet of the Ethernet\r
+ address if UIP_FIXEDETHADDR is\r
+ 1. \hideinitializer */\r
+#define UIP_ETHADDR2 0x3b /**< The third octet of the Ethernet\r
+ address if UIP_FIXEDETHADDR is\r
+ 1. \hideinitializer */\r
+#define UIP_ETHADDR3 0x33 /**< The fourth octet of the Ethernet\r
+ address if UIP_FIXEDETHADDR is\r
+ 1. \hideinitializer */\r
+#define UIP_ETHADDR4 0x05 /**< The fifth octet of the Ethernet\r
+ address if UIP_FIXEDETHADDR is\r
+ 1. \hideinitializer */\r
+#define UIP_ETHADDR5 0x71 /**< The sixth octet of the Ethernet\r
+ address if UIP_FIXEDETHADDR is\r
+ 1. \hideinitializer */\r
+\r
+/** @} */\r
+/*------------------------------------------------------------------------------*/\r
+/**\r
+ * \defgroup uipoptip IP configuration options\r
+ * @{\r
+ *\r
+ */\r
+/**\r
+ * The IP TTL (time to live) of IP packets sent by uIP.\r
+ *\r
+ * This should normally not be changed.\r
+ */\r
+#define UIP_TTL 255\r
+\r
+/**\r
+ * Turn on support for IP packet reassembly.\r
+ *\r
+ * uIP supports reassembly of fragmented IP packets. This features\r
+ * requires an additonal amount of RAM to hold the reassembly buffer\r
+ * and the reassembly code size is approximately 700 bytes. The\r
+ * reassembly buffer is of the same size as the uip_buf buffer\r
+ * (configured by UIP_BUFSIZE).\r
+ *\r
+ * \note IP packet reassembly is not heavily tested.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_REASSEMBLY 0\r
+\r
+/**\r
+ * The maximum time an IP fragment should wait in the reassembly\r
+ * buffer before it is dropped.\r
+ *\r
+ */\r
+#define UIP_REASS_MAXAGE 40\r
+\r
+/** @} */\r
+\r
+/*------------------------------------------------------------------------------*/\r
+/**\r
+ * \defgroup uipoptudp UDP configuration options\r
+ * @{\r
+ *\r
+ * \note The UDP support in uIP is still not entirely complete; there\r
+ * is no support for sending or receiving broadcast or multicast\r
+ * packets, but it works well enough to support a number of vital\r
+ * applications such as DNS queries, though\r
+ */\r
+\r
+/**\r
+ * Toggles wether UDP support should be compiled in or not.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_UDP 0\r
+\r
+/**\r
+ * Toggles if UDP checksums should be used or not.\r
+ *\r
+ * \note Support for UDP checksums is currently not included in uIP,\r
+ * so this option has no function.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_UDP_CHECKSUMS 0\r
+\r
+/**\r
+ * The maximum amount of concurrent UDP connections.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_UDP_CONNS 2\r
+\r
+/**\r
+ * The name of the function that should be called when UDP datagrams arrive.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_UDP_APPCALL udp_appcall\r
+\r
+/** @} */\r
+/*------------------------------------------------------------------------------*/\r
+/**\r
+ * \defgroup uipopttcp TCP configuration options\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * Determines if support for opening connections from uIP should be\r
+ * compiled in.\r
+ *\r
+ * If the applications that are running on top of uIP for this project\r
+ * do not need to open outgoing TCP connections, this configration\r
+ * option can be turned off to reduce the code size of uIP.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_ACTIVE_OPEN 1\r
+\r
+/**\r
+ * The maximum number of simultaneously open TCP connections.\r
+ *\r
+ * Since the TCP connections are statically allocated, turning this\r
+ * configuration knob down results in less RAM used. Each TCP\r
+ * connection requires approximatly 30 bytes of memory.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_CONNS 20\r
+\r
+/**\r
+ * The maximum number of simultaneously listening TCP ports.\r
+ *\r
+ * Each listening TCP port requires 2 bytes of memory.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_LISTENPORTS 10\r
+\r
+/**\r
+ * The size of the advertised receiver's window.\r
+ *\r
+ * Should be set low (i.e., to the size of the uip_buf buffer) is the\r
+ * application is slow to process incoming data, or high (32768 bytes)\r
+ * if the application processes data quickly.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_RECEIVE_WINDOW 32768\r
+\r
+/**\r
+ * Determines if support for TCP urgent data notification should be\r
+ * compiled in.\r
+ *\r
+ * Urgent data (out-of-band data) is a rarely used TCP feature that\r
+ * very seldom would be required.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_URGDATA 1\r
+\r
+/**\r
+ * The initial retransmission timeout counted in timer pulses.\r
+ *\r
+ * This should not be changed.\r
+ */\r
+#define UIP_RTO 3\r
+\r
+/**\r
+ * The maximum number of times a segment should be retransmitted\r
+ * before the connection should be aborted.\r
+ *\r
+ * This should not be changed.\r
+ */\r
+#define UIP_MAXRTX 8\r
+\r
+/**\r
+ * The maximum number of times a SYN segment should be retransmitted\r
+ * before a connection request should be deemed to have been\r
+ * unsuccessful.\r
+ *\r
+ * This should not need to be changed.\r
+ */\r
+#define UIP_MAXSYNRTX 3\r
+\r
+/**\r
+ * The TCP maximum segment size.\r
+ *\r
+ * This is should not be to set to more than UIP_BUFSIZE - UIP_LLH_LEN - 40.\r
+ */\r
+#define UIP_TCP_MSS (UIP_BUFSIZE - UIP_LLH_LEN - 40)\r
+\r
+/**\r
+ * How long a connection should stay in the TIME_WAIT state.\r
+ *\r
+ * This configiration option has no real implication, and it should be\r
+ * left untouched.\r
+ */ \r
+#define UIP_TIME_WAIT_TIMEOUT 120\r
+\r
+\r
+/** @} */\r
+/*------------------------------------------------------------------------------*/\r
+/**\r
+ * \defgroup uipoptarp ARP configuration options\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * The size of the ARP table.\r
+ *\r
+ * This option should be set to a larger value if this uIP node will\r
+ * have many connections from the local network.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_ARPTAB_SIZE 8\r
+\r
+/**\r
+ * The maxium age of ARP table entries measured in 10ths of seconds.\r
+ *\r
+ * An UIP_ARP_MAXAGE of 120 corresponds to 20 minutes (BSD\r
+ * default).\r
+ */\r
+#define UIP_ARP_MAXAGE 120\r
+\r
+/** @} */\r
+\r
+/*------------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \defgroup uipoptgeneral General configuration options\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * The size of the uIP packet buffer.\r
+ *\r
+ * The uIP packet buffer should not be smaller than 60 bytes, and does\r
+ * not need to be larger than 1500 bytes. Lower size results in lower\r
+ * TCP throughput, larger size results in higher TCP throughput.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_BUFSIZE 2048\r
+\r
+\r
+/**\r
+ * Determines if statistics support should be compiled in.\r
+ *\r
+ * The statistics is useful for debugging and to show the user.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_STATISTICS 1\r
+\r
+/**\r
+ * Determines if logging of certain events should be compiled in.\r
+ *\r
+ * This is useful mostly for debugging. The function uip_log()\r
+ * must be implemented to suit the architecture of the project, if\r
+ * logging is turned on.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_LOGGING 0\r
+\r
+/**\r
+ * Print out a uIP log message.\r
+ *\r
+ * This function must be implemented by the module that uses uIP, and\r
+ * is called by uIP whenever a log message is generated.\r
+ */\r
+void uip_log(char *msg);\r
+\r
+/**\r
+ * The link level header length.\r
+ *\r
+ * This is the offset into the uip_buf where the IP header can be\r
+ * found. For Ethernet, this should be set to 14. For SLIP, this\r
+ * should be set to 0.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_LLH_LEN 14\r
+\r
+\r
+/** @} */\r
+/*------------------------------------------------------------------------------*/\r
+/**\r
+ * \defgroup uipoptcpu CPU architecture configuration\r
+ * @{\r
+ *\r
+ * The CPU architecture configuration is where the endianess of the\r
+ * CPU on which uIP is to be run is specified. Most CPUs today are\r
+ * little endian, and the most notable exception are the Motorolas\r
+ * which are big endian. The BYTE_ORDER macro should be changed to\r
+ * reflect the CPU architecture on which uIP is to be run.\r
+ */\r
+#ifndef LITTLE_ENDIAN\r
+#define LITTLE_ENDIAN 3412\r
+#endif /* LITTLE_ENDIAN */\r
+#ifndef BIG_ENDIAN\r
+#define BIG_ENDIAN 1234\r
+#endif /* BIGE_ENDIAN */\r
+\r
+/**\r
+ * The byte order of the CPU architecture on which uIP is to be run.\r
+ *\r
+ * This option can be either BIG_ENDIAN (Motorola byte order) or\r
+ * LITTLE_ENDIAN (Intel byte order).\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#ifndef BYTE_ORDER\r
+#define BYTE_ORDER LITTLE_ENDIAN\r
+#endif /* BYTE_ORDER */\r
+\r
+/** @} */\r
+/*------------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \defgroup uipoptapp Appication specific configurations\r
+ * @{\r
+ *\r
+ * An uIP application is implemented using a single application\r
+ * function that is called by uIP whenever a TCP/IP event occurs. The\r
+ * name of this function must be registered with uIP at compile time\r
+ * using the UIP_APPCALL definition.\r
+ *\r
+ * uIP applications can store the application state within the\r
+ * uip_conn structure by specifying the size of the application\r
+ * structure with the UIP_APPSTATE_SIZE macro.\r
+ *\r
+ * The file containing the definitions must be included in the\r
+ * uipopt.h file.\r
+ *\r
+ * The following example illustrates how this can look.\r
+ \code\r
+\r
+void httpd_appcall(void);\r
+#define UIP_APPCALL httpd_appcall\r
+\r
+struct httpd_state {\r
+ u8_t state; \r
+ u16_t count;\r
+ char *dataptr;\r
+ char *script;\r
+};\r
+#define UIP_APPSTATE_SIZE (sizeof(struct httpd_state))\r
+ \endcode\r
+ */\r
+\r
+/**\r
+ * \var #define UIP_APPCALL\r
+ *\r
+ * The name of the application function that uIP should call in\r
+ * response to TCP/IP events.\r
+ *\r
+ */\r
+\r
+/**\r
+ * \var #define UIP_APPSTATE_SIZE\r
+ *\r
+ * The size of the application state that is to be stored in the\r
+ * uip_conn structure.\r
+ */\r
+/** @} */\r
+\r
+/* Include the header file for the application program that should be\r
+ used. If you don't use the example web server, you should change\r
+ this. */\r
+#include "httpd.h"\r
+\r
+\r
+#endif /* __UIPOPT_H__ */\r
--- /dev/null
+The FreeRTOS source code is licensed by the modified GNU General Public \r
+License (GPL) text provided below. The FreeRTOS download also includes \r
+demo application source code, some of which is provided by third parties \r
+AND IS LICENSED SEPARATELY FROM FREERTOS. \r
+\r
+For the avoidance of any doubt refer to the comment included at the top\r
+of each source and header file for license and copyright information.\r
+\r
+This is a list of files for which Richard Barry is not the copyright owner\r
+and are NOT COVERED BY THE GPL.\r
+\r
+\r
+1) Various header files provided by silicon manufacturers and tool vendors\r
+ that define processor specific memory addresses and utility macros.\r
+ Permission has been granted by the various copyright holders for these\r
+ files to be included in the FreeRTOS download. Users must ensure license\r
+ conditions are adhered to for any use other than compilation of the \r
+ FreeRTOS demo application.\r
+\r
+2) The uIP TCP/IP stack the copyright of which is held by Adam Dunkels.\r
+ Users must ensure the open source license conditions stated at the top \r
+ of each uIP source file is understood and adhered to.\r
+\r
+3) The lwIP TCP/IP stack the copyright of which is held by the Swedish \r
+ Institute of Computer Science. Users must ensure the open source license \r
+ conditions stated at the top of each lwIP source file is understood and \r
+ adhered to.\r
+\r
+4) All files contained within the FreeRTOS\Demo\CORTEX_LM3S102_GCC\hw_include\r
+ directory. The copyright of these files is owned by Luminary Micro.\r
+ Permission has been granted by Luminary Micro for these files to be \r
+ included in the FreeRTOS download. Users must ensure the license \r
+ conditions stated at the top of the human readable files are understood \r
+ and adhered at all times for all files in that directory.\r
+\r
+\r
+Errors and omissions should be reported to Richard Barry, contact details for\r
+whom can be obtained from http://www.FreeRTOS.org.\r
+\r
+\r
+\r
+\r
+\r
+The GPL license text follows.\r
+\r
+An exception to this license exists that can be applied should you \r
+wish to use FreeRTOS in a work that includes commercial or \r
+proprietary code without being obliged to provide source code for the \r
+proprietary components. See the licensing section of \r
+http://www.FreeRTOS.org for full details.\r
+--------------------------------------------------------------------\r
+\r
+\r
+\r
+ GNU GENERAL PUBLIC LICENSE\r
+ Version 2, June 1991\r
+\r
+ Copyright (C) 1989, 1991 Free Software Foundation, Inc.\r
+ 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+ Everyone is permitted to copy and distribute verbatim copies\r
+ of this license document, but changing it is not allowed.\r
+\r
+ Preamble\r
+\r
+ The licenses for most software are designed to take away your\r
+freedom to share and change it. By contrast, the GNU General Public\r
+License is intended to guarantee your freedom to share and change free\r
+software--to make sure the software is free for all its users. This\r
+General Public License applies to most of the Free Software\r
+Foundation's software and to any other program whose authors commit to\r
+using it. (Some other Free Software Foundation software is covered by\r
+the GNU Library General Public License instead.) You can apply it to\r
+your programs, too.\r
+\r
+ When we speak of free software, we are referring to freedom, not\r
+price. Our General Public Licenses are designed to make sure that you\r
+have the freedom to distribute copies of free software (and charge for\r
+this service if you wish), that you receive source code or can get it\r
+if you want it, that you can change the software or use pieces of it\r
+in new free programs; and that you know you can do these things.\r
+\r
+ To protect your rights, we need to make restrictions that forbid\r
+anyone to deny you these rights or to ask you to surrender the rights.\r
+These restrictions translate to certain responsibilities for you if you\r
+distribute copies of the software, or if you modify it.\r
+\r
+ For example, if you distribute copies of such a program, whether\r
+gratis or for a fee, you must give the recipients all the rights that\r
+you have. You must make sure that they, too, receive or can get the\r
+source code. And you must show them these terms so they know their\r
+rights.\r
+\r
+ We protect your rights with two steps: (1) copyright the software, and\r
+(2) offer you this license which gives you legal permission to copy,\r
+distribute and/or modify the software.\r
+\r
+ Also, for each author's protection and ours, we want to make certain\r
+that everyone understands that there is no warranty for this free\r
+software. If the software is modified by someone else and passed on, we\r
+want its recipients to know that what they have is not the original, so\r
+that any problems introduced by others will not reflect on the original\r
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+\r
+ Finally, any free program is threatened constantly by software\r
+patents. We wish to avoid the danger that redistributors of a free\r
+program will individually obtain patent licenses, in effect making the\r
+program proprietary. To prevent this, we have made it clear that any\r
+patent must be licensed for everyone's free use or not licensed at all.\r
+\r
+ The precise terms and conditions for copying, distribution and\r
+modification follow.\r
+\f\r
+ GNU GENERAL PUBLIC LICENSE\r
+ TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION\r
+\r
+ 0. This License applies to any program or other work which contains\r
+a notice placed by the copyright holder saying it may be distributed\r
+under the terms of this General Public License. The "Program", below,\r
+refers to any such program or work, and a "work based on the Program"\r
+means either the Program or any derivative work under copyright law:\r
+that is to say, a work containing the Program or a portion of it,\r
+either verbatim or with modifications and/or translated into another\r
+language. (Hereinafter, translation is included without limitation in\r
+the term "modification".) Each licensee is addressed as "you".\r
+\r
+Activities other than copying, distribution and modification are not\r
+covered by this License; they are outside its scope. The act of\r
+running the Program is not restricted, and the output from the Program\r
+is covered only if its contents constitute a work based on the\r
+Program (independent of having been made by running the Program).\r
+Whether that is true depends on what the Program does.\r
+\r
+ 1. You may copy and distribute verbatim copies of the Program's\r
+source code as you receive it, in any medium, provided that you\r
+conspicuously and appropriately publish on each copy an appropriate\r
+copyright notice and disclaimer of warranty; keep intact all the\r
+notices that refer to this License and to the absence of any warranty;\r
+and give any other recipients of the Program a copy of this License\r
+along with the Program.\r
+\r
+You may charge a fee for the physical act of transferring a copy, and\r
+you may at your option offer warranty protection in exchange for a fee.\r
+\r
+ 2. You may modify your copy or copies of the Program or any portion\r
+of it, thus forming a work based on the Program, and copy and\r
+distribute such modifications or work under the terms of Section 1\r
+above, provided that you also meet all of these conditions:\r
+\r
+ a) You must cause the modified files to carry prominent notices\r
+ stating that you changed the files and the date of any change.\r
+\r
+ b) You must cause any work that you distribute or publish, that in\r
+ whole or in part contains or is derived from the Program or any\r
+ part thereof, to be licensed as a whole at no charge to all third\r
+ parties under the terms of this License.\r
+\r
+ c) If the modified program normally reads commands interactively\r
+ when run, you must cause it, when started running for such\r
+ interactive use in the most ordinary way, to print or display an\r
+ announcement including an appropriate copyright notice and a\r
+ notice that there is no warranty (or else, saying that you provide\r
+ a warranty) and that users may redistribute the program under\r
+ these conditions, and telling the user how to view a copy of this\r
+ License. (Exception: if the Program itself is interactive but\r
+ does not normally print such an announcement, your work based on\r
+ the Program is not required to print an announcement.)\r
+\f\r
+These requirements apply to the modified work as a whole. If\r
+identifiable sections of that work are not derived from the Program,\r
+and can be reasonably considered independent and separate works in\r
+themselves, then this License, and its terms, do not apply to those\r
+sections when you distribute them as separate works. But when you\r
+distribute the same sections as part of a whole which is a work based\r
+on the Program, the distribution of the whole must be on the terms of\r
+this License, whose permissions for other licensees extend to the\r
+entire whole, and thus to each and every part regardless of who wrote it.\r
+\r
+Thus, it is not the intent of this section to claim rights or contest\r
+your rights to work written entirely by you; rather, the intent is to\r
+exercise the right to control the distribution of derivative or\r
+collective works based on the Program.\r
+\r
+In addition, mere aggregation of another work not based on the Program\r
+with the Program (or with a work based on the Program) on a volume of\r
+a storage or distribution medium does not bring the other work under\r
+the scope of this License.\r
+\r
+ 3. You may copy and distribute the Program (or a work based on it,\r
+under Section 2) in object code or executable form under the terms of\r
+Sections 1 and 2 above provided that you also do one of the following:\r
+\r
+ a) Accompany it with the complete corresponding machine-readable\r
+ source code, which must be distributed under the terms of Sections\r
+ 1 and 2 above on a medium customarily used for software interchange; or,\r
+\r
+ b) Accompany it with a written offer, valid for at least three\r
+ years, to give any third party, for a charge no more than your\r
+ cost of physically performing source distribution, a complete\r
+ machine-readable copy of the corresponding source code, to be\r
+ distributed under the terms of Sections 1 and 2 above on a medium\r
+ customarily used for software interchange; or,\r
+\r
+ c) Accompany it with the information you received as to the offer\r
+ to distribute corresponding source code. (This alternative is\r
+ allowed only for noncommercial distribution and only if you\r
+ received the program in object code or executable form with such\r
+ an offer, in accord with Subsection b above.)\r
+\r
+The source code for a work means the preferred form of the work for\r
+making modifications to it. For an executable work, complete source\r
+code means all the source code for all modules it contains, plus any\r
+associated interface definition files, plus the scripts used to\r
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+special exception, the source code distributed need not include\r
+anything that is normally distributed (in either source or binary\r
+form) with the major components (compiler, kernel, and so on) of the\r
+operating system on which the executable runs, unless that component\r
+itself accompanies the executable.\r
+\r
+If distribution of executable or object code is made by offering\r
+access to copy from a designated place, then offering equivalent\r
+access to copy the source code from the same place counts as\r
+distribution of the source code, even though third parties are not\r
+compelled to copy the source along with the object code.\r
+\f\r
+ 4. You may not copy, modify, sublicense, or distribute the Program\r
+except as expressly provided under this License. Any attempt\r
+otherwise to copy, modify, sublicense or distribute the Program is\r
+void, and will automatically terminate your rights under this License.\r
+However, parties who have received copies, or rights, from you under\r
+this License will not have their licenses terminated so long as such\r
+parties remain in full compliance.\r
+\r
+ 5. You are not required to accept this License, since you have not\r
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+distribute the Program or its derivative works. These actions are\r
+prohibited by law if you do not accept this License. Therefore, by\r
+modifying or distributing the Program (or any work based on the\r
+Program), you indicate your acceptance of this License to do so, and\r
+all its terms and conditions for copying, distributing or modifying\r
+the Program or works based on it.\r
+\r
+ 6. Each time you redistribute the Program (or any work based on the\r
+Program), the recipient automatically receives a license from the\r
+original licensor to copy, distribute or modify the Program subject to\r
+these terms and conditions. You may not impose any further\r
+restrictions on the recipients' exercise of the rights granted herein.\r
+You are not responsible for enforcing compliance by third parties to\r
+this License.\r
+\r
+ 7. If, as a consequence of a court judgment or allegation of patent\r
+infringement or for any other reason (not limited to patent issues),\r
+conditions are imposed on you (whether by court order, agreement or\r
+otherwise) that contradict the conditions of this License, they do not\r
+excuse you from the conditions of this License. If you cannot\r
+distribute so as to satisfy simultaneously your obligations under this\r
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+may not distribute the Program at all. For example, if a patent\r
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+all those who receive copies directly or indirectly through you, then\r
+the only way you could satisfy both it and this License would be to\r
+refrain entirely from distribution of the Program.\r
+\r
+If any portion of this section is held invalid or unenforceable under\r
+any particular circumstance, the balance of the section is intended to\r
+apply and the section as a whole is intended to apply in other\r
+circumstances.\r
+\r
+It is not the purpose of this section to induce you to infringe any\r
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+integrity of the free software distribution system, which is\r
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+generous contributions to the wide range of software distributed\r
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+system; it is up to the author/donor to decide if he or she is willing\r
+to distribute software through any other system and a licensee cannot\r
+impose that choice.\r
+\r
+This section is intended to make thoroughly clear what is believed to\r
+be a consequence of the rest of this License.\r
+\f\r
+ 8. If the distribution and/or use of the Program is restricted in\r
+certain countries either by patents or by copyrighted interfaces, the\r
+original copyright holder who places the Program under this License\r
+may add an explicit geographical distribution limitation excluding\r
+those countries, so that distribution is permitted only in or among\r
+countries not thus excluded. In such case, this License incorporates\r
+the limitation as if written in the body of this License.\r
+\r
+ 9. The Free Software Foundation may publish revised and/or new versions\r
+of the General Public License from time to time. Such new versions will\r
+be similar in spirit to the present version, but may differ in detail to\r
+address new problems or concerns.\r
+\r
+Each version is given a distinguishing version number. If the Program\r
+specifies a version number of this License which applies to it and "any\r
+later version", you have the option of following the terms and conditions\r
+either of that version or of any later version published by the Free\r
+Software Foundation. If the Program does not specify a version number of\r
+this License, you may choose any version ever published by the Free Software\r
+Foundation.\r
+\r
+ 10. If you wish to incorporate parts of the Program into other free\r
+programs whose distribution conditions are different, write to the author\r
+to ask for permission. For software which is copyrighted by the Free\r
+Software Foundation, write to the Free Software Foundation; we sometimes\r
+make exceptions for this. Our decision will be guided by the two goals\r
+of preserving the free status of all derivatives of our free software and\r
+of promoting the sharing and reuse of software generally.\r
+\r
+ NO WARRANTY\r
+\r
+ 11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY\r
+FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN\r
+OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES\r
+PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED\r
+OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
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+TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE\r
+PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,\r
+REPAIR OR CORRECTION.\r
+\r
+ 12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING\r
+WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR\r
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+YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER\r
+PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE\r
+POSSIBILITY OF SUCH DAMAGES.\r
+\r
+ END OF TERMS AND CONDITIONS\r
+\f\r
+ How to Apply These Terms to Your New Programs\r
+\r
+ If you develop a new program, and you want it to be of the greatest\r
+possible use to the public, the best way to achieve this is to make it\r
+free software which everyone can redistribute and change under these terms.\r
+\r
+ To do so, attach the following notices to the program. It is safest\r
+to attach them to the start of each source file to most effectively\r
+convey the exclusion of warranty; and each file should have at least\r
+the "copyright" line and a pointer to where the full notice is found.\r
+\r
+ <one line to give the program's name and a brief idea of what it does.>\r
+ Copyright (C) <year> <name of author>\r
+\r
+ This program is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ This program is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with this program; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+\r
+Also add information on how to contact you by electronic and paper mail.\r
+\r
+If the program is interactive, make it output a short notice like this\r
+when it starts in an interactive mode:\r
+\r
+ Gnomovision version 69, Copyright (C) year name of author\r
+ Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.\r
+ This is free software, and you are welcome to redistribute it\r
+ under certain conditions; type `show c' for details.\r
+\r
+The hypothetical commands `show w' and `show c' should show the appropriate\r
+parts of the General Public License. Of course, the commands you use may\r
+be called something other than `show w' and `show c'; they could even be\r
+mouse-clicks or menu items--whatever suits your program.\r
+\r
+You should also get your employer (if you work as a programmer) or your\r
+school, if any, to sign a "copyright disclaimer" for the program, if\r
+necessary. Here is a sample; alter the names:\r
+\r
+ Yoyodyne, Inc., hereby disclaims all copyright interest in the program\r
+ `Gnomovision' (which makes passes at compilers) written by James Hacker.\r
+\r
+ <signature of Ty Coon>, 1 April 1989\r
+ Ty Coon, President of Vice\r
+\r
+This General Public License does not permit incorporating your program into\r
+proprietary programs. If your program is a subroutine library, you may\r
+consider it more useful to permit linking proprietary applications with the\r
+library. If this is what you want to do, use the GNU Library General\r
+Public License instead of this License.\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "croutine.h"\r
+\r
+/* Lists for ready and blocked co-routines. --------------------*/\r
+static xList pxReadyCoRoutineLists[ configMAX_CO_ROUTINE_PRIORITIES ]; /*< Prioritised ready co-routines. */\r
+static xList xDelayedCoRoutineList1; /*< Delayed co-routines. */\r
+static xList xDelayedCoRoutineList2; /*< Delayed co-routines (two lists are used - one for delays that have overflowed the current tick count. */\r
+static xList * pxDelayedCoRoutineList; /*< Points to the delayed co-routine list currently being used. */\r
+static xList * pxOverflowDelayedCoRoutineList; /*< Points to the delayed co-routine list currently being used to hold co-routines that have overflowed the current tick count. */\r
+static xList xPendingReadyList; /*< Holds co-routines that have been readied by an external event. They cannot be added directly to the ready lists as the ready lists cannot be accessed by interrupts. */\r
+\r
+/* Other file private variables. --------------------------------*/\r
+corCRCB * pxCurrentCoRoutine = NULL;\r
+static unsigned portBASE_TYPE uxTopCoRoutineReadyPriority = 0;\r
+static portTickType xCoRoutineTickCount = 0;\r
+\r
+/* The initial state of the co-routine when it is created. */\r
+#define corINITIAL_STATE ( 0 )\r
+\r
+/*\r
+ * Place the co-routine represented by pxCRCB into the appropriate ready queue \r
+ * for the priority. It is inserted at the end of the list. \r
+ *\r
+ * This macro accesses the co-routine ready lists and therefore must not be\r
+ * used from within an ISR.\r
+ */\r
+#define prvAddCoRoutineToReadyQueue( pxCRCB ) \\r
+{ \\r
+ if( pxCRCB->uxPriority > uxTopCoRoutineReadyPriority ) \\r
+ { \\r
+ uxTopCoRoutineReadyPriority = pxCRCB->uxPriority; \\r
+ } \\r
+ vListInsertEnd( ( xList * ) &( pxReadyCoRoutineLists[ pxCRCB->uxPriority ] ), &( pxCRCB->xGenericListItem ) ); \\r
+} \r
+\r
+/*\r
+ * Utility to ready all the lists used by the scheduler. This is called\r
+ * automatically upon the creation of the first co-routine.\r
+ */\r
+static void prvInitialiseCoRoutineLists( void );\r
+\r
+/*\r
+ * Co-routines that are readied by an interrupt cannot be placed directly into\r
+ * the ready lists (there is no mutual exclusion). Instead they are placed in\r
+ * in the pending ready list in order that they can later be moved to the ready\r
+ * list by the co-routine scheduler.\r
+ */\r
+static inline void prvCheckPendingReadyList( void );\r
+\r
+/*\r
+ * Macro that looks at the list of co-routines that are currently delayed to \r
+ * see if any require waking.\r
+ *\r
+ * Co-routines are stored in the queue in the order of their wake time - \r
+ * meaning once one co-routine has been found whose timer has not expired \r
+ * we need not look any further down the list.\r
+ */\r
+static inline void prvCheckDelayedList( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+portBASE_TYPE xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, unsigned portBASE_TYPE uxPriority, unsigned portBASE_TYPE uxIndex )\r
+{\r
+portBASE_TYPE xReturn;\r
+corCRCB *pxCoRoutine;\r
+\r
+ /* Allocate the memory that will store the co-routine control block. */\r
+ pxCoRoutine = ( corCRCB * ) pvPortMalloc( sizeof( corCRCB ) );\r
+ if( pxCoRoutine )\r
+ {\r
+ /* If pxCurrentCoRoutine is NULL then this is the first co-routine to\r
+ be created and the co-routine data structures need initialising. */\r
+ if( pxCurrentCoRoutine == NULL )\r
+ {\r
+ pxCurrentCoRoutine = pxCoRoutine;\r
+ prvInitialiseCoRoutineLists();\r
+ }\r
+\r
+ /* Check the priority is within limits. */\r
+ if( uxPriority >= configMAX_CO_ROUTINE_PRIORITIES )\r
+ {\r
+ uxPriority = configMAX_CO_ROUTINE_PRIORITIES - 1;\r
+ }\r
+\r
+ /* Fill out the co-routine control block from the function parameters. */\r
+ pxCoRoutine->uxState = corINITIAL_STATE;\r
+ pxCoRoutine->uxPriority = uxPriority;\r
+ pxCoRoutine->uxIndex = uxIndex;\r
+ pxCoRoutine->pxCoRoutineFunction = pxCoRoutineCode;\r
+\r
+ /* Initialise all the other co-routine control block parameters. */\r
+ vListInitialiseItem( &( pxCoRoutine->xGenericListItem ) );\r
+ vListInitialiseItem( &( pxCoRoutine->xEventListItem ) );\r
+\r
+ /* Set the co-routine control block as a link back from the xListItem. \r
+ This is so we can get back to the containing CRCB from a generic item \r
+ in a list. */\r
+ listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xGenericListItem ), pxCoRoutine );\r
+ listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xEventListItem ), pxCoRoutine );\r
+ \r
+ /* Event lists are always in priority order. */\r
+ listSET_LIST_ITEM_VALUE( &( pxCoRoutine->xEventListItem ), configMAX_PRIORITIES - ( portTickType ) uxPriority );\r
+ \r
+ /* Now the co-routine has been initialised it can be added to the ready\r
+ list at the correct priority. */\r
+ prvAddCoRoutineToReadyQueue( pxCoRoutine );\r
+\r
+ xReturn = pdPASS;\r
+ }\r
+ else\r
+ { \r
+ xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;\r
+ }\r
+ \r
+ return xReturn; \r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vCoRoutineAddToDelayedList( portTickType xTicksToDelay, xList *pxEventList )\r
+{\r
+portTickType xTimeToWake;\r
+\r
+ /* Calculate the time to wake - this may overflow but this is\r
+ not a problem. */\r
+ xTimeToWake = xCoRoutineTickCount + xTicksToDelay;\r
+\r
+ /* We must remove ourselves from the ready list before adding\r
+ ourselves to the blocked list as the same list item is used for\r
+ both lists. */\r
+ vListRemove( ( xListItem * ) &( pxCurrentCoRoutine->xGenericListItem ) );\r
+\r
+ /* The list item will be inserted in wake time order. */\r
+ listSET_LIST_ITEM_VALUE( &( pxCurrentCoRoutine->xGenericListItem ), xTimeToWake );\r
+\r
+ if( xTimeToWake < xCoRoutineTickCount )\r
+ {\r
+ /* Wake time has overflowed. Place this item in the\r
+ overflow list. */\r
+ vListInsert( ( xList * ) pxOverflowDelayedCoRoutineList, ( xListItem * ) &( pxCurrentCoRoutine->xGenericListItem ) );\r
+ }\r
+ else\r
+ {\r
+ /* The wake time has not overflowed, so we can use the\r
+ current block list. */\r
+ vListInsert( ( xList * ) pxDelayedCoRoutineList, ( xListItem * ) &( pxCurrentCoRoutine->xGenericListItem ) );\r
+ }\r
+\r
+ if( pxEventList )\r
+ {\r
+ /* Also add the co-routine to an event list. If this is done then the\r
+ function must be called with interrupts disabled. */\r
+ vListInsert( pxEventList, &( pxCurrentCoRoutine->xEventListItem ) );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static inline void prvCheckPendingReadyList( void )\r
+{\r
+ /* Are there any co-routines waiting to get moved to the ready list? These\r
+ are co-routines that have been readied by an ISR. The ISR cannot access \r
+ the ready lists itself. */\r
+ while( !listLIST_IS_EMPTY( &xPendingReadyList ) )\r
+ {\r
+ corCRCB *pxUnblockedCRCB;\r
+\r
+ /* The pending ready list can be accessed by an ISR. */\r
+ portDISABLE_INTERRUPTS();\r
+ { \r
+ pxUnblockedCRCB = ( corCRCB * ) listGET_OWNER_OF_HEAD_ENTRY( (&xPendingReadyList) ); \r
+ vListRemove( &( pxUnblockedCRCB->xEventListItem ) );\r
+ }\r
+ portENABLE_INTERRUPTS();\r
+\r
+ vListRemove( &( pxUnblockedCRCB->xGenericListItem ) );\r
+ prvAddCoRoutineToReadyQueue( pxUnblockedCRCB ); \r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static inline void prvCheckDelayedList( void )\r
+{\r
+static portTickType xLastTickCount, xPassedTicks;\r
+corCRCB *pxCRCB;\r
+\r
+ xPassedTicks = xTaskGetTickCount() - xLastTickCount;\r
+ while( xPassedTicks )\r
+ {\r
+ xCoRoutineTickCount++;\r
+ xPassedTicks--;\r
+\r
+ /* If the tick count has overflowed we need to swap the ready lists. */\r
+ if( xCoRoutineTickCount == 0 )\r
+ {\r
+ xList * pxTemp;\r
+\r
+ /* Tick count has overflowed so we need to swap the delay lists. If there are\r
+ any items in pxDelayedCoRoutineList here then there is an error! */\r
+ pxTemp = pxDelayedCoRoutineList;\r
+ pxDelayedCoRoutineList = pxOverflowDelayedCoRoutineList;\r
+ pxOverflowDelayedCoRoutineList = pxTemp;\r
+ }\r
+\r
+ /* See if this tick has made a timeout expire. */\r
+ while( ( pxCRCB = ( corCRCB * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedCoRoutineList ) ) != NULL )\r
+ { \r
+ if( xCoRoutineTickCount < listGET_LIST_ITEM_VALUE( &( pxCRCB->xGenericListItem ) ) ) \r
+ { \r
+ /* Timeout not yet expired. */ \r
+ break; \r
+ } \r
+\r
+ portDISABLE_INTERRUPTS();\r
+ {\r
+ /* The event could have occurred just before this critical \r
+ section. If this is the case then the generic list item will\r
+ have been moved to the pending ready list and the following \r
+ line is still valid. Also the pvContainer parameter will have\r
+ been set to NULL so the following lines are also valid. */\r
+ vListRemove( &( pxCRCB->xGenericListItem ) ); \r
+\r
+ /* Is the co-routine waiting on an event also? */ \r
+ if( pxCRCB->xEventListItem.pvContainer ) \r
+ { \r
+ vListRemove( &( pxCRCB->xEventListItem ) ); \r
+ }\r
+ }\r
+ portENABLE_INTERRUPTS();\r
+\r
+ prvAddCoRoutineToReadyQueue( pxCRCB ); \r
+ } \r
+ }\r
+\r
+ xLastTickCount = xCoRoutineTickCount;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vCoRoutineSchedule( void )\r
+{\r
+ /* See if any co-routines readied by events need moving to the ready lists. */\r
+ prvCheckPendingReadyList();\r
+\r
+ /* See if any delayed co-routines have timed out. */\r
+ prvCheckDelayedList();\r
+\r
+ /* Find the highest priority queue that contains ready co-routines. */\r
+ while( listLIST_IS_EMPTY( &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ) )\r
+ {\r
+ if( uxTopCoRoutineReadyPriority == 0 )\r
+ {\r
+ /* No more co-routines to check. */\r
+ return;\r
+ }\r
+ --uxTopCoRoutineReadyPriority;\r
+ }\r
+\r
+ /* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the co-routines\r
+ of the same priority get an equal share of the processor time. */\r
+ listGET_OWNER_OF_NEXT_ENTRY( pxCurrentCoRoutine, &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) );\r
+\r
+ /* Call the co-routine. */\r
+ ( pxCurrentCoRoutine->pxCoRoutineFunction )( pxCurrentCoRoutine, pxCurrentCoRoutine->uxIndex );\r
+\r
+ return;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvInitialiseCoRoutineLists( void )\r
+{\r
+unsigned portBASE_TYPE uxPriority;\r
+\r
+ for( uxPriority = 0; uxPriority < configMAX_CO_ROUTINE_PRIORITIES; uxPriority++ )\r
+ {\r
+ vListInitialise( ( xList * ) &( pxReadyCoRoutineLists[ uxPriority ] ) );\r
+ }\r
+\r
+ vListInitialise( ( xList * ) &xDelayedCoRoutineList1 );\r
+ vListInitialise( ( xList * ) &xDelayedCoRoutineList2 );\r
+ vListInitialise( ( xList * ) &xPendingReadyList );\r
+\r
+ /* Start with pxDelayedCoRoutineList using list1 and the \r
+ pxOverflowDelayedCoRoutineList using list2. */\r
+ pxDelayedCoRoutineList = &xDelayedCoRoutineList1;\r
+ pxOverflowDelayedCoRoutineList = &xDelayedCoRoutineList2;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portBASE_TYPE xCoRoutineRemoveFromEventList( const xList *pxEventList )\r
+{\r
+corCRCB *pxUnblockedCRCB;\r
+portBASE_TYPE xReturn;\r
+\r
+ /* This function is called from within an interrupt. It can only access\r
+ event lists and the pending ready list. */\r
+ pxUnblockedCRCB = ( corCRCB * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList );\r
+ vListRemove( &( pxUnblockedCRCB->xEventListItem ) );\r
+ vListInsertEnd( ( xList * ) &( xPendingReadyList ), &( pxUnblockedCRCB->xEventListItem ) );\r
+\r
+ if( pxUnblockedCRCB->uxPriority >= pxCurrentCoRoutine->uxPriority )\r
+ {\r
+ xReturn = pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ xReturn = pdFALSE;\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef INC_FREERTOS_H\r
+#define INC_FREERTOS_H\r
+\r
+\r
+/* \r
+ * Include the generic headers required for the FreeRTOS port being used. \r
+ */\r
+#include <stddef.h>\r
+\r
+/* Basic FreeRTOS definitions. */\r
+#include "projdefs.h"\r
+\r
+/* Application specific configuration options. */\r
+#include "FreeRTOSConfig.h"\r
+\r
+/* Definitions specific to the port being used. */\r
+#include "portable.h"\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+/*\r
+ * Check all the required application specific macros have been defined. \r
+ * These macros are application specific and (as downloaded) are defined\r
+ * within FreeRTOSConfig.h.\r
+ */\r
+\r
+#ifndef configUSE_PREEMPTION\r
+ #error Missing definition: configUSE_PREEMPTION should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details.\r
+#endif\r
+\r
+#ifndef configUSE_IDLE_HOOK\r
+ #error Missing definition: configUSE_IDLE_HOOK should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details.\r
+#endif\r
+\r
+#ifndef configUSE_TICK_HOOK\r
+ #error Missing definition: configUSE_TICK_HOOK should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details.\r
+#endif\r
+\r
+#ifndef configUSE_CO_ROUTINES\r
+ #error Missing definition: configUSE_CO_ROUTINES should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details.\r
+#endif\r
+\r
+#ifndef INCLUDE_vTaskPrioritySet\r
+ #error Missing definition: INCLUDE_vTaskPrioritySet should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details.\r
+#endif\r
+\r
+#ifndef INCLUDE_uxTaskPriorityGet\r
+ #error Missing definition: INCLUDE_uxTaskPriorityGet should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details.\r
+#endif\r
+\r
+#ifndef INCLUDE_vTaskDelete \r
+ #error Missing definition: INCLUDE_vTaskDelete should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details.\r
+#endif\r
+\r
+#ifndef INCLUDE_vTaskCleanUpResources\r
+ #error Missing definition: INCLUDE_vTaskCleanUpResources should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details.\r
+#endif\r
+\r
+#ifndef INCLUDE_vTaskSuspend \r
+ #error Missing definition: INCLUDE_vTaskSuspend should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details.\r
+#endif\r
+\r
+#ifndef INCLUDE_vTaskDelayUntil\r
+ #error Missing definition: INCLUDE_vTaskDelayUntil should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details.\r
+#endif\r
+\r
+#ifndef INCLUDE_vTaskDelay\r
+ #error Missing definition: INCLUDE_vTaskDelay should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details.\r
+#endif\r
+\r
+#ifndef configUSE_16_BIT_TICKS\r
+ #error Missing definition: configUSE_16_BIT_TICKS should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details.\r
+#endif\r
+\r
+#endif\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+#ifndef CO_ROUTINE_H\r
+#define CO_ROUTINE_H\r
+\r
+#include "list.h"\r
+\r
+/* Used to hide the implementation of the co-routine control block. The \r
+control block structure however has to be included in the header due to \r
+the macro implementation of the co-routine functionality. */\r
+typedef void * xCoRoutineHandle;\r
+\r
+/* Defines the prototype to which co-routine functions must conform. */\r
+typedef void (*crCOROUTINE_CODE)( xCoRoutineHandle, unsigned portBASE_TYPE );\r
+\r
+typedef struct corCoRoutineControlBlock\r
+{\r
+ crCOROUTINE_CODE pxCoRoutineFunction;\r
+ xListItem xGenericListItem; /*< List item used to place the CRCB in ready and blocked queues. */\r
+ xListItem xEventListItem; /*< List item used to place the CRCB in event lists. */\r
+ unsigned portBASE_TYPE uxPriority; /*< The priority of the co-routine in relation to other co-routines. */\r
+ unsigned portBASE_TYPE uxIndex; /*< Used to distinguish between co-routines when multiple co-routines use the same co-routine function. */\r
+ unsigned portSHORT uxState; /*< Used internally by the co-routine implementation. */\r
+} corCRCB; /* Co-routine control block. Note must be identical in size down to uxPriority with tskTCB. */\r
+\r
+/**\r
+ * croutine. h\r
+ *<pre>\r
+ portBASE_TYPE xCoRoutineCreate(\r
+ crCOROUTINE_CODE pxCoRoutineCode,\r
+ unsigned portBASE_TYPE uxPriority,\r
+ unsigned portBASE_TYPE uxIndex\r
+ );</pre>\r
+ *\r
+ * Create a new co-routine and add it to the list of co-routines that are \r
+ * ready to run.\r
+ *\r
+ * @param pxCoRoutineCode Pointer to the co-routine function. Co-routine \r
+ * functions require special syntax - see the co-routine section of the WEB \r
+ * documentation for more information.\r
+ *\r
+ * @param uxPriority The priority with respect to other co-routines at which \r
+ * the co-routine will run.\r
+ *\r
+ * @param uxIndex Used to distinguish between different co-routines that\r
+ * execute the same function. See the example below and the co-routine section\r
+ * of the WEB documentation for further information.\r
+ *\r
+ * @return pdPASS if the co-routine was successfully created and added to a ready\r
+ * list, otherwise an error code defined with ProjDefs.h.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ // Co-routine to be created.\r
+ void vFlashCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )\r
+ {\r
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.\r
+ // This may not be necessary for const variables.\r
+ static const char cLedToFlash[ 2 ] = { 5, 6 };\r
+ static const portTickType xTimeToDelay[ 2 ] = { 200, 400 };\r
+\r
+ // Must start every co-routine with a call to crSTART();\r
+ crSTART( xHandle );\r
+\r
+ for( ;; )\r
+ {\r
+ // This co-routine just delays for a fixed period, then toggles\r
+ // an LED. Two co-routines are created using this function, so\r
+ // the uxIndex parameter is used to tell the co-routine which\r
+ // LED to flash and how long to delay. This assumes xQueue has\r
+ // already been created.\r
+ vParTestToggleLED( cLedToFlash[ uxIndex ] );\r
+ crDELAY( xHandle, uxFlashRates[ uxIndex ] );\r
+ }\r
+\r
+ // Must end every co-routine with a call to crEND();\r
+ crEND();\r
+ }\r
+\r
+ // Function that creates two co-routines.\r
+ void vOtherFunction( void )\r
+ {\r
+ unsigned char ucParameterToPass;\r
+ xTaskHandle xHandle;\r
+ \r
+ // Create two co-routines at priority 0. The first is given index 0\r
+ // so (from the code above) toggles LED 5 every 200 ticks. The second\r
+ // is given index 1 so toggles LED 6 every 400 ticks.\r
+ for( uxIndex = 0; uxIndex < 2; uxIndex++ )\r
+ {\r
+ xCoRoutineCreate( vFlashCoRoutine, 0, uxIndex );\r
+ } \r
+ }\r
+ </pre>\r
+ * \defgroup xCoRoutineCreate xCoRoutineCreate\r
+ * \ingroup Tasks\r
+ */\r
+portBASE_TYPE xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, unsigned portBASE_TYPE uxPriority, unsigned portBASE_TYPE uxIndex );\r
+\r
+\r
+/**\r
+ * croutine. h\r
+ *<pre>\r
+ void vCoRoutineSchedule( void );</pre>\r
+ *\r
+ * Run a co-routine.\r
+ * \r
+ * vCoRoutineSchedule() executes the highest priority co-routine that is able\r
+ * to run. The co-routine will execute until it either blocks, yields or is\r
+ * preempted by a task. Co-routines execute cooperatively so one \r
+ * co-routine cannot be preempted by another, but can be preempted by a task.\r
+ *\r
+ * If an application comprises of both tasks and co-routines then \r
+ * vCoRoutineSchedule should be called from the idle task (in an idle task \r
+ * hook).\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ // This idle task hook will schedule a co-routine each time it is called.\r
+ // The rest of the idle task will execute between co-routine calls.\r
+ void vApplicationIdleHook( void )\r
+ {\r
+ vCoRoutineSchedule();\r
+ }\r
+\r
+ // Alternatively, if you do not require any other part of the idle task to \r
+ // execute, the idle task hook can call vCoRoutineScheduler() within an\r
+ // infinite loop.\r
+ void vApplicationIdleHook( void )\r
+ {\r
+ for( ;; )\r
+ {\r
+ vCoRoutineSchedule();\r
+ }\r
+ }\r
+ </pre>\r
+ * \defgroup vCoRoutineSchedule vCoRoutineSchedule\r
+ * \ingroup Tasks\r
+ */\r
+void vCoRoutineSchedule( void );\r
+\r
+/**\r
+ * croutine. h\r
+ * <pre>\r
+ crSTART( xCoRoutineHandle xHandle );</pre>\r
+ *\r
+ * This macro MUST always be called at the start of a co-routine function.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ // Co-routine to be created.\r
+ void vACoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )\r
+ {\r
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.\r
+ static portLONG ulAVariable;\r
+\r
+ // Must start every co-routine with a call to crSTART();\r
+ crSTART( xHandle );\r
+\r
+ for( ;; )\r
+ {\r
+ // Co-routine functionality goes here.\r
+ }\r
+\r
+ // Must end every co-routine with a call to crEND();\r
+ crEND();\r
+ }</pre>\r
+ * \defgroup crSTART crSTART\r
+ * \ingroup Tasks\r
+ */\r
+#define crSTART( pxCRCB ) switch( ( ( corCRCB * )pxCRCB )->uxState ) { case 0:\r
+\r
+/**\r
+ * croutine. h\r
+ * <pre>\r
+ crEND();</pre>\r
+ *\r
+ * This macro MUST always be called at the end of a co-routine function.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ // Co-routine to be created.\r
+ void vACoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )\r
+ {\r
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.\r
+ static portLONG ulAVariable;\r
+\r
+ // Must start every co-routine with a call to crSTART();\r
+ crSTART( xHandle );\r
+\r
+ for( ;; )\r
+ {\r
+ // Co-routine functionality goes here.\r
+ }\r
+\r
+ // Must end every co-routine with a call to crEND();\r
+ crEND();\r
+ }</pre>\r
+ * \defgroup crSTART crSTART\r
+ * \ingroup Tasks\r
+ */\r
+#define crEND() }\r
+\r
+/*\r
+ * These macros are intended for internal use by the co-routine implementation \r
+ * only. The macros should not be used directly by application writers.\r
+ */\r
+#define crSET_STATE0( xHandle ) ( ( corCRCB * )xHandle)->uxState = (__LINE__ * 2); return; case (__LINE__ * 2):\r
+#define crSET_STATE1( xHandle ) ( ( corCRCB * )xHandle)->uxState = ((__LINE__ * 2)+1); return; case ((__LINE__ * 2)+1):\r
+\r
+/**\r
+ * croutine. h\r
+ *<pre>\r
+ crDELAY( xCoRoutineHandle xHandle, portTickType xTicksToDelay );</pre>\r
+ *\r
+ * Delay a co-routine for a fixed period of time.\r
+ *\r
+ * crDELAY can only be called from the co-routine function itself - not\r
+ * from within a function called by the co-routine function. This is because\r
+ * co-routines do not maintain their own stack.\r
+ *\r
+ * @param xHandle The handle of the co-routine to delay. This is the xHandle\r
+ * parameter of the co-routine function.\r
+ *\r
+ * @param xTickToDelay The number of ticks that the co-routine should delay \r
+ * for. The actual amount of time this equates to is defined by \r
+ * configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant portTICK_RATE_MS\r
+ * can be used to convert ticks to milliseconds.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ // Co-routine to be created.\r
+ void vACoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )\r
+ {\r
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.\r
+ // This may not be necessary for const variables.\r
+ // We are to delay for 200ms.\r
+ static const xTickType xDelayTime = 200 / portTICK_RATE_MS;\r
+\r
+ // Must start every co-routine with a call to crSTART();\r
+ crSTART( xHandle );\r
+\r
+ for( ;; )\r
+ {\r
+ // Delay for 200ms.\r
+ crDELAY( xHandle, xDelayTime );\r
+\r
+ // Do something here.\r
+ }\r
+\r
+ // Must end every co-routine with a call to crEND();\r
+ crEND();\r
+ }</pre>\r
+ * \defgroup crDELAY crDELAY\r
+ * \ingroup Tasks\r
+ */\r
+#define crDELAY( xHandle, xTicksToDelay ) \\r
+ if( xTicksToDelay > 0 ) \\r
+ { \\r
+ vCoRoutineAddToDelayedList( xTicksToDelay, NULL ); \\r
+ } \\r
+ crSET_STATE0( xHandle );\r
+\r
+/**\r
+ * <pre>\r
+ crQUEUE_SEND( \r
+ xCoRoutineHandle xHandle, \r
+ xQueueHandle pxQueue, \r
+ void *pvItemToQueue, \r
+ portTickType xTicksToWait, \r
+ portBASE_TYPE *pxResult \r
+ )</pre>\r
+ *\r
+ * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine \r
+ * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks. \r
+ *\r
+ * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas \r
+ * xQueueSend() and xQueueReceive() can only be used from tasks.\r
+ *\r
+ * crQUEUE_SEND can only be called from the co-routine function itself - not\r
+ * from within a function called by the co-routine function. This is because\r
+ * co-routines do not maintain their own stack.\r
+ *\r
+ * See the co-routine section of the WEB documentation for information on \r
+ * passing data between tasks and co-routines and between ISR's and \r
+ * co-routines.\r
+ *\r
+ * @param xHandle The handle of the calling co-routine. This is the xHandle\r
+ * parameter of the co-routine function.\r
+ *\r
+ * @param pxQueue The handle of the queue on which the data will be posted. \r
+ * The handle is obtained as the return value when the queue is created using \r
+ * the xQueueCreate() API function.\r
+ *\r
+ * @param pvItemToQueue A pointer to the data being posted onto the queue.\r
+ * The number of bytes of each queued item is specified when the queue is\r
+ * created. This number of bytes is copied from pvItemToQueue into the queue\r
+ * itself.\r
+ *\r
+ * @param xTickToDelay The number of ticks that the co-routine should block \r
+ * to wait for space to become available on the queue, should space not be\r
+ * available immediately. The actual amount of time this equates to is defined \r
+ * by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant \r
+ * portTICK_RATE_MS can be used to convert ticks to milliseconds (see example\r
+ * below).\r
+ *\r
+ * @param pxResult The variable pointed to by pxResult will be set to pdPASS if\r
+ * data was successfully posted onto the queue, otherwise it will be set to an \r
+ * error defined within ProjDefs.h.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ // Co-routine function that blocks for a fixed period then posts a number onto\r
+ // a queue.\r
+ static void prvCoRoutineFlashTask( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )\r
+ {\r
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.\r
+ static portBASE_TYPE xNumberToPost = 0;\r
+ static portBASE_TYPE xResult;\r
+\r
+ // Co-routines must begin with a call to crSTART().\r
+ crSTART( xHandle );\r
+\r
+ for( ;; )\r
+ {\r
+ // This assumes the queue has already been created.\r
+ crQUEUE_SEND( xHandle, xCoRoutineQueue, &xNumberToPost, NO_DELAY, &xResult );\r
+\r
+ if( xResult != pdPASS )\r
+ {\r
+ // The message was not posted!\r
+ }\r
+\r
+ // Increment the number to be posted onto the queue.\r
+ xNumberToPost++;\r
+ \r
+ // Delay for 100 ticks.\r
+ crDELAY( xHandle, 100 );\r
+ }\r
+\r
+ // Co-routines must end with a call to crEND().\r
+ crEND();\r
+ }</pre>\r
+ * \defgroup crQUEUE_SEND crQUEUE_SEND\r
+ * \ingroup Tasks\r
+ */\r
+#define crQUEUE_SEND( xHandle, pxQueue, pvItemToQueue, xTicksToWait, pxResult ) \\r
+{ \\r
+ *pxResult = xQueueCRSend( pxQueue, pvItemToQueue, xTicksToWait ); \\r
+ if( *pxResult == errQUEUE_BLOCKED ) \\r
+ { \\r
+ crSET_STATE0( xHandle ); \\r
+ *pxResult = xQueueCRSend( pxQueue, pvItemToQueue, 0 ); \\r
+ } \\r
+ if( *pxResult == errQUEUE_YIELD ) \\r
+ { \\r
+ crSET_STATE1( xHandle ); \\r
+ *pxResult = pdPASS; \\r
+ } \\r
+}\r
+\r
+/**\r
+ * croutine. h\r
+ * <pre>\r
+ crQUEUE_RECEIVE( \r
+ xCoRoutineHandle xHandle, \r
+ xQueueHandle pxQueue, \r
+ void *pvBuffer, \r
+ portTickType xTicksToWait, \r
+ portBASE_TYPE *pxResult \r
+ )</pre>\r
+ *\r
+ * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine \r
+ * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks. \r
+ *\r
+ * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas \r
+ * xQueueSend() and xQueueReceive() can only be used from tasks.\r
+ *\r
+ * crQUEUE_RECEIVE can only be called from the co-routine function itself - not\r
+ * from within a function called by the co-routine function. This is because\r
+ * co-routines do not maintain their own stack.\r
+ *\r
+ * See the co-routine section of the WEB documentation for information on \r
+ * passing data between tasks and co-routines and between ISR's and \r
+ * co-routines.\r
+ *\r
+ * @param xHandle The handle of the calling co-routine. This is the xHandle\r
+ * parameter of the co-routine function.\r
+ *\r
+ * @param pxQueue The handle of the queue from which the data will be received. \r
+ * The handle is obtained as the return value when the queue is created using \r
+ * the xQueueCreate() API function.\r
+ *\r
+ * @param pvBuffer The buffer into which the received item is to be copied.\r
+ * The number of bytes of each queued item is specified when the queue is\r
+ * created. This number of bytes is copied into pvBuffer.\r
+ *\r
+ * @param xTickToDelay The number of ticks that the co-routine should block \r
+ * to wait for data to become available from the queue, should data not be\r
+ * available immediately. The actual amount of time this equates to is defined \r
+ * by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant \r
+ * portTICK_RATE_MS can be used to convert ticks to milliseconds (see the\r
+ * crQUEUE_SEND example).\r
+ *\r
+ * @param pxResult The variable pointed to by pxResult will be set to pdPASS if\r
+ * data was successfully retrieved from the queue, otherwise it will be set to\r
+ * an error code as defined within ProjDefs.h.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ // A co-routine receives the number of an LED to flash from a queue. It \r
+ // blocks on the queue until the number is received.\r
+ static void prvCoRoutineFlashWorkTask( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )\r
+ {\r
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.\r
+ static portBASE_TYPE xResult;\r
+ static unsigned portBASE_TYPE uxLEDToFlash;\r
+\r
+ // All co-routines must start with a call to crSTART().\r
+ crSTART( xHandle );\r
+\r
+ for( ;; )\r
+ {\r
+ // Wait for data to become available on the queue.\r
+ crQUEUE_RECEIVE( xHandle, xCoRoutineQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );\r
+\r
+ if( xResult == pdPASS )\r
+ {\r
+ // We received the LED to flash - flash it!\r
+ vParTestToggleLED( uxLEDToFlash );\r
+ }\r
+ }\r
+\r
+ crEND();\r
+ }</pre>\r
+ * \defgroup crQUEUE_RECEIVE crQUEUE_RECEIVE\r
+ * \ingroup Tasks\r
+ */\r
+#define crQUEUE_RECEIVE( xHandle, pxQueue, pvBuffer, xTicksToWait, pxResult ) \\r
+{ \\r
+ *pxResult = xQueueCRReceive( pxQueue, pvBuffer, xTicksToWait ); \\r
+ if( *pxResult == errQUEUE_BLOCKED ) \\r
+ { \\r
+ crSET_STATE0( xHandle ); \\r
+ *pxResult = xQueueCRReceive( pxQueue, pvBuffer, 0 ); \\r
+ } \\r
+ if( *pxResult == errQUEUE_YIELD ) \\r
+ { \\r
+ crSET_STATE1( xHandle ); \\r
+ *pxResult = pdPASS; \\r
+ } \\r
+}\r
+\r
+/**\r
+ * croutine. h\r
+ * <pre>\r
+ crQUEUE_SEND_FROM_ISR( \r
+ xQueueHandle pxQueue, \r
+ void *pvItemToQueue, \r
+ portBASE_TYPE xCoRoutinePreviouslyWoken\r
+ )</pre>\r
+ *\r
+ * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the \r
+ * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR() \r
+ * functions used by tasks. \r
+ *\r
+ * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to\r
+ * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and \r
+ * xQueueReceiveFromISR() can only be used to pass data between a task and and\r
+ * ISR.\r
+ *\r
+ * crQUEUE_SEND_FROM_ISR can only be called from an ISR to send data to a queue\r
+ * that is being used from within a co-routine.\r
+ *\r
+ * See the co-routine section of the WEB documentation for information on \r
+ * passing data between tasks and co-routines and between ISR's and \r
+ * co-routines.\r
+ *\r
+ * @param xQueue The handle to the queue on which the item is to be posted.\r
+ * \r
+ * @param pvItemToQueue A pointer to the item that is to be placed on the \r
+ * queue. The size of the items the queue will hold was defined when the\r
+ * queue was created, so this many bytes will be copied from pvItemToQueue\r
+ * into the queue storage area.\r
+ *\r
+ * @param xCoRoutinePreviouslyWoken This is included so an ISR can post onto\r
+ * the same queue multiple times from a single interrupt. The first call\r
+ * should always pass in pdFALSE. Subsequent calls should pass in\r
+ * the value returned from the previous call. \r
+ *\r
+ * @return pdTRUE if a co-routine was woken by posting onto the queue. This is \r
+ * used by the ISR to determine if a context switch may be required following\r
+ * the ISR.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ // A co-routine that blocks on a queue waiting for characters to be received.\r
+ static void vReceivingCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )\r
+ {\r
+ portCHAR cRxedChar;\r
+ portBASE_TYPE xResult;\r
+\r
+ // All co-routines must start with a call to crSTART().\r
+ crSTART( xHandle );\r
+\r
+ for( ;; )\r
+ {\r
+ // Wait for data to become available on the queue. This assumes the\r
+ // queue xCommsRxQueue has already been created!\r
+ crQUEUE_RECEIVE( xHandle, xCommsRxQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );\r
+ \r
+ // Was a character received?\r
+ if( xResult == pdPASS )\r
+ {\r
+ // Process the character here.\r
+ }\r
+ }\r
+\r
+ // All co-routines must end with a call to crEND().\r
+ crEND();\r
+ }\r
+\r
+ // An ISR that uses a queue to send characters received on a serial port to\r
+ // a co-routine.\r
+ void vUART_ISR( void )\r
+ {\r
+ portCHAR cRxedChar;\r
+ portBASE_TYPE xCRWokenByPost = pdFALSE;\r
+\r
+ // We loop around reading characters until there are none left in the UART.\r
+ while( UART_RX_REG_NOT_EMPTY() )\r
+ {\r
+ // Obtain the character from the UART.\r
+ cRxedChar = UART_RX_REG;\r
+ \r
+ // Post the character onto a queue. xCRWokenByPost will be pdFALSE \r
+ // the first time around the loop. If the post causes a co-routine\r
+ // to be woken (unblocked) then xCRWokenByPost will be set to pdTRUE.\r
+ // In this manner we can ensure that if more than one co-routine is\r
+ // blocked on the queue only one is woken by this ISR no matter how\r
+ // many characters are posted to the queue.\r
+ xCRWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsRxQueue, &cRxedChar, xCRWokenByPost );\r
+ }\r
+ }</pre>\r
+ * \defgroup crQUEUE_SEND_FROM_ISR crQUEUE_SEND_FROM_ISR\r
+ * \ingroup Tasks\r
+ */\r
+#define crQUEUE_SEND_FROM_ISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) xQueueCRSendFromISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken )\r
+\r
+\r
+/**\r
+ * croutine. h\r
+ * <pre>\r
+ crQUEUE_SEND_FROM_ISR( \r
+ xQueueHandle pxQueue, \r
+ void *pvBuffer, \r
+ portBASE_TYPE * pxCoRoutineWoken\r
+ )</pre>\r
+ *\r
+ * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the \r
+ * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR() \r
+ * functions used by tasks. \r
+ *\r
+ * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to\r
+ * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and \r
+ * xQueueReceiveFromISR() can only be used to pass data between a task and and\r
+ * ISR.\r
+ *\r
+ * crQUEUE_RECEIVE_FROM_ISR can only be called from an ISR to receive data \r
+ * from a queue that is being used from within a co-routine (a co-routine\r
+ * posted to the queue).\r
+ *\r
+ * See the co-routine section of the WEB documentation for information on \r
+ * passing data between tasks and co-routines and between ISR's and \r
+ * co-routines.\r
+ *\r
+ * @param xQueue The handle to the queue on which the item is to be posted.\r
+ * \r
+ * @param pvBuffer A pointer to a buffer into which the received item will be\r
+ * placed. The size of the items the queue will hold was defined when the\r
+ * queue was created, so this many bytes will be copied from the queue into\r
+ * pvBuffer.\r
+ *\r
+ * @param pxCoRoutineWoken A co-routine may be blocked waiting for space to become\r
+ * available on the queue. If crQUEUE_RECEIVE_FROM_ISR causes such a \r
+ * co-routine to unblock *pxCoRoutineWoken will get set to pdTRUE, otherwise \r
+ * *pxCoRoutineWoken will remain unchanged.\r
+ *\r
+ * @return pdTRUE an item was successfully received from the queue, otherwise\r
+ * pdFALSE.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ // A co-routine that posts a character to a queue then blocks for a fixed \r
+ // period. The character is incremented each time.\r
+ static void vSendingCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )\r
+ {\r
+ // cChar holds its value while this co-routine is blocked and must therefore\r
+ // be declared static.\r
+ static portCHAR cCharToTx = 'a';\r
+ portBASE_TYPE xResult;\r
+\r
+ // All co-routines must start with a call to crSTART().\r
+ crSTART( xHandle );\r
+\r
+ for( ;; )\r
+ {\r
+ // Send the next character to the queue.\r
+ crQUEUE_SEND( xHandle, xCoRoutineQueue, &cCharToTx, NO_DELAY, &xResult );\r
+ \r
+ if( xResult == pdPASS )\r
+ {\r
+ // The character was successfully posted to the queue.\r
+ }\r
+ else\r
+ {\r
+ // Could not post the character to the queue.\r
+ }\r
+\r
+ // Enable the UART Tx interrupt to cause an interrupt in this\r
+ // hypothetical UART. The interrupt will obtain the character\r
+ // from the queue and send it.\r
+ ENABLE_RX_INTERRUPT();\r
+\r
+ // Increment to the next character then block for a fixed period. \r
+ // cCharToTx will maintain its value across the delay as it is\r
+ // declared static.\r
+ cCharToTx++;\r
+ if( cCharToTx > 'x' )\r
+ {\r
+ cCharToTx = 'a';\r
+ }\r
+ crDELAY( 100 );\r
+ }\r
+\r
+ // All co-routines must end with a call to crEND().\r
+ crEND();\r
+ }\r
+\r
+ // An ISR that uses a queue to receive characters to send on a UART.\r
+ void vUART_ISR( void )\r
+ {\r
+ portCHAR cCharToTx;\r
+ portBASE_TYPE xCRWokenByPost = pdFALSE;\r
+\r
+ while( UART_TX_REG_EMPTY() )\r
+ {\r
+ // Are there any characters in the queue waiting to be sent?\r
+ // xCRWokenByPost will automatically be set to pdTRUE if a co-routine\r
+ // is woken by the post - ensuring that only a single co-routine is\r
+ // woken no matter how many times we go around this loop.\r
+ if( crQUEUE_RECEIVE_FROM_ISR( pxQueue, &cCharToTx, &xCRWokenByPost ) )\r
+ {\r
+ SEND_CHARACTER( cCharToTx );\r
+ }\r
+ }\r
+ }</pre>\r
+ * \defgroup crQUEUE_RECEIVE_FROM_ISR crQUEUE_RECEIVE_FROM_ISR\r
+ * \ingroup Tasks\r
+ */\r
+#define crQUEUE_RECEIVE_FROM_ISR( pxQueue, pvBuffer, pxCoRoutineWoken ) xQueueCRReceiveFromISR( pxQueue, pvBuffer, pxCoRoutineWoken )\r
+\r
+/*\r
+ * This function is intended for internal use by the co-routine macros only.\r
+ * The macro nature of the co-routine implementation requires that the \r
+ * prototype appears here. The function should not be used by application \r
+ * writers.\r
+ *\r
+ * Removes the current co-routine from its ready list and places it in the \r
+ * appropriate delayed list.\r
+ */\r
+void vCoRoutineAddToDelayedList( portTickType xTicksToDelay, xList *pxEventList );\r
+\r
+/*\r
+ * This function is intended for internal use by the queue implementation only.\r
+ * The function should not be used by application writers.\r
+ *\r
+ * Removes the highest priority co-routine from the event list and places it in\r
+ * the pending ready list.\r
+ */\r
+portBASE_TYPE xCoRoutineRemoveFromEventList( const xList *pxEventList );\r
+\r
+\r
+#endif /* CO_ROUTINE_H */\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+ * This is the list implementation used by the scheduler. While it is tailored\r
+ * heavily for the schedulers needs, it is also available for use by\r
+ * application code.\r
+ *\r
+ * xLists can only store pointers to xListItems. Each xListItem contains a\r
+ * numeric value (xItemValue). Most of the time the lists are sorted in\r
+ * descending item value order.\r
+ *\r
+ * Lists are created already containing one list item. The value of this\r
+ * item is the maximum possible that can be stored, it is therefore always at\r
+ * the end of the list and acts as a marker. The list member pxHead always\r
+ * points to this marker - even though it is at the tail of the list. This\r
+ * is because the tail contains a wrap back pointer to the true head of\r
+ * the list.\r
+ *\r
+ * In addition to it's value, each list item contains a pointer to the next\r
+ * item in the list (pxNext), a pointer to the list it is in (pxContainer)\r
+ * and a pointer to back to the object that contains it. These later two\r
+ * pointers are included for efficiency of list manipulation. There is\r
+ * effectively a two way link between the object containing the list item and\r
+ * the list item itself.\r
+ *\r
+ *\r
+ * \page ListIntroduction List Implementation\r
+ * \ingroup FreeRTOSIntro\r
+ */\r
+\r
+\r
+#ifndef LIST_H\r
+#define LIST_H\r
+\r
+/*\r
+ * Definition of the only type of object that a list can contain.\r
+ */\r
+struct xLIST_ITEM\r
+{\r
+ portTickType xItemValue; /*< The value being listed. In most cases this is used to sort the list in descending order. */\r
+ volatile struct xLIST_ITEM * pxNext; /*< Pointer to the next xListItem in the list. */\r
+ volatile struct xLIST_ITEM * pxPrevious;/*< Pointer to the previous xListItem in the list. */\r
+ void * pvOwner; /*< Pointer to the object (normally a TCB) that contains the list item. There is therefore a two way link between the object containing the list item and the list item itself. */\r
+ void * pvContainer; /*< Pointer to the list in which this list item is placed (if any). */\r
+};\r
+typedef struct xLIST_ITEM xListItem; /* For some reason lint wants this as two separate definitions. */\r
+\r
+struct xMINI_LIST_ITEM\r
+{\r
+ portTickType xItemValue;\r
+ volatile struct xLIST_ITEM *pxNext;\r
+ volatile struct xLIST_ITEM *pxPrevious;\r
+};\r
+typedef struct xMINI_LIST_ITEM xMiniListItem;\r
+\r
+/*\r
+ * Definition of the type of queue used by the scheduler.\r
+ */\r
+typedef struct xLIST\r
+{\r
+ volatile unsigned portBASE_TYPE uxNumberOfItems;\r
+ volatile xListItem * pxIndex; /*< Used to walk through the list. Points to the last item returned by a call to pvListGetOwnerOfNextEntry (). */\r
+ volatile xMiniListItem xListEnd; /*< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */\r
+} xList;\r
+\r
+/*\r
+ * Access macro to set the owner of a list item. The owner of a list item\r
+ * is the object (usually a TCB) that contains the list item.\r
+ *\r
+ * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER\r
+ * \ingroup LinkedList\r
+ */\r
+#define listSET_LIST_ITEM_OWNER( pxListItem, pxOwner ) ( pxListItem )->pvOwner = ( void * ) pxOwner\r
+\r
+/*\r
+ * Access macro to set the value of the list item. In most cases the value is\r
+ * used to sort the list in descending order.\r
+ *\r
+ * \page listSET_LIST_ITEM_VALUE listSET_LIST_ITEM_VALUE\r
+ * \ingroup LinkedList\r
+ */\r
+#define listSET_LIST_ITEM_VALUE( pxListItem, xValue ) ( pxListItem )->xItemValue = xValue\r
+\r
+/*\r
+ * Access macro the retrieve the value of the list item. The value can\r
+ * represent anything - for example a the priority of a task, or the time at\r
+ * which a task should be unblocked.\r
+ *\r
+ * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE\r
+ * \ingroup LinkedList\r
+ */\r
+#define listGET_LIST_ITEM_VALUE( pxListItem ) ( ( pxListItem )->xItemValue )\r
+\r
+/*\r
+ * Access macro to determine if a list contains any items. The macro will\r
+ * only have the value true if the list is empty.\r
+ *\r
+ * \page listLIST_IS_EMPTY listLIST_IS_EMPTY\r
+ * \ingroup LinkedList\r
+ */\r
+#define listLIST_IS_EMPTY( pxList ) ( ( pxList )->uxNumberOfItems == ( unsigned portBASE_TYPE ) 0 )\r
+\r
+/*\r
+ * Access macro to return the number of items in the list.\r
+ */\r
+#define listCURRENT_LIST_LENGTH( pxList ) ( ( pxList )->uxNumberOfItems )\r
+\r
+/*\r
+ * Access function to obtain the owner of the next entry in a list.\r
+ *\r
+ * The list member pxIndex is used to walk through a list. Calling\r
+ * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list\r
+ * and returns that entries pxOwner parameter. Using multiple calls to this\r
+ * function it is therefore possible to move through every item contained in\r
+ * a list.\r
+ *\r
+ * The pxOwner parameter of a list item is a pointer to the object that owns\r
+ * the list item. In the scheduler this is normally a task control block.\r
+ * The pxOwner parameter effectively creates a two way link between the list\r
+ * item and its owner.\r
+ *\r
+ * @param pxList The list from which the next item owner is to be returned.\r
+ *\r
+ * \page listGET_OWNER_OF_NEXT_ENTRY listGET_OWNER_OF_NEXT_ENTRY\r
+ * \ingroup LinkedList\r
+ */\r
+#define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList ) \\r
+ /* Increment the index to the next item and return the item, ensuring */ \\r
+ /* we don't return the marker used at the end of the list. */ \\r
+ ( pxList )->pxIndex = ( pxList )->pxIndex->pxNext; \\r
+ if( ( pxList )->pxIndex == ( xListItem * ) &( ( pxList )->xListEnd ) ) \\r
+ { \\r
+ ( pxList )->pxIndex = ( pxList )->pxIndex->pxNext; \\r
+ } \\r
+ pxTCB = ( pxList )->pxIndex->pvOwner\r
+\r
+\r
+/*\r
+ * Access function to obtain the owner of the first entry in a list. Lists\r
+ * are normally sorted in ascending item value order.\r
+ *\r
+ * This function returns the pxOwner member of the first item in the list.\r
+ * The pxOwner parameter of a list item is a pointer to the object that owns\r
+ * the list item. In the scheduler this is normally a task control block.\r
+ * The pxOwner parameter effectively creates a two way link between the list\r
+ * item and its owner.\r
+ *\r
+ * @param pxList The list from which the owner of the head item is to be\r
+ * returned.\r
+ *\r
+ * \page listGET_OWNER_OF_HEAD_ENTRY listGET_OWNER_OF_HEAD_ENTRY\r
+ * \ingroup LinkedList\r
+ */\r
+#define listGET_OWNER_OF_HEAD_ENTRY( pxList ) ( ( pxList->uxNumberOfItems != ( unsigned portBASE_TYPE ) 0 ) ? ( (&( pxList->xListEnd ))->pxNext->pvOwner ) : ( NULL ) )\r
+\r
+/*\r
+ * Check to see if a list item is within a list. The list item maintains a\r
+ * "container" pointer that points to the list it is in. All this macro does\r
+ * is check to see if the container and the list match.\r
+ *\r
+ * @param pxList The list we want to know if the list item is within.\r
+ * @param pxListItem The list item we want to know if is in the list.\r
+ * @return pdTRUE is the list item is in the list, otherwise pdFALSE.\r
+ * pointer against\r
+ */\r
+#define listIS_CONTAINED_WITHIN( pxList, pxListItem ) ( ( pxListItem )->pvContainer == ( void * ) pxList )\r
+\r
+/*\r
+ * Must be called before a list is used! This initialises all the members\r
+ * of the list structure and inserts the xListEnd item into the list as a\r
+ * marker to the back of the list.\r
+ *\r
+ * @param pxList Pointer to the list being initialised.\r
+ *\r
+ * \page vListInitialise vListInitialise\r
+ * \ingroup LinkedList\r
+ */\r
+void vListInitialise( xList *pxList );\r
+\r
+/*\r
+ * Must be called before a list item is used. This sets the list container to\r
+ * null so the item does not think that it is already contained in a list.\r
+ *\r
+ * @param pxItem Pointer to the list item being initialised.\r
+ *\r
+ * \page vListInitialiseItem vListInitialiseItem\r
+ * \ingroup LinkedList\r
+ */\r
+void vListInitialiseItem( xListItem *pxItem );\r
+\r
+/*\r
+ * Insert a list item into a list. The item will be inserted into the list in\r
+ * a position determined by its item value (descending item value order).\r
+ *\r
+ * @param pxList The list into which the item is to be inserted.\r
+ *\r
+ * @param pxNewListItem The item to that is to be placed in the list.\r
+ *\r
+ * \page vListInsert vListInsert\r
+ * \ingroup LinkedList\r
+ */\r
+void vListInsert( xList *pxList, xListItem *pxNewListItem );\r
+\r
+/*\r
+ * Insert a list item into a list. The item will be inserted in a position\r
+ * such that it will be the last item within the list returned by multiple\r
+ * calls to listGET_OWNER_OF_NEXT_ENTRY.\r
+ *\r
+ * The list member pvIndex is used to walk through a list. Calling\r
+ * listGET_OWNER_OF_NEXT_ENTRY increments pvIndex to the next item in the list.\r
+ * Placing an item in a list using vListInsertEnd effectively places the item\r
+ * in the list position pointed to by pvIndex. This means that every other\r
+ * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before\r
+ * the pvIndex parameter again points to the item being inserted.\r
+ *\r
+ * @param pxList The list into which the item is to be inserted.\r
+ *\r
+ * @param pxNewListItem The list item to be inserted into the list.\r
+ *\r
+ * \page vListInsertEnd vListInsertEnd\r
+ * \ingroup LinkedList\r
+ */\r
+void vListInsertEnd( xList *pxList, xListItem *pxNewListItem );\r
+\r
+/*\r
+ * Remove an item from a list. The list item has a pointer to the list that\r
+ * it is in, so only the list item need be passed into the function.\r
+ *\r
+ * @param vListRemove The item to be removed. The item will remove itself from\r
+ * the list pointed to by it's pxContainer parameter.\r
+ *\r
+ * \page vListRemove vListRemove\r
+ * \ingroup LinkedList\r
+ */\r
+void vListRemove( xListItem *pxItemToRemove );\r
+\r
+\r
+\r
+#endif\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http:www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http:www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Portable layer API. Each function must be defined for each port.\r
+ *----------------------------------------------------------*/\r
+\r
+#ifndef PORTABLE_H\r
+#define PORTABLE_H\r
+\r
+/* Include the macro file relevant to the port being used. */\r
+\r
+#ifdef OPEN_WATCOM_INDUSTRIAL_PC_PORT\r
+ #include "..\..\source\portable\owatcom\16bitdos\pc\portmacro.h"\r
+ typedef void ( __interrupt __far *pxISR )();\r
+#endif\r
+\r
+#ifdef OPEN_WATCOM_FLASH_LITE_186_PORT\r
+ #include "..\..\source\portable\owatcom\16bitdos\flsh186\portmacro.h"\r
+ typedef void ( __interrupt __far *pxISR )();\r
+#endif\r
+\r
+#ifdef GCC_MEGA_AVR\r
+ #include "../portable/GCC/ATMega323/portmacro.h"\r
+#endif\r
+\r
+#ifdef IAR_MEGA_AVR\r
+ #include "../portable/IAR/ATMega323/portmacro.h"\r
+#endif\r
+\r
+#ifdef MPLAB_PIC18F_PORT\r
+ #include "..\..\source\portable\MPLAB\PIC18F\portmacro.h"\r
+#endif\r
+\r
+#ifdef _FEDPICC\r
+ #include "libFreeRTOS/Include/portmacro.h"\r
+#endif\r
+\r
+#ifdef SDCC_CYGNAL\r
+ #include "../../Source/portable/SDCC/Cygnal/portmacro.h"\r
+#endif\r
+\r
+#ifdef GCC_ARM7\r
+ #include "../../Source/portable/GCC/ARM7_LPC2000/portmacro.h"\r
+#endif\r
+\r
+#ifdef GCC_MSP430\r
+ #include "../../Source/portable/GCC/MSP430F449/portmacro.h"\r
+#endif\r
+\r
+#ifdef ROWLEY_MSP430\r
+ #include "../../Source/portable/Rowley/MSP430F449/portmacro.h"\r
+#endif\r
+\r
+#ifdef KEIL_ARM7\r
+ #include "..\..\Source\portable\Keil\ARM7\portmacro.h"\r
+#endif\r
+\r
+#ifdef SAM7_GCC\r
+ #include "../../Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h"\r
+#endif\r
+\r
+#ifdef SAM7_IAR\r
+ #include "..\..\Source\portable\IAR\AtmelSAM7S64\portmacro.h"\r
+#endif\r
+\r
+#ifdef LPC2000_IAR\r
+ #include "..\..\Source\portable\IAR\LPC2000\portmacro.h"\r
+#endif\r
+\r
+#ifdef STR71X_IAR\r
+ #include "..\..\Source\portable\IAR\STR71x\portmacro.h"\r
+#endif\r
+\r
+#ifdef GCC_H8S\r
+ #include "../../Source/portable/GCC/H8S2329/portmacro.h"\r
+#endif\r
+\r
+#ifdef GCC_AT91FR40008\r
+ #include "../../Source/portable/GCC/ARM7_AT91FR40008/portmacro.h"\r
+#endif\r
+\r
+#ifdef RVDS_ARMCM3_LM3S102\r
+ #include "../../Source/portable/RVDS/ARM_CM3/portmacro.h"\r
+#endif\r
+\r
+#ifdef GCC_ARMCM3_LM3S102\r
+ #include "../../Source/portable/GCC/ARM_CM3/portmacro.h"\r
+#endif\r
+\r
+#ifdef HCS12_CODE_WARRIOR\r
+ #include "../../Source/portable/CodeWarrior/HCS12/portmacro.h"\r
+#endif \r
+\r
+#ifdef MICROBLAZE_GCC\r
+ #include "../../Source/portable/GCC/MicroBlaze/portmacro.h"\r
+#endif\r
+\r
+#ifdef BCC_INDUSTRIAL_PC_PORT\r
+ /* A short file name has to be used in place of the normal\r
+ FreeRTOSConfig.h when using the Borland compiler. */\r
+ #include "frconfig.h"\r
+ #include "..\portable\BCC\16BitDOS\PC\prtmacro.h"\r
+ typedef void ( __interrupt __far *pxISR )();\r
+#endif\r
+\r
+#ifdef BCC_FLASH_LITE_186_PORT\r
+ /* A short file name has to be used in place of the normal\r
+ FreeRTOSConfig.h when using the Borland compiler. */\r
+ #include "frconfig.h"\r
+ #include "..\portable\BCC\16BitDOS\flsh186\prtmacro.h"\r
+ typedef void ( __interrupt __far *pxISR )();\r
+#endif\r
+/*\r
+ * Setup the stack of a new task so it is ready to be placed under the\r
+ * scheduler control. The registers have to be placed on the stack in\r
+ * the order that the port expects to find them.\r
+ */\r
+portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters );\r
+\r
+/*\r
+ * Map to the memory management routines required for the port.\r
+ */\r
+void *pvPortMalloc( size_t xSize );\r
+void vPortFree( void *pv );\r
+void vPortInitialiseBlocks( void );\r
+\r
+/*\r
+ * Setup the hardware ready for the scheduler to take control. This generally\r
+ * sets up a tick interrupt and sets timers for the correct tick frequency.\r
+ */\r
+portBASE_TYPE xPortStartScheduler( void );\r
+\r
+/*\r
+ * Undo any hardware/ISR setup that was performed by xPortStartScheduler() so\r
+ * the hardware is left in its original condition after the scheduler stops\r
+ * executing.\r
+ */\r
+void vPortEndScheduler( void );\r
+\r
+\r
+#endif /* PORTABLE_H */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef PROJDEFS_H\r
+#define PROJDEFS_H\r
+\r
+/* Defines to prototype to which task functions must conform. */\r
+typedef void (*pdTASK_CODE)( void * );\r
+\r
+#define pdTRUE ( 1 )\r
+#define pdFALSE ( 0 )\r
+\r
+#define pdPASS ( 1 )\r
+#define pdFAIL ( 0 )\r
+\r
+/* Error definitions. */\r
+#define errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY ( -1 )\r
+#define errNO_TASK_TO_RUN ( -2 )\r
+#define errQUEUE_FULL ( -3 )\r
+#define errQUEUE_BLOCKED ( -4 )\r
+#define errQUEUE_YIELD ( -5 )\r
+\r
+#endif\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef QUEUE_H\r
+#define QUEUE_H\r
+\r
+typedef void * xQueueHandle;\r
+\r
+/**\r
+ * queue. h\r
+ * <pre>\r
+ xQueueHandle xQueueCreate( \r
+ unsigned portBASE_TYPE uxQueueLength, \r
+ unsigned portBASE_TYPE uxItemSize \r
+ );\r
+ * </pre>\r
+ *\r
+ * Creates a new queue instance. This allocates the storage required by the\r
+ * new queue and returns a handle for the queue.\r
+ *\r
+ * @param uxQueueLength The maximum number of items that the queue can contain.\r
+ *\r
+ * @param uxItemSize The number of bytes each item in the queue will require. \r
+ * Items are queued by copy, not by reference, so this is the number of bytes\r
+ * that will be copied for each posted item. Each item on the queue must be\r
+ * the same size.\r
+ *\r
+ * @return If the queue is successfully create then a handle to the newly \r
+ * created queue is returned. If the queue cannot be created then 0 is\r
+ * returned.\r
+ * \r
+ * Example usage:\r
+ <pre>\r
+ struct AMessage\r
+ {\r
+ portCHAR ucMessageID;\r
+ portCHAR ucData[ 20 ];\r
+ };\r
+\r
+ void vATask( void *pvParameters )\r
+ {\r
+ xQueueHandle xQueue1, xQueue2;\r
+\r
+ // Create a queue capable of containing 10 unsigned long values.\r
+ xQueue1 = xQueueCreate( 10, sizeof( unsigned portLONG ) );\r
+ if( xQueue1 == 0 )\r
+ {\r
+ // Queue was not created and must not be used.\r
+ }\r
+\r
+ // Create a queue capable of containing 10 pointers to AMessage structures.\r
+ // These should be passed by pointer as they contain a lot of data.\r
+ xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );\r
+ if( xQueue2 == 0 )\r
+ {\r
+ // Queue was not created and must not be used.\r
+ }\r
+\r
+ // ... Rest of task code.\r
+ }\r
+ </pre>\r
+ * \defgroup xQueueCreate xQueueCreate\r
+ * \ingroup QueueManagement\r
+ */\r
+xQueueHandle xQueueCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize );\r
+\r
+/**\r
+ * queue. h\r
+ * <pre>\r
+ portBASE_TYPE xQueueSend( \r
+ xQueueHandle xQueue, \r
+ const void * pvItemToQueue, \r
+ portTickType xTicksToWait \r
+ );\r
+ * </pre>\r
+ *\r
+ * Post an item on a queue. The item is queued by copy, not by reference.\r
+ * This function must not be called from an interrupt service routine.\r
+ * See xQueueSendFromISR () for an alternative which may be used in an ISR.\r
+ *\r
+ * @param xQueue The handle to the queue on which the item is to be posted.\r
+ * \r
+ * @param pvItemToQueue A pointer to the item that is to be placed on the \r
+ * queue. The size of the items the queue will hold was defined when the\r
+ * queue was created, so this many bytes will be copied from pvItemToQueue\r
+ * into the queue storage area.\r
+ *\r
+ * @param xTicksToWait The maximum amount of time the task should block\r
+ * waiting for space to become available on the queue, should it already\r
+ * be full. The call will return immediately if this is set to 0. The\r
+ * time is defined in tick periods so the constant portTICK_RATE_MS \r
+ * should be used to convert to real time if this is required.\r
+ *\r
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ struct AMessage\r
+ {\r
+ portCHAR ucMessageID;\r
+ portCHAR ucData[ 20 ];\r
+ } xMessage;\r
+\r
+ unsigned portLONG ulVar = 10UL;\r
+\r
+ void vATask( void *pvParameters )\r
+ {\r
+ xQueueHandle xQueue1, xQueue2;\r
+ struct AMessage *pxMessage;\r
+\r
+ // Create a queue capable of containing 10 unsigned long values.\r
+ xQueue1 = xQueueCreate( 10, sizeof( unsigned portLONG ) );\r
+\r
+ // Create a queue capable of containing 10 pointers to AMessage structures.\r
+ // These should be passed by pointer as they contain a lot of data.\r
+ xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );\r
+\r
+ // ...\r
+\r
+ if( xQueue1 != 0 )\r
+ {\r
+ // Send an unsigned long. Wait for 10 ticks for space to become \r
+ // available if necessary.\r
+ if( xQueueSend( xQueue1, ( void * ) &ulVar, ( portTickType ) 10 ) != pdPASS )\r
+ {\r
+ // Failed to post the message, even after 10 ticks.\r
+ }\r
+ }\r
+\r
+ if( xQueue2 != 0 )\r
+ {\r
+ // Send a pointer to a struct AMessage object. Don't block if the\r
+ // queue is already full.\r
+ pxMessage = & xMessage;\r
+ xQueueSend( xQueue2, ( void * ) &pxMessage, ( portTickType ) 0 );\r
+ }\r
+\r
+ // ... Rest of task code.\r
+ }\r
+ </pre>\r
+ * \defgroup xQueueSend xQueueSend\r
+ * \ingroup QueueManagement\r
+ */\r
+signed portBASE_TYPE xQueueSend( xQueueHandle xQueue, const void * pvItemToQueue, portTickType xTicksToWait );\r
+\r
+/**\r
+ * queue. h\r
+ * <pre>\r
+ portBASE_TYPE xQueueReceive( \r
+ xQueueHandle xQueue, \r
+ void *pvBuffer, \r
+ portTickType xTicksToWait \r
+ );</pre>\r
+ *\r
+ * Receive an item from a queue. The item is received by copy so a buffer of \r
+ * adequate size must be provided. The number of bytes copied into the buffer\r
+ * was defined when the queue was created.\r
+ *\r
+ * This function must not be used in an interrupt service routine. See\r
+ * xQueueReceiveFromISR for an alternative that can.\r
+ *\r
+ * @param pxQueue The handle to the queue from which the item is to be\r
+ * received.\r
+ *\r
+ * @param pvBuffer Pointer to the buffer into which the received item will\r
+ * be copied.\r
+ * \r
+ * @param xTicksToWait The maximum amount of time the task should block\r
+ * waiting for an item to receive should the queue be empty at the time\r
+ * of the call. The time is defined in tick periods so the constant \r
+ * portTICK_RATE_MS should be used to convert to real time if this is required.\r
+ *\r
+ * @return pdTRUE if an item was successfully received from the queue,\r
+ * otherwise pdFALSE.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ struct AMessage\r
+ {\r
+ portCHAR ucMessageID;\r
+ portCHAR ucData[ 20 ];\r
+ } xMessage;\r
+\r
+ xQueueHandle xQueue;\r
+ \r
+ // Task to create a queue and post a value.\r
+ void vATask( void *pvParameters )\r
+ {\r
+ struct AMessage *pxMessage;\r
+\r
+ // Create a queue capable of containing 10 pointers to AMessage structures.\r
+ // These should be passed by pointer as they contain a lot of data.\r
+ xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );\r
+ if( xQueue == 0 )\r
+ {\r
+ // Failed to create the queue.\r
+ }\r
+\r
+ // ...\r
+\r
+ // Send a pointer to a struct AMessage object. Don't block if the\r
+ // queue is already full.\r
+ pxMessage = & xMessage;\r
+ xQueueSend( xQueue, ( void * ) &pxMessage, ( portTickType ) 0 );\r
+\r
+ // ... Rest of task code.\r
+ }\r
+\r
+ // Task to receive from the queue.\r
+ void vADifferentTask( void *pvParameters )\r
+ {\r
+ struct AMessage *pxRxedMessage;\r
+\r
+ if( xQueue != 0 )\r
+ {\r
+ // Receive a message on the created queue. Block for 10 ticks if a\r
+ // message is not immediately available.\r
+ if( xQueueReceive( xQueue, &( pxRxedMessage ), ( portTickType ) 10 ) )\r
+ {\r
+ // pcRxedMessage now points to the struct AMessage variable posted\r
+ // by vATask.\r
+ }\r
+ }\r
+\r
+ // ... Rest of task code.\r
+ }\r
+ </pre>\r
+ * \defgroup xQueueReceive xQueueReceive\r
+ * \ingroup QueueManagement\r
+ */\r
+signed portBASE_TYPE xQueueReceive( xQueueHandle xQueue, void *pvBuffer, portTickType xTicksToWait );\r
+\r
+/**\r
+ * queue. h\r
+ * <pre>unsigned portBASE_TYPE uxQueueMessagesWaiting( xQueueHandle xQueue );</pre>\r
+ *\r
+ * Return the number of messages stored in a queue.\r
+ *\r
+ * @param xQueue A handle to the queue being queried.\r
+ * \r
+ * @return The number of messages available in the queue.\r
+ *\r
+ * \page uxQueueMessagesWaiting uxQueueMessagesWaiting\r
+ * \ingroup QueueManagement\r
+ */\r
+unsigned portBASE_TYPE uxQueueMessagesWaiting( xQueueHandle xQueue );\r
+\r
+/**\r
+ * queue. h\r
+ * <pre>void vQueueDelete( xQueueHandle xQueue );</pre>\r
+ *\r
+ * Delete a queue - freeing all the memory allocated for storing of items\r
+ * placed on the queue.\r
+ * \r
+ * @param xQueue A handle to the queue to be deleted.\r
+ *\r
+ * \page vQueueDelete vQueueDelete\r
+ * \ingroup QueueManagement\r
+ */\r
+void vQueueDelete( xQueueHandle xQueue );\r
+\r
+/**\r
+ * queue. h\r
+ * <pre>\r
+ portBASE_TYPE xQueueSendFromISR( \r
+ xQueueHandle pxQueue, \r
+ const void *pvItemToQueue, \r
+ portBASE_TYPE xTaskPreviouslyWoken \r
+ );\r
+ </pre>\r
+ *\r
+ * Post an item on a queue. It is safe to use this function from within an\r
+ * interrupt service routine.\r
+ *\r
+ * Items are queued by copy not reference so it is preferable to only\r
+ * queue small items, especially when called from an ISR. In most cases\r
+ * it would be preferable to store a pointer to the item being queued.\r
+ *\r
+ * @param xQueue The handle to the queue on which the item is to be posted.\r
+ * \r
+ * @param pvItemToQueue A pointer to the item that is to be placed on the \r
+ * queue. The size of the items the queue will hold was defined when the\r
+ * queue was created, so this many bytes will be copied from pvItemToQueue\r
+ * into the queue storage area.\r
+ *\r
+ * @param cTaskPreviouslyWoken This is included so an ISR can post onto\r
+ * the same queue multiple times from a single interrupt. The first call\r
+ * should always pass in pdFALSE. Subsequent calls should pass in\r
+ * the value returned from the previous call. See the file serial .c in the\r
+ * PC port for a good example of this mechanism.\r
+ *\r
+ * @return pdTRUE if a task was woken by posting onto the queue. This is \r
+ * used by the ISR to determine if a context switch may be required following\r
+ * the ISR.\r
+ *\r
+ * Example usage for buffered IO (where the ISR can obtain more than one value\r
+ * per call):\r
+ <pre>\r
+ void vBufferISR( void )\r
+ {\r
+ portCHAR cIn;\r
+ portBASE_TYPE xTaskWokenByPost;\r
+\r
+ // We have not woken a task at the start of the ISR.\r
+ cTaskWokenByPost = pdFALSE;\r
+\r
+ // Loop until the buffer is empty.\r
+ do\r
+ {\r
+ // Obtain a byte from the buffer.\r
+ cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS ); \r
+\r
+ // Post the byte. The first time round the loop cTaskWokenByPost\r
+ // will be pdFALSE. If the queue send causes a task to wake we do\r
+ // not want the task to run until we have finished the ISR, so\r
+ // xQueueSendFromISR does not cause a context switch. Also we \r
+ // don't want subsequent posts to wake any other tasks, so we store\r
+ // the return value back into cTaskWokenByPost so xQueueSendFromISR\r
+ // knows not to wake any task the next iteration of the loop.\r
+ xTaskWokenByPost = xQueueSendFromISR( xRxQueue, &cIn, cTaskWokenByPost );\r
+\r
+ } while( portINPUT_BYTE( BUFFER_COUNT ) );\r
+\r
+ // Now the buffer is empty we can switch context if necessary.\r
+ if( cTaskWokenByPost )\r
+ {\r
+ taskYIELD ();\r
+ }\r
+ }\r
+ </pre>\r
+ *\r
+ * \defgroup xQueueSendFromISR xQueueSendFromISR\r
+ * \ingroup QueueManagement\r
+ */\r
+signed portBASE_TYPE xQueueSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xTaskPreviouslyWoken );\r
+\r
+/**\r
+ * queue. h\r
+ * <pre>\r
+ portBASE_TYPE xQueueReceiveFromISR( \r
+ xQueueHandle pxQueue, \r
+ void *pvBuffer, \r
+ portBASE_TYPE *pxTaskWoken \r
+ ); \r
+ * </pre>\r
+ *\r
+ * Receive an item from a queue. It is safe to use this function from within an\r
+ * interrupt service routine.\r
+ *\r
+ * @param pxQueue The handle to the queue from which the item is to be\r
+ * received.\r
+ *\r
+ * @param pvBuffer Pointer to the buffer into which the received item will\r
+ * be copied.\r
+ * \r
+ * @param pxTaskWoken A task may be blocked waiting for space to become\r
+ * available on the queue. If xQueueReceiveFromISR causes such a task to\r
+ * unblock *pxTaskWoken will get set to pdTRUE, otherwise *pxTaskWoken will\r
+ * remain unchanged.\r
+ *\r
+ * @return pdTRUE if an item was successfully received from the queue,\r
+ * otherwise pdFALSE.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ \r
+ xQueueHandle xQueue;\r
+ \r
+ // Function to create a queue and post some values.\r
+ void vAFunction( void *pvParameters )\r
+ {\r
+ portCHAR cValueToPost;\r
+ const portTickType xBlockTime = ( portTickType )0xff;\r
+\r
+ // Create a queue capable of containing 10 characters.\r
+ xQueue = xQueueCreate( 10, sizeof( portCHAR ) );\r
+ if( xQueue == 0 )\r
+ {\r
+ // Failed to create the queue.\r
+ }\r
+\r
+ // ...\r
+\r
+ // Post some characters that will be used within an ISR. If the queue\r
+ // is full then this task will block for xBlockTime ticks.\r
+ cValueToPost = 'a';\r
+ xQueueSend( xQueue, ( void * ) &cValueToPost, xBlockTime );\r
+ cValueToPost = 'b';\r
+ xQueueSend( xQueue, ( void * ) &cValueToPost, xBlockTime );\r
+\r
+ // ... keep posting characters ... this task may block when the queue\r
+ // becomes full.\r
+\r
+ cValueToPost = 'c';\r
+ xQueueSend( xQueue, ( void * ) &cValueToPost, xBlockTime );\r
+ }\r
+\r
+ // ISR that outputs all the characters received on the queue. \r
+ void vISR_Routine( void )\r
+ {\r
+ portBASE_TYPE xTaskWokenByReceive = pdFALSE;\r
+ portCHAR cRxedChar;\r
+\r
+ while( xQueueReceiveFromISR( xQueue, ( void * ) &cRxedChar, &xTaskWokenByReceive) )\r
+ {\r
+ // A character was received. Output the character now.\r
+ vOutputCharacter( cRxedChar );\r
+\r
+ // If removing the character from the queue woke the task that was \r
+ // posting onto the queue cTaskWokenByReceive will have been set to\r
+ // pdTRUE. No matter how many times this loop iterates only one\r
+ // task will be woken.\r
+ }\r
+\r
+ if( cTaskWokenByPost != ( portCHAR ) pdFALSE;\r
+ {\r
+ taskYIELD ();\r
+ }\r
+ }\r
+ </pre>\r
+ * \defgroup xQueueReceiveFromISR xQueueReceiveFromISR\r
+ * \ingroup QueueManagement\r
+ */\r
+signed portBASE_TYPE xQueueReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxTaskWoken );\r
+\r
+\r
+/* \r
+ * The functions defined above are for passing data to and from tasks. The \r
+ * functions below are the equivalents for passing data to and from \r
+ * co-rtoutines.\r
+ *\r
+ * These functions are called from the co-routine macro implementation and\r
+ * should not be called directly from application code. Instead use the macro\r
+ * wrappers defined within croutine.h.\r
+ */\r
+signed portBASE_TYPE xQueueCRSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xCoRoutinePreviouslyWoken );\r
+signed portBASE_TYPE xQueueCRReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxTaskWoken );\r
+signed portBASE_TYPE xQueueCRSend( xQueueHandle pxQueue, const void *pvItemToQueue, portTickType xTicksToWait );\r
+signed portBASE_TYPE xQueueCRReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait );\r
+\r
+#endif\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#include "queue.h"\r
+\r
+#ifndef SEMAPHORE_H\r
+#define SEMAPHORE_H\r
+\r
+typedef xQueueHandle xSemaphoreHandle;\r
+\r
+#define semBINARY_SEMAPHORE_QUEUE_LENGTH ( ( unsigned portCHAR ) 1 )\r
+#define semSEMAPHORE_QUEUE_ITEM_LENGTH ( ( unsigned portCHAR ) 0 )\r
+#define semGIVE_BLOCK_TIME ( ( portTickType ) 0 )\r
+\r
+\r
+/**\r
+ * semphr. h\r
+ * <pre>vSemaphoreCreateBinary( xSemaphoreHandle xSemaphore )</pre>\r
+ *\r
+ * <i>Macro</i> that implements a semaphore by using the existing queue mechanism.\r
+ * The queue length is 1 as this is a binary semaphore. The data size is 0\r
+ * as we don't want to actually store any data - we just want to know if the\r
+ * queue is empty or full.\r
+ *\r
+ * @param xSemaphore Handle to the created semaphore. Should be of type xSemaphoreHandle.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ xSemaphoreHandle xSemaphore;\r
+\r
+ void vATask( void * pvParameters )\r
+ {\r
+ // Semaphore cannot be used before a call to vSemaphoreCreateBinary ().\r
+ // This is a macro so pass the variable in directly.\r
+ vSemaphoreCreateBinary( xSemaphore );\r
+\r
+ if( xSemaphore != NULL )\r
+ {\r
+ // The semaphore was created successfully.\r
+ // The semaphore can now be used. \r
+ }\r
+ }\r
+ </pre>\r
+ * \defgroup vSemaphoreCreateBinary vSemaphoreCreateBinary\r
+ * \ingroup Semaphores\r
+ */\r
+#define vSemaphoreCreateBinary( xSemaphore ) { \\r
+ xSemaphore = xQueueCreate( ( unsigned portCHAR ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH ); \\r
+ if( xSemaphore != NULL ) \\r
+ { \\r
+ xSemaphoreGive( xSemaphore ); \\r
+ } \\r
+ }\r
+\r
+/**\r
+ * semphr. h\r
+ * xSemaphoreTake( \r
+ * xSemaphoreHandle xSemaphore, \r
+ * portTickType xBlockTime \r
+ * )</pre>\r
+ *\r
+ * <i>Macro</i> to obtain a semaphore. The semaphore must of been created using \r
+ * vSemaphoreCreateBinary ().\r
+ *\r
+ * @param xSemaphore A handle to the semaphore being obtained. This is the\r
+ * handle returned by vSemaphoreCreateBinary ();\r
+ *\r
+ * @param xBlockTime The time in ticks to wait for the semaphore to become\r
+ * available. The macro portTICK_RATE_MS can be used to convert this to a\r
+ * real time. A block time of zero can be used to poll the semaphore.\r
+ *\r
+ * @return pdTRUE if the semaphore was obtained. pdFALSE if xBlockTime\r
+ * expired without the semaphore becoming available.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ xSemaphoreHandle xSemaphore = NULL;\r
+\r
+ // A task that creates a semaphore.\r
+ void vATask( void * pvParameters )\r
+ {\r
+ // Create the semaphore to guard a shared resource.\r
+ vSemaphoreCreateBinary( xSemaphore );\r
+ }\r
+\r
+ // A task that uses the semaphore.\r
+ void vAnotherTask( void * pvParameters )\r
+ {\r
+ // ... Do other things.\r
+\r
+ if( xSemaphore != NULL )\r
+ {\r
+ // See if we can obtain the semaphore. If the semaphore is not available\r
+ // wait 10 ticks to see if it becomes free. \r
+ if( xSemaphoreTake( xSemaphore, ( portTickType ) 10 ) == pdTRUE )\r
+ {\r
+ // We were able to obtain the semaphore and can now access the\r
+ // shared resource.\r
+\r
+ // ...\r
+\r
+ // We have finished accessing the shared resource. Release the \r
+ // semaphore.\r
+ xSemaphoreGive( xSemaphore );\r
+ }\r
+ else\r
+ {\r
+ // We could not obtain the semaphore and can therefore not access\r
+ // the shared resource safely.\r
+ }\r
+ }\r
+ }\r
+ </pre>\r
+ * \defgroup xSemaphoreTake xSemaphoreTake\r
+ * \ingroup Semaphores\r
+ */\r
+#define xSemaphoreTake( xSemaphore, xBlockTime ) xQueueReceive( ( xQueueHandle ) xSemaphore, NULL, xBlockTime )\r
+\r
+/**\r
+ * semphr. h\r
+ * <pre>xSemaphoreGive( xSemaphoreHandle xSemaphore )</pre>\r
+ *\r
+ * <i>Macro</i> to release a semaphore. The semaphore must of been created using \r
+ * vSemaphoreCreateBinary (), and obtained using sSemaphoreTake ().\r
+ *\r
+ * This must not be used from an ISR. See xSemaphoreGiveFromISR () for\r
+ * an alternative which can be used from an ISR.\r
+ *\r
+ * @param xSemaphore A handle to the semaphore being released. This is the\r
+ * handle returned by vSemaphoreCreateBinary ();\r
+ *\r
+ * @return pdTRUE if the semaphore was released. pdFALSE if an error occurred.\r
+ * Semaphores are implemented using queues. An error can occur if there is\r
+ * no space on the queue to post a message - indicating that the \r
+ * semaphore was not first obtained correctly.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ xSemaphoreHandle xSemaphore = NULL;\r
+\r
+ void vATask( void * pvParameters )\r
+ {\r
+ // Create the semaphore to guard a shared resource.\r
+ vSemaphoreCreateBinary( xSemaphore );\r
+\r
+ if( xSemaphore != NULL )\r
+ {\r
+ if( xSemaphoreGive( xSemaphore ) != pdTRUE )\r
+ {\r
+ // We would expect this call to fail because we cannot give\r
+ // a semaphore without first "taking" it!\r
+ }\r
+\r
+ // Obtain the semaphore - don't block if the semaphore is not\r
+ // immediately available.\r
+ if( xSemaphoreTake( xSemaphore, ( portTickType ) 0 ) )\r
+ {\r
+ // We now have the semaphore and can access the shared resource.\r
+\r
+ // ...\r
+\r
+ // We have finished accessing the shared resource so can free the\r
+ // semaphore.\r
+ if( xSemaphoreGive( xSemaphore ) != pdTRUE )\r
+ {\r
+ // We would not expect this call to fail because we must have\r
+ // obtained the semaphore to get here.\r
+ }\r
+ }\r
+ }\r
+ }\r
+ </pre>\r
+ * \defgroup xSemaphoreGive xSemaphoreGive\r
+ * \ingroup Semaphores\r
+ */\r
+#define xSemaphoreGive( xSemaphore ) xQueueSend( ( xQueueHandle ) xSemaphore, NULL, semGIVE_BLOCK_TIME )\r
+\r
+/**\r
+ * semphr. h\r
+ * <pre>\r
+ xSemaphoreGiveFromISR( \r
+ xSemaphoreHandle xSemaphore, \r
+ portSHORT sTaskPreviouslyWoken \r
+ )</pre>\r
+ *\r
+ * <i>Macro</i> to release a semaphore. The semaphore must of been created using \r
+ * vSemaphoreCreateBinary (), and obtained using xSemaphoreTake ().\r
+ *\r
+ * This macro can be used from an ISR.\r
+ *\r
+ * @param xSemaphore A handle to the semaphore being released. This is the\r
+ * handle returned by vSemaphoreCreateBinary ();\r
+ *\r
+ * @param sTaskPreviouslyWoken This is included so an ISR can make multiple calls\r
+ * to xSemaphoreGiveFromISR () from a single interrupt. The first call\r
+ * should always pass in pdFALSE. Subsequent calls should pass in\r
+ * the value returned from the previous call. See the file serial .c in the\r
+ * PC port for a good example of using xSemaphoreGiveFromISR ().\r
+ *\r
+ * @return pdTRUE if a task was woken by releasing the semaphore. This is \r
+ * used by the ISR to determine if a context switch may be required following\r
+ * the ISR.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ #define LONG_TIME 0xffff\r
+ #define TICKS_TO_WAIT 10\r
+ xSemaphoreHandle xSemaphore = NULL;\r
+\r
+ // Repetitive task.\r
+ void vATask( void * pvParameters )\r
+ {\r
+ for( ;; )\r
+ {\r
+ // We want this task to run every 10 ticks or a timer. The semaphore \r
+ // was created before this task was started\r
+\r
+ // Block waiting for the semaphore to become available.\r
+ if( xSemaphoreTake( xSemaphore, LONG_TIME ) == pdTRUE )\r
+ {\r
+ // It is time to execute.\r
+\r
+ // ...\r
+\r
+ // We have finished our task. Return to the top of the loop where\r
+ // we will block on the semaphore until it is time to execute \r
+ // again.\r
+ }\r
+ }\r
+ }\r
+\r
+ // Timer ISR\r
+ void vTimerISR( void * pvParameters )\r
+ {\r
+ static unsigned portCHAR ucLocalTickCount = 0;\r
+\r
+ // A timer tick has occurred.\r
+\r
+ // ... Do other time functions.\r
+\r
+ // Is it time for vATask () to run?\r
+ ucLocalTickCount++;\r
+ if( ucLocalTickCount >= TICKS_TO_WAIT )\r
+ {\r
+ // Unblock the task by releasing the semaphore.\r
+ xSemaphoreGive( xSemaphore );\r
+\r
+ // Reset the count so we release the semaphore again in 10 ticks time.\r
+ ucLocalTickCount = 0;\r
+ }\r
+ }\r
+ </pre>\r
+ * \defgroup xSemaphoreGiveFromISR xSemaphoreGiveFromISR\r
+ * \ingroup Semaphores\r
+ */\r
+#define xSemaphoreGiveFromISR( xSemaphore, xTaskPreviouslyWoken ) xQueueSendFromISR( ( xQueueHandle ) xSemaphore, NULL, xTaskPreviouslyWoken )\r
+\r
+\r
+#endif\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef TASK_H\r
+#define TASK_H\r
+\r
+#include "portable.h"\r
+#include "list.h"\r
+\r
+/*-----------------------------------------------------------\r
+ * MACROS AND DEFINITIONS\r
+ *----------------------------------------------------------*/\r
+\r
+#define tskKERNEL_VERSION_NUMBER "V3.2.4"\r
+\r
+/**\r
+ * task. h\r
+ *\r
+ * Type by which tasks are referenced. For example, a call to xTaskCreate\r
+ * returns (via a pointer parameter) an xTaskHandle variable that can then\r
+ * be used as a parameter to vTaskDelete to delete the task.\r
+ *\r
+ * \page xTaskHandle xTaskHandle\r
+ * \ingroup Tasks\r
+ */\r
+typedef void * xTaskHandle;\r
+\r
+/*\r
+ * Defines the priority used by the idle task. This must not be modified.\r
+ *\r
+ * \ingroup TaskUtils\r
+ */\r
+#define tskIDLE_PRIORITY ( ( unsigned portBASE_TYPE ) 0 )\r
+\r
+/**\r
+ * task. h\r
+ *\r
+ * Macro for forcing a context switch.\r
+ *\r
+ * \page taskYIELD taskYIELD\r
+ * \ingroup SchedulerControl\r
+ */\r
+#define taskYIELD() portYIELD()\r
+\r
+/**\r
+ * task. h\r
+ *\r
+ * Macro to mark the start of a critical code region. Preemptive context\r
+ * switches cannot occur when in a critical region.\r
+ *\r
+ * NOTE: This may alter the stack (depending on the portable implementation)\r
+ * so must be used with care!\r
+ *\r
+ * \page taskENTER_CRITICAL taskENTER_CRITICAL\r
+ * \ingroup SchedulerControl\r
+ */\r
+#define taskENTER_CRITICAL() portENTER_CRITICAL()\r
+\r
+/**\r
+ * task. h\r
+ *\r
+ * Macro to mark the end of a critical code region. Preemptive context\r
+ * switches cannot occur when in a critical region.\r
+ *\r
+ * NOTE: This may alter the stack (depending on the portable implementation)\r
+ * so must be used with care!\r
+ *\r
+ * \page taskEXIT_CRITICAL taskEXIT_CRITICAL\r
+ * \ingroup SchedulerControl\r
+ */\r
+#define taskEXIT_CRITICAL() portEXIT_CRITICAL()\r
+\r
+/**\r
+ * task. h\r
+ *\r
+ * Macro to disable all maskable interrupts.\r
+ *\r
+ * \page taskDISABLE_INTERRUPTS taskDISABLE_INTERRUPTS\r
+ * \ingroup SchedulerControl\r
+ */\r
+#define taskDISABLE_INTERRUPTS() portDISABLE_INTERRUPTS()\r
+\r
+/**\r
+ * task. h\r
+ *\r
+ * Macro to enable microcontroller interrupts.\r
+ *\r
+ * \page taskENABLE_INTERRUPTS taskENABLE_INTERRUPTS\r
+ * \ingroup SchedulerControl\r
+ */\r
+#define taskENABLE_INTERRUPTS() portENABLE_INTERRUPTS()\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ * TASK CREATION API\r
+ *----------------------------------------------------------*/\r
+\r
+/**\r
+ * task. h\r
+ *<pre>\r
+ portBASE_TYPE xTaskCreate(\r
+ pdTASK_CODE pvTaskCode,\r
+ const portCHAR * const pcName,\r
+ unsigned portSHORT usStackDepth,\r
+ void *pvParameters,\r
+ unsigned portBASE_TYPE uxPriority,\r
+ xTaskHandle *pvCreatedTask\r
+ );</pre>\r
+ *\r
+ * Create a new task and add it to the list of tasks that are ready to run.\r
+ *\r
+ * @param pvTaskCode Pointer to the task entry function. Tasks\r
+ * must be implemented to never return (i.e. continuous loop).\r
+ *\r
+ * @param pcName A descriptive name for the task. This is mainly used to\r
+ * facilitate debugging. Max length defined by tskMAX_TASK_NAME_LEN - default\r
+ * is 16.\r
+ *\r
+ * @param usStackDepth The size of the task stack specified as the number of\r
+ * variables the stack can hold - not the number of bytes. For example, if\r
+ * the stack is 16 bits wide and usStackDepth is defined as 100, 200 bytes\r
+ * will be allocated for stack storage.\r
+ *\r
+ * @param pvParameters Pointer that will be used as the parameter for the task\r
+ * being created.\r
+ *\r
+ * @param uxPriority The priority at which the task should run.\r
+ *\r
+ * @param pvCreatedTask Used to pass back a handle by which the created task\r
+ * can be referenced.\r
+ *\r
+ * @return pdPASS if the task was successfully created and added to a ready\r
+ * list, otherwise an error code defined in the file errors. h\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ // Task to be created.\r
+ void vTaskCode( void * pvParameters )\r
+ {\r
+ for( ;; )\r
+ {\r
+ // Task code goes here.\r
+ }\r
+ }\r
+\r
+ // Function that creates a task.\r
+ void vOtherFunction( void )\r
+ {\r
+ unsigned char ucParameterToPass;\r
+ xTaskHandle xHandle;\r
+ \r
+ // Create the task, storing the handle.\r
+ xTaskCreate( vTaskCode, "NAME", STACK_SIZE, &ucParameterToPass, tskIDLE_PRIORITY, &xHandle );\r
+ \r
+ // Use the handle to delete the task.\r
+ vTaskDelete( xHandle );\r
+ }\r
+ </pre>\r
+ * \defgroup xTaskCreate xTaskCreate\r
+ * \ingroup Tasks\r
+ */\r
+signed portBASE_TYPE xTaskCreate( pdTASK_CODE pvTaskCode, const signed portCHAR * const pcName, unsigned portSHORT usStackDepth, void *pvParameters, unsigned portBASE_TYPE uxPriority, xTaskHandle *pvCreatedTask );\r
+\r
+/**\r
+ * task. h\r
+ * <pre>void vTaskDelete( xTaskHandle pxTask );</pre>\r
+ *\r
+ * INCLUDE_vTaskDelete must be defined as 1 for this function to be available.\r
+ * See the configuration section for more information.\r
+ *\r
+ * Remove a task from the RTOS real time kernels management. The task being\r
+ * deleted will be removed from all ready, blocked, suspended and event lists.\r
+ *\r
+ * NOTE: The idle task is responsible for freeing the kernel allocated\r
+ * memory from tasks that have been deleted. It is therefore important that\r
+ * the idle task is not starved of microcontroller processing time if your\r
+ * application makes any calls to vTaskDelete (). Memory allocated by the\r
+ * task code is not automatically freed, and should be freed before the task\r
+ * is deleted.\r
+ *\r
+ * See the demo application file death.c for sample code that utilises\r
+ * vTaskDelete ().\r
+ *\r
+ * @param pxTask The handle of the task to be deleted. Passing NULL will\r
+ * cause the calling task to be deleted.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ void vOtherFunction( void )\r
+ {\r
+ xTaskHandle xHandle;\r
+ \r
+ // Create the task, storing the handle.\r
+ xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );\r
+ \r
+ // Use the handle to delete the task.\r
+ vTaskDelete( xHandle );\r
+ }\r
+ </pre>\r
+ * \defgroup vTaskDelete vTaskDelete\r
+ * \ingroup Tasks\r
+ */\r
+void vTaskDelete( xTaskHandle pxTask );\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ * TASK CONTROL API\r
+ *----------------------------------------------------------*/\r
+\r
+/**\r
+ * task. h\r
+ * <pre>void vTaskDelay( portTickType xTicksToDelay );</pre>\r
+ *\r
+ * Delay a task for a given number of ticks. The actual time that the\r
+ * task remains blocked depends on the tick rate. The constant\r
+ * portTICK_RATE_MS can be used to calculate real time from the tick\r
+ * rate - with the resolution of one tick period.\r
+ *\r
+ * INCLUDE_vTaskDelay must be defined as 1 for this function to be available.\r
+ * See the configuration section for more information.\r
+ *\r
+ * @param xTicksToDelay The amount of time, in tick periods, that\r
+ * the calling task should block.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ // Wait 10 ticks before performing an action.\r
+ // NOTE:\r
+ // This is for demonstration only and would be better achieved\r
+ // using vTaskDelayUntil ().\r
+ void vTaskFunction( void * pvParameters )\r
+ {\r
+ portTickType xDelay, xNextTime;\r
+\r
+ // Calc the time at which we want to perform the action\r
+ // next.\r
+ xNextTime = xTaskGetTickCount () + ( portTickType ) 10;\r
+\r
+ for( ;; )\r
+ {\r
+ xDelay = xNextTime - xTaskGetTickCount ();\r
+ xNextTime += ( portTickType ) 10;\r
+\r
+ // Guard against overflow\r
+ if( xDelay <= ( portTickType ) 10 )\r
+ {\r
+ vTaskDelay( xDelay );\r
+ }\r
+\r
+ // Perform action here.\r
+ }\r
+ }\r
+ </pre>\r
+ * \defgroup vTaskDelay vTaskDelay\r
+ * \ingroup TaskCtrl\r
+ */\r
+void vTaskDelay( portTickType xTicksToDelay );\r
+\r
+/**\r
+ * task. h\r
+ * <pre>void vTaskDelayUntil( portTickType *pxPreviousWakeTime, portTickType xTimeIncrement );</pre>\r
+ *\r
+ * INCLUDE_vTaskDelayUntil must be defined as 1 for this function to be available.\r
+ * See the configuration section for more information.\r
+ *\r
+ * Delay a task until a specified time. This function can be used by cyclical\r
+ * tasks to ensure a constant execution frequency.\r
+ *\r
+ * This function differs from vTaskDelay () in one important aspect: vTaskDelay () will\r
+ * cause a task to block for the specified number of ticks from the time vTaskDelay () is\r
+ * called. It is therefore difficult to use vTaskDelay () by itself to generate a fixed\r
+ * execution frequency as the time between a task starting to execute and that task\r
+ * calling vTaskDelay () may not be fixed [the task may take a different path though the\r
+ * code between calls, or may get interrupted or preempted a different number of times\r
+ * each time it executes].\r
+ *\r
+ * Whereas vTaskDelay () specifies a wake time relative to the time at which the function\r
+ * is called, vTaskDelayUntil () specifies the absolute (exact) time at which it wishes to\r
+ * unblock.\r
+ *\r
+ * The constant portTICK_RATE_MS can be used to calculate real time from the tick\r
+ * rate - with the resolution of one tick period.\r
+ *\r
+ * @param pxPreviousWakeTime Pointer to a variable that holds the time at which the\r
+ * task was last unblocked. The variable must be initialised with the current time\r
+ * prior to its first use (see the example below). Following this the variable is\r
+ * automatically updated within vTaskDelayUntil ().\r
+ *\r
+ * @param xTimeIncrement The cycle time period. The task will be unblocked at\r
+ * time *pxPreviousWakeTime + xTimeIncrement. Calling vTaskDelayUntil with the\r
+ * same xTimeIncrement parameter value will cause the task to execute with\r
+ * a fixed interface period.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ // Perform an action every 10 ticks.\r
+ void vTaskFunction( void * pvParameters )\r
+ {\r
+ portTickType xLastWakeTime;\r
+ const portTickType xFrequency = 10;\r
+\r
+ // Initialise the xLastWakeTime variable with the current time.\r
+ xLastWakeTime = xTaskGetTickCount ();\r
+ for( ;; )\r
+ {\r
+ // Wait for the next cycle.\r
+ vTaskDelayUntil( &xLastWakeTime, xFrequency );\r
+\r
+ // Perform action here.\r
+ }\r
+ }\r
+ </pre>\r
+ * \defgroup vTaskDelayUntil vTaskDelayUntil\r
+ * \ingroup TaskCtrl\r
+ */\r
+void vTaskDelayUntil( portTickType *pxPreviousWakeTime, portTickType xTimeIncrement );\r
+\r
+/**\r
+ * task. h\r
+ * <pre>unsigned portBASE_TYPE uxTaskPriorityGet( xTaskHandle pxTask );</pre>\r
+ *\r
+ * INCLUDE_xTaskPriorityGet must be defined as 1 for this function to be available.\r
+ * See the configuration section for more information.\r
+ *\r
+ * Obtain the priority of any task.\r
+ *\r
+ * @param pxTask Handle of the task to be queried. Passing a NULL\r
+ * handle results in the priority of the calling task being returned.\r
+ *\r
+ * @return The priority of pxTask.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ void vAFunction( void )\r
+ {\r
+ xTaskHandle xHandle;\r
+ \r
+ // Create a task, storing the handle.\r
+ xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );\r
+ \r
+ // ...\r
+\r
+ // Use the handle to obtain the priority of the created task.\r
+ // It was created with tskIDLE_PRIORITY, but may have changed\r
+ // it itself.\r
+ if( uxTaskPriorityGet( xHandle ) != tskIDLE_PRIORITY )\r
+ {\r
+ // The task has changed it's priority.\r
+ }\r
+\r
+ // ...\r
+\r
+ // Is our priority higher than the created task?\r
+ if( uxTaskPriorityGet( xHandle ) < uxTaskPriorityGet( NULL ) )\r
+ {\r
+ // Our priority (obtained using NULL handle) is higher.\r
+ }\r
+ }\r
+ </pre>\r
+ * \defgroup uxTaskPriorityGet uxTaskPriorityGet\r
+ * \ingroup TaskCtrl\r
+ */\r
+unsigned portBASE_TYPE uxTaskPriorityGet( xTaskHandle pxTask );\r
+\r
+/**\r
+ * task. h\r
+ * <pre>void vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority );</pre>\r
+ *\r
+ * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available.\r
+ * See the configuration section for more information.\r
+ *\r
+ * Set the priority of any task.\r
+ *\r
+ * A context switch will occur before the function returns if the priority\r
+ * being set is higher than the currently executing task.\r
+ *\r
+ * @param pxTask Handle to the task for which the priority is being set.\r
+ * Passing a NULL handle results in the priority of the calling task being set.\r
+ *\r
+ * @param uxNewPriority The priority to which the task will be set.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ void vAFunction( void )\r
+ {\r
+ xTaskHandle xHandle;\r
+ \r
+ // Create a task, storing the handle.\r
+ xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );\r
+\r
+ // ...\r
+\r
+ // Use the handle to raise the priority of the created task.\r
+ vTaskPrioritySet( xHandle, tskIDLE_PRIORITY + 1 );\r
+\r
+ // ...\r
+\r
+ // Use a NULL handle to raise our priority to the same value.\r
+ vTaskPrioritySet( NULL, tskIDLE_PRIORITY + 1 );\r
+ }\r
+ </pre>\r
+ * \defgroup vTaskPrioritySet vTaskPrioritySet\r
+ * \ingroup TaskCtrl\r
+ */\r
+void vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority );\r
+\r
+/**\r
+ * task. h\r
+ * <pre>void vTaskSuspend( xTaskHandle pxTaskToSuspend );</pre>\r
+ *\r
+ * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.\r
+ * See the configuration section for more information.\r
+ *\r
+ * Suspend any task. When suspended a task will never get any microcontroller\r
+ * processing time, no matter what its priority.\r
+ *\r
+ * Calls to vTaskSuspend are not accumulative -\r
+ * i.e. calling vTaskSuspend () twice on the same task still only requires one\r
+ * call to vTaskResume () to ready the suspended task.\r
+ *\r
+ * @param pxTaskToSuspend Handle to the task being suspended. Passing a NULL\r
+ * handle will cause the calling task to be suspended.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ void vAFunction( void )\r
+ {\r
+ xTaskHandle xHandle;\r
+ \r
+ // Create a task, storing the handle.\r
+ xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );\r
+ \r
+ // ...\r
+\r
+ // Use the handle to suspend the created task.\r
+ vTaskSuspend( xHandle );\r
+\r
+ // ...\r
+ \r
+ // The created task will not run during this period, unless\r
+ // another task calls vTaskResume( xHandle ).\r
+ \r
+ //...\r
+ \r
+\r
+ // Suspend ourselves.\r
+ vTaskSuspend( NULL );\r
+\r
+ // We cannot get here unless another task calls vTaskResume\r
+ // with our handle as the parameter.\r
+ }\r
+ </pre>\r
+ * \defgroup vTaskSuspend vTaskSuspend\r
+ * \ingroup TaskCtrl\r
+ */\r
+void vTaskSuspend( xTaskHandle pxTaskToSuspend );\r
+\r
+/**\r
+ * task. h\r
+ * <pre>void vTaskResume( xTaskHandle pxTaskToResume );</pre>\r
+ *\r
+ * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.\r
+ * See the configuration section for more information.\r
+ *\r
+ * Resumes a suspended task.\r
+ *\r
+ * A task that has been suspended by one of more calls to vTaskSuspend ()\r
+ * will be made available for running again by a single call to\r
+ * vTaskResume ().\r
+ *\r
+ * @param pxTaskToResume Handle to the task being readied.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ void vAFunction( void )\r
+ {\r
+ xTaskHandle xHandle;\r
+ \r
+ // Create a task, storing the handle.\r
+ xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );\r
+ \r
+ // ...\r
+\r
+ // Use the handle to suspend the created task.\r
+ vTaskSuspend( xHandle );\r
+\r
+ // ...\r
+ \r
+ // The created task will not run during this period, unless\r
+ // another task calls vTaskResume( xHandle ).\r
+ \r
+ //...\r
+ \r
+\r
+ // Resume the suspended task ourselves.\r
+ vTaskResume( xHandle );\r
+\r
+ // The created task will once again get microcontroller processing\r
+ // time in accordance with it priority within the system.\r
+ }\r
+ </pre>\r
+ * \defgroup vTaskResume vTaskResume\r
+ * \ingroup TaskCtrl\r
+ */\r
+void vTaskResume( xTaskHandle pxTaskToResume );\r
+\r
+/*-----------------------------------------------------------\r
+ * SCHEDULER CONTROL\r
+ *----------------------------------------------------------*/\r
+\r
+/**\r
+ * task. h\r
+ * <pre>void vTaskStartScheduler( void );</pre>\r
+ *\r
+ * Starts the real time kernel tick processing. After calling the kernel\r
+ * has control over which tasks are executed and when. This function\r
+ * does not return until an executing task calls vTaskEndScheduler ().\r
+ *\r
+ * At least one task should be created via a call to xTaskCreate ()\r
+ * before calling vTaskStartScheduler (). The idle task is created\r
+ * automatically when the first application task is created.\r
+ *\r
+ * See the demo application file main.c for an example of creating\r
+ * tasks and starting the kernel.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ void vAFunction( void )\r
+ {\r
+ // Create at least one task before starting the kernel.\r
+ xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );\r
+\r
+ // Start the real time kernel with preemption.\r
+ vTaskStartScheduler ();\r
+\r
+ // Will not get here unless a task calls vTaskEndScheduler ()\r
+ }\r
+ </pre>\r
+ *\r
+ * \defgroup vTaskStartScheduler vTaskStartScheduler\r
+ * \ingroup SchedulerControl\r
+ */\r
+void vTaskStartScheduler( void );\r
+\r
+/**\r
+ * task. h\r
+ * <pre>void vTaskEndScheduler( void );</pre>\r
+ *\r
+ * Stops the real time kernel tick. All created tasks will be automatically\r
+ * deleted and multitasking (either preemptive or cooperative) will\r
+ * stop. Execution then resumes from the point where vTaskStartScheduler ()\r
+ * was called, as if vTaskStartScheduler () had just returned.\r
+ *\r
+ * See the demo application file main. c in the demo/PC directory for an\r
+ * example that uses vTaskEndScheduler ().\r
+ *\r
+ * vTaskEndScheduler () requires an exit function to be defined within the\r
+ * portable layer (see vPortEndScheduler () in port. c for the PC port). This\r
+ * performs hardware specific operations such as stopping the kernel tick.\r
+ *\r
+ * vTaskEndScheduler () will cause all of the resources allocated by the\r
+ * kernel to be freed - but will not free resources allocated by application\r
+ * tasks.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ void vTaskCode( void * pvParameters )\r
+ {\r
+ for( ;; )\r
+ {\r
+ // Task code goes here.\r
+\r
+ // At some point we want to end the real time kernel processing\r
+ // so call ...\r
+ vTaskEndScheduler ();\r
+ }\r
+ }\r
+\r
+ void vAFunction( void )\r
+ {\r
+ // Create at least one task before starting the kernel.\r
+ xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );\r
+\r
+ // Start the real time kernel with preemption.\r
+ vTaskStartScheduler ();\r
+\r
+ // Will only get here when the vTaskCode () task has called\r
+ // vTaskEndScheduler (). When we get here we are back to single task\r
+ // execution.\r
+ }\r
+ </pre>\r
+ *\r
+ * \defgroup vTaskEndScheduler vTaskEndScheduler\r
+ * \ingroup SchedulerControl\r
+ */\r
+void vTaskEndScheduler( void );\r
+\r
+/**\r
+ * task. h\r
+ * <pre>void vTaskSuspendAll( void );</pre>\r
+ *\r
+ * Suspends all real time kernel activity while keeping interrupts (including the\r
+ * kernel tick) enabled.\r
+ *\r
+ * After calling vTaskSuspendAll () the calling task will continue to execute\r
+ * without risk of being swapped out until a call to xTaskResumeAll () has been\r
+ * made.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ void vTask1( void * pvParameters )\r
+ {\r
+ for( ;; )\r
+ {\r
+ // Task code goes here.\r
+\r
+ // ...\r
+\r
+ // At some point the task wants to perform a long operation during\r
+ // which it does not want to get swapped out. It cannot use\r
+ // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the\r
+ // operation may cause interrupts to be missed - including the\r
+ // ticks.\r
+\r
+ // Prevent the real time kernel swapping out the task.\r
+ vTaskSuspendAll ();\r
+\r
+ // Perform the operation here. There is no need to use critical\r
+ // sections as we have all the microcontroller processing time.\r
+ // During this time interrupts will still operate and the kernel\r
+ // tick count will be maintained.\r
+\r
+ // ...\r
+\r
+ // The operation is complete. Restart the kernel.\r
+ xTaskResumeAll ();\r
+ }\r
+ }\r
+ </pre>\r
+ * \defgroup vTaskSuspendAll vTaskSuspendAll\r
+ * \ingroup SchedulerControl\r
+ */\r
+void vTaskSuspendAll( void );\r
+\r
+/**\r
+ * task. h\r
+ * <pre>portCHAR xTaskResumeAll( void );</pre>\r
+ *\r
+ * Resumes real time kernel activity following a call to vTaskSuspendAll ().\r
+ * After a call to vTaskSuspendAll () the kernel will take control of which\r
+ * task is executing at any time.\r
+ *\r
+ * @return If resuming the scheduler caused a context switch then pdTRUE is\r
+ * returned, otherwise pdFALSE is returned.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ void vTask1( void * pvParameters )\r
+ {\r
+ for( ;; )\r
+ {\r
+ // Task code goes here.\r
+\r
+ // ...\r
+\r
+ // At some point the task wants to perform a long operation during\r
+ // which it does not want to get swapped out. It cannot use\r
+ // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the\r
+ // operation may cause interrupts to be missed - including the\r
+ // ticks.\r
+\r
+ // Prevent the real time kernel swapping out the task.\r
+ vTaskSuspendAll ();\r
+\r
+ // Perform the operation here. There is no need to use critical\r
+ // sections as we have all the microcontroller processing time.\r
+ // During this time interrupts will still operate and the real\r
+ // time kernel tick count will be maintained.\r
+\r
+ // ...\r
+\r
+ // The operation is complete. Restart the kernel. We want to force\r
+ // a context switch - but there is no point if resuming the scheduler\r
+ // caused a context switch already.\r
+ if( !xTaskResumeAll () )\r
+ {\r
+ taskYIELD ();\r
+ }\r
+ }\r
+ }\r
+ </pre>\r
+ * \defgroup xTaskResumeAll xTaskResumeAll\r
+ * \ingroup SchedulerControl\r
+ */\r
+signed portBASE_TYPE xTaskResumeAll( void );\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ * TASK UTILITIES\r
+ *----------------------------------------------------------*/\r
+\r
+/**\r
+ * task. h\r
+ * <PRE>volatile portTickType xTaskGetTickCount( void );</PRE>\r
+ *\r
+ * @return The count of ticks since vTaskStartScheduler was called.\r
+ *\r
+ * \page xTaskGetTickCount xTaskGetTickCount\r
+ * \ingroup TaskUtils\r
+ */\r
+portTickType xTaskGetTickCount( void );\r
+\r
+/**\r
+ * task. h\r
+ * <PRE>unsigned portSHORT uxTaskGetNumberOfTasks( void );</PRE>\r
+ *\r
+ * @return The number of tasks that the real time kernel is currently managing.\r
+ * This includes all ready, blocked and suspended tasks. A task that\r
+ * has been deleted but not yet freed by the idle task will also be\r
+ * included in the count.\r
+ *\r
+ * \page uxTaskGetNumberOfTasks uxTaskGetNumberOfTasks\r
+ * \ingroup TaskUtils\r
+ */\r
+unsigned portBASE_TYPE uxTaskGetNumberOfTasks( void );\r
+\r
+/**\r
+ * task. h\r
+ * <PRE>void vTaskList( portCHAR *pcWriteBuffer );</PRE>\r
+ *\r
+ * configUSE_TRACE_FACILITY, INCLUDE_vTaskDelete and INCLUDE_vTaskSuspend\r
+ * must all be defined as 1 for this function to be available.\r
+ * See the configuration section for more information.\r
+ *\r
+ * NOTE: This function will disable interrupts for its duration. It is\r
+ * not intended for normal application runtime use but as a debug aid.\r
+ *\r
+ * Lists all the current tasks, along with their current state and stack\r
+ * usage high water mark.\r
+ *\r
+ * Tasks are reported as blocked ('B'), ready ('R'), deleted ('D') or\r
+ * suspended ('S').\r
+ *\r
+ * @param pcWriteBuffer A buffer into which the above mentioned details\r
+ * will be written, in ascii form. This buffer is assumed to be large\r
+ * enough to contain the generated report. Approximately 40 bytes per\r
+ * task should be sufficient.\r
+ *\r
+ * \page vTaskList vTaskList\r
+ * \ingroup TaskUtils\r
+ */\r
+void vTaskList( signed portCHAR *pcWriteBuffer );\r
+\r
+/**\r
+ * task. h\r
+ * <PRE>void vTaskStartTrace( portCHAR * pcBuffer, unsigned portBASE_TYPE uxBufferSize );</PRE>\r
+ *\r
+ * Starts a real time kernel activity trace. The trace logs the identity of\r
+ * which task is running when.\r
+ *\r
+ * The trace file is stored in binary format. A separate DOS utility called\r
+ * convtrce.exe is used to convert this into a tab delimited text file which\r
+ * can be viewed and plotted in a spread sheet.\r
+ *\r
+ * @param pcBuffer The buffer into which the trace will be written.\r
+ *\r
+ * @param ulBufferSize The size of pcBuffer in bytes. The trace will continue\r
+ * until either the buffer in full, or ulTaskEndTrace () is called.\r
+ *\r
+ * \page vTaskStartTrace vTaskStartTrace\r
+ * \ingroup TaskUtils\r
+ */\r
+void vTaskStartTrace( signed portCHAR * pcBuffer, unsigned portLONG ulBufferSize );\r
+\r
+/**\r
+ * task. h\r
+ * <PRE>unsigned portLONG ulTaskEndTrace( void );</PRE>\r
+ *\r
+ * Stops a kernel activity trace. See vTaskStartTrace ().\r
+ *\r
+ * @return The number of bytes that have been written into the trace buffer.\r
+ *\r
+ * \page usTaskEndTrace usTaskEndTrace\r
+ * \ingroup TaskUtils\r
+ */\r
+unsigned portLONG ulTaskEndTrace( void );\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ * SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES\r
+ *----------------------------------------------------------*/\r
+\r
+/*\r
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS ONLY\r
+ * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS\r
+ * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.\r
+ *\r
+ * Called from the real time kernel tick (either preemptive or cooperative),\r
+ * this increments the tick count and checks if any tasks that are blocked\r
+ * for a finite period required removing from a blocked list and placing on\r
+ * a ready list.\r
+ */\r
+inline void vTaskIncrementTick( void );\r
+\r
+/*\r
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN\r
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.\r
+ *\r
+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.\r
+ *\r
+ * Removes the calling task from the ready list and places it both\r
+ * on the list of tasks waiting for a particular event, and the\r
+ * list of delayed tasks. The task will be removed from both lists\r
+ * and replaced on the ready list should either the event occur (and\r
+ * there be no higher priority tasks waiting on the same event) or\r
+ * the delay period expires.\r
+ *\r
+ * @param pxEventList The list containing tasks that are blocked waiting\r
+ * for the event to occur.\r
+ *\r
+ * @param xTicksToWait The maximum amount of time that the task should wait\r
+ * for the event to occur. This is specified in kernel ticks,the constant\r
+ * portTICK_RATE_MS can be used to convert kernel ticks into a real time\r
+ * period.\r
+ */\r
+void vTaskPlaceOnEventList( xList *pxEventList, portTickType xTicksToWait );\r
+\r
+/*\r
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN\r
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.\r
+ *\r
+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.\r
+ *\r
+ * Removes a task from both the specified event list and the list of blocked\r
+ * tasks, and places it on a ready queue.\r
+ *\r
+ * xTaskRemoveFromEventList () will be called if either an event occurs to\r
+ * unblock a task, or the block timeout period expires.\r
+ *\r
+ * @return pdTRUE if the task being removed has a higher priority than the task\r
+ * making the call, otherwise pdFALSE.\r
+ */\r
+signed portBASE_TYPE xTaskRemoveFromEventList( const xList *pxEventList );\r
+\r
+/*\r
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN\r
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.\r
+ *\r
+ * INCLUDE_vTaskCleanUpResources and INCLUDE_vTaskSuspend must be defined as 1\r
+ * for this function to be available.\r
+ * See the configuration section for more information.\r
+ *\r
+ * Empties the ready and delayed queues of task control blocks, freeing the\r
+ * memory allocated for the task control block and task stacks as it goes.\r
+ */\r
+void vTaskCleanUpResources( void );\r
+\r
+/*\r
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS ONLY\r
+ * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS\r
+ * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.\r
+ *\r
+ * Sets the pointer to the current TCB to the TCB of the highest priority task\r
+ * that is ready to run.\r
+ */\r
+inline void vTaskSwitchContext( void );\r
+\r
+/*\r
+ * Return the handle of the calling task.\r
+ */\r
+xTaskHandle xTaskGetCurrentTaskHandle( void );\r
+\r
+\r
+#endif /* TASK_H */\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+Changes from V1.2.0\r
+\r
+ + Removed the volatile modifier from the function parameters. This was\r
+ only ever included to prevent compiler warnings. Now warnings are\r
+ removed by casting parameters where the calls are made.\r
+\r
+ + prvListGetOwnerOfNextEntry() and prvListGetOwnerOfHeadEntry() have been\r
+ removed from the c file and added as macros to the h file.\r
+\r
+ + uxNumberOfItems has been added to the list structure. This removes the\r
+ need for a pointer comparison when checking if a list is empty, and so\r
+ is slightly faster.\r
+\r
+ + Removed the NULL check in vListRemove(). This makes the call faster but\r
+ necessitates any application code utilising the list implementation to\r
+ ensure NULL pointers are not passed.\r
+\r
+Changes from V2.0.0\r
+\r
+ + Double linked the lists to allow faster removal item removal.\r
+\r
+Changes from V2.6.1\r
+\r
+ + Make use of the new portBASE_TYPE definition where ever appropriate.\r
+\r
+Changes from V3.0.0\r
+\r
+ + API changes as described on the FreeRTOS.org WEB site.\r
+\r
+Changes from V3.2.4\r
+\r
+ + Removed the pxHead member of the xList structure. This always pointed\r
+ to the same place so has been removed to free a few bytes of RAM.\r
+\r
+ + Introduced the xMiniListItem structure that does not include the \r
+ xListItem members that are not required by the xListEnd member of a list.\r
+ Again this was done to reduce RAM usage.\r
+\r
+ + Changed the volatile definitions of some structure members to clean up\r
+ the code where the list structures are used.\r
+*/\r
+\r
+#include <stdlib.h>\r
+#include "FreeRTOS.h"\r
+#include "list.h"\r
+\r
+/*-----------------------------------------------------------\r
+ * PUBLIC LIST API documented in list.h\r
+ *----------------------------------------------------------*/\r
+\r
+void vListInitialise( xList *pxList )\r
+{\r
+ /* The list structure contains a list item which is used to mark the\r
+ end of the list. To initialise the list the list end is inserted\r
+ as the only list entry. */\r
+ pxList->pxIndex = ( xListItem * ) &( pxList->xListEnd );\r
+\r
+ /* The list end value is the highest possible value in the list to\r
+ ensure it remains at the end of the list. */\r
+ pxList->xListEnd.xItemValue = portMAX_DELAY;\r
+\r
+ /* The list end next and previous pointers point to itself so we know\r
+ when the list is empty. */\r
+ pxList->xListEnd.pxNext = ( xListItem * ) &( pxList->xListEnd );\r
+ pxList->xListEnd.pxPrevious = ( xListItem * ) &( pxList->xListEnd );\r
+\r
+ pxList->uxNumberOfItems = 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vListInitialiseItem( xListItem *pxItem )\r
+{\r
+ /* Make sure the list item is not recorded as being on a list. */\r
+ pxItem->pvContainer = NULL;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vListInsertEnd( xList *pxList, xListItem *pxNewListItem )\r
+{\r
+volatile xListItem * pxIndex;\r
+\r
+ /* Insert a new list item into pxList, but rather than sort the list,\r
+ makes the new list item the last item to be removed by a call to\r
+ pvListGetOwnerOfNextEntry. This means it has to be the item pointed to by\r
+ the pxIndex member. */\r
+ pxIndex = pxList->pxIndex;\r
+\r
+ pxNewListItem->pxNext = pxIndex->pxNext;\r
+ pxNewListItem->pxPrevious = pxList->pxIndex;\r
+ pxIndex->pxNext->pxPrevious = ( volatile xListItem * ) pxNewListItem;\r
+ pxIndex->pxNext = ( volatile xListItem * ) pxNewListItem;\r
+ pxList->pxIndex = ( volatile xListItem * ) pxNewListItem;\r
+\r
+ /* Remember which list the item is in. */\r
+ pxNewListItem->pvContainer = ( void * ) pxList;\r
+\r
+ ( pxList->uxNumberOfItems )++;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vListInsert( xList *pxList, xListItem *pxNewListItem )\r
+{\r
+volatile xListItem *pxIterator;\r
+portTickType xValueOfInsertion;\r
+\r
+ /* Insert the new list item into the list, sorted in ulListItem order. */\r
+ xValueOfInsertion = pxNewListItem->xItemValue;\r
+\r
+ /* If the list already contains a list item with the same item value then\r
+ the new list item should be placed after it. This ensures that TCB's which\r
+ are stored in ready lists (all of which have the same ulListItem value)\r
+ get an equal share of the CPU. However, if the xItemValue is the same as \r
+ the back marker the iteration loop below will not end. This means we need\r
+ to guard against this by checking the value first and modifying the \r
+ algorithm slightly if necessary. */\r
+ if( xValueOfInsertion == portMAX_DELAY )\r
+ {\r
+ for( pxIterator = ( xListItem * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue < xValueOfInsertion; pxIterator = pxIterator->pxNext )\r
+ {\r
+ /* There is nothing to do here, we are just iterating to the\r
+ wanted insertion position. */\r
+ }\r
+ }\r
+ else\r
+ {\r
+ for( pxIterator = ( xListItem * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext )\r
+ {\r
+ /* There is nothing to do here, we are just iterating to the\r
+ wanted insertion position. */\r
+ }\r
+ }\r
+\r
+ pxNewListItem->pxNext = pxIterator->pxNext;\r
+ pxNewListItem->pxNext->pxPrevious = ( volatile xListItem * ) pxNewListItem;\r
+ pxNewListItem->pxPrevious = pxIterator;\r
+ pxIterator->pxNext = ( volatile xListItem * ) pxNewListItem;\r
+\r
+ /* Remember which list the item is in. This allows fast removal of the\r
+ item later. */\r
+ pxNewListItem->pvContainer = ( void * ) pxList;\r
+\r
+ ( pxList->uxNumberOfItems )++;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vListRemove( xListItem *pxItemToRemove )\r
+{\r
+xList * pxList;\r
+\r
+ pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;\r
+ pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;\r
+ \r
+ /* The list item knows which list it is in. Obtain the list from the list\r
+ item. */\r
+ pxList = ( xList * ) pxItemToRemove->pvContainer;\r
+\r
+ /* Make sure the index is left pointing to a valid item. */\r
+ if( pxList->pxIndex == pxItemToRemove )\r
+ {\r
+ pxList->pxIndex = pxItemToRemove->pxPrevious;\r
+ }\r
+\r
+ pxItemToRemove->pvContainer = NULL;\r
+ ( pxList->uxNumberOfItems )--;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+Changes from V1.00:\r
+\r
+ + Call to taskYIELD() from within tick ISR has been replaced by the more\r
+ efficient portSWITCH_CONTEXT().\r
+ + ISR function definitions renamed to include the prv prefix.\r
+\r
+Changes from V2.6.1\r
+\r
+ + Replaced the sUsingPreemption variable with the configUSE_PREEMPTION\r
+ macro to be consistent with the later ports.\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Implementation of functions defined in portable.h for the Flashlite 186\r
+ * port.\r
+ *----------------------------------------------------------*/\r
+\r
+#include <dos.h>\r
+#include <stdlib.h>\r
+#include <setjmp.h>\r
+\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "portasm.h"\r
+\r
+/*lint -e950 Non ANSI reserved words okay in this file only. */\r
+\r
+#define portTIMER_EOI_TYPE ( 8 )\r
+#define portRESET_PIC() portOUTPUT_WORD( ( unsigned portSHORT ) 0xff22, portTIMER_EOI_TYPE )\r
+#define portTIMER_INT_NUMBER 0x12\r
+\r
+#define portTIMER_1_CONTROL_REGISTER ( ( unsigned portSHORT ) 0xff5e )\r
+#define portTIMER_0_CONTROL_REGISTER ( ( unsigned portSHORT ) 0xff56 )\r
+#define portTIMER_INTERRUPT_ENABLE ( ( unsigned portSHORT ) 0x2000 )\r
+\r
+/* Setup the hardware to generate the required tick frequency. */\r
+static void prvSetTickFrequency( unsigned portLONG ulTickRateHz );\r
+\r
+/* Set the hardware back to the state as per before the scheduler started. */\r
+static void prvExitFunction( void );\r
+\r
+/* The ISR used depends on whether the preemptive or cooperative scheduler\r
+is being used. */\r
+#if( configUSE_PREEMPTION == 1 )\r
+ /* Tick service routine used by the scheduler when preemptive scheduling is\r
+ being used. */\r
+ static void __interrupt __far prvPreemptiveTick( void );\r
+#else\r
+ /* Tick service routine used by the scheduler when cooperative scheduling is\r
+ being used. */\r
+ static void __interrupt __far prvNonPreemptiveTick( void );\r
+#endif\r
+\r
+/* Trap routine used by taskYIELD() to manually cause a context switch. */\r
+static void __interrupt __far prvYieldProcessor( void );\r
+\r
+/*lint -e956 File scopes necessary here. */\r
+\r
+/* Set true when the vectors are set so the scheduler will service the tick. */\r
+static portBASE_TYPE xSchedulerRunning = pdFALSE;\r
+\r
+/* Points to the original routine installed on the vector we use for manual\r
+context switches. This is then used to restore the original routine during\r
+prvExitFunction(). */\r
+static void ( __interrupt __far *pxOldSwitchISR )();\r
+\r
+/* Used to restore the original DOS context when the scheduler is ended. */\r
+static jmp_buf xJumpBuf;\r
+\r
+/*lint +e956 */\r
+\r
+/*-----------------------------------------------------------*/\r
+portBASE_TYPE xPortStartScheduler( void )\r
+{\r
+ /* This is called with interrupts already disabled. */\r
+\r
+ /* Remember what was on the interrupts we are going to use\r
+ so we can put them back later if required. */\r
+ pxOldSwitchISR = _dos_getvect( portSWITCH_INT_NUMBER );\r
+\r
+ /* Put our manual switch (yield) function on a known\r
+ vector. */\r
+ _dos_setvect( portSWITCH_INT_NUMBER, prvYieldProcessor );\r
+\r
+ #if( configUSE_PREEMPTION == 1 )\r
+ {\r
+ /* Put our tick switch function on the timer interrupt. */\r
+ _dos_setvect( portTIMER_INT_NUMBER, prvPreemptiveTick );\r
+ }\r
+ #else\r
+ {\r
+ /* We want the timer interrupt to just increment the tick count. */\r
+ _dos_setvect( portTIMER_INT_NUMBER, prvNonPreemptiveTick );\r
+ }\r
+ #endif\r
+\r
+ prvSetTickFrequency( configTICK_RATE_HZ );\r
+\r
+ /* Clean up function if we want to return to DOS. */\r
+ if( setjmp( xJumpBuf ) != 0 )\r
+ {\r
+ prvExitFunction();\r
+ xSchedulerRunning = pdFALSE;\r
+ }\r
+ else\r
+ {\r
+ xSchedulerRunning = pdTRUE;\r
+\r
+ /* Kick off the scheduler by setting up the context of the first task. */\r
+ portFIRST_CONTEXT();\r
+ }\r
+\r
+ return xSchedulerRunning;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The ISR used depends on whether the preemptive or cooperative scheduler\r
+is being used. */\r
+#if( configUSE_PREEMPTION == 1 )\r
+ static void __interrupt __far prvPreemptiveTick( void )\r
+ {\r
+ /* Get the scheduler to update the task states following the tick. */\r
+ vTaskIncrementTick();\r
+\r
+ /* Switch in the context of the next task to be run. */\r
+ portSWITCH_CONTEXT();\r
+\r
+ /* Reset the PIC ready for the next time. */\r
+ portRESET_PIC();\r
+ }\r
+#else\r
+ static void __interrupt __far prvNonPreemptiveTick( void )\r
+ {\r
+ /* Same as preemptive tick, but the cooperative scheduler is being used\r
+ so we don't have to switch in the context of the next task. */\r
+ vTaskIncrementTick();\r
+ portRESET_PIC();\r
+ }\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+static void __interrupt __far prvYieldProcessor( void )\r
+{\r
+ /* Switch in the context of the next task to be run. */\r
+ portSWITCH_CONTEXT();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEndScheduler( void )\r
+{\r
+ /* Jump back to the processor state prior to starting the\r
+ scheduler. This means we are not going to be using a\r
+ task stack frame so the task can be deleted. */\r
+ longjmp( xJumpBuf, 1 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvExitFunction( void )\r
+{\r
+const unsigned portSHORT usTimerDisable = 0x0000;\r
+unsigned portSHORT usTimer0Control;\r
+\r
+ /* Interrupts should be disabled here anyway - but no\r
+ harm in making sure. */\r
+ portDISABLE_INTERRUPTS();\r
+ if( xSchedulerRunning == pdTRUE )\r
+ {\r
+ /* Put back the switch interrupt routines that was in place\r
+ before the scheduler started. */\r
+ _dos_setvect( portSWITCH_INT_NUMBER, pxOldSwitchISR );\r
+ }\r
+\r
+ /* Disable the timer used for the tick to ensure the scheduler is\r
+ not called before restoring interrupts. There was previously nothing\r
+ on this timer so there is no old ISR to restore. */\r
+ portOUTPUT_WORD( portTIMER_1_CONTROL_REGISTER, usTimerDisable );\r
+\r
+ /* Restart the DOS tick. */\r
+ usTimer0Control = portINPUT_WORD( portTIMER_0_CONTROL_REGISTER );\r
+ usTimer0Control |= portTIMER_INTERRUPT_ENABLE;\r
+ portOUTPUT_WORD( portTIMER_0_CONTROL_REGISTER, usTimer0Control );\r
+\r
+\r
+ portENABLE_INTERRUPTS();\r
+\r
+ /* This will free up all the memory used by the scheduler.\r
+ exiting back to dos with INT21 AH=4CH will do this anyway so\r
+ it is not necessary to call this. */\r
+ vTaskCleanUpResources();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetTickFrequency( unsigned portLONG ulTickRateHz )\r
+{\r
+const unsigned portSHORT usMaxCountRegister = 0xff5a;\r
+const unsigned portSHORT usTimerPriorityRegister = 0xff32;\r
+const unsigned portSHORT usTimerEnable = 0xC000;\r
+const unsigned portSHORT usRetrigger = 0x0001;\r
+const unsigned portSHORT usTimerHighPriority = 0x0000;\r
+unsigned portSHORT usTimer0Control;\r
+\r
+/* ( CPU frequency / 4 ) / clock 2 max count [inpw( 0xff62 ) = 7] */\r
+\r
+const unsigned portLONG ulClockFrequency = ( unsigned portLONG ) 0x7f31a0UL;\r
+\r
+unsigned portLONG ulTimerCount = ulClockFrequency / ulTickRateHz;\r
+\r
+ portOUTPUT_WORD( portTIMER_1_CONTROL_REGISTER, usTimerEnable | portTIMER_INTERRUPT_ENABLE | usRetrigger );\r
+ portOUTPUT_WORD( usMaxCountRegister, ( unsigned portSHORT ) ulTimerCount );\r
+ portOUTPUT_WORD( usTimerPriorityRegister, usTimerHighPriority );\r
+\r
+ /* Stop the DOS tick - don't do this if you want to maintain a TOD clock. */\r
+ usTimer0Control = portINPUT_WORD( portTIMER_0_CONTROL_REGISTER );\r
+ usTimer0Control &= ~portTIMER_INTERRUPT_ENABLE;\r
+ portOUTPUT_WORD( portTIMER_0_CONTROL_REGISTER, usTimer0Control );\r
+}\r
+\r
+\r
+/*lint +e950 */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Port specific definitions. \r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the\r
+ * given hardware and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *-----------------------------------------------------------\r
+ */\r
+\r
+/* Type definitions. */\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE long\r
+#define portLONG long\r
+#define portSHORT int\r
+#define portSTACK_TYPE unsigned portSHORT\r
+#define portBASE_TYPE portSHORT\r
+\r
+#if( configUSE_16_BIT_TICKS == 1 )\r
+ typedef unsigned portSHORT portTickType;\r
+ #define portMAX_DELAY ( portTickType ) 0xffff\r
+#else\r
+ typedef unsigned portLONG portTickType;\r
+ #define portMAX_DELAY ( portTickType ) 0xffffffff\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Critical section handling. */\r
+#define portENTER_CRITICAL() __asm{ pushf } \\r
+ __asm{ cli } \\r
+\r
+#define portEXIT_CRITICAL() __asm{ popf }\r
+\r
+#define portDISABLE_INTERRUPTS() __asm{ cli }\r
+\r
+#define portENABLE_INTERRUPTS() __asm{ sti }\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Hardware specifics. */\r
+#define portNOP() __asm{ nop }\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portSWITCH_INT_NUMBER 0x80\r
+#define portYIELD() __asm{ int portSWITCH_INT_NUMBER } \r
+#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) \r
+#define portBYTE_ALIGNMENT 2\r
+#define portINITIAL_SW ( ( portSTACK_TYPE ) 0x0202 ) /* Start the tasks with interrupts enabled. */\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Compiler specifics. */\r
+#define portINPUT_BYTE( xAddr ) inp( xAddr )\r
+#define portOUTPUT_BYTE( xAddr, ucValue ) outp( xAddr, ucValue )\r
+#define portINPUT_WORD( xAddr ) inpw( xAddr )\r
+#define portOUTPUT_WORD( xAddr, usValue ) outpw( xAddr, usValue )\r
+#define inline\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Task function macros as described on the FreeRTOS.org WEB site. */\r
+#define portTASK_FUNCTION_PROTO( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters )\r
+\r
+#endif /* PORTMACRO_H */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+Changes from V2.6.1\r
+\r
+ + Replaced the sUsingPreemption variable with the configUSE_PREEMPTION\r
+ macro to be consistent with the later ports.\r
+*/\r
+\r
+#include <stdlib.h>\r
+#include <dos.h>\r
+#include <setjmp.h>\r
+\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "portasm.h"\r
+\r
+/*-----------------------------------------------------------\r
+ * Implementation of functions defined in portable.h for the industrial\r
+ * PC port.\r
+ *----------------------------------------------------------*/\r
+\r
+/*lint -e950 Non ANSI reserved words okay in this file only. */\r
+\r
+#define portTIMER_INT_NUMBER 0x08\r
+\r
+/* Setup hardware for required tick interrupt rate. */\r
+static void prvSetTickFrequency( unsigned portLONG ulTickRateHz );\r
+\r
+/* Restore hardware to as it was prior to starting the scheduler. */\r
+static void prvExitFunction( void );\r
+\r
+/* Either chain to the DOS tick (which itself clears the PIC) or clear the PIC\r
+directly. We chain to the DOS tick as close as possible to the standard DOS\r
+tick rate. */\r
+static void prvPortResetPIC( void );\r
+\r
+/* The ISR used depends on whether the preemptive or cooperative\r
+scheduler is being used. */\r
+#if( configUSE_PREEMPTION == 1 )\r
+ /* Tick service routine used by the scheduler when preemptive scheduling is\r
+ being used. */\r
+ static void __interrupt __far prvPreemptiveTick( void );\r
+#else\r
+ /* Tick service routine used by the scheduler when cooperative scheduling is\r
+ being used. */\r
+ static void __interrupt __far prvNonPreemptiveTick( void );\r
+#endif\r
+\r
+/* Trap routine used by taskYIELD() to manually cause a context switch. */\r
+static void __interrupt __far prvYieldProcessor( void );\r
+\r
+/*lint -e956 File scopes necessary here. */\r
+\r
+/* Used to signal when to chain to the DOS tick, and when to just clear the PIC ourselves. */\r
+static portSHORT sDOSTickCounter;\r
+\r
+/* Set true when the vectors are set so the scheduler will service the tick. */\r
+static portBASE_TYPE xSchedulerRunning = pdFALSE; \r
+\r
+/* Points to the original routine installed on the vector we use for manual context switches. This is then used to restore the original routine during prvExitFunction(). */\r
+static void ( __interrupt __far *pxOldSwitchISR )(); \r
+\r
+/* Points to the original routine installed on the vector we use to chain to the DOS tick. This is then used to restore the original routine during prvExitFunction(). */\r
+static void ( __interrupt __far *pxOldSwitchISRPlus1 )(); \r
+\r
+/* Used to restore the original DOS context when the scheduler is ended. */\r
+static jmp_buf xJumpBuf;\r
+\r
+/*lint +e956 */\r
+\r
+/*-----------------------------------------------------------*/\r
+portBASE_TYPE xPortStartScheduler( void )\r
+{\r
+pxISR pxOriginalTickISR;\r
+ \r
+ /* This is called with interrupts already disabled. */\r
+\r
+ /* Remember what was on the interrupts we are going to use\r
+ so we can put them back later if required. */\r
+ pxOldSwitchISR = _dos_getvect( portSWITCH_INT_NUMBER );\r
+ pxOriginalTickISR = _dos_getvect( portTIMER_INT_NUMBER );\r
+ pxOldSwitchISRPlus1 = _dos_getvect( portSWITCH_INT_NUMBER + 1 );\r
+\r
+ prvSetTickFrequency( configTICK_RATE_HZ );\r
+\r
+ /* Put our manual switch (yield) function on a known\r
+ vector. */\r
+ _dos_setvect( portSWITCH_INT_NUMBER, prvYieldProcessor );\r
+\r
+ /* Put the old tick on a different interrupt number so we can\r
+ call it when we want. */\r
+ _dos_setvect( portSWITCH_INT_NUMBER + 1, pxOriginalTickISR );\r
+\r
+ /* The ISR used depends on whether the preemptive or cooperative\r
+ scheduler is being used. */\r
+ #if( configUSE_PREEMPTION == 1 )\r
+ {\r
+ /* Put our tick switch function on the timer interrupt. */\r
+ _dos_setvect( portTIMER_INT_NUMBER, prvPreemptiveTick );\r
+ }\r
+ #else\r
+ {\r
+ /* We want the timer interrupt to just increment the tick count. */\r
+ _dos_setvect( portTIMER_INT_NUMBER, prvNonPreemptiveTick );\r
+ }\r
+ #endif\r
+\r
+ /* Setup a counter that is used to call the DOS interrupt as close\r
+ to it's original frequency as can be achieved given our chosen tick\r
+ frequency. */\r
+ sDOSTickCounter = portTICKS_PER_DOS_TICK;\r
+\r
+ /* Clean up function if we want to return to DOS. */\r
+ if( setjmp( xJumpBuf ) != 0 )\r
+ {\r
+ prvExitFunction();\r
+ xSchedulerRunning = pdFALSE;\r
+ }\r
+ else\r
+ {\r
+ xSchedulerRunning = pdTRUE;\r
+\r
+ /* Kick off the scheduler by setting up the context of the first task. */\r
+ portFIRST_CONTEXT();\r
+ }\r
+\r
+ return xSchedulerRunning;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The ISR used depends on whether the preemptive or cooperative\r
+scheduler is being used. */\r
+#if( configUSE_PREEMPTION == 1 )\r
+ static void __interrupt __far prvPreemptiveTick( void )\r
+ {\r
+ /* Get the scheduler to update the task states following the tick. */\r
+ vTaskIncrementTick();\r
+\r
+ /* Switch in the context of the next task to be run. */\r
+ portSWITCH_CONTEXT();\r
+\r
+ /* Reset the PIC ready for the next time. */\r
+ prvPortResetPIC();\r
+ }\r
+#else\r
+ static void __interrupt __far prvNonPreemptiveTick( void )\r
+ {\r
+ /* Same as preemptive tick, but the cooperative scheduler is being used\r
+ so we don't have to switch in the context of the next task. */\r
+ vTaskIncrementTick();\r
+ prvPortResetPIC();\r
+ }\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+static void __interrupt __far prvYieldProcessor( void )\r
+{\r
+ /* Switch in the context of the next task to be run. */\r
+ portSWITCH_CONTEXT();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvPortResetPIC( void )\r
+{\r
+ /* We are going to call the DOS tick interrupt at as close a\r
+ frequency to the normal DOS tick as possible. */\r
+\r
+ /* WE SHOULD NOT DO THIS IF YIELD WAS CALLED. */\r
+ --sDOSTickCounter;\r
+ if( sDOSTickCounter <= 0 )\r
+ {\r
+ sDOSTickCounter = ( portSHORT ) portTICKS_PER_DOS_TICK;\r
+ __asm{ int portSWITCH_INT_NUMBER + 1 }; \r
+ }\r
+ else\r
+ {\r
+ /* Reset the PIC as the DOS tick is not being called to\r
+ do it. */\r
+ __asm\r
+ {\r
+ mov al, 20H\r
+ out 20H, al\r
+ };\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEndScheduler( void )\r
+{\r
+ /* Jump back to the processor state prior to starting the\r
+ scheduler. This means we are not going to be using a\r
+ task stack frame so the task can be deleted. */\r
+ longjmp( xJumpBuf, 1 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvExitFunction( void )\r
+{\r
+void ( __interrupt __far *pxOriginalTickISR )();\r
+\r
+ /* Interrupts should be disabled here anyway - but no \r
+ harm in making sure. */\r
+ portDISABLE_INTERRUPTS();\r
+ if( xSchedulerRunning == pdTRUE )\r
+ {\r
+ /* Set the DOS tick back onto the timer ticker. */\r
+ pxOriginalTickISR = _dos_getvect( portSWITCH_INT_NUMBER + 1 );\r
+ _dos_setvect( portTIMER_INT_NUMBER, pxOriginalTickISR );\r
+ /* This won't set the frequency quite the same as it was,\r
+ but using an integer value removes the need for any floating\r
+ point in the scheduler code. */\r
+ prvSetTickFrequency( ( unsigned portLONG ) portDOS_TICK_RATE );\r
+\r
+ /* Put back the switch interrupt routines that was in place\r
+ before the scheduler started. */\r
+ _dos_setvect( portSWITCH_INT_NUMBER, pxOldSwitchISR );\r
+ _dos_setvect( portSWITCH_INT_NUMBER + 1, pxOldSwitchISRPlus1 );\r
+ }\r
+ /* The tick timer is back how DOS wants it. We can re-enable\r
+ interrupts without the scheduler being called. */\r
+ portENABLE_INTERRUPTS();\r
+\r
+ /* This will free up all the memory used by the scheduler.\r
+ exiting back to dos with INT21 AH=4CH will do this anyway so\r
+ it is not necessary to call this. */\r
+ vTaskCleanUpResources(); \r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetTickFrequency( unsigned portLONG ulTickRateHz )\r
+{\r
+const unsigned portSHORT usPIT_MODE = ( unsigned portSHORT ) 0x43;\r
+const unsigned portSHORT usPIT0 = ( unsigned portSHORT ) 0x40;\r
+const unsigned portLONG ulPIT_CONST = ( unsigned portLONG ) 1193180UL;\r
+const unsigned portSHORT us8254_CTR0_MODE3 = ( unsigned portSHORT ) 0x36;\r
+unsigned portLONG ulOutput;\r
+\r
+ /* Setup the 8245 to tick at the wanted frequency. */\r
+ portOUTPUT_BYTE( usPIT_MODE, us8254_CTR0_MODE3 );\r
+ ulOutput = ulPIT_CONST / ulTickRateHz;\r
+ portOUTPUT_BYTE( usPIT0, ( unsigned portSHORT )( ulOutput & ( unsigned portLONG ) 0xff ) );\r
+ ulOutput >>= 8;\r
+ portOUTPUT_BYTE( usPIT0, ( unsigned portSHORT ) ( ulOutput & ( unsigned portLONG ) 0xff ) );\r
+}\r
+\r
+\r
+/*lint +e950 */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Port specific definitions. \r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the\r
+ * given hardware and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *-----------------------------------------------------------\r
+ */\r
+\r
+/* Type definitions. */\r
+#define portCHAR char\r
+#define portFLOAT long\r
+#define portDOUBLE long\r
+#define portLONG long\r
+#define portSHORT int\r
+#define portSTACK_TYPE unsigned portSHORT\r
+#define portBASE_TYPE portSHORT\r
+\r
+#if( configUSE_16_BIT_TICKS == 1 )\r
+ typedef unsigned portSHORT portTickType;\r
+ #define portMAX_DELAY ( portTickType ) 0xffff\r
+#else\r
+ typedef unsigned portLONG portTickType;\r
+ #define portMAX_DELAY ( portTickType ) 0xffffffff\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Critical section management. */\r
+#define portENTER_CRITICAL() __asm{ pushf } \\r
+ __asm{ cli } \\r
+\r
+#define portEXIT_CRITICAL() __asm{ popf }\r
+\r
+#define portDISABLE_INTERRUPTS() __asm{ cli }\r
+\r
+#define portENABLE_INTERRUPTS() __asm{ sti }\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Hardware specifics. */\r
+#define portNOP() __asm{ nop }\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portSWITCH_INT_NUMBER 0x80\r
+#define portYIELD() __asm{ int portSWITCH_INT_NUMBER } \r
+#define portDOS_TICK_RATE ( 18.20648 )\r
+#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) \r
+#define portTICKS_PER_DOS_TICK ( ( unsigned portSHORT ) ( ( ( portDOUBLE ) configTICK_RATE_HZ / portDOS_TICK_RATE ) + 0.5 ) )\r
+#define portINITIAL_SW ( ( portSTACK_TYPE ) 0x0202 ) /* Start the tasks with interrupts enabled. */\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Compiler specifics. */\r
+#define portINPUT_BYTE( xAddr ) inp( xAddr )\r
+#define portOUTPUT_BYTE( xAddr, ucValue ) outp( xAddr, ucValue )\r
+#define inline\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Task function macros as described on the FreeRTOS.org WEB site. */\r
+#define portTASK_FUNCTION_PROTO( vTaskFunction, pvParameters ) void vTaskFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vTaskFunction, pvParameters ) void vTaskFunction( void *pvParameters )\r
+\r
+#endif /* PORTMACRO_H */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+typedef void tskTCB;\r
+extern volatile tskTCB * volatile pxCurrentTCB;\r
+extern void vTaskSwitchContext( void );\r
+\r
+/*\r
+ * Saves the stack pointer for one task into its TCB, calls\r
+ * vTaskSwitchContext() to update the TCB being used, then restores the stack\r
+ * from the new TCB read to run the task.\r
+ */\r
+void portSWITCH_CONTEXT( void );\r
+\r
+/*\r
+ * Load the stack pointer from the TCB of the task which is going to be first\r
+ * to execute. Then force an IRET so the registers and IP are popped off the\r
+ * stack.\r
+ */\r
+void portFIRST_CONTEXT( void );\r
+\r
+/* There are slightly different versions depending on whether you are building\r
+to include debugger information. If debugger information is used then there\r
+are a couple of extra bytes left of the ISR stack (presumably for use by the\r
+debugger). The true stack pointer is then stored in the bp register. We add\r
+2 to the stack pointer to remove the extra bytes before we restore our context. */\r
+\r
+#define portSWITCH_CONTEXT() \\r
+ asm { mov ax, seg pxCurrentTCB } \\r
+ asm { mov ds, ax } \\r
+ asm { les bx, pxCurrentTCB } /* Save the stack pointer into the TCB. */ \\r
+ asm { mov es:0x2[ bx ], ss } \\r
+ asm { mov es:[ bx ], sp } \\r
+ asm { call far ptr vTaskSwitchContext } /* Perform the switch. */ \\r
+ asm { mov ax, seg pxCurrentTCB } /* Restore the stack pointer from the TCB. */ \\r
+ asm { mov ds, ax } \\r
+ asm { les bx, dword ptr pxCurrentTCB } \\r
+ asm { mov ss, es:[ bx + 2 ] } \\r
+ asm { mov sp, es:[ bx ] }\r
+\r
+#define portFIRST_CONTEXT() \\r
+ __asm { mov ax, seg pxCurrentTCB } \\r
+ __asm { mov ds, ax } \\r
+ __asm { les bx, dword ptr pxCurrentTCB } \\r
+ __asm { mov ss, es:[ bx + 2 ] } \\r
+ __asm { mov sp, es:[ bx ] } \\r
+ __asm { pop bx } \\r
+ __asm { pop di } \\r
+ __asm { pop si } \\r
+ __asm { pop ds } \\r
+ __asm { pop es } \\r
+ __asm { pop dx } \\r
+ __asm { pop cx } \\r
+ __asm { pop bx } \\r
+ __asm { pop ax } \\r
+ __asm { iret }\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+Changes from V1.00:\r
+\r
+ + pxPortInitialiseStack() now initialises the stack of new tasks to the\r
+ same format used by the compiler. This allows the compiler generated\r
+ interrupt mechanism to be used for context switches.\r
+\r
+Changes from V2.6.1\r
+\r
+ + Move usPortCheckFreeStackSpace() to tasks.c.\r
+*/\r
+\r
+\r
+#include <dos.h>\r
+#include <stdlib.h>\r
+#include "FreeRTOS.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* See header file for description. */\r
+portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
+{\r
+portSTACK_TYPE DS_Reg = 0;\r
+\r
+ /* Place a few bytes of known values on the bottom of the stack.\r
+ This is just useful for debugging. */\r
+\r
+ *pxTopOfStack = 0x1111;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x2222;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x3333;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x4444;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x5555;\r
+ pxTopOfStack--;\r
+\r
+\r
+ /*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */\r
+\r
+ /* We are going to start the scheduler using a return from interrupt\r
+ instruction to load the program counter, so first there would be the\r
+ function call with parameters preamble. */\r
+ \r
+ *pxTopOfStack = FP_SEG( pvParameters );\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = FP_OFF( pvParameters );\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = FP_SEG( pxCode );\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = FP_OFF( pxCode );\r
+ pxTopOfStack--;\r
+\r
+ /* Next the status register and interrupt return address. */\r
+ *pxTopOfStack = portINITIAL_SW; \r
+ pxTopOfStack--;\r
+ *pxTopOfStack = FP_SEG( pxCode );\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = FP_OFF( pxCode );\r
+ pxTopOfStack--;\r
+\r
+ /* The remaining registers would be pushed on the stack by our context\r
+ switch function. These are loaded with values simply to make debugging\r
+ easier. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0xAAAA; /* AX */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0xBBBB; /* BX */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0xCCCC; /* CX */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0xDDDD; /* DX */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0xEEEE; /* ES */\r
+ pxTopOfStack--;\r
+\r
+ /* We need the true data segment. */\r
+ __asm{ MOV DS_Reg, DS };\r
+\r
+ *pxTopOfStack = DS_Reg; /* DS */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x0123; /* SI */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0xDDDD; /* DI */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0xBBBB; /* BP */\r
+\r
+ /*lint +e950 +e611 +e923 */\r
+\r
+ return pxTopOfStack;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+/* \r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ * Implementation of functions defined in portable.h for the HCS12 port.\r
+ *----------------------------------------------------------*/\r
+\r
+\r
+/*\r
+ * Configure a timer to generate the RTOS tick at the frequency specified \r
+ * within FreeRTOSConfig.h.\r
+ */\r
+static void prvSetupTimerInterrupt( void );\r
+\r
+/* Interrupt service routines have to be in non-banked memory - as does the\r
+scheduler startup function. */\r
+#pragma CODE_SEG __NEAR_SEG NON_BANKED\r
+\r
+ /* Manual context switch function. This is the SWI ISR. */\r
+ void interrupt vPortYield( void );\r
+\r
+ /* Tick context switch function. This is the timer ISR. */\r
+ void interrupt vPortTickInterrupt( void );\r
+ \r
+ /* Simply called by xPortStartScheduler(). xPortStartScheduler() does not\r
+ start the scheduler directly because the header file containing the \r
+ xPortStartScheduler() prototype is part of the common kernel code, and \r
+ therefore cannot use the CODE_SEG pragma. */\r
+ static portBASE_TYPE xBankedStartScheduler( void );\r
+\r
+#pragma CODE_SEG DEFAULT\r
+\r
+/* Calls to portENTER_CRITICAL() can be nested. When they are nested the \r
+critical section should not be left (i.e. interrupts should not be re-enabled)\r
+until the nesting depth reaches 0. This variable simply tracks the nesting \r
+depth. Each task maintains it's own critical nesting depth variable so \r
+uxCriticalNesting is saved and restored from the task stack during a context\r
+switch. */\r
+volatile unsigned portBASE_TYPE uxCriticalNesting = 0xff;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* \r
+ * See header file for description. \r
+ */\r
+portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
+{\r
+ /* \r
+ Place a few bytes of known values on the bottom of the stack.\r
+ This can be uncommented to provide useful stack markers when debugging.\r
+\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x11;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x22;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x33;\r
+ pxTopOfStack--;\r
+ */\r
+\r
+\r
+\r
+ /* Setup the initial stack of the task. The stack is set exactly as \r
+ expected by the portRESTORE_CONTEXT() macro. In this case the stack as\r
+ expected by the HCS12 RTI instruction. */\r
+\r
+\r
+ /* The address of the task function is placed in the stack byte at a time. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) *( ((portSTACK_TYPE *) (&pxCode) ) + 1 );\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) *( ((portSTACK_TYPE *) (&pxCode) ) + 0 );\r
+ pxTopOfStack--;\r
+\r
+ /* Next are all the registers that form part of the task context. */\r
+\r
+ /* Y register */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0xff;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0xee;\r
+ pxTopOfStack--;\r
+\r
+ /* X register */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0xdd;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0xcc;\r
+ pxTopOfStack--;\r
+ \r
+ /* A register contains parameter high byte. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) *( ((portSTACK_TYPE *) (&pvParameters) ) + 0 );\r
+ pxTopOfStack--;\r
+\r
+ /* B register contains parameter low byte. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) *( ((portSTACK_TYPE *) (&pvParameters) ) + 1 );\r
+ pxTopOfStack--;\r
+\r
+ /* CCR: Note that when the task starts interrupts will be enabled since\r
+ "I" bit of CCR is cleared */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x00;\r
+ pxTopOfStack--;\r
+ \r
+ #ifdef BANKED_MODEL\r
+ /* The page of the task. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) ( ( int ) pxCode );\r
+ pxTopOfStack--;\r
+ #endif\r
+ \r
+ /* Finally the critical nesting depth is initialised with 0 (not within\r
+ a critical section). */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x00;\r
+\r
+ return pxTopOfStack;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEndScheduler( void )\r
+{\r
+ /* It is unlikely that the HCS12 port will get stopped. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupTimerInterrupt( void )\r
+{\r
+ TickTimer_SetFreqHz( configTICK_RATE_HZ );\r
+ TickTimer_Enable();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portBASE_TYPE xPortStartScheduler( void )\r
+{\r
+ /* xPortStartScheduler() does not start the scheduler directly because \r
+ the header file containing the xPortStartScheduler() prototype is part \r
+ of the common kernel code, and therefore cannot use the CODE_SEG pragma. \r
+ Instead it simply calls the locally defined xBankedStartScheduler() - \r
+ which does use the CODE_SEG pragma. */\r
+\r
+ return xBankedStartScheduler();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#pragma CODE_SEG __NEAR_SEG NON_BANKED\r
+\r
+static portBASE_TYPE xBankedStartScheduler( void )\r
+{\r
+ /* Configure the timer that will generate the RTOS tick. Interrupts are\r
+ disabled when this function is called. */\r
+ prvSetupTimerInterrupt();\r
+\r
+ /* Restore the context of the first task. */\r
+ portRESTORE_CONTEXT();\r
+\r
+ /* Simulate the end of an interrupt to start the scheduler off. */\r
+ __asm( "rti" );\r
+\r
+ /* Should not get here! */\r
+ return pdFALSE;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Context switch functions. These are both interrupt service routines.\r
+ */\r
+\r
+/*\r
+ * Manual context switch forced by calling portYIELD(). This is the SWI\r
+ * handler.\r
+ */\r
+void interrupt vPortYield( void )\r
+{\r
+ portSAVE_CONTEXT();\r
+ vTaskSwitchContext();\r
+ portRESTORE_CONTEXT();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * RTOS tick interrupt service routine. If the cooperative scheduler is \r
+ * being used then this simply increments the tick count. If the \r
+ * preemptive scheduler is being used a context switch can occur.\r
+ */\r
+void interrupt vPortTickInterrupt( void )\r
+{\r
+ #if configUSE_PREEMPTION == 1\r
+ {\r
+ /* A context switch might happen so save the context. */\r
+ portSAVE_CONTEXT();\r
+\r
+ /* Increment the tick ... */\r
+ vTaskIncrementTick();\r
+\r
+ /* ... then see if the new tick value has necessitated a\r
+ context switch. */\r
+ vTaskSwitchContext();\r
+\r
+ TFLG1 = 1; \r
+\r
+ /* Restore the context of a task - which may be a different task\r
+ to that interrupted. */\r
+ portRESTORE_CONTEXT(); \r
+ }\r
+ #else\r
+ {\r
+ vTaskIncrementTick();\r
+ TFLG1 = 1;\r
+ }\r
+ #endif\r
+}\r
+\r
+#pragma CODE_SEG DEFAULT\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Port specific definitions. \r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the\r
+ * given hardware and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *-----------------------------------------------------------\r
+ */\r
+\r
+/* Type definitions. */\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE double\r
+#define portLONG long\r
+#define portSHORT short\r
+#define portSTACK_TYPE unsigned portCHAR\r
+#define portBASE_TYPE char\r
+\r
+#if( configUSE_16_BIT_TICKS == 1 )\r
+ typedef unsigned portSHORT portTickType;\r
+ #define portMAX_DELAY ( portTickType ) 0xffff\r
+#else\r
+ typedef unsigned portLONG portTickType;\r
+ #define portMAX_DELAY ( portTickType ) 0xffffffff\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Hardware specifics. */\r
+#define portBYTE_ALIGNMENT 1\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) \r
+#define portYIELD() __asm( "swi" );\r
+#define portNOP() __asm( "nop" );\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Critical section handling. */\r
+#define portENABLE_INTERRUPTS() __asm( "cli" ) \r
+#define portDISABLE_INTERRUPTS() __asm( "sei" )\r
+\r
+/*\r
+ * Disable interrupts before incrementing the count of critical section nesting.\r
+ * The nesting count is maintained so we know when interrupts should be\r
+ * re-enabled. Once interrupts are disabled the nesting count can be accessed\r
+ * directly. Each task maintains its own nesting count.\r
+ */\r
+#define portENTER_CRITICAL() \\r
+{ \\r
+ extern volatile unsigned portBASE_TYPE uxCriticalNesting; \\r
+ \\r
+ portDISABLE_INTERRUPTS(); \\r
+ uxCriticalNesting++; \\r
+}\r
+\r
+/*\r
+ * Interrupts are disabled so we can access the nesting count directly. If the\r
+ * nesting is found to be 0 (no nesting) then we are leaving the critical \r
+ * section and interrupts can be re-enabled.\r
+ */\r
+#define portEXIT_CRITICAL() \\r
+{ \\r
+ extern volatile unsigned portBASE_TYPE uxCriticalNesting; \\r
+ \\r
+ uxCriticalNesting--; \\r
+ if( uxCriticalNesting == 0 ) \\r
+ { \\r
+ portENABLE_INTERRUPTS(); \\r
+ } \\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Task utilities. */\r
+\r
+/* \r
+ * These macros are very simple as the processor automatically saves and \r
+ * restores its registers as interrupts are entered and exited. In\r
+ * addition to the (automatically stacked) registers we also stack the \r
+ * critical nesting count. Each task maintains its own critical nesting\r
+ * count as it is legitimate for a task to yield from within a critical\r
+ * section. If the banked memory model is being used then the PPAGE\r
+ * register is also stored as part of the tasks context.\r
+ */\r
+\r
+#ifdef BANKED_MODEL\r
+ /* \r
+ * Load the stack pointer for the task, then pull the critical nesting\r
+ * count and PPAGE register from the stack. The remains of the \r
+ * context are restored by the RTI instruction.\r
+ */\r
+ #define portRESTORE_CONTEXT() \\r
+ { \\r
+ extern volatile void * pxCurrentTCB; \\r
+ extern volatile unsigned portBASE_TYPE uxCriticalNesting; \\r
+ \\r
+ __asm( "ldx pxCurrentTCB" ); \\r
+ __asm( "lds 0, x" ); \\r
+ __asm( "pula" ); \\r
+ __asm( "staa uxCriticalNesting" ); \\r
+ __asm( "pula" ); \\r
+ __asm( "staa 0x30" ); /* 0x30 = PPAGE */ \\r
+ }\r
+\r
+ /* \r
+ * By the time this macro is called the processor has already stacked the\r
+ * registers. Simply stack the nesting count and PPAGE value, then save \r
+ * the task stack pointer.\r
+ */\r
+ #define portSAVE_CONTEXT() \\r
+ { \\r
+ extern volatile void * pxCurrentTCB; \\r
+ extern volatile unsigned portBASE_TYPE uxCriticalNesting; \\r
+ \\r
+ __asm( "ldaa 0x30" ); /* 0x30 = PPAGE */ \\r
+ __asm( "psha" ); \\r
+ __asm( "ldaa uxCriticalNesting" ); \\r
+ __asm( "psha" ); \\r
+ __asm( "ldx pxCurrentTCB" ); \\r
+ __asm( "sts 0, x" ); \\r
+ }\r
+#else\r
+\r
+ /* \r
+ * These macros are as per the BANKED versions above, but without saving\r
+ * and restoring the PPAGE register.\r
+ */\r
+\r
+ #define portRESTORE_CONTEXT() \\r
+ { \\r
+ extern volatile void * pxCurrentTCB; \\r
+ extern volatile unsigned portBASE_TYPE uxCriticalNesting; \\r
+ \\r
+ __asm( "ldx pxCurrentTCB" ); \\r
+ __asm( "lds 0, x" ); \\r
+ __asm( "pula" ); \\r
+ __asm( "staa uxCriticalNesting" ); \\r
+ }\r
+\r
+ #define portSAVE_CONTEXT() \\r
+ { \\r
+ extern volatile void * pxCurrentTCB; \\r
+ extern volatile unsigned portBASE_TYPE uxCriticalNesting; \\r
+ \\r
+ __asm( "ldaa uxCriticalNesting" ); \\r
+ __asm( "psha" ); \\r
+ __asm( "ldx pxCurrentTCB" ); \\r
+ __asm( "sts 0, x" ); \\r
+ }\r
+#endif\r
+\r
+/*\r
+ * Utility macro to call macros above in correct order in order to perform a\r
+ * task switch from within a standard ISR. This macro can only be used if\r
+ * the ISR does not use any local (stack) variables. If the ISR uses stack\r
+ * variables portYIELD() should be used in it's place.\r
+ */\r
+#define portTASK_SWITCH_FROM_ISR() \\r
+ portSAVE_CONTEXT(); \\r
+ vTaskSwitchContext(); \\r
+ portRESTORE_CONTEXT();\r
+\r
+\r
+/* Task function macros as described on the FreeRTOS.org WEB site. */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+\r
+#define inline\r
+\r
+#endif /* PORTMACRO_H */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ * Implementation of functions defined in portable.h for the Atmel AT91R40008\r
+ * port.\r
+ *\r
+ * Components that can be compiled to either ARM or THUMB mode are\r
+ * contained in this file. The ISR routines, which can only be compiled\r
+ * to ARM mode are contained in portISR.c.\r
+ *----------------------------------------------------------*/\r
+\r
+/* Standard includes. */\r
+#include <stdlib.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Hardware specific definitions. */\r
+#include "AT91R40008.h"\r
+#include "pio.h"\r
+#include "aic.h"\r
+#include "tc.h"\r
+\r
+/* Constants required to setup the task context. */\r
+#define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */\r
+#define portTHUMB_MODE_BIT ( ( portSTACK_TYPE ) 0x20 )\r
+#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 )\r
+#define portNO_CRITICAL_SECTION_NESTING ( ( portSTACK_TYPE ) 0 )\r
+#define portTICK_PRIORITY_6 ( 6 )\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Setup the timer to generate the tick interrupts. */\r
+static void prvSetupTimerInterrupt( void );\r
+\r
+/* \r
+ * The scheduler can only be started from ARM mode, so \r
+ * vPortISRStartFirstSTask() is defined in portISR.c. \r
+ */\r
+extern void vPortISRStartFirstTask( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* \r
+ * Initialise the stack of a task to look exactly as if a call to \r
+ * portSAVE_CONTEXT had been called.\r
+ *\r
+ * See header file for description. \r
+ */\r
+portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
+{\r
+portSTACK_TYPE *pxOriginalTOS;\r
+\r
+ pxOriginalTOS = pxTopOfStack;\r
+\r
+ /* Setup the initial stack of the task. The stack is set exactly as \r
+ expected by the portRESTORE_CONTEXT() macro. */\r
+\r
+ /* First on the stack is the return address - which in this case is the\r
+ start of the task. The offset is added to make the return address appear\r
+ as it would within an IRQ ISR. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; \r
+ pxTopOfStack--;\r
+\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */\r
+ pxTopOfStack--; \r
+\r
+ /* When the task starts is will expect to find the function parameter in\r
+ R0. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */\r
+ pxTopOfStack--;\r
+\r
+ /* The last thing onto the stack is the status register, which is set for\r
+ system mode, with interrupts enabled. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR;\r
+\r
+ #ifdef THUMB_INTERWORK\r
+ {\r
+ /* We want the task to start in thumb mode. */\r
+ *pxTopOfStack |= portTHUMB_MODE_BIT;\r
+ }\r
+ #endif\r
+\r
+ pxTopOfStack--;\r
+\r
+ /* Some optimisation levels use the stack differently to others. This \r
+ means the interrupt flags cannot always be stored on the stack and will\r
+ instead be stored in a variable, which is then saved as part of the\r
+ tasks context. */\r
+ *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;\r
+\r
+ return pxTopOfStack;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portBASE_TYPE xPortStartScheduler( void )\r
+{\r
+ /* Start the timer that generates the tick ISR. Interrupts are disabled\r
+ here already. */\r
+ prvSetupTimerInterrupt();\r
+\r
+ /* Start the first task. */\r
+ vPortISRStartFirstTask(); \r
+\r
+ /* Should not get here! */\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEndScheduler( void )\r
+{\r
+ /* It is unlikely that the ARM port will require this function as there\r
+ is nothing to return to. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Setup the tick timer to generate the tick interrupts at the required frequency.\r
+ */\r
+static void prvSetupTimerInterrupt( void )\r
+{\r
+volatile unsigned portLONG ulDummy;\r
+\r
+ /* Enable clock to the tick timer... */\r
+ AT91C_BASE_PS->PS_PCER = portTIMER_CLK_ENABLE_BIT;\r
+\r
+ /* Stop the tick timer... */\r
+ portTIMER_REG_BASE_PTR->TC_CCR = TC_CLKDIS;\r
+\r
+ /* Start with tick timer interrupts disabled... */\r
+ portTIMER_REG_BASE_PTR->TC_IDR = 0xFFFFFFFF;\r
+\r
+ /* Clear any pending tick timer interrupts... */\r
+ ulDummy = portTIMER_REG_BASE_PTR->TC_SR;\r
+\r
+ /* Store interrupt handler function address in tick timer vector register...\r
+ The ISR installed depends on whether the preemptive or cooperative\r
+ scheduler is being used. */\r
+ #if configUSE_PREEMPTION == 1\r
+ {\r
+ extern void ( vPreemptiveTick )( void );\r
+ AT91C_BASE_AIC->AIC_SVR[portTIMER_AIC_CHANNEL] = ( unsigned portLONG ) vPreemptiveTick;\r
+ }\r
+ #else // else use cooperative scheduler\r
+ {\r
+ extern void ( vNonPreemptiveTick )( void );\r
+ AT91C_BASE_AIC->AIC_SVR[portTIMER_AIC_CHANNEL] = ( unsigned portLONG ) vNonPreemptiveTick;\r
+ }\r
+ #endif\r
+\r
+ /* Tick timer interrupt level-sensitive, priority 6... */\r
+ AT91C_BASE_AIC->AIC_SMR[ portTIMER_AIC_CHANNEL ] = AIC_SRCTYPE_INT_LEVEL_SENSITIVE | portTICK_PRIORITY_6;\r
+\r
+ /* Enable the tick timer interrupt...\r
+\r
+ First at timer level */\r
+ portTIMER_REG_BASE_PTR->TC_IER = TC_CPCS;\r
+\r
+ /* Then at the AIC level. */\r
+ AT91C_BASE_AIC->AIC_IECR = (1 << portTIMER_AIC_CHANNEL);\r
+\r
+ /* Calculate timer compare value to achieve the desired tick rate... */\r
+ if( (configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 2) ) <= 0xFFFF )\r
+ {\r
+ /* The tick rate is fast enough for us to use the faster timer input\r
+ clock (main clock / 2). */\r
+ portTIMER_REG_BASE_PTR->TC_CMR = TC_WAVE | TC_CLKS_MCK2 | TC_BURST_NONE | TC_CPCTRG;\r
+ portTIMER_REG_BASE_PTR->TC_RC = configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 2);\r
+ }\r
+ else\r
+ {\r
+ /* We must use a slower timer input clock (main clock / 8) because the\r
+ tick rate is too slow for the faster input clock. */\r
+ portTIMER_REG_BASE_PTR->TC_CMR = TC_WAVE | TC_CLKS_MCK8 | TC_BURST_NONE | TC_CPCTRG;\r
+ portTIMER_REG_BASE_PTR->TC_RC = configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 8);\r
+ }\r
+\r
+ /* Start tick timer... */\r
+ portTIMER_REG_BASE_PTR->TC_CCR = TC_SWTRG | TC_CLKEN;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ * Components that can be compiled to either ARM or THUMB mode are\r
+ * contained in port.c The ISR routines, which can only be compiled\r
+ * to ARM mode, are contained in this file.\r
+ *----------------------------------------------------------*/\r
+\r
+/*\r
+ Changes from V3.2.4\r
+\r
+ + The assembler statements are now included in a single asm block rather\r
+ than each line having its own asm block.\r
+*/\r
+\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Constants required to handle interrupts. */\r
+#define portCLEAR_AIC_INTERRUPT ( ( unsigned portLONG ) 0 )\r
+\r
+/* Constants required to handle critical sections. */\r
+#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 )\r
+volatile unsigned portLONG ulCriticalNesting = 9999UL;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* ISR to handle manual context switches (from a call to taskYIELD()). */\r
+void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));\r
+\r
+/* \r
+ * The scheduler can only be started from ARM mode, hence the inclusion of this\r
+ * function here.\r
+ */\r
+void vPortISRStartFirstTask( void );\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortISRStartFirstTask( void )\r
+{\r
+ /* Simply start the scheduler. This is included here as it can only be\r
+ called from ARM mode. */\r
+ portRESTORE_CONTEXT();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Called by portYIELD() or taskYIELD() to manually force a context switch.\r
+ *\r
+ * When a context switch is performed from the task level the saved task \r
+ * context is made to look as if it occurred from within the tick ISR. This\r
+ * way the same restore context function can be used when restoring the context\r
+ * saved from the ISR or that saved from a call to vPortYieldProcessor.\r
+ */\r
+void vPortYieldProcessor( void )\r
+{\r
+ /* Within an IRQ ISR the link register has an offset from the true return \r
+ address, but an SWI ISR does not. Add the offset manually so the same \r
+ ISR return code can be used in both cases. */\r
+ asm volatile ( "ADD LR, LR, #4" );\r
+\r
+ /* Perform the context switch. First save the context of the current task. */\r
+ portSAVE_CONTEXT();\r
+\r
+ /* Find the highest priority task that is ready to run. */\r
+ vTaskSwitchContext();\r
+\r
+ /* Restore the context of the new task. */\r
+ portRESTORE_CONTEXT(); \r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* \r
+ * The ISR used for the scheduler tick depends on whether the cooperative or\r
+ * the preemptive scheduler is being used.\r
+ */\r
+\r
+#if configUSE_PREEMPTION == 0\r
+\r
+ /* The cooperative scheduler requires a normal IRQ service routine to \r
+ simply increment the system tick. */\r
+ void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ")));\r
+ void vNonPreemptiveTick( void )\r
+ { \r
+ static volatile unsigned portLONG ulDummy;\r
+\r
+ /* Clear tick timer interrupt indication. */\r
+ ulDummy = portTIMER_REG_BASE_PTR->TC_SR; \r
+\r
+ vTaskIncrementTick();\r
+\r
+ /* Acknowledge the interrupt at AIC level... */\r
+ AT91C_BASE_AIC->AIC_EOICR = portCLEAR_AIC_INTERRUPT;\r
+ }\r
+\r
+#else /* else preemption is turned on */\r
+\r
+ /* The preemptive scheduler is defined as "naked" as the full context is\r
+ saved on entry as part of the context switch. */\r
+ void vPreemptiveTick( void ) __attribute__((naked));\r
+ void vPreemptiveTick( void )\r
+ {\r
+ /* Save the context of the interrupted task. */\r
+ portSAVE_CONTEXT(); \r
+\r
+ /* WARNING - Do not use local (stack) variables here. Use globals\r
+ if you must! */\r
+ static volatile unsigned portLONG ulDummy;\r
+\r
+ /* Clear tick timer interrupt indication. */\r
+ ulDummy = portTIMER_REG_BASE_PTR->TC_SR; \r
+\r
+ /* Increment the RTOS tick count, then look for the highest priority \r
+ task that is ready to run. */\r
+ vTaskIncrementTick();\r
+ vTaskSwitchContext();\r
+\r
+ /* Acknowledge the interrupt at AIC level... */\r
+ AT91C_BASE_AIC->AIC_EOICR = portCLEAR_AIC_INTERRUPT;\r
+\r
+ /* Restore the context of the new task. */\r
+ portRESTORE_CONTEXT();\r
+ }\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The interrupt management utilities can only be called from ARM mode. When\r
+ * THUMB_INTERWORK is defined the utilities are defined as functions here to\r
+ * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then\r
+ * the utilities are defined as macros in portmacro.h - as per other ports.\r
+ */\r
+#ifdef THUMB_INTERWORK\r
+\r
+ void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));\r
+ void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));\r
+\r
+ void vPortDisableInterruptsFromThumb( void )\r
+ {\r
+ asm volatile ( \r
+ "STMDB SP!, {R0} \n\t" /* Push R0. */\r
+ "MRS R0, CPSR \n\t" /* Get CPSR. */\r
+ "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */\r
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */\r
+ "LDMIA SP!, {R0} \n\t" /* Pop R0. */\r
+ "BX R14" ); /* Return back to thumb. */\r
+ }\r
+ \r
+ void vPortEnableInterruptsFromThumb( void )\r
+ {\r
+ asm volatile ( \r
+ "STMDB SP!, {R0} \n\t" /* Push R0. */ \r
+ "MRS R0, CPSR \n\t" /* Get CPSR. */ \r
+ "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \r
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */ \r
+ "LDMIA SP!, {R0} \n\t" /* Pop R0. */\r
+ "BX R14" ); /* Return back to thumb. */\r
+ }\r
+\r
+#endif /* THUMB_INTERWORK */\r
+\r
+/* The code generated by the GCC compiler uses the stack in different ways at\r
+different optimisation levels. The interrupt flags can therefore not always\r
+be saved to the stack. Instead the critical section nesting level is stored\r
+in a variable, which is then saved as part of the stack context. */\r
+void vPortEnterCritical( void )\r
+{\r
+ /* Disable interrupts as per portDISABLE_INTERRUPTS(); */\r
+ asm volatile ( \r
+ "STMDB SP!, {R0} \n\t" /* Push R0. */\r
+ "MRS R0, CPSR \n\t" /* Get CPSR. */\r
+ "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */\r
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */\r
+ "LDMIA SP!, {R0}" ); /* Pop R0. */\r
+\r
+ /* Now interrupts are disabled ulCriticalNesting can be accessed \r
+ directly. Increment ulCriticalNesting to keep a count of how many times\r
+ portENTER_CRITICAL() has been called. */\r
+ ulCriticalNesting++;\r
+}\r
+\r
+void vPortExitCritical( void )\r
+{\r
+ if( ulCriticalNesting > portNO_CRITICAL_NESTING )\r
+ {\r
+ /* Decrement the nesting count as we are leaving a critical section. */\r
+ ulCriticalNesting--;\r
+\r
+ /* If the nesting level has reached zero then interrupts should be\r
+ re-enabled. */\r
+ if( ulCriticalNesting == portNO_CRITICAL_NESTING )\r
+ {\r
+ /* Enable interrupts as per portEXIT_CRITICAL(). */\r
+ asm volatile ( \r
+ "STMDB SP!, {R0} \n\t" /* Push R0. */ \r
+ "MRS R0, CPSR \n\t" /* Get CPSR. */ \r
+ "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \r
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */ \r
+ "LDMIA SP!, {R0}" ); /* Pop R0. */\r
+ }\r
+ }\r
+}\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+ Changes from V3.2.3\r
+ \r
+ + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1.\r
+\r
+ Changes from V3.2.4\r
+\r
+ + Removed the use of the %0 parameter within the assembler macros and \r
+ replaced them with hard coded registers. This will ensure the\r
+ assembler does not select the link register as the temp register as\r
+ was occasionally happening previously.\r
+\r
+ + The assembler statements are now included in a single asm block rather\r
+ than each line having its own asm block.\r
+*/\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Port specific definitions. \r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the\r
+ * given hardware and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *-----------------------------------------------------------\r
+ */\r
+\r
+/* Type definitions. */\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE double\r
+#define portLONG long\r
+#define portSHORT short\r
+#define portSTACK_TYPE unsigned portLONG\r
+#define portBASE_TYPE long\r
+\r
+#if( configUSE_16_BIT_TICKS == 1 )\r
+ typedef unsigned portSHORT portTickType;\r
+ #define portMAX_DELAY ( portTickType ) 0xffff\r
+#else\r
+ typedef unsigned portLONG portTickType;\r
+ #define portMAX_DELAY ( portTickType ) 0xffffffff\r
+#endif\r
+/*-----------------------------------------------------------*/ \r
+\r
+/* Hardware specifics. */\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) \r
+#define portBYTE_ALIGNMENT 4\r
+#define portYIELD() asm volatile ( "SWI" ); \r
+#define portNOP() asm volatile ( "NOP" );\r
+\r
+/*\r
+ * These define the timer to use for generating the tick interrupt.\r
+ * They are put in this file so they can be shared between "port.c"\r
+ * and "portisr.c".\r
+ */\r
+#define portTIMER_REG_BASE_PTR AT91C_BASE_TC0\r
+#define portTIMER_CLK_ENABLE_BIT AT91C_PS_TC0\r
+#define portTIMER_AIC_CHANNEL ( ( unsigned portLONG ) 4 )\r
+/*-----------------------------------------------------------*/ \r
+\r
+/* Task utilities. */\r
+\r
+/*\r
+ * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR\r
+ * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but\r
+ * are included here for efficiency. An attempt to call one from\r
+ * THUMB mode code will result in a compile time error.\r
+ */\r
+\r
+#define portRESTORE_CONTEXT() \\r
+{ \\r
+extern volatile void * volatile pxCurrentTCB; \\r
+extern volatile unsigned portLONG ulCriticalNesting; \\r
+ \\r
+ /* Set the LR to the task stack. */ \\r
+ asm volatile ( \\r
+ "LDR R0, =pxCurrentTCB \n\t" \\r
+ "LDR R0, [R0] \n\t" \\r
+ "LDR LR, [R0] \n\t" \\r
+ \\r
+ /* The critical nesting depth is the first item on the stack. */ \\r
+ /* Load it into the ulCriticalNesting variable. */ \\r
+ "LDR R0, =ulCriticalNesting \n\t" \\r
+ "LDMFD LR!, {R1} \n\t" \\r
+ "STR R1, [R0] \n\t" \\r
+ \\r
+ /* Get the SPSR from the stack. */ \\r
+ "LDMFD LR!, {R0} \n\t" \\r
+ "MSR SPSR, R0 \n\t" \\r
+ \\r
+ /* Restore all system mode registers for the task. */ \\r
+ "LDMFD LR, {R0-R14}^ \n\t" \\r
+ "NOP \n\t" \\r
+ \\r
+ /* Restore the return address. */ \\r
+ "LDR LR, [LR, #+60] \n\t" \\r
+ \\r
+ /* And return - correcting the offset in the LR to obtain the */ \\r
+ /* correct address. */ \\r
+ "SUBS PC, LR, #4 \n\t" \\r
+ ); \\r
+ ( void ) ulCriticalNesting; \\r
+ ( void ) pxCurrentTCB; \\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#define portSAVE_CONTEXT() \\r
+{ \\r
+extern volatile void * volatile pxCurrentTCB; \\r
+extern volatile unsigned portLONG ulCriticalNesting; \\r
+ \\r
+ /* Push R0 as we are going to use the register. */ \\r
+ asm volatile ( \\r
+ "STMDB SP!, {R0} \n\t" \\r
+ \\r
+ /* Set R0 to point to the task stack pointer. */ \\r
+ "STMDB SP,{SP}^ \n\t" \\r
+ "NOP \n\t" \\r
+ "SUB SP, SP, #4 \n\t" \\r
+ "LDMIA SP!,{R0} \n\t" \\r
+ \\r
+ /* Push the return address onto the stack. */ \\r
+ "STMDB R0!, {LR} \n\t" \\r
+ \\r
+ /* Now we have saved LR we can use it instead of R0. */ \\r
+ "MOV LR, R0 \n\t" \\r
+ \\r
+ /* Pop R0 so we can save it onto the system mode stack. */ \\r
+ "LDMIA SP!, {R0} \n\t" \\r
+ \\r
+ /* Push all the system mode registers onto the task stack. */ \\r
+ "STMDB LR,{R0-LR}^ \n\t" \\r
+ "NOP \n\t" \\r
+ "SUB LR, LR, #60 \n\t" \\r
+ \\r
+ /* Push the SPSR onto the task stack. */ \\r
+ "MRS R0, SPSR \n\t" \\r
+ "STMDB LR!, {R0} \n\t" \\r
+ \\r
+ "LDR R0, =ulCriticalNesting \n\t" \\r
+ "LDR R0, [R0] \n\t" \\r
+ "STMDB LR!, {R0} \n\t" \\r
+ \\r
+ /* Store the new top of stack for the task. */ \\r
+ "LDR R0, =pxCurrentTCB \n\t" \\r
+ "LDR R0, [R0] \n\t" \\r
+ "STR LR, [R0] \n\t" \\r
+ ); \\r
+ ( void ) ulCriticalNesting; \\r
+ ( void ) pxCurrentTCB; \\r
+}\r
+\r
+/*-----------------------------------------------------------\r
+ * ISR entry and exit macros. These are only required if a task switch\r
+ * is required from the ISR.\r
+ *----------------------------------------------------------*/\r
+\r
+#define portENTER_SWITCHING_ISR() \\r
+ /* Save the context of the interrupted task. */ \\r
+ portSAVE_CONTEXT(); \\r
+ \\r
+ /* We don't know the stack requirements for the ISR, so the frame */\\r
+ /* pointer will be set to the top of the task stack, and the stack*/\\r
+ /* pointer left where it is. The IRQ stack will get used for any */\\r
+ /* functions calls made by this ISR. */ \\r
+ asm volatile ( "SUB R11, LR, #4" ); \\r
+ {\r
+\r
+#define portEXIT_SWITCHING_ISR( SwitchRequired ) \\r
+ /* If a switch is required then we just need to call */ \\r
+ /* vTaskSwitchContext() as the context has already been */ \\r
+ /* saved. */ \\r
+ if( SwitchRequired ) \\r
+ { \\r
+ vTaskSwitchContext(); \\r
+ } \\r
+ } \\r
+ /* Restore the context of which ever task is now the highest */ \\r
+ /* priority that is ready to run. */ \\r
+ portRESTORE_CONTEXT();\r
+/*-----------------------------------------------------------*/ \r
+\r
+/* Critical section handling. */\r
+\r
+/*\r
+ * The interrupt management utilities can only be called from ARM mode. When\r
+ * THUMB_INTERWORK is defined the utilities are defined as functions in \r
+ * portISR.c to ensure a switch to ARM mode. When THUMB_INTERWORK is not \r
+ * defined then the utilities are defined as macros here - as per other ports.\r
+ */\r
+\r
+#ifdef THUMB_INTERWORK\r
+\r
+ extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));\r
+ extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));\r
+\r
+ #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb()\r
+ #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb()\r
+ \r
+#else\r
+\r
+ #define portDISABLE_INTERRUPTS() \\r
+ asm volatile ( \\r
+ "STMDB SP!, {R0} \n\t" /* Push R0. */ \\r
+ "MRS R0, CPSR \n\t" /* Get CPSR. */ \\r
+ "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \\r
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */ \\r
+ "LDMIA SP!, {R0} " ) /* Pop R0. */\r
+ \r
+ #define portENABLE_INTERRUPTS() \\r
+ asm volatile ( \\r
+ "STMDB SP!, {R0} \n\t" /* Push R0. */ \\r
+ "MRS R0, CPSR \n\t" /* Get CPSR. */ \\r
+ "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \\r
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */ \\r
+ "LDMIA SP!, {R0} " ) /* Pop R0. */\r
+\r
+#endif /* THUMB_INTERWORK */\r
+\r
+extern void vPortEnterCritical( void );\r
+extern void vPortExitCritical( void );\r
+\r
+#define portENTER_CRITICAL() vPortEnterCritical();\r
+#define portEXIT_CRITICAL() vPortExitCritical();\r
+\r
+/*-----------------------------------------------------------*/ \r
+\r
+/* Task function macros as described on the FreeRTOS.org WEB site. */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+\r
+#endif /* PORTMACRO_H */\r
+\r
--- /dev/null
+// ----------------------------------------------------------------------------\r
+// ATMEL Microcontroller Software Support - ROUSSET -\r
+// ----------------------------------------------------------------------------\r
+// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+// ----------------------------------------------------------------------------\r
+// File Name : AT91SAM7X256.h\r
+// Object : AT91SAM7X256 definitions\r
+// Generated : AT91 SW Application Group 05/20/2005 (16:22:29)\r
+// \r
+// CVS Reference : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005//\r
+// CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005//\r
+// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//\r
+// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005//\r
+// CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005//\r
+// CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//\r
+// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//\r
+// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//\r
+// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005//\r
+// CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004//\r
+// CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004//\r
+// CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004//\r
+// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005//\r
+// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005//\r
+// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//\r
+// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//\r
+// CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//\r
+// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//\r
+// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//\r
+// CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//\r
+// CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005//\r
+// CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005//\r
+// CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//\r
+// CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005//\r
+// CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005//\r
+// ----------------------------------------------------------------------------\r
+\r
+#ifndef AT91SAM7X256_H\r
+#define AT91SAM7X256_H\r
+\r
+typedef volatile unsigned int AT91_REG;// Hardware register definition\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR System Peripherals\r
+// *****************************************************************************\r
+typedef struct _AT91S_SYS {\r
+ AT91_REG AIC_SMR[32]; // Source Mode Register\r
+ AT91_REG AIC_SVR[32]; // Source Vector Register\r
+ AT91_REG AIC_IVR; // IRQ Vector Register\r
+ AT91_REG AIC_FVR; // FIQ Vector Register\r
+ AT91_REG AIC_ISR; // Interrupt Status Register\r
+ AT91_REG AIC_IPR; // Interrupt Pending Register\r
+ AT91_REG AIC_IMR; // Interrupt Mask Register\r
+ AT91_REG AIC_CISR; // Core Interrupt Status Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG AIC_IECR; // Interrupt Enable Command Register\r
+ AT91_REG AIC_IDCR; // Interrupt Disable Command Register\r
+ AT91_REG AIC_ICCR; // Interrupt Clear Command Register\r
+ AT91_REG AIC_ISCR; // Interrupt Set Command Register\r
+ AT91_REG AIC_EOICR; // End of Interrupt Command Register\r
+ AT91_REG AIC_SPU; // Spurious Vector Register\r
+ AT91_REG AIC_DCR; // Debug Control Register (Protect)\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG AIC_FFER; // Fast Forcing Enable Register\r
+ AT91_REG AIC_FFDR; // Fast Forcing Disable Register\r
+ AT91_REG AIC_FFSR; // Fast Forcing Status Register\r
+ AT91_REG Reserved2[45]; // \r
+ AT91_REG DBGU_CR; // Control Register\r
+ AT91_REG DBGU_MR; // Mode Register\r
+ AT91_REG DBGU_IER; // Interrupt Enable Register\r
+ AT91_REG DBGU_IDR; // Interrupt Disable Register\r
+ AT91_REG DBGU_IMR; // Interrupt Mask Register\r
+ AT91_REG DBGU_CSR; // Channel Status Register\r
+ AT91_REG DBGU_RHR; // Receiver Holding Register\r
+ AT91_REG DBGU_THR; // Transmitter Holding Register\r
+ AT91_REG DBGU_BRGR; // Baud Rate Generator Register\r
+ AT91_REG Reserved3[7]; // \r
+ AT91_REG DBGU_CIDR; // Chip ID Register\r
+ AT91_REG DBGU_EXID; // Chip ID Extension Register\r
+ AT91_REG DBGU_FNTR; // Force NTRST Register\r
+ AT91_REG Reserved4[45]; // \r
+ AT91_REG DBGU_RPR; // Receive Pointer Register\r
+ AT91_REG DBGU_RCR; // Receive Counter Register\r
+ AT91_REG DBGU_TPR; // Transmit Pointer Register\r
+ AT91_REG DBGU_TCR; // Transmit Counter Register\r
+ AT91_REG DBGU_RNPR; // Receive Next Pointer Register\r
+ AT91_REG DBGU_RNCR; // Receive Next Counter Register\r
+ AT91_REG DBGU_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG DBGU_TNCR; // Transmit Next Counter Register\r
+ AT91_REG DBGU_PTCR; // PDC Transfer Control Register\r
+ AT91_REG DBGU_PTSR; // PDC Transfer Status Register\r
+ AT91_REG Reserved5[54]; // \r
+ AT91_REG PIOA_PER; // PIO Enable Register\r
+ AT91_REG PIOA_PDR; // PIO Disable Register\r
+ AT91_REG PIOA_PSR; // PIO Status Register\r
+ AT91_REG Reserved6[1]; // \r
+ AT91_REG PIOA_OER; // Output Enable Register\r
+ AT91_REG PIOA_ODR; // Output Disable Registerr\r
+ AT91_REG PIOA_OSR; // Output Status Register\r
+ AT91_REG Reserved7[1]; // \r
+ AT91_REG PIOA_IFER; // Input Filter Enable Register\r
+ AT91_REG PIOA_IFDR; // Input Filter Disable Register\r
+ AT91_REG PIOA_IFSR; // Input Filter Status Register\r
+ AT91_REG Reserved8[1]; // \r
+ AT91_REG PIOA_SODR; // Set Output Data Register\r
+ AT91_REG PIOA_CODR; // Clear Output Data Register\r
+ AT91_REG PIOA_ODSR; // Output Data Status Register\r
+ AT91_REG PIOA_PDSR; // Pin Data Status Register\r
+ AT91_REG PIOA_IER; // Interrupt Enable Register\r
+ AT91_REG PIOA_IDR; // Interrupt Disable Register\r
+ AT91_REG PIOA_IMR; // Interrupt Mask Register\r
+ AT91_REG PIOA_ISR; // Interrupt Status Register\r
+ AT91_REG PIOA_MDER; // Multi-driver Enable Register\r
+ AT91_REG PIOA_MDDR; // Multi-driver Disable Register\r
+ AT91_REG PIOA_MDSR; // Multi-driver Status Register\r
+ AT91_REG Reserved9[1]; // \r
+ AT91_REG PIOA_PPUDR; // Pull-up Disable Register\r
+ AT91_REG PIOA_PPUER; // Pull-up Enable Register\r
+ AT91_REG PIOA_PPUSR; // Pull-up Status Register\r
+ AT91_REG Reserved10[1]; // \r
+ AT91_REG PIOA_ASR; // Select A Register\r
+ AT91_REG PIOA_BSR; // Select B Register\r
+ AT91_REG PIOA_ABSR; // AB Select Status Register\r
+ AT91_REG Reserved11[9]; // \r
+ AT91_REG PIOA_OWER; // Output Write Enable Register\r
+ AT91_REG PIOA_OWDR; // Output Write Disable Register\r
+ AT91_REG PIOA_OWSR; // Output Write Status Register\r
+ AT91_REG Reserved12[85]; // \r
+ AT91_REG PIOB_PER; // PIO Enable Register\r
+ AT91_REG PIOB_PDR; // PIO Disable Register\r
+ AT91_REG PIOB_PSR; // PIO Status Register\r
+ AT91_REG Reserved13[1]; // \r
+ AT91_REG PIOB_OER; // Output Enable Register\r
+ AT91_REG PIOB_ODR; // Output Disable Registerr\r
+ AT91_REG PIOB_OSR; // Output Status Register\r
+ AT91_REG Reserved14[1]; // \r
+ AT91_REG PIOB_IFER; // Input Filter Enable Register\r
+ AT91_REG PIOB_IFDR; // Input Filter Disable Register\r
+ AT91_REG PIOB_IFSR; // Input Filter Status Register\r
+ AT91_REG Reserved15[1]; // \r
+ AT91_REG PIOB_SODR; // Set Output Data Register\r
+ AT91_REG PIOB_CODR; // Clear Output Data Register\r
+ AT91_REG PIOB_ODSR; // Output Data Status Register\r
+ AT91_REG PIOB_PDSR; // Pin Data Status Register\r
+ AT91_REG PIOB_IER; // Interrupt Enable Register\r
+ AT91_REG PIOB_IDR; // Interrupt Disable Register\r
+ AT91_REG PIOB_IMR; // Interrupt Mask Register\r
+ AT91_REG PIOB_ISR; // Interrupt Status Register\r
+ AT91_REG PIOB_MDER; // Multi-driver Enable Register\r
+ AT91_REG PIOB_MDDR; // Multi-driver Disable Register\r
+ AT91_REG PIOB_MDSR; // Multi-driver Status Register\r
+ AT91_REG Reserved16[1]; // \r
+ AT91_REG PIOB_PPUDR; // Pull-up Disable Register\r
+ AT91_REG PIOB_PPUER; // Pull-up Enable Register\r
+ AT91_REG PIOB_PPUSR; // Pull-up Status Register\r
+ AT91_REG Reserved17[1]; // \r
+ AT91_REG PIOB_ASR; // Select A Register\r
+ AT91_REG PIOB_BSR; // Select B Register\r
+ AT91_REG PIOB_ABSR; // AB Select Status Register\r
+ AT91_REG Reserved18[9]; // \r
+ AT91_REG PIOB_OWER; // Output Write Enable Register\r
+ AT91_REG PIOB_OWDR; // Output Write Disable Register\r
+ AT91_REG PIOB_OWSR; // Output Write Status Register\r
+ AT91_REG Reserved19[341]; // \r
+ AT91_REG PMC_SCER; // System Clock Enable Register\r
+ AT91_REG PMC_SCDR; // System Clock Disable Register\r
+ AT91_REG PMC_SCSR; // System Clock Status Register\r
+ AT91_REG Reserved20[1]; // \r
+ AT91_REG PMC_PCER; // Peripheral Clock Enable Register\r
+ AT91_REG PMC_PCDR; // Peripheral Clock Disable Register\r
+ AT91_REG PMC_PCSR; // Peripheral Clock Status Register\r
+ AT91_REG Reserved21[1]; // \r
+ AT91_REG PMC_MOR; // Main Oscillator Register\r
+ AT91_REG PMC_MCFR; // Main Clock Frequency Register\r
+ AT91_REG Reserved22[1]; // \r
+ AT91_REG PMC_PLLR; // PLL Register\r
+ AT91_REG PMC_MCKR; // Master Clock Register\r
+ AT91_REG Reserved23[3]; // \r
+ AT91_REG PMC_PCKR[4]; // Programmable Clock Register\r
+ AT91_REG Reserved24[4]; // \r
+ AT91_REG PMC_IER; // Interrupt Enable Register\r
+ AT91_REG PMC_IDR; // Interrupt Disable Register\r
+ AT91_REG PMC_SR; // Status Register\r
+ AT91_REG PMC_IMR; // Interrupt Mask Register\r
+ AT91_REG Reserved25[36]; // \r
+ AT91_REG RSTC_RCR; // Reset Control Register\r
+ AT91_REG RSTC_RSR; // Reset Status Register\r
+ AT91_REG RSTC_RMR; // Reset Mode Register\r
+ AT91_REG Reserved26[5]; // \r
+ AT91_REG RTTC_RTMR; // Real-time Mode Register\r
+ AT91_REG RTTC_RTAR; // Real-time Alarm Register\r
+ AT91_REG RTTC_RTVR; // Real-time Value Register\r
+ AT91_REG RTTC_RTSR; // Real-time Status Register\r
+ AT91_REG PITC_PIMR; // Period Interval Mode Register\r
+ AT91_REG PITC_PISR; // Period Interval Status Register\r
+ AT91_REG PITC_PIVR; // Period Interval Value Register\r
+ AT91_REG PITC_PIIR; // Period Interval Image Register\r
+ AT91_REG WDTC_WDCR; // Watchdog Control Register\r
+ AT91_REG WDTC_WDMR; // Watchdog Mode Register\r
+ AT91_REG WDTC_WDSR; // Watchdog Status Register\r
+ AT91_REG Reserved27[5]; // \r
+ AT91_REG VREG_MR; // Voltage Regulator Mode Register\r
+} AT91S_SYS, *AT91PS_SYS;\r
+\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller\r
+// *****************************************************************************\r
+typedef struct _AT91S_AIC {\r
+ AT91_REG AIC_SMR[32]; // Source Mode Register\r
+ AT91_REG AIC_SVR[32]; // Source Vector Register\r
+ AT91_REG AIC_IVR; // IRQ Vector Register\r
+ AT91_REG AIC_FVR; // FIQ Vector Register\r
+ AT91_REG AIC_ISR; // Interrupt Status Register\r
+ AT91_REG AIC_IPR; // Interrupt Pending Register\r
+ AT91_REG AIC_IMR; // Interrupt Mask Register\r
+ AT91_REG AIC_CISR; // Core Interrupt Status Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG AIC_IECR; // Interrupt Enable Command Register\r
+ AT91_REG AIC_IDCR; // Interrupt Disable Command Register\r
+ AT91_REG AIC_ICCR; // Interrupt Clear Command Register\r
+ AT91_REG AIC_ISCR; // Interrupt Set Command Register\r
+ AT91_REG AIC_EOICR; // End of Interrupt Command Register\r
+ AT91_REG AIC_SPU; // Spurious Vector Register\r
+ AT91_REG AIC_DCR; // Debug Control Register (Protect)\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG AIC_FFER; // Fast Forcing Enable Register\r
+ AT91_REG AIC_FFDR; // Fast Forcing Disable Register\r
+ AT91_REG AIC_FFSR; // Fast Forcing Status Register\r
+} AT91S_AIC, *AT91PS_AIC;\r
+\r
+// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- \r
+#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level\r
+#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level\r
+#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level\r
+#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type\r
+#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive\r
+#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ((unsigned int) 0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive\r
+#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered\r
+#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered\r
+#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive\r
+#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered\r
+// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- \r
+#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status\r
+#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status\r
+// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- \r
+#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode\r
+#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Peripheral DMA Controller\r
+// *****************************************************************************\r
+typedef struct _AT91S_PDC {\r
+ AT91_REG PDC_RPR; // Receive Pointer Register\r
+ AT91_REG PDC_RCR; // Receive Counter Register\r
+ AT91_REG PDC_TPR; // Transmit Pointer Register\r
+ AT91_REG PDC_TCR; // Transmit Counter Register\r
+ AT91_REG PDC_RNPR; // Receive Next Pointer Register\r
+ AT91_REG PDC_RNCR; // Receive Next Counter Register\r
+ AT91_REG PDC_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG PDC_TNCR; // Transmit Next Counter Register\r
+ AT91_REG PDC_PTCR; // PDC Transfer Control Register\r
+ AT91_REG PDC_PTSR; // PDC Transfer Status Register\r
+} AT91S_PDC, *AT91PS_PDC;\r
+\r
+// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- \r
+#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable\r
+#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable\r
+#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable\r
+#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable\r
+// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Debug Unit\r
+// *****************************************************************************\r
+typedef struct _AT91S_DBGU {\r
+ AT91_REG DBGU_CR; // Control Register\r
+ AT91_REG DBGU_MR; // Mode Register\r
+ AT91_REG DBGU_IER; // Interrupt Enable Register\r
+ AT91_REG DBGU_IDR; // Interrupt Disable Register\r
+ AT91_REG DBGU_IMR; // Interrupt Mask Register\r
+ AT91_REG DBGU_CSR; // Channel Status Register\r
+ AT91_REG DBGU_RHR; // Receiver Holding Register\r
+ AT91_REG DBGU_THR; // Transmitter Holding Register\r
+ AT91_REG DBGU_BRGR; // Baud Rate Generator Register\r
+ AT91_REG Reserved0[7]; // \r
+ AT91_REG DBGU_CIDR; // Chip ID Register\r
+ AT91_REG DBGU_EXID; // Chip ID Extension Register\r
+ AT91_REG DBGU_FNTR; // Force NTRST Register\r
+ AT91_REG Reserved1[45]; // \r
+ AT91_REG DBGU_RPR; // Receive Pointer Register\r
+ AT91_REG DBGU_RCR; // Receive Counter Register\r
+ AT91_REG DBGU_TPR; // Transmit Pointer Register\r
+ AT91_REG DBGU_TCR; // Transmit Counter Register\r
+ AT91_REG DBGU_RNPR; // Receive Next Pointer Register\r
+ AT91_REG DBGU_RNCR; // Receive Next Counter Register\r
+ AT91_REG DBGU_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG DBGU_TNCR; // Transmit Next Counter Register\r
+ AT91_REG DBGU_PTCR; // PDC Transfer Control Register\r
+ AT91_REG DBGU_PTSR; // PDC Transfer Status Register\r
+} AT91S_DBGU, *AT91PS_DBGU;\r
+\r
+// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- \r
+#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver\r
+#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter\r
+#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable\r
+#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable\r
+#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable\r
+#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable\r
+#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits\r
+// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- \r
+#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type\r
+#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity\r
+#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity\r
+#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space)\r
+#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark)\r
+#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity\r
+#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode\r
+#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode\r
+#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.\r
+#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.\r
+#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.\r
+#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.\r
+// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- \r
+#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt\r
+#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt\r
+#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt\r
+#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt\r
+#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt\r
+#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt\r
+#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt\r
+#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt\r
+#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt\r
+#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt\r
+#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt\r
+#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt\r
+// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- \r
+// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- \r
+// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- \r
+// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- \r
+#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Parallel Input Output Controler\r
+// *****************************************************************************\r
+typedef struct _AT91S_PIO {\r
+ AT91_REG PIO_PER; // PIO Enable Register\r
+ AT91_REG PIO_PDR; // PIO Disable Register\r
+ AT91_REG PIO_PSR; // PIO Status Register\r
+ AT91_REG Reserved0[1]; // \r
+ AT91_REG PIO_OER; // Output Enable Register\r
+ AT91_REG PIO_ODR; // Output Disable Registerr\r
+ AT91_REG PIO_OSR; // Output Status Register\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG PIO_IFER; // Input Filter Enable Register\r
+ AT91_REG PIO_IFDR; // Input Filter Disable Register\r
+ AT91_REG PIO_IFSR; // Input Filter Status Register\r
+ AT91_REG Reserved2[1]; // \r
+ AT91_REG PIO_SODR; // Set Output Data Register\r
+ AT91_REG PIO_CODR; // Clear Output Data Register\r
+ AT91_REG PIO_ODSR; // Output Data Status Register\r
+ AT91_REG PIO_PDSR; // Pin Data Status Register\r
+ AT91_REG PIO_IER; // Interrupt Enable Register\r
+ AT91_REG PIO_IDR; // Interrupt Disable Register\r
+ AT91_REG PIO_IMR; // Interrupt Mask Register\r
+ AT91_REG PIO_ISR; // Interrupt Status Register\r
+ AT91_REG PIO_MDER; // Multi-driver Enable Register\r
+ AT91_REG PIO_MDDR; // Multi-driver Disable Register\r
+ AT91_REG PIO_MDSR; // Multi-driver Status Register\r
+ AT91_REG Reserved3[1]; // \r
+ AT91_REG PIO_PPUDR; // Pull-up Disable Register\r
+ AT91_REG PIO_PPUER; // Pull-up Enable Register\r
+ AT91_REG PIO_PPUSR; // Pull-up Status Register\r
+ AT91_REG Reserved4[1]; // \r
+ AT91_REG PIO_ASR; // Select A Register\r
+ AT91_REG PIO_BSR; // Select B Register\r
+ AT91_REG PIO_ABSR; // AB Select Status Register\r
+ AT91_REG Reserved5[9]; // \r
+ AT91_REG PIO_OWER; // Output Write Enable Register\r
+ AT91_REG PIO_OWDR; // Output Write Disable Register\r
+ AT91_REG PIO_OWSR; // Output Write Status Register\r
+} AT91S_PIO, *AT91PS_PIO;\r
+\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Clock Generator Controler\r
+// *****************************************************************************\r
+typedef struct _AT91S_CKGR {\r
+ AT91_REG CKGR_MOR; // Main Oscillator Register\r
+ AT91_REG CKGR_MCFR; // Main Clock Frequency Register\r
+ AT91_REG Reserved0[1]; // \r
+ AT91_REG CKGR_PLLR; // PLL Register\r
+} AT91S_CKGR, *AT91PS_CKGR;\r
+\r
+// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- \r
+#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable\r
+#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass\r
+#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time\r
+// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- \r
+#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency\r
+#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready\r
+// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- \r
+#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected\r
+#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0\r
+#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed\r
+#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter\r
+#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range\r
+#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet\r
+#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet\r
+#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet\r
+#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet\r
+#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier\r
+#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks\r
+#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output\r
+#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2\r
+#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Power Management Controler\r
+// *****************************************************************************\r
+typedef struct _AT91S_PMC {\r
+ AT91_REG PMC_SCER; // System Clock Enable Register\r
+ AT91_REG PMC_SCDR; // System Clock Disable Register\r
+ AT91_REG PMC_SCSR; // System Clock Status Register\r
+ AT91_REG Reserved0[1]; // \r
+ AT91_REG PMC_PCER; // Peripheral Clock Enable Register\r
+ AT91_REG PMC_PCDR; // Peripheral Clock Disable Register\r
+ AT91_REG PMC_PCSR; // Peripheral Clock Status Register\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG PMC_MOR; // Main Oscillator Register\r
+ AT91_REG PMC_MCFR; // Main Clock Frequency Register\r
+ AT91_REG Reserved2[1]; // \r
+ AT91_REG PMC_PLLR; // PLL Register\r
+ AT91_REG PMC_MCKR; // Master Clock Register\r
+ AT91_REG Reserved3[3]; // \r
+ AT91_REG PMC_PCKR[4]; // Programmable Clock Register\r
+ AT91_REG Reserved4[4]; // \r
+ AT91_REG PMC_IER; // Interrupt Enable Register\r
+ AT91_REG PMC_IDR; // Interrupt Disable Register\r
+ AT91_REG PMC_SR; // Status Register\r
+ AT91_REG PMC_IMR; // Interrupt Mask Register\r
+} AT91S_PMC, *AT91PS_PMC;\r
+\r
+// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- \r
+#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock\r
+#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock\r
+#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output\r
+#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output\r
+#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output\r
+#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output\r
+// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- \r
+// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- \r
+// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- \r
+// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- \r
+// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- \r
+// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- \r
+#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection\r
+#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected\r
+#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected\r
+#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected\r
+#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler\r
+#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock\r
+#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2\r
+#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4\r
+#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8\r
+#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16\r
+#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32\r
+#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64\r
+// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- \r
+// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- \r
+#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask\r
+#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask\r
+#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask\r
+// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- \r
+// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- \r
+// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Reset Controller Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_RSTC {\r
+ AT91_REG RSTC_RCR; // Reset Control Register\r
+ AT91_REG RSTC_RSR; // Reset Status Register\r
+ AT91_REG RSTC_RMR; // Reset Mode Register\r
+} AT91S_RSTC, *AT91PS_RSTC;\r
+\r
+// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- \r
+#define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset\r
+#define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset\r
+#define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset\r
+#define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password\r
+// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- \r
+#define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status\r
+#define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status\r
+#define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type\r
+#define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising.\r
+#define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising.\r
+#define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.\r
+#define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.\r
+#define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low.\r
+#define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured.\r
+#define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level\r
+#define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress.\r
+// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- \r
+#define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable\r
+#define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable\r
+#define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable\r
+#define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_RTTC {\r
+ AT91_REG RTTC_RTMR; // Real-time Mode Register\r
+ AT91_REG RTTC_RTAR; // Real-time Alarm Register\r
+ AT91_REG RTTC_RTVR; // Real-time Value Register\r
+ AT91_REG RTTC_RTSR; // Real-time Status Register\r
+} AT91S_RTTC, *AT91PS_RTTC;\r
+\r
+// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- \r
+#define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value\r
+#define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable\r
+#define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable\r
+#define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart\r
+// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- \r
+#define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value\r
+// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- \r
+#define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value\r
+// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- \r
+#define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status\r
+#define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_PITC {\r
+ AT91_REG PITC_PIMR; // Period Interval Mode Register\r
+ AT91_REG PITC_PISR; // Period Interval Status Register\r
+ AT91_REG PITC_PIVR; // Period Interval Value Register\r
+ AT91_REG PITC_PIIR; // Period Interval Image Register\r
+} AT91S_PITC, *AT91PS_PITC;\r
+\r
+// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- \r
+#define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value\r
+#define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled\r
+#define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable\r
+// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- \r
+#define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status\r
+// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- \r
+#define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value\r
+#define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter\r
+// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_WDTC {\r
+ AT91_REG WDTC_WDCR; // Watchdog Control Register\r
+ AT91_REG WDTC_WDMR; // Watchdog Mode Register\r
+ AT91_REG WDTC_WDSR; // Watchdog Status Register\r
+} AT91S_WDTC, *AT91PS_WDTC;\r
+\r
+// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- \r
+#define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart\r
+#define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password\r
+// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- \r
+#define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart\r
+#define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable\r
+#define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable\r
+#define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart\r
+#define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable\r
+#define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value\r
+#define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt\r
+#define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt\r
+// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- \r
+#define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow\r
+#define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_VREG {\r
+ AT91_REG VREG_MR; // Voltage Regulator Mode Register\r
+} AT91S_VREG, *AT91PS_VREG;\r
+\r
+// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- \r
+#define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Memory Controller Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_MC {\r
+ AT91_REG MC_RCR; // MC Remap Control Register\r
+ AT91_REG MC_ASR; // MC Abort Status Register\r
+ AT91_REG MC_AASR; // MC Abort Address Status Register\r
+ AT91_REG Reserved0[21]; // \r
+ AT91_REG MC_FMR; // MC Flash Mode Register\r
+ AT91_REG MC_FCR; // MC Flash Command Register\r
+ AT91_REG MC_FSR; // MC Flash Status Register\r
+} AT91S_MC, *AT91PS_MC;\r
+\r
+// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- \r
+#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit\r
+// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- \r
+#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status\r
+#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status\r
+#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status\r
+#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte\r
+#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word\r
+#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word\r
+#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status\r
+#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read\r
+#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write\r
+#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch\r
+#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source\r
+#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source\r
+#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source\r
+#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source\r
+// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- \r
+#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready\r
+#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error\r
+#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error\r
+#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming\r
+#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State\r
+#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations\r
+#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations\r
+#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations\r
+#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations\r
+#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number\r
+// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- \r
+#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command\r
+#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN.\r
+#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.\r
+#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.\r
+#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.\r
+#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.\r
+#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits.\r
+#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits.\r
+#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit.\r
+#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number\r
+#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key\r
+// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- \r
+#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status\r
+#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status\r
+#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status\r
+#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status\r
+#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status\r
+#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status\r
+#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status\r
+#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status\r
+#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status\r
+#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status\r
+#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status\r
+#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status\r
+#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status\r
+#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status\r
+#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status\r
+#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status\r
+#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status\r
+#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status\r
+#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status\r
+#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status\r
+#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status\r
+#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status\r
+#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status\r
+#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status\r
+#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Serial Parallel Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_SPI {\r
+ AT91_REG SPI_CR; // Control Register\r
+ AT91_REG SPI_MR; // Mode Register\r
+ AT91_REG SPI_RDR; // Receive Data Register\r
+ AT91_REG SPI_TDR; // Transmit Data Register\r
+ AT91_REG SPI_SR; // Status Register\r
+ AT91_REG SPI_IER; // Interrupt Enable Register\r
+ AT91_REG SPI_IDR; // Interrupt Disable Register\r
+ AT91_REG SPI_IMR; // Interrupt Mask Register\r
+ AT91_REG Reserved0[4]; // \r
+ AT91_REG SPI_CSR[4]; // Chip Select Register\r
+ AT91_REG Reserved1[48]; // \r
+ AT91_REG SPI_RPR; // Receive Pointer Register\r
+ AT91_REG SPI_RCR; // Receive Counter Register\r
+ AT91_REG SPI_TPR; // Transmit Pointer Register\r
+ AT91_REG SPI_TCR; // Transmit Counter Register\r
+ AT91_REG SPI_RNPR; // Receive Next Pointer Register\r
+ AT91_REG SPI_RNCR; // Receive Next Counter Register\r
+ AT91_REG SPI_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG SPI_TNCR; // Transmit Next Counter Register\r
+ AT91_REG SPI_PTCR; // PDC Transfer Control Register\r
+ AT91_REG SPI_PTSR; // PDC Transfer Status Register\r
+} AT91S_SPI, *AT91PS_SPI;\r
+\r
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- \r
+#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable\r
+#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable\r
+#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset\r
+#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer\r
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- \r
+#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode\r
+#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select\r
+#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select\r
+#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select\r
+#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode\r
+#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection\r
+#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection\r
+#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection\r
+#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select\r
+#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects\r
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- \r
+#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data\r
+#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status\r
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- \r
+#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data\r
+#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status\r
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- \r
+#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full\r
+#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty\r
+#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error\r
+#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status\r
+#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer\r
+#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer\r
+#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt\r
+#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt\r
+#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt\r
+#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt\r
+#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status\r
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- \r
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- \r
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- \r
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- \r
+#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity\r
+#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase\r
+#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer\r
+#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer\r
+#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer\r
+#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer\r
+#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer\r
+#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer\r
+#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer\r
+#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer\r
+#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer\r
+#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer\r
+#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer\r
+#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate\r
+#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK\r
+#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Usart\r
+// *****************************************************************************\r
+typedef struct _AT91S_USART {\r
+ AT91_REG US_CR; // Control Register\r
+ AT91_REG US_MR; // Mode Register\r
+ AT91_REG US_IER; // Interrupt Enable Register\r
+ AT91_REG US_IDR; // Interrupt Disable Register\r
+ AT91_REG US_IMR; // Interrupt Mask Register\r
+ AT91_REG US_CSR; // Channel Status Register\r
+ AT91_REG US_RHR; // Receiver Holding Register\r
+ AT91_REG US_THR; // Transmitter Holding Register\r
+ AT91_REG US_BRGR; // Baud Rate Generator Register\r
+ AT91_REG US_RTOR; // Receiver Time-out Register\r
+ AT91_REG US_TTGR; // Transmitter Time-guard Register\r
+ AT91_REG Reserved0[5]; // \r
+ AT91_REG US_FIDI; // FI_DI_Ratio Register\r
+ AT91_REG US_NER; // Nb Errors Register\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG US_IF; // IRDA_FILTER Register\r
+ AT91_REG Reserved2[44]; // \r
+ AT91_REG US_RPR; // Receive Pointer Register\r
+ AT91_REG US_RCR; // Receive Counter Register\r
+ AT91_REG US_TPR; // Transmit Pointer Register\r
+ AT91_REG US_TCR; // Transmit Counter Register\r
+ AT91_REG US_RNPR; // Receive Next Pointer Register\r
+ AT91_REG US_RNCR; // Receive Next Counter Register\r
+ AT91_REG US_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG US_TNCR; // Transmit Next Counter Register\r
+ AT91_REG US_PTCR; // PDC Transfer Control Register\r
+ AT91_REG US_PTSR; // PDC Transfer Status Register\r
+} AT91S_USART, *AT91PS_USART;\r
+\r
+// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- \r
+#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break\r
+#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break\r
+#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out\r
+#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address\r
+#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations\r
+#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge\r
+#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out\r
+#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable\r
+#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable\r
+#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable\r
+#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable\r
+// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- \r
+#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode\r
+#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal\r
+#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485\r
+#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking\r
+#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem\r
+#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0\r
+#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1\r
+#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA\r
+#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking\r
+#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock\r
+#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock\r
+#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1\r
+#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM)\r
+#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK)\r
+#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock\r
+#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits\r
+#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits\r
+#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits\r
+#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits\r
+#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select\r
+#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits\r
+#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit\r
+#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits\r
+#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits\r
+#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order\r
+#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length\r
+#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select\r
+#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode\r
+#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge\r
+#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK\r
+#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions\r
+#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter\r
+// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- \r
+#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break\r
+#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out\r
+#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached\r
+#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge\r
+#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag\r
+#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag\r
+#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag\r
+#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag\r
+// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- \r
+// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- \r
+// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- \r
+#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input\r
+#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input\r
+#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input\r
+#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_SSC {\r
+ AT91_REG SSC_CR; // Control Register\r
+ AT91_REG SSC_CMR; // Clock Mode Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG SSC_RCMR; // Receive Clock ModeRegister\r
+ AT91_REG SSC_RFMR; // Receive Frame Mode Register\r
+ AT91_REG SSC_TCMR; // Transmit Clock Mode Register\r
+ AT91_REG SSC_TFMR; // Transmit Frame Mode Register\r
+ AT91_REG SSC_RHR; // Receive Holding Register\r
+ AT91_REG SSC_THR; // Transmit Holding Register\r
+ AT91_REG Reserved1[2]; // \r
+ AT91_REG SSC_RSHR; // Receive Sync Holding Register\r
+ AT91_REG SSC_TSHR; // Transmit Sync Holding Register\r
+ AT91_REG Reserved2[2]; // \r
+ AT91_REG SSC_SR; // Status Register\r
+ AT91_REG SSC_IER; // Interrupt Enable Register\r
+ AT91_REG SSC_IDR; // Interrupt Disable Register\r
+ AT91_REG SSC_IMR; // Interrupt Mask Register\r
+ AT91_REG Reserved3[44]; // \r
+ AT91_REG SSC_RPR; // Receive Pointer Register\r
+ AT91_REG SSC_RCR; // Receive Counter Register\r
+ AT91_REG SSC_TPR; // Transmit Pointer Register\r
+ AT91_REG SSC_TCR; // Transmit Counter Register\r
+ AT91_REG SSC_RNPR; // Receive Next Pointer Register\r
+ AT91_REG SSC_RNCR; // Receive Next Counter Register\r
+ AT91_REG SSC_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG SSC_TNCR; // Transmit Next Counter Register\r
+ AT91_REG SSC_PTCR; // PDC Transfer Control Register\r
+ AT91_REG SSC_PTSR; // PDC Transfer Status Register\r
+} AT91S_SSC, *AT91PS_SSC;\r
+\r
+// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- \r
+#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable\r
+#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable\r
+#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable\r
+#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable\r
+#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset\r
+// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- \r
+#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection\r
+#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock\r
+#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal\r
+#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin\r
+#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection\r
+#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only\r
+#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output\r
+#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output\r
+#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion\r
+#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection\r
+#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.\r
+#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start\r
+#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input\r
+#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input\r
+#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input\r
+#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input\r
+#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input\r
+#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input\r
+#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0\r
+#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay\r
+#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection\r
+// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- \r
+#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length\r
+#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode\r
+#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First\r
+#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame\r
+#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length\r
+#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection\r
+#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only\r
+#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse\r
+#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse\r
+#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer\r
+#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer\r
+#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer\r
+#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection\r
+// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- \r
+// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- \r
+#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value\r
+#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable\r
+// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- \r
+#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready\r
+#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty\r
+#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission\r
+#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty\r
+#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready\r
+#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun\r
+#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception\r
+#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full\r
+#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync\r
+#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync\r
+#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable\r
+#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable\r
+// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- \r
+// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- \r
+// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Two-wire Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_TWI {\r
+ AT91_REG TWI_CR; // Control Register\r
+ AT91_REG TWI_MMR; // Master Mode Register\r
+ AT91_REG Reserved0[1]; // \r
+ AT91_REG TWI_IADR; // Internal Address Register\r
+ AT91_REG TWI_CWGR; // Clock Waveform Generator Register\r
+ AT91_REG Reserved1[3]; // \r
+ AT91_REG TWI_SR; // Status Register\r
+ AT91_REG TWI_IER; // Interrupt Enable Register\r
+ AT91_REG TWI_IDR; // Interrupt Disable Register\r
+ AT91_REG TWI_IMR; // Interrupt Mask Register\r
+ AT91_REG TWI_RHR; // Receive Holding Register\r
+ AT91_REG TWI_THR; // Transmit Holding Register\r
+} AT91S_TWI, *AT91PS_TWI;\r
+\r
+// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- \r
+#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition\r
+#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition\r
+#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled\r
+#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled\r
+#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset\r
+// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- \r
+#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size\r
+#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address\r
+#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address\r
+#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address\r
+#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address\r
+#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction\r
+#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address\r
+// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- \r
+#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider\r
+#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider\r
+#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider\r
+// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- \r
+#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed\r
+#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY\r
+#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY\r
+#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error\r
+#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error\r
+#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged\r
+// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- \r
+// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- \r
+// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR PWMC Channel Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_PWMC_CH {\r
+ AT91_REG PWMC_CMR; // Channel Mode Register\r
+ AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register\r
+ AT91_REG PWMC_CPRDR; // Channel Period Register\r
+ AT91_REG PWMC_CCNTR; // Channel Counter Register\r
+ AT91_REG PWMC_CUPDR; // Channel Update Register\r
+ AT91_REG PWMC_Reserved[3]; // Reserved\r
+} AT91S_PWMC_CH, *AT91PS_PWMC_CH;\r
+\r
+// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- \r
+#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx\r
+#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH) \r
+#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH) \r
+#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH) \r
+#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment\r
+#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity\r
+#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period\r
+// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- \r
+#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle\r
+// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- \r
+#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period\r
+// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- \r
+#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter\r
+// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- \r
+#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_PWMC {\r
+ AT91_REG PWMC_MR; // PWMC Mode Register\r
+ AT91_REG PWMC_ENA; // PWMC Enable Register\r
+ AT91_REG PWMC_DIS; // PWMC Disable Register\r
+ AT91_REG PWMC_SR; // PWMC Status Register\r
+ AT91_REG PWMC_IER; // PWMC Interrupt Enable Register\r
+ AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register\r
+ AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register\r
+ AT91_REG PWMC_ISR; // PWMC Interrupt Status Register\r
+ AT91_REG Reserved0[55]; // \r
+ AT91_REG PWMC_VR; // PWMC Version Register\r
+ AT91_REG Reserved1[64]; // \r
+ AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel\r
+} AT91S_PWMC, *AT91PS_PWMC;\r
+\r
+// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- \r
+#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor.\r
+#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A\r
+#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC) \r
+#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor.\r
+#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B\r
+#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC) \r
+// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- \r
+#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0\r
+#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1\r
+#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2\r
+#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3\r
+// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- \r
+// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- \r
+// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- \r
+// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- \r
+// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- \r
+// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR USB Device Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_UDP {\r
+ AT91_REG UDP_NUM; // Frame Number Register\r
+ AT91_REG UDP_GLBSTATE; // Global State Register\r
+ AT91_REG UDP_FADDR; // Function Address Register\r
+ AT91_REG Reserved0[1]; // \r
+ AT91_REG UDP_IER; // Interrupt Enable Register\r
+ AT91_REG UDP_IDR; // Interrupt Disable Register\r
+ AT91_REG UDP_IMR; // Interrupt Mask Register\r
+ AT91_REG UDP_ISR; // Interrupt Status Register\r
+ AT91_REG UDP_ICR; // Interrupt Clear Register\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG UDP_RSTEP; // Reset Endpoint Register\r
+ AT91_REG Reserved2[1]; // \r
+ AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register\r
+ AT91_REG Reserved3[2]; // \r
+ AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register\r
+ AT91_REG Reserved4[3]; // \r
+ AT91_REG UDP_TXVC; // Transceiver Control Register\r
+} AT91S_UDP, *AT91PS_UDP;\r
+\r
+// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- \r
+#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats\r
+#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error\r
+#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK\r
+// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- \r
+#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable\r
+#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured\r
+#define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume\r
+#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host\r
+#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable\r
+// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- \r
+#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value\r
+#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable\r
+// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- \r
+#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt\r
+#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt\r
+#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt\r
+#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt\r
+#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt\r
+#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt\r
+#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt\r
+#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt\r
+#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt\r
+#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt\r
+#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt\r
+// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- \r
+// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- \r
+// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- \r
+#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt\r
+// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- \r
+// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- \r
+#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0\r
+#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1\r
+#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2\r
+#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3\r
+#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4\r
+#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5\r
+// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- \r
+#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR\r
+#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0\r
+#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)\r
+#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)\r
+#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready\r
+#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).\r
+#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).\r
+#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction\r
+#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type\r
+#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control\r
+#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT\r
+#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT\r
+#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT\r
+#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN\r
+#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN\r
+#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN\r
+#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle\r
+#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable\r
+#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO\r
+// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- \r
+#define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP) \r
+#define AT91C_UDP_PUON ((unsigned int) 0x1 << 9) // (UDP) Pull-up ON\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_TC {\r
+ AT91_REG TC_CCR; // Channel Control Register\r
+ AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode)\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG TC_CV; // Counter Value\r
+ AT91_REG TC_RA; // Register A\r
+ AT91_REG TC_RB; // Register B\r
+ AT91_REG TC_RC; // Register C\r
+ AT91_REG TC_SR; // Status Register\r
+ AT91_REG TC_IER; // Interrupt Enable Register\r
+ AT91_REG TC_IDR; // Interrupt Disable Register\r
+ AT91_REG TC_IMR; // Interrupt Mask Register\r
+} AT91S_TC, *AT91PS_TC;\r
+\r
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- \r
+#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command\r
+#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command\r
+#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command\r
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- \r
+#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection\r
+#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK\r
+#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK\r
+#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK\r
+#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK\r
+#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK\r
+#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0\r
+#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1\r
+#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2\r
+#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert\r
+#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection\r
+#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal\r
+#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock\r
+#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock\r
+#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock\r
+#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare\r
+#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading\r
+#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare\r
+#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading\r
+#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection\r
+#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None\r
+#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge\r
+#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge\r
+#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge\r
+#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection\r
+#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None\r
+#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge\r
+#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge\r
+#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge\r
+#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection\r
+#define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input\r
+#define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output\r
+#define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output\r
+#define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output\r
+#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection\r
+#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable\r
+#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection\r
+#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare\r
+#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare\r
+#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare\r
+#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare\r
+#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable\r
+#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) \r
+#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA\r
+#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none\r
+#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set\r
+#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear\r
+#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle\r
+#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection\r
+#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None\r
+#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA\r
+#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA\r
+#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA\r
+#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA\r
+#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none\r
+#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set\r
+#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear\r
+#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle\r
+#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection\r
+#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None\r
+#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA\r
+#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA\r
+#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA\r
+#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA\r
+#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none\r
+#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set\r
+#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear\r
+#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle\r
+#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA\r
+#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none\r
+#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set\r
+#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear\r
+#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle\r
+#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB\r
+#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none\r
+#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set\r
+#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear\r
+#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle\r
+#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB\r
+#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none\r
+#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set\r
+#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear\r
+#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle\r
+#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB\r
+#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none\r
+#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set\r
+#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear\r
+#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle\r
+#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB\r
+#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none\r
+#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set\r
+#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear\r
+#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle\r
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- \r
+#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow\r
+#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun\r
+#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare\r
+#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare\r
+#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare\r
+#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading\r
+#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading\r
+#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger\r
+#define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling\r
+#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror\r
+#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror\r
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- \r
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- \r
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Timer Counter Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_TCB {\r
+ AT91S_TC TCB_TC0; // TC Channel 0\r
+ AT91_REG Reserved0[4]; // \r
+ AT91S_TC TCB_TC1; // TC Channel 1\r
+ AT91_REG Reserved1[4]; // \r
+ AT91S_TC TCB_TC2; // TC Channel 2\r
+ AT91_REG Reserved2[4]; // \r
+ AT91_REG TCB_BCR; // TC Block Control Register\r
+ AT91_REG TCB_BMR; // TC Block Mode Register\r
+} AT91S_TCB, *AT91PS_TCB;\r
+\r
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- \r
+#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command\r
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- \r
+#define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection\r
+#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0\r
+#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0\r
+#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0\r
+#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0\r
+#define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection\r
+#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1\r
+#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1\r
+#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1\r
+#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1\r
+#define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection\r
+#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2\r
+#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2\r
+#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2\r
+#define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_CAN_MB {\r
+ AT91_REG CAN_MB_MMR; // MailBox Mode Register\r
+ AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register\r
+ AT91_REG CAN_MB_MID; // MailBox ID Register\r
+ AT91_REG CAN_MB_MFID; // MailBox Family ID Register\r
+ AT91_REG CAN_MB_MSR; // MailBox Status Register\r
+ AT91_REG CAN_MB_MDL; // MailBox Data Low Register\r
+ AT91_REG CAN_MB_MDH; // MailBox Data High Register\r
+ AT91_REG CAN_MB_MCR; // MailBox Control Register\r
+} AT91S_CAN_MB, *AT91PS_CAN_MB;\r
+\r
+// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- \r
+#define AT91C_CAN_MTIMEMARK ((unsigned int) 0xFFFF << 0) // (CAN_MB) Mailbox Timemark\r
+#define AT91C_CAN_PRIOR ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority\r
+#define AT91C_CAN_MOT ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type\r
+#define AT91C_CAN_MOT_DIS ((unsigned int) 0x0 << 24) // (CAN_MB) \r
+#define AT91C_CAN_MOT_RX ((unsigned int) 0x1 << 24) // (CAN_MB) \r
+#define AT91C_CAN_MOT_RXOVERWRITE ((unsigned int) 0x2 << 24) // (CAN_MB) \r
+#define AT91C_CAN_MOT_TX ((unsigned int) 0x3 << 24) // (CAN_MB) \r
+#define AT91C_CAN_MOT_CONSUMER ((unsigned int) 0x4 << 24) // (CAN_MB) \r
+#define AT91C_CAN_MOT_PRODUCER ((unsigned int) 0x5 << 24) // (CAN_MB) \r
+// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- \r
+#define AT91C_CAN_MIDvB ((unsigned int) 0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode\r
+#define AT91C_CAN_MIDvA ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode\r
+#define AT91C_CAN_MIDE ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version\r
+// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- \r
+// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- \r
+// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- \r
+#define AT91C_CAN_MTIMESTAMP ((unsigned int) 0xFFFF << 0) // (CAN_MB) Timer Value\r
+#define AT91C_CAN_MDLC ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code\r
+#define AT91C_CAN_MRTR ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request\r
+#define AT91C_CAN_MABT ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort\r
+#define AT91C_CAN_MRDY ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready\r
+#define AT91C_CAN_MMI ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored\r
+// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- \r
+// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- \r
+// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- \r
+#define AT91C_CAN_MACR ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox\r
+#define AT91C_CAN_MTCR ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Control Area Network Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_CAN {\r
+ AT91_REG CAN_MR; // Mode Register\r
+ AT91_REG CAN_IER; // Interrupt Enable Register\r
+ AT91_REG CAN_IDR; // Interrupt Disable Register\r
+ AT91_REG CAN_IMR; // Interrupt Mask Register\r
+ AT91_REG CAN_SR; // Status Register\r
+ AT91_REG CAN_BR; // Baudrate Register\r
+ AT91_REG CAN_TIM; // Timer Register\r
+ AT91_REG CAN_TIMESTP; // Time Stamp Register\r
+ AT91_REG CAN_ECR; // Error Counter Register\r
+ AT91_REG CAN_TCR; // Transfer Command Register\r
+ AT91_REG CAN_ACR; // Abort Command Register\r
+ AT91_REG Reserved0[52]; // \r
+ AT91_REG CAN_VR; // Version Register\r
+ AT91_REG Reserved1[64]; // \r
+ AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0\r
+ AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1\r
+ AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2\r
+ AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3\r
+ AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4\r
+ AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5\r
+ AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6\r
+ AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7\r
+ AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8\r
+ AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9\r
+ AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10\r
+ AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11\r
+ AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12\r
+ AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13\r
+ AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14\r
+ AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15\r
+} AT91S_CAN, *AT91PS_CAN;\r
+\r
+// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- \r
+#define AT91C_CAN_CANEN ((unsigned int) 0x1 << 0) // (CAN) CAN Controller Enable\r
+#define AT91C_CAN_LPM ((unsigned int) 0x1 << 1) // (CAN) Disable/Enable Low Power Mode\r
+#define AT91C_CAN_ABM ((unsigned int) 0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode\r
+#define AT91C_CAN_OVL ((unsigned int) 0x1 << 3) // (CAN) Disable/Enable Overload Frame\r
+#define AT91C_CAN_TEOF ((unsigned int) 0x1 << 4) // (CAN) Time Stamp messages at each end of Frame\r
+#define AT91C_CAN_TTM ((unsigned int) 0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode\r
+#define AT91C_CAN_TIMFRZ ((unsigned int) 0x1 << 6) // (CAN) Enable Timer Freeze\r
+#define AT91C_CAN_DRPT ((unsigned int) 0x1 << 7) // (CAN) Disable Repeat\r
+// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- \r
+#define AT91C_CAN_MB0 ((unsigned int) 0x1 << 0) // (CAN) Mailbox 0 Flag\r
+#define AT91C_CAN_MB1 ((unsigned int) 0x1 << 1) // (CAN) Mailbox 1 Flag\r
+#define AT91C_CAN_MB2 ((unsigned int) 0x1 << 2) // (CAN) Mailbox 2 Flag\r
+#define AT91C_CAN_MB3 ((unsigned int) 0x1 << 3) // (CAN) Mailbox 3 Flag\r
+#define AT91C_CAN_MB4 ((unsigned int) 0x1 << 4) // (CAN) Mailbox 4 Flag\r
+#define AT91C_CAN_MB5 ((unsigned int) 0x1 << 5) // (CAN) Mailbox 5 Flag\r
+#define AT91C_CAN_MB6 ((unsigned int) 0x1 << 6) // (CAN) Mailbox 6 Flag\r
+#define AT91C_CAN_MB7 ((unsigned int) 0x1 << 7) // (CAN) Mailbox 7 Flag\r
+#define AT91C_CAN_MB8 ((unsigned int) 0x1 << 8) // (CAN) Mailbox 8 Flag\r
+#define AT91C_CAN_MB9 ((unsigned int) 0x1 << 9) // (CAN) Mailbox 9 Flag\r
+#define AT91C_CAN_MB10 ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag\r
+#define AT91C_CAN_MB11 ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag\r
+#define AT91C_CAN_MB12 ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag\r
+#define AT91C_CAN_MB13 ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag\r
+#define AT91C_CAN_MB14 ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag\r
+#define AT91C_CAN_MB15 ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag\r
+#define AT91C_CAN_ERRA ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag\r
+#define AT91C_CAN_WARN ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag\r
+#define AT91C_CAN_ERRP ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag\r
+#define AT91C_CAN_BOFF ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag\r
+#define AT91C_CAN_SLEEP ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag\r
+#define AT91C_CAN_WAKEUP ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag\r
+#define AT91C_CAN_TOVF ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag\r
+#define AT91C_CAN_TSTP ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag\r
+#define AT91C_CAN_CERR ((unsigned int) 0x1 << 24) // (CAN) CRC Error\r
+#define AT91C_CAN_SERR ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error\r
+#define AT91C_CAN_AERR ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error\r
+#define AT91C_CAN_FERR ((unsigned int) 0x1 << 27) // (CAN) Form Error\r
+#define AT91C_CAN_BERR ((unsigned int) 0x1 << 28) // (CAN) Bit Error\r
+// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- \r
+// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- \r
+// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- \r
+#define AT91C_CAN_RBSY ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy\r
+#define AT91C_CAN_TBSY ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy\r
+#define AT91C_CAN_OVLY ((unsigned int) 0x1 << 31) // (CAN) Overload Busy\r
+// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- \r
+#define AT91C_CAN_PHASE2 ((unsigned int) 0x7 << 0) // (CAN) Phase 2 segment\r
+#define AT91C_CAN_PHASE1 ((unsigned int) 0x7 << 4) // (CAN) Phase 1 segment\r
+#define AT91C_CAN_PROPAG ((unsigned int) 0x7 << 8) // (CAN) Programmation time segment\r
+#define AT91C_CAN_SYNC ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment\r
+#define AT91C_CAN_BRP ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler\r
+#define AT91C_CAN_SMP ((unsigned int) 0x1 << 24) // (CAN) Sampling mode\r
+// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- \r
+#define AT91C_CAN_TIMER ((unsigned int) 0xFFFF << 0) // (CAN) Timer field\r
+// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- \r
+// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- \r
+#define AT91C_CAN_REC ((unsigned int) 0xFF << 0) // (CAN) Receive Error Counter\r
+#define AT91C_CAN_TEC ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter\r
+// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- \r
+#define AT91C_CAN_TIMRST ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field\r
+// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100\r
+// *****************************************************************************\r
+typedef struct _AT91S_EMAC {\r
+ AT91_REG EMAC_NCR; // Network Control Register\r
+ AT91_REG EMAC_NCFGR; // Network Configuration Register\r
+ AT91_REG EMAC_NSR; // Network Status Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG EMAC_TSR; // Transmit Status Register\r
+ AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer\r
+ AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer\r
+ AT91_REG EMAC_RSR; // Receive Status Register\r
+ AT91_REG EMAC_ISR; // Interrupt Status Register\r
+ AT91_REG EMAC_IER; // Interrupt Enable Register\r
+ AT91_REG EMAC_IDR; // Interrupt Disable Register\r
+ AT91_REG EMAC_IMR; // Interrupt Mask Register\r
+ AT91_REG EMAC_MAN; // PHY Maintenance Register\r
+ AT91_REG EMAC_PTR; // Pause Time Register\r
+ AT91_REG EMAC_PFR; // Pause Frames received Register\r
+ AT91_REG EMAC_FTO; // Frames Transmitted OK Register\r
+ AT91_REG EMAC_SCF; // Single Collision Frame Register\r
+ AT91_REG EMAC_MCF; // Multiple Collision Frame Register\r
+ AT91_REG EMAC_FRO; // Frames Received OK Register\r
+ AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register\r
+ AT91_REG EMAC_ALE; // Alignment Error Register\r
+ AT91_REG EMAC_DTF; // Deferred Transmission Frame Register\r
+ AT91_REG EMAC_LCOL; // Late Collision Register\r
+ AT91_REG EMAC_ECOL; // Excessive Collision Register\r
+ AT91_REG EMAC_TUND; // Transmit Underrun Error Register\r
+ AT91_REG EMAC_CSE; // Carrier Sense Error Register\r
+ AT91_REG EMAC_RRE; // Receive Ressource Error Register\r
+ AT91_REG EMAC_ROV; // Receive Overrun Errors Register\r
+ AT91_REG EMAC_RSE; // Receive Symbol Errors Register\r
+ AT91_REG EMAC_ELE; // Excessive Length Errors Register\r
+ AT91_REG EMAC_RJA; // Receive Jabbers Register\r
+ AT91_REG EMAC_USF; // Undersize Frames Register\r
+ AT91_REG EMAC_STE; // SQE Test Error Register\r
+ AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register\r
+ AT91_REG EMAC_TPF; // Transmitted Pause Frames Register\r
+ AT91_REG EMAC_HRB; // Hash Address Bottom[31:0]\r
+ AT91_REG EMAC_HRT; // Hash Address Top[63:32]\r
+ AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes\r
+ AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes\r
+ AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes\r
+ AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes\r
+ AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes\r
+ AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes\r
+ AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes\r
+ AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes\r
+ AT91_REG EMAC_TID; // Type ID Checking Register\r
+ AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register\r
+ AT91_REG EMAC_USRIO; // USER Input/Output Register\r
+ AT91_REG EMAC_WOL; // Wake On LAN Register\r
+ AT91_REG Reserved1[13]; // \r
+ AT91_REG EMAC_REV; // Revision Register\r
+} AT91S_EMAC, *AT91PS_EMAC;\r
+\r
+// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- \r
+#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.\r
+#define AT91C_EMAC_LLB ((unsigned int) 0x1 << 1) // (EMAC) Loopback local. \r
+#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) // (EMAC) Receive enable. \r
+#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) // (EMAC) Transmit enable. \r
+#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) // (EMAC) Management port enable. \r
+#define AT91C_EMAC_CLRSTAT ((unsigned int) 0x1 << 5) // (EMAC) Clear statistics registers. \r
+#define AT91C_EMAC_INCSTAT ((unsigned int) 0x1 << 6) // (EMAC) Increment statistics registers. \r
+#define AT91C_EMAC_WESTAT ((unsigned int) 0x1 << 7) // (EMAC) Write enable for statistics registers. \r
+#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) // (EMAC) Back pressure. \r
+#define AT91C_EMAC_TSTART ((unsigned int) 0x1 << 9) // (EMAC) Start Transmission. \r
+#define AT91C_EMAC_THALT ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt. \r
+#define AT91C_EMAC_TPFR ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame \r
+#define AT91C_EMAC_TZQ ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame\r
+// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- \r
+#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) // (EMAC) Speed. \r
+#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) // (EMAC) Full duplex. \r
+#define AT91C_EMAC_JFRAME ((unsigned int) 0x1 << 3) // (EMAC) Jumbo Frames. \r
+#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) // (EMAC) Copy all frames. \r
+#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) // (EMAC) No broadcast. \r
+#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) // (EMAC) Multicast hash event enable\r
+#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) // (EMAC) Unicast hash enable. \r
+#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) // (EMAC) Receive 1522 bytes. \r
+#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) // (EMAC) External address match enable. \r
+#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) // (EMAC) \r
+#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8\r
+#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16\r
+#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32\r
+#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64\r
+#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) // (EMAC) \r
+#define AT91C_EMAC_PAE ((unsigned int) 0x1 << 13) // (EMAC) \r
+#define AT91C_EMAC_RBOF ((unsigned int) 0x3 << 14) // (EMAC) \r
+#define AT91C_EMAC_RBOF_OFFSET_0 ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer\r
+#define AT91C_EMAC_RBOF_OFFSET_1 ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer\r
+#define AT91C_EMAC_RBOF_OFFSET_2 ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer\r
+#define AT91C_EMAC_RBOF_OFFSET_3 ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer\r
+#define AT91C_EMAC_RLCE ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable\r
+#define AT91C_EMAC_DRFCS ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS\r
+#define AT91C_EMAC_EFRHD ((unsigned int) 0x1 << 18) // (EMAC) \r
+#define AT91C_EMAC_IRXFCS ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS\r
+// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- \r
+#define AT91C_EMAC_LINKR ((unsigned int) 0x1 << 0) // (EMAC) \r
+#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) // (EMAC) \r
+#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) // (EMAC) \r
+// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- \r
+#define AT91C_EMAC_UBR ((unsigned int) 0x1 << 0) // (EMAC) \r
+#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) // (EMAC) \r
+#define AT91C_EMAC_RLES ((unsigned int) 0x1 << 2) // (EMAC) \r
+#define AT91C_EMAC_TGO ((unsigned int) 0x1 << 3) // (EMAC) Transmit Go\r
+#define AT91C_EMAC_BEX ((unsigned int) 0x1 << 4) // (EMAC) Buffers exhausted mid frame\r
+#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) // (EMAC) \r
+#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) // (EMAC) \r
+// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- \r
+#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) // (EMAC) \r
+#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) // (EMAC) \r
+#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 2) // (EMAC) \r
+// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- \r
+#define AT91C_EMAC_MFD ((unsigned int) 0x1 << 0) // (EMAC) \r
+#define AT91C_EMAC_RCOMP ((unsigned int) 0x1 << 1) // (EMAC) \r
+#define AT91C_EMAC_RXUBR ((unsigned int) 0x1 << 2) // (EMAC) \r
+#define AT91C_EMAC_TXUBR ((unsigned int) 0x1 << 3) // (EMAC) \r
+#define AT91C_EMAC_TUNDR ((unsigned int) 0x1 << 4) // (EMAC) \r
+#define AT91C_EMAC_RLEX ((unsigned int) 0x1 << 5) // (EMAC) \r
+#define AT91C_EMAC_TXERR ((unsigned int) 0x1 << 6) // (EMAC) \r
+#define AT91C_EMAC_TCOMP ((unsigned int) 0x1 << 7) // (EMAC) \r
+#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) // (EMAC) \r
+#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) // (EMAC) \r
+#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) // (EMAC) \r
+#define AT91C_EMAC_PFRE ((unsigned int) 0x1 << 12) // (EMAC) \r
+#define AT91C_EMAC_PTZ ((unsigned int) 0x1 << 13) // (EMAC) \r
+// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- \r
+// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- \r
+// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- \r
+// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- \r
+#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) // (EMAC) \r
+#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) // (EMAC) \r
+#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) // (EMAC) \r
+#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) // (EMAC) \r
+#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) // (EMAC) \r
+#define AT91C_EMAC_SOF ((unsigned int) 0x3 << 30) // (EMAC) \r
+// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- \r
+#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 0) // (EMAC) Reduce MII\r
+// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- \r
+#define AT91C_EMAC_IP ((unsigned int) 0xFFFF << 0) // (EMAC) ARP request IP address\r
+#define AT91C_EMAC_MAG ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable\r
+#define AT91C_EMAC_ARP ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable\r
+#define AT91C_EMAC_SA1 ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable\r
+// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- \r
+#define AT91C_EMAC_REVREF ((unsigned int) 0xFFFF << 0) // (EMAC) \r
+#define AT91C_EMAC_PARTREF ((unsigned int) 0xFFFF << 16) // (EMAC) \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Analog to Digital Convertor\r
+// *****************************************************************************\r
+typedef struct _AT91S_ADC {\r
+ AT91_REG ADC_CR; // ADC Control Register\r
+ AT91_REG ADC_MR; // ADC Mode Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG ADC_CHER; // ADC Channel Enable Register\r
+ AT91_REG ADC_CHDR; // ADC Channel Disable Register\r
+ AT91_REG ADC_CHSR; // ADC Channel Status Register\r
+ AT91_REG ADC_SR; // ADC Status Register\r
+ AT91_REG ADC_LCDR; // ADC Last Converted Data Register\r
+ AT91_REG ADC_IER; // ADC Interrupt Enable Register\r
+ AT91_REG ADC_IDR; // ADC Interrupt Disable Register\r
+ AT91_REG ADC_IMR; // ADC Interrupt Mask Register\r
+ AT91_REG ADC_CDR0; // ADC Channel Data Register 0\r
+ AT91_REG ADC_CDR1; // ADC Channel Data Register 1\r
+ AT91_REG ADC_CDR2; // ADC Channel Data Register 2\r
+ AT91_REG ADC_CDR3; // ADC Channel Data Register 3\r
+ AT91_REG ADC_CDR4; // ADC Channel Data Register 4\r
+ AT91_REG ADC_CDR5; // ADC Channel Data Register 5\r
+ AT91_REG ADC_CDR6; // ADC Channel Data Register 6\r
+ AT91_REG ADC_CDR7; // ADC Channel Data Register 7\r
+ AT91_REG Reserved1[44]; // \r
+ AT91_REG ADC_RPR; // Receive Pointer Register\r
+ AT91_REG ADC_RCR; // Receive Counter Register\r
+ AT91_REG ADC_TPR; // Transmit Pointer Register\r
+ AT91_REG ADC_TCR; // Transmit Counter Register\r
+ AT91_REG ADC_RNPR; // Receive Next Pointer Register\r
+ AT91_REG ADC_RNCR; // Receive Next Counter Register\r
+ AT91_REG ADC_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG ADC_TNCR; // Transmit Next Counter Register\r
+ AT91_REG ADC_PTCR; // PDC Transfer Control Register\r
+ AT91_REG ADC_PTSR; // PDC Transfer Status Register\r
+} AT91S_ADC, *AT91PS_ADC;\r
+\r
+// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- \r
+#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset\r
+#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion\r
+// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- \r
+#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable\r
+#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software\r
+#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.\r
+#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection\r
+#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0\r
+#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1\r
+#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2\r
+#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3\r
+#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4\r
+#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5\r
+#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger\r
+#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution.\r
+#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution\r
+#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution\r
+#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode\r
+#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode\r
+#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode\r
+#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection\r
+#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time\r
+#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time\r
+// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- \r
+#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0\r
+#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1\r
+#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2\r
+#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3\r
+#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4\r
+#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5\r
+#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6\r
+#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7\r
+// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- \r
+// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- \r
+// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- \r
+#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion\r
+#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error\r
+#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready\r
+#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun\r
+#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer\r
+#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt\r
+// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- \r
+#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted\r
+// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- \r
+// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- \r
+// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- \r
+// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- \r
+#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data\r
+// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- \r
+// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- \r
+// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- \r
+// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- \r
+// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- \r
+// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- \r
+// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Advanced Encryption Standard\r
+// *****************************************************************************\r
+typedef struct _AT91S_AES {\r
+ AT91_REG AES_CR; // Control Register\r
+ AT91_REG AES_MR; // Mode Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG AES_IER; // Interrupt Enable Register\r
+ AT91_REG AES_IDR; // Interrupt Disable Register\r
+ AT91_REG AES_IMR; // Interrupt Mask Register\r
+ AT91_REG AES_ISR; // Interrupt Status Register\r
+ AT91_REG AES_KEYWxR[4]; // Key Word x Register\r
+ AT91_REG Reserved1[4]; // \r
+ AT91_REG AES_IDATAxR[4]; // Input Data x Register\r
+ AT91_REG AES_ODATAxR[4]; // Output Data x Register\r
+ AT91_REG AES_IVxR[4]; // Initialization Vector x Register\r
+ AT91_REG Reserved2[35]; // \r
+ AT91_REG AES_VR; // AES Version Register\r
+ AT91_REG AES_RPR; // Receive Pointer Register\r
+ AT91_REG AES_RCR; // Receive Counter Register\r
+ AT91_REG AES_TPR; // Transmit Pointer Register\r
+ AT91_REG AES_TCR; // Transmit Counter Register\r
+ AT91_REG AES_RNPR; // Receive Next Pointer Register\r
+ AT91_REG AES_RNCR; // Receive Next Counter Register\r
+ AT91_REG AES_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG AES_TNCR; // Transmit Next Counter Register\r
+ AT91_REG AES_PTCR; // PDC Transfer Control Register\r
+ AT91_REG AES_PTSR; // PDC Transfer Status Register\r
+} AT91S_AES, *AT91PS_AES;\r
+\r
+// -------- AES_CR : (AES Offset: 0x0) Control Register -------- \r
+#define AT91C_AES_START ((unsigned int) 0x1 << 0) // (AES) Starts Processing\r
+#define AT91C_AES_SWRST ((unsigned int) 0x1 << 8) // (AES) Software Reset\r
+#define AT91C_AES_LOADSEED ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading\r
+// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- \r
+#define AT91C_AES_CIPHER ((unsigned int) 0x1 << 0) // (AES) Processing Mode\r
+#define AT91C_AES_PROCDLY ((unsigned int) 0xF << 4) // (AES) Processing Delay\r
+#define AT91C_AES_SMOD ((unsigned int) 0x3 << 8) // (AES) Start Mode\r
+#define AT91C_AES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.\r
+#define AT91C_AES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).\r
+#define AT91C_AES_SMOD_PDC ((unsigned int) 0x2 << 8) // (AES) PDC Mode (cf datasheet).\r
+#define AT91C_AES_OPMOD ((unsigned int) 0x7 << 12) // (AES) Operation Mode\r
+#define AT91C_AES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode.\r
+#define AT91C_AES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode.\r
+#define AT91C_AES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode.\r
+#define AT91C_AES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode.\r
+#define AT91C_AES_OPMOD_CTR ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode.\r
+#define AT91C_AES_LOD ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode\r
+#define AT91C_AES_CFBS ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size\r
+#define AT91C_AES_CFBS_128_BIT ((unsigned int) 0x0 << 16) // (AES) 128-bit.\r
+#define AT91C_AES_CFBS_64_BIT ((unsigned int) 0x1 << 16) // (AES) 64-bit.\r
+#define AT91C_AES_CFBS_32_BIT ((unsigned int) 0x2 << 16) // (AES) 32-bit.\r
+#define AT91C_AES_CFBS_16_BIT ((unsigned int) 0x3 << 16) // (AES) 16-bit.\r
+#define AT91C_AES_CFBS_8_BIT ((unsigned int) 0x4 << 16) // (AES) 8-bit.\r
+#define AT91C_AES_CKEY ((unsigned int) 0xF << 20) // (AES) Countermeasure Key\r
+#define AT91C_AES_CTYPE ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type\r
+#define AT91C_AES_CTYPE_TYPE1_EN ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled.\r
+#define AT91C_AES_CTYPE_TYPE2_EN ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled.\r
+#define AT91C_AES_CTYPE_TYPE3_EN ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled.\r
+#define AT91C_AES_CTYPE_TYPE4_EN ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled.\r
+#define AT91C_AES_CTYPE_TYPE5_EN ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled.\r
+// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- \r
+#define AT91C_AES_DATRDY ((unsigned int) 0x1 << 0) // (AES) DATRDY\r
+#define AT91C_AES_ENDRX ((unsigned int) 0x1 << 1) // (AES) PDC Read Buffer End\r
+#define AT91C_AES_ENDTX ((unsigned int) 0x1 << 2) // (AES) PDC Write Buffer End\r
+#define AT91C_AES_RXBUFF ((unsigned int) 0x1 << 3) // (AES) PDC Read Buffer Full\r
+#define AT91C_AES_TXBUFE ((unsigned int) 0x1 << 4) // (AES) PDC Write Buffer Empty\r
+#define AT91C_AES_URAD ((unsigned int) 0x1 << 8) // (AES) Unspecified Register Access Detection\r
+// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- \r
+// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- \r
+// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- \r
+#define AT91C_AES_URAT ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status\r
+#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode.\r
+#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing.\r
+#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing.\r
+#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation.\r
+#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation.\r
+#define AT91C_AES_URAT_WO_REG_READ ((unsigned int) 0x5 << 12) // (AES) Write-only register read access.\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard\r
+// *****************************************************************************\r
+typedef struct _AT91S_TDES {\r
+ AT91_REG TDES_CR; // Control Register\r
+ AT91_REG TDES_MR; // Mode Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG TDES_IER; // Interrupt Enable Register\r
+ AT91_REG TDES_IDR; // Interrupt Disable Register\r
+ AT91_REG TDES_IMR; // Interrupt Mask Register\r
+ AT91_REG TDES_ISR; // Interrupt Status Register\r
+ AT91_REG TDES_KEY1WxR[2]; // Key 1 Word x Register\r
+ AT91_REG TDES_KEY2WxR[2]; // Key 2 Word x Register\r
+ AT91_REG TDES_KEY3WxR[2]; // Key 3 Word x Register\r
+ AT91_REG Reserved1[2]; // \r
+ AT91_REG TDES_IDATAxR[2]; // Input Data x Register\r
+ AT91_REG Reserved2[2]; // \r
+ AT91_REG TDES_ODATAxR[2]; // Output Data x Register\r
+ AT91_REG Reserved3[2]; // \r
+ AT91_REG TDES_IVxR[2]; // Initialization Vector x Register\r
+ AT91_REG Reserved4[37]; // \r
+ AT91_REG TDES_VR; // TDES Version Register\r
+ AT91_REG TDES_RPR; // Receive Pointer Register\r
+ AT91_REG TDES_RCR; // Receive Counter Register\r
+ AT91_REG TDES_TPR; // Transmit Pointer Register\r
+ AT91_REG TDES_TCR; // Transmit Counter Register\r
+ AT91_REG TDES_RNPR; // Receive Next Pointer Register\r
+ AT91_REG TDES_RNCR; // Receive Next Counter Register\r
+ AT91_REG TDES_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG TDES_TNCR; // Transmit Next Counter Register\r
+ AT91_REG TDES_PTCR; // PDC Transfer Control Register\r
+ AT91_REG TDES_PTSR; // PDC Transfer Status Register\r
+} AT91S_TDES, *AT91PS_TDES;\r
+\r
+// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- \r
+#define AT91C_TDES_START ((unsigned int) 0x1 << 0) // (TDES) Starts Processing\r
+#define AT91C_TDES_SWRST ((unsigned int) 0x1 << 8) // (TDES) Software Reset\r
+// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- \r
+#define AT91C_TDES_CIPHER ((unsigned int) 0x1 << 0) // (TDES) Processing Mode\r
+#define AT91C_TDES_TDESMOD ((unsigned int) 0x1 << 1) // (TDES) Single or Triple DES Mode\r
+#define AT91C_TDES_KEYMOD ((unsigned int) 0x1 << 4) // (TDES) Key Mode\r
+#define AT91C_TDES_SMOD ((unsigned int) 0x3 << 8) // (TDES) Start Mode\r
+#define AT91C_TDES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.\r
+#define AT91C_TDES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).\r
+#define AT91C_TDES_SMOD_PDC ((unsigned int) 0x2 << 8) // (TDES) PDC Mode (cf datasheet).\r
+#define AT91C_TDES_OPMOD ((unsigned int) 0x3 << 12) // (TDES) Operation Mode\r
+#define AT91C_TDES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode.\r
+#define AT91C_TDES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode.\r
+#define AT91C_TDES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode.\r
+#define AT91C_TDES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode.\r
+#define AT91C_TDES_LOD ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode\r
+#define AT91C_TDES_CFBS ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size\r
+#define AT91C_TDES_CFBS_64_BIT ((unsigned int) 0x0 << 16) // (TDES) 64-bit.\r
+#define AT91C_TDES_CFBS_32_BIT ((unsigned int) 0x1 << 16) // (TDES) 32-bit.\r
+#define AT91C_TDES_CFBS_16_BIT ((unsigned int) 0x2 << 16) // (TDES) 16-bit.\r
+#define AT91C_TDES_CFBS_8_BIT ((unsigned int) 0x3 << 16) // (TDES) 8-bit.\r
+// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- \r
+#define AT91C_TDES_DATRDY ((unsigned int) 0x1 << 0) // (TDES) DATRDY\r
+#define AT91C_TDES_ENDRX ((unsigned int) 0x1 << 1) // (TDES) PDC Read Buffer End\r
+#define AT91C_TDES_ENDTX ((unsigned int) 0x1 << 2) // (TDES) PDC Write Buffer End\r
+#define AT91C_TDES_RXBUFF ((unsigned int) 0x1 << 3) // (TDES) PDC Read Buffer Full\r
+#define AT91C_TDES_TXBUFE ((unsigned int) 0x1 << 4) // (TDES) PDC Write Buffer Empty\r
+#define AT91C_TDES_URAD ((unsigned int) 0x1 << 8) // (TDES) Unspecified Register Access Detection\r
+// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- \r
+// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- \r
+// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- \r
+#define AT91C_TDES_URAT ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status\r
+#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode.\r
+#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing.\r
+#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing.\r
+#define AT91C_TDES_URAT_WO_REG_READ ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access.\r
+\r
+// *****************************************************************************\r
+// REGISTER ADDRESS DEFINITION FOR AT91SAM7X256\r
+// *****************************************************************************\r
+// ========== Register definition for SYS peripheral ========== \r
+// ========== Register definition for AIC peripheral ========== \r
+#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register\r
+#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register\r
+#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register\r
+#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect)\r
+#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register\r
+#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register\r
+#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register\r
+#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register\r
+#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register\r
+#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register\r
+#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register\r
+#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register\r
+#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register\r
+#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register\r
+#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register\r
+#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register\r
+#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register\r
+#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register\r
+// ========== Register definition for PDC_DBGU peripheral ========== \r
+#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register\r
+#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register\r
+#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register\r
+#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register\r
+#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register\r
+#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register\r
+#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register\r
+#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register\r
+#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register\r
+#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register\r
+// ========== Register definition for DBGU peripheral ========== \r
+#define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register\r
+#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register\r
+#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register\r
+#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register\r
+#define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register\r
+#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register\r
+#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register\r
+#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register\r
+#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register\r
+#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register\r
+#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register\r
+#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register\r
+// ========== Register definition for PIOA peripheral ========== \r
+#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr\r
+#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register\r
+#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register\r
+#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register\r
+#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register\r
+#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register\r
+#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register\r
+#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register\r
+#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register\r
+#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register\r
+#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register\r
+#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register\r
+#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register\r
+#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register\r
+#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register\r
+#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register\r
+#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register\r
+#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register\r
+#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register\r
+#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register\r
+#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register\r
+#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register\r
+#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register\r
+#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register\r
+#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register\r
+#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register\r
+#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register\r
+#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register\r
+#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register\r
+// ========== Register definition for PIOB peripheral ========== \r
+#define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register\r
+#define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register\r
+#define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register\r
+#define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register\r
+#define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register\r
+#define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register\r
+#define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register\r
+#define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register\r
+#define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register\r
+#define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register\r
+#define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register\r
+#define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register\r
+#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register\r
+#define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register\r
+#define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register\r
+#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register\r
+#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr\r
+#define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register\r
+#define AT91C_PIOB_PPUER ((AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register\r
+#define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register\r
+#define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register\r
+#define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register\r
+#define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register\r
+#define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register\r
+#define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register\r
+#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register\r
+#define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register\r
+#define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register\r
+#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register\r
+// ========== Register definition for CKGR peripheral ========== \r
+#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register\r
+#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register\r
+#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register\r
+// ========== Register definition for PMC peripheral ========== \r
+#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register\r
+#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register\r
+#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register\r
+#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register\r
+#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register\r
+#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register\r
+#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register\r
+#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register\r
+#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register\r
+#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register\r
+#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register\r
+#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register\r
+#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register\r
+#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register\r
+#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register\r
+// ========== Register definition for RSTC peripheral ========== \r
+#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register\r
+#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register\r
+#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register\r
+// ========== Register definition for RTTC peripheral ========== \r
+#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register\r
+#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register\r
+#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register\r
+#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register\r
+// ========== Register definition for PITC peripheral ========== \r
+#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register\r
+#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register\r
+#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register\r
+#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register\r
+// ========== Register definition for WDTC peripheral ========== \r
+#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register\r
+#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register\r
+#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register\r
+// ========== Register definition for VREG peripheral ========== \r
+#define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register\r
+// ========== Register definition for MC peripheral ========== \r
+#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register\r
+#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register\r
+#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register\r
+#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register\r
+#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register\r
+#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register\r
+// ========== Register definition for PDC_SPI1 peripheral ========== \r
+#define AT91C_SPI1_PTCR ((AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register\r
+#define AT91C_SPI1_RPR ((AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register\r
+#define AT91C_SPI1_TNCR ((AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register\r
+#define AT91C_SPI1_TPR ((AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register\r
+#define AT91C_SPI1_TNPR ((AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register\r
+#define AT91C_SPI1_TCR ((AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register\r
+#define AT91C_SPI1_RCR ((AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register\r
+#define AT91C_SPI1_RNPR ((AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register\r
+#define AT91C_SPI1_RNCR ((AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register\r
+#define AT91C_SPI1_PTSR ((AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register\r
+// ========== Register definition for SPI1 peripheral ========== \r
+#define AT91C_SPI1_IMR ((AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register\r
+#define AT91C_SPI1_IER ((AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register\r
+#define AT91C_SPI1_MR ((AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register\r
+#define AT91C_SPI1_RDR ((AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register\r
+#define AT91C_SPI1_IDR ((AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register\r
+#define AT91C_SPI1_SR ((AT91_REG *) 0xFFFE4010) // (SPI1) Status Register\r
+#define AT91C_SPI1_TDR ((AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register\r
+#define AT91C_SPI1_CR ((AT91_REG *) 0xFFFE4000) // (SPI1) Control Register\r
+#define AT91C_SPI1_CSR ((AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register\r
+// ========== Register definition for PDC_SPI0 peripheral ========== \r
+#define AT91C_SPI0_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register\r
+#define AT91C_SPI0_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register\r
+#define AT91C_SPI0_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register\r
+#define AT91C_SPI0_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register\r
+#define AT91C_SPI0_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register\r
+#define AT91C_SPI0_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register\r
+#define AT91C_SPI0_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register\r
+#define AT91C_SPI0_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register\r
+#define AT91C_SPI0_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register\r
+#define AT91C_SPI0_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register\r
+// ========== Register definition for SPI0 peripheral ========== \r
+#define AT91C_SPI0_IER ((AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register\r
+#define AT91C_SPI0_SR ((AT91_REG *) 0xFFFE0010) // (SPI0) Status Register\r
+#define AT91C_SPI0_IDR ((AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register\r
+#define AT91C_SPI0_CR ((AT91_REG *) 0xFFFE0000) // (SPI0) Control Register\r
+#define AT91C_SPI0_MR ((AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register\r
+#define AT91C_SPI0_IMR ((AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register\r
+#define AT91C_SPI0_TDR ((AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register\r
+#define AT91C_SPI0_RDR ((AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register\r
+#define AT91C_SPI0_CSR ((AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register\r
+// ========== Register definition for PDC_US1 peripheral ========== \r
+#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register\r
+#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register\r
+#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register\r
+#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register\r
+#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register\r
+#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register\r
+#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register\r
+#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register\r
+#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register\r
+#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register\r
+// ========== Register definition for US1 peripheral ========== \r
+#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register\r
+#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register\r
+#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register\r
+#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register\r
+#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register\r
+#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register\r
+#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register\r
+#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register\r
+#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register\r
+#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register\r
+#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register\r
+#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register\r
+#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register\r
+#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register\r
+// ========== Register definition for PDC_US0 peripheral ========== \r
+#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register\r
+#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register\r
+#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register\r
+#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register\r
+#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register\r
+#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register\r
+#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register\r
+#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register\r
+#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register\r
+#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register\r
+// ========== Register definition for US0 peripheral ========== \r
+#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register\r
+#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register\r
+#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register\r
+#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register\r
+#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register\r
+#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register\r
+#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register\r
+#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register\r
+#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register\r
+#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register\r
+#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register\r
+#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register\r
+#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register\r
+#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register\r
+// ========== Register definition for PDC_SSC peripheral ========== \r
+#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register\r
+#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register\r
+#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register\r
+#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register\r
+#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register\r
+#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register\r
+#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register\r
+#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register\r
+#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register\r
+#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register\r
+// ========== Register definition for SSC peripheral ========== \r
+#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register\r
+#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register\r
+#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register\r
+#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register\r
+#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register\r
+#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister\r
+#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register\r
+#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register\r
+#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register\r
+#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register\r
+#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register\r
+#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register\r
+#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register\r
+#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register\r
+// ========== Register definition for TWI peripheral ========== \r
+#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register\r
+#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register\r
+#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register\r
+#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register\r
+#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register\r
+#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register\r
+#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register\r
+#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register\r
+#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register\r
+#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register\r
+// ========== Register definition for PWMC_CH3 peripheral ========== \r
+#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register\r
+#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved\r
+#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register\r
+#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register\r
+#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register\r
+#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register\r
+// ========== Register definition for PWMC_CH2 peripheral ========== \r
+#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved\r
+#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register\r
+#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register\r
+#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register\r
+#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register\r
+#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register\r
+// ========== Register definition for PWMC_CH1 peripheral ========== \r
+#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved\r
+#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register\r
+#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register\r
+#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register\r
+#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register\r
+#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register\r
+// ========== Register definition for PWMC_CH0 peripheral ========== \r
+#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved\r
+#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register\r
+#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register\r
+#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register\r
+#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register\r
+#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register\r
+// ========== Register definition for PWMC peripheral ========== \r
+#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register\r
+#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register\r
+#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register\r
+#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register\r
+#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register\r
+#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register\r
+#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register\r
+#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register\r
+#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register\r
+// ========== Register definition for UDP peripheral ========== \r
+#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register\r
+#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register\r
+#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register\r
+#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register\r
+#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register\r
+#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register\r
+#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register\r
+#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register\r
+#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register\r
+#define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register\r
+#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register\r
+#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register\r
+// ========== Register definition for TC0 peripheral ========== \r
+#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register\r
+#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C\r
+#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B\r
+#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register\r
+#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register\r
+#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A\r
+#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register\r
+#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value\r
+#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register\r
+// ========== Register definition for TC1 peripheral ========== \r
+#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B\r
+#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register\r
+#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register\r
+#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register\r
+#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register\r
+#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A\r
+#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C\r
+#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register\r
+#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value\r
+// ========== Register definition for TC2 peripheral ========== \r
+#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register\r
+#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value\r
+#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A\r
+#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B\r
+#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register\r
+#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register\r
+#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C\r
+#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register\r
+#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register\r
+// ========== Register definition for TCB peripheral ========== \r
+#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register\r
+#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register\r
+// ========== Register definition for CAN_MB0 peripheral ========== \r
+#define AT91C_CAN_MB0_MDL ((AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register\r
+#define AT91C_CAN_MB0_MAM ((AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register\r
+#define AT91C_CAN_MB0_MCR ((AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register\r
+#define AT91C_CAN_MB0_MID ((AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register\r
+#define AT91C_CAN_MB0_MSR ((AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register\r
+#define AT91C_CAN_MB0_MFID ((AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register\r
+#define AT91C_CAN_MB0_MDH ((AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register\r
+#define AT91C_CAN_MB0_MMR ((AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register\r
+// ========== Register definition for CAN_MB1 peripheral ========== \r
+#define AT91C_CAN_MB1_MDL ((AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register\r
+#define AT91C_CAN_MB1_MID ((AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register\r
+#define AT91C_CAN_MB1_MMR ((AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register\r
+#define AT91C_CAN_MB1_MSR ((AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register\r
+#define AT91C_CAN_MB1_MAM ((AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register\r
+#define AT91C_CAN_MB1_MDH ((AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register\r
+#define AT91C_CAN_MB1_MCR ((AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register\r
+#define AT91C_CAN_MB1_MFID ((AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register\r
+// ========== Register definition for CAN_MB2 peripheral ========== \r
+#define AT91C_CAN_MB2_MCR ((AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register\r
+#define AT91C_CAN_MB2_MDH ((AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register\r
+#define AT91C_CAN_MB2_MID ((AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register\r
+#define AT91C_CAN_MB2_MDL ((AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register\r
+#define AT91C_CAN_MB2_MMR ((AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register\r
+#define AT91C_CAN_MB2_MAM ((AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register\r
+#define AT91C_CAN_MB2_MFID ((AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register\r
+#define AT91C_CAN_MB2_MSR ((AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register\r
+// ========== Register definition for CAN_MB3 peripheral ========== \r
+#define AT91C_CAN_MB3_MFID ((AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register\r
+#define AT91C_CAN_MB3_MAM ((AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register\r
+#define AT91C_CAN_MB3_MID ((AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register\r
+#define AT91C_CAN_MB3_MCR ((AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register\r
+#define AT91C_CAN_MB3_MMR ((AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register\r
+#define AT91C_CAN_MB3_MSR ((AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register\r
+#define AT91C_CAN_MB3_MDL ((AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register\r
+#define AT91C_CAN_MB3_MDH ((AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register\r
+// ========== Register definition for CAN_MB4 peripheral ========== \r
+#define AT91C_CAN_MB4_MID ((AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register\r
+#define AT91C_CAN_MB4_MMR ((AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register\r
+#define AT91C_CAN_MB4_MDH ((AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register\r
+#define AT91C_CAN_MB4_MFID ((AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register\r
+#define AT91C_CAN_MB4_MSR ((AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register\r
+#define AT91C_CAN_MB4_MCR ((AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register\r
+#define AT91C_CAN_MB4_MDL ((AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register\r
+#define AT91C_CAN_MB4_MAM ((AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register\r
+// ========== Register definition for CAN_MB5 peripheral ========== \r
+#define AT91C_CAN_MB5_MSR ((AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register\r
+#define AT91C_CAN_MB5_MCR ((AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register\r
+#define AT91C_CAN_MB5_MFID ((AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register\r
+#define AT91C_CAN_MB5_MDH ((AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register\r
+#define AT91C_CAN_MB5_MID ((AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register\r
+#define AT91C_CAN_MB5_MMR ((AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register\r
+#define AT91C_CAN_MB5_MDL ((AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register\r
+#define AT91C_CAN_MB5_MAM ((AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register\r
+// ========== Register definition for CAN_MB6 peripheral ========== \r
+#define AT91C_CAN_MB6_MFID ((AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register\r
+#define AT91C_CAN_MB6_MID ((AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register\r
+#define AT91C_CAN_MB6_MAM ((AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register\r
+#define AT91C_CAN_MB6_MSR ((AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register\r
+#define AT91C_CAN_MB6_MDL ((AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register\r
+#define AT91C_CAN_MB6_MCR ((AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register\r
+#define AT91C_CAN_MB6_MDH ((AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register\r
+#define AT91C_CAN_MB6_MMR ((AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register\r
+// ========== Register definition for CAN_MB7 peripheral ========== \r
+#define AT91C_CAN_MB7_MCR ((AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register\r
+#define AT91C_CAN_MB7_MDH ((AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register\r
+#define AT91C_CAN_MB7_MFID ((AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register\r
+#define AT91C_CAN_MB7_MDL ((AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register\r
+#define AT91C_CAN_MB7_MID ((AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register\r
+#define AT91C_CAN_MB7_MMR ((AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register\r
+#define AT91C_CAN_MB7_MAM ((AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register\r
+#define AT91C_CAN_MB7_MSR ((AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register\r
+// ========== Register definition for CAN peripheral ========== \r
+#define AT91C_CAN_TCR ((AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register\r
+#define AT91C_CAN_IMR ((AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register\r
+#define AT91C_CAN_IER ((AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register\r
+#define AT91C_CAN_ECR ((AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register\r
+#define AT91C_CAN_TIMESTP ((AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register\r
+#define AT91C_CAN_MR ((AT91_REG *) 0xFFFD0000) // (CAN) Mode Register\r
+#define AT91C_CAN_IDR ((AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register\r
+#define AT91C_CAN_ACR ((AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register\r
+#define AT91C_CAN_TIM ((AT91_REG *) 0xFFFD0018) // (CAN) Timer Register\r
+#define AT91C_CAN_SR ((AT91_REG *) 0xFFFD0010) // (CAN) Status Register\r
+#define AT91C_CAN_BR ((AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register\r
+#define AT91C_CAN_VR ((AT91_REG *) 0xFFFD00FC) // (CAN) Version Register\r
+// ========== Register definition for EMAC peripheral ========== \r
+#define AT91C_EMAC_ISR ((AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register\r
+#define AT91C_EMAC_SA4H ((AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes\r
+#define AT91C_EMAC_SA1L ((AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes\r
+#define AT91C_EMAC_ELE ((AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register\r
+#define AT91C_EMAC_LCOL ((AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register\r
+#define AT91C_EMAC_RLE ((AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register\r
+#define AT91C_EMAC_WOL ((AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register\r
+#define AT91C_EMAC_DTF ((AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register\r
+#define AT91C_EMAC_TUND ((AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register\r
+#define AT91C_EMAC_NCR ((AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register\r
+#define AT91C_EMAC_SA4L ((AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes\r
+#define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register\r
+#define AT91C_EMAC_SA3L ((AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes\r
+#define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register\r
+#define AT91C_EMAC_IDR ((AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register\r
+#define AT91C_EMAC_RSE ((AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register\r
+#define AT91C_EMAC_ECOL ((AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register\r
+#define AT91C_EMAC_TID ((AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register\r
+#define AT91C_EMAC_HRB ((AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]\r
+#define AT91C_EMAC_TBQP ((AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer\r
+#define AT91C_EMAC_USRIO ((AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register\r
+#define AT91C_EMAC_PTR ((AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register\r
+#define AT91C_EMAC_SA2H ((AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes\r
+#define AT91C_EMAC_ROV ((AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register\r
+#define AT91C_EMAC_ALE ((AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register\r
+#define AT91C_EMAC_RJA ((AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register\r
+#define AT91C_EMAC_RBQP ((AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer\r
+#define AT91C_EMAC_TPF ((AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register\r
+#define AT91C_EMAC_NCFGR ((AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register\r
+#define AT91C_EMAC_HRT ((AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32]\r
+#define AT91C_EMAC_USF ((AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register\r
+#define AT91C_EMAC_FCSE ((AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register\r
+#define AT91C_EMAC_TPQ ((AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register\r
+#define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register\r
+#define AT91C_EMAC_FTO ((AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register\r
+#define AT91C_EMAC_REV ((AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register\r
+#define AT91C_EMAC_IMR ((AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register\r
+#define AT91C_EMAC_SCF ((AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register\r
+#define AT91C_EMAC_PFR ((AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register\r
+#define AT91C_EMAC_MCF ((AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register\r
+#define AT91C_EMAC_NSR ((AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register\r
+#define AT91C_EMAC_SA2L ((AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes\r
+#define AT91C_EMAC_FRO ((AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register\r
+#define AT91C_EMAC_IER ((AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register\r
+#define AT91C_EMAC_SA1H ((AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes\r
+#define AT91C_EMAC_CSE ((AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register\r
+#define AT91C_EMAC_SA3H ((AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes\r
+#define AT91C_EMAC_RRE ((AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register\r
+#define AT91C_EMAC_STE ((AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register\r
+// ========== Register definition for PDC_ADC peripheral ========== \r
+#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register\r
+#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register\r
+#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register\r
+#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register\r
+#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register\r
+#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register\r
+#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register\r
+#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register\r
+#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register\r
+#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register\r
+// ========== Register definition for ADC peripheral ========== \r
+#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2\r
+#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3\r
+#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0\r
+#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5\r
+#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register\r
+#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register\r
+#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4\r
+#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1\r
+#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register\r
+#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register\r
+#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register\r
+#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7\r
+#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6\r
+#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register\r
+#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register\r
+#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register\r
+#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register\r
+#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register\r
+// ========== Register definition for PDC_AES peripheral ========== \r
+#define AT91C_AES_TPR ((AT91_REG *) 0xFFFA4108) // (PDC_AES) Transmit Pointer Register\r
+#define AT91C_AES_PTCR ((AT91_REG *) 0xFFFA4120) // (PDC_AES) PDC Transfer Control Register\r
+#define AT91C_AES_RNPR ((AT91_REG *) 0xFFFA4110) // (PDC_AES) Receive Next Pointer Register\r
+#define AT91C_AES_TNCR ((AT91_REG *) 0xFFFA411C) // (PDC_AES) Transmit Next Counter Register\r
+#define AT91C_AES_TCR ((AT91_REG *) 0xFFFA410C) // (PDC_AES) Transmit Counter Register\r
+#define AT91C_AES_RCR ((AT91_REG *) 0xFFFA4104) // (PDC_AES) Receive Counter Register\r
+#define AT91C_AES_RNCR ((AT91_REG *) 0xFFFA4114) // (PDC_AES) Receive Next Counter Register\r
+#define AT91C_AES_TNPR ((AT91_REG *) 0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register\r
+#define AT91C_AES_RPR ((AT91_REG *) 0xFFFA4100) // (PDC_AES) Receive Pointer Register\r
+#define AT91C_AES_PTSR ((AT91_REG *) 0xFFFA4124) // (PDC_AES) PDC Transfer Status Register\r
+// ========== Register definition for AES peripheral ========== \r
+#define AT91C_AES_IVxR ((AT91_REG *) 0xFFFA4060) // (AES) Initialization Vector x Register\r
+#define AT91C_AES_MR ((AT91_REG *) 0xFFFA4004) // (AES) Mode Register\r
+#define AT91C_AES_VR ((AT91_REG *) 0xFFFA40FC) // (AES) AES Version Register\r
+#define AT91C_AES_ODATAxR ((AT91_REG *) 0xFFFA4050) // (AES) Output Data x Register\r
+#define AT91C_AES_IDATAxR ((AT91_REG *) 0xFFFA4040) // (AES) Input Data x Register\r
+#define AT91C_AES_CR ((AT91_REG *) 0xFFFA4000) // (AES) Control Register\r
+#define AT91C_AES_IDR ((AT91_REG *) 0xFFFA4014) // (AES) Interrupt Disable Register\r
+#define AT91C_AES_IMR ((AT91_REG *) 0xFFFA4018) // (AES) Interrupt Mask Register\r
+#define AT91C_AES_IER ((AT91_REG *) 0xFFFA4010) // (AES) Interrupt Enable Register\r
+#define AT91C_AES_KEYWxR ((AT91_REG *) 0xFFFA4020) // (AES) Key Word x Register\r
+#define AT91C_AES_ISR ((AT91_REG *) 0xFFFA401C) // (AES) Interrupt Status Register\r
+// ========== Register definition for PDC_TDES peripheral ========== \r
+#define AT91C_TDES_RNCR ((AT91_REG *) 0xFFFA8114) // (PDC_TDES) Receive Next Counter Register\r
+#define AT91C_TDES_TCR ((AT91_REG *) 0xFFFA810C) // (PDC_TDES) Transmit Counter Register\r
+#define AT91C_TDES_RCR ((AT91_REG *) 0xFFFA8104) // (PDC_TDES) Receive Counter Register\r
+#define AT91C_TDES_TNPR ((AT91_REG *) 0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register\r
+#define AT91C_TDES_RNPR ((AT91_REG *) 0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register\r
+#define AT91C_TDES_RPR ((AT91_REG *) 0xFFFA8100) // (PDC_TDES) Receive Pointer Register\r
+#define AT91C_TDES_TNCR ((AT91_REG *) 0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register\r
+#define AT91C_TDES_TPR ((AT91_REG *) 0xFFFA8108) // (PDC_TDES) Transmit Pointer Register\r
+#define AT91C_TDES_PTSR ((AT91_REG *) 0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register\r
+#define AT91C_TDES_PTCR ((AT91_REG *) 0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register\r
+// ========== Register definition for TDES peripheral ========== \r
+#define AT91C_TDES_KEY2WxR ((AT91_REG *) 0xFFFA8028) // (TDES) Key 2 Word x Register\r
+#define AT91C_TDES_KEY3WxR ((AT91_REG *) 0xFFFA8030) // (TDES) Key 3 Word x Register\r
+#define AT91C_TDES_IDR ((AT91_REG *) 0xFFFA8014) // (TDES) Interrupt Disable Register\r
+#define AT91C_TDES_VR ((AT91_REG *) 0xFFFA80FC) // (TDES) TDES Version Register\r
+#define AT91C_TDES_IVxR ((AT91_REG *) 0xFFFA8060) // (TDES) Initialization Vector x Register\r
+#define AT91C_TDES_ODATAxR ((AT91_REG *) 0xFFFA8050) // (TDES) Output Data x Register\r
+#define AT91C_TDES_IMR ((AT91_REG *) 0xFFFA8018) // (TDES) Interrupt Mask Register\r
+#define AT91C_TDES_MR ((AT91_REG *) 0xFFFA8004) // (TDES) Mode Register\r
+#define AT91C_TDES_CR ((AT91_REG *) 0xFFFA8000) // (TDES) Control Register\r
+#define AT91C_TDES_IER ((AT91_REG *) 0xFFFA8010) // (TDES) Interrupt Enable Register\r
+#define AT91C_TDES_ISR ((AT91_REG *) 0xFFFA801C) // (TDES) Interrupt Status Register\r
+#define AT91C_TDES_IDATAxR ((AT91_REG *) 0xFFFA8040) // (TDES) Input Data x Register\r
+#define AT91C_TDES_KEY1WxR ((AT91_REG *) 0xFFFA8020) // (TDES) Key 1 Word x Register\r
+\r
+// *****************************************************************************\r
+// PIO DEFINITIONS FOR AT91SAM7X256\r
+// *****************************************************************************\r
+#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0\r
+#define AT91C_PA0_RXD0 ((unsigned int) AT91C_PIO_PA0) // USART 0 Receive Data\r
+#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1\r
+#define AT91C_PA1_TXD0 ((unsigned int) AT91C_PIO_PA1) // USART 0 Transmit Data\r
+#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10\r
+#define AT91C_PA10_TWD ((unsigned int) AT91C_PIO_PA10) // TWI Two-wire Serial Data\r
+#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11\r
+#define AT91C_PA11_TWCK ((unsigned int) AT91C_PIO_PA11) // TWI Two-wire Serial Clock\r
+#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12\r
+#define AT91C_PA12_NPCS00 ((unsigned int) AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0\r
+#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13\r
+#define AT91C_PA13_NPCS01 ((unsigned int) AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1\r
+#define AT91C_PA13_PCK1 ((unsigned int) AT91C_PIO_PA13) // PMC Programmable Clock Output 1\r
+#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14\r
+#define AT91C_PA14_NPCS02 ((unsigned int) AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2\r
+#define AT91C_PA14_IRQ1 ((unsigned int) AT91C_PIO_PA14) // External Interrupt 1\r
+#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15\r
+#define AT91C_PA15_NPCS03 ((unsigned int) AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3\r
+#define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input\r
+#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16\r
+#define AT91C_PA16_MISO0 ((unsigned int) AT91C_PIO_PA16) // SPI 0 Master In Slave\r
+#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17\r
+#define AT91C_PA17_MOSI0 ((unsigned int) AT91C_PIO_PA17) // SPI 0 Master Out Slave\r
+#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18\r
+#define AT91C_PA18_SPCK0 ((unsigned int) AT91C_PIO_PA18) // SPI 0 Serial Clock\r
+#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19\r
+#define AT91C_PA19_CANRX ((unsigned int) AT91C_PIO_PA19) // CAN Receive\r
+#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2\r
+#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock\r
+#define AT91C_PA2_NPCS11 ((unsigned int) AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1\r
+#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20\r
+#define AT91C_PA20_CANTX ((unsigned int) AT91C_PIO_PA20) // CAN Transmit\r
+#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21\r
+#define AT91C_PA21_TF ((unsigned int) AT91C_PIO_PA21) // SSC Transmit Frame Sync\r
+#define AT91C_PA21_NPCS10 ((unsigned int) AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0\r
+#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22\r
+#define AT91C_PA22_TK ((unsigned int) AT91C_PIO_PA22) // SSC Transmit Clock\r
+#define AT91C_PA22_SPCK1 ((unsigned int) AT91C_PIO_PA22) // SPI 1 Serial Clock\r
+#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23\r
+#define AT91C_PA23_TD ((unsigned int) AT91C_PIO_PA23) // SSC Transmit data\r
+#define AT91C_PA23_MOSI1 ((unsigned int) AT91C_PIO_PA23) // SPI 1 Master Out Slave\r
+#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24\r
+#define AT91C_PA24_RD ((unsigned int) AT91C_PIO_PA24) // SSC Receive Data\r
+#define AT91C_PA24_MISO1 ((unsigned int) AT91C_PIO_PA24) // SPI 1 Master In Slave\r
+#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25\r
+#define AT91C_PA25_RK ((unsigned int) AT91C_PIO_PA25) // SSC Receive Clock\r
+#define AT91C_PA25_NPCS11 ((unsigned int) AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1\r
+#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26\r
+#define AT91C_PA26_RF ((unsigned int) AT91C_PIO_PA26) // SSC Receive Frame Sync\r
+#define AT91C_PA26_NPCS12 ((unsigned int) AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2\r
+#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27\r
+#define AT91C_PA27_DRXD ((unsigned int) AT91C_PIO_PA27) // DBGU Debug Receive Data\r
+#define AT91C_PA27_PCK3 ((unsigned int) AT91C_PIO_PA27) // PMC Programmable Clock Output 3\r
+#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28\r
+#define AT91C_PA28_DTXD ((unsigned int) AT91C_PIO_PA28) // DBGU Debug Transmit Data\r
+#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29\r
+#define AT91C_PA29_FIQ ((unsigned int) AT91C_PIO_PA29) // AIC Fast Interrupt Input\r
+#define AT91C_PA29_NPCS13 ((unsigned int) AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3\r
+#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3\r
+#define AT91C_PA3_RTS0 ((unsigned int) AT91C_PIO_PA3) // USART 0 Ready To Send\r
+#define AT91C_PA3_NPCS12 ((unsigned int) AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2\r
+#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30\r
+#define AT91C_PA30_IRQ0 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 0\r
+#define AT91C_PA30_PCK2 ((unsigned int) AT91C_PIO_PA30) // PMC Programmable Clock Output 2\r
+#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4\r
+#define AT91C_PA4_CTS0 ((unsigned int) AT91C_PIO_PA4) // USART 0 Clear To Send\r
+#define AT91C_PA4_NPCS13 ((unsigned int) AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3\r
+#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5\r
+#define AT91C_PA5_RXD1 ((unsigned int) AT91C_PIO_PA5) // USART 1 Receive Data\r
+#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6\r
+#define AT91C_PA6_TXD1 ((unsigned int) AT91C_PIO_PA6) // USART 1 Transmit Data\r
+#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7\r
+#define AT91C_PA7_SCK1 ((unsigned int) AT91C_PIO_PA7) // USART 1 Serial Clock\r
+#define AT91C_PA7_NPCS01 ((unsigned int) AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1\r
+#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8\r
+#define AT91C_PA8_RTS1 ((unsigned int) AT91C_PIO_PA8) // USART 1 Ready To Send\r
+#define AT91C_PA8_NPCS02 ((unsigned int) AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2\r
+#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9\r
+#define AT91C_PA9_CTS1 ((unsigned int) AT91C_PIO_PA9) // USART 1 Clear To Send\r
+#define AT91C_PA9_NPCS03 ((unsigned int) AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3\r
+#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0\r
+#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock\r
+#define AT91C_PB0_PCK0 ((unsigned int) AT91C_PIO_PB0) // PMC Programmable Clock Output 0\r
+#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1\r
+#define AT91C_PB1_ETXEN ((unsigned int) AT91C_PIO_PB1) // Ethernet MAC Transmit Enable\r
+#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10\r
+#define AT91C_PB10_ETX2 ((unsigned int) AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2\r
+#define AT91C_PB10_NPCS11 ((unsigned int) AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1\r
+#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11\r
+#define AT91C_PB11_ETX3 ((unsigned int) AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3\r
+#define AT91C_PB11_NPCS12 ((unsigned int) AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2\r
+#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12\r
+#define AT91C_PB12_ETXER ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error\r
+#define AT91C_PB12_TCLK0 ((unsigned int) AT91C_PIO_PB12) // Timer Counter 0 external clock input\r
+#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13\r
+#define AT91C_PB13_ERX2 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Receive Data 2\r
+#define AT91C_PB13_NPCS01 ((unsigned int) AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1\r
+#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14\r
+#define AT91C_PB14_ERX3 ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Receive Data 3\r
+#define AT91C_PB14_NPCS02 ((unsigned int) AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2\r
+#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15\r
+#define AT91C_PB15_ERXDV ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid\r
+#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16\r
+#define AT91C_PB16_ECOL ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Collision Detected\r
+#define AT91C_PB16_NPCS13 ((unsigned int) AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3\r
+#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17\r
+#define AT91C_PB17_ERXCK ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Clock\r
+#define AT91C_PB17_NPCS03 ((unsigned int) AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3\r
+#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18\r
+#define AT91C_PB18_EF100 ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec\r
+#define AT91C_PB18_ADTRG ((unsigned int) AT91C_PIO_PB18) // ADC External Trigger\r
+#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19\r
+#define AT91C_PB19_PWM0 ((unsigned int) AT91C_PIO_PB19) // PWM Channel 0\r
+#define AT91C_PB19_TCLK1 ((unsigned int) AT91C_PIO_PB19) // Timer Counter 1 external clock input\r
+#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2\r
+#define AT91C_PB2_ETX0 ((unsigned int) AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0\r
+#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20\r
+#define AT91C_PB20_PWM1 ((unsigned int) AT91C_PIO_PB20) // PWM Channel 1\r
+#define AT91C_PB20_PCK0 ((unsigned int) AT91C_PIO_PB20) // PMC Programmable Clock Output 0\r
+#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21\r
+#define AT91C_PB21_PWM2 ((unsigned int) AT91C_PIO_PB21) // PWM Channel 2\r
+#define AT91C_PB21_PCK1 ((unsigned int) AT91C_PIO_PB21) // PMC Programmable Clock Output 1\r
+#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22\r
+#define AT91C_PB22_PWM3 ((unsigned int) AT91C_PIO_PB22) // PWM Channel 3\r
+#define AT91C_PB22_PCK2 ((unsigned int) AT91C_PIO_PB22) // PMC Programmable Clock Output 2\r
+#define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23\r
+#define AT91C_PB23_TIOA0 ((unsigned int) AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A\r
+#define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect\r
+#define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24\r
+#define AT91C_PB24_TIOB0 ((unsigned int) AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B\r
+#define AT91C_PB24_DSR1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Data Set ready\r
+#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25\r
+#define AT91C_PB25_TIOA1 ((unsigned int) AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A\r
+#define AT91C_PB25_DTR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Terminal ready\r
+#define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26\r
+#define AT91C_PB26_TIOB1 ((unsigned int) AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B\r
+#define AT91C_PB26_RI1 ((unsigned int) AT91C_PIO_PB26) // USART 1 Ring Indicator\r
+#define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27\r
+#define AT91C_PB27_TIOA2 ((unsigned int) AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A\r
+#define AT91C_PB27_PWM0 ((unsigned int) AT91C_PIO_PB27) // PWM Channel 0\r
+#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28\r
+#define AT91C_PB28_TIOB2 ((unsigned int) AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B\r
+#define AT91C_PB28_PWM1 ((unsigned int) AT91C_PIO_PB28) // PWM Channel 1\r
+#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29\r
+#define AT91C_PB29_PCK1 ((unsigned int) AT91C_PIO_PB29) // PMC Programmable Clock Output 1\r
+#define AT91C_PB29_PWM2 ((unsigned int) AT91C_PIO_PB29) // PWM Channel 2\r
+#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3\r
+#define AT91C_PB3_ETX1 ((unsigned int) AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1\r
+#define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30\r
+#define AT91C_PB30_PCK2 ((unsigned int) AT91C_PIO_PB30) // PMC Programmable Clock Output 2\r
+#define AT91C_PB30_PWM3 ((unsigned int) AT91C_PIO_PB30) // PWM Channel 3\r
+#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4\r
+#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid\r
+#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5\r
+#define AT91C_PB5_ERX0 ((unsigned int) AT91C_PIO_PB5) // Ethernet MAC Receive Data 0\r
+#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6\r
+#define AT91C_PB6_ERX1 ((unsigned int) AT91C_PIO_PB6) // Ethernet MAC Receive Data 1\r
+#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7\r
+#define AT91C_PB7_ERXER ((unsigned int) AT91C_PIO_PB7) // Ethernet MAC Receive Error\r
+#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8\r
+#define AT91C_PB8_EMDC ((unsigned int) AT91C_PIO_PB8) // Ethernet MAC Management Data Clock\r
+#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9\r
+#define AT91C_PB9_EMDIO ((unsigned int) AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output\r
+\r
+// *****************************************************************************\r
+// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256\r
+// *****************************************************************************\r
+#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ)\r
+#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral\r
+#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller A\r
+#define AT91C_ID_PIOB ((unsigned int) 3) // Parallel IO Controller B\r
+#define AT91C_ID_SPI0 ((unsigned int) 4) // Serial Peripheral Interface 0\r
+#define AT91C_ID_SPI1 ((unsigned int) 5) // Serial Peripheral Interface 1\r
+#define AT91C_ID_US0 ((unsigned int) 6) // USART 0\r
+#define AT91C_ID_US1 ((unsigned int) 7) // USART 1\r
+#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller\r
+#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface\r
+#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller\r
+#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port\r
+#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0\r
+#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1\r
+#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2\r
+#define AT91C_ID_CAN ((unsigned int) 15) // Control Area Network Controller\r
+#define AT91C_ID_EMAC ((unsigned int) 16) // Ethernet MAC\r
+#define AT91C_ID_ADC ((unsigned int) 17) // Analog-to-Digital Converter\r
+#define AT91C_ID_AES ((unsigned int) 18) // Advanced Encryption Standard 128-bit\r
+#define AT91C_ID_TDES ((unsigned int) 19) // Triple Data Encryption Standard\r
+#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved\r
+#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved\r
+#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved\r
+#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved\r
+#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved\r
+#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved\r
+#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved\r
+#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved\r
+#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved\r
+#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved\r
+#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0)\r
+#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1)\r
+\r
+// *****************************************************************************\r
+// BASE ADDRESS DEFINITIONS FOR AT91SAM7X256\r
+// *****************************************************************************\r
+#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address\r
+#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address\r
+#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address\r
+#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address\r
+#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address\r
+#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address\r
+#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address\r
+#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address\r
+#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address\r
+#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address\r
+#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address\r
+#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address\r
+#define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address\r
+#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address\r
+#define AT91C_BASE_PDC_SPI1 ((AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address\r
+#define AT91C_BASE_SPI1 ((AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address\r
+#define AT91C_BASE_PDC_SPI0 ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address\r
+#define AT91C_BASE_SPI0 ((AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address\r
+#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address\r
+#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address\r
+#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address\r
+#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address\r
+#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address\r
+#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address\r
+#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address\r
+#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address\r
+#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address\r
+#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address\r
+#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address\r
+#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address\r
+#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address\r
+#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address\r
+#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address\r
+#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address\r
+#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address\r
+#define AT91C_BASE_CAN_MB0 ((AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address\r
+#define AT91C_BASE_CAN_MB1 ((AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address\r
+#define AT91C_BASE_CAN_MB2 ((AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address\r
+#define AT91C_BASE_CAN_MB3 ((AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address\r
+#define AT91C_BASE_CAN_MB4 ((AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address\r
+#define AT91C_BASE_CAN_MB5 ((AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address\r
+#define AT91C_BASE_CAN_MB6 ((AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address\r
+#define AT91C_BASE_CAN_MB7 ((AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address\r
+#define AT91C_BASE_CAN ((AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address\r
+#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address\r
+#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address\r
+#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address\r
+#define AT91C_BASE_PDC_AES ((AT91PS_PDC) 0xFFFA4100) // (PDC_AES) Base Address\r
+#define AT91C_BASE_AES ((AT91PS_AES) 0xFFFA4000) // (AES) Base Address\r
+#define AT91C_BASE_PDC_TDES ((AT91PS_PDC) 0xFFFA8100) // (PDC_TDES) Base Address\r
+#define AT91C_BASE_TDES ((AT91PS_TDES) 0xFFFA8000) // (TDES) Base Address\r
+\r
+// *****************************************************************************\r
+// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256\r
+// *****************************************************************************\r
+#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address\r
+#define AT91C_ISRAM_SIZE ((unsigned int) 0x00010000) // Internal SRAM size in byte (64 Kbyte)\r
+#define AT91C_IFLASH ((char *) 0x00100000) // Internal ROM base address\r
+#define AT91C_IFLASH_SIZE ((unsigned int) 0x00040000) // Internal ROM size in byte (256 Kbyte)\r
+\r
+#define AT91F_AIC_ConfigureIt( irq_id, priority, src_type, newHandler ) \\r
+{ \\r
+ unsigned int mask ; \\r
+ \\r
+ mask = 0x1 << irq_id; \\r
+ /* Disable the interrupt on the interrupt controller */ \\r
+ AT91C_BASE_AIC->AIC_IDCR = mask ; \\r
+ /* Save the interrupt handler routine pointer and the interrupt priority */ \\r
+ AT91C_BASE_AIC->AIC_SVR[irq_id] = (unsigned int) newHandler ; \\r
+ /* Store the Source Mode Register */ \\r
+ AT91C_BASE_AIC->AIC_SMR[irq_id] = src_type | priority ; \\r
+ /* Clear the interrupt on the interrupt controller */ \\r
+ AT91C_BASE_AIC->AIC_ICCR = mask ; \\r
+}\r
+\r
+\r
+#endif\r
--- /dev/null
+// - ----------------------------------------------------------------------------\r
+// - ATMEL Microcontroller Software Support - ROUSSET -\r
+// - ----------------------------------------------------------------------------\r
+// - DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+// - IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+// - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+// - DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+// - INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+// - LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+// - OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+// - LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+// - NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+// - EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+// - ----------------------------------------------------------------------------\r
+// - File Name : AT91SAM7X256.h\r
+// - Object : AT91SAM7X256 definitions\r
+// - Generated : AT91 SW Application Group 05/20/2005 (16:22:29)\r
+// - \r
+// - CVS Reference : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005//\r
+// - CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005//\r
+// - CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//\r
+// - CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005//\r
+// - CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005//\r
+// - CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//\r
+// - CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//\r
+// - CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//\r
+// - CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005//\r
+// - CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004//\r
+// - CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004//\r
+// - CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004//\r
+// - CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005//\r
+// - CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005//\r
+// - CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//\r
+// - CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//\r
+// - CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//\r
+// - CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//\r
+// - CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//\r
+// - CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//\r
+// - CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005//\r
+// - CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005//\r
+// - CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//\r
+// - CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005//\r
+// - CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005//\r
+// - ----------------------------------------------------------------------------\r
+\r
+#ifndef AT91SAM7X256_H\r
+#define AT91SAM7X256_H\r
+\r
+typedef volatile unsigned int AT91_REG;// Hardware register definition\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR System Peripherals\r
+// *****************************************************************************\r
+typedef struct _AT91S_SYS {\r
+ AT91_REG AIC_SMR[32]; // Source Mode Register\r
+ AT91_REG AIC_SVR[32]; // Source Vector Register\r
+ AT91_REG AIC_IVR; // IRQ Vector Register\r
+ AT91_REG AIC_FVR; // FIQ Vector Register\r
+ AT91_REG AIC_ISR; // Interrupt Status Register\r
+ AT91_REG AIC_IPR; // Interrupt Pending Register\r
+ AT91_REG AIC_IMR; // Interrupt Mask Register\r
+ AT91_REG AIC_CISR; // Core Interrupt Status Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG AIC_IECR; // Interrupt Enable Command Register\r
+ AT91_REG AIC_IDCR; // Interrupt Disable Command Register\r
+ AT91_REG AIC_ICCR; // Interrupt Clear Command Register\r
+ AT91_REG AIC_ISCR; // Interrupt Set Command Register\r
+ AT91_REG AIC_EOICR; // End of Interrupt Command Register\r
+ AT91_REG AIC_SPU; // Spurious Vector Register\r
+ AT91_REG AIC_DCR; // Debug Control Register (Protect)\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG AIC_FFER; // Fast Forcing Enable Register\r
+ AT91_REG AIC_FFDR; // Fast Forcing Disable Register\r
+ AT91_REG AIC_FFSR; // Fast Forcing Status Register\r
+ AT91_REG Reserved2[45]; // \r
+ AT91_REG DBGU_CR; // Control Register\r
+ AT91_REG DBGU_MR; // Mode Register\r
+ AT91_REG DBGU_IER; // Interrupt Enable Register\r
+ AT91_REG DBGU_IDR; // Interrupt Disable Register\r
+ AT91_REG DBGU_IMR; // Interrupt Mask Register\r
+ AT91_REG DBGU_CSR; // Channel Status Register\r
+ AT91_REG DBGU_RHR; // Receiver Holding Register\r
+ AT91_REG DBGU_THR; // Transmitter Holding Register\r
+ AT91_REG DBGU_BRGR; // Baud Rate Generator Register\r
+ AT91_REG Reserved3[7]; // \r
+ AT91_REG DBGU_CIDR; // Chip ID Register\r
+ AT91_REG DBGU_EXID; // Chip ID Extension Register\r
+ AT91_REG DBGU_FNTR; // Force NTRST Register\r
+ AT91_REG Reserved4[45]; // \r
+ AT91_REG DBGU_RPR; // Receive Pointer Register\r
+ AT91_REG DBGU_RCR; // Receive Counter Register\r
+ AT91_REG DBGU_TPR; // Transmit Pointer Register\r
+ AT91_REG DBGU_TCR; // Transmit Counter Register\r
+ AT91_REG DBGU_RNPR; // Receive Next Pointer Register\r
+ AT91_REG DBGU_RNCR; // Receive Next Counter Register\r
+ AT91_REG DBGU_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG DBGU_TNCR; // Transmit Next Counter Register\r
+ AT91_REG DBGU_PTCR; // PDC Transfer Control Register\r
+ AT91_REG DBGU_PTSR; // PDC Transfer Status Register\r
+ AT91_REG Reserved5[54]; // \r
+ AT91_REG PIOA_PER; // PIO Enable Register\r
+ AT91_REG PIOA_PDR; // PIO Disable Register\r
+ AT91_REG PIOA_PSR; // PIO Status Register\r
+ AT91_REG Reserved6[1]; // \r
+ AT91_REG PIOA_OER; // Output Enable Register\r
+ AT91_REG PIOA_ODR; // Output Disable Registerr\r
+ AT91_REG PIOA_OSR; // Output Status Register\r
+ AT91_REG Reserved7[1]; // \r
+ AT91_REG PIOA_IFER; // Input Filter Enable Register\r
+ AT91_REG PIOA_IFDR; // Input Filter Disable Register\r
+ AT91_REG PIOA_IFSR; // Input Filter Status Register\r
+ AT91_REG Reserved8[1]; // \r
+ AT91_REG PIOA_SODR; // Set Output Data Register\r
+ AT91_REG PIOA_CODR; // Clear Output Data Register\r
+ AT91_REG PIOA_ODSR; // Output Data Status Register\r
+ AT91_REG PIOA_PDSR; // Pin Data Status Register\r
+ AT91_REG PIOA_IER; // Interrupt Enable Register\r
+ AT91_REG PIOA_IDR; // Interrupt Disable Register\r
+ AT91_REG PIOA_IMR; // Interrupt Mask Register\r
+ AT91_REG PIOA_ISR; // Interrupt Status Register\r
+ AT91_REG PIOA_MDER; // Multi-driver Enable Register\r
+ AT91_REG PIOA_MDDR; // Multi-driver Disable Register\r
+ AT91_REG PIOA_MDSR; // Multi-driver Status Register\r
+ AT91_REG Reserved9[1]; // \r
+ AT91_REG PIOA_PPUDR; // Pull-up Disable Register\r
+ AT91_REG PIOA_PPUER; // Pull-up Enable Register\r
+ AT91_REG PIOA_PPUSR; // Pull-up Status Register\r
+ AT91_REG Reserved10[1]; // \r
+ AT91_REG PIOA_ASR; // Select A Register\r
+ AT91_REG PIOA_BSR; // Select B Register\r
+ AT91_REG PIOA_ABSR; // AB Select Status Register\r
+ AT91_REG Reserved11[9]; // \r
+ AT91_REG PIOA_OWER; // Output Write Enable Register\r
+ AT91_REG PIOA_OWDR; // Output Write Disable Register\r
+ AT91_REG PIOA_OWSR; // Output Write Status Register\r
+ AT91_REG Reserved12[85]; // \r
+ AT91_REG PIOB_PER; // PIO Enable Register\r
+ AT91_REG PIOB_PDR; // PIO Disable Register\r
+ AT91_REG PIOB_PSR; // PIO Status Register\r
+ AT91_REG Reserved13[1]; // \r
+ AT91_REG PIOB_OER; // Output Enable Register\r
+ AT91_REG PIOB_ODR; // Output Disable Registerr\r
+ AT91_REG PIOB_OSR; // Output Status Register\r
+ AT91_REG Reserved14[1]; // \r
+ AT91_REG PIOB_IFER; // Input Filter Enable Register\r
+ AT91_REG PIOB_IFDR; // Input Filter Disable Register\r
+ AT91_REG PIOB_IFSR; // Input Filter Status Register\r
+ AT91_REG Reserved15[1]; // \r
+ AT91_REG PIOB_SODR; // Set Output Data Register\r
+ AT91_REG PIOB_CODR; // Clear Output Data Register\r
+ AT91_REG PIOB_ODSR; // Output Data Status Register\r
+ AT91_REG PIOB_PDSR; // Pin Data Status Register\r
+ AT91_REG PIOB_IER; // Interrupt Enable Register\r
+ AT91_REG PIOB_IDR; // Interrupt Disable Register\r
+ AT91_REG PIOB_IMR; // Interrupt Mask Register\r
+ AT91_REG PIOB_ISR; // Interrupt Status Register\r
+ AT91_REG PIOB_MDER; // Multi-driver Enable Register\r
+ AT91_REG PIOB_MDDR; // Multi-driver Disable Register\r
+ AT91_REG PIOB_MDSR; // Multi-driver Status Register\r
+ AT91_REG Reserved16[1]; // \r
+ AT91_REG PIOB_PPUDR; // Pull-up Disable Register\r
+ AT91_REG PIOB_PPUER; // Pull-up Enable Register\r
+ AT91_REG PIOB_PPUSR; // Pull-up Status Register\r
+ AT91_REG Reserved17[1]; // \r
+ AT91_REG PIOB_ASR; // Select A Register\r
+ AT91_REG PIOB_BSR; // Select B Register\r
+ AT91_REG PIOB_ABSR; // AB Select Status Register\r
+ AT91_REG Reserved18[9]; // \r
+ AT91_REG PIOB_OWER; // Output Write Enable Register\r
+ AT91_REG PIOB_OWDR; // Output Write Disable Register\r
+ AT91_REG PIOB_OWSR; // Output Write Status Register\r
+ AT91_REG Reserved19[341]; // \r
+ AT91_REG PMC_SCER; // System Clock Enable Register\r
+ AT91_REG PMC_SCDR; // System Clock Disable Register\r
+ AT91_REG PMC_SCSR; // System Clock Status Register\r
+ AT91_REG Reserved20[1]; // \r
+ AT91_REG PMC_PCER; // Peripheral Clock Enable Register\r
+ AT91_REG PMC_PCDR; // Peripheral Clock Disable Register\r
+ AT91_REG PMC_PCSR; // Peripheral Clock Status Register\r
+ AT91_REG Reserved21[1]; // \r
+ AT91_REG PMC_MOR; // Main Oscillator Register\r
+ AT91_REG PMC_MCFR; // Main Clock Frequency Register\r
+ AT91_REG Reserved22[1]; // \r
+ AT91_REG PMC_PLLR; // PLL Register\r
+ AT91_REG PMC_MCKR; // Master Clock Register\r
+ AT91_REG Reserved23[3]; // \r
+ AT91_REG PMC_PCKR[4]; // Programmable Clock Register\r
+ AT91_REG Reserved24[4]; // \r
+ AT91_REG PMC_IER; // Interrupt Enable Register\r
+ AT91_REG PMC_IDR; // Interrupt Disable Register\r
+ AT91_REG PMC_SR; // Status Register\r
+ AT91_REG PMC_IMR; // Interrupt Mask Register\r
+ AT91_REG Reserved25[36]; // \r
+ AT91_REG RSTC_RCR; // Reset Control Register\r
+ AT91_REG RSTC_RSR; // Reset Status Register\r
+ AT91_REG RSTC_RMR; // Reset Mode Register\r
+ AT91_REG Reserved26[5]; // \r
+ AT91_REG RTTC_RTMR; // Real-time Mode Register\r
+ AT91_REG RTTC_RTAR; // Real-time Alarm Register\r
+ AT91_REG RTTC_RTVR; // Real-time Value Register\r
+ AT91_REG RTTC_RTSR; // Real-time Status Register\r
+ AT91_REG PITC_PIMR; // Period Interval Mode Register\r
+ AT91_REG PITC_PISR; // Period Interval Status Register\r
+ AT91_REG PITC_PIVR; // Period Interval Value Register\r
+ AT91_REG PITC_PIIR; // Period Interval Image Register\r
+ AT91_REG WDTC_WDCR; // Watchdog Control Register\r
+ AT91_REG WDTC_WDMR; // Watchdog Mode Register\r
+ AT91_REG WDTC_WDSR; // Watchdog Status Register\r
+ AT91_REG Reserved27[5]; // \r
+ AT91_REG VREG_MR; // Voltage Regulator Mode Register\r
+} AT91S_SYS, *AT91PS_SYS;\r
+\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller\r
+// *****************************************************************************\r
+typedef struct _AT91S_AIC {\r
+ AT91_REG AIC_SMR[32]; // Source Mode Register\r
+ AT91_REG AIC_SVR[32]; // Source Vector Register\r
+ AT91_REG AIC_IVR; // IRQ Vector Register\r
+ AT91_REG AIC_FVR; // FIQ Vector Register\r
+ AT91_REG AIC_ISR; // Interrupt Status Register\r
+ AT91_REG AIC_IPR; // Interrupt Pending Register\r
+ AT91_REG AIC_IMR; // Interrupt Mask Register\r
+ AT91_REG AIC_CISR; // Core Interrupt Status Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG AIC_IECR; // Interrupt Enable Command Register\r
+ AT91_REG AIC_IDCR; // Interrupt Disable Command Register\r
+ AT91_REG AIC_ICCR; // Interrupt Clear Command Register\r
+ AT91_REG AIC_ISCR; // Interrupt Set Command Register\r
+ AT91_REG AIC_EOICR; // End of Interrupt Command Register\r
+ AT91_REG AIC_SPU; // Spurious Vector Register\r
+ AT91_REG AIC_DCR; // Debug Control Register (Protect)\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG AIC_FFER; // Fast Forcing Enable Register\r
+ AT91_REG AIC_FFDR; // Fast Forcing Disable Register\r
+ AT91_REG AIC_FFSR; // Fast Forcing Status Register\r
+} AT91S_AIC, *AT91PS_AIC;\r
+\r
+// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- \r
+#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level\r
+#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level\r
+#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level\r
+#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type\r
+#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive\r
+#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ((unsigned int) 0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive\r
+#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered\r
+#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered\r
+#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive\r
+#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered\r
+// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- \r
+#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status\r
+#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status\r
+// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- \r
+#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode\r
+#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Peripheral DMA Controller\r
+// *****************************************************************************\r
+typedef struct _AT91S_PDC {\r
+ AT91_REG PDC_RPR; // Receive Pointer Register\r
+ AT91_REG PDC_RCR; // Receive Counter Register\r
+ AT91_REG PDC_TPR; // Transmit Pointer Register\r
+ AT91_REG PDC_TCR; // Transmit Counter Register\r
+ AT91_REG PDC_RNPR; // Receive Next Pointer Register\r
+ AT91_REG PDC_RNCR; // Receive Next Counter Register\r
+ AT91_REG PDC_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG PDC_TNCR; // Transmit Next Counter Register\r
+ AT91_REG PDC_PTCR; // PDC Transfer Control Register\r
+ AT91_REG PDC_PTSR; // PDC Transfer Status Register\r
+} AT91S_PDC, *AT91PS_PDC;\r
+\r
+// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- \r
+#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable\r
+#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable\r
+#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable\r
+#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable\r
+// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Debug Unit\r
+// *****************************************************************************\r
+typedef struct _AT91S_DBGU {\r
+ AT91_REG DBGU_CR; // Control Register\r
+ AT91_REG DBGU_MR; // Mode Register\r
+ AT91_REG DBGU_IER; // Interrupt Enable Register\r
+ AT91_REG DBGU_IDR; // Interrupt Disable Register\r
+ AT91_REG DBGU_IMR; // Interrupt Mask Register\r
+ AT91_REG DBGU_CSR; // Channel Status Register\r
+ AT91_REG DBGU_RHR; // Receiver Holding Register\r
+ AT91_REG DBGU_THR; // Transmitter Holding Register\r
+ AT91_REG DBGU_BRGR; // Baud Rate Generator Register\r
+ AT91_REG Reserved0[7]; // \r
+ AT91_REG DBGU_CIDR; // Chip ID Register\r
+ AT91_REG DBGU_EXID; // Chip ID Extension Register\r
+ AT91_REG DBGU_FNTR; // Force NTRST Register\r
+ AT91_REG Reserved1[45]; // \r
+ AT91_REG DBGU_RPR; // Receive Pointer Register\r
+ AT91_REG DBGU_RCR; // Receive Counter Register\r
+ AT91_REG DBGU_TPR; // Transmit Pointer Register\r
+ AT91_REG DBGU_TCR; // Transmit Counter Register\r
+ AT91_REG DBGU_RNPR; // Receive Next Pointer Register\r
+ AT91_REG DBGU_RNCR; // Receive Next Counter Register\r
+ AT91_REG DBGU_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG DBGU_TNCR; // Transmit Next Counter Register\r
+ AT91_REG DBGU_PTCR; // PDC Transfer Control Register\r
+ AT91_REG DBGU_PTSR; // PDC Transfer Status Register\r
+} AT91S_DBGU, *AT91PS_DBGU;\r
+\r
+// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- \r
+#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver\r
+#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter\r
+#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable\r
+#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable\r
+#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable\r
+#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable\r
+#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits\r
+// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- \r
+#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type\r
+#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity\r
+#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity\r
+#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space)\r
+#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark)\r
+#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity\r
+#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode\r
+#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode\r
+#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.\r
+#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.\r
+#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.\r
+#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.\r
+// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- \r
+#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt\r
+#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt\r
+#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt\r
+#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt\r
+#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt\r
+#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt\r
+#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt\r
+#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt\r
+#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt\r
+#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt\r
+#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt\r
+#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt\r
+// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- \r
+// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- \r
+// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- \r
+// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- \r
+#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Parallel Input Output Controler\r
+// *****************************************************************************\r
+typedef struct _AT91S_PIO {\r
+ AT91_REG PIO_PER; // PIO Enable Register\r
+ AT91_REG PIO_PDR; // PIO Disable Register\r
+ AT91_REG PIO_PSR; // PIO Status Register\r
+ AT91_REG Reserved0[1]; // \r
+ AT91_REG PIO_OER; // Output Enable Register\r
+ AT91_REG PIO_ODR; // Output Disable Registerr\r
+ AT91_REG PIO_OSR; // Output Status Register\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG PIO_IFER; // Input Filter Enable Register\r
+ AT91_REG PIO_IFDR; // Input Filter Disable Register\r
+ AT91_REG PIO_IFSR; // Input Filter Status Register\r
+ AT91_REG Reserved2[1]; // \r
+ AT91_REG PIO_SODR; // Set Output Data Register\r
+ AT91_REG PIO_CODR; // Clear Output Data Register\r
+ AT91_REG PIO_ODSR; // Output Data Status Register\r
+ AT91_REG PIO_PDSR; // Pin Data Status Register\r
+ AT91_REG PIO_IER; // Interrupt Enable Register\r
+ AT91_REG PIO_IDR; // Interrupt Disable Register\r
+ AT91_REG PIO_IMR; // Interrupt Mask Register\r
+ AT91_REG PIO_ISR; // Interrupt Status Register\r
+ AT91_REG PIO_MDER; // Multi-driver Enable Register\r
+ AT91_REG PIO_MDDR; // Multi-driver Disable Register\r
+ AT91_REG PIO_MDSR; // Multi-driver Status Register\r
+ AT91_REG Reserved3[1]; // \r
+ AT91_REG PIO_PPUDR; // Pull-up Disable Register\r
+ AT91_REG PIO_PPUER; // Pull-up Enable Register\r
+ AT91_REG PIO_PPUSR; // Pull-up Status Register\r
+ AT91_REG Reserved4[1]; // \r
+ AT91_REG PIO_ASR; // Select A Register\r
+ AT91_REG PIO_BSR; // Select B Register\r
+ AT91_REG PIO_ABSR; // AB Select Status Register\r
+ AT91_REG Reserved5[9]; // \r
+ AT91_REG PIO_OWER; // Output Write Enable Register\r
+ AT91_REG PIO_OWDR; // Output Write Disable Register\r
+ AT91_REG PIO_OWSR; // Output Write Status Register\r
+} AT91S_PIO, *AT91PS_PIO;\r
+\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Clock Generator Controler\r
+// *****************************************************************************\r
+typedef struct _AT91S_CKGR {\r
+ AT91_REG CKGR_MOR; // Main Oscillator Register\r
+ AT91_REG CKGR_MCFR; // Main Clock Frequency Register\r
+ AT91_REG Reserved0[1]; // \r
+ AT91_REG CKGR_PLLR; // PLL Register\r
+} AT91S_CKGR, *AT91PS_CKGR;\r
+\r
+// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- \r
+#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable\r
+#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass\r
+#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time\r
+// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- \r
+#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency\r
+#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready\r
+// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- \r
+#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected\r
+#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0\r
+#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed\r
+#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter\r
+#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range\r
+#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet\r
+#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet\r
+#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet\r
+#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet\r
+#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier\r
+#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks\r
+#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output\r
+#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2\r
+#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Power Management Controler\r
+// *****************************************************************************\r
+typedef struct _AT91S_PMC {\r
+ AT91_REG PMC_SCER; // System Clock Enable Register\r
+ AT91_REG PMC_SCDR; // System Clock Disable Register\r
+ AT91_REG PMC_SCSR; // System Clock Status Register\r
+ AT91_REG Reserved0[1]; // \r
+ AT91_REG PMC_PCER; // Peripheral Clock Enable Register\r
+ AT91_REG PMC_PCDR; // Peripheral Clock Disable Register\r
+ AT91_REG PMC_PCSR; // Peripheral Clock Status Register\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG PMC_MOR; // Main Oscillator Register\r
+ AT91_REG PMC_MCFR; // Main Clock Frequency Register\r
+ AT91_REG Reserved2[1]; // \r
+ AT91_REG PMC_PLLR; // PLL Register\r
+ AT91_REG PMC_MCKR; // Master Clock Register\r
+ AT91_REG Reserved3[3]; // \r
+ AT91_REG PMC_PCKR[4]; // Programmable Clock Register\r
+ AT91_REG Reserved4[4]; // \r
+ AT91_REG PMC_IER; // Interrupt Enable Register\r
+ AT91_REG PMC_IDR; // Interrupt Disable Register\r
+ AT91_REG PMC_SR; // Status Register\r
+ AT91_REG PMC_IMR; // Interrupt Mask Register\r
+} AT91S_PMC, *AT91PS_PMC;\r
+\r
+// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- \r
+#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock\r
+#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock\r
+#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output\r
+#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output\r
+#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output\r
+#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output\r
+// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- \r
+// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- \r
+// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- \r
+// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- \r
+// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- \r
+// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- \r
+#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection\r
+#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected\r
+#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected\r
+#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected\r
+#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler\r
+#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock\r
+#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2\r
+#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4\r
+#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8\r
+#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16\r
+#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32\r
+#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64\r
+// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- \r
+// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- \r
+#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask\r
+#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask\r
+#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask\r
+// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- \r
+// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- \r
+// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Reset Controller Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_RSTC {\r
+ AT91_REG RSTC_RCR; // Reset Control Register\r
+ AT91_REG RSTC_RSR; // Reset Status Register\r
+ AT91_REG RSTC_RMR; // Reset Mode Register\r
+} AT91S_RSTC, *AT91PS_RSTC;\r
+\r
+// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- \r
+#define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset\r
+#define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset\r
+#define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset\r
+#define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password\r
+// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- \r
+#define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status\r
+#define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status\r
+#define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type\r
+#define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising.\r
+#define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising.\r
+#define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.\r
+#define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.\r
+#define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low.\r
+#define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured.\r
+#define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level\r
+#define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress.\r
+// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- \r
+#define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable\r
+#define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable\r
+#define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable\r
+#define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_RTTC {\r
+ AT91_REG RTTC_RTMR; // Real-time Mode Register\r
+ AT91_REG RTTC_RTAR; // Real-time Alarm Register\r
+ AT91_REG RTTC_RTVR; // Real-time Value Register\r
+ AT91_REG RTTC_RTSR; // Real-time Status Register\r
+} AT91S_RTTC, *AT91PS_RTTC;\r
+\r
+// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- \r
+#define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value\r
+#define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable\r
+#define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable\r
+#define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart\r
+// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- \r
+#define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value\r
+// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- \r
+#define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value\r
+// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- \r
+#define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status\r
+#define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_PITC {\r
+ AT91_REG PITC_PIMR; // Period Interval Mode Register\r
+ AT91_REG PITC_PISR; // Period Interval Status Register\r
+ AT91_REG PITC_PIVR; // Period Interval Value Register\r
+ AT91_REG PITC_PIIR; // Period Interval Image Register\r
+} AT91S_PITC, *AT91PS_PITC;\r
+\r
+// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- \r
+#define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value\r
+#define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled\r
+#define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable\r
+// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- \r
+#define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status\r
+// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- \r
+#define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value\r
+#define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter\r
+// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_WDTC {\r
+ AT91_REG WDTC_WDCR; // Watchdog Control Register\r
+ AT91_REG WDTC_WDMR; // Watchdog Mode Register\r
+ AT91_REG WDTC_WDSR; // Watchdog Status Register\r
+} AT91S_WDTC, *AT91PS_WDTC;\r
+\r
+// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- \r
+#define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart\r
+#define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password\r
+// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- \r
+#define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart\r
+#define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable\r
+#define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable\r
+#define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart\r
+#define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable\r
+#define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value\r
+#define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt\r
+#define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt\r
+// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- \r
+#define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow\r
+#define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_VREG {\r
+ AT91_REG VREG_MR; // Voltage Regulator Mode Register\r
+} AT91S_VREG, *AT91PS_VREG;\r
+\r
+// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- \r
+#define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Memory Controller Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_MC {\r
+ AT91_REG MC_RCR; // MC Remap Control Register\r
+ AT91_REG MC_ASR; // MC Abort Status Register\r
+ AT91_REG MC_AASR; // MC Abort Address Status Register\r
+ AT91_REG Reserved0[21]; // \r
+ AT91_REG MC_FMR; // MC Flash Mode Register\r
+ AT91_REG MC_FCR; // MC Flash Command Register\r
+ AT91_REG MC_FSR; // MC Flash Status Register\r
+} AT91S_MC, *AT91PS_MC;\r
+\r
+// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- \r
+#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit\r
+// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- \r
+#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status\r
+#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status\r
+#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status\r
+#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte\r
+#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word\r
+#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word\r
+#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status\r
+#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read\r
+#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write\r
+#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch\r
+#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source\r
+#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source\r
+#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source\r
+#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source\r
+// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- \r
+#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready\r
+#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error\r
+#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error\r
+#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming\r
+#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State\r
+#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations\r
+#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations\r
+#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations\r
+#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations\r
+#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number\r
+// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- \r
+#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command\r
+#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN.\r
+#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.\r
+#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.\r
+#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.\r
+#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.\r
+#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits.\r
+#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits.\r
+#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit.\r
+#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number\r
+#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key\r
+// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- \r
+#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status\r
+#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status\r
+#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status\r
+#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status\r
+#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status\r
+#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status\r
+#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status\r
+#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status\r
+#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status\r
+#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status\r
+#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status\r
+#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status\r
+#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status\r
+#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status\r
+#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status\r
+#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status\r
+#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status\r
+#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status\r
+#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status\r
+#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status\r
+#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status\r
+#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status\r
+#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status\r
+#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status\r
+#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Serial Parallel Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_SPI {\r
+ AT91_REG SPI_CR; // Control Register\r
+ AT91_REG SPI_MR; // Mode Register\r
+ AT91_REG SPI_RDR; // Receive Data Register\r
+ AT91_REG SPI_TDR; // Transmit Data Register\r
+ AT91_REG SPI_SR; // Status Register\r
+ AT91_REG SPI_IER; // Interrupt Enable Register\r
+ AT91_REG SPI_IDR; // Interrupt Disable Register\r
+ AT91_REG SPI_IMR; // Interrupt Mask Register\r
+ AT91_REG Reserved0[4]; // \r
+ AT91_REG SPI_CSR[4]; // Chip Select Register\r
+ AT91_REG Reserved1[48]; // \r
+ AT91_REG SPI_RPR; // Receive Pointer Register\r
+ AT91_REG SPI_RCR; // Receive Counter Register\r
+ AT91_REG SPI_TPR; // Transmit Pointer Register\r
+ AT91_REG SPI_TCR; // Transmit Counter Register\r
+ AT91_REG SPI_RNPR; // Receive Next Pointer Register\r
+ AT91_REG SPI_RNCR; // Receive Next Counter Register\r
+ AT91_REG SPI_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG SPI_TNCR; // Transmit Next Counter Register\r
+ AT91_REG SPI_PTCR; // PDC Transfer Control Register\r
+ AT91_REG SPI_PTSR; // PDC Transfer Status Register\r
+} AT91S_SPI, *AT91PS_SPI;\r
+\r
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- \r
+#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable\r
+#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable\r
+#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset\r
+#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer\r
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- \r
+#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode\r
+#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select\r
+#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select\r
+#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select\r
+#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode\r
+#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection\r
+#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection\r
+#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection\r
+#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select\r
+#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects\r
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- \r
+#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data\r
+#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status\r
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- \r
+#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data\r
+#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status\r
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- \r
+#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full\r
+#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty\r
+#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error\r
+#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status\r
+#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer\r
+#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer\r
+#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt\r
+#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt\r
+#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt\r
+#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt\r
+#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status\r
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- \r
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- \r
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- \r
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- \r
+#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity\r
+#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase\r
+#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer\r
+#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer\r
+#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer\r
+#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer\r
+#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer\r
+#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer\r
+#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer\r
+#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer\r
+#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer\r
+#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer\r
+#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer\r
+#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate\r
+#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK\r
+#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Usart\r
+// *****************************************************************************\r
+typedef struct _AT91S_USART {\r
+ AT91_REG US_CR; // Control Register\r
+ AT91_REG US_MR; // Mode Register\r
+ AT91_REG US_IER; // Interrupt Enable Register\r
+ AT91_REG US_IDR; // Interrupt Disable Register\r
+ AT91_REG US_IMR; // Interrupt Mask Register\r
+ AT91_REG US_CSR; // Channel Status Register\r
+ AT91_REG US_RHR; // Receiver Holding Register\r
+ AT91_REG US_THR; // Transmitter Holding Register\r
+ AT91_REG US_BRGR; // Baud Rate Generator Register\r
+ AT91_REG US_RTOR; // Receiver Time-out Register\r
+ AT91_REG US_TTGR; // Transmitter Time-guard Register\r
+ AT91_REG Reserved0[5]; // \r
+ AT91_REG US_FIDI; // FI_DI_Ratio Register\r
+ AT91_REG US_NER; // Nb Errors Register\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG US_IF; // IRDA_FILTER Register\r
+ AT91_REG Reserved2[44]; // \r
+ AT91_REG US_RPR; // Receive Pointer Register\r
+ AT91_REG US_RCR; // Receive Counter Register\r
+ AT91_REG US_TPR; // Transmit Pointer Register\r
+ AT91_REG US_TCR; // Transmit Counter Register\r
+ AT91_REG US_RNPR; // Receive Next Pointer Register\r
+ AT91_REG US_RNCR; // Receive Next Counter Register\r
+ AT91_REG US_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG US_TNCR; // Transmit Next Counter Register\r
+ AT91_REG US_PTCR; // PDC Transfer Control Register\r
+ AT91_REG US_PTSR; // PDC Transfer Status Register\r
+} AT91S_USART, *AT91PS_USART;\r
+\r
+// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- \r
+#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break\r
+#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break\r
+#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out\r
+#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address\r
+#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations\r
+#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge\r
+#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out\r
+#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable\r
+#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable\r
+#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable\r
+#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable\r
+// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- \r
+#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode\r
+#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal\r
+#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485\r
+#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking\r
+#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem\r
+#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0\r
+#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1\r
+#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA\r
+#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking\r
+#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock\r
+#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock\r
+#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1\r
+#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM)\r
+#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK)\r
+#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock\r
+#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits\r
+#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits\r
+#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits\r
+#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits\r
+#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select\r
+#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits\r
+#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit\r
+#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits\r
+#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits\r
+#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order\r
+#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length\r
+#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select\r
+#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode\r
+#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge\r
+#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK\r
+#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions\r
+#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter\r
+// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- \r
+#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break\r
+#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out\r
+#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached\r
+#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge\r
+#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag\r
+#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag\r
+#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag\r
+#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag\r
+// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- \r
+// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- \r
+// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- \r
+#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input\r
+#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input\r
+#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input\r
+#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_SSC {\r
+ AT91_REG SSC_CR; // Control Register\r
+ AT91_REG SSC_CMR; // Clock Mode Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG SSC_RCMR; // Receive Clock ModeRegister\r
+ AT91_REG SSC_RFMR; // Receive Frame Mode Register\r
+ AT91_REG SSC_TCMR; // Transmit Clock Mode Register\r
+ AT91_REG SSC_TFMR; // Transmit Frame Mode Register\r
+ AT91_REG SSC_RHR; // Receive Holding Register\r
+ AT91_REG SSC_THR; // Transmit Holding Register\r
+ AT91_REG Reserved1[2]; // \r
+ AT91_REG SSC_RSHR; // Receive Sync Holding Register\r
+ AT91_REG SSC_TSHR; // Transmit Sync Holding Register\r
+ AT91_REG Reserved2[2]; // \r
+ AT91_REG SSC_SR; // Status Register\r
+ AT91_REG SSC_IER; // Interrupt Enable Register\r
+ AT91_REG SSC_IDR; // Interrupt Disable Register\r
+ AT91_REG SSC_IMR; // Interrupt Mask Register\r
+ AT91_REG Reserved3[44]; // \r
+ AT91_REG SSC_RPR; // Receive Pointer Register\r
+ AT91_REG SSC_RCR; // Receive Counter Register\r
+ AT91_REG SSC_TPR; // Transmit Pointer Register\r
+ AT91_REG SSC_TCR; // Transmit Counter Register\r
+ AT91_REG SSC_RNPR; // Receive Next Pointer Register\r
+ AT91_REG SSC_RNCR; // Receive Next Counter Register\r
+ AT91_REG SSC_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG SSC_TNCR; // Transmit Next Counter Register\r
+ AT91_REG SSC_PTCR; // PDC Transfer Control Register\r
+ AT91_REG SSC_PTSR; // PDC Transfer Status Register\r
+} AT91S_SSC, *AT91PS_SSC;\r
+\r
+// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- \r
+#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable\r
+#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable\r
+#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable\r
+#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable\r
+#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset\r
+// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- \r
+#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection\r
+#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock\r
+#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal\r
+#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin\r
+#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection\r
+#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only\r
+#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output\r
+#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output\r
+#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion\r
+#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection\r
+#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.\r
+#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start\r
+#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input\r
+#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input\r
+#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input\r
+#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input\r
+#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input\r
+#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input\r
+#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0\r
+#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay\r
+#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection\r
+// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- \r
+#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length\r
+#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode\r
+#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First\r
+#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame\r
+#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length\r
+#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection\r
+#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only\r
+#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse\r
+#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse\r
+#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer\r
+#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer\r
+#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer\r
+#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection\r
+// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- \r
+// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- \r
+#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value\r
+#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable\r
+// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- \r
+#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready\r
+#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty\r
+#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission\r
+#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty\r
+#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready\r
+#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun\r
+#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception\r
+#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full\r
+#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync\r
+#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync\r
+#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable\r
+#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable\r
+// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- \r
+// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- \r
+// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Two-wire Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_TWI {\r
+ AT91_REG TWI_CR; // Control Register\r
+ AT91_REG TWI_MMR; // Master Mode Register\r
+ AT91_REG Reserved0[1]; // \r
+ AT91_REG TWI_IADR; // Internal Address Register\r
+ AT91_REG TWI_CWGR; // Clock Waveform Generator Register\r
+ AT91_REG Reserved1[3]; // \r
+ AT91_REG TWI_SR; // Status Register\r
+ AT91_REG TWI_IER; // Interrupt Enable Register\r
+ AT91_REG TWI_IDR; // Interrupt Disable Register\r
+ AT91_REG TWI_IMR; // Interrupt Mask Register\r
+ AT91_REG TWI_RHR; // Receive Holding Register\r
+ AT91_REG TWI_THR; // Transmit Holding Register\r
+} AT91S_TWI, *AT91PS_TWI;\r
+\r
+// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- \r
+#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition\r
+#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition\r
+#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled\r
+#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled\r
+#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset\r
+// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- \r
+#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size\r
+#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address\r
+#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address\r
+#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address\r
+#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address\r
+#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction\r
+#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address\r
+// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- \r
+#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider\r
+#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider\r
+#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider\r
+// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- \r
+#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed\r
+#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY\r
+#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY\r
+#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error\r
+#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error\r
+#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged\r
+// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- \r
+// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- \r
+// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR PWMC Channel Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_PWMC_CH {\r
+ AT91_REG PWMC_CMR; // Channel Mode Register\r
+ AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register\r
+ AT91_REG PWMC_CPRDR; // Channel Period Register\r
+ AT91_REG PWMC_CCNTR; // Channel Counter Register\r
+ AT91_REG PWMC_CUPDR; // Channel Update Register\r
+ AT91_REG PWMC_Reserved[3]; // Reserved\r
+} AT91S_PWMC_CH, *AT91PS_PWMC_CH;\r
+\r
+// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- \r
+#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx\r
+#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH) \r
+#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH) \r
+#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH) \r
+#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment\r
+#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity\r
+#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period\r
+// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- \r
+#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle\r
+// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- \r
+#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period\r
+// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- \r
+#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter\r
+// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- \r
+#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_PWMC {\r
+ AT91_REG PWMC_MR; // PWMC Mode Register\r
+ AT91_REG PWMC_ENA; // PWMC Enable Register\r
+ AT91_REG PWMC_DIS; // PWMC Disable Register\r
+ AT91_REG PWMC_SR; // PWMC Status Register\r
+ AT91_REG PWMC_IER; // PWMC Interrupt Enable Register\r
+ AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register\r
+ AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register\r
+ AT91_REG PWMC_ISR; // PWMC Interrupt Status Register\r
+ AT91_REG Reserved0[55]; // \r
+ AT91_REG PWMC_VR; // PWMC Version Register\r
+ AT91_REG Reserved1[64]; // \r
+ AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel\r
+} AT91S_PWMC, *AT91PS_PWMC;\r
+\r
+// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- \r
+#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor.\r
+#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A\r
+#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC) \r
+#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor.\r
+#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B\r
+#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC) \r
+// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- \r
+#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0\r
+#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1\r
+#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2\r
+#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3\r
+// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- \r
+// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- \r
+// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- \r
+// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- \r
+// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- \r
+// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR USB Device Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_UDP {\r
+ AT91_REG UDP_NUM; // Frame Number Register\r
+ AT91_REG UDP_GLBSTATE; // Global State Register\r
+ AT91_REG UDP_FADDR; // Function Address Register\r
+ AT91_REG Reserved0[1]; // \r
+ AT91_REG UDP_IER; // Interrupt Enable Register\r
+ AT91_REG UDP_IDR; // Interrupt Disable Register\r
+ AT91_REG UDP_IMR; // Interrupt Mask Register\r
+ AT91_REG UDP_ISR; // Interrupt Status Register\r
+ AT91_REG UDP_ICR; // Interrupt Clear Register\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG UDP_RSTEP; // Reset Endpoint Register\r
+ AT91_REG Reserved2[1]; // \r
+ AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register\r
+ AT91_REG Reserved3[2]; // \r
+ AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register\r
+ AT91_REG Reserved4[3]; // \r
+ AT91_REG UDP_TXVC; // Transceiver Control Register\r
+} AT91S_UDP, *AT91PS_UDP;\r
+\r
+// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- \r
+#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats\r
+#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error\r
+#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK\r
+// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- \r
+#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable\r
+#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured\r
+#define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume\r
+#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host\r
+#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable\r
+// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- \r
+#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value\r
+#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable\r
+// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- \r
+#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt\r
+#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt\r
+#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt\r
+#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt\r
+#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt\r
+#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt\r
+#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt\r
+#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt\r
+#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt\r
+#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt\r
+#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt\r
+// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- \r
+// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- \r
+// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- \r
+#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt\r
+// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- \r
+// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- \r
+#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0\r
+#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1\r
+#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2\r
+#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3\r
+#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4\r
+#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5\r
+// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- \r
+#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR\r
+#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0\r
+#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)\r
+#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)\r
+#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready\r
+#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).\r
+#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).\r
+#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction\r
+#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type\r
+#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control\r
+#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT\r
+#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT\r
+#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT\r
+#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN\r
+#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN\r
+#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN\r
+#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle\r
+#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable\r
+#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO\r
+// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- \r
+#define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP) \r
+#define AT91C_UDP_PUON ((unsigned int) 0x1 << 9) // (UDP) Pull-up ON\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_TC {\r
+ AT91_REG TC_CCR; // Channel Control Register\r
+ AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode)\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG TC_CV; // Counter Value\r
+ AT91_REG TC_RA; // Register A\r
+ AT91_REG TC_RB; // Register B\r
+ AT91_REG TC_RC; // Register C\r
+ AT91_REG TC_SR; // Status Register\r
+ AT91_REG TC_IER; // Interrupt Enable Register\r
+ AT91_REG TC_IDR; // Interrupt Disable Register\r
+ AT91_REG TC_IMR; // Interrupt Mask Register\r
+} AT91S_TC, *AT91PS_TC;\r
+\r
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- \r
+#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command\r
+#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command\r
+#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command\r
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- \r
+#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection\r
+#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK\r
+#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK\r
+#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK\r
+#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK\r
+#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK\r
+#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0\r
+#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1\r
+#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2\r
+#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert\r
+#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection\r
+#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal\r
+#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock\r
+#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock\r
+#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock\r
+#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare\r
+#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading\r
+#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare\r
+#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading\r
+#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection\r
+#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None\r
+#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge\r
+#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge\r
+#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge\r
+#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection\r
+#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None\r
+#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge\r
+#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge\r
+#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge\r
+#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection\r
+#define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input\r
+#define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output\r
+#define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output\r
+#define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output\r
+#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection\r
+#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable\r
+#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection\r
+#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare\r
+#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare\r
+#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare\r
+#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare\r
+#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable\r
+#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) \r
+#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA\r
+#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none\r
+#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set\r
+#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear\r
+#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle\r
+#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection\r
+#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None\r
+#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA\r
+#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA\r
+#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA\r
+#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA\r
+#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none\r
+#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set\r
+#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear\r
+#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle\r
+#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection\r
+#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None\r
+#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA\r
+#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA\r
+#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA\r
+#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA\r
+#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none\r
+#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set\r
+#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear\r
+#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle\r
+#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA\r
+#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none\r
+#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set\r
+#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear\r
+#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle\r
+#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB\r
+#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none\r
+#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set\r
+#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear\r
+#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle\r
+#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB\r
+#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none\r
+#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set\r
+#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear\r
+#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle\r
+#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB\r
+#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none\r
+#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set\r
+#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear\r
+#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle\r
+#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB\r
+#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none\r
+#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set\r
+#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear\r
+#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle\r
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- \r
+#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow\r
+#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun\r
+#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare\r
+#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare\r
+#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare\r
+#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading\r
+#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading\r
+#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger\r
+#define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling\r
+#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror\r
+#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror\r
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- \r
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- \r
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Timer Counter Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_TCB {\r
+ AT91S_TC TCB_TC0; // TC Channel 0\r
+ AT91_REG Reserved0[4]; // \r
+ AT91S_TC TCB_TC1; // TC Channel 1\r
+ AT91_REG Reserved1[4]; // \r
+ AT91S_TC TCB_TC2; // TC Channel 2\r
+ AT91_REG Reserved2[4]; // \r
+ AT91_REG TCB_BCR; // TC Block Control Register\r
+ AT91_REG TCB_BMR; // TC Block Mode Register\r
+} AT91S_TCB, *AT91PS_TCB;\r
+\r
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- \r
+#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command\r
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- \r
+#define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection\r
+#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0\r
+#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0\r
+#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0\r
+#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0\r
+#define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection\r
+#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1\r
+#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1\r
+#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1\r
+#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1\r
+#define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection\r
+#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2\r
+#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2\r
+#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2\r
+#define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_CAN_MB {\r
+ AT91_REG CAN_MB_MMR; // MailBox Mode Register\r
+ AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register\r
+ AT91_REG CAN_MB_MID; // MailBox ID Register\r
+ AT91_REG CAN_MB_MFID; // MailBox Family ID Register\r
+ AT91_REG CAN_MB_MSR; // MailBox Status Register\r
+ AT91_REG CAN_MB_MDL; // MailBox Data Low Register\r
+ AT91_REG CAN_MB_MDH; // MailBox Data High Register\r
+ AT91_REG CAN_MB_MCR; // MailBox Control Register\r
+} AT91S_CAN_MB, *AT91PS_CAN_MB;\r
+\r
+// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- \r
+#define AT91C_CAN_MTIMEMARK ((unsigned int) 0xFFFF << 0) // (CAN_MB) Mailbox Timemark\r
+#define AT91C_CAN_PRIOR ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority\r
+#define AT91C_CAN_MOT ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type\r
+#define AT91C_CAN_MOT_DIS ((unsigned int) 0x0 << 24) // (CAN_MB) \r
+#define AT91C_CAN_MOT_RX ((unsigned int) 0x1 << 24) // (CAN_MB) \r
+#define AT91C_CAN_MOT_RXOVERWRITE ((unsigned int) 0x2 << 24) // (CAN_MB) \r
+#define AT91C_CAN_MOT_TX ((unsigned int) 0x3 << 24) // (CAN_MB) \r
+#define AT91C_CAN_MOT_CONSUMER ((unsigned int) 0x4 << 24) // (CAN_MB) \r
+#define AT91C_CAN_MOT_PRODUCER ((unsigned int) 0x5 << 24) // (CAN_MB) \r
+// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- \r
+#define AT91C_CAN_MIDvB ((unsigned int) 0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode\r
+#define AT91C_CAN_MIDvA ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode\r
+#define AT91C_CAN_MIDE ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version\r
+// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- \r
+// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- \r
+// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- \r
+#define AT91C_CAN_MTIMESTAMP ((unsigned int) 0xFFFF << 0) // (CAN_MB) Timer Value\r
+#define AT91C_CAN_MDLC ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code\r
+#define AT91C_CAN_MRTR ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request\r
+#define AT91C_CAN_MABT ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort\r
+#define AT91C_CAN_MRDY ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready\r
+#define AT91C_CAN_MMI ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored\r
+// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- \r
+// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- \r
+// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- \r
+#define AT91C_CAN_MACR ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox\r
+#define AT91C_CAN_MTCR ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Control Area Network Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_CAN {\r
+ AT91_REG CAN_MR; // Mode Register\r
+ AT91_REG CAN_IER; // Interrupt Enable Register\r
+ AT91_REG CAN_IDR; // Interrupt Disable Register\r
+ AT91_REG CAN_IMR; // Interrupt Mask Register\r
+ AT91_REG CAN_SR; // Status Register\r
+ AT91_REG CAN_BR; // Baudrate Register\r
+ AT91_REG CAN_TIM; // Timer Register\r
+ AT91_REG CAN_TIMESTP; // Time Stamp Register\r
+ AT91_REG CAN_ECR; // Error Counter Register\r
+ AT91_REG CAN_TCR; // Transfer Command Register\r
+ AT91_REG CAN_ACR; // Abort Command Register\r
+ AT91_REG Reserved0[52]; // \r
+ AT91_REG CAN_VR; // Version Register\r
+ AT91_REG Reserved1[64]; // \r
+ AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0\r
+ AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1\r
+ AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2\r
+ AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3\r
+ AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4\r
+ AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5\r
+ AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6\r
+ AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7\r
+ AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8\r
+ AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9\r
+ AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10\r
+ AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11\r
+ AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12\r
+ AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13\r
+ AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14\r
+ AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15\r
+} AT91S_CAN, *AT91PS_CAN;\r
+\r
+// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- \r
+#define AT91C_CAN_CANEN ((unsigned int) 0x1 << 0) // (CAN) CAN Controller Enable\r
+#define AT91C_CAN_LPM ((unsigned int) 0x1 << 1) // (CAN) Disable/Enable Low Power Mode\r
+#define AT91C_CAN_ABM ((unsigned int) 0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode\r
+#define AT91C_CAN_OVL ((unsigned int) 0x1 << 3) // (CAN) Disable/Enable Overload Frame\r
+#define AT91C_CAN_TEOF ((unsigned int) 0x1 << 4) // (CAN) Time Stamp messages at each end of Frame\r
+#define AT91C_CAN_TTM ((unsigned int) 0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode\r
+#define AT91C_CAN_TIMFRZ ((unsigned int) 0x1 << 6) // (CAN) Enable Timer Freeze\r
+#define AT91C_CAN_DRPT ((unsigned int) 0x1 << 7) // (CAN) Disable Repeat\r
+// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- \r
+#define AT91C_CAN_MB0 ((unsigned int) 0x1 << 0) // (CAN) Mailbox 0 Flag\r
+#define AT91C_CAN_MB1 ((unsigned int) 0x1 << 1) // (CAN) Mailbox 1 Flag\r
+#define AT91C_CAN_MB2 ((unsigned int) 0x1 << 2) // (CAN) Mailbox 2 Flag\r
+#define AT91C_CAN_MB3 ((unsigned int) 0x1 << 3) // (CAN) Mailbox 3 Flag\r
+#define AT91C_CAN_MB4 ((unsigned int) 0x1 << 4) // (CAN) Mailbox 4 Flag\r
+#define AT91C_CAN_MB5 ((unsigned int) 0x1 << 5) // (CAN) Mailbox 5 Flag\r
+#define AT91C_CAN_MB6 ((unsigned int) 0x1 << 6) // (CAN) Mailbox 6 Flag\r
+#define AT91C_CAN_MB7 ((unsigned int) 0x1 << 7) // (CAN) Mailbox 7 Flag\r
+#define AT91C_CAN_MB8 ((unsigned int) 0x1 << 8) // (CAN) Mailbox 8 Flag\r
+#define AT91C_CAN_MB9 ((unsigned int) 0x1 << 9) // (CAN) Mailbox 9 Flag\r
+#define AT91C_CAN_MB10 ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag\r
+#define AT91C_CAN_MB11 ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag\r
+#define AT91C_CAN_MB12 ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag\r
+#define AT91C_CAN_MB13 ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag\r
+#define AT91C_CAN_MB14 ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag\r
+#define AT91C_CAN_MB15 ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag\r
+#define AT91C_CAN_ERRA ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag\r
+#define AT91C_CAN_WARN ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag\r
+#define AT91C_CAN_ERRP ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag\r
+#define AT91C_CAN_BOFF ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag\r
+#define AT91C_CAN_SLEEP ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag\r
+#define AT91C_CAN_WAKEUP ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag\r
+#define AT91C_CAN_TOVF ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag\r
+#define AT91C_CAN_TSTP ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag\r
+#define AT91C_CAN_CERR ((unsigned int) 0x1 << 24) // (CAN) CRC Error\r
+#define AT91C_CAN_SERR ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error\r
+#define AT91C_CAN_AERR ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error\r
+#define AT91C_CAN_FERR ((unsigned int) 0x1 << 27) // (CAN) Form Error\r
+#define AT91C_CAN_BERR ((unsigned int) 0x1 << 28) // (CAN) Bit Error\r
+// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- \r
+// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- \r
+// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- \r
+#define AT91C_CAN_RBSY ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy\r
+#define AT91C_CAN_TBSY ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy\r
+#define AT91C_CAN_OVLY ((unsigned int) 0x1 << 31) // (CAN) Overload Busy\r
+// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- \r
+#define AT91C_CAN_PHASE2 ((unsigned int) 0x7 << 0) // (CAN) Phase 2 segment\r
+#define AT91C_CAN_PHASE1 ((unsigned int) 0x7 << 4) // (CAN) Phase 1 segment\r
+#define AT91C_CAN_PROPAG ((unsigned int) 0x7 << 8) // (CAN) Programmation time segment\r
+#define AT91C_CAN_SYNC ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment\r
+#define AT91C_CAN_BRP ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler\r
+#define AT91C_CAN_SMP ((unsigned int) 0x1 << 24) // (CAN) Sampling mode\r
+// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- \r
+#define AT91C_CAN_TIMER ((unsigned int) 0xFFFF << 0) // (CAN) Timer field\r
+// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- \r
+// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- \r
+#define AT91C_CAN_REC ((unsigned int) 0xFF << 0) // (CAN) Receive Error Counter\r
+#define AT91C_CAN_TEC ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter\r
+// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- \r
+#define AT91C_CAN_TIMRST ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field\r
+// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100\r
+// *****************************************************************************\r
+typedef struct _AT91S_EMAC {\r
+ AT91_REG EMAC_NCR; // Network Control Register\r
+ AT91_REG EMAC_NCFGR; // Network Configuration Register\r
+ AT91_REG EMAC_NSR; // Network Status Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG EMAC_TSR; // Transmit Status Register\r
+ AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer\r
+ AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer\r
+ AT91_REG EMAC_RSR; // Receive Status Register\r
+ AT91_REG EMAC_ISR; // Interrupt Status Register\r
+ AT91_REG EMAC_IER; // Interrupt Enable Register\r
+ AT91_REG EMAC_IDR; // Interrupt Disable Register\r
+ AT91_REG EMAC_IMR; // Interrupt Mask Register\r
+ AT91_REG EMAC_MAN; // PHY Maintenance Register\r
+ AT91_REG EMAC_PTR; // Pause Time Register\r
+ AT91_REG EMAC_PFR; // Pause Frames received Register\r
+ AT91_REG EMAC_FTO; // Frames Transmitted OK Register\r
+ AT91_REG EMAC_SCF; // Single Collision Frame Register\r
+ AT91_REG EMAC_MCF; // Multiple Collision Frame Register\r
+ AT91_REG EMAC_FRO; // Frames Received OK Register\r
+ AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register\r
+ AT91_REG EMAC_ALE; // Alignment Error Register\r
+ AT91_REG EMAC_DTF; // Deferred Transmission Frame Register\r
+ AT91_REG EMAC_LCOL; // Late Collision Register\r
+ AT91_REG EMAC_ECOL; // Excessive Collision Register\r
+ AT91_REG EMAC_TUND; // Transmit Underrun Error Register\r
+ AT91_REG EMAC_CSE; // Carrier Sense Error Register\r
+ AT91_REG EMAC_RRE; // Receive Ressource Error Register\r
+ AT91_REG EMAC_ROV; // Receive Overrun Errors Register\r
+ AT91_REG EMAC_RSE; // Receive Symbol Errors Register\r
+ AT91_REG EMAC_ELE; // Excessive Length Errors Register\r
+ AT91_REG EMAC_RJA; // Receive Jabbers Register\r
+ AT91_REG EMAC_USF; // Undersize Frames Register\r
+ AT91_REG EMAC_STE; // SQE Test Error Register\r
+ AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register\r
+ AT91_REG EMAC_TPF; // Transmitted Pause Frames Register\r
+ AT91_REG EMAC_HRB; // Hash Address Bottom[31:0]\r
+ AT91_REG EMAC_HRT; // Hash Address Top[63:32]\r
+ AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes\r
+ AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes\r
+ AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes\r
+ AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes\r
+ AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes\r
+ AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes\r
+ AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes\r
+ AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes\r
+ AT91_REG EMAC_TID; // Type ID Checking Register\r
+ AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register\r
+ AT91_REG EMAC_USRIO; // USER Input/Output Register\r
+ AT91_REG EMAC_WOL; // Wake On LAN Register\r
+ AT91_REG Reserved1[13]; // \r
+ AT91_REG EMAC_REV; // Revision Register\r
+} AT91S_EMAC, *AT91PS_EMAC;\r
+\r
+// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- \r
+#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.\r
+#define AT91C_EMAC_LLB ((unsigned int) 0x1 << 1) // (EMAC) Loopback local. \r
+#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) // (EMAC) Receive enable. \r
+#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) // (EMAC) Transmit enable. \r
+#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) // (EMAC) Management port enable. \r
+#define AT91C_EMAC_CLRSTAT ((unsigned int) 0x1 << 5) // (EMAC) Clear statistics registers. \r
+#define AT91C_EMAC_INCSTAT ((unsigned int) 0x1 << 6) // (EMAC) Increment statistics registers. \r
+#define AT91C_EMAC_WESTAT ((unsigned int) 0x1 << 7) // (EMAC) Write enable for statistics registers. \r
+#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) // (EMAC) Back pressure. \r
+#define AT91C_EMAC_TSTART ((unsigned int) 0x1 << 9) // (EMAC) Start Transmission. \r
+#define AT91C_EMAC_THALT ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt. \r
+#define AT91C_EMAC_TPFR ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame \r
+#define AT91C_EMAC_TZQ ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame\r
+// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- \r
+#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) // (EMAC) Speed. \r
+#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) // (EMAC) Full duplex. \r
+#define AT91C_EMAC_JFRAME ((unsigned int) 0x1 << 3) // (EMAC) Jumbo Frames. \r
+#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) // (EMAC) Copy all frames. \r
+#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) // (EMAC) No broadcast. \r
+#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) // (EMAC) Multicast hash event enable\r
+#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) // (EMAC) Unicast hash enable. \r
+#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) // (EMAC) Receive 1522 bytes. \r
+#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) // (EMAC) External address match enable. \r
+#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) // (EMAC) \r
+#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8\r
+#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16\r
+#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32\r
+#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64\r
+#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) // (EMAC) \r
+#define AT91C_EMAC_PAE ((unsigned int) 0x1 << 13) // (EMAC) \r
+#define AT91C_EMAC_RBOF ((unsigned int) 0x3 << 14) // (EMAC) \r
+#define AT91C_EMAC_RBOF_OFFSET_0 ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer\r
+#define AT91C_EMAC_RBOF_OFFSET_1 ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer\r
+#define AT91C_EMAC_RBOF_OFFSET_2 ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer\r
+#define AT91C_EMAC_RBOF_OFFSET_3 ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer\r
+#define AT91C_EMAC_RLCE ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable\r
+#define AT91C_EMAC_DRFCS ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS\r
+#define AT91C_EMAC_EFRHD ((unsigned int) 0x1 << 18) // (EMAC) \r
+#define AT91C_EMAC_IRXFCS ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS\r
+// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- \r
+#define AT91C_EMAC_LINKR ((unsigned int) 0x1 << 0) // (EMAC) \r
+#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) // (EMAC) \r
+#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) // (EMAC) \r
+// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- \r
+#define AT91C_EMAC_UBR ((unsigned int) 0x1 << 0) // (EMAC) \r
+#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) // (EMAC) \r
+#define AT91C_EMAC_RLES ((unsigned int) 0x1 << 2) // (EMAC) \r
+#define AT91C_EMAC_TGO ((unsigned int) 0x1 << 3) // (EMAC) Transmit Go\r
+#define AT91C_EMAC_BEX ((unsigned int) 0x1 << 4) // (EMAC) Buffers exhausted mid frame\r
+#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) // (EMAC) \r
+#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) // (EMAC) \r
+// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- \r
+#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) // (EMAC) \r
+#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) // (EMAC) \r
+#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 2) // (EMAC) \r
+// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- \r
+#define AT91C_EMAC_MFD ((unsigned int) 0x1 << 0) // (EMAC) \r
+#define AT91C_EMAC_RCOMP ((unsigned int) 0x1 << 1) // (EMAC) \r
+#define AT91C_EMAC_RXUBR ((unsigned int) 0x1 << 2) // (EMAC) \r
+#define AT91C_EMAC_TXUBR ((unsigned int) 0x1 << 3) // (EMAC) \r
+#define AT91C_EMAC_TUNDR ((unsigned int) 0x1 << 4) // (EMAC) \r
+#define AT91C_EMAC_RLEX ((unsigned int) 0x1 << 5) // (EMAC) \r
+#define AT91C_EMAC_TXERR ((unsigned int) 0x1 << 6) // (EMAC) \r
+#define AT91C_EMAC_TCOMP ((unsigned int) 0x1 << 7) // (EMAC) \r
+#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) // (EMAC) \r
+#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) // (EMAC) \r
+#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) // (EMAC) \r
+#define AT91C_EMAC_PFRE ((unsigned int) 0x1 << 12) // (EMAC) \r
+#define AT91C_EMAC_PTZ ((unsigned int) 0x1 << 13) // (EMAC) \r
+// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- \r
+// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- \r
+// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- \r
+// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- \r
+#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) // (EMAC) \r
+#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) // (EMAC) \r
+#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) // (EMAC) \r
+#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) // (EMAC) \r
+#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) // (EMAC) \r
+#define AT91C_EMAC_SOF ((unsigned int) 0x3 << 30) // (EMAC) \r
+// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- \r
+#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 0) // (EMAC) Reduce MII\r
+// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- \r
+#define AT91C_EMAC_IP ((unsigned int) 0xFFFF << 0) // (EMAC) ARP request IP address\r
+#define AT91C_EMAC_MAG ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable\r
+#define AT91C_EMAC_ARP ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable\r
+#define AT91C_EMAC_SA1 ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable\r
+// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- \r
+#define AT91C_EMAC_REVREF ((unsigned int) 0xFFFF << 0) // (EMAC) \r
+#define AT91C_EMAC_PARTREF ((unsigned int) 0xFFFF << 16) // (EMAC) \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Analog to Digital Convertor\r
+// *****************************************************************************\r
+typedef struct _AT91S_ADC {\r
+ AT91_REG ADC_CR; // ADC Control Register\r
+ AT91_REG ADC_MR; // ADC Mode Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG ADC_CHER; // ADC Channel Enable Register\r
+ AT91_REG ADC_CHDR; // ADC Channel Disable Register\r
+ AT91_REG ADC_CHSR; // ADC Channel Status Register\r
+ AT91_REG ADC_SR; // ADC Status Register\r
+ AT91_REG ADC_LCDR; // ADC Last Converted Data Register\r
+ AT91_REG ADC_IER; // ADC Interrupt Enable Register\r
+ AT91_REG ADC_IDR; // ADC Interrupt Disable Register\r
+ AT91_REG ADC_IMR; // ADC Interrupt Mask Register\r
+ AT91_REG ADC_CDR0; // ADC Channel Data Register 0\r
+ AT91_REG ADC_CDR1; // ADC Channel Data Register 1\r
+ AT91_REG ADC_CDR2; // ADC Channel Data Register 2\r
+ AT91_REG ADC_CDR3; // ADC Channel Data Register 3\r
+ AT91_REG ADC_CDR4; // ADC Channel Data Register 4\r
+ AT91_REG ADC_CDR5; // ADC Channel Data Register 5\r
+ AT91_REG ADC_CDR6; // ADC Channel Data Register 6\r
+ AT91_REG ADC_CDR7; // ADC Channel Data Register 7\r
+ AT91_REG Reserved1[44]; // \r
+ AT91_REG ADC_RPR; // Receive Pointer Register\r
+ AT91_REG ADC_RCR; // Receive Counter Register\r
+ AT91_REG ADC_TPR; // Transmit Pointer Register\r
+ AT91_REG ADC_TCR; // Transmit Counter Register\r
+ AT91_REG ADC_RNPR; // Receive Next Pointer Register\r
+ AT91_REG ADC_RNCR; // Receive Next Counter Register\r
+ AT91_REG ADC_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG ADC_TNCR; // Transmit Next Counter Register\r
+ AT91_REG ADC_PTCR; // PDC Transfer Control Register\r
+ AT91_REG ADC_PTSR; // PDC Transfer Status Register\r
+} AT91S_ADC, *AT91PS_ADC;\r
+\r
+// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- \r
+#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset\r
+#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion\r
+// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- \r
+#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable\r
+#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software\r
+#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.\r
+#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection\r
+#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0\r
+#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1\r
+#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2\r
+#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3\r
+#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4\r
+#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5\r
+#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger\r
+#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution.\r
+#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution\r
+#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution\r
+#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode\r
+#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode\r
+#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode\r
+#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection\r
+#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time\r
+#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time\r
+// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- \r
+#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0\r
+#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1\r
+#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2\r
+#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3\r
+#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4\r
+#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5\r
+#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6\r
+#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7\r
+// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- \r
+// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- \r
+// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- \r
+#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion\r
+#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error\r
+#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready\r
+#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun\r
+#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer\r
+#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt\r
+// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- \r
+#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted\r
+// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- \r
+// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- \r
+// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- \r
+// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- \r
+#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data\r
+// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- \r
+// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- \r
+// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- \r
+// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- \r
+// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- \r
+// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- \r
+// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Advanced Encryption Standard\r
+// *****************************************************************************\r
+typedef struct _AT91S_AES {\r
+ AT91_REG AES_CR; // Control Register\r
+ AT91_REG AES_MR; // Mode Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG AES_IER; // Interrupt Enable Register\r
+ AT91_REG AES_IDR; // Interrupt Disable Register\r
+ AT91_REG AES_IMR; // Interrupt Mask Register\r
+ AT91_REG AES_ISR; // Interrupt Status Register\r
+ AT91_REG AES_KEYWxR[4]; // Key Word x Register\r
+ AT91_REG Reserved1[4]; // \r
+ AT91_REG AES_IDATAxR[4]; // Input Data x Register\r
+ AT91_REG AES_ODATAxR[4]; // Output Data x Register\r
+ AT91_REG AES_IVxR[4]; // Initialization Vector x Register\r
+ AT91_REG Reserved2[35]; // \r
+ AT91_REG AES_VR; // AES Version Register\r
+ AT91_REG AES_RPR; // Receive Pointer Register\r
+ AT91_REG AES_RCR; // Receive Counter Register\r
+ AT91_REG AES_TPR; // Transmit Pointer Register\r
+ AT91_REG AES_TCR; // Transmit Counter Register\r
+ AT91_REG AES_RNPR; // Receive Next Pointer Register\r
+ AT91_REG AES_RNCR; // Receive Next Counter Register\r
+ AT91_REG AES_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG AES_TNCR; // Transmit Next Counter Register\r
+ AT91_REG AES_PTCR; // PDC Transfer Control Register\r
+ AT91_REG AES_PTSR; // PDC Transfer Status Register\r
+} AT91S_AES, *AT91PS_AES;\r
+\r
+// -------- AES_CR : (AES Offset: 0x0) Control Register -------- \r
+#define AT91C_AES_START ((unsigned int) 0x1 << 0) // (AES) Starts Processing\r
+#define AT91C_AES_SWRST ((unsigned int) 0x1 << 8) // (AES) Software Reset\r
+#define AT91C_AES_LOADSEED ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading\r
+// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- \r
+#define AT91C_AES_CIPHER ((unsigned int) 0x1 << 0) // (AES) Processing Mode\r
+#define AT91C_AES_PROCDLY ((unsigned int) 0xF << 4) // (AES) Processing Delay\r
+#define AT91C_AES_SMOD ((unsigned int) 0x3 << 8) // (AES) Start Mode\r
+#define AT91C_AES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.\r
+#define AT91C_AES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).\r
+#define AT91C_AES_SMOD_PDC ((unsigned int) 0x2 << 8) // (AES) PDC Mode (cf datasheet).\r
+#define AT91C_AES_OPMOD ((unsigned int) 0x7 << 12) // (AES) Operation Mode\r
+#define AT91C_AES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode.\r
+#define AT91C_AES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode.\r
+#define AT91C_AES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode.\r
+#define AT91C_AES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode.\r
+#define AT91C_AES_OPMOD_CTR ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode.\r
+#define AT91C_AES_LOD ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode\r
+#define AT91C_AES_CFBS ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size\r
+#define AT91C_AES_CFBS_128_BIT ((unsigned int) 0x0 << 16) // (AES) 128-bit.\r
+#define AT91C_AES_CFBS_64_BIT ((unsigned int) 0x1 << 16) // (AES) 64-bit.\r
+#define AT91C_AES_CFBS_32_BIT ((unsigned int) 0x2 << 16) // (AES) 32-bit.\r
+#define AT91C_AES_CFBS_16_BIT ((unsigned int) 0x3 << 16) // (AES) 16-bit.\r
+#define AT91C_AES_CFBS_8_BIT ((unsigned int) 0x4 << 16) // (AES) 8-bit.\r
+#define AT91C_AES_CKEY ((unsigned int) 0xF << 20) // (AES) Countermeasure Key\r
+#define AT91C_AES_CTYPE ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type\r
+#define AT91C_AES_CTYPE_TYPE1_EN ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled.\r
+#define AT91C_AES_CTYPE_TYPE2_EN ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled.\r
+#define AT91C_AES_CTYPE_TYPE3_EN ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled.\r
+#define AT91C_AES_CTYPE_TYPE4_EN ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled.\r
+#define AT91C_AES_CTYPE_TYPE5_EN ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled.\r
+// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- \r
+#define AT91C_AES_DATRDY ((unsigned int) 0x1 << 0) // (AES) DATRDY\r
+#define AT91C_AES_ENDRX ((unsigned int) 0x1 << 1) // (AES) PDC Read Buffer End\r
+#define AT91C_AES_ENDTX ((unsigned int) 0x1 << 2) // (AES) PDC Write Buffer End\r
+#define AT91C_AES_RXBUFF ((unsigned int) 0x1 << 3) // (AES) PDC Read Buffer Full\r
+#define AT91C_AES_TXBUFE ((unsigned int) 0x1 << 4) // (AES) PDC Write Buffer Empty\r
+#define AT91C_AES_URAD ((unsigned int) 0x1 << 8) // (AES) Unspecified Register Access Detection\r
+// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- \r
+// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- \r
+// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- \r
+#define AT91C_AES_URAT ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status\r
+#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode.\r
+#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing.\r
+#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing.\r
+#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation.\r
+#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation.\r
+#define AT91C_AES_URAT_WO_REG_READ ((unsigned int) 0x5 << 12) // (AES) Write-only register read access.\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard\r
+// *****************************************************************************\r
+typedef struct _AT91S_TDES {\r
+ AT91_REG TDES_CR; // Control Register\r
+ AT91_REG TDES_MR; // Mode Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG TDES_IER; // Interrupt Enable Register\r
+ AT91_REG TDES_IDR; // Interrupt Disable Register\r
+ AT91_REG TDES_IMR; // Interrupt Mask Register\r
+ AT91_REG TDES_ISR; // Interrupt Status Register\r
+ AT91_REG TDES_KEY1WxR[2]; // Key 1 Word x Register\r
+ AT91_REG TDES_KEY2WxR[2]; // Key 2 Word x Register\r
+ AT91_REG TDES_KEY3WxR[2]; // Key 3 Word x Register\r
+ AT91_REG Reserved1[2]; // \r
+ AT91_REG TDES_IDATAxR[2]; // Input Data x Register\r
+ AT91_REG Reserved2[2]; // \r
+ AT91_REG TDES_ODATAxR[2]; // Output Data x Register\r
+ AT91_REG Reserved3[2]; // \r
+ AT91_REG TDES_IVxR[2]; // Initialization Vector x Register\r
+ AT91_REG Reserved4[37]; // \r
+ AT91_REG TDES_VR; // TDES Version Register\r
+ AT91_REG TDES_RPR; // Receive Pointer Register\r
+ AT91_REG TDES_RCR; // Receive Counter Register\r
+ AT91_REG TDES_TPR; // Transmit Pointer Register\r
+ AT91_REG TDES_TCR; // Transmit Counter Register\r
+ AT91_REG TDES_RNPR; // Receive Next Pointer Register\r
+ AT91_REG TDES_RNCR; // Receive Next Counter Register\r
+ AT91_REG TDES_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG TDES_TNCR; // Transmit Next Counter Register\r
+ AT91_REG TDES_PTCR; // PDC Transfer Control Register\r
+ AT91_REG TDES_PTSR; // PDC Transfer Status Register\r
+} AT91S_TDES, *AT91PS_TDES;\r
+\r
+// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- \r
+#define AT91C_TDES_START ((unsigned int) 0x1 << 0) // (TDES) Starts Processing\r
+#define AT91C_TDES_SWRST ((unsigned int) 0x1 << 8) // (TDES) Software Reset\r
+// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- \r
+#define AT91C_TDES_CIPHER ((unsigned int) 0x1 << 0) // (TDES) Processing Mode\r
+#define AT91C_TDES_TDESMOD ((unsigned int) 0x1 << 1) // (TDES) Single or Triple DES Mode\r
+#define AT91C_TDES_KEYMOD ((unsigned int) 0x1 << 4) // (TDES) Key Mode\r
+#define AT91C_TDES_SMOD ((unsigned int) 0x3 << 8) // (TDES) Start Mode\r
+#define AT91C_TDES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.\r
+#define AT91C_TDES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).\r
+#define AT91C_TDES_SMOD_PDC ((unsigned int) 0x2 << 8) // (TDES) PDC Mode (cf datasheet).\r
+#define AT91C_TDES_OPMOD ((unsigned int) 0x3 << 12) // (TDES) Operation Mode\r
+#define AT91C_TDES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode.\r
+#define AT91C_TDES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode.\r
+#define AT91C_TDES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode.\r
+#define AT91C_TDES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode.\r
+#define AT91C_TDES_LOD ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode\r
+#define AT91C_TDES_CFBS ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size\r
+#define AT91C_TDES_CFBS_64_BIT ((unsigned int) 0x0 << 16) // (TDES) 64-bit.\r
+#define AT91C_TDES_CFBS_32_BIT ((unsigned int) 0x1 << 16) // (TDES) 32-bit.\r
+#define AT91C_TDES_CFBS_16_BIT ((unsigned int) 0x2 << 16) // (TDES) 16-bit.\r
+#define AT91C_TDES_CFBS_8_BIT ((unsigned int) 0x3 << 16) // (TDES) 8-bit.\r
+// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- \r
+#define AT91C_TDES_DATRDY ((unsigned int) 0x1 << 0) // (TDES) DATRDY\r
+#define AT91C_TDES_ENDRX ((unsigned int) 0x1 << 1) // (TDES) PDC Read Buffer End\r
+#define AT91C_TDES_ENDTX ((unsigned int) 0x1 << 2) // (TDES) PDC Write Buffer End\r
+#define AT91C_TDES_RXBUFF ((unsigned int) 0x1 << 3) // (TDES) PDC Read Buffer Full\r
+#define AT91C_TDES_TXBUFE ((unsigned int) 0x1 << 4) // (TDES) PDC Write Buffer Empty\r
+#define AT91C_TDES_URAD ((unsigned int) 0x1 << 8) // (TDES) Unspecified Register Access Detection\r
+// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- \r
+// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- \r
+// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- \r
+#define AT91C_TDES_URAT ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status\r
+#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode.\r
+#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing.\r
+#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing.\r
+#define AT91C_TDES_URAT_WO_REG_READ ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access.\r
+\r
+// *****************************************************************************\r
+// REGISTER ADDRESS DEFINITION FOR AT91SAM7X256\r
+// *****************************************************************************\r
+// ========== Register definition for SYS peripheral ========== \r
+// ========== Register definition for AIC peripheral ========== \r
+#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register\r
+#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register\r
+#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register\r
+#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect)\r
+#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register\r
+#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register\r
+#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register\r
+#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register\r
+#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register\r
+#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register\r
+#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register\r
+#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register\r
+#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register\r
+#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register\r
+#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register\r
+#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register\r
+#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register\r
+#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register\r
+// ========== Register definition for PDC_DBGU peripheral ========== \r
+#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register\r
+#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register\r
+#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register\r
+#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register\r
+#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register\r
+#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register\r
+#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register\r
+#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register\r
+#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register\r
+#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register\r
+// ========== Register definition for DBGU peripheral ========== \r
+#define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register\r
+#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register\r
+#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register\r
+#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register\r
+#define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register\r
+#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register\r
+#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register\r
+#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register\r
+#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register\r
+#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register\r
+#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register\r
+#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register\r
+// ========== Register definition for PIOA peripheral ========== \r
+#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr\r
+#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register\r
+#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register\r
+#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register\r
+#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register\r
+#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register\r
+#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register\r
+#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register\r
+#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register\r
+#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register\r
+#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register\r
+#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register\r
+#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register\r
+#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register\r
+#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register\r
+#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register\r
+#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register\r
+#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register\r
+#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register\r
+#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register\r
+#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register\r
+#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register\r
+#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register\r
+#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register\r
+#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register\r
+#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register\r
+#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register\r
+#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register\r
+#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register\r
+// ========== Register definition for PIOB peripheral ========== \r
+#define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register\r
+#define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register\r
+#define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register\r
+#define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register\r
+#define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register\r
+#define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register\r
+#define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register\r
+#define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register\r
+#define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register\r
+#define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register\r
+#define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register\r
+#define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register\r
+#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register\r
+#define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register\r
+#define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register\r
+#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register\r
+#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr\r
+#define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register\r
+#define AT91C_PIOB_PPUER ((AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register\r
+#define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register\r
+#define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register\r
+#define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register\r
+#define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register\r
+#define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register\r
+#define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register\r
+#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register\r
+#define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register\r
+#define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register\r
+#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register\r
+// ========== Register definition for CKGR peripheral ========== \r
+#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register\r
+#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register\r
+#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register\r
+// ========== Register definition for PMC peripheral ========== \r
+#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register\r
+#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register\r
+#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register\r
+#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register\r
+#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register\r
+#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register\r
+#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register\r
+#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register\r
+#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register\r
+#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register\r
+#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register\r
+#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register\r
+#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register\r
+#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register\r
+#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register\r
+// ========== Register definition for RSTC peripheral ========== \r
+#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register\r
+#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register\r
+#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register\r
+// ========== Register definition for RTTC peripheral ========== \r
+#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register\r
+#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register\r
+#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register\r
+#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register\r
+// ========== Register definition for PITC peripheral ========== \r
+#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register\r
+#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register\r
+#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register\r
+#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register\r
+// ========== Register definition for WDTC peripheral ========== \r
+#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register\r
+#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register\r
+#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register\r
+// ========== Register definition for VREG peripheral ========== \r
+#define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register\r
+// ========== Register definition for MC peripheral ========== \r
+#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register\r
+#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register\r
+#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register\r
+#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register\r
+#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register\r
+#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register\r
+// ========== Register definition for PDC_SPI1 peripheral ========== \r
+#define AT91C_SPI1_PTCR ((AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register\r
+#define AT91C_SPI1_RPR ((AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register\r
+#define AT91C_SPI1_TNCR ((AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register\r
+#define AT91C_SPI1_TPR ((AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register\r
+#define AT91C_SPI1_TNPR ((AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register\r
+#define AT91C_SPI1_TCR ((AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register\r
+#define AT91C_SPI1_RCR ((AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register\r
+#define AT91C_SPI1_RNPR ((AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register\r
+#define AT91C_SPI1_RNCR ((AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register\r
+#define AT91C_SPI1_PTSR ((AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register\r
+// ========== Register definition for SPI1 peripheral ========== \r
+#define AT91C_SPI1_IMR ((AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register\r
+#define AT91C_SPI1_IER ((AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register\r
+#define AT91C_SPI1_MR ((AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register\r
+#define AT91C_SPI1_RDR ((AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register\r
+#define AT91C_SPI1_IDR ((AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register\r
+#define AT91C_SPI1_SR ((AT91_REG *) 0xFFFE4010) // (SPI1) Status Register\r
+#define AT91C_SPI1_TDR ((AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register\r
+#define AT91C_SPI1_CR ((AT91_REG *) 0xFFFE4000) // (SPI1) Control Register\r
+#define AT91C_SPI1_CSR ((AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register\r
+// ========== Register definition for PDC_SPI0 peripheral ========== \r
+#define AT91C_SPI0_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register\r
+#define AT91C_SPI0_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register\r
+#define AT91C_SPI0_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register\r
+#define AT91C_SPI0_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register\r
+#define AT91C_SPI0_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register\r
+#define AT91C_SPI0_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register\r
+#define AT91C_SPI0_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register\r
+#define AT91C_SPI0_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register\r
+#define AT91C_SPI0_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register\r
+#define AT91C_SPI0_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register\r
+// ========== Register definition for SPI0 peripheral ========== \r
+#define AT91C_SPI0_IER ((AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register\r
+#define AT91C_SPI0_SR ((AT91_REG *) 0xFFFE0010) // (SPI0) Status Register\r
+#define AT91C_SPI0_IDR ((AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register\r
+#define AT91C_SPI0_CR ((AT91_REG *) 0xFFFE0000) // (SPI0) Control Register\r
+#define AT91C_SPI0_MR ((AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register\r
+#define AT91C_SPI0_IMR ((AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register\r
+#define AT91C_SPI0_TDR ((AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register\r
+#define AT91C_SPI0_RDR ((AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register\r
+#define AT91C_SPI0_CSR ((AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register\r
+// ========== Register definition for PDC_US1 peripheral ========== \r
+#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register\r
+#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register\r
+#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register\r
+#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register\r
+#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register\r
+#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register\r
+#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register\r
+#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register\r
+#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register\r
+#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register\r
+// ========== Register definition for US1 peripheral ========== \r
+#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register\r
+#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register\r
+#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register\r
+#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register\r
+#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register\r
+#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register\r
+#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register\r
+#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register\r
+#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register\r
+#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register\r
+#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register\r
+#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register\r
+#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register\r
+#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register\r
+// ========== Register definition for PDC_US0 peripheral ========== \r
+#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register\r
+#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register\r
+#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register\r
+#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register\r
+#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register\r
+#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register\r
+#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register\r
+#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register\r
+#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register\r
+#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register\r
+// ========== Register definition for US0 peripheral ========== \r
+#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register\r
+#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register\r
+#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register\r
+#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register\r
+#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register\r
+#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register\r
+#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register\r
+#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register\r
+#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register\r
+#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register\r
+#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register\r
+#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register\r
+#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register\r
+#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register\r
+// ========== Register definition for PDC_SSC peripheral ========== \r
+#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register\r
+#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register\r
+#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register\r
+#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register\r
+#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register\r
+#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register\r
+#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register\r
+#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register\r
+#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register\r
+#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register\r
+// ========== Register definition for SSC peripheral ========== \r
+#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register\r
+#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register\r
+#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register\r
+#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register\r
+#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register\r
+#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister\r
+#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register\r
+#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register\r
+#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register\r
+#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register\r
+#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register\r
+#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register\r
+#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register\r
+#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register\r
+// ========== Register definition for TWI peripheral ========== \r
+#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register\r
+#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register\r
+#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register\r
+#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register\r
+#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register\r
+#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register\r
+#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register\r
+#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register\r
+#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register\r
+#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register\r
+// ========== Register definition for PWMC_CH3 peripheral ========== \r
+#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register\r
+#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved\r
+#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register\r
+#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register\r
+#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register\r
+#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register\r
+// ========== Register definition for PWMC_CH2 peripheral ========== \r
+#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved\r
+#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register\r
+#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register\r
+#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register\r
+#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register\r
+#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register\r
+// ========== Register definition for PWMC_CH1 peripheral ========== \r
+#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved\r
+#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register\r
+#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register\r
+#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register\r
+#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register\r
+#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register\r
+// ========== Register definition for PWMC_CH0 peripheral ========== \r
+#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved\r
+#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register\r
+#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register\r
+#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register\r
+#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register\r
+#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register\r
+// ========== Register definition for PWMC peripheral ========== \r
+#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register\r
+#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register\r
+#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register\r
+#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register\r
+#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register\r
+#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register\r
+#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register\r
+#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register\r
+#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register\r
+// ========== Register definition for UDP peripheral ========== \r
+#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register\r
+#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register\r
+#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register\r
+#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register\r
+#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register\r
+#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register\r
+#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register\r
+#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register\r
+#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register\r
+#define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register\r
+#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register\r
+#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register\r
+// ========== Register definition for TC0 peripheral ========== \r
+#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register\r
+#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C\r
+#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B\r
+#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register\r
+#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register\r
+#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A\r
+#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register\r
+#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value\r
+#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register\r
+// ========== Register definition for TC1 peripheral ========== \r
+#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B\r
+#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register\r
+#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register\r
+#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register\r
+#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register\r
+#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A\r
+#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C\r
+#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register\r
+#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value\r
+// ========== Register definition for TC2 peripheral ========== \r
+#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register\r
+#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value\r
+#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A\r
+#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B\r
+#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register\r
+#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register\r
+#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C\r
+#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register\r
+#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register\r
+// ========== Register definition for TCB peripheral ========== \r
+#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register\r
+#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register\r
+// ========== Register definition for CAN_MB0 peripheral ========== \r
+#define AT91C_CAN_MB0_MDL ((AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register\r
+#define AT91C_CAN_MB0_MAM ((AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register\r
+#define AT91C_CAN_MB0_MCR ((AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register\r
+#define AT91C_CAN_MB0_MID ((AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register\r
+#define AT91C_CAN_MB0_MSR ((AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register\r
+#define AT91C_CAN_MB0_MFID ((AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register\r
+#define AT91C_CAN_MB0_MDH ((AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register\r
+#define AT91C_CAN_MB0_MMR ((AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register\r
+// ========== Register definition for CAN_MB1 peripheral ========== \r
+#define AT91C_CAN_MB1_MDL ((AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register\r
+#define AT91C_CAN_MB1_MID ((AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register\r
+#define AT91C_CAN_MB1_MMR ((AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register\r
+#define AT91C_CAN_MB1_MSR ((AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register\r
+#define AT91C_CAN_MB1_MAM ((AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register\r
+#define AT91C_CAN_MB1_MDH ((AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register\r
+#define AT91C_CAN_MB1_MCR ((AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register\r
+#define AT91C_CAN_MB1_MFID ((AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register\r
+// ========== Register definition for CAN_MB2 peripheral ========== \r
+#define AT91C_CAN_MB2_MCR ((AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register\r
+#define AT91C_CAN_MB2_MDH ((AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register\r
+#define AT91C_CAN_MB2_MID ((AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register\r
+#define AT91C_CAN_MB2_MDL ((AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register\r
+#define AT91C_CAN_MB2_MMR ((AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register\r
+#define AT91C_CAN_MB2_MAM ((AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register\r
+#define AT91C_CAN_MB2_MFID ((AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register\r
+#define AT91C_CAN_MB2_MSR ((AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register\r
+// ========== Register definition for CAN_MB3 peripheral ========== \r
+#define AT91C_CAN_MB3_MFID ((AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register\r
+#define AT91C_CAN_MB3_MAM ((AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register\r
+#define AT91C_CAN_MB3_MID ((AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register\r
+#define AT91C_CAN_MB3_MCR ((AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register\r
+#define AT91C_CAN_MB3_MMR ((AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register\r
+#define AT91C_CAN_MB3_MSR ((AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register\r
+#define AT91C_CAN_MB3_MDL ((AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register\r
+#define AT91C_CAN_MB3_MDH ((AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register\r
+// ========== Register definition for CAN_MB4 peripheral ========== \r
+#define AT91C_CAN_MB4_MID ((AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register\r
+#define AT91C_CAN_MB4_MMR ((AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register\r
+#define AT91C_CAN_MB4_MDH ((AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register\r
+#define AT91C_CAN_MB4_MFID ((AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register\r
+#define AT91C_CAN_MB4_MSR ((AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register\r
+#define AT91C_CAN_MB4_MCR ((AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register\r
+#define AT91C_CAN_MB4_MDL ((AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register\r
+#define AT91C_CAN_MB4_MAM ((AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register\r
+// ========== Register definition for CAN_MB5 peripheral ========== \r
+#define AT91C_CAN_MB5_MSR ((AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register\r
+#define AT91C_CAN_MB5_MCR ((AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register\r
+#define AT91C_CAN_MB5_MFID ((AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register\r
+#define AT91C_CAN_MB5_MDH ((AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register\r
+#define AT91C_CAN_MB5_MID ((AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register\r
+#define AT91C_CAN_MB5_MMR ((AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register\r
+#define AT91C_CAN_MB5_MDL ((AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register\r
+#define AT91C_CAN_MB5_MAM ((AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register\r
+// ========== Register definition for CAN_MB6 peripheral ========== \r
+#define AT91C_CAN_MB6_MFID ((AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register\r
+#define AT91C_CAN_MB6_MID ((AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register\r
+#define AT91C_CAN_MB6_MAM ((AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register\r
+#define AT91C_CAN_MB6_MSR ((AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register\r
+#define AT91C_CAN_MB6_MDL ((AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register\r
+#define AT91C_CAN_MB6_MCR ((AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register\r
+#define AT91C_CAN_MB6_MDH ((AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register\r
+#define AT91C_CAN_MB6_MMR ((AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register\r
+// ========== Register definition for CAN_MB7 peripheral ========== \r
+#define AT91C_CAN_MB7_MCR ((AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register\r
+#define AT91C_CAN_MB7_MDH ((AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register\r
+#define AT91C_CAN_MB7_MFID ((AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register\r
+#define AT91C_CAN_MB7_MDL ((AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register\r
+#define AT91C_CAN_MB7_MID ((AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register\r
+#define AT91C_CAN_MB7_MMR ((AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register\r
+#define AT91C_CAN_MB7_MAM ((AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register\r
+#define AT91C_CAN_MB7_MSR ((AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register\r
+// ========== Register definition for CAN peripheral ========== \r
+#define AT91C_CAN_TCR ((AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register\r
+#define AT91C_CAN_IMR ((AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register\r
+#define AT91C_CAN_IER ((AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register\r
+#define AT91C_CAN_ECR ((AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register\r
+#define AT91C_CAN_TIMESTP ((AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register\r
+#define AT91C_CAN_MR ((AT91_REG *) 0xFFFD0000) // (CAN) Mode Register\r
+#define AT91C_CAN_IDR ((AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register\r
+#define AT91C_CAN_ACR ((AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register\r
+#define AT91C_CAN_TIM ((AT91_REG *) 0xFFFD0018) // (CAN) Timer Register\r
+#define AT91C_CAN_SR ((AT91_REG *) 0xFFFD0010) // (CAN) Status Register\r
+#define AT91C_CAN_BR ((AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register\r
+#define AT91C_CAN_VR ((AT91_REG *) 0xFFFD00FC) // (CAN) Version Register\r
+// ========== Register definition for EMAC peripheral ========== \r
+#define AT91C_EMAC_ISR ((AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register\r
+#define AT91C_EMAC_SA4H ((AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes\r
+#define AT91C_EMAC_SA1L ((AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes\r
+#define AT91C_EMAC_ELE ((AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register\r
+#define AT91C_EMAC_LCOL ((AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register\r
+#define AT91C_EMAC_RLE ((AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register\r
+#define AT91C_EMAC_WOL ((AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register\r
+#define AT91C_EMAC_DTF ((AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register\r
+#define AT91C_EMAC_TUND ((AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register\r
+#define AT91C_EMAC_NCR ((AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register\r
+#define AT91C_EMAC_SA4L ((AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes\r
+#define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register\r
+#define AT91C_EMAC_SA3L ((AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes\r
+#define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register\r
+#define AT91C_EMAC_IDR ((AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register\r
+#define AT91C_EMAC_RSE ((AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register\r
+#define AT91C_EMAC_ECOL ((AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register\r
+#define AT91C_EMAC_TID ((AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register\r
+#define AT91C_EMAC_HRB ((AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]\r
+#define AT91C_EMAC_TBQP ((AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer\r
+#define AT91C_EMAC_USRIO ((AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register\r
+#define AT91C_EMAC_PTR ((AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register\r
+#define AT91C_EMAC_SA2H ((AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes\r
+#define AT91C_EMAC_ROV ((AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register\r
+#define AT91C_EMAC_ALE ((AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register\r
+#define AT91C_EMAC_RJA ((AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register\r
+#define AT91C_EMAC_RBQP ((AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer\r
+#define AT91C_EMAC_TPF ((AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register\r
+#define AT91C_EMAC_NCFGR ((AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register\r
+#define AT91C_EMAC_HRT ((AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32]\r
+#define AT91C_EMAC_USF ((AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register\r
+#define AT91C_EMAC_FCSE ((AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register\r
+#define AT91C_EMAC_TPQ ((AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register\r
+#define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register\r
+#define AT91C_EMAC_FTO ((AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register\r
+#define AT91C_EMAC_REV ((AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register\r
+#define AT91C_EMAC_IMR ((AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register\r
+#define AT91C_EMAC_SCF ((AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register\r
+#define AT91C_EMAC_PFR ((AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register\r
+#define AT91C_EMAC_MCF ((AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register\r
+#define AT91C_EMAC_NSR ((AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register\r
+#define AT91C_EMAC_SA2L ((AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes\r
+#define AT91C_EMAC_FRO ((AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register\r
+#define AT91C_EMAC_IER ((AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register\r
+#define AT91C_EMAC_SA1H ((AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes\r
+#define AT91C_EMAC_CSE ((AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register\r
+#define AT91C_EMAC_SA3H ((AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes\r
+#define AT91C_EMAC_RRE ((AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register\r
+#define AT91C_EMAC_STE ((AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register\r
+// ========== Register definition for PDC_ADC peripheral ========== \r
+#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register\r
+#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register\r
+#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register\r
+#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register\r
+#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register\r
+#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register\r
+#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register\r
+#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register\r
+#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register\r
+#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register\r
+// ========== Register definition for ADC peripheral ========== \r
+#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2\r
+#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3\r
+#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0\r
+#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5\r
+#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register\r
+#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register\r
+#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4\r
+#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1\r
+#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register\r
+#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register\r
+#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register\r
+#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7\r
+#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6\r
+#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register\r
+#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register\r
+#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register\r
+#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register\r
+#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register\r
+// ========== Register definition for PDC_AES peripheral ========== \r
+#define AT91C_AES_TPR ((AT91_REG *) 0xFFFA4108) // (PDC_AES) Transmit Pointer Register\r
+#define AT91C_AES_PTCR ((AT91_REG *) 0xFFFA4120) // (PDC_AES) PDC Transfer Control Register\r
+#define AT91C_AES_RNPR ((AT91_REG *) 0xFFFA4110) // (PDC_AES) Receive Next Pointer Register\r
+#define AT91C_AES_TNCR ((AT91_REG *) 0xFFFA411C) // (PDC_AES) Transmit Next Counter Register\r
+#define AT91C_AES_TCR ((AT91_REG *) 0xFFFA410C) // (PDC_AES) Transmit Counter Register\r
+#define AT91C_AES_RCR ((AT91_REG *) 0xFFFA4104) // (PDC_AES) Receive Counter Register\r
+#define AT91C_AES_RNCR ((AT91_REG *) 0xFFFA4114) // (PDC_AES) Receive Next Counter Register\r
+#define AT91C_AES_TNPR ((AT91_REG *) 0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register\r
+#define AT91C_AES_RPR ((AT91_REG *) 0xFFFA4100) // (PDC_AES) Receive Pointer Register\r
+#define AT91C_AES_PTSR ((AT91_REG *) 0xFFFA4124) // (PDC_AES) PDC Transfer Status Register\r
+// ========== Register definition for AES peripheral ========== \r
+#define AT91C_AES_IVxR ((AT91_REG *) 0xFFFA4060) // (AES) Initialization Vector x Register\r
+#define AT91C_AES_MR ((AT91_REG *) 0xFFFA4004) // (AES) Mode Register\r
+#define AT91C_AES_VR ((AT91_REG *) 0xFFFA40FC) // (AES) AES Version Register\r
+#define AT91C_AES_ODATAxR ((AT91_REG *) 0xFFFA4050) // (AES) Output Data x Register\r
+#define AT91C_AES_IDATAxR ((AT91_REG *) 0xFFFA4040) // (AES) Input Data x Register\r
+#define AT91C_AES_CR ((AT91_REG *) 0xFFFA4000) // (AES) Control Register\r
+#define AT91C_AES_IDR ((AT91_REG *) 0xFFFA4014) // (AES) Interrupt Disable Register\r
+#define AT91C_AES_IMR ((AT91_REG *) 0xFFFA4018) // (AES) Interrupt Mask Register\r
+#define AT91C_AES_IER ((AT91_REG *) 0xFFFA4010) // (AES) Interrupt Enable Register\r
+#define AT91C_AES_KEYWxR ((AT91_REG *) 0xFFFA4020) // (AES) Key Word x Register\r
+#define AT91C_AES_ISR ((AT91_REG *) 0xFFFA401C) // (AES) Interrupt Status Register\r
+// ========== Register definition for PDC_TDES peripheral ========== \r
+#define AT91C_TDES_RNCR ((AT91_REG *) 0xFFFA8114) // (PDC_TDES) Receive Next Counter Register\r
+#define AT91C_TDES_TCR ((AT91_REG *) 0xFFFA810C) // (PDC_TDES) Transmit Counter Register\r
+#define AT91C_TDES_RCR ((AT91_REG *) 0xFFFA8104) // (PDC_TDES) Receive Counter Register\r
+#define AT91C_TDES_TNPR ((AT91_REG *) 0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register\r
+#define AT91C_TDES_RNPR ((AT91_REG *) 0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register\r
+#define AT91C_TDES_RPR ((AT91_REG *) 0xFFFA8100) // (PDC_TDES) Receive Pointer Register\r
+#define AT91C_TDES_TNCR ((AT91_REG *) 0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register\r
+#define AT91C_TDES_TPR ((AT91_REG *) 0xFFFA8108) // (PDC_TDES) Transmit Pointer Register\r
+#define AT91C_TDES_PTSR ((AT91_REG *) 0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register\r
+#define AT91C_TDES_PTCR ((AT91_REG *) 0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register\r
+// ========== Register definition for TDES peripheral ========== \r
+#define AT91C_TDES_KEY2WxR ((AT91_REG *) 0xFFFA8028) // (TDES) Key 2 Word x Register\r
+#define AT91C_TDES_KEY3WxR ((AT91_REG *) 0xFFFA8030) // (TDES) Key 3 Word x Register\r
+#define AT91C_TDES_IDR ((AT91_REG *) 0xFFFA8014) // (TDES) Interrupt Disable Register\r
+#define AT91C_TDES_VR ((AT91_REG *) 0xFFFA80FC) // (TDES) TDES Version Register\r
+#define AT91C_TDES_IVxR ((AT91_REG *) 0xFFFA8060) // (TDES) Initialization Vector x Register\r
+#define AT91C_TDES_ODATAxR ((AT91_REG *) 0xFFFA8050) // (TDES) Output Data x Register\r
+#define AT91C_TDES_IMR ((AT91_REG *) 0xFFFA8018) // (TDES) Interrupt Mask Register\r
+#define AT91C_TDES_MR ((AT91_REG *) 0xFFFA8004) // (TDES) Mode Register\r
+#define AT91C_TDES_CR ((AT91_REG *) 0xFFFA8000) // (TDES) Control Register\r
+#define AT91C_TDES_IER ((AT91_REG *) 0xFFFA8010) // (TDES) Interrupt Enable Register\r
+#define AT91C_TDES_ISR ((AT91_REG *) 0xFFFA801C) // (TDES) Interrupt Status Register\r
+#define AT91C_TDES_IDATAxR ((AT91_REG *) 0xFFFA8040) // (TDES) Input Data x Register\r
+#define AT91C_TDES_KEY1WxR ((AT91_REG *) 0xFFFA8020) // (TDES) Key 1 Word x Register\r
+\r
+// *****************************************************************************\r
+// PIO DEFINITIONS FOR AT91SAM7X256\r
+// *****************************************************************************\r
+#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0\r
+#define AT91C_PA0_RXD0 ((unsigned int) AT91C_PIO_PA0) // USART 0 Receive Data\r
+#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1\r
+#define AT91C_PA1_TXD0 ((unsigned int) AT91C_PIO_PA1) // USART 0 Transmit Data\r
+#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10\r
+#define AT91C_PA10_TWD ((unsigned int) AT91C_PIO_PA10) // TWI Two-wire Serial Data\r
+#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11\r
+#define AT91C_PA11_TWCK ((unsigned int) AT91C_PIO_PA11) // TWI Two-wire Serial Clock\r
+#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12\r
+#define AT91C_PA12_NPCS00 ((unsigned int) AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0\r
+#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13\r
+#define AT91C_PA13_NPCS01 ((unsigned int) AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1\r
+#define AT91C_PA13_PCK1 ((unsigned int) AT91C_PIO_PA13) // PMC Programmable Clock Output 1\r
+#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14\r
+#define AT91C_PA14_NPCS02 ((unsigned int) AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2\r
+#define AT91C_PA14_IRQ1 ((unsigned int) AT91C_PIO_PA14) // External Interrupt 1\r
+#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15\r
+#define AT91C_PA15_NPCS03 ((unsigned int) AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3\r
+#define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input\r
+#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16\r
+#define AT91C_PA16_MISO0 ((unsigned int) AT91C_PIO_PA16) // SPI 0 Master In Slave\r
+#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17\r
+#define AT91C_PA17_MOSI0 ((unsigned int) AT91C_PIO_PA17) // SPI 0 Master Out Slave\r
+#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18\r
+#define AT91C_PA18_SPCK0 ((unsigned int) AT91C_PIO_PA18) // SPI 0 Serial Clock\r
+#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19\r
+#define AT91C_PA19_CANRX ((unsigned int) AT91C_PIO_PA19) // CAN Receive\r
+#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2\r
+#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock\r
+#define AT91C_PA2_NPCS11 ((unsigned int) AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1\r
+#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20\r
+#define AT91C_PA20_CANTX ((unsigned int) AT91C_PIO_PA20) // CAN Transmit\r
+#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21\r
+#define AT91C_PA21_TF ((unsigned int) AT91C_PIO_PA21) // SSC Transmit Frame Sync\r
+#define AT91C_PA21_NPCS10 ((unsigned int) AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0\r
+#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22\r
+#define AT91C_PA22_TK ((unsigned int) AT91C_PIO_PA22) // SSC Transmit Clock\r
+#define AT91C_PA22_SPCK1 ((unsigned int) AT91C_PIO_PA22) // SPI 1 Serial Clock\r
+#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23\r
+#define AT91C_PA23_TD ((unsigned int) AT91C_PIO_PA23) // SSC Transmit data\r
+#define AT91C_PA23_MOSI1 ((unsigned int) AT91C_PIO_PA23) // SPI 1 Master Out Slave\r
+#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24\r
+#define AT91C_PA24_RD ((unsigned int) AT91C_PIO_PA24) // SSC Receive Data\r
+#define AT91C_PA24_MISO1 ((unsigned int) AT91C_PIO_PA24) // SPI 1 Master In Slave\r
+#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25\r
+#define AT91C_PA25_RK ((unsigned int) AT91C_PIO_PA25) // SSC Receive Clock\r
+#define AT91C_PA25_NPCS11 ((unsigned int) AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1\r
+#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26\r
+#define AT91C_PA26_RF ((unsigned int) AT91C_PIO_PA26) // SSC Receive Frame Sync\r
+#define AT91C_PA26_NPCS12 ((unsigned int) AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2\r
+#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27\r
+#define AT91C_PA27_DRXD ((unsigned int) AT91C_PIO_PA27) // DBGU Debug Receive Data\r
+#define AT91C_PA27_PCK3 ((unsigned int) AT91C_PIO_PA27) // PMC Programmable Clock Output 3\r
+#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28\r
+#define AT91C_PA28_DTXD ((unsigned int) AT91C_PIO_PA28) // DBGU Debug Transmit Data\r
+#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29\r
+#define AT91C_PA29_FIQ ((unsigned int) AT91C_PIO_PA29) // AIC Fast Interrupt Input\r
+#define AT91C_PA29_NPCS13 ((unsigned int) AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3\r
+#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3\r
+#define AT91C_PA3_RTS0 ((unsigned int) AT91C_PIO_PA3) // USART 0 Ready To Send\r
+#define AT91C_PA3_NPCS12 ((unsigned int) AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2\r
+#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30\r
+#define AT91C_PA30_IRQ0 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 0\r
+#define AT91C_PA30_PCK2 ((unsigned int) AT91C_PIO_PA30) // PMC Programmable Clock Output 2\r
+#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4\r
+#define AT91C_PA4_CTS0 ((unsigned int) AT91C_PIO_PA4) // USART 0 Clear To Send\r
+#define AT91C_PA4_NPCS13 ((unsigned int) AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3\r
+#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5\r
+#define AT91C_PA5_RXD1 ((unsigned int) AT91C_PIO_PA5) // USART 1 Receive Data\r
+#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6\r
+#define AT91C_PA6_TXD1 ((unsigned int) AT91C_PIO_PA6) // USART 1 Transmit Data\r
+#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7\r
+#define AT91C_PA7_SCK1 ((unsigned int) AT91C_PIO_PA7) // USART 1 Serial Clock\r
+#define AT91C_PA7_NPCS01 ((unsigned int) AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1\r
+#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8\r
+#define AT91C_PA8_RTS1 ((unsigned int) AT91C_PIO_PA8) // USART 1 Ready To Send\r
+#define AT91C_PA8_NPCS02 ((unsigned int) AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2\r
+#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9\r
+#define AT91C_PA9_CTS1 ((unsigned int) AT91C_PIO_PA9) // USART 1 Clear To Send\r
+#define AT91C_PA9_NPCS03 ((unsigned int) AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3\r
+#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0\r
+#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock\r
+#define AT91C_PB0_PCK0 ((unsigned int) AT91C_PIO_PB0) // PMC Programmable Clock Output 0\r
+#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1\r
+#define AT91C_PB1_ETXEN ((unsigned int) AT91C_PIO_PB1) // Ethernet MAC Transmit Enable\r
+#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10\r
+#define AT91C_PB10_ETX2 ((unsigned int) AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2\r
+#define AT91C_PB10_NPCS11 ((unsigned int) AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1\r
+#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11\r
+#define AT91C_PB11_ETX3 ((unsigned int) AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3\r
+#define AT91C_PB11_NPCS12 ((unsigned int) AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2\r
+#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12\r
+#define AT91C_PB12_ETXER ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error\r
+#define AT91C_PB12_TCLK0 ((unsigned int) AT91C_PIO_PB12) // Timer Counter 0 external clock input\r
+#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13\r
+#define AT91C_PB13_ERX2 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Receive Data 2\r
+#define AT91C_PB13_NPCS01 ((unsigned int) AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1\r
+#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14\r
+#define AT91C_PB14_ERX3 ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Receive Data 3\r
+#define AT91C_PB14_NPCS02 ((unsigned int) AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2\r
+#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15\r
+#define AT91C_PB15_ERXDV ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid\r
+#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16\r
+#define AT91C_PB16_ECOL ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Collision Detected\r
+#define AT91C_PB16_NPCS13 ((unsigned int) AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3\r
+#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17\r
+#define AT91C_PB17_ERXCK ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Clock\r
+#define AT91C_PB17_NPCS03 ((unsigned int) AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3\r
+#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18\r
+#define AT91C_PB18_EF100 ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec\r
+#define AT91C_PB18_ADTRG ((unsigned int) AT91C_PIO_PB18) // ADC External Trigger\r
+#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19\r
+#define AT91C_PB19_PWM0 ((unsigned int) AT91C_PIO_PB19) // PWM Channel 0\r
+#define AT91C_PB19_TCLK1 ((unsigned int) AT91C_PIO_PB19) // Timer Counter 1 external clock input\r
+#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2\r
+#define AT91C_PB2_ETX0 ((unsigned int) AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0\r
+#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20\r
+#define AT91C_PB20_PWM1 ((unsigned int) AT91C_PIO_PB20) // PWM Channel 1\r
+#define AT91C_PB20_PCK0 ((unsigned int) AT91C_PIO_PB20) // PMC Programmable Clock Output 0\r
+#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21\r
+#define AT91C_PB21_PWM2 ((unsigned int) AT91C_PIO_PB21) // PWM Channel 2\r
+#define AT91C_PB21_PCK1 ((unsigned int) AT91C_PIO_PB21) // PMC Programmable Clock Output 1\r
+#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22\r
+#define AT91C_PB22_PWM3 ((unsigned int) AT91C_PIO_PB22) // PWM Channel 3\r
+#define AT91C_PB22_PCK2 ((unsigned int) AT91C_PIO_PB22) // PMC Programmable Clock Output 2\r
+#define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23\r
+#define AT91C_PB23_TIOA0 ((unsigned int) AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A\r
+#define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect\r
+#define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24\r
+#define AT91C_PB24_TIOB0 ((unsigned int) AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B\r
+#define AT91C_PB24_DSR1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Data Set ready\r
+#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25\r
+#define AT91C_PB25_TIOA1 ((unsigned int) AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A\r
+#define AT91C_PB25_DTR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Terminal ready\r
+#define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26\r
+#define AT91C_PB26_TIOB1 ((unsigned int) AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B\r
+#define AT91C_PB26_RI1 ((unsigned int) AT91C_PIO_PB26) // USART 1 Ring Indicator\r
+#define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27\r
+#define AT91C_PB27_TIOA2 ((unsigned int) AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A\r
+#define AT91C_PB27_PWM0 ((unsigned int) AT91C_PIO_PB27) // PWM Channel 0\r
+#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28\r
+#define AT91C_PB28_TIOB2 ((unsigned int) AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B\r
+#define AT91C_PB28_PWM1 ((unsigned int) AT91C_PIO_PB28) // PWM Channel 1\r
+#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29\r
+#define AT91C_PB29_PCK1 ((unsigned int) AT91C_PIO_PB29) // PMC Programmable Clock Output 1\r
+#define AT91C_PB29_PWM2 ((unsigned int) AT91C_PIO_PB29) // PWM Channel 2\r
+#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3\r
+#define AT91C_PB3_ETX1 ((unsigned int) AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1\r
+#define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30\r
+#define AT91C_PB30_PCK2 ((unsigned int) AT91C_PIO_PB30) // PMC Programmable Clock Output 2\r
+#define AT91C_PB30_PWM3 ((unsigned int) AT91C_PIO_PB30) // PWM Channel 3\r
+#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4\r
+#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid\r
+#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5\r
+#define AT91C_PB5_ERX0 ((unsigned int) AT91C_PIO_PB5) // Ethernet MAC Receive Data 0\r
+#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6\r
+#define AT91C_PB6_ERX1 ((unsigned int) AT91C_PIO_PB6) // Ethernet MAC Receive Data 1\r
+#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7\r
+#define AT91C_PB7_ERXER ((unsigned int) AT91C_PIO_PB7) // Ethernet MAC Receive Error\r
+#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8\r
+#define AT91C_PB8_EMDC ((unsigned int) AT91C_PIO_PB8) // Ethernet MAC Management Data Clock\r
+#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9\r
+#define AT91C_PB9_EMDIO ((unsigned int) AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output\r
+\r
+// *****************************************************************************\r
+// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256\r
+// *****************************************************************************\r
+#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ)\r
+#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral\r
+#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller A\r
+#define AT91C_ID_PIOB ((unsigned int) 3) // Parallel IO Controller B\r
+#define AT91C_ID_SPI0 ((unsigned int) 4) // Serial Peripheral Interface 0\r
+#define AT91C_ID_SPI1 ((unsigned int) 5) // Serial Peripheral Interface 1\r
+#define AT91C_ID_US0 ((unsigned int) 6) // USART 0\r
+#define AT91C_ID_US1 ((unsigned int) 7) // USART 1\r
+#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller\r
+#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface\r
+#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller\r
+#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port\r
+#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0\r
+#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1\r
+#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2\r
+#define AT91C_ID_CAN ((unsigned int) 15) // Control Area Network Controller\r
+#define AT91C_ID_EMAC ((unsigned int) 16) // Ethernet MAC\r
+#define AT91C_ID_ADC ((unsigned int) 17) // Analog-to-Digital Converter\r
+#define AT91C_ID_AES ((unsigned int) 18) // Advanced Encryption Standard 128-bit\r
+#define AT91C_ID_TDES ((unsigned int) 19) // Triple Data Encryption Standard\r
+#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved\r
+#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved\r
+#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved\r
+#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved\r
+#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved\r
+#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved\r
+#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved\r
+#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved\r
+#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved\r
+#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved\r
+#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0)\r
+#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1)\r
+\r
+// *****************************************************************************\r
+// BASE ADDRESS DEFINITIONS FOR AT91SAM7X256\r
+// *****************************************************************************\r
+#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address\r
+#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address\r
+#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address\r
+#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address\r
+#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address\r
+#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address\r
+#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address\r
+#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address\r
+#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address\r
+#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address\r
+#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address\r
+#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address\r
+#define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address\r
+#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address\r
+#define AT91C_BASE_PDC_SPI1 ((AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address\r
+#define AT91C_BASE_SPI1 ((AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address\r
+#define AT91C_BASE_PDC_SPI0 ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address\r
+#define AT91C_BASE_SPI0 ((AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address\r
+#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address\r
+#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address\r
+#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address\r
+#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address\r
+#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address\r
+#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address\r
+#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address\r
+#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address\r
+#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address\r
+#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address\r
+#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address\r
+#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address\r
+#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address\r
+#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address\r
+#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address\r
+#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address\r
+#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address\r
+#define AT91C_BASE_CAN_MB0 ((AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address\r
+#define AT91C_BASE_CAN_MB1 ((AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address\r
+#define AT91C_BASE_CAN_MB2 ((AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address\r
+#define AT91C_BASE_CAN_MB3 ((AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address\r
+#define AT91C_BASE_CAN_MB4 ((AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address\r
+#define AT91C_BASE_CAN_MB5 ((AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address\r
+#define AT91C_BASE_CAN_MB6 ((AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address\r
+#define AT91C_BASE_CAN_MB7 ((AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address\r
+#define AT91C_BASE_CAN ((AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address\r
+#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address\r
+#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address\r
+#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address\r
+#define AT91C_BASE_PDC_AES ((AT91PS_PDC) 0xFFFA4100) // (PDC_AES) Base Address\r
+#define AT91C_BASE_AES ((AT91PS_AES) 0xFFFA4000) // (AES) Base Address\r
+#define AT91C_BASE_PDC_TDES ((AT91PS_PDC) 0xFFFA8100) // (PDC_TDES) Base Address\r
+#define AT91C_BASE_TDES ((AT91PS_TDES) 0xFFFA8000) // (TDES) Base Address\r
+\r
+// *****************************************************************************\r
+// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256\r
+// *****************************************************************************\r
+#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address\r
+#define AT91C_ISRAM_SIZE ((unsigned int) 0x00010000) // Internal SRAM size in byte (64 Kbyte)\r
+#define AT91C_IFLASH ((char *) 0x00100000) // Internal ROM base address\r
+#define AT91C_IFLASH_SIZE ((unsigned int) 0x00040000) // Internal ROM size in byte (256 Kbyte)\r
+\r
+\r
+\r
+// - Hardware register definition\r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR System Peripherals\r
+// - *****************************************************************************\r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Advanced Interrupt Controller\r
+// - *****************************************************************************\r
+// - -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- \r
+#if 0 /*_RB_*/\r
+AT91C_AIC_PRIOR EQU (0x7 << 0) ;- (AIC) Priority Level\r
+AT91C_AIC_PRIOR_LOWEST EQU (0x0) ;- (AIC) Lowest priority level\r
+AT91C_AIC_PRIOR_HIGHEST EQU (0x7) ;- (AIC) Highest priority level\r
+AT91C_AIC_SRCTYPE EQU (0x3 << 5) ;- (AIC) Interrupt Source Type\r
+AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL EQU (0x0 << 5) ;- (AIC) Internal Sources Code Label High-level Sensitive\r
+AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL EQU (0x0 << 5) ;- (AIC) External Sources Code Label Low-level Sensitive\r
+AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE EQU (0x1 << 5) ;- (AIC) Internal Sources Code Label Positive Edge triggered\r
+AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE EQU (0x1 << 5) ;- (AIC) External Sources Code Label Negative Edge triggered\r
+AT91C_AIC_SRCTYPE_HIGH_LEVEL EQU (0x2 << 5) ;- (AIC) Internal Or External Sources Code Label High-level Sensitive\r
+AT91C_AIC_SRCTYPE_POSITIVE_EDGE EQU (0x3 << 5) ;- (AIC) Internal Or External Sources Code Label Positive Edge triggered\r
+// - -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- \r
+AT91C_AIC_NFIQ EQU (0x1 << 0) ;- (AIC) NFIQ Status\r
+AT91C_AIC_NIRQ EQU (0x1 << 1) ;- (AIC) NIRQ Status\r
+// - -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- \r
+AT91C_AIC_DCR_PROT EQU (0x1 << 0) ;- (AIC) Protection Mode\r
+AT91C_AIC_DCR_GMSK EQU (0x1 << 1) ;- (AIC) General Mask\r
+#endif\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Peripheral DMA Controller\r
+// - *****************************************************************************\r
+// - -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- \r
+AT91C_PDC_RXTEN EQU (0x1 << 0) ;- (PDC) Receiver Transfer Enable\r
+AT91C_PDC_RXTDIS EQU (0x1 << 1) ;- (PDC) Receiver Transfer Disable\r
+AT91C_PDC_TXTEN EQU (0x1 << 8) ;- (PDC) Transmitter Transfer Enable\r
+AT91C_PDC_TXTDIS EQU (0x1 << 9) ;- (PDC) Transmitter Transfer Disable\r
+// - -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- \r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Debug Unit\r
+// - *****************************************************************************\r
+// - -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- \r
+AT91C_US_RSTRX EQU (0x1 << 2) ;- (DBGU) Reset Receiver\r
+AT91C_US_RSTTX EQU (0x1 << 3) ;- (DBGU) Reset Transmitter\r
+AT91C_US_RXEN EQU (0x1 << 4) ;- (DBGU) Receiver Enable\r
+AT91C_US_RXDIS EQU (0x1 << 5) ;- (DBGU) Receiver Disable\r
+AT91C_US_TXEN EQU (0x1 << 6) ;- (DBGU) Transmitter Enable\r
+AT91C_US_TXDIS EQU (0x1 << 7) ;- (DBGU) Transmitter Disable\r
+AT91C_US_RSTSTA EQU (0x1 << 8) ;- (DBGU) Reset Status Bits\r
+// - -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- \r
+AT91C_US_PAR EQU (0x7 << 9) ;- (DBGU) Parity type\r
+AT91C_US_PAR_EVEN EQU (0x0 << 9) ;- (DBGU) Even Parity\r
+AT91C_US_PAR_ODD EQU (0x1 << 9) ;- (DBGU) Odd Parity\r
+AT91C_US_PAR_SPACE EQU (0x2 << 9) ;- (DBGU) Parity forced to 0 (Space)\r
+AT91C_US_PAR_MARK EQU (0x3 << 9) ;- (DBGU) Parity forced to 1 (Mark)\r
+AT91C_US_PAR_NONE EQU (0x4 << 9) ;- (DBGU) No Parity\r
+AT91C_US_PAR_MULTI_DROP EQU (0x6 << 9) ;- (DBGU) Multi-drop mode\r
+AT91C_US_CHMODE EQU (0x3 << 14) ;- (DBGU) Channel Mode\r
+AT91C_US_CHMODE_NORMAL EQU (0x0 << 14) ;- (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.\r
+AT91C_US_CHMODE_AUTO EQU (0x1 << 14) ;- (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.\r
+AT91C_US_CHMODE_LOCAL EQU (0x2 << 14) ;- (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.\r
+AT91C_US_CHMODE_REMOTE EQU (0x3 << 14) ;- (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.\r
+// - -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- \r
+AT91C_US_RXRDY EQU (0x1 << 0) ;- (DBGU) RXRDY Interrupt\r
+AT91C_US_TXRDY EQU (0x1 << 1) ;- (DBGU) TXRDY Interrupt\r
+AT91C_US_ENDRX EQU (0x1 << 3) ;- (DBGU) End of Receive Transfer Interrupt\r
+AT91C_US_ENDTX EQU (0x1 << 4) ;- (DBGU) End of Transmit Interrupt\r
+AT91C_US_OVRE EQU (0x1 << 5) ;- (DBGU) Overrun Interrupt\r
+AT91C_US_FRAME EQU (0x1 << 6) ;- (DBGU) Framing Error Interrupt\r
+AT91C_US_PARE EQU (0x1 << 7) ;- (DBGU) Parity Error Interrupt\r
+AT91C_US_TXEMPTY EQU (0x1 << 9) ;- (DBGU) TXEMPTY Interrupt\r
+AT91C_US_TXBUFE EQU (0x1 << 11) ;- (DBGU) TXBUFE Interrupt\r
+AT91C_US_RXBUFF EQU (0x1 << 12) ;- (DBGU) RXBUFF Interrupt\r
+AT91C_US_COMM_TX EQU (0x1 << 30) ;- (DBGU) COMM_TX Interrupt\r
+AT91C_US_COMM_RX EQU (0x1 << 31) ;- (DBGU) COMM_RX Interrupt\r
+// - -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- \r
+// - -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- \r
+// - -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- \r
+// - -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- \r
+AT91C_US_FORCE_NTRST EQU (0x1 << 0) ;- (DBGU) Force NTRST in JTAG\r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Parallel Input Output Controler\r
+// - *****************************************************************************\r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Clock Generator Controler\r
+// - *****************************************************************************\r
+// - -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- \r
+AT91C_CKGR_MOSCEN EQU (0x1 << 0) ;- (CKGR) Main Oscillator Enable\r
+AT91C_CKGR_OSCBYPASS EQU (0x1 << 1) ;- (CKGR) Main Oscillator Bypass\r
+AT91C_CKGR_OSCOUNT EQU (0xFF << 8) ;- (CKGR) Main Oscillator Start-up Time\r
+// - -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- \r
+AT91C_CKGR_MAINF EQU (0xFFFF << 0) ;- (CKGR) Main Clock Frequency\r
+AT91C_CKGR_MAINRDY EQU (0x1 << 16) ;- (CKGR) Main Clock Ready\r
+// - -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- \r
+AT91C_CKGR_DIV EQU (0xFF << 0) ;- (CKGR) Divider Selected\r
+AT91C_CKGR_DIV_0 EQU (0x0) ;- (CKGR) Divider output is 0\r
+AT91C_CKGR_DIV_BYPASS EQU (0x1) ;- (CKGR) Divider is bypassed\r
+AT91C_CKGR_PLLCOUNT EQU (0x3F << 8) ;- (CKGR) PLL Counter\r
+AT91C_CKGR_OUT EQU (0x3 << 14) ;- (CKGR) PLL Output Frequency Range\r
+AT91C_CKGR_OUT_0 EQU (0x0 << 14) ;- (CKGR) Please refer to the PLL datasheet\r
+AT91C_CKGR_OUT_1 EQU (0x1 << 14) ;- (CKGR) Please refer to the PLL datasheet\r
+AT91C_CKGR_OUT_2 EQU (0x2 << 14) ;- (CKGR) Please refer to the PLL datasheet\r
+AT91C_CKGR_OUT_3 EQU (0x3 << 14) ;- (CKGR) Please refer to the PLL datasheet\r
+AT91C_CKGR_MUL EQU (0x7FF << 16) ;- (CKGR) PLL Multiplier\r
+AT91C_CKGR_USBDIV EQU (0x3 << 28) ;- (CKGR) Divider for USB Clocks\r
+AT91C_CKGR_USBDIV_0 EQU (0x0 << 28) ;- (CKGR) Divider output is PLL clock output\r
+AT91C_CKGR_USBDIV_1 EQU (0x1 << 28) ;- (CKGR) Divider output is PLL clock output divided by 2\r
+AT91C_CKGR_USBDIV_2 EQU (0x2 << 28) ;- (CKGR) Divider output is PLL clock output divided by 4\r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Power Management Controler\r
+// - *****************************************************************************\r
+// - -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- \r
+AT91C_PMC_PCK EQU (0x1 << 0) ;- (PMC) Processor Clock\r
+AT91C_PMC_UDP EQU (0x1 << 7) ;- (PMC) USB Device Port Clock\r
+AT91C_PMC_PCK0 EQU (0x1 << 8) ;- (PMC) Programmable Clock Output\r
+AT91C_PMC_PCK1 EQU (0x1 << 9) ;- (PMC) Programmable Clock Output\r
+AT91C_PMC_PCK2 EQU (0x1 << 10) ;- (PMC) Programmable Clock Output\r
+AT91C_PMC_PCK3 EQU (0x1 << 11) ;- (PMC) Programmable Clock Output\r
+// - -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- \r
+// - -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- \r
+// - -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- \r
+// - -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- \r
+// - -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- \r
+// - -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- \r
+AT91C_PMC_CSS EQU (0x3 << 0) ;- (PMC) Programmable Clock Selection\r
+AT91C_PMC_CSS_SLOW_CLK EQU (0x0) ;- (PMC) Slow Clock is selected\r
+AT91C_PMC_CSS_MAIN_CLK EQU (0x1) ;- (PMC) Main Clock is selected\r
+AT91C_PMC_CSS_PLL_CLK EQU (0x3) ;- (PMC) Clock from PLL is selected\r
+AT91C_PMC_PRES EQU (0x7 << 2) ;- (PMC) Programmable Clock Prescaler\r
+AT91C_PMC_PRES_CLK EQU (0x0 << 2) ;- (PMC) Selected clock\r
+AT91C_PMC_PRES_CLK_2 EQU (0x1 << 2) ;- (PMC) Selected clock divided by 2\r
+AT91C_PMC_PRES_CLK_4 EQU (0x2 << 2) ;- (PMC) Selected clock divided by 4\r
+AT91C_PMC_PRES_CLK_8 EQU (0x3 << 2) ;- (PMC) Selected clock divided by 8\r
+AT91C_PMC_PRES_CLK_16 EQU (0x4 << 2) ;- (PMC) Selected clock divided by 16\r
+AT91C_PMC_PRES_CLK_32 EQU (0x5 << 2) ;- (PMC) Selected clock divided by 32\r
+AT91C_PMC_PRES_CLK_64 EQU (0x6 << 2) ;- (PMC) Selected clock divided by 64\r
+// - -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- \r
+// - -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- \r
+AT91C_PMC_MOSCS EQU (0x1 << 0) ;- (PMC) MOSC Status/Enable/Disable/Mask\r
+AT91C_PMC_LOCK EQU (0x1 << 2) ;- (PMC) PLL Status/Enable/Disable/Mask\r
+AT91C_PMC_MCKRDY EQU (0x1 << 3) ;- (PMC) MCK_RDY Status/Enable/Disable/Mask\r
+AT91C_PMC_PCK0RDY EQU (0x1 << 8) ;- (PMC) PCK0_RDY Status/Enable/Disable/Mask\r
+AT91C_PMC_PCK1RDY EQU (0x1 << 9) ;- (PMC) PCK1_RDY Status/Enable/Disable/Mask\r
+AT91C_PMC_PCK2RDY EQU (0x1 << 10) ;- (PMC) PCK2_RDY Status/Enable/Disable/Mask\r
+AT91C_PMC_PCK3RDY EQU (0x1 << 11) ;- (PMC) PCK3_RDY Status/Enable/Disable/Mask\r
+// - -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- \r
+// - -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- \r
+// - -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- \r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Reset Controller Interface\r
+// - *****************************************************************************\r
+// - -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- \r
+AT91C_RSTC_PROCRST EQU (0x1 << 0) ;- (RSTC) Processor Reset\r
+AT91C_RSTC_PERRST EQU (0x1 << 2) ;- (RSTC) Peripheral Reset\r
+AT91C_RSTC_EXTRST EQU (0x1 << 3) ;- (RSTC) External Reset\r
+AT91C_RSTC_KEY EQU (0xFF << 24) ;- (RSTC) Password\r
+// - -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- \r
+AT91C_RSTC_URSTS EQU (0x1 << 0) ;- (RSTC) User Reset Status\r
+AT91C_RSTC_BODSTS EQU (0x1 << 1) ;- (RSTC) Brownout Detection Status\r
+AT91C_RSTC_RSTTYP EQU (0x7 << 8) ;- (RSTC) Reset Type\r
+AT91C_RSTC_RSTTYP_POWERUP EQU (0x0 << 8) ;- (RSTC) Power-up Reset. VDDCORE rising.\r
+AT91C_RSTC_RSTTYP_WAKEUP EQU (0x1 << 8) ;- (RSTC) WakeUp Reset. VDDCORE rising.\r
+AT91C_RSTC_RSTTYP_WATCHDOG EQU (0x2 << 8) ;- (RSTC) Watchdog Reset. Watchdog overflow occured.\r
+AT91C_RSTC_RSTTYP_SOFTWARE EQU (0x3 << 8) ;- (RSTC) Software Reset. Processor reset required by the software.\r
+AT91C_RSTC_RSTTYP_USER EQU (0x4 << 8) ;- (RSTC) User Reset. NRST pin detected low.\r
+AT91C_RSTC_RSTTYP_BROWNOUT EQU (0x5 << 8) ;- (RSTC) Brownout Reset occured.\r
+AT91C_RSTC_NRSTL EQU (0x1 << 16) ;- (RSTC) NRST pin level\r
+AT91C_RSTC_SRCMP EQU (0x1 << 17) ;- (RSTC) Software Reset Command in Progress.\r
+// - -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- \r
+AT91C_RSTC_URSTEN EQU (0x1 << 0) ;- (RSTC) User Reset Enable\r
+AT91C_RSTC_URSTIEN EQU (0x1 << 4) ;- (RSTC) User Reset Interrupt Enable\r
+AT91C_RSTC_ERSTL EQU (0xF << 8) ;- (RSTC) User Reset Enable\r
+AT91C_RSTC_BODIEN EQU (0x1 << 16) ;- (RSTC) Brownout Detection Interrupt Enable\r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface\r
+// - *****************************************************************************\r
+// - -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- \r
+AT91C_RTTC_RTPRES EQU (0xFFFF << 0) ;- (RTTC) Real-time Timer Prescaler Value\r
+AT91C_RTTC_ALMIEN EQU (0x1 << 16) ;- (RTTC) Alarm Interrupt Enable\r
+AT91C_RTTC_RTTINCIEN EQU (0x1 << 17) ;- (RTTC) Real Time Timer Increment Interrupt Enable\r
+AT91C_RTTC_RTTRST EQU (0x1 << 18) ;- (RTTC) Real Time Timer Restart\r
+// - -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- \r
+AT91C_RTTC_ALMV EQU (0x0 << 0) ;- (RTTC) Alarm Value\r
+// - -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- \r
+AT91C_RTTC_CRTV EQU (0x0 << 0) ;- (RTTC) Current Real-time Value\r
+// - -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- \r
+AT91C_RTTC_ALMS EQU (0x1 << 0) ;- (RTTC) Real-time Alarm Status\r
+AT91C_RTTC_RTTINC EQU (0x1 << 1) ;- (RTTC) Real-time Timer Increment\r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface\r
+// - *****************************************************************************\r
+// - -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- \r
+AT91C_PITC_PIV EQU (0xFFFFF << 0) ;- (PITC) Periodic Interval Value\r
+AT91C_PITC_PITEN EQU (0x1 << 24) ;- (PITC) Periodic Interval Timer Enabled\r
+AT91C_PITC_PITIEN EQU (0x1 << 25) ;- (PITC) Periodic Interval Timer Interrupt Enable\r
+// - -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- \r
+AT91C_PITC_PITS EQU (0x1 << 0) ;- (PITC) Periodic Interval Timer Status\r
+// - -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- \r
+AT91C_PITC_CPIV EQU (0xFFFFF << 0) ;- (PITC) Current Periodic Interval Value\r
+AT91C_PITC_PICNT EQU (0xFFF << 20) ;- (PITC) Periodic Interval Counter\r
+// - -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- \r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface\r
+// - *****************************************************************************\r
+// - -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- \r
+AT91C_WDTC_WDRSTT EQU (0x1 << 0) ;- (WDTC) Watchdog Restart\r
+AT91C_WDTC_KEY EQU (0xFF << 24) ;- (WDTC) Watchdog KEY Password\r
+// - -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- \r
+AT91C_WDTC_WDV EQU (0xFFF << 0) ;- (WDTC) Watchdog Timer Restart\r
+AT91C_WDTC_WDFIEN EQU (0x1 << 12) ;- (WDTC) Watchdog Fault Interrupt Enable\r
+AT91C_WDTC_WDRSTEN EQU (0x1 << 13) ;- (WDTC) Watchdog Reset Enable\r
+AT91C_WDTC_WDRPROC EQU (0x1 << 14) ;- (WDTC) Watchdog Timer Restart\r
+AT91C_WDTC_WDDIS EQU (0x1 << 15) ;- (WDTC) Watchdog Disable\r
+AT91C_WDTC_WDD EQU (0xFFF << 16) ;- (WDTC) Watchdog Delta Value\r
+AT91C_WDTC_WDDBGHLT EQU (0x1 << 28) ;- (WDTC) Watchdog Debug Halt\r
+AT91C_WDTC_WDIDLEHLT EQU (0x1 << 29) ;- (WDTC) Watchdog Idle Halt\r
+// - -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- \r
+AT91C_WDTC_WDUNF EQU (0x1 << 0) ;- (WDTC) Watchdog Underflow\r
+AT91C_WDTC_WDERR EQU (0x1 << 1) ;- (WDTC) Watchdog Error\r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface\r
+// - *****************************************************************************\r
+// - -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- \r
+AT91C_VREG_PSTDBY EQU (0x1 << 0) ;- (VREG) Voltage Regulator Power Standby Mode\r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Memory Controller Interface\r
+// - *****************************************************************************\r
+// - -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- \r
+AT91C_MC_RCB EQU (0x1 << 0) ;- (MC) Remap Command Bit\r
+// - -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- \r
+AT91C_MC_UNDADD EQU (0x1 << 0) ;- (MC) Undefined Addess Abort Status\r
+AT91C_MC_MISADD EQU (0x1 << 1) ;- (MC) Misaligned Addess Abort Status\r
+AT91C_MC_ABTSZ EQU (0x3 << 8) ;- (MC) Abort Size Status\r
+AT91C_MC_ABTSZ_BYTE EQU (0x0 << 8) ;- (MC) Byte\r
+AT91C_MC_ABTSZ_HWORD EQU (0x1 << 8) ;- (MC) Half-word\r
+AT91C_MC_ABTSZ_WORD EQU (0x2 << 8) ;- (MC) Word\r
+AT91C_MC_ABTTYP EQU (0x3 << 10) ;- (MC) Abort Type Status\r
+AT91C_MC_ABTTYP_DATAR EQU (0x0 << 10) ;- (MC) Data Read\r
+AT91C_MC_ABTTYP_DATAW EQU (0x1 << 10) ;- (MC) Data Write\r
+AT91C_MC_ABTTYP_FETCH EQU (0x2 << 10) ;- (MC) Code Fetch\r
+AT91C_MC_MST0 EQU (0x1 << 16) ;- (MC) Master 0 Abort Source\r
+AT91C_MC_MST1 EQU (0x1 << 17) ;- (MC) Master 1 Abort Source\r
+AT91C_MC_SVMST0 EQU (0x1 << 24) ;- (MC) Saved Master 0 Abort Source\r
+AT91C_MC_SVMST1 EQU (0x1 << 25) ;- (MC) Saved Master 1 Abort Source\r
+// - -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- \r
+AT91C_MC_FRDY EQU (0x1 << 0) ;- (MC) Flash Ready\r
+AT91C_MC_LOCKE EQU (0x1 << 2) ;- (MC) Lock Error\r
+AT91C_MC_PROGE EQU (0x1 << 3) ;- (MC) Programming Error\r
+AT91C_MC_NEBP EQU (0x1 << 7) ;- (MC) No Erase Before Programming\r
+AT91C_MC_FWS EQU (0x3 << 8) ;- (MC) Flash Wait State\r
+AT91C_MC_FWS_0FWS EQU (0x0 << 8) ;- (MC) 1 cycle for Read, 2 for Write operations\r
+AT91C_MC_FWS_1FWS EQU (0x1 << 8) ;- (MC) 2 cycles for Read, 3 for Write operations\r
+AT91C_MC_FWS_2FWS EQU (0x2 << 8) ;- (MC) 3 cycles for Read, 4 for Write operations\r
+AT91C_MC_FWS_3FWS EQU (0x3 << 8) ;- (MC) 4 cycles for Read, 4 for Write operations\r
+AT91C_MC_FMCN EQU (0xFF << 16) ;- (MC) Flash Microsecond Cycle Number\r
+// - -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- \r
+AT91C_MC_FCMD EQU (0xF << 0) ;- (MC) Flash Command\r
+AT91C_MC_FCMD_START_PROG EQU (0x1) ;- (MC) Starts the programming of th epage specified by PAGEN.\r
+AT91C_MC_FCMD_LOCK EQU (0x2) ;- (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.\r
+AT91C_MC_FCMD_PROG_AND_LOCK EQU (0x3) ;- (MC) The lock sequence automatically happens after the programming sequence is completed.\r
+AT91C_MC_FCMD_UNLOCK EQU (0x4) ;- (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.\r
+AT91C_MC_FCMD_ERASE_ALL EQU (0x8) ;- (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.\r
+AT91C_MC_FCMD_SET_GP_NVM EQU (0xB) ;- (MC) Set General Purpose NVM bits.\r
+AT91C_MC_FCMD_CLR_GP_NVM EQU (0xD) ;- (MC) Clear General Purpose NVM bits.\r
+AT91C_MC_FCMD_SET_SECURITY EQU (0xF) ;- (MC) Set Security Bit.\r
+AT91C_MC_PAGEN EQU (0x3FF << 8) ;- (MC) Page Number\r
+AT91C_MC_KEY EQU (0xFF << 24) ;- (MC) Writing Protect Key\r
+// - -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- \r
+AT91C_MC_SECURITY EQU (0x1 << 4) ;- (MC) Security Bit Status\r
+AT91C_MC_GPNVM0 EQU (0x1 << 8) ;- (MC) Sector 0 Lock Status\r
+AT91C_MC_GPNVM1 EQU (0x1 << 9) ;- (MC) Sector 1 Lock Status\r
+AT91C_MC_GPNVM2 EQU (0x1 << 10) ;- (MC) Sector 2 Lock Status\r
+AT91C_MC_GPNVM3 EQU (0x1 << 11) ;- (MC) Sector 3 Lock Status\r
+AT91C_MC_GPNVM4 EQU (0x1 << 12) ;- (MC) Sector 4 Lock Status\r
+AT91C_MC_GPNVM5 EQU (0x1 << 13) ;- (MC) Sector 5 Lock Status\r
+AT91C_MC_GPNVM6 EQU (0x1 << 14) ;- (MC) Sector 6 Lock Status\r
+AT91C_MC_GPNVM7 EQU (0x1 << 15) ;- (MC) Sector 7 Lock Status\r
+AT91C_MC_LOCKS0 EQU (0x1 << 16) ;- (MC) Sector 0 Lock Status\r
+AT91C_MC_LOCKS1 EQU (0x1 << 17) ;- (MC) Sector 1 Lock Status\r
+AT91C_MC_LOCKS2 EQU (0x1 << 18) ;- (MC) Sector 2 Lock Status\r
+AT91C_MC_LOCKS3 EQU (0x1 << 19) ;- (MC) Sector 3 Lock Status\r
+AT91C_MC_LOCKS4 EQU (0x1 << 20) ;- (MC) Sector 4 Lock Status\r
+AT91C_MC_LOCKS5 EQU (0x1 << 21) ;- (MC) Sector 5 Lock Status\r
+AT91C_MC_LOCKS6 EQU (0x1 << 22) ;- (MC) Sector 6 Lock Status\r
+AT91C_MC_LOCKS7 EQU (0x1 << 23) ;- (MC) Sector 7 Lock Status\r
+AT91C_MC_LOCKS8 EQU (0x1 << 24) ;- (MC) Sector 8 Lock Status\r
+AT91C_MC_LOCKS9 EQU (0x1 << 25) ;- (MC) Sector 9 Lock Status\r
+AT91C_MC_LOCKS10 EQU (0x1 << 26) ;- (MC) Sector 10 Lock Status\r
+AT91C_MC_LOCKS11 EQU (0x1 << 27) ;- (MC) Sector 11 Lock Status\r
+AT91C_MC_LOCKS12 EQU (0x1 << 28) ;- (MC) Sector 12 Lock Status\r
+AT91C_MC_LOCKS13 EQU (0x1 << 29) ;- (MC) Sector 13 Lock Status\r
+AT91C_MC_LOCKS14 EQU (0x1 << 30) ;- (MC) Sector 14 Lock Status\r
+AT91C_MC_LOCKS15 EQU (0x1 << 31) ;- (MC) Sector 15 Lock Status\r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Serial Parallel Interface\r
+// - *****************************************************************************\r
+// - -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- \r
+AT91C_SPI_SPIEN EQU (0x1 << 0) ;- (SPI) SPI Enable\r
+AT91C_SPI_SPIDIS EQU (0x1 << 1) ;- (SPI) SPI Disable\r
+AT91C_SPI_SWRST EQU (0x1 << 7) ;- (SPI) SPI Software reset\r
+AT91C_SPI_LASTXFER EQU (0x1 << 24) ;- (SPI) SPI Last Transfer\r
+// - -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- \r
+AT91C_SPI_MSTR EQU (0x1 << 0) ;- (SPI) Master/Slave Mode\r
+AT91C_SPI_PS EQU (0x1 << 1) ;- (SPI) Peripheral Select\r
+AT91C_SPI_PS_FIXED EQU (0x0 << 1) ;- (SPI) Fixed Peripheral Select\r
+AT91C_SPI_PS_VARIABLE EQU (0x1 << 1) ;- (SPI) Variable Peripheral Select\r
+AT91C_SPI_PCSDEC EQU (0x1 << 2) ;- (SPI) Chip Select Decode\r
+AT91C_SPI_FDIV EQU (0x1 << 3) ;- (SPI) Clock Selection\r
+AT91C_SPI_MODFDIS EQU (0x1 << 4) ;- (SPI) Mode Fault Detection\r
+AT91C_SPI_LLB EQU (0x1 << 7) ;- (SPI) Clock Selection\r
+AT91C_SPI_PCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select\r
+AT91C_SPI_DLYBCS EQU (0xFF << 24) ;- (SPI) Delay Between Chip Selects\r
+// - -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- \r
+AT91C_SPI_RD EQU (0xFFFF << 0) ;- (SPI) Receive Data\r
+AT91C_SPI_RPCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status\r
+// - -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- \r
+AT91C_SPI_TD EQU (0xFFFF << 0) ;- (SPI) Transmit Data\r
+AT91C_SPI_TPCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status\r
+// - -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- \r
+AT91C_SPI_RDRF EQU (0x1 << 0) ;- (SPI) Receive Data Register Full\r
+AT91C_SPI_TDRE EQU (0x1 << 1) ;- (SPI) Transmit Data Register Empty\r
+AT91C_SPI_MODF EQU (0x1 << 2) ;- (SPI) Mode Fault Error\r
+AT91C_SPI_OVRES EQU (0x1 << 3) ;- (SPI) Overrun Error Status\r
+AT91C_SPI_ENDRX EQU (0x1 << 4) ;- (SPI) End of Receiver Transfer\r
+AT91C_SPI_ENDTX EQU (0x1 << 5) ;- (SPI) End of Receiver Transfer\r
+AT91C_SPI_RXBUFF EQU (0x1 << 6) ;- (SPI) RXBUFF Interrupt\r
+AT91C_SPI_TXBUFE EQU (0x1 << 7) ;- (SPI) TXBUFE Interrupt\r
+AT91C_SPI_NSSR EQU (0x1 << 8) ;- (SPI) NSSR Interrupt\r
+AT91C_SPI_TXEMPTY EQU (0x1 << 9) ;- (SPI) TXEMPTY Interrupt\r
+AT91C_SPI_SPIENS EQU (0x1 << 16) ;- (SPI) Enable Status\r
+// - -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- \r
+// - -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- \r
+// - -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- \r
+// - -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- \r
+AT91C_SPI_CPOL EQU (0x1 << 0) ;- (SPI) Clock Polarity\r
+AT91C_SPI_NCPHA EQU (0x1 << 1) ;- (SPI) Clock Phase\r
+AT91C_SPI_CSAAT EQU (0x1 << 3) ;- (SPI) Chip Select Active After Transfer\r
+AT91C_SPI_BITS EQU (0xF << 4) ;- (SPI) Bits Per Transfer\r
+AT91C_SPI_BITS_8 EQU (0x0 << 4) ;- (SPI) 8 Bits Per transfer\r
+AT91C_SPI_BITS_9 EQU (0x1 << 4) ;- (SPI) 9 Bits Per transfer\r
+AT91C_SPI_BITS_10 EQU (0x2 << 4) ;- (SPI) 10 Bits Per transfer\r
+AT91C_SPI_BITS_11 EQU (0x3 << 4) ;- (SPI) 11 Bits Per transfer\r
+AT91C_SPI_BITS_12 EQU (0x4 << 4) ;- (SPI) 12 Bits Per transfer\r
+AT91C_SPI_BITS_13 EQU (0x5 << 4) ;- (SPI) 13 Bits Per transfer\r
+AT91C_SPI_BITS_14 EQU (0x6 << 4) ;- (SPI) 14 Bits Per transfer\r
+AT91C_SPI_BITS_15 EQU (0x7 << 4) ;- (SPI) 15 Bits Per transfer\r
+AT91C_SPI_BITS_16 EQU (0x8 << 4) ;- (SPI) 16 Bits Per transfer\r
+AT91C_SPI_SCBR EQU (0xFF << 8) ;- (SPI) Serial Clock Baud Rate\r
+AT91C_SPI_DLYBS EQU (0xFF << 16) ;- (SPI) Delay Before SPCK\r
+AT91C_SPI_DLYBCT EQU (0xFF << 24) ;- (SPI) Delay Between Consecutive Transfers\r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Usart\r
+// - *****************************************************************************\r
+// - -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- \r
+AT91C_US_STTBRK EQU (0x1 << 9) ;- (USART) Start Break\r
+AT91C_US_STPBRK EQU (0x1 << 10) ;- (USART) Stop Break\r
+AT91C_US_STTTO EQU (0x1 << 11) ;- (USART) Start Time-out\r
+AT91C_US_SENDA EQU (0x1 << 12) ;- (USART) Send Address\r
+AT91C_US_RSTIT EQU (0x1 << 13) ;- (USART) Reset Iterations\r
+AT91C_US_RSTNACK EQU (0x1 << 14) ;- (USART) Reset Non Acknowledge\r
+AT91C_US_RETTO EQU (0x1 << 15) ;- (USART) Rearm Time-out\r
+AT91C_US_DTREN EQU (0x1 << 16) ;- (USART) Data Terminal ready Enable\r
+AT91C_US_DTRDIS EQU (0x1 << 17) ;- (USART) Data Terminal ready Disable\r
+AT91C_US_RTSEN EQU (0x1 << 18) ;- (USART) Request to Send enable\r
+AT91C_US_RTSDIS EQU (0x1 << 19) ;- (USART) Request to Send Disable\r
+// - -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- \r
+AT91C_US_USMODE EQU (0xF << 0) ;- (USART) Usart mode\r
+AT91C_US_USMODE_NORMAL EQU (0x0) ;- (USART) Normal\r
+AT91C_US_USMODE_RS485 EQU (0x1) ;- (USART) RS485\r
+AT91C_US_USMODE_HWHSH EQU (0x2) ;- (USART) Hardware Handshaking\r
+AT91C_US_USMODE_MODEM EQU (0x3) ;- (USART) Modem\r
+AT91C_US_USMODE_ISO7816_0 EQU (0x4) ;- (USART) ISO7816 protocol: T = 0\r
+AT91C_US_USMODE_ISO7816_1 EQU (0x6) ;- (USART) ISO7816 protocol: T = 1\r
+AT91C_US_USMODE_IRDA EQU (0x8) ;- (USART) IrDA\r
+AT91C_US_USMODE_SWHSH EQU (0xC) ;- (USART) Software Handshaking\r
+AT91C_US_CLKS EQU (0x3 << 4) ;- (USART) Clock Selection (Baud Rate generator Input Clock\r
+AT91C_US_CLKS_CLOCK EQU (0x0 << 4) ;- (USART) Clock\r
+AT91C_US_CLKS_FDIV1 EQU (0x1 << 4) ;- (USART) fdiv1\r
+AT91C_US_CLKS_SLOW EQU (0x2 << 4) ;- (USART) slow_clock (ARM)\r
+AT91C_US_CLKS_EXT EQU (0x3 << 4) ;- (USART) External (SCK)\r
+AT91C_US_CHRL EQU (0x3 << 6) ;- (USART) Clock Selection (Baud Rate generator Input Clock\r
+AT91C_US_CHRL_5_BITS EQU (0x0 << 6) ;- (USART) Character Length: 5 bits\r
+AT91C_US_CHRL_6_BITS EQU (0x1 << 6) ;- (USART) Character Length: 6 bits\r
+AT91C_US_CHRL_7_BITS EQU (0x2 << 6) ;- (USART) Character Length: 7 bits\r
+AT91C_US_CHRL_8_BITS EQU (0x3 << 6) ;- (USART) Character Length: 8 bits\r
+AT91C_US_SYNC EQU (0x1 << 8) ;- (USART) Synchronous Mode Select\r
+AT91C_US_NBSTOP EQU (0x3 << 12) ;- (USART) Number of Stop bits\r
+AT91C_US_NBSTOP_1_BIT EQU (0x0 << 12) ;- (USART) 1 stop bit\r
+AT91C_US_NBSTOP_15_BIT EQU (0x1 << 12) ;- (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits\r
+AT91C_US_NBSTOP_2_BIT EQU (0x2 << 12) ;- (USART) 2 stop bits\r
+AT91C_US_MSBF EQU (0x1 << 16) ;- (USART) Bit Order\r
+AT91C_US_MODE9 EQU (0x1 << 17) ;- (USART) 9-bit Character length\r
+AT91C_US_CKLO EQU (0x1 << 18) ;- (USART) Clock Output Select\r
+AT91C_US_OVER EQU (0x1 << 19) ;- (USART) Over Sampling Mode\r
+AT91C_US_INACK EQU (0x1 << 20) ;- (USART) Inhibit Non Acknowledge\r
+AT91C_US_DSNACK EQU (0x1 << 21) ;- (USART) Disable Successive NACK\r
+AT91C_US_MAX_ITER EQU (0x1 << 24) ;- (USART) Number of Repetitions\r
+AT91C_US_FILTER EQU (0x1 << 28) ;- (USART) Receive Line Filter\r
+// - -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- \r
+AT91C_US_RXBRK EQU (0x1 << 2) ;- (USART) Break Received/End of Break\r
+AT91C_US_TIMEOUT EQU (0x1 << 8) ;- (USART) Receiver Time-out\r
+AT91C_US_ITERATION EQU (0x1 << 10) ;- (USART) Max number of Repetitions Reached\r
+AT91C_US_NACK EQU (0x1 << 13) ;- (USART) Non Acknowledge\r
+AT91C_US_RIIC EQU (0x1 << 16) ;- (USART) Ring INdicator Input Change Flag\r
+AT91C_US_DSRIC EQU (0x1 << 17) ;- (USART) Data Set Ready Input Change Flag\r
+AT91C_US_DCDIC EQU (0x1 << 18) ;- (USART) Data Carrier Flag\r
+AT91C_US_CTSIC EQU (0x1 << 19) ;- (USART) Clear To Send Input Change Flag\r
+// - -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- \r
+// - -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- \r
+// - -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- \r
+AT91C_US_RI EQU (0x1 << 20) ;- (USART) Image of RI Input\r
+AT91C_US_DSR EQU (0x1 << 21) ;- (USART) Image of DSR Input\r
+AT91C_US_DCD EQU (0x1 << 22) ;- (USART) Image of DCD Input\r
+AT91C_US_CTS EQU (0x1 << 23) ;- (USART) Image of CTS Input\r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface\r
+// - *****************************************************************************\r
+// - -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- \r
+AT91C_SSC_RXEN EQU (0x1 << 0) ;- (SSC) Receive Enable\r
+AT91C_SSC_RXDIS EQU (0x1 << 1) ;- (SSC) Receive Disable\r
+AT91C_SSC_TXEN EQU (0x1 << 8) ;- (SSC) Transmit Enable\r
+AT91C_SSC_TXDIS EQU (0x1 << 9) ;- (SSC) Transmit Disable\r
+AT91C_SSC_SWRST EQU (0x1 << 15) ;- (SSC) Software Reset\r
+// - -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- \r
+AT91C_SSC_CKS EQU (0x3 << 0) ;- (SSC) Receive/Transmit Clock Selection\r
+AT91C_SSC_CKS_DIV EQU (0x0) ;- (SSC) Divided Clock\r
+AT91C_SSC_CKS_TK EQU (0x1) ;- (SSC) TK Clock signal\r
+AT91C_SSC_CKS_RK EQU (0x2) ;- (SSC) RK pin\r
+AT91C_SSC_CKO EQU (0x7 << 2) ;- (SSC) Receive/Transmit Clock Output Mode Selection\r
+AT91C_SSC_CKO_NONE EQU (0x0 << 2) ;- (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only\r
+AT91C_SSC_CKO_CONTINOUS EQU (0x1 << 2) ;- (SSC) Continuous Receive/Transmit Clock RK pin: Output\r
+AT91C_SSC_CKO_DATA_TX EQU (0x2 << 2) ;- (SSC) Receive/Transmit Clock only during data transfers RK pin: Output\r
+AT91C_SSC_CKI EQU (0x1 << 5) ;- (SSC) Receive/Transmit Clock Inversion\r
+AT91C_SSC_START EQU (0xF << 8) ;- (SSC) Receive/Transmit Start Selection\r
+AT91C_SSC_START_CONTINOUS EQU (0x0 << 8) ;- (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.\r
+AT91C_SSC_START_TX EQU (0x1 << 8) ;- (SSC) Transmit/Receive start\r
+AT91C_SSC_START_LOW_RF EQU (0x2 << 8) ;- (SSC) Detection of a low level on RF input\r
+AT91C_SSC_START_HIGH_RF EQU (0x3 << 8) ;- (SSC) Detection of a high level on RF input\r
+AT91C_SSC_START_FALL_RF EQU (0x4 << 8) ;- (SSC) Detection of a falling edge on RF input\r
+AT91C_SSC_START_RISE_RF EQU (0x5 << 8) ;- (SSC) Detection of a rising edge on RF input\r
+AT91C_SSC_START_LEVEL_RF EQU (0x6 << 8) ;- (SSC) Detection of any level change on RF input\r
+AT91C_SSC_START_EDGE_RF EQU (0x7 << 8) ;- (SSC) Detection of any edge on RF input\r
+AT91C_SSC_START_0 EQU (0x8 << 8) ;- (SSC) Compare 0\r
+AT91C_SSC_STTDLY EQU (0xFF << 16) ;- (SSC) Receive/Transmit Start Delay\r
+AT91C_SSC_PERIOD EQU (0xFF << 24) ;- (SSC) Receive/Transmit Period Divider Selection\r
+// - -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- \r
+AT91C_SSC_DATLEN EQU (0x1F << 0) ;- (SSC) Data Length\r
+AT91C_SSC_LOOP EQU (0x1 << 5) ;- (SSC) Loop Mode\r
+AT91C_SSC_MSBF EQU (0x1 << 7) ;- (SSC) Most Significant Bit First\r
+AT91C_SSC_DATNB EQU (0xF << 8) ;- (SSC) Data Number per Frame\r
+AT91C_SSC_FSLEN EQU (0xF << 16) ;- (SSC) Receive/Transmit Frame Sync length\r
+AT91C_SSC_FSOS EQU (0x7 << 20) ;- (SSC) Receive/Transmit Frame Sync Output Selection\r
+AT91C_SSC_FSOS_NONE EQU (0x0 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only\r
+AT91C_SSC_FSOS_NEGATIVE EQU (0x1 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse\r
+AT91C_SSC_FSOS_POSITIVE EQU (0x2 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse\r
+AT91C_SSC_FSOS_LOW EQU (0x3 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer\r
+AT91C_SSC_FSOS_HIGH EQU (0x4 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer\r
+AT91C_SSC_FSOS_TOGGLE EQU (0x5 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer\r
+AT91C_SSC_FSEDGE EQU (0x1 << 24) ;- (SSC) Frame Sync Edge Detection\r
+// - -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- \r
+// - -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- \r
+AT91C_SSC_DATDEF EQU (0x1 << 5) ;- (SSC) Data Default Value\r
+AT91C_SSC_FSDEN EQU (0x1 << 23) ;- (SSC) Frame Sync Data Enable\r
+// - -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- \r
+AT91C_SSC_TXRDY EQU (0x1 << 0) ;- (SSC) Transmit Ready\r
+AT91C_SSC_TXEMPTY EQU (0x1 << 1) ;- (SSC) Transmit Empty\r
+AT91C_SSC_ENDTX EQU (0x1 << 2) ;- (SSC) End Of Transmission\r
+AT91C_SSC_TXBUFE EQU (0x1 << 3) ;- (SSC) Transmit Buffer Empty\r
+AT91C_SSC_RXRDY EQU (0x1 << 4) ;- (SSC) Receive Ready\r
+AT91C_SSC_OVRUN EQU (0x1 << 5) ;- (SSC) Receive Overrun\r
+AT91C_SSC_ENDRX EQU (0x1 << 6) ;- (SSC) End of Reception\r
+AT91C_SSC_RXBUFF EQU (0x1 << 7) ;- (SSC) Receive Buffer Full\r
+AT91C_SSC_TXSYN EQU (0x1 << 10) ;- (SSC) Transmit Sync\r
+AT91C_SSC_RXSYN EQU (0x1 << 11) ;- (SSC) Receive Sync\r
+AT91C_SSC_TXENA EQU (0x1 << 16) ;- (SSC) Transmit Enable\r
+AT91C_SSC_RXENA EQU (0x1 << 17) ;- (SSC) Receive Enable\r
+// - -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- \r
+// - -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- \r
+// - -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- \r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Two-wire Interface\r
+// - *****************************************************************************\r
+// - -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- \r
+AT91C_TWI_START EQU (0x1 << 0) ;- (TWI) Send a START Condition\r
+AT91C_TWI_STOP EQU (0x1 << 1) ;- (TWI) Send a STOP Condition\r
+AT91C_TWI_MSEN EQU (0x1 << 2) ;- (TWI) TWI Master Transfer Enabled\r
+AT91C_TWI_MSDIS EQU (0x1 << 3) ;- (TWI) TWI Master Transfer Disabled\r
+AT91C_TWI_SWRST EQU (0x1 << 7) ;- (TWI) Software Reset\r
+// - -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- \r
+AT91C_TWI_IADRSZ EQU (0x3 << 8) ;- (TWI) Internal Device Address Size\r
+AT91C_TWI_IADRSZ_NO EQU (0x0 << 8) ;- (TWI) No internal device address\r
+AT91C_TWI_IADRSZ_1_BYTE EQU (0x1 << 8) ;- (TWI) One-byte internal device address\r
+AT91C_TWI_IADRSZ_2_BYTE EQU (0x2 << 8) ;- (TWI) Two-byte internal device address\r
+AT91C_TWI_IADRSZ_3_BYTE EQU (0x3 << 8) ;- (TWI) Three-byte internal device address\r
+AT91C_TWI_MREAD EQU (0x1 << 12) ;- (TWI) Master Read Direction\r
+AT91C_TWI_DADR EQU (0x7F << 16) ;- (TWI) Device Address\r
+// - -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- \r
+AT91C_TWI_CLDIV EQU (0xFF << 0) ;- (TWI) Clock Low Divider\r
+AT91C_TWI_CHDIV EQU (0xFF << 8) ;- (TWI) Clock High Divider\r
+AT91C_TWI_CKDIV EQU (0x7 << 16) ;- (TWI) Clock Divider\r
+// - -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- \r
+AT91C_TWI_TXCOMP EQU (0x1 << 0) ;- (TWI) Transmission Completed\r
+AT91C_TWI_RXRDY EQU (0x1 << 1) ;- (TWI) Receive holding register ReaDY\r
+AT91C_TWI_TXRDY EQU (0x1 << 2) ;- (TWI) Transmit holding register ReaDY\r
+AT91C_TWI_OVRE EQU (0x1 << 6) ;- (TWI) Overrun Error\r
+AT91C_TWI_UNRE EQU (0x1 << 7) ;- (TWI) Underrun Error\r
+AT91C_TWI_NACK EQU (0x1 << 8) ;- (TWI) Not Acknowledged\r
+// - -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- \r
+// - -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- \r
+// - -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- \r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR PWMC Channel Interface\r
+// - *****************************************************************************\r
+// - -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- \r
+AT91C_PWMC_CPRE EQU (0xF << 0) ;- (PWMC_CH) Channel Pre-scaler : PWMC_CLKx\r
+AT91C_PWMC_CPRE_MCK EQU (0x0) ;- (PWMC_CH) \r
+AT91C_PWMC_CPRE_MCKA EQU (0xB) ;- (PWMC_CH) \r
+AT91C_PWMC_CPRE_MCKB EQU (0xC) ;- (PWMC_CH) \r
+AT91C_PWMC_CALG EQU (0x1 << 8) ;- (PWMC_CH) Channel Alignment\r
+AT91C_PWMC_CPOL EQU (0x1 << 9) ;- (PWMC_CH) Channel Polarity\r
+AT91C_PWMC_CPD EQU (0x1 << 10) ;- (PWMC_CH) Channel Update Period\r
+// - -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- \r
+AT91C_PWMC_CDTY EQU (0x0 << 0) ;- (PWMC_CH) Channel Duty Cycle\r
+// - -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- \r
+AT91C_PWMC_CPRD EQU (0x0 << 0) ;- (PWMC_CH) Channel Period\r
+// - -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- \r
+AT91C_PWMC_CCNT EQU (0x0 << 0) ;- (PWMC_CH) Channel Counter\r
+// - -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- \r
+AT91C_PWMC_CUPD EQU (0x0 << 0) ;- (PWMC_CH) Channel Update\r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface\r
+// - *****************************************************************************\r
+// - -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- \r
+AT91C_PWMC_DIVA EQU (0xFF << 0) ;- (PWMC) CLKA divide factor.\r
+AT91C_PWMC_PREA EQU (0xF << 8) ;- (PWMC) Divider Input Clock Prescaler A\r
+AT91C_PWMC_PREA_MCK EQU (0x0 << 8) ;- (PWMC) \r
+AT91C_PWMC_DIVB EQU (0xFF << 16) ;- (PWMC) CLKB divide factor.\r
+AT91C_PWMC_PREB EQU (0xF << 24) ;- (PWMC) Divider Input Clock Prescaler B\r
+AT91C_PWMC_PREB_MCK EQU (0x0 << 24) ;- (PWMC) \r
+// - -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- \r
+AT91C_PWMC_CHID0 EQU (0x1 << 0) ;- (PWMC) Channel ID 0\r
+AT91C_PWMC_CHID1 EQU (0x1 << 1) ;- (PWMC) Channel ID 1\r
+AT91C_PWMC_CHID2 EQU (0x1 << 2) ;- (PWMC) Channel ID 2\r
+AT91C_PWMC_CHID3 EQU (0x1 << 3) ;- (PWMC) Channel ID 3\r
+// - -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- \r
+// - -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- \r
+// - -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- \r
+// - -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- \r
+// - -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- \r
+// - -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- \r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR USB Device Interface\r
+// - *****************************************************************************\r
+// - -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- \r
+AT91C_UDP_FRM_NUM EQU (0x7FF << 0) ;- (UDP) Frame Number as Defined in the Packet Field Formats\r
+AT91C_UDP_FRM_ERR EQU (0x1 << 16) ;- (UDP) Frame Error\r
+AT91C_UDP_FRM_OK EQU (0x1 << 17) ;- (UDP) Frame OK\r
+// - -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- \r
+AT91C_UDP_FADDEN EQU (0x1 << 0) ;- (UDP) Function Address Enable\r
+AT91C_UDP_CONFG EQU (0x1 << 1) ;- (UDP) Configured\r
+AT91C_UDP_ESR EQU (0x1 << 2) ;- (UDP) Enable Send Resume\r
+AT91C_UDP_RSMINPR EQU (0x1 << 3) ;- (UDP) A Resume Has Been Sent to the Host\r
+AT91C_UDP_RMWUPE EQU (0x1 << 4) ;- (UDP) Remote Wake Up Enable\r
+// - -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- \r
+AT91C_UDP_FADD EQU (0xFF << 0) ;- (UDP) Function Address Value\r
+AT91C_UDP_FEN EQU (0x1 << 8) ;- (UDP) Function Enable\r
+// - -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- \r
+AT91C_UDP_EPINT0 EQU (0x1 << 0) ;- (UDP) Endpoint 0 Interrupt\r
+AT91C_UDP_EPINT1 EQU (0x1 << 1) ;- (UDP) Endpoint 0 Interrupt\r
+AT91C_UDP_EPINT2 EQU (0x1 << 2) ;- (UDP) Endpoint 2 Interrupt\r
+AT91C_UDP_EPINT3 EQU (0x1 << 3) ;- (UDP) Endpoint 3 Interrupt\r
+AT91C_UDP_EPINT4 EQU (0x1 << 4) ;- (UDP) Endpoint 4 Interrupt\r
+AT91C_UDP_EPINT5 EQU (0x1 << 5) ;- (UDP) Endpoint 5 Interrupt\r
+AT91C_UDP_RXSUSP EQU (0x1 << 8) ;- (UDP) USB Suspend Interrupt\r
+AT91C_UDP_RXRSM EQU (0x1 << 9) ;- (UDP) USB Resume Interrupt\r
+AT91C_UDP_EXTRSM EQU (0x1 << 10) ;- (UDP) USB External Resume Interrupt\r
+AT91C_UDP_SOFINT EQU (0x1 << 11) ;- (UDP) USB Start Of frame Interrupt\r
+AT91C_UDP_WAKEUP EQU (0x1 << 13) ;- (UDP) USB Resume Interrupt\r
+// - -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- \r
+// - -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- \r
+// - -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- \r
+AT91C_UDP_ENDBUSRES EQU (0x1 << 12) ;- (UDP) USB End Of Bus Reset Interrupt\r
+// - -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- \r
+// - -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- \r
+AT91C_UDP_EP0 EQU (0x1 << 0) ;- (UDP) Reset Endpoint 0\r
+AT91C_UDP_EP1 EQU (0x1 << 1) ;- (UDP) Reset Endpoint 1\r
+AT91C_UDP_EP2 EQU (0x1 << 2) ;- (UDP) Reset Endpoint 2\r
+AT91C_UDP_EP3 EQU (0x1 << 3) ;- (UDP) Reset Endpoint 3\r
+AT91C_UDP_EP4 EQU (0x1 << 4) ;- (UDP) Reset Endpoint 4\r
+AT91C_UDP_EP5 EQU (0x1 << 5) ;- (UDP) Reset Endpoint 5\r
+// - -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- \r
+AT91C_UDP_TXCOMP EQU (0x1 << 0) ;- (UDP) Generates an IN packet with data previously written in the DPR\r
+AT91C_UDP_RX_DATA_BK0 EQU (0x1 << 1) ;- (UDP) Receive Data Bank 0\r
+AT91C_UDP_RXSETUP EQU (0x1 << 2) ;- (UDP) Sends STALL to the Host (Control endpoints)\r
+AT91C_UDP_ISOERROR EQU (0x1 << 3) ;- (UDP) Isochronous error (Isochronous endpoints)\r
+AT91C_UDP_TXPKTRDY EQU (0x1 << 4) ;- (UDP) Transmit Packet Ready\r
+AT91C_UDP_FORCESTALL EQU (0x1 << 5) ;- (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).\r
+AT91C_UDP_RX_DATA_BK1 EQU (0x1 << 6) ;- (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).\r
+AT91C_UDP_DIR EQU (0x1 << 7) ;- (UDP) Transfer Direction\r
+AT91C_UDP_EPTYPE EQU (0x7 << 8) ;- (UDP) Endpoint type\r
+AT91C_UDP_EPTYPE_CTRL EQU (0x0 << 8) ;- (UDP) Control\r
+AT91C_UDP_EPTYPE_ISO_OUT EQU (0x1 << 8) ;- (UDP) Isochronous OUT\r
+AT91C_UDP_EPTYPE_BULK_OUT EQU (0x2 << 8) ;- (UDP) Bulk OUT\r
+AT91C_UDP_EPTYPE_INT_OUT EQU (0x3 << 8) ;- (UDP) Interrupt OUT\r
+AT91C_UDP_EPTYPE_ISO_IN EQU (0x5 << 8) ;- (UDP) Isochronous IN\r
+AT91C_UDP_EPTYPE_BULK_IN EQU (0x6 << 8) ;- (UDP) Bulk IN\r
+AT91C_UDP_EPTYPE_INT_IN EQU (0x7 << 8) ;- (UDP) Interrupt IN\r
+AT91C_UDP_DTGLE EQU (0x1 << 11) ;- (UDP) Data Toggle\r
+AT91C_UDP_EPEDS EQU (0x1 << 15) ;- (UDP) Endpoint Enable Disable\r
+AT91C_UDP_RXBYTECNT EQU (0x7FF << 16) ;- (UDP) Number Of Bytes Available in the FIFO\r
+// - -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- \r
+AT91C_UDP_TXVDIS EQU (0x1 << 8) ;- (UDP) \r
+AT91C_UDP_PUON EQU (0x1 << 9) ;- (UDP) Pull-up ON\r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Timer Counter Channel Interface\r
+// - *****************************************************************************\r
+// - -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- \r
+AT91C_TC_CLKEN EQU (0x1 << 0) ;- (TC) Counter Clock Enable Command\r
+AT91C_TC_CLKDIS EQU (0x1 << 1) ;- (TC) Counter Clock Disable Command\r
+AT91C_TC_SWTRG EQU (0x1 << 2) ;- (TC) Software Trigger Command\r
+// - -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- \r
+AT91C_TC_CLKS EQU (0x7 << 0) ;- (TC) Clock Selection\r
+AT91C_TC_CLKS_TIMER_DIV1_CLOCK EQU (0x0) ;- (TC) Clock selected: TIMER_DIV1_CLOCK\r
+AT91C_TC_CLKS_TIMER_DIV2_CLOCK EQU (0x1) ;- (TC) Clock selected: TIMER_DIV2_CLOCK\r
+AT91C_TC_CLKS_TIMER_DIV3_CLOCK EQU (0x2) ;- (TC) Clock selected: TIMER_DIV3_CLOCK\r
+AT91C_TC_CLKS_TIMER_DIV4_CLOCK EQU (0x3) ;- (TC) Clock selected: TIMER_DIV4_CLOCK\r
+AT91C_TC_CLKS_TIMER_DIV5_CLOCK EQU (0x4) ;- (TC) Clock selected: TIMER_DIV5_CLOCK\r
+AT91C_TC_CLKS_XC0 EQU (0x5) ;- (TC) Clock selected: XC0\r
+AT91C_TC_CLKS_XC1 EQU (0x6) ;- (TC) Clock selected: XC1\r
+AT91C_TC_CLKS_XC2 EQU (0x7) ;- (TC) Clock selected: XC2\r
+AT91C_TC_CLKI EQU (0x1 << 3) ;- (TC) Clock Invert\r
+AT91C_TC_BURST EQU (0x3 << 4) ;- (TC) Burst Signal Selection\r
+AT91C_TC_BURST_NONE EQU (0x0 << 4) ;- (TC) The clock is not gated by an external signal\r
+AT91C_TC_BURST_XC0 EQU (0x1 << 4) ;- (TC) XC0 is ANDed with the selected clock\r
+AT91C_TC_BURST_XC1 EQU (0x2 << 4) ;- (TC) XC1 is ANDed with the selected clock\r
+AT91C_TC_BURST_XC2 EQU (0x3 << 4) ;- (TC) XC2 is ANDed with the selected clock\r
+AT91C_TC_CPCSTOP EQU (0x1 << 6) ;- (TC) Counter Clock Stopped with RC Compare\r
+AT91C_TC_LDBSTOP EQU (0x1 << 6) ;- (TC) Counter Clock Stopped with RB Loading\r
+AT91C_TC_CPCDIS EQU (0x1 << 7) ;- (TC) Counter Clock Disable with RC Compare\r
+AT91C_TC_LDBDIS EQU (0x1 << 7) ;- (TC) Counter Clock Disabled with RB Loading\r
+AT91C_TC_ETRGEDG EQU (0x3 << 8) ;- (TC) External Trigger Edge Selection\r
+AT91C_TC_ETRGEDG_NONE EQU (0x0 << 8) ;- (TC) Edge: None\r
+AT91C_TC_ETRGEDG_RISING EQU (0x1 << 8) ;- (TC) Edge: rising edge\r
+AT91C_TC_ETRGEDG_FALLING EQU (0x2 << 8) ;- (TC) Edge: falling edge\r
+AT91C_TC_ETRGEDG_BOTH EQU (0x3 << 8) ;- (TC) Edge: each edge\r
+AT91C_TC_EEVTEDG EQU (0x3 << 8) ;- (TC) External Event Edge Selection\r
+AT91C_TC_EEVTEDG_NONE EQU (0x0 << 8) ;- (TC) Edge: None\r
+AT91C_TC_EEVTEDG_RISING EQU (0x1 << 8) ;- (TC) Edge: rising edge\r
+AT91C_TC_EEVTEDG_FALLING EQU (0x2 << 8) ;- (TC) Edge: falling edge\r
+AT91C_TC_EEVTEDG_BOTH EQU (0x3 << 8) ;- (TC) Edge: each edge\r
+AT91C_TC_EEVT EQU (0x3 << 10) ;- (TC) External Event Selection\r
+AT91C_TC_EEVT_TIOB EQU (0x0 << 10) ;- (TC) Signal selected as external event: TIOB TIOB direction: input\r
+AT91C_TC_EEVT_XC0 EQU (0x1 << 10) ;- (TC) Signal selected as external event: XC0 TIOB direction: output\r
+AT91C_TC_EEVT_XC1 EQU (0x2 << 10) ;- (TC) Signal selected as external event: XC1 TIOB direction: output\r
+AT91C_TC_EEVT_XC2 EQU (0x3 << 10) ;- (TC) Signal selected as external event: XC2 TIOB direction: output\r
+AT91C_TC_ABETRG EQU (0x1 << 10) ;- (TC) TIOA or TIOB External Trigger Selection\r
+AT91C_TC_ENETRG EQU (0x1 << 12) ;- (TC) External Event Trigger enable\r
+AT91C_TC_WAVESEL EQU (0x3 << 13) ;- (TC) Waveform Selection\r
+AT91C_TC_WAVESEL_UP EQU (0x0 << 13) ;- (TC) UP mode without atomatic trigger on RC Compare\r
+AT91C_TC_WAVESEL_UPDOWN EQU (0x1 << 13) ;- (TC) UPDOWN mode without automatic trigger on RC Compare\r
+AT91C_TC_WAVESEL_UP_AUTO EQU (0x2 << 13) ;- (TC) UP mode with automatic trigger on RC Compare\r
+AT91C_TC_WAVESEL_UPDOWN_AUTO EQU (0x3 << 13) ;- (TC) UPDOWN mode with automatic trigger on RC Compare\r
+AT91C_TC_CPCTRG EQU (0x1 << 14) ;- (TC) RC Compare Trigger Enable\r
+AT91C_TC_WAVE EQU (0x1 << 15) ;- (TC) \r
+AT91C_TC_ACPA EQU (0x3 << 16) ;- (TC) RA Compare Effect on TIOA\r
+AT91C_TC_ACPA_NONE EQU (0x0 << 16) ;- (TC) Effect: none\r
+AT91C_TC_ACPA_SET EQU (0x1 << 16) ;- (TC) Effect: set\r
+AT91C_TC_ACPA_CLEAR EQU (0x2 << 16) ;- (TC) Effect: clear\r
+AT91C_TC_ACPA_TOGGLE EQU (0x3 << 16) ;- (TC) Effect: toggle\r
+AT91C_TC_LDRA EQU (0x3 << 16) ;- (TC) RA Loading Selection\r
+AT91C_TC_LDRA_NONE EQU (0x0 << 16) ;- (TC) Edge: None\r
+AT91C_TC_LDRA_RISING EQU (0x1 << 16) ;- (TC) Edge: rising edge of TIOA\r
+AT91C_TC_LDRA_FALLING EQU (0x2 << 16) ;- (TC) Edge: falling edge of TIOA\r
+AT91C_TC_LDRA_BOTH EQU (0x3 << 16) ;- (TC) Edge: each edge of TIOA\r
+AT91C_TC_ACPC EQU (0x3 << 18) ;- (TC) RC Compare Effect on TIOA\r
+AT91C_TC_ACPC_NONE EQU (0x0 << 18) ;- (TC) Effect: none\r
+AT91C_TC_ACPC_SET EQU (0x1 << 18) ;- (TC) Effect: set\r
+AT91C_TC_ACPC_CLEAR EQU (0x2 << 18) ;- (TC) Effect: clear\r
+AT91C_TC_ACPC_TOGGLE EQU (0x3 << 18) ;- (TC) Effect: toggle\r
+AT91C_TC_LDRB EQU (0x3 << 18) ;- (TC) RB Loading Selection\r
+AT91C_TC_LDRB_NONE EQU (0x0 << 18) ;- (TC) Edge: None\r
+AT91C_TC_LDRB_RISING EQU (0x1 << 18) ;- (TC) Edge: rising edge of TIOA\r
+AT91C_TC_LDRB_FALLING EQU (0x2 << 18) ;- (TC) Edge: falling edge of TIOA\r
+AT91C_TC_LDRB_BOTH EQU (0x3 << 18) ;- (TC) Edge: each edge of TIOA\r
+AT91C_TC_AEEVT EQU (0x3 << 20) ;- (TC) External Event Effect on TIOA\r
+AT91C_TC_AEEVT_NONE EQU (0x0 << 20) ;- (TC) Effect: none\r
+AT91C_TC_AEEVT_SET EQU (0x1 << 20) ;- (TC) Effect: set\r
+AT91C_TC_AEEVT_CLEAR EQU (0x2 << 20) ;- (TC) Effect: clear\r
+AT91C_TC_AEEVT_TOGGLE EQU (0x3 << 20) ;- (TC) Effect: toggle\r
+AT91C_TC_ASWTRG EQU (0x3 << 22) ;- (TC) Software Trigger Effect on TIOA\r
+AT91C_TC_ASWTRG_NONE EQU (0x0 << 22) ;- (TC) Effect: none\r
+AT91C_TC_ASWTRG_SET EQU (0x1 << 22) ;- (TC) Effect: set\r
+AT91C_TC_ASWTRG_CLEAR EQU (0x2 << 22) ;- (TC) Effect: clear\r
+AT91C_TC_ASWTRG_TOGGLE EQU (0x3 << 22) ;- (TC) Effect: toggle\r
+AT91C_TC_BCPB EQU (0x3 << 24) ;- (TC) RB Compare Effect on TIOB\r
+AT91C_TC_BCPB_NONE EQU (0x0 << 24) ;- (TC) Effect: none\r
+AT91C_TC_BCPB_SET EQU (0x1 << 24) ;- (TC) Effect: set\r
+AT91C_TC_BCPB_CLEAR EQU (0x2 << 24) ;- (TC) Effect: clear\r
+AT91C_TC_BCPB_TOGGLE EQU (0x3 << 24) ;- (TC) Effect: toggle\r
+AT91C_TC_BCPC EQU (0x3 << 26) ;- (TC) RC Compare Effect on TIOB\r
+AT91C_TC_BCPC_NONE EQU (0x0 << 26) ;- (TC) Effect: none\r
+AT91C_TC_BCPC_SET EQU (0x1 << 26) ;- (TC) Effect: set\r
+AT91C_TC_BCPC_CLEAR EQU (0x2 << 26) ;- (TC) Effect: clear\r
+AT91C_TC_BCPC_TOGGLE EQU (0x3 << 26) ;- (TC) Effect: toggle\r
+AT91C_TC_BEEVT EQU (0x3 << 28) ;- (TC) External Event Effect on TIOB\r
+AT91C_TC_BEEVT_NONE EQU (0x0 << 28) ;- (TC) Effect: none\r
+AT91C_TC_BEEVT_SET EQU (0x1 << 28) ;- (TC) Effect: set\r
+AT91C_TC_BEEVT_CLEAR EQU (0x2 << 28) ;- (TC) Effect: clear\r
+AT91C_TC_BEEVT_TOGGLE EQU (0x3 << 28) ;- (TC) Effect: toggle\r
+AT91C_TC_BSWTRG EQU (0x3 << 30) ;- (TC) Software Trigger Effect on TIOB\r
+AT91C_TC_BSWTRG_NONE EQU (0x0 << 30) ;- (TC) Effect: none\r
+AT91C_TC_BSWTRG_SET EQU (0x1 << 30) ;- (TC) Effect: set\r
+AT91C_TC_BSWTRG_CLEAR EQU (0x2 << 30) ;- (TC) Effect: clear\r
+AT91C_TC_BSWTRG_TOGGLE EQU (0x3 << 30) ;- (TC) Effect: toggle\r
+// - -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- \r
+AT91C_TC_COVFS EQU (0x1 << 0) ;- (TC) Counter Overflow\r
+AT91C_TC_LOVRS EQU (0x1 << 1) ;- (TC) Load Overrun\r
+AT91C_TC_CPAS EQU (0x1 << 2) ;- (TC) RA Compare\r
+AT91C_TC_CPBS EQU (0x1 << 3) ;- (TC) RB Compare\r
+AT91C_TC_CPCS EQU (0x1 << 4) ;- (TC) RC Compare\r
+AT91C_TC_LDRAS EQU (0x1 << 5) ;- (TC) RA Loading\r
+AT91C_TC_LDRBS EQU (0x1 << 6) ;- (TC) RB Loading\r
+AT91C_TC_ETRGS EQU (0x1 << 7) ;- (TC) External Trigger\r
+AT91C_TC_CLKSTA EQU (0x1 << 16) ;- (TC) Clock Enabling\r
+AT91C_TC_MTIOA EQU (0x1 << 17) ;- (TC) TIOA Mirror\r
+AT91C_TC_MTIOB EQU (0x1 << 18) ;- (TC) TIOA Mirror\r
+// - -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- \r
+// - -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- \r
+// - -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- \r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Timer Counter Interface\r
+// - *****************************************************************************\r
+// - -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- \r
+AT91C_TCB_SYNC EQU (0x1 << 0) ;- (TCB) Synchro Command\r
+// - -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- \r
+AT91C_TCB_TC0XC0S EQU (0x3 << 0) ;- (TCB) External Clock Signal 0 Selection\r
+AT91C_TCB_TC0XC0S_TCLK0 EQU (0x0) ;- (TCB) TCLK0 connected to XC0\r
+AT91C_TCB_TC0XC0S_NONE EQU (0x1) ;- (TCB) None signal connected to XC0\r
+AT91C_TCB_TC0XC0S_TIOA1 EQU (0x2) ;- (TCB) TIOA1 connected to XC0\r
+AT91C_TCB_TC0XC0S_TIOA2 EQU (0x3) ;- (TCB) TIOA2 connected to XC0\r
+AT91C_TCB_TC1XC1S EQU (0x3 << 2) ;- (TCB) External Clock Signal 1 Selection\r
+AT91C_TCB_TC1XC1S_TCLK1 EQU (0x0 << 2) ;- (TCB) TCLK1 connected to XC1\r
+AT91C_TCB_TC1XC1S_NONE EQU (0x1 << 2) ;- (TCB) None signal connected to XC1\r
+AT91C_TCB_TC1XC1S_TIOA0 EQU (0x2 << 2) ;- (TCB) TIOA0 connected to XC1\r
+AT91C_TCB_TC1XC1S_TIOA2 EQU (0x3 << 2) ;- (TCB) TIOA2 connected to XC1\r
+AT91C_TCB_TC2XC2S EQU (0x3 << 4) ;- (TCB) External Clock Signal 2 Selection\r
+AT91C_TCB_TC2XC2S_TCLK2 EQU (0x0 << 4) ;- (TCB) TCLK2 connected to XC2\r
+AT91C_TCB_TC2XC2S_NONE EQU (0x1 << 4) ;- (TCB) None signal connected to XC2\r
+AT91C_TCB_TC2XC2S_TIOA0 EQU (0x2 << 4) ;- (TCB) TIOA0 connected to XC2\r
+AT91C_TCB_TC2XC2S_TIOA1 EQU (0x3 << 4) ;- (TCB) TIOA2 connected to XC2\r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface\r
+// - *****************************************************************************\r
+// - -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- \r
+AT91C_CAN_MTIMEMARK EQU (0xFFFF << 0) ;- (CAN_MB) Mailbox Timemark\r
+AT91C_CAN_PRIOR EQU (0xF << 16) ;- (CAN_MB) Mailbox Priority\r
+AT91C_CAN_MOT EQU (0x7 << 24) ;- (CAN_MB) Mailbox Object Type\r
+AT91C_CAN_MOT_DIS EQU (0x0 << 24) ;- (CAN_MB) \r
+AT91C_CAN_MOT_RX EQU (0x1 << 24) ;- (CAN_MB) \r
+AT91C_CAN_MOT_RXOVERWRITE EQU (0x2 << 24) ;- (CAN_MB) \r
+AT91C_CAN_MOT_TX EQU (0x3 << 24) ;- (CAN_MB) \r
+AT91C_CAN_MOT_CONSUMER EQU (0x4 << 24) ;- (CAN_MB) \r
+AT91C_CAN_MOT_PRODUCER EQU (0x5 << 24) ;- (CAN_MB) \r
+// - -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- \r
+AT91C_CAN_MIDvB EQU (0x3FFFF << 0) ;- (CAN_MB) Complementary bits for identifier in extended mode\r
+AT91C_CAN_MIDvA EQU (0x7FF << 18) ;- (CAN_MB) Identifier for standard frame mode\r
+AT91C_CAN_MIDE EQU (0x1 << 29) ;- (CAN_MB) Identifier Version\r
+// - -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- \r
+// - -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- \r
+// - -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- \r
+AT91C_CAN_MTIMESTAMP EQU (0xFFFF << 0) ;- (CAN_MB) Timer Value\r
+AT91C_CAN_MDLC EQU (0xF << 16) ;- (CAN_MB) Mailbox Data Length Code\r
+AT91C_CAN_MRTR EQU (0x1 << 20) ;- (CAN_MB) Mailbox Remote Transmission Request\r
+AT91C_CAN_MABT EQU (0x1 << 22) ;- (CAN_MB) Mailbox Message Abort\r
+AT91C_CAN_MRDY EQU (0x1 << 23) ;- (CAN_MB) Mailbox Ready\r
+AT91C_CAN_MMI EQU (0x1 << 24) ;- (CAN_MB) Mailbox Message Ignored\r
+// - -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- \r
+// - -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- \r
+// - -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- \r
+AT91C_CAN_MACR EQU (0x1 << 22) ;- (CAN_MB) Abort Request for Mailbox\r
+AT91C_CAN_MTCR EQU (0x1 << 23) ;- (CAN_MB) Mailbox Transfer Command\r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Control Area Network Interface\r
+// - *****************************************************************************\r
+// - -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- \r
+AT91C_CAN_CANEN EQU (0x1 << 0) ;- (CAN) CAN Controller Enable\r
+AT91C_CAN_LPM EQU (0x1 << 1) ;- (CAN) Disable/Enable Low Power Mode\r
+AT91C_CAN_ABM EQU (0x1 << 2) ;- (CAN) Disable/Enable Autobaud/Listen Mode\r
+AT91C_CAN_OVL EQU (0x1 << 3) ;- (CAN) Disable/Enable Overload Frame\r
+AT91C_CAN_TEOF EQU (0x1 << 4) ;- (CAN) Time Stamp messages at each end of Frame\r
+AT91C_CAN_TTM EQU (0x1 << 5) ;- (CAN) Disable/Enable Time Trigger Mode\r
+AT91C_CAN_TIMFRZ EQU (0x1 << 6) ;- (CAN) Enable Timer Freeze\r
+AT91C_CAN_DRPT EQU (0x1 << 7) ;- (CAN) Disable Repeat\r
+// - -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- \r
+AT91C_CAN_MB0 EQU (0x1 << 0) ;- (CAN) Mailbox 0 Flag\r
+AT91C_CAN_MB1 EQU (0x1 << 1) ;- (CAN) Mailbox 1 Flag\r
+AT91C_CAN_MB2 EQU (0x1 << 2) ;- (CAN) Mailbox 2 Flag\r
+AT91C_CAN_MB3 EQU (0x1 << 3) ;- (CAN) Mailbox 3 Flag\r
+AT91C_CAN_MB4 EQU (0x1 << 4) ;- (CAN) Mailbox 4 Flag\r
+AT91C_CAN_MB5 EQU (0x1 << 5) ;- (CAN) Mailbox 5 Flag\r
+AT91C_CAN_MB6 EQU (0x1 << 6) ;- (CAN) Mailbox 6 Flag\r
+AT91C_CAN_MB7 EQU (0x1 << 7) ;- (CAN) Mailbox 7 Flag\r
+AT91C_CAN_MB8 EQU (0x1 << 8) ;- (CAN) Mailbox 8 Flag\r
+AT91C_CAN_MB9 EQU (0x1 << 9) ;- (CAN) Mailbox 9 Flag\r
+AT91C_CAN_MB10 EQU (0x1 << 10) ;- (CAN) Mailbox 10 Flag\r
+AT91C_CAN_MB11 EQU (0x1 << 11) ;- (CAN) Mailbox 11 Flag\r
+AT91C_CAN_MB12 EQU (0x1 << 12) ;- (CAN) Mailbox 12 Flag\r
+AT91C_CAN_MB13 EQU (0x1 << 13) ;- (CAN) Mailbox 13 Flag\r
+AT91C_CAN_MB14 EQU (0x1 << 14) ;- (CAN) Mailbox 14 Flag\r
+AT91C_CAN_MB15 EQU (0x1 << 15) ;- (CAN) Mailbox 15 Flag\r
+AT91C_CAN_ERRA EQU (0x1 << 16) ;- (CAN) Error Active Mode Flag\r
+AT91C_CAN_WARN EQU (0x1 << 17) ;- (CAN) Warning Limit Flag\r
+AT91C_CAN_ERRP EQU (0x1 << 18) ;- (CAN) Error Passive Mode Flag\r
+AT91C_CAN_BOFF EQU (0x1 << 19) ;- (CAN) Bus Off Mode Flag\r
+AT91C_CAN_SLEEP EQU (0x1 << 20) ;- (CAN) Sleep Flag\r
+AT91C_CAN_WAKEUP EQU (0x1 << 21) ;- (CAN) Wakeup Flag\r
+AT91C_CAN_TOVF EQU (0x1 << 22) ;- (CAN) Timer Overflow Flag\r
+AT91C_CAN_TSTP EQU (0x1 << 23) ;- (CAN) Timestamp Flag\r
+AT91C_CAN_CERR EQU (0x1 << 24) ;- (CAN) CRC Error\r
+AT91C_CAN_SERR EQU (0x1 << 25) ;- (CAN) Stuffing Error\r
+AT91C_CAN_AERR EQU (0x1 << 26) ;- (CAN) Acknowledgment Error\r
+AT91C_CAN_FERR EQU (0x1 << 27) ;- (CAN) Form Error\r
+AT91C_CAN_BERR EQU (0x1 << 28) ;- (CAN) Bit Error\r
+// - -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- \r
+// - -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- \r
+// - -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- \r
+AT91C_CAN_RBSY EQU (0x1 << 29) ;- (CAN) Receiver Busy\r
+AT91C_CAN_TBSY EQU (0x1 << 30) ;- (CAN) Transmitter Busy\r
+AT91C_CAN_OVLY EQU (0x1 << 31) ;- (CAN) Overload Busy\r
+// - -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- \r
+AT91C_CAN_PHASE2 EQU (0x7 << 0) ;- (CAN) Phase 2 segment\r
+AT91C_CAN_PHASE1 EQU (0x7 << 4) ;- (CAN) Phase 1 segment\r
+AT91C_CAN_PROPAG EQU (0x7 << 8) ;- (CAN) Programmation time segment\r
+AT91C_CAN_SYNC EQU (0x3 << 12) ;- (CAN) Re-synchronization jump width segment\r
+AT91C_CAN_BRP EQU (0x7F << 16) ;- (CAN) Baudrate Prescaler\r
+AT91C_CAN_SMP EQU (0x1 << 24) ;- (CAN) Sampling mode\r
+// - -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- \r
+AT91C_CAN_TIMER EQU (0xFFFF << 0) ;- (CAN) Timer field\r
+// - -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- \r
+// - -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- \r
+AT91C_CAN_REC EQU (0xFF << 0) ;- (CAN) Receive Error Counter\r
+AT91C_CAN_TEC EQU (0xFF << 16) ;- (CAN) Transmit Error Counter\r
+// - -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- \r
+AT91C_CAN_TIMRST EQU (0x1 << 31) ;- (CAN) Timer Reset Field\r
+// - -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- \r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Ethernet MAC 10/100\r
+// - *****************************************************************************\r
+// - -------- EMAC_NCR : (EMAC Offset: 0x0) -------- \r
+AT91C_EMAC_LB EQU (0x1 << 0) ;- (EMAC) Loopback. Optional. When set, loopback signal is at high level.\r
+AT91C_EMAC_LLB EQU (0x1 << 1) ;- (EMAC) Loopback local. \r
+AT91C_EMAC_RE EQU (0x1 << 2) ;- (EMAC) Receive enable. \r
+AT91C_EMAC_TE EQU (0x1 << 3) ;- (EMAC) Transmit enable. \r
+AT91C_EMAC_MPE EQU (0x1 << 4) ;- (EMAC) Management port enable. \r
+AT91C_EMAC_CLRSTAT EQU (0x1 << 5) ;- (EMAC) Clear statistics registers. \r
+AT91C_EMAC_INCSTAT EQU (0x1 << 6) ;- (EMAC) Increment statistics registers. \r
+AT91C_EMAC_WESTAT EQU (0x1 << 7) ;- (EMAC) Write enable for statistics registers. \r
+AT91C_EMAC_BP EQU (0x1 << 8) ;- (EMAC) Back pressure. \r
+AT91C_EMAC_TSTART EQU (0x1 << 9) ;- (EMAC) Start Transmission. \r
+AT91C_EMAC_THALT EQU (0x1 << 10) ;- (EMAC) Transmission Halt. \r
+AT91C_EMAC_TPFR EQU (0x1 << 11) ;- (EMAC) Transmit pause frame \r
+AT91C_EMAC_TZQ EQU (0x1 << 12) ;- (EMAC) Transmit zero quantum pause frame\r
+// - -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- \r
+AT91C_EMAC_SPD EQU (0x1 << 0) ;- (EMAC) Speed. \r
+AT91C_EMAC_FD EQU (0x1 << 1) ;- (EMAC) Full duplex. \r
+AT91C_EMAC_JFRAME EQU (0x1 << 3) ;- (EMAC) Jumbo Frames. \r
+AT91C_EMAC_CAF EQU (0x1 << 4) ;- (EMAC) Copy all frames. \r
+AT91C_EMAC_NBC EQU (0x1 << 5) ;- (EMAC) No broadcast. \r
+AT91C_EMAC_MTI EQU (0x1 << 6) ;- (EMAC) Multicast hash event enable\r
+AT91C_EMAC_UNI EQU (0x1 << 7) ;- (EMAC) Unicast hash enable. \r
+AT91C_EMAC_BIG EQU (0x1 << 8) ;- (EMAC) Receive 1522 bytes. \r
+AT91C_EMAC_EAE EQU (0x1 << 9) ;- (EMAC) External address match enable. \r
+AT91C_EMAC_CLK EQU (0x3 << 10) ;- (EMAC) \r
+AT91C_EMAC_CLK_HCLK_8 EQU (0x0 << 10) ;- (EMAC) HCLK divided by 8\r
+AT91C_EMAC_CLK_HCLK_16 EQU (0x1 << 10) ;- (EMAC) HCLK divided by 16\r
+AT91C_EMAC_CLK_HCLK_32 EQU (0x2 << 10) ;- (EMAC) HCLK divided by 32\r
+AT91C_EMAC_CLK_HCLK_64 EQU (0x3 << 10) ;- (EMAC) HCLK divided by 64\r
+AT91C_EMAC_RTY EQU (0x1 << 12) ;- (EMAC) \r
+AT91C_EMAC_PAE EQU (0x1 << 13) ;- (EMAC) \r
+AT91C_EMAC_RBOF EQU (0x3 << 14) ;- (EMAC) \r
+AT91C_EMAC_RBOF_OFFSET_0 EQU (0x0 << 14) ;- (EMAC) no offset from start of receive buffer\r
+AT91C_EMAC_RBOF_OFFSET_1 EQU (0x1 << 14) ;- (EMAC) one byte offset from start of receive buffer\r
+AT91C_EMAC_RBOF_OFFSET_2 EQU (0x2 << 14) ;- (EMAC) two bytes offset from start of receive buffer\r
+AT91C_EMAC_RBOF_OFFSET_3 EQU (0x3 << 14) ;- (EMAC) three bytes offset from start of receive buffer\r
+AT91C_EMAC_RLCE EQU (0x1 << 16) ;- (EMAC) Receive Length field Checking Enable\r
+AT91C_EMAC_DRFCS EQU (0x1 << 17) ;- (EMAC) Discard Receive FCS\r
+AT91C_EMAC_EFRHD EQU (0x1 << 18) ;- (EMAC) \r
+AT91C_EMAC_IRXFCS EQU (0x1 << 19) ;- (EMAC) Ignore RX FCS\r
+// - -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- \r
+AT91C_EMAC_LINKR EQU (0x1 << 0) ;- (EMAC) \r
+AT91C_EMAC_MDIO EQU (0x1 << 1) ;- (EMAC) \r
+AT91C_EMAC_IDLE EQU (0x1 << 2) ;- (EMAC) \r
+// - -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- \r
+AT91C_EMAC_UBR EQU (0x1 << 0) ;- (EMAC) \r
+AT91C_EMAC_COL EQU (0x1 << 1) ;- (EMAC) \r
+AT91C_EMAC_RLES EQU (0x1 << 2) ;- (EMAC) \r
+AT91C_EMAC_TGO EQU (0x1 << 3) ;- (EMAC) Transmit Go\r
+AT91C_EMAC_BEX EQU (0x1 << 4) ;- (EMAC) Buffers exhausted mid frame\r
+AT91C_EMAC_COMP EQU (0x1 << 5) ;- (EMAC) \r
+AT91C_EMAC_UND EQU (0x1 << 6) ;- (EMAC) \r
+// - -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- \r
+AT91C_EMAC_BNA EQU (0x1 << 0) ;- (EMAC) \r
+AT91C_EMAC_REC EQU (0x1 << 1) ;- (EMAC) \r
+AT91C_EMAC_OVR EQU (0x1 << 2) ;- (EMAC) \r
+// - -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- \r
+AT91C_EMAC_MFD EQU (0x1 << 0) ;- (EMAC) \r
+AT91C_EMAC_RCOMP EQU (0x1 << 1) ;- (EMAC) \r
+AT91C_EMAC_RXUBR EQU (0x1 << 2) ;- (EMAC) \r
+AT91C_EMAC_TXUBR EQU (0x1 << 3) ;- (EMAC) \r
+AT91C_EMAC_TUNDR EQU (0x1 << 4) ;- (EMAC) \r
+AT91C_EMAC_RLEX EQU (0x1 << 5) ;- (EMAC) \r
+AT91C_EMAC_TXERR EQU (0x1 << 6) ;- (EMAC) \r
+AT91C_EMAC_TCOMP EQU (0x1 << 7) ;- (EMAC) \r
+AT91C_EMAC_LINK EQU (0x1 << 9) ;- (EMAC) \r
+AT91C_EMAC_ROVR EQU (0x1 << 10) ;- (EMAC) \r
+AT91C_EMAC_HRESP EQU (0x1 << 11) ;- (EMAC) \r
+AT91C_EMAC_PFRE EQU (0x1 << 12) ;- (EMAC) \r
+AT91C_EMAC_PTZ EQU (0x1 << 13) ;- (EMAC) \r
+// - -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- \r
+// - -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- \r
+// - -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- \r
+// - -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- \r
+AT91C_EMAC_DATA EQU (0xFFFF << 0) ;- (EMAC) \r
+AT91C_EMAC_CODE EQU (0x3 << 16) ;- (EMAC) \r
+AT91C_EMAC_REGA EQU (0x1F << 18) ;- (EMAC) \r
+AT91C_EMAC_PHYA EQU (0x1F << 23) ;- (EMAC) \r
+AT91C_EMAC_RW EQU (0x3 << 28) ;- (EMAC) \r
+AT91C_EMAC_SOF EQU (0x3 << 30) ;- (EMAC) \r
+// - -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- \r
+AT91C_EMAC_RMII EQU (0x1 << 0) ;- (EMAC) Reduce MII\r
+// - -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- \r
+AT91C_EMAC_IP EQU (0xFFFF << 0) ;- (EMAC) ARP request IP address\r
+AT91C_EMAC_MAG EQU (0x1 << 16) ;- (EMAC) Magic packet event enable\r
+AT91C_EMAC_ARP EQU (0x1 << 17) ;- (EMAC) ARP request event enable\r
+AT91C_EMAC_SA1 EQU (0x1 << 18) ;- (EMAC) Specific address register 1 event enable\r
+// - -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- \r
+AT91C_EMAC_REVREF EQU (0xFFFF << 0) ;- (EMAC) \r
+AT91C_EMAC_PARTREF EQU (0xFFFF << 16) ;- (EMAC) \r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Analog to Digital Convertor\r
+// - *****************************************************************************\r
+// - -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- \r
+AT91C_ADC_SWRST EQU (0x1 << 0) ;- (ADC) Software Reset\r
+AT91C_ADC_START EQU (0x1 << 1) ;- (ADC) Start Conversion\r
+// - -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- \r
+AT91C_ADC_TRGEN EQU (0x1 << 0) ;- (ADC) Trigger Enable\r
+AT91C_ADC_TRGEN_DIS EQU (0x0) ;- (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software\r
+AT91C_ADC_TRGEN_EN EQU (0x1) ;- (ADC) Hardware trigger selected by TRGSEL field is enabled.\r
+AT91C_ADC_TRGSEL EQU (0x7 << 1) ;- (ADC) Trigger Selection\r
+AT91C_ADC_TRGSEL_TIOA0 EQU (0x0 << 1) ;- (ADC) Selected TRGSEL = TIAO0\r
+AT91C_ADC_TRGSEL_TIOA1 EQU (0x1 << 1) ;- (ADC) Selected TRGSEL = TIAO1\r
+AT91C_ADC_TRGSEL_TIOA2 EQU (0x2 << 1) ;- (ADC) Selected TRGSEL = TIAO2\r
+AT91C_ADC_TRGSEL_TIOA3 EQU (0x3 << 1) ;- (ADC) Selected TRGSEL = TIAO3\r
+AT91C_ADC_TRGSEL_TIOA4 EQU (0x4 << 1) ;- (ADC) Selected TRGSEL = TIAO4\r
+AT91C_ADC_TRGSEL_TIOA5 EQU (0x5 << 1) ;- (ADC) Selected TRGSEL = TIAO5\r
+AT91C_ADC_TRGSEL_EXT EQU (0x6 << 1) ;- (ADC) Selected TRGSEL = External Trigger\r
+AT91C_ADC_LOWRES EQU (0x1 << 4) ;- (ADC) Resolution.\r
+AT91C_ADC_LOWRES_10_BIT EQU (0x0 << 4) ;- (ADC) 10-bit resolution\r
+AT91C_ADC_LOWRES_8_BIT EQU (0x1 << 4) ;- (ADC) 8-bit resolution\r
+AT91C_ADC_SLEEP EQU (0x1 << 5) ;- (ADC) Sleep Mode\r
+AT91C_ADC_SLEEP_NORMAL_MODE EQU (0x0 << 5) ;- (ADC) Normal Mode\r
+AT91C_ADC_SLEEP_MODE EQU (0x1 << 5) ;- (ADC) Sleep Mode\r
+AT91C_ADC_PRESCAL EQU (0x3F << 8) ;- (ADC) Prescaler rate selection\r
+AT91C_ADC_STARTUP EQU (0x1F << 16) ;- (ADC) Startup Time\r
+AT91C_ADC_SHTIM EQU (0xF << 24) ;- (ADC) Sample & Hold Time\r
+// - -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- \r
+AT91C_ADC_CH0 EQU (0x1 << 0) ;- (ADC) Channel 0\r
+AT91C_ADC_CH1 EQU (0x1 << 1) ;- (ADC) Channel 1\r
+AT91C_ADC_CH2 EQU (0x1 << 2) ;- (ADC) Channel 2\r
+AT91C_ADC_CH3 EQU (0x1 << 3) ;- (ADC) Channel 3\r
+AT91C_ADC_CH4 EQU (0x1 << 4) ;- (ADC) Channel 4\r
+AT91C_ADC_CH5 EQU (0x1 << 5) ;- (ADC) Channel 5\r
+AT91C_ADC_CH6 EQU (0x1 << 6) ;- (ADC) Channel 6\r
+AT91C_ADC_CH7 EQU (0x1 << 7) ;- (ADC) Channel 7\r
+// - -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- \r
+// - -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- \r
+// - -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- \r
+AT91C_ADC_EOC0 EQU (0x1 << 0) ;- (ADC) End of Conversion\r
+AT91C_ADC_EOC1 EQU (0x1 << 1) ;- (ADC) End of Conversion\r
+AT91C_ADC_EOC2 EQU (0x1 << 2) ;- (ADC) End of Conversion\r
+AT91C_ADC_EOC3 EQU (0x1 << 3) ;- (ADC) End of Conversion\r
+AT91C_ADC_EOC4 EQU (0x1 << 4) ;- (ADC) End of Conversion\r
+AT91C_ADC_EOC5 EQU (0x1 << 5) ;- (ADC) End of Conversion\r
+AT91C_ADC_EOC6 EQU (0x1 << 6) ;- (ADC) End of Conversion\r
+AT91C_ADC_EOC7 EQU (0x1 << 7) ;- (ADC) End of Conversion\r
+AT91C_ADC_OVRE0 EQU (0x1 << 8) ;- (ADC) Overrun Error\r
+AT91C_ADC_OVRE1 EQU (0x1 << 9) ;- (ADC) Overrun Error\r
+AT91C_ADC_OVRE2 EQU (0x1 << 10) ;- (ADC) Overrun Error\r
+AT91C_ADC_OVRE3 EQU (0x1 << 11) ;- (ADC) Overrun Error\r
+AT91C_ADC_OVRE4 EQU (0x1 << 12) ;- (ADC) Overrun Error\r
+AT91C_ADC_OVRE5 EQU (0x1 << 13) ;- (ADC) Overrun Error\r
+AT91C_ADC_OVRE6 EQU (0x1 << 14) ;- (ADC) Overrun Error\r
+AT91C_ADC_OVRE7 EQU (0x1 << 15) ;- (ADC) Overrun Error\r
+AT91C_ADC_DRDY EQU (0x1 << 16) ;- (ADC) Data Ready\r
+AT91C_ADC_GOVRE EQU (0x1 << 17) ;- (ADC) General Overrun\r
+AT91C_ADC_ENDRX EQU (0x1 << 18) ;- (ADC) End of Receiver Transfer\r
+AT91C_ADC_RXBUFF EQU (0x1 << 19) ;- (ADC) RXBUFF Interrupt\r
+// - -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- \r
+AT91C_ADC_LDATA EQU (0x3FF << 0) ;- (ADC) Last Data Converted\r
+// - -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- \r
+// - -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- \r
+// - -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- \r
+// - -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- \r
+AT91C_ADC_DATA EQU (0x3FF << 0) ;- (ADC) Converted Data\r
+// - -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- \r
+// - -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- \r
+// - -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- \r
+// - -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- \r
+// - -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- \r
+// - -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- \r
+// - -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- \r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Advanced Encryption Standard\r
+// - *****************************************************************************\r
+// - -------- AES_CR : (AES Offset: 0x0) Control Register -------- \r
+AT91C_AES_START EQU (0x1 << 0) ;- (AES) Starts Processing\r
+AT91C_AES_SWRST EQU (0x1 << 8) ;- (AES) Software Reset\r
+AT91C_AES_LOADSEED EQU (0x1 << 16) ;- (AES) Random Number Generator Seed Loading\r
+// - -------- AES_MR : (AES Offset: 0x4) Mode Register -------- \r
+AT91C_AES_CIPHER EQU (0x1 << 0) ;- (AES) Processing Mode\r
+AT91C_AES_PROCDLY EQU (0xF << 4) ;- (AES) Processing Delay\r
+AT91C_AES_SMOD EQU (0x3 << 8) ;- (AES) Start Mode\r
+AT91C_AES_SMOD_MANUAL EQU (0x0 << 8) ;- (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.\r
+AT91C_AES_SMOD_AUTO EQU (0x1 << 8) ;- (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).\r
+AT91C_AES_SMOD_PDC EQU (0x2 << 8) ;- (AES) PDC Mode (cf datasheet).\r
+AT91C_AES_OPMOD EQU (0x7 << 12) ;- (AES) Operation Mode\r
+AT91C_AES_OPMOD_ECB EQU (0x0 << 12) ;- (AES) ECB Electronic CodeBook mode.\r
+AT91C_AES_OPMOD_CBC EQU (0x1 << 12) ;- (AES) CBC Cipher Block Chaining mode.\r
+AT91C_AES_OPMOD_OFB EQU (0x2 << 12) ;- (AES) OFB Output Feedback mode.\r
+AT91C_AES_OPMOD_CFB EQU (0x3 << 12) ;- (AES) CFB Cipher Feedback mode.\r
+AT91C_AES_OPMOD_CTR EQU (0x4 << 12) ;- (AES) CTR Counter mode.\r
+AT91C_AES_LOD EQU (0x1 << 15) ;- (AES) Last Output Data Mode\r
+AT91C_AES_CFBS EQU (0x7 << 16) ;- (AES) Cipher Feedback Data Size\r
+AT91C_AES_CFBS_128_BIT EQU (0x0 << 16) ;- (AES) 128-bit.\r
+AT91C_AES_CFBS_64_BIT EQU (0x1 << 16) ;- (AES) 64-bit.\r
+AT91C_AES_CFBS_32_BIT EQU (0x2 << 16) ;- (AES) 32-bit.\r
+AT91C_AES_CFBS_16_BIT EQU (0x3 << 16) ;- (AES) 16-bit.\r
+AT91C_AES_CFBS_8_BIT EQU (0x4 << 16) ;- (AES) 8-bit.\r
+AT91C_AES_CKEY EQU (0xF << 20) ;- (AES) Countermeasure Key\r
+AT91C_AES_CTYPE EQU (0x1F << 24) ;- (AES) Countermeasure Type\r
+AT91C_AES_CTYPE_TYPE1_EN EQU (0x1 << 24) ;- (AES) Countermeasure type 1 is enabled.\r
+AT91C_AES_CTYPE_TYPE2_EN EQU (0x2 << 24) ;- (AES) Countermeasure type 2 is enabled.\r
+AT91C_AES_CTYPE_TYPE3_EN EQU (0x4 << 24) ;- (AES) Countermeasure type 3 is enabled.\r
+AT91C_AES_CTYPE_TYPE4_EN EQU (0x8 << 24) ;- (AES) Countermeasure type 4 is enabled.\r
+AT91C_AES_CTYPE_TYPE5_EN EQU (0x10 << 24) ;- (AES) Countermeasure type 5 is enabled.\r
+// - -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- \r
+AT91C_AES_DATRDY EQU (0x1 << 0) ;- (AES) DATRDY\r
+AT91C_AES_ENDRX EQU (0x1 << 1) ;- (AES) PDC Read Buffer End\r
+AT91C_AES_ENDTX EQU (0x1 << 2) ;- (AES) PDC Write Buffer End\r
+AT91C_AES_RXBUFF EQU (0x1 << 3) ;- (AES) PDC Read Buffer Full\r
+AT91C_AES_TXBUFE EQU (0x1 << 4) ;- (AES) PDC Write Buffer Empty\r
+AT91C_AES_URAD EQU (0x1 << 8) ;- (AES) Unspecified Register Access Detection\r
+// - -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- \r
+// - -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- \r
+// - -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- \r
+AT91C_AES_URAT EQU (0x7 << 12) ;- (AES) Unspecified Register Access Type Status\r
+AT91C_AES_URAT_IN_DAT_WRITE_DATPROC EQU (0x0 << 12) ;- (AES) Input data register written during the data processing in PDC mode.\r
+AT91C_AES_URAT_OUT_DAT_READ_DATPROC EQU (0x1 << 12) ;- (AES) Output data register read during the data processing.\r
+AT91C_AES_URAT_MODEREG_WRITE_DATPROC EQU (0x2 << 12) ;- (AES) Mode register written during the data processing.\r
+AT91C_AES_URAT_OUT_DAT_READ_SUBKEY EQU (0x3 << 12) ;- (AES) Output data register read during the sub-keys generation.\r
+AT91C_AES_URAT_MODEREG_WRITE_SUBKEY EQU (0x4 << 12) ;- (AES) Mode register written during the sub-keys generation.\r
+AT91C_AES_URAT_WO_REG_READ EQU (0x5 << 12) ;- (AES) Write-only register read access.\r
+\r
+// - *****************************************************************************\r
+// - SOFTWARE API DEFINITION FOR Triple Data Encryption Standard\r
+// - *****************************************************************************\r
+// - -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- \r
+AT91C_TDES_START EQU (0x1 << 0) ;- (TDES) Starts Processing\r
+AT91C_TDES_SWRST EQU (0x1 << 8) ;- (TDES) Software Reset\r
+// - -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- \r
+AT91C_TDES_CIPHER EQU (0x1 << 0) ;- (TDES) Processing Mode\r
+AT91C_TDES_TDESMOD EQU (0x1 << 1) ;- (TDES) Single or Triple DES Mode\r
+AT91C_TDES_KEYMOD EQU (0x1 << 4) ;- (TDES) Key Mode\r
+AT91C_TDES_SMOD EQU (0x3 << 8) ;- (TDES) Start Mode\r
+AT91C_TDES_SMOD_MANUAL EQU (0x0 << 8) ;- (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.\r
+AT91C_TDES_SMOD_AUTO EQU (0x1 << 8) ;- (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).\r
+AT91C_TDES_SMOD_PDC EQU (0x2 << 8) ;- (TDES) PDC Mode (cf datasheet).\r
+AT91C_TDES_OPMOD EQU (0x3 << 12) ;- (TDES) Operation Mode\r
+AT91C_TDES_OPMOD_ECB EQU (0x0 << 12) ;- (TDES) ECB Electronic CodeBook mode.\r
+AT91C_TDES_OPMOD_CBC EQU (0x1 << 12) ;- (TDES) CBC Cipher Block Chaining mode.\r
+AT91C_TDES_OPMOD_OFB EQU (0x2 << 12) ;- (TDES) OFB Output Feedback mode.\r
+AT91C_TDES_OPMOD_CFB EQU (0x3 << 12) ;- (TDES) CFB Cipher Feedback mode.\r
+AT91C_TDES_LOD EQU (0x1 << 15) ;- (TDES) Last Output Data Mode\r
+AT91C_TDES_CFBS EQU (0x3 << 16) ;- (TDES) Cipher Feedback Data Size\r
+AT91C_TDES_CFBS_64_BIT EQU (0x0 << 16) ;- (TDES) 64-bit.\r
+AT91C_TDES_CFBS_32_BIT EQU (0x1 << 16) ;- (TDES) 32-bit.\r
+AT91C_TDES_CFBS_16_BIT EQU (0x2 << 16) ;- (TDES) 16-bit.\r
+AT91C_TDES_CFBS_8_BIT EQU (0x3 << 16) ;- (TDES) 8-bit.\r
+// - -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- \r
+AT91C_TDES_DATRDY EQU (0x1 << 0) ;- (TDES) DATRDY\r
+AT91C_TDES_ENDRX EQU (0x1 << 1) ;- (TDES) PDC Read Buffer End\r
+AT91C_TDES_ENDTX EQU (0x1 << 2) ;- (TDES) PDC Write Buffer End\r
+AT91C_TDES_RXBUFF EQU (0x1 << 3) ;- (TDES) PDC Read Buffer Full\r
+AT91C_TDES_TXBUFE EQU (0x1 << 4) ;- (TDES) PDC Write Buffer Empty\r
+AT91C_TDES_URAD EQU (0x1 << 8) ;- (TDES) Unspecified Register Access Detection\r
+// - -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- \r
+// - -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- \r
+// - -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- \r
+AT91C_TDES_URAT EQU (0x3 << 12) ;- (TDES) Unspecified Register Access Type Status\r
+AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC EQU (0x0 << 12) ;- (TDES) Input data register written during the data processing in PDC mode.\r
+AT91C_TDES_URAT_OUT_DAT_READ_DATPROC EQU (0x1 << 12) ;- (TDES) Output data register read during the data processing.\r
+AT91C_TDES_URAT_MODEREG_WRITE_DATPROC EQU (0x2 << 12) ;- (TDES) Mode register written during the data processing.\r
+AT91C_TDES_URAT_WO_REG_READ EQU (0x3 << 12) ;- (TDES) Write-only register read access.\r
+\r
+// - *****************************************************************************\r
+// - REGISTER ADDRESS DEFINITION FOR AT91SAM7X256\r
+// - *****************************************************************************\r
+// - ========== Register definition for SYS peripheral ========== \r
+// - ========== Register definition for AIC peripheral ========== \r
+AT91C_AIC_IVR EQU (0xFFFFF100) ;- (AIC) IRQ Vector Register\r
+AT91C_AIC_SMR EQU (0xFFFFF000) ;- (AIC) Source Mode Register\r
+AT91C_AIC_FVR EQU (0xFFFFF104) ;- (AIC) FIQ Vector Register\r
+AT91C_AIC_DCR EQU (0xFFFFF138) ;- (AIC) Debug Control Register (Protect)\r
+AT91C_AIC_EOICR EQU (0xFFFFF130) ;- (AIC) End of Interrupt Command Register\r
+AT91C_AIC_SVR EQU (0xFFFFF080) ;- (AIC) Source Vector Register\r
+AT91C_AIC_FFSR EQU (0xFFFFF148) ;- (AIC) Fast Forcing Status Register\r
+AT91C_AIC_ICCR EQU (0xFFFFF128) ;- (AIC) Interrupt Clear Command Register\r
+AT91C_AIC_ISR EQU (0xFFFFF108) ;- (AIC) Interrupt Status Register\r
+AT91C_AIC_IMR EQU (0xFFFFF110) ;- (AIC) Interrupt Mask Register\r
+AT91C_AIC_IPR EQU (0xFFFFF10C) ;- (AIC) Interrupt Pending Register\r
+AT91C_AIC_FFER EQU (0xFFFFF140) ;- (AIC) Fast Forcing Enable Register\r
+AT91C_AIC_IECR EQU (0xFFFFF120) ;- (AIC) Interrupt Enable Command Register\r
+AT91C_AIC_ISCR EQU (0xFFFFF12C) ;- (AIC) Interrupt Set Command Register\r
+AT91C_AIC_FFDR EQU (0xFFFFF144) ;- (AIC) Fast Forcing Disable Register\r
+AT91C_AIC_CISR EQU (0xFFFFF114) ;- (AIC) Core Interrupt Status Register\r
+AT91C_AIC_IDCR EQU (0xFFFFF124) ;- (AIC) Interrupt Disable Command Register\r
+AT91C_AIC_SPU EQU (0xFFFFF134) ;- (AIC) Spurious Vector Register\r
+// - ========== Register definition for PDC_DBGU peripheral ========== \r
+AT91C_DBGU_TCR EQU (0xFFFFF30C) ;- (PDC_DBGU) Transmit Counter Register\r
+AT91C_DBGU_RNPR EQU (0xFFFFF310) ;- (PDC_DBGU) Receive Next Pointer Register\r
+AT91C_DBGU_TNPR EQU (0xFFFFF318) ;- (PDC_DBGU) Transmit Next Pointer Register\r
+AT91C_DBGU_TPR EQU (0xFFFFF308) ;- (PDC_DBGU) Transmit Pointer Register\r
+AT91C_DBGU_RPR EQU (0xFFFFF300) ;- (PDC_DBGU) Receive Pointer Register\r
+AT91C_DBGU_RCR EQU (0xFFFFF304) ;- (PDC_DBGU) Receive Counter Register\r
+AT91C_DBGU_RNCR EQU (0xFFFFF314) ;- (PDC_DBGU) Receive Next Counter Register\r
+AT91C_DBGU_PTCR EQU (0xFFFFF320) ;- (PDC_DBGU) PDC Transfer Control Register\r
+AT91C_DBGU_PTSR EQU (0xFFFFF324) ;- (PDC_DBGU) PDC Transfer Status Register\r
+AT91C_DBGU_TNCR EQU (0xFFFFF31C) ;- (PDC_DBGU) Transmit Next Counter Register\r
+// - ========== Register definition for DBGU peripheral ========== \r
+AT91C_DBGU_EXID EQU (0xFFFFF244) ;- (DBGU) Chip ID Extension Register\r
+AT91C_DBGU_BRGR EQU (0xFFFFF220) ;- (DBGU) Baud Rate Generator Register\r
+AT91C_DBGU_IDR EQU (0xFFFFF20C) ;- (DBGU) Interrupt Disable Register\r
+AT91C_DBGU_CSR EQU (0xFFFFF214) ;- (DBGU) Channel Status Register\r
+AT91C_DBGU_CIDR EQU (0xFFFFF240) ;- (DBGU) Chip ID Register\r
+AT91C_DBGU_MR EQU (0xFFFFF204) ;- (DBGU) Mode Register\r
+AT91C_DBGU_IMR EQU (0xFFFFF210) ;- (DBGU) Interrupt Mask Register\r
+AT91C_DBGU_CR EQU (0xFFFFF200) ;- (DBGU) Control Register\r
+AT91C_DBGU_FNTR EQU (0xFFFFF248) ;- (DBGU) Force NTRST Register\r
+AT91C_DBGU_THR EQU (0xFFFFF21C) ;- (DBGU) Transmitter Holding Register\r
+AT91C_DBGU_RHR EQU (0xFFFFF218) ;- (DBGU) Receiver Holding Register\r
+AT91C_DBGU_IER EQU (0xFFFFF208) ;- (DBGU) Interrupt Enable Register\r
+// - ========== Register definition for PIOA peripheral ========== \r
+AT91C_PIOA_ODR EQU (0xFFFFF414) ;- (PIOA) Output Disable Registerr\r
+AT91C_PIOA_SODR EQU (0xFFFFF430) ;- (PIOA) Set Output Data Register\r
+AT91C_PIOA_ISR EQU (0xFFFFF44C) ;- (PIOA) Interrupt Status Register\r
+AT91C_PIOA_ABSR EQU (0xFFFFF478) ;- (PIOA) AB Select Status Register\r
+AT91C_PIOA_IER EQU (0xFFFFF440) ;- (PIOA) Interrupt Enable Register\r
+AT91C_PIOA_PPUDR EQU (0xFFFFF460) ;- (PIOA) Pull-up Disable Register\r
+AT91C_PIOA_IMR EQU (0xFFFFF448) ;- (PIOA) Interrupt Mask Register\r
+AT91C_PIOA_PER EQU (0xFFFFF400) ;- (PIOA) PIO Enable Register\r
+AT91C_PIOA_IFDR EQU (0xFFFFF424) ;- (PIOA) Input Filter Disable Register\r
+AT91C_PIOA_OWDR EQU (0xFFFFF4A4) ;- (PIOA) Output Write Disable Register\r
+AT91C_PIOA_MDSR EQU (0xFFFFF458) ;- (PIOA) Multi-driver Status Register\r
+AT91C_PIOA_IDR EQU (0xFFFFF444) ;- (PIOA) Interrupt Disable Register\r
+AT91C_PIOA_ODSR EQU (0xFFFFF438) ;- (PIOA) Output Data Status Register\r
+AT91C_PIOA_PPUSR EQU (0xFFFFF468) ;- (PIOA) Pull-up Status Register\r
+AT91C_PIOA_OWSR EQU (0xFFFFF4A8) ;- (PIOA) Output Write Status Register\r
+AT91C_PIOA_BSR EQU (0xFFFFF474) ;- (PIOA) Select B Register\r
+AT91C_PIOA_OWER EQU (0xFFFFF4A0) ;- (PIOA) Output Write Enable Register\r
+AT91C_PIOA_IFER EQU (0xFFFFF420) ;- (PIOA) Input Filter Enable Register\r
+AT91C_PIOA_PDSR EQU (0xFFFFF43C) ;- (PIOA) Pin Data Status Register\r
+AT91C_PIOA_PPUER EQU (0xFFFFF464) ;- (PIOA) Pull-up Enable Register\r
+AT91C_PIOA_OSR EQU (0xFFFFF418) ;- (PIOA) Output Status Register\r
+AT91C_PIOA_ASR EQU (0xFFFFF470) ;- (PIOA) Select A Register\r
+AT91C_PIOA_MDDR EQU (0xFFFFF454) ;- (PIOA) Multi-driver Disable Register\r
+AT91C_PIOA_CODR EQU (0xFFFFF434) ;- (PIOA) Clear Output Data Register\r
+AT91C_PIOA_MDER EQU (0xFFFFF450) ;- (PIOA) Multi-driver Enable Register\r
+AT91C_PIOA_PDR EQU (0xFFFFF404) ;- (PIOA) PIO Disable Register\r
+AT91C_PIOA_IFSR EQU (0xFFFFF428) ;- (PIOA) Input Filter Status Register\r
+AT91C_PIOA_OER EQU (0xFFFFF410) ;- (PIOA) Output Enable Register\r
+AT91C_PIOA_PSR EQU (0xFFFFF408) ;- (PIOA) PIO Status Register\r
+// - ========== Register definition for PIOB peripheral ========== \r
+AT91C_PIOB_OWDR EQU (0xFFFFF6A4) ;- (PIOB) Output Write Disable Register\r
+AT91C_PIOB_MDER EQU (0xFFFFF650) ;- (PIOB) Multi-driver Enable Register\r
+AT91C_PIOB_PPUSR EQU (0xFFFFF668) ;- (PIOB) Pull-up Status Register\r
+AT91C_PIOB_IMR EQU (0xFFFFF648) ;- (PIOB) Interrupt Mask Register\r
+AT91C_PIOB_ASR EQU (0xFFFFF670) ;- (PIOB) Select A Register\r
+AT91C_PIOB_PPUDR EQU (0xFFFFF660) ;- (PIOB) Pull-up Disable Register\r
+AT91C_PIOB_PSR EQU (0xFFFFF608) ;- (PIOB) PIO Status Register\r
+AT91C_PIOB_IER EQU (0xFFFFF640) ;- (PIOB) Interrupt Enable Register\r
+AT91C_PIOB_CODR EQU (0xFFFFF634) ;- (PIOB) Clear Output Data Register\r
+AT91C_PIOB_OWER EQU (0xFFFFF6A0) ;- (PIOB) Output Write Enable Register\r
+AT91C_PIOB_ABSR EQU (0xFFFFF678) ;- (PIOB) AB Select Status Register\r
+AT91C_PIOB_IFDR EQU (0xFFFFF624) ;- (PIOB) Input Filter Disable Register\r
+AT91C_PIOB_PDSR EQU (0xFFFFF63C) ;- (PIOB) Pin Data Status Register\r
+AT91C_PIOB_IDR EQU (0xFFFFF644) ;- (PIOB) Interrupt Disable Register\r
+AT91C_PIOB_OWSR EQU (0xFFFFF6A8) ;- (PIOB) Output Write Status Register\r
+AT91C_PIOB_PDR EQU (0xFFFFF604) ;- (PIOB) PIO Disable Register\r
+AT91C_PIOB_ODR EQU (0xFFFFF614) ;- (PIOB) Output Disable Registerr\r
+AT91C_PIOB_IFSR EQU (0xFFFFF628) ;- (PIOB) Input Filter Status Register\r
+AT91C_PIOB_PPUER EQU (0xFFFFF664) ;- (PIOB) Pull-up Enable Register\r
+AT91C_PIOB_SODR EQU (0xFFFFF630) ;- (PIOB) Set Output Data Register\r
+AT91C_PIOB_ISR EQU (0xFFFFF64C) ;- (PIOB) Interrupt Status Register\r
+AT91C_PIOB_ODSR EQU (0xFFFFF638) ;- (PIOB) Output Data Status Register\r
+AT91C_PIOB_OSR EQU (0xFFFFF618) ;- (PIOB) Output Status Register\r
+AT91C_PIOB_MDSR EQU (0xFFFFF658) ;- (PIOB) Multi-driver Status Register\r
+AT91C_PIOB_IFER EQU (0xFFFFF620) ;- (PIOB) Input Filter Enable Register\r
+AT91C_PIOB_BSR EQU (0xFFFFF674) ;- (PIOB) Select B Register\r
+AT91C_PIOB_MDDR EQU (0xFFFFF654) ;- (PIOB) Multi-driver Disable Register\r
+AT91C_PIOB_OER EQU (0xFFFFF610) ;- (PIOB) Output Enable Register\r
+AT91C_PIOB_PER EQU (0xFFFFF600) ;- (PIOB) PIO Enable Register\r
+// - ========== Register definition for CKGR peripheral ========== \r
+AT91C_CKGR_MOR EQU (0xFFFFFC20) ;- (CKGR) Main Oscillator Register\r
+AT91C_CKGR_PLLR EQU (0xFFFFFC2C) ;- (CKGR) PLL Register\r
+AT91C_CKGR_MCFR EQU (0xFFFFFC24) ;- (CKGR) Main Clock Frequency Register\r
+// - ========== Register definition for PMC peripheral ========== \r
+AT91C_PMC_IDR EQU (0xFFFFFC64) ;- (PMC) Interrupt Disable Register\r
+AT91C_PMC_MOR EQU (0xFFFFFC20) ;- (PMC) Main Oscillator Register\r
+AT91C_PMC_PLLR EQU (0xFFFFFC2C) ;- (PMC) PLL Register\r
+AT91C_PMC_PCER EQU (0xFFFFFC10) ;- (PMC) Peripheral Clock Enable Register\r
+AT91C_PMC_PCKR EQU (0xFFFFFC40) ;- (PMC) Programmable Clock Register\r
+AT91C_PMC_MCKR EQU (0xFFFFFC30) ;- (PMC) Master Clock Register\r
+AT91C_PMC_SCDR EQU (0xFFFFFC04) ;- (PMC) System Clock Disable Register\r
+AT91C_PMC_PCDR EQU (0xFFFFFC14) ;- (PMC) Peripheral Clock Disable Register\r
+AT91C_PMC_SCSR EQU (0xFFFFFC08) ;- (PMC) System Clock Status Register\r
+AT91C_PMC_PCSR EQU (0xFFFFFC18) ;- (PMC) Peripheral Clock Status Register\r
+AT91C_PMC_MCFR EQU (0xFFFFFC24) ;- (PMC) Main Clock Frequency Register\r
+AT91C_PMC_SCER EQU (0xFFFFFC00) ;- (PMC) System Clock Enable Register\r
+AT91C_PMC_IMR EQU (0xFFFFFC6C) ;- (PMC) Interrupt Mask Register\r
+AT91C_PMC_IER EQU (0xFFFFFC60) ;- (PMC) Interrupt Enable Register\r
+AT91C_PMC_SR EQU (0xFFFFFC68) ;- (PMC) Status Register\r
+// - ========== Register definition for RSTC peripheral ========== \r
+AT91C_RSTC_RCR EQU (0xFFFFFD00) ;- (RSTC) Reset Control Register\r
+AT91C_RSTC_RMR EQU (0xFFFFFD08) ;- (RSTC) Reset Mode Register\r
+AT91C_RSTC_RSR EQU (0xFFFFFD04) ;- (RSTC) Reset Status Register\r
+// - ========== Register definition for RTTC peripheral ========== \r
+AT91C_RTTC_RTSR EQU (0xFFFFFD2C) ;- (RTTC) Real-time Status Register\r
+AT91C_RTTC_RTMR EQU (0xFFFFFD20) ;- (RTTC) Real-time Mode Register\r
+AT91C_RTTC_RTVR EQU (0xFFFFFD28) ;- (RTTC) Real-time Value Register\r
+AT91C_RTTC_RTAR EQU (0xFFFFFD24) ;- (RTTC) Real-time Alarm Register\r
+// - ========== Register definition for PITC peripheral ========== \r
+AT91C_PITC_PIVR EQU (0xFFFFFD38) ;- (PITC) Period Interval Value Register\r
+AT91C_PITC_PISR EQU (0xFFFFFD34) ;- (PITC) Period Interval Status Register\r
+AT91C_PITC_PIIR EQU (0xFFFFFD3C) ;- (PITC) Period Interval Image Register\r
+AT91C_PITC_PIMR EQU (0xFFFFFD30) ;- (PITC) Period Interval Mode Register\r
+// - ========== Register definition for WDTC peripheral ========== \r
+AT91C_WDTC_WDCR EQU (0xFFFFFD40) ;- (WDTC) Watchdog Control Register\r
+AT91C_WDTC_WDSR EQU (0xFFFFFD48) ;- (WDTC) Watchdog Status Register\r
+AT91C_WDTC_WDMR EQU (0xFFFFFD44) ;- (WDTC) Watchdog Mode Register\r
+// - ========== Register definition for VREG peripheral ========== \r
+AT91C_VREG_MR EQU (0xFFFFFD60) ;- (VREG) Voltage Regulator Mode Register\r
+// - ========== Register definition for MC peripheral ========== \r
+AT91C_MC_ASR EQU (0xFFFFFF04) ;- (MC) MC Abort Status Register\r
+AT91C_MC_RCR EQU (0xFFFFFF00) ;- (MC) MC Remap Control Register\r
+AT91C_MC_FCR EQU (0xFFFFFF64) ;- (MC) MC Flash Command Register\r
+AT91C_MC_AASR EQU (0xFFFFFF08) ;- (MC) MC Abort Address Status Register\r
+AT91C_MC_FSR EQU (0xFFFFFF68) ;- (MC) MC Flash Status Register\r
+AT91C_MC_FMR EQU (0xFFFFFF60) ;- (MC) MC Flash Mode Register\r
+// - ========== Register definition for PDC_SPI1 peripheral ========== \r
+AT91C_SPI1_PTCR EQU (0xFFFE4120) ;- (PDC_SPI1) PDC Transfer Control Register\r
+AT91C_SPI1_RPR EQU (0xFFFE4100) ;- (PDC_SPI1) Receive Pointer Register\r
+AT91C_SPI1_TNCR EQU (0xFFFE411C) ;- (PDC_SPI1) Transmit Next Counter Register\r
+AT91C_SPI1_TPR EQU (0xFFFE4108) ;- (PDC_SPI1) Transmit Pointer Register\r
+AT91C_SPI1_TNPR EQU (0xFFFE4118) ;- (PDC_SPI1) Transmit Next Pointer Register\r
+AT91C_SPI1_TCR EQU (0xFFFE410C) ;- (PDC_SPI1) Transmit Counter Register\r
+AT91C_SPI1_RCR EQU (0xFFFE4104) ;- (PDC_SPI1) Receive Counter Register\r
+AT91C_SPI1_RNPR EQU (0xFFFE4110) ;- (PDC_SPI1) Receive Next Pointer Register\r
+AT91C_SPI1_RNCR EQU (0xFFFE4114) ;- (PDC_SPI1) Receive Next Counter Register\r
+AT91C_SPI1_PTSR EQU (0xFFFE4124) ;- (PDC_SPI1) PDC Transfer Status Register\r
+// - ========== Register definition for SPI1 peripheral ========== \r
+AT91C_SPI1_IMR EQU (0xFFFE401C) ;- (SPI1) Interrupt Mask Register\r
+AT91C_SPI1_IER EQU (0xFFFE4014) ;- (SPI1) Interrupt Enable Register\r
+AT91C_SPI1_MR EQU (0xFFFE4004) ;- (SPI1) Mode Register\r
+AT91C_SPI1_RDR EQU (0xFFFE4008) ;- (SPI1) Receive Data Register\r
+AT91C_SPI1_IDR EQU (0xFFFE4018) ;- (SPI1) Interrupt Disable Register\r
+AT91C_SPI1_SR EQU (0xFFFE4010) ;- (SPI1) Status Register\r
+AT91C_SPI1_TDR EQU (0xFFFE400C) ;- (SPI1) Transmit Data Register\r
+AT91C_SPI1_CR EQU (0xFFFE4000) ;- (SPI1) Control Register\r
+AT91C_SPI1_CSR EQU (0xFFFE4030) ;- (SPI1) Chip Select Register\r
+// - ========== Register definition for PDC_SPI0 peripheral ========== \r
+AT91C_SPI0_PTCR EQU (0xFFFE0120) ;- (PDC_SPI0) PDC Transfer Control Register\r
+AT91C_SPI0_TPR EQU (0xFFFE0108) ;- (PDC_SPI0) Transmit Pointer Register\r
+AT91C_SPI0_TCR EQU (0xFFFE010C) ;- (PDC_SPI0) Transmit Counter Register\r
+AT91C_SPI0_RCR EQU (0xFFFE0104) ;- (PDC_SPI0) Receive Counter Register\r
+AT91C_SPI0_PTSR EQU (0xFFFE0124) ;- (PDC_SPI0) PDC Transfer Status Register\r
+AT91C_SPI0_RNPR EQU (0xFFFE0110) ;- (PDC_SPI0) Receive Next Pointer Register\r
+AT91C_SPI0_RPR EQU (0xFFFE0100) ;- (PDC_SPI0) Receive Pointer Register\r
+AT91C_SPI0_TNCR EQU (0xFFFE011C) ;- (PDC_SPI0) Transmit Next Counter Register\r
+AT91C_SPI0_RNCR EQU (0xFFFE0114) ;- (PDC_SPI0) Receive Next Counter Register\r
+AT91C_SPI0_TNPR EQU (0xFFFE0118) ;- (PDC_SPI0) Transmit Next Pointer Register\r
+// - ========== Register definition for SPI0 peripheral ========== \r
+AT91C_SPI0_IER EQU (0xFFFE0014) ;- (SPI0) Interrupt Enable Register\r
+AT91C_SPI0_SR EQU (0xFFFE0010) ;- (SPI0) Status Register\r
+AT91C_SPI0_IDR EQU (0xFFFE0018) ;- (SPI0) Interrupt Disable Register\r
+AT91C_SPI0_CR EQU (0xFFFE0000) ;- (SPI0) Control Register\r
+AT91C_SPI0_MR EQU (0xFFFE0004) ;- (SPI0) Mode Register\r
+AT91C_SPI0_IMR EQU (0xFFFE001C) ;- (SPI0) Interrupt Mask Register\r
+AT91C_SPI0_TDR EQU (0xFFFE000C) ;- (SPI0) Transmit Data Register\r
+AT91C_SPI0_RDR EQU (0xFFFE0008) ;- (SPI0) Receive Data Register\r
+AT91C_SPI0_CSR EQU (0xFFFE0030) ;- (SPI0) Chip Select Register\r
+// - ========== Register definition for PDC_US1 peripheral ========== \r
+AT91C_US1_RNCR EQU (0xFFFC4114) ;- (PDC_US1) Receive Next Counter Register\r
+AT91C_US1_PTCR EQU (0xFFFC4120) ;- (PDC_US1) PDC Transfer Control Register\r
+AT91C_US1_TCR EQU (0xFFFC410C) ;- (PDC_US1) Transmit Counter Register\r
+AT91C_US1_PTSR EQU (0xFFFC4124) ;- (PDC_US1) PDC Transfer Status Register\r
+AT91C_US1_TNPR EQU (0xFFFC4118) ;- (PDC_US1) Transmit Next Pointer Register\r
+AT91C_US1_RCR EQU (0xFFFC4104) ;- (PDC_US1) Receive Counter Register\r
+AT91C_US1_RNPR EQU (0xFFFC4110) ;- (PDC_US1) Receive Next Pointer Register\r
+AT91C_US1_RPR EQU (0xFFFC4100) ;- (PDC_US1) Receive Pointer Register\r
+AT91C_US1_TNCR EQU (0xFFFC411C) ;- (PDC_US1) Transmit Next Counter Register\r
+AT91C_US1_TPR EQU (0xFFFC4108) ;- (PDC_US1) Transmit Pointer Register\r
+// - ========== Register definition for US1 peripheral ========== \r
+AT91C_US1_IF EQU (0xFFFC404C) ;- (US1) IRDA_FILTER Register\r
+AT91C_US1_NER EQU (0xFFFC4044) ;- (US1) Nb Errors Register\r
+AT91C_US1_RTOR EQU (0xFFFC4024) ;- (US1) Receiver Time-out Register\r
+AT91C_US1_CSR EQU (0xFFFC4014) ;- (US1) Channel Status Register\r
+AT91C_US1_IDR EQU (0xFFFC400C) ;- (US1) Interrupt Disable Register\r
+AT91C_US1_IER EQU (0xFFFC4008) ;- (US1) Interrupt Enable Register\r
+AT91C_US1_THR EQU (0xFFFC401C) ;- (US1) Transmitter Holding Register\r
+AT91C_US1_TTGR EQU (0xFFFC4028) ;- (US1) Transmitter Time-guard Register\r
+AT91C_US1_RHR EQU (0xFFFC4018) ;- (US1) Receiver Holding Register\r
+AT91C_US1_BRGR EQU (0xFFFC4020) ;- (US1) Baud Rate Generator Register\r
+AT91C_US1_IMR EQU (0xFFFC4010) ;- (US1) Interrupt Mask Register\r
+AT91C_US1_FIDI EQU (0xFFFC4040) ;- (US1) FI_DI_Ratio Register\r
+AT91C_US1_CR EQU (0xFFFC4000) ;- (US1) Control Register\r
+AT91C_US1_MR EQU (0xFFFC4004) ;- (US1) Mode Register\r
+// - ========== Register definition for PDC_US0 peripheral ========== \r
+AT91C_US0_TNPR EQU (0xFFFC0118) ;- (PDC_US0) Transmit Next Pointer Register\r
+AT91C_US0_RNPR EQU (0xFFFC0110) ;- (PDC_US0) Receive Next Pointer Register\r
+AT91C_US0_TCR EQU (0xFFFC010C) ;- (PDC_US0) Transmit Counter Register\r
+AT91C_US0_PTCR EQU (0xFFFC0120) ;- (PDC_US0) PDC Transfer Control Register\r
+AT91C_US0_PTSR EQU (0xFFFC0124) ;- (PDC_US0) PDC Transfer Status Register\r
+AT91C_US0_TNCR EQU (0xFFFC011C) ;- (PDC_US0) Transmit Next Counter Register\r
+AT91C_US0_TPR EQU (0xFFFC0108) ;- (PDC_US0) Transmit Pointer Register\r
+AT91C_US0_RCR EQU (0xFFFC0104) ;- (PDC_US0) Receive Counter Register\r
+AT91C_US0_RPR EQU (0xFFFC0100) ;- (PDC_US0) Receive Pointer Register\r
+AT91C_US0_RNCR EQU (0xFFFC0114) ;- (PDC_US0) Receive Next Counter Register\r
+// - ========== Register definition for US0 peripheral ========== \r
+AT91C_US0_BRGR EQU (0xFFFC0020) ;- (US0) Baud Rate Generator Register\r
+AT91C_US0_NER EQU (0xFFFC0044) ;- (US0) Nb Errors Register\r
+AT91C_US0_CR EQU (0xFFFC0000) ;- (US0) Control Register\r
+AT91C_US0_IMR EQU (0xFFFC0010) ;- (US0) Interrupt Mask Register\r
+AT91C_US0_FIDI EQU (0xFFFC0040) ;- (US0) FI_DI_Ratio Register\r
+AT91C_US0_TTGR EQU (0xFFFC0028) ;- (US0) Transmitter Time-guard Register\r
+AT91C_US0_MR EQU (0xFFFC0004) ;- (US0) Mode Register\r
+AT91C_US0_RTOR EQU (0xFFFC0024) ;- (US0) Receiver Time-out Register\r
+AT91C_US0_CSR EQU (0xFFFC0014) ;- (US0) Channel Status Register\r
+AT91C_US0_RHR EQU (0xFFFC0018) ;- (US0) Receiver Holding Register\r
+AT91C_US0_IDR EQU (0xFFFC000C) ;- (US0) Interrupt Disable Register\r
+AT91C_US0_THR EQU (0xFFFC001C) ;- (US0) Transmitter Holding Register\r
+AT91C_US0_IF EQU (0xFFFC004C) ;- (US0) IRDA_FILTER Register\r
+AT91C_US0_IER EQU (0xFFFC0008) ;- (US0) Interrupt Enable Register\r
+// - ========== Register definition for PDC_SSC peripheral ========== \r
+AT91C_SSC_TNCR EQU (0xFFFD411C) ;- (PDC_SSC) Transmit Next Counter Register\r
+AT91C_SSC_RPR EQU (0xFFFD4100) ;- (PDC_SSC) Receive Pointer Register\r
+AT91C_SSC_RNCR EQU (0xFFFD4114) ;- (PDC_SSC) Receive Next Counter Register\r
+AT91C_SSC_TPR EQU (0xFFFD4108) ;- (PDC_SSC) Transmit Pointer Register\r
+AT91C_SSC_PTCR EQU (0xFFFD4120) ;- (PDC_SSC) PDC Transfer Control Register\r
+AT91C_SSC_TCR EQU (0xFFFD410C) ;- (PDC_SSC) Transmit Counter Register\r
+AT91C_SSC_RCR EQU (0xFFFD4104) ;- (PDC_SSC) Receive Counter Register\r
+AT91C_SSC_RNPR EQU (0xFFFD4110) ;- (PDC_SSC) Receive Next Pointer Register\r
+AT91C_SSC_TNPR EQU (0xFFFD4118) ;- (PDC_SSC) Transmit Next Pointer Register\r
+AT91C_SSC_PTSR EQU (0xFFFD4124) ;- (PDC_SSC) PDC Transfer Status Register\r
+// - ========== Register definition for SSC peripheral ========== \r
+AT91C_SSC_RHR EQU (0xFFFD4020) ;- (SSC) Receive Holding Register\r
+AT91C_SSC_RSHR EQU (0xFFFD4030) ;- (SSC) Receive Sync Holding Register\r
+AT91C_SSC_TFMR EQU (0xFFFD401C) ;- (SSC) Transmit Frame Mode Register\r
+AT91C_SSC_IDR EQU (0xFFFD4048) ;- (SSC) Interrupt Disable Register\r
+AT91C_SSC_THR EQU (0xFFFD4024) ;- (SSC) Transmit Holding Register\r
+AT91C_SSC_RCMR EQU (0xFFFD4010) ;- (SSC) Receive Clock ModeRegister\r
+AT91C_SSC_IER EQU (0xFFFD4044) ;- (SSC) Interrupt Enable Register\r
+AT91C_SSC_TSHR EQU (0xFFFD4034) ;- (SSC) Transmit Sync Holding Register\r
+AT91C_SSC_SR EQU (0xFFFD4040) ;- (SSC) Status Register\r
+AT91C_SSC_CMR EQU (0xFFFD4004) ;- (SSC) Clock Mode Register\r
+AT91C_SSC_TCMR EQU (0xFFFD4018) ;- (SSC) Transmit Clock Mode Register\r
+AT91C_SSC_CR EQU (0xFFFD4000) ;- (SSC) Control Register\r
+AT91C_SSC_IMR EQU (0xFFFD404C) ;- (SSC) Interrupt Mask Register\r
+AT91C_SSC_RFMR EQU (0xFFFD4014) ;- (SSC) Receive Frame Mode Register\r
+// - ========== Register definition for TWI peripheral ========== \r
+AT91C_TWI_IER EQU (0xFFFB8024) ;- (TWI) Interrupt Enable Register\r
+AT91C_TWI_CR EQU (0xFFFB8000) ;- (TWI) Control Register\r
+AT91C_TWI_SR EQU (0xFFFB8020) ;- (TWI) Status Register\r
+AT91C_TWI_IMR EQU (0xFFFB802C) ;- (TWI) Interrupt Mask Register\r
+AT91C_TWI_THR EQU (0xFFFB8034) ;- (TWI) Transmit Holding Register\r
+AT91C_TWI_IDR EQU (0xFFFB8028) ;- (TWI) Interrupt Disable Register\r
+AT91C_TWI_IADR EQU (0xFFFB800C) ;- (TWI) Internal Address Register\r
+AT91C_TWI_MMR EQU (0xFFFB8004) ;- (TWI) Master Mode Register\r
+AT91C_TWI_CWGR EQU (0xFFFB8010) ;- (TWI) Clock Waveform Generator Register\r
+AT91C_TWI_RHR EQU (0xFFFB8030) ;- (TWI) Receive Holding Register\r
+// - ========== Register definition for PWMC_CH3 peripheral ========== \r
+AT91C_PWMC_CH3_CUPDR EQU (0xFFFCC270) ;- (PWMC_CH3) Channel Update Register\r
+AT91C_PWMC_CH3_Reserved EQU (0xFFFCC274) ;- (PWMC_CH3) Reserved\r
+AT91C_PWMC_CH3_CPRDR EQU (0xFFFCC268) ;- (PWMC_CH3) Channel Period Register\r
+AT91C_PWMC_CH3_CDTYR EQU (0xFFFCC264) ;- (PWMC_CH3) Channel Duty Cycle Register\r
+AT91C_PWMC_CH3_CCNTR EQU (0xFFFCC26C) ;- (PWMC_CH3) Channel Counter Register\r
+AT91C_PWMC_CH3_CMR EQU (0xFFFCC260) ;- (PWMC_CH3) Channel Mode Register\r
+// - ========== Register definition for PWMC_CH2 peripheral ========== \r
+AT91C_PWMC_CH2_Reserved EQU (0xFFFCC254) ;- (PWMC_CH2) Reserved\r
+AT91C_PWMC_CH2_CMR EQU (0xFFFCC240) ;- (PWMC_CH2) Channel Mode Register\r
+AT91C_PWMC_CH2_CCNTR EQU (0xFFFCC24C) ;- (PWMC_CH2) Channel Counter Register\r
+AT91C_PWMC_CH2_CPRDR EQU (0xFFFCC248) ;- (PWMC_CH2) Channel Period Register\r
+AT91C_PWMC_CH2_CUPDR EQU (0xFFFCC250) ;- (PWMC_CH2) Channel Update Register\r
+AT91C_PWMC_CH2_CDTYR EQU (0xFFFCC244) ;- (PWMC_CH2) Channel Duty Cycle Register\r
+// - ========== Register definition for PWMC_CH1 peripheral ========== \r
+AT91C_PWMC_CH1_Reserved EQU (0xFFFCC234) ;- (PWMC_CH1) Reserved\r
+AT91C_PWMC_CH1_CUPDR EQU (0xFFFCC230) ;- (PWMC_CH1) Channel Update Register\r
+AT91C_PWMC_CH1_CPRDR EQU (0xFFFCC228) ;- (PWMC_CH1) Channel Period Register\r
+AT91C_PWMC_CH1_CCNTR EQU (0xFFFCC22C) ;- (PWMC_CH1) Channel Counter Register\r
+AT91C_PWMC_CH1_CDTYR EQU (0xFFFCC224) ;- (PWMC_CH1) Channel Duty Cycle Register\r
+AT91C_PWMC_CH1_CMR EQU (0xFFFCC220) ;- (PWMC_CH1) Channel Mode Register\r
+// - ========== Register definition for PWMC_CH0 peripheral ========== \r
+AT91C_PWMC_CH0_Reserved EQU (0xFFFCC214) ;- (PWMC_CH0) Reserved\r
+AT91C_PWMC_CH0_CPRDR EQU (0xFFFCC208) ;- (PWMC_CH0) Channel Period Register\r
+AT91C_PWMC_CH0_CDTYR EQU (0xFFFCC204) ;- (PWMC_CH0) Channel Duty Cycle Register\r
+AT91C_PWMC_CH0_CMR EQU (0xFFFCC200) ;- (PWMC_CH0) Channel Mode Register\r
+AT91C_PWMC_CH0_CUPDR EQU (0xFFFCC210) ;- (PWMC_CH0) Channel Update Register\r
+AT91C_PWMC_CH0_CCNTR EQU (0xFFFCC20C) ;- (PWMC_CH0) Channel Counter Register\r
+// - ========== Register definition for PWMC peripheral ========== \r
+AT91C_PWMC_IDR EQU (0xFFFCC014) ;- (PWMC) PWMC Interrupt Disable Register\r
+AT91C_PWMC_DIS EQU (0xFFFCC008) ;- (PWMC) PWMC Disable Register\r
+AT91C_PWMC_IER EQU (0xFFFCC010) ;- (PWMC) PWMC Interrupt Enable Register\r
+AT91C_PWMC_VR EQU (0xFFFCC0FC) ;- (PWMC) PWMC Version Register\r
+AT91C_PWMC_ISR EQU (0xFFFCC01C) ;- (PWMC) PWMC Interrupt Status Register\r
+AT91C_PWMC_SR EQU (0xFFFCC00C) ;- (PWMC) PWMC Status Register\r
+AT91C_PWMC_IMR EQU (0xFFFCC018) ;- (PWMC) PWMC Interrupt Mask Register\r
+AT91C_PWMC_MR EQU (0xFFFCC000) ;- (PWMC) PWMC Mode Register\r
+AT91C_PWMC_ENA EQU (0xFFFCC004) ;- (PWMC) PWMC Enable Register\r
+// - ========== Register definition for UDP peripheral ========== \r
+AT91C_UDP_IMR EQU (0xFFFB0018) ;- (UDP) Interrupt Mask Register\r
+AT91C_UDP_FADDR EQU (0xFFFB0008) ;- (UDP) Function Address Register\r
+AT91C_UDP_NUM EQU (0xFFFB0000) ;- (UDP) Frame Number Register\r
+AT91C_UDP_FDR EQU (0xFFFB0050) ;- (UDP) Endpoint FIFO Data Register\r
+AT91C_UDP_ISR EQU (0xFFFB001C) ;- (UDP) Interrupt Status Register\r
+AT91C_UDP_CSR EQU (0xFFFB0030) ;- (UDP) Endpoint Control and Status Register\r
+AT91C_UDP_IDR EQU (0xFFFB0014) ;- (UDP) Interrupt Disable Register\r
+AT91C_UDP_ICR EQU (0xFFFB0020) ;- (UDP) Interrupt Clear Register\r
+AT91C_UDP_RSTEP EQU (0xFFFB0028) ;- (UDP) Reset Endpoint Register\r
+AT91C_UDP_TXVC EQU (0xFFFB0074) ;- (UDP) Transceiver Control Register\r
+AT91C_UDP_GLBSTATE EQU (0xFFFB0004) ;- (UDP) Global State Register\r
+AT91C_UDP_IER EQU (0xFFFB0010) ;- (UDP) Interrupt Enable Register\r
+// - ========== Register definition for TC0 peripheral ========== \r
+AT91C_TC0_SR EQU (0xFFFA0020) ;- (TC0) Status Register\r
+AT91C_TC0_RC EQU (0xFFFA001C) ;- (TC0) Register C\r
+AT91C_TC0_RB EQU (0xFFFA0018) ;- (TC0) Register B\r
+AT91C_TC0_CCR EQU (0xFFFA0000) ;- (TC0) Channel Control Register\r
+AT91C_TC0_CMR EQU (0xFFFA0004) ;- (TC0) Channel Mode Register (Capture Mode / Waveform Mode)\r
+AT91C_TC0_IER EQU (0xFFFA0024) ;- (TC0) Interrupt Enable Register\r
+AT91C_TC0_RA EQU (0xFFFA0014) ;- (TC0) Register A\r
+AT91C_TC0_IDR EQU (0xFFFA0028) ;- (TC0) Interrupt Disable Register\r
+AT91C_TC0_CV EQU (0xFFFA0010) ;- (TC0) Counter Value\r
+AT91C_TC0_IMR EQU (0xFFFA002C) ;- (TC0) Interrupt Mask Register\r
+// - ========== Register definition for TC1 peripheral ========== \r
+AT91C_TC1_RB EQU (0xFFFA0058) ;- (TC1) Register B\r
+AT91C_TC1_CCR EQU (0xFFFA0040) ;- (TC1) Channel Control Register\r
+AT91C_TC1_IER EQU (0xFFFA0064) ;- (TC1) Interrupt Enable Register\r
+AT91C_TC1_IDR EQU (0xFFFA0068) ;- (TC1) Interrupt Disable Register\r
+AT91C_TC1_SR EQU (0xFFFA0060) ;- (TC1) Status Register\r
+AT91C_TC1_CMR EQU (0xFFFA0044) ;- (TC1) Channel Mode Register (Capture Mode / Waveform Mode)\r
+AT91C_TC1_RA EQU (0xFFFA0054) ;- (TC1) Register A\r
+AT91C_TC1_RC EQU (0xFFFA005C) ;- (TC1) Register C\r
+AT91C_TC1_IMR EQU (0xFFFA006C) ;- (TC1) Interrupt Mask Register\r
+AT91C_TC1_CV EQU (0xFFFA0050) ;- (TC1) Counter Value\r
+// - ========== Register definition for TC2 peripheral ========== \r
+AT91C_TC2_CMR EQU (0xFFFA0084) ;- (TC2) Channel Mode Register (Capture Mode / Waveform Mode)\r
+AT91C_TC2_CCR EQU (0xFFFA0080) ;- (TC2) Channel Control Register\r
+AT91C_TC2_CV EQU (0xFFFA0090) ;- (TC2) Counter Value\r
+AT91C_TC2_RA EQU (0xFFFA0094) ;- (TC2) Register A\r
+AT91C_TC2_RB EQU (0xFFFA0098) ;- (TC2) Register B\r
+AT91C_TC2_IDR EQU (0xFFFA00A8) ;- (TC2) Interrupt Disable Register\r
+AT91C_TC2_IMR EQU (0xFFFA00AC) ;- (TC2) Interrupt Mask Register\r
+AT91C_TC2_RC EQU (0xFFFA009C) ;- (TC2) Register C\r
+AT91C_TC2_IER EQU (0xFFFA00A4) ;- (TC2) Interrupt Enable Register\r
+AT91C_TC2_SR EQU (0xFFFA00A0) ;- (TC2) Status Register\r
+// - ========== Register definition for TCB peripheral ========== \r
+AT91C_TCB_BMR EQU (0xFFFA00C4) ;- (TCB) TC Block Mode Register\r
+AT91C_TCB_BCR EQU (0xFFFA00C0) ;- (TCB) TC Block Control Register\r
+// - ========== Register definition for CAN_MB0 peripheral ========== \r
+AT91C_CAN_MB0_MDL EQU (0xFFFD0214) ;- (CAN_MB0) MailBox Data Low Register\r
+AT91C_CAN_MB0_MAM EQU (0xFFFD0204) ;- (CAN_MB0) MailBox Acceptance Mask Register\r
+AT91C_CAN_MB0_MCR EQU (0xFFFD021C) ;- (CAN_MB0) MailBox Control Register\r
+AT91C_CAN_MB0_MID EQU (0xFFFD0208) ;- (CAN_MB0) MailBox ID Register\r
+AT91C_CAN_MB0_MSR EQU (0xFFFD0210) ;- (CAN_MB0) MailBox Status Register\r
+AT91C_CAN_MB0_MFID EQU (0xFFFD020C) ;- (CAN_MB0) MailBox Family ID Register\r
+AT91C_CAN_MB0_MDH EQU (0xFFFD0218) ;- (CAN_MB0) MailBox Data High Register\r
+AT91C_CAN_MB0_MMR EQU (0xFFFD0200) ;- (CAN_MB0) MailBox Mode Register\r
+// - ========== Register definition for CAN_MB1 peripheral ========== \r
+AT91C_CAN_MB1_MDL EQU (0xFFFD0234) ;- (CAN_MB1) MailBox Data Low Register\r
+AT91C_CAN_MB1_MID EQU (0xFFFD0228) ;- (CAN_MB1) MailBox ID Register\r
+AT91C_CAN_MB1_MMR EQU (0xFFFD0220) ;- (CAN_MB1) MailBox Mode Register\r
+AT91C_CAN_MB1_MSR EQU (0xFFFD0230) ;- (CAN_MB1) MailBox Status Register\r
+AT91C_CAN_MB1_MAM EQU (0xFFFD0224) ;- (CAN_MB1) MailBox Acceptance Mask Register\r
+AT91C_CAN_MB1_MDH EQU (0xFFFD0238) ;- (CAN_MB1) MailBox Data High Register\r
+AT91C_CAN_MB1_MCR EQU (0xFFFD023C) ;- (CAN_MB1) MailBox Control Register\r
+AT91C_CAN_MB1_MFID EQU (0xFFFD022C) ;- (CAN_MB1) MailBox Family ID Register\r
+// - ========== Register definition for CAN_MB2 peripheral ========== \r
+AT91C_CAN_MB2_MCR EQU (0xFFFD025C) ;- (CAN_MB2) MailBox Control Register\r
+AT91C_CAN_MB2_MDH EQU (0xFFFD0258) ;- (CAN_MB2) MailBox Data High Register\r
+AT91C_CAN_MB2_MID EQU (0xFFFD0248) ;- (CAN_MB2) MailBox ID Register\r
+AT91C_CAN_MB2_MDL EQU (0xFFFD0254) ;- (CAN_MB2) MailBox Data Low Register\r
+AT91C_CAN_MB2_MMR EQU (0xFFFD0240) ;- (CAN_MB2) MailBox Mode Register\r
+AT91C_CAN_MB2_MAM EQU (0xFFFD0244) ;- (CAN_MB2) MailBox Acceptance Mask Register\r
+AT91C_CAN_MB2_MFID EQU (0xFFFD024C) ;- (CAN_MB2) MailBox Family ID Register\r
+AT91C_CAN_MB2_MSR EQU (0xFFFD0250) ;- (CAN_MB2) MailBox Status Register\r
+// - ========== Register definition for CAN_MB3 peripheral ========== \r
+AT91C_CAN_MB3_MFID EQU (0xFFFD026C) ;- (CAN_MB3) MailBox Family ID Register\r
+AT91C_CAN_MB3_MAM EQU (0xFFFD0264) ;- (CAN_MB3) MailBox Acceptance Mask Register\r
+AT91C_CAN_MB3_MID EQU (0xFFFD0268) ;- (CAN_MB3) MailBox ID Register\r
+AT91C_CAN_MB3_MCR EQU (0xFFFD027C) ;- (CAN_MB3) MailBox Control Register\r
+AT91C_CAN_MB3_MMR EQU (0xFFFD0260) ;- (CAN_MB3) MailBox Mode Register\r
+AT91C_CAN_MB3_MSR EQU (0xFFFD0270) ;- (CAN_MB3) MailBox Status Register\r
+AT91C_CAN_MB3_MDL EQU (0xFFFD0274) ;- (CAN_MB3) MailBox Data Low Register\r
+AT91C_CAN_MB3_MDH EQU (0xFFFD0278) ;- (CAN_MB3) MailBox Data High Register\r
+// - ========== Register definition for CAN_MB4 peripheral ========== \r
+AT91C_CAN_MB4_MID EQU (0xFFFD0288) ;- (CAN_MB4) MailBox ID Register\r
+AT91C_CAN_MB4_MMR EQU (0xFFFD0280) ;- (CAN_MB4) MailBox Mode Register\r
+AT91C_CAN_MB4_MDH EQU (0xFFFD0298) ;- (CAN_MB4) MailBox Data High Register\r
+AT91C_CAN_MB4_MFID EQU (0xFFFD028C) ;- (CAN_MB4) MailBox Family ID Register\r
+AT91C_CAN_MB4_MSR EQU (0xFFFD0290) ;- (CAN_MB4) MailBox Status Register\r
+AT91C_CAN_MB4_MCR EQU (0xFFFD029C) ;- (CAN_MB4) MailBox Control Register\r
+AT91C_CAN_MB4_MDL EQU (0xFFFD0294) ;- (CAN_MB4) MailBox Data Low Register\r
+AT91C_CAN_MB4_MAM EQU (0xFFFD0284) ;- (CAN_MB4) MailBox Acceptance Mask Register\r
+// - ========== Register definition for CAN_MB5 peripheral ========== \r
+AT91C_CAN_MB5_MSR EQU (0xFFFD02B0) ;- (CAN_MB5) MailBox Status Register\r
+AT91C_CAN_MB5_MCR EQU (0xFFFD02BC) ;- (CAN_MB5) MailBox Control Register\r
+AT91C_CAN_MB5_MFID EQU (0xFFFD02AC) ;- (CAN_MB5) MailBox Family ID Register\r
+AT91C_CAN_MB5_MDH EQU (0xFFFD02B8) ;- (CAN_MB5) MailBox Data High Register\r
+AT91C_CAN_MB5_MID EQU (0xFFFD02A8) ;- (CAN_MB5) MailBox ID Register\r
+AT91C_CAN_MB5_MMR EQU (0xFFFD02A0) ;- (CAN_MB5) MailBox Mode Register\r
+AT91C_CAN_MB5_MDL EQU (0xFFFD02B4) ;- (CAN_MB5) MailBox Data Low Register\r
+AT91C_CAN_MB5_MAM EQU (0xFFFD02A4) ;- (CAN_MB5) MailBox Acceptance Mask Register\r
+// - ========== Register definition for CAN_MB6 peripheral ========== \r
+AT91C_CAN_MB6_MFID EQU (0xFFFD02CC) ;- (CAN_MB6) MailBox Family ID Register\r
+AT91C_CAN_MB6_MID EQU (0xFFFD02C8) ;- (CAN_MB6) MailBox ID Register\r
+AT91C_CAN_MB6_MAM EQU (0xFFFD02C4) ;- (CAN_MB6) MailBox Acceptance Mask Register\r
+AT91C_CAN_MB6_MSR EQU (0xFFFD02D0) ;- (CAN_MB6) MailBox Status Register\r
+AT91C_CAN_MB6_MDL EQU (0xFFFD02D4) ;- (CAN_MB6) MailBox Data Low Register\r
+AT91C_CAN_MB6_MCR EQU (0xFFFD02DC) ;- (CAN_MB6) MailBox Control Register\r
+AT91C_CAN_MB6_MDH EQU (0xFFFD02D8) ;- (CAN_MB6) MailBox Data High Register\r
+AT91C_CAN_MB6_MMR EQU (0xFFFD02C0) ;- (CAN_MB6) MailBox Mode Register\r
+// - ========== Register definition for CAN_MB7 peripheral ========== \r
+AT91C_CAN_MB7_MCR EQU (0xFFFD02FC) ;- (CAN_MB7) MailBox Control Register\r
+AT91C_CAN_MB7_MDH EQU (0xFFFD02F8) ;- (CAN_MB7) MailBox Data High Register\r
+AT91C_CAN_MB7_MFID EQU (0xFFFD02EC) ;- (CAN_MB7) MailBox Family ID Register\r
+AT91C_CAN_MB7_MDL EQU (0xFFFD02F4) ;- (CAN_MB7) MailBox Data Low Register\r
+AT91C_CAN_MB7_MID EQU (0xFFFD02E8) ;- (CAN_MB7) MailBox ID Register\r
+AT91C_CAN_MB7_MMR EQU (0xFFFD02E0) ;- (CAN_MB7) MailBox Mode Register\r
+AT91C_CAN_MB7_MAM EQU (0xFFFD02E4) ;- (CAN_MB7) MailBox Acceptance Mask Register\r
+AT91C_CAN_MB7_MSR EQU (0xFFFD02F0) ;- (CAN_MB7) MailBox Status Register\r
+// - ========== Register definition for CAN peripheral ========== \r
+AT91C_CAN_TCR EQU (0xFFFD0024) ;- (CAN) Transfer Command Register\r
+AT91C_CAN_IMR EQU (0xFFFD000C) ;- (CAN) Interrupt Mask Register\r
+AT91C_CAN_IER EQU (0xFFFD0004) ;- (CAN) Interrupt Enable Register\r
+AT91C_CAN_ECR EQU (0xFFFD0020) ;- (CAN) Error Counter Register\r
+AT91C_CAN_TIMESTP EQU (0xFFFD001C) ;- (CAN) Time Stamp Register\r
+AT91C_CAN_MR EQU (0xFFFD0000) ;- (CAN) Mode Register\r
+AT91C_CAN_IDR EQU (0xFFFD0008) ;- (CAN) Interrupt Disable Register\r
+AT91C_CAN_ACR EQU (0xFFFD0028) ;- (CAN) Abort Command Register\r
+AT91C_CAN_TIM EQU (0xFFFD0018) ;- (CAN) Timer Register\r
+AT91C_CAN_SR EQU (0xFFFD0010) ;- (CAN) Status Register\r
+AT91C_CAN_BR EQU (0xFFFD0014) ;- (CAN) Baudrate Register\r
+AT91C_CAN_VR EQU (0xFFFD00FC) ;- (CAN) Version Register\r
+// - ========== Register definition for EMAC peripheral ========== \r
+AT91C_EMAC_ISR EQU (0xFFFDC024) ;- (EMAC) Interrupt Status Register\r
+AT91C_EMAC_SA4H EQU (0xFFFDC0B4) ;- (EMAC) Specific Address 4 Top, Last 2 bytes\r
+AT91C_EMAC_SA1L EQU (0xFFFDC098) ;- (EMAC) Specific Address 1 Bottom, First 4 bytes\r
+AT91C_EMAC_ELE EQU (0xFFFDC078) ;- (EMAC) Excessive Length Errors Register\r
+AT91C_EMAC_LCOL EQU (0xFFFDC05C) ;- (EMAC) Late Collision Register\r
+AT91C_EMAC_RLE EQU (0xFFFDC088) ;- (EMAC) Receive Length Field Mismatch Register\r
+AT91C_EMAC_WOL EQU (0xFFFDC0C4) ;- (EMAC) Wake On LAN Register\r
+AT91C_EMAC_DTF EQU (0xFFFDC058) ;- (EMAC) Deferred Transmission Frame Register\r
+AT91C_EMAC_TUND EQU (0xFFFDC064) ;- (EMAC) Transmit Underrun Error Register\r
+AT91C_EMAC_NCR EQU (0xFFFDC000) ;- (EMAC) Network Control Register\r
+AT91C_EMAC_SA4L EQU (0xFFFDC0B0) ;- (EMAC) Specific Address 4 Bottom, First 4 bytes\r
+AT91C_EMAC_RSR EQU (0xFFFDC020) ;- (EMAC) Receive Status Register\r
+AT91C_EMAC_SA3L EQU (0xFFFDC0A8) ;- (EMAC) Specific Address 3 Bottom, First 4 bytes\r
+AT91C_EMAC_TSR EQU (0xFFFDC014) ;- (EMAC) Transmit Status Register\r
+AT91C_EMAC_IDR EQU (0xFFFDC02C) ;- (EMAC) Interrupt Disable Register\r
+AT91C_EMAC_RSE EQU (0xFFFDC074) ;- (EMAC) Receive Symbol Errors Register\r
+AT91C_EMAC_ECOL EQU (0xFFFDC060) ;- (EMAC) Excessive Collision Register\r
+AT91C_EMAC_TID EQU (0xFFFDC0B8) ;- (EMAC) Type ID Checking Register\r
+AT91C_EMAC_HRB EQU (0xFFFDC090) ;- (EMAC) Hash Address Bottom[31:0]\r
+AT91C_EMAC_TBQP EQU (0xFFFDC01C) ;- (EMAC) Transmit Buffer Queue Pointer\r
+AT91C_EMAC_USRIO EQU (0xFFFDC0C0) ;- (EMAC) USER Input/Output Register\r
+AT91C_EMAC_PTR EQU (0xFFFDC038) ;- (EMAC) Pause Time Register\r
+AT91C_EMAC_SA2H EQU (0xFFFDC0A4) ;- (EMAC) Specific Address 2 Top, Last 2 bytes\r
+AT91C_EMAC_ROV EQU (0xFFFDC070) ;- (EMAC) Receive Overrun Errors Register\r
+AT91C_EMAC_ALE EQU (0xFFFDC054) ;- (EMAC) Alignment Error Register\r
+AT91C_EMAC_RJA EQU (0xFFFDC07C) ;- (EMAC) Receive Jabbers Register\r
+AT91C_EMAC_RBQP EQU (0xFFFDC018) ;- (EMAC) Receive Buffer Queue Pointer\r
+AT91C_EMAC_TPF EQU (0xFFFDC08C) ;- (EMAC) Transmitted Pause Frames Register\r
+AT91C_EMAC_NCFGR EQU (0xFFFDC004) ;- (EMAC) Network Configuration Register\r
+AT91C_EMAC_HRT EQU (0xFFFDC094) ;- (EMAC) Hash Address Top[63:32]\r
+AT91C_EMAC_USF EQU (0xFFFDC080) ;- (EMAC) Undersize Frames Register\r
+AT91C_EMAC_FCSE EQU (0xFFFDC050) ;- (EMAC) Frame Check Sequence Error Register\r
+AT91C_EMAC_TPQ EQU (0xFFFDC0BC) ;- (EMAC) Transmit Pause Quantum Register\r
+AT91C_EMAC_MAN EQU (0xFFFDC034) ;- (EMAC) PHY Maintenance Register\r
+AT91C_EMAC_FTO EQU (0xFFFDC040) ;- (EMAC) Frames Transmitted OK Register\r
+AT91C_EMAC_REV EQU (0xFFFDC0FC) ;- (EMAC) Revision Register\r
+AT91C_EMAC_IMR EQU (0xFFFDC030) ;- (EMAC) Interrupt Mask Register\r
+AT91C_EMAC_SCF EQU (0xFFFDC044) ;- (EMAC) Single Collision Frame Register\r
+AT91C_EMAC_PFR EQU (0xFFFDC03C) ;- (EMAC) Pause Frames received Register\r
+AT91C_EMAC_MCF EQU (0xFFFDC048) ;- (EMAC) Multiple Collision Frame Register\r
+AT91C_EMAC_NSR EQU (0xFFFDC008) ;- (EMAC) Network Status Register\r
+AT91C_EMAC_SA2L EQU (0xFFFDC0A0) ;- (EMAC) Specific Address 2 Bottom, First 4 bytes\r
+AT91C_EMAC_FRO EQU (0xFFFDC04C) ;- (EMAC) Frames Received OK Register\r
+AT91C_EMAC_IER EQU (0xFFFDC028) ;- (EMAC) Interrupt Enable Register\r
+AT91C_EMAC_SA1H EQU (0xFFFDC09C) ;- (EMAC) Specific Address 1 Top, Last 2 bytes\r
+AT91C_EMAC_CSE EQU (0xFFFDC068) ;- (EMAC) Carrier Sense Error Register\r
+AT91C_EMAC_SA3H EQU (0xFFFDC0AC) ;- (EMAC) Specific Address 3 Top, Last 2 bytes\r
+AT91C_EMAC_RRE EQU (0xFFFDC06C) ;- (EMAC) Receive Ressource Error Register\r
+AT91C_EMAC_STE EQU (0xFFFDC084) ;- (EMAC) SQE Test Error Register\r
+// - ========== Register definition for PDC_ADC peripheral ========== \r
+AT91C_ADC_PTSR EQU (0xFFFD8124) ;- (PDC_ADC) PDC Transfer Status Register\r
+AT91C_ADC_PTCR EQU (0xFFFD8120) ;- (PDC_ADC) PDC Transfer Control Register\r
+AT91C_ADC_TNPR EQU (0xFFFD8118) ;- (PDC_ADC) Transmit Next Pointer Register\r
+AT91C_ADC_TNCR EQU (0xFFFD811C) ;- (PDC_ADC) Transmit Next Counter Register\r
+AT91C_ADC_RNPR EQU (0xFFFD8110) ;- (PDC_ADC) Receive Next Pointer Register\r
+AT91C_ADC_RNCR EQU (0xFFFD8114) ;- (PDC_ADC) Receive Next Counter Register\r
+AT91C_ADC_RPR EQU (0xFFFD8100) ;- (PDC_ADC) Receive Pointer Register\r
+AT91C_ADC_TCR EQU (0xFFFD810C) ;- (PDC_ADC) Transmit Counter Register\r
+AT91C_ADC_TPR EQU (0xFFFD8108) ;- (PDC_ADC) Transmit Pointer Register\r
+AT91C_ADC_RCR EQU (0xFFFD8104) ;- (PDC_ADC) Receive Counter Register\r
+// - ========== Register definition for ADC peripheral ========== \r
+AT91C_ADC_CDR2 EQU (0xFFFD8038) ;- (ADC) ADC Channel Data Register 2\r
+AT91C_ADC_CDR3 EQU (0xFFFD803C) ;- (ADC) ADC Channel Data Register 3\r
+AT91C_ADC_CDR0 EQU (0xFFFD8030) ;- (ADC) ADC Channel Data Register 0\r
+AT91C_ADC_CDR5 EQU (0xFFFD8044) ;- (ADC) ADC Channel Data Register 5\r
+AT91C_ADC_CHDR EQU (0xFFFD8014) ;- (ADC) ADC Channel Disable Register\r
+AT91C_ADC_SR EQU (0xFFFD801C) ;- (ADC) ADC Status Register\r
+AT91C_ADC_CDR4 EQU (0xFFFD8040) ;- (ADC) ADC Channel Data Register 4\r
+AT91C_ADC_CDR1 EQU (0xFFFD8034) ;- (ADC) ADC Channel Data Register 1\r
+AT91C_ADC_LCDR EQU (0xFFFD8020) ;- (ADC) ADC Last Converted Data Register\r
+AT91C_ADC_IDR EQU (0xFFFD8028) ;- (ADC) ADC Interrupt Disable Register\r
+AT91C_ADC_CR EQU (0xFFFD8000) ;- (ADC) ADC Control Register\r
+AT91C_ADC_CDR7 EQU (0xFFFD804C) ;- (ADC) ADC Channel Data Register 7\r
+AT91C_ADC_CDR6 EQU (0xFFFD8048) ;- (ADC) ADC Channel Data Register 6\r
+AT91C_ADC_IER EQU (0xFFFD8024) ;- (ADC) ADC Interrupt Enable Register\r
+AT91C_ADC_CHER EQU (0xFFFD8010) ;- (ADC) ADC Channel Enable Register\r
+AT91C_ADC_CHSR EQU (0xFFFD8018) ;- (ADC) ADC Channel Status Register\r
+AT91C_ADC_MR EQU (0xFFFD8004) ;- (ADC) ADC Mode Register\r
+AT91C_ADC_IMR EQU (0xFFFD802C) ;- (ADC) ADC Interrupt Mask Register\r
+// - ========== Register definition for PDC_AES peripheral ========== \r
+AT91C_AES_TPR EQU (0xFFFA4108) ;- (PDC_AES) Transmit Pointer Register\r
+AT91C_AES_PTCR EQU (0xFFFA4120) ;- (PDC_AES) PDC Transfer Control Register\r
+AT91C_AES_RNPR EQU (0xFFFA4110) ;- (PDC_AES) Receive Next Pointer Register\r
+AT91C_AES_TNCR EQU (0xFFFA411C) ;- (PDC_AES) Transmit Next Counter Register\r
+AT91C_AES_TCR EQU (0xFFFA410C) ;- (PDC_AES) Transmit Counter Register\r
+AT91C_AES_RCR EQU (0xFFFA4104) ;- (PDC_AES) Receive Counter Register\r
+AT91C_AES_RNCR EQU (0xFFFA4114) ;- (PDC_AES) Receive Next Counter Register\r
+AT91C_AES_TNPR EQU (0xFFFA4118) ;- (PDC_AES) Transmit Next Pointer Register\r
+AT91C_AES_RPR EQU (0xFFFA4100) ;- (PDC_AES) Receive Pointer Register\r
+AT91C_AES_PTSR EQU (0xFFFA4124) ;- (PDC_AES) PDC Transfer Status Register\r
+// - ========== Register definition for AES peripheral ========== \r
+AT91C_AES_IVxR EQU (0xFFFA4060) ;- (AES) Initialization Vector x Register\r
+AT91C_AES_MR EQU (0xFFFA4004) ;- (AES) Mode Register\r
+AT91C_AES_VR EQU (0xFFFA40FC) ;- (AES) AES Version Register\r
+AT91C_AES_ODATAxR EQU (0xFFFA4050) ;- (AES) Output Data x Register\r
+AT91C_AES_IDATAxR EQU (0xFFFA4040) ;- (AES) Input Data x Register\r
+AT91C_AES_CR EQU (0xFFFA4000) ;- (AES) Control Register\r
+AT91C_AES_IDR EQU (0xFFFA4014) ;- (AES) Interrupt Disable Register\r
+AT91C_AES_IMR EQU (0xFFFA4018) ;- (AES) Interrupt Mask Register\r
+AT91C_AES_IER EQU (0xFFFA4010) ;- (AES) Interrupt Enable Register\r
+AT91C_AES_KEYWxR EQU (0xFFFA4020) ;- (AES) Key Word x Register\r
+AT91C_AES_ISR EQU (0xFFFA401C) ;- (AES) Interrupt Status Register\r
+// - ========== Register definition for PDC_TDES peripheral ========== \r
+AT91C_TDES_RNCR EQU (0xFFFA8114) ;- (PDC_TDES) Receive Next Counter Register\r
+AT91C_TDES_TCR EQU (0xFFFA810C) ;- (PDC_TDES) Transmit Counter Register\r
+AT91C_TDES_RCR EQU (0xFFFA8104) ;- (PDC_TDES) Receive Counter Register\r
+AT91C_TDES_TNPR EQU (0xFFFA8118) ;- (PDC_TDES) Transmit Next Pointer Register\r
+AT91C_TDES_RNPR EQU (0xFFFA8110) ;- (PDC_TDES) Receive Next Pointer Register\r
+AT91C_TDES_RPR EQU (0xFFFA8100) ;- (PDC_TDES) Receive Pointer Register\r
+AT91C_TDES_TNCR EQU (0xFFFA811C) ;- (PDC_TDES) Transmit Next Counter Register\r
+AT91C_TDES_TPR EQU (0xFFFA8108) ;- (PDC_TDES) Transmit Pointer Register\r
+AT91C_TDES_PTSR EQU (0xFFFA8124) ;- (PDC_TDES) PDC Transfer Status Register\r
+AT91C_TDES_PTCR EQU (0xFFFA8120) ;- (PDC_TDES) PDC Transfer Control Register\r
+// - ========== Register definition for TDES peripheral ========== \r
+AT91C_TDES_KEY2WxR EQU (0xFFFA8028) ;- (TDES) Key 2 Word x Register\r
+AT91C_TDES_KEY3WxR EQU (0xFFFA8030) ;- (TDES) Key 3 Word x Register\r
+AT91C_TDES_IDR EQU (0xFFFA8014) ;- (TDES) Interrupt Disable Register\r
+AT91C_TDES_VR EQU (0xFFFA80FC) ;- (TDES) TDES Version Register\r
+AT91C_TDES_IVxR EQU (0xFFFA8060) ;- (TDES) Initialization Vector x Register\r
+AT91C_TDES_ODATAxR EQU (0xFFFA8050) ;- (TDES) Output Data x Register\r
+AT91C_TDES_IMR EQU (0xFFFA8018) ;- (TDES) Interrupt Mask Register\r
+AT91C_TDES_MR EQU (0xFFFA8004) ;- (TDES) Mode Register\r
+AT91C_TDES_CR EQU (0xFFFA8000) ;- (TDES) Control Register\r
+AT91C_TDES_IER EQU (0xFFFA8010) ;- (TDES) Interrupt Enable Register\r
+AT91C_TDES_ISR EQU (0xFFFA801C) ;- (TDES) Interrupt Status Register\r
+AT91C_TDES_IDATAxR EQU (0xFFFA8040) ;- (TDES) Input Data x Register\r
+AT91C_TDES_KEY1WxR EQU (0xFFFA8020) ;- (TDES) Key 1 Word x Register\r
+\r
+// - *****************************************************************************\r
+// - PIO DEFINITIONS FOR AT91SAM7X256\r
+// - *****************************************************************************\r
+AT91C_PIO_PA0 EQU (1 << 0) ;- Pin Controlled by PA0\r
+AT91C_PA0_RXD0 EQU (AT91C_PIO_PA0) ;- USART 0 Receive Data\r
+AT91C_PIO_PA1 EQU (1 << 1) ;- Pin Controlled by PA1\r
+AT91C_PA1_TXD0 EQU (AT91C_PIO_PA1) ;- USART 0 Transmit Data\r
+AT91C_PIO_PA10 EQU (1 << 10) ;- Pin Controlled by PA10\r
+AT91C_PA10_TWD EQU (AT91C_PIO_PA10) ;- TWI Two-wire Serial Data\r
+AT91C_PIO_PA11 EQU (1 << 11) ;- Pin Controlled by PA11\r
+AT91C_PA11_TWCK EQU (AT91C_PIO_PA11) ;- TWI Two-wire Serial Clock\r
+AT91C_PIO_PA12 EQU (1 << 12) ;- Pin Controlled by PA12\r
+AT91C_PA12_NPCS00 EQU (AT91C_PIO_PA12) ;- SPI 0 Peripheral Chip Select 0\r
+AT91C_PIO_PA13 EQU (1 << 13) ;- Pin Controlled by PA13\r
+AT91C_PA13_NPCS01 EQU (AT91C_PIO_PA13) ;- SPI 0 Peripheral Chip Select 1\r
+AT91C_PA13_PCK1 EQU (AT91C_PIO_PA13) ;- PMC Programmable Clock Output 1\r
+AT91C_PIO_PA14 EQU (1 << 14) ;- Pin Controlled by PA14\r
+AT91C_PA14_NPCS02 EQU (AT91C_PIO_PA14) ;- SPI 0 Peripheral Chip Select 2\r
+AT91C_PA14_IRQ1 EQU (AT91C_PIO_PA14) ;- External Interrupt 1\r
+AT91C_PIO_PA15 EQU (1 << 15) ;- Pin Controlled by PA15\r
+AT91C_PA15_NPCS03 EQU (AT91C_PIO_PA15) ;- SPI 0 Peripheral Chip Select 3\r
+AT91C_PA15_TCLK2 EQU (AT91C_PIO_PA15) ;- Timer Counter 2 external clock input\r
+AT91C_PIO_PA16 EQU (1 << 16) ;- Pin Controlled by PA16\r
+AT91C_PA16_MISO0 EQU (AT91C_PIO_PA16) ;- SPI 0 Master In Slave\r
+AT91C_PIO_PA17 EQU (1 << 17) ;- Pin Controlled by PA17\r
+AT91C_PA17_MOSI0 EQU (AT91C_PIO_PA17) ;- SPI 0 Master Out Slave\r
+AT91C_PIO_PA18 EQU (1 << 18) ;- Pin Controlled by PA18\r
+AT91C_PA18_SPCK0 EQU (AT91C_PIO_PA18) ;- SPI 0 Serial Clock\r
+AT91C_PIO_PA19 EQU (1 << 19) ;- Pin Controlled by PA19\r
+AT91C_PA19_CANRX EQU (AT91C_PIO_PA19) ;- CAN Receive\r
+AT91C_PIO_PA2 EQU (1 << 2) ;- Pin Controlled by PA2\r
+AT91C_PA2_SCK0 EQU (AT91C_PIO_PA2) ;- USART 0 Serial Clock\r
+AT91C_PA2_NPCS11 EQU (AT91C_PIO_PA2) ;- SPI 1 Peripheral Chip Select 1\r
+AT91C_PIO_PA20 EQU (1 << 20) ;- Pin Controlled by PA20\r
+AT91C_PA20_CANTX EQU (AT91C_PIO_PA20) ;- CAN Transmit\r
+AT91C_PIO_PA21 EQU (1 << 21) ;- Pin Controlled by PA21\r
+AT91C_PA21_TF EQU (AT91C_PIO_PA21) ;- SSC Transmit Frame Sync\r
+AT91C_PA21_NPCS10 EQU (AT91C_PIO_PA21) ;- SPI 1 Peripheral Chip Select 0\r
+AT91C_PIO_PA22 EQU (1 << 22) ;- Pin Controlled by PA22\r
+AT91C_PA22_TK EQU (AT91C_PIO_PA22) ;- SSC Transmit Clock\r
+AT91C_PA22_SPCK1 EQU (AT91C_PIO_PA22) ;- SPI 1 Serial Clock\r
+AT91C_PIO_PA23 EQU (1 << 23) ;- Pin Controlled by PA23\r
+AT91C_PA23_TD EQU (AT91C_PIO_PA23) ;- SSC Transmit data\r
+AT91C_PA23_MOSI1 EQU (AT91C_PIO_PA23) ;- SPI 1 Master Out Slave\r
+AT91C_PIO_PA24 EQU (1 << 24) ;- Pin Controlled by PA24\r
+AT91C_PA24_RD EQU (AT91C_PIO_PA24) ;- SSC Receive Data\r
+AT91C_PA24_MISO1 EQU (AT91C_PIO_PA24) ;- SPI 1 Master In Slave\r
+AT91C_PIO_PA25 EQU (1 << 25) ;- Pin Controlled by PA25\r
+AT91C_PA25_RK EQU (AT91C_PIO_PA25) ;- SSC Receive Clock\r
+AT91C_PA25_NPCS11 EQU (AT91C_PIO_PA25) ;- SPI 1 Peripheral Chip Select 1\r
+AT91C_PIO_PA26 EQU (1 << 26) ;- Pin Controlled by PA26\r
+AT91C_PA26_RF EQU (AT91C_PIO_PA26) ;- SSC Receive Frame Sync\r
+AT91C_PA26_NPCS12 EQU (AT91C_PIO_PA26) ;- SPI 1 Peripheral Chip Select 2\r
+AT91C_PIO_PA27 EQU (1 << 27) ;- Pin Controlled by PA27\r
+AT91C_PA27_DRXD EQU (AT91C_PIO_PA27) ;- DBGU Debug Receive Data\r
+AT91C_PA27_PCK3 EQU (AT91C_PIO_PA27) ;- PMC Programmable Clock Output 3\r
+AT91C_PIO_PA28 EQU (1 << 28) ;- Pin Controlled by PA28\r
+AT91C_PA28_DTXD EQU (AT91C_PIO_PA28) ;- DBGU Debug Transmit Data\r
+AT91C_PIO_PA29 EQU (1 << 29) ;- Pin Controlled by PA29\r
+AT91C_PA29_FIQ EQU (AT91C_PIO_PA29) ;- AIC Fast Interrupt Input\r
+AT91C_PA29_NPCS13 EQU (AT91C_PIO_PA29) ;- SPI 1 Peripheral Chip Select 3\r
+AT91C_PIO_PA3 EQU (1 << 3) ;- Pin Controlled by PA3\r
+AT91C_PA3_RTS0 EQU (AT91C_PIO_PA3) ;- USART 0 Ready To Send\r
+AT91C_PA3_NPCS12 EQU (AT91C_PIO_PA3) ;- SPI 1 Peripheral Chip Select 2\r
+AT91C_PIO_PA30 EQU (1 << 30) ;- Pin Controlled by PA30\r
+AT91C_PA30_IRQ0 EQU (AT91C_PIO_PA30) ;- External Interrupt 0\r
+AT91C_PA30_PCK2 EQU (AT91C_PIO_PA30) ;- PMC Programmable Clock Output 2\r
+AT91C_PIO_PA4 EQU (1 << 4) ;- Pin Controlled by PA4\r
+AT91C_PA4_CTS0 EQU (AT91C_PIO_PA4) ;- USART 0 Clear To Send\r
+AT91C_PA4_NPCS13 EQU (AT91C_PIO_PA4) ;- SPI 1 Peripheral Chip Select 3\r
+AT91C_PIO_PA5 EQU (1 << 5) ;- Pin Controlled by PA5\r
+AT91C_PA5_RXD1 EQU (AT91C_PIO_PA5) ;- USART 1 Receive Data\r
+AT91C_PIO_PA6 EQU (1 << 6) ;- Pin Controlled by PA6\r
+AT91C_PA6_TXD1 EQU (AT91C_PIO_PA6) ;- USART 1 Transmit Data\r
+AT91C_PIO_PA7 EQU (1 << 7) ;- Pin Controlled by PA7\r
+AT91C_PA7_SCK1 EQU (AT91C_PIO_PA7) ;- USART 1 Serial Clock\r
+AT91C_PA7_NPCS01 EQU (AT91C_PIO_PA7) ;- SPI 0 Peripheral Chip Select 1\r
+AT91C_PIO_PA8 EQU (1 << 8) ;- Pin Controlled by PA8\r
+AT91C_PA8_RTS1 EQU (AT91C_PIO_PA8) ;- USART 1 Ready To Send\r
+AT91C_PA8_NPCS02 EQU (AT91C_PIO_PA8) ;- SPI 0 Peripheral Chip Select 2\r
+AT91C_PIO_PA9 EQU (1 << 9) ;- Pin Controlled by PA9\r
+AT91C_PA9_CTS1 EQU (AT91C_PIO_PA9) ;- USART 1 Clear To Send\r
+AT91C_PA9_NPCS03 EQU (AT91C_PIO_PA9) ;- SPI 0 Peripheral Chip Select 3\r
+AT91C_PIO_PB0 EQU (1 << 0) ;- Pin Controlled by PB0\r
+AT91C_PB0_ETXCK_EREFCK EQU (AT91C_PIO_PB0) ;- Ethernet MAC Transmit Clock/Reference Clock\r
+AT91C_PB0_PCK0 EQU (AT91C_PIO_PB0) ;- PMC Programmable Clock Output 0\r
+AT91C_PIO_PB1 EQU (1 << 1) ;- Pin Controlled by PB1\r
+AT91C_PB1_ETXEN EQU (AT91C_PIO_PB1) ;- Ethernet MAC Transmit Enable\r
+AT91C_PIO_PB10 EQU (1 << 10) ;- Pin Controlled by PB10\r
+AT91C_PB10_ETX2 EQU (AT91C_PIO_PB10) ;- Ethernet MAC Transmit Data 2\r
+AT91C_PB10_NPCS11 EQU (AT91C_PIO_PB10) ;- SPI 1 Peripheral Chip Select 1\r
+AT91C_PIO_PB11 EQU (1 << 11) ;- Pin Controlled by PB11\r
+AT91C_PB11_ETX3 EQU (AT91C_PIO_PB11) ;- Ethernet MAC Transmit Data 3\r
+AT91C_PB11_NPCS12 EQU (AT91C_PIO_PB11) ;- SPI 1 Peripheral Chip Select 2\r
+AT91C_PIO_PB12 EQU (1 << 12) ;- Pin Controlled by PB12\r
+AT91C_PB12_ETXER EQU (AT91C_PIO_PB12) ;- Ethernet MAC Transmikt Coding Error\r
+AT91C_PB12_TCLK0 EQU (AT91C_PIO_PB12) ;- Timer Counter 0 external clock input\r
+AT91C_PIO_PB13 EQU (1 << 13) ;- Pin Controlled by PB13\r
+AT91C_PB13_ERX2 EQU (AT91C_PIO_PB13) ;- Ethernet MAC Receive Data 2\r
+AT91C_PB13_NPCS01 EQU (AT91C_PIO_PB13) ;- SPI 0 Peripheral Chip Select 1\r
+AT91C_PIO_PB14 EQU (1 << 14) ;- Pin Controlled by PB14\r
+AT91C_PB14_ERX3 EQU (AT91C_PIO_PB14) ;- Ethernet MAC Receive Data 3\r
+AT91C_PB14_NPCS02 EQU (AT91C_PIO_PB14) ;- SPI 0 Peripheral Chip Select 2\r
+AT91C_PIO_PB15 EQU (1 << 15) ;- Pin Controlled by PB15\r
+AT91C_PB15_ERXDV EQU (AT91C_PIO_PB15) ;- Ethernet MAC Receive Data Valid\r
+AT91C_PIO_PB16 EQU (1 << 16) ;- Pin Controlled by PB16\r
+AT91C_PB16_ECOL EQU (AT91C_PIO_PB16) ;- Ethernet MAC Collision Detected\r
+AT91C_PB16_NPCS13 EQU (AT91C_PIO_PB16) ;- SPI 1 Peripheral Chip Select 3\r
+AT91C_PIO_PB17 EQU (1 << 17) ;- Pin Controlled by PB17\r
+AT91C_PB17_ERXCK EQU (AT91C_PIO_PB17) ;- Ethernet MAC Receive Clock\r
+AT91C_PB17_NPCS03 EQU (AT91C_PIO_PB17) ;- SPI 0 Peripheral Chip Select 3\r
+AT91C_PIO_PB18 EQU (1 << 18) ;- Pin Controlled by PB18\r
+AT91C_PB18_EF100 EQU (AT91C_PIO_PB18) ;- Ethernet MAC Force 100 Mbits/sec\r
+AT91C_PB18_ADTRG EQU (AT91C_PIO_PB18) ;- ADC External Trigger\r
+AT91C_PIO_PB19 EQU (1 << 19) ;- Pin Controlled by PB19\r
+AT91C_PB19_PWM0 EQU (AT91C_PIO_PB19) ;- PWM Channel 0\r
+AT91C_PB19_TCLK1 EQU (AT91C_PIO_PB19) ;- Timer Counter 1 external clock input\r
+AT91C_PIO_PB2 EQU (1 << 2) ;- Pin Controlled by PB2\r
+AT91C_PB2_ETX0 EQU (AT91C_PIO_PB2) ;- Ethernet MAC Transmit Data 0\r
+AT91C_PIO_PB20 EQU (1 << 20) ;- Pin Controlled by PB20\r
+AT91C_PB20_PWM1 EQU (AT91C_PIO_PB20) ;- PWM Channel 1\r
+AT91C_PB20_PCK0 EQU (AT91C_PIO_PB20) ;- PMC Programmable Clock Output 0\r
+AT91C_PIO_PB21 EQU (1 << 21) ;- Pin Controlled by PB21\r
+AT91C_PB21_PWM2 EQU (AT91C_PIO_PB21) ;- PWM Channel 2\r
+AT91C_PB21_PCK1 EQU (AT91C_PIO_PB21) ;- PMC Programmable Clock Output 1\r
+AT91C_PIO_PB22 EQU (1 << 22) ;- Pin Controlled by PB22\r
+AT91C_PB22_PWM3 EQU (AT91C_PIO_PB22) ;- PWM Channel 3\r
+AT91C_PB22_PCK2 EQU (AT91C_PIO_PB22) ;- PMC Programmable Clock Output 2\r
+AT91C_PIO_PB23 EQU (1 << 23) ;- Pin Controlled by PB23\r
+AT91C_PB23_TIOA0 EQU (AT91C_PIO_PB23) ;- Timer Counter 0 Multipurpose Timer I/O Pin A\r
+AT91C_PB23_DCD1 EQU (AT91C_PIO_PB23) ;- USART 1 Data Carrier Detect\r
+AT91C_PIO_PB24 EQU (1 << 24) ;- Pin Controlled by PB24\r
+AT91C_PB24_TIOB0 EQU (AT91C_PIO_PB24) ;- Timer Counter 0 Multipurpose Timer I/O Pin B\r
+AT91C_PB24_DSR1 EQU (AT91C_PIO_PB24) ;- USART 1 Data Set ready\r
+AT91C_PIO_PB25 EQU (1 << 25) ;- Pin Controlled by PB25\r
+AT91C_PB25_TIOA1 EQU (AT91C_PIO_PB25) ;- Timer Counter 1 Multipurpose Timer I/O Pin A\r
+AT91C_PB25_DTR1 EQU (AT91C_PIO_PB25) ;- USART 1 Data Terminal ready\r
+AT91C_PIO_PB26 EQU (1 << 26) ;- Pin Controlled by PB26\r
+AT91C_PB26_TIOB1 EQU (AT91C_PIO_PB26) ;- Timer Counter 1 Multipurpose Timer I/O Pin B\r
+AT91C_PB26_RI1 EQU (AT91C_PIO_PB26) ;- USART 1 Ring Indicator\r
+AT91C_PIO_PB27 EQU (1 << 27) ;- Pin Controlled by PB27\r
+AT91C_PB27_TIOA2 EQU (AT91C_PIO_PB27) ;- Timer Counter 2 Multipurpose Timer I/O Pin A\r
+AT91C_PB27_PWM0 EQU (AT91C_PIO_PB27) ;- PWM Channel 0\r
+AT91C_PIO_PB28 EQU (1 << 28) ;- Pin Controlled by PB28\r
+AT91C_PB28_TIOB2 EQU (AT91C_PIO_PB28) ;- Timer Counter 2 Multipurpose Timer I/O Pin B\r
+AT91C_PB28_PWM1 EQU (AT91C_PIO_PB28) ;- PWM Channel 1\r
+AT91C_PIO_PB29 EQU (1 << 29) ;- Pin Controlled by PB29\r
+AT91C_PB29_PCK1 EQU (AT91C_PIO_PB29) ;- PMC Programmable Clock Output 1\r
+AT91C_PB29_PWM2 EQU (AT91C_PIO_PB29) ;- PWM Channel 2\r
+AT91C_PIO_PB3 EQU (1 << 3) ;- Pin Controlled by PB3\r
+AT91C_PB3_ETX1 EQU (AT91C_PIO_PB3) ;- Ethernet MAC Transmit Data 1\r
+AT91C_PIO_PB30 EQU (1 << 30) ;- Pin Controlled by PB30\r
+AT91C_PB30_PCK2 EQU (AT91C_PIO_PB30) ;- PMC Programmable Clock Output 2\r
+AT91C_PB30_PWM3 EQU (AT91C_PIO_PB30) ;- PWM Channel 3\r
+AT91C_PIO_PB4 EQU (1 << 4) ;- Pin Controlled by PB4\r
+AT91C_PB4_ECRS_ECRSDV EQU (AT91C_PIO_PB4) ;- Ethernet MAC Carrier Sense/Carrier Sense and Data Valid\r
+AT91C_PIO_PB5 EQU (1 << 5) ;- Pin Controlled by PB5\r
+AT91C_PB5_ERX0 EQU (AT91C_PIO_PB5) ;- Ethernet MAC Receive Data 0\r
+AT91C_PIO_PB6 EQU (1 << 6) ;- Pin Controlled by PB6\r
+AT91C_PB6_ERX1 EQU (AT91C_PIO_PB6) ;- Ethernet MAC Receive Data 1\r
+AT91C_PIO_PB7 EQU (1 << 7) ;- Pin Controlled by PB7\r
+AT91C_PB7_ERXER EQU (AT91C_PIO_PB7) ;- Ethernet MAC Receive Error\r
+AT91C_PIO_PB8 EQU (1 << 8) ;- Pin Controlled by PB8\r
+AT91C_PB8_EMDC EQU (AT91C_PIO_PB8) ;- Ethernet MAC Management Data Clock\r
+AT91C_PIO_PB9 EQU (1 << 9) ;- Pin Controlled by PB9\r
+AT91C_PB9_EMDIO EQU (AT91C_PIO_PB9) ;- Ethernet MAC Management Data Input/Output\r
+\r
+// - *****************************************************************************\r
+// - PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256\r
+// - *****************************************************************************\r
+AT91C_ID_FIQ EQU ( 0) ;- Advanced Interrupt Controller (FIQ)\r
+AT91C_ID_SYS EQU ( 1) ;- System Peripheral\r
+AT91C_ID_PIOA EQU ( 2) ;- Parallel IO Controller A\r
+AT91C_ID_PIOB EQU ( 3) ;- Parallel IO Controller B\r
+AT91C_ID_SPI0 EQU ( 4) ;- Serial Peripheral Interface 0\r
+AT91C_ID_SPI1 EQU ( 5) ;- Serial Peripheral Interface 1\r
+AT91C_ID_US0 EQU ( 6) ;- USART 0\r
+AT91C_ID_US1 EQU ( 7) ;- USART 1\r
+AT91C_ID_SSC EQU ( 8) ;- Serial Synchronous Controller\r
+AT91C_ID_TWI EQU ( 9) ;- Two-Wire Interface\r
+AT91C_ID_PWMC EQU (10) ;- PWM Controller\r
+AT91C_ID_UDP EQU (11) ;- USB Device Port\r
+AT91C_ID_TC0 EQU (12) ;- Timer Counter 0\r
+AT91C_ID_TC1 EQU (13) ;- Timer Counter 1\r
+AT91C_ID_TC2 EQU (14) ;- Timer Counter 2\r
+AT91C_ID_CAN EQU (15) ;- Control Area Network Controller\r
+AT91C_ID_EMAC EQU (16) ;- Ethernet MAC\r
+AT91C_ID_ADC EQU (17) ;- Analog-to-Digital Converter\r
+AT91C_ID_AES EQU (18) ;- Advanced Encryption Standard 128-bit\r
+AT91C_ID_TDES EQU (19) ;- Triple Data Encryption Standard\r
+AT91C_ID_20_Reserved EQU (20) ;- Reserved\r
+AT91C_ID_21_Reserved EQU (21) ;- Reserved\r
+AT91C_ID_22_Reserved EQU (22) ;- Reserved\r
+AT91C_ID_23_Reserved EQU (23) ;- Reserved\r
+AT91C_ID_24_Reserved EQU (24) ;- Reserved\r
+AT91C_ID_25_Reserved EQU (25) ;- Reserved\r
+AT91C_ID_26_Reserved EQU (26) ;- Reserved\r
+AT91C_ID_27_Reserved EQU (27) ;- Reserved\r
+AT91C_ID_28_Reserved EQU (28) ;- Reserved\r
+AT91C_ID_29_Reserved EQU (29) ;- Reserved\r
+AT91C_ID_IRQ0 EQU (30) ;- Advanced Interrupt Controller (IRQ0)\r
+AT91C_ID_IRQ1 EQU (31) ;- Advanced Interrupt Controller (IRQ1)\r
+\r
+// - *****************************************************************************\r
+// - BASE ADDRESS DEFINITIONS FOR AT91SAM7X256\r
+// - *****************************************************************************\r
+AT91C_BASE_SYS EQU (0xFFFFF000) ;- (SYS) Base Address\r
+AT91C_BASE_AIC EQU (0xFFFFF000) ;- (AIC) Base Address\r
+AT91C_BASE_PDC_DBGU EQU (0xFFFFF300) ;- (PDC_DBGU) Base Address\r
+AT91C_BASE_DBGU EQU (0xFFFFF200) ;- (DBGU) Base Address\r
+AT91C_BASE_PIOA EQU (0xFFFFF400) ;- (PIOA) Base Address\r
+AT91C_BASE_PIOB EQU (0xFFFFF600) ;- (PIOB) Base Address\r
+AT91C_BASE_CKGR EQU (0xFFFFFC20) ;- (CKGR) Base Address\r
+AT91C_BASE_PMC EQU (0xFFFFFC00) ;- (PMC) Base Address\r
+AT91C_BASE_RSTC EQU (0xFFFFFD00) ;- (RSTC) Base Address\r
+AT91C_BASE_RTTC EQU (0xFFFFFD20) ;- (RTTC) Base Address\r
+AT91C_BASE_PITC EQU (0xFFFFFD30) ;- (PITC) Base Address\r
+AT91C_BASE_WDTC EQU (0xFFFFFD40) ;- (WDTC) Base Address\r
+AT91C_BASE_VREG EQU (0xFFFFFD60) ;- (VREG) Base Address\r
+AT91C_BASE_MC EQU (0xFFFFFF00) ;- (MC) Base Address\r
+AT91C_BASE_PDC_SPI1 EQU (0xFFFE4100) ;- (PDC_SPI1) Base Address\r
+AT91C_BASE_SPI1 EQU (0xFFFE4000) ;- (SPI1) Base Address\r
+AT91C_BASE_PDC_SPI0 EQU (0xFFFE0100) ;- (PDC_SPI0) Base Address\r
+AT91C_BASE_SPI0 EQU (0xFFFE0000) ;- (SPI0) Base Address\r
+AT91C_BASE_PDC_US1 EQU (0xFFFC4100) ;- (PDC_US1) Base Address\r
+AT91C_BASE_US1 EQU (0xFFFC4000) ;- (US1) Base Address\r
+AT91C_BASE_PDC_US0 EQU (0xFFFC0100) ;- (PDC_US0) Base Address\r
+AT91C_BASE_US0 EQU (0xFFFC0000) ;- (US0) Base Address\r
+AT91C_BASE_PDC_SSC EQU (0xFFFD4100) ;- (PDC_SSC) Base Address\r
+AT91C_BASE_SSC EQU (0xFFFD4000) ;- (SSC) Base Address\r
+AT91C_BASE_TWI EQU (0xFFFB8000) ;- (TWI) Base Address\r
+AT91C_BASE_PWMC_CH3 EQU (0xFFFCC260) ;- (PWMC_CH3) Base Address\r
+AT91C_BASE_PWMC_CH2 EQU (0xFFFCC240) ;- (PWMC_CH2) Base Address\r
+AT91C_BASE_PWMC_CH1 EQU (0xFFFCC220) ;- (PWMC_CH1) Base Address\r
+AT91C_BASE_PWMC_CH0 EQU (0xFFFCC200) ;- (PWMC_CH0) Base Address\r
+AT91C_BASE_PWMC EQU (0xFFFCC000) ;- (PWMC) Base Address\r
+AT91C_BASE_UDP EQU (0xFFFB0000) ;- (UDP) Base Address\r
+AT91C_BASE_TC0 EQU (0xFFFA0000) ;- (TC0) Base Address\r
+AT91C_BASE_TC1 EQU (0xFFFA0040) ;- (TC1) Base Address\r
+AT91C_BASE_TC2 EQU (0xFFFA0080) ;- (TC2) Base Address\r
+AT91C_BASE_TCB EQU (0xFFFA0000) ;- (TCB) Base Address\r
+AT91C_BASE_CAN_MB0 EQU (0xFFFD0200) ;- (CAN_MB0) Base Address\r
+AT91C_BASE_CAN_MB1 EQU (0xFFFD0220) ;- (CAN_MB1) Base Address\r
+AT91C_BASE_CAN_MB2 EQU (0xFFFD0240) ;- (CAN_MB2) Base Address\r
+AT91C_BASE_CAN_MB3 EQU (0xFFFD0260) ;- (CAN_MB3) Base Address\r
+AT91C_BASE_CAN_MB4 EQU (0xFFFD0280) ;- (CAN_MB4) Base Address\r
+AT91C_BASE_CAN_MB5 EQU (0xFFFD02A0) ;- (CAN_MB5) Base Address\r
+AT91C_BASE_CAN_MB6 EQU (0xFFFD02C0) ;- (CAN_MB6) Base Address\r
+AT91C_BASE_CAN_MB7 EQU (0xFFFD02E0) ;- (CAN_MB7) Base Address\r
+AT91C_BASE_CAN EQU (0xFFFD0000) ;- (CAN) Base Address\r
+AT91C_BASE_EMAC EQU (0xFFFDC000) ;- (EMAC) Base Address\r
+AT91C_BASE_PDC_ADC EQU (0xFFFD8100) ;- (PDC_ADC) Base Address\r
+AT91C_BASE_ADC EQU (0xFFFD8000) ;- (ADC) Base Address\r
+AT91C_BASE_PDC_AES EQU (0xFFFA4100) ;- (PDC_AES) Base Address\r
+AT91C_BASE_AES EQU (0xFFFA4000) ;- (AES) Base Address\r
+AT91C_BASE_PDC_TDES EQU (0xFFFA8100) ;- (PDC_TDES) Base Address\r
+AT91C_BASE_TDES EQU (0xFFFA8000) ;- (TDES) Base Address\r
+\r
+// - *****************************************************************************\r
+// - MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256\r
+// - *****************************************************************************\r
+AT91C_ISRAM EQU (0x00200000) ;- Internal SRAM base address\r
+AT91C_ISRAM_SIZE EQU (0x00010000) ;- Internal SRAM size in byte (64 Kbyte)\r
+AT91C_IFLASH EQU (0x00100000) ;- Internal ROM base address\r
+AT91C_IFLASH_SIZE EQU (0x00040000) ;- Internal ROM size in byte (256 Kbyte)\r
+\r
+\r
+\r
+#endif /* AT91SAM7X256_H */\r
--- /dev/null
+//* ----------------------------------------------------------------------------\r
+//* ATMEL Microcontroller Software Support - ROUSSET -\r
+//* ----------------------------------------------------------------------------\r
+//* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+//* ----------------------------------------------------------------------------\r
+//* File Name : lib_AT91SAM7X256.h\r
+//* Object : AT91SAM7X256 inlined functions\r
+//* Generated : AT91 SW Application Group 05/20/2005 (16:22:29)\r
+//*\r
+//* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003//\r
+//* CVS Reference : /lib_pmc_SAM7X.h/1.1/Tue Feb 1 08:32:10 2005//\r
+//* CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005//\r
+//* CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004//\r
+//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003//\r
+//* CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004//\r
+//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002//\r
+//* CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003//\r
+//* CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004//\r
+//* CVS Reference : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005//\r
+//* CVS Reference : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005//\r
+//* CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004//\r
+//* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003//\r
+//* CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004//\r
+//* CVS Reference : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005//\r
+//* CVS Reference : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005//\r
+//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//\r
+//* CVS Reference : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004//\r
+//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003//\r
+//* CVS Reference : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003//\r
+//* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//\r
+//* CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002//\r
+//* ----------------------------------------------------------------------------\r
+\r
+\r
+#include "AT91SAM7X256.h"\r
+\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AIC_ConfigureIt\r
+//* \brief Interrupt Handler Initialization\r
+//*----------------------------------------------------------------------------\r
+\r
--- /dev/null
+//* ----------------------------------------------------------------------------\r
+//* ATMEL Microcontroller Software Support - ROUSSET -\r
+//* ----------------------------------------------------------------------------\r
+//* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+//* ----------------------------------------------------------------------------\r
+//* File Name : lib_AT91SAM7X256.h\r
+//* Object : AT91SAM7X256 inlined functions\r
+//* Generated : AT91 SW Application Group 05/20/2005 (16:22:29)\r
+//*\r
+//* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003//\r
+//* CVS Reference : /lib_pmc_SAM7X.h/1.1/Tue Feb 1 08:32:10 2005//\r
+//* CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005//\r
+//* CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004//\r
+//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003//\r
+//* CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004//\r
+//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002//\r
+//* CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003//\r
+//* CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004//\r
+//* CVS Reference : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005//\r
+//* CVS Reference : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005//\r
+//* CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004//\r
+//* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003//\r
+//* CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004//\r
+//* CVS Reference : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005//\r
+//* CVS Reference : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005//\r
+//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//\r
+//* CVS Reference : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004//\r
+//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003//\r
+//* CVS Reference : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003//\r
+//* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//\r
+//* CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002//\r
+//* ----------------------------------------------------------------------------\r
+\r
+#ifndef lib_AT91SAM7X256_H\r
+#define lib_AT91SAM7X256_H\r
+\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR AIC\r
+ ***************************************************************************** */\r
+#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20]\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AIC_ConfigureIt\r
+//* \brief Interrupt Handler Initialization\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_AIC_ConfigureIt (\r
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers\r
+ unsigned int irq_id, // \arg interrupt number to initialize\r
+ unsigned int priority, // \arg priority to give to the interrupt\r
+ unsigned int src_type, // \arg activation and sense of activation\r
+ void (*newHandler) (void) ) // \arg address of the interrupt handler\r
+{\r
+ unsigned int oldHandler;\r
+ unsigned int mask ;\r
+\r
+ oldHandler = pAic->AIC_SVR[irq_id];\r
+\r
+ mask = 0x1 << irq_id ;\r
+ //* Disable the interrupt on the interrupt controller\r
+ pAic->AIC_IDCR = mask ;\r
+ //* Save the interrupt handler routine pointer and the interrupt priority\r
+ pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ;\r
+ //* Store the Source Mode Register\r
+ pAic->AIC_SMR[irq_id] = src_type | priority ;\r
+ //* Clear the interrupt on the interrupt controller\r
+ pAic->AIC_ICCR = mask ;\r
+\r
+ return oldHandler;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AIC_EnableIt\r
+//* \brief Enable corresponding IT number\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AIC_EnableIt (\r
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers\r
+ unsigned int irq_id ) // \arg interrupt number to initialize\r
+{\r
+ //* Enable the interrupt on the interrupt controller\r
+ pAic->AIC_IECR = 0x1 << irq_id ;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AIC_DisableIt\r
+//* \brief Disable corresponding IT number\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AIC_DisableIt (\r
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers\r
+ unsigned int irq_id ) // \arg interrupt number to initialize\r
+{\r
+ unsigned int mask = 0x1 << irq_id;\r
+ //* Disable the interrupt on the interrupt controller\r
+ pAic->AIC_IDCR = mask ;\r
+ //* Clear the interrupt on the Interrupt Controller ( if one is pending )\r
+ pAic->AIC_ICCR = mask ;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AIC_ClearIt\r
+//* \brief Clear corresponding IT number\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AIC_ClearIt (\r
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers\r
+ unsigned int irq_id) // \arg interrupt number to initialize\r
+{\r
+ //* Clear the interrupt on the Interrupt Controller ( if one is pending )\r
+ pAic->AIC_ICCR = (0x1 << irq_id);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AIC_AcknowledgeIt\r
+//* \brief Acknowledge corresponding IT number\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AIC_AcknowledgeIt (\r
+ AT91PS_AIC pAic) // \arg pointer to the AIC registers\r
+{\r
+ pAic->AIC_EOICR = pAic->AIC_EOICR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AIC_SetExceptionVector\r
+//* \brief Configure vector handler\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_AIC_SetExceptionVector (\r
+ unsigned int *pVector, // \arg pointer to the AIC registers\r
+ void (*Handler) () ) // \arg Interrupt Handler\r
+{\r
+ unsigned int oldVector = *pVector;\r
+\r
+ if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE)\r
+ *pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE;\r
+ else\r
+ *pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000;\r
+\r
+ return oldVector;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AIC_Trig\r
+//* \brief Trig an IT\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AIC_Trig (\r
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers\r
+ unsigned int irq_id) // \arg interrupt number\r
+{\r
+ pAic->AIC_ISCR = (0x1 << irq_id) ;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AIC_IsActive\r
+//* \brief Test if an IT is active\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_AIC_IsActive (\r
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers\r
+ unsigned int irq_id) // \arg Interrupt Number\r
+{\r
+ return (pAic->AIC_ISR & (0x1 << irq_id));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AIC_IsPending\r
+//* \brief Test if an IT is pending\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_AIC_IsPending (\r
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers\r
+ unsigned int irq_id) // \arg Interrupt Number\r
+{\r
+ return (pAic->AIC_IPR & (0x1 << irq_id));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AIC_Open\r
+//* \brief Set exception vectors and AIC registers to default values\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AIC_Open(\r
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers\r
+ void (*IrqHandler) (), // \arg Default IRQ vector exception\r
+ void (*FiqHandler) (), // \arg Default FIQ vector exception\r
+ void (*DefaultHandler) (), // \arg Default Handler set in ISR\r
+ void (*SpuriousHandler) (), // \arg Default Spurious Handler\r
+ unsigned int protectMode) // \arg Debug Control Register\r
+{\r
+ int i;\r
+\r
+ // Disable all interrupts and set IVR to the default handler\r
+ for (i = 0; i < 32; ++i) {\r
+ AT91F_AIC_DisableIt(pAic, i);\r
+ AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler);\r
+ }\r
+\r
+ // Set the IRQ exception vector\r
+ AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler);\r
+ // Set the Fast Interrupt exception vector\r
+ AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler);\r
+\r
+ pAic->AIC_SPU = (unsigned int) SpuriousHandler;\r
+ pAic->AIC_DCR = protectMode;\r
+}\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR PDC\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_SetNextRx\r
+//* \brief Set the next receive transfer descriptor\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PDC_SetNextRx (\r
+ AT91PS_PDC pPDC, // \arg pointer to a PDC controller\r
+ char *address, // \arg address to the next bloc to be received\r
+ unsigned int bytes) // \arg number of bytes to be received\r
+{\r
+ pPDC->PDC_RNPR = (unsigned int) address;\r
+ pPDC->PDC_RNCR = bytes;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_SetNextTx\r
+//* \brief Set the next transmit transfer descriptor\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PDC_SetNextTx (\r
+ AT91PS_PDC pPDC, // \arg pointer to a PDC controller\r
+ char *address, // \arg address to the next bloc to be transmitted\r
+ unsigned int bytes) // \arg number of bytes to be transmitted\r
+{\r
+ pPDC->PDC_TNPR = (unsigned int) address;\r
+ pPDC->PDC_TNCR = bytes;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_SetRx\r
+//* \brief Set the receive transfer descriptor\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PDC_SetRx (\r
+ AT91PS_PDC pPDC, // \arg pointer to a PDC controller\r
+ char *address, // \arg address to the next bloc to be received\r
+ unsigned int bytes) // \arg number of bytes to be received\r
+{\r
+ pPDC->PDC_RPR = (unsigned int) address;\r
+ pPDC->PDC_RCR = bytes;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_SetTx\r
+//* \brief Set the transmit transfer descriptor\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PDC_SetTx (\r
+ AT91PS_PDC pPDC, // \arg pointer to a PDC controller\r
+ char *address, // \arg address to the next bloc to be transmitted\r
+ unsigned int bytes) // \arg number of bytes to be transmitted\r
+{\r
+ pPDC->PDC_TPR = (unsigned int) address;\r
+ pPDC->PDC_TCR = bytes;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_EnableTx\r
+//* \brief Enable transmit\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PDC_EnableTx (\r
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller\r
+{\r
+ pPDC->PDC_PTCR = AT91C_PDC_TXTEN;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_EnableRx\r
+//* \brief Enable receive\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PDC_EnableRx (\r
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller\r
+{\r
+ pPDC->PDC_PTCR = AT91C_PDC_RXTEN;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_DisableTx\r
+//* \brief Disable transmit\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PDC_DisableTx (\r
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller\r
+{\r
+ pPDC->PDC_PTCR = AT91C_PDC_TXTDIS;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_DisableRx\r
+//* \brief Disable receive\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PDC_DisableRx (\r
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller\r
+{\r
+ pPDC->PDC_PTCR = AT91C_PDC_RXTDIS;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_IsTxEmpty\r
+//* \brief Test if the current transfer descriptor has been sent\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete\r
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller\r
+{\r
+ return !(pPDC->PDC_TCR);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_IsNextTxEmpty\r
+//* \brief Test if the next transfer descriptor has been moved to the current td\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete\r
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller\r
+{\r
+ return !(pPDC->PDC_TNCR);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_IsRxEmpty\r
+//* \brief Test if the current transfer descriptor has been filled\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete\r
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller\r
+{\r
+ return !(pPDC->PDC_RCR);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_IsNextRxEmpty\r
+//* \brief Test if the next transfer descriptor has been moved to the current td\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete\r
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller\r
+{\r
+ return !(pPDC->PDC_RNCR);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_Open\r
+//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PDC_Open (\r
+ AT91PS_PDC pPDC) // \arg pointer to a PDC controller\r
+{\r
+ //* Disable the RX and TX PDC transfer requests\r
+ AT91F_PDC_DisableRx(pPDC);\r
+ AT91F_PDC_DisableTx(pPDC);\r
+\r
+ //* Reset all Counter register Next buffer first\r
+ AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);\r
+ AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);\r
+ AT91F_PDC_SetTx(pPDC, (char *) 0, 0);\r
+ AT91F_PDC_SetRx(pPDC, (char *) 0, 0);\r
+\r
+ //* Enable the RX and TX PDC transfer requests\r
+ AT91F_PDC_EnableRx(pPDC);\r
+ AT91F_PDC_EnableTx(pPDC);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_Close\r
+//* \brief Close PDC: disable TX and RX reset transfer descriptors\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PDC_Close (\r
+ AT91PS_PDC pPDC) // \arg pointer to a PDC controller\r
+{\r
+ //* Disable the RX and TX PDC transfer requests\r
+ AT91F_PDC_DisableRx(pPDC);\r
+ AT91F_PDC_DisableTx(pPDC);\r
+\r
+ //* Reset all Counter register Next buffer first\r
+ AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);\r
+ AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);\r
+ AT91F_PDC_SetTx(pPDC, (char *) 0, 0);\r
+ AT91F_PDC_SetRx(pPDC, (char *) 0, 0);\r
+\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_SendFrame\r
+//* \brief Close PDC: disable TX and RX reset transfer descriptors\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PDC_SendFrame(\r
+ AT91PS_PDC pPDC,\r
+ char *pBuffer,\r
+ unsigned int szBuffer,\r
+ char *pNextBuffer,\r
+ unsigned int szNextBuffer )\r
+{\r
+ if (AT91F_PDC_IsTxEmpty(pPDC)) {\r
+ //* Buffer and next buffer can be initialized\r
+ AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer);\r
+ AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer);\r
+ return 2;\r
+ }\r
+ else if (AT91F_PDC_IsNextTxEmpty(pPDC)) {\r
+ //* Only one buffer can be initialized\r
+ AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer);\r
+ return 1;\r
+ }\r
+ else {\r
+ //* All buffer are in use...\r
+ return 0;\r
+ }\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_ReceiveFrame\r
+//* \brief Close PDC: disable TX and RX reset transfer descriptors\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PDC_ReceiveFrame (\r
+ AT91PS_PDC pPDC,\r
+ char *pBuffer,\r
+ unsigned int szBuffer,\r
+ char *pNextBuffer,\r
+ unsigned int szNextBuffer )\r
+{\r
+ if (AT91F_PDC_IsRxEmpty(pPDC)) {\r
+ //* Buffer and next buffer can be initialized\r
+ AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer);\r
+ AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer);\r
+ return 2;\r
+ }\r
+ else if (AT91F_PDC_IsNextRxEmpty(pPDC)) {\r
+ //* Only one buffer can be initialized\r
+ AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer);\r
+ return 1;\r
+ }\r
+ else {\r
+ //* All buffer are in use...\r
+ return 0;\r
+ }\r
+}\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR DBGU\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_DBGU_InterruptEnable\r
+//* \brief Enable DBGU Interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_DBGU_InterruptEnable(\r
+ AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller\r
+ unsigned int flag) // \arg dbgu interrupt to be enabled\r
+{\r
+ pDbgu->DBGU_IER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_DBGU_InterruptDisable\r
+//* \brief Disable DBGU Interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_DBGU_InterruptDisable(\r
+ AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller\r
+ unsigned int flag) // \arg dbgu interrupt to be disabled\r
+{\r
+ pDbgu->DBGU_IDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_DBGU_GetInterruptMaskStatus\r
+//* \brief Return DBGU Interrupt Mask Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status\r
+ AT91PS_DBGU pDbgu) // \arg pointer to a DBGU controller\r
+{\r
+ return pDbgu->DBGU_IMR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_DBGU_IsInterruptMasked\r
+//* \brief Test if DBGU Interrupt is Masked \r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_DBGU_IsInterruptMasked(\r
+ AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag);\r
+}\r
+\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR PIO\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_CfgPeriph\r
+//* \brief Enable pins to be drived by peripheral\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_CfgPeriph(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int periphAEnable, // \arg PERIPH A to enable\r
+ unsigned int periphBEnable) // \arg PERIPH B to enable\r
+\r
+{\r
+ pPio->PIO_ASR = periphAEnable;\r
+ pPio->PIO_BSR = periphBEnable;\r
+ pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_CfgOutput\r
+//* \brief Enable PIO in output mode\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_CfgOutput(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int pioEnable) // \arg PIO to be enabled\r
+{\r
+ pPio->PIO_PER = pioEnable; // Set in PIO mode\r
+ pPio->PIO_OER = pioEnable; // Configure in Output\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_CfgInput\r
+//* \brief Enable PIO in input mode\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_CfgInput(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int inputEnable) // \arg PIO to be enabled\r
+{\r
+ // Disable output\r
+ pPio->PIO_ODR = inputEnable;\r
+ pPio->PIO_PER = inputEnable;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_CfgOpendrain\r
+//* \brief Configure PIO in open drain\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_CfgOpendrain(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int multiDrvEnable) // \arg pio to be configured in open drain\r
+{\r
+ // Configure the multi-drive option\r
+ pPio->PIO_MDDR = ~multiDrvEnable;\r
+ pPio->PIO_MDER = multiDrvEnable;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_CfgPullup\r
+//* \brief Enable pullup on PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_CfgPullup(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int pullupEnable) // \arg enable pullup on PIO\r
+{\r
+ // Connect or not Pullup\r
+ pPio->PIO_PPUDR = ~pullupEnable;\r
+ pPio->PIO_PPUER = pullupEnable;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_CfgDirectDrive\r
+//* \brief Enable direct drive on PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_CfgDirectDrive(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int directDrive) // \arg PIO to be configured with direct drive\r
+\r
+{\r
+ // Configure the Direct Drive\r
+ pPio->PIO_OWDR = ~directDrive;\r
+ pPio->PIO_OWER = directDrive;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_CfgInputFilter\r
+//* \brief Enable input filter on input PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_CfgInputFilter(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int inputFilter) // \arg PIO to be configured with input filter\r
+\r
+{\r
+ // Configure the Direct Drive\r
+ pPio->PIO_IFDR = ~inputFilter;\r
+ pPio->PIO_IFER = inputFilter;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_GetInput\r
+//* \brief Return PIO input value\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PIO_GetInput( // \return PIO input\r
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller\r
+{\r
+ return pPio->PIO_PDSR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_IsInputSet\r
+//* \brief Test if PIO is input flag is active\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PIO_IsInputSet(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_PIO_GetInput(pPio) & flag);\r
+}\r
+\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_SetOutput\r
+//* \brief Set to 1 output PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_SetOutput(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg output to be set\r
+{\r
+ pPio->PIO_SODR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_ClearOutput\r
+//* \brief Set to 0 output PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_ClearOutput(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg output to be cleared\r
+{\r
+ pPio->PIO_CODR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_ForceOutput\r
+//* \brief Force output when Direct drive option is enabled\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_ForceOutput(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg output to be forced\r
+{\r
+ pPio->PIO_ODSR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_Enable\r
+//* \brief Enable PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_Enable(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg pio to be enabled \r
+{\r
+ pPio->PIO_PER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_Disable\r
+//* \brief Disable PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_Disable(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg pio to be disabled \r
+{\r
+ pPio->PIO_PDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_GetStatus\r
+//* \brief Return PIO Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status\r
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller\r
+{\r
+ return pPio->PIO_PSR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_IsSet\r
+//* \brief Test if PIO is Set\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PIO_IsSet(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_PIO_GetStatus(pPio) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_OutputEnable\r
+//* \brief Output Enable PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_OutputEnable(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg pio output to be enabled\r
+{\r
+ pPio->PIO_OER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_OutputDisable\r
+//* \brief Output Enable PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_OutputDisable(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg pio output to be disabled\r
+{\r
+ pPio->PIO_ODR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_GetOutputStatus\r
+//* \brief Return PIO Output Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status\r
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller\r
+{\r
+ return pPio->PIO_OSR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_IsOuputSet\r
+//* \brief Test if PIO Output is Set\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PIO_IsOutputSet(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_PIO_GetOutputStatus(pPio) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_InputFilterEnable\r
+//* \brief Input Filter Enable PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_InputFilterEnable(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg pio input filter to be enabled\r
+{\r
+ pPio->PIO_IFER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_InputFilterDisable\r
+//* \brief Input Filter Disable PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_InputFilterDisable(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg pio input filter to be disabled\r
+{\r
+ pPio->PIO_IFDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_GetInputFilterStatus\r
+//* \brief Return PIO Input Filter Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status\r
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller\r
+{\r
+ return pPio->PIO_IFSR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_IsInputFilterSet\r
+//* \brief Test if PIO Input filter is Set\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PIO_IsInputFilterSet(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_PIO_GetInputFilterStatus(pPio) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_GetOutputDataStatus\r
+//* \brief Return PIO Output Data Status \r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status \r
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller\r
+{\r
+ return pPio->PIO_ODSR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_InterruptEnable\r
+//* \brief Enable PIO Interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_InterruptEnable(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg pio interrupt to be enabled\r
+{\r
+ pPio->PIO_IER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_InterruptDisable\r
+//* \brief Disable PIO Interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_InterruptDisable(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg pio interrupt to be disabled\r
+{\r
+ pPio->PIO_IDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_GetInterruptMaskStatus\r
+//* \brief Return PIO Interrupt Mask Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status\r
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller\r
+{\r
+ return pPio->PIO_IMR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_GetInterruptStatus\r
+//* \brief Return PIO Interrupt Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status\r
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller\r
+{\r
+ return pPio->PIO_ISR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_IsInterruptMasked\r
+//* \brief Test if PIO Interrupt is Masked \r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PIO_IsInterruptMasked(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_IsInterruptSet\r
+//* \brief Test if PIO Interrupt is Set\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PIO_IsInterruptSet(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_PIO_GetInterruptStatus(pPio) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_MultiDriverEnable\r
+//* \brief Multi Driver Enable PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_MultiDriverEnable(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg pio to be enabled\r
+{\r
+ pPio->PIO_MDER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_MultiDriverDisable\r
+//* \brief Multi Driver Disable PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_MultiDriverDisable(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg pio to be disabled\r
+{\r
+ pPio->PIO_MDDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_GetMultiDriverStatus\r
+//* \brief Return PIO Multi Driver Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status\r
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller\r
+{\r
+ return pPio->PIO_MDSR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_IsMultiDriverSet\r
+//* \brief Test if PIO MultiDriver is Set\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PIO_IsMultiDriverSet(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_A_RegisterSelection\r
+//* \brief PIO A Register Selection \r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_A_RegisterSelection(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg pio A register selection\r
+{\r
+ pPio->PIO_ASR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_B_RegisterSelection\r
+//* \brief PIO B Register Selection \r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_B_RegisterSelection(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg pio B register selection \r
+{\r
+ pPio->PIO_BSR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_Get_AB_RegisterStatus\r
+//* \brief Return PIO Interrupt Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status\r
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller\r
+{\r
+ return pPio->PIO_ABSR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_IsAB_RegisterSet\r
+//* \brief Test if PIO AB Register is Set\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PIO_IsAB_RegisterSet(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_OutputWriteEnable\r
+//* \brief Output Write Enable PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_OutputWriteEnable(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg pio output write to be enabled\r
+{\r
+ pPio->PIO_OWER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_OutputWriteDisable\r
+//* \brief Output Write Disable PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_OutputWriteDisable(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg pio output write to be disabled\r
+{\r
+ pPio->PIO_OWDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_GetOutputWriteStatus\r
+//* \brief Return PIO Output Write Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status\r
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller\r
+{\r
+ return pPio->PIO_OWSR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_IsOutputWriteSet\r
+//* \brief Test if PIO OutputWrite is Set\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PIO_IsOutputWriteSet(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_GetCfgPullup\r
+//* \brief Return PIO Configuration Pullup\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup \r
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller\r
+{\r
+ return pPio->PIO_PPUSR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_IsOutputDataStatusSet\r
+//* \brief Test if PIO Output Data Status is Set \r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PIO_IsOutputDataStatusSet(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_PIO_GetOutputDataStatus(pPio) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_IsCfgPullupStatusSet\r
+//* \brief Test if PIO Configuration Pullup Status is Set\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PIO_IsCfgPullupStatusSet(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (~AT91F_PIO_GetCfgPullup(pPio) & flag);\r
+}\r
+\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR PMC\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_CfgSysClkEnableReg\r
+//* \brief Configure the System Clock Enable Register of the PMC controller\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PMC_CfgSysClkEnableReg (\r
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller\r
+ unsigned int mode)\r
+{\r
+ //* Write to the SCER register\r
+ pPMC->PMC_SCER = mode;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_CfgSysClkDisableReg\r
+//* \brief Configure the System Clock Disable Register of the PMC controller\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PMC_CfgSysClkDisableReg (\r
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller\r
+ unsigned int mode)\r
+{\r
+ //* Write to the SCDR register\r
+ pPMC->PMC_SCDR = mode;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_GetSysClkStatusReg\r
+//* \brief Return the System Clock Status Register of the PMC controller\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PMC_GetSysClkStatusReg (\r
+ AT91PS_PMC pPMC // pointer to a CAN controller\r
+ )\r
+{\r
+ return pPMC->PMC_SCSR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_EnablePeriphClock\r
+//* \brief Enable peripheral clock\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PMC_EnablePeriphClock (\r
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller\r
+ unsigned int periphIds) // \arg IDs of peripherals to enable\r
+{\r
+ pPMC->PMC_PCER = periphIds;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_DisablePeriphClock\r
+//* \brief Disable peripheral clock\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PMC_DisablePeriphClock (\r
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller\r
+ unsigned int periphIds) // \arg IDs of peripherals to enable\r
+{\r
+ pPMC->PMC_PCDR = periphIds;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_GetPeriphClock\r
+//* \brief Get peripheral clock status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PMC_GetPeriphClock (\r
+ AT91PS_PMC pPMC) // \arg pointer to PMC controller\r
+{\r
+ return pPMC->PMC_PCSR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CKGR_CfgMainOscillatorReg\r
+//* \brief Cfg the main oscillator\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CKGR_CfgMainOscillatorReg (\r
+ AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller\r
+ unsigned int mode)\r
+{\r
+ pCKGR->CKGR_MOR = mode;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CKGR_GetMainOscillatorReg\r
+//* \brief Cfg the main oscillator\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CKGR_GetMainOscillatorReg (\r
+ AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller\r
+{\r
+ return pCKGR->CKGR_MOR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CKGR_EnableMainOscillator\r
+//* \brief Enable the main oscillator\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CKGR_EnableMainOscillator(\r
+ AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller\r
+{\r
+ pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CKGR_DisableMainOscillator\r
+//* \brief Disable the main oscillator\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CKGR_DisableMainOscillator (\r
+ AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller\r
+{\r
+ pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CKGR_CfgMainOscStartUpTime\r
+//* \brief Cfg MOR Register according to the main osc startup time\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CKGR_CfgMainOscStartUpTime (\r
+ AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller\r
+ unsigned int startup_time, // \arg main osc startup time in microsecond (us)\r
+ unsigned int slowClock) // \arg slowClock in Hz\r
+{\r
+ pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT;\r
+ pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CKGR_GetMainClockFreqReg\r
+//* \brief Cfg the main oscillator\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CKGR_GetMainClockFreqReg (\r
+ AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller\r
+{\r
+ return pCKGR->CKGR_MCFR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CKGR_GetMainClock\r
+//* \brief Return Main clock in Hz\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CKGR_GetMainClock (\r
+ AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller\r
+ unsigned int slowClock) // \arg slowClock in Hz\r
+{\r
+ return ((pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF) * slowClock) >> 4;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_CfgMCKReg\r
+//* \brief Cfg Master Clock Register\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PMC_CfgMCKReg (\r
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller\r
+ unsigned int mode)\r
+{\r
+ pPMC->PMC_MCKR = mode;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_GetMCKReg\r
+//* \brief Return Master Clock Register\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PMC_GetMCKReg(\r
+ AT91PS_PMC pPMC) // \arg pointer to PMC controller\r
+{\r
+ return pPMC->PMC_MCKR;\r
+}\r
+\r
+//*------------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_GetMasterClock\r
+//* \brief Return master clock in Hz which correponds to processor clock for ARM7\r
+//*------------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PMC_GetMasterClock (\r
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller\r
+ AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller\r
+ unsigned int slowClock) // \arg slowClock in Hz\r
+{\r
+ unsigned int reg = pPMC->PMC_MCKR;\r
+ unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2));\r
+ unsigned int pllDivider, pllMultiplier;\r
+\r
+ switch (reg & AT91C_PMC_CSS) {\r
+ case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected\r
+ return slowClock / prescaler;\r
+ case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected\r
+ return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler;\r
+ case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected\r
+ reg = pCKGR->CKGR_PLLR;\r
+ pllDivider = (reg & AT91C_CKGR_DIV);\r
+ pllMultiplier = ((reg & AT91C_CKGR_MUL) >> 16) + 1;\r
+ return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler;\r
+ }\r
+ return 0;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_EnablePCK\r
+//* \brief Enable peripheral clock\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PMC_EnablePCK (\r
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller\r
+ unsigned int pck, // \arg Peripheral clock identifier 0 .. 7\r
+ unsigned int mode)\r
+{\r
+ pPMC->PMC_PCKR[pck] = mode;\r
+ pPMC->PMC_SCER = (1 << pck) << 8;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_DisablePCK\r
+//* \brief Enable peripheral clock\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PMC_DisablePCK (\r
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller\r
+ unsigned int pck) // \arg Peripheral clock identifier 0 .. 7\r
+{\r
+ pPMC->PMC_SCDR = (1 << pck) << 8;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_EnableIt\r
+//* \brief Enable PMC interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PMC_EnableIt (\r
+ AT91PS_PMC pPMC, // pointer to a PMC controller\r
+ unsigned int flag) // IT to be enabled\r
+{\r
+ //* Write to the IER register\r
+ pPMC->PMC_IER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_DisableIt\r
+//* \brief Disable PMC interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PMC_DisableIt (\r
+ AT91PS_PMC pPMC, // pointer to a PMC controller\r
+ unsigned int flag) // IT to be disabled\r
+{\r
+ //* Write to the IDR register\r
+ pPMC->PMC_IDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_GetStatus\r
+//* \brief Return PMC Interrupt Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status\r
+ AT91PS_PMC pPMC) // pointer to a PMC controller\r
+{\r
+ return pPMC->PMC_SR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_GetInterruptMaskStatus\r
+//* \brief Return PMC Interrupt Mask Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status\r
+ AT91PS_PMC pPMC) // pointer to a PMC controller\r
+{\r
+ return pPMC->PMC_IMR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_IsInterruptMasked\r
+//* \brief Test if PMC Interrupt is Masked\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PMC_IsInterruptMasked(\r
+ AT91PS_PMC pPMC, // \arg pointer to a PMC controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_IsStatusSet\r
+//* \brief Test if PMC Status is Set\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PMC_IsStatusSet(\r
+ AT91PS_PMC pPMC, // \arg pointer to a PMC controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_PMC_GetStatus(pPMC) & flag);\r
+}/* *****************************************************************************\r
+ SOFTWARE API FOR RSTC\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_RSTSoftReset\r
+//* \brief Start Software Reset\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_RSTSoftReset(\r
+ AT91PS_RSTC pRSTC,\r
+ unsigned int reset)\r
+{\r
+ pRSTC->RSTC_RCR = (0xA5000000 | reset);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_RSTSetMode\r
+//* \brief Set Reset Mode\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_RSTSetMode(\r
+ AT91PS_RSTC pRSTC,\r
+ unsigned int mode)\r
+{\r
+ pRSTC->RSTC_RMR = (0xA5000000 | mode);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_RSTGetMode\r
+//* \brief Get Reset Mode\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_RSTGetMode(\r
+ AT91PS_RSTC pRSTC)\r
+{\r
+ return (pRSTC->RSTC_RMR);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_RSTGetStatus\r
+//* \brief Get Reset Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_RSTGetStatus(\r
+ AT91PS_RSTC pRSTC)\r
+{\r
+ return (pRSTC->RSTC_RSR);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_RSTIsSoftRstActive\r
+//* \brief Return !=0 if software reset is still not completed\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_RSTIsSoftRstActive(\r
+ AT91PS_RSTC pRSTC)\r
+{\r
+ return ((pRSTC->RSTC_RSR) & AT91C_RSTC_SRCMP);\r
+}\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR RTTC\r
+ ***************************************************************************** */\r
+//*--------------------------------------------------------------------------------------\r
+//* \fn AT91F_SetRTT_TimeBase()\r
+//* \brief Set the RTT prescaler according to the TimeBase in ms\r
+//*--------------------------------------------------------------------------------------\r
+__inline unsigned int AT91F_RTTSetTimeBase(\r
+ AT91PS_RTTC pRTTC, \r
+ unsigned int ms)\r
+{\r
+ if (ms > 2000)\r
+ return 1; // AT91C_TIME_OUT_OF_RANGE\r
+ pRTTC->RTTC_RTMR &= ~0xFFFF; \r
+ pRTTC->RTTC_RTMR |= (((ms << 15) /1000) & 0xFFFF); \r
+ return 0;\r
+}\r
+\r
+//*--------------------------------------------------------------------------------------\r
+//* \fn AT91F_RTTSetPrescaler()\r
+//* \brief Set the new prescaler value\r
+//*--------------------------------------------------------------------------------------\r
+__inline unsigned int AT91F_RTTSetPrescaler(\r
+ AT91PS_RTTC pRTTC, \r
+ unsigned int rtpres)\r
+{\r
+ pRTTC->RTTC_RTMR &= ~0xFFFF; \r
+ pRTTC->RTTC_RTMR |= (rtpres & 0xFFFF); \r
+ return (pRTTC->RTTC_RTMR);\r
+}\r
+\r
+//*--------------------------------------------------------------------------------------\r
+//* \fn AT91F_RTTRestart()\r
+//* \brief Restart the RTT prescaler\r
+//*--------------------------------------------------------------------------------------\r
+__inline void AT91F_RTTRestart(\r
+ AT91PS_RTTC pRTTC)\r
+{\r
+ pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST; \r
+}\r
+\r
+\r
+//*--------------------------------------------------------------------------------------\r
+//* \fn AT91F_RTT_SetAlarmINT()\r
+//* \brief Enable RTT Alarm Interrupt\r
+//*--------------------------------------------------------------------------------------\r
+__inline void AT91F_RTTSetAlarmINT(\r
+ AT91PS_RTTC pRTTC)\r
+{\r
+ pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN;\r
+}\r
+\r
+//*--------------------------------------------------------------------------------------\r
+//* \fn AT91F_RTT_ClearAlarmINT()\r
+//* \brief Disable RTT Alarm Interrupt\r
+//*--------------------------------------------------------------------------------------\r
+__inline void AT91F_RTTClearAlarmINT(\r
+ AT91PS_RTTC pRTTC)\r
+{\r
+ pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN;\r
+}\r
+\r
+//*--------------------------------------------------------------------------------------\r
+//* \fn AT91F_RTT_SetRttIncINT()\r
+//* \brief Enable RTT INC Interrupt\r
+//*--------------------------------------------------------------------------------------\r
+__inline void AT91F_RTTSetRttIncINT(\r
+ AT91PS_RTTC pRTTC)\r
+{\r
+ pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN;\r
+}\r
+\r
+//*--------------------------------------------------------------------------------------\r
+//* \fn AT91F_RTT_ClearRttIncINT()\r
+//* \brief Disable RTT INC Interrupt\r
+//*--------------------------------------------------------------------------------------\r
+__inline void AT91F_RTTClearRttIncINT(\r
+ AT91PS_RTTC pRTTC)\r
+{\r
+ pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN;\r
+}\r
+\r
+//*--------------------------------------------------------------------------------------\r
+//* \fn AT91F_RTT_SetAlarmValue()\r
+//* \brief Set RTT Alarm Value\r
+//*--------------------------------------------------------------------------------------\r
+__inline void AT91F_RTTSetAlarmValue(\r
+ AT91PS_RTTC pRTTC, unsigned int alarm)\r
+{\r
+ pRTTC->RTTC_RTAR = alarm;\r
+}\r
+\r
+//*--------------------------------------------------------------------------------------\r
+//* \fn AT91F_RTT_GetAlarmValue()\r
+//* \brief Get RTT Alarm Value\r
+//*--------------------------------------------------------------------------------------\r
+__inline unsigned int AT91F_RTTGetAlarmValue(\r
+ AT91PS_RTTC pRTTC)\r
+{\r
+ return(pRTTC->RTTC_RTAR);\r
+}\r
+\r
+//*--------------------------------------------------------------------------------------\r
+//* \fn AT91F_RTTGetStatus()\r
+//* \brief Read the RTT status\r
+//*--------------------------------------------------------------------------------------\r
+__inline unsigned int AT91F_RTTGetStatus(\r
+ AT91PS_RTTC pRTTC)\r
+{\r
+ return(pRTTC->RTTC_RTSR);\r
+}\r
+\r
+//*--------------------------------------------------------------------------------------\r
+//* \fn AT91F_RTT_ReadValue()\r
+//* \brief Read the RTT value\r
+//*--------------------------------------------------------------------------------------\r
+__inline unsigned int AT91F_RTTReadValue(\r
+ AT91PS_RTTC pRTTC)\r
+{\r
+ register volatile unsigned int val1,val2;\r
+ do\r
+ {\r
+ val1 = pRTTC->RTTC_RTVR;\r
+ val2 = pRTTC->RTTC_RTVR;\r
+ } \r
+ while(val1 != val2);\r
+ return(val1);\r
+}\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR PITC\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PITInit\r
+//* \brief System timer init : period in µsecond, system clock freq in MHz\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PITInit(\r
+ AT91PS_PITC pPITC,\r
+ unsigned int period,\r
+ unsigned int pit_frequency)\r
+{\r
+ pPITC->PITC_PIMR = period? (period * pit_frequency + 8) >> 4 : 0; // +8 to avoid %10 and /10\r
+ pPITC->PITC_PIMR |= AT91C_PITC_PITEN; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PITSetPIV\r
+//* \brief Set the PIT Periodic Interval Value \r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PITSetPIV(\r
+ AT91PS_PITC pPITC,\r
+ unsigned int piv)\r
+{\r
+ pPITC->PITC_PIMR = piv | (pPITC->PITC_PIMR & (AT91C_PITC_PITEN | AT91C_PITC_PITIEN));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PITEnableInt\r
+//* \brief Enable PIT periodic interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PITEnableInt(\r
+ AT91PS_PITC pPITC)\r
+{\r
+ pPITC->PITC_PIMR |= AT91C_PITC_PITIEN; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PITDisableInt\r
+//* \brief Disable PIT periodic interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PITDisableInt(\r
+ AT91PS_PITC pPITC)\r
+{\r
+ pPITC->PITC_PIMR &= ~AT91C_PITC_PITIEN; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PITGetMode\r
+//* \brief Read PIT mode register\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PITGetMode(\r
+ AT91PS_PITC pPITC)\r
+{\r
+ return(pPITC->PITC_PIMR);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PITGetStatus\r
+//* \brief Read PIT status register\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PITGetStatus(\r
+ AT91PS_PITC pPITC)\r
+{\r
+ return(pPITC->PITC_PISR);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PITGetPIIR\r
+//* \brief Read PIT CPIV and PICNT without ressetting the counters\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PITGetPIIR(\r
+ AT91PS_PITC pPITC)\r
+{\r
+ return(pPITC->PITC_PIIR);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PITGetPIVR\r
+//* \brief Read System timer CPIV and PICNT without ressetting the counters\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PITGetPIVR(\r
+ AT91PS_PITC pPITC)\r
+{\r
+ return(pPITC->PITC_PIVR);\r
+}\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR WDTC\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_WDTSetMode\r
+//* \brief Set Watchdog Mode Register\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_WDTSetMode(\r
+ AT91PS_WDTC pWDTC,\r
+ unsigned int Mode)\r
+{\r
+ pWDTC->WDTC_WDMR = Mode;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_WDTRestart\r
+//* \brief Restart Watchdog\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_WDTRestart(\r
+ AT91PS_WDTC pWDTC)\r
+{\r
+ pWDTC->WDTC_WDCR = 0xA5000001;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_WDTSGettatus\r
+//* \brief Get Watchdog Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_WDTSGettatus(\r
+ AT91PS_WDTC pWDTC)\r
+{\r
+ return(pWDTC->WDTC_WDSR & 0x3);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_WDTGetPeriod\r
+//* \brief Translate ms into Watchdog Compatible value\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_WDTGetPeriod(unsigned int ms)\r
+{\r
+ if ((ms < 4) || (ms > 16000))\r
+ return 0;\r
+ return((ms << 8) / 1000);\r
+}\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR VREG\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_VREG_Enable_LowPowerMode\r
+//* \brief Enable VREG Low Power Mode\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_VREG_Enable_LowPowerMode(\r
+ AT91PS_VREG pVREG)\r
+{\r
+ pVREG->VREG_MR |= AT91C_VREG_PSTDBY; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_VREG_Disable_LowPowerMode\r
+//* \brief Disable VREG Low Power Mode\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_VREG_Disable_LowPowerMode(\r
+ AT91PS_VREG pVREG)\r
+{\r
+ pVREG->VREG_MR &= ~AT91C_VREG_PSTDBY; \r
+}/* *****************************************************************************\r
+ SOFTWARE API FOR MC\r
+ ***************************************************************************** */\r
+\r
+#define AT91C_MC_CORRECT_KEY ((unsigned int) 0x5A << 24) // (MC) Correct Protect Key\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_MC_Remap\r
+//* \brief Make Remap\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_MC_Remap (void) // \r
+{\r
+ AT91PS_MC pMC = (AT91PS_MC) AT91C_BASE_MC;\r
+ \r
+ pMC->MC_RCR = AT91C_MC_RCB;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_MC_EFC_CfgModeReg\r
+//* \brief Configure the EFC Mode Register of the MC controller\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_MC_EFC_CfgModeReg (\r
+ AT91PS_MC pMC, // pointer to a MC controller\r
+ unsigned int mode) // mode register \r
+{\r
+ // Write to the FMR register\r
+ pMC->MC_FMR = mode;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_MC_EFC_GetModeReg\r
+//* \brief Return MC EFC Mode Regsiter\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_MC_EFC_GetModeReg(\r
+ AT91PS_MC pMC) // pointer to a MC controller\r
+{\r
+ return pMC->MC_FMR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_MC_EFC_ComputeFMCN\r
+//* \brief Return MC EFC Mode Regsiter\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_MC_EFC_ComputeFMCN(\r
+ int master_clock) // master clock in Hz\r
+{\r
+ return (master_clock/1000000 +2);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_MC_EFC_PerformCmd\r
+//* \brief Perform EFC Command\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_MC_EFC_PerformCmd (\r
+ AT91PS_MC pMC, // pointer to a MC controller\r
+ unsigned int transfer_cmd)\r
+{\r
+ pMC->MC_FCR = transfer_cmd; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_MC_EFC_GetStatus\r
+//* \brief Return MC EFC Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_MC_EFC_GetStatus(\r
+ AT91PS_MC pMC) // pointer to a MC controller\r
+{\r
+ return pMC->MC_FSR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_MC_EFC_IsInterruptMasked\r
+//* \brief Test if EFC MC Interrupt is Masked \r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_MC_EFC_IsInterruptMasked(\r
+ AT91PS_MC pMC, // \arg pointer to a MC controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_MC_EFC_GetModeReg(pMC) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_MC_EFC_IsInterruptSet\r
+//* \brief Test if EFC MC Interrupt is Set\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_MC_EFC_IsInterruptSet(\r
+ AT91PS_MC pMC, // \arg pointer to a MC controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_MC_EFC_GetStatus(pMC) & flag);\r
+}\r
+\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR SPI\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_Open\r
+//* \brief Open a SPI Port\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_SPI_Open (\r
+ const unsigned int null) // \arg\r
+{\r
+ /* NOT DEFINED AT THIS MOMENT */\r
+ return ( 0 );\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_CfgCs\r
+//* \brief Configure SPI chip select register\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SPI_CfgCs (\r
+ AT91PS_SPI pSPI, // pointer to a SPI controller\r
+ int cs, // SPI cs number (0 to 3)\r
+ int val) // chip select register\r
+{\r
+ //* Write to the CSR register\r
+ *(pSPI->SPI_CSR + cs) = val;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_EnableIt\r
+//* \brief Enable SPI interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SPI_EnableIt (\r
+ AT91PS_SPI pSPI, // pointer to a SPI controller\r
+ unsigned int flag) // IT to be enabled\r
+{\r
+ //* Write to the IER register\r
+ pSPI->SPI_IER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_DisableIt\r
+//* \brief Disable SPI interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SPI_DisableIt (\r
+ AT91PS_SPI pSPI, // pointer to a SPI controller\r
+ unsigned int flag) // IT to be disabled\r
+{\r
+ //* Write to the IDR register\r
+ pSPI->SPI_IDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_Reset\r
+//* \brief Reset the SPI controller\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SPI_Reset (\r
+ AT91PS_SPI pSPI // pointer to a SPI controller\r
+ )\r
+{\r
+ //* Write to the CR register\r
+ pSPI->SPI_CR = AT91C_SPI_SWRST;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_Enable\r
+//* \brief Enable the SPI controller\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SPI_Enable (\r
+ AT91PS_SPI pSPI // pointer to a SPI controller\r
+ )\r
+{\r
+ //* Write to the CR register\r
+ pSPI->SPI_CR = AT91C_SPI_SPIEN;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_Disable\r
+//* \brief Disable the SPI controller\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SPI_Disable (\r
+ AT91PS_SPI pSPI // pointer to a SPI controller\r
+ )\r
+{\r
+ //* Write to the CR register\r
+ pSPI->SPI_CR = AT91C_SPI_SPIDIS;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_CfgMode\r
+//* \brief Enable the SPI controller\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SPI_CfgMode (\r
+ AT91PS_SPI pSPI, // pointer to a SPI controller\r
+ int mode) // mode register \r
+{\r
+ //* Write to the MR register\r
+ pSPI->SPI_MR = mode;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_CfgPCS\r
+//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SPI_CfgPCS (\r
+ AT91PS_SPI pSPI, // pointer to a SPI controller\r
+ char PCS_Device) // PCS of the Device\r
+{ \r
+ //* Write to the MR register\r
+ pSPI->SPI_MR &= 0xFFF0FFFF;\r
+ pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS );\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_ReceiveFrame\r
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_SPI_ReceiveFrame (\r
+ AT91PS_SPI pSPI,\r
+ char *pBuffer,\r
+ unsigned int szBuffer,\r
+ char *pNextBuffer,\r
+ unsigned int szNextBuffer )\r
+{\r
+ return AT91F_PDC_ReceiveFrame(\r
+ (AT91PS_PDC) &(pSPI->SPI_RPR),\r
+ pBuffer,\r
+ szBuffer,\r
+ pNextBuffer,\r
+ szNextBuffer);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_SendFrame\r
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_SPI_SendFrame(\r
+ AT91PS_SPI pSPI,\r
+ char *pBuffer,\r
+ unsigned int szBuffer,\r
+ char *pNextBuffer,\r
+ unsigned int szNextBuffer )\r
+{\r
+ return AT91F_PDC_SendFrame(\r
+ (AT91PS_PDC) &(pSPI->SPI_RPR),\r
+ pBuffer,\r
+ szBuffer,\r
+ pNextBuffer,\r
+ szNextBuffer);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_Close\r
+//* \brief Close SPI: disable IT disable transfert, close PDC\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SPI_Close (\r
+ AT91PS_SPI pSPI) // \arg pointer to a SPI controller\r
+{\r
+ //* Reset all the Chip Select register\r
+ pSPI->SPI_CSR[0] = 0 ;\r
+ pSPI->SPI_CSR[1] = 0 ;\r
+ pSPI->SPI_CSR[2] = 0 ;\r
+ pSPI->SPI_CSR[3] = 0 ;\r
+\r
+ //* Reset the SPI mode\r
+ pSPI->SPI_MR = 0 ;\r
+\r
+ //* Disable all interrupts\r
+ pSPI->SPI_IDR = 0xFFFFFFFF ;\r
+\r
+ //* Abort the Peripheral Data Transfers\r
+ AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR));\r
+\r
+ //* Disable receiver and transmitter and stop any activity immediately\r
+ pSPI->SPI_CR = AT91C_SPI_SPIDIS;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_PutChar\r
+//* \brief Send a character,does not check if ready to send\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SPI_PutChar (\r
+ AT91PS_SPI pSPI,\r
+ unsigned int character,\r
+ unsigned int cs_number )\r
+{\r
+ unsigned int value_for_cs;\r
+ value_for_cs = (~(1 << cs_number)) & 0xF; //Place a zero among a 4 ONEs number\r
+ pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_GetChar\r
+//* \brief Receive a character,does not check if a character is available\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_SPI_GetChar (\r
+ const AT91PS_SPI pSPI)\r
+{\r
+ return((pSPI->SPI_RDR) & 0xFFFF);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_GetInterruptMaskStatus\r
+//* \brief Return SPI Interrupt Mask Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status\r
+ AT91PS_SPI pSpi) // \arg pointer to a SPI controller\r
+{\r
+ return pSpi->SPI_IMR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_IsInterruptMasked\r
+//* \brief Test if SPI Interrupt is Masked \r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_SPI_IsInterruptMasked(\r
+ AT91PS_SPI pSpi, // \arg pointer to a SPI controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag);\r
+}\r
+\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR USART\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_Baudrate\r
+//* \brief Calculate the baudrate\r
+//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity\r
+#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \\r
+ AT91C_US_NBSTOP_1_BIT + \\r
+ AT91C_US_PAR_NONE + \\r
+ AT91C_US_CHRL_8_BITS + \\r
+ AT91C_US_CLKS_CLOCK )\r
+\r
+//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity\r
+#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \\r
+ AT91C_US_NBSTOP_1_BIT + \\r
+ AT91C_US_PAR_NONE + \\r
+ AT91C_US_CHRL_8_BITS + \\r
+ AT91C_US_CLKS_EXT )\r
+\r
+//* Standard Synchronous Mode : 8 bits , 1 stop , no parity\r
+#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \\r
+ AT91C_US_USMODE_NORMAL + \\r
+ AT91C_US_NBSTOP_1_BIT + \\r
+ AT91C_US_PAR_NONE + \\r
+ AT91C_US_CHRL_8_BITS + \\r
+ AT91C_US_CLKS_CLOCK )\r
+\r
+//* SCK used Label\r
+#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT)\r
+\r
+//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity\r
+#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \\r
+ AT91C_US_CLKS_CLOCK +\\r
+ AT91C_US_NBSTOP_1_BIT + \\r
+ AT91C_US_PAR_EVEN + \\r
+ AT91C_US_CHRL_8_BITS + \\r
+ AT91C_US_CKLO +\\r
+ AT91C_US_OVER)\r
+\r
+//* Standard IRDA mode\r
+#define AT91C_US_ASYNC_IRDA_MODE ( AT91C_US_USMODE_IRDA + \\r
+ AT91C_US_NBSTOP_1_BIT + \\r
+ AT91C_US_PAR_NONE + \\r
+ AT91C_US_CHRL_8_BITS + \\r
+ AT91C_US_CLKS_CLOCK )\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_Baudrate\r
+//* \brief Caluculate baud_value according to the main clock and the baud rate\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_US_Baudrate (\r
+ const unsigned int main_clock, // \arg peripheral clock\r
+ const unsigned int baud_rate) // \arg UART baudrate\r
+{\r
+ unsigned int baud_value = ((main_clock*10)/(baud_rate * 16));\r
+ if ((baud_value % 10) >= 5)\r
+ baud_value = (baud_value / 10) + 1;\r
+ else\r
+ baud_value /= 10;\r
+ return baud_value;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_SetBaudrate\r
+//* \brief Set the baudrate according to the CPU clock\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US_SetBaudrate (\r
+ AT91PS_USART pUSART, // \arg pointer to a USART controller\r
+ unsigned int mainClock, // \arg peripheral clock\r
+ unsigned int speed) // \arg UART baudrate\r
+{\r
+ //* Define the baud rate divisor register\r
+ pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_SetTimeguard\r
+//* \brief Set USART timeguard\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US_SetTimeguard (\r
+ AT91PS_USART pUSART, // \arg pointer to a USART controller\r
+ unsigned int timeguard) // \arg timeguard value\r
+{\r
+ //* Write the Timeguard Register\r
+ pUSART->US_TTGR = timeguard ;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_EnableIt\r
+//* \brief Enable USART IT\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US_EnableIt (\r
+ AT91PS_USART pUSART, // \arg pointer to a USART controller\r
+ unsigned int flag) // \arg IT to be enabled\r
+{\r
+ //* Write to the IER register\r
+ pUSART->US_IER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_DisableIt\r
+//* \brief Disable USART IT\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US_DisableIt (\r
+ AT91PS_USART pUSART, // \arg pointer to a USART controller\r
+ unsigned int flag) // \arg IT to be disabled\r
+{\r
+ //* Write to the IER register\r
+ pUSART->US_IDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_Configure\r
+//* \brief Configure USART\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US_Configure (\r
+ AT91PS_USART pUSART, // \arg pointer to a USART controller\r
+ unsigned int mainClock, // \arg peripheral clock\r
+ unsigned int mode , // \arg mode Register to be programmed\r
+ unsigned int baudRate , // \arg baudrate to be programmed\r
+ unsigned int timeguard ) // \arg timeguard to be programmed\r
+{\r
+ //* Disable interrupts\r
+ pUSART->US_IDR = (unsigned int) -1;\r
+\r
+ //* Reset receiver and transmitter\r
+ pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ;\r
+\r
+ //* Define the baud rate divisor register\r
+ AT91F_US_SetBaudrate(pUSART, mainClock, baudRate);\r
+\r
+ //* Write the Timeguard Register\r
+ AT91F_US_SetTimeguard(pUSART, timeguard);\r
+\r
+ //* Clear Transmit and Receive Counters\r
+ AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR));\r
+\r
+ //* Define the USART mode\r
+ pUSART->US_MR = mode ;\r
+\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_EnableRx\r
+//* \brief Enable receiving characters\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US_EnableRx (\r
+ AT91PS_USART pUSART) // \arg pointer to a USART controller\r
+{\r
+ //* Enable receiver\r
+ pUSART->US_CR = AT91C_US_RXEN;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_EnableTx\r
+//* \brief Enable sending characters\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US_EnableTx (\r
+ AT91PS_USART pUSART) // \arg pointer to a USART controller\r
+{\r
+ //* Enable transmitter\r
+ pUSART->US_CR = AT91C_US_TXEN;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_ResetRx\r
+//* \brief Reset Receiver and re-enable it\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US_ResetRx (\r
+ AT91PS_USART pUSART) // \arg pointer to a USART controller\r
+{\r
+ //* Reset receiver\r
+ pUSART->US_CR = AT91C_US_RSTRX;\r
+ //* Re-Enable receiver\r
+ pUSART->US_CR = AT91C_US_RXEN;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_ResetTx\r
+//* \brief Reset Transmitter and re-enable it\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US_ResetTx (\r
+ AT91PS_USART pUSART) // \arg pointer to a USART controller\r
+{\r
+ //* Reset transmitter\r
+ pUSART->US_CR = AT91C_US_RSTTX;\r
+ //* Enable transmitter\r
+ pUSART->US_CR = AT91C_US_TXEN;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_DisableRx\r
+//* \brief Disable Receiver\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US_DisableRx (\r
+ AT91PS_USART pUSART) // \arg pointer to a USART controller\r
+{\r
+ //* Disable receiver\r
+ pUSART->US_CR = AT91C_US_RXDIS;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_DisableTx\r
+//* \brief Disable Transmitter\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US_DisableTx (\r
+ AT91PS_USART pUSART) // \arg pointer to a USART controller\r
+{\r
+ //* Disable transmitter\r
+ pUSART->US_CR = AT91C_US_TXDIS;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_Close\r
+//* \brief Close USART: disable IT disable receiver and transmitter, close PDC\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US_Close (\r
+ AT91PS_USART pUSART) // \arg pointer to a USART controller\r
+{\r
+ //* Reset the baud rate divisor register\r
+ pUSART->US_BRGR = 0 ;\r
+\r
+ //* Reset the USART mode\r
+ pUSART->US_MR = 0 ;\r
+\r
+ //* Reset the Timeguard Register\r
+ pUSART->US_TTGR = 0;\r
+\r
+ //* Disable all interrupts\r
+ pUSART->US_IDR = 0xFFFFFFFF ;\r
+\r
+ //* Abort the Peripheral Data Transfers\r
+ AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR));\r
+\r
+ //* Disable receiver and transmitter and stop any activity immediately\r
+ pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_TxReady\r
+//* \brief Return 1 if a character can be written in US_THR\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_US_TxReady (\r
+ AT91PS_USART pUSART ) // \arg pointer to a USART controller\r
+{\r
+ return (pUSART->US_CSR & AT91C_US_TXRDY);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_RxReady\r
+//* \brief Return 1 if a character can be read in US_RHR\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_US_RxReady (\r
+ AT91PS_USART pUSART ) // \arg pointer to a USART controller\r
+{\r
+ return (pUSART->US_CSR & AT91C_US_RXRDY);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_Error\r
+//* \brief Return the error flag\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_US_Error (\r
+ AT91PS_USART pUSART ) // \arg pointer to a USART controller\r
+{\r
+ return (pUSART->US_CSR &\r
+ (AT91C_US_OVRE | // Overrun error\r
+ AT91C_US_FRAME | // Framing error\r
+ AT91C_US_PARE)); // Parity error\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_PutChar\r
+//* \brief Send a character,does not check if ready to send\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US_PutChar (\r
+ AT91PS_USART pUSART,\r
+ int character )\r
+{\r
+ pUSART->US_THR = (character & 0x1FF);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_GetChar\r
+//* \brief Receive a character,does not check if a character is available\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_US_GetChar (\r
+ const AT91PS_USART pUSART)\r
+{\r
+ return((pUSART->US_RHR) & 0x1FF);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_SendFrame\r
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_US_SendFrame(\r
+ AT91PS_USART pUSART,\r
+ char *pBuffer,\r
+ unsigned int szBuffer,\r
+ char *pNextBuffer,\r
+ unsigned int szNextBuffer )\r
+{\r
+ return AT91F_PDC_SendFrame(\r
+ (AT91PS_PDC) &(pUSART->US_RPR),\r
+ pBuffer,\r
+ szBuffer,\r
+ pNextBuffer,\r
+ szNextBuffer);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_ReceiveFrame\r
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_US_ReceiveFrame (\r
+ AT91PS_USART pUSART,\r
+ char *pBuffer,\r
+ unsigned int szBuffer,\r
+ char *pNextBuffer,\r
+ unsigned int szNextBuffer )\r
+{\r
+ return AT91F_PDC_ReceiveFrame(\r
+ (AT91PS_PDC) &(pUSART->US_RPR),\r
+ pBuffer,\r
+ szBuffer,\r
+ pNextBuffer,\r
+ szNextBuffer);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_SetIrdaFilter\r
+//* \brief Set the value of IrDa filter tregister\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US_SetIrdaFilter (\r
+ AT91PS_USART pUSART,\r
+ unsigned char value\r
+)\r
+{\r
+ pUSART->US_IF = value;\r
+}\r
+\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR SSC\r
+ ***************************************************************************** */\r
+//* Define the standard I2S mode configuration\r
+\r
+//* Configuration to set in the SSC Transmit Clock Mode Register\r
+//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits\r
+//* nb_slot_by_frame : number of channels\r
+#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\\r
+ AT91C_SSC_CKS_DIV +\\r
+ AT91C_SSC_CKO_CONTINOUS +\\r
+ AT91C_SSC_CKG_NONE +\\r
+ AT91C_SSC_START_FALL_RF +\\r
+ AT91C_SSC_STTOUT +\\r
+ ((1<<16) & AT91C_SSC_STTDLY) +\\r
+ ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24))\r
+\r
+\r
+//* Configuration to set in the SSC Transmit Frame Mode Register\r
+//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits\r
+//* nb_slot_by_frame : number of channels\r
+#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\\r
+ (nb_bit_by_slot-1) +\\r
+ AT91C_SSC_MSBF +\\r
+ (((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB) +\\r
+ (((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\\r
+ AT91C_SSC_FSOS_NEGATIVE)\r
+\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SSC_SetBaudrate\r
+//* \brief Set the baudrate according to the CPU clock\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SSC_SetBaudrate (\r
+ AT91PS_SSC pSSC, // \arg pointer to a SSC controller\r
+ unsigned int mainClock, // \arg peripheral clock\r
+ unsigned int speed) // \arg SSC baudrate\r
+{\r
+ unsigned int baud_value;\r
+ //* Define the baud rate divisor register\r
+ if (speed == 0)\r
+ baud_value = 0;\r
+ else\r
+ {\r
+ baud_value = (unsigned int) (mainClock * 10)/(2*speed);\r
+ if ((baud_value % 10) >= 5)\r
+ baud_value = (baud_value / 10) + 1;\r
+ else\r
+ baud_value /= 10;\r
+ }\r
+\r
+ pSSC->SSC_CMR = baud_value;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SSC_Configure\r
+//* \brief Configure SSC\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SSC_Configure (\r
+ AT91PS_SSC pSSC, // \arg pointer to a SSC controller\r
+ unsigned int syst_clock, // \arg System Clock Frequency\r
+ unsigned int baud_rate, // \arg Expected Baud Rate Frequency\r
+ unsigned int clock_rx, // \arg Receiver Clock Parameters\r
+ unsigned int mode_rx, // \arg mode Register to be programmed\r
+ unsigned int clock_tx, // \arg Transmitter Clock Parameters\r
+ unsigned int mode_tx) // \arg mode Register to be programmed\r
+{\r
+ //* Disable interrupts\r
+ pSSC->SSC_IDR = (unsigned int) -1;\r
+\r
+ //* Reset receiver and transmitter\r
+ pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ;\r
+\r
+ //* Define the Clock Mode Register\r
+ AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate);\r
+\r
+ //* Write the Receive Clock Mode Register\r
+ pSSC->SSC_RCMR = clock_rx;\r
+\r
+ //* Write the Transmit Clock Mode Register\r
+ pSSC->SSC_TCMR = clock_tx;\r
+\r
+ //* Write the Receive Frame Mode Register\r
+ pSSC->SSC_RFMR = mode_rx;\r
+\r
+ //* Write the Transmit Frame Mode Register\r
+ pSSC->SSC_TFMR = mode_tx;\r
+\r
+ //* Clear Transmit and Receive Counters\r
+ AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR));\r
+\r
+\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SSC_EnableRx\r
+//* \brief Enable receiving datas\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SSC_EnableRx (\r
+ AT91PS_SSC pSSC) // \arg pointer to a SSC controller\r
+{\r
+ //* Enable receiver\r
+ pSSC->SSC_CR = AT91C_SSC_RXEN;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SSC_DisableRx\r
+//* \brief Disable receiving datas\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SSC_DisableRx (\r
+ AT91PS_SSC pSSC) // \arg pointer to a SSC controller\r
+{\r
+ //* Disable receiver\r
+ pSSC->SSC_CR = AT91C_SSC_RXDIS;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SSC_EnableTx\r
+//* \brief Enable sending datas\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SSC_EnableTx (\r
+ AT91PS_SSC pSSC) // \arg pointer to a SSC controller\r
+{\r
+ //* Enable transmitter\r
+ pSSC->SSC_CR = AT91C_SSC_TXEN;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SSC_DisableTx\r
+//* \brief Disable sending datas\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SSC_DisableTx (\r
+ AT91PS_SSC pSSC) // \arg pointer to a SSC controller\r
+{\r
+ //* Disable transmitter\r
+ pSSC->SSC_CR = AT91C_SSC_TXDIS;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SSC_EnableIt\r
+//* \brief Enable SSC IT\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SSC_EnableIt (\r
+ AT91PS_SSC pSSC, // \arg pointer to a SSC controller\r
+ unsigned int flag) // \arg IT to be enabled\r
+{\r
+ //* Write to the IER register\r
+ pSSC->SSC_IER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SSC_DisableIt\r
+//* \brief Disable SSC IT\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SSC_DisableIt (\r
+ AT91PS_SSC pSSC, // \arg pointer to a SSC controller\r
+ unsigned int flag) // \arg IT to be disabled\r
+{\r
+ //* Write to the IDR register\r
+ pSSC->SSC_IDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SSC_ReceiveFrame\r
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_SSC_ReceiveFrame (\r
+ AT91PS_SSC pSSC,\r
+ char *pBuffer,\r
+ unsigned int szBuffer,\r
+ char *pNextBuffer,\r
+ unsigned int szNextBuffer )\r
+{\r
+ return AT91F_PDC_ReceiveFrame(\r
+ (AT91PS_PDC) &(pSSC->SSC_RPR),\r
+ pBuffer,\r
+ szBuffer,\r
+ pNextBuffer,\r
+ szNextBuffer);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SSC_SendFrame\r
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_SSC_SendFrame(\r
+ AT91PS_SSC pSSC,\r
+ char *pBuffer,\r
+ unsigned int szBuffer,\r
+ char *pNextBuffer,\r
+ unsigned int szNextBuffer )\r
+{\r
+ return AT91F_PDC_SendFrame(\r
+ (AT91PS_PDC) &(pSSC->SSC_RPR),\r
+ pBuffer,\r
+ szBuffer,\r
+ pNextBuffer,\r
+ szNextBuffer);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SSC_GetInterruptMaskStatus\r
+//* \brief Return SSC Interrupt Mask Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status\r
+ AT91PS_SSC pSsc) // \arg pointer to a SSC controller\r
+{\r
+ return pSsc->SSC_IMR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SSC_IsInterruptMasked\r
+//* \brief Test if SSC Interrupt is Masked \r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_SSC_IsInterruptMasked(\r
+ AT91PS_SSC pSsc, // \arg pointer to a SSC controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag);\r
+}\r
+\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR TWI\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TWI_EnableIt\r
+//* \brief Enable TWI IT\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TWI_EnableIt (\r
+ AT91PS_TWI pTWI, // \arg pointer to a TWI controller\r
+ unsigned int flag) // \arg IT to be enabled\r
+{\r
+ //* Write to the IER register\r
+ pTWI->TWI_IER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TWI_DisableIt\r
+//* \brief Disable TWI IT\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TWI_DisableIt (\r
+ AT91PS_TWI pTWI, // \arg pointer to a TWI controller\r
+ unsigned int flag) // \arg IT to be disabled\r
+{\r
+ //* Write to the IDR register\r
+ pTWI->TWI_IDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TWI_Configure\r
+//* \brief Configure TWI in master mode\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI ) // \arg pointer to a TWI controller\r
+{\r
+ //* Disable interrupts\r
+ pTWI->TWI_IDR = (unsigned int) -1;\r
+\r
+ //* Reset peripheral\r
+ pTWI->TWI_CR = AT91C_TWI_SWRST;\r
+\r
+ //* Set Master mode\r
+ pTWI->TWI_CR = AT91C_TWI_MSEN;\r
+\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TWI_GetInterruptMaskStatus\r
+//* \brief Return TWI Interrupt Mask Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status\r
+ AT91PS_TWI pTwi) // \arg pointer to a TWI controller\r
+{\r
+ return pTwi->TWI_IMR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TWI_IsInterruptMasked\r
+//* \brief Test if TWI Interrupt is Masked \r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_TWI_IsInterruptMasked(\r
+ AT91PS_TWI pTwi, // \arg pointer to a TWI controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag);\r
+}\r
+\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR PWMC\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWM_GetStatus\r
+//* \brief Return PWM Interrupt Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PWMC_GetStatus( // \return PWM Interrupt Status\r
+ AT91PS_PWMC pPWM) // pointer to a PWM controller\r
+{\r
+ return pPWM->PWMC_SR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWM_InterruptEnable\r
+//* \brief Enable PWM Interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PWMC_InterruptEnable(\r
+ AT91PS_PWMC pPwm, // \arg pointer to a PWM controller\r
+ unsigned int flag) // \arg PWM interrupt to be enabled\r
+{\r
+ pPwm->PWMC_IER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWM_InterruptDisable\r
+//* \brief Disable PWM Interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PWMC_InterruptDisable(\r
+ AT91PS_PWMC pPwm, // \arg pointer to a PWM controller\r
+ unsigned int flag) // \arg PWM interrupt to be disabled\r
+{\r
+ pPwm->PWMC_IDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWM_GetInterruptMaskStatus\r
+//* \brief Return PWM Interrupt Mask Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( // \return PWM Interrupt Mask Status\r
+ AT91PS_PWMC pPwm) // \arg pointer to a PWM controller\r
+{\r
+ return pPwm->PWMC_IMR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWM_IsInterruptMasked\r
+//* \brief Test if PWM Interrupt is Masked\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PWMC_IsInterruptMasked(\r
+ AT91PS_PWMC pPWM, // \arg pointer to a PWM controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_PWMC_GetInterruptMaskStatus(pPWM) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWM_IsStatusSet\r
+//* \brief Test if PWM Interrupt is Set\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PWMC_IsStatusSet(\r
+ AT91PS_PWMC pPWM, // \arg pointer to a PWM controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_PWMC_GetStatus(pPWM) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWM_CfgChannel\r
+//* \brief Test if PWM Interrupt is Set\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PWMC_CfgChannel(\r
+ AT91PS_PWMC pPWM, // \arg pointer to a PWM controller\r
+ unsigned int channelId, // \arg PWM channel ID\r
+ unsigned int mode, // \arg PWM mode\r
+ unsigned int period, // \arg PWM period\r
+ unsigned int duty) // \arg PWM duty cycle\r
+{\r
+ pPWM->PWMC_CH[channelId].PWMC_CMR = mode;\r
+ pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty;\r
+ pPWM->PWMC_CH[channelId].PWMC_CPRDR = period;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWM_StartChannel\r
+//* \brief Enable channel\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PWMC_StartChannel(\r
+ AT91PS_PWMC pPWM, // \arg pointer to a PWM controller\r
+ unsigned int flag) // \arg Channels IDs to be enabled\r
+{\r
+ pPWM->PWMC_ENA = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWM_StopChannel\r
+//* \brief Disable channel\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PWMC_StopChannel(\r
+ AT91PS_PWMC pPWM, // \arg pointer to a PWM controller\r
+ unsigned int flag) // \arg Channels IDs to be enabled\r
+{\r
+ pPWM->PWMC_DIS = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWM_UpdateChannel\r
+//* \brief Update Period or Duty Cycle\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PWMC_UpdateChannel(\r
+ AT91PS_PWMC pPWM, // \arg pointer to a PWM controller\r
+ unsigned int channelId, // \arg PWM channel ID\r
+ unsigned int update) // \arg Channels IDs to be enabled\r
+{\r
+ pPWM->PWMC_CH[channelId].PWMC_CUPDR = update;\r
+}\r
+\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR UDP\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_EnableIt\r
+//* \brief Enable UDP IT\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_UDP_EnableIt (\r
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller\r
+ unsigned int flag) // \arg IT to be enabled\r
+{\r
+ //* Write to the IER register\r
+ pUDP->UDP_IER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_DisableIt\r
+//* \brief Disable UDP IT\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_UDP_DisableIt (\r
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller\r
+ unsigned int flag) // \arg IT to be disabled\r
+{\r
+ //* Write to the IDR register\r
+ pUDP->UDP_IDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_SetAddress\r
+//* \brief Set UDP functional address\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_UDP_SetAddress (\r
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller\r
+ unsigned char address) // \arg new UDP address\r
+{\r
+ pUDP->UDP_FADDR = (AT91C_UDP_FEN | address);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_EnableEp\r
+//* \brief Enable Endpoint\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_UDP_EnableEp (\r
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller\r
+ unsigned char endpoint) // \arg endpoint number\r
+{\r
+ pUDP->UDP_CSR[endpoint] |= AT91C_UDP_EPEDS;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_DisableEp\r
+//* \brief Enable Endpoint\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_UDP_DisableEp (\r
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller\r
+ unsigned char endpoint) // \arg endpoint number\r
+{\r
+ pUDP->UDP_CSR[endpoint] &= ~AT91C_UDP_EPEDS;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_SetState\r
+//* \brief Set UDP Device state\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_UDP_SetState (\r
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller\r
+ unsigned int flag) // \arg new UDP address\r
+{\r
+ pUDP->UDP_GLBSTATE &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG);\r
+ pUDP->UDP_GLBSTATE |= flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_GetState\r
+//* \brief return UDP Device state\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state\r
+ AT91PS_UDP pUDP) // \arg pointer to a UDP controller\r
+{\r
+ return (pUDP->UDP_GLBSTATE & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_ResetEp\r
+//* \brief Reset UDP endpoint\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_UDP_ResetEp ( // \return the UDP device state\r
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller\r
+ unsigned int flag) // \arg Endpoints to be reset\r
+{\r
+ pUDP->UDP_RSTEP = flag;\r
+ pUDP->UDP_RSTEP = 0;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_EpStall\r
+//* \brief Endpoint will STALL requests\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_UDP_EpStall(\r
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller\r
+ unsigned char endpoint) // \arg endpoint number\r
+{\r
+ pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_EpWrite\r
+//* \brief Write value in the DPR\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_UDP_EpWrite(\r
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller\r
+ unsigned char endpoint, // \arg endpoint number\r
+ unsigned char value) // \arg value to be written in the DPR\r
+{\r
+ pUDP->UDP_FDR[endpoint] = value;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_EpRead\r
+//* \brief Return value from the DPR\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_UDP_EpRead(\r
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller\r
+ unsigned char endpoint) // \arg endpoint number\r
+{\r
+ return pUDP->UDP_FDR[endpoint];\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_EpEndOfWr\r
+//* \brief Notify the UDP that values in DPR are ready to be sent\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_UDP_EpEndOfWr(\r
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller\r
+ unsigned char endpoint) // \arg endpoint number\r
+{\r
+ pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_EpClear\r
+//* \brief Clear flag in the endpoint CSR register\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_UDP_EpClear(\r
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller\r
+ unsigned char endpoint, // \arg endpoint number\r
+ unsigned int flag) // \arg flag to be cleared\r
+{\r
+ pUDP->UDP_CSR[endpoint] &= ~(flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_EpSet\r
+//* \brief Set flag in the endpoint CSR register\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_UDP_EpSet(\r
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller\r
+ unsigned char endpoint, // \arg endpoint number\r
+ unsigned int flag) // \arg flag to be cleared\r
+{\r
+ pUDP->UDP_CSR[endpoint] |= flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_EpStatus\r
+//* \brief Return the endpoint CSR register\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_UDP_EpStatus(\r
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller\r
+ unsigned char endpoint) // \arg endpoint number\r
+{\r
+ return pUDP->UDP_CSR[endpoint];\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_GetInterruptMaskStatus\r
+//* \brief Return UDP Interrupt Mask Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \return UDP Interrupt Mask Status\r
+ AT91PS_UDP pUdp) // \arg pointer to a UDP controller\r
+{\r
+ return pUdp->UDP_IMR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_IsInterruptMasked\r
+//* \brief Test if UDP Interrupt is Masked \r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_UDP_IsInterruptMasked(\r
+ AT91PS_UDP pUdp, // \arg pointer to a UDP controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag);\r
+}\r
+\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR TC\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TC_InterruptEnable\r
+//* \brief Enable TC Interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TC_InterruptEnable(\r
+ AT91PS_TC pTc, // \arg pointer to a TC controller\r
+ unsigned int flag) // \arg TC interrupt to be enabled\r
+{\r
+ pTc->TC_IER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TC_InterruptDisable\r
+//* \brief Disable TC Interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TC_InterruptDisable(\r
+ AT91PS_TC pTc, // \arg pointer to a TC controller\r
+ unsigned int flag) // \arg TC interrupt to be disabled\r
+{\r
+ pTc->TC_IDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TC_GetInterruptMaskStatus\r
+//* \brief Return TC Interrupt Mask Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status\r
+ AT91PS_TC pTc) // \arg pointer to a TC controller\r
+{\r
+ return pTc->TC_IMR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TC_IsInterruptMasked\r
+//* \brief Test if TC Interrupt is Masked \r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_TC_IsInterruptMasked(\r
+ AT91PS_TC pTc, // \arg pointer to a TC controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag);\r
+}\r
+\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR CAN\r
+ ***************************************************************************** */\r
+#define STANDARD_FORMAT 0\r
+#define EXTENDED_FORMAT 1\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_InitMailboxRegisters()\r
+//* \brief Configure the corresponding mailbox\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_InitMailboxRegisters(AT91PS_CAN_MB CAN_Mailbox,\r
+ int mode_reg,\r
+ int acceptance_mask_reg,\r
+ int id_reg,\r
+ int data_low_reg,\r
+ int data_high_reg,\r
+ int control_reg)\r
+{\r
+ CAN_Mailbox->CAN_MB_MCR = 0x0;\r
+ CAN_Mailbox->CAN_MB_MMR = mode_reg;\r
+ CAN_Mailbox->CAN_MB_MAM = acceptance_mask_reg;\r
+ CAN_Mailbox->CAN_MB_MID = id_reg;\r
+ CAN_Mailbox->CAN_MB_MDL = data_low_reg; \r
+ CAN_Mailbox->CAN_MB_MDH = data_high_reg;\r
+ CAN_Mailbox->CAN_MB_MCR = control_reg;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_EnableCAN()\r
+//* \brief \r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_EnableCAN(\r
+ AT91PS_CAN pCAN) // pointer to a CAN controller\r
+{\r
+ pCAN->CAN_MR |= AT91C_CAN_CANEN;\r
+\r
+ // Wait for WAKEUP flag raising <=> 11-recessive-bit were scanned by the transceiver\r
+ while( (pCAN->CAN_SR & AT91C_CAN_WAKEUP) != AT91C_CAN_WAKEUP );\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_DisableCAN()\r
+//* \brief \r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_DisableCAN(\r
+ AT91PS_CAN pCAN) // pointer to a CAN controller\r
+{\r
+ pCAN->CAN_MR &= ~AT91C_CAN_CANEN;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_EnableIt\r
+//* \brief Enable CAN interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CAN_EnableIt (\r
+ AT91PS_CAN pCAN, // pointer to a CAN controller\r
+ unsigned int flag) // IT to be enabled\r
+{\r
+ //* Write to the IER register\r
+ pCAN->CAN_IER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_DisableIt\r
+//* \brief Disable CAN interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CAN_DisableIt (\r
+ AT91PS_CAN pCAN, // pointer to a CAN controller\r
+ unsigned int flag) // IT to be disabled\r
+{\r
+ //* Write to the IDR register\r
+ pCAN->CAN_IDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_GetStatus\r
+//* \brief Return CAN Interrupt Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CAN_GetStatus( // \return CAN Interrupt Status\r
+ AT91PS_CAN pCAN) // pointer to a CAN controller\r
+{\r
+ return pCAN->CAN_SR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_GetInterruptMaskStatus\r
+//* \brief Return CAN Interrupt Mask Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CAN_GetInterruptMaskStatus( // \return CAN Interrupt Mask Status\r
+ AT91PS_CAN pCAN) // pointer to a CAN controller\r
+{\r
+ return pCAN->CAN_IMR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_IsInterruptMasked\r
+//* \brief Test if CAN Interrupt is Masked \r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CAN_IsInterruptMasked(\r
+ AT91PS_CAN pCAN, // \arg pointer to a CAN controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_CAN_GetInterruptMaskStatus(pCAN) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_IsStatusSet\r
+//* \brief Test if CAN Interrupt is Set\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CAN_IsStatusSet(\r
+ AT91PS_CAN pCAN, // \arg pointer to a CAN controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_CAN_GetStatus(pCAN) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_CfgModeReg\r
+//* \brief Configure the Mode Register of the CAN controller\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CAN_CfgModeReg (\r
+ AT91PS_CAN pCAN, // pointer to a CAN controller\r
+ unsigned int mode) // mode register \r
+{\r
+ //* Write to the MR register\r
+ pCAN->CAN_MR = mode;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_GetModeReg\r
+//* \brief Return the Mode Register of the CAN controller value\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CAN_GetModeReg (\r
+ AT91PS_CAN pCAN // pointer to a CAN controller\r
+ )\r
+{\r
+ return pCAN->CAN_MR; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_CfgBaudrateReg\r
+//* \brief Configure the Baudrate of the CAN controller for the network\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CAN_CfgBaudrateReg (\r
+ AT91PS_CAN pCAN, // pointer to a CAN controller\r
+ unsigned int baudrate_cfg)\r
+{\r
+ //* Write to the BR register\r
+ pCAN->CAN_BR = baudrate_cfg; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_GetBaudrate\r
+//* \brief Return the Baudrate of the CAN controller for the network value\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CAN_GetBaudrate (\r
+ AT91PS_CAN pCAN // pointer to a CAN controller\r
+ )\r
+{\r
+ return pCAN->CAN_BR; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_GetInternalCounter\r
+//* \brief Return CAN Timer Regsiter Value\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CAN_GetInternalCounter (\r
+ AT91PS_CAN pCAN // pointer to a CAN controller\r
+ )\r
+{\r
+ return pCAN->CAN_TIM; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_GetTimestamp\r
+//* \brief Return CAN Timestamp Register Value\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CAN_GetTimestamp (\r
+ AT91PS_CAN pCAN // pointer to a CAN controller\r
+ )\r
+{\r
+ return pCAN->CAN_TIMESTP; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_GetErrorCounter\r
+//* \brief Return CAN Error Counter Register Value\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CAN_GetErrorCounter (\r
+ AT91PS_CAN pCAN // pointer to a CAN controller\r
+ )\r
+{\r
+ return pCAN->CAN_ECR; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_InitTransferRequest\r
+//* \brief Request for a transfer on the corresponding mailboxes\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CAN_InitTransferRequest (\r
+ AT91PS_CAN pCAN, // pointer to a CAN controller\r
+ unsigned int transfer_cmd)\r
+{\r
+ pCAN->CAN_TCR = transfer_cmd; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_InitAbortRequest\r
+//* \brief Abort the corresponding mailboxes\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CAN_InitAbortRequest (\r
+ AT91PS_CAN pCAN, // pointer to a CAN controller\r
+ unsigned int abort_cmd)\r
+{\r
+ pCAN->CAN_ACR = abort_cmd; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_CfgMessageModeReg\r
+//* \brief Program the Message Mode Register\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CAN_CfgMessageModeReg (\r
+ AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox\r
+ unsigned int mode)\r
+{\r
+ CAN_Mailbox->CAN_MB_MMR = mode; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_GetMessageModeReg\r
+//* \brief Return the Message Mode Register\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CAN_GetMessageModeReg (\r
+ AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox\r
+{\r
+ return CAN_Mailbox->CAN_MB_MMR; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_CfgMessageIDReg\r
+//* \brief Program the Message ID Register\r
+//* \brief Version == 0 for Standard messsage, Version == 1 for Extended \r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CAN_CfgMessageIDReg (\r
+ AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox\r
+ unsigned int id,\r
+ unsigned char version)\r
+{\r
+ if(version==0) // IDvA Standard Format\r
+ CAN_Mailbox->CAN_MB_MID = id<<18;\r
+ else // IDvB Extended Format\r
+ CAN_Mailbox->CAN_MB_MID = id | (1<<29); // set MIDE bit\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_GetMessageIDReg\r
+//* \brief Return the Message ID Register\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CAN_GetMessageIDReg (\r
+ AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox\r
+{\r
+ return CAN_Mailbox->CAN_MB_MID;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_CfgMessageAcceptanceMaskReg\r
+//* \brief Program the Message Acceptance Mask Register\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CAN_CfgMessageAcceptanceMaskReg (\r
+ AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox\r
+ unsigned int mask)\r
+{\r
+ CAN_Mailbox->CAN_MB_MAM = mask;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_GetMessageAcceptanceMaskReg\r
+//* \brief Return the Message Acceptance Mask Register\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CAN_GetMessageAcceptanceMaskReg (\r
+ AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox\r
+{\r
+ return CAN_Mailbox->CAN_MB_MAM;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_GetFamilyID\r
+//* \brief Return the Message ID Register\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CAN_GetFamilyID (\r
+ AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox\r
+{\r
+ return CAN_Mailbox->CAN_MB_MFID; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_CfgMessageCtrl\r
+//* \brief Request and config for a transfer on the corresponding mailbox\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CAN_CfgMessageCtrlReg (\r
+ AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox\r
+ unsigned int message_ctrl_cmd)\r
+{\r
+ CAN_Mailbox->CAN_MB_MCR = message_ctrl_cmd; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_GetMessageStatus\r
+//* \brief Return CAN Mailbox Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CAN_GetMessageStatus (\r
+ AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox\r
+{\r
+ return CAN_Mailbox->CAN_MB_MSR; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_CfgMessageDataLow\r
+//* \brief Program data low value\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CAN_CfgMessageDataLow (\r
+ AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox\r
+ unsigned int data)\r
+{\r
+ CAN_Mailbox->CAN_MB_MDL = data; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_GetMessageDataLow\r
+//* \brief Return data low value\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CAN_GetMessageDataLow (\r
+ AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox\r
+{\r
+ return CAN_Mailbox->CAN_MB_MDL; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_CfgMessageDataHigh\r
+//* \brief Program data high value\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CAN_CfgMessageDataHigh (\r
+ AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox\r
+ unsigned int data)\r
+{\r
+ CAN_Mailbox->CAN_MB_MDH = data; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_GetMessageDataHigh\r
+//* \brief Return data high value\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CAN_GetMessageDataHigh (\r
+ AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox\r
+{\r
+ return CAN_Mailbox->CAN_MB_MDH; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_Open\r
+//* \brief Open a CAN Port\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CAN_Open (\r
+ const unsigned int null) // \arg\r
+{\r
+ /* NOT DEFINED AT THIS MOMENT */\r
+ return ( 0 );\r
+}\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR ADC\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_EnableIt\r
+//* \brief Enable ADC interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_ADC_EnableIt (\r
+ AT91PS_ADC pADC, // pointer to a ADC controller\r
+ unsigned int flag) // IT to be enabled\r
+{\r
+ //* Write to the IER register\r
+ pADC->ADC_IER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_DisableIt\r
+//* \brief Disable ADC interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_ADC_DisableIt (\r
+ AT91PS_ADC pADC, // pointer to a ADC controller\r
+ unsigned int flag) // IT to be disabled\r
+{\r
+ //* Write to the IDR register\r
+ pADC->ADC_IDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_GetStatus\r
+//* \brief Return ADC Interrupt Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_GetStatus( // \return ADC Interrupt Status\r
+ AT91PS_ADC pADC) // pointer to a ADC controller\r
+{\r
+ return pADC->ADC_SR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_GetInterruptMaskStatus\r
+//* \brief Return ADC Interrupt Mask Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_GetInterruptMaskStatus( // \return ADC Interrupt Mask Status\r
+ AT91PS_ADC pADC) // pointer to a ADC controller\r
+{\r
+ return pADC->ADC_IMR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_IsInterruptMasked\r
+//* \brief Test if ADC Interrupt is Masked \r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_IsInterruptMasked(\r
+ AT91PS_ADC pADC, // \arg pointer to a ADC controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_ADC_GetInterruptMaskStatus(pADC) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_IsStatusSet\r
+//* \brief Test if ADC Status is Set\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_IsStatusSet(\r
+ AT91PS_ADC pADC, // \arg pointer to a ADC controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_ADC_GetStatus(pADC) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_CfgModeReg\r
+//* \brief Configure the Mode Register of the ADC controller\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_ADC_CfgModeReg (\r
+ AT91PS_ADC pADC, // pointer to a ADC controller\r
+ unsigned int mode) // mode register \r
+{\r
+ //* Write to the MR register\r
+ pADC->ADC_MR = mode;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_GetModeReg\r
+//* \brief Return the Mode Register of the ADC controller value\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_GetModeReg (\r
+ AT91PS_ADC pADC // pointer to a ADC controller\r
+ )\r
+{\r
+ return pADC->ADC_MR; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_CfgTimings\r
+//* \brief Configure the different necessary timings of the ADC controller\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_ADC_CfgTimings (\r
+ AT91PS_ADC pADC, // pointer to a ADC controller\r
+ unsigned int mck_clock, // in MHz \r
+ unsigned int adc_clock, // in MHz \r
+ unsigned int startup_time, // in us \r
+ unsigned int sample_and_hold_time) // in ns \r
+{\r
+ unsigned int prescal,startup,shtim;\r
+ \r
+ prescal = mck_clock/(2*adc_clock) - 1;\r
+ startup = adc_clock*startup_time/8 - 1;\r
+ shtim = adc_clock*sample_and_hold_time/1000 - 1;\r
+ \r
+ //* Write to the MR register\r
+ pADC->ADC_MR = ( (prescal<<8) & AT91C_ADC_PRESCAL) | ( (startup<<16) & AT91C_ADC_STARTUP) | ( (shtim<<24) & AT91C_ADC_SHTIM);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_EnableChannel\r
+//* \brief Return ADC Timer Register Value\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_ADC_EnableChannel (\r
+ AT91PS_ADC pADC, // pointer to a ADC controller\r
+ unsigned int channel) // mode register \r
+{\r
+ //* Write to the CHER register\r
+ pADC->ADC_CHER = channel;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_DisableChannel\r
+//* \brief Return ADC Timer Register Value\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_ADC_DisableChannel (\r
+ AT91PS_ADC pADC, // pointer to a ADC controller\r
+ unsigned int channel) // mode register \r
+{\r
+ //* Write to the CHDR register\r
+ pADC->ADC_CHDR = channel;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_GetChannelStatus\r
+//* \brief Return ADC Timer Register Value\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_GetChannelStatus (\r
+ AT91PS_ADC pADC // pointer to a ADC controller\r
+ )\r
+{\r
+ return pADC->ADC_CHSR; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_StartConversion\r
+//* \brief Software request for a analog to digital conversion \r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_ADC_StartConversion (\r
+ AT91PS_ADC pADC // pointer to a ADC controller\r
+ )\r
+{\r
+ pADC->ADC_CR = AT91C_ADC_START; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_SoftReset\r
+//* \brief Software reset\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_ADC_SoftReset (\r
+ AT91PS_ADC pADC // pointer to a ADC controller\r
+ )\r
+{\r
+ pADC->ADC_CR = AT91C_ADC_SWRST; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_GetLastConvertedData\r
+//* \brief Return the Last Converted Data\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_GetLastConvertedData (\r
+ AT91PS_ADC pADC // pointer to a ADC controller\r
+ )\r
+{\r
+ return pADC->ADC_LCDR; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_GetConvertedDataCH0\r
+//* \brief Return the Channel 0 Converted Data\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_GetConvertedDataCH0 (\r
+ AT91PS_ADC pADC // pointer to a ADC controller\r
+ )\r
+{\r
+ return pADC->ADC_CDR0; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_GetConvertedDataCH1\r
+//* \brief Return the Channel 1 Converted Data\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_GetConvertedDataCH1 (\r
+ AT91PS_ADC pADC // pointer to a ADC controller\r
+ )\r
+{\r
+ return pADC->ADC_CDR1; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_GetConvertedDataCH2\r
+//* \brief Return the Channel 2 Converted Data\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_GetConvertedDataCH2 (\r
+ AT91PS_ADC pADC // pointer to a ADC controller\r
+ )\r
+{\r
+ return pADC->ADC_CDR2; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_GetConvertedDataCH3\r
+//* \brief Return the Channel 3 Converted Data\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_GetConvertedDataCH3 (\r
+ AT91PS_ADC pADC // pointer to a ADC controller\r
+ )\r
+{\r
+ return pADC->ADC_CDR3; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_GetConvertedDataCH4\r
+//* \brief Return the Channel 4 Converted Data\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_GetConvertedDataCH4 (\r
+ AT91PS_ADC pADC // pointer to a ADC controller\r
+ )\r
+{\r
+ return pADC->ADC_CDR4; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_GetConvertedDataCH5\r
+//* \brief Return the Channel 5 Converted Data\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_GetConvertedDataCH5 (\r
+ AT91PS_ADC pADC // pointer to a ADC controller\r
+ )\r
+{\r
+ return pADC->ADC_CDR5; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_GetConvertedDataCH6\r
+//* \brief Return the Channel 6 Converted Data\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_GetConvertedDataCH6 (\r
+ AT91PS_ADC pADC // pointer to a ADC controller\r
+ )\r
+{\r
+ return pADC->ADC_CDR6; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_GetConvertedDataCH7\r
+//* \brief Return the Channel 7 Converted Data\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_GetConvertedDataCH7 (\r
+ AT91PS_ADC pADC // pointer to a ADC controller\r
+ )\r
+{\r
+ return pADC->ADC_CDR7; \r
+}\r
+\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR AES\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AES_EnableIt\r
+//* \brief Enable AES interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AES_EnableIt (\r
+ AT91PS_AES pAES, // pointer to a AES controller\r
+ unsigned int flag) // IT to be enabled\r
+{\r
+ //* Write to the IER register\r
+ pAES->AES_IER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AES_DisableIt\r
+//* \brief Disable AES interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AES_DisableIt (\r
+ AT91PS_AES pAES, // pointer to a AES controller\r
+ unsigned int flag) // IT to be disabled\r
+{\r
+ //* Write to the IDR register\r
+ pAES->AES_IDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AES_GetStatus\r
+//* \brief Return AES Interrupt Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_AES_GetStatus( // \return AES Interrupt Status\r
+ AT91PS_AES pAES) // pointer to a AES controller\r
+{\r
+ return pAES->AES_ISR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AES_GetInterruptMaskStatus\r
+//* \brief Return AES Interrupt Mask Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_AES_GetInterruptMaskStatus( // \return AES Interrupt Mask Status\r
+ AT91PS_AES pAES) // pointer to a AES controller\r
+{\r
+ return pAES->AES_IMR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AES_IsInterruptMasked\r
+//* \brief Test if AES Interrupt is Masked \r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_AES_IsInterruptMasked(\r
+ AT91PS_AES pAES, // \arg pointer to a AES controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_AES_GetInterruptMaskStatus(pAES) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AES_IsStatusSet\r
+//* \brief Test if AES Status is Set\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_AES_IsStatusSet(\r
+ AT91PS_AES pAES, // \arg pointer to a AES controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_AES_GetStatus(pAES) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AES_CfgModeReg\r
+//* \brief Configure the Mode Register of the AES controller\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AES_CfgModeReg (\r
+ AT91PS_AES pAES, // pointer to a AES controller\r
+ unsigned int mode) // mode register \r
+{\r
+ //* Write to the MR register\r
+ pAES->AES_MR = mode;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AES_GetModeReg\r
+//* \brief Return the Mode Register of the AES controller value\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_AES_GetModeReg (\r
+ AT91PS_AES pAES // pointer to a AES controller\r
+ )\r
+{\r
+ return pAES->AES_MR; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AES_StartProcessing\r
+//* \brief Start Encryption or Decryption\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AES_StartProcessing (\r
+ AT91PS_AES pAES // pointer to a AES controller\r
+ )\r
+{\r
+ pAES->AES_CR = AT91C_AES_START; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AES_SoftReset\r
+//* \brief Reset AES\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AES_SoftReset (\r
+ AT91PS_AES pAES // pointer to a AES controller\r
+ )\r
+{\r
+ pAES->AES_CR = AT91C_AES_SWRST; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AES_LoadNewSeed\r
+//* \brief Load New Seed in the random number generator\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AES_LoadNewSeed (\r
+ AT91PS_AES pAES // pointer to a AES controller\r
+ )\r
+{\r
+ pAES->AES_CR = AT91C_AES_LOADSEED; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AES_SetCryptoKey\r
+//* \brief Set Cryptographic Key x\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AES_SetCryptoKey (\r
+ AT91PS_AES pAES, // pointer to a AES controller\r
+ unsigned char index,\r
+ unsigned int keyword\r
+ )\r
+{\r
+ pAES->AES_KEYWxR[index] = keyword; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AES_InputData\r
+//* \brief Set Input Data x\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AES_InputData (\r
+ AT91PS_AES pAES, // pointer to a AES controller\r
+ unsigned char index,\r
+ unsigned int indata\r
+ )\r
+{\r
+ pAES->AES_IDATAxR[index] = indata; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AES_GetOutputData\r
+//* \brief Get Output Data x\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_AES_GetOutputData (\r
+ AT91PS_AES pAES, // pointer to a AES controller\r
+ unsigned char index\r
+ )\r
+{\r
+ return pAES->AES_ODATAxR[index]; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AES_SetInitializationVector\r
+//* \brief Set Initialization Vector (or Counter) x\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AES_SetInitializationVector (\r
+ AT91PS_AES pAES, // pointer to a AES controller\r
+ unsigned char index,\r
+ unsigned int initvector\r
+ )\r
+{\r
+ pAES->AES_IVxR[index] = initvector; \r
+}\r
+\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR TDES\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TDES_EnableIt\r
+//* \brief Enable TDES interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TDES_EnableIt (\r
+ AT91PS_TDES pTDES, // pointer to a TDES controller\r
+ unsigned int flag) // IT to be enabled\r
+{\r
+ //* Write to the IER register\r
+ pTDES->TDES_IER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TDES_DisableIt\r
+//* \brief Disable TDES interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TDES_DisableIt (\r
+ AT91PS_TDES pTDES, // pointer to a TDES controller\r
+ unsigned int flag) // IT to be disabled\r
+{\r
+ //* Write to the IDR register\r
+ pTDES->TDES_IDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TDES_GetStatus\r
+//* \brief Return TDES Interrupt Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_TDES_GetStatus( // \return TDES Interrupt Status\r
+ AT91PS_TDES pTDES) // pointer to a TDES controller\r
+{\r
+ return pTDES->TDES_ISR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TDES_GetInterruptMaskStatus\r
+//* \brief Return TDES Interrupt Mask Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_TDES_GetInterruptMaskStatus( // \return TDES Interrupt Mask Status\r
+ AT91PS_TDES pTDES) // pointer to a TDES controller\r
+{\r
+ return pTDES->TDES_IMR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TDES_IsInterruptMasked\r
+//* \brief Test if TDES Interrupt is Masked \r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_TDES_IsInterruptMasked(\r
+ AT91PS_TDES pTDES, // \arg pointer to a TDES controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_TDES_GetInterruptMaskStatus(pTDES) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TDES_IsStatusSet\r
+//* \brief Test if TDES Status is Set\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_TDES_IsStatusSet(\r
+ AT91PS_TDES pTDES, // \arg pointer to a TDES controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_TDES_GetStatus(pTDES) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TDES_CfgModeReg\r
+//* \brief Configure the Mode Register of the TDES controller\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TDES_CfgModeReg (\r
+ AT91PS_TDES pTDES, // pointer to a TDES controller\r
+ unsigned int mode) // mode register \r
+{\r
+ //* Write to the MR register\r
+ pTDES->TDES_MR = mode;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TDES_GetModeReg\r
+//* \brief Return the Mode Register of the TDES controller value\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_TDES_GetModeReg (\r
+ AT91PS_TDES pTDES // pointer to a TDES controller\r
+ )\r
+{\r
+ return pTDES->TDES_MR; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TDES_StartProcessing\r
+//* \brief Start Encryption or Decryption\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TDES_StartProcessing (\r
+ AT91PS_TDES pTDES // pointer to a TDES controller\r
+ )\r
+{\r
+ pTDES->TDES_CR = AT91C_TDES_START; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TDES_SoftReset\r
+//* \brief Reset TDES\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TDES_SoftReset (\r
+ AT91PS_TDES pTDES // pointer to a TDES controller\r
+ )\r
+{\r
+ pTDES->TDES_CR = AT91C_TDES_SWRST; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TDES_SetCryptoKey1\r
+//* \brief Set Cryptographic Key 1 Word x\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TDES_SetCryptoKey1 (\r
+ AT91PS_TDES pTDES, // pointer to a TDES controller\r
+ unsigned char index,\r
+ unsigned int keyword\r
+ )\r
+{\r
+ pTDES->TDES_KEY1WxR[index] = keyword; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TDES_SetCryptoKey2\r
+//* \brief Set Cryptographic Key 2 Word x\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TDES_SetCryptoKey2 (\r
+ AT91PS_TDES pTDES, // pointer to a TDES controller\r
+ unsigned char index,\r
+ unsigned int keyword\r
+ )\r
+{\r
+ pTDES->TDES_KEY2WxR[index] = keyword; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TDES_SetCryptoKey3\r
+//* \brief Set Cryptographic Key 3 Word x\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TDES_SetCryptoKey3 (\r
+ AT91PS_TDES pTDES, // pointer to a TDES controller\r
+ unsigned char index,\r
+ unsigned int keyword\r
+ )\r
+{\r
+ pTDES->TDES_KEY3WxR[index] = keyword; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TDES_InputData\r
+//* \brief Set Input Data x\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TDES_InputData (\r
+ AT91PS_TDES pTDES, // pointer to a TDES controller\r
+ unsigned char index,\r
+ unsigned int indata\r
+ )\r
+{\r
+ pTDES->TDES_IDATAxR[index] = indata; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TDES_GetOutputData\r
+//* \brief Get Output Data x\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_TDES_GetOutputData (\r
+ AT91PS_TDES pTDES, // pointer to a TDES controller\r
+ unsigned char index\r
+ )\r
+{\r
+ return pTDES->TDES_ODATAxR[index]; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TDES_SetInitializationVector\r
+//* \brief Set Initialization Vector x\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TDES_SetInitializationVector (\r
+ AT91PS_TDES pTDES, // pointer to a TDES controller\r
+ unsigned char index,\r
+ unsigned int initvector\r
+ )\r
+{\r
+ pTDES->TDES_IVxR[index] = initvector; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_DBGU_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for DBGU\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_DBGU_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_SYS));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_DBGU_CfgPIO\r
+//* \brief Configure PIO controllers to drive DBGU signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_DBGU_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOA, // PIO controller base address\r
+ ((unsigned int) AT91C_PA27_DRXD ) |\r
+ ((unsigned int) AT91C_PA28_DTXD ), // Peripheral A\r
+ 0); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for PMC\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PMC_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_SYS));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_CfgPIO\r
+//* \brief Configure PIO controllers to drive PMC signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PMC_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOB, // PIO controller base address\r
+ ((unsigned int) AT91C_PB30_PCK2 ) |\r
+ ((unsigned int) AT91C_PB29_PCK1 ), // Peripheral A\r
+ ((unsigned int) AT91C_PB20_PCK0 ) |\r
+ ((unsigned int) AT91C_PB0_PCK0 ) |\r
+ ((unsigned int) AT91C_PB22_PCK2 ) |\r
+ ((unsigned int) AT91C_PB21_PCK1 )); // Peripheral B\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOA, // PIO controller base address\r
+ 0, // Peripheral A\r
+ ((unsigned int) AT91C_PA30_PCK2 ) |\r
+ ((unsigned int) AT91C_PA13_PCK1 ) |\r
+ ((unsigned int) AT91C_PA27_PCK3 )); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_VREG_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for VREG\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_VREG_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_SYS));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_RSTC_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for RSTC\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_RSTC_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_SYS));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SSC_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for SSC\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SSC_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_SSC));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SSC_CfgPIO\r
+//* \brief Configure PIO controllers to drive SSC signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SSC_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOA, // PIO controller base address\r
+ ((unsigned int) AT91C_PA25_RK ) |\r
+ ((unsigned int) AT91C_PA22_TK ) |\r
+ ((unsigned int) AT91C_PA21_TF ) |\r
+ ((unsigned int) AT91C_PA24_RD ) |\r
+ ((unsigned int) AT91C_PA26_RF ) |\r
+ ((unsigned int) AT91C_PA23_TD ), // Peripheral A\r
+ 0); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_WDTC_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for WDTC\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_WDTC_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_SYS));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US1_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for US1\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US1_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_US1));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US1_CfgPIO\r
+//* \brief Configure PIO controllers to drive US1 signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US1_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOB, // PIO controller base address\r
+ 0, // Peripheral A\r
+ ((unsigned int) AT91C_PB26_RI1 ) |\r
+ ((unsigned int) AT91C_PB24_DSR1 ) |\r
+ ((unsigned int) AT91C_PB23_DCD1 ) |\r
+ ((unsigned int) AT91C_PB25_DTR1 )); // Peripheral B\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOA, // PIO controller base address\r
+ ((unsigned int) AT91C_PA7_SCK1 ) |\r
+ ((unsigned int) AT91C_PA8_RTS1 ) |\r
+ ((unsigned int) AT91C_PA6_TXD1 ) |\r
+ ((unsigned int) AT91C_PA5_RXD1 ) |\r
+ ((unsigned int) AT91C_PA9_CTS1 ), // Peripheral A\r
+ 0); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US0_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for US0\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US0_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_US0));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US0_CfgPIO\r
+//* \brief Configure PIO controllers to drive US0 signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US0_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOA, // PIO controller base address\r
+ ((unsigned int) AT91C_PA0_RXD0 ) |\r
+ ((unsigned int) AT91C_PA4_CTS0 ) |\r
+ ((unsigned int) AT91C_PA3_RTS0 ) |\r
+ ((unsigned int) AT91C_PA2_SCK0 ) |\r
+ ((unsigned int) AT91C_PA1_TXD0 ), // Peripheral A\r
+ 0); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI1_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for SPI1\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SPI1_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_SPI1));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI1_CfgPIO\r
+//* \brief Configure PIO controllers to drive SPI1 signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SPI1_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOB, // PIO controller base address\r
+ 0, // Peripheral A\r
+ ((unsigned int) AT91C_PB16_NPCS13 ) |\r
+ ((unsigned int) AT91C_PB10_NPCS11 ) |\r
+ ((unsigned int) AT91C_PB11_NPCS12 )); // Peripheral B\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOA, // PIO controller base address\r
+ 0, // Peripheral A\r
+ ((unsigned int) AT91C_PA4_NPCS13 ) |\r
+ ((unsigned int) AT91C_PA29_NPCS13 ) |\r
+ ((unsigned int) AT91C_PA21_NPCS10 ) |\r
+ ((unsigned int) AT91C_PA22_SPCK1 ) |\r
+ ((unsigned int) AT91C_PA25_NPCS11 ) |\r
+ ((unsigned int) AT91C_PA2_NPCS11 ) |\r
+ ((unsigned int) AT91C_PA24_MISO1 ) |\r
+ ((unsigned int) AT91C_PA3_NPCS12 ) |\r
+ ((unsigned int) AT91C_PA26_NPCS12 ) |\r
+ ((unsigned int) AT91C_PA23_MOSI1 )); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI0_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for SPI0\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SPI0_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_SPI0));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI0_CfgPIO\r
+//* \brief Configure PIO controllers to drive SPI0 signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SPI0_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOB, // PIO controller base address\r
+ 0, // Peripheral A\r
+ ((unsigned int) AT91C_PB13_NPCS01 ) |\r
+ ((unsigned int) AT91C_PB17_NPCS03 ) |\r
+ ((unsigned int) AT91C_PB14_NPCS02 )); // Peripheral B\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOA, // PIO controller base address\r
+ ((unsigned int) AT91C_PA16_MISO0 ) |\r
+ ((unsigned int) AT91C_PA13_NPCS01 ) |\r
+ ((unsigned int) AT91C_PA15_NPCS03 ) |\r
+ ((unsigned int) AT91C_PA17_MOSI0 ) |\r
+ ((unsigned int) AT91C_PA18_SPCK0 ) |\r
+ ((unsigned int) AT91C_PA14_NPCS02 ) |\r
+ ((unsigned int) AT91C_PA12_NPCS00 ), // Peripheral A\r
+ ((unsigned int) AT91C_PA7_NPCS01 ) |\r
+ ((unsigned int) AT91C_PA9_NPCS03 ) |\r
+ ((unsigned int) AT91C_PA8_NPCS02 )); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PITC_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for PITC\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PITC_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_SYS));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AIC_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for AIC\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AIC_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_FIQ) |\r
+ ((unsigned int) 1 << AT91C_ID_IRQ0) |\r
+ ((unsigned int) 1 << AT91C_ID_IRQ1));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AIC_CfgPIO\r
+//* \brief Configure PIO controllers to drive AIC signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AIC_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOA, // PIO controller base address\r
+ ((unsigned int) AT91C_PA30_IRQ0 ) |\r
+ ((unsigned int) AT91C_PA29_FIQ ), // Peripheral A\r
+ ((unsigned int) AT91C_PA14_IRQ1 )); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AES_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for AES\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AES_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_AES));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TWI_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for TWI\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TWI_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_TWI));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TWI_CfgPIO\r
+//* \brief Configure PIO controllers to drive TWI signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TWI_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOA, // PIO controller base address\r
+ ((unsigned int) AT91C_PA11_TWCK ) |\r
+ ((unsigned int) AT91C_PA10_TWD ), // Peripheral A\r
+ 0); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for ADC\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_ADC_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_ADC));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_CfgPIO\r
+//* \brief Configure PIO controllers to drive ADC signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_ADC_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOB, // PIO controller base address\r
+ 0, // Peripheral A\r
+ ((unsigned int) AT91C_PB18_ADTRG )); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWMC_CH3_CfgPIO\r
+//* \brief Configure PIO controllers to drive PWMC_CH3 signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PWMC_CH3_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOB, // PIO controller base address\r
+ ((unsigned int) AT91C_PB22_PWM3 ), // Peripheral A\r
+ ((unsigned int) AT91C_PB30_PWM3 )); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWMC_CH2_CfgPIO\r
+//* \brief Configure PIO controllers to drive PWMC_CH2 signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PWMC_CH2_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOB, // PIO controller base address\r
+ ((unsigned int) AT91C_PB21_PWM2 ), // Peripheral A\r
+ ((unsigned int) AT91C_PB29_PWM2 )); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWMC_CH1_CfgPIO\r
+//* \brief Configure PIO controllers to drive PWMC_CH1 signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PWMC_CH1_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOB, // PIO controller base address\r
+ ((unsigned int) AT91C_PB20_PWM1 ), // Peripheral A\r
+ ((unsigned int) AT91C_PB28_PWM1 )); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWMC_CH0_CfgPIO\r
+//* \brief Configure PIO controllers to drive PWMC_CH0 signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PWMC_CH0_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOB, // PIO controller base address\r
+ ((unsigned int) AT91C_PB19_PWM0 ), // Peripheral A\r
+ ((unsigned int) AT91C_PB27_PWM0 )); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_RTTC_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for RTTC\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_RTTC_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_SYS));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for UDP\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_UDP_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_UDP));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TDES_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for TDES\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TDES_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_TDES));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_EMAC_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for EMAC\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_EMAC_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_EMAC));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_EMAC_CfgPIO\r
+//* \brief Configure PIO controllers to drive EMAC signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_EMAC_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOB, // PIO controller base address\r
+ ((unsigned int) AT91C_PB2_ETX0 ) |\r
+ ((unsigned int) AT91C_PB12_ETXER ) |\r
+ ((unsigned int) AT91C_PB16_ECOL ) |\r
+ ((unsigned int) AT91C_PB11_ETX3 ) |\r
+ ((unsigned int) AT91C_PB6_ERX1 ) |\r
+ ((unsigned int) AT91C_PB15_ERXDV ) |\r
+ ((unsigned int) AT91C_PB13_ERX2 ) |\r
+ ((unsigned int) AT91C_PB3_ETX1 ) |\r
+ ((unsigned int) AT91C_PB8_EMDC ) |\r
+ ((unsigned int) AT91C_PB5_ERX0 ) |\r
+ //((unsigned int) AT91C_PB18_EF100 ) |\r
+ ((unsigned int) AT91C_PB14_ERX3 ) |\r
+ ((unsigned int) AT91C_PB4_ECRS_ECRSDV) |\r
+ ((unsigned int) AT91C_PB1_ETXEN ) |\r
+ ((unsigned int) AT91C_PB10_ETX2 ) |\r
+ ((unsigned int) AT91C_PB0_ETXCK_EREFCK) |\r
+ ((unsigned int) AT91C_PB9_EMDIO ) |\r
+ ((unsigned int) AT91C_PB7_ERXER ) |\r
+ ((unsigned int) AT91C_PB17_ERXCK ), // Peripheral A\r
+ 0); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TC0_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for TC0\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TC0_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_TC0));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TC0_CfgPIO\r
+//* \brief Configure PIO controllers to drive TC0 signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TC0_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOB, // PIO controller base address\r
+ ((unsigned int) AT91C_PB23_TIOA0 ) |\r
+ ((unsigned int) AT91C_PB24_TIOB0 ), // Peripheral A\r
+ ((unsigned int) AT91C_PB12_TCLK0 )); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TC1_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for TC1\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TC1_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_TC1));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TC1_CfgPIO\r
+//* \brief Configure PIO controllers to drive TC1 signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TC1_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOB, // PIO controller base address\r
+ ((unsigned int) AT91C_PB25_TIOA1 ) |\r
+ ((unsigned int) AT91C_PB26_TIOB1 ), // Peripheral A\r
+ ((unsigned int) AT91C_PB19_TCLK1 )); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TC2_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for TC2\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TC2_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_TC2));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TC2_CfgPIO\r
+//* \brief Configure PIO controllers to drive TC2 signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TC2_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOB, // PIO controller base address\r
+ ((unsigned int) AT91C_PB28_TIOB2 ) |\r
+ ((unsigned int) AT91C_PB27_TIOA2 ), // Peripheral A\r
+ 0); // Peripheral B\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOA, // PIO controller base address\r
+ 0, // Peripheral A\r
+ ((unsigned int) AT91C_PA15_TCLK2 )); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_MC_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for MC\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_MC_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_SYS));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIOA_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for PIOA\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIOA_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_PIOA));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIOB_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for PIOB\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIOB_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_PIOB));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for CAN\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CAN_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_CAN));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_CfgPIO\r
+//* \brief Configure PIO controllers to drive CAN signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CAN_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOA, // PIO controller base address\r
+ ((unsigned int) AT91C_PA20_CANTX ) |\r
+ ((unsigned int) AT91C_PA19_CANRX ), // Peripheral A\r
+ 0); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWMC_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for PWMC\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PWMC_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_PWMC));\r
+}\r
+\r
+#endif // lib_AT91SAM7X256_H\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ * Implementation of functions defined in portable.h for the ARM7 port.\r
+ *\r
+ * Components that can be compiled to either ARM or THUMB mode are\r
+ * contained in this file. The ISR routines, which can only be compiled\r
+ * to ARM mode are contained in portISR.c.\r
+ *----------------------------------------------------------*/\r
+\r
+/*\r
+ Changes from V2.5.2\r
+ \r
+ + ulCriticalNesting is now saved as part of the task context, as is \r
+ therefore added to the initial task stack during pxPortInitialiseStack.\r
+*/\r
+\r
+\r
+/* Standard includes. */\r
+#include <stdlib.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Processor constants. */\r
+#include "AT91SAM7X256.h"\r
+\r
+/* Constants required to setup the task context. */\r
+#define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */\r
+#define portTHUMB_MODE_BIT ( ( portSTACK_TYPE ) 0x20 )\r
+#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 )\r
+#define portNO_CRITICAL_SECTION_NESTING ( ( portSTACK_TYPE ) 0 )\r
+\r
+/* Constants required to setup the tick ISR. */\r
+#define portENABLE_TIMER ( ( unsigned portCHAR ) 0x01 )\r
+#define portPRESCALE_VALUE 0x00\r
+#define portINTERRUPT_ON_MATCH ( ( unsigned portLONG ) 0x01 )\r
+#define portRESET_COUNT_ON_MATCH ( ( unsigned portLONG ) 0x02 )\r
+\r
+/* Constants required to setup the PIT. */\r
+#define portPIT_CLOCK_DIVISOR ( ( unsigned portLONG ) 16 )\r
+#define portPIT_COUNTER_VALUE ( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_RATE_MS )\r
+\r
+#define portINT_LEVEL_SENSITIVE 0\r
+#define portPIT_ENABLE ( ( unsigned portSHORT ) 0x1 << 24 )\r
+#define portPIT_INT_ENABLE ( ( unsigned portSHORT ) 0x1 << 25 )\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Setup the timer to generate the tick interrupts. */\r
+static void prvSetupTimerInterrupt( void );\r
+\r
+/* \r
+ * The scheduler can only be started from ARM mode, so \r
+ * vPortISRStartFirstSTask() is defined in portISR.c. \r
+ */\r
+extern void vPortISRStartFirstTask( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* \r
+ * Initialise the stack of a task to look exactly as if a call to \r
+ * portSAVE_CONTEXT had been called.\r
+ *\r
+ * See header file for description. \r
+ */\r
+portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
+{\r
+portSTACK_TYPE *pxOriginalTOS;\r
+\r
+ pxOriginalTOS = pxTopOfStack;\r
+\r
+ /* Setup the initial stack of the task. The stack is set exactly as \r
+ expected by the portRESTORE_CONTEXT() macro. */\r
+\r
+ /* First on the stack is the return address - which in this case is the\r
+ start of the task. The offset is added to make the return address appear\r
+ as it would within an IRQ ISR. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; \r
+ pxTopOfStack--;\r
+\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */\r
+ pxTopOfStack--; \r
+\r
+ /* When the task starts is will expect to find the function parameter in\r
+ R0. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */\r
+ pxTopOfStack--;\r
+\r
+ /* The last thing onto the stack is the status register, which is set for\r
+ system mode, with interrupts enabled. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR;\r
+\r
+ #ifdef THUMB_INTERWORK\r
+ {\r
+ /* We want the task to start in thumb mode. */\r
+ *pxTopOfStack |= portTHUMB_MODE_BIT;\r
+ }\r
+ #endif\r
+\r
+ pxTopOfStack--;\r
+\r
+ /* Some optimisation levels use the stack differently to others. This \r
+ means the interrupt flags cannot always be stored on the stack and will\r
+ instead be stored in a variable, which is then saved as part of the\r
+ tasks context. */\r
+ *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;\r
+\r
+ return pxTopOfStack;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portBASE_TYPE xPortStartScheduler( void )\r
+{\r
+ /* Start the timer that generates the tick ISR. Interrupts are disabled\r
+ here already. */\r
+ prvSetupTimerInterrupt();\r
+\r
+ /* Start the first task. */\r
+ vPortISRStartFirstTask(); \r
+\r
+ /* Should not get here! */\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEndScheduler( void )\r
+{\r
+ /* It is unlikely that the ARM port will require this function as there\r
+ is nothing to return to. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Setup the timer 0 to generate the tick interrupts at the required frequency.\r
+ */\r
+static void prvSetupTimerInterrupt( void )\r
+{\r
+AT91PS_PITC pxPIT = AT91C_BASE_PITC;\r
+\r
+ /* Setup the AIC for PIT interrupts. The interrupt routine chosen depends\r
+ on whether the preemptive or cooperative scheduler is being used. */\r
+ #if configUSE_PREEMPTION == 0\r
+\r
+ extern void ( vNonPreemptiveTick ) ( void );\r
+ AT91F_AIC_ConfigureIt( AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vNonPreemptiveTick );\r
+\r
+ #else\r
+ \r
+ extern void ( vPreemptiveTick )( void );\r
+ AT91F_AIC_ConfigureIt( AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vPreemptiveTick );\r
+\r
+ #endif\r
+\r
+ /* Configure the PIT period. */\r
+ pxPIT->PITC_PIMR = portPIT_ENABLE | portPIT_INT_ENABLE | portPIT_COUNTER_VALUE;\r
+\r
+ /* Enable the interrupt. Global interrupts are disables at this point so \r
+ this is safe. */\r
+ AT91C_BASE_AIC->AIC_IECR = 0x1 << AT91C_ID_SYS;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ * Components that can be compiled to either ARM or THUMB mode are\r
+ * contained in port.c The ISR routines, which can only be compiled\r
+ * to ARM mode, are contained in this file.\r
+ *----------------------------------------------------------*/\r
+\r
+/*\r
+ Changes from V3.2.4\r
+\r
+ + The assembler statements are now included in a single asm block rather\r
+ than each line having its own asm block.\r
+*/\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+#include "AT91SAM7X256.h"\r
+\r
+/* Constants required to handle interrupts. */\r
+#define portTIMER_MATCH_ISR_BIT ( ( unsigned portCHAR ) 0x01 )\r
+#define portCLEAR_VIC_INTERRUPT ( ( unsigned portLONG ) 0 )\r
+\r
+/* Constants required to handle critical sections. */\r
+#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 )\r
+volatile unsigned portLONG ulCriticalNesting = 9999UL;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* ISR to handle manual context switches (from a call to taskYIELD()). */\r
+void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));\r
+\r
+/* \r
+ * The scheduler can only be started from ARM mode, hence the inclusion of this\r
+ * function here.\r
+ */\r
+void vPortISRStartFirstTask( void );\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortISRStartFirstTask( void )\r
+{\r
+ /* Simply start the scheduler. This is included here as it can only be\r
+ called from ARM mode. */\r
+ portRESTORE_CONTEXT();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Called by portYIELD() or taskYIELD() to manually force a context switch.\r
+ *\r
+ * When a context switch is performed from the task level the saved task \r
+ * context is made to look as if it occurred from within the tick ISR. This\r
+ * way the same restore context function can be used when restoring the context\r
+ * saved from the ISR or that saved from a call to vPortYieldProcessor.\r
+ */\r
+void vPortYieldProcessor( void )\r
+{\r
+ /* Within an IRQ ISR the link register has an offset from the true return \r
+ address, but an SWI ISR does not. Add the offset manually so the same \r
+ ISR return code can be used in both cases. */\r
+ asm volatile ( "ADD LR, LR, #4" );\r
+\r
+ /* Perform the context switch. First save the context of the current task. */\r
+ portSAVE_CONTEXT();\r
+\r
+ /* Find the highest priority task that is ready to run. */\r
+ vTaskSwitchContext();\r
+\r
+ /* Restore the context of the new task. */\r
+ portRESTORE_CONTEXT(); \r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* \r
+ * The ISR used for the scheduler tick depends on whether the cooperative or\r
+ * the preemptive scheduler is being used.\r
+ */\r
+\r
+#if configUSE_PREEMPTION == 0\r
+\r
+ /* The cooperative scheduler requires a normal IRQ service routine to \r
+ simply increment the system tick. */\r
+ void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ")));\r
+ void vNonPreemptiveTick( void )\r
+ { \r
+ unsigned portLONG ulDummy;\r
+ \r
+ /* Increment the tick count - which may wake some tasks but as the\r
+ preemptive scheduler is not being used any woken task is not given\r
+ processor time no matter what its priority. */\r
+ vTaskIncrementTick();\r
+ \r
+ /* Clear the PIT interrupt. */\r
+ ulDummy = AT91C_BASE_PITC->PITC_PIVR;\r
+ \r
+ /* End the interrupt in the AIC. */\r
+ AT91C_BASE_AIC->AIC_EOICR = ulDummy;\r
+ }\r
+\r
+#else\r
+\r
+ /* The preemptive scheduler is defined as "naked" as the full context is\r
+ saved on entry as part of the context switch. */\r
+ void vPreemptiveTick( void ) __attribute__((naked));\r
+ void vPreemptiveTick( void )\r
+ {\r
+ /* Save the context of the current task. */\r
+ portSAVE_CONTEXT(); \r
+\r
+ /* Increment the tick count - this may wake a task. */\r
+ vTaskIncrementTick();\r
+\r
+ /* Find the highest priority task that is ready to run. */\r
+ vTaskSwitchContext();\r
+ \r
+ /* End the interrupt in the AIC. */\r
+ AT91C_BASE_AIC->AIC_EOICR = AT91C_BASE_PITC->PITC_PIVR;;\r
+ \r
+ portRESTORE_CONTEXT();\r
+ }\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The interrupt management utilities can only be called from ARM mode. When\r
+ * THUMB_INTERWORK is defined the utilities are defined as functions here to\r
+ * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then\r
+ * the utilities are defined as macros in portmacro.h - as per other ports.\r
+ */\r
+void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));\r
+void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));\r
+\r
+void vPortDisableInterruptsFromThumb( void )\r
+{\r
+ asm volatile ( \r
+ "STMDB SP!, {R0} \n\t" /* Push R0. */\r
+ "MRS R0, CPSR \n\t" /* Get CPSR. */\r
+ "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */\r
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */\r
+ "LDMIA SP!, {R0} \n\t" /* Pop R0. */\r
+ "BX R14" ); /* Return back to thumb. */\r
+}\r
+ \r
+void vPortEnableInterruptsFromThumb( void )\r
+{\r
+ asm volatile ( \r
+ "STMDB SP!, {R0} \n\t" /* Push R0. */ \r
+ "MRS R0, CPSR \n\t" /* Get CPSR. */ \r
+ "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \r
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */ \r
+ "LDMIA SP!, {R0} \n\t" /* Pop R0. */\r
+ "BX R14" ); /* Return back to thumb. */\r
+}\r
+\r
+\r
+/* The code generated by the GCC compiler uses the stack in different ways at\r
+different optimisation levels. The interrupt flags can therefore not always\r
+be saved to the stack. Instead the critical section nesting level is stored\r
+in a variable, which is then saved as part of the stack context. */\r
+void vPortEnterCritical( void )\r
+{\r
+ /* Disable interrupts as per portDISABLE_INTERRUPTS(); */\r
+ asm volatile ( \r
+ "STMDB SP!, {R0} \n\t" /* Push R0. */\r
+ "MRS R0, CPSR \n\t" /* Get CPSR. */\r
+ "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */\r
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */\r
+ "LDMIA SP!, {R0}" ); /* Pop R0. */\r
+\r
+ /* Now interrupts are disabled ulCriticalNesting can be accessed \r
+ directly. Increment ulCriticalNesting to keep a count of how many times\r
+ portENTER_CRITICAL() has been called. */\r
+ ulCriticalNesting++;\r
+}\r
+\r
+void vPortExitCritical( void )\r
+{\r
+ if( ulCriticalNesting > portNO_CRITICAL_NESTING )\r
+ {\r
+ /* Decrement the nesting count as we are leaving a critical section. */\r
+ ulCriticalNesting--;\r
+\r
+ /* If the nesting level has reached zero then interrupts should be\r
+ re-enabled. */\r
+ if( ulCriticalNesting == portNO_CRITICAL_NESTING )\r
+ {\r
+ /* Enable interrupts as per portEXIT_CRITICAL(). */\r
+ asm volatile ( \r
+ "STMDB SP!, {R0} \n\t" /* Push R0. */ \r
+ "MRS R0, CPSR \n\t" /* Get CPSR. */ \r
+ "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \r
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */ \r
+ "LDMIA SP!, {R0}" ); /* Pop R0. */\r
+ }\r
+ }\r
+}\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+ Changes from V3.2.3\r
+ \r
+ + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1.\r
+\r
+ Changes from V3.2.4\r
+\r
+ + Removed the use of the %0 parameter within the assembler macros and \r
+ replaced them with hard coded registers. This will ensure the\r
+ assembler does not select the link register as the temp register as\r
+ was occasionally happening previously.\r
+\r
+ + The assembler statements are now included in a single asm block rather\r
+ than each line having its own asm block.\r
+*/\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Port specific definitions. \r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the\r
+ * given hardware and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *-----------------------------------------------------------\r
+ */\r
+\r
+/* Type definitions. */\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE double\r
+#define portLONG long\r
+#define portSHORT short\r
+#define portSTACK_TYPE unsigned portLONG\r
+#define portBASE_TYPE portLONG\r
+\r
+#if( configUSE_16_BIT_TICKS == 1 )\r
+ typedef unsigned portSHORT portTickType;\r
+ #define portMAX_DELAY ( portTickType ) 0xffff\r
+#else\r
+ typedef unsigned portLONG portTickType;\r
+ #define portMAX_DELAY ( portTickType ) 0xffffffff\r
+#endif\r
+/*-----------------------------------------------------------*/ \r
+\r
+/* Architecture specifics. */\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) \r
+#define portBYTE_ALIGNMENT 4\r
+#define portNOP() asm volatile ( "NOP" );\r
+/*-----------------------------------------------------------*/ \r
+\r
+\r
+/* Scheduler utilities. */\r
+\r
+/*\r
+ * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR\r
+ * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but\r
+ * are included here for efficiency. An attempt to call one from\r
+ * THUMB mode code will result in a compile time error.\r
+ */\r
+\r
+#define portRESTORE_CONTEXT() \\r
+{ \\r
+extern volatile void * volatile pxCurrentTCB; \\r
+extern volatile unsigned portLONG ulCriticalNesting; \\r
+ \\r
+ /* Set the LR to the task stack. */ \\r
+ asm volatile ( \\r
+ "LDR R0, =pxCurrentTCB \n\t" \\r
+ "LDR R0, [R0] \n\t" \\r
+ "LDR LR, [R0] \n\t" \\r
+ \\r
+ /* The critical nesting depth is the first item on the stack. */ \\r
+ /* Load it into the ulCriticalNesting variable. */ \\r
+ "LDR R0, =ulCriticalNesting \n\t" \\r
+ "LDMFD LR!, {R1} \n\t" \\r
+ "STR R1, [R0] \n\t" \\r
+ \\r
+ /* Get the SPSR from the stack. */ \\r
+ "LDMFD LR!, {R0} \n\t" \\r
+ "MSR SPSR, R0 \n\t" \\r
+ \\r
+ /* Restore all system mode registers for the task. */ \\r
+ "LDMFD LR, {R0-R14}^ \n\t" \\r
+ "NOP \n\t" \\r
+ \\r
+ /* Restore the return address. */ \\r
+ "LDR LR, [LR, #+60] \n\t" \\r
+ \\r
+ /* And return - correcting the offset in the LR to obtain the */ \\r
+ /* correct address. */ \\r
+ "SUBS PC, LR, #4 \n\t" \\r
+ ); \\r
+ ( void ) ulCriticalNesting; \\r
+ ( void ) pxCurrentTCB; \\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#define portSAVE_CONTEXT() \\r
+{ \\r
+extern volatile void * volatile pxCurrentTCB; \\r
+extern volatile unsigned portLONG ulCriticalNesting; \\r
+ \\r
+ /* Push R0 as we are going to use the register. */ \\r
+ asm volatile ( \\r
+ "STMDB SP!, {R0} \n\t" \\r
+ \\r
+ /* Set R0 to point to the task stack pointer. */ \\r
+ "STMDB SP,{SP}^ \n\t" \\r
+ "NOP \n\t" \\r
+ "SUB SP, SP, #4 \n\t" \\r
+ "LDMIA SP!,{R0} \n\t" \\r
+ \\r
+ /* Push the return address onto the stack. */ \\r
+ "STMDB R0!, {LR} \n\t" \\r
+ \\r
+ /* Now we have saved LR we can use it instead of R0. */ \\r
+ "MOV LR, R0 \n\t" \\r
+ \\r
+ /* Pop R0 so we can save it onto the system mode stack. */ \\r
+ "LDMIA SP!, {R0} \n\t" \\r
+ \\r
+ /* Push all the system mode registers onto the task stack. */ \\r
+ "STMDB LR,{R0-LR}^ \n\t" \\r
+ "NOP \n\t" \\r
+ "SUB LR, LR, #60 \n\t" \\r
+ \\r
+ /* Push the SPSR onto the task stack. */ \\r
+ "MRS R0, SPSR \n\t" \\r
+ "STMDB LR!, {R0} \n\t" \\r
+ \\r
+ "LDR R0, =ulCriticalNesting \n\t" \\r
+ "LDR R0, [R0] \n\t" \\r
+ "STMDB LR!, {R0} \n\t" \\r
+ \\r
+ /* Store the new top of stack for the task. */ \\r
+ "LDR R0, =pxCurrentTCB \n\t" \\r
+ "LDR R0, [R0] \n\t" \\r
+ "STR LR, [R0] \n\t" \\r
+ ); \\r
+ ( void ) ulCriticalNesting; \\r
+ ( void ) pxCurrentTCB; \\r
+}\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ * ISR entry and exit macros. These are only required if a task switch\r
+ * is required from the ISR.\r
+ *----------------------------------------------------------*/\r
+\r
+\r
+#define portENTER_SWITCHING_ISR() \\r
+ /* Save the context of the interrupted task. */ \\r
+ portSAVE_CONTEXT(); \\r
+ \\r
+ /* We don't know the stack requirements for the ISR, so the frame */\\r
+ /* pointer will be set to the top of the task stack, and the stack*/\\r
+ /* pointer left where it is. The IRQ stack will get used for any */\\r
+ /* functions calls made by this ISR. */ \\r
+ asm volatile ( "SUB R11, LR, #4" ); \\r
+ {\r
+\r
+#define portEXIT_SWITCHING_ISR( SwitchRequired ) \\r
+ /* If a switch is required then we just need to call */ \\r
+ /* vTaskSwitchContext() as the context has already been */ \\r
+ /* saved. */ \\r
+ if( SwitchRequired ) \\r
+ { \\r
+ vTaskSwitchContext(); \\r
+ } \\r
+ } \\r
+ /* Restore the context of which ever task is now the highest */ \\r
+ /* priority that is ready to run. */ \\r
+ portRESTORE_CONTEXT();\r
+\r
+#define portYIELD() asm volatile ( "SWI" ); \r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+/* Critical section management. */\r
+\r
+/*\r
+ * The interrupt management utilities can only be called from ARM mode. When\r
+ * THUMB_INTERWORK is defined the utilities are defined as functions in \r
+ * portISR.c to ensure a switch to ARM mode. When THUMB_INTERWORK is not \r
+ * defined then the utilities are defined as macros here - as per other ports.\r
+ */\r
+\r
+#ifdef THUMB_INTERWORK\r
+\r
+ extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));\r
+ extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));\r
+\r
+ #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb()\r
+ #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb()\r
+ \r
+#else\r
+\r
+ #define portDISABLE_INTERRUPTS() \\r
+ #define portDISABLE_INTERRUPTS() \\r
+ asm volatile ( \\r
+ "STMDB SP!, {R0} \n\t" /* Push R0. */ \\r
+ "MRS R0, CPSR \n\t" /* Get CPSR. */ \\r
+ "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \\r
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */ \\r
+ "LDMIA SP!, {R0} " ) /* Pop R0. */\r
+ \r
+ #define portENABLE_INTERRUPTS() \\r
+ asm volatile ( \\r
+ "STMDB SP!, {R0} \n\t" /* Push R0. */ \\r
+ "MRS R0, CPSR \n\t" /* Get CPSR. */ \\r
+ "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \\r
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */ \\r
+ "LDMIA SP!, {R0} " ) /* Pop R0. */\r
+\r
+#endif /* THUMB_INTERWORK */\r
+\r
+extern void vPortEnterCritical( void );\r
+extern void vPortExitCritical( void );\r
+\r
+#define portENTER_CRITICAL() vPortEnterCritical();\r
+#define portEXIT_CRITICAL() vPortExitCritical();\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Task function macros as described on the FreeRTOS.org WEB site. */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+\r
+#endif /* PORTMACRO_H */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ * Implementation of functions defined in portable.h for the ARM7 port.\r
+ *\r
+ * Components that can be compiled to either ARM or THUMB mode are\r
+ * contained in this file. The ISR routines, which can only be compiled\r
+ * to ARM mode are contained in portISR.c.\r
+ *----------------------------------------------------------*/\r
+\r
+/*\r
+ Changes from V2.5.2\r
+ \r
+ + ulCriticalNesting is now saved as part of the task context, as is \r
+ therefore added to the initial task stack during pxPortInitialiseStack.\r
+\r
+ Changes from V3.2.2\r
+\r
+ + Bug fix - The prescale value for the timer setup is now written to T0_PR \r
+ instead of T0_PC. This bug would have had no effect unless a prescale \r
+ value was actually used.\r
+*/\r
+\r
+\r
+/* Standard includes. */\r
+#include <stdlib.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Constants required to setup the task context. */\r
+#define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */\r
+#define portTHUMB_MODE_BIT ( ( portSTACK_TYPE ) 0x20 )\r
+#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 )\r
+#define portNO_CRITICAL_SECTION_NESTING ( ( portSTACK_TYPE ) 0 )\r
+\r
+/* Constants required to setup the tick ISR. */\r
+#define portENABLE_TIMER ( ( unsigned portCHAR ) 0x01 )\r
+#define portPRESCALE_VALUE 0x00\r
+#define portINTERRUPT_ON_MATCH ( ( unsigned portLONG ) 0x01 )\r
+#define portRESET_COUNT_ON_MATCH ( ( unsigned portLONG ) 0x02 )\r
+\r
+/* Constants required to setup the VIC for the tick ISR. */\r
+#define portTIMER_VIC_CHANNEL ( ( unsigned portLONG ) 0x0004 )\r
+#define portTIMER_VIC_CHANNEL_BIT ( ( unsigned portLONG ) 0x0010 )\r
+#define portTIMER_VIC_ENABLE ( ( unsigned portLONG ) 0x0020 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Setup the timer to generate the tick interrupts. */\r
+static void prvSetupTimerInterrupt( void );\r
+\r
+/* \r
+ * The scheduler can only be started from ARM mode, so \r
+ * vPortISRStartFirstSTask() is defined in portISR.c. \r
+ */\r
+extern void vPortISRStartFirstTask( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* \r
+ * Initialise the stack of a task to look exactly as if a call to \r
+ * portSAVE_CONTEXT had been called.\r
+ *\r
+ * See header file for description. \r
+ */\r
+portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
+{\r
+portSTACK_TYPE *pxOriginalTOS;\r
+\r
+ pxOriginalTOS = pxTopOfStack;\r
+\r
+ /* Setup the initial stack of the task. The stack is set exactly as \r
+ expected by the portRESTORE_CONTEXT() macro. */\r
+\r
+ /* First on the stack is the return address - which in this case is the\r
+ start of the task. The offset is added to make the return address appear\r
+ as it would within an IRQ ISR. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; \r
+ pxTopOfStack--;\r
+\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */\r
+ pxTopOfStack--; \r
+\r
+ /* When the task starts is will expect to find the function parameter in\r
+ R0. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */\r
+ pxTopOfStack--;\r
+\r
+ /* The last thing onto the stack is the status register, which is set for\r
+ system mode, with interrupts enabled. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR;\r
+\r
+ #ifdef THUMB_INTERWORK\r
+ {\r
+ /* We want the task to start in thumb mode. */\r
+ *pxTopOfStack |= portTHUMB_MODE_BIT;\r
+ }\r
+ #endif\r
+\r
+ pxTopOfStack--;\r
+\r
+ /* Some optimisation levels use the stack differently to others. This \r
+ means the interrupt flags cannot always be stored on the stack and will\r
+ instead be stored in a variable, which is then saved as part of the\r
+ tasks context. */\r
+ *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;\r
+\r
+ return pxTopOfStack;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portBASE_TYPE xPortStartScheduler( void )\r
+{\r
+ /* Start the timer that generates the tick ISR. Interrupts are disabled\r
+ here already. */\r
+ prvSetupTimerInterrupt();\r
+\r
+ /* Start the first task. */\r
+ vPortISRStartFirstTask(); \r
+\r
+ /* Should not get here! */\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEndScheduler( void )\r
+{\r
+ /* It is unlikely that the ARM port will require this function as there\r
+ is nothing to return to. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Setup the timer 0 to generate the tick interrupts at the required frequency.\r
+ */\r
+static void prvSetupTimerInterrupt( void )\r
+{\r
+unsigned portLONG ulCompareMatch;\r
+\r
+ /* A 1ms tick does not require the use of the timer prescale. This is\r
+ defaulted to zero but can be used if necessary. */\r
+ T0_PR = portPRESCALE_VALUE;\r
+\r
+ /* Calculate the match value required for our wanted tick rate. */\r
+ ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;\r
+\r
+ /* Protect against divide by zero. Using an if() statement still results\r
+ in a warning - hence the #if. */\r
+ #if portPRESCALE_VALUE != 0\r
+ {\r
+ ulCompareMatch /= ( portPRESCALE_VALUE + 1 );\r
+ }\r
+ #endif\r
+ T0_MR0 = ulCompareMatch;\r
+\r
+ /* Generate tick with timer 0 compare match. */\r
+ T0_MCR = portRESET_COUNT_ON_MATCH | portINTERRUPT_ON_MATCH;\r
+\r
+ /* Setup the VIC for the timer. */\r
+ VICIntSelect &= ~( portTIMER_VIC_CHANNEL_BIT );\r
+ VICIntEnable |= portTIMER_VIC_CHANNEL_BIT;\r
+ \r
+ /* The ISR installed depends on whether the preemptive or cooperative\r
+ scheduler is being used. */\r
+ #if configUSE_PREEMPTION == 1\r
+ {\r
+ extern void ( vPreemptiveTick )( void );\r
+ VICVectAddr0 = ( portLONG ) vPreemptiveTick;\r
+ }\r
+ #else\r
+ {\r
+ extern void ( vNonPreemptiveTick )( void );\r
+ VICVectAddr0 = ( portLONG ) vNonPreemptiveTick;\r
+ }\r
+ #endif\r
+\r
+ VICVectCntl0 = portTIMER_VIC_CHANNEL | portTIMER_VIC_ENABLE;\r
+\r
+ /* Start the timer - interrupts are disabled when this function is called\r
+ so it is okay to do this here. */\r
+ T0_TCR = portENABLE_TIMER;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ * Components that can be compiled to either ARM or THUMB mode are\r
+ * contained in port.c The ISR routines, which can only be compiled\r
+ * to ARM mode, are contained in this file.\r
+ *----------------------------------------------------------*/\r
+\r
+/*\r
+ Changes from V2.5.2\r
+ \r
+ + The critical section management functions have been changed. These no\r
+ longer modify the stack and are safe to use at all optimisation levels.\r
+ The functions are now also the same for both ARM and THUMB modes.\r
+\r
+ Changes from V2.6.0\r
+\r
+ + Removed the 'static' from the definition of vNonPreemptiveTick() to \r
+ allow the demo to link when using the cooperative scheduler.\r
+\r
+ Changes from V3.2.4\r
+\r
+ + The assembler statements are now included in a single asm block rather\r
+ than each line having its own asm block.\r
+*/\r
+\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Constants required to handle interrupts. */\r
+#define portTIMER_MATCH_ISR_BIT ( ( unsigned portCHAR ) 0x01 )\r
+#define portCLEAR_VIC_INTERRUPT ( ( unsigned portLONG ) 0 )\r
+\r
+/* Constants required to handle critical sections. */\r
+#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 )\r
+volatile unsigned portLONG ulCriticalNesting = 9999UL;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* ISR to handle manual context switches (from a call to taskYIELD()). */\r
+void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));\r
+\r
+/* \r
+ * The scheduler can only be started from ARM mode, hence the inclusion of this\r
+ * function here.\r
+ */\r
+void vPortISRStartFirstTask( void );\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortISRStartFirstTask( void )\r
+{\r
+ /* Simply start the scheduler. This is included here as it can only be\r
+ called from ARM mode. */\r
+ portRESTORE_CONTEXT();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Called by portYIELD() or taskYIELD() to manually force a context switch.\r
+ *\r
+ * When a context switch is performed from the task level the saved task \r
+ * context is made to look as if it occurred from within the tick ISR. This\r
+ * way the same restore context function can be used when restoring the context\r
+ * saved from the ISR or that saved from a call to vPortYieldProcessor.\r
+ */\r
+void vPortYieldProcessor( void )\r
+{\r
+ /* Within an IRQ ISR the link register has an offset from the true return \r
+ address, but an SWI ISR does not. Add the offset manually so the same \r
+ ISR return code can be used in both cases. */\r
+ asm volatile ( "ADD LR, LR, #4" );\r
+\r
+ /* Perform the context switch. First save the context of the current task. */\r
+ portSAVE_CONTEXT();\r
+\r
+ /* Find the highest priority task that is ready to run. */\r
+ vTaskSwitchContext();\r
+\r
+ /* Restore the context of the new task. */\r
+ portRESTORE_CONTEXT(); \r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* \r
+ * The ISR used for the scheduler tick depends on whether the cooperative or\r
+ * the preemptive scheduler is being used.\r
+ */\r
+\r
+#if configUSE_PREEMPTION == 0\r
+\r
+ /* The cooperative scheduler requires a normal IRQ service routine to \r
+ simply increment the system tick. */\r
+ void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ")));\r
+ void vNonPreemptiveTick( void )\r
+ { \r
+ vTaskIncrementTick();\r
+ T0_IR = portTIMER_MATCH_ISR_BIT;\r
+ VICVectAddr = portCLEAR_VIC_INTERRUPT;\r
+ }\r
+\r
+#else\r
+\r
+ /* The preemptive scheduler is defined as "naked" as the full context is\r
+ saved on entry as part of the context switch. */\r
+ void vPreemptiveTick( void ) __attribute__((naked));\r
+ void vPreemptiveTick( void )\r
+ {\r
+ /* Save the context of the interrupted task. */\r
+ portSAVE_CONTEXT(); \r
+\r
+ /* Increment the RTOS tick count, then look for the highest priority \r
+ task that is ready to run. */\r
+ vTaskIncrementTick();\r
+ vTaskSwitchContext();\r
+\r
+ /* Ready for the next interrupt. */\r
+ T0_IR = portTIMER_MATCH_ISR_BIT;\r
+ VICVectAddr = portCLEAR_VIC_INTERRUPT;\r
+ \r
+ /* Restore the context of the new task. */\r
+ portRESTORE_CONTEXT();\r
+ }\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The interrupt management utilities can only be called from ARM mode. When\r
+ * THUMB_INTERWORK is defined the utilities are defined as functions here to\r
+ * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then\r
+ * the utilities are defined as macros in portmacro.h - as per other ports.\r
+ */\r
+#ifdef THUMB_INTERWORK\r
+\r
+ void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));\r
+ void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));\r
+\r
+ void vPortDisableInterruptsFromThumb( void )\r
+ {\r
+ asm volatile ( \r
+ "STMDB SP!, {R0} \n\t" /* Push R0. */\r
+ "MRS R0, CPSR \n\t" /* Get CPSR. */\r
+ "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */\r
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */\r
+ "LDMIA SP!, {R0} \n\t" /* Pop R0. */\r
+ "BX R14" ); /* Return back to thumb. */\r
+ }\r
+ \r
+ void vPortEnableInterruptsFromThumb( void )\r
+ {\r
+ asm volatile ( \r
+ "STMDB SP!, {R0} \n\t" /* Push R0. */ \r
+ "MRS R0, CPSR \n\t" /* Get CPSR. */ \r
+ "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \r
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */ \r
+ "LDMIA SP!, {R0} \n\t" /* Pop R0. */\r
+ "BX R14" ); /* Return back to thumb. */\r
+ }\r
+\r
+#endif /* THUMB_INTERWORK */\r
+\r
+/* The code generated by the GCC compiler uses the stack in different ways at\r
+different optimisation levels. The interrupt flags can therefore not always\r
+be saved to the stack. Instead the critical section nesting level is stored\r
+in a variable, which is then saved as part of the stack context. */\r
+void vPortEnterCritical( void )\r
+{\r
+ /* Disable interrupts as per portDISABLE_INTERRUPTS(); */\r
+ asm volatile ( \r
+ "STMDB SP!, {R0} \n\t" /* Push R0. */\r
+ "MRS R0, CPSR \n\t" /* Get CPSR. */\r
+ "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */\r
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */\r
+ "LDMIA SP!, {R0}" ); /* Pop R0. */\r
+\r
+ /* Now interrupts are disabled ulCriticalNesting can be accessed \r
+ directly. Increment ulCriticalNesting to keep a count of how many times\r
+ portENTER_CRITICAL() has been called. */\r
+ ulCriticalNesting++;\r
+}\r
+\r
+void vPortExitCritical( void )\r
+{\r
+ if( ulCriticalNesting > portNO_CRITICAL_NESTING )\r
+ {\r
+ /* Decrement the nesting count as we are leaving a critical section. */\r
+ ulCriticalNesting--;\r
+\r
+ /* If the nesting level has reached zero then interrupts should be\r
+ re-enabled. */\r
+ if( ulCriticalNesting == portNO_CRITICAL_NESTING )\r
+ {\r
+ /* Enable interrupts as per portEXIT_CRITICAL(). */\r
+ asm volatile ( \r
+ "STMDB SP!, {R0} \n\t" /* Push R0. */ \r
+ "MRS R0, CPSR \n\t" /* Get CPSR. */ \r
+ "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \r
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */ \r
+ "LDMIA SP!, {R0}" ); /* Pop R0. */\r
+ }\r
+ }\r
+}\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+ Changes from V3.2.3\r
+ \r
+ + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1.\r
+\r
+ Changes from V3.2.4\r
+\r
+ + Removed the use of the %0 parameter within the assembler macros and \r
+ replaced them with hard coded registers. This will ensure the\r
+ assembler does not select the link register as the temp register as\r
+ was occasionally happening previously.\r
+\r
+ + The assembler statements are now included in a single asm block rather\r
+ than each line having its own asm block.\r
+*/\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Port specific definitions. \r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the\r
+ * given hardware and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *-----------------------------------------------------------\r
+ */\r
+\r
+/* Type definitions. */\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE double\r
+#define portLONG long\r
+#define portSHORT short\r
+#define portSTACK_TYPE unsigned portLONG\r
+#define portBASE_TYPE portLONG\r
+\r
+#if( configUSE_16_BIT_TICKS == 1 )\r
+ typedef unsigned portSHORT portTickType;\r
+ #define portMAX_DELAY ( portTickType ) 0xffff\r
+#else\r
+ typedef unsigned portLONG portTickType;\r
+ #define portMAX_DELAY ( portTickType ) 0xffffffff\r
+#endif\r
+/*-----------------------------------------------------------*/ \r
+\r
+/* Architecture specifics. */\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) \r
+#define portBYTE_ALIGNMENT 4\r
+#define portNOP() asm volatile ( "NOP" );\r
+/*-----------------------------------------------------------*/ \r
+\r
+\r
+/* Scheduler utilities. */\r
+\r
+/*\r
+ * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR\r
+ * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but\r
+ * are included here for efficiency. An attempt to call one from\r
+ * THUMB mode code will result in a compile time error.\r
+ */\r
+\r
+#define portRESTORE_CONTEXT() \\r
+{ \\r
+extern volatile void * volatile pxCurrentTCB; \\r
+extern volatile unsigned portLONG ulCriticalNesting; \\r
+ \\r
+ /* Set the LR to the task stack. */ \\r
+ asm volatile ( \\r
+ "LDR R0, =pxCurrentTCB \n\t" \\r
+ "LDR R0, [R0] \n\t" \\r
+ "LDR LR, [R0] \n\t" \\r
+ \\r
+ /* The critical nesting depth is the first item on the stack. */ \\r
+ /* Load it into the ulCriticalNesting variable. */ \\r
+ "LDR R0, =ulCriticalNesting \n\t" \\r
+ "LDMFD LR!, {R1} \n\t" \\r
+ "STR R1, [R0] \n\t" \\r
+ \\r
+ /* Get the SPSR from the stack. */ \\r
+ "LDMFD LR!, {R0} \n\t" \\r
+ "MSR SPSR, R0 \n\t" \\r
+ \\r
+ /* Restore all system mode registers for the task. */ \\r
+ "LDMFD LR, {R0-R14}^ \n\t" \\r
+ "NOP \n\t" \\r
+ \\r
+ /* Restore the return address. */ \\r
+ "LDR LR, [LR, #+60] \n\t" \\r
+ \\r
+ /* And return - correcting the offset in the LR to obtain the */ \\r
+ /* correct address. */ \\r
+ "SUBS PC, LR, #4 \n\t" \\r
+ ); \\r
+ ( void ) ulCriticalNesting; \\r
+ ( void ) pxCurrentTCB; \\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#define portSAVE_CONTEXT() \\r
+{ \\r
+extern volatile void * volatile pxCurrentTCB; \\r
+extern volatile unsigned portLONG ulCriticalNesting; \\r
+ \\r
+ /* Push R0 as we are going to use the register. */ \\r
+ asm volatile ( \\r
+ "STMDB SP!, {R0} \n\t" \\r
+ \\r
+ /* Set R0 to point to the task stack pointer. */ \\r
+ "STMDB SP,{SP}^ \n\t" \\r
+ "NOP \n\t" \\r
+ "SUB SP, SP, #4 \n\t" \\r
+ "LDMIA SP!,{R0} \n\t" \\r
+ \\r
+ /* Push the return address onto the stack. */ \\r
+ "STMDB R0!, {LR} \n\t" \\r
+ \\r
+ /* Now we have saved LR we can use it instead of R0. */ \\r
+ "MOV LR, R0 \n\t" \\r
+ \\r
+ /* Pop R0 so we can save it onto the system mode stack. */ \\r
+ "LDMIA SP!, {R0} \n\t" \\r
+ \\r
+ /* Push all the system mode registers onto the task stack. */ \\r
+ "STMDB LR,{R0-LR}^ \n\t" \\r
+ "NOP \n\t" \\r
+ "SUB LR, LR, #60 \n\t" \\r
+ \\r
+ /* Push the SPSR onto the task stack. */ \\r
+ "MRS R0, SPSR \n\t" \\r
+ "STMDB LR!, {R0} \n\t" \\r
+ \\r
+ "LDR R0, =ulCriticalNesting \n\t" \\r
+ "LDR R0, [R0] \n\t" \\r
+ "STMDB LR!, {R0} \n\t" \\r
+ \\r
+ /* Store the new top of stack for the task. */ \\r
+ "LDR R0, =pxCurrentTCB \n\t" \\r
+ "LDR R0, [R0] \n\t" \\r
+ "STR LR, [R0] \n\t" \\r
+ ); \\r
+ ( void ) ulCriticalNesting; \\r
+ ( void ) pxCurrentTCB; \\r
+}\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ * ISR entry and exit macros. These are only required if a task switch\r
+ * is required from the ISR.\r
+ *----------------------------------------------------------*/\r
+\r
+\r
+#define portENTER_SWITCHING_ISR() \\r
+ /* Save the context of the interrupted task. */ \\r
+ portSAVE_CONTEXT(); \\r
+ \\r
+ /* We don't know the stack requirements for the ISR, so the frame */\\r
+ /* pointer will be set to the top of the task stack, and the stack*/\\r
+ /* pointer left where it is. The IRQ stack will get used for any */\\r
+ /* functions calls made by this ISR. */ \\r
+ asm volatile ( "SUB R11, LR, #4" ); \\r
+ {\r
+\r
+#define portEXIT_SWITCHING_ISR( SwitchRequired ) \\r
+ /* If a switch is required then we just need to call */ \\r
+ /* vTaskSwitchContext() as the context has already been */ \\r
+ /* saved. */ \\r
+ if( SwitchRequired ) \\r
+ { \\r
+ vTaskSwitchContext(); \\r
+ } \\r
+ } \\r
+ /* Restore the context of which ever task is now the highest */ \\r
+ /* priority that is ready to run. */ \\r
+ portRESTORE_CONTEXT();\r
+\r
+#define portYIELD() asm volatile ( "SWI" ); \r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+/* Critical section management. */\r
+\r
+/*\r
+ * The interrupt management utilities can only be called from ARM mode. When\r
+ * THUMB_INTERWORK is defined the utilities are defined as functions in \r
+ * portISR.c to ensure a switch to ARM mode. When THUMB_INTERWORK is not \r
+ * defined then the utilities are defined as macros here - as per other ports.\r
+ */\r
+\r
+#ifdef THUMB_INTERWORK\r
+\r
+ extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));\r
+ extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));\r
+\r
+ #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb()\r
+ #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb()\r
+ \r
+#else\r
+\r
+ #define portDISABLE_INTERRUPTS() \\r
+ asm volatile ( \\r
+ "STMDB SP!, {R0} \n\t" /* Push R0. */ \\r
+ "MRS R0, CPSR \n\t" /* Get CPSR. */ \\r
+ "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \\r
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */ \\r
+ "LDMIA SP!, {R0} " ) /* Pop R0. */\r
+ \r
+ #define portENABLE_INTERRUPTS() \\r
+ asm volatile ( \\r
+ "STMDB SP!, {R0} \n\t" /* Push R0. */ \\r
+ "MRS R0, CPSR \n\t" /* Get CPSR. */ \\r
+ "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \\r
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */ \\r
+ "LDMIA SP!, {R0} " ) /* Pop R0. */\r
+\r
+#endif /* THUMB_INTERWORK */\r
+\r
+extern void vPortEnterCritical( void );\r
+extern void vPortExitCritical( void );\r
+\r
+#define portENTER_CRITICAL() vPortEnterCritical();\r
+#define portEXIT_CRITICAL() vPortExitCritical();\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Task function macros as described on the FreeRTOS.org WEB site. */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+\r
+#endif /* PORTMACRO_H */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+ Changes between V4.0.0 and V4.0.1\r
+\r
+ + Reduced the code used to setup the initial stack frame.\r
+ + The kernel no longer has to install or handle the fault interrupt.\r
+*/\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ * Implementation of functions defined in portable.h for the ARM CM3 port.\r
+ *----------------------------------------------------------*/\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Constants required to manipulate the NVIC. */\r
+#define portNVIC_SYSTICK_CTRL ( ( volatile unsigned portLONG *) 0xe000e010 )\r
+#define portNVIC_SYSTICK_LOAD ( ( volatile unsigned portLONG *) 0xe000e014 )\r
+#define portNVIC_INT_CTRL ( ( volatile unsigned portLONG *) 0xe000ed04 )\r
+#define portNVIC_SYSPRI2 ( ( volatile unsigned portLONG *) 0xe000ed20 )\r
+#define portNVIC_SYSPRI1 ( ( volatile unsigned portLONG *) 0xe000ed1c )\r
+#define portNVIC_SYSTICK_CLK 0x00000004\r
+#define portNVIC_SYSTICK_INT 0x00000002\r
+#define portNVIC_SYSTICK_ENABLE 0x00000001\r
+#define portNVIC_PENDSVSET 0x10000000\r
+#define portNVIC_PENDSV_PRI 0x00ff0000\r
+#define portNVIC_SVCALL_PRI 0xff000000\r
+#define portNVIC_SYSTICK_PRI 0xff000000\r
+\r
+/* Constants required to set up the initial stack. */\r
+#define portINITIAL_XPSR ( 0x01000000 )\r
+\r
+/* Each task maintains its own interrupt status in the critical nesting\r
+variable. */\r
+unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;\r
+\r
+/* \r
+ * Setup the timer to generate the tick interrupts.\r
+ */\r
+static void prvSetupTimerInterrupt( void );\r
+\r
+/*\r
+ * Exception handlers.\r
+ */\r
+void xPortPendSVHandler( void ) __attribute__ (( naked ));\r
+void xPortSysTickHandler( void ) __attribute__ (( naked ));\r
+\r
+/*\r
+ * Set the MSP/PSP to a known value.\r
+ */\r
+void prvSetMSP( unsigned long ulValue ) __attribute__ (( naked ));\r
+void prvSetPSP( unsigned long ulValue ) __attribute__ (( naked )); \r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* \r
+ * See header file for description. \r
+ */\r
+portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
+{\r
+ /* Simulate the stack frame as it would be created by a context switch\r
+ interrupt. */\r
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* PC */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0xfffffffd; /* LR */\r
+ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */\r
+ pxTopOfStack -= 9; /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
+ *pxTopOfStack = 0x00000000; /* uxCriticalNesting. */\r
+\r
+ return pxTopOfStack;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void prvSetPSP( unsigned long ulValue )\r
+{\r
+ asm volatile( "msr psp, r0" );\r
+ asm volatile( "bx lr" );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void prvSetMSP( unsigned long ulValue )\r
+{\r
+ asm volatile( "msr msp, r0" );\r
+ asm volatile( "bx lr" );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* \r
+ * See header file for description. \r
+ */\r
+portBASE_TYPE xPortStartScheduler( void )\r
+{\r
+ /* Make PendSV, CallSV and SysTick the lowest priority interrupts. */\r
+ *(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI;\r
+ *(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI;\r
+\r
+ /* Start the timer that generates the tick ISR. Interrupts are disabled\r
+ here already. */\r
+ prvSetupTimerInterrupt();\r
+ \r
+ /* Start the first task. */\r
+ prvSetPSP( 0 );\r
+ prvSetMSP( *((unsigned portLONG *) 0 ) );\r
+ *(portNVIC_INT_CTRL) |= portNVIC_PENDSVSET;\r
+\r
+ /* Enable interrupts */\r
+ portENABLE_INTERRUPTS();\r
+\r
+ /* Should not get here! */\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEndScheduler( void )\r
+{\r
+ /* It is unlikely that the CM3 port will require this function as there\r
+ is nothing to return to. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortYieldFromISR( void )\r
+{\r
+ /* Set a PendSV to request a context switch. */\r
+ *(portNVIC_INT_CTRL) |= portNVIC_PENDSVSET;\r
+\r
+ /* This function is also called in response to a Yield(), so we want\r
+ the yield to occur immediately. */\r
+ portENABLE_INTERRUPTS();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEnterCritical( void )\r
+{\r
+ portDISABLE_INTERRUPTS();\r
+ uxCriticalNesting++;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortExitCritical( void )\r
+{\r
+ uxCriticalNesting--;\r
+ if( uxCriticalNesting == 0 )\r
+ {\r
+ portENABLE_INTERRUPTS();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void xPortPendSVHandler( void )\r
+{\r
+ /* Start first task if the stack has not yet been setup. */\r
+ __asm volatile\r
+ ( \r
+ " mrs r0, psp \n"\r
+ " cbz r0, no_save \n"\r
+ " \n" /* Save the context into the TCB. */ \r
+ " sub r0, #0x20 \n"\r
+ " stm r0, {r4-r11} \n"\r
+ " nop \n"\r
+ " sub r0, #0x04 \n"\r
+ " ldr r1, uxCriticalNestingConst \n"\r
+ " ldr r1, [r1] \n"\r
+ " stm r0, {r1} \n"\r
+ " ldr r1, pxCurrentTCBConst \n"\r
+ " ldr r1, [r1] \n"\r
+ " str r0, [r1] \n"\r
+ " \n"\r
+ "no_save:\n" \r
+ " ldr r0, vTaskSwitchContextConst \n" /* Find the task to execute. */\r
+ " push {r14} \n"\r
+ " cpsid i \n"\r
+ " blx r0 \n"\r
+ " cpsie i \n"\r
+ " pop {r14} \n"\r
+ " \n" /* Restore the context. */ \r
+ " ldr r1, pxCurrentTCBConst \n"\r
+ " ldr r1, [r1] \n"\r
+ " ldr r0, [r1] \n"\r
+ " ldm r0, {r1, r4-r11} \n"\r
+ " nop \n"\r
+ " ldr r2, uxCriticalNestingConst \n"\r
+ " str r1, [r2] \n"\r
+ " add r0, #0x24 \n"\r
+ " msr psp, r0 \n"\r
+ " orr r14, #0xd \n"\r
+ " \n" /* Exit with interrupts in the state required by the task. */ \r
+ " cbnz r1, sv_disable_interrupts \n"\r
+ " bx r14 \n"\r
+ " \n"\r
+ "sv_disable_interrupts: \n"\r
+ " cpsid i \n"\r
+ " bx r14 \n"\r
+ " \n"\r
+ " .align 2 \n"\r
+ "vTaskSwitchContextConst: .word vTaskSwitchContext \n"\r
+ "pxCurrentTCBConst: .word pxCurrentTCB \n"\r
+ "uxCriticalNestingConst: .word uxCriticalNesting \n"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void xPortSysTickHandler( void )\r
+{\r
+ extern void vTaskIncrementTick( void );\r
+ extern void vPortYieldFromISR( void );\r
+\r
+ /* Call the scheduler tick function. */\r
+ __asm volatile\r
+ ( \r
+ " ldr r0, vTaskIncrementTickConst \n"\r
+ " push {r14} \n"\r
+ " cpsid i \n"\r
+ " blx r0 \n"\r
+ " cpsie i \n"\r
+ " pop {r14}" \r
+ );\r
+\r
+ /* If using preemption, also force a context switch. */\r
+ #if configUSE_PREEMPTION == 1\r
+ __asm volatile\r
+ ( \r
+ " push {r14} \n"\r
+ " ldr r0, vPortYieldFromISRConst2 \n"\r
+ " blx r0 \n"\r
+ " pop {r14}" \r
+ );\r
+ #endif\r
+\r
+ /* Exit with interrupts in the correct state. */\r
+ __asm volatile\r
+ (\r
+ " ldr r2, uxCriticalNestingConst2 \n" \r
+ " ldr r2, [r2] \n"\r
+ " cbnz r2, tick_disable_interrupts \n"\r
+ " bx r14" \r
+ );\r
+\r
+ __asm volatile\r
+ (\r
+ "tick_disable_interrupts: \n"\r
+ " cpsid i \n"\r
+ " bx r14 \n"\r
+ " \n"\r
+ " .align 2 \n"\r
+ "vPortYieldFromISRConst2: .word vPortYieldFromISR\n"\r
+ "vTaskIncrementTickConst: .word vTaskIncrementTick\n" \r
+ "uxCriticalNestingConst2: .word uxCriticalNesting"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Setup the systick timer to generate the tick interrupts at the required\r
+ * frequency.\r
+ */\r
+void prvSetupTimerInterrupt( void )\r
+{\r
+ /* Configure SysTick to interrupt at the requested rate. */\r
+ *(portNVIC_SYSTICK_LOAD) = configCPU_CLOCK_HZ / configTICK_RATE_HZ;\r
+ *(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;\r
+}\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Port specific definitions. \r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the\r
+ * given hardware and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *-----------------------------------------------------------\r
+ */\r
+\r
+/* Type definitions. */\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE double\r
+#define portLONG long\r
+#define portSHORT short\r
+#define portSTACK_TYPE unsigned portLONG\r
+#define portBASE_TYPE long\r
+\r
+#if( configUSE_16_BIT_TICKS == 1 )\r
+ typedef unsigned portSHORT portTickType;\r
+ #define portMAX_DELAY ( portTickType ) 0xffff\r
+#else\r
+ typedef unsigned portLONG portTickType;\r
+ #define portMAX_DELAY ( portTickType ) 0xffffffff\r
+#endif\r
+/*-----------------------------------------------------------*/ \r
+\r
+/* Architecture specifics. */\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) \r
+#define portBYTE_ALIGNMENT 4\r
+/*-----------------------------------------------------------*/ \r
+\r
+\r
+/* Scheduler utilities. */\r
+extern void vPortYieldFromISR( void );\r
+\r
+#define portYIELD() vPortYieldFromISR()\r
+\r
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) vPortYieldFromISR()\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+/* Critical section management. */\r
+\r
+extern void vPortEnableInterrupts( void );\r
+extern void vPortEnterCritical( void );\r
+extern void vPortExitCritical( void );\r
+\r
+#define portDISABLE_INTERRUPTS() __asm volatile( "cpsid i" )\r
+#define portENABLE_INTERRUPTS() __asm volatile( "cpsie i" )\r
+#define portENTER_CRITICAL() vPortEnterCritical()\r
+#define portEXIT_CRITICAL() vPortExitCritical()\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Task function macros as described on the FreeRTOS.org WEB site. */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+\r
+#define inline\r
+#define portNOP()\r
+\r
+#endif /* PORTMACRO_H */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* \r
+\r
+Changes from V2.6.0\r
+\r
+ + AVR port - Replaced the inb() and outb() functions with direct memory\r
+ access. This allows the port to be built with the 20050414 build of\r
+ WinAVR.\r
+*/\r
+\r
+#include <stdlib.h>\r
+#include <avr/interrupt.h>\r
+\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/*-----------------------------------------------------------\r
+ * Implementation of functions defined in portable.h for the AVR port.\r
+ *----------------------------------------------------------*/\r
+\r
+/* Start tasks with interrupts enables. */\r
+#define portFLAGS_INT_ENABLED ( ( portSTACK_TYPE ) 0x80 )\r
+\r
+/* Hardware constants for timer 1. */\r
+#define portCLEAR_COUNTER_ON_MATCH ( ( unsigned portCHAR ) 0x08 )\r
+#define portPRESCALE_64 ( ( unsigned portCHAR ) 0x03 )\r
+#define portCLOCK_PRESCALER ( ( unsigned portLONG ) 64 )\r
+#define portCOMPARE_MATCH_A_INTERRUPT_ENABLE ( ( unsigned portCHAR ) 0x10 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* We require the address of the pxCurrentTCB variable, but don't want to know\r
+any details of its type. */\r
+typedef void tskTCB;\r
+extern volatile tskTCB * volatile pxCurrentTCB;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* \r
+ * Macro to save all the general purpose registers, the save the stack pointer\r
+ * into the TCB. \r
+ * \r
+ * The first thing we do is save the flags then disable interrupts. This is to \r
+ * guard our stack against having a context switch interrupt after we have already \r
+ * pushed the registers onto the stack - causing the 32 registers to be on the \r
+ * stack twice. \r
+ * \r
+ * r1 is set to zero as the compiler expects it to be thus, however some\r
+ * of the math routines make use of R1. \r
+ * \r
+ * The interrupts will have been disabled during the call to portSAVE_CONTEXT()\r
+ * so we need not worry about reading/writing to the stack pointer. \r
+ */\r
+\r
+#define portSAVE_CONTEXT() \\r
+ asm volatile ( "push r0 \n\t" \\r
+ "in r0, __SREG__ \n\t" \\r
+ "cli \n\t" \\r
+ "push r0 \n\t" \\r
+ "push r1 \n\t" \\r
+ "clr r1 \n\t" \\r
+ "push r2 \n\t" \\r
+ "push r3 \n\t" \\r
+ "push r4 \n\t" \\r
+ "push r5 \n\t" \\r
+ "push r6 \n\t" \\r
+ "push r7 \n\t" \\r
+ "push r8 \n\t" \\r
+ "push r9 \n\t" \\r
+ "push r10 \n\t" \\r
+ "push r11 \n\t" \\r
+ "push r12 \n\t" \\r
+ "push r13 \n\t" \\r
+ "push r14 \n\t" \\r
+ "push r15 \n\t" \\r
+ "push r16 \n\t" \\r
+ "push r17 \n\t" \\r
+ "push r18 \n\t" \\r
+ "push r19 \n\t" \\r
+ "push r20 \n\t" \\r
+ "push r21 \n\t" \\r
+ "push r22 \n\t" \\r
+ "push r23 \n\t" \\r
+ "push r24 \n\t" \\r
+ "push r25 \n\t" \\r
+ "push r26 \n\t" \\r
+ "push r27 \n\t" \\r
+ "push r28 \n\t" \\r
+ "push r29 \n\t" \\r
+ "push r30 \n\t" \\r
+ "push r31 \n\t" \\r
+ "lds r26, pxCurrentTCB \n\t" \\r
+ "lds r27, pxCurrentTCB + 1 \n\t" \\r
+ "in r0, 0x3d \n\t" \\r
+ "st x+, r0 \n\t" \\r
+ "in r0, 0x3e \n\t" \\r
+ "st x+, r0 \n\t" \\r
+ );\r
+\r
+/* \r
+ * Opposite to portSAVE_CONTEXT(). Interrupts will have been disabled during\r
+ * the context save so we can write to the stack pointer. \r
+ */\r
+\r
+#define portRESTORE_CONTEXT() \\r
+ asm volatile ( "lds r26, pxCurrentTCB \n\t" \\r
+ "lds r27, pxCurrentTCB + 1 \n\t" \\r
+ "ld r28, x+ \n\t" \\r
+ "out __SP_L__, r28 \n\t" \\r
+ "ld r29, x+ \n\t" \\r
+ "out __SP_H__, r29 \n\t" \\r
+ "pop r31 \n\t" \\r
+ "pop r30 \n\t" \\r
+ "pop r29 \n\t" \\r
+ "pop r28 \n\t" \\r
+ "pop r27 \n\t" \\r
+ "pop r26 \n\t" \\r
+ "pop r25 \n\t" \\r
+ "pop r24 \n\t" \\r
+ "pop r23 \n\t" \\r
+ "pop r22 \n\t" \\r
+ "pop r21 \n\t" \\r
+ "pop r20 \n\t" \\r
+ "pop r19 \n\t" \\r
+ "pop r18 \n\t" \\r
+ "pop r17 \n\t" \\r
+ "pop r16 \n\t" \\r
+ "pop r15 \n\t" \\r
+ "pop r14 \n\t" \\r
+ "pop r13 \n\t" \\r
+ "pop r12 \n\t" \\r
+ "pop r11 \n\t" \\r
+ "pop r10 \n\t" \\r
+ "pop r9 \n\t" \\r
+ "pop r8 \n\t" \\r
+ "pop r7 \n\t" \\r
+ "pop r6 \n\t" \\r
+ "pop r5 \n\t" \\r
+ "pop r4 \n\t" \\r
+ "pop r3 \n\t" \\r
+ "pop r2 \n\t" \\r
+ "pop r1 \n\t" \\r
+ "pop r0 \n\t" \\r
+ "out __SREG__, r0 \n\t" \\r
+ "pop r0 \n\t" \\r
+ );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Perform hardware setup to enable ticks from timer 1, compare match A.\r
+ */\r
+static void prvSetupTimerInterrupt( void );\r
+/*-----------------------------------------------------------*/\r
+\r
+/* \r
+ * See header file for description. \r
+ */\r
+portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
+{\r
+unsigned portSHORT usAddress;\r
+\r
+ /* Place a few bytes of known values on the bottom of the stack. \r
+ This is just useful for debugging. */\r
+\r
+ *pxTopOfStack = 0x11;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x22;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x33;\r
+ pxTopOfStack--;\r
+\r
+ /* Simulate how the stack would look after a call to vPortYield() generated by \r
+ the compiler. */\r
+\r
+ /*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */\r
+\r
+ /* The start of the task code will be popped off the stack last, so place\r
+ it on first. */\r
+ usAddress = ( unsigned portSHORT ) pxCode;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) ( usAddress & ( unsigned portSHORT ) 0x00ff );\r
+ pxTopOfStack--;\r
+\r
+ usAddress >>= 8;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) ( usAddress & ( unsigned portSHORT ) 0x00ff );\r
+ pxTopOfStack--;\r
+\r
+ /* Next simulate the stack as if after a call to portSAVE_CONTEXT(). \r
+ portSAVE_CONTEXT places the flags on the stack immediately after r0\r
+ to ensure the interrupts get disabled as soon as possible, and so ensuring\r
+ the stack use is minimal should a context switch interrupt occur. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* R0 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portFLAGS_INT_ENABLED;\r
+ pxTopOfStack--;\r
+\r
+\r
+ /* Now the remaining registers. The compiler expects R1 to be 0. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* R1 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x02; /* R2 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x03; /* R3 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x04; /* R4 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x05; /* R5 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x06; /* R6 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x07; /* R7 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x08; /* R8 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x09; /* R9 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x10; /* R10 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x11; /* R11 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x12; /* R12 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x13; /* R13 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x14; /* R14 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x15; /* R15 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x16; /* R16 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x17; /* R17 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x18; /* R18 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x19; /* R19 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x20; /* R20 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x21; /* R21 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x22; /* R22 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x23; /* R23 */\r
+ pxTopOfStack--;\r
+\r
+ /* Place the parameter on the stack in the expected location. */\r
+ usAddress = ( unsigned portSHORT ) pvParameters;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) ( usAddress & ( unsigned portSHORT ) 0x00ff );\r
+ pxTopOfStack--;\r
+\r
+ usAddress >>= 8;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) ( usAddress & ( unsigned portSHORT ) 0x00ff );\r
+ pxTopOfStack--;\r
+\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x26; /* R26 X */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x27; /* R27 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x28; /* R28 Y */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x29; /* R29 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x30; /* R30 Z */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x031; /* R31 */\r
+ pxTopOfStack--;\r
+\r
+ /*lint +e950 +e611 +e923 */\r
+\r
+ return pxTopOfStack;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portBASE_TYPE xPortStartScheduler( void )\r
+{\r
+ /* In this port we ignore the parameter and use the configUSE_PREEMPTION\r
+ definition instead. */\r
+\r
+ /* Setup the hardware to generate the tick. */\r
+ prvSetupTimerInterrupt();\r
+\r
+ /* Restore the context of the first task that is going to run. */\r
+ portRESTORE_CONTEXT();\r
+\r
+ /* Simulate a function call end as generated by the compiler. We will now\r
+ jump to the start of the task the context of which we have just restored. */\r
+ asm volatile ( "ret" );\r
+\r
+ /* Should not get here. */\r
+ return pdTRUE;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEndScheduler( void )\r
+{\r
+ /* It is unlikely that the AVR port will get stopped. If required simply\r
+ disable the tick interrupt here. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Manual context switch. The first thing we do is save the registers so we\r
+ * can use a naked attribute.\r
+ */\r
+void vPortYield( void ) __attribute__ ( ( naked ) );\r
+void vPortYield( void )\r
+{\r
+ portSAVE_CONTEXT();\r
+ vTaskSwitchContext();\r
+ portRESTORE_CONTEXT();\r
+\r
+ asm volatile ( "ret" );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Context switch function used by the tick. This must be identical to \r
+ * vPortYield() from the call to vTaskSwitchContext() onwards. The only\r
+ * difference from vPortYield() is the tick count is incremented as the\r
+ * call comes from the tick ISR.\r
+ */\r
+void vPortYieldFromTick( void ) __attribute__ ( ( naked ) );\r
+void vPortYieldFromTick( void )\r
+{\r
+ portSAVE_CONTEXT();\r
+ vTaskIncrementTick();\r
+ vTaskSwitchContext();\r
+ portRESTORE_CONTEXT();\r
+\r
+ asm volatile ( "ret" );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Setup timer 1 compare match A to generate a tick interrupt.\r
+ */\r
+static void prvSetupTimerInterrupt( void )\r
+{\r
+unsigned portLONG ulCompareMatch;\r
+unsigned portCHAR ucHighByte, ucLowByte;\r
+\r
+ /* Using 16bit timer 1 to generate the tick. Correct fuses must be\r
+ selected for the configCPU_CLOCK_HZ clock. */\r
+\r
+ ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;\r
+\r
+ /* We only have 16 bits so have to scale to get our required tick rate. */\r
+ ulCompareMatch /= portCLOCK_PRESCALER;\r
+\r
+ /* Adjust for correct value. */\r
+ ulCompareMatch -= ( unsigned portLONG ) 1;\r
+\r
+ /* Setup compare match value for compare match A. Interrupts are disabled \r
+ before this is called so we need not worry here. */\r
+ ucLowByte = ( unsigned portCHAR ) ( ulCompareMatch & ( unsigned portLONG ) 0xff );\r
+ ulCompareMatch >>= 8;\r
+ ucHighByte = ( unsigned portCHAR ) ( ulCompareMatch & ( unsigned portLONG ) 0xff );\r
+ OCR1AH = ucHighByte;\r
+ OCR1AL = ucLowByte;\r
+\r
+ /* Setup clock source and compare match behaviour. */\r
+ ucLowByte = portCLEAR_COUNTER_ON_MATCH | portPRESCALE_64;\r
+ TCCR1B = ucLowByte;\r
+\r
+ /* Enable the interrupt - this is okay as interrupt are currently globally\r
+ disabled. */\r
+ ucLowByte = TIMSK;\r
+ ucLowByte |= portCOMPARE_MATCH_A_INTERRUPT_ENABLE;\r
+ TIMSK = ucLowByte;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if configUSE_PREEMPTION == 1\r
+\r
+ /*\r
+ * Tick ISR for preemptive scheduler. We can use a naked attribute as\r
+ * the context is saved at the start of vPortYieldFromTick(). The tick\r
+ * count is incremented after the context is saved.\r
+ */\r
+ void SIG_OUTPUT_COMPARE1A( void ) __attribute__ ( ( signal, naked ) );\r
+ void SIG_OUTPUT_COMPARE1A( void )\r
+ {\r
+ vPortYieldFromTick();\r
+ asm volatile ( "reti" );\r
+ }\r
+#else\r
+\r
+ /*\r
+ * Tick ISR for the cooperative scheduler. All this does is increment the\r
+ * tick count. We don't need to switch context, this can only be done by\r
+ * manual calls to taskYIELD();\r
+ */\r
+ void SIG_OUTPUT_COMPARE1A( void ) __attribute__ ( ( signal ) );\r
+ void SIG_OUTPUT_COMPARE1A( void )\r
+ {\r
+ vTaskIncrementTick();\r
+ }\r
+#endif\r
+\r
+\r
+ \r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+Changes from V1.2.3\r
+\r
+ + portCPU_CLOSK_HZ definition changed to 8MHz base 10, previously it \r
+ base 16.\r
+*/\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Port specific definitions. \r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the\r
+ * given hardware and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *-----------------------------------------------------------\r
+ */\r
+\r
+/* Type definitions. */\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE double\r
+#define portLONG long\r
+#define portSHORT int\r
+#define portSTACK_TYPE unsigned portCHAR\r
+#define portBASE_TYPE char\r
+\r
+#if( configUSE_16_BIT_TICKS == 1 )\r
+ typedef unsigned portSHORT portTickType;\r
+ #define portMAX_DELAY ( portTickType ) 0xffff\r
+#else\r
+ typedef unsigned portLONG portTickType;\r
+ #define portMAX_DELAY ( portTickType ) 0xffffffff\r
+#endif\r
+/*-----------------------------------------------------------*/ \r
+\r
+/* Critical section management. */\r
+#define portENTER_CRITICAL() asm volatile ( "in __tmp_reg__, __SREG__" :: ); \\r
+ asm volatile ( "cli" :: ); \\r
+ asm volatile ( "push __tmp_reg__" :: )\r
+\r
+#define portEXIT_CRITICAL() asm volatile ( "pop __tmp_reg__" :: ); \\r
+ asm volatile ( "out __SREG__, __tmp_reg__" :: )\r
+\r
+#define portDISABLE_INTERRUPTS() asm volatile ( "cli" :: );\r
+#define portENABLE_INTERRUPTS() asm volatile ( "sei" :: );\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Architecture specifics. */\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) \r
+#define portBYTE_ALIGNMENT 1\r
+#define portNOP() asm volatile ( "nop" );\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Kernel utilities. */\r
+extern void vPortYield( void ) __attribute__ ( ( naked ) );\r
+#define portYIELD() vPortYield()\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Task function macros as described on the FreeRTOS.org WEB site. */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+\r
+#endif /* PORTMACRO_H */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ * Implementation of functions defined in portable.h for the H8S port.\r
+ *----------------------------------------------------------*/\r
+\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* When the task starts interrupts should be enabled. */\r
+#define portINITIAL_CCR ( ( portSTACK_TYPE ) 0x00 )\r
+\r
+/* Hardware specific constants used to generate the RTOS tick from the TPU. */\r
+#define portCLEAR_ON_TGRA_COMPARE_MATCH ( ( unsigned portCHAR ) 0x20 )\r
+#define portCLOCK_DIV_64 ( ( unsigned portCHAR ) 0x03 )\r
+#define portCLOCK_DIV ( ( unsigned portLONG ) 64 )\r
+#define portTGRA_INTERRUPT_ENABLE ( ( unsigned portCHAR ) 0x01 )\r
+#define portTIMER_CHANNEL ( ( unsigned portCHAR ) 0x02 )\r
+#define portMSTP13 ( ( unsigned portSHORT ) 0x2000 )\r
+\r
+/*\r
+ * Setup TPU channel one for the RTOS tick at the requested frequency.\r
+ */\r
+static void prvSetupTimerInterrupt( void );\r
+\r
+/*\r
+ * The ISR used by portYIELD(). This is installed as a trap handler.\r
+ */\r
+void vPortYield( void ) __attribute__ ( ( saveall, interrupt_handler ) );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* \r
+ * See header file for description. \r
+ */\r
+portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
+{\r
+unsigned portLONG ulValue;\r
+\r
+ /* This requires an even address. */\r
+ ulValue = ( unsigned portLONG ) pxTopOfStack;\r
+ if( ulValue & 1UL )\r
+ {\r
+ pxTopOfStack = pxTopOfStack - 1;\r
+ }\r
+\r
+ /* Place a few bytes of known values on the bottom of the stack. \r
+ This is just useful for debugging. */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0xaa;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0xbb;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0xcc;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0xdd;\r
+\r
+ /* The initial stack mimics an interrupt stack. First there is the program\r
+ counter (24 bits). */\r
+ ulValue = ( unsigned portLONG ) pxCode;\r
+\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) ( ulValue & 0xff );\r
+ pxTopOfStack--;\r
+ ulValue >>= 8UL;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) ( ulValue & 0xff );\r
+ pxTopOfStack--;\r
+ ulValue >>= 8UL;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) ( ulValue & 0xff );\r
+\r
+ /* Followed by the CCR. */ \r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portINITIAL_CCR;\r
+\r
+ /* Next all the general purpose registers - with the parameters being passed\r
+ in ER0. The parameter order must match that used by the compiler when the\r
+ "saveall" function attribute is used. */\r
+\r
+ /* ER6 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x66;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x66;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x66;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x66;\r
+ \r
+ /* ER0 */\r
+ ulValue = ( unsigned portLONG ) pvParameters;\r
+\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) ( ulValue & 0xff );\r
+ pxTopOfStack--;\r
+ ulValue >>= 8UL;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) ( ulValue & 0xff );\r
+ pxTopOfStack--;\r
+ ulValue >>= 8UL;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) ( ulValue & 0xff );\r
+ pxTopOfStack--;\r
+ ulValue >>= 8UL;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) ( ulValue & 0xff );\r
+ \r
+ /* ER1 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x11;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x11;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x11;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x11;\r
+\r
+ /* ER2 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x22;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x22;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x22;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x22;\r
+\r
+ /* ER3 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x33;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x33;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x33;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x33;\r
+\r
+ /* ER4 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x44;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x44;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x44;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x44;\r
+\r
+ /* ER5 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x55;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x55;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x55;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x55;\r
+\r
+ return pxTopOfStack;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portBASE_TYPE xPortStartScheduler( void )\r
+{\r
+extern void * pxCurrentTCB;\r
+\r
+ /* Setup the hardware to generate the tick. */\r
+ prvSetupTimerInterrupt();\r
+\r
+ /* Restore the context of the first task that is going to run. This\r
+ mirrors the function epilogue code generated by the compiler when the\r
+ "saveall" function attribute is used. */\r
+ asm volatile ( \r
+ "MOV.L @_pxCurrentTCB, ER6 \n\t"\r
+ "MOV.L @ER6, ER7 \n\t"\r
+ "LDM.L @SP+, (ER4-ER5) \n\t"\r
+ "LDM.L @SP+, (ER0-ER3) \n\t"\r
+ "MOV.L @ER7+, ER6 \n\t"\r
+ "RTE \n\t"\r
+ );\r
+\r
+ ( void ) pxCurrentTCB;\r
+\r
+ /* Should not get here. */\r
+ return pdTRUE;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEndScheduler( void )\r
+{\r
+ /* It is unlikely that the h8 port will get stopped. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Manual context switch. This is a trap handler. The "saveall" function\r
+ * attribute is used so the context is saved by the compiler prologue. All\r
+ * we have to do is save the stack pointer.\r
+ */\r
+void vPortYield( void )\r
+{\r
+ portSAVE_STACK_POINTER();\r
+ vTaskSwitchContext();\r
+ portRESTORE_STACK_POINTER();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* \r
+ * The interrupt handler installed for the RTOS tick depends on whether the \r
+ * preemptive or cooperative scheduler is being used. \r
+ */\r
+#if( configUSE_PREEMPTION == 1 )\r
+\r
+ /* \r
+ * The preemptive scheduler is used so the ISR calls vTaskSwitchContext().\r
+ * The function prologue saves the context so all we have to do is save\r
+ * the stack pointer.\r
+ */\r
+ void vTickISR( void ) __attribute__ ( ( saveall, interrupt_handler ) );\r
+ void vTickISR( void )\r
+ {\r
+ portSAVE_STACK_POINTER();\r
+ \r
+ vTaskIncrementTick();\r
+ vTaskSwitchContext();\r
+\r
+ /* Clear the interrupt. */\r
+ TSR1 &= ~0x01;\r
+\r
+ portRESTORE_STACK_POINTER();\r
+ }\r
+\r
+#else\r
+\r
+ /*\r
+ * The cooperative scheduler is being used so all we have to do is \r
+ * periodically increment the tick. This can just be a normal ISR and\r
+ * the "saveall" attribute is not required.\r
+ */\r
+ void vTickISR( void ) __attribute__ ( ( interrupt_handler ) );\r
+ void vTickISR( void )\r
+ {\r
+ vTaskIncrementTick();\r
+\r
+ /* Clear the interrupt. */\r
+ TSR1 &= ~0x01;\r
+ }\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Setup timer 1 compare match to generate a tick interrupt.\r
+ */\r
+static void prvSetupTimerInterrupt( void )\r
+{\r
+const unsigned portLONG ulCompareMatch = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) / portCLOCK_DIV;\r
+\r
+ /* Turn the module on. */\r
+ MSTPCR &= ~portMSTP13;\r
+\r
+ /* Configure timer 1. */\r
+ TCR1 = portCLEAR_ON_TGRA_COMPARE_MATCH | portCLOCK_DIV_64;\r
+\r
+ /* Configure the compare match value for a tick of configTICK_RATE_HZ. */\r
+ TGR1A = ulCompareMatch;\r
+\r
+ /* Start the timer and enable the interrupt - we can do this here as \r
+ interrupts are globally disabled when this function is called. */\r
+ TIER1 |= portTGRA_INTERRUPT_ENABLE;\r
+ TSTR |= portTIMER_CHANNEL;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Port specific definitions. \r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the\r
+ * given hardware and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *-----------------------------------------------------------\r
+ */\r
+\r
+/* Type definitions. */\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE double\r
+#define portLONG long\r
+#define portSHORT short\r
+#define portSTACK_TYPE unsigned portCHAR\r
+#define portBASE_TYPE char\r
+\r
+#if( configUSE_16_BIT_TICKS == 1 )\r
+ typedef unsigned portSHORT portTickType;\r
+ #define portMAX_DELAY ( portTickType ) 0xffff\r
+#else\r
+ typedef unsigned portLONG portTickType;\r
+ #define portMAX_DELAY ( portTickType ) 0xffffffff\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Hardware specifics. */\r
+#define portBYTE_ALIGNMENT 2\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) \r
+#define portYIELD() asm volatile( "TRAPA #0" )\r
+#define portNOP() asm volatile( "NOP" )\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Critical section handling. */\r
+#define portENABLE_INTERRUPTS() asm volatile( "ANDC #0x7F, CCR" );\r
+#define portDISABLE_INTERRUPTS() asm volatile( "ORC #0x80, CCR" );\r
+\r
+/* Push the CCR then disable interrupts. */\r
+#define portENTER_CRITICAL() asm volatile( "STC CCR, @-ER7" ); \\r
+ portDISABLE_INTERRUPTS();\r
+\r
+/* Pop the CCR to set the interrupt masking back to its previous state. */\r
+#define portEXIT_CRITICAL() asm volatile( "LDC @ER7+, CCR" );\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Task utilities. */\r
+\r
+/* Context switch macros. These macros are very simple as the context \r
+is saved simply by selecting the saveall attribute of the context switch \r
+interrupt service routines. These macros save and restore the stack\r
+pointer to the TCB. */\r
+\r
+#define portSAVE_STACK_POINTER() \\r
+extern void* pxCurrentTCB; \\r
+ \\r
+ asm volatile( \\r
+ "MOV.L @_pxCurrentTCB, ER5 \n\t" \\r
+ "MOV.L ER7, @ER5 \n\t" \\r
+ ); \\r
+ ( void ) pxCurrentTCB;\r
+\r
+\r
+#define portRESTORE_STACK_POINTER() \\r
+extern void* pxCurrentTCB; \\r
+ \\r
+ asm volatile( \\r
+ "MOV.L @_pxCurrentTCB, ER5 \n\t" \\r
+ "MOV.L @ER5, ER7 \n\t" \\r
+ ); \\r
+ ( void ) pxCurrentTCB;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Macros to allow a context switch from within an application ISR. */\r
+\r
+#define portENTER_SWITCHING_ISR() portSAVE_STACK_POINTER(); {\r
+\r
+#define portEXIT_SWITCHING_ISR( x ) \\r
+ if( x ) \\r
+ { \\r
+ extern void vTaskSwitchContext( void ); \\r
+ vTaskSwitchContext(); \\r
+ } \\r
+ } portRESTORE_STACK_POINTER();\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Task function macros as described on the FreeRTOS.org WEB site. */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+\r
+#endif /* PORTMACRO_H */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+ Changes from V2.5.2\r
+ \r
+ + usCriticalNesting now has a volatile qualifier.\r
+*/\r
+\r
+/* Standard includes. */\r
+#include <stdlib.h>\r
+#include <signal.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/*-----------------------------------------------------------\r
+ * Implementation of functions defined in portable.h for the MSP430 port.\r
+ *----------------------------------------------------------*/\r
+\r
+/* Constants required for hardware setup. The tick ISR runs off the ACLK, \r
+not the MCLK. */\r
+#define portACLK_FREQUENCY_HZ ( ( portTickType ) 32768 )\r
+#define portINITIAL_CRITICAL_NESTING ( ( unsigned portSHORT ) 10 )\r
+#define portFLAGS_INT_ENABLED ( ( portSTACK_TYPE ) 0x08 )\r
+\r
+/* We require the address of the pxCurrentTCB variable, but don't want to know\r
+any details of its type. */\r
+typedef void tskTCB;\r
+extern volatile tskTCB * volatile pxCurrentTCB;\r
+\r
+/* Most ports implement critical sections by placing the interrupt flags on\r
+the stack before disabling interrupts. Exiting the critical section is then\r
+simply a case of popping the flags from the stack. As mspgcc does not use\r
+a frame pointer this cannot be done as modifying the stack will clobber all\r
+the stack variables. Instead each task maintains a count of the critical\r
+section nesting depth. Each time a critical section is entered the count is\r
+incremented. Each time a critical section is left the count is decremented -\r
+with interrupts only being re-enabled if the count is zero.\r
+\r
+usCriticalNesting will get set to zero when the scheduler starts, but must\r
+not be initialised to zero as this will cause problems during the startup\r
+sequence. */\r
+volatile unsigned portSHORT usCriticalNesting = portINITIAL_CRITICAL_NESTING;\r
+/*-----------------------------------------------------------*/\r
+\r
+/* \r
+ * Macro to save a task context to the task stack. This simply pushes all the \r
+ * general purpose msp430 registers onto the stack, followed by the \r
+ * usCriticalNesting value used by the task. Finally the resultant stack \r
+ * pointer value is saved into the task control block so it can be retrieved \r
+ * the next time the task executes.\r
+ */\r
+#define portSAVE_CONTEXT() \\r
+ asm volatile ( "push r4 \n\t" \\r
+ "push r5 \n\t" \\r
+ "push r6 \n\t" \\r
+ "push r7 \n\t" \\r
+ "push r8 \n\t" \\r
+ "push r9 \n\t" \\r
+ "push r10 \n\t" \\r
+ "push r11 \n\t" \\r
+ "push r12 \n\t" \\r
+ "push r13 \n\t" \\r
+ "push r14 \n\t" \\r
+ "push r15 \n\t" \\r
+ "mov.w usCriticalNesting, r14 \n\t" \\r
+ "push r14 \n\t" \\r
+ "mov.w pxCurrentTCB, r12 \n\t" \\r
+ "mov.w r1, @r12 \n\t" \\r
+ );\r
+\r
+/* \r
+ * Macro to restore a task context from the task stack. This is effectively\r
+ * the reverse of portSAVE_CONTEXT(). First the stack pointer value is\r
+ * loaded from the task control block. Next the value for usCriticalNesting\r
+ * used by the task is retrieved from the stack - followed by the value of all\r
+ * the general purpose msp430 registers.\r
+ */\r
+#define portRESTORE_CONTEXT() \\r
+ asm volatile ( "mov.w pxCurrentTCB, r12 \n\t" \\r
+ "mov.w @r12, r1 \n\t" \\r
+ "pop r15 \n\t" \\r
+ "mov.w r15, usCriticalNesting \n\t" \\r
+ "pop r15 \n\t" \\r
+ "pop r14 \n\t" \\r
+ "pop r13 \n\t" \\r
+ "pop r12 \n\t" \\r
+ "pop r11 \n\t" \\r
+ "pop r10 \n\t" \\r
+ "pop r9 \n\t" \\r
+ "pop r8 \n\t" \\r
+ "pop r7 \n\t" \\r
+ "pop r6 \n\t" \\r
+ "pop r5 \n\t" \\r
+ "pop r4 \n\t" \\r
+ "reti \n\t" \\r
+ );\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Sets up the periodic ISR used for the RTOS tick. This uses timer 0, but\r
+ * could have alternatively used the watchdog timer or timer 1.\r
+ */\r
+static void prvSetupTimerInterrupt( void );\r
+/*-----------------------------------------------------------*/\r
+\r
+/* \r
+ * Initialise the stack of a task to look exactly as if a call to \r
+ * portSAVE_CONTEXT had been called.\r
+ * \r
+ * See the header file portable.h.\r
+ */\r
+portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
+{\r
+ /* \r
+ Place a few bytes of known values on the bottom of the stack. \r
+ This is just useful for debugging and can be included if required.\r
+\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x1111;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x2222;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x3333;\r
+ pxTopOfStack--; \r
+ */\r
+\r
+ /* The msp430 automatically pushes the PC then SR onto the stack before \r
+ executing an ISR. We want the stack to look just as if this has happened\r
+ so place a pointer to the start of the task on the stack first - followed\r
+ by the flags we want the task to use when it starts up. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) pxCode;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portFLAGS_INT_ENABLED;\r
+ pxTopOfStack--;\r
+\r
+ /* Next the general purpose registers. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x4444;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x5555;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x6666;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x7777;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x8888;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x9999;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaa;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0xbbbb;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0xcccc;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0xdddd;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0xeeee;\r
+ pxTopOfStack--;\r
+\r
+ /* When the task starts is will expect to find the function parameter in\r
+ R15. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) pvParameters;\r
+ pxTopOfStack--;\r
+\r
+ /* The code generated by the mspgcc compiler does not maintain separate\r
+ stack and frame pointers. The portENTER_CRITICAL macro cannot therefore\r
+ use the stack as per other ports. Instead a variable is used to keep\r
+ track of the critical section nesting. This variable has to be stored\r
+ as part of the task context and is initially set to zero. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) portNO_CRITICAL_SECTION_NESTING; \r
+\r
+ /* Return a pointer to the top of the stack we have generated so this can\r
+ be stored in the task control block for the task. */\r
+ return pxTopOfStack;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portBASE_TYPE xPortStartScheduler( void )\r
+{\r
+ /* Setup the hardware to generate the tick. Interrupts are disabled when\r
+ this function is called. */\r
+ prvSetupTimerInterrupt();\r
+\r
+ /* Restore the context of the first task that is going to run. */\r
+ portRESTORE_CONTEXT();\r
+\r
+ /* Should not get here as the tasks are now running! */\r
+ return pdTRUE;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEndScheduler( void )\r
+{\r
+ /* It is unlikely that the MSP430 port will get stopped. If required simply\r
+ disable the tick interrupt here. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Manual context switch called by portYIELD or taskYIELD. \r
+ *\r
+ * The first thing we do is save the registers so we can use a naked attribute.\r
+ */\r
+void vPortYield( void ) __attribute__ ( ( naked ) );\r
+void vPortYield( void )\r
+{\r
+ /* We want the stack of the task being saved to look exactly as if the task\r
+ was saved during a pre-emptive RTOS tick ISR. Before calling an ISR the \r
+ msp430 places the status register onto the stack. As this is a function \r
+ call and not an ISR we have to do this manually. */\r
+ asm volatile ( "push r2" );\r
+ _DINT();\r
+\r
+ /* Save the context of the current task. */\r
+ portSAVE_CONTEXT();\r
+\r
+ /* Switch to the highest priority task that is ready to run. */\r
+ vTaskSwitchContext();\r
+\r
+ /* Restore the context of the new task. */\r
+ portRESTORE_CONTEXT();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Hardware initialisation to generate the RTOS tick. This uses timer 0\r
+ * but could alternatively use the watchdog timer or timer 1. \r
+ */\r
+static void prvSetupTimerInterrupt( void )\r
+{\r
+ /* Ensure the timer is stopped. */\r
+ TACTL = 0;\r
+\r
+ /* Run the timer of the ACLK. */\r
+ TACTL = TASSEL_1;\r
+\r
+ /* Clear everything to start with. */\r
+ TACTL |= TACLR;\r
+\r
+ /* Set the compare match value according to the tick rate we want. */\r
+ TACCR0 = portACLK_FREQUENCY_HZ / configTICK_RATE_HZ;\r
+\r
+ /* Enable the interrupts. */\r
+ TACCTL0 = CCIE;\r
+\r
+ /* Start up clean. */\r
+ TACTL |= TACLR;\r
+\r
+ /* Up mode. */\r
+ TACTL |= MC_1;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* \r
+ * The interrupt service routine used depends on whether the pre-emptive\r
+ * scheduler is being used or not.\r
+ */\r
+\r
+#if configUSE_PREEMPTION == 1\r
+\r
+ /*\r
+ * Tick ISR for preemptive scheduler. We can use a naked attribute as\r
+ * the context is saved at the start of vPortYieldFromTick(). The tick\r
+ * count is incremented after the context is saved.\r
+ */\r
+ interrupt (TIMERA0_VECTOR) prvTickISR( void ) __attribute__ ( ( naked ) );\r
+ interrupt (TIMERA0_VECTOR) prvTickISR( void )\r
+ {\r
+ /* Save the context of the interrupted task. */\r
+ portSAVE_CONTEXT();\r
+\r
+ /* Increment the tick count then switch to the highest priority task\r
+ that is ready to run. */\r
+ vTaskIncrementTick();\r
+ vTaskSwitchContext();\r
+\r
+ /* Restore the context of the new task. */\r
+ portRESTORE_CONTEXT();\r
+ }\r
+\r
+#else\r
+\r
+ /*\r
+ * Tick ISR for the cooperative scheduler. All this does is increment the\r
+ * tick count. We don't need to switch context, this can only be done by\r
+ * manual calls to taskYIELD();\r
+ */\r
+ interrupt (TIMERA0_VECTOR) prvTickISR( void );\r
+ interrupt (TIMERA0_VECTOR) prvTickISR( void )\r
+ {\r
+ vTaskIncrementTick();\r
+ }\r
+#endif\r
+\r
+\r
+ \r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Port specific definitions. \r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the\r
+ * given hardware and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *-----------------------------------------------------------\r
+ */\r
+\r
+/* Type definitions. */\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE double\r
+#define portLONG long\r
+#define portSHORT int\r
+#define portSTACK_TYPE unsigned portSHORT\r
+#define portBASE_TYPE portSHORT\r
+\r
+#if( configUSE_16_BIT_TICKS == 1 )\r
+ typedef unsigned portSHORT portTickType;\r
+ #define portMAX_DELAY ( portTickType ) 0xffff\r
+#else\r
+ typedef unsigned portLONG portTickType;\r
+ #define portMAX_DELAY ( portTickType ) 0xffffffff\r
+#endif\r
+/*-----------------------------------------------------------*/ \r
+\r
+/* Interrupt control macros. */\r
+#define portDISABLE_INTERRUPTS() asm volatile ( "DINT" )\r
+#define portENABLE_INTERRUPTS() asm volatile ( "EINT" )\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Critical section control macros. */\r
+#define portNO_CRITICAL_SECTION_NESTING ( ( unsigned portSHORT ) 0 )\r
+\r
+#define portENTER_CRITICAL() \\r
+{ \\r
+extern volatile unsigned portSHORT usCriticalNesting; \\r
+ \\r
+ portDISABLE_INTERRUPTS(); \\r
+ \\r
+ /* Now interrupts are disabled ulCriticalNesting can be accessed */ \\r
+ /* directly. Increment ulCriticalNesting to keep a count of how many */ \\r
+ /* times portENTER_CRITICAL() has been called. */ \\r
+ usCriticalNesting++; \\r
+}\r
+\r
+#define portEXIT_CRITICAL() \\r
+{ \\r
+extern volatile unsigned portSHORT usCriticalNesting; \\r
+ \\r
+ if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \\r
+ { \\r
+ /* Decrement the nesting count as we are leaving a critical section. */ \\r
+ usCriticalNesting--; \\r
+ \\r
+ /* If the nesting level has reached zero then interrupts should be */ \\r
+ /* re-enabled. */ \\r
+ if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \\r
+ { \\r
+ portENABLE_INTERRUPTS(); \\r
+ } \\r
+ } \\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Task utilities. */\r
+extern void vPortYield( void ) __attribute__ ( ( naked ) );\r
+#define portYIELD() vPortYield()\r
+#define portNOP() asm volatile ( "NOP" )\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Hardwware specifics. */\r
+#define portBYTE_ALIGNMENT 2\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) \r
+/*-----------------------------------------------------------*/\r
+\r
+/* Task function macros as described on the FreeRTOS.org WEB site. */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+\r
+#endif /* PORTMACRO_H */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Implementation of functions defined in portable.h for the MicroBlaze port.\r
+ *----------------------------------------------------------*/\r
+\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Standard includes. */\r
+#include <string.h>\r
+\r
+/* Hardware includes. */\r
+#include <xintc.h>\r
+#include <xintc_i.h>\r
+#include <xtmrctr.h>\r
+\r
+/* Tasks are started with interrupts enabled. */\r
+#define portINITIAL_MSR_STATE ( ( portSTACK_TYPE ) 0x02 )\r
+\r
+/* Tasks are started with a critical section nesting of 0 - however prior\r
+to the scheduler being commenced we don't want the critical nesting level\r
+to reach zero, so it is initialised to a high value. */\r
+#define portINITIAL_NESTING_VALUE ( 0xff )\r
+\r
+/* Our hardware setup only uses one counter. */\r
+#define portCOUNTER_0 0\r
+\r
+/* The stack used by the ISR is filled with a known value to assist in\r
+debugging. */\r
+#define portISR_STACK_FILL_VALUE 0x55555555\r
+\r
+/* Counts the nesting depth of calls to portENTER_CRITICAL(). Each task \r
+maintains it's own count, so this variable is saved as part of the task\r
+context. */\r
+volatile unsigned portBASE_TYPE uxCriticalNesting = portINITIAL_NESTING_VALUE;\r
+\r
+/* To limit the amount of stack required by each task, this port uses a\r
+separate stack for interrupts. */\r
+unsigned portLONG *pulISRStack;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Sets up the periodic ISR used for the RTOS tick. This uses timer 0, but\r
+ * could have alternatively used the watchdog timer or timer 1.\r
+ */\r
+static void prvSetupTimerInterrupt( void );\r
+/*-----------------------------------------------------------*/\r
+\r
+/* \r
+ * Initialise the stack of a task to look exactly as if a call to \r
+ * portSAVE_CONTEXT had been made.\r
+ * \r
+ * See the header file portable.h.\r
+ */\r
+portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
+{\r
+extern void *_SDA2_BASE_, *_SDA_BASE_;\r
+const unsigned portLONG ulR2 = ( unsigned portLONG ) &_SDA2_BASE_;\r
+const unsigned portLONG ulR13 = ( unsigned portLONG ) &_SDA_BASE_;\r
+\r
+ /* Place a few bytes of known values on the bottom of the stack. \r
+ This is essential for the Microblaze port and these lines must\r
+ not be omitted. The parameter value will overwrite the \r
+ 0x22222222 value during the function prologue. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x22222222;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x33333333;\r
+ pxTopOfStack--; \r
+\r
+ /* First stack an initial value for the critical section nesting. This\r
+ is initialised to zero as tasks are started with interrupts enabled. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* R0. */\r
+\r
+ /* Place an initial value for all the general purpose registers. */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) ulR2; /* R2 - small data area. */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x03; /* R3. */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x04; /* R4. */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) pvParameters;/* R5 contains the function call parameters. */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x06; /* R6. */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x07; /* R7. */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x08; /* R8. */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x09; /* R9. */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x0a; /* R10. */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x0b; /* R11. */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x0c; /* R12. */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) ulR13; /* R13 - small data read write area. */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* R14. */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x0f; /* R15. */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x10; /* R16. */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x11; /* R17. */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x12; /* R18. */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x13; /* R19. */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x14; /* R20. */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x15; /* R21. */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x16; /* R22. */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x17; /* R23. */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x18; /* R24. */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x19; /* R25. */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x1a; /* R26. */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x1b; /* R27. */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x1c; /* R28. */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x1d; /* R29. */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x1e; /* R30. */\r
+ pxTopOfStack--;\r
+\r
+ /* The MSR is stacked between R30 and R31. */\r
+ *pxTopOfStack = portINITIAL_MSR_STATE;\r
+ pxTopOfStack--;\r
+\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x1f; /* R31. */\r
+ pxTopOfStack--;\r
+\r
+ /* Return a pointer to the top of the stack we have generated so this can\r
+ be stored in the task control block for the task. */\r
+ return pxTopOfStack;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portBASE_TYPE xPortStartScheduler( void )\r
+{\r
+extern void ( __FreeRTOS_interrupt_Handler )( void );\r
+extern void ( vStartFirstTask )( void );\r
+\r
+\r
+ /* Setup the FreeRTOS interrupt handler. Code copied from crt0.s. */\r
+ asm volatile ( "la r6, r0, __FreeRTOS_interrupt_handler \n\t" \
+ "sw r6, r1, r0 \n\t" \
+ "lhu r7, r1, r0 \n\t" \
+ "shi r7, r0, 0x12 \n\t" \
+ "shi r6, r0, 0x16 " );\r
+\r
+ /* Setup the hardware to generate the tick. Interrupts are disabled when\r
+ this function is called. */\r
+ prvSetupTimerInterrupt();\r
+\r
+ /* Allocate the stack to be used by the interrupt handler. */\r
+ pulISRStack = ( unsigned portLONG * ) pvPortMalloc( configMINIMAL_STACK_SIZE * sizeof( portSTACK_TYPE ) );\r
+\r
+ /* Restore the context of the first task that is going to run. */\r
+ if( pulISRStack != NULL )\r
+ {\r
+ /* Fill the ISR stack with a known value to facilitate debugging. */\r
+ memset( pulISRStack, portISR_STACK_FILL_VALUE, configMINIMAL_STACK_SIZE * sizeof( portSTACK_TYPE ) );\r
+ pulISRStack += ( configMINIMAL_STACK_SIZE - 1 );\r
+\r
+ /* Kick off the first task. */\r
+ vStartFirstTask();\r
+ }\r
+\r
+ /* Should not get here as the tasks are now running! */\r
+ return pdFALSE;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEndScheduler( void )\r
+{\r
+ /* Not implemented. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Manual context switch called by portYIELD or taskYIELD. \r
+ */\r
+void vPortYield( void )\r
+{\r
+extern void VPortYieldASM( void );\r
+\r
+ /* Perform the context switch in a critical section to assure it is\r
+ not interrupted by the tick ISR. It is not a problem to do this as\r
+ each task maintains it's own interrupt status. */\r
+ portENTER_CRITICAL();\r
+ /* Jump directly to the yield function to ensure there is no\r
+ compiler generated prologue code. */\r
+ asm volatile ( "bralid r14, VPortYieldASM \n\t" \\r
+ "or r0, r0, r0 \n\t" );\r
+ portEXIT_CRITICAL();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Hardware initialisation to generate the RTOS tick. \r
+ */\r
+static void prvSetupTimerInterrupt( void )\r
+{\r
+XTmrCtr xTimer;\r
+const unsigned portLONG ulCounterValue = configCPU_CLOCK_HZ / configTICK_RATE_HZ;\r
+unsigned portBASE_TYPE uxMask;\r
+\r
+ /* The OPB timer1 is used to generate the tick. Use the provided library\r
+ functions to enable the timer and set the tick frequency. */\r
+ XTmrCtr_mDisable( XPAR_OPB_TIMER_1_BASEADDR, XPAR_OPB_TIMER_1_DEVICE_ID );\r
+ XTmrCtr_Initialize( &xTimer, XPAR_OPB_TIMER_1_DEVICE_ID );\r
+ XTmrCtr_mSetLoadReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, ulCounterValue );\r
+ XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_LOAD_MASK | XTC_CSR_INT_OCCURED_MASK );\r
+\r
+ /* Set the timer interrupt enable bit while maintaining the other bit \r
+ states. */\r
+ uxMask = XIntc_In32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ) );\r
+ uxMask |= XPAR_OPB_TIMER_1_INTERRUPT_MASK;\r
+ XIntc_Out32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ), ( uxMask ) ); \r
+ \r
+ XTmrCtr_Start( &xTimer, XPAR_OPB_TIMER_1_DEVICE_ID );\r
+ XTmrCtr_mSetControlStatusReg(XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK | XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK | XTC_CSR_INT_OCCURED_MASK );\r
+ XIntc_mAckIntr( XPAR_INTC_SINGLE_BASEADDR, 1 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The interrupt handler placed in the interrupt vector when the scheduler is\r
+ * started. The task context has already been saved when this is called.\r
+ * This handler determines the interrupt source and calls the relevant \r
+ * peripheral handler.\r
+ */\r
+void vTaskISRHandler( void )\r
+{\r
+static unsigned portLONG ulPending;
+\r
+ /* Which interrupts are pending? */
+ ulPending = XIntc_In32( ( XPAR_INTC_SINGLE_BASEADDR + XIN_IVR_OFFSET ) );
+\r
+ if( ulPending < XPAR_INTC_MAX_NUM_INTR_INPUTS )\r
+ {\r
+ static XIntc_VectorTableEntry *pxTablePtr;\r
+ static XIntc_Config *pxConfig;\r
+ static unsigned portLONG ulInterruptMask;\r
+\r
+ ulInterruptMask = ( unsigned portLONG ) 1 << ulPending;\r
+\r
+ /* Get the configuration data using the device ID */
+ pxConfig = &XIntc_ConfigTable[ ( unsigned portLONG ) XPAR_INTC_SINGLE_DEVICE_ID ];\r
+\r
+ pxTablePtr = &( pxConfig->HandlerTable[ ulPending ] );\r
+ if( pxConfig->AckBeforeService & ( ulInterruptMask ) )
+ {
+ XIntc_mAckIntr( pxConfig->BaseAddress, ulInterruptMask );\r
+ pxTablePtr->Handler( pxTablePtr->CallBackRef );
+ }\r
+ else
+ {\r
+ pxTablePtr->Handler( pxTablePtr->CallBackRef );
+ XIntc_mAckIntr( pxConfig->BaseAddress, ulInterruptMask );
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* \r
+ * Handler for the timer interrupt.\r
+ */\r
+void vTickISR( void *pvBaseAddress )\r
+{\r
+unsigned portLONG ulCSR;\r
+\r
+ /* Increment the RTOS tick - this might cause a task to unblock. */\r
+ vTaskIncrementTick();\r
+\r
+ /* Clear the timer interrupt */\r
+ ulCSR = XTmrCtr_mGetControlStatusReg(XPAR_OPB_TIMER_1_BASEADDR, 0); \r
+ XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, ulCSR );\r
+\r
+ /* If we are using the preemptive scheduler then we also need to determine\r
+ if this tick should cause a context switch. */\r
+ #if configUSE_PREEMPTION == 1\r
+ vTaskSwitchContext();\r
+ #endif\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+ .extern pxCurrentTCB\r
+ .extern vTaskISRHandler\r
+ .extern vTaskSwitchContext\r
+ .extern uxCriticalNesting\r
+ .extern pulISRStack\r
+\r
+ .global __FreeRTOS_interrupt_handler\r
+ .global VPortYieldASM\r
+ .global vStartFirstTask\r
+\r
+\r
+.macro portSAVE_CONTEXT\r
+ /* Make room for the context on the stack. */\r
+ addik r1, r1, -132\r
+ /* Save r31 so it can then be used. */\r
+ swi r31, r1, 4\r
+ /* Copy the msr into r31 - this is stacked later. */\r
+ mfs r31, rmsr\r
+ /* Stack general registers. */\r
+ swi r30, r1, 12\r
+ swi r29, r1, 16\r
+ swi r28, r1, 20\r
+ swi r27, r1, 24\r
+ swi r26, r1, 28\r
+ swi r25, r1, 32\r
+ swi r24, r1, 36\r
+ swi r23, r1, 40\r
+ swi r22, r1, 44\r
+ swi r21, r1, 48\r
+ swi r20, r1, 52\r
+ swi r19, r1, 56\r
+ swi r18, r1, 60\r
+ swi r17, r1, 64\r
+ swi r16, r1, 68\r
+ swi r15, r1, 72\r
+ swi r13, r1, 80\r
+ swi r12, r1, 84\r
+ swi r11, r1, 88\r
+ swi r10, r1, 92\r
+ swi r9, r1, 96\r
+ swi r8, r1, 100\r
+ swi r7, r1, 104\r
+ swi r6, r1, 108\r
+ swi r5, r1, 112\r
+ swi r4, r1, 116\r
+ swi r3, r1, 120\r
+ swi r2, r1, 124\r
+ /* Stack the critical section nesting value. */\r
+ lwi r3, r0, uxCriticalNesting\r
+ swi r3, r1, 128\r
+ /* Save the top of stack value to the TCB. */\r
+ lwi r3, r0, pxCurrentTCB\r
+ sw r1, r0, r3\r
+ \r
+ .endm\r
+\r
+.macro portRESTORE_CONTEXT\r
+ /* Load the top of stack value from the TCB. */\r
+ lwi r3, r0, pxCurrentTCB\r
+ lw r1, r0, r3 \r
+ /* Restore the general registers. */\r
+ lwi r31, r1, 4 \r
+ lwi r30, r1, 12 \r
+ lwi r29, r1, 16 \r
+ lwi r28, r1, 20 \r
+ lwi r27, r1, 24 \r
+ lwi r26, r1, 28 \r
+ lwi r25, r1, 32 \r
+ lwi r24, r1, 36 \r
+ lwi r23, r1, 40 \r
+ lwi r22, r1, 44 \r
+ lwi r21, r1, 48 \r
+ lwi r20, r1, 52 \r
+ lwi r19, r1, 56 \r
+ lwi r18, r1, 60 \r
+ lwi r17, r1, 64 \r
+ lwi r16, r1, 68 \r
+ lwi r15, r1, 72 \r
+ lwi r14, r1, 76 \r
+ lwi r13, r1, 80 \r
+ lwi r12, r1, 84 \r
+ lwi r11, r1, 88 \r
+ lwi r10, r1, 92 \r
+ lwi r9, r1, 96 \r
+ lwi r8, r1, 100 \r
+ lwi r7, r1, 104\r
+ lwi r6, r1, 108\r
+ lwi r5, r1, 112\r
+ lwi r4, r1, 116\r
+ lwi r2, r1, 124\r
+\r
+ /* Load the critical nesting value. */\r
+ lwi r3, r1, 128\r
+ swi r3, r0, uxCriticalNesting\r
+\r
+ /* Obtain the MSR value from the stack. */\r
+ lwi r3, r1, 8\r
+\r
+ /* Are interrupts enabled in the MSR? If so return using an return from \r
+ interrupt instruction to ensure interrupts are enabled only once the task\r
+ is running again. */\r
+ andi r3, r3, 2\r
+ beqid r3, 36\r
+ or r0, r0, r0\r
+\r
+ /* Reload the rmsr from the stack, clear the enable interrupt bit in the\r
+ value before saving back to rmsr register, then return enabling interrupts\r
+ as we return. */\r
+ lwi r3, r1, 8\r
+ andi r3, r3, ~2\r
+ mts rmsr, r3\r
+ lwi r3, r1, 120\r
+ addik r1, r1, 132\r
+ rtid r14, 0\r
+ or r0, r0, r0\r
+\r
+ /* Reload the rmsr from the stack, place it in the rmsr register, and\r
+ return without enabling interrupts. */\r
+ lwi r3, r1, 8\r
+ mts rmsr, r3\r
+ lwi r3, r1, 120\r
+ addik r1, r1, 132\r
+ rtsd r14, 0\r
+ or r0, r0, r0\r
+\r
+ .endm\r
+\r
+ .text\r
+ .align 2\r
+\r
+\r
+__FreeRTOS_interrupt_handler:\r
+ portSAVE_CONTEXT\r
+ /* Entered via an interrupt so interrupts must be enabled in msr. */\r
+ ori r31, r31, 2\r
+ /* Stack msr. */\r
+ swi r31, r1, 8\r
+ /* Stack the return address. As we entered via an interrupt we do\r
+ not need to modify the return address prior to stacking. */\r
+ swi r14, r1, 76\r
+ /* Now switch to use the ISR stack. */\r
+ lwi r3, r0, pulISRStack\r
+ add r1, r3, r0\r
+ bralid r15, vTaskISRHandler\r
+ or r0, r0, r0\r
+ portRESTORE_CONTEXT\r
+\r
+\r
+VPortYieldASM:\r
+ portSAVE_CONTEXT\r
+ /* Stack msr. */\r
+ swi r31, r1, 8\r
+ /* Modify the return address so we return to the instruction after the\r
+ exception. */\r
+ addi r14, r14, 8\r
+ swi r14, r1, 76\r
+ /* Now switch to use the ISR stack. */\r
+ lwi r3, r0, pulISRStack\r
+ add r1, r3, r0\r
+ bralid r15, vTaskSwitchContext\r
+ or r0, r0, r0\r
+ portRESTORE_CONTEXT\r
+\r
+vStartFirstTask:\r
+ portRESTORE_CONTEXT\r
+ \r
+ \r
+\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Port specific definitions. \r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the\r
+ * given hardware and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *-----------------------------------------------------------\r
+ */\r
+\r
+/* Type definitions. */\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE double\r
+#define portLONG long\r
+#define portSHORT short\r
+#define portSTACK_TYPE unsigned portLONG\r
+#define portBASE_TYPE portLONG\r
+\r
+#if( configUSE_16_BIT_TICKS == 1 )\r
+ typedef unsigned portSHORT portTickType;\r
+ #define portMAX_DELAY ( portTickType ) 0xffff\r
+#else\r
+ typedef unsigned portLONG portTickType;\r
+ #define portMAX_DELAY ( portTickType ) 0xffffffff\r
+#endif\r
+/*-----------------------------------------------------------*/ \r
+\r
+/* Interrupt control macros. */\r
+void microblaze_disable_interrupts( void );\r
+void microblaze_enable_interrupts( void );\r
+#define portDISABLE_INTERRUPTS() microblaze_disable_interrupts()\r
+#define portENABLE_INTERRUPTS() microblaze_enable_interrupts()\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Critical section macros. */\r
+void vPortEnterCritical( void );\r
+void vPortExitCritical( void );\r
+#define portENTER_CRITICAL() { \\r
+ extern unsigned portBASE_TYPE uxCriticalNesting; \\r
+ microblaze_disable_interrupts(); \\r
+ uxCriticalNesting++; \\r
+ }\r
+ \r
+#define portEXIT_CRITICAL() { \\r
+ extern unsigned portBASE_TYPE uxCriticalNesting; \\r
+ /* Interrupts are disabled, so we can */ \\r
+ /* access the variable directly. */ \\r
+ uxCriticalNesting--; \\r
+ if( uxCriticalNesting == 0 ) \\r
+ { \\r
+ /* The nesting has unwound and we \\r
+ can enable interrupts again. */ \\r
+ portENABLE_INTERRUPTS(); \\r
+ } \\r
+ }\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Task utilities. */\r
+void vPortYield( void );\r
+#define portYIELD() vPortYield()\r
+\r
+void vTaskSwitchContext();\r
+#define portYIELD_FROM_ISR() vTaskSwitchContext()\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Hardware specifics. */\r
+#define portBYTE_ALIGNMENT 4\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) \r
+#define portNOP() asm volatile ( "NOP" )\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Task function macros as described on the FreeRTOS.org WEB site. */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+\r
+#endif /* PORTMACRO_H */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#include <stdlib.h>\r
+\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/*-----------------------------------------------------------\r
+ * Implementation of functions defined in portable.h for the AVR/IAR port.\r
+ *----------------------------------------------------------*/\r
+\r
+/* Start tasks with interrupts enables. */\r
+#define portFLAGS_INT_ENABLED ( ( portSTACK_TYPE ) 0x80 )\r
+\r
+/* Hardware constants for timer 1. */\r
+#define portCLEAR_COUNTER_ON_MATCH ( ( unsigned portCHAR ) 0x08 )\r
+#define portPRESCALE_64 ( ( unsigned portCHAR ) 0x03 )\r
+#define portCLOCK_PRESCALER ( ( unsigned portLONG ) 64 )\r
+#define portCOMPARE_MATCH_A_INTERRUPT_ENABLE ( ( unsigned portCHAR ) 0x10 )\r
+\r
+/* The number of bytes used on the hardware stack by the task start address. */\r
+#define portBYTES_USED_BY_RETURN_ADDRESS ( 2 )\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Perform hardware setup to enable ticks from timer 1, compare match A.\r
+ */\r
+static void prvSetupTimerInterrupt( void );\r
+\r
+/*\r
+ * The IAR compiler does not have full support for inline assembler, so\r
+ * these are defined in the portmacro assembler file.\r
+ */\r
+extern void vPortYieldFromTick( void );\r
+extern void vPortStart( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * See header file for description.\r
+ */\r
+portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
+{\r
+unsigned portSHORT usAddress;\r
+portSTACK_TYPE *pxTopOfHardwareStack;\r
+\r
+ /* Place a few bytes of known values on the bottom of the stack.\r
+ This is just useful for debugging. */\r
+\r
+ *pxTopOfStack = 0x11;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x22;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x33;\r
+ pxTopOfStack--;\r
+\r
+ /* Remember where the top of the hardware stack is - this is required\r
+ below. */\r
+ pxTopOfHardwareStack = pxTopOfStack;\r
+\r
+\r
+ /* Simulate how the stack would look after a call to vPortYield(). */\r
+\r
+ /*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */\r
+\r
+\r
+\r
+ /* The IAR compiler requires two stacks per task. First there is the\r
+ hardware call stack which uses the AVR stack pointer. Second there is the\r
+ software stack (local variables, parameter passing, etc.) which uses the\r
+ AVR Y register.\r
+ \r
+ This function places both stacks within the memory block passed in as the\r
+ first parameter. The hardware stack is placed at the bottom of the memory\r
+ block. A gap is then left for the hardware stack to grow. Next the software\r
+ stack is placed. The amount of space between the software and hardware\r
+ stacks is defined by configCALL_STACK_SIZE.\r
+\r
+\r
+\r
+ The first part of the stack is the hardware stack. Place the start\r
+ address of the task on the hardware stack. */\r
+ usAddress = ( unsigned portSHORT ) pxCode;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) ( usAddress & ( unsigned portSHORT ) 0x00ff );\r
+ pxTopOfStack--;\r
+\r
+ usAddress >>= 8;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) ( usAddress & ( unsigned portSHORT ) 0x00ff );\r
+ pxTopOfStack--;\r
+\r
+\r
+ /* Leave enough space for the hardware stack before starting the software\r
+ stack. The '- 2' is because we have already used two spaces for the\r
+ address of the start of the task. */\r
+ pxTopOfStack -= ( configCALL_STACK_SIZE - 2 );\r
+\r
+\r
+\r
+ /* Next simulate the stack as if after a call to portSAVE_CONTEXT().\r
+ portSAVE_CONTEXT places the flags on the stack immediately after r0\r
+ to ensure the interrupts get disabled as soon as possible, and so ensuring\r
+ the stack use is minimal should a context switch interrupt occur. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* R0 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portFLAGS_INT_ENABLED;\r
+ pxTopOfStack--;\r
+\r
+ /* Next place the address of the hardware stack. This is required so\r
+ the AVR stack pointer can be restored to point to the hardware stack. */\r
+ pxTopOfHardwareStack -= portBYTES_USED_BY_RETURN_ADDRESS;\r
+ usAddress = ( unsigned portSHORT ) pxTopOfHardwareStack;\r
+\r
+ /* SPL */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) ( usAddress & ( unsigned portSHORT ) 0x00ff );\r
+ pxTopOfStack--;\r
+\r
+ /* SPH */\r
+ usAddress >>= 8;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) ( usAddress & ( unsigned portSHORT ) 0x00ff );\r
+ pxTopOfStack--;\r
+\r
+\r
+\r
+\r
+ /* Now the remaining registers. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x01; /* R1 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x02; /* R2 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x03; /* R3 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x04; /* R4 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x05; /* R5 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x06; /* R6 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x07; /* R7 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x08; /* R8 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x09; /* R9 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x10; /* R10 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x11; /* R11 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x12; /* R12 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x13; /* R13 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x14; /* R14 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x15; /* R15 */\r
+ pxTopOfStack--;\r
+\r
+ /* Place the parameter on the stack in the expected location. */\r
+ usAddress = ( unsigned portSHORT ) pvParameters;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) ( usAddress & ( unsigned portSHORT ) 0x00ff );\r
+ pxTopOfStack--;\r
+\r
+ usAddress >>= 8;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) ( usAddress & ( unsigned portSHORT ) 0x00ff );\r
+ pxTopOfStack--;\r
+\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x18; /* R18 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x19; /* R19 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x20; /* R20 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x21; /* R21 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x22; /* R22 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x23; /* R23 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x24; /* R24 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x25; /* R25 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x26; /* R26 X */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x27; /* R27 */\r
+ pxTopOfStack--;\r
+\r
+ /* The Y register is not stored as it is used as the software stack and\r
+ gets saved into the task control block. */\r
+\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x30; /* R30 Z */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x031; /* R31 */\r
+\r
+ /*lint +e950 +e611 +e923 */\r
+\r
+ return pxTopOfStack;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portBASE_TYPE xPortStartScheduler( void )\r
+{\r
+ /* Setup the hardware to generate the tick. */\r
+ prvSetupTimerInterrupt();\r
+\r
+ /* Restore the context of the first task that is going to run.\r
+ Normally we would just call portRESTORE_CONTEXT() here, but as the IAR\r
+ compiler does not fully support inline assembler we have to make a call.*/\r
+ vPortStart();\r
+\r
+\r
+ /* Should not get here! */\r
+ return pdTRUE;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEndScheduler( void )\r
+{\r
+ /* It is unlikely that the AVR port will get stopped. If required simply\r
+ disable the tick interrupt here. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Setup timer 1 compare match A to generate a tick interrupt.\r
+ */\r
+static void prvSetupTimerInterrupt( void )\r
+{\r
+unsigned portLONG ulCompareMatch;\r
+unsigned portCHAR ucHighByte, ucLowByte;\r
+\r
+ /* Using 16bit timer 1 to generate the tick. Correct fuses must be\r
+ selected for the configCPU_CLOCK_HZ clock. */\r
+\r
+ ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;\r
+\r
+ /* We only have 16 bits so have to scale to get our required tick rate. */\r
+ ulCompareMatch /= portCLOCK_PRESCALER;\r
+\r
+ /* Adjust for correct value. */\r
+ ulCompareMatch -= ( unsigned portLONG ) 1;\r
+\r
+ /* Setup compare match value for compare match A. Interrupts are disabled\r
+ before this is called so we need not worry here. */\r
+ ucLowByte = ( unsigned portCHAR ) ( ulCompareMatch & ( unsigned portLONG ) 0xff );\r
+ ulCompareMatch >>= 8;\r
+ ucHighByte = ( unsigned portCHAR ) ( ulCompareMatch & ( unsigned portLONG ) 0xff );\r
+ OCR1AH = ucHighByte;\r
+ OCR1AL = ucLowByte;\r
+\r
+ /* Setup clock source and compare match behaviour. */\r
+ ucLowByte = portCLEAR_COUNTER_ON_MATCH | portPRESCALE_64;\r
+ TCCR1B = ucLowByte;\r
+\r
+ /* Enable the interrupt - this is okay as interrupt are currently globally\r
+ disabled. */\r
+ TIMSK |= portCOMPARE_MATCH_A_INTERRUPT_ENABLE;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if configUSE_PREEMPTION == 1\r
+\r
+ /*\r
+ * Tick ISR for preemptive scheduler. We can use a __task attribute as\r
+ * the context is saved at the start of vPortYieldFromTick(). The tick\r
+ * count is incremented after the context is saved.\r
+ */\r
+ __task void SIG_OUTPUT_COMPARE1A( void )\r
+ {\r
+ vPortYieldFromTick();\r
+ asm( "reti" );\r
+ }\r
+ \r
+#else\r
+\r
+ /*\r
+ * Tick ISR for the cooperative scheduler. All this does is increment the\r
+ * tick count. We don't need to switch context, this can only be done by\r
+ * manual calls to taskYIELD();\r
+ *\r
+ * THE INTERRUPT VECTOR IS POPULATED IN portmacro.s90. DO NOT INSTALL\r
+ * IT HERE USING THE USUAL PRAGMA.\r
+ */ \r
+ __interrupt void SIG_OUTPUT_COMPARE1A( void )\r
+ {\r
+ vTaskIncrementTick();\r
+ }\r
+#endif\r
+\r
+\r
+ \r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+Changes from V1.2.3\r
+\r
+ + portCPU_CLOSK_HZ definition changed to 8MHz base 10, previously it\r
+ base 16.\r
+*/\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Port specific definitions.\r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the\r
+ * given hardware and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *-----------------------------------------------------------\r
+ */\r
+\r
+/* Type definitions. */\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE double\r
+#define portLONG long\r
+#define portSHORT int\r
+#define portSTACK_TYPE unsigned portCHAR\r
+#define portBASE_TYPE portCHAR\r
+\r
+#if( configUSE_16_BIT_TICKS == 1 )\r
+ typedef unsigned portSHORT portTickType;\r
+ #define portMAX_DELAY ( portTickType ) 0xffff\r
+#else\r
+ typedef unsigned portLONG portTickType;\r
+ #define portMAX_DELAY ( portTickType ) 0xffffffff\r
+#endif\r
+\r
+/*-----------------------------------------------------------*/ \r
+\r
+/* Critical section management. */\r
+#define portENTER_CRITICAL() asm( "in r15, 3fh" ); \\r
+ asm( "cli" ); \\r
+ asm( "st -y, r15" )\r
+\r
+#define portEXIT_CRITICAL() asm( "ld r15, y+" ); \\r
+ asm( "out 3fh, r15" )\r
+\r
+#define portDISABLE_INTERRUPTS() asm( "cli" );\r
+#define portENABLE_INTERRUPTS() asm( "sti" );\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Architecture specifics. */\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) \r
+#define portBYTE_ALIGNMENT 1\r
+#define portNOP() asm( "nop" )\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Kernel utilities. */\r
+void vPortYield( void );\r
+#define portYIELD() vPortYield()\r
+\r
+#ifdef IAR_MEGA_AVR\r
+ #define outb( PORT, VALUE ) PORT = VALUE\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Compiler specifics. */\r
+#define inline\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Task function macros as described on the FreeRTOS.org WEB site. */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+\r
+#endif /* PORTMACRO_H */\r
+\r
+\r
--- /dev/null
+; FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+;\r
+; This file is part of the FreeRTOS distribution.\r
+;\r
+; FreeRTOS is free software; you can redistribute it and/or modify\r
+; it under the terms of the GNU General Public License as published by\r
+; the Free Software Foundation; either version 2 of the License, or\r
+; (at your option) any later version.\r
+;\r
+; FreeRTOS is distributed in the hope that it will be useful,\r
+; but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+; GNU General Public License for more details.\r
+;\r
+; You should have received a copy of the GNU General Public License\r
+; along with FreeRTOS; if not, write to the Free Software\r
+; Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+;\r
+; A special exception to the GPL can be applied should you wish to distribute\r
+; a combined work that includes FreeRTOS, without being obliged to provide\r
+; the source code for any proprietary components. See the licensing section \r
+; of http://www.FreeRTOS.org for full details of how and when the exception\r
+; can be applied.\r
+;\r
+; ***************************************************************************\r
+; See http://www.FreeRTOS.org for documentation, latest information, license \r
+; and contact details. Please ensure to read the configuration and relevant \r
+; port sections of the online documentation.\r
+; ***************************************************************************\r
+\r
+#include <iom323.h>\r
+\r
+; Declare all extern symbols here - including any ISRs that are referenced in\r
+; the vector table.\r
+\r
+; ISR functions\r
+; -------------\r
+EXTERN SIG_OUTPUT_COMPARE1A\r
+EXTERN SIG_UART_RECV\r
+EXTERN SIG_UART_DATA\r
+\r
+\r
+; Functions used by scheduler\r
+; ---------------------------\r
+EXTERN vTaskSwitchContext\r
+EXTERN pxCurrentTCB\r
+EXTERN vTaskIncrementTick\r
+\r
+; Functions implemented in this file\r
+; ----------------------------------\r
+PUBLIC vPortYield\r
+PUBLIC vPortYieldFromTick\r
+PUBLIC vPortStart\r
+\r
+\r
+; Interrupt vector table.\r
+; -----------------------\r
+;\r
+; For simplicity the RTOS tick interrupt routine uses the __task keyword.\r
+; As the IAR compiler does not permit a function to be declared using both\r
+; __task and __interrupt, the use of __task necessitates that the interrupt\r
+; vector table be setup manually.\r
+;\r
+; To write an ISR, implement the ISR function using the __interrupt keyword\r
+; but do not install the interrupt using the "#pragma vector=ABC" method.\r
+; Instead manually place the name of the ISR in the vector table using an\r
+; ORG and jmp instruction as demonstrated below.\r
+; You will also have to add an EXTERN statement at the top of the file.\r
+\r
+ ASEG\r
+\r
+\r
+ ORG TIMER1_COMPA_vect ; Vector address\r
+ jmp SIG_OUTPUT_COMPARE1A ; ISR\r
+\r
+ ORG USART_RXC_vect ; Vector address\r
+ jmp SIG_UART_RECV ; ISR\r
+\r
+ ORG USART_UDRE_vect ; Vector address\r
+ jmp SIG_UART_DATA ; ISR\r
+\r
+ \r
+ RSEG CODE\r
+\r
+\r
+\r
+; Saving and Restoring a Task Context and Task Switching\r
+; ------------------------------------------------------\r
+;\r
+; The IAR compiler does not fully support inline assembler, so saving and\r
+; restoring a task context has to be written in an asm file. \r
+;\r
+; vPortYield() and vPortYieldFromTick() are usually written in C. Doing\r
+; so in this case would required calls to be made to portSAVE_CONTEXT() and\r
+; portRESTORE_CONTEXT(). This is dis-advantageous as the context switch \r
+; function would require two extra jump and return instructions over the \r
+; WinAVR equivalent. \r
+;\r
+; To avoid this I have opted to implement both vPortYield() and \r
+; vPortYieldFromTick() in this assembly file. For convenience\r
+; portSAVE_CONTEXT and portRESTORE_CONTEXT are implemented as macros.\r
+\r
+portSAVE_CONTEXT MACRO\r
+ st -y, r0 ; First save the r0 register - we need to use this.\r
+ in r0, SREG ; Obtain the SREG value so we can disable interrupts...\r
+ cli ; ... as soon as possible.\r
+ st -y, r0 ; Store the SREG as it was before we disabled interrupts.\r
+\r
+ in r0, SPL ; Next store the hardware stack pointer. The IAR...\r
+ st -y, r0 ; ... compiler uses the hardware stack as a call stack ...\r
+ in r0, SPH ; ... only.\r
+ st -y, r0\r
+\r
+ st -y, r1 ; Now store the rest of the registers. Dont store the ...\r
+ st -y, r2 ; ... the Y register here as it is used as the software\r
+ st -y, r3 ; stack pointer and will get saved into the TCB.\r
+ st -y, r4\r
+ st -y, r5\r
+ st -y, r6\r
+ st -y, r7\r
+ st -y, r8\r
+ st -y, r9\r
+ st -y, r10\r
+ st -y, r11\r
+ st -y, r12\r
+ st -y, r13\r
+ st -y, r14\r
+ st -y, r15\r
+ st -y, r16\r
+ st -y, r17\r
+ st -y, r18\r
+ st -y, r19\r
+ st -y, r20\r
+ st -y, r21\r
+ st -y, r22\r
+ st -y, r23\r
+ st -y, r24\r
+ st -y, r25\r
+ st -y, r26\r
+ st -y, r27\r
+ st -y, r30\r
+ st -y, r31\r
+\r
+ lds r26, pxCurrentTCB ; Finally save the software stack pointer (Y ...\r
+ lds r27, pxCurrentTCB + 1 ; ... register) into the TCB.\r
+ st x+, r28\r
+ st x+, r29\r
+\r
+ ENDM\r
+\r
+\r
+portRESTORE_CONTEXT MACRO\r
+ lds r26, pxCurrentTCB\r
+ lds r27, pxCurrentTCB + 1 ; Restore the software stack pointer from ...\r
+ ld r28, x+ ; the TCB into the software stack pointer (...\r
+ ld r29, x+ ; ... the Y register).\r
+\r
+ ld r31, y+ ; Restore the registers down to R0. The Y\r
+ ld r30, y+ ; register is missing from this list as it\r
+ ld r27, y+ ; has already been restored.\r
+ ld r26, y+ \r
+ ld r25, y+\r
+ ld r24, y+\r
+ ld r23, y+\r
+ ld r22, y+\r
+ ld r21, y+\r
+ ld r20, y+\r
+ ld r19, y+\r
+ ld r18, y+\r
+ ld r17, y+\r
+ ld r16, y+\r
+ ld r15, y+\r
+ ld r14, y+\r
+ ld r13, y+\r
+ ld r12, y+\r
+ ld r11, y+\r
+ ld r10, y+\r
+ ld r9, y+\r
+ ld r8, y+\r
+ ld r7, y+\r
+ ld r6, y+\r
+ ld r5, y+\r
+ ld r4, y+\r
+ ld r3, y+\r
+ ld r2, y+\r
+ ld r1, y+\r
+\r
+ ld r0, y+ ; The next thing on the stack is the ...\r
+ out SPH, r0 ; ... hardware stack pointer.\r
+ ld r0, y+\r
+ out SPL, r0\r
+\r
+ ld r0, y+ ; Next there is the SREG register.\r
+ out SREG, r0\r
+\r
+ ld r0, y+ ; Finally we have finished with r0, so restore r0.\r
+ \r
+ ENDM\r
+\r
+\r
+\r
+; vPortYield() and vPortYieldFromTick()\r
+; -------------------------------------\r
+;\r
+; Manual and preemptive context switch functions respectively. \r
+; The IAR compiler does not fully support inline assembler, \r
+; so these are implemented here rather than the more usually \r
+; place of within port.c.\r
+\r
+vPortYield:\r
+ portSAVE_CONTEXT ; Save the context of the current task.\r
+ call vTaskSwitchContext ; Call the scheduler.\r
+ portRESTORE_CONTEXT ; Restore the context of whichever task the ...\r
+ ret ; ... scheduler decided should run.\r
+\r
+vPortYieldFromTick:\r
+ portSAVE_CONTEXT ; Save the context of the current task.\r
+ call vTaskIncrementTick ; Call the timer tick function.\r
+ call vTaskSwitchContext ; Call the scheduler.\r
+ portRESTORE_CONTEXT ; Restore the context of whichever task the ...\r
+ ret ; ... scheduler decided should run.\r
+\r
+; vPortStart()\r
+; ------------\r
+;\r
+; Again due to the lack of inline assembler, this is required\r
+; to get access to the portRESTORE_CONTEXT macro.\r
+\r
+vPortStart:\r
+ portRESTORE_CONTEXT\r
+ ret\r
+\r
+\r
+; Just a filler for unused interrupt vectors.\r
+vNoISR:\r
+ reti\r
+\r
+\r
+ END\r
+\r
--- /dev/null
+// ----------------------------------------------------------------------------\r
+// ATMEL Microcontroller Software Support - ROUSSET -\r
+// ----------------------------------------------------------------------------\r
+// The software is delivered "AS IS" without warranty or condition of any\r
+// kind, either express, implied or statutory. This includes without\r
+// limitation any warranty or condition with respect to merchantability or\r
+// fitness for any particular purpose, or against the infringements of\r
+// intellectual property rights of others.\r
+// ----------------------------------------------------------------------------\r
+// File Name : AT91SAM7S64.h\r
+// Object : AT91SAM7S64 definitions\r
+// Generated : AT91 SW Application Group 07/16/2004 (07:43:08)\r
+// \r
+// CVS Reference : /AT91SAM7S64.pl/1.12/Mon Jul 12 13:02:30 2004//\r
+// CVS Reference : /SYSC_SAM7Sxx.pl/1.5/Mon Jul 12 16:22:12 2004//\r
+// CVS Reference : /MC_SAM02.pl/1.3/Wed Mar 10 08:37:04 2004//\r
+// CVS Reference : /UDP_1765B.pl/1.3/Fri Aug 2 14:45:38 2002//\r
+// CVS Reference : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:48 2002//\r
+// CVS Reference : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004//\r
+// CVS Reference : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:48 2002//\r
+// CVS Reference : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003//\r
+// CVS Reference : /US_1739C.pl/1.2/Mon Jul 12 17:26:24 2004//\r
+// CVS Reference : /SPI2.pl/1.2/Fri Oct 17 08:13:40 2003//\r
+// CVS Reference : /SSC_1762A.pl/1.2/Fri Nov 8 13:26:40 2002//\r
+// CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//\r
+// CVS Reference : /TWI_1761B.pl/1.4/Fri Feb 7 10:30:08 2003//\r
+// CVS Reference : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:24 2002//\r
+// CVS Reference : /ADC_SAM.pl/1.7/Fri Oct 17 08:12:38 2003//\r
+// CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//\r
+// ----------------------------------------------------------------------------\r
+\r
+#ifndef AT91SAM7S64_H\r
+#define AT91SAM7S64_H\r
+\r
+typedef volatile unsigned int AT91_REG;// Hardware register definition\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR System Peripherals\r
+// *****************************************************************************\r
+typedef struct _AT91S_SYSC {\r
+ AT91_REG SYSC_AIC_SMR[32]; // Source Mode Register\r
+ AT91_REG SYSC_AIC_SVR[32]; // Source Vector Register\r
+ AT91_REG SYSC_AIC_IVR; // IRQ Vector Register\r
+ AT91_REG SYSC_AIC_FVR; // FIQ Vector Register\r
+ AT91_REG SYSC_AIC_ISR; // Interrupt Status Register\r
+ AT91_REG SYSC_AIC_IPR; // Interrupt Pending Register\r
+ AT91_REG SYSC_AIC_IMR; // Interrupt Mask Register\r
+ AT91_REG SYSC_AIC_CISR; // Core Interrupt Status Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG SYSC_AIC_IECR; // Interrupt Enable Command Register\r
+ AT91_REG SYSC_AIC_IDCR; // Interrupt Disable Command Register\r
+ AT91_REG SYSC_AIC_ICCR; // Interrupt Clear Command Register\r
+ AT91_REG SYSC_AIC_ISCR; // Interrupt Set Command Register\r
+ AT91_REG SYSC_AIC_EOICR; // End of Interrupt Command Register\r
+ AT91_REG SYSC_AIC_SPU; // Spurious Vector Register\r
+ AT91_REG SYSC_AIC_DCR; // Debug Control Register (Protect)\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG SYSC_AIC_FFER; // Fast Forcing Enable Register\r
+ AT91_REG SYSC_AIC_FFDR; // Fast Forcing Disable Register\r
+ AT91_REG SYSC_AIC_FFSR; // Fast Forcing Status Register\r
+ AT91_REG Reserved2[45]; // \r
+ AT91_REG SYSC_DBGU_CR; // Control Register\r
+ AT91_REG SYSC_DBGU_MR; // Mode Register\r
+ AT91_REG SYSC_DBGU_IER; // Interrupt Enable Register\r
+ AT91_REG SYSC_DBGU_IDR; // Interrupt Disable Register\r
+ AT91_REG SYSC_DBGU_IMR; // Interrupt Mask Register\r
+ AT91_REG SYSC_DBGU_CSR; // Channel Status Register\r
+ AT91_REG SYSC_DBGU_RHR; // Receiver Holding Register\r
+ AT91_REG SYSC_DBGU_THR; // Transmitter Holding Register\r
+ AT91_REG SYSC_DBGU_BRGR; // Baud Rate Generator Register\r
+ AT91_REG Reserved3[7]; // \r
+ AT91_REG SYSC_DBGU_C1R; // Chip ID1 Register\r
+ AT91_REG SYSC_DBGU_C2R; // Chip ID2 Register\r
+ AT91_REG SYSC_DBGU_FNTR; // Force NTRST Register\r
+ AT91_REG Reserved4[45]; // \r
+ AT91_REG SYSC_DBGU_RPR; // Receive Pointer Register\r
+ AT91_REG SYSC_DBGU_RCR; // Receive Counter Register\r
+ AT91_REG SYSC_DBGU_TPR; // Transmit Pointer Register\r
+ AT91_REG SYSC_DBGU_TCR; // Transmit Counter Register\r
+ AT91_REG SYSC_DBGU_RNPR; // Receive Next Pointer Register\r
+ AT91_REG SYSC_DBGU_RNCR; // Receive Next Counter Register\r
+ AT91_REG SYSC_DBGU_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG SYSC_DBGU_TNCR; // Transmit Next Counter Register\r
+ AT91_REG SYSC_DBGU_PTCR; // PDC Transfer Control Register\r
+ AT91_REG SYSC_DBGU_PTSR; // PDC Transfer Status Register\r
+ AT91_REG Reserved5[54]; // \r
+ AT91_REG SYSC_PIOA_PER; // PIO Enable Register\r
+ AT91_REG SYSC_PIOA_PDR; // PIO Disable Register\r
+ AT91_REG SYSC_PIOA_PSR; // PIO Status Register\r
+ AT91_REG Reserved6[1]; // \r
+ AT91_REG SYSC_PIOA_OER; // Output Enable Register\r
+ AT91_REG SYSC_PIOA_ODR; // Output Disable Registerr\r
+ AT91_REG SYSC_PIOA_OSR; // Output Status Register\r
+ AT91_REG Reserved7[1]; // \r
+ AT91_REG SYSC_PIOA_IFER; // Input Filter Enable Register\r
+ AT91_REG SYSC_PIOA_IFDR; // Input Filter Disable Register\r
+ AT91_REG SYSC_PIOA_IFSR; // Input Filter Status Register\r
+ AT91_REG Reserved8[1]; // \r
+ AT91_REG SYSC_PIOA_SODR; // Set Output Data Register\r
+ AT91_REG SYSC_PIOA_CODR; // Clear Output Data Register\r
+ AT91_REG SYSC_PIOA_ODSR; // Output Data Status Register\r
+ AT91_REG SYSC_PIOA_PDSR; // Pin Data Status Register\r
+ AT91_REG SYSC_PIOA_IER; // Interrupt Enable Register\r
+ AT91_REG SYSC_PIOA_IDR; // Interrupt Disable Register\r
+ AT91_REG SYSC_PIOA_IMR; // Interrupt Mask Register\r
+ AT91_REG SYSC_PIOA_ISR; // Interrupt Status Register\r
+ AT91_REG SYSC_PIOA_MDER; // Multi-driver Enable Register\r
+ AT91_REG SYSC_PIOA_MDDR; // Multi-driver Disable Register\r
+ AT91_REG SYSC_PIOA_MDSR; // Multi-driver Status Register\r
+ AT91_REG Reserved9[1]; // \r
+ AT91_REG SYSC_PIOA_PPUDR; // Pull-up Disable Register\r
+ AT91_REG SYSC_PIOA_PPUER; // Pull-up Enable Register\r
+ AT91_REG SYSC_PIOA_PPUSR; // Pad Pull-up Status Register\r
+ AT91_REG Reserved10[1]; // \r
+ AT91_REG SYSC_PIOA_ASR; // Select A Register\r
+ AT91_REG SYSC_PIOA_BSR; // Select B Register\r
+ AT91_REG SYSC_PIOA_ABSR; // AB Select Status Register\r
+ AT91_REG Reserved11[9]; // \r
+ AT91_REG SYSC_PIOA_OWER; // Output Write Enable Register\r
+ AT91_REG SYSC_PIOA_OWDR; // Output Write Disable Register\r
+ AT91_REG SYSC_PIOA_OWSR; // Output Write Status Register\r
+ AT91_REG Reserved12[469]; // \r
+ AT91_REG SYSC_PMC_SCER; // System Clock Enable Register\r
+ AT91_REG SYSC_PMC_SCDR; // System Clock Disable Register\r
+ AT91_REG SYSC_PMC_SCSR; // System Clock Status Register\r
+ AT91_REG Reserved13[1]; // \r
+ AT91_REG SYSC_PMC_PCER; // Peripheral Clock Enable Register\r
+ AT91_REG SYSC_PMC_PCDR; // Peripheral Clock Disable Register\r
+ AT91_REG SYSC_PMC_PCSR; // Peripheral Clock Status Register\r
+ AT91_REG Reserved14[1]; // \r
+ AT91_REG SYSC_PMC_MOR; // Main Oscillator Register\r
+ AT91_REG SYSC_PMC_MCFR; // Main Clock Frequency Register\r
+ AT91_REG Reserved15[1]; // \r
+ AT91_REG SYSC_PMC_PLLR; // PLL Register\r
+ AT91_REG SYSC_PMC_MCKR; // Master Clock Register\r
+ AT91_REG Reserved16[3]; // \r
+ AT91_REG SYSC_PMC_PCKR[8]; // Programmable Clock Register\r
+ AT91_REG SYSC_PMC_IER; // Interrupt Enable Register\r
+ AT91_REG SYSC_PMC_IDR; // Interrupt Disable Register\r
+ AT91_REG SYSC_PMC_SR; // Status Register\r
+ AT91_REG SYSC_PMC_IMR; // Interrupt Mask Register\r
+ AT91_REG Reserved17[36]; // \r
+ AT91_REG SYSC_RSTC_RCR; // Reset Control Register\r
+ AT91_REG SYSC_RSTC_RSR; // Reset Status Register\r
+ AT91_REG SYSC_RSTC_RMR; // Reset Mode Register\r
+ AT91_REG Reserved18[5]; // \r
+ AT91_REG SYSC_RTTC_RTMR; // Real-time Mode Register\r
+ AT91_REG SYSC_RTTC_RTAR; // Real-time Alarm Register\r
+ AT91_REG SYSC_RTTC_RTVR; // Real-time Value Register\r
+ AT91_REG SYSC_RTTC_RTSR; // Real-time Status Register\r
+ AT91_REG SYSC_PITC_PIMR; // Period Interval Mode Register\r
+ AT91_REG SYSC_PITC_PISR; // Period Interval Status Register\r
+ AT91_REG SYSC_PITC_PIVR; // Period Interval Value Register\r
+ AT91_REG SYSC_PITC_PIIR; // Period Interval Image Register\r
+ AT91_REG SYSC_WDTC_WDCR; // Watchdog Control Register\r
+ AT91_REG SYSC_WDTC_WDMR; // Watchdog Mode Register\r
+ AT91_REG SYSC_WDTC_WDSR; // Watchdog Status Register\r
+ AT91_REG Reserved19[5]; // \r
+ AT91_REG SYSC_SYSC_VRPM; // Voltage Regulator Power Mode Register\r
+} AT91S_SYSC, *AT91PS_SYSC;\r
+\r
+// -------- VRPM : (SYSC Offset: 0xd60) Voltage Regulator Power Mode Register -------- \r
+#define AT91C_SYSC_PSTDBY ((unsigned int) 0x1 << 0) // (SYSC) Voltage Regulator Power Mode\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller\r
+// *****************************************************************************\r
+typedef struct _AT91S_AIC {\r
+ AT91_REG AIC_SMR[32]; // Source Mode Register\r
+ AT91_REG AIC_SVR[32]; // Source Vector Register\r
+ AT91_REG AIC_IVR; // IRQ Vector Register\r
+ AT91_REG AIC_FVR; // FIQ Vector Register\r
+ AT91_REG AIC_ISR; // Interrupt Status Register\r
+ AT91_REG AIC_IPR; // Interrupt Pending Register\r
+ AT91_REG AIC_IMR; // Interrupt Mask Register\r
+ AT91_REG AIC_CISR; // Core Interrupt Status Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG AIC_IECR; // Interrupt Enable Command Register\r
+ AT91_REG AIC_IDCR; // Interrupt Disable Command Register\r
+ AT91_REG AIC_ICCR; // Interrupt Clear Command Register\r
+ AT91_REG AIC_ISCR; // Interrupt Set Command Register\r
+ AT91_REG AIC_EOICR; // End of Interrupt Command Register\r
+ AT91_REG AIC_SPU; // Spurious Vector Register\r
+ AT91_REG AIC_DCR; // Debug Control Register (Protect)\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG AIC_FFER; // Fast Forcing Enable Register\r
+ AT91_REG AIC_FFDR; // Fast Forcing Disable Register\r
+ AT91_REG AIC_FFSR; // Fast Forcing Status Register\r
+} AT91S_AIC, *AT91PS_AIC;\r
+\r
+// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- \r
+#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level\r
+#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level\r
+#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level\r
+#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type\r
+#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive\r
+#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered\r
+#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive\r
+#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered\r
+// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- \r
+#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status\r
+#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status\r
+// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- \r
+#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode\r
+#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Debug Unit\r
+// *****************************************************************************\r
+typedef struct _AT91S_DBGU {\r
+ AT91_REG DBGU_CR; // Control Register\r
+ AT91_REG DBGU_MR; // Mode Register\r
+ AT91_REG DBGU_IER; // Interrupt Enable Register\r
+ AT91_REG DBGU_IDR; // Interrupt Disable Register\r
+ AT91_REG DBGU_IMR; // Interrupt Mask Register\r
+ AT91_REG DBGU_CSR; // Channel Status Register\r
+ AT91_REG DBGU_RHR; // Receiver Holding Register\r
+ AT91_REG DBGU_THR; // Transmitter Holding Register\r
+ AT91_REG DBGU_BRGR; // Baud Rate Generator Register\r
+ AT91_REG Reserved0[7]; // \r
+ AT91_REG DBGU_C1R; // Chip ID1 Register\r
+ AT91_REG DBGU_C2R; // Chip ID2 Register\r
+ AT91_REG DBGU_FNTR; // Force NTRST Register\r
+ AT91_REG Reserved1[45]; // \r
+ AT91_REG DBGU_RPR; // Receive Pointer Register\r
+ AT91_REG DBGU_RCR; // Receive Counter Register\r
+ AT91_REG DBGU_TPR; // Transmit Pointer Register\r
+ AT91_REG DBGU_TCR; // Transmit Counter Register\r
+ AT91_REG DBGU_RNPR; // Receive Next Pointer Register\r
+ AT91_REG DBGU_RNCR; // Receive Next Counter Register\r
+ AT91_REG DBGU_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG DBGU_TNCR; // Transmit Next Counter Register\r
+ AT91_REG DBGU_PTCR; // PDC Transfer Control Register\r
+ AT91_REG DBGU_PTSR; // PDC Transfer Status Register\r
+} AT91S_DBGU, *AT91PS_DBGU;\r
+\r
+// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- \r
+#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver\r
+#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter\r
+#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable\r
+#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable\r
+#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable\r
+#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable\r
+// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- \r
+#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type\r
+#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity\r
+#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity\r
+#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space)\r
+#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark)\r
+#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity\r
+#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode\r
+#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode\r
+#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.\r
+#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.\r
+#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.\r
+#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.\r
+// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- \r
+#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt\r
+#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt\r
+#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt\r
+#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt\r
+#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt\r
+#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt\r
+#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt\r
+#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt\r
+#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt\r
+#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt\r
+#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt\r
+#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt\r
+// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- \r
+// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- \r
+// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- \r
+// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- \r
+#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Peripheral Data Controller\r
+// *****************************************************************************\r
+typedef struct _AT91S_PDC {\r
+ AT91_REG PDC_RPR; // Receive Pointer Register\r
+ AT91_REG PDC_RCR; // Receive Counter Register\r
+ AT91_REG PDC_TPR; // Transmit Pointer Register\r
+ AT91_REG PDC_TCR; // Transmit Counter Register\r
+ AT91_REG PDC_RNPR; // Receive Next Pointer Register\r
+ AT91_REG PDC_RNCR; // Receive Next Counter Register\r
+ AT91_REG PDC_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG PDC_TNCR; // Transmit Next Counter Register\r
+ AT91_REG PDC_PTCR; // PDC Transfer Control Register\r
+ AT91_REG PDC_PTSR; // PDC Transfer Status Register\r
+} AT91S_PDC, *AT91PS_PDC;\r
+\r
+// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- \r
+#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable\r
+#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable\r
+#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable\r
+#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable\r
+// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Parallel Input Output Controler\r
+// *****************************************************************************\r
+typedef struct _AT91S_PIO {\r
+ AT91_REG PIO_PER; // PIO Enable Register\r
+ AT91_REG PIO_PDR; // PIO Disable Register\r
+ AT91_REG PIO_PSR; // PIO Status Register\r
+ AT91_REG Reserved0[1]; // \r
+ AT91_REG PIO_OER; // Output Enable Register\r
+ AT91_REG PIO_ODR; // Output Disable Registerr\r
+ AT91_REG PIO_OSR; // Output Status Register\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG PIO_IFER; // Input Filter Enable Register\r
+ AT91_REG PIO_IFDR; // Input Filter Disable Register\r
+ AT91_REG PIO_IFSR; // Input Filter Status Register\r
+ AT91_REG Reserved2[1]; // \r
+ AT91_REG PIO_SODR; // Set Output Data Register\r
+ AT91_REG PIO_CODR; // Clear Output Data Register\r
+ AT91_REG PIO_ODSR; // Output Data Status Register\r
+ AT91_REG PIO_PDSR; // Pin Data Status Register\r
+ AT91_REG PIO_IER; // Interrupt Enable Register\r
+ AT91_REG PIO_IDR; // Interrupt Disable Register\r
+ AT91_REG PIO_IMR; // Interrupt Mask Register\r
+ AT91_REG PIO_ISR; // Interrupt Status Register\r
+ AT91_REG PIO_MDER; // Multi-driver Enable Register\r
+ AT91_REG PIO_MDDR; // Multi-driver Disable Register\r
+ AT91_REG PIO_MDSR; // Multi-driver Status Register\r
+ AT91_REG Reserved3[1]; // \r
+ AT91_REG PIO_PPUDR; // Pull-up Disable Register\r
+ AT91_REG PIO_PPUER; // Pull-up Enable Register\r
+ AT91_REG PIO_PPUSR; // Pad Pull-up Status Register\r
+ AT91_REG Reserved4[1]; // \r
+ AT91_REG PIO_ASR; // Select A Register\r
+ AT91_REG PIO_BSR; // Select B Register\r
+ AT91_REG PIO_ABSR; // AB Select Status Register\r
+ AT91_REG Reserved5[9]; // \r
+ AT91_REG PIO_OWER; // Output Write Enable Register\r
+ AT91_REG PIO_OWDR; // Output Write Disable Register\r
+ AT91_REG PIO_OWSR; // Output Write Status Register\r
+} AT91S_PIO, *AT91PS_PIO;\r
+\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Clock Generator Controler\r
+// *****************************************************************************\r
+typedef struct _AT91S_CKGR {\r
+ AT91_REG CKGR_MOR; // Main Oscillator Register\r
+ AT91_REG CKGR_MCFR; // Main Clock Frequency Register\r
+ AT91_REG Reserved0[1]; // \r
+ AT91_REG CKGR_PLLR; // PLL Register\r
+} AT91S_CKGR, *AT91PS_CKGR;\r
+\r
+// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- \r
+#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable\r
+#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass\r
+#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time\r
+// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- \r
+#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency\r
+#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready\r
+// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- \r
+#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected\r
+#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0\r
+#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed\r
+#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter\r
+#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range\r
+#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet\r
+#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet\r
+#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet\r
+#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet\r
+#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier\r
+#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks\r
+#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output\r
+#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2\r
+#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Power Management Controler\r
+// *****************************************************************************\r
+typedef struct _AT91S_PMC {\r
+ AT91_REG PMC_SCER; // System Clock Enable Register\r
+ AT91_REG PMC_SCDR; // System Clock Disable Register\r
+ AT91_REG PMC_SCSR; // System Clock Status Register\r
+ AT91_REG Reserved0[1]; // \r
+ AT91_REG PMC_PCER; // Peripheral Clock Enable Register\r
+ AT91_REG PMC_PCDR; // Peripheral Clock Disable Register\r
+ AT91_REG PMC_PCSR; // Peripheral Clock Status Register\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG PMC_MOR; // Main Oscillator Register\r
+ AT91_REG PMC_MCFR; // Main Clock Frequency Register\r
+ AT91_REG Reserved2[1]; // \r
+ AT91_REG PMC_PLLR; // PLL Register\r
+ AT91_REG PMC_MCKR; // Master Clock Register\r
+ AT91_REG Reserved3[3]; // \r
+ AT91_REG PMC_PCKR[8]; // Programmable Clock Register\r
+ AT91_REG PMC_IER; // Interrupt Enable Register\r
+ AT91_REG PMC_IDR; // Interrupt Disable Register\r
+ AT91_REG PMC_SR; // Status Register\r
+ AT91_REG PMC_IMR; // Interrupt Mask Register\r
+} AT91S_PMC, *AT91PS_PMC;\r
+\r
+// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- \r
+#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock\r
+#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock\r
+#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output\r
+#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output\r
+#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output\r
+#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output\r
+// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- \r
+// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- \r
+// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- \r
+// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- \r
+// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- \r
+// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- \r
+#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection\r
+#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected\r
+#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected\r
+#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected\r
+#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler\r
+#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock\r
+#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2\r
+#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4\r
+#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8\r
+#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16\r
+#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32\r
+#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64\r
+// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- \r
+// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- \r
+#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask\r
+#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask\r
+#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask\r
+// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- \r
+// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- \r
+// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Reset Controller Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_RSTC {\r
+ AT91_REG RSTC_RCR; // Reset Control Register\r
+ AT91_REG RSTC_RSR; // Reset Status Register\r
+ AT91_REG RSTC_RMR; // Reset Mode Register\r
+} AT91S_RSTC, *AT91PS_RSTC;\r
+\r
+// -------- SYSC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- \r
+#define AT91C_SYSC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset\r
+#define AT91C_SYSC_ICERST ((unsigned int) 0x1 << 1) // (RSTC) ICE Interface Reset\r
+#define AT91C_SYSC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset\r
+#define AT91C_SYSC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset\r
+#define AT91C_SYSC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password\r
+// -------- SYSC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- \r
+#define AT91C_SYSC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status\r
+#define AT91C_SYSC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brown-out Detection Status\r
+#define AT91C_SYSC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type\r
+#define AT91C_SYSC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising.\r
+#define AT91C_SYSC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.\r
+#define AT91C_SYSC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.\r
+#define AT91C_SYSC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low.\r
+#define AT91C_SYSC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brown-out Reset.\r
+#define AT91C_SYSC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level\r
+#define AT91C_SYSC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress.\r
+// -------- SYSC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- \r
+#define AT91C_SYSC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable\r
+#define AT91C_SYSC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable\r
+#define AT91C_SYSC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable\r
+#define AT91C_SYSC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brown-out Detection Interrupt Enable\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_RTTC {\r
+ AT91_REG RTTC_RTMR; // Real-time Mode Register\r
+ AT91_REG RTTC_RTAR; // Real-time Alarm Register\r
+ AT91_REG RTTC_RTVR; // Real-time Value Register\r
+ AT91_REG RTTC_RTSR; // Real-time Status Register\r
+} AT91S_RTTC, *AT91PS_RTTC;\r
+\r
+// -------- SYSC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- \r
+#define AT91C_SYSC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value\r
+#define AT91C_SYSC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable\r
+#define AT91C_SYSC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable\r
+#define AT91C_SYSC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart\r
+// -------- SYSC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- \r
+#define AT91C_SYSC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value\r
+// -------- SYSC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- \r
+#define AT91C_SYSC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value\r
+// -------- SYSC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- \r
+#define AT91C_SYSC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status\r
+#define AT91C_SYSC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_PITC {\r
+ AT91_REG PITC_PIMR; // Period Interval Mode Register\r
+ AT91_REG PITC_PISR; // Period Interval Status Register\r
+ AT91_REG PITC_PIVR; // Period Interval Value Register\r
+ AT91_REG PITC_PIIR; // Period Interval Image Register\r
+} AT91S_PITC, *AT91PS_PITC;\r
+\r
+// -------- SYSC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- \r
+#define AT91C_SYSC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value\r
+#define AT91C_SYSC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled\r
+#define AT91C_SYSC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable\r
+// -------- SYSC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- \r
+#define AT91C_SYSC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status\r
+// -------- SYSC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- \r
+#define AT91C_SYSC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value\r
+#define AT91C_SYSC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter\r
+// -------- SYSC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_WDTC {\r
+ AT91_REG WDTC_WDCR; // Watchdog Control Register\r
+ AT91_REG WDTC_WDMR; // Watchdog Mode Register\r
+ AT91_REG WDTC_WDSR; // Watchdog Status Register\r
+} AT91S_WDTC, *AT91PS_WDTC;\r
+\r
+// -------- SYSC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- \r
+#define AT91C_SYSC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart\r
+// -------- SYSC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- \r
+#define AT91C_SYSC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart\r
+#define AT91C_SYSC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable\r
+#define AT91C_SYSC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable\r
+#define AT91C_SYSC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart\r
+#define AT91C_SYSC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable\r
+#define AT91C_SYSC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value\r
+#define AT91C_SYSC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt\r
+#define AT91C_SYSC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt\r
+// -------- SYSC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- \r
+#define AT91C_SYSC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow\r
+#define AT91C_SYSC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Memory Controller Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_MC {\r
+ AT91_REG MC_RCR; // MC Remap Control Register\r
+ AT91_REG MC_ASR; // MC Abort Status Register\r
+ AT91_REG MC_AASR; // MC Abort Address Status Register\r
+ AT91_REG Reserved0[21]; // \r
+ AT91_REG MC_FMR; // MC Flash Mode Register\r
+ AT91_REG MC_FCR; // MC Flash Command Register\r
+ AT91_REG MC_FSR; // MC Flash Status Register\r
+} AT91S_MC, *AT91PS_MC;\r
+\r
+// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- \r
+#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit\r
+// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- \r
+#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status\r
+#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status\r
+#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status\r
+#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte\r
+#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word\r
+#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word\r
+#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status\r
+#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read\r
+#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write\r
+#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch\r
+#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source\r
+#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source\r
+#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source\r
+#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source\r
+// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- \r
+#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready\r
+#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error\r
+#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error\r
+#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming\r
+#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State\r
+#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations\r
+#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations\r
+#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations\r
+#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations\r
+#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number\r
+// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- \r
+#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command\r
+#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN.\r
+#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.\r
+#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.\r
+#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.\r
+#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.\r
+#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits.\r
+#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits.\r
+#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit.\r
+#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number\r
+#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key\r
+// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- \r
+#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status\r
+#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status\r
+#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status\r
+#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status\r
+#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status\r
+#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status\r
+#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status\r
+#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status\r
+#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status\r
+#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status\r
+#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status\r
+#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status\r
+#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status\r
+#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status\r
+#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status\r
+#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status\r
+#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status\r
+#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status\r
+#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status\r
+#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status\r
+#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status\r
+#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status\r
+#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status\r
+#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status\r
+#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Serial Parallel Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_SPI {\r
+ AT91_REG SPI_CR; // Control Register\r
+ AT91_REG SPI_MR; // Mode Register\r
+ AT91_REG SPI_RDR; // Receive Data Register\r
+ AT91_REG SPI_TDR; // Transmit Data Register\r
+ AT91_REG SPI_SR; // Status Register\r
+ AT91_REG SPI_IER; // Interrupt Enable Register\r
+ AT91_REG SPI_IDR; // Interrupt Disable Register\r
+ AT91_REG SPI_IMR; // Interrupt Mask Register\r
+ AT91_REG Reserved0[4]; // \r
+ AT91_REG SPI_CSR[4]; // Chip Select Register\r
+ AT91_REG Reserved1[48]; // \r
+ AT91_REG SPI_RPR; // Receive Pointer Register\r
+ AT91_REG SPI_RCR; // Receive Counter Register\r
+ AT91_REG SPI_TPR; // Transmit Pointer Register\r
+ AT91_REG SPI_TCR; // Transmit Counter Register\r
+ AT91_REG SPI_RNPR; // Receive Next Pointer Register\r
+ AT91_REG SPI_RNCR; // Receive Next Counter Register\r
+ AT91_REG SPI_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG SPI_TNCR; // Transmit Next Counter Register\r
+ AT91_REG SPI_PTCR; // PDC Transfer Control Register\r
+ AT91_REG SPI_PTSR; // PDC Transfer Status Register\r
+} AT91S_SPI, *AT91PS_SPI;\r
+\r
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- \r
+#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable\r
+#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable\r
+#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset\r
+#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer\r
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- \r
+#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode\r
+#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select\r
+#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select\r
+#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select\r
+#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode\r
+#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection\r
+#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection\r
+#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection\r
+#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select\r
+#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects\r
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- \r
+#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data\r
+#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status\r
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- \r
+#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data\r
+#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status\r
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- \r
+#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full\r
+#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty\r
+#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error\r
+#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status\r
+#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer\r
+#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer\r
+#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt\r
+#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt\r
+#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt\r
+#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt\r
+#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status\r
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- \r
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- \r
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- \r
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- \r
+#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity\r
+#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase\r
+#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 2) // (SPI) Chip Select Active After Transfer\r
+#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer\r
+#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer\r
+#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer\r
+#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer\r
+#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer\r
+#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer\r
+#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer\r
+#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer\r
+#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer\r
+#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer\r
+#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate\r
+#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Serial Clock Baud Rate\r
+#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Analog to Digital Convertor\r
+// *****************************************************************************\r
+typedef struct _AT91S_ADC {\r
+ AT91_REG ADC_CR; // ADC Control Register\r
+ AT91_REG ADC_MR; // ADC Mode Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG ADC_CHER; // ADC Channel Enable Register\r
+ AT91_REG ADC_CHDR; // ADC Channel Disable Register\r
+ AT91_REG ADC_CHSR; // ADC Channel Status Register\r
+ AT91_REG ADC_SR; // ADC Status Register\r
+ AT91_REG ADC_LCDR; // ADC Last Converted Data Register\r
+ AT91_REG ADC_IER; // ADC Interrupt Enable Register\r
+ AT91_REG ADC_IDR; // ADC Interrupt Disable Register\r
+ AT91_REG ADC_IMR; // ADC Interrupt Mask Register\r
+ AT91_REG ADC_CDR0; // ADC Channel Data Register 0\r
+ AT91_REG ADC_CDR1; // ADC Channel Data Register 1\r
+ AT91_REG ADC_CDR2; // ADC Channel Data Register 2\r
+ AT91_REG ADC_CDR3; // ADC Channel Data Register 3\r
+ AT91_REG ADC_CDR4; // ADC Channel Data Register 4\r
+ AT91_REG ADC_CDR5; // ADC Channel Data Register 5\r
+ AT91_REG ADC_CDR6; // ADC Channel Data Register 6\r
+ AT91_REG ADC_CDR7; // ADC Channel Data Register 7\r
+ AT91_REG Reserved1[44]; // \r
+ AT91_REG ADC_RPR; // Receive Pointer Register\r
+ AT91_REG ADC_RCR; // Receive Counter Register\r
+ AT91_REG ADC_TPR; // Transmit Pointer Register\r
+ AT91_REG ADC_TCR; // Transmit Counter Register\r
+ AT91_REG ADC_RNPR; // Receive Next Pointer Register\r
+ AT91_REG ADC_RNCR; // Receive Next Counter Register\r
+ AT91_REG ADC_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG ADC_TNCR; // Transmit Next Counter Register\r
+ AT91_REG ADC_PTCR; // PDC Transfer Control Register\r
+ AT91_REG ADC_PTSR; // PDC Transfer Status Register\r
+} AT91S_ADC, *AT91PS_ADC;\r
+\r
+// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- \r
+#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset\r
+#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion\r
+// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- \r
+#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable\r
+#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software\r
+#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.\r
+#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection\r
+#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0\r
+#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1\r
+#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2\r
+#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3\r
+#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4\r
+#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5\r
+#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger\r
+#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution.\r
+#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution\r
+#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution\r
+#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode\r
+#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode\r
+#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode\r
+#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection\r
+#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time\r
+#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time\r
+// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- \r
+#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0\r
+#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1\r
+#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2\r
+#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3\r
+#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4\r
+#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5\r
+#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6\r
+#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7\r
+// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- \r
+// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- \r
+// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- \r
+#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion\r
+#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error\r
+#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready\r
+#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun\r
+#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer\r
+#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt\r
+// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- \r
+#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted\r
+// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- \r
+// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- \r
+// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- \r
+// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- \r
+#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data\r
+// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- \r
+// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- \r
+// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- \r
+// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- \r
+// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- \r
+// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- \r
+// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_SSC {\r
+ AT91_REG SSC_CR; // Control Register\r
+ AT91_REG SSC_CMR; // Clock Mode Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG SSC_RCMR; // Receive Clock ModeRegister\r
+ AT91_REG SSC_RFMR; // Receive Frame Mode Register\r
+ AT91_REG SSC_TCMR; // Transmit Clock Mode Register\r
+ AT91_REG SSC_TFMR; // Transmit Frame Mode Register\r
+ AT91_REG SSC_RHR; // Receive Holding Register\r
+ AT91_REG SSC_THR; // Transmit Holding Register\r
+ AT91_REG Reserved1[2]; // \r
+ AT91_REG SSC_RSHR; // Receive Sync Holding Register\r
+ AT91_REG SSC_TSHR; // Transmit Sync Holding Register\r
+ AT91_REG SSC_RC0R; // Receive Compare 0 Register\r
+ AT91_REG SSC_RC1R; // Receive Compare 1 Register\r
+ AT91_REG SSC_SR; // Status Register\r
+ AT91_REG SSC_IER; // Interrupt Enable Register\r
+ AT91_REG SSC_IDR; // Interrupt Disable Register\r
+ AT91_REG SSC_IMR; // Interrupt Mask Register\r
+ AT91_REG Reserved2[44]; // \r
+ AT91_REG SSC_RPR; // Receive Pointer Register\r
+ AT91_REG SSC_RCR; // Receive Counter Register\r
+ AT91_REG SSC_TPR; // Transmit Pointer Register\r
+ AT91_REG SSC_TCR; // Transmit Counter Register\r
+ AT91_REG SSC_RNPR; // Receive Next Pointer Register\r
+ AT91_REG SSC_RNCR; // Receive Next Counter Register\r
+ AT91_REG SSC_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG SSC_TNCR; // Transmit Next Counter Register\r
+ AT91_REG SSC_PTCR; // PDC Transfer Control Register\r
+ AT91_REG SSC_PTSR; // PDC Transfer Status Register\r
+} AT91S_SSC, *AT91PS_SSC;\r
+\r
+// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- \r
+#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable\r
+#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable\r
+#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable\r
+#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable\r
+#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset\r
+// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- \r
+#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection\r
+#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock\r
+#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal\r
+#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin\r
+#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection\r
+#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only\r
+#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output\r
+#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output\r
+#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion\r
+#define AT91C_SSC_CKG ((unsigned int) 0x3 << 6) // (SSC) Receive/Transmit Clock Gating Selection\r
+#define AT91C_SSC_CKG_NONE ((unsigned int) 0x0 << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock\r
+#define AT91C_SSC_CKG_LOW ((unsigned int) 0x1 << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low\r
+#define AT91C_SSC_CKG_HIGH ((unsigned int) 0x2 << 6) // (SSC) Receive/Transmit Clock enabled only if RF High\r
+#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection\r
+#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.\r
+#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start\r
+#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input\r
+#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input\r
+#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input\r
+#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input\r
+#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input\r
+#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input\r
+#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0\r
+#define AT91C_SSC_STOP ((unsigned int) 0x1 << 12) // (SSC) Receive Stop Selection\r
+#define AT91C_SSC_STTOUT ((unsigned int) 0x1 << 15) // (SSC) Receive/Transmit Start Output Selection\r
+#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay\r
+#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection\r
+// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- \r
+#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length\r
+#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode\r
+#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First\r
+#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame\r
+#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length\r
+#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection\r
+#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only\r
+#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse\r
+#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse\r
+#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer\r
+#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer\r
+#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer\r
+#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection\r
+// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- \r
+// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- \r
+#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value\r
+#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable\r
+// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- \r
+#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready\r
+#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty\r
+#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission\r
+#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty\r
+#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready\r
+#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun\r
+#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception\r
+#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full\r
+#define AT91C_SSC_CP0 ((unsigned int) 0x1 << 8) // (SSC) Compare 0\r
+#define AT91C_SSC_CP1 ((unsigned int) 0x1 << 9) // (SSC) Compare 1\r
+#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync\r
+#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync\r
+#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable\r
+#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable\r
+// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- \r
+// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- \r
+// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Usart\r
+// *****************************************************************************\r
+typedef struct _AT91S_USART {\r
+ AT91_REG US_CR; // Control Register\r
+ AT91_REG US_MR; // Mode Register\r
+ AT91_REG US_IER; // Interrupt Enable Register\r
+ AT91_REG US_IDR; // Interrupt Disable Register\r
+ AT91_REG US_IMR; // Interrupt Mask Register\r
+ AT91_REG US_CSR; // Channel Status Register\r
+ AT91_REG US_RHR; // Receiver Holding Register\r
+ AT91_REG US_THR; // Transmitter Holding Register\r
+ AT91_REG US_BRGR; // Baud Rate Generator Register\r
+ AT91_REG US_RTOR; // Receiver Time-out Register\r
+ AT91_REG US_TTGR; // Transmitter Time-guard Register\r
+ AT91_REG Reserved0[5]; // \r
+ AT91_REG US_FIDI; // FI_DI_Ratio Register\r
+ AT91_REG US_NER; // Nb Errors Register\r
+ AT91_REG US_XXR; // XON_XOFF Register\r
+ AT91_REG US_IF; // IRDA_FILTER Register\r
+ AT91_REG Reserved1[44]; // \r
+ AT91_REG US_RPR; // Receive Pointer Register\r
+ AT91_REG US_RCR; // Receive Counter Register\r
+ AT91_REG US_TPR; // Transmit Pointer Register\r
+ AT91_REG US_TCR; // Transmit Counter Register\r
+ AT91_REG US_RNPR; // Receive Next Pointer Register\r
+ AT91_REG US_RNCR; // Receive Next Counter Register\r
+ AT91_REG US_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG US_TNCR; // Transmit Next Counter Register\r
+ AT91_REG US_PTCR; // PDC Transfer Control Register\r
+ AT91_REG US_PTSR; // PDC Transfer Status Register\r
+} AT91S_USART, *AT91PS_USART;\r
+\r
+// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- \r
+#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (USART) Reset Status Bits\r
+#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break\r
+#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break\r
+#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out\r
+#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address\r
+#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations\r
+#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge\r
+#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out\r
+#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable\r
+#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable\r
+#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable\r
+#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable\r
+// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- \r
+#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode\r
+#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal\r
+#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485\r
+#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking\r
+#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem\r
+#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0\r
+#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1\r
+#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA\r
+#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking\r
+#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock\r
+#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock\r
+#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1\r
+#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM)\r
+#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK)\r
+#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock\r
+#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits\r
+#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits\r
+#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits\r
+#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits\r
+#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select\r
+#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits\r
+#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit\r
+#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits\r
+#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits\r
+#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order\r
+#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length\r
+#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select\r
+#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode\r
+#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge\r
+#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK\r
+#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions\r
+#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter\r
+// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- \r
+#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break\r
+#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out\r
+#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached\r
+#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge\r
+#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag\r
+#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag\r
+#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag\r
+#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag\r
+// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- \r
+// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- \r
+// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- \r
+#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input\r
+#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input\r
+#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input\r
+#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Two-wire Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_TWI {\r
+ AT91_REG TWI_CR; // Control Register\r
+ AT91_REG TWI_MMR; // Master Mode Register\r
+ AT91_REG TWI_SMR; // Slave Mode Register\r
+ AT91_REG TWI_IADR; // Internal Address Register\r
+ AT91_REG TWI_CWGR; // Clock Waveform Generator Register\r
+ AT91_REG Reserved0[3]; // \r
+ AT91_REG TWI_SR; // Status Register\r
+ AT91_REG TWI_IER; // Interrupt Enable Register\r
+ AT91_REG TWI_IDR; // Interrupt Disable Register\r
+ AT91_REG TWI_IMR; // Interrupt Mask Register\r
+ AT91_REG TWI_RHR; // Receive Holding Register\r
+ AT91_REG TWI_THR; // Transmit Holding Register\r
+} AT91S_TWI, *AT91PS_TWI;\r
+\r
+// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- \r
+#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition\r
+#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition\r
+#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled\r
+#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled\r
+#define AT91C_TWI_SVEN ((unsigned int) 0x1 << 4) // (TWI) TWI Slave Transfer Enabled\r
+#define AT91C_TWI_SVDIS ((unsigned int) 0x1 << 5) // (TWI) TWI Slave Transfer Disabled\r
+#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset\r
+// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- \r
+#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size\r
+#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address\r
+#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address\r
+#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address\r
+#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address\r
+#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction\r
+#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address\r
+// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- \r
+#define AT91C_TWI_SADR ((unsigned int) 0x7F << 16) // (TWI) Slave Device Address\r
+// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- \r
+#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider\r
+#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider\r
+#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider\r
+// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- \r
+#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed\r
+#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY\r
+#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY\r
+#define AT91C_TWI_SVREAD ((unsigned int) 0x1 << 3) // (TWI) Slave Read\r
+#define AT91C_TWI_SVACC ((unsigned int) 0x1 << 4) // (TWI) Slave Access\r
+#define AT91C_TWI_GCACC ((unsigned int) 0x1 << 5) // (TWI) General Call Access\r
+#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error\r
+#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error\r
+#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged\r
+#define AT91C_TWI_ARBLST ((unsigned int) 0x1 << 9) // (TWI) Arbitration Lost\r
+// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- \r
+// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- \r
+// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_TC {\r
+ AT91_REG TC_CCR; // Channel Control Register\r
+ AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode)\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG TC_CV; // Counter Value\r
+ AT91_REG TC_RA; // Register A\r
+ AT91_REG TC_RB; // Register B\r
+ AT91_REG TC_RC; // Register C\r
+ AT91_REG TC_SR; // Status Register\r
+ AT91_REG TC_IER; // Interrupt Enable Register\r
+ AT91_REG TC_IDR; // Interrupt Disable Register\r
+ AT91_REG TC_IMR; // Interrupt Mask Register\r
+} AT91S_TC, *AT91PS_TC;\r
+\r
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- \r
+#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command\r
+#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command\r
+#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command\r
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- \r
+#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection\r
+#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK\r
+#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK\r
+#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK\r
+#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK\r
+#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK\r
+#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0\r
+#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1\r
+#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2\r
+#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert\r
+#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection\r
+#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal\r
+#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock\r
+#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock\r
+#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock\r
+#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare\r
+#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading\r
+#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading\r
+#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare\r
+#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection\r
+#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None\r
+#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge\r
+#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge\r
+#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge\r
+#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection\r
+#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None\r
+#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge\r
+#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge\r
+#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge\r
+#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection\r
+#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection\r
+#define AT91C_TC_EEVT_NONE ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input\r
+#define AT91C_TC_EEVT_RISING ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output\r
+#define AT91C_TC_EEVT_FALLING ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output\r
+#define AT91C_TC_EEVT_BOTH ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output\r
+#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable\r
+#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection\r
+#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare\r
+#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare\r
+#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare\r
+#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare\r
+#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable\r
+#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) \r
+#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection\r
+#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None\r
+#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA\r
+#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA\r
+#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA\r
+#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA\r
+#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none\r
+#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set\r
+#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear\r
+#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle\r
+#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection\r
+#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None\r
+#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA\r
+#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA\r
+#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA\r
+#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA\r
+#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none\r
+#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set\r
+#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear\r
+#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle\r
+#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA\r
+#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none\r
+#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set\r
+#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear\r
+#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle\r
+#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA\r
+#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none\r
+#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set\r
+#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear\r
+#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle\r
+#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB\r
+#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none\r
+#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set\r
+#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear\r
+#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle\r
+#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB\r
+#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none\r
+#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set\r
+#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear\r
+#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle\r
+#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB\r
+#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none\r
+#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set\r
+#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear\r
+#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle\r
+#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB\r
+#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none\r
+#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set\r
+#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear\r
+#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle\r
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- \r
+#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow\r
+#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun\r
+#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare\r
+#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare\r
+#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare\r
+#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading\r
+#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading\r
+#define AT91C_TC_ETRCS ((unsigned int) 0x1 << 7) // (TC) External Trigger\r
+#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 16) // (TC) Clock Enabling\r
+#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror\r
+#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror\r
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- \r
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- \r
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Timer Counter Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_TCB {\r
+ AT91S_TC TCB_TC0; // TC Channel 0\r
+ AT91_REG Reserved0[4]; // \r
+ AT91S_TC TCB_TC1; // TC Channel 1\r
+ AT91_REG Reserved1[4]; // \r
+ AT91S_TC TCB_TC2; // TC Channel 2\r
+ AT91_REG Reserved2[4]; // \r
+ AT91_REG TCB_BCR; // TC Block Control Register\r
+ AT91_REG TCB_BMR; // TC Block Mode Register\r
+} AT91S_TCB, *AT91PS_TCB;\r
+\r
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- \r
+#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command\r
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- \r
+#define AT91C_TCB_TC0XC0S ((unsigned int) 0x1 << 0) // (TCB) External Clock Signal 0 Selection\r
+#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0\r
+#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0\r
+#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0\r
+#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0\r
+#define AT91C_TCB_TC1XC1S ((unsigned int) 0x1 << 2) // (TCB) External Clock Signal 1 Selection\r
+#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1\r
+#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1\r
+#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1\r
+#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1\r
+#define AT91C_TCB_TC2XC2S ((unsigned int) 0x1 << 4) // (TCB) External Clock Signal 2 Selection\r
+#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2\r
+#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2\r
+#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2\r
+#define AT91C_TCB_TC2XC2S_TIOA2 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR PWMC Channel Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_PWMC_CH {\r
+ AT91_REG PWMC_CMR; // Channel Mode Register\r
+ AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register\r
+ AT91_REG PWMC_CPRDR; // Channel Period Register\r
+ AT91_REG PWMC_CCNTR; // Channel Counter Register\r
+ AT91_REG PWMC_CUPDR; // Channel Update Register\r
+ AT91_REG PWMC_Reserved[3]; // Reserved\r
+} AT91S_PWMC_CH, *AT91PS_PWMC_CH;\r
+\r
+// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- \r
+#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx\r
+#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH) \r
+#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH) \r
+#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH) \r
+#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment\r
+#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity\r
+#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period\r
+// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- \r
+#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle\r
+// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- \r
+#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period\r
+// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- \r
+#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter\r
+// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- \r
+#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_PWMC {\r
+ AT91_REG PWMC_MR; // PWMC Mode Register\r
+ AT91_REG PWMC_ENA; // PWMC Enable Register\r
+ AT91_REG PWMC_DIS; // PWMC Disable Register\r
+ AT91_REG PWMC_SR; // PWMC Status Register\r
+ AT91_REG PWMC_IER; // PWMC Interrupt Enable Register\r
+ AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register\r
+ AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register\r
+ AT91_REG PWMC_ISR; // PWMC Interrupt Status Register\r
+ AT91_REG Reserved0[55]; // \r
+ AT91_REG PWMC_VR; // PWMC Version Register\r
+ AT91_REG Reserved1[64]; // \r
+ AT91S_PWMC_CH PWMC_CH[32]; // PWMC Channel 0\r
+} AT91S_PWMC, *AT91PS_PWMC;\r
+\r
+// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- \r
+#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor.\r
+#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A\r
+#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC) \r
+#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor.\r
+#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B\r
+#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC) \r
+// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- \r
+#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0\r
+#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1\r
+#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2\r
+#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3\r
+#define AT91C_PWMC_CHID4 ((unsigned int) 0x1 << 4) // (PWMC) Channel ID 4\r
+#define AT91C_PWMC_CHID5 ((unsigned int) 0x1 << 5) // (PWMC) Channel ID 5\r
+#define AT91C_PWMC_CHID6 ((unsigned int) 0x1 << 6) // (PWMC) Channel ID 6\r
+#define AT91C_PWMC_CHID7 ((unsigned int) 0x1 << 7) // (PWMC) Channel ID 7\r
+// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- \r
+// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- \r
+// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- \r
+// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- \r
+// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- \r
+// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR USB Device Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_UDP {\r
+ AT91_REG UDP_NUM; // Frame Number Register\r
+ AT91_REG UDP_GLBSTATE; // Global State Register\r
+ AT91_REG UDP_FADDR; // Function Address Register\r
+ AT91_REG Reserved0[1]; // \r
+ AT91_REG UDP_IER; // Interrupt Enable Register\r
+ AT91_REG UDP_IDR; // Interrupt Disable Register\r
+ AT91_REG UDP_IMR; // Interrupt Mask Register\r
+ AT91_REG UDP_ISR; // Interrupt Status Register\r
+ AT91_REG UDP_ICR; // Interrupt Clear Register\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG UDP_RSTEP; // Reset Endpoint Register\r
+ AT91_REG Reserved2[1]; // \r
+ AT91_REG UDP_CSR[8]; // Endpoint Control and Status Register\r
+ AT91_REG UDP_FDR[8]; // Endpoint FIFO Data Register\r
+} AT91S_UDP, *AT91PS_UDP;\r
+\r
+// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- \r
+#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats\r
+#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error\r
+#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK\r
+// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- \r
+#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable\r
+#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured\r
+#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 2) // (UDP) Remote Wake Up Enable\r
+#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host\r
+// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- \r
+#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value\r
+#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable\r
+// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- \r
+#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt\r
+#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt\r
+#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt\r
+#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt\r
+#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt\r
+#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt\r
+#define AT91C_UDP_EPINT6 ((unsigned int) 0x1 << 6) // (UDP) Endpoint 6 Interrupt\r
+#define AT91C_UDP_EPINT7 ((unsigned int) 0x1 << 7) // (UDP) Endpoint 7 Interrupt\r
+#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt\r
+#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt\r
+#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt\r
+#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt\r
+#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt\r
+// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- \r
+// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- \r
+// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- \r
+#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt\r
+// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- \r
+// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- \r
+#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0\r
+#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1\r
+#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2\r
+#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3\r
+#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4\r
+#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5\r
+#define AT91C_UDP_EP6 ((unsigned int) 0x1 << 6) // (UDP) Reset Endpoint 6\r
+#define AT91C_UDP_EP7 ((unsigned int) 0x1 << 7) // (UDP) Reset Endpoint 7\r
+// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- \r
+#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR\r
+#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0\r
+#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)\r
+#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)\r
+#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready\r
+#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).\r
+#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).\r
+#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction\r
+#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type\r
+#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control\r
+#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT\r
+#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT\r
+#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT\r
+#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN\r
+#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN\r
+#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN\r
+#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle\r
+#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable\r
+#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO\r
+\r
+// *****************************************************************************\r
+// REGISTER ADDRESS DEFINITION FOR AT91SAM7S64\r
+// *****************************************************************************\r
+// ========== Register definition for SYSC peripheral ========== \r
+#define AT91C_SYSC_SYSC_VRPM ((AT91_REG *) 0xFFFFFD60) // (SYSC) Voltage Regulator Power Mode Register\r
+// ========== Register definition for AIC peripheral ========== \r
+#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register\r
+#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register\r
+#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register\r
+#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register\r
+#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register\r
+#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect)\r
+#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register\r
+#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register\r
+#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register\r
+#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register\r
+#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register\r
+#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register\r
+#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register\r
+#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register\r
+#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register\r
+#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register\r
+#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register\r
+#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register\r
+// ========== Register definition for DBGU peripheral ========== \r
+#define AT91C_DBGU_C2R ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID2 Register\r
+#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register\r
+#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register\r
+#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register\r
+#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register\r
+#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register\r
+#define AT91C_DBGU_C1R ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID1 Register\r
+#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register\r
+#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register\r
+#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register\r
+#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register\r
+#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register\r
+// ========== Register definition for PDC_DBGU peripheral ========== \r
+#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register\r
+#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register\r
+#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register\r
+#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register\r
+#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register\r
+#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register\r
+#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register\r
+#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register\r
+#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register\r
+#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register\r
+// ========== Register definition for PIOA peripheral ========== \r
+#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register\r
+#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register\r
+#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register\r
+#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register\r
+#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register\r
+#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register\r
+#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register\r
+#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register\r
+#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register\r
+#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register\r
+#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register\r
+#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register\r
+#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register\r
+#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register\r
+#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr\r
+#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register\r
+#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register\r
+#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register\r
+#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pad Pull-up Status Register\r
+#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register\r
+#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register\r
+#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register\r
+#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register\r
+#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register\r
+#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register\r
+#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register\r
+#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register\r
+#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register\r
+#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register\r
+// ========== Register definition for CKGR peripheral ========== \r
+#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register\r
+#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register\r
+#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register\r
+// ========== Register definition for PMC peripheral ========== \r
+#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register\r
+#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register\r
+#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register\r
+#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register\r
+#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register\r
+#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register\r
+#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register\r
+#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register\r
+#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register\r
+#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register\r
+#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register\r
+#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register\r
+#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register\r
+#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register\r
+#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register\r
+// ========== Register definition for RSTC peripheral ========== \r
+#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register\r
+#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register\r
+#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register\r
+// ========== Register definition for RTTC peripheral ========== \r
+#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register\r
+#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register\r
+#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register\r
+#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register\r
+// ========== Register definition for PITC peripheral ========== \r
+#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register\r
+#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register\r
+#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register\r
+#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register\r
+// ========== Register definition for WDTC peripheral ========== \r
+#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register\r
+#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register\r
+#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register\r
+// ========== Register definition for MC peripheral ========== \r
+#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register\r
+#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register\r
+#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register\r
+#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register\r
+#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register\r
+#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register\r
+// ========== Register definition for PDC_SPI peripheral ========== \r
+#define AT91C_SPI_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register\r
+#define AT91C_SPI_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register\r
+#define AT91C_SPI_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register\r
+#define AT91C_SPI_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI) Transmit Pointer Register\r
+#define AT91C_SPI_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI) Receive Pointer Register\r
+#define AT91C_SPI_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register\r
+#define AT91C_SPI_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register\r
+#define AT91C_SPI_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI) Receive Next Counter Register\r
+#define AT91C_SPI_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI) Transmit Counter Register\r
+#define AT91C_SPI_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI) Receive Counter Register\r
+// ========== Register definition for SPI peripheral ========== \r
+#define AT91C_SPI_CSR ((AT91_REG *) 0xFFFE0030) // (SPI) Chip Select Register\r
+#define AT91C_SPI_IDR ((AT91_REG *) 0xFFFE0018) // (SPI) Interrupt Disable Register\r
+#define AT91C_SPI_SR ((AT91_REG *) 0xFFFE0010) // (SPI) Status Register\r
+#define AT91C_SPI_RDR ((AT91_REG *) 0xFFFE0008) // (SPI) Receive Data Register\r
+#define AT91C_SPI_CR ((AT91_REG *) 0xFFFE0000) // (SPI) Control Register\r
+#define AT91C_SPI_IMR ((AT91_REG *) 0xFFFE001C) // (SPI) Interrupt Mask Register\r
+#define AT91C_SPI_IER ((AT91_REG *) 0xFFFE0014) // (SPI) Interrupt Enable Register\r
+#define AT91C_SPI_TDR ((AT91_REG *) 0xFFFE000C) // (SPI) Transmit Data Register\r
+#define AT91C_SPI_MR ((AT91_REG *) 0xFFFE0004) // (SPI) Mode Register\r
+// ========== Register definition for PDC_ADC peripheral ========== \r
+#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register\r
+#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register\r
+#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register\r
+#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register\r
+#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register\r
+#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register\r
+#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register\r
+#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register\r
+#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register\r
+#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register\r
+// ========== Register definition for ADC peripheral ========== \r
+#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register\r
+#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4\r
+#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2\r
+#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0\r
+#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7\r
+#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1\r
+#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3\r
+#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5\r
+#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register\r
+#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6\r
+#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register\r
+#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register\r
+#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register\r
+#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register\r
+#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register\r
+#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register\r
+#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register\r
+#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register\r
+// ========== Register definition for PDC_SSC peripheral ========== \r
+#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register\r
+#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register\r
+#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register\r
+#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register\r
+#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register\r
+#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register\r
+#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register\r
+#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register\r
+#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register\r
+#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register\r
+// ========== Register definition for SSC peripheral ========== \r
+#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register\r
+#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register\r
+#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register\r
+#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register\r
+#define AT91C_SSC_RC0R ((AT91_REG *) 0xFFFD4038) // (SSC) Receive Compare 0 Register\r
+#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register\r
+#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register\r
+#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register\r
+#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister\r
+#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register\r
+#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register\r
+#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register\r
+#define AT91C_SSC_RC1R ((AT91_REG *) 0xFFFD403C) // (SSC) Receive Compare 1 Register\r
+#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register\r
+#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register\r
+#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register\r
+// ========== Register definition for PDC_US1 peripheral ========== \r
+#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register\r
+#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register\r
+#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register\r
+#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register\r
+#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register\r
+#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register\r
+#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register\r
+#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register\r
+#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register\r
+#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register\r
+// ========== Register definition for US1 peripheral ========== \r
+#define AT91C_US1_XXR ((AT91_REG *) 0xFFFC4048) // (US1) XON_XOFF Register\r
+#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register\r
+#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register\r
+#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register\r
+#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register\r
+#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register\r
+#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register\r
+#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register\r
+#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register\r
+#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register\r
+#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register\r
+#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register\r
+#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register\r
+#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register\r
+#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register\r
+// ========== Register definition for PDC_US0 peripheral ========== \r
+#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register\r
+#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register\r
+#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register\r
+#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register\r
+#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register\r
+#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register\r
+#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register\r
+#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register\r
+#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register\r
+#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register\r
+// ========== Register definition for US0 peripheral ========== \r
+#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register\r
+#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register\r
+#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register\r
+#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register\r
+#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register\r
+#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register\r
+#define AT91C_US0_XXR ((AT91_REG *) 0xFFFC0048) // (US0) XON_XOFF Register\r
+#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register\r
+#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register\r
+#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register\r
+#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register\r
+#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register\r
+#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register\r
+#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register\r
+#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register\r
+// ========== Register definition for TWI peripheral ========== \r
+#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register\r
+#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register\r
+#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register\r
+#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register\r
+#define AT91C_TWI_SMR ((AT91_REG *) 0xFFFB8008) // (TWI) Slave Mode Register\r
+#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register\r
+#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register\r
+#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register\r
+#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register\r
+#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register\r
+#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register\r
+// ========== Register definition for TC2 peripheral ========== \r
+#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register\r
+#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register\r
+#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C\r
+#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A\r
+#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register\r
+#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register\r
+#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B\r
+#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value\r
+#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register\r
+// ========== Register definition for TC1 peripheral ========== \r
+#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register\r
+#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register\r
+#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C\r
+#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A\r
+#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register\r
+#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register\r
+#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B\r
+#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value\r
+#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register\r
+// ========== Register definition for TC0 peripheral ========== \r
+#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register\r
+#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register\r
+#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C\r
+#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A\r
+#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register\r
+#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register\r
+#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B\r
+#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value\r
+#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register\r
+// ========== Register definition for TCB peripheral ========== \r
+#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register\r
+#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register\r
+// ========== Register definition for PWMC_CH3 peripheral ========== \r
+#define AT91C_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register\r
+#define AT91C_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register\r
+#define AT91C_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register\r
+#define AT91C_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved\r
+#define AT91C_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register\r
+#define AT91C_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register\r
+// ========== Register definition for PWMC_CH2 peripheral ========== \r
+#define AT91C_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register\r
+#define AT91C_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register\r
+#define AT91C_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register\r
+#define AT91C_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved\r
+#define AT91C_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register\r
+#define AT91C_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register\r
+// ========== Register definition for PWMC_CH1 peripheral ========== \r
+#define AT91C_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register\r
+#define AT91C_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register\r
+#define AT91C_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register\r
+#define AT91C_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved\r
+#define AT91C_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register\r
+#define AT91C_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register\r
+// ========== Register definition for PWMC_CH0 peripheral ========== \r
+#define AT91C_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register\r
+#define AT91C_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register\r
+#define AT91C_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register\r
+#define AT91C_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved\r
+#define AT91C_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register\r
+#define AT91C_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register\r
+// ========== Register definition for PWMC peripheral ========== \r
+#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register\r
+#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register\r
+#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register\r
+#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register\r
+#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register\r
+#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register\r
+#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register\r
+#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register\r
+#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register\r
+// ========== Register definition for UDP peripheral ========== \r
+#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register\r
+#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register\r
+#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register\r
+#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register\r
+#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register\r
+#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register\r
+#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register\r
+#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register\r
+#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register\r
+#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register\r
+#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register\r
+\r
+// *****************************************************************************\r
+// PIO DEFINITIONS FOR AT91SAM7S64\r
+// *****************************************************************************\r
+#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0\r
+#define AT91C_PA0_PWM0 ((unsigned int) AT91C_PIO_PA0) // PWM Channel 0\r
+#define AT91C_PA0_TIOA0 ((unsigned int) AT91C_PIO_PA0) // Timer Counter 0 Multipurpose Timer I/O Pin A\r
+#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1\r
+#define AT91C_PA1_PWM1 ((unsigned int) AT91C_PIO_PA1) // PWM Channel 1\r
+#define AT91C_PA1_TIOB0 ((unsigned int) AT91C_PIO_PA1) // Timer Counter 0 Multipurpose Timer I/O Pin B\r
+#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10\r
+#define AT91C_PA10_DTXD ((unsigned int) AT91C_PIO_PA10) // DBGU Debug Transmit Data\r
+#define AT91C_PA10_NPCS2 ((unsigned int) AT91C_PIO_PA10) // SPI Peripheral Chip Select 2\r
+#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11\r
+#define AT91C_PA11_NPCS0 ((unsigned int) AT91C_PIO_PA11) // SPI Peripheral Chip Select 0\r
+#define AT91C_PA11_PWM0 ((unsigned int) AT91C_PIO_PA11) // PWM Channel 0\r
+#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12\r
+#define AT91C_PA12_MISO ((unsigned int) AT91C_PIO_PA12) // SPI Master In Slave\r
+#define AT91C_PA12_PWM1 ((unsigned int) AT91C_PIO_PA12) // PWM Channel 1\r
+#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13\r
+#define AT91C_PA13_MOSI ((unsigned int) AT91C_PIO_PA13) // SPI Master Out Slave\r
+#define AT91C_PA13_PWM2 ((unsigned int) AT91C_PIO_PA13) // PWM Channel 2\r
+#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14\r
+#define AT91C_PA14_SPCK ((unsigned int) AT91C_PIO_PA14) // SPI Serial Clock\r
+#define AT91C_PA14_PWM3 ((unsigned int) AT91C_PIO_PA14) // PWM Channel 3\r
+#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15\r
+#define AT91C_PA15_TF ((unsigned int) AT91C_PIO_PA15) // SSC Transmit Frame Sync\r
+#define AT91C_PA15_TIOA1 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 1 Multipurpose Timer I/O Pin A\r
+#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16\r
+#define AT91C_PA16_TK ((unsigned int) AT91C_PIO_PA16) // SSC Transmit Clock\r
+#define AT91C_PA16_TIOB1 ((unsigned int) AT91C_PIO_PA16) // Timer Counter 1 Multipurpose Timer I/O Pin B\r
+#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17\r
+#define AT91C_PA17_TD ((unsigned int) AT91C_PIO_PA17) // SSC Transmit data\r
+#define AT91C_PA17_PCK1 ((unsigned int) AT91C_PIO_PA17) // PMC Programmable Clock Output 1\r
+#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18\r
+#define AT91C_PA18_RD ((unsigned int) AT91C_PIO_PA18) // SSC Receive Data\r
+#define AT91C_PA18_PCK2 ((unsigned int) AT91C_PIO_PA18) // PMC Programmable Clock Output 2\r
+#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19\r
+#define AT91C_PA19_RK ((unsigned int) AT91C_PIO_PA19) // SSC Receive Clock\r
+#define AT91C_PA19_FIQ ((unsigned int) AT91C_PIO_PA19) // AIC Fast Interrupt Input\r
+#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2\r
+#define AT91C_PA2_PWM2 ((unsigned int) AT91C_PIO_PA2) // PWM Channel 2\r
+#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock\r
+#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20\r
+#define AT91C_PA20_RF ((unsigned int) AT91C_PIO_PA20) // SSC Receive Frame Sync\r
+#define AT91C_PA20_IRQ0 ((unsigned int) AT91C_PIO_PA20) // External Interrupt 0\r
+#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21\r
+#define AT91C_PA21_RXD1 ((unsigned int) AT91C_PIO_PA21) // USART 1 Receive Data\r
+#define AT91C_PA21_PCK1 ((unsigned int) AT91C_PIO_PA21) // PMC Programmable Clock Output 1\r
+#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22\r
+#define AT91C_PA22_TXD1 ((unsigned int) AT91C_PIO_PA22) // USART 1 Transmit Data\r
+#define AT91C_PA22_NPCS3 ((unsigned int) AT91C_PIO_PA22) // SPI Peripheral Chip Select 3\r
+#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23\r
+#define AT91C_PA23_SCK1 ((unsigned int) AT91C_PIO_PA23) // USART 1 Serial Clock\r
+#define AT91C_PA23_PWM0 ((unsigned int) AT91C_PIO_PA23) // PWM Channel 0\r
+#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24\r
+#define AT91C_PA24_RTS1 ((unsigned int) AT91C_PIO_PA24) // USART 1 Ready To Send\r
+#define AT91C_PA24_PWM1 ((unsigned int) AT91C_PIO_PA24) // PWM Channel 1\r
+#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25\r
+#define AT91C_PA25_CTS1 ((unsigned int) AT91C_PIO_PA25) // USART 1 Clear To Send\r
+#define AT91C_PA25_PWM2 ((unsigned int) AT91C_PIO_PA25) // PWM Channel 2\r
+#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26\r
+#define AT91C_PA26_DCD1 ((unsigned int) AT91C_PIO_PA26) // USART 1 Data Carrier Detect\r
+#define AT91C_PA26_TIOA2 ((unsigned int) AT91C_PIO_PA26) // Timer Counter 2 Multipurpose Timer I/O Pin A\r
+#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27\r
+#define AT91C_PA27_DTR1 ((unsigned int) AT91C_PIO_PA27) // USART 1 Data Terminal ready\r
+#define AT91C_PA27_TIOB2 ((unsigned int) AT91C_PIO_PA27) // Timer Counter 2 Multipurpose Timer I/O Pin B\r
+#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28\r
+#define AT91C_PA28_DSR1 ((unsigned int) AT91C_PIO_PA28) // USART 1 Data Set ready\r
+#define AT91C_PA28_TCLK1 ((unsigned int) AT91C_PIO_PA28) // Timer Counter 1 external clock input\r
+#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29\r
+#define AT91C_PA29_RI1 ((unsigned int) AT91C_PIO_PA29) // USART 1 Ring Indicator\r
+#define AT91C_PA29_TCLK2 ((unsigned int) AT91C_PIO_PA29) // Timer Counter 2 external clock input\r
+#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3\r
+#define AT91C_PA3_TWD ((unsigned int) AT91C_PIO_PA3) // TWI Two-wire Serial Data\r
+#define AT91C_PA3_NPCS3 ((unsigned int) AT91C_PIO_PA3) // SPI Peripheral Chip Select 3\r
+#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30\r
+#define AT91C_PA30_IRQ1 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 1\r
+#define AT91C_PA30_NPCS2 ((unsigned int) AT91C_PIO_PA30) // SPI Peripheral Chip Select 2\r
+#define AT91C_PIO_PA31 ((unsigned int) 1 << 31) // Pin Controlled by PA31\r
+#define AT91C_PA31_NPCS1 ((unsigned int) AT91C_PIO_PA31) // SPI Peripheral Chip Select 1\r
+#define AT91C_PA31_PCK2 ((unsigned int) AT91C_PIO_PA31) // PMC Programmable Clock Output 2\r
+#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4\r
+#define AT91C_PA4_TWCK ((unsigned int) AT91C_PIO_PA4) // TWI Two-wire Serial Clock\r
+#define AT91C_PA4_TCLK0 ((unsigned int) AT91C_PIO_PA4) // Timer Counter 0 external clock input\r
+#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5\r
+#define AT91C_PA5_RXD0 ((unsigned int) AT91C_PIO_PA5) // USART 0 Receive Data\r
+#define AT91C_PA5_NPCS3 ((unsigned int) AT91C_PIO_PA5) // SPI Peripheral Chip Select 3\r
+#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6\r
+#define AT91C_PA6_TXD0 ((unsigned int) AT91C_PIO_PA6) // USART 0 Transmit Data\r
+#define AT91C_PA6_PCK0 ((unsigned int) AT91C_PIO_PA6) // PMC Programmable Clock Output 0\r
+#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7\r
+#define AT91C_PA7_RTS0 ((unsigned int) AT91C_PIO_PA7) // USART 0 Ready To Send\r
+#define AT91C_PA7_PWM3 ((unsigned int) AT91C_PIO_PA7) // PWM Channel 3\r
+#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8\r
+#define AT91C_PA8_CTS0 ((unsigned int) AT91C_PIO_PA8) // USART 0 Clear To Send\r
+#define AT91C_PA8_ADTRG ((unsigned int) AT91C_PIO_PA8) // ADC External Trigger\r
+#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9\r
+#define AT91C_PA9_DRXD ((unsigned int) AT91C_PIO_PA9) // DBGU Debug Receive Data\r
+#define AT91C_PA9_NPCS1 ((unsigned int) AT91C_PIO_PA9) // SPI Peripheral Chip Select 1\r
+\r
+// *****************************************************************************\r
+// PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64\r
+// *****************************************************************************\r
+#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ)\r
+#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral\r
+#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller\r
+#define AT91C_ID_3_Reserved ((unsigned int) 3) // Reserved\r
+#define AT91C_ID_ADC ((unsigned int) 4) // Analog-to-Digital Converter\r
+#define AT91C_ID_SPI ((unsigned int) 5) // Serial Peripheral Interface\r
+#define AT91C_ID_US0 ((unsigned int) 6) // USART 0\r
+#define AT91C_ID_US1 ((unsigned int) 7) // USART 1\r
+#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller\r
+#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface\r
+#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller\r
+#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port\r
+#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0\r
+#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1\r
+#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2\r
+#define AT91C_ID_15_Reserved ((unsigned int) 15) // Reserved\r
+#define AT91C_ID_16_Reserved ((unsigned int) 16) // Reserved\r
+#define AT91C_ID_17_Reserved ((unsigned int) 17) // Reserved\r
+#define AT91C_ID_18_Reserved ((unsigned int) 18) // Reserved\r
+#define AT91C_ID_19_Reserved ((unsigned int) 19) // Reserved\r
+#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved\r
+#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved\r
+#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved\r
+#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved\r
+#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved\r
+#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved\r
+#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved\r
+#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved\r
+#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved\r
+#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved\r
+#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0)\r
+#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1)\r
+\r
+// *****************************************************************************\r
+// BASE ADDRESS DEFINITIONS FOR AT91SAM7S64\r
+// *****************************************************************************\r
+#define AT91C_BASE_SYSC ((AT91PS_SYSC) 0xFFFFF000) // (SYSC) Base Address\r
+#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address\r
+#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address\r
+#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address\r
+#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address\r
+#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address\r
+#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address\r
+#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address\r
+#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address\r
+#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address\r
+#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address\r
+#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address\r
+#define AT91C_BASE_PDC_SPI ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI) Base Address\r
+#define AT91C_BASE_SPI ((AT91PS_SPI) 0xFFFE0000) // (SPI) Base Address\r
+#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address\r
+#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address\r
+#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address\r
+#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address\r
+#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address\r
+#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address\r
+#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address\r
+#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address\r
+#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address\r
+#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address\r
+#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address\r
+#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address\r
+#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address\r
+#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address\r
+#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address\r
+#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address\r
+#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address\r
+#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address\r
+#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address\r
+\r
+// *****************************************************************************\r
+// MEMORY MAPPING DEFINITIONS FOR AT91SAM7S64\r
+// *****************************************************************************\r
+#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address\r
+#define AT91C_ISRAM_SIZE ((unsigned int) 0x00004000) // Internal SRAM size in byte (16 Kbyte)\r
+#define AT91C_IFLASH ((char *) 0x00100000) // Internal ROM base address\r
+#define AT91C_IFLASH_SIZE ((unsigned int) 0x00010000) // Internal ROM size in byte (64 Kbyte)\r
+\r
+#endif\r
--- /dev/null
+// ----------------------------------------------------------------------------\r
+// ATMEL Microcontroller Software Support - ROUSSET -\r
+// ----------------------------------------------------------------------------\r
+// The software is delivered "AS IS" without warranty or condition of any\r
+// kind, either express, implied or statutory. This includes without\r
+// limitation any warranty or condition with respect to merchantability or\r
+// fitness for any particular purpose, or against the infringements of\r
+// intellectual property rights of others.\r
+// ----------------------------------------------------------------------------\r
+// File Name : AT91SAM7S64.h\r
+// Object : AT91SAM7S64 definitions\r
+// Generated : AT91 SW Application Group 07/16/2004 (07:43:09)\r
+// \r
+// CVS Reference : /AT91SAM7S64.pl/1.12/Mon Jul 12 13:02:30 2004//\r
+// CVS Reference : /SYSC_SAM7Sxx.pl/1.5/Mon Jul 12 16:22:12 2004//\r
+// CVS Reference : /MC_SAM02.pl/1.3/Wed Mar 10 08:37:04 2004//\r
+// CVS Reference : /UDP_1765B.pl/1.3/Fri Aug 2 14:45:38 2002//\r
+// CVS Reference : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:48 2002//\r
+// CVS Reference : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004//\r
+// CVS Reference : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:48 2002//\r
+// CVS Reference : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003//\r
+// CVS Reference : /US_1739C.pl/1.2/Mon Jul 12 17:26:24 2004//\r
+// CVS Reference : /SPI2.pl/1.2/Fri Oct 17 08:13:40 2003//\r
+// CVS Reference : /SSC_1762A.pl/1.2/Fri Nov 8 13:26:40 2002//\r
+// CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//\r
+// CVS Reference : /TWI_1761B.pl/1.4/Fri Feb 7 10:30:08 2003//\r
+// CVS Reference : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:24 2002//\r
+// CVS Reference : /ADC_SAM.pl/1.7/Fri Oct 17 08:12:38 2003//\r
+// CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//\r
+// ----------------------------------------------------------------------------\r
+\r
+// Hardware register definition\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR System Peripherals\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_SYSC structure ***\r
+#define SYSC_AIC_SMR ( 0) // Source Mode Register\r
+#define SYSC_AIC_SVR (128) // Source Vector Register\r
+#define SYSC_AIC_IVR (256) // IRQ Vector Register\r
+#define SYSC_AIC_FVR (260) // FIQ Vector Register\r
+#define SYSC_AIC_ISR (264) // Interrupt Status Register\r
+#define SYSC_AIC_IPR (268) // Interrupt Pending Register\r
+#define SYSC_AIC_IMR (272) // Interrupt Mask Register\r
+#define SYSC_AIC_CISR (276) // Core Interrupt Status Register\r
+#define SYSC_AIC_IECR (288) // Interrupt Enable Command Register\r
+#define SYSC_AIC_IDCR (292) // Interrupt Disable Command Register\r
+#define SYSC_AIC_ICCR (296) // Interrupt Clear Command Register\r
+#define SYSC_AIC_ISCR (300) // Interrupt Set Command Register\r
+#define SYSC_AIC_EOICR (304) // End of Interrupt Command Register\r
+#define SYSC_AIC_SPU (308) // Spurious Vector Register\r
+#define SYSC_AIC_DCR (312) // Debug Control Register (Protect)\r
+#define SYSC_AIC_FFER (320) // Fast Forcing Enable Register\r
+#define SYSC_AIC_FFDR (324) // Fast Forcing Disable Register\r
+#define SYSC_AIC_FFSR (328) // Fast Forcing Status Register\r
+#define SYSC_DBGU_CR (512) // Control Register\r
+#define SYSC_DBGU_MR (516) // Mode Register\r
+#define SYSC_DBGU_IER (520) // Interrupt Enable Register\r
+#define SYSC_DBGU_IDR (524) // Interrupt Disable Register\r
+#define SYSC_DBGU_IMR (528) // Interrupt Mask Register\r
+#define SYSC_DBGU_CSR (532) // Channel Status Register\r
+#define SYSC_DBGU_RHR (536) // Receiver Holding Register\r
+#define SYSC_DBGU_THR (540) // Transmitter Holding Register\r
+#define SYSC_DBGU_BRGR (544) // Baud Rate Generator Register\r
+#define SYSC_DBGU_C1R (576) // Chip ID1 Register\r
+#define SYSC_DBGU_C2R (580) // Chip ID2 Register\r
+#define SYSC_DBGU_FNTR (584) // Force NTRST Register\r
+#define SYSC_DBGU_RPR (768) // Receive Pointer Register\r
+#define SYSC_DBGU_RCR (772) // Receive Counter Register\r
+#define SYSC_DBGU_TPR (776) // Transmit Pointer Register\r
+#define SYSC_DBGU_TCR (780) // Transmit Counter Register\r
+#define SYSC_DBGU_RNPR (784) // Receive Next Pointer Register\r
+#define SYSC_DBGU_RNCR (788) // Receive Next Counter Register\r
+#define SYSC_DBGU_TNPR (792) // Transmit Next Pointer Register\r
+#define SYSC_DBGU_TNCR (796) // Transmit Next Counter Register\r
+#define SYSC_DBGU_PTCR (800) // PDC Transfer Control Register\r
+#define SYSC_DBGU_PTSR (804) // PDC Transfer Status Register\r
+#define SYSC_PIOA_PER (1024) // PIO Enable Register\r
+#define SYSC_PIOA_PDR (1028) // PIO Disable Register\r
+#define SYSC_PIOA_PSR (1032) // PIO Status Register\r
+#define SYSC_PIOA_OER (1040) // Output Enable Register\r
+#define SYSC_PIOA_ODR (1044) // Output Disable Registerr\r
+#define SYSC_PIOA_OSR (1048) // Output Status Register\r
+#define SYSC_PIOA_IFER (1056) // Input Filter Enable Register\r
+#define SYSC_PIOA_IFDR (1060) // Input Filter Disable Register\r
+#define SYSC_PIOA_IFSR (1064) // Input Filter Status Register\r
+#define SYSC_PIOA_SODR (1072) // Set Output Data Register\r
+#define SYSC_PIOA_CODR (1076) // Clear Output Data Register\r
+#define SYSC_PIOA_ODSR (1080) // Output Data Status Register\r
+#define SYSC_PIOA_PDSR (1084) // Pin Data Status Register\r
+#define SYSC_PIOA_IER (1088) // Interrupt Enable Register\r
+#define SYSC_PIOA_IDR (1092) // Interrupt Disable Register\r
+#define SYSC_PIOA_IMR (1096) // Interrupt Mask Register\r
+#define SYSC_PIOA_ISR (1100) // Interrupt Status Register\r
+#define SYSC_PIOA_MDER (1104) // Multi-driver Enable Register\r
+#define SYSC_PIOA_MDDR (1108) // Multi-driver Disable Register\r
+#define SYSC_PIOA_MDSR (1112) // Multi-driver Status Register\r
+#define SYSC_PIOA_PPUDR (1120) // Pull-up Disable Register\r
+#define SYSC_PIOA_PPUER (1124) // Pull-up Enable Register\r
+#define SYSC_PIOA_PPUSR (1128) // Pad Pull-up Status Register\r
+#define SYSC_PIOA_ASR (1136) // Select A Register\r
+#define SYSC_PIOA_BSR (1140) // Select B Register\r
+#define SYSC_PIOA_ABSR (1144) // AB Select Status Register\r
+#define SYSC_PIOA_OWER (1184) // Output Write Enable Register\r
+#define SYSC_PIOA_OWDR (1188) // Output Write Disable Register\r
+#define SYSC_PIOA_OWSR (1192) // Output Write Status Register\r
+#define SYSC_PMC_SCER (3072) // System Clock Enable Register\r
+#define SYSC_PMC_SCDR (3076) // System Clock Disable Register\r
+#define SYSC_PMC_SCSR (3080) // System Clock Status Register\r
+#define SYSC_PMC_PCER (3088) // Peripheral Clock Enable Register\r
+#define SYSC_PMC_PCDR (3092) // Peripheral Clock Disable Register\r
+#define SYSC_PMC_PCSR (3096) // Peripheral Clock Status Register\r
+#define SYSC_PMC_MOR (3104) // Main Oscillator Register\r
+#define SYSC_PMC_MCFR (3108) // Main Clock Frequency Register\r
+#define SYSC_PMC_PLLR (3116) // PLL Register\r
+#define SYSC_PMC_MCKR (3120) // Master Clock Register\r
+#define SYSC_PMC_PCKR (3136) // Programmable Clock Register\r
+#define SYSC_PMC_IER (3168) // Interrupt Enable Register\r
+#define SYSC_PMC_IDR (3172) // Interrupt Disable Register\r
+#define SYSC_PMC_SR (3176) // Status Register\r
+#define SYSC_PMC_IMR (3180) // Interrupt Mask Register\r
+#define SYSC_RSTC_RCR (3328) // Reset Control Register\r
+#define SYSC_RSTC_RSR (3332) // Reset Status Register\r
+#define SYSC_RSTC_RMR (3336) // Reset Mode Register\r
+#define SYSC_RTTC_RTMR (3360) // Real-time Mode Register\r
+#define SYSC_RTTC_RTAR (3364) // Real-time Alarm Register\r
+#define SYSC_RTTC_RTVR (3368) // Real-time Value Register\r
+#define SYSC_RTTC_RTSR (3372) // Real-time Status Register\r
+#define SYSC_PITC_PIMR (3376) // Period Interval Mode Register\r
+#define SYSC_PITC_PISR (3380) // Period Interval Status Register\r
+#define SYSC_PITC_PIVR (3384) // Period Interval Value Register\r
+#define SYSC_PITC_PIIR (3388) // Period Interval Image Register\r
+#define SYSC_WDTC_WDCR (3392) // Watchdog Control Register\r
+#define SYSC_WDTC_WDMR (3396) // Watchdog Mode Register\r
+#define SYSC_WDTC_WDSR (3400) // Watchdog Status Register\r
+#define SYSC_SYSC_VRPM (3424) // Voltage Regulator Power Mode Register\r
+// -------- VRPM : (SYSC Offset: 0xd60) Voltage Regulator Power Mode Register -------- \r
+#define AT91C_SYSC_PSTDBY (0x1 << 0) // (SYSC) Voltage Regulator Power Mode\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_AIC structure ***\r
+#define AIC_SMR ( 0) // Source Mode Register\r
+#define AIC_SVR (128) // Source Vector Register\r
+#define AIC_IVR (256) // IRQ Vector Register\r
+#define AIC_FVR (260) // FIQ Vector Register\r
+#define AIC_ISR (264) // Interrupt Status Register\r
+#define AIC_IPR (268) // Interrupt Pending Register\r
+#define AIC_IMR (272) // Interrupt Mask Register\r
+#define AIC_CISR (276) // Core Interrupt Status Register\r
+#define AIC_IECR (288) // Interrupt Enable Command Register\r
+#define AIC_IDCR (292) // Interrupt Disable Command Register\r
+#define AIC_ICCR (296) // Interrupt Clear Command Register\r
+#define AIC_ISCR (300) // Interrupt Set Command Register\r
+#define AIC_EOICR (304) // End of Interrupt Command Register\r
+#define AIC_SPU (308) // Spurious Vector Register\r
+#define AIC_DCR (312) // Debug Control Register (Protect)\r
+#define AIC_FFER (320) // Fast Forcing Enable Register\r
+#define AIC_FFDR (324) // Fast Forcing Disable Register\r
+#define AIC_FFSR (328) // Fast Forcing Status Register\r
+// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- \r
+#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level\r
+#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level\r
+#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level\r
+#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type\r
+#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE (0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive\r
+#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED (0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered\r
+#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL (0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive\r
+#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE (0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered\r
+// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- \r
+#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status\r
+#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status\r
+// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- \r
+#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode\r
+#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Debug Unit\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_DBGU structure ***\r
+#define DBGU_CR ( 0) // Control Register\r
+#define DBGU_MR ( 4) // Mode Register\r
+#define DBGU_IER ( 8) // Interrupt Enable Register\r
+#define DBGU_IDR (12) // Interrupt Disable Register\r
+#define DBGU_IMR (16) // Interrupt Mask Register\r
+#define DBGU_CSR (20) // Channel Status Register\r
+#define DBGU_RHR (24) // Receiver Holding Register\r
+#define DBGU_THR (28) // Transmitter Holding Register\r
+#define DBGU_BRGR (32) // Baud Rate Generator Register\r
+#define DBGU_C1R (64) // Chip ID1 Register\r
+#define DBGU_C2R (68) // Chip ID2 Register\r
+#define DBGU_FNTR (72) // Force NTRST Register\r
+#define DBGU_RPR (256) // Receive Pointer Register\r
+#define DBGU_RCR (260) // Receive Counter Register\r
+#define DBGU_TPR (264) // Transmit Pointer Register\r
+#define DBGU_TCR (268) // Transmit Counter Register\r
+#define DBGU_RNPR (272) // Receive Next Pointer Register\r
+#define DBGU_RNCR (276) // Receive Next Counter Register\r
+#define DBGU_TNPR (280) // Transmit Next Pointer Register\r
+#define DBGU_TNCR (284) // Transmit Next Counter Register\r
+#define DBGU_PTCR (288) // PDC Transfer Control Register\r
+#define DBGU_PTSR (292) // PDC Transfer Status Register\r
+// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- \r
+#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver\r
+#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter\r
+#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable\r
+#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable\r
+#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable\r
+#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable\r
+// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- \r
+#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type\r
+#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity\r
+#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity\r
+#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space)\r
+#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark)\r
+#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity\r
+#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode\r
+#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode\r
+#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.\r
+#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.\r
+#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.\r
+#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.\r
+// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- \r
+#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt\r
+#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt\r
+#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt\r
+#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt\r
+#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt\r
+#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt\r
+#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt\r
+#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt\r
+#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt\r
+#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt\r
+#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt\r
+#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt\r
+// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- \r
+// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- \r
+// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- \r
+// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- \r
+#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Peripheral Data Controller\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_PDC structure ***\r
+#define PDC_RPR ( 0) // Receive Pointer Register\r
+#define PDC_RCR ( 4) // Receive Counter Register\r
+#define PDC_TPR ( 8) // Transmit Pointer Register\r
+#define PDC_TCR (12) // Transmit Counter Register\r
+#define PDC_RNPR (16) // Receive Next Pointer Register\r
+#define PDC_RNCR (20) // Receive Next Counter Register\r
+#define PDC_TNPR (24) // Transmit Next Pointer Register\r
+#define PDC_TNCR (28) // Transmit Next Counter Register\r
+#define PDC_PTCR (32) // PDC Transfer Control Register\r
+#define PDC_PTSR (36) // PDC Transfer Status Register\r
+// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- \r
+#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable\r
+#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable\r
+#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable\r
+#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable\r
+// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Parallel Input Output Controler\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_PIO structure ***\r
+#define PIO_PER ( 0) // PIO Enable Register\r
+#define PIO_PDR ( 4) // PIO Disable Register\r
+#define PIO_PSR ( 8) // PIO Status Register\r
+#define PIO_OER (16) // Output Enable Register\r
+#define PIO_ODR (20) // Output Disable Registerr\r
+#define PIO_OSR (24) // Output Status Register\r
+#define PIO_IFER (32) // Input Filter Enable Register\r
+#define PIO_IFDR (36) // Input Filter Disable Register\r
+#define PIO_IFSR (40) // Input Filter Status Register\r
+#define PIO_SODR (48) // Set Output Data Register\r
+#define PIO_CODR (52) // Clear Output Data Register\r
+#define PIO_ODSR (56) // Output Data Status Register\r
+#define PIO_PDSR (60) // Pin Data Status Register\r
+#define PIO_IER (64) // Interrupt Enable Register\r
+#define PIO_IDR (68) // Interrupt Disable Register\r
+#define PIO_IMR (72) // Interrupt Mask Register\r
+#define PIO_ISR (76) // Interrupt Status Register\r
+#define PIO_MDER (80) // Multi-driver Enable Register\r
+#define PIO_MDDR (84) // Multi-driver Disable Register\r
+#define PIO_MDSR (88) // Multi-driver Status Register\r
+#define PIO_PPUDR (96) // Pull-up Disable Register\r
+#define PIO_PPUER (100) // Pull-up Enable Register\r
+#define PIO_PPUSR (104) // Pad Pull-up Status Register\r
+#define PIO_ASR (112) // Select A Register\r
+#define PIO_BSR (116) // Select B Register\r
+#define PIO_ABSR (120) // AB Select Status Register\r
+#define PIO_OWER (160) // Output Write Enable Register\r
+#define PIO_OWDR (164) // Output Write Disable Register\r
+#define PIO_OWSR (168) // Output Write Status Register\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Clock Generator Controler\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_CKGR structure ***\r
+#define CKGR_MOR ( 0) // Main Oscillator Register\r
+#define CKGR_MCFR ( 4) // Main Clock Frequency Register\r
+#define CKGR_PLLR (12) // PLL Register\r
+// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- \r
+#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable\r
+#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass\r
+#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time\r
+// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- \r
+#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency\r
+#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready\r
+// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- \r
+#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected\r
+#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0\r
+#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed\r
+#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter\r
+#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range\r
+#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet\r
+#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet\r
+#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet\r
+#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet\r
+#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier\r
+#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks\r
+#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output\r
+#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2\r
+#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Power Management Controler\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_PMC structure ***\r
+#define PMC_SCER ( 0) // System Clock Enable Register\r
+#define PMC_SCDR ( 4) // System Clock Disable Register\r
+#define PMC_SCSR ( 8) // System Clock Status Register\r
+#define PMC_PCER (16) // Peripheral Clock Enable Register\r
+#define PMC_PCDR (20) // Peripheral Clock Disable Register\r
+#define PMC_PCSR (24) // Peripheral Clock Status Register\r
+#define PMC_MOR (32) // Main Oscillator Register\r
+#define PMC_MCFR (36) // Main Clock Frequency Register\r
+#define PMC_PLLR (44) // PLL Register\r
+#define PMC_MCKR (48) // Master Clock Register\r
+#define PMC_PCKR (64) // Programmable Clock Register\r
+#define PMC_IER (96) // Interrupt Enable Register\r
+#define PMC_IDR (100) // Interrupt Disable Register\r
+#define PMC_SR (104) // Status Register\r
+#define PMC_IMR (108) // Interrupt Mask Register\r
+// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- \r
+#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock\r
+#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock\r
+#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output\r
+#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output\r
+#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output\r
+#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output\r
+// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- \r
+// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- \r
+// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- \r
+// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- \r
+// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- \r
+// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- \r
+#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection\r
+#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected\r
+#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected\r
+#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected\r
+#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler\r
+#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock\r
+#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2\r
+#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4\r
+#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8\r
+#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16\r
+#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32\r
+#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64\r
+// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- \r
+// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- \r
+#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask\r
+#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask\r
+#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask\r
+// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- \r
+// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- \r
+// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Reset Controller Interface\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_RSTC structure ***\r
+#define RSTC_RCR ( 0) // Reset Control Register\r
+#define RSTC_RSR ( 4) // Reset Status Register\r
+#define RSTC_RMR ( 8) // Reset Mode Register\r
+// -------- SYSC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- \r
+#define AT91C_SYSC_PROCRST (0x1 << 0) // (RSTC) Processor Reset\r
+#define AT91C_SYSC_ICERST (0x1 << 1) // (RSTC) ICE Interface Reset\r
+#define AT91C_SYSC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset\r
+#define AT91C_SYSC_EXTRST (0x1 << 3) // (RSTC) External Reset\r
+#define AT91C_SYSC_KEY (0xFF << 24) // (RSTC) Password\r
+// -------- SYSC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- \r
+#define AT91C_SYSC_URSTS (0x1 << 0) // (RSTC) User Reset Status\r
+#define AT91C_SYSC_BODSTS (0x1 << 1) // (RSTC) Brown-out Detection Status\r
+#define AT91C_SYSC_RSTTYP (0x7 << 8) // (RSTC) Reset Type\r
+#define AT91C_SYSC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising.\r
+#define AT91C_SYSC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.\r
+#define AT91C_SYSC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.\r
+#define AT91C_SYSC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low.\r
+#define AT91C_SYSC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brown-out Reset.\r
+#define AT91C_SYSC_NRSTL (0x1 << 16) // (RSTC) NRST pin level\r
+#define AT91C_SYSC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress.\r
+// -------- SYSC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- \r
+#define AT91C_SYSC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable\r
+#define AT91C_SYSC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable\r
+#define AT91C_SYSC_ERSTL (0xF << 8) // (RSTC) User Reset Enable\r
+#define AT91C_SYSC_BODIEN (0x1 << 16) // (RSTC) Brown-out Detection Interrupt Enable\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_RTTC structure ***\r
+#define RTTC_RTMR ( 0) // Real-time Mode Register\r
+#define RTTC_RTAR ( 4) // Real-time Alarm Register\r
+#define RTTC_RTVR ( 8) // Real-time Value Register\r
+#define RTTC_RTSR (12) // Real-time Status Register\r
+// -------- SYSC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- \r
+#define AT91C_SYSC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value\r
+#define AT91C_SYSC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable\r
+#define AT91C_SYSC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable\r
+#define AT91C_SYSC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart\r
+// -------- SYSC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- \r
+#define AT91C_SYSC_ALMV (0x0 << 0) // (RTTC) Alarm Value\r
+// -------- SYSC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- \r
+#define AT91C_SYSC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value\r
+// -------- SYSC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- \r
+#define AT91C_SYSC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status\r
+#define AT91C_SYSC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_PITC structure ***\r
+#define PITC_PIMR ( 0) // Period Interval Mode Register\r
+#define PITC_PISR ( 4) // Period Interval Status Register\r
+#define PITC_PIVR ( 8) // Period Interval Value Register\r
+#define PITC_PIIR (12) // Period Interval Image Register\r
+// -------- SYSC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- \r
+#define AT91C_SYSC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value\r
+#define AT91C_SYSC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled\r
+#define AT91C_SYSC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable\r
+// -------- SYSC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- \r
+#define AT91C_SYSC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status\r
+// -------- SYSC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- \r
+#define AT91C_SYSC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value\r
+#define AT91C_SYSC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter\r
+// -------- SYSC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_WDTC structure ***\r
+#define WDTC_WDCR ( 0) // Watchdog Control Register\r
+#define WDTC_WDMR ( 4) // Watchdog Mode Register\r
+#define WDTC_WDSR ( 8) // Watchdog Status Register\r
+// -------- SYSC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- \r
+#define AT91C_SYSC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart\r
+// -------- SYSC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- \r
+#define AT91C_SYSC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart\r
+#define AT91C_SYSC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable\r
+#define AT91C_SYSC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable\r
+#define AT91C_SYSC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart\r
+#define AT91C_SYSC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable\r
+#define AT91C_SYSC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value\r
+#define AT91C_SYSC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt\r
+#define AT91C_SYSC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt\r
+// -------- SYSC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- \r
+#define AT91C_SYSC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow\r
+#define AT91C_SYSC_WDERR (0x1 << 1) // (WDTC) Watchdog Error\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Memory Controller Interface\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_MC structure ***\r
+#define MC_RCR ( 0) // MC Remap Control Register\r
+#define MC_ASR ( 4) // MC Abort Status Register\r
+#define MC_AASR ( 8) // MC Abort Address Status Register\r
+#define MC_FMR (96) // MC Flash Mode Register\r
+#define MC_FCR (100) // MC Flash Command Register\r
+#define MC_FSR (104) // MC Flash Status Register\r
+// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- \r
+#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit\r
+// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- \r
+#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status\r
+#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status\r
+#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status\r
+#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte\r
+#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word\r
+#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word\r
+#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status\r
+#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read\r
+#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write\r
+#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch\r
+#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source\r
+#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source\r
+#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source\r
+#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source\r
+// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- \r
+#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready\r
+#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error\r
+#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error\r
+#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming\r
+#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State\r
+#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations\r
+#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations\r
+#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations\r
+#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations\r
+#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number\r
+// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- \r
+#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command\r
+#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN.\r
+#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.\r
+#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.\r
+#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.\r
+#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.\r
+#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits.\r
+#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits.\r
+#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit.\r
+#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number\r
+#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key\r
+// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- \r
+#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status\r
+#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status\r
+#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status\r
+#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status\r
+#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status\r
+#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status\r
+#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status\r
+#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status\r
+#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status\r
+#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status\r
+#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status\r
+#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status\r
+#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status\r
+#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status\r
+#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status\r
+#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status\r
+#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status\r
+#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status\r
+#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status\r
+#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status\r
+#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status\r
+#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status\r
+#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status\r
+#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status\r
+#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Serial Parallel Interface\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_SPI structure ***\r
+#define SPI_CR ( 0) // Control Register\r
+#define SPI_MR ( 4) // Mode Register\r
+#define SPI_RDR ( 8) // Receive Data Register\r
+#define SPI_TDR (12) // Transmit Data Register\r
+#define SPI_SR (16) // Status Register\r
+#define SPI_IER (20) // Interrupt Enable Register\r
+#define SPI_IDR (24) // Interrupt Disable Register\r
+#define SPI_IMR (28) // Interrupt Mask Register\r
+#define SPI_CSR (48) // Chip Select Register\r
+#define SPI_RPR (256) // Receive Pointer Register\r
+#define SPI_RCR (260) // Receive Counter Register\r
+#define SPI_TPR (264) // Transmit Pointer Register\r
+#define SPI_TCR (268) // Transmit Counter Register\r
+#define SPI_RNPR (272) // Receive Next Pointer Register\r
+#define SPI_RNCR (276) // Receive Next Counter Register\r
+#define SPI_TNPR (280) // Transmit Next Pointer Register\r
+#define SPI_TNCR (284) // Transmit Next Counter Register\r
+#define SPI_PTCR (288) // PDC Transfer Control Register\r
+#define SPI_PTSR (292) // PDC Transfer Status Register\r
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- \r
+#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable\r
+#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable\r
+#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset\r
+#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer\r
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- \r
+#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode\r
+#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select\r
+#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select\r
+#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select\r
+#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode\r
+#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection\r
+#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection\r
+#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection\r
+#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select\r
+#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects\r
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- \r
+#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data\r
+#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status\r
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- \r
+#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data\r
+#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status\r
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- \r
+#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full\r
+#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty\r
+#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error\r
+#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status\r
+#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer\r
+#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer\r
+#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt\r
+#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt\r
+#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt\r
+#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt\r
+#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status\r
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- \r
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- \r
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- \r
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- \r
+#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity\r
+#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase\r
+#define AT91C_SPI_CSAAT (0x1 << 2) // (SPI) Chip Select Active After Transfer\r
+#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer\r
+#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer\r
+#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer\r
+#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer\r
+#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer\r
+#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer\r
+#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer\r
+#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer\r
+#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer\r
+#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer\r
+#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate\r
+#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Serial Clock Baud Rate\r
+#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Analog to Digital Convertor\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_ADC structure ***\r
+#define ADC_CR ( 0) // ADC Control Register\r
+#define ADC_MR ( 4) // ADC Mode Register\r
+#define ADC_CHER (16) // ADC Channel Enable Register\r
+#define ADC_CHDR (20) // ADC Channel Disable Register\r
+#define ADC_CHSR (24) // ADC Channel Status Register\r
+#define ADC_SR (28) // ADC Status Register\r
+#define ADC_LCDR (32) // ADC Last Converted Data Register\r
+#define ADC_IER (36) // ADC Interrupt Enable Register\r
+#define ADC_IDR (40) // ADC Interrupt Disable Register\r
+#define ADC_IMR (44) // ADC Interrupt Mask Register\r
+#define ADC_CDR0 (48) // ADC Channel Data Register 0\r
+#define ADC_CDR1 (52) // ADC Channel Data Register 1\r
+#define ADC_CDR2 (56) // ADC Channel Data Register 2\r
+#define ADC_CDR3 (60) // ADC Channel Data Register 3\r
+#define ADC_CDR4 (64) // ADC Channel Data Register 4\r
+#define ADC_CDR5 (68) // ADC Channel Data Register 5\r
+#define ADC_CDR6 (72) // ADC Channel Data Register 6\r
+#define ADC_CDR7 (76) // ADC Channel Data Register 7\r
+#define ADC_RPR (256) // Receive Pointer Register\r
+#define ADC_RCR (260) // Receive Counter Register\r
+#define ADC_TPR (264) // Transmit Pointer Register\r
+#define ADC_TCR (268) // Transmit Counter Register\r
+#define ADC_RNPR (272) // Receive Next Pointer Register\r
+#define ADC_RNCR (276) // Receive Next Counter Register\r
+#define ADC_TNPR (280) // Transmit Next Pointer Register\r
+#define ADC_TNCR (284) // Transmit Next Counter Register\r
+#define ADC_PTCR (288) // PDC Transfer Control Register\r
+#define ADC_PTSR (292) // PDC Transfer Status Register\r
+// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- \r
+#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset\r
+#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion\r
+// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- \r
+#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable\r
+#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software\r
+#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.\r
+#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection\r
+#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0\r
+#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1\r
+#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2\r
+#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3\r
+#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4\r
+#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5\r
+#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger\r
+#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution.\r
+#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution\r
+#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution\r
+#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode\r
+#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode\r
+#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode\r
+#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection\r
+#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time\r
+#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time\r
+// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- \r
+#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0\r
+#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1\r
+#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2\r
+#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3\r
+#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4\r
+#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5\r
+#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6\r
+#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7\r
+// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- \r
+// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- \r
+// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- \r
+#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion\r
+#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error\r
+#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready\r
+#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun\r
+#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer\r
+#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt\r
+// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- \r
+#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted\r
+// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- \r
+// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- \r
+// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- \r
+// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- \r
+#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data\r
+// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- \r
+// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- \r
+// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- \r
+// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- \r
+// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- \r
+// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- \r
+// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_SSC structure ***\r
+#define SSC_CR ( 0) // Control Register\r
+#define SSC_CMR ( 4) // Clock Mode Register\r
+#define SSC_RCMR (16) // Receive Clock ModeRegister\r
+#define SSC_RFMR (20) // Receive Frame Mode Register\r
+#define SSC_TCMR (24) // Transmit Clock Mode Register\r
+#define SSC_TFMR (28) // Transmit Frame Mode Register\r
+#define SSC_RHR (32) // Receive Holding Register\r
+#define SSC_THR (36) // Transmit Holding Register\r
+#define SSC_RSHR (48) // Receive Sync Holding Register\r
+#define SSC_TSHR (52) // Transmit Sync Holding Register\r
+#define SSC_RC0R (56) // Receive Compare 0 Register\r
+#define SSC_RC1R (60) // Receive Compare 1 Register\r
+#define SSC_SR (64) // Status Register\r
+#define SSC_IER (68) // Interrupt Enable Register\r
+#define SSC_IDR (72) // Interrupt Disable Register\r
+#define SSC_IMR (76) // Interrupt Mask Register\r
+#define SSC_RPR (256) // Receive Pointer Register\r
+#define SSC_RCR (260) // Receive Counter Register\r
+#define SSC_TPR (264) // Transmit Pointer Register\r
+#define SSC_TCR (268) // Transmit Counter Register\r
+#define SSC_RNPR (272) // Receive Next Pointer Register\r
+#define SSC_RNCR (276) // Receive Next Counter Register\r
+#define SSC_TNPR (280) // Transmit Next Pointer Register\r
+#define SSC_TNCR (284) // Transmit Next Counter Register\r
+#define SSC_PTCR (288) // PDC Transfer Control Register\r
+#define SSC_PTSR (292) // PDC Transfer Status Register\r
+// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- \r
+#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable\r
+#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable\r
+#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable\r
+#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable\r
+#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset\r
+// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- \r
+#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection\r
+#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock\r
+#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal\r
+#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin\r
+#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection\r
+#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only\r
+#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output\r
+#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output\r
+#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion\r
+#define AT91C_SSC_CKG (0x3 << 6) // (SSC) Receive/Transmit Clock Gating Selection\r
+#define AT91C_SSC_CKG_NONE (0x0 << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock\r
+#define AT91C_SSC_CKG_LOW (0x1 << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low\r
+#define AT91C_SSC_CKG_HIGH (0x2 << 6) // (SSC) Receive/Transmit Clock enabled only if RF High\r
+#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection\r
+#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.\r
+#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start\r
+#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input\r
+#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input\r
+#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input\r
+#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input\r
+#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input\r
+#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input\r
+#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0\r
+#define AT91C_SSC_STOP (0x1 << 12) // (SSC) Receive Stop Selection\r
+#define AT91C_SSC_STTOUT (0x1 << 15) // (SSC) Receive/Transmit Start Output Selection\r
+#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay\r
+#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection\r
+// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- \r
+#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length\r
+#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode\r
+#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First\r
+#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame\r
+#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length\r
+#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection\r
+#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only\r
+#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse\r
+#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse\r
+#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer\r
+#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer\r
+#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer\r
+#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection\r
+// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- \r
+// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- \r
+#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value\r
+#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable\r
+// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- \r
+#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready\r
+#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty\r
+#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission\r
+#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty\r
+#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready\r
+#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun\r
+#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception\r
+#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full\r
+#define AT91C_SSC_CP0 (0x1 << 8) // (SSC) Compare 0\r
+#define AT91C_SSC_CP1 (0x1 << 9) // (SSC) Compare 1\r
+#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync\r
+#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync\r
+#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable\r
+#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable\r
+// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- \r
+// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- \r
+// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Usart\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_USART structure ***\r
+#define US_CR ( 0) // Control Register\r
+#define US_MR ( 4) // Mode Register\r
+#define US_IER ( 8) // Interrupt Enable Register\r
+#define US_IDR (12) // Interrupt Disable Register\r
+#define US_IMR (16) // Interrupt Mask Register\r
+#define US_CSR (20) // Channel Status Register\r
+#define US_RHR (24) // Receiver Holding Register\r
+#define US_THR (28) // Transmitter Holding Register\r
+#define US_BRGR (32) // Baud Rate Generator Register\r
+#define US_RTOR (36) // Receiver Time-out Register\r
+#define US_TTGR (40) // Transmitter Time-guard Register\r
+#define US_FIDI (64) // FI_DI_Ratio Register\r
+#define US_NER (68) // Nb Errors Register\r
+#define US_XXR (72) // XON_XOFF Register\r
+#define US_IF (76) // IRDA_FILTER Register\r
+#define US_RPR (256) // Receive Pointer Register\r
+#define US_RCR (260) // Receive Counter Register\r
+#define US_TPR (264) // Transmit Pointer Register\r
+#define US_TCR (268) // Transmit Counter Register\r
+#define US_RNPR (272) // Receive Next Pointer Register\r
+#define US_RNCR (276) // Receive Next Counter Register\r
+#define US_TNPR (280) // Transmit Next Pointer Register\r
+#define US_TNCR (284) // Transmit Next Counter Register\r
+#define US_PTCR (288) // PDC Transfer Control Register\r
+#define US_PTSR (292) // PDC Transfer Status Register\r
+// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- \r
+#define AT91C_US_RSTSTA (0x1 << 8) // (USART) Reset Status Bits\r
+#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break\r
+#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break\r
+#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out\r
+#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address\r
+#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations\r
+#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge\r
+#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out\r
+#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable\r
+#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable\r
+#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable\r
+#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable\r
+// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- \r
+#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode\r
+#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal\r
+#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485\r
+#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking\r
+#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem\r
+#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0\r
+#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1\r
+#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA\r
+#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking\r
+#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock\r
+#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock\r
+#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1\r
+#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM)\r
+#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK)\r
+#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock\r
+#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits\r
+#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits\r
+#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits\r
+#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits\r
+#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select\r
+#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits\r
+#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit\r
+#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits\r
+#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits\r
+#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order\r
+#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length\r
+#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select\r
+#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode\r
+#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge\r
+#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK\r
+#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions\r
+#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter\r
+// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- \r
+#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break\r
+#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out\r
+#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached\r
+#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge\r
+#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag\r
+#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag\r
+#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag\r
+#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag\r
+// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- \r
+// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- \r
+// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- \r
+#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input\r
+#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input\r
+#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input\r
+#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Two-wire Interface\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_TWI structure ***\r
+#define TWI_CR ( 0) // Control Register\r
+#define TWI_MMR ( 4) // Master Mode Register\r
+#define TWI_SMR ( 8) // Slave Mode Register\r
+#define TWI_IADR (12) // Internal Address Register\r
+#define TWI_CWGR (16) // Clock Waveform Generator Register\r
+#define TWI_SR (32) // Status Register\r
+#define TWI_IER (36) // Interrupt Enable Register\r
+#define TWI_IDR (40) // Interrupt Disable Register\r
+#define TWI_IMR (44) // Interrupt Mask Register\r
+#define TWI_RHR (48) // Receive Holding Register\r
+#define TWI_THR (52) // Transmit Holding Register\r
+// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- \r
+#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition\r
+#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition\r
+#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled\r
+#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled\r
+#define AT91C_TWI_SVEN (0x1 << 4) // (TWI) TWI Slave Transfer Enabled\r
+#define AT91C_TWI_SVDIS (0x1 << 5) // (TWI) TWI Slave Transfer Disabled\r
+#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset\r
+// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- \r
+#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size\r
+#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address\r
+#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address\r
+#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address\r
+#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address\r
+#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction\r
+#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address\r
+// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- \r
+#define AT91C_TWI_SADR (0x7F << 16) // (TWI) Slave Device Address\r
+// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- \r
+#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider\r
+#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider\r
+#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider\r
+// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- \r
+#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed\r
+#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY\r
+#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY\r
+#define AT91C_TWI_SVREAD (0x1 << 3) // (TWI) Slave Read\r
+#define AT91C_TWI_SVACC (0x1 << 4) // (TWI) Slave Access\r
+#define AT91C_TWI_GCACC (0x1 << 5) // (TWI) General Call Access\r
+#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error\r
+#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error\r
+#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged\r
+#define AT91C_TWI_ARBLST (0x1 << 9) // (TWI) Arbitration Lost\r
+// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- \r
+// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- \r
+// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_TC structure ***\r
+#define TC_CCR ( 0) // Channel Control Register\r
+#define TC_CMR ( 4) // Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define TC_CV (16) // Counter Value\r
+#define TC_RA (20) // Register A\r
+#define TC_RB (24) // Register B\r
+#define TC_RC (28) // Register C\r
+#define TC_SR (32) // Status Register\r
+#define TC_IER (36) // Interrupt Enable Register\r
+#define TC_IDR (40) // Interrupt Disable Register\r
+#define TC_IMR (44) // Interrupt Mask Register\r
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- \r
+#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command\r
+#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command\r
+#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command\r
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- \r
+#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection\r
+#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK\r
+#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK\r
+#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK\r
+#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK\r
+#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK\r
+#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0\r
+#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1\r
+#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2\r
+#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert\r
+#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection\r
+#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal\r
+#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock\r
+#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock\r
+#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock\r
+#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare\r
+#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading\r
+#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading\r
+#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare\r
+#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection\r
+#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None\r
+#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge\r
+#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge\r
+#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge\r
+#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection\r
+#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None\r
+#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge\r
+#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge\r
+#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge\r
+#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection\r
+#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection\r
+#define AT91C_TC_EEVT_NONE (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input\r
+#define AT91C_TC_EEVT_RISING (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output\r
+#define AT91C_TC_EEVT_FALLING (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output\r
+#define AT91C_TC_EEVT_BOTH (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output\r
+#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable\r
+#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection\r
+#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare\r
+#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare\r
+#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare\r
+#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare\r
+#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable\r
+#define AT91C_TC_WAVE (0x1 << 15) // (TC) \r
+#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection\r
+#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None\r
+#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA\r
+#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA\r
+#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA\r
+#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA\r
+#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none\r
+#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set\r
+#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear\r
+#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle\r
+#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection\r
+#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None\r
+#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA\r
+#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA\r
+#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA\r
+#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA\r
+#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none\r
+#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set\r
+#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear\r
+#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle\r
+#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA\r
+#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none\r
+#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set\r
+#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear\r
+#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle\r
+#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA\r
+#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none\r
+#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set\r
+#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear\r
+#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle\r
+#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB\r
+#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none\r
+#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set\r
+#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear\r
+#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle\r
+#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB\r
+#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none\r
+#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set\r
+#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear\r
+#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle\r
+#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB\r
+#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none\r
+#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set\r
+#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear\r
+#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle\r
+#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB\r
+#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none\r
+#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set\r
+#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear\r
+#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle\r
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- \r
+#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow\r
+#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun\r
+#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare\r
+#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare\r
+#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare\r
+#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading\r
+#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading\r
+#define AT91C_TC_ETRCS (0x1 << 7) // (TC) External Trigger\r
+#define AT91C_TC_ETRGS (0x1 << 16) // (TC) Clock Enabling\r
+#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror\r
+#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror\r
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- \r
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- \r
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Timer Counter Interface\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_TCB structure ***\r
+#define TCB_TC0 ( 0) // TC Channel 0\r
+#define TCB_TC1 (64) // TC Channel 1\r
+#define TCB_TC2 (128) // TC Channel 2\r
+#define TCB_BCR (192) // TC Block Control Register\r
+#define TCB_BMR (196) // TC Block Mode Register\r
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- \r
+#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command\r
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- \r
+#define AT91C_TCB_TC0XC0S (0x1 << 0) // (TCB) External Clock Signal 0 Selection\r
+#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0\r
+#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0\r
+#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0\r
+#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0\r
+#define AT91C_TCB_TC1XC1S (0x1 << 2) // (TCB) External Clock Signal 1 Selection\r
+#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1\r
+#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1\r
+#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1\r
+#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1\r
+#define AT91C_TCB_TC2XC2S (0x1 << 4) // (TCB) External Clock Signal 2 Selection\r
+#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2\r
+#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2\r
+#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2\r
+#define AT91C_TCB_TC2XC2S_TIOA2 (0x3 << 4) // (TCB) TIOA2 connected to XC2\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR PWMC Channel Interface\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_PWMC_CH structure ***\r
+#define PWMC_CMR ( 0) // Channel Mode Register\r
+#define PWMC_CDTYR ( 4) // Channel Duty Cycle Register\r
+#define PWMC_CPRDR ( 8) // Channel Period Register\r
+#define PWMC_CCNTR (12) // Channel Counter Register\r
+#define PWMC_CUPDR (16) // Channel Update Register\r
+#define PWMC_Reserved (20) // Reserved\r
+// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- \r
+#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx\r
+#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH) \r
+#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH) \r
+#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH) \r
+#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment\r
+#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity\r
+#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period\r
+// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- \r
+#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle\r
+// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- \r
+#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period\r
+// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- \r
+#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter\r
+// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- \r
+#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_PWMC structure ***\r
+#define PWMC_MR ( 0) // PWMC Mode Register\r
+#define PWMC_ENA ( 4) // PWMC Enable Register\r
+#define PWMC_DIS ( 8) // PWMC Disable Register\r
+#define PWMC_SR (12) // PWMC Status Register\r
+#define PWMC_IER (16) // PWMC Interrupt Enable Register\r
+#define PWMC_IDR (20) // PWMC Interrupt Disable Register\r
+#define PWMC_IMR (24) // PWMC Interrupt Mask Register\r
+#define PWMC_ISR (28) // PWMC Interrupt Status Register\r
+#define PWMC_VR (252) // PWMC Version Register\r
+#define PWMC_CH (512) // PWMC Channel 0\r
+// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- \r
+#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor.\r
+#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A\r
+#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC) \r
+#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor.\r
+#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B\r
+#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC) \r
+// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- \r
+#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0\r
+#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1\r
+#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2\r
+#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3\r
+#define AT91C_PWMC_CHID4 (0x1 << 4) // (PWMC) Channel ID 4\r
+#define AT91C_PWMC_CHID5 (0x1 << 5) // (PWMC) Channel ID 5\r
+#define AT91C_PWMC_CHID6 (0x1 << 6) // (PWMC) Channel ID 6\r
+#define AT91C_PWMC_CHID7 (0x1 << 7) // (PWMC) Channel ID 7\r
+// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- \r
+// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- \r
+// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- \r
+// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- \r
+// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- \r
+// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR USB Device Interface\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_UDP structure ***\r
+#define UDP_NUM ( 0) // Frame Number Register\r
+#define UDP_GLBSTATE ( 4) // Global State Register\r
+#define UDP_FADDR ( 8) // Function Address Register\r
+#define UDP_IER (16) // Interrupt Enable Register\r
+#define UDP_IDR (20) // Interrupt Disable Register\r
+#define UDP_IMR (24) // Interrupt Mask Register\r
+#define UDP_ISR (28) // Interrupt Status Register\r
+#define UDP_ICR (32) // Interrupt Clear Register\r
+#define UDP_RSTEP (40) // Reset Endpoint Register\r
+#define UDP_CSR (48) // Endpoint Control and Status Register\r
+#define UDP_FDR (80) // Endpoint FIFO Data Register\r
+// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- \r
+#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats\r
+#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error\r
+#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK\r
+// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- \r
+#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable\r
+#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured\r
+#define AT91C_UDP_RMWUPE (0x1 << 2) // (UDP) Remote Wake Up Enable\r
+#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host\r
+// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- \r
+#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value\r
+#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable\r
+// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- \r
+#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt\r
+#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt\r
+#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt\r
+#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt\r
+#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt\r
+#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt\r
+#define AT91C_UDP_EPINT6 (0x1 << 6) // (UDP) Endpoint 6 Interrupt\r
+#define AT91C_UDP_EPINT7 (0x1 << 7) // (UDP) Endpoint 7 Interrupt\r
+#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt\r
+#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt\r
+#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt\r
+#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt\r
+#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt\r
+// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- \r
+// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- \r
+// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- \r
+#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt\r
+// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- \r
+// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- \r
+#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0\r
+#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1\r
+#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2\r
+#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3\r
+#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4\r
+#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5\r
+#define AT91C_UDP_EP6 (0x1 << 6) // (UDP) Reset Endpoint 6\r
+#define AT91C_UDP_EP7 (0x1 << 7) // (UDP) Reset Endpoint 7\r
+// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- \r
+#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR\r
+#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0\r
+#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)\r
+#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)\r
+#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready\r
+#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).\r
+#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).\r
+#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction\r
+#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type\r
+#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control\r
+#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT\r
+#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT\r
+#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT\r
+#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN\r
+#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN\r
+#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN\r
+#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle\r
+#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable\r
+#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO\r
+\r
+// *****************************************************************************\r
+// REGISTER ADDRESS DEFINITION FOR AT91SAM7S64\r
+// *****************************************************************************\r
+// ========== Register definition for SYSC peripheral ========== \r
+#define AT91C_SYSC_SYSC_VRPM (0xFFFFFD60) // (SYSC) Voltage Regulator Power Mode Register\r
+// ========== Register definition for AIC peripheral ========== \r
+#define AT91C_AIC_ICCR (0xFFFFF128) // (AIC) Interrupt Clear Command Register\r
+#define AT91C_AIC_IECR (0xFFFFF120) // (AIC) Interrupt Enable Command Register\r
+#define AT91C_AIC_SMR (0xFFFFF000) // (AIC) Source Mode Register\r
+#define AT91C_AIC_ISCR (0xFFFFF12C) // (AIC) Interrupt Set Command Register\r
+#define AT91C_AIC_EOICR (0xFFFFF130) // (AIC) End of Interrupt Command Register\r
+#define AT91C_AIC_DCR (0xFFFFF138) // (AIC) Debug Control Register (Protect)\r
+#define AT91C_AIC_FFER (0xFFFFF140) // (AIC) Fast Forcing Enable Register\r
+#define AT91C_AIC_SVR (0xFFFFF080) // (AIC) Source Vector Register\r
+#define AT91C_AIC_SPU (0xFFFFF134) // (AIC) Spurious Vector Register\r
+#define AT91C_AIC_FFDR (0xFFFFF144) // (AIC) Fast Forcing Disable Register\r
+#define AT91C_AIC_FVR (0xFFFFF104) // (AIC) FIQ Vector Register\r
+#define AT91C_AIC_FFSR (0xFFFFF148) // (AIC) Fast Forcing Status Register\r
+#define AT91C_AIC_IMR (0xFFFFF110) // (AIC) Interrupt Mask Register\r
+#define AT91C_AIC_ISR (0xFFFFF108) // (AIC) Interrupt Status Register\r
+#define AT91C_AIC_IVR (0xFFFFF100) // (AIC) IRQ Vector Register\r
+#define AT91C_AIC_IDCR (0xFFFFF124) // (AIC) Interrupt Disable Command Register\r
+#define AT91C_AIC_CISR (0xFFFFF114) // (AIC) Core Interrupt Status Register\r
+#define AT91C_AIC_IPR (0xFFFFF10C) // (AIC) Interrupt Pending Register\r
+// ========== Register definition for DBGU peripheral ========== \r
+#define AT91C_DBGU_C2R (0xFFFFF244) // (DBGU) Chip ID2 Register\r
+#define AT91C_DBGU_THR (0xFFFFF21C) // (DBGU) Transmitter Holding Register\r
+#define AT91C_DBGU_CSR (0xFFFFF214) // (DBGU) Channel Status Register\r
+#define AT91C_DBGU_IDR (0xFFFFF20C) // (DBGU) Interrupt Disable Register\r
+#define AT91C_DBGU_MR (0xFFFFF204) // (DBGU) Mode Register\r
+#define AT91C_DBGU_FNTR (0xFFFFF248) // (DBGU) Force NTRST Register\r
+#define AT91C_DBGU_C1R (0xFFFFF240) // (DBGU) Chip ID1 Register\r
+#define AT91C_DBGU_BRGR (0xFFFFF220) // (DBGU) Baud Rate Generator Register\r
+#define AT91C_DBGU_RHR (0xFFFFF218) // (DBGU) Receiver Holding Register\r
+#define AT91C_DBGU_IMR (0xFFFFF210) // (DBGU) Interrupt Mask Register\r
+#define AT91C_DBGU_IER (0xFFFFF208) // (DBGU) Interrupt Enable Register\r
+#define AT91C_DBGU_CR (0xFFFFF200) // (DBGU) Control Register\r
+// ========== Register definition for PDC_DBGU peripheral ========== \r
+#define AT91C_DBGU_TNCR (0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register\r
+#define AT91C_DBGU_RNCR (0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register\r
+#define AT91C_DBGU_PTCR (0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register\r
+#define AT91C_DBGU_PTSR (0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register\r
+#define AT91C_DBGU_RCR (0xFFFFF304) // (PDC_DBGU) Receive Counter Register\r
+#define AT91C_DBGU_TCR (0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register\r
+#define AT91C_DBGU_RPR (0xFFFFF300) // (PDC_DBGU) Receive Pointer Register\r
+#define AT91C_DBGU_TPR (0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register\r
+#define AT91C_DBGU_RNPR (0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register\r
+#define AT91C_DBGU_TNPR (0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register\r
+// ========== Register definition for PIOA peripheral ========== \r
+#define AT91C_PIOA_IMR (0xFFFFF448) // (PIOA) Interrupt Mask Register\r
+#define AT91C_PIOA_IER (0xFFFFF440) // (PIOA) Interrupt Enable Register\r
+#define AT91C_PIOA_OWDR (0xFFFFF4A4) // (PIOA) Output Write Disable Register\r
+#define AT91C_PIOA_ISR (0xFFFFF44C) // (PIOA) Interrupt Status Register\r
+#define AT91C_PIOA_PPUDR (0xFFFFF460) // (PIOA) Pull-up Disable Register\r
+#define AT91C_PIOA_MDSR (0xFFFFF458) // (PIOA) Multi-driver Status Register\r
+#define AT91C_PIOA_MDER (0xFFFFF450) // (PIOA) Multi-driver Enable Register\r
+#define AT91C_PIOA_PER (0xFFFFF400) // (PIOA) PIO Enable Register\r
+#define AT91C_PIOA_PSR (0xFFFFF408) // (PIOA) PIO Status Register\r
+#define AT91C_PIOA_OER (0xFFFFF410) // (PIOA) Output Enable Register\r
+#define AT91C_PIOA_BSR (0xFFFFF474) // (PIOA) Select B Register\r
+#define AT91C_PIOA_PPUER (0xFFFFF464) // (PIOA) Pull-up Enable Register\r
+#define AT91C_PIOA_MDDR (0xFFFFF454) // (PIOA) Multi-driver Disable Register\r
+#define AT91C_PIOA_PDR (0xFFFFF404) // (PIOA) PIO Disable Register\r
+#define AT91C_PIOA_ODR (0xFFFFF414) // (PIOA) Output Disable Registerr\r
+#define AT91C_PIOA_IFDR (0xFFFFF424) // (PIOA) Input Filter Disable Register\r
+#define AT91C_PIOA_ABSR (0xFFFFF478) // (PIOA) AB Select Status Register\r
+#define AT91C_PIOA_ASR (0xFFFFF470) // (PIOA) Select A Register\r
+#define AT91C_PIOA_PPUSR (0xFFFFF468) // (PIOA) Pad Pull-up Status Register\r
+#define AT91C_PIOA_ODSR (0xFFFFF438) // (PIOA) Output Data Status Register\r
+#define AT91C_PIOA_SODR (0xFFFFF430) // (PIOA) Set Output Data Register\r
+#define AT91C_PIOA_IFSR (0xFFFFF428) // (PIOA) Input Filter Status Register\r
+#define AT91C_PIOA_IFER (0xFFFFF420) // (PIOA) Input Filter Enable Register\r
+#define AT91C_PIOA_OSR (0xFFFFF418) // (PIOA) Output Status Register\r
+#define AT91C_PIOA_IDR (0xFFFFF444) // (PIOA) Interrupt Disable Register\r
+#define AT91C_PIOA_PDSR (0xFFFFF43C) // (PIOA) Pin Data Status Register\r
+#define AT91C_PIOA_CODR (0xFFFFF434) // (PIOA) Clear Output Data Register\r
+#define AT91C_PIOA_OWSR (0xFFFFF4A8) // (PIOA) Output Write Status Register\r
+#define AT91C_PIOA_OWER (0xFFFFF4A0) // (PIOA) Output Write Enable Register\r
+// ========== Register definition for CKGR peripheral ========== \r
+#define AT91C_CKGR_PLLR (0xFFFFFC2C) // (CKGR) PLL Register\r
+#define AT91C_CKGR_MCFR (0xFFFFFC24) // (CKGR) Main Clock Frequency Register\r
+#define AT91C_CKGR_MOR (0xFFFFFC20) // (CKGR) Main Oscillator Register\r
+// ========== Register definition for PMC peripheral ========== \r
+#define AT91C_PMC_SCSR (0xFFFFFC08) // (PMC) System Clock Status Register\r
+#define AT91C_PMC_SCER (0xFFFFFC00) // (PMC) System Clock Enable Register\r
+#define AT91C_PMC_IMR (0xFFFFFC6C) // (PMC) Interrupt Mask Register\r
+#define AT91C_PMC_IDR (0xFFFFFC64) // (PMC) Interrupt Disable Register\r
+#define AT91C_PMC_PCDR (0xFFFFFC14) // (PMC) Peripheral Clock Disable Register\r
+#define AT91C_PMC_SCDR (0xFFFFFC04) // (PMC) System Clock Disable Register\r
+#define AT91C_PMC_SR (0xFFFFFC68) // (PMC) Status Register\r
+#define AT91C_PMC_IER (0xFFFFFC60) // (PMC) Interrupt Enable Register\r
+#define AT91C_PMC_MCKR (0xFFFFFC30) // (PMC) Master Clock Register\r
+#define AT91C_PMC_MOR (0xFFFFFC20) // (PMC) Main Oscillator Register\r
+#define AT91C_PMC_PCER (0xFFFFFC10) // (PMC) Peripheral Clock Enable Register\r
+#define AT91C_PMC_PCSR (0xFFFFFC18) // (PMC) Peripheral Clock Status Register\r
+#define AT91C_PMC_PLLR (0xFFFFFC2C) // (PMC) PLL Register\r
+#define AT91C_PMC_MCFR (0xFFFFFC24) // (PMC) Main Clock Frequency Register\r
+#define AT91C_PMC_PCKR (0xFFFFFC40) // (PMC) Programmable Clock Register\r
+// ========== Register definition for RSTC peripheral ========== \r
+#define AT91C_RSTC_RSR (0xFFFFFD04) // (RSTC) Reset Status Register\r
+#define AT91C_RSTC_RMR (0xFFFFFD08) // (RSTC) Reset Mode Register\r
+#define AT91C_RSTC_RCR (0xFFFFFD00) // (RSTC) Reset Control Register\r
+// ========== Register definition for RTTC peripheral ========== \r
+#define AT91C_RTTC_RTSR (0xFFFFFD2C) // (RTTC) Real-time Status Register\r
+#define AT91C_RTTC_RTAR (0xFFFFFD24) // (RTTC) Real-time Alarm Register\r
+#define AT91C_RTTC_RTVR (0xFFFFFD28) // (RTTC) Real-time Value Register\r
+#define AT91C_RTTC_RTMR (0xFFFFFD20) // (RTTC) Real-time Mode Register\r
+// ========== Register definition for PITC peripheral ========== \r
+#define AT91C_PITC_PIIR (0xFFFFFD3C) // (PITC) Period Interval Image Register\r
+#define AT91C_PITC_PISR (0xFFFFFD34) // (PITC) Period Interval Status Register\r
+#define AT91C_PITC_PIVR (0xFFFFFD38) // (PITC) Period Interval Value Register\r
+#define AT91C_PITC_PIMR (0xFFFFFD30) // (PITC) Period Interval Mode Register\r
+// ========== Register definition for WDTC peripheral ========== \r
+#define AT91C_WDTC_WDMR (0xFFFFFD44) // (WDTC) Watchdog Mode Register\r
+#define AT91C_WDTC_WDSR (0xFFFFFD48) // (WDTC) Watchdog Status Register\r
+#define AT91C_WDTC_WDCR (0xFFFFFD40) // (WDTC) Watchdog Control Register\r
+// ========== Register definition for MC peripheral ========== \r
+#define AT91C_MC_FCR (0xFFFFFF64) // (MC) MC Flash Command Register\r
+#define AT91C_MC_ASR (0xFFFFFF04) // (MC) MC Abort Status Register\r
+#define AT91C_MC_FSR (0xFFFFFF68) // (MC) MC Flash Status Register\r
+#define AT91C_MC_FMR (0xFFFFFF60) // (MC) MC Flash Mode Register\r
+#define AT91C_MC_AASR (0xFFFFFF08) // (MC) MC Abort Address Status Register\r
+#define AT91C_MC_RCR (0xFFFFFF00) // (MC) MC Remap Control Register\r
+// ========== Register definition for PDC_SPI peripheral ========== \r
+#define AT91C_SPI_PTCR (0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register\r
+#define AT91C_SPI_TNPR (0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register\r
+#define AT91C_SPI_RNPR (0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register\r
+#define AT91C_SPI_TPR (0xFFFE0108) // (PDC_SPI) Transmit Pointer Register\r
+#define AT91C_SPI_RPR (0xFFFE0100) // (PDC_SPI) Receive Pointer Register\r
+#define AT91C_SPI_PTSR (0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register\r
+#define AT91C_SPI_TNCR (0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register\r
+#define AT91C_SPI_RNCR (0xFFFE0114) // (PDC_SPI) Receive Next Counter Register\r
+#define AT91C_SPI_TCR (0xFFFE010C) // (PDC_SPI) Transmit Counter Register\r
+#define AT91C_SPI_RCR (0xFFFE0104) // (PDC_SPI) Receive Counter Register\r
+// ========== Register definition for SPI peripheral ========== \r
+#define AT91C_SPI_CSR (0xFFFE0030) // (SPI) Chip Select Register\r
+#define AT91C_SPI_IDR (0xFFFE0018) // (SPI) Interrupt Disable Register\r
+#define AT91C_SPI_SR (0xFFFE0010) // (SPI) Status Register\r
+#define AT91C_SPI_RDR (0xFFFE0008) // (SPI) Receive Data Register\r
+#define AT91C_SPI_CR (0xFFFE0000) // (SPI) Control Register\r
+#define AT91C_SPI_IMR (0xFFFE001C) // (SPI) Interrupt Mask Register\r
+#define AT91C_SPI_IER (0xFFFE0014) // (SPI) Interrupt Enable Register\r
+#define AT91C_SPI_TDR (0xFFFE000C) // (SPI) Transmit Data Register\r
+#define AT91C_SPI_MR (0xFFFE0004) // (SPI) Mode Register\r
+// ========== Register definition for PDC_ADC peripheral ========== \r
+#define AT91C_ADC_PTCR (0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register\r
+#define AT91C_ADC_TNPR (0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register\r
+#define AT91C_ADC_RNPR (0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register\r
+#define AT91C_ADC_TPR (0xFFFD8108) // (PDC_ADC) Transmit Pointer Register\r
+#define AT91C_ADC_RPR (0xFFFD8100) // (PDC_ADC) Receive Pointer Register\r
+#define AT91C_ADC_PTSR (0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register\r
+#define AT91C_ADC_TNCR (0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register\r
+#define AT91C_ADC_RNCR (0xFFFD8114) // (PDC_ADC) Receive Next Counter Register\r
+#define AT91C_ADC_TCR (0xFFFD810C) // (PDC_ADC) Transmit Counter Register\r
+#define AT91C_ADC_RCR (0xFFFD8104) // (PDC_ADC) Receive Counter Register\r
+// ========== Register definition for ADC peripheral ========== \r
+#define AT91C_ADC_IMR (0xFFFD802C) // (ADC) ADC Interrupt Mask Register\r
+#define AT91C_ADC_CDR4 (0xFFFD8040) // (ADC) ADC Channel Data Register 4\r
+#define AT91C_ADC_CDR2 (0xFFFD8038) // (ADC) ADC Channel Data Register 2\r
+#define AT91C_ADC_CDR0 (0xFFFD8030) // (ADC) ADC Channel Data Register 0\r
+#define AT91C_ADC_CDR7 (0xFFFD804C) // (ADC) ADC Channel Data Register 7\r
+#define AT91C_ADC_CDR1 (0xFFFD8034) // (ADC) ADC Channel Data Register 1\r
+#define AT91C_ADC_CDR3 (0xFFFD803C) // (ADC) ADC Channel Data Register 3\r
+#define AT91C_ADC_CDR5 (0xFFFD8044) // (ADC) ADC Channel Data Register 5\r
+#define AT91C_ADC_MR (0xFFFD8004) // (ADC) ADC Mode Register\r
+#define AT91C_ADC_CDR6 (0xFFFD8048) // (ADC) ADC Channel Data Register 6\r
+#define AT91C_ADC_CR (0xFFFD8000) // (ADC) ADC Control Register\r
+#define AT91C_ADC_CHER (0xFFFD8010) // (ADC) ADC Channel Enable Register\r
+#define AT91C_ADC_CHSR (0xFFFD8018) // (ADC) ADC Channel Status Register\r
+#define AT91C_ADC_IER (0xFFFD8024) // (ADC) ADC Interrupt Enable Register\r
+#define AT91C_ADC_SR (0xFFFD801C) // (ADC) ADC Status Register\r
+#define AT91C_ADC_CHDR (0xFFFD8014) // (ADC) ADC Channel Disable Register\r
+#define AT91C_ADC_IDR (0xFFFD8028) // (ADC) ADC Interrupt Disable Register\r
+#define AT91C_ADC_LCDR (0xFFFD8020) // (ADC) ADC Last Converted Data Register\r
+// ========== Register definition for PDC_SSC peripheral ========== \r
+#define AT91C_SSC_PTCR (0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register\r
+#define AT91C_SSC_TNPR (0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register\r
+#define AT91C_SSC_RNPR (0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register\r
+#define AT91C_SSC_TPR (0xFFFD4108) // (PDC_SSC) Transmit Pointer Register\r
+#define AT91C_SSC_RPR (0xFFFD4100) // (PDC_SSC) Receive Pointer Register\r
+#define AT91C_SSC_PTSR (0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register\r
+#define AT91C_SSC_TNCR (0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register\r
+#define AT91C_SSC_RNCR (0xFFFD4114) // (PDC_SSC) Receive Next Counter Register\r
+#define AT91C_SSC_TCR (0xFFFD410C) // (PDC_SSC) Transmit Counter Register\r
+#define AT91C_SSC_RCR (0xFFFD4104) // (PDC_SSC) Receive Counter Register\r
+// ========== Register definition for SSC peripheral ========== \r
+#define AT91C_SSC_RFMR (0xFFFD4014) // (SSC) Receive Frame Mode Register\r
+#define AT91C_SSC_CMR (0xFFFD4004) // (SSC) Clock Mode Register\r
+#define AT91C_SSC_IDR (0xFFFD4048) // (SSC) Interrupt Disable Register\r
+#define AT91C_SSC_SR (0xFFFD4040) // (SSC) Status Register\r
+#define AT91C_SSC_RC0R (0xFFFD4038) // (SSC) Receive Compare 0 Register\r
+#define AT91C_SSC_RSHR (0xFFFD4030) // (SSC) Receive Sync Holding Register\r
+#define AT91C_SSC_RHR (0xFFFD4020) // (SSC) Receive Holding Register\r
+#define AT91C_SSC_TCMR (0xFFFD4018) // (SSC) Transmit Clock Mode Register\r
+#define AT91C_SSC_RCMR (0xFFFD4010) // (SSC) Receive Clock ModeRegister\r
+#define AT91C_SSC_CR (0xFFFD4000) // (SSC) Control Register\r
+#define AT91C_SSC_IMR (0xFFFD404C) // (SSC) Interrupt Mask Register\r
+#define AT91C_SSC_IER (0xFFFD4044) // (SSC) Interrupt Enable Register\r
+#define AT91C_SSC_RC1R (0xFFFD403C) // (SSC) Receive Compare 1 Register\r
+#define AT91C_SSC_TSHR (0xFFFD4034) // (SSC) Transmit Sync Holding Register\r
+#define AT91C_SSC_THR (0xFFFD4024) // (SSC) Transmit Holding Register\r
+#define AT91C_SSC_TFMR (0xFFFD401C) // (SSC) Transmit Frame Mode Register\r
+// ========== Register definition for PDC_US1 peripheral ========== \r
+#define AT91C_US1_PTSR (0xFFFC4124) // (PDC_US1) PDC Transfer Status Register\r
+#define AT91C_US1_TNCR (0xFFFC411C) // (PDC_US1) Transmit Next Counter Register\r
+#define AT91C_US1_RNCR (0xFFFC4114) // (PDC_US1) Receive Next Counter Register\r
+#define AT91C_US1_TCR (0xFFFC410C) // (PDC_US1) Transmit Counter Register\r
+#define AT91C_US1_RCR (0xFFFC4104) // (PDC_US1) Receive Counter Register\r
+#define AT91C_US1_PTCR (0xFFFC4120) // (PDC_US1) PDC Transfer Control Register\r
+#define AT91C_US1_TNPR (0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register\r
+#define AT91C_US1_RNPR (0xFFFC4110) // (PDC_US1) Receive Next Pointer Register\r
+#define AT91C_US1_TPR (0xFFFC4108) // (PDC_US1) Transmit Pointer Register\r
+#define AT91C_US1_RPR (0xFFFC4100) // (PDC_US1) Receive Pointer Register\r
+// ========== Register definition for US1 peripheral ========== \r
+#define AT91C_US1_XXR (0xFFFC4048) // (US1) XON_XOFF Register\r
+#define AT91C_US1_RHR (0xFFFC4018) // (US1) Receiver Holding Register\r
+#define AT91C_US1_IMR (0xFFFC4010) // (US1) Interrupt Mask Register\r
+#define AT91C_US1_IER (0xFFFC4008) // (US1) Interrupt Enable Register\r
+#define AT91C_US1_CR (0xFFFC4000) // (US1) Control Register\r
+#define AT91C_US1_RTOR (0xFFFC4024) // (US1) Receiver Time-out Register\r
+#define AT91C_US1_THR (0xFFFC401C) // (US1) Transmitter Holding Register\r
+#define AT91C_US1_CSR (0xFFFC4014) // (US1) Channel Status Register\r
+#define AT91C_US1_IDR (0xFFFC400C) // (US1) Interrupt Disable Register\r
+#define AT91C_US1_FIDI (0xFFFC4040) // (US1) FI_DI_Ratio Register\r
+#define AT91C_US1_BRGR (0xFFFC4020) // (US1) Baud Rate Generator Register\r
+#define AT91C_US1_TTGR (0xFFFC4028) // (US1) Transmitter Time-guard Register\r
+#define AT91C_US1_IF (0xFFFC404C) // (US1) IRDA_FILTER Register\r
+#define AT91C_US1_NER (0xFFFC4044) // (US1) Nb Errors Register\r
+#define AT91C_US1_MR (0xFFFC4004) // (US1) Mode Register\r
+// ========== Register definition for PDC_US0 peripheral ========== \r
+#define AT91C_US0_PTCR (0xFFFC0120) // (PDC_US0) PDC Transfer Control Register\r
+#define AT91C_US0_TNPR (0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register\r
+#define AT91C_US0_RNPR (0xFFFC0110) // (PDC_US0) Receive Next Pointer Register\r
+#define AT91C_US0_TPR (0xFFFC0108) // (PDC_US0) Transmit Pointer Register\r
+#define AT91C_US0_RPR (0xFFFC0100) // (PDC_US0) Receive Pointer Register\r
+#define AT91C_US0_PTSR (0xFFFC0124) // (PDC_US0) PDC Transfer Status Register\r
+#define AT91C_US0_TNCR (0xFFFC011C) // (PDC_US0) Transmit Next Counter Register\r
+#define AT91C_US0_RNCR (0xFFFC0114) // (PDC_US0) Receive Next Counter Register\r
+#define AT91C_US0_TCR (0xFFFC010C) // (PDC_US0) Transmit Counter Register\r
+#define AT91C_US0_RCR (0xFFFC0104) // (PDC_US0) Receive Counter Register\r
+// ========== Register definition for US0 peripheral ========== \r
+#define AT91C_US0_TTGR (0xFFFC0028) // (US0) Transmitter Time-guard Register\r
+#define AT91C_US0_BRGR (0xFFFC0020) // (US0) Baud Rate Generator Register\r
+#define AT91C_US0_RHR (0xFFFC0018) // (US0) Receiver Holding Register\r
+#define AT91C_US0_IMR (0xFFFC0010) // (US0) Interrupt Mask Register\r
+#define AT91C_US0_NER (0xFFFC0044) // (US0) Nb Errors Register\r
+#define AT91C_US0_RTOR (0xFFFC0024) // (US0) Receiver Time-out Register\r
+#define AT91C_US0_XXR (0xFFFC0048) // (US0) XON_XOFF Register\r
+#define AT91C_US0_FIDI (0xFFFC0040) // (US0) FI_DI_Ratio Register\r
+#define AT91C_US0_CR (0xFFFC0000) // (US0) Control Register\r
+#define AT91C_US0_IER (0xFFFC0008) // (US0) Interrupt Enable Register\r
+#define AT91C_US0_IF (0xFFFC004C) // (US0) IRDA_FILTER Register\r
+#define AT91C_US0_MR (0xFFFC0004) // (US0) Mode Register\r
+#define AT91C_US0_IDR (0xFFFC000C) // (US0) Interrupt Disable Register\r
+#define AT91C_US0_CSR (0xFFFC0014) // (US0) Channel Status Register\r
+#define AT91C_US0_THR (0xFFFC001C) // (US0) Transmitter Holding Register\r
+// ========== Register definition for TWI peripheral ========== \r
+#define AT91C_TWI_RHR (0xFFFB8030) // (TWI) Receive Holding Register\r
+#define AT91C_TWI_IDR (0xFFFB8028) // (TWI) Interrupt Disable Register\r
+#define AT91C_TWI_SR (0xFFFB8020) // (TWI) Status Register\r
+#define AT91C_TWI_CWGR (0xFFFB8010) // (TWI) Clock Waveform Generator Register\r
+#define AT91C_TWI_SMR (0xFFFB8008) // (TWI) Slave Mode Register\r
+#define AT91C_TWI_CR (0xFFFB8000) // (TWI) Control Register\r
+#define AT91C_TWI_THR (0xFFFB8034) // (TWI) Transmit Holding Register\r
+#define AT91C_TWI_IMR (0xFFFB802C) // (TWI) Interrupt Mask Register\r
+#define AT91C_TWI_IER (0xFFFB8024) // (TWI) Interrupt Enable Register\r
+#define AT91C_TWI_IADR (0xFFFB800C) // (TWI) Internal Address Register\r
+#define AT91C_TWI_MMR (0xFFFB8004) // (TWI) Master Mode Register\r
+// ========== Register definition for TC2 peripheral ========== \r
+#define AT91C_TC2_IMR (0xFFFA00AC) // (TC2) Interrupt Mask Register\r
+#define AT91C_TC2_IER (0xFFFA00A4) // (TC2) Interrupt Enable Register\r
+#define AT91C_TC2_RC (0xFFFA009C) // (TC2) Register C\r
+#define AT91C_TC2_RA (0xFFFA0094) // (TC2) Register A\r
+#define AT91C_TC2_CMR (0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define AT91C_TC2_IDR (0xFFFA00A8) // (TC2) Interrupt Disable Register\r
+#define AT91C_TC2_SR (0xFFFA00A0) // (TC2) Status Register\r
+#define AT91C_TC2_RB (0xFFFA0098) // (TC2) Register B\r
+#define AT91C_TC2_CV (0xFFFA0090) // (TC2) Counter Value\r
+#define AT91C_TC2_CCR (0xFFFA0080) // (TC2) Channel Control Register\r
+// ========== Register definition for TC1 peripheral ========== \r
+#define AT91C_TC1_IMR (0xFFFA006C) // (TC1) Interrupt Mask Register\r
+#define AT91C_TC1_IER (0xFFFA0064) // (TC1) Interrupt Enable Register\r
+#define AT91C_TC1_RC (0xFFFA005C) // (TC1) Register C\r
+#define AT91C_TC1_RA (0xFFFA0054) // (TC1) Register A\r
+#define AT91C_TC1_CMR (0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define AT91C_TC1_IDR (0xFFFA0068) // (TC1) Interrupt Disable Register\r
+#define AT91C_TC1_SR (0xFFFA0060) // (TC1) Status Register\r
+#define AT91C_TC1_RB (0xFFFA0058) // (TC1) Register B\r
+#define AT91C_TC1_CV (0xFFFA0050) // (TC1) Counter Value\r
+#define AT91C_TC1_CCR (0xFFFA0040) // (TC1) Channel Control Register\r
+// ========== Register definition for TC0 peripheral ========== \r
+#define AT91C_TC0_IMR (0xFFFA002C) // (TC0) Interrupt Mask Register\r
+#define AT91C_TC0_IER (0xFFFA0024) // (TC0) Interrupt Enable Register\r
+#define AT91C_TC0_RC (0xFFFA001C) // (TC0) Register C\r
+#define AT91C_TC0_RA (0xFFFA0014) // (TC0) Register A\r
+#define AT91C_TC0_CMR (0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define AT91C_TC0_IDR (0xFFFA0028) // (TC0) Interrupt Disable Register\r
+#define AT91C_TC0_SR (0xFFFA0020) // (TC0) Status Register\r
+#define AT91C_TC0_RB (0xFFFA0018) // (TC0) Register B\r
+#define AT91C_TC0_CV (0xFFFA0010) // (TC0) Counter Value\r
+#define AT91C_TC0_CCR (0xFFFA0000) // (TC0) Channel Control Register\r
+// ========== Register definition for TCB peripheral ========== \r
+#define AT91C_TCB_BMR (0xFFFA00C4) // (TCB) TC Block Mode Register\r
+#define AT91C_TCB_BCR (0xFFFA00C0) // (TCB) TC Block Control Register\r
+// ========== Register definition for PWMC_CH3 peripheral ========== \r
+#define AT91C_CH3_CUPDR (0xFFFCC270) // (PWMC_CH3) Channel Update Register\r
+#define AT91C_CH3_CPRDR (0xFFFCC268) // (PWMC_CH3) Channel Period Register\r
+#define AT91C_CH3_CMR (0xFFFCC260) // (PWMC_CH3) Channel Mode Register\r
+#define AT91C_CH3_Reserved (0xFFFCC274) // (PWMC_CH3) Reserved\r
+#define AT91C_CH3_CCNTR (0xFFFCC26C) // (PWMC_CH3) Channel Counter Register\r
+#define AT91C_CH3_CDTYR (0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register\r
+// ========== Register definition for PWMC_CH2 peripheral ========== \r
+#define AT91C_CH2_CUPDR (0xFFFCC250) // (PWMC_CH2) Channel Update Register\r
+#define AT91C_CH2_CPRDR (0xFFFCC248) // (PWMC_CH2) Channel Period Register\r
+#define AT91C_CH2_CMR (0xFFFCC240) // (PWMC_CH2) Channel Mode Register\r
+#define AT91C_CH2_Reserved (0xFFFCC254) // (PWMC_CH2) Reserved\r
+#define AT91C_CH2_CCNTR (0xFFFCC24C) // (PWMC_CH2) Channel Counter Register\r
+#define AT91C_CH2_CDTYR (0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register\r
+// ========== Register definition for PWMC_CH1 peripheral ========== \r
+#define AT91C_CH1_CUPDR (0xFFFCC230) // (PWMC_CH1) Channel Update Register\r
+#define AT91C_CH1_CPRDR (0xFFFCC228) // (PWMC_CH1) Channel Period Register\r
+#define AT91C_CH1_CMR (0xFFFCC220) // (PWMC_CH1) Channel Mode Register\r
+#define AT91C_CH1_Reserved (0xFFFCC234) // (PWMC_CH1) Reserved\r
+#define AT91C_CH1_CCNTR (0xFFFCC22C) // (PWMC_CH1) Channel Counter Register\r
+#define AT91C_CH1_CDTYR (0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register\r
+// ========== Register definition for PWMC_CH0 peripheral ========== \r
+#define AT91C_CH0_CUPDR (0xFFFCC210) // (PWMC_CH0) Channel Update Register\r
+#define AT91C_CH0_CPRDR (0xFFFCC208) // (PWMC_CH0) Channel Period Register\r
+#define AT91C_CH0_CMR (0xFFFCC200) // (PWMC_CH0) Channel Mode Register\r
+#define AT91C_CH0_Reserved (0xFFFCC214) // (PWMC_CH0) Reserved\r
+#define AT91C_CH0_CCNTR (0xFFFCC20C) // (PWMC_CH0) Channel Counter Register\r
+#define AT91C_CH0_CDTYR (0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register\r
+// ========== Register definition for PWMC peripheral ========== \r
+#define AT91C_PWMC_VR (0xFFFCC0FC) // (PWMC) PWMC Version Register\r
+#define AT91C_PWMC_ISR (0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register\r
+#define AT91C_PWMC_IDR (0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register\r
+#define AT91C_PWMC_SR (0xFFFCC00C) // (PWMC) PWMC Status Register\r
+#define AT91C_PWMC_ENA (0xFFFCC004) // (PWMC) PWMC Enable Register\r
+#define AT91C_PWMC_IMR (0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register\r
+#define AT91C_PWMC_MR (0xFFFCC000) // (PWMC) PWMC Mode Register\r
+#define AT91C_PWMC_DIS (0xFFFCC008) // (PWMC) PWMC Disable Register\r
+#define AT91C_PWMC_IER (0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register\r
+// ========== Register definition for UDP peripheral ========== \r
+#define AT91C_UDP_ISR (0xFFFB001C) // (UDP) Interrupt Status Register\r
+#define AT91C_UDP_IDR (0xFFFB0014) // (UDP) Interrupt Disable Register\r
+#define AT91C_UDP_GLBSTATE (0xFFFB0004) // (UDP) Global State Register\r
+#define AT91C_UDP_FDR (0xFFFB0050) // (UDP) Endpoint FIFO Data Register\r
+#define AT91C_UDP_CSR (0xFFFB0030) // (UDP) Endpoint Control and Status Register\r
+#define AT91C_UDP_RSTEP (0xFFFB0028) // (UDP) Reset Endpoint Register\r
+#define AT91C_UDP_ICR (0xFFFB0020) // (UDP) Interrupt Clear Register\r
+#define AT91C_UDP_IMR (0xFFFB0018) // (UDP) Interrupt Mask Register\r
+#define AT91C_UDP_IER (0xFFFB0010) // (UDP) Interrupt Enable Register\r
+#define AT91C_UDP_FADDR (0xFFFB0008) // (UDP) Function Address Register\r
+#define AT91C_UDP_NUM (0xFFFB0000) // (UDP) Frame Number Register\r
+\r
+// *****************************************************************************\r
+// PIO DEFINITIONS FOR AT91SAM7S64\r
+// *****************************************************************************\r
+#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0\r
+#define AT91C_PA0_PWM0 (AT91C_PIO_PA0) // PWM Channel 0\r
+#define AT91C_PA0_TIOA0 (AT91C_PIO_PA0) // Timer Counter 0 Multipurpose Timer I/O Pin A\r
+#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1\r
+#define AT91C_PA1_PWM1 (AT91C_PIO_PA1) // PWM Channel 1\r
+#define AT91C_PA1_TIOB0 (AT91C_PIO_PA1) // Timer Counter 0 Multipurpose Timer I/O Pin B\r
+#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10\r
+#define AT91C_PA10_DTXD (AT91C_PIO_PA10) // DBGU Debug Transmit Data\r
+#define AT91C_PA10_NPCS2 (AT91C_PIO_PA10) // SPI Peripheral Chip Select 2\r
+#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11\r
+#define AT91C_PA11_NPCS0 (AT91C_PIO_PA11) // SPI Peripheral Chip Select 0\r
+#define AT91C_PA11_PWM0 (AT91C_PIO_PA11) // PWM Channel 0\r
+#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12\r
+#define AT91C_PA12_MISO (AT91C_PIO_PA12) // SPI Master In Slave\r
+#define AT91C_PA12_PWM1 (AT91C_PIO_PA12) // PWM Channel 1\r
+#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13\r
+#define AT91C_PA13_MOSI (AT91C_PIO_PA13) // SPI Master Out Slave\r
+#define AT91C_PA13_PWM2 (AT91C_PIO_PA13) // PWM Channel 2\r
+#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14\r
+#define AT91C_PA14_SPCK (AT91C_PIO_PA14) // SPI Serial Clock\r
+#define AT91C_PA14_PWM3 (AT91C_PIO_PA14) // PWM Channel 3\r
+#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15\r
+#define AT91C_PA15_TF (AT91C_PIO_PA15) // SSC Transmit Frame Sync\r
+#define AT91C_PA15_TIOA1 (AT91C_PIO_PA15) // Timer Counter 1 Multipurpose Timer I/O Pin A\r
+#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16\r
+#define AT91C_PA16_TK (AT91C_PIO_PA16) // SSC Transmit Clock\r
+#define AT91C_PA16_TIOB1 (AT91C_PIO_PA16) // Timer Counter 1 Multipurpose Timer I/O Pin B\r
+#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17\r
+#define AT91C_PA17_TD (AT91C_PIO_PA17) // SSC Transmit data\r
+#define AT91C_PA17_PCK1 (AT91C_PIO_PA17) // PMC Programmable Clock Output 1\r
+#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18\r
+#define AT91C_PA18_RD (AT91C_PIO_PA18) // SSC Receive Data\r
+#define AT91C_PA18_PCK2 (AT91C_PIO_PA18) // PMC Programmable Clock Output 2\r
+#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19\r
+#define AT91C_PA19_RK (AT91C_PIO_PA19) // SSC Receive Clock\r
+#define AT91C_PA19_FIQ (AT91C_PIO_PA19) // AIC Fast Interrupt Input\r
+#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2\r
+#define AT91C_PA2_PWM2 (AT91C_PIO_PA2) // PWM Channel 2\r
+#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock\r
+#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20\r
+#define AT91C_PA20_RF (AT91C_PIO_PA20) // SSC Receive Frame Sync\r
+#define AT91C_PA20_IRQ0 (AT91C_PIO_PA20) // External Interrupt 0\r
+#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21\r
+#define AT91C_PA21_RXD1 (AT91C_PIO_PA21) // USART 1 Receive Data\r
+#define AT91C_PA21_PCK1 (AT91C_PIO_PA21) // PMC Programmable Clock Output 1\r
+#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22\r
+#define AT91C_PA22_TXD1 (AT91C_PIO_PA22) // USART 1 Transmit Data\r
+#define AT91C_PA22_NPCS3 (AT91C_PIO_PA22) // SPI Peripheral Chip Select 3\r
+#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23\r
+#define AT91C_PA23_SCK1 (AT91C_PIO_PA23) // USART 1 Serial Clock\r
+#define AT91C_PA23_PWM0 (AT91C_PIO_PA23) // PWM Channel 0\r
+#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24\r
+#define AT91C_PA24_RTS1 (AT91C_PIO_PA24) // USART 1 Ready To Send\r
+#define AT91C_PA24_PWM1 (AT91C_PIO_PA24) // PWM Channel 1\r
+#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25\r
+#define AT91C_PA25_CTS1 (AT91C_PIO_PA25) // USART 1 Clear To Send\r
+#define AT91C_PA25_PWM2 (AT91C_PIO_PA25) // PWM Channel 2\r
+#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26\r
+#define AT91C_PA26_DCD1 (AT91C_PIO_PA26) // USART 1 Data Carrier Detect\r
+#define AT91C_PA26_TIOA2 (AT91C_PIO_PA26) // Timer Counter 2 Multipurpose Timer I/O Pin A\r
+#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27\r
+#define AT91C_PA27_DTR1 (AT91C_PIO_PA27) // USART 1 Data Terminal ready\r
+#define AT91C_PA27_TIOB2 (AT91C_PIO_PA27) // Timer Counter 2 Multipurpose Timer I/O Pin B\r
+#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28\r
+#define AT91C_PA28_DSR1 (AT91C_PIO_PA28) // USART 1 Data Set ready\r
+#define AT91C_PA28_TCLK1 (AT91C_PIO_PA28) // Timer Counter 1 external clock input\r
+#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29\r
+#define AT91C_PA29_RI1 (AT91C_PIO_PA29) // USART 1 Ring Indicator\r
+#define AT91C_PA29_TCLK2 (AT91C_PIO_PA29) // Timer Counter 2 external clock input\r
+#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3\r
+#define AT91C_PA3_TWD (AT91C_PIO_PA3) // TWI Two-wire Serial Data\r
+#define AT91C_PA3_NPCS3 (AT91C_PIO_PA3) // SPI Peripheral Chip Select 3\r
+#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30\r
+#define AT91C_PA30_IRQ1 (AT91C_PIO_PA30) // External Interrupt 1\r
+#define AT91C_PA30_NPCS2 (AT91C_PIO_PA30) // SPI Peripheral Chip Select 2\r
+#define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31\r
+#define AT91C_PA31_NPCS1 (AT91C_PIO_PA31) // SPI Peripheral Chip Select 1\r
+#define AT91C_PA31_PCK2 (AT91C_PIO_PA31) // PMC Programmable Clock Output 2\r
+#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4\r
+#define AT91C_PA4_TWCK (AT91C_PIO_PA4) // TWI Two-wire Serial Clock\r
+#define AT91C_PA4_TCLK0 (AT91C_PIO_PA4) // Timer Counter 0 external clock input\r
+#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5\r
+#define AT91C_PA5_RXD0 (AT91C_PIO_PA5) // USART 0 Receive Data\r
+#define AT91C_PA5_NPCS3 (AT91C_PIO_PA5) // SPI Peripheral Chip Select 3\r
+#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6\r
+#define AT91C_PA6_TXD0 (AT91C_PIO_PA6) // USART 0 Transmit Data\r
+#define AT91C_PA6_PCK0 (AT91C_PIO_PA6) // PMC Programmable Clock Output 0\r
+#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7\r
+#define AT91C_PA7_RTS0 (AT91C_PIO_PA7) // USART 0 Ready To Send\r
+#define AT91C_PA7_PWM3 (AT91C_PIO_PA7) // PWM Channel 3\r
+#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8\r
+#define AT91C_PA8_CTS0 (AT91C_PIO_PA8) // USART 0 Clear To Send\r
+#define AT91C_PA8_ADTRG (AT91C_PIO_PA8) // ADC External Trigger\r
+#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9\r
+#define AT91C_PA9_DRXD (AT91C_PIO_PA9) // DBGU Debug Receive Data\r
+#define AT91C_PA9_NPCS1 (AT91C_PIO_PA9) // SPI Peripheral Chip Select 1\r
+\r
+// *****************************************************************************\r
+// PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64\r
+// *****************************************************************************\r
+#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ)\r
+#define AT91C_ID_SYS ( 1) // System Peripheral\r
+#define AT91C_ID_PIOA ( 2) // Parallel IO Controller\r
+#define AT91C_ID_3_Reserved ( 3) // Reserved\r
+#define AT91C_ID_ADC ( 4) // Analog-to-Digital Converter\r
+#define AT91C_ID_SPI ( 5) // Serial Peripheral Interface\r
+#define AT91C_ID_US0 ( 6) // USART 0\r
+#define AT91C_ID_US1 ( 7) // USART 1\r
+#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller\r
+#define AT91C_ID_TWI ( 9) // Two-Wire Interface\r
+#define AT91C_ID_PWMC (10) // PWM Controller\r
+#define AT91C_ID_UDP (11) // USB Device Port\r
+#define AT91C_ID_TC0 (12) // Timer Counter 0\r
+#define AT91C_ID_TC1 (13) // Timer Counter 1\r
+#define AT91C_ID_TC2 (14) // Timer Counter 2\r
+#define AT91C_ID_15_Reserved (15) // Reserved\r
+#define AT91C_ID_16_Reserved (16) // Reserved\r
+#define AT91C_ID_17_Reserved (17) // Reserved\r
+#define AT91C_ID_18_Reserved (18) // Reserved\r
+#define AT91C_ID_19_Reserved (19) // Reserved\r
+#define AT91C_ID_20_Reserved (20) // Reserved\r
+#define AT91C_ID_21_Reserved (21) // Reserved\r
+#define AT91C_ID_22_Reserved (22) // Reserved\r
+#define AT91C_ID_23_Reserved (23) // Reserved\r
+#define AT91C_ID_24_Reserved (24) // Reserved\r
+#define AT91C_ID_25_Reserved (25) // Reserved\r
+#define AT91C_ID_26_Reserved (26) // Reserved\r
+#define AT91C_ID_27_Reserved (27) // Reserved\r
+#define AT91C_ID_28_Reserved (28) // Reserved\r
+#define AT91C_ID_29_Reserved (29) // Reserved\r
+#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0)\r
+#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1)\r
+\r
+// *****************************************************************************\r
+// BASE ADDRESS DEFINITIONS FOR AT91SAM7S64\r
+// *****************************************************************************\r
+#define AT91C_BASE_SYSC (0xFFFFF000) // (SYSC) Base Address\r
+#define AT91C_BASE_AIC (0xFFFFF000) // (AIC) Base Address\r
+#define AT91C_BASE_DBGU (0xFFFFF200) // (DBGU) Base Address\r
+#define AT91C_BASE_PDC_DBGU (0xFFFFF300) // (PDC_DBGU) Base Address\r
+#define AT91C_BASE_PIOA (0xFFFFF400) // (PIOA) Base Address\r
+#define AT91C_BASE_CKGR (0xFFFFFC20) // (CKGR) Base Address\r
+#define AT91C_BASE_PMC (0xFFFFFC00) // (PMC) Base Address\r
+#define AT91C_BASE_RSTC (0xFFFFFD00) // (RSTC) Base Address\r
+#define AT91C_BASE_RTTC (0xFFFFFD20) // (RTTC) Base Address\r
+#define AT91C_BASE_PITC (0xFFFFFD30) // (PITC) Base Address\r
+#define AT91C_BASE_WDTC (0xFFFFFD40) // (WDTC) Base Address\r
+#define AT91C_BASE_MC (0xFFFFFF00) // (MC) Base Address\r
+#define AT91C_BASE_PDC_SPI (0xFFFE0100) // (PDC_SPI) Base Address\r
+#define AT91C_BASE_SPI (0xFFFE0000) // (SPI) Base Address\r
+#define AT91C_BASE_PDC_ADC (0xFFFD8100) // (PDC_ADC) Base Address\r
+#define AT91C_BASE_ADC (0xFFFD8000) // (ADC) Base Address\r
+#define AT91C_BASE_PDC_SSC (0xFFFD4100) // (PDC_SSC) Base Address\r
+#define AT91C_BASE_SSC (0xFFFD4000) // (SSC) Base Address\r
+#define AT91C_BASE_PDC_US1 (0xFFFC4100) // (PDC_US1) Base Address\r
+#define AT91C_BASE_US1 (0xFFFC4000) // (US1) Base Address\r
+#define AT91C_BASE_PDC_US0 (0xFFFC0100) // (PDC_US0) Base Address\r
+#define AT91C_BASE_US0 (0xFFFC0000) // (US0) Base Address\r
+#define AT91C_BASE_TWI (0xFFFB8000) // (TWI) Base Address\r
+#define AT91C_BASE_TC2 (0xFFFA0080) // (TC2) Base Address\r
+#define AT91C_BASE_TC1 (0xFFFA0040) // (TC1) Base Address\r
+#define AT91C_BASE_TC0 (0xFFFA0000) // (TC0) Base Address\r
+#define AT91C_BASE_TCB (0xFFFA0000) // (TCB) Base Address\r
+#define AT91C_BASE_PWMC_CH3 (0xFFFCC260) // (PWMC_CH3) Base Address\r
+#define AT91C_BASE_PWMC_CH2 (0xFFFCC240) // (PWMC_CH2) Base Address\r
+#define AT91C_BASE_PWMC_CH1 (0xFFFCC220) // (PWMC_CH1) Base Address\r
+#define AT91C_BASE_PWMC_CH0 (0xFFFCC200) // (PWMC_CH0) Base Address\r
+#define AT91C_BASE_PWMC (0xFFFCC000) // (PWMC) Base Address\r
+#define AT91C_BASE_UDP (0xFFFB0000) // (UDP) Base Address\r
+\r
+// *****************************************************************************\r
+// MEMORY MAPPING DEFINITIONS FOR AT91SAM7S64\r
+// *****************************************************************************\r
+#define AT91C_ISRAM (0x00200000) // Internal SRAM base address\r
+#define AT91C_ISRAM_SIZE (0x00004000) // Internal SRAM size in byte (16 Kbyte)\r
+#define AT91C_IFLASH (0x00100000) // Internal ROM base address\r
+#define AT91C_IFLASH_SIZE (0x00010000) // Internal ROM size in byte (64 Kbyte)\r
+\r
+\r
--- /dev/null
+// ----------------------------------------------------------------------------\r
+// ATMEL Microcontroller Software Support - ROUSSET -\r
+// ----------------------------------------------------------------------------\r
+// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+// ----------------------------------------------------------------------------\r
+// File Name : AT91SAM7X128.h\r
+// Object : AT91SAM7X128 definitions\r
+// Generated : AT91 SW Application Group 05/20/2005 (16:22:23)\r
+// \r
+// CVS Reference : /AT91SAM7X128.pl/1.14/Tue May 10 12:12:05 2005//\r
+// CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005//\r
+// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//\r
+// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005//\r
+// CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005//\r
+// CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//\r
+// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//\r
+// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//\r
+// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005//\r
+// CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004//\r
+// CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004//\r
+// CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004//\r
+// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005//\r
+// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005//\r
+// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//\r
+// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//\r
+// CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//\r
+// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//\r
+// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//\r
+// CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//\r
+// CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005//\r
+// CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005//\r
+// CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//\r
+// CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005//\r
+// CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005//\r
+// ----------------------------------------------------------------------------\r
+\r
+#ifndef AT91SAM7X128_H\r
+#define AT91SAM7X128_H\r
+\r
+typedef volatile unsigned int AT91_REG;// Hardware register definition\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR System Peripherals\r
+// *****************************************************************************\r
+typedef struct _AT91S_SYS {\r
+ AT91_REG AIC_SMR[32]; // Source Mode Register\r
+ AT91_REG AIC_SVR[32]; // Source Vector Register\r
+ AT91_REG AIC_IVR; // IRQ Vector Register\r
+ AT91_REG AIC_FVR; // FIQ Vector Register\r
+ AT91_REG AIC_ISR; // Interrupt Status Register\r
+ AT91_REG AIC_IPR; // Interrupt Pending Register\r
+ AT91_REG AIC_IMR; // Interrupt Mask Register\r
+ AT91_REG AIC_CISR; // Core Interrupt Status Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG AIC_IECR; // Interrupt Enable Command Register\r
+ AT91_REG AIC_IDCR; // Interrupt Disable Command Register\r
+ AT91_REG AIC_ICCR; // Interrupt Clear Command Register\r
+ AT91_REG AIC_ISCR; // Interrupt Set Command Register\r
+ AT91_REG AIC_EOICR; // End of Interrupt Command Register\r
+ AT91_REG AIC_SPU; // Spurious Vector Register\r
+ AT91_REG AIC_DCR; // Debug Control Register (Protect)\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG AIC_FFER; // Fast Forcing Enable Register\r
+ AT91_REG AIC_FFDR; // Fast Forcing Disable Register\r
+ AT91_REG AIC_FFSR; // Fast Forcing Status Register\r
+ AT91_REG Reserved2[45]; // \r
+ AT91_REG DBGU_CR; // Control Register\r
+ AT91_REG DBGU_MR; // Mode Register\r
+ AT91_REG DBGU_IER; // Interrupt Enable Register\r
+ AT91_REG DBGU_IDR; // Interrupt Disable Register\r
+ AT91_REG DBGU_IMR; // Interrupt Mask Register\r
+ AT91_REG DBGU_CSR; // Channel Status Register\r
+ AT91_REG DBGU_RHR; // Receiver Holding Register\r
+ AT91_REG DBGU_THR; // Transmitter Holding Register\r
+ AT91_REG DBGU_BRGR; // Baud Rate Generator Register\r
+ AT91_REG Reserved3[7]; // \r
+ AT91_REG DBGU_CIDR; // Chip ID Register\r
+ AT91_REG DBGU_EXID; // Chip ID Extension Register\r
+ AT91_REG DBGU_FNTR; // Force NTRST Register\r
+ AT91_REG Reserved4[45]; // \r
+ AT91_REG DBGU_RPR; // Receive Pointer Register\r
+ AT91_REG DBGU_RCR; // Receive Counter Register\r
+ AT91_REG DBGU_TPR; // Transmit Pointer Register\r
+ AT91_REG DBGU_TCR; // Transmit Counter Register\r
+ AT91_REG DBGU_RNPR; // Receive Next Pointer Register\r
+ AT91_REG DBGU_RNCR; // Receive Next Counter Register\r
+ AT91_REG DBGU_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG DBGU_TNCR; // Transmit Next Counter Register\r
+ AT91_REG DBGU_PTCR; // PDC Transfer Control Register\r
+ AT91_REG DBGU_PTSR; // PDC Transfer Status Register\r
+ AT91_REG Reserved5[54]; // \r
+ AT91_REG PIOA_PER; // PIO Enable Register\r
+ AT91_REG PIOA_PDR; // PIO Disable Register\r
+ AT91_REG PIOA_PSR; // PIO Status Register\r
+ AT91_REG Reserved6[1]; // \r
+ AT91_REG PIOA_OER; // Output Enable Register\r
+ AT91_REG PIOA_ODR; // Output Disable Registerr\r
+ AT91_REG PIOA_OSR; // Output Status Register\r
+ AT91_REG Reserved7[1]; // \r
+ AT91_REG PIOA_IFER; // Input Filter Enable Register\r
+ AT91_REG PIOA_IFDR; // Input Filter Disable Register\r
+ AT91_REG PIOA_IFSR; // Input Filter Status Register\r
+ AT91_REG Reserved8[1]; // \r
+ AT91_REG PIOA_SODR; // Set Output Data Register\r
+ AT91_REG PIOA_CODR; // Clear Output Data Register\r
+ AT91_REG PIOA_ODSR; // Output Data Status Register\r
+ AT91_REG PIOA_PDSR; // Pin Data Status Register\r
+ AT91_REG PIOA_IER; // Interrupt Enable Register\r
+ AT91_REG PIOA_IDR; // Interrupt Disable Register\r
+ AT91_REG PIOA_IMR; // Interrupt Mask Register\r
+ AT91_REG PIOA_ISR; // Interrupt Status Register\r
+ AT91_REG PIOA_MDER; // Multi-driver Enable Register\r
+ AT91_REG PIOA_MDDR; // Multi-driver Disable Register\r
+ AT91_REG PIOA_MDSR; // Multi-driver Status Register\r
+ AT91_REG Reserved9[1]; // \r
+ AT91_REG PIOA_PPUDR; // Pull-up Disable Register\r
+ AT91_REG PIOA_PPUER; // Pull-up Enable Register\r
+ AT91_REG PIOA_PPUSR; // Pull-up Status Register\r
+ AT91_REG Reserved10[1]; // \r
+ AT91_REG PIOA_ASR; // Select A Register\r
+ AT91_REG PIOA_BSR; // Select B Register\r
+ AT91_REG PIOA_ABSR; // AB Select Status Register\r
+ AT91_REG Reserved11[9]; // \r
+ AT91_REG PIOA_OWER; // Output Write Enable Register\r
+ AT91_REG PIOA_OWDR; // Output Write Disable Register\r
+ AT91_REG PIOA_OWSR; // Output Write Status Register\r
+ AT91_REG Reserved12[85]; // \r
+ AT91_REG PIOB_PER; // PIO Enable Register\r
+ AT91_REG PIOB_PDR; // PIO Disable Register\r
+ AT91_REG PIOB_PSR; // PIO Status Register\r
+ AT91_REG Reserved13[1]; // \r
+ AT91_REG PIOB_OER; // Output Enable Register\r
+ AT91_REG PIOB_ODR; // Output Disable Registerr\r
+ AT91_REG PIOB_OSR; // Output Status Register\r
+ AT91_REG Reserved14[1]; // \r
+ AT91_REG PIOB_IFER; // Input Filter Enable Register\r
+ AT91_REG PIOB_IFDR; // Input Filter Disable Register\r
+ AT91_REG PIOB_IFSR; // Input Filter Status Register\r
+ AT91_REG Reserved15[1]; // \r
+ AT91_REG PIOB_SODR; // Set Output Data Register\r
+ AT91_REG PIOB_CODR; // Clear Output Data Register\r
+ AT91_REG PIOB_ODSR; // Output Data Status Register\r
+ AT91_REG PIOB_PDSR; // Pin Data Status Register\r
+ AT91_REG PIOB_IER; // Interrupt Enable Register\r
+ AT91_REG PIOB_IDR; // Interrupt Disable Register\r
+ AT91_REG PIOB_IMR; // Interrupt Mask Register\r
+ AT91_REG PIOB_ISR; // Interrupt Status Register\r
+ AT91_REG PIOB_MDER; // Multi-driver Enable Register\r
+ AT91_REG PIOB_MDDR; // Multi-driver Disable Register\r
+ AT91_REG PIOB_MDSR; // Multi-driver Status Register\r
+ AT91_REG Reserved16[1]; // \r
+ AT91_REG PIOB_PPUDR; // Pull-up Disable Register\r
+ AT91_REG PIOB_PPUER; // Pull-up Enable Register\r
+ AT91_REG PIOB_PPUSR; // Pull-up Status Register\r
+ AT91_REG Reserved17[1]; // \r
+ AT91_REG PIOB_ASR; // Select A Register\r
+ AT91_REG PIOB_BSR; // Select B Register\r
+ AT91_REG PIOB_ABSR; // AB Select Status Register\r
+ AT91_REG Reserved18[9]; // \r
+ AT91_REG PIOB_OWER; // Output Write Enable Register\r
+ AT91_REG PIOB_OWDR; // Output Write Disable Register\r
+ AT91_REG PIOB_OWSR; // Output Write Status Register\r
+ AT91_REG Reserved19[341]; // \r
+ AT91_REG PMC_SCER; // System Clock Enable Register\r
+ AT91_REG PMC_SCDR; // System Clock Disable Register\r
+ AT91_REG PMC_SCSR; // System Clock Status Register\r
+ AT91_REG Reserved20[1]; // \r
+ AT91_REG PMC_PCER; // Peripheral Clock Enable Register\r
+ AT91_REG PMC_PCDR; // Peripheral Clock Disable Register\r
+ AT91_REG PMC_PCSR; // Peripheral Clock Status Register\r
+ AT91_REG Reserved21[1]; // \r
+ AT91_REG PMC_MOR; // Main Oscillator Register\r
+ AT91_REG PMC_MCFR; // Main Clock Frequency Register\r
+ AT91_REG Reserved22[1]; // \r
+ AT91_REG PMC_PLLR; // PLL Register\r
+ AT91_REG PMC_MCKR; // Master Clock Register\r
+ AT91_REG Reserved23[3]; // \r
+ AT91_REG PMC_PCKR[4]; // Programmable Clock Register\r
+ AT91_REG Reserved24[4]; // \r
+ AT91_REG PMC_IER; // Interrupt Enable Register\r
+ AT91_REG PMC_IDR; // Interrupt Disable Register\r
+ AT91_REG PMC_SR; // Status Register\r
+ AT91_REG PMC_IMR; // Interrupt Mask Register\r
+ AT91_REG Reserved25[36]; // \r
+ AT91_REG RSTC_RCR; // Reset Control Register\r
+ AT91_REG RSTC_RSR; // Reset Status Register\r
+ AT91_REG RSTC_RMR; // Reset Mode Register\r
+ AT91_REG Reserved26[5]; // \r
+ AT91_REG RTTC_RTMR; // Real-time Mode Register\r
+ AT91_REG RTTC_RTAR; // Real-time Alarm Register\r
+ AT91_REG RTTC_RTVR; // Real-time Value Register\r
+ AT91_REG RTTC_RTSR; // Real-time Status Register\r
+ AT91_REG PITC_PIMR; // Period Interval Mode Register\r
+ AT91_REG PITC_PISR; // Period Interval Status Register\r
+ AT91_REG PITC_PIVR; // Period Interval Value Register\r
+ AT91_REG PITC_PIIR; // Period Interval Image Register\r
+ AT91_REG WDTC_WDCR; // Watchdog Control Register\r
+ AT91_REG WDTC_WDMR; // Watchdog Mode Register\r
+ AT91_REG WDTC_WDSR; // Watchdog Status Register\r
+ AT91_REG Reserved27[5]; // \r
+ AT91_REG VREG_MR; // Voltage Regulator Mode Register\r
+} AT91S_SYS, *AT91PS_SYS;\r
+\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller\r
+// *****************************************************************************\r
+typedef struct _AT91S_AIC {\r
+ AT91_REG AIC_SMR[32]; // Source Mode Register\r
+ AT91_REG AIC_SVR[32]; // Source Vector Register\r
+ AT91_REG AIC_IVR; // IRQ Vector Register\r
+ AT91_REG AIC_FVR; // FIQ Vector Register\r
+ AT91_REG AIC_ISR; // Interrupt Status Register\r
+ AT91_REG AIC_IPR; // Interrupt Pending Register\r
+ AT91_REG AIC_IMR; // Interrupt Mask Register\r
+ AT91_REG AIC_CISR; // Core Interrupt Status Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG AIC_IECR; // Interrupt Enable Command Register\r
+ AT91_REG AIC_IDCR; // Interrupt Disable Command Register\r
+ AT91_REG AIC_ICCR; // Interrupt Clear Command Register\r
+ AT91_REG AIC_ISCR; // Interrupt Set Command Register\r
+ AT91_REG AIC_EOICR; // End of Interrupt Command Register\r
+ AT91_REG AIC_SPU; // Spurious Vector Register\r
+ AT91_REG AIC_DCR; // Debug Control Register (Protect)\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG AIC_FFER; // Fast Forcing Enable Register\r
+ AT91_REG AIC_FFDR; // Fast Forcing Disable Register\r
+ AT91_REG AIC_FFSR; // Fast Forcing Status Register\r
+} AT91S_AIC, *AT91PS_AIC;\r
+\r
+// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- \r
+#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level\r
+#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level\r
+#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level\r
+#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type\r
+#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive\r
+#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ((unsigned int) 0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive\r
+#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered\r
+#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered\r
+#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive\r
+#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered\r
+// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- \r
+#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status\r
+#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status\r
+// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- \r
+#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode\r
+#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Peripheral DMA Controller\r
+// *****************************************************************************\r
+typedef struct _AT91S_PDC {\r
+ AT91_REG PDC_RPR; // Receive Pointer Register\r
+ AT91_REG PDC_RCR; // Receive Counter Register\r
+ AT91_REG PDC_TPR; // Transmit Pointer Register\r
+ AT91_REG PDC_TCR; // Transmit Counter Register\r
+ AT91_REG PDC_RNPR; // Receive Next Pointer Register\r
+ AT91_REG PDC_RNCR; // Receive Next Counter Register\r
+ AT91_REG PDC_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG PDC_TNCR; // Transmit Next Counter Register\r
+ AT91_REG PDC_PTCR; // PDC Transfer Control Register\r
+ AT91_REG PDC_PTSR; // PDC Transfer Status Register\r
+} AT91S_PDC, *AT91PS_PDC;\r
+\r
+// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- \r
+#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable\r
+#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable\r
+#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable\r
+#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable\r
+// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Debug Unit\r
+// *****************************************************************************\r
+typedef struct _AT91S_DBGU {\r
+ AT91_REG DBGU_CR; // Control Register\r
+ AT91_REG DBGU_MR; // Mode Register\r
+ AT91_REG DBGU_IER; // Interrupt Enable Register\r
+ AT91_REG DBGU_IDR; // Interrupt Disable Register\r
+ AT91_REG DBGU_IMR; // Interrupt Mask Register\r
+ AT91_REG DBGU_CSR; // Channel Status Register\r
+ AT91_REG DBGU_RHR; // Receiver Holding Register\r
+ AT91_REG DBGU_THR; // Transmitter Holding Register\r
+ AT91_REG DBGU_BRGR; // Baud Rate Generator Register\r
+ AT91_REG Reserved0[7]; // \r
+ AT91_REG DBGU_CIDR; // Chip ID Register\r
+ AT91_REG DBGU_EXID; // Chip ID Extension Register\r
+ AT91_REG DBGU_FNTR; // Force NTRST Register\r
+ AT91_REG Reserved1[45]; // \r
+ AT91_REG DBGU_RPR; // Receive Pointer Register\r
+ AT91_REG DBGU_RCR; // Receive Counter Register\r
+ AT91_REG DBGU_TPR; // Transmit Pointer Register\r
+ AT91_REG DBGU_TCR; // Transmit Counter Register\r
+ AT91_REG DBGU_RNPR; // Receive Next Pointer Register\r
+ AT91_REG DBGU_RNCR; // Receive Next Counter Register\r
+ AT91_REG DBGU_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG DBGU_TNCR; // Transmit Next Counter Register\r
+ AT91_REG DBGU_PTCR; // PDC Transfer Control Register\r
+ AT91_REG DBGU_PTSR; // PDC Transfer Status Register\r
+} AT91S_DBGU, *AT91PS_DBGU;\r
+\r
+// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- \r
+#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver\r
+#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter\r
+#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable\r
+#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable\r
+#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable\r
+#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable\r
+#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits\r
+// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- \r
+#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type\r
+#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity\r
+#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity\r
+#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space)\r
+#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark)\r
+#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity\r
+#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode\r
+#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode\r
+#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.\r
+#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.\r
+#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.\r
+#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.\r
+// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- \r
+#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt\r
+#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt\r
+#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt\r
+#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt\r
+#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt\r
+#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt\r
+#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt\r
+#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt\r
+#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt\r
+#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt\r
+#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt\r
+#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt\r
+// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- \r
+// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- \r
+// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- \r
+// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- \r
+#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Parallel Input Output Controler\r
+// *****************************************************************************\r
+typedef struct _AT91S_PIO {\r
+ AT91_REG PIO_PER; // PIO Enable Register\r
+ AT91_REG PIO_PDR; // PIO Disable Register\r
+ AT91_REG PIO_PSR; // PIO Status Register\r
+ AT91_REG Reserved0[1]; // \r
+ AT91_REG PIO_OER; // Output Enable Register\r
+ AT91_REG PIO_ODR; // Output Disable Registerr\r
+ AT91_REG PIO_OSR; // Output Status Register\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG PIO_IFER; // Input Filter Enable Register\r
+ AT91_REG PIO_IFDR; // Input Filter Disable Register\r
+ AT91_REG PIO_IFSR; // Input Filter Status Register\r
+ AT91_REG Reserved2[1]; // \r
+ AT91_REG PIO_SODR; // Set Output Data Register\r
+ AT91_REG PIO_CODR; // Clear Output Data Register\r
+ AT91_REG PIO_ODSR; // Output Data Status Register\r
+ AT91_REG PIO_PDSR; // Pin Data Status Register\r
+ AT91_REG PIO_IER; // Interrupt Enable Register\r
+ AT91_REG PIO_IDR; // Interrupt Disable Register\r
+ AT91_REG PIO_IMR; // Interrupt Mask Register\r
+ AT91_REG PIO_ISR; // Interrupt Status Register\r
+ AT91_REG PIO_MDER; // Multi-driver Enable Register\r
+ AT91_REG PIO_MDDR; // Multi-driver Disable Register\r
+ AT91_REG PIO_MDSR; // Multi-driver Status Register\r
+ AT91_REG Reserved3[1]; // \r
+ AT91_REG PIO_PPUDR; // Pull-up Disable Register\r
+ AT91_REG PIO_PPUER; // Pull-up Enable Register\r
+ AT91_REG PIO_PPUSR; // Pull-up Status Register\r
+ AT91_REG Reserved4[1]; // \r
+ AT91_REG PIO_ASR; // Select A Register\r
+ AT91_REG PIO_BSR; // Select B Register\r
+ AT91_REG PIO_ABSR; // AB Select Status Register\r
+ AT91_REG Reserved5[9]; // \r
+ AT91_REG PIO_OWER; // Output Write Enable Register\r
+ AT91_REG PIO_OWDR; // Output Write Disable Register\r
+ AT91_REG PIO_OWSR; // Output Write Status Register\r
+} AT91S_PIO, *AT91PS_PIO;\r
+\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Clock Generator Controler\r
+// *****************************************************************************\r
+typedef struct _AT91S_CKGR {\r
+ AT91_REG CKGR_MOR; // Main Oscillator Register\r
+ AT91_REG CKGR_MCFR; // Main Clock Frequency Register\r
+ AT91_REG Reserved0[1]; // \r
+ AT91_REG CKGR_PLLR; // PLL Register\r
+} AT91S_CKGR, *AT91PS_CKGR;\r
+\r
+// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- \r
+#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable\r
+#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass\r
+#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time\r
+// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- \r
+#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency\r
+#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready\r
+// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- \r
+#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected\r
+#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0\r
+#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed\r
+#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter\r
+#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range\r
+#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet\r
+#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet\r
+#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet\r
+#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet\r
+#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier\r
+#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks\r
+#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output\r
+#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2\r
+#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Power Management Controler\r
+// *****************************************************************************\r
+typedef struct _AT91S_PMC {\r
+ AT91_REG PMC_SCER; // System Clock Enable Register\r
+ AT91_REG PMC_SCDR; // System Clock Disable Register\r
+ AT91_REG PMC_SCSR; // System Clock Status Register\r
+ AT91_REG Reserved0[1]; // \r
+ AT91_REG PMC_PCER; // Peripheral Clock Enable Register\r
+ AT91_REG PMC_PCDR; // Peripheral Clock Disable Register\r
+ AT91_REG PMC_PCSR; // Peripheral Clock Status Register\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG PMC_MOR; // Main Oscillator Register\r
+ AT91_REG PMC_MCFR; // Main Clock Frequency Register\r
+ AT91_REG Reserved2[1]; // \r
+ AT91_REG PMC_PLLR; // PLL Register\r
+ AT91_REG PMC_MCKR; // Master Clock Register\r
+ AT91_REG Reserved3[3]; // \r
+ AT91_REG PMC_PCKR[4]; // Programmable Clock Register\r
+ AT91_REG Reserved4[4]; // \r
+ AT91_REG PMC_IER; // Interrupt Enable Register\r
+ AT91_REG PMC_IDR; // Interrupt Disable Register\r
+ AT91_REG PMC_SR; // Status Register\r
+ AT91_REG PMC_IMR; // Interrupt Mask Register\r
+} AT91S_PMC, *AT91PS_PMC;\r
+\r
+// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- \r
+#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock\r
+#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock\r
+#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output\r
+#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output\r
+#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output\r
+#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output\r
+// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- \r
+// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- \r
+// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- \r
+// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- \r
+// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- \r
+// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- \r
+#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection\r
+#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected\r
+#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected\r
+#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected\r
+#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler\r
+#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock\r
+#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2\r
+#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4\r
+#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8\r
+#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16\r
+#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32\r
+#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64\r
+// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- \r
+// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- \r
+#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask\r
+#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask\r
+#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask\r
+// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- \r
+// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- \r
+// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Reset Controller Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_RSTC {\r
+ AT91_REG RSTC_RCR; // Reset Control Register\r
+ AT91_REG RSTC_RSR; // Reset Status Register\r
+ AT91_REG RSTC_RMR; // Reset Mode Register\r
+} AT91S_RSTC, *AT91PS_RSTC;\r
+\r
+// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- \r
+#define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset\r
+#define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset\r
+#define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset\r
+#define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password\r
+// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- \r
+#define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status\r
+#define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status\r
+#define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type\r
+#define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising.\r
+#define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising.\r
+#define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.\r
+#define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.\r
+#define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low.\r
+#define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured.\r
+#define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level\r
+#define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress.\r
+// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- \r
+#define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable\r
+#define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable\r
+#define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable\r
+#define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_RTTC {\r
+ AT91_REG RTTC_RTMR; // Real-time Mode Register\r
+ AT91_REG RTTC_RTAR; // Real-time Alarm Register\r
+ AT91_REG RTTC_RTVR; // Real-time Value Register\r
+ AT91_REG RTTC_RTSR; // Real-time Status Register\r
+} AT91S_RTTC, *AT91PS_RTTC;\r
+\r
+// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- \r
+#define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value\r
+#define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable\r
+#define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable\r
+#define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart\r
+// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- \r
+#define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value\r
+// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- \r
+#define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value\r
+// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- \r
+#define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status\r
+#define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_PITC {\r
+ AT91_REG PITC_PIMR; // Period Interval Mode Register\r
+ AT91_REG PITC_PISR; // Period Interval Status Register\r
+ AT91_REG PITC_PIVR; // Period Interval Value Register\r
+ AT91_REG PITC_PIIR; // Period Interval Image Register\r
+} AT91S_PITC, *AT91PS_PITC;\r
+\r
+// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- \r
+#define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value\r
+#define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled\r
+#define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable\r
+// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- \r
+#define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status\r
+// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- \r
+#define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value\r
+#define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter\r
+// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_WDTC {\r
+ AT91_REG WDTC_WDCR; // Watchdog Control Register\r
+ AT91_REG WDTC_WDMR; // Watchdog Mode Register\r
+ AT91_REG WDTC_WDSR; // Watchdog Status Register\r
+} AT91S_WDTC, *AT91PS_WDTC;\r
+\r
+// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- \r
+#define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart\r
+#define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password\r
+// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- \r
+#define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart\r
+#define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable\r
+#define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable\r
+#define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart\r
+#define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable\r
+#define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value\r
+#define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt\r
+#define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt\r
+// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- \r
+#define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow\r
+#define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_VREG {\r
+ AT91_REG VREG_MR; // Voltage Regulator Mode Register\r
+} AT91S_VREG, *AT91PS_VREG;\r
+\r
+// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- \r
+#define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Memory Controller Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_MC {\r
+ AT91_REG MC_RCR; // MC Remap Control Register\r
+ AT91_REG MC_ASR; // MC Abort Status Register\r
+ AT91_REG MC_AASR; // MC Abort Address Status Register\r
+ AT91_REG Reserved0[21]; // \r
+ AT91_REG MC_FMR; // MC Flash Mode Register\r
+ AT91_REG MC_FCR; // MC Flash Command Register\r
+ AT91_REG MC_FSR; // MC Flash Status Register\r
+} AT91S_MC, *AT91PS_MC;\r
+\r
+// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- \r
+#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit\r
+// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- \r
+#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status\r
+#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status\r
+#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status\r
+#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte\r
+#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word\r
+#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word\r
+#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status\r
+#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read\r
+#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write\r
+#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch\r
+#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source\r
+#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source\r
+#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source\r
+#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source\r
+// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- \r
+#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready\r
+#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error\r
+#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error\r
+#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming\r
+#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State\r
+#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations\r
+#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations\r
+#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations\r
+#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations\r
+#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number\r
+// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- \r
+#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command\r
+#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN.\r
+#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.\r
+#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.\r
+#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.\r
+#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.\r
+#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits.\r
+#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits.\r
+#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit.\r
+#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number\r
+#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key\r
+// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- \r
+#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status\r
+#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status\r
+#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status\r
+#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status\r
+#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status\r
+#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status\r
+#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status\r
+#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status\r
+#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status\r
+#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status\r
+#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status\r
+#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status\r
+#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status\r
+#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status\r
+#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status\r
+#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status\r
+#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status\r
+#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status\r
+#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status\r
+#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status\r
+#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status\r
+#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status\r
+#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status\r
+#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status\r
+#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Serial Parallel Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_SPI {\r
+ AT91_REG SPI_CR; // Control Register\r
+ AT91_REG SPI_MR; // Mode Register\r
+ AT91_REG SPI_RDR; // Receive Data Register\r
+ AT91_REG SPI_TDR; // Transmit Data Register\r
+ AT91_REG SPI_SR; // Status Register\r
+ AT91_REG SPI_IER; // Interrupt Enable Register\r
+ AT91_REG SPI_IDR; // Interrupt Disable Register\r
+ AT91_REG SPI_IMR; // Interrupt Mask Register\r
+ AT91_REG Reserved0[4]; // \r
+ AT91_REG SPI_CSR[4]; // Chip Select Register\r
+ AT91_REG Reserved1[48]; // \r
+ AT91_REG SPI_RPR; // Receive Pointer Register\r
+ AT91_REG SPI_RCR; // Receive Counter Register\r
+ AT91_REG SPI_TPR; // Transmit Pointer Register\r
+ AT91_REG SPI_TCR; // Transmit Counter Register\r
+ AT91_REG SPI_RNPR; // Receive Next Pointer Register\r
+ AT91_REG SPI_RNCR; // Receive Next Counter Register\r
+ AT91_REG SPI_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG SPI_TNCR; // Transmit Next Counter Register\r
+ AT91_REG SPI_PTCR; // PDC Transfer Control Register\r
+ AT91_REG SPI_PTSR; // PDC Transfer Status Register\r
+} AT91S_SPI, *AT91PS_SPI;\r
+\r
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- \r
+#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable\r
+#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable\r
+#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset\r
+#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer\r
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- \r
+#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode\r
+#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select\r
+#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select\r
+#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select\r
+#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode\r
+#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection\r
+#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection\r
+#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection\r
+#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select\r
+#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects\r
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- \r
+#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data\r
+#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status\r
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- \r
+#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data\r
+#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status\r
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- \r
+#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full\r
+#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty\r
+#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error\r
+#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status\r
+#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer\r
+#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer\r
+#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt\r
+#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt\r
+#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt\r
+#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt\r
+#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status\r
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- \r
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- \r
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- \r
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- \r
+#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity\r
+#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase\r
+#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer\r
+#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer\r
+#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer\r
+#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer\r
+#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer\r
+#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer\r
+#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer\r
+#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer\r
+#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer\r
+#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer\r
+#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer\r
+#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate\r
+#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK\r
+#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Usart\r
+// *****************************************************************************\r
+typedef struct _AT91S_USART {\r
+ AT91_REG US_CR; // Control Register\r
+ AT91_REG US_MR; // Mode Register\r
+ AT91_REG US_IER; // Interrupt Enable Register\r
+ AT91_REG US_IDR; // Interrupt Disable Register\r
+ AT91_REG US_IMR; // Interrupt Mask Register\r
+ AT91_REG US_CSR; // Channel Status Register\r
+ AT91_REG US_RHR; // Receiver Holding Register\r
+ AT91_REG US_THR; // Transmitter Holding Register\r
+ AT91_REG US_BRGR; // Baud Rate Generator Register\r
+ AT91_REG US_RTOR; // Receiver Time-out Register\r
+ AT91_REG US_TTGR; // Transmitter Time-guard Register\r
+ AT91_REG Reserved0[5]; // \r
+ AT91_REG US_FIDI; // FI_DI_Ratio Register\r
+ AT91_REG US_NER; // Nb Errors Register\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG US_IF; // IRDA_FILTER Register\r
+ AT91_REG Reserved2[44]; // \r
+ AT91_REG US_RPR; // Receive Pointer Register\r
+ AT91_REG US_RCR; // Receive Counter Register\r
+ AT91_REG US_TPR; // Transmit Pointer Register\r
+ AT91_REG US_TCR; // Transmit Counter Register\r
+ AT91_REG US_RNPR; // Receive Next Pointer Register\r
+ AT91_REG US_RNCR; // Receive Next Counter Register\r
+ AT91_REG US_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG US_TNCR; // Transmit Next Counter Register\r
+ AT91_REG US_PTCR; // PDC Transfer Control Register\r
+ AT91_REG US_PTSR; // PDC Transfer Status Register\r
+} AT91S_USART, *AT91PS_USART;\r
+\r
+// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- \r
+#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break\r
+#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break\r
+#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out\r
+#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address\r
+#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations\r
+#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge\r
+#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out\r
+#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable\r
+#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable\r
+#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable\r
+#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable\r
+// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- \r
+#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode\r
+#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal\r
+#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485\r
+#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking\r
+#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem\r
+#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0\r
+#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1\r
+#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA\r
+#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking\r
+#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock\r
+#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock\r
+#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1\r
+#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM)\r
+#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK)\r
+#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock\r
+#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits\r
+#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits\r
+#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits\r
+#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits\r
+#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select\r
+#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits\r
+#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit\r
+#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits\r
+#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits\r
+#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order\r
+#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length\r
+#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select\r
+#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode\r
+#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge\r
+#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK\r
+#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions\r
+#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter\r
+// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- \r
+#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break\r
+#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out\r
+#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached\r
+#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge\r
+#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag\r
+#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag\r
+#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag\r
+#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag\r
+// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- \r
+// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- \r
+// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- \r
+#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input\r
+#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input\r
+#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input\r
+#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_SSC {\r
+ AT91_REG SSC_CR; // Control Register\r
+ AT91_REG SSC_CMR; // Clock Mode Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG SSC_RCMR; // Receive Clock ModeRegister\r
+ AT91_REG SSC_RFMR; // Receive Frame Mode Register\r
+ AT91_REG SSC_TCMR; // Transmit Clock Mode Register\r
+ AT91_REG SSC_TFMR; // Transmit Frame Mode Register\r
+ AT91_REG SSC_RHR; // Receive Holding Register\r
+ AT91_REG SSC_THR; // Transmit Holding Register\r
+ AT91_REG Reserved1[2]; // \r
+ AT91_REG SSC_RSHR; // Receive Sync Holding Register\r
+ AT91_REG SSC_TSHR; // Transmit Sync Holding Register\r
+ AT91_REG Reserved2[2]; // \r
+ AT91_REG SSC_SR; // Status Register\r
+ AT91_REG SSC_IER; // Interrupt Enable Register\r
+ AT91_REG SSC_IDR; // Interrupt Disable Register\r
+ AT91_REG SSC_IMR; // Interrupt Mask Register\r
+ AT91_REG Reserved3[44]; // \r
+ AT91_REG SSC_RPR; // Receive Pointer Register\r
+ AT91_REG SSC_RCR; // Receive Counter Register\r
+ AT91_REG SSC_TPR; // Transmit Pointer Register\r
+ AT91_REG SSC_TCR; // Transmit Counter Register\r
+ AT91_REG SSC_RNPR; // Receive Next Pointer Register\r
+ AT91_REG SSC_RNCR; // Receive Next Counter Register\r
+ AT91_REG SSC_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG SSC_TNCR; // Transmit Next Counter Register\r
+ AT91_REG SSC_PTCR; // PDC Transfer Control Register\r
+ AT91_REG SSC_PTSR; // PDC Transfer Status Register\r
+} AT91S_SSC, *AT91PS_SSC;\r
+\r
+// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- \r
+#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable\r
+#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable\r
+#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable\r
+#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable\r
+#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset\r
+// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- \r
+#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection\r
+#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock\r
+#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal\r
+#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin\r
+#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection\r
+#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only\r
+#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output\r
+#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output\r
+#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion\r
+#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection\r
+#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.\r
+#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start\r
+#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input\r
+#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input\r
+#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input\r
+#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input\r
+#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input\r
+#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input\r
+#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0\r
+#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay\r
+#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection\r
+// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- \r
+#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length\r
+#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode\r
+#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First\r
+#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame\r
+#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length\r
+#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection\r
+#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only\r
+#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse\r
+#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse\r
+#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer\r
+#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer\r
+#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer\r
+#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection\r
+// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- \r
+// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- \r
+#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value\r
+#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable\r
+// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- \r
+#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready\r
+#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty\r
+#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission\r
+#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty\r
+#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready\r
+#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun\r
+#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception\r
+#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full\r
+#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync\r
+#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync\r
+#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable\r
+#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable\r
+// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- \r
+// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- \r
+// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Two-wire Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_TWI {\r
+ AT91_REG TWI_CR; // Control Register\r
+ AT91_REG TWI_MMR; // Master Mode Register\r
+ AT91_REG Reserved0[1]; // \r
+ AT91_REG TWI_IADR; // Internal Address Register\r
+ AT91_REG TWI_CWGR; // Clock Waveform Generator Register\r
+ AT91_REG Reserved1[3]; // \r
+ AT91_REG TWI_SR; // Status Register\r
+ AT91_REG TWI_IER; // Interrupt Enable Register\r
+ AT91_REG TWI_IDR; // Interrupt Disable Register\r
+ AT91_REG TWI_IMR; // Interrupt Mask Register\r
+ AT91_REG TWI_RHR; // Receive Holding Register\r
+ AT91_REG TWI_THR; // Transmit Holding Register\r
+} AT91S_TWI, *AT91PS_TWI;\r
+\r
+// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- \r
+#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition\r
+#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition\r
+#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled\r
+#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled\r
+#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset\r
+// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- \r
+#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size\r
+#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address\r
+#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address\r
+#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address\r
+#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address\r
+#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction\r
+#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address\r
+// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- \r
+#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider\r
+#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider\r
+#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider\r
+// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- \r
+#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed\r
+#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY\r
+#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY\r
+#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error\r
+#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error\r
+#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged\r
+// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- \r
+// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- \r
+// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR PWMC Channel Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_PWMC_CH {\r
+ AT91_REG PWMC_CMR; // Channel Mode Register\r
+ AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register\r
+ AT91_REG PWMC_CPRDR; // Channel Period Register\r
+ AT91_REG PWMC_CCNTR; // Channel Counter Register\r
+ AT91_REG PWMC_CUPDR; // Channel Update Register\r
+ AT91_REG PWMC_Reserved[3]; // Reserved\r
+} AT91S_PWMC_CH, *AT91PS_PWMC_CH;\r
+\r
+// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- \r
+#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx\r
+#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH) \r
+#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH) \r
+#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH) \r
+#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment\r
+#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity\r
+#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period\r
+// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- \r
+#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle\r
+// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- \r
+#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period\r
+// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- \r
+#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter\r
+// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- \r
+#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_PWMC {\r
+ AT91_REG PWMC_MR; // PWMC Mode Register\r
+ AT91_REG PWMC_ENA; // PWMC Enable Register\r
+ AT91_REG PWMC_DIS; // PWMC Disable Register\r
+ AT91_REG PWMC_SR; // PWMC Status Register\r
+ AT91_REG PWMC_IER; // PWMC Interrupt Enable Register\r
+ AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register\r
+ AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register\r
+ AT91_REG PWMC_ISR; // PWMC Interrupt Status Register\r
+ AT91_REG Reserved0[55]; // \r
+ AT91_REG PWMC_VR; // PWMC Version Register\r
+ AT91_REG Reserved1[64]; // \r
+ AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel\r
+} AT91S_PWMC, *AT91PS_PWMC;\r
+\r
+// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- \r
+#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor.\r
+#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A\r
+#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC) \r
+#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor.\r
+#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B\r
+#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC) \r
+// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- \r
+#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0\r
+#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1\r
+#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2\r
+#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3\r
+// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- \r
+// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- \r
+// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- \r
+// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- \r
+// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- \r
+// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR USB Device Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_UDP {\r
+ AT91_REG UDP_NUM; // Frame Number Register\r
+ AT91_REG UDP_GLBSTATE; // Global State Register\r
+ AT91_REG UDP_FADDR; // Function Address Register\r
+ AT91_REG Reserved0[1]; // \r
+ AT91_REG UDP_IER; // Interrupt Enable Register\r
+ AT91_REG UDP_IDR; // Interrupt Disable Register\r
+ AT91_REG UDP_IMR; // Interrupt Mask Register\r
+ AT91_REG UDP_ISR; // Interrupt Status Register\r
+ AT91_REG UDP_ICR; // Interrupt Clear Register\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG UDP_RSTEP; // Reset Endpoint Register\r
+ AT91_REG Reserved2[1]; // \r
+ AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register\r
+ AT91_REG Reserved3[2]; // \r
+ AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register\r
+ AT91_REG Reserved4[3]; // \r
+ AT91_REG UDP_TXVC; // Transceiver Control Register\r
+} AT91S_UDP, *AT91PS_UDP;\r
+\r
+// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- \r
+#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats\r
+#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error\r
+#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK\r
+// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- \r
+#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable\r
+#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured\r
+#define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume\r
+#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host\r
+#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable\r
+// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- \r
+#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value\r
+#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable\r
+// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- \r
+#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt\r
+#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt\r
+#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt\r
+#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt\r
+#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt\r
+#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt\r
+#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt\r
+#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt\r
+#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt\r
+#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt\r
+#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt\r
+// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- \r
+// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- \r
+// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- \r
+#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt\r
+// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- \r
+// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- \r
+#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0\r
+#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1\r
+#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2\r
+#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3\r
+#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4\r
+#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5\r
+// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- \r
+#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR\r
+#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0\r
+#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)\r
+#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)\r
+#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready\r
+#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).\r
+#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).\r
+#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction\r
+#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type\r
+#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control\r
+#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT\r
+#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT\r
+#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT\r
+#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN\r
+#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN\r
+#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN\r
+#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle\r
+#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable\r
+#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO\r
+// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- \r
+#define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP) \r
+#define AT91C_UDP_PUON ((unsigned int) 0x1 << 9) // (UDP) Pull-up ON\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_TC {\r
+ AT91_REG TC_CCR; // Channel Control Register\r
+ AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode)\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG TC_CV; // Counter Value\r
+ AT91_REG TC_RA; // Register A\r
+ AT91_REG TC_RB; // Register B\r
+ AT91_REG TC_RC; // Register C\r
+ AT91_REG TC_SR; // Status Register\r
+ AT91_REG TC_IER; // Interrupt Enable Register\r
+ AT91_REG TC_IDR; // Interrupt Disable Register\r
+ AT91_REG TC_IMR; // Interrupt Mask Register\r
+} AT91S_TC, *AT91PS_TC;\r
+\r
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- \r
+#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command\r
+#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command\r
+#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command\r
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- \r
+#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection\r
+#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK\r
+#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK\r
+#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK\r
+#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK\r
+#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK\r
+#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0\r
+#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1\r
+#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2\r
+#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert\r
+#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection\r
+#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal\r
+#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock\r
+#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock\r
+#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock\r
+#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare\r
+#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading\r
+#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare\r
+#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading\r
+#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection\r
+#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None\r
+#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge\r
+#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge\r
+#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge\r
+#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection\r
+#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None\r
+#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge\r
+#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge\r
+#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge\r
+#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection\r
+#define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input\r
+#define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output\r
+#define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output\r
+#define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output\r
+#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection\r
+#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable\r
+#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection\r
+#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare\r
+#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare\r
+#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare\r
+#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare\r
+#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable\r
+#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) \r
+#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA\r
+#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none\r
+#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set\r
+#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear\r
+#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle\r
+#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection\r
+#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None\r
+#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA\r
+#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA\r
+#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA\r
+#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA\r
+#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none\r
+#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set\r
+#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear\r
+#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle\r
+#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection\r
+#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None\r
+#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA\r
+#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA\r
+#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA\r
+#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA\r
+#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none\r
+#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set\r
+#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear\r
+#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle\r
+#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA\r
+#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none\r
+#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set\r
+#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear\r
+#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle\r
+#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB\r
+#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none\r
+#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set\r
+#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear\r
+#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle\r
+#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB\r
+#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none\r
+#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set\r
+#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear\r
+#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle\r
+#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB\r
+#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none\r
+#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set\r
+#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear\r
+#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle\r
+#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB\r
+#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none\r
+#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set\r
+#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear\r
+#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle\r
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- \r
+#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow\r
+#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun\r
+#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare\r
+#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare\r
+#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare\r
+#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading\r
+#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading\r
+#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger\r
+#define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling\r
+#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror\r
+#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror\r
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- \r
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- \r
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Timer Counter Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_TCB {\r
+ AT91S_TC TCB_TC0; // TC Channel 0\r
+ AT91_REG Reserved0[4]; // \r
+ AT91S_TC TCB_TC1; // TC Channel 1\r
+ AT91_REG Reserved1[4]; // \r
+ AT91S_TC TCB_TC2; // TC Channel 2\r
+ AT91_REG Reserved2[4]; // \r
+ AT91_REG TCB_BCR; // TC Block Control Register\r
+ AT91_REG TCB_BMR; // TC Block Mode Register\r
+} AT91S_TCB, *AT91PS_TCB;\r
+\r
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- \r
+#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command\r
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- \r
+#define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection\r
+#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0\r
+#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0\r
+#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0\r
+#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0\r
+#define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection\r
+#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1\r
+#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1\r
+#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1\r
+#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1\r
+#define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection\r
+#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2\r
+#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2\r
+#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2\r
+#define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_CAN_MB {\r
+ AT91_REG CAN_MB_MMR; // MailBox Mode Register\r
+ AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register\r
+ AT91_REG CAN_MB_MID; // MailBox ID Register\r
+ AT91_REG CAN_MB_MFID; // MailBox Family ID Register\r
+ AT91_REG CAN_MB_MSR; // MailBox Status Register\r
+ AT91_REG CAN_MB_MDL; // MailBox Data Low Register\r
+ AT91_REG CAN_MB_MDH; // MailBox Data High Register\r
+ AT91_REG CAN_MB_MCR; // MailBox Control Register\r
+} AT91S_CAN_MB, *AT91PS_CAN_MB;\r
+\r
+// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- \r
+#define AT91C_CAN_MTIMEMARK ((unsigned int) 0xFFFF << 0) // (CAN_MB) Mailbox Timemark\r
+#define AT91C_CAN_PRIOR ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority\r
+#define AT91C_CAN_MOT ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type\r
+#define AT91C_CAN_MOT_DIS ((unsigned int) 0x0 << 24) // (CAN_MB) \r
+#define AT91C_CAN_MOT_RX ((unsigned int) 0x1 << 24) // (CAN_MB) \r
+#define AT91C_CAN_MOT_RXOVERWRITE ((unsigned int) 0x2 << 24) // (CAN_MB) \r
+#define AT91C_CAN_MOT_TX ((unsigned int) 0x3 << 24) // (CAN_MB) \r
+#define AT91C_CAN_MOT_CONSUMER ((unsigned int) 0x4 << 24) // (CAN_MB) \r
+#define AT91C_CAN_MOT_PRODUCER ((unsigned int) 0x5 << 24) // (CAN_MB) \r
+// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- \r
+#define AT91C_CAN_MIDvB ((unsigned int) 0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode\r
+#define AT91C_CAN_MIDvA ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode\r
+#define AT91C_CAN_MIDE ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version\r
+// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- \r
+// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- \r
+// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- \r
+#define AT91C_CAN_MTIMESTAMP ((unsigned int) 0xFFFF << 0) // (CAN_MB) Timer Value\r
+#define AT91C_CAN_MDLC ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code\r
+#define AT91C_CAN_MRTR ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request\r
+#define AT91C_CAN_MABT ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort\r
+#define AT91C_CAN_MRDY ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready\r
+#define AT91C_CAN_MMI ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored\r
+// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- \r
+// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- \r
+// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- \r
+#define AT91C_CAN_MACR ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox\r
+#define AT91C_CAN_MTCR ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Control Area Network Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_CAN {\r
+ AT91_REG CAN_MR; // Mode Register\r
+ AT91_REG CAN_IER; // Interrupt Enable Register\r
+ AT91_REG CAN_IDR; // Interrupt Disable Register\r
+ AT91_REG CAN_IMR; // Interrupt Mask Register\r
+ AT91_REG CAN_SR; // Status Register\r
+ AT91_REG CAN_BR; // Baudrate Register\r
+ AT91_REG CAN_TIM; // Timer Register\r
+ AT91_REG CAN_TIMESTP; // Time Stamp Register\r
+ AT91_REG CAN_ECR; // Error Counter Register\r
+ AT91_REG CAN_TCR; // Transfer Command Register\r
+ AT91_REG CAN_ACR; // Abort Command Register\r
+ AT91_REG Reserved0[52]; // \r
+ AT91_REG CAN_VR; // Version Register\r
+ AT91_REG Reserved1[64]; // \r
+ AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0\r
+ AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1\r
+ AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2\r
+ AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3\r
+ AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4\r
+ AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5\r
+ AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6\r
+ AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7\r
+ AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8\r
+ AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9\r
+ AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10\r
+ AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11\r
+ AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12\r
+ AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13\r
+ AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14\r
+ AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15\r
+} AT91S_CAN, *AT91PS_CAN;\r
+\r
+// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- \r
+#define AT91C_CAN_CANEN ((unsigned int) 0x1 << 0) // (CAN) CAN Controller Enable\r
+#define AT91C_CAN_LPM ((unsigned int) 0x1 << 1) // (CAN) Disable/Enable Low Power Mode\r
+#define AT91C_CAN_ABM ((unsigned int) 0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode\r
+#define AT91C_CAN_OVL ((unsigned int) 0x1 << 3) // (CAN) Disable/Enable Overload Frame\r
+#define AT91C_CAN_TEOF ((unsigned int) 0x1 << 4) // (CAN) Time Stamp messages at each end of Frame\r
+#define AT91C_CAN_TTM ((unsigned int) 0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode\r
+#define AT91C_CAN_TIMFRZ ((unsigned int) 0x1 << 6) // (CAN) Enable Timer Freeze\r
+#define AT91C_CAN_DRPT ((unsigned int) 0x1 << 7) // (CAN) Disable Repeat\r
+// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- \r
+#define AT91C_CAN_MB0 ((unsigned int) 0x1 << 0) // (CAN) Mailbox 0 Flag\r
+#define AT91C_CAN_MB1 ((unsigned int) 0x1 << 1) // (CAN) Mailbox 1 Flag\r
+#define AT91C_CAN_MB2 ((unsigned int) 0x1 << 2) // (CAN) Mailbox 2 Flag\r
+#define AT91C_CAN_MB3 ((unsigned int) 0x1 << 3) // (CAN) Mailbox 3 Flag\r
+#define AT91C_CAN_MB4 ((unsigned int) 0x1 << 4) // (CAN) Mailbox 4 Flag\r
+#define AT91C_CAN_MB5 ((unsigned int) 0x1 << 5) // (CAN) Mailbox 5 Flag\r
+#define AT91C_CAN_MB6 ((unsigned int) 0x1 << 6) // (CAN) Mailbox 6 Flag\r
+#define AT91C_CAN_MB7 ((unsigned int) 0x1 << 7) // (CAN) Mailbox 7 Flag\r
+#define AT91C_CAN_MB8 ((unsigned int) 0x1 << 8) // (CAN) Mailbox 8 Flag\r
+#define AT91C_CAN_MB9 ((unsigned int) 0x1 << 9) // (CAN) Mailbox 9 Flag\r
+#define AT91C_CAN_MB10 ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag\r
+#define AT91C_CAN_MB11 ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag\r
+#define AT91C_CAN_MB12 ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag\r
+#define AT91C_CAN_MB13 ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag\r
+#define AT91C_CAN_MB14 ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag\r
+#define AT91C_CAN_MB15 ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag\r
+#define AT91C_CAN_ERRA ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag\r
+#define AT91C_CAN_WARN ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag\r
+#define AT91C_CAN_ERRP ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag\r
+#define AT91C_CAN_BOFF ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag\r
+#define AT91C_CAN_SLEEP ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag\r
+#define AT91C_CAN_WAKEUP ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag\r
+#define AT91C_CAN_TOVF ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag\r
+#define AT91C_CAN_TSTP ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag\r
+#define AT91C_CAN_CERR ((unsigned int) 0x1 << 24) // (CAN) CRC Error\r
+#define AT91C_CAN_SERR ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error\r
+#define AT91C_CAN_AERR ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error\r
+#define AT91C_CAN_FERR ((unsigned int) 0x1 << 27) // (CAN) Form Error\r
+#define AT91C_CAN_BERR ((unsigned int) 0x1 << 28) // (CAN) Bit Error\r
+// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- \r
+// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- \r
+// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- \r
+#define AT91C_CAN_RBSY ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy\r
+#define AT91C_CAN_TBSY ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy\r
+#define AT91C_CAN_OVLY ((unsigned int) 0x1 << 31) // (CAN) Overload Busy\r
+// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- \r
+#define AT91C_CAN_PHASE2 ((unsigned int) 0x7 << 0) // (CAN) Phase 2 segment\r
+#define AT91C_CAN_PHASE1 ((unsigned int) 0x7 << 4) // (CAN) Phase 1 segment\r
+#define AT91C_CAN_PROPAG ((unsigned int) 0x7 << 8) // (CAN) Programmation time segment\r
+#define AT91C_CAN_SYNC ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment\r
+#define AT91C_CAN_BRP ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler\r
+#define AT91C_CAN_SMP ((unsigned int) 0x1 << 24) // (CAN) Sampling mode\r
+// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- \r
+#define AT91C_CAN_TIMER ((unsigned int) 0xFFFF << 0) // (CAN) Timer field\r
+// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- \r
+// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- \r
+#define AT91C_CAN_REC ((unsigned int) 0xFF << 0) // (CAN) Receive Error Counter\r
+#define AT91C_CAN_TEC ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter\r
+// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- \r
+#define AT91C_CAN_TIMRST ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field\r
+// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100\r
+// *****************************************************************************\r
+typedef struct _AT91S_EMAC {\r
+ AT91_REG EMAC_NCR; // Network Control Register\r
+ AT91_REG EMAC_NCFGR; // Network Configuration Register\r
+ AT91_REG EMAC_NSR; // Network Status Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG EMAC_TSR; // Transmit Status Register\r
+ AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer\r
+ AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer\r
+ AT91_REG EMAC_RSR; // Receive Status Register\r
+ AT91_REG EMAC_ISR; // Interrupt Status Register\r
+ AT91_REG EMAC_IER; // Interrupt Enable Register\r
+ AT91_REG EMAC_IDR; // Interrupt Disable Register\r
+ AT91_REG EMAC_IMR; // Interrupt Mask Register\r
+ AT91_REG EMAC_MAN; // PHY Maintenance Register\r
+ AT91_REG EMAC_PTR; // Pause Time Register\r
+ AT91_REG EMAC_PFR; // Pause Frames received Register\r
+ AT91_REG EMAC_FTO; // Frames Transmitted OK Register\r
+ AT91_REG EMAC_SCF; // Single Collision Frame Register\r
+ AT91_REG EMAC_MCF; // Multiple Collision Frame Register\r
+ AT91_REG EMAC_FRO; // Frames Received OK Register\r
+ AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register\r
+ AT91_REG EMAC_ALE; // Alignment Error Register\r
+ AT91_REG EMAC_DTF; // Deferred Transmission Frame Register\r
+ AT91_REG EMAC_LCOL; // Late Collision Register\r
+ AT91_REG EMAC_ECOL; // Excessive Collision Register\r
+ AT91_REG EMAC_TUND; // Transmit Underrun Error Register\r
+ AT91_REG EMAC_CSE; // Carrier Sense Error Register\r
+ AT91_REG EMAC_RRE; // Receive Ressource Error Register\r
+ AT91_REG EMAC_ROV; // Receive Overrun Errors Register\r
+ AT91_REG EMAC_RSE; // Receive Symbol Errors Register\r
+ AT91_REG EMAC_ELE; // Excessive Length Errors Register\r
+ AT91_REG EMAC_RJA; // Receive Jabbers Register\r
+ AT91_REG EMAC_USF; // Undersize Frames Register\r
+ AT91_REG EMAC_STE; // SQE Test Error Register\r
+ AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register\r
+ AT91_REG EMAC_TPF; // Transmitted Pause Frames Register\r
+ AT91_REG EMAC_HRB; // Hash Address Bottom[31:0]\r
+ AT91_REG EMAC_HRT; // Hash Address Top[63:32]\r
+ AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes\r
+ AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes\r
+ AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes\r
+ AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes\r
+ AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes\r
+ AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes\r
+ AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes\r
+ AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes\r
+ AT91_REG EMAC_TID; // Type ID Checking Register\r
+ AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register\r
+ AT91_REG EMAC_USRIO; // USER Input/Output Register\r
+ AT91_REG EMAC_WOL; // Wake On LAN Register\r
+ AT91_REG Reserved1[13]; // \r
+ AT91_REG EMAC_REV; // Revision Register\r
+} AT91S_EMAC, *AT91PS_EMAC;\r
+\r
+// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- \r
+#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.\r
+#define AT91C_EMAC_LLB ((unsigned int) 0x1 << 1) // (EMAC) Loopback local. \r
+#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) // (EMAC) Receive enable. \r
+#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) // (EMAC) Transmit enable. \r
+#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) // (EMAC) Management port enable. \r
+#define AT91C_EMAC_CLRSTAT ((unsigned int) 0x1 << 5) // (EMAC) Clear statistics registers. \r
+#define AT91C_EMAC_INCSTAT ((unsigned int) 0x1 << 6) // (EMAC) Increment statistics registers. \r
+#define AT91C_EMAC_WESTAT ((unsigned int) 0x1 << 7) // (EMAC) Write enable for statistics registers. \r
+#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) // (EMAC) Back pressure. \r
+#define AT91C_EMAC_TSTART ((unsigned int) 0x1 << 9) // (EMAC) Start Transmission. \r
+#define AT91C_EMAC_THALT ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt. \r
+#define AT91C_EMAC_TPFR ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame \r
+#define AT91C_EMAC_TZQ ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame\r
+// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- \r
+#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) // (EMAC) Speed. \r
+#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) // (EMAC) Full duplex. \r
+#define AT91C_EMAC_JFRAME ((unsigned int) 0x1 << 3) // (EMAC) Jumbo Frames. \r
+#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) // (EMAC) Copy all frames. \r
+#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) // (EMAC) No broadcast. \r
+#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) // (EMAC) Multicast hash event enable\r
+#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) // (EMAC) Unicast hash enable. \r
+#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) // (EMAC) Receive 1522 bytes. \r
+#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) // (EMAC) External address match enable. \r
+#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) // (EMAC) \r
+#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8\r
+#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16\r
+#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32\r
+#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64\r
+#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) // (EMAC) \r
+#define AT91C_EMAC_PAE ((unsigned int) 0x1 << 13) // (EMAC) \r
+#define AT91C_EMAC_RBOF ((unsigned int) 0x3 << 14) // (EMAC) \r
+#define AT91C_EMAC_RBOF_OFFSET_0 ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer\r
+#define AT91C_EMAC_RBOF_OFFSET_1 ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer\r
+#define AT91C_EMAC_RBOF_OFFSET_2 ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer\r
+#define AT91C_EMAC_RBOF_OFFSET_3 ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer\r
+#define AT91C_EMAC_RLCE ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable\r
+#define AT91C_EMAC_DRFCS ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS\r
+#define AT91C_EMAC_EFRHD ((unsigned int) 0x1 << 18) // (EMAC) \r
+#define AT91C_EMAC_IRXFCS ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS\r
+// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- \r
+#define AT91C_EMAC_LINKR ((unsigned int) 0x1 << 0) // (EMAC) \r
+#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) // (EMAC) \r
+#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) // (EMAC) \r
+// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- \r
+#define AT91C_EMAC_UBR ((unsigned int) 0x1 << 0) // (EMAC) \r
+#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) // (EMAC) \r
+#define AT91C_EMAC_RLES ((unsigned int) 0x1 << 2) // (EMAC) \r
+#define AT91C_EMAC_TGO ((unsigned int) 0x1 << 3) // (EMAC) Transmit Go\r
+#define AT91C_EMAC_BEX ((unsigned int) 0x1 << 4) // (EMAC) Buffers exhausted mid frame\r
+#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) // (EMAC) \r
+#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) // (EMAC) \r
+// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- \r
+#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) // (EMAC) \r
+#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) // (EMAC) \r
+#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 2) // (EMAC) \r
+// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- \r
+#define AT91C_EMAC_MFD ((unsigned int) 0x1 << 0) // (EMAC) \r
+#define AT91C_EMAC_RCOMP ((unsigned int) 0x1 << 1) // (EMAC) \r
+#define AT91C_EMAC_RXUBR ((unsigned int) 0x1 << 2) // (EMAC) \r
+#define AT91C_EMAC_TXUBR ((unsigned int) 0x1 << 3) // (EMAC) \r
+#define AT91C_EMAC_TUNDR ((unsigned int) 0x1 << 4) // (EMAC) \r
+#define AT91C_EMAC_RLEX ((unsigned int) 0x1 << 5) // (EMAC) \r
+#define AT91C_EMAC_TXERR ((unsigned int) 0x1 << 6) // (EMAC) \r
+#define AT91C_EMAC_TCOMP ((unsigned int) 0x1 << 7) // (EMAC) \r
+#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) // (EMAC) \r
+#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) // (EMAC) \r
+#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) // (EMAC) \r
+#define AT91C_EMAC_PFRE ((unsigned int) 0x1 << 12) // (EMAC) \r
+#define AT91C_EMAC_PTZ ((unsigned int) 0x1 << 13) // (EMAC) \r
+// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- \r
+// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- \r
+// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- \r
+// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- \r
+#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) // (EMAC) \r
+#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) // (EMAC) \r
+#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) // (EMAC) \r
+#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) // (EMAC) \r
+#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) // (EMAC) \r
+#define AT91C_EMAC_SOF ((unsigned int) 0x3 << 30) // (EMAC) \r
+// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- \r
+#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 0) // (EMAC) Reduce MII\r
+// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- \r
+#define AT91C_EMAC_IP ((unsigned int) 0xFFFF << 0) // (EMAC) ARP request IP address\r
+#define AT91C_EMAC_MAG ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable\r
+#define AT91C_EMAC_ARP ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable\r
+#define AT91C_EMAC_SA1 ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable\r
+// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- \r
+#define AT91C_EMAC_REVREF ((unsigned int) 0xFFFF << 0) // (EMAC) \r
+#define AT91C_EMAC_PARTREF ((unsigned int) 0xFFFF << 16) // (EMAC) \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Analog to Digital Convertor\r
+// *****************************************************************************\r
+typedef struct _AT91S_ADC {\r
+ AT91_REG ADC_CR; // ADC Control Register\r
+ AT91_REG ADC_MR; // ADC Mode Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG ADC_CHER; // ADC Channel Enable Register\r
+ AT91_REG ADC_CHDR; // ADC Channel Disable Register\r
+ AT91_REG ADC_CHSR; // ADC Channel Status Register\r
+ AT91_REG ADC_SR; // ADC Status Register\r
+ AT91_REG ADC_LCDR; // ADC Last Converted Data Register\r
+ AT91_REG ADC_IER; // ADC Interrupt Enable Register\r
+ AT91_REG ADC_IDR; // ADC Interrupt Disable Register\r
+ AT91_REG ADC_IMR; // ADC Interrupt Mask Register\r
+ AT91_REG ADC_CDR0; // ADC Channel Data Register 0\r
+ AT91_REG ADC_CDR1; // ADC Channel Data Register 1\r
+ AT91_REG ADC_CDR2; // ADC Channel Data Register 2\r
+ AT91_REG ADC_CDR3; // ADC Channel Data Register 3\r
+ AT91_REG ADC_CDR4; // ADC Channel Data Register 4\r
+ AT91_REG ADC_CDR5; // ADC Channel Data Register 5\r
+ AT91_REG ADC_CDR6; // ADC Channel Data Register 6\r
+ AT91_REG ADC_CDR7; // ADC Channel Data Register 7\r
+ AT91_REG Reserved1[44]; // \r
+ AT91_REG ADC_RPR; // Receive Pointer Register\r
+ AT91_REG ADC_RCR; // Receive Counter Register\r
+ AT91_REG ADC_TPR; // Transmit Pointer Register\r
+ AT91_REG ADC_TCR; // Transmit Counter Register\r
+ AT91_REG ADC_RNPR; // Receive Next Pointer Register\r
+ AT91_REG ADC_RNCR; // Receive Next Counter Register\r
+ AT91_REG ADC_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG ADC_TNCR; // Transmit Next Counter Register\r
+ AT91_REG ADC_PTCR; // PDC Transfer Control Register\r
+ AT91_REG ADC_PTSR; // PDC Transfer Status Register\r
+} AT91S_ADC, *AT91PS_ADC;\r
+\r
+// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- \r
+#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset\r
+#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion\r
+// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- \r
+#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable\r
+#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software\r
+#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.\r
+#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection\r
+#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0\r
+#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1\r
+#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2\r
+#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3\r
+#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4\r
+#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5\r
+#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger\r
+#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution.\r
+#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution\r
+#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution\r
+#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode\r
+#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode\r
+#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode\r
+#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection\r
+#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time\r
+#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time\r
+// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- \r
+#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0\r
+#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1\r
+#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2\r
+#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3\r
+#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4\r
+#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5\r
+#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6\r
+#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7\r
+// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- \r
+// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- \r
+// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- \r
+#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion\r
+#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error\r
+#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready\r
+#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun\r
+#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer\r
+#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt\r
+// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- \r
+#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted\r
+// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- \r
+// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- \r
+// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- \r
+// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- \r
+#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data\r
+// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- \r
+// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- \r
+// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- \r
+// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- \r
+// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- \r
+// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- \r
+// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Advanced Encryption Standard\r
+// *****************************************************************************\r
+typedef struct _AT91S_AES {\r
+ AT91_REG AES_CR; // Control Register\r
+ AT91_REG AES_MR; // Mode Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG AES_IER; // Interrupt Enable Register\r
+ AT91_REG AES_IDR; // Interrupt Disable Register\r
+ AT91_REG AES_IMR; // Interrupt Mask Register\r
+ AT91_REG AES_ISR; // Interrupt Status Register\r
+ AT91_REG AES_KEYWxR[4]; // Key Word x Register\r
+ AT91_REG Reserved1[4]; // \r
+ AT91_REG AES_IDATAxR[4]; // Input Data x Register\r
+ AT91_REG AES_ODATAxR[4]; // Output Data x Register\r
+ AT91_REG AES_IVxR[4]; // Initialization Vector x Register\r
+ AT91_REG Reserved2[35]; // \r
+ AT91_REG AES_VR; // AES Version Register\r
+ AT91_REG AES_RPR; // Receive Pointer Register\r
+ AT91_REG AES_RCR; // Receive Counter Register\r
+ AT91_REG AES_TPR; // Transmit Pointer Register\r
+ AT91_REG AES_TCR; // Transmit Counter Register\r
+ AT91_REG AES_RNPR; // Receive Next Pointer Register\r
+ AT91_REG AES_RNCR; // Receive Next Counter Register\r
+ AT91_REG AES_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG AES_TNCR; // Transmit Next Counter Register\r
+ AT91_REG AES_PTCR; // PDC Transfer Control Register\r
+ AT91_REG AES_PTSR; // PDC Transfer Status Register\r
+} AT91S_AES, *AT91PS_AES;\r
+\r
+// -------- AES_CR : (AES Offset: 0x0) Control Register -------- \r
+#define AT91C_AES_START ((unsigned int) 0x1 << 0) // (AES) Starts Processing\r
+#define AT91C_AES_SWRST ((unsigned int) 0x1 << 8) // (AES) Software Reset\r
+#define AT91C_AES_LOADSEED ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading\r
+// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- \r
+#define AT91C_AES_CIPHER ((unsigned int) 0x1 << 0) // (AES) Processing Mode\r
+#define AT91C_AES_PROCDLY ((unsigned int) 0xF << 4) // (AES) Processing Delay\r
+#define AT91C_AES_SMOD ((unsigned int) 0x3 << 8) // (AES) Start Mode\r
+#define AT91C_AES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.\r
+#define AT91C_AES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).\r
+#define AT91C_AES_SMOD_PDC ((unsigned int) 0x2 << 8) // (AES) PDC Mode (cf datasheet).\r
+#define AT91C_AES_OPMOD ((unsigned int) 0x7 << 12) // (AES) Operation Mode\r
+#define AT91C_AES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode.\r
+#define AT91C_AES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode.\r
+#define AT91C_AES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode.\r
+#define AT91C_AES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode.\r
+#define AT91C_AES_OPMOD_CTR ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode.\r
+#define AT91C_AES_LOD ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode\r
+#define AT91C_AES_CFBS ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size\r
+#define AT91C_AES_CFBS_128_BIT ((unsigned int) 0x0 << 16) // (AES) 128-bit.\r
+#define AT91C_AES_CFBS_64_BIT ((unsigned int) 0x1 << 16) // (AES) 64-bit.\r
+#define AT91C_AES_CFBS_32_BIT ((unsigned int) 0x2 << 16) // (AES) 32-bit.\r
+#define AT91C_AES_CFBS_16_BIT ((unsigned int) 0x3 << 16) // (AES) 16-bit.\r
+#define AT91C_AES_CFBS_8_BIT ((unsigned int) 0x4 << 16) // (AES) 8-bit.\r
+#define AT91C_AES_CKEY ((unsigned int) 0xF << 20) // (AES) Countermeasure Key\r
+#define AT91C_AES_CTYPE ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type\r
+#define AT91C_AES_CTYPE_TYPE1_EN ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled.\r
+#define AT91C_AES_CTYPE_TYPE2_EN ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled.\r
+#define AT91C_AES_CTYPE_TYPE3_EN ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled.\r
+#define AT91C_AES_CTYPE_TYPE4_EN ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled.\r
+#define AT91C_AES_CTYPE_TYPE5_EN ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled.\r
+// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- \r
+#define AT91C_AES_DATRDY ((unsigned int) 0x1 << 0) // (AES) DATRDY\r
+#define AT91C_AES_ENDRX ((unsigned int) 0x1 << 1) // (AES) PDC Read Buffer End\r
+#define AT91C_AES_ENDTX ((unsigned int) 0x1 << 2) // (AES) PDC Write Buffer End\r
+#define AT91C_AES_RXBUFF ((unsigned int) 0x1 << 3) // (AES) PDC Read Buffer Full\r
+#define AT91C_AES_TXBUFE ((unsigned int) 0x1 << 4) // (AES) PDC Write Buffer Empty\r
+#define AT91C_AES_URAD ((unsigned int) 0x1 << 8) // (AES) Unspecified Register Access Detection\r
+// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- \r
+// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- \r
+// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- \r
+#define AT91C_AES_URAT ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status\r
+#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode.\r
+#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing.\r
+#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing.\r
+#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation.\r
+#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation.\r
+#define AT91C_AES_URAT_WO_REG_READ ((unsigned int) 0x5 << 12) // (AES) Write-only register read access.\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard\r
+// *****************************************************************************\r
+typedef struct _AT91S_TDES {\r
+ AT91_REG TDES_CR; // Control Register\r
+ AT91_REG TDES_MR; // Mode Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG TDES_IER; // Interrupt Enable Register\r
+ AT91_REG TDES_IDR; // Interrupt Disable Register\r
+ AT91_REG TDES_IMR; // Interrupt Mask Register\r
+ AT91_REG TDES_ISR; // Interrupt Status Register\r
+ AT91_REG TDES_KEY1WxR[2]; // Key 1 Word x Register\r
+ AT91_REG TDES_KEY2WxR[2]; // Key 2 Word x Register\r
+ AT91_REG TDES_KEY3WxR[2]; // Key 3 Word x Register\r
+ AT91_REG Reserved1[2]; // \r
+ AT91_REG TDES_IDATAxR[2]; // Input Data x Register\r
+ AT91_REG Reserved2[2]; // \r
+ AT91_REG TDES_ODATAxR[2]; // Output Data x Register\r
+ AT91_REG Reserved3[2]; // \r
+ AT91_REG TDES_IVxR[2]; // Initialization Vector x Register\r
+ AT91_REG Reserved4[37]; // \r
+ AT91_REG TDES_VR; // TDES Version Register\r
+ AT91_REG TDES_RPR; // Receive Pointer Register\r
+ AT91_REG TDES_RCR; // Receive Counter Register\r
+ AT91_REG TDES_TPR; // Transmit Pointer Register\r
+ AT91_REG TDES_TCR; // Transmit Counter Register\r
+ AT91_REG TDES_RNPR; // Receive Next Pointer Register\r
+ AT91_REG TDES_RNCR; // Receive Next Counter Register\r
+ AT91_REG TDES_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG TDES_TNCR; // Transmit Next Counter Register\r
+ AT91_REG TDES_PTCR; // PDC Transfer Control Register\r
+ AT91_REG TDES_PTSR; // PDC Transfer Status Register\r
+} AT91S_TDES, *AT91PS_TDES;\r
+\r
+// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- \r
+#define AT91C_TDES_START ((unsigned int) 0x1 << 0) // (TDES) Starts Processing\r
+#define AT91C_TDES_SWRST ((unsigned int) 0x1 << 8) // (TDES) Software Reset\r
+// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- \r
+#define AT91C_TDES_CIPHER ((unsigned int) 0x1 << 0) // (TDES) Processing Mode\r
+#define AT91C_TDES_TDESMOD ((unsigned int) 0x1 << 1) // (TDES) Single or Triple DES Mode\r
+#define AT91C_TDES_KEYMOD ((unsigned int) 0x1 << 4) // (TDES) Key Mode\r
+#define AT91C_TDES_SMOD ((unsigned int) 0x3 << 8) // (TDES) Start Mode\r
+#define AT91C_TDES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.\r
+#define AT91C_TDES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).\r
+#define AT91C_TDES_SMOD_PDC ((unsigned int) 0x2 << 8) // (TDES) PDC Mode (cf datasheet).\r
+#define AT91C_TDES_OPMOD ((unsigned int) 0x3 << 12) // (TDES) Operation Mode\r
+#define AT91C_TDES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode.\r
+#define AT91C_TDES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode.\r
+#define AT91C_TDES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode.\r
+#define AT91C_TDES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode.\r
+#define AT91C_TDES_LOD ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode\r
+#define AT91C_TDES_CFBS ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size\r
+#define AT91C_TDES_CFBS_64_BIT ((unsigned int) 0x0 << 16) // (TDES) 64-bit.\r
+#define AT91C_TDES_CFBS_32_BIT ((unsigned int) 0x1 << 16) // (TDES) 32-bit.\r
+#define AT91C_TDES_CFBS_16_BIT ((unsigned int) 0x2 << 16) // (TDES) 16-bit.\r
+#define AT91C_TDES_CFBS_8_BIT ((unsigned int) 0x3 << 16) // (TDES) 8-bit.\r
+// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- \r
+#define AT91C_TDES_DATRDY ((unsigned int) 0x1 << 0) // (TDES) DATRDY\r
+#define AT91C_TDES_ENDRX ((unsigned int) 0x1 << 1) // (TDES) PDC Read Buffer End\r
+#define AT91C_TDES_ENDTX ((unsigned int) 0x1 << 2) // (TDES) PDC Write Buffer End\r
+#define AT91C_TDES_RXBUFF ((unsigned int) 0x1 << 3) // (TDES) PDC Read Buffer Full\r
+#define AT91C_TDES_TXBUFE ((unsigned int) 0x1 << 4) // (TDES) PDC Write Buffer Empty\r
+#define AT91C_TDES_URAD ((unsigned int) 0x1 << 8) // (TDES) Unspecified Register Access Detection\r
+// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- \r
+// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- \r
+// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- \r
+#define AT91C_TDES_URAT ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status\r
+#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode.\r
+#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing.\r
+#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing.\r
+#define AT91C_TDES_URAT_WO_REG_READ ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access.\r
+\r
+// *****************************************************************************\r
+// REGISTER ADDRESS DEFINITION FOR AT91SAM7X128\r
+// *****************************************************************************\r
+// ========== Register definition for SYS peripheral ========== \r
+// ========== Register definition for AIC peripheral ========== \r
+#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register\r
+#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register\r
+#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register\r
+#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect)\r
+#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register\r
+#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register\r
+#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register\r
+#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register\r
+#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register\r
+#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register\r
+#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register\r
+#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register\r
+#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register\r
+#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register\r
+#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register\r
+#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register\r
+#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register\r
+#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register\r
+// ========== Register definition for PDC_DBGU peripheral ========== \r
+#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register\r
+#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register\r
+#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register\r
+#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register\r
+#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register\r
+#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register\r
+#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register\r
+#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register\r
+#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register\r
+#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register\r
+// ========== Register definition for DBGU peripheral ========== \r
+#define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register\r
+#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register\r
+#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register\r
+#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register\r
+#define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register\r
+#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register\r
+#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register\r
+#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register\r
+#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register\r
+#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register\r
+#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register\r
+#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register\r
+// ========== Register definition for PIOA peripheral ========== \r
+#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr\r
+#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register\r
+#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register\r
+#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register\r
+#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register\r
+#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register\r
+#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register\r
+#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register\r
+#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register\r
+#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register\r
+#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register\r
+#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register\r
+#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register\r
+#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register\r
+#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register\r
+#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register\r
+#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register\r
+#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register\r
+#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register\r
+#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register\r
+#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register\r
+#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register\r
+#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register\r
+#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register\r
+#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register\r
+#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register\r
+#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register\r
+#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register\r
+#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register\r
+// ========== Register definition for PIOB peripheral ========== \r
+#define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register\r
+#define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register\r
+#define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register\r
+#define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register\r
+#define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register\r
+#define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register\r
+#define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register\r
+#define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register\r
+#define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register\r
+#define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register\r
+#define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register\r
+#define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register\r
+#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register\r
+#define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register\r
+#define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register\r
+#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register\r
+#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr\r
+#define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register\r
+#define AT91C_PIOB_PPUER ((AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register\r
+#define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register\r
+#define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register\r
+#define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register\r
+#define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register\r
+#define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register\r
+#define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register\r
+#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register\r
+#define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register\r
+#define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register\r
+#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register\r
+// ========== Register definition for CKGR peripheral ========== \r
+#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register\r
+#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register\r
+#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register\r
+// ========== Register definition for PMC peripheral ========== \r
+#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register\r
+#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register\r
+#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register\r
+#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register\r
+#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register\r
+#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register\r
+#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register\r
+#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register\r
+#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register\r
+#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register\r
+#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register\r
+#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register\r
+#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register\r
+#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register\r
+#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register\r
+// ========== Register definition for RSTC peripheral ========== \r
+#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register\r
+#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register\r
+#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register\r
+// ========== Register definition for RTTC peripheral ========== \r
+#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register\r
+#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register\r
+#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register\r
+#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register\r
+// ========== Register definition for PITC peripheral ========== \r
+#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register\r
+#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register\r
+#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register\r
+#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register\r
+// ========== Register definition for WDTC peripheral ========== \r
+#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register\r
+#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register\r
+#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register\r
+// ========== Register definition for VREG peripheral ========== \r
+#define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register\r
+// ========== Register definition for MC peripheral ========== \r
+#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register\r
+#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register\r
+#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register\r
+#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register\r
+#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register\r
+#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register\r
+// ========== Register definition for PDC_SPI1 peripheral ========== \r
+#define AT91C_SPI1_PTCR ((AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register\r
+#define AT91C_SPI1_RPR ((AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register\r
+#define AT91C_SPI1_TNCR ((AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register\r
+#define AT91C_SPI1_TPR ((AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register\r
+#define AT91C_SPI1_TNPR ((AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register\r
+#define AT91C_SPI1_TCR ((AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register\r
+#define AT91C_SPI1_RCR ((AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register\r
+#define AT91C_SPI1_RNPR ((AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register\r
+#define AT91C_SPI1_RNCR ((AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register\r
+#define AT91C_SPI1_PTSR ((AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register\r
+// ========== Register definition for SPI1 peripheral ========== \r
+#define AT91C_SPI1_IMR ((AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register\r
+#define AT91C_SPI1_IER ((AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register\r
+#define AT91C_SPI1_MR ((AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register\r
+#define AT91C_SPI1_RDR ((AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register\r
+#define AT91C_SPI1_IDR ((AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register\r
+#define AT91C_SPI1_SR ((AT91_REG *) 0xFFFE4010) // (SPI1) Status Register\r
+#define AT91C_SPI1_TDR ((AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register\r
+#define AT91C_SPI1_CR ((AT91_REG *) 0xFFFE4000) // (SPI1) Control Register\r
+#define AT91C_SPI1_CSR ((AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register\r
+// ========== Register definition for PDC_SPI0 peripheral ========== \r
+#define AT91C_SPI0_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register\r
+#define AT91C_SPI0_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register\r
+#define AT91C_SPI0_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register\r
+#define AT91C_SPI0_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register\r
+#define AT91C_SPI0_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register\r
+#define AT91C_SPI0_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register\r
+#define AT91C_SPI0_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register\r
+#define AT91C_SPI0_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register\r
+#define AT91C_SPI0_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register\r
+#define AT91C_SPI0_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register\r
+// ========== Register definition for SPI0 peripheral ========== \r
+#define AT91C_SPI0_IER ((AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register\r
+#define AT91C_SPI0_SR ((AT91_REG *) 0xFFFE0010) // (SPI0) Status Register\r
+#define AT91C_SPI0_IDR ((AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register\r
+#define AT91C_SPI0_CR ((AT91_REG *) 0xFFFE0000) // (SPI0) Control Register\r
+#define AT91C_SPI0_MR ((AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register\r
+#define AT91C_SPI0_IMR ((AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register\r
+#define AT91C_SPI0_TDR ((AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register\r
+#define AT91C_SPI0_RDR ((AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register\r
+#define AT91C_SPI0_CSR ((AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register\r
+// ========== Register definition for PDC_US1 peripheral ========== \r
+#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register\r
+#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register\r
+#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register\r
+#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register\r
+#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register\r
+#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register\r
+#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register\r
+#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register\r
+#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register\r
+#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register\r
+// ========== Register definition for US1 peripheral ========== \r
+#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register\r
+#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register\r
+#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register\r
+#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register\r
+#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register\r
+#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register\r
+#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register\r
+#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register\r
+#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register\r
+#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register\r
+#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register\r
+#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register\r
+#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register\r
+#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register\r
+// ========== Register definition for PDC_US0 peripheral ========== \r
+#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register\r
+#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register\r
+#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register\r
+#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register\r
+#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register\r
+#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register\r
+#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register\r
+#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register\r
+#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register\r
+#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register\r
+// ========== Register definition for US0 peripheral ========== \r
+#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register\r
+#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register\r
+#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register\r
+#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register\r
+#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register\r
+#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register\r
+#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register\r
+#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register\r
+#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register\r
+#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register\r
+#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register\r
+#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register\r
+#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register\r
+#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register\r
+// ========== Register definition for PDC_SSC peripheral ========== \r
+#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register\r
+#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register\r
+#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register\r
+#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register\r
+#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register\r
+#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register\r
+#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register\r
+#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register\r
+#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register\r
+#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register\r
+// ========== Register definition for SSC peripheral ========== \r
+#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register\r
+#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register\r
+#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register\r
+#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register\r
+#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register\r
+#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister\r
+#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register\r
+#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register\r
+#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register\r
+#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register\r
+#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register\r
+#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register\r
+#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register\r
+#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register\r
+// ========== Register definition for TWI peripheral ========== \r
+#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register\r
+#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register\r
+#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register\r
+#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register\r
+#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register\r
+#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register\r
+#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register\r
+#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register\r
+#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register\r
+#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register\r
+// ========== Register definition for PWMC_CH3 peripheral ========== \r
+#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register\r
+#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved\r
+#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register\r
+#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register\r
+#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register\r
+#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register\r
+// ========== Register definition for PWMC_CH2 peripheral ========== \r
+#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved\r
+#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register\r
+#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register\r
+#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register\r
+#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register\r
+#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register\r
+// ========== Register definition for PWMC_CH1 peripheral ========== \r
+#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved\r
+#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register\r
+#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register\r
+#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register\r
+#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register\r
+#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register\r
+// ========== Register definition for PWMC_CH0 peripheral ========== \r
+#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved\r
+#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register\r
+#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register\r
+#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register\r
+#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register\r
+#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register\r
+// ========== Register definition for PWMC peripheral ========== \r
+#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register\r
+#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register\r
+#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register\r
+#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register\r
+#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register\r
+#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register\r
+#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register\r
+#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register\r
+#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register\r
+// ========== Register definition for UDP peripheral ========== \r
+#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register\r
+#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register\r
+#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register\r
+#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register\r
+#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register\r
+#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register\r
+#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register\r
+#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register\r
+#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register\r
+#define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register\r
+#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register\r
+#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register\r
+// ========== Register definition for TC0 peripheral ========== \r
+#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register\r
+#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C\r
+#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B\r
+#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register\r
+#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register\r
+#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A\r
+#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register\r
+#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value\r
+#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register\r
+// ========== Register definition for TC1 peripheral ========== \r
+#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B\r
+#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register\r
+#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register\r
+#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register\r
+#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register\r
+#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A\r
+#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C\r
+#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register\r
+#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value\r
+// ========== Register definition for TC2 peripheral ========== \r
+#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register\r
+#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value\r
+#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A\r
+#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B\r
+#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register\r
+#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register\r
+#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C\r
+#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register\r
+#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register\r
+// ========== Register definition for TCB peripheral ========== \r
+#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register\r
+#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register\r
+// ========== Register definition for CAN_MB0 peripheral ========== \r
+#define AT91C_CAN_MB0_MDL ((AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register\r
+#define AT91C_CAN_MB0_MAM ((AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register\r
+#define AT91C_CAN_MB0_MCR ((AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register\r
+#define AT91C_CAN_MB0_MID ((AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register\r
+#define AT91C_CAN_MB0_MSR ((AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register\r
+#define AT91C_CAN_MB0_MFID ((AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register\r
+#define AT91C_CAN_MB0_MDH ((AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register\r
+#define AT91C_CAN_MB0_MMR ((AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register\r
+// ========== Register definition for CAN_MB1 peripheral ========== \r
+#define AT91C_CAN_MB1_MDL ((AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register\r
+#define AT91C_CAN_MB1_MID ((AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register\r
+#define AT91C_CAN_MB1_MMR ((AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register\r
+#define AT91C_CAN_MB1_MSR ((AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register\r
+#define AT91C_CAN_MB1_MAM ((AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register\r
+#define AT91C_CAN_MB1_MDH ((AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register\r
+#define AT91C_CAN_MB1_MCR ((AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register\r
+#define AT91C_CAN_MB1_MFID ((AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register\r
+// ========== Register definition for CAN_MB2 peripheral ========== \r
+#define AT91C_CAN_MB2_MCR ((AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register\r
+#define AT91C_CAN_MB2_MDH ((AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register\r
+#define AT91C_CAN_MB2_MID ((AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register\r
+#define AT91C_CAN_MB2_MDL ((AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register\r
+#define AT91C_CAN_MB2_MMR ((AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register\r
+#define AT91C_CAN_MB2_MAM ((AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register\r
+#define AT91C_CAN_MB2_MFID ((AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register\r
+#define AT91C_CAN_MB2_MSR ((AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register\r
+// ========== Register definition for CAN_MB3 peripheral ========== \r
+#define AT91C_CAN_MB3_MFID ((AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register\r
+#define AT91C_CAN_MB3_MAM ((AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register\r
+#define AT91C_CAN_MB3_MID ((AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register\r
+#define AT91C_CAN_MB3_MCR ((AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register\r
+#define AT91C_CAN_MB3_MMR ((AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register\r
+#define AT91C_CAN_MB3_MSR ((AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register\r
+#define AT91C_CAN_MB3_MDL ((AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register\r
+#define AT91C_CAN_MB3_MDH ((AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register\r
+// ========== Register definition for CAN_MB4 peripheral ========== \r
+#define AT91C_CAN_MB4_MID ((AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register\r
+#define AT91C_CAN_MB4_MMR ((AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register\r
+#define AT91C_CAN_MB4_MDH ((AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register\r
+#define AT91C_CAN_MB4_MFID ((AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register\r
+#define AT91C_CAN_MB4_MSR ((AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register\r
+#define AT91C_CAN_MB4_MCR ((AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register\r
+#define AT91C_CAN_MB4_MDL ((AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register\r
+#define AT91C_CAN_MB4_MAM ((AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register\r
+// ========== Register definition for CAN_MB5 peripheral ========== \r
+#define AT91C_CAN_MB5_MSR ((AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register\r
+#define AT91C_CAN_MB5_MCR ((AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register\r
+#define AT91C_CAN_MB5_MFID ((AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register\r
+#define AT91C_CAN_MB5_MDH ((AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register\r
+#define AT91C_CAN_MB5_MID ((AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register\r
+#define AT91C_CAN_MB5_MMR ((AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register\r
+#define AT91C_CAN_MB5_MDL ((AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register\r
+#define AT91C_CAN_MB5_MAM ((AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register\r
+// ========== Register definition for CAN_MB6 peripheral ========== \r
+#define AT91C_CAN_MB6_MFID ((AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register\r
+#define AT91C_CAN_MB6_MID ((AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register\r
+#define AT91C_CAN_MB6_MAM ((AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register\r
+#define AT91C_CAN_MB6_MSR ((AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register\r
+#define AT91C_CAN_MB6_MDL ((AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register\r
+#define AT91C_CAN_MB6_MCR ((AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register\r
+#define AT91C_CAN_MB6_MDH ((AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register\r
+#define AT91C_CAN_MB6_MMR ((AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register\r
+// ========== Register definition for CAN_MB7 peripheral ========== \r
+#define AT91C_CAN_MB7_MCR ((AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register\r
+#define AT91C_CAN_MB7_MDH ((AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register\r
+#define AT91C_CAN_MB7_MFID ((AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register\r
+#define AT91C_CAN_MB7_MDL ((AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register\r
+#define AT91C_CAN_MB7_MID ((AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register\r
+#define AT91C_CAN_MB7_MMR ((AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register\r
+#define AT91C_CAN_MB7_MAM ((AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register\r
+#define AT91C_CAN_MB7_MSR ((AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register\r
+// ========== Register definition for CAN peripheral ========== \r
+#define AT91C_CAN_TCR ((AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register\r
+#define AT91C_CAN_IMR ((AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register\r
+#define AT91C_CAN_IER ((AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register\r
+#define AT91C_CAN_ECR ((AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register\r
+#define AT91C_CAN_TIMESTP ((AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register\r
+#define AT91C_CAN_MR ((AT91_REG *) 0xFFFD0000) // (CAN) Mode Register\r
+#define AT91C_CAN_IDR ((AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register\r
+#define AT91C_CAN_ACR ((AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register\r
+#define AT91C_CAN_TIM ((AT91_REG *) 0xFFFD0018) // (CAN) Timer Register\r
+#define AT91C_CAN_SR ((AT91_REG *) 0xFFFD0010) // (CAN) Status Register\r
+#define AT91C_CAN_BR ((AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register\r
+#define AT91C_CAN_VR ((AT91_REG *) 0xFFFD00FC) // (CAN) Version Register\r
+// ========== Register definition for EMAC peripheral ========== \r
+#define AT91C_EMAC_ISR ((AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register\r
+#define AT91C_EMAC_SA4H ((AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes\r
+#define AT91C_EMAC_SA1L ((AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes\r
+#define AT91C_EMAC_ELE ((AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register\r
+#define AT91C_EMAC_LCOL ((AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register\r
+#define AT91C_EMAC_RLE ((AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register\r
+#define AT91C_EMAC_WOL ((AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register\r
+#define AT91C_EMAC_DTF ((AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register\r
+#define AT91C_EMAC_TUND ((AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register\r
+#define AT91C_EMAC_NCR ((AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register\r
+#define AT91C_EMAC_SA4L ((AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes\r
+#define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register\r
+#define AT91C_EMAC_SA3L ((AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes\r
+#define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register\r
+#define AT91C_EMAC_IDR ((AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register\r
+#define AT91C_EMAC_RSE ((AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register\r
+#define AT91C_EMAC_ECOL ((AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register\r
+#define AT91C_EMAC_TID ((AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register\r
+#define AT91C_EMAC_HRB ((AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]\r
+#define AT91C_EMAC_TBQP ((AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer\r
+#define AT91C_EMAC_USRIO ((AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register\r
+#define AT91C_EMAC_PTR ((AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register\r
+#define AT91C_EMAC_SA2H ((AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes\r
+#define AT91C_EMAC_ROV ((AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register\r
+#define AT91C_EMAC_ALE ((AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register\r
+#define AT91C_EMAC_RJA ((AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register\r
+#define AT91C_EMAC_RBQP ((AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer\r
+#define AT91C_EMAC_TPF ((AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register\r
+#define AT91C_EMAC_NCFGR ((AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register\r
+#define AT91C_EMAC_HRT ((AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32]\r
+#define AT91C_EMAC_USF ((AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register\r
+#define AT91C_EMAC_FCSE ((AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register\r
+#define AT91C_EMAC_TPQ ((AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register\r
+#define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register\r
+#define AT91C_EMAC_FTO ((AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register\r
+#define AT91C_EMAC_REV ((AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register\r
+#define AT91C_EMAC_IMR ((AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register\r
+#define AT91C_EMAC_SCF ((AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register\r
+#define AT91C_EMAC_PFR ((AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register\r
+#define AT91C_EMAC_MCF ((AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register\r
+#define AT91C_EMAC_NSR ((AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register\r
+#define AT91C_EMAC_SA2L ((AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes\r
+#define AT91C_EMAC_FRO ((AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register\r
+#define AT91C_EMAC_IER ((AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register\r
+#define AT91C_EMAC_SA1H ((AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes\r
+#define AT91C_EMAC_CSE ((AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register\r
+#define AT91C_EMAC_SA3H ((AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes\r
+#define AT91C_EMAC_RRE ((AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register\r
+#define AT91C_EMAC_STE ((AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register\r
+// ========== Register definition for PDC_ADC peripheral ========== \r
+#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register\r
+#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register\r
+#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register\r
+#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register\r
+#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register\r
+#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register\r
+#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register\r
+#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register\r
+#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register\r
+#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register\r
+// ========== Register definition for ADC peripheral ========== \r
+#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2\r
+#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3\r
+#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0\r
+#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5\r
+#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register\r
+#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register\r
+#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4\r
+#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1\r
+#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register\r
+#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register\r
+#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register\r
+#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7\r
+#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6\r
+#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register\r
+#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register\r
+#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register\r
+#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register\r
+#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register\r
+// ========== Register definition for PDC_AES peripheral ========== \r
+#define AT91C_AES_TPR ((AT91_REG *) 0xFFFA4108) // (PDC_AES) Transmit Pointer Register\r
+#define AT91C_AES_PTCR ((AT91_REG *) 0xFFFA4120) // (PDC_AES) PDC Transfer Control Register\r
+#define AT91C_AES_RNPR ((AT91_REG *) 0xFFFA4110) // (PDC_AES) Receive Next Pointer Register\r
+#define AT91C_AES_TNCR ((AT91_REG *) 0xFFFA411C) // (PDC_AES) Transmit Next Counter Register\r
+#define AT91C_AES_TCR ((AT91_REG *) 0xFFFA410C) // (PDC_AES) Transmit Counter Register\r
+#define AT91C_AES_RCR ((AT91_REG *) 0xFFFA4104) // (PDC_AES) Receive Counter Register\r
+#define AT91C_AES_RNCR ((AT91_REG *) 0xFFFA4114) // (PDC_AES) Receive Next Counter Register\r
+#define AT91C_AES_TNPR ((AT91_REG *) 0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register\r
+#define AT91C_AES_RPR ((AT91_REG *) 0xFFFA4100) // (PDC_AES) Receive Pointer Register\r
+#define AT91C_AES_PTSR ((AT91_REG *) 0xFFFA4124) // (PDC_AES) PDC Transfer Status Register\r
+// ========== Register definition for AES peripheral ========== \r
+#define AT91C_AES_IVxR ((AT91_REG *) 0xFFFA4060) // (AES) Initialization Vector x Register\r
+#define AT91C_AES_MR ((AT91_REG *) 0xFFFA4004) // (AES) Mode Register\r
+#define AT91C_AES_VR ((AT91_REG *) 0xFFFA40FC) // (AES) AES Version Register\r
+#define AT91C_AES_ODATAxR ((AT91_REG *) 0xFFFA4050) // (AES) Output Data x Register\r
+#define AT91C_AES_IDATAxR ((AT91_REG *) 0xFFFA4040) // (AES) Input Data x Register\r
+#define AT91C_AES_CR ((AT91_REG *) 0xFFFA4000) // (AES) Control Register\r
+#define AT91C_AES_IDR ((AT91_REG *) 0xFFFA4014) // (AES) Interrupt Disable Register\r
+#define AT91C_AES_IMR ((AT91_REG *) 0xFFFA4018) // (AES) Interrupt Mask Register\r
+#define AT91C_AES_IER ((AT91_REG *) 0xFFFA4010) // (AES) Interrupt Enable Register\r
+#define AT91C_AES_KEYWxR ((AT91_REG *) 0xFFFA4020) // (AES) Key Word x Register\r
+#define AT91C_AES_ISR ((AT91_REG *) 0xFFFA401C) // (AES) Interrupt Status Register\r
+// ========== Register definition for PDC_TDES peripheral ========== \r
+#define AT91C_TDES_RNCR ((AT91_REG *) 0xFFFA8114) // (PDC_TDES) Receive Next Counter Register\r
+#define AT91C_TDES_TCR ((AT91_REG *) 0xFFFA810C) // (PDC_TDES) Transmit Counter Register\r
+#define AT91C_TDES_RCR ((AT91_REG *) 0xFFFA8104) // (PDC_TDES) Receive Counter Register\r
+#define AT91C_TDES_TNPR ((AT91_REG *) 0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register\r
+#define AT91C_TDES_RNPR ((AT91_REG *) 0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register\r
+#define AT91C_TDES_RPR ((AT91_REG *) 0xFFFA8100) // (PDC_TDES) Receive Pointer Register\r
+#define AT91C_TDES_TNCR ((AT91_REG *) 0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register\r
+#define AT91C_TDES_TPR ((AT91_REG *) 0xFFFA8108) // (PDC_TDES) Transmit Pointer Register\r
+#define AT91C_TDES_PTSR ((AT91_REG *) 0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register\r
+#define AT91C_TDES_PTCR ((AT91_REG *) 0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register\r
+// ========== Register definition for TDES peripheral ========== \r
+#define AT91C_TDES_KEY2WxR ((AT91_REG *) 0xFFFA8028) // (TDES) Key 2 Word x Register\r
+#define AT91C_TDES_KEY3WxR ((AT91_REG *) 0xFFFA8030) // (TDES) Key 3 Word x Register\r
+#define AT91C_TDES_IDR ((AT91_REG *) 0xFFFA8014) // (TDES) Interrupt Disable Register\r
+#define AT91C_TDES_VR ((AT91_REG *) 0xFFFA80FC) // (TDES) TDES Version Register\r
+#define AT91C_TDES_IVxR ((AT91_REG *) 0xFFFA8060) // (TDES) Initialization Vector x Register\r
+#define AT91C_TDES_ODATAxR ((AT91_REG *) 0xFFFA8050) // (TDES) Output Data x Register\r
+#define AT91C_TDES_IMR ((AT91_REG *) 0xFFFA8018) // (TDES) Interrupt Mask Register\r
+#define AT91C_TDES_MR ((AT91_REG *) 0xFFFA8004) // (TDES) Mode Register\r
+#define AT91C_TDES_CR ((AT91_REG *) 0xFFFA8000) // (TDES) Control Register\r
+#define AT91C_TDES_IER ((AT91_REG *) 0xFFFA8010) // (TDES) Interrupt Enable Register\r
+#define AT91C_TDES_ISR ((AT91_REG *) 0xFFFA801C) // (TDES) Interrupt Status Register\r
+#define AT91C_TDES_IDATAxR ((AT91_REG *) 0xFFFA8040) // (TDES) Input Data x Register\r
+#define AT91C_TDES_KEY1WxR ((AT91_REG *) 0xFFFA8020) // (TDES) Key 1 Word x Register\r
+\r
+// *****************************************************************************\r
+// PIO DEFINITIONS FOR AT91SAM7X128\r
+// *****************************************************************************\r
+#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0\r
+#define AT91C_PA0_RXD0 ((unsigned int) AT91C_PIO_PA0) // USART 0 Receive Data\r
+#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1\r
+#define AT91C_PA1_TXD0 ((unsigned int) AT91C_PIO_PA1) // USART 0 Transmit Data\r
+#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10\r
+#define AT91C_PA10_TWD ((unsigned int) AT91C_PIO_PA10) // TWI Two-wire Serial Data\r
+#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11\r
+#define AT91C_PA11_TWCK ((unsigned int) AT91C_PIO_PA11) // TWI Two-wire Serial Clock\r
+#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12\r
+#define AT91C_PA12_NPCS00 ((unsigned int) AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0\r
+#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13\r
+#define AT91C_PA13_NPCS01 ((unsigned int) AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1\r
+#define AT91C_PA13_PCK1 ((unsigned int) AT91C_PIO_PA13) // PMC Programmable Clock Output 1\r
+#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14\r
+#define AT91C_PA14_NPCS02 ((unsigned int) AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2\r
+#define AT91C_PA14_IRQ1 ((unsigned int) AT91C_PIO_PA14) // External Interrupt 1\r
+#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15\r
+#define AT91C_PA15_NPCS03 ((unsigned int) AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3\r
+#define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input\r
+#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16\r
+#define AT91C_PA16_MISO0 ((unsigned int) AT91C_PIO_PA16) // SPI 0 Master In Slave\r
+#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17\r
+#define AT91C_PA17_MOSI0 ((unsigned int) AT91C_PIO_PA17) // SPI 0 Master Out Slave\r
+#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18\r
+#define AT91C_PA18_SPCK0 ((unsigned int) AT91C_PIO_PA18) // SPI 0 Serial Clock\r
+#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19\r
+#define AT91C_PA19_CANRX ((unsigned int) AT91C_PIO_PA19) // CAN Receive\r
+#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2\r
+#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock\r
+#define AT91C_PA2_NPCS11 ((unsigned int) AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1\r
+#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20\r
+#define AT91C_PA20_CANTX ((unsigned int) AT91C_PIO_PA20) // CAN Transmit\r
+#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21\r
+#define AT91C_PA21_TF ((unsigned int) AT91C_PIO_PA21) // SSC Transmit Frame Sync\r
+#define AT91C_PA21_NPCS10 ((unsigned int) AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0\r
+#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22\r
+#define AT91C_PA22_TK ((unsigned int) AT91C_PIO_PA22) // SSC Transmit Clock\r
+#define AT91C_PA22_SPCK1 ((unsigned int) AT91C_PIO_PA22) // SPI 1 Serial Clock\r
+#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23\r
+#define AT91C_PA23_TD ((unsigned int) AT91C_PIO_PA23) // SSC Transmit data\r
+#define AT91C_PA23_MOSI1 ((unsigned int) AT91C_PIO_PA23) // SPI 1 Master Out Slave\r
+#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24\r
+#define AT91C_PA24_RD ((unsigned int) AT91C_PIO_PA24) // SSC Receive Data\r
+#define AT91C_PA24_MISO1 ((unsigned int) AT91C_PIO_PA24) // SPI 1 Master In Slave\r
+#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25\r
+#define AT91C_PA25_RK ((unsigned int) AT91C_PIO_PA25) // SSC Receive Clock\r
+#define AT91C_PA25_NPCS11 ((unsigned int) AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1\r
+#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26\r
+#define AT91C_PA26_RF ((unsigned int) AT91C_PIO_PA26) // SSC Receive Frame Sync\r
+#define AT91C_PA26_NPCS12 ((unsigned int) AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2\r
+#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27\r
+#define AT91C_PA27_DRXD ((unsigned int) AT91C_PIO_PA27) // DBGU Debug Receive Data\r
+#define AT91C_PA27_PCK3 ((unsigned int) AT91C_PIO_PA27) // PMC Programmable Clock Output 3\r
+#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28\r
+#define AT91C_PA28_DTXD ((unsigned int) AT91C_PIO_PA28) // DBGU Debug Transmit Data\r
+#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29\r
+#define AT91C_PA29_FIQ ((unsigned int) AT91C_PIO_PA29) // AIC Fast Interrupt Input\r
+#define AT91C_PA29_NPCS13 ((unsigned int) AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3\r
+#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3\r
+#define AT91C_PA3_RTS0 ((unsigned int) AT91C_PIO_PA3) // USART 0 Ready To Send\r
+#define AT91C_PA3_NPCS12 ((unsigned int) AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2\r
+#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30\r
+#define AT91C_PA30_IRQ0 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 0\r
+#define AT91C_PA30_PCK2 ((unsigned int) AT91C_PIO_PA30) // PMC Programmable Clock Output 2\r
+#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4\r
+#define AT91C_PA4_CTS0 ((unsigned int) AT91C_PIO_PA4) // USART 0 Clear To Send\r
+#define AT91C_PA4_NPCS13 ((unsigned int) AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3\r
+#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5\r
+#define AT91C_PA5_RXD1 ((unsigned int) AT91C_PIO_PA5) // USART 1 Receive Data\r
+#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6\r
+#define AT91C_PA6_TXD1 ((unsigned int) AT91C_PIO_PA6) // USART 1 Transmit Data\r
+#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7\r
+#define AT91C_PA7_SCK1 ((unsigned int) AT91C_PIO_PA7) // USART 1 Serial Clock\r
+#define AT91C_PA7_NPCS01 ((unsigned int) AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1\r
+#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8\r
+#define AT91C_PA8_RTS1 ((unsigned int) AT91C_PIO_PA8) // USART 1 Ready To Send\r
+#define AT91C_PA8_NPCS02 ((unsigned int) AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2\r
+#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9\r
+#define AT91C_PA9_CTS1 ((unsigned int) AT91C_PIO_PA9) // USART 1 Clear To Send\r
+#define AT91C_PA9_NPCS03 ((unsigned int) AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3\r
+#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0\r
+#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock\r
+#define AT91C_PB0_PCK0 ((unsigned int) AT91C_PIO_PB0) // PMC Programmable Clock Output 0\r
+#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1\r
+#define AT91C_PB1_ETXEN ((unsigned int) AT91C_PIO_PB1) // Ethernet MAC Transmit Enable\r
+#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10\r
+#define AT91C_PB10_ETX2 ((unsigned int) AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2\r
+#define AT91C_PB10_NPCS11 ((unsigned int) AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1\r
+#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11\r
+#define AT91C_PB11_ETX3 ((unsigned int) AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3\r
+#define AT91C_PB11_NPCS12 ((unsigned int) AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2\r
+#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12\r
+#define AT91C_PB12_ETXER ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error\r
+#define AT91C_PB12_TCLK0 ((unsigned int) AT91C_PIO_PB12) // Timer Counter 0 external clock input\r
+#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13\r
+#define AT91C_PB13_ERX2 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Receive Data 2\r
+#define AT91C_PB13_NPCS01 ((unsigned int) AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1\r
+#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14\r
+#define AT91C_PB14_ERX3 ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Receive Data 3\r
+#define AT91C_PB14_NPCS02 ((unsigned int) AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2\r
+#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15\r
+#define AT91C_PB15_ERXDV ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid\r
+#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16\r
+#define AT91C_PB16_ECOL ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Collision Detected\r
+#define AT91C_PB16_NPCS13 ((unsigned int) AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3\r
+#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17\r
+#define AT91C_PB17_ERXCK ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Clock\r
+#define AT91C_PB17_NPCS03 ((unsigned int) AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3\r
+#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18\r
+#define AT91C_PB18_EF100 ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec\r
+#define AT91C_PB18_ADTRG ((unsigned int) AT91C_PIO_PB18) // ADC External Trigger\r
+#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19\r
+#define AT91C_PB19_PWM0 ((unsigned int) AT91C_PIO_PB19) // PWM Channel 0\r
+#define AT91C_PB19_TCLK1 ((unsigned int) AT91C_PIO_PB19) // Timer Counter 1 external clock input\r
+#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2\r
+#define AT91C_PB2_ETX0 ((unsigned int) AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0\r
+#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20\r
+#define AT91C_PB20_PWM1 ((unsigned int) AT91C_PIO_PB20) // PWM Channel 1\r
+#define AT91C_PB20_PCK0 ((unsigned int) AT91C_PIO_PB20) // PMC Programmable Clock Output 0\r
+#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21\r
+#define AT91C_PB21_PWM2 ((unsigned int) AT91C_PIO_PB21) // PWM Channel 2\r
+#define AT91C_PB21_PCK1 ((unsigned int) AT91C_PIO_PB21) // PMC Programmable Clock Output 1\r
+#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22\r
+#define AT91C_PB22_PWM3 ((unsigned int) AT91C_PIO_PB22) // PWM Channel 3\r
+#define AT91C_PB22_PCK2 ((unsigned int) AT91C_PIO_PB22) // PMC Programmable Clock Output 2\r
+#define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23\r
+#define AT91C_PB23_TIOA0 ((unsigned int) AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A\r
+#define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect\r
+#define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24\r
+#define AT91C_PB24_TIOB0 ((unsigned int) AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B\r
+#define AT91C_PB24_DSR1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Data Set ready\r
+#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25\r
+#define AT91C_PB25_TIOA1 ((unsigned int) AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A\r
+#define AT91C_PB25_DTR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Terminal ready\r
+#define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26\r
+#define AT91C_PB26_TIOB1 ((unsigned int) AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B\r
+#define AT91C_PB26_RI1 ((unsigned int) AT91C_PIO_PB26) // USART 1 Ring Indicator\r
+#define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27\r
+#define AT91C_PB27_TIOA2 ((unsigned int) AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A\r
+#define AT91C_PB27_PWM0 ((unsigned int) AT91C_PIO_PB27) // PWM Channel 0\r
+#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28\r
+#define AT91C_PB28_TIOB2 ((unsigned int) AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B\r
+#define AT91C_PB28_PWM1 ((unsigned int) AT91C_PIO_PB28) // PWM Channel 1\r
+#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29\r
+#define AT91C_PB29_PCK1 ((unsigned int) AT91C_PIO_PB29) // PMC Programmable Clock Output 1\r
+#define AT91C_PB29_PWM2 ((unsigned int) AT91C_PIO_PB29) // PWM Channel 2\r
+#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3\r
+#define AT91C_PB3_ETX1 ((unsigned int) AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1\r
+#define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30\r
+#define AT91C_PB30_PCK2 ((unsigned int) AT91C_PIO_PB30) // PMC Programmable Clock Output 2\r
+#define AT91C_PB30_PWM3 ((unsigned int) AT91C_PIO_PB30) // PWM Channel 3\r
+#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4\r
+#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid\r
+#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5\r
+#define AT91C_PB5_ERX0 ((unsigned int) AT91C_PIO_PB5) // Ethernet MAC Receive Data 0\r
+#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6\r
+#define AT91C_PB6_ERX1 ((unsigned int) AT91C_PIO_PB6) // Ethernet MAC Receive Data 1\r
+#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7\r
+#define AT91C_PB7_ERXER ((unsigned int) AT91C_PIO_PB7) // Ethernet MAC Receive Error\r
+#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8\r
+#define AT91C_PB8_EMDC ((unsigned int) AT91C_PIO_PB8) // Ethernet MAC Management Data Clock\r
+#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9\r
+#define AT91C_PB9_EMDIO ((unsigned int) AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output\r
+\r
+// *****************************************************************************\r
+// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X128\r
+// *****************************************************************************\r
+#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ)\r
+#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral\r
+#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller A\r
+#define AT91C_ID_PIOB ((unsigned int) 3) // Parallel IO Controller B\r
+#define AT91C_ID_SPI0 ((unsigned int) 4) // Serial Peripheral Interface 0\r
+#define AT91C_ID_SPI1 ((unsigned int) 5) // Serial Peripheral Interface 1\r
+#define AT91C_ID_US0 ((unsigned int) 6) // USART 0\r
+#define AT91C_ID_US1 ((unsigned int) 7) // USART 1\r
+#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller\r
+#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface\r
+#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller\r
+#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port\r
+#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0\r
+#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1\r
+#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2\r
+#define AT91C_ID_CAN ((unsigned int) 15) // Control Area Network Controller\r
+#define AT91C_ID_EMAC ((unsigned int) 16) // Ethernet MAC\r
+#define AT91C_ID_ADC ((unsigned int) 17) // Analog-to-Digital Converter\r
+#define AT91C_ID_AES ((unsigned int) 18) // Advanced Encryption Standard 128-bit\r
+#define AT91C_ID_TDES ((unsigned int) 19) // Triple Data Encryption Standard\r
+#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved\r
+#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved\r
+#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved\r
+#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved\r
+#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved\r
+#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved\r
+#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved\r
+#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved\r
+#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved\r
+#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved\r
+#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0)\r
+#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1)\r
+\r
+// *****************************************************************************\r
+// BASE ADDRESS DEFINITIONS FOR AT91SAM7X128\r
+// *****************************************************************************\r
+#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address\r
+#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address\r
+#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address\r
+#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address\r
+#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address\r
+#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address\r
+#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address\r
+#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address\r
+#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address\r
+#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address\r
+#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address\r
+#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address\r
+#define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address\r
+#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address\r
+#define AT91C_BASE_PDC_SPI1 ((AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address\r
+#define AT91C_BASE_SPI1 ((AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address\r
+#define AT91C_BASE_PDC_SPI0 ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address\r
+#define AT91C_BASE_SPI0 ((AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address\r
+#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address\r
+#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address\r
+#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address\r
+#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address\r
+#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address\r
+#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address\r
+#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address\r
+#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address\r
+#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address\r
+#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address\r
+#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address\r
+#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address\r
+#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address\r
+#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address\r
+#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address\r
+#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address\r
+#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address\r
+#define AT91C_BASE_CAN_MB0 ((AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address\r
+#define AT91C_BASE_CAN_MB1 ((AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address\r
+#define AT91C_BASE_CAN_MB2 ((AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address\r
+#define AT91C_BASE_CAN_MB3 ((AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address\r
+#define AT91C_BASE_CAN_MB4 ((AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address\r
+#define AT91C_BASE_CAN_MB5 ((AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address\r
+#define AT91C_BASE_CAN_MB6 ((AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address\r
+#define AT91C_BASE_CAN_MB7 ((AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address\r
+#define AT91C_BASE_CAN ((AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address\r
+#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address\r
+#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address\r
+#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address\r
+#define AT91C_BASE_PDC_AES ((AT91PS_PDC) 0xFFFA4100) // (PDC_AES) Base Address\r
+#define AT91C_BASE_AES ((AT91PS_AES) 0xFFFA4000) // (AES) Base Address\r
+#define AT91C_BASE_PDC_TDES ((AT91PS_PDC) 0xFFFA8100) // (PDC_TDES) Base Address\r
+#define AT91C_BASE_TDES ((AT91PS_TDES) 0xFFFA8000) // (TDES) Base Address\r
+\r
+// *****************************************************************************\r
+// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X128\r
+// *****************************************************************************\r
+#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address\r
+#define AT91C_ISRAM_SIZE ((unsigned int) 0x00008000) // Internal SRAM size in byte (32 Kbyte)\r
+#define AT91C_IFLASH ((char *) 0x00100000) // Internal ROM base address\r
+#define AT91C_IFLASH_SIZE ((unsigned int) 0x00020000) // Internal ROM size in byte (128 Kbyte)\r
+\r
+#endif\r
--- /dev/null
+// ----------------------------------------------------------------------------\r
+// ATMEL Microcontroller Software Support - ROUSSET -\r
+// ----------------------------------------------------------------------------\r
+// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+// ----------------------------------------------------------------------------\r
+// File Name : AT91SAM7X128.h\r
+// Object : AT91SAM7X128 definitions\r
+// Generated : AT91 SW Application Group 05/20/2005 (16:22:23)\r
+// \r
+// CVS Reference : /AT91SAM7X128.pl/1.14/Tue May 10 12:12:05 2005//\r
+// CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005//\r
+// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//\r
+// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005//\r
+// CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005//\r
+// CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//\r
+// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//\r
+// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//\r
+// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005//\r
+// CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004//\r
+// CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004//\r
+// CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004//\r
+// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005//\r
+// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005//\r
+// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//\r
+// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//\r
+// CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//\r
+// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//\r
+// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//\r
+// CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//\r
+// CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005//\r
+// CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005//\r
+// CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//\r
+// CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005//\r
+// CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005//\r
+// ----------------------------------------------------------------------------\r
+\r
+// Hardware register definition\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR System Peripherals\r
+// *****************************************************************************\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_AIC structure ***\r
+#define AIC_SMR ( 0) // Source Mode Register\r
+#define AIC_SVR (128) // Source Vector Register\r
+#define AIC_IVR (256) // IRQ Vector Register\r
+#define AIC_FVR (260) // FIQ Vector Register\r
+#define AIC_ISR (264) // Interrupt Status Register\r
+#define AIC_IPR (268) // Interrupt Pending Register\r
+#define AIC_IMR (272) // Interrupt Mask Register\r
+#define AIC_CISR (276) // Core Interrupt Status Register\r
+#define AIC_IECR (288) // Interrupt Enable Command Register\r
+#define AIC_IDCR (292) // Interrupt Disable Command Register\r
+#define AIC_ICCR (296) // Interrupt Clear Command Register\r
+#define AIC_ISCR (300) // Interrupt Set Command Register\r
+#define AIC_EOICR (304) // End of Interrupt Command Register\r
+#define AIC_SPU (308) // Spurious Vector Register\r
+#define AIC_DCR (312) // Debug Control Register (Protect)\r
+#define AIC_FFER (320) // Fast Forcing Enable Register\r
+#define AIC_FFDR (324) // Fast Forcing Disable Register\r
+#define AIC_FFSR (328) // Fast Forcing Status Register\r
+// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- \r
+#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level\r
+#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level\r
+#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level\r
+#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type\r
+#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive\r
+#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive\r
+#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered\r
+#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered\r
+#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive\r
+#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered\r
+// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- \r
+#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status\r
+#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status\r
+// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- \r
+#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode\r
+#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Peripheral DMA Controller\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_PDC structure ***\r
+#define PDC_RPR ( 0) // Receive Pointer Register\r
+#define PDC_RCR ( 4) // Receive Counter Register\r
+#define PDC_TPR ( 8) // Transmit Pointer Register\r
+#define PDC_TCR (12) // Transmit Counter Register\r
+#define PDC_RNPR (16) // Receive Next Pointer Register\r
+#define PDC_RNCR (20) // Receive Next Counter Register\r
+#define PDC_TNPR (24) // Transmit Next Pointer Register\r
+#define PDC_TNCR (28) // Transmit Next Counter Register\r
+#define PDC_PTCR (32) // PDC Transfer Control Register\r
+#define PDC_PTSR (36) // PDC Transfer Status Register\r
+// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- \r
+#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable\r
+#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable\r
+#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable\r
+#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable\r
+// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Debug Unit\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_DBGU structure ***\r
+#define DBGU_CR ( 0) // Control Register\r
+#define DBGU_MR ( 4) // Mode Register\r
+#define DBGU_IER ( 8) // Interrupt Enable Register\r
+#define DBGU_IDR (12) // Interrupt Disable Register\r
+#define DBGU_IMR (16) // Interrupt Mask Register\r
+#define DBGU_CSR (20) // Channel Status Register\r
+#define DBGU_RHR (24) // Receiver Holding Register\r
+#define DBGU_THR (28) // Transmitter Holding Register\r
+#define DBGU_BRGR (32) // Baud Rate Generator Register\r
+#define DBGU_CIDR (64) // Chip ID Register\r
+#define DBGU_EXID (68) // Chip ID Extension Register\r
+#define DBGU_FNTR (72) // Force NTRST Register\r
+#define DBGU_RPR (256) // Receive Pointer Register\r
+#define DBGU_RCR (260) // Receive Counter Register\r
+#define DBGU_TPR (264) // Transmit Pointer Register\r
+#define DBGU_TCR (268) // Transmit Counter Register\r
+#define DBGU_RNPR (272) // Receive Next Pointer Register\r
+#define DBGU_RNCR (276) // Receive Next Counter Register\r
+#define DBGU_TNPR (280) // Transmit Next Pointer Register\r
+#define DBGU_TNCR (284) // Transmit Next Counter Register\r
+#define DBGU_PTCR (288) // PDC Transfer Control Register\r
+#define DBGU_PTSR (292) // PDC Transfer Status Register\r
+// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- \r
+#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver\r
+#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter\r
+#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable\r
+#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable\r
+#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable\r
+#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable\r
+#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits\r
+// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- \r
+#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type\r
+#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity\r
+#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity\r
+#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space)\r
+#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark)\r
+#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity\r
+#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode\r
+#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode\r
+#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.\r
+#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.\r
+#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.\r
+#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.\r
+// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- \r
+#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt\r
+#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt\r
+#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt\r
+#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt\r
+#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt\r
+#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt\r
+#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt\r
+#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt\r
+#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt\r
+#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt\r
+#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt\r
+#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt\r
+// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- \r
+// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- \r
+// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- \r
+// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- \r
+#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Parallel Input Output Controler\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_PIO structure ***\r
+#define PIO_PER ( 0) // PIO Enable Register\r
+#define PIO_PDR ( 4) // PIO Disable Register\r
+#define PIO_PSR ( 8) // PIO Status Register\r
+#define PIO_OER (16) // Output Enable Register\r
+#define PIO_ODR (20) // Output Disable Registerr\r
+#define PIO_OSR (24) // Output Status Register\r
+#define PIO_IFER (32) // Input Filter Enable Register\r
+#define PIO_IFDR (36) // Input Filter Disable Register\r
+#define PIO_IFSR (40) // Input Filter Status Register\r
+#define PIO_SODR (48) // Set Output Data Register\r
+#define PIO_CODR (52) // Clear Output Data Register\r
+#define PIO_ODSR (56) // Output Data Status Register\r
+#define PIO_PDSR (60) // Pin Data Status Register\r
+#define PIO_IER (64) // Interrupt Enable Register\r
+#define PIO_IDR (68) // Interrupt Disable Register\r
+#define PIO_IMR (72) // Interrupt Mask Register\r
+#define PIO_ISR (76) // Interrupt Status Register\r
+#define PIO_MDER (80) // Multi-driver Enable Register\r
+#define PIO_MDDR (84) // Multi-driver Disable Register\r
+#define PIO_MDSR (88) // Multi-driver Status Register\r
+#define PIO_PPUDR (96) // Pull-up Disable Register\r
+#define PIO_PPUER (100) // Pull-up Enable Register\r
+#define PIO_PPUSR (104) // Pull-up Status Register\r
+#define PIO_ASR (112) // Select A Register\r
+#define PIO_BSR (116) // Select B Register\r
+#define PIO_ABSR (120) // AB Select Status Register\r
+#define PIO_OWER (160) // Output Write Enable Register\r
+#define PIO_OWDR (164) // Output Write Disable Register\r
+#define PIO_OWSR (168) // Output Write Status Register\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Clock Generator Controler\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_CKGR structure ***\r
+#define CKGR_MOR ( 0) // Main Oscillator Register\r
+#define CKGR_MCFR ( 4) // Main Clock Frequency Register\r
+#define CKGR_PLLR (12) // PLL Register\r
+// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- \r
+#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable\r
+#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass\r
+#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time\r
+// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- \r
+#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency\r
+#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready\r
+// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- \r
+#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected\r
+#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0\r
+#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed\r
+#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter\r
+#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range\r
+#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet\r
+#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet\r
+#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet\r
+#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet\r
+#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier\r
+#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks\r
+#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output\r
+#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2\r
+#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Power Management Controler\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_PMC structure ***\r
+#define PMC_SCER ( 0) // System Clock Enable Register\r
+#define PMC_SCDR ( 4) // System Clock Disable Register\r
+#define PMC_SCSR ( 8) // System Clock Status Register\r
+#define PMC_PCER (16) // Peripheral Clock Enable Register\r
+#define PMC_PCDR (20) // Peripheral Clock Disable Register\r
+#define PMC_PCSR (24) // Peripheral Clock Status Register\r
+#define PMC_MOR (32) // Main Oscillator Register\r
+#define PMC_MCFR (36) // Main Clock Frequency Register\r
+#define PMC_PLLR (44) // PLL Register\r
+#define PMC_MCKR (48) // Master Clock Register\r
+#define PMC_PCKR (64) // Programmable Clock Register\r
+#define PMC_IER (96) // Interrupt Enable Register\r
+#define PMC_IDR (100) // Interrupt Disable Register\r
+#define PMC_SR (104) // Status Register\r
+#define PMC_IMR (108) // Interrupt Mask Register\r
+// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- \r
+#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock\r
+#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock\r
+#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output\r
+#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output\r
+#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output\r
+#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output\r
+// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- \r
+// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- \r
+// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- \r
+// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- \r
+// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- \r
+// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- \r
+#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection\r
+#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected\r
+#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected\r
+#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected\r
+#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler\r
+#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock\r
+#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2\r
+#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4\r
+#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8\r
+#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16\r
+#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32\r
+#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64\r
+// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- \r
+// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- \r
+#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask\r
+#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask\r
+#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask\r
+// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- \r
+// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- \r
+// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Reset Controller Interface\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_RSTC structure ***\r
+#define RSTC_RCR ( 0) // Reset Control Register\r
+#define RSTC_RSR ( 4) // Reset Status Register\r
+#define RSTC_RMR ( 8) // Reset Mode Register\r
+// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- \r
+#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset\r
+#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset\r
+#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset\r
+#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password\r
+// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- \r
+#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status\r
+#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status\r
+#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type\r
+#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising.\r
+#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising.\r
+#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.\r
+#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.\r
+#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low.\r
+#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured.\r
+#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level\r
+#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress.\r
+// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- \r
+#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable\r
+#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable\r
+#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Enable\r
+#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_RTTC structure ***\r
+#define RTTC_RTMR ( 0) // Real-time Mode Register\r
+#define RTTC_RTAR ( 4) // Real-time Alarm Register\r
+#define RTTC_RTVR ( 8) // Real-time Value Register\r
+#define RTTC_RTSR (12) // Real-time Status Register\r
+// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- \r
+#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value\r
+#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable\r
+#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable\r
+#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart\r
+// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- \r
+#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value\r
+// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- \r
+#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value\r
+// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- \r
+#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status\r
+#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_PITC structure ***\r
+#define PITC_PIMR ( 0) // Period Interval Mode Register\r
+#define PITC_PISR ( 4) // Period Interval Status Register\r
+#define PITC_PIVR ( 8) // Period Interval Value Register\r
+#define PITC_PIIR (12) // Period Interval Image Register\r
+// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- \r
+#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value\r
+#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled\r
+#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable\r
+// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- \r
+#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status\r
+// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- \r
+#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value\r
+#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter\r
+// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_WDTC structure ***\r
+#define WDTC_WDCR ( 0) // Watchdog Control Register\r
+#define WDTC_WDMR ( 4) // Watchdog Mode Register\r
+#define WDTC_WDSR ( 8) // Watchdog Status Register\r
+// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- \r
+#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart\r
+#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password\r
+// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- \r
+#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart\r
+#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable\r
+#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable\r
+#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart\r
+#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable\r
+#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value\r
+#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt\r
+#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt\r
+// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- \r
+#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow\r
+#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_VREG structure ***\r
+#define VREG_MR ( 0) // Voltage Regulator Mode Register\r
+// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- \r
+#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Memory Controller Interface\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_MC structure ***\r
+#define MC_RCR ( 0) // MC Remap Control Register\r
+#define MC_ASR ( 4) // MC Abort Status Register\r
+#define MC_AASR ( 8) // MC Abort Address Status Register\r
+#define MC_FMR (96) // MC Flash Mode Register\r
+#define MC_FCR (100) // MC Flash Command Register\r
+#define MC_FSR (104) // MC Flash Status Register\r
+// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- \r
+#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit\r
+// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- \r
+#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status\r
+#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status\r
+#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status\r
+#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte\r
+#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word\r
+#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word\r
+#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status\r
+#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read\r
+#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write\r
+#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch\r
+#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source\r
+#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source\r
+#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source\r
+#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source\r
+// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- \r
+#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready\r
+#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error\r
+#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error\r
+#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming\r
+#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State\r
+#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations\r
+#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations\r
+#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations\r
+#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations\r
+#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number\r
+// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- \r
+#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command\r
+#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN.\r
+#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.\r
+#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.\r
+#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.\r
+#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.\r
+#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits.\r
+#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits.\r
+#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit.\r
+#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number\r
+#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key\r
+// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- \r
+#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status\r
+#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status\r
+#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status\r
+#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status\r
+#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status\r
+#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status\r
+#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status\r
+#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status\r
+#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status\r
+#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status\r
+#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status\r
+#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status\r
+#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status\r
+#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status\r
+#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status\r
+#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status\r
+#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status\r
+#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status\r
+#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status\r
+#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status\r
+#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status\r
+#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status\r
+#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status\r
+#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status\r
+#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Serial Parallel Interface\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_SPI structure ***\r
+#define SPI_CR ( 0) // Control Register\r
+#define SPI_MR ( 4) // Mode Register\r
+#define SPI_RDR ( 8) // Receive Data Register\r
+#define SPI_TDR (12) // Transmit Data Register\r
+#define SPI_SR (16) // Status Register\r
+#define SPI_IER (20) // Interrupt Enable Register\r
+#define SPI_IDR (24) // Interrupt Disable Register\r
+#define SPI_IMR (28) // Interrupt Mask Register\r
+#define SPI_CSR (48) // Chip Select Register\r
+#define SPI_RPR (256) // Receive Pointer Register\r
+#define SPI_RCR (260) // Receive Counter Register\r
+#define SPI_TPR (264) // Transmit Pointer Register\r
+#define SPI_TCR (268) // Transmit Counter Register\r
+#define SPI_RNPR (272) // Receive Next Pointer Register\r
+#define SPI_RNCR (276) // Receive Next Counter Register\r
+#define SPI_TNPR (280) // Transmit Next Pointer Register\r
+#define SPI_TNCR (284) // Transmit Next Counter Register\r
+#define SPI_PTCR (288) // PDC Transfer Control Register\r
+#define SPI_PTSR (292) // PDC Transfer Status Register\r
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- \r
+#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable\r
+#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable\r
+#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset\r
+#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer\r
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- \r
+#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode\r
+#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select\r
+#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select\r
+#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select\r
+#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode\r
+#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection\r
+#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection\r
+#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection\r
+#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select\r
+#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects\r
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- \r
+#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data\r
+#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status\r
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- \r
+#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data\r
+#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status\r
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- \r
+#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full\r
+#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty\r
+#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error\r
+#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status\r
+#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer\r
+#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer\r
+#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt\r
+#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt\r
+#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt\r
+#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt\r
+#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status\r
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- \r
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- \r
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- \r
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- \r
+#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity\r
+#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase\r
+#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer\r
+#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer\r
+#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer\r
+#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer\r
+#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer\r
+#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer\r
+#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer\r
+#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer\r
+#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer\r
+#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer\r
+#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer\r
+#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate\r
+#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK\r
+#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Usart\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_USART structure ***\r
+#define US_CR ( 0) // Control Register\r
+#define US_MR ( 4) // Mode Register\r
+#define US_IER ( 8) // Interrupt Enable Register\r
+#define US_IDR (12) // Interrupt Disable Register\r
+#define US_IMR (16) // Interrupt Mask Register\r
+#define US_CSR (20) // Channel Status Register\r
+#define US_RHR (24) // Receiver Holding Register\r
+#define US_THR (28) // Transmitter Holding Register\r
+#define US_BRGR (32) // Baud Rate Generator Register\r
+#define US_RTOR (36) // Receiver Time-out Register\r
+#define US_TTGR (40) // Transmitter Time-guard Register\r
+#define US_FIDI (64) // FI_DI_Ratio Register\r
+#define US_NER (68) // Nb Errors Register\r
+#define US_IF (76) // IRDA_FILTER Register\r
+#define US_RPR (256) // Receive Pointer Register\r
+#define US_RCR (260) // Receive Counter Register\r
+#define US_TPR (264) // Transmit Pointer Register\r
+#define US_TCR (268) // Transmit Counter Register\r
+#define US_RNPR (272) // Receive Next Pointer Register\r
+#define US_RNCR (276) // Receive Next Counter Register\r
+#define US_TNPR (280) // Transmit Next Pointer Register\r
+#define US_TNCR (284) // Transmit Next Counter Register\r
+#define US_PTCR (288) // PDC Transfer Control Register\r
+#define US_PTSR (292) // PDC Transfer Status Register\r
+// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- \r
+#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break\r
+#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break\r
+#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out\r
+#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address\r
+#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations\r
+#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge\r
+#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out\r
+#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable\r
+#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable\r
+#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable\r
+#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable\r
+// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- \r
+#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode\r
+#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal\r
+#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485\r
+#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking\r
+#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem\r
+#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0\r
+#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1\r
+#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA\r
+#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking\r
+#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock\r
+#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock\r
+#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1\r
+#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM)\r
+#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK)\r
+#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock\r
+#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits\r
+#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits\r
+#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits\r
+#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits\r
+#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select\r
+#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits\r
+#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit\r
+#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits\r
+#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits\r
+#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order\r
+#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length\r
+#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select\r
+#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode\r
+#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge\r
+#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK\r
+#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions\r
+#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter\r
+// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- \r
+#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break\r
+#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out\r
+#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached\r
+#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge\r
+#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag\r
+#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag\r
+#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag\r
+#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag\r
+// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- \r
+// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- \r
+// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- \r
+#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input\r
+#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input\r
+#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input\r
+#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_SSC structure ***\r
+#define SSC_CR ( 0) // Control Register\r
+#define SSC_CMR ( 4) // Clock Mode Register\r
+#define SSC_RCMR (16) // Receive Clock ModeRegister\r
+#define SSC_RFMR (20) // Receive Frame Mode Register\r
+#define SSC_TCMR (24) // Transmit Clock Mode Register\r
+#define SSC_TFMR (28) // Transmit Frame Mode Register\r
+#define SSC_RHR (32) // Receive Holding Register\r
+#define SSC_THR (36) // Transmit Holding Register\r
+#define SSC_RSHR (48) // Receive Sync Holding Register\r
+#define SSC_TSHR (52) // Transmit Sync Holding Register\r
+#define SSC_SR (64) // Status Register\r
+#define SSC_IER (68) // Interrupt Enable Register\r
+#define SSC_IDR (72) // Interrupt Disable Register\r
+#define SSC_IMR (76) // Interrupt Mask Register\r
+#define SSC_RPR (256) // Receive Pointer Register\r
+#define SSC_RCR (260) // Receive Counter Register\r
+#define SSC_TPR (264) // Transmit Pointer Register\r
+#define SSC_TCR (268) // Transmit Counter Register\r
+#define SSC_RNPR (272) // Receive Next Pointer Register\r
+#define SSC_RNCR (276) // Receive Next Counter Register\r
+#define SSC_TNPR (280) // Transmit Next Pointer Register\r
+#define SSC_TNCR (284) // Transmit Next Counter Register\r
+#define SSC_PTCR (288) // PDC Transfer Control Register\r
+#define SSC_PTSR (292) // PDC Transfer Status Register\r
+// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- \r
+#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable\r
+#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable\r
+#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable\r
+#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable\r
+#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset\r
+// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- \r
+#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection\r
+#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock\r
+#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal\r
+#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin\r
+#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection\r
+#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only\r
+#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output\r
+#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output\r
+#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion\r
+#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection\r
+#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.\r
+#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start\r
+#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input\r
+#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input\r
+#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input\r
+#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input\r
+#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input\r
+#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input\r
+#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0\r
+#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay\r
+#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection\r
+// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- \r
+#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length\r
+#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode\r
+#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First\r
+#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame\r
+#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length\r
+#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection\r
+#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only\r
+#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse\r
+#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse\r
+#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer\r
+#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer\r
+#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer\r
+#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection\r
+// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- \r
+// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- \r
+#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value\r
+#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable\r
+// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- \r
+#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready\r
+#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty\r
+#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission\r
+#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty\r
+#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready\r
+#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun\r
+#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception\r
+#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full\r
+#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync\r
+#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync\r
+#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable\r
+#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable\r
+// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- \r
+// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- \r
+// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Two-wire Interface\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_TWI structure ***\r
+#define TWI_CR ( 0) // Control Register\r
+#define TWI_MMR ( 4) // Master Mode Register\r
+#define TWI_IADR (12) // Internal Address Register\r
+#define TWI_CWGR (16) // Clock Waveform Generator Register\r
+#define TWI_SR (32) // Status Register\r
+#define TWI_IER (36) // Interrupt Enable Register\r
+#define TWI_IDR (40) // Interrupt Disable Register\r
+#define TWI_IMR (44) // Interrupt Mask Register\r
+#define TWI_RHR (48) // Receive Holding Register\r
+#define TWI_THR (52) // Transmit Holding Register\r
+// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- \r
+#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition\r
+#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition\r
+#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled\r
+#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled\r
+#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset\r
+// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- \r
+#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size\r
+#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address\r
+#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address\r
+#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address\r
+#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address\r
+#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction\r
+#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address\r
+// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- \r
+#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider\r
+#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider\r
+#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider\r
+// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- \r
+#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed\r
+#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY\r
+#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY\r
+#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error\r
+#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error\r
+#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged\r
+// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- \r
+// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- \r
+// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR PWMC Channel Interface\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_PWMC_CH structure ***\r
+#define PWMC_CMR ( 0) // Channel Mode Register\r
+#define PWMC_CDTYR ( 4) // Channel Duty Cycle Register\r
+#define PWMC_CPRDR ( 8) // Channel Period Register\r
+#define PWMC_CCNTR (12) // Channel Counter Register\r
+#define PWMC_CUPDR (16) // Channel Update Register\r
+#define PWMC_Reserved (20) // Reserved\r
+// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- \r
+#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx\r
+#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH) \r
+#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH) \r
+#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH) \r
+#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment\r
+#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity\r
+#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period\r
+// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- \r
+#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle\r
+// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- \r
+#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period\r
+// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- \r
+#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter\r
+// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- \r
+#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_PWMC structure ***\r
+#define PWMC_MR ( 0) // PWMC Mode Register\r
+#define PWMC_ENA ( 4) // PWMC Enable Register\r
+#define PWMC_DIS ( 8) // PWMC Disable Register\r
+#define PWMC_SR (12) // PWMC Status Register\r
+#define PWMC_IER (16) // PWMC Interrupt Enable Register\r
+#define PWMC_IDR (20) // PWMC Interrupt Disable Register\r
+#define PWMC_IMR (24) // PWMC Interrupt Mask Register\r
+#define PWMC_ISR (28) // PWMC Interrupt Status Register\r
+#define PWMC_VR (252) // PWMC Version Register\r
+#define PWMC_CH (512) // PWMC Channel\r
+// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- \r
+#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor.\r
+#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A\r
+#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC) \r
+#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor.\r
+#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B\r
+#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC) \r
+// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- \r
+#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0\r
+#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1\r
+#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2\r
+#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3\r
+// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- \r
+// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- \r
+// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- \r
+// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- \r
+// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- \r
+// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR USB Device Interface\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_UDP structure ***\r
+#define UDP_NUM ( 0) // Frame Number Register\r
+#define UDP_GLBSTATE ( 4) // Global State Register\r
+#define UDP_FADDR ( 8) // Function Address Register\r
+#define UDP_IER (16) // Interrupt Enable Register\r
+#define UDP_IDR (20) // Interrupt Disable Register\r
+#define UDP_IMR (24) // Interrupt Mask Register\r
+#define UDP_ISR (28) // Interrupt Status Register\r
+#define UDP_ICR (32) // Interrupt Clear Register\r
+#define UDP_RSTEP (40) // Reset Endpoint Register\r
+#define UDP_CSR (48) // Endpoint Control and Status Register\r
+#define UDP_FDR (80) // Endpoint FIFO Data Register\r
+#define UDP_TXVC (116) // Transceiver Control Register\r
+// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- \r
+#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats\r
+#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error\r
+#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK\r
+// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- \r
+#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable\r
+#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured\r
+#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume\r
+#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host\r
+#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable\r
+// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- \r
+#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value\r
+#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable\r
+// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- \r
+#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt\r
+#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt\r
+#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt\r
+#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt\r
+#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt\r
+#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt\r
+#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt\r
+#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt\r
+#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt\r
+#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt\r
+#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt\r
+// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- \r
+// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- \r
+// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- \r
+#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt\r
+// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- \r
+// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- \r
+#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0\r
+#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1\r
+#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2\r
+#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3\r
+#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4\r
+#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5\r
+// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- \r
+#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR\r
+#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0\r
+#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)\r
+#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)\r
+#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready\r
+#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).\r
+#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).\r
+#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction\r
+#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type\r
+#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control\r
+#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT\r
+#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT\r
+#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT\r
+#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN\r
+#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN\r
+#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN\r
+#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle\r
+#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable\r
+#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO\r
+// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- \r
+#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP) \r
+#define AT91C_UDP_PUON (0x1 << 9) // (UDP) Pull-up ON\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_TC structure ***\r
+#define TC_CCR ( 0) // Channel Control Register\r
+#define TC_CMR ( 4) // Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define TC_CV (16) // Counter Value\r
+#define TC_RA (20) // Register A\r
+#define TC_RB (24) // Register B\r
+#define TC_RC (28) // Register C\r
+#define TC_SR (32) // Status Register\r
+#define TC_IER (36) // Interrupt Enable Register\r
+#define TC_IDR (40) // Interrupt Disable Register\r
+#define TC_IMR (44) // Interrupt Mask Register\r
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- \r
+#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command\r
+#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command\r
+#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command\r
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- \r
+#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection\r
+#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK\r
+#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK\r
+#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK\r
+#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK\r
+#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK\r
+#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0\r
+#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1\r
+#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2\r
+#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert\r
+#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection\r
+#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal\r
+#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock\r
+#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock\r
+#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock\r
+#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare\r
+#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading\r
+#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare\r
+#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading\r
+#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection\r
+#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None\r
+#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge\r
+#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge\r
+#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge\r
+#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection\r
+#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None\r
+#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge\r
+#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge\r
+#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge\r
+#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection\r
+#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input\r
+#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output\r
+#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output\r
+#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output\r
+#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection\r
+#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable\r
+#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection\r
+#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare\r
+#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare\r
+#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare\r
+#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare\r
+#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable\r
+#define AT91C_TC_WAVE (0x1 << 15) // (TC) \r
+#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA\r
+#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none\r
+#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set\r
+#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear\r
+#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle\r
+#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection\r
+#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None\r
+#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA\r
+#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA\r
+#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA\r
+#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA\r
+#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none\r
+#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set\r
+#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear\r
+#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle\r
+#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection\r
+#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None\r
+#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA\r
+#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA\r
+#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA\r
+#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA\r
+#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none\r
+#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set\r
+#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear\r
+#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle\r
+#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA\r
+#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none\r
+#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set\r
+#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear\r
+#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle\r
+#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB\r
+#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none\r
+#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set\r
+#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear\r
+#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle\r
+#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB\r
+#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none\r
+#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set\r
+#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear\r
+#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle\r
+#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB\r
+#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none\r
+#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set\r
+#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear\r
+#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle\r
+#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB\r
+#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none\r
+#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set\r
+#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear\r
+#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle\r
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- \r
+#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow\r
+#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun\r
+#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare\r
+#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare\r
+#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare\r
+#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading\r
+#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading\r
+#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger\r
+#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling\r
+#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror\r
+#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror\r
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- \r
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- \r
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Timer Counter Interface\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_TCB structure ***\r
+#define TCB_TC0 ( 0) // TC Channel 0\r
+#define TCB_TC1 (64) // TC Channel 1\r
+#define TCB_TC2 (128) // TC Channel 2\r
+#define TCB_BCR (192) // TC Block Control Register\r
+#define TCB_BMR (196) // TC Block Mode Register\r
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- \r
+#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command\r
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- \r
+#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection\r
+#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0\r
+#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0\r
+#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0\r
+#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0\r
+#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection\r
+#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1\r
+#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1\r
+#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1\r
+#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1\r
+#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection\r
+#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2\r
+#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2\r
+#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2\r
+#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_CAN_MB structure ***\r
+#define CAN_MB_MMR ( 0) // MailBox Mode Register\r
+#define CAN_MB_MAM ( 4) // MailBox Acceptance Mask Register\r
+#define CAN_MB_MID ( 8) // MailBox ID Register\r
+#define CAN_MB_MFID (12) // MailBox Family ID Register\r
+#define CAN_MB_MSR (16) // MailBox Status Register\r
+#define CAN_MB_MDL (20) // MailBox Data Low Register\r
+#define CAN_MB_MDH (24) // MailBox Data High Register\r
+#define CAN_MB_MCR (28) // MailBox Control Register\r
+// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- \r
+#define AT91C_CAN_MTIMEMARK (0xFFFF << 0) // (CAN_MB) Mailbox Timemark\r
+#define AT91C_CAN_PRIOR (0xF << 16) // (CAN_MB) Mailbox Priority\r
+#define AT91C_CAN_MOT (0x7 << 24) // (CAN_MB) Mailbox Object Type\r
+#define AT91C_CAN_MOT_DIS (0x0 << 24) // (CAN_MB) \r
+#define AT91C_CAN_MOT_RX (0x1 << 24) // (CAN_MB) \r
+#define AT91C_CAN_MOT_RXOVERWRITE (0x2 << 24) // (CAN_MB) \r
+#define AT91C_CAN_MOT_TX (0x3 << 24) // (CAN_MB) \r
+#define AT91C_CAN_MOT_CONSUMER (0x4 << 24) // (CAN_MB) \r
+#define AT91C_CAN_MOT_PRODUCER (0x5 << 24) // (CAN_MB) \r
+// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- \r
+#define AT91C_CAN_MIDvB (0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode\r
+#define AT91C_CAN_MIDvA (0x7FF << 18) // (CAN_MB) Identifier for standard frame mode\r
+#define AT91C_CAN_MIDE (0x1 << 29) // (CAN_MB) Identifier Version\r
+// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- \r
+// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- \r
+// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- \r
+#define AT91C_CAN_MTIMESTAMP (0xFFFF << 0) // (CAN_MB) Timer Value\r
+#define AT91C_CAN_MDLC (0xF << 16) // (CAN_MB) Mailbox Data Length Code\r
+#define AT91C_CAN_MRTR (0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request\r
+#define AT91C_CAN_MABT (0x1 << 22) // (CAN_MB) Mailbox Message Abort\r
+#define AT91C_CAN_MRDY (0x1 << 23) // (CAN_MB) Mailbox Ready\r
+#define AT91C_CAN_MMI (0x1 << 24) // (CAN_MB) Mailbox Message Ignored\r
+// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- \r
+// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- \r
+// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- \r
+#define AT91C_CAN_MACR (0x1 << 22) // (CAN_MB) Abort Request for Mailbox\r
+#define AT91C_CAN_MTCR (0x1 << 23) // (CAN_MB) Mailbox Transfer Command\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Control Area Network Interface\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_CAN structure ***\r
+#define CAN_MR ( 0) // Mode Register\r
+#define CAN_IER ( 4) // Interrupt Enable Register\r
+#define CAN_IDR ( 8) // Interrupt Disable Register\r
+#define CAN_IMR (12) // Interrupt Mask Register\r
+#define CAN_SR (16) // Status Register\r
+#define CAN_BR (20) // Baudrate Register\r
+#define CAN_TIM (24) // Timer Register\r
+#define CAN_TIMESTP (28) // Time Stamp Register\r
+#define CAN_ECR (32) // Error Counter Register\r
+#define CAN_TCR (36) // Transfer Command Register\r
+#define CAN_ACR (40) // Abort Command Register\r
+#define CAN_VR (252) // Version Register\r
+#define CAN_MB0 (512) // CAN Mailbox 0\r
+#define CAN_MB1 (544) // CAN Mailbox 1\r
+#define CAN_MB2 (576) // CAN Mailbox 2\r
+#define CAN_MB3 (608) // CAN Mailbox 3\r
+#define CAN_MB4 (640) // CAN Mailbox 4\r
+#define CAN_MB5 (672) // CAN Mailbox 5\r
+#define CAN_MB6 (704) // CAN Mailbox 6\r
+#define CAN_MB7 (736) // CAN Mailbox 7\r
+#define CAN_MB8 (768) // CAN Mailbox 8\r
+#define CAN_MB9 (800) // CAN Mailbox 9\r
+#define CAN_MB10 (832) // CAN Mailbox 10\r
+#define CAN_MB11 (864) // CAN Mailbox 11\r
+#define CAN_MB12 (896) // CAN Mailbox 12\r
+#define CAN_MB13 (928) // CAN Mailbox 13\r
+#define CAN_MB14 (960) // CAN Mailbox 14\r
+#define CAN_MB15 (992) // CAN Mailbox 15\r
+// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- \r
+#define AT91C_CAN_CANEN (0x1 << 0) // (CAN) CAN Controller Enable\r
+#define AT91C_CAN_LPM (0x1 << 1) // (CAN) Disable/Enable Low Power Mode\r
+#define AT91C_CAN_ABM (0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode\r
+#define AT91C_CAN_OVL (0x1 << 3) // (CAN) Disable/Enable Overload Frame\r
+#define AT91C_CAN_TEOF (0x1 << 4) // (CAN) Time Stamp messages at each end of Frame\r
+#define AT91C_CAN_TTM (0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode\r
+#define AT91C_CAN_TIMFRZ (0x1 << 6) // (CAN) Enable Timer Freeze\r
+#define AT91C_CAN_DRPT (0x1 << 7) // (CAN) Disable Repeat\r
+// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- \r
+#define AT91C_CAN_MB0 (0x1 << 0) // (CAN) Mailbox 0 Flag\r
+#define AT91C_CAN_MB1 (0x1 << 1) // (CAN) Mailbox 1 Flag\r
+#define AT91C_CAN_MB2 (0x1 << 2) // (CAN) Mailbox 2 Flag\r
+#define AT91C_CAN_MB3 (0x1 << 3) // (CAN) Mailbox 3 Flag\r
+#define AT91C_CAN_MB4 (0x1 << 4) // (CAN) Mailbox 4 Flag\r
+#define AT91C_CAN_MB5 (0x1 << 5) // (CAN) Mailbox 5 Flag\r
+#define AT91C_CAN_MB6 (0x1 << 6) // (CAN) Mailbox 6 Flag\r
+#define AT91C_CAN_MB7 (0x1 << 7) // (CAN) Mailbox 7 Flag\r
+#define AT91C_CAN_MB8 (0x1 << 8) // (CAN) Mailbox 8 Flag\r
+#define AT91C_CAN_MB9 (0x1 << 9) // (CAN) Mailbox 9 Flag\r
+#define AT91C_CAN_MB10 (0x1 << 10) // (CAN) Mailbox 10 Flag\r
+#define AT91C_CAN_MB11 (0x1 << 11) // (CAN) Mailbox 11 Flag\r
+#define AT91C_CAN_MB12 (0x1 << 12) // (CAN) Mailbox 12 Flag\r
+#define AT91C_CAN_MB13 (0x1 << 13) // (CAN) Mailbox 13 Flag\r
+#define AT91C_CAN_MB14 (0x1 << 14) // (CAN) Mailbox 14 Flag\r
+#define AT91C_CAN_MB15 (0x1 << 15) // (CAN) Mailbox 15 Flag\r
+#define AT91C_CAN_ERRA (0x1 << 16) // (CAN) Error Active Mode Flag\r
+#define AT91C_CAN_WARN (0x1 << 17) // (CAN) Warning Limit Flag\r
+#define AT91C_CAN_ERRP (0x1 << 18) // (CAN) Error Passive Mode Flag\r
+#define AT91C_CAN_BOFF (0x1 << 19) // (CAN) Bus Off Mode Flag\r
+#define AT91C_CAN_SLEEP (0x1 << 20) // (CAN) Sleep Flag\r
+#define AT91C_CAN_WAKEUP (0x1 << 21) // (CAN) Wakeup Flag\r
+#define AT91C_CAN_TOVF (0x1 << 22) // (CAN) Timer Overflow Flag\r
+#define AT91C_CAN_TSTP (0x1 << 23) // (CAN) Timestamp Flag\r
+#define AT91C_CAN_CERR (0x1 << 24) // (CAN) CRC Error\r
+#define AT91C_CAN_SERR (0x1 << 25) // (CAN) Stuffing Error\r
+#define AT91C_CAN_AERR (0x1 << 26) // (CAN) Acknowledgment Error\r
+#define AT91C_CAN_FERR (0x1 << 27) // (CAN) Form Error\r
+#define AT91C_CAN_BERR (0x1 << 28) // (CAN) Bit Error\r
+// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- \r
+// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- \r
+// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- \r
+#define AT91C_CAN_RBSY (0x1 << 29) // (CAN) Receiver Busy\r
+#define AT91C_CAN_TBSY (0x1 << 30) // (CAN) Transmitter Busy\r
+#define AT91C_CAN_OVLY (0x1 << 31) // (CAN) Overload Busy\r
+// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- \r
+#define AT91C_CAN_PHASE2 (0x7 << 0) // (CAN) Phase 2 segment\r
+#define AT91C_CAN_PHASE1 (0x7 << 4) // (CAN) Phase 1 segment\r
+#define AT91C_CAN_PROPAG (0x7 << 8) // (CAN) Programmation time segment\r
+#define AT91C_CAN_SYNC (0x3 << 12) // (CAN) Re-synchronization jump width segment\r
+#define AT91C_CAN_BRP (0x7F << 16) // (CAN) Baudrate Prescaler\r
+#define AT91C_CAN_SMP (0x1 << 24) // (CAN) Sampling mode\r
+// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- \r
+#define AT91C_CAN_TIMER (0xFFFF << 0) // (CAN) Timer field\r
+// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- \r
+// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- \r
+#define AT91C_CAN_REC (0xFF << 0) // (CAN) Receive Error Counter\r
+#define AT91C_CAN_TEC (0xFF << 16) // (CAN) Transmit Error Counter\r
+// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- \r
+#define AT91C_CAN_TIMRST (0x1 << 31) // (CAN) Timer Reset Field\r
+// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_EMAC structure ***\r
+#define EMAC_NCR ( 0) // Network Control Register\r
+#define EMAC_NCFGR ( 4) // Network Configuration Register\r
+#define EMAC_NSR ( 8) // Network Status Register\r
+#define EMAC_TSR (20) // Transmit Status Register\r
+#define EMAC_RBQP (24) // Receive Buffer Queue Pointer\r
+#define EMAC_TBQP (28) // Transmit Buffer Queue Pointer\r
+#define EMAC_RSR (32) // Receive Status Register\r
+#define EMAC_ISR (36) // Interrupt Status Register\r
+#define EMAC_IER (40) // Interrupt Enable Register\r
+#define EMAC_IDR (44) // Interrupt Disable Register\r
+#define EMAC_IMR (48) // Interrupt Mask Register\r
+#define EMAC_MAN (52) // PHY Maintenance Register\r
+#define EMAC_PTR (56) // Pause Time Register\r
+#define EMAC_PFR (60) // Pause Frames received Register\r
+#define EMAC_FTO (64) // Frames Transmitted OK Register\r
+#define EMAC_SCF (68) // Single Collision Frame Register\r
+#define EMAC_MCF (72) // Multiple Collision Frame Register\r
+#define EMAC_FRO (76) // Frames Received OK Register\r
+#define EMAC_FCSE (80) // Frame Check Sequence Error Register\r
+#define EMAC_ALE (84) // Alignment Error Register\r
+#define EMAC_DTF (88) // Deferred Transmission Frame Register\r
+#define EMAC_LCOL (92) // Late Collision Register\r
+#define EMAC_ECOL (96) // Excessive Collision Register\r
+#define EMAC_TUND (100) // Transmit Underrun Error Register\r
+#define EMAC_CSE (104) // Carrier Sense Error Register\r
+#define EMAC_RRE (108) // Receive Ressource Error Register\r
+#define EMAC_ROV (112) // Receive Overrun Errors Register\r
+#define EMAC_RSE (116) // Receive Symbol Errors Register\r
+#define EMAC_ELE (120) // Excessive Length Errors Register\r
+#define EMAC_RJA (124) // Receive Jabbers Register\r
+#define EMAC_USF (128) // Undersize Frames Register\r
+#define EMAC_STE (132) // SQE Test Error Register\r
+#define EMAC_RLE (136) // Receive Length Field Mismatch Register\r
+#define EMAC_TPF (140) // Transmitted Pause Frames Register\r
+#define EMAC_HRB (144) // Hash Address Bottom[31:0]\r
+#define EMAC_HRT (148) // Hash Address Top[63:32]\r
+#define EMAC_SA1L (152) // Specific Address 1 Bottom, First 4 bytes\r
+#define EMAC_SA1H (156) // Specific Address 1 Top, Last 2 bytes\r
+#define EMAC_SA2L (160) // Specific Address 2 Bottom, First 4 bytes\r
+#define EMAC_SA2H (164) // Specific Address 2 Top, Last 2 bytes\r
+#define EMAC_SA3L (168) // Specific Address 3 Bottom, First 4 bytes\r
+#define EMAC_SA3H (172) // Specific Address 3 Top, Last 2 bytes\r
+#define EMAC_SA4L (176) // Specific Address 4 Bottom, First 4 bytes\r
+#define EMAC_SA4H (180) // Specific Address 4 Top, Last 2 bytes\r
+#define EMAC_TID (184) // Type ID Checking Register\r
+#define EMAC_TPQ (188) // Transmit Pause Quantum Register\r
+#define EMAC_USRIO (192) // USER Input/Output Register\r
+#define EMAC_WOL (196) // Wake On LAN Register\r
+#define EMAC_REV (252) // Revision Register\r
+// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- \r
+#define AT91C_EMAC_LB (0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.\r
+#define AT91C_EMAC_LLB (0x1 << 1) // (EMAC) Loopback local. \r
+#define AT91C_EMAC_RE (0x1 << 2) // (EMAC) Receive enable. \r
+#define AT91C_EMAC_TE (0x1 << 3) // (EMAC) Transmit enable. \r
+#define AT91C_EMAC_MPE (0x1 << 4) // (EMAC) Management port enable. \r
+#define AT91C_EMAC_CLRSTAT (0x1 << 5) // (EMAC) Clear statistics registers. \r
+#define AT91C_EMAC_INCSTAT (0x1 << 6) // (EMAC) Increment statistics registers. \r
+#define AT91C_EMAC_WESTAT (0x1 << 7) // (EMAC) Write enable for statistics registers. \r
+#define AT91C_EMAC_BP (0x1 << 8) // (EMAC) Back pressure. \r
+#define AT91C_EMAC_TSTART (0x1 << 9) // (EMAC) Start Transmission. \r
+#define AT91C_EMAC_THALT (0x1 << 10) // (EMAC) Transmission Halt. \r
+#define AT91C_EMAC_TPFR (0x1 << 11) // (EMAC) Transmit pause frame \r
+#define AT91C_EMAC_TZQ (0x1 << 12) // (EMAC) Transmit zero quantum pause frame\r
+// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- \r
+#define AT91C_EMAC_SPD (0x1 << 0) // (EMAC) Speed. \r
+#define AT91C_EMAC_FD (0x1 << 1) // (EMAC) Full duplex. \r
+#define AT91C_EMAC_JFRAME (0x1 << 3) // (EMAC) Jumbo Frames. \r
+#define AT91C_EMAC_CAF (0x1 << 4) // (EMAC) Copy all frames. \r
+#define AT91C_EMAC_NBC (0x1 << 5) // (EMAC) No broadcast. \r
+#define AT91C_EMAC_MTI (0x1 << 6) // (EMAC) Multicast hash event enable\r
+#define AT91C_EMAC_UNI (0x1 << 7) // (EMAC) Unicast hash enable. \r
+#define AT91C_EMAC_BIG (0x1 << 8) // (EMAC) Receive 1522 bytes. \r
+#define AT91C_EMAC_EAE (0x1 << 9) // (EMAC) External address match enable. \r
+#define AT91C_EMAC_CLK (0x3 << 10) // (EMAC) \r
+#define AT91C_EMAC_CLK_HCLK_8 (0x0 << 10) // (EMAC) HCLK divided by 8\r
+#define AT91C_EMAC_CLK_HCLK_16 (0x1 << 10) // (EMAC) HCLK divided by 16\r
+#define AT91C_EMAC_CLK_HCLK_32 (0x2 << 10) // (EMAC) HCLK divided by 32\r
+#define AT91C_EMAC_CLK_HCLK_64 (0x3 << 10) // (EMAC) HCLK divided by 64\r
+#define AT91C_EMAC_RTY (0x1 << 12) // (EMAC) \r
+#define AT91C_EMAC_PAE (0x1 << 13) // (EMAC) \r
+#define AT91C_EMAC_RBOF (0x3 << 14) // (EMAC) \r
+#define AT91C_EMAC_RBOF_OFFSET_0 (0x0 << 14) // (EMAC) no offset from start of receive buffer\r
+#define AT91C_EMAC_RBOF_OFFSET_1 (0x1 << 14) // (EMAC) one byte offset from start of receive buffer\r
+#define AT91C_EMAC_RBOF_OFFSET_2 (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer\r
+#define AT91C_EMAC_RBOF_OFFSET_3 (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer\r
+#define AT91C_EMAC_RLCE (0x1 << 16) // (EMAC) Receive Length field Checking Enable\r
+#define AT91C_EMAC_DRFCS (0x1 << 17) // (EMAC) Discard Receive FCS\r
+#define AT91C_EMAC_EFRHD (0x1 << 18) // (EMAC) \r
+#define AT91C_EMAC_IRXFCS (0x1 << 19) // (EMAC) Ignore RX FCS\r
+// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- \r
+#define AT91C_EMAC_LINKR (0x1 << 0) // (EMAC) \r
+#define AT91C_EMAC_MDIO (0x1 << 1) // (EMAC) \r
+#define AT91C_EMAC_IDLE (0x1 << 2) // (EMAC) \r
+// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- \r
+#define AT91C_EMAC_UBR (0x1 << 0) // (EMAC) \r
+#define AT91C_EMAC_COL (0x1 << 1) // (EMAC) \r
+#define AT91C_EMAC_RLES (0x1 << 2) // (EMAC) \r
+#define AT91C_EMAC_TGO (0x1 << 3) // (EMAC) Transmit Go\r
+#define AT91C_EMAC_BEX (0x1 << 4) // (EMAC) Buffers exhausted mid frame\r
+#define AT91C_EMAC_COMP (0x1 << 5) // (EMAC) \r
+#define AT91C_EMAC_UND (0x1 << 6) // (EMAC) \r
+// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- \r
+#define AT91C_EMAC_BNA (0x1 << 0) // (EMAC) \r
+#define AT91C_EMAC_REC (0x1 << 1) // (EMAC) \r
+#define AT91C_EMAC_OVR (0x1 << 2) // (EMAC) \r
+// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- \r
+#define AT91C_EMAC_MFD (0x1 << 0) // (EMAC) \r
+#define AT91C_EMAC_RCOMP (0x1 << 1) // (EMAC) \r
+#define AT91C_EMAC_RXUBR (0x1 << 2) // (EMAC) \r
+#define AT91C_EMAC_TXUBR (0x1 << 3) // (EMAC) \r
+#define AT91C_EMAC_TUNDR (0x1 << 4) // (EMAC) \r
+#define AT91C_EMAC_RLEX (0x1 << 5) // (EMAC) \r
+#define AT91C_EMAC_TXERR (0x1 << 6) // (EMAC) \r
+#define AT91C_EMAC_TCOMP (0x1 << 7) // (EMAC) \r
+#define AT91C_EMAC_LINK (0x1 << 9) // (EMAC) \r
+#define AT91C_EMAC_ROVR (0x1 << 10) // (EMAC) \r
+#define AT91C_EMAC_HRESP (0x1 << 11) // (EMAC) \r
+#define AT91C_EMAC_PFRE (0x1 << 12) // (EMAC) \r
+#define AT91C_EMAC_PTZ (0x1 << 13) // (EMAC) \r
+// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- \r
+// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- \r
+// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- \r
+// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- \r
+#define AT91C_EMAC_DATA (0xFFFF << 0) // (EMAC) \r
+#define AT91C_EMAC_CODE (0x3 << 16) // (EMAC) \r
+#define AT91C_EMAC_REGA (0x1F << 18) // (EMAC) \r
+#define AT91C_EMAC_PHYA (0x1F << 23) // (EMAC) \r
+#define AT91C_EMAC_RW (0x3 << 28) // (EMAC) \r
+#define AT91C_EMAC_SOF (0x3 << 30) // (EMAC) \r
+// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- \r
+#define AT91C_EMAC_RMII (0x1 << 0) // (EMAC) Reduce MII\r
+// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- \r
+#define AT91C_EMAC_IP (0xFFFF << 0) // (EMAC) ARP request IP address\r
+#define AT91C_EMAC_MAG (0x1 << 16) // (EMAC) Magic packet event enable\r
+#define AT91C_EMAC_ARP (0x1 << 17) // (EMAC) ARP request event enable\r
+#define AT91C_EMAC_SA1 (0x1 << 18) // (EMAC) Specific address register 1 event enable\r
+// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- \r
+#define AT91C_EMAC_REVREF (0xFFFF << 0) // (EMAC) \r
+#define AT91C_EMAC_PARTREF (0xFFFF << 16) // (EMAC) \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Analog to Digital Convertor\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_ADC structure ***\r
+#define ADC_CR ( 0) // ADC Control Register\r
+#define ADC_MR ( 4) // ADC Mode Register\r
+#define ADC_CHER (16) // ADC Channel Enable Register\r
+#define ADC_CHDR (20) // ADC Channel Disable Register\r
+#define ADC_CHSR (24) // ADC Channel Status Register\r
+#define ADC_SR (28) // ADC Status Register\r
+#define ADC_LCDR (32) // ADC Last Converted Data Register\r
+#define ADC_IER (36) // ADC Interrupt Enable Register\r
+#define ADC_IDR (40) // ADC Interrupt Disable Register\r
+#define ADC_IMR (44) // ADC Interrupt Mask Register\r
+#define ADC_CDR0 (48) // ADC Channel Data Register 0\r
+#define ADC_CDR1 (52) // ADC Channel Data Register 1\r
+#define ADC_CDR2 (56) // ADC Channel Data Register 2\r
+#define ADC_CDR3 (60) // ADC Channel Data Register 3\r
+#define ADC_CDR4 (64) // ADC Channel Data Register 4\r
+#define ADC_CDR5 (68) // ADC Channel Data Register 5\r
+#define ADC_CDR6 (72) // ADC Channel Data Register 6\r
+#define ADC_CDR7 (76) // ADC Channel Data Register 7\r
+#define ADC_RPR (256) // Receive Pointer Register\r
+#define ADC_RCR (260) // Receive Counter Register\r
+#define ADC_TPR (264) // Transmit Pointer Register\r
+#define ADC_TCR (268) // Transmit Counter Register\r
+#define ADC_RNPR (272) // Receive Next Pointer Register\r
+#define ADC_RNCR (276) // Receive Next Counter Register\r
+#define ADC_TNPR (280) // Transmit Next Pointer Register\r
+#define ADC_TNCR (284) // Transmit Next Counter Register\r
+#define ADC_PTCR (288) // PDC Transfer Control Register\r
+#define ADC_PTSR (292) // PDC Transfer Status Register\r
+// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- \r
+#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset\r
+#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion\r
+// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- \r
+#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable\r
+#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software\r
+#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.\r
+#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection\r
+#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0\r
+#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1\r
+#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2\r
+#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3\r
+#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4\r
+#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5\r
+#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger\r
+#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution.\r
+#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution\r
+#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution\r
+#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode\r
+#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode\r
+#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode\r
+#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection\r
+#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time\r
+#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time\r
+// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- \r
+#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0\r
+#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1\r
+#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2\r
+#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3\r
+#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4\r
+#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5\r
+#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6\r
+#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7\r
+// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- \r
+// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- \r
+// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- \r
+#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion\r
+#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error\r
+#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready\r
+#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun\r
+#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer\r
+#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt\r
+// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- \r
+#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted\r
+// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- \r
+// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- \r
+// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- \r
+// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- \r
+#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data\r
+// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- \r
+// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- \r
+// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- \r
+// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- \r
+// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- \r
+// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- \r
+// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Advanced Encryption Standard\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_AES structure ***\r
+#define AES_CR ( 0) // Control Register\r
+#define AES_MR ( 4) // Mode Register\r
+#define AES_IER (16) // Interrupt Enable Register\r
+#define AES_IDR (20) // Interrupt Disable Register\r
+#define AES_IMR (24) // Interrupt Mask Register\r
+#define AES_ISR (28) // Interrupt Status Register\r
+#define AES_KEYWxR (32) // Key Word x Register\r
+#define AES_IDATAxR (64) // Input Data x Register\r
+#define AES_ODATAxR (80) // Output Data x Register\r
+#define AES_IVxR (96) // Initialization Vector x Register\r
+#define AES_VR (252) // AES Version Register\r
+#define AES_RPR (256) // Receive Pointer Register\r
+#define AES_RCR (260) // Receive Counter Register\r
+#define AES_TPR (264) // Transmit Pointer Register\r
+#define AES_TCR (268) // Transmit Counter Register\r
+#define AES_RNPR (272) // Receive Next Pointer Register\r
+#define AES_RNCR (276) // Receive Next Counter Register\r
+#define AES_TNPR (280) // Transmit Next Pointer Register\r
+#define AES_TNCR (284) // Transmit Next Counter Register\r
+#define AES_PTCR (288) // PDC Transfer Control Register\r
+#define AES_PTSR (292) // PDC Transfer Status Register\r
+// -------- AES_CR : (AES Offset: 0x0) Control Register -------- \r
+#define AT91C_AES_START (0x1 << 0) // (AES) Starts Processing\r
+#define AT91C_AES_SWRST (0x1 << 8) // (AES) Software Reset\r
+#define AT91C_AES_LOADSEED (0x1 << 16) // (AES) Random Number Generator Seed Loading\r
+// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- \r
+#define AT91C_AES_CIPHER (0x1 << 0) // (AES) Processing Mode\r
+#define AT91C_AES_PROCDLY (0xF << 4) // (AES) Processing Delay\r
+#define AT91C_AES_SMOD (0x3 << 8) // (AES) Start Mode\r
+#define AT91C_AES_SMOD_MANUAL (0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.\r
+#define AT91C_AES_SMOD_AUTO (0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).\r
+#define AT91C_AES_SMOD_PDC (0x2 << 8) // (AES) PDC Mode (cf datasheet).\r
+#define AT91C_AES_OPMOD (0x7 << 12) // (AES) Operation Mode\r
+#define AT91C_AES_OPMOD_ECB (0x0 << 12) // (AES) ECB Electronic CodeBook mode.\r
+#define AT91C_AES_OPMOD_CBC (0x1 << 12) // (AES) CBC Cipher Block Chaining mode.\r
+#define AT91C_AES_OPMOD_OFB (0x2 << 12) // (AES) OFB Output Feedback mode.\r
+#define AT91C_AES_OPMOD_CFB (0x3 << 12) // (AES) CFB Cipher Feedback mode.\r
+#define AT91C_AES_OPMOD_CTR (0x4 << 12) // (AES) CTR Counter mode.\r
+#define AT91C_AES_LOD (0x1 << 15) // (AES) Last Output Data Mode\r
+#define AT91C_AES_CFBS (0x7 << 16) // (AES) Cipher Feedback Data Size\r
+#define AT91C_AES_CFBS_128_BIT (0x0 << 16) // (AES) 128-bit.\r
+#define AT91C_AES_CFBS_64_BIT (0x1 << 16) // (AES) 64-bit.\r
+#define AT91C_AES_CFBS_32_BIT (0x2 << 16) // (AES) 32-bit.\r
+#define AT91C_AES_CFBS_16_BIT (0x3 << 16) // (AES) 16-bit.\r
+#define AT91C_AES_CFBS_8_BIT (0x4 << 16) // (AES) 8-bit.\r
+#define AT91C_AES_CKEY (0xF << 20) // (AES) Countermeasure Key\r
+#define AT91C_AES_CTYPE (0x1F << 24) // (AES) Countermeasure Type\r
+#define AT91C_AES_CTYPE_TYPE1_EN (0x1 << 24) // (AES) Countermeasure type 1 is enabled.\r
+#define AT91C_AES_CTYPE_TYPE2_EN (0x2 << 24) // (AES) Countermeasure type 2 is enabled.\r
+#define AT91C_AES_CTYPE_TYPE3_EN (0x4 << 24) // (AES) Countermeasure type 3 is enabled.\r
+#define AT91C_AES_CTYPE_TYPE4_EN (0x8 << 24) // (AES) Countermeasure type 4 is enabled.\r
+#define AT91C_AES_CTYPE_TYPE5_EN (0x10 << 24) // (AES) Countermeasure type 5 is enabled.\r
+// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- \r
+#define AT91C_AES_DATRDY (0x1 << 0) // (AES) DATRDY\r
+#define AT91C_AES_ENDRX (0x1 << 1) // (AES) PDC Read Buffer End\r
+#define AT91C_AES_ENDTX (0x1 << 2) // (AES) PDC Write Buffer End\r
+#define AT91C_AES_RXBUFF (0x1 << 3) // (AES) PDC Read Buffer Full\r
+#define AT91C_AES_TXBUFE (0x1 << 4) // (AES) PDC Write Buffer Empty\r
+#define AT91C_AES_URAD (0x1 << 8) // (AES) Unspecified Register Access Detection\r
+// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- \r
+// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- \r
+// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- \r
+#define AT91C_AES_URAT (0x7 << 12) // (AES) Unspecified Register Access Type Status\r
+#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC (0x0 << 12) // (AES) Input data register written during the data processing in PDC mode.\r
+#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC (0x1 << 12) // (AES) Output data register read during the data processing.\r
+#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC (0x2 << 12) // (AES) Mode register written during the data processing.\r
+#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY (0x3 << 12) // (AES) Output data register read during the sub-keys generation.\r
+#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY (0x4 << 12) // (AES) Mode register written during the sub-keys generation.\r
+#define AT91C_AES_URAT_WO_REG_READ (0x5 << 12) // (AES) Write-only register read access.\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_TDES structure ***\r
+#define TDES_CR ( 0) // Control Register\r
+#define TDES_MR ( 4) // Mode Register\r
+#define TDES_IER (16) // Interrupt Enable Register\r
+#define TDES_IDR (20) // Interrupt Disable Register\r
+#define TDES_IMR (24) // Interrupt Mask Register\r
+#define TDES_ISR (28) // Interrupt Status Register\r
+#define TDES_KEY1WxR (32) // Key 1 Word x Register\r
+#define TDES_KEY2WxR (40) // Key 2 Word x Register\r
+#define TDES_KEY3WxR (48) // Key 3 Word x Register\r
+#define TDES_IDATAxR (64) // Input Data x Register\r
+#define TDES_ODATAxR (80) // Output Data x Register\r
+#define TDES_IVxR (96) // Initialization Vector x Register\r
+#define TDES_VR (252) // TDES Version Register\r
+#define TDES_RPR (256) // Receive Pointer Register\r
+#define TDES_RCR (260) // Receive Counter Register\r
+#define TDES_TPR (264) // Transmit Pointer Register\r
+#define TDES_TCR (268) // Transmit Counter Register\r
+#define TDES_RNPR (272) // Receive Next Pointer Register\r
+#define TDES_RNCR (276) // Receive Next Counter Register\r
+#define TDES_TNPR (280) // Transmit Next Pointer Register\r
+#define TDES_TNCR (284) // Transmit Next Counter Register\r
+#define TDES_PTCR (288) // PDC Transfer Control Register\r
+#define TDES_PTSR (292) // PDC Transfer Status Register\r
+// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- \r
+#define AT91C_TDES_START (0x1 << 0) // (TDES) Starts Processing\r
+#define AT91C_TDES_SWRST (0x1 << 8) // (TDES) Software Reset\r
+// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- \r
+#define AT91C_TDES_CIPHER (0x1 << 0) // (TDES) Processing Mode\r
+#define AT91C_TDES_TDESMOD (0x1 << 1) // (TDES) Single or Triple DES Mode\r
+#define AT91C_TDES_KEYMOD (0x1 << 4) // (TDES) Key Mode\r
+#define AT91C_TDES_SMOD (0x3 << 8) // (TDES) Start Mode\r
+#define AT91C_TDES_SMOD_MANUAL (0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.\r
+#define AT91C_TDES_SMOD_AUTO (0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).\r
+#define AT91C_TDES_SMOD_PDC (0x2 << 8) // (TDES) PDC Mode (cf datasheet).\r
+#define AT91C_TDES_OPMOD (0x3 << 12) // (TDES) Operation Mode\r
+#define AT91C_TDES_OPMOD_ECB (0x0 << 12) // (TDES) ECB Electronic CodeBook mode.\r
+#define AT91C_TDES_OPMOD_CBC (0x1 << 12) // (TDES) CBC Cipher Block Chaining mode.\r
+#define AT91C_TDES_OPMOD_OFB (0x2 << 12) // (TDES) OFB Output Feedback mode.\r
+#define AT91C_TDES_OPMOD_CFB (0x3 << 12) // (TDES) CFB Cipher Feedback mode.\r
+#define AT91C_TDES_LOD (0x1 << 15) // (TDES) Last Output Data Mode\r
+#define AT91C_TDES_CFBS (0x3 << 16) // (TDES) Cipher Feedback Data Size\r
+#define AT91C_TDES_CFBS_64_BIT (0x0 << 16) // (TDES) 64-bit.\r
+#define AT91C_TDES_CFBS_32_BIT (0x1 << 16) // (TDES) 32-bit.\r
+#define AT91C_TDES_CFBS_16_BIT (0x2 << 16) // (TDES) 16-bit.\r
+#define AT91C_TDES_CFBS_8_BIT (0x3 << 16) // (TDES) 8-bit.\r
+// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- \r
+#define AT91C_TDES_DATRDY (0x1 << 0) // (TDES) DATRDY\r
+#define AT91C_TDES_ENDRX (0x1 << 1) // (TDES) PDC Read Buffer End\r
+#define AT91C_TDES_ENDTX (0x1 << 2) // (TDES) PDC Write Buffer End\r
+#define AT91C_TDES_RXBUFF (0x1 << 3) // (TDES) PDC Read Buffer Full\r
+#define AT91C_TDES_TXBUFE (0x1 << 4) // (TDES) PDC Write Buffer Empty\r
+#define AT91C_TDES_URAD (0x1 << 8) // (TDES) Unspecified Register Access Detection\r
+// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- \r
+// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- \r
+// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- \r
+#define AT91C_TDES_URAT (0x3 << 12) // (TDES) Unspecified Register Access Type Status\r
+#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC (0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode.\r
+#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC (0x1 << 12) // (TDES) Output data register read during the data processing.\r
+#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC (0x2 << 12) // (TDES) Mode register written during the data processing.\r
+#define AT91C_TDES_URAT_WO_REG_READ (0x3 << 12) // (TDES) Write-only register read access.\r
+\r
+// *****************************************************************************\r
+// REGISTER ADDRESS DEFINITION FOR AT91SAM7X128\r
+// *****************************************************************************\r
+// ========== Register definition for SYS peripheral ========== \r
+// ========== Register definition for AIC peripheral ========== \r
+#define AT91C_AIC_IVR (0xFFFFF100) // (AIC) IRQ Vector Register\r
+#define AT91C_AIC_SMR (0xFFFFF000) // (AIC) Source Mode Register\r
+#define AT91C_AIC_FVR (0xFFFFF104) // (AIC) FIQ Vector Register\r
+#define AT91C_AIC_DCR (0xFFFFF138) // (AIC) Debug Control Register (Protect)\r
+#define AT91C_AIC_EOICR (0xFFFFF130) // (AIC) End of Interrupt Command Register\r
+#define AT91C_AIC_SVR (0xFFFFF080) // (AIC) Source Vector Register\r
+#define AT91C_AIC_FFSR (0xFFFFF148) // (AIC) Fast Forcing Status Register\r
+#define AT91C_AIC_ICCR (0xFFFFF128) // (AIC) Interrupt Clear Command Register\r
+#define AT91C_AIC_ISR (0xFFFFF108) // (AIC) Interrupt Status Register\r
+#define AT91C_AIC_IMR (0xFFFFF110) // (AIC) Interrupt Mask Register\r
+#define AT91C_AIC_IPR (0xFFFFF10C) // (AIC) Interrupt Pending Register\r
+#define AT91C_AIC_FFER (0xFFFFF140) // (AIC) Fast Forcing Enable Register\r
+#define AT91C_AIC_IECR (0xFFFFF120) // (AIC) Interrupt Enable Command Register\r
+#define AT91C_AIC_ISCR (0xFFFFF12C) // (AIC) Interrupt Set Command Register\r
+#define AT91C_AIC_FFDR (0xFFFFF144) // (AIC) Fast Forcing Disable Register\r
+#define AT91C_AIC_CISR (0xFFFFF114) // (AIC) Core Interrupt Status Register\r
+#define AT91C_AIC_IDCR (0xFFFFF124) // (AIC) Interrupt Disable Command Register\r
+#define AT91C_AIC_SPU (0xFFFFF134) // (AIC) Spurious Vector Register\r
+// ========== Register definition for PDC_DBGU peripheral ========== \r
+#define AT91C_DBGU_TCR (0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register\r
+#define AT91C_DBGU_RNPR (0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register\r
+#define AT91C_DBGU_TNPR (0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register\r
+#define AT91C_DBGU_TPR (0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register\r
+#define AT91C_DBGU_RPR (0xFFFFF300) // (PDC_DBGU) Receive Pointer Register\r
+#define AT91C_DBGU_RCR (0xFFFFF304) // (PDC_DBGU) Receive Counter Register\r
+#define AT91C_DBGU_RNCR (0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register\r
+#define AT91C_DBGU_PTCR (0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register\r
+#define AT91C_DBGU_PTSR (0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register\r
+#define AT91C_DBGU_TNCR (0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register\r
+// ========== Register definition for DBGU peripheral ========== \r
+#define AT91C_DBGU_EXID (0xFFFFF244) // (DBGU) Chip ID Extension Register\r
+#define AT91C_DBGU_BRGR (0xFFFFF220) // (DBGU) Baud Rate Generator Register\r
+#define AT91C_DBGU_IDR (0xFFFFF20C) // (DBGU) Interrupt Disable Register\r
+#define AT91C_DBGU_CSR (0xFFFFF214) // (DBGU) Channel Status Register\r
+#define AT91C_DBGU_CIDR (0xFFFFF240) // (DBGU) Chip ID Register\r
+#define AT91C_DBGU_MR (0xFFFFF204) // (DBGU) Mode Register\r
+#define AT91C_DBGU_IMR (0xFFFFF210) // (DBGU) Interrupt Mask Register\r
+#define AT91C_DBGU_CR (0xFFFFF200) // (DBGU) Control Register\r
+#define AT91C_DBGU_FNTR (0xFFFFF248) // (DBGU) Force NTRST Register\r
+#define AT91C_DBGU_THR (0xFFFFF21C) // (DBGU) Transmitter Holding Register\r
+#define AT91C_DBGU_RHR (0xFFFFF218) // (DBGU) Receiver Holding Register\r
+#define AT91C_DBGU_IER (0xFFFFF208) // (DBGU) Interrupt Enable Register\r
+// ========== Register definition for PIOA peripheral ========== \r
+#define AT91C_PIOA_ODR (0xFFFFF414) // (PIOA) Output Disable Registerr\r
+#define AT91C_PIOA_SODR (0xFFFFF430) // (PIOA) Set Output Data Register\r
+#define AT91C_PIOA_ISR (0xFFFFF44C) // (PIOA) Interrupt Status Register\r
+#define AT91C_PIOA_ABSR (0xFFFFF478) // (PIOA) AB Select Status Register\r
+#define AT91C_PIOA_IER (0xFFFFF440) // (PIOA) Interrupt Enable Register\r
+#define AT91C_PIOA_PPUDR (0xFFFFF460) // (PIOA) Pull-up Disable Register\r
+#define AT91C_PIOA_IMR (0xFFFFF448) // (PIOA) Interrupt Mask Register\r
+#define AT91C_PIOA_PER (0xFFFFF400) // (PIOA) PIO Enable Register\r
+#define AT91C_PIOA_IFDR (0xFFFFF424) // (PIOA) Input Filter Disable Register\r
+#define AT91C_PIOA_OWDR (0xFFFFF4A4) // (PIOA) Output Write Disable Register\r
+#define AT91C_PIOA_MDSR (0xFFFFF458) // (PIOA) Multi-driver Status Register\r
+#define AT91C_PIOA_IDR (0xFFFFF444) // (PIOA) Interrupt Disable Register\r
+#define AT91C_PIOA_ODSR (0xFFFFF438) // (PIOA) Output Data Status Register\r
+#define AT91C_PIOA_PPUSR (0xFFFFF468) // (PIOA) Pull-up Status Register\r
+#define AT91C_PIOA_OWSR (0xFFFFF4A8) // (PIOA) Output Write Status Register\r
+#define AT91C_PIOA_BSR (0xFFFFF474) // (PIOA) Select B Register\r
+#define AT91C_PIOA_OWER (0xFFFFF4A0) // (PIOA) Output Write Enable Register\r
+#define AT91C_PIOA_IFER (0xFFFFF420) // (PIOA) Input Filter Enable Register\r
+#define AT91C_PIOA_PDSR (0xFFFFF43C) // (PIOA) Pin Data Status Register\r
+#define AT91C_PIOA_PPUER (0xFFFFF464) // (PIOA) Pull-up Enable Register\r
+#define AT91C_PIOA_OSR (0xFFFFF418) // (PIOA) Output Status Register\r
+#define AT91C_PIOA_ASR (0xFFFFF470) // (PIOA) Select A Register\r
+#define AT91C_PIOA_MDDR (0xFFFFF454) // (PIOA) Multi-driver Disable Register\r
+#define AT91C_PIOA_CODR (0xFFFFF434) // (PIOA) Clear Output Data Register\r
+#define AT91C_PIOA_MDER (0xFFFFF450) // (PIOA) Multi-driver Enable Register\r
+#define AT91C_PIOA_PDR (0xFFFFF404) // (PIOA) PIO Disable Register\r
+#define AT91C_PIOA_IFSR (0xFFFFF428) // (PIOA) Input Filter Status Register\r
+#define AT91C_PIOA_OER (0xFFFFF410) // (PIOA) Output Enable Register\r
+#define AT91C_PIOA_PSR (0xFFFFF408) // (PIOA) PIO Status Register\r
+// ========== Register definition for PIOB peripheral ========== \r
+#define AT91C_PIOB_OWDR (0xFFFFF6A4) // (PIOB) Output Write Disable Register\r
+#define AT91C_PIOB_MDER (0xFFFFF650) // (PIOB) Multi-driver Enable Register\r
+#define AT91C_PIOB_PPUSR (0xFFFFF668) // (PIOB) Pull-up Status Register\r
+#define AT91C_PIOB_IMR (0xFFFFF648) // (PIOB) Interrupt Mask Register\r
+#define AT91C_PIOB_ASR (0xFFFFF670) // (PIOB) Select A Register\r
+#define AT91C_PIOB_PPUDR (0xFFFFF660) // (PIOB) Pull-up Disable Register\r
+#define AT91C_PIOB_PSR (0xFFFFF608) // (PIOB) PIO Status Register\r
+#define AT91C_PIOB_IER (0xFFFFF640) // (PIOB) Interrupt Enable Register\r
+#define AT91C_PIOB_CODR (0xFFFFF634) // (PIOB) Clear Output Data Register\r
+#define AT91C_PIOB_OWER (0xFFFFF6A0) // (PIOB) Output Write Enable Register\r
+#define AT91C_PIOB_ABSR (0xFFFFF678) // (PIOB) AB Select Status Register\r
+#define AT91C_PIOB_IFDR (0xFFFFF624) // (PIOB) Input Filter Disable Register\r
+#define AT91C_PIOB_PDSR (0xFFFFF63C) // (PIOB) Pin Data Status Register\r
+#define AT91C_PIOB_IDR (0xFFFFF644) // (PIOB) Interrupt Disable Register\r
+#define AT91C_PIOB_OWSR (0xFFFFF6A8) // (PIOB) Output Write Status Register\r
+#define AT91C_PIOB_PDR (0xFFFFF604) // (PIOB) PIO Disable Register\r
+#define AT91C_PIOB_ODR (0xFFFFF614) // (PIOB) Output Disable Registerr\r
+#define AT91C_PIOB_IFSR (0xFFFFF628) // (PIOB) Input Filter Status Register\r
+#define AT91C_PIOB_PPUER (0xFFFFF664) // (PIOB) Pull-up Enable Register\r
+#define AT91C_PIOB_SODR (0xFFFFF630) // (PIOB) Set Output Data Register\r
+#define AT91C_PIOB_ISR (0xFFFFF64C) // (PIOB) Interrupt Status Register\r
+#define AT91C_PIOB_ODSR (0xFFFFF638) // (PIOB) Output Data Status Register\r
+#define AT91C_PIOB_OSR (0xFFFFF618) // (PIOB) Output Status Register\r
+#define AT91C_PIOB_MDSR (0xFFFFF658) // (PIOB) Multi-driver Status Register\r
+#define AT91C_PIOB_IFER (0xFFFFF620) // (PIOB) Input Filter Enable Register\r
+#define AT91C_PIOB_BSR (0xFFFFF674) // (PIOB) Select B Register\r
+#define AT91C_PIOB_MDDR (0xFFFFF654) // (PIOB) Multi-driver Disable Register\r
+#define AT91C_PIOB_OER (0xFFFFF610) // (PIOB) Output Enable Register\r
+#define AT91C_PIOB_PER (0xFFFFF600) // (PIOB) PIO Enable Register\r
+// ========== Register definition for CKGR peripheral ========== \r
+#define AT91C_CKGR_MOR (0xFFFFFC20) // (CKGR) Main Oscillator Register\r
+#define AT91C_CKGR_PLLR (0xFFFFFC2C) // (CKGR) PLL Register\r
+#define AT91C_CKGR_MCFR (0xFFFFFC24) // (CKGR) Main Clock Frequency Register\r
+// ========== Register definition for PMC peripheral ========== \r
+#define AT91C_PMC_IDR (0xFFFFFC64) // (PMC) Interrupt Disable Register\r
+#define AT91C_PMC_MOR (0xFFFFFC20) // (PMC) Main Oscillator Register\r
+#define AT91C_PMC_PLLR (0xFFFFFC2C) // (PMC) PLL Register\r
+#define AT91C_PMC_PCER (0xFFFFFC10) // (PMC) Peripheral Clock Enable Register\r
+#define AT91C_PMC_PCKR (0xFFFFFC40) // (PMC) Programmable Clock Register\r
+#define AT91C_PMC_MCKR (0xFFFFFC30) // (PMC) Master Clock Register\r
+#define AT91C_PMC_SCDR (0xFFFFFC04) // (PMC) System Clock Disable Register\r
+#define AT91C_PMC_PCDR (0xFFFFFC14) // (PMC) Peripheral Clock Disable Register\r
+#define AT91C_PMC_SCSR (0xFFFFFC08) // (PMC) System Clock Status Register\r
+#define AT91C_PMC_PCSR (0xFFFFFC18) // (PMC) Peripheral Clock Status Register\r
+#define AT91C_PMC_MCFR (0xFFFFFC24) // (PMC) Main Clock Frequency Register\r
+#define AT91C_PMC_SCER (0xFFFFFC00) // (PMC) System Clock Enable Register\r
+#define AT91C_PMC_IMR (0xFFFFFC6C) // (PMC) Interrupt Mask Register\r
+#define AT91C_PMC_IER (0xFFFFFC60) // (PMC) Interrupt Enable Register\r
+#define AT91C_PMC_SR (0xFFFFFC68) // (PMC) Status Register\r
+// ========== Register definition for RSTC peripheral ========== \r
+#define AT91C_RSTC_RCR (0xFFFFFD00) // (RSTC) Reset Control Register\r
+#define AT91C_RSTC_RMR (0xFFFFFD08) // (RSTC) Reset Mode Register\r
+#define AT91C_RSTC_RSR (0xFFFFFD04) // (RSTC) Reset Status Register\r
+// ========== Register definition for RTTC peripheral ========== \r
+#define AT91C_RTTC_RTSR (0xFFFFFD2C) // (RTTC) Real-time Status Register\r
+#define AT91C_RTTC_RTMR (0xFFFFFD20) // (RTTC) Real-time Mode Register\r
+#define AT91C_RTTC_RTVR (0xFFFFFD28) // (RTTC) Real-time Value Register\r
+#define AT91C_RTTC_RTAR (0xFFFFFD24) // (RTTC) Real-time Alarm Register\r
+// ========== Register definition for PITC peripheral ========== \r
+#define AT91C_PITC_PIVR (0xFFFFFD38) // (PITC) Period Interval Value Register\r
+#define AT91C_PITC_PISR (0xFFFFFD34) // (PITC) Period Interval Status Register\r
+#define AT91C_PITC_PIIR (0xFFFFFD3C) // (PITC) Period Interval Image Register\r
+#define AT91C_PITC_PIMR (0xFFFFFD30) // (PITC) Period Interval Mode Register\r
+// ========== Register definition for WDTC peripheral ========== \r
+#define AT91C_WDTC_WDCR (0xFFFFFD40) // (WDTC) Watchdog Control Register\r
+#define AT91C_WDTC_WDSR (0xFFFFFD48) // (WDTC) Watchdog Status Register\r
+#define AT91C_WDTC_WDMR (0xFFFFFD44) // (WDTC) Watchdog Mode Register\r
+// ========== Register definition for VREG peripheral ========== \r
+#define AT91C_VREG_MR (0xFFFFFD60) // (VREG) Voltage Regulator Mode Register\r
+// ========== Register definition for MC peripheral ========== \r
+#define AT91C_MC_ASR (0xFFFFFF04) // (MC) MC Abort Status Register\r
+#define AT91C_MC_RCR (0xFFFFFF00) // (MC) MC Remap Control Register\r
+#define AT91C_MC_FCR (0xFFFFFF64) // (MC) MC Flash Command Register\r
+#define AT91C_MC_AASR (0xFFFFFF08) // (MC) MC Abort Address Status Register\r
+#define AT91C_MC_FSR (0xFFFFFF68) // (MC) MC Flash Status Register\r
+#define AT91C_MC_FMR (0xFFFFFF60) // (MC) MC Flash Mode Register\r
+// ========== Register definition for PDC_SPI1 peripheral ========== \r
+#define AT91C_SPI1_PTCR (0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register\r
+#define AT91C_SPI1_RPR (0xFFFE4100) // (PDC_SPI1) Receive Pointer Register\r
+#define AT91C_SPI1_TNCR (0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register\r
+#define AT91C_SPI1_TPR (0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register\r
+#define AT91C_SPI1_TNPR (0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register\r
+#define AT91C_SPI1_TCR (0xFFFE410C) // (PDC_SPI1) Transmit Counter Register\r
+#define AT91C_SPI1_RCR (0xFFFE4104) // (PDC_SPI1) Receive Counter Register\r
+#define AT91C_SPI1_RNPR (0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register\r
+#define AT91C_SPI1_RNCR (0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register\r
+#define AT91C_SPI1_PTSR (0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register\r
+// ========== Register definition for SPI1 peripheral ========== \r
+#define AT91C_SPI1_IMR (0xFFFE401C) // (SPI1) Interrupt Mask Register\r
+#define AT91C_SPI1_IER (0xFFFE4014) // (SPI1) Interrupt Enable Register\r
+#define AT91C_SPI1_MR (0xFFFE4004) // (SPI1) Mode Register\r
+#define AT91C_SPI1_RDR (0xFFFE4008) // (SPI1) Receive Data Register\r
+#define AT91C_SPI1_IDR (0xFFFE4018) // (SPI1) Interrupt Disable Register\r
+#define AT91C_SPI1_SR (0xFFFE4010) // (SPI1) Status Register\r
+#define AT91C_SPI1_TDR (0xFFFE400C) // (SPI1) Transmit Data Register\r
+#define AT91C_SPI1_CR (0xFFFE4000) // (SPI1) Control Register\r
+#define AT91C_SPI1_CSR (0xFFFE4030) // (SPI1) Chip Select Register\r
+// ========== Register definition for PDC_SPI0 peripheral ========== \r
+#define AT91C_SPI0_PTCR (0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register\r
+#define AT91C_SPI0_TPR (0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register\r
+#define AT91C_SPI0_TCR (0xFFFE010C) // (PDC_SPI0) Transmit Counter Register\r
+#define AT91C_SPI0_RCR (0xFFFE0104) // (PDC_SPI0) Receive Counter Register\r
+#define AT91C_SPI0_PTSR (0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register\r
+#define AT91C_SPI0_RNPR (0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register\r
+#define AT91C_SPI0_RPR (0xFFFE0100) // (PDC_SPI0) Receive Pointer Register\r
+#define AT91C_SPI0_TNCR (0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register\r
+#define AT91C_SPI0_RNCR (0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register\r
+#define AT91C_SPI0_TNPR (0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register\r
+// ========== Register definition for SPI0 peripheral ========== \r
+#define AT91C_SPI0_IER (0xFFFE0014) // (SPI0) Interrupt Enable Register\r
+#define AT91C_SPI0_SR (0xFFFE0010) // (SPI0) Status Register\r
+#define AT91C_SPI0_IDR (0xFFFE0018) // (SPI0) Interrupt Disable Register\r
+#define AT91C_SPI0_CR (0xFFFE0000) // (SPI0) Control Register\r
+#define AT91C_SPI0_MR (0xFFFE0004) // (SPI0) Mode Register\r
+#define AT91C_SPI0_IMR (0xFFFE001C) // (SPI0) Interrupt Mask Register\r
+#define AT91C_SPI0_TDR (0xFFFE000C) // (SPI0) Transmit Data Register\r
+#define AT91C_SPI0_RDR (0xFFFE0008) // (SPI0) Receive Data Register\r
+#define AT91C_SPI0_CSR (0xFFFE0030) // (SPI0) Chip Select Register\r
+// ========== Register definition for PDC_US1 peripheral ========== \r
+#define AT91C_US1_RNCR (0xFFFC4114) // (PDC_US1) Receive Next Counter Register\r
+#define AT91C_US1_PTCR (0xFFFC4120) // (PDC_US1) PDC Transfer Control Register\r
+#define AT91C_US1_TCR (0xFFFC410C) // (PDC_US1) Transmit Counter Register\r
+#define AT91C_US1_PTSR (0xFFFC4124) // (PDC_US1) PDC Transfer Status Register\r
+#define AT91C_US1_TNPR (0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register\r
+#define AT91C_US1_RCR (0xFFFC4104) // (PDC_US1) Receive Counter Register\r
+#define AT91C_US1_RNPR (0xFFFC4110) // (PDC_US1) Receive Next Pointer Register\r
+#define AT91C_US1_RPR (0xFFFC4100) // (PDC_US1) Receive Pointer Register\r
+#define AT91C_US1_TNCR (0xFFFC411C) // (PDC_US1) Transmit Next Counter Register\r
+#define AT91C_US1_TPR (0xFFFC4108) // (PDC_US1) Transmit Pointer Register\r
+// ========== Register definition for US1 peripheral ========== \r
+#define AT91C_US1_IF (0xFFFC404C) // (US1) IRDA_FILTER Register\r
+#define AT91C_US1_NER (0xFFFC4044) // (US1) Nb Errors Register\r
+#define AT91C_US1_RTOR (0xFFFC4024) // (US1) Receiver Time-out Register\r
+#define AT91C_US1_CSR (0xFFFC4014) // (US1) Channel Status Register\r
+#define AT91C_US1_IDR (0xFFFC400C) // (US1) Interrupt Disable Register\r
+#define AT91C_US1_IER (0xFFFC4008) // (US1) Interrupt Enable Register\r
+#define AT91C_US1_THR (0xFFFC401C) // (US1) Transmitter Holding Register\r
+#define AT91C_US1_TTGR (0xFFFC4028) // (US1) Transmitter Time-guard Register\r
+#define AT91C_US1_RHR (0xFFFC4018) // (US1) Receiver Holding Register\r
+#define AT91C_US1_BRGR (0xFFFC4020) // (US1) Baud Rate Generator Register\r
+#define AT91C_US1_IMR (0xFFFC4010) // (US1) Interrupt Mask Register\r
+#define AT91C_US1_FIDI (0xFFFC4040) // (US1) FI_DI_Ratio Register\r
+#define AT91C_US1_CR (0xFFFC4000) // (US1) Control Register\r
+#define AT91C_US1_MR (0xFFFC4004) // (US1) Mode Register\r
+// ========== Register definition for PDC_US0 peripheral ========== \r
+#define AT91C_US0_TNPR (0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register\r
+#define AT91C_US0_RNPR (0xFFFC0110) // (PDC_US0) Receive Next Pointer Register\r
+#define AT91C_US0_TCR (0xFFFC010C) // (PDC_US0) Transmit Counter Register\r
+#define AT91C_US0_PTCR (0xFFFC0120) // (PDC_US0) PDC Transfer Control Register\r
+#define AT91C_US0_PTSR (0xFFFC0124) // (PDC_US0) PDC Transfer Status Register\r
+#define AT91C_US0_TNCR (0xFFFC011C) // (PDC_US0) Transmit Next Counter Register\r
+#define AT91C_US0_TPR (0xFFFC0108) // (PDC_US0) Transmit Pointer Register\r
+#define AT91C_US0_RCR (0xFFFC0104) // (PDC_US0) Receive Counter Register\r
+#define AT91C_US0_RPR (0xFFFC0100) // (PDC_US0) Receive Pointer Register\r
+#define AT91C_US0_RNCR (0xFFFC0114) // (PDC_US0) Receive Next Counter Register\r
+// ========== Register definition for US0 peripheral ========== \r
+#define AT91C_US0_BRGR (0xFFFC0020) // (US0) Baud Rate Generator Register\r
+#define AT91C_US0_NER (0xFFFC0044) // (US0) Nb Errors Register\r
+#define AT91C_US0_CR (0xFFFC0000) // (US0) Control Register\r
+#define AT91C_US0_IMR (0xFFFC0010) // (US0) Interrupt Mask Register\r
+#define AT91C_US0_FIDI (0xFFFC0040) // (US0) FI_DI_Ratio Register\r
+#define AT91C_US0_TTGR (0xFFFC0028) // (US0) Transmitter Time-guard Register\r
+#define AT91C_US0_MR (0xFFFC0004) // (US0) Mode Register\r
+#define AT91C_US0_RTOR (0xFFFC0024) // (US0) Receiver Time-out Register\r
+#define AT91C_US0_CSR (0xFFFC0014) // (US0) Channel Status Register\r
+#define AT91C_US0_RHR (0xFFFC0018) // (US0) Receiver Holding Register\r
+#define AT91C_US0_IDR (0xFFFC000C) // (US0) Interrupt Disable Register\r
+#define AT91C_US0_THR (0xFFFC001C) // (US0) Transmitter Holding Register\r
+#define AT91C_US0_IF (0xFFFC004C) // (US0) IRDA_FILTER Register\r
+#define AT91C_US0_IER (0xFFFC0008) // (US0) Interrupt Enable Register\r
+// ========== Register definition for PDC_SSC peripheral ========== \r
+#define AT91C_SSC_TNCR (0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register\r
+#define AT91C_SSC_RPR (0xFFFD4100) // (PDC_SSC) Receive Pointer Register\r
+#define AT91C_SSC_RNCR (0xFFFD4114) // (PDC_SSC) Receive Next Counter Register\r
+#define AT91C_SSC_TPR (0xFFFD4108) // (PDC_SSC) Transmit Pointer Register\r
+#define AT91C_SSC_PTCR (0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register\r
+#define AT91C_SSC_TCR (0xFFFD410C) // (PDC_SSC) Transmit Counter Register\r
+#define AT91C_SSC_RCR (0xFFFD4104) // (PDC_SSC) Receive Counter Register\r
+#define AT91C_SSC_RNPR (0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register\r
+#define AT91C_SSC_TNPR (0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register\r
+#define AT91C_SSC_PTSR (0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register\r
+// ========== Register definition for SSC peripheral ========== \r
+#define AT91C_SSC_RHR (0xFFFD4020) // (SSC) Receive Holding Register\r
+#define AT91C_SSC_RSHR (0xFFFD4030) // (SSC) Receive Sync Holding Register\r
+#define AT91C_SSC_TFMR (0xFFFD401C) // (SSC) Transmit Frame Mode Register\r
+#define AT91C_SSC_IDR (0xFFFD4048) // (SSC) Interrupt Disable Register\r
+#define AT91C_SSC_THR (0xFFFD4024) // (SSC) Transmit Holding Register\r
+#define AT91C_SSC_RCMR (0xFFFD4010) // (SSC) Receive Clock ModeRegister\r
+#define AT91C_SSC_IER (0xFFFD4044) // (SSC) Interrupt Enable Register\r
+#define AT91C_SSC_TSHR (0xFFFD4034) // (SSC) Transmit Sync Holding Register\r
+#define AT91C_SSC_SR (0xFFFD4040) // (SSC) Status Register\r
+#define AT91C_SSC_CMR (0xFFFD4004) // (SSC) Clock Mode Register\r
+#define AT91C_SSC_TCMR (0xFFFD4018) // (SSC) Transmit Clock Mode Register\r
+#define AT91C_SSC_CR (0xFFFD4000) // (SSC) Control Register\r
+#define AT91C_SSC_IMR (0xFFFD404C) // (SSC) Interrupt Mask Register\r
+#define AT91C_SSC_RFMR (0xFFFD4014) // (SSC) Receive Frame Mode Register\r
+// ========== Register definition for TWI peripheral ========== \r
+#define AT91C_TWI_IER (0xFFFB8024) // (TWI) Interrupt Enable Register\r
+#define AT91C_TWI_CR (0xFFFB8000) // (TWI) Control Register\r
+#define AT91C_TWI_SR (0xFFFB8020) // (TWI) Status Register\r
+#define AT91C_TWI_IMR (0xFFFB802C) // (TWI) Interrupt Mask Register\r
+#define AT91C_TWI_THR (0xFFFB8034) // (TWI) Transmit Holding Register\r
+#define AT91C_TWI_IDR (0xFFFB8028) // (TWI) Interrupt Disable Register\r
+#define AT91C_TWI_IADR (0xFFFB800C) // (TWI) Internal Address Register\r
+#define AT91C_TWI_MMR (0xFFFB8004) // (TWI) Master Mode Register\r
+#define AT91C_TWI_CWGR (0xFFFB8010) // (TWI) Clock Waveform Generator Register\r
+#define AT91C_TWI_RHR (0xFFFB8030) // (TWI) Receive Holding Register\r
+// ========== Register definition for PWMC_CH3 peripheral ========== \r
+#define AT91C_PWMC_CH3_CUPDR (0xFFFCC270) // (PWMC_CH3) Channel Update Register\r
+#define AT91C_PWMC_CH3_Reserved (0xFFFCC274) // (PWMC_CH3) Reserved\r
+#define AT91C_PWMC_CH3_CPRDR (0xFFFCC268) // (PWMC_CH3) Channel Period Register\r
+#define AT91C_PWMC_CH3_CDTYR (0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register\r
+#define AT91C_PWMC_CH3_CCNTR (0xFFFCC26C) // (PWMC_CH3) Channel Counter Register\r
+#define AT91C_PWMC_CH3_CMR (0xFFFCC260) // (PWMC_CH3) Channel Mode Register\r
+// ========== Register definition for PWMC_CH2 peripheral ========== \r
+#define AT91C_PWMC_CH2_Reserved (0xFFFCC254) // (PWMC_CH2) Reserved\r
+#define AT91C_PWMC_CH2_CMR (0xFFFCC240) // (PWMC_CH2) Channel Mode Register\r
+#define AT91C_PWMC_CH2_CCNTR (0xFFFCC24C) // (PWMC_CH2) Channel Counter Register\r
+#define AT91C_PWMC_CH2_CPRDR (0xFFFCC248) // (PWMC_CH2) Channel Period Register\r
+#define AT91C_PWMC_CH2_CUPDR (0xFFFCC250) // (PWMC_CH2) Channel Update Register\r
+#define AT91C_PWMC_CH2_CDTYR (0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register\r
+// ========== Register definition for PWMC_CH1 peripheral ========== \r
+#define AT91C_PWMC_CH1_Reserved (0xFFFCC234) // (PWMC_CH1) Reserved\r
+#define AT91C_PWMC_CH1_CUPDR (0xFFFCC230) // (PWMC_CH1) Channel Update Register\r
+#define AT91C_PWMC_CH1_CPRDR (0xFFFCC228) // (PWMC_CH1) Channel Period Register\r
+#define AT91C_PWMC_CH1_CCNTR (0xFFFCC22C) // (PWMC_CH1) Channel Counter Register\r
+#define AT91C_PWMC_CH1_CDTYR (0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register\r
+#define AT91C_PWMC_CH1_CMR (0xFFFCC220) // (PWMC_CH1) Channel Mode Register\r
+// ========== Register definition for PWMC_CH0 peripheral ========== \r
+#define AT91C_PWMC_CH0_Reserved (0xFFFCC214) // (PWMC_CH0) Reserved\r
+#define AT91C_PWMC_CH0_CPRDR (0xFFFCC208) // (PWMC_CH0) Channel Period Register\r
+#define AT91C_PWMC_CH0_CDTYR (0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register\r
+#define AT91C_PWMC_CH0_CMR (0xFFFCC200) // (PWMC_CH0) Channel Mode Register\r
+#define AT91C_PWMC_CH0_CUPDR (0xFFFCC210) // (PWMC_CH0) Channel Update Register\r
+#define AT91C_PWMC_CH0_CCNTR (0xFFFCC20C) // (PWMC_CH0) Channel Counter Register\r
+// ========== Register definition for PWMC peripheral ========== \r
+#define AT91C_PWMC_IDR (0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register\r
+#define AT91C_PWMC_DIS (0xFFFCC008) // (PWMC) PWMC Disable Register\r
+#define AT91C_PWMC_IER (0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register\r
+#define AT91C_PWMC_VR (0xFFFCC0FC) // (PWMC) PWMC Version Register\r
+#define AT91C_PWMC_ISR (0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register\r
+#define AT91C_PWMC_SR (0xFFFCC00C) // (PWMC) PWMC Status Register\r
+#define AT91C_PWMC_IMR (0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register\r
+#define AT91C_PWMC_MR (0xFFFCC000) // (PWMC) PWMC Mode Register\r
+#define AT91C_PWMC_ENA (0xFFFCC004) // (PWMC) PWMC Enable Register\r
+// ========== Register definition for UDP peripheral ========== \r
+#define AT91C_UDP_IMR (0xFFFB0018) // (UDP) Interrupt Mask Register\r
+#define AT91C_UDP_FADDR (0xFFFB0008) // (UDP) Function Address Register\r
+#define AT91C_UDP_NUM (0xFFFB0000) // (UDP) Frame Number Register\r
+#define AT91C_UDP_FDR (0xFFFB0050) // (UDP) Endpoint FIFO Data Register\r
+#define AT91C_UDP_ISR (0xFFFB001C) // (UDP) Interrupt Status Register\r
+#define AT91C_UDP_CSR (0xFFFB0030) // (UDP) Endpoint Control and Status Register\r
+#define AT91C_UDP_IDR (0xFFFB0014) // (UDP) Interrupt Disable Register\r
+#define AT91C_UDP_ICR (0xFFFB0020) // (UDP) Interrupt Clear Register\r
+#define AT91C_UDP_RSTEP (0xFFFB0028) // (UDP) Reset Endpoint Register\r
+#define AT91C_UDP_TXVC (0xFFFB0074) // (UDP) Transceiver Control Register\r
+#define AT91C_UDP_GLBSTATE (0xFFFB0004) // (UDP) Global State Register\r
+#define AT91C_UDP_IER (0xFFFB0010) // (UDP) Interrupt Enable Register\r
+// ========== Register definition for TC0 peripheral ========== \r
+#define AT91C_TC0_SR (0xFFFA0020) // (TC0) Status Register\r
+#define AT91C_TC0_RC (0xFFFA001C) // (TC0) Register C\r
+#define AT91C_TC0_RB (0xFFFA0018) // (TC0) Register B\r
+#define AT91C_TC0_CCR (0xFFFA0000) // (TC0) Channel Control Register\r
+#define AT91C_TC0_CMR (0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define AT91C_TC0_IER (0xFFFA0024) // (TC0) Interrupt Enable Register\r
+#define AT91C_TC0_RA (0xFFFA0014) // (TC0) Register A\r
+#define AT91C_TC0_IDR (0xFFFA0028) // (TC0) Interrupt Disable Register\r
+#define AT91C_TC0_CV (0xFFFA0010) // (TC0) Counter Value\r
+#define AT91C_TC0_IMR (0xFFFA002C) // (TC0) Interrupt Mask Register\r
+// ========== Register definition for TC1 peripheral ========== \r
+#define AT91C_TC1_RB (0xFFFA0058) // (TC1) Register B\r
+#define AT91C_TC1_CCR (0xFFFA0040) // (TC1) Channel Control Register\r
+#define AT91C_TC1_IER (0xFFFA0064) // (TC1) Interrupt Enable Register\r
+#define AT91C_TC1_IDR (0xFFFA0068) // (TC1) Interrupt Disable Register\r
+#define AT91C_TC1_SR (0xFFFA0060) // (TC1) Status Register\r
+#define AT91C_TC1_CMR (0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define AT91C_TC1_RA (0xFFFA0054) // (TC1) Register A\r
+#define AT91C_TC1_RC (0xFFFA005C) // (TC1) Register C\r
+#define AT91C_TC1_IMR (0xFFFA006C) // (TC1) Interrupt Mask Register\r
+#define AT91C_TC1_CV (0xFFFA0050) // (TC1) Counter Value\r
+// ========== Register definition for TC2 peripheral ========== \r
+#define AT91C_TC2_CMR (0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define AT91C_TC2_CCR (0xFFFA0080) // (TC2) Channel Control Register\r
+#define AT91C_TC2_CV (0xFFFA0090) // (TC2) Counter Value\r
+#define AT91C_TC2_RA (0xFFFA0094) // (TC2) Register A\r
+#define AT91C_TC2_RB (0xFFFA0098) // (TC2) Register B\r
+#define AT91C_TC2_IDR (0xFFFA00A8) // (TC2) Interrupt Disable Register\r
+#define AT91C_TC2_IMR (0xFFFA00AC) // (TC2) Interrupt Mask Register\r
+#define AT91C_TC2_RC (0xFFFA009C) // (TC2) Register C\r
+#define AT91C_TC2_IER (0xFFFA00A4) // (TC2) Interrupt Enable Register\r
+#define AT91C_TC2_SR (0xFFFA00A0) // (TC2) Status Register\r
+// ========== Register definition for TCB peripheral ========== \r
+#define AT91C_TCB_BMR (0xFFFA00C4) // (TCB) TC Block Mode Register\r
+#define AT91C_TCB_BCR (0xFFFA00C0) // (TCB) TC Block Control Register\r
+// ========== Register definition for CAN_MB0 peripheral ========== \r
+#define AT91C_CAN_MB0_MDL (0xFFFD0214) // (CAN_MB0) MailBox Data Low Register\r
+#define AT91C_CAN_MB0_MAM (0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register\r
+#define AT91C_CAN_MB0_MCR (0xFFFD021C) // (CAN_MB0) MailBox Control Register\r
+#define AT91C_CAN_MB0_MID (0xFFFD0208) // (CAN_MB0) MailBox ID Register\r
+#define AT91C_CAN_MB0_MSR (0xFFFD0210) // (CAN_MB0) MailBox Status Register\r
+#define AT91C_CAN_MB0_MFID (0xFFFD020C) // (CAN_MB0) MailBox Family ID Register\r
+#define AT91C_CAN_MB0_MDH (0xFFFD0218) // (CAN_MB0) MailBox Data High Register\r
+#define AT91C_CAN_MB0_MMR (0xFFFD0200) // (CAN_MB0) MailBox Mode Register\r
+// ========== Register definition for CAN_MB1 peripheral ========== \r
+#define AT91C_CAN_MB1_MDL (0xFFFD0234) // (CAN_MB1) MailBox Data Low Register\r
+#define AT91C_CAN_MB1_MID (0xFFFD0228) // (CAN_MB1) MailBox ID Register\r
+#define AT91C_CAN_MB1_MMR (0xFFFD0220) // (CAN_MB1) MailBox Mode Register\r
+#define AT91C_CAN_MB1_MSR (0xFFFD0230) // (CAN_MB1) MailBox Status Register\r
+#define AT91C_CAN_MB1_MAM (0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register\r
+#define AT91C_CAN_MB1_MDH (0xFFFD0238) // (CAN_MB1) MailBox Data High Register\r
+#define AT91C_CAN_MB1_MCR (0xFFFD023C) // (CAN_MB1) MailBox Control Register\r
+#define AT91C_CAN_MB1_MFID (0xFFFD022C) // (CAN_MB1) MailBox Family ID Register\r
+// ========== Register definition for CAN_MB2 peripheral ========== \r
+#define AT91C_CAN_MB2_MCR (0xFFFD025C) // (CAN_MB2) MailBox Control Register\r
+#define AT91C_CAN_MB2_MDH (0xFFFD0258) // (CAN_MB2) MailBox Data High Register\r
+#define AT91C_CAN_MB2_MID (0xFFFD0248) // (CAN_MB2) MailBox ID Register\r
+#define AT91C_CAN_MB2_MDL (0xFFFD0254) // (CAN_MB2) MailBox Data Low Register\r
+#define AT91C_CAN_MB2_MMR (0xFFFD0240) // (CAN_MB2) MailBox Mode Register\r
+#define AT91C_CAN_MB2_MAM (0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register\r
+#define AT91C_CAN_MB2_MFID (0xFFFD024C) // (CAN_MB2) MailBox Family ID Register\r
+#define AT91C_CAN_MB2_MSR (0xFFFD0250) // (CAN_MB2) MailBox Status Register\r
+// ========== Register definition for CAN_MB3 peripheral ========== \r
+#define AT91C_CAN_MB3_MFID (0xFFFD026C) // (CAN_MB3) MailBox Family ID Register\r
+#define AT91C_CAN_MB3_MAM (0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register\r
+#define AT91C_CAN_MB3_MID (0xFFFD0268) // (CAN_MB3) MailBox ID Register\r
+#define AT91C_CAN_MB3_MCR (0xFFFD027C) // (CAN_MB3) MailBox Control Register\r
+#define AT91C_CAN_MB3_MMR (0xFFFD0260) // (CAN_MB3) MailBox Mode Register\r
+#define AT91C_CAN_MB3_MSR (0xFFFD0270) // (CAN_MB3) MailBox Status Register\r
+#define AT91C_CAN_MB3_MDL (0xFFFD0274) // (CAN_MB3) MailBox Data Low Register\r
+#define AT91C_CAN_MB3_MDH (0xFFFD0278) // (CAN_MB3) MailBox Data High Register\r
+// ========== Register definition for CAN_MB4 peripheral ========== \r
+#define AT91C_CAN_MB4_MID (0xFFFD0288) // (CAN_MB4) MailBox ID Register\r
+#define AT91C_CAN_MB4_MMR (0xFFFD0280) // (CAN_MB4) MailBox Mode Register\r
+#define AT91C_CAN_MB4_MDH (0xFFFD0298) // (CAN_MB4) MailBox Data High Register\r
+#define AT91C_CAN_MB4_MFID (0xFFFD028C) // (CAN_MB4) MailBox Family ID Register\r
+#define AT91C_CAN_MB4_MSR (0xFFFD0290) // (CAN_MB4) MailBox Status Register\r
+#define AT91C_CAN_MB4_MCR (0xFFFD029C) // (CAN_MB4) MailBox Control Register\r
+#define AT91C_CAN_MB4_MDL (0xFFFD0294) // (CAN_MB4) MailBox Data Low Register\r
+#define AT91C_CAN_MB4_MAM (0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register\r
+// ========== Register definition for CAN_MB5 peripheral ========== \r
+#define AT91C_CAN_MB5_MSR (0xFFFD02B0) // (CAN_MB5) MailBox Status Register\r
+#define AT91C_CAN_MB5_MCR (0xFFFD02BC) // (CAN_MB5) MailBox Control Register\r
+#define AT91C_CAN_MB5_MFID (0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register\r
+#define AT91C_CAN_MB5_MDH (0xFFFD02B8) // (CAN_MB5) MailBox Data High Register\r
+#define AT91C_CAN_MB5_MID (0xFFFD02A8) // (CAN_MB5) MailBox ID Register\r
+#define AT91C_CAN_MB5_MMR (0xFFFD02A0) // (CAN_MB5) MailBox Mode Register\r
+#define AT91C_CAN_MB5_MDL (0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register\r
+#define AT91C_CAN_MB5_MAM (0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register\r
+// ========== Register definition for CAN_MB6 peripheral ========== \r
+#define AT91C_CAN_MB6_MFID (0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register\r
+#define AT91C_CAN_MB6_MID (0xFFFD02C8) // (CAN_MB6) MailBox ID Register\r
+#define AT91C_CAN_MB6_MAM (0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register\r
+#define AT91C_CAN_MB6_MSR (0xFFFD02D0) // (CAN_MB6) MailBox Status Register\r
+#define AT91C_CAN_MB6_MDL (0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register\r
+#define AT91C_CAN_MB6_MCR (0xFFFD02DC) // (CAN_MB6) MailBox Control Register\r
+#define AT91C_CAN_MB6_MDH (0xFFFD02D8) // (CAN_MB6) MailBox Data High Register\r
+#define AT91C_CAN_MB6_MMR (0xFFFD02C0) // (CAN_MB6) MailBox Mode Register\r
+// ========== Register definition for CAN_MB7 peripheral ========== \r
+#define AT91C_CAN_MB7_MCR (0xFFFD02FC) // (CAN_MB7) MailBox Control Register\r
+#define AT91C_CAN_MB7_MDH (0xFFFD02F8) // (CAN_MB7) MailBox Data High Register\r
+#define AT91C_CAN_MB7_MFID (0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register\r
+#define AT91C_CAN_MB7_MDL (0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register\r
+#define AT91C_CAN_MB7_MID (0xFFFD02E8) // (CAN_MB7) MailBox ID Register\r
+#define AT91C_CAN_MB7_MMR (0xFFFD02E0) // (CAN_MB7) MailBox Mode Register\r
+#define AT91C_CAN_MB7_MAM (0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register\r
+#define AT91C_CAN_MB7_MSR (0xFFFD02F0) // (CAN_MB7) MailBox Status Register\r
+// ========== Register definition for CAN peripheral ========== \r
+#define AT91C_CAN_TCR (0xFFFD0024) // (CAN) Transfer Command Register\r
+#define AT91C_CAN_IMR (0xFFFD000C) // (CAN) Interrupt Mask Register\r
+#define AT91C_CAN_IER (0xFFFD0004) // (CAN) Interrupt Enable Register\r
+#define AT91C_CAN_ECR (0xFFFD0020) // (CAN) Error Counter Register\r
+#define AT91C_CAN_TIMESTP (0xFFFD001C) // (CAN) Time Stamp Register\r
+#define AT91C_CAN_MR (0xFFFD0000) // (CAN) Mode Register\r
+#define AT91C_CAN_IDR (0xFFFD0008) // (CAN) Interrupt Disable Register\r
+#define AT91C_CAN_ACR (0xFFFD0028) // (CAN) Abort Command Register\r
+#define AT91C_CAN_TIM (0xFFFD0018) // (CAN) Timer Register\r
+#define AT91C_CAN_SR (0xFFFD0010) // (CAN) Status Register\r
+#define AT91C_CAN_BR (0xFFFD0014) // (CAN) Baudrate Register\r
+#define AT91C_CAN_VR (0xFFFD00FC) // (CAN) Version Register\r
+// ========== Register definition for EMAC peripheral ========== \r
+#define AT91C_EMAC_ISR (0xFFFDC024) // (EMAC) Interrupt Status Register\r
+#define AT91C_EMAC_SA4H (0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes\r
+#define AT91C_EMAC_SA1L (0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes\r
+#define AT91C_EMAC_ELE (0xFFFDC078) // (EMAC) Excessive Length Errors Register\r
+#define AT91C_EMAC_LCOL (0xFFFDC05C) // (EMAC) Late Collision Register\r
+#define AT91C_EMAC_RLE (0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register\r
+#define AT91C_EMAC_WOL (0xFFFDC0C4) // (EMAC) Wake On LAN Register\r
+#define AT91C_EMAC_DTF (0xFFFDC058) // (EMAC) Deferred Transmission Frame Register\r
+#define AT91C_EMAC_TUND (0xFFFDC064) // (EMAC) Transmit Underrun Error Register\r
+#define AT91C_EMAC_NCR (0xFFFDC000) // (EMAC) Network Control Register\r
+#define AT91C_EMAC_SA4L (0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes\r
+#define AT91C_EMAC_RSR (0xFFFDC020) // (EMAC) Receive Status Register\r
+#define AT91C_EMAC_SA3L (0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes\r
+#define AT91C_EMAC_TSR (0xFFFDC014) // (EMAC) Transmit Status Register\r
+#define AT91C_EMAC_IDR (0xFFFDC02C) // (EMAC) Interrupt Disable Register\r
+#define AT91C_EMAC_RSE (0xFFFDC074) // (EMAC) Receive Symbol Errors Register\r
+#define AT91C_EMAC_ECOL (0xFFFDC060) // (EMAC) Excessive Collision Register\r
+#define AT91C_EMAC_TID (0xFFFDC0B8) // (EMAC) Type ID Checking Register\r
+#define AT91C_EMAC_HRB (0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]\r
+#define AT91C_EMAC_TBQP (0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer\r
+#define AT91C_EMAC_USRIO (0xFFFDC0C0) // (EMAC) USER Input/Output Register\r
+#define AT91C_EMAC_PTR (0xFFFDC038) // (EMAC) Pause Time Register\r
+#define AT91C_EMAC_SA2H (0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes\r
+#define AT91C_EMAC_ROV (0xFFFDC070) // (EMAC) Receive Overrun Errors Register\r
+#define AT91C_EMAC_ALE (0xFFFDC054) // (EMAC) Alignment Error Register\r
+#define AT91C_EMAC_RJA (0xFFFDC07C) // (EMAC) Receive Jabbers Register\r
+#define AT91C_EMAC_RBQP (0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer\r
+#define AT91C_EMAC_TPF (0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register\r
+#define AT91C_EMAC_NCFGR (0xFFFDC004) // (EMAC) Network Configuration Register\r
+#define AT91C_EMAC_HRT (0xFFFDC094) // (EMAC) Hash Address Top[63:32]\r
+#define AT91C_EMAC_USF (0xFFFDC080) // (EMAC) Undersize Frames Register\r
+#define AT91C_EMAC_FCSE (0xFFFDC050) // (EMAC) Frame Check Sequence Error Register\r
+#define AT91C_EMAC_TPQ (0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register\r
+#define AT91C_EMAC_MAN (0xFFFDC034) // (EMAC) PHY Maintenance Register\r
+#define AT91C_EMAC_FTO (0xFFFDC040) // (EMAC) Frames Transmitted OK Register\r
+#define AT91C_EMAC_REV (0xFFFDC0FC) // (EMAC) Revision Register\r
+#define AT91C_EMAC_IMR (0xFFFDC030) // (EMAC) Interrupt Mask Register\r
+#define AT91C_EMAC_SCF (0xFFFDC044) // (EMAC) Single Collision Frame Register\r
+#define AT91C_EMAC_PFR (0xFFFDC03C) // (EMAC) Pause Frames received Register\r
+#define AT91C_EMAC_MCF (0xFFFDC048) // (EMAC) Multiple Collision Frame Register\r
+#define AT91C_EMAC_NSR (0xFFFDC008) // (EMAC) Network Status Register\r
+#define AT91C_EMAC_SA2L (0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes\r
+#define AT91C_EMAC_FRO (0xFFFDC04C) // (EMAC) Frames Received OK Register\r
+#define AT91C_EMAC_IER (0xFFFDC028) // (EMAC) Interrupt Enable Register\r
+#define AT91C_EMAC_SA1H (0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes\r
+#define AT91C_EMAC_CSE (0xFFFDC068) // (EMAC) Carrier Sense Error Register\r
+#define AT91C_EMAC_SA3H (0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes\r
+#define AT91C_EMAC_RRE (0xFFFDC06C) // (EMAC) Receive Ressource Error Register\r
+#define AT91C_EMAC_STE (0xFFFDC084) // (EMAC) SQE Test Error Register\r
+// ========== Register definition for PDC_ADC peripheral ========== \r
+#define AT91C_ADC_PTSR (0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register\r
+#define AT91C_ADC_PTCR (0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register\r
+#define AT91C_ADC_TNPR (0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register\r
+#define AT91C_ADC_TNCR (0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register\r
+#define AT91C_ADC_RNPR (0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register\r
+#define AT91C_ADC_RNCR (0xFFFD8114) // (PDC_ADC) Receive Next Counter Register\r
+#define AT91C_ADC_RPR (0xFFFD8100) // (PDC_ADC) Receive Pointer Register\r
+#define AT91C_ADC_TCR (0xFFFD810C) // (PDC_ADC) Transmit Counter Register\r
+#define AT91C_ADC_TPR (0xFFFD8108) // (PDC_ADC) Transmit Pointer Register\r
+#define AT91C_ADC_RCR (0xFFFD8104) // (PDC_ADC) Receive Counter Register\r
+// ========== Register definition for ADC peripheral ========== \r
+#define AT91C_ADC_CDR2 (0xFFFD8038) // (ADC) ADC Channel Data Register 2\r
+#define AT91C_ADC_CDR3 (0xFFFD803C) // (ADC) ADC Channel Data Register 3\r
+#define AT91C_ADC_CDR0 (0xFFFD8030) // (ADC) ADC Channel Data Register 0\r
+#define AT91C_ADC_CDR5 (0xFFFD8044) // (ADC) ADC Channel Data Register 5\r
+#define AT91C_ADC_CHDR (0xFFFD8014) // (ADC) ADC Channel Disable Register\r
+#define AT91C_ADC_SR (0xFFFD801C) // (ADC) ADC Status Register\r
+#define AT91C_ADC_CDR4 (0xFFFD8040) // (ADC) ADC Channel Data Register 4\r
+#define AT91C_ADC_CDR1 (0xFFFD8034) // (ADC) ADC Channel Data Register 1\r
+#define AT91C_ADC_LCDR (0xFFFD8020) // (ADC) ADC Last Converted Data Register\r
+#define AT91C_ADC_IDR (0xFFFD8028) // (ADC) ADC Interrupt Disable Register\r
+#define AT91C_ADC_CR (0xFFFD8000) // (ADC) ADC Control Register\r
+#define AT91C_ADC_CDR7 (0xFFFD804C) // (ADC) ADC Channel Data Register 7\r
+#define AT91C_ADC_CDR6 (0xFFFD8048) // (ADC) ADC Channel Data Register 6\r
+#define AT91C_ADC_IER (0xFFFD8024) // (ADC) ADC Interrupt Enable Register\r
+#define AT91C_ADC_CHER (0xFFFD8010) // (ADC) ADC Channel Enable Register\r
+#define AT91C_ADC_CHSR (0xFFFD8018) // (ADC) ADC Channel Status Register\r
+#define AT91C_ADC_MR (0xFFFD8004) // (ADC) ADC Mode Register\r
+#define AT91C_ADC_IMR (0xFFFD802C) // (ADC) ADC Interrupt Mask Register\r
+// ========== Register definition for PDC_AES peripheral ========== \r
+#define AT91C_AES_TPR (0xFFFA4108) // (PDC_AES) Transmit Pointer Register\r
+#define AT91C_AES_PTCR (0xFFFA4120) // (PDC_AES) PDC Transfer Control Register\r
+#define AT91C_AES_RNPR (0xFFFA4110) // (PDC_AES) Receive Next Pointer Register\r
+#define AT91C_AES_TNCR (0xFFFA411C) // (PDC_AES) Transmit Next Counter Register\r
+#define AT91C_AES_TCR (0xFFFA410C) // (PDC_AES) Transmit Counter Register\r
+#define AT91C_AES_RCR (0xFFFA4104) // (PDC_AES) Receive Counter Register\r
+#define AT91C_AES_RNCR (0xFFFA4114) // (PDC_AES) Receive Next Counter Register\r
+#define AT91C_AES_TNPR (0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register\r
+#define AT91C_AES_RPR (0xFFFA4100) // (PDC_AES) Receive Pointer Register\r
+#define AT91C_AES_PTSR (0xFFFA4124) // (PDC_AES) PDC Transfer Status Register\r
+// ========== Register definition for AES peripheral ========== \r
+#define AT91C_AES_IVxR (0xFFFA4060) // (AES) Initialization Vector x Register\r
+#define AT91C_AES_MR (0xFFFA4004) // (AES) Mode Register\r
+#define AT91C_AES_VR (0xFFFA40FC) // (AES) AES Version Register\r
+#define AT91C_AES_ODATAxR (0xFFFA4050) // (AES) Output Data x Register\r
+#define AT91C_AES_IDATAxR (0xFFFA4040) // (AES) Input Data x Register\r
+#define AT91C_AES_CR (0xFFFA4000) // (AES) Control Register\r
+#define AT91C_AES_IDR (0xFFFA4014) // (AES) Interrupt Disable Register\r
+#define AT91C_AES_IMR (0xFFFA4018) // (AES) Interrupt Mask Register\r
+#define AT91C_AES_IER (0xFFFA4010) // (AES) Interrupt Enable Register\r
+#define AT91C_AES_KEYWxR (0xFFFA4020) // (AES) Key Word x Register\r
+#define AT91C_AES_ISR (0xFFFA401C) // (AES) Interrupt Status Register\r
+// ========== Register definition for PDC_TDES peripheral ========== \r
+#define AT91C_TDES_RNCR (0xFFFA8114) // (PDC_TDES) Receive Next Counter Register\r
+#define AT91C_TDES_TCR (0xFFFA810C) // (PDC_TDES) Transmit Counter Register\r
+#define AT91C_TDES_RCR (0xFFFA8104) // (PDC_TDES) Receive Counter Register\r
+#define AT91C_TDES_TNPR (0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register\r
+#define AT91C_TDES_RNPR (0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register\r
+#define AT91C_TDES_RPR (0xFFFA8100) // (PDC_TDES) Receive Pointer Register\r
+#define AT91C_TDES_TNCR (0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register\r
+#define AT91C_TDES_TPR (0xFFFA8108) // (PDC_TDES) Transmit Pointer Register\r
+#define AT91C_TDES_PTSR (0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register\r
+#define AT91C_TDES_PTCR (0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register\r
+// ========== Register definition for TDES peripheral ========== \r
+#define AT91C_TDES_KEY2WxR (0xFFFA8028) // (TDES) Key 2 Word x Register\r
+#define AT91C_TDES_KEY3WxR (0xFFFA8030) // (TDES) Key 3 Word x Register\r
+#define AT91C_TDES_IDR (0xFFFA8014) // (TDES) Interrupt Disable Register\r
+#define AT91C_TDES_VR (0xFFFA80FC) // (TDES) TDES Version Register\r
+#define AT91C_TDES_IVxR (0xFFFA8060) // (TDES) Initialization Vector x Register\r
+#define AT91C_TDES_ODATAxR (0xFFFA8050) // (TDES) Output Data x Register\r
+#define AT91C_TDES_IMR (0xFFFA8018) // (TDES) Interrupt Mask Register\r
+#define AT91C_TDES_MR (0xFFFA8004) // (TDES) Mode Register\r
+#define AT91C_TDES_CR (0xFFFA8000) // (TDES) Control Register\r
+#define AT91C_TDES_IER (0xFFFA8010) // (TDES) Interrupt Enable Register\r
+#define AT91C_TDES_ISR (0xFFFA801C) // (TDES) Interrupt Status Register\r
+#define AT91C_TDES_IDATAxR (0xFFFA8040) // (TDES) Input Data x Register\r
+#define AT91C_TDES_KEY1WxR (0xFFFA8020) // (TDES) Key 1 Word x Register\r
+\r
+// *****************************************************************************\r
+// PIO DEFINITIONS FOR AT91SAM7X128\r
+// *****************************************************************************\r
+#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0\r
+#define AT91C_PA0_RXD0 (AT91C_PIO_PA0) // USART 0 Receive Data\r
+#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1\r
+#define AT91C_PA1_TXD0 (AT91C_PIO_PA1) // USART 0 Transmit Data\r
+#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10\r
+#define AT91C_PA10_TWD (AT91C_PIO_PA10) // TWI Two-wire Serial Data\r
+#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11\r
+#define AT91C_PA11_TWCK (AT91C_PIO_PA11) // TWI Two-wire Serial Clock\r
+#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12\r
+#define AT91C_PA12_NPCS00 (AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0\r
+#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13\r
+#define AT91C_PA13_NPCS01 (AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1\r
+#define AT91C_PA13_PCK1 (AT91C_PIO_PA13) // PMC Programmable Clock Output 1\r
+#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14\r
+#define AT91C_PA14_NPCS02 (AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2\r
+#define AT91C_PA14_IRQ1 (AT91C_PIO_PA14) // External Interrupt 1\r
+#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15\r
+#define AT91C_PA15_NPCS03 (AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3\r
+#define AT91C_PA15_TCLK2 (AT91C_PIO_PA15) // Timer Counter 2 external clock input\r
+#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16\r
+#define AT91C_PA16_MISO0 (AT91C_PIO_PA16) // SPI 0 Master In Slave\r
+#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17\r
+#define AT91C_PA17_MOSI0 (AT91C_PIO_PA17) // SPI 0 Master Out Slave\r
+#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18\r
+#define AT91C_PA18_SPCK0 (AT91C_PIO_PA18) // SPI 0 Serial Clock\r
+#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19\r
+#define AT91C_PA19_CANRX (AT91C_PIO_PA19) // CAN Receive\r
+#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2\r
+#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock\r
+#define AT91C_PA2_NPCS11 (AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1\r
+#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20\r
+#define AT91C_PA20_CANTX (AT91C_PIO_PA20) // CAN Transmit\r
+#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21\r
+#define AT91C_PA21_TF (AT91C_PIO_PA21) // SSC Transmit Frame Sync\r
+#define AT91C_PA21_NPCS10 (AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0\r
+#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22\r
+#define AT91C_PA22_TK (AT91C_PIO_PA22) // SSC Transmit Clock\r
+#define AT91C_PA22_SPCK1 (AT91C_PIO_PA22) // SPI 1 Serial Clock\r
+#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23\r
+#define AT91C_PA23_TD (AT91C_PIO_PA23) // SSC Transmit data\r
+#define AT91C_PA23_MOSI1 (AT91C_PIO_PA23) // SPI 1 Master Out Slave\r
+#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24\r
+#define AT91C_PA24_RD (AT91C_PIO_PA24) // SSC Receive Data\r
+#define AT91C_PA24_MISO1 (AT91C_PIO_PA24) // SPI 1 Master In Slave\r
+#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25\r
+#define AT91C_PA25_RK (AT91C_PIO_PA25) // SSC Receive Clock\r
+#define AT91C_PA25_NPCS11 (AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1\r
+#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26\r
+#define AT91C_PA26_RF (AT91C_PIO_PA26) // SSC Receive Frame Sync\r
+#define AT91C_PA26_NPCS12 (AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2\r
+#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27\r
+#define AT91C_PA27_DRXD (AT91C_PIO_PA27) // DBGU Debug Receive Data\r
+#define AT91C_PA27_PCK3 (AT91C_PIO_PA27) // PMC Programmable Clock Output 3\r
+#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28\r
+#define AT91C_PA28_DTXD (AT91C_PIO_PA28) // DBGU Debug Transmit Data\r
+#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29\r
+#define AT91C_PA29_FIQ (AT91C_PIO_PA29) // AIC Fast Interrupt Input\r
+#define AT91C_PA29_NPCS13 (AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3\r
+#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3\r
+#define AT91C_PA3_RTS0 (AT91C_PIO_PA3) // USART 0 Ready To Send\r
+#define AT91C_PA3_NPCS12 (AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2\r
+#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30\r
+#define AT91C_PA30_IRQ0 (AT91C_PIO_PA30) // External Interrupt 0\r
+#define AT91C_PA30_PCK2 (AT91C_PIO_PA30) // PMC Programmable Clock Output 2\r
+#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4\r
+#define AT91C_PA4_CTS0 (AT91C_PIO_PA4) // USART 0 Clear To Send\r
+#define AT91C_PA4_NPCS13 (AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3\r
+#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5\r
+#define AT91C_PA5_RXD1 (AT91C_PIO_PA5) // USART 1 Receive Data\r
+#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6\r
+#define AT91C_PA6_TXD1 (AT91C_PIO_PA6) // USART 1 Transmit Data\r
+#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7\r
+#define AT91C_PA7_SCK1 (AT91C_PIO_PA7) // USART 1 Serial Clock\r
+#define AT91C_PA7_NPCS01 (AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1\r
+#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8\r
+#define AT91C_PA8_RTS1 (AT91C_PIO_PA8) // USART 1 Ready To Send\r
+#define AT91C_PA8_NPCS02 (AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2\r
+#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9\r
+#define AT91C_PA9_CTS1 (AT91C_PIO_PA9) // USART 1 Clear To Send\r
+#define AT91C_PA9_NPCS03 (AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3\r
+#define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0\r
+#define AT91C_PB0_ETXCK_EREFCK (AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock\r
+#define AT91C_PB0_PCK0 (AT91C_PIO_PB0) // PMC Programmable Clock Output 0\r
+#define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1\r
+#define AT91C_PB1_ETXEN (AT91C_PIO_PB1) // Ethernet MAC Transmit Enable\r
+#define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10\r
+#define AT91C_PB10_ETX2 (AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2\r
+#define AT91C_PB10_NPCS11 (AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1\r
+#define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11\r
+#define AT91C_PB11_ETX3 (AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3\r
+#define AT91C_PB11_NPCS12 (AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2\r
+#define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12\r
+#define AT91C_PB12_ETXER (AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error\r
+#define AT91C_PB12_TCLK0 (AT91C_PIO_PB12) // Timer Counter 0 external clock input\r
+#define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13\r
+#define AT91C_PB13_ERX2 (AT91C_PIO_PB13) // Ethernet MAC Receive Data 2\r
+#define AT91C_PB13_NPCS01 (AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1\r
+#define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14\r
+#define AT91C_PB14_ERX3 (AT91C_PIO_PB14) // Ethernet MAC Receive Data 3\r
+#define AT91C_PB14_NPCS02 (AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2\r
+#define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15\r
+#define AT91C_PB15_ERXDV (AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid\r
+#define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16\r
+#define AT91C_PB16_ECOL (AT91C_PIO_PB16) // Ethernet MAC Collision Detected\r
+#define AT91C_PB16_NPCS13 (AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3\r
+#define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17\r
+#define AT91C_PB17_ERXCK (AT91C_PIO_PB17) // Ethernet MAC Receive Clock\r
+#define AT91C_PB17_NPCS03 (AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3\r
+#define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18\r
+#define AT91C_PB18_EF100 (AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec\r
+#define AT91C_PB18_ADTRG (AT91C_PIO_PB18) // ADC External Trigger\r
+#define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19\r
+#define AT91C_PB19_PWM0 (AT91C_PIO_PB19) // PWM Channel 0\r
+#define AT91C_PB19_TCLK1 (AT91C_PIO_PB19) // Timer Counter 1 external clock input\r
+#define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2\r
+#define AT91C_PB2_ETX0 (AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0\r
+#define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20\r
+#define AT91C_PB20_PWM1 (AT91C_PIO_PB20) // PWM Channel 1\r
+#define AT91C_PB20_PCK0 (AT91C_PIO_PB20) // PMC Programmable Clock Output 0\r
+#define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21\r
+#define AT91C_PB21_PWM2 (AT91C_PIO_PB21) // PWM Channel 2\r
+#define AT91C_PB21_PCK1 (AT91C_PIO_PB21) // PMC Programmable Clock Output 1\r
+#define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22\r
+#define AT91C_PB22_PWM3 (AT91C_PIO_PB22) // PWM Channel 3\r
+#define AT91C_PB22_PCK2 (AT91C_PIO_PB22) // PMC Programmable Clock Output 2\r
+#define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23\r
+#define AT91C_PB23_TIOA0 (AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A\r
+#define AT91C_PB23_DCD1 (AT91C_PIO_PB23) // USART 1 Data Carrier Detect\r
+#define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24\r
+#define AT91C_PB24_TIOB0 (AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B\r
+#define AT91C_PB24_DSR1 (AT91C_PIO_PB24) // USART 1 Data Set ready\r
+#define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25\r
+#define AT91C_PB25_TIOA1 (AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A\r
+#define AT91C_PB25_DTR1 (AT91C_PIO_PB25) // USART 1 Data Terminal ready\r
+#define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26\r
+#define AT91C_PB26_TIOB1 (AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B\r
+#define AT91C_PB26_RI1 (AT91C_PIO_PB26) // USART 1 Ring Indicator\r
+#define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27\r
+#define AT91C_PB27_TIOA2 (AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A\r
+#define AT91C_PB27_PWM0 (AT91C_PIO_PB27) // PWM Channel 0\r
+#define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28\r
+#define AT91C_PB28_TIOB2 (AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B\r
+#define AT91C_PB28_PWM1 (AT91C_PIO_PB28) // PWM Channel 1\r
+#define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29\r
+#define AT91C_PB29_PCK1 (AT91C_PIO_PB29) // PMC Programmable Clock Output 1\r
+#define AT91C_PB29_PWM2 (AT91C_PIO_PB29) // PWM Channel 2\r
+#define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3\r
+#define AT91C_PB3_ETX1 (AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1\r
+#define AT91C_PIO_PB30 (1 << 30) // Pin Controlled by PB30\r
+#define AT91C_PB30_PCK2 (AT91C_PIO_PB30) // PMC Programmable Clock Output 2\r
+#define AT91C_PB30_PWM3 (AT91C_PIO_PB30) // PWM Channel 3\r
+#define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4\r
+#define AT91C_PB4_ECRS_ECRSDV (AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid\r
+#define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5\r
+#define AT91C_PB5_ERX0 (AT91C_PIO_PB5) // Ethernet MAC Receive Data 0\r
+#define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6\r
+#define AT91C_PB6_ERX1 (AT91C_PIO_PB6) // Ethernet MAC Receive Data 1\r
+#define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7\r
+#define AT91C_PB7_ERXER (AT91C_PIO_PB7) // Ethernet MAC Receive Error\r
+#define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8\r
+#define AT91C_PB8_EMDC (AT91C_PIO_PB8) // Ethernet MAC Management Data Clock\r
+#define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9\r
+#define AT91C_PB9_EMDIO (AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output\r
+\r
+// *****************************************************************************\r
+// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X128\r
+// *****************************************************************************\r
+#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ)\r
+#define AT91C_ID_SYS ( 1) // System Peripheral\r
+#define AT91C_ID_PIOA ( 2) // Parallel IO Controller A\r
+#define AT91C_ID_PIOB ( 3) // Parallel IO Controller B\r
+#define AT91C_ID_SPI0 ( 4) // Serial Peripheral Interface 0\r
+#define AT91C_ID_SPI1 ( 5) // Serial Peripheral Interface 1\r
+#define AT91C_ID_US0 ( 6) // USART 0\r
+#define AT91C_ID_US1 ( 7) // USART 1\r
+#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller\r
+#define AT91C_ID_TWI ( 9) // Two-Wire Interface\r
+#define AT91C_ID_PWMC (10) // PWM Controller\r
+#define AT91C_ID_UDP (11) // USB Device Port\r
+#define AT91C_ID_TC0 (12) // Timer Counter 0\r
+#define AT91C_ID_TC1 (13) // Timer Counter 1\r
+#define AT91C_ID_TC2 (14) // Timer Counter 2\r
+#define AT91C_ID_CAN (15) // Control Area Network Controller\r
+#define AT91C_ID_EMAC (16) // Ethernet MAC\r
+#define AT91C_ID_ADC (17) // Analog-to-Digital Converter\r
+#define AT91C_ID_AES (18) // Advanced Encryption Standard 128-bit\r
+#define AT91C_ID_TDES (19) // Triple Data Encryption Standard\r
+#define AT91C_ID_20_Reserved (20) // Reserved\r
+#define AT91C_ID_21_Reserved (21) // Reserved\r
+#define AT91C_ID_22_Reserved (22) // Reserved\r
+#define AT91C_ID_23_Reserved (23) // Reserved\r
+#define AT91C_ID_24_Reserved (24) // Reserved\r
+#define AT91C_ID_25_Reserved (25) // Reserved\r
+#define AT91C_ID_26_Reserved (26) // Reserved\r
+#define AT91C_ID_27_Reserved (27) // Reserved\r
+#define AT91C_ID_28_Reserved (28) // Reserved\r
+#define AT91C_ID_29_Reserved (29) // Reserved\r
+#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0)\r
+#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1)\r
+\r
+// *****************************************************************************\r
+// BASE ADDRESS DEFINITIONS FOR AT91SAM7X128\r
+// *****************************************************************************\r
+#define AT91C_BASE_SYS (0xFFFFF000) // (SYS) Base Address\r
+#define AT91C_BASE_AIC (0xFFFFF000) // (AIC) Base Address\r
+#define AT91C_BASE_PDC_DBGU (0xFFFFF300) // (PDC_DBGU) Base Address\r
+#define AT91C_BASE_DBGU (0xFFFFF200) // (DBGU) Base Address\r
+#define AT91C_BASE_PIOA (0xFFFFF400) // (PIOA) Base Address\r
+#define AT91C_BASE_PIOB (0xFFFFF600) // (PIOB) Base Address\r
+#define AT91C_BASE_CKGR (0xFFFFFC20) // (CKGR) Base Address\r
+#define AT91C_BASE_PMC (0xFFFFFC00) // (PMC) Base Address\r
+#define AT91C_BASE_RSTC (0xFFFFFD00) // (RSTC) Base Address\r
+#define AT91C_BASE_RTTC (0xFFFFFD20) // (RTTC) Base Address\r
+#define AT91C_BASE_PITC (0xFFFFFD30) // (PITC) Base Address\r
+#define AT91C_BASE_WDTC (0xFFFFFD40) // (WDTC) Base Address\r
+#define AT91C_BASE_VREG (0xFFFFFD60) // (VREG) Base Address\r
+#define AT91C_BASE_MC (0xFFFFFF00) // (MC) Base Address\r
+#define AT91C_BASE_PDC_SPI1 (0xFFFE4100) // (PDC_SPI1) Base Address\r
+#define AT91C_BASE_SPI1 (0xFFFE4000) // (SPI1) Base Address\r
+#define AT91C_BASE_PDC_SPI0 (0xFFFE0100) // (PDC_SPI0) Base Address\r
+#define AT91C_BASE_SPI0 (0xFFFE0000) // (SPI0) Base Address\r
+#define AT91C_BASE_PDC_US1 (0xFFFC4100) // (PDC_US1) Base Address\r
+#define AT91C_BASE_US1 (0xFFFC4000) // (US1) Base Address\r
+#define AT91C_BASE_PDC_US0 (0xFFFC0100) // (PDC_US0) Base Address\r
+#define AT91C_BASE_US0 (0xFFFC0000) // (US0) Base Address\r
+#define AT91C_BASE_PDC_SSC (0xFFFD4100) // (PDC_SSC) Base Address\r
+#define AT91C_BASE_SSC (0xFFFD4000) // (SSC) Base Address\r
+#define AT91C_BASE_TWI (0xFFFB8000) // (TWI) Base Address\r
+#define AT91C_BASE_PWMC_CH3 (0xFFFCC260) // (PWMC_CH3) Base Address\r
+#define AT91C_BASE_PWMC_CH2 (0xFFFCC240) // (PWMC_CH2) Base Address\r
+#define AT91C_BASE_PWMC_CH1 (0xFFFCC220) // (PWMC_CH1) Base Address\r
+#define AT91C_BASE_PWMC_CH0 (0xFFFCC200) // (PWMC_CH0) Base Address\r
+#define AT91C_BASE_PWMC (0xFFFCC000) // (PWMC) Base Address\r
+#define AT91C_BASE_UDP (0xFFFB0000) // (UDP) Base Address\r
+#define AT91C_BASE_TC0 (0xFFFA0000) // (TC0) Base Address\r
+#define AT91C_BASE_TC1 (0xFFFA0040) // (TC1) Base Address\r
+#define AT91C_BASE_TC2 (0xFFFA0080) // (TC2) Base Address\r
+#define AT91C_BASE_TCB (0xFFFA0000) // (TCB) Base Address\r
+#define AT91C_BASE_CAN_MB0 (0xFFFD0200) // (CAN_MB0) Base Address\r
+#define AT91C_BASE_CAN_MB1 (0xFFFD0220) // (CAN_MB1) Base Address\r
+#define AT91C_BASE_CAN_MB2 (0xFFFD0240) // (CAN_MB2) Base Address\r
+#define AT91C_BASE_CAN_MB3 (0xFFFD0260) // (CAN_MB3) Base Address\r
+#define AT91C_BASE_CAN_MB4 (0xFFFD0280) // (CAN_MB4) Base Address\r
+#define AT91C_BASE_CAN_MB5 (0xFFFD02A0) // (CAN_MB5) Base Address\r
+#define AT91C_BASE_CAN_MB6 (0xFFFD02C0) // (CAN_MB6) Base Address\r
+#define AT91C_BASE_CAN_MB7 (0xFFFD02E0) // (CAN_MB7) Base Address\r
+#define AT91C_BASE_CAN (0xFFFD0000) // (CAN) Base Address\r
+#define AT91C_BASE_EMAC (0xFFFDC000) // (EMAC) Base Address\r
+#define AT91C_BASE_PDC_ADC (0xFFFD8100) // (PDC_ADC) Base Address\r
+#define AT91C_BASE_ADC (0xFFFD8000) // (ADC) Base Address\r
+#define AT91C_BASE_PDC_AES (0xFFFA4100) // (PDC_AES) Base Address\r
+#define AT91C_BASE_AES (0xFFFA4000) // (AES) Base Address\r
+#define AT91C_BASE_PDC_TDES (0xFFFA8100) // (PDC_TDES) Base Address\r
+#define AT91C_BASE_TDES (0xFFFA8000) // (TDES) Base Address\r
+\r
+// *****************************************************************************\r
+// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X128\r
+// *****************************************************************************\r
+#define AT91C_ISRAM (0x00200000) // Internal SRAM base address\r
+#define AT91C_ISRAM_SIZE (0x00008000) // Internal SRAM size in byte (32 Kbyte)\r
+#define AT91C_IFLASH (0x00100000) // Internal ROM base address\r
+#define AT91C_IFLASH_SIZE (0x00020000) // Internal ROM size in byte (128 Kbyte)\r
+\r
+\r
--- /dev/null
+// ----------------------------------------------------------------------------\r
+// ATMEL Microcontroller Software Support - ROUSSET -\r
+// ----------------------------------------------------------------------------\r
+// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+// ----------------------------------------------------------------------------\r
+// File Name : AT91SAM7X256.h\r
+// Object : AT91SAM7X256 definitions\r
+// Generated : AT91 SW Application Group 05/20/2005 (16:22:29)\r
+// \r
+// CVS Reference : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005//\r
+// CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005//\r
+// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//\r
+// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005//\r
+// CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005//\r
+// CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//\r
+// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//\r
+// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//\r
+// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005//\r
+// CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004//\r
+// CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004//\r
+// CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004//\r
+// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005//\r
+// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005//\r
+// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//\r
+// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//\r
+// CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//\r
+// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//\r
+// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//\r
+// CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//\r
+// CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005//\r
+// CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005//\r
+// CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//\r
+// CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005//\r
+// CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005//\r
+// ----------------------------------------------------------------------------\r
+\r
+#ifndef AT91SAM7X256_H\r
+#define AT91SAM7X256_H\r
+\r
+typedef volatile unsigned int AT91_REG;// Hardware register definition\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR System Peripherals\r
+// *****************************************************************************\r
+typedef struct _AT91S_SYS {\r
+ AT91_REG AIC_SMR[32]; // Source Mode Register\r
+ AT91_REG AIC_SVR[32]; // Source Vector Register\r
+ AT91_REG AIC_IVR; // IRQ Vector Register\r
+ AT91_REG AIC_FVR; // FIQ Vector Register\r
+ AT91_REG AIC_ISR; // Interrupt Status Register\r
+ AT91_REG AIC_IPR; // Interrupt Pending Register\r
+ AT91_REG AIC_IMR; // Interrupt Mask Register\r
+ AT91_REG AIC_CISR; // Core Interrupt Status Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG AIC_IECR; // Interrupt Enable Command Register\r
+ AT91_REG AIC_IDCR; // Interrupt Disable Command Register\r
+ AT91_REG AIC_ICCR; // Interrupt Clear Command Register\r
+ AT91_REG AIC_ISCR; // Interrupt Set Command Register\r
+ AT91_REG AIC_EOICR; // End of Interrupt Command Register\r
+ AT91_REG AIC_SPU; // Spurious Vector Register\r
+ AT91_REG AIC_DCR; // Debug Control Register (Protect)\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG AIC_FFER; // Fast Forcing Enable Register\r
+ AT91_REG AIC_FFDR; // Fast Forcing Disable Register\r
+ AT91_REG AIC_FFSR; // Fast Forcing Status Register\r
+ AT91_REG Reserved2[45]; // \r
+ AT91_REG DBGU_CR; // Control Register\r
+ AT91_REG DBGU_MR; // Mode Register\r
+ AT91_REG DBGU_IER; // Interrupt Enable Register\r
+ AT91_REG DBGU_IDR; // Interrupt Disable Register\r
+ AT91_REG DBGU_IMR; // Interrupt Mask Register\r
+ AT91_REG DBGU_CSR; // Channel Status Register\r
+ AT91_REG DBGU_RHR; // Receiver Holding Register\r
+ AT91_REG DBGU_THR; // Transmitter Holding Register\r
+ AT91_REG DBGU_BRGR; // Baud Rate Generator Register\r
+ AT91_REG Reserved3[7]; // \r
+ AT91_REG DBGU_CIDR; // Chip ID Register\r
+ AT91_REG DBGU_EXID; // Chip ID Extension Register\r
+ AT91_REG DBGU_FNTR; // Force NTRST Register\r
+ AT91_REG Reserved4[45]; // \r
+ AT91_REG DBGU_RPR; // Receive Pointer Register\r
+ AT91_REG DBGU_RCR; // Receive Counter Register\r
+ AT91_REG DBGU_TPR; // Transmit Pointer Register\r
+ AT91_REG DBGU_TCR; // Transmit Counter Register\r
+ AT91_REG DBGU_RNPR; // Receive Next Pointer Register\r
+ AT91_REG DBGU_RNCR; // Receive Next Counter Register\r
+ AT91_REG DBGU_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG DBGU_TNCR; // Transmit Next Counter Register\r
+ AT91_REG DBGU_PTCR; // PDC Transfer Control Register\r
+ AT91_REG DBGU_PTSR; // PDC Transfer Status Register\r
+ AT91_REG Reserved5[54]; // \r
+ AT91_REG PIOA_PER; // PIO Enable Register\r
+ AT91_REG PIOA_PDR; // PIO Disable Register\r
+ AT91_REG PIOA_PSR; // PIO Status Register\r
+ AT91_REG Reserved6[1]; // \r
+ AT91_REG PIOA_OER; // Output Enable Register\r
+ AT91_REG PIOA_ODR; // Output Disable Registerr\r
+ AT91_REG PIOA_OSR; // Output Status Register\r
+ AT91_REG Reserved7[1]; // \r
+ AT91_REG PIOA_IFER; // Input Filter Enable Register\r
+ AT91_REG PIOA_IFDR; // Input Filter Disable Register\r
+ AT91_REG PIOA_IFSR; // Input Filter Status Register\r
+ AT91_REG Reserved8[1]; // \r
+ AT91_REG PIOA_SODR; // Set Output Data Register\r
+ AT91_REG PIOA_CODR; // Clear Output Data Register\r
+ AT91_REG PIOA_ODSR; // Output Data Status Register\r
+ AT91_REG PIOA_PDSR; // Pin Data Status Register\r
+ AT91_REG PIOA_IER; // Interrupt Enable Register\r
+ AT91_REG PIOA_IDR; // Interrupt Disable Register\r
+ AT91_REG PIOA_IMR; // Interrupt Mask Register\r
+ AT91_REG PIOA_ISR; // Interrupt Status Register\r
+ AT91_REG PIOA_MDER; // Multi-driver Enable Register\r
+ AT91_REG PIOA_MDDR; // Multi-driver Disable Register\r
+ AT91_REG PIOA_MDSR; // Multi-driver Status Register\r
+ AT91_REG Reserved9[1]; // \r
+ AT91_REG PIOA_PPUDR; // Pull-up Disable Register\r
+ AT91_REG PIOA_PPUER; // Pull-up Enable Register\r
+ AT91_REG PIOA_PPUSR; // Pull-up Status Register\r
+ AT91_REG Reserved10[1]; // \r
+ AT91_REG PIOA_ASR; // Select A Register\r
+ AT91_REG PIOA_BSR; // Select B Register\r
+ AT91_REG PIOA_ABSR; // AB Select Status Register\r
+ AT91_REG Reserved11[9]; // \r
+ AT91_REG PIOA_OWER; // Output Write Enable Register\r
+ AT91_REG PIOA_OWDR; // Output Write Disable Register\r
+ AT91_REG PIOA_OWSR; // Output Write Status Register\r
+ AT91_REG Reserved12[85]; // \r
+ AT91_REG PIOB_PER; // PIO Enable Register\r
+ AT91_REG PIOB_PDR; // PIO Disable Register\r
+ AT91_REG PIOB_PSR; // PIO Status Register\r
+ AT91_REG Reserved13[1]; // \r
+ AT91_REG PIOB_OER; // Output Enable Register\r
+ AT91_REG PIOB_ODR; // Output Disable Registerr\r
+ AT91_REG PIOB_OSR; // Output Status Register\r
+ AT91_REG Reserved14[1]; // \r
+ AT91_REG PIOB_IFER; // Input Filter Enable Register\r
+ AT91_REG PIOB_IFDR; // Input Filter Disable Register\r
+ AT91_REG PIOB_IFSR; // Input Filter Status Register\r
+ AT91_REG Reserved15[1]; // \r
+ AT91_REG PIOB_SODR; // Set Output Data Register\r
+ AT91_REG PIOB_CODR; // Clear Output Data Register\r
+ AT91_REG PIOB_ODSR; // Output Data Status Register\r
+ AT91_REG PIOB_PDSR; // Pin Data Status Register\r
+ AT91_REG PIOB_IER; // Interrupt Enable Register\r
+ AT91_REG PIOB_IDR; // Interrupt Disable Register\r
+ AT91_REG PIOB_IMR; // Interrupt Mask Register\r
+ AT91_REG PIOB_ISR; // Interrupt Status Register\r
+ AT91_REG PIOB_MDER; // Multi-driver Enable Register\r
+ AT91_REG PIOB_MDDR; // Multi-driver Disable Register\r
+ AT91_REG PIOB_MDSR; // Multi-driver Status Register\r
+ AT91_REG Reserved16[1]; // \r
+ AT91_REG PIOB_PPUDR; // Pull-up Disable Register\r
+ AT91_REG PIOB_PPUER; // Pull-up Enable Register\r
+ AT91_REG PIOB_PPUSR; // Pull-up Status Register\r
+ AT91_REG Reserved17[1]; // \r
+ AT91_REG PIOB_ASR; // Select A Register\r
+ AT91_REG PIOB_BSR; // Select B Register\r
+ AT91_REG PIOB_ABSR; // AB Select Status Register\r
+ AT91_REG Reserved18[9]; // \r
+ AT91_REG PIOB_OWER; // Output Write Enable Register\r
+ AT91_REG PIOB_OWDR; // Output Write Disable Register\r
+ AT91_REG PIOB_OWSR; // Output Write Status Register\r
+ AT91_REG Reserved19[341]; // \r
+ AT91_REG PMC_SCER; // System Clock Enable Register\r
+ AT91_REG PMC_SCDR; // System Clock Disable Register\r
+ AT91_REG PMC_SCSR; // System Clock Status Register\r
+ AT91_REG Reserved20[1]; // \r
+ AT91_REG PMC_PCER; // Peripheral Clock Enable Register\r
+ AT91_REG PMC_PCDR; // Peripheral Clock Disable Register\r
+ AT91_REG PMC_PCSR; // Peripheral Clock Status Register\r
+ AT91_REG Reserved21[1]; // \r
+ AT91_REG PMC_MOR; // Main Oscillator Register\r
+ AT91_REG PMC_MCFR; // Main Clock Frequency Register\r
+ AT91_REG Reserved22[1]; // \r
+ AT91_REG PMC_PLLR; // PLL Register\r
+ AT91_REG PMC_MCKR; // Master Clock Register\r
+ AT91_REG Reserved23[3]; // \r
+ AT91_REG PMC_PCKR[4]; // Programmable Clock Register\r
+ AT91_REG Reserved24[4]; // \r
+ AT91_REG PMC_IER; // Interrupt Enable Register\r
+ AT91_REG PMC_IDR; // Interrupt Disable Register\r
+ AT91_REG PMC_SR; // Status Register\r
+ AT91_REG PMC_IMR; // Interrupt Mask Register\r
+ AT91_REG Reserved25[36]; // \r
+ AT91_REG RSTC_RCR; // Reset Control Register\r
+ AT91_REG RSTC_RSR; // Reset Status Register\r
+ AT91_REG RSTC_RMR; // Reset Mode Register\r
+ AT91_REG Reserved26[5]; // \r
+ AT91_REG RTTC_RTMR; // Real-time Mode Register\r
+ AT91_REG RTTC_RTAR; // Real-time Alarm Register\r
+ AT91_REG RTTC_RTVR; // Real-time Value Register\r
+ AT91_REG RTTC_RTSR; // Real-time Status Register\r
+ AT91_REG PITC_PIMR; // Period Interval Mode Register\r
+ AT91_REG PITC_PISR; // Period Interval Status Register\r
+ AT91_REG PITC_PIVR; // Period Interval Value Register\r
+ AT91_REG PITC_PIIR; // Period Interval Image Register\r
+ AT91_REG WDTC_WDCR; // Watchdog Control Register\r
+ AT91_REG WDTC_WDMR; // Watchdog Mode Register\r
+ AT91_REG WDTC_WDSR; // Watchdog Status Register\r
+ AT91_REG Reserved27[5]; // \r
+ AT91_REG VREG_MR; // Voltage Regulator Mode Register\r
+} AT91S_SYS, *AT91PS_SYS;\r
+\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller\r
+// *****************************************************************************\r
+typedef struct _AT91S_AIC {\r
+ AT91_REG AIC_SMR[32]; // Source Mode Register\r
+ AT91_REG AIC_SVR[32]; // Source Vector Register\r
+ AT91_REG AIC_IVR; // IRQ Vector Register\r
+ AT91_REG AIC_FVR; // FIQ Vector Register\r
+ AT91_REG AIC_ISR; // Interrupt Status Register\r
+ AT91_REG AIC_IPR; // Interrupt Pending Register\r
+ AT91_REG AIC_IMR; // Interrupt Mask Register\r
+ AT91_REG AIC_CISR; // Core Interrupt Status Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG AIC_IECR; // Interrupt Enable Command Register\r
+ AT91_REG AIC_IDCR; // Interrupt Disable Command Register\r
+ AT91_REG AIC_ICCR; // Interrupt Clear Command Register\r
+ AT91_REG AIC_ISCR; // Interrupt Set Command Register\r
+ AT91_REG AIC_EOICR; // End of Interrupt Command Register\r
+ AT91_REG AIC_SPU; // Spurious Vector Register\r
+ AT91_REG AIC_DCR; // Debug Control Register (Protect)\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG AIC_FFER; // Fast Forcing Enable Register\r
+ AT91_REG AIC_FFDR; // Fast Forcing Disable Register\r
+ AT91_REG AIC_FFSR; // Fast Forcing Status Register\r
+} AT91S_AIC, *AT91PS_AIC;\r
+\r
+// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- \r
+#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level\r
+#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level\r
+#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level\r
+#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type\r
+#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive\r
+#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ((unsigned int) 0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive\r
+#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered\r
+#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered\r
+#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive\r
+#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered\r
+// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- \r
+#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status\r
+#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status\r
+// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- \r
+#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode\r
+#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Peripheral DMA Controller\r
+// *****************************************************************************\r
+typedef struct _AT91S_PDC {\r
+ AT91_REG PDC_RPR; // Receive Pointer Register\r
+ AT91_REG PDC_RCR; // Receive Counter Register\r
+ AT91_REG PDC_TPR; // Transmit Pointer Register\r
+ AT91_REG PDC_TCR; // Transmit Counter Register\r
+ AT91_REG PDC_RNPR; // Receive Next Pointer Register\r
+ AT91_REG PDC_RNCR; // Receive Next Counter Register\r
+ AT91_REG PDC_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG PDC_TNCR; // Transmit Next Counter Register\r
+ AT91_REG PDC_PTCR; // PDC Transfer Control Register\r
+ AT91_REG PDC_PTSR; // PDC Transfer Status Register\r
+} AT91S_PDC, *AT91PS_PDC;\r
+\r
+// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- \r
+#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable\r
+#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable\r
+#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable\r
+#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable\r
+// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Debug Unit\r
+// *****************************************************************************\r
+typedef struct _AT91S_DBGU {\r
+ AT91_REG DBGU_CR; // Control Register\r
+ AT91_REG DBGU_MR; // Mode Register\r
+ AT91_REG DBGU_IER; // Interrupt Enable Register\r
+ AT91_REG DBGU_IDR; // Interrupt Disable Register\r
+ AT91_REG DBGU_IMR; // Interrupt Mask Register\r
+ AT91_REG DBGU_CSR; // Channel Status Register\r
+ AT91_REG DBGU_RHR; // Receiver Holding Register\r
+ AT91_REG DBGU_THR; // Transmitter Holding Register\r
+ AT91_REG DBGU_BRGR; // Baud Rate Generator Register\r
+ AT91_REG Reserved0[7]; // \r
+ AT91_REG DBGU_CIDR; // Chip ID Register\r
+ AT91_REG DBGU_EXID; // Chip ID Extension Register\r
+ AT91_REG DBGU_FNTR; // Force NTRST Register\r
+ AT91_REG Reserved1[45]; // \r
+ AT91_REG DBGU_RPR; // Receive Pointer Register\r
+ AT91_REG DBGU_RCR; // Receive Counter Register\r
+ AT91_REG DBGU_TPR; // Transmit Pointer Register\r
+ AT91_REG DBGU_TCR; // Transmit Counter Register\r
+ AT91_REG DBGU_RNPR; // Receive Next Pointer Register\r
+ AT91_REG DBGU_RNCR; // Receive Next Counter Register\r
+ AT91_REG DBGU_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG DBGU_TNCR; // Transmit Next Counter Register\r
+ AT91_REG DBGU_PTCR; // PDC Transfer Control Register\r
+ AT91_REG DBGU_PTSR; // PDC Transfer Status Register\r
+} AT91S_DBGU, *AT91PS_DBGU;\r
+\r
+// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- \r
+#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver\r
+#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter\r
+#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable\r
+#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable\r
+#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable\r
+#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable\r
+#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits\r
+// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- \r
+#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type\r
+#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity\r
+#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity\r
+#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space)\r
+#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark)\r
+#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity\r
+#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode\r
+#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode\r
+#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.\r
+#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.\r
+#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.\r
+#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.\r
+// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- \r
+#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt\r
+#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt\r
+#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt\r
+#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt\r
+#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt\r
+#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt\r
+#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt\r
+#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt\r
+#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt\r
+#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt\r
+#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt\r
+#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt\r
+// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- \r
+// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- \r
+// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- \r
+// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- \r
+#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Parallel Input Output Controler\r
+// *****************************************************************************\r
+typedef struct _AT91S_PIO {\r
+ AT91_REG PIO_PER; // PIO Enable Register\r
+ AT91_REG PIO_PDR; // PIO Disable Register\r
+ AT91_REG PIO_PSR; // PIO Status Register\r
+ AT91_REG Reserved0[1]; // \r
+ AT91_REG PIO_OER; // Output Enable Register\r
+ AT91_REG PIO_ODR; // Output Disable Registerr\r
+ AT91_REG PIO_OSR; // Output Status Register\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG PIO_IFER; // Input Filter Enable Register\r
+ AT91_REG PIO_IFDR; // Input Filter Disable Register\r
+ AT91_REG PIO_IFSR; // Input Filter Status Register\r
+ AT91_REG Reserved2[1]; // \r
+ AT91_REG PIO_SODR; // Set Output Data Register\r
+ AT91_REG PIO_CODR; // Clear Output Data Register\r
+ AT91_REG PIO_ODSR; // Output Data Status Register\r
+ AT91_REG PIO_PDSR; // Pin Data Status Register\r
+ AT91_REG PIO_IER; // Interrupt Enable Register\r
+ AT91_REG PIO_IDR; // Interrupt Disable Register\r
+ AT91_REG PIO_IMR; // Interrupt Mask Register\r
+ AT91_REG PIO_ISR; // Interrupt Status Register\r
+ AT91_REG PIO_MDER; // Multi-driver Enable Register\r
+ AT91_REG PIO_MDDR; // Multi-driver Disable Register\r
+ AT91_REG PIO_MDSR; // Multi-driver Status Register\r
+ AT91_REG Reserved3[1]; // \r
+ AT91_REG PIO_PPUDR; // Pull-up Disable Register\r
+ AT91_REG PIO_PPUER; // Pull-up Enable Register\r
+ AT91_REG PIO_PPUSR; // Pull-up Status Register\r
+ AT91_REG Reserved4[1]; // \r
+ AT91_REG PIO_ASR; // Select A Register\r
+ AT91_REG PIO_BSR; // Select B Register\r
+ AT91_REG PIO_ABSR; // AB Select Status Register\r
+ AT91_REG Reserved5[9]; // \r
+ AT91_REG PIO_OWER; // Output Write Enable Register\r
+ AT91_REG PIO_OWDR; // Output Write Disable Register\r
+ AT91_REG PIO_OWSR; // Output Write Status Register\r
+} AT91S_PIO, *AT91PS_PIO;\r
+\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Clock Generator Controler\r
+// *****************************************************************************\r
+typedef struct _AT91S_CKGR {\r
+ AT91_REG CKGR_MOR; // Main Oscillator Register\r
+ AT91_REG CKGR_MCFR; // Main Clock Frequency Register\r
+ AT91_REG Reserved0[1]; // \r
+ AT91_REG CKGR_PLLR; // PLL Register\r
+} AT91S_CKGR, *AT91PS_CKGR;\r
+\r
+// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- \r
+#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable\r
+#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass\r
+#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time\r
+// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- \r
+#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency\r
+#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready\r
+// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- \r
+#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected\r
+#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0\r
+#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed\r
+#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter\r
+#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range\r
+#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet\r
+#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet\r
+#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet\r
+#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet\r
+#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier\r
+#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks\r
+#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output\r
+#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2\r
+#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Power Management Controler\r
+// *****************************************************************************\r
+typedef struct _AT91S_PMC {\r
+ AT91_REG PMC_SCER; // System Clock Enable Register\r
+ AT91_REG PMC_SCDR; // System Clock Disable Register\r
+ AT91_REG PMC_SCSR; // System Clock Status Register\r
+ AT91_REG Reserved0[1]; // \r
+ AT91_REG PMC_PCER; // Peripheral Clock Enable Register\r
+ AT91_REG PMC_PCDR; // Peripheral Clock Disable Register\r
+ AT91_REG PMC_PCSR; // Peripheral Clock Status Register\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG PMC_MOR; // Main Oscillator Register\r
+ AT91_REG PMC_MCFR; // Main Clock Frequency Register\r
+ AT91_REG Reserved2[1]; // \r
+ AT91_REG PMC_PLLR; // PLL Register\r
+ AT91_REG PMC_MCKR; // Master Clock Register\r
+ AT91_REG Reserved3[3]; // \r
+ AT91_REG PMC_PCKR[4]; // Programmable Clock Register\r
+ AT91_REG Reserved4[4]; // \r
+ AT91_REG PMC_IER; // Interrupt Enable Register\r
+ AT91_REG PMC_IDR; // Interrupt Disable Register\r
+ AT91_REG PMC_SR; // Status Register\r
+ AT91_REG PMC_IMR; // Interrupt Mask Register\r
+} AT91S_PMC, *AT91PS_PMC;\r
+\r
+// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- \r
+#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock\r
+#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock\r
+#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output\r
+#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output\r
+#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output\r
+#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output\r
+// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- \r
+// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- \r
+// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- \r
+// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- \r
+// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- \r
+// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- \r
+#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection\r
+#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected\r
+#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected\r
+#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected\r
+#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler\r
+#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock\r
+#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2\r
+#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4\r
+#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8\r
+#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16\r
+#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32\r
+#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64\r
+// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- \r
+// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- \r
+#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask\r
+#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask\r
+#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask\r
+// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- \r
+// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- \r
+// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Reset Controller Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_RSTC {\r
+ AT91_REG RSTC_RCR; // Reset Control Register\r
+ AT91_REG RSTC_RSR; // Reset Status Register\r
+ AT91_REG RSTC_RMR; // Reset Mode Register\r
+} AT91S_RSTC, *AT91PS_RSTC;\r
+\r
+// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- \r
+#define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset\r
+#define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset\r
+#define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset\r
+#define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password\r
+// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- \r
+#define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status\r
+#define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status\r
+#define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type\r
+#define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising.\r
+#define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising.\r
+#define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.\r
+#define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.\r
+#define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low.\r
+#define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured.\r
+#define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level\r
+#define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress.\r
+// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- \r
+#define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable\r
+#define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable\r
+#define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable\r
+#define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_RTTC {\r
+ AT91_REG RTTC_RTMR; // Real-time Mode Register\r
+ AT91_REG RTTC_RTAR; // Real-time Alarm Register\r
+ AT91_REG RTTC_RTVR; // Real-time Value Register\r
+ AT91_REG RTTC_RTSR; // Real-time Status Register\r
+} AT91S_RTTC, *AT91PS_RTTC;\r
+\r
+// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- \r
+#define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value\r
+#define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable\r
+#define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable\r
+#define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart\r
+// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- \r
+#define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value\r
+// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- \r
+#define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value\r
+// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- \r
+#define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status\r
+#define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_PITC {\r
+ AT91_REG PITC_PIMR; // Period Interval Mode Register\r
+ AT91_REG PITC_PISR; // Period Interval Status Register\r
+ AT91_REG PITC_PIVR; // Period Interval Value Register\r
+ AT91_REG PITC_PIIR; // Period Interval Image Register\r
+} AT91S_PITC, *AT91PS_PITC;\r
+\r
+// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- \r
+#define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value\r
+#define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled\r
+#define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable\r
+// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- \r
+#define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status\r
+// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- \r
+#define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value\r
+#define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter\r
+// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_WDTC {\r
+ AT91_REG WDTC_WDCR; // Watchdog Control Register\r
+ AT91_REG WDTC_WDMR; // Watchdog Mode Register\r
+ AT91_REG WDTC_WDSR; // Watchdog Status Register\r
+} AT91S_WDTC, *AT91PS_WDTC;\r
+\r
+// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- \r
+#define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart\r
+#define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password\r
+// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- \r
+#define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart\r
+#define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable\r
+#define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable\r
+#define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart\r
+#define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable\r
+#define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value\r
+#define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt\r
+#define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt\r
+// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- \r
+#define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow\r
+#define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_VREG {\r
+ AT91_REG VREG_MR; // Voltage Regulator Mode Register\r
+} AT91S_VREG, *AT91PS_VREG;\r
+\r
+// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- \r
+#define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Memory Controller Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_MC {\r
+ AT91_REG MC_RCR; // MC Remap Control Register\r
+ AT91_REG MC_ASR; // MC Abort Status Register\r
+ AT91_REG MC_AASR; // MC Abort Address Status Register\r
+ AT91_REG Reserved0[21]; // \r
+ AT91_REG MC_FMR; // MC Flash Mode Register\r
+ AT91_REG MC_FCR; // MC Flash Command Register\r
+ AT91_REG MC_FSR; // MC Flash Status Register\r
+} AT91S_MC, *AT91PS_MC;\r
+\r
+// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- \r
+#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit\r
+// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- \r
+#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status\r
+#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status\r
+#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status\r
+#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte\r
+#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word\r
+#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word\r
+#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status\r
+#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read\r
+#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write\r
+#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch\r
+#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source\r
+#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source\r
+#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source\r
+#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source\r
+// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- \r
+#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready\r
+#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error\r
+#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error\r
+#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming\r
+#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State\r
+#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations\r
+#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations\r
+#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations\r
+#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations\r
+#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number\r
+// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- \r
+#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command\r
+#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN.\r
+#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.\r
+#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.\r
+#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.\r
+#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.\r
+#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits.\r
+#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits.\r
+#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit.\r
+#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number\r
+#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key\r
+// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- \r
+#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status\r
+#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status\r
+#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status\r
+#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status\r
+#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status\r
+#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status\r
+#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status\r
+#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status\r
+#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status\r
+#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status\r
+#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status\r
+#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status\r
+#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status\r
+#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status\r
+#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status\r
+#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status\r
+#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status\r
+#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status\r
+#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status\r
+#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status\r
+#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status\r
+#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status\r
+#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status\r
+#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status\r
+#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Serial Parallel Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_SPI {\r
+ AT91_REG SPI_CR; // Control Register\r
+ AT91_REG SPI_MR; // Mode Register\r
+ AT91_REG SPI_RDR; // Receive Data Register\r
+ AT91_REG SPI_TDR; // Transmit Data Register\r
+ AT91_REG SPI_SR; // Status Register\r
+ AT91_REG SPI_IER; // Interrupt Enable Register\r
+ AT91_REG SPI_IDR; // Interrupt Disable Register\r
+ AT91_REG SPI_IMR; // Interrupt Mask Register\r
+ AT91_REG Reserved0[4]; // \r
+ AT91_REG SPI_CSR[4]; // Chip Select Register\r
+ AT91_REG Reserved1[48]; // \r
+ AT91_REG SPI_RPR; // Receive Pointer Register\r
+ AT91_REG SPI_RCR; // Receive Counter Register\r
+ AT91_REG SPI_TPR; // Transmit Pointer Register\r
+ AT91_REG SPI_TCR; // Transmit Counter Register\r
+ AT91_REG SPI_RNPR; // Receive Next Pointer Register\r
+ AT91_REG SPI_RNCR; // Receive Next Counter Register\r
+ AT91_REG SPI_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG SPI_TNCR; // Transmit Next Counter Register\r
+ AT91_REG SPI_PTCR; // PDC Transfer Control Register\r
+ AT91_REG SPI_PTSR; // PDC Transfer Status Register\r
+} AT91S_SPI, *AT91PS_SPI;\r
+\r
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- \r
+#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable\r
+#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable\r
+#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset\r
+#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer\r
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- \r
+#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode\r
+#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select\r
+#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select\r
+#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select\r
+#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode\r
+#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection\r
+#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection\r
+#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection\r
+#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select\r
+#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects\r
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- \r
+#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data\r
+#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status\r
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- \r
+#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data\r
+#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status\r
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- \r
+#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full\r
+#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty\r
+#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error\r
+#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status\r
+#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer\r
+#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer\r
+#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt\r
+#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt\r
+#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt\r
+#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt\r
+#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status\r
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- \r
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- \r
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- \r
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- \r
+#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity\r
+#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase\r
+#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer\r
+#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer\r
+#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer\r
+#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer\r
+#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer\r
+#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer\r
+#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer\r
+#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer\r
+#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer\r
+#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer\r
+#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer\r
+#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate\r
+#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK\r
+#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Usart\r
+// *****************************************************************************\r
+typedef struct _AT91S_USART {\r
+ AT91_REG US_CR; // Control Register\r
+ AT91_REG US_MR; // Mode Register\r
+ AT91_REG US_IER; // Interrupt Enable Register\r
+ AT91_REG US_IDR; // Interrupt Disable Register\r
+ AT91_REG US_IMR; // Interrupt Mask Register\r
+ AT91_REG US_CSR; // Channel Status Register\r
+ AT91_REG US_RHR; // Receiver Holding Register\r
+ AT91_REG US_THR; // Transmitter Holding Register\r
+ AT91_REG US_BRGR; // Baud Rate Generator Register\r
+ AT91_REG US_RTOR; // Receiver Time-out Register\r
+ AT91_REG US_TTGR; // Transmitter Time-guard Register\r
+ AT91_REG Reserved0[5]; // \r
+ AT91_REG US_FIDI; // FI_DI_Ratio Register\r
+ AT91_REG US_NER; // Nb Errors Register\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG US_IF; // IRDA_FILTER Register\r
+ AT91_REG Reserved2[44]; // \r
+ AT91_REG US_RPR; // Receive Pointer Register\r
+ AT91_REG US_RCR; // Receive Counter Register\r
+ AT91_REG US_TPR; // Transmit Pointer Register\r
+ AT91_REG US_TCR; // Transmit Counter Register\r
+ AT91_REG US_RNPR; // Receive Next Pointer Register\r
+ AT91_REG US_RNCR; // Receive Next Counter Register\r
+ AT91_REG US_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG US_TNCR; // Transmit Next Counter Register\r
+ AT91_REG US_PTCR; // PDC Transfer Control Register\r
+ AT91_REG US_PTSR; // PDC Transfer Status Register\r
+} AT91S_USART, *AT91PS_USART;\r
+\r
+// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- \r
+#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break\r
+#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break\r
+#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out\r
+#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address\r
+#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations\r
+#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge\r
+#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out\r
+#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable\r
+#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable\r
+#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable\r
+#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable\r
+// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- \r
+#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode\r
+#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal\r
+#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485\r
+#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking\r
+#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem\r
+#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0\r
+#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1\r
+#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA\r
+#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking\r
+#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock\r
+#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock\r
+#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1\r
+#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM)\r
+#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK)\r
+#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock\r
+#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits\r
+#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits\r
+#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits\r
+#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits\r
+#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select\r
+#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits\r
+#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit\r
+#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits\r
+#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits\r
+#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order\r
+#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length\r
+#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select\r
+#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode\r
+#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge\r
+#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK\r
+#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions\r
+#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter\r
+// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- \r
+#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break\r
+#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out\r
+#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached\r
+#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge\r
+#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag\r
+#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag\r
+#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag\r
+#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag\r
+// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- \r
+// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- \r
+// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- \r
+#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input\r
+#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input\r
+#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input\r
+#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_SSC {\r
+ AT91_REG SSC_CR; // Control Register\r
+ AT91_REG SSC_CMR; // Clock Mode Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG SSC_RCMR; // Receive Clock ModeRegister\r
+ AT91_REG SSC_RFMR; // Receive Frame Mode Register\r
+ AT91_REG SSC_TCMR; // Transmit Clock Mode Register\r
+ AT91_REG SSC_TFMR; // Transmit Frame Mode Register\r
+ AT91_REG SSC_RHR; // Receive Holding Register\r
+ AT91_REG SSC_THR; // Transmit Holding Register\r
+ AT91_REG Reserved1[2]; // \r
+ AT91_REG SSC_RSHR; // Receive Sync Holding Register\r
+ AT91_REG SSC_TSHR; // Transmit Sync Holding Register\r
+ AT91_REG Reserved2[2]; // \r
+ AT91_REG SSC_SR; // Status Register\r
+ AT91_REG SSC_IER; // Interrupt Enable Register\r
+ AT91_REG SSC_IDR; // Interrupt Disable Register\r
+ AT91_REG SSC_IMR; // Interrupt Mask Register\r
+ AT91_REG Reserved3[44]; // \r
+ AT91_REG SSC_RPR; // Receive Pointer Register\r
+ AT91_REG SSC_RCR; // Receive Counter Register\r
+ AT91_REG SSC_TPR; // Transmit Pointer Register\r
+ AT91_REG SSC_TCR; // Transmit Counter Register\r
+ AT91_REG SSC_RNPR; // Receive Next Pointer Register\r
+ AT91_REG SSC_RNCR; // Receive Next Counter Register\r
+ AT91_REG SSC_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG SSC_TNCR; // Transmit Next Counter Register\r
+ AT91_REG SSC_PTCR; // PDC Transfer Control Register\r
+ AT91_REG SSC_PTSR; // PDC Transfer Status Register\r
+} AT91S_SSC, *AT91PS_SSC;\r
+\r
+// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- \r
+#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable\r
+#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable\r
+#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable\r
+#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable\r
+#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset\r
+// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- \r
+#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection\r
+#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock\r
+#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal\r
+#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin\r
+#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection\r
+#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only\r
+#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output\r
+#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output\r
+#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion\r
+#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection\r
+#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.\r
+#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start\r
+#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input\r
+#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input\r
+#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input\r
+#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input\r
+#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input\r
+#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input\r
+#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0\r
+#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay\r
+#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection\r
+// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- \r
+#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length\r
+#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode\r
+#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First\r
+#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame\r
+#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length\r
+#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection\r
+#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only\r
+#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse\r
+#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse\r
+#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer\r
+#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer\r
+#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer\r
+#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection\r
+// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- \r
+// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- \r
+#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value\r
+#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable\r
+// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- \r
+#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready\r
+#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty\r
+#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission\r
+#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty\r
+#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready\r
+#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun\r
+#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception\r
+#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full\r
+#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync\r
+#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync\r
+#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable\r
+#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable\r
+// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- \r
+// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- \r
+// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Two-wire Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_TWI {\r
+ AT91_REG TWI_CR; // Control Register\r
+ AT91_REG TWI_MMR; // Master Mode Register\r
+ AT91_REG Reserved0[1]; // \r
+ AT91_REG TWI_IADR; // Internal Address Register\r
+ AT91_REG TWI_CWGR; // Clock Waveform Generator Register\r
+ AT91_REG Reserved1[3]; // \r
+ AT91_REG TWI_SR; // Status Register\r
+ AT91_REG TWI_IER; // Interrupt Enable Register\r
+ AT91_REG TWI_IDR; // Interrupt Disable Register\r
+ AT91_REG TWI_IMR; // Interrupt Mask Register\r
+ AT91_REG TWI_RHR; // Receive Holding Register\r
+ AT91_REG TWI_THR; // Transmit Holding Register\r
+} AT91S_TWI, *AT91PS_TWI;\r
+\r
+// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- \r
+#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition\r
+#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition\r
+#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled\r
+#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled\r
+#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset\r
+// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- \r
+#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size\r
+#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address\r
+#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address\r
+#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address\r
+#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address\r
+#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction\r
+#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address\r
+// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- \r
+#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider\r
+#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider\r
+#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider\r
+// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- \r
+#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed\r
+#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY\r
+#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY\r
+#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error\r
+#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error\r
+#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged\r
+// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- \r
+// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- \r
+// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR PWMC Channel Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_PWMC_CH {\r
+ AT91_REG PWMC_CMR; // Channel Mode Register\r
+ AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register\r
+ AT91_REG PWMC_CPRDR; // Channel Period Register\r
+ AT91_REG PWMC_CCNTR; // Channel Counter Register\r
+ AT91_REG PWMC_CUPDR; // Channel Update Register\r
+ AT91_REG PWMC_Reserved[3]; // Reserved\r
+} AT91S_PWMC_CH, *AT91PS_PWMC_CH;\r
+\r
+// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- \r
+#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx\r
+#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH) \r
+#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH) \r
+#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH) \r
+#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment\r
+#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity\r
+#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period\r
+// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- \r
+#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle\r
+// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- \r
+#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period\r
+// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- \r
+#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter\r
+// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- \r
+#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_PWMC {\r
+ AT91_REG PWMC_MR; // PWMC Mode Register\r
+ AT91_REG PWMC_ENA; // PWMC Enable Register\r
+ AT91_REG PWMC_DIS; // PWMC Disable Register\r
+ AT91_REG PWMC_SR; // PWMC Status Register\r
+ AT91_REG PWMC_IER; // PWMC Interrupt Enable Register\r
+ AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register\r
+ AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register\r
+ AT91_REG PWMC_ISR; // PWMC Interrupt Status Register\r
+ AT91_REG Reserved0[55]; // \r
+ AT91_REG PWMC_VR; // PWMC Version Register\r
+ AT91_REG Reserved1[64]; // \r
+ AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel\r
+} AT91S_PWMC, *AT91PS_PWMC;\r
+\r
+// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- \r
+#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor.\r
+#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A\r
+#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC) \r
+#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor.\r
+#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B\r
+#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC) \r
+// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- \r
+#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0\r
+#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1\r
+#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2\r
+#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3\r
+// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- \r
+// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- \r
+// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- \r
+// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- \r
+// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- \r
+// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR USB Device Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_UDP {\r
+ AT91_REG UDP_NUM; // Frame Number Register\r
+ AT91_REG UDP_GLBSTATE; // Global State Register\r
+ AT91_REG UDP_FADDR; // Function Address Register\r
+ AT91_REG Reserved0[1]; // \r
+ AT91_REG UDP_IER; // Interrupt Enable Register\r
+ AT91_REG UDP_IDR; // Interrupt Disable Register\r
+ AT91_REG UDP_IMR; // Interrupt Mask Register\r
+ AT91_REG UDP_ISR; // Interrupt Status Register\r
+ AT91_REG UDP_ICR; // Interrupt Clear Register\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG UDP_RSTEP; // Reset Endpoint Register\r
+ AT91_REG Reserved2[1]; // \r
+ AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register\r
+ AT91_REG Reserved3[2]; // \r
+ AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register\r
+ AT91_REG Reserved4[3]; // \r
+ AT91_REG UDP_TXVC; // Transceiver Control Register\r
+} AT91S_UDP, *AT91PS_UDP;\r
+\r
+// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- \r
+#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats\r
+#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error\r
+#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK\r
+// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- \r
+#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable\r
+#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured\r
+#define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume\r
+#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host\r
+#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable\r
+// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- \r
+#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value\r
+#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable\r
+// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- \r
+#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt\r
+#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt\r
+#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt\r
+#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt\r
+#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt\r
+#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt\r
+#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt\r
+#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt\r
+#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt\r
+#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt\r
+#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt\r
+// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- \r
+// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- \r
+// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- \r
+#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt\r
+// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- \r
+// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- \r
+#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0\r
+#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1\r
+#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2\r
+#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3\r
+#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4\r
+#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5\r
+// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- \r
+#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR\r
+#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0\r
+#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)\r
+#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)\r
+#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready\r
+#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).\r
+#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).\r
+#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction\r
+#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type\r
+#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control\r
+#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT\r
+#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT\r
+#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT\r
+#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN\r
+#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN\r
+#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN\r
+#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle\r
+#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable\r
+#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO\r
+// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- \r
+#define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP) \r
+#define AT91C_UDP_PUON ((unsigned int) 0x1 << 9) // (UDP) Pull-up ON\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_TC {\r
+ AT91_REG TC_CCR; // Channel Control Register\r
+ AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode)\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG TC_CV; // Counter Value\r
+ AT91_REG TC_RA; // Register A\r
+ AT91_REG TC_RB; // Register B\r
+ AT91_REG TC_RC; // Register C\r
+ AT91_REG TC_SR; // Status Register\r
+ AT91_REG TC_IER; // Interrupt Enable Register\r
+ AT91_REG TC_IDR; // Interrupt Disable Register\r
+ AT91_REG TC_IMR; // Interrupt Mask Register\r
+} AT91S_TC, *AT91PS_TC;\r
+\r
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- \r
+#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command\r
+#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command\r
+#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command\r
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- \r
+#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection\r
+#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK\r
+#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK\r
+#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK\r
+#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK\r
+#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK\r
+#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0\r
+#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1\r
+#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2\r
+#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert\r
+#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection\r
+#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal\r
+#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock\r
+#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock\r
+#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock\r
+#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare\r
+#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading\r
+#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare\r
+#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading\r
+#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection\r
+#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None\r
+#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge\r
+#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge\r
+#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge\r
+#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection\r
+#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None\r
+#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge\r
+#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge\r
+#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge\r
+#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection\r
+#define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input\r
+#define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output\r
+#define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output\r
+#define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output\r
+#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection\r
+#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable\r
+#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection\r
+#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare\r
+#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare\r
+#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare\r
+#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare\r
+#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable\r
+#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) \r
+#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA\r
+#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none\r
+#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set\r
+#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear\r
+#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle\r
+#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection\r
+#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None\r
+#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA\r
+#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA\r
+#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA\r
+#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA\r
+#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none\r
+#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set\r
+#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear\r
+#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle\r
+#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection\r
+#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None\r
+#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA\r
+#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA\r
+#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA\r
+#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA\r
+#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none\r
+#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set\r
+#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear\r
+#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle\r
+#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA\r
+#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none\r
+#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set\r
+#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear\r
+#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle\r
+#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB\r
+#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none\r
+#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set\r
+#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear\r
+#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle\r
+#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB\r
+#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none\r
+#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set\r
+#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear\r
+#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle\r
+#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB\r
+#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none\r
+#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set\r
+#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear\r
+#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle\r
+#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB\r
+#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none\r
+#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set\r
+#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear\r
+#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle\r
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- \r
+#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow\r
+#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun\r
+#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare\r
+#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare\r
+#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare\r
+#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading\r
+#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading\r
+#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger\r
+#define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling\r
+#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror\r
+#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror\r
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- \r
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- \r
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Timer Counter Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_TCB {\r
+ AT91S_TC TCB_TC0; // TC Channel 0\r
+ AT91_REG Reserved0[4]; // \r
+ AT91S_TC TCB_TC1; // TC Channel 1\r
+ AT91_REG Reserved1[4]; // \r
+ AT91S_TC TCB_TC2; // TC Channel 2\r
+ AT91_REG Reserved2[4]; // \r
+ AT91_REG TCB_BCR; // TC Block Control Register\r
+ AT91_REG TCB_BMR; // TC Block Mode Register\r
+} AT91S_TCB, *AT91PS_TCB;\r
+\r
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- \r
+#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command\r
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- \r
+#define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection\r
+#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0\r
+#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0\r
+#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0\r
+#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0\r
+#define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection\r
+#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1\r
+#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1\r
+#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1\r
+#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1\r
+#define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection\r
+#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2\r
+#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2\r
+#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2\r
+#define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_CAN_MB {\r
+ AT91_REG CAN_MB_MMR; // MailBox Mode Register\r
+ AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register\r
+ AT91_REG CAN_MB_MID; // MailBox ID Register\r
+ AT91_REG CAN_MB_MFID; // MailBox Family ID Register\r
+ AT91_REG CAN_MB_MSR; // MailBox Status Register\r
+ AT91_REG CAN_MB_MDL; // MailBox Data Low Register\r
+ AT91_REG CAN_MB_MDH; // MailBox Data High Register\r
+ AT91_REG CAN_MB_MCR; // MailBox Control Register\r
+} AT91S_CAN_MB, *AT91PS_CAN_MB;\r
+\r
+// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- \r
+#define AT91C_CAN_MTIMEMARK ((unsigned int) 0xFFFF << 0) // (CAN_MB) Mailbox Timemark\r
+#define AT91C_CAN_PRIOR ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority\r
+#define AT91C_CAN_MOT ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type\r
+#define AT91C_CAN_MOT_DIS ((unsigned int) 0x0 << 24) // (CAN_MB) \r
+#define AT91C_CAN_MOT_RX ((unsigned int) 0x1 << 24) // (CAN_MB) \r
+#define AT91C_CAN_MOT_RXOVERWRITE ((unsigned int) 0x2 << 24) // (CAN_MB) \r
+#define AT91C_CAN_MOT_TX ((unsigned int) 0x3 << 24) // (CAN_MB) \r
+#define AT91C_CAN_MOT_CONSUMER ((unsigned int) 0x4 << 24) // (CAN_MB) \r
+#define AT91C_CAN_MOT_PRODUCER ((unsigned int) 0x5 << 24) // (CAN_MB) \r
+// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- \r
+#define AT91C_CAN_MIDvB ((unsigned int) 0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode\r
+#define AT91C_CAN_MIDvA ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode\r
+#define AT91C_CAN_MIDE ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version\r
+// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- \r
+// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- \r
+// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- \r
+#define AT91C_CAN_MTIMESTAMP ((unsigned int) 0xFFFF << 0) // (CAN_MB) Timer Value\r
+#define AT91C_CAN_MDLC ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code\r
+#define AT91C_CAN_MRTR ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request\r
+#define AT91C_CAN_MABT ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort\r
+#define AT91C_CAN_MRDY ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready\r
+#define AT91C_CAN_MMI ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored\r
+// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- \r
+// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- \r
+// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- \r
+#define AT91C_CAN_MACR ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox\r
+#define AT91C_CAN_MTCR ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Control Area Network Interface\r
+// *****************************************************************************\r
+typedef struct _AT91S_CAN {\r
+ AT91_REG CAN_MR; // Mode Register\r
+ AT91_REG CAN_IER; // Interrupt Enable Register\r
+ AT91_REG CAN_IDR; // Interrupt Disable Register\r
+ AT91_REG CAN_IMR; // Interrupt Mask Register\r
+ AT91_REG CAN_SR; // Status Register\r
+ AT91_REG CAN_BR; // Baudrate Register\r
+ AT91_REG CAN_TIM; // Timer Register\r
+ AT91_REG CAN_TIMESTP; // Time Stamp Register\r
+ AT91_REG CAN_ECR; // Error Counter Register\r
+ AT91_REG CAN_TCR; // Transfer Command Register\r
+ AT91_REG CAN_ACR; // Abort Command Register\r
+ AT91_REG Reserved0[52]; // \r
+ AT91_REG CAN_VR; // Version Register\r
+ AT91_REG Reserved1[64]; // \r
+ AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0\r
+ AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1\r
+ AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2\r
+ AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3\r
+ AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4\r
+ AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5\r
+ AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6\r
+ AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7\r
+ AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8\r
+ AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9\r
+ AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10\r
+ AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11\r
+ AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12\r
+ AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13\r
+ AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14\r
+ AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15\r
+} AT91S_CAN, *AT91PS_CAN;\r
+\r
+// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- \r
+#define AT91C_CAN_CANEN ((unsigned int) 0x1 << 0) // (CAN) CAN Controller Enable\r
+#define AT91C_CAN_LPM ((unsigned int) 0x1 << 1) // (CAN) Disable/Enable Low Power Mode\r
+#define AT91C_CAN_ABM ((unsigned int) 0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode\r
+#define AT91C_CAN_OVL ((unsigned int) 0x1 << 3) // (CAN) Disable/Enable Overload Frame\r
+#define AT91C_CAN_TEOF ((unsigned int) 0x1 << 4) // (CAN) Time Stamp messages at each end of Frame\r
+#define AT91C_CAN_TTM ((unsigned int) 0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode\r
+#define AT91C_CAN_TIMFRZ ((unsigned int) 0x1 << 6) // (CAN) Enable Timer Freeze\r
+#define AT91C_CAN_DRPT ((unsigned int) 0x1 << 7) // (CAN) Disable Repeat\r
+// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- \r
+#define AT91C_CAN_MB0 ((unsigned int) 0x1 << 0) // (CAN) Mailbox 0 Flag\r
+#define AT91C_CAN_MB1 ((unsigned int) 0x1 << 1) // (CAN) Mailbox 1 Flag\r
+#define AT91C_CAN_MB2 ((unsigned int) 0x1 << 2) // (CAN) Mailbox 2 Flag\r
+#define AT91C_CAN_MB3 ((unsigned int) 0x1 << 3) // (CAN) Mailbox 3 Flag\r
+#define AT91C_CAN_MB4 ((unsigned int) 0x1 << 4) // (CAN) Mailbox 4 Flag\r
+#define AT91C_CAN_MB5 ((unsigned int) 0x1 << 5) // (CAN) Mailbox 5 Flag\r
+#define AT91C_CAN_MB6 ((unsigned int) 0x1 << 6) // (CAN) Mailbox 6 Flag\r
+#define AT91C_CAN_MB7 ((unsigned int) 0x1 << 7) // (CAN) Mailbox 7 Flag\r
+#define AT91C_CAN_MB8 ((unsigned int) 0x1 << 8) // (CAN) Mailbox 8 Flag\r
+#define AT91C_CAN_MB9 ((unsigned int) 0x1 << 9) // (CAN) Mailbox 9 Flag\r
+#define AT91C_CAN_MB10 ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag\r
+#define AT91C_CAN_MB11 ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag\r
+#define AT91C_CAN_MB12 ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag\r
+#define AT91C_CAN_MB13 ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag\r
+#define AT91C_CAN_MB14 ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag\r
+#define AT91C_CAN_MB15 ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag\r
+#define AT91C_CAN_ERRA ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag\r
+#define AT91C_CAN_WARN ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag\r
+#define AT91C_CAN_ERRP ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag\r
+#define AT91C_CAN_BOFF ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag\r
+#define AT91C_CAN_SLEEP ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag\r
+#define AT91C_CAN_WAKEUP ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag\r
+#define AT91C_CAN_TOVF ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag\r
+#define AT91C_CAN_TSTP ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag\r
+#define AT91C_CAN_CERR ((unsigned int) 0x1 << 24) // (CAN) CRC Error\r
+#define AT91C_CAN_SERR ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error\r
+#define AT91C_CAN_AERR ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error\r
+#define AT91C_CAN_FERR ((unsigned int) 0x1 << 27) // (CAN) Form Error\r
+#define AT91C_CAN_BERR ((unsigned int) 0x1 << 28) // (CAN) Bit Error\r
+// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- \r
+// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- \r
+// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- \r
+#define AT91C_CAN_RBSY ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy\r
+#define AT91C_CAN_TBSY ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy\r
+#define AT91C_CAN_OVLY ((unsigned int) 0x1 << 31) // (CAN) Overload Busy\r
+// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- \r
+#define AT91C_CAN_PHASE2 ((unsigned int) 0x7 << 0) // (CAN) Phase 2 segment\r
+#define AT91C_CAN_PHASE1 ((unsigned int) 0x7 << 4) // (CAN) Phase 1 segment\r
+#define AT91C_CAN_PROPAG ((unsigned int) 0x7 << 8) // (CAN) Programmation time segment\r
+#define AT91C_CAN_SYNC ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment\r
+#define AT91C_CAN_BRP ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler\r
+#define AT91C_CAN_SMP ((unsigned int) 0x1 << 24) // (CAN) Sampling mode\r
+// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- \r
+#define AT91C_CAN_TIMER ((unsigned int) 0xFFFF << 0) // (CAN) Timer field\r
+// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- \r
+// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- \r
+#define AT91C_CAN_REC ((unsigned int) 0xFF << 0) // (CAN) Receive Error Counter\r
+#define AT91C_CAN_TEC ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter\r
+// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- \r
+#define AT91C_CAN_TIMRST ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field\r
+// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100\r
+// *****************************************************************************\r
+typedef struct _AT91S_EMAC {\r
+ AT91_REG EMAC_NCR; // Network Control Register\r
+ AT91_REG EMAC_NCFGR; // Network Configuration Register\r
+ AT91_REG EMAC_NSR; // Network Status Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG EMAC_TSR; // Transmit Status Register\r
+ AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer\r
+ AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer\r
+ AT91_REG EMAC_RSR; // Receive Status Register\r
+ AT91_REG EMAC_ISR; // Interrupt Status Register\r
+ AT91_REG EMAC_IER; // Interrupt Enable Register\r
+ AT91_REG EMAC_IDR; // Interrupt Disable Register\r
+ AT91_REG EMAC_IMR; // Interrupt Mask Register\r
+ AT91_REG EMAC_MAN; // PHY Maintenance Register\r
+ AT91_REG EMAC_PTR; // Pause Time Register\r
+ AT91_REG EMAC_PFR; // Pause Frames received Register\r
+ AT91_REG EMAC_FTO; // Frames Transmitted OK Register\r
+ AT91_REG EMAC_SCF; // Single Collision Frame Register\r
+ AT91_REG EMAC_MCF; // Multiple Collision Frame Register\r
+ AT91_REG EMAC_FRO; // Frames Received OK Register\r
+ AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register\r
+ AT91_REG EMAC_ALE; // Alignment Error Register\r
+ AT91_REG EMAC_DTF; // Deferred Transmission Frame Register\r
+ AT91_REG EMAC_LCOL; // Late Collision Register\r
+ AT91_REG EMAC_ECOL; // Excessive Collision Register\r
+ AT91_REG EMAC_TUND; // Transmit Underrun Error Register\r
+ AT91_REG EMAC_CSE; // Carrier Sense Error Register\r
+ AT91_REG EMAC_RRE; // Receive Ressource Error Register\r
+ AT91_REG EMAC_ROV; // Receive Overrun Errors Register\r
+ AT91_REG EMAC_RSE; // Receive Symbol Errors Register\r
+ AT91_REG EMAC_ELE; // Excessive Length Errors Register\r
+ AT91_REG EMAC_RJA; // Receive Jabbers Register\r
+ AT91_REG EMAC_USF; // Undersize Frames Register\r
+ AT91_REG EMAC_STE; // SQE Test Error Register\r
+ AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register\r
+ AT91_REG EMAC_TPF; // Transmitted Pause Frames Register\r
+ AT91_REG EMAC_HRB; // Hash Address Bottom[31:0]\r
+ AT91_REG EMAC_HRT; // Hash Address Top[63:32]\r
+ AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes\r
+ AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes\r
+ AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes\r
+ AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes\r
+ AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes\r
+ AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes\r
+ AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes\r
+ AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes\r
+ AT91_REG EMAC_TID; // Type ID Checking Register\r
+ AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register\r
+ AT91_REG EMAC_USRIO; // USER Input/Output Register\r
+ AT91_REG EMAC_WOL; // Wake On LAN Register\r
+ AT91_REG Reserved1[13]; // \r
+ AT91_REG EMAC_REV; // Revision Register\r
+} AT91S_EMAC, *AT91PS_EMAC;\r
+\r
+// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- \r
+#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.\r
+#define AT91C_EMAC_LLB ((unsigned int) 0x1 << 1) // (EMAC) Loopback local. \r
+#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) // (EMAC) Receive enable. \r
+#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) // (EMAC) Transmit enable. \r
+#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) // (EMAC) Management port enable. \r
+#define AT91C_EMAC_CLRSTAT ((unsigned int) 0x1 << 5) // (EMAC) Clear statistics registers. \r
+#define AT91C_EMAC_INCSTAT ((unsigned int) 0x1 << 6) // (EMAC) Increment statistics registers. \r
+#define AT91C_EMAC_WESTAT ((unsigned int) 0x1 << 7) // (EMAC) Write enable for statistics registers. \r
+#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) // (EMAC) Back pressure. \r
+#define AT91C_EMAC_TSTART ((unsigned int) 0x1 << 9) // (EMAC) Start Transmission. \r
+#define AT91C_EMAC_THALT ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt. \r
+#define AT91C_EMAC_TPFR ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame \r
+#define AT91C_EMAC_TZQ ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame\r
+// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- \r
+#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) // (EMAC) Speed. \r
+#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) // (EMAC) Full duplex. \r
+#define AT91C_EMAC_JFRAME ((unsigned int) 0x1 << 3) // (EMAC) Jumbo Frames. \r
+#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) // (EMAC) Copy all frames. \r
+#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) // (EMAC) No broadcast. \r
+#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) // (EMAC) Multicast hash event enable\r
+#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) // (EMAC) Unicast hash enable. \r
+#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) // (EMAC) Receive 1522 bytes. \r
+#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) // (EMAC) External address match enable. \r
+#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) // (EMAC) \r
+#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8\r
+#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16\r
+#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32\r
+#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64\r
+#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) // (EMAC) \r
+#define AT91C_EMAC_PAE ((unsigned int) 0x1 << 13) // (EMAC) \r
+#define AT91C_EMAC_RBOF ((unsigned int) 0x3 << 14) // (EMAC) \r
+#define AT91C_EMAC_RBOF_OFFSET_0 ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer\r
+#define AT91C_EMAC_RBOF_OFFSET_1 ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer\r
+#define AT91C_EMAC_RBOF_OFFSET_2 ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer\r
+#define AT91C_EMAC_RBOF_OFFSET_3 ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer\r
+#define AT91C_EMAC_RLCE ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable\r
+#define AT91C_EMAC_DRFCS ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS\r
+#define AT91C_EMAC_EFRHD ((unsigned int) 0x1 << 18) // (EMAC) \r
+#define AT91C_EMAC_IRXFCS ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS\r
+// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- \r
+#define AT91C_EMAC_LINKR ((unsigned int) 0x1 << 0) // (EMAC) \r
+#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) // (EMAC) \r
+#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) // (EMAC) \r
+// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- \r
+#define AT91C_EMAC_UBR ((unsigned int) 0x1 << 0) // (EMAC) \r
+#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) // (EMAC) \r
+#define AT91C_EMAC_RLES ((unsigned int) 0x1 << 2) // (EMAC) \r
+#define AT91C_EMAC_TGO ((unsigned int) 0x1 << 3) // (EMAC) Transmit Go\r
+#define AT91C_EMAC_BEX ((unsigned int) 0x1 << 4) // (EMAC) Buffers exhausted mid frame\r
+#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) // (EMAC) \r
+#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) // (EMAC) \r
+// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- \r
+#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) // (EMAC) \r
+#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) // (EMAC) \r
+#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 2) // (EMAC) \r
+// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- \r
+#define AT91C_EMAC_MFD ((unsigned int) 0x1 << 0) // (EMAC) \r
+#define AT91C_EMAC_RCOMP ((unsigned int) 0x1 << 1) // (EMAC) \r
+#define AT91C_EMAC_RXUBR ((unsigned int) 0x1 << 2) // (EMAC) \r
+#define AT91C_EMAC_TXUBR ((unsigned int) 0x1 << 3) // (EMAC) \r
+#define AT91C_EMAC_TUNDR ((unsigned int) 0x1 << 4) // (EMAC) \r
+#define AT91C_EMAC_RLEX ((unsigned int) 0x1 << 5) // (EMAC) \r
+#define AT91C_EMAC_TXERR ((unsigned int) 0x1 << 6) // (EMAC) \r
+#define AT91C_EMAC_TCOMP ((unsigned int) 0x1 << 7) // (EMAC) \r
+#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) // (EMAC) \r
+#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) // (EMAC) \r
+#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) // (EMAC) \r
+#define AT91C_EMAC_PFRE ((unsigned int) 0x1 << 12) // (EMAC) \r
+#define AT91C_EMAC_PTZ ((unsigned int) 0x1 << 13) // (EMAC) \r
+// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- \r
+// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- \r
+// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- \r
+// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- \r
+#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) // (EMAC) \r
+#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) // (EMAC) \r
+#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) // (EMAC) \r
+#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) // (EMAC) \r
+#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) // (EMAC) \r
+#define AT91C_EMAC_SOF ((unsigned int) 0x3 << 30) // (EMAC) \r
+// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- \r
+#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 0) // (EMAC) Reduce MII\r
+// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- \r
+#define AT91C_EMAC_IP ((unsigned int) 0xFFFF << 0) // (EMAC) ARP request IP address\r
+#define AT91C_EMAC_MAG ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable\r
+#define AT91C_EMAC_ARP ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable\r
+#define AT91C_EMAC_SA1 ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable\r
+// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- \r
+#define AT91C_EMAC_REVREF ((unsigned int) 0xFFFF << 0) // (EMAC) \r
+#define AT91C_EMAC_PARTREF ((unsigned int) 0xFFFF << 16) // (EMAC) \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Analog to Digital Convertor\r
+// *****************************************************************************\r
+typedef struct _AT91S_ADC {\r
+ AT91_REG ADC_CR; // ADC Control Register\r
+ AT91_REG ADC_MR; // ADC Mode Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG ADC_CHER; // ADC Channel Enable Register\r
+ AT91_REG ADC_CHDR; // ADC Channel Disable Register\r
+ AT91_REG ADC_CHSR; // ADC Channel Status Register\r
+ AT91_REG ADC_SR; // ADC Status Register\r
+ AT91_REG ADC_LCDR; // ADC Last Converted Data Register\r
+ AT91_REG ADC_IER; // ADC Interrupt Enable Register\r
+ AT91_REG ADC_IDR; // ADC Interrupt Disable Register\r
+ AT91_REG ADC_IMR; // ADC Interrupt Mask Register\r
+ AT91_REG ADC_CDR0; // ADC Channel Data Register 0\r
+ AT91_REG ADC_CDR1; // ADC Channel Data Register 1\r
+ AT91_REG ADC_CDR2; // ADC Channel Data Register 2\r
+ AT91_REG ADC_CDR3; // ADC Channel Data Register 3\r
+ AT91_REG ADC_CDR4; // ADC Channel Data Register 4\r
+ AT91_REG ADC_CDR5; // ADC Channel Data Register 5\r
+ AT91_REG ADC_CDR6; // ADC Channel Data Register 6\r
+ AT91_REG ADC_CDR7; // ADC Channel Data Register 7\r
+ AT91_REG Reserved1[44]; // \r
+ AT91_REG ADC_RPR; // Receive Pointer Register\r
+ AT91_REG ADC_RCR; // Receive Counter Register\r
+ AT91_REG ADC_TPR; // Transmit Pointer Register\r
+ AT91_REG ADC_TCR; // Transmit Counter Register\r
+ AT91_REG ADC_RNPR; // Receive Next Pointer Register\r
+ AT91_REG ADC_RNCR; // Receive Next Counter Register\r
+ AT91_REG ADC_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG ADC_TNCR; // Transmit Next Counter Register\r
+ AT91_REG ADC_PTCR; // PDC Transfer Control Register\r
+ AT91_REG ADC_PTSR; // PDC Transfer Status Register\r
+} AT91S_ADC, *AT91PS_ADC;\r
+\r
+// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- \r
+#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset\r
+#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion\r
+// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- \r
+#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable\r
+#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software\r
+#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.\r
+#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection\r
+#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0\r
+#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1\r
+#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2\r
+#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3\r
+#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4\r
+#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5\r
+#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger\r
+#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution.\r
+#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution\r
+#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution\r
+#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode\r
+#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode\r
+#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode\r
+#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection\r
+#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time\r
+#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time\r
+// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- \r
+#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0\r
+#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1\r
+#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2\r
+#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3\r
+#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4\r
+#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5\r
+#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6\r
+#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7\r
+// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- \r
+// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- \r
+// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- \r
+#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion\r
+#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error\r
+#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready\r
+#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun\r
+#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer\r
+#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt\r
+// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- \r
+#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted\r
+// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- \r
+// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- \r
+// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- \r
+// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- \r
+#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data\r
+// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- \r
+// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- \r
+// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- \r
+// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- \r
+// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- \r
+// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- \r
+// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Advanced Encryption Standard\r
+// *****************************************************************************\r
+typedef struct _AT91S_AES {\r
+ AT91_REG AES_CR; // Control Register\r
+ AT91_REG AES_MR; // Mode Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG AES_IER; // Interrupt Enable Register\r
+ AT91_REG AES_IDR; // Interrupt Disable Register\r
+ AT91_REG AES_IMR; // Interrupt Mask Register\r
+ AT91_REG AES_ISR; // Interrupt Status Register\r
+ AT91_REG AES_KEYWxR[4]; // Key Word x Register\r
+ AT91_REG Reserved1[4]; // \r
+ AT91_REG AES_IDATAxR[4]; // Input Data x Register\r
+ AT91_REG AES_ODATAxR[4]; // Output Data x Register\r
+ AT91_REG AES_IVxR[4]; // Initialization Vector x Register\r
+ AT91_REG Reserved2[35]; // \r
+ AT91_REG AES_VR; // AES Version Register\r
+ AT91_REG AES_RPR; // Receive Pointer Register\r
+ AT91_REG AES_RCR; // Receive Counter Register\r
+ AT91_REG AES_TPR; // Transmit Pointer Register\r
+ AT91_REG AES_TCR; // Transmit Counter Register\r
+ AT91_REG AES_RNPR; // Receive Next Pointer Register\r
+ AT91_REG AES_RNCR; // Receive Next Counter Register\r
+ AT91_REG AES_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG AES_TNCR; // Transmit Next Counter Register\r
+ AT91_REG AES_PTCR; // PDC Transfer Control Register\r
+ AT91_REG AES_PTSR; // PDC Transfer Status Register\r
+} AT91S_AES, *AT91PS_AES;\r
+\r
+// -------- AES_CR : (AES Offset: 0x0) Control Register -------- \r
+#define AT91C_AES_START ((unsigned int) 0x1 << 0) // (AES) Starts Processing\r
+#define AT91C_AES_SWRST ((unsigned int) 0x1 << 8) // (AES) Software Reset\r
+#define AT91C_AES_LOADSEED ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading\r
+// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- \r
+#define AT91C_AES_CIPHER ((unsigned int) 0x1 << 0) // (AES) Processing Mode\r
+#define AT91C_AES_PROCDLY ((unsigned int) 0xF << 4) // (AES) Processing Delay\r
+#define AT91C_AES_SMOD ((unsigned int) 0x3 << 8) // (AES) Start Mode\r
+#define AT91C_AES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.\r
+#define AT91C_AES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).\r
+#define AT91C_AES_SMOD_PDC ((unsigned int) 0x2 << 8) // (AES) PDC Mode (cf datasheet).\r
+#define AT91C_AES_OPMOD ((unsigned int) 0x7 << 12) // (AES) Operation Mode\r
+#define AT91C_AES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode.\r
+#define AT91C_AES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode.\r
+#define AT91C_AES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode.\r
+#define AT91C_AES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode.\r
+#define AT91C_AES_OPMOD_CTR ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode.\r
+#define AT91C_AES_LOD ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode\r
+#define AT91C_AES_CFBS ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size\r
+#define AT91C_AES_CFBS_128_BIT ((unsigned int) 0x0 << 16) // (AES) 128-bit.\r
+#define AT91C_AES_CFBS_64_BIT ((unsigned int) 0x1 << 16) // (AES) 64-bit.\r
+#define AT91C_AES_CFBS_32_BIT ((unsigned int) 0x2 << 16) // (AES) 32-bit.\r
+#define AT91C_AES_CFBS_16_BIT ((unsigned int) 0x3 << 16) // (AES) 16-bit.\r
+#define AT91C_AES_CFBS_8_BIT ((unsigned int) 0x4 << 16) // (AES) 8-bit.\r
+#define AT91C_AES_CKEY ((unsigned int) 0xF << 20) // (AES) Countermeasure Key\r
+#define AT91C_AES_CTYPE ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type\r
+#define AT91C_AES_CTYPE_TYPE1_EN ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled.\r
+#define AT91C_AES_CTYPE_TYPE2_EN ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled.\r
+#define AT91C_AES_CTYPE_TYPE3_EN ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled.\r
+#define AT91C_AES_CTYPE_TYPE4_EN ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled.\r
+#define AT91C_AES_CTYPE_TYPE5_EN ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled.\r
+// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- \r
+#define AT91C_AES_DATRDY ((unsigned int) 0x1 << 0) // (AES) DATRDY\r
+#define AT91C_AES_ENDRX ((unsigned int) 0x1 << 1) // (AES) PDC Read Buffer End\r
+#define AT91C_AES_ENDTX ((unsigned int) 0x1 << 2) // (AES) PDC Write Buffer End\r
+#define AT91C_AES_RXBUFF ((unsigned int) 0x1 << 3) // (AES) PDC Read Buffer Full\r
+#define AT91C_AES_TXBUFE ((unsigned int) 0x1 << 4) // (AES) PDC Write Buffer Empty\r
+#define AT91C_AES_URAD ((unsigned int) 0x1 << 8) // (AES) Unspecified Register Access Detection\r
+// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- \r
+// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- \r
+// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- \r
+#define AT91C_AES_URAT ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status\r
+#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode.\r
+#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing.\r
+#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing.\r
+#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation.\r
+#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation.\r
+#define AT91C_AES_URAT_WO_REG_READ ((unsigned int) 0x5 << 12) // (AES) Write-only register read access.\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard\r
+// *****************************************************************************\r
+typedef struct _AT91S_TDES {\r
+ AT91_REG TDES_CR; // Control Register\r
+ AT91_REG TDES_MR; // Mode Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG TDES_IER; // Interrupt Enable Register\r
+ AT91_REG TDES_IDR; // Interrupt Disable Register\r
+ AT91_REG TDES_IMR; // Interrupt Mask Register\r
+ AT91_REG TDES_ISR; // Interrupt Status Register\r
+ AT91_REG TDES_KEY1WxR[2]; // Key 1 Word x Register\r
+ AT91_REG TDES_KEY2WxR[2]; // Key 2 Word x Register\r
+ AT91_REG TDES_KEY3WxR[2]; // Key 3 Word x Register\r
+ AT91_REG Reserved1[2]; // \r
+ AT91_REG TDES_IDATAxR[2]; // Input Data x Register\r
+ AT91_REG Reserved2[2]; // \r
+ AT91_REG TDES_ODATAxR[2]; // Output Data x Register\r
+ AT91_REG Reserved3[2]; // \r
+ AT91_REG TDES_IVxR[2]; // Initialization Vector x Register\r
+ AT91_REG Reserved4[37]; // \r
+ AT91_REG TDES_VR; // TDES Version Register\r
+ AT91_REG TDES_RPR; // Receive Pointer Register\r
+ AT91_REG TDES_RCR; // Receive Counter Register\r
+ AT91_REG TDES_TPR; // Transmit Pointer Register\r
+ AT91_REG TDES_TCR; // Transmit Counter Register\r
+ AT91_REG TDES_RNPR; // Receive Next Pointer Register\r
+ AT91_REG TDES_RNCR; // Receive Next Counter Register\r
+ AT91_REG TDES_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG TDES_TNCR; // Transmit Next Counter Register\r
+ AT91_REG TDES_PTCR; // PDC Transfer Control Register\r
+ AT91_REG TDES_PTSR; // PDC Transfer Status Register\r
+} AT91S_TDES, *AT91PS_TDES;\r
+\r
+// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- \r
+#define AT91C_TDES_START ((unsigned int) 0x1 << 0) // (TDES) Starts Processing\r
+#define AT91C_TDES_SWRST ((unsigned int) 0x1 << 8) // (TDES) Software Reset\r
+// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- \r
+#define AT91C_TDES_CIPHER ((unsigned int) 0x1 << 0) // (TDES) Processing Mode\r
+#define AT91C_TDES_TDESMOD ((unsigned int) 0x1 << 1) // (TDES) Single or Triple DES Mode\r
+#define AT91C_TDES_KEYMOD ((unsigned int) 0x1 << 4) // (TDES) Key Mode\r
+#define AT91C_TDES_SMOD ((unsigned int) 0x3 << 8) // (TDES) Start Mode\r
+#define AT91C_TDES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.\r
+#define AT91C_TDES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).\r
+#define AT91C_TDES_SMOD_PDC ((unsigned int) 0x2 << 8) // (TDES) PDC Mode (cf datasheet).\r
+#define AT91C_TDES_OPMOD ((unsigned int) 0x3 << 12) // (TDES) Operation Mode\r
+#define AT91C_TDES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode.\r
+#define AT91C_TDES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode.\r
+#define AT91C_TDES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode.\r
+#define AT91C_TDES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode.\r
+#define AT91C_TDES_LOD ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode\r
+#define AT91C_TDES_CFBS ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size\r
+#define AT91C_TDES_CFBS_64_BIT ((unsigned int) 0x0 << 16) // (TDES) 64-bit.\r
+#define AT91C_TDES_CFBS_32_BIT ((unsigned int) 0x1 << 16) // (TDES) 32-bit.\r
+#define AT91C_TDES_CFBS_16_BIT ((unsigned int) 0x2 << 16) // (TDES) 16-bit.\r
+#define AT91C_TDES_CFBS_8_BIT ((unsigned int) 0x3 << 16) // (TDES) 8-bit.\r
+// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- \r
+#define AT91C_TDES_DATRDY ((unsigned int) 0x1 << 0) // (TDES) DATRDY\r
+#define AT91C_TDES_ENDRX ((unsigned int) 0x1 << 1) // (TDES) PDC Read Buffer End\r
+#define AT91C_TDES_ENDTX ((unsigned int) 0x1 << 2) // (TDES) PDC Write Buffer End\r
+#define AT91C_TDES_RXBUFF ((unsigned int) 0x1 << 3) // (TDES) PDC Read Buffer Full\r
+#define AT91C_TDES_TXBUFE ((unsigned int) 0x1 << 4) // (TDES) PDC Write Buffer Empty\r
+#define AT91C_TDES_URAD ((unsigned int) 0x1 << 8) // (TDES) Unspecified Register Access Detection\r
+// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- \r
+// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- \r
+// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- \r
+#define AT91C_TDES_URAT ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status\r
+#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode.\r
+#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing.\r
+#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing.\r
+#define AT91C_TDES_URAT_WO_REG_READ ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access.\r
+\r
+// *****************************************************************************\r
+// REGISTER ADDRESS DEFINITION FOR AT91SAM7X256\r
+// *****************************************************************************\r
+// ========== Register definition for SYS peripheral ========== \r
+// ========== Register definition for AIC peripheral ========== \r
+#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register\r
+#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register\r
+#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register\r
+#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect)\r
+#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register\r
+#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register\r
+#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register\r
+#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register\r
+#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register\r
+#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register\r
+#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register\r
+#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register\r
+#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register\r
+#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register\r
+#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register\r
+#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register\r
+#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register\r
+#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register\r
+// ========== Register definition for PDC_DBGU peripheral ========== \r
+#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register\r
+#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register\r
+#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register\r
+#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register\r
+#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register\r
+#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register\r
+#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register\r
+#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register\r
+#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register\r
+#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register\r
+// ========== Register definition for DBGU peripheral ========== \r
+#define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register\r
+#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register\r
+#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register\r
+#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register\r
+#define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register\r
+#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register\r
+#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register\r
+#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register\r
+#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register\r
+#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register\r
+#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register\r
+#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register\r
+// ========== Register definition for PIOA peripheral ========== \r
+#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr\r
+#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register\r
+#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register\r
+#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register\r
+#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register\r
+#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register\r
+#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register\r
+#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register\r
+#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register\r
+#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register\r
+#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register\r
+#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register\r
+#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register\r
+#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register\r
+#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register\r
+#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register\r
+#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register\r
+#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register\r
+#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register\r
+#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register\r
+#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register\r
+#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register\r
+#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register\r
+#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register\r
+#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register\r
+#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register\r
+#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register\r
+#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register\r
+#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register\r
+// ========== Register definition for PIOB peripheral ========== \r
+#define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register\r
+#define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register\r
+#define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register\r
+#define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register\r
+#define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register\r
+#define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register\r
+#define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register\r
+#define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register\r
+#define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register\r
+#define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register\r
+#define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register\r
+#define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register\r
+#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register\r
+#define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register\r
+#define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register\r
+#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register\r
+#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr\r
+#define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register\r
+#define AT91C_PIOB_PPUER ((AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register\r
+#define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register\r
+#define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register\r
+#define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register\r
+#define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register\r
+#define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register\r
+#define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register\r
+#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register\r
+#define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register\r
+#define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register\r
+#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register\r
+// ========== Register definition for CKGR peripheral ========== \r
+#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register\r
+#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register\r
+#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register\r
+// ========== Register definition for PMC peripheral ========== \r
+#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register\r
+#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register\r
+#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register\r
+#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register\r
+#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register\r
+#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register\r
+#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register\r
+#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register\r
+#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register\r
+#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register\r
+#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register\r
+#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register\r
+#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register\r
+#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register\r
+#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register\r
+// ========== Register definition for RSTC peripheral ========== \r
+#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register\r
+#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register\r
+#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register\r
+// ========== Register definition for RTTC peripheral ========== \r
+#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register\r
+#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register\r
+#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register\r
+#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register\r
+// ========== Register definition for PITC peripheral ========== \r
+#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register\r
+#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register\r
+#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register\r
+#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register\r
+// ========== Register definition for WDTC peripheral ========== \r
+#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register\r
+#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register\r
+#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register\r
+// ========== Register definition for VREG peripheral ========== \r
+#define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register\r
+// ========== Register definition for MC peripheral ========== \r
+#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register\r
+#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register\r
+#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register\r
+#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register\r
+#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register\r
+#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register\r
+// ========== Register definition for PDC_SPI1 peripheral ========== \r
+#define AT91C_SPI1_PTCR ((AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register\r
+#define AT91C_SPI1_RPR ((AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register\r
+#define AT91C_SPI1_TNCR ((AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register\r
+#define AT91C_SPI1_TPR ((AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register\r
+#define AT91C_SPI1_TNPR ((AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register\r
+#define AT91C_SPI1_TCR ((AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register\r
+#define AT91C_SPI1_RCR ((AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register\r
+#define AT91C_SPI1_RNPR ((AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register\r
+#define AT91C_SPI1_RNCR ((AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register\r
+#define AT91C_SPI1_PTSR ((AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register\r
+// ========== Register definition for SPI1 peripheral ========== \r
+#define AT91C_SPI1_IMR ((AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register\r
+#define AT91C_SPI1_IER ((AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register\r
+#define AT91C_SPI1_MR ((AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register\r
+#define AT91C_SPI1_RDR ((AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register\r
+#define AT91C_SPI1_IDR ((AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register\r
+#define AT91C_SPI1_SR ((AT91_REG *) 0xFFFE4010) // (SPI1) Status Register\r
+#define AT91C_SPI1_TDR ((AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register\r
+#define AT91C_SPI1_CR ((AT91_REG *) 0xFFFE4000) // (SPI1) Control Register\r
+#define AT91C_SPI1_CSR ((AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register\r
+// ========== Register definition for PDC_SPI0 peripheral ========== \r
+#define AT91C_SPI0_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register\r
+#define AT91C_SPI0_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register\r
+#define AT91C_SPI0_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register\r
+#define AT91C_SPI0_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register\r
+#define AT91C_SPI0_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register\r
+#define AT91C_SPI0_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register\r
+#define AT91C_SPI0_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register\r
+#define AT91C_SPI0_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register\r
+#define AT91C_SPI0_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register\r
+#define AT91C_SPI0_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register\r
+// ========== Register definition for SPI0 peripheral ========== \r
+#define AT91C_SPI0_IER ((AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register\r
+#define AT91C_SPI0_SR ((AT91_REG *) 0xFFFE0010) // (SPI0) Status Register\r
+#define AT91C_SPI0_IDR ((AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register\r
+#define AT91C_SPI0_CR ((AT91_REG *) 0xFFFE0000) // (SPI0) Control Register\r
+#define AT91C_SPI0_MR ((AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register\r
+#define AT91C_SPI0_IMR ((AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register\r
+#define AT91C_SPI0_TDR ((AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register\r
+#define AT91C_SPI0_RDR ((AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register\r
+#define AT91C_SPI0_CSR ((AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register\r
+// ========== Register definition for PDC_US1 peripheral ========== \r
+#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register\r
+#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register\r
+#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register\r
+#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register\r
+#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register\r
+#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register\r
+#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register\r
+#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register\r
+#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register\r
+#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register\r
+// ========== Register definition for US1 peripheral ========== \r
+#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register\r
+#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register\r
+#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register\r
+#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register\r
+#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register\r
+#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register\r
+#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register\r
+#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register\r
+#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register\r
+#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register\r
+#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register\r
+#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register\r
+#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register\r
+#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register\r
+// ========== Register definition for PDC_US0 peripheral ========== \r
+#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register\r
+#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register\r
+#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register\r
+#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register\r
+#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register\r
+#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register\r
+#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register\r
+#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register\r
+#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register\r
+#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register\r
+// ========== Register definition for US0 peripheral ========== \r
+#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register\r
+#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register\r
+#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register\r
+#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register\r
+#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register\r
+#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register\r
+#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register\r
+#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register\r
+#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register\r
+#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register\r
+#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register\r
+#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register\r
+#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register\r
+#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register\r
+// ========== Register definition for PDC_SSC peripheral ========== \r
+#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register\r
+#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register\r
+#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register\r
+#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register\r
+#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register\r
+#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register\r
+#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register\r
+#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register\r
+#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register\r
+#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register\r
+// ========== Register definition for SSC peripheral ========== \r
+#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register\r
+#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register\r
+#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register\r
+#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register\r
+#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register\r
+#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister\r
+#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register\r
+#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register\r
+#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register\r
+#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register\r
+#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register\r
+#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register\r
+#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register\r
+#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register\r
+// ========== Register definition for TWI peripheral ========== \r
+#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register\r
+#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register\r
+#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register\r
+#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register\r
+#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register\r
+#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register\r
+#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register\r
+#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register\r
+#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register\r
+#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register\r
+// ========== Register definition for PWMC_CH3 peripheral ========== \r
+#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register\r
+#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved\r
+#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register\r
+#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register\r
+#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register\r
+#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register\r
+// ========== Register definition for PWMC_CH2 peripheral ========== \r
+#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved\r
+#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register\r
+#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register\r
+#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register\r
+#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register\r
+#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register\r
+// ========== Register definition for PWMC_CH1 peripheral ========== \r
+#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved\r
+#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register\r
+#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register\r
+#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register\r
+#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register\r
+#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register\r
+// ========== Register definition for PWMC_CH0 peripheral ========== \r
+#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved\r
+#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register\r
+#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register\r
+#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register\r
+#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register\r
+#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register\r
+// ========== Register definition for PWMC peripheral ========== \r
+#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register\r
+#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register\r
+#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register\r
+#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register\r
+#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register\r
+#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register\r
+#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register\r
+#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register\r
+#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register\r
+// ========== Register definition for UDP peripheral ========== \r
+#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register\r
+#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register\r
+#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register\r
+#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register\r
+#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register\r
+#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register\r
+#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register\r
+#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register\r
+#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register\r
+#define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register\r
+#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register\r
+#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register\r
+// ========== Register definition for TC0 peripheral ========== \r
+#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register\r
+#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C\r
+#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B\r
+#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register\r
+#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register\r
+#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A\r
+#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register\r
+#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value\r
+#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register\r
+// ========== Register definition for TC1 peripheral ========== \r
+#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B\r
+#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register\r
+#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register\r
+#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register\r
+#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register\r
+#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A\r
+#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C\r
+#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register\r
+#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value\r
+// ========== Register definition for TC2 peripheral ========== \r
+#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register\r
+#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value\r
+#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A\r
+#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B\r
+#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register\r
+#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register\r
+#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C\r
+#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register\r
+#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register\r
+// ========== Register definition for TCB peripheral ========== \r
+#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register\r
+#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register\r
+// ========== Register definition for CAN_MB0 peripheral ========== \r
+#define AT91C_CAN_MB0_MDL ((AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register\r
+#define AT91C_CAN_MB0_MAM ((AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register\r
+#define AT91C_CAN_MB0_MCR ((AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register\r
+#define AT91C_CAN_MB0_MID ((AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register\r
+#define AT91C_CAN_MB0_MSR ((AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register\r
+#define AT91C_CAN_MB0_MFID ((AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register\r
+#define AT91C_CAN_MB0_MDH ((AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register\r
+#define AT91C_CAN_MB0_MMR ((AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register\r
+// ========== Register definition for CAN_MB1 peripheral ========== \r
+#define AT91C_CAN_MB1_MDL ((AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register\r
+#define AT91C_CAN_MB1_MID ((AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register\r
+#define AT91C_CAN_MB1_MMR ((AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register\r
+#define AT91C_CAN_MB1_MSR ((AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register\r
+#define AT91C_CAN_MB1_MAM ((AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register\r
+#define AT91C_CAN_MB1_MDH ((AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register\r
+#define AT91C_CAN_MB1_MCR ((AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register\r
+#define AT91C_CAN_MB1_MFID ((AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register\r
+// ========== Register definition for CAN_MB2 peripheral ========== \r
+#define AT91C_CAN_MB2_MCR ((AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register\r
+#define AT91C_CAN_MB2_MDH ((AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register\r
+#define AT91C_CAN_MB2_MID ((AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register\r
+#define AT91C_CAN_MB2_MDL ((AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register\r
+#define AT91C_CAN_MB2_MMR ((AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register\r
+#define AT91C_CAN_MB2_MAM ((AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register\r
+#define AT91C_CAN_MB2_MFID ((AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register\r
+#define AT91C_CAN_MB2_MSR ((AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register\r
+// ========== Register definition for CAN_MB3 peripheral ========== \r
+#define AT91C_CAN_MB3_MFID ((AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register\r
+#define AT91C_CAN_MB3_MAM ((AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register\r
+#define AT91C_CAN_MB3_MID ((AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register\r
+#define AT91C_CAN_MB3_MCR ((AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register\r
+#define AT91C_CAN_MB3_MMR ((AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register\r
+#define AT91C_CAN_MB3_MSR ((AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register\r
+#define AT91C_CAN_MB3_MDL ((AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register\r
+#define AT91C_CAN_MB3_MDH ((AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register\r
+// ========== Register definition for CAN_MB4 peripheral ========== \r
+#define AT91C_CAN_MB4_MID ((AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register\r
+#define AT91C_CAN_MB4_MMR ((AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register\r
+#define AT91C_CAN_MB4_MDH ((AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register\r
+#define AT91C_CAN_MB4_MFID ((AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register\r
+#define AT91C_CAN_MB4_MSR ((AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register\r
+#define AT91C_CAN_MB4_MCR ((AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register\r
+#define AT91C_CAN_MB4_MDL ((AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register\r
+#define AT91C_CAN_MB4_MAM ((AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register\r
+// ========== Register definition for CAN_MB5 peripheral ========== \r
+#define AT91C_CAN_MB5_MSR ((AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register\r
+#define AT91C_CAN_MB5_MCR ((AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register\r
+#define AT91C_CAN_MB5_MFID ((AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register\r
+#define AT91C_CAN_MB5_MDH ((AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register\r
+#define AT91C_CAN_MB5_MID ((AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register\r
+#define AT91C_CAN_MB5_MMR ((AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register\r
+#define AT91C_CAN_MB5_MDL ((AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register\r
+#define AT91C_CAN_MB5_MAM ((AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register\r
+// ========== Register definition for CAN_MB6 peripheral ========== \r
+#define AT91C_CAN_MB6_MFID ((AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register\r
+#define AT91C_CAN_MB6_MID ((AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register\r
+#define AT91C_CAN_MB6_MAM ((AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register\r
+#define AT91C_CAN_MB6_MSR ((AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register\r
+#define AT91C_CAN_MB6_MDL ((AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register\r
+#define AT91C_CAN_MB6_MCR ((AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register\r
+#define AT91C_CAN_MB6_MDH ((AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register\r
+#define AT91C_CAN_MB6_MMR ((AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register\r
+// ========== Register definition for CAN_MB7 peripheral ========== \r
+#define AT91C_CAN_MB7_MCR ((AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register\r
+#define AT91C_CAN_MB7_MDH ((AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register\r
+#define AT91C_CAN_MB7_MFID ((AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register\r
+#define AT91C_CAN_MB7_MDL ((AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register\r
+#define AT91C_CAN_MB7_MID ((AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register\r
+#define AT91C_CAN_MB7_MMR ((AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register\r
+#define AT91C_CAN_MB7_MAM ((AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register\r
+#define AT91C_CAN_MB7_MSR ((AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register\r
+// ========== Register definition for CAN peripheral ========== \r
+#define AT91C_CAN_TCR ((AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register\r
+#define AT91C_CAN_IMR ((AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register\r
+#define AT91C_CAN_IER ((AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register\r
+#define AT91C_CAN_ECR ((AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register\r
+#define AT91C_CAN_TIMESTP ((AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register\r
+#define AT91C_CAN_MR ((AT91_REG *) 0xFFFD0000) // (CAN) Mode Register\r
+#define AT91C_CAN_IDR ((AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register\r
+#define AT91C_CAN_ACR ((AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register\r
+#define AT91C_CAN_TIM ((AT91_REG *) 0xFFFD0018) // (CAN) Timer Register\r
+#define AT91C_CAN_SR ((AT91_REG *) 0xFFFD0010) // (CAN) Status Register\r
+#define AT91C_CAN_BR ((AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register\r
+#define AT91C_CAN_VR ((AT91_REG *) 0xFFFD00FC) // (CAN) Version Register\r
+// ========== Register definition for EMAC peripheral ========== \r
+#define AT91C_EMAC_ISR ((AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register\r
+#define AT91C_EMAC_SA4H ((AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes\r
+#define AT91C_EMAC_SA1L ((AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes\r
+#define AT91C_EMAC_ELE ((AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register\r
+#define AT91C_EMAC_LCOL ((AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register\r
+#define AT91C_EMAC_RLE ((AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register\r
+#define AT91C_EMAC_WOL ((AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register\r
+#define AT91C_EMAC_DTF ((AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register\r
+#define AT91C_EMAC_TUND ((AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register\r
+#define AT91C_EMAC_NCR ((AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register\r
+#define AT91C_EMAC_SA4L ((AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes\r
+#define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register\r
+#define AT91C_EMAC_SA3L ((AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes\r
+#define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register\r
+#define AT91C_EMAC_IDR ((AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register\r
+#define AT91C_EMAC_RSE ((AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register\r
+#define AT91C_EMAC_ECOL ((AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register\r
+#define AT91C_EMAC_TID ((AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register\r
+#define AT91C_EMAC_HRB ((AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]\r
+#define AT91C_EMAC_TBQP ((AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer\r
+#define AT91C_EMAC_USRIO ((AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register\r
+#define AT91C_EMAC_PTR ((AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register\r
+#define AT91C_EMAC_SA2H ((AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes\r
+#define AT91C_EMAC_ROV ((AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register\r
+#define AT91C_EMAC_ALE ((AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register\r
+#define AT91C_EMAC_RJA ((AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register\r
+#define AT91C_EMAC_RBQP ((AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer\r
+#define AT91C_EMAC_TPF ((AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register\r
+#define AT91C_EMAC_NCFGR ((AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register\r
+#define AT91C_EMAC_HRT ((AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32]\r
+#define AT91C_EMAC_USF ((AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register\r
+#define AT91C_EMAC_FCSE ((AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register\r
+#define AT91C_EMAC_TPQ ((AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register\r
+#define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register\r
+#define AT91C_EMAC_FTO ((AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register\r
+#define AT91C_EMAC_REV ((AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register\r
+#define AT91C_EMAC_IMR ((AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register\r
+#define AT91C_EMAC_SCF ((AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register\r
+#define AT91C_EMAC_PFR ((AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register\r
+#define AT91C_EMAC_MCF ((AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register\r
+#define AT91C_EMAC_NSR ((AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register\r
+#define AT91C_EMAC_SA2L ((AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes\r
+#define AT91C_EMAC_FRO ((AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register\r
+#define AT91C_EMAC_IER ((AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register\r
+#define AT91C_EMAC_SA1H ((AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes\r
+#define AT91C_EMAC_CSE ((AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register\r
+#define AT91C_EMAC_SA3H ((AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes\r
+#define AT91C_EMAC_RRE ((AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register\r
+#define AT91C_EMAC_STE ((AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register\r
+// ========== Register definition for PDC_ADC peripheral ========== \r
+#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register\r
+#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register\r
+#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register\r
+#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register\r
+#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register\r
+#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register\r
+#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register\r
+#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register\r
+#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register\r
+#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register\r
+// ========== Register definition for ADC peripheral ========== \r
+#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2\r
+#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3\r
+#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0\r
+#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5\r
+#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register\r
+#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register\r
+#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4\r
+#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1\r
+#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register\r
+#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register\r
+#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register\r
+#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7\r
+#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6\r
+#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register\r
+#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register\r
+#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register\r
+#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register\r
+#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register\r
+// ========== Register definition for PDC_AES peripheral ========== \r
+#define AT91C_AES_TPR ((AT91_REG *) 0xFFFA4108) // (PDC_AES) Transmit Pointer Register\r
+#define AT91C_AES_PTCR ((AT91_REG *) 0xFFFA4120) // (PDC_AES) PDC Transfer Control Register\r
+#define AT91C_AES_RNPR ((AT91_REG *) 0xFFFA4110) // (PDC_AES) Receive Next Pointer Register\r
+#define AT91C_AES_TNCR ((AT91_REG *) 0xFFFA411C) // (PDC_AES) Transmit Next Counter Register\r
+#define AT91C_AES_TCR ((AT91_REG *) 0xFFFA410C) // (PDC_AES) Transmit Counter Register\r
+#define AT91C_AES_RCR ((AT91_REG *) 0xFFFA4104) // (PDC_AES) Receive Counter Register\r
+#define AT91C_AES_RNCR ((AT91_REG *) 0xFFFA4114) // (PDC_AES) Receive Next Counter Register\r
+#define AT91C_AES_TNPR ((AT91_REG *) 0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register\r
+#define AT91C_AES_RPR ((AT91_REG *) 0xFFFA4100) // (PDC_AES) Receive Pointer Register\r
+#define AT91C_AES_PTSR ((AT91_REG *) 0xFFFA4124) // (PDC_AES) PDC Transfer Status Register\r
+// ========== Register definition for AES peripheral ========== \r
+#define AT91C_AES_IVxR ((AT91_REG *) 0xFFFA4060) // (AES) Initialization Vector x Register\r
+#define AT91C_AES_MR ((AT91_REG *) 0xFFFA4004) // (AES) Mode Register\r
+#define AT91C_AES_VR ((AT91_REG *) 0xFFFA40FC) // (AES) AES Version Register\r
+#define AT91C_AES_ODATAxR ((AT91_REG *) 0xFFFA4050) // (AES) Output Data x Register\r
+#define AT91C_AES_IDATAxR ((AT91_REG *) 0xFFFA4040) // (AES) Input Data x Register\r
+#define AT91C_AES_CR ((AT91_REG *) 0xFFFA4000) // (AES) Control Register\r
+#define AT91C_AES_IDR ((AT91_REG *) 0xFFFA4014) // (AES) Interrupt Disable Register\r
+#define AT91C_AES_IMR ((AT91_REG *) 0xFFFA4018) // (AES) Interrupt Mask Register\r
+#define AT91C_AES_IER ((AT91_REG *) 0xFFFA4010) // (AES) Interrupt Enable Register\r
+#define AT91C_AES_KEYWxR ((AT91_REG *) 0xFFFA4020) // (AES) Key Word x Register\r
+#define AT91C_AES_ISR ((AT91_REG *) 0xFFFA401C) // (AES) Interrupt Status Register\r
+// ========== Register definition for PDC_TDES peripheral ========== \r
+#define AT91C_TDES_RNCR ((AT91_REG *) 0xFFFA8114) // (PDC_TDES) Receive Next Counter Register\r
+#define AT91C_TDES_TCR ((AT91_REG *) 0xFFFA810C) // (PDC_TDES) Transmit Counter Register\r
+#define AT91C_TDES_RCR ((AT91_REG *) 0xFFFA8104) // (PDC_TDES) Receive Counter Register\r
+#define AT91C_TDES_TNPR ((AT91_REG *) 0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register\r
+#define AT91C_TDES_RNPR ((AT91_REG *) 0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register\r
+#define AT91C_TDES_RPR ((AT91_REG *) 0xFFFA8100) // (PDC_TDES) Receive Pointer Register\r
+#define AT91C_TDES_TNCR ((AT91_REG *) 0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register\r
+#define AT91C_TDES_TPR ((AT91_REG *) 0xFFFA8108) // (PDC_TDES) Transmit Pointer Register\r
+#define AT91C_TDES_PTSR ((AT91_REG *) 0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register\r
+#define AT91C_TDES_PTCR ((AT91_REG *) 0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register\r
+// ========== Register definition for TDES peripheral ========== \r
+#define AT91C_TDES_KEY2WxR ((AT91_REG *) 0xFFFA8028) // (TDES) Key 2 Word x Register\r
+#define AT91C_TDES_KEY3WxR ((AT91_REG *) 0xFFFA8030) // (TDES) Key 3 Word x Register\r
+#define AT91C_TDES_IDR ((AT91_REG *) 0xFFFA8014) // (TDES) Interrupt Disable Register\r
+#define AT91C_TDES_VR ((AT91_REG *) 0xFFFA80FC) // (TDES) TDES Version Register\r
+#define AT91C_TDES_IVxR ((AT91_REG *) 0xFFFA8060) // (TDES) Initialization Vector x Register\r
+#define AT91C_TDES_ODATAxR ((AT91_REG *) 0xFFFA8050) // (TDES) Output Data x Register\r
+#define AT91C_TDES_IMR ((AT91_REG *) 0xFFFA8018) // (TDES) Interrupt Mask Register\r
+#define AT91C_TDES_MR ((AT91_REG *) 0xFFFA8004) // (TDES) Mode Register\r
+#define AT91C_TDES_CR ((AT91_REG *) 0xFFFA8000) // (TDES) Control Register\r
+#define AT91C_TDES_IER ((AT91_REG *) 0xFFFA8010) // (TDES) Interrupt Enable Register\r
+#define AT91C_TDES_ISR ((AT91_REG *) 0xFFFA801C) // (TDES) Interrupt Status Register\r
+#define AT91C_TDES_IDATAxR ((AT91_REG *) 0xFFFA8040) // (TDES) Input Data x Register\r
+#define AT91C_TDES_KEY1WxR ((AT91_REG *) 0xFFFA8020) // (TDES) Key 1 Word x Register\r
+\r
+// *****************************************************************************\r
+// PIO DEFINITIONS FOR AT91SAM7X256\r
+// *****************************************************************************\r
+#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0\r
+#define AT91C_PA0_RXD0 ((unsigned int) AT91C_PIO_PA0) // USART 0 Receive Data\r
+#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1\r
+#define AT91C_PA1_TXD0 ((unsigned int) AT91C_PIO_PA1) // USART 0 Transmit Data\r
+#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10\r
+#define AT91C_PA10_TWD ((unsigned int) AT91C_PIO_PA10) // TWI Two-wire Serial Data\r
+#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11\r
+#define AT91C_PA11_TWCK ((unsigned int) AT91C_PIO_PA11) // TWI Two-wire Serial Clock\r
+#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12\r
+#define AT91C_PA12_NPCS00 ((unsigned int) AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0\r
+#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13\r
+#define AT91C_PA13_NPCS01 ((unsigned int) AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1\r
+#define AT91C_PA13_PCK1 ((unsigned int) AT91C_PIO_PA13) // PMC Programmable Clock Output 1\r
+#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14\r
+#define AT91C_PA14_NPCS02 ((unsigned int) AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2\r
+#define AT91C_PA14_IRQ1 ((unsigned int) AT91C_PIO_PA14) // External Interrupt 1\r
+#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15\r
+#define AT91C_PA15_NPCS03 ((unsigned int) AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3\r
+#define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input\r
+#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16\r
+#define AT91C_PA16_MISO0 ((unsigned int) AT91C_PIO_PA16) // SPI 0 Master In Slave\r
+#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17\r
+#define AT91C_PA17_MOSI0 ((unsigned int) AT91C_PIO_PA17) // SPI 0 Master Out Slave\r
+#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18\r
+#define AT91C_PA18_SPCK0 ((unsigned int) AT91C_PIO_PA18) // SPI 0 Serial Clock\r
+#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19\r
+#define AT91C_PA19_CANRX ((unsigned int) AT91C_PIO_PA19) // CAN Receive\r
+#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2\r
+#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock\r
+#define AT91C_PA2_NPCS11 ((unsigned int) AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1\r
+#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20\r
+#define AT91C_PA20_CANTX ((unsigned int) AT91C_PIO_PA20) // CAN Transmit\r
+#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21\r
+#define AT91C_PA21_TF ((unsigned int) AT91C_PIO_PA21) // SSC Transmit Frame Sync\r
+#define AT91C_PA21_NPCS10 ((unsigned int) AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0\r
+#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22\r
+#define AT91C_PA22_TK ((unsigned int) AT91C_PIO_PA22) // SSC Transmit Clock\r
+#define AT91C_PA22_SPCK1 ((unsigned int) AT91C_PIO_PA22) // SPI 1 Serial Clock\r
+#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23\r
+#define AT91C_PA23_TD ((unsigned int) AT91C_PIO_PA23) // SSC Transmit data\r
+#define AT91C_PA23_MOSI1 ((unsigned int) AT91C_PIO_PA23) // SPI 1 Master Out Slave\r
+#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24\r
+#define AT91C_PA24_RD ((unsigned int) AT91C_PIO_PA24) // SSC Receive Data\r
+#define AT91C_PA24_MISO1 ((unsigned int) AT91C_PIO_PA24) // SPI 1 Master In Slave\r
+#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25\r
+#define AT91C_PA25_RK ((unsigned int) AT91C_PIO_PA25) // SSC Receive Clock\r
+#define AT91C_PA25_NPCS11 ((unsigned int) AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1\r
+#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26\r
+#define AT91C_PA26_RF ((unsigned int) AT91C_PIO_PA26) // SSC Receive Frame Sync\r
+#define AT91C_PA26_NPCS12 ((unsigned int) AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2\r
+#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27\r
+#define AT91C_PA27_DRXD ((unsigned int) AT91C_PIO_PA27) // DBGU Debug Receive Data\r
+#define AT91C_PA27_PCK3 ((unsigned int) AT91C_PIO_PA27) // PMC Programmable Clock Output 3\r
+#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28\r
+#define AT91C_PA28_DTXD ((unsigned int) AT91C_PIO_PA28) // DBGU Debug Transmit Data\r
+#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29\r
+#define AT91C_PA29_FIQ ((unsigned int) AT91C_PIO_PA29) // AIC Fast Interrupt Input\r
+#define AT91C_PA29_NPCS13 ((unsigned int) AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3\r
+#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3\r
+#define AT91C_PA3_RTS0 ((unsigned int) AT91C_PIO_PA3) // USART 0 Ready To Send\r
+#define AT91C_PA3_NPCS12 ((unsigned int) AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2\r
+#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30\r
+#define AT91C_PA30_IRQ0 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 0\r
+#define AT91C_PA30_PCK2 ((unsigned int) AT91C_PIO_PA30) // PMC Programmable Clock Output 2\r
+#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4\r
+#define AT91C_PA4_CTS0 ((unsigned int) AT91C_PIO_PA4) // USART 0 Clear To Send\r
+#define AT91C_PA4_NPCS13 ((unsigned int) AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3\r
+#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5\r
+#define AT91C_PA5_RXD1 ((unsigned int) AT91C_PIO_PA5) // USART 1 Receive Data\r
+#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6\r
+#define AT91C_PA6_TXD1 ((unsigned int) AT91C_PIO_PA6) // USART 1 Transmit Data\r
+#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7\r
+#define AT91C_PA7_SCK1 ((unsigned int) AT91C_PIO_PA7) // USART 1 Serial Clock\r
+#define AT91C_PA7_NPCS01 ((unsigned int) AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1\r
+#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8\r
+#define AT91C_PA8_RTS1 ((unsigned int) AT91C_PIO_PA8) // USART 1 Ready To Send\r
+#define AT91C_PA8_NPCS02 ((unsigned int) AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2\r
+#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9\r
+#define AT91C_PA9_CTS1 ((unsigned int) AT91C_PIO_PA9) // USART 1 Clear To Send\r
+#define AT91C_PA9_NPCS03 ((unsigned int) AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3\r
+#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0\r
+#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock\r
+#define AT91C_PB0_PCK0 ((unsigned int) AT91C_PIO_PB0) // PMC Programmable Clock Output 0\r
+#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1\r
+#define AT91C_PB1_ETXEN ((unsigned int) AT91C_PIO_PB1) // Ethernet MAC Transmit Enable\r
+#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10\r
+#define AT91C_PB10_ETX2 ((unsigned int) AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2\r
+#define AT91C_PB10_NPCS11 ((unsigned int) AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1\r
+#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11\r
+#define AT91C_PB11_ETX3 ((unsigned int) AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3\r
+#define AT91C_PB11_NPCS12 ((unsigned int) AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2\r
+#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12\r
+#define AT91C_PB12_ETXER ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error\r
+#define AT91C_PB12_TCLK0 ((unsigned int) AT91C_PIO_PB12) // Timer Counter 0 external clock input\r
+#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13\r
+#define AT91C_PB13_ERX2 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Receive Data 2\r
+#define AT91C_PB13_NPCS01 ((unsigned int) AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1\r
+#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14\r
+#define AT91C_PB14_ERX3 ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Receive Data 3\r
+#define AT91C_PB14_NPCS02 ((unsigned int) AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2\r
+#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15\r
+#define AT91C_PB15_ERXDV ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid\r
+#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16\r
+#define AT91C_PB16_ECOL ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Collision Detected\r
+#define AT91C_PB16_NPCS13 ((unsigned int) AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3\r
+#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17\r
+#define AT91C_PB17_ERXCK ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Clock\r
+#define AT91C_PB17_NPCS03 ((unsigned int) AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3\r
+#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18\r
+#define AT91C_PB18_EF100 ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec\r
+#define AT91C_PB18_ADTRG ((unsigned int) AT91C_PIO_PB18) // ADC External Trigger\r
+#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19\r
+#define AT91C_PB19_PWM0 ((unsigned int) AT91C_PIO_PB19) // PWM Channel 0\r
+#define AT91C_PB19_TCLK1 ((unsigned int) AT91C_PIO_PB19) // Timer Counter 1 external clock input\r
+#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2\r
+#define AT91C_PB2_ETX0 ((unsigned int) AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0\r
+#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20\r
+#define AT91C_PB20_PWM1 ((unsigned int) AT91C_PIO_PB20) // PWM Channel 1\r
+#define AT91C_PB20_PCK0 ((unsigned int) AT91C_PIO_PB20) // PMC Programmable Clock Output 0\r
+#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21\r
+#define AT91C_PB21_PWM2 ((unsigned int) AT91C_PIO_PB21) // PWM Channel 2\r
+#define AT91C_PB21_PCK1 ((unsigned int) AT91C_PIO_PB21) // PMC Programmable Clock Output 1\r
+#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22\r
+#define AT91C_PB22_PWM3 ((unsigned int) AT91C_PIO_PB22) // PWM Channel 3\r
+#define AT91C_PB22_PCK2 ((unsigned int) AT91C_PIO_PB22) // PMC Programmable Clock Output 2\r
+#define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23\r
+#define AT91C_PB23_TIOA0 ((unsigned int) AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A\r
+#define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect\r
+#define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24\r
+#define AT91C_PB24_TIOB0 ((unsigned int) AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B\r
+#define AT91C_PB24_DSR1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Data Set ready\r
+#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25\r
+#define AT91C_PB25_TIOA1 ((unsigned int) AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A\r
+#define AT91C_PB25_DTR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Terminal ready\r
+#define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26\r
+#define AT91C_PB26_TIOB1 ((unsigned int) AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B\r
+#define AT91C_PB26_RI1 ((unsigned int) AT91C_PIO_PB26) // USART 1 Ring Indicator\r
+#define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27\r
+#define AT91C_PB27_TIOA2 ((unsigned int) AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A\r
+#define AT91C_PB27_PWM0 ((unsigned int) AT91C_PIO_PB27) // PWM Channel 0\r
+#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28\r
+#define AT91C_PB28_TIOB2 ((unsigned int) AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B\r
+#define AT91C_PB28_PWM1 ((unsigned int) AT91C_PIO_PB28) // PWM Channel 1\r
+#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29\r
+#define AT91C_PB29_PCK1 ((unsigned int) AT91C_PIO_PB29) // PMC Programmable Clock Output 1\r
+#define AT91C_PB29_PWM2 ((unsigned int) AT91C_PIO_PB29) // PWM Channel 2\r
+#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3\r
+#define AT91C_PB3_ETX1 ((unsigned int) AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1\r
+#define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30\r
+#define AT91C_PB30_PCK2 ((unsigned int) AT91C_PIO_PB30) // PMC Programmable Clock Output 2\r
+#define AT91C_PB30_PWM3 ((unsigned int) AT91C_PIO_PB30) // PWM Channel 3\r
+#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4\r
+#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid\r
+#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5\r
+#define AT91C_PB5_ERX0 ((unsigned int) AT91C_PIO_PB5) // Ethernet MAC Receive Data 0\r
+#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6\r
+#define AT91C_PB6_ERX1 ((unsigned int) AT91C_PIO_PB6) // Ethernet MAC Receive Data 1\r
+#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7\r
+#define AT91C_PB7_ERXER ((unsigned int) AT91C_PIO_PB7) // Ethernet MAC Receive Error\r
+#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8\r
+#define AT91C_PB8_EMDC ((unsigned int) AT91C_PIO_PB8) // Ethernet MAC Management Data Clock\r
+#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9\r
+#define AT91C_PB9_EMDIO ((unsigned int) AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output\r
+\r
+// *****************************************************************************\r
+// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256\r
+// *****************************************************************************\r
+#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ)\r
+#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral\r
+#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller A\r
+#define AT91C_ID_PIOB ((unsigned int) 3) // Parallel IO Controller B\r
+#define AT91C_ID_SPI0 ((unsigned int) 4) // Serial Peripheral Interface 0\r
+#define AT91C_ID_SPI1 ((unsigned int) 5) // Serial Peripheral Interface 1\r
+#define AT91C_ID_US0 ((unsigned int) 6) // USART 0\r
+#define AT91C_ID_US1 ((unsigned int) 7) // USART 1\r
+#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller\r
+#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface\r
+#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller\r
+#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port\r
+#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0\r
+#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1\r
+#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2\r
+#define AT91C_ID_CAN ((unsigned int) 15) // Control Area Network Controller\r
+#define AT91C_ID_EMAC ((unsigned int) 16) // Ethernet MAC\r
+#define AT91C_ID_ADC ((unsigned int) 17) // Analog-to-Digital Converter\r
+#define AT91C_ID_AES ((unsigned int) 18) // Advanced Encryption Standard 128-bit\r
+#define AT91C_ID_TDES ((unsigned int) 19) // Triple Data Encryption Standard\r
+#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved\r
+#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved\r
+#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved\r
+#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved\r
+#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved\r
+#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved\r
+#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved\r
+#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved\r
+#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved\r
+#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved\r
+#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0)\r
+#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1)\r
+\r
+// *****************************************************************************\r
+// BASE ADDRESS DEFINITIONS FOR AT91SAM7X256\r
+// *****************************************************************************\r
+#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address\r
+#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address\r
+#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address\r
+#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address\r
+#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address\r
+#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address\r
+#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address\r
+#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address\r
+#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address\r
+#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address\r
+#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address\r
+#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address\r
+#define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address\r
+#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address\r
+#define AT91C_BASE_PDC_SPI1 ((AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address\r
+#define AT91C_BASE_SPI1 ((AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address\r
+#define AT91C_BASE_PDC_SPI0 ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address\r
+#define AT91C_BASE_SPI0 ((AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address\r
+#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address\r
+#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address\r
+#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address\r
+#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address\r
+#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address\r
+#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address\r
+#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address\r
+#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address\r
+#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address\r
+#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address\r
+#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address\r
+#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address\r
+#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address\r
+#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address\r
+#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address\r
+#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address\r
+#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address\r
+#define AT91C_BASE_CAN_MB0 ((AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address\r
+#define AT91C_BASE_CAN_MB1 ((AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address\r
+#define AT91C_BASE_CAN_MB2 ((AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address\r
+#define AT91C_BASE_CAN_MB3 ((AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address\r
+#define AT91C_BASE_CAN_MB4 ((AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address\r
+#define AT91C_BASE_CAN_MB5 ((AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address\r
+#define AT91C_BASE_CAN_MB6 ((AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address\r
+#define AT91C_BASE_CAN_MB7 ((AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address\r
+#define AT91C_BASE_CAN ((AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address\r
+#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address\r
+#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address\r
+#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address\r
+#define AT91C_BASE_PDC_AES ((AT91PS_PDC) 0xFFFA4100) // (PDC_AES) Base Address\r
+#define AT91C_BASE_AES ((AT91PS_AES) 0xFFFA4000) // (AES) Base Address\r
+#define AT91C_BASE_PDC_TDES ((AT91PS_PDC) 0xFFFA8100) // (PDC_TDES) Base Address\r
+#define AT91C_BASE_TDES ((AT91PS_TDES) 0xFFFA8000) // (TDES) Base Address\r
+\r
+// *****************************************************************************\r
+// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256\r
+// *****************************************************************************\r
+#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address\r
+#define AT91C_ISRAM_SIZE ((unsigned int) 0x00010000) // Internal SRAM size in byte (64 Kbyte)\r
+#define AT91C_IFLASH ((char *) 0x00100000) // Internal ROM base address\r
+#define AT91C_IFLASH_SIZE ((unsigned int) 0x00040000) // Internal ROM size in byte (256 Kbyte)\r
+\r
+#endif\r
--- /dev/null
+// ----------------------------------------------------------------------------\r
+// ATMEL Microcontroller Software Support - ROUSSET -\r
+// ----------------------------------------------------------------------------\r
+// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+// ----------------------------------------------------------------------------\r
+// File Name : AT91SAM7X256.h\r
+// Object : AT91SAM7X256 definitions\r
+// Generated : AT91 SW Application Group 05/20/2005 (16:22:29)\r
+// \r
+// CVS Reference : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005//\r
+// CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005//\r
+// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//\r
+// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005//\r
+// CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005//\r
+// CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//\r
+// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//\r
+// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//\r
+// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005//\r
+// CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004//\r
+// CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004//\r
+// CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004//\r
+// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005//\r
+// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005//\r
+// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//\r
+// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//\r
+// CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//\r
+// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//\r
+// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//\r
+// CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//\r
+// CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005//\r
+// CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005//\r
+// CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//\r
+// CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005//\r
+// CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005//\r
+// ----------------------------------------------------------------------------\r
+\r
+// Hardware register definition\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR System Peripherals\r
+// *****************************************************************************\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_AIC structure ***\r
+#define AIC_SMR ( 0) // Source Mode Register\r
+#define AIC_SVR (128) // Source Vector Register\r
+#define AIC_IVR (256) // IRQ Vector Register\r
+#define AIC_FVR (260) // FIQ Vector Register\r
+#define AIC_ISR (264) // Interrupt Status Register\r
+#define AIC_IPR (268) // Interrupt Pending Register\r
+#define AIC_IMR (272) // Interrupt Mask Register\r
+#define AIC_CISR (276) // Core Interrupt Status Register\r
+#define AIC_IECR (288) // Interrupt Enable Command Register\r
+#define AIC_IDCR (292) // Interrupt Disable Command Register\r
+#define AIC_ICCR (296) // Interrupt Clear Command Register\r
+#define AIC_ISCR (300) // Interrupt Set Command Register\r
+#define AIC_EOICR (304) // End of Interrupt Command Register\r
+#define AIC_SPU (308) // Spurious Vector Register\r
+#define AIC_DCR (312) // Debug Control Register (Protect)\r
+#define AIC_FFER (320) // Fast Forcing Enable Register\r
+#define AIC_FFDR (324) // Fast Forcing Disable Register\r
+#define AIC_FFSR (328) // Fast Forcing Status Register\r
+// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- \r
+#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level\r
+#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level\r
+#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level\r
+#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type\r
+#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive\r
+#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive\r
+#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered\r
+#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered\r
+#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive\r
+#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered\r
+// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- \r
+#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status\r
+#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status\r
+// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- \r
+#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode\r
+#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Peripheral DMA Controller\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_PDC structure ***\r
+#define PDC_RPR ( 0) // Receive Pointer Register\r
+#define PDC_RCR ( 4) // Receive Counter Register\r
+#define PDC_TPR ( 8) // Transmit Pointer Register\r
+#define PDC_TCR (12) // Transmit Counter Register\r
+#define PDC_RNPR (16) // Receive Next Pointer Register\r
+#define PDC_RNCR (20) // Receive Next Counter Register\r
+#define PDC_TNPR (24) // Transmit Next Pointer Register\r
+#define PDC_TNCR (28) // Transmit Next Counter Register\r
+#define PDC_PTCR (32) // PDC Transfer Control Register\r
+#define PDC_PTSR (36) // PDC Transfer Status Register\r
+// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- \r
+#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable\r
+#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable\r
+#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable\r
+#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable\r
+// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Debug Unit\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_DBGU structure ***\r
+#define DBGU_CR ( 0) // Control Register\r
+#define DBGU_MR ( 4) // Mode Register\r
+#define DBGU_IER ( 8) // Interrupt Enable Register\r
+#define DBGU_IDR (12) // Interrupt Disable Register\r
+#define DBGU_IMR (16) // Interrupt Mask Register\r
+#define DBGU_CSR (20) // Channel Status Register\r
+#define DBGU_RHR (24) // Receiver Holding Register\r
+#define DBGU_THR (28) // Transmitter Holding Register\r
+#define DBGU_BRGR (32) // Baud Rate Generator Register\r
+#define DBGU_CIDR (64) // Chip ID Register\r
+#define DBGU_EXID (68) // Chip ID Extension Register\r
+#define DBGU_FNTR (72) // Force NTRST Register\r
+#define DBGU_RPR (256) // Receive Pointer Register\r
+#define DBGU_RCR (260) // Receive Counter Register\r
+#define DBGU_TPR (264) // Transmit Pointer Register\r
+#define DBGU_TCR (268) // Transmit Counter Register\r
+#define DBGU_RNPR (272) // Receive Next Pointer Register\r
+#define DBGU_RNCR (276) // Receive Next Counter Register\r
+#define DBGU_TNPR (280) // Transmit Next Pointer Register\r
+#define DBGU_TNCR (284) // Transmit Next Counter Register\r
+#define DBGU_PTCR (288) // PDC Transfer Control Register\r
+#define DBGU_PTSR (292) // PDC Transfer Status Register\r
+// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- \r
+#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver\r
+#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter\r
+#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable\r
+#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable\r
+#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable\r
+#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable\r
+#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits\r
+// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- \r
+#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type\r
+#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity\r
+#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity\r
+#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space)\r
+#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark)\r
+#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity\r
+#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode\r
+#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode\r
+#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.\r
+#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.\r
+#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.\r
+#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.\r
+// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- \r
+#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt\r
+#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt\r
+#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt\r
+#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt\r
+#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt\r
+#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt\r
+#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt\r
+#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt\r
+#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt\r
+#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt\r
+#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt\r
+#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt\r
+// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- \r
+// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- \r
+// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- \r
+// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- \r
+#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Parallel Input Output Controler\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_PIO structure ***\r
+#define PIO_PER ( 0) // PIO Enable Register\r
+#define PIO_PDR ( 4) // PIO Disable Register\r
+#define PIO_PSR ( 8) // PIO Status Register\r
+#define PIO_OER (16) // Output Enable Register\r
+#define PIO_ODR (20) // Output Disable Registerr\r
+#define PIO_OSR (24) // Output Status Register\r
+#define PIO_IFER (32) // Input Filter Enable Register\r
+#define PIO_IFDR (36) // Input Filter Disable Register\r
+#define PIO_IFSR (40) // Input Filter Status Register\r
+#define PIO_SODR (48) // Set Output Data Register\r
+#define PIO_CODR (52) // Clear Output Data Register\r
+#define PIO_ODSR (56) // Output Data Status Register\r
+#define PIO_PDSR (60) // Pin Data Status Register\r
+#define PIO_IER (64) // Interrupt Enable Register\r
+#define PIO_IDR (68) // Interrupt Disable Register\r
+#define PIO_IMR (72) // Interrupt Mask Register\r
+#define PIO_ISR (76) // Interrupt Status Register\r
+#define PIO_MDER (80) // Multi-driver Enable Register\r
+#define PIO_MDDR (84) // Multi-driver Disable Register\r
+#define PIO_MDSR (88) // Multi-driver Status Register\r
+#define PIO_PPUDR (96) // Pull-up Disable Register\r
+#define PIO_PPUER (100) // Pull-up Enable Register\r
+#define PIO_PPUSR (104) // Pull-up Status Register\r
+#define PIO_ASR (112) // Select A Register\r
+#define PIO_BSR (116) // Select B Register\r
+#define PIO_ABSR (120) // AB Select Status Register\r
+#define PIO_OWER (160) // Output Write Enable Register\r
+#define PIO_OWDR (164) // Output Write Disable Register\r
+#define PIO_OWSR (168) // Output Write Status Register\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Clock Generator Controler\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_CKGR structure ***\r
+#define CKGR_MOR ( 0) // Main Oscillator Register\r
+#define CKGR_MCFR ( 4) // Main Clock Frequency Register\r
+#define CKGR_PLLR (12) // PLL Register\r
+// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- \r
+#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable\r
+#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass\r
+#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time\r
+// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- \r
+#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency\r
+#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready\r
+// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- \r
+#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected\r
+#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0\r
+#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed\r
+#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter\r
+#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range\r
+#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet\r
+#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet\r
+#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet\r
+#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet\r
+#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier\r
+#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks\r
+#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output\r
+#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2\r
+#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Power Management Controler\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_PMC structure ***\r
+#define PMC_SCER ( 0) // System Clock Enable Register\r
+#define PMC_SCDR ( 4) // System Clock Disable Register\r
+#define PMC_SCSR ( 8) // System Clock Status Register\r
+#define PMC_PCER (16) // Peripheral Clock Enable Register\r
+#define PMC_PCDR (20) // Peripheral Clock Disable Register\r
+#define PMC_PCSR (24) // Peripheral Clock Status Register\r
+#define PMC_MOR (32) // Main Oscillator Register\r
+#define PMC_MCFR (36) // Main Clock Frequency Register\r
+#define PMC_PLLR (44) // PLL Register\r
+#define PMC_MCKR (48) // Master Clock Register\r
+#define PMC_PCKR (64) // Programmable Clock Register\r
+#define PMC_IER (96) // Interrupt Enable Register\r
+#define PMC_IDR (100) // Interrupt Disable Register\r
+#define PMC_SR (104) // Status Register\r
+#define PMC_IMR (108) // Interrupt Mask Register\r
+// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- \r
+#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock\r
+#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock\r
+#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output\r
+#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output\r
+#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output\r
+#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output\r
+// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- \r
+// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- \r
+// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- \r
+// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- \r
+// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- \r
+// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- \r
+#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection\r
+#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected\r
+#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected\r
+#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected\r
+#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler\r
+#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock\r
+#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2\r
+#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4\r
+#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8\r
+#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16\r
+#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32\r
+#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64\r
+// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- \r
+// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- \r
+#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask\r
+#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask\r
+#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask\r
+// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- \r
+// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- \r
+// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Reset Controller Interface\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_RSTC structure ***\r
+#define RSTC_RCR ( 0) // Reset Control Register\r
+#define RSTC_RSR ( 4) // Reset Status Register\r
+#define RSTC_RMR ( 8) // Reset Mode Register\r
+// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- \r
+#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset\r
+#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset\r
+#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset\r
+#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password\r
+// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- \r
+#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status\r
+#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status\r
+#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type\r
+#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising.\r
+#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising.\r
+#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.\r
+#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.\r
+#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low.\r
+#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured.\r
+#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level\r
+#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress.\r
+// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- \r
+#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable\r
+#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable\r
+#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Enable\r
+#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_RTTC structure ***\r
+#define RTTC_RTMR ( 0) // Real-time Mode Register\r
+#define RTTC_RTAR ( 4) // Real-time Alarm Register\r
+#define RTTC_RTVR ( 8) // Real-time Value Register\r
+#define RTTC_RTSR (12) // Real-time Status Register\r
+// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- \r
+#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value\r
+#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable\r
+#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable\r
+#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart\r
+// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- \r
+#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value\r
+// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- \r
+#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value\r
+// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- \r
+#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status\r
+#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_PITC structure ***\r
+#define PITC_PIMR ( 0) // Period Interval Mode Register\r
+#define PITC_PISR ( 4) // Period Interval Status Register\r
+#define PITC_PIVR ( 8) // Period Interval Value Register\r
+#define PITC_PIIR (12) // Period Interval Image Register\r
+// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- \r
+#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value\r
+#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled\r
+#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable\r
+// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- \r
+#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status\r
+// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- \r
+#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value\r
+#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter\r
+// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_WDTC structure ***\r
+#define WDTC_WDCR ( 0) // Watchdog Control Register\r
+#define WDTC_WDMR ( 4) // Watchdog Mode Register\r
+#define WDTC_WDSR ( 8) // Watchdog Status Register\r
+// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- \r
+#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart\r
+#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password\r
+// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- \r
+#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart\r
+#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable\r
+#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable\r
+#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart\r
+#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable\r
+#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value\r
+#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt\r
+#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt\r
+// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- \r
+#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow\r
+#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_VREG structure ***\r
+#define VREG_MR ( 0) // Voltage Regulator Mode Register\r
+// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- \r
+#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Memory Controller Interface\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_MC structure ***\r
+#define MC_RCR ( 0) // MC Remap Control Register\r
+#define MC_ASR ( 4) // MC Abort Status Register\r
+#define MC_AASR ( 8) // MC Abort Address Status Register\r
+#define MC_FMR (96) // MC Flash Mode Register\r
+#define MC_FCR (100) // MC Flash Command Register\r
+#define MC_FSR (104) // MC Flash Status Register\r
+// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- \r
+#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit\r
+// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- \r
+#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status\r
+#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status\r
+#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status\r
+#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte\r
+#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word\r
+#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word\r
+#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status\r
+#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read\r
+#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write\r
+#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch\r
+#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source\r
+#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source\r
+#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source\r
+#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source\r
+// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- \r
+#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready\r
+#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error\r
+#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error\r
+#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming\r
+#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State\r
+#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations\r
+#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations\r
+#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations\r
+#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations\r
+#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number\r
+// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- \r
+#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command\r
+#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN.\r
+#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.\r
+#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.\r
+#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.\r
+#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.\r
+#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits.\r
+#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits.\r
+#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit.\r
+#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number\r
+#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key\r
+// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- \r
+#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status\r
+#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status\r
+#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status\r
+#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status\r
+#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status\r
+#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status\r
+#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status\r
+#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status\r
+#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status\r
+#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status\r
+#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status\r
+#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status\r
+#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status\r
+#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status\r
+#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status\r
+#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status\r
+#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status\r
+#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status\r
+#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status\r
+#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status\r
+#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status\r
+#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status\r
+#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status\r
+#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status\r
+#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Serial Parallel Interface\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_SPI structure ***\r
+#define SPI_CR ( 0) // Control Register\r
+#define SPI_MR ( 4) // Mode Register\r
+#define SPI_RDR ( 8) // Receive Data Register\r
+#define SPI_TDR (12) // Transmit Data Register\r
+#define SPI_SR (16) // Status Register\r
+#define SPI_IER (20) // Interrupt Enable Register\r
+#define SPI_IDR (24) // Interrupt Disable Register\r
+#define SPI_IMR (28) // Interrupt Mask Register\r
+#define SPI_CSR (48) // Chip Select Register\r
+#define SPI_RPR (256) // Receive Pointer Register\r
+#define SPI_RCR (260) // Receive Counter Register\r
+#define SPI_TPR (264) // Transmit Pointer Register\r
+#define SPI_TCR (268) // Transmit Counter Register\r
+#define SPI_RNPR (272) // Receive Next Pointer Register\r
+#define SPI_RNCR (276) // Receive Next Counter Register\r
+#define SPI_TNPR (280) // Transmit Next Pointer Register\r
+#define SPI_TNCR (284) // Transmit Next Counter Register\r
+#define SPI_PTCR (288) // PDC Transfer Control Register\r
+#define SPI_PTSR (292) // PDC Transfer Status Register\r
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- \r
+#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable\r
+#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable\r
+#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset\r
+#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer\r
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- \r
+#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode\r
+#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select\r
+#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select\r
+#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select\r
+#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode\r
+#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection\r
+#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection\r
+#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection\r
+#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select\r
+#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects\r
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- \r
+#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data\r
+#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status\r
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- \r
+#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data\r
+#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status\r
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- \r
+#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full\r
+#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty\r
+#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error\r
+#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status\r
+#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer\r
+#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer\r
+#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt\r
+#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt\r
+#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt\r
+#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt\r
+#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status\r
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- \r
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- \r
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- \r
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- \r
+#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity\r
+#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase\r
+#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer\r
+#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer\r
+#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer\r
+#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer\r
+#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer\r
+#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer\r
+#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer\r
+#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer\r
+#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer\r
+#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer\r
+#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer\r
+#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate\r
+#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK\r
+#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Usart\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_USART structure ***\r
+#define US_CR ( 0) // Control Register\r
+#define US_MR ( 4) // Mode Register\r
+#define US_IER ( 8) // Interrupt Enable Register\r
+#define US_IDR (12) // Interrupt Disable Register\r
+#define US_IMR (16) // Interrupt Mask Register\r
+#define US_CSR (20) // Channel Status Register\r
+#define US_RHR (24) // Receiver Holding Register\r
+#define US_THR (28) // Transmitter Holding Register\r
+#define US_BRGR (32) // Baud Rate Generator Register\r
+#define US_RTOR (36) // Receiver Time-out Register\r
+#define US_TTGR (40) // Transmitter Time-guard Register\r
+#define US_FIDI (64) // FI_DI_Ratio Register\r
+#define US_NER (68) // Nb Errors Register\r
+#define US_IF (76) // IRDA_FILTER Register\r
+#define US_RPR (256) // Receive Pointer Register\r
+#define US_RCR (260) // Receive Counter Register\r
+#define US_TPR (264) // Transmit Pointer Register\r
+#define US_TCR (268) // Transmit Counter Register\r
+#define US_RNPR (272) // Receive Next Pointer Register\r
+#define US_RNCR (276) // Receive Next Counter Register\r
+#define US_TNPR (280) // Transmit Next Pointer Register\r
+#define US_TNCR (284) // Transmit Next Counter Register\r
+#define US_PTCR (288) // PDC Transfer Control Register\r
+#define US_PTSR (292) // PDC Transfer Status Register\r
+// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- \r
+#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break\r
+#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break\r
+#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out\r
+#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address\r
+#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations\r
+#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge\r
+#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out\r
+#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable\r
+#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable\r
+#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable\r
+#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable\r
+// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- \r
+#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode\r
+#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal\r
+#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485\r
+#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking\r
+#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem\r
+#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0\r
+#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1\r
+#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA\r
+#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking\r
+#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock\r
+#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock\r
+#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1\r
+#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM)\r
+#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK)\r
+#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock\r
+#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits\r
+#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits\r
+#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits\r
+#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits\r
+#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select\r
+#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits\r
+#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit\r
+#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits\r
+#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits\r
+#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order\r
+#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length\r
+#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select\r
+#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode\r
+#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge\r
+#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK\r
+#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions\r
+#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter\r
+// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- \r
+#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break\r
+#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out\r
+#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached\r
+#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge\r
+#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag\r
+#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag\r
+#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag\r
+#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag\r
+// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- \r
+// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- \r
+// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- \r
+#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input\r
+#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input\r
+#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input\r
+#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_SSC structure ***\r
+#define SSC_CR ( 0) // Control Register\r
+#define SSC_CMR ( 4) // Clock Mode Register\r
+#define SSC_RCMR (16) // Receive Clock ModeRegister\r
+#define SSC_RFMR (20) // Receive Frame Mode Register\r
+#define SSC_TCMR (24) // Transmit Clock Mode Register\r
+#define SSC_TFMR (28) // Transmit Frame Mode Register\r
+#define SSC_RHR (32) // Receive Holding Register\r
+#define SSC_THR (36) // Transmit Holding Register\r
+#define SSC_RSHR (48) // Receive Sync Holding Register\r
+#define SSC_TSHR (52) // Transmit Sync Holding Register\r
+#define SSC_SR (64) // Status Register\r
+#define SSC_IER (68) // Interrupt Enable Register\r
+#define SSC_IDR (72) // Interrupt Disable Register\r
+#define SSC_IMR (76) // Interrupt Mask Register\r
+#define SSC_RPR (256) // Receive Pointer Register\r
+#define SSC_RCR (260) // Receive Counter Register\r
+#define SSC_TPR (264) // Transmit Pointer Register\r
+#define SSC_TCR (268) // Transmit Counter Register\r
+#define SSC_RNPR (272) // Receive Next Pointer Register\r
+#define SSC_RNCR (276) // Receive Next Counter Register\r
+#define SSC_TNPR (280) // Transmit Next Pointer Register\r
+#define SSC_TNCR (284) // Transmit Next Counter Register\r
+#define SSC_PTCR (288) // PDC Transfer Control Register\r
+#define SSC_PTSR (292) // PDC Transfer Status Register\r
+// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- \r
+#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable\r
+#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable\r
+#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable\r
+#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable\r
+#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset\r
+// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- \r
+#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection\r
+#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock\r
+#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal\r
+#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin\r
+#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection\r
+#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only\r
+#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output\r
+#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output\r
+#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion\r
+#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection\r
+#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.\r
+#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start\r
+#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input\r
+#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input\r
+#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input\r
+#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input\r
+#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input\r
+#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input\r
+#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0\r
+#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay\r
+#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection\r
+// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- \r
+#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length\r
+#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode\r
+#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First\r
+#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame\r
+#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length\r
+#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection\r
+#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only\r
+#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse\r
+#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse\r
+#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer\r
+#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer\r
+#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer\r
+#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection\r
+// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- \r
+// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- \r
+#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value\r
+#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable\r
+// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- \r
+#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready\r
+#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty\r
+#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission\r
+#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty\r
+#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready\r
+#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun\r
+#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception\r
+#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full\r
+#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync\r
+#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync\r
+#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable\r
+#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable\r
+// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- \r
+// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- \r
+// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Two-wire Interface\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_TWI structure ***\r
+#define TWI_CR ( 0) // Control Register\r
+#define TWI_MMR ( 4) // Master Mode Register\r
+#define TWI_IADR (12) // Internal Address Register\r
+#define TWI_CWGR (16) // Clock Waveform Generator Register\r
+#define TWI_SR (32) // Status Register\r
+#define TWI_IER (36) // Interrupt Enable Register\r
+#define TWI_IDR (40) // Interrupt Disable Register\r
+#define TWI_IMR (44) // Interrupt Mask Register\r
+#define TWI_RHR (48) // Receive Holding Register\r
+#define TWI_THR (52) // Transmit Holding Register\r
+// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- \r
+#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition\r
+#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition\r
+#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled\r
+#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled\r
+#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset\r
+// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- \r
+#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size\r
+#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address\r
+#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address\r
+#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address\r
+#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address\r
+#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction\r
+#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address\r
+// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- \r
+#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider\r
+#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider\r
+#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider\r
+// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- \r
+#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed\r
+#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY\r
+#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY\r
+#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error\r
+#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error\r
+#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged\r
+// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- \r
+// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- \r
+// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR PWMC Channel Interface\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_PWMC_CH structure ***\r
+#define PWMC_CMR ( 0) // Channel Mode Register\r
+#define PWMC_CDTYR ( 4) // Channel Duty Cycle Register\r
+#define PWMC_CPRDR ( 8) // Channel Period Register\r
+#define PWMC_CCNTR (12) // Channel Counter Register\r
+#define PWMC_CUPDR (16) // Channel Update Register\r
+#define PWMC_Reserved (20) // Reserved\r
+// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- \r
+#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx\r
+#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH) \r
+#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH) \r
+#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH) \r
+#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment\r
+#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity\r
+#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period\r
+// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- \r
+#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle\r
+// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- \r
+#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period\r
+// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- \r
+#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter\r
+// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- \r
+#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_PWMC structure ***\r
+#define PWMC_MR ( 0) // PWMC Mode Register\r
+#define PWMC_ENA ( 4) // PWMC Enable Register\r
+#define PWMC_DIS ( 8) // PWMC Disable Register\r
+#define PWMC_SR (12) // PWMC Status Register\r
+#define PWMC_IER (16) // PWMC Interrupt Enable Register\r
+#define PWMC_IDR (20) // PWMC Interrupt Disable Register\r
+#define PWMC_IMR (24) // PWMC Interrupt Mask Register\r
+#define PWMC_ISR (28) // PWMC Interrupt Status Register\r
+#define PWMC_VR (252) // PWMC Version Register\r
+#define PWMC_CH (512) // PWMC Channel\r
+// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- \r
+#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor.\r
+#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A\r
+#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC) \r
+#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor.\r
+#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B\r
+#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC) \r
+// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- \r
+#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0\r
+#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1\r
+#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2\r
+#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3\r
+// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- \r
+// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- \r
+// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- \r
+// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- \r
+// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- \r
+// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR USB Device Interface\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_UDP structure ***\r
+#define UDP_NUM ( 0) // Frame Number Register\r
+#define UDP_GLBSTATE ( 4) // Global State Register\r
+#define UDP_FADDR ( 8) // Function Address Register\r
+#define UDP_IER (16) // Interrupt Enable Register\r
+#define UDP_IDR (20) // Interrupt Disable Register\r
+#define UDP_IMR (24) // Interrupt Mask Register\r
+#define UDP_ISR (28) // Interrupt Status Register\r
+#define UDP_ICR (32) // Interrupt Clear Register\r
+#define UDP_RSTEP (40) // Reset Endpoint Register\r
+#define UDP_CSR (48) // Endpoint Control and Status Register\r
+#define UDP_FDR (80) // Endpoint FIFO Data Register\r
+#define UDP_TXVC (116) // Transceiver Control Register\r
+// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- \r
+#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats\r
+#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error\r
+#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK\r
+// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- \r
+#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable\r
+#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured\r
+#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume\r
+#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host\r
+#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable\r
+// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- \r
+#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value\r
+#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable\r
+// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- \r
+#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt\r
+#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt\r
+#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt\r
+#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt\r
+#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt\r
+#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt\r
+#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt\r
+#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt\r
+#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt\r
+#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt\r
+#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt\r
+// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- \r
+// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- \r
+// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- \r
+#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt\r
+// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- \r
+// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- \r
+#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0\r
+#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1\r
+#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2\r
+#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3\r
+#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4\r
+#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5\r
+// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- \r
+#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR\r
+#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0\r
+#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)\r
+#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)\r
+#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready\r
+#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).\r
+#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).\r
+#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction\r
+#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type\r
+#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control\r
+#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT\r
+#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT\r
+#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT\r
+#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN\r
+#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN\r
+#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN\r
+#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle\r
+#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable\r
+#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO\r
+// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- \r
+#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP) \r
+#define AT91C_UDP_PUON (0x1 << 9) // (UDP) Pull-up ON\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_TC structure ***\r
+#define TC_CCR ( 0) // Channel Control Register\r
+#define TC_CMR ( 4) // Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define TC_CV (16) // Counter Value\r
+#define TC_RA (20) // Register A\r
+#define TC_RB (24) // Register B\r
+#define TC_RC (28) // Register C\r
+#define TC_SR (32) // Status Register\r
+#define TC_IER (36) // Interrupt Enable Register\r
+#define TC_IDR (40) // Interrupt Disable Register\r
+#define TC_IMR (44) // Interrupt Mask Register\r
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- \r
+#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command\r
+#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command\r
+#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command\r
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- \r
+#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection\r
+#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK\r
+#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK\r
+#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK\r
+#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK\r
+#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK\r
+#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0\r
+#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1\r
+#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2\r
+#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert\r
+#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection\r
+#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal\r
+#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock\r
+#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock\r
+#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock\r
+#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare\r
+#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading\r
+#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare\r
+#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading\r
+#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection\r
+#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None\r
+#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge\r
+#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge\r
+#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge\r
+#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection\r
+#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None\r
+#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge\r
+#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge\r
+#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge\r
+#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection\r
+#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input\r
+#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output\r
+#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output\r
+#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output\r
+#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection\r
+#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable\r
+#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection\r
+#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare\r
+#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare\r
+#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare\r
+#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare\r
+#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable\r
+#define AT91C_TC_WAVE (0x1 << 15) // (TC) \r
+#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA\r
+#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none\r
+#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set\r
+#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear\r
+#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle\r
+#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection\r
+#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None\r
+#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA\r
+#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA\r
+#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA\r
+#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA\r
+#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none\r
+#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set\r
+#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear\r
+#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle\r
+#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection\r
+#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None\r
+#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA\r
+#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA\r
+#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA\r
+#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA\r
+#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none\r
+#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set\r
+#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear\r
+#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle\r
+#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA\r
+#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none\r
+#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set\r
+#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear\r
+#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle\r
+#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB\r
+#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none\r
+#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set\r
+#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear\r
+#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle\r
+#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB\r
+#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none\r
+#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set\r
+#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear\r
+#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle\r
+#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB\r
+#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none\r
+#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set\r
+#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear\r
+#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle\r
+#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB\r
+#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none\r
+#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set\r
+#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear\r
+#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle\r
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- \r
+#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow\r
+#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun\r
+#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare\r
+#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare\r
+#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare\r
+#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading\r
+#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading\r
+#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger\r
+#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling\r
+#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror\r
+#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror\r
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- \r
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- \r
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Timer Counter Interface\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_TCB structure ***\r
+#define TCB_TC0 ( 0) // TC Channel 0\r
+#define TCB_TC1 (64) // TC Channel 1\r
+#define TCB_TC2 (128) // TC Channel 2\r
+#define TCB_BCR (192) // TC Block Control Register\r
+#define TCB_BMR (196) // TC Block Mode Register\r
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- \r
+#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command\r
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- \r
+#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection\r
+#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0\r
+#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0\r
+#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0\r
+#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0\r
+#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection\r
+#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1\r
+#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1\r
+#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1\r
+#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1\r
+#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection\r
+#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2\r
+#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2\r
+#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2\r
+#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_CAN_MB structure ***\r
+#define CAN_MB_MMR ( 0) // MailBox Mode Register\r
+#define CAN_MB_MAM ( 4) // MailBox Acceptance Mask Register\r
+#define CAN_MB_MID ( 8) // MailBox ID Register\r
+#define CAN_MB_MFID (12) // MailBox Family ID Register\r
+#define CAN_MB_MSR (16) // MailBox Status Register\r
+#define CAN_MB_MDL (20) // MailBox Data Low Register\r
+#define CAN_MB_MDH (24) // MailBox Data High Register\r
+#define CAN_MB_MCR (28) // MailBox Control Register\r
+// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- \r
+#define AT91C_CAN_MTIMEMARK (0xFFFF << 0) // (CAN_MB) Mailbox Timemark\r
+#define AT91C_CAN_PRIOR (0xF << 16) // (CAN_MB) Mailbox Priority\r
+#define AT91C_CAN_MOT (0x7 << 24) // (CAN_MB) Mailbox Object Type\r
+#define AT91C_CAN_MOT_DIS (0x0 << 24) // (CAN_MB) \r
+#define AT91C_CAN_MOT_RX (0x1 << 24) // (CAN_MB) \r
+#define AT91C_CAN_MOT_RXOVERWRITE (0x2 << 24) // (CAN_MB) \r
+#define AT91C_CAN_MOT_TX (0x3 << 24) // (CAN_MB) \r
+#define AT91C_CAN_MOT_CONSUMER (0x4 << 24) // (CAN_MB) \r
+#define AT91C_CAN_MOT_PRODUCER (0x5 << 24) // (CAN_MB) \r
+// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- \r
+#define AT91C_CAN_MIDvB (0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode\r
+#define AT91C_CAN_MIDvA (0x7FF << 18) // (CAN_MB) Identifier for standard frame mode\r
+#define AT91C_CAN_MIDE (0x1 << 29) // (CAN_MB) Identifier Version\r
+// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- \r
+// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- \r
+// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- \r
+#define AT91C_CAN_MTIMESTAMP (0xFFFF << 0) // (CAN_MB) Timer Value\r
+#define AT91C_CAN_MDLC (0xF << 16) // (CAN_MB) Mailbox Data Length Code\r
+#define AT91C_CAN_MRTR (0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request\r
+#define AT91C_CAN_MABT (0x1 << 22) // (CAN_MB) Mailbox Message Abort\r
+#define AT91C_CAN_MRDY (0x1 << 23) // (CAN_MB) Mailbox Ready\r
+#define AT91C_CAN_MMI (0x1 << 24) // (CAN_MB) Mailbox Message Ignored\r
+// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- \r
+// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- \r
+// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- \r
+#define AT91C_CAN_MACR (0x1 << 22) // (CAN_MB) Abort Request for Mailbox\r
+#define AT91C_CAN_MTCR (0x1 << 23) // (CAN_MB) Mailbox Transfer Command\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Control Area Network Interface\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_CAN structure ***\r
+#define CAN_MR ( 0) // Mode Register\r
+#define CAN_IER ( 4) // Interrupt Enable Register\r
+#define CAN_IDR ( 8) // Interrupt Disable Register\r
+#define CAN_IMR (12) // Interrupt Mask Register\r
+#define CAN_SR (16) // Status Register\r
+#define CAN_BR (20) // Baudrate Register\r
+#define CAN_TIM (24) // Timer Register\r
+#define CAN_TIMESTP (28) // Time Stamp Register\r
+#define CAN_ECR (32) // Error Counter Register\r
+#define CAN_TCR (36) // Transfer Command Register\r
+#define CAN_ACR (40) // Abort Command Register\r
+#define CAN_VR (252) // Version Register\r
+#define CAN_MB0 (512) // CAN Mailbox 0\r
+#define CAN_MB1 (544) // CAN Mailbox 1\r
+#define CAN_MB2 (576) // CAN Mailbox 2\r
+#define CAN_MB3 (608) // CAN Mailbox 3\r
+#define CAN_MB4 (640) // CAN Mailbox 4\r
+#define CAN_MB5 (672) // CAN Mailbox 5\r
+#define CAN_MB6 (704) // CAN Mailbox 6\r
+#define CAN_MB7 (736) // CAN Mailbox 7\r
+#define CAN_MB8 (768) // CAN Mailbox 8\r
+#define CAN_MB9 (800) // CAN Mailbox 9\r
+#define CAN_MB10 (832) // CAN Mailbox 10\r
+#define CAN_MB11 (864) // CAN Mailbox 11\r
+#define CAN_MB12 (896) // CAN Mailbox 12\r
+#define CAN_MB13 (928) // CAN Mailbox 13\r
+#define CAN_MB14 (960) // CAN Mailbox 14\r
+#define CAN_MB15 (992) // CAN Mailbox 15\r
+// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- \r
+#define AT91C_CAN_CANEN (0x1 << 0) // (CAN) CAN Controller Enable\r
+#define AT91C_CAN_LPM (0x1 << 1) // (CAN) Disable/Enable Low Power Mode\r
+#define AT91C_CAN_ABM (0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode\r
+#define AT91C_CAN_OVL (0x1 << 3) // (CAN) Disable/Enable Overload Frame\r
+#define AT91C_CAN_TEOF (0x1 << 4) // (CAN) Time Stamp messages at each end of Frame\r
+#define AT91C_CAN_TTM (0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode\r
+#define AT91C_CAN_TIMFRZ (0x1 << 6) // (CAN) Enable Timer Freeze\r
+#define AT91C_CAN_DRPT (0x1 << 7) // (CAN) Disable Repeat\r
+// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- \r
+#define AT91C_CAN_MB0 (0x1 << 0) // (CAN) Mailbox 0 Flag\r
+#define AT91C_CAN_MB1 (0x1 << 1) // (CAN) Mailbox 1 Flag\r
+#define AT91C_CAN_MB2 (0x1 << 2) // (CAN) Mailbox 2 Flag\r
+#define AT91C_CAN_MB3 (0x1 << 3) // (CAN) Mailbox 3 Flag\r
+#define AT91C_CAN_MB4 (0x1 << 4) // (CAN) Mailbox 4 Flag\r
+#define AT91C_CAN_MB5 (0x1 << 5) // (CAN) Mailbox 5 Flag\r
+#define AT91C_CAN_MB6 (0x1 << 6) // (CAN) Mailbox 6 Flag\r
+#define AT91C_CAN_MB7 (0x1 << 7) // (CAN) Mailbox 7 Flag\r
+#define AT91C_CAN_MB8 (0x1 << 8) // (CAN) Mailbox 8 Flag\r
+#define AT91C_CAN_MB9 (0x1 << 9) // (CAN) Mailbox 9 Flag\r
+#define AT91C_CAN_MB10 (0x1 << 10) // (CAN) Mailbox 10 Flag\r
+#define AT91C_CAN_MB11 (0x1 << 11) // (CAN) Mailbox 11 Flag\r
+#define AT91C_CAN_MB12 (0x1 << 12) // (CAN) Mailbox 12 Flag\r
+#define AT91C_CAN_MB13 (0x1 << 13) // (CAN) Mailbox 13 Flag\r
+#define AT91C_CAN_MB14 (0x1 << 14) // (CAN) Mailbox 14 Flag\r
+#define AT91C_CAN_MB15 (0x1 << 15) // (CAN) Mailbox 15 Flag\r
+#define AT91C_CAN_ERRA (0x1 << 16) // (CAN) Error Active Mode Flag\r
+#define AT91C_CAN_WARN (0x1 << 17) // (CAN) Warning Limit Flag\r
+#define AT91C_CAN_ERRP (0x1 << 18) // (CAN) Error Passive Mode Flag\r
+#define AT91C_CAN_BOFF (0x1 << 19) // (CAN) Bus Off Mode Flag\r
+#define AT91C_CAN_SLEEP (0x1 << 20) // (CAN) Sleep Flag\r
+#define AT91C_CAN_WAKEUP (0x1 << 21) // (CAN) Wakeup Flag\r
+#define AT91C_CAN_TOVF (0x1 << 22) // (CAN) Timer Overflow Flag\r
+#define AT91C_CAN_TSTP (0x1 << 23) // (CAN) Timestamp Flag\r
+#define AT91C_CAN_CERR (0x1 << 24) // (CAN) CRC Error\r
+#define AT91C_CAN_SERR (0x1 << 25) // (CAN) Stuffing Error\r
+#define AT91C_CAN_AERR (0x1 << 26) // (CAN) Acknowledgment Error\r
+#define AT91C_CAN_FERR (0x1 << 27) // (CAN) Form Error\r
+#define AT91C_CAN_BERR (0x1 << 28) // (CAN) Bit Error\r
+// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- \r
+// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- \r
+// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- \r
+#define AT91C_CAN_RBSY (0x1 << 29) // (CAN) Receiver Busy\r
+#define AT91C_CAN_TBSY (0x1 << 30) // (CAN) Transmitter Busy\r
+#define AT91C_CAN_OVLY (0x1 << 31) // (CAN) Overload Busy\r
+// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- \r
+#define AT91C_CAN_PHASE2 (0x7 << 0) // (CAN) Phase 2 segment\r
+#define AT91C_CAN_PHASE1 (0x7 << 4) // (CAN) Phase 1 segment\r
+#define AT91C_CAN_PROPAG (0x7 << 8) // (CAN) Programmation time segment\r
+#define AT91C_CAN_SYNC (0x3 << 12) // (CAN) Re-synchronization jump width segment\r
+#define AT91C_CAN_BRP (0x7F << 16) // (CAN) Baudrate Prescaler\r
+#define AT91C_CAN_SMP (0x1 << 24) // (CAN) Sampling mode\r
+// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- \r
+#define AT91C_CAN_TIMER (0xFFFF << 0) // (CAN) Timer field\r
+// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- \r
+// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- \r
+#define AT91C_CAN_REC (0xFF << 0) // (CAN) Receive Error Counter\r
+#define AT91C_CAN_TEC (0xFF << 16) // (CAN) Transmit Error Counter\r
+// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- \r
+#define AT91C_CAN_TIMRST (0x1 << 31) // (CAN) Timer Reset Field\r
+// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_EMAC structure ***\r
+#define EMAC_NCR ( 0) // Network Control Register\r
+#define EMAC_NCFGR ( 4) // Network Configuration Register\r
+#define EMAC_NSR ( 8) // Network Status Register\r
+#define EMAC_TSR (20) // Transmit Status Register\r
+#define EMAC_RBQP (24) // Receive Buffer Queue Pointer\r
+#define EMAC_TBQP (28) // Transmit Buffer Queue Pointer\r
+#define EMAC_RSR (32) // Receive Status Register\r
+#define EMAC_ISR (36) // Interrupt Status Register\r
+#define EMAC_IER (40) // Interrupt Enable Register\r
+#define EMAC_IDR (44) // Interrupt Disable Register\r
+#define EMAC_IMR (48) // Interrupt Mask Register\r
+#define EMAC_MAN (52) // PHY Maintenance Register\r
+#define EMAC_PTR (56) // Pause Time Register\r
+#define EMAC_PFR (60) // Pause Frames received Register\r
+#define EMAC_FTO (64) // Frames Transmitted OK Register\r
+#define EMAC_SCF (68) // Single Collision Frame Register\r
+#define EMAC_MCF (72) // Multiple Collision Frame Register\r
+#define EMAC_FRO (76) // Frames Received OK Register\r
+#define EMAC_FCSE (80) // Frame Check Sequence Error Register\r
+#define EMAC_ALE (84) // Alignment Error Register\r
+#define EMAC_DTF (88) // Deferred Transmission Frame Register\r
+#define EMAC_LCOL (92) // Late Collision Register\r
+#define EMAC_ECOL (96) // Excessive Collision Register\r
+#define EMAC_TUND (100) // Transmit Underrun Error Register\r
+#define EMAC_CSE (104) // Carrier Sense Error Register\r
+#define EMAC_RRE (108) // Receive Ressource Error Register\r
+#define EMAC_ROV (112) // Receive Overrun Errors Register\r
+#define EMAC_RSE (116) // Receive Symbol Errors Register\r
+#define EMAC_ELE (120) // Excessive Length Errors Register\r
+#define EMAC_RJA (124) // Receive Jabbers Register\r
+#define EMAC_USF (128) // Undersize Frames Register\r
+#define EMAC_STE (132) // SQE Test Error Register\r
+#define EMAC_RLE (136) // Receive Length Field Mismatch Register\r
+#define EMAC_TPF (140) // Transmitted Pause Frames Register\r
+#define EMAC_HRB (144) // Hash Address Bottom[31:0]\r
+#define EMAC_HRT (148) // Hash Address Top[63:32]\r
+#define EMAC_SA1L (152) // Specific Address 1 Bottom, First 4 bytes\r
+#define EMAC_SA1H (156) // Specific Address 1 Top, Last 2 bytes\r
+#define EMAC_SA2L (160) // Specific Address 2 Bottom, First 4 bytes\r
+#define EMAC_SA2H (164) // Specific Address 2 Top, Last 2 bytes\r
+#define EMAC_SA3L (168) // Specific Address 3 Bottom, First 4 bytes\r
+#define EMAC_SA3H (172) // Specific Address 3 Top, Last 2 bytes\r
+#define EMAC_SA4L (176) // Specific Address 4 Bottom, First 4 bytes\r
+#define EMAC_SA4H (180) // Specific Address 4 Top, Last 2 bytes\r
+#define EMAC_TID (184) // Type ID Checking Register\r
+#define EMAC_TPQ (188) // Transmit Pause Quantum Register\r
+#define EMAC_USRIO (192) // USER Input/Output Register\r
+#define EMAC_WOL (196) // Wake On LAN Register\r
+#define EMAC_REV (252) // Revision Register\r
+// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- \r
+#define AT91C_EMAC_LB (0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.\r
+#define AT91C_EMAC_LLB (0x1 << 1) // (EMAC) Loopback local. \r
+#define AT91C_EMAC_RE (0x1 << 2) // (EMAC) Receive enable. \r
+#define AT91C_EMAC_TE (0x1 << 3) // (EMAC) Transmit enable. \r
+#define AT91C_EMAC_MPE (0x1 << 4) // (EMAC) Management port enable. \r
+#define AT91C_EMAC_CLRSTAT (0x1 << 5) // (EMAC) Clear statistics registers. \r
+#define AT91C_EMAC_INCSTAT (0x1 << 6) // (EMAC) Increment statistics registers. \r
+#define AT91C_EMAC_WESTAT (0x1 << 7) // (EMAC) Write enable for statistics registers. \r
+#define AT91C_EMAC_BP (0x1 << 8) // (EMAC) Back pressure. \r
+#define AT91C_EMAC_TSTART (0x1 << 9) // (EMAC) Start Transmission. \r
+#define AT91C_EMAC_THALT (0x1 << 10) // (EMAC) Transmission Halt. \r
+#define AT91C_EMAC_TPFR (0x1 << 11) // (EMAC) Transmit pause frame \r
+#define AT91C_EMAC_TZQ (0x1 << 12) // (EMAC) Transmit zero quantum pause frame\r
+// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- \r
+#define AT91C_EMAC_SPD (0x1 << 0) // (EMAC) Speed. \r
+#define AT91C_EMAC_FD (0x1 << 1) // (EMAC) Full duplex. \r
+#define AT91C_EMAC_JFRAME (0x1 << 3) // (EMAC) Jumbo Frames. \r
+#define AT91C_EMAC_CAF (0x1 << 4) // (EMAC) Copy all frames. \r
+#define AT91C_EMAC_NBC (0x1 << 5) // (EMAC) No broadcast. \r
+#define AT91C_EMAC_MTI (0x1 << 6) // (EMAC) Multicast hash event enable\r
+#define AT91C_EMAC_UNI (0x1 << 7) // (EMAC) Unicast hash enable. \r
+#define AT91C_EMAC_BIG (0x1 << 8) // (EMAC) Receive 1522 bytes. \r
+#define AT91C_EMAC_EAE (0x1 << 9) // (EMAC) External address match enable. \r
+#define AT91C_EMAC_CLK (0x3 << 10) // (EMAC) \r
+#define AT91C_EMAC_CLK_HCLK_8 (0x0 << 10) // (EMAC) HCLK divided by 8\r
+#define AT91C_EMAC_CLK_HCLK_16 (0x1 << 10) // (EMAC) HCLK divided by 16\r
+#define AT91C_EMAC_CLK_HCLK_32 (0x2 << 10) // (EMAC) HCLK divided by 32\r
+#define AT91C_EMAC_CLK_HCLK_64 (0x3 << 10) // (EMAC) HCLK divided by 64\r
+#define AT91C_EMAC_RTY (0x1 << 12) // (EMAC) \r
+#define AT91C_EMAC_PAE (0x1 << 13) // (EMAC) \r
+#define AT91C_EMAC_RBOF (0x3 << 14) // (EMAC) \r
+#define AT91C_EMAC_RBOF_OFFSET_0 (0x0 << 14) // (EMAC) no offset from start of receive buffer\r
+#define AT91C_EMAC_RBOF_OFFSET_1 (0x1 << 14) // (EMAC) one byte offset from start of receive buffer\r
+#define AT91C_EMAC_RBOF_OFFSET_2 (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer\r
+#define AT91C_EMAC_RBOF_OFFSET_3 (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer\r
+#define AT91C_EMAC_RLCE (0x1 << 16) // (EMAC) Receive Length field Checking Enable\r
+#define AT91C_EMAC_DRFCS (0x1 << 17) // (EMAC) Discard Receive FCS\r
+#define AT91C_EMAC_EFRHD (0x1 << 18) // (EMAC) \r
+#define AT91C_EMAC_IRXFCS (0x1 << 19) // (EMAC) Ignore RX FCS\r
+// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- \r
+#define AT91C_EMAC_LINKR (0x1 << 0) // (EMAC) \r
+#define AT91C_EMAC_MDIO (0x1 << 1) // (EMAC) \r
+#define AT91C_EMAC_IDLE (0x1 << 2) // (EMAC) \r
+// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- \r
+#define AT91C_EMAC_UBR (0x1 << 0) // (EMAC) \r
+#define AT91C_EMAC_COL (0x1 << 1) // (EMAC) \r
+#define AT91C_EMAC_RLES (0x1 << 2) // (EMAC) \r
+#define AT91C_EMAC_TGO (0x1 << 3) // (EMAC) Transmit Go\r
+#define AT91C_EMAC_BEX (0x1 << 4) // (EMAC) Buffers exhausted mid frame\r
+#define AT91C_EMAC_COMP (0x1 << 5) // (EMAC) \r
+#define AT91C_EMAC_UND (0x1 << 6) // (EMAC) \r
+// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- \r
+#define AT91C_EMAC_BNA (0x1 << 0) // (EMAC) \r
+#define AT91C_EMAC_REC (0x1 << 1) // (EMAC) \r
+#define AT91C_EMAC_OVR (0x1 << 2) // (EMAC) \r
+// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- \r
+#define AT91C_EMAC_MFD (0x1 << 0) // (EMAC) \r
+#define AT91C_EMAC_RCOMP (0x1 << 1) // (EMAC) \r
+#define AT91C_EMAC_RXUBR (0x1 << 2) // (EMAC) \r
+#define AT91C_EMAC_TXUBR (0x1 << 3) // (EMAC) \r
+#define AT91C_EMAC_TUNDR (0x1 << 4) // (EMAC) \r
+#define AT91C_EMAC_RLEX (0x1 << 5) // (EMAC) \r
+#define AT91C_EMAC_TXERR (0x1 << 6) // (EMAC) \r
+#define AT91C_EMAC_TCOMP (0x1 << 7) // (EMAC) \r
+#define AT91C_EMAC_LINK (0x1 << 9) // (EMAC) \r
+#define AT91C_EMAC_ROVR (0x1 << 10) // (EMAC) \r
+#define AT91C_EMAC_HRESP (0x1 << 11) // (EMAC) \r
+#define AT91C_EMAC_PFRE (0x1 << 12) // (EMAC) \r
+#define AT91C_EMAC_PTZ (0x1 << 13) // (EMAC) \r
+// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- \r
+// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- \r
+// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- \r
+// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- \r
+#define AT91C_EMAC_DATA (0xFFFF << 0) // (EMAC) \r
+#define AT91C_EMAC_CODE (0x3 << 16) // (EMAC) \r
+#define AT91C_EMAC_REGA (0x1F << 18) // (EMAC) \r
+#define AT91C_EMAC_PHYA (0x1F << 23) // (EMAC) \r
+#define AT91C_EMAC_RW (0x3 << 28) // (EMAC) \r
+#define AT91C_EMAC_SOF (0x3 << 30) // (EMAC) \r
+// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- \r
+#define AT91C_EMAC_RMII (0x1 << 0) // (EMAC) Reduce MII\r
+// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- \r
+#define AT91C_EMAC_IP (0xFFFF << 0) // (EMAC) ARP request IP address\r
+#define AT91C_EMAC_MAG (0x1 << 16) // (EMAC) Magic packet event enable\r
+#define AT91C_EMAC_ARP (0x1 << 17) // (EMAC) ARP request event enable\r
+#define AT91C_EMAC_SA1 (0x1 << 18) // (EMAC) Specific address register 1 event enable\r
+// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- \r
+#define AT91C_EMAC_REVREF (0xFFFF << 0) // (EMAC) \r
+#define AT91C_EMAC_PARTREF (0xFFFF << 16) // (EMAC) \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Analog to Digital Convertor\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_ADC structure ***\r
+#define ADC_CR ( 0) // ADC Control Register\r
+#define ADC_MR ( 4) // ADC Mode Register\r
+#define ADC_CHER (16) // ADC Channel Enable Register\r
+#define ADC_CHDR (20) // ADC Channel Disable Register\r
+#define ADC_CHSR (24) // ADC Channel Status Register\r
+#define ADC_SR (28) // ADC Status Register\r
+#define ADC_LCDR (32) // ADC Last Converted Data Register\r
+#define ADC_IER (36) // ADC Interrupt Enable Register\r
+#define ADC_IDR (40) // ADC Interrupt Disable Register\r
+#define ADC_IMR (44) // ADC Interrupt Mask Register\r
+#define ADC_CDR0 (48) // ADC Channel Data Register 0\r
+#define ADC_CDR1 (52) // ADC Channel Data Register 1\r
+#define ADC_CDR2 (56) // ADC Channel Data Register 2\r
+#define ADC_CDR3 (60) // ADC Channel Data Register 3\r
+#define ADC_CDR4 (64) // ADC Channel Data Register 4\r
+#define ADC_CDR5 (68) // ADC Channel Data Register 5\r
+#define ADC_CDR6 (72) // ADC Channel Data Register 6\r
+#define ADC_CDR7 (76) // ADC Channel Data Register 7\r
+#define ADC_RPR (256) // Receive Pointer Register\r
+#define ADC_RCR (260) // Receive Counter Register\r
+#define ADC_TPR (264) // Transmit Pointer Register\r
+#define ADC_TCR (268) // Transmit Counter Register\r
+#define ADC_RNPR (272) // Receive Next Pointer Register\r
+#define ADC_RNCR (276) // Receive Next Counter Register\r
+#define ADC_TNPR (280) // Transmit Next Pointer Register\r
+#define ADC_TNCR (284) // Transmit Next Counter Register\r
+#define ADC_PTCR (288) // PDC Transfer Control Register\r
+#define ADC_PTSR (292) // PDC Transfer Status Register\r
+// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- \r
+#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset\r
+#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion\r
+// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- \r
+#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable\r
+#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software\r
+#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.\r
+#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection\r
+#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0\r
+#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1\r
+#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2\r
+#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3\r
+#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4\r
+#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5\r
+#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger\r
+#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution.\r
+#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution\r
+#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution\r
+#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode\r
+#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode\r
+#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode\r
+#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection\r
+#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time\r
+#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time\r
+// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- \r
+#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0\r
+#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1\r
+#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2\r
+#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3\r
+#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4\r
+#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5\r
+#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6\r
+#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7\r
+// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- \r
+// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- \r
+// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- \r
+#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion\r
+#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error\r
+#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready\r
+#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun\r
+#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer\r
+#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt\r
+// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- \r
+#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted\r
+// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- \r
+// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- \r
+// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- \r
+// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- \r
+#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data\r
+// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- \r
+// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- \r
+// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- \r
+// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- \r
+// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- \r
+// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- \r
+// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Advanced Encryption Standard\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_AES structure ***\r
+#define AES_CR ( 0) // Control Register\r
+#define AES_MR ( 4) // Mode Register\r
+#define AES_IER (16) // Interrupt Enable Register\r
+#define AES_IDR (20) // Interrupt Disable Register\r
+#define AES_IMR (24) // Interrupt Mask Register\r
+#define AES_ISR (28) // Interrupt Status Register\r
+#define AES_KEYWxR (32) // Key Word x Register\r
+#define AES_IDATAxR (64) // Input Data x Register\r
+#define AES_ODATAxR (80) // Output Data x Register\r
+#define AES_IVxR (96) // Initialization Vector x Register\r
+#define AES_VR (252) // AES Version Register\r
+#define AES_RPR (256) // Receive Pointer Register\r
+#define AES_RCR (260) // Receive Counter Register\r
+#define AES_TPR (264) // Transmit Pointer Register\r
+#define AES_TCR (268) // Transmit Counter Register\r
+#define AES_RNPR (272) // Receive Next Pointer Register\r
+#define AES_RNCR (276) // Receive Next Counter Register\r
+#define AES_TNPR (280) // Transmit Next Pointer Register\r
+#define AES_TNCR (284) // Transmit Next Counter Register\r
+#define AES_PTCR (288) // PDC Transfer Control Register\r
+#define AES_PTSR (292) // PDC Transfer Status Register\r
+// -------- AES_CR : (AES Offset: 0x0) Control Register -------- \r
+#define AT91C_AES_START (0x1 << 0) // (AES) Starts Processing\r
+#define AT91C_AES_SWRST (0x1 << 8) // (AES) Software Reset\r
+#define AT91C_AES_LOADSEED (0x1 << 16) // (AES) Random Number Generator Seed Loading\r
+// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- \r
+#define AT91C_AES_CIPHER (0x1 << 0) // (AES) Processing Mode\r
+#define AT91C_AES_PROCDLY (0xF << 4) // (AES) Processing Delay\r
+#define AT91C_AES_SMOD (0x3 << 8) // (AES) Start Mode\r
+#define AT91C_AES_SMOD_MANUAL (0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.\r
+#define AT91C_AES_SMOD_AUTO (0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).\r
+#define AT91C_AES_SMOD_PDC (0x2 << 8) // (AES) PDC Mode (cf datasheet).\r
+#define AT91C_AES_OPMOD (0x7 << 12) // (AES) Operation Mode\r
+#define AT91C_AES_OPMOD_ECB (0x0 << 12) // (AES) ECB Electronic CodeBook mode.\r
+#define AT91C_AES_OPMOD_CBC (0x1 << 12) // (AES) CBC Cipher Block Chaining mode.\r
+#define AT91C_AES_OPMOD_OFB (0x2 << 12) // (AES) OFB Output Feedback mode.\r
+#define AT91C_AES_OPMOD_CFB (0x3 << 12) // (AES) CFB Cipher Feedback mode.\r
+#define AT91C_AES_OPMOD_CTR (0x4 << 12) // (AES) CTR Counter mode.\r
+#define AT91C_AES_LOD (0x1 << 15) // (AES) Last Output Data Mode\r
+#define AT91C_AES_CFBS (0x7 << 16) // (AES) Cipher Feedback Data Size\r
+#define AT91C_AES_CFBS_128_BIT (0x0 << 16) // (AES) 128-bit.\r
+#define AT91C_AES_CFBS_64_BIT (0x1 << 16) // (AES) 64-bit.\r
+#define AT91C_AES_CFBS_32_BIT (0x2 << 16) // (AES) 32-bit.\r
+#define AT91C_AES_CFBS_16_BIT (0x3 << 16) // (AES) 16-bit.\r
+#define AT91C_AES_CFBS_8_BIT (0x4 << 16) // (AES) 8-bit.\r
+#define AT91C_AES_CKEY (0xF << 20) // (AES) Countermeasure Key\r
+#define AT91C_AES_CTYPE (0x1F << 24) // (AES) Countermeasure Type\r
+#define AT91C_AES_CTYPE_TYPE1_EN (0x1 << 24) // (AES) Countermeasure type 1 is enabled.\r
+#define AT91C_AES_CTYPE_TYPE2_EN (0x2 << 24) // (AES) Countermeasure type 2 is enabled.\r
+#define AT91C_AES_CTYPE_TYPE3_EN (0x4 << 24) // (AES) Countermeasure type 3 is enabled.\r
+#define AT91C_AES_CTYPE_TYPE4_EN (0x8 << 24) // (AES) Countermeasure type 4 is enabled.\r
+#define AT91C_AES_CTYPE_TYPE5_EN (0x10 << 24) // (AES) Countermeasure type 5 is enabled.\r
+// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- \r
+#define AT91C_AES_DATRDY (0x1 << 0) // (AES) DATRDY\r
+#define AT91C_AES_ENDRX (0x1 << 1) // (AES) PDC Read Buffer End\r
+#define AT91C_AES_ENDTX (0x1 << 2) // (AES) PDC Write Buffer End\r
+#define AT91C_AES_RXBUFF (0x1 << 3) // (AES) PDC Read Buffer Full\r
+#define AT91C_AES_TXBUFE (0x1 << 4) // (AES) PDC Write Buffer Empty\r
+#define AT91C_AES_URAD (0x1 << 8) // (AES) Unspecified Register Access Detection\r
+// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- \r
+// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- \r
+// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- \r
+#define AT91C_AES_URAT (0x7 << 12) // (AES) Unspecified Register Access Type Status\r
+#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC (0x0 << 12) // (AES) Input data register written during the data processing in PDC mode.\r
+#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC (0x1 << 12) // (AES) Output data register read during the data processing.\r
+#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC (0x2 << 12) // (AES) Mode register written during the data processing.\r
+#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY (0x3 << 12) // (AES) Output data register read during the sub-keys generation.\r
+#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY (0x4 << 12) // (AES) Mode register written during the sub-keys generation.\r
+#define AT91C_AES_URAT_WO_REG_READ (0x5 << 12) // (AES) Write-only register read access.\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard\r
+// *****************************************************************************\r
+// *** Register offset in AT91S_TDES structure ***\r
+#define TDES_CR ( 0) // Control Register\r
+#define TDES_MR ( 4) // Mode Register\r
+#define TDES_IER (16) // Interrupt Enable Register\r
+#define TDES_IDR (20) // Interrupt Disable Register\r
+#define TDES_IMR (24) // Interrupt Mask Register\r
+#define TDES_ISR (28) // Interrupt Status Register\r
+#define TDES_KEY1WxR (32) // Key 1 Word x Register\r
+#define TDES_KEY2WxR (40) // Key 2 Word x Register\r
+#define TDES_KEY3WxR (48) // Key 3 Word x Register\r
+#define TDES_IDATAxR (64) // Input Data x Register\r
+#define TDES_ODATAxR (80) // Output Data x Register\r
+#define TDES_IVxR (96) // Initialization Vector x Register\r
+#define TDES_VR (252) // TDES Version Register\r
+#define TDES_RPR (256) // Receive Pointer Register\r
+#define TDES_RCR (260) // Receive Counter Register\r
+#define TDES_TPR (264) // Transmit Pointer Register\r
+#define TDES_TCR (268) // Transmit Counter Register\r
+#define TDES_RNPR (272) // Receive Next Pointer Register\r
+#define TDES_RNCR (276) // Receive Next Counter Register\r
+#define TDES_TNPR (280) // Transmit Next Pointer Register\r
+#define TDES_TNCR (284) // Transmit Next Counter Register\r
+#define TDES_PTCR (288) // PDC Transfer Control Register\r
+#define TDES_PTSR (292) // PDC Transfer Status Register\r
+// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- \r
+#define AT91C_TDES_START (0x1 << 0) // (TDES) Starts Processing\r
+#define AT91C_TDES_SWRST (0x1 << 8) // (TDES) Software Reset\r
+// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- \r
+#define AT91C_TDES_CIPHER (0x1 << 0) // (TDES) Processing Mode\r
+#define AT91C_TDES_TDESMOD (0x1 << 1) // (TDES) Single or Triple DES Mode\r
+#define AT91C_TDES_KEYMOD (0x1 << 4) // (TDES) Key Mode\r
+#define AT91C_TDES_SMOD (0x3 << 8) // (TDES) Start Mode\r
+#define AT91C_TDES_SMOD_MANUAL (0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.\r
+#define AT91C_TDES_SMOD_AUTO (0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).\r
+#define AT91C_TDES_SMOD_PDC (0x2 << 8) // (TDES) PDC Mode (cf datasheet).\r
+#define AT91C_TDES_OPMOD (0x3 << 12) // (TDES) Operation Mode\r
+#define AT91C_TDES_OPMOD_ECB (0x0 << 12) // (TDES) ECB Electronic CodeBook mode.\r
+#define AT91C_TDES_OPMOD_CBC (0x1 << 12) // (TDES) CBC Cipher Block Chaining mode.\r
+#define AT91C_TDES_OPMOD_OFB (0x2 << 12) // (TDES) OFB Output Feedback mode.\r
+#define AT91C_TDES_OPMOD_CFB (0x3 << 12) // (TDES) CFB Cipher Feedback mode.\r
+#define AT91C_TDES_LOD (0x1 << 15) // (TDES) Last Output Data Mode\r
+#define AT91C_TDES_CFBS (0x3 << 16) // (TDES) Cipher Feedback Data Size\r
+#define AT91C_TDES_CFBS_64_BIT (0x0 << 16) // (TDES) 64-bit.\r
+#define AT91C_TDES_CFBS_32_BIT (0x1 << 16) // (TDES) 32-bit.\r
+#define AT91C_TDES_CFBS_16_BIT (0x2 << 16) // (TDES) 16-bit.\r
+#define AT91C_TDES_CFBS_8_BIT (0x3 << 16) // (TDES) 8-bit.\r
+// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- \r
+#define AT91C_TDES_DATRDY (0x1 << 0) // (TDES) DATRDY\r
+#define AT91C_TDES_ENDRX (0x1 << 1) // (TDES) PDC Read Buffer End\r
+#define AT91C_TDES_ENDTX (0x1 << 2) // (TDES) PDC Write Buffer End\r
+#define AT91C_TDES_RXBUFF (0x1 << 3) // (TDES) PDC Read Buffer Full\r
+#define AT91C_TDES_TXBUFE (0x1 << 4) // (TDES) PDC Write Buffer Empty\r
+#define AT91C_TDES_URAD (0x1 << 8) // (TDES) Unspecified Register Access Detection\r
+// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- \r
+// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- \r
+// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- \r
+#define AT91C_TDES_URAT (0x3 << 12) // (TDES) Unspecified Register Access Type Status\r
+#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC (0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode.\r
+#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC (0x1 << 12) // (TDES) Output data register read during the data processing.\r
+#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC (0x2 << 12) // (TDES) Mode register written during the data processing.\r
+#define AT91C_TDES_URAT_WO_REG_READ (0x3 << 12) // (TDES) Write-only register read access.\r
+\r
+// *****************************************************************************\r
+// REGISTER ADDRESS DEFINITION FOR AT91SAM7X256\r
+// *****************************************************************************\r
+// ========== Register definition for SYS peripheral ========== \r
+// ========== Register definition for AIC peripheral ========== \r
+#define AT91C_AIC_IVR (0xFFFFF100) // (AIC) IRQ Vector Register\r
+#define AT91C_AIC_SMR (0xFFFFF000) // (AIC) Source Mode Register\r
+#define AT91C_AIC_FVR (0xFFFFF104) // (AIC) FIQ Vector Register\r
+#define AT91C_AIC_DCR (0xFFFFF138) // (AIC) Debug Control Register (Protect)\r
+#define AT91C_AIC_EOICR (0xFFFFF130) // (AIC) End of Interrupt Command Register\r
+#define AT91C_AIC_SVR (0xFFFFF080) // (AIC) Source Vector Register\r
+#define AT91C_AIC_FFSR (0xFFFFF148) // (AIC) Fast Forcing Status Register\r
+#define AT91C_AIC_ICCR (0xFFFFF128) // (AIC) Interrupt Clear Command Register\r
+#define AT91C_AIC_ISR (0xFFFFF108) // (AIC) Interrupt Status Register\r
+#define AT91C_AIC_IMR (0xFFFFF110) // (AIC) Interrupt Mask Register\r
+#define AT91C_AIC_IPR (0xFFFFF10C) // (AIC) Interrupt Pending Register\r
+#define AT91C_AIC_FFER (0xFFFFF140) // (AIC) Fast Forcing Enable Register\r
+#define AT91C_AIC_IECR (0xFFFFF120) // (AIC) Interrupt Enable Command Register\r
+#define AT91C_AIC_ISCR (0xFFFFF12C) // (AIC) Interrupt Set Command Register\r
+#define AT91C_AIC_FFDR (0xFFFFF144) // (AIC) Fast Forcing Disable Register\r
+#define AT91C_AIC_CISR (0xFFFFF114) // (AIC) Core Interrupt Status Register\r
+#define AT91C_AIC_IDCR (0xFFFFF124) // (AIC) Interrupt Disable Command Register\r
+#define AT91C_AIC_SPU (0xFFFFF134) // (AIC) Spurious Vector Register\r
+// ========== Register definition for PDC_DBGU peripheral ========== \r
+#define AT91C_DBGU_TCR (0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register\r
+#define AT91C_DBGU_RNPR (0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register\r
+#define AT91C_DBGU_TNPR (0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register\r
+#define AT91C_DBGU_TPR (0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register\r
+#define AT91C_DBGU_RPR (0xFFFFF300) // (PDC_DBGU) Receive Pointer Register\r
+#define AT91C_DBGU_RCR (0xFFFFF304) // (PDC_DBGU) Receive Counter Register\r
+#define AT91C_DBGU_RNCR (0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register\r
+#define AT91C_DBGU_PTCR (0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register\r
+#define AT91C_DBGU_PTSR (0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register\r
+#define AT91C_DBGU_TNCR (0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register\r
+// ========== Register definition for DBGU peripheral ========== \r
+#define AT91C_DBGU_EXID (0xFFFFF244) // (DBGU) Chip ID Extension Register\r
+#define AT91C_DBGU_BRGR (0xFFFFF220) // (DBGU) Baud Rate Generator Register\r
+#define AT91C_DBGU_IDR (0xFFFFF20C) // (DBGU) Interrupt Disable Register\r
+#define AT91C_DBGU_CSR (0xFFFFF214) // (DBGU) Channel Status Register\r
+#define AT91C_DBGU_CIDR (0xFFFFF240) // (DBGU) Chip ID Register\r
+#define AT91C_DBGU_MR (0xFFFFF204) // (DBGU) Mode Register\r
+#define AT91C_DBGU_IMR (0xFFFFF210) // (DBGU) Interrupt Mask Register\r
+#define AT91C_DBGU_CR (0xFFFFF200) // (DBGU) Control Register\r
+#define AT91C_DBGU_FNTR (0xFFFFF248) // (DBGU) Force NTRST Register\r
+#define AT91C_DBGU_THR (0xFFFFF21C) // (DBGU) Transmitter Holding Register\r
+#define AT91C_DBGU_RHR (0xFFFFF218) // (DBGU) Receiver Holding Register\r
+#define AT91C_DBGU_IER (0xFFFFF208) // (DBGU) Interrupt Enable Register\r
+// ========== Register definition for PIOA peripheral ========== \r
+#define AT91C_PIOA_ODR (0xFFFFF414) // (PIOA) Output Disable Registerr\r
+#define AT91C_PIOA_SODR (0xFFFFF430) // (PIOA) Set Output Data Register\r
+#define AT91C_PIOA_ISR (0xFFFFF44C) // (PIOA) Interrupt Status Register\r
+#define AT91C_PIOA_ABSR (0xFFFFF478) // (PIOA) AB Select Status Register\r
+#define AT91C_PIOA_IER (0xFFFFF440) // (PIOA) Interrupt Enable Register\r
+#define AT91C_PIOA_PPUDR (0xFFFFF460) // (PIOA) Pull-up Disable Register\r
+#define AT91C_PIOA_IMR (0xFFFFF448) // (PIOA) Interrupt Mask Register\r
+#define AT91C_PIOA_PER (0xFFFFF400) // (PIOA) PIO Enable Register\r
+#define AT91C_PIOA_IFDR (0xFFFFF424) // (PIOA) Input Filter Disable Register\r
+#define AT91C_PIOA_OWDR (0xFFFFF4A4) // (PIOA) Output Write Disable Register\r
+#define AT91C_PIOA_MDSR (0xFFFFF458) // (PIOA) Multi-driver Status Register\r
+#define AT91C_PIOA_IDR (0xFFFFF444) // (PIOA) Interrupt Disable Register\r
+#define AT91C_PIOA_ODSR (0xFFFFF438) // (PIOA) Output Data Status Register\r
+#define AT91C_PIOA_PPUSR (0xFFFFF468) // (PIOA) Pull-up Status Register\r
+#define AT91C_PIOA_OWSR (0xFFFFF4A8) // (PIOA) Output Write Status Register\r
+#define AT91C_PIOA_BSR (0xFFFFF474) // (PIOA) Select B Register\r
+#define AT91C_PIOA_OWER (0xFFFFF4A0) // (PIOA) Output Write Enable Register\r
+#define AT91C_PIOA_IFER (0xFFFFF420) // (PIOA) Input Filter Enable Register\r
+#define AT91C_PIOA_PDSR (0xFFFFF43C) // (PIOA) Pin Data Status Register\r
+#define AT91C_PIOA_PPUER (0xFFFFF464) // (PIOA) Pull-up Enable Register\r
+#define AT91C_PIOA_OSR (0xFFFFF418) // (PIOA) Output Status Register\r
+#define AT91C_PIOA_ASR (0xFFFFF470) // (PIOA) Select A Register\r
+#define AT91C_PIOA_MDDR (0xFFFFF454) // (PIOA) Multi-driver Disable Register\r
+#define AT91C_PIOA_CODR (0xFFFFF434) // (PIOA) Clear Output Data Register\r
+#define AT91C_PIOA_MDER (0xFFFFF450) // (PIOA) Multi-driver Enable Register\r
+#define AT91C_PIOA_PDR (0xFFFFF404) // (PIOA) PIO Disable Register\r
+#define AT91C_PIOA_IFSR (0xFFFFF428) // (PIOA) Input Filter Status Register\r
+#define AT91C_PIOA_OER (0xFFFFF410) // (PIOA) Output Enable Register\r
+#define AT91C_PIOA_PSR (0xFFFFF408) // (PIOA) PIO Status Register\r
+// ========== Register definition for PIOB peripheral ========== \r
+#define AT91C_PIOB_OWDR (0xFFFFF6A4) // (PIOB) Output Write Disable Register\r
+#define AT91C_PIOB_MDER (0xFFFFF650) // (PIOB) Multi-driver Enable Register\r
+#define AT91C_PIOB_PPUSR (0xFFFFF668) // (PIOB) Pull-up Status Register\r
+#define AT91C_PIOB_IMR (0xFFFFF648) // (PIOB) Interrupt Mask Register\r
+#define AT91C_PIOB_ASR (0xFFFFF670) // (PIOB) Select A Register\r
+#define AT91C_PIOB_PPUDR (0xFFFFF660) // (PIOB) Pull-up Disable Register\r
+#define AT91C_PIOB_PSR (0xFFFFF608) // (PIOB) PIO Status Register\r
+#define AT91C_PIOB_IER (0xFFFFF640) // (PIOB) Interrupt Enable Register\r
+#define AT91C_PIOB_CODR (0xFFFFF634) // (PIOB) Clear Output Data Register\r
+#define AT91C_PIOB_OWER (0xFFFFF6A0) // (PIOB) Output Write Enable Register\r
+#define AT91C_PIOB_ABSR (0xFFFFF678) // (PIOB) AB Select Status Register\r
+#define AT91C_PIOB_IFDR (0xFFFFF624) // (PIOB) Input Filter Disable Register\r
+#define AT91C_PIOB_PDSR (0xFFFFF63C) // (PIOB) Pin Data Status Register\r
+#define AT91C_PIOB_IDR (0xFFFFF644) // (PIOB) Interrupt Disable Register\r
+#define AT91C_PIOB_OWSR (0xFFFFF6A8) // (PIOB) Output Write Status Register\r
+#define AT91C_PIOB_PDR (0xFFFFF604) // (PIOB) PIO Disable Register\r
+#define AT91C_PIOB_ODR (0xFFFFF614) // (PIOB) Output Disable Registerr\r
+#define AT91C_PIOB_IFSR (0xFFFFF628) // (PIOB) Input Filter Status Register\r
+#define AT91C_PIOB_PPUER (0xFFFFF664) // (PIOB) Pull-up Enable Register\r
+#define AT91C_PIOB_SODR (0xFFFFF630) // (PIOB) Set Output Data Register\r
+#define AT91C_PIOB_ISR (0xFFFFF64C) // (PIOB) Interrupt Status Register\r
+#define AT91C_PIOB_ODSR (0xFFFFF638) // (PIOB) Output Data Status Register\r
+#define AT91C_PIOB_OSR (0xFFFFF618) // (PIOB) Output Status Register\r
+#define AT91C_PIOB_MDSR (0xFFFFF658) // (PIOB) Multi-driver Status Register\r
+#define AT91C_PIOB_IFER (0xFFFFF620) // (PIOB) Input Filter Enable Register\r
+#define AT91C_PIOB_BSR (0xFFFFF674) // (PIOB) Select B Register\r
+#define AT91C_PIOB_MDDR (0xFFFFF654) // (PIOB) Multi-driver Disable Register\r
+#define AT91C_PIOB_OER (0xFFFFF610) // (PIOB) Output Enable Register\r
+#define AT91C_PIOB_PER (0xFFFFF600) // (PIOB) PIO Enable Register\r
+// ========== Register definition for CKGR peripheral ========== \r
+#define AT91C_CKGR_MOR (0xFFFFFC20) // (CKGR) Main Oscillator Register\r
+#define AT91C_CKGR_PLLR (0xFFFFFC2C) // (CKGR) PLL Register\r
+#define AT91C_CKGR_MCFR (0xFFFFFC24) // (CKGR) Main Clock Frequency Register\r
+// ========== Register definition for PMC peripheral ========== \r
+#define AT91C_PMC_IDR (0xFFFFFC64) // (PMC) Interrupt Disable Register\r
+#define AT91C_PMC_MOR (0xFFFFFC20) // (PMC) Main Oscillator Register\r
+#define AT91C_PMC_PLLR (0xFFFFFC2C) // (PMC) PLL Register\r
+#define AT91C_PMC_PCER (0xFFFFFC10) // (PMC) Peripheral Clock Enable Register\r
+#define AT91C_PMC_PCKR (0xFFFFFC40) // (PMC) Programmable Clock Register\r
+#define AT91C_PMC_MCKR (0xFFFFFC30) // (PMC) Master Clock Register\r
+#define AT91C_PMC_SCDR (0xFFFFFC04) // (PMC) System Clock Disable Register\r
+#define AT91C_PMC_PCDR (0xFFFFFC14) // (PMC) Peripheral Clock Disable Register\r
+#define AT91C_PMC_SCSR (0xFFFFFC08) // (PMC) System Clock Status Register\r
+#define AT91C_PMC_PCSR (0xFFFFFC18) // (PMC) Peripheral Clock Status Register\r
+#define AT91C_PMC_MCFR (0xFFFFFC24) // (PMC) Main Clock Frequency Register\r
+#define AT91C_PMC_SCER (0xFFFFFC00) // (PMC) System Clock Enable Register\r
+#define AT91C_PMC_IMR (0xFFFFFC6C) // (PMC) Interrupt Mask Register\r
+#define AT91C_PMC_IER (0xFFFFFC60) // (PMC) Interrupt Enable Register\r
+#define AT91C_PMC_SR (0xFFFFFC68) // (PMC) Status Register\r
+// ========== Register definition for RSTC peripheral ========== \r
+#define AT91C_RSTC_RCR (0xFFFFFD00) // (RSTC) Reset Control Register\r
+#define AT91C_RSTC_RMR (0xFFFFFD08) // (RSTC) Reset Mode Register\r
+#define AT91C_RSTC_RSR (0xFFFFFD04) // (RSTC) Reset Status Register\r
+// ========== Register definition for RTTC peripheral ========== \r
+#define AT91C_RTTC_RTSR (0xFFFFFD2C) // (RTTC) Real-time Status Register\r
+#define AT91C_RTTC_RTMR (0xFFFFFD20) // (RTTC) Real-time Mode Register\r
+#define AT91C_RTTC_RTVR (0xFFFFFD28) // (RTTC) Real-time Value Register\r
+#define AT91C_RTTC_RTAR (0xFFFFFD24) // (RTTC) Real-time Alarm Register\r
+// ========== Register definition for PITC peripheral ========== \r
+#define AT91C_PITC_PIVR (0xFFFFFD38) // (PITC) Period Interval Value Register\r
+#define AT91C_PITC_PISR (0xFFFFFD34) // (PITC) Period Interval Status Register\r
+#define AT91C_PITC_PIIR (0xFFFFFD3C) // (PITC) Period Interval Image Register\r
+#define AT91C_PITC_PIMR (0xFFFFFD30) // (PITC) Period Interval Mode Register\r
+// ========== Register definition for WDTC peripheral ========== \r
+#define AT91C_WDTC_WDCR (0xFFFFFD40) // (WDTC) Watchdog Control Register\r
+#define AT91C_WDTC_WDSR (0xFFFFFD48) // (WDTC) Watchdog Status Register\r
+#define AT91C_WDTC_WDMR (0xFFFFFD44) // (WDTC) Watchdog Mode Register\r
+// ========== Register definition for VREG peripheral ========== \r
+#define AT91C_VREG_MR (0xFFFFFD60) // (VREG) Voltage Regulator Mode Register\r
+// ========== Register definition for MC peripheral ========== \r
+#define AT91C_MC_ASR (0xFFFFFF04) // (MC) MC Abort Status Register\r
+#define AT91C_MC_RCR (0xFFFFFF00) // (MC) MC Remap Control Register\r
+#define AT91C_MC_FCR (0xFFFFFF64) // (MC) MC Flash Command Register\r
+#define AT91C_MC_AASR (0xFFFFFF08) // (MC) MC Abort Address Status Register\r
+#define AT91C_MC_FSR (0xFFFFFF68) // (MC) MC Flash Status Register\r
+#define AT91C_MC_FMR (0xFFFFFF60) // (MC) MC Flash Mode Register\r
+// ========== Register definition for PDC_SPI1 peripheral ========== \r
+#define AT91C_SPI1_PTCR (0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register\r
+#define AT91C_SPI1_RPR (0xFFFE4100) // (PDC_SPI1) Receive Pointer Register\r
+#define AT91C_SPI1_TNCR (0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register\r
+#define AT91C_SPI1_TPR (0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register\r
+#define AT91C_SPI1_TNPR (0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register\r
+#define AT91C_SPI1_TCR (0xFFFE410C) // (PDC_SPI1) Transmit Counter Register\r
+#define AT91C_SPI1_RCR (0xFFFE4104) // (PDC_SPI1) Receive Counter Register\r
+#define AT91C_SPI1_RNPR (0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register\r
+#define AT91C_SPI1_RNCR (0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register\r
+#define AT91C_SPI1_PTSR (0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register\r
+// ========== Register definition for SPI1 peripheral ========== \r
+#define AT91C_SPI1_IMR (0xFFFE401C) // (SPI1) Interrupt Mask Register\r
+#define AT91C_SPI1_IER (0xFFFE4014) // (SPI1) Interrupt Enable Register\r
+#define AT91C_SPI1_MR (0xFFFE4004) // (SPI1) Mode Register\r
+#define AT91C_SPI1_RDR (0xFFFE4008) // (SPI1) Receive Data Register\r
+#define AT91C_SPI1_IDR (0xFFFE4018) // (SPI1) Interrupt Disable Register\r
+#define AT91C_SPI1_SR (0xFFFE4010) // (SPI1) Status Register\r
+#define AT91C_SPI1_TDR (0xFFFE400C) // (SPI1) Transmit Data Register\r
+#define AT91C_SPI1_CR (0xFFFE4000) // (SPI1) Control Register\r
+#define AT91C_SPI1_CSR (0xFFFE4030) // (SPI1) Chip Select Register\r
+// ========== Register definition for PDC_SPI0 peripheral ========== \r
+#define AT91C_SPI0_PTCR (0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register\r
+#define AT91C_SPI0_TPR (0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register\r
+#define AT91C_SPI0_TCR (0xFFFE010C) // (PDC_SPI0) Transmit Counter Register\r
+#define AT91C_SPI0_RCR (0xFFFE0104) // (PDC_SPI0) Receive Counter Register\r
+#define AT91C_SPI0_PTSR (0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register\r
+#define AT91C_SPI0_RNPR (0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register\r
+#define AT91C_SPI0_RPR (0xFFFE0100) // (PDC_SPI0) Receive Pointer Register\r
+#define AT91C_SPI0_TNCR (0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register\r
+#define AT91C_SPI0_RNCR (0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register\r
+#define AT91C_SPI0_TNPR (0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register\r
+// ========== Register definition for SPI0 peripheral ========== \r
+#define AT91C_SPI0_IER (0xFFFE0014) // (SPI0) Interrupt Enable Register\r
+#define AT91C_SPI0_SR (0xFFFE0010) // (SPI0) Status Register\r
+#define AT91C_SPI0_IDR (0xFFFE0018) // (SPI0) Interrupt Disable Register\r
+#define AT91C_SPI0_CR (0xFFFE0000) // (SPI0) Control Register\r
+#define AT91C_SPI0_MR (0xFFFE0004) // (SPI0) Mode Register\r
+#define AT91C_SPI0_IMR (0xFFFE001C) // (SPI0) Interrupt Mask Register\r
+#define AT91C_SPI0_TDR (0xFFFE000C) // (SPI0) Transmit Data Register\r
+#define AT91C_SPI0_RDR (0xFFFE0008) // (SPI0) Receive Data Register\r
+#define AT91C_SPI0_CSR (0xFFFE0030) // (SPI0) Chip Select Register\r
+// ========== Register definition for PDC_US1 peripheral ========== \r
+#define AT91C_US1_RNCR (0xFFFC4114) // (PDC_US1) Receive Next Counter Register\r
+#define AT91C_US1_PTCR (0xFFFC4120) // (PDC_US1) PDC Transfer Control Register\r
+#define AT91C_US1_TCR (0xFFFC410C) // (PDC_US1) Transmit Counter Register\r
+#define AT91C_US1_PTSR (0xFFFC4124) // (PDC_US1) PDC Transfer Status Register\r
+#define AT91C_US1_TNPR (0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register\r
+#define AT91C_US1_RCR (0xFFFC4104) // (PDC_US1) Receive Counter Register\r
+#define AT91C_US1_RNPR (0xFFFC4110) // (PDC_US1) Receive Next Pointer Register\r
+#define AT91C_US1_RPR (0xFFFC4100) // (PDC_US1) Receive Pointer Register\r
+#define AT91C_US1_TNCR (0xFFFC411C) // (PDC_US1) Transmit Next Counter Register\r
+#define AT91C_US1_TPR (0xFFFC4108) // (PDC_US1) Transmit Pointer Register\r
+// ========== Register definition for US1 peripheral ========== \r
+#define AT91C_US1_IF (0xFFFC404C) // (US1) IRDA_FILTER Register\r
+#define AT91C_US1_NER (0xFFFC4044) // (US1) Nb Errors Register\r
+#define AT91C_US1_RTOR (0xFFFC4024) // (US1) Receiver Time-out Register\r
+#define AT91C_US1_CSR (0xFFFC4014) // (US1) Channel Status Register\r
+#define AT91C_US1_IDR (0xFFFC400C) // (US1) Interrupt Disable Register\r
+#define AT91C_US1_IER (0xFFFC4008) // (US1) Interrupt Enable Register\r
+#define AT91C_US1_THR (0xFFFC401C) // (US1) Transmitter Holding Register\r
+#define AT91C_US1_TTGR (0xFFFC4028) // (US1) Transmitter Time-guard Register\r
+#define AT91C_US1_RHR (0xFFFC4018) // (US1) Receiver Holding Register\r
+#define AT91C_US1_BRGR (0xFFFC4020) // (US1) Baud Rate Generator Register\r
+#define AT91C_US1_IMR (0xFFFC4010) // (US1) Interrupt Mask Register\r
+#define AT91C_US1_FIDI (0xFFFC4040) // (US1) FI_DI_Ratio Register\r
+#define AT91C_US1_CR (0xFFFC4000) // (US1) Control Register\r
+#define AT91C_US1_MR (0xFFFC4004) // (US1) Mode Register\r
+// ========== Register definition for PDC_US0 peripheral ========== \r
+#define AT91C_US0_TNPR (0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register\r
+#define AT91C_US0_RNPR (0xFFFC0110) // (PDC_US0) Receive Next Pointer Register\r
+#define AT91C_US0_TCR (0xFFFC010C) // (PDC_US0) Transmit Counter Register\r
+#define AT91C_US0_PTCR (0xFFFC0120) // (PDC_US0) PDC Transfer Control Register\r
+#define AT91C_US0_PTSR (0xFFFC0124) // (PDC_US0) PDC Transfer Status Register\r
+#define AT91C_US0_TNCR (0xFFFC011C) // (PDC_US0) Transmit Next Counter Register\r
+#define AT91C_US0_TPR (0xFFFC0108) // (PDC_US0) Transmit Pointer Register\r
+#define AT91C_US0_RCR (0xFFFC0104) // (PDC_US0) Receive Counter Register\r
+#define AT91C_US0_RPR (0xFFFC0100) // (PDC_US0) Receive Pointer Register\r
+#define AT91C_US0_RNCR (0xFFFC0114) // (PDC_US0) Receive Next Counter Register\r
+// ========== Register definition for US0 peripheral ========== \r
+#define AT91C_US0_BRGR (0xFFFC0020) // (US0) Baud Rate Generator Register\r
+#define AT91C_US0_NER (0xFFFC0044) // (US0) Nb Errors Register\r
+#define AT91C_US0_CR (0xFFFC0000) // (US0) Control Register\r
+#define AT91C_US0_IMR (0xFFFC0010) // (US0) Interrupt Mask Register\r
+#define AT91C_US0_FIDI (0xFFFC0040) // (US0) FI_DI_Ratio Register\r
+#define AT91C_US0_TTGR (0xFFFC0028) // (US0) Transmitter Time-guard Register\r
+#define AT91C_US0_MR (0xFFFC0004) // (US0) Mode Register\r
+#define AT91C_US0_RTOR (0xFFFC0024) // (US0) Receiver Time-out Register\r
+#define AT91C_US0_CSR (0xFFFC0014) // (US0) Channel Status Register\r
+#define AT91C_US0_RHR (0xFFFC0018) // (US0) Receiver Holding Register\r
+#define AT91C_US0_IDR (0xFFFC000C) // (US0) Interrupt Disable Register\r
+#define AT91C_US0_THR (0xFFFC001C) // (US0) Transmitter Holding Register\r
+#define AT91C_US0_IF (0xFFFC004C) // (US0) IRDA_FILTER Register\r
+#define AT91C_US0_IER (0xFFFC0008) // (US0) Interrupt Enable Register\r
+// ========== Register definition for PDC_SSC peripheral ========== \r
+#define AT91C_SSC_TNCR (0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register\r
+#define AT91C_SSC_RPR (0xFFFD4100) // (PDC_SSC) Receive Pointer Register\r
+#define AT91C_SSC_RNCR (0xFFFD4114) // (PDC_SSC) Receive Next Counter Register\r
+#define AT91C_SSC_TPR (0xFFFD4108) // (PDC_SSC) Transmit Pointer Register\r
+#define AT91C_SSC_PTCR (0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register\r
+#define AT91C_SSC_TCR (0xFFFD410C) // (PDC_SSC) Transmit Counter Register\r
+#define AT91C_SSC_RCR (0xFFFD4104) // (PDC_SSC) Receive Counter Register\r
+#define AT91C_SSC_RNPR (0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register\r
+#define AT91C_SSC_TNPR (0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register\r
+#define AT91C_SSC_PTSR (0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register\r
+// ========== Register definition for SSC peripheral ========== \r
+#define AT91C_SSC_RHR (0xFFFD4020) // (SSC) Receive Holding Register\r
+#define AT91C_SSC_RSHR (0xFFFD4030) // (SSC) Receive Sync Holding Register\r
+#define AT91C_SSC_TFMR (0xFFFD401C) // (SSC) Transmit Frame Mode Register\r
+#define AT91C_SSC_IDR (0xFFFD4048) // (SSC) Interrupt Disable Register\r
+#define AT91C_SSC_THR (0xFFFD4024) // (SSC) Transmit Holding Register\r
+#define AT91C_SSC_RCMR (0xFFFD4010) // (SSC) Receive Clock ModeRegister\r
+#define AT91C_SSC_IER (0xFFFD4044) // (SSC) Interrupt Enable Register\r
+#define AT91C_SSC_TSHR (0xFFFD4034) // (SSC) Transmit Sync Holding Register\r
+#define AT91C_SSC_SR (0xFFFD4040) // (SSC) Status Register\r
+#define AT91C_SSC_CMR (0xFFFD4004) // (SSC) Clock Mode Register\r
+#define AT91C_SSC_TCMR (0xFFFD4018) // (SSC) Transmit Clock Mode Register\r
+#define AT91C_SSC_CR (0xFFFD4000) // (SSC) Control Register\r
+#define AT91C_SSC_IMR (0xFFFD404C) // (SSC) Interrupt Mask Register\r
+#define AT91C_SSC_RFMR (0xFFFD4014) // (SSC) Receive Frame Mode Register\r
+// ========== Register definition for TWI peripheral ========== \r
+#define AT91C_TWI_IER (0xFFFB8024) // (TWI) Interrupt Enable Register\r
+#define AT91C_TWI_CR (0xFFFB8000) // (TWI) Control Register\r
+#define AT91C_TWI_SR (0xFFFB8020) // (TWI) Status Register\r
+#define AT91C_TWI_IMR (0xFFFB802C) // (TWI) Interrupt Mask Register\r
+#define AT91C_TWI_THR (0xFFFB8034) // (TWI) Transmit Holding Register\r
+#define AT91C_TWI_IDR (0xFFFB8028) // (TWI) Interrupt Disable Register\r
+#define AT91C_TWI_IADR (0xFFFB800C) // (TWI) Internal Address Register\r
+#define AT91C_TWI_MMR (0xFFFB8004) // (TWI) Master Mode Register\r
+#define AT91C_TWI_CWGR (0xFFFB8010) // (TWI) Clock Waveform Generator Register\r
+#define AT91C_TWI_RHR (0xFFFB8030) // (TWI) Receive Holding Register\r
+// ========== Register definition for PWMC_CH3 peripheral ========== \r
+#define AT91C_PWMC_CH3_CUPDR (0xFFFCC270) // (PWMC_CH3) Channel Update Register\r
+#define AT91C_PWMC_CH3_Reserved (0xFFFCC274) // (PWMC_CH3) Reserved\r
+#define AT91C_PWMC_CH3_CPRDR (0xFFFCC268) // (PWMC_CH3) Channel Period Register\r
+#define AT91C_PWMC_CH3_CDTYR (0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register\r
+#define AT91C_PWMC_CH3_CCNTR (0xFFFCC26C) // (PWMC_CH3) Channel Counter Register\r
+#define AT91C_PWMC_CH3_CMR (0xFFFCC260) // (PWMC_CH3) Channel Mode Register\r
+// ========== Register definition for PWMC_CH2 peripheral ========== \r
+#define AT91C_PWMC_CH2_Reserved (0xFFFCC254) // (PWMC_CH2) Reserved\r
+#define AT91C_PWMC_CH2_CMR (0xFFFCC240) // (PWMC_CH2) Channel Mode Register\r
+#define AT91C_PWMC_CH2_CCNTR (0xFFFCC24C) // (PWMC_CH2) Channel Counter Register\r
+#define AT91C_PWMC_CH2_CPRDR (0xFFFCC248) // (PWMC_CH2) Channel Period Register\r
+#define AT91C_PWMC_CH2_CUPDR (0xFFFCC250) // (PWMC_CH2) Channel Update Register\r
+#define AT91C_PWMC_CH2_CDTYR (0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register\r
+// ========== Register definition for PWMC_CH1 peripheral ========== \r
+#define AT91C_PWMC_CH1_Reserved (0xFFFCC234) // (PWMC_CH1) Reserved\r
+#define AT91C_PWMC_CH1_CUPDR (0xFFFCC230) // (PWMC_CH1) Channel Update Register\r
+#define AT91C_PWMC_CH1_CPRDR (0xFFFCC228) // (PWMC_CH1) Channel Period Register\r
+#define AT91C_PWMC_CH1_CCNTR (0xFFFCC22C) // (PWMC_CH1) Channel Counter Register\r
+#define AT91C_PWMC_CH1_CDTYR (0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register\r
+#define AT91C_PWMC_CH1_CMR (0xFFFCC220) // (PWMC_CH1) Channel Mode Register\r
+// ========== Register definition for PWMC_CH0 peripheral ========== \r
+#define AT91C_PWMC_CH0_Reserved (0xFFFCC214) // (PWMC_CH0) Reserved\r
+#define AT91C_PWMC_CH0_CPRDR (0xFFFCC208) // (PWMC_CH0) Channel Period Register\r
+#define AT91C_PWMC_CH0_CDTYR (0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register\r
+#define AT91C_PWMC_CH0_CMR (0xFFFCC200) // (PWMC_CH0) Channel Mode Register\r
+#define AT91C_PWMC_CH0_CUPDR (0xFFFCC210) // (PWMC_CH0) Channel Update Register\r
+#define AT91C_PWMC_CH0_CCNTR (0xFFFCC20C) // (PWMC_CH0) Channel Counter Register\r
+// ========== Register definition for PWMC peripheral ========== \r
+#define AT91C_PWMC_IDR (0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register\r
+#define AT91C_PWMC_DIS (0xFFFCC008) // (PWMC) PWMC Disable Register\r
+#define AT91C_PWMC_IER (0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register\r
+#define AT91C_PWMC_VR (0xFFFCC0FC) // (PWMC) PWMC Version Register\r
+#define AT91C_PWMC_ISR (0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register\r
+#define AT91C_PWMC_SR (0xFFFCC00C) // (PWMC) PWMC Status Register\r
+#define AT91C_PWMC_IMR (0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register\r
+#define AT91C_PWMC_MR (0xFFFCC000) // (PWMC) PWMC Mode Register\r
+#define AT91C_PWMC_ENA (0xFFFCC004) // (PWMC) PWMC Enable Register\r
+// ========== Register definition for UDP peripheral ========== \r
+#define AT91C_UDP_IMR (0xFFFB0018) // (UDP) Interrupt Mask Register\r
+#define AT91C_UDP_FADDR (0xFFFB0008) // (UDP) Function Address Register\r
+#define AT91C_UDP_NUM (0xFFFB0000) // (UDP) Frame Number Register\r
+#define AT91C_UDP_FDR (0xFFFB0050) // (UDP) Endpoint FIFO Data Register\r
+#define AT91C_UDP_ISR (0xFFFB001C) // (UDP) Interrupt Status Register\r
+#define AT91C_UDP_CSR (0xFFFB0030) // (UDP) Endpoint Control and Status Register\r
+#define AT91C_UDP_IDR (0xFFFB0014) // (UDP) Interrupt Disable Register\r
+#define AT91C_UDP_ICR (0xFFFB0020) // (UDP) Interrupt Clear Register\r
+#define AT91C_UDP_RSTEP (0xFFFB0028) // (UDP) Reset Endpoint Register\r
+#define AT91C_UDP_TXVC (0xFFFB0074) // (UDP) Transceiver Control Register\r
+#define AT91C_UDP_GLBSTATE (0xFFFB0004) // (UDP) Global State Register\r
+#define AT91C_UDP_IER (0xFFFB0010) // (UDP) Interrupt Enable Register\r
+// ========== Register definition for TC0 peripheral ========== \r
+#define AT91C_TC0_SR (0xFFFA0020) // (TC0) Status Register\r
+#define AT91C_TC0_RC (0xFFFA001C) // (TC0) Register C\r
+#define AT91C_TC0_RB (0xFFFA0018) // (TC0) Register B\r
+#define AT91C_TC0_CCR (0xFFFA0000) // (TC0) Channel Control Register\r
+#define AT91C_TC0_CMR (0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define AT91C_TC0_IER (0xFFFA0024) // (TC0) Interrupt Enable Register\r
+#define AT91C_TC0_RA (0xFFFA0014) // (TC0) Register A\r
+#define AT91C_TC0_IDR (0xFFFA0028) // (TC0) Interrupt Disable Register\r
+#define AT91C_TC0_CV (0xFFFA0010) // (TC0) Counter Value\r
+#define AT91C_TC0_IMR (0xFFFA002C) // (TC0) Interrupt Mask Register\r
+// ========== Register definition for TC1 peripheral ========== \r
+#define AT91C_TC1_RB (0xFFFA0058) // (TC1) Register B\r
+#define AT91C_TC1_CCR (0xFFFA0040) // (TC1) Channel Control Register\r
+#define AT91C_TC1_IER (0xFFFA0064) // (TC1) Interrupt Enable Register\r
+#define AT91C_TC1_IDR (0xFFFA0068) // (TC1) Interrupt Disable Register\r
+#define AT91C_TC1_SR (0xFFFA0060) // (TC1) Status Register\r
+#define AT91C_TC1_CMR (0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define AT91C_TC1_RA (0xFFFA0054) // (TC1) Register A\r
+#define AT91C_TC1_RC (0xFFFA005C) // (TC1) Register C\r
+#define AT91C_TC1_IMR (0xFFFA006C) // (TC1) Interrupt Mask Register\r
+#define AT91C_TC1_CV (0xFFFA0050) // (TC1) Counter Value\r
+// ========== Register definition for TC2 peripheral ========== \r
+#define AT91C_TC2_CMR (0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define AT91C_TC2_CCR (0xFFFA0080) // (TC2) Channel Control Register\r
+#define AT91C_TC2_CV (0xFFFA0090) // (TC2) Counter Value\r
+#define AT91C_TC2_RA (0xFFFA0094) // (TC2) Register A\r
+#define AT91C_TC2_RB (0xFFFA0098) // (TC2) Register B\r
+#define AT91C_TC2_IDR (0xFFFA00A8) // (TC2) Interrupt Disable Register\r
+#define AT91C_TC2_IMR (0xFFFA00AC) // (TC2) Interrupt Mask Register\r
+#define AT91C_TC2_RC (0xFFFA009C) // (TC2) Register C\r
+#define AT91C_TC2_IER (0xFFFA00A4) // (TC2) Interrupt Enable Register\r
+#define AT91C_TC2_SR (0xFFFA00A0) // (TC2) Status Register\r
+// ========== Register definition for TCB peripheral ========== \r
+#define AT91C_TCB_BMR (0xFFFA00C4) // (TCB) TC Block Mode Register\r
+#define AT91C_TCB_BCR (0xFFFA00C0) // (TCB) TC Block Control Register\r
+// ========== Register definition for CAN_MB0 peripheral ========== \r
+#define AT91C_CAN_MB0_MDL (0xFFFD0214) // (CAN_MB0) MailBox Data Low Register\r
+#define AT91C_CAN_MB0_MAM (0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register\r
+#define AT91C_CAN_MB0_MCR (0xFFFD021C) // (CAN_MB0) MailBox Control Register\r
+#define AT91C_CAN_MB0_MID (0xFFFD0208) // (CAN_MB0) MailBox ID Register\r
+#define AT91C_CAN_MB0_MSR (0xFFFD0210) // (CAN_MB0) MailBox Status Register\r
+#define AT91C_CAN_MB0_MFID (0xFFFD020C) // (CAN_MB0) MailBox Family ID Register\r
+#define AT91C_CAN_MB0_MDH (0xFFFD0218) // (CAN_MB0) MailBox Data High Register\r
+#define AT91C_CAN_MB0_MMR (0xFFFD0200) // (CAN_MB0) MailBox Mode Register\r
+// ========== Register definition for CAN_MB1 peripheral ========== \r
+#define AT91C_CAN_MB1_MDL (0xFFFD0234) // (CAN_MB1) MailBox Data Low Register\r
+#define AT91C_CAN_MB1_MID (0xFFFD0228) // (CAN_MB1) MailBox ID Register\r
+#define AT91C_CAN_MB1_MMR (0xFFFD0220) // (CAN_MB1) MailBox Mode Register\r
+#define AT91C_CAN_MB1_MSR (0xFFFD0230) // (CAN_MB1) MailBox Status Register\r
+#define AT91C_CAN_MB1_MAM (0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register\r
+#define AT91C_CAN_MB1_MDH (0xFFFD0238) // (CAN_MB1) MailBox Data High Register\r
+#define AT91C_CAN_MB1_MCR (0xFFFD023C) // (CAN_MB1) MailBox Control Register\r
+#define AT91C_CAN_MB1_MFID (0xFFFD022C) // (CAN_MB1) MailBox Family ID Register\r
+// ========== Register definition for CAN_MB2 peripheral ========== \r
+#define AT91C_CAN_MB2_MCR (0xFFFD025C) // (CAN_MB2) MailBox Control Register\r
+#define AT91C_CAN_MB2_MDH (0xFFFD0258) // (CAN_MB2) MailBox Data High Register\r
+#define AT91C_CAN_MB2_MID (0xFFFD0248) // (CAN_MB2) MailBox ID Register\r
+#define AT91C_CAN_MB2_MDL (0xFFFD0254) // (CAN_MB2) MailBox Data Low Register\r
+#define AT91C_CAN_MB2_MMR (0xFFFD0240) // (CAN_MB2) MailBox Mode Register\r
+#define AT91C_CAN_MB2_MAM (0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register\r
+#define AT91C_CAN_MB2_MFID (0xFFFD024C) // (CAN_MB2) MailBox Family ID Register\r
+#define AT91C_CAN_MB2_MSR (0xFFFD0250) // (CAN_MB2) MailBox Status Register\r
+// ========== Register definition for CAN_MB3 peripheral ========== \r
+#define AT91C_CAN_MB3_MFID (0xFFFD026C) // (CAN_MB3) MailBox Family ID Register\r
+#define AT91C_CAN_MB3_MAM (0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register\r
+#define AT91C_CAN_MB3_MID (0xFFFD0268) // (CAN_MB3) MailBox ID Register\r
+#define AT91C_CAN_MB3_MCR (0xFFFD027C) // (CAN_MB3) MailBox Control Register\r
+#define AT91C_CAN_MB3_MMR (0xFFFD0260) // (CAN_MB3) MailBox Mode Register\r
+#define AT91C_CAN_MB3_MSR (0xFFFD0270) // (CAN_MB3) MailBox Status Register\r
+#define AT91C_CAN_MB3_MDL (0xFFFD0274) // (CAN_MB3) MailBox Data Low Register\r
+#define AT91C_CAN_MB3_MDH (0xFFFD0278) // (CAN_MB3) MailBox Data High Register\r
+// ========== Register definition for CAN_MB4 peripheral ========== \r
+#define AT91C_CAN_MB4_MID (0xFFFD0288) // (CAN_MB4) MailBox ID Register\r
+#define AT91C_CAN_MB4_MMR (0xFFFD0280) // (CAN_MB4) MailBox Mode Register\r
+#define AT91C_CAN_MB4_MDH (0xFFFD0298) // (CAN_MB4) MailBox Data High Register\r
+#define AT91C_CAN_MB4_MFID (0xFFFD028C) // (CAN_MB4) MailBox Family ID Register\r
+#define AT91C_CAN_MB4_MSR (0xFFFD0290) // (CAN_MB4) MailBox Status Register\r
+#define AT91C_CAN_MB4_MCR (0xFFFD029C) // (CAN_MB4) MailBox Control Register\r
+#define AT91C_CAN_MB4_MDL (0xFFFD0294) // (CAN_MB4) MailBox Data Low Register\r
+#define AT91C_CAN_MB4_MAM (0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register\r
+// ========== Register definition for CAN_MB5 peripheral ========== \r
+#define AT91C_CAN_MB5_MSR (0xFFFD02B0) // (CAN_MB5) MailBox Status Register\r
+#define AT91C_CAN_MB5_MCR (0xFFFD02BC) // (CAN_MB5) MailBox Control Register\r
+#define AT91C_CAN_MB5_MFID (0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register\r
+#define AT91C_CAN_MB5_MDH (0xFFFD02B8) // (CAN_MB5) MailBox Data High Register\r
+#define AT91C_CAN_MB5_MID (0xFFFD02A8) // (CAN_MB5) MailBox ID Register\r
+#define AT91C_CAN_MB5_MMR (0xFFFD02A0) // (CAN_MB5) MailBox Mode Register\r
+#define AT91C_CAN_MB5_MDL (0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register\r
+#define AT91C_CAN_MB5_MAM (0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register\r
+// ========== Register definition for CAN_MB6 peripheral ========== \r
+#define AT91C_CAN_MB6_MFID (0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register\r
+#define AT91C_CAN_MB6_MID (0xFFFD02C8) // (CAN_MB6) MailBox ID Register\r
+#define AT91C_CAN_MB6_MAM (0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register\r
+#define AT91C_CAN_MB6_MSR (0xFFFD02D0) // (CAN_MB6) MailBox Status Register\r
+#define AT91C_CAN_MB6_MDL (0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register\r
+#define AT91C_CAN_MB6_MCR (0xFFFD02DC) // (CAN_MB6) MailBox Control Register\r
+#define AT91C_CAN_MB6_MDH (0xFFFD02D8) // (CAN_MB6) MailBox Data High Register\r
+#define AT91C_CAN_MB6_MMR (0xFFFD02C0) // (CAN_MB6) MailBox Mode Register\r
+// ========== Register definition for CAN_MB7 peripheral ========== \r
+#define AT91C_CAN_MB7_MCR (0xFFFD02FC) // (CAN_MB7) MailBox Control Register\r
+#define AT91C_CAN_MB7_MDH (0xFFFD02F8) // (CAN_MB7) MailBox Data High Register\r
+#define AT91C_CAN_MB7_MFID (0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register\r
+#define AT91C_CAN_MB7_MDL (0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register\r
+#define AT91C_CAN_MB7_MID (0xFFFD02E8) // (CAN_MB7) MailBox ID Register\r
+#define AT91C_CAN_MB7_MMR (0xFFFD02E0) // (CAN_MB7) MailBox Mode Register\r
+#define AT91C_CAN_MB7_MAM (0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register\r
+#define AT91C_CAN_MB7_MSR (0xFFFD02F0) // (CAN_MB7) MailBox Status Register\r
+// ========== Register definition for CAN peripheral ========== \r
+#define AT91C_CAN_TCR (0xFFFD0024) // (CAN) Transfer Command Register\r
+#define AT91C_CAN_IMR (0xFFFD000C) // (CAN) Interrupt Mask Register\r
+#define AT91C_CAN_IER (0xFFFD0004) // (CAN) Interrupt Enable Register\r
+#define AT91C_CAN_ECR (0xFFFD0020) // (CAN) Error Counter Register\r
+#define AT91C_CAN_TIMESTP (0xFFFD001C) // (CAN) Time Stamp Register\r
+#define AT91C_CAN_MR (0xFFFD0000) // (CAN) Mode Register\r
+#define AT91C_CAN_IDR (0xFFFD0008) // (CAN) Interrupt Disable Register\r
+#define AT91C_CAN_ACR (0xFFFD0028) // (CAN) Abort Command Register\r
+#define AT91C_CAN_TIM (0xFFFD0018) // (CAN) Timer Register\r
+#define AT91C_CAN_SR (0xFFFD0010) // (CAN) Status Register\r
+#define AT91C_CAN_BR (0xFFFD0014) // (CAN) Baudrate Register\r
+#define AT91C_CAN_VR (0xFFFD00FC) // (CAN) Version Register\r
+// ========== Register definition for EMAC peripheral ========== \r
+#define AT91C_EMAC_ISR (0xFFFDC024) // (EMAC) Interrupt Status Register\r
+#define AT91C_EMAC_SA4H (0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes\r
+#define AT91C_EMAC_SA1L (0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes\r
+#define AT91C_EMAC_ELE (0xFFFDC078) // (EMAC) Excessive Length Errors Register\r
+#define AT91C_EMAC_LCOL (0xFFFDC05C) // (EMAC) Late Collision Register\r
+#define AT91C_EMAC_RLE (0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register\r
+#define AT91C_EMAC_WOL (0xFFFDC0C4) // (EMAC) Wake On LAN Register\r
+#define AT91C_EMAC_DTF (0xFFFDC058) // (EMAC) Deferred Transmission Frame Register\r
+#define AT91C_EMAC_TUND (0xFFFDC064) // (EMAC) Transmit Underrun Error Register\r
+#define AT91C_EMAC_NCR (0xFFFDC000) // (EMAC) Network Control Register\r
+#define AT91C_EMAC_SA4L (0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes\r
+#define AT91C_EMAC_RSR (0xFFFDC020) // (EMAC) Receive Status Register\r
+#define AT91C_EMAC_SA3L (0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes\r
+#define AT91C_EMAC_TSR (0xFFFDC014) // (EMAC) Transmit Status Register\r
+#define AT91C_EMAC_IDR (0xFFFDC02C) // (EMAC) Interrupt Disable Register\r
+#define AT91C_EMAC_RSE (0xFFFDC074) // (EMAC) Receive Symbol Errors Register\r
+#define AT91C_EMAC_ECOL (0xFFFDC060) // (EMAC) Excessive Collision Register\r
+#define AT91C_EMAC_TID (0xFFFDC0B8) // (EMAC) Type ID Checking Register\r
+#define AT91C_EMAC_HRB (0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]\r
+#define AT91C_EMAC_TBQP (0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer\r
+#define AT91C_EMAC_USRIO (0xFFFDC0C0) // (EMAC) USER Input/Output Register\r
+#define AT91C_EMAC_PTR (0xFFFDC038) // (EMAC) Pause Time Register\r
+#define AT91C_EMAC_SA2H (0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes\r
+#define AT91C_EMAC_ROV (0xFFFDC070) // (EMAC) Receive Overrun Errors Register\r
+#define AT91C_EMAC_ALE (0xFFFDC054) // (EMAC) Alignment Error Register\r
+#define AT91C_EMAC_RJA (0xFFFDC07C) // (EMAC) Receive Jabbers Register\r
+#define AT91C_EMAC_RBQP (0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer\r
+#define AT91C_EMAC_TPF (0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register\r
+#define AT91C_EMAC_NCFGR (0xFFFDC004) // (EMAC) Network Configuration Register\r
+#define AT91C_EMAC_HRT (0xFFFDC094) // (EMAC) Hash Address Top[63:32]\r
+#define AT91C_EMAC_USF (0xFFFDC080) // (EMAC) Undersize Frames Register\r
+#define AT91C_EMAC_FCSE (0xFFFDC050) // (EMAC) Frame Check Sequence Error Register\r
+#define AT91C_EMAC_TPQ (0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register\r
+#define AT91C_EMAC_MAN (0xFFFDC034) // (EMAC) PHY Maintenance Register\r
+#define AT91C_EMAC_FTO (0xFFFDC040) // (EMAC) Frames Transmitted OK Register\r
+#define AT91C_EMAC_REV (0xFFFDC0FC) // (EMAC) Revision Register\r
+#define AT91C_EMAC_IMR (0xFFFDC030) // (EMAC) Interrupt Mask Register\r
+#define AT91C_EMAC_SCF (0xFFFDC044) // (EMAC) Single Collision Frame Register\r
+#define AT91C_EMAC_PFR (0xFFFDC03C) // (EMAC) Pause Frames received Register\r
+#define AT91C_EMAC_MCF (0xFFFDC048) // (EMAC) Multiple Collision Frame Register\r
+#define AT91C_EMAC_NSR (0xFFFDC008) // (EMAC) Network Status Register\r
+#define AT91C_EMAC_SA2L (0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes\r
+#define AT91C_EMAC_FRO (0xFFFDC04C) // (EMAC) Frames Received OK Register\r
+#define AT91C_EMAC_IER (0xFFFDC028) // (EMAC) Interrupt Enable Register\r
+#define AT91C_EMAC_SA1H (0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes\r
+#define AT91C_EMAC_CSE (0xFFFDC068) // (EMAC) Carrier Sense Error Register\r
+#define AT91C_EMAC_SA3H (0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes\r
+#define AT91C_EMAC_RRE (0xFFFDC06C) // (EMAC) Receive Ressource Error Register\r
+#define AT91C_EMAC_STE (0xFFFDC084) // (EMAC) SQE Test Error Register\r
+// ========== Register definition for PDC_ADC peripheral ========== \r
+#define AT91C_ADC_PTSR (0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register\r
+#define AT91C_ADC_PTCR (0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register\r
+#define AT91C_ADC_TNPR (0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register\r
+#define AT91C_ADC_TNCR (0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register\r
+#define AT91C_ADC_RNPR (0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register\r
+#define AT91C_ADC_RNCR (0xFFFD8114) // (PDC_ADC) Receive Next Counter Register\r
+#define AT91C_ADC_RPR (0xFFFD8100) // (PDC_ADC) Receive Pointer Register\r
+#define AT91C_ADC_TCR (0xFFFD810C) // (PDC_ADC) Transmit Counter Register\r
+#define AT91C_ADC_TPR (0xFFFD8108) // (PDC_ADC) Transmit Pointer Register\r
+#define AT91C_ADC_RCR (0xFFFD8104) // (PDC_ADC) Receive Counter Register\r
+// ========== Register definition for ADC peripheral ========== \r
+#define AT91C_ADC_CDR2 (0xFFFD8038) // (ADC) ADC Channel Data Register 2\r
+#define AT91C_ADC_CDR3 (0xFFFD803C) // (ADC) ADC Channel Data Register 3\r
+#define AT91C_ADC_CDR0 (0xFFFD8030) // (ADC) ADC Channel Data Register 0\r
+#define AT91C_ADC_CDR5 (0xFFFD8044) // (ADC) ADC Channel Data Register 5\r
+#define AT91C_ADC_CHDR (0xFFFD8014) // (ADC) ADC Channel Disable Register\r
+#define AT91C_ADC_SR (0xFFFD801C) // (ADC) ADC Status Register\r
+#define AT91C_ADC_CDR4 (0xFFFD8040) // (ADC) ADC Channel Data Register 4\r
+#define AT91C_ADC_CDR1 (0xFFFD8034) // (ADC) ADC Channel Data Register 1\r
+#define AT91C_ADC_LCDR (0xFFFD8020) // (ADC) ADC Last Converted Data Register\r
+#define AT91C_ADC_IDR (0xFFFD8028) // (ADC) ADC Interrupt Disable Register\r
+#define AT91C_ADC_CR (0xFFFD8000) // (ADC) ADC Control Register\r
+#define AT91C_ADC_CDR7 (0xFFFD804C) // (ADC) ADC Channel Data Register 7\r
+#define AT91C_ADC_CDR6 (0xFFFD8048) // (ADC) ADC Channel Data Register 6\r
+#define AT91C_ADC_IER (0xFFFD8024) // (ADC) ADC Interrupt Enable Register\r
+#define AT91C_ADC_CHER (0xFFFD8010) // (ADC) ADC Channel Enable Register\r
+#define AT91C_ADC_CHSR (0xFFFD8018) // (ADC) ADC Channel Status Register\r
+#define AT91C_ADC_MR (0xFFFD8004) // (ADC) ADC Mode Register\r
+#define AT91C_ADC_IMR (0xFFFD802C) // (ADC) ADC Interrupt Mask Register\r
+// ========== Register definition for PDC_AES peripheral ========== \r
+#define AT91C_AES_TPR (0xFFFA4108) // (PDC_AES) Transmit Pointer Register\r
+#define AT91C_AES_PTCR (0xFFFA4120) // (PDC_AES) PDC Transfer Control Register\r
+#define AT91C_AES_RNPR (0xFFFA4110) // (PDC_AES) Receive Next Pointer Register\r
+#define AT91C_AES_TNCR (0xFFFA411C) // (PDC_AES) Transmit Next Counter Register\r
+#define AT91C_AES_TCR (0xFFFA410C) // (PDC_AES) Transmit Counter Register\r
+#define AT91C_AES_RCR (0xFFFA4104) // (PDC_AES) Receive Counter Register\r
+#define AT91C_AES_RNCR (0xFFFA4114) // (PDC_AES) Receive Next Counter Register\r
+#define AT91C_AES_TNPR (0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register\r
+#define AT91C_AES_RPR (0xFFFA4100) // (PDC_AES) Receive Pointer Register\r
+#define AT91C_AES_PTSR (0xFFFA4124) // (PDC_AES) PDC Transfer Status Register\r
+// ========== Register definition for AES peripheral ========== \r
+#define AT91C_AES_IVxR (0xFFFA4060) // (AES) Initialization Vector x Register\r
+#define AT91C_AES_MR (0xFFFA4004) // (AES) Mode Register\r
+#define AT91C_AES_VR (0xFFFA40FC) // (AES) AES Version Register\r
+#define AT91C_AES_ODATAxR (0xFFFA4050) // (AES) Output Data x Register\r
+#define AT91C_AES_IDATAxR (0xFFFA4040) // (AES) Input Data x Register\r
+#define AT91C_AES_CR (0xFFFA4000) // (AES) Control Register\r
+#define AT91C_AES_IDR (0xFFFA4014) // (AES) Interrupt Disable Register\r
+#define AT91C_AES_IMR (0xFFFA4018) // (AES) Interrupt Mask Register\r
+#define AT91C_AES_IER (0xFFFA4010) // (AES) Interrupt Enable Register\r
+#define AT91C_AES_KEYWxR (0xFFFA4020) // (AES) Key Word x Register\r
+#define AT91C_AES_ISR (0xFFFA401C) // (AES) Interrupt Status Register\r
+// ========== Register definition for PDC_TDES peripheral ========== \r
+#define AT91C_TDES_RNCR (0xFFFA8114) // (PDC_TDES) Receive Next Counter Register\r
+#define AT91C_TDES_TCR (0xFFFA810C) // (PDC_TDES) Transmit Counter Register\r
+#define AT91C_TDES_RCR (0xFFFA8104) // (PDC_TDES) Receive Counter Register\r
+#define AT91C_TDES_TNPR (0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register\r
+#define AT91C_TDES_RNPR (0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register\r
+#define AT91C_TDES_RPR (0xFFFA8100) // (PDC_TDES) Receive Pointer Register\r
+#define AT91C_TDES_TNCR (0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register\r
+#define AT91C_TDES_TPR (0xFFFA8108) // (PDC_TDES) Transmit Pointer Register\r
+#define AT91C_TDES_PTSR (0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register\r
+#define AT91C_TDES_PTCR (0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register\r
+// ========== Register definition for TDES peripheral ========== \r
+#define AT91C_TDES_KEY2WxR (0xFFFA8028) // (TDES) Key 2 Word x Register\r
+#define AT91C_TDES_KEY3WxR (0xFFFA8030) // (TDES) Key 3 Word x Register\r
+#define AT91C_TDES_IDR (0xFFFA8014) // (TDES) Interrupt Disable Register\r
+#define AT91C_TDES_VR (0xFFFA80FC) // (TDES) TDES Version Register\r
+#define AT91C_TDES_IVxR (0xFFFA8060) // (TDES) Initialization Vector x Register\r
+#define AT91C_TDES_ODATAxR (0xFFFA8050) // (TDES) Output Data x Register\r
+#define AT91C_TDES_IMR (0xFFFA8018) // (TDES) Interrupt Mask Register\r
+#define AT91C_TDES_MR (0xFFFA8004) // (TDES) Mode Register\r
+#define AT91C_TDES_CR (0xFFFA8000) // (TDES) Control Register\r
+#define AT91C_TDES_IER (0xFFFA8010) // (TDES) Interrupt Enable Register\r
+#define AT91C_TDES_ISR (0xFFFA801C) // (TDES) Interrupt Status Register\r
+#define AT91C_TDES_IDATAxR (0xFFFA8040) // (TDES) Input Data x Register\r
+#define AT91C_TDES_KEY1WxR (0xFFFA8020) // (TDES) Key 1 Word x Register\r
+\r
+// *****************************************************************************\r
+// PIO DEFINITIONS FOR AT91SAM7X256\r
+// *****************************************************************************\r
+#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0\r
+#define AT91C_PA0_RXD0 (AT91C_PIO_PA0) // USART 0 Receive Data\r
+#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1\r
+#define AT91C_PA1_TXD0 (AT91C_PIO_PA1) // USART 0 Transmit Data\r
+#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10\r
+#define AT91C_PA10_TWD (AT91C_PIO_PA10) // TWI Two-wire Serial Data\r
+#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11\r
+#define AT91C_PA11_TWCK (AT91C_PIO_PA11) // TWI Two-wire Serial Clock\r
+#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12\r
+#define AT91C_PA12_NPCS00 (AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0\r
+#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13\r
+#define AT91C_PA13_NPCS01 (AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1\r
+#define AT91C_PA13_PCK1 (AT91C_PIO_PA13) // PMC Programmable Clock Output 1\r
+#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14\r
+#define AT91C_PA14_NPCS02 (AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2\r
+#define AT91C_PA14_IRQ1 (AT91C_PIO_PA14) // External Interrupt 1\r
+#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15\r
+#define AT91C_PA15_NPCS03 (AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3\r
+#define AT91C_PA15_TCLK2 (AT91C_PIO_PA15) // Timer Counter 2 external clock input\r
+#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16\r
+#define AT91C_PA16_MISO0 (AT91C_PIO_PA16) // SPI 0 Master In Slave\r
+#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17\r
+#define AT91C_PA17_MOSI0 (AT91C_PIO_PA17) // SPI 0 Master Out Slave\r
+#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18\r
+#define AT91C_PA18_SPCK0 (AT91C_PIO_PA18) // SPI 0 Serial Clock\r
+#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19\r
+#define AT91C_PA19_CANRX (AT91C_PIO_PA19) // CAN Receive\r
+#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2\r
+#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock\r
+#define AT91C_PA2_NPCS11 (AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1\r
+#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20\r
+#define AT91C_PA20_CANTX (AT91C_PIO_PA20) // CAN Transmit\r
+#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21\r
+#define AT91C_PA21_TF (AT91C_PIO_PA21) // SSC Transmit Frame Sync\r
+#define AT91C_PA21_NPCS10 (AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0\r
+#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22\r
+#define AT91C_PA22_TK (AT91C_PIO_PA22) // SSC Transmit Clock\r
+#define AT91C_PA22_SPCK1 (AT91C_PIO_PA22) // SPI 1 Serial Clock\r
+#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23\r
+#define AT91C_PA23_TD (AT91C_PIO_PA23) // SSC Transmit data\r
+#define AT91C_PA23_MOSI1 (AT91C_PIO_PA23) // SPI 1 Master Out Slave\r
+#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24\r
+#define AT91C_PA24_RD (AT91C_PIO_PA24) // SSC Receive Data\r
+#define AT91C_PA24_MISO1 (AT91C_PIO_PA24) // SPI 1 Master In Slave\r
+#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25\r
+#define AT91C_PA25_RK (AT91C_PIO_PA25) // SSC Receive Clock\r
+#define AT91C_PA25_NPCS11 (AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1\r
+#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26\r
+#define AT91C_PA26_RF (AT91C_PIO_PA26) // SSC Receive Frame Sync\r
+#define AT91C_PA26_NPCS12 (AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2\r
+#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27\r
+#define AT91C_PA27_DRXD (AT91C_PIO_PA27) // DBGU Debug Receive Data\r
+#define AT91C_PA27_PCK3 (AT91C_PIO_PA27) // PMC Programmable Clock Output 3\r
+#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28\r
+#define AT91C_PA28_DTXD (AT91C_PIO_PA28) // DBGU Debug Transmit Data\r
+#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29\r
+#define AT91C_PA29_FIQ (AT91C_PIO_PA29) // AIC Fast Interrupt Input\r
+#define AT91C_PA29_NPCS13 (AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3\r
+#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3\r
+#define AT91C_PA3_RTS0 (AT91C_PIO_PA3) // USART 0 Ready To Send\r
+#define AT91C_PA3_NPCS12 (AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2\r
+#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30\r
+#define AT91C_PA30_IRQ0 (AT91C_PIO_PA30) // External Interrupt 0\r
+#define AT91C_PA30_PCK2 (AT91C_PIO_PA30) // PMC Programmable Clock Output 2\r
+#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4\r
+#define AT91C_PA4_CTS0 (AT91C_PIO_PA4) // USART 0 Clear To Send\r
+#define AT91C_PA4_NPCS13 (AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3\r
+#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5\r
+#define AT91C_PA5_RXD1 (AT91C_PIO_PA5) // USART 1 Receive Data\r
+#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6\r
+#define AT91C_PA6_TXD1 (AT91C_PIO_PA6) // USART 1 Transmit Data\r
+#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7\r
+#define AT91C_PA7_SCK1 (AT91C_PIO_PA7) // USART 1 Serial Clock\r
+#define AT91C_PA7_NPCS01 (AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1\r
+#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8\r
+#define AT91C_PA8_RTS1 (AT91C_PIO_PA8) // USART 1 Ready To Send\r
+#define AT91C_PA8_NPCS02 (AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2\r
+#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9\r
+#define AT91C_PA9_CTS1 (AT91C_PIO_PA9) // USART 1 Clear To Send\r
+#define AT91C_PA9_NPCS03 (AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3\r
+#define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0\r
+#define AT91C_PB0_ETXCK_EREFCK (AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock\r
+#define AT91C_PB0_PCK0 (AT91C_PIO_PB0) // PMC Programmable Clock Output 0\r
+#define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1\r
+#define AT91C_PB1_ETXEN (AT91C_PIO_PB1) // Ethernet MAC Transmit Enable\r
+#define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10\r
+#define AT91C_PB10_ETX2 (AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2\r
+#define AT91C_PB10_NPCS11 (AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1\r
+#define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11\r
+#define AT91C_PB11_ETX3 (AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3\r
+#define AT91C_PB11_NPCS12 (AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2\r
+#define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12\r
+#define AT91C_PB12_ETXER (AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error\r
+#define AT91C_PB12_TCLK0 (AT91C_PIO_PB12) // Timer Counter 0 external clock input\r
+#define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13\r
+#define AT91C_PB13_ERX2 (AT91C_PIO_PB13) // Ethernet MAC Receive Data 2\r
+#define AT91C_PB13_NPCS01 (AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1\r
+#define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14\r
+#define AT91C_PB14_ERX3 (AT91C_PIO_PB14) // Ethernet MAC Receive Data 3\r
+#define AT91C_PB14_NPCS02 (AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2\r
+#define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15\r
+#define AT91C_PB15_ERXDV (AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid\r
+#define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16\r
+#define AT91C_PB16_ECOL (AT91C_PIO_PB16) // Ethernet MAC Collision Detected\r
+#define AT91C_PB16_NPCS13 (AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3\r
+#define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17\r
+#define AT91C_PB17_ERXCK (AT91C_PIO_PB17) // Ethernet MAC Receive Clock\r
+#define AT91C_PB17_NPCS03 (AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3\r
+#define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18\r
+#define AT91C_PB18_EF100 (AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec\r
+#define AT91C_PB18_ADTRG (AT91C_PIO_PB18) // ADC External Trigger\r
+#define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19\r
+#define AT91C_PB19_PWM0 (AT91C_PIO_PB19) // PWM Channel 0\r
+#define AT91C_PB19_TCLK1 (AT91C_PIO_PB19) // Timer Counter 1 external clock input\r
+#define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2\r
+#define AT91C_PB2_ETX0 (AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0\r
+#define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20\r
+#define AT91C_PB20_PWM1 (AT91C_PIO_PB20) // PWM Channel 1\r
+#define AT91C_PB20_PCK0 (AT91C_PIO_PB20) // PMC Programmable Clock Output 0\r
+#define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21\r
+#define AT91C_PB21_PWM2 (AT91C_PIO_PB21) // PWM Channel 2\r
+#define AT91C_PB21_PCK1 (AT91C_PIO_PB21) // PMC Programmable Clock Output 1\r
+#define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22\r
+#define AT91C_PB22_PWM3 (AT91C_PIO_PB22) // PWM Channel 3\r
+#define AT91C_PB22_PCK2 (AT91C_PIO_PB22) // PMC Programmable Clock Output 2\r
+#define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23\r
+#define AT91C_PB23_TIOA0 (AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A\r
+#define AT91C_PB23_DCD1 (AT91C_PIO_PB23) // USART 1 Data Carrier Detect\r
+#define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24\r
+#define AT91C_PB24_TIOB0 (AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B\r
+#define AT91C_PB24_DSR1 (AT91C_PIO_PB24) // USART 1 Data Set ready\r
+#define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25\r
+#define AT91C_PB25_TIOA1 (AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A\r
+#define AT91C_PB25_DTR1 (AT91C_PIO_PB25) // USART 1 Data Terminal ready\r
+#define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26\r
+#define AT91C_PB26_TIOB1 (AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B\r
+#define AT91C_PB26_RI1 (AT91C_PIO_PB26) // USART 1 Ring Indicator\r
+#define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27\r
+#define AT91C_PB27_TIOA2 (AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A\r
+#define AT91C_PB27_PWM0 (AT91C_PIO_PB27) // PWM Channel 0\r
+#define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28\r
+#define AT91C_PB28_TIOB2 (AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B\r
+#define AT91C_PB28_PWM1 (AT91C_PIO_PB28) // PWM Channel 1\r
+#define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29\r
+#define AT91C_PB29_PCK1 (AT91C_PIO_PB29) // PMC Programmable Clock Output 1\r
+#define AT91C_PB29_PWM2 (AT91C_PIO_PB29) // PWM Channel 2\r
+#define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3\r
+#define AT91C_PB3_ETX1 (AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1\r
+#define AT91C_PIO_PB30 (1 << 30) // Pin Controlled by PB30\r
+#define AT91C_PB30_PCK2 (AT91C_PIO_PB30) // PMC Programmable Clock Output 2\r
+#define AT91C_PB30_PWM3 (AT91C_PIO_PB30) // PWM Channel 3\r
+#define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4\r
+#define AT91C_PB4_ECRS_ECRSDV (AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid\r
+#define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5\r
+#define AT91C_PB5_ERX0 (AT91C_PIO_PB5) // Ethernet MAC Receive Data 0\r
+#define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6\r
+#define AT91C_PB6_ERX1 (AT91C_PIO_PB6) // Ethernet MAC Receive Data 1\r
+#define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7\r
+#define AT91C_PB7_ERXER (AT91C_PIO_PB7) // Ethernet MAC Receive Error\r
+#define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8\r
+#define AT91C_PB8_EMDC (AT91C_PIO_PB8) // Ethernet MAC Management Data Clock\r
+#define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9\r
+#define AT91C_PB9_EMDIO (AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output\r
+\r
+// *****************************************************************************\r
+// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256\r
+// *****************************************************************************\r
+#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ)\r
+#define AT91C_ID_SYS ( 1) // System Peripheral\r
+#define AT91C_ID_PIOA ( 2) // Parallel IO Controller A\r
+#define AT91C_ID_PIOB ( 3) // Parallel IO Controller B\r
+#define AT91C_ID_SPI0 ( 4) // Serial Peripheral Interface 0\r
+#define AT91C_ID_SPI1 ( 5) // Serial Peripheral Interface 1\r
+#define AT91C_ID_US0 ( 6) // USART 0\r
+#define AT91C_ID_US1 ( 7) // USART 1\r
+#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller\r
+#define AT91C_ID_TWI ( 9) // Two-Wire Interface\r
+#define AT91C_ID_PWMC (10) // PWM Controller\r
+#define AT91C_ID_UDP (11) // USB Device Port\r
+#define AT91C_ID_TC0 (12) // Timer Counter 0\r
+#define AT91C_ID_TC1 (13) // Timer Counter 1\r
+#define AT91C_ID_TC2 (14) // Timer Counter 2\r
+#define AT91C_ID_CAN (15) // Control Area Network Controller\r
+#define AT91C_ID_EMAC (16) // Ethernet MAC\r
+#define AT91C_ID_ADC (17) // Analog-to-Digital Converter\r
+#define AT91C_ID_AES (18) // Advanced Encryption Standard 128-bit\r
+#define AT91C_ID_TDES (19) // Triple Data Encryption Standard\r
+#define AT91C_ID_20_Reserved (20) // Reserved\r
+#define AT91C_ID_21_Reserved (21) // Reserved\r
+#define AT91C_ID_22_Reserved (22) // Reserved\r
+#define AT91C_ID_23_Reserved (23) // Reserved\r
+#define AT91C_ID_24_Reserved (24) // Reserved\r
+#define AT91C_ID_25_Reserved (25) // Reserved\r
+#define AT91C_ID_26_Reserved (26) // Reserved\r
+#define AT91C_ID_27_Reserved (27) // Reserved\r
+#define AT91C_ID_28_Reserved (28) // Reserved\r
+#define AT91C_ID_29_Reserved (29) // Reserved\r
+#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0)\r
+#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1)\r
+\r
+// *****************************************************************************\r
+// BASE ADDRESS DEFINITIONS FOR AT91SAM7X256\r
+// *****************************************************************************\r
+#define AT91C_BASE_SYS (0xFFFFF000) // (SYS) Base Address\r
+#define AT91C_BASE_AIC (0xFFFFF000) // (AIC) Base Address\r
+#define AT91C_BASE_PDC_DBGU (0xFFFFF300) // (PDC_DBGU) Base Address\r
+#define AT91C_BASE_DBGU (0xFFFFF200) // (DBGU) Base Address\r
+#define AT91C_BASE_PIOA (0xFFFFF400) // (PIOA) Base Address\r
+#define AT91C_BASE_PIOB (0xFFFFF600) // (PIOB) Base Address\r
+#define AT91C_BASE_CKGR (0xFFFFFC20) // (CKGR) Base Address\r
+#define AT91C_BASE_PMC (0xFFFFFC00) // (PMC) Base Address\r
+#define AT91C_BASE_RSTC (0xFFFFFD00) // (RSTC) Base Address\r
+#define AT91C_BASE_RTTC (0xFFFFFD20) // (RTTC) Base Address\r
+#define AT91C_BASE_PITC (0xFFFFFD30) // (PITC) Base Address\r
+#define AT91C_BASE_WDTC (0xFFFFFD40) // (WDTC) Base Address\r
+#define AT91C_BASE_VREG (0xFFFFFD60) // (VREG) Base Address\r
+#define AT91C_BASE_MC (0xFFFFFF00) // (MC) Base Address\r
+#define AT91C_BASE_PDC_SPI1 (0xFFFE4100) // (PDC_SPI1) Base Address\r
+#define AT91C_BASE_SPI1 (0xFFFE4000) // (SPI1) Base Address\r
+#define AT91C_BASE_PDC_SPI0 (0xFFFE0100) // (PDC_SPI0) Base Address\r
+#define AT91C_BASE_SPI0 (0xFFFE0000) // (SPI0) Base Address\r
+#define AT91C_BASE_PDC_US1 (0xFFFC4100) // (PDC_US1) Base Address\r
+#define AT91C_BASE_US1 (0xFFFC4000) // (US1) Base Address\r
+#define AT91C_BASE_PDC_US0 (0xFFFC0100) // (PDC_US0) Base Address\r
+#define AT91C_BASE_US0 (0xFFFC0000) // (US0) Base Address\r
+#define AT91C_BASE_PDC_SSC (0xFFFD4100) // (PDC_SSC) Base Address\r
+#define AT91C_BASE_SSC (0xFFFD4000) // (SSC) Base Address\r
+#define AT91C_BASE_TWI (0xFFFB8000) // (TWI) Base Address\r
+#define AT91C_BASE_PWMC_CH3 (0xFFFCC260) // (PWMC_CH3) Base Address\r
+#define AT91C_BASE_PWMC_CH2 (0xFFFCC240) // (PWMC_CH2) Base Address\r
+#define AT91C_BASE_PWMC_CH1 (0xFFFCC220) // (PWMC_CH1) Base Address\r
+#define AT91C_BASE_PWMC_CH0 (0xFFFCC200) // (PWMC_CH0) Base Address\r
+#define AT91C_BASE_PWMC (0xFFFCC000) // (PWMC) Base Address\r
+#define AT91C_BASE_UDP (0xFFFB0000) // (UDP) Base Address\r
+#define AT91C_BASE_TC0 (0xFFFA0000) // (TC0) Base Address\r
+#define AT91C_BASE_TC1 (0xFFFA0040) // (TC1) Base Address\r
+#define AT91C_BASE_TC2 (0xFFFA0080) // (TC2) Base Address\r
+#define AT91C_BASE_TCB (0xFFFA0000) // (TCB) Base Address\r
+#define AT91C_BASE_CAN_MB0 (0xFFFD0200) // (CAN_MB0) Base Address\r
+#define AT91C_BASE_CAN_MB1 (0xFFFD0220) // (CAN_MB1) Base Address\r
+#define AT91C_BASE_CAN_MB2 (0xFFFD0240) // (CAN_MB2) Base Address\r
+#define AT91C_BASE_CAN_MB3 (0xFFFD0260) // (CAN_MB3) Base Address\r
+#define AT91C_BASE_CAN_MB4 (0xFFFD0280) // (CAN_MB4) Base Address\r
+#define AT91C_BASE_CAN_MB5 (0xFFFD02A0) // (CAN_MB5) Base Address\r
+#define AT91C_BASE_CAN_MB6 (0xFFFD02C0) // (CAN_MB6) Base Address\r
+#define AT91C_BASE_CAN_MB7 (0xFFFD02E0) // (CAN_MB7) Base Address\r
+#define AT91C_BASE_CAN (0xFFFD0000) // (CAN) Base Address\r
+#define AT91C_BASE_EMAC (0xFFFDC000) // (EMAC) Base Address\r
+#define AT91C_BASE_PDC_ADC (0xFFFD8100) // (PDC_ADC) Base Address\r
+#define AT91C_BASE_ADC (0xFFFD8000) // (ADC) Base Address\r
+#define AT91C_BASE_PDC_AES (0xFFFA4100) // (PDC_AES) Base Address\r
+#define AT91C_BASE_AES (0xFFFA4000) // (AES) Base Address\r
+#define AT91C_BASE_PDC_TDES (0xFFFA8100) // (PDC_TDES) Base Address\r
+#define AT91C_BASE_TDES (0xFFFA8000) // (TDES) Base Address\r
+\r
+// *****************************************************************************\r
+// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256\r
+// *****************************************************************************\r
+#define AT91C_ISRAM (0x00200000) // Internal SRAM base address\r
+#define AT91C_ISRAM_SIZE (0x00010000) // Internal SRAM size in byte (64 Kbyte)\r
+#define AT91C_IFLASH (0x00100000) // Internal ROM base address\r
+#define AT91C_IFLASH_SIZE (0x00040000) // Internal ROM size in byte (256 Kbyte)\r
+\r
+\r
--- /dev/null
+ EXTERN pxCurrentTCB\r
+ EXTERN ulCriticalNesting\r
+\r
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+; Context save and restore macro definitions\r
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+\r
+portSAVE_CONTEXT MACRO\r
+\r
+ ; Push R0 as we are going to use the register. \r
+ STMDB SP!, {R0}\r
+\r
+ ; Set R0 to point to the task stack pointer. \r
+ STMDB SP, {SP}^\r
+ NOP\r
+ SUB SP, SP, #4\r
+ LDMIA SP!, {R0}\r
+\r
+ ; Push the return address onto the stack. \r
+ STMDB R0!, {LR}\r
+\r
+ ; Now we have saved LR we can use it instead of R0. \r
+ MOV LR, R0\r
+\r
+ ; Pop R0 so we can save it onto the system mode stack. \r
+ LDMIA SP!, {R0}\r
+\r
+ ; Push all the system mode registers onto the task stack. \r
+ STMDB LR, {R0-LR}^\r
+ NOP\r
+ SUB LR, LR, #60\r
+\r
+ ; Push the SPSR onto the task stack. \r
+ MRS R0, SPSR\r
+ STMDB LR!, {R0}\r
+\r
+ LDR R0, =ulCriticalNesting \r
+ LDR R0, [R0]\r
+ STMDB LR!, {R0}\r
+\r
+ ; Store the new top of stack for the task. \r
+ LDR R1, =pxCurrentTCB\r
+ LDR R0, [R1]\r
+ STR LR, [R0]\r
+\r
+ ENDM\r
+\r
+\r
+portRESTORE_CONTEXT MACRO\r
+\r
+ ; Set the LR to the task stack. \r
+ LDR R1, =pxCurrentTCB\r
+ LDR R0, [R1]\r
+ LDR LR, [R0]\r
+\r
+ ; The critical nesting depth is the first item on the stack. \r
+ ; Load it into the ulCriticalNesting variable. \r
+ LDR R0, =ulCriticalNesting\r
+ LDMFD LR!, {R1}\r
+ STR R1, [R0]\r
+\r
+ ; Get the SPSR from the stack. \r
+ LDMFD LR!, {R0}\r
+ MSR SPSR_cxsf, R0\r
+\r
+ ; Restore all system mode registers for the task. \r
+ LDMFD LR, {R0-R14}^\r
+ NOP\r
+\r
+ ; Restore the return address. \r
+ LDR LR, [LR, #+60]\r
+\r
+ ; And return - correcting the offset in the LR to obtain the \r
+ ; correct address. \r
+ SUBS PC, LR, #4\r
+\r
+ ENDM\r
+\r
--- /dev/null
+//*----------------------------------------------------------------------------\r
+//* ATMEL Microcontroller Software Support - ROUSSET -\r
+//*----------------------------------------------------------------------------\r
+//* The software is delivered "AS IS" without warranty or condition of any\r
+//* kind, either express, implied or statutory. This includes without\r
+//* limitation any warranty or condition with respect to merchantability or\r
+//* fitness for any particular purpose, or against the infringements of\r
+//* intellectual property rights of others.\r
+//*----------------------------------------------------------------------------\r
+//* File Name : lib_AT91SAM7S64.h\r
+//* Object : AT91SAM7S64 inlined functions\r
+//* Generated : AT91 SW Application Group 07/16/2004 (07:43:09)\r
+//*\r
+//* CVS Reference : /lib_MC_SAM.h/1.3/Thu Mar 25 15:19:14 2004//\r
+//* CVS Reference : /lib_pdc_1363d.h/1.2/Wed Feb 19 09:25:22 2003//\r
+//* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003//\r
+//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003//\r
+//* CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 13:23:52 2003//\r
+//* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//\r
+//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//\r
+//* CVS Reference : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004//\r
+//* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 08:12:38 2003//\r
+//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003//\r
+//* CVS Reference : /lib_twi.h/1.2/Fri Jan 31 12:19:38 2003//\r
+//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002//\r
+//* CVS Reference : /lib_udp.h/1.3/Fri Jan 31 12:19:48 2003//\r
+//* CVS Reference : /lib_aic.h/1.3/Fri Jul 12 07:46:12 2002//\r
+//*----------------------------------------------------------------------------\r
+\r
+#ifndef lib_AT91SAM7S64_H\r
+#define lib_AT91SAM7S64_H\r
+\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR MC\r
+ ***************************************************************************** */\r
+\r
+#define AT91C_MC_CORRECT_KEY ((unsigned int) 0x5A << 24) // (MC) Correct Protect Key\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_MC_Remap\r
+//* \brief Make Remap\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_MC_Remap (void) // \r
+{\r
+ AT91PS_MC pMC = (AT91PS_MC) AT91C_BASE_MC;\r
+ \r
+ pMC->MC_RCR = AT91C_MC_RCB;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_MC_EFC_CfgModeReg\r
+//* \brief Configure the EFC Mode Register of the MC controller\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_MC_EFC_CfgModeReg (\r
+ AT91PS_MC pMC, // pointer to a MC controller\r
+ unsigned int mode) // mode register \r
+{\r
+ // Write to the FMR register\r
+ pMC->MC_FMR = mode;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_MC_EFC_GetModeReg\r
+//* \brief Return MC EFC Mode Regsiter\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_MC_EFC_GetModeReg(\r
+ AT91PS_MC pMC) // pointer to a MC controller\r
+{\r
+ return pMC->MC_FMR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_MC_EFC_ComputeFMCN\r
+//* \brief Return MC EFC Mode Regsiter\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_MC_EFC_ComputeFMCN(\r
+ int master_clock) // master clock in Hz\r
+{\r
+ return (master_clock/1000000 +2);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_MC_EFC_PerformCmd\r
+//* \brief Perform EFC Command\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_MC_EFC_PerformCmd (\r
+ AT91PS_MC pMC, // pointer to a MC controller\r
+ unsigned int transfer_cmd)\r
+{\r
+ pMC->MC_FCR = transfer_cmd; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_MC_EFC_GetStatus\r
+//* \brief Return MC EFC Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_MC_EFC_GetStatus(\r
+ AT91PS_MC pMC) // pointer to a MC controller\r
+{\r
+ return pMC->MC_FSR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_MC_EFC_IsInterruptMasked\r
+//* \brief Test if EFC MC Interrupt is Masked \r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_MC_EFC_IsInterruptMasked(\r
+ AT91PS_MC pMC, // \arg pointer to a MC controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_MC_EFC_GetModeReg(pMC) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_MC_EFC_IsInterruptSet\r
+//* \brief Test if EFC MC Interrupt is Set\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_MC_EFC_IsInterruptSet(\r
+ AT91PS_MC pMC, // \arg pointer to a MC controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_MC_EFC_GetStatus(pMC) & flag);\r
+}\r
+\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR PDC\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_SetNextRx\r
+//* \brief Set the next receive transfer descriptor\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PDC_SetNextRx (\r
+ AT91PS_PDC pPDC, // \arg pointer to a PDC controller\r
+ char *address, // \arg address to the next bloc to be received\r
+ unsigned int bytes) // \arg number of bytes to be received\r
+{\r
+ pPDC->PDC_RNPR = (unsigned int) address;\r
+ pPDC->PDC_RNCR = bytes;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_SetNextTx\r
+//* \brief Set the next transmit transfer descriptor\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PDC_SetNextTx (\r
+ AT91PS_PDC pPDC, // \arg pointer to a PDC controller\r
+ char *address, // \arg address to the next bloc to be transmitted\r
+ unsigned int bytes) // \arg number of bytes to be transmitted\r
+{\r
+ pPDC->PDC_TNPR = (unsigned int) address;\r
+ pPDC->PDC_TNCR = bytes;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_SetRx\r
+//* \brief Set the receive transfer descriptor\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PDC_SetRx (\r
+ AT91PS_PDC pPDC, // \arg pointer to a PDC controller\r
+ char *address, // \arg address to the next bloc to be received\r
+ unsigned int bytes) // \arg number of bytes to be received\r
+{\r
+ pPDC->PDC_RPR = (unsigned int) address;\r
+ pPDC->PDC_RCR = bytes;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_SetTx\r
+//* \brief Set the transmit transfer descriptor\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PDC_SetTx (\r
+ AT91PS_PDC pPDC, // \arg pointer to a PDC controller\r
+ char *address, // \arg address to the next bloc to be transmitted\r
+ unsigned int bytes) // \arg number of bytes to be transmitted\r
+{\r
+ pPDC->PDC_TPR = (unsigned int) address;\r
+ pPDC->PDC_TCR = bytes;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_EnableTx\r
+//* \brief Enable transmit\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PDC_EnableTx (\r
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller\r
+{\r
+ pPDC->PDC_PTCR = AT91C_PDC_TXTEN;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_EnableRx\r
+//* \brief Enable receive\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PDC_EnableRx (\r
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller\r
+{\r
+ pPDC->PDC_PTCR = AT91C_PDC_RXTEN;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_DisableTx\r
+//* \brief Disable transmit\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PDC_DisableTx (\r
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller\r
+{\r
+ pPDC->PDC_PTCR = AT91C_PDC_TXTDIS;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_DisableRx\r
+//* \brief Disable receive\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PDC_DisableRx (\r
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller\r
+{\r
+ pPDC->PDC_PTCR = AT91C_PDC_RXTDIS;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_IsTxEmpty\r
+//* \brief Test if the current transfer descriptor has been sent\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete\r
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller\r
+{\r
+ return !(pPDC->PDC_TCR);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_IsNextTxEmpty\r
+//* \brief Test if the next transfer descriptor has been moved to the current td\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete\r
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller\r
+{\r
+ return !(pPDC->PDC_TNCR);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_IsRxEmpty\r
+//* \brief Test if the current transfer descriptor has been filled\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete\r
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller\r
+{\r
+ return !(pPDC->PDC_RCR);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_IsNextRxEmpty\r
+//* \brief Test if the next transfer descriptor has been moved to the current td\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete\r
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller\r
+{\r
+ return !(pPDC->PDC_RNCR);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_Open\r
+//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PDC_Open (\r
+ AT91PS_PDC pPDC) // \arg pointer to a PDC controller\r
+{\r
+ //* Disable the RX and TX PDC transfer requests\r
+ AT91F_PDC_DisableRx(pPDC);\r
+ AT91F_PDC_DisableTx(pPDC);\r
+\r
+ //* Reset all Counter register Next buffer first\r
+ AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);\r
+ AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);\r
+ AT91F_PDC_SetTx(pPDC, (char *) 0, 0);\r
+ AT91F_PDC_SetRx(pPDC, (char *) 0, 0);\r
+\r
+ //* Enable the RX and TX PDC transfer requests\r
+ AT91F_PDC_EnableRx(pPDC);\r
+ AT91F_PDC_EnableTx(pPDC);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_Close\r
+//* \brief Close PDC: disable TX and RX reset transfer descriptors\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PDC_Close (\r
+ AT91PS_PDC pPDC) // \arg pointer to a PDC controller\r
+{\r
+ //* Disable the RX and TX PDC transfer requests\r
+ AT91F_PDC_DisableRx(pPDC);\r
+ AT91F_PDC_DisableTx(pPDC);\r
+\r
+ //* Reset all Counter register Next buffer first\r
+ AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);\r
+ AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);\r
+ AT91F_PDC_SetTx(pPDC, (char *) 0, 0);\r
+ AT91F_PDC_SetRx(pPDC, (char *) 0, 0);\r
+\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_SendFrame\r
+//* \brief Close PDC: disable TX and RX reset transfer descriptors\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PDC_SendFrame(\r
+ AT91PS_PDC pPDC,\r
+ char *pBuffer,\r
+ unsigned int szBuffer,\r
+ char *pNextBuffer,\r
+ unsigned int szNextBuffer )\r
+{\r
+ if (AT91F_PDC_IsTxEmpty(pPDC)) {\r
+ //* Buffer and next buffer can be initialized\r
+ AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer);\r
+ AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer);\r
+ return 2;\r
+ }\r
+ else if (AT91F_PDC_IsNextTxEmpty(pPDC)) {\r
+ //* Only one buffer can be initialized\r
+ AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer);\r
+ return 1;\r
+ }\r
+ else {\r
+ //* All buffer are in use...\r
+ return 0;\r
+ }\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_ReceiveFrame\r
+//* \brief Close PDC: disable TX and RX reset transfer descriptors\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PDC_ReceiveFrame (\r
+ AT91PS_PDC pPDC,\r
+ char *pBuffer,\r
+ unsigned int szBuffer,\r
+ char *pNextBuffer,\r
+ unsigned int szNextBuffer )\r
+{\r
+ if (AT91F_PDC_IsRxEmpty(pPDC)) {\r
+ //* Buffer and next buffer can be initialized\r
+ AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer);\r
+ AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer);\r
+ return 2;\r
+ }\r
+ else if (AT91F_PDC_IsNextRxEmpty(pPDC)) {\r
+ //* Only one buffer can be initialized\r
+ AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer);\r
+ return 1;\r
+ }\r
+ else {\r
+ //* All buffer are in use...\r
+ return 0;\r
+ }\r
+}\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR DBGU\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_DBGU_InterruptEnable\r
+//* \brief Enable DBGU Interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_DBGU_InterruptEnable(\r
+ AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller\r
+ unsigned int flag) // \arg dbgu interrupt to be enabled\r
+{\r
+ pDbgu->DBGU_IER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_DBGU_InterruptDisable\r
+//* \brief Disable DBGU Interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_DBGU_InterruptDisable(\r
+ AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller\r
+ unsigned int flag) // \arg dbgu interrupt to be disabled\r
+{\r
+ pDbgu->DBGU_IDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_DBGU_GetInterruptMaskStatus\r
+//* \brief Return DBGU Interrupt Mask Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status\r
+ AT91PS_DBGU pDbgu) // \arg pointer to a DBGU controller\r
+{\r
+ return pDbgu->DBGU_IMR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_DBGU_IsInterruptMasked\r
+//* \brief Test if DBGU Interrupt is Masked \r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_DBGU_IsInterruptMasked(\r
+ AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag);\r
+}\r
+\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR SSC\r
+ ***************************************************************************** */\r
+//* Define the standard I2S mode configuration\r
+\r
+//* Configuration to set in the SSC Transmit Clock Mode Register\r
+//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits\r
+//* nb_slot_by_frame : number of channels\r
+#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\\r
+ AT91C_SSC_CKS_DIV +\\r
+ AT91C_SSC_CKO_CONTINOUS +\\r
+ AT91C_SSC_CKG_NONE +\\r
+ AT91C_SSC_START_FALL_RF +\\r
+ AT91C_SSC_STTOUT +\\r
+ ((1<<16) & AT91C_SSC_STTDLY) +\\r
+ ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24))\r
+\r
+\r
+//* Configuration to set in the SSC Transmit Frame Mode Register\r
+//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits\r
+//* nb_slot_by_frame : number of channels\r
+#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\\r
+ (nb_bit_by_slot-1) +\\r
+ AT91C_SSC_MSBF +\\r
+ (((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB) +\\r
+ (((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\\r
+ AT91C_SSC_FSOS_NEGATIVE)\r
+\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SSC_SetBaudrate\r
+//* \brief Set the baudrate according to the CPU clock\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SSC_SetBaudrate (\r
+ AT91PS_SSC pSSC, // \arg pointer to a SSC controller\r
+ unsigned int mainClock, // \arg peripheral clock\r
+ unsigned int speed) // \arg SSC baudrate\r
+{\r
+ unsigned int baud_value;\r
+ //* Define the baud rate divisor register\r
+ if (speed == 0)\r
+ baud_value = 0;\r
+ else\r
+ {\r
+ baud_value = (unsigned int) (mainClock * 10)/(2*speed);\r
+ if ((baud_value % 10) >= 5)\r
+ baud_value = (baud_value / 10) + 1;\r
+ else\r
+ baud_value /= 10;\r
+ }\r
+\r
+ pSSC->SSC_CMR = baud_value;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SSC_Configure\r
+//* \brief Configure SSC\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SSC_Configure (\r
+ AT91PS_SSC pSSC, // \arg pointer to a SSC controller\r
+ unsigned int syst_clock, // \arg System Clock Frequency\r
+ unsigned int baud_rate, // \arg Expected Baud Rate Frequency\r
+ unsigned int clock_rx, // \arg Receiver Clock Parameters\r
+ unsigned int mode_rx, // \arg mode Register to be programmed\r
+ unsigned int clock_tx, // \arg Transmitter Clock Parameters\r
+ unsigned int mode_tx) // \arg mode Register to be programmed\r
+{\r
+ //* Disable interrupts\r
+ pSSC->SSC_IDR = (unsigned int) -1;\r
+\r
+ //* Reset receiver and transmitter\r
+ pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ;\r
+\r
+ //* Define the Clock Mode Register\r
+ AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate);\r
+\r
+ //* Write the Receive Clock Mode Register\r
+ pSSC->SSC_RCMR = clock_rx;\r
+\r
+ //* Write the Transmit Clock Mode Register\r
+ pSSC->SSC_TCMR = clock_tx;\r
+\r
+ //* Write the Receive Frame Mode Register\r
+ pSSC->SSC_RFMR = mode_rx;\r
+\r
+ //* Write the Transmit Frame Mode Register\r
+ pSSC->SSC_TFMR = mode_tx;\r
+\r
+ //* Clear Transmit and Receive Counters\r
+ AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR));\r
+\r
+\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SSC_EnableRx\r
+//* \brief Enable receiving datas\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SSC_EnableRx (\r
+ AT91PS_SSC pSSC) // \arg pointer to a SSC controller\r
+{\r
+ //* Enable receiver\r
+ pSSC->SSC_CR = AT91C_SSC_RXEN;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SSC_DisableRx\r
+//* \brief Disable receiving datas\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SSC_DisableRx (\r
+ AT91PS_SSC pSSC) // \arg pointer to a SSC controller\r
+{\r
+ //* Disable receiver\r
+ pSSC->SSC_CR = AT91C_SSC_RXDIS;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SSC_EnableTx\r
+//* \brief Enable sending datas\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SSC_EnableTx (\r
+ AT91PS_SSC pSSC) // \arg pointer to a SSC controller\r
+{\r
+ //* Enable transmitter\r
+ pSSC->SSC_CR = AT91C_SSC_TXEN;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SSC_DisableTx\r
+//* \brief Disable sending datas\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SSC_DisableTx (\r
+ AT91PS_SSC pSSC) // \arg pointer to a SSC controller\r
+{\r
+ //* Disable transmitter\r
+ pSSC->SSC_CR = AT91C_SSC_TXDIS;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SSC_EnableIt\r
+//* \brief Enable SSC IT\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SSC_EnableIt (\r
+ AT91PS_SSC pSSC, // \arg pointer to a SSC controller\r
+ unsigned int flag) // \arg IT to be enabled\r
+{\r
+ //* Write to the IER register\r
+ pSSC->SSC_IER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SSC_DisableIt\r
+//* \brief Disable SSC IT\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SSC_DisableIt (\r
+ AT91PS_SSC pSSC, // \arg pointer to a SSC controller\r
+ unsigned int flag) // \arg IT to be disabled\r
+{\r
+ //* Write to the IDR register\r
+ pSSC->SSC_IDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SSC_ReceiveFrame\r
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_SSC_ReceiveFrame (\r
+ AT91PS_SSC pSSC,\r
+ char *pBuffer,\r
+ unsigned int szBuffer,\r
+ char *pNextBuffer,\r
+ unsigned int szNextBuffer )\r
+{\r
+ return AT91F_PDC_ReceiveFrame(\r
+ (AT91PS_PDC) &(pSSC->SSC_RPR),\r
+ pBuffer,\r
+ szBuffer,\r
+ pNextBuffer,\r
+ szNextBuffer);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SSC_SendFrame\r
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_SSC_SendFrame(\r
+ AT91PS_SSC pSSC,\r
+ char *pBuffer,\r
+ unsigned int szBuffer,\r
+ char *pNextBuffer,\r
+ unsigned int szNextBuffer )\r
+{\r
+ return AT91F_PDC_SendFrame(\r
+ (AT91PS_PDC) &(pSSC->SSC_RPR),\r
+ pBuffer,\r
+ szBuffer,\r
+ pNextBuffer,\r
+ szNextBuffer);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SSC_GetInterruptMaskStatus\r
+//* \brief Return SSC Interrupt Mask Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status\r
+ AT91PS_SSC pSsc) // \arg pointer to a SSC controller\r
+{\r
+ return pSsc->SSC_IMR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SSC_IsInterruptMasked\r
+//* \brief Test if SSC Interrupt is Masked \r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_SSC_IsInterruptMasked(\r
+ AT91PS_SSC pSsc, // \arg pointer to a SSC controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag);\r
+}\r
+\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR SPI\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_Open\r
+//* \brief Open a SPI Port\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_SPI_Open (\r
+ const unsigned int null) // \arg\r
+{\r
+ /* NOT DEFINED AT THIS MOMENT */\r
+ return ( 0 );\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_CfgCs\r
+//* \brief Configure SPI chip select register\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SPI_CfgCs (\r
+ AT91PS_SPI pSPI, // pointer to a SPI controller\r
+ int cs, // SPI cs number (0 to 3)\r
+ int val) // chip select register\r
+{\r
+ //* Write to the CSR register\r
+ *(pSPI->SPI_CSR + cs) = val;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_EnableIt\r
+//* \brief Enable SPI interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SPI_EnableIt (\r
+ AT91PS_SPI pSPI, // pointer to a SPI controller\r
+ unsigned int flag) // IT to be enabled\r
+{\r
+ //* Write to the IER register\r
+ pSPI->SPI_IER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_DisableIt\r
+//* \brief Disable SPI interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SPI_DisableIt (\r
+ AT91PS_SPI pSPI, // pointer to a SPI controller\r
+ unsigned int flag) // IT to be disabled\r
+{\r
+ //* Write to the IDR register\r
+ pSPI->SPI_IDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_Reset\r
+//* \brief Reset the SPI controller\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SPI_Reset (\r
+ AT91PS_SPI pSPI // pointer to a SPI controller\r
+ )\r
+{\r
+ //* Write to the CR register\r
+ pSPI->SPI_CR = AT91C_SPI_SWRST;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_Enable\r
+//* \brief Enable the SPI controller\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SPI_Enable (\r
+ AT91PS_SPI pSPI // pointer to a SPI controller\r
+ )\r
+{\r
+ //* Write to the CR register\r
+ pSPI->SPI_CR = AT91C_SPI_SPIEN;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_Disable\r
+//* \brief Disable the SPI controller\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SPI_Disable (\r
+ AT91PS_SPI pSPI // pointer to a SPI controller\r
+ )\r
+{\r
+ //* Write to the CR register\r
+ pSPI->SPI_CR = AT91C_SPI_SPIDIS;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_CfgMode\r
+//* \brief Enable the SPI controller\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SPI_CfgMode (\r
+ AT91PS_SPI pSPI, // pointer to a SPI controller\r
+ int mode) // mode register \r
+{\r
+ //* Write to the MR register\r
+ pSPI->SPI_MR = mode;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_CfgPCS\r
+//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SPI_CfgPCS (\r
+ AT91PS_SPI pSPI, // pointer to a SPI controller\r
+ char PCS_Device) // PCS of the Device\r
+{ \r
+ //* Write to the MR register\r
+ pSPI->SPI_MR &= 0xFFF0FFFF;\r
+ pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS );\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_ReceiveFrame\r
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_SPI_ReceiveFrame (\r
+ AT91PS_SPI pSPI,\r
+ char *pBuffer,\r
+ unsigned int szBuffer,\r
+ char *pNextBuffer,\r
+ unsigned int szNextBuffer )\r
+{\r
+ return AT91F_PDC_ReceiveFrame(\r
+ (AT91PS_PDC) &(pSPI->SPI_RPR),\r
+ pBuffer,\r
+ szBuffer,\r
+ pNextBuffer,\r
+ szNextBuffer);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_SendFrame\r
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_SPI_SendFrame(\r
+ AT91PS_SPI pSPI,\r
+ char *pBuffer,\r
+ unsigned int szBuffer,\r
+ char *pNextBuffer,\r
+ unsigned int szNextBuffer )\r
+{\r
+ return AT91F_PDC_SendFrame(\r
+ (AT91PS_PDC) &(pSPI->SPI_RPR),\r
+ pBuffer,\r
+ szBuffer,\r
+ pNextBuffer,\r
+ szNextBuffer);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_Close\r
+//* \brief Close SPI: disable IT disable transfert, close PDC\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SPI_Close (\r
+ AT91PS_SPI pSPI) // \arg pointer to a SPI controller\r
+{\r
+ //* Reset all the Chip Select register\r
+ pSPI->SPI_CSR[0] = 0 ;\r
+ pSPI->SPI_CSR[1] = 0 ;\r
+ pSPI->SPI_CSR[2] = 0 ;\r
+ pSPI->SPI_CSR[3] = 0 ;\r
+\r
+ //* Reset the SPI mode\r
+ pSPI->SPI_MR = 0 ;\r
+\r
+ //* Disable all interrupts\r
+ pSPI->SPI_IDR = 0xFFFFFFFF ;\r
+\r
+ //* Abort the Peripheral Data Transfers\r
+ AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR));\r
+\r
+ //* Disable receiver and transmitter and stop any activity immediately\r
+ pSPI->SPI_CR = AT91C_SPI_SPIDIS;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_PutChar\r
+//* \brief Send a character,does not check if ready to send\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SPI_PutChar (\r
+ AT91PS_SPI pSPI,\r
+ unsigned int character,\r
+ unsigned int cs_number )\r
+{\r
+ unsigned int value_for_cs;\r
+ value_for_cs = (~(1 << cs_number)) & 0xF; //Place a zero among a 4 ONEs number\r
+ pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_GetChar\r
+//* \brief Receive a character,does not check if a character is available\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_SPI_GetChar (\r
+ const AT91PS_SPI pSPI)\r
+{\r
+ return((pSPI->SPI_RDR) & 0xFFFF);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_GetInterruptMaskStatus\r
+//* \brief Return SPI Interrupt Mask Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status\r
+ AT91PS_SPI pSpi) // \arg pointer to a SPI controller\r
+{\r
+ return pSpi->SPI_IMR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_IsInterruptMasked\r
+//* \brief Test if SPI Interrupt is Masked \r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_SPI_IsInterruptMasked(\r
+ AT91PS_SPI pSpi, // \arg pointer to a SPI controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag);\r
+}\r
+\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR PWMC\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWM_GetStatus\r
+//* \brief Return PWM Interrupt Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PWMC_GetStatus( // \return PWM Interrupt Status\r
+ AT91PS_PWMC pPWM) // pointer to a PWM controller\r
+{\r
+ return pPWM->PWMC_SR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWM_InterruptEnable\r
+//* \brief Enable PWM Interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PWMC_InterruptEnable(\r
+ AT91PS_PWMC pPwm, // \arg pointer to a PWM controller\r
+ unsigned int flag) // \arg PWM interrupt to be enabled\r
+{\r
+ pPwm->PWMC_IER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWM_InterruptDisable\r
+//* \brief Disable PWM Interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PWMC_InterruptDisable(\r
+ AT91PS_PWMC pPwm, // \arg pointer to a PWM controller\r
+ unsigned int flag) // \arg PWM interrupt to be disabled\r
+{\r
+ pPwm->PWMC_IDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWM_GetInterruptMaskStatus\r
+//* \brief Return PWM Interrupt Mask Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( // \return PWM Interrupt Mask Status\r
+ AT91PS_PWMC pPwm) // \arg pointer to a PWM controller\r
+{\r
+ return pPwm->PWMC_IMR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWM_IsInterruptMasked\r
+//* \brief Test if PWM Interrupt is Masked\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PWMC_IsInterruptMasked(\r
+ AT91PS_PWMC pPWM, // \arg pointer to a PWM controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_PWMC_GetInterruptMaskStatus(pPWM) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWM_IsStatusSet\r
+//* \brief Test if PWM Interrupt is Set\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PWMC_IsStatusSet(\r
+ AT91PS_PWMC pPWM, // \arg pointer to a PWM controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_PWMC_GetStatus(pPWM) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWM_CfgChannel\r
+//* \brief Test if PWM Interrupt is Set\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PWMC_CfgChannel(\r
+ AT91PS_PWMC pPWM, // \arg pointer to a PWM controller\r
+ unsigned int channelId, // \arg PWM channel ID\r
+ unsigned int mode, // \arg PWM mode\r
+ unsigned int period, // \arg PWM period\r
+ unsigned int duty) // \arg PWM duty cycle\r
+{\r
+ pPWM->PWMC_CH[channelId].PWMC_CMR = mode;\r
+ pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty;\r
+ pPWM->PWMC_CH[channelId].PWMC_CPRDR = period;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWM_StartChannel\r
+//* \brief Enable channel\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PWMC_StartChannel(\r
+ AT91PS_PWMC pPWM, // \arg pointer to a PWM controller\r
+ unsigned int flag) // \arg Channels IDs to be enabled\r
+{\r
+ pPWM->PWMC_ENA = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWM_StopChannel\r
+//* \brief Disable channel\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PWMC_StopChannel(\r
+ AT91PS_PWMC pPWM, // \arg pointer to a PWM controller\r
+ unsigned int flag) // \arg Channels IDs to be enabled\r
+{\r
+ pPWM->PWMC_DIS = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWM_UpdateChannel\r
+//* \brief Update Period or Duty Cycle\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PWMC_UpdateChannel(\r
+ AT91PS_PWMC pPWM, // \arg pointer to a PWM controller\r
+ unsigned int channelId, // \arg PWM channel ID\r
+ unsigned int update) // \arg Channels IDs to be enabled\r
+{\r
+ pPWM->PWMC_CH[channelId].PWMC_CUPDR = update;\r
+}\r
+\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR TC\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TC_InterruptEnable\r
+//* \brief Enable TC Interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TC_InterruptEnable(\r
+ AT91PS_TC pTc, // \arg pointer to a TC controller\r
+ unsigned int flag) // \arg TC interrupt to be enabled\r
+{\r
+ pTc->TC_IER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TC_InterruptDisable\r
+//* \brief Disable TC Interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TC_InterruptDisable(\r
+ AT91PS_TC pTc, // \arg pointer to a TC controller\r
+ unsigned int flag) // \arg TC interrupt to be disabled\r
+{\r
+ pTc->TC_IDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TC_GetInterruptMaskStatus\r
+//* \brief Return TC Interrupt Mask Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status\r
+ AT91PS_TC pTc) // \arg pointer to a TC controller\r
+{\r
+ return pTc->TC_IMR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TC_IsInterruptMasked\r
+//* \brief Test if TC Interrupt is Masked \r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_TC_IsInterruptMasked(\r
+ AT91PS_TC pTc, // \arg pointer to a TC controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag);\r
+}\r
+\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR PMC\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_CfgSysClkEnableReg\r
+//* \brief Configure the System Clock Enable Register of the PMC controller\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PMC_CfgSysClkEnableReg (\r
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller\r
+ unsigned int mode)\r
+{\r
+ //* Write to the SCER register\r
+ pPMC->PMC_SCER = mode;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_CfgSysClkDisableReg\r
+//* \brief Configure the System Clock Disable Register of the PMC controller\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PMC_CfgSysClkDisableReg (\r
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller\r
+ unsigned int mode)\r
+{\r
+ //* Write to the SCDR register\r
+ pPMC->PMC_SCDR = mode;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_GetSysClkStatusReg\r
+//* \brief Return the System Clock Status Register of the PMC controller\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PMC_GetSysClkStatusReg (\r
+ AT91PS_PMC pPMC // pointer to a CAN controller\r
+ )\r
+{\r
+ return pPMC->PMC_SCSR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_EnablePeriphClock\r
+//* \brief Enable peripheral clock\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PMC_EnablePeriphClock (\r
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller\r
+ unsigned int periphIds) // \arg IDs of peripherals to enable\r
+{\r
+ pPMC->PMC_PCER = periphIds;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_DisablePeriphClock\r
+//* \brief Disable peripheral clock\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PMC_DisablePeriphClock (\r
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller\r
+ unsigned int periphIds) // \arg IDs of peripherals to enable\r
+{\r
+ pPMC->PMC_PCDR = periphIds;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_GetPeriphClock\r
+//* \brief Get peripheral clock status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PMC_GetPeriphClock (\r
+ AT91PS_PMC pPMC) // \arg pointer to PMC controller\r
+{\r
+ return pPMC->PMC_PCSR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CKGR_CfgMainOscillatorReg\r
+//* \brief Cfg the main oscillator\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CKGR_CfgMainOscillatorReg (\r
+ AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller\r
+ unsigned int mode)\r
+{\r
+ pCKGR->CKGR_MOR = mode;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CKGR_GetMainOscillatorReg\r
+//* \brief Cfg the main oscillator\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CKGR_GetMainOscillatorReg (\r
+ AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller\r
+{\r
+ return pCKGR->CKGR_MOR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CKGR_EnableMainOscillator\r
+//* \brief Enable the main oscillator\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CKGR_EnableMainOscillator(\r
+ AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller\r
+{\r
+ pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CKGR_DisableMainOscillator\r
+//* \brief Disable the main oscillator\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CKGR_DisableMainOscillator (\r
+ AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller\r
+{\r
+ pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CKGR_CfgMainOscStartUpTime\r
+//* \brief Cfg MOR Register according to the main osc startup time\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CKGR_CfgMainOscStartUpTime (\r
+ AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller\r
+ unsigned int startup_time, // \arg main osc startup time in microsecond (us)\r
+ unsigned int slowClock) // \arg slowClock in Hz\r
+{\r
+ pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT;\r
+ pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CKGR_GetMainClockFreqReg\r
+//* \brief Cfg the main oscillator\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CKGR_GetMainClockFreqReg (\r
+ AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller\r
+{\r
+ return pCKGR->CKGR_MCFR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CKGR_GetMainClock\r
+//* \brief Return Main clock in Hz\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CKGR_GetMainClock (\r
+ AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller\r
+ unsigned int slowClock) // \arg slowClock in Hz\r
+{\r
+ return ((pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF) * slowClock) >> 4;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_CfgMCKReg\r
+//* \brief Cfg Master Clock Register\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PMC_CfgMCKReg (\r
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller\r
+ unsigned int mode)\r
+{\r
+ pPMC->PMC_MCKR = mode;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_GetMCKReg\r
+//* \brief Return Master Clock Register\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PMC_GetMCKReg(\r
+ AT91PS_PMC pPMC) // \arg pointer to PMC controller\r
+{\r
+ return pPMC->PMC_MCKR;\r
+}\r
+\r
+//*------------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_GetMasterClock\r
+//* \brief Return master clock in Hz which correponds to processor clock for ARM7\r
+//*------------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PMC_GetMasterClock (\r
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller\r
+ AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller\r
+ unsigned int slowClock) // \arg slowClock in Hz\r
+{\r
+ unsigned int reg = pPMC->PMC_MCKR;\r
+ unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2));\r
+ unsigned int pllDivider, pllMultiplier;\r
+\r
+ switch (reg & AT91C_PMC_CSS) {\r
+ case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected\r
+ return slowClock / prescaler;\r
+ case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected\r
+ return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler;\r
+ case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected\r
+ reg = pCKGR->CKGR_PLLR;\r
+ pllDivider = (reg & AT91C_CKGR_DIV);\r
+ pllMultiplier = ((reg & AT91C_CKGR_MUL) >> 16) + 1;\r
+ return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler;\r
+ }\r
+ return 0;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_EnablePCK\r
+//* \brief Enable peripheral clock\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PMC_EnablePCK (\r
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller\r
+ unsigned int pck, // \arg Peripheral clock identifier 0 .. 7\r
+ unsigned int mode)\r
+{\r
+ pPMC->PMC_PCKR[pck] = mode;\r
+ pPMC->PMC_SCER = (1 << pck) << 8;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_DisablePCK\r
+//* \brief Enable peripheral clock\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PMC_DisablePCK (\r
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller\r
+ unsigned int pck) // \arg Peripheral clock identifier 0 .. 7\r
+{\r
+ pPMC->PMC_SCDR = (1 << pck) << 8;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_EnableIt\r
+//* \brief Enable PMC interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PMC_EnableIt (\r
+ AT91PS_PMC pPMC, // pointer to a PMC controller\r
+ unsigned int flag) // IT to be enabled\r
+{\r
+ //* Write to the IER register\r
+ pPMC->PMC_IER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_DisableIt\r
+//* \brief Disable PMC interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PMC_DisableIt (\r
+ AT91PS_PMC pPMC, // pointer to a PMC controller\r
+ unsigned int flag) // IT to be disabled\r
+{\r
+ //* Write to the IDR register\r
+ pPMC->PMC_IDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_GetStatus\r
+//* \brief Return PMC Interrupt Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status\r
+ AT91PS_PMC pPMC) // pointer to a PMC controller\r
+{\r
+ return pPMC->PMC_SR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_GetInterruptMaskStatus\r
+//* \brief Return PMC Interrupt Mask Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status\r
+ AT91PS_PMC pPMC) // pointer to a PMC controller\r
+{\r
+ return pPMC->PMC_IMR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_IsInterruptMasked\r
+//* \brief Test if PMC Interrupt is Masked\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PMC_IsInterruptMasked(\r
+ AT91PS_PMC pPMC, // \arg pointer to a PMC controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_IsStatusSet\r
+//* \brief Test if PMC Status is Set\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PMC_IsStatusSet(\r
+ AT91PS_PMC pPMC, // \arg pointer to a PMC controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_PMC_GetStatus(pPMC) & flag);\r
+}/* *****************************************************************************\r
+ SOFTWARE API FOR ADC\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_EnableIt\r
+//* \brief Enable ADC interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_ADC_EnableIt (\r
+ AT91PS_ADC pADC, // pointer to a ADC controller\r
+ unsigned int flag) // IT to be enabled\r
+{\r
+ //* Write to the IER register\r
+ pADC->ADC_IER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_DisableIt\r
+//* \brief Disable ADC interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_ADC_DisableIt (\r
+ AT91PS_ADC pADC, // pointer to a ADC controller\r
+ unsigned int flag) // IT to be disabled\r
+{\r
+ //* Write to the IDR register\r
+ pADC->ADC_IDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_GetStatus\r
+//* \brief Return ADC Interrupt Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_GetStatus( // \return ADC Interrupt Status\r
+ AT91PS_ADC pADC) // pointer to a ADC controller\r
+{\r
+ return pADC->ADC_SR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_GetInterruptMaskStatus\r
+//* \brief Return ADC Interrupt Mask Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_GetInterruptMaskStatus( // \return ADC Interrupt Mask Status\r
+ AT91PS_ADC pADC) // pointer to a ADC controller\r
+{\r
+ return pADC->ADC_IMR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_IsInterruptMasked\r
+//* \brief Test if ADC Interrupt is Masked \r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_IsInterruptMasked(\r
+ AT91PS_ADC pADC, // \arg pointer to a ADC controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_ADC_GetInterruptMaskStatus(pADC) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_IsStatusSet\r
+//* \brief Test if ADC Status is Set\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_IsStatusSet(\r
+ AT91PS_ADC pADC, // \arg pointer to a ADC controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_ADC_GetStatus(pADC) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_CfgModeReg\r
+//* \brief Configure the Mode Register of the ADC controller\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_ADC_CfgModeReg (\r
+ AT91PS_ADC pADC, // pointer to a ADC controller\r
+ unsigned int mode) // mode register \r
+{\r
+ //* Write to the MR register\r
+ pADC->ADC_MR = mode;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_GetModeReg\r
+//* \brief Return the Mode Register of the ADC controller value\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_GetModeReg (\r
+ AT91PS_ADC pADC // pointer to a ADC controller\r
+ )\r
+{\r
+ return pADC->ADC_MR; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_CfgTimings\r
+//* \brief Configure the different necessary timings of the ADC controller\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_ADC_CfgTimings (\r
+ AT91PS_ADC pADC, // pointer to a ADC controller\r
+ unsigned int mck_clock, // in MHz \r
+ unsigned int adc_clock, // in MHz \r
+ unsigned int startup_time, // in us \r
+ unsigned int sample_and_hold_time) // in ns \r
+{\r
+ unsigned int prescal,startup,shtim;\r
+ \r
+ prescal = mck_clock/(2*adc_clock) - 1;\r
+ startup = adc_clock*startup_time/8 - 1;\r
+ shtim = adc_clock*sample_and_hold_time/1000 - 1;\r
+ \r
+ //* Write to the MR register\r
+ pADC->ADC_MR = ( (prescal<<8) & AT91C_ADC_PRESCAL) | ( (startup<<16) & AT91C_ADC_STARTUP) | ( (shtim<<24) & AT91C_ADC_SHTIM);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_EnableChannel\r
+//* \brief Return ADC Timer Register Value\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_ADC_EnableChannel (\r
+ AT91PS_ADC pADC, // pointer to a ADC controller\r
+ unsigned int channel) // mode register \r
+{\r
+ //* Write to the CHER register\r
+ pADC->ADC_CHER = channel;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_DisableChannel\r
+//* \brief Return ADC Timer Register Value\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_ADC_DisableChannel (\r
+ AT91PS_ADC pADC, // pointer to a ADC controller\r
+ unsigned int channel) // mode register \r
+{\r
+ //* Write to the CHDR register\r
+ pADC->ADC_CHDR = channel;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_GetChannelStatus\r
+//* \brief Return ADC Timer Register Value\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_GetChannelStatus (\r
+ AT91PS_ADC pADC // pointer to a ADC controller\r
+ )\r
+{\r
+ return pADC->ADC_CHSR; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_StartConversion\r
+//* \brief Software request for a analog to digital conversion \r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_ADC_StartConversion (\r
+ AT91PS_ADC pADC // pointer to a ADC controller\r
+ )\r
+{\r
+ pADC->ADC_CR = AT91C_ADC_START; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_SoftReset\r
+//* \brief Software reset\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_ADC_SoftReset (\r
+ AT91PS_ADC pADC // pointer to a ADC controller\r
+ )\r
+{\r
+ pADC->ADC_CR = AT91C_ADC_SWRST; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_GetLastConvertedData\r
+//* \brief Return the Last Converted Data\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_GetLastConvertedData (\r
+ AT91PS_ADC pADC // pointer to a ADC controller\r
+ )\r
+{\r
+ return pADC->ADC_LCDR; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_GetConvertedDataCH0\r
+//* \brief Return the Channel 0 Converted Data\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_GetConvertedDataCH0 (\r
+ AT91PS_ADC pADC // pointer to a ADC controller\r
+ )\r
+{\r
+ return pADC->ADC_CDR0; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_GetConvertedDataCH1\r
+//* \brief Return the Channel 1 Converted Data\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_GetConvertedDataCH1 (\r
+ AT91PS_ADC pADC // pointer to a ADC controller\r
+ )\r
+{\r
+ return pADC->ADC_CDR1; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_GetConvertedDataCH2\r
+//* \brief Return the Channel 2 Converted Data\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_GetConvertedDataCH2 (\r
+ AT91PS_ADC pADC // pointer to a ADC controller\r
+ )\r
+{\r
+ return pADC->ADC_CDR2; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_GetConvertedDataCH3\r
+//* \brief Return the Channel 3 Converted Data\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_GetConvertedDataCH3 (\r
+ AT91PS_ADC pADC // pointer to a ADC controller\r
+ )\r
+{\r
+ return pADC->ADC_CDR3; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_GetConvertedDataCH4\r
+//* \brief Return the Channel 4 Converted Data\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_GetConvertedDataCH4 (\r
+ AT91PS_ADC pADC // pointer to a ADC controller\r
+ )\r
+{\r
+ return pADC->ADC_CDR4; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_GetConvertedDataCH5\r
+//* \brief Return the Channel 5 Converted Data\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_GetConvertedDataCH5 (\r
+ AT91PS_ADC pADC // pointer to a ADC controller\r
+ )\r
+{\r
+ return pADC->ADC_CDR5; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_GetConvertedDataCH6\r
+//* \brief Return the Channel 6 Converted Data\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_GetConvertedDataCH6 (\r
+ AT91PS_ADC pADC // pointer to a ADC controller\r
+ )\r
+{\r
+ return pADC->ADC_CDR6; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_GetConvertedDataCH7\r
+//* \brief Return the Channel 7 Converted Data\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_GetConvertedDataCH7 (\r
+ AT91PS_ADC pADC // pointer to a ADC controller\r
+ )\r
+{\r
+ return pADC->ADC_CDR7; \r
+}\r
+\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR PIO\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_CfgPeriph\r
+//* \brief Enable pins to be drived by peripheral\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_CfgPeriph(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int periphAEnable, // \arg PERIPH A to enable\r
+ unsigned int periphBEnable) // \arg PERIPH B to enable\r
+\r
+{\r
+ pPio->PIO_ASR = periphAEnable;\r
+ pPio->PIO_BSR = periphBEnable;\r
+ pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_CfgOutput\r
+//* \brief Enable PIO in output mode\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_CfgOutput(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int pioEnable) // \arg PIO to be enabled\r
+{\r
+ pPio->PIO_PER = pioEnable; // Set in PIO mode\r
+ pPio->PIO_OER = pioEnable; // Configure in Output\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_CfgInput\r
+//* \brief Enable PIO in input mode\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_CfgInput(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int inputEnable) // \arg PIO to be enabled\r
+{\r
+ // Disable output\r
+ pPio->PIO_ODR = inputEnable;\r
+ pPio->PIO_PER = inputEnable;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_CfgOpendrain\r
+//* \brief Configure PIO in open drain\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_CfgOpendrain(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int multiDrvEnable) // \arg pio to be configured in open drain\r
+{\r
+ // Configure the multi-drive option\r
+ pPio->PIO_MDDR = ~multiDrvEnable;\r
+ pPio->PIO_MDER = multiDrvEnable;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_CfgPullup\r
+//* \brief Enable pullup on PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_CfgPullup(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int pullupEnable) // \arg enable pullup on PIO\r
+{\r
+ // Connect or not Pullup\r
+ pPio->PIO_PPUDR = ~pullupEnable;\r
+ pPio->PIO_PPUER = pullupEnable;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_CfgDirectDrive\r
+//* \brief Enable direct drive on PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_CfgDirectDrive(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int directDrive) // \arg PIO to be configured with direct drive\r
+\r
+{\r
+ // Configure the Direct Drive\r
+ pPio->PIO_OWDR = ~directDrive;\r
+ pPio->PIO_OWER = directDrive;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_CfgInputFilter\r
+//* \brief Enable input filter on input PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_CfgInputFilter(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int inputFilter) // \arg PIO to be configured with input filter\r
+\r
+{\r
+ // Configure the Direct Drive\r
+ pPio->PIO_IFDR = ~inputFilter;\r
+ pPio->PIO_IFER = inputFilter;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_GetInput\r
+//* \brief Return PIO input value\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PIO_GetInput( // \return PIO input\r
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller\r
+{\r
+ return pPio->PIO_PDSR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_IsInputSet\r
+//* \brief Test if PIO is input flag is active\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PIO_IsInputSet(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_PIO_GetInput(pPio) & flag);\r
+}\r
+\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_SetOutput\r
+//* \brief Set to 1 output PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_SetOutput(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg output to be set\r
+{\r
+ pPio->PIO_SODR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_ClearOutput\r
+//* \brief Set to 0 output PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_ClearOutput(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg output to be cleared\r
+{\r
+ pPio->PIO_CODR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_ForceOutput\r
+//* \brief Force output when Direct drive option is enabled\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_ForceOutput(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg output to be forced\r
+{\r
+ pPio->PIO_ODSR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_Enable\r
+//* \brief Enable PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_Enable(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg pio to be enabled \r
+{\r
+ pPio->PIO_PER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_Disable\r
+//* \brief Disable PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_Disable(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg pio to be disabled \r
+{\r
+ pPio->PIO_PDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_GetStatus\r
+//* \brief Return PIO Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status\r
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller\r
+{\r
+ return pPio->PIO_PSR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_IsSet\r
+//* \brief Test if PIO is Set\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PIO_IsSet(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_PIO_GetStatus(pPio) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_OutputEnable\r
+//* \brief Output Enable PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_OutputEnable(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg pio output to be enabled\r
+{\r
+ pPio->PIO_OER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_OutputDisable\r
+//* \brief Output Enable PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_OutputDisable(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg pio output to be disabled\r
+{\r
+ pPio->PIO_ODR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_GetOutputStatus\r
+//* \brief Return PIO Output Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status\r
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller\r
+{\r
+ return pPio->PIO_OSR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_IsOuputSet\r
+//* \brief Test if PIO Output is Set\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PIO_IsOutputSet(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_PIO_GetOutputStatus(pPio) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_InputFilterEnable\r
+//* \brief Input Filter Enable PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_InputFilterEnable(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg pio input filter to be enabled\r
+{\r
+ pPio->PIO_IFER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_InputFilterDisable\r
+//* \brief Input Filter Disable PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_InputFilterDisable(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg pio input filter to be disabled\r
+{\r
+ pPio->PIO_IFDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_GetInputFilterStatus\r
+//* \brief Return PIO Input Filter Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status\r
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller\r
+{\r
+ return pPio->PIO_IFSR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_IsInputFilterSet\r
+//* \brief Test if PIO Input filter is Set\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PIO_IsInputFilterSet(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_PIO_GetInputFilterStatus(pPio) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_GetOutputDataStatus\r
+//* \brief Return PIO Output Data Status \r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status \r
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller\r
+{\r
+ return pPio->PIO_ODSR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_InterruptEnable\r
+//* \brief Enable PIO Interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_InterruptEnable(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg pio interrupt to be enabled\r
+{\r
+ pPio->PIO_IER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_InterruptDisable\r
+//* \brief Disable PIO Interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_InterruptDisable(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg pio interrupt to be disabled\r
+{\r
+ pPio->PIO_IDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_GetInterruptMaskStatus\r
+//* \brief Return PIO Interrupt Mask Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status\r
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller\r
+{\r
+ return pPio->PIO_IMR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_GetInterruptStatus\r
+//* \brief Return PIO Interrupt Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status\r
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller\r
+{\r
+ return pPio->PIO_ISR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_IsInterruptMasked\r
+//* \brief Test if PIO Interrupt is Masked \r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PIO_IsInterruptMasked(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_IsInterruptSet\r
+//* \brief Test if PIO Interrupt is Set\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PIO_IsInterruptSet(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_PIO_GetInterruptStatus(pPio) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_MultiDriverEnable\r
+//* \brief Multi Driver Enable PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_MultiDriverEnable(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg pio to be enabled\r
+{\r
+ pPio->PIO_MDER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_MultiDriverDisable\r
+//* \brief Multi Driver Disable PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_MultiDriverDisable(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg pio to be disabled\r
+{\r
+ pPio->PIO_MDDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_GetMultiDriverStatus\r
+//* \brief Return PIO Multi Driver Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status\r
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller\r
+{\r
+ return pPio->PIO_MDSR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_IsMultiDriverSet\r
+//* \brief Test if PIO MultiDriver is Set\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PIO_IsMultiDriverSet(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_A_RegisterSelection\r
+//* \brief PIO A Register Selection \r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_A_RegisterSelection(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg pio A register selection\r
+{\r
+ pPio->PIO_ASR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_B_RegisterSelection\r
+//* \brief PIO B Register Selection \r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_B_RegisterSelection(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg pio B register selection \r
+{\r
+ pPio->PIO_BSR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_Get_AB_RegisterStatus\r
+//* \brief Return PIO Interrupt Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status\r
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller\r
+{\r
+ return pPio->PIO_ABSR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_IsAB_RegisterSet\r
+//* \brief Test if PIO AB Register is Set\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PIO_IsAB_RegisterSet(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_OutputWriteEnable\r
+//* \brief Output Write Enable PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_OutputWriteEnable(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg pio output write to be enabled\r
+{\r
+ pPio->PIO_OWER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_OutputWriteDisable\r
+//* \brief Output Write Disable PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_OutputWriteDisable(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg pio output write to be disabled\r
+{\r
+ pPio->PIO_OWDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_GetOutputWriteStatus\r
+//* \brief Return PIO Output Write Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status\r
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller\r
+{\r
+ return pPio->PIO_OWSR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_IsOutputWriteSet\r
+//* \brief Test if PIO OutputWrite is Set\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PIO_IsOutputWriteSet(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_GetCfgPullup\r
+//* \brief Return PIO Configuration Pullup\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup \r
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller\r
+{\r
+ return pPio->PIO_PPUSR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_IsOutputDataStatusSet\r
+//* \brief Test if PIO Output Data Status is Set \r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PIO_IsOutputDataStatusSet(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_PIO_GetOutputDataStatus(pPio) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_IsCfgPullupStatusSet\r
+//* \brief Test if PIO Configuration Pullup Status is Set\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PIO_IsCfgPullupStatusSet(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (~AT91F_PIO_GetCfgPullup(pPio) & flag);\r
+}\r
+\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR TWI\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TWI_EnableIt\r
+//* \brief Enable TWI IT\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TWI_EnableIt (\r
+ AT91PS_TWI pTWI, // \arg pointer to a TWI controller\r
+ unsigned int flag) // \arg IT to be enabled\r
+{\r
+ //* Write to the IER register\r
+ pTWI->TWI_IER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TWI_DisableIt\r
+//* \brief Disable TWI IT\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TWI_DisableIt (\r
+ AT91PS_TWI pTWI, // \arg pointer to a TWI controller\r
+ unsigned int flag) // \arg IT to be disabled\r
+{\r
+ //* Write to the IDR register\r
+ pTWI->TWI_IDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TWI_Configure\r
+//* \brief Configure TWI in master mode\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI ) // \arg pointer to a TWI controller\r
+{\r
+ //* Disable interrupts\r
+ pTWI->TWI_IDR = (unsigned int) -1;\r
+\r
+ //* Reset peripheral\r
+ pTWI->TWI_CR = AT91C_TWI_SWRST;\r
+\r
+ //* Set Master mode\r
+ pTWI->TWI_CR = AT91C_TWI_MSEN | AT91C_TWI_SVDIS;\r
+\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TWI_GetInterruptMaskStatus\r
+//* \brief Return TWI Interrupt Mask Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status\r
+ AT91PS_TWI pTwi) // \arg pointer to a TWI controller\r
+{\r
+ return pTwi->TWI_IMR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TWI_IsInterruptMasked\r
+//* \brief Test if TWI Interrupt is Masked \r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_TWI_IsInterruptMasked(\r
+ AT91PS_TWI pTwi, // \arg pointer to a TWI controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag);\r
+}\r
+\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR USART\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_Baudrate\r
+//* \brief Calculate the baudrate\r
+//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity\r
+#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \\r
+ AT91C_US_NBSTOP_1_BIT + \\r
+ AT91C_US_PAR_NONE + \\r
+ AT91C_US_CHRL_8_BITS + \\r
+ AT91C_US_CLKS_CLOCK )\r
+\r
+//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity\r
+#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \\r
+ AT91C_US_NBSTOP_1_BIT + \\r
+ AT91C_US_PAR_NONE + \\r
+ AT91C_US_CHRL_8_BITS + \\r
+ AT91C_US_CLKS_EXT )\r
+\r
+//* Standard Synchronous Mode : 8 bits , 1 stop , no parity\r
+#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \\r
+ AT91C_US_USMODE_NORMAL + \\r
+ AT91C_US_NBSTOP_1_BIT + \\r
+ AT91C_US_PAR_NONE + \\r
+ AT91C_US_CHRL_8_BITS + \\r
+ AT91C_US_CLKS_CLOCK )\r
+\r
+//* SCK used Label\r
+#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT)\r
+\r
+//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity\r
+#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \\r
+ AT91C_US_CLKS_CLOCK +\\r
+ AT91C_US_NBSTOP_1_BIT + \\r
+ AT91C_US_PAR_EVEN + \\r
+ AT91C_US_CHRL_8_BITS + \\r
+ AT91C_US_CKLO +\\r
+ AT91C_US_OVER)\r
+\r
+//* Standard IRDA mode\r
+#define AT91C_US_ASYNC_IRDA_MODE ( AT91C_US_USMODE_IRDA + \\r
+ AT91C_US_NBSTOP_1_BIT + \\r
+ AT91C_US_PAR_NONE + \\r
+ AT91C_US_CHRL_8_BITS + \\r
+ AT91C_US_CLKS_CLOCK )\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_Baudrate\r
+//* \brief Caluculate baud_value according to the main clock and the baud rate\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_US_Baudrate (\r
+ const unsigned int main_clock, // \arg peripheral clock\r
+ const unsigned int baud_rate) // \arg UART baudrate\r
+{\r
+ unsigned int baud_value = ((main_clock*10)/(baud_rate * 16));\r
+ if ((baud_value % 10) >= 5)\r
+ baud_value = (baud_value / 10) + 1;\r
+ else\r
+ baud_value /= 10;\r
+ return baud_value;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_SetBaudrate\r
+//* \brief Set the baudrate according to the CPU clock\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US_SetBaudrate (\r
+ AT91PS_USART pUSART, // \arg pointer to a USART controller\r
+ unsigned int mainClock, // \arg peripheral clock\r
+ unsigned int speed) // \arg UART baudrate\r
+{\r
+ //* Define the baud rate divisor register\r
+ pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_SetTimeguard\r
+//* \brief Set USART timeguard\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US_SetTimeguard (\r
+ AT91PS_USART pUSART, // \arg pointer to a USART controller\r
+ unsigned int timeguard) // \arg timeguard value\r
+{\r
+ //* Write the Timeguard Register\r
+ pUSART->US_TTGR = timeguard ;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_EnableIt\r
+//* \brief Enable USART IT\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US_EnableIt (\r
+ AT91PS_USART pUSART, // \arg pointer to a USART controller\r
+ unsigned int flag) // \arg IT to be enabled\r
+{\r
+ //* Write to the IER register\r
+ pUSART->US_IER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_DisableIt\r
+//* \brief Disable USART IT\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US_DisableIt (\r
+ AT91PS_USART pUSART, // \arg pointer to a USART controller\r
+ unsigned int flag) // \arg IT to be disabled\r
+{\r
+ //* Write to the IER register\r
+ pUSART->US_IDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_Configure\r
+//* \brief Configure USART\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US_Configure (\r
+ AT91PS_USART pUSART, // \arg pointer to a USART controller\r
+ unsigned int mainClock, // \arg peripheral clock\r
+ unsigned int mode , // \arg mode Register to be programmed\r
+ unsigned int baudRate , // \arg baudrate to be programmed\r
+ unsigned int timeguard ) // \arg timeguard to be programmed\r
+{\r
+ //* Disable interrupts\r
+ pUSART->US_IDR = (unsigned int) -1;\r
+\r
+ //* Reset receiver and transmitter\r
+ pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ;\r
+\r
+ //* Define the baud rate divisor register\r
+ AT91F_US_SetBaudrate(pUSART, mainClock, baudRate);\r
+\r
+ //* Write the Timeguard Register\r
+ AT91F_US_SetTimeguard(pUSART, timeguard);\r
+\r
+ //* Clear Transmit and Receive Counters\r
+ AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR));\r
+\r
+ //* Define the USART mode\r
+ pUSART->US_MR = mode ;\r
+\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_EnableRx\r
+//* \brief Enable receiving characters\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US_EnableRx (\r
+ AT91PS_USART pUSART) // \arg pointer to a USART controller\r
+{\r
+ //* Enable receiver\r
+ pUSART->US_CR = AT91C_US_RXEN;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_EnableTx\r
+//* \brief Enable sending characters\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US_EnableTx (\r
+ AT91PS_USART pUSART) // \arg pointer to a USART controller\r
+{\r
+ //* Enable transmitter\r
+ pUSART->US_CR = AT91C_US_TXEN;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_ResetRx\r
+//* \brief Reset Receiver and re-enable it\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US_ResetRx (\r
+ AT91PS_USART pUSART) // \arg pointer to a USART controller\r
+{\r
+ //* Reset receiver\r
+ pUSART->US_CR = AT91C_US_RSTRX;\r
+ //* Re-Enable receiver\r
+ pUSART->US_CR = AT91C_US_RXEN;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_ResetTx\r
+//* \brief Reset Transmitter and re-enable it\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US_ResetTx (\r
+ AT91PS_USART pUSART) // \arg pointer to a USART controller\r
+{\r
+ //* Reset transmitter\r
+ pUSART->US_CR = AT91C_US_RSTTX;\r
+ //* Enable transmitter\r
+ pUSART->US_CR = AT91C_US_TXEN;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_DisableRx\r
+//* \brief Disable Receiver\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US_DisableRx (\r
+ AT91PS_USART pUSART) // \arg pointer to a USART controller\r
+{\r
+ //* Disable receiver\r
+ pUSART->US_CR = AT91C_US_RXDIS;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_DisableTx\r
+//* \brief Disable Transmitter\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US_DisableTx (\r
+ AT91PS_USART pUSART) // \arg pointer to a USART controller\r
+{\r
+ //* Disable transmitter\r
+ pUSART->US_CR = AT91C_US_TXDIS;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_Close\r
+//* \brief Close USART: disable IT disable receiver and transmitter, close PDC\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US_Close (\r
+ AT91PS_USART pUSART) // \arg pointer to a USART controller\r
+{\r
+ //* Reset the baud rate divisor register\r
+ pUSART->US_BRGR = 0 ;\r
+\r
+ //* Reset the USART mode\r
+ pUSART->US_MR = 0 ;\r
+\r
+ //* Reset the Timeguard Register\r
+ pUSART->US_TTGR = 0;\r
+\r
+ //* Disable all interrupts\r
+ pUSART->US_IDR = 0xFFFFFFFF ;\r
+\r
+ //* Abort the Peripheral Data Transfers\r
+ AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR));\r
+\r
+ //* Disable receiver and transmitter and stop any activity immediately\r
+ pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_TxReady\r
+//* \brief Return 1 if a character can be written in US_THR\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_US_TxReady (\r
+ AT91PS_USART pUSART ) // \arg pointer to a USART controller\r
+{\r
+ return (pUSART->US_CSR & AT91C_US_TXRDY);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_RxReady\r
+//* \brief Return 1 if a character can be read in US_RHR\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_US_RxReady (\r
+ AT91PS_USART pUSART ) // \arg pointer to a USART controller\r
+{\r
+ return (pUSART->US_CSR & AT91C_US_RXRDY);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_Error\r
+//* \brief Return the error flag\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_US_Error (\r
+ AT91PS_USART pUSART ) // \arg pointer to a USART controller\r
+{\r
+ return (pUSART->US_CSR &\r
+ (AT91C_US_OVRE | // Overrun error\r
+ AT91C_US_FRAME | // Framing error\r
+ AT91C_US_PARE)); // Parity error\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_PutChar\r
+//* \brief Send a character,does not check if ready to send\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US_PutChar (\r
+ AT91PS_USART pUSART,\r
+ int character )\r
+{\r
+ pUSART->US_THR = (character & 0x1FF);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_GetChar\r
+//* \brief Receive a character,does not check if a character is available\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_US_GetChar (\r
+ const AT91PS_USART pUSART)\r
+{\r
+ return((pUSART->US_RHR) & 0x1FF);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_SendFrame\r
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_US_SendFrame(\r
+ AT91PS_USART pUSART,\r
+ char *pBuffer,\r
+ unsigned int szBuffer,\r
+ char *pNextBuffer,\r
+ unsigned int szNextBuffer )\r
+{\r
+ return AT91F_PDC_SendFrame(\r
+ (AT91PS_PDC) &(pUSART->US_RPR),\r
+ pBuffer,\r
+ szBuffer,\r
+ pNextBuffer,\r
+ szNextBuffer);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_ReceiveFrame\r
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_US_ReceiveFrame (\r
+ AT91PS_USART pUSART,\r
+ char *pBuffer,\r
+ unsigned int szBuffer,\r
+ char *pNextBuffer,\r
+ unsigned int szNextBuffer )\r
+{\r
+ return AT91F_PDC_ReceiveFrame(\r
+ (AT91PS_PDC) &(pUSART->US_RPR),\r
+ pBuffer,\r
+ szBuffer,\r
+ pNextBuffer,\r
+ szNextBuffer);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_SetIrdaFilter\r
+//* \brief Set the value of IrDa filter tregister\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US_SetIrdaFilter (\r
+ AT91PS_USART pUSART,\r
+ unsigned char value\r
+)\r
+{\r
+ pUSART->US_IF = value;\r
+}\r
+\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR UDP\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_EnableIt\r
+//* \brief Enable UDP IT\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_UDP_EnableIt (\r
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller\r
+ unsigned int flag) // \arg IT to be enabled\r
+{\r
+ //* Write to the IER register\r
+ pUDP->UDP_IER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_DisableIt\r
+//* \brief Disable UDP IT\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_UDP_DisableIt (\r
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller\r
+ unsigned int flag) // \arg IT to be disabled\r
+{\r
+ //* Write to the IDR register\r
+ pUDP->UDP_IDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_SetAddress\r
+//* \brief Set UDP functional address\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_UDP_SetAddress (\r
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller\r
+ unsigned char address) // \arg new UDP address\r
+{\r
+ pUDP->UDP_FADDR = (AT91C_UDP_FEN | address);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_EnableEp\r
+//* \brief Enable Endpoint\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_UDP_EnableEp (\r
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller\r
+ unsigned int flag) // \arg endpoints to be enabled\r
+{\r
+ pUDP->UDP_GLBSTATE |= flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_DisableEp\r
+//* \brief Enable Endpoint\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_UDP_DisableEp (\r
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller\r
+ unsigned int flag) // \arg endpoints to be enabled\r
+{\r
+ pUDP->UDP_GLBSTATE &= ~(flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_SetState\r
+//* \brief Set UDP Device state\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_UDP_SetState (\r
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller\r
+ unsigned int flag) // \arg new UDP address\r
+{\r
+ pUDP->UDP_GLBSTATE &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG);\r
+ pUDP->UDP_GLBSTATE |= flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_GetState\r
+//* \brief return UDP Device state\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state\r
+ AT91PS_UDP pUDP) // \arg pointer to a UDP controller\r
+{\r
+ return (pUDP->UDP_GLBSTATE & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_ResetEp\r
+//* \brief Reset UDP endpoint\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_UDP_ResetEp ( // \return the UDP device state\r
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller\r
+ unsigned int flag) // \arg Endpoints to be reset\r
+{\r
+ pUDP->UDP_RSTEP = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_EpStall\r
+//* \brief Endpoint will STALL requests\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_UDP_EpStall(\r
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller\r
+ unsigned char endpoint) // \arg endpoint number\r
+{\r
+ pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_EpWrite\r
+//* \brief Write value in the DPR\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_UDP_EpWrite(\r
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller\r
+ unsigned char endpoint, // \arg endpoint number\r
+ unsigned char value) // \arg value to be written in the DPR\r
+{\r
+ pUDP->UDP_FDR[endpoint] = value;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_EpRead\r
+//* \brief Return value from the DPR\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_UDP_EpRead(\r
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller\r
+ unsigned char endpoint) // \arg endpoint number\r
+{\r
+ return pUDP->UDP_FDR[endpoint];\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_EpEndOfWr\r
+//* \brief Notify the UDP that values in DPR are ready to be sent\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_UDP_EpEndOfWr(\r
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller\r
+ unsigned char endpoint) // \arg endpoint number\r
+{\r
+ pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_EpClear\r
+//* \brief Clear flag in the endpoint CSR register\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_UDP_EpClear(\r
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller\r
+ unsigned char endpoint, // \arg endpoint number\r
+ unsigned int flag) // \arg flag to be cleared\r
+{\r
+ pUDP->UDP_CSR[endpoint] &= ~(flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_EpSet\r
+//* \brief Set flag in the endpoint CSR register\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_UDP_EpSet(\r
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller\r
+ unsigned char endpoint, // \arg endpoint number\r
+ unsigned int flag) // \arg flag to be cleared\r
+{\r
+ pUDP->UDP_CSR[endpoint] |= flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_EpStatus\r
+//* \brief Return the endpoint CSR register\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_UDP_EpStatus(\r
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller\r
+ unsigned char endpoint) // \arg endpoint number\r
+{\r
+ return pUDP->UDP_CSR[endpoint];\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_GetInterruptMaskStatus\r
+//* \brief Return UDP Interrupt Mask Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \return UDP Interrupt Mask Status\r
+ AT91PS_UDP pUdp) // \arg pointer to a UDP controller\r
+{\r
+ return pUdp->UDP_IMR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_IsInterruptMasked\r
+//* \brief Test if UDP Interrupt is Masked \r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_UDP_IsInterruptMasked(\r
+ AT91PS_UDP pUdp, // \arg pointer to a UDP controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag);\r
+}\r
+\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR AIC\r
+ ***************************************************************************** */\r
+#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20]\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AIC_ConfigureIt\r
+//* \brief Interrupt Handler Initialization\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_AIC_ConfigureIt (\r
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers\r
+ unsigned int irq_id, // \arg interrupt number to initialize\r
+ unsigned int priority, // \arg priority to give to the interrupt\r
+ unsigned int src_type, // \arg activation and sense of activation\r
+ void (*newHandler) (void) ) // \arg address of the interrupt handler\r
+{\r
+ unsigned int oldHandler;\r
+ unsigned int mask ;\r
+\r
+ oldHandler = pAic->AIC_SVR[irq_id];\r
+\r
+ mask = 0x1 << irq_id ;\r
+ //* Disable the interrupt on the interrupt controller\r
+ pAic->AIC_IDCR = mask ;\r
+ //* Save the interrupt handler routine pointer and the interrupt priority\r
+ pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ;\r
+ //* Store the Source Mode Register\r
+ pAic->AIC_SMR[irq_id] = src_type | priority ;\r
+ //* Clear the interrupt on the interrupt controller\r
+ pAic->AIC_ICCR = mask ;\r
+\r
+ return oldHandler;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AIC_EnableIt\r
+//* \brief Enable corresponding IT number\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AIC_EnableIt (\r
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers\r
+ unsigned int irq_id ) // \arg interrupt number to initialize\r
+{\r
+ //* Enable the interrupt on the interrupt controller\r
+ pAic->AIC_IECR = 0x1 << irq_id ;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AIC_DisableIt\r
+//* \brief Disable corresponding IT number\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AIC_DisableIt (\r
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers\r
+ unsigned int irq_id ) // \arg interrupt number to initialize\r
+{\r
+ unsigned int mask = 0x1 << irq_id;\r
+ //* Disable the interrupt on the interrupt controller\r
+ pAic->AIC_IDCR = mask ;\r
+ //* Clear the interrupt on the Interrupt Controller ( if one is pending )\r
+ pAic->AIC_ICCR = mask ;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AIC_ClearIt\r
+//* \brief Clear corresponding IT number\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AIC_ClearIt (\r
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers\r
+ unsigned int irq_id) // \arg interrupt number to initialize\r
+{\r
+ //* Clear the interrupt on the Interrupt Controller ( if one is pending )\r
+ pAic->AIC_ICCR = (0x1 << irq_id);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AIC_AcknowledgeIt\r
+//* \brief Acknowledge corresponding IT number\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AIC_AcknowledgeIt (\r
+ AT91PS_AIC pAic) // \arg pointer to the AIC registers\r
+{\r
+ pAic->AIC_EOICR = pAic->AIC_EOICR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AIC_SetExceptionVector\r
+//* \brief Configure vector handler\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_AIC_SetExceptionVector (\r
+ unsigned int *pVector, // \arg pointer to the AIC registers\r
+ void (*Handler) () ) // \arg Interrupt Handler\r
+{\r
+ unsigned int oldVector = *pVector;\r
+\r
+ if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE)\r
+ *pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE;\r
+ else\r
+ *pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000;\r
+\r
+ return oldVector;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AIC_Trig\r
+//* \brief Trig an IT\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AIC_Trig (\r
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers\r
+ unsigned int irq_id) // \arg interrupt number\r
+{\r
+ pAic->AIC_ISCR = (0x1 << irq_id) ;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AIC_IsActive\r
+//* \brief Test if an IT is active\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_AIC_IsActive (\r
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers\r
+ unsigned int irq_id) // \arg Interrupt Number\r
+{\r
+ return (pAic->AIC_ISR & (0x1 << irq_id));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AIC_IsPending\r
+//* \brief Test if an IT is pending\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_AIC_IsPending (\r
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers\r
+ unsigned int irq_id) // \arg Interrupt Number\r
+{\r
+ return (pAic->AIC_IPR & (0x1 << irq_id));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AIC_Open\r
+//* \brief Set exception vectors and AIC registers to default values\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AIC_Open(\r
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers\r
+ void (*IrqHandler) (), // \arg Default IRQ vector exception\r
+ void (*FiqHandler) (), // \arg Default FIQ vector exception\r
+ void (*DefaultHandler) (), // \arg Default Handler set in ISR\r
+ void (*SpuriousHandler) (), // \arg Default Spurious Handler\r
+ unsigned int protectMode) // \arg Debug Control Register\r
+{\r
+ int i;\r
+\r
+ // Disable all interrupts and set IVR to the default handler\r
+ for (i = 0; i < 32; ++i) {\r
+ AT91F_AIC_DisableIt(pAic, i);\r
+ AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE, DefaultHandler);\r
+ }\r
+\r
+ // Set the IRQ exception vector\r
+ AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler);\r
+ // Set the Fast Interrupt exception vector\r
+ AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler);\r
+\r
+ pAic->AIC_SPU = (unsigned int) SpuriousHandler;\r
+ pAic->AIC_DCR = protectMode;\r
+}\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_MC_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for MC\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_MC_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_SYS));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_DBGU_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for DBGU\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_DBGU_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_SYS));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_DBGU_CfgPIO\r
+//* \brief Configure PIO controllers to drive DBGU signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_DBGU_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOA, // PIO controller base address\r
+ ((unsigned int) AT91C_PA10_DTXD ) |\r
+ ((unsigned int) AT91C_PA9_DRXD ), // Peripheral A\r
+ 0); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWMC_CH3_CfgPIO\r
+//* \brief Configure PIO controllers to drive PWMC_CH3 signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PWMC_CH3_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOA, // PIO controller base address\r
+ 0, // Peripheral A\r
+ ((unsigned int) AT91C_PA14_PWM3 ) |\r
+ ((unsigned int) AT91C_PA7_PWM3 )); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWMC_CH2_CfgPIO\r
+//* \brief Configure PIO controllers to drive PWMC_CH2 signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PWMC_CH2_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOA, // PIO controller base address\r
+ ((unsigned int) AT91C_PA2_PWM2 ), // Peripheral A\r
+ ((unsigned int) AT91C_PA25_PWM2 ) |\r
+ ((unsigned int) AT91C_PA13_PWM2 )); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWMC_CH1_CfgPIO\r
+//* \brief Configure PIO controllers to drive PWMC_CH1 signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PWMC_CH1_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOA, // PIO controller base address\r
+ ((unsigned int) AT91C_PA1_PWM1 ), // Peripheral A\r
+ ((unsigned int) AT91C_PA24_PWM1 ) |\r
+ ((unsigned int) AT91C_PA12_PWM1 )); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWMC_CH0_CfgPIO\r
+//* \brief Configure PIO controllers to drive PWMC_CH0 signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PWMC_CH0_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOA, // PIO controller base address\r
+ ((unsigned int) AT91C_PA0_PWM0 ), // Peripheral A\r
+ ((unsigned int) AT91C_PA23_PWM0 ) |\r
+ ((unsigned int) AT91C_PA11_PWM0 )); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SSC_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for SSC\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SSC_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_SSC));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SSC_CfgPIO\r
+//* \brief Configure PIO controllers to drive SSC signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SSC_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOA, // PIO controller base address\r
+ ((unsigned int) AT91C_PA17_TD ) |\r
+ ((unsigned int) AT91C_PA15_TF ) |\r
+ ((unsigned int) AT91C_PA19_RK ) |\r
+ ((unsigned int) AT91C_PA18_RD ) |\r
+ ((unsigned int) AT91C_PA20_RF ) |\r
+ ((unsigned int) AT91C_PA16_TK ), // Peripheral A\r
+ 0); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for SPI\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SPI_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_SPI));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_CfgPIO\r
+//* \brief Configure PIO controllers to drive SPI signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SPI_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOA, // PIO controller base address\r
+ ((unsigned int) AT91C_PA11_NPCS0 ) |\r
+ ((unsigned int) AT91C_PA13_MOSI ) |\r
+ ((unsigned int) AT91C_PA31_NPCS1 ) |\r
+ ((unsigned int) AT91C_PA12_MISO ) |\r
+ ((unsigned int) AT91C_PA14_SPCK ), // Peripheral A\r
+ ((unsigned int) AT91C_PA9_NPCS1 ) |\r
+ ((unsigned int) AT91C_PA30_NPCS2 ) |\r
+ ((unsigned int) AT91C_PA10_NPCS2 ) |\r
+ ((unsigned int) AT91C_PA22_NPCS3 ) |\r
+ ((unsigned int) AT91C_PA3_NPCS3 ) |\r
+ ((unsigned int) AT91C_PA5_NPCS3 )); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWMC_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for PWMC\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PWMC_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_PWMC));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TC2_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for TC2\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TC2_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_TC2));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TC2_CfgPIO\r
+//* \brief Configure PIO controllers to drive TC2 signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TC2_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOA, // PIO controller base address\r
+ 0, // Peripheral A\r
+ ((unsigned int) AT91C_PA26_TIOA2 ) |\r
+ ((unsigned int) AT91C_PA27_TIOB2 ) |\r
+ ((unsigned int) AT91C_PA29_TCLK2 )); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TC1_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for TC1\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TC1_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_TC1));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TC1_CfgPIO\r
+//* \brief Configure PIO controllers to drive TC1 signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TC1_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOA, // PIO controller base address\r
+ 0, // Peripheral A\r
+ ((unsigned int) AT91C_PA15_TIOA1 ) |\r
+ ((unsigned int) AT91C_PA16_TIOB1 ) |\r
+ ((unsigned int) AT91C_PA28_TCLK1 )); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TC0_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for TC0\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TC0_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_TC0));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TC0_CfgPIO\r
+//* \brief Configure PIO controllers to drive TC0 signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TC0_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOA, // PIO controller base address\r
+ 0, // Peripheral A\r
+ ((unsigned int) AT91C_PA0_TIOA0 ) |\r
+ ((unsigned int) AT91C_PA1_TIOB0 ) |\r
+ ((unsigned int) AT91C_PA4_TCLK0 )); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for PMC\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PMC_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_SYS));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_CfgPIO\r
+//* \brief Configure PIO controllers to drive PMC signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PMC_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOA, // PIO controller base address\r
+ 0, // Peripheral A\r
+ ((unsigned int) AT91C_PA17_PCK1 ) |\r
+ ((unsigned int) AT91C_PA21_PCK1 ) |\r
+ ((unsigned int) AT91C_PA31_PCK2 ) |\r
+ ((unsigned int) AT91C_PA18_PCK2 ) |\r
+ ((unsigned int) AT91C_PA6_PCK0 )); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for ADC\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_ADC_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_ADC));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_CfgPIO\r
+//* \brief Configure PIO controllers to drive ADC signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_ADC_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOA, // PIO controller base address\r
+ 0, // Peripheral A\r
+ ((unsigned int) AT91C_PA8_ADTRG )); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIOA_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for PIOA\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIOA_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_PIOA));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TWI_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for TWI\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TWI_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_TWI));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TWI_CfgPIO\r
+//* \brief Configure PIO controllers to drive TWI signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TWI_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOA, // PIO controller base address\r
+ ((unsigned int) AT91C_PA3_TWD ) |\r
+ ((unsigned int) AT91C_PA4_TWCK ), // Peripheral A\r
+ 0); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US1_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for US1\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US1_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_US1));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US1_CfgPIO\r
+//* \brief Configure PIO controllers to drive US1 signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US1_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOA, // PIO controller base address\r
+ ((unsigned int) AT91C_PA21_RXD1 ) |\r
+ ((unsigned int) AT91C_PA27_DTR1 ) |\r
+ ((unsigned int) AT91C_PA26_DCD1 ) |\r
+ ((unsigned int) AT91C_PA22_TXD1 ) |\r
+ ((unsigned int) AT91C_PA24_RTS1 ) |\r
+ ((unsigned int) AT91C_PA23_SCK1 ) |\r
+ ((unsigned int) AT91C_PA28_DSR1 ) |\r
+ ((unsigned int) AT91C_PA29_RI1 ) |\r
+ ((unsigned int) AT91C_PA25_CTS1 ), // Peripheral A\r
+ 0); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US0_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for US0\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US0_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_US0));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US0_CfgPIO\r
+//* \brief Configure PIO controllers to drive US0 signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US0_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOA, // PIO controller base address\r
+ ((unsigned int) AT91C_PA5_RXD0 ) |\r
+ ((unsigned int) AT91C_PA6_TXD0 ) |\r
+ ((unsigned int) AT91C_PA7_RTS0 ) |\r
+ ((unsigned int) AT91C_PA8_CTS0 ), // Peripheral A\r
+ ((unsigned int) AT91C_PA2_SCK0 )); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for UDP\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_UDP_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_UDP));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AIC_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for AIC\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AIC_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_IRQ0) |\r
+ ((unsigned int) 1 << AT91C_ID_FIQ) |\r
+ ((unsigned int) 1 << AT91C_ID_IRQ1));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AIC_CfgPIO\r
+//* \brief Configure PIO controllers to drive AIC signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AIC_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOA, // PIO controller base address\r
+ ((unsigned int) AT91C_PA30_IRQ1 ), // Peripheral A\r
+ ((unsigned int) AT91C_PA20_IRQ0 ) |\r
+ ((unsigned int) AT91C_PA19_FIQ )); // Peripheral B\r
+}\r
+\r
+#endif // lib_AT91SAM7S64_H\r
--- /dev/null
+//* ----------------------------------------------------------------------------\r
+//* ATMEL Microcontroller Software Support - ROUSSET -\r
+//* ----------------------------------------------------------------------------\r
+//* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+//* ----------------------------------------------------------------------------\r
+//* File Name : lib_AT91SAM7X128.h\r
+//* Object : AT91SAM7X128 inlined functions\r
+//* Generated : AT91 SW Application Group 05/20/2005 (16:22:23)\r
+//*\r
+//* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003//\r
+//* CVS Reference : /lib_pmc_SAM7X.h/1.1/Tue Feb 1 08:32:10 2005//\r
+//* CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005//\r
+//* CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004//\r
+//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003//\r
+//* CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004//\r
+//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002//\r
+//* CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003//\r
+//* CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004//\r
+//* CVS Reference : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005//\r
+//* CVS Reference : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005//\r
+//* CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004//\r
+//* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003//\r
+//* CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004//\r
+//* CVS Reference : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005//\r
+//* CVS Reference : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005//\r
+//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//\r
+//* CVS Reference : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004//\r
+//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003//\r
+//* CVS Reference : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003//\r
+//* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//\r
+//* CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002//\r
+//* ----------------------------------------------------------------------------\r
+\r
+#ifndef lib_AT91SAM7X128_H\r
+#define lib_AT91SAM7X128_H\r
+\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR AIC\r
+ ***************************************************************************** */\r
+#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20]\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AIC_ConfigureIt\r
+//* \brief Interrupt Handler Initialization\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_AIC_ConfigureIt (\r
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers\r
+ unsigned int irq_id, // \arg interrupt number to initialize\r
+ unsigned int priority, // \arg priority to give to the interrupt\r
+ unsigned int src_type, // \arg activation and sense of activation\r
+ void (*newHandler) (void) ) // \arg address of the interrupt handler\r
+{\r
+ unsigned int oldHandler;\r
+ unsigned int mask ;\r
+\r
+ oldHandler = pAic->AIC_SVR[irq_id];\r
+\r
+ mask = 0x1 << irq_id ;\r
+ //* Disable the interrupt on the interrupt controller\r
+ pAic->AIC_IDCR = mask ;\r
+ //* Save the interrupt handler routine pointer and the interrupt priority\r
+ pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ;\r
+ //* Store the Source Mode Register\r
+ pAic->AIC_SMR[irq_id] = src_type | priority ;\r
+ //* Clear the interrupt on the interrupt controller\r
+ pAic->AIC_ICCR = mask ;\r
+\r
+ return oldHandler;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AIC_EnableIt\r
+//* \brief Enable corresponding IT number\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AIC_EnableIt (\r
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers\r
+ unsigned int irq_id ) // \arg interrupt number to initialize\r
+{\r
+ //* Enable the interrupt on the interrupt controller\r
+ pAic->AIC_IECR = 0x1 << irq_id ;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AIC_DisableIt\r
+//* \brief Disable corresponding IT number\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AIC_DisableIt (\r
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers\r
+ unsigned int irq_id ) // \arg interrupt number to initialize\r
+{\r
+ unsigned int mask = 0x1 << irq_id;\r
+ //* Disable the interrupt on the interrupt controller\r
+ pAic->AIC_IDCR = mask ;\r
+ //* Clear the interrupt on the Interrupt Controller ( if one is pending )\r
+ pAic->AIC_ICCR = mask ;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AIC_ClearIt\r
+//* \brief Clear corresponding IT number\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AIC_ClearIt (\r
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers\r
+ unsigned int irq_id) // \arg interrupt number to initialize\r
+{\r
+ //* Clear the interrupt on the Interrupt Controller ( if one is pending )\r
+ pAic->AIC_ICCR = (0x1 << irq_id);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AIC_AcknowledgeIt\r
+//* \brief Acknowledge corresponding IT number\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AIC_AcknowledgeIt (\r
+ AT91PS_AIC pAic) // \arg pointer to the AIC registers\r
+{\r
+ pAic->AIC_EOICR = pAic->AIC_EOICR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AIC_SetExceptionVector\r
+//* \brief Configure vector handler\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_AIC_SetExceptionVector (\r
+ unsigned int *pVector, // \arg pointer to the AIC registers\r
+ void (*Handler) () ) // \arg Interrupt Handler\r
+{\r
+ unsigned int oldVector = *pVector;\r
+\r
+ if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE)\r
+ *pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE;\r
+ else\r
+ *pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000;\r
+\r
+ return oldVector;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AIC_Trig\r
+//* \brief Trig an IT\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AIC_Trig (\r
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers\r
+ unsigned int irq_id) // \arg interrupt number\r
+{\r
+ pAic->AIC_ISCR = (0x1 << irq_id) ;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AIC_IsActive\r
+//* \brief Test if an IT is active\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_AIC_IsActive (\r
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers\r
+ unsigned int irq_id) // \arg Interrupt Number\r
+{\r
+ return (pAic->AIC_ISR & (0x1 << irq_id));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AIC_IsPending\r
+//* \brief Test if an IT is pending\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_AIC_IsPending (\r
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers\r
+ unsigned int irq_id) // \arg Interrupt Number\r
+{\r
+ return (pAic->AIC_IPR & (0x1 << irq_id));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AIC_Open\r
+//* \brief Set exception vectors and AIC registers to default values\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AIC_Open(\r
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers\r
+ void (*IrqHandler) (), // \arg Default IRQ vector exception\r
+ void (*FiqHandler) (), // \arg Default FIQ vector exception\r
+ void (*DefaultHandler) (), // \arg Default Handler set in ISR\r
+ void (*SpuriousHandler) (), // \arg Default Spurious Handler\r
+ unsigned int protectMode) // \arg Debug Control Register\r
+{\r
+ int i;\r
+\r
+ // Disable all interrupts and set IVR to the default handler\r
+ for (i = 0; i < 32; ++i) {\r
+ AT91F_AIC_DisableIt(pAic, i);\r
+ AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler);\r
+ }\r
+\r
+ // Set the IRQ exception vector\r
+ AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler);\r
+ // Set the Fast Interrupt exception vector\r
+ AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler);\r
+\r
+ pAic->AIC_SPU = (unsigned int) SpuriousHandler;\r
+ pAic->AIC_DCR = protectMode;\r
+}\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR PDC\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_SetNextRx\r
+//* \brief Set the next receive transfer descriptor\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PDC_SetNextRx (\r
+ AT91PS_PDC pPDC, // \arg pointer to a PDC controller\r
+ char *address, // \arg address to the next bloc to be received\r
+ unsigned int bytes) // \arg number of bytes to be received\r
+{\r
+ pPDC->PDC_RNPR = (unsigned int) address;\r
+ pPDC->PDC_RNCR = bytes;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_SetNextTx\r
+//* \brief Set the next transmit transfer descriptor\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PDC_SetNextTx (\r
+ AT91PS_PDC pPDC, // \arg pointer to a PDC controller\r
+ char *address, // \arg address to the next bloc to be transmitted\r
+ unsigned int bytes) // \arg number of bytes to be transmitted\r
+{\r
+ pPDC->PDC_TNPR = (unsigned int) address;\r
+ pPDC->PDC_TNCR = bytes;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_SetRx\r
+//* \brief Set the receive transfer descriptor\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PDC_SetRx (\r
+ AT91PS_PDC pPDC, // \arg pointer to a PDC controller\r
+ char *address, // \arg address to the next bloc to be received\r
+ unsigned int bytes) // \arg number of bytes to be received\r
+{\r
+ pPDC->PDC_RPR = (unsigned int) address;\r
+ pPDC->PDC_RCR = bytes;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_SetTx\r
+//* \brief Set the transmit transfer descriptor\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PDC_SetTx (\r
+ AT91PS_PDC pPDC, // \arg pointer to a PDC controller\r
+ char *address, // \arg address to the next bloc to be transmitted\r
+ unsigned int bytes) // \arg number of bytes to be transmitted\r
+{\r
+ pPDC->PDC_TPR = (unsigned int) address;\r
+ pPDC->PDC_TCR = bytes;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_EnableTx\r
+//* \brief Enable transmit\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PDC_EnableTx (\r
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller\r
+{\r
+ pPDC->PDC_PTCR = AT91C_PDC_TXTEN;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_EnableRx\r
+//* \brief Enable receive\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PDC_EnableRx (\r
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller\r
+{\r
+ pPDC->PDC_PTCR = AT91C_PDC_RXTEN;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_DisableTx\r
+//* \brief Disable transmit\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PDC_DisableTx (\r
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller\r
+{\r
+ pPDC->PDC_PTCR = AT91C_PDC_TXTDIS;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_DisableRx\r
+//* \brief Disable receive\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PDC_DisableRx (\r
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller\r
+{\r
+ pPDC->PDC_PTCR = AT91C_PDC_RXTDIS;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_IsTxEmpty\r
+//* \brief Test if the current transfer descriptor has been sent\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete\r
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller\r
+{\r
+ return !(pPDC->PDC_TCR);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_IsNextTxEmpty\r
+//* \brief Test if the next transfer descriptor has been moved to the current td\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete\r
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller\r
+{\r
+ return !(pPDC->PDC_TNCR);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_IsRxEmpty\r
+//* \brief Test if the current transfer descriptor has been filled\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete\r
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller\r
+{\r
+ return !(pPDC->PDC_RCR);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_IsNextRxEmpty\r
+//* \brief Test if the next transfer descriptor has been moved to the current td\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete\r
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller\r
+{\r
+ return !(pPDC->PDC_RNCR);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_Open\r
+//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PDC_Open (\r
+ AT91PS_PDC pPDC) // \arg pointer to a PDC controller\r
+{\r
+ //* Disable the RX and TX PDC transfer requests\r
+ AT91F_PDC_DisableRx(pPDC);\r
+ AT91F_PDC_DisableTx(pPDC);\r
+\r
+ //* Reset all Counter register Next buffer first\r
+ AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);\r
+ AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);\r
+ AT91F_PDC_SetTx(pPDC, (char *) 0, 0);\r
+ AT91F_PDC_SetRx(pPDC, (char *) 0, 0);\r
+\r
+ //* Enable the RX and TX PDC transfer requests\r
+ AT91F_PDC_EnableRx(pPDC);\r
+ AT91F_PDC_EnableTx(pPDC);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_Close\r
+//* \brief Close PDC: disable TX and RX reset transfer descriptors\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PDC_Close (\r
+ AT91PS_PDC pPDC) // \arg pointer to a PDC controller\r
+{\r
+ //* Disable the RX and TX PDC transfer requests\r
+ AT91F_PDC_DisableRx(pPDC);\r
+ AT91F_PDC_DisableTx(pPDC);\r
+\r
+ //* Reset all Counter register Next buffer first\r
+ AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);\r
+ AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);\r
+ AT91F_PDC_SetTx(pPDC, (char *) 0, 0);\r
+ AT91F_PDC_SetRx(pPDC, (char *) 0, 0);\r
+\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_SendFrame\r
+//* \brief Close PDC: disable TX and RX reset transfer descriptors\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PDC_SendFrame(\r
+ AT91PS_PDC pPDC,\r
+ char *pBuffer,\r
+ unsigned int szBuffer,\r
+ char *pNextBuffer,\r
+ unsigned int szNextBuffer )\r
+{\r
+ if (AT91F_PDC_IsTxEmpty(pPDC)) {\r
+ //* Buffer and next buffer can be initialized\r
+ AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer);\r
+ AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer);\r
+ return 2;\r
+ }\r
+ else if (AT91F_PDC_IsNextTxEmpty(pPDC)) {\r
+ //* Only one buffer can be initialized\r
+ AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer);\r
+ return 1;\r
+ }\r
+ else {\r
+ //* All buffer are in use...\r
+ return 0;\r
+ }\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_ReceiveFrame\r
+//* \brief Close PDC: disable TX and RX reset transfer descriptors\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PDC_ReceiveFrame (\r
+ AT91PS_PDC pPDC,\r
+ char *pBuffer,\r
+ unsigned int szBuffer,\r
+ char *pNextBuffer,\r
+ unsigned int szNextBuffer )\r
+{\r
+ if (AT91F_PDC_IsRxEmpty(pPDC)) {\r
+ //* Buffer and next buffer can be initialized\r
+ AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer);\r
+ AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer);\r
+ return 2;\r
+ }\r
+ else if (AT91F_PDC_IsNextRxEmpty(pPDC)) {\r
+ //* Only one buffer can be initialized\r
+ AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer);\r
+ return 1;\r
+ }\r
+ else {\r
+ //* All buffer are in use...\r
+ return 0;\r
+ }\r
+}\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR DBGU\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_DBGU_InterruptEnable\r
+//* \brief Enable DBGU Interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_DBGU_InterruptEnable(\r
+ AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller\r
+ unsigned int flag) // \arg dbgu interrupt to be enabled\r
+{\r
+ pDbgu->DBGU_IER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_DBGU_InterruptDisable\r
+//* \brief Disable DBGU Interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_DBGU_InterruptDisable(\r
+ AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller\r
+ unsigned int flag) // \arg dbgu interrupt to be disabled\r
+{\r
+ pDbgu->DBGU_IDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_DBGU_GetInterruptMaskStatus\r
+//* \brief Return DBGU Interrupt Mask Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status\r
+ AT91PS_DBGU pDbgu) // \arg pointer to a DBGU controller\r
+{\r
+ return pDbgu->DBGU_IMR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_DBGU_IsInterruptMasked\r
+//* \brief Test if DBGU Interrupt is Masked \r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_DBGU_IsInterruptMasked(\r
+ AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag);\r
+}\r
+\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR PIO\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_CfgPeriph\r
+//* \brief Enable pins to be drived by peripheral\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_CfgPeriph(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int periphAEnable, // \arg PERIPH A to enable\r
+ unsigned int periphBEnable) // \arg PERIPH B to enable\r
+\r
+{\r
+ pPio->PIO_ASR = periphAEnable;\r
+ pPio->PIO_BSR = periphBEnable;\r
+ pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_CfgOutput\r
+//* \brief Enable PIO in output mode\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_CfgOutput(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int pioEnable) // \arg PIO to be enabled\r
+{\r
+ pPio->PIO_PER = pioEnable; // Set in PIO mode\r
+ pPio->PIO_OER = pioEnable; // Configure in Output\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_CfgInput\r
+//* \brief Enable PIO in input mode\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_CfgInput(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int inputEnable) // \arg PIO to be enabled\r
+{\r
+ // Disable output\r
+ pPio->PIO_ODR = inputEnable;\r
+ pPio->PIO_PER = inputEnable;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_CfgOpendrain\r
+//* \brief Configure PIO in open drain\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_CfgOpendrain(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int multiDrvEnable) // \arg pio to be configured in open drain\r
+{\r
+ // Configure the multi-drive option\r
+ pPio->PIO_MDDR = ~multiDrvEnable;\r
+ pPio->PIO_MDER = multiDrvEnable;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_CfgPullup\r
+//* \brief Enable pullup on PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_CfgPullup(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int pullupEnable) // \arg enable pullup on PIO\r
+{\r
+ // Connect or not Pullup\r
+ pPio->PIO_PPUDR = ~pullupEnable;\r
+ pPio->PIO_PPUER = pullupEnable;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_CfgDirectDrive\r
+//* \brief Enable direct drive on PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_CfgDirectDrive(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int directDrive) // \arg PIO to be configured with direct drive\r
+\r
+{\r
+ // Configure the Direct Drive\r
+ pPio->PIO_OWDR = ~directDrive;\r
+ pPio->PIO_OWER = directDrive;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_CfgInputFilter\r
+//* \brief Enable input filter on input PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_CfgInputFilter(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int inputFilter) // \arg PIO to be configured with input filter\r
+\r
+{\r
+ // Configure the Direct Drive\r
+ pPio->PIO_IFDR = ~inputFilter;\r
+ pPio->PIO_IFER = inputFilter;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_GetInput\r
+//* \brief Return PIO input value\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PIO_GetInput( // \return PIO input\r
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller\r
+{\r
+ return pPio->PIO_PDSR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_IsInputSet\r
+//* \brief Test if PIO is input flag is active\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PIO_IsInputSet(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_PIO_GetInput(pPio) & flag);\r
+}\r
+\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_SetOutput\r
+//* \brief Set to 1 output PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_SetOutput(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg output to be set\r
+{\r
+ pPio->PIO_SODR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_ClearOutput\r
+//* \brief Set to 0 output PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_ClearOutput(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg output to be cleared\r
+{\r
+ pPio->PIO_CODR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_ForceOutput\r
+//* \brief Force output when Direct drive option is enabled\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_ForceOutput(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg output to be forced\r
+{\r
+ pPio->PIO_ODSR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_Enable\r
+//* \brief Enable PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_Enable(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg pio to be enabled \r
+{\r
+ pPio->PIO_PER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_Disable\r
+//* \brief Disable PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_Disable(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg pio to be disabled \r
+{\r
+ pPio->PIO_PDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_GetStatus\r
+//* \brief Return PIO Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status\r
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller\r
+{\r
+ return pPio->PIO_PSR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_IsSet\r
+//* \brief Test if PIO is Set\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PIO_IsSet(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_PIO_GetStatus(pPio) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_OutputEnable\r
+//* \brief Output Enable PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_OutputEnable(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg pio output to be enabled\r
+{\r
+ pPio->PIO_OER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_OutputDisable\r
+//* \brief Output Enable PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_OutputDisable(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg pio output to be disabled\r
+{\r
+ pPio->PIO_ODR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_GetOutputStatus\r
+//* \brief Return PIO Output Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status\r
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller\r
+{\r
+ return pPio->PIO_OSR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_IsOuputSet\r
+//* \brief Test if PIO Output is Set\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PIO_IsOutputSet(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_PIO_GetOutputStatus(pPio) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_InputFilterEnable\r
+//* \brief Input Filter Enable PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_InputFilterEnable(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg pio input filter to be enabled\r
+{\r
+ pPio->PIO_IFER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_InputFilterDisable\r
+//* \brief Input Filter Disable PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_InputFilterDisable(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg pio input filter to be disabled\r
+{\r
+ pPio->PIO_IFDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_GetInputFilterStatus\r
+//* \brief Return PIO Input Filter Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status\r
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller\r
+{\r
+ return pPio->PIO_IFSR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_IsInputFilterSet\r
+//* \brief Test if PIO Input filter is Set\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PIO_IsInputFilterSet(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_PIO_GetInputFilterStatus(pPio) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_GetOutputDataStatus\r
+//* \brief Return PIO Output Data Status \r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status \r
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller\r
+{\r
+ return pPio->PIO_ODSR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_InterruptEnable\r
+//* \brief Enable PIO Interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_InterruptEnable(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg pio interrupt to be enabled\r
+{\r
+ pPio->PIO_IER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_InterruptDisable\r
+//* \brief Disable PIO Interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_InterruptDisable(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg pio interrupt to be disabled\r
+{\r
+ pPio->PIO_IDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_GetInterruptMaskStatus\r
+//* \brief Return PIO Interrupt Mask Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status\r
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller\r
+{\r
+ return pPio->PIO_IMR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_GetInterruptStatus\r
+//* \brief Return PIO Interrupt Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status\r
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller\r
+{\r
+ return pPio->PIO_ISR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_IsInterruptMasked\r
+//* \brief Test if PIO Interrupt is Masked \r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PIO_IsInterruptMasked(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_IsInterruptSet\r
+//* \brief Test if PIO Interrupt is Set\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PIO_IsInterruptSet(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_PIO_GetInterruptStatus(pPio) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_MultiDriverEnable\r
+//* \brief Multi Driver Enable PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_MultiDriverEnable(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg pio to be enabled\r
+{\r
+ pPio->PIO_MDER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_MultiDriverDisable\r
+//* \brief Multi Driver Disable PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_MultiDriverDisable(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg pio to be disabled\r
+{\r
+ pPio->PIO_MDDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_GetMultiDriverStatus\r
+//* \brief Return PIO Multi Driver Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status\r
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller\r
+{\r
+ return pPio->PIO_MDSR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_IsMultiDriverSet\r
+//* \brief Test if PIO MultiDriver is Set\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PIO_IsMultiDriverSet(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_A_RegisterSelection\r
+//* \brief PIO A Register Selection \r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_A_RegisterSelection(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg pio A register selection\r
+{\r
+ pPio->PIO_ASR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_B_RegisterSelection\r
+//* \brief PIO B Register Selection \r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_B_RegisterSelection(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg pio B register selection \r
+{\r
+ pPio->PIO_BSR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_Get_AB_RegisterStatus\r
+//* \brief Return PIO Interrupt Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status\r
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller\r
+{\r
+ return pPio->PIO_ABSR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_IsAB_RegisterSet\r
+//* \brief Test if PIO AB Register is Set\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PIO_IsAB_RegisterSet(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_OutputWriteEnable\r
+//* \brief Output Write Enable PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_OutputWriteEnable(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg pio output write to be enabled\r
+{\r
+ pPio->PIO_OWER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_OutputWriteDisable\r
+//* \brief Output Write Disable PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_OutputWriteDisable(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg pio output write to be disabled\r
+{\r
+ pPio->PIO_OWDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_GetOutputWriteStatus\r
+//* \brief Return PIO Output Write Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status\r
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller\r
+{\r
+ return pPio->PIO_OWSR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_IsOutputWriteSet\r
+//* \brief Test if PIO OutputWrite is Set\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PIO_IsOutputWriteSet(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_GetCfgPullup\r
+//* \brief Return PIO Configuration Pullup\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup \r
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller\r
+{\r
+ return pPio->PIO_PPUSR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_IsOutputDataStatusSet\r
+//* \brief Test if PIO Output Data Status is Set \r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PIO_IsOutputDataStatusSet(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_PIO_GetOutputDataStatus(pPio) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_IsCfgPullupStatusSet\r
+//* \brief Test if PIO Configuration Pullup Status is Set\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PIO_IsCfgPullupStatusSet(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (~AT91F_PIO_GetCfgPullup(pPio) & flag);\r
+}\r
+\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR PMC\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_CfgSysClkEnableReg\r
+//* \brief Configure the System Clock Enable Register of the PMC controller\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PMC_CfgSysClkEnableReg (\r
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller\r
+ unsigned int mode)\r
+{\r
+ //* Write to the SCER register\r
+ pPMC->PMC_SCER = mode;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_CfgSysClkDisableReg\r
+//* \brief Configure the System Clock Disable Register of the PMC controller\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PMC_CfgSysClkDisableReg (\r
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller\r
+ unsigned int mode)\r
+{\r
+ //* Write to the SCDR register\r
+ pPMC->PMC_SCDR = mode;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_GetSysClkStatusReg\r
+//* \brief Return the System Clock Status Register of the PMC controller\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PMC_GetSysClkStatusReg (\r
+ AT91PS_PMC pPMC // pointer to a CAN controller\r
+ )\r
+{\r
+ return pPMC->PMC_SCSR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_EnablePeriphClock\r
+//* \brief Enable peripheral clock\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PMC_EnablePeriphClock (\r
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller\r
+ unsigned int periphIds) // \arg IDs of peripherals to enable\r
+{\r
+ pPMC->PMC_PCER = periphIds;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_DisablePeriphClock\r
+//* \brief Disable peripheral clock\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PMC_DisablePeriphClock (\r
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller\r
+ unsigned int periphIds) // \arg IDs of peripherals to enable\r
+{\r
+ pPMC->PMC_PCDR = periphIds;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_GetPeriphClock\r
+//* \brief Get peripheral clock status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PMC_GetPeriphClock (\r
+ AT91PS_PMC pPMC) // \arg pointer to PMC controller\r
+{\r
+ return pPMC->PMC_PCSR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CKGR_CfgMainOscillatorReg\r
+//* \brief Cfg the main oscillator\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CKGR_CfgMainOscillatorReg (\r
+ AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller\r
+ unsigned int mode)\r
+{\r
+ pCKGR->CKGR_MOR = mode;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CKGR_GetMainOscillatorReg\r
+//* \brief Cfg the main oscillator\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CKGR_GetMainOscillatorReg (\r
+ AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller\r
+{\r
+ return pCKGR->CKGR_MOR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CKGR_EnableMainOscillator\r
+//* \brief Enable the main oscillator\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CKGR_EnableMainOscillator(\r
+ AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller\r
+{\r
+ pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CKGR_DisableMainOscillator\r
+//* \brief Disable the main oscillator\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CKGR_DisableMainOscillator (\r
+ AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller\r
+{\r
+ pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CKGR_CfgMainOscStartUpTime\r
+//* \brief Cfg MOR Register according to the main osc startup time\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CKGR_CfgMainOscStartUpTime (\r
+ AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller\r
+ unsigned int startup_time, // \arg main osc startup time in microsecond (us)\r
+ unsigned int slowClock) // \arg slowClock in Hz\r
+{\r
+ pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT;\r
+ pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CKGR_GetMainClockFreqReg\r
+//* \brief Cfg the main oscillator\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CKGR_GetMainClockFreqReg (\r
+ AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller\r
+{\r
+ return pCKGR->CKGR_MCFR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CKGR_GetMainClock\r
+//* \brief Return Main clock in Hz\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CKGR_GetMainClock (\r
+ AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller\r
+ unsigned int slowClock) // \arg slowClock in Hz\r
+{\r
+ return ((pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF) * slowClock) >> 4;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_CfgMCKReg\r
+//* \brief Cfg Master Clock Register\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PMC_CfgMCKReg (\r
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller\r
+ unsigned int mode)\r
+{\r
+ pPMC->PMC_MCKR = mode;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_GetMCKReg\r
+//* \brief Return Master Clock Register\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PMC_GetMCKReg(\r
+ AT91PS_PMC pPMC) // \arg pointer to PMC controller\r
+{\r
+ return pPMC->PMC_MCKR;\r
+}\r
+\r
+//*------------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_GetMasterClock\r
+//* \brief Return master clock in Hz which correponds to processor clock for ARM7\r
+//*------------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PMC_GetMasterClock (\r
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller\r
+ AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller\r
+ unsigned int slowClock) // \arg slowClock in Hz\r
+{\r
+ unsigned int reg = pPMC->PMC_MCKR;\r
+ unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2));\r
+ unsigned int pllDivider, pllMultiplier;\r
+\r
+ switch (reg & AT91C_PMC_CSS) {\r
+ case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected\r
+ return slowClock / prescaler;\r
+ case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected\r
+ return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler;\r
+ case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected\r
+ reg = pCKGR->CKGR_PLLR;\r
+ pllDivider = (reg & AT91C_CKGR_DIV);\r
+ pllMultiplier = ((reg & AT91C_CKGR_MUL) >> 16) + 1;\r
+ return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler;\r
+ }\r
+ return 0;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_EnablePCK\r
+//* \brief Enable peripheral clock\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PMC_EnablePCK (\r
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller\r
+ unsigned int pck, // \arg Peripheral clock identifier 0 .. 7\r
+ unsigned int mode)\r
+{\r
+ pPMC->PMC_PCKR[pck] = mode;\r
+ pPMC->PMC_SCER = (1 << pck) << 8;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_DisablePCK\r
+//* \brief Enable peripheral clock\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PMC_DisablePCK (\r
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller\r
+ unsigned int pck) // \arg Peripheral clock identifier 0 .. 7\r
+{\r
+ pPMC->PMC_SCDR = (1 << pck) << 8;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_EnableIt\r
+//* \brief Enable PMC interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PMC_EnableIt (\r
+ AT91PS_PMC pPMC, // pointer to a PMC controller\r
+ unsigned int flag) // IT to be enabled\r
+{\r
+ //* Write to the IER register\r
+ pPMC->PMC_IER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_DisableIt\r
+//* \brief Disable PMC interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PMC_DisableIt (\r
+ AT91PS_PMC pPMC, // pointer to a PMC controller\r
+ unsigned int flag) // IT to be disabled\r
+{\r
+ //* Write to the IDR register\r
+ pPMC->PMC_IDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_GetStatus\r
+//* \brief Return PMC Interrupt Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status\r
+ AT91PS_PMC pPMC) // pointer to a PMC controller\r
+{\r
+ return pPMC->PMC_SR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_GetInterruptMaskStatus\r
+//* \brief Return PMC Interrupt Mask Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status\r
+ AT91PS_PMC pPMC) // pointer to a PMC controller\r
+{\r
+ return pPMC->PMC_IMR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_IsInterruptMasked\r
+//* \brief Test if PMC Interrupt is Masked\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PMC_IsInterruptMasked(\r
+ AT91PS_PMC pPMC, // \arg pointer to a PMC controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_IsStatusSet\r
+//* \brief Test if PMC Status is Set\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PMC_IsStatusSet(\r
+ AT91PS_PMC pPMC, // \arg pointer to a PMC controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_PMC_GetStatus(pPMC) & flag);\r
+}/* *****************************************************************************\r
+ SOFTWARE API FOR RSTC\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_RSTSoftReset\r
+//* \brief Start Software Reset\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_RSTSoftReset(\r
+ AT91PS_RSTC pRSTC,\r
+ unsigned int reset)\r
+{\r
+ pRSTC->RSTC_RCR = (0xA5000000 | reset);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_RSTSetMode\r
+//* \brief Set Reset Mode\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_RSTSetMode(\r
+ AT91PS_RSTC pRSTC,\r
+ unsigned int mode)\r
+{\r
+ pRSTC->RSTC_RMR = (0xA5000000 | mode);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_RSTGetMode\r
+//* \brief Get Reset Mode\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_RSTGetMode(\r
+ AT91PS_RSTC pRSTC)\r
+{\r
+ return (pRSTC->RSTC_RMR);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_RSTGetStatus\r
+//* \brief Get Reset Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_RSTGetStatus(\r
+ AT91PS_RSTC pRSTC)\r
+{\r
+ return (pRSTC->RSTC_RSR);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_RSTIsSoftRstActive\r
+//* \brief Return !=0 if software reset is still not completed\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_RSTIsSoftRstActive(\r
+ AT91PS_RSTC pRSTC)\r
+{\r
+ return ((pRSTC->RSTC_RSR) & AT91C_RSTC_SRCMP);\r
+}\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR RTTC\r
+ ***************************************************************************** */\r
+//*--------------------------------------------------------------------------------------\r
+//* \fn AT91F_SetRTT_TimeBase()\r
+//* \brief Set the RTT prescaler according to the TimeBase in ms\r
+//*--------------------------------------------------------------------------------------\r
+__inline unsigned int AT91F_RTTSetTimeBase(\r
+ AT91PS_RTTC pRTTC, \r
+ unsigned int ms)\r
+{\r
+ if (ms > 2000)\r
+ return 1; // AT91C_TIME_OUT_OF_RANGE\r
+ pRTTC->RTTC_RTMR &= ~0xFFFF; \r
+ pRTTC->RTTC_RTMR |= (((ms << 15) /1000) & 0xFFFF); \r
+ return 0;\r
+}\r
+\r
+//*--------------------------------------------------------------------------------------\r
+//* \fn AT91F_RTTSetPrescaler()\r
+//* \brief Set the new prescaler value\r
+//*--------------------------------------------------------------------------------------\r
+__inline unsigned int AT91F_RTTSetPrescaler(\r
+ AT91PS_RTTC pRTTC, \r
+ unsigned int rtpres)\r
+{\r
+ pRTTC->RTTC_RTMR &= ~0xFFFF; \r
+ pRTTC->RTTC_RTMR |= (rtpres & 0xFFFF); \r
+ return (pRTTC->RTTC_RTMR);\r
+}\r
+\r
+//*--------------------------------------------------------------------------------------\r
+//* \fn AT91F_RTTRestart()\r
+//* \brief Restart the RTT prescaler\r
+//*--------------------------------------------------------------------------------------\r
+__inline void AT91F_RTTRestart(\r
+ AT91PS_RTTC pRTTC)\r
+{\r
+ pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST; \r
+}\r
+\r
+\r
+//*--------------------------------------------------------------------------------------\r
+//* \fn AT91F_RTT_SetAlarmINT()\r
+//* \brief Enable RTT Alarm Interrupt\r
+//*--------------------------------------------------------------------------------------\r
+__inline void AT91F_RTTSetAlarmINT(\r
+ AT91PS_RTTC pRTTC)\r
+{\r
+ pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN;\r
+}\r
+\r
+//*--------------------------------------------------------------------------------------\r
+//* \fn AT91F_RTT_ClearAlarmINT()\r
+//* \brief Disable RTT Alarm Interrupt\r
+//*--------------------------------------------------------------------------------------\r
+__inline void AT91F_RTTClearAlarmINT(\r
+ AT91PS_RTTC pRTTC)\r
+{\r
+ pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN;\r
+}\r
+\r
+//*--------------------------------------------------------------------------------------\r
+//* \fn AT91F_RTT_SetRttIncINT()\r
+//* \brief Enable RTT INC Interrupt\r
+//*--------------------------------------------------------------------------------------\r
+__inline void AT91F_RTTSetRttIncINT(\r
+ AT91PS_RTTC pRTTC)\r
+{\r
+ pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN;\r
+}\r
+\r
+//*--------------------------------------------------------------------------------------\r
+//* \fn AT91F_RTT_ClearRttIncINT()\r
+//* \brief Disable RTT INC Interrupt\r
+//*--------------------------------------------------------------------------------------\r
+__inline void AT91F_RTTClearRttIncINT(\r
+ AT91PS_RTTC pRTTC)\r
+{\r
+ pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN;\r
+}\r
+\r
+//*--------------------------------------------------------------------------------------\r
+//* \fn AT91F_RTT_SetAlarmValue()\r
+//* \brief Set RTT Alarm Value\r
+//*--------------------------------------------------------------------------------------\r
+__inline void AT91F_RTTSetAlarmValue(\r
+ AT91PS_RTTC pRTTC, unsigned int alarm)\r
+{\r
+ pRTTC->RTTC_RTAR = alarm;\r
+}\r
+\r
+//*--------------------------------------------------------------------------------------\r
+//* \fn AT91F_RTT_GetAlarmValue()\r
+//* \brief Get RTT Alarm Value\r
+//*--------------------------------------------------------------------------------------\r
+__inline unsigned int AT91F_RTTGetAlarmValue(\r
+ AT91PS_RTTC pRTTC)\r
+{\r
+ return(pRTTC->RTTC_RTAR);\r
+}\r
+\r
+//*--------------------------------------------------------------------------------------\r
+//* \fn AT91F_RTTGetStatus()\r
+//* \brief Read the RTT status\r
+//*--------------------------------------------------------------------------------------\r
+__inline unsigned int AT91F_RTTGetStatus(\r
+ AT91PS_RTTC pRTTC)\r
+{\r
+ return(pRTTC->RTTC_RTSR);\r
+}\r
+\r
+//*--------------------------------------------------------------------------------------\r
+//* \fn AT91F_RTT_ReadValue()\r
+//* \brief Read the RTT value\r
+//*--------------------------------------------------------------------------------------\r
+__inline unsigned int AT91F_RTTReadValue(\r
+ AT91PS_RTTC pRTTC)\r
+{\r
+ register volatile unsigned int val1,val2;\r
+ do\r
+ {\r
+ val1 = pRTTC->RTTC_RTVR;\r
+ val2 = pRTTC->RTTC_RTVR;\r
+ } \r
+ while(val1 != val2);\r
+ return(val1);\r
+}\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR PITC\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PITInit\r
+//* \brief System timer init : period in µsecond, system clock freq in MHz\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PITInit(\r
+ AT91PS_PITC pPITC,\r
+ unsigned int period,\r
+ unsigned int pit_frequency)\r
+{\r
+ pPITC->PITC_PIMR = period? (period * pit_frequency + 8) >> 4 : 0; // +8 to avoid %10 and /10\r
+ pPITC->PITC_PIMR |= AT91C_PITC_PITEN; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PITSetPIV\r
+//* \brief Set the PIT Periodic Interval Value \r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PITSetPIV(\r
+ AT91PS_PITC pPITC,\r
+ unsigned int piv)\r
+{\r
+ pPITC->PITC_PIMR = piv | (pPITC->PITC_PIMR & (AT91C_PITC_PITEN | AT91C_PITC_PITIEN));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PITEnableInt\r
+//* \brief Enable PIT periodic interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PITEnableInt(\r
+ AT91PS_PITC pPITC)\r
+{\r
+ pPITC->PITC_PIMR |= AT91C_PITC_PITIEN; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PITDisableInt\r
+//* \brief Disable PIT periodic interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PITDisableInt(\r
+ AT91PS_PITC pPITC)\r
+{\r
+ pPITC->PITC_PIMR &= ~AT91C_PITC_PITIEN; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PITGetMode\r
+//* \brief Read PIT mode register\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PITGetMode(\r
+ AT91PS_PITC pPITC)\r
+{\r
+ return(pPITC->PITC_PIMR);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PITGetStatus\r
+//* \brief Read PIT status register\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PITGetStatus(\r
+ AT91PS_PITC pPITC)\r
+{\r
+ return(pPITC->PITC_PISR);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PITGetPIIR\r
+//* \brief Read PIT CPIV and PICNT without ressetting the counters\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PITGetPIIR(\r
+ AT91PS_PITC pPITC)\r
+{\r
+ return(pPITC->PITC_PIIR);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PITGetPIVR\r
+//* \brief Read System timer CPIV and PICNT without ressetting the counters\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PITGetPIVR(\r
+ AT91PS_PITC pPITC)\r
+{\r
+ return(pPITC->PITC_PIVR);\r
+}\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR WDTC\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_WDTSetMode\r
+//* \brief Set Watchdog Mode Register\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_WDTSetMode(\r
+ AT91PS_WDTC pWDTC,\r
+ unsigned int Mode)\r
+{\r
+ pWDTC->WDTC_WDMR = Mode;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_WDTRestart\r
+//* \brief Restart Watchdog\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_WDTRestart(\r
+ AT91PS_WDTC pWDTC)\r
+{\r
+ pWDTC->WDTC_WDCR = 0xA5000001;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_WDTSGettatus\r
+//* \brief Get Watchdog Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_WDTSGettatus(\r
+ AT91PS_WDTC pWDTC)\r
+{\r
+ return(pWDTC->WDTC_WDSR & 0x3);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_WDTGetPeriod\r
+//* \brief Translate ms into Watchdog Compatible value\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_WDTGetPeriod(unsigned int ms)\r
+{\r
+ if ((ms < 4) || (ms > 16000))\r
+ return 0;\r
+ return((ms << 8) / 1000);\r
+}\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR VREG\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_VREG_Enable_LowPowerMode\r
+//* \brief Enable VREG Low Power Mode\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_VREG_Enable_LowPowerMode(\r
+ AT91PS_VREG pVREG)\r
+{\r
+ pVREG->VREG_MR |= AT91C_VREG_PSTDBY; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_VREG_Disable_LowPowerMode\r
+//* \brief Disable VREG Low Power Mode\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_VREG_Disable_LowPowerMode(\r
+ AT91PS_VREG pVREG)\r
+{\r
+ pVREG->VREG_MR &= ~AT91C_VREG_PSTDBY; \r
+}/* *****************************************************************************\r
+ SOFTWARE API FOR MC\r
+ ***************************************************************************** */\r
+\r
+#define AT91C_MC_CORRECT_KEY ((unsigned int) 0x5A << 24) // (MC) Correct Protect Key\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_MC_Remap\r
+//* \brief Make Remap\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_MC_Remap (void) // \r
+{\r
+ AT91PS_MC pMC = (AT91PS_MC) AT91C_BASE_MC;\r
+ \r
+ pMC->MC_RCR = AT91C_MC_RCB;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_MC_EFC_CfgModeReg\r
+//* \brief Configure the EFC Mode Register of the MC controller\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_MC_EFC_CfgModeReg (\r
+ AT91PS_MC pMC, // pointer to a MC controller\r
+ unsigned int mode) // mode register \r
+{\r
+ // Write to the FMR register\r
+ pMC->MC_FMR = mode;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_MC_EFC_GetModeReg\r
+//* \brief Return MC EFC Mode Regsiter\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_MC_EFC_GetModeReg(\r
+ AT91PS_MC pMC) // pointer to a MC controller\r
+{\r
+ return pMC->MC_FMR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_MC_EFC_ComputeFMCN\r
+//* \brief Return MC EFC Mode Regsiter\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_MC_EFC_ComputeFMCN(\r
+ int master_clock) // master clock in Hz\r
+{\r
+ return (master_clock/1000000 +2);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_MC_EFC_PerformCmd\r
+//* \brief Perform EFC Command\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_MC_EFC_PerformCmd (\r
+ AT91PS_MC pMC, // pointer to a MC controller\r
+ unsigned int transfer_cmd)\r
+{\r
+ pMC->MC_FCR = transfer_cmd; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_MC_EFC_GetStatus\r
+//* \brief Return MC EFC Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_MC_EFC_GetStatus(\r
+ AT91PS_MC pMC) // pointer to a MC controller\r
+{\r
+ return pMC->MC_FSR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_MC_EFC_IsInterruptMasked\r
+//* \brief Test if EFC MC Interrupt is Masked \r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_MC_EFC_IsInterruptMasked(\r
+ AT91PS_MC pMC, // \arg pointer to a MC controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_MC_EFC_GetModeReg(pMC) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_MC_EFC_IsInterruptSet\r
+//* \brief Test if EFC MC Interrupt is Set\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_MC_EFC_IsInterruptSet(\r
+ AT91PS_MC pMC, // \arg pointer to a MC controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_MC_EFC_GetStatus(pMC) & flag);\r
+}\r
+\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR SPI\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_Open\r
+//* \brief Open a SPI Port\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_SPI_Open (\r
+ const unsigned int null) // \arg\r
+{\r
+ /* NOT DEFINED AT THIS MOMENT */\r
+ return ( 0 );\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_CfgCs\r
+//* \brief Configure SPI chip select register\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SPI_CfgCs (\r
+ AT91PS_SPI pSPI, // pointer to a SPI controller\r
+ int cs, // SPI cs number (0 to 3)\r
+ int val) // chip select register\r
+{\r
+ //* Write to the CSR register\r
+ *(pSPI->SPI_CSR + cs) = val;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_EnableIt\r
+//* \brief Enable SPI interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SPI_EnableIt (\r
+ AT91PS_SPI pSPI, // pointer to a SPI controller\r
+ unsigned int flag) // IT to be enabled\r
+{\r
+ //* Write to the IER register\r
+ pSPI->SPI_IER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_DisableIt\r
+//* \brief Disable SPI interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SPI_DisableIt (\r
+ AT91PS_SPI pSPI, // pointer to a SPI controller\r
+ unsigned int flag) // IT to be disabled\r
+{\r
+ //* Write to the IDR register\r
+ pSPI->SPI_IDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_Reset\r
+//* \brief Reset the SPI controller\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SPI_Reset (\r
+ AT91PS_SPI pSPI // pointer to a SPI controller\r
+ )\r
+{\r
+ //* Write to the CR register\r
+ pSPI->SPI_CR = AT91C_SPI_SWRST;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_Enable\r
+//* \brief Enable the SPI controller\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SPI_Enable (\r
+ AT91PS_SPI pSPI // pointer to a SPI controller\r
+ )\r
+{\r
+ //* Write to the CR register\r
+ pSPI->SPI_CR = AT91C_SPI_SPIEN;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_Disable\r
+//* \brief Disable the SPI controller\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SPI_Disable (\r
+ AT91PS_SPI pSPI // pointer to a SPI controller\r
+ )\r
+{\r
+ //* Write to the CR register\r
+ pSPI->SPI_CR = AT91C_SPI_SPIDIS;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_CfgMode\r
+//* \brief Enable the SPI controller\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SPI_CfgMode (\r
+ AT91PS_SPI pSPI, // pointer to a SPI controller\r
+ int mode) // mode register \r
+{\r
+ //* Write to the MR register\r
+ pSPI->SPI_MR = mode;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_CfgPCS\r
+//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SPI_CfgPCS (\r
+ AT91PS_SPI pSPI, // pointer to a SPI controller\r
+ char PCS_Device) // PCS of the Device\r
+{ \r
+ //* Write to the MR register\r
+ pSPI->SPI_MR &= 0xFFF0FFFF;\r
+ pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS );\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_ReceiveFrame\r
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_SPI_ReceiveFrame (\r
+ AT91PS_SPI pSPI,\r
+ char *pBuffer,\r
+ unsigned int szBuffer,\r
+ char *pNextBuffer,\r
+ unsigned int szNextBuffer )\r
+{\r
+ return AT91F_PDC_ReceiveFrame(\r
+ (AT91PS_PDC) &(pSPI->SPI_RPR),\r
+ pBuffer,\r
+ szBuffer,\r
+ pNextBuffer,\r
+ szNextBuffer);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_SendFrame\r
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_SPI_SendFrame(\r
+ AT91PS_SPI pSPI,\r
+ char *pBuffer,\r
+ unsigned int szBuffer,\r
+ char *pNextBuffer,\r
+ unsigned int szNextBuffer )\r
+{\r
+ return AT91F_PDC_SendFrame(\r
+ (AT91PS_PDC) &(pSPI->SPI_RPR),\r
+ pBuffer,\r
+ szBuffer,\r
+ pNextBuffer,\r
+ szNextBuffer);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_Close\r
+//* \brief Close SPI: disable IT disable transfert, close PDC\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SPI_Close (\r
+ AT91PS_SPI pSPI) // \arg pointer to a SPI controller\r
+{\r
+ //* Reset all the Chip Select register\r
+ pSPI->SPI_CSR[0] = 0 ;\r
+ pSPI->SPI_CSR[1] = 0 ;\r
+ pSPI->SPI_CSR[2] = 0 ;\r
+ pSPI->SPI_CSR[3] = 0 ;\r
+\r
+ //* Reset the SPI mode\r
+ pSPI->SPI_MR = 0 ;\r
+\r
+ //* Disable all interrupts\r
+ pSPI->SPI_IDR = 0xFFFFFFFF ;\r
+\r
+ //* Abort the Peripheral Data Transfers\r
+ AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR));\r
+\r
+ //* Disable receiver and transmitter and stop any activity immediately\r
+ pSPI->SPI_CR = AT91C_SPI_SPIDIS;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_PutChar\r
+//* \brief Send a character,does not check if ready to send\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SPI_PutChar (\r
+ AT91PS_SPI pSPI,\r
+ unsigned int character,\r
+ unsigned int cs_number )\r
+{\r
+ unsigned int value_for_cs;\r
+ value_for_cs = (~(1 << cs_number)) & 0xF; //Place a zero among a 4 ONEs number\r
+ pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_GetChar\r
+//* \brief Receive a character,does not check if a character is available\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_SPI_GetChar (\r
+ const AT91PS_SPI pSPI)\r
+{\r
+ return((pSPI->SPI_RDR) & 0xFFFF);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_GetInterruptMaskStatus\r
+//* \brief Return SPI Interrupt Mask Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status\r
+ AT91PS_SPI pSpi) // \arg pointer to a SPI controller\r
+{\r
+ return pSpi->SPI_IMR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_IsInterruptMasked\r
+//* \brief Test if SPI Interrupt is Masked \r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_SPI_IsInterruptMasked(\r
+ AT91PS_SPI pSpi, // \arg pointer to a SPI controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag);\r
+}\r
+\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR USART\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_Baudrate\r
+//* \brief Calculate the baudrate\r
+//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity\r
+#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \\r
+ AT91C_US_NBSTOP_1_BIT + \\r
+ AT91C_US_PAR_NONE + \\r
+ AT91C_US_CHRL_8_BITS + \\r
+ AT91C_US_CLKS_CLOCK )\r
+\r
+//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity\r
+#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \\r
+ AT91C_US_NBSTOP_1_BIT + \\r
+ AT91C_US_PAR_NONE + \\r
+ AT91C_US_CHRL_8_BITS + \\r
+ AT91C_US_CLKS_EXT )\r
+\r
+//* Standard Synchronous Mode : 8 bits , 1 stop , no parity\r
+#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \\r
+ AT91C_US_USMODE_NORMAL + \\r
+ AT91C_US_NBSTOP_1_BIT + \\r
+ AT91C_US_PAR_NONE + \\r
+ AT91C_US_CHRL_8_BITS + \\r
+ AT91C_US_CLKS_CLOCK )\r
+\r
+//* SCK used Label\r
+#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT)\r
+\r
+//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity\r
+#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \\r
+ AT91C_US_CLKS_CLOCK +\\r
+ AT91C_US_NBSTOP_1_BIT + \\r
+ AT91C_US_PAR_EVEN + \\r
+ AT91C_US_CHRL_8_BITS + \\r
+ AT91C_US_CKLO +\\r
+ AT91C_US_OVER)\r
+\r
+//* Standard IRDA mode\r
+#define AT91C_US_ASYNC_IRDA_MODE ( AT91C_US_USMODE_IRDA + \\r
+ AT91C_US_NBSTOP_1_BIT + \\r
+ AT91C_US_PAR_NONE + \\r
+ AT91C_US_CHRL_8_BITS + \\r
+ AT91C_US_CLKS_CLOCK )\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_Baudrate\r
+//* \brief Caluculate baud_value according to the main clock and the baud rate\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_US_Baudrate (\r
+ const unsigned int main_clock, // \arg peripheral clock\r
+ const unsigned int baud_rate) // \arg UART baudrate\r
+{\r
+ unsigned int baud_value = ((main_clock*10)/(baud_rate * 16));\r
+ if ((baud_value % 10) >= 5)\r
+ baud_value = (baud_value / 10) + 1;\r
+ else\r
+ baud_value /= 10;\r
+ return baud_value;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_SetBaudrate\r
+//* \brief Set the baudrate according to the CPU clock\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US_SetBaudrate (\r
+ AT91PS_USART pUSART, // \arg pointer to a USART controller\r
+ unsigned int mainClock, // \arg peripheral clock\r
+ unsigned int speed) // \arg UART baudrate\r
+{\r
+ //* Define the baud rate divisor register\r
+ pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_SetTimeguard\r
+//* \brief Set USART timeguard\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US_SetTimeguard (\r
+ AT91PS_USART pUSART, // \arg pointer to a USART controller\r
+ unsigned int timeguard) // \arg timeguard value\r
+{\r
+ //* Write the Timeguard Register\r
+ pUSART->US_TTGR = timeguard ;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_EnableIt\r
+//* \brief Enable USART IT\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US_EnableIt (\r
+ AT91PS_USART pUSART, // \arg pointer to a USART controller\r
+ unsigned int flag) // \arg IT to be enabled\r
+{\r
+ //* Write to the IER register\r
+ pUSART->US_IER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_DisableIt\r
+//* \brief Disable USART IT\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US_DisableIt (\r
+ AT91PS_USART pUSART, // \arg pointer to a USART controller\r
+ unsigned int flag) // \arg IT to be disabled\r
+{\r
+ //* Write to the IER register\r
+ pUSART->US_IDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_Configure\r
+//* \brief Configure USART\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US_Configure (\r
+ AT91PS_USART pUSART, // \arg pointer to a USART controller\r
+ unsigned int mainClock, // \arg peripheral clock\r
+ unsigned int mode , // \arg mode Register to be programmed\r
+ unsigned int baudRate , // \arg baudrate to be programmed\r
+ unsigned int timeguard ) // \arg timeguard to be programmed\r
+{\r
+ //* Disable interrupts\r
+ pUSART->US_IDR = (unsigned int) -1;\r
+\r
+ //* Reset receiver and transmitter\r
+ pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ;\r
+\r
+ //* Define the baud rate divisor register\r
+ AT91F_US_SetBaudrate(pUSART, mainClock, baudRate);\r
+\r
+ //* Write the Timeguard Register\r
+ AT91F_US_SetTimeguard(pUSART, timeguard);\r
+\r
+ //* Clear Transmit and Receive Counters\r
+ AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR));\r
+\r
+ //* Define the USART mode\r
+ pUSART->US_MR = mode ;\r
+\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_EnableRx\r
+//* \brief Enable receiving characters\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US_EnableRx (\r
+ AT91PS_USART pUSART) // \arg pointer to a USART controller\r
+{\r
+ //* Enable receiver\r
+ pUSART->US_CR = AT91C_US_RXEN;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_EnableTx\r
+//* \brief Enable sending characters\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US_EnableTx (\r
+ AT91PS_USART pUSART) // \arg pointer to a USART controller\r
+{\r
+ //* Enable transmitter\r
+ pUSART->US_CR = AT91C_US_TXEN;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_ResetRx\r
+//* \brief Reset Receiver and re-enable it\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US_ResetRx (\r
+ AT91PS_USART pUSART) // \arg pointer to a USART controller\r
+{\r
+ //* Reset receiver\r
+ pUSART->US_CR = AT91C_US_RSTRX;\r
+ //* Re-Enable receiver\r
+ pUSART->US_CR = AT91C_US_RXEN;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_ResetTx\r
+//* \brief Reset Transmitter and re-enable it\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US_ResetTx (\r
+ AT91PS_USART pUSART) // \arg pointer to a USART controller\r
+{\r
+ //* Reset transmitter\r
+ pUSART->US_CR = AT91C_US_RSTTX;\r
+ //* Enable transmitter\r
+ pUSART->US_CR = AT91C_US_TXEN;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_DisableRx\r
+//* \brief Disable Receiver\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US_DisableRx (\r
+ AT91PS_USART pUSART) // \arg pointer to a USART controller\r
+{\r
+ //* Disable receiver\r
+ pUSART->US_CR = AT91C_US_RXDIS;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_DisableTx\r
+//* \brief Disable Transmitter\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US_DisableTx (\r
+ AT91PS_USART pUSART) // \arg pointer to a USART controller\r
+{\r
+ //* Disable transmitter\r
+ pUSART->US_CR = AT91C_US_TXDIS;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_Close\r
+//* \brief Close USART: disable IT disable receiver and transmitter, close PDC\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US_Close (\r
+ AT91PS_USART pUSART) // \arg pointer to a USART controller\r
+{\r
+ //* Reset the baud rate divisor register\r
+ pUSART->US_BRGR = 0 ;\r
+\r
+ //* Reset the USART mode\r
+ pUSART->US_MR = 0 ;\r
+\r
+ //* Reset the Timeguard Register\r
+ pUSART->US_TTGR = 0;\r
+\r
+ //* Disable all interrupts\r
+ pUSART->US_IDR = 0xFFFFFFFF ;\r
+\r
+ //* Abort the Peripheral Data Transfers\r
+ AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR));\r
+\r
+ //* Disable receiver and transmitter and stop any activity immediately\r
+ pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_TxReady\r
+//* \brief Return 1 if a character can be written in US_THR\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_US_TxReady (\r
+ AT91PS_USART pUSART ) // \arg pointer to a USART controller\r
+{\r
+ return (pUSART->US_CSR & AT91C_US_TXRDY);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_RxReady\r
+//* \brief Return 1 if a character can be read in US_RHR\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_US_RxReady (\r
+ AT91PS_USART pUSART ) // \arg pointer to a USART controller\r
+{\r
+ return (pUSART->US_CSR & AT91C_US_RXRDY);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_Error\r
+//* \brief Return the error flag\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_US_Error (\r
+ AT91PS_USART pUSART ) // \arg pointer to a USART controller\r
+{\r
+ return (pUSART->US_CSR &\r
+ (AT91C_US_OVRE | // Overrun error\r
+ AT91C_US_FRAME | // Framing error\r
+ AT91C_US_PARE)); // Parity error\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_PutChar\r
+//* \brief Send a character,does not check if ready to send\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US_PutChar (\r
+ AT91PS_USART pUSART,\r
+ int character )\r
+{\r
+ pUSART->US_THR = (character & 0x1FF);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_GetChar\r
+//* \brief Receive a character,does not check if a character is available\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_US_GetChar (\r
+ const AT91PS_USART pUSART)\r
+{\r
+ return((pUSART->US_RHR) & 0x1FF);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_SendFrame\r
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_US_SendFrame(\r
+ AT91PS_USART pUSART,\r
+ char *pBuffer,\r
+ unsigned int szBuffer,\r
+ char *pNextBuffer,\r
+ unsigned int szNextBuffer )\r
+{\r
+ return AT91F_PDC_SendFrame(\r
+ (AT91PS_PDC) &(pUSART->US_RPR),\r
+ pBuffer,\r
+ szBuffer,\r
+ pNextBuffer,\r
+ szNextBuffer);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_ReceiveFrame\r
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_US_ReceiveFrame (\r
+ AT91PS_USART pUSART,\r
+ char *pBuffer,\r
+ unsigned int szBuffer,\r
+ char *pNextBuffer,\r
+ unsigned int szNextBuffer )\r
+{\r
+ return AT91F_PDC_ReceiveFrame(\r
+ (AT91PS_PDC) &(pUSART->US_RPR),\r
+ pBuffer,\r
+ szBuffer,\r
+ pNextBuffer,\r
+ szNextBuffer);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_SetIrdaFilter\r
+//* \brief Set the value of IrDa filter tregister\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US_SetIrdaFilter (\r
+ AT91PS_USART pUSART,\r
+ unsigned char value\r
+)\r
+{\r
+ pUSART->US_IF = value;\r
+}\r
+\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR SSC\r
+ ***************************************************************************** */\r
+//* Define the standard I2S mode configuration\r
+\r
+//* Configuration to set in the SSC Transmit Clock Mode Register\r
+//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits\r
+//* nb_slot_by_frame : number of channels\r
+#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\\r
+ AT91C_SSC_CKS_DIV +\\r
+ AT91C_SSC_CKO_CONTINOUS +\\r
+ AT91C_SSC_CKG_NONE +\\r
+ AT91C_SSC_START_FALL_RF +\\r
+ AT91C_SSC_STTOUT +\\r
+ ((1<<16) & AT91C_SSC_STTDLY) +\\r
+ ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24))\r
+\r
+\r
+//* Configuration to set in the SSC Transmit Frame Mode Register\r
+//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits\r
+//* nb_slot_by_frame : number of channels\r
+#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\\r
+ (nb_bit_by_slot-1) +\\r
+ AT91C_SSC_MSBF +\\r
+ (((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB) +\\r
+ (((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\\r
+ AT91C_SSC_FSOS_NEGATIVE)\r
+\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SSC_SetBaudrate\r
+//* \brief Set the baudrate according to the CPU clock\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SSC_SetBaudrate (\r
+ AT91PS_SSC pSSC, // \arg pointer to a SSC controller\r
+ unsigned int mainClock, // \arg peripheral clock\r
+ unsigned int speed) // \arg SSC baudrate\r
+{\r
+ unsigned int baud_value;\r
+ //* Define the baud rate divisor register\r
+ if (speed == 0)\r
+ baud_value = 0;\r
+ else\r
+ {\r
+ baud_value = (unsigned int) (mainClock * 10)/(2*speed);\r
+ if ((baud_value % 10) >= 5)\r
+ baud_value = (baud_value / 10) + 1;\r
+ else\r
+ baud_value /= 10;\r
+ }\r
+\r
+ pSSC->SSC_CMR = baud_value;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SSC_Configure\r
+//* \brief Configure SSC\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SSC_Configure (\r
+ AT91PS_SSC pSSC, // \arg pointer to a SSC controller\r
+ unsigned int syst_clock, // \arg System Clock Frequency\r
+ unsigned int baud_rate, // \arg Expected Baud Rate Frequency\r
+ unsigned int clock_rx, // \arg Receiver Clock Parameters\r
+ unsigned int mode_rx, // \arg mode Register to be programmed\r
+ unsigned int clock_tx, // \arg Transmitter Clock Parameters\r
+ unsigned int mode_tx) // \arg mode Register to be programmed\r
+{\r
+ //* Disable interrupts\r
+ pSSC->SSC_IDR = (unsigned int) -1;\r
+\r
+ //* Reset receiver and transmitter\r
+ pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ;\r
+\r
+ //* Define the Clock Mode Register\r
+ AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate);\r
+\r
+ //* Write the Receive Clock Mode Register\r
+ pSSC->SSC_RCMR = clock_rx;\r
+\r
+ //* Write the Transmit Clock Mode Register\r
+ pSSC->SSC_TCMR = clock_tx;\r
+\r
+ //* Write the Receive Frame Mode Register\r
+ pSSC->SSC_RFMR = mode_rx;\r
+\r
+ //* Write the Transmit Frame Mode Register\r
+ pSSC->SSC_TFMR = mode_tx;\r
+\r
+ //* Clear Transmit and Receive Counters\r
+ AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR));\r
+\r
+\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SSC_EnableRx\r
+//* \brief Enable receiving datas\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SSC_EnableRx (\r
+ AT91PS_SSC pSSC) // \arg pointer to a SSC controller\r
+{\r
+ //* Enable receiver\r
+ pSSC->SSC_CR = AT91C_SSC_RXEN;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SSC_DisableRx\r
+//* \brief Disable receiving datas\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SSC_DisableRx (\r
+ AT91PS_SSC pSSC) // \arg pointer to a SSC controller\r
+{\r
+ //* Disable receiver\r
+ pSSC->SSC_CR = AT91C_SSC_RXDIS;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SSC_EnableTx\r
+//* \brief Enable sending datas\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SSC_EnableTx (\r
+ AT91PS_SSC pSSC) // \arg pointer to a SSC controller\r
+{\r
+ //* Enable transmitter\r
+ pSSC->SSC_CR = AT91C_SSC_TXEN;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SSC_DisableTx\r
+//* \brief Disable sending datas\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SSC_DisableTx (\r
+ AT91PS_SSC pSSC) // \arg pointer to a SSC controller\r
+{\r
+ //* Disable transmitter\r
+ pSSC->SSC_CR = AT91C_SSC_TXDIS;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SSC_EnableIt\r
+//* \brief Enable SSC IT\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SSC_EnableIt (\r
+ AT91PS_SSC pSSC, // \arg pointer to a SSC controller\r
+ unsigned int flag) // \arg IT to be enabled\r
+{\r
+ //* Write to the IER register\r
+ pSSC->SSC_IER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SSC_DisableIt\r
+//* \brief Disable SSC IT\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SSC_DisableIt (\r
+ AT91PS_SSC pSSC, // \arg pointer to a SSC controller\r
+ unsigned int flag) // \arg IT to be disabled\r
+{\r
+ //* Write to the IDR register\r
+ pSSC->SSC_IDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SSC_ReceiveFrame\r
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_SSC_ReceiveFrame (\r
+ AT91PS_SSC pSSC,\r
+ char *pBuffer,\r
+ unsigned int szBuffer,\r
+ char *pNextBuffer,\r
+ unsigned int szNextBuffer )\r
+{\r
+ return AT91F_PDC_ReceiveFrame(\r
+ (AT91PS_PDC) &(pSSC->SSC_RPR),\r
+ pBuffer,\r
+ szBuffer,\r
+ pNextBuffer,\r
+ szNextBuffer);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SSC_SendFrame\r
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_SSC_SendFrame(\r
+ AT91PS_SSC pSSC,\r
+ char *pBuffer,\r
+ unsigned int szBuffer,\r
+ char *pNextBuffer,\r
+ unsigned int szNextBuffer )\r
+{\r
+ return AT91F_PDC_SendFrame(\r
+ (AT91PS_PDC) &(pSSC->SSC_RPR),\r
+ pBuffer,\r
+ szBuffer,\r
+ pNextBuffer,\r
+ szNextBuffer);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SSC_GetInterruptMaskStatus\r
+//* \brief Return SSC Interrupt Mask Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status\r
+ AT91PS_SSC pSsc) // \arg pointer to a SSC controller\r
+{\r
+ return pSsc->SSC_IMR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SSC_IsInterruptMasked\r
+//* \brief Test if SSC Interrupt is Masked \r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_SSC_IsInterruptMasked(\r
+ AT91PS_SSC pSsc, // \arg pointer to a SSC controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag);\r
+}\r
+\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR TWI\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TWI_EnableIt\r
+//* \brief Enable TWI IT\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TWI_EnableIt (\r
+ AT91PS_TWI pTWI, // \arg pointer to a TWI controller\r
+ unsigned int flag) // \arg IT to be enabled\r
+{\r
+ //* Write to the IER register\r
+ pTWI->TWI_IER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TWI_DisableIt\r
+//* \brief Disable TWI IT\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TWI_DisableIt (\r
+ AT91PS_TWI pTWI, // \arg pointer to a TWI controller\r
+ unsigned int flag) // \arg IT to be disabled\r
+{\r
+ //* Write to the IDR register\r
+ pTWI->TWI_IDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TWI_Configure\r
+//* \brief Configure TWI in master mode\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI ) // \arg pointer to a TWI controller\r
+{\r
+ //* Disable interrupts\r
+ pTWI->TWI_IDR = (unsigned int) -1;\r
+\r
+ //* Reset peripheral\r
+ pTWI->TWI_CR = AT91C_TWI_SWRST;\r
+\r
+ //* Set Master mode\r
+ pTWI->TWI_CR = AT91C_TWI_MSEN;\r
+\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TWI_GetInterruptMaskStatus\r
+//* \brief Return TWI Interrupt Mask Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status\r
+ AT91PS_TWI pTwi) // \arg pointer to a TWI controller\r
+{\r
+ return pTwi->TWI_IMR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TWI_IsInterruptMasked\r
+//* \brief Test if TWI Interrupt is Masked \r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_TWI_IsInterruptMasked(\r
+ AT91PS_TWI pTwi, // \arg pointer to a TWI controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag);\r
+}\r
+\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR PWMC\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWM_GetStatus\r
+//* \brief Return PWM Interrupt Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PWMC_GetStatus( // \return PWM Interrupt Status\r
+ AT91PS_PWMC pPWM) // pointer to a PWM controller\r
+{\r
+ return pPWM->PWMC_SR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWM_InterruptEnable\r
+//* \brief Enable PWM Interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PWMC_InterruptEnable(\r
+ AT91PS_PWMC pPwm, // \arg pointer to a PWM controller\r
+ unsigned int flag) // \arg PWM interrupt to be enabled\r
+{\r
+ pPwm->PWMC_IER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWM_InterruptDisable\r
+//* \brief Disable PWM Interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PWMC_InterruptDisable(\r
+ AT91PS_PWMC pPwm, // \arg pointer to a PWM controller\r
+ unsigned int flag) // \arg PWM interrupt to be disabled\r
+{\r
+ pPwm->PWMC_IDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWM_GetInterruptMaskStatus\r
+//* \brief Return PWM Interrupt Mask Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( // \return PWM Interrupt Mask Status\r
+ AT91PS_PWMC pPwm) // \arg pointer to a PWM controller\r
+{\r
+ return pPwm->PWMC_IMR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWM_IsInterruptMasked\r
+//* \brief Test if PWM Interrupt is Masked\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PWMC_IsInterruptMasked(\r
+ AT91PS_PWMC pPWM, // \arg pointer to a PWM controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_PWMC_GetInterruptMaskStatus(pPWM) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWM_IsStatusSet\r
+//* \brief Test if PWM Interrupt is Set\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PWMC_IsStatusSet(\r
+ AT91PS_PWMC pPWM, // \arg pointer to a PWM controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_PWMC_GetStatus(pPWM) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWM_CfgChannel\r
+//* \brief Test if PWM Interrupt is Set\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PWMC_CfgChannel(\r
+ AT91PS_PWMC pPWM, // \arg pointer to a PWM controller\r
+ unsigned int channelId, // \arg PWM channel ID\r
+ unsigned int mode, // \arg PWM mode\r
+ unsigned int period, // \arg PWM period\r
+ unsigned int duty) // \arg PWM duty cycle\r
+{\r
+ pPWM->PWMC_CH[channelId].PWMC_CMR = mode;\r
+ pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty;\r
+ pPWM->PWMC_CH[channelId].PWMC_CPRDR = period;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWM_StartChannel\r
+//* \brief Enable channel\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PWMC_StartChannel(\r
+ AT91PS_PWMC pPWM, // \arg pointer to a PWM controller\r
+ unsigned int flag) // \arg Channels IDs to be enabled\r
+{\r
+ pPWM->PWMC_ENA = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWM_StopChannel\r
+//* \brief Disable channel\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PWMC_StopChannel(\r
+ AT91PS_PWMC pPWM, // \arg pointer to a PWM controller\r
+ unsigned int flag) // \arg Channels IDs to be enabled\r
+{\r
+ pPWM->PWMC_DIS = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWM_UpdateChannel\r
+//* \brief Update Period or Duty Cycle\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PWMC_UpdateChannel(\r
+ AT91PS_PWMC pPWM, // \arg pointer to a PWM controller\r
+ unsigned int channelId, // \arg PWM channel ID\r
+ unsigned int update) // \arg Channels IDs to be enabled\r
+{\r
+ pPWM->PWMC_CH[channelId].PWMC_CUPDR = update;\r
+}\r
+\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR UDP\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_EnableIt\r
+//* \brief Enable UDP IT\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_UDP_EnableIt (\r
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller\r
+ unsigned int flag) // \arg IT to be enabled\r
+{\r
+ //* Write to the IER register\r
+ pUDP->UDP_IER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_DisableIt\r
+//* \brief Disable UDP IT\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_UDP_DisableIt (\r
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller\r
+ unsigned int flag) // \arg IT to be disabled\r
+{\r
+ //* Write to the IDR register\r
+ pUDP->UDP_IDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_SetAddress\r
+//* \brief Set UDP functional address\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_UDP_SetAddress (\r
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller\r
+ unsigned char address) // \arg new UDP address\r
+{\r
+ pUDP->UDP_FADDR = (AT91C_UDP_FEN | address);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_EnableEp\r
+//* \brief Enable Endpoint\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_UDP_EnableEp (\r
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller\r
+ unsigned char endpoint) // \arg endpoint number\r
+{\r
+ pUDP->UDP_CSR[endpoint] |= AT91C_UDP_EPEDS;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_DisableEp\r
+//* \brief Enable Endpoint\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_UDP_DisableEp (\r
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller\r
+ unsigned char endpoint) // \arg endpoint number\r
+{\r
+ pUDP->UDP_CSR[endpoint] &= ~AT91C_UDP_EPEDS;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_SetState\r
+//* \brief Set UDP Device state\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_UDP_SetState (\r
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller\r
+ unsigned int flag) // \arg new UDP address\r
+{\r
+ pUDP->UDP_GLBSTATE &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG);\r
+ pUDP->UDP_GLBSTATE |= flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_GetState\r
+//* \brief return UDP Device state\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state\r
+ AT91PS_UDP pUDP) // \arg pointer to a UDP controller\r
+{\r
+ return (pUDP->UDP_GLBSTATE & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_ResetEp\r
+//* \brief Reset UDP endpoint\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_UDP_ResetEp ( // \return the UDP device state\r
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller\r
+ unsigned int flag) // \arg Endpoints to be reset\r
+{\r
+ pUDP->UDP_RSTEP = flag;\r
+ pUDP->UDP_RSTEP = 0;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_EpStall\r
+//* \brief Endpoint will STALL requests\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_UDP_EpStall(\r
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller\r
+ unsigned char endpoint) // \arg endpoint number\r
+{\r
+ pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_EpWrite\r
+//* \brief Write value in the DPR\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_UDP_EpWrite(\r
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller\r
+ unsigned char endpoint, // \arg endpoint number\r
+ unsigned char value) // \arg value to be written in the DPR\r
+{\r
+ pUDP->UDP_FDR[endpoint] = value;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_EpRead\r
+//* \brief Return value from the DPR\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_UDP_EpRead(\r
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller\r
+ unsigned char endpoint) // \arg endpoint number\r
+{\r
+ return pUDP->UDP_FDR[endpoint];\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_EpEndOfWr\r
+//* \brief Notify the UDP that values in DPR are ready to be sent\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_UDP_EpEndOfWr(\r
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller\r
+ unsigned char endpoint) // \arg endpoint number\r
+{\r
+ pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_EpClear\r
+//* \brief Clear flag in the endpoint CSR register\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_UDP_EpClear(\r
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller\r
+ unsigned char endpoint, // \arg endpoint number\r
+ unsigned int flag) // \arg flag to be cleared\r
+{\r
+ pUDP->UDP_CSR[endpoint] &= ~(flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_EpSet\r
+//* \brief Set flag in the endpoint CSR register\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_UDP_EpSet(\r
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller\r
+ unsigned char endpoint, // \arg endpoint number\r
+ unsigned int flag) // \arg flag to be cleared\r
+{\r
+ pUDP->UDP_CSR[endpoint] |= flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_EpStatus\r
+//* \brief Return the endpoint CSR register\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_UDP_EpStatus(\r
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller\r
+ unsigned char endpoint) // \arg endpoint number\r
+{\r
+ return pUDP->UDP_CSR[endpoint];\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_GetInterruptMaskStatus\r
+//* \brief Return UDP Interrupt Mask Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \return UDP Interrupt Mask Status\r
+ AT91PS_UDP pUdp) // \arg pointer to a UDP controller\r
+{\r
+ return pUdp->UDP_IMR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_IsInterruptMasked\r
+//* \brief Test if UDP Interrupt is Masked \r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_UDP_IsInterruptMasked(\r
+ AT91PS_UDP pUdp, // \arg pointer to a UDP controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag);\r
+}\r
+\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR TC\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TC_InterruptEnable\r
+//* \brief Enable TC Interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TC_InterruptEnable(\r
+ AT91PS_TC pTc, // \arg pointer to a TC controller\r
+ unsigned int flag) // \arg TC interrupt to be enabled\r
+{\r
+ pTc->TC_IER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TC_InterruptDisable\r
+//* \brief Disable TC Interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TC_InterruptDisable(\r
+ AT91PS_TC pTc, // \arg pointer to a TC controller\r
+ unsigned int flag) // \arg TC interrupt to be disabled\r
+{\r
+ pTc->TC_IDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TC_GetInterruptMaskStatus\r
+//* \brief Return TC Interrupt Mask Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status\r
+ AT91PS_TC pTc) // \arg pointer to a TC controller\r
+{\r
+ return pTc->TC_IMR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TC_IsInterruptMasked\r
+//* \brief Test if TC Interrupt is Masked \r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_TC_IsInterruptMasked(\r
+ AT91PS_TC pTc, // \arg pointer to a TC controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag);\r
+}\r
+\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR CAN\r
+ ***************************************************************************** */\r
+#define STANDARD_FORMAT 0\r
+#define EXTENDED_FORMAT 1\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_InitMailboxRegisters()\r
+//* \brief Configure the corresponding mailbox\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_InitMailboxRegisters(AT91PS_CAN_MB CAN_Mailbox,\r
+ int mode_reg,\r
+ int acceptance_mask_reg,\r
+ int id_reg,\r
+ int data_low_reg,\r
+ int data_high_reg,\r
+ int control_reg)\r
+{\r
+ CAN_Mailbox->CAN_MB_MCR = 0x0;\r
+ CAN_Mailbox->CAN_MB_MMR = mode_reg;\r
+ CAN_Mailbox->CAN_MB_MAM = acceptance_mask_reg;\r
+ CAN_Mailbox->CAN_MB_MID = id_reg;\r
+ CAN_Mailbox->CAN_MB_MDL = data_low_reg; \r
+ CAN_Mailbox->CAN_MB_MDH = data_high_reg;\r
+ CAN_Mailbox->CAN_MB_MCR = control_reg;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_EnableCAN()\r
+//* \brief \r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_EnableCAN(\r
+ AT91PS_CAN pCAN) // pointer to a CAN controller\r
+{\r
+ pCAN->CAN_MR |= AT91C_CAN_CANEN;\r
+\r
+ // Wait for WAKEUP flag raising <=> 11-recessive-bit were scanned by the transceiver\r
+ while( (pCAN->CAN_SR & AT91C_CAN_WAKEUP) != AT91C_CAN_WAKEUP );\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_DisableCAN()\r
+//* \brief \r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_DisableCAN(\r
+ AT91PS_CAN pCAN) // pointer to a CAN controller\r
+{\r
+ pCAN->CAN_MR &= ~AT91C_CAN_CANEN;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_EnableIt\r
+//* \brief Enable CAN interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CAN_EnableIt (\r
+ AT91PS_CAN pCAN, // pointer to a CAN controller\r
+ unsigned int flag) // IT to be enabled\r
+{\r
+ //* Write to the IER register\r
+ pCAN->CAN_IER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_DisableIt\r
+//* \brief Disable CAN interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CAN_DisableIt (\r
+ AT91PS_CAN pCAN, // pointer to a CAN controller\r
+ unsigned int flag) // IT to be disabled\r
+{\r
+ //* Write to the IDR register\r
+ pCAN->CAN_IDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_GetStatus\r
+//* \brief Return CAN Interrupt Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CAN_GetStatus( // \return CAN Interrupt Status\r
+ AT91PS_CAN pCAN) // pointer to a CAN controller\r
+{\r
+ return pCAN->CAN_SR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_GetInterruptMaskStatus\r
+//* \brief Return CAN Interrupt Mask Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CAN_GetInterruptMaskStatus( // \return CAN Interrupt Mask Status\r
+ AT91PS_CAN pCAN) // pointer to a CAN controller\r
+{\r
+ return pCAN->CAN_IMR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_IsInterruptMasked\r
+//* \brief Test if CAN Interrupt is Masked \r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CAN_IsInterruptMasked(\r
+ AT91PS_CAN pCAN, // \arg pointer to a CAN controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_CAN_GetInterruptMaskStatus(pCAN) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_IsStatusSet\r
+//* \brief Test if CAN Interrupt is Set\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CAN_IsStatusSet(\r
+ AT91PS_CAN pCAN, // \arg pointer to a CAN controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_CAN_GetStatus(pCAN) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_CfgModeReg\r
+//* \brief Configure the Mode Register of the CAN controller\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CAN_CfgModeReg (\r
+ AT91PS_CAN pCAN, // pointer to a CAN controller\r
+ unsigned int mode) // mode register \r
+{\r
+ //* Write to the MR register\r
+ pCAN->CAN_MR = mode;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_GetModeReg\r
+//* \brief Return the Mode Register of the CAN controller value\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CAN_GetModeReg (\r
+ AT91PS_CAN pCAN // pointer to a CAN controller\r
+ )\r
+{\r
+ return pCAN->CAN_MR; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_CfgBaudrateReg\r
+//* \brief Configure the Baudrate of the CAN controller for the network\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CAN_CfgBaudrateReg (\r
+ AT91PS_CAN pCAN, // pointer to a CAN controller\r
+ unsigned int baudrate_cfg)\r
+{\r
+ //* Write to the BR register\r
+ pCAN->CAN_BR = baudrate_cfg; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_GetBaudrate\r
+//* \brief Return the Baudrate of the CAN controller for the network value\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CAN_GetBaudrate (\r
+ AT91PS_CAN pCAN // pointer to a CAN controller\r
+ )\r
+{\r
+ return pCAN->CAN_BR; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_GetInternalCounter\r
+//* \brief Return CAN Timer Regsiter Value\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CAN_GetInternalCounter (\r
+ AT91PS_CAN pCAN // pointer to a CAN controller\r
+ )\r
+{\r
+ return pCAN->CAN_TIM; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_GetTimestamp\r
+//* \brief Return CAN Timestamp Register Value\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CAN_GetTimestamp (\r
+ AT91PS_CAN pCAN // pointer to a CAN controller\r
+ )\r
+{\r
+ return pCAN->CAN_TIMESTP; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_GetErrorCounter\r
+//* \brief Return CAN Error Counter Register Value\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CAN_GetErrorCounter (\r
+ AT91PS_CAN pCAN // pointer to a CAN controller\r
+ )\r
+{\r
+ return pCAN->CAN_ECR; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_InitTransferRequest\r
+//* \brief Request for a transfer on the corresponding mailboxes\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CAN_InitTransferRequest (\r
+ AT91PS_CAN pCAN, // pointer to a CAN controller\r
+ unsigned int transfer_cmd)\r
+{\r
+ pCAN->CAN_TCR = transfer_cmd; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_InitAbortRequest\r
+//* \brief Abort the corresponding mailboxes\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CAN_InitAbortRequest (\r
+ AT91PS_CAN pCAN, // pointer to a CAN controller\r
+ unsigned int abort_cmd)\r
+{\r
+ pCAN->CAN_ACR = abort_cmd; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_CfgMessageModeReg\r
+//* \brief Program the Message Mode Register\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CAN_CfgMessageModeReg (\r
+ AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox\r
+ unsigned int mode)\r
+{\r
+ CAN_Mailbox->CAN_MB_MMR = mode; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_GetMessageModeReg\r
+//* \brief Return the Message Mode Register\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CAN_GetMessageModeReg (\r
+ AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox\r
+{\r
+ return CAN_Mailbox->CAN_MB_MMR; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_CfgMessageIDReg\r
+//* \brief Program the Message ID Register\r
+//* \brief Version == 0 for Standard messsage, Version == 1 for Extended \r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CAN_CfgMessageIDReg (\r
+ AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox\r
+ unsigned int id,\r
+ unsigned char version)\r
+{\r
+ if(version==0) // IDvA Standard Format\r
+ CAN_Mailbox->CAN_MB_MID = id<<18;\r
+ else // IDvB Extended Format\r
+ CAN_Mailbox->CAN_MB_MID = id | (1<<29); // set MIDE bit\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_GetMessageIDReg\r
+//* \brief Return the Message ID Register\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CAN_GetMessageIDReg (\r
+ AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox\r
+{\r
+ return CAN_Mailbox->CAN_MB_MID;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_CfgMessageAcceptanceMaskReg\r
+//* \brief Program the Message Acceptance Mask Register\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CAN_CfgMessageAcceptanceMaskReg (\r
+ AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox\r
+ unsigned int mask)\r
+{\r
+ CAN_Mailbox->CAN_MB_MAM = mask;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_GetMessageAcceptanceMaskReg\r
+//* \brief Return the Message Acceptance Mask Register\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CAN_GetMessageAcceptanceMaskReg (\r
+ AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox\r
+{\r
+ return CAN_Mailbox->CAN_MB_MAM;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_GetFamilyID\r
+//* \brief Return the Message ID Register\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CAN_GetFamilyID (\r
+ AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox\r
+{\r
+ return CAN_Mailbox->CAN_MB_MFID; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_CfgMessageCtrl\r
+//* \brief Request and config for a transfer on the corresponding mailbox\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CAN_CfgMessageCtrlReg (\r
+ AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox\r
+ unsigned int message_ctrl_cmd)\r
+{\r
+ CAN_Mailbox->CAN_MB_MCR = message_ctrl_cmd; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_GetMessageStatus\r
+//* \brief Return CAN Mailbox Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CAN_GetMessageStatus (\r
+ AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox\r
+{\r
+ return CAN_Mailbox->CAN_MB_MSR; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_CfgMessageDataLow\r
+//* \brief Program data low value\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CAN_CfgMessageDataLow (\r
+ AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox\r
+ unsigned int data)\r
+{\r
+ CAN_Mailbox->CAN_MB_MDL = data; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_GetMessageDataLow\r
+//* \brief Return data low value\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CAN_GetMessageDataLow (\r
+ AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox\r
+{\r
+ return CAN_Mailbox->CAN_MB_MDL; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_CfgMessageDataHigh\r
+//* \brief Program data high value\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CAN_CfgMessageDataHigh (\r
+ AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox\r
+ unsigned int data)\r
+{\r
+ CAN_Mailbox->CAN_MB_MDH = data; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_GetMessageDataHigh\r
+//* \brief Return data high value\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CAN_GetMessageDataHigh (\r
+ AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox\r
+{\r
+ return CAN_Mailbox->CAN_MB_MDH; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_Open\r
+//* \brief Open a CAN Port\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CAN_Open (\r
+ const unsigned int null) // \arg\r
+{\r
+ /* NOT DEFINED AT THIS MOMENT */\r
+ return ( 0 );\r
+}\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR ADC\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_EnableIt\r
+//* \brief Enable ADC interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_ADC_EnableIt (\r
+ AT91PS_ADC pADC, // pointer to a ADC controller\r
+ unsigned int flag) // IT to be enabled\r
+{\r
+ //* Write to the IER register\r
+ pADC->ADC_IER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_DisableIt\r
+//* \brief Disable ADC interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_ADC_DisableIt (\r
+ AT91PS_ADC pADC, // pointer to a ADC controller\r
+ unsigned int flag) // IT to be disabled\r
+{\r
+ //* Write to the IDR register\r
+ pADC->ADC_IDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_GetStatus\r
+//* \brief Return ADC Interrupt Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_GetStatus( // \return ADC Interrupt Status\r
+ AT91PS_ADC pADC) // pointer to a ADC controller\r
+{\r
+ return pADC->ADC_SR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_GetInterruptMaskStatus\r
+//* \brief Return ADC Interrupt Mask Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_GetInterruptMaskStatus( // \return ADC Interrupt Mask Status\r
+ AT91PS_ADC pADC) // pointer to a ADC controller\r
+{\r
+ return pADC->ADC_IMR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_IsInterruptMasked\r
+//* \brief Test if ADC Interrupt is Masked \r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_IsInterruptMasked(\r
+ AT91PS_ADC pADC, // \arg pointer to a ADC controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_ADC_GetInterruptMaskStatus(pADC) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_IsStatusSet\r
+//* \brief Test if ADC Status is Set\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_IsStatusSet(\r
+ AT91PS_ADC pADC, // \arg pointer to a ADC controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_ADC_GetStatus(pADC) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_CfgModeReg\r
+//* \brief Configure the Mode Register of the ADC controller\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_ADC_CfgModeReg (\r
+ AT91PS_ADC pADC, // pointer to a ADC controller\r
+ unsigned int mode) // mode register \r
+{\r
+ //* Write to the MR register\r
+ pADC->ADC_MR = mode;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_GetModeReg\r
+//* \brief Return the Mode Register of the ADC controller value\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_GetModeReg (\r
+ AT91PS_ADC pADC // pointer to a ADC controller\r
+ )\r
+{\r
+ return pADC->ADC_MR; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_CfgTimings\r
+//* \brief Configure the different necessary timings of the ADC controller\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_ADC_CfgTimings (\r
+ AT91PS_ADC pADC, // pointer to a ADC controller\r
+ unsigned int mck_clock, // in MHz \r
+ unsigned int adc_clock, // in MHz \r
+ unsigned int startup_time, // in us \r
+ unsigned int sample_and_hold_time) // in ns \r
+{\r
+ unsigned int prescal,startup,shtim;\r
+ \r
+ prescal = mck_clock/(2*adc_clock) - 1;\r
+ startup = adc_clock*startup_time/8 - 1;\r
+ shtim = adc_clock*sample_and_hold_time/1000 - 1;\r
+ \r
+ //* Write to the MR register\r
+ pADC->ADC_MR = ( (prescal<<8) & AT91C_ADC_PRESCAL) | ( (startup<<16) & AT91C_ADC_STARTUP) | ( (shtim<<24) & AT91C_ADC_SHTIM);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_EnableChannel\r
+//* \brief Return ADC Timer Register Value\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_ADC_EnableChannel (\r
+ AT91PS_ADC pADC, // pointer to a ADC controller\r
+ unsigned int channel) // mode register \r
+{\r
+ //* Write to the CHER register\r
+ pADC->ADC_CHER = channel;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_DisableChannel\r
+//* \brief Return ADC Timer Register Value\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_ADC_DisableChannel (\r
+ AT91PS_ADC pADC, // pointer to a ADC controller\r
+ unsigned int channel) // mode register \r
+{\r
+ //* Write to the CHDR register\r
+ pADC->ADC_CHDR = channel;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_GetChannelStatus\r
+//* \brief Return ADC Timer Register Value\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_GetChannelStatus (\r
+ AT91PS_ADC pADC // pointer to a ADC controller\r
+ )\r
+{\r
+ return pADC->ADC_CHSR; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_StartConversion\r
+//* \brief Software request for a analog to digital conversion \r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_ADC_StartConversion (\r
+ AT91PS_ADC pADC // pointer to a ADC controller\r
+ )\r
+{\r
+ pADC->ADC_CR = AT91C_ADC_START; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_SoftReset\r
+//* \brief Software reset\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_ADC_SoftReset (\r
+ AT91PS_ADC pADC // pointer to a ADC controller\r
+ )\r
+{\r
+ pADC->ADC_CR = AT91C_ADC_SWRST; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_GetLastConvertedData\r
+//* \brief Return the Last Converted Data\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_GetLastConvertedData (\r
+ AT91PS_ADC pADC // pointer to a ADC controller\r
+ )\r
+{\r
+ return pADC->ADC_LCDR; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_GetConvertedDataCH0\r
+//* \brief Return the Channel 0 Converted Data\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_GetConvertedDataCH0 (\r
+ AT91PS_ADC pADC // pointer to a ADC controller\r
+ )\r
+{\r
+ return pADC->ADC_CDR0; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_GetConvertedDataCH1\r
+//* \brief Return the Channel 1 Converted Data\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_GetConvertedDataCH1 (\r
+ AT91PS_ADC pADC // pointer to a ADC controller\r
+ )\r
+{\r
+ return pADC->ADC_CDR1; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_GetConvertedDataCH2\r
+//* \brief Return the Channel 2 Converted Data\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_GetConvertedDataCH2 (\r
+ AT91PS_ADC pADC // pointer to a ADC controller\r
+ )\r
+{\r
+ return pADC->ADC_CDR2; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_GetConvertedDataCH3\r
+//* \brief Return the Channel 3 Converted Data\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_GetConvertedDataCH3 (\r
+ AT91PS_ADC pADC // pointer to a ADC controller\r
+ )\r
+{\r
+ return pADC->ADC_CDR3; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_GetConvertedDataCH4\r
+//* \brief Return the Channel 4 Converted Data\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_GetConvertedDataCH4 (\r
+ AT91PS_ADC pADC // pointer to a ADC controller\r
+ )\r
+{\r
+ return pADC->ADC_CDR4; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_GetConvertedDataCH5\r
+//* \brief Return the Channel 5 Converted Data\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_GetConvertedDataCH5 (\r
+ AT91PS_ADC pADC // pointer to a ADC controller\r
+ )\r
+{\r
+ return pADC->ADC_CDR5; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_GetConvertedDataCH6\r
+//* \brief Return the Channel 6 Converted Data\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_GetConvertedDataCH6 (\r
+ AT91PS_ADC pADC // pointer to a ADC controller\r
+ )\r
+{\r
+ return pADC->ADC_CDR6; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_GetConvertedDataCH7\r
+//* \brief Return the Channel 7 Converted Data\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_GetConvertedDataCH7 (\r
+ AT91PS_ADC pADC // pointer to a ADC controller\r
+ )\r
+{\r
+ return pADC->ADC_CDR7; \r
+}\r
+\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR AES\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AES_EnableIt\r
+//* \brief Enable AES interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AES_EnableIt (\r
+ AT91PS_AES pAES, // pointer to a AES controller\r
+ unsigned int flag) // IT to be enabled\r
+{\r
+ //* Write to the IER register\r
+ pAES->AES_IER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AES_DisableIt\r
+//* \brief Disable AES interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AES_DisableIt (\r
+ AT91PS_AES pAES, // pointer to a AES controller\r
+ unsigned int flag) // IT to be disabled\r
+{\r
+ //* Write to the IDR register\r
+ pAES->AES_IDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AES_GetStatus\r
+//* \brief Return AES Interrupt Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_AES_GetStatus( // \return AES Interrupt Status\r
+ AT91PS_AES pAES) // pointer to a AES controller\r
+{\r
+ return pAES->AES_ISR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AES_GetInterruptMaskStatus\r
+//* \brief Return AES Interrupt Mask Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_AES_GetInterruptMaskStatus( // \return AES Interrupt Mask Status\r
+ AT91PS_AES pAES) // pointer to a AES controller\r
+{\r
+ return pAES->AES_IMR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AES_IsInterruptMasked\r
+//* \brief Test if AES Interrupt is Masked \r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_AES_IsInterruptMasked(\r
+ AT91PS_AES pAES, // \arg pointer to a AES controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_AES_GetInterruptMaskStatus(pAES) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AES_IsStatusSet\r
+//* \brief Test if AES Status is Set\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_AES_IsStatusSet(\r
+ AT91PS_AES pAES, // \arg pointer to a AES controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_AES_GetStatus(pAES) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AES_CfgModeReg\r
+//* \brief Configure the Mode Register of the AES controller\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AES_CfgModeReg (\r
+ AT91PS_AES pAES, // pointer to a AES controller\r
+ unsigned int mode) // mode register \r
+{\r
+ //* Write to the MR register\r
+ pAES->AES_MR = mode;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AES_GetModeReg\r
+//* \brief Return the Mode Register of the AES controller value\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_AES_GetModeReg (\r
+ AT91PS_AES pAES // pointer to a AES controller\r
+ )\r
+{\r
+ return pAES->AES_MR; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AES_StartProcessing\r
+//* \brief Start Encryption or Decryption\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AES_StartProcessing (\r
+ AT91PS_AES pAES // pointer to a AES controller\r
+ )\r
+{\r
+ pAES->AES_CR = AT91C_AES_START; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AES_SoftReset\r
+//* \brief Reset AES\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AES_SoftReset (\r
+ AT91PS_AES pAES // pointer to a AES controller\r
+ )\r
+{\r
+ pAES->AES_CR = AT91C_AES_SWRST; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AES_LoadNewSeed\r
+//* \brief Load New Seed in the random number generator\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AES_LoadNewSeed (\r
+ AT91PS_AES pAES // pointer to a AES controller\r
+ )\r
+{\r
+ pAES->AES_CR = AT91C_AES_LOADSEED; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AES_SetCryptoKey\r
+//* \brief Set Cryptographic Key x\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AES_SetCryptoKey (\r
+ AT91PS_AES pAES, // pointer to a AES controller\r
+ unsigned char index,\r
+ unsigned int keyword\r
+ )\r
+{\r
+ pAES->AES_KEYWxR[index] = keyword; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AES_InputData\r
+//* \brief Set Input Data x\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AES_InputData (\r
+ AT91PS_AES pAES, // pointer to a AES controller\r
+ unsigned char index,\r
+ unsigned int indata\r
+ )\r
+{\r
+ pAES->AES_IDATAxR[index] = indata; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AES_GetOutputData\r
+//* \brief Get Output Data x\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_AES_GetOutputData (\r
+ AT91PS_AES pAES, // pointer to a AES controller\r
+ unsigned char index\r
+ )\r
+{\r
+ return pAES->AES_ODATAxR[index]; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AES_SetInitializationVector\r
+//* \brief Set Initialization Vector (or Counter) x\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AES_SetInitializationVector (\r
+ AT91PS_AES pAES, // pointer to a AES controller\r
+ unsigned char index,\r
+ unsigned int initvector\r
+ )\r
+{\r
+ pAES->AES_IVxR[index] = initvector; \r
+}\r
+\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR TDES\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TDES_EnableIt\r
+//* \brief Enable TDES interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TDES_EnableIt (\r
+ AT91PS_TDES pTDES, // pointer to a TDES controller\r
+ unsigned int flag) // IT to be enabled\r
+{\r
+ //* Write to the IER register\r
+ pTDES->TDES_IER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TDES_DisableIt\r
+//* \brief Disable TDES interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TDES_DisableIt (\r
+ AT91PS_TDES pTDES, // pointer to a TDES controller\r
+ unsigned int flag) // IT to be disabled\r
+{\r
+ //* Write to the IDR register\r
+ pTDES->TDES_IDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TDES_GetStatus\r
+//* \brief Return TDES Interrupt Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_TDES_GetStatus( // \return TDES Interrupt Status\r
+ AT91PS_TDES pTDES) // pointer to a TDES controller\r
+{\r
+ return pTDES->TDES_ISR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TDES_GetInterruptMaskStatus\r
+//* \brief Return TDES Interrupt Mask Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_TDES_GetInterruptMaskStatus( // \return TDES Interrupt Mask Status\r
+ AT91PS_TDES pTDES) // pointer to a TDES controller\r
+{\r
+ return pTDES->TDES_IMR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TDES_IsInterruptMasked\r
+//* \brief Test if TDES Interrupt is Masked \r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_TDES_IsInterruptMasked(\r
+ AT91PS_TDES pTDES, // \arg pointer to a TDES controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_TDES_GetInterruptMaskStatus(pTDES) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TDES_IsStatusSet\r
+//* \brief Test if TDES Status is Set\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_TDES_IsStatusSet(\r
+ AT91PS_TDES pTDES, // \arg pointer to a TDES controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_TDES_GetStatus(pTDES) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TDES_CfgModeReg\r
+//* \brief Configure the Mode Register of the TDES controller\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TDES_CfgModeReg (\r
+ AT91PS_TDES pTDES, // pointer to a TDES controller\r
+ unsigned int mode) // mode register \r
+{\r
+ //* Write to the MR register\r
+ pTDES->TDES_MR = mode;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TDES_GetModeReg\r
+//* \brief Return the Mode Register of the TDES controller value\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_TDES_GetModeReg (\r
+ AT91PS_TDES pTDES // pointer to a TDES controller\r
+ )\r
+{\r
+ return pTDES->TDES_MR; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TDES_StartProcessing\r
+//* \brief Start Encryption or Decryption\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TDES_StartProcessing (\r
+ AT91PS_TDES pTDES // pointer to a TDES controller\r
+ )\r
+{\r
+ pTDES->TDES_CR = AT91C_TDES_START; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TDES_SoftReset\r
+//* \brief Reset TDES\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TDES_SoftReset (\r
+ AT91PS_TDES pTDES // pointer to a TDES controller\r
+ )\r
+{\r
+ pTDES->TDES_CR = AT91C_TDES_SWRST; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TDES_SetCryptoKey1\r
+//* \brief Set Cryptographic Key 1 Word x\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TDES_SetCryptoKey1 (\r
+ AT91PS_TDES pTDES, // pointer to a TDES controller\r
+ unsigned char index,\r
+ unsigned int keyword\r
+ )\r
+{\r
+ pTDES->TDES_KEY1WxR[index] = keyword; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TDES_SetCryptoKey2\r
+//* \brief Set Cryptographic Key 2 Word x\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TDES_SetCryptoKey2 (\r
+ AT91PS_TDES pTDES, // pointer to a TDES controller\r
+ unsigned char index,\r
+ unsigned int keyword\r
+ )\r
+{\r
+ pTDES->TDES_KEY2WxR[index] = keyword; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TDES_SetCryptoKey3\r
+//* \brief Set Cryptographic Key 3 Word x\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TDES_SetCryptoKey3 (\r
+ AT91PS_TDES pTDES, // pointer to a TDES controller\r
+ unsigned char index,\r
+ unsigned int keyword\r
+ )\r
+{\r
+ pTDES->TDES_KEY3WxR[index] = keyword; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TDES_InputData\r
+//* \brief Set Input Data x\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TDES_InputData (\r
+ AT91PS_TDES pTDES, // pointer to a TDES controller\r
+ unsigned char index,\r
+ unsigned int indata\r
+ )\r
+{\r
+ pTDES->TDES_IDATAxR[index] = indata; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TDES_GetOutputData\r
+//* \brief Get Output Data x\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_TDES_GetOutputData (\r
+ AT91PS_TDES pTDES, // pointer to a TDES controller\r
+ unsigned char index\r
+ )\r
+{\r
+ return pTDES->TDES_ODATAxR[index]; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TDES_SetInitializationVector\r
+//* \brief Set Initialization Vector x\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TDES_SetInitializationVector (\r
+ AT91PS_TDES pTDES, // pointer to a TDES controller\r
+ unsigned char index,\r
+ unsigned int initvector\r
+ )\r
+{\r
+ pTDES->TDES_IVxR[index] = initvector; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_DBGU_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for DBGU\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_DBGU_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_SYS));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_DBGU_CfgPIO\r
+//* \brief Configure PIO controllers to drive DBGU signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_DBGU_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOA, // PIO controller base address\r
+ ((unsigned int) AT91C_PA27_DRXD ) |\r
+ ((unsigned int) AT91C_PA28_DTXD ), // Peripheral A\r
+ 0); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for PMC\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PMC_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_SYS));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_CfgPIO\r
+//* \brief Configure PIO controllers to drive PMC signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PMC_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOB, // PIO controller base address\r
+ ((unsigned int) AT91C_PB30_PCK2 ) |\r
+ ((unsigned int) AT91C_PB29_PCK1 ), // Peripheral A\r
+ ((unsigned int) AT91C_PB20_PCK0 ) |\r
+ ((unsigned int) AT91C_PB0_PCK0 ) |\r
+ ((unsigned int) AT91C_PB22_PCK2 ) |\r
+ ((unsigned int) AT91C_PB21_PCK1 )); // Peripheral B\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOA, // PIO controller base address\r
+ 0, // Peripheral A\r
+ ((unsigned int) AT91C_PA30_PCK2 ) |\r
+ ((unsigned int) AT91C_PA13_PCK1 ) |\r
+ ((unsigned int) AT91C_PA27_PCK3 )); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_VREG_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for VREG\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_VREG_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_SYS));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_RSTC_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for RSTC\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_RSTC_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_SYS));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SSC_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for SSC\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SSC_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_SSC));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SSC_CfgPIO\r
+//* \brief Configure PIO controllers to drive SSC signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SSC_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOA, // PIO controller base address\r
+ ((unsigned int) AT91C_PA25_RK ) |\r
+ ((unsigned int) AT91C_PA22_TK ) |\r
+ ((unsigned int) AT91C_PA21_TF ) |\r
+ ((unsigned int) AT91C_PA24_RD ) |\r
+ ((unsigned int) AT91C_PA26_RF ) |\r
+ ((unsigned int) AT91C_PA23_TD ), // Peripheral A\r
+ 0); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_WDTC_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for WDTC\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_WDTC_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_SYS));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US1_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for US1\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US1_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_US1));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US1_CfgPIO\r
+//* \brief Configure PIO controllers to drive US1 signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US1_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOB, // PIO controller base address\r
+ 0, // Peripheral A\r
+ ((unsigned int) AT91C_PB26_RI1 ) |\r
+ ((unsigned int) AT91C_PB24_DSR1 ) |\r
+ ((unsigned int) AT91C_PB23_DCD1 ) |\r
+ ((unsigned int) AT91C_PB25_DTR1 )); // Peripheral B\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOA, // PIO controller base address\r
+ ((unsigned int) AT91C_PA7_SCK1 ) |\r
+ ((unsigned int) AT91C_PA8_RTS1 ) |\r
+ ((unsigned int) AT91C_PA6_TXD1 ) |\r
+ ((unsigned int) AT91C_PA5_RXD1 ) |\r
+ ((unsigned int) AT91C_PA9_CTS1 ), // Peripheral A\r
+ 0); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US0_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for US0\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US0_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_US0));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US0_CfgPIO\r
+//* \brief Configure PIO controllers to drive US0 signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US0_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOA, // PIO controller base address\r
+ ((unsigned int) AT91C_PA0_RXD0 ) |\r
+ ((unsigned int) AT91C_PA4_CTS0 ) |\r
+ ((unsigned int) AT91C_PA3_RTS0 ) |\r
+ ((unsigned int) AT91C_PA2_SCK0 ) |\r
+ ((unsigned int) AT91C_PA1_TXD0 ), // Peripheral A\r
+ 0); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI1_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for SPI1\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SPI1_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_SPI1));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI1_CfgPIO\r
+//* \brief Configure PIO controllers to drive SPI1 signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SPI1_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOB, // PIO controller base address\r
+ 0, // Peripheral A\r
+ ((unsigned int) AT91C_PB16_NPCS13 ) |\r
+ ((unsigned int) AT91C_PB10_NPCS11 ) |\r
+ ((unsigned int) AT91C_PB11_NPCS12 )); // Peripheral B\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOA, // PIO controller base address\r
+ 0, // Peripheral A\r
+ ((unsigned int) AT91C_PA4_NPCS13 ) |\r
+ ((unsigned int) AT91C_PA29_NPCS13 ) |\r
+ ((unsigned int) AT91C_PA21_NPCS10 ) |\r
+ ((unsigned int) AT91C_PA22_SPCK1 ) |\r
+ ((unsigned int) AT91C_PA25_NPCS11 ) |\r
+ ((unsigned int) AT91C_PA2_NPCS11 ) |\r
+ ((unsigned int) AT91C_PA24_MISO1 ) |\r
+ ((unsigned int) AT91C_PA3_NPCS12 ) |\r
+ ((unsigned int) AT91C_PA26_NPCS12 ) |\r
+ ((unsigned int) AT91C_PA23_MOSI1 )); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI0_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for SPI0\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SPI0_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_SPI0));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI0_CfgPIO\r
+//* \brief Configure PIO controllers to drive SPI0 signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SPI0_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOB, // PIO controller base address\r
+ 0, // Peripheral A\r
+ ((unsigned int) AT91C_PB13_NPCS01 ) |\r
+ ((unsigned int) AT91C_PB17_NPCS03 ) |\r
+ ((unsigned int) AT91C_PB14_NPCS02 )); // Peripheral B\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOA, // PIO controller base address\r
+ ((unsigned int) AT91C_PA16_MISO0 ) |\r
+ ((unsigned int) AT91C_PA13_NPCS01 ) |\r
+ ((unsigned int) AT91C_PA15_NPCS03 ) |\r
+ ((unsigned int) AT91C_PA17_MOSI0 ) |\r
+ ((unsigned int) AT91C_PA18_SPCK0 ) |\r
+ ((unsigned int) AT91C_PA14_NPCS02 ) |\r
+ ((unsigned int) AT91C_PA12_NPCS00 ), // Peripheral A\r
+ ((unsigned int) AT91C_PA7_NPCS01 ) |\r
+ ((unsigned int) AT91C_PA9_NPCS03 ) |\r
+ ((unsigned int) AT91C_PA8_NPCS02 )); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PITC_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for PITC\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PITC_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_SYS));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AIC_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for AIC\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AIC_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_FIQ) |\r
+ ((unsigned int) 1 << AT91C_ID_IRQ0) |\r
+ ((unsigned int) 1 << AT91C_ID_IRQ1));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AIC_CfgPIO\r
+//* \brief Configure PIO controllers to drive AIC signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AIC_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOA, // PIO controller base address\r
+ ((unsigned int) AT91C_PA30_IRQ0 ) |\r
+ ((unsigned int) AT91C_PA29_FIQ ), // Peripheral A\r
+ ((unsigned int) AT91C_PA14_IRQ1 )); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AES_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for AES\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AES_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_AES));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TWI_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for TWI\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TWI_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_TWI));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TWI_CfgPIO\r
+//* \brief Configure PIO controllers to drive TWI signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TWI_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOA, // PIO controller base address\r
+ ((unsigned int) AT91C_PA11_TWCK ) |\r
+ ((unsigned int) AT91C_PA10_TWD ), // Peripheral A\r
+ 0); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for ADC\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_ADC_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_ADC));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_CfgPIO\r
+//* \brief Configure PIO controllers to drive ADC signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_ADC_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOB, // PIO controller base address\r
+ 0, // Peripheral A\r
+ ((unsigned int) AT91C_PB18_ADTRG )); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWMC_CH3_CfgPIO\r
+//* \brief Configure PIO controllers to drive PWMC_CH3 signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PWMC_CH3_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOB, // PIO controller base address\r
+ ((unsigned int) AT91C_PB22_PWM3 ), // Peripheral A\r
+ ((unsigned int) AT91C_PB30_PWM3 )); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWMC_CH2_CfgPIO\r
+//* \brief Configure PIO controllers to drive PWMC_CH2 signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PWMC_CH2_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOB, // PIO controller base address\r
+ ((unsigned int) AT91C_PB21_PWM2 ), // Peripheral A\r
+ ((unsigned int) AT91C_PB29_PWM2 )); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWMC_CH1_CfgPIO\r
+//* \brief Configure PIO controllers to drive PWMC_CH1 signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PWMC_CH1_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOB, // PIO controller base address\r
+ ((unsigned int) AT91C_PB20_PWM1 ), // Peripheral A\r
+ ((unsigned int) AT91C_PB28_PWM1 )); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWMC_CH0_CfgPIO\r
+//* \brief Configure PIO controllers to drive PWMC_CH0 signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PWMC_CH0_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOB, // PIO controller base address\r
+ ((unsigned int) AT91C_PB19_PWM0 ), // Peripheral A\r
+ ((unsigned int) AT91C_PB27_PWM0 )); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_RTTC_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for RTTC\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_RTTC_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_SYS));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for UDP\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_UDP_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_UDP));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TDES_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for TDES\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TDES_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_TDES));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_EMAC_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for EMAC\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_EMAC_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_EMAC));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_EMAC_CfgPIO\r
+//* \brief Configure PIO controllers to drive EMAC signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_EMAC_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOB, // PIO controller base address\r
+ ((unsigned int) AT91C_PB2_ETX0 ) |\r
+ ((unsigned int) AT91C_PB12_ETXER ) |\r
+ ((unsigned int) AT91C_PB16_ECOL ) |\r
+ ((unsigned int) AT91C_PB11_ETX3 ) |\r
+ ((unsigned int) AT91C_PB6_ERX1 ) |\r
+ ((unsigned int) AT91C_PB15_ERXDV ) |\r
+ ((unsigned int) AT91C_PB13_ERX2 ) |\r
+ ((unsigned int) AT91C_PB3_ETX1 ) |\r
+ ((unsigned int) AT91C_PB8_EMDC ) |\r
+ ((unsigned int) AT91C_PB5_ERX0 ) |\r
+ //((unsigned int) AT91C_PB18_EF100 ) |\r
+ ((unsigned int) AT91C_PB14_ERX3 ) |\r
+ ((unsigned int) AT91C_PB4_ECRS_ECRSDV) |\r
+ ((unsigned int) AT91C_PB1_ETXEN ) |\r
+ ((unsigned int) AT91C_PB10_ETX2 ) |\r
+ ((unsigned int) AT91C_PB0_ETXCK_EREFCK) |\r
+ ((unsigned int) AT91C_PB9_EMDIO ) |\r
+ ((unsigned int) AT91C_PB7_ERXER ) |\r
+ ((unsigned int) AT91C_PB17_ERXCK ), // Peripheral A\r
+ 0); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TC0_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for TC0\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TC0_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_TC0));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TC0_CfgPIO\r
+//* \brief Configure PIO controllers to drive TC0 signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TC0_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOB, // PIO controller base address\r
+ ((unsigned int) AT91C_PB23_TIOA0 ) |\r
+ ((unsigned int) AT91C_PB24_TIOB0 ), // Peripheral A\r
+ ((unsigned int) AT91C_PB12_TCLK0 )); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TC1_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for TC1\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TC1_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_TC1));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TC1_CfgPIO\r
+//* \brief Configure PIO controllers to drive TC1 signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TC1_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOB, // PIO controller base address\r
+ ((unsigned int) AT91C_PB25_TIOA1 ) |\r
+ ((unsigned int) AT91C_PB26_TIOB1 ), // Peripheral A\r
+ ((unsigned int) AT91C_PB19_TCLK1 )); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TC2_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for TC2\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TC2_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_TC2));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TC2_CfgPIO\r
+//* \brief Configure PIO controllers to drive TC2 signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TC2_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOB, // PIO controller base address\r
+ ((unsigned int) AT91C_PB28_TIOB2 ) |\r
+ ((unsigned int) AT91C_PB27_TIOA2 ), // Peripheral A\r
+ 0); // Peripheral B\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOA, // PIO controller base address\r
+ 0, // Peripheral A\r
+ ((unsigned int) AT91C_PA15_TCLK2 )); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_MC_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for MC\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_MC_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_SYS));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIOA_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for PIOA\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIOA_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_PIOA));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIOB_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for PIOB\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIOB_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_PIOB));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for CAN\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CAN_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_CAN));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_CfgPIO\r
+//* \brief Configure PIO controllers to drive CAN signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CAN_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOA, // PIO controller base address\r
+ ((unsigned int) AT91C_PA20_CANTX ) |\r
+ ((unsigned int) AT91C_PA19_CANRX ), // Peripheral A\r
+ 0); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWMC_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for PWMC\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PWMC_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_PWMC));\r
+}\r
+\r
+#endif // lib_AT91SAM7X128_H\r
--- /dev/null
+//* ----------------------------------------------------------------------------\r
+//* ATMEL Microcontroller Software Support - ROUSSET -\r
+//* ----------------------------------------------------------------------------\r
+//* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+//* ----------------------------------------------------------------------------\r
+//* File Name : lib_AT91SAM7X256.h\r
+//* Object : AT91SAM7X256 inlined functions\r
+//* Generated : AT91 SW Application Group 05/20/2005 (16:22:29)\r
+//*\r
+//* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003//\r
+//* CVS Reference : /lib_pmc_SAM7X.h/1.1/Tue Feb 1 08:32:10 2005//\r
+//* CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005//\r
+//* CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004//\r
+//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003//\r
+//* CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004//\r
+//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002//\r
+//* CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003//\r
+//* CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004//\r
+//* CVS Reference : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005//\r
+//* CVS Reference : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005//\r
+//* CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004//\r
+//* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003//\r
+//* CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004//\r
+//* CVS Reference : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005//\r
+//* CVS Reference : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005//\r
+//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//\r
+//* CVS Reference : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004//\r
+//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003//\r
+//* CVS Reference : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003//\r
+//* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//\r
+//* CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002//\r
+//* ----------------------------------------------------------------------------\r
+\r
+#ifndef lib_AT91SAM7X256_H\r
+#define lib_AT91SAM7X256_H\r
+\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR AIC\r
+ ***************************************************************************** */\r
+#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20]\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AIC_ConfigureIt\r
+//* \brief Interrupt Handler Initialization\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_AIC_ConfigureIt (\r
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers\r
+ unsigned int irq_id, // \arg interrupt number to initialize\r
+ unsigned int priority, // \arg priority to give to the interrupt\r
+ unsigned int src_type, // \arg activation and sense of activation\r
+ void (*newHandler) (void) ) // \arg address of the interrupt handler\r
+{\r
+ unsigned int oldHandler;\r
+ unsigned int mask ;\r
+\r
+ oldHandler = pAic->AIC_SVR[irq_id];\r
+\r
+ mask = 0x1 << irq_id ;\r
+ //* Disable the interrupt on the interrupt controller\r
+ pAic->AIC_IDCR = mask ;\r
+ //* Save the interrupt handler routine pointer and the interrupt priority\r
+ pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ;\r
+ //* Store the Source Mode Register\r
+ pAic->AIC_SMR[irq_id] = src_type | priority ;\r
+ //* Clear the interrupt on the interrupt controller\r
+ pAic->AIC_ICCR = mask ;\r
+\r
+ return oldHandler;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AIC_EnableIt\r
+//* \brief Enable corresponding IT number\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AIC_EnableIt (\r
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers\r
+ unsigned int irq_id ) // \arg interrupt number to initialize\r
+{\r
+ //* Enable the interrupt on the interrupt controller\r
+ pAic->AIC_IECR = 0x1 << irq_id ;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AIC_DisableIt\r
+//* \brief Disable corresponding IT number\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AIC_DisableIt (\r
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers\r
+ unsigned int irq_id ) // \arg interrupt number to initialize\r
+{\r
+ unsigned int mask = 0x1 << irq_id;\r
+ //* Disable the interrupt on the interrupt controller\r
+ pAic->AIC_IDCR = mask ;\r
+ //* Clear the interrupt on the Interrupt Controller ( if one is pending )\r
+ pAic->AIC_ICCR = mask ;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AIC_ClearIt\r
+//* \brief Clear corresponding IT number\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AIC_ClearIt (\r
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers\r
+ unsigned int irq_id) // \arg interrupt number to initialize\r
+{\r
+ //* Clear the interrupt on the Interrupt Controller ( if one is pending )\r
+ pAic->AIC_ICCR = (0x1 << irq_id);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AIC_AcknowledgeIt\r
+//* \brief Acknowledge corresponding IT number\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AIC_AcknowledgeIt (\r
+ AT91PS_AIC pAic) // \arg pointer to the AIC registers\r
+{\r
+ pAic->AIC_EOICR = pAic->AIC_EOICR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AIC_SetExceptionVector\r
+//* \brief Configure vector handler\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_AIC_SetExceptionVector (\r
+ unsigned int *pVector, // \arg pointer to the AIC registers\r
+ void (*Handler) () ) // \arg Interrupt Handler\r
+{\r
+ unsigned int oldVector = *pVector;\r
+\r
+ if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE)\r
+ *pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE;\r
+ else\r
+ *pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000;\r
+\r
+ return oldVector;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AIC_Trig\r
+//* \brief Trig an IT\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AIC_Trig (\r
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers\r
+ unsigned int irq_id) // \arg interrupt number\r
+{\r
+ pAic->AIC_ISCR = (0x1 << irq_id) ;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AIC_IsActive\r
+//* \brief Test if an IT is active\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_AIC_IsActive (\r
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers\r
+ unsigned int irq_id) // \arg Interrupt Number\r
+{\r
+ return (pAic->AIC_ISR & (0x1 << irq_id));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AIC_IsPending\r
+//* \brief Test if an IT is pending\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_AIC_IsPending (\r
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers\r
+ unsigned int irq_id) // \arg Interrupt Number\r
+{\r
+ return (pAic->AIC_IPR & (0x1 << irq_id));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AIC_Open\r
+//* \brief Set exception vectors and AIC registers to default values\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AIC_Open(\r
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers\r
+ void (*IrqHandler) (), // \arg Default IRQ vector exception\r
+ void (*FiqHandler) (), // \arg Default FIQ vector exception\r
+ void (*DefaultHandler) (), // \arg Default Handler set in ISR\r
+ void (*SpuriousHandler) (), // \arg Default Spurious Handler\r
+ unsigned int protectMode) // \arg Debug Control Register\r
+{\r
+ int i;\r
+\r
+ // Disable all interrupts and set IVR to the default handler\r
+ for (i = 0; i < 32; ++i) {\r
+ AT91F_AIC_DisableIt(pAic, i);\r
+ AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler);\r
+ }\r
+\r
+ // Set the IRQ exception vector\r
+ AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler);\r
+ // Set the Fast Interrupt exception vector\r
+ AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler);\r
+\r
+ pAic->AIC_SPU = (unsigned int) SpuriousHandler;\r
+ pAic->AIC_DCR = protectMode;\r
+}\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR PDC\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_SetNextRx\r
+//* \brief Set the next receive transfer descriptor\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PDC_SetNextRx (\r
+ AT91PS_PDC pPDC, // \arg pointer to a PDC controller\r
+ char *address, // \arg address to the next bloc to be received\r
+ unsigned int bytes) // \arg number of bytes to be received\r
+{\r
+ pPDC->PDC_RNPR = (unsigned int) address;\r
+ pPDC->PDC_RNCR = bytes;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_SetNextTx\r
+//* \brief Set the next transmit transfer descriptor\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PDC_SetNextTx (\r
+ AT91PS_PDC pPDC, // \arg pointer to a PDC controller\r
+ char *address, // \arg address to the next bloc to be transmitted\r
+ unsigned int bytes) // \arg number of bytes to be transmitted\r
+{\r
+ pPDC->PDC_TNPR = (unsigned int) address;\r
+ pPDC->PDC_TNCR = bytes;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_SetRx\r
+//* \brief Set the receive transfer descriptor\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PDC_SetRx (\r
+ AT91PS_PDC pPDC, // \arg pointer to a PDC controller\r
+ char *address, // \arg address to the next bloc to be received\r
+ unsigned int bytes) // \arg number of bytes to be received\r
+{\r
+ pPDC->PDC_RPR = (unsigned int) address;\r
+ pPDC->PDC_RCR = bytes;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_SetTx\r
+//* \brief Set the transmit transfer descriptor\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PDC_SetTx (\r
+ AT91PS_PDC pPDC, // \arg pointer to a PDC controller\r
+ char *address, // \arg address to the next bloc to be transmitted\r
+ unsigned int bytes) // \arg number of bytes to be transmitted\r
+{\r
+ pPDC->PDC_TPR = (unsigned int) address;\r
+ pPDC->PDC_TCR = bytes;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_EnableTx\r
+//* \brief Enable transmit\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PDC_EnableTx (\r
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller\r
+{\r
+ pPDC->PDC_PTCR = AT91C_PDC_TXTEN;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_EnableRx\r
+//* \brief Enable receive\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PDC_EnableRx (\r
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller\r
+{\r
+ pPDC->PDC_PTCR = AT91C_PDC_RXTEN;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_DisableTx\r
+//* \brief Disable transmit\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PDC_DisableTx (\r
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller\r
+{\r
+ pPDC->PDC_PTCR = AT91C_PDC_TXTDIS;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_DisableRx\r
+//* \brief Disable receive\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PDC_DisableRx (\r
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller\r
+{\r
+ pPDC->PDC_PTCR = AT91C_PDC_RXTDIS;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_IsTxEmpty\r
+//* \brief Test if the current transfer descriptor has been sent\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete\r
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller\r
+{\r
+ return !(pPDC->PDC_TCR);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_IsNextTxEmpty\r
+//* \brief Test if the next transfer descriptor has been moved to the current td\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete\r
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller\r
+{\r
+ return !(pPDC->PDC_TNCR);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_IsRxEmpty\r
+//* \brief Test if the current transfer descriptor has been filled\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete\r
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller\r
+{\r
+ return !(pPDC->PDC_RCR);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_IsNextRxEmpty\r
+//* \brief Test if the next transfer descriptor has been moved to the current td\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete\r
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller\r
+{\r
+ return !(pPDC->PDC_RNCR);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_Open\r
+//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PDC_Open (\r
+ AT91PS_PDC pPDC) // \arg pointer to a PDC controller\r
+{\r
+ //* Disable the RX and TX PDC transfer requests\r
+ AT91F_PDC_DisableRx(pPDC);\r
+ AT91F_PDC_DisableTx(pPDC);\r
+\r
+ //* Reset all Counter register Next buffer first\r
+ AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);\r
+ AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);\r
+ AT91F_PDC_SetTx(pPDC, (char *) 0, 0);\r
+ AT91F_PDC_SetRx(pPDC, (char *) 0, 0);\r
+\r
+ //* Enable the RX and TX PDC transfer requests\r
+ AT91F_PDC_EnableRx(pPDC);\r
+ AT91F_PDC_EnableTx(pPDC);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_Close\r
+//* \brief Close PDC: disable TX and RX reset transfer descriptors\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PDC_Close (\r
+ AT91PS_PDC pPDC) // \arg pointer to a PDC controller\r
+{\r
+ //* Disable the RX and TX PDC transfer requests\r
+ AT91F_PDC_DisableRx(pPDC);\r
+ AT91F_PDC_DisableTx(pPDC);\r
+\r
+ //* Reset all Counter register Next buffer first\r
+ AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);\r
+ AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);\r
+ AT91F_PDC_SetTx(pPDC, (char *) 0, 0);\r
+ AT91F_PDC_SetRx(pPDC, (char *) 0, 0);\r
+\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_SendFrame\r
+//* \brief Close PDC: disable TX and RX reset transfer descriptors\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PDC_SendFrame(\r
+ AT91PS_PDC pPDC,\r
+ char *pBuffer,\r
+ unsigned int szBuffer,\r
+ char *pNextBuffer,\r
+ unsigned int szNextBuffer )\r
+{\r
+ if (AT91F_PDC_IsTxEmpty(pPDC)) {\r
+ //* Buffer and next buffer can be initialized\r
+ AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer);\r
+ AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer);\r
+ return 2;\r
+ }\r
+ else if (AT91F_PDC_IsNextTxEmpty(pPDC)) {\r
+ //* Only one buffer can be initialized\r
+ AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer);\r
+ return 1;\r
+ }\r
+ else {\r
+ //* All buffer are in use...\r
+ return 0;\r
+ }\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PDC_ReceiveFrame\r
+//* \brief Close PDC: disable TX and RX reset transfer descriptors\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PDC_ReceiveFrame (\r
+ AT91PS_PDC pPDC,\r
+ char *pBuffer,\r
+ unsigned int szBuffer,\r
+ char *pNextBuffer,\r
+ unsigned int szNextBuffer )\r
+{\r
+ if (AT91F_PDC_IsRxEmpty(pPDC)) {\r
+ //* Buffer and next buffer can be initialized\r
+ AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer);\r
+ AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer);\r
+ return 2;\r
+ }\r
+ else if (AT91F_PDC_IsNextRxEmpty(pPDC)) {\r
+ //* Only one buffer can be initialized\r
+ AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer);\r
+ return 1;\r
+ }\r
+ else {\r
+ //* All buffer are in use...\r
+ return 0;\r
+ }\r
+}\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR DBGU\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_DBGU_InterruptEnable\r
+//* \brief Enable DBGU Interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_DBGU_InterruptEnable(\r
+ AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller\r
+ unsigned int flag) // \arg dbgu interrupt to be enabled\r
+{\r
+ pDbgu->DBGU_IER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_DBGU_InterruptDisable\r
+//* \brief Disable DBGU Interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_DBGU_InterruptDisable(\r
+ AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller\r
+ unsigned int flag) // \arg dbgu interrupt to be disabled\r
+{\r
+ pDbgu->DBGU_IDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_DBGU_GetInterruptMaskStatus\r
+//* \brief Return DBGU Interrupt Mask Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status\r
+ AT91PS_DBGU pDbgu) // \arg pointer to a DBGU controller\r
+{\r
+ return pDbgu->DBGU_IMR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_DBGU_IsInterruptMasked\r
+//* \brief Test if DBGU Interrupt is Masked\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_DBGU_IsInterruptMasked(\r
+ AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag);\r
+}\r
+\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR PIO\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_CfgPeriph\r
+//* \brief Enable pins to be drived by peripheral\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_CfgPeriph(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int periphAEnable, // \arg PERIPH A to enable\r
+ unsigned int periphBEnable) // \arg PERIPH B to enable\r
+\r
+{\r
+ pPio->PIO_ASR = periphAEnable;\r
+ pPio->PIO_BSR = periphBEnable;\r
+ pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_CfgOutput\r
+//* \brief Enable PIO in output mode\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_CfgOutput(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int pioEnable) // \arg PIO to be enabled\r
+{\r
+ pPio->PIO_PER = pioEnable; // Set in PIO mode\r
+ pPio->PIO_OER = pioEnable; // Configure in Output\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_CfgInput\r
+//* \brief Enable PIO in input mode\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_CfgInput(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int inputEnable) // \arg PIO to be enabled\r
+{\r
+ // Disable output\r
+ pPio->PIO_ODR = inputEnable;\r
+ pPio->PIO_PER = inputEnable;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_CfgOpendrain\r
+//* \brief Configure PIO in open drain\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_CfgOpendrain(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int multiDrvEnable) // \arg pio to be configured in open drain\r
+{\r
+ // Configure the multi-drive option\r
+ pPio->PIO_MDDR = ~multiDrvEnable;\r
+ pPio->PIO_MDER = multiDrvEnable;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_CfgPullup\r
+//* \brief Enable pullup on PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_CfgPullup(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int pullupEnable) // \arg enable pullup on PIO\r
+{\r
+ // Connect or not Pullup\r
+ pPio->PIO_PPUDR = ~pullupEnable;\r
+ pPio->PIO_PPUER = pullupEnable;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_CfgDirectDrive\r
+//* \brief Enable direct drive on PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_CfgDirectDrive(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int directDrive) // \arg PIO to be configured with direct drive\r
+\r
+{\r
+ // Configure the Direct Drive\r
+ pPio->PIO_OWDR = ~directDrive;\r
+ pPio->PIO_OWER = directDrive;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_CfgInputFilter\r
+//* \brief Enable input filter on input PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_CfgInputFilter(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int inputFilter) // \arg PIO to be configured with input filter\r
+\r
+{\r
+ // Configure the Direct Drive\r
+ pPio->PIO_IFDR = ~inputFilter;\r
+ pPio->PIO_IFER = inputFilter;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_GetInput\r
+//* \brief Return PIO input value\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PIO_GetInput( // \return PIO input\r
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller\r
+{\r
+ return pPio->PIO_PDSR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_IsInputSet\r
+//* \brief Test if PIO is input flag is active\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PIO_IsInputSet(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_PIO_GetInput(pPio) & flag);\r
+}\r
+\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_SetOutput\r
+//* \brief Set to 1 output PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_SetOutput(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg output to be set\r
+{\r
+ pPio->PIO_SODR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_ClearOutput\r
+//* \brief Set to 0 output PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_ClearOutput(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg output to be cleared\r
+{\r
+ pPio->PIO_CODR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_ForceOutput\r
+//* \brief Force output when Direct drive option is enabled\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_ForceOutput(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg output to be forced\r
+{\r
+ pPio->PIO_ODSR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_Enable\r
+//* \brief Enable PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_Enable(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg pio to be enabled\r
+{\r
+ pPio->PIO_PER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_Disable\r
+//* \brief Disable PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_Disable(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg pio to be disabled\r
+{\r
+ pPio->PIO_PDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_GetStatus\r
+//* \brief Return PIO Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status\r
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller\r
+{\r
+ return pPio->PIO_PSR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_IsSet\r
+//* \brief Test if PIO is Set\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PIO_IsSet(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_PIO_GetStatus(pPio) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_OutputEnable\r
+//* \brief Output Enable PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_OutputEnable(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg pio output to be enabled\r
+{\r
+ pPio->PIO_OER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_OutputDisable\r
+//* \brief Output Enable PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_OutputDisable(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg pio output to be disabled\r
+{\r
+ pPio->PIO_ODR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_GetOutputStatus\r
+//* \brief Return PIO Output Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status\r
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller\r
+{\r
+ return pPio->PIO_OSR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_IsOuputSet\r
+//* \brief Test if PIO Output is Set\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PIO_IsOutputSet(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_PIO_GetOutputStatus(pPio) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_InputFilterEnable\r
+//* \brief Input Filter Enable PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_InputFilterEnable(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg pio input filter to be enabled\r
+{\r
+ pPio->PIO_IFER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_InputFilterDisable\r
+//* \brief Input Filter Disable PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_InputFilterDisable(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg pio input filter to be disabled\r
+{\r
+ pPio->PIO_IFDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_GetInputFilterStatus\r
+//* \brief Return PIO Input Filter Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status\r
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller\r
+{\r
+ return pPio->PIO_IFSR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_IsInputFilterSet\r
+//* \brief Test if PIO Input filter is Set\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PIO_IsInputFilterSet(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_PIO_GetInputFilterStatus(pPio) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_GetOutputDataStatus\r
+//* \brief Return PIO Output Data Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status\r
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller\r
+{\r
+ return pPio->PIO_ODSR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_InterruptEnable\r
+//* \brief Enable PIO Interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_InterruptEnable(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg pio interrupt to be enabled\r
+{\r
+ pPio->PIO_IER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_InterruptDisable\r
+//* \brief Disable PIO Interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_InterruptDisable(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg pio interrupt to be disabled\r
+{\r
+ pPio->PIO_IDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_GetInterruptMaskStatus\r
+//* \brief Return PIO Interrupt Mask Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status\r
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller\r
+{\r
+ return pPio->PIO_IMR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_GetInterruptStatus\r
+//* \brief Return PIO Interrupt Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status\r
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller\r
+{\r
+ return pPio->PIO_ISR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_IsInterruptMasked\r
+//* \brief Test if PIO Interrupt is Masked\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PIO_IsInterruptMasked(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_IsInterruptSet\r
+//* \brief Test if PIO Interrupt is Set\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PIO_IsInterruptSet(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_PIO_GetInterruptStatus(pPio) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_MultiDriverEnable\r
+//* \brief Multi Driver Enable PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_MultiDriverEnable(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg pio to be enabled\r
+{\r
+ pPio->PIO_MDER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_MultiDriverDisable\r
+//* \brief Multi Driver Disable PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_MultiDriverDisable(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg pio to be disabled\r
+{\r
+ pPio->PIO_MDDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_GetMultiDriverStatus\r
+//* \brief Return PIO Multi Driver Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status\r
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller\r
+{\r
+ return pPio->PIO_MDSR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_IsMultiDriverSet\r
+//* \brief Test if PIO MultiDriver is Set\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PIO_IsMultiDriverSet(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_A_RegisterSelection\r
+//* \brief PIO A Register Selection\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_A_RegisterSelection(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg pio A register selection\r
+{\r
+ pPio->PIO_ASR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_B_RegisterSelection\r
+//* \brief PIO B Register Selection\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_B_RegisterSelection(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg pio B register selection\r
+{\r
+ pPio->PIO_BSR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_Get_AB_RegisterStatus\r
+//* \brief Return PIO Interrupt Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status\r
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller\r
+{\r
+ return pPio->PIO_ABSR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_IsAB_RegisterSet\r
+//* \brief Test if PIO AB Register is Set\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PIO_IsAB_RegisterSet(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_OutputWriteEnable\r
+//* \brief Output Write Enable PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_OutputWriteEnable(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg pio output write to be enabled\r
+{\r
+ pPio->PIO_OWER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_OutputWriteDisable\r
+//* \brief Output Write Disable PIO\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIO_OutputWriteDisable(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg pio output write to be disabled\r
+{\r
+ pPio->PIO_OWDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_GetOutputWriteStatus\r
+//* \brief Return PIO Output Write Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status\r
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller\r
+{\r
+ return pPio->PIO_OWSR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_IsOutputWriteSet\r
+//* \brief Test if PIO OutputWrite is Set\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PIO_IsOutputWriteSet(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_GetCfgPullup\r
+//* \brief Return PIO Configuration Pullup\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup\r
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller\r
+{\r
+ return pPio->PIO_PPUSR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_IsOutputDataStatusSet\r
+//* \brief Test if PIO Output Data Status is Set\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PIO_IsOutputDataStatusSet(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_PIO_GetOutputDataStatus(pPio) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIO_IsCfgPullupStatusSet\r
+//* \brief Test if PIO Configuration Pullup Status is Set\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_PIO_IsCfgPullupStatusSet(\r
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (~AT91F_PIO_GetCfgPullup(pPio) & flag);\r
+}\r
+\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR PMC\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_CfgSysClkEnableReg\r
+//* \brief Configure the System Clock Enable Register of the PMC controller\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PMC_CfgSysClkEnableReg (\r
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller\r
+ unsigned int mode)\r
+{\r
+ //* Write to the SCER register\r
+ pPMC->PMC_SCER = mode;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_CfgSysClkDisableReg\r
+//* \brief Configure the System Clock Disable Register of the PMC controller\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PMC_CfgSysClkDisableReg (\r
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller\r
+ unsigned int mode)\r
+{\r
+ //* Write to the SCDR register\r
+ pPMC->PMC_SCDR = mode;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_GetSysClkStatusReg\r
+//* \brief Return the System Clock Status Register of the PMC controller\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PMC_GetSysClkStatusReg (\r
+ AT91PS_PMC pPMC // pointer to a CAN controller\r
+ )\r
+{\r
+ return pPMC->PMC_SCSR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_EnablePeriphClock\r
+//* \brief Enable peripheral clock\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PMC_EnablePeriphClock (\r
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller\r
+ unsigned int periphIds) // \arg IDs of peripherals to enable\r
+{\r
+ pPMC->PMC_PCER = periphIds;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_DisablePeriphClock\r
+//* \brief Disable peripheral clock\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PMC_DisablePeriphClock (\r
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller\r
+ unsigned int periphIds) // \arg IDs of peripherals to enable\r
+{\r
+ pPMC->PMC_PCDR = periphIds;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_GetPeriphClock\r
+//* \brief Get peripheral clock status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PMC_GetPeriphClock (\r
+ AT91PS_PMC pPMC) // \arg pointer to PMC controller\r
+{\r
+ return pPMC->PMC_PCSR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CKGR_CfgMainOscillatorReg\r
+//* \brief Cfg the main oscillator\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CKGR_CfgMainOscillatorReg (\r
+ AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller\r
+ unsigned int mode)\r
+{\r
+ pCKGR->CKGR_MOR = mode;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CKGR_GetMainOscillatorReg\r
+//* \brief Cfg the main oscillator\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CKGR_GetMainOscillatorReg (\r
+ AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller\r
+{\r
+ return pCKGR->CKGR_MOR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CKGR_EnableMainOscillator\r
+//* \brief Enable the main oscillator\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CKGR_EnableMainOscillator(\r
+ AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller\r
+{\r
+ pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CKGR_DisableMainOscillator\r
+//* \brief Disable the main oscillator\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CKGR_DisableMainOscillator (\r
+ AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller\r
+{\r
+ pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CKGR_CfgMainOscStartUpTime\r
+//* \brief Cfg MOR Register according to the main osc startup time\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CKGR_CfgMainOscStartUpTime (\r
+ AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller\r
+ unsigned int startup_time, // \arg main osc startup time in microsecond (us)\r
+ unsigned int slowClock) // \arg slowClock in Hz\r
+{\r
+ pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT;\r
+ pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CKGR_GetMainClockFreqReg\r
+//* \brief Cfg the main oscillator\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CKGR_GetMainClockFreqReg (\r
+ AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller\r
+{\r
+ return pCKGR->CKGR_MCFR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CKGR_GetMainClock\r
+//* \brief Return Main clock in Hz\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CKGR_GetMainClock (\r
+ AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller\r
+ unsigned int slowClock) // \arg slowClock in Hz\r
+{\r
+ return ((pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF) * slowClock) >> 4;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_CfgMCKReg\r
+//* \brief Cfg Master Clock Register\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PMC_CfgMCKReg (\r
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller\r
+ unsigned int mode)\r
+{\r
+ pPMC->PMC_MCKR = mode;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_GetMCKReg\r
+//* \brief Return Master Clock Register\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PMC_GetMCKReg(\r
+ AT91PS_PMC pPMC) // \arg pointer to PMC controller\r
+{\r
+ return pPMC->PMC_MCKR;\r
+}\r
+\r
+//*------------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_GetMasterClock\r
+//* \brief Return master clock in Hz which correponds to processor clock for ARM7\r
+//*------------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PMC_GetMasterClock (\r
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller\r
+ AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller\r
+ unsigned int slowClock) // \arg slowClock in Hz\r
+{\r
+ unsigned int reg = pPMC->PMC_MCKR;\r
+ unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2));\r
+ unsigned int pllDivider, pllMultiplier;\r
+\r
+ switch (reg & AT91C_PMC_CSS) {\r
+ case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected\r
+ return slowClock / prescaler;\r
+ case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected\r
+ return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler;\r
+ case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected\r
+ reg = pCKGR->CKGR_PLLR;\r
+ pllDivider = (reg & AT91C_CKGR_DIV);\r
+ pllMultiplier = ((reg & AT91C_CKGR_MUL) >> 16) + 1;\r
+ return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler;\r
+ }\r
+ return 0;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_EnablePCK\r
+//* \brief Enable peripheral clock\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PMC_EnablePCK (\r
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller\r
+ unsigned int pck, // \arg Peripheral clock identifier 0 .. 7\r
+ unsigned int mode)\r
+{\r
+ pPMC->PMC_PCKR[pck] = mode;\r
+ pPMC->PMC_SCER = (1 << pck) << 8;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_DisablePCK\r
+//* \brief Enable peripheral clock\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PMC_DisablePCK (\r
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller\r
+ unsigned int pck) // \arg Peripheral clock identifier 0 .. 7\r
+{\r
+ pPMC->PMC_SCDR = (1 << pck) << 8;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_EnableIt\r
+//* \brief Enable PMC interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PMC_EnableIt (\r
+ AT91PS_PMC pPMC, // pointer to a PMC controller\r
+ unsigned int flag) // IT to be enabled\r
+{\r
+ //* Write to the IER register\r
+ pPMC->PMC_IER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_DisableIt\r
+//* \brief Disable PMC interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PMC_DisableIt (\r
+ AT91PS_PMC pPMC, // pointer to a PMC controller\r
+ unsigned int flag) // IT to be disabled\r
+{\r
+ //* Write to the IDR register\r
+ pPMC->PMC_IDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_GetStatus\r
+//* \brief Return PMC Interrupt Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status\r
+ AT91PS_PMC pPMC) // pointer to a PMC controller\r
+{\r
+ return pPMC->PMC_SR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_GetInterruptMaskStatus\r
+//* \brief Return PMC Interrupt Mask Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status\r
+ AT91PS_PMC pPMC) // pointer to a PMC controller\r
+{\r
+ return pPMC->PMC_IMR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_IsInterruptMasked\r
+//* \brief Test if PMC Interrupt is Masked\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PMC_IsInterruptMasked(\r
+ AT91PS_PMC pPMC, // \arg pointer to a PMC controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_IsStatusSet\r
+//* \brief Test if PMC Status is Set\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PMC_IsStatusSet(\r
+ AT91PS_PMC pPMC, // \arg pointer to a PMC controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_PMC_GetStatus(pPMC) & flag);\r
+}/* *****************************************************************************\r
+ SOFTWARE API FOR RSTC\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_RSTSoftReset\r
+//* \brief Start Software Reset\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_RSTSoftReset(\r
+ AT91PS_RSTC pRSTC,\r
+ unsigned int reset)\r
+{\r
+ pRSTC->RSTC_RCR = (0xA5000000 | reset);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_RSTSetMode\r
+//* \brief Set Reset Mode\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_RSTSetMode(\r
+ AT91PS_RSTC pRSTC,\r
+ unsigned int mode)\r
+{\r
+ pRSTC->RSTC_RMR = (0xA5000000 | mode);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_RSTGetMode\r
+//* \brief Get Reset Mode\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_RSTGetMode(\r
+ AT91PS_RSTC pRSTC)\r
+{\r
+ return (pRSTC->RSTC_RMR);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_RSTGetStatus\r
+//* \brief Get Reset Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_RSTGetStatus(\r
+ AT91PS_RSTC pRSTC)\r
+{\r
+ return (pRSTC->RSTC_RSR);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_RSTIsSoftRstActive\r
+//* \brief Return !=0 if software reset is still not completed\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_RSTIsSoftRstActive(\r
+ AT91PS_RSTC pRSTC)\r
+{\r
+ return ((pRSTC->RSTC_RSR) & AT91C_RSTC_SRCMP);\r
+}\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR RTTC\r
+ ***************************************************************************** */\r
+//*--------------------------------------------------------------------------------------\r
+//* \fn AT91F_SetRTT_TimeBase()\r
+//* \brief Set the RTT prescaler according to the TimeBase in ms\r
+//*--------------------------------------------------------------------------------------\r
+__inline unsigned int AT91F_RTTSetTimeBase(\r
+ AT91PS_RTTC pRTTC,\r
+ unsigned int ms)\r
+{\r
+ if (ms > 2000)\r
+ return 1; // AT91C_TIME_OUT_OF_RANGE\r
+ pRTTC->RTTC_RTMR &= ~0xFFFF; \r
+ pRTTC->RTTC_RTMR |= (((ms << 15) /1000) & 0xFFFF); \r
+ return 0;\r
+}\r
+\r
+//*--------------------------------------------------------------------------------------\r
+//* \fn AT91F_RTTSetPrescaler()\r
+//* \brief Set the new prescaler value\r
+//*--------------------------------------------------------------------------------------\r
+__inline unsigned int AT91F_RTTSetPrescaler(\r
+ AT91PS_RTTC pRTTC,\r
+ unsigned int rtpres)\r
+{\r
+ pRTTC->RTTC_RTMR &= ~0xFFFF; \r
+ pRTTC->RTTC_RTMR |= (rtpres & 0xFFFF); \r
+ return (pRTTC->RTTC_RTMR);\r
+}\r
+\r
+//*--------------------------------------------------------------------------------------\r
+//* \fn AT91F_RTTRestart()\r
+//* \brief Restart the RTT prescaler\r
+//*--------------------------------------------------------------------------------------\r
+__inline void AT91F_RTTRestart(\r
+ AT91PS_RTTC pRTTC)\r
+{\r
+ pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST; \r
+}\r
+\r
+\r
+//*--------------------------------------------------------------------------------------\r
+//* \fn AT91F_RTT_SetAlarmINT()\r
+//* \brief Enable RTT Alarm Interrupt\r
+//*--------------------------------------------------------------------------------------\r
+__inline void AT91F_RTTSetAlarmINT(\r
+ AT91PS_RTTC pRTTC)\r
+{\r
+ pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN;\r
+}\r
+\r
+//*--------------------------------------------------------------------------------------\r
+//* \fn AT91F_RTT_ClearAlarmINT()\r
+//* \brief Disable RTT Alarm Interrupt\r
+//*--------------------------------------------------------------------------------------\r
+__inline void AT91F_RTTClearAlarmINT(\r
+ AT91PS_RTTC pRTTC)\r
+{\r
+ pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN;\r
+}\r
+\r
+//*--------------------------------------------------------------------------------------\r
+//* \fn AT91F_RTT_SetRttIncINT()\r
+//* \brief Enable RTT INC Interrupt\r
+//*--------------------------------------------------------------------------------------\r
+__inline void AT91F_RTTSetRttIncINT(\r
+ AT91PS_RTTC pRTTC)\r
+{\r
+ pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN;\r
+}\r
+\r
+//*--------------------------------------------------------------------------------------\r
+//* \fn AT91F_RTT_ClearRttIncINT()\r
+//* \brief Disable RTT INC Interrupt\r
+//*--------------------------------------------------------------------------------------\r
+__inline void AT91F_RTTClearRttIncINT(\r
+ AT91PS_RTTC pRTTC)\r
+{\r
+ pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN;\r
+}\r
+\r
+//*--------------------------------------------------------------------------------------\r
+//* \fn AT91F_RTT_SetAlarmValue()\r
+//* \brief Set RTT Alarm Value\r
+//*--------------------------------------------------------------------------------------\r
+__inline void AT91F_RTTSetAlarmValue(\r
+ AT91PS_RTTC pRTTC, unsigned int alarm)\r
+{\r
+ pRTTC->RTTC_RTAR = alarm;\r
+}\r
+\r
+//*--------------------------------------------------------------------------------------\r
+//* \fn AT91F_RTT_GetAlarmValue()\r
+//* \brief Get RTT Alarm Value\r
+//*--------------------------------------------------------------------------------------\r
+__inline unsigned int AT91F_RTTGetAlarmValue(\r
+ AT91PS_RTTC pRTTC)\r
+{\r
+ return(pRTTC->RTTC_RTAR);\r
+}\r
+\r
+//*--------------------------------------------------------------------------------------\r
+//* \fn AT91F_RTTGetStatus()\r
+//* \brief Read the RTT status\r
+//*--------------------------------------------------------------------------------------\r
+__inline unsigned int AT91F_RTTGetStatus(\r
+ AT91PS_RTTC pRTTC)\r
+{\r
+ return(pRTTC->RTTC_RTSR);\r
+}\r
+\r
+//*--------------------------------------------------------------------------------------\r
+//* \fn AT91F_RTT_ReadValue()\r
+//* \brief Read the RTT value\r
+//*--------------------------------------------------------------------------------------\r
+__inline unsigned int AT91F_RTTReadValue(\r
+ AT91PS_RTTC pRTTC)\r
+{\r
+ register volatile unsigned int val1,val2;\r
+ do\r
+ {\r
+ val1 = pRTTC->RTTC_RTVR;\r
+ val2 = pRTTC->RTTC_RTVR;\r
+ } \r
+ while(val1 != val2);\r
+ return(val1);\r
+}\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR PITC\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PITInit\r
+//* \brief System timer init : period in µsecond, system clock freq in MHz\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PITInit(\r
+ AT91PS_PITC pPITC,\r
+ unsigned int period,\r
+ unsigned int pit_frequency)\r
+{\r
+ pPITC->PITC_PIMR = period? (period * pit_frequency + 8) >> 4 : 0; // +8 to avoid %10 and /10\r
+ pPITC->PITC_PIMR |= AT91C_PITC_PITEN; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PITSetPIV\r
+//* \brief Set the PIT Periodic Interval Value\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PITSetPIV(\r
+ AT91PS_PITC pPITC,\r
+ unsigned int piv)\r
+{\r
+ pPITC->PITC_PIMR = piv | (pPITC->PITC_PIMR & (AT91C_PITC_PITEN | AT91C_PITC_PITIEN));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PITEnableInt\r
+//* \brief Enable PIT periodic interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PITEnableInt(\r
+ AT91PS_PITC pPITC)\r
+{\r
+ pPITC->PITC_PIMR |= AT91C_PITC_PITIEN; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PITDisableInt\r
+//* \brief Disable PIT periodic interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PITDisableInt(\r
+ AT91PS_PITC pPITC)\r
+{\r
+ pPITC->PITC_PIMR &= ~AT91C_PITC_PITIEN; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PITGetMode\r
+//* \brief Read PIT mode register\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PITGetMode(\r
+ AT91PS_PITC pPITC)\r
+{\r
+ return(pPITC->PITC_PIMR);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PITGetStatus\r
+//* \brief Read PIT status register\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PITGetStatus(\r
+ AT91PS_PITC pPITC)\r
+{\r
+ return(pPITC->PITC_PISR);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PITGetPIIR\r
+//* \brief Read PIT CPIV and PICNT without ressetting the counters\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PITGetPIIR(\r
+ AT91PS_PITC pPITC)\r
+{\r
+ return(pPITC->PITC_PIIR);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PITGetPIVR\r
+//* \brief Read System timer CPIV and PICNT without ressetting the counters\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PITGetPIVR(\r
+ AT91PS_PITC pPITC)\r
+{\r
+ return(pPITC->PITC_PIVR);\r
+}\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR WDTC\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_WDTSetMode\r
+//* \brief Set Watchdog Mode Register\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_WDTSetMode(\r
+ AT91PS_WDTC pWDTC,\r
+ unsigned int Mode)\r
+{\r
+ pWDTC->WDTC_WDMR = Mode;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_WDTRestart\r
+//* \brief Restart Watchdog\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_WDTRestart(\r
+ AT91PS_WDTC pWDTC)\r
+{\r
+ pWDTC->WDTC_WDCR = 0xA5000001;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_WDTSGettatus\r
+//* \brief Get Watchdog Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_WDTSGettatus(\r
+ AT91PS_WDTC pWDTC)\r
+{\r
+ return(pWDTC->WDTC_WDSR & 0x3);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_WDTGetPeriod\r
+//* \brief Translate ms into Watchdog Compatible value\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_WDTGetPeriod(unsigned int ms)\r
+{\r
+ if ((ms < 4) || (ms > 16000))\r
+ return 0;\r
+ return((ms << 8) / 1000);\r
+}\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR VREG\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_VREG_Enable_LowPowerMode\r
+//* \brief Enable VREG Low Power Mode\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_VREG_Enable_LowPowerMode(\r
+ AT91PS_VREG pVREG)\r
+{\r
+ pVREG->VREG_MR |= AT91C_VREG_PSTDBY; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_VREG_Disable_LowPowerMode\r
+//* \brief Disable VREG Low Power Mode\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_VREG_Disable_LowPowerMode(\r
+ AT91PS_VREG pVREG)\r
+{\r
+ pVREG->VREG_MR &= ~AT91C_VREG_PSTDBY; \r
+}/* *****************************************************************************\r
+ SOFTWARE API FOR MC\r
+ ***************************************************************************** */\r
+\r
+#define AT91C_MC_CORRECT_KEY ((unsigned int) 0x5A << 24) // (MC) Correct Protect Key\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_MC_Remap\r
+//* \brief Make Remap\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_MC_Remap (void) //\r
+{\r
+ AT91PS_MC pMC = (AT91PS_MC) AT91C_BASE_MC;\r
+\r
+ pMC->MC_RCR = AT91C_MC_RCB;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_MC_EFC_CfgModeReg\r
+//* \brief Configure the EFC Mode Register of the MC controller\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_MC_EFC_CfgModeReg (\r
+ AT91PS_MC pMC, // pointer to a MC controller\r
+ unsigned int mode) // mode register\r
+{\r
+ // Write to the FMR register\r
+ pMC->MC_FMR = mode;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_MC_EFC_GetModeReg\r
+//* \brief Return MC EFC Mode Regsiter\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_MC_EFC_GetModeReg(\r
+ AT91PS_MC pMC) // pointer to a MC controller\r
+{\r
+ return pMC->MC_FMR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_MC_EFC_ComputeFMCN\r
+//* \brief Return MC EFC Mode Regsiter\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_MC_EFC_ComputeFMCN(\r
+ int master_clock) // master clock in Hz\r
+{\r
+ return (master_clock/1000000 +2);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_MC_EFC_PerformCmd\r
+//* \brief Perform EFC Command\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_MC_EFC_PerformCmd (\r
+ AT91PS_MC pMC, // pointer to a MC controller\r
+ unsigned int transfer_cmd)\r
+{\r
+ pMC->MC_FCR = transfer_cmd; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_MC_EFC_GetStatus\r
+//* \brief Return MC EFC Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_MC_EFC_GetStatus(\r
+ AT91PS_MC pMC) // pointer to a MC controller\r
+{\r
+ return pMC->MC_FSR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_MC_EFC_IsInterruptMasked\r
+//* \brief Test if EFC MC Interrupt is Masked\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_MC_EFC_IsInterruptMasked(\r
+ AT91PS_MC pMC, // \arg pointer to a MC controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_MC_EFC_GetModeReg(pMC) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_MC_EFC_IsInterruptSet\r
+//* \brief Test if EFC MC Interrupt is Set\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_MC_EFC_IsInterruptSet(\r
+ AT91PS_MC pMC, // \arg pointer to a MC controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_MC_EFC_GetStatus(pMC) & flag);\r
+}\r
+\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR SPI\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_Open\r
+//* \brief Open a SPI Port\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_SPI_Open (\r
+ const unsigned int null) // \arg\r
+{\r
+ /* NOT DEFINED AT THIS MOMENT */\r
+ return ( 0 );\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_CfgCs\r
+//* \brief Configure SPI chip select register\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SPI_CfgCs (\r
+ AT91PS_SPI pSPI, // pointer to a SPI controller\r
+ int cs, // SPI cs number (0 to 3)\r
+ int val) // chip select register\r
+{\r
+ //* Write to the CSR register\r
+ *(pSPI->SPI_CSR + cs) = val;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_EnableIt\r
+//* \brief Enable SPI interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SPI_EnableIt (\r
+ AT91PS_SPI pSPI, // pointer to a SPI controller\r
+ unsigned int flag) // IT to be enabled\r
+{\r
+ //* Write to the IER register\r
+ pSPI->SPI_IER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_DisableIt\r
+//* \brief Disable SPI interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SPI_DisableIt (\r
+ AT91PS_SPI pSPI, // pointer to a SPI controller\r
+ unsigned int flag) // IT to be disabled\r
+{\r
+ //* Write to the IDR register\r
+ pSPI->SPI_IDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_Reset\r
+//* \brief Reset the SPI controller\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SPI_Reset (\r
+ AT91PS_SPI pSPI // pointer to a SPI controller\r
+ )\r
+{\r
+ //* Write to the CR register\r
+ pSPI->SPI_CR = AT91C_SPI_SWRST;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_Enable\r
+//* \brief Enable the SPI controller\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SPI_Enable (\r
+ AT91PS_SPI pSPI // pointer to a SPI controller\r
+ )\r
+{\r
+ //* Write to the CR register\r
+ pSPI->SPI_CR = AT91C_SPI_SPIEN;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_Disable\r
+//* \brief Disable the SPI controller\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SPI_Disable (\r
+ AT91PS_SPI pSPI // pointer to a SPI controller\r
+ )\r
+{\r
+ //* Write to the CR register\r
+ pSPI->SPI_CR = AT91C_SPI_SPIDIS;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_CfgMode\r
+//* \brief Enable the SPI controller\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SPI_CfgMode (\r
+ AT91PS_SPI pSPI, // pointer to a SPI controller\r
+ int mode) // mode register\r
+{\r
+ //* Write to the MR register\r
+ pSPI->SPI_MR = mode;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_CfgPCS\r
+//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SPI_CfgPCS (\r
+ AT91PS_SPI pSPI, // pointer to a SPI controller\r
+ char PCS_Device) // PCS of the Device\r
+{ \r
+ //* Write to the MR register\r
+ pSPI->SPI_MR &= 0xFFF0FFFF;\r
+ pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS );\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_ReceiveFrame\r
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_SPI_ReceiveFrame (\r
+ AT91PS_SPI pSPI,\r
+ char *pBuffer,\r
+ unsigned int szBuffer,\r
+ char *pNextBuffer,\r
+ unsigned int szNextBuffer )\r
+{\r
+ return AT91F_PDC_ReceiveFrame(\r
+ (AT91PS_PDC) &(pSPI->SPI_RPR),\r
+ pBuffer,\r
+ szBuffer,\r
+ pNextBuffer,\r
+ szNextBuffer);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_SendFrame\r
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_SPI_SendFrame(\r
+ AT91PS_SPI pSPI,\r
+ char *pBuffer,\r
+ unsigned int szBuffer,\r
+ char *pNextBuffer,\r
+ unsigned int szNextBuffer )\r
+{\r
+ return AT91F_PDC_SendFrame(\r
+ (AT91PS_PDC) &(pSPI->SPI_RPR),\r
+ pBuffer,\r
+ szBuffer,\r
+ pNextBuffer,\r
+ szNextBuffer);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_Close\r
+//* \brief Close SPI: disable IT disable transfert, close PDC\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SPI_Close (\r
+ AT91PS_SPI pSPI) // \arg pointer to a SPI controller\r
+{\r
+ //* Reset all the Chip Select register\r
+ pSPI->SPI_CSR[0] = 0 ;\r
+ pSPI->SPI_CSR[1] = 0 ;\r
+ pSPI->SPI_CSR[2] = 0 ;\r
+ pSPI->SPI_CSR[3] = 0 ;\r
+\r
+ //* Reset the SPI mode\r
+ pSPI->SPI_MR = 0 ;\r
+\r
+ //* Disable all interrupts\r
+ pSPI->SPI_IDR = 0xFFFFFFFF ;\r
+\r
+ //* Abort the Peripheral Data Transfers\r
+ AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR));\r
+\r
+ //* Disable receiver and transmitter and stop any activity immediately\r
+ pSPI->SPI_CR = AT91C_SPI_SPIDIS;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_PutChar\r
+//* \brief Send a character,does not check if ready to send\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SPI_PutChar (\r
+ AT91PS_SPI pSPI,\r
+ unsigned int character,\r
+ unsigned int cs_number )\r
+{\r
+ unsigned int value_for_cs;\r
+ value_for_cs = (~(1 << cs_number)) & 0xF; //Place a zero among a 4 ONEs number\r
+ pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_GetChar\r
+//* \brief Receive a character,does not check if a character is available\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_SPI_GetChar (\r
+ const AT91PS_SPI pSPI)\r
+{\r
+ return((pSPI->SPI_RDR) & 0xFFFF);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_GetInterruptMaskStatus\r
+//* \brief Return SPI Interrupt Mask Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status\r
+ AT91PS_SPI pSpi) // \arg pointer to a SPI controller\r
+{\r
+ return pSpi->SPI_IMR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI_IsInterruptMasked\r
+//* \brief Test if SPI Interrupt is Masked\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_SPI_IsInterruptMasked(\r
+ AT91PS_SPI pSpi, // \arg pointer to a SPI controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag);\r
+}\r
+\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR USART\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_Baudrate\r
+//* \brief Calculate the baudrate\r
+//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity\r
+#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \\r
+ AT91C_US_NBSTOP_1_BIT + \\r
+ AT91C_US_PAR_NONE + \\r
+ AT91C_US_CHRL_8_BITS + \\r
+ AT91C_US_CLKS_CLOCK )\r
+\r
+//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity\r
+#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \\r
+ AT91C_US_NBSTOP_1_BIT + \\r
+ AT91C_US_PAR_NONE + \\r
+ AT91C_US_CHRL_8_BITS + \\r
+ AT91C_US_CLKS_EXT )\r
+\r
+//* Standard Synchronous Mode : 8 bits , 1 stop , no parity\r
+#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \\r
+ AT91C_US_USMODE_NORMAL + \\r
+ AT91C_US_NBSTOP_1_BIT + \\r
+ AT91C_US_PAR_NONE + \\r
+ AT91C_US_CHRL_8_BITS + \\r
+ AT91C_US_CLKS_CLOCK )\r
+\r
+//* SCK used Label\r
+#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT)\r
+\r
+//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity\r
+#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \\r
+ AT91C_US_CLKS_CLOCK +\\r
+ AT91C_US_NBSTOP_1_BIT + \\r
+ AT91C_US_PAR_EVEN + \\r
+ AT91C_US_CHRL_8_BITS + \\r
+ AT91C_US_CKLO +\\r
+ AT91C_US_OVER)\r
+\r
+//* Standard IRDA mode\r
+#define AT91C_US_ASYNC_IRDA_MODE ( AT91C_US_USMODE_IRDA + \\r
+ AT91C_US_NBSTOP_1_BIT + \\r
+ AT91C_US_PAR_NONE + \\r
+ AT91C_US_CHRL_8_BITS + \\r
+ AT91C_US_CLKS_CLOCK )\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_Baudrate\r
+//* \brief Caluculate baud_value according to the main clock and the baud rate\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_US_Baudrate (\r
+ const unsigned int main_clock, // \arg peripheral clock\r
+ const unsigned int baud_rate) // \arg UART baudrate\r
+{\r
+ unsigned int baud_value = ((main_clock*10)/(baud_rate * 16));\r
+ if ((baud_value % 10) >= 5)\r
+ baud_value = (baud_value / 10) + 1;\r
+ else\r
+ baud_value /= 10;\r
+ return baud_value;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_SetBaudrate\r
+//* \brief Set the baudrate according to the CPU clock\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US_SetBaudrate (\r
+ AT91PS_USART pUSART, // \arg pointer to a USART controller\r
+ unsigned int mainClock, // \arg peripheral clock\r
+ unsigned int speed) // \arg UART baudrate\r
+{\r
+ //* Define the baud rate divisor register\r
+ pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_SetTimeguard\r
+//* \brief Set USART timeguard\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US_SetTimeguard (\r
+ AT91PS_USART pUSART, // \arg pointer to a USART controller\r
+ unsigned int timeguard) // \arg timeguard value\r
+{\r
+ //* Write the Timeguard Register\r
+ pUSART->US_TTGR = timeguard ;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_EnableIt\r
+//* \brief Enable USART IT\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US_EnableIt (\r
+ AT91PS_USART pUSART, // \arg pointer to a USART controller\r
+ unsigned int flag) // \arg IT to be enabled\r
+{\r
+ //* Write to the IER register\r
+ pUSART->US_IER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_DisableIt\r
+//* \brief Disable USART IT\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US_DisableIt (\r
+ AT91PS_USART pUSART, // \arg pointer to a USART controller\r
+ unsigned int flag) // \arg IT to be disabled\r
+{\r
+ //* Write to the IER register\r
+ pUSART->US_IDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_Configure\r
+//* \brief Configure USART\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US_Configure (\r
+ AT91PS_USART pUSART, // \arg pointer to a USART controller\r
+ unsigned int mainClock, // \arg peripheral clock\r
+ unsigned int mode , // \arg mode Register to be programmed\r
+ unsigned int baudRate , // \arg baudrate to be programmed\r
+ unsigned int timeguard ) // \arg timeguard to be programmed\r
+{\r
+ //* Disable interrupts\r
+ pUSART->US_IDR = (unsigned int) -1;\r
+\r
+ //* Reset receiver and transmitter\r
+ pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ;\r
+\r
+ //* Define the baud rate divisor register\r
+ AT91F_US_SetBaudrate(pUSART, mainClock, baudRate);\r
+\r
+ //* Write the Timeguard Register\r
+ AT91F_US_SetTimeguard(pUSART, timeguard);\r
+\r
+ //* Clear Transmit and Receive Counters\r
+ AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR));\r
+\r
+ //* Define the USART mode\r
+ pUSART->US_MR = mode ;\r
+\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_EnableRx\r
+//* \brief Enable receiving characters\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US_EnableRx (\r
+ AT91PS_USART pUSART) // \arg pointer to a USART controller\r
+{\r
+ //* Enable receiver\r
+ pUSART->US_CR = AT91C_US_RXEN;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_EnableTx\r
+//* \brief Enable sending characters\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US_EnableTx (\r
+ AT91PS_USART pUSART) // \arg pointer to a USART controller\r
+{\r
+ //* Enable transmitter\r
+ pUSART->US_CR = AT91C_US_TXEN;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_ResetRx\r
+//* \brief Reset Receiver and re-enable it\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US_ResetRx (\r
+ AT91PS_USART pUSART) // \arg pointer to a USART controller\r
+{\r
+ //* Reset receiver\r
+ pUSART->US_CR = AT91C_US_RSTRX;\r
+ //* Re-Enable receiver\r
+ pUSART->US_CR = AT91C_US_RXEN;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_ResetTx\r
+//* \brief Reset Transmitter and re-enable it\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US_ResetTx (\r
+ AT91PS_USART pUSART) // \arg pointer to a USART controller\r
+{\r
+ //* Reset transmitter\r
+ pUSART->US_CR = AT91C_US_RSTTX;\r
+ //* Enable transmitter\r
+ pUSART->US_CR = AT91C_US_TXEN;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_DisableRx\r
+//* \brief Disable Receiver\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US_DisableRx (\r
+ AT91PS_USART pUSART) // \arg pointer to a USART controller\r
+{\r
+ //* Disable receiver\r
+ pUSART->US_CR = AT91C_US_RXDIS;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_DisableTx\r
+//* \brief Disable Transmitter\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US_DisableTx (\r
+ AT91PS_USART pUSART) // \arg pointer to a USART controller\r
+{\r
+ //* Disable transmitter\r
+ pUSART->US_CR = AT91C_US_TXDIS;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_Close\r
+//* \brief Close USART: disable IT disable receiver and transmitter, close PDC\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US_Close (\r
+ AT91PS_USART pUSART) // \arg pointer to a USART controller\r
+{\r
+ //* Reset the baud rate divisor register\r
+ pUSART->US_BRGR = 0 ;\r
+\r
+ //* Reset the USART mode\r
+ pUSART->US_MR = 0 ;\r
+\r
+ //* Reset the Timeguard Register\r
+ pUSART->US_TTGR = 0;\r
+\r
+ //* Disable all interrupts\r
+ pUSART->US_IDR = 0xFFFFFFFF ;\r
+\r
+ //* Abort the Peripheral Data Transfers\r
+ AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR));\r
+\r
+ //* Disable receiver and transmitter and stop any activity immediately\r
+ pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_TxReady\r
+//* \brief Return 1 if a character can be written in US_THR\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_US_TxReady (\r
+ AT91PS_USART pUSART ) // \arg pointer to a USART controller\r
+{\r
+ return (pUSART->US_CSR & AT91C_US_TXRDY);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_RxReady\r
+//* \brief Return 1 if a character can be read in US_RHR\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_US_RxReady (\r
+ AT91PS_USART pUSART ) // \arg pointer to a USART controller\r
+{\r
+ return (pUSART->US_CSR & AT91C_US_RXRDY);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_Error\r
+//* \brief Return the error flag\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_US_Error (\r
+ AT91PS_USART pUSART ) // \arg pointer to a USART controller\r
+{\r
+ return (pUSART->US_CSR &\r
+ (AT91C_US_OVRE | // Overrun error\r
+ AT91C_US_FRAME | // Framing error\r
+ AT91C_US_PARE)); // Parity error\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_PutChar\r
+//* \brief Send a character,does not check if ready to send\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US_PutChar (\r
+ AT91PS_USART pUSART,\r
+ int character )\r
+{\r
+ pUSART->US_THR = (character & 0x1FF);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_GetChar\r
+//* \brief Receive a character,does not check if a character is available\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_US_GetChar (\r
+ const AT91PS_USART pUSART)\r
+{\r
+ return((pUSART->US_RHR) & 0x1FF);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_SendFrame\r
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_US_SendFrame(\r
+ AT91PS_USART pUSART,\r
+ char *pBuffer,\r
+ unsigned int szBuffer,\r
+ char *pNextBuffer,\r
+ unsigned int szNextBuffer )\r
+{\r
+ return AT91F_PDC_SendFrame(\r
+ (AT91PS_PDC) &(pUSART->US_RPR),\r
+ pBuffer,\r
+ szBuffer,\r
+ pNextBuffer,\r
+ szNextBuffer);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_ReceiveFrame\r
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_US_ReceiveFrame (\r
+ AT91PS_USART pUSART,\r
+ char *pBuffer,\r
+ unsigned int szBuffer,\r
+ char *pNextBuffer,\r
+ unsigned int szNextBuffer )\r
+{\r
+ return AT91F_PDC_ReceiveFrame(\r
+ (AT91PS_PDC) &(pUSART->US_RPR),\r
+ pBuffer,\r
+ szBuffer,\r
+ pNextBuffer,\r
+ szNextBuffer);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US_SetIrdaFilter\r
+//* \brief Set the value of IrDa filter tregister\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US_SetIrdaFilter (\r
+ AT91PS_USART pUSART,\r
+ unsigned char value\r
+)\r
+{\r
+ pUSART->US_IF = value;\r
+}\r
+\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR SSC\r
+ ***************************************************************************** */\r
+//* Define the standard I2S mode configuration\r
+\r
+//* Configuration to set in the SSC Transmit Clock Mode Register\r
+//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits\r
+//* nb_slot_by_frame : number of channels\r
+#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\\r
+ AT91C_SSC_CKS_DIV +\\r
+ AT91C_SSC_CKO_CONTINOUS +\\r
+ AT91C_SSC_CKG_NONE +\\r
+ AT91C_SSC_START_FALL_RF +\\r
+ AT91C_SSC_STTOUT +\\r
+ ((1<<16) & AT91C_SSC_STTDLY) +\\r
+ ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24))\r
+\r
+\r
+//* Configuration to set in the SSC Transmit Frame Mode Register\r
+//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits\r
+//* nb_slot_by_frame : number of channels\r
+#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\\r
+ (nb_bit_by_slot-1) +\\r
+ AT91C_SSC_MSBF +\\r
+ (((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB) +\\r
+ (((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\\r
+ AT91C_SSC_FSOS_NEGATIVE)\r
+\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SSC_SetBaudrate\r
+//* \brief Set the baudrate according to the CPU clock\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SSC_SetBaudrate (\r
+ AT91PS_SSC pSSC, // \arg pointer to a SSC controller\r
+ unsigned int mainClock, // \arg peripheral clock\r
+ unsigned int speed) // \arg SSC baudrate\r
+{\r
+ unsigned int baud_value;\r
+ //* Define the baud rate divisor register\r
+ if (speed == 0)\r
+ baud_value = 0;\r
+ else\r
+ {\r
+ baud_value = (unsigned int) (mainClock * 10)/(2*speed);\r
+ if ((baud_value % 10) >= 5)\r
+ baud_value = (baud_value / 10) + 1;\r
+ else\r
+ baud_value /= 10;\r
+ }\r
+\r
+ pSSC->SSC_CMR = baud_value;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SSC_Configure\r
+//* \brief Configure SSC\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SSC_Configure (\r
+ AT91PS_SSC pSSC, // \arg pointer to a SSC controller\r
+ unsigned int syst_clock, // \arg System Clock Frequency\r
+ unsigned int baud_rate, // \arg Expected Baud Rate Frequency\r
+ unsigned int clock_rx, // \arg Receiver Clock Parameters\r
+ unsigned int mode_rx, // \arg mode Register to be programmed\r
+ unsigned int clock_tx, // \arg Transmitter Clock Parameters\r
+ unsigned int mode_tx) // \arg mode Register to be programmed\r
+{\r
+ //* Disable interrupts\r
+ pSSC->SSC_IDR = (unsigned int) -1;\r
+\r
+ //* Reset receiver and transmitter\r
+ pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ;\r
+\r
+ //* Define the Clock Mode Register\r
+ AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate);\r
+\r
+ //* Write the Receive Clock Mode Register\r
+ pSSC->SSC_RCMR = clock_rx;\r
+\r
+ //* Write the Transmit Clock Mode Register\r
+ pSSC->SSC_TCMR = clock_tx;\r
+\r
+ //* Write the Receive Frame Mode Register\r
+ pSSC->SSC_RFMR = mode_rx;\r
+\r
+ //* Write the Transmit Frame Mode Register\r
+ pSSC->SSC_TFMR = mode_tx;\r
+\r
+ //* Clear Transmit and Receive Counters\r
+ AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR));\r
+\r
+\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SSC_EnableRx\r
+//* \brief Enable receiving datas\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SSC_EnableRx (\r
+ AT91PS_SSC pSSC) // \arg pointer to a SSC controller\r
+{\r
+ //* Enable receiver\r
+ pSSC->SSC_CR = AT91C_SSC_RXEN;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SSC_DisableRx\r
+//* \brief Disable receiving datas\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SSC_DisableRx (\r
+ AT91PS_SSC pSSC) // \arg pointer to a SSC controller\r
+{\r
+ //* Disable receiver\r
+ pSSC->SSC_CR = AT91C_SSC_RXDIS;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SSC_EnableTx\r
+//* \brief Enable sending datas\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SSC_EnableTx (\r
+ AT91PS_SSC pSSC) // \arg pointer to a SSC controller\r
+{\r
+ //* Enable transmitter\r
+ pSSC->SSC_CR = AT91C_SSC_TXEN;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SSC_DisableTx\r
+//* \brief Disable sending datas\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SSC_DisableTx (\r
+ AT91PS_SSC pSSC) // \arg pointer to a SSC controller\r
+{\r
+ //* Disable transmitter\r
+ pSSC->SSC_CR = AT91C_SSC_TXDIS;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SSC_EnableIt\r
+//* \brief Enable SSC IT\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SSC_EnableIt (\r
+ AT91PS_SSC pSSC, // \arg pointer to a SSC controller\r
+ unsigned int flag) // \arg IT to be enabled\r
+{\r
+ //* Write to the IER register\r
+ pSSC->SSC_IER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SSC_DisableIt\r
+//* \brief Disable SSC IT\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SSC_DisableIt (\r
+ AT91PS_SSC pSSC, // \arg pointer to a SSC controller\r
+ unsigned int flag) // \arg IT to be disabled\r
+{\r
+ //* Write to the IDR register\r
+ pSSC->SSC_IDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SSC_ReceiveFrame\r
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_SSC_ReceiveFrame (\r
+ AT91PS_SSC pSSC,\r
+ char *pBuffer,\r
+ unsigned int szBuffer,\r
+ char *pNextBuffer,\r
+ unsigned int szNextBuffer )\r
+{\r
+ return AT91F_PDC_ReceiveFrame(\r
+ (AT91PS_PDC) &(pSSC->SSC_RPR),\r
+ pBuffer,\r
+ szBuffer,\r
+ pNextBuffer,\r
+ szNextBuffer);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SSC_SendFrame\r
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_SSC_SendFrame(\r
+ AT91PS_SSC pSSC,\r
+ char *pBuffer,\r
+ unsigned int szBuffer,\r
+ char *pNextBuffer,\r
+ unsigned int szNextBuffer )\r
+{\r
+ return AT91F_PDC_SendFrame(\r
+ (AT91PS_PDC) &(pSSC->SSC_RPR),\r
+ pBuffer,\r
+ szBuffer,\r
+ pNextBuffer,\r
+ szNextBuffer);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SSC_GetInterruptMaskStatus\r
+//* \brief Return SSC Interrupt Mask Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status\r
+ AT91PS_SSC pSsc) // \arg pointer to a SSC controller\r
+{\r
+ return pSsc->SSC_IMR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SSC_IsInterruptMasked\r
+//* \brief Test if SSC Interrupt is Masked\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_SSC_IsInterruptMasked(\r
+ AT91PS_SSC pSsc, // \arg pointer to a SSC controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag);\r
+}\r
+\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR TWI\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TWI_EnableIt\r
+//* \brief Enable TWI IT\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TWI_EnableIt (\r
+ AT91PS_TWI pTWI, // \arg pointer to a TWI controller\r
+ unsigned int flag) // \arg IT to be enabled\r
+{\r
+ //* Write to the IER register\r
+ pTWI->TWI_IER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TWI_DisableIt\r
+//* \brief Disable TWI IT\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TWI_DisableIt (\r
+ AT91PS_TWI pTWI, // \arg pointer to a TWI controller\r
+ unsigned int flag) // \arg IT to be disabled\r
+{\r
+ //* Write to the IDR register\r
+ pTWI->TWI_IDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TWI_Configure\r
+//* \brief Configure TWI in master mode\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI ) // \arg pointer to a TWI controller\r
+{\r
+ //* Disable interrupts\r
+ pTWI->TWI_IDR = (unsigned int) -1;\r
+\r
+ //* Reset peripheral\r
+ pTWI->TWI_CR = AT91C_TWI_SWRST;\r
+\r
+ //* Set Master mode\r
+ pTWI->TWI_CR = AT91C_TWI_MSEN;\r
+\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TWI_GetInterruptMaskStatus\r
+//* \brief Return TWI Interrupt Mask Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status\r
+ AT91PS_TWI pTwi) // \arg pointer to a TWI controller\r
+{\r
+ return pTwi->TWI_IMR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TWI_IsInterruptMasked\r
+//* \brief Test if TWI Interrupt is Masked\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_TWI_IsInterruptMasked(\r
+ AT91PS_TWI pTwi, // \arg pointer to a TWI controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag);\r
+}\r
+\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR PWMC\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWM_GetStatus\r
+//* \brief Return PWM Interrupt Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PWMC_GetStatus( // \return PWM Interrupt Status\r
+ AT91PS_PWMC pPWM) // pointer to a PWM controller\r
+{\r
+ return pPWM->PWMC_SR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWM_InterruptEnable\r
+//* \brief Enable PWM Interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PWMC_InterruptEnable(\r
+ AT91PS_PWMC pPwm, // \arg pointer to a PWM controller\r
+ unsigned int flag) // \arg PWM interrupt to be enabled\r
+{\r
+ pPwm->PWMC_IER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWM_InterruptDisable\r
+//* \brief Disable PWM Interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PWMC_InterruptDisable(\r
+ AT91PS_PWMC pPwm, // \arg pointer to a PWM controller\r
+ unsigned int flag) // \arg PWM interrupt to be disabled\r
+{\r
+ pPwm->PWMC_IDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWM_GetInterruptMaskStatus\r
+//* \brief Return PWM Interrupt Mask Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( // \return PWM Interrupt Mask Status\r
+ AT91PS_PWMC pPwm) // \arg pointer to a PWM controller\r
+{\r
+ return pPwm->PWMC_IMR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWM_IsInterruptMasked\r
+//* \brief Test if PWM Interrupt is Masked\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PWMC_IsInterruptMasked(\r
+ AT91PS_PWMC pPWM, // \arg pointer to a PWM controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_PWMC_GetInterruptMaskStatus(pPWM) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWM_IsStatusSet\r
+//* \brief Test if PWM Interrupt is Set\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_PWMC_IsStatusSet(\r
+ AT91PS_PWMC pPWM, // \arg pointer to a PWM controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_PWMC_GetStatus(pPWM) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWM_CfgChannel\r
+//* \brief Test if PWM Interrupt is Set\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PWMC_CfgChannel(\r
+ AT91PS_PWMC pPWM, // \arg pointer to a PWM controller\r
+ unsigned int channelId, // \arg PWM channel ID\r
+ unsigned int mode, // \arg PWM mode\r
+ unsigned int period, // \arg PWM period\r
+ unsigned int duty) // \arg PWM duty cycle\r
+{\r
+ pPWM->PWMC_CH[channelId].PWMC_CMR = mode;\r
+ pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty;\r
+ pPWM->PWMC_CH[channelId].PWMC_CPRDR = period;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWM_StartChannel\r
+//* \brief Enable channel\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PWMC_StartChannel(\r
+ AT91PS_PWMC pPWM, // \arg pointer to a PWM controller\r
+ unsigned int flag) // \arg Channels IDs to be enabled\r
+{\r
+ pPWM->PWMC_ENA = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWM_StopChannel\r
+//* \brief Disable channel\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PWMC_StopChannel(\r
+ AT91PS_PWMC pPWM, // \arg pointer to a PWM controller\r
+ unsigned int flag) // \arg Channels IDs to be enabled\r
+{\r
+ pPWM->PWMC_DIS = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWM_UpdateChannel\r
+//* \brief Update Period or Duty Cycle\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PWMC_UpdateChannel(\r
+ AT91PS_PWMC pPWM, // \arg pointer to a PWM controller\r
+ unsigned int channelId, // \arg PWM channel ID\r
+ unsigned int update) // \arg Channels IDs to be enabled\r
+{\r
+ pPWM->PWMC_CH[channelId].PWMC_CUPDR = update;\r
+}\r
+\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR UDP\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_EnableIt\r
+//* \brief Enable UDP IT\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_UDP_EnableIt (\r
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller\r
+ unsigned int flag) // \arg IT to be enabled\r
+{\r
+ //* Write to the IER register\r
+ pUDP->UDP_IER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_DisableIt\r
+//* \brief Disable UDP IT\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_UDP_DisableIt (\r
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller\r
+ unsigned int flag) // \arg IT to be disabled\r
+{\r
+ //* Write to the IDR register\r
+ pUDP->UDP_IDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_SetAddress\r
+//* \brief Set UDP functional address\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_UDP_SetAddress (\r
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller\r
+ unsigned char address) // \arg new UDP address\r
+{\r
+ pUDP->UDP_FADDR = (AT91C_UDP_FEN | address);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_EnableEp\r
+//* \brief Enable Endpoint\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_UDP_EnableEp (\r
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller\r
+ unsigned char endpoint) // \arg endpoint number\r
+{\r
+ pUDP->UDP_CSR[endpoint] |= AT91C_UDP_EPEDS;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_DisableEp\r
+//* \brief Enable Endpoint\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_UDP_DisableEp (\r
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller\r
+ unsigned char endpoint) // \arg endpoint number\r
+{\r
+ pUDP->UDP_CSR[endpoint] &= ~AT91C_UDP_EPEDS;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_SetState\r
+//* \brief Set UDP Device state\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_UDP_SetState (\r
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller\r
+ unsigned int flag) // \arg new UDP address\r
+{\r
+ pUDP->UDP_GLBSTATE &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG);\r
+ pUDP->UDP_GLBSTATE |= flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_GetState\r
+//* \brief return UDP Device state\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state\r
+ AT91PS_UDP pUDP) // \arg pointer to a UDP controller\r
+{\r
+ return (pUDP->UDP_GLBSTATE & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_ResetEp\r
+//* \brief Reset UDP endpoint\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_UDP_ResetEp ( // \return the UDP device state\r
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller\r
+ unsigned int flag) // \arg Endpoints to be reset\r
+{\r
+ pUDP->UDP_RSTEP = flag;\r
+ pUDP->UDP_RSTEP = 0;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_EpStall\r
+//* \brief Endpoint will STALL requests\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_UDP_EpStall(\r
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller\r
+ unsigned char endpoint) // \arg endpoint number\r
+{\r
+ pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_EpWrite\r
+//* \brief Write value in the DPR\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_UDP_EpWrite(\r
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller\r
+ unsigned char endpoint, // \arg endpoint number\r
+ unsigned char value) // \arg value to be written in the DPR\r
+{\r
+ pUDP->UDP_FDR[endpoint] = value;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_EpRead\r
+//* \brief Return value from the DPR\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_UDP_EpRead(\r
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller\r
+ unsigned char endpoint) // \arg endpoint number\r
+{\r
+ return pUDP->UDP_FDR[endpoint];\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_EpEndOfWr\r
+//* \brief Notify the UDP that values in DPR are ready to be sent\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_UDP_EpEndOfWr(\r
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller\r
+ unsigned char endpoint) // \arg endpoint number\r
+{\r
+ pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_EpClear\r
+//* \brief Clear flag in the endpoint CSR register\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_UDP_EpClear(\r
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller\r
+ unsigned char endpoint, // \arg endpoint number\r
+ unsigned int flag) // \arg flag to be cleared\r
+{\r
+ pUDP->UDP_CSR[endpoint] &= ~(flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_EpSet\r
+//* \brief Set flag in the endpoint CSR register\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_UDP_EpSet(\r
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller\r
+ unsigned char endpoint, // \arg endpoint number\r
+ unsigned int flag) // \arg flag to be cleared\r
+{\r
+ pUDP->UDP_CSR[endpoint] |= flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_EpStatus\r
+//* \brief Return the endpoint CSR register\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_UDP_EpStatus(\r
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller\r
+ unsigned char endpoint) // \arg endpoint number\r
+{\r
+ return pUDP->UDP_CSR[endpoint];\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_GetInterruptMaskStatus\r
+//* \brief Return UDP Interrupt Mask Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \return UDP Interrupt Mask Status\r
+ AT91PS_UDP pUdp) // \arg pointer to a UDP controller\r
+{\r
+ return pUdp->UDP_IMR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_IsInterruptMasked\r
+//* \brief Test if UDP Interrupt is Masked\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_UDP_IsInterruptMasked(\r
+ AT91PS_UDP pUdp, // \arg pointer to a UDP controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag);\r
+}\r
+\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR TC\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TC_InterruptEnable\r
+//* \brief Enable TC Interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TC_InterruptEnable(\r
+ AT91PS_TC pTc, // \arg pointer to a TC controller\r
+ unsigned int flag) // \arg TC interrupt to be enabled\r
+{\r
+ pTc->TC_IER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TC_InterruptDisable\r
+//* \brief Disable TC Interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TC_InterruptDisable(\r
+ AT91PS_TC pTc, // \arg pointer to a TC controller\r
+ unsigned int flag) // \arg TC interrupt to be disabled\r
+{\r
+ pTc->TC_IDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TC_GetInterruptMaskStatus\r
+//* \brief Return TC Interrupt Mask Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status\r
+ AT91PS_TC pTc) // \arg pointer to a TC controller\r
+{\r
+ return pTc->TC_IMR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TC_IsInterruptMasked\r
+//* \brief Test if TC Interrupt is Masked\r
+//*----------------------------------------------------------------------------\r
+__inline int AT91F_TC_IsInterruptMasked(\r
+ AT91PS_TC pTc, // \arg pointer to a TC controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag);\r
+}\r
+\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR CAN\r
+ ***************************************************************************** */\r
+#define STANDARD_FORMAT 0\r
+#define EXTENDED_FORMAT 1\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_InitMailboxRegisters()\r
+//* \brief Configure the corresponding mailbox\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_InitMailboxRegisters(AT91PS_CAN_MB CAN_Mailbox,\r
+ int mode_reg,\r
+ int acceptance_mask_reg,\r
+ int id_reg,\r
+ int data_low_reg,\r
+ int data_high_reg,\r
+ int control_reg)\r
+{\r
+ CAN_Mailbox->CAN_MB_MCR = 0x0;\r
+ CAN_Mailbox->CAN_MB_MMR = mode_reg;\r
+ CAN_Mailbox->CAN_MB_MAM = acceptance_mask_reg;\r
+ CAN_Mailbox->CAN_MB_MID = id_reg;\r
+ CAN_Mailbox->CAN_MB_MDL = data_low_reg; \r
+ CAN_Mailbox->CAN_MB_MDH = data_high_reg;\r
+ CAN_Mailbox->CAN_MB_MCR = control_reg;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_EnableCAN()\r
+//* \brief\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_EnableCAN(\r
+ AT91PS_CAN pCAN) // pointer to a CAN controller\r
+{\r
+ pCAN->CAN_MR |= AT91C_CAN_CANEN;\r
+\r
+ // Wait for WAKEUP flag raising <=> 11-recessive-bit were scanned by the transceiver\r
+ while( (pCAN->CAN_SR & AT91C_CAN_WAKEUP) != AT91C_CAN_WAKEUP );\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_DisableCAN()\r
+//* \brief\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_DisableCAN(\r
+ AT91PS_CAN pCAN) // pointer to a CAN controller\r
+{\r
+ pCAN->CAN_MR &= ~AT91C_CAN_CANEN;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_EnableIt\r
+//* \brief Enable CAN interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CAN_EnableIt (\r
+ AT91PS_CAN pCAN, // pointer to a CAN controller\r
+ unsigned int flag) // IT to be enabled\r
+{\r
+ //* Write to the IER register\r
+ pCAN->CAN_IER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_DisableIt\r
+//* \brief Disable CAN interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CAN_DisableIt (\r
+ AT91PS_CAN pCAN, // pointer to a CAN controller\r
+ unsigned int flag) // IT to be disabled\r
+{\r
+ //* Write to the IDR register\r
+ pCAN->CAN_IDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_GetStatus\r
+//* \brief Return CAN Interrupt Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CAN_GetStatus( // \return CAN Interrupt Status\r
+ AT91PS_CAN pCAN) // pointer to a CAN controller\r
+{\r
+ return pCAN->CAN_SR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_GetInterruptMaskStatus\r
+//* \brief Return CAN Interrupt Mask Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CAN_GetInterruptMaskStatus( // \return CAN Interrupt Mask Status\r
+ AT91PS_CAN pCAN) // pointer to a CAN controller\r
+{\r
+ return pCAN->CAN_IMR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_IsInterruptMasked\r
+//* \brief Test if CAN Interrupt is Masked\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CAN_IsInterruptMasked(\r
+ AT91PS_CAN pCAN, // \arg pointer to a CAN controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_CAN_GetInterruptMaskStatus(pCAN) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_IsStatusSet\r
+//* \brief Test if CAN Interrupt is Set\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CAN_IsStatusSet(\r
+ AT91PS_CAN pCAN, // \arg pointer to a CAN controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_CAN_GetStatus(pCAN) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_CfgModeReg\r
+//* \brief Configure the Mode Register of the CAN controller\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CAN_CfgModeReg (\r
+ AT91PS_CAN pCAN, // pointer to a CAN controller\r
+ unsigned int mode) // mode register\r
+{\r
+ //* Write to the MR register\r
+ pCAN->CAN_MR = mode;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_GetModeReg\r
+//* \brief Return the Mode Register of the CAN controller value\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CAN_GetModeReg (\r
+ AT91PS_CAN pCAN // pointer to a CAN controller\r
+ )\r
+{\r
+ return pCAN->CAN_MR; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_CfgBaudrateReg\r
+//* \brief Configure the Baudrate of the CAN controller for the network\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CAN_CfgBaudrateReg (\r
+ AT91PS_CAN pCAN, // pointer to a CAN controller\r
+ unsigned int baudrate_cfg)\r
+{\r
+ //* Write to the BR register\r
+ pCAN->CAN_BR = baudrate_cfg; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_GetBaudrate\r
+//* \brief Return the Baudrate of the CAN controller for the network value\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CAN_GetBaudrate (\r
+ AT91PS_CAN pCAN // pointer to a CAN controller\r
+ )\r
+{\r
+ return pCAN->CAN_BR; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_GetInternalCounter\r
+//* \brief Return CAN Timer Regsiter Value\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CAN_GetInternalCounter (\r
+ AT91PS_CAN pCAN // pointer to a CAN controller\r
+ )\r
+{\r
+ return pCAN->CAN_TIM; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_GetTimestamp\r
+//* \brief Return CAN Timestamp Register Value\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CAN_GetTimestamp (\r
+ AT91PS_CAN pCAN // pointer to a CAN controller\r
+ )\r
+{\r
+ return pCAN->CAN_TIMESTP; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_GetErrorCounter\r
+//* \brief Return CAN Error Counter Register Value\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CAN_GetErrorCounter (\r
+ AT91PS_CAN pCAN // pointer to a CAN controller\r
+ )\r
+{\r
+ return pCAN->CAN_ECR; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_InitTransferRequest\r
+//* \brief Request for a transfer on the corresponding mailboxes\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CAN_InitTransferRequest (\r
+ AT91PS_CAN pCAN, // pointer to a CAN controller\r
+ unsigned int transfer_cmd)\r
+{\r
+ pCAN->CAN_TCR = transfer_cmd; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_InitAbortRequest\r
+//* \brief Abort the corresponding mailboxes\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CAN_InitAbortRequest (\r
+ AT91PS_CAN pCAN, // pointer to a CAN controller\r
+ unsigned int abort_cmd)\r
+{\r
+ pCAN->CAN_ACR = abort_cmd; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_CfgMessageModeReg\r
+//* \brief Program the Message Mode Register\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CAN_CfgMessageModeReg (\r
+ AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox\r
+ unsigned int mode)\r
+{\r
+ CAN_Mailbox->CAN_MB_MMR = mode; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_GetMessageModeReg\r
+//* \brief Return the Message Mode Register\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CAN_GetMessageModeReg (\r
+ AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox\r
+{\r
+ return CAN_Mailbox->CAN_MB_MMR; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_CfgMessageIDReg\r
+//* \brief Program the Message ID Register\r
+//* \brief Version == 0 for Standard messsage, Version == 1 for Extended\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CAN_CfgMessageIDReg (\r
+ AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox\r
+ unsigned int id,\r
+ unsigned char version)\r
+{\r
+ if(version==0) // IDvA Standard Format\r
+ CAN_Mailbox->CAN_MB_MID = id<<18;\r
+ else // IDvB Extended Format\r
+ CAN_Mailbox->CAN_MB_MID = id | (1<<29); // set MIDE bit\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_GetMessageIDReg\r
+//* \brief Return the Message ID Register\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CAN_GetMessageIDReg (\r
+ AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox\r
+{\r
+ return CAN_Mailbox->CAN_MB_MID;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_CfgMessageAcceptanceMaskReg\r
+//* \brief Program the Message Acceptance Mask Register\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CAN_CfgMessageAcceptanceMaskReg (\r
+ AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox\r
+ unsigned int mask)\r
+{\r
+ CAN_Mailbox->CAN_MB_MAM = mask;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_GetMessageAcceptanceMaskReg\r
+//* \brief Return the Message Acceptance Mask Register\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CAN_GetMessageAcceptanceMaskReg (\r
+ AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox\r
+{\r
+ return CAN_Mailbox->CAN_MB_MAM;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_GetFamilyID\r
+//* \brief Return the Message ID Register\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CAN_GetFamilyID (\r
+ AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox\r
+{\r
+ return CAN_Mailbox->CAN_MB_MFID; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_CfgMessageCtrl\r
+//* \brief Request and config for a transfer on the corresponding mailbox\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CAN_CfgMessageCtrlReg (\r
+ AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox\r
+ unsigned int message_ctrl_cmd)\r
+{\r
+ CAN_Mailbox->CAN_MB_MCR = message_ctrl_cmd; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_GetMessageStatus\r
+//* \brief Return CAN Mailbox Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CAN_GetMessageStatus (\r
+ AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox\r
+{\r
+ return CAN_Mailbox->CAN_MB_MSR; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_CfgMessageDataLow\r
+//* \brief Program data low value\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CAN_CfgMessageDataLow (\r
+ AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox\r
+ unsigned int data)\r
+{\r
+ CAN_Mailbox->CAN_MB_MDL = data; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_GetMessageDataLow\r
+//* \brief Return data low value\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CAN_GetMessageDataLow (\r
+ AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox\r
+{\r
+ return CAN_Mailbox->CAN_MB_MDL; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_CfgMessageDataHigh\r
+//* \brief Program data high value\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CAN_CfgMessageDataHigh (\r
+ AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox\r
+ unsigned int data)\r
+{\r
+ CAN_Mailbox->CAN_MB_MDH = data; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_GetMessageDataHigh\r
+//* \brief Return data high value\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CAN_GetMessageDataHigh (\r
+ AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox\r
+{\r
+ return CAN_Mailbox->CAN_MB_MDH; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_Open\r
+//* \brief Open a CAN Port\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_CAN_Open (\r
+ const unsigned int null) // \arg\r
+{\r
+ /* NOT DEFINED AT THIS MOMENT */\r
+ return ( 0 );\r
+}\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR ADC\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_EnableIt\r
+//* \brief Enable ADC interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_ADC_EnableIt (\r
+ AT91PS_ADC pADC, // pointer to a ADC controller\r
+ unsigned int flag) // IT to be enabled\r
+{\r
+ //* Write to the IER register\r
+ pADC->ADC_IER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_DisableIt\r
+//* \brief Disable ADC interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_ADC_DisableIt (\r
+ AT91PS_ADC pADC, // pointer to a ADC controller\r
+ unsigned int flag) // IT to be disabled\r
+{\r
+ //* Write to the IDR register\r
+ pADC->ADC_IDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_GetStatus\r
+//* \brief Return ADC Interrupt Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_GetStatus( // \return ADC Interrupt Status\r
+ AT91PS_ADC pADC) // pointer to a ADC controller\r
+{\r
+ return pADC->ADC_SR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_GetInterruptMaskStatus\r
+//* \brief Return ADC Interrupt Mask Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_GetInterruptMaskStatus( // \return ADC Interrupt Mask Status\r
+ AT91PS_ADC pADC) // pointer to a ADC controller\r
+{\r
+ return pADC->ADC_IMR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_IsInterruptMasked\r
+//* \brief Test if ADC Interrupt is Masked\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_IsInterruptMasked(\r
+ AT91PS_ADC pADC, // \arg pointer to a ADC controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_ADC_GetInterruptMaskStatus(pADC) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_IsStatusSet\r
+//* \brief Test if ADC Status is Set\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_IsStatusSet(\r
+ AT91PS_ADC pADC, // \arg pointer to a ADC controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_ADC_GetStatus(pADC) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_CfgModeReg\r
+//* \brief Configure the Mode Register of the ADC controller\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_ADC_CfgModeReg (\r
+ AT91PS_ADC pADC, // pointer to a ADC controller\r
+ unsigned int mode) // mode register\r
+{\r
+ //* Write to the MR register\r
+ pADC->ADC_MR = mode;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_GetModeReg\r
+//* \brief Return the Mode Register of the ADC controller value\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_GetModeReg (\r
+ AT91PS_ADC pADC // pointer to a ADC controller\r
+ )\r
+{\r
+ return pADC->ADC_MR; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_CfgTimings\r
+//* \brief Configure the different necessary timings of the ADC controller\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_ADC_CfgTimings (\r
+ AT91PS_ADC pADC, // pointer to a ADC controller\r
+ unsigned int mck_clock, // in MHz\r
+ unsigned int adc_clock, // in MHz\r
+ unsigned int startup_time, // in us\r
+ unsigned int sample_and_hold_time) // in ns\r
+{\r
+ unsigned int prescal,startup,shtim;\r
+ \r
+ prescal = mck_clock/(2*adc_clock) - 1;\r
+ startup = adc_clock*startup_time/8 - 1;\r
+ shtim = adc_clock*sample_and_hold_time/1000 - 1;\r
+ \r
+ //* Write to the MR register\r
+ pADC->ADC_MR = ( (prescal<<8) & AT91C_ADC_PRESCAL) | ( (startup<<16) & AT91C_ADC_STARTUP) | ( (shtim<<24) & AT91C_ADC_SHTIM);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_EnableChannel\r
+//* \brief Return ADC Timer Register Value\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_ADC_EnableChannel (\r
+ AT91PS_ADC pADC, // pointer to a ADC controller\r
+ unsigned int channel) // mode register\r
+{\r
+ //* Write to the CHER register\r
+ pADC->ADC_CHER = channel;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_DisableChannel\r
+//* \brief Return ADC Timer Register Value\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_ADC_DisableChannel (\r
+ AT91PS_ADC pADC, // pointer to a ADC controller\r
+ unsigned int channel) // mode register\r
+{\r
+ //* Write to the CHDR register\r
+ pADC->ADC_CHDR = channel;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_GetChannelStatus\r
+//* \brief Return ADC Timer Register Value\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_GetChannelStatus (\r
+ AT91PS_ADC pADC // pointer to a ADC controller\r
+ )\r
+{\r
+ return pADC->ADC_CHSR; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_StartConversion\r
+//* \brief Software request for a analog to digital conversion\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_ADC_StartConversion (\r
+ AT91PS_ADC pADC // pointer to a ADC controller\r
+ )\r
+{\r
+ pADC->ADC_CR = AT91C_ADC_START; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_SoftReset\r
+//* \brief Software reset\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_ADC_SoftReset (\r
+ AT91PS_ADC pADC // pointer to a ADC controller\r
+ )\r
+{\r
+ pADC->ADC_CR = AT91C_ADC_SWRST; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_GetLastConvertedData\r
+//* \brief Return the Last Converted Data\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_GetLastConvertedData (\r
+ AT91PS_ADC pADC // pointer to a ADC controller\r
+ )\r
+{\r
+ return pADC->ADC_LCDR; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_GetConvertedDataCH0\r
+//* \brief Return the Channel 0 Converted Data\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_GetConvertedDataCH0 (\r
+ AT91PS_ADC pADC // pointer to a ADC controller\r
+ )\r
+{\r
+ return pADC->ADC_CDR0; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_GetConvertedDataCH1\r
+//* \brief Return the Channel 1 Converted Data\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_GetConvertedDataCH1 (\r
+ AT91PS_ADC pADC // pointer to a ADC controller\r
+ )\r
+{\r
+ return pADC->ADC_CDR1; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_GetConvertedDataCH2\r
+//* \brief Return the Channel 2 Converted Data\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_GetConvertedDataCH2 (\r
+ AT91PS_ADC pADC // pointer to a ADC controller\r
+ )\r
+{\r
+ return pADC->ADC_CDR2; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_GetConvertedDataCH3\r
+//* \brief Return the Channel 3 Converted Data\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_GetConvertedDataCH3 (\r
+ AT91PS_ADC pADC // pointer to a ADC controller\r
+ )\r
+{\r
+ return pADC->ADC_CDR3; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_GetConvertedDataCH4\r
+//* \brief Return the Channel 4 Converted Data\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_GetConvertedDataCH4 (\r
+ AT91PS_ADC pADC // pointer to a ADC controller\r
+ )\r
+{\r
+ return pADC->ADC_CDR4; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_GetConvertedDataCH5\r
+//* \brief Return the Channel 5 Converted Data\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_GetConvertedDataCH5 (\r
+ AT91PS_ADC pADC // pointer to a ADC controller\r
+ )\r
+{\r
+ return pADC->ADC_CDR5; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_GetConvertedDataCH6\r
+//* \brief Return the Channel 6 Converted Data\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_GetConvertedDataCH6 (\r
+ AT91PS_ADC pADC // pointer to a ADC controller\r
+ )\r
+{\r
+ return pADC->ADC_CDR6; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_GetConvertedDataCH7\r
+//* \brief Return the Channel 7 Converted Data\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_ADC_GetConvertedDataCH7 (\r
+ AT91PS_ADC pADC // pointer to a ADC controller\r
+ )\r
+{\r
+ return pADC->ADC_CDR7; \r
+}\r
+\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR AES\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AES_EnableIt\r
+//* \brief Enable AES interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AES_EnableIt (\r
+ AT91PS_AES pAES, // pointer to a AES controller\r
+ unsigned int flag) // IT to be enabled\r
+{\r
+ //* Write to the IER register\r
+ pAES->AES_IER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AES_DisableIt\r
+//* \brief Disable AES interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AES_DisableIt (\r
+ AT91PS_AES pAES, // pointer to a AES controller\r
+ unsigned int flag) // IT to be disabled\r
+{\r
+ //* Write to the IDR register\r
+ pAES->AES_IDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AES_GetStatus\r
+//* \brief Return AES Interrupt Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_AES_GetStatus( // \return AES Interrupt Status\r
+ AT91PS_AES pAES) // pointer to a AES controller\r
+{\r
+ return pAES->AES_ISR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AES_GetInterruptMaskStatus\r
+//* \brief Return AES Interrupt Mask Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_AES_GetInterruptMaskStatus( // \return AES Interrupt Mask Status\r
+ AT91PS_AES pAES) // pointer to a AES controller\r
+{\r
+ return pAES->AES_IMR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AES_IsInterruptMasked\r
+//* \brief Test if AES Interrupt is Masked\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_AES_IsInterruptMasked(\r
+ AT91PS_AES pAES, // \arg pointer to a AES controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_AES_GetInterruptMaskStatus(pAES) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AES_IsStatusSet\r
+//* \brief Test if AES Status is Set\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_AES_IsStatusSet(\r
+ AT91PS_AES pAES, // \arg pointer to a AES controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_AES_GetStatus(pAES) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AES_CfgModeReg\r
+//* \brief Configure the Mode Register of the AES controller\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AES_CfgModeReg (\r
+ AT91PS_AES pAES, // pointer to a AES controller\r
+ unsigned int mode) // mode register\r
+{\r
+ //* Write to the MR register\r
+ pAES->AES_MR = mode;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AES_GetModeReg\r
+//* \brief Return the Mode Register of the AES controller value\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_AES_GetModeReg (\r
+ AT91PS_AES pAES // pointer to a AES controller\r
+ )\r
+{\r
+ return pAES->AES_MR; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AES_StartProcessing\r
+//* \brief Start Encryption or Decryption\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AES_StartProcessing (\r
+ AT91PS_AES pAES // pointer to a AES controller\r
+ )\r
+{\r
+ pAES->AES_CR = AT91C_AES_START; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AES_SoftReset\r
+//* \brief Reset AES\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AES_SoftReset (\r
+ AT91PS_AES pAES // pointer to a AES controller\r
+ )\r
+{\r
+ pAES->AES_CR = AT91C_AES_SWRST; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AES_LoadNewSeed\r
+//* \brief Load New Seed in the random number generator\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AES_LoadNewSeed (\r
+ AT91PS_AES pAES // pointer to a AES controller\r
+ )\r
+{\r
+ pAES->AES_CR = AT91C_AES_LOADSEED; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AES_SetCryptoKey\r
+//* \brief Set Cryptographic Key x\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AES_SetCryptoKey (\r
+ AT91PS_AES pAES, // pointer to a AES controller\r
+ unsigned char index,\r
+ unsigned int keyword\r
+ )\r
+{\r
+ pAES->AES_KEYWxR[index] = keyword; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AES_InputData\r
+//* \brief Set Input Data x\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AES_InputData (\r
+ AT91PS_AES pAES, // pointer to a AES controller\r
+ unsigned char index,\r
+ unsigned int indata\r
+ )\r
+{\r
+ pAES->AES_IDATAxR[index] = indata; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AES_GetOutputData\r
+//* \brief Get Output Data x\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_AES_GetOutputData (\r
+ AT91PS_AES pAES, // pointer to a AES controller\r
+ unsigned char index\r
+ )\r
+{\r
+ return pAES->AES_ODATAxR[index]; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AES_SetInitializationVector\r
+//* \brief Set Initialization Vector (or Counter) x\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AES_SetInitializationVector (\r
+ AT91PS_AES pAES, // pointer to a AES controller\r
+ unsigned char index,\r
+ unsigned int initvector\r
+ )\r
+{\r
+ pAES->AES_IVxR[index] = initvector; \r
+}\r
+\r
+/* *****************************************************************************\r
+ SOFTWARE API FOR TDES\r
+ ***************************************************************************** */\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TDES_EnableIt\r
+//* \brief Enable TDES interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TDES_EnableIt (\r
+ AT91PS_TDES pTDES, // pointer to a TDES controller\r
+ unsigned int flag) // IT to be enabled\r
+{\r
+ //* Write to the IER register\r
+ pTDES->TDES_IER = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TDES_DisableIt\r
+//* \brief Disable TDES interrupt\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TDES_DisableIt (\r
+ AT91PS_TDES pTDES, // pointer to a TDES controller\r
+ unsigned int flag) // IT to be disabled\r
+{\r
+ //* Write to the IDR register\r
+ pTDES->TDES_IDR = flag;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TDES_GetStatus\r
+//* \brief Return TDES Interrupt Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_TDES_GetStatus( // \return TDES Interrupt Status\r
+ AT91PS_TDES pTDES) // pointer to a TDES controller\r
+{\r
+ return pTDES->TDES_ISR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TDES_GetInterruptMaskStatus\r
+//* \brief Return TDES Interrupt Mask Status\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_TDES_GetInterruptMaskStatus( // \return TDES Interrupt Mask Status\r
+ AT91PS_TDES pTDES) // pointer to a TDES controller\r
+{\r
+ return pTDES->TDES_IMR;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TDES_IsInterruptMasked\r
+//* \brief Test if TDES Interrupt is Masked\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_TDES_IsInterruptMasked(\r
+ AT91PS_TDES pTDES, // \arg pointer to a TDES controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_TDES_GetInterruptMaskStatus(pTDES) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TDES_IsStatusSet\r
+//* \brief Test if TDES Status is Set\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_TDES_IsStatusSet(\r
+ AT91PS_TDES pTDES, // \arg pointer to a TDES controller\r
+ unsigned int flag) // \arg flag to be tested\r
+{\r
+ return (AT91F_TDES_GetStatus(pTDES) & flag);\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TDES_CfgModeReg\r
+//* \brief Configure the Mode Register of the TDES controller\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TDES_CfgModeReg (\r
+ AT91PS_TDES pTDES, // pointer to a TDES controller\r
+ unsigned int mode) // mode register\r
+{\r
+ //* Write to the MR register\r
+ pTDES->TDES_MR = mode;\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TDES_GetModeReg\r
+//* \brief Return the Mode Register of the TDES controller value\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_TDES_GetModeReg (\r
+ AT91PS_TDES pTDES // pointer to a TDES controller\r
+ )\r
+{\r
+ return pTDES->TDES_MR; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TDES_StartProcessing\r
+//* \brief Start Encryption or Decryption\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TDES_StartProcessing (\r
+ AT91PS_TDES pTDES // pointer to a TDES controller\r
+ )\r
+{\r
+ pTDES->TDES_CR = AT91C_TDES_START; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TDES_SoftReset\r
+//* \brief Reset TDES\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TDES_SoftReset (\r
+ AT91PS_TDES pTDES // pointer to a TDES controller\r
+ )\r
+{\r
+ pTDES->TDES_CR = AT91C_TDES_SWRST; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TDES_SetCryptoKey1\r
+//* \brief Set Cryptographic Key 1 Word x\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TDES_SetCryptoKey1 (\r
+ AT91PS_TDES pTDES, // pointer to a TDES controller\r
+ unsigned char index,\r
+ unsigned int keyword\r
+ )\r
+{\r
+ pTDES->TDES_KEY1WxR[index] = keyword; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TDES_SetCryptoKey2\r
+//* \brief Set Cryptographic Key 2 Word x\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TDES_SetCryptoKey2 (\r
+ AT91PS_TDES pTDES, // pointer to a TDES controller\r
+ unsigned char index,\r
+ unsigned int keyword\r
+ )\r
+{\r
+ pTDES->TDES_KEY2WxR[index] = keyword; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TDES_SetCryptoKey3\r
+//* \brief Set Cryptographic Key 3 Word x\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TDES_SetCryptoKey3 (\r
+ AT91PS_TDES pTDES, // pointer to a TDES controller\r
+ unsigned char index,\r
+ unsigned int keyword\r
+ )\r
+{\r
+ pTDES->TDES_KEY3WxR[index] = keyword; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TDES_InputData\r
+//* \brief Set Input Data x\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TDES_InputData (\r
+ AT91PS_TDES pTDES, // pointer to a TDES controller\r
+ unsigned char index,\r
+ unsigned int indata\r
+ )\r
+{\r
+ pTDES->TDES_IDATAxR[index] = indata; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TDES_GetOutputData\r
+//* \brief Get Output Data x\r
+//*----------------------------------------------------------------------------\r
+__inline unsigned int AT91F_TDES_GetOutputData (\r
+ AT91PS_TDES pTDES, // pointer to a TDES controller\r
+ unsigned char index\r
+ )\r
+{\r
+ return pTDES->TDES_ODATAxR[index]; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TDES_SetInitializationVector\r
+//* \brief Set Initialization Vector x\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TDES_SetInitializationVector (\r
+ AT91PS_TDES pTDES, // pointer to a TDES controller\r
+ unsigned char index,\r
+ unsigned int initvector\r
+ )\r
+{\r
+ pTDES->TDES_IVxR[index] = initvector; \r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_DBGU_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for DBGU\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_DBGU_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_SYS));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_DBGU_CfgPIO\r
+//* \brief Configure PIO controllers to drive DBGU signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_DBGU_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOA, // PIO controller base address\r
+ ((unsigned int) AT91C_PA27_DRXD ) |\r
+ ((unsigned int) AT91C_PA28_DTXD ), // Peripheral A\r
+ 0); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for PMC\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PMC_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_SYS));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PMC_CfgPIO\r
+//* \brief Configure PIO controllers to drive PMC signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PMC_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOB, // PIO controller base address\r
+ ((unsigned int) AT91C_PB30_PCK2 ) |\r
+ ((unsigned int) AT91C_PB29_PCK1 ), // Peripheral A\r
+ ((unsigned int) AT91C_PB20_PCK0 ) |\r
+ ((unsigned int) AT91C_PB0_PCK0 ) |\r
+ ((unsigned int) AT91C_PB22_PCK2 ) |\r
+ ((unsigned int) AT91C_PB21_PCK1 )); // Peripheral B\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOA, // PIO controller base address\r
+ 0, // Peripheral A\r
+ ((unsigned int) AT91C_PA30_PCK2 ) |\r
+ ((unsigned int) AT91C_PA13_PCK1 ) |\r
+ ((unsigned int) AT91C_PA27_PCK3 )); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_VREG_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for VREG\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_VREG_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_SYS));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_RSTC_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for RSTC\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_RSTC_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_SYS));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SSC_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for SSC\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SSC_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_SSC));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SSC_CfgPIO\r
+//* \brief Configure PIO controllers to drive SSC signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SSC_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOA, // PIO controller base address\r
+ ((unsigned int) AT91C_PA25_RK ) |\r
+ ((unsigned int) AT91C_PA22_TK ) |\r
+ ((unsigned int) AT91C_PA21_TF ) |\r
+ ((unsigned int) AT91C_PA24_RD ) |\r
+ ((unsigned int) AT91C_PA26_RF ) |\r
+ ((unsigned int) AT91C_PA23_TD ), // Peripheral A\r
+ 0); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_WDTC_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for WDTC\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_WDTC_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_SYS));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US1_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for US1\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US1_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_US1));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US1_CfgPIO\r
+//* \brief Configure PIO controllers to drive US1 signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US1_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOB, // PIO controller base address\r
+ 0, // Peripheral A\r
+ ((unsigned int) AT91C_PB26_RI1 ) |\r
+ ((unsigned int) AT91C_PB24_DSR1 ) |\r
+ ((unsigned int) AT91C_PB23_DCD1 ) |\r
+ ((unsigned int) AT91C_PB25_DTR1 )); // Peripheral B\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOA, // PIO controller base address\r
+ ((unsigned int) AT91C_PA7_SCK1 ) |\r
+ ((unsigned int) AT91C_PA8_RTS1 ) |\r
+ ((unsigned int) AT91C_PA6_TXD1 ) |\r
+ ((unsigned int) AT91C_PA5_RXD1 ) |\r
+ ((unsigned int) AT91C_PA9_CTS1 ), // Peripheral A\r
+ 0); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US0_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for US0\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US0_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_US0));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_US0_CfgPIO\r
+//* \brief Configure PIO controllers to drive US0 signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_US0_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOA, // PIO controller base address\r
+ ((unsigned int) AT91C_PA0_RXD0 ) |\r
+ ((unsigned int) AT91C_PA4_CTS0 ) |\r
+ ((unsigned int) AT91C_PA3_RTS0 ) |\r
+ ((unsigned int) AT91C_PA2_SCK0 ) |\r
+ ((unsigned int) AT91C_PA1_TXD0 ), // Peripheral A\r
+ 0); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI1_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for SPI1\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SPI1_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_SPI1));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI1_CfgPIO\r
+//* \brief Configure PIO controllers to drive SPI1 signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SPI1_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOB, // PIO controller base address\r
+ 0, // Peripheral A\r
+ ((unsigned int) AT91C_PB16_NPCS13 ) |\r
+ ((unsigned int) AT91C_PB10_NPCS11 ) |\r
+ ((unsigned int) AT91C_PB11_NPCS12 )); // Peripheral B\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOA, // PIO controller base address\r
+ 0, // Peripheral A\r
+ ((unsigned int) AT91C_PA4_NPCS13 ) |\r
+ ((unsigned int) AT91C_PA29_NPCS13 ) |\r
+ ((unsigned int) AT91C_PA21_NPCS10 ) |\r
+ ((unsigned int) AT91C_PA22_SPCK1 ) |\r
+ ((unsigned int) AT91C_PA25_NPCS11 ) |\r
+ ((unsigned int) AT91C_PA2_NPCS11 ) |\r
+ ((unsigned int) AT91C_PA24_MISO1 ) |\r
+ ((unsigned int) AT91C_PA3_NPCS12 ) |\r
+ ((unsigned int) AT91C_PA26_NPCS12 ) |\r
+ ((unsigned int) AT91C_PA23_MOSI1 )); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI0_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for SPI0\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SPI0_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_SPI0));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_SPI0_CfgPIO\r
+//* \brief Configure PIO controllers to drive SPI0 signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_SPI0_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOB, // PIO controller base address\r
+ 0, // Peripheral A\r
+ ((unsigned int) AT91C_PB13_NPCS01 ) |\r
+ ((unsigned int) AT91C_PB17_NPCS03 ) |\r
+ ((unsigned int) AT91C_PB14_NPCS02 )); // Peripheral B\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOA, // PIO controller base address\r
+ ((unsigned int) AT91C_PA16_MISO0 ) |\r
+ ((unsigned int) AT91C_PA13_NPCS01 ) |\r
+ ((unsigned int) AT91C_PA15_NPCS03 ) |\r
+ ((unsigned int) AT91C_PA17_MOSI0 ) |\r
+ ((unsigned int) AT91C_PA18_SPCK0 ) |\r
+ ((unsigned int) AT91C_PA14_NPCS02 ) |\r
+ ((unsigned int) AT91C_PA12_NPCS00 ), // Peripheral A\r
+ ((unsigned int) AT91C_PA7_NPCS01 ) |\r
+ ((unsigned int) AT91C_PA9_NPCS03 ) |\r
+ ((unsigned int) AT91C_PA8_NPCS02 )); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PITC_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for PITC\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PITC_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_SYS));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AIC_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for AIC\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AIC_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_FIQ) |\r
+ ((unsigned int) 1 << AT91C_ID_IRQ0) |\r
+ ((unsigned int) 1 << AT91C_ID_IRQ1));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AIC_CfgPIO\r
+//* \brief Configure PIO controllers to drive AIC signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AIC_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOA, // PIO controller base address\r
+ ((unsigned int) AT91C_PA30_IRQ0 ) |\r
+ ((unsigned int) AT91C_PA29_FIQ ), // Peripheral A\r
+ ((unsigned int) AT91C_PA14_IRQ1 )); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_AES_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for AES\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_AES_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_AES));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TWI_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for TWI\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TWI_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_TWI));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TWI_CfgPIO\r
+//* \brief Configure PIO controllers to drive TWI signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TWI_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOA, // PIO controller base address\r
+ ((unsigned int) AT91C_PA11_TWCK ) |\r
+ ((unsigned int) AT91C_PA10_TWD ), // Peripheral A\r
+ 0); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for ADC\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_ADC_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_ADC));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_ADC_CfgPIO\r
+//* \brief Configure PIO controllers to drive ADC signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_ADC_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOB, // PIO controller base address\r
+ 0, // Peripheral A\r
+ ((unsigned int) AT91C_PB18_ADTRG )); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWMC_CH3_CfgPIO\r
+//* \brief Configure PIO controllers to drive PWMC_CH3 signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PWMC_CH3_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOB, // PIO controller base address\r
+ ((unsigned int) AT91C_PB22_PWM3 ), // Peripheral A\r
+ ((unsigned int) AT91C_PB30_PWM3 )); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWMC_CH2_CfgPIO\r
+//* \brief Configure PIO controllers to drive PWMC_CH2 signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PWMC_CH2_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOB, // PIO controller base address\r
+ ((unsigned int) AT91C_PB21_PWM2 ), // Peripheral A\r
+ ((unsigned int) AT91C_PB29_PWM2 )); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWMC_CH1_CfgPIO\r
+//* \brief Configure PIO controllers to drive PWMC_CH1 signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PWMC_CH1_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOB, // PIO controller base address\r
+ ((unsigned int) AT91C_PB20_PWM1 ), // Peripheral A\r
+ ((unsigned int) AT91C_PB28_PWM1 )); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWMC_CH0_CfgPIO\r
+//* \brief Configure PIO controllers to drive PWMC_CH0 signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PWMC_CH0_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOB, // PIO controller base address\r
+ ((unsigned int) AT91C_PB19_PWM0 ), // Peripheral A\r
+ ((unsigned int) AT91C_PB27_PWM0 )); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_RTTC_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for RTTC\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_RTTC_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_SYS));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_UDP_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for UDP\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_UDP_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_UDP));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TDES_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for TDES\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TDES_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_TDES));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_EMAC_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for EMAC\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_EMAC_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_EMAC));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_EMAC_CfgPIO\r
+//* \brief Configure PIO controllers to drive EMAC signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_EMAC_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOB, // PIO controller base address\r
+ ((unsigned int) AT91C_PB2_ETX0 ) |\r
+ ((unsigned int) AT91C_PB12_ETXER ) |\r
+ ((unsigned int) AT91C_PB16_ECOL ) |\r
+ ((unsigned int) AT91C_PB11_ETX3 ) |\r
+ ((unsigned int) AT91C_PB6_ERX1 ) |\r
+ ((unsigned int) AT91C_PB15_ERXDV ) |\r
+ ((unsigned int) AT91C_PB13_ERX2 ) |\r
+ ((unsigned int) AT91C_PB3_ETX1 ) |\r
+ ((unsigned int) AT91C_PB8_EMDC ) |\r
+ ((unsigned int) AT91C_PB5_ERX0 ) |\r
+ //((unsigned int) AT91C_PB18_EF100 ) |\r
+ ((unsigned int) AT91C_PB14_ERX3 ) |\r
+ ((unsigned int) AT91C_PB4_ECRS_ECRSDV) |\r
+ ((unsigned int) AT91C_PB1_ETXEN ) |\r
+ ((unsigned int) AT91C_PB10_ETX2 ) |\r
+ ((unsigned int) AT91C_PB0_ETXCK_EREFCK) |\r
+ ((unsigned int) AT91C_PB9_EMDIO ) |\r
+ ((unsigned int) AT91C_PB7_ERXER ) |\r
+ ((unsigned int) AT91C_PB17_ERXCK ), // Peripheral A\r
+ 0); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TC0_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for TC0\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TC0_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_TC0));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TC0_CfgPIO\r
+//* \brief Configure PIO controllers to drive TC0 signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TC0_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOB, // PIO controller base address\r
+ ((unsigned int) AT91C_PB23_TIOA0 ) |\r
+ ((unsigned int) AT91C_PB24_TIOB0 ), // Peripheral A\r
+ ((unsigned int) AT91C_PB12_TCLK0 )); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TC1_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for TC1\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TC1_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_TC1));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TC1_CfgPIO\r
+//* \brief Configure PIO controllers to drive TC1 signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TC1_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOB, // PIO controller base address\r
+ ((unsigned int) AT91C_PB25_TIOA1 ) |\r
+ ((unsigned int) AT91C_PB26_TIOB1 ), // Peripheral A\r
+ ((unsigned int) AT91C_PB19_TCLK1 )); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TC2_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for TC2\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TC2_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_TC2));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_TC2_CfgPIO\r
+//* \brief Configure PIO controllers to drive TC2 signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_TC2_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOB, // PIO controller base address\r
+ ((unsigned int) AT91C_PB28_TIOB2 ) |\r
+ ((unsigned int) AT91C_PB27_TIOA2 ), // Peripheral A\r
+ 0); // Peripheral B\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOA, // PIO controller base address\r
+ 0, // Peripheral A\r
+ ((unsigned int) AT91C_PA15_TCLK2 )); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_MC_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for MC\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_MC_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_SYS));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIOA_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for PIOA\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIOA_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_PIOA));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PIOB_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for PIOB\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PIOB_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_PIOB));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for CAN\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CAN_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_CAN));\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_CAN_CfgPIO\r
+//* \brief Configure PIO controllers to drive CAN signals\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_CAN_CfgPIO (void)\r
+{\r
+ // Configure PIO controllers to periph mode\r
+ AT91F_PIO_CfgPeriph(\r
+ AT91C_BASE_PIOA, // PIO controller base address\r
+ ((unsigned int) AT91C_PA20_CANTX ) |\r
+ ((unsigned int) AT91C_PA19_CANRX ), // Peripheral A\r
+ 0); // Peripheral B\r
+}\r
+\r
+//*----------------------------------------------------------------------------\r
+//* \fn AT91F_PWMC_CfgPMC\r
+//* \brief Enable Peripheral clock in PMC for PWMC\r
+//*----------------------------------------------------------------------------\r
+__inline void AT91F_PWMC_CfgPMC (void)\r
+{\r
+ AT91F_PMC_EnablePeriphClock(\r
+ AT91C_BASE_PMC, // PIO controller base address\r
+ ((unsigned int) 1 << AT91C_ID_PWMC));\r
+}\r
+\r
+#endif // lib_AT91SAM7X256_H\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Implementation of functions defined in portable.h for the Atmel ARM7 port.\r
+ *----------------------------------------------------------*/\r
+\r
+\r
+/* Standard includes. */\r
+#include <stdlib.h>\r
+#include <intrinsic.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Constants required to setup the initial stack. */\r
+#define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x3f ) /* System mode, THUMB mode, interrupts enabled. */\r
+#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 )\r
+\r
+/* Constants required to setup the PIT. */\r
+#define portPIT_CLOCK_DIVISOR ( ( unsigned portLONG ) 16 )\r
+#define portPIT_COUNTER_VALUE ( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_RATE_MS )\r
+\r
+/* Constants required to handle critical sections. */\r
+#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 )\r
+\r
+\r
+#define portINT_LEVEL_SENSITIVE 0\r
+#define portPIT_ENABLE ( ( unsigned portSHORT ) 0x1 << 24 )\r
+#define portPIT_INT_ENABLE ( ( unsigned portSHORT ) 0x1 << 25 )\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Setup the PIT to generate the tick interrupts. */\r
+static void prvSetupTimerInterrupt( void );\r
+\r
+/* ulCriticalNesting will get set to zero when the first task starts. It\r
+cannot be initialised to 0 as this will cause interrupts to be enabled\r
+during the kernel initialisation process. */\r
+unsigned portLONG ulCriticalNesting = ( unsigned portLONG ) 9999;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Initialise the stack of a task to look exactly as if a call to\r
+ * portSAVE_CONTEXT had been called.\r
+ *\r
+ * See header file for description.\r
+ */\r
+portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
+{\r
+portSTACK_TYPE *pxOriginalTOS;\r
+\r
+ pxOriginalTOS = pxTopOfStack;\r
+\r
+ /* Setup the initial stack of the task. The stack is set exactly as\r
+ expected by the portRESTORE_CONTEXT() macro. */\r
+\r
+ /* First on the stack is the return address - which in this case is the\r
+ start of the task. The offset is added to make the return address appear\r
+ as it would within an IRQ ISR. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; \r
+ pxTopOfStack--;\r
+\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */\r
+ pxTopOfStack--; \r
+\r
+ /* When the task starts is will expect to find the function parameter in\r
+ R0. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */\r
+ pxTopOfStack--;\r
+\r
+ /* The status register is set for system mode, with interrupts enabled. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR;\r
+ pxTopOfStack--;\r
+\r
+ /* Interrupt flags cannot always be stored on the stack and will\r
+ instead be stored in a variable, which is then saved as part of the\r
+ tasks context. */\r
+ *pxTopOfStack = portNO_CRITICAL_NESTING;\r
+\r
+ return pxTopOfStack; \r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portBASE_TYPE xPortStartScheduler( void )\r
+{\r
+extern void vPortStartFirstTask( void );\r
+\r
+ /* Start the timer that generates the tick ISR. Interrupts are disabled\r
+ here already. */\r
+ prvSetupTimerInterrupt();\r
+\r
+ /* Start the first task. */\r
+ vPortStartFirstTask(); \r
+\r
+ /* Should not get here! */\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEndScheduler( void )\r
+{\r
+ /* It is unlikely that the ARM port will require this function as there\r
+ is nothing to return to. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if configUSE_PREEMPTION == 0\r
+\r
+ /* The cooperative scheduler requires a normal IRQ service routine to\r
+ simply increment the system tick. */\r
+ static __arm __irq void vPortNonPreemptiveTick( void );\r
+ static __arm __irq void vPortNonPreemptiveTick( void )\r
+ {\r
+ unsigned portLONG ulDummy;\r
+ \r
+ /* Increment the tick count - which may wake some tasks but as the\r
+ preemptive scheduler is not being used any woken task is not given\r
+ processor time no matter what its priority. */\r
+ vTaskIncrementTick();\r
+ \r
+ /* Clear the PIT interrupt. */\r
+ ulDummy = AT91C_BASE_PITC->PITC_PIVR;\r
+ \r
+ /* End the interrupt in the AIC. */\r
+ AT91C_BASE_AIC->AIC_EOICR = ulDummy;\r
+ }\r
+\r
+#else\r
+\r
+ /* Currently the IAR port requires the preemptive tick function to be\r
+ defined in an asm file. */\r
+\r
+#endif\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupTimerInterrupt( void )\r
+{\r
+AT91PS_PITC pxPIT = AT91C_BASE_PITC;\r
+\r
+ /* Setup the AIC for PIT interrupts. The interrupt routine chosen depends\r
+ on whether the preemptive or cooperative scheduler is being used. */\r
+ #if configUSE_PREEMPTION == 0\r
+\r
+ AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vPortNonPreemptiveTick );\r
+\r
+ #else\r
+ \r
+ extern void ( vPortPreemptiveTick )( void );\r
+ AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vPortPreemptiveTick );\r
+\r
+ #endif\r
+\r
+ /* Configure the PIT period. */\r
+ pxPIT->PITC_PIMR = portPIT_ENABLE | portPIT_INT_ENABLE | portPIT_COUNTER_VALUE;\r
+\r
+ /* Enable the interrupt. Global interrupts are disables at this point so\r
+ this is safe. */\r
+ AT91F_AIC_EnableIt( AT91C_BASE_AIC, AT91C_ID_SYS );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEnterCritical( void )\r
+{\r
+ /* Disable interrupts first! */\r
+ __disable_interrupt();\r
+\r
+ /* Now interrupts are disabled ulCriticalNesting can be accessed\r
+ directly. Increment ulCriticalNesting to keep a count of how many times\r
+ portENTER_CRITICAL() has been called. */\r
+ ulCriticalNesting++;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortExitCritical( void )\r
+{\r
+ if( ulCriticalNesting > portNO_CRITICAL_NESTING )\r
+ {\r
+ /* Decrement the nesting count as we are leaving a critical section. */\r
+ ulCriticalNesting--;\r
+\r
+ /* If the nesting level has reached zero then interrupts should be\r
+ re-enabled. */\r
+ if( ulCriticalNesting == portNO_CRITICAL_NESTING )\r
+ {\r
+ __enable_interrupt();\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+ RSEG ICODE:CODE\r
+ CODE32\r
+\r
+ EXTERN vTaskSwitchContext\r
+ EXTERN vTaskIncrementTick\r
+\r
+ PUBLIC vPortYieldProcessor\r
+ PUBLIC vPortPreemptiveTick\r
+ PUBLIC vPortStartFirstTask\r
+\r
+#include "AT91SAM7S64_inc.h"\r
+#include "ISR_Support.h"\r
+\r
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+; Starting the first task is just a matter of restoring the context that\r
+; was created by pxPortInitialiseStack().\r
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+vPortStartFirstTask:\r
+ portRESTORE_CONTEXT\r
+\r
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+; Manual context switch function. This is the SWI hander.\r
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+vPortYieldProcessor:\r
+ ADD LR, LR, #4 ; Add 4 to the LR to make the LR appear exactly \r
+ ; as if the context was saved during and IRQ \r
+ ; handler.\r
+ \r
+ portSAVE_CONTEXT ; Save the context of the current task...\r
+ LDR R0, =vTaskSwitchContext ; before selecting the next task to execute.\r
+ mov lr, pc\r
+ BX R0\r
+ portRESTORE_CONTEXT ; Restore the context of the selected task.\r
+\r
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+; Preemptive context switch function. This will only ever get installed if\r
+; portUSE_PREEMPTION is set to 1 in portmacro.h.\r
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+vPortPreemptiveTick:\r
+ portSAVE_CONTEXT ; Save the context of the current task.\r
+\r
+ LDR R0, =vTaskIncrementTick ; Increment the tick count - this may wake a task.\r
+ mov lr, pc\r
+ BX R0\r
+ LDR R0, =vTaskSwitchContext ; Select the next task to execute.\r
+ mov lr, pc\r
+ BX R0\r
+\r
+ LDR R14, =AT91C_BASE_PITC ; Clear the PIT interrupt\r
+ LDR R0, [R14, #PITC_PIVR ]\r
+\r
+ LDR R14, =AT91C_BASE_AIC ; Mark the End of Interrupt on the AIC\r
+ STR R14, [R14, #AIC_EOICR]\r
+\r
+ portRESTORE_CONTEXT ; Restore the context of the selected task.\r
+\r
+\r
+ END\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+#include <intrinsic.h>\r
+\r
+/*-----------------------------------------------------------\r
+ * Port specific definitions.\r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the\r
+ * given hardware and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *-----------------------------------------------------------\r
+ */\r
+\r
+/* Type definitions. */\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE double\r
+#define portLONG long\r
+#define portSHORT short\r
+#define portSTACK_TYPE unsigned portLONG\r
+#define portBASE_TYPE portLONG\r
+\r
+#if( configUSE_16_BIT_TICKS == 1 )\r
+ typedef unsigned portSHORT portTickType;\r
+ #define portMAX_DELAY ( portTickType ) 0xffff\r
+#else\r
+ typedef unsigned portLONG portTickType;\r
+ #define portMAX_DELAY ( portTickType ) 0xffffffff\r
+#endif\r
+/*-----------------------------------------------------------*/ \r
+\r
+/* Hardware specifics. */\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) \r
+#define portBYTE_ALIGNMENT 4\r
+#define portYIELD() asm ( "SWI 0" )\r
+#define portNOP() asm ( "NOP" )\r
+/*-----------------------------------------------------------*/ \r
+\r
+/* Critical section handling. */\r
+__arm __interwork void vPortDisableInterruptsFromThumb( void );\r
+__arm __interwork void vPortEnableInterruptsFromThumb( void );\r
+__arm __interwork void vPortEnterCritical( void );\r
+__arm __interwork void vPortExitCritical( void );\r
+\r
+#define portDISABLE_INTERRUPTS() __disable_interrupt()\r
+#define portENABLE_INTERRUPTS() __enable_interrupt()\r
+#define portENTER_CRITICAL() vPortEnterCritical()\r
+#define portEXIT_CRITICAL() vPortExitCritical()\r
+/*-----------------------------------------------------------*/ \r
+\r
+/* Task utilities. */\r
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \\r
+{ \\r
+extern void vTaskSwitchContext( void ); \\r
+ \\r
+ if( xSwitchRequired ) \\r
+ { \\r
+ vTaskSwitchContext(); \\r
+ } \\r
+}\r
+/*-----------------------------------------------------------*/ \r
+\r
+/* Compiler specifics. */\r
+#define inline\r
+/*-----------------------------------------------------------*/ \r
+\r
+/* Task function macros as described on the FreeRTOS.org WEB site. */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )\r
+\r
+#endif /* PORTMACRO_H */\r
+\r
+\r
--- /dev/null
+ EXTERN pxCurrentTCB\r
+ EXTERN ulCriticalNesting\r
+\r
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+; Context save and restore macro definitions\r
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+\r
+portSAVE_CONTEXT MACRO\r
+\r
+ ; Push R0 as we are going to use the register. \r
+ STMDB SP!, {R0}\r
+\r
+ ; Set R0 to point to the task stack pointer. \r
+ STMDB SP, {SP}^\r
+ NOP\r
+ SUB SP, SP, #4\r
+ LDMIA SP!, {R0}\r
+\r
+ ; Push the return address onto the stack. \r
+ STMDB R0!, {LR}\r
+\r
+ ; Now we have saved LR we can use it instead of R0. \r
+ MOV LR, R0\r
+\r
+ ; Pop R0 so we can save it onto the system mode stack. \r
+ LDMIA SP!, {R0}\r
+\r
+ ; Push all the system mode registers onto the task stack. \r
+ STMDB LR, {R0-LR}^\r
+ NOP\r
+ SUB LR, LR, #60\r
+\r
+ ; Push the SPSR onto the task stack. \r
+ MRS R0, SPSR\r
+ STMDB LR!, {R0}\r
+\r
+ LDR R0, =ulCriticalNesting \r
+ LDR R0, [R0]\r
+ STMDB LR!, {R0}\r
+\r
+ ; Store the new top of stack for the task. \r
+ LDR R1, =pxCurrentTCB\r
+ LDR R0, [R1]\r
+ STR LR, [R0]\r
+\r
+ ENDM\r
+\r
+\r
+portRESTORE_CONTEXT MACRO\r
+\r
+ ; Set the LR to the task stack. \r
+ LDR R1, =pxCurrentTCB\r
+ LDR R0, [R1]\r
+ LDR LR, [R0]\r
+\r
+ ; The critical nesting depth is the first item on the stack. \r
+ ; Load it into the ulCriticalNesting variable. \r
+ LDR R0, =ulCriticalNesting\r
+ LDMFD LR!, {R1}\r
+ STR R1, [R0]\r
+\r
+ ; Get the SPSR from the stack. \r
+ LDMFD LR!, {R0}\r
+ MSR SPSR_cxsf, R0\r
+\r
+ ; Restore all system mode registers for the task. \r
+ LDMFD LR, {R0-R14}^\r
+ NOP\r
+\r
+ ; Restore the return address. \r
+ LDR LR, [LR, #+60]\r
+\r
+ ; And return - correcting the offset in the LR to obtain the \r
+ ; correct address. \r
+ SUBS PC, LR, #4\r
+\r
+ ENDM\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Implementation of functions defined in portable.h for the Philips ARM7 port.\r
+ *----------------------------------------------------------*/\r
+\r
+/*\r
+ Changes from V3.2.2\r
+\r
+ + Bug fix - The prescale value for the timer setup is now written to T0PR \r
+ instead of T0PC. This bug would have had no effect unless a prescale \r
+ value was actually used.\r
+*/\r
+\r
+/* Standard includes. */\r
+#include <stdlib.h>\r
+#include <intrinsic.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Constants required to setup the tick ISR. */\r
+#define portENABLE_TIMER ( ( unsigned portCHAR ) 0x01 )\r
+#define portPRESCALE_VALUE 0x00\r
+#define portINTERRUPT_ON_MATCH ( ( unsigned portLONG ) 0x01 )\r
+#define portRESET_COUNT_ON_MATCH ( ( unsigned portLONG ) 0x02 )\r
+\r
+/* Constants required to setup the initial stack. */\r
+#define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x3f ) /* System mode, THUMB mode, interrupts enabled. */\r
+#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 )\r
+\r
+/* Constants required to setup the PIT. */\r
+#define portPIT_CLOCK_DIVISOR ( ( unsigned portLONG ) 16 )\r
+#define portPIT_COUNTER_VALUE ( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_RATE_MS )\r
+\r
+/* Constants required to handle interrupts. */\r
+#define portTIMER_MATCH_ISR_BIT ( ( unsigned portCHAR ) 0x01 )\r
+#define portCLEAR_VIC_INTERRUPT ( ( unsigned portLONG ) 0 )\r
+\r
+/* Constants required to handle critical sections. */\r
+#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 )\r
+\r
+\r
+#define portINT_LEVEL_SENSITIVE 0\r
+#define portPIT_ENABLE ( ( unsigned portSHORT ) 0x1 << 24 )\r
+#define portPIT_INT_ENABLE ( ( unsigned portSHORT ) 0x1 << 25 )\r
+\r
+/* Constants required to setup the VIC for the tick ISR. */\r
+#define portTIMER_VIC_CHANNEL ( ( unsigned portLONG ) 0x0004 )\r
+#define portTIMER_VIC_CHANNEL_BIT ( ( unsigned portLONG ) 0x0010 )\r
+#define portTIMER_VIC_ENABLE ( ( unsigned portLONG ) 0x0020 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Setup the PIT to generate the tick interrupts. */\r
+static void prvSetupTimerInterrupt( void );\r
+\r
+/* ulCriticalNesting will get set to zero when the first task starts. It\r
+cannot be initialised to 0 as this will cause interrupts to be enabled\r
+during the kernel initialisation process. */\r
+unsigned portLONG ulCriticalNesting = ( unsigned portLONG ) 9999;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Initialise the stack of a task to look exactly as if a call to\r
+ * portSAVE_CONTEXT had been called.\r
+ *\r
+ * See header file for description.\r
+ */\r
+portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
+{\r
+portSTACK_TYPE *pxOriginalTOS;\r
+\r
+ pxOriginalTOS = pxTopOfStack;\r
+\r
+ /* Setup the initial stack of the task. The stack is set exactly as\r
+ expected by the portRESTORE_CONTEXT() macro. */\r
+\r
+ /* First on the stack is the return address - which in this case is the\r
+ start of the task. The offset is added to make the return address appear\r
+ as it would within an IRQ ISR. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; \r
+ pxTopOfStack--;\r
+\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */\r
+ pxTopOfStack--; \r
+\r
+ /* When the task starts is will expect to find the function parameter in\r
+ R0. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */\r
+ pxTopOfStack--;\r
+\r
+ /* The status register is set for system mode, with interrupts enabled. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR;\r
+ pxTopOfStack--;\r
+\r
+ /* Interrupt flags cannot always be stored on the stack and will\r
+ instead be stored in a variable, which is then saved as part of the\r
+ tasks context. */\r
+ *pxTopOfStack = portNO_CRITICAL_NESTING;\r
+\r
+ return pxTopOfStack; \r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portBASE_TYPE xPortStartScheduler( void )\r
+{\r
+extern void vPortStartFirstTask( void );\r
+\r
+ /* Start the timer that generates the tick ISR. Interrupts are disabled\r
+ here already. */\r
+ prvSetupTimerInterrupt();\r
+\r
+ /* Start the first task. */\r
+ vPortStartFirstTask(); \r
+\r
+ /* Should not get here! */\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEndScheduler( void )\r
+{\r
+ /* It is unlikely that the ARM port will require this function as there\r
+ is nothing to return to. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if configUSE_PREEMPTION == 0\r
+\r
+ /* The cooperative scheduler requires a normal IRQ service routine to\r
+ simply increment the system tick. */\r
+ static __arm __irq void vPortNonPreemptiveTick( void );\r
+ static __arm __irq void vPortNonPreemptiveTick( void )\r
+ {\r
+ /* Increment the tick count - which may wake some tasks but as the\r
+ preemptive scheduler is not being used any woken task is not given\r
+ processor time no matter what its priority. */\r
+ vTaskIncrementTick();\r
+ \r
+ /* Ready for the next interrupt. */\r
+ T0IR = portTIMER_MATCH_ISR_BIT;\r
+ VICVectAddr = portCLEAR_VIC_INTERRUPT;\r
+ }\r
+\r
+#else\r
+\r
+ /* This function is called from an asm wrapper, so does not require the __irq\r
+ keyword. */\r
+ void vPortPreemptiveTick( void );\r
+ void vPortPreemptiveTick( void )\r
+ {\r
+ /* Increment the tick counter. */\r
+ vTaskIncrementTick();\r
+ \r
+ /* The new tick value might unblock a task. Ensure the highest task that\r
+ is ready to execute is the task that will execute when the tick ISR\r
+ exits. */\r
+ vTaskSwitchContext();\r
+ \r
+ /* Ready for the next interrupt. */\r
+ T0IR = portTIMER_MATCH_ISR_BIT;\r
+ VICVectAddr = portCLEAR_VIC_INTERRUPT;\r
+ }\r
+\r
+#endif\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupTimerInterrupt( void )\r
+{\r
+unsigned portLONG ulCompareMatch;\r
+\r
+ /* A 1ms tick does not require the use of the timer prescale. This is\r
+ defaulted to zero but can be used if necessary. */\r
+ T0PR = portPRESCALE_VALUE;\r
+\r
+ /* Calculate the match value required for our wanted tick rate. */\r
+ ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;\r
+\r
+ /* Protect against divide by zero. Using an if() statement still results\r
+ in a warning - hence the #if. */\r
+ #if portPRESCALE_VALUE != 0\r
+ {\r
+ ulCompareMatch /= ( portPRESCALE_VALUE + 1 );\r
+ }\r
+ #endif\r
+\r
+ T0MR0 = ulCompareMatch;\r
+\r
+ /* Generate tick with timer 0 compare match. */\r
+ T0MCR = portRESET_COUNT_ON_MATCH | portINTERRUPT_ON_MATCH;\r
+\r
+ /* Setup the VIC for the timer. */\r
+ VICIntSelect &= ~( portTIMER_VIC_CHANNEL_BIT );\r
+ VICIntEnable |= portTIMER_VIC_CHANNEL_BIT;\r
+ \r
+ /* The ISR installed depends on whether the preemptive or cooperative\r
+ scheduler is being used. */\r
+ #if configUSE_PREEMPTION == 1\r
+ { \r
+ extern void ( vPortPreemptiveTickEntry )( void );\r
+\r
+ VICVectAddr0 = ( unsigned portLONG ) vPortPreemptiveTickEntry;\r
+ }\r
+ #else\r
+ {\r
+ extern void ( vNonPreemptiveTick )( void );\r
+\r
+ VICVectAddr0 = ( portLONG ) vPortNonPreemptiveTick;\r
+ }\r
+ #endif\r
+\r
+ VICVectCntl0 = portTIMER_VIC_CHANNEL | portTIMER_VIC_ENABLE;\r
+\r
+ /* Start the timer - interrupts are disabled when this function is called\r
+ so it is okay to do this here. */\r
+ T0TCR = portENABLE_TIMER;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEnterCritical( void )\r
+{\r
+ /* Disable interrupts first! */\r
+ __disable_interrupt();\r
+\r
+ /* Now interrupts are disabled ulCriticalNesting can be accessed\r
+ directly. Increment ulCriticalNesting to keep a count of how many times\r
+ portENTER_CRITICAL() has been called. */\r
+ ulCriticalNesting++;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortExitCritical( void )\r
+{\r
+ if( ulCriticalNesting > portNO_CRITICAL_NESTING )\r
+ {\r
+ /* Decrement the nesting count as we are leaving a critical section. */\r
+ ulCriticalNesting--;\r
+\r
+ /* If the nesting level has reached zero then interrupts should be\r
+ re-enabled. */\r
+ if( ulCriticalNesting == portNO_CRITICAL_NESTING )\r
+ {\r
+ __enable_interrupt();\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+ RSEG ICODE:CODE\r
+ CODE32\r
+\r
+ EXTERN vTaskSwitchContext\r
+ EXTERN vTaskIncrementTick\r
+ EXTERN vPortPreemptiveTick\r
+ \r
+ PUBLIC vPortPreemptiveTickEntry\r
+ PUBLIC vPortYieldProcessor\r
+ PUBLIC vPortStartFirstTask\r
+\r
+#include "FreeRTOSConfig.h"\r
+#include "ISR_Support.h"\r
+\r
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+; Starting the first task is just a matter of restoring the context that\r
+; was created by pxPortInitialiseStack().\r
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+vPortStartFirstTask:\r
+ portRESTORE_CONTEXT\r
+\r
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+; Manual context switch function. This is the SWI hander.\r
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+vPortYieldProcessor:\r
+ ADD LR, LR, #4 ; Add 4 to the LR to make the LR appear exactly\r
+ ; as if the context was saved during and IRQ\r
+ ; handler.\r
+ \r
+ portSAVE_CONTEXT ; Save the context of the current task...\r
+ LDR R0, =vTaskSwitchContext ; before selecting the next task to execute.\r
+ mov lr, pc\r
+ BX R0\r
+ portRESTORE_CONTEXT ; Restore the context of the selected task.\r
+\r
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+; Preemptive context switch function. This will only ever get installed if\r
+; portUSE_PREEMPTION is set to 1 in portmacro.h.\r
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+vPortPreemptiveTickEntry:\r
+#if configUSE_PREEMPTION == 1\r
+ portSAVE_CONTEXT ; Save the context of the current task...\r
+ LDR R0, =vPortPreemptiveTick; before selecting the next task to execute.\r
+ mov lr, pc\r
+ BX R0\r
+ portRESTORE_CONTEXT ; Restore the context of the selected task.\r
+#endif\r
+\r
+ END\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+#include <intrinsic.h>\r
+\r
+/*-----------------------------------------------------------\r
+ * Port specific definitions.\r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the\r
+ * given hardware and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *-----------------------------------------------------------\r
+ */\r
+\r
+/* Type definitions. */\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE double\r
+#define portLONG long\r
+#define portSHORT short\r
+#define portSTACK_TYPE unsigned portLONG\r
+#define portBASE_TYPE portLONG\r
+\r
+#if( configUSE_16_BIT_TICKS == 1 )\r
+ typedef unsigned portSHORT portTickType;\r
+ #define portMAX_DELAY ( portTickType ) 0xffff\r
+#else\r
+ typedef unsigned portLONG portTickType;\r
+ #define portMAX_DELAY ( portTickType ) 0xffffffff\r
+#endif\r
+/*-----------------------------------------------------------*/ \r
+\r
+/* Hardware specifics. */\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) \r
+#define portBYTE_ALIGNMENT 4\r
+#define portYIELD() asm ( "SWI 0" )\r
+#define portNOP() asm ( "NOP" )\r
+/*-----------------------------------------------------------*/ \r
+\r
+/* Critical section handling. */\r
+__arm __interwork void vPortDisableInterruptsFromThumb( void );\r
+__arm __interwork void vPortEnableInterruptsFromThumb( void );\r
+__arm __interwork void vPortEnterCritical( void );\r
+__arm __interwork void vPortExitCritical( void );\r
+\r
+#define portDISABLE_INTERRUPTS() __disable_interrupt()\r
+#define portENABLE_INTERRUPTS() __enable_interrupt()\r
+#define portENTER_CRITICAL() vPortEnterCritical()\r
+#define portEXIT_CRITICAL() vPortExitCritical()\r
+/*-----------------------------------------------------------*/ \r
+\r
+/* Task utilities. */\r
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \\r
+{ \\r
+extern void vTaskSwitchContext( void ); \\r
+ \\r
+ if( xSwitchRequired ) \\r
+ { \\r
+ vTaskSwitchContext(); \\r
+ } \\r
+}\r
+/*-----------------------------------------------------------*/ \r
+\r
+/* Compiler specifics. */\r
+#define inline\r
+/*-----------------------------------------------------------*/ \r
+\r
+/* Task function macros as described on the FreeRTOS.org WEB site. */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )\r
+\r
+#endif /* PORTMACRO_H */\r
+\r
+\r
--- /dev/null
+ EXTERN pxCurrentTCB\r
+ EXTERN ulCriticalNesting\r
+\r
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+; Context save and restore macro definitions\r
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+\r
+portSAVE_CONTEXT MACRO\r
+\r
+ ; Push R0 as we are going to use the register. \r
+ STMDB SP!, {R0}\r
+\r
+ ; Set R0 to point to the task stack pointer. \r
+ STMDB SP, {SP}^\r
+ NOP\r
+ SUB SP, SP, #4\r
+ LDMIA SP!, {R0}\r
+\r
+ ; Push the return address onto the stack. \r
+ STMDB R0!, {LR}\r
+\r
+ ; Now we have saved LR we can use it instead of R0. \r
+ MOV LR, R0\r
+\r
+ ; Pop R0 so we can save it onto the system mode stack. \r
+ LDMIA SP!, {R0}\r
+\r
+ ; Push all the system mode registers onto the task stack. \r
+ STMDB LR, {R0-LR}^\r
+ NOP\r
+ SUB LR, LR, #60\r
+\r
+ ; Push the SPSR onto the task stack. \r
+ MRS R0, SPSR\r
+ STMDB LR!, {R0}\r
+\r
+ LDR R0, =ulCriticalNesting \r
+ LDR R0, [R0]\r
+ STMDB LR!, {R0}\r
+\r
+ ; Store the new top of stack for the task. \r
+ LDR R1, =pxCurrentTCB\r
+ LDR R0, [R1]\r
+ STR LR, [R0]\r
+\r
+ ENDM\r
+\r
+\r
+portRESTORE_CONTEXT MACRO\r
+\r
+ ; Set the LR to the task stack. \r
+ LDR R1, =pxCurrentTCB\r
+ LDR R0, [R1]\r
+ LDR LR, [R0]\r
+\r
+ ; The critical nesting depth is the first item on the stack. \r
+ ; Load it into the ulCriticalNesting variable. \r
+ LDR R0, =ulCriticalNesting\r
+ LDMFD LR!, {R1}\r
+ STR R1, [R0]\r
+\r
+ ; Get the SPSR from the stack. \r
+ LDMFD LR!, {R0}\r
+ MSR SPSR_cxsf, R0\r
+\r
+ ; Restore all system mode registers for the task. \r
+ LDMFD LR, {R0-R14}^\r
+ NOP\r
+\r
+ ; Restore the return address. \r
+ LDR LR, [LR, #+60]\r
+\r
+ ; And return - correcting the offset in the LR to obtain the \r
+ ; correct address. \r
+ SUBS PC, LR, #4\r
+\r
+ ENDM\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Implementation of functions defined in portable.h for the ST STR71x ARM7 \r
+ * port.\r
+ *----------------------------------------------------------*/\r
+\r
+/* Library includes. */\r
+#include "wdg.h"\r
+#include "eic.h"\r
+\r
+/* Standard includes. */\r
+#include <stdlib.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Constants required to setup the initial stack. */\r
+#define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x3f ) /* System mode, THUMB mode, interrupts enabled. */\r
+#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 )\r
+\r
+/* Constants required to handle critical sections. */\r
+#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Setup the watchdog to generate the tick interrupts. */\r
+static void prvSetupTimerInterrupt( void );\r
+\r
+/* ulCriticalNesting will get set to zero when the first task starts. It\r
+cannot be initialised to 0 as this will cause interrupts to be enabled\r
+during the kernel initialisation process. */\r
+unsigned portLONG ulCriticalNesting = ( unsigned portLONG ) 9999;\r
+\r
+/* Tick interrupt routines for cooperative and preemptive operation \r
+respectively. The preemptive version is not defined as __irq as it is called\r
+from an asm wrapper function. */\r
+__arm __irq void vPortNonPreemptiveTick( void );\r
+void vPortPreemptiveTick( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Initialise the stack of a task to look exactly as if a call to\r
+ * portSAVE_CONTEXT had been called.\r
+ *\r
+ * See header file for description.\r
+ */\r
+portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
+{\r
+portSTACK_TYPE *pxOriginalTOS;\r
+\r
+ pxOriginalTOS = pxTopOfStack;\r
+\r
+ /* Setup the initial stack of the task. The stack is set exactly as\r
+ expected by the portRESTORE_CONTEXT() macro. */\r
+\r
+ /* First on the stack is the return address - which in this case is the\r
+ start of the task. The offset is added to make the return address appear\r
+ as it would within an IRQ ISR. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; \r
+ pxTopOfStack--;\r
+\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */\r
+ pxTopOfStack--; \r
+\r
+ /* When the task starts is will expect to find the function parameter in\r
+ R0. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */\r
+ pxTopOfStack--;\r
+\r
+ /* The status register is set for system mode, with interrupts enabled. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR;\r
+ pxTopOfStack--;\r
+\r
+ /* Interrupt flags cannot always be stored on the stack and will\r
+ instead be stored in a variable, which is then saved as part of the\r
+ tasks context. */\r
+ *pxTopOfStack = portNO_CRITICAL_NESTING;\r
+\r
+ return pxTopOfStack; \r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portBASE_TYPE xPortStartScheduler( void )\r
+{\r
+extern void vPortStartFirstTask( void );\r
+\r
+ /* Start the timer that generates the tick ISR. Interrupts are disabled\r
+ here already. */\r
+ prvSetupTimerInterrupt();\r
+\r
+ /* Start the first task. */\r
+ vPortStartFirstTask(); \r
+\r
+ /* Should not get here! */\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEndScheduler( void )\r
+{\r
+ /* It is unlikely that the ARM port will require this function as there\r
+ is nothing to return to. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The cooperative scheduler requires a normal IRQ service routine to\r
+simply increment the system tick. */\r
+__arm __irq void vPortNonPreemptiveTick( void )\r
+{\r
+ /* Increment the tick count - which may wake some tasks but as the\r
+ preemptive scheduler is not being used any woken task is not given\r
+ processor time no matter what its priority. */\r
+ vTaskIncrementTick();\r
+\r
+ /* Clear the interrupt in the watchdog and EIC. */\r
+ WDG->SR = 0x0000;\r
+ portCLEAR_EIC(); \r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This function is called from an asm wrapper, so does not require the __irq\r
+keyword. */\r
+void vPortPreemptiveTick( void )\r
+{\r
+ /* Increment the tick counter. */\r
+ vTaskIncrementTick();\r
+\r
+ /* The new tick value might unblock a task. Ensure the highest task that\r
+ is ready to execute is the task that will execute when the tick ISR \r
+ exits. */\r
+ vTaskSwitchContext();\r
+\r
+ /* Clear the interrupt in the watchdog and EIC. */\r
+ WDG->SR = 0x0000;\r
+ portCLEAR_EIC(); \r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupTimerInterrupt( void )\r
+{\r
+ /* Set the watchdog up to generate a periodic tick. */\r
+ WDG_ECITConfig( DISABLE );\r
+ WDG_CntOnOffConfig( DISABLE );\r
+ WDG_PeriodValueConfig( configTICK_RATE_HZ );\r
+\r
+ /* Setup the tick interrupt in the EIC. */\r
+ EIC_IRQChannelPriorityConfig( WDG_IRQChannel, 1 );\r
+ EIC_IRQChannelConfig( WDG_IRQChannel, ENABLE );\r
+ EIC_IRQConfig( ENABLE );\r
+ WDG_ECITConfig( ENABLE );\r
+\r
+ /* Start the timer - interrupts are actually disabled at this point so\r
+ it is safe to do this here. */\r
+ WDG_CntOnOffConfig( ENABLE );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+__arm __interwork void vPortEnterCritical( void )\r
+{\r
+ /* Disable interrupts first! */\r
+ __disable_interrupt();\r
+\r
+ /* Now interrupts are disabled ulCriticalNesting can be accessed\r
+ directly. Increment ulCriticalNesting to keep a count of how many times\r
+ portENTER_CRITICAL() has been called. */\r
+ ulCriticalNesting++;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+__arm __interwork void vPortExitCritical( void )\r
+{\r
+ if( ulCriticalNesting > portNO_CRITICAL_NESTING )\r
+ {\r
+ /* Decrement the nesting count as we are leaving a critical section. */\r
+ ulCriticalNesting--;\r
+\r
+ /* If the nesting level has reached zero then interrupts should be\r
+ re-enabled. */\r
+ if( ulCriticalNesting == portNO_CRITICAL_NESTING )\r
+ {\r
+ __enable_interrupt();\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+ RSEG ICODE:CODE\r
+ CODE32\r
+\r
+ EXTERN vPortPreemptiveTick\r
+ EXTERN vTaskSwitchContext\r
+\r
+ PUBLIC vPortYieldProcessor\r
+ PUBLIC vPortStartFirstTask\r
+ PUBLIC vPortPreemptiveTickISR\r
+\r
+#include "ISR_Support.h"\r
+\r
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+; Starting the first task is just a matter of restoring the context that\r
+; was created by pxPortInitialiseStack().\r
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+vPortStartFirstTask:\r
+ portRESTORE_CONTEXT\r
+\r
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+; Manual context switch function. This is the SWI hander.\r
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+vPortYieldProcessor:\r
+ ADD LR, LR, #4 ; Add 4 to the LR to make the LR appear exactly\r
+ ; as if the context was saved during and IRQ\r
+ ; handler.\r
+ \r
+ portSAVE_CONTEXT ; Save the context of the current task...\r
+ LDR R0, =vTaskSwitchContext ; before selecting the next task to execute.\r
+ mov lr, pc\r
+ BX R0\r
+ portRESTORE_CONTEXT ; Restore the context of the selected task.\r
+\r
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+; Preemptive context switch function. This will only ever get used if\r
+; portUSE_PREEMPTION is set to 1 in portmacro.h.\r
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+vPortPreemptiveTickISR:\r
+ portSAVE_CONTEXT ; Save the context of the current task.\r
+\r
+ LDR R0, =vPortPreemptiveTick ; Increment the tick count - this may wake a task.\r
+ MOV lr, pc\r
+ BX R0\r
+\r
+ portRESTORE_CONTEXT ; Restore the context of the selected task.\r
+\r
+\r
+ END\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Port specific definitions.\r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the\r
+ * given hardware and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *-----------------------------------------------------------\r
+ */\r
+\r
+#include <intrinsic.h>\r
+\r
+/* Type definitions. */\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE double\r
+#define portLONG long\r
+#define portSHORT short\r
+#define portSTACK_TYPE unsigned portLONG\r
+#define portBASE_TYPE portLONG\r
+\r
+#if( configUSE_16_BIT_TICKS == 1 )\r
+ typedef unsigned portSHORT portTickType;\r
+ #define portMAX_DELAY ( portTickType ) 0xffff\r
+#else\r
+ typedef unsigned portLONG portTickType;\r
+ #define portMAX_DELAY ( portTickType ) 0xffffffff\r
+#endif\r
+/*-----------------------------------------------------------*/ \r
+\r
+/* Hardware specifics. */\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) \r
+#define portBYTE_ALIGNMENT 4\r
+#define portYIELD() asm ( "SWI 0" )\r
+#define portNOP() asm ( "NOP" )\r
+/*-----------------------------------------------------------*/ \r
+\r
+/* Critical section handling. */\r
+__arm __interwork void vPortDisableInterruptsFromThumb( void );\r
+__arm __interwork void vPortEnableInterruptsFromThumb( void );\r
+__arm __interwork void vPortEnterCritical( void );\r
+__arm __interwork void vPortExitCritical( void );\r
+\r
+#define portDISABLE_INTERRUPTS() __disable_interrupt()\r
+#define portENABLE_INTERRUPTS() __enable_interrupt()\r
+#define portENTER_CRITICAL() vPortEnterCritical()\r
+#define portEXIT_CRITICAL() vPortExitCritical()\r
+/*-----------------------------------------------------------*/ \r
+\r
+/* Task utilities. */\r
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \\r
+{ \\r
+extern void vTaskSwitchContext( void ); \\r
+ \\r
+ if( xSwitchRequired ) \\r
+ { \\r
+ vTaskSwitchContext(); \\r
+ } \\r
+}\r
+/*-----------------------------------------------------------*/ \r
+\r
+/* EIC utilities. */\r
+#define portEIC_CICR_ADDR *( ( unsigned portLONG * ) 0xFFFFF804 )\r
+#define portEIC_IPR_ADDR *( ( unsigned portLONG * ) 0xFFFFF840 )\r
+#define portCLEAR_EIC() portEIC_IPR_ADDR = 0x01 << portEIC_CICR_ADDR\r
+\r
+/*-----------------------------------------------------------*/ \r
+\r
+/* Compiler specifics */\r
+#define inline\r
+\r
+/* Task function macros as described on the FreeRTOS.org WEB site. */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )\r
+\r
+#endif /* PORTMACRO_H */\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ * Implementation of functions defined in portable.h for the ARM7 port\r
+ * using the Keil compiler.\r
+ *\r
+ * Components that can be compiled to either ARM or THUMB mode are\r
+ * contained in this file. The ISR routines, which can only be compiled\r
+ * to ARM mode are contained in portISR.c.\r
+ *----------------------------------------------------------*/\r
+\r
+/*\r
+ Changes from V3.2.2\r
+\r
+ + Bug fix - The prescale value for the timer setup is now written to T0PR \r
+ instead of T0PC. This bug would have had no effect unless a prescale \r
+ value was actually used.\r
+*/\r
+\r
+/* Standard includes. */\r
+#include <stdlib.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Constants required to setup the initial task context. */\r
+#define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */\r
+#define portTHUMB_MODE_BIT ( ( portSTACK_TYPE ) 0x20 )\r
+#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 )\r
+#define portNO_CRITICAL_SECTION_NESTING ( ( portSTACK_TYPE ) 0 )\r
+\r
+/* Constants required to setup the tick ISR. */\r
+#define portENABLE_TIMER ( ( unsigned portCHAR ) 0x01 )\r
+#define portPRESCALE_VALUE 0x00\r
+#define portINTERRUPT_ON_MATCH ( ( unsigned portLONG ) 0x01 )\r
+#define portRESET_COUNT_ON_MATCH ( ( unsigned portLONG ) 0x02 )\r
+\r
+/* Constants required to setup the VIC for the tick ISR. */\r
+#define portTIMER_VIC_CHANNEL ( ( unsigned portLONG ) 0x0004 )\r
+#define portTIMER_VIC_CHANNEL_BIT ( ( unsigned portLONG ) 0x0010 )\r
+#define portTIMER_VIC_ENABLE ( ( unsigned portLONG ) 0x0020 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Setup the timer to generate the tick interrupts. */\r
+static void prvSetupTimerInterrupt( void );\r
+\r
+/* \r
+ * The scheduler can only be started from ARM mode, so \r
+ * vPortISRStartFirstSTask() is defined in portISR.c. \r
+ */\r
+extern void vPortISRStartFirstTask( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* \r
+ * See header file for description. \r
+ */\r
+portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
+{\r
+portSTACK_TYPE *pxOriginalTOS;\r
+\r
+ /* Setup the initial stack of the task. The stack is set exactly as \r
+ expected by the portRESTORE_CONTEXT() macro.\r
+\r
+ Remember where the top of the (simulated) stack is before we place \r
+ anything on it. */\r
+ pxOriginalTOS = pxTopOfStack;\r
+\r
+ /* First on the stack is the return address - which in this case is the\r
+ start of the task. The offset is added to make the return address appear\r
+ as it would within an IRQ ISR. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; \r
+ pxTopOfStack--;\r
+\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */\r
+ pxTopOfStack--;\r
+\r
+ /* The last thing onto the stack is the status register, which is set for\r
+ system mode, with interrupts enabled. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR;\r
+\r
+ #ifdef KEIL_THUMB_INTERWORK\r
+ { \r
+ /* We want the task to start in thumb mode. */\r
+ *pxTopOfStack |= portTHUMB_MODE_BIT;\r
+ }\r
+ #endif\r
+\r
+ pxTopOfStack--;\r
+\r
+ /* The code generated by the Keil compiler does not maintain separate\r
+ stack and frame pointers. The portENTER_CRITICAL macro cannot therefore\r
+ use the stack as per other ports. Instead a variable is used to keep\r
+ track of the critical section nesting. This variable has to be stored\r
+ as part of the task context and is initially set to zero. */\r
+ *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;\r
+\r
+ return pxTopOfStack;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portBASE_TYPE xPortStartScheduler( void )\r
+{\r
+ /* Start the timer that generates the tick ISR. */\r
+ prvSetupTimerInterrupt();\r
+\r
+ /* Start the first task. This is done from portISR.c as ARM mode must be\r
+ used. */\r
+ vPortISRStartFirstTask();\r
+\r
+ /* Should not get here! */\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEndScheduler( void )\r
+{\r
+ /* It is unlikely that the ARM port will require this function as there\r
+ is nothing to return to. If this is required - stop the tick ISR then\r
+ return back to main. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupTimerInterrupt( void )\r
+{\r
+unsigned portLONG ulCompareMatch;\r
+\r
+ /* A 1ms tick does not require the use of the timer prescale. This is\r
+ defaulted to zero but can be used if necessary. */\r
+ T0PR = portPRESCALE_VALUE;\r
+\r
+ /* Calculate the match value required for our wanted tick rate. */\r
+ ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;\r
+\r
+ /* Protect against divide by zero. Using an if() statement still results\r
+ in a warning - hence the #if. */\r
+ #if portPRESCALE_VALUE != 0\r
+ {\r
+ ulCompareMatch /= ( portPRESCALE_VALUE + 1 );\r
+ }\r
+ #endif\r
+\r
+ T0MR0 = ulCompareMatch;\r
+\r
+ /* Generate tick with timer 0 compare match. */\r
+ T0MCR = portRESET_COUNT_ON_MATCH | portINTERRUPT_ON_MATCH;\r
+\r
+ /* Setup the VIC for the timer. */\r
+ VICIntSelect &= ~( portTIMER_VIC_CHANNEL_BIT );\r
+ VICIntEnable |= portTIMER_VIC_CHANNEL_BIT;\r
+ \r
+ /* The ISR installed depends on whether the preemptive or cooperative\r
+ scheduler is being used. */\r
+ #if configUSE_PREEMPTION == 1\r
+ { \r
+ #ifdef KEIL_THUMB_INTERWORK\r
+ extern void ( vPreemptiveTick )( void ) __arm __task;\r
+ #else\r
+ extern void ( vPreemptiveTick )( void ) __task;\r
+ #endif\r
+\r
+ VICVectAddr0 = ( unsigned portLONG ) vPreemptiveTick;\r
+ }\r
+ #else\r
+ {\r
+ extern void ( vNonPreemptiveTick )( void ) __irq;\r
+\r
+ VICVectAddr0 = ( portLONG ) vNonPreemptiveTick;\r
+ }\r
+ #endif\r
+\r
+ VICVectCntl0 = portTIMER_VIC_CHANNEL | portTIMER_VIC_ENABLE;\r
+\r
+ /* Start the timer - interrupts are disabled when this function is called\r
+ so it is okay to do this here. */\r
+ T0TCR = portENABLE_TIMER;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ * Components that can be compiled to either ARM or THUMB mode are\r
+ * contained in port.c The ISR routines, which can only be compiled\r
+ * to ARM mode, are contained in this file.\r
+ *----------------------------------------------------------*/\r
+\r
+/* This file must always be compiled to ARM mode as it contains ISR \r
+definitions. */\r
+#pragma ARM\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Constants required to handle interrupts. */\r
+#define portTIMER_MATCH_ISR_BIT ( ( unsigned portCHAR ) 0x01 )\r
+#define portCLEAR_VIC_INTERRUPT ( ( unsigned portLONG ) 0 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The code generated by the Keil compiler does not maintain separate\r
+stack and frame pointers. The portENTER_CRITICAL macro cannot therefore\r
+use the stack as per other ports. Instead a variable is used to keep\r
+track of the critical section nesting. This variable has to be stored\r
+as part of the task context and must be initialised to a non zero value. */\r
+\r
+#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 )\r
+volatile unsigned portLONG ulCriticalNesting = 9999UL;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* ISR to handle manual context switches (from a call to taskYIELD()). */\r
+void vPortYieldProcessor( void );\r
+\r
+/* \r
+ * The scheduler can only be started from ARM mode, hence the inclusion of this\r
+ * function here.\r
+ */\r
+void vPortISRStartFirstTask( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortISRStartFirstTask( void )\r
+{\r
+ /* Simply start the scheduler. This is included here as it can only be\r
+ called from ARM mode. */\r
+ portRESTORE_CONTEXT();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Interrupt service routine for the SWI interrupt. The vector table is\r
+ * configured within startup.s.\r
+ *\r
+ * vPortYieldProcessor() is used to manually force a context switch. The\r
+ * SWI interrupt is generated by a call to taskYIELD() or portYIELD().\r
+ */\r
+void vPortYieldProcessor( void ) __task\r
+{\r
+ /* Within an IRQ ISR the link register has an offset from the true return \r
+ address, but an SWI ISR does not. Add the offset manually so the same \r
+ ISR return code can be used in both cases. */\r
+ __asm{ ADD LR, LR, #4 };\r
+\r
+ /* Perform the context switch. */\r
+ portSAVE_CONTEXT();\r
+ vTaskSwitchContext();\r
+ portRESTORE_CONTEXT(); \r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* \r
+ * The ISR used for the scheduler tick depends on whether the cooperative or\r
+ * the preemptive scheduler is being used.\r
+ */\r
+\r
+#if configUSE_PREEMPTION == 0\r
+\r
+ /* \r
+ * The cooperative scheduler requires a normal IRQ service routine to \r
+ * simply increment the system tick. \r
+ */\r
+ void vNonPreemptiveTick( void );\r
+ void vNonPreemptiveTick( void ) __irq\r
+ {\r
+ /* Increment the tick count - this may make a delaying task ready\r
+ to run - but a context switch is not performed. */ \r
+ vTaskIncrementTick();\r
+\r
+ /* Ready for the next interrupt. */\r
+ T0IR = portTIMER_MATCH_ISR_BIT;\r
+ VICVectAddr = portCLEAR_VIC_INTERRUPT;\r
+ }\r
+\r
+#else\r
+\r
+ /* \r
+ * The preemptive scheduler ISR is defined as "naked" as the full context \r
+ * is saved on entry as part of the context switch. \r
+ */\r
+ void vPreemptiveTick( void );\r
+ void vPreemptiveTick( void ) __task\r
+ {\r
+ /* Save the context of the current task. */\r
+ portSAVE_CONTEXT(); \r
+\r
+ /* Increment the tick count - this may make a delayed task ready to \r
+ run. */\r
+ vTaskIncrementTick();\r
+\r
+ /* Find the highest priority task that is ready to run. */\r
+ vTaskSwitchContext();\r
+\r
+ /* Ready for the next interrupt. */\r
+ T0IR = portTIMER_MATCH_ISR_BIT;\r
+ VICVectAddr = portCLEAR_VIC_INTERRUPT;\r
+ \r
+ /* Restore the context of the highest priority task that is ready to \r
+ run. */\r
+ portRESTORE_CONTEXT();\r
+ }\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The interrupt management utilities can only be called from ARM mode. When\r
+ * KEIL_THUMB_INTERWORK is defined the utilities are defined as functions here \r
+ * to ensure a switch to ARM mode. When KEIL_THUMB_INTERWORK is not defined \r
+ * then the utilities are defined as macros in portmacro.h - as per other \r
+ * ports.\r
+ */\r
+#ifdef KEIL_THUMB_INTERWORK\r
+\r
+ void vPortDisableInterruptsFromThumb( void ) __task;\r
+ void vPortEnableInterruptsFromThumb( void ) __task;\r
+\r
+ void vPortDisableInterruptsFromThumb( void ) __task\r
+ {\r
+ __asm{ STMDB SP!, {R0} }; /* Push R0. */\r
+ __asm{ MRS R0, CPSR }; /* Get CPSR. */\r
+ __asm{ ORR R0, R0, #0xC0 }; /* Disable IRQ, FIQ. */\r
+ __asm{ MSR CPSR_CXSF, R0 }; /* Write back modified value. */\r
+ __asm{ LDMIA SP!, {R0} }; /* Pop R0. */\r
+ __asm{ BX R14 }; /* Return back to thumb. */\r
+ }\r
+ \r
+ void vPortEnableInterruptsFromThumb( void ) __task\r
+ {\r
+ __asm{ STMDB SP!, {R0} }; /* Push R0. */\r
+ __asm{ MRS R0, CPSR }; /* Get CPSR. */\r
+ __asm{ BIC R0, R0, #0xC0 }; /* Enable IRQ, FIQ. */\r
+ __asm{ MSR CPSR_CXSF, R0 }; /* Write back modified value. */\r
+ __asm{ LDMIA SP!, {R0} }; /* Pop R0. */\r
+ __asm{ BX R14 }; /* Return back to thumb. */\r
+ }\r
+\r
+#endif /* KEIL_THUMB_INTERWORK */\r
+\r
+\r
+\r
+/* The code generated by the Keil compiler does not maintain separate\r
+stack and frame pointers. The portENTER_CRITICAL macro cannot therefore\r
+use the stack as per other ports. Instead a variable is used to keep\r
+track of the critical section nesting. This necessitates the use of a \r
+function in place of the macro. */\r
+\r
+void vPortEnterCritical( void )\r
+{\r
+ /* Disable interrupts as per portDISABLE_INTERRUPTS(); */\r
+ __asm{ STMDB SP!, {R0} }; /* Push R0. */\r
+ __asm{ MRS R0, CPSR }; /* Get CPSR. */\r
+ __asm{ ORR R0, R0, #0xC0 }; /* Disable IRQ, FIQ. */\r
+ __asm{ MSR CPSR_CXSF, R0 }; /* Write back modified value. */\r
+ __asm{ LDMIA SP!, {R0} }; /* Pop R0. */\r
+\r
+ /* Now interrupts are disabled ulCriticalNesting can be accessed \r
+ directly. Increment ulCriticalNesting to keep a count of how many times\r
+ portENTER_CRITICAL() has been called. */\r
+ ulCriticalNesting++;\r
+}\r
+\r
+void vPortExitCritical( void )\r
+{\r
+ if( ulCriticalNesting > portNO_CRITICAL_NESTING )\r
+ {\r
+ /* Decrement the nesting count as we are leaving a critical section. */\r
+ ulCriticalNesting--;\r
+\r
+ /* If the nesting level has reached zero then interrupts should be\r
+ re-enabled. */\r
+ if( ulCriticalNesting == portNO_CRITICAL_NESTING )\r
+ {\r
+ /* Enable interrupts as per portEXIT_CRITICAL(). */\r
+ __asm{ STMDB SP!, {R0} }; /* Push R0. */\r
+ __asm{ MRS R0, CPSR }; /* Get CPSR. */\r
+ __asm{ BIC R0, R0, #0xC0 }; /* Enable IRQ, FIQ. */\r
+ __asm{ MSR CPSR_CXSF, R0 }; /* Write back modified value. */\r
+ __asm{ LDMIA SP!, {R0} }; /* Pop R0. */\r
+ }\r
+ }\r
+}\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Port specific definitions. \r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the\r
+ * given hardware and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *-----------------------------------------------------------\r
+ */\r
+\r
+/* Type definitions. */\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE double\r
+#define portLONG long\r
+#define portSHORT short\r
+#define portSTACK_TYPE unsigned portLONG\r
+#define portBASE_TYPE portLONG\r
+\r
+#if( configUSE_16_BIT_TICKS == 1 )\r
+ typedef unsigned portSHORT portTickType;\r
+ #define portMAX_DELAY ( portTickType ) 0xffff\r
+#else\r
+ typedef unsigned portLONG portTickType;\r
+ #define portMAX_DELAY ( portTickType ) 0xffffffff\r
+#endif\r
+/*-----------------------------------------------------------*/ \r
+\r
+/* Hardware specifics. */\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) \r
+#define portBYTE_ALIGNMENT 4\r
+/*-----------------------------------------------------------*/ \r
+\r
+/* Task utilities. */\r
+#define portRESTORE_CONTEXT() \\r
+{ \\r
+extern volatile unsigned portLONG ulCriticalNesting; \\r
+extern volatile void * volatile pxCurrentTCB; \\r
+ \\r
+ __asm{ LDR R1, =pxCurrentTCB };/* Set the LR to the task stack. The location was ... */ \\r
+ __asm{ LDR R0, [R1] }; /* ... stored in pxCurrentTCB. */ \\r
+ __asm{ LDR LR, [R0] }; \\r
+ \\r
+ __asm{ LDR R0, =ulCriticalNesting }; /* The critical nesting depth is the first item on ... */ \\r
+ __asm{ LDMFD LR!, {R1 } } /* ... the stack. Load it into the ulCriticalNesting var. */ \\r
+ __asm{ STR R1, [R0] } \\r
+ \\r
+ __asm{ LDMFD LR!, {R0} }; /* Get the SPSR from the stack. */ \\r
+ __asm{ MSR SPSR_CXSF, R0 }; \\r
+ \\r
+ __asm{ LDMFD LR, {R0-R14}^ }; /* Restore all system mode registers for the task. */ \\r
+ __asm{ NOP }; \\r
+ \\r
+ __asm{ LDR LR, [LR, #+60] }; /* Restore the return address. */ \\r
+ \\r
+ /* And return - correcting the offset in the LR to obtain ... */ \\r
+ __asm{ SUBS PC, LR, #4 }; /* ... the correct address. */ \\r
+}\r
+/*----------------------------------------------------------*/\r
+\r
+#define portSAVE_CONTEXT() \\r
+{ \\r
+extern volatile unsigned portLONG ulCriticalNesting; \\r
+extern volatile void * volatile pxCurrentTCB; \\r
+ \\r
+ __asm{ STMDB SP!, {R0} }; /* Store R0 first as we need to use it. */ \\r
+ \\r
+ __asm{ STMDB SP,{SP}^ }; /* Set R0 to point to the task stack pointer. */ \\r
+ __asm{ NOP }; \\r
+ __asm{ SUB SP, SP, #4 }; \\r
+ __asm{ LDMIA SP!,{R0} }; \\r
+ \ \r
+ __asm{ STMDB R0!, {LR} }; /* Push the return address onto the stack. */ \\r
+ __asm{ MOV LR, R0 }; /* Now we have saved LR we can use it instead of R0. */ \\r
+ __asm{ LDMIA SP!, {R0} }; /* Pop R0 so we can save it onto the system mode stack. */ \\r
+ \\r
+ __asm{ STMDB LR,{R0-LR}^ }; /* Push all the system mode registers onto the task stack. */ \\r
+ __asm{ NOP }; \\r
+ __asm{ SUB LR, LR, #60 }; \\r
+ \\r
+ __asm{ MRS R0, SPSR }; /* Push the SPSR onto the task stack. */ \\r
+ __asm{ STMDB LR!, {R0} }; \\r
+ \\r
+ __asm{ LDR R0, =ulCriticalNesting }; \\r
+ __asm{ LDR R0, [R0] }; \\r
+ __asm{ STMDB LR!, {R0} }; \\r
+ \\r
+ __asm{ LDR R0, =pxCurrentTCB };/* Store the new top of stack for the task. */ \\r
+ __asm{ LDR R1, [R0] }; \\r
+ __asm{ STR LR, [R1] }; \\r
+}\r
+\r
+/*-----------------------------------------------------------\r
+ * ISR entry and exit macros. These are only required if a task switch\r
+ * is required from an ISR.\r
+ *----------------------------------------------------------*/\r
+\r
+#define portENTER_SWITCHING_ISR() \\r
+ portSAVE_CONTEXT(); \\r
+ {\r
+\r
+#define portEXIT_SWITCHING_ISR( SwitchRequired ) \\r
+ /* If a switch is required then we just need to call */ \\r
+ /* vTaskSwitchContext() as the context has already been */ \\r
+ /* saved. */ \\r
+ if( SwitchRequired ) \\r
+ { \\r
+ vTaskSwitchContext(); \\r
+ } \\r
+ } \\r
+ /* Restore the context of which ever task is now the highest */ \\r
+ /* priority that is ready to run. */ \\r
+ portRESTORE_CONTEXT();\r
+\r
+\r
+/* Yield the processor - force a context switch. */\r
+#define portYIELD() __asm{ SWI 0 }; \r
+/*-----------------------------------------------------------*/ \r
+\r
+/* Critical section management. */\r
+\r
+/*-----------------------------------------------------------\r
+ * Interrupt control macros.\r
+ *\r
+ * The interrupt management utilities can only be called from ARM mode. When\r
+ * KEIL_THUMB_INTERWORK is defined the utilities are defined as functions in \r
+ * portISR.c to ensure a switch to ARM mode. When KEIL_THUMB_INTERWORK is not \r
+ * defined then the utilities are defined as macros here - as per other ports.\r
+ *----------------------------------------------------------*/\r
+\r
+#ifdef KEIL_THUMB_INTERWORK\r
+\r
+ extern void vPortDisableInterruptsFromThumb( void ) __task;\r
+ extern void vPortEnableInterruptsFromThumb( void ) __task;\r
+\r
+ #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb()\r
+ #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb()\r
+\r
+#else\r
+\r
+ /*-----------------------------------------------------------*/\r
+\r
+ #define portDISABLE_INTERRUPTS() \\r
+ __asm{ STMDB SP!, {R0} }; /* Push R0. */ \\r
+ __asm{ MRS R0, CPSR }; /* Get CPSR. */ \\r
+ __asm{ ORR R0, R0, #0xC0 }; /* Disable IRQ, FIQ. */ \\r
+ __asm{ MSR CPSR_CXSF, R0 }; /* Write back modified value. */ \\r
+ __asm{ LDMIA SP!, {R0} } /* Pop R0. */\r
+ \r
+ #define portENABLE_INTERRUPTS() \\r
+ __asm{ STMDB SP!, {R0} }; /* Push R0. */ \\r
+ __asm{ MRS R0, CPSR }; /* Get CPSR. */ \\r
+ __asm{ BIC R0, R0, #0xC0 }; /* Enable IRQ, FIQ. */ \\r
+ __asm{ MSR CPSR_CXSF, R0 }; /* Write back modified value. */ \\r
+ __asm{ LDMIA SP!, {R0} } /* Pop R0. */\r
+\r
+#endif /* KEIL_THUMB_INTERWORK */\r
+\r
+/*-----------------------------------------------------------\r
+ * Critical section control\r
+ *\r
+ * The code generated by the Keil compiler does not maintain separate\r
+ * stack and frame pointers. The portENTER_CRITICAL macro cannot therefore\r
+ * use the stack as per other ports. Instead a variable is used to keep\r
+ * track of the critical section nesting. This necessitates the use of a \r
+ * function in place of the macro.\r
+ *----------------------------------------------------------*/\r
+\r
+extern void vPortEnterCritical( void );\r
+extern void vPortExitCritical( void );\r
+\r
+#define portENTER_CRITICAL() vPortEnterCritical();\r
+#define portEXIT_CRITICAL() vPortExitCritical();\r
+/*-----------------------------------------------------------*/ \r
+\r
+/* Compiler specifics. */\r
+#define inline\r
+#define register\r
+#define portNOP() __asm{ NOP }\r
+/*-----------------------------------------------------------*/ \r
+\r
+/* Task function macros as described on the FreeRTOS.org WEB site. */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __task\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+\r
+#endif /* PORTMACRO_H */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* \r
+Changes between V1.2.4 and V1.2.5\r
+\r
+ + Introduced portGLOBAL_INTERRUPT_FLAG definition to test the global \r
+ interrupt flag setting. Using the two bits defined within\r
+ portINITAL_INTERRUPT_STATE was causing the w register to get clobbered\r
+ before the test was performed.\r
+\r
+Changes from V1.2.5\r
+\r
+ + Set the interrupt vector address to 0x08. Previously it was at the\r
+ incorrect address for compatibility mode of 0x18.\r
+\r
+Changes from V2.1.1\r
+\r
+ + PCLATU and PCLATH are now saved as part of the context. This allows\r
+ function pointers to be used within tasks. Thanks to Javier Espeche\r
+ for the enhancement. \r
+\r
+Changes from V2.3.1\r
+\r
+ + TABLAT is now saved as part of the task context.\r
+ \r
+Changes from V3.2.0\r
+\r
+ + TBLPTRU is now initialised to zero as the MPLAB compiler expects this\r
+ value and does not write to the register.\r
+*/\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* MPLAB library include file. */\r
+#include "timers.h"\r
+\r
+/*-----------------------------------------------------------\r
+ * Implementation of functions defined in portable.h for the PIC port.\r
+ *----------------------------------------------------------*/\r
+\r
+/* Hardware setup for tick. */\r
+#define portTIMER_FOSC_SCALE ( ( unsigned portLONG ) 4 )\r
+\r
+/* Initial interrupt enable state for newly created tasks. This value is\r
+copied into INTCON when a task switches in for the first time. */\r
+#define portINITAL_INTERRUPT_STATE 0xc0\r
+\r
+/* Just the bit within INTCON for the global interrupt flag. */\r
+#define portGLOBAL_INTERRUPT_FLAG 0x80\r
+\r
+/* Constant used for context switch macro when we require the interrupt \r
+enable state to be unchanged when the interrupted task is switched back in. */\r
+#define portINTERRUPTS_UNCHANGED 0x00\r
+\r
+/* Some memory areas get saved as part of the task context. These memory\r
+area's get used by the compiler for temporary storage, especially when \r
+performing mathematical operations, or when using 32bit data types. This\r
+constant defines the size of memory area which must be saved. */\r
+#define portCOMPILER_MANAGED_MEMORY_SIZE ( ( unsigned portCHAR ) 0x13 )\r
+\r
+/* We require the address of the pxCurrentTCB variable, but don't want to know\r
+any details of its type. */\r
+typedef void tskTCB;\r
+extern volatile tskTCB * volatile pxCurrentTCB;\r
+\r
+/* IO port constants. */\r
+#define portBIT_SET ( ( unsigned portCHAR ) 1 )\r
+#define portBIT_CLEAR ( ( unsigned portCHAR ) 0 )\r
+\r
+/*\r
+ * The serial port ISR's are defined in serial.c, but are called from portable\r
+ * as they use the same vector as the tick ISR.\r
+ */\r
+void vSerialTxISR( void );\r
+void vSerialRxISR( void );\r
+\r
+/*\r
+ * Perform hardware setup to enable ticks.\r
+ */\r
+static void prvSetupTimerInterrupt( void );\r
+\r
+/* \r
+ * ISR to maintain the tick, and perform tick context switches if the\r
+ * preemptive scheduler is being used.\r
+ */\r
+static void prvTickISR( void );\r
+\r
+/*\r
+ * ISR placed on the low priority vector. This calls the appropriate ISR for\r
+ * the actual interrupt.\r
+ */\r
+static void prvLowInterrupt( void );\r
+\r
+/* \r
+ * Macro that pushes all the registers that make up the context of a task onto\r
+ * the stack, then saves the new top of stack into the TCB.\r
+ * \r
+ * If this is called from an ISR then the interrupt enable bits must have been \r
+ * set for the ISR to ever get called. Therefore we want to save the INTCON\r
+ * register with the enable bits forced to be set - and ucForcedInterruptFlags \r
+ * must contain these bit settings. This means the interrupts will again be\r
+ * enabled when the interrupted task is switched back in.\r
+ *\r
+ * If this is called from a manual context switch (i.e. from a call to yield),\r
+ * then we want to save the INTCON so it is restored with its current state,\r
+ * and ucForcedInterruptFlags must be 0. This allows a yield from within\r
+ * a critical section.\r
+ *\r
+ * The compiler uses some locations at the bottom of the memory for temporary\r
+ * storage during math and other computations. This is especially true if\r
+ * 32bit data types are utilised (as they are by the scheduler). The .tmpdata\r
+ * and MATH_DATA sections have to be stored in there entirety as part of a task\r
+ * context. This macro stores from data address 0x00 to \r
+ * portCOMPILER_MANAGED_MEMORY_SIZE. This is sufficient for the demo \r
+ * applications but you should check the map file for your project to ensure \r
+ * this is sufficient for your needs. It is not clear whether this size is \r
+ * fixed for all compilations or has the potential to be program specific.\r
+ */\r
+#define portSAVE_CONTEXT( ucForcedInterruptFlags ) \\r
+{ \\r
+ _asm \\r
+ /* Save the status and WREG registers first, as these will get modified \\r
+ by the operations below. */ \\r
+ MOVFF WREG, PREINC1 \\r
+ MOVFF STATUS, PREINC1 \\r
+ /* Save the INTCON register with the appropriate bits forced if \\r
+ necessary - as described above. */ \\r
+ MOVFF INTCON, WREG \\r
+ IORLW ucForcedInterruptFlags \\r
+ MOVFF WREG, PREINC1 \\r
+ _endasm \\r
+ \\r
+ portDISABLE_INTERRUPTS(); \\r
+ \\r
+ _asm \\r
+ /* Store the necessary registers to the stack. */ \\r
+ MOVFF BSR, PREINC1 \\r
+ MOVFF FSR2L, PREINC1 \\r
+ MOVFF FSR2H, PREINC1 \\r
+ MOVFF FSR0L, PREINC1 \\r
+ MOVFF FSR0H, PREINC1 \\r
+ MOVFF TABLAT, PREINC1 \\r
+ MOVFF TBLPTRU, PREINC1 \\r
+ MOVFF TBLPTRH, PREINC1 \\r
+ MOVFF TBLPTRL, PREINC1 \\r
+ MOVFF PRODH, PREINC1 \\r
+ MOVFF PRODL, PREINC1 \\r
+ MOVFF PCLATU, PREINC1 \\r
+ MOVFF PCLATH, PREINC1 \\r
+ /* Store the .tempdata and MATH_DATA areas as described above. */ \\r
+ CLRF FSR0L, 0 \\r
+ CLRF FSR0H, 0 \\r
+ MOVFF POSTINC0, PREINC1 \\r
+ MOVFF POSTINC0, PREINC1 \\r
+ MOVFF POSTINC0, PREINC1 \\r
+ MOVFF POSTINC0, PREINC1 \\r
+ MOVFF POSTINC0, PREINC1 \\r
+ MOVFF POSTINC0, PREINC1 \\r
+ MOVFF POSTINC0, PREINC1 \\r
+ MOVFF POSTINC0, PREINC1 \\r
+ MOVFF POSTINC0, PREINC1 \\r
+ MOVFF POSTINC0, PREINC1 \\r
+ MOVFF POSTINC0, PREINC1 \\r
+ MOVFF POSTINC0, PREINC1 \\r
+ MOVFF POSTINC0, PREINC1 \\r
+ MOVFF POSTINC0, PREINC1 \\r
+ MOVFF POSTINC0, PREINC1 \\r
+ MOVFF POSTINC0, PREINC1 \\r
+ MOVFF POSTINC0, PREINC1 \\r
+ MOVFF POSTINC0, PREINC1 \\r
+ MOVFF POSTINC0, PREINC1 \\r
+ MOVFF INDF0, PREINC1 \\r
+ MOVFF FSR0L, PREINC1 \\r
+ MOVFF FSR0H, PREINC1 \\r
+ /* Store the hardware stack pointer in a temp register before we \\r
+ modify it. */ \\r
+ MOVFF STKPTR, FSR0L \\r
+ _endasm \\r
+ \\r
+ /* Store each address from the hardware stack. */ \\r
+ while( STKPTR > ( unsigned portCHAR ) 0 ) \\r
+ { \\r
+ _asm \\r
+ MOVFF TOSL, PREINC1 \\r
+ MOVFF TOSH, PREINC1 \\r
+ MOVFF TOSU, PREINC1 \\r
+ POP \\r
+ _endasm \\r
+ } \\r
+ \\r
+ _asm \\r
+ /* Store the number of addresses on the hardware stack (from the \\r
+ temporary register). */ \\r
+ MOVFF FSR0L, PREINC1 \\r
+ MOVF PREINC1, 1, 0 \\r
+ _endasm \\r
+ \\r
+ /* Save the new top of the software stack in the TCB. */ \\r
+ _asm \\r
+ MOVFF pxCurrentTCB, FSR0L \\r
+ MOVFF pxCurrentTCB + 1, FSR0H \\r
+ MOVFF FSR1L, POSTINC0 \\r
+ MOVFF FSR1H, POSTINC0 \\r
+ _endasm \\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * This is the reverse of portSAVE_CONTEXT. See portSAVE_CONTEXT for more\r
+ * details.\r
+ */\r
+#define portRESTORE_CONTEXT() \\r
+{ \\r
+ _asm \\r
+ /* Set FSR0 to point to pxCurrentTCB->pxTopOfStack. */ \\r
+ MOVFF pxCurrentTCB, FSR0L \\r
+ MOVFF pxCurrentTCB + 1, FSR0H \\r
+ \\r
+ /* De-reference FSR0 to set the address it holds into FSR1. \\r
+ (i.e. *( pxCurrentTCB->pxTopOfStack ) ). */ \\r
+ MOVFF POSTINC0, FSR1L \\r
+ MOVFF POSTINC0, FSR1H \\r
+ \\r
+ /* How many return addresses are there on the hardware stack? Discard \\r
+ the first byte as we are pointing to the next free space. */ \\r
+ MOVFF POSTDEC1, FSR0L \\r
+ MOVFF POSTDEC1, FSR0L \\r
+ _endasm \\r
+ \\r
+ /* Fill the hardware stack from our software stack. */ \\r
+ STKPTR = 0; \\r
+ \\r
+ while( STKPTR < FSR0L ) \\r
+ { \\r
+ _asm \\r
+ PUSH \\r
+ MOVF POSTDEC1, 0, 0 \\r
+ MOVWF TOSU, 0 \\r
+ MOVF POSTDEC1, 0, 0 \\r
+ MOVWF TOSH, 0 \\r
+ MOVF POSTDEC1, 0, 0 \\r
+ MOVWF TOSL, 0 \\r
+ _endasm \\r
+ } \\r
+ \\r
+ _asm \\r
+ /* Restore the .tmpdata and MATH_DATA memory. */ \\r
+ MOVFF POSTDEC1, FSR0H \\r
+ MOVFF POSTDEC1, FSR0L \\r
+ MOVFF POSTDEC1, POSTDEC0 \\r
+ MOVFF POSTDEC1, POSTDEC0 \\r
+ MOVFF POSTDEC1, POSTDEC0 \\r
+ MOVFF POSTDEC1, POSTDEC0 \\r
+ MOVFF POSTDEC1, POSTDEC0 \\r
+ MOVFF POSTDEC1, POSTDEC0 \\r
+ MOVFF POSTDEC1, POSTDEC0 \\r
+ MOVFF POSTDEC1, POSTDEC0 \\r
+ MOVFF POSTDEC1, POSTDEC0 \\r
+ MOVFF POSTDEC1, POSTDEC0 \\r
+ MOVFF POSTDEC1, POSTDEC0 \\r
+ MOVFF POSTDEC1, POSTDEC0 \\r
+ MOVFF POSTDEC1, POSTDEC0 \\r
+ MOVFF POSTDEC1, POSTDEC0 \\r
+ MOVFF POSTDEC1, POSTDEC0 \\r
+ MOVFF POSTDEC1, POSTDEC0 \\r
+ MOVFF POSTDEC1, POSTDEC0 \\r
+ MOVFF POSTDEC1, POSTDEC0 \\r
+ MOVFF POSTDEC1, POSTDEC0 \\r
+ MOVFF POSTDEC1, INDF0 \\r
+ /* Restore the other registers forming the tasks context. */ \\r
+ MOVFF POSTDEC1, PCLATH \\r
+ MOVFF POSTDEC1, PCLATU \\r
+ MOVFF POSTDEC1, PRODL \\r
+ MOVFF POSTDEC1, PRODH \\r
+ MOVFF POSTDEC1, TBLPTRL \\r
+ MOVFF POSTDEC1, TBLPTRH \\r
+ MOVFF POSTDEC1, TBLPTRU \\r
+ MOVFF POSTDEC1, TABLAT \\r
+ MOVFF POSTDEC1, FSR0H \\r
+ MOVFF POSTDEC1, FSR0L \\r
+ MOVFF POSTDEC1, FSR2H \\r
+ MOVFF POSTDEC1, FSR2L \\r
+ MOVFF POSTDEC1, BSR \\r
+ /* The next byte is the INTCON register. Read this into WREG as some \\r
+ manipulation is required. */ \\r
+ MOVFF POSTDEC1, WREG \\r
+ _endasm \\r
+ \\r
+ /* From the INTCON register, only the interrupt enable bits form part \\r
+ of the tasks context. It is perfectly legitimate for another task to \\r
+ have modified any other bits. We therefore only restore the top two bits. \\r
+ */ \\r
+ if( WREG & portGLOBAL_INTERRUPT_FLAG ) \\r
+ { \\r
+ _asm \\r
+ MOVFF POSTDEC1, STATUS \\r
+ MOVFF POSTDEC1, WREG \\r
+ /* Return enabling interrupts. */ \\r
+ RETFIE 0 \\r
+ _endasm \\r
+ } \\r
+ else \\r
+ { \\r
+ _asm \\r
+ MOVFF POSTDEC1, STATUS \\r
+ MOVFF POSTDEC1, WREG \\r
+ /* Return without effecting interrupts. The context may have \\r
+ been saved from a critical region. */ \\r
+ RETURN 0 \\r
+ _endasm \\r
+ } \\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* \r
+ * See header file for description. \r
+ */\r
+portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
+{\r
+unsigned portLONG ulAddress;\r
+unsigned portCHAR ucBlock;\r
+\r
+ /* Place a few bytes of known values on the bottom of the stack. \r
+ This is just useful for debugging. */\r
+\r
+ *pxTopOfStack = 0x11;\r
+ pxTopOfStack++;\r
+ *pxTopOfStack = 0x22;\r
+ pxTopOfStack++;\r
+ *pxTopOfStack = 0x33;\r
+ pxTopOfStack++;\r
+\r
+\r
+ /* Simulate how the stack would look after a call to vPortYield() generated\r
+ by the compiler. \r
+\r
+ First store the function parameters. This is where the task will expect to\r
+ find them when it starts running. */\r
+ ulAddress = ( unsigned portLONG ) pvParameters;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) ( ulAddress & ( unsigned portLONG ) 0x00ff );\r
+ pxTopOfStack++;\r
+\r
+ ulAddress >>= 8;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) ( ulAddress & ( unsigned portLONG ) 0x00ff );\r
+ pxTopOfStack++;\r
+\r
+ /* Next we just leave a space. When a context is saved the stack pointer\r
+ is incremented before it is used so as not to corrupt whatever the stack\r
+ pointer is actually pointing to. This is especially necessary during \r
+ function epilogue code generated by the compiler. */\r
+ *pxTopOfStack = 0x44;\r
+ pxTopOfStack++;\r
+\r
+ /* Next are all the registers that form part of the task context. */\r
+ \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x66; /* WREG. */\r
+ pxTopOfStack++;\r
+\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0xcc; /* Status. */\r
+ pxTopOfStack++;\r
+\r
+ /* INTCON is saved with interrupts enabled. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) portINITAL_INTERRUPT_STATE; /* INTCON */\r
+ pxTopOfStack++;\r
+\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x11; /* BSR. */\r
+ pxTopOfStack++;\r
+\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x22; /* FSR2L. */\r
+ pxTopOfStack++;\r
+\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x33; /* FSR2H. */\r
+ pxTopOfStack++;\r
+\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x44; /* FSR0L. */\r
+ pxTopOfStack++;\r
+\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x55; /* FSR0H. */\r
+ pxTopOfStack++;\r
+\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x66; /* TABLAT. */\r
+ pxTopOfStack++;\r
+\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* TBLPTRU. */\r
+ pxTopOfStack++;\r
+\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x88; /* TBLPTRUH. */\r
+ pxTopOfStack++;\r
+\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x99; /* TBLPTRUL. */\r
+ pxTopOfStack++;\r
+\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0xaa; /* PRODH. */\r
+ pxTopOfStack++;\r
+\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0xbb; /* PRODL. */\r
+ pxTopOfStack++;\r
+\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* PCLATU. */\r
+ pxTopOfStack++;\r
+\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* PCLATH. */\r
+ pxTopOfStack++;\r
+\r
+ /* Next the .tmpdata and MATH_DATA sections. */\r
+ for( ucBlock = 0; ucBlock <= portCOMPILER_MANAGED_MEMORY_SIZE; ucBlock++ )\r
+ {\r
+ *pxTopOfStack = ( portSTACK_TYPE ) ucBlock;\r
+ *pxTopOfStack++;\r
+ }\r
+\r
+ /* Store the top of the global data section. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) portCOMPILER_MANAGED_MEMORY_SIZE; /* Low. */\r
+ pxTopOfStack++;\r
+\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* High. */\r
+ pxTopOfStack++;\r
+\r
+ /* The only function return address so far is the address of the \r
+ task. */\r
+ ulAddress = ( unsigned portLONG ) pxCode;\r
+\r
+ /* TOS low. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) ( ulAddress & ( unsigned portLONG ) 0x00ff );\r
+ pxTopOfStack++;\r
+ ulAddress >>= 8;\r
+\r
+ /* TOS high. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) ( ulAddress & ( unsigned portLONG ) 0x00ff );\r
+ pxTopOfStack++;\r
+ ulAddress >>= 8;\r
+\r
+ /* TOS even higher. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) ( ulAddress & ( unsigned portLONG ) 0x00ff );\r
+ pxTopOfStack++;\r
+\r
+ /* Store the number of return addresses on the hardware stack - so far only\r
+ the address of the task entry point. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 1;\r
+ pxTopOfStack++;\r
+\r
+ return pxTopOfStack;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portBASE_TYPE xPortStartScheduler( void )\r
+{\r
+ /* In this port we ignore the parameter and use the configUSE_PREEMPTION\r
+ definition instead. */\r
+\r
+ /* Setup a timer for the tick ISR is using the preemptive scheduler. */\r
+ prvSetupTimerInterrupt(); \r
+\r
+ /* Restore the context of the first task to run. */\r
+ portRESTORE_CONTEXT();\r
+\r
+ /* Should not get here. Use the function name to stop compiler warnings. */\r
+ ( void ) prvLowInterrupt;\r
+ ( void ) prvTickISR;\r
+\r
+ return pdTRUE;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEndScheduler( void )\r
+{\r
+ /* It is unlikely that the scheduler for the PIC port will get stopped\r
+ once running. If required disable the tick interrupt here, then return \r
+ to xPortStartScheduler(). */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Manual context switch. This is similar to the tick context switch,\r
+ * but does not increment the tick count. It must be identical to the\r
+ * tick context switch in how it stores the stack of a task.\r
+ */\r
+void vPortYield( void )\r
+{\r
+ /* This can get called with interrupts either enabled or disabled. We\r
+ will save the INTCON register with the interrupt enable bits unmodified. */\r
+ portSAVE_CONTEXT( portINTERRUPTS_UNCHANGED );\r
+\r
+ /* Switch to the highest priority task that is ready to run. */\r
+ vTaskSwitchContext();\r
+\r
+ /* Start executing the task we have just switched to. */\r
+ portRESTORE_CONTEXT();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Vector for ISR. Nothing here must alter any registers!\r
+ */\r
+#pragma code high_vector=0x08\r
+static void prvLowInterrupt( void )\r
+{\r
+ /* Was the interrupt the tick? */\r
+ if( PIR1bits.CCP1IF )\r
+ { \r
+ _asm\r
+ goto prvTickISR\r
+ _endasm\r
+ }\r
+\r
+ /* Was the interrupt a byte being received? */\r
+ if( PIR1bits.RCIF )\r
+ {\r
+ _asm\r
+ goto vSerialRxISR\r
+ _endasm\r
+ }\r
+\r
+ /* Was the interrupt the Tx register becoming empty? */\r
+ if( PIR1bits.TXIF )\r
+ {\r
+ if( PIE1bits.TXIE )\r
+ {\r
+ _asm\r
+ goto vSerialTxISR\r
+ _endasm\r
+ }\r
+ }\r
+}\r
+#pragma code\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * ISR for the tick.\r
+ * This increments the tick count and, if using the preemptive scheduler, \r
+ * performs a context switch. This must be identical to the manual \r
+ * context switch in how it stores the context of a task. \r
+ */\r
+static void prvTickISR( void )\r
+{\r
+ /* Interrupts must have been enabled for the ISR to fire, so we have to \r
+ save the context with interrupts enabled. */\r
+ portSAVE_CONTEXT( portGLOBAL_INTERRUPT_FLAG );\r
+ PIR1bits.CCP1IF = 0;\r
+
+ /* Maintain the tick count. */\r
+ vTaskIncrementTick();\r
+\r
+ #if configUSE_PREEMPTION == 1\r
+ {\r
+ /* Switch to the highest priority task that is ready to run. */\r
+ vTaskSwitchContext();\r
+ }\r
+ #endif\r
+\r
+ portRESTORE_CONTEXT();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Setup a timer for a regular tick.\r
+ */\r
+static void prvSetupTimerInterrupt( void )\r
+{\r
+const unsigned portLONG ulConstCompareValue = ( ( configCPU_CLOCK_HZ / portTIMER_FOSC_SCALE ) / configTICK_RATE_HZ );\r
+unsigned portLONG ulCompareValue;\r
+unsigned portCHAR ucByte;\r
+\r
+ /* Interrupts are disabled when this function is called.\r
+\r
+ Setup CCP1 to provide the tick interrupt using a compare match on timer\r
+ 1.\r
+\r
+ Clear the time count then setup timer. */\r
+ TMR1H = ( unsigned portCHAR ) 0x00;\r
+ TMR1L = ( unsigned portCHAR ) 0x00;\r
+\r
+ /* Set the compare match value. */\r
+ ulCompareValue = ulConstCompareValue;\r
+ CCPR1L = ( unsigned portCHAR ) ( ulCompareValue & ( unsigned portLONG ) 0xff );\r
+ ulCompareValue >>= ( unsigned portLONG ) 8;\r
+ CCPR1H = ( unsigned portCHAR ) ( ulCompareValue & ( unsigned portLONG ) 0xff ); \r
+\r
+ CCP1CONbits.CCP1M0 = portBIT_SET; /*< Compare match mode. */\r
+ CCP1CONbits.CCP1M1 = portBIT_SET; /*< Compare match mode. */\r
+ CCP1CONbits.CCP1M2 = portBIT_CLEAR; /*< Compare match mode. */\r
+ CCP1CONbits.CCP1M3 = portBIT_SET; /*< Compare match mode. */\r
+ PIE1bits.CCP1IE = portBIT_SET; /*< Interrupt enable. */\r
+\r
+ /* We are only going to use the global interrupt bit, so set the peripheral\r
+ bit to true. */\r
+ INTCONbits.GIEL = portBIT_SET;\r
+\r
+ /* Provided library function for setting up the timer that will produce the\r
+ tick. */\r
+ OpenTimer1( T1_16BIT_RW & T1_SOURCE_INT & T1_PS_1_1 & T1_CCP1_T3_CCP2 );\r
+}\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Port specific definitions. \r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the\r
+ * given hardware and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *-----------------------------------------------------------\r
+ */\r
+\r
+/* Type definitions. */\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE double\r
+#define portLONG long\r
+#define portSHORT int\r
+#define portSTACK_TYPE unsigned char\r
+#define portBASE_TYPE char\r
+\r
+#if( configUSE_16_BIT_TICKS == 1 )\r
+ typedef unsigned portSHORT portTickType;\r
+ #define portMAX_DELAY ( portTickType ) 0xffff\r
+#else\r
+ typedef unsigned portLONG portTickType;\r
+ #define portMAX_DELAY ( portTickType ) 0xffffffff\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Hardware specifics. */\r
+#define portBYTE_ALIGNMENT 1\r
+#define portGLOBAL_INT_ENABLE_BIT 0x80\r
+#define portSTACK_GROWTH 1\r
+#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) \r
+/*-----------------------------------------------------------*/\r
+\r
+/* Critical section management. */\r
+#define portDISABLE_INTERRUPTS() INTCONbits.GIEH = 0;\r
+#define portENABLE_INTERRUPTS() INTCONbits.GIEH = 1;\r
+\r
+/* Push the INTCON register onto the stack, then disable interrupts. */\r
+#define portENTER_CRITICAL() POSTINC1 = INTCON; \\r
+ INTCONbits.GIEH = 0;\r
+\r
+/* Retrieve the INTCON register from the stack, and enable interrupts\r
+if they were saved as being enabled. Don't modify any other bits\r
+within the INTCON register as these may have lagitimately have been\r
+modified within the critical region. */\r
+#define portEXIT_CRITICAL() _asm \\r
+ MOVF POSTDEC1, 1, 0 \\r
+ _endasm \\r
+ if( INDF1 & portGLOBAL_INT_ENABLE_BIT ) \\r
+ { \\r
+ portENABLE_INTERRUPTS(); \\r
+ }\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Task utilities. */\r
+extern void vPortYield( void );\r
+#define portYIELD() vPortYield()\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Task function macros as described on the FreeRTOS.org WEB site. */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Compiler specifics. */\r
+#define inline\r
+\r
+#define portNOP() _asm \\r
+ NOP \\r
+ _endasm\r
+\r
+#endif /* PORTMACRO_H */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* \r
+\r
+Changes between V2.5.1 and V2.5.1\r
+\r
+ + The memory pool has been defined within a struct to ensure correct memory\r
+ alignment on 32bit systems.\r
+\r
+Changes between V2.6.1 and V3.0.0\r
+\r
+ + An overflow check has been added to ensure the next free byte variable \r
+ does not wrap around.\r
+*/\r
+\r
+\r
+/*\r
+ * The simplest possible implementation of pvPortMalloc(). Note that this\r
+ * implementation does NOT allow allocated memory to be freed again.\r
+ *\r
+ * See heap_2.c and heap_3.c for alternative implementations, and the memory\r
+ * management pages of http://www.FreeRTOS.org for more information.\r
+ */\r
+#include <stdlib.h>\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Setup the correct byte alignment mask for the defined byte alignment. */\r
+#if portBYTE_ALIGNMENT == 4\r
+ #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0003 )\r
+#endif\r
+\r
+#if portBYTE_ALIGNMENT == 2\r
+ #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0001 )\r
+#endif\r
+\r
+#if portBYTE_ALIGNMENT == 1 \r
+ #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0000 )\r
+#endif\r
+\r
+#ifndef heapBYTE_ALIGNMENT_MASK\r
+ #error "Invalid portBYTE_ALIGNMENT definition"\r
+#endif\r
+\r
+/* Allocate the memory for the heap. The struct is used to force byte\r
+alignment without using any non-portable code. */\r
+static struct xRTOS_HEAP\r
+{\r
+ unsigned portLONG ulDummy;\r
+ unsigned portCHAR ucHeap[ configTOTAL_HEAP_SIZE ];\r
+} xHeap;\r
+\r
+static size_t xNextFreeByte = ( size_t ) 0;\r
+/*-----------------------------------------------------------*/\r
+\r
+void *pvPortMalloc( size_t xWantedSize )\r
+{\r
+void *pvReturn = NULL; \r
+\r
+ /* Ensure that blocks are always aligned to the required number of bytes. */\r
+ #if portBYTE_ALIGNMENT != 1\r
+ if( xWantedSize & heapBYTE_ALIGNMENT_MASK )\r
+ {\r
+ /* Byte alignment required. */\r
+ xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & heapBYTE_ALIGNMENT_MASK ) );\r
+ }\r
+ #endif\r
+\r
+ vTaskSuspendAll();\r
+ {\r
+ /* Check there is enough room left for the allocation. */\r
+ if( ( ( xNextFreeByte + xWantedSize ) < configTOTAL_HEAP_SIZE ) &&\r
+ ( ( xNextFreeByte + xWantedSize ) > xNextFreeByte ) )/* Check for overflow. */\r
+ {\r
+ /* Return the next free byte then increment the index past this\r
+ block. */\r
+ pvReturn = &( xHeap.ucHeap[ xNextFreeByte ] );\r
+ xNextFreeByte += xWantedSize; \r
+ } \r
+ }\r
+ xTaskResumeAll();\r
+\r
+ return pvReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortFree( void *pv )\r
+{\r
+ /* Memory cannot be freed using this scheme. See heap_2.c and heap_3.c \r
+ for alternative implementations, and the memory management pages of \r
+ http://www.FreeRTOS.org for more information. */\r
+ ( void ) pv;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortInitialiseBlocks( void )\r
+{\r
+ /* Only required when static memory is not cleared. */\r
+ xNextFreeByte = ( size_t ) 0;\r
+}\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+ * A sample implementation of pvPortMalloc() and vPortFree() that permits\r
+ * allocated blocks to be freed, but does not combine adjacent free blocks\r
+ * into a single larger block.\r
+ *\r
+ * See heap_1.c and heap_3.c for alternative implementations, and the memory\r
+ * management pages of http://www.FreeRTOS.org for more information.\r
+ */\r
+#include <stdlib.h>\r
+\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Setup the correct byte alignment mask for the defined byte alignment. */\r
+#if portBYTE_ALIGNMENT == 4\r
+ #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0003 )\r
+#endif\r
+\r
+#if portBYTE_ALIGNMENT == 2\r
+ #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0001 )\r
+#endif\r
+\r
+#if portBYTE_ALIGNMENT == 1\r
+ #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0000 )\r
+#endif\r
+\r
+#ifndef heapBYTE_ALIGNMENT_MASK\r
+ #error "Invalid portBYTE_ALIGNMENT definition"\r
+#endif\r
+\r
+/* Allocate the memory for the heap. The struct is used to force byte\r
+alignment without using any non-portable code. */\r
+static struct xRTOS_HEAP\r
+{\r
+ unsigned portLONG ulDummy;\r
+ unsigned portCHAR ucHeap[ configTOTAL_HEAP_SIZE ];\r
+} xHeap;\r
+\r
+/* Define the linked list structure. This is used to link free blocks in order\r
+of their size. */\r
+typedef struct A_BLOCK_LINK\r
+{\r
+ struct A_BLOCK_LINK *pxNextFreeBlock; /*<< The next free block in the list. */\r
+ size_t xBlockSize; /*<< The size of the free block. */\r
+} xBlockLink;\r
+\r
+\r
+static const unsigned portSHORT heapSTRUCT_SIZE = ( sizeof( xBlockLink ) + ( sizeof( xBlockLink ) % portBYTE_ALIGNMENT ) );\r
+#define heapMINIMUM_BLOCK_SIZE ( ( size_t ) ( heapSTRUCT_SIZE * 2 ) )\r
+\r
+/* Create a couple of list links to mark the start and end of the list. */\r
+static xBlockLink xStart, xEnd;\r
+\r
+/* STATIC FUNCTIONS ARE DEFINED AS MACROS TO MINIMIZE THE FUNCTION CALL DEPTH. */\r
+\r
+/*\r
+ * Insert a block into the list of free blocks - which is ordered by size of\r
+ * the block. Small blocks at the start of the list and large blocks at the end\r
+ * of the list.\r
+ */\r
+#define prvInsertBlockIntoFreeList( pxBlockToInsert ) \\r
+{ \\r
+xBlockLink *pxIterator; \\r
+size_t xBlockSize; \\r
+ \\r
+ xBlockSize = pxBlockToInsert->xBlockSize; \\r
+ \\r
+ /* Iterate through the list until a block is found that has a larger size */ \\r
+ /* than the block we are inserting. */ \\r
+ for( pxIterator = &xStart; pxIterator->pxNextFreeBlock->xBlockSize < xBlockSize; pxIterator = pxIterator->pxNextFreeBlock ) \\r
+ { \\r
+ /* There is nothing to do here - just iterate to the correct position. */ \\r
+ } \\r
+ \\r
+ /* Update the list to include the block being inserted in the correct */ \\r
+ /* position. */ \\r
+ pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; \\r
+ pxIterator->pxNextFreeBlock = pxBlockToInsert; \\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#define prvHeapInit() \\r
+{ \\r
+xBlockLink *pxFirstFreeBlock; \\r
+ \\r
+ /* xStart is used to hold a pointer to the first item in the list of free */ \\r
+ /* blocks. The void cast is used to prevent compiler warnings. */ \\r
+ xStart.pxNextFreeBlock = ( void * ) xHeap.ucHeap; \\r
+ xStart.xBlockSize = ( size_t ) 0; \\r
+ \\r
+ /* xEnd is used to mark the end of the list of free blocks. */ \\r
+ xEnd.xBlockSize = configTOTAL_HEAP_SIZE; \\r
+ xEnd.pxNextFreeBlock = NULL; \\r
+ \\r
+ /* To start with there is a single free block that is sized to take up the \\r
+ entire heap space. */ \\r
+ pxFirstFreeBlock = ( void * ) xHeap.ucHeap; \\r
+ pxFirstFreeBlock->xBlockSize = configTOTAL_HEAP_SIZE; \\r
+ pxFirstFreeBlock->pxNextFreeBlock = &xEnd; \\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void *pvPortMalloc( size_t xWantedSize )\r
+{\r
+xBlockLink *pxBlock, *pxPreviousBlock, *pxNewBlockLink;\r
+static portBASE_TYPE xHeapHasBeenInitialised = pdFALSE;\r
+void *pvReturn = NULL;\r
+\r
+ vTaskSuspendAll();\r
+ {\r
+ /* If this is the first call to malloc then the heap will require\r
+ initialisation to setup the list of free blocks. */\r
+ if( xHeapHasBeenInitialised == pdFALSE )\r
+ {\r
+ prvHeapInit();\r
+ xHeapHasBeenInitialised = pdTRUE;\r
+ }\r
+\r
+ /* The wanted size is increased so it can contain a xBlockLink\r
+ structure in addition to the requested amount of bytes. */\r
+ if( xWantedSize > 0 )\r
+ {\r
+ xWantedSize += heapSTRUCT_SIZE;\r
+\r
+ /* Ensure that blocks are always aligned to the required number of bytes. */\r
+ if( xWantedSize & heapBYTE_ALIGNMENT_MASK )\r
+ {\r
+ /* Byte alignment required. */\r
+ xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & heapBYTE_ALIGNMENT_MASK ) );\r
+ }\r
+ }\r
+\r
+ if( ( xWantedSize > 0 ) && ( xWantedSize < configTOTAL_HEAP_SIZE ) )\r
+ {\r
+ /* Blocks are stored in byte order - traverse the list from the start\r
+ (smallest) block until one of adequate size is found. */\r
+ pxPreviousBlock = &xStart;\r
+ pxBlock = xStart.pxNextFreeBlock;\r
+ while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock ) )\r
+ {\r
+ pxPreviousBlock = pxBlock;\r
+ pxBlock = pxBlock->pxNextFreeBlock;\r
+ }\r
+\r
+ /* If we found the end marker then a block of adequate size was not found. */\r
+ if( pxBlock != &xEnd )\r
+ {\r
+ /* Return the memory space - jumping over the xBlockLink structure\r
+ at its start. */\r
+ pvReturn = ( void * ) ( ( ( unsigned portCHAR * ) pxPreviousBlock->pxNextFreeBlock ) + heapSTRUCT_SIZE );\r
+\r
+ /* This block is being returned for use so must be taken our of the\r
+ list of free blocks. */\r
+ pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;\r
+\r
+ /* If the block is larger than required it can be split into two. */\r
+ if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )\r
+ {\r
+ /* This block is to be split into two. Create a new block\r
+ following the number of bytes requested. The void cast is\r
+ used to prevent byte alignment warnings from the compiler. */\r
+ pxNewBlockLink = ( void * ) ( ( ( unsigned portCHAR * ) pxBlock ) + xWantedSize );\r
+ \r
+ /* Calculate the sizes of two blocks split from the single\r
+ block. */\r
+ pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; \r
+ pxBlock->xBlockSize = xWantedSize; \r
+ \r
+ /* Insert the new block into the list of free blocks. */\r
+ prvInsertBlockIntoFreeList( ( pxNewBlockLink ) );\r
+ }\r
+ }\r
+ }\r
+ }\r
+ xTaskResumeAll();\r
+\r
+ return pvReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortFree( void *pv )\r
+{\r
+unsigned portCHAR *puc = ( unsigned portCHAR * ) pv;\r
+xBlockLink *pxLink;\r
+\r
+ if( pv )\r
+ {\r
+ /* The memory being freed will have an xBlockLink structure immediately\r
+ before it. */\r
+ puc -= heapSTRUCT_SIZE;\r
+\r
+ /* This casting is to keep the compiler from issuing warnings. */\r
+ pxLink = ( void * ) puc;\r
+\r
+ vTaskSuspendAll();\r
+ { \r
+ /* Add this block to the list of free blocks. */\r
+ prvInsertBlockIntoFreeList( ( ( xBlockLink * ) pxLink ) );\r
+ }\r
+ xTaskResumeAll();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+\r
+/*\r
+ * Implementation of pvPortMalloc() and vPortFree() that relies on the\r
+ * compilers own malloc() and free() implementations.\r
+ *\r
+ * This file can only be used if the linker is configured to to generate\r
+ * a heap memory area.\r
+ *\r
+ * See heap_2.c and heap_1.c for alternative implementations, and the memory\r
+ * management pages of http://www.FreeRTOS.org for more information.\r
+ */\r
+\r
+#include <stdlib.h>\r
+\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void *pvPortMalloc( size_t xWantedSize )\r
+{\r
+void *pvReturn;\r
+\r
+ vTaskSuspendAll();\r
+ {\r
+ pvReturn = malloc( xWantedSize );\r
+ }\r
+ xTaskResumeAll();\r
+\r
+ return pvReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortFree( void *pv )\r
+{\r
+ if( pv )\r
+ {\r
+ vTaskSuspendAll();\r
+ {\r
+ free( pv );\r
+ }\r
+ xTaskResumeAll();\r
+ }\r
+}\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+ Changes between V4.0.0 and V4.0.1\r
+\r
+ + Reduced the code used to setup the initial stack frame.\r
+ + The kernel no longer has to install or handle the fault interrupt.\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Implementation of functions defined in portable.h for the ARM CM3 port.\r
+ *----------------------------------------------------------*/\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Constants required to manipulate the NVIC. */\r
+#define portNVIC_SYSTICK_CTRL ( ( volatile unsigned portLONG *) 0xe000e010 )\r
+#define portNVIC_SYSTICK_LOAD ( ( volatile unsigned portLONG *) 0xe000e014 )\r
+#define portNVIC_INT_CTRL ( ( volatile unsigned portLONG *) 0xe000ed04 )\r
+#define portNVIC_SYSPRI2 ( ( volatile unsigned portLONG *) 0xe000ed20 )\r
+#define portNVIC_SYSPRI1 ( ( volatile unsigned portLONG *) 0xe000ed1c )\r
+#define portNVIC_HARD_FAULT_STATUS 0xe000ed2c\r
+#define portNVIC_FORCED_FAULT_BIT 0x40000000\r
+#define portNVIC_SYSTICK_CLK 0x00000004\r
+#define portNVIC_SYSTICK_INT 0x00000002\r
+#define portNVIC_SYSTICK_ENABLE 0x00000001\r
+#define portNVIC_PENDSVSET 0x10000000\r
+#define portNVIC_PENDSV_PRI 0x00ff0000\r
+#define portNVIC_SVCALL_PRI 0xff000000\r
+#define portNVIC_SYSTICK_PRI 0xff000000\r
+\r
+/* Constants required to set up the initial stack. */\r
+#define portINITIAL_XPSR ( 0x01000000 )\r
+\r
+/* Each task maintains its own interrupt status in the critical nesting\r
+variable. */\r
+unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;\r
+\r
+/* Constant hardware definitions to assist asm code. */\r
+const unsigned long ulHardFaultStatus = portNVIC_HARD_FAULT_STATUS;\r
+const unsigned long ulNVICIntCtrl = ( unsigned long ) 0xe000ed04;\r
+const unsigned long ulForceFaultBit = portNVIC_FORCED_FAULT_BIT;\r
+const unsigned long ulPendSVBit = portNVIC_PENDSVSET;\r
+\r
+/* \r
+ * Setup the timer to generate the tick interrupts.\r
+ */\r
+static void prvSetupTimerInterrupt( void );\r
+\r
+/*\r
+ * Set the MSP/PSP to a known value.\r
+ */\r
+void prvSetMSP( unsigned long ulValue );\r
+void prvSetPSP( unsigned long ulValue );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* \r
+ * See header file for description. \r
+ */\r
+portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
+{\r
+ /* Simulate the stack frame as it would be created by a context switch\r
+ interrupt. */\r
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* PC */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0xfffffffd; /* LR */\r
+ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */\r
+ pxTopOfStack -= 9; /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
+ *pxTopOfStack = 0x00000000; /* uxCriticalNesting. */\r
+\r
+ return pxTopOfStack;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+__asm void prvSetPSP( unsigned long ulValue )\r
+{\r
+ msr psp, r0\r
+ bx lr;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+__asm void prvSetMSP( unsigned long ulValue )\r
+{\r
+ msr msp, r0\r
+ bx lr;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* \r
+ * See header file for description. \r
+ */\r
+portBASE_TYPE xPortStartScheduler( void )\r
+{\r
+ /* Start the timer that generates the tick ISR. Interrupts are disabled\r
+ here already. */\r
+ prvSetupTimerInterrupt();\r
+\r
+ /* Make PendSV, CallSV and SysTick the lowest priority interrupts. */\r
+ *(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI;\r
+ *(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI;\r
+ *(portNVIC_SYSPRI1) |= portNVIC_SVCALL_PRI;\r
+\r
+ /* Start the first task. */\r
+ prvSetPSP( 0 );\r
+ prvSetMSP( *((unsigned portLONG *) 0 ) );\r
+ *(portNVIC_INT_CTRL) |= portNVIC_PENDSVSET;\r
+\r
+ /* Enable interrupts */\r
+ portENABLE_INTERRUPTS();\r
+\r
+ /* Should not get here! */\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEndScheduler( void )\r
+{\r
+ /* It is unlikely that the CM3 port will require this function as there\r
+ is nothing to return to. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortYieldFromISR( void )\r
+{\r
+ /* Set a PendSV to request a context switch. */\r
+ *(portNVIC_INT_CTRL) |= portNVIC_PENDSVSET; \r
+ portENABLE_INTERRUPTS();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+__asm void vPortDisableInterrupts( void )\r
+{\r
+ cpsid i;\r
+ bx lr;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+__asm void vPortEnableInterrupts( void )\r
+{\r
+ cpsie i;\r
+ bx lr;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEnterCritical( void )\r
+{\r
+ vPortDisableInterrupts();\r
+ uxCriticalNesting++;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortExitCritical( void )\r
+{\r
+ uxCriticalNesting--;\r
+ if( uxCriticalNesting == 0 )\r
+ {\r
+ vPortEnableInterrupts();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+__asm void xPortPendSVHandler( void )\r
+{\r
+ extern uxCriticalNesting;\r
+ extern pxCurrentTCB;\r
+ extern vTaskSwitchContext;\r
+\r
+ /* Start first task if the stack has not yet been setup. */\r
+ mrs r0, psp\r
+ cbz r0, no_save\r
+\r
+ /* Save the context into the TCB. */\r
+ sub r0, #0x20\r
+ stm r0, {r4-r11}\r
+ sub r0, #0x04\r
+ ldr r1, =uxCriticalNesting\r
+ ldr r1, [r1]\r
+ stm r0, {r1}\r
+ ldr r1, =pxCurrentTCB\r
+ ldr r1, [r1]\r
+ str r0, [r1]\r
+\r
+no_save;\r
+ \r
+ /* Find the task to execute. */\r
+ ldr r0, =vTaskSwitchContext\r
+ push {r14}\r
+ cpsid i\r
+ blx r0\r
+ cpsie i\r
+ pop {r14} \r
+\r
+ /* Restore the context. */\r
+ ldr r1, =pxCurrentTCB\r
+ ldr r1, [r1];\r
+ ldr r0, [r1];\r
+ ldm r0, {r1, r4-r11}\r
+ ldr r2, =uxCriticalNesting\r
+ str r1, [r2]\r
+ ldr r2, [r2]\r
+ add r0, #0x24\r
+ msr psp, r0\r
+ orr r14, #0xd\r
+\r
+ /* Exit with interrupts in the state required by the task. */\r
+ cbnz r2, sv_disable_interrupts\r
+ \r
+ bx r14\r
+\r
+sv_disable_interrupts;\r
+ cpsid i\r
+ bx r14\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+__asm void xPortSysTickHandler( void )\r
+{\r
+ extern vTaskIncrementTick\r
+\r
+ /* Call the scheduler tick function. */\r
+ ldr r0, =vTaskIncrementTick\r
+ push {r14}\r
+ cpsid i\r
+ blx r0\r
+ cpsie i\r
+ pop {r14} \r
+\r
+ /* If using preemption, also force a context switch. */\r
+ #if configUSE_PREEMPTION == 1\r
+ extern vPortYieldFromISR\r
+ push {r14}\r
+ ldr r0, =vPortYieldFromISR\r
+ blx r0\r
+ pop {r14}\r
+ #endif\r
+\r
+ /* Exit with interrupts in the correct state. */\r
+ ldr r2, =uxCriticalNesting\r
+ ldr r2, [r2]\r
+ cbnz r2, tick_disable_interrupts\r
+\r
+ bx r14\r
+\r
+tick_disable_interrupts;\r
+ cpsid i\r
+ bx r14\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Setup the systick timer to generate the tick interrupts at the required\r
+ * frequency.\r
+ */\r
+void prvSetupTimerInterrupt( void )\r
+{\r
+ /* Configure SysTick to interrupt at the requested rate. */\r
+ *(portNVIC_SYSTICK_LOAD) = configCPU_CLOCK_HZ / configTICK_RATE_HZ;\r
+ *(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;\r
+}\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Port specific definitions. \r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the\r
+ * given hardware and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *-----------------------------------------------------------\r
+ */\r
+\r
+/* Type definitions. */\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE double\r
+#define portLONG long\r
+#define portSHORT short\r
+#define portSTACK_TYPE unsigned portLONG\r
+#define portBASE_TYPE long\r
+\r
+#if( configUSE_16_BIT_TICKS == 1 )\r
+ typedef unsigned portSHORT portTickType;\r
+ #define portMAX_DELAY ( portTickType ) 0xffff\r
+#else\r
+ typedef unsigned portLONG portTickType;\r
+ #define portMAX_DELAY ( portTickType ) 0xffffffff\r
+#endif\r
+/*-----------------------------------------------------------*/ \r
+\r
+/* Architecture specifics. */\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) \r
+#define portBYTE_ALIGNMENT 4\r
+/*-----------------------------------------------------------*/ \r
+\r
+\r
+/* Scheduler utilities. */\r
+extern void vPortYield( void );\r
+extern void vPortYieldFromISR( void );\r
+\r
+#define portYIELD() vPortYieldFromISR()\r
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) vPortYieldFromISR()\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+/* Critical section management. */\r
+\r
+extern void vPortDisableInterrupts( void );\r
+extern void vPortEnableInterrupts( void );\r
+extern void vPortEnterCritical( void );\r
+extern void vPortExitCritical( void );\r
+\r
+#define portDISABLE_INTERRUPTS() vPortDisableInterrupts()\r
+#define portENABLE_INTERRUPTS() vPortEnableInterrupts()\r
+#define portENTER_CRITICAL() vPortEnterCritical()\r
+#define portEXIT_CRITICAL() vPortExitCritical()\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Task function macros as described on the FreeRTOS.org WEB site. */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+\r
+#define inline\r
+#define portNOP()\r
+\r
+#endif /* PORTMACRO_H */\r
+\r
--- /dev/null
+The Rowley ARM7 demo uses the GCC ARM7 port files.
\ No newline at end of file
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/*-----------------------------------------------------------\r
+ * Implementation of functions defined in portable.h for the MSP430 port.\r
+ *----------------------------------------------------------*/\r
+\r
+/* Constants required for hardware setup. The tick ISR runs off the ACLK, \r
+not the MCLK. */\r
+#define portACLK_FREQUENCY_HZ ( ( portTickType ) 32768 )\r
+#define portINITIAL_CRITICAL_NESTING ( ( unsigned portSHORT ) 10 )\r
+#define portFLAGS_INT_ENABLED ( ( portSTACK_TYPE ) 0x08 )\r
+\r
+/* We require the address of the pxCurrentTCB variable, but don't want to know\r
+any details of its type. */\r
+typedef void tskTCB;\r
+extern volatile tskTCB * volatile pxCurrentTCB;\r
+\r
+/* Each task maintains a count of the critical section nesting depth. Each \r
+time a critical section is entered the count is incremented. Each time a \r
+critical section is exited the count is decremented - with interrupts only \r
+being re-enabled if the count is zero.\r
+\r
+usCriticalNesting will get set to zero when the scheduler starts, but must\r
+not be initialised to zero as this will cause problems during the startup\r
+sequence. */\r
+volatile unsigned portSHORT usCriticalNesting = portINITIAL_CRITICAL_NESTING;\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+/*\r
+ * Sets up the periodic ISR used for the RTOS tick. This uses timer 0, but\r
+ * could have alternatively used the watchdog timer or timer 1.\r
+ */\r
+void prvSetupTimerInterrupt( void );\r
+/*-----------------------------------------------------------*/\r
+\r
+/* \r
+ * Initialise the stack of a task to look exactly as if a call to \r
+ * portSAVE_CONTEXT had been called.\r
+ * \r
+ * See the header file portable.h.\r
+ */\r
+portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
+{\r
+ /* \r
+ Place a few bytes of known values on the bottom of the stack. \r
+ This is just useful for debugging and can be included if required.\r
+\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x1111;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x2222;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x3333;\r
+ pxTopOfStack--; \r
+ */\r
+\r
+ /* The msp430 automatically pushes the PC then SR onto the stack before \r
+ executing an ISR. We want the stack to look just as if this has happened\r
+ so place a pointer to the start of the task on the stack first - followed\r
+ by the flags we want the task to use when it starts up. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) pxCode;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portFLAGS_INT_ENABLED;\r
+ pxTopOfStack--;\r
+\r
+ /* Next the general purpose registers. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x4444;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x5555;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x6666;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x7777;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x8888;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x9999;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaa;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0xbbbb;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0xcccc;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0xdddd;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0xeeee;\r
+ pxTopOfStack--;\r
+\r
+ /* When the task starts is will expect to find the function parameter in\r
+ R15. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) pvParameters;\r
+ pxTopOfStack--;\r
+\r
+ /* A variable is used to keep track of the critical section nesting. \r
+ This variable has to be stored as part of the task context and is \r
+ initially set to zero. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) portNO_CRITICAL_SECTION_NESTING; \r
+\r
+ /* Return a pointer to the top of the stack we have generated so this can\r
+ be stored in the task control block for the task. */\r
+ return pxTopOfStack;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEndScheduler( void )\r
+{\r
+ /* It is unlikely that the MSP430 port will get stopped. If required simply\r
+ disable the tick interrupt here. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Hardware initialisation to generate the RTOS tick. This uses timer 0\r
+ * but could alternatively use the watchdog timer or timer 1. \r
+ */\r
+void prvSetupTimerInterrupt( void )\r
+{\r
+ /* Ensure the timer is stopped. */\r
+ TACTL = 0;\r
+\r
+ /* Run the timer of the ACLK. */\r
+ TACTL = TASSEL_1;\r
+\r
+ /* Clear everything to start with. */\r
+ TACTL |= TACLR;\r
+\r
+ /* Set the compare match value according to the tick rate we want. */\r
+ TACCR0 = portACLK_FREQUENCY_HZ / configTICK_RATE_HZ;\r
+\r
+ /* Enable the interrupts. */\r
+ TACCTL0 = CCIE;\r
+\r
+ /* Start up clean. */\r
+ TACTL |= TACLR;\r
+\r
+ /* Up mode. */\r
+ TACTL |= MC_1;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+ \r
--- /dev/null
+#include "FreeRTOSConfig.h"\r
+\r
+portSAVE_CONTEXT macro\r
+ push r4\r
+ push r5\r
+ push r6\r
+ push r7\r
+ push r8\r
+ push r9\r
+ push r10\r
+ push r11\r
+ push r12\r
+ push r13\r
+ push r14\r
+ push r15\r
+ mov.w &_usCriticalNesting, r14\r
+ push r14\r
+ mov.w &_pxCurrentTCB, r12\r
+ mov.w r1, @r12\r
+ endm\r
+/*-----------------------------------------------------------*/\r
+ \r
+portRESTORE_CONTEXT macro\r
+ mov.w &_pxCurrentTCB, r12\r
+ mov.w @r12, r1\r
+ pop r15\r
+ mov.w r15, &_usCriticalNesting\r
+ pop r15\r
+ pop r14\r
+ pop r13\r
+ pop r12\r
+ pop r11\r
+ pop r10\r
+ pop r9\r
+ pop r8\r
+ pop r7\r
+ pop r6\r
+ pop r5\r
+ pop r4\r
+ reti\r
+ endm\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+.CODE\r
+\r
+/*\r
+ * The RTOS tick ISR.\r
+ *\r
+ * If the cooperative scheduler is in use this simply increments the tick \r
+ * count.\r
+ *\r
+ * If the preemptive scheduler is in use a context switch can also occur.\r
+ */\r
+_vTickISR:\r
+ portSAVE_CONTEXT\r
+ \r
+ call #_vTaskIncrementTick\r
+\r
+ #if configUSE_PREEMPTION == 1\r
+ call #_vTaskSwitchContext\r
+ #endif\r
+ \r
+ portRESTORE_CONTEXT\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+/*\r
+ * Manual context switch called by the portYIELD() macro.\r
+ */ \r
+_vPortYield::\r
+\r
+ /* Mimic an interrupt by pushing the SR. */\r
+ push SR \r
+\r
+ /* Now the SR is stacked we can disable interrupts. */\r
+ dint \r
+ \r
+ /* Save the context of the current task. */\r
+ portSAVE_CONTEXT \r
+\r
+ /* Switch to the highest priority task that is ready to run. */\r
+ call #_vTaskSwitchContext \r
+\r
+ /* Restore the context of the new task. */\r
+ portRESTORE_CONTEXT\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+/*\r
+ * Start off the scheduler by initialising the RTOS tick timer, then restoring\r
+ * the context of the first task.\r
+ */\r
+_xPortStartScheduler::\r
+\r
+ /* Setup the hardware to generate the tick. Interrupts are disabled \r
+ when this function is called. */\r
+ call #_prvSetupTimerInterrupt\r
+\r
+ /* Restore the context of the first task that is going to run. */\r
+ portRESTORE_CONTEXT\r
+/*-----------------------------------------------------------*/ \r
+ \r
+\r
+ /* Place the tick ISR in the correct vector. */\r
+ .VECTORS\r
+ \r
+ .KEEP\r
+ \r
+ ORG TIMERA0_VECTOR\r
+ DW _vTickISR\r
+ \r
+\r
+\r
+ END\r
+ \r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Port specific definitions. \r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the\r
+ * given hardware and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *-----------------------------------------------------------\r
+ */\r
+\r
+/* Type definitions. */\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE double\r
+#define portLONG long\r
+#define portSHORT int\r
+#define portSTACK_TYPE unsigned portSHORT\r
+#define portBASE_TYPE portSHORT\r
+\r
+#if( configUSE_16_BIT_TICKS == 1 )\r
+ typedef unsigned portSHORT portTickType;\r
+ #define portMAX_DELAY ( portTickType ) 0xffff\r
+#else\r
+ typedef unsigned portLONG portTickType;\r
+ #define portMAX_DELAY ( portTickType ) 0xffffffff\r
+#endif\r
+\r
+/*-----------------------------------------------------------*/ \r
+\r
+/* Interrupt control macros. */\r
+#define portDISABLE_INTERRUPTS() _DINT();\r
+#define portENABLE_INTERRUPTS() _EINT();\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Critical section control macros. */\r
+#define portNO_CRITICAL_SECTION_NESTING ( ( unsigned portSHORT ) 0 )\r
+\r
+#define portENTER_CRITICAL() \\r
+{ \\r
+extern volatile unsigned portSHORT usCriticalNesting; \\r
+ \\r
+ portDISABLE_INTERRUPTS(); \\r
+ \\r
+ /* Now interrupts are disabled usCriticalNesting can be accessed */ \\r
+ /* directly. Increment ulCriticalNesting to keep a count of how many */ \\r
+ /* times portENTER_CRITICAL() has been called. */ \\r
+ usCriticalNesting++; \\r
+}\r
+\r
+#define portEXIT_CRITICAL() \\r
+{ \\r
+extern volatile unsigned portSHORT usCriticalNesting; \\r
+ \\r
+ if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \\r
+ { \\r
+ /* Decrement the nesting count as we are leaving a critical section. */ \\r
+ usCriticalNesting--; \\r
+ \\r
+ /* If the nesting level has reached zero then interrupts should be */ \\r
+ /* re-enabled. */ \\r
+ if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \\r
+ { \\r
+ portENABLE_INTERRUPTS(); \\r
+ } \\r
+ } \\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Task utilities. */\r
+\r
+/*\r
+ * Manual context switch called by portYIELD or taskYIELD. \r
+ */\r
+extern void vPortYield( void ); \r
+#define portYIELD() vPortYield()\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Hardware specifics. */\r
+#define portBYTE_ALIGNMENT 2\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) \r
+/*-----------------------------------------------------------*/\r
+\r
+/* Task function macros as described on the FreeRTOS.org WEB site. */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) __toplevel\r
+\r
+/* Compiler specifics. */\r
+#define inline\r
+\r
+/* Just used by the demo application to indicate which form of interrupt \r
+service routine should be used. See the online port documentation for more\r
+information. */\r
+#define MSP_ROWLEY_RB_PORT\r
+\r
+#define portNOP()\r
+\r
+#endif /* PORTMACRO_H */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+\r
+/*\r
+ * Milos Prokic\r
+ * \r
+ * File adopted from the MSP430 GCC port\r
+ * Interrupt handling, xPortStartScheduler, vPortYield, portSAVE_CONTEXT(), portRESTORE_CONTEXT() \r
+/* Standard includes. */\r
+\r
+#include <stdlib.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/*-----------------------------------------------------------\r
+ * Implementation of functions defined in portable.h for the MSP430 port.\r
+ *----------------------------------------------------------*/\r
+\r
+/* Constants required for hardware setup. The tick ISR runs off the ACLK, \r
+not the MCLK. */\r
+#define portACLK_FREQUENCY_HZ ( ( portTickType ) 32768 )\r
+#define portINITIAL_CRITICAL_NESTING ( ( unsigned portSHORT ) 10 )\r
+#define portFLAGS_INT_ENABLED ( ( portSTACK_TYPE ) 0x08 )\r
+\r
+/* We require the address of the pxCurrentTCB variable, but don't want to know\r
+any details of its type. */\r
+typedef void tskTCB;\r
+extern volatile tskTCB * volatile pxCurrentTCB;\r
+\r
+unsigned portCHAR ucReschedule;\r
+\r
+/* Each task maintains a count of the critical section nesting depth. Each \r
+time a critical section is entered the count is incremented. Each time a \r
+critical section is exited the count is decremented - with interrupts only \r
+being re-enabled if the count is zero.\r
+\r
+usCriticalNesting will get set to zero when the scheduler starts, but must\r
+not be initialised to zero as this will cause problems during the startup\r
+sequence. */\r
+volatile unsigned portSHORT usCriticalNesting = portINITIAL_CRITICAL_NESTING;\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Sets up the periodic ISR used for the RTOS tick. This uses timer 0, but\r
+ * could have alternatively used the watchdog timer or timer 1.\r
+ */\r
+void prvSetupTimerInterrupt( void );\r
+/*-----------------------------------------------------------*/\r
+\r
+/* \r
+ * Initialise the stack of a task to look exactly as if a call to \r
+ * portSAVE_CONTEXT had been called.\r
+ * \r
+ * See the header file portable.h.\r
+ */\r
+portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
+{\r
+ /* \r
+ Place a few bytes of known values on the bottom of the stack. \r
+ This is just useful for debugging and can be included if required.\r
+\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x1111;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x2222;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x3333;\r
+ pxTopOfStack--; \r
+ */\r
+\r
+ /* The msp430 automatically pushes the PC then SR onto the stack before \r
+ executing an ISR. We want the stack to look just as if this has happened\r
+ so place a pointer to the start of the task on the stack first - followed\r
+ by the flags we want the task to use when it starts up. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) pxCode;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portFLAGS_INT_ENABLED;\r
+ pxTopOfStack--;\r
+\r
+ /* Next the general purpose registers. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x4444;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x5555;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x6666;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x7777;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x8888;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x9999;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaa;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0xbbbb;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0xcccc;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0xdddd;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0xeeee;\r
+ pxTopOfStack--;\r
+\r
+ /* When the task starts is will expect to find the function parameter in\r
+ R15. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) pvParameters;\r
+ pxTopOfStack--;\r
+\r
+ /* A variable is used to keep track of the critical section nesting. \r
+ This variable has to be stored as part of the task context and is \r
+ initially set to zero. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) portNO_CRITICAL_SECTION_NESTING; \r
+\r
+ /* Return a pointer to the top of the stack we have generated so this can\r
+ be stored in the task control block for the task. */\r
+ return pxTopOfStack;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEndScheduler( void )\r
+{\r
+ /* It is unlikely that the MSP430 port will get stopped. If required simply\r
+ disable the tick interrupt here. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Hardware initialisation to generate the RTOS tick. This uses timer 0\r
+ * but could alternatively use the watchdog timer or timer 1. \r
+ */\r
+void prvSetupTimerInterrupt( void )\r
+{\r
+ /* Ensure the timer is stopped. */\r
+ TACTL = 0;\r
+\r
+ /* Run the timer of the ACLK. */\r
+ TACTL = TASSEL_1;\r
+\r
+ /* Clear everything to start with. */\r
+ TACTL |= TACLR;\r
+\r
+ /* Set the compare match value according to the tick rate we want. */\r
+ TACCR0 = portACLK_FREQUENCY_HZ / configTICK_RATE_HZ;\r
+\r
+ /* Enable the interrupts. */\r
+ TACCTL0 = CCIE;\r
+\r
+ /* Start up clean. */\r
+ TACTL |= TACLR;\r
+\r
+ /* Up mode. */\r
+ TACTL |= MC_1;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* \r
+ * The interrupt service routine used depends on whether the pre-emptive\r
+ * scheduler is being used or not.\r
+ */\r
+\r
+#if configUSE_PREEMPTION == 1\r
+\r
+ /*\r
+ * Tick ISR for preemptive scheduler. We can use a naked attribute as\r
+ * the context is saved at the start of vPortYieldFromTick(). The tick\r
+ * count is incremented after the context is saved.\r
+ */\r
+ void ISROsTick( void )\r
+ {\r
+ /* Increment the tick count then switch to the highest priority task\r
+ that is ready to run. */\r
+ vTaskIncrementTick();\r
+ vTaskSwitchContext();\r
+ }\r
+\r
+#else\r
+\r
+ /*\r
+ * Tick ISR for the cooperative scheduler. All this does is increment the\r
+ * tick count. We don't need to switch context, this can only be done by\r
+ * manual calls to taskYIELD();\r
+ */\r
+ void ISROsTick( void )\r
+ {\r
+ vTaskIncrementTick();\r
+ }\r
+#endif\r
+\r
+\r
+ \r
--- /dev/null
+#include <msp430x14x.h>\r
+\r
+/*\r
+ * Milos Prokic\r
+ */\r
+\r
+/**********************************************************\r
+All Interrupts should follow the naming convention : ISR"name" and declared\r
+as a normal function in C.\r
+\r
+One must not forget to allocate interrupts below (see the line "MSPINT OsTick"\r
+below for an example).\r
+\r
+By default the ISR will not cause the context switch, but if called in \r
+conjunction with portENTER_SWITCHING_ISR/portEXIT_SWITCHING_ISR(wakeup), where \r
+wakeup = TRUE upon exit the ISR will force the context switch via the \r
+ucReschedule global variable.\r
+**********************************************************/ \r
+MSPINT macro name\r
+_##name::\r
+ call #_portSAVE_CONTEXT \r
+ call #_ISR##name \r
+ br #_portSWITCH_EXIT \r
+ endm\r
+\r
+\r
+/**********************************************************\r
+API code\r
+**********************************************************/ \r
+\r
+ .CODE\r
+_vPortYield::\r
+ /* Mimic an INT call by pushing SR. */\r
+ push SR \r
+ /* no INTs !! */\r
+ dint \r
+ /* Save the context of the current task. */\r
+ call #_portSAVE_CONTEXT \r
+ /* Switch to the highest priority task that is ready to run. */\r
+ call #_vTaskSwitchContext \r
+ /* Restore the context of the new task. */\r
+ br #_portSWITCH_EXIT \r
+\r
+_xPortStartScheduler::\r
+ /* Setup the hardware to generate the tick. Interrupts are disabled when\r
+ this function is called. */\r
+ call #_prvSetupTimerInterrupt\r
+\r
+ /* Restore the context of the first task that is going to run. */\r
+ jmp _portRESTORE_CONTEXT\r
+ \r
+_portSAVE_CONTEXT::\r
+ /* Function to save the context. When this function is called the\r
+ return address will appear on the stack. This does not need to be\r
+ saved so is overwritten by R4 - hence R4 is not saved initially.\r
+\r
+ Save the general purpose registers. */\r
+ push R5 \r
+ push R6 \r
+ push R7\r
+ push R8 \r
+ push R9\r
+ push R10 \r
+ push R11 \r
+ push R12 \r
+ push R13 \r
+ push R14 \r
+ push R15 \r
+\r
+ /* Now R10 has been saved we can use it to hold the return address, \r
+ which is about to be overwritten. */\r
+ mov 22(R1),R10 \r
+\r
+ /* Store R4 where the return address was on the stack. */\r
+ mov R4,22(R1) \r
+\r
+ /* Save the critical nesting depth. */\r
+ mov.w &_usCriticalNesting, R14 \r
+ push R14 \r
+\r
+ /* Finally save the new top of stack. */\r
+ mov.w &_pxCurrentTCB, R12 \r
+ mov.w R1, @R12\r
+\r
+ /* No rescheduling by default. */\r
+ mov.b #0,&_ucReschedule \r
+\r
+ /* Return using the saved return address. */\r
+ br R10 \r
+\r
+\r
+_portSWITCH_EXIT::\r
+ /* Check ucReschedule to see if a context switch is required. */\r
+ tst.b &_ucReschedule\r
+ jz _portRESTORE_CONTEXT\r
+ call #_vTaskSwitchContext\r
+_portRESTORE_CONTEXT:: \r
+ /* Restore the context in the opposite order to the save. */\r
+ mov.w &_pxCurrentTCB, R12\r
+ mov.w @R12, R1\r
+ pop R15\r
+ mov.w R15, &_usCriticalNesting\r
+ pop R15\r
+ pop R14 \r
+ pop R13 \r
+ pop R12 \r
+ pop R11 \r
+ pop R10 \r
+ pop R9 \r
+ pop R8 \r
+ pop R7 \r
+ pop R6 \r
+ pop R5 \r
+ pop R4 \r
+ reti \r
+ \r
+\r
+/**********************************************************\r
+Allocate Interrupts using the MSPINT macro (defined at the top of this file.\r
+ex: MSPINT "name"\r
+**********************************************************/ \r
+ \r
+ MSPINT OsTick\r
+ MSPINT Com1Rx\r
+ MSPINT Com1Tx\r
+ \r
+\r
+/*********************************************************\r
+Interrupt Vectors\r
+Timer_A0\r
+ex: PORT1 would look like:\r
+ORG PORT1_VECTOR\r
+DW _"name"\r
+**********************************************************/ \r
+ .VECTORS\r
+ .KEEP\r
+\r
+ ORG TIMERA0_VECTOR\r
+ DW _OsTick\r
+\r
+ ORG UART1RX_VECTOR\r
+ DW _Com1Rx\r
+\r
+ ORG UART1TX_VECTOR\r
+ DW _Com1Tx \r
+ \r
+ END\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Port specific definitions. \r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the\r
+ * given hardware and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *-----------------------------------------------------------\r
+ */\r
+\r
+/* Type definitions. */\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE double\r
+#define portLONG long\r
+#define portSHORT int\r
+#define portSTACK_TYPE unsigned portSHORT\r
+#define portBASE_TYPE portSHORT\r
+\r
+#if( configUSE_16_BIT_TICKS == 1 )\r
+ typedef unsigned portSHORT portTickType;\r
+ #define portMAX_DELAY ( portTickType ) 0xffff\r
+#else\r
+ typedef unsigned portLONG portTickType;\r
+ #define portMAX_DELAY ( portTickType ) 0xffffffff\r
+#endif\r
+/*-----------------------------------------------------------*/ \r
+\r
+/* Interrupt control macros. */\r
+#define portDISABLE_INTERRUPTS() _DINT();\r
+#define portENABLE_INTERRUPTS() _EINT();\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Critical section control macros. */\r
+#define portNO_CRITICAL_SECTION_NESTING ( ( unsigned portSHORT ) 0 )\r
+\r
+#define portENTER_CRITICAL() \\r
+{ \\r
+extern volatile unsigned portSHORT usCriticalNesting; \\r
+ \\r
+ portDISABLE_INTERRUPTS(); \\r
+ \\r
+ /* Now interrupts are disabled ulCriticalNesting can be accessed */ \\r
+ /* directly. Increment ulCriticalNesting to keep a count of how many */ \\r
+ /* times portENTER_CRITICAL() has been called. */ \\r
+ usCriticalNesting++; \\r
+}\r
+\r
+#define portEXIT_CRITICAL() \\r
+{ \\r
+extern volatile unsigned portSHORT usCriticalNesting; \\r
+ \\r
+ if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \\r
+ { \\r
+ /* Decrement the nesting count as we are leaving a critical section. */ \\r
+ usCriticalNesting--; \\r
+ \\r
+ /* If the nesting level has reached zero then interrupts should be */ \\r
+ /* re-enabled. */ \\r
+ if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \\r
+ { \\r
+ portENABLE_INTERRUPTS(); \\r
+ } \\r
+ } \\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Task utilities. */\r
+\r
+/*\r
+ * Manual context switch called by portYIELD or taskYIELD. \r
+ */\r
+extern void vPortYield( void );\r
+ \r
+#define portYIELD() vPortYield()\r
+/*-----------------------------------------------------------*/\r
+\r
+#define portENTER_SWITCHING_ISR()\r
+#define portEXIT_SWITCHING_ISR( SwitchRequired ) \\r
+ { \\r
+ extern unsigned portCHAR ucReschedule; \\r
+ if( SwitchRequired ) \\r
+ { \\r
+ ucReschedule = 1; \\r
+ } \\r
+ }\r
+\r
+/* Hardwware specifics. */\r
+#define portBYTE_ALIGNMENT 2\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) \r
+/*-----------------------------------------------------------*/\r
+\r
+/* Task function macros as described on the FreeRTOS.org WEB site. */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) __toplevel\r
+\r
+/* Compiler specifics. */\r
+#define inline\r
+#define portNOP()\r
+\r
+\r
+/* Just used by the demo application to indicate which form of interrupt \r
+service routine should be used. See the online port documentation for more\r
+information. */\r
+#define MSP_ROWLEY_MP_PORT\r
+\r
+#endif /* PORTMACRO_H */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/*-----------------------------------------------------------\r
+ * Implementation of functions defined in portable.h for the MSP430 port.\r
+ *----------------------------------------------------------*/\r
+\r
+/* Constants required for hardware setup. The tick ISR runs off the ACLK, \r
+not the MCLK. */\r
+#define portACLK_FREQUENCY_HZ ( ( portTickType ) 32768 )\r
+#define portINITIAL_CRITICAL_NESTING ( ( unsigned portSHORT ) 10 )\r
+#define portFLAGS_INT_ENABLED ( ( portSTACK_TYPE ) 0x08 )\r
+\r
+/* We require the address of the pxCurrentTCB variable, but don't want to know\r
+any details of its type. */\r
+typedef void tskTCB;\r
+extern volatile tskTCB * volatile pxCurrentTCB;\r
+\r
+/* Each task maintains a count of the critical section nesting depth. Each \r
+time a critical section is entered the count is incremented. Each time a \r
+critical section is exited the count is decremented - with interrupts only \r
+being re-enabled if the count is zero.\r
+\r
+usCriticalNesting will get set to zero when the scheduler starts, but must\r
+not be initialised to zero as this will cause problems during the startup\r
+sequence. */\r
+volatile unsigned portSHORT usCriticalNesting = portINITIAL_CRITICAL_NESTING;\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+/*\r
+ * Sets up the periodic ISR used for the RTOS tick. This uses timer 0, but\r
+ * could have alternatively used the watchdog timer or timer 1.\r
+ */\r
+void prvSetupTimerInterrupt( void );\r
+/*-----------------------------------------------------------*/\r
+\r
+/* \r
+ * Initialise the stack of a task to look exactly as if a call to \r
+ * portSAVE_CONTEXT had been called.\r
+ * \r
+ * See the header file portable.h.\r
+ */\r
+portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
+{\r
+ /* \r
+ Place a few bytes of known values on the bottom of the stack. \r
+ This is just useful for debugging and can be included if required.\r
+\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x1111;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x2222;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x3333;\r
+ pxTopOfStack--; \r
+ */\r
+\r
+ /* The msp430 automatically pushes the PC then SR onto the stack before \r
+ executing an ISR. We want the stack to look just as if this has happened\r
+ so place a pointer to the start of the task on the stack first - followed\r
+ by the flags we want the task to use when it starts up. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) pxCode;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portFLAGS_INT_ENABLED;\r
+ pxTopOfStack--;\r
+\r
+ /* Next the general purpose registers. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x4444;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x5555;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x6666;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x7777;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x8888;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x9999;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaa;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0xbbbb;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0xcccc;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0xdddd;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0xeeee;\r
+ pxTopOfStack--;\r
+\r
+ /* When the task starts is will expect to find the function parameter in\r
+ R15. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) pvParameters;\r
+ pxTopOfStack--;\r
+\r
+ /* A variable is used to keep track of the critical section nesting. \r
+ This variable has to be stored as part of the task context and is \r
+ initially set to zero. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) portNO_CRITICAL_SECTION_NESTING; \r
+\r
+ /* Return a pointer to the top of the stack we have generated so this can\r
+ be stored in the task control block for the task. */\r
+ return pxTopOfStack;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEndScheduler( void )\r
+{\r
+ /* It is unlikely that the MSP430 port will get stopped. If required simply\r
+ disable the tick interrupt here. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Hardware initialisation to generate the RTOS tick. This uses timer 0\r
+ * but could alternatively use the watchdog timer or timer 1. \r
+ */\r
+void prvSetupTimerInterrupt( void )\r
+{\r
+ /* Ensure the timer is stopped. */\r
+ TACTL = 0;\r
+\r
+ /* Run the timer of the ACLK. */\r
+ TACTL = TASSEL_1;\r
+\r
+ /* Clear everything to start with. */\r
+ TACTL |= TACLR;\r
+\r
+ /* Set the compare match value according to the tick rate we want. */\r
+ TACCR0 = portACLK_FREQUENCY_HZ / configTICK_RATE_HZ;\r
+\r
+ /* Enable the interrupts. */\r
+ TACCTL0 = CCIE;\r
+\r
+ /* Start up clean. */\r
+ TACTL |= TACLR;\r
+\r
+ /* Up mode. */\r
+ TACTL |= MC_1;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+ \r
--- /dev/null
+#include "FreeRTOSConfig.h"\r
+\r
+portSAVE_CONTEXT macro\r
+ push r4\r
+ push r5\r
+ push r6\r
+ push r7\r
+ push r8\r
+ push r9\r
+ push r10\r
+ push r11\r
+ push r12\r
+ push r13\r
+ push r14\r
+ push r15\r
+ mov.w &_usCriticalNesting, r14\r
+ push r14\r
+ mov.w &_pxCurrentTCB, r12\r
+ mov.w r1, @r12\r
+ endm\r
+/*-----------------------------------------------------------*/\r
+ \r
+portRESTORE_CONTEXT macro\r
+ mov.w &_pxCurrentTCB, r12\r
+ mov.w @r12, r1\r
+ pop r15\r
+ mov.w r15, &_usCriticalNesting\r
+ pop r15\r
+ pop r14\r
+ pop r13\r
+ pop r12\r
+ pop r11\r
+ pop r10\r
+ pop r9\r
+ pop r8\r
+ pop r7\r
+ pop r6\r
+ pop r5\r
+ pop r4\r
+ reti\r
+ endm\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+.CODE\r
+\r
+/*\r
+ * The RTOS tick ISR.\r
+ *\r
+ * If the cooperative scheduler is in use this simply increments the tick \r
+ * count.\r
+ *\r
+ * If the preemptive scheduler is in use a context switch can also occur.\r
+ */\r
+_vTickISR:\r
+ portSAVE_CONTEXT\r
+ \r
+ call #_vTaskIncrementTick\r
+\r
+ #if configUSE_PREEMPTION == 1\r
+ call #_vTaskSwitchContext\r
+ #endif\r
+ \r
+ portRESTORE_CONTEXT\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+/*\r
+ * Manual context switch called by the portYIELD() macro.\r
+ */ \r
+_vPortYield::\r
+\r
+ /* Mimic an interrupt by pushing the SR. */\r
+ push SR \r
+\r
+ /* Now the SR is stacked we can disable interrupts. */\r
+ dint \r
+ \r
+ /* Save the context of the current task. */\r
+ portSAVE_CONTEXT \r
+\r
+ /* Switch to the highest priority task that is ready to run. */\r
+ call #_vTaskSwitchContext \r
+\r
+ /* Restore the context of the new task. */\r
+ portRESTORE_CONTEXT\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+/*\r
+ * Start off the scheduler by initialising the RTOS tick timer, then restoring\r
+ * the context of the first task.\r
+ */\r
+_xPortStartScheduler::\r
+\r
+ /* Setup the hardware to generate the tick. Interrupts are disabled \r
+ when this function is called. */\r
+ call #_prvSetupTimerInterrupt\r
+\r
+ /* Restore the context of the first task that is going to run. */\r
+ portRESTORE_CONTEXT\r
+/*-----------------------------------------------------------*/ \r
+ \r
+\r
+ /* Place the tick ISR in the correct vector. */\r
+ .VECTORS\r
+ \r
+ .KEEP\r
+ \r
+ ORG TIMERA0_VECTOR\r
+ DW _vTickISR\r
+ \r
+\r
+\r
+ END\r
+ \r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Port specific definitions. \r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the\r
+ * given hardware and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *-----------------------------------------------------------\r
+ */\r
+\r
+/* Type definitions. */\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE double\r
+#define portLONG long\r
+#define portSHORT int\r
+#define portSTACK_TYPE unsigned portSHORT\r
+#define portBASE_TYPE portSHORT\r
+\r
+#if( configUSE_16_BIT_TICKS == 1 )\r
+ typedef unsigned portSHORT portTickType;\r
+ #define portMAX_DELAY ( portTickType ) 0xffff\r
+#else\r
+ typedef unsigned portLONG portTickType;\r
+ #define portMAX_DELAY ( portTickType ) 0xffffffff\r
+#endif\r
+\r
+/*-----------------------------------------------------------*/ \r
+\r
+/* Interrupt control macros. */\r
+#define portDISABLE_INTERRUPTS() _DINT();\r
+#define portENABLE_INTERRUPTS() _EINT();\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Critical section control macros. */\r
+#define portNO_CRITICAL_SECTION_NESTING ( ( unsigned portSHORT ) 0 )\r
+\r
+#define portENTER_CRITICAL() \\r
+{ \\r
+extern volatile unsigned portSHORT usCriticalNesting; \\r
+ \\r
+ portDISABLE_INTERRUPTS(); \\r
+ \\r
+ /* Now interrupts are disabled usCriticalNesting can be accessed */ \\r
+ /* directly. Increment ulCriticalNesting to keep a count of how many */ \\r
+ /* times portENTER_CRITICAL() has been called. */ \\r
+ usCriticalNesting++; \\r
+}\r
+\r
+#define portEXIT_CRITICAL() \\r
+{ \\r
+extern volatile unsigned portSHORT usCriticalNesting; \\r
+ \\r
+ if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \\r
+ { \\r
+ /* Decrement the nesting count as we are leaving a critical section. */ \\r
+ usCriticalNesting--; \\r
+ \\r
+ /* If the nesting level has reached zero then interrupts should be */ \\r
+ /* re-enabled. */ \\r
+ if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \\r
+ { \\r
+ portENABLE_INTERRUPTS(); \\r
+ } \\r
+ } \\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Task utilities. */\r
+\r
+/*\r
+ * Manual context switch called by portYIELD or taskYIELD. \r
+ */\r
+extern void vPortYield( void ); \r
+#define portYIELD() vPortYield()\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Hardware specifics. */\r
+#define portBYTE_ALIGNMENT 2\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) \r
+#define portNOP() \r
+/*-----------------------------------------------------------*/\r
+\r
+/* Task function macros as described on the FreeRTOS.org WEB site. */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) __toplevel\r
+\r
+/* Compiler specifics. */\r
+#define inline\r
+\r
+/* Just used by the demo application to indicate which form of interrupt \r
+service routine should be used. See the online port documentation for more\r
+information. */\r
+#define MSP_ROWLEY_RB_PORT\r
+\r
+#endif /* PORTMACRO_H */\r
+\r
--- /dev/null
+To use Port1, copy the three files from the Port1 directory into this directory.\r
+\r
+To use Port2, copy the three files from the Port2 directory into this directory.\r
+\r
+Ensure to perform a complete rebuild.
\ No newline at end of file
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Implementation of functions defined in portable.h for the Cygnal port.\r
+ *----------------------------------------------------------*/\r
+\r
+/* Standard includes. */\r
+#include <string.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Constants required to setup timer 2 to produce the RTOS tick. */\r
+#define portCLOCK_DIVISOR ( ( unsigned portLONG ) 12 )\r
+#define portMAX_TIMER_VALUE ( ( unsigned portLONG ) 0xffff )\r
+#define portENABLE_TIMER ( ( unsigned portCHAR ) 0x04 )\r
+#define portTIMER_2_INTERRUPT_ENABLE ( ( unsigned portCHAR ) 0x20 )\r
+\r
+/* The value used in the IE register when a task first starts. */\r
+#define portGLOBAL_INTERRUPT_BIT ( ( portSTACK_TYPE ) 0x80 )\r
+\r
+/* The value used in the PSW register when a task first starts. */\r
+#define portINITIAL_PSW ( ( portSTACK_TYPE ) 0x00 )\r
+\r
+/* Macro to clear the timer 2 interrupt flag. */\r
+#define portCLEAR_INTERRUPT_FLAG() TMR2CN &= ~0x80;\r
+\r
+/* Used during a context switch to store the size of the stack being copied\r
+to or from XRAM. */\r
+data static unsigned portCHAR ucStackBytes;\r
+\r
+/* Used during a context switch to point to the next byte in XRAM from/to which\r
+a RAM byte is to be copied. */\r
+xdata static portSTACK_TYPE * data pxXRAMStack;\r
+\r
+/* Used during a context switch to point to the next byte in RAM from/to which\r
+an XRAM byte is to be copied. */\r
+data static portSTACK_TYPE * data pxRAMStack;\r
+\r
+/* We require the address of the pxCurrentTCB variable, but don't want to know\r
+any details of its type. */\r
+typedef void tskTCB;\r
+extern volatile tskTCB * volatile pxCurrentTCB;\r
+\r
+/*\r
+ * Setup the hardware to generate an interrupt off timer 2 at the required \r
+ * frequency.\r
+ */\r
+static void prvSetupTimerInterrupt( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+/*\r
+ * Macro that copies the current stack from internal RAM to XRAM. This is \r
+ * required as the 8051 only contains enough internal RAM for a single stack, \r
+ * but we have a stack for every task.\r
+ */\r
+#define portCOPY_STACK_TO_XRAM() \\r
+{ \\r
+ /* pxCurrentTCB points to a TCB which itself points to the location into \\r
+ which the first stack byte should be copied. Set pxXRAMStack to point \\r
+ to the location into which the first stack byte is to be copied. */ \\r
+ pxXRAMStack = ( xdata portSTACK_TYPE * ) *( ( xdata portSTACK_TYPE ** ) pxCurrentTCB ); \\r
+ \\r
+ /* Set pxRAMStack to point to the first byte to be coped from the stack. */ \\r
+ pxRAMStack = ( data portSTACK_TYPE * data ) configSTACK_START; \\r
+ \\r
+ /* Calculate the size of the stack we are about to copy from the current \\r
+ stack pointer value. */ \\r
+ ucStackBytes = SP - ( configSTACK_START - 1 ); \\r
+ \\r
+ /* Before starting to copy the stack, store the calculated stack size so \\r
+ the stack can be restored when the task is resumed. */ \\r
+ *pxXRAMStack = ucStackBytes; \\r
+ \\r
+ /* Copy each stack byte in turn. pxXRAMStack is incremented first as we \\r
+ have already stored the stack size into XRAM. */ \\r
+ while( ucStackBytes ) \\r
+ { \\r
+ pxXRAMStack++; \\r
+ *pxXRAMStack = *pxRAMStack; \\r
+ pxRAMStack++; \\r
+ ucStackBytes--; \\r
+ } \\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Macro that copies the stack of the task being resumed from XRAM into \r
+ * internal RAM.\r
+ */\r
+#define portCOPY_XRAM_TO_STACK() \\r
+{ \\r
+ /* Setup the pointers as per portCOPY_STACK_TO_XRAM(), but this time to \\r
+ copy the data back out of XRAM and into the stack. */ \\r
+ pxXRAMStack = ( xdata portSTACK_TYPE * ) *( ( xdata portSTACK_TYPE ** ) pxCurrentTCB ); \\r
+ pxRAMStack = ( data portSTACK_TYPE * data ) ( configSTACK_START - 1 ); \\r
+ \\r
+ /* The first value stored in XRAM was the size of the stack - i.e. the \\r
+ number of bytes we need to copy back. */ \\r
+ ucStackBytes = pxXRAMStack[ 0 ]; \\r
+ \\r
+ /* Copy the required number of bytes back into the stack. */ \\r
+ do \\r
+ { \\r
+ pxXRAMStack++; \\r
+ pxRAMStack++; \\r
+ *pxRAMStack = *pxXRAMStack; \\r
+ ucStackBytes--; \\r
+ } while( ucStackBytes ); \\r
+ \\r
+ /* Restore the stack pointer ready to use the restored stack. */ \\r
+ SP = ( unsigned portCHAR ) pxRAMStack; \\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Macro to push the current execution context onto the stack, before the stack \r
+ * is moved to XRAM. \r
+ */\r
+#define portSAVE_CONTEXT() \\r
+{ \\r
+ _asm \\r
+ /* Push ACC first, as when restoring the context it must be restored \\r
+ last (it is used to set the IE register). */ \\r
+ push ACC \\r
+ /* Store the IE register then disable interrupts. */ \\r
+ push IE \\r
+ clr _EA \\r
+ push DPL \\r
+ push DPH \\r
+ push b \\r
+ push ar2 \\r
+ push ar3 \\r
+ push ar4 \\r
+ push ar5 \\r
+ push ar6 \\r
+ push ar7 \\r
+ push ar0 \\r
+ push ar1 \\r
+ push PSW \\r
+ _endasm; \\r
+ PSW = 0; \\r
+ _asm \\r
+ push _bp \\r
+ _endasm; \\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Macro that restores the execution context from the stack. The execution \r
+ * context was saved into the stack before the stack was copied into XRAM.\r
+ */\r
+#define portRESTORE_CONTEXT() \\r
+{ \\r
+ _asm \\r
+ pop _bp \\r
+ pop PSW \\r
+ pop ar1 \\r
+ pop ar0 \\r
+ pop ar7 \\r
+ pop ar6 \\r
+ pop ar5 \\r
+ pop ar4 \\r
+ pop ar3 \\r
+ pop ar2 \\r
+ pop b \\r
+ pop DPH \\r
+ pop DPL \\r
+ /* The next byte of the stack is the IE register. Only the global \\r
+ enable bit forms part of the task context. Pop off the IE then set \\r
+ the global enable bit to match that of the stored IE register. */ \\r
+ pop ACC \\r
+ JB ACC.7,0098$ \\r
+ CLR IE.7 \\r
+ LJMP 0099$ \\r
+ 0098$: \\r
+ SETB IE.7 \\r
+ 0099$: \\r
+ /* Finally pop off the ACC, which was the first register saved. */ \\r
+ pop ACC \\r
+ reti \\r
+ _endasm; \\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* \r
+ * See header file for description. \r
+ */\r
+portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
+{\r
+unsigned portLONG ulAddress;\r
+portSTACK_TYPE *pxStartOfStack;\r
+\r
+ /* Leave space to write the size of the stack as the first byte. */\r
+ pxStartOfStack = pxTopOfStack;\r
+ pxTopOfStack++;\r
+\r
+ /* Place a few bytes of known values on the bottom of the stack. \r
+ This is just useful for debugging and can be uncommented if required.\r
+ *pxTopOfStack = 0x11;\r
+ pxTopOfStack++;\r
+ *pxTopOfStack = 0x22;\r
+ pxTopOfStack++;\r
+ *pxTopOfStack = 0x33;\r
+ pxTopOfStack++;\r
+ */\r
+\r
+ /* Simulate how the stack would look after a call to the scheduler tick \r
+ ISR. \r
+\r
+ The return address that would have been pushed by the MCU. */\r
+ ulAddress = ( unsigned portLONG ) pxCode;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) ulAddress;\r
+ ulAddress >>= 8;\r
+ pxTopOfStack++;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) ( ulAddress );\r
+ pxTopOfStack++;\r
+\r
+ /* Next all the registers will have been pushed by portSAVE_CONTEXT(). */\r
+ *pxTopOfStack = 0xaa; /* acc */\r
+ pxTopOfStack++; \r
+\r
+ /* We want tasks to start with interrupts enabled. */\r
+ *pxTopOfStack = portGLOBAL_INTERRUPT_BIT;\r
+ pxTopOfStack++;\r
+\r
+ /* The function parameters will be passed in the DPTR and B register as\r
+ a three byte generic pointer is used. */\r
+ ulAddress = ( unsigned portLONG ) pvParameters;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) ulAddress; /* DPL */\r
+ ulAddress >>= 8;\r
+ *pxTopOfStack++;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) ulAddress; /* DPH */\r
+ ulAddress >>= 8;\r
+ pxTopOfStack++;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) ulAddress; /* b */\r
+ pxTopOfStack++;\r
+\r
+ /* The remaining registers are straight forward. */\r
+ *pxTopOfStack = 0x02; /* R2 */\r
+ pxTopOfStack++;\r
+ *pxTopOfStack = 0x03; /* R3 */\r
+ pxTopOfStack++;\r
+ *pxTopOfStack = 0x04; /* R4 */\r
+ pxTopOfStack++;\r
+ *pxTopOfStack = 0x05; /* R5 */\r
+ pxTopOfStack++;\r
+ *pxTopOfStack = 0x06; /* R6 */\r
+ pxTopOfStack++;\r
+ *pxTopOfStack = 0x07; /* R7 */\r
+ pxTopOfStack++;\r
+ *pxTopOfStack = 0x00; /* R0 */\r
+ pxTopOfStack++;\r
+ *pxTopOfStack = 0x01; /* R1 */\r
+ pxTopOfStack++;\r
+ *pxTopOfStack = 0x00; /* PSW */\r
+ pxTopOfStack++;\r
+ *pxTopOfStack = 0xbb; /* BP */\r
+\r
+ /* Dont increment the stack size here as we don't want to include\r
+ the stack size byte as part of the stack size count.\r
+\r
+ Finally we place the stack size at the beginning. */\r
+ *pxStartOfStack = ( portSTACK_TYPE ) ( pxTopOfStack - pxStartOfStack );\r
+\r
+ /* Unlike most ports, we return the start of the stack as this is where the\r
+ size of the stack is stored. */\r
+ return pxStartOfStack;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* \r
+ * See header file for description. \r
+ */\r
+portBASE_TYPE xPortStartScheduler( void )\r
+{\r
+ /* Setup timer 2 to generate the RTOS tick. */\r
+ prvSetupTimerInterrupt(); \r
+\r
+ /* Make sure we start with the expected SFR page. This line should not\r
+ really be required. */\r
+ SFRPAGE = 0;\r
+\r
+ /* Copy the stack for the first task to execute from XRAM into the stack,\r
+ restore the task context from the new stack, then start running the task. */\r
+ portCOPY_XRAM_TO_STACK();\r
+ portRESTORE_CONTEXT();\r
+\r
+ /* Should never get here! */\r
+ return pdTRUE;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEndScheduler( void )\r
+{\r
+ /* Not implemented for this port. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Manual context switch. The first thing we do is save the registers so we\r
+ * can use a naked attribute.\r
+ */\r
+void vPortYield( void ) _naked\r
+{\r
+ /* Save the execution context onto the stack, then copy the entire stack\r
+ to XRAM. This is necessary as the internal RAM is only large enough to\r
+ hold one stack, and we want one per task. \r
+ \r
+ PERFORMANCE COULD BE IMPROVED BY ONLY COPYING TO XRAM IF A TASK SWITCH\r
+ IS REQUIRED. */\r
+ portSAVE_CONTEXT();\r
+ portCOPY_STACK_TO_XRAM();\r
+\r
+ /* Call the standard scheduler context switch function. */\r
+ vTaskSwitchContext();\r
+\r
+ /* Copy the stack of the task about to execute from XRAM into RAM and\r
+ restore it's context ready to run on exiting. */\r
+ portCOPY_XRAM_TO_STACK();\r
+ portRESTORE_CONTEXT();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if configUSE_PREEMPTION == 1\r
+ void vTimer2ISR( void ) interrupt 5 _naked\r
+ {\r
+ /* Preemptive context switch function triggered by the timer 2 ISR.\r
+ This does the same as vPortYield() (see above) with the addition\r
+ of incrementing the RTOS tick count. */\r
+\r
+ portSAVE_CONTEXT();\r
+ portCOPY_STACK_TO_XRAM();\r
+\r
+ vTaskIncrementTick();\r
+ vTaskSwitchContext();\r
+ \r
+ portCLEAR_INTERRUPT_FLAG();\r
+ portCOPY_XRAM_TO_STACK();\r
+ portRESTORE_CONTEXT();\r
+ }\r
+#else\r
+ void vTimer2ISR( void ) interrupt 5\r
+ {\r
+ /* When using the cooperative scheduler the timer 2 ISR is only \r
+ required to increment the RTOS tick count. */\r
+\r
+ vTaskIncrementTick();\r
+ portCLEAR_INTERRUPT_FLAG();\r
+ }\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupTimerInterrupt( void )\r
+{\r
+unsigned portCHAR ucOriginalSFRPage;\r
+\r
+/* Constants calculated to give the required timer capture values. */\r
+const unsigned portLONG ulTicksPerSecond = configCPU_CLOCK_HZ / portCLOCK_DIVISOR;\r
+const unsigned portLONG ulCaptureTime = ulTicksPerSecond / configTICK_RATE_HZ;\r
+const unsigned portLONG ulCaptureValue = portMAX_TIMER_VALUE - ulCaptureTime;\r
+const unsigned portCHAR ucLowCaptureByte = ( unsigned portCHAR ) ( ulCaptureValue & ( unsigned portLONG ) 0xff );\r
+const unsigned portCHAR ucHighCaptureByte = ( unsigned portCHAR ) ( ulCaptureValue >> ( unsigned portLONG ) 8 );\r
+\r
+ /* NOTE: This uses a timer only present on 8052 architecture. */\r
+\r
+ /* Remember the current SFR page so we can restore it at the end of the\r
+ function. */\r
+ ucOriginalSFRPage = SFRPAGE;\r
+ SFRPAGE = 0;\r
+\r
+ /* TMR2CF can be left in its default state. */ \r
+ TMR2CF = ( unsigned portCHAR ) 0;\r
+\r
+ /* Setup the overflow reload value. */\r
+ RCAP2L = ucLowCaptureByte;\r
+ RCAP2H = ucHighCaptureByte;\r
+\r
+ /* The initial load is performed manually. */\r
+ TMR2L = ucLowCaptureByte;\r
+ TMR2H = ucHighCaptureByte;\r
+\r
+ /* Enable the timer 2 interrupts. */\r
+ IE |= portTIMER_2_INTERRUPT_ENABLE;\r
+\r
+ /* Interrupts are disabled when this is called so the timer can be started\r
+ here. */\r
+ TMR2CN = portENABLE_TIMER;\r
+\r
+ /* Restore the original SFR page. */\r
+ SFRPAGE = ucOriginalSFRPage;\r
+}\r
+\r
+\r
+\r
+\r
--- /dev/null
+/* \r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+#if configUSE_PREEMPTION == 0\r
+ void vTimer2ISR( void ) interrupt 5;\r
+#else\r
+ void vTimer2ISR( void ) interrupt 5 _naked;\r
+#endif\r
+\r
+void vSerialISR( void ) interrupt 4;\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ * Port specific definitions. \r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the\r
+ * given hardware and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *-----------------------------------------------------------\r
+ */\r
+\r
+/* Type definitions. */\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE float\r
+#define portLONG long\r
+#define portSHORT short\r
+#define portSTACK_TYPE unsigned portCHAR\r
+#define portBASE_TYPE char\r
+\r
+#if( configUSE_16_BIT_TICKS == 1 )\r
+ typedef unsigned portSHORT portTickType;\r
+ #define portMAX_DELAY ( portTickType ) 0xffff\r
+#else\r
+ typedef unsigned portLONG portTickType;\r
+ #define portMAX_DELAY ( portTickType ) 0xffffffff\r
+#endif\r
+/*-----------------------------------------------------------*/ \r
+\r
+/* Critical section management. */\r
+#define portENTER_CRITICAL() _asm \\r
+ push ACC \\r
+ push IE \\r
+ _endasm; \\r
+ EA = 0;\r
+\r
+#define portEXIT_CRITICAL() _asm \\r
+ pop ACC \\r
+ _endasm; \\r
+ ACC &= 0x80; \\r
+ IE |= ACC; \\r
+ _asm \\r
+ pop ACC \\r
+ _endasm;\r
+\r
+#define portDISABLE_INTERRUPTS() EA = 0;\r
+#define portENABLE_INTERRUPTS() EA = 1;\r
+/*-----------------------------------------------------------*/ \r
+\r
+/* Hardware specifics. */\r
+#define portBYTE_ALIGNMENT 1\r
+#define portSTACK_GROWTH ( 1 )\r
+#define portTICK_RATE_MS ( ( unsigned portLONG ) 1000 / configTICK_RATE_HZ ) \r
+/*-----------------------------------------------------------*/ \r
+\r
+/* Task utilities. */\r
+void vPortYield( void ) _naked;\r
+#define portYIELD() vPortYield();\r
+/*-----------------------------------------------------------*/ \r
+\r
+/* Compiler specifics. */\r
+#define inline\r
+#define portNOP() _asm \\r
+ nop \\r
+ _endasm;\r
+\r
+/*-----------------------------------------------------------*/ \r
+\r
+/* Task function macros as described on the FreeRTOS.org WEB site. */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+\r
+#endif /* PORTMACRO_H */\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* \r
+Changes from V3.0.0\r
+ + ISRcode is pulled inline and portTICKisr() is therefore\r
+ deleted from this file.\r
+\r
+ + Prescaler logic for Timer1 added to allow for a wider\r
+ range of TickRates.\r
+\r
+Changes from V3.0.1\r
+*/\r
+\r
+#include <FreeRTOS.h>\r
+#include <task.h>\r
+\r
+/* IO port constants. */\r
+#define portBIT_SET (1)\r
+#define portBIT_CLEAR (0)\r
+\r
+/* \r
+ * Hardware setup for the tick.\r
+ * We use a compare match on timer1. Depending on MPU-frequency\r
+ * and requested tickrate, a prescaled value with a matching\r
+ * prescaler are determined.\r
+ */\r
+#define portTIMER_COMPARE_BASE ((APROCFREQ/4)/configTICK_RATE_HZ)\r
+\r
+#if portTIMER_COMPARE_BASE < 0x10000\r
+ #define portTIMER_COMPARE_VALUE (portTIMER_COMPARE_BASE)\r
+ #define portTIMER_COMPARE_PS1 (portBIT_CLEAR)\r
+ #define portTIMER_COMPARE_PS0 (portBIT_CLEAR)\r
+#elif portTIMER_COMPARE_BASE < 0x20000\r
+ #define portTIMER_COMPARE_VALUE (portTIMER_COMPARE_BASE / 2)\r
+ #define portTIMER_COMPARE_PS1 (portBIT_CLEAR)\r
+ #define portTIMER_COMPARE_PS0 (portBIT_SET)\r
+#elif portTIMER_COMPARE_BASE < 0x40000\r
+ #define portTIMER_COMPARE_VALUE (portTIMER_COMPARE_BASE / 4)\r
+ #define portTIMER_COMPARE_PS1 (portBIT_SET)\r
+ #define portTIMER_COMPARE_PS0 (portBIT_CLEAR)\r
+#elif portTIMER_COMPARE_BASE < 0x80000\r
+ #define portTIMER_COMPARE_VALUE (portTIMER_COMPARE_BASE / 8)\r
+ #define portTIMER_COMPARE_PS1 (portBIT_SET)\r
+ #define portTIMER_COMPARE_PS0 (portBIT_SET)\r
+#else\r
+ #error "TickRate out of range"\r
+#endif\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Setup a timer for a regular tick.\r
+ */\r
+void portSetupTick( void )\r
+{\r
+ /*\r
+ * Interrupts are disabled when this function is called.\r
+ */\r
+\r
+ /*\r
+ * Setup CCP1\r
+ * Provide the tick interrupt using a compare match on timer1.\r
+ */\r
+\r
+ /*\r
+ * Set the compare match value.\r
+ */\r
+ CCPR1H = ( unsigned portCHAR ) ( ( portTIMER_COMPARE_VALUE >> 8 ) & 0xff );\r
+ CCPR1L = ( unsigned portCHAR ) ( portTIMER_COMPARE_VALUE & 0xff );\r
+\r
+ /*\r
+ * Set Compare Special Event Trigger Mode\r
+ */\r
+ bCCP1M3 = portBIT_SET;\r
+ bCCP1M2 = portBIT_CLEAR;\r
+ bCCP1M1 = portBIT_SET;\r
+ bCCP1M0 = portBIT_SET;\r
+\r
+ /*\r
+ * Enable CCP1 interrupt\r
+ */\r
+ bCCP1IE = portBIT_SET;\r
+\r
+ /*\r
+ * We are only going to use the global interrupt bit, so disable\r
+ * interruptpriorities and enable peripheral interrupts.\r
+ */\r
+ bIPEN = portBIT_CLEAR;\r
+ bPEIE = portBIT_SET;\r
+\r
+ /*\r
+ * Set up timer1\r
+ * It will produce the system tick.\r
+ */\r
+\r
+ /*\r
+ * Clear the time count\r
+ */\r
+ TMR1H = ( unsigned portCHAR ) 0x00;\r
+ TMR1L = ( unsigned portCHAR ) 0x00;\r
+\r
+ /*\r
+ * Setup the timer\r
+ */\r
+ bRD16 = portBIT_SET; // 16-bit\r
+ bT1CKPS1 = portTIMER_COMPARE_PS1; // prescaler\r
+ bT1CKPS0 = portTIMER_COMPARE_PS0; // prescaler\r
+ bT1OSCEN = portBIT_SET; // Oscillator enable\r
+ bT1SYNC = portBIT_SET; // No external clock sync\r
+ bTMR1CS = portBIT_CLEAR; // Internal clock\r
+ \r
+ bTMR1ON = portBIT_SET; // Start timer1\r
+}\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* \r
+Changes from V3.0.0\r
+ + ISRcode pulled inline to reduce stack-usage.\r
+\r
+ + Added functionality to only call vTaskSwitchContext() once\r
+ when handling multiple interruptsources in a single interruptcall.\r
+\r
+ + Filename changed to a .c extension to allow stepping through code\r
+ using F7.\r
+\r
+Changes from V3.0.1\r
+*/\r
+\r
+/*\r
+ * ISR for the tick.\r
+ * This increments the tick count and, if using the preemptive scheduler, \r
+ * performs a context switch. This must be identical to the manual \r
+ * context switch in how it stores the context of a task. \r
+ */\r
+\r
+#ifndef _FREERTOS_DRIVERS_TICK_ISRTICK_C\r
+#define _FREERTOS_DRIVERS_TICK_ISRTICK_C\r
+\r
+{\r
+ /*\r
+ * Was the interrupt the SystemClock?\r
+ */\r
+ if( bCCP1IF && bCCP1IE )\r
+ {\r
+ /*\r
+ * Reset the interrupt flag\r
+ */\r
+ bCCP1IF = 0;\r
+ \r
+ /*\r
+ * Maintain the tick count.\r
+ */\r
+ vTaskIncrementTick();\r
+ \r
+ #if configUSE_PREEMPTION == 1\r
+ {\r
+ /*\r
+ * Ask for a switch to the highest priority task\r
+ * that is ready to run.\r
+ */\r
+ uxSwitchRequested = pdTRUE;\r
+ }\r
+ #endif\r
+ }\r
+}\r
+\r
+#pragma wizcpp uselib "$__PATHNAME__/Tick.c"\r
+\r
+#endif /* _FREERTOS_DRIVERS_TICK_ISRTICK_C */\r
--- /dev/null
+@echo off\r
+cls\r
+\r
+SET PACKAGENAME=the FreeRTOS port for fedC and wizC\r
+\r
+echo.\r
+echo Hello, I'm the installationscript for %PACKAGENAME%.\r
+echo.\r
+\r
+:CHECKFEDC\r
+ set FED=C:\Program Files\FED\PIC_C\r
+ echo.\r
+ echo I'm checking your system for fedC\r
+ if not exist "%FED%" goto NOFEDC\r
+ echo YES, I found a fedC-installation!\r
+ goto FOUNDFED\r
+:NOFEDC\r
+ echo I could not find a fedC-installation.\r
+\r
+\r
+:CHECKWIZC\r
+ set FED=C:\Program Files\FED\PIXIE\r
+ echo.\r
+ echo I'm checking your system for wizC\r
+ if not exist "%FED%" goto NOWIZC\r
+ echo YES, I found a wizC-installation!\r
+ goto FOUNDFED\r
+:noWIZC\r
+ echo I could not find a wizC-installation.\r
+\r
+\r
+:ERROR\r
+ echo.\r
+ echo.\r
+ echo I could not find a FED C-compiler installation on your system.\r
+ echo.\r
+ echo Perhaps I got confused because you installed fedC or wizC in a non-default directory.\r
+ echo If this is the case, please change the path at the top of this install-script.\r
+ echo After that rerun the script and I will be happy to try again.\r
+ echo.\r
+ goto ENDIT\r
+\r
+\r
+:FOUNDFED\r
+ echo.\r
+ echo.\r
+\r
+ set FEDLIBS=%FED%\Libs\r
+ set FEDLIBSUSER=%FEDLIBS%\LibsUser\r
+\r
+ if exist "%FEDLIBS%" goto INSTALL\r
+ echo The FED installationdirectory "%FED%"\r
+ echo contains no Libs subdirectory. This is weird!\r
+ echo.\r
+ echo Installation is aborted, sorry...\r
+ goto ENDIT\r
+\r
+\r
+:INSTALL\r
+ echo I am about to install %PACKAGENAME%\r
+ echo into directory %FEDLIBSUSER%\r
+ echo.\r
+ echo Press 'enter' to let me do my thing\r
+ echo Press 'ctrl-c' to stop me\r
+ pause >nul\r
+ echo.\r
+ echo Installing...\r
+\r
+\r
+:RESET_READONLY\r
+ echo.\r
+ echo Removing ReadOnly attributes\r
+ attrib -R "%FEDLIBSUSER%\libFreeRTOS\Modules\Port.c" >nul\r
+ attrib -R "%FEDLIBSUSER%\libFreeRTOS\Modules\List.c" >nul\r
+ attrib -R "%FEDLIBSUSER%\libFreeRTOS\Modules\Queue.c" >nul\r
+ attrib -R "%FEDLIBSUSER%\libFreeRTOS\Modules\Tasks.c" >nul\r
+ attrib -R "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick\Tick.c" >nul\r
+ attrib -R "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick\isrTick.c" >nul\r
+ attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Portmacro.h" >nul\r
+ attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\List.h" >nul\r
+ attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Portable.h" >nul\r
+ attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Projdefs.h" >nul\r
+ attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Queue.h" >nul\r
+ attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Semphr.h" >nul\r
+ attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Task.h" >nul\r
+ attrib -R "%FEDLIBSUSER%\FreeRTOS.h" >nul\r
+ echo Done\r
+\r
+:CREATE_DIRECTORIES\r
+ echo.\r
+ echo Creating directories (if necessary)...\r
+ if not exist "%FEDLIBSUSER%" mkdir "%FEDLIBSUSER%"\r
+ if not exist "%FEDLIBSUSER%\libFreeRTOS" mkdir "%FEDLIBSUSER%\libFreeRTOS"\r
+ if not exist "%FEDLIBSUSER%\libFreeRTOS\Drivers" mkdir "%FEDLIBSUSER%\libFreeRTOS\Drivers"\r
+ if not exist "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick" mkdir "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick"\r
+ if not exist "%FEDLIBSUSER%\libFreeRTOS\Include" mkdir "%FEDLIBSUSER%\libFreeRTOS\Include"\r
+ if not exist "%FEDLIBSUSER%\libFreeRTOS\Modules" mkdir "%FEDLIBSUSER%\libFreeRTOS\Modules"\r
+ echo Done\r
+\r
+\r
+ echo.\r
+ echo Copying Files...\r
+:COPY_MODULES\r
+ echo Modules...\r
+ copy /V /Y "Port.c" "%FEDLIBSUSER%\libFreeRTOS\Modules\Port.c" >nul\r
+ copy /V /Y "..\..\..\List.c" "%FEDLIBSUSER%\libFreeRTOS\Modules\List.c" >nul\r
+ copy /V /Y "..\..\..\Queue.c" "%FEDLIBSUSER%\libFreeRTOS\Modules\Queue.c" >nul\r
+ copy /V /Y "..\..\..\Tasks.c" "%FEDLIBSUSER%\libFreeRTOS\Modules\Tasks.c" >nul\r
+\r
+:COPY_DRIVERS\r
+ echo Drivers...\r
+ copy /V /Y "Drivers\Tick\Tick.c" "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick\Tick.c" >nul\r
+ copy /V /Y "Drivers\Tick\isrTick.c" "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick\isrTick.c" >nul\r
+\r
+:COPY_HEADERS\r
+ echo Headers...\r
+ copy /V /Y "portmacro.h" "%FEDLIBSUSER%\libFreeRTOS\Include\Portmacro.h" >nul\r
+ copy /V /Y "..\..\..\include\List.h" "%FEDLIBSUSER%\libFreeRTOS\Include\List.h" >nul\r
+ copy /V /Y "..\..\..\include\Portable.h" "%FEDLIBSUSER%\libFreeRTOS\Include\Portable.h" >nul\r
+ copy /V /Y "..\..\..\include\Projdefs.h" "%FEDLIBSUSER%\libFreeRTOS\Include\Projdefs.h" >nul\r
+ copy /V /Y "..\..\..\include\Queue.h" "%FEDLIBSUSER%\libFreeRTOS\Include\Queue.h" >nul\r
+ copy /V /Y "..\..\..\include\Semphr.h" "%FEDLIBSUSER%\libFreeRTOS\Include\Semphr.h" >nul\r
+ copy /V /Y "..\..\..\include\Task.h" "%FEDLIBSUSER%\libFreeRTOS\Include\Task.h" >nul\r
+ copy /V /Y "addFreeRTOS.h" + "..\..\..\include\FreeRTOS.h" "%FEDLIBSUSER%\FreeRTOS.h" >nul\r
+\r
+\r
+ echo Done\r
+\r
+\r
+:SET_READONLY\r
+ echo.\r
+ echo Setting files to ReadOnly\r
+ attrib +R "%FEDLIBSUSER%\libFreeRTOS\Modules\Port.c" >nul\r
+ attrib +R "%FEDLIBSUSER%\libFreeRTOS\Modules\List.c" >nul\r
+ attrib +R "%FEDLIBSUSER%\libFreeRTOS\Modules\Queue.c" >nul\r
+ attrib +R "%FEDLIBSUSER%\libFreeRTOS\Modules\Tasks.c" >nul\r
+ attrib +R "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick\Tick.c" >nul\r
+ attrib +R "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick\isrTick.c" >nul\r
+ attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Portmacro.h" >nul\r
+ attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\List.h" >nul\r
+ attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Portable.h" >nul\r
+ attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Projdefs.h" >nul\r
+ attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Queue.h" >nul\r
+ attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Semphr.h" >nul\r
+ attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Task.h" >nul\r
+ attrib +R "%FEDLIBSUSER%\FreeRTOS.h" >nul\r
+ echo Done\r
+\r
+\r
+:FINISHED\r
+ echo.\r
+ echo The installation of %PACKAGENAME% is completed.\r
+ echo.\r
+ echo Please review the installation instructions as additional libraries and\r
+ echo fedC/wizC configuration settings are needed for FreeRTOS to function correctly.\r
+\r
+ goto ENDIT\r
+\r
+\r
+:ENDIT\r
+ echo.\r
+ echo.\r
+ echo Press 'enter' to close this window\r
+ pause >nul
\ No newline at end of file
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+Changes from V3.0.0\r
+\r
+Changes from V3.0.1\r
+*/\r
+\r
+/*\r
+ * The installation script will automatically prepend this file to the default FreeRTOS.h.\r
+ */\r
+\r
+#ifndef WIZC_FREERTOS_H\r
+#define WIZC_FREERTOS_H\r
+\r
+#pragma noheap\r
+#pragma wizcpp expandnl on\r
+#pragma wizcpp searchpath "$__PATHNAME__/libFreeRTOS/Include/"\r
+#pragma wizcpp uselib "$__PATHNAME__/libFreeRTOS/Modules/tasks.c"\r
+#pragma wizcpp uselib "$__PATHNAME__/libFreeRTOS/Modules/queue.c"\r
+#pragma wizcpp uselib "$__PATHNAME__/libFreeRTOS/Modules/list.c"\r
+#pragma wizcpp uselib "$__PATHNAME__/libFreeRTOS/Modules/port.c"\r
+\r
+#endif /* WIZC_FREERTOS_H */\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+Changes from V3.2.1\r
+ + CallReturn Depth increased from 8 to 10 levels to accomodate wizC/fedC V12.\r
+ \r
+Changes from V3.2.0\r
+ + TBLPTRU is now initialised to zero during the initial stack creation of a new task. This solves\r
+ an error on devices with more than 64kB ROM.\r
+\r
+Changes from V3.0.0\r
+ + ucCriticalNesting is now initialised to 0x7F to prevent interrupts from being\r
+ handled before the scheduler is started.\r
+\r
+Changes from V3.0.1\r
+*/\r
+\r
+/* Scheduler include files. */\r
+#include <FreeRTOS.h>\r
+#include <task.h>\r
+\r
+#include <malloc.h>\r
+\r
+/*---------------------------------------------------------------------------\r
+ * Implementation of functions defined in portable.h for the WizC PIC18 port.\r
+ *---------------------------------------------------------------------------*/\r
+\r
+/*\r
+ * We require the address of the pxCurrentTCB variable, but don't want to\r
+ * know any details of its type.\r
+ */\r
+typedef void tskTCB;\r
+extern volatile tskTCB * volatile pxCurrentTCB;\r
+\r
+/*\r
+ * Define minimal-stack constants\r
+ * -----\r
+ * FSR's:\r
+ * STATUS, WREG, BSR, PRODH, PRODL, FSR0H, FSR0L,\r
+ * FSR1H, FSR1L,TABLAT, (TBLPTRU), TBLPTRH, TBLPTRL,\r
+ * (PCLATU), PCLATH\r
+ * sfr's within parenthesis only on devices > 64kB\r
+ * -----\r
+ * Call/Return stack:\r
+ * 2 bytes per entry on devices <= 64kB\r
+ * 3 bytes per entry on devices > 64kB\r
+ * -----\r
+ * Other bytes:\r
+ * 2 bytes: FunctionParameter for initial taskcode\r
+ * 1 byte : Number of entries on call/return stack\r
+ * 1 byte : ucCriticalNesting\r
+ * 16 bytes: Free space on stack\r
+ */\r
+#if _ROMSIZE > 0x8000\r
+ #define portSTACK_FSR_BYTES ( 15 )\r
+ #define portSTACK_CALLRETURN_ENTRY_SIZE ( 3 )\r
+#else\r
+ #define portSTACK_FSR_BYTES ( 13 )\r
+ #define portSTACK_CALLRETURN_ENTRY_SIZE ( 2 )\r
+#endif\r
+\r
+#define portSTACK_MINIMAL_CALLRETURN_DEPTH ( 10 )\r
+#define portSTACK_OTHER_BYTES ( 20 )\r
+\r
+unsigned portSHORT usCalcMinStackSize = 0;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * We initialise ucCriticalNesting to the middle value an \r
+ * unsigned char can contain. This way portENTER_CRITICAL()\r
+ * and portEXIT_CRITICAL() can be called without interrupts\r
+ * being enabled before the scheduler starts.\r
+ */\r
+register unsigned portCHAR ucCriticalNesting = 0x7F;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* \r
+ * Initialise the stack of a new task.\r
+ * See portSAVE_CONTEXT macro for description. \r
+ */\r
+portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
+{\r
+unsigned portCHAR ucScratch;\r
+ /*\r
+ * Get the size of the RAMarea in page 0 used by the compiler\r
+ * We do this here already to avoid W-register conflicts.\r
+ */\r
+ _Pragma("asm")\r
+ movlw OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE\r
+ movwf PRODL,ACCESS ; PRODL is used as temp register\r
+ _Pragma("asmend")\r
+ ucScratch = PRODL;\r
+\r
+ /*\r
+ * Place a few bytes of known values on the bottom of the stack. \r
+ * This is just useful for debugging.\r
+ */\r
+// *pxTopOfStack-- = 0x11;\r
+// *pxTopOfStack-- = 0x22;\r
+// *pxTopOfStack-- = 0x33;\r
+\r
+ /*\r
+ * Simulate how the stack would look after a call to vPortYield()\r
+ * generated by the compiler.\r
+ */\r
+\r
+ /*\r
+ * First store the function parameters. This is where the task expects\r
+ * to find them when it starts running.\r
+ */\r
+ *pxTopOfStack-- = ( portSTACK_TYPE ) ( (( unsigned portSHORT ) pvParameters >> 8) & 0x00ff );\r
+ *pxTopOfStack-- = ( portSTACK_TYPE ) ( ( unsigned portSHORT ) pvParameters & 0x00ff );\r
+\r
+ /*\r
+ * Next are all the registers that form part of the task context.\r
+ */\r
+ *pxTopOfStack-- = ( portSTACK_TYPE ) 0x11; /* STATUS. */\r
+ *pxTopOfStack-- = ( portSTACK_TYPE ) 0x22; /* WREG. */\r
+ *pxTopOfStack-- = ( portSTACK_TYPE ) 0x33; /* BSR. */\r
+ *pxTopOfStack-- = ( portSTACK_TYPE ) 0x44; /* PRODH. */\r
+ *pxTopOfStack-- = ( portSTACK_TYPE ) 0x55; /* PRODL. */\r
+ *pxTopOfStack-- = ( portSTACK_TYPE ) 0x66; /* FSR0H. */\r
+ *pxTopOfStack-- = ( portSTACK_TYPE ) 0x77; /* FSR0L. */\r
+ *pxTopOfStack-- = ( portSTACK_TYPE ) 0x88; /* FSR1H. */\r
+ *pxTopOfStack-- = ( portSTACK_TYPE ) 0x99; /* FSR1L. */\r
+ *pxTopOfStack-- = ( portSTACK_TYPE ) 0xAA; /* TABLAT. */\r
+#if _ROMSIZE > 0x8000\r
+ *pxTopOfStack-- = ( portSTACK_TYPE ) 0x00; /* TBLPTRU. */\r
+#endif\r
+ *pxTopOfStack-- = ( portSTACK_TYPE ) 0xCC; /* TBLPTRH. */\r
+ *pxTopOfStack-- = ( portSTACK_TYPE ) 0xDD; /* TBLPTRL. */\r
+#if _ROMSIZE > 0x8000\r
+ *pxTopOfStack-- = ( portSTACK_TYPE ) 0xEE; /* PCLATU. */\r
+#endif\r
+ *pxTopOfStack-- = ( portSTACK_TYPE ) 0xFF; /* PCLATH. */\r
+\r
+ /*\r
+ * Next the compiler's scratchspace.\r
+ */\r
+ while(ucScratch-- > 0)\r
+ {\r
+ *pxTopOfStack-- = ( portSTACK_TYPE ) 0;\r
+ }\r
+ \r
+ /*\r
+ * The only function return address so far is the address of the task entry.\r
+ * The order is TOSU/TOSH/TOSL. For devices > 64kB, TOSU is put on the \r
+ * stack, too. TOSU is always written as zero here because wizC does not allow\r
+ * functionpointers to point above 64kB in ROM.\r
+ */\r
+#if _ROMSIZE > 0x8000\r
+ *pxTopOfStack-- = ( portSTACK_TYPE ) 0;\r
+#endif\r
+ *pxTopOfStack-- = ( portSTACK_TYPE ) ( ( ( unsigned portSHORT ) pxCode >> 8 ) & 0x00ff );\r
+ *pxTopOfStack-- = ( portSTACK_TYPE ) ( ( unsigned portSHORT ) pxCode & 0x00ff );\r
+\r
+ /*\r
+ * Store the number of return addresses on the hardware stack.\r
+ * So far only the address of the task entry point.\r
+ */\r
+ *pxTopOfStack-- = ( portSTACK_TYPE ) 1;\r
+\r
+ /*\r
+ * The code generated by wizC does not maintain separate\r
+ * stack and frame pointers. Therefore the portENTER_CRITICAL macro cannot \r
+ * use the stack as per other ports. Instead a variable is used to keep\r
+ * track of the critical section nesting. This variable has to be stored\r
+ * as part of the task context and is initially set to zero.\r
+ */\r
+ *pxTopOfStack-- = ( portSTACK_TYPE ) portNO_CRITICAL_SECTION_NESTING; \r
+\r
+ return pxTopOfStack;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+unsigned portSHORT usPortCALCULATE_MINIMAL_STACK_SIZE( void )\r
+{\r
+ /*\r
+ * Fetch the size of compiler's scratchspace.\r
+ */\r
+ _Pragma("asm")\r
+ movlw OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE\r
+ movlb usCalcMinStackSize>>8\r
+ movwf usCalcMinStackSize,BANKED\r
+ _Pragma("asmend")\r
+\r
+ /*\r
+ * Add minimum needed stackspace\r
+ */\r
+ usCalcMinStackSize += ( portSTACK_FSR_BYTES )\r
+ + ( portSTACK_MINIMAL_CALLRETURN_DEPTH * portSTACK_CALLRETURN_ENTRY_SIZE )\r
+ + ( portSTACK_OTHER_BYTES );\r
+\r
+ return(usCalcMinStackSize);\r
+}\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+portBASE_TYPE xPortStartScheduler( void )\r
+{\r
+ extern void portSetupTick( void );\r
+\r
+ /*\r
+ * Setup a timer for the tick ISR for the preemptive scheduler.\r
+ */\r
+ portSetupTick(); \r
+\r
+ /*\r
+ * Restore the context of the first task to run.\r
+ */\r
+ portRESTORE_CONTEXT();\r
+\r
+ /*\r
+ * This point should never be reached during execution.\r
+ */\r
+ return pdTRUE;\r
+}\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEndScheduler( void )\r
+{\r
+ /*\r
+ * It is unlikely that the scheduler for the PIC port will get stopped\r
+ * once running. When called a reset is done which is probably the\r
+ * most valid action.\r
+ */\r
+ _Pragma(asmline reset);\r
+}\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Manual context switch. This is similar to the tick context switch,\r
+ * but does not increment the tick count. It must be identical to the\r
+ * tick context switch in how it stores the stack of a task.\r
+ */\r
+void vPortYield( void )\r
+{\r
+ /*\r
+ * Save the context of the current task.\r
+ */\r
+ portSAVE_CONTEXT( portINTERRUPTS_UNCHANGED );\r
+\r
+ /*\r
+ * Switch to the highest priority task that is ready to run.\r
+ */\r
+ vTaskSwitchContext();\r
+\r
+ /*\r
+ * Start executing the task we have just switched to.\r
+ */\r
+ portRESTORE_CONTEXT();\r
+}\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void *pvPortMalloc( unsigned portSHORT usWantedSize )\r
+{\r
+void *pvReturn;\r
+\r
+ vTaskSuspendAll();\r
+ {\r
+ pvReturn = malloc( ( malloc_t ) usWantedSize );\r
+ }\r
+ xTaskResumeAll();\r
+\r
+ return pvReturn;\r
+}\r
+\r
+void vPortFree( void *pv )\r
+{\r
+ if( pv )\r
+ {\r
+ vTaskSuspendAll();\r
+ {\r
+ free( pv );\r
+ }\r
+ xTaskResumeAll();\r
+ }\r
+}\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* \r
+Changes from V3.0.0\r
+\r
+Changes from V3.0.1\r
+*/\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+#if !defined(_SERIES) || _SERIES != 18\r
+ #error "WizC supports FreeRTOS on the Microchip PIC18-series only"\r
+#endif\r
+\r
+#if !defined(QUICKCALL) || QUICKCALL != 1\r
+ #error "QuickCall must be enabled (see ProjectOptions/Optimisations)"\r
+#endif\r
+\r
+#include <stddef.h>\r
+#include <pic.h>\r
+\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE portFLOAT\r
+#define portLONG long\r
+#define portSHORT short\r
+#define portSTACK_TYPE unsigned char\r
+#define portBASE_TYPE char\r
+\r
+#if( configUSE_16_BIT_TICKS == 1 )\r
+ typedef unsigned portSHORT portTickType;\r
+ #define portMAX_DELAY ( portTickType ) ( 0xFFFF )\r
+#else\r
+ typedef unsigned portLONG portTickType;\r
+ #define portMAX_DELAY ( portTickType ) ( 0xFFFFFFFF )\r
+#endif\r
+\r
+#define portBYTE_ALIGNMENT 1\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Constant used for context switch macro when we require the interrupt \r
+ * enable state to be forced when the interrupted task is switched back in.\r
+ */\r
+#define portINTERRUPTS_FORCED (0x01)\r
+\r
+/*\r
+ * Constant used for context switch macro when we require the interrupt \r
+ * enable state to be unchanged when the interrupted task is switched back in.\r
+ */\r
+#define portINTERRUPTS_UNCHANGED (0x00)\r
+\r
+/* Initial interrupt enable state for newly created tasks. This value is\r
+ * used when a task switches in for the first time.\r
+ */\r
+#define portINTERRUPTS_INITIAL_STATE (portINTERRUPTS_FORCED)\r
+\r
+/*\r
+ * Macros to modify the global interrupt enable bit in INTCON.\r
+ */\r
+#define portDISABLE_INTERRUPTS() \\r
+ do \\r
+ { \\r
+ bGIE=0; \\r
+ } while(bGIE) // MicroChip recommends this check!\r
+ \r
+#define portENABLE_INTERRUPTS() \\r
+ do \\r
+ { \\r
+ bGIE=1; \\r
+ } while(0)\r
+\r
+/*-----------------------------------------------------------*/ \r
+\r
+/*\r
+ * Critical section macros.\r
+ */\r
+extern unsigned portCHAR ucCriticalNesting;\r
+\r
+#define portNO_CRITICAL_SECTION_NESTING ( ( unsigned portCHAR ) 0 )\r
+\r
+#define portENTER_CRITICAL() \\r
+ do \\r
+ { \\r
+ portDISABLE_INTERRUPTS(); \\r
+ \\r
+ /* \\r
+ * Now interrupts are disabled ucCriticalNesting \\r
+ * can be accessed directly. Increment \\r
+ * ucCriticalNesting to keep a count of how \\r
+ * many times portENTER_CRITICAL() has been called. \\r
+ */ \\r
+ ucCriticalNesting++; \\r
+ } while(0)\r
+\r
+#define portEXIT_CRITICAL() \\r
+ do \\r
+ { \\r
+ if(ucCriticalNesting > portNO_CRITICAL_SECTION_NESTING) \\r
+ { \\r
+ /* \\r
+ * Decrement the nesting count as we are leaving a \\r
+ * critical section. \\r
+ */ \\r
+ ucCriticalNesting--; \\r
+ } \\r
+ \\r
+ /* \\r
+ * If the nesting level has reached zero then \\r
+ * interrupts should be re-enabled. \\r
+ */ \\r
+ if( ucCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \\r
+ { \\r
+ portENABLE_INTERRUPTS(); \\r
+ } \\r
+ } while(0)\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The minimal stacksize is calculated on the first reference of\r
+ * portMINIMAL_STACK_SIZE. Some input to this calculation is\r
+ * compiletime determined, other input is port-defined (see port.c)\r
+ */\r
+extern unsigned portSHORT usPortCALCULATE_MINIMAL_STACK_SIZE( void );\r
+extern unsigned portSHORT usCalcMinStackSize;\r
+\r
+#define portMINIMAL_STACK_SIZE \\r
+ ((usCalcMinStackSize == 0) \\r
+ ? usPortCALCULATE_MINIMAL_STACK_SIZE() \\r
+ : usCalcMinStackSize )\r
+\r
+/*\r
+ * WizC uses a downgrowing stack\r
+ */\r
+#define portSTACK_GROWTH ( -1 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Macro's that pushes all the registers that make up the context of a task onto\r
+ * the stack, then saves the new top of stack into the TCB. TOSU and TBLPTRU\r
+ * are only saved/restored on devices with more than 64kB (32k Words) ROM.\r
+ * \r
+ * The stackpointer is helt by WizC in FSR2 and points to the first free byte.\r
+ * WizC uses a "downgrowing" stack. There is no framepointer.\r
+ *\r
+ * We keep track of the interruptstatus using ucCriticalNesting. When this\r
+ * value equals zero, interrupts have to be enabled upon exit from the\r
+ * portRESTORE_CONTEXT macro.\r
+ * \r
+ * If this is called from an ISR then the interrupt enable bits must have been \r
+ * set for the ISR to ever get called. Therefore we want to save\r
+ * ucCriticalNesting with value zero. This means the interrupts will again be\r
+ * re-enabled when the interrupted task is switched back in.\r
+ *\r
+ * If this is called from a manual context switch (i.e. from a call to yield),\r
+ * then we want to keep the current value of ucCritialNesting so it is restored\r
+ * with its current value. This allows a yield from within a critical section.\r
+ *\r
+ * The compiler uses some locations at the bottom of RAM for temporary\r
+ * storage. The compiler may also have been instructed to optimize\r
+ * function-parameters and local variables to global storage. The compiler\r
+ * uses an area called LocOpt for this wizC feature.\r
+ * The total overheadstorage has to be saved in it's entirety as part of\r
+ * a task context. These macro's store/restore from data address 0x0000 to\r
+ * (OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE - 1).\r
+ * OVERHEADPAGE0, LOCOPTSIZE and MAXLOCOPTSIZE are compiler-generated\r
+ * assembler definitions.\r
+ */\r
+\r
+#define portSAVE_CONTEXT( ucInterruptForced ) \\r
+ do \\r
+ { \\r
+ portDISABLE_INTERRUPTS(); \\r
+ \\r
+ _Pragma("asm") \\r
+ ; \\r
+ ; Push the relevant SFR's onto the task's stack \\r
+ ; \\r
+ movff STATUS,POSTDEC2 \\r
+ movff WREG,POSTDEC2 \\r
+ movff BSR,POSTDEC2 \\r
+ movff PRODH,POSTDEC2 \\r
+ movff PRODL,POSTDEC2 \\r
+ movff FSR0H,POSTDEC2 \\r
+ movff FSR0L,POSTDEC2 \\r
+ movff FSR1H,POSTDEC2 \\r
+ movff FSR1L,POSTDEC2 \\r
+ movff TABLAT,POSTDEC2 \\r
+ if __ROMSIZE > 0x8000 \\r
+ movff TBLPTRU,POSTDEC2 \\r
+ endif \\r
+ movff TBLPTRH,POSTDEC2 \\r
+ movff TBLPTRL,POSTDEC2 \\r
+ if __ROMSIZE > 0x8000 \\r
+ movff PCLATU,POSTDEC2 \\r
+ endif \\r
+ movff PCLATH,POSTDEC2 \\r
+ ; \\r
+ ; Store the compiler-scratch-area as described above. \\r
+ ; \\r
+ movlw OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE \\r
+ clrf FSR0L,ACCESS \\r
+ clrf FSR0H,ACCESS \\r
+ _rtos_S1: \\r
+ movff POSTINC0,POSTDEC2 \\r
+ decfsz WREG,W,ACCESS \\r
+ SMARTJUMP _rtos_S1 \\r
+ ; \\r
+ ; Save the pic call/return-stack belonging to the \\r
+ ; current task by copying it to the task's software- \\r
+ ; stack. We save the hardware stack pointer (which \\r
+ ; is the number of addresses on the stack) in the \\r
+ ; W-register first because we need it later and it \\r
+ ; is modified in the save-loop by executing pop's. \\r
+ ; After the loop the W-register is stored on the \\r
+ ; stack, too. \\r
+ ; \\r
+ movf STKPTR,W,ACCESS \\r
+ bz _rtos_s3 \\r
+ _rtos_S2: \\r
+ if __ROMSIZE > 0x8000 \\r
+ movff TOSU,POSTDEC2 \\r
+ endif \\r
+ movff TOSH,POSTDEC2 \\r
+ movff TOSL,POSTDEC2 \\r
+ pop \\r
+ tstfsz STKPTR,ACCESS \\r
+ SMARTJUMP _rtos_S2 \\r
+ _rtos_s3: \\r
+ movwf POSTDEC2,ACCESS \\r
+ ; \\r
+ ; Next the value for ucCriticalNesting used by the \\r
+ ; task is stored on the stack. When \\r
+ ; (ucInterruptForced == portINTERRUPTS_FORCED), we save \\r
+ ; it as 0 (portNO_CRITICAL_SECTION_NESTING). \\r
+ ; \\r
+ if ucInterruptForced == portINTERRUPTS_FORCED \\r
+ clrf POSTDEC2,ACCESS \\r
+ else \\r
+ movff ucCriticalNesting,POSTDEC2 \\r
+ endif \\r
+ ; \\r
+ ; Save the new top of the software stack in the TCB. \\r
+ ; \\r
+ movff pxCurrentTCB,FSR0L \\r
+ movff pxCurrentTCB+1,FSR0H \\r
+ movff FSR2L,POSTINC0 \\r
+ movff FSR2H,POSTINC0 \\r
+ _Pragma("asmend") \\r
+ } while(0)\r
+\r
+/************************************************************/\r
+\r
+/*\r
+ * This is the reverse of portSAVE_CONTEXT.\r
+ */\r
+#define portRESTORE_CONTEXT() \\r
+ do \\r
+ { \\r
+ _Pragma("asm") \\r
+ ; \\r
+ ; Set FSR0 to point to pxCurrentTCB->pxTopOfStack. \\r
+ ; \\r
+ movff pxCurrentTCB,FSR0L \\r
+ movff pxCurrentTCB+1,FSR0H \\r
+ ; \\r
+ ; De-reference FSR0 to set the address it holds into \\r
+ ; FSR2 (i.e. *( pxCurrentTCB->pxTopOfStack ) ). FSR2 \\r
+ ; is used by wizC as stackpointer. \\r
+ ; \\r
+ movff POSTINC0,FSR2L \\r
+ movff POSTINC0,FSR2H \\r
+ ; \\r
+ ; Next, the value for ucCriticalNesting used by the \\r
+ ; task is retrieved from the stack. \\r
+ ; \\r
+ movff PREINC2,ucCriticalNesting \\r
+ ; \\r
+ ; Rebuild the pic call/return-stack. The number of \\r
+ ; return addresses is the next item on the task stack. \\r
+ ; Save this number in PRODL. Then fetch the addresses \\r
+ ; and store them on the hardwarestack. \\r
+ ; The datasheets say we can't use movff here... \\r
+ ; \\r
+ movff PREINC2,PRODL // Use PRODL as tempregister \\r
+ clrf STKPTR,ACCESS \\r
+ _rtos_R1: \\r
+ push \\r
+ movf PREINC2,W,ACCESS \\r
+ movwf TOSL,ACCESS \\r
+ movf PREINC2,W,ACCESS \\r
+ movwf TOSH,ACCESS \\r
+ if __ROMSIZE > 0x8000 \\r
+ movf PREINC2,W,ACCESS \\r
+ movwf TOSU,ACCESS \\r
+ else \\r
+ clrf TOSU,ACCESS \\r
+ endif \\r
+ decfsz PRODL,F,ACCESS \\r
+ SMARTJUMP _rtos_R1 \\r
+ ; \\r
+ ; Restore the compiler's working storage area to page 0 \\r
+ ; \\r
+ movlw OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE \\r
+ movwf FSR0L,ACCESS \\r
+ clrf FSR0H,ACCESS \\r
+ _rtos_R2: \\r
+ decf FSR0L,F,ACCESS \\r
+ movff PREINC2,INDF0 \\r
+ tstfsz FSR0L,ACCESS \\r
+ SMARTJUMP _rtos_R2 \\r
+ ; \\r
+ ; Restore the sfr's forming the tasks context. \\r
+ ; We cannot yet restore bsr, w and status because \\r
+ ; we need these registers for a final test. \\r
+ ; \\r
+ movff PREINC2,PCLATH \\r
+ if __ROMSIZE > 0x8000 \\r
+ movff PREINC2,PCLATU \\r
+ else \\r
+ clrf PCLATU,ACCESS \\r
+ endif \\r
+ movff PREINC2,TBLPTRL \\r
+ movff PREINC2,TBLPTRH \\r
+ if __ROMSIZE > 0x8000 \\r
+ movff PREINC2,TBLPTRU \\r
+ else \\r
+ clrf TBLPTRU,ACCESS \\r
+ endif \\r
+ movff PREINC2,TABLAT \\r
+ movff PREINC2,FSR1L \\r
+ movff PREINC2,FSR1H \\r
+ movff PREINC2,FSR0L \\r
+ movff PREINC2,FSR0H \\r
+ movff PREINC2,PRODL \\r
+ movff PREINC2,PRODH \\r
+ ; \\r
+ ; The return from portRESTORE_CONTEXT() depends on \\r
+ ; the value of ucCriticalNesting. When it is zero, \\r
+ ; interrupts need to be enabled. This is done via a \\r
+ ; retfie instruction because we need the \\r
+ ; interrupt-enabling and the return to the restored \\r
+ ; task to be uninterruptable. \\r
+ ; Because bsr, status and W are affected by the test \\r
+ ; they are restored after the test. \\r
+ ; \\r
+ movlb ucCriticalNesting>>8 \\r
+ tstfsz ucCriticalNesting,BANKED \\r
+ SMARTJUMP _rtos_R4 \\r
+ _rtos_R3: \\r
+ movff PREINC2,BSR \\r
+ movff PREINC2,WREG \\r
+ movff PREINC2,STATUS \\r
+ retfie 0 ; Return enabling interrupts \\r
+ _rtos_R4: \\r
+ movff PREINC2,BSR \\r
+ movff PREINC2,WREG \\r
+ movff PREINC2,STATUS \\r
+ return 0 ; Return without affecting interrupts \\r
+ _Pragma("asmend") \\r
+ } while(0)\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) \r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+extern void vPortYield( void );\r
+#define portYIELD() vPortYield()\r
+\r
+#define portNOP() _Pragma("asm") \\r
+ nop \\r
+ _Pragma("asmend")\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+#define portTASK_FUNCTION( xFunction, pvParameters ) \\r
+ void pointed xFunction( void *pvParameters ) \\r
+ _Pragma(asmfunc xFunction)\r
+\r
+#define portTASK_FUNCTION_PROTO portTASK_FUNCTION\r
+/*-----------------------------------------------------------*/\r
+\r
+#define inline\r
+#define volatile\r
+#define register\r
+\r
+#endif /* PORTMACRO_H */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+Changes from V1.00:\r
+ \r
+ + Call to taskYIELD() from within tick ISR has been replaced by the more\r
+ efficient portSWITCH_CONTEXT().\r
+ + ISR function definitions renamed to include the prv prefix.\r
+\r
+Changes from V1.2.0:\r
+\r
+ + portRESET_PIC() is now called last thing before the end of the preemptive\r
+ tick routine.\r
+\r
+Changes from V2.6.1\r
+\r
+ + Replaced the sUsingPreemption variable with the configUSE_PREEMPTION\r
+ macro to be consistent with the later ports.\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Implementation of functions defined in portable.h for the Flashlite 186\r
+ * port.\r
+ *----------------------------------------------------------*/\r
+\r
+#include <stdlib.h>\r
+#include <i86.h>\r
+#include <dos.h>\r
+#include <setjmp.h>\r
+\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "portasm.h"\r
+\r
+/*lint -e950 Non ANSI reserved words okay in this file only. */\r
+\r
+#define portTIMER_EOI_TYPE ( 8 )\r
+#define portRESET_PIC() portOUTPUT_WORD( ( unsigned portSHORT ) 0xff22, portTIMER_EOI_TYPE )\r
+#define portTIMER_INT_NUMBER 0x12\r
+\r
+#define portTIMER_1_CONTROL_REGISTER ( ( unsigned portSHORT ) 0xff5e )\r
+#define portTIMER_0_CONTROL_REGISTER ( ( unsigned portSHORT ) 0xff56 )\r
+#define portTIMER_INTERRUPT_ENABLE ( ( unsigned portSHORT ) 0x2000 )\r
+\r
+/* Setup the hardware to generate the required tick frequency. */\r
+static void prvSetTickFrequency( unsigned portLONG ulTickRateHz );\r
+\r
+/* Set the hardware back to the state as per before the scheduler started. */\r
+static void prvExitFunction( void );\r
+\r
+#if configUSE_PREEMPTION == 1\r
+ /* Tick service routine used by the scheduler when preemptive scheduling is\r
+ being used. */\r
+ static void __interrupt __far prvPreemptiveTick( void );\r
+#else\r
+ /* Tick service routine used by the scheduler when cooperative scheduling is \r
+ being used. */\r
+ static void __interrupt __far prvNonPreemptiveTick( void );\r
+#endif\r
+\r
+/* Trap routine used by taskYIELD() to manually cause a context switch. */\r
+static void __interrupt __far prvYieldProcessor( void );\r
+\r
+/*lint -e956 File scopes necessary here. */\r
+\r
+/* Set true when the vectors are set so the scheduler will service the tick. */\r
+static portSHORT sSchedulerRunning = pdFALSE;\r
+\r
+/* Points to the original routine installed on the vector we use for manual context switches. This is then used to restore the original routine during prvExitFunction(). */\r
+static void ( __interrupt __far *pxOldSwitchISR )();\r
+\r
+/* Used to restore the original DOS context when the scheduler is ended. */\r
+static jmp_buf xJumpBuf;\r
+\r
+/*lint +e956 */\r
+\r
+/*-----------------------------------------------------------*/\r
+portBASE_TYPE xPortStartScheduler( void )\r
+{\r
+ /* This is called with interrupts already disabled. */\r
+\r
+ /* Remember what was on the interrupts we are going to use\r
+ so we can put them back later if required. */\r
+ pxOldSwitchISR = _dos_getvect( portSWITCH_INT_NUMBER );\r
+\r
+ /* Put our manual switch (yield) function on a known\r
+ vector. */\r
+ _dos_setvect( portSWITCH_INT_NUMBER, prvYieldProcessor );\r
+\r
+ #if configUSE_PREEMPTION == 1\r
+ { \r
+ /* Put our tick switch function on the timer interrupt. */\r
+ _dos_setvect( portTIMER_INT_NUMBER, prvPreemptiveTick );\r
+ }\r
+ #else\r
+ {\r
+ /* We want the timer interrupt to just increment the tick count. */\r
+ _dos_setvect( portTIMER_INT_NUMBER, prvNonPreemptiveTick );\r
+ }\r
+ #endif\r
+\r
+ prvSetTickFrequency( configTICK_RATE_HZ );\r
+\r
+ /* Clean up function if we want to return to DOS. */\r
+ if( setjmp( xJumpBuf ) != 0 )\r
+ {\r
+ prvExitFunction();\r
+ sSchedulerRunning = pdFALSE;\r
+ }\r
+ else\r
+ {\r
+ sSchedulerRunning = pdTRUE;\r
+\r
+ /* Kick off the scheduler by setting up the context of the first task. */\r
+ portFIRST_CONTEXT();\r
+ }\r
+\r
+ return sSchedulerRunning;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The tick ISR used depend on whether or not the preemptive or cooperative\r
+kernel is being used. */\r
+#if configUSE_PREEMPTION == 1\r
+ static void __interrupt __far prvPreemptiveTick( void )\r
+ {\r
+ /* Get the scheduler to update the task states following the tick. */\r
+ vTaskIncrementTick();\r
+\r
+ /* Switch in the context of the next task to be run. */\r
+ portSWITCH_CONTEXT();\r
+\r
+ /* Reset the PIC ready for the next time. */\r
+ portRESET_PIC();\r
+ }\r
+#else\r
+ static void __interrupt __far prvNonPreemptiveTick( void )\r
+ {\r
+ /* Same as preemptive tick, but the cooperative scheduler is being used\r
+ so we don't have to switch in the context of the next task. */\r
+ vTaskIncrementTick();\r
+ portRESET_PIC();\r
+ }\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+static void __interrupt __far prvYieldProcessor( void )\r
+{\r
+ /* Switch in the context of the next task to be run. */\r
+ portSWITCH_CONTEXT();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEndScheduler( void )\r
+{\r
+ /* Jump back to the processor state prior to starting the\r
+ scheduler. This means we are not going to be using a\r
+ task stack frame so the task can be deleted. */\r
+ longjmp( xJumpBuf, 1 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvExitFunction( void )\r
+{\r
+const unsigned portSHORT usTimerDisable = 0x0000;\r
+unsigned portSHORT usTimer0Control;\r
+\r
+ /* Interrupts should be disabled here anyway - but no \r
+ harm in making sure. */\r
+ portDISABLE_INTERRUPTS();\r
+ if( sSchedulerRunning == pdTRUE )\r
+ {\r
+ /* Put back the switch interrupt routines that was in place\r
+ before the scheduler started. */\r
+ _dos_setvect( portSWITCH_INT_NUMBER, pxOldSwitchISR );\r
+ }\r
+\r
+ /* Disable the timer used for the tick to ensure the scheduler is\r
+ not called before restoring interrupts. There was previously nothing\r
+ on this timer so there is no old ISR to restore. */\r
+ portOUTPUT_WORD( portTIMER_1_CONTROL_REGISTER, usTimerDisable );\r
+\r
+ /* Restart the DOS tick. */\r
+ usTimer0Control = portINPUT_WORD( portTIMER_0_CONTROL_REGISTER );\r
+ usTimer0Control |= portTIMER_INTERRUPT_ENABLE;\r
+ portOUTPUT_WORD( portTIMER_0_CONTROL_REGISTER, usTimer0Control );\r
+\r
+\r
+ portENABLE_INTERRUPTS();\r
+\r
+ /* This will free up all the memory used by the scheduler.\r
+ exiting back to dos with INT21 AH=4CH will do this anyway so\r
+ it is not necessary to call this. */\r
+ vTaskCleanUpResources(); \r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetTickFrequency( unsigned portLONG ulTickRateHz )\r
+{\r
+const unsigned portSHORT usMaxCountRegister = 0xff5a;\r
+const unsigned portSHORT usTimerPriorityRegister = 0xff32;\r
+const unsigned portSHORT usTimerEnable = 0xC000;\r
+const unsigned portSHORT usRetrigger = 0x0001;\r
+const unsigned portSHORT usTimerHighPriority = 0x0000;\r
+unsigned portSHORT usTimer0Control;\r
+\r
+/* ( CPU frequency / 4 ) / clock 2 max count [inpw( 0xff62 ) = 7] */\r
+\r
+const unsigned portLONG ulClockFrequency = 0x7f31a0;\r
+\r
+unsigned portLONG ulTimerCount = ulClockFrequency / ulTickRateHz;\r
+\r
+ portOUTPUT_WORD( portTIMER_1_CONTROL_REGISTER, usTimerEnable | portTIMER_INTERRUPT_ENABLE | usRetrigger );\r
+ portOUTPUT_WORD( usMaxCountRegister, ( unsigned portSHORT ) ulTimerCount );\r
+ portOUTPUT_WORD( usTimerPriorityRegister, usTimerHighPriority );\r
+\r
+ /* Stop the DOS tick - don't do this if you want to maintain a TOD clock. */\r
+ usTimer0Control = portINPUT_WORD( portTIMER_0_CONTROL_REGISTER );\r
+ usTimer0Control &= ~portTIMER_INTERRUPT_ENABLE;\r
+ portOUTPUT_WORD( portTIMER_0_CONTROL_REGISTER, usTimer0Control );\r
+}\r
+\r
+\r
+/*lint +e950 */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Port specific definitions. \r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the\r
+ * given hardware and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *-----------------------------------------------------------\r
+ */\r
+\r
+\r
+/* Type definitions. */\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE long\r
+#define portLONG long\r
+#define portSHORT int\r
+#define portSTACK_TYPE unsigned portSHORT\r
+#define portBASE_TYPE portSHORT\r
+\r
+#if( configUSE_16_BIT_TICKS == 1 )\r
+ typedef unsigned portSHORT portTickType;\r
+ #define portMAX_DELAY ( portTickType ) 0xffff\r
+#else\r
+ typedef unsigned portLONG portTickType;\r
+ #define portMAX_DELAY ( portTickType ) 0xffffffff\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Critical section management. */\r
+void portENTER_CRITICAL( void );\r
+#pragma aux portENTER_CRITICAL = "pushf" \\r
+ "cli";\r
+\r
+void portEXIT_CRITICAL( void );\r
+#pragma aux portEXIT_CRITICAL = "popf";\r
+\r
+void portDISABLE_INTERRUPTS( void );\r
+#pragma aux portDISABLE_INTERRUPTS = "cli";\r
+\r
+void portENABLE_INTERRUPTS( void );\r
+#pragma aux portENABLE_INTERRUPTS = "sti";\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Architecture specifics. */\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portSWITCH_INT_NUMBER 0x80\r
+#define portYIELD() __asm{ int portSWITCH_INT_NUMBER } \r
+#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ )\r
+#define portBYTE_ALIGNMENT 2\r
+#define portINITIAL_SW ( ( portSTACK_TYPE ) 0x0202 ) /* Start the tasks with interrupts enabled. */\r
+#define portNOP() __asm{ nop }\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Compiler specifics. */\r
+#define portINPUT_BYTE( xAddr ) inp( xAddr )\r
+#define portOUTPUT_BYTE( xAddr, ucValue ) outp( xAddr, ucValue )\r
+#define portINPUT_WORD( xAddr ) inpw( xAddr )\r
+#define portOUTPUT_WORD( xAddr, usValue ) outpw( xAddr, usValue )\r
+#define inline\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Task function macros as described on the FreeRTOS.org WEB site. */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+\r
+\r
+#endif /* PORTMACRO_H */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+Changes from V1.00:\r
+ \r
+ + Call to taskYIELD() from within tick ISR has been replaced by the more\r
+ efficient portSWITCH_CONTEXT().\r
+ + ISR function definitions renamed to include the prv prefix.\r
+\r
+Changes from V1.2.0:\r
+\r
+ + prvPortResetPIC() is now called last thing before the end of the \r
+ preemptive tick routine.\r
+\r
+Changes from V2.6.1\r
+\r
+ + Replaced the sUsingPreemption variable with the configUSE_PREEMPTION\r
+ macro to be consistent with the later ports.\r
+\r
+*/\r
+\r
+#include <stdlib.h>\r
+#include <stdio.h>\r
+#include <i86.h>\r
+#include <dos.h>\r
+#include <setjmp.h>\r
+\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "portasm.h"\r
+\r
+/*-----------------------------------------------------------\r
+ * Implementation of functions defined in portable.h for the industrial\r
+ * PC port.\r
+ *----------------------------------------------------------*/\r
+\r
+/*lint -e950 Non ANSI reserved words okay in this file only. */\r
+\r
+#define portTIMER_INT_NUMBER 0x08\r
+\r
+/* Setup hardware for required tick interrupt rate. */\r
+static void prvSetTickFrequency( unsigned portLONG ulTickRateHz );\r
+\r
+/* Restore hardware to as it was prior to starting the scheduler. */\r
+static void prvExitFunction( void );\r
+\r
+/* Either chain to the DOS tick (which itself clears the PIC) or clear the PIC\r
+directly. We chain to the DOS tick as close as possible to the standard DOS\r
+tick rate. */\r
+static void prvPortResetPIC( void );\r
+\r
+/* The tick ISR used depends on whether the preemptive or cooperative scheduler\r
+is being used. */\r
+#if configUSE_PREEMPTION == 1\r
+ /* Tick service routine used by the scheduler when preemptive scheduling is\r
+ being used. */\r
+ static void __interrupt __far prvPreemptiveTick( void );\r
+#else\r
+ /* Tick service routine used by the scheduler when cooperative scheduling is \r
+ being used. */\r
+ static void __interrupt __far prvNonPreemptiveTick( void );\r
+#endif\r
+/* Trap routine used by taskYIELD() to manually cause a context switch. */\r
+static void __interrupt __far prvYieldProcessor( void );\r
+\r
+/*lint -e956 File scopes necessary here. */\r
+\r
+/* Used to signal when to chain to the DOS tick, and when to just clear the PIC ourselves. */\r
+static portSHORT sDOSTickCounter; \r
+\r
+/* Set true when the vectors are set so the scheduler will service the tick. */\r
+static portSHORT sSchedulerRunning = pdFALSE; \r
+\r
+/* Points to the original routine installed on the vector we use for manual context switches. This is then used to restore the original routine during prvExitFunction(). */\r
+static void ( __interrupt __far *pxOldSwitchISR )(); \r
+\r
+/* Points to the original routine installed on the vector we use to chain to the DOS tick. This is then used to restore the original routine during prvExitFunction(). */\r
+static void ( __interrupt __far *pxOldSwitchISRPlus1 )(); \r
+\r
+/* Used to restore the original DOS context when the scheduler is ended. */\r
+static jmp_buf xJumpBuf;\r
+\r
+/*lint +e956 */\r
+\r
+/*-----------------------------------------------------------*/\r
+portBASE_TYPE xPortStartScheduler( void )\r
+{\r
+pxISR pxOriginalTickISR;\r
+ \r
+ /* This is called with interrupts already disabled. */\r
+\r
+ /* Remember what was on the interrupts we are going to use\r
+ so we can put them back later if required. */\r
+ pxOldSwitchISR = _dos_getvect( portSWITCH_INT_NUMBER );\r
+ pxOriginalTickISR = _dos_getvect( portTIMER_INT_NUMBER );\r
+ pxOldSwitchISRPlus1 = _dos_getvect( portSWITCH_INT_NUMBER + 1 );\r
+\r
+ prvSetTickFrequency( configTICK_RATE_HZ );\r
+\r
+ /* Put our manual switch (yield) function on a known\r
+ vector. */\r
+ _dos_setvect( portSWITCH_INT_NUMBER, prvYieldProcessor );\r
+\r
+ /* Put the old tick on a different interrupt number so we can\r
+ call it when we want. */\r
+ _dos_setvect( portSWITCH_INT_NUMBER + 1, pxOriginalTickISR );\r
+\r
+ #if configUSE_PREEMPTION == 1\r
+ { \r
+ /* Put our tick switch function on the timer interrupt. */\r
+ _dos_setvect( portTIMER_INT_NUMBER, prvPreemptiveTick );\r
+ }\r
+ #else\r
+ {\r
+ /* We want the timer interrupt to just increment the tick count. */\r
+ _dos_setvect( portTIMER_INT_NUMBER, prvNonPreemptiveTick );\r
+ }\r
+ #endif\r
+\r
+ /* Setup a counter that is used to call the DOS interrupt as close\r
+ to it's original frequency as can be achieved given our chosen tick\r
+ frequency. */\r
+ sDOSTickCounter = portTICKS_PER_DOS_TICK;\r
+\r
+ /* Clean up function if we want to return to DOS. */\r
+ if( setjmp( xJumpBuf ) != 0 )\r
+ {\r
+ prvExitFunction();\r
+ sSchedulerRunning = pdFALSE;\r
+ }\r
+ else\r
+ {\r
+ sSchedulerRunning = pdTRUE;\r
+\r
+ /* Kick off the scheduler by setting up the context of the first task. */\r
+ portFIRST_CONTEXT();\r
+ }\r
+\r
+ return sSchedulerRunning;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The tick ISR used depends on whether the preemptive or cooperative scheduler\r
+is being used. */\r
+#if configUSE_PREEMPTION == 1\r
+ /* Tick service routine used by the scheduler when preemptive scheduling is\r
+ being used. */\r
+ static void __interrupt __far prvPreemptiveTick( void )\r
+ {\r
+ /* Get the scheduler to update the task states following the tick. */\r
+ vTaskIncrementTick();\r
+\r
+ /* Switch in the context of the next task to be run. */\r
+ portSWITCH_CONTEXT();\r
+\r
+ /* Reset the PIC ready for the next time. */\r
+ prvPortResetPIC();\r
+ }\r
+#else\r
+ static void __interrupt __far prvNonPreemptiveTick( void )\r
+ {\r
+ /* Same as preemptive tick, but the cooperative scheduler is being used\r
+ so we don't have to switch in the context of the next task. */\r
+ vTaskIncrementTick();\r
+ prvPortResetPIC();\r
+ }\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+static void __interrupt __far prvYieldProcessor( void )\r
+{\r
+ /* Switch in the context of the next task to be run. */\r
+ portSWITCH_CONTEXT();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvPortResetPIC( void )\r
+{\r
+ /* We are going to call the DOS tick interrupt at as close a\r
+ frequency to the normal DOS tick as possible. */\r
+\r
+ /* WE SHOULD NOT DO THIS IF YIELD WAS CALLED. */\r
+ --sDOSTickCounter;\r
+ if( sDOSTickCounter <= 0 )\r
+ {\r
+ sDOSTickCounter = ( portSHORT ) portTICKS_PER_DOS_TICK;\r
+ __asm{ int portSWITCH_INT_NUMBER + 1 }; \r
+ }\r
+ else\r
+ {\r
+ /* Reset the PIC as the DOS tick is not being called to\r
+ do it. */\r
+ __asm\r
+ {\r
+ mov al, 20H\r
+ out 20H, al\r
+ };\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEndScheduler( void )\r
+{\r
+ /* Jump back to the processor state prior to starting the\r
+ scheduler. This means we are not going to be using a\r
+ task stack frame so the task can be deleted. */\r
+ longjmp( xJumpBuf, 1 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvExitFunction( void )\r
+{\r
+void ( __interrupt __far *pxOriginalTickISR )();\r
+\r
+ /* Interrupts should be disabled here anyway - but no \r
+ harm in making sure. */\r
+ portDISABLE_INTERRUPTS();\r
+ if( sSchedulerRunning == pdTRUE )\r
+ {\r
+ /* Set the DOS tick back onto the timer ticker. */\r
+ pxOriginalTickISR = _dos_getvect( portSWITCH_INT_NUMBER + 1 );\r
+ _dos_setvect( portTIMER_INT_NUMBER, pxOriginalTickISR );\r
+ /* This won't set the frequency quite the same as it was,\r
+ but using an integer value removes the need for any floating\r
+ point in the scheduler code. */\r
+ prvSetTickFrequency( ( unsigned portLONG ) portDOS_TICK_RATE );\r
+\r
+ /* Put back the switch interrupt routines that was in place\r
+ before the scheduler started. */\r
+ _dos_setvect( portSWITCH_INT_NUMBER, pxOldSwitchISR );\r
+ _dos_setvect( portSWITCH_INT_NUMBER + 1, pxOldSwitchISRPlus1 );\r
+ }\r
+ /* The tick timer is back how DOS wants it. We can re-enable\r
+ interrupts without the scheduler being called. */\r
+ portENABLE_INTERRUPTS();\r
+\r
+ /* This will free up all the memory used by the scheduler.\r
+ exiting back to dos with INT21 AH=4CH will do this anyway so\r
+ it is not necessary to call this. */\r
+ vTaskCleanUpResources(); \r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetTickFrequency( unsigned portLONG ulTickRateHz )\r
+{\r
+const unsigned portSHORT usPIT_MODE = ( unsigned portSHORT ) 0x43;\r
+const unsigned portSHORT usPIT0 = ( unsigned portSHORT ) 0x40;\r
+const unsigned portLONG ulPIT_CONST = ( unsigned portLONG ) 1193180;\r
+const unsigned portSHORT us8254_CTR0_MODE3 = ( unsigned portSHORT ) 0x36;\r
+unsigned portLONG ulOutput;\r
+\r
+ /* Setup the 8245 to tick at the wanted frequency. */\r
+ portOUTPUT_BYTE( usPIT_MODE, us8254_CTR0_MODE3 );\r
+ ulOutput = ulPIT_CONST / ulTickRateHz;\r
+ \r
+ portOUTPUT_BYTE( usPIT0, ( unsigned portSHORT )( ulOutput & ( unsigned portLONG ) 0xff ) );\r
+ ulOutput >>= 8;\r
+ portOUTPUT_BYTE( usPIT0, ( unsigned portSHORT ) ( ulOutput & ( unsigned portLONG ) 0xff ) );\r
+}\r
+\r
+\r
+/*lint +e950 */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Port specific definitions. \r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the\r
+ * given hardware and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *-----------------------------------------------------------\r
+ */\r
+\r
+/* Type definitions. */\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE double\r
+#define portLONG long\r
+#define portSHORT int\r
+#define portSTACK_TYPE unsigned portSHORT\r
+#define portBASE_TYPE portSHORT\r
+\r
+#if( configUSE_16_BIT_TICKS == 1 )\r
+ typedef unsigned portSHORT portTickType;\r
+ #define portMAX_DELAY ( portTickType ) 0xffff\r
+#else\r
+ typedef unsigned portLONG portTickType;\r
+ #define portMAX_DELAY ( portTickType ) 0xffffffff\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Critical section definitions. */\r
+void portENTER_CRITICAL( void );\r
+#pragma aux portENTER_CRITICAL = "pushf" \\r
+ "cli";\r
+void portEXIT_CRITICAL( void );\r
+#pragma aux portEXIT_CRITICAL = "popf";\r
+\r
+void portDISABLE_INTERRUPTS( void );\r
+#pragma aux portDISABLE_INTERRUPTS = "cli";\r
+\r
+void portENABLE_INTERRUPTS( void );\r
+#pragma aux portENABLE_INTERRUPTS = "sti";\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Architecture specifics. */\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portSWITCH_INT_NUMBER 0x80\r
+#define portYIELD() __asm{ int portSWITCH_INT_NUMBER } \r
+#define portDOS_TICK_RATE ( 18.20648 )\r
+#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ )\r
+#define portTICKS_PER_DOS_TICK ( ( unsigned portSHORT ) ( ( ( portDOUBLE ) configTICK_RATE_HZ / portDOS_TICK_RATE ) + 0.5 ) )\r
+#define portINITIAL_SW ( ( portSTACK_TYPE ) 0x0202 ) /* Start the tasks with interrupts enabled. */\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Compiler specifics. */\r
+#define portINPUT_BYTE( xAddr ) inp( xAddr )\r
+#define portOUTPUT_BYTE( xAddr, ucValue ) outp( xAddr, ucValue )\r
+#define inline\r
+#define portNOP() __asm{ nop }\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Task function macros as described on the FreeRTOS.org WEB site. */\r
+#define portTASK_FUNCTION_PROTO( vTaskFunction, pvParameters ) void vTaskFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vTaskFunction, pvParameters ) void vTaskFunction( void *pvParameters )\r
+\r
+#endif /* PORTMACRO_H */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+typedef void tskTCB;\r
+extern volatile tskTCB * volatile pxCurrentTCB;\r
+extern void vTaskSwitchContext( void );\r
+\r
+/* \r
+ * Saves the stack pointer for one task into its TCB, calls \r
+ * vTaskSwitchContext() to update the TCB being used, then restores the stack \r
+ * from the new TCB read to run the task. \r
+ */\r
+void portSWITCH_CONTEXT( void );\r
+\r
+/*\r
+ * Load the stack pointer from the TCB of the task which is going to be first\r
+ * to execute. Then force an IRET so the registers and IP are popped off the\r
+ * stack.\r
+ */\r
+void portFIRST_CONTEXT( void );\r
+\r
+/* There are slightly different versions depending on whether you are building\r
+to include debugger information. If debugger information is used then there\r
+are a couple of extra bytes left of the ISR stack (presumably for use by the\r
+debugger). The true stack pointer is then stored in the bp register. We add\r
+2 to the stack pointer to remove the extra bytes before we restore our context. */\r
+\r
+#ifdef DEBUG_BUILD\r
+\r
+ #pragma aux portSWITCH_CONTEXT = "mov ax, seg pxCurrentTCB" \\r
+ "mov ds, ax" \\r
+ "les bx, pxCurrentTCB" /* Save the stack pointer into the TCB. */ \\r
+ "mov es:0x2[ bx ], ss" \\r
+ "mov es:[ bx ], sp" \\r
+ "call vTaskSwitchContext" /* Perform the switch. */ \\r
+ "mov ax, seg pxCurrentTCB" /* Restore the stack pointer from the TCB. */ \\r
+ "mov ds, ax" \\r
+ "les bx, dword ptr pxCurrentTCB" \\r
+ "mov ss, es:[ bx + 2 ]" \\r
+ "mov sp, es:[ bx ]" \\r
+ "mov bp, sp" /* Prepair the bp register for the restoration of the SP in the compiler generated portion of the ISR */ \\r
+ "add bp, 0x0002"\r
+\r
+ \r
+\r
+ #pragma aux portFIRST_CONTEXT = "mov ax, seg pxCurrentTCB" \\r
+ "mov ds, ax" \\r
+ "les bx, dword ptr pxCurrentTCB" \\r
+ "mov ss, es:[ bx + 2 ]" \\r
+ "mov sp, es:[ bx ]" \\r
+ "add sp, 0x0002" /* Remove the extra bytes that exist in debug builds before restoring the context. */ \\r
+ "pop ax" \\r
+ "pop ax" \\r
+ "pop es" \\r
+ "pop ds" \\r
+ "popa" \\r
+ "iret" \r
+#else\r
+\r
+ #pragma aux portSWITCH_CONTEXT = "mov ax, seg pxCurrentTCB" \\r
+ "mov ds, ax" \\r
+ "les bx, pxCurrentTCB" /* Save the stack pointer into the TCB. */ \\r
+ "mov es:0x2[ bx ], ss" \\r
+ "mov es:[ bx ], sp" \\r
+ "call vTaskSwitchContext" /* Perform the switch. */ \\r
+ "mov ax, seg pxCurrentTCB" /* Restore the stack pointer from the TCB. */ \\r
+ "mov ds, ax" \\r
+ "les bx, dword ptr pxCurrentTCB" \\r
+ "mov ss, es:[ bx + 2 ]" \\r
+ "mov sp, es:[ bx ]"\r
+ \r
+\r
+ #pragma aux portFIRST_CONTEXT = "mov ax, seg pxCurrentTCB" \\r
+ "mov ds, ax" \\r
+ "les bx, dword ptr pxCurrentTCB" \\r
+ "mov ss, es:[ bx + 2 ]" \\r
+ "mov sp, es:[ bx ]" \\r
+ "pop ax" \\r
+ "pop ax" \\r
+ "pop es" \\r
+ "pop ds" \\r
+ "popa" \\r
+ "iret" \r
+#endif\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+Changes from V1.00:\r
+ \r
+ + pxPortInitialiseStack() now initialises the stack of new tasks to the \r
+ same format used by the compiler. This allows the compiler generated\r
+ interrupt mechanism to be used for context switches.\r
+\r
+Changes from V2.4.2:\r
+\r
+ + pvPortMalloc and vPortFree have been removed. The projects now use\r
+ the definitions from the source/portable/MemMang directory.\r
+\r
+Changes from V2.6.1:\r
+\r
+ + usPortCheckFreeStackSpace() has been moved to tasks.c.\r
+*/\r
+\r
+ \r
+\r
+#include <stdlib.h>\r
+#include "FreeRTOS.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* See header file for description. */\r
+portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
+{\r
+portSTACK_TYPE DS_Reg = 0, *pxOriginalSP;\r
+\r
+ /* Place a few bytes of known values on the bottom of the stack. \r
+ This is just useful for debugging. */\r
+\r
+ *pxTopOfStack = 0x1111;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x2222;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x3333;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x4444;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x5555;\r
+ pxTopOfStack--;\r
+\r
+\r
+ /*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */\r
+\r
+ /* We are going to start the scheduler using a return from interrupt\r
+ instruction to load the program counter, so first there would be the\r
+ status register and interrupt return address. We make this the start \r
+ of the task. */\r
+ *pxTopOfStack = portINITIAL_SW; \r
+ pxTopOfStack--;\r
+ *pxTopOfStack = FP_SEG( pxCode );\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = FP_OFF( pxCode );\r
+ pxTopOfStack--;\r
+\r
+ /* We are going to setup the stack for the new task to look like\r
+ the stack frame was setup by a compiler generated ISR. We need to know\r
+ the address of the existing stack top to place in the SP register within\r
+ the stack frame. pxOriginalSP holds SP before (simulated) pusha was \r
+ called. */\r
+ pxOriginalSP = pxTopOfStack;\r
+\r
+ /* The remaining registers would be pushed on the stack by our context \r
+ switch function. These are loaded with values simply to make debugging\r
+ easier. */\r
+ *pxTopOfStack = FP_OFF( pvParameters ); /* AX */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0xCCCC; /* CX */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = FP_SEG( pvParameters ); /* DX */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0xBBBB; /* BX */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = FP_OFF( pxOriginalSP ); /* SP */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0xBBBB; /* BP */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x0123; /* SI */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0xDDDD; /* DI */\r
+\r
+ /* We need the true data segment. */\r
+ __asm{ MOV DS_Reg, DS };\r
+\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = DS_Reg; /* DS */\r
+\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0xEEEE; /* ES */\r
+\r
+ /* The AX register is pushed again twice - don't know why. */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = FP_OFF( pvParameters ); /* AX */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = FP_OFF( pvParameters ); /* AX */\r
+\r
+\r
+ #ifdef DEBUG_BUILD\r
+ /* The compiler adds space to each ISR stack if building to\r
+ include debug information. Presumably this is used by the\r
+ debugger - we don't need to initialise it to anything just\r
+ make sure it is there. */\r
+ pxTopOfStack--;\r
+ #endif\r
+\r
+ /*lint +e950 +e611 +e923 */\r
+\r
+ return pxTopOfStack;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
--- /dev/null
+Each real time kernel port consists of three files that contain the core kernel\r
+components and are common to every port, and one or more files that are \r
+specific to a particular microcontroller and/or compiler.\r
+\r
+\r
++ The FreeRTOS/Source/Portable/MemMang directory contains the three sample \r
+memory allocators as described on the http://www.FreeRTOS.org WEB site.\r
+\r
++ The other directories each contain files specific to a particular \r
+microcontroller or compiler.\r
+\r
+\r
+\r
+For example, if you are interested in the GCC port for the ATMega323 \r
+microcontroller then the port specific files are contained in\r
+FreeRTOS/Source/Portable/GCC/ATMega323 directory. If this is the only\r
+port you are interested in then all the other directories can be\r
+ignored.\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+Changes from V1.01\r
+\r
+ + More use of 8bit data types.\r
+ + Function name prefixes changed where the data type returned has changed.\r
+\r
+Changed from V2.0.0\r
+\r
+ + Added the queue locking mechanism and make more use of the scheduler\r
+ suspension feature to minimise the time interrupts have to be disabled\r
+ when accessing a queue.\r
+\r
+Changed from V2.2.0\r
+\r
+ + Explicit use of 'signed' qualifier on portCHAR types added.\r
+\r
+Changes from V3.0.0\r
+\r
+ + API changes as described on the FreeRTOS.org WEB site.\r
+\r
+Changes from V3.2.3\r
+\r
+ + Added the queue functions that can be used from co-routines.\r
+\r
+*/\r
+\r
+#include <stdlib.h>\r
+#include <string.h>\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "croutine.h"\r
+\r
+/*-----------------------------------------------------------\r
+ * PUBLIC LIST API documented in list.h\r
+ *----------------------------------------------------------*/\r
+\r
+/* Constants used with the cRxLock and cTxLock structure members. */\r
+#define queueUNLOCKED ( ( signed portBASE_TYPE ) -1 )\r
+\r
+/*\r
+ * Definition of the queue used by the scheduler.\r
+ * Items are queued by copy, not reference.\r
+ */\r
+typedef struct QueueDefinition\r
+{\r
+ signed portCHAR *pcHead; /*< Points to the beginning of the queue storage area. */\r
+ signed portCHAR *pcTail; /*< Points to the byte at the end of the queue storage area. Once more byte is allocated than necessary to store the queue items, this is used as a marker. */\r
+\r
+ signed portCHAR *pcWriteTo; /*< Points to the free next place in the storage area. */\r
+ signed portCHAR *pcReadFrom; /*< Points to the last place that a queued item was read from. */\r
+\r
+ xList xTasksWaitingToSend; /*< List of tasks that are blocked waiting to post onto this queue. Stored in priority order. */\r
+ xList xTasksWaitingToReceive; /*< List of tasks that are blocked waiting to read from this queue. Stored in priority order. */\r
+\r
+ unsigned portBASE_TYPE uxMessagesWaiting;/*< The number of items currently in the queue. */\r
+ unsigned portBASE_TYPE uxLength; /*< The length of the queue defined as the number of items it will hold, not the number of bytes. */\r
+ unsigned portBASE_TYPE uxItemSize; /*< The size of each items that the queue will hold. */\r
+\r
+ signed portBASE_TYPE xRxLock; /*< Stores the number of items received from the queue (removed from the queue) while the queue was locked. Set to queueUNLOCKED when the queue is not locked. */\r
+ signed portBASE_TYPE xTxLock; /*< Stores the number of items transmitted to the queue (added to the queue) while the queue was locked. Set to queueUNLOCKED when the queue is not locked. */\r
+} xQUEUE;\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Inside this file xQueueHandle is a pointer to a xQUEUE structure.\r
+ * To keep the definition private the API header file defines it as a\r
+ * pointer to void.\r
+ */\r
+typedef xQUEUE * xQueueHandle;\r
+\r
+/*\r
+ * Prototypes for public functions are included here so we don't have to\r
+ * include the API header file (as it defines xQueueHandle differently). These\r
+ * functions are documented in the API header file.\r
+ */\r
+xQueueHandle xQueueCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize );\r
+signed portBASE_TYPE xQueueSend( xQueueHandle xQueue, const void * pvItemToQueue, portTickType xTicksToWait );\r
+unsigned portBASE_TYPE uxQueueMessagesWaiting( xQueueHandle pxQueue );\r
+void vQueueDelete( xQueueHandle xQueue );\r
+signed portBASE_TYPE xQueueSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xTaskPreviouslyWoken );\r
+signed portBASE_TYPE xQueueReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait );\r
+signed portBASE_TYPE xQueueReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxTaskWoken );\r
+\r
+#if configUSE_CO_ROUTINES == 1\r
+ signed portBASE_TYPE xQueueCRSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xCoRoutinePreviouslyWoken );\r
+ signed portBASE_TYPE xQueueCRReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxTaskWoken );\r
+ signed portBASE_TYPE xQueueCRSend( xQueueHandle pxQueue, const void *pvItemToQueue, portTickType xTicksToWait );\r
+ signed portBASE_TYPE xQueueCRReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait );\r
+#endif\r
+\r
+/*\r
+ * Unlocks a queue locked by a call to prvLockQueue. Locking a queue does not\r
+ * prevent an ISR from adding or removing items to the queue, but does prevent\r
+ * an ISR from removing tasks from the queue event lists. If an ISR finds a\r
+ * queue is locked it will instead increment the appropriate queue lock count\r
+ * to indicate that a task may require unblocking. When the queue in unlocked\r
+ * these lock counts are inspected, and the appropriate action taken.\r
+ */\r
+static signed portBASE_TYPE prvUnlockQueue( xQueueHandle pxQueue );\r
+\r
+/*\r
+ * Uses a critical section to determine if there is any data in a queue.\r
+ *\r
+ * @return pdTRUE if the queue contains no items, otherwise pdFALSE.\r
+ */\r
+static signed portBASE_TYPE prvIsQueueEmpty( const xQueueHandle pxQueue );\r
+\r
+/*\r
+ * Uses a critical section to determine if there is any space in a queue.\r
+ *\r
+ * @return pdTRUE if there is no space, otherwise pdFALSE;\r
+ */\r
+static signed portBASE_TYPE prvIsQueueFull( const xQueueHandle pxQueue );\r
+\r
+/*\r
+ * Macro that copies an item into the queue. This is done by copying the item\r
+ * byte for byte, not by reference. Updates the queue state to ensure it's\r
+ * integrity after the copy.\r
+ */\r
+#define prvCopyQueueData( pxQueue, pvItemToQueue ) \\r
+{ \\r
+ memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( unsigned ) pxQueue->uxItemSize ); \\r
+ ++( pxQueue->uxMessagesWaiting ); \\r
+ pxQueue->pcWriteTo += pxQueue->uxItemSize; \\r
+ if( pxQueue->pcWriteTo >= pxQueue->pcTail ) \\r
+ { \\r
+ pxQueue->pcWriteTo = pxQueue->pcHead; \\r
+ } \\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Macro to mark a queue as locked. Locking a queue prevents an ISR from\r
+ * accessing the queue event lists.\r
+ */\r
+#define prvLockQueue( pxQueue ) \\r
+{ \\r
+ taskENTER_CRITICAL(); \\r
+ ++( pxQueue->xRxLock ); \\r
+ ++( pxQueue->xTxLock ); \\r
+ taskEXIT_CRITICAL(); \\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ * PUBLIC QUEUE MANAGEMENT API documented in queue.h\r
+ *----------------------------------------------------------*/\r
+\r
+xQueueHandle xQueueCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize )\r
+{\r
+xQUEUE *pxNewQueue;\r
+size_t xQueueSizeInBytes;\r
+\r
+ /* Allocate the new queue structure. */\r
+ if( uxQueueLength > ( unsigned portBASE_TYPE ) 0 )\r
+ {\r
+ pxNewQueue = ( xQUEUE * ) pvPortMalloc( sizeof( xQUEUE ) );\r
+ if( pxNewQueue != NULL )\r
+ {\r
+ /* Create the list of pointers to queue items. The queue is one byte\r
+ longer than asked for to make wrap checking easier/faster. */\r
+ xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ) + ( size_t ) 1;\r
+\r
+ pxNewQueue->pcHead = ( signed portCHAR * ) pvPortMalloc( xQueueSizeInBytes );\r
+ if( pxNewQueue->pcHead != NULL )\r
+ {\r
+ /* Initialise the queue members as described above where the\r
+ queue type is defined. */\r
+ pxNewQueue->pcTail = pxNewQueue->pcHead + ( uxQueueLength * uxItemSize );\r
+ pxNewQueue->uxMessagesWaiting = 0;\r
+ pxNewQueue->pcWriteTo = pxNewQueue->pcHead;\r
+ pxNewQueue->pcReadFrom = pxNewQueue->pcHead + ( ( uxQueueLength - 1 ) * uxItemSize );\r
+ pxNewQueue->uxLength = uxQueueLength;\r
+ pxNewQueue->uxItemSize = uxItemSize;\r
+ pxNewQueue->xRxLock = queueUNLOCKED;\r
+ pxNewQueue->xTxLock = queueUNLOCKED;\r
+\r
+ /* Likewise ensure the event queues start with the correct state. */\r
+ vListInitialise( &( pxNewQueue->xTasksWaitingToSend ) );\r
+ vListInitialise( &( pxNewQueue->xTasksWaitingToReceive ) );\r
+\r
+ return pxNewQueue;\r
+ }\r
+ else\r
+ {\r
+ vPortFree( pxNewQueue );\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Will only reach here if we could not allocate enough memory or no memory\r
+ was required. */\r
+ return NULL;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xQueueSend( xQueueHandle pxQueue, const void *pvItemToQueue, portTickType xTicksToWait )\r
+{\r
+signed portBASE_TYPE xReturn;\r
+\r
+ /* Make sure other tasks do not access the queue. */\r
+ vTaskSuspendAll();\r
+\r
+ /* It is important that this is the only thread/ISR that modifies the\r
+ ready or delayed lists until xTaskResumeAll() is called. Places where\r
+ the ready/delayed lists are modified include:\r
+\r
+ + vTaskDelay() - Nothing can call vTaskDelay as the scheduler is\r
+ suspended, vTaskDelay() cannot be called from an ISR.\r
+ + vTaskPrioritySet() - Has a critical section around the access.\r
+ + vTaskSwitchContext() - This will not get executed while the scheduler\r
+ is suspended.\r
+ + prvCheckDelayedTasks() - This will not get executed while the\r
+ scheduler is suspended.\r
+ + xTaskCreate() - Has a critical section around the access.\r
+ + vTaskResume() - Has a critical section around the access.\r
+ + xTaskResumeAll() - Has a critical section around the access.\r
+ + xTaskRemoveFromEventList - Checks to see if the scheduler is\r
+ suspended. If so then the TCB being removed from the event is\r
+ removed from the event and added to the xPendingReadyList.\r
+ */\r
+\r
+ /* Make sure interrupts do not access the queue event list. */\r
+ prvLockQueue( pxQueue );\r
+\r
+ /* It is important that interrupts to not access the event list of the\r
+ queue being modified here. Places where the event list is modified\r
+ include:\r
+\r
+ + xQueueSendFromISR(). This checks the lock on the queue to see if\r
+ it has access. If the queue is locked then the Tx lock count is\r
+ incremented to signify that a task waiting for data can be made ready\r
+ once the queue lock is removed. If the queue is not locked then\r
+ a task can be moved from the event list, but will not be removed\r
+ from the delayed list or placed in the ready list until the scheduler\r
+ is unlocked.\r
+\r
+ + xQueueReceiveFromISR(). As per xQueueSendFromISR().\r
+ */\r
+ \r
+ /* If the queue is already full we may have to block. */\r
+ if( prvIsQueueFull( pxQueue ) )\r
+ {\r
+ /* The queue is full - do we want to block or just leave without\r
+ posting? */\r
+ if( xTicksToWait > ( portTickType ) 0 )\r
+ {\r
+ /* We are going to place ourselves on the xTasksWaitingToSend event\r
+ list, and will get woken should the delay expire, or space become\r
+ available on the queue.\r
+ \r
+ As detailed above we do not require mutual exclusion on the event\r
+ list as nothing else can modify it or the ready lists while we\r
+ have the scheduler suspended and queue locked.\r
+ \r
+ It is possible that an ISR has removed data from the queue since we\r
+ checked if any was available. If this is the case then the data\r
+ will have been copied from the queue, and the queue variables\r
+ updated, but the event list will not yet have been checked to see if\r
+ anything is waiting as the queue is locked. */\r
+ vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );\r
+\r
+ /* Force a context switch now as we are blocked. We can do\r
+ this from within a critical section as the task we are\r
+ switching to has its own context. When we return here (i.e. we\r
+ unblock) we will leave the critical section as normal.\r
+ \r
+ It is possible that an ISR has caused an event on an unrelated and\r
+ unlocked queue. If this was the case then the event list for that\r
+ queue will have been updated but the ready lists left unchanged -\r
+ instead the readied task will have been added to the pending ready\r
+ list. */\r
+ taskENTER_CRITICAL();\r
+ {\r
+ /* We can safely unlock the queue and scheduler here as\r
+ interrupts are disabled. We must not yield with anything\r
+ locked, but we can yield from within a critical section.\r
+ \r
+ Tasks that have been placed on the pending ready list cannot\r
+ be tasks that are waiting for events on this queue. See\r
+ in comment xTaskRemoveFromEventList(). */\r
+ prvUnlockQueue( pxQueue );\r
+\r
+ /* Resuming the scheduler may cause a yield. If so then there\r
+ is no point yielding again here. */\r
+ if( !xTaskResumeAll() )\r
+ {\r
+ taskYIELD();\r
+ }\r
+\r
+ /* Before leaving the critical section we have to ensure\r
+ exclusive access again. */\r
+ vTaskSuspendAll();\r
+ prvLockQueue( pxQueue ); \r
+ }\r
+ taskEXIT_CRITICAL();\r
+ }\r
+ }\r
+ \r
+ /* When we are here it is possible that we unblocked as space became\r
+ available on the queue. It is also possible that an ISR posted to the\r
+ queue since we left the critical section, so it may be that again there\r
+ is no space. This would only happen if a task and ISR post onto the\r
+ same queue. */\r
+ taskENTER_CRITICAL();\r
+ {\r
+ if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )\r
+ {\r
+ /* There is room in the queue, copy the data into the queue. */ \r
+ prvCopyQueueData( pxQueue, pvItemToQueue ); \r
+ xReturn = pdPASS;\r
+\r
+ /* Update the TxLock count so prvUnlockQueue knows to check for\r
+ tasks waiting for data to become available in the queue. */\r
+ ++( pxQueue->xTxLock );\r
+ }\r
+ else\r
+ {\r
+ xReturn = errQUEUE_FULL;\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+\r
+ /* We no longer require exclusive access to the queue. prvUnlockQueue\r
+ will remove any tasks suspended on a receive if either this function\r
+ or an ISR has posted onto the queue. */\r
+ if( prvUnlockQueue( pxQueue ) )\r
+ {\r
+ /* Resume the scheduler - making ready any tasks that were woken\r
+ by an event while the scheduler was locked. Resuming the\r
+ scheduler may cause a yield, in which case there is no point\r
+ yielding again here. */\r
+ if( !xTaskResumeAll() )\r
+ {\r
+ taskYIELD();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Resume the scheduler - making ready any tasks that were woken\r
+ by an event while the scheduler was locked. */\r
+ xTaskResumeAll();\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xQueueSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xTaskPreviouslyWoken )\r
+{\r
+ /* Similar to xQueueSend, except we don't block if there is no room in the\r
+ queue. Also we don't directly wake a task that was blocked on a queue\r
+ read, instead we return a flag to say whether a context switch is required\r
+ or not (i.e. has a task with a higher priority than us been woken by this\r
+ post). */\r
+ if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )\r
+ {\r
+ prvCopyQueueData( pxQueue, pvItemToQueue );\r
+\r
+ /* If the queue is locked we do not alter the event list. This will\r
+ be done when the queue is unlocked later. */\r
+ if( pxQueue->xTxLock == queueUNLOCKED )\r
+ {\r
+ /* We only want to wake one task per ISR, so check that a task has\r
+ not already been woken. */\r
+ if( !xTaskPreviouslyWoken ) \r
+ {\r
+ if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) )\r
+ {\r
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\r
+ {\r
+ /* The task waiting has a higher priority so record that a\r
+ context switch is required. */\r
+ return pdTRUE;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Increment the lock count so the task that unlocks the queue\r
+ knows that data was posted while it was locked. */\r
+ ++( pxQueue->xTxLock );\r
+ }\r
+ }\r
+\r
+ return xTaskPreviouslyWoken;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xQueueReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait )\r
+{\r
+signed portBASE_TYPE xReturn;\r
+\r
+ /* This function is very similar to xQueueSend(). See comments within\r
+ xQueueSend() for a more detailed explanation.\r
+\r
+ Make sure other tasks do not access the queue. */\r
+ vTaskSuspendAll();\r
+\r
+ /* Make sure interrupts do not access the queue. */\r
+ prvLockQueue( pxQueue );\r
+\r
+ /* If there are no messages in the queue we may have to block. */\r
+ if( prvIsQueueEmpty( pxQueue ) )\r
+ {\r
+ /* There are no messages in the queue, do we want to block or just\r
+ leave with nothing? */ \r
+ if( xTicksToWait > ( portTickType ) 0 )\r
+ {\r
+ vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );\r
+ taskENTER_CRITICAL();\r
+ {\r
+ prvUnlockQueue( pxQueue );\r
+ if( !xTaskResumeAll() )\r
+ {\r
+ taskYIELD();\r
+ }\r
+\r
+ vTaskSuspendAll();\r
+ prvLockQueue( pxQueue );\r
+ }\r
+ taskEXIT_CRITICAL();\r
+ }\r
+ }\r
+\r
+ taskENTER_CRITICAL();\r
+ {\r
+ if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 )\r
+ {\r
+ pxQueue->pcReadFrom += pxQueue->uxItemSize;\r
+ if( pxQueue->pcReadFrom >= pxQueue->pcTail )\r
+ {\r
+ pxQueue->pcReadFrom = pxQueue->pcHead;\r
+ }\r
+ --( pxQueue->uxMessagesWaiting );\r
+ memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->pcReadFrom, ( unsigned ) pxQueue->uxItemSize );\r
+\r
+ /* Increment the lock count so prvUnlockQueue knows to check for\r
+ tasks waiting for space to become available on the queue. */\r
+ ++( pxQueue->xRxLock );\r
+ xReturn = pdPASS;\r
+ }\r
+ else\r
+ {\r
+ xReturn = pdFAIL;\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+\r
+ /* We no longer require exclusive access to the queue. */\r
+ if( prvUnlockQueue( pxQueue ) )\r
+ {\r
+ if( !xTaskResumeAll() )\r
+ {\r
+ taskYIELD();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ xTaskResumeAll();\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xQueueReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxTaskWoken )\r
+{\r
+signed portBASE_TYPE xReturn;\r
+\r
+ /* We cannot block from an ISR, so check there is data available. */\r
+ if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 )\r
+ {\r
+ /* Copy the data from the queue. */\r
+ pxQueue->pcReadFrom += pxQueue->uxItemSize;\r
+ if( pxQueue->pcReadFrom >= pxQueue->pcTail )\r
+ {\r
+ pxQueue->pcReadFrom = pxQueue->pcHead;\r
+ }\r
+ --( pxQueue->uxMessagesWaiting );\r
+ memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->pcReadFrom, ( unsigned ) pxQueue->uxItemSize );\r
+\r
+ /* If the queue is locked we will not modify the event list. Instead\r
+ we update the lock count so the task that unlocks the queue will know\r
+ that an ISR has removed data while the queue was locked. */\r
+ if( pxQueue->xRxLock == queueUNLOCKED )\r
+ {\r
+ /* We only want to wake one task per ISR, so check that a task has\r
+ not already been woken. */\r
+ if( !( *pxTaskWoken ) )\r
+ {\r
+ if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) )\r
+ {\r
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )\r
+ {\r
+ /* The task waiting has a higher priority than us so\r
+ force a context switch. */\r
+ *pxTaskWoken = pdTRUE;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Increment the lock count so the task that unlocks the queue\r
+ knows that data was removed while it was locked. */\r
+ ++( pxQueue->xRxLock );\r
+ }\r
+\r
+ xReturn = pdPASS;\r
+ }\r
+ else\r
+ {\r
+ xReturn = pdFAIL;\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+unsigned portBASE_TYPE uxQueueMessagesWaiting( xQueueHandle pxQueue )\r
+{\r
+unsigned portBASE_TYPE uxReturn;\r
+\r
+ taskENTER_CRITICAL();\r
+ uxReturn = pxQueue->uxMessagesWaiting;\r
+ taskEXIT_CRITICAL();\r
+\r
+ return uxReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vQueueDelete( xQueueHandle pxQueue )\r
+{\r
+ vPortFree( pxQueue->pcHead );\r
+ vPortFree( pxQueue );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static signed portBASE_TYPE prvUnlockQueue( xQueueHandle pxQueue )\r
+{\r
+signed portBASE_TYPE xYieldRequired = pdFALSE;\r
+\r
+ /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. */\r
+\r
+ /* The lock counts contains the number of extra data items placed or\r
+ removed from the queue while the queue was locked. When a queue is\r
+ locked items can be added or removed, but the event lists cannot be\r
+ updated. */\r
+ taskENTER_CRITICAL();\r
+ {\r
+ --( pxQueue->xTxLock );\r
+\r
+ /* See if data was added to the queue while it was locked. */\r
+ if( pxQueue->xTxLock > queueUNLOCKED )\r
+ {\r
+ pxQueue->xTxLock = queueUNLOCKED;\r
+\r
+ /* Data was posted while the queue was locked. Are any tasks\r
+ blocked waiting for data to become available? */\r
+ if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) )\r
+ {\r
+ /* Tasks that are removed from the event list will get added to\r
+ the pending ready list as the scheduler is still suspended. */\r
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\r
+ {\r
+ /* The task waiting has a higher priority so record that a\r
+ context switch is required. */\r
+ xYieldRequired = pdTRUE;\r
+ }\r
+ } \r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+\r
+ /* Do the same for the Rx lock. */\r
+ taskENTER_CRITICAL();\r
+ {\r
+ --( pxQueue->xRxLock );\r
+\r
+ if( pxQueue->xRxLock > queueUNLOCKED )\r
+ {\r
+ pxQueue->xRxLock = queueUNLOCKED;\r
+\r
+ if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) )\r
+ {\r
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )\r
+ {\r
+ xYieldRequired = pdTRUE;\r
+ }\r
+ } \r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+\r
+ return xYieldRequired;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static signed portBASE_TYPE prvIsQueueEmpty( const xQueueHandle pxQueue )\r
+{\r
+signed portBASE_TYPE xReturn;\r
+\r
+ taskENTER_CRITICAL();\r
+ xReturn = ( pxQueue->uxMessagesWaiting == ( unsigned portBASE_TYPE ) 0 );\r
+ taskEXIT_CRITICAL();\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static signed portBASE_TYPE prvIsQueueFull( const xQueueHandle pxQueue )\r
+{\r
+signed portBASE_TYPE xReturn;\r
+\r
+ taskENTER_CRITICAL();\r
+ xReturn = ( pxQueue->uxMessagesWaiting == pxQueue->uxLength );\r
+ taskEXIT_CRITICAL();\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if configUSE_CO_ROUTINES == 1\r
+signed portBASE_TYPE xQueueCRSend( xQueueHandle pxQueue, const void *pvItemToQueue, portTickType xTicksToWait )\r
+{\r
+signed portBASE_TYPE xReturn;\r
+ \r
+ /* If the queue is already full we may have to block. A critical section\r
+ is required to prevent an interrupt removing something from the queue \r
+ between the check to see if the queue is full and blocking on the queue. */\r
+ portDISABLE_INTERRUPTS();\r
+ {\r
+ if( prvIsQueueFull( pxQueue ) )\r
+ {\r
+ /* The queue is full - do we want to block or just leave without\r
+ posting? */\r
+ if( xTicksToWait > ( portTickType ) 0 )\r
+ {\r
+ /* As this is called from a coroutine we cannot block directly, but\r
+ return indicating that we need to block. */\r
+ vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToSend ) ); \r
+ portENABLE_INTERRUPTS();\r
+ return errQUEUE_BLOCKED;\r
+ }\r
+ else\r
+ {\r
+ portENABLE_INTERRUPTS();\r
+ return errQUEUE_FULL;\r
+ }\r
+ }\r
+ }\r
+ portENABLE_INTERRUPTS();\r
+ \r
+ portNOP();\r
+\r
+ portDISABLE_INTERRUPTS();\r
+ {\r
+ if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )\r
+ {\r
+ /* There is room in the queue, copy the data into the queue. */ \r
+ prvCopyQueueData( pxQueue, pvItemToQueue ); \r
+ xReturn = pdPASS;\r
+\r
+ /* Were any co-routines waiting for data to become available? */\r
+ if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) )\r
+ {\r
+ /* In this instance the co-routine could be placed directly \r
+ into the ready list as we are within a critical section. \r
+ Instead the same pending ready list mechansim is used as if\r
+ the event were caused from within an interrupt. */\r
+ if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\r
+ {\r
+ /* The co-routine waiting has a higher priority so record \r
+ that a yield might be appropriate. */\r
+ xReturn = errQUEUE_YIELD;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ xReturn = errQUEUE_FULL;\r
+ }\r
+ }\r
+ portENABLE_INTERRUPTS();\r
+\r
+ return xReturn;\r
+}\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if configUSE_CO_ROUTINES == 1\r
+signed portBASE_TYPE xQueueCRReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait )\r
+{\r
+signed portBASE_TYPE xReturn;\r
+\r
+ /* If the queue is already empty we may have to block. A critical section\r
+ is required to prevent an interrupt adding something to the queue \r
+ between the check to see if the queue is empty and blocking on the queue. */\r
+ portDISABLE_INTERRUPTS();\r
+ {\r
+ if( prvIsQueueEmpty( pxQueue ) )\r
+ {\r
+ /* There are no messages in the queue, do we want to block or just\r
+ leave with nothing? */ \r
+ if( xTicksToWait > ( portTickType ) 0 )\r
+ {\r
+ /* As this is a co-routine we cannot block directly, but return\r
+ indicating that we need to block. */\r
+ vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToReceive ) );\r
+ portENABLE_INTERRUPTS();\r
+ return errQUEUE_BLOCKED;\r
+ }\r
+ else\r
+ {\r
+ portENABLE_INTERRUPTS();\r
+ return errQUEUE_FULL;\r
+ }\r
+ }\r
+ }\r
+ portENABLE_INTERRUPTS();\r
+\r
+ portNOP();\r
+\r
+ portDISABLE_INTERRUPTS();\r
+ {\r
+ if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 )\r
+ {\r
+ /* Data is available from the queue. */\r
+ pxQueue->pcReadFrom += pxQueue->uxItemSize;\r
+ if( pxQueue->pcReadFrom >= pxQueue->pcTail )\r
+ {\r
+ pxQueue->pcReadFrom = pxQueue->pcHead;\r
+ }\r
+ --( pxQueue->uxMessagesWaiting );\r
+ memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->pcReadFrom, ( unsigned ) pxQueue->uxItemSize );\r
+\r
+ xReturn = pdPASS;\r
+\r
+ /* Were any co-routines waiting for space to become available? */\r
+ if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) )\r
+ {\r
+ /* In this instance the co-routine could be placed directly \r
+ into the ready list as we are within a critical section. \r
+ Instead the same pending ready list mechansim is used as if\r
+ the event were caused from within an interrupt. */\r
+ if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )\r
+ {\r
+ xReturn = errQUEUE_YIELD;\r
+ }\r
+ } \r
+ }\r
+ else\r
+ {\r
+ xReturn = pdFAIL;\r
+ }\r
+ }\r
+ portENABLE_INTERRUPTS();\r
+\r
+ return xReturn;\r
+}\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+\r
+#if configUSE_CO_ROUTINES == 1\r
+signed portBASE_TYPE xQueueCRSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xCoRoutinePreviouslyWoken )\r
+{\r
+ /* Cannot block within an ISR so if there is no space on the queue then\r
+ exit without doing anything. */\r
+ if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )\r
+ {\r
+ prvCopyQueueData( pxQueue, pvItemToQueue );\r
+\r
+ /* We only want to wake one co-routine per ISR, so check that a \r
+ co-routine has not already been woken. */\r
+ if( !xCoRoutinePreviouslyWoken ) \r
+ {\r
+ if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) )\r
+ {\r
+ if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\r
+ {\r
+ return pdTRUE;\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ return xCoRoutinePreviouslyWoken;\r
+}\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if configUSE_CO_ROUTINES == 1\r
+signed portBASE_TYPE xQueueCRReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxCoRoutineWoken )\r
+{\r
+signed portBASE_TYPE xReturn;\r
+\r
+ /* We cannot block from an ISR, so check there is data available. If\r
+ not then just leave without doing anything. */\r
+ if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 )\r
+ {\r
+ /* Copy the data from the queue. */\r
+ pxQueue->pcReadFrom += pxQueue->uxItemSize;\r
+ if( pxQueue->pcReadFrom >= pxQueue->pcTail )\r
+ {\r
+ pxQueue->pcReadFrom = pxQueue->pcHead;\r
+ }\r
+ --( pxQueue->uxMessagesWaiting );\r
+ memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->pcReadFrom, ( unsigned ) pxQueue->uxItemSize );\r
+\r
+ if( !( *pxCoRoutineWoken ) )\r
+ {\r
+ if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) )\r
+ {\r
+ if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )\r
+ {\r
+ *pxCoRoutineWoken = pdTRUE;\r
+ }\r
+ }\r
+ }\r
+\r
+ xReturn = pdPASS;\r
+ }\r
+ else\r
+ {\r
+ xReturn = pdFAIL;\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+Each real time kernel port consists of three files that contain the core kernel\r
+components and are common to every port, and one or more files that are \r
+specific to a particular microcontroller and or compiler.\r
+\r
++ The FreeRTOS/Source directory contains the three files that are common to \r
+every port. The kernel is contained within these three files.\r
+\r
++ The FreeRTOS/Source/Portable directory contains the files that are specific to \r
+a particular microcontroller and or compiler.\r
+\r
++ The FreeRTOS/Source/include directory contains the real time kernel header \r
+files.\r
+\r
+See the readme file in the FreeRTOS/Source/Portable directory for more \r
+information.
\ No newline at end of file
--- /dev/null
+/*\r
+ FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+Changes from V1.00:\r
+ \r
+ + Call to portRESTORE_CONTEXT has been removed. The first context\r
+ switch is now performed within sPortStartScheduler().\r
+\r
+Changes from V1.01:\r
+\r
+ + More use of 8bit data types.\r
+ + Function name prefixes changed where the data type returned has changed.\r
+ + configUSE_TRACE_FACILITY is no longer defined by default.\r
+\r
+Changes from V1.2.0\r
+\r
+ + Introduced ucTopReadyPriority. This tracks the highest priority ready\r
+ queue that contains a valid TCB and thus makes the context switch\r
+ slightly faster.\r
+\r
+ + prvAddTaskToReadyQueue() has been made a macro.\r
+\r
+Changes from V1.2.6\r
+\r
+ + Added conditional compilation directives.\r
+ + Extended API.\r
+ + Rearranged function order.\r
+ + Creating a task now causes a context switch if the task being created\r
+ has a higher priority than the calling task - assuming the kernel is\r
+ running.\r
+ + vTaskDelete() now only causes a context switch if the calling task is\r
+ the task being deleted.\r
+\r
+Changes from V2.0.0\r
+\r
+ + Allow the type of the tick count to be 16 or 32 bits.\r
+ + Introduce xPendingReadyList feature to allow the time interrupts have to\r
+ be disabled to be minimised.\r
+ + Remove the #if( INCLUDE_vTaskSuspendAll ) statements. vTaskSuspendAll()\r
+ is now always included as it is used by the scheduler itself.\r
+\r
+Changes from V2.1.0\r
+\r
+ + Bug fix - pxCurrentTCB is now initialised before the call to\r
+ prvInitializeTaskLists(). Previously pxCurrentTCB could be accessed\r
+ while null.\r
+\r
+Changed from V2.1.1\r
+\r
+ + Change to where lStackSize is declared within sTaskCreate() to prevent\r
+ compiler warnings with 8051 port.\r
+\r
+Changes from V2.2.0\r
+\r
+ + Explicit use of 'signed' qualifier on portCHAR types added.\r
+ + Changed odd calculation of initial pxTopOfStack value when\r
+ portSTACK_GROWTH < 0.\r
+ + Removed pcVersionNumber definition.\r
+\r
+Changes from V2.5.3\r
+\r
+ + cTaskResumeAll() modified to ensure it can be called prior to the task\r
+ lists being initialised.\r
+\r
+Changes from V2.5.5\r
+\r
+ + Added API function vTaskDelayUntil().\r
+ + Added INCLUDE_vTaskDelay conditional compilation.\r
+\r
+Changes from V2.6.0\r
+\r
+ + Updated the vWriteTraceToBuffer macro to always be 4 byte aligned so it\r
+ can be used on ARM architectures.\r
+ + tskMAX_TASK_NAME_LEN definition replaced with the port specific\r
+ configMAX_TASK_NAME_LEN definition.\r
+ + Removed the call to strcpy when copying across the task name into the\r
+ TCB.\r
+ + Added ucTasksDeleted variable to prevent vTaskSuspendAll() being called\r
+ too often in the idle task.\r
+\r
+Changes between V3.0.0 and V2.6.1\r
+\r
+ + When resuming the scheduler a yield is performed if either a tick has\r
+ been missed, or a task is moved from the pending ready list into a ready\r
+ list. Previously a yield was not performed on this second condition.\r
+ + Introduced the type portBASE_TYPE. This necessitates several API\r
+ changes.\r
+ + Removed the sUsingPreemption variable. The constant defined in\r
+ portmacro.h is now used directly.\r
+ + The idle task can now include an optional hook function - and no longer\r
+ completes its time slice if other tasks with equal priority to it are\r
+ ready to run.\r
+ + See the FreeRTOS.org documentation for more information on V2.x.x to\r
+ V3.x.x modifications.\r
+\r
+Changes from V3.1.1\r
+\r
+ + Modified vTaskPrioritySet() and vTaskResume() to allow these functions to\r
+ be called while the scheduler is suspended.\r
+ + Corrected the task ordering within event lists.\r
+\r
+Changes from V3.2.0\r
+\r
+ + Added function xTaskGetCurrentTaskHandle().\r
+\r
+Changes from V3.2.4\r
+\r
+ + Changed the volatile declarations on some variables to reflect the \r
+ changes to the list definitions.\r
+ + Changed the order of the TCB definition so there is commonality between\r
+ the task control block and a co-routine control block.\r
+ + Allow the scheduler to be started even if no tasks other than the idle\r
+ task has been created. This allows co-routines to run even when no tasks\r
+ have been created.\r
+ + The need for a context switch is now signalled if a task woken by an \r
+ event has a priority greater or equal to the currently running task.\r
+ Previously this was only greater than.\r
+\r
+Changes from V4.0.0\r
+\r
+ + Added the xMissedYield handling.\r
+*/\r
+\r
+#include <stdio.h>\r
+#include <stdlib.h>\r
+#include <string.h>\r
+\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/*\r
+ * Macro to define the amount of stack available to the idle task.\r
+ */\r
+#define tskIDLE_STACK_SIZE configMINIMAL_STACK_SIZE\r
+\r
+\r
+/*\r
+ * Default a definitions for backwards compatibility with old\r
+ * portmacro.h files.\r
+ */\r
+#ifndef configMAX_TASK_NAME_LEN\r
+ #define configMAX_TASK_NAME_LEN 16\r
+#endif\r
+\r
+#ifndef INCLUDE_xTaskGetCurrentTaskHandle\r
+ #define INCLUDE_xTaskGetCurrentTaskHandle 0\r
+#endif\r
+\r
+#ifndef configIDLE_SHOULD_YIELD\r
+ #define configIDLE_SHOULD_YIELD 1\r
+#endif\r
+\r
+#if configMAX_TASK_NAME_LEN < 1\r
+ #undef configMAX_TASK_NAME_LEN\r
+ #define configMAX_TASK_NAME_LEN 1\r
+#endif\r
+\r
+\r
+/*\r
+ * Task control block. A task control block (TCB) is allocated to each task,\r
+ * and stores the context of the task.\r
+ */\r
+typedef struct tskTaskControlBlock\r
+{\r
+ volatile portSTACK_TYPE *pxTopOfStack; /*< Points to the location of the last item placed on the tasks stack. THIS MUST BE THE FIRST MEMBER OF THE STRUCT. */\r
+ xListItem xGenericListItem; /*< List item used to place the TCB in ready and blocked queues. */\r
+ xListItem xEventListItem; /*< List item used to place the TCB in event lists. */\r
+ unsigned portBASE_TYPE uxPriority; /*< The priority of the task where 0 is the lowest priority. */\r
+ portSTACK_TYPE *pxStack; /*< Points to the start of the stack. */\r
+ unsigned portBASE_TYPE uxTCBNumber; /*< This is used for tracing the scheduler and making debugging easier only. */\r
+ signed portCHAR pcTaskName[ configMAX_TASK_NAME_LEN ];/*< Descriptive name given to the task when created. Facilitates debugging only. */\r
+ unsigned portSHORT usStackDepth; /*< Total depth of the stack (when empty). This is defined as the number of variables the stack can hold, not the number of bytes. */\r
+} tskTCB;\r
+\r
+/*lint -e956 */\r
+\r
+tskTCB * volatile pxCurrentTCB = NULL; \r
+\r
+/* Lists for ready and blocked tasks. --------------------*/\r
+\r
+static xList pxReadyTasksLists[ configMAX_PRIORITIES ]; /*< Prioritised ready tasks. */\r
+static xList xDelayedTaskList1; /*< Delayed tasks. */\r
+static xList xDelayedTaskList2; /*< Delayed tasks (two lists are used - one for delays that have overflowed the current tick count. */\r
+static xList * volatile pxDelayedTaskList; /*< Points to the delayed task list currently being used. */\r
+static xList * volatile pxOverflowDelayedTaskList; /*< Points to the delayed task list currently being used to hold tasks that have overflowed the current tick count. */\r
+static xList xPendingReadyList; /*< Tasks that have been readied while the scheduler was suspended. They will be moved to the ready queue when the scheduler is resumed. */\r
+\r
+#if ( INCLUDE_vTaskDelete == 1 )\r
+\r
+ static volatile xList xTasksWaitingTermination; /*< Tasks that have been deleted - but the their memory not yet freed. */\r
+ static volatile unsigned portBASE_TYPE uxTasksDeleted = ( unsigned portBASE_TYPE ) 0;\r
+\r
+#endif\r
+\r
+#if ( INCLUDE_vTaskSuspend == 1 )\r
+\r
+ static xList xSuspendedTaskList; /*< Tasks that are currently suspended. */\r
+\r
+#endif\r
+\r
+/* File private variables. --------------------------------*/\r
+static volatile unsigned portBASE_TYPE uxCurrentNumberOfTasks = ( unsigned portBASE_TYPE ) 0;\r
+static volatile portTickType xTickCount = ( portTickType ) 0;\r
+static unsigned portBASE_TYPE uxTopUsedPriority = tskIDLE_PRIORITY;\r
+static volatile unsigned portBASE_TYPE uxTopReadyPriority = tskIDLE_PRIORITY;\r
+static volatile signed portBASE_TYPE xSchedulerRunning = pdFALSE;\r
+static volatile unsigned portBASE_TYPE uxSchedulerSuspended = ( unsigned portBASE_TYPE ) pdFALSE;\r
+static volatile unsigned portBASE_TYPE uxMissedTicks = ( unsigned portBASE_TYPE ) 0;\r
+static volatile portBASE_TYPE xMissedYield = ( portBASE_TYPE ) pdFALSE;\r
+\r
+/* Debugging and trace facilities private variables and macros. ------------*/\r
+\r
+/*\r
+ * The value used to fill the stack of a task when the task is created. This\r
+ * is used purely for checking the high water mark for tasks.\r
+ */\r
+#define tskSTACK_FILL_BYTE ( 0xa5 )\r
+\r
+/*\r
+ * Macros used by vListTask to indicate which state a task is in.\r
+ */\r
+#define tskBLOCKED_CHAR ( ( signed portCHAR ) 'B' )\r
+#define tskREADY_CHAR ( ( signed portCHAR ) 'R' )\r
+#define tskDELETED_CHAR ( ( signed portCHAR ) 'D' )\r
+#define tskSUSPENDED_CHAR ( ( signed portCHAR ) 'S' )\r
+\r
+/*\r
+ * Macros and private variables used by the trace facility.\r
+ */\r
+#if ( configUSE_TRACE_FACILITY == 1 )\r
+\r
+ #define tskSIZE_OF_EACH_TRACE_LINE ( ( unsigned portLONG ) ( sizeof( unsigned portLONG ) + sizeof( unsigned portLONG ) ) )\r
+ static volatile signed portCHAR * volatile pcTraceBuffer;\r
+ static signed portCHAR *pcTraceBufferStart;\r
+ static signed portCHAR *pcTraceBufferEnd;\r
+ static signed portBASE_TYPE xTracing = pdFALSE;\r
+\r
+#endif\r
+\r
+/*\r
+ * Macro that writes a trace of scheduler activity to a buffer. This trace\r
+ * shows which task is running when and is very useful as a debugging tool.\r
+ * As this macro is called each context switch it is a good idea to undefine\r
+ * it if not using the facility.\r
+ */\r
+#if ( configUSE_TRACE_FACILITY == 1 )\r
+\r
+ #define vWriteTraceToBuffer() \\r
+ { \\r
+ if( xTracing ) \\r
+ { \\r
+ static unsigned portBASE_TYPE uxPreviousTask = 255; \\r
+ \\r
+ if( uxPreviousTask != pxCurrentTCB->uxTCBNumber ) \\r
+ { \\r
+ if( ( pcTraceBuffer + tskSIZE_OF_EACH_TRACE_LINE ) < pcTraceBufferEnd ) \\r
+ { \\r
+ uxPreviousTask = pxCurrentTCB->uxTCBNumber; \\r
+ *( unsigned portLONG * ) pcTraceBuffer = ( unsigned portLONG ) xTickCount; \\r
+ pcTraceBuffer += sizeof( unsigned portLONG ); \\r
+ *( unsigned portLONG * ) pcTraceBuffer = ( unsigned portLONG ) uxPreviousTask; \\r
+ pcTraceBuffer += sizeof( unsigned portLONG ); \\r
+ } \\r
+ else \\r
+ { \\r
+ xTracing = pdFALSE; \\r
+ } \\r
+ } \\r
+ } \\r
+ }\r
+\r
+#else\r
+\r
+ #define vWriteTraceToBuffer()\r
+\r
+#endif\r
+\r
+\r
+/*\r
+ * Place the task represented by pxTCB into the appropriate ready queue for\r
+ * the task. It is inserted at the end of the list. One quirk of this is\r
+ * that if the task being inserted is at the same priority as the currently\r
+ * executing task, then it will only be rescheduled after the currently\r
+ * executing task has been rescheduled.\r
+ */\r
+#define prvAddTaskToReadyQueue( pxTCB ) \\r
+{ \\r
+ if( pxTCB->uxPriority > uxTopReadyPriority ) \\r
+ { \\r
+ uxTopReadyPriority = pxTCB->uxPriority; \\r
+ } \\r
+ vListInsertEnd( ( xList * ) &( pxReadyTasksLists[ pxTCB->uxPriority ] ), &( pxTCB->xGenericListItem ) ); \\r
+} \r
+\r
+\r
+/*\r
+ * Macro that looks at the list of tasks that are currently delayed to see if\r
+ * any require waking.\r
+ *\r
+ * Tasks are stored in the queue in the order of their wake time - meaning\r
+ * once one tasks has been found whose timer has not expired we need not look\r
+ * any further down the list.\r
+ */\r
+#define prvCheckDelayedTasks() \\r
+{ \\r
+register tskTCB *pxTCB; \\r
+ \\r
+ while( ( pxTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ) ) != NULL ) \\r
+ { \\r
+ if( xTickCount < listGET_LIST_ITEM_VALUE( &( pxTCB->xGenericListItem ) ) ) \\r
+ { \\r
+ break; \\r
+ } \\r
+ vListRemove( &( pxTCB->xGenericListItem ) ); \\r
+ /* Is the task waiting on an event also? */ \\r
+ if( pxTCB->xEventListItem.pvContainer ) \\r
+ { \\r
+ vListRemove( &( pxTCB->xEventListItem ) ); \\r
+ } \\r
+ prvAddTaskToReadyQueue( pxTCB ); \\r
+ } \\r
+} \r
+\r
+/*\r
+ * Several functions take an xTaskHandle parameter that can optionally be NULL,\r
+ * where NULL is used to indicate that the handle of the currently executing\r
+ * task should be used in place of the parameter. This macro simply checks to\r
+ * see if the parameter is NULL and returns a pointer to the appropriate TCB.\r
+ */\r
+#define prvGetTCBFromHandle( pxHandle ) ( ( pxHandle == NULL ) ? ( tskTCB * ) pxCurrentTCB : ( tskTCB * ) pxHandle )\r
+\r
+\r
+/* File private functions. --------------------------------*/\r
+\r
+/*\r
+ * Utility to ready a TCB for a given task. Mainly just copies the parameters\r
+ * into the TCB structure.\r
+ */\r
+static void prvInitialiseTCBVariables( tskTCB *pxTCB, unsigned portSHORT usStackDepth, const signed portCHAR * const pcName, unsigned portBASE_TYPE uxPriority );\r
+\r
+/*\r
+ * Utility to ready all the lists used by the scheduler. This is called\r
+ * automatically upon the creation of the first task.\r
+ */\r
+static void prvInitialiseTaskLists( void );\r
+\r
+/*\r
+ * The idle task, which as all tasks is implemented as a never ending loop.\r
+ * The idle task is automatically created and added to the ready lists upon\r
+ * creation of the first user task.\r
+ *\r
+ * The portTASK_FUNCTION_PROTO() macro is used to allow port/compiler specific\r
+ * language extensions. The equivalent prototype for this function is:\r
+ *\r
+ * void prvIdleTask( void *pvParameters );\r
+ *\r
+ */\r
+static portTASK_FUNCTION_PROTO( prvIdleTask, pvParameters );\r
+\r
+/*\r
+ * Utility to free all memory allocated by the scheduler to hold a TCB,\r
+ * including the stack pointed to by the TCB.\r
+ *\r
+ * This does not free memory allocated by the task itself (i.e. memory\r
+ * allocated by calls to pvPortMalloc from within the tasks application code).\r
+ */\r
+#if ( ( INCLUDE_vTaskDelete == 1 ) || ( INCLUDE_vTaskCleanUpResources == 1 ) )\r
+ static void prvDeleteTCB( tskTCB *pxTCB );\r
+#endif\r
+\r
+/*\r
+ * Used only by the idle task. This checks to see if anything has been placed\r
+ * in the list of tasks waiting to be deleted. If so the task is cleaned up\r
+ * and its TCB deleted.\r
+ */\r
+static void prvCheckTasksWaitingTermination( void );\r
+\r
+/*\r
+ * Allocates memory from the heap for a TCB and associated stack. Checks the\r
+ * allocation was successful.\r
+ */\r
+static tskTCB *prvAllocateTCBAndStack( unsigned portSHORT usStackDepth );\r
+\r
+/*\r
+ * Called from vTaskList. vListTasks details all the tasks currently under\r
+ * control of the scheduler. The tasks may be in one of a number of lists.\r
+ * prvListTaskWithinSingleList accepts a list and details the tasks from\r
+ * within just that list.\r
+ *\r
+ * THIS FUNCTION IS INTENDED FOR DEBUGGING ONLY, AND SHOULD NOT BE CALLED FROM\r
+ * NORMAL APPLICATION CODE.\r
+ */\r
+#if ( configUSE_TRACE_FACILITY == 1 )\r
+\r
+ static void prvListTaskWithinSingleList( signed portCHAR *pcWriteBuffer, xList *pxList, signed portCHAR cStatus );\r
+\r
+#endif\r
+\r
+/*\r
+ * When a task is created, the stack of the task is filled with a known value.\r
+ * This function determines the 'high water mark' of the task stack by\r
+ * determining how much of the stack remains at the original preset value.\r
+ */\r
+#if ( configUSE_TRACE_FACILITY == 1 )\r
+\r
+ unsigned portSHORT usTaskCheckFreeStackSpace( const unsigned portCHAR *pucStackByte );\r
+\r
+#endif\r
+\r
+/*lint +e956 */\r
+\r
+\r
+\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ * TASK CREATION API documented in task.h\r
+ *----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xTaskCreate( pdTASK_CODE pvTaskCode, const signed portCHAR * const pcName, unsigned portSHORT usStackDepth, void *pvParameters, unsigned portBASE_TYPE uxPriority, xTaskHandle *pxCreatedTask )\r
+{\r
+signed portBASE_TYPE xReturn;\r
+tskTCB * pxNewTCB;\r
+static unsigned portBASE_TYPE uxTaskNumber = 0; /*lint !e956 Static is deliberate - this is guarded before use. */\r
+\r
+ /* Allocate the memory required by the TCB and stack for the new task.\r
+ checking that the allocation was successful. */\r
+ pxNewTCB = prvAllocateTCBAndStack( usStackDepth );\r
+\r
+ if( pxNewTCB != NULL )\r
+ { \r
+ portSTACK_TYPE *pxTopOfStack;\r
+\r
+ /* Setup the newly allocated TCB with the initial state of the task. */\r
+ prvInitialiseTCBVariables( pxNewTCB, usStackDepth, pcName, uxPriority );\r
+\r
+ /* Calculate the top of stack address. This depends on whether the\r
+ stack grows from high memory to low (as per the 80x86) or visa versa.\r
+ portSTACK_GROWTH is used to make the result positive or negative as\r
+ required by the port. */\r
+ #if portSTACK_GROWTH < 0\r
+ {\r
+ pxTopOfStack = pxNewTCB->pxStack + ( pxNewTCB->usStackDepth - 1 );\r
+ }\r
+ #else\r
+ {\r
+ pxTopOfStack = pxNewTCB->pxStack; \r
+ }\r
+ #endif\r
+\r
+ /* Initialize the TCB stack to look as if the task was already running,\r
+ but had been interrupted by the scheduler. The return address is set\r
+ to the start of the task function. Once the stack has been initialised\r
+ the top of stack variable is updated. */\r
+ pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pvTaskCode, pvParameters );\r
+\r
+ /* We are going to manipulate the task queues to add this task to a\r
+ ready list, so must make sure no interrupts occur. */\r
+ portENTER_CRITICAL();\r
+ {\r
+ uxCurrentNumberOfTasks++;\r
+ if( uxCurrentNumberOfTasks == ( unsigned portBASE_TYPE ) 1 )\r
+ {\r
+ /* As this is the first task it must also be the current task. */\r
+ pxCurrentTCB = pxNewTCB;\r
+\r
+ /* This is the first task to be created so do the preliminary\r
+ initialisation required. We will not recover if this call\r
+ fails, but we will report the failure. */\r
+ prvInitialiseTaskLists();\r
+ }\r
+ else\r
+ { \r
+ /* If the scheduler is not already running, make this task the\r
+ current task if it is the highest priority task to be created\r
+ so far. */\r
+ if( xSchedulerRunning == pdFALSE )\r
+ {\r
+ if( pxCurrentTCB->uxPriority <= uxPriority )\r
+ {\r
+ pxCurrentTCB = pxNewTCB; \r
+ }\r
+ }\r
+ } \r
+\r
+ /* Remember the top priority to make context switching faster. Use\r
+ the priority in pxNewTCB as this has been capped to a valid value. */\r
+ if( pxNewTCB->uxPriority > uxTopUsedPriority )\r
+ {\r
+ uxTopUsedPriority = pxNewTCB->uxPriority;\r
+ }\r
+\r
+ /* Add a counter into the TCB for tracing only. */\r
+ pxNewTCB->uxTCBNumber = uxTaskNumber;\r
+ uxTaskNumber++;\r
+\r
+ prvAddTaskToReadyQueue( pxNewTCB );\r
+\r
+ xReturn = pdPASS;\r
+ }\r
+ portEXIT_CRITICAL();\r
+ }\r
+ else\r
+ {\r
+ xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;\r
+ }\r
+\r
+ if( xReturn == pdPASS )\r
+ {\r
+ if( ( void * ) pxCreatedTask != NULL )\r
+ {\r
+ /* Pass the TCB out - in an anonymous way. The calling function/\r
+ task can use this as a handle to delete the task later if\r
+ required.*/\r
+ *pxCreatedTask = ( xTaskHandle ) pxNewTCB;\r
+ }\r
+\r
+ if( xSchedulerRunning != pdFALSE )\r
+ {\r
+ /* If the created task is of a higher priority than the current task\r
+ then it should run now. */\r
+ if( pxCurrentTCB->uxPriority < uxPriority )\r
+ {\r
+ taskYIELD();\r
+ }\r
+ }\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( INCLUDE_vTaskDelete == 1 )\r
+\r
+ void vTaskDelete( xTaskHandle pxTaskToDelete )\r
+ {\r
+ tskTCB *pxTCB;\r
+\r
+ taskENTER_CRITICAL();\r
+ {\r
+ /* If null is passed in here then we are deleting ourselves. */\r
+ pxTCB = prvGetTCBFromHandle( pxTaskToDelete );\r
+\r
+ /* Remove task from the ready list and place in the termination list.\r
+ This will stop the task from be scheduled. The idle task will check\r
+ the termination list and free up any memory allocated by the\r
+ scheduler for the TCB and stack. */\r
+ vListRemove( &( pxTCB->xGenericListItem ) );\r
+\r
+ /* Is the task waiting on an event also? */ \r
+ if( pxTCB->xEventListItem.pvContainer )\r
+ {\r
+ vListRemove( &( pxTCB->xEventListItem ) );\r
+ }\r
+\r
+ vListInsertEnd( ( xList * ) &xTasksWaitingTermination, &( pxTCB->xGenericListItem ) );\r
+\r
+ /* Increment the ucTasksDeleted variable so the idle task knows\r
+ there is a task that has been deleted and that it should therefore\r
+ check the xTasksWaitingTermination list. */\r
+ ++uxTasksDeleted;\r
+ }\r
+ taskEXIT_CRITICAL();\r
+\r
+ /* Force a reschedule if we have just deleted the current task. */\r
+ if( ( void * ) pxTaskToDelete == NULL )\r
+ {\r
+ taskYIELD();\r
+ }\r
+ }\r
+\r
+#endif\r
+\r
+\r
+\r
+\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ * TASK CONTROL API documented in task.h\r
+ *----------------------------------------------------------*/\r
+\r
+#if ( INCLUDE_vTaskDelayUntil == 1 )\r
+\r
+ void vTaskDelayUntil( portTickType *pxPreviousWakeTime, portTickType xTimeIncrement )\r
+ {\r
+ portTickType xTimeToWake;\r
+ portBASE_TYPE xAlreadyYielded, xShouldDelay = pdFALSE;\r
+\r
+ vTaskSuspendAll();\r
+ {\r
+ /* Generate the tick time at which the task wants to wake. */\r
+ xTimeToWake = *pxPreviousWakeTime + xTimeIncrement;\r
+\r
+ if( xTickCount < *pxPreviousWakeTime )\r
+ {\r
+ /* The tick count has overflowed since this function was\r
+ lasted called. In this case the only time we should ever\r
+ actually delay is if the wake time has also overflowed,\r
+ and the wake time is greater than the tick time. When this\r
+ is the case it is as if neither time had overflowed. */\r
+ if( ( xTimeToWake < *pxPreviousWakeTime ) && ( xTimeToWake > xTickCount ) )\r
+ {\r
+ xShouldDelay = pdTRUE;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* The tick time has not overflowed. In this case we will\r
+ delay if either the wake time has overflowed, and/or the\r
+ tick time is less than the wake time. */\r
+ if( ( xTimeToWake < *pxPreviousWakeTime ) || ( xTimeToWake > xTickCount ) )\r
+ {\r
+ xShouldDelay = pdTRUE;\r
+ }\r
+ }\r
+\r
+ /* Update the wake time ready for the next call. */\r
+ *pxPreviousWakeTime = xTimeToWake;\r
+\r
+ if( xShouldDelay )\r
+ {\r
+ /* We must remove ourselves from the ready list before adding\r
+ ourselves to the blocked list as the same list item is used for\r
+ both lists. */\r
+ vListRemove( ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) );\r
+\r
+ /* The list item will be inserted in wake time order. */\r
+ listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xGenericListItem ), xTimeToWake );\r
+\r
+ if( xTimeToWake < xTickCount )\r
+ {\r
+ /* Wake time has overflowed. Place this item in the\r
+ overflow list. */\r
+ vListInsert( ( xList * ) pxOverflowDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) );\r
+ }\r
+ else\r
+ {\r
+ /* The wake time has not overflowed, so we can use the\r
+ current block list. */\r
+ vListInsert( ( xList * ) pxDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) );\r
+ }\r
+ }\r
+ }\r
+ xAlreadyYielded = xTaskResumeAll();\r
+\r
+ /* Force a reschedule if xTaskResumeAll has not already done so, we may\r
+ have put ourselves to sleep. */\r
+ if( !xAlreadyYielded )\r
+ {\r
+ taskYIELD();\r
+ }\r
+ } \r
+ \r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( INCLUDE_vTaskDelay == 1 )\r
+\r
+ void vTaskDelay( portTickType xTicksToDelay )\r
+ {\r
+ portTickType xTimeToWake;\r
+ signed portBASE_TYPE xAlreadyYielded = pdFALSE;\r
+\r
+ /* A delay time of zero just forces a reschedule. */\r
+ if( xTicksToDelay > ( portTickType ) 0 )\r
+ {\r
+ vTaskSuspendAll();\r
+ {\r
+ /* A task that is removed from the event list while the\r
+ scheduler is suspended will not get placed in the ready\r
+ list or removed from the blocked list until the scheduler\r
+ is resumed.\r
+ \r
+ This task cannot be in an event list as it is the currently\r
+ executing task. */\r
+\r
+ /* Calculate the time to wake - this may overflow but this is\r
+ not a problem. */\r
+ xTimeToWake = xTickCount + xTicksToDelay;\r
+\r
+ /* We must remove ourselves from the ready list before adding\r
+ ourselves to the blocked list as the same list item is used for\r
+ both lists. */\r
+ vListRemove( ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) );\r
+\r
+ /* The list item will be inserted in wake time order. */\r
+ listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xGenericListItem ), xTimeToWake );\r
+\r
+ if( xTimeToWake < xTickCount )\r
+ {\r
+ /* Wake time has overflowed. Place this item in the\r
+ overflow list. */\r
+ vListInsert( ( xList * ) pxOverflowDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) );\r
+ }\r
+ else\r
+ {\r
+ /* The wake time has not overflowed, so we can use the\r
+ current block list. */\r
+ vListInsert( ( xList * ) pxDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) );\r
+ }\r
+ }\r
+ xAlreadyYielded = xTaskResumeAll();\r
+ }\r
+ \r
+ /* Force a reschedule if xTaskResumeAll has not already done so, we may\r
+ have put ourselves to sleep. */\r
+ if( !xAlreadyYielded )\r
+ {\r
+ taskYIELD();\r
+ }\r
+ }\r
+ \r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( INCLUDE_uxTaskPriorityGet == 1 )\r
+\r
+ unsigned portBASE_TYPE uxTaskPriorityGet( xTaskHandle pxTask )\r
+ {\r
+ tskTCB *pxTCB;\r
+ unsigned portBASE_TYPE uxReturn;\r
+\r
+ taskENTER_CRITICAL();\r
+ {\r
+ /* If null is passed in here then we are changing the\r
+ priority of the calling function. */\r
+ pxTCB = prvGetTCBFromHandle( pxTask );\r
+ uxReturn = pxTCB->uxPriority;\r
+ }\r
+ taskEXIT_CRITICAL();\r
+\r
+ return uxReturn;\r
+ }\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( INCLUDE_vTaskPrioritySet == 1 )\r
+\r
+ void vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority )\r
+ {\r
+ tskTCB *pxTCB;\r
+ unsigned portBASE_TYPE uxCurrentPriority;\r
+\r
+ /* Ensure the new priority is valid. */\r
+ if( uxNewPriority >= configMAX_PRIORITIES )\r
+ {\r
+ uxNewPriority = configMAX_PRIORITIES - 1;\r
+ }\r
+\r
+ taskENTER_CRITICAL();\r
+ {\r
+ /* If null is passed in here then we are changing the\r
+ priority of the calling function. */\r
+ pxTCB = prvGetTCBFromHandle( pxTask );\r
+ uxCurrentPriority = pxTCB->uxPriority;\r
+\r
+ if( uxCurrentPriority != uxNewPriority )\r
+ {\r
+ pxTCB->uxPriority = uxNewPriority;\r
+\r
+ /* If the task is in the blocked or suspended list we need do\r
+ nothing more than change it's priority variable. However, if\r
+ the task is in a ready list it needs to be removed and placed\r
+ in the queue appropriate to its new priority. */\r
+ if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxCurrentPriority ] ), &( pxTCB->xGenericListItem ) ) )\r
+ {\r
+ if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE )\r
+ {\r
+ /* The task is currently in its ready list - remove before adding\r
+ it to it's new ready list. */\r
+ vListRemove( &( pxTCB->xGenericListItem ) );\r
+ prvAddTaskToReadyQueue( pxTCB );\r
+ }\r
+ else\r
+ {\r
+ /* We cannot access the delayed or ready lists, so will hold this\r
+ task pending until the scheduler is resumed. */\r
+ vListInsertEnd( ( xList * ) &( xPendingReadyList ), &( pxTCB->xEventListItem ) );\r
+ }\r
+ } \r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+\r
+ /* The priority change may have readied a task of higher\r
+ priority than the calling task. */\r
+ taskYIELD();\r
+ }\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( INCLUDE_vTaskSuspend == 1 )\r
+\r
+ void vTaskSuspend( xTaskHandle pxTaskToSuspend )\r
+ {\r
+ tskTCB *pxTCB;\r
+\r
+ taskENTER_CRITICAL();\r
+ {\r
+ /* If null is passed in here then we are suspending ourselves. */\r
+ pxTCB = prvGetTCBFromHandle( pxTaskToSuspend );\r
+\r
+ /* Remove task from the ready/delayed list and place in the suspended list. */\r
+ vListRemove( &( pxTCB->xGenericListItem ) );\r
+\r
+ /* Is the task waiting on an event also? */ \r
+ if( pxTCB->xEventListItem.pvContainer )\r
+ {\r
+ vListRemove( &( pxTCB->xEventListItem ) );\r
+ }\r
+\r
+ vListInsertEnd( ( xList * ) &xSuspendedTaskList, &( pxTCB->xGenericListItem ) );\r
+ }\r
+ taskEXIT_CRITICAL();\r
+\r
+ /* We may have just suspended the current task. */\r
+ if( ( void * ) pxTaskToSuspend == NULL )\r
+ {\r
+ taskYIELD();\r
+ }\r
+ }\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( INCLUDE_vTaskSuspend == 1 )\r
+\r
+ void vTaskResume( xTaskHandle pxTaskToResume )\r
+ {\r
+ tskTCB *pxTCB;\r
+ portBASE_TYPE xYieldRequired;\r
+\r
+ /* Remove the task from whichever list it is currently in, and place\r
+ it in the ready list. */\r
+ pxTCB = ( tskTCB * ) pxTaskToResume;\r
+\r
+ /* The parameter cannot be NULL as it is impossible to resume the\r
+ currently executing task. */\r
+ if( pxTCB != NULL )\r
+ {\r
+ taskENTER_CRITICAL();\r
+ {\r
+ if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE )\r
+ {\r
+ xYieldRequired = ( pxTCB->uxPriority >= pxCurrentTCB->uxPriority );\r
+ vListRemove( &( pxTCB->xGenericListItem ) );\r
+ prvAddTaskToReadyQueue( pxTCB );\r
+ }\r
+ else\r
+ {\r
+ /* We cannot access the delayed or ready lists, so will hold this\r
+ task pending until the scheduler is resumed. */\r
+ xYieldRequired = pdFALSE;\r
+ vListInsertEnd( ( xList * ) &( xPendingReadyList ), &( pxTCB->xEventListItem ) );\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+\r
+ /* We may have just resumed a higher priority task. */\r
+ if( xYieldRequired )\r
+ {\r
+ /* This yield may not cause the task just resumed to run, but\r
+ will leave the lists in the correct state for the next yield. */\r
+ taskYIELD();\r
+ }\r
+ }\r
+ }\r
+\r
+#endif\r
+\r
+\r
+\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ * PUBLIC SCHEDULER CONTROL documented in task.h\r
+ *----------------------------------------------------------*/\r
+\r
+\r
+void vTaskStartScheduler( void )\r
+{\r
+portBASE_TYPE xReturn;\r
+\r
+ /* Add the idle task at the lowest priority. */\r
+ xReturn = xTaskCreate( prvIdleTask, ( signed portCHAR * ) "IDLE", tskIDLE_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, ( xTaskHandle * ) NULL );\r
+\r
+ if( xReturn == pdPASS )\r
+ {\r
+ /* Interrupts are turned off here, to ensure a tick does not occur\r
+ before or during the call to xPortStartScheduler(). The stacks of\r
+ the created tasks contain a status word with interrupts switched on\r
+ so interrupts will automatically get re-enabled when the first task\r
+ starts to run.\r
+ \r
+ STEPPING THROUGH HERE USING A DEBUGGER CAN CAUSE BIG PROBLEMS IF THE\r
+ DEBUGGER ALLOWS INTERRUPTS TO BE PROCESSED. */\r
+ portDISABLE_INTERRUPTS();\r
+\r
+ xSchedulerRunning = pdTRUE;\r
+ xTickCount = ( portTickType ) 0;\r
+\r
+ /* Setting up the timer tick is hardware specific and thus in the\r
+ portable interface. */\r
+ if( xPortStartScheduler() )\r
+ {\r
+ /* Should not reach here as if the scheduler is running the\r
+ function will not return. */\r
+ }\r
+ else\r
+ {\r
+ /* Should only reach here if a task calls xTaskEndScheduler(). */\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vTaskEndScheduler( void )\r
+{\r
+ /* Stop the scheduler interrupts and call the portable scheduler end\r
+ routine so the original ISRs can be restored if necessary. The port\r
+ layer must ensure interrupts enable bit is left in the correct state. */\r
+ portDISABLE_INTERRUPTS();\r
+ xSchedulerRunning = pdFALSE;\r
+ vPortEndScheduler();\r
+}\r
+/*----------------------------------------------------------*/\r
+\r
+void vTaskSuspendAll( void )\r
+{\r
+ portENTER_CRITICAL();\r
+ ++uxSchedulerSuspended;\r
+ portEXIT_CRITICAL();\r
+}\r
+/*----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xTaskResumeAll( void )\r
+{\r
+register tskTCB *pxTCB;\r
+signed portBASE_TYPE xAlreadyYielded = pdFALSE;\r
+\r
+ /* It is possible that an ISR caused a task to be removed from an event\r
+ list while the scheduler was suspended. If this was the case then the\r
+ removed task will have been added to the xPendingReadyList. Once the\r
+ scheduler has been resumed it is safe to move all the pending ready\r
+ tasks from this list into their appropriate ready list. */\r
+ portENTER_CRITICAL();\r
+ {\r
+ --uxSchedulerSuspended;\r
+\r
+ if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE )\r
+ { \r
+ if( uxCurrentNumberOfTasks > ( unsigned portBASE_TYPE ) 0 )\r
+ {\r
+ portBASE_TYPE xYieldRequired = pdFALSE;\r
+ \r
+ /* Move any readied tasks from the pending list into the\r
+ appropriate ready list. */\r
+ while( ( pxTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( ( ( xList * ) &xPendingReadyList ) ) ) != NULL )\r
+ {\r
+ vListRemove( &( pxTCB->xEventListItem ) );\r
+ vListRemove( &( pxTCB->xGenericListItem ) );\r
+ prvAddTaskToReadyQueue( pxTCB );\r
+ \r
+ /* If we have moved a task that has a priority higher than\r
+ the current task then we should yield. */\r
+ if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )\r
+ {\r
+ xYieldRequired = pdTRUE;\r
+ }\r
+ }\r
+\r
+ /* If any ticks occurred while the scheduler was suspended then\r
+ they should be processed now. This ensures the tick count does not\r
+ slip, and that any delayed tasks are resumed at the correct time. */\r
+ if( uxMissedTicks > ( unsigned portBASE_TYPE ) 0 )\r
+ {\r
+ while( uxMissedTicks > ( unsigned portBASE_TYPE ) 0 )\r
+ {\r
+ vTaskIncrementTick();\r
+ --uxMissedTicks;\r
+ }\r
+\r
+ /* As we have processed some ticks it is appropriate to yield\r
+ to ensure the highest priority task that is ready to run is\r
+ the task actually running. */\r
+ xYieldRequired = pdTRUE;\r
+ }\r
+ \r
+ if( ( xYieldRequired == pdTRUE ) || ( xMissedYield == pdTRUE ) )\r
+ {\r
+ xAlreadyYielded = pdTRUE;\r
+ xMissedYield = pdFALSE;\r
+ taskYIELD();\r
+ }\r
+ }\r
+ }\r
+ }\r
+ portEXIT_CRITICAL();\r
+\r
+ return xAlreadyYielded;\r
+}\r
+\r
+\r
+\r
+\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ * PUBLIC TASK UTILITIES documented in task.h\r
+ *----------------------------------------------------------*/\r
+\r
+\r
+\r
+portTickType xTaskGetTickCount( void )\r
+{\r
+portTickType xTicks;\r
+\r
+ /* Critical section required if running on a 16 bit processor. */\r
+ taskENTER_CRITICAL();\r
+ {\r
+ xTicks = xTickCount;\r
+ }\r
+ taskEXIT_CRITICAL();\r
+\r
+ return xTicks;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+unsigned portBASE_TYPE uxTaskGetNumberOfTasks( void )\r
+{\r
+unsigned portBASE_TYPE uxNumberOfTasks;\r
+\r
+ taskENTER_CRITICAL();\r
+ uxNumberOfTasks = uxCurrentNumberOfTasks;\r
+ taskEXIT_CRITICAL();\r
+\r
+ return uxNumberOfTasks;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_vTaskDelete == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) )\r
+\r
+ void vTaskList( signed portCHAR *pcWriteBuffer )\r
+ {\r
+ unsigned portBASE_TYPE uxQueue;\r
+\r
+ /* This is a VERY costly function that should be used for debug only.\r
+ It leaves interrupts disabled for a LONG time. */\r
+\r
+ taskENTER_CRITICAL();\r
+ {\r
+ /* Run through all the lists that could potentially contain a TCB and\r
+ report the task name, state and stack high water mark. */\r
+\r
+ pcWriteBuffer[ 0 ] = ( signed portCHAR ) 0x00;\r
+ strcat( ( portCHAR * ) pcWriteBuffer, ( const portCHAR * ) "\r\n" );\r
+\r
+ uxQueue = uxTopUsedPriority + 1;\r
+\r
+ do\r
+ {\r
+ uxQueue--;\r
+\r
+ if( !listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxQueue ] ) ) )\r
+ {\r
+ prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) &( pxReadyTasksLists[ uxQueue ] ), tskREADY_CHAR ); \r
+ }\r
+ }while( uxQueue > ( unsigned portSHORT ) tskIDLE_PRIORITY );\r
+\r
+ if( !listLIST_IS_EMPTY( pxDelayedTaskList ) )\r
+ {\r
+ prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) pxDelayedTaskList, tskBLOCKED_CHAR );\r
+ }\r
+\r
+ if( !listLIST_IS_EMPTY( pxOverflowDelayedTaskList ) )\r
+ {\r
+ prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) pxOverflowDelayedTaskList, tskBLOCKED_CHAR );\r
+ }\r
+\r
+ if( !listLIST_IS_EMPTY( &xTasksWaitingTermination ) )\r
+ {\r
+ prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) &xTasksWaitingTermination, tskDELETED_CHAR );\r
+ }\r
+\r
+ if( !listLIST_IS_EMPTY( &xSuspendedTaskList ) )\r
+ {\r
+ prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) &xSuspendedTaskList, tskSUSPENDED_CHAR );\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+ }\r
+\r
+#endif\r
+/*----------------------------------------------------------*/\r
+\r
+#if ( configUSE_TRACE_FACILITY == 1 )\r
+\r
+ void vTaskStartTrace( signed portCHAR * pcBuffer, unsigned portLONG ulBufferSize )\r
+ {\r
+ portENTER_CRITICAL();\r
+ {\r
+ pcTraceBuffer = ( volatile signed portCHAR * volatile )pcBuffer;\r
+ pcTraceBufferStart = pcBuffer;\r
+ pcTraceBufferEnd = pcBuffer + ( ulBufferSize - tskSIZE_OF_EACH_TRACE_LINE );\r
+ xTracing = pdTRUE;\r
+ }\r
+ portEXIT_CRITICAL();\r
+ }\r
+\r
+#endif\r
+/*----------------------------------------------------------*/\r
+\r
+#if ( configUSE_TRACE_FACILITY == 1 )\r
+\r
+ unsigned portLONG ulTaskEndTrace( void )\r
+ {\r
+ unsigned portLONG ulBufferLength;\r
+\r
+ portENTER_CRITICAL();\r
+ xTracing = pdFALSE;\r
+ portEXIT_CRITICAL();\r
+\r
+ ulBufferLength = ( unsigned portLONG ) ( pcTraceBuffer - pcTraceBufferStart );\r
+\r
+ return ulBufferLength;\r
+ }\r
+\r
+#endif\r
+\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ * SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES\r
+ * documented in task.h\r
+ *----------------------------------------------------------*/\r
+\r
+\r
+inline void vTaskIncrementTick( void )\r
+{\r
+ /* Called by the portable layer each time a tick interrupt occurs.\r
+ Increments the tick then checks to see if the new tick value will cause any\r
+ tasks to be unblocked. */\r
+ if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE )\r
+ {\r
+ ++xTickCount;\r
+ if( xTickCount == ( portTickType ) 0 )\r
+ {\r
+ xList *pxTemp;\r
+\r
+ /* Tick count has overflowed so we need to swap the delay lists. If there are\r
+ any items in pxDelayedTaskList here then there is an error! */\r
+ pxTemp = pxDelayedTaskList;\r
+ pxDelayedTaskList = pxOverflowDelayedTaskList;\r
+ pxOverflowDelayedTaskList = pxTemp;\r
+ }\r
+\r
+ /* See if this tick has made a timeout expire. */\r
+ prvCheckDelayedTasks();\r
+ }\r
+ else\r
+ {\r
+ ++uxMissedTicks;\r
+ }\r
+\r
+ #if ( configUSE_TICK_HOOK == 1 )\r
+ {\r
+ extern void vApplicationTickHook( void );\r
+\r
+ vApplicationTickHook();\r
+ }\r
+ #endif\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( ( INCLUDE_vTaskCleanUpResources == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) )\r
+\r
+ void vTaskCleanUpResources( void )\r
+ {\r
+ unsigned portSHORT usQueue;\r
+ volatile tskTCB *pxTCB;\r
+\r
+ usQueue = ( unsigned portSHORT ) uxTopUsedPriority + ( unsigned portSHORT ) 1;\r
+\r
+ /* Remove any TCB's from the ready queues. */\r
+ do\r
+ {\r
+ usQueue--;\r
+\r
+ while( !listLIST_IS_EMPTY( &( pxReadyTasksLists[ usQueue ] ) ) )\r
+ {\r
+ listGET_OWNER_OF_NEXT_ENTRY( pxTCB, &( pxReadyTasksLists[ usQueue ] ) );\r
+ vListRemove( ( xListItem * ) &( pxTCB->xGenericListItem ) );\r
+\r
+ prvDeleteTCB( ( tskTCB * ) pxTCB );\r
+ }\r
+ }while( usQueue > ( unsigned portSHORT ) tskIDLE_PRIORITY );\r
+\r
+ /* Remove any TCB's from the delayed queue. */\r
+ while( !listLIST_IS_EMPTY( &xDelayedTaskList1 ) )\r
+ {\r
+ listGET_OWNER_OF_NEXT_ENTRY( pxTCB, &xDelayedTaskList1 );\r
+ vListRemove( ( xListItem * ) &( pxTCB->xGenericListItem ) );\r
+\r
+ prvDeleteTCB( ( tskTCB * ) pxTCB );\r
+ }\r
+\r
+ /* Remove any TCB's from the overflow delayed queue. */\r
+ while( !listLIST_IS_EMPTY( &xDelayedTaskList2 ) )\r
+ {\r
+ listGET_OWNER_OF_NEXT_ENTRY( pxTCB, &xDelayedTaskList2 );\r
+ vListRemove( ( xListItem * ) &( pxTCB->xGenericListItem ) );\r
+\r
+ prvDeleteTCB( ( tskTCB * ) pxTCB );\r
+ }\r
+\r
+ while( !listLIST_IS_EMPTY( &xSuspendedTaskList ) )\r
+ {\r
+ listGET_OWNER_OF_NEXT_ENTRY( pxTCB, &xSuspendedTaskList );\r
+ vListRemove( ( xListItem * ) &( pxTCB->xGenericListItem ) );\r
+\r
+ prvDeleteTCB( ( tskTCB * ) pxTCB );\r
+ } \r
+\r
+ while( !listLIST_IS_EMPTY( &xPendingReadyList ) )\r
+ {\r
+ listGET_OWNER_OF_NEXT_ENTRY( pxTCB, &xPendingReadyList );\r
+ vListRemove( ( xListItem * ) &( pxTCB->xGenericListItem ) );\r
+\r
+ prvDeleteTCB( ( tskTCB * ) pxTCB );\r
+ } \r
+ }\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+void vTaskSwitchContext( void )\r
+{\r
+ if( uxSchedulerSuspended != ( unsigned portBASE_TYPE ) pdFALSE )\r
+ {\r
+ /* The scheduler is currently suspended - do not allow a context\r
+ switch. */\r
+ xMissedYield = pdTRUE;\r
+ return;\r
+ }\r
+\r
+ /* Find the highest priority queue that contains ready tasks. */\r
+ while( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxTopReadyPriority ] ) ) )\r
+ {\r
+ --uxTopReadyPriority;\r
+ }\r
+\r
+ /* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the tasks of the\r
+ same priority get an equal share of the processor time. */\r
+ listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopReadyPriority ] ) );\r
+ vWriteTraceToBuffer();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vTaskPlaceOnEventList( xList *pxEventList, portTickType xTicksToWait )\r
+{\r
+portTickType xTimeToWake;\r
+\r
+ /* THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED OR THE\r
+ SCHEDULER SUSPENDED. */\r
+\r
+ /* Place the event list item of the TCB in the appropriate event list.\r
+ This is placed in the list in priority order so the highest priority task\r
+ is the first to be woken by the event. */\r
+ vListInsert( ( xList * ) pxEventList, ( xListItem * ) &( pxCurrentTCB->xEventListItem ) );\r
+\r
+ /* Calculate the time at which the task should be woken if the event does\r
+ not occur. This may overflow but this doesn't matter. */\r
+ xTimeToWake = xTickCount + xTicksToWait;\r
+\r
+ /* We must remove ourselves from the ready list before adding ourselves\r
+ to the blocked list as the same list item is used for both lists. We have\r
+ exclusive access to the ready lists as the scheduler is locked. */\r
+ vListRemove( ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) );\r
+\r
+ listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xGenericListItem ), xTimeToWake );\r
+\r
+ if( xTimeToWake < xTickCount )\r
+ {\r
+ /* Wake time has overflowed. Place this item in the overflow list. */\r
+ vListInsert( ( xList * ) pxOverflowDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) );\r
+ }\r
+ else\r
+ {\r
+ /* The wake time has not overflowed, so we can use the current block list. */\r
+ vListInsert( ( xList * ) pxDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xTaskRemoveFromEventList( const xList *pxEventList )\r
+{\r
+tskTCB *pxUnblockedTCB;\r
+portBASE_TYPE xReturn;\r
+\r
+ /* THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED OR THE\r
+ SCHEDULER SUSPENDED. It can also be called from within an ISR. */\r
+\r
+ /* The event list is sorted in priority order, so we can remove the\r
+ first in the list, remove the TCB from the delayed list, and add\r
+ it to the ready list.\r
+ \r
+ If an event is for a queue that is locked then this function will never\r
+ get called - the lock count on the queue will get modified instead. This\r
+ means we can always expect exclusive access to the event list here. */\r
+ pxUnblockedTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList );\r
+ vListRemove( &( pxUnblockedTCB->xEventListItem ) );\r
+\r
+ if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE )\r
+ {\r
+ vListRemove( &( pxUnblockedTCB->xGenericListItem ) );\r
+ prvAddTaskToReadyQueue( pxUnblockedTCB );\r
+ }\r
+ else\r
+ {\r
+ /* We cannot access the delayed or ready lists, so will hold this\r
+ task pending until the scheduler is resumed. */\r
+ vListInsertEnd( ( xList * ) &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );\r
+ }\r
+\r
+ if( pxUnblockedTCB->uxPriority >= pxCurrentTCB->uxPriority )\r
+ {\r
+ /* Return true if the task removed from the event list has\r
+ a higher priority than the calling task. This allows\r
+ the calling task to know if it should force a context\r
+ switch now. */\r
+ xReturn = pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ xReturn = pdFALSE;\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+\r
+\r
+\r
+\r
+\r
+/*\r
+ * -----------------------------------------------------------\r
+ * The Idle task.\r
+ * ----------------------------------------------------------\r
+ *\r
+ * The portTASK_FUNCTION() macro is used to allow port/compiler specific\r
+ * language extensions. The equivalent prototype for this function is:\r
+ *\r
+ * void prvIdleTask( void *pvParameters );\r
+ *\r
+ */\r
+static portTASK_FUNCTION( prvIdleTask, pvParameters )\r
+{\r
+ /* Stop warnings. */\r
+ ( void ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ /* See if any tasks have been deleted. */\r
+ prvCheckTasksWaitingTermination();\r
+\r
+ #if ( configUSE_PREEMPTION == 0 )\r
+ {\r
+ /* If we are not using preemption we keep forcing a task switch to\r
+ see if any other task has become available. If we are using\r
+ preemption we don't need to do this as any task becoming available\r
+ will automatically get the processor anyway. */\r
+ taskYIELD(); \r
+ }\r
+ #endif\r
+\r
+ #if ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) )\r
+ {\r
+ /* When using preemption tasks of equal priority will be\r
+ timesliced. If a task that is sharing the idle priority is ready\r
+ to run then the idle task should yield before the end of the\r
+ timeslice.\r
+ \r
+ A critical region is not required here as we are just reading from\r
+ the list, and an occasional incorrect value will not matter. If\r
+ the ready list at the idle priority contains more than one task\r
+ then a task other than the idle task is ready to execute. */\r
+ if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( unsigned portBASE_TYPE ) 1 )\r
+ {\r
+ taskYIELD();\r
+ }\r
+ }\r
+ #endif\r
+\r
+ #if ( configUSE_IDLE_HOOK == 1 )\r
+ {\r
+ extern void vApplicationIdleHook( void );\r
+\r
+ /* Call the user defined function from within the idle task. This\r
+ allows the application designer to add background functionality\r
+ without the overhead of a separate task.\r
+ NOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES,\r
+ CALL A FUNCTION THAT MIGHT BLOCK. */\r
+ vApplicationIdleHook();\r
+ }\r
+ #endif\r
+ }\r
+} /*lint !e715 pvParameters is not accessed but all task functions require the same prototype. */\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ * File private functions documented at the top of the file.\r
+ *----------------------------------------------------------*/\r
+\r
+\r
+\r
+static void prvInitialiseTCBVariables( tskTCB *pxTCB, unsigned portSHORT usStackDepth, const signed portCHAR * const pcName, unsigned portBASE_TYPE uxPriority )\r
+{\r
+ pxTCB->usStackDepth = usStackDepth;\r
+\r
+ /* Store the function name in the TCB. */\r
+ strncpy( ( char * ) pxTCB->pcTaskName, ( const char * ) pcName, ( unsigned portSHORT ) configMAX_TASK_NAME_LEN );\r
+ pxTCB->pcTaskName[ ( unsigned portSHORT ) configMAX_TASK_NAME_LEN - ( unsigned portSHORT ) 1 ] = '\0';\r
+\r
+ /* This is used as an array index so must ensure it's not too large. */\r
+ if( uxPriority >= configMAX_PRIORITIES )\r
+ {\r
+ uxPriority = configMAX_PRIORITIES - 1;\r
+ }\r
+\r
+ pxTCB->uxPriority = uxPriority;\r
+\r
+ vListInitialiseItem( &( pxTCB->xGenericListItem ) );\r
+ vListInitialiseItem( &( pxTCB->xEventListItem ) );\r
+\r
+ /* Set the pxTCB as a link back from the xListItem. This is so we can get\r
+ back to the containing TCB from a generic item in a list. */\r
+ listSET_LIST_ITEM_OWNER( &( pxTCB->xGenericListItem ), pxTCB );\r
+\r
+ /* Event lists are always in priority order. */\r
+ listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), configMAX_PRIORITIES - ( portTickType ) uxPriority );\r
+ listSET_LIST_ITEM_OWNER( &( pxTCB->xEventListItem ), pxTCB );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvInitialiseTaskLists( void )\r
+{\r
+unsigned portBASE_TYPE uxPriority;\r
+\r
+ for( uxPriority = 0; uxPriority < configMAX_PRIORITIES; uxPriority++ )\r
+ {\r
+ vListInitialise( ( xList * ) &( pxReadyTasksLists[ uxPriority ] ) );\r
+ }\r
+\r
+ vListInitialise( ( xList * ) &xDelayedTaskList1 );\r
+ vListInitialise( ( xList * ) &xDelayedTaskList2 );\r
+ vListInitialise( ( xList * ) &xPendingReadyList );\r
+\r
+ #if ( INCLUDE_vTaskDelete == 1 )\r
+ {\r
+ vListInitialise( ( xList * ) &xTasksWaitingTermination );\r
+ }\r
+ #endif\r
+\r
+ #if ( INCLUDE_vTaskSuspend == 1 )\r
+ {\r
+ vListInitialise( ( xList * ) &xSuspendedTaskList );\r
+ }\r
+ #endif\r
+\r
+ /* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList\r
+ using list2. */\r
+ pxDelayedTaskList = &xDelayedTaskList1;\r
+ pxOverflowDelayedTaskList = &xDelayedTaskList2;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCheckTasksWaitingTermination( void )\r
+{ \r
+ #if ( INCLUDE_vTaskDelete == 1 )\r
+ { \r
+ portBASE_TYPE xListIsEmpty;\r
+\r
+ /* ucTasksDeleted is used to prevent vTaskSuspendAll() being called\r
+ too often in the idle task. */\r
+ if( uxTasksDeleted > ( unsigned portBASE_TYPE ) 0 )\r
+ {\r
+ vTaskSuspendAll();\r
+ xListIsEmpty = listLIST_IS_EMPTY( &xTasksWaitingTermination ); \r
+ xTaskResumeAll();\r
+\r
+ if( !xListIsEmpty )\r
+ {\r
+ tskTCB *pxTCB;\r
+\r
+ portENTER_CRITICAL();\r
+ { \r
+ pxTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( ( ( xList * ) &xTasksWaitingTermination ) );\r
+ vListRemove( &( pxTCB->xGenericListItem ) );\r
+ --uxCurrentNumberOfTasks;\r
+ --uxTasksDeleted;\r
+ }\r
+ portEXIT_CRITICAL();\r
+\r
+ prvDeleteTCB( pxTCB );\r
+ }\r
+ }\r
+ }\r
+ #endif\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static tskTCB *prvAllocateTCBAndStack( unsigned portSHORT usStackDepth )\r
+{\r
+tskTCB *pxNewTCB;\r
+\r
+ /* Allocate space for the TCB. Where the memory comes from depends on\r
+ the implementation of the port malloc function. */\r
+ pxNewTCB = ( tskTCB * ) pvPortMalloc( sizeof( tskTCB ) );\r
+\r
+ if( pxNewTCB != NULL )\r
+ {\r
+ /* Allocate space for the stack used by the task being created.\r
+ The base of the stack memory stored in the TCB so the task can\r
+ be deleted later if required. */\r
+ pxNewTCB->pxStack = ( portSTACK_TYPE * ) pvPortMalloc( ( ( size_t )usStackDepth ) * sizeof( portSTACK_TYPE ) );\r
+\r
+ if( pxNewTCB->pxStack == NULL )\r
+ {\r
+ /* Could not allocate the stack. Delete the allocated TCB. */\r
+ vPortFree( pxNewTCB ); \r
+ pxNewTCB = NULL; \r
+ } \r
+ else\r
+ {\r
+ /* Just to help debugging. */\r
+ memset( pxNewTCB->pxStack, tskSTACK_FILL_BYTE, usStackDepth * sizeof( portSTACK_TYPE ) );\r
+ }\r
+ }\r
+\r
+ return pxNewTCB;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( configUSE_TRACE_FACILITY == 1 )\r
+\r
+ static void prvListTaskWithinSingleList( signed portCHAR *pcWriteBuffer, xList *pxList, signed portCHAR cStatus )\r
+ {\r
+ volatile tskTCB *pxNextTCB, *pxFirstTCB;\r
+ static portCHAR pcStatusString[ 50 ];\r
+ unsigned portSHORT usStackRemaining;\r
+\r
+ /* Write the details of all the TCB's in pxList into the buffer. */\r
+ listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList );\r
+ do\r
+ {\r
+ listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList );\r
+ usStackRemaining = usTaskCheckFreeStackSpace( ( unsigned portCHAR * ) pxNextTCB->pxStack );\r
+ sprintf( pcStatusString, ( portCHAR * ) "%s\t\t%c\t%u\t%u\t%u\r\n", pxNextTCB->pcTaskName, cStatus, ( unsigned int ) pxNextTCB->uxPriority, usStackRemaining, ( unsigned int ) pxNextTCB->uxTCBNumber );\r
+ strcat( ( portCHAR * ) pcWriteBuffer, ( portCHAR * ) pcStatusString );\r
+\r
+ } while( pxNextTCB != pxFirstTCB );\r
+ }\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( configUSE_TRACE_FACILITY == 1 )\r
+ unsigned portSHORT usTaskCheckFreeStackSpace( const unsigned portCHAR *pucStackByte )\r
+ {\r
+ register unsigned portSHORT usCount = 0;\r
+\r
+ while( *pucStackByte == tskSTACK_FILL_BYTE )\r
+ {\r
+ pucStackByte -= portSTACK_GROWTH;\r
+ usCount++;\r
+ }\r
+\r
+ usCount /= sizeof( portSTACK_TYPE );\r
+\r
+ return usCount;\r
+ }\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+\r
+#if ( ( INCLUDE_vTaskDelete == 1 ) || ( INCLUDE_vTaskCleanUpResources == 1 ) )\r
+\r
+ static void prvDeleteTCB( tskTCB *pxTCB )\r
+ {\r
+ /* Free up the memory allocated by the scheduler for the task. It is up to\r
+ the task to free any memory allocated at the application level. */\r
+ vPortFree( pxTCB->pxStack );\r
+ vPortFree( pxTCB );\r
+ }\r
+\r
+#endif\r
+\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( INCLUDE_xTaskGetCurrentTaskHandle == 1 )\r
+\r
+ xTaskHandle xTaskGetCurrentTaskHandle( void )\r
+ {\r
+ xTaskHandle xReturn;\r
+\r
+ portENTER_CRITICAL();\r
+ {\r
+ xReturn = ( xTaskHandle ) pxCurrentTCB;\r
+ }\r
+ portEXIT_CRITICAL();\r
+\r
+ return xReturn;\r
+ }\r
+\r
+#endif\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+Tracecon.exe is a very simplistic utility for converting the trace data captured by the scheduler into a tab delimited text file. The text file can be opened using a spread sheet program as described on www.FreeRTOS.org.\r
+\r
+Tracecon should be executed from a command prompt. It looks for a file called Trace.bin in the current directory and creates a file called trace.txt.\r
+\r
+Use the big endian version for file captured on big endian targets.\r
+\r
--- /dev/null
+The download includes the kernel source code, and a demo application for EVERY\r
+RTOS port. See http://www.freertos.org/a00017.html for full details of the \r
+directory structure and information on locating the files you require.\r
+\r
+The easiest way to use FreeRTOS is start start with one of the demo application \r
+projects. Once this is running the project can be modified to include your own\r
+source files. This way the correct files and compiler options will be \r
+automatically included in your application.\r
+\r
++ The Source directory contains the real time kernel source files for every \r
+port. The kernel itself is only 3 files.\r
+\r
++ The Demo directory contains the demo application source files for every \r
+port.\r
+\r
++ The TraceCon directory contains the trace visualisation exe file.\r
+\r
+See the readme files in the respective directories for further information.\r
+\r
projects / freertos / commitdiff
